Boot log: mt8192-asurada-spherion-r0
- Errors: 1
- Kernel Errors: 30
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 24
1 18:03:06.682232 lava-dispatcher, installed at version: 2024.03
2 18:03:06.682420 start: 0 validate
3 18:03:06.682557 Start time: 2024-06-11 18:03:06.682549+00:00 (UTC)
4 18:03:06.682676 Using caching service: 'http://localhost/cache/?uri=%s'
5 18:03:06.682800 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-v4l2%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 18:03:06.951587 Using caching service: 'http://localhost/cache/?uri=%s'
7 18:03:06.952272 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22-17-g24b63cdc814f%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 18:03:07.224047 Using caching service: 'http://localhost/cache/?uri=%s'
9 18:03:07.224764 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22-17-g24b63cdc814f%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 18:03:07.494779 Using caching service: 'http://localhost/cache/?uri=%s'
11 18:03:07.495421 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22-17-g24b63cdc814f%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 18:03:07.771728 validate duration: 1.09
14 18:03:07.773020 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 18:03:07.773620 start: 1.1 download-retry (timeout 00:10:00) [common]
16 18:03:07.774246 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 18:03:07.774859 Not decompressing ramdisk as can be used compressed.
18 18:03:07.775293 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-v4l2/20240313.0/arm64/rootfs.cpio.gz
19 18:03:07.775626 saving as /var/lib/lava/dispatcher/tmp/14291408/tftp-deploy-n4a6lwod/ramdisk/rootfs.cpio.gz
20 18:03:07.775953 total size: 28105535 (26 MB)
21 18:03:07.780710 progress 0 % (0 MB)
22 18:03:07.807665 progress 5 % (1 MB)
23 18:03:07.820287 progress 10 % (2 MB)
24 18:03:07.829573 progress 15 % (4 MB)
25 18:03:07.837772 progress 20 % (5 MB)
26 18:03:07.844954 progress 25 % (6 MB)
27 18:03:07.852100 progress 30 % (8 MB)
28 18:03:07.859216 progress 35 % (9 MB)
29 18:03:07.866419 progress 40 % (10 MB)
30 18:03:07.873569 progress 45 % (12 MB)
31 18:03:07.880683 progress 50 % (13 MB)
32 18:03:07.887819 progress 55 % (14 MB)
33 18:03:07.894869 progress 60 % (16 MB)
34 18:03:07.902034 progress 65 % (17 MB)
35 18:03:07.909124 progress 70 % (18 MB)
36 18:03:07.916225 progress 75 % (20 MB)
37 18:03:07.923342 progress 80 % (21 MB)
38 18:03:07.930482 progress 85 % (22 MB)
39 18:03:07.937300 progress 90 % (24 MB)
40 18:03:07.944236 progress 95 % (25 MB)
41 18:03:07.951195 progress 100 % (26 MB)
42 18:03:07.951400 26 MB downloaded in 0.18 s (152.75 MB/s)
43 18:03:07.951555 end: 1.1.1 http-download (duration 00:00:00) [common]
45 18:03:07.951795 end: 1.1 download-retry (duration 00:00:00) [common]
46 18:03:07.951880 start: 1.2 download-retry (timeout 00:10:00) [common]
47 18:03:07.951963 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 18:03:07.952099 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-17-g24b63cdc814f/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 18:03:07.952172 saving as /var/lib/lava/dispatcher/tmp/14291408/tftp-deploy-n4a6lwod/kernel/Image
50 18:03:07.952232 total size: 54813184 (52 MB)
51 18:03:07.952293 No compression specified
52 18:03:07.953439 progress 0 % (0 MB)
53 18:03:07.967186 progress 5 % (2 MB)
54 18:03:07.981206 progress 10 % (5 MB)
55 18:03:07.994853 progress 15 % (7 MB)
56 18:03:08.008628 progress 20 % (10 MB)
57 18:03:08.022466 progress 25 % (13 MB)
58 18:03:08.036041 progress 30 % (15 MB)
59 18:03:08.049795 progress 35 % (18 MB)
60 18:03:08.063665 progress 40 % (20 MB)
61 18:03:08.077603 progress 45 % (23 MB)
62 18:03:08.091451 progress 50 % (26 MB)
63 18:03:08.105315 progress 55 % (28 MB)
64 18:03:08.118849 progress 60 % (31 MB)
65 18:03:08.132710 progress 65 % (34 MB)
66 18:03:08.146294 progress 70 % (36 MB)
67 18:03:08.160014 progress 75 % (39 MB)
68 18:03:08.173897 progress 80 % (41 MB)
69 18:03:08.187635 progress 85 % (44 MB)
70 18:03:08.201475 progress 90 % (47 MB)
71 18:03:08.215160 progress 95 % (49 MB)
72 18:03:08.229007 progress 100 % (52 MB)
73 18:03:08.229252 52 MB downloaded in 0.28 s (188.70 MB/s)
74 18:03:08.229404 end: 1.2.1 http-download (duration 00:00:00) [common]
76 18:03:08.229641 end: 1.2 download-retry (duration 00:00:00) [common]
77 18:03:08.229726 start: 1.3 download-retry (timeout 00:10:00) [common]
78 18:03:08.229809 start: 1.3.1 http-download (timeout 00:10:00) [common]
79 18:03:08.229945 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-17-g24b63cdc814f/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 18:03:08.230019 saving as /var/lib/lava/dispatcher/tmp/14291408/tftp-deploy-n4a6lwod/dtb/mt8192-asurada-spherion-r0.dtb
81 18:03:08.230079 total size: 47258 (0 MB)
82 18:03:08.230139 No compression specified
83 18:03:08.231289 progress 69 % (0 MB)
84 18:03:08.231568 progress 100 % (0 MB)
85 18:03:08.231725 0 MB downloaded in 0.00 s (27.42 MB/s)
86 18:03:08.231848 end: 1.3.1 http-download (duration 00:00:00) [common]
88 18:03:08.232083 end: 1.3 download-retry (duration 00:00:00) [common]
89 18:03:08.232172 start: 1.4 download-retry (timeout 00:10:00) [common]
90 18:03:08.232291 start: 1.4.1 http-download (timeout 00:10:00) [common]
91 18:03:08.232411 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-17-g24b63cdc814f/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 18:03:08.232480 saving as /var/lib/lava/dispatcher/tmp/14291408/tftp-deploy-n4a6lwod/modules/modules.tar
93 18:03:08.232540 total size: 8618176 (8 MB)
94 18:03:08.232602 Using unxz to decompress xz
95 18:03:08.236499 progress 0 % (0 MB)
96 18:03:08.255329 progress 5 % (0 MB)
97 18:03:08.284438 progress 10 % (0 MB)
98 18:03:08.314239 progress 15 % (1 MB)
99 18:03:08.338829 progress 20 % (1 MB)
100 18:03:08.362572 progress 25 % (2 MB)
101 18:03:08.386498 progress 30 % (2 MB)
102 18:03:08.412960 progress 35 % (2 MB)
103 18:03:08.438147 progress 40 % (3 MB)
104 18:03:08.460736 progress 45 % (3 MB)
105 18:03:08.485529 progress 50 % (4 MB)
106 18:03:08.510810 progress 55 % (4 MB)
107 18:03:08.535402 progress 60 % (4 MB)
108 18:03:08.560251 progress 65 % (5 MB)
109 18:03:08.587528 progress 70 % (5 MB)
110 18:03:08.611595 progress 75 % (6 MB)
111 18:03:08.637465 progress 80 % (6 MB)
112 18:03:08.662165 progress 85 % (7 MB)
113 18:03:08.687935 progress 90 % (7 MB)
114 18:03:08.713287 progress 95 % (7 MB)
115 18:03:08.740108 progress 100 % (8 MB)
116 18:03:08.744506 8 MB downloaded in 0.51 s (16.05 MB/s)
117 18:03:08.744735 end: 1.4.1 http-download (duration 00:00:01) [common]
119 18:03:08.745130 end: 1.4 download-retry (duration 00:00:01) [common]
120 18:03:08.745236 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 18:03:08.745342 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 18:03:08.745461 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 18:03:08.745583 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 18:03:08.745856 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14291408/lava-overlay-asg5wvju
125 18:03:08.746023 makedir: /var/lib/lava/dispatcher/tmp/14291408/lava-overlay-asg5wvju/lava-14291408/bin
126 18:03:08.746159 makedir: /var/lib/lava/dispatcher/tmp/14291408/lava-overlay-asg5wvju/lava-14291408/tests
127 18:03:08.746286 makedir: /var/lib/lava/dispatcher/tmp/14291408/lava-overlay-asg5wvju/lava-14291408/results
128 18:03:08.746426 Creating /var/lib/lava/dispatcher/tmp/14291408/lava-overlay-asg5wvju/lava-14291408/bin/lava-add-keys
129 18:03:08.746600 Creating /var/lib/lava/dispatcher/tmp/14291408/lava-overlay-asg5wvju/lava-14291408/bin/lava-add-sources
130 18:03:08.746731 Creating /var/lib/lava/dispatcher/tmp/14291408/lava-overlay-asg5wvju/lava-14291408/bin/lava-background-process-start
131 18:03:08.746860 Creating /var/lib/lava/dispatcher/tmp/14291408/lava-overlay-asg5wvju/lava-14291408/bin/lava-background-process-stop
132 18:03:08.746985 Creating /var/lib/lava/dispatcher/tmp/14291408/lava-overlay-asg5wvju/lava-14291408/bin/lava-common-functions
133 18:03:08.747107 Creating /var/lib/lava/dispatcher/tmp/14291408/lava-overlay-asg5wvju/lava-14291408/bin/lava-echo-ipv4
134 18:03:08.747228 Creating /var/lib/lava/dispatcher/tmp/14291408/lava-overlay-asg5wvju/lava-14291408/bin/lava-install-packages
135 18:03:08.747350 Creating /var/lib/lava/dispatcher/tmp/14291408/lava-overlay-asg5wvju/lava-14291408/bin/lava-installed-packages
136 18:03:08.747471 Creating /var/lib/lava/dispatcher/tmp/14291408/lava-overlay-asg5wvju/lava-14291408/bin/lava-os-build
137 18:03:08.747599 Creating /var/lib/lava/dispatcher/tmp/14291408/lava-overlay-asg5wvju/lava-14291408/bin/lava-probe-channel
138 18:03:08.747725 Creating /var/lib/lava/dispatcher/tmp/14291408/lava-overlay-asg5wvju/lava-14291408/bin/lava-probe-ip
139 18:03:08.747854 Creating /var/lib/lava/dispatcher/tmp/14291408/lava-overlay-asg5wvju/lava-14291408/bin/lava-target-ip
140 18:03:08.748011 Creating /var/lib/lava/dispatcher/tmp/14291408/lava-overlay-asg5wvju/lava-14291408/bin/lava-target-mac
141 18:03:08.748212 Creating /var/lib/lava/dispatcher/tmp/14291408/lava-overlay-asg5wvju/lava-14291408/bin/lava-target-storage
142 18:03:08.748376 Creating /var/lib/lava/dispatcher/tmp/14291408/lava-overlay-asg5wvju/lava-14291408/bin/lava-test-case
143 18:03:08.748532 Creating /var/lib/lava/dispatcher/tmp/14291408/lava-overlay-asg5wvju/lava-14291408/bin/lava-test-event
144 18:03:08.748698 Creating /var/lib/lava/dispatcher/tmp/14291408/lava-overlay-asg5wvju/lava-14291408/bin/lava-test-feedback
145 18:03:08.748870 Creating /var/lib/lava/dispatcher/tmp/14291408/lava-overlay-asg5wvju/lava-14291408/bin/lava-test-raise
146 18:03:08.749073 Creating /var/lib/lava/dispatcher/tmp/14291408/lava-overlay-asg5wvju/lava-14291408/bin/lava-test-reference
147 18:03:08.749240 Creating /var/lib/lava/dispatcher/tmp/14291408/lava-overlay-asg5wvju/lava-14291408/bin/lava-test-runner
148 18:03:08.749406 Creating /var/lib/lava/dispatcher/tmp/14291408/lava-overlay-asg5wvju/lava-14291408/bin/lava-test-set
149 18:03:08.749571 Creating /var/lib/lava/dispatcher/tmp/14291408/lava-overlay-asg5wvju/lava-14291408/bin/lava-test-shell
150 18:03:08.749712 Updating /var/lib/lava/dispatcher/tmp/14291408/lava-overlay-asg5wvju/lava-14291408/bin/lava-install-packages (oe)
151 18:03:08.749876 Updating /var/lib/lava/dispatcher/tmp/14291408/lava-overlay-asg5wvju/lava-14291408/bin/lava-installed-packages (oe)
152 18:03:08.750012 Creating /var/lib/lava/dispatcher/tmp/14291408/lava-overlay-asg5wvju/lava-14291408/environment
153 18:03:08.750147 LAVA metadata
154 18:03:08.750254 - LAVA_JOB_ID=14291408
155 18:03:08.750357 - LAVA_DISPATCHER_IP=192.168.201.1
156 18:03:08.750506 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 18:03:08.750605 skipped lava-vland-overlay
158 18:03:08.750709 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 18:03:08.750822 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 18:03:08.750922 skipped lava-multinode-overlay
161 18:03:08.751024 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 18:03:08.751145 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 18:03:08.751248 Loading test definitions
164 18:03:08.751371 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 18:03:08.751472 Using /lava-14291408 at stage 0
166 18:03:08.751880 uuid=14291408_1.5.2.3.1 testdef=None
167 18:03:08.751997 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 18:03:08.752110 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 18:03:08.752810 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 18:03:08.753164 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 18:03:08.754024 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 18:03:08.754375 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 18:03:08.755020 runner path: /var/lib/lava/dispatcher/tmp/14291408/lava-overlay-asg5wvju/lava-14291408/0/tests/0_v4l2-compliance-uvc test_uuid 14291408_1.5.2.3.1
176 18:03:08.755212 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 18:03:08.755455 Creating lava-test-runner.conf files
179 18:03:08.755526 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14291408/lava-overlay-asg5wvju/lava-14291408/0 for stage 0
180 18:03:08.755647 - 0_v4l2-compliance-uvc
181 18:03:08.755774 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 18:03:08.755887 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 18:03:08.763245 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 18:03:08.763356 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 18:03:08.763442 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 18:03:08.763526 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 18:03:08.763609 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 18:03:09.652755 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 18:03:09.653170 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 18:03:09.653287 extracting modules file /var/lib/lava/dispatcher/tmp/14291408/tftp-deploy-n4a6lwod/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14291408/extract-overlay-ramdisk-qy_q8zwl/ramdisk
191 18:03:09.873865 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 18:03:09.874042 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
193 18:03:09.874137 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14291408/compress-overlay-m78ezfg7/overlay-1.5.2.4.tar.gz to ramdisk
194 18:03:09.874207 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14291408/compress-overlay-m78ezfg7/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14291408/extract-overlay-ramdisk-qy_q8zwl/ramdisk
195 18:03:09.880932 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 18:03:09.881143 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
197 18:03:09.881237 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 18:03:09.881325 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
199 18:03:09.881404 Building ramdisk /var/lib/lava/dispatcher/tmp/14291408/extract-overlay-ramdisk-qy_q8zwl/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14291408/extract-overlay-ramdisk-qy_q8zwl/ramdisk
200 18:03:10.519023 >> 275946 blocks
201 18:03:14.552685 rename /var/lib/lava/dispatcher/tmp/14291408/extract-overlay-ramdisk-qy_q8zwl/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14291408/tftp-deploy-n4a6lwod/ramdisk/ramdisk.cpio.gz
202 18:03:14.553161 end: 1.5.7 compress-ramdisk (duration 00:00:05) [common]
203 18:03:14.553292 start: 1.5.8 prepare-kernel (timeout 00:09:53) [common]
204 18:03:14.553392 start: 1.5.8.1 prepare-fit (timeout 00:09:53) [common]
205 18:03:14.553499 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14291408/tftp-deploy-n4a6lwod/kernel/Image']
206 18:03:28.823216 Returned 0 in 14 seconds
207 18:03:28.924183 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14291408/tftp-deploy-n4a6lwod/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14291408/tftp-deploy-n4a6lwod/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14291408/tftp-deploy-n4a6lwod/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14291408/tftp-deploy-n4a6lwod/kernel/image.itb
208 18:03:29.532232 output: FIT description: Kernel Image image with one or more FDT blobs
209 18:03:29.532584 output: Created: Tue Jun 11 19:03:29 2024
210 18:03:29.532662 output: Image 0 (kernel-1)
211 18:03:29.532726 output: Description:
212 18:03:29.532786 output: Created: Tue Jun 11 19:03:29 2024
213 18:03:29.532846 output: Type: Kernel Image
214 18:03:29.532908 output: Compression: lzma compressed
215 18:03:29.532968 output: Data Size: 13125101 Bytes = 12817.48 KiB = 12.52 MiB
216 18:03:29.533075 output: Architecture: AArch64
217 18:03:29.533135 output: OS: Linux
218 18:03:29.533193 output: Load Address: 0x00000000
219 18:03:29.533253 output: Entry Point: 0x00000000
220 18:03:29.533310 output: Hash algo: crc32
221 18:03:29.533367 output: Hash value: 7a9e9d3e
222 18:03:29.533422 output: Image 1 (fdt-1)
223 18:03:29.533475 output: Description: mt8192-asurada-spherion-r0
224 18:03:29.533530 output: Created: Tue Jun 11 19:03:29 2024
225 18:03:29.533584 output: Type: Flat Device Tree
226 18:03:29.533637 output: Compression: uncompressed
227 18:03:29.533690 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
228 18:03:29.533742 output: Architecture: AArch64
229 18:03:29.533794 output: Hash algo: crc32
230 18:03:29.533846 output: Hash value: 0f8e4d2e
231 18:03:29.533939 output: Image 2 (ramdisk-1)
232 18:03:29.534042 output: Description: unavailable
233 18:03:29.534102 output: Created: Tue Jun 11 19:03:29 2024
234 18:03:29.534156 output: Type: RAMDisk Image
235 18:03:29.534209 output: Compression: Unknown Compression
236 18:03:29.534262 output: Data Size: 41216624 Bytes = 40250.61 KiB = 39.31 MiB
237 18:03:29.534316 output: Architecture: AArch64
238 18:03:29.534368 output: OS: Linux
239 18:03:29.534421 output: Load Address: unavailable
240 18:03:29.534473 output: Entry Point: unavailable
241 18:03:29.534526 output: Hash algo: crc32
242 18:03:29.534577 output: Hash value: 3c322242
243 18:03:29.534629 output: Default Configuration: 'conf-1'
244 18:03:29.534681 output: Configuration 0 (conf-1)
245 18:03:29.534733 output: Description: mt8192-asurada-spherion-r0
246 18:03:29.534785 output: Kernel: kernel-1
247 18:03:29.534837 output: Init Ramdisk: ramdisk-1
248 18:03:29.534889 output: FDT: fdt-1
249 18:03:29.534941 output: Loadables: kernel-1
250 18:03:29.534993 output:
251 18:03:29.535196 end: 1.5.8.1 prepare-fit (duration 00:00:15) [common]
252 18:03:29.535295 end: 1.5.8 prepare-kernel (duration 00:00:15) [common]
253 18:03:29.535396 end: 1.5 prepare-tftp-overlay (duration 00:00:21) [common]
254 18:03:29.535494 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:38) [common]
255 18:03:29.535574 No LXC device requested
256 18:03:29.535655 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 18:03:29.535740 start: 1.7 deploy-device-env (timeout 00:09:38) [common]
258 18:03:29.535818 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 18:03:29.535888 Checking files for TFTP limit of 4294967296 bytes.
260 18:03:29.536385 end: 1 tftp-deploy (duration 00:00:22) [common]
261 18:03:29.536495 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 18:03:29.536587 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 18:03:29.536709 substitutions:
264 18:03:29.536776 - {DTB}: 14291408/tftp-deploy-n4a6lwod/dtb/mt8192-asurada-spherion-r0.dtb
265 18:03:29.536839 - {INITRD}: 14291408/tftp-deploy-n4a6lwod/ramdisk/ramdisk.cpio.gz
266 18:03:29.536898 - {KERNEL}: 14291408/tftp-deploy-n4a6lwod/kernel/Image
267 18:03:29.536957 - {LAVA_MAC}: None
268 18:03:29.537064 - {PRESEED_CONFIG}: None
269 18:03:29.537121 - {PRESEED_LOCAL}: None
270 18:03:29.537176 - {RAMDISK}: 14291408/tftp-deploy-n4a6lwod/ramdisk/ramdisk.cpio.gz
271 18:03:29.537232 - {ROOT_PART}: None
272 18:03:29.537287 - {ROOT}: None
273 18:03:29.537341 - {SERVER_IP}: 192.168.201.1
274 18:03:29.537395 - {TEE}: None
275 18:03:29.537449 Parsed boot commands:
276 18:03:29.537502 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 18:03:29.537675 Parsed boot commands: tftpboot 192.168.201.1 14291408/tftp-deploy-n4a6lwod/kernel/image.itb 14291408/tftp-deploy-n4a6lwod/kernel/cmdline
278 18:03:29.537765 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 18:03:29.537849 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 18:03:29.537943 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 18:03:29.538030 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 18:03:29.538100 Not connected, no need to disconnect.
283 18:03:29.538174 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 18:03:29.538252 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 18:03:29.538320 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-3'
286 18:03:29.541897 Setting prompt string to ['lava-test: # ']
287 18:03:29.542262 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 18:03:29.542372 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 18:03:29.542474 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 18:03:29.542569 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 18:03:29.542765 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-3', '--port=1', '--command=reboot']
292 18:03:34.679119 >> Command sent successfully.
293 18:03:34.681513 Returned 0 in 5 seconds
294 18:03:34.781863 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 18:03:34.782188 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 18:03:34.782289 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 18:03:34.782377 Setting prompt string to 'Starting depthcharge on Spherion...'
299 18:03:34.782444 Changing prompt to 'Starting depthcharge on Spherion...'
300 18:03:34.782510 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 18:03:34.782893 [Enter `^Ec?' for help]
302 18:03:34.956245
303 18:03:34.956391
304 18:03:34.956463 F0: 102B 0000
305 18:03:34.956528
306 18:03:34.956590 F3: 1001 0000 [0200]
307 18:03:34.956649
308 18:03:34.959628 F3: 1001 0000
309 18:03:34.959714
310 18:03:34.959780 F7: 102D 0000
311 18:03:34.959843
312 18:03:34.962806 F1: 0000 0000
313 18:03:34.962890
314 18:03:34.962955 V0: 0000 0000 [0001]
315 18:03:34.963016
316 18:03:34.963075 00: 0007 8000
317 18:03:34.966152
318 18:03:34.966234 01: 0000 0000
319 18:03:34.966300
320 18:03:34.966362 BP: 0C00 0209 [0000]
321 18:03:34.966420
322 18:03:34.969693 G0: 1182 0000
323 18:03:34.969776
324 18:03:34.969841 EC: 0000 0021 [4000]
325 18:03:34.969902
326 18:03:34.973018 S7: 0000 0000 [0000]
327 18:03:34.973114
328 18:03:34.973180 CC: 0000 0000 [0001]
329 18:03:34.976584
330 18:03:34.976666 T0: 0000 0040 [010F]
331 18:03:34.976732
332 18:03:34.976793 Jump to BL
333 18:03:34.976851
334 18:03:35.003189
335 18:03:35.003282
336 18:03:35.010275 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
337 18:03:35.013869 ARM64: Exception handlers installed.
338 18:03:35.017847 ARM64: Testing exception
339 18:03:35.020724 ARM64: Done test exception
340 18:03:35.027818 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
341 18:03:35.037564 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
342 18:03:35.044230 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
343 18:03:35.054729 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
344 18:03:35.061259 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
345 18:03:35.068159 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
346 18:03:35.079605 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
347 18:03:35.086501 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
348 18:03:35.105541 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
349 18:03:35.108944 WDT: Last reset was cold boot
350 18:03:35.112519 SPI1(PAD0) initialized at 2873684 Hz
351 18:03:35.115448 SPI5(PAD0) initialized at 992727 Hz
352 18:03:35.118952 VBOOT: Loading verstage.
353 18:03:35.125671 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
354 18:03:35.129192 FMAP: Found "FLASH" version 1.1 at 0x20000.
355 18:03:35.132054 FMAP: base = 0x0 size = 0x800000 #areas = 25
356 18:03:35.135662 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
357 18:03:35.143256 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
358 18:03:35.149389 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
359 18:03:35.160496 read SPI 0x96554 0xa1eb: 4594 us, 9022 KB/s, 72.176 Mbps
360 18:03:35.160580
361 18:03:35.160645
362 18:03:35.170747 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
363 18:03:35.173743 ARM64: Exception handlers installed.
364 18:03:35.177554 ARM64: Testing exception
365 18:03:35.177636 ARM64: Done test exception
366 18:03:35.183806 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
367 18:03:35.187162 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
368 18:03:35.202487 Probing TPM: . done!
369 18:03:35.202570 TPM ready after 0 ms
370 18:03:35.209926 Connected to device vid:did:rid of 1ae0:0028:00
371 18:03:35.216388 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
372 18:03:35.276225 Initialized TPM device CR50 revision 0
373 18:03:35.285487 tlcl_send_startup: Startup return code is 0
374 18:03:35.285576 TPM: setup succeeded
375 18:03:35.296967 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
376 18:03:35.305601 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
377 18:03:35.318501 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
378 18:03:35.328398 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
379 18:03:35.331695 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
380 18:03:35.337013 in-header: 03 07 00 00 08 00 00 00
381 18:03:35.340436 in-data: aa e4 47 04 13 02 00 00
382 18:03:35.344053 Chrome EC: UHEPI supported
383 18:03:35.351266 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
384 18:03:35.355450 in-header: 03 ad 00 00 08 00 00 00
385 18:03:35.359035 in-data: 00 20 20 08 00 00 00 00
386 18:03:35.359131 Phase 1
387 18:03:35.362326 FMAP: area GBB found @ 3f5000 (12032 bytes)
388 18:03:35.369780 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
389 18:03:35.373649 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
390 18:03:35.376811 Recovery requested (1009000e)
391 18:03:35.385486 TPM: Extending digest for VBOOT: boot mode into PCR 0
392 18:03:35.390820 tlcl_extend: response is 0
393 18:03:35.399913 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
394 18:03:35.405700 tlcl_extend: response is 0
395 18:03:35.412823 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
396 18:03:35.432563 read SPI 0x210d4 0x2173b: 15146 us, 9046 KB/s, 72.368 Mbps
397 18:03:35.439412 BS: bootblock times (exec / console): total (unknown) / 148 ms
398 18:03:35.439496
399 18:03:35.439562
400 18:03:35.450055 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
401 18:03:35.453584 ARM64: Exception handlers installed.
402 18:03:35.453666 ARM64: Testing exception
403 18:03:35.456526 ARM64: Done test exception
404 18:03:35.477937 pmic_efuse_setting: Set efuses in 11 msecs
405 18:03:35.481315 pmwrap_interface_init: Select PMIF_VLD_RDY
406 18:03:35.488199 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
407 18:03:35.491617 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
408 18:03:35.498120 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
409 18:03:35.502183 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
410 18:03:35.506026 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
411 18:03:35.513334 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
412 18:03:35.516620 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
413 18:03:35.520384 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
414 18:03:35.524362 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
415 18:03:35.531858 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
416 18:03:35.535487 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
417 18:03:35.539022 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
418 18:03:35.542506 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
419 18:03:35.550639 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
420 18:03:35.557818 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
421 18:03:35.561435 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
422 18:03:35.568616 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
423 18:03:35.572422 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
424 18:03:35.580009 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
425 18:03:35.583525 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
426 18:03:35.590278 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
427 18:03:35.594400 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
428 18:03:35.601915 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
429 18:03:35.605222 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
430 18:03:35.612822 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
431 18:03:35.616595 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
432 18:03:35.623675 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
433 18:03:35.627279 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
434 18:03:35.631296 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
435 18:03:35.634984 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
436 18:03:35.642639 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
437 18:03:35.646131 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
438 18:03:35.653633 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
439 18:03:35.657125 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
440 18:03:35.661155 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
441 18:03:35.668415 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
442 18:03:35.671907 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
443 18:03:35.675366 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
444 18:03:35.682942 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
445 18:03:35.686446 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
446 18:03:35.690051 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
447 18:03:35.693364 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
448 18:03:35.697063 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
449 18:03:35.704783 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
450 18:03:35.708491 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
451 18:03:35.712659 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
452 18:03:35.715905 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
453 18:03:35.719960 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
454 18:03:35.723575 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
455 18:03:35.727515 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
456 18:03:35.734328 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
457 18:03:35.742430 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
458 18:03:35.749894 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
459 18:03:35.753181 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
460 18:03:35.760802 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
461 18:03:35.771996 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
462 18:03:35.775535 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
463 18:03:35.779628 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
464 18:03:35.783017 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 18:03:35.790526 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x34
466 18:03:35.798340 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
467 18:03:35.801787 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
468 18:03:35.804837 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
469 18:03:35.815391 [RTC]rtc_get_frequency_meter,154: input=15, output=789
470 18:03:35.824929 [RTC]rtc_get_frequency_meter,154: input=23, output=978
471 18:03:35.834334 [RTC]rtc_get_frequency_meter,154: input=19, output=883
472 18:03:35.844010 [RTC]rtc_get_frequency_meter,154: input=17, output=837
473 18:03:35.853750 [RTC]rtc_get_frequency_meter,154: input=16, output=812
474 18:03:35.863046 [RTC]rtc_get_frequency_meter,154: input=15, output=789
475 18:03:35.872518 [RTC]rtc_get_frequency_meter,154: input=16, output=814
476 18:03:35.876170 [RTC]rtc_eosc_cali,47: left: 15, middle: 15, right: 16
477 18:03:35.883435 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
478 18:03:35.887384 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
479 18:03:35.891053 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
480 18:03:35.894560 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
481 18:03:35.898019 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
482 18:03:35.902132 ADC[4]: Raw value=902436 ID=7
483 18:03:35.905669 ADC[3]: Raw value=213336 ID=1
484 18:03:35.905753 RAM Code: 0x71
485 18:03:35.909797 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
486 18:03:35.913317 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
487 18:03:35.924632 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
488 18:03:35.928174 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
489 18:03:35.931638 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
490 18:03:35.937467 in-header: 03 07 00 00 08 00 00 00
491 18:03:35.941184 in-data: aa e4 47 04 13 02 00 00
492 18:03:35.944868 Chrome EC: UHEPI supported
493 18:03:35.952322 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
494 18:03:35.956630 in-header: 03 ed 00 00 08 00 00 00
495 18:03:35.956713 in-data: 80 20 60 08 00 00 00 00
496 18:03:35.960163 MRC: failed to locate region type 0.
497 18:03:35.967687 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
498 18:03:35.971701 DRAM-K: Running full calibration
499 18:03:35.975382 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
500 18:03:35.979237 header.status = 0x0
501 18:03:35.982631 header.version = 0x6 (expected: 0x6)
502 18:03:35.986081 header.size = 0xd00 (expected: 0xd00)
503 18:03:35.986164 header.flags = 0x0
504 18:03:35.993386 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
505 18:03:36.011067 read SPI 0x72590 0x1c583: 12503 us, 9285 KB/s, 74.280 Mbps
506 18:03:36.018711 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
507 18:03:36.018795 dram_init: ddr_geometry: 2
508 18:03:36.022203 [EMI] MDL number = 2
509 18:03:36.025861 [EMI] Get MDL freq = 0
510 18:03:36.025943 dram_init: ddr_type: 0
511 18:03:36.030043 is_discrete_lpddr4: 1
512 18:03:36.033126 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
513 18:03:36.033209
514 18:03:36.033275
515 18:03:36.033337 [Bian_co] ETT version 0.0.0.1
516 18:03:36.040631 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
517 18:03:36.040714
518 18:03:36.043988 dramc_set_vcore_voltage set vcore to 650000
519 18:03:36.044071 Read voltage for 800, 4
520 18:03:36.047111 Vio18 = 0
521 18:03:36.047194 Vcore = 650000
522 18:03:36.047259 Vdram = 0
523 18:03:36.050419 Vddq = 0
524 18:03:36.050501 Vmddr = 0
525 18:03:36.054078 dram_init: config_dvfs: 1
526 18:03:36.057185 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
527 18:03:36.063809 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
528 18:03:36.067211 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=10
529 18:03:36.070446 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=10
530 18:03:36.073930 [SwImpedanceCal] DRVP=12, DRVN=25, ODTN=9
531 18:03:36.077467 freq_region=1, Reg: DRVP=12, DRVN=25, ODTN=9
532 18:03:36.080618 MEM_TYPE=3, freq_sel=18
533 18:03:36.084440 sv_algorithm_assistance_LP4_1600
534 18:03:36.087285 ============ PULL DRAM RESETB DOWN ============
535 18:03:36.090735 ========== PULL DRAM RESETB DOWN end =========
536 18:03:36.097699 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
537 18:03:36.101215 ===================================
538 18:03:36.101298 LPDDR4 DRAM CONFIGURATION
539 18:03:36.104144 ===================================
540 18:03:36.107686 EX_ROW_EN[0] = 0x0
541 18:03:36.111165 EX_ROW_EN[1] = 0x0
542 18:03:36.111247 LP4Y_EN = 0x0
543 18:03:36.114144 WORK_FSP = 0x0
544 18:03:36.114226 WL = 0x2
545 18:03:36.117662 RL = 0x2
546 18:03:36.117745 BL = 0x2
547 18:03:36.121172 RPST = 0x0
548 18:03:36.121254 RD_PRE = 0x0
549 18:03:36.124264 WR_PRE = 0x1
550 18:03:36.124346 WR_PST = 0x0
551 18:03:36.127610 DBI_WR = 0x0
552 18:03:36.127693 DBI_RD = 0x0
553 18:03:36.131239 OTF = 0x1
554 18:03:36.134947 ===================================
555 18:03:36.137714 ===================================
556 18:03:36.137798 ANA top config
557 18:03:36.141288 ===================================
558 18:03:36.144708 DLL_ASYNC_EN = 0
559 18:03:36.148021 ALL_SLAVE_EN = 1
560 18:03:36.148104 NEW_RANK_MODE = 1
561 18:03:36.151510 DLL_IDLE_MODE = 1
562 18:03:36.154518 LP45_APHY_COMB_EN = 1
563 18:03:36.157906 TX_ODT_DIS = 1
564 18:03:36.157990 NEW_8X_MODE = 1
565 18:03:36.161442 ===================================
566 18:03:36.164615 ===================================
567 18:03:36.168052 data_rate = 1600
568 18:03:36.171198 CKR = 1
569 18:03:36.174798 DQ_P2S_RATIO = 8
570 18:03:36.178423 ===================================
571 18:03:36.181414 CA_P2S_RATIO = 8
572 18:03:36.184894 DQ_CA_OPEN = 0
573 18:03:36.184999 DQ_SEMI_OPEN = 0
574 18:03:36.188211 CA_SEMI_OPEN = 0
575 18:03:36.191472 CA_FULL_RATE = 0
576 18:03:36.195076 DQ_CKDIV4_EN = 1
577 18:03:36.198301 CA_CKDIV4_EN = 1
578 18:03:36.198384 CA_PREDIV_EN = 0
579 18:03:36.201450 PH8_DLY = 0
580 18:03:36.205052 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
581 18:03:36.207981 DQ_AAMCK_DIV = 4
582 18:03:36.211802 CA_AAMCK_DIV = 4
583 18:03:36.214687 CA_ADMCK_DIV = 4
584 18:03:36.214770 DQ_TRACK_CA_EN = 0
585 18:03:36.218349 CA_PICK = 800
586 18:03:36.221848 CA_MCKIO = 800
587 18:03:36.224887 MCKIO_SEMI = 0
588 18:03:36.228358 PLL_FREQ = 3068
589 18:03:36.232046 DQ_UI_PI_RATIO = 32
590 18:03:36.235433 CA_UI_PI_RATIO = 0
591 18:03:36.235517 ===================================
592 18:03:36.239122 ===================================
593 18:03:36.242576 memory_type:LPDDR4
594 18:03:36.246002 GP_NUM : 10
595 18:03:36.246078 SRAM_EN : 1
596 18:03:36.249644 MD32_EN : 0
597 18:03:36.253431 ===================================
598 18:03:36.253542 [ANA_INIT] >>>>>>>>>>>>>>
599 18:03:36.257187 <<<<<< [CONFIGURE PHASE]: ANA_TX
600 18:03:36.260812 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
601 18:03:36.264468 ===================================
602 18:03:36.267852 data_rate = 1600,PCW = 0X7600
603 18:03:36.271388 ===================================
604 18:03:36.274842 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
605 18:03:36.278032 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
606 18:03:36.284935 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 18:03:36.288285 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
608 18:03:36.291521 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
609 18:03:36.295031 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
610 18:03:36.298255 [ANA_INIT] flow start
611 18:03:36.301517 [ANA_INIT] PLL >>>>>>>>
612 18:03:36.301599 [ANA_INIT] PLL <<<<<<<<
613 18:03:36.304719 [ANA_INIT] MIDPI >>>>>>>>
614 18:03:36.307762 [ANA_INIT] MIDPI <<<<<<<<
615 18:03:36.307844 [ANA_INIT] DLL >>>>>>>>
616 18:03:36.311162 [ANA_INIT] flow end
617 18:03:36.314901 ============ LP4 DIFF to SE enter ============
618 18:03:36.318067 ============ LP4 DIFF to SE exit ============
619 18:03:36.321666 [ANA_INIT] <<<<<<<<<<<<<
620 18:03:36.325105 [Flow] Enable top DCM control >>>>>
621 18:03:36.328139 [Flow] Enable top DCM control <<<<<
622 18:03:36.331792 Enable DLL master slave shuffle
623 18:03:36.338188 ==============================================================
624 18:03:36.338271 Gating Mode config
625 18:03:36.345304 ==============================================================
626 18:03:36.345387 Config description:
627 18:03:36.355137 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
628 18:03:36.361450 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
629 18:03:36.368530 SELPH_MODE 0: By rank 1: By Phase
630 18:03:36.372026 ==============================================================
631 18:03:36.375377 GAT_TRACK_EN = 1
632 18:03:36.378346 RX_GATING_MODE = 2
633 18:03:36.381832 RX_GATING_TRACK_MODE = 2
634 18:03:36.385387 SELPH_MODE = 1
635 18:03:36.388242 PICG_EARLY_EN = 1
636 18:03:36.392054 VALID_LAT_VALUE = 1
637 18:03:36.394999 ==============================================================
638 18:03:36.398567 Enter into Gating configuration >>>>
639 18:03:36.401853 Exit from Gating configuration <<<<
640 18:03:36.405121 Enter into DVFS_PRE_config >>>>>
641 18:03:36.419145 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
642 18:03:36.419234 Exit from DVFS_PRE_config <<<<<
643 18:03:36.422425 Enter into PICG configuration >>>>
644 18:03:36.425330 Exit from PICG configuration <<<<
645 18:03:36.428995 [RX_INPUT] configuration >>>>>
646 18:03:36.432134 [RX_INPUT] configuration <<<<<
647 18:03:36.438729 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
648 18:03:36.442150 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
649 18:03:36.449472 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
650 18:03:36.456005 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
651 18:03:36.462720 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
652 18:03:36.466397 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
653 18:03:36.472933 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
654 18:03:36.476365 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
655 18:03:36.479722 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
656 18:03:36.483343 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
657 18:03:36.486317 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
658 18:03:36.493177 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
659 18:03:36.496646 ===================================
660 18:03:36.496728 LPDDR4 DRAM CONFIGURATION
661 18:03:36.499634 ===================================
662 18:03:36.503109 EX_ROW_EN[0] = 0x0
663 18:03:36.506496 EX_ROW_EN[1] = 0x0
664 18:03:36.506578 LP4Y_EN = 0x0
665 18:03:36.510038 WORK_FSP = 0x0
666 18:03:36.510119 WL = 0x2
667 18:03:36.513329 RL = 0x2
668 18:03:36.513411 BL = 0x2
669 18:03:36.516581 RPST = 0x0
670 18:03:36.516662 RD_PRE = 0x0
671 18:03:36.520041 WR_PRE = 0x1
672 18:03:36.520123 WR_PST = 0x0
673 18:03:36.523542 DBI_WR = 0x0
674 18:03:36.523624 DBI_RD = 0x0
675 18:03:36.526384 OTF = 0x1
676 18:03:36.529927 ===================================
677 18:03:36.533623 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
678 18:03:36.536695 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
679 18:03:36.543307 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
680 18:03:36.546616 ===================================
681 18:03:36.546698 LPDDR4 DRAM CONFIGURATION
682 18:03:36.549806 ===================================
683 18:03:36.553895 EX_ROW_EN[0] = 0x10
684 18:03:36.553977 EX_ROW_EN[1] = 0x0
685 18:03:36.556793 LP4Y_EN = 0x0
686 18:03:36.556904 WORK_FSP = 0x0
687 18:03:36.560210 WL = 0x2
688 18:03:36.563580 RL = 0x2
689 18:03:36.563662 BL = 0x2
690 18:03:36.566534 RPST = 0x0
691 18:03:36.566616 RD_PRE = 0x0
692 18:03:36.569929 WR_PRE = 0x1
693 18:03:36.570011 WR_PST = 0x0
694 18:03:36.573663 DBI_WR = 0x0
695 18:03:36.573751 DBI_RD = 0x0
696 18:03:36.576934 OTF = 0x1
697 18:03:36.580613 ===================================
698 18:03:36.583696 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
699 18:03:36.589487 nWR fixed to 40
700 18:03:36.592534 [ModeRegInit_LP4] CH0 RK0
701 18:03:36.592955 [ModeRegInit_LP4] CH0 RK1
702 18:03:36.595799 [ModeRegInit_LP4] CH1 RK0
703 18:03:36.599240 [ModeRegInit_LP4] CH1 RK1
704 18:03:36.599659 match AC timing 13
705 18:03:36.606472 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
706 18:03:36.609773 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
707 18:03:36.612831 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
708 18:03:36.619821 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
709 18:03:36.623212 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
710 18:03:36.623639 [EMI DOE] emi_dcm 0
711 18:03:36.629797 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
712 18:03:36.630235 ==
713 18:03:36.633146 Dram Type= 6, Freq= 0, CH_0, rank 0
714 18:03:36.636229 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
715 18:03:36.636653 ==
716 18:03:36.643400 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
717 18:03:36.646256 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
718 18:03:36.656672 [CA 0] Center 37 (7~68) winsize 62
719 18:03:36.660110 [CA 1] Center 37 (6~68) winsize 63
720 18:03:36.663633 [CA 2] Center 35 (5~66) winsize 62
721 18:03:36.666898 [CA 3] Center 34 (4~65) winsize 62
722 18:03:36.670296 [CA 4] Center 34 (3~65) winsize 63
723 18:03:36.673817 [CA 5] Center 33 (3~64) winsize 62
724 18:03:36.674236
725 18:03:36.676632 [CmdBusTrainingLP45] Vref(ca) range 1: 34
726 18:03:36.677217
727 18:03:36.680063 [CATrainingPosCal] consider 1 rank data
728 18:03:36.683573 u2DelayCellTimex100 = 270/100 ps
729 18:03:36.687046 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
730 18:03:36.690765 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
731 18:03:36.693680 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
732 18:03:36.700359 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
733 18:03:36.703776 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
734 18:03:36.707696 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
735 18:03:36.708215
736 18:03:36.710376 CA PerBit enable=1, Macro0, CA PI delay=33
737 18:03:36.710795
738 18:03:36.714311 [CBTSetCACLKResult] CA Dly = 33
739 18:03:36.714830 CS Dly: 5 (0~36)
740 18:03:36.715169 ==
741 18:03:36.717423 Dram Type= 6, Freq= 0, CH_0, rank 1
742 18:03:36.724267 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
743 18:03:36.724801 ==
744 18:03:36.727750 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
745 18:03:36.734435 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
746 18:03:36.743518 [CA 0] Center 37 (6~68) winsize 63
747 18:03:36.746106 [CA 1] Center 37 (7~68) winsize 62
748 18:03:36.749812 [CA 2] Center 35 (5~66) winsize 62
749 18:03:36.753124 [CA 3] Center 35 (4~66) winsize 63
750 18:03:36.757093 [CA 4] Center 34 (4~65) winsize 62
751 18:03:36.759850 [CA 5] Center 33 (3~64) winsize 62
752 18:03:36.760414
753 18:03:36.763486 [CmdBusTrainingLP45] Vref(ca) range 1: 34
754 18:03:36.764053
755 18:03:36.766784 [CATrainingPosCal] consider 2 rank data
756 18:03:36.770251 u2DelayCellTimex100 = 270/100 ps
757 18:03:36.773452 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
758 18:03:36.776884 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
759 18:03:36.779964 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
760 18:03:36.786913 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
761 18:03:36.790099 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
762 18:03:36.793089 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
763 18:03:36.793563
764 18:03:36.797058 CA PerBit enable=1, Macro0, CA PI delay=33
765 18:03:36.797525
766 18:03:36.800623 [CBTSetCACLKResult] CA Dly = 33
767 18:03:36.801260 CS Dly: 5 (0~37)
768 18:03:36.801636
769 18:03:36.803728 ----->DramcWriteLeveling(PI) begin...
770 18:03:36.804332 ==
771 18:03:36.807350 Dram Type= 6, Freq= 0, CH_0, rank 0
772 18:03:36.813995 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
773 18:03:36.814468 ==
774 18:03:36.814841 Write leveling (Byte 0): 29 => 29
775 18:03:36.817946 Write leveling (Byte 1): 30 => 30
776 18:03:36.821686 DramcWriteLeveling(PI) end<-----
777 18:03:36.822264
778 18:03:36.822638 ==
779 18:03:36.825147 Dram Type= 6, Freq= 0, CH_0, rank 0
780 18:03:36.828944 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
781 18:03:36.829669 ==
782 18:03:36.832395 [Gating] SW mode calibration
783 18:03:36.839317 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
784 18:03:36.845985 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
785 18:03:36.849578 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
786 18:03:36.853037 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
787 18:03:36.856317 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
788 18:03:36.863033 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 18:03:36.865945 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 18:03:36.869677 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 18:03:36.876328 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 18:03:36.879739 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 18:03:36.882919 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 18:03:36.890066 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 18:03:36.893363 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 18:03:36.896585 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 18:03:36.903426 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 18:03:36.906829 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 18:03:36.910074 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 18:03:36.913584 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 18:03:36.919921 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 18:03:36.923505 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 18:03:36.926914 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
804 18:03:36.933228 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 18:03:36.936886 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 18:03:36.940142 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 18:03:36.946797 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 18:03:36.950113 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 18:03:36.953077 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 18:03:36.960446 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 18:03:36.963842 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 18:03:36.966836 0 9 12 | B1->B0 | 2626 3030 | 1 0 | (1 1) (0 0)
813 18:03:36.973924 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
814 18:03:36.977596 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 18:03:36.980948 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 18:03:36.983813 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 18:03:36.990987 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 18:03:36.993889 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 18:03:36.996887 0 10 8 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (1 0)
820 18:03:37.004281 0 10 12 | B1->B0 | 2e2e 2323 | 0 0 | (0 0) (0 0)
821 18:03:37.007201 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 18:03:37.010624 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 18:03:37.017085 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 18:03:37.020673 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 18:03:37.024188 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 18:03:37.030329 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 18:03:37.034197 0 11 8 | B1->B0 | 2424 2e2e | 0 0 | (0 0) (0 0)
828 18:03:37.037510 0 11 12 | B1->B0 | 3434 3d3d | 0 0 | (0 0) (0 0)
829 18:03:37.040387 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
830 18:03:37.048120 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 18:03:37.051028 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 18:03:37.053899 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 18:03:37.060692 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 18:03:37.064563 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 18:03:37.067738 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
836 18:03:37.074317 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
837 18:03:37.077815 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 18:03:37.081336 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 18:03:37.087890 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 18:03:37.091323 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 18:03:37.094303 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 18:03:37.098259 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 18:03:37.104143 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 18:03:37.107914 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 18:03:37.111340 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 18:03:37.117738 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 18:03:37.121225 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 18:03:37.125105 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 18:03:37.131066 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 18:03:37.134804 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 18:03:37.138063 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
852 18:03:37.144900 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
853 18:03:37.145496 Total UI for P1: 0, mck2ui 16
854 18:03:37.151185 best dqsien dly found for B0: ( 0, 14, 8)
855 18:03:37.151661 Total UI for P1: 0, mck2ui 16
856 18:03:37.154676 best dqsien dly found for B1: ( 0, 14, 10)
857 18:03:37.161325 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
858 18:03:37.165053 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
859 18:03:37.165534
860 18:03:37.167957 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
861 18:03:37.171358 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
862 18:03:37.174953 [Gating] SW calibration Done
863 18:03:37.175428 ==
864 18:03:37.178483 Dram Type= 6, Freq= 0, CH_0, rank 0
865 18:03:37.181333 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
866 18:03:37.181811 ==
867 18:03:37.182288 RX Vref Scan: 0
868 18:03:37.185176
869 18:03:37.185749 RX Vref 0 -> 0, step: 1
870 18:03:37.186238
871 18:03:37.188552 RX Delay -130 -> 252, step: 16
872 18:03:37.191796 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
873 18:03:37.194924 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
874 18:03:37.202015 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
875 18:03:37.205098 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
876 18:03:37.208777 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
877 18:03:37.212324 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
878 18:03:37.215709 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
879 18:03:37.218948 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
880 18:03:37.225603 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
881 18:03:37.229138 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
882 18:03:37.232095 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
883 18:03:37.235454 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
884 18:03:37.238673 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
885 18:03:37.245696 iDelay=222, Bit 13, Center 77 (-34 ~ 189) 224
886 18:03:37.248860 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
887 18:03:37.252127 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
888 18:03:37.252589 ==
889 18:03:37.255678 Dram Type= 6, Freq= 0, CH_0, rank 0
890 18:03:37.259224 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
891 18:03:37.259787 ==
892 18:03:37.261974 DQS Delay:
893 18:03:37.262438 DQS0 = 0, DQS1 = 0
894 18:03:37.265890 DQM Delay:
895 18:03:37.266451 DQM0 = 84, DQM1 = 77
896 18:03:37.266825 DQ Delay:
897 18:03:37.268964 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
898 18:03:37.272267 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =85
899 18:03:37.275662 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
900 18:03:37.279612 DQ12 =85, DQ13 =77, DQ14 =85, DQ15 =85
901 18:03:37.280206
902 18:03:37.280780
903 18:03:37.282560 ==
904 18:03:37.283022 Dram Type= 6, Freq= 0, CH_0, rank 0
905 18:03:37.289091 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
906 18:03:37.289653 ==
907 18:03:37.290024
908 18:03:37.290364
909 18:03:37.292827 TX Vref Scan disable
910 18:03:37.293441 == TX Byte 0 ==
911 18:03:37.295575 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
912 18:03:37.302863 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
913 18:03:37.303437 == TX Byte 1 ==
914 18:03:37.306024 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
915 18:03:37.312571 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
916 18:03:37.313174 ==
917 18:03:37.316338 Dram Type= 6, Freq= 0, CH_0, rank 0
918 18:03:37.318815 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
919 18:03:37.319285 ==
920 18:03:37.332250 TX Vref=22, minBit 0, minWin=27, winSum=441
921 18:03:37.335692 TX Vref=24, minBit 0, minWin=27, winSum=441
922 18:03:37.338605 TX Vref=26, minBit 0, minWin=27, winSum=444
923 18:03:37.342375 TX Vref=28, minBit 5, minWin=27, winSum=448
924 18:03:37.345465 TX Vref=30, minBit 3, minWin=28, winSum=452
925 18:03:37.348878 TX Vref=32, minBit 2, minWin=28, winSum=453
926 18:03:37.355700 [TxChooseVref] Worse bit 2, Min win 28, Win sum 453, Final Vref 32
927 18:03:37.356341
928 18:03:37.358543 Final TX Range 1 Vref 32
929 18:03:37.359020
930 18:03:37.359511 ==
931 18:03:37.362105 Dram Type= 6, Freq= 0, CH_0, rank 0
932 18:03:37.365492 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
933 18:03:37.365974 ==
934 18:03:37.366451
935 18:03:37.366896
936 18:03:37.368803 TX Vref Scan disable
937 18:03:37.372091 == TX Byte 0 ==
938 18:03:37.375377 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
939 18:03:37.378876 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
940 18:03:37.382232 == TX Byte 1 ==
941 18:03:37.385610 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
942 18:03:37.389010 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
943 18:03:37.389451
944 18:03:37.392333 [DATLAT]
945 18:03:37.392863 Freq=800, CH0 RK0
946 18:03:37.393310
947 18:03:37.395572 DATLAT Default: 0xa
948 18:03:37.396036 0, 0xFFFF, sum = 0
949 18:03:37.398607 1, 0xFFFF, sum = 0
950 18:03:37.399036 2, 0xFFFF, sum = 0
951 18:03:37.402151 3, 0xFFFF, sum = 0
952 18:03:37.402579 4, 0xFFFF, sum = 0
953 18:03:37.405491 5, 0xFFFF, sum = 0
954 18:03:37.405917 6, 0xFFFF, sum = 0
955 18:03:37.409070 7, 0xFFFF, sum = 0
956 18:03:37.409498 8, 0xFFFF, sum = 0
957 18:03:37.412369 9, 0x0, sum = 1
958 18:03:37.412795 10, 0x0, sum = 2
959 18:03:37.416223 11, 0x0, sum = 3
960 18:03:37.416754 12, 0x0, sum = 4
961 18:03:37.419288 best_step = 10
962 18:03:37.419705
963 18:03:37.420038 ==
964 18:03:37.422661 Dram Type= 6, Freq= 0, CH_0, rank 0
965 18:03:37.425822 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
966 18:03:37.426379 ==
967 18:03:37.428873 RX Vref Scan: 1
968 18:03:37.429327
969 18:03:37.429660 Set Vref Range= 32 -> 127
970 18:03:37.429973
971 18:03:37.432513 RX Vref 32 -> 127, step: 1
972 18:03:37.433292
973 18:03:37.435737 RX Delay -95 -> 252, step: 8
974 18:03:37.436154
975 18:03:37.439433 Set Vref, RX VrefLevel [Byte0]: 32
976 18:03:37.442248 [Byte1]: 32
977 18:03:37.442662
978 18:03:37.446037 Set Vref, RX VrefLevel [Byte0]: 33
979 18:03:37.449639 [Byte1]: 33
980 18:03:37.450075
981 18:03:37.453143 Set Vref, RX VrefLevel [Byte0]: 34
982 18:03:37.456418 [Byte1]: 34
983 18:03:37.459947
984 18:03:37.460362 Set Vref, RX VrefLevel [Byte0]: 35
985 18:03:37.463257 [Byte1]: 35
986 18:03:37.467868
987 18:03:37.468378 Set Vref, RX VrefLevel [Byte0]: 36
988 18:03:37.470562 [Byte1]: 36
989 18:03:37.474980
990 18:03:37.475566 Set Vref, RX VrefLevel [Byte0]: 37
991 18:03:37.478322 [Byte1]: 37
992 18:03:37.483051
993 18:03:37.483528 Set Vref, RX VrefLevel [Byte0]: 38
994 18:03:37.486426 [Byte1]: 38
995 18:03:37.490443
996 18:03:37.490855 Set Vref, RX VrefLevel [Byte0]: 39
997 18:03:37.493763 [Byte1]: 39
998 18:03:37.498561
999 18:03:37.498974 Set Vref, RX VrefLevel [Byte0]: 40
1000 18:03:37.501495 [Byte1]: 40
1001 18:03:37.505374
1002 18:03:37.505794 Set Vref, RX VrefLevel [Byte0]: 41
1003 18:03:37.509077 [Byte1]: 41
1004 18:03:37.513242
1005 18:03:37.513657 Set Vref, RX VrefLevel [Byte0]: 42
1006 18:03:37.516428 [Byte1]: 42
1007 18:03:37.520864
1008 18:03:37.521428 Set Vref, RX VrefLevel [Byte0]: 43
1009 18:03:37.524234 [Byte1]: 43
1010 18:03:37.528488
1011 18:03:37.529084 Set Vref, RX VrefLevel [Byte0]: 44
1012 18:03:37.531660 [Byte1]: 44
1013 18:03:37.535762
1014 18:03:37.536323 Set Vref, RX VrefLevel [Byte0]: 45
1015 18:03:37.539000 [Byte1]: 45
1016 18:03:37.543366
1017 18:03:37.543932 Set Vref, RX VrefLevel [Byte0]: 46
1018 18:03:37.546717 [Byte1]: 46
1019 18:03:37.551397
1020 18:03:37.551958 Set Vref, RX VrefLevel [Byte0]: 47
1021 18:03:37.554478 [Byte1]: 47
1022 18:03:37.558354
1023 18:03:37.558836 Set Vref, RX VrefLevel [Byte0]: 48
1024 18:03:37.561915 [Byte1]: 48
1025 18:03:37.566463
1026 18:03:37.566955 Set Vref, RX VrefLevel [Byte0]: 49
1027 18:03:37.569467 [Byte1]: 49
1028 18:03:37.573939
1029 18:03:37.574490 Set Vref, RX VrefLevel [Byte0]: 50
1030 18:03:37.577165 [Byte1]: 50
1031 18:03:37.581342
1032 18:03:37.582103 Set Vref, RX VrefLevel [Byte0]: 51
1033 18:03:37.584507 [Byte1]: 51
1034 18:03:37.589159
1035 18:03:37.589717 Set Vref, RX VrefLevel [Byte0]: 52
1036 18:03:37.592243 [Byte1]: 52
1037 18:03:37.596573
1038 18:03:37.597165 Set Vref, RX VrefLevel [Byte0]: 53
1039 18:03:37.599942 [Byte1]: 53
1040 18:03:37.604376
1041 18:03:37.605044 Set Vref, RX VrefLevel [Byte0]: 54
1042 18:03:37.607935 [Byte1]: 54
1043 18:03:37.611741
1044 18:03:37.612198 Set Vref, RX VrefLevel [Byte0]: 55
1045 18:03:37.615085 [Byte1]: 55
1046 18:03:37.619704
1047 18:03:37.620257 Set Vref, RX VrefLevel [Byte0]: 56
1048 18:03:37.622367 [Byte1]: 56
1049 18:03:37.626809
1050 18:03:37.627266 Set Vref, RX VrefLevel [Byte0]: 57
1051 18:03:37.629987 [Byte1]: 57
1052 18:03:37.634315
1053 18:03:37.634766 Set Vref, RX VrefLevel [Byte0]: 58
1054 18:03:37.637783 [Byte1]: 58
1055 18:03:37.642115
1056 18:03:37.642567 Set Vref, RX VrefLevel [Byte0]: 59
1057 18:03:37.645348 [Byte1]: 59
1058 18:03:37.649905
1059 18:03:37.650453 Set Vref, RX VrefLevel [Byte0]: 60
1060 18:03:37.652832 [Byte1]: 60
1061 18:03:37.656909
1062 18:03:37.657395 Set Vref, RX VrefLevel [Byte0]: 61
1063 18:03:37.660355 [Byte1]: 61
1064 18:03:37.664706
1065 18:03:37.665295 Set Vref, RX VrefLevel [Byte0]: 62
1066 18:03:37.668027 [Byte1]: 62
1067 18:03:37.672408
1068 18:03:37.672934 Set Vref, RX VrefLevel [Byte0]: 63
1069 18:03:37.675949 [Byte1]: 63
1070 18:03:37.680372
1071 18:03:37.680926 Set Vref, RX VrefLevel [Byte0]: 64
1072 18:03:37.683896 [Byte1]: 64
1073 18:03:37.687478
1074 18:03:37.687932 Set Vref, RX VrefLevel [Byte0]: 65
1075 18:03:37.691387 [Byte1]: 65
1076 18:03:37.695417
1077 18:03:37.695970 Set Vref, RX VrefLevel [Byte0]: 66
1078 18:03:37.699066 [Byte1]: 66
1079 18:03:37.702951
1080 18:03:37.703478 Set Vref, RX VrefLevel [Byte0]: 67
1081 18:03:37.705827 [Byte1]: 67
1082 18:03:37.710198
1083 18:03:37.710654 Set Vref, RX VrefLevel [Byte0]: 68
1084 18:03:37.713760 [Byte1]: 68
1085 18:03:37.718316
1086 18:03:37.719054 Set Vref, RX VrefLevel [Byte0]: 69
1087 18:03:37.721258 [Byte1]: 69
1088 18:03:37.725820
1089 18:03:37.726380 Set Vref, RX VrefLevel [Byte0]: 70
1090 18:03:37.728688 [Byte1]: 70
1091 18:03:37.732882
1092 18:03:37.733493 Set Vref, RX VrefLevel [Byte0]: 71
1093 18:03:37.736443 [Byte1]: 71
1094 18:03:37.741422
1095 18:03:37.741900 Set Vref, RX VrefLevel [Byte0]: 72
1096 18:03:37.746585 [Byte1]: 72
1097 18:03:37.748389
1098 18:03:37.748846 Set Vref, RX VrefLevel [Byte0]: 73
1099 18:03:37.751313 [Byte1]: 73
1100 18:03:37.755968
1101 18:03:37.756533 Set Vref, RX VrefLevel [Byte0]: 74
1102 18:03:37.759012 [Byte1]: 74
1103 18:03:37.763859
1104 18:03:37.764381 Set Vref, RX VrefLevel [Byte0]: 75
1105 18:03:37.766963 [Byte1]: 75
1106 18:03:37.771288
1107 18:03:37.771839 Set Vref, RX VrefLevel [Byte0]: 76
1108 18:03:37.774676 [Byte1]: 76
1109 18:03:37.778971
1110 18:03:37.779527 Set Vref, RX VrefLevel [Byte0]: 77
1111 18:03:37.782168 [Byte1]: 77
1112 18:03:37.786436
1113 18:03:37.786995 Final RX Vref Byte 0 = 59 to rank0
1114 18:03:37.789862 Final RX Vref Byte 1 = 58 to rank0
1115 18:03:37.793066 Final RX Vref Byte 0 = 59 to rank1
1116 18:03:37.796948 Final RX Vref Byte 1 = 58 to rank1==
1117 18:03:37.799975 Dram Type= 6, Freq= 0, CH_0, rank 0
1118 18:03:37.803542 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1119 18:03:37.806193 ==
1120 18:03:37.806650 DQS Delay:
1121 18:03:37.807015 DQS0 = 0, DQS1 = 0
1122 18:03:37.809847 DQM Delay:
1123 18:03:37.810297 DQM0 = 86, DQM1 = 79
1124 18:03:37.813390 DQ Delay:
1125 18:03:37.813948 DQ0 =84, DQ1 =92, DQ2 =84, DQ3 =84
1126 18:03:37.817132 DQ4 =84, DQ5 =76, DQ6 =92, DQ7 =92
1127 18:03:37.820589 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =76
1128 18:03:37.823281 DQ12 =80, DQ13 =80, DQ14 =92, DQ15 =88
1129 18:03:37.823838
1130 18:03:37.826329
1131 18:03:37.833299 [DQSOSCAuto] RK0, (LSB)MR18= 0x2a11, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 399 ps
1132 18:03:37.836888 CH0 RK0: MR19=606, MR18=2A11
1133 18:03:37.843294 CH0_RK0: MR19=0x606, MR18=0x2A11, DQSOSC=399, MR23=63, INC=92, DEC=61
1134 18:03:37.843758
1135 18:03:37.846963 ----->DramcWriteLeveling(PI) begin...
1136 18:03:37.847442 ==
1137 18:03:37.850294 Dram Type= 6, Freq= 0, CH_0, rank 1
1138 18:03:37.853644 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1139 18:03:37.854110 ==
1140 18:03:37.856862 Write leveling (Byte 0): 30 => 30
1141 18:03:37.860400 Write leveling (Byte 1): 29 => 29
1142 18:03:37.863749 DramcWriteLeveling(PI) end<-----
1143 18:03:37.864303
1144 18:03:37.864667 ==
1145 18:03:37.866872 Dram Type= 6, Freq= 0, CH_0, rank 1
1146 18:03:37.870461 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1147 18:03:37.870921 ==
1148 18:03:37.873383 [Gating] SW mode calibration
1149 18:03:37.880400 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1150 18:03:37.886631 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1151 18:03:37.931000 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1152 18:03:37.931517 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1153 18:03:37.931886 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1154 18:03:37.932292 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1155 18:03:37.933049 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 18:03:37.933437 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 18:03:37.933767 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 18:03:37.934084 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 18:03:37.934400 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 18:03:37.934712 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 18:03:37.939730 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 18:03:37.940188 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 18:03:37.942908 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 18:03:37.946345 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 18:03:37.949561 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 18:03:37.956642 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 18:03:37.959474 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 18:03:37.963257 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 18:03:37.969885 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1170 18:03:37.972716 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 18:03:37.975937 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 18:03:37.982791 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 18:03:37.986245 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 18:03:37.989543 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 18:03:37.996609 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 18:03:38.000216 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 18:03:38.002625 0 9 8 | B1->B0 | 2323 3232 | 0 0 | (1 1) (0 0)
1178 18:03:38.010295 0 9 12 | B1->B0 | 2f2f 3434 | 0 1 | (1 1) (1 1)
1179 18:03:38.012833 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1180 18:03:38.016560 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1181 18:03:38.022988 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1182 18:03:38.026575 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1183 18:03:38.030081 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1184 18:03:38.033548 0 10 4 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
1185 18:03:38.039956 0 10 8 | B1->B0 | 3434 2828 | 1 0 | (1 1) (0 0)
1186 18:03:38.043542 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
1187 18:03:38.046303 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 18:03:38.053461 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 18:03:38.056601 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 18:03:38.060337 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 18:03:38.063819 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 18:03:38.071239 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 18:03:38.074693 0 11 8 | B1->B0 | 2f2f 4343 | 0 0 | (0 0) (0 0)
1194 18:03:38.077814 0 11 12 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
1195 18:03:38.081278 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1196 18:03:38.088576 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1197 18:03:38.091930 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1198 18:03:38.095200 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1199 18:03:38.101954 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1200 18:03:38.105383 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1201 18:03:38.108862 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1202 18:03:38.115892 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 18:03:38.118906 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 18:03:38.122190 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 18:03:38.125536 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 18:03:38.132124 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 18:03:38.135726 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 18:03:38.139092 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 18:03:38.145878 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 18:03:38.148763 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 18:03:38.152306 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 18:03:38.159539 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 18:03:38.162376 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 18:03:38.165763 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 18:03:38.172285 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 18:03:38.175517 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1217 18:03:38.179130 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1218 18:03:38.182071 Total UI for P1: 0, mck2ui 16
1219 18:03:38.185489 best dqsien dly found for B0: ( 0, 14, 4)
1220 18:03:38.188879 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1221 18:03:38.192332 Total UI for P1: 0, mck2ui 16
1222 18:03:38.196160 best dqsien dly found for B1: ( 0, 14, 8)
1223 18:03:38.199152 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1224 18:03:38.202383 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1225 18:03:38.205633
1226 18:03:38.209468 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1227 18:03:38.212591 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1228 18:03:38.215495 [Gating] SW calibration Done
1229 18:03:38.215915 ==
1230 18:03:38.218909 Dram Type= 6, Freq= 0, CH_0, rank 1
1231 18:03:38.222395 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1232 18:03:38.222857 ==
1233 18:03:38.223224 RX Vref Scan: 0
1234 18:03:38.223567
1235 18:03:38.225904 RX Vref 0 -> 0, step: 1
1236 18:03:38.226362
1237 18:03:38.229386 RX Delay -130 -> 252, step: 16
1238 18:03:38.232387 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1239 18:03:38.235731 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1240 18:03:38.242381 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1241 18:03:38.245647 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1242 18:03:38.249362 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1243 18:03:38.252774 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1244 18:03:38.255779 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1245 18:03:38.259386 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1246 18:03:38.265790 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1247 18:03:38.269432 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1248 18:03:38.272828 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1249 18:03:38.276438 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1250 18:03:38.279410 iDelay=222, Bit 12, Center 69 (-50 ~ 189) 240
1251 18:03:38.285796 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1252 18:03:38.289355 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1253 18:03:38.292995 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1254 18:03:38.293420 ==
1255 18:03:38.296238 Dram Type= 6, Freq= 0, CH_0, rank 1
1256 18:03:38.299743 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1257 18:03:38.300264 ==
1258 18:03:38.302683 DQS Delay:
1259 18:03:38.303102 DQS0 = 0, DQS1 = 0
1260 18:03:38.306166 DQM Delay:
1261 18:03:38.306582 DQM0 = 86, DQM1 = 75
1262 18:03:38.306917 DQ Delay:
1263 18:03:38.309535 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
1264 18:03:38.313478 DQ4 =85, DQ5 =69, DQ6 =101, DQ7 =93
1265 18:03:38.316104 DQ8 =69, DQ9 =69, DQ10 =69, DQ11 =69
1266 18:03:38.319846 DQ12 =69, DQ13 =85, DQ14 =85, DQ15 =85
1267 18:03:38.320338
1268 18:03:38.320668
1269 18:03:38.321013 ==
1270 18:03:38.323132 Dram Type= 6, Freq= 0, CH_0, rank 1
1271 18:03:38.329777 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1272 18:03:38.330265 ==
1273 18:03:38.330602
1274 18:03:38.330908
1275 18:03:38.331202 TX Vref Scan disable
1276 18:03:38.333891 == TX Byte 0 ==
1277 18:03:38.336885 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1278 18:03:38.340448 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1279 18:03:38.343411 == TX Byte 1 ==
1280 18:03:38.347410 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1281 18:03:38.350350 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1282 18:03:38.353634 ==
1283 18:03:38.357407 Dram Type= 6, Freq= 0, CH_0, rank 1
1284 18:03:38.360259 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1285 18:03:38.360768 ==
1286 18:03:38.372713 TX Vref=22, minBit 1, minWin=27, winSum=443
1287 18:03:38.376063 TX Vref=24, minBit 2, minWin=27, winSum=447
1288 18:03:38.379614 TX Vref=26, minBit 7, minWin=27, winSum=450
1289 18:03:38.382394 TX Vref=28, minBit 0, minWin=28, winSum=451
1290 18:03:38.385939 TX Vref=30, minBit 0, minWin=28, winSum=454
1291 18:03:38.389375 TX Vref=32, minBit 0, minWin=28, winSum=453
1292 18:03:38.396454 [TxChooseVref] Worse bit 0, Min win 28, Win sum 454, Final Vref 30
1293 18:03:38.396918
1294 18:03:38.399380 Final TX Range 1 Vref 30
1295 18:03:38.399794
1296 18:03:38.400120 ==
1297 18:03:38.402766 Dram Type= 6, Freq= 0, CH_0, rank 1
1298 18:03:38.406591 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1299 18:03:38.407009 ==
1300 18:03:38.407338
1301 18:03:38.407727
1302 18:03:38.409605 TX Vref Scan disable
1303 18:03:38.412755 == TX Byte 0 ==
1304 18:03:38.415774 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1305 18:03:38.419686 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1306 18:03:38.423150 == TX Byte 1 ==
1307 18:03:38.426081 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1308 18:03:38.429663 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1309 18:03:38.429960
1310 18:03:38.432818 [DATLAT]
1311 18:03:38.433136 Freq=800, CH0 RK1
1312 18:03:38.433374
1313 18:03:38.435882 DATLAT Default: 0xa
1314 18:03:38.436177 0, 0xFFFF, sum = 0
1315 18:03:38.439242 1, 0xFFFF, sum = 0
1316 18:03:38.439555 2, 0xFFFF, sum = 0
1317 18:03:38.442624 3, 0xFFFF, sum = 0
1318 18:03:38.442921 4, 0xFFFF, sum = 0
1319 18:03:38.445922 5, 0xFFFF, sum = 0
1320 18:03:38.446223 6, 0xFFFF, sum = 0
1321 18:03:38.449591 7, 0xFFFF, sum = 0
1322 18:03:38.449891 8, 0xFFFF, sum = 0
1323 18:03:38.452435 9, 0x0, sum = 1
1324 18:03:38.452734 10, 0x0, sum = 2
1325 18:03:38.455976 11, 0x0, sum = 3
1326 18:03:38.456393 12, 0x0, sum = 4
1327 18:03:38.459530 best_step = 10
1328 18:03:38.459940
1329 18:03:38.460268 ==
1330 18:03:38.463173 Dram Type= 6, Freq= 0, CH_0, rank 1
1331 18:03:38.466199 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1332 18:03:38.466616 ==
1333 18:03:38.469863 RX Vref Scan: 0
1334 18:03:38.470298
1335 18:03:38.470654 RX Vref 0 -> 0, step: 1
1336 18:03:38.470960
1337 18:03:38.472513 RX Delay -95 -> 252, step: 8
1338 18:03:38.479248 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1339 18:03:38.482788 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1340 18:03:38.486262 iDelay=209, Bit 2, Center 84 (-31 ~ 200) 232
1341 18:03:38.489653 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1342 18:03:38.493315 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1343 18:03:38.499727 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1344 18:03:38.503285 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1345 18:03:38.506047 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1346 18:03:38.509370 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
1347 18:03:38.513012 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1348 18:03:38.516463 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1349 18:03:38.522912 iDelay=209, Bit 11, Center 68 (-39 ~ 176) 216
1350 18:03:38.526346 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
1351 18:03:38.529586 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1352 18:03:38.533243 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1353 18:03:38.536318 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1354 18:03:38.539630 ==
1355 18:03:38.543236 Dram Type= 6, Freq= 0, CH_0, rank 1
1356 18:03:38.546538 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1357 18:03:38.546960 ==
1358 18:03:38.547289 DQS Delay:
1359 18:03:38.550269 DQS0 = 0, DQS1 = 0
1360 18:03:38.550684 DQM Delay:
1361 18:03:38.553069 DQM0 = 87, DQM1 = 78
1362 18:03:38.553483 DQ Delay:
1363 18:03:38.556474 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =84
1364 18:03:38.559728 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1365 18:03:38.563448 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1366 18:03:38.566546 DQ12 =80, DQ13 =84, DQ14 =88, DQ15 =88
1367 18:03:38.566964
1368 18:03:38.567290
1369 18:03:38.573522 [DQSOSCAuto] RK1, (LSB)MR18= 0x3019, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 397 ps
1370 18:03:38.576903 CH0 RK1: MR19=606, MR18=3019
1371 18:03:38.583329 CH0_RK1: MR19=0x606, MR18=0x3019, DQSOSC=397, MR23=63, INC=93, DEC=62
1372 18:03:38.586619 [RxdqsGatingPostProcess] freq 800
1373 18:03:38.590017 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1374 18:03:38.593416 Pre-setting of DQS Precalculation
1375 18:03:38.600492 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1376 18:03:38.600916 ==
1377 18:03:38.603373 Dram Type= 6, Freq= 0, CH_1, rank 0
1378 18:03:38.606933 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1379 18:03:38.607353 ==
1380 18:03:38.613483 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1381 18:03:38.616907 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1382 18:03:38.627403 [CA 0] Center 36 (6~67) winsize 62
1383 18:03:38.631030 [CA 1] Center 36 (6~67) winsize 62
1384 18:03:38.634488 [CA 2] Center 35 (5~65) winsize 61
1385 18:03:38.637847 [CA 3] Center 34 (3~65) winsize 63
1386 18:03:38.640796 [CA 4] Center 34 (3~65) winsize 63
1387 18:03:38.644061 [CA 5] Center 33 (3~64) winsize 62
1388 18:03:38.644477
1389 18:03:38.647940 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1390 18:03:38.648360
1391 18:03:38.651265 [CATrainingPosCal] consider 1 rank data
1392 18:03:38.654918 u2DelayCellTimex100 = 270/100 ps
1393 18:03:38.657991 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1394 18:03:38.661369 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1395 18:03:38.664363 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
1396 18:03:38.671556 CA3 delay=34 (3~65),Diff = 1 PI (7 cell)
1397 18:03:38.674505 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
1398 18:03:38.677964 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1399 18:03:38.678424
1400 18:03:38.681136 CA PerBit enable=1, Macro0, CA PI delay=33
1401 18:03:38.681559
1402 18:03:38.684827 [CBTSetCACLKResult] CA Dly = 33
1403 18:03:38.685273 CS Dly: 5 (0~36)
1404 18:03:38.685610 ==
1405 18:03:38.687854 Dram Type= 6, Freq= 0, CH_1, rank 1
1406 18:03:38.694268 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1407 18:03:38.694779 ==
1408 18:03:38.697950 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1409 18:03:38.704775 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1410 18:03:38.713766 [CA 0] Center 36 (6~67) winsize 62
1411 18:03:38.716765 [CA 1] Center 36 (6~67) winsize 62
1412 18:03:38.721027 [CA 2] Center 34 (4~65) winsize 62
1413 18:03:38.723619 [CA 3] Center 33 (3~64) winsize 62
1414 18:03:38.727384 [CA 4] Center 34 (3~65) winsize 63
1415 18:03:38.731303 [CA 5] Center 33 (3~64) winsize 62
1416 18:03:38.731741
1417 18:03:38.734911 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1418 18:03:38.735331
1419 18:03:38.738375 [CATrainingPosCal] consider 2 rank data
1420 18:03:38.742547 u2DelayCellTimex100 = 270/100 ps
1421 18:03:38.746017 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1422 18:03:38.749458 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1423 18:03:38.752969 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
1424 18:03:38.756514 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1425 18:03:38.760587 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
1426 18:03:38.764178 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1427 18:03:38.764594
1428 18:03:38.767060 CA PerBit enable=1, Macro0, CA PI delay=33
1429 18:03:38.767479
1430 18:03:38.770387 [CBTSetCACLKResult] CA Dly = 33
1431 18:03:38.770804 CS Dly: 5 (0~37)
1432 18:03:38.771136
1433 18:03:38.773792 ----->DramcWriteLeveling(PI) begin...
1434 18:03:38.774250 ==
1435 18:03:38.777244 Dram Type= 6, Freq= 0, CH_1, rank 0
1436 18:03:38.783594 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1437 18:03:38.784140 ==
1438 18:03:38.787443 Write leveling (Byte 0): 28 => 28
1439 18:03:38.790422 Write leveling (Byte 1): 29 => 29
1440 18:03:38.790840 DramcWriteLeveling(PI) end<-----
1441 18:03:38.791170
1442 18:03:38.794493 ==
1443 18:03:38.797283 Dram Type= 6, Freq= 0, CH_1, rank 0
1444 18:03:38.800659 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1445 18:03:38.801113 ==
1446 18:03:38.803902 [Gating] SW mode calibration
1447 18:03:38.810804 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1448 18:03:38.813673 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1449 18:03:38.820365 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1450 18:03:38.824320 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1451 18:03:38.827817 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1452 18:03:38.834268 0 6 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1453 18:03:38.837643 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 18:03:38.840506 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 18:03:38.847782 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 18:03:38.850913 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 18:03:38.854420 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 18:03:38.857665 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 18:03:38.864238 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 18:03:38.867436 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 18:03:38.870895 0 7 16 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1462 18:03:38.877926 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 18:03:38.880885 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 18:03:38.884059 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 18:03:38.891002 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 18:03:38.894238 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 1)
1467 18:03:38.897476 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
1468 18:03:38.904587 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 18:03:38.907782 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 18:03:38.911107 0 8 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1471 18:03:38.917657 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 18:03:38.921289 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 18:03:38.924177 0 9 0 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1474 18:03:38.931222 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 18:03:38.934208 0 9 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1476 18:03:38.937835 0 9 12 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1477 18:03:38.940674 0 9 16 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1478 18:03:38.947803 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1479 18:03:38.951499 0 9 24 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1480 18:03:38.954297 0 9 28 | B1->B0 | 3535 3434 | 1 1 | (0 0) (1 1)
1481 18:03:38.961594 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1482 18:03:38.964183 0 10 4 | B1->B0 | 3535 3434 | 0 1 | (0 1) (1 0)
1483 18:03:38.967655 0 10 8 | B1->B0 | 2c2c 3030 | 0 1 | (0 0) (1 0)
1484 18:03:38.974407 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1485 18:03:38.978031 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 18:03:38.981382 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 18:03:38.987769 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 18:03:38.990841 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 18:03:38.994601 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 18:03:39.001140 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 18:03:39.004572 0 11 8 | B1->B0 | 3030 2e2e | 0 0 | (0 0) (0 0)
1492 18:03:39.007930 0 11 12 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
1493 18:03:39.014429 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1494 18:03:39.017798 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1495 18:03:39.021242 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1496 18:03:39.024563 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1497 18:03:39.031590 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1498 18:03:39.034598 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1499 18:03:39.038088 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1500 18:03:39.044348 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1501 18:03:39.048174 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 18:03:39.051485 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 18:03:39.057871 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 18:03:39.061384 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 18:03:39.064965 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 18:03:39.071297 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 18:03:39.074787 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 18:03:39.078293 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 18:03:39.085215 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 18:03:39.088439 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 18:03:39.091367 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 18:03:39.094691 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 18:03:39.101686 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 18:03:39.105124 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1515 18:03:39.108562 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1516 18:03:39.111729 Total UI for P1: 0, mck2ui 16
1517 18:03:39.114760 best dqsien dly found for B1: ( 0, 14, 6)
1518 18:03:39.121738 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1519 18:03:39.122283 Total UI for P1: 0, mck2ui 16
1520 18:03:39.125155 best dqsien dly found for B0: ( 0, 14, 6)
1521 18:03:39.132404 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1522 18:03:39.135152 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1523 18:03:39.135604
1524 18:03:39.138607 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1525 18:03:39.141956 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1526 18:03:39.145724 [Gating] SW calibration Done
1527 18:03:39.146178 ==
1528 18:03:39.148691 Dram Type= 6, Freq= 0, CH_1, rank 0
1529 18:03:39.152198 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1530 18:03:39.152656 ==
1531 18:03:39.153145 RX Vref Scan: 0
1532 18:03:39.153476
1533 18:03:39.155216 RX Vref 0 -> 0, step: 1
1534 18:03:39.155699
1535 18:03:39.158899 RX Delay -130 -> 252, step: 16
1536 18:03:39.162041 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
1537 18:03:39.165600 iDelay=206, Bit 1, Center 77 (-34 ~ 189) 224
1538 18:03:39.172354 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1539 18:03:39.175805 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1540 18:03:39.179286 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1541 18:03:39.182520 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1542 18:03:39.185517 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1543 18:03:39.192466 iDelay=206, Bit 7, Center 77 (-34 ~ 189) 224
1544 18:03:39.196184 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1545 18:03:39.198760 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1546 18:03:39.202167 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1547 18:03:39.205827 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1548 18:03:39.212647 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1549 18:03:39.215446 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1550 18:03:39.219224 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1551 18:03:39.222860 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1552 18:03:39.223555 ==
1553 18:03:39.225926 Dram Type= 6, Freq= 0, CH_1, rank 0
1554 18:03:39.229368 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1555 18:03:39.232378 ==
1556 18:03:39.232918 DQS Delay:
1557 18:03:39.233511 DQS0 = 0, DQS1 = 0
1558 18:03:39.236113 DQM Delay:
1559 18:03:39.236662 DQM0 = 84, DQM1 = 77
1560 18:03:39.237103 DQ Delay:
1561 18:03:39.239339 DQ0 =93, DQ1 =77, DQ2 =69, DQ3 =85
1562 18:03:39.242916 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =77
1563 18:03:39.245750 DQ8 =69, DQ9 =69, DQ10 =69, DQ11 =69
1564 18:03:39.249303 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1565 18:03:39.249761
1566 18:03:39.250121
1567 18:03:39.253049 ==
1568 18:03:39.253467 Dram Type= 6, Freq= 0, CH_1, rank 0
1569 18:03:39.259403 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1570 18:03:39.259815 ==
1571 18:03:39.260137
1572 18:03:39.260440
1573 18:03:39.262330 TX Vref Scan disable
1574 18:03:39.262737 == TX Byte 0 ==
1575 18:03:39.265754 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1576 18:03:39.272758 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1577 18:03:39.273200 == TX Byte 1 ==
1578 18:03:39.276181 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1579 18:03:39.283043 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1580 18:03:39.283458 ==
1581 18:03:39.286460 Dram Type= 6, Freq= 0, CH_1, rank 0
1582 18:03:39.289532 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1583 18:03:39.289940 ==
1584 18:03:39.302436 TX Vref=22, minBit 1, minWin=27, winSum=440
1585 18:03:39.305489 TX Vref=24, minBit 1, minWin=27, winSum=445
1586 18:03:39.309403 TX Vref=26, minBit 0, minWin=28, winSum=449
1587 18:03:39.313091 TX Vref=28, minBit 0, minWin=28, winSum=453
1588 18:03:39.316408 TX Vref=30, minBit 11, minWin=27, winSum=453
1589 18:03:39.319574 TX Vref=32, minBit 11, minWin=27, winSum=455
1590 18:03:39.326360 [TxChooseVref] Worse bit 0, Min win 28, Win sum 453, Final Vref 28
1591 18:03:39.326775
1592 18:03:39.330323 Final TX Range 1 Vref 28
1593 18:03:39.330774
1594 18:03:39.331269 ==
1595 18:03:39.333192 Dram Type= 6, Freq= 0, CH_1, rank 0
1596 18:03:39.337074 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1597 18:03:39.337809 ==
1598 18:03:39.338322
1599 18:03:39.338740
1600 18:03:39.340040 TX Vref Scan disable
1601 18:03:39.343161 == TX Byte 0 ==
1602 18:03:39.346468 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1603 18:03:39.349951 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1604 18:03:39.353643 == TX Byte 1 ==
1605 18:03:39.357091 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1606 18:03:39.360157 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1607 18:03:39.360569
1608 18:03:39.361098 [DATLAT]
1609 18:03:39.363632 Freq=800, CH1 RK0
1610 18:03:39.364044
1611 18:03:39.367102 DATLAT Default: 0xa
1612 18:03:39.367719 0, 0xFFFF, sum = 0
1613 18:03:39.370029 1, 0xFFFF, sum = 0
1614 18:03:39.370460 2, 0xFFFF, sum = 0
1615 18:03:39.373453 3, 0xFFFF, sum = 0
1616 18:03:39.373869 4, 0xFFFF, sum = 0
1617 18:03:39.376857 5, 0xFFFF, sum = 0
1618 18:03:39.377296 6, 0xFFFF, sum = 0
1619 18:03:39.380441 7, 0xFFFF, sum = 0
1620 18:03:39.380876 8, 0xFFFF, sum = 0
1621 18:03:39.383367 9, 0x0, sum = 1
1622 18:03:39.383823 10, 0x0, sum = 2
1623 18:03:39.386783 11, 0x0, sum = 3
1624 18:03:39.387249 12, 0x0, sum = 4
1625 18:03:39.387654 best_step = 10
1626 18:03:39.387960
1627 18:03:39.390351 ==
1628 18:03:39.393974 Dram Type= 6, Freq= 0, CH_1, rank 0
1629 18:03:39.397706 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1630 18:03:39.398233 ==
1631 18:03:39.398563 RX Vref Scan: 1
1632 18:03:39.398873
1633 18:03:39.400602 Set Vref Range= 32 -> 127
1634 18:03:39.401150
1635 18:03:39.403844 RX Vref 32 -> 127, step: 1
1636 18:03:39.404251
1637 18:03:39.407180 RX Delay -95 -> 252, step: 8
1638 18:03:39.407639
1639 18:03:39.410170 Set Vref, RX VrefLevel [Byte0]: 32
1640 18:03:39.414038 [Byte1]: 32
1641 18:03:39.414556
1642 18:03:39.417493 Set Vref, RX VrefLevel [Byte0]: 33
1643 18:03:39.420754 [Byte1]: 33
1644 18:03:39.421317
1645 18:03:39.424078 Set Vref, RX VrefLevel [Byte0]: 34
1646 18:03:39.427273 [Byte1]: 34
1647 18:03:39.427786
1648 18:03:39.430531 Set Vref, RX VrefLevel [Byte0]: 35
1649 18:03:39.433630 [Byte1]: 35
1650 18:03:39.437733
1651 18:03:39.438397 Set Vref, RX VrefLevel [Byte0]: 36
1652 18:03:39.440889 [Byte1]: 36
1653 18:03:39.445118
1654 18:03:39.445533 Set Vref, RX VrefLevel [Byte0]: 37
1655 18:03:39.448864 [Byte1]: 37
1656 18:03:39.453203
1657 18:03:39.453693 Set Vref, RX VrefLevel [Byte0]: 38
1658 18:03:39.456406 [Byte1]: 38
1659 18:03:39.461095
1660 18:03:39.461506 Set Vref, RX VrefLevel [Byte0]: 39
1661 18:03:39.464013 [Byte1]: 39
1662 18:03:39.468087
1663 18:03:39.468632 Set Vref, RX VrefLevel [Byte0]: 40
1664 18:03:39.471686 [Byte1]: 40
1665 18:03:39.475568
1666 18:03:39.476107 Set Vref, RX VrefLevel [Byte0]: 41
1667 18:03:39.479044 [Byte1]: 41
1668 18:03:39.483225
1669 18:03:39.483732 Set Vref, RX VrefLevel [Byte0]: 42
1670 18:03:39.486921 [Byte1]: 42
1671 18:03:39.490778
1672 18:03:39.491190 Set Vref, RX VrefLevel [Byte0]: 43
1673 18:03:39.494214 [Byte1]: 43
1674 18:03:39.498999
1675 18:03:39.499513 Set Vref, RX VrefLevel [Byte0]: 44
1676 18:03:39.502538 [Byte1]: 44
1677 18:03:39.506405
1678 18:03:39.506821 Set Vref, RX VrefLevel [Byte0]: 45
1679 18:03:39.509467 [Byte1]: 45
1680 18:03:39.513785
1681 18:03:39.514196 Set Vref, RX VrefLevel [Byte0]: 46
1682 18:03:39.517434 [Byte1]: 46
1683 18:03:39.521172
1684 18:03:39.521673 Set Vref, RX VrefLevel [Byte0]: 47
1685 18:03:39.524848 [Byte1]: 47
1686 18:03:39.529003
1687 18:03:39.529415 Set Vref, RX VrefLevel [Byte0]: 48
1688 18:03:39.532508 [Byte1]: 48
1689 18:03:39.536658
1690 18:03:39.537103 Set Vref, RX VrefLevel [Byte0]: 49
1691 18:03:39.540068 [Byte1]: 49
1692 18:03:39.543986
1693 18:03:39.544493 Set Vref, RX VrefLevel [Byte0]: 50
1694 18:03:39.547543 [Byte1]: 50
1695 18:03:39.552146
1696 18:03:39.552742 Set Vref, RX VrefLevel [Byte0]: 51
1697 18:03:39.555347 [Byte1]: 51
1698 18:03:39.559301
1699 18:03:39.559711 Set Vref, RX VrefLevel [Byte0]: 52
1700 18:03:39.562577 [Byte1]: 52
1701 18:03:39.567267
1702 18:03:39.567688 Set Vref, RX VrefLevel [Byte0]: 53
1703 18:03:39.569971 [Byte1]: 53
1704 18:03:39.574605
1705 18:03:39.575011 Set Vref, RX VrefLevel [Byte0]: 54
1706 18:03:39.577933 [Byte1]: 54
1707 18:03:39.582325
1708 18:03:39.582739 Set Vref, RX VrefLevel [Byte0]: 55
1709 18:03:39.585389 [Byte1]: 55
1710 18:03:39.589554
1711 18:03:39.589965 Set Vref, RX VrefLevel [Byte0]: 56
1712 18:03:39.592866 [Byte1]: 56
1713 18:03:39.597028
1714 18:03:39.597442 Set Vref, RX VrefLevel [Byte0]: 57
1715 18:03:39.600518 [Byte1]: 57
1716 18:03:39.604588
1717 18:03:39.604878 Set Vref, RX VrefLevel [Byte0]: 58
1718 18:03:39.608138 [Byte1]: 58
1719 18:03:39.612223
1720 18:03:39.612443 Set Vref, RX VrefLevel [Byte0]: 59
1721 18:03:39.615499 [Byte1]: 59
1722 18:03:39.619657
1723 18:03:39.619806 Set Vref, RX VrefLevel [Byte0]: 60
1724 18:03:39.623084 [Byte1]: 60
1725 18:03:39.628003
1726 18:03:39.628580 Set Vref, RX VrefLevel [Byte0]: 61
1727 18:03:39.630868 [Byte1]: 61
1728 18:03:39.635125
1729 18:03:39.635571 Set Vref, RX VrefLevel [Byte0]: 62
1730 18:03:39.638740 [Byte1]: 62
1731 18:03:39.642521
1732 18:03:39.643028 Set Vref, RX VrefLevel [Byte0]: 63
1733 18:03:39.646244 [Byte1]: 63
1734 18:03:39.650329
1735 18:03:39.650852 Set Vref, RX VrefLevel [Byte0]: 64
1736 18:03:39.654045 [Byte1]: 64
1737 18:03:39.658199
1738 18:03:39.658901 Set Vref, RX VrefLevel [Byte0]: 65
1739 18:03:39.661611 [Byte1]: 65
1740 18:03:39.665712
1741 18:03:39.666117 Set Vref, RX VrefLevel [Byte0]: 66
1742 18:03:39.669087 [Byte1]: 66
1743 18:03:39.673312
1744 18:03:39.673718 Set Vref, RX VrefLevel [Byte0]: 67
1745 18:03:39.676681 [Byte1]: 67
1746 18:03:39.680655
1747 18:03:39.681151 Set Vref, RX VrefLevel [Byte0]: 68
1748 18:03:39.684170 [Byte1]: 68
1749 18:03:39.688576
1750 18:03:39.689058 Set Vref, RX VrefLevel [Byte0]: 69
1751 18:03:39.692027 [Byte1]: 69
1752 18:03:39.696329
1753 18:03:39.696734 Set Vref, RX VrefLevel [Byte0]: 70
1754 18:03:39.699634 [Byte1]: 70
1755 18:03:39.703644
1756 18:03:39.704118 Set Vref, RX VrefLevel [Byte0]: 71
1757 18:03:39.707205 [Byte1]: 71
1758 18:03:39.711479
1759 18:03:39.711884 Set Vref, RX VrefLevel [Byte0]: 72
1760 18:03:39.714382 [Byte1]: 72
1761 18:03:39.718879
1762 18:03:39.719286 Set Vref, RX VrefLevel [Byte0]: 73
1763 18:03:39.722231 [Byte1]: 73
1764 18:03:39.726397
1765 18:03:39.726813 Set Vref, RX VrefLevel [Byte0]: 74
1766 18:03:39.729832 [Byte1]: 74
1767 18:03:39.733840
1768 18:03:39.734263 Set Vref, RX VrefLevel [Byte0]: 75
1769 18:03:39.737271 [Byte1]: 75
1770 18:03:39.742032
1771 18:03:39.742441 Set Vref, RX VrefLevel [Byte0]: 76
1772 18:03:39.745178 [Byte1]: 76
1773 18:03:39.749172
1774 18:03:39.749584 Set Vref, RX VrefLevel [Byte0]: 77
1775 18:03:39.752244 [Byte1]: 77
1776 18:03:39.757085
1777 18:03:39.757623 Set Vref, RX VrefLevel [Byte0]: 78
1778 18:03:39.760023 [Byte1]: 78
1779 18:03:39.764214
1780 18:03:39.764619 Set Vref, RX VrefLevel [Byte0]: 79
1781 18:03:39.767862 [Byte1]: 79
1782 18:03:39.771895
1783 18:03:39.772315 Final RX Vref Byte 0 = 65 to rank0
1784 18:03:39.775376 Final RX Vref Byte 1 = 57 to rank0
1785 18:03:39.778718 Final RX Vref Byte 0 = 65 to rank1
1786 18:03:39.782077 Final RX Vref Byte 1 = 57 to rank1==
1787 18:03:39.785680 Dram Type= 6, Freq= 0, CH_1, rank 0
1788 18:03:39.788648 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1789 18:03:39.792044 ==
1790 18:03:39.792465 DQS Delay:
1791 18:03:39.792891 DQS0 = 0, DQS1 = 0
1792 18:03:39.795497 DQM Delay:
1793 18:03:39.795916 DQM0 = 84, DQM1 = 73
1794 18:03:39.799085 DQ Delay:
1795 18:03:39.799506 DQ0 =92, DQ1 =76, DQ2 =76, DQ3 =84
1796 18:03:39.802408 DQ4 =80, DQ5 =96, DQ6 =92, DQ7 =76
1797 18:03:39.805877 DQ8 =60, DQ9 =60, DQ10 =76, DQ11 =72
1798 18:03:39.808702 DQ12 =84, DQ13 =80, DQ14 =80, DQ15 =76
1799 18:03:39.809151
1800 18:03:39.812534
1801 18:03:39.819062 [DQSOSCAuto] RK0, (LSB)MR18= 0x24f9, (MSB)MR19= 0x605, tDQSOscB0 = 412 ps tDQSOscB1 = 400 ps
1802 18:03:39.822889 CH1 RK0: MR19=605, MR18=24F9
1803 18:03:39.828906 CH1_RK0: MR19=0x605, MR18=0x24F9, DQSOSC=400, MR23=63, INC=92, DEC=61
1804 18:03:39.829370
1805 18:03:39.832199 ----->DramcWriteLeveling(PI) begin...
1806 18:03:39.832610 ==
1807 18:03:39.835876 Dram Type= 6, Freq= 0, CH_1, rank 1
1808 18:03:39.839269 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1809 18:03:39.839683 ==
1810 18:03:39.842353 Write leveling (Byte 0): 29 => 29
1811 18:03:39.845770 Write leveling (Byte 1): 30 => 30
1812 18:03:39.848789 DramcWriteLeveling(PI) end<-----
1813 18:03:39.849226
1814 18:03:39.849550 ==
1815 18:03:39.852338 Dram Type= 6, Freq= 0, CH_1, rank 1
1816 18:03:39.855796 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1817 18:03:39.856204 ==
1818 18:03:39.859411 [Gating] SW mode calibration
1819 18:03:39.865635 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1820 18:03:39.872571 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1821 18:03:39.876149 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1822 18:03:39.879446 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1823 18:03:39.882613 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 18:03:39.889466 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 18:03:39.892795 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 18:03:39.895692 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 18:03:39.902671 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 18:03:39.906156 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 18:03:39.909285 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 18:03:39.915914 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 18:03:39.919710 0 7 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1832 18:03:39.923426 0 7 12 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1833 18:03:39.929621 0 7 16 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1834 18:03:39.932485 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 18:03:39.936419 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 18:03:39.943073 0 7 28 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1837 18:03:39.945764 0 8 0 | B1->B0 | 2423 2323 | 1 0 | (0 0) (0 1)
1838 18:03:39.949438 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1839 18:03:39.956460 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 18:03:39.959778 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 18:03:39.963142 0 8 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1842 18:03:39.966270 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 18:03:39.973178 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1844 18:03:39.976342 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1845 18:03:39.979712 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1846 18:03:39.986152 0 9 4 | B1->B0 | 2323 2727 | 0 1 | (0 0) (0 0)
1847 18:03:39.989709 0 9 8 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 1)
1848 18:03:39.993076 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1849 18:03:40.000004 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1850 18:03:40.003115 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1851 18:03:40.006317 0 9 24 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1852 18:03:40.013048 0 9 28 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1853 18:03:40.016451 0 10 0 | B1->B0 | 3535 3434 | 0 0 | (0 0) (0 0)
1854 18:03:40.019790 0 10 4 | B1->B0 | 3030 2d2d | 1 0 | (1 0) (0 0)
1855 18:03:40.026312 0 10 8 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
1856 18:03:40.030020 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1857 18:03:40.033363 0 10 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1858 18:03:40.036885 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1859 18:03:40.043168 0 10 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1860 18:03:40.046707 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1861 18:03:40.049586 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1862 18:03:40.056710 0 11 4 | B1->B0 | 2626 3737 | 0 0 | (0 0) (0 0)
1863 18:03:40.059719 0 11 8 | B1->B0 | 3b3b 4646 | 1 0 | (1 1) (0 0)
1864 18:03:40.063138 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1865 18:03:40.070012 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1866 18:03:40.073755 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1867 18:03:40.076549 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1868 18:03:40.083447 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1869 18:03:40.086991 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1870 18:03:40.090198 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1871 18:03:40.093507 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1872 18:03:40.100210 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 18:03:40.103246 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 18:03:40.106731 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 18:03:40.113648 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 18:03:40.116854 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1877 18:03:40.120122 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1878 18:03:40.127052 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1879 18:03:40.130703 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1880 18:03:40.133868 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1881 18:03:40.140376 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1882 18:03:40.143617 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1883 18:03:40.147098 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1884 18:03:40.150816 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1885 18:03:40.157392 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1886 18:03:40.160905 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1887 18:03:40.163825 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1888 18:03:40.167642 Total UI for P1: 0, mck2ui 16
1889 18:03:40.170559 best dqsien dly found for B0: ( 0, 14, 4)
1890 18:03:40.173862 Total UI for P1: 0, mck2ui 16
1891 18:03:40.177341 best dqsien dly found for B1: ( 0, 14, 4)
1892 18:03:40.180771 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1893 18:03:40.184163 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1894 18:03:40.184602
1895 18:03:40.190452 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1896 18:03:40.193651 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1897 18:03:40.194066 [Gating] SW calibration Done
1898 18:03:40.197138 ==
1899 18:03:40.200808 Dram Type= 6, Freq= 0, CH_1, rank 1
1900 18:03:40.204146 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1901 18:03:40.204569 ==
1902 18:03:40.204893 RX Vref Scan: 0
1903 18:03:40.205247
1904 18:03:40.207072 RX Vref 0 -> 0, step: 1
1905 18:03:40.207480
1906 18:03:40.210708 RX Delay -130 -> 252, step: 16
1907 18:03:40.214347 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1908 18:03:40.217009 iDelay=206, Bit 1, Center 77 (-34 ~ 189) 224
1909 18:03:40.220929 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1910 18:03:40.227488 iDelay=206, Bit 3, Center 77 (-34 ~ 189) 224
1911 18:03:40.230740 iDelay=206, Bit 4, Center 77 (-34 ~ 189) 224
1912 18:03:40.234220 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1913 18:03:40.237340 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1914 18:03:40.241123 iDelay=206, Bit 7, Center 77 (-34 ~ 189) 224
1915 18:03:40.247654 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1916 18:03:40.250825 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1917 18:03:40.254412 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
1918 18:03:40.257310 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1919 18:03:40.260766 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1920 18:03:40.267756 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1921 18:03:40.271232 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1922 18:03:40.274247 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1923 18:03:40.274755 ==
1924 18:03:40.277723 Dram Type= 6, Freq= 0, CH_1, rank 1
1925 18:03:40.281102 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1926 18:03:40.281561 ==
1927 18:03:40.284164 DQS Delay:
1928 18:03:40.284679 DQS0 = 0, DQS1 = 0
1929 18:03:40.287651 DQM Delay:
1930 18:03:40.288070 DQM0 = 81, DQM1 = 78
1931 18:03:40.288399 DQ Delay:
1932 18:03:40.291263 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1933 18:03:40.294436 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1934 18:03:40.297691 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1935 18:03:40.301254 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1936 18:03:40.301669
1937 18:03:40.301995
1938 18:03:40.302300 ==
1939 18:03:40.304747 Dram Type= 6, Freq= 0, CH_1, rank 1
1940 18:03:40.311301 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1941 18:03:40.311713 ==
1942 18:03:40.312039
1943 18:03:40.312341
1944 18:03:40.312634 TX Vref Scan disable
1945 18:03:40.314675 == TX Byte 0 ==
1946 18:03:40.318031 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1947 18:03:40.321638 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1948 18:03:40.324691 == TX Byte 1 ==
1949 18:03:40.328110 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1950 18:03:40.331249 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1951 18:03:40.334919 ==
1952 18:03:40.335335 Dram Type= 6, Freq= 0, CH_1, rank 1
1953 18:03:40.342005 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1954 18:03:40.342421 ==
1955 18:03:40.353618 TX Vref=22, minBit 0, minWin=27, winSum=444
1956 18:03:40.356903 TX Vref=24, minBit 10, minWin=27, winSum=449
1957 18:03:40.360241 TX Vref=26, minBit 1, minWin=27, winSum=447
1958 18:03:40.363841 TX Vref=28, minBit 0, minWin=28, winSum=453
1959 18:03:40.366718 TX Vref=30, minBit 0, minWin=28, winSum=453
1960 18:03:40.370663 TX Vref=32, minBit 1, minWin=27, winSum=450
1961 18:03:40.376855 [TxChooseVref] Worse bit 0, Min win 28, Win sum 453, Final Vref 28
1962 18:03:40.377326
1963 18:03:40.380652 Final TX Range 1 Vref 28
1964 18:03:40.381118
1965 18:03:40.381456 ==
1966 18:03:40.384220 Dram Type= 6, Freq= 0, CH_1, rank 1
1967 18:03:40.387204 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1968 18:03:40.387622 ==
1969 18:03:40.387953
1970 18:03:40.388259
1971 18:03:40.390542 TX Vref Scan disable
1972 18:03:40.393607 == TX Byte 0 ==
1973 18:03:40.397070 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1974 18:03:40.400698 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1975 18:03:40.404667 == TX Byte 1 ==
1976 18:03:40.407343 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1977 18:03:40.410847 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1978 18:03:40.411267
1979 18:03:40.414304 [DATLAT]
1980 18:03:40.414716 Freq=800, CH1 RK1
1981 18:03:40.415049
1982 18:03:40.417663 DATLAT Default: 0xa
1983 18:03:40.418078 0, 0xFFFF, sum = 0
1984 18:03:40.420597 1, 0xFFFF, sum = 0
1985 18:03:40.421060 2, 0xFFFF, sum = 0
1986 18:03:40.423911 3, 0xFFFF, sum = 0
1987 18:03:40.424332 4, 0xFFFF, sum = 0
1988 18:03:40.427735 5, 0xFFFF, sum = 0
1989 18:03:40.428158 6, 0xFFFF, sum = 0
1990 18:03:40.430573 7, 0xFFFF, sum = 0
1991 18:03:40.430994 8, 0xFFFF, sum = 0
1992 18:03:40.434065 9, 0x0, sum = 1
1993 18:03:40.434501 10, 0x0, sum = 2
1994 18:03:40.437673 11, 0x0, sum = 3
1995 18:03:40.438181 12, 0x0, sum = 4
1996 18:03:40.441388 best_step = 10
1997 18:03:40.441908
1998 18:03:40.442243 ==
1999 18:03:40.443997 Dram Type= 6, Freq= 0, CH_1, rank 1
2000 18:03:40.447583 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2001 18:03:40.448020 ==
2002 18:03:40.451245 RX Vref Scan: 0
2003 18:03:40.451791
2004 18:03:40.452222 RX Vref 0 -> 0, step: 1
2005 18:03:40.452592
2006 18:03:40.454449 RX Delay -95 -> 252, step: 8
2007 18:03:40.457384 iDelay=201, Bit 0, Center 80 (-31 ~ 192) 224
2008 18:03:40.464514 iDelay=201, Bit 1, Center 76 (-39 ~ 192) 232
2009 18:03:40.467431 iDelay=201, Bit 2, Center 68 (-47 ~ 184) 232
2010 18:03:40.470983 iDelay=201, Bit 3, Center 76 (-39 ~ 192) 232
2011 18:03:40.474438 iDelay=201, Bit 4, Center 80 (-31 ~ 192) 224
2012 18:03:40.477623 iDelay=201, Bit 5, Center 88 (-23 ~ 200) 224
2013 18:03:40.484375 iDelay=201, Bit 6, Center 88 (-23 ~ 200) 224
2014 18:03:40.487875 iDelay=201, Bit 7, Center 76 (-31 ~ 184) 216
2015 18:03:40.491796 iDelay=201, Bit 8, Center 64 (-55 ~ 184) 240
2016 18:03:40.494671 iDelay=201, Bit 9, Center 64 (-47 ~ 176) 224
2017 18:03:40.497870 iDelay=201, Bit 10, Center 76 (-39 ~ 192) 232
2018 18:03:40.501408 iDelay=201, Bit 11, Center 68 (-47 ~ 184) 232
2019 18:03:40.508149 iDelay=201, Bit 12, Center 80 (-31 ~ 192) 224
2020 18:03:40.511356 iDelay=201, Bit 13, Center 84 (-31 ~ 200) 232
2021 18:03:40.514810 iDelay=201, Bit 14, Center 84 (-31 ~ 200) 232
2022 18:03:40.518171 iDelay=201, Bit 15, Center 84 (-31 ~ 200) 232
2023 18:03:40.518626 ==
2024 18:03:40.521315 Dram Type= 6, Freq= 0, CH_1, rank 1
2025 18:03:40.527804 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2026 18:03:40.528226 ==
2027 18:03:40.528558 DQS Delay:
2028 18:03:40.531587 DQS0 = 0, DQS1 = 0
2029 18:03:40.532004 DQM Delay:
2030 18:03:40.532437 DQM0 = 79, DQM1 = 75
2031 18:03:40.534957 DQ Delay:
2032 18:03:40.538407 DQ0 =80, DQ1 =76, DQ2 =68, DQ3 =76
2033 18:03:40.541398 DQ4 =80, DQ5 =88, DQ6 =88, DQ7 =76
2034 18:03:40.544783 DQ8 =64, DQ9 =64, DQ10 =76, DQ11 =68
2035 18:03:40.548704 DQ12 =80, DQ13 =84, DQ14 =84, DQ15 =84
2036 18:03:40.549343
2037 18:03:40.549692
2038 18:03:40.554872 [DQSOSCAuto] RK1, (LSB)MR18= 0x212c, (MSB)MR19= 0x606, tDQSOscB0 = 398 ps tDQSOscB1 = 401 ps
2039 18:03:40.558280 CH1 RK1: MR19=606, MR18=212C
2040 18:03:40.565030 CH1_RK1: MR19=0x606, MR18=0x212C, DQSOSC=398, MR23=63, INC=93, DEC=62
2041 18:03:40.567931 [RxdqsGatingPostProcess] freq 800
2042 18:03:40.571483 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2043 18:03:40.575074 Pre-setting of DQS Precalculation
2044 18:03:40.581469 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2045 18:03:40.588653 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2046 18:03:40.595167 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2047 18:03:40.595580
2048 18:03:40.595906
2049 18:03:40.598237 [Calibration Summary] 1600 Mbps
2050 18:03:40.598652 CH 0, Rank 0
2051 18:03:40.602142 SW Impedance : PASS
2052 18:03:40.602587 DUTY Scan : NO K
2053 18:03:40.605081 ZQ Calibration : PASS
2054 18:03:40.608370 Jitter Meter : NO K
2055 18:03:40.608782 CBT Training : PASS
2056 18:03:40.611836 Write leveling : PASS
2057 18:03:40.615402 RX DQS gating : PASS
2058 18:03:40.615814 RX DQ/DQS(RDDQC) : PASS
2059 18:03:40.618681 TX DQ/DQS : PASS
2060 18:03:40.621791 RX DATLAT : PASS
2061 18:03:40.622244 RX DQ/DQS(Engine): PASS
2062 18:03:40.625243 TX OE : NO K
2063 18:03:40.625654 All Pass.
2064 18:03:40.625978
2065 18:03:40.628737 CH 0, Rank 1
2066 18:03:40.629186 SW Impedance : PASS
2067 18:03:40.631739 DUTY Scan : NO K
2068 18:03:40.635003 ZQ Calibration : PASS
2069 18:03:40.635416 Jitter Meter : NO K
2070 18:03:40.638429 CBT Training : PASS
2071 18:03:40.638841 Write leveling : PASS
2072 18:03:40.642059 RX DQS gating : PASS
2073 18:03:40.645427 RX DQ/DQS(RDDQC) : PASS
2074 18:03:40.645853 TX DQ/DQS : PASS
2075 18:03:40.648413 RX DATLAT : PASS
2076 18:03:40.652322 RX DQ/DQS(Engine): PASS
2077 18:03:40.652761 TX OE : NO K
2078 18:03:40.655411 All Pass.
2079 18:03:40.655821
2080 18:03:40.656145 CH 1, Rank 0
2081 18:03:40.658914 SW Impedance : PASS
2082 18:03:40.659425 DUTY Scan : NO K
2083 18:03:40.662447 ZQ Calibration : PASS
2084 18:03:40.665230 Jitter Meter : NO K
2085 18:03:40.665645 CBT Training : PASS
2086 18:03:40.668576 Write leveling : PASS
2087 18:03:40.672239 RX DQS gating : PASS
2088 18:03:40.672651 RX DQ/DQS(RDDQC) : PASS
2089 18:03:40.675398 TX DQ/DQS : PASS
2090 18:03:40.675810 RX DATLAT : PASS
2091 18:03:40.678953 RX DQ/DQS(Engine): PASS
2092 18:03:40.682484 TX OE : NO K
2093 18:03:40.682896 All Pass.
2094 18:03:40.683224
2095 18:03:40.683528 CH 1, Rank 1
2096 18:03:40.685423 SW Impedance : PASS
2097 18:03:40.688897 DUTY Scan : NO K
2098 18:03:40.689340 ZQ Calibration : PASS
2099 18:03:40.692436 Jitter Meter : NO K
2100 18:03:40.695822 CBT Training : PASS
2101 18:03:40.696235 Write leveling : PASS
2102 18:03:40.698808 RX DQS gating : PASS
2103 18:03:40.702194 RX DQ/DQS(RDDQC) : PASS
2104 18:03:40.702607 TX DQ/DQS : PASS
2105 18:03:40.705678 RX DATLAT : PASS
2106 18:03:40.708824 RX DQ/DQS(Engine): PASS
2107 18:03:40.709356 TX OE : NO K
2108 18:03:40.709695 All Pass.
2109 18:03:40.712232
2110 18:03:40.712645 DramC Write-DBI off
2111 18:03:40.715763 PER_BANK_REFRESH: Hybrid Mode
2112 18:03:40.716172 TX_TRACKING: ON
2113 18:03:40.719182 [GetDramInforAfterCalByMRR] Vendor 6.
2114 18:03:40.722543 [GetDramInforAfterCalByMRR] Revision 606.
2115 18:03:40.728970 [GetDramInforAfterCalByMRR] Revision 2 0.
2116 18:03:40.729584 MR0 0x3b3b
2117 18:03:40.729925 MR8 0x5151
2118 18:03:40.732213 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2119 18:03:40.732625
2120 18:03:40.735799 MR0 0x3b3b
2121 18:03:40.736325 MR8 0x5151
2122 18:03:40.739282 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2123 18:03:40.739697
2124 18:03:40.749141 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2125 18:03:40.752282 [FAST_K] Save calibration result to emmc
2126 18:03:40.755908 [FAST_K] Save calibration result to emmc
2127 18:03:40.759492 dram_init: config_dvfs: 1
2128 18:03:40.762970 dramc_set_vcore_voltage set vcore to 662500
2129 18:03:40.763387 Read voltage for 1200, 2
2130 18:03:40.765892 Vio18 = 0
2131 18:03:40.766328 Vcore = 662500
2132 18:03:40.766655 Vdram = 0
2133 18:03:40.769233 Vddq = 0
2134 18:03:40.769648 Vmddr = 0
2135 18:03:40.772679 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2136 18:03:40.779170 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2137 18:03:40.782893 MEM_TYPE=3, freq_sel=15
2138 18:03:40.785942 sv_algorithm_assistance_LP4_1600
2139 18:03:40.789410 ============ PULL DRAM RESETB DOWN ============
2140 18:03:40.793016 ========== PULL DRAM RESETB DOWN end =========
2141 18:03:40.795822 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2142 18:03:40.799285 ===================================
2143 18:03:40.802828 LPDDR4 DRAM CONFIGURATION
2144 18:03:40.805829 ===================================
2145 18:03:40.809231 EX_ROW_EN[0] = 0x0
2146 18:03:40.809642 EX_ROW_EN[1] = 0x0
2147 18:03:40.813303 LP4Y_EN = 0x0
2148 18:03:40.813717 WORK_FSP = 0x0
2149 18:03:40.816126 WL = 0x4
2150 18:03:40.816536 RL = 0x4
2151 18:03:40.819562 BL = 0x2
2152 18:03:40.820178 RPST = 0x0
2153 18:03:40.823289 RD_PRE = 0x0
2154 18:03:40.823700 WR_PRE = 0x1
2155 18:03:40.825970 WR_PST = 0x0
2156 18:03:40.826414 DBI_WR = 0x0
2157 18:03:40.829648 DBI_RD = 0x0
2158 18:03:40.830098 OTF = 0x1
2159 18:03:40.833110 ===================================
2160 18:03:40.836045 ===================================
2161 18:03:40.839501 ANA top config
2162 18:03:40.843083 ===================================
2163 18:03:40.846223 DLL_ASYNC_EN = 0
2164 18:03:40.846643 ALL_SLAVE_EN = 0
2165 18:03:40.849717 NEW_RANK_MODE = 1
2166 18:03:40.853037 DLL_IDLE_MODE = 1
2167 18:03:40.856359 LP45_APHY_COMB_EN = 1
2168 18:03:40.856768 TX_ODT_DIS = 1
2169 18:03:40.859636 NEW_8X_MODE = 1
2170 18:03:40.863022 ===================================
2171 18:03:40.866635 ===================================
2172 18:03:40.869871 data_rate = 2400
2173 18:03:40.873143 CKR = 1
2174 18:03:40.876651 DQ_P2S_RATIO = 8
2175 18:03:40.879689 ===================================
2176 18:03:40.880205 CA_P2S_RATIO = 8
2177 18:03:40.883549 DQ_CA_OPEN = 0
2178 18:03:40.887083 DQ_SEMI_OPEN = 0
2179 18:03:40.889687 CA_SEMI_OPEN = 0
2180 18:03:40.893276 CA_FULL_RATE = 0
2181 18:03:40.896867 DQ_CKDIV4_EN = 0
2182 18:03:40.897324 CA_CKDIV4_EN = 0
2183 18:03:40.900434 CA_PREDIV_EN = 0
2184 18:03:40.903449 PH8_DLY = 17
2185 18:03:40.906584 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2186 18:03:40.910102 DQ_AAMCK_DIV = 4
2187 18:03:40.913834 CA_AAMCK_DIV = 4
2188 18:03:40.914251 CA_ADMCK_DIV = 4
2189 18:03:40.916798 DQ_TRACK_CA_EN = 0
2190 18:03:40.920312 CA_PICK = 1200
2191 18:03:40.923597 CA_MCKIO = 1200
2192 18:03:40.927334 MCKIO_SEMI = 0
2193 18:03:40.929972 PLL_FREQ = 2366
2194 18:03:40.933496 DQ_UI_PI_RATIO = 32
2195 18:03:40.933905 CA_UI_PI_RATIO = 0
2196 18:03:40.937143 ===================================
2197 18:03:40.940339 ===================================
2198 18:03:40.943823 memory_type:LPDDR4
2199 18:03:40.947331 GP_NUM : 10
2200 18:03:40.947839 SRAM_EN : 1
2201 18:03:40.949937 MD32_EN : 0
2202 18:03:40.953666 ===================================
2203 18:03:40.957374 [ANA_INIT] >>>>>>>>>>>>>>
2204 18:03:40.957912 <<<<<< [CONFIGURE PHASE]: ANA_TX
2205 18:03:40.960668 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2206 18:03:40.963520 ===================================
2207 18:03:40.967000 data_rate = 2400,PCW = 0X5b00
2208 18:03:40.970090 ===================================
2209 18:03:40.974032 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2210 18:03:40.980466 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2211 18:03:40.987104 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2212 18:03:40.990834 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2213 18:03:40.993724 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2214 18:03:40.997375 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2215 18:03:41.000673 [ANA_INIT] flow start
2216 18:03:41.001250 [ANA_INIT] PLL >>>>>>>>
2217 18:03:41.003918 [ANA_INIT] PLL <<<<<<<<
2218 18:03:41.007435 [ANA_INIT] MIDPI >>>>>>>>
2219 18:03:41.007950 [ANA_INIT] MIDPI <<<<<<<<
2220 18:03:41.010614 [ANA_INIT] DLL >>>>>>>>
2221 18:03:41.014047 [ANA_INIT] DLL <<<<<<<<
2222 18:03:41.014459 [ANA_INIT] flow end
2223 18:03:41.017685 ============ LP4 DIFF to SE enter ============
2224 18:03:41.023961 ============ LP4 DIFF to SE exit ============
2225 18:03:41.024375 [ANA_INIT] <<<<<<<<<<<<<
2226 18:03:41.027483 [Flow] Enable top DCM control >>>>>
2227 18:03:41.030683 [Flow] Enable top DCM control <<<<<
2228 18:03:41.034560 Enable DLL master slave shuffle
2229 18:03:41.041042 ==============================================================
2230 18:03:41.041552 Gating Mode config
2231 18:03:41.048103 ==============================================================
2232 18:03:41.051045 Config description:
2233 18:03:41.057580 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2234 18:03:41.064518 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2235 18:03:41.070994 SELPH_MODE 0: By rank 1: By Phase
2236 18:03:41.077765 ==============================================================
2237 18:03:41.078313 GAT_TRACK_EN = 1
2238 18:03:41.081213 RX_GATING_MODE = 2
2239 18:03:41.084750 RX_GATING_TRACK_MODE = 2
2240 18:03:41.087681 SELPH_MODE = 1
2241 18:03:41.091283 PICG_EARLY_EN = 1
2242 18:03:41.094868 VALID_LAT_VALUE = 1
2243 18:03:41.101395 ==============================================================
2244 18:03:41.105508 Enter into Gating configuration >>>>
2245 18:03:41.107763 Exit from Gating configuration <<<<
2246 18:03:41.108190 Enter into DVFS_PRE_config >>>>>
2247 18:03:41.121844 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2248 18:03:41.125008 Exit from DVFS_PRE_config <<<<<
2249 18:03:41.127839 Enter into PICG configuration >>>>
2250 18:03:41.131840 Exit from PICG configuration <<<<
2251 18:03:41.132385 [RX_INPUT] configuration >>>>>
2252 18:03:41.134940 [RX_INPUT] configuration <<<<<
2253 18:03:41.141658 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2254 18:03:41.144739 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2255 18:03:41.151534 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2256 18:03:41.158045 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2257 18:03:41.165381 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2258 18:03:41.171674 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2259 18:03:41.175209 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2260 18:03:41.178743 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2261 18:03:41.181509 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2262 18:03:41.188291 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2263 18:03:41.191942 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2264 18:03:41.195474 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2265 18:03:41.198387 ===================================
2266 18:03:41.201910 LPDDR4 DRAM CONFIGURATION
2267 18:03:41.205242 ===================================
2268 18:03:41.205696 EX_ROW_EN[0] = 0x0
2269 18:03:41.208438 EX_ROW_EN[1] = 0x0
2270 18:03:41.211719 LP4Y_EN = 0x0
2271 18:03:41.212352 WORK_FSP = 0x0
2272 18:03:41.215181 WL = 0x4
2273 18:03:41.215614 RL = 0x4
2274 18:03:41.218175 BL = 0x2
2275 18:03:41.218599 RPST = 0x0
2276 18:03:41.221574 RD_PRE = 0x0
2277 18:03:41.222004 WR_PRE = 0x1
2278 18:03:41.225180 WR_PST = 0x0
2279 18:03:41.225603 DBI_WR = 0x0
2280 18:03:41.228466 DBI_RD = 0x0
2281 18:03:41.228893 OTF = 0x1
2282 18:03:41.231928 ===================================
2283 18:03:41.235427 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2284 18:03:41.242340 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2285 18:03:41.245381 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2286 18:03:41.248759 ===================================
2287 18:03:41.251720 LPDDR4 DRAM CONFIGURATION
2288 18:03:41.255443 ===================================
2289 18:03:41.255893 EX_ROW_EN[0] = 0x10
2290 18:03:41.258833 EX_ROW_EN[1] = 0x0
2291 18:03:41.259325 LP4Y_EN = 0x0
2292 18:03:41.262337 WORK_FSP = 0x0
2293 18:03:41.262873 WL = 0x4
2294 18:03:41.265272 RL = 0x4
2295 18:03:41.265767 BL = 0x2
2296 18:03:41.268918 RPST = 0x0
2297 18:03:41.269437 RD_PRE = 0x0
2298 18:03:41.271820 WR_PRE = 0x1
2299 18:03:41.272221 WR_PST = 0x0
2300 18:03:41.275369 DBI_WR = 0x0
2301 18:03:41.275793 DBI_RD = 0x0
2302 18:03:41.278789 OTF = 0x1
2303 18:03:41.281919 ===================================
2304 18:03:41.289075 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2305 18:03:41.289371 ==
2306 18:03:41.292129 Dram Type= 6, Freq= 0, CH_0, rank 0
2307 18:03:41.295566 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2308 18:03:41.295898 ==
2309 18:03:41.298785 [Duty_Offset_Calibration]
2310 18:03:41.299108 B0:2 B1:-1 CA:1
2311 18:03:41.299362
2312 18:03:41.302485 [DutyScan_Calibration_Flow] k_type=0
2313 18:03:41.312043
2314 18:03:41.312461 ==CLK 0==
2315 18:03:41.315283 Final CLK duty delay cell = -4
2316 18:03:41.318672 [-4] MAX Duty = 5031%(X100), DQS PI = 4
2317 18:03:41.322380 [-4] MIN Duty = 4875%(X100), DQS PI = 30
2318 18:03:41.325796 [-4] AVG Duty = 4953%(X100)
2319 18:03:41.326119
2320 18:03:41.328673 CH0 CLK Duty spec in!! Max-Min= 156%
2321 18:03:41.332602 [DutyScan_Calibration_Flow] ====Done====
2322 18:03:41.333055
2323 18:03:41.335451 [DutyScan_Calibration_Flow] k_type=1
2324 18:03:41.350957
2325 18:03:41.351432 ==DQS 0 ==
2326 18:03:41.354361 Final DQS duty delay cell = 0
2327 18:03:41.357712 [0] MAX Duty = 5124%(X100), DQS PI = 44
2328 18:03:41.361400 [0] MIN Duty = 5000%(X100), DQS PI = 12
2329 18:03:41.361809 [0] AVG Duty = 5062%(X100)
2330 18:03:41.362131
2331 18:03:41.364598 ==DQS 1 ==
2332 18:03:41.367884 Final DQS duty delay cell = -4
2333 18:03:41.371423 [-4] MAX Duty = 5124%(X100), DQS PI = 6
2334 18:03:41.374437 [-4] MIN Duty = 5000%(X100), DQS PI = 44
2335 18:03:41.374842 [-4] AVG Duty = 5062%(X100)
2336 18:03:41.377818
2337 18:03:41.381540 CH0 DQS 0 Duty spec in!! Max-Min= 124%
2338 18:03:41.381944
2339 18:03:41.384839 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2340 18:03:41.387979 [DutyScan_Calibration_Flow] ====Done====
2341 18:03:41.388382
2342 18:03:41.391112 [DutyScan_Calibration_Flow] k_type=3
2343 18:03:41.407658
2344 18:03:41.408063 ==DQM 0 ==
2345 18:03:41.411230 Final DQM duty delay cell = 0
2346 18:03:41.414484 [0] MAX Duty = 5031%(X100), DQS PI = 54
2347 18:03:41.418045 [0] MIN Duty = 4907%(X100), DQS PI = 2
2348 18:03:41.418472 [0] AVG Duty = 4969%(X100)
2349 18:03:41.421374
2350 18:03:41.421857 ==DQM 1 ==
2351 18:03:41.424805 Final DQM duty delay cell = 0
2352 18:03:41.428424 [0] MAX Duty = 5156%(X100), DQS PI = 62
2353 18:03:41.431045 [0] MIN Duty = 4969%(X100), DQS PI = 8
2354 18:03:41.431528 [0] AVG Duty = 5062%(X100)
2355 18:03:41.431854
2356 18:03:41.438009 CH0 DQM 0 Duty spec in!! Max-Min= 124%
2357 18:03:41.438505
2358 18:03:41.441473 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2359 18:03:41.444388 [DutyScan_Calibration_Flow] ====Done====
2360 18:03:41.444812
2361 18:03:41.448042 [DutyScan_Calibration_Flow] k_type=2
2362 18:03:41.463789
2363 18:03:41.464292 ==DQ 0 ==
2364 18:03:41.467077 Final DQ duty delay cell = -4
2365 18:03:41.470217 [-4] MAX Duty = 5031%(X100), DQS PI = 0
2366 18:03:41.473282 [-4] MIN Duty = 4876%(X100), DQS PI = 12
2367 18:03:41.476748 [-4] AVG Duty = 4953%(X100)
2368 18:03:41.477283
2369 18:03:41.477787 ==DQ 1 ==
2370 18:03:41.480546 Final DQ duty delay cell = 0
2371 18:03:41.483485 [0] MAX Duty = 5031%(X100), DQS PI = 18
2372 18:03:41.487224 [0] MIN Duty = 4907%(X100), DQS PI = 46
2373 18:03:41.487633 [0] AVG Duty = 4969%(X100)
2374 18:03:41.487958
2375 18:03:41.490780 CH0 DQ 0 Duty spec in!! Max-Min= 155%
2376 18:03:41.493570
2377 18:03:41.497503 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2378 18:03:41.500771 [DutyScan_Calibration_Flow] ====Done====
2379 18:03:41.501484 ==
2380 18:03:41.503993 Dram Type= 6, Freq= 0, CH_1, rank 0
2381 18:03:41.507045 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2382 18:03:41.507458 ==
2383 18:03:41.510232 [Duty_Offset_Calibration]
2384 18:03:41.510640 B0:1 B1:1 CA:2
2385 18:03:41.510968
2386 18:03:41.513482 [DutyScan_Calibration_Flow] k_type=0
2387 18:03:41.523945
2388 18:03:41.524393 ==CLK 0==
2389 18:03:41.526822 Final CLK duty delay cell = 0
2390 18:03:41.530221 [0] MAX Duty = 5156%(X100), DQS PI = 24
2391 18:03:41.533658 [0] MIN Duty = 4938%(X100), DQS PI = 48
2392 18:03:41.534066 [0] AVG Duty = 5047%(X100)
2393 18:03:41.537155
2394 18:03:41.537561 CH1 CLK Duty spec in!! Max-Min= 218%
2395 18:03:41.543840 [DutyScan_Calibration_Flow] ====Done====
2396 18:03:41.544344
2397 18:03:41.546855 [DutyScan_Calibration_Flow] k_type=1
2398 18:03:41.562999
2399 18:03:41.563519 ==DQS 0 ==
2400 18:03:41.566375 Final DQS duty delay cell = 0
2401 18:03:41.569760 [0] MAX Duty = 5031%(X100), DQS PI = 18
2402 18:03:41.573190 [0] MIN Duty = 4813%(X100), DQS PI = 50
2403 18:03:41.573602 [0] AVG Duty = 4922%(X100)
2404 18:03:41.576787
2405 18:03:41.577245 ==DQS 1 ==
2406 18:03:41.579720 Final DQS duty delay cell = 0
2407 18:03:41.583062 [0] MAX Duty = 5062%(X100), DQS PI = 36
2408 18:03:41.586951 [0] MIN Duty = 4907%(X100), DQS PI = 0
2409 18:03:41.587468 [0] AVG Duty = 4984%(X100)
2410 18:03:41.587807
2411 18:03:41.593461 CH1 DQS 0 Duty spec in!! Max-Min= 218%
2412 18:03:41.593879
2413 18:03:41.596943 CH1 DQS 1 Duty spec in!! Max-Min= 155%
2414 18:03:41.600508 [DutyScan_Calibration_Flow] ====Done====
2415 18:03:41.601070
2416 18:03:41.603128 [DutyScan_Calibration_Flow] k_type=3
2417 18:03:41.619675
2418 18:03:41.620183 ==DQM 0 ==
2419 18:03:41.623341 Final DQM duty delay cell = 0
2420 18:03:41.626404 [0] MAX Duty = 5093%(X100), DQS PI = 18
2421 18:03:41.629350 [0] MIN Duty = 4875%(X100), DQS PI = 50
2422 18:03:41.629768 [0] AVG Duty = 4984%(X100)
2423 18:03:41.633030
2424 18:03:41.633549 ==DQM 1 ==
2425 18:03:41.636154 Final DQM duty delay cell = 0
2426 18:03:41.639571 [0] MAX Duty = 5156%(X100), DQS PI = 62
2427 18:03:41.643331 [0] MIN Duty = 4938%(X100), DQS PI = 22
2428 18:03:41.643858 [0] AVG Duty = 5047%(X100)
2429 18:03:41.646506
2430 18:03:41.649530 CH1 DQM 0 Duty spec in!! Max-Min= 218%
2431 18:03:41.649952
2432 18:03:41.653020 CH1 DQM 1 Duty spec in!! Max-Min= 218%
2433 18:03:41.655894 [DutyScan_Calibration_Flow] ====Done====
2434 18:03:41.656339
2435 18:03:41.659480 [DutyScan_Calibration_Flow] k_type=2
2436 18:03:41.675869
2437 18:03:41.676350 ==DQ 0 ==
2438 18:03:41.679411 Final DQ duty delay cell = 0
2439 18:03:41.682950 [0] MAX Duty = 5093%(X100), DQS PI = 18
2440 18:03:41.686011 [0] MIN Duty = 4907%(X100), DQS PI = 50
2441 18:03:41.686425 [0] AVG Duty = 5000%(X100)
2442 18:03:41.686760
2443 18:03:41.689649 ==DQ 1 ==
2444 18:03:41.693146 Final DQ duty delay cell = 0
2445 18:03:41.695973 [0] MAX Duty = 5093%(X100), DQS PI = 10
2446 18:03:41.699541 [0] MIN Duty = 5000%(X100), DQS PI = 2
2447 18:03:41.699956 [0] AVG Duty = 5046%(X100)
2448 18:03:41.700285
2449 18:03:41.702537 CH1 DQ 0 Duty spec in!! Max-Min= 186%
2450 18:03:41.702952
2451 18:03:41.705993 CH1 DQ 1 Duty spec in!! Max-Min= 93%
2452 18:03:41.712870 [DutyScan_Calibration_Flow] ====Done====
2453 18:03:41.716361 nWR fixed to 30
2454 18:03:41.716774 [ModeRegInit_LP4] CH0 RK0
2455 18:03:41.719645 [ModeRegInit_LP4] CH0 RK1
2456 18:03:41.722554 [ModeRegInit_LP4] CH1 RK0
2457 18:03:41.722965 [ModeRegInit_LP4] CH1 RK1
2458 18:03:41.726135 match AC timing 7
2459 18:03:41.729458 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2460 18:03:41.732786 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2461 18:03:41.739589 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2462 18:03:41.742935 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2463 18:03:41.749553 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2464 18:03:41.749973 ==
2465 18:03:41.752881 Dram Type= 6, Freq= 0, CH_0, rank 0
2466 18:03:41.756483 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2467 18:03:41.756907 ==
2468 18:03:41.763291 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2469 18:03:41.766030 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2470 18:03:41.776375 [CA 0] Center 40 (10~71) winsize 62
2471 18:03:41.779646 [CA 1] Center 39 (9~70) winsize 62
2472 18:03:41.782873 [CA 2] Center 36 (6~67) winsize 62
2473 18:03:41.785695 [CA 3] Center 36 (5~67) winsize 63
2474 18:03:41.789446 [CA 4] Center 35 (5~65) winsize 61
2475 18:03:41.793148 [CA 5] Center 34 (4~65) winsize 62
2476 18:03:41.793698
2477 18:03:41.796156 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2478 18:03:41.796612
2479 18:03:41.799102 [CATrainingPosCal] consider 1 rank data
2480 18:03:41.802577 u2DelayCellTimex100 = 270/100 ps
2481 18:03:41.806104 CA0 delay=40 (10~71),Diff = 6 PI (28 cell)
2482 18:03:41.809622 CA1 delay=39 (9~70),Diff = 5 PI (24 cell)
2483 18:03:41.815824 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2484 18:03:41.819606 CA3 delay=36 (5~67),Diff = 2 PI (9 cell)
2485 18:03:41.822718 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
2486 18:03:41.826028 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
2487 18:03:41.826539
2488 18:03:41.829447 CA PerBit enable=1, Macro0, CA PI delay=34
2489 18:03:41.829866
2490 18:03:41.832715 [CBTSetCACLKResult] CA Dly = 34
2491 18:03:41.833173 CS Dly: 7 (0~38)
2492 18:03:41.833513 ==
2493 18:03:41.835931 Dram Type= 6, Freq= 0, CH_0, rank 1
2494 18:03:41.842923 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2495 18:03:41.843339 ==
2496 18:03:41.846398 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2497 18:03:41.852859 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2498 18:03:41.862094 [CA 0] Center 39 (9~70) winsize 62
2499 18:03:41.865044 [CA 1] Center 40 (10~70) winsize 61
2500 18:03:41.868572 [CA 2] Center 36 (6~67) winsize 62
2501 18:03:41.872053 [CA 3] Center 36 (5~67) winsize 63
2502 18:03:41.874948 [CA 4] Center 34 (4~65) winsize 62
2503 18:03:41.878659 [CA 5] Center 34 (4~64) winsize 61
2504 18:03:41.879072
2505 18:03:41.882194 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2506 18:03:41.882898
2507 18:03:41.885217 [CATrainingPosCal] consider 2 rank data
2508 18:03:41.888919 u2DelayCellTimex100 = 270/100 ps
2509 18:03:41.892438 CA0 delay=40 (10~70),Diff = 6 PI (28 cell)
2510 18:03:41.895485 CA1 delay=40 (10~70),Diff = 6 PI (28 cell)
2511 18:03:41.902202 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2512 18:03:41.905443 CA3 delay=36 (5~67),Diff = 2 PI (9 cell)
2513 18:03:41.909093 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
2514 18:03:41.912451 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2515 18:03:41.913087
2516 18:03:41.915377 CA PerBit enable=1, Macro0, CA PI delay=34
2517 18:03:41.915802
2518 18:03:41.919032 [CBTSetCACLKResult] CA Dly = 34
2519 18:03:41.919539 CS Dly: 8 (0~41)
2520 18:03:41.919872
2521 18:03:41.922499 ----->DramcWriteLeveling(PI) begin...
2522 18:03:41.923203 ==
2523 18:03:41.925850 Dram Type= 6, Freq= 0, CH_0, rank 0
2524 18:03:41.932348 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2525 18:03:41.932894 ==
2526 18:03:41.935976 Write leveling (Byte 0): 31 => 31
2527 18:03:41.939320 Write leveling (Byte 1): 30 => 30
2528 18:03:41.939736 DramcWriteLeveling(PI) end<-----
2529 18:03:41.940064
2530 18:03:41.942263 ==
2531 18:03:41.946040 Dram Type= 6, Freq= 0, CH_0, rank 0
2532 18:03:41.949348 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2533 18:03:41.949946 ==
2534 18:03:41.952691 [Gating] SW mode calibration
2535 18:03:41.958934 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2536 18:03:41.962683 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2537 18:03:41.969083 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2538 18:03:41.972511 0 15 4 | B1->B0 | 2323 3333 | 0 1 | (0 0) (1 1)
2539 18:03:41.976170 0 15 8 | B1->B0 | 3333 3434 | 1 1 | (0 0) (1 1)
2540 18:03:41.982971 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2541 18:03:41.985890 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2542 18:03:41.989531 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2543 18:03:41.992521 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2544 18:03:41.999713 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2545 18:03:42.003302 1 0 0 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
2546 18:03:42.006110 1 0 4 | B1->B0 | 2c2c 2323 | 0 0 | (0 1) (0 0)
2547 18:03:42.012663 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2548 18:03:42.016147 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2549 18:03:42.019634 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2550 18:03:42.026662 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2551 18:03:42.029686 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2552 18:03:42.033051 1 0 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2553 18:03:42.039783 1 1 0 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
2554 18:03:42.043222 1 1 4 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
2555 18:03:42.046346 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2556 18:03:42.052887 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2557 18:03:42.056619 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2558 18:03:42.059855 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2559 18:03:42.063312 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2560 18:03:42.069881 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2561 18:03:42.073582 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2562 18:03:42.076805 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2563 18:03:42.083826 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2564 18:03:42.086897 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 18:03:42.089789 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2566 18:03:42.096794 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2567 18:03:42.100115 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2568 18:03:42.103203 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2569 18:03:42.110587 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2570 18:03:42.113463 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2571 18:03:42.116915 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2572 18:03:42.120295 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2573 18:03:42.126828 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2574 18:03:42.130329 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2575 18:03:42.134058 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2576 18:03:42.140214 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2577 18:03:42.143698 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2578 18:03:42.147298 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2579 18:03:42.150774 Total UI for P1: 0, mck2ui 16
2580 18:03:42.153574 best dqsien dly found for B0: ( 1, 4, 0)
2581 18:03:42.156884 Total UI for P1: 0, mck2ui 16
2582 18:03:42.160609 best dqsien dly found for B1: ( 1, 4, 0)
2583 18:03:42.163796 best DQS0 dly(MCK, UI, PI) = (1, 4, 0)
2584 18:03:42.167220 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2585 18:03:42.167684
2586 18:03:42.170725 best DQS0 P1 dly(MCK, UI, PI) = (1, 8, 0)
2587 18:03:42.177250 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2588 18:03:42.177824 [Gating] SW calibration Done
2589 18:03:42.178217 ==
2590 18:03:42.180592 Dram Type= 6, Freq= 0, CH_0, rank 0
2591 18:03:42.188074 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2592 18:03:42.188611 ==
2593 18:03:42.188968 RX Vref Scan: 0
2594 18:03:42.189335
2595 18:03:42.190598 RX Vref 0 -> 0, step: 1
2596 18:03:42.191085
2597 18:03:42.193950 RX Delay -40 -> 252, step: 8
2598 18:03:42.197390 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2599 18:03:42.200767 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2600 18:03:42.203708 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2601 18:03:42.207448 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2602 18:03:42.213942 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2603 18:03:42.217383 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2604 18:03:42.221141 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2605 18:03:42.224228 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2606 18:03:42.227832 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2607 18:03:42.231289 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2608 18:03:42.237759 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2609 18:03:42.240918 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2610 18:03:42.243931 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2611 18:03:42.247433 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2612 18:03:42.250901 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2613 18:03:42.257743 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2614 18:03:42.258178 ==
2615 18:03:42.260718 Dram Type= 6, Freq= 0, CH_0, rank 0
2616 18:03:42.264059 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2617 18:03:42.264492 ==
2618 18:03:42.264925 DQS Delay:
2619 18:03:42.267506 DQS0 = 0, DQS1 = 0
2620 18:03:42.267939 DQM Delay:
2621 18:03:42.271002 DQM0 = 116, DQM1 = 107
2622 18:03:42.271575 DQ Delay:
2623 18:03:42.274141 DQ0 =115, DQ1 =115, DQ2 =111, DQ3 =115
2624 18:03:42.277637 DQ4 =115, DQ5 =111, DQ6 =123, DQ7 =123
2625 18:03:42.281077 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2626 18:03:42.284542 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =115
2627 18:03:42.284964
2628 18:03:42.285321
2629 18:03:42.287603 ==
2630 18:03:42.288011 Dram Type= 6, Freq= 0, CH_0, rank 0
2631 18:03:42.295046 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2632 18:03:42.295678 ==
2633 18:03:42.296020
2634 18:03:42.296328
2635 18:03:42.297736 TX Vref Scan disable
2636 18:03:42.298144 == TX Byte 0 ==
2637 18:03:42.301266 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2638 18:03:42.307784 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2639 18:03:42.308194 == TX Byte 1 ==
2640 18:03:42.311191 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2641 18:03:42.317932 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2642 18:03:42.318343 ==
2643 18:03:42.321427 Dram Type= 6, Freq= 0, CH_0, rank 0
2644 18:03:42.324386 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2645 18:03:42.324793 ==
2646 18:03:42.336116 TX Vref=22, minBit 1, minWin=25, winSum=418
2647 18:03:42.339497 TX Vref=24, minBit 1, minWin=24, winSum=420
2648 18:03:42.343168 TX Vref=26, minBit 0, minWin=26, winSum=426
2649 18:03:42.346127 TX Vref=28, minBit 1, minWin=26, winSum=432
2650 18:03:42.349927 TX Vref=30, minBit 1, minWin=26, winSum=434
2651 18:03:42.352751 TX Vref=32, minBit 1, minWin=26, winSum=432
2652 18:03:42.359810 [TxChooseVref] Worse bit 1, Min win 26, Win sum 434, Final Vref 30
2653 18:03:42.360345
2654 18:03:42.363449 Final TX Range 1 Vref 30
2655 18:03:42.363958
2656 18:03:42.364400 ==
2657 18:03:42.366328 Dram Type= 6, Freq= 0, CH_0, rank 0
2658 18:03:42.369483 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2659 18:03:42.369919 ==
2660 18:03:42.370354
2661 18:03:42.370764
2662 18:03:42.373384 TX Vref Scan disable
2663 18:03:42.376359 == TX Byte 0 ==
2664 18:03:42.379853 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2665 18:03:42.383146 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2666 18:03:42.386818 == TX Byte 1 ==
2667 18:03:42.389925 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2668 18:03:42.393165 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2669 18:03:42.393587
2670 18:03:42.396774 [DATLAT]
2671 18:03:42.397266 Freq=1200, CH0 RK0
2672 18:03:42.397605
2673 18:03:42.399792 DATLAT Default: 0xd
2674 18:03:42.400207 0, 0xFFFF, sum = 0
2675 18:03:42.403351 1, 0xFFFF, sum = 0
2676 18:03:42.403870 2, 0xFFFF, sum = 0
2677 18:03:42.406673 3, 0xFFFF, sum = 0
2678 18:03:42.407098 4, 0xFFFF, sum = 0
2679 18:03:42.410334 5, 0xFFFF, sum = 0
2680 18:03:42.410756 6, 0xFFFF, sum = 0
2681 18:03:42.413305 7, 0xFFFF, sum = 0
2682 18:03:42.413763 8, 0xFFFF, sum = 0
2683 18:03:42.416658 9, 0xFFFF, sum = 0
2684 18:03:42.417129 10, 0xFFFF, sum = 0
2685 18:03:42.420113 11, 0xFFFF, sum = 0
2686 18:03:42.420629 12, 0x0, sum = 1
2687 18:03:42.423615 13, 0x0, sum = 2
2688 18:03:42.424039 14, 0x0, sum = 3
2689 18:03:42.427094 15, 0x0, sum = 4
2690 18:03:42.427518 best_step = 13
2691 18:03:42.427853
2692 18:03:42.428166 ==
2693 18:03:42.430057 Dram Type= 6, Freq= 0, CH_0, rank 0
2694 18:03:42.437052 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2695 18:03:42.437480 ==
2696 18:03:42.437811 RX Vref Scan: 1
2697 18:03:42.438122
2698 18:03:42.440309 Set Vref Range= 32 -> 127
2699 18:03:42.440725
2700 18:03:42.443560 RX Vref 32 -> 127, step: 1
2701 18:03:42.443977
2702 18:03:42.444386 RX Delay -21 -> 252, step: 4
2703 18:03:42.447041
2704 18:03:42.447457 Set Vref, RX VrefLevel [Byte0]: 32
2705 18:03:42.450814 [Byte1]: 32
2706 18:03:42.454482
2707 18:03:42.454897 Set Vref, RX VrefLevel [Byte0]: 33
2708 18:03:42.458294 [Byte1]: 33
2709 18:03:42.462549
2710 18:03:42.462982 Set Vref, RX VrefLevel [Byte0]: 34
2711 18:03:42.465883 [Byte1]: 34
2712 18:03:42.470633
2713 18:03:42.471061 Set Vref, RX VrefLevel [Byte0]: 35
2714 18:03:42.477026 [Byte1]: 35
2715 18:03:42.477463
2716 18:03:42.480061 Set Vref, RX VrefLevel [Byte0]: 36
2717 18:03:42.483542 [Byte1]: 36
2718 18:03:42.484065
2719 18:03:42.486991 Set Vref, RX VrefLevel [Byte0]: 37
2720 18:03:42.490069 [Byte1]: 37
2721 18:03:42.494266
2722 18:03:42.494696 Set Vref, RX VrefLevel [Byte0]: 38
2723 18:03:42.497731 [Byte1]: 38
2724 18:03:42.501876
2725 18:03:42.502330 Set Vref, RX VrefLevel [Byte0]: 39
2726 18:03:42.505309 [Byte1]: 39
2727 18:03:42.509915
2728 18:03:42.510417 Set Vref, RX VrefLevel [Byte0]: 40
2729 18:03:42.513474 [Byte1]: 40
2730 18:03:42.518605
2731 18:03:42.519139 Set Vref, RX VrefLevel [Byte0]: 41
2732 18:03:42.521038 [Byte1]: 41
2733 18:03:42.525739
2734 18:03:42.526252 Set Vref, RX VrefLevel [Byte0]: 42
2735 18:03:42.529296 [Byte1]: 42
2736 18:03:42.533900
2737 18:03:42.534393 Set Vref, RX VrefLevel [Byte0]: 43
2738 18:03:42.536960 [Byte1]: 43
2739 18:03:42.542058
2740 18:03:42.542488 Set Vref, RX VrefLevel [Byte0]: 44
2741 18:03:42.545020 [Byte1]: 44
2742 18:03:42.549675
2743 18:03:42.550174 Set Vref, RX VrefLevel [Byte0]: 45
2744 18:03:42.553062 [Byte1]: 45
2745 18:03:42.557796
2746 18:03:42.558298 Set Vref, RX VrefLevel [Byte0]: 46
2747 18:03:42.560659 [Byte1]: 46
2748 18:03:42.565886
2749 18:03:42.566302 Set Vref, RX VrefLevel [Byte0]: 47
2750 18:03:42.568776 [Byte1]: 47
2751 18:03:42.573420
2752 18:03:42.573833 Set Vref, RX VrefLevel [Byte0]: 48
2753 18:03:42.576888 [Byte1]: 48
2754 18:03:42.581289
2755 18:03:42.581792 Set Vref, RX VrefLevel [Byte0]: 49
2756 18:03:42.584622 [Byte1]: 49
2757 18:03:42.589324
2758 18:03:42.589804 Set Vref, RX VrefLevel [Byte0]: 50
2759 18:03:42.592781 [Byte1]: 50
2760 18:03:42.597990
2761 18:03:42.598500 Set Vref, RX VrefLevel [Byte0]: 51
2762 18:03:42.600896 [Byte1]: 51
2763 18:03:42.605378
2764 18:03:42.605797 Set Vref, RX VrefLevel [Byte0]: 52
2765 18:03:42.608450 [Byte1]: 52
2766 18:03:42.613276
2767 18:03:42.613767 Set Vref, RX VrefLevel [Byte0]: 53
2768 18:03:42.616346 [Byte1]: 53
2769 18:03:42.621496
2770 18:03:42.622015 Set Vref, RX VrefLevel [Byte0]: 54
2771 18:03:42.624039 [Byte1]: 54
2772 18:03:42.628644
2773 18:03:42.629204 Set Vref, RX VrefLevel [Byte0]: 55
2774 18:03:42.632051 [Byte1]: 55
2775 18:03:42.637046
2776 18:03:42.637561 Set Vref, RX VrefLevel [Byte0]: 56
2777 18:03:42.639905 [Byte1]: 56
2778 18:03:42.645146
2779 18:03:42.645643 Set Vref, RX VrefLevel [Byte0]: 57
2780 18:03:42.647895 [Byte1]: 57
2781 18:03:42.652624
2782 18:03:42.653155 Set Vref, RX VrefLevel [Byte0]: 58
2783 18:03:42.656041 [Byte1]: 58
2784 18:03:42.660599
2785 18:03:42.661053 Set Vref, RX VrefLevel [Byte0]: 59
2786 18:03:42.664258 [Byte1]: 59
2787 18:03:42.668661
2788 18:03:42.669120 Set Vref, RX VrefLevel [Byte0]: 60
2789 18:03:42.671559 [Byte1]: 60
2790 18:03:42.676356
2791 18:03:42.676772 Set Vref, RX VrefLevel [Byte0]: 61
2792 18:03:42.679848 [Byte1]: 61
2793 18:03:42.684553
2794 18:03:42.684968 Set Vref, RX VrefLevel [Byte0]: 62
2795 18:03:42.687736 [Byte1]: 62
2796 18:03:42.692369
2797 18:03:42.692781 Set Vref, RX VrefLevel [Byte0]: 63
2798 18:03:42.695350 [Byte1]: 63
2799 18:03:42.700342
2800 18:03:42.700759 Set Vref, RX VrefLevel [Byte0]: 64
2801 18:03:42.703782 [Byte1]: 64
2802 18:03:42.708040
2803 18:03:42.708459 Set Vref, RX VrefLevel [Byte0]: 65
2804 18:03:42.711721 [Byte1]: 65
2805 18:03:42.715819
2806 18:03:42.716232 Set Vref, RX VrefLevel [Byte0]: 66
2807 18:03:42.719699 [Byte1]: 66
2808 18:03:42.724260
2809 18:03:42.724783 Set Vref, RX VrefLevel [Byte0]: 67
2810 18:03:42.727320 [Byte1]: 67
2811 18:03:42.731791
2812 18:03:42.732212 Set Vref, RX VrefLevel [Byte0]: 68
2813 18:03:42.735166 [Byte1]: 68
2814 18:03:42.740171
2815 18:03:42.740690 Set Vref, RX VrefLevel [Byte0]: 69
2816 18:03:42.743332 [Byte1]: 69
2817 18:03:42.747595
2818 18:03:42.748149 Set Vref, RX VrefLevel [Byte0]: 70
2819 18:03:42.751033 [Byte1]: 70
2820 18:03:42.755696
2821 18:03:42.756173 Final RX Vref Byte 0 = 53 to rank0
2822 18:03:42.759202 Final RX Vref Byte 1 = 51 to rank0
2823 18:03:42.762803 Final RX Vref Byte 0 = 53 to rank1
2824 18:03:42.765697 Final RX Vref Byte 1 = 51 to rank1==
2825 18:03:42.768881 Dram Type= 6, Freq= 0, CH_0, rank 0
2826 18:03:42.775813 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2827 18:03:42.776230 ==
2828 18:03:42.776566 DQS Delay:
2829 18:03:42.776877 DQS0 = 0, DQS1 = 0
2830 18:03:42.779316 DQM Delay:
2831 18:03:42.779730 DQM0 = 115, DQM1 = 104
2832 18:03:42.782896 DQ Delay:
2833 18:03:42.785803 DQ0 =116, DQ1 =114, DQ2 =112, DQ3 =114
2834 18:03:42.789728 DQ4 =116, DQ5 =108, DQ6 =122, DQ7 =122
2835 18:03:42.792501 DQ8 =92, DQ9 =90, DQ10 =104, DQ11 =96
2836 18:03:42.795898 DQ12 =112, DQ13 =110, DQ14 =118, DQ15 =114
2837 18:03:42.796350
2838 18:03:42.796685
2839 18:03:42.802728 [DQSOSCAuto] RK0, (LSB)MR18= 0xfcec, (MSB)MR19= 0x303, tDQSOscB0 = 418 ps tDQSOscB1 = 411 ps
2840 18:03:42.805940 CH0 RK0: MR19=303, MR18=FCEC
2841 18:03:42.812923 CH0_RK0: MR19=0x303, MR18=0xFCEC, DQSOSC=411, MR23=63, INC=38, DEC=25
2842 18:03:42.813394
2843 18:03:42.815970 ----->DramcWriteLeveling(PI) begin...
2844 18:03:42.816418 ==
2845 18:03:42.819988 Dram Type= 6, Freq= 0, CH_0, rank 1
2846 18:03:42.822780 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2847 18:03:42.823310 ==
2848 18:03:42.826227 Write leveling (Byte 0): 32 => 32
2849 18:03:42.829996 Write leveling (Byte 1): 30 => 30
2850 18:03:42.833163 DramcWriteLeveling(PI) end<-----
2851 18:03:42.833672
2852 18:03:42.834008 ==
2853 18:03:42.836480 Dram Type= 6, Freq= 0, CH_0, rank 1
2854 18:03:42.839695 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2855 18:03:42.843122 ==
2856 18:03:42.843634 [Gating] SW mode calibration
2857 18:03:42.849418 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2858 18:03:42.856072 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2859 18:03:42.859712 0 15 0 | B1->B0 | 2323 2827 | 0 1 | (0 0) (1 1)
2860 18:03:42.866136 0 15 4 | B1->B0 | 2d2d 3434 | 1 1 | (1 1) (1 1)
2861 18:03:42.869694 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2862 18:03:42.873095 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2863 18:03:42.876372 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2864 18:03:42.883231 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2865 18:03:42.886221 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2866 18:03:42.889851 0 15 28 | B1->B0 | 3434 2626 | 1 0 | (1 0) (1 0)
2867 18:03:42.896384 1 0 0 | B1->B0 | 2d2d 2424 | 0 0 | (0 0) (0 0)
2868 18:03:42.899837 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2869 18:03:42.903357 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2870 18:03:42.909951 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2871 18:03:42.913032 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2872 18:03:42.916927 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2873 18:03:42.923293 1 0 24 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
2874 18:03:42.926850 1 0 28 | B1->B0 | 2323 4444 | 0 0 | (0 0) (0 0)
2875 18:03:42.930440 1 1 0 | B1->B0 | 3333 4242 | 0 0 | (0 0) (1 1)
2876 18:03:42.933407 1 1 4 | B1->B0 | 4444 4646 | 0 0 | (1 1) (0 0)
2877 18:03:42.940433 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2878 18:03:42.943249 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2879 18:03:42.946805 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2880 18:03:42.953387 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2881 18:03:42.957089 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2882 18:03:42.960022 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2883 18:03:42.966848 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2884 18:03:42.970193 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2885 18:03:42.974012 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2886 18:03:42.980348 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2887 18:03:42.983822 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2888 18:03:42.986980 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2889 18:03:42.993675 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2890 18:03:42.997422 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2891 18:03:43.000320 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2892 18:03:43.003720 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2893 18:03:43.011096 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2894 18:03:43.013660 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2895 18:03:43.017475 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2896 18:03:43.024056 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2897 18:03:43.027542 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2898 18:03:43.030826 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2899 18:03:43.037489 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2900 18:03:43.037923 Total UI for P1: 0, mck2ui 16
2901 18:03:43.043967 best dqsien dly found for B0: ( 1, 3, 26)
2902 18:03:43.047490 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2903 18:03:43.050884 Total UI for P1: 0, mck2ui 16
2904 18:03:43.054056 best dqsien dly found for B1: ( 1, 4, 0)
2905 18:03:43.057454 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2906 18:03:43.060944 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2907 18:03:43.061489
2908 18:03:43.064490 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2909 18:03:43.067386 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2910 18:03:43.070658 [Gating] SW calibration Done
2911 18:03:43.071072 ==
2912 18:03:43.074507 Dram Type= 6, Freq= 0, CH_0, rank 1
2913 18:03:43.077334 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2914 18:03:43.077753 ==
2915 18:03:43.080825 RX Vref Scan: 0
2916 18:03:43.081438
2917 18:03:43.081930 RX Vref 0 -> 0, step: 1
2918 18:03:43.084029
2919 18:03:43.084464 RX Delay -40 -> 252, step: 8
2920 18:03:43.090988 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2921 18:03:43.094270 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2922 18:03:43.097726 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2923 18:03:43.101029 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2924 18:03:43.104586 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2925 18:03:43.107525 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2926 18:03:43.114197 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2927 18:03:43.117761 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2928 18:03:43.121116 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2929 18:03:43.124263 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2930 18:03:43.127794 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2931 18:03:43.134742 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2932 18:03:43.137469 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2933 18:03:43.141100 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2934 18:03:43.144551 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2935 18:03:43.147613 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2936 18:03:43.148166 ==
2937 18:03:43.150856 Dram Type= 6, Freq= 0, CH_0, rank 1
2938 18:03:43.157521 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2939 18:03:43.157749 ==
2940 18:03:43.157929 DQS Delay:
2941 18:03:43.161020 DQS0 = 0, DQS1 = 0
2942 18:03:43.161256 DQM Delay:
2943 18:03:43.161556 DQM0 = 115, DQM1 = 106
2944 18:03:43.164418 DQ Delay:
2945 18:03:43.167766 DQ0 =115, DQ1 =115, DQ2 =111, DQ3 =115
2946 18:03:43.171402 DQ4 =115, DQ5 =107, DQ6 =123, DQ7 =123
2947 18:03:43.174156 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =99
2948 18:03:43.177814 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =111
2949 18:03:43.178039
2950 18:03:43.178216
2951 18:03:43.178381 ==
2952 18:03:43.181303 Dram Type= 6, Freq= 0, CH_0, rank 1
2953 18:03:43.184431 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2954 18:03:43.184657 ==
2955 18:03:43.187631
2956 18:03:43.187859
2957 18:03:43.188102 TX Vref Scan disable
2958 18:03:43.191113 == TX Byte 0 ==
2959 18:03:43.194862 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2960 18:03:43.197839 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2961 18:03:43.201210 == TX Byte 1 ==
2962 18:03:43.204596 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2963 18:03:43.208063 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2964 18:03:43.208288 ==
2965 18:03:43.211478 Dram Type= 6, Freq= 0, CH_0, rank 1
2966 18:03:43.217956 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2967 18:03:43.218309 ==
2968 18:03:43.228829 TX Vref=22, minBit 0, minWin=25, winSum=419
2969 18:03:43.231992 TX Vref=24, minBit 0, minWin=26, winSum=426
2970 18:03:43.235619 TX Vref=26, minBit 3, minWin=26, winSum=432
2971 18:03:43.238583 TX Vref=28, minBit 5, minWin=26, winSum=435
2972 18:03:43.242157 TX Vref=30, minBit 0, minWin=27, winSum=438
2973 18:03:43.245365 TX Vref=32, minBit 4, minWin=26, winSum=436
2974 18:03:43.252299 [TxChooseVref] Worse bit 0, Min win 27, Win sum 438, Final Vref 30
2975 18:03:43.252716
2976 18:03:43.255272 Final TX Range 1 Vref 30
2977 18:03:43.255686
2978 18:03:43.256011 ==
2979 18:03:43.258900 Dram Type= 6, Freq= 0, CH_0, rank 1
2980 18:03:43.262390 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2981 18:03:43.262808 ==
2982 18:03:43.263136
2983 18:03:43.263438
2984 18:03:43.265434 TX Vref Scan disable
2985 18:03:43.268646 == TX Byte 0 ==
2986 18:03:43.272250 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2987 18:03:43.276209 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2988 18:03:43.278880 == TX Byte 1 ==
2989 18:03:43.282845 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2990 18:03:43.285983 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2991 18:03:43.286408
2992 18:03:43.288937 [DATLAT]
2993 18:03:43.289403 Freq=1200, CH0 RK1
2994 18:03:43.289740
2995 18:03:43.292256 DATLAT Default: 0xd
2996 18:03:43.292853 0, 0xFFFF, sum = 0
2997 18:03:43.296052 1, 0xFFFF, sum = 0
2998 18:03:43.296475 2, 0xFFFF, sum = 0
2999 18:03:43.299398 3, 0xFFFF, sum = 0
3000 18:03:43.300013 4, 0xFFFF, sum = 0
3001 18:03:43.302409 5, 0xFFFF, sum = 0
3002 18:03:43.302978 6, 0xFFFF, sum = 0
3003 18:03:43.305515 7, 0xFFFF, sum = 0
3004 18:03:43.305991 8, 0xFFFF, sum = 0
3005 18:03:43.309932 9, 0xFFFF, sum = 0
3006 18:03:43.310457 10, 0xFFFF, sum = 0
3007 18:03:43.312812 11, 0xFFFF, sum = 0
3008 18:03:43.313364 12, 0x0, sum = 1
3009 18:03:43.316067 13, 0x0, sum = 2
3010 18:03:43.316513 14, 0x0, sum = 3
3011 18:03:43.319379 15, 0x0, sum = 4
3012 18:03:43.319803 best_step = 13
3013 18:03:43.320133
3014 18:03:43.320445 ==
3015 18:03:43.322387 Dram Type= 6, Freq= 0, CH_0, rank 1
3016 18:03:43.329271 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3017 18:03:43.329734 ==
3018 18:03:43.330226 RX Vref Scan: 0
3019 18:03:43.330563
3020 18:03:43.332709 RX Vref 0 -> 0, step: 1
3021 18:03:43.333165
3022 18:03:43.336112 RX Delay -21 -> 252, step: 4
3023 18:03:43.339414 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3024 18:03:43.342418 iDelay=195, Bit 1, Center 114 (43 ~ 186) 144
3025 18:03:43.349056 iDelay=195, Bit 2, Center 110 (39 ~ 182) 144
3026 18:03:43.352545 iDelay=195, Bit 3, Center 114 (43 ~ 186) 144
3027 18:03:43.356127 iDelay=195, Bit 4, Center 114 (47 ~ 182) 136
3028 18:03:43.359025 iDelay=195, Bit 5, Center 104 (35 ~ 174) 140
3029 18:03:43.362673 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3030 18:03:43.366322 iDelay=195, Bit 7, Center 122 (51 ~ 194) 144
3031 18:03:43.372617 iDelay=195, Bit 8, Center 94 (27 ~ 162) 136
3032 18:03:43.376436 iDelay=195, Bit 9, Center 92 (23 ~ 162) 140
3033 18:03:43.379456 iDelay=195, Bit 10, Center 106 (39 ~ 174) 136
3034 18:03:43.382935 iDelay=195, Bit 11, Center 94 (27 ~ 162) 136
3035 18:03:43.386553 iDelay=195, Bit 12, Center 110 (43 ~ 178) 136
3036 18:03:43.389541 iDelay=195, Bit 13, Center 110 (43 ~ 178) 136
3037 18:03:43.396581 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
3038 18:03:43.399693 iDelay=195, Bit 15, Center 112 (47 ~ 178) 132
3039 18:03:43.400110 ==
3040 18:03:43.402939 Dram Type= 6, Freq= 0, CH_0, rank 1
3041 18:03:43.406328 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3042 18:03:43.406869 ==
3043 18:03:43.409578 DQS Delay:
3044 18:03:43.410091 DQS0 = 0, DQS1 = 0
3045 18:03:43.410418 DQM Delay:
3046 18:03:43.413399 DQM0 = 114, DQM1 = 104
3047 18:03:43.413896 DQ Delay:
3048 18:03:43.416341 DQ0 =114, DQ1 =114, DQ2 =110, DQ3 =114
3049 18:03:43.419644 DQ4 =114, DQ5 =104, DQ6 =122, DQ7 =122
3050 18:03:43.423313 DQ8 =94, DQ9 =92, DQ10 =106, DQ11 =94
3051 18:03:43.430154 DQ12 =110, DQ13 =110, DQ14 =116, DQ15 =112
3052 18:03:43.430568
3053 18:03:43.430892
3054 18:03:43.436698 [DQSOSCAuto] RK1, (LSB)MR18= 0xf2, (MSB)MR19= 0x403, tDQSOscB0 = 415 ps tDQSOscB1 = 410 ps
3055 18:03:43.440306 CH0 RK1: MR19=403, MR18=F2
3056 18:03:43.446318 CH0_RK1: MR19=0x403, MR18=0xF2, DQSOSC=410, MR23=63, INC=39, DEC=26
3057 18:03:43.446735 [RxdqsGatingPostProcess] freq 1200
3058 18:03:43.453476 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3059 18:03:43.456316 best DQS0 dly(2T, 0.5T) = (0, 12)
3060 18:03:43.459752 best DQS1 dly(2T, 0.5T) = (0, 12)
3061 18:03:43.463435 best DQS0 P1 dly(2T, 0.5T) = (1, 0)
3062 18:03:43.466438 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3063 18:03:43.470060 best DQS0 dly(2T, 0.5T) = (0, 11)
3064 18:03:43.473536 best DQS1 dly(2T, 0.5T) = (0, 12)
3065 18:03:43.476611 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3066 18:03:43.479796 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3067 18:03:43.480313 Pre-setting of DQS Precalculation
3068 18:03:43.487032 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3069 18:03:43.487484 ==
3070 18:03:43.489929 Dram Type= 6, Freq= 0, CH_1, rank 0
3071 18:03:43.493388 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3072 18:03:43.493811 ==
3073 18:03:43.500272 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3074 18:03:43.506430 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3075 18:03:43.513766 [CA 0] Center 38 (9~68) winsize 60
3076 18:03:43.517192 [CA 1] Center 38 (8~68) winsize 61
3077 18:03:43.520305 [CA 2] Center 35 (5~65) winsize 61
3078 18:03:43.524394 [CA 3] Center 34 (3~65) winsize 63
3079 18:03:43.527639 [CA 4] Center 34 (4~65) winsize 62
3080 18:03:43.530751 [CA 5] Center 34 (4~64) winsize 61
3081 18:03:43.531173
3082 18:03:43.534283 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3083 18:03:43.534698
3084 18:03:43.537620 [CATrainingPosCal] consider 1 rank data
3085 18:03:43.540764 u2DelayCellTimex100 = 270/100 ps
3086 18:03:43.544196 CA0 delay=38 (9~68),Diff = 4 PI (19 cell)
3087 18:03:43.547365 CA1 delay=38 (8~68),Diff = 4 PI (19 cell)
3088 18:03:43.551090 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3089 18:03:43.557447 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
3090 18:03:43.561334 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3091 18:03:43.564209 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3092 18:03:43.564629
3093 18:03:43.567754 CA PerBit enable=1, Macro0, CA PI delay=34
3094 18:03:43.568199
3095 18:03:43.570724 [CBTSetCACLKResult] CA Dly = 34
3096 18:03:43.571138 CS Dly: 6 (0~37)
3097 18:03:43.571471 ==
3098 18:03:43.574361 Dram Type= 6, Freq= 0, CH_1, rank 1
3099 18:03:43.580739 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3100 18:03:43.581270 ==
3101 18:03:43.584203 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3102 18:03:43.591119 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3103 18:03:43.599862 [CA 0] Center 38 (8~68) winsize 61
3104 18:03:43.603269 [CA 1] Center 38 (9~68) winsize 60
3105 18:03:43.606153 [CA 2] Center 34 (4~65) winsize 62
3106 18:03:43.609887 [CA 3] Center 34 (4~65) winsize 62
3107 18:03:43.612969 [CA 4] Center 35 (5~65) winsize 61
3108 18:03:43.616331 [CA 5] Center 33 (3~64) winsize 62
3109 18:03:43.616750
3110 18:03:43.619919 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3111 18:03:43.620338
3112 18:03:43.622845 [CATrainingPosCal] consider 2 rank data
3113 18:03:43.626233 u2DelayCellTimex100 = 270/100 ps
3114 18:03:43.629730 CA0 delay=38 (9~68),Diff = 4 PI (19 cell)
3115 18:03:43.633502 CA1 delay=38 (9~68),Diff = 4 PI (19 cell)
3116 18:03:43.636737 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3117 18:03:43.642981 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
3118 18:03:43.646296 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
3119 18:03:43.650117 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3120 18:03:43.650577
3121 18:03:43.652931 CA PerBit enable=1, Macro0, CA PI delay=34
3122 18:03:43.653380
3123 18:03:43.656896 [CBTSetCACLKResult] CA Dly = 34
3124 18:03:43.657356 CS Dly: 7 (0~40)
3125 18:03:43.657691
3126 18:03:43.660113 ----->DramcWriteLeveling(PI) begin...
3127 18:03:43.660711 ==
3128 18:03:43.663194 Dram Type= 6, Freq= 0, CH_1, rank 0
3129 18:03:43.669692 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3130 18:03:43.670113 ==
3131 18:03:43.673099 Write leveling (Byte 0): 25 => 25
3132 18:03:43.676609 Write leveling (Byte 1): 30 => 30
3133 18:03:43.677064 DramcWriteLeveling(PI) end<-----
3134 18:03:43.677409
3135 18:03:43.680313 ==
3136 18:03:43.683352 Dram Type= 6, Freq= 0, CH_1, rank 0
3137 18:03:43.686831 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3138 18:03:43.687358 ==
3139 18:03:43.690013 [Gating] SW mode calibration
3140 18:03:43.697057 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3141 18:03:43.700432 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3142 18:03:43.707058 0 15 0 | B1->B0 | 2323 2323 | 1 0 | (1 1) (0 0)
3143 18:03:43.710215 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3144 18:03:43.713655 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3145 18:03:43.720535 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3146 18:03:43.723791 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3147 18:03:43.727025 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3148 18:03:43.730590 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3149 18:03:43.736805 0 15 28 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 0)
3150 18:03:43.740509 1 0 0 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
3151 18:03:43.744004 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3152 18:03:43.750226 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3153 18:03:43.753660 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3154 18:03:43.756853 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3155 18:03:43.763488 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3156 18:03:43.767292 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3157 18:03:43.770330 1 0 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3158 18:03:43.776949 1 1 0 | B1->B0 | 4040 3232 | 0 0 | (0 0) (0 0)
3159 18:03:43.780040 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3160 18:03:43.783619 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3161 18:03:43.789896 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3162 18:03:43.793671 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3163 18:03:43.796564 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3164 18:03:43.800045 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3165 18:03:43.807198 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3166 18:03:43.810135 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3167 18:03:43.813499 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3168 18:03:43.819964 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3169 18:03:43.823378 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3170 18:03:43.826998 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3171 18:03:43.833476 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3172 18:03:43.837863 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3173 18:03:43.840342 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3174 18:03:43.846920 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3175 18:03:43.850539 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3176 18:03:43.853881 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3177 18:03:43.860040 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3178 18:03:43.863469 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3179 18:03:43.867120 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3180 18:03:43.870675 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3181 18:03:43.877152 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3182 18:03:43.880095 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3183 18:03:43.883907 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3184 18:03:43.887039 Total UI for P1: 0, mck2ui 16
3185 18:03:43.890420 best dqsien dly found for B0: ( 1, 3, 30)
3186 18:03:43.893618 Total UI for P1: 0, mck2ui 16
3187 18:03:43.897202 best dqsien dly found for B1: ( 1, 4, 0)
3188 18:03:43.900524 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
3189 18:03:43.903931 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
3190 18:03:43.904110
3191 18:03:43.910445 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
3192 18:03:43.914044 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
3193 18:03:43.914207 [Gating] SW calibration Done
3194 18:03:43.917442 ==
3195 18:03:43.917596 Dram Type= 6, Freq= 0, CH_1, rank 0
3196 18:03:43.924463 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3197 18:03:43.924613 ==
3198 18:03:43.924695 RX Vref Scan: 0
3199 18:03:43.924767
3200 18:03:43.927755 RX Vref 0 -> 0, step: 1
3201 18:03:43.927877
3202 18:03:43.930799 RX Delay -40 -> 252, step: 8
3203 18:03:43.934285 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3204 18:03:43.937703 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3205 18:03:43.940647 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3206 18:03:43.947700 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3207 18:03:43.950990 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3208 18:03:43.954202 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3209 18:03:43.957553 iDelay=200, Bit 6, Center 123 (56 ~ 191) 136
3210 18:03:43.961057 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3211 18:03:43.964498 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3212 18:03:43.971117 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3213 18:03:43.974603 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
3214 18:03:43.978094 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3215 18:03:43.981053 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3216 18:03:43.984524 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
3217 18:03:43.991519 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3218 18:03:43.995093 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
3219 18:03:43.995612 ==
3220 18:03:43.998008 Dram Type= 6, Freq= 0, CH_1, rank 0
3221 18:03:44.001724 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3222 18:03:44.002443 ==
3223 18:03:44.005092 DQS Delay:
3224 18:03:44.005710 DQS0 = 0, DQS1 = 0
3225 18:03:44.006255 DQM Delay:
3226 18:03:44.008264 DQM0 = 116, DQM1 = 109
3227 18:03:44.008710 DQ Delay:
3228 18:03:44.011547 DQ0 =119, DQ1 =111, DQ2 =107, DQ3 =119
3229 18:03:44.014836 DQ4 =111, DQ5 =127, DQ6 =123, DQ7 =115
3230 18:03:44.018046 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =107
3231 18:03:44.022366 DQ12 =123, DQ13 =115, DQ14 =115, DQ15 =115
3232 18:03:44.024693
3233 18:03:44.025198
3234 18:03:44.025547 ==
3235 18:03:44.028111 Dram Type= 6, Freq= 0, CH_1, rank 0
3236 18:03:44.031959 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3237 18:03:44.032540 ==
3238 18:03:44.032887
3239 18:03:44.033252
3240 18:03:44.034825 TX Vref Scan disable
3241 18:03:44.035240 == TX Byte 0 ==
3242 18:03:44.041346 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3243 18:03:44.044747 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3244 18:03:44.045209 == TX Byte 1 ==
3245 18:03:44.051449 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3246 18:03:44.054854 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3247 18:03:44.055272 ==
3248 18:03:44.058197 Dram Type= 6, Freq= 0, CH_1, rank 0
3249 18:03:44.061582 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3250 18:03:44.061879 ==
3251 18:03:44.073668 TX Vref=22, minBit 1, minWin=24, winSum=408
3252 18:03:44.077130 TX Vref=24, minBit 1, minWin=24, winSum=418
3253 18:03:44.080603 TX Vref=26, minBit 3, minWin=25, winSum=425
3254 18:03:44.083622 TX Vref=28, minBit 0, minWin=26, winSum=426
3255 18:03:44.087071 TX Vref=30, minBit 1, minWin=26, winSum=427
3256 18:03:44.090686 TX Vref=32, minBit 12, minWin=25, winSum=424
3257 18:03:44.096866 [TxChooseVref] Worse bit 1, Min win 26, Win sum 427, Final Vref 30
3258 18:03:44.096999
3259 18:03:44.100533 Final TX Range 1 Vref 30
3260 18:03:44.100619
3261 18:03:44.100684 ==
3262 18:03:44.104078 Dram Type= 6, Freq= 0, CH_1, rank 0
3263 18:03:44.107084 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3264 18:03:44.107165 ==
3265 18:03:44.107230
3266 18:03:44.107289
3267 18:03:44.110837 TX Vref Scan disable
3268 18:03:44.114172 == TX Byte 0 ==
3269 18:03:44.117714 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3270 18:03:44.120907 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3271 18:03:44.124018 == TX Byte 1 ==
3272 18:03:44.127375 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3273 18:03:44.130400 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3274 18:03:44.130532
3275 18:03:44.134151 [DATLAT]
3276 18:03:44.134238 Freq=1200, CH1 RK0
3277 18:03:44.134303
3278 18:03:44.137161 DATLAT Default: 0xd
3279 18:03:44.137253 0, 0xFFFF, sum = 0
3280 18:03:44.140836 1, 0xFFFF, sum = 0
3281 18:03:44.140955 2, 0xFFFF, sum = 0
3282 18:03:44.144269 3, 0xFFFF, sum = 0
3283 18:03:44.144390 4, 0xFFFF, sum = 0
3284 18:03:44.147177 5, 0xFFFF, sum = 0
3285 18:03:44.147293 6, 0xFFFF, sum = 0
3286 18:03:44.150705 7, 0xFFFF, sum = 0
3287 18:03:44.150831 8, 0xFFFF, sum = 0
3288 18:03:44.154391 9, 0xFFFF, sum = 0
3289 18:03:44.154532 10, 0xFFFF, sum = 0
3290 18:03:44.157192 11, 0xFFFF, sum = 0
3291 18:03:44.157301 12, 0x0, sum = 1
3292 18:03:44.160726 13, 0x0, sum = 2
3293 18:03:44.160826 14, 0x0, sum = 3
3294 18:03:44.164054 15, 0x0, sum = 4
3295 18:03:44.164151 best_step = 13
3296 18:03:44.164225
3297 18:03:44.164294 ==
3298 18:03:44.167545 Dram Type= 6, Freq= 0, CH_1, rank 0
3299 18:03:44.174229 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3300 18:03:44.174345 ==
3301 18:03:44.174424 RX Vref Scan: 1
3302 18:03:44.174495
3303 18:03:44.177661 Set Vref Range= 32 -> 127
3304 18:03:44.177756
3305 18:03:44.180964 RX Vref 32 -> 127, step: 1
3306 18:03:44.181072
3307 18:03:44.181148 RX Delay -21 -> 252, step: 4
3308 18:03:44.184538
3309 18:03:44.184633 Set Vref, RX VrefLevel [Byte0]: 32
3310 18:03:44.187537 [Byte1]: 32
3311 18:03:44.192101
3312 18:03:44.192209 Set Vref, RX VrefLevel [Byte0]: 33
3313 18:03:44.195235 [Byte1]: 33
3314 18:03:44.199905
3315 18:03:44.199999 Set Vref, RX VrefLevel [Byte0]: 34
3316 18:03:44.203597 [Byte1]: 34
3317 18:03:44.208360
3318 18:03:44.208770 Set Vref, RX VrefLevel [Byte0]: 35
3319 18:03:44.211887 [Byte1]: 35
3320 18:03:44.216774
3321 18:03:44.217325 Set Vref, RX VrefLevel [Byte0]: 36
3322 18:03:44.219466 [Byte1]: 36
3323 18:03:44.224201
3324 18:03:44.224609 Set Vref, RX VrefLevel [Byte0]: 37
3325 18:03:44.227480 [Byte1]: 37
3326 18:03:44.232590
3327 18:03:44.233125 Set Vref, RX VrefLevel [Byte0]: 38
3328 18:03:44.236106 [Byte1]: 38
3329 18:03:44.239793
3330 18:03:44.240206 Set Vref, RX VrefLevel [Byte0]: 39
3331 18:03:44.243280 [Byte1]: 39
3332 18:03:44.247739
3333 18:03:44.248145 Set Vref, RX VrefLevel [Byte0]: 40
3334 18:03:44.251312 [Byte1]: 40
3335 18:03:44.255949
3336 18:03:44.256361 Set Vref, RX VrefLevel [Byte0]: 41
3337 18:03:44.258907 [Byte1]: 41
3338 18:03:44.264215
3339 18:03:44.264720 Set Vref, RX VrefLevel [Byte0]: 42
3340 18:03:44.266787 [Byte1]: 42
3341 18:03:44.271277
3342 18:03:44.271686 Set Vref, RX VrefLevel [Byte0]: 43
3343 18:03:44.274786 [Byte1]: 43
3344 18:03:44.279772
3345 18:03:44.280253 Set Vref, RX VrefLevel [Byte0]: 44
3346 18:03:44.282685 [Byte1]: 44
3347 18:03:44.287685
3348 18:03:44.288392 Set Vref, RX VrefLevel [Byte0]: 45
3349 18:03:44.290729 [Byte1]: 45
3350 18:03:44.295367
3351 18:03:44.295773 Set Vref, RX VrefLevel [Byte0]: 46
3352 18:03:44.298814 [Byte1]: 46
3353 18:03:44.303431
3354 18:03:44.303838 Set Vref, RX VrefLevel [Byte0]: 47
3355 18:03:44.306948 [Byte1]: 47
3356 18:03:44.311159
3357 18:03:44.311565 Set Vref, RX VrefLevel [Byte0]: 48
3358 18:03:44.315096 [Byte1]: 48
3359 18:03:44.319036
3360 18:03:44.319450 Set Vref, RX VrefLevel [Byte0]: 49
3361 18:03:44.322364 [Byte1]: 49
3362 18:03:44.327032
3363 18:03:44.327436 Set Vref, RX VrefLevel [Byte0]: 50
3364 18:03:44.330987 [Byte1]: 50
3365 18:03:44.335024
3366 18:03:44.335438 Set Vref, RX VrefLevel [Byte0]: 51
3367 18:03:44.338224 [Byte1]: 51
3368 18:03:44.343129
3369 18:03:44.343536 Set Vref, RX VrefLevel [Byte0]: 52
3370 18:03:44.346172 [Byte1]: 52
3371 18:03:44.350604
3372 18:03:44.351010 Set Vref, RX VrefLevel [Byte0]: 53
3373 18:03:44.354370 [Byte1]: 53
3374 18:03:44.358965
3375 18:03:44.359658 Set Vref, RX VrefLevel [Byte0]: 54
3376 18:03:44.361961 [Byte1]: 54
3377 18:03:44.366718
3378 18:03:44.367132 Set Vref, RX VrefLevel [Byte0]: 55
3379 18:03:44.369714 [Byte1]: 55
3380 18:03:44.374786
3381 18:03:44.375236 Set Vref, RX VrefLevel [Byte0]: 56
3382 18:03:44.377730 [Byte1]: 56
3383 18:03:44.382266
3384 18:03:44.382701 Set Vref, RX VrefLevel [Byte0]: 57
3385 18:03:44.385585 [Byte1]: 57
3386 18:03:44.390522
3387 18:03:44.390812 Set Vref, RX VrefLevel [Byte0]: 58
3388 18:03:44.393415 [Byte1]: 58
3389 18:03:44.398160
3390 18:03:44.398528 Set Vref, RX VrefLevel [Byte0]: 59
3391 18:03:44.401547 [Byte1]: 59
3392 18:03:44.405618
3393 18:03:44.405909 Set Vref, RX VrefLevel [Byte0]: 60
3394 18:03:44.409042 [Byte1]: 60
3395 18:03:44.413662
3396 18:03:44.413772 Set Vref, RX VrefLevel [Byte0]: 61
3397 18:03:44.417095 [Byte1]: 61
3398 18:03:44.421871
3399 18:03:44.421970 Set Vref, RX VrefLevel [Byte0]: 62
3400 18:03:44.425331 [Byte1]: 62
3401 18:03:44.429845
3402 18:03:44.429926 Set Vref, RX VrefLevel [Byte0]: 63
3403 18:03:44.432832 [Byte1]: 63
3404 18:03:44.437359
3405 18:03:44.437440 Set Vref, RX VrefLevel [Byte0]: 64
3406 18:03:44.440937 [Byte1]: 64
3407 18:03:44.445383
3408 18:03:44.445540 Set Vref, RX VrefLevel [Byte0]: 65
3409 18:03:44.448574 [Byte1]: 65
3410 18:03:44.453322
3411 18:03:44.453402 Set Vref, RX VrefLevel [Byte0]: 66
3412 18:03:44.456740 [Byte1]: 66
3413 18:03:44.461354
3414 18:03:44.461445 Set Vref, RX VrefLevel [Byte0]: 67
3415 18:03:44.464333 [Byte1]: 67
3416 18:03:44.469577
3417 18:03:44.469895 Set Vref, RX VrefLevel [Byte0]: 68
3418 18:03:44.473005 [Byte1]: 68
3419 18:03:44.477337
3420 18:03:44.477575 Set Vref, RX VrefLevel [Byte0]: 69
3421 18:03:44.480583 [Byte1]: 69
3422 18:03:44.485535
3423 18:03:44.485942 Set Vref, RX VrefLevel [Byte0]: 70
3424 18:03:44.488834 [Byte1]: 70
3425 18:03:44.493642
3426 18:03:44.494049 Final RX Vref Byte 0 = 56 to rank0
3427 18:03:44.496747 Final RX Vref Byte 1 = 53 to rank0
3428 18:03:44.500221 Final RX Vref Byte 0 = 56 to rank1
3429 18:03:44.503292 Final RX Vref Byte 1 = 53 to rank1==
3430 18:03:44.506890 Dram Type= 6, Freq= 0, CH_1, rank 0
3431 18:03:44.510473 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3432 18:03:44.513336 ==
3433 18:03:44.513745 DQS Delay:
3434 18:03:44.514073 DQS0 = 0, DQS1 = 0
3435 18:03:44.516647 DQM Delay:
3436 18:03:44.517075 DQM0 = 116, DQM1 = 109
3437 18:03:44.520297 DQ Delay:
3438 18:03:44.523637 DQ0 =118, DQ1 =108, DQ2 =106, DQ3 =114
3439 18:03:44.527179 DQ4 =114, DQ5 =126, DQ6 =128, DQ7 =114
3440 18:03:44.530462 DQ8 =98, DQ9 =98, DQ10 =114, DQ11 =104
3441 18:03:44.533967 DQ12 =116, DQ13 =116, DQ14 =116, DQ15 =114
3442 18:03:44.534476
3443 18:03:44.534805
3444 18:03:44.540443 [DQSOSCAuto] RK0, (LSB)MR18= 0xffe4, (MSB)MR19= 0x303, tDQSOscB0 = 421 ps tDQSOscB1 = 410 ps
3445 18:03:44.543803 CH1 RK0: MR19=303, MR18=FFE4
3446 18:03:44.550526 CH1_RK0: MR19=0x303, MR18=0xFFE4, DQSOSC=410, MR23=63, INC=39, DEC=26
3447 18:03:44.551036
3448 18:03:44.553596 ----->DramcWriteLeveling(PI) begin...
3449 18:03:44.554021 ==
3450 18:03:44.557252 Dram Type= 6, Freq= 0, CH_1, rank 1
3451 18:03:44.561083 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3452 18:03:44.561598 ==
3453 18:03:44.563920 Write leveling (Byte 0): 27 => 27
3454 18:03:44.567063 Write leveling (Byte 1): 27 => 27
3455 18:03:44.570559 DramcWriteLeveling(PI) end<-----
3456 18:03:44.570984
3457 18:03:44.571309 ==
3458 18:03:44.573532 Dram Type= 6, Freq= 0, CH_1, rank 1
3459 18:03:44.577480 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3460 18:03:44.580911 ==
3461 18:03:44.581527 [Gating] SW mode calibration
3462 18:03:44.587859 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3463 18:03:44.593877 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3464 18:03:44.597392 0 15 0 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
3465 18:03:44.603703 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3466 18:03:44.607077 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3467 18:03:44.610488 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3468 18:03:44.617363 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3469 18:03:44.620644 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3470 18:03:44.624529 0 15 24 | B1->B0 | 3434 2a2a | 0 1 | (0 0) (1 0)
3471 18:03:44.627910 0 15 28 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
3472 18:03:44.634532 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3473 18:03:44.637598 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3474 18:03:44.641163 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3475 18:03:44.647360 1 0 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3476 18:03:44.651251 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3477 18:03:44.654432 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3478 18:03:44.660732 1 0 24 | B1->B0 | 2424 3c3c | 1 0 | (0 0) (0 0)
3479 18:03:44.664418 1 0 28 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
3480 18:03:44.667887 1 1 0 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
3481 18:03:44.674230 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3482 18:03:44.677209 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3483 18:03:44.680904 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3484 18:03:44.687820 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3485 18:03:44.690661 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3486 18:03:44.694241 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3487 18:03:44.701193 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3488 18:03:44.704631 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3489 18:03:44.707335 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3490 18:03:44.710770 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3491 18:03:44.717703 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3492 18:03:44.721115 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3493 18:03:44.724698 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3494 18:03:44.730908 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3495 18:03:44.734046 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3496 18:03:44.737251 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3497 18:03:44.744503 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3498 18:03:44.747581 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3499 18:03:44.751052 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3500 18:03:44.757449 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3501 18:03:44.761025 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3502 18:03:44.764173 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3503 18:03:44.770988 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3504 18:03:44.773799 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3505 18:03:44.777571 Total UI for P1: 0, mck2ui 16
3506 18:03:44.781035 best dqsien dly found for B0: ( 1, 3, 24)
3507 18:03:44.783934 Total UI for P1: 0, mck2ui 16
3508 18:03:44.787518 best dqsien dly found for B1: ( 1, 3, 30)
3509 18:03:44.790927 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3510 18:03:44.794339 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
3511 18:03:44.794753
3512 18:03:44.797294 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3513 18:03:44.800958 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
3514 18:03:44.804104 [Gating] SW calibration Done
3515 18:03:44.804518 ==
3516 18:03:44.807418 Dram Type= 6, Freq= 0, CH_1, rank 1
3517 18:03:44.810828 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3518 18:03:44.811246 ==
3519 18:03:44.813911 RX Vref Scan: 0
3520 18:03:44.814323
3521 18:03:44.817107 RX Vref 0 -> 0, step: 1
3522 18:03:44.817522
3523 18:03:44.817850 RX Delay -40 -> 252, step: 8
3524 18:03:44.824321 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3525 18:03:44.827355 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3526 18:03:44.831010 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3527 18:03:44.834372 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3528 18:03:44.837724 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3529 18:03:44.844170 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3530 18:03:44.847122 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
3531 18:03:44.850884 iDelay=200, Bit 7, Center 107 (40 ~ 175) 136
3532 18:03:44.854099 iDelay=200, Bit 8, Center 103 (32 ~ 175) 144
3533 18:03:44.857333 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3534 18:03:44.863891 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3535 18:03:44.867544 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3536 18:03:44.870866 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3537 18:03:44.874140 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3538 18:03:44.877519 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3539 18:03:44.884006 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3540 18:03:44.884417 ==
3541 18:03:44.887414 Dram Type= 6, Freq= 0, CH_1, rank 1
3542 18:03:44.890883 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3543 18:03:44.891402 ==
3544 18:03:44.891922 DQS Delay:
3545 18:03:44.894325 DQS0 = 0, DQS1 = 0
3546 18:03:44.894910 DQM Delay:
3547 18:03:44.897391 DQM0 = 113, DQM1 = 111
3548 18:03:44.897936 DQ Delay:
3549 18:03:44.900890 DQ0 =115, DQ1 =111, DQ2 =103, DQ3 =111
3550 18:03:44.904453 DQ4 =111, DQ5 =127, DQ6 =119, DQ7 =107
3551 18:03:44.907359 DQ8 =103, DQ9 =95, DQ10 =111, DQ11 =103
3552 18:03:44.910894 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3553 18:03:44.911384
3554 18:03:44.911944
3555 18:03:44.914140 ==
3556 18:03:44.914664 Dram Type= 6, Freq= 0, CH_1, rank 1
3557 18:03:44.920698 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3558 18:03:44.921062 ==
3559 18:03:44.921306
3560 18:03:44.921545
3561 18:03:44.923775 TX Vref Scan disable
3562 18:03:44.923998 == TX Byte 0 ==
3563 18:03:44.927464 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3564 18:03:44.933873 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3565 18:03:44.934043 == TX Byte 1 ==
3566 18:03:44.937306 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3567 18:03:44.943853 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3568 18:03:44.944029 ==
3569 18:03:44.947134 Dram Type= 6, Freq= 0, CH_1, rank 1
3570 18:03:44.950561 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3571 18:03:44.950806 ==
3572 18:03:44.962074 TX Vref=22, minBit 1, minWin=25, winSum=418
3573 18:03:44.965261 TX Vref=24, minBit 1, minWin=25, winSum=421
3574 18:03:44.969113 TX Vref=26, minBit 0, minWin=26, winSum=426
3575 18:03:44.972312 TX Vref=28, minBit 2, minWin=26, winSum=430
3576 18:03:44.975537 TX Vref=30, minBit 2, minWin=26, winSum=433
3577 18:03:44.979077 TX Vref=32, minBit 1, minWin=26, winSum=431
3578 18:03:44.985337 [TxChooseVref] Worse bit 2, Min win 26, Win sum 433, Final Vref 30
3579 18:03:44.985467
3580 18:03:44.988844 Final TX Range 1 Vref 30
3581 18:03:44.989009
3582 18:03:44.989127 ==
3583 18:03:44.992464 Dram Type= 6, Freq= 0, CH_1, rank 1
3584 18:03:44.995224 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3585 18:03:44.995387 ==
3586 18:03:44.995548
3587 18:03:44.998972
3588 18:03:44.999176 TX Vref Scan disable
3589 18:03:45.002312 == TX Byte 0 ==
3590 18:03:45.005427 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3591 18:03:45.009040 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3592 18:03:45.012561 == TX Byte 1 ==
3593 18:03:45.015593 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3594 18:03:45.019020 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3595 18:03:45.019548
3596 18:03:45.022479 [DATLAT]
3597 18:03:45.022888 Freq=1200, CH1 RK1
3598 18:03:45.023305
3599 18:03:45.025697 DATLAT Default: 0xd
3600 18:03:45.026239 0, 0xFFFF, sum = 0
3601 18:03:45.029369 1, 0xFFFF, sum = 0
3602 18:03:45.029895 2, 0xFFFF, sum = 0
3603 18:03:45.032338 3, 0xFFFF, sum = 0
3604 18:03:45.032794 4, 0xFFFF, sum = 0
3605 18:03:45.035702 5, 0xFFFF, sum = 0
3606 18:03:45.036119 6, 0xFFFF, sum = 0
3607 18:03:45.039329 7, 0xFFFF, sum = 0
3608 18:03:45.039816 8, 0xFFFF, sum = 0
3609 18:03:45.042229 9, 0xFFFF, sum = 0
3610 18:03:45.045876 10, 0xFFFF, sum = 0
3611 18:03:45.046313 11, 0xFFFF, sum = 0
3612 18:03:45.048714 12, 0x0, sum = 1
3613 18:03:45.049155 13, 0x0, sum = 2
3614 18:03:45.049494 14, 0x0, sum = 3
3615 18:03:45.052358 15, 0x0, sum = 4
3616 18:03:45.052815 best_step = 13
3617 18:03:45.053212
3618 18:03:45.053528 ==
3619 18:03:45.055898 Dram Type= 6, Freq= 0, CH_1, rank 1
3620 18:03:45.062466 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3621 18:03:45.062878 ==
3622 18:03:45.063262 RX Vref Scan: 0
3623 18:03:45.063573
3624 18:03:45.065880 RX Vref 0 -> 0, step: 1
3625 18:03:45.066317
3626 18:03:45.069143 RX Delay -21 -> 252, step: 4
3627 18:03:45.072581 iDelay=191, Bit 0, Center 112 (43 ~ 182) 140
3628 18:03:45.076197 iDelay=191, Bit 1, Center 110 (43 ~ 178) 136
3629 18:03:45.082565 iDelay=191, Bit 2, Center 106 (43 ~ 170) 128
3630 18:03:45.085836 iDelay=191, Bit 3, Center 112 (47 ~ 178) 132
3631 18:03:45.089135 iDelay=191, Bit 4, Center 114 (47 ~ 182) 136
3632 18:03:45.092277 iDelay=191, Bit 5, Center 124 (59 ~ 190) 132
3633 18:03:45.095934 iDelay=191, Bit 6, Center 122 (55 ~ 190) 136
3634 18:03:45.102471 iDelay=191, Bit 7, Center 110 (47 ~ 174) 128
3635 18:03:45.105981 iDelay=191, Bit 8, Center 98 (31 ~ 166) 136
3636 18:03:45.109379 iDelay=191, Bit 9, Center 98 (35 ~ 162) 128
3637 18:03:45.112446 iDelay=191, Bit 10, Center 110 (43 ~ 178) 136
3638 18:03:45.115754 iDelay=191, Bit 11, Center 102 (35 ~ 170) 136
3639 18:03:45.122339 iDelay=191, Bit 12, Center 114 (51 ~ 178) 128
3640 18:03:45.125703 iDelay=191, Bit 13, Center 120 (55 ~ 186) 132
3641 18:03:45.129224 iDelay=191, Bit 14, Center 118 (55 ~ 182) 128
3642 18:03:45.132338 iDelay=191, Bit 15, Center 118 (55 ~ 182) 128
3643 18:03:45.132901 ==
3644 18:03:45.136264 Dram Type= 6, Freq= 0, CH_1, rank 1
3645 18:03:45.139335 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3646 18:03:45.142787 ==
3647 18:03:45.143256 DQS Delay:
3648 18:03:45.143582 DQS0 = 0, DQS1 = 0
3649 18:03:45.145626 DQM Delay:
3650 18:03:45.146032 DQM0 = 113, DQM1 = 109
3651 18:03:45.149255 DQ Delay:
3652 18:03:45.152656 DQ0 =112, DQ1 =110, DQ2 =106, DQ3 =112
3653 18:03:45.156472 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =110
3654 18:03:45.159642 DQ8 =98, DQ9 =98, DQ10 =110, DQ11 =102
3655 18:03:45.162801 DQ12 =114, DQ13 =120, DQ14 =118, DQ15 =118
3656 18:03:45.163215
3657 18:03:45.163542
3658 18:03:45.169225 [DQSOSCAuto] RK1, (LSB)MR18= 0xf4fb, (MSB)MR19= 0x303, tDQSOscB0 = 412 ps tDQSOscB1 = 415 ps
3659 18:03:45.173022 CH1 RK1: MR19=303, MR18=F4FB
3660 18:03:45.179022 CH1_RK1: MR19=0x303, MR18=0xF4FB, DQSOSC=412, MR23=63, INC=38, DEC=25
3661 18:03:45.182390 [RxdqsGatingPostProcess] freq 1200
3662 18:03:45.189173 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3663 18:03:45.192238 best DQS0 dly(2T, 0.5T) = (0, 11)
3664 18:03:45.192692 best DQS1 dly(2T, 0.5T) = (0, 12)
3665 18:03:45.195914 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3666 18:03:45.199445 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3667 18:03:45.202706 best DQS0 dly(2T, 0.5T) = (0, 11)
3668 18:03:45.205982 best DQS1 dly(2T, 0.5T) = (0, 11)
3669 18:03:45.209385 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3670 18:03:45.212920 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3671 18:03:45.215811 Pre-setting of DQS Precalculation
3672 18:03:45.222528 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3673 18:03:45.229287 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3674 18:03:45.235789 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3675 18:03:45.236208
3676 18:03:45.236532
3677 18:03:45.238935 [Calibration Summary] 2400 Mbps
3678 18:03:45.239347 CH 0, Rank 0
3679 18:03:45.242798 SW Impedance : PASS
3680 18:03:45.243304 DUTY Scan : NO K
3681 18:03:45.245648 ZQ Calibration : PASS
3682 18:03:45.249065 Jitter Meter : NO K
3683 18:03:45.249542 CBT Training : PASS
3684 18:03:45.252471 Write leveling : PASS
3685 18:03:45.256256 RX DQS gating : PASS
3686 18:03:45.256670 RX DQ/DQS(RDDQC) : PASS
3687 18:03:45.259200 TX DQ/DQS : PASS
3688 18:03:45.262634 RX DATLAT : PASS
3689 18:03:45.263048 RX DQ/DQS(Engine): PASS
3690 18:03:45.266272 TX OE : NO K
3691 18:03:45.266719 All Pass.
3692 18:03:45.267054
3693 18:03:45.269103 CH 0, Rank 1
3694 18:03:45.269517 SW Impedance : PASS
3695 18:03:45.272635 DUTY Scan : NO K
3696 18:03:45.275982 ZQ Calibration : PASS
3697 18:03:45.276445 Jitter Meter : NO K
3698 18:03:45.279423 CBT Training : PASS
3699 18:03:45.279834 Write leveling : PASS
3700 18:03:45.282718 RX DQS gating : PASS
3701 18:03:45.286065 RX DQ/DQS(RDDQC) : PASS
3702 18:03:45.286477 TX DQ/DQS : PASS
3703 18:03:45.289456 RX DATLAT : PASS
3704 18:03:45.292854 RX DQ/DQS(Engine): PASS
3705 18:03:45.293296 TX OE : NO K
3706 18:03:45.295827 All Pass.
3707 18:03:45.296234
3708 18:03:45.296560 CH 1, Rank 0
3709 18:03:45.299280 SW Impedance : PASS
3710 18:03:45.299695 DUTY Scan : NO K
3711 18:03:45.302630 ZQ Calibration : PASS
3712 18:03:45.305838 Jitter Meter : NO K
3713 18:03:45.306252 CBT Training : PASS
3714 18:03:45.309284 Write leveling : PASS
3715 18:03:45.312566 RX DQS gating : PASS
3716 18:03:45.313011 RX DQ/DQS(RDDQC) : PASS
3717 18:03:45.316048 TX DQ/DQS : PASS
3718 18:03:45.319059 RX DATLAT : PASS
3719 18:03:45.319576 RX DQ/DQS(Engine): PASS
3720 18:03:45.322450 TX OE : NO K
3721 18:03:45.322862 All Pass.
3722 18:03:45.323206
3723 18:03:45.323694 CH 1, Rank 1
3724 18:03:45.325981 SW Impedance : PASS
3725 18:03:45.329406 DUTY Scan : NO K
3726 18:03:45.329842 ZQ Calibration : PASS
3727 18:03:45.332807 Jitter Meter : NO K
3728 18:03:45.335834 CBT Training : PASS
3729 18:03:45.336246 Write leveling : PASS
3730 18:03:45.339311 RX DQS gating : PASS
3731 18:03:45.342895 RX DQ/DQS(RDDQC) : PASS
3732 18:03:45.343405 TX DQ/DQS : PASS
3733 18:03:45.345798 RX DATLAT : PASS
3734 18:03:45.349460 RX DQ/DQS(Engine): PASS
3735 18:03:45.349873 TX OE : NO K
3736 18:03:45.352358 All Pass.
3737 18:03:45.352790
3738 18:03:45.353165 DramC Write-DBI off
3739 18:03:45.355867 PER_BANK_REFRESH: Hybrid Mode
3740 18:03:45.356318 TX_TRACKING: ON
3741 18:03:45.365947 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3742 18:03:45.369034 [FAST_K] Save calibration result to emmc
3743 18:03:45.372384 dramc_set_vcore_voltage set vcore to 650000
3744 18:03:45.375843 Read voltage for 600, 5
3745 18:03:45.376352 Vio18 = 0
3746 18:03:45.379363 Vcore = 650000
3747 18:03:45.379932 Vdram = 0
3748 18:03:45.380273 Vddq = 0
3749 18:03:45.380586 Vmddr = 0
3750 18:03:45.386146 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3751 18:03:45.392559 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3752 18:03:45.393172 MEM_TYPE=3, freq_sel=19
3753 18:03:45.396046 sv_algorithm_assistance_LP4_1600
3754 18:03:45.399516 ============ PULL DRAM RESETB DOWN ============
3755 18:03:45.405675 ========== PULL DRAM RESETB DOWN end =========
3756 18:03:45.409445 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3757 18:03:45.412618 ===================================
3758 18:03:45.415681 LPDDR4 DRAM CONFIGURATION
3759 18:03:45.419581 ===================================
3760 18:03:45.420117 EX_ROW_EN[0] = 0x0
3761 18:03:45.422757 EX_ROW_EN[1] = 0x0
3762 18:03:45.423207 LP4Y_EN = 0x0
3763 18:03:45.426366 WORK_FSP = 0x0
3764 18:03:45.426762 WL = 0x2
3765 18:03:45.429319 RL = 0x2
3766 18:03:45.429833 BL = 0x2
3767 18:03:45.432720 RPST = 0x0
3768 18:03:45.436034 RD_PRE = 0x0
3769 18:03:45.436615 WR_PRE = 0x1
3770 18:03:45.439209 WR_PST = 0x0
3771 18:03:45.439742 DBI_WR = 0x0
3772 18:03:45.442647 DBI_RD = 0x0
3773 18:03:45.443188 OTF = 0x1
3774 18:03:45.446137 ===================================
3775 18:03:45.449496 ===================================
3776 18:03:45.450043 ANA top config
3777 18:03:45.452891 ===================================
3778 18:03:45.455819 DLL_ASYNC_EN = 0
3779 18:03:45.459010 ALL_SLAVE_EN = 1
3780 18:03:45.462650 NEW_RANK_MODE = 1
3781 18:03:45.465774 DLL_IDLE_MODE = 1
3782 18:03:45.466210 LP45_APHY_COMB_EN = 1
3783 18:03:45.469232 TX_ODT_DIS = 1
3784 18:03:45.472546 NEW_8X_MODE = 1
3785 18:03:45.475652 ===================================
3786 18:03:45.479441 ===================================
3787 18:03:45.482897 data_rate = 1200
3788 18:03:45.485948 CKR = 1
3789 18:03:45.486361 DQ_P2S_RATIO = 8
3790 18:03:45.489228 ===================================
3791 18:03:45.492498 CA_P2S_RATIO = 8
3792 18:03:45.495905 DQ_CA_OPEN = 0
3793 18:03:45.499344 DQ_SEMI_OPEN = 0
3794 18:03:45.502625 CA_SEMI_OPEN = 0
3795 18:03:45.506313 CA_FULL_RATE = 0
3796 18:03:45.506754 DQ_CKDIV4_EN = 1
3797 18:03:45.509607 CA_CKDIV4_EN = 1
3798 18:03:45.512903 CA_PREDIV_EN = 0
3799 18:03:45.515880 PH8_DLY = 0
3800 18:03:45.519370 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3801 18:03:45.519613 DQ_AAMCK_DIV = 4
3802 18:03:45.522794 CA_AAMCK_DIV = 4
3803 18:03:45.525568 CA_ADMCK_DIV = 4
3804 18:03:45.528957 DQ_TRACK_CA_EN = 0
3805 18:03:45.532399 CA_PICK = 600
3806 18:03:45.535952 CA_MCKIO = 600
3807 18:03:45.536080 MCKIO_SEMI = 0
3808 18:03:45.539210 PLL_FREQ = 2288
3809 18:03:45.542500 DQ_UI_PI_RATIO = 32
3810 18:03:45.545992 CA_UI_PI_RATIO = 0
3811 18:03:45.548941 ===================================
3812 18:03:45.552586 ===================================
3813 18:03:45.556060 memory_type:LPDDR4
3814 18:03:45.556145 GP_NUM : 10
3815 18:03:45.559552 SRAM_EN : 1
3816 18:03:45.562855 MD32_EN : 0
3817 18:03:45.566008 ===================================
3818 18:03:45.566092 [ANA_INIT] >>>>>>>>>>>>>>
3819 18:03:45.569153 <<<<<< [CONFIGURE PHASE]: ANA_TX
3820 18:03:45.572612 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3821 18:03:45.576134 ===================================
3822 18:03:45.579229 data_rate = 1200,PCW = 0X5800
3823 18:03:45.582634 ===================================
3824 18:03:45.585756 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3825 18:03:45.592285 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3826 18:03:45.595709 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3827 18:03:45.602442 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3828 18:03:45.605692 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3829 18:03:45.609069 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3830 18:03:45.609154 [ANA_INIT] flow start
3831 18:03:45.612582 [ANA_INIT] PLL >>>>>>>>
3832 18:03:45.615595 [ANA_INIT] PLL <<<<<<<<
3833 18:03:45.619334 [ANA_INIT] MIDPI >>>>>>>>
3834 18:03:45.619789 [ANA_INIT] MIDPI <<<<<<<<
3835 18:03:45.622363 [ANA_INIT] DLL >>>>>>>>
3836 18:03:45.622809 [ANA_INIT] flow end
3837 18:03:45.629410 ============ LP4 DIFF to SE enter ============
3838 18:03:45.632854 ============ LP4 DIFF to SE exit ============
3839 18:03:45.635708 [ANA_INIT] <<<<<<<<<<<<<
3840 18:03:45.639217 [Flow] Enable top DCM control >>>>>
3841 18:03:45.642585 [Flow] Enable top DCM control <<<<<
3842 18:03:45.646025 Enable DLL master slave shuffle
3843 18:03:45.649358 ==============================================================
3844 18:03:45.652485 Gating Mode config
3845 18:03:45.655953 ==============================================================
3846 18:03:45.659580 Config description:
3847 18:03:45.669495 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3848 18:03:45.676050 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3849 18:03:45.679415 SELPH_MODE 0: By rank 1: By Phase
3850 18:03:45.685942 ==============================================================
3851 18:03:45.689508 GAT_TRACK_EN = 1
3852 18:03:45.692887 RX_GATING_MODE = 2
3853 18:03:45.695741 RX_GATING_TRACK_MODE = 2
3854 18:03:45.699283 SELPH_MODE = 1
3855 18:03:45.699713 PICG_EARLY_EN = 1
3856 18:03:45.702506 VALID_LAT_VALUE = 1
3857 18:03:45.709476 ==============================================================
3858 18:03:45.712796 Enter into Gating configuration >>>>
3859 18:03:45.716214 Exit from Gating configuration <<<<
3860 18:03:45.719046 Enter into DVFS_PRE_config >>>>>
3861 18:03:45.729058 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3862 18:03:45.732618 Exit from DVFS_PRE_config <<<<<
3863 18:03:45.736143 Enter into PICG configuration >>>>
3864 18:03:45.739633 Exit from PICG configuration <<<<
3865 18:03:45.742452 [RX_INPUT] configuration >>>>>
3866 18:03:45.745798 [RX_INPUT] configuration <<<<<
3867 18:03:45.749430 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3868 18:03:45.755995 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3869 18:03:45.762536 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3870 18:03:45.769396 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3871 18:03:45.772560 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3872 18:03:45.779377 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3873 18:03:45.785770 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3874 18:03:45.789460 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3875 18:03:45.792388 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3876 18:03:45.795942 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3877 18:03:45.799435 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3878 18:03:45.805829 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3879 18:03:45.808914 ===================================
3880 18:03:45.812553 LPDDR4 DRAM CONFIGURATION
3881 18:03:45.816147 ===================================
3882 18:03:45.816673 EX_ROW_EN[0] = 0x0
3883 18:03:45.819557 EX_ROW_EN[1] = 0x0
3884 18:03:45.820094 LP4Y_EN = 0x0
3885 18:03:45.822475 WORK_FSP = 0x0
3886 18:03:45.822935 WL = 0x2
3887 18:03:45.825839 RL = 0x2
3888 18:03:45.826249 BL = 0x2
3889 18:03:45.829131 RPST = 0x0
3890 18:03:45.829544 RD_PRE = 0x0
3891 18:03:45.832105 WR_PRE = 0x1
3892 18:03:45.832532 WR_PST = 0x0
3893 18:03:45.835564 DBI_WR = 0x0
3894 18:03:45.835987 DBI_RD = 0x0
3895 18:03:45.839170 OTF = 0x1
3896 18:03:45.842079 ===================================
3897 18:03:45.845704 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3898 18:03:45.848993 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3899 18:03:45.855596 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3900 18:03:45.859471 ===================================
3901 18:03:45.859988 LPDDR4 DRAM CONFIGURATION
3902 18:03:45.862410 ===================================
3903 18:03:45.865733 EX_ROW_EN[0] = 0x10
3904 18:03:45.868846 EX_ROW_EN[1] = 0x0
3905 18:03:45.869304 LP4Y_EN = 0x0
3906 18:03:45.872650 WORK_FSP = 0x0
3907 18:03:45.873281 WL = 0x2
3908 18:03:45.875692 RL = 0x2
3909 18:03:45.876119 BL = 0x2
3910 18:03:45.879143 RPST = 0x0
3911 18:03:45.879553 RD_PRE = 0x0
3912 18:03:45.882414 WR_PRE = 0x1
3913 18:03:45.882825 WR_PST = 0x0
3914 18:03:45.885403 DBI_WR = 0x0
3915 18:03:45.885816 DBI_RD = 0x0
3916 18:03:45.888804 OTF = 0x1
3917 18:03:45.891931 ===================================
3918 18:03:45.899090 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3919 18:03:45.902045 nWR fixed to 30
3920 18:03:45.902472 [ModeRegInit_LP4] CH0 RK0
3921 18:03:45.905509 [ModeRegInit_LP4] CH0 RK1
3922 18:03:45.908972 [ModeRegInit_LP4] CH1 RK0
3923 18:03:45.912000 [ModeRegInit_LP4] CH1 RK1
3924 18:03:45.912409 match AC timing 17
3925 18:03:45.918673 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3926 18:03:45.922213 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3927 18:03:45.925460 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3928 18:03:45.932285 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3929 18:03:45.935600 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3930 18:03:45.936013 ==
3931 18:03:45.938549 Dram Type= 6, Freq= 0, CH_0, rank 0
3932 18:03:45.942112 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3933 18:03:45.942525 ==
3934 18:03:45.948724 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3935 18:03:45.955276 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3936 18:03:45.958700 [CA 0] Center 36 (6~67) winsize 62
3937 18:03:45.962331 [CA 1] Center 36 (6~66) winsize 61
3938 18:03:45.965785 [CA 2] Center 34 (4~65) winsize 62
3939 18:03:45.969042 [CA 3] Center 34 (4~65) winsize 62
3940 18:03:45.972566 [CA 4] Center 33 (3~64) winsize 62
3941 18:03:45.975959 [CA 5] Center 33 (3~64) winsize 62
3942 18:03:45.976370
3943 18:03:45.978767 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3944 18:03:45.979218
3945 18:03:45.982502 [CATrainingPosCal] consider 1 rank data
3946 18:03:45.985573 u2DelayCellTimex100 = 270/100 ps
3947 18:03:45.988899 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3948 18:03:45.992298 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3949 18:03:45.995323 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3950 18:03:45.998677 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3951 18:03:46.002371 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3952 18:03:46.005510 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3953 18:03:46.005920
3954 18:03:46.009011 CA PerBit enable=1, Macro0, CA PI delay=33
3955 18:03:46.009449
3956 18:03:46.011925 [CBTSetCACLKResult] CA Dly = 33
3957 18:03:46.015416 CS Dly: 5 (0~36)
3958 18:03:46.015829 ==
3959 18:03:46.018878 Dram Type= 6, Freq= 0, CH_0, rank 1
3960 18:03:46.022352 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3961 18:03:46.022780 ==
3962 18:03:46.029231 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3963 18:03:46.035945 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3964 18:03:46.039295 [CA 0] Center 36 (6~67) winsize 62
3965 18:03:46.042749 [CA 1] Center 35 (5~66) winsize 62
3966 18:03:46.045563 [CA 2] Center 34 (4~65) winsize 62
3967 18:03:46.049451 [CA 3] Center 34 (4~65) winsize 62
3968 18:03:46.052461 [CA 4] Center 33 (3~64) winsize 62
3969 18:03:46.055506 [CA 5] Center 33 (3~64) winsize 62
3970 18:03:46.055934
3971 18:03:46.058873 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3972 18:03:46.059299
3973 18:03:46.062529 [CATrainingPosCal] consider 2 rank data
3974 18:03:46.065415 u2DelayCellTimex100 = 270/100 ps
3975 18:03:46.068998 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3976 18:03:46.072703 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3977 18:03:46.075418 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3978 18:03:46.078662 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3979 18:03:46.082299 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3980 18:03:46.085830 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3981 18:03:46.086245
3982 18:03:46.088745 CA PerBit enable=1, Macro0, CA PI delay=33
3983 18:03:46.092075
3984 18:03:46.092502 [CBTSetCACLKResult] CA Dly = 33
3985 18:03:46.095462 CS Dly: 5 (0~36)
3986 18:03:46.095867
3987 18:03:46.098845 ----->DramcWriteLeveling(PI) begin...
3988 18:03:46.099385 ==
3989 18:03:46.102161 Dram Type= 6, Freq= 0, CH_0, rank 0
3990 18:03:46.105412 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3991 18:03:46.105827 ==
3992 18:03:46.108649 Write leveling (Byte 0): 32 => 32
3993 18:03:46.111883 Write leveling (Byte 1): 28 => 28
3994 18:03:46.115165 DramcWriteLeveling(PI) end<-----
3995 18:03:46.115590
3996 18:03:46.116018 ==
3997 18:03:46.118786 Dram Type= 6, Freq= 0, CH_0, rank 0
3998 18:03:46.121691 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3999 18:03:46.125051 ==
4000 18:03:46.125498 [Gating] SW mode calibration
4001 18:03:46.132028 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4002 18:03:46.138749 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4003 18:03:46.142035 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4004 18:03:46.148807 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4005 18:03:46.151718 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4006 18:03:46.155216 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4007 18:03:46.162356 0 9 16 | B1->B0 | 3030 2c2c | 0 0 | (1 0) (1 1)
4008 18:03:46.165081 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4009 18:03:46.168478 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4010 18:03:46.175555 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4011 18:03:46.178394 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4012 18:03:46.181588 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4013 18:03:46.185025 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4014 18:03:46.192059 0 10 12 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4015 18:03:46.195428 0 10 16 | B1->B0 | 3131 3a3a | 0 0 | (0 0) (0 0)
4016 18:03:46.198440 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4017 18:03:46.205123 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4018 18:03:46.208500 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4019 18:03:46.212161 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4020 18:03:46.218732 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4021 18:03:46.221951 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4022 18:03:46.225002 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4023 18:03:46.231935 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4024 18:03:46.235444 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4025 18:03:46.238307 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4026 18:03:46.245016 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4027 18:03:46.248654 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4028 18:03:46.251905 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4029 18:03:46.258697 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4030 18:03:46.261826 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4031 18:03:46.265382 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4032 18:03:46.271713 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4033 18:03:46.275096 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4034 18:03:46.278772 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4035 18:03:46.282015 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4036 18:03:46.288347 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4037 18:03:46.291616 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4038 18:03:46.295200 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4039 18:03:46.301472 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4040 18:03:46.304949 Total UI for P1: 0, mck2ui 16
4041 18:03:46.308472 best dqsien dly found for B0: ( 0, 13, 14)
4042 18:03:46.311300 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4043 18:03:46.315205 Total UI for P1: 0, mck2ui 16
4044 18:03:46.318157 best dqsien dly found for B1: ( 0, 13, 16)
4045 18:03:46.321587 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4046 18:03:46.324586 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4047 18:03:46.324726
4048 18:03:46.328058 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4049 18:03:46.331630 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4050 18:03:46.334729 [Gating] SW calibration Done
4051 18:03:46.334915 ==
4052 18:03:46.338304 Dram Type= 6, Freq= 0, CH_0, rank 0
4053 18:03:46.345850 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4054 18:03:46.346030 ==
4055 18:03:46.346140 RX Vref Scan: 0
4056 18:03:46.346218
4057 18:03:46.348428 RX Vref 0 -> 0, step: 1
4058 18:03:46.348600
4059 18:03:46.351772 RX Delay -230 -> 252, step: 16
4060 18:03:46.354616 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4061 18:03:46.358094 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4062 18:03:46.361519 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4063 18:03:46.367911 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4064 18:03:46.371461 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4065 18:03:46.374768 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4066 18:03:46.378189 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4067 18:03:46.381933 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4068 18:03:46.388273 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4069 18:03:46.391641 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4070 18:03:46.395308 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4071 18:03:46.399179 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4072 18:03:46.401718 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4073 18:03:46.408528 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4074 18:03:46.412075 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4075 18:03:46.415572 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4076 18:03:46.415997 ==
4077 18:03:46.418259 Dram Type= 6, Freq= 0, CH_0, rank 0
4078 18:03:46.425314 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4079 18:03:46.425587 ==
4080 18:03:46.425766 DQS Delay:
4081 18:03:46.425932 DQS0 = 0, DQS1 = 0
4082 18:03:46.428655 DQM Delay:
4083 18:03:46.428938 DQM0 = 40, DQM1 = 31
4084 18:03:46.431610 DQ Delay:
4085 18:03:46.435000 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =33
4086 18:03:46.435182 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4087 18:03:46.438497 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4088 18:03:46.441488 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =41
4089 18:03:46.445042
4090 18:03:46.445199
4091 18:03:46.445343 ==
4092 18:03:46.448575 Dram Type= 6, Freq= 0, CH_0, rank 0
4093 18:03:46.451903 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4094 18:03:46.452063 ==
4095 18:03:46.452182
4096 18:03:46.452281
4097 18:03:46.455216 TX Vref Scan disable
4098 18:03:46.455337 == TX Byte 0 ==
4099 18:03:46.461810 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4100 18:03:46.465274 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4101 18:03:46.465425 == TX Byte 1 ==
4102 18:03:46.471816 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4103 18:03:46.475209 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4104 18:03:46.475343 ==
4105 18:03:46.478663 Dram Type= 6, Freq= 0, CH_0, rank 0
4106 18:03:46.481664 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4107 18:03:46.481794 ==
4108 18:03:46.481867
4109 18:03:46.481928
4110 18:03:46.485112 TX Vref Scan disable
4111 18:03:46.488574 == TX Byte 0 ==
4112 18:03:46.491400 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4113 18:03:46.494845 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4114 18:03:46.498191 == TX Byte 1 ==
4115 18:03:46.501415 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4116 18:03:46.504931 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4117 18:03:46.508800
4118 18:03:46.508960 [DATLAT]
4119 18:03:46.509049 Freq=600, CH0 RK0
4120 18:03:46.509112
4121 18:03:46.511917 DATLAT Default: 0x9
4122 18:03:46.512003 0, 0xFFFF, sum = 0
4123 18:03:46.515436 1, 0xFFFF, sum = 0
4124 18:03:46.515523 2, 0xFFFF, sum = 0
4125 18:03:46.518287 3, 0xFFFF, sum = 0
4126 18:03:46.518372 4, 0xFFFF, sum = 0
4127 18:03:46.521852 5, 0xFFFF, sum = 0
4128 18:03:46.521943 6, 0xFFFF, sum = 0
4129 18:03:46.525462 7, 0xFFFF, sum = 0
4130 18:03:46.525546 8, 0x0, sum = 1
4131 18:03:46.528789 9, 0x0, sum = 2
4132 18:03:46.528900 10, 0x0, sum = 3
4133 18:03:46.531942 11, 0x0, sum = 4
4134 18:03:46.532015 best_step = 9
4135 18:03:46.532077
4136 18:03:46.532136 ==
4137 18:03:46.535505 Dram Type= 6, Freq= 0, CH_0, rank 0
4138 18:03:46.538393 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4139 18:03:46.541903 ==
4140 18:03:46.541989 RX Vref Scan: 1
4141 18:03:46.542054
4142 18:03:46.545474 RX Vref 0 -> 0, step: 1
4143 18:03:46.545561
4144 18:03:46.548887 RX Delay -195 -> 252, step: 8
4145 18:03:46.549010
4146 18:03:46.552153 Set Vref, RX VrefLevel [Byte0]: 53
4147 18:03:46.555244 [Byte1]: 51
4148 18:03:46.555380
4149 18:03:46.558747 Final RX Vref Byte 0 = 53 to rank0
4150 18:03:46.561665 Final RX Vref Byte 1 = 51 to rank0
4151 18:03:46.565508 Final RX Vref Byte 0 = 53 to rank1
4152 18:03:46.568624 Final RX Vref Byte 1 = 51 to rank1==
4153 18:03:46.571964 Dram Type= 6, Freq= 0, CH_0, rank 0
4154 18:03:46.575327 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4155 18:03:46.575441 ==
4156 18:03:46.575511 DQS Delay:
4157 18:03:46.578567 DQS0 = 0, DQS1 = 0
4158 18:03:46.578662 DQM Delay:
4159 18:03:46.582011 DQM0 = 42, DQM1 = 33
4160 18:03:46.582114 DQ Delay:
4161 18:03:46.585399 DQ0 =44, DQ1 =44, DQ2 =36, DQ3 =40
4162 18:03:46.588476 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =52
4163 18:03:46.592097 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =28
4164 18:03:46.594936 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =44
4165 18:03:46.595133
4166 18:03:46.595252
4167 18:03:46.605554 [DQSOSCAuto] RK0, (LSB)MR18= 0x3c1a, (MSB)MR19= 0x808, tDQSOscB0 = 405 ps tDQSOscB1 = 398 ps
4168 18:03:46.605767 CH0 RK0: MR19=808, MR18=3C1A
4169 18:03:46.611583 CH0_RK0: MR19=0x808, MR18=0x3C1A, DQSOSC=398, MR23=63, INC=165, DEC=110
4170 18:03:46.611788
4171 18:03:46.615146 ----->DramcWriteLeveling(PI) begin...
4172 18:03:46.615402 ==
4173 18:03:46.618536 Dram Type= 6, Freq= 0, CH_0, rank 1
4174 18:03:46.625425 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4175 18:03:46.625637 ==
4176 18:03:46.628705 Write leveling (Byte 0): 33 => 33
4177 18:03:46.628872 Write leveling (Byte 1): 31 => 31
4178 18:03:46.631748 DramcWriteLeveling(PI) end<-----
4179 18:03:46.631881
4180 18:03:46.635264 ==
4181 18:03:46.635389 Dram Type= 6, Freq= 0, CH_0, rank 1
4182 18:03:46.642050 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4183 18:03:46.642174 ==
4184 18:03:46.644855 [Gating] SW mode calibration
4185 18:03:46.652046 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4186 18:03:46.655041 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4187 18:03:46.661555 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4188 18:03:46.665242 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4189 18:03:46.668409 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4190 18:03:46.675390 0 9 12 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
4191 18:03:46.678585 0 9 16 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
4192 18:03:46.681546 0 9 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4193 18:03:46.688630 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4194 18:03:46.691957 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4195 18:03:46.695049 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4196 18:03:46.701584 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4197 18:03:46.704968 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4198 18:03:46.708326 0 10 12 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
4199 18:03:46.711941 0 10 16 | B1->B0 | 3535 4646 | 1 0 | (0 0) (0 0)
4200 18:03:46.718792 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4201 18:03:46.722087 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4202 18:03:46.724875 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4203 18:03:46.731883 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4204 18:03:46.735168 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4205 18:03:46.738566 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4206 18:03:46.744922 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4207 18:03:46.748869 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4208 18:03:46.751636 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4209 18:03:46.758459 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4210 18:03:46.761692 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4211 18:03:46.765086 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4212 18:03:46.771952 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4213 18:03:46.775171 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4214 18:03:46.778508 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4215 18:03:46.784795 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4216 18:03:46.788611 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4217 18:03:46.791500 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4218 18:03:46.798163 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4219 18:03:46.801563 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4220 18:03:46.804951 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4221 18:03:46.808262 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4222 18:03:46.814972 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4223 18:03:46.818312 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4224 18:03:46.822033 Total UI for P1: 0, mck2ui 16
4225 18:03:46.825243 best dqsien dly found for B0: ( 0, 13, 12)
4226 18:03:46.828323 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4227 18:03:46.835179 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4228 18:03:46.838116 Total UI for P1: 0, mck2ui 16
4229 18:03:46.841404 best dqsien dly found for B1: ( 0, 13, 18)
4230 18:03:46.844951 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4231 18:03:46.848112 best DQS1 dly(MCK, UI, PI) = (0, 13, 18)
4232 18:03:46.848192
4233 18:03:46.851492 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4234 18:03:46.854869 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 18)
4235 18:03:46.858162 [Gating] SW calibration Done
4236 18:03:46.858242 ==
4237 18:03:46.861890 Dram Type= 6, Freq= 0, CH_0, rank 1
4238 18:03:46.864614 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4239 18:03:46.864695 ==
4240 18:03:46.868304 RX Vref Scan: 0
4241 18:03:46.868385
4242 18:03:46.868448 RX Vref 0 -> 0, step: 1
4243 18:03:46.871325
4244 18:03:46.871404 RX Delay -230 -> 252, step: 16
4245 18:03:46.878066 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4246 18:03:46.881330 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4247 18:03:46.884933 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4248 18:03:46.888291 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4249 18:03:46.891785 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4250 18:03:46.898163 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4251 18:03:46.901700 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4252 18:03:46.904792 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4253 18:03:46.908155 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4254 18:03:46.915122 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4255 18:03:46.918581 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4256 18:03:46.921878 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4257 18:03:46.924915 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4258 18:03:46.928218 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4259 18:03:46.935161 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4260 18:03:46.938171 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4261 18:03:46.938253 ==
4262 18:03:46.941734 Dram Type= 6, Freq= 0, CH_0, rank 1
4263 18:03:46.944792 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4264 18:03:46.944873 ==
4265 18:03:46.948257 DQS Delay:
4266 18:03:46.948337 DQS0 = 0, DQS1 = 0
4267 18:03:46.951733 DQM Delay:
4268 18:03:46.951814 DQM0 = 40, DQM1 = 32
4269 18:03:46.951879 DQ Delay:
4270 18:03:46.955464 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =41
4271 18:03:46.958421 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4272 18:03:46.961665 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4273 18:03:46.965246 DQ12 =33, DQ13 =41, DQ14 =49, DQ15 =41
4274 18:03:46.965327
4275 18:03:46.965391
4276 18:03:46.965449 ==
4277 18:03:46.968394 Dram Type= 6, Freq= 0, CH_0, rank 1
4278 18:03:46.975788 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4279 18:03:46.976106 ==
4280 18:03:46.976359
4281 18:03:46.976735
4282 18:03:46.977131 TX Vref Scan disable
4283 18:03:46.978926 == TX Byte 0 ==
4284 18:03:46.982386 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4285 18:03:46.989184 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4286 18:03:46.989411 == TX Byte 1 ==
4287 18:03:46.991901 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4288 18:03:46.998841 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4289 18:03:46.999028 ==
4290 18:03:47.002474 Dram Type= 6, Freq= 0, CH_0, rank 1
4291 18:03:47.005583 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4292 18:03:47.005856 ==
4293 18:03:47.006020
4294 18:03:47.006167
4295 18:03:47.008676 TX Vref Scan disable
4296 18:03:47.012067 == TX Byte 0 ==
4297 18:03:47.015512 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4298 18:03:47.018832 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4299 18:03:47.021999 == TX Byte 1 ==
4300 18:03:47.025518 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4301 18:03:47.028874 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4302 18:03:47.029177
4303 18:03:47.029335 [DATLAT]
4304 18:03:47.032600 Freq=600, CH0 RK1
4305 18:03:47.032875
4306 18:03:47.033058 DATLAT Default: 0x9
4307 18:03:47.035902 0, 0xFFFF, sum = 0
4308 18:03:47.036181 1, 0xFFFF, sum = 0
4309 18:03:47.038754 2, 0xFFFF, sum = 0
4310 18:03:47.042272 3, 0xFFFF, sum = 0
4311 18:03:47.042586 4, 0xFFFF, sum = 0
4312 18:03:47.045746 5, 0xFFFF, sum = 0
4313 18:03:47.046113 6, 0xFFFF, sum = 0
4314 18:03:47.048946 7, 0xFFFF, sum = 0
4315 18:03:47.049334 8, 0x0, sum = 1
4316 18:03:47.049618 9, 0x0, sum = 2
4317 18:03:47.052226 10, 0x0, sum = 3
4318 18:03:47.052577 11, 0x0, sum = 4
4319 18:03:47.055975 best_step = 9
4320 18:03:47.056518
4321 18:03:47.056869 ==
4322 18:03:47.059212 Dram Type= 6, Freq= 0, CH_0, rank 1
4323 18:03:47.062329 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4324 18:03:47.062744 ==
4325 18:03:47.065681 RX Vref Scan: 0
4326 18:03:47.066087
4327 18:03:47.066410 RX Vref 0 -> 0, step: 1
4328 18:03:47.066714
4329 18:03:47.069094 RX Delay -195 -> 252, step: 8
4330 18:03:47.076454 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4331 18:03:47.079968 iDelay=205, Bit 1, Center 40 (-115 ~ 196) 312
4332 18:03:47.083534 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4333 18:03:47.086481 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4334 18:03:47.093336 iDelay=205, Bit 4, Center 36 (-115 ~ 188) 304
4335 18:03:47.096388 iDelay=205, Bit 5, Center 28 (-123 ~ 180) 304
4336 18:03:47.099388 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4337 18:03:47.102812 iDelay=205, Bit 7, Center 44 (-107 ~ 196) 304
4338 18:03:47.106374 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4339 18:03:47.112967 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4340 18:03:47.116464 iDelay=205, Bit 10, Center 36 (-115 ~ 188) 304
4341 18:03:47.120446 iDelay=205, Bit 11, Center 24 (-123 ~ 172) 296
4342 18:03:47.123168 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4343 18:03:47.130289 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4344 18:03:47.133423 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4345 18:03:47.136842 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4346 18:03:47.137401 ==
4347 18:03:47.139927 Dram Type= 6, Freq= 0, CH_0, rank 1
4348 18:03:47.143691 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4349 18:03:47.144204 ==
4350 18:03:47.146718 DQS Delay:
4351 18:03:47.147144 DQS0 = 0, DQS1 = 0
4352 18:03:47.150314 DQM Delay:
4353 18:03:47.150829 DQM0 = 39, DQM1 = 33
4354 18:03:47.151172 DQ Delay:
4355 18:03:47.153365 DQ0 =40, DQ1 =40, DQ2 =36, DQ3 =40
4356 18:03:47.156429 DQ4 =36, DQ5 =28, DQ6 =48, DQ7 =44
4357 18:03:47.159843 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =24
4358 18:03:47.163502 DQ12 =36, DQ13 =40, DQ14 =44, DQ15 =40
4359 18:03:47.163920
4360 18:03:47.164245
4361 18:03:47.173478 [DQSOSCAuto] RK1, (LSB)MR18= 0x4527, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 396 ps
4362 18:03:47.176781 CH0 RK1: MR19=808, MR18=4527
4363 18:03:47.179699 CH0_RK1: MR19=0x808, MR18=0x4527, DQSOSC=396, MR23=63, INC=167, DEC=111
4364 18:03:47.183396 [RxdqsGatingPostProcess] freq 600
4365 18:03:47.189689 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4366 18:03:47.193081 Pre-setting of DQS Precalculation
4367 18:03:47.196479 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4368 18:03:47.196776 ==
4369 18:03:47.199889 Dram Type= 6, Freq= 0, CH_1, rank 0
4370 18:03:47.206320 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4371 18:03:47.206547 ==
4372 18:03:47.209533 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4373 18:03:47.215927 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4374 18:03:47.219792 [CA 0] Center 35 (5~65) winsize 61
4375 18:03:47.222949 [CA 1] Center 35 (5~66) winsize 62
4376 18:03:47.226520 [CA 2] Center 34 (4~65) winsize 62
4377 18:03:47.230044 [CA 3] Center 33 (3~64) winsize 62
4378 18:03:47.233440 [CA 4] Center 34 (3~65) winsize 63
4379 18:03:47.236854 [CA 5] Center 33 (3~64) winsize 62
4380 18:03:47.237023
4381 18:03:47.240114 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4382 18:03:47.240275
4383 18:03:47.243110 [CATrainingPosCal] consider 1 rank data
4384 18:03:47.246482 u2DelayCellTimex100 = 270/100 ps
4385 18:03:47.249832 CA0 delay=35 (5~65),Diff = 2 PI (19 cell)
4386 18:03:47.253391 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4387 18:03:47.256384 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4388 18:03:47.263288 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4389 18:03:47.266453 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4390 18:03:47.269738 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4391 18:03:47.269869
4392 18:03:47.273467 CA PerBit enable=1, Macro0, CA PI delay=33
4393 18:03:47.273641
4394 18:03:47.276445 [CBTSetCACLKResult] CA Dly = 33
4395 18:03:47.276607 CS Dly: 5 (0~36)
4396 18:03:47.276699 ==
4397 18:03:47.279726 Dram Type= 6, Freq= 0, CH_1, rank 1
4398 18:03:47.286540 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4399 18:03:47.286744 ==
4400 18:03:47.289584 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4401 18:03:47.296543 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4402 18:03:47.300117 [CA 0] Center 35 (5~66) winsize 62
4403 18:03:47.302932 [CA 1] Center 36 (6~66) winsize 61
4404 18:03:47.306326 [CA 2] Center 34 (4~65) winsize 62
4405 18:03:47.309929 [CA 3] Center 34 (3~65) winsize 63
4406 18:03:47.313056 [CA 4] Center 34 (4~65) winsize 62
4407 18:03:47.316477 [CA 5] Center 33 (3~64) winsize 62
4408 18:03:47.316850
4409 18:03:47.320240 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4410 18:03:47.320597
4411 18:03:47.323443 [CATrainingPosCal] consider 2 rank data
4412 18:03:47.326848 u2DelayCellTimex100 = 270/100 ps
4413 18:03:47.330362 CA0 delay=35 (5~65),Diff = 2 PI (19 cell)
4414 18:03:47.333810 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4415 18:03:47.340413 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4416 18:03:47.343915 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4417 18:03:47.347216 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4418 18:03:47.350202 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4419 18:03:47.350617
4420 18:03:47.353591 CA PerBit enable=1, Macro0, CA PI delay=33
4421 18:03:47.354008
4422 18:03:47.356913 [CBTSetCACLKResult] CA Dly = 33
4423 18:03:47.357369 CS Dly: 5 (0~37)
4424 18:03:47.357699
4425 18:03:47.359872 ----->DramcWriteLeveling(PI) begin...
4426 18:03:47.363091 ==
4427 18:03:47.363503 Dram Type= 6, Freq= 0, CH_1, rank 0
4428 18:03:47.369934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4429 18:03:47.370041 ==
4430 18:03:47.373216 Write leveling (Byte 0): 29 => 29
4431 18:03:47.376184 Write leveling (Byte 1): 29 => 29
4432 18:03:47.376299 DramcWriteLeveling(PI) end<-----
4433 18:03:47.379618
4434 18:03:47.379760 ==
4435 18:03:47.383148 Dram Type= 6, Freq= 0, CH_1, rank 0
4436 18:03:47.386149 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4437 18:03:47.386258 ==
4438 18:03:47.389815 [Gating] SW mode calibration
4439 18:03:47.396471 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4440 18:03:47.399788 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4441 18:03:47.406719 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4442 18:03:47.409929 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4443 18:03:47.413049 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4444 18:03:47.420318 0 9 12 | B1->B0 | 3535 3434 | 1 1 | (0 0) (1 1)
4445 18:03:47.423434 0 9 16 | B1->B0 | 2828 2828 | 1 1 | (0 0) (0 0)
4446 18:03:47.427071 0 9 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4447 18:03:47.433628 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4448 18:03:47.437113 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4449 18:03:47.439840 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4450 18:03:47.446945 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4451 18:03:47.450058 0 10 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4452 18:03:47.453608 0 10 12 | B1->B0 | 2828 2d2d | 0 1 | (0 0) (0 0)
4453 18:03:47.457014 0 10 16 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
4454 18:03:47.463502 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4455 18:03:47.466934 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4456 18:03:47.470821 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4457 18:03:47.476888 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4458 18:03:47.480099 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4459 18:03:47.483475 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4460 18:03:47.490363 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4461 18:03:47.493127 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4462 18:03:47.496810 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4463 18:03:47.503348 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4464 18:03:47.506898 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4465 18:03:47.510246 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4466 18:03:47.517170 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4467 18:03:47.520650 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4468 18:03:47.523323 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4469 18:03:47.530019 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4470 18:03:47.533329 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4471 18:03:47.536825 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4472 18:03:47.543285 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4473 18:03:47.546583 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4474 18:03:47.549969 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4475 18:03:47.557060 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4476 18:03:47.560138 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4477 18:03:47.563220 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4478 18:03:47.569547 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4479 18:03:47.569964 Total UI for P1: 0, mck2ui 16
4480 18:03:47.573321 best dqsien dly found for B0: ( 0, 13, 14)
4481 18:03:47.576726 Total UI for P1: 0, mck2ui 16
4482 18:03:47.580039 best dqsien dly found for B1: ( 0, 13, 14)
4483 18:03:47.583762 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4484 18:03:47.590181 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4485 18:03:47.590689
4486 18:03:47.593372 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4487 18:03:47.596620 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4488 18:03:47.600092 [Gating] SW calibration Done
4489 18:03:47.600596 ==
4490 18:03:47.603134 Dram Type= 6, Freq= 0, CH_1, rank 0
4491 18:03:47.606946 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4492 18:03:47.607556 ==
4493 18:03:47.608026 RX Vref Scan: 0
4494 18:03:47.610169
4495 18:03:47.610576 RX Vref 0 -> 0, step: 1
4496 18:03:47.610902
4497 18:03:47.613599 RX Delay -230 -> 252, step: 16
4498 18:03:47.616494 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4499 18:03:47.623338 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4500 18:03:47.626945 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4501 18:03:47.630239 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4502 18:03:47.633125 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4503 18:03:47.636669 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4504 18:03:47.644033 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4505 18:03:47.647019 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4506 18:03:47.650036 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4507 18:03:47.653691 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4508 18:03:47.656807 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4509 18:03:47.663905 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4510 18:03:47.666910 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4511 18:03:47.670269 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4512 18:03:47.673316 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4513 18:03:47.680448 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4514 18:03:47.681121 ==
4515 18:03:47.683276 Dram Type= 6, Freq= 0, CH_1, rank 0
4516 18:03:47.686690 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4517 18:03:47.687111 ==
4518 18:03:47.687486 DQS Delay:
4519 18:03:47.689720 DQS0 = 0, DQS1 = 0
4520 18:03:47.690175 DQM Delay:
4521 18:03:47.693099 DQM0 = 43, DQM1 = 34
4522 18:03:47.693468 DQ Delay:
4523 18:03:47.696713 DQ0 =41, DQ1 =41, DQ2 =25, DQ3 =41
4524 18:03:47.699939 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4525 18:03:47.703106 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =33
4526 18:03:47.706491 DQ12 =49, DQ13 =41, DQ14 =41, DQ15 =41
4527 18:03:47.706907
4528 18:03:47.707236
4529 18:03:47.707540 ==
4530 18:03:47.709878 Dram Type= 6, Freq= 0, CH_1, rank 0
4531 18:03:47.713167 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4532 18:03:47.716491 ==
4533 18:03:47.716919
4534 18:03:47.717504
4535 18:03:47.717857 TX Vref Scan disable
4536 18:03:47.719587 == TX Byte 0 ==
4537 18:03:47.723380 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4538 18:03:47.726761 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4539 18:03:47.729840 == TX Byte 1 ==
4540 18:03:47.733174 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4541 18:03:47.736110 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4542 18:03:47.739299 ==
4543 18:03:47.743056 Dram Type= 6, Freq= 0, CH_1, rank 0
4544 18:03:47.746028 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4545 18:03:47.746445 ==
4546 18:03:47.746774
4547 18:03:47.747078
4548 18:03:47.749414 TX Vref Scan disable
4549 18:03:47.750009 == TX Byte 0 ==
4550 18:03:47.755965 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4551 18:03:47.759718 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4552 18:03:47.760133 == TX Byte 1 ==
4553 18:03:47.766335 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4554 18:03:47.769355 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4555 18:03:47.769774
4556 18:03:47.770131 [DATLAT]
4557 18:03:47.773091 Freq=600, CH1 RK0
4558 18:03:47.773533
4559 18:03:47.773862 DATLAT Default: 0x9
4560 18:03:47.776277 0, 0xFFFF, sum = 0
4561 18:03:47.776701 1, 0xFFFF, sum = 0
4562 18:03:47.779426 2, 0xFFFF, sum = 0
4563 18:03:47.779847 3, 0xFFFF, sum = 0
4564 18:03:47.782596 4, 0xFFFF, sum = 0
4565 18:03:47.786459 5, 0xFFFF, sum = 0
4566 18:03:47.786879 6, 0xFFFF, sum = 0
4567 18:03:47.790149 7, 0xFFFF, sum = 0
4568 18:03:47.790962 8, 0x0, sum = 1
4569 18:03:47.791545 9, 0x0, sum = 2
4570 18:03:47.793031 10, 0x0, sum = 3
4571 18:03:47.793457 11, 0x0, sum = 4
4572 18:03:47.796307 best_step = 9
4573 18:03:47.797002
4574 18:03:47.797575 ==
4575 18:03:47.799750 Dram Type= 6, Freq= 0, CH_1, rank 0
4576 18:03:47.802502 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4577 18:03:47.803110 ==
4578 18:03:47.805992 RX Vref Scan: 1
4579 18:03:47.806400
4580 18:03:47.806754 RX Vref 0 -> 0, step: 1
4581 18:03:47.807058
4582 18:03:47.809433 RX Delay -195 -> 252, step: 8
4583 18:03:47.809842
4584 18:03:47.812904 Set Vref, RX VrefLevel [Byte0]: 56
4585 18:03:47.816376 [Byte1]: 53
4586 18:03:47.819867
4587 18:03:47.820274 Final RX Vref Byte 0 = 56 to rank0
4588 18:03:47.823721 Final RX Vref Byte 1 = 53 to rank0
4589 18:03:47.827609 Final RX Vref Byte 0 = 56 to rank1
4590 18:03:47.830319 Final RX Vref Byte 1 = 53 to rank1==
4591 18:03:47.833390 Dram Type= 6, Freq= 0, CH_1, rank 0
4592 18:03:47.839993 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4593 18:03:47.840440 ==
4594 18:03:47.840879 DQS Delay:
4595 18:03:47.841348 DQS0 = 0, DQS1 = 0
4596 18:03:47.843673 DQM Delay:
4597 18:03:47.844103 DQM0 = 41, DQM1 = 33
4598 18:03:47.846637 DQ Delay:
4599 18:03:47.850380 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =40
4600 18:03:47.850795 DQ4 =44, DQ5 =48, DQ6 =52, DQ7 =36
4601 18:03:47.853592 DQ8 =20, DQ9 =24, DQ10 =36, DQ11 =24
4602 18:03:47.859733 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4603 18:03:47.860029
4604 18:03:47.860262
4605 18:03:47.866844 [DQSOSCAuto] RK0, (LSB)MR18= 0x4107, (MSB)MR19= 0x808, tDQSOscB0 = 408 ps tDQSOscB1 = 397 ps
4606 18:03:47.869603 CH1 RK0: MR19=808, MR18=4107
4607 18:03:47.876737 CH1_RK0: MR19=0x808, MR18=0x4107, DQSOSC=397, MR23=63, INC=166, DEC=110
4608 18:03:47.877160
4609 18:03:47.879663 ----->DramcWriteLeveling(PI) begin...
4610 18:03:47.879962 ==
4611 18:03:47.883404 Dram Type= 6, Freq= 0, CH_1, rank 1
4612 18:03:47.886949 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4613 18:03:47.887446 ==
4614 18:03:47.890165 Write leveling (Byte 0): 31 => 31
4615 18:03:47.893628 Write leveling (Byte 1): 31 => 31
4616 18:03:47.897112 DramcWriteLeveling(PI) end<-----
4617 18:03:47.897522
4618 18:03:47.897847 ==
4619 18:03:47.900087 Dram Type= 6, Freq= 0, CH_1, rank 1
4620 18:03:47.903439 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4621 18:03:47.903854 ==
4622 18:03:47.906858 [Gating] SW mode calibration
4623 18:03:47.913223 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4624 18:03:47.920584 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4625 18:03:47.923612 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4626 18:03:47.926874 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4627 18:03:47.933804 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4628 18:03:47.937172 0 9 12 | B1->B0 | 3131 2f2f | 0 0 | (1 0) (1 1)
4629 18:03:47.941047 0 9 16 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
4630 18:03:47.947186 0 9 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4631 18:03:47.950348 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4632 18:03:47.953969 0 9 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4633 18:03:47.960335 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4634 18:03:47.963829 0 10 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4635 18:03:47.967405 0 10 8 | B1->B0 | 2323 2a2a | 0 1 | (0 0) (0 0)
4636 18:03:47.970445 0 10 12 | B1->B0 | 2f2f 3939 | 0 0 | (1 1) (0 0)
4637 18:03:47.977064 0 10 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4638 18:03:47.980618 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4639 18:03:47.984159 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4640 18:03:47.990483 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4641 18:03:47.993560 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4642 18:03:47.997378 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4643 18:03:48.004038 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4644 18:03:48.007652 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4645 18:03:48.010882 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4646 18:03:48.017715 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4647 18:03:48.020682 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4648 18:03:48.024250 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4649 18:03:48.027928 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4650 18:03:48.033939 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4651 18:03:48.037682 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4652 18:03:48.041054 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4653 18:03:48.047899 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4654 18:03:48.051260 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4655 18:03:48.054428 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4656 18:03:48.060879 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4657 18:03:48.064160 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4658 18:03:48.067156 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4659 18:03:48.074031 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4660 18:03:48.077945 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4661 18:03:48.080956 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4662 18:03:48.084307 Total UI for P1: 0, mck2ui 16
4663 18:03:48.087159 best dqsien dly found for B0: ( 0, 13, 12)
4664 18:03:48.093982 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4665 18:03:48.094522 Total UI for P1: 0, mck2ui 16
4666 18:03:48.100580 best dqsien dly found for B1: ( 0, 13, 16)
4667 18:03:48.103988 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4668 18:03:48.107142 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4669 18:03:48.107576
4670 18:03:48.110648 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4671 18:03:48.113881 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4672 18:03:48.117297 [Gating] SW calibration Done
4673 18:03:48.117737 ==
4674 18:03:48.120540 Dram Type= 6, Freq= 0, CH_1, rank 1
4675 18:03:48.124116 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4676 18:03:48.124658 ==
4677 18:03:48.127538 RX Vref Scan: 0
4678 18:03:48.128080
4679 18:03:48.128524 RX Vref 0 -> 0, step: 1
4680 18:03:48.128938
4681 18:03:48.130534 RX Delay -230 -> 252, step: 16
4682 18:03:48.137822 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4683 18:03:48.140969 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4684 18:03:48.144453 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4685 18:03:48.147742 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4686 18:03:48.150845 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4687 18:03:48.157518 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4688 18:03:48.161121 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4689 18:03:48.164351 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4690 18:03:48.168574 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4691 18:03:48.171145 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4692 18:03:48.177683 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4693 18:03:48.181143 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4694 18:03:48.183761 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4695 18:03:48.187172 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4696 18:03:48.194073 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4697 18:03:48.197548 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4698 18:03:48.197962 ==
4699 18:03:48.201141 Dram Type= 6, Freq= 0, CH_1, rank 1
4700 18:03:48.204104 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4701 18:03:48.204620 ==
4702 18:03:48.207573 DQS Delay:
4703 18:03:48.208083 DQS0 = 0, DQS1 = 0
4704 18:03:48.208411 DQM Delay:
4705 18:03:48.211343 DQM0 = 40, DQM1 = 37
4706 18:03:48.211849 DQ Delay:
4707 18:03:48.214002 DQ0 =41, DQ1 =33, DQ2 =25, DQ3 =41
4708 18:03:48.217596 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4709 18:03:48.220818 DQ8 =17, DQ9 =25, DQ10 =41, DQ11 =33
4710 18:03:48.224258 DQ12 =41, DQ13 =49, DQ14 =49, DQ15 =41
4711 18:03:48.224782
4712 18:03:48.225147
4713 18:03:48.225453 ==
4714 18:03:48.228088 Dram Type= 6, Freq= 0, CH_1, rank 1
4715 18:03:48.234461 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4716 18:03:48.234990 ==
4717 18:03:48.235316
4718 18:03:48.235618
4719 18:03:48.235905 TX Vref Scan disable
4720 18:03:48.237548 == TX Byte 0 ==
4721 18:03:48.241067 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4722 18:03:48.247695 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4723 18:03:48.248207 == TX Byte 1 ==
4724 18:03:48.251003 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4725 18:03:48.254182 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4726 18:03:48.257689 ==
4727 18:03:48.261225 Dram Type= 6, Freq= 0, CH_1, rank 1
4728 18:03:48.264693 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4729 18:03:48.265243 ==
4730 18:03:48.265576
4731 18:03:48.265878
4732 18:03:48.267310 TX Vref Scan disable
4733 18:03:48.267713 == TX Byte 0 ==
4734 18:03:48.274521 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4735 18:03:48.277754 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4736 18:03:48.278195 == TX Byte 1 ==
4737 18:03:48.284828 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4738 18:03:48.288392 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4739 18:03:48.288904
4740 18:03:48.289293 [DATLAT]
4741 18:03:48.291158 Freq=600, CH1 RK1
4742 18:03:48.291581
4743 18:03:48.291906 DATLAT Default: 0x9
4744 18:03:48.294218 0, 0xFFFF, sum = 0
4745 18:03:48.294732 1, 0xFFFF, sum = 0
4746 18:03:48.297829 2, 0xFFFF, sum = 0
4747 18:03:48.298249 3, 0xFFFF, sum = 0
4748 18:03:48.300822 4, 0xFFFF, sum = 0
4749 18:03:48.301290 5, 0xFFFF, sum = 0
4750 18:03:48.304282 6, 0xFFFF, sum = 0
4751 18:03:48.304699 7, 0xFFFF, sum = 0
4752 18:03:48.308111 8, 0x0, sum = 1
4753 18:03:48.308626 9, 0x0, sum = 2
4754 18:03:48.311578 10, 0x0, sum = 3
4755 18:03:48.312099 11, 0x0, sum = 4
4756 18:03:48.314272 best_step = 9
4757 18:03:48.314680
4758 18:03:48.315006 ==
4759 18:03:48.317536 Dram Type= 6, Freq= 0, CH_1, rank 1
4760 18:03:48.321054 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4761 18:03:48.321561 ==
4762 18:03:48.325054 RX Vref Scan: 0
4763 18:03:48.325561
4764 18:03:48.325891 RX Vref 0 -> 0, step: 1
4765 18:03:48.326195
4766 18:03:48.327595 RX Delay -195 -> 252, step: 8
4767 18:03:48.334630 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4768 18:03:48.338147 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4769 18:03:48.341347 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4770 18:03:48.344554 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4771 18:03:48.351448 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312
4772 18:03:48.354614 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4773 18:03:48.357883 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4774 18:03:48.361139 iDelay=205, Bit 7, Center 36 (-115 ~ 188) 304
4775 18:03:48.364778 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4776 18:03:48.371069 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4777 18:03:48.374671 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4778 18:03:48.378061 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4779 18:03:48.381523 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4780 18:03:48.387592 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4781 18:03:48.391303 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4782 18:03:48.394706 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4783 18:03:48.395277 ==
4784 18:03:48.397853 Dram Type= 6, Freq= 0, CH_1, rank 1
4785 18:03:48.400687 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4786 18:03:48.404601 ==
4787 18:03:48.405297 DQS Delay:
4788 18:03:48.405693 DQS0 = 0, DQS1 = 0
4789 18:03:48.407953 DQM Delay:
4790 18:03:48.408464 DQM0 = 38, DQM1 = 33
4791 18:03:48.411143 DQ Delay:
4792 18:03:48.411556 DQ0 =40, DQ1 =32, DQ2 =24, DQ3 =36
4793 18:03:48.414215 DQ4 =40, DQ5 =48, DQ6 =48, DQ7 =36
4794 18:03:48.417574 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =24
4795 18:03:48.420918 DQ12 =40, DQ13 =40, DQ14 =44, DQ15 =40
4796 18:03:48.421352
4797 18:03:48.424544
4798 18:03:48.431297 [DQSOSCAuto] RK1, (LSB)MR18= 0x3544, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 399 ps
4799 18:03:48.434889 CH1 RK1: MR19=808, MR18=3544
4800 18:03:48.441185 CH1_RK1: MR19=0x808, MR18=0x3544, DQSOSC=396, MR23=63, INC=167, DEC=111
4801 18:03:48.444569 [RxdqsGatingPostProcess] freq 600
4802 18:03:48.447688 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4803 18:03:48.450919 Pre-setting of DQS Precalculation
4804 18:03:48.457244 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4805 18:03:48.464582 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4806 18:03:48.471331 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4807 18:03:48.471858
4808 18:03:48.472188
4809 18:03:48.474048 [Calibration Summary] 1200 Mbps
4810 18:03:48.474459 CH 0, Rank 0
4811 18:03:48.477611 SW Impedance : PASS
4812 18:03:48.478220 DUTY Scan : NO K
4813 18:03:48.481036 ZQ Calibration : PASS
4814 18:03:48.484020 Jitter Meter : NO K
4815 18:03:48.484431 CBT Training : PASS
4816 18:03:48.487563 Write leveling : PASS
4817 18:03:48.490927 RX DQS gating : PASS
4818 18:03:48.491340 RX DQ/DQS(RDDQC) : PASS
4819 18:03:48.494787 TX DQ/DQS : PASS
4820 18:03:48.497494 RX DATLAT : PASS
4821 18:03:48.497909 RX DQ/DQS(Engine): PASS
4822 18:03:48.501055 TX OE : NO K
4823 18:03:48.501569 All Pass.
4824 18:03:48.501903
4825 18:03:48.504088 CH 0, Rank 1
4826 18:03:48.504601 SW Impedance : PASS
4827 18:03:48.507383 DUTY Scan : NO K
4828 18:03:48.511477 ZQ Calibration : PASS
4829 18:03:48.511995 Jitter Meter : NO K
4830 18:03:48.514267 CBT Training : PASS
4831 18:03:48.517473 Write leveling : PASS
4832 18:03:48.517910 RX DQS gating : PASS
4833 18:03:48.521162 RX DQ/DQS(RDDQC) : PASS
4834 18:03:48.521670 TX DQ/DQS : PASS
4835 18:03:48.524351 RX DATLAT : PASS
4836 18:03:48.527500 RX DQ/DQS(Engine): PASS
4837 18:03:48.527909 TX OE : NO K
4838 18:03:48.530867 All Pass.
4839 18:03:48.531280
4840 18:03:48.531610 CH 1, Rank 0
4841 18:03:48.534313 SW Impedance : PASS
4842 18:03:48.534829 DUTY Scan : NO K
4843 18:03:48.537629 ZQ Calibration : PASS
4844 18:03:48.541425 Jitter Meter : NO K
4845 18:03:48.541931 CBT Training : PASS
4846 18:03:48.544095 Write leveling : PASS
4847 18:03:48.547816 RX DQS gating : PASS
4848 18:03:48.548323 RX DQ/DQS(RDDQC) : PASS
4849 18:03:48.551275 TX DQ/DQS : PASS
4850 18:03:48.554494 RX DATLAT : PASS
4851 18:03:48.555022 RX DQ/DQS(Engine): PASS
4852 18:03:48.557347 TX OE : NO K
4853 18:03:48.557762 All Pass.
4854 18:03:48.558092
4855 18:03:48.560866 CH 1, Rank 1
4856 18:03:48.561415 SW Impedance : PASS
4857 18:03:48.564043 DUTY Scan : NO K
4858 18:03:48.564454 ZQ Calibration : PASS
4859 18:03:48.567372 Jitter Meter : NO K
4860 18:03:48.570669 CBT Training : PASS
4861 18:03:48.571082 Write leveling : PASS
4862 18:03:48.574004 RX DQS gating : PASS
4863 18:03:48.577705 RX DQ/DQS(RDDQC) : PASS
4864 18:03:48.578220 TX DQ/DQS : PASS
4865 18:03:48.581195 RX DATLAT : PASS
4866 18:03:48.584453 RX DQ/DQS(Engine): PASS
4867 18:03:48.584960 TX OE : NO K
4868 18:03:48.587402 All Pass.
4869 18:03:48.587814
4870 18:03:48.588203 DramC Write-DBI off
4871 18:03:48.591240 PER_BANK_REFRESH: Hybrid Mode
4872 18:03:48.591735 TX_TRACKING: ON
4873 18:03:48.601866 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4874 18:03:48.604443 [FAST_K] Save calibration result to emmc
4875 18:03:48.607362 dramc_set_vcore_voltage set vcore to 662500
4876 18:03:48.611052 Read voltage for 933, 3
4877 18:03:48.611465 Vio18 = 0
4878 18:03:48.614263 Vcore = 662500
4879 18:03:48.614674 Vdram = 0
4880 18:03:48.614999 Vddq = 0
4881 18:03:48.615303 Vmddr = 0
4882 18:03:48.621042 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4883 18:03:48.627589 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4884 18:03:48.628132 MEM_TYPE=3, freq_sel=17
4885 18:03:48.630589 sv_algorithm_assistance_LP4_1600
4886 18:03:48.634325 ============ PULL DRAM RESETB DOWN ============
4887 18:03:48.640696 ========== PULL DRAM RESETB DOWN end =========
4888 18:03:48.644518 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4889 18:03:48.648154 ===================================
4890 18:03:48.651271 LPDDR4 DRAM CONFIGURATION
4891 18:03:48.654187 ===================================
4892 18:03:48.654598 EX_ROW_EN[0] = 0x0
4893 18:03:48.657792 EX_ROW_EN[1] = 0x0
4894 18:03:48.658299 LP4Y_EN = 0x0
4895 18:03:48.661439 WORK_FSP = 0x0
4896 18:03:48.661960 WL = 0x3
4897 18:03:48.664328 RL = 0x3
4898 18:03:48.664741 BL = 0x2
4899 18:03:48.667754 RPST = 0x0
4900 18:03:48.668400 RD_PRE = 0x0
4901 18:03:48.671412 WR_PRE = 0x1
4902 18:03:48.674715 WR_PST = 0x0
4903 18:03:48.675220 DBI_WR = 0x0
4904 18:03:48.677720 DBI_RD = 0x0
4905 18:03:48.678250 OTF = 0x1
4906 18:03:48.681366 ===================================
4907 18:03:48.684537 ===================================
4908 18:03:48.685112 ANA top config
4909 18:03:48.687679 ===================================
4910 18:03:48.691087 DLL_ASYNC_EN = 0
4911 18:03:48.694451 ALL_SLAVE_EN = 1
4912 18:03:48.697597 NEW_RANK_MODE = 1
4913 18:03:48.701192 DLL_IDLE_MODE = 1
4914 18:03:48.701707 LP45_APHY_COMB_EN = 1
4915 18:03:48.704476 TX_ODT_DIS = 1
4916 18:03:48.707496 NEW_8X_MODE = 1
4917 18:03:48.711069 ===================================
4918 18:03:48.714546 ===================================
4919 18:03:48.717250 data_rate = 1866
4920 18:03:48.720838 CKR = 1
4921 18:03:48.721296 DQ_P2S_RATIO = 8
4922 18:03:48.724659 ===================================
4923 18:03:48.727979 CA_P2S_RATIO = 8
4924 18:03:48.731328 DQ_CA_OPEN = 0
4925 18:03:48.734858 DQ_SEMI_OPEN = 0
4926 18:03:48.738106 CA_SEMI_OPEN = 0
4927 18:03:48.738563 CA_FULL_RATE = 0
4928 18:03:48.741427 DQ_CKDIV4_EN = 1
4929 18:03:48.744861 CA_CKDIV4_EN = 1
4930 18:03:48.747658 CA_PREDIV_EN = 0
4931 18:03:48.751095 PH8_DLY = 0
4932 18:03:48.754322 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4933 18:03:48.754734 DQ_AAMCK_DIV = 4
4934 18:03:48.758257 CA_AAMCK_DIV = 4
4935 18:03:48.761654 CA_ADMCK_DIV = 4
4936 18:03:48.764831 DQ_TRACK_CA_EN = 0
4937 18:03:48.767899 CA_PICK = 933
4938 18:03:48.771706 CA_MCKIO = 933
4939 18:03:48.772257 MCKIO_SEMI = 0
4940 18:03:48.774976 PLL_FREQ = 3732
4941 18:03:48.777918 DQ_UI_PI_RATIO = 32
4942 18:03:48.781351 CA_UI_PI_RATIO = 0
4943 18:03:48.784893 ===================================
4944 18:03:48.788047 ===================================
4945 18:03:48.791094 memory_type:LPDDR4
4946 18:03:48.791508 GP_NUM : 10
4947 18:03:48.794523 SRAM_EN : 1
4948 18:03:48.798185 MD32_EN : 0
4949 18:03:48.800812 ===================================
4950 18:03:48.801275 [ANA_INIT] >>>>>>>>>>>>>>
4951 18:03:48.804391 <<<<<< [CONFIGURE PHASE]: ANA_TX
4952 18:03:48.808254 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4953 18:03:48.811316 ===================================
4954 18:03:48.814365 data_rate = 1866,PCW = 0X8f00
4955 18:03:48.817609 ===================================
4956 18:03:48.821048 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4957 18:03:48.827997 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4958 18:03:48.830938 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4959 18:03:48.837780 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4960 18:03:48.841106 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4961 18:03:48.844514 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4962 18:03:48.844931 [ANA_INIT] flow start
4963 18:03:48.848000 [ANA_INIT] PLL >>>>>>>>
4964 18:03:48.850846 [ANA_INIT] PLL <<<<<<<<
4965 18:03:48.851259 [ANA_INIT] MIDPI >>>>>>>>
4966 18:03:48.854282 [ANA_INIT] MIDPI <<<<<<<<
4967 18:03:48.857959 [ANA_INIT] DLL >>>>>>>>
4968 18:03:48.858433 [ANA_INIT] flow end
4969 18:03:48.864718 ============ LP4 DIFF to SE enter ============
4970 18:03:48.867655 ============ LP4 DIFF to SE exit ============
4971 18:03:48.871142 [ANA_INIT] <<<<<<<<<<<<<
4972 18:03:48.874458 [Flow] Enable top DCM control >>>>>
4973 18:03:48.877933 [Flow] Enable top DCM control <<<<<
4974 18:03:48.878345 Enable DLL master slave shuffle
4975 18:03:48.884357 ==============================================================
4976 18:03:48.888279 Gating Mode config
4977 18:03:48.891143 ==============================================================
4978 18:03:48.894667 Config description:
4979 18:03:48.904894 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4980 18:03:48.911218 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4981 18:03:48.914471 SELPH_MODE 0: By rank 1: By Phase
4982 18:03:48.921096 ==============================================================
4983 18:03:48.924601 GAT_TRACK_EN = 1
4984 18:03:48.927937 RX_GATING_MODE = 2
4985 18:03:48.931159 RX_GATING_TRACK_MODE = 2
4986 18:03:48.931753 SELPH_MODE = 1
4987 18:03:48.934554 PICG_EARLY_EN = 1
4988 18:03:48.937941 VALID_LAT_VALUE = 1
4989 18:03:48.944350 ==============================================================
4990 18:03:48.948232 Enter into Gating configuration >>>>
4991 18:03:48.951511 Exit from Gating configuration <<<<
4992 18:03:48.955093 Enter into DVFS_PRE_config >>>>>
4993 18:03:48.964900 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4994 18:03:48.967781 Exit from DVFS_PRE_config <<<<<
4995 18:03:48.971035 Enter into PICG configuration >>>>
4996 18:03:48.974689 Exit from PICG configuration <<<<
4997 18:03:48.977558 [RX_INPUT] configuration >>>>>
4998 18:03:48.980898 [RX_INPUT] configuration <<<<<
4999 18:03:48.984272 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5000 18:03:48.991272 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5001 18:03:48.997516 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5002 18:03:49.004674 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5003 18:03:49.007759 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5004 18:03:49.014625 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5005 18:03:49.017612 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5006 18:03:49.024399 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5007 18:03:49.028128 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5008 18:03:49.031437 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5009 18:03:49.034613 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5010 18:03:49.041128 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5011 18:03:49.044562 ===================================
5012 18:03:49.045049 LPDDR4 DRAM CONFIGURATION
5013 18:03:49.047754 ===================================
5014 18:03:49.051191 EX_ROW_EN[0] = 0x0
5015 18:03:49.054440 EX_ROW_EN[1] = 0x0
5016 18:03:49.054852 LP4Y_EN = 0x0
5017 18:03:49.057885 WORK_FSP = 0x0
5018 18:03:49.058297 WL = 0x3
5019 18:03:49.061535 RL = 0x3
5020 18:03:49.061947 BL = 0x2
5021 18:03:49.064732 RPST = 0x0
5022 18:03:49.065314 RD_PRE = 0x0
5023 18:03:49.068087 WR_PRE = 0x1
5024 18:03:49.068497 WR_PST = 0x0
5025 18:03:49.071008 DBI_WR = 0x0
5026 18:03:49.071419 DBI_RD = 0x0
5027 18:03:49.074646 OTF = 0x1
5028 18:03:49.078125 ===================================
5029 18:03:49.081518 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5030 18:03:49.084457 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5031 18:03:49.091250 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5032 18:03:49.094637 ===================================
5033 18:03:49.095165 LPDDR4 DRAM CONFIGURATION
5034 18:03:49.097913 ===================================
5035 18:03:49.101210 EX_ROW_EN[0] = 0x10
5036 18:03:49.101678 EX_ROW_EN[1] = 0x0
5037 18:03:49.104760 LP4Y_EN = 0x0
5038 18:03:49.105215 WORK_FSP = 0x0
5039 18:03:49.107756 WL = 0x3
5040 18:03:49.108292 RL = 0x3
5041 18:03:49.111040 BL = 0x2
5042 18:03:49.114324 RPST = 0x0
5043 18:03:49.114800 RD_PRE = 0x0
5044 18:03:49.117976 WR_PRE = 0x1
5045 18:03:49.118315 WR_PST = 0x0
5046 18:03:49.121362 DBI_WR = 0x0
5047 18:03:49.121654 DBI_RD = 0x0
5048 18:03:49.124134 OTF = 0x1
5049 18:03:49.127749 ===================================
5050 18:03:49.131332 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5051 18:03:49.136542 nWR fixed to 30
5052 18:03:49.140194 [ModeRegInit_LP4] CH0 RK0
5053 18:03:49.140508 [ModeRegInit_LP4] CH0 RK1
5054 18:03:49.143358 [ModeRegInit_LP4] CH1 RK0
5055 18:03:49.146468 [ModeRegInit_LP4] CH1 RK1
5056 18:03:49.146852 match AC timing 9
5057 18:03:49.152798 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5058 18:03:49.156244 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5059 18:03:49.159591 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5060 18:03:49.166388 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5061 18:03:49.169579 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5062 18:03:49.169931 ==
5063 18:03:49.173126 Dram Type= 6, Freq= 0, CH_0, rank 0
5064 18:03:49.176521 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5065 18:03:49.176943 ==
5066 18:03:49.183288 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5067 18:03:49.190264 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5068 18:03:49.193555 [CA 0] Center 38 (8~69) winsize 62
5069 18:03:49.196291 [CA 1] Center 37 (7~68) winsize 62
5070 18:03:49.200105 [CA 2] Center 35 (5~66) winsize 62
5071 18:03:49.202910 [CA 3] Center 34 (4~65) winsize 62
5072 18:03:49.206838 [CA 4] Center 34 (4~64) winsize 61
5073 18:03:49.209888 [CA 5] Center 34 (4~64) winsize 61
5074 18:03:49.210306
5075 18:03:49.213353 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5076 18:03:49.213769
5077 18:03:49.216597 [CATrainingPosCal] consider 1 rank data
5078 18:03:49.219997 u2DelayCellTimex100 = 270/100 ps
5079 18:03:49.222937 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5080 18:03:49.226325 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5081 18:03:49.229838 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5082 18:03:49.233226 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5083 18:03:49.236705 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5084 18:03:49.240415 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5085 18:03:49.240926
5086 18:03:49.246833 CA PerBit enable=1, Macro0, CA PI delay=34
5087 18:03:49.247328
5088 18:03:49.247658 [CBTSetCACLKResult] CA Dly = 34
5089 18:03:49.250406 CS Dly: 6 (0~37)
5090 18:03:49.250828 ==
5091 18:03:49.253244 Dram Type= 6, Freq= 0, CH_0, rank 1
5092 18:03:49.256702 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5093 18:03:49.257247 ==
5094 18:03:49.263571 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5095 18:03:49.270084 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5096 18:03:49.273030 [CA 0] Center 38 (7~69) winsize 63
5097 18:03:49.277106 [CA 1] Center 38 (7~69) winsize 63
5098 18:03:49.280573 [CA 2] Center 35 (5~66) winsize 62
5099 18:03:49.283517 [CA 3] Center 35 (4~66) winsize 63
5100 18:03:49.287261 [CA 4] Center 34 (4~65) winsize 62
5101 18:03:49.290323 [CA 5] Center 33 (3~64) winsize 62
5102 18:03:49.290877
5103 18:03:49.293121 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5104 18:03:49.293613
5105 18:03:49.297039 [CATrainingPosCal] consider 2 rank data
5106 18:03:49.299884 u2DelayCellTimex100 = 270/100 ps
5107 18:03:49.303402 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5108 18:03:49.306839 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5109 18:03:49.310510 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5110 18:03:49.313721 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5111 18:03:49.316910 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5112 18:03:49.320389 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5113 18:03:49.320800
5114 18:03:49.323387 CA PerBit enable=1, Macro0, CA PI delay=34
5115 18:03:49.326638
5116 18:03:49.327051 [CBTSetCACLKResult] CA Dly = 34
5117 18:03:49.330081 CS Dly: 7 (0~39)
5118 18:03:49.330579
5119 18:03:49.333467 ----->DramcWriteLeveling(PI) begin...
5120 18:03:49.333885 ==
5121 18:03:49.336575 Dram Type= 6, Freq= 0, CH_0, rank 0
5122 18:03:49.339895 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5123 18:03:49.340309 ==
5124 18:03:49.343469 Write leveling (Byte 0): 34 => 34
5125 18:03:49.346422 Write leveling (Byte 1): 26 => 26
5126 18:03:49.349920 DramcWriteLeveling(PI) end<-----
5127 18:03:49.350332
5128 18:03:49.350661 ==
5129 18:03:49.353335 Dram Type= 6, Freq= 0, CH_0, rank 0
5130 18:03:49.356508 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5131 18:03:49.359684 ==
5132 18:03:49.360221 [Gating] SW mode calibration
5133 18:03:49.366561 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5134 18:03:49.372944 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5135 18:03:49.376497 0 14 0 | B1->B0 | 2323 2c2c | 1 0 | (1 1) (0 0)
5136 18:03:49.383209 0 14 4 | B1->B0 | 2d2d 3434 | 1 1 | (1 1) (1 1)
5137 18:03:49.386141 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5138 18:03:49.389501 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5139 18:03:49.396028 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5140 18:03:49.399336 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5141 18:03:49.402516 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5142 18:03:49.409462 0 14 28 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
5143 18:03:49.412826 0 15 0 | B1->B0 | 3131 2929 | 0 1 | (0 1) (1 1)
5144 18:03:49.416414 0 15 4 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
5145 18:03:49.423066 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5146 18:03:49.426335 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5147 18:03:49.428933 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5148 18:03:49.435679 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5149 18:03:49.439159 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5150 18:03:49.442156 0 15 28 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5151 18:03:49.445554 1 0 0 | B1->B0 | 2f2f 3c3c | 1 1 | (0 0) (0 0)
5152 18:03:49.452530 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5153 18:03:49.456053 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5154 18:03:49.459023 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5155 18:03:49.465807 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5156 18:03:49.468936 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5157 18:03:49.472385 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5158 18:03:49.479180 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5159 18:03:49.482591 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5160 18:03:49.485328 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5161 18:03:49.492020 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5162 18:03:49.495640 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5163 18:03:49.499084 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5164 18:03:49.505969 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5165 18:03:49.509072 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5166 18:03:49.512105 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5167 18:03:49.518746 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5168 18:03:49.522069 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5169 18:03:49.525326 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5170 18:03:49.532315 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5171 18:03:49.535407 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5172 18:03:49.538724 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5173 18:03:49.545686 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5174 18:03:49.549353 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5175 18:03:49.552198 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5176 18:03:49.558979 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5177 18:03:49.562490 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5178 18:03:49.565440 Total UI for P1: 0, mck2ui 16
5179 18:03:49.568823 best dqsien dly found for B0: ( 1, 3, 2)
5180 18:03:49.572415 Total UI for P1: 0, mck2ui 16
5181 18:03:49.575882 best dqsien dly found for B1: ( 1, 3, 2)
5182 18:03:49.579164 best DQS0 dly(MCK, UI, PI) = (1, 3, 2)
5183 18:03:49.582358 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5184 18:03:49.582439
5185 18:03:49.585397 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 2)
5186 18:03:49.589258 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5187 18:03:49.592026 [Gating] SW calibration Done
5188 18:03:49.592111 ==
5189 18:03:49.595563 Dram Type= 6, Freq= 0, CH_0, rank 0
5190 18:03:49.599026 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5191 18:03:49.599108 ==
5192 18:03:49.602139 RX Vref Scan: 0
5193 18:03:49.602247
5194 18:03:49.602337 RX Vref 0 -> 0, step: 1
5195 18:03:49.602399
5196 18:03:49.606181 RX Delay -80 -> 252, step: 8
5197 18:03:49.608993 iDelay=200, Bit 0, Center 99 (8 ~ 191) 184
5198 18:03:49.615980 iDelay=200, Bit 1, Center 103 (8 ~ 199) 192
5199 18:03:49.619346 iDelay=200, Bit 2, Center 91 (-8 ~ 191) 200
5200 18:03:49.622511 iDelay=200, Bit 3, Center 91 (-8 ~ 191) 200
5201 18:03:49.626017 iDelay=200, Bit 4, Center 103 (8 ~ 199) 192
5202 18:03:49.629297 iDelay=200, Bit 5, Center 87 (-8 ~ 183) 192
5203 18:03:49.632772 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5204 18:03:49.636178 iDelay=200, Bit 7, Center 107 (16 ~ 199) 184
5205 18:03:49.643116 iDelay=200, Bit 8, Center 75 (-16 ~ 167) 184
5206 18:03:49.645784 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5207 18:03:49.649116 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5208 18:03:49.652861 iDelay=200, Bit 11, Center 79 (-16 ~ 175) 192
5209 18:03:49.656210 iDelay=200, Bit 12, Center 91 (-8 ~ 191) 200
5210 18:03:49.662465 iDelay=200, Bit 13, Center 91 (-8 ~ 191) 200
5211 18:03:49.665901 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5212 18:03:49.669422 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5213 18:03:49.669503 ==
5214 18:03:49.672438 Dram Type= 6, Freq= 0, CH_0, rank 0
5215 18:03:49.675855 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5216 18:03:49.675940 ==
5217 18:03:49.679352 DQS Delay:
5218 18:03:49.679432 DQS0 = 0, DQS1 = 0
5219 18:03:49.679495 DQM Delay:
5220 18:03:49.682851 DQM0 = 98, DQM1 = 86
5221 18:03:49.682930 DQ Delay:
5222 18:03:49.685703 DQ0 =99, DQ1 =103, DQ2 =91, DQ3 =91
5223 18:03:49.689222 DQ4 =103, DQ5 =87, DQ6 =107, DQ7 =107
5224 18:03:49.692496 DQ8 =75, DQ9 =79, DQ10 =87, DQ11 =79
5225 18:03:49.696093 DQ12 =91, DQ13 =91, DQ14 =95, DQ15 =95
5226 18:03:49.696173
5227 18:03:49.696235
5228 18:03:49.699467 ==
5229 18:03:49.702558 Dram Type= 6, Freq= 0, CH_0, rank 0
5230 18:03:49.705835 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5231 18:03:49.705916 ==
5232 18:03:49.705980
5233 18:03:49.706042
5234 18:03:49.709205 TX Vref Scan disable
5235 18:03:49.709285 == TX Byte 0 ==
5236 18:03:49.712297 Update DQ dly =719 (2 ,6, 15) DQ OEN =(2 ,3)
5237 18:03:49.719260 Update DQM dly =719 (2 ,6, 15) DQM OEN =(2 ,3)
5238 18:03:49.719341 == TX Byte 1 ==
5239 18:03:49.722253 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5240 18:03:49.728924 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5241 18:03:49.729053 ==
5242 18:03:49.732545 Dram Type= 6, Freq= 0, CH_0, rank 0
5243 18:03:49.735897 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5244 18:03:49.735974 ==
5245 18:03:49.736036
5246 18:03:49.736095
5247 18:03:49.739115 TX Vref Scan disable
5248 18:03:49.742556 == TX Byte 0 ==
5249 18:03:49.745927 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5250 18:03:49.749173 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5251 18:03:49.752654 == TX Byte 1 ==
5252 18:03:49.755861 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5253 18:03:49.759285 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5254 18:03:49.759369
5255 18:03:49.762850 [DATLAT]
5256 18:03:49.762930 Freq=933, CH0 RK0
5257 18:03:49.762993
5258 18:03:49.765587 DATLAT Default: 0xd
5259 18:03:49.765667 0, 0xFFFF, sum = 0
5260 18:03:49.769174 1, 0xFFFF, sum = 0
5261 18:03:49.769282 2, 0xFFFF, sum = 0
5262 18:03:49.772692 3, 0xFFFF, sum = 0
5263 18:03:49.772789 4, 0xFFFF, sum = 0
5264 18:03:49.776160 5, 0xFFFF, sum = 0
5265 18:03:49.776242 6, 0xFFFF, sum = 0
5266 18:03:49.779092 7, 0xFFFF, sum = 0
5267 18:03:49.779173 8, 0xFFFF, sum = 0
5268 18:03:49.782478 9, 0xFFFF, sum = 0
5269 18:03:49.782559 10, 0x0, sum = 1
5270 18:03:49.786013 11, 0x0, sum = 2
5271 18:03:49.786094 12, 0x0, sum = 3
5272 18:03:49.789575 13, 0x0, sum = 4
5273 18:03:49.789655 best_step = 11
5274 18:03:49.789719
5275 18:03:49.789777 ==
5276 18:03:49.793033 Dram Type= 6, Freq= 0, CH_0, rank 0
5277 18:03:49.796431 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5278 18:03:49.796513 ==
5279 18:03:49.799383 RX Vref Scan: 1
5280 18:03:49.799464
5281 18:03:49.802692 RX Vref 0 -> 0, step: 1
5282 18:03:49.802774
5283 18:03:49.802838 RX Delay -61 -> 252, step: 4
5284 18:03:49.802940
5285 18:03:49.806069 Set Vref, RX VrefLevel [Byte0]: 53
5286 18:03:49.809125 [Byte1]: 51
5287 18:03:49.813804
5288 18:03:49.813916 Final RX Vref Byte 0 = 53 to rank0
5289 18:03:49.817252 Final RX Vref Byte 1 = 51 to rank0
5290 18:03:49.820644 Final RX Vref Byte 0 = 53 to rank1
5291 18:03:49.824286 Final RX Vref Byte 1 = 51 to rank1==
5292 18:03:49.827625 Dram Type= 6, Freq= 0, CH_0, rank 0
5293 18:03:49.833748 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5294 18:03:49.833862 ==
5295 18:03:49.833956 DQS Delay:
5296 18:03:49.834049 DQS0 = 0, DQS1 = 0
5297 18:03:49.837934 DQM Delay:
5298 18:03:49.838039 DQM0 = 96, DQM1 = 88
5299 18:03:49.840902 DQ Delay:
5300 18:03:49.844088 DQ0 =98, DQ1 =98, DQ2 =92, DQ3 =94
5301 18:03:49.847431 DQ4 =98, DQ5 =86, DQ6 =104, DQ7 =102
5302 18:03:49.850859 DQ8 =78, DQ9 =76, DQ10 =90, DQ11 =80
5303 18:03:49.853623 DQ12 =96, DQ13 =92, DQ14 =98, DQ15 =94
5304 18:03:49.853734
5305 18:03:49.853828
5306 18:03:49.860611 [DQSOSCAuto] RK0, (LSB)MR18= 0x1500, (MSB)MR19= 0x505, tDQSOscB0 = 422 ps tDQSOscB1 = 415 ps
5307 18:03:49.863751 CH0 RK0: MR19=505, MR18=1500
5308 18:03:49.870475 CH0_RK0: MR19=0x505, MR18=0x1500, DQSOSC=415, MR23=63, INC=62, DEC=41
5309 18:03:49.870560
5310 18:03:49.874107 ----->DramcWriteLeveling(PI) begin...
5311 18:03:49.874189 ==
5312 18:03:49.877151 Dram Type= 6, Freq= 0, CH_0, rank 1
5313 18:03:49.880553 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5314 18:03:49.880635 ==
5315 18:03:49.884129 Write leveling (Byte 0): 29 => 29
5316 18:03:49.886958 Write leveling (Byte 1): 29 => 29
5317 18:03:49.890434 DramcWriteLeveling(PI) end<-----
5318 18:03:49.890514
5319 18:03:49.890577 ==
5320 18:03:49.894000 Dram Type= 6, Freq= 0, CH_0, rank 1
5321 18:03:49.897047 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5322 18:03:49.897127 ==
5323 18:03:49.900384 [Gating] SW mode calibration
5324 18:03:49.907370 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5325 18:03:49.914458 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5326 18:03:49.917210 0 14 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
5327 18:03:49.920435 0 14 4 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
5328 18:03:49.927664 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5329 18:03:49.931230 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5330 18:03:49.934498 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5331 18:03:49.940892 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5332 18:03:49.944548 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5333 18:03:49.947622 0 14 28 | B1->B0 | 3232 2f2f | 0 0 | (0 0) (0 1)
5334 18:03:49.954336 0 15 0 | B1->B0 | 2f2f 2323 | 1 0 | (1 1) (1 0)
5335 18:03:49.957758 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5336 18:03:49.960901 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5337 18:03:49.967684 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5338 18:03:49.971389 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5339 18:03:49.974281 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5340 18:03:49.977473 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5341 18:03:49.984361 0 15 28 | B1->B0 | 2424 3333 | 1 1 | (0 0) (0 0)
5342 18:03:49.987816 1 0 0 | B1->B0 | 3535 4646 | 0 0 | (0 0) (0 0)
5343 18:03:49.991259 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5344 18:03:49.997696 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5345 18:03:50.001123 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5346 18:03:50.004508 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5347 18:03:50.011028 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5348 18:03:50.014474 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5349 18:03:50.017766 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5350 18:03:50.024178 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5351 18:03:50.027743 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5352 18:03:50.031073 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5353 18:03:50.037555 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5354 18:03:50.041012 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5355 18:03:50.044340 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5356 18:03:50.051328 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5357 18:03:50.054087 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5358 18:03:50.057543 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5359 18:03:50.061135 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5360 18:03:50.067611 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5361 18:03:50.070933 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5362 18:03:50.074330 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5363 18:03:50.080857 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5364 18:03:50.084248 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5365 18:03:50.087969 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5366 18:03:50.094801 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
5367 18:03:50.097847 Total UI for P1: 0, mck2ui 16
5368 18:03:50.100922 best dqsien dly found for B0: ( 1, 2, 26)
5369 18:03:50.104519 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5370 18:03:50.107902 Total UI for P1: 0, mck2ui 16
5371 18:03:50.110927 best dqsien dly found for B1: ( 1, 3, 2)
5372 18:03:50.114457 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5373 18:03:50.117855 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5374 18:03:50.117964
5375 18:03:50.121265 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5376 18:03:50.124247 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5377 18:03:50.127689 [Gating] SW calibration Done
5378 18:03:50.127797 ==
5379 18:03:50.130811 Dram Type= 6, Freq= 0, CH_0, rank 1
5380 18:03:50.134186 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5381 18:03:50.134272 ==
5382 18:03:50.137574 RX Vref Scan: 0
5383 18:03:50.137654
5384 18:03:50.140892 RX Vref 0 -> 0, step: 1
5385 18:03:50.141001
5386 18:03:50.141070 RX Delay -80 -> 252, step: 8
5387 18:03:50.148196 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5388 18:03:50.151102 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5389 18:03:50.154211 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5390 18:03:50.157837 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5391 18:03:50.161193 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5392 18:03:50.164272 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5393 18:03:50.171006 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5394 18:03:50.174368 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5395 18:03:50.177725 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5396 18:03:50.180882 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5397 18:03:50.184875 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5398 18:03:50.187980 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5399 18:03:50.194496 iDelay=208, Bit 12, Center 91 (0 ~ 183) 184
5400 18:03:50.197689 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5401 18:03:50.201739 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5402 18:03:50.204518 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5403 18:03:50.204603 ==
5404 18:03:50.208059 Dram Type= 6, Freq= 0, CH_0, rank 1
5405 18:03:50.211279 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5406 18:03:50.211360 ==
5407 18:03:50.214741 DQS Delay:
5408 18:03:50.214821 DQS0 = 0, DQS1 = 0
5409 18:03:50.218179 DQM Delay:
5410 18:03:50.218259 DQM0 = 97, DQM1 = 87
5411 18:03:50.218322 DQ Delay:
5412 18:03:50.221169 DQ0 =99, DQ1 =99, DQ2 =95, DQ3 =95
5413 18:03:50.224502 DQ4 =95, DQ5 =87, DQ6 =107, DQ7 =103
5414 18:03:50.227834 DQ8 =83, DQ9 =79, DQ10 =87, DQ11 =79
5415 18:03:50.231292 DQ12 =91, DQ13 =91, DQ14 =95, DQ15 =95
5416 18:03:50.231399
5417 18:03:50.231489
5418 18:03:50.234883 ==
5419 18:03:50.238105 Dram Type= 6, Freq= 0, CH_0, rank 1
5420 18:03:50.241012 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5421 18:03:50.241093 ==
5422 18:03:50.241156
5423 18:03:50.241215
5424 18:03:50.244446 TX Vref Scan disable
5425 18:03:50.244526 == TX Byte 0 ==
5426 18:03:50.247936 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5427 18:03:50.254736 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5428 18:03:50.254821 == TX Byte 1 ==
5429 18:03:50.257890 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5430 18:03:50.264862 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5431 18:03:50.264952 ==
5432 18:03:50.267652 Dram Type= 6, Freq= 0, CH_0, rank 1
5433 18:03:50.271222 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5434 18:03:50.271361 ==
5435 18:03:50.271460
5436 18:03:50.271557
5437 18:03:50.274544 TX Vref Scan disable
5438 18:03:50.278151 == TX Byte 0 ==
5439 18:03:50.281172 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5440 18:03:50.284686 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5441 18:03:50.287686 == TX Byte 1 ==
5442 18:03:50.291287 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5443 18:03:50.294663 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5444 18:03:50.294771
5445 18:03:50.294864 [DATLAT]
5446 18:03:50.297545 Freq=933, CH0 RK1
5447 18:03:50.297653
5448 18:03:50.301042 DATLAT Default: 0xb
5449 18:03:50.301150 0, 0xFFFF, sum = 0
5450 18:03:50.304738 1, 0xFFFF, sum = 0
5451 18:03:50.304845 2, 0xFFFF, sum = 0
5452 18:03:50.307909 3, 0xFFFF, sum = 0
5453 18:03:50.308020 4, 0xFFFF, sum = 0
5454 18:03:50.311124 5, 0xFFFF, sum = 0
5455 18:03:50.311235 6, 0xFFFF, sum = 0
5456 18:03:50.314340 7, 0xFFFF, sum = 0
5457 18:03:50.314446 8, 0xFFFF, sum = 0
5458 18:03:50.317906 9, 0xFFFF, sum = 0
5459 18:03:50.318018 10, 0x0, sum = 1
5460 18:03:50.321705 11, 0x0, sum = 2
5461 18:03:50.321814 12, 0x0, sum = 3
5462 18:03:50.324576 13, 0x0, sum = 4
5463 18:03:50.324682 best_step = 11
5464 18:03:50.324778
5465 18:03:50.324870 ==
5466 18:03:50.327932 Dram Type= 6, Freq= 0, CH_0, rank 1
5467 18:03:50.331524 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5468 18:03:50.331632 ==
5469 18:03:50.334215 RX Vref Scan: 0
5470 18:03:50.334321
5471 18:03:50.337888 RX Vref 0 -> 0, step: 1
5472 18:03:50.337995
5473 18:03:50.338089 RX Delay -61 -> 252, step: 4
5474 18:03:50.345812 iDelay=199, Bit 0, Center 94 (-1 ~ 190) 192
5475 18:03:50.349069 iDelay=199, Bit 1, Center 96 (3 ~ 190) 188
5476 18:03:50.352513 iDelay=199, Bit 2, Center 92 (-1 ~ 186) 188
5477 18:03:50.355560 iDelay=199, Bit 3, Center 94 (-1 ~ 190) 192
5478 18:03:50.359074 iDelay=199, Bit 4, Center 94 (3 ~ 186) 184
5479 18:03:50.362425 iDelay=199, Bit 5, Center 86 (-5 ~ 178) 184
5480 18:03:50.368839 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5481 18:03:50.372202 iDelay=199, Bit 7, Center 102 (11 ~ 194) 184
5482 18:03:50.375620 iDelay=199, Bit 8, Center 80 (-9 ~ 170) 180
5483 18:03:50.379291 iDelay=199, Bit 9, Center 80 (-9 ~ 170) 180
5484 18:03:50.382681 iDelay=199, Bit 10, Center 88 (-1 ~ 178) 180
5485 18:03:50.385842 iDelay=199, Bit 11, Center 80 (-5 ~ 166) 172
5486 18:03:50.392720 iDelay=199, Bit 12, Center 90 (-1 ~ 182) 184
5487 18:03:50.395843 iDelay=199, Bit 13, Center 92 (3 ~ 182) 180
5488 18:03:50.399157 iDelay=199, Bit 14, Center 96 (7 ~ 186) 180
5489 18:03:50.402620 iDelay=199, Bit 15, Center 96 (7 ~ 186) 180
5490 18:03:50.402730 ==
5491 18:03:50.406159 Dram Type= 6, Freq= 0, CH_0, rank 1
5492 18:03:50.409031 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5493 18:03:50.412393 ==
5494 18:03:50.412497 DQS Delay:
5495 18:03:50.412589 DQS0 = 0, DQS1 = 0
5496 18:03:50.415913 DQM Delay:
5497 18:03:50.416020 DQM0 = 95, DQM1 = 87
5498 18:03:50.416115 DQ Delay:
5499 18:03:50.419341 DQ0 =94, DQ1 =96, DQ2 =92, DQ3 =94
5500 18:03:50.423138 DQ4 =94, DQ5 =86, DQ6 =104, DQ7 =102
5501 18:03:50.426551 DQ8 =80, DQ9 =80, DQ10 =88, DQ11 =80
5502 18:03:50.429400 DQ12 =90, DQ13 =92, DQ14 =96, DQ15 =96
5503 18:03:50.429504
5504 18:03:50.432479
5505 18:03:50.439560 [DQSOSCAuto] RK1, (LSB)MR18= 0x1a08, (MSB)MR19= 0x505, tDQSOscB0 = 419 ps tDQSOscB1 = 413 ps
5506 18:03:50.442607 CH0 RK1: MR19=505, MR18=1A08
5507 18:03:50.449507 CH0_RK1: MR19=0x505, MR18=0x1A08, DQSOSC=413, MR23=63, INC=63, DEC=42
5508 18:03:50.449618 [RxdqsGatingPostProcess] freq 933
5509 18:03:50.455839 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5510 18:03:50.459547 best DQS0 dly(2T, 0.5T) = (0, 11)
5511 18:03:50.462894 best DQS1 dly(2T, 0.5T) = (0, 11)
5512 18:03:50.466393 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
5513 18:03:50.469160 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5514 18:03:50.472576 best DQS0 dly(2T, 0.5T) = (0, 10)
5515 18:03:50.476007 best DQS1 dly(2T, 0.5T) = (0, 11)
5516 18:03:50.479198 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5517 18:03:50.482537 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5518 18:03:50.486236 Pre-setting of DQS Precalculation
5519 18:03:50.489173 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5520 18:03:50.489287 ==
5521 18:03:50.492726 Dram Type= 6, Freq= 0, CH_1, rank 0
5522 18:03:50.496130 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5523 18:03:50.496240 ==
5524 18:03:50.502637 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5525 18:03:50.509364 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5526 18:03:50.512801 [CA 0] Center 36 (6~67) winsize 62
5527 18:03:50.516148 [CA 1] Center 36 (6~67) winsize 62
5528 18:03:50.519333 [CA 2] Center 34 (4~64) winsize 61
5529 18:03:50.522903 [CA 3] Center 33 (2~64) winsize 63
5530 18:03:50.525833 [CA 4] Center 33 (3~64) winsize 62
5531 18:03:50.529390 [CA 5] Center 32 (2~63) winsize 62
5532 18:03:50.529497
5533 18:03:50.532601 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5534 18:03:50.532708
5535 18:03:50.536022 [CATrainingPosCal] consider 1 rank data
5536 18:03:50.539362 u2DelayCellTimex100 = 270/100 ps
5537 18:03:50.542668 CA0 delay=36 (6~67),Diff = 4 PI (24 cell)
5538 18:03:50.546357 CA1 delay=36 (6~67),Diff = 4 PI (24 cell)
5539 18:03:50.549050 CA2 delay=34 (4~64),Diff = 2 PI (12 cell)
5540 18:03:50.552462 CA3 delay=33 (2~64),Diff = 1 PI (6 cell)
5541 18:03:50.556396 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5542 18:03:50.559304 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5543 18:03:50.562972
5544 18:03:50.566177 CA PerBit enable=1, Macro0, CA PI delay=32
5545 18:03:50.566285
5546 18:03:50.569195 [CBTSetCACLKResult] CA Dly = 32
5547 18:03:50.569305 CS Dly: 4 (0~35)
5548 18:03:50.569403 ==
5549 18:03:50.572738 Dram Type= 6, Freq= 0, CH_1, rank 1
5550 18:03:50.575818 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5551 18:03:50.575925 ==
5552 18:03:50.582748 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5553 18:03:50.589514 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5554 18:03:50.592794 [CA 0] Center 36 (6~67) winsize 62
5555 18:03:50.596295 [CA 1] Center 37 (7~67) winsize 61
5556 18:03:50.599256 [CA 2] Center 33 (3~64) winsize 62
5557 18:03:50.603090 [CA 3] Center 33 (3~64) winsize 62
5558 18:03:50.605783 [CA 4] Center 33 (3~64) winsize 62
5559 18:03:50.609317 [CA 5] Center 32 (2~63) winsize 62
5560 18:03:50.609429
5561 18:03:50.612829 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5562 18:03:50.612939
5563 18:03:50.616206 [CATrainingPosCal] consider 2 rank data
5564 18:03:50.619744 u2DelayCellTimex100 = 270/100 ps
5565 18:03:50.622591 CA0 delay=36 (6~67),Diff = 4 PI (24 cell)
5566 18:03:50.626242 CA1 delay=37 (7~67),Diff = 5 PI (31 cell)
5567 18:03:50.629282 CA2 delay=34 (4~64),Diff = 2 PI (12 cell)
5568 18:03:50.632850 CA3 delay=33 (3~64),Diff = 1 PI (6 cell)
5569 18:03:50.635972 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5570 18:03:50.639381 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5571 18:03:50.642773
5572 18:03:50.645930 CA PerBit enable=1, Macro0, CA PI delay=32
5573 18:03:50.646035
5574 18:03:50.649268 [CBTSetCACLKResult] CA Dly = 32
5575 18:03:50.649381 CS Dly: 5 (0~38)
5576 18:03:50.649480
5577 18:03:50.652848 ----->DramcWriteLeveling(PI) begin...
5578 18:03:50.652982 ==
5579 18:03:50.656197 Dram Type= 6, Freq= 0, CH_1, rank 0
5580 18:03:50.659875 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5581 18:03:50.659982 ==
5582 18:03:50.662606 Write leveling (Byte 0): 28 => 28
5583 18:03:50.666130 Write leveling (Byte 1): 27 => 27
5584 18:03:50.669568 DramcWriteLeveling(PI) end<-----
5585 18:03:50.669677
5586 18:03:50.669774 ==
5587 18:03:50.672924 Dram Type= 6, Freq= 0, CH_1, rank 0
5588 18:03:50.679795 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5589 18:03:50.679908 ==
5590 18:03:50.680008 [Gating] SW mode calibration
5591 18:03:50.689684 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5592 18:03:50.692923 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5593 18:03:50.696452 0 14 0 | B1->B0 | 3232 3333 | 1 0 | (1 1) (0 0)
5594 18:03:50.702986 0 14 4 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5595 18:03:50.706468 0 14 8 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5596 18:03:50.709425 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5597 18:03:50.716055 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5598 18:03:50.719448 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5599 18:03:50.722906 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5600 18:03:50.729748 0 14 28 | B1->B0 | 2e2e 3333 | 1 1 | (1 0) (1 0)
5601 18:03:50.732876 0 15 0 | B1->B0 | 2626 2929 | 0 0 | (0 0) (0 0)
5602 18:03:50.736496 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5603 18:03:50.742860 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5604 18:03:50.746400 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5605 18:03:50.749923 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5606 18:03:50.756110 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5607 18:03:50.759387 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5608 18:03:50.763092 0 15 28 | B1->B0 | 2e2e 2d2d | 1 0 | (0 0) (0 0)
5609 18:03:50.769341 1 0 0 | B1->B0 | 3f3f 4343 | 0 0 | (0 0) (0 0)
5610 18:03:50.772908 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5611 18:03:50.776269 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5612 18:03:50.779787 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5613 18:03:50.786175 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5614 18:03:50.789398 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5615 18:03:50.792348 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5616 18:03:50.799180 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5617 18:03:50.802547 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5618 18:03:50.806173 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5619 18:03:50.812757 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5620 18:03:50.815883 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5621 18:03:50.819288 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5622 18:03:50.826052 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5623 18:03:50.830012 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5624 18:03:50.832675 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5625 18:03:50.839234 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5626 18:03:50.842687 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5627 18:03:50.845894 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5628 18:03:50.852551 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5629 18:03:50.856327 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5630 18:03:50.859316 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5631 18:03:50.866190 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5632 18:03:50.869265 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5633 18:03:50.872878 Total UI for P1: 0, mck2ui 16
5634 18:03:50.876256 best dqsien dly found for B0: ( 1, 2, 26)
5635 18:03:50.879654 Total UI for P1: 0, mck2ui 16
5636 18:03:50.882525 best dqsien dly found for B1: ( 1, 2, 26)
5637 18:03:50.885900 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5638 18:03:50.889333 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5639 18:03:50.889444
5640 18:03:50.892774 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5641 18:03:50.896263 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5642 18:03:50.899213 [Gating] SW calibration Done
5643 18:03:50.899319 ==
5644 18:03:50.902708 Dram Type= 6, Freq= 0, CH_1, rank 0
5645 18:03:50.906112 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5646 18:03:50.906222 ==
5647 18:03:50.909521 RX Vref Scan: 0
5648 18:03:50.909627
5649 18:03:50.909722 RX Vref 0 -> 0, step: 1
5650 18:03:50.912839
5651 18:03:50.912944 RX Delay -80 -> 252, step: 8
5652 18:03:50.919331 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5653 18:03:50.922773 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5654 18:03:50.926658 iDelay=208, Bit 2, Center 79 (-16 ~ 175) 192
5655 18:03:50.929399 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5656 18:03:50.932617 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5657 18:03:50.936072 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5658 18:03:50.942614 iDelay=208, Bit 6, Center 107 (16 ~ 199) 184
5659 18:03:50.946015 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5660 18:03:50.949526 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5661 18:03:50.952452 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5662 18:03:50.955887 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5663 18:03:50.963132 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5664 18:03:50.965856 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5665 18:03:50.969262 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5666 18:03:50.972603 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5667 18:03:50.976426 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5668 18:03:50.976535 ==
5669 18:03:50.979368 Dram Type= 6, Freq= 0, CH_1, rank 0
5670 18:03:50.982775 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5671 18:03:50.986015 ==
5672 18:03:50.986124 DQS Delay:
5673 18:03:50.986221 DQS0 = 0, DQS1 = 0
5674 18:03:50.989420 DQM Delay:
5675 18:03:50.989532 DQM0 = 94, DQM1 = 88
5676 18:03:50.992689 DQ Delay:
5677 18:03:50.992810 DQ0 =95, DQ1 =91, DQ2 =79, DQ3 =91
5678 18:03:50.996403 DQ4 =95, DQ5 =107, DQ6 =107, DQ7 =91
5679 18:03:50.999674 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =83
5680 18:03:51.003348 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5681 18:03:51.003456
5682 18:03:51.006568
5683 18:03:51.006669 ==
5684 18:03:51.010003 Dram Type= 6, Freq= 0, CH_1, rank 0
5685 18:03:51.012632 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5686 18:03:51.012735 ==
5687 18:03:51.012825
5688 18:03:51.012911
5689 18:03:51.015970 TX Vref Scan disable
5690 18:03:51.016066 == TX Byte 0 ==
5691 18:03:51.019406 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5692 18:03:51.026388 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5693 18:03:51.026501 == TX Byte 1 ==
5694 18:03:51.032727 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5695 18:03:51.036214 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5696 18:03:51.036318 ==
5697 18:03:51.039463 Dram Type= 6, Freq= 0, CH_1, rank 0
5698 18:03:51.043197 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5699 18:03:51.043301 ==
5700 18:03:51.043415
5701 18:03:51.043516
5702 18:03:51.046177 TX Vref Scan disable
5703 18:03:51.049461 == TX Byte 0 ==
5704 18:03:51.053398 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5705 18:03:51.056506 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5706 18:03:51.059760 == TX Byte 1 ==
5707 18:03:51.062956 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5708 18:03:51.066278 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5709 18:03:51.066384
5710 18:03:51.066474 [DATLAT]
5711 18:03:51.069685 Freq=933, CH1 RK0
5712 18:03:51.069790
5713 18:03:51.072939 DATLAT Default: 0xd
5714 18:03:51.073077 0, 0xFFFF, sum = 0
5715 18:03:51.076390 1, 0xFFFF, sum = 0
5716 18:03:51.076493 2, 0xFFFF, sum = 0
5717 18:03:51.079709 3, 0xFFFF, sum = 0
5718 18:03:51.079813 4, 0xFFFF, sum = 0
5719 18:03:51.083315 5, 0xFFFF, sum = 0
5720 18:03:51.083421 6, 0xFFFF, sum = 0
5721 18:03:51.085981 7, 0xFFFF, sum = 0
5722 18:03:51.086085 8, 0xFFFF, sum = 0
5723 18:03:51.089646 9, 0xFFFF, sum = 0
5724 18:03:51.089752 10, 0x0, sum = 1
5725 18:03:51.092788 11, 0x0, sum = 2
5726 18:03:51.092911 12, 0x0, sum = 3
5727 18:03:51.096240 13, 0x0, sum = 4
5728 18:03:51.096346 best_step = 11
5729 18:03:51.096436
5730 18:03:51.096524 ==
5731 18:03:51.099692 Dram Type= 6, Freq= 0, CH_1, rank 0
5732 18:03:51.103202 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5733 18:03:51.103309 ==
5734 18:03:51.106062 RX Vref Scan: 1
5735 18:03:51.106164
5736 18:03:51.109476 RX Vref 0 -> 0, step: 1
5737 18:03:51.109580
5738 18:03:51.109675 RX Delay -61 -> 252, step: 4
5739 18:03:51.112940
5740 18:03:51.113080 Set Vref, RX VrefLevel [Byte0]: 56
5741 18:03:51.116202 [Byte1]: 53
5742 18:03:51.120956
5743 18:03:51.121097 Final RX Vref Byte 0 = 56 to rank0
5744 18:03:51.124160 Final RX Vref Byte 1 = 53 to rank0
5745 18:03:51.127700 Final RX Vref Byte 0 = 56 to rank1
5746 18:03:51.131181 Final RX Vref Byte 1 = 53 to rank1==
5747 18:03:51.134790 Dram Type= 6, Freq= 0, CH_1, rank 0
5748 18:03:51.140952 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5749 18:03:51.141095 ==
5750 18:03:51.141185 DQS Delay:
5751 18:03:51.141276 DQS0 = 0, DQS1 = 0
5752 18:03:51.144370 DQM Delay:
5753 18:03:51.144471 DQM0 = 97, DQM1 = 91
5754 18:03:51.147741 DQ Delay:
5755 18:03:51.151111 DQ0 =102, DQ1 =92, DQ2 =88, DQ3 =96
5756 18:03:51.154362 DQ4 =96, DQ5 =108, DQ6 =106, DQ7 =94
5757 18:03:51.157414 DQ8 =80, DQ9 =80, DQ10 =96, DQ11 =86
5758 18:03:51.160978 DQ12 =96, DQ13 =98, DQ14 =96, DQ15 =96
5759 18:03:51.161111
5760 18:03:51.161202
5761 18:03:51.167851 [DQSOSCAuto] RK0, (LSB)MR18= 0x15f3, (MSB)MR19= 0x504, tDQSOscB0 = 426 ps tDQSOscB1 = 415 ps
5762 18:03:51.170954 CH1 RK0: MR19=504, MR18=15F3
5763 18:03:51.177714 CH1_RK0: MR19=0x504, MR18=0x15F3, DQSOSC=415, MR23=63, INC=62, DEC=41
5764 18:03:51.177821
5765 18:03:51.180743 ----->DramcWriteLeveling(PI) begin...
5766 18:03:51.180847 ==
5767 18:03:51.184158 Dram Type= 6, Freq= 0, CH_1, rank 1
5768 18:03:51.187889 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5769 18:03:51.187995 ==
5770 18:03:51.190811 Write leveling (Byte 0): 27 => 27
5771 18:03:51.194285 Write leveling (Byte 1): 27 => 27
5772 18:03:51.197476 DramcWriteLeveling(PI) end<-----
5773 18:03:51.197581
5774 18:03:51.197672 ==
5775 18:03:51.200766 Dram Type= 6, Freq= 0, CH_1, rank 1
5776 18:03:51.204455 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5777 18:03:51.204558 ==
5778 18:03:51.207386 [Gating] SW mode calibration
5779 18:03:51.214357 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5780 18:03:51.220781 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5781 18:03:51.224296 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5782 18:03:51.227688 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5783 18:03:51.234516 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5784 18:03:51.237469 0 14 12 | B1->B0 | 3535 3434 | 1 1 | (0 0) (1 1)
5785 18:03:51.240849 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5786 18:03:51.247665 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5787 18:03:51.251099 0 14 24 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (1 0)
5788 18:03:51.254616 0 14 28 | B1->B0 | 2a2a 2323 | 0 0 | (1 1) (0 0)
5789 18:03:51.260727 0 15 0 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
5790 18:03:51.264383 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5791 18:03:51.267564 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5792 18:03:51.273919 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5793 18:03:51.277363 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5794 18:03:51.281161 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5795 18:03:51.287987 0 15 24 | B1->B0 | 2727 3232 | 0 0 | (0 0) (0 0)
5796 18:03:51.290971 0 15 28 | B1->B0 | 3a3a 4646 | 1 0 | (0 0) (0 0)
5797 18:03:51.294326 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5798 18:03:51.300967 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5799 18:03:51.304530 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5800 18:03:51.307854 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5801 18:03:51.310743 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5802 18:03:51.317361 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5803 18:03:51.321638 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5804 18:03:51.324136 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5805 18:03:51.331148 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5806 18:03:51.334435 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5807 18:03:51.337543 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5808 18:03:51.344147 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5809 18:03:51.347712 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5810 18:03:51.351220 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5811 18:03:51.357935 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5812 18:03:51.360763 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5813 18:03:51.364290 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5814 18:03:51.370735 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5815 18:03:51.374434 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5816 18:03:51.377487 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5817 18:03:51.384350 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5818 18:03:51.387492 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5819 18:03:51.390874 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5820 18:03:51.397756 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5821 18:03:51.397884 Total UI for P1: 0, mck2ui 16
5822 18:03:51.403844 best dqsien dly found for B0: ( 1, 2, 22)
5823 18:03:51.407451 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5824 18:03:51.410919 Total UI for P1: 0, mck2ui 16
5825 18:03:51.414133 best dqsien dly found for B1: ( 1, 2, 28)
5826 18:03:51.417591 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5827 18:03:51.420633 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5828 18:03:51.420743
5829 18:03:51.423853 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5830 18:03:51.427402 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5831 18:03:51.431082 [Gating] SW calibration Done
5832 18:03:51.431186 ==
5833 18:03:51.433908 Dram Type= 6, Freq= 0, CH_1, rank 1
5834 18:03:51.437239 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5835 18:03:51.437349 ==
5836 18:03:51.440875 RX Vref Scan: 0
5837 18:03:51.440996
5838 18:03:51.443723 RX Vref 0 -> 0, step: 1
5839 18:03:51.443835
5840 18:03:51.443932 RX Delay -80 -> 252, step: 8
5841 18:03:51.450674 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5842 18:03:51.454081 iDelay=200, Bit 1, Center 91 (-8 ~ 191) 200
5843 18:03:51.457462 iDelay=200, Bit 2, Center 87 (-8 ~ 183) 192
5844 18:03:51.460370 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5845 18:03:51.463887 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5846 18:03:51.467187 iDelay=200, Bit 5, Center 103 (8 ~ 199) 192
5847 18:03:51.474133 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5848 18:03:51.477249 iDelay=200, Bit 7, Center 87 (-8 ~ 183) 192
5849 18:03:51.481081 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5850 18:03:51.483923 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5851 18:03:51.487113 iDelay=200, Bit 10, Center 91 (-8 ~ 191) 200
5852 18:03:51.490700 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5853 18:03:51.497883 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5854 18:03:51.500369 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5855 18:03:51.503709 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5856 18:03:51.507222 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5857 18:03:51.507310 ==
5858 18:03:51.510322 Dram Type= 6, Freq= 0, CH_1, rank 1
5859 18:03:51.513786 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5860 18:03:51.517278 ==
5861 18:03:51.517358 DQS Delay:
5862 18:03:51.517422 DQS0 = 0, DQS1 = 0
5863 18:03:51.520682 DQM Delay:
5864 18:03:51.520786 DQM0 = 94, DQM1 = 89
5865 18:03:51.524279 DQ Delay:
5866 18:03:51.527070 DQ0 =95, DQ1 =91, DQ2 =87, DQ3 =95
5867 18:03:51.530464 DQ4 =95, DQ5 =103, DQ6 =103, DQ7 =87
5868 18:03:51.530558 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =83
5869 18:03:51.536949 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5870 18:03:51.537055
5871 18:03:51.537119
5872 18:03:51.537201 ==
5873 18:03:51.540284 Dram Type= 6, Freq= 0, CH_1, rank 1
5874 18:03:51.544035 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5875 18:03:51.544116 ==
5876 18:03:51.544180
5877 18:03:51.544243
5878 18:03:51.547620 TX Vref Scan disable
5879 18:03:51.547694 == TX Byte 0 ==
5880 18:03:51.553583 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5881 18:03:51.557551 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5882 18:03:51.557629 == TX Byte 1 ==
5883 18:03:51.563858 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5884 18:03:51.567255 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5885 18:03:51.567367 ==
5886 18:03:51.570241 Dram Type= 6, Freq= 0, CH_1, rank 1
5887 18:03:51.573667 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5888 18:03:51.573754 ==
5889 18:03:51.573818
5890 18:03:51.573877
5891 18:03:51.577089 TX Vref Scan disable
5892 18:03:51.580470 == TX Byte 0 ==
5893 18:03:51.583907 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5894 18:03:51.587008 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5895 18:03:51.590662 == TX Byte 1 ==
5896 18:03:51.593382 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5897 18:03:51.596917 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5898 18:03:51.597058
5899 18:03:51.600249 [DATLAT]
5900 18:03:51.600342 Freq=933, CH1 RK1
5901 18:03:51.600406
5902 18:03:51.603784 DATLAT Default: 0xb
5903 18:03:51.603909 0, 0xFFFF, sum = 0
5904 18:03:51.607246 1, 0xFFFF, sum = 0
5905 18:03:51.607328 2, 0xFFFF, sum = 0
5906 18:03:51.610666 3, 0xFFFF, sum = 0
5907 18:03:51.610773 4, 0xFFFF, sum = 0
5908 18:03:51.614110 5, 0xFFFF, sum = 0
5909 18:03:51.614192 6, 0xFFFF, sum = 0
5910 18:03:51.616842 7, 0xFFFF, sum = 0
5911 18:03:51.616916 8, 0xFFFF, sum = 0
5912 18:03:51.620196 9, 0xFFFF, sum = 0
5913 18:03:51.620276 10, 0x0, sum = 1
5914 18:03:51.623809 11, 0x0, sum = 2
5915 18:03:51.623883 12, 0x0, sum = 3
5916 18:03:51.627075 13, 0x0, sum = 4
5917 18:03:51.627149 best_step = 11
5918 18:03:51.627209
5919 18:03:51.627266 ==
5920 18:03:51.630550 Dram Type= 6, Freq= 0, CH_1, rank 1
5921 18:03:51.633545 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5922 18:03:51.636919 ==
5923 18:03:51.637044 RX Vref Scan: 0
5924 18:03:51.637108
5925 18:03:51.640314 RX Vref 0 -> 0, step: 1
5926 18:03:51.640387
5927 18:03:51.643663 RX Delay -61 -> 252, step: 4
5928 18:03:51.647157 iDelay=199, Bit 0, Center 98 (7 ~ 190) 184
5929 18:03:51.650483 iDelay=199, Bit 1, Center 88 (-5 ~ 182) 188
5930 18:03:51.653546 iDelay=199, Bit 2, Center 84 (-9 ~ 178) 188
5931 18:03:51.660477 iDelay=199, Bit 3, Center 92 (-1 ~ 186) 188
5932 18:03:51.663842 iDelay=199, Bit 4, Center 96 (3 ~ 190) 188
5933 18:03:51.667132 iDelay=199, Bit 5, Center 104 (11 ~ 198) 188
5934 18:03:51.670538 iDelay=199, Bit 6, Center 102 (11 ~ 194) 184
5935 18:03:51.673965 iDelay=199, Bit 7, Center 92 (3 ~ 182) 180
5936 18:03:51.676884 iDelay=199, Bit 8, Center 80 (-13 ~ 174) 188
5937 18:03:51.683707 iDelay=199, Bit 9, Center 80 (-9 ~ 170) 180
5938 18:03:51.686992 iDelay=199, Bit 10, Center 92 (-1 ~ 186) 188
5939 18:03:51.690516 iDelay=199, Bit 11, Center 82 (-9 ~ 174) 184
5940 18:03:51.693717 iDelay=199, Bit 12, Center 98 (11 ~ 186) 176
5941 18:03:51.697033 iDelay=199, Bit 13, Center 98 (7 ~ 190) 184
5942 18:03:51.703612 iDelay=199, Bit 14, Center 96 (3 ~ 190) 188
5943 18:03:51.706776 iDelay=199, Bit 15, Center 98 (7 ~ 190) 184
5944 18:03:51.706858 ==
5945 18:03:51.710631 Dram Type= 6, Freq= 0, CH_1, rank 1
5946 18:03:51.713797 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5947 18:03:51.713879 ==
5948 18:03:51.713946 DQS Delay:
5949 18:03:51.717280 DQS0 = 0, DQS1 = 0
5950 18:03:51.717372 DQM Delay:
5951 18:03:51.720508 DQM0 = 94, DQM1 = 90
5952 18:03:51.720594 DQ Delay:
5953 18:03:51.724158 DQ0 =98, DQ1 =88, DQ2 =84, DQ3 =92
5954 18:03:51.726975 DQ4 =96, DQ5 =104, DQ6 =102, DQ7 =92
5955 18:03:51.730423 DQ8 =80, DQ9 =80, DQ10 =92, DQ11 =82
5956 18:03:51.733765 DQ12 =98, DQ13 =98, DQ14 =96, DQ15 =98
5957 18:03:51.733845
5958 18:03:51.733918
5959 18:03:51.743702 [DQSOSCAuto] RK1, (LSB)MR18= 0x811, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 419 ps
5960 18:03:51.743790 CH1 RK1: MR19=505, MR18=811
5961 18:03:51.750915 CH1_RK1: MR19=0x505, MR18=0x811, DQSOSC=416, MR23=63, INC=62, DEC=41
5962 18:03:51.753734 [RxdqsGatingPostProcess] freq 933
5963 18:03:51.760543 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5964 18:03:51.763415 best DQS0 dly(2T, 0.5T) = (0, 10)
5965 18:03:51.763497 best DQS1 dly(2T, 0.5T) = (0, 10)
5966 18:03:51.766945 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5967 18:03:51.770097 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5968 18:03:51.773762 best DQS0 dly(2T, 0.5T) = (0, 10)
5969 18:03:51.776931 best DQS1 dly(2T, 0.5T) = (0, 10)
5970 18:03:51.780142 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5971 18:03:51.783986 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5972 18:03:51.786718 Pre-setting of DQS Precalculation
5973 18:03:51.793950 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5974 18:03:51.800070 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5975 18:03:51.807035 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5976 18:03:51.807122
5977 18:03:51.807186
5978 18:03:51.810359 [Calibration Summary] 1866 Mbps
5979 18:03:51.810435 CH 0, Rank 0
5980 18:03:51.813783 SW Impedance : PASS
5981 18:03:51.817154 DUTY Scan : NO K
5982 18:03:51.817252 ZQ Calibration : PASS
5983 18:03:51.820457 Jitter Meter : NO K
5984 18:03:51.820558 CBT Training : PASS
5985 18:03:51.823775 Write leveling : PASS
5986 18:03:51.827412 RX DQS gating : PASS
5987 18:03:51.827485 RX DQ/DQS(RDDQC) : PASS
5988 18:03:51.830106 TX DQ/DQS : PASS
5989 18:03:51.833717 RX DATLAT : PASS
5990 18:03:51.833817 RX DQ/DQS(Engine): PASS
5991 18:03:51.837160 TX OE : NO K
5992 18:03:51.837257 All Pass.
5993 18:03:51.837341
5994 18:03:51.840248 CH 0, Rank 1
5995 18:03:51.840348 SW Impedance : PASS
5996 18:03:51.843734 DUTY Scan : NO K
5997 18:03:51.847050 ZQ Calibration : PASS
5998 18:03:51.847134 Jitter Meter : NO K
5999 18:03:51.850529 CBT Training : PASS
6000 18:03:51.854039 Write leveling : PASS
6001 18:03:51.854120 RX DQS gating : PASS
6002 18:03:51.857102 RX DQ/DQS(RDDQC) : PASS
6003 18:03:51.857183 TX DQ/DQS : PASS
6004 18:03:51.860405 RX DATLAT : PASS
6005 18:03:51.863791 RX DQ/DQS(Engine): PASS
6006 18:03:51.863872 TX OE : NO K
6007 18:03:51.867445 All Pass.
6008 18:03:51.867526
6009 18:03:51.867591 CH 1, Rank 0
6010 18:03:51.870275 SW Impedance : PASS
6011 18:03:51.870357 DUTY Scan : NO K
6012 18:03:51.873726 ZQ Calibration : PASS
6013 18:03:51.877248 Jitter Meter : NO K
6014 18:03:51.877346 CBT Training : PASS
6015 18:03:51.880756 Write leveling : PASS
6016 18:03:51.883995 RX DQS gating : PASS
6017 18:03:51.884077 RX DQ/DQS(RDDQC) : PASS
6018 18:03:51.887076 TX DQ/DQS : PASS
6019 18:03:51.890647 RX DATLAT : PASS
6020 18:03:51.890728 RX DQ/DQS(Engine): PASS
6021 18:03:51.893704 TX OE : NO K
6022 18:03:51.893788 All Pass.
6023 18:03:51.893853
6024 18:03:51.897138 CH 1, Rank 1
6025 18:03:51.897222 SW Impedance : PASS
6026 18:03:51.900573 DUTY Scan : NO K
6027 18:03:51.903295 ZQ Calibration : PASS
6028 18:03:51.903376 Jitter Meter : NO K
6029 18:03:51.906850 CBT Training : PASS
6030 18:03:51.910209 Write leveling : PASS
6031 18:03:51.910291 RX DQS gating : PASS
6032 18:03:51.913294 RX DQ/DQS(RDDQC) : PASS
6033 18:03:51.913375 TX DQ/DQS : PASS
6034 18:03:51.916582 RX DATLAT : PASS
6035 18:03:51.920121 RX DQ/DQS(Engine): PASS
6036 18:03:51.920237 TX OE : NO K
6037 18:03:51.923306 All Pass.
6038 18:03:51.923388
6039 18:03:51.923453 DramC Write-DBI off
6040 18:03:51.926952 PER_BANK_REFRESH: Hybrid Mode
6041 18:03:51.930372 TX_TRACKING: ON
6042 18:03:51.936664 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6043 18:03:51.940031 [FAST_K] Save calibration result to emmc
6044 18:03:51.946948 dramc_set_vcore_voltage set vcore to 650000
6045 18:03:51.947030 Read voltage for 400, 6
6046 18:03:51.947095 Vio18 = 0
6047 18:03:51.949935 Vcore = 650000
6048 18:03:51.950016 Vdram = 0
6049 18:03:51.950081 Vddq = 0
6050 18:03:51.953255 Vmddr = 0
6051 18:03:51.956556 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6052 18:03:51.963309 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6053 18:03:51.963391 MEM_TYPE=3, freq_sel=20
6054 18:03:51.966548 sv_algorithm_assistance_LP4_800
6055 18:03:51.973228 ============ PULL DRAM RESETB DOWN ============
6056 18:03:51.976766 ========== PULL DRAM RESETB DOWN end =========
6057 18:03:51.980076 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6058 18:03:51.983017 ===================================
6059 18:03:51.986455 LPDDR4 DRAM CONFIGURATION
6060 18:03:51.989943 ===================================
6061 18:03:51.993403 EX_ROW_EN[0] = 0x0
6062 18:03:51.993484 EX_ROW_EN[1] = 0x0
6063 18:03:51.996668 LP4Y_EN = 0x0
6064 18:03:51.996750 WORK_FSP = 0x0
6065 18:03:52.000201 WL = 0x2
6066 18:03:52.000282 RL = 0x2
6067 18:03:52.003177 BL = 0x2
6068 18:03:52.003259 RPST = 0x0
6069 18:03:52.006916 RD_PRE = 0x0
6070 18:03:52.006998 WR_PRE = 0x1
6071 18:03:52.009881 WR_PST = 0x0
6072 18:03:52.009965 DBI_WR = 0x0
6073 18:03:52.013108 DBI_RD = 0x0
6074 18:03:52.013186 OTF = 0x1
6075 18:03:52.017093 ===================================
6076 18:03:52.019856 ===================================
6077 18:03:52.023167 ANA top config
6078 18:03:52.026498 ===================================
6079 18:03:52.026579 DLL_ASYNC_EN = 0
6080 18:03:52.030090 ALL_SLAVE_EN = 1
6081 18:03:52.033471 NEW_RANK_MODE = 1
6082 18:03:52.036699 DLL_IDLE_MODE = 1
6083 18:03:52.040217 LP45_APHY_COMB_EN = 1
6084 18:03:52.040298 TX_ODT_DIS = 1
6085 18:03:52.043197 NEW_8X_MODE = 1
6086 18:03:52.046695 ===================================
6087 18:03:52.050170 ===================================
6088 18:03:52.053428 data_rate = 800
6089 18:03:52.056862 CKR = 1
6090 18:03:52.059755 DQ_P2S_RATIO = 4
6091 18:03:52.063424 ===================================
6092 18:03:52.063499 CA_P2S_RATIO = 4
6093 18:03:52.066830 DQ_CA_OPEN = 0
6094 18:03:52.070075 DQ_SEMI_OPEN = 1
6095 18:03:52.073351 CA_SEMI_OPEN = 1
6096 18:03:52.076703 CA_FULL_RATE = 0
6097 18:03:52.080054 DQ_CKDIV4_EN = 0
6098 18:03:52.080136 CA_CKDIV4_EN = 1
6099 18:03:52.083814 CA_PREDIV_EN = 0
6100 18:03:52.086549 PH8_DLY = 0
6101 18:03:52.089950 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6102 18:03:52.093424 DQ_AAMCK_DIV = 0
6103 18:03:52.093504 CA_AAMCK_DIV = 0
6104 18:03:52.096834 CA_ADMCK_DIV = 4
6105 18:03:52.099762 DQ_TRACK_CA_EN = 0
6106 18:03:52.103507 CA_PICK = 800
6107 18:03:52.106319 CA_MCKIO = 400
6108 18:03:52.109724 MCKIO_SEMI = 400
6109 18:03:52.113201 PLL_FREQ = 3016
6110 18:03:52.116582 DQ_UI_PI_RATIO = 32
6111 18:03:52.116660 CA_UI_PI_RATIO = 32
6112 18:03:52.119723 ===================================
6113 18:03:52.123090 ===================================
6114 18:03:52.126406 memory_type:LPDDR4
6115 18:03:52.130216 GP_NUM : 10
6116 18:03:52.130328 SRAM_EN : 1
6117 18:03:52.133727 MD32_EN : 0
6118 18:03:52.136348 ===================================
6119 18:03:52.140129 [ANA_INIT] >>>>>>>>>>>>>>
6120 18:03:52.143219 <<<<<< [CONFIGURE PHASE]: ANA_TX
6121 18:03:52.146642 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6122 18:03:52.149866 ===================================
6123 18:03:52.149972 data_rate = 800,PCW = 0X7400
6124 18:03:52.153457 ===================================
6125 18:03:52.156833 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6126 18:03:52.163248 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6127 18:03:52.173549 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6128 18:03:52.180318 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6129 18:03:52.183696 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6130 18:03:52.186868 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6131 18:03:52.186963 [ANA_INIT] flow start
6132 18:03:52.189930 [ANA_INIT] PLL >>>>>>>>
6133 18:03:52.193167 [ANA_INIT] PLL <<<<<<<<
6134 18:03:52.196370 [ANA_INIT] MIDPI >>>>>>>>
6135 18:03:52.196480 [ANA_INIT] MIDPI <<<<<<<<
6136 18:03:52.199960 [ANA_INIT] DLL >>>>>>>>
6137 18:03:52.203251 [ANA_INIT] flow end
6138 18:03:52.206757 ============ LP4 DIFF to SE enter ============
6139 18:03:52.209804 ============ LP4 DIFF to SE exit ============
6140 18:03:52.213106 [ANA_INIT] <<<<<<<<<<<<<
6141 18:03:52.216460 [Flow] Enable top DCM control >>>>>
6142 18:03:52.220107 [Flow] Enable top DCM control <<<<<
6143 18:03:52.223643 Enable DLL master slave shuffle
6144 18:03:52.226488 ==============================================================
6145 18:03:52.229583 Gating Mode config
6146 18:03:52.233012 ==============================================================
6147 18:03:52.236304 Config description:
6148 18:03:52.246629 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6149 18:03:52.253232 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6150 18:03:52.256507 SELPH_MODE 0: By rank 1: By Phase
6151 18:03:52.263136 ==============================================================
6152 18:03:52.266433 GAT_TRACK_EN = 0
6153 18:03:52.269781 RX_GATING_MODE = 2
6154 18:03:52.273308 RX_GATING_TRACK_MODE = 2
6155 18:03:52.276328 SELPH_MODE = 1
6156 18:03:52.276424 PICG_EARLY_EN = 1
6157 18:03:52.279726 VALID_LAT_VALUE = 1
6158 18:03:52.286411 ==============================================================
6159 18:03:52.289830 Enter into Gating configuration >>>>
6160 18:03:52.292882 Exit from Gating configuration <<<<
6161 18:03:52.296620 Enter into DVFS_PRE_config >>>>>
6162 18:03:52.306288 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6163 18:03:52.309823 Exit from DVFS_PRE_config <<<<<
6164 18:03:52.313101 Enter into PICG configuration >>>>
6165 18:03:52.316735 Exit from PICG configuration <<<<
6166 18:03:52.320159 [RX_INPUT] configuration >>>>>
6167 18:03:52.323073 [RX_INPUT] configuration <<<<<
6168 18:03:52.326645 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6169 18:03:52.333359 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6170 18:03:52.339957 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6171 18:03:52.346667 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6172 18:03:52.353296 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6173 18:03:52.356566 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6174 18:03:52.363155 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6175 18:03:52.366347 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6176 18:03:52.369877 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6177 18:03:52.373051 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6178 18:03:52.376859 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6179 18:03:52.382989 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6180 18:03:52.386578 ===================================
6181 18:03:52.389981 LPDDR4 DRAM CONFIGURATION
6182 18:03:52.392839 ===================================
6183 18:03:52.392920 EX_ROW_EN[0] = 0x0
6184 18:03:52.396363 EX_ROW_EN[1] = 0x0
6185 18:03:52.396444 LP4Y_EN = 0x0
6186 18:03:52.400019 WORK_FSP = 0x0
6187 18:03:52.400099 WL = 0x2
6188 18:03:52.403413 RL = 0x2
6189 18:03:52.403493 BL = 0x2
6190 18:03:52.406261 RPST = 0x0
6191 18:03:52.406341 RD_PRE = 0x0
6192 18:03:52.409654 WR_PRE = 0x1
6193 18:03:52.409735 WR_PST = 0x0
6194 18:03:52.413282 DBI_WR = 0x0
6195 18:03:52.413363 DBI_RD = 0x0
6196 18:03:52.416536 OTF = 0x1
6197 18:03:52.419828 ===================================
6198 18:03:52.423212 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6199 18:03:52.426701 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6200 18:03:52.433081 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6201 18:03:52.436352 ===================================
6202 18:03:52.436471 LPDDR4 DRAM CONFIGURATION
6203 18:03:52.439293 ===================================
6204 18:03:52.442896 EX_ROW_EN[0] = 0x10
6205 18:03:52.446452 EX_ROW_EN[1] = 0x0
6206 18:03:52.446535 LP4Y_EN = 0x0
6207 18:03:52.449443 WORK_FSP = 0x0
6208 18:03:52.449523 WL = 0x2
6209 18:03:52.453279 RL = 0x2
6210 18:03:52.453359 BL = 0x2
6211 18:03:52.456695 RPST = 0x0
6212 18:03:52.456801 RD_PRE = 0x0
6213 18:03:52.459553 WR_PRE = 0x1
6214 18:03:52.459634 WR_PST = 0x0
6215 18:03:52.463075 DBI_WR = 0x0
6216 18:03:52.463178 DBI_RD = 0x0
6217 18:03:52.466773 OTF = 0x1
6218 18:03:52.469816 ===================================
6219 18:03:52.476139 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6220 18:03:52.479675 nWR fixed to 30
6221 18:03:52.479774 [ModeRegInit_LP4] CH0 RK0
6222 18:03:52.483291 [ModeRegInit_LP4] CH0 RK1
6223 18:03:52.486367 [ModeRegInit_LP4] CH1 RK0
6224 18:03:52.489759 [ModeRegInit_LP4] CH1 RK1
6225 18:03:52.489841 match AC timing 19
6226 18:03:52.493244 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6227 18:03:52.496820 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6228 18:03:52.503138 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6229 18:03:52.506593 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6230 18:03:52.513179 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6231 18:03:52.513265 ==
6232 18:03:52.516458 Dram Type= 6, Freq= 0, CH_0, rank 0
6233 18:03:52.520068 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6234 18:03:52.520151 ==
6235 18:03:52.526873 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6236 18:03:52.530192 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6237 18:03:52.533239 [CA 0] Center 36 (8~64) winsize 57
6238 18:03:52.536583 [CA 1] Center 36 (8~64) winsize 57
6239 18:03:52.539831 [CA 2] Center 36 (8~64) winsize 57
6240 18:03:52.543403 [CA 3] Center 36 (8~64) winsize 57
6241 18:03:52.546708 [CA 4] Center 36 (8~64) winsize 57
6242 18:03:52.549927 [CA 5] Center 36 (8~64) winsize 57
6243 18:03:52.550124
6244 18:03:52.553698 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6245 18:03:52.553779
6246 18:03:52.556760 [CATrainingPosCal] consider 1 rank data
6247 18:03:52.559909 u2DelayCellTimex100 = 270/100 ps
6248 18:03:52.563038 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6249 18:03:52.566455 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6250 18:03:52.569531 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6251 18:03:52.576555 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6252 18:03:52.579693 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6253 18:03:52.583207 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6254 18:03:52.583291
6255 18:03:52.586380 CA PerBit enable=1, Macro0, CA PI delay=36
6256 18:03:52.586461
6257 18:03:52.589957 [CBTSetCACLKResult] CA Dly = 36
6258 18:03:52.590038 CS Dly: 1 (0~32)
6259 18:03:52.590102 ==
6260 18:03:52.593222 Dram Type= 6, Freq= 0, CH_0, rank 1
6261 18:03:52.600043 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6262 18:03:52.600134 ==
6263 18:03:52.603317 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6264 18:03:52.610099 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6265 18:03:52.613114 [CA 0] Center 36 (8~64) winsize 57
6266 18:03:52.616458 [CA 1] Center 36 (8~64) winsize 57
6267 18:03:52.620073 [CA 2] Center 36 (8~64) winsize 57
6268 18:03:52.623339 [CA 3] Center 36 (8~64) winsize 57
6269 18:03:52.626752 [CA 4] Center 36 (8~64) winsize 57
6270 18:03:52.630332 [CA 5] Center 36 (8~64) winsize 57
6271 18:03:52.630412
6272 18:03:52.633227 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6273 18:03:52.633308
6274 18:03:52.636905 [CATrainingPosCal] consider 2 rank data
6275 18:03:52.640390 u2DelayCellTimex100 = 270/100 ps
6276 18:03:52.643396 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6277 18:03:52.646937 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6278 18:03:52.650040 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6279 18:03:52.653158 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6280 18:03:52.656601 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6281 18:03:52.659886 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6282 18:03:52.659969
6283 18:03:52.663546 CA PerBit enable=1, Macro0, CA PI delay=36
6284 18:03:52.663627
6285 18:03:52.666897 [CBTSetCACLKResult] CA Dly = 36
6286 18:03:52.670480 CS Dly: 1 (0~32)
6287 18:03:52.670561
6288 18:03:52.673262 ----->DramcWriteLeveling(PI) begin...
6289 18:03:52.673352 ==
6290 18:03:52.677090 Dram Type= 6, Freq= 0, CH_0, rank 0
6291 18:03:52.680229 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6292 18:03:52.680355 ==
6293 18:03:52.683758 Write leveling (Byte 0): 40 => 8
6294 18:03:52.686840 Write leveling (Byte 1): 32 => 0
6295 18:03:52.690137 DramcWriteLeveling(PI) end<-----
6296 18:03:52.690233
6297 18:03:52.690296 ==
6298 18:03:52.693814 Dram Type= 6, Freq= 0, CH_0, rank 0
6299 18:03:52.696863 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6300 18:03:52.696944 ==
6301 18:03:52.700231 [Gating] SW mode calibration
6302 18:03:52.706715 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6303 18:03:52.713665 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6304 18:03:52.716919 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6305 18:03:52.720271 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6306 18:03:52.727283 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6307 18:03:52.730207 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6308 18:03:52.733778 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6309 18:03:52.740543 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6310 18:03:52.744146 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6311 18:03:52.746937 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6312 18:03:52.753704 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6313 18:03:52.753788 Total UI for P1: 0, mck2ui 16
6314 18:03:52.760082 best dqsien dly found for B0: ( 0, 14, 24)
6315 18:03:52.760192 Total UI for P1: 0, mck2ui 16
6316 18:03:52.766909 best dqsien dly found for B1: ( 0, 14, 24)
6317 18:03:52.770236 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6318 18:03:52.773586 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6319 18:03:52.773663
6320 18:03:52.777090 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6321 18:03:52.779943 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6322 18:03:52.783780 [Gating] SW calibration Done
6323 18:03:52.783879 ==
6324 18:03:52.787124 Dram Type= 6, Freq= 0, CH_0, rank 0
6325 18:03:52.790121 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6326 18:03:52.790195 ==
6327 18:03:52.793523 RX Vref Scan: 0
6328 18:03:52.793621
6329 18:03:52.793710 RX Vref 0 -> 0, step: 1
6330 18:03:52.793796
6331 18:03:52.797112 RX Delay -410 -> 252, step: 16
6332 18:03:52.803291 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6333 18:03:52.806454 iDelay=230, Bit 1, Center -27 (-282 ~ 229) 512
6334 18:03:52.810343 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6335 18:03:52.813196 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6336 18:03:52.820205 iDelay=230, Bit 4, Center -19 (-266 ~ 229) 496
6337 18:03:52.823172 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6338 18:03:52.826624 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6339 18:03:52.829839 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6340 18:03:52.836725 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6341 18:03:52.839760 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6342 18:03:52.843165 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6343 18:03:52.846410 iDelay=230, Bit 11, Center -43 (-282 ~ 197) 480
6344 18:03:52.853054 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6345 18:03:52.856621 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6346 18:03:52.860015 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6347 18:03:52.862927 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6348 18:03:52.866187 ==
6349 18:03:52.869596 Dram Type= 6, Freq= 0, CH_0, rank 0
6350 18:03:52.873264 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6351 18:03:52.873365 ==
6352 18:03:52.873438 DQS Delay:
6353 18:03:52.876245 DQS0 = 35, DQS1 = 51
6354 18:03:52.876316 DQM Delay:
6355 18:03:52.879632 DQM0 = 8, DQM1 = 11
6356 18:03:52.879737 DQ Delay:
6357 18:03:52.883345 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =0
6358 18:03:52.886992 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6359 18:03:52.887064 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6360 18:03:52.892933 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6361 18:03:52.893050
6362 18:03:52.893114
6363 18:03:52.893173 ==
6364 18:03:52.896349 Dram Type= 6, Freq= 0, CH_0, rank 0
6365 18:03:52.899878 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6366 18:03:52.899961 ==
6367 18:03:52.900025
6368 18:03:52.900083
6369 18:03:52.903130 TX Vref Scan disable
6370 18:03:52.903210 == TX Byte 0 ==
6371 18:03:52.906470 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6372 18:03:52.913225 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6373 18:03:52.913311 == TX Byte 1 ==
6374 18:03:52.916544 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6375 18:03:52.923365 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6376 18:03:52.923449 ==
6377 18:03:52.926749 Dram Type= 6, Freq= 0, CH_0, rank 0
6378 18:03:52.929773 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6379 18:03:52.929856 ==
6380 18:03:52.929920
6381 18:03:52.929979
6382 18:03:52.933298 TX Vref Scan disable
6383 18:03:52.933379 == TX Byte 0 ==
6384 18:03:52.939997 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6385 18:03:52.943406 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6386 18:03:52.943489 == TX Byte 1 ==
6387 18:03:52.946944 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6388 18:03:52.953405 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6389 18:03:52.953488
6390 18:03:52.953551 [DATLAT]
6391 18:03:52.956568 Freq=400, CH0 RK0
6392 18:03:52.956649
6393 18:03:52.956713 DATLAT Default: 0xf
6394 18:03:52.959960 0, 0xFFFF, sum = 0
6395 18:03:52.960043 1, 0xFFFF, sum = 0
6396 18:03:52.963424 2, 0xFFFF, sum = 0
6397 18:03:52.963506 3, 0xFFFF, sum = 0
6398 18:03:52.966797 4, 0xFFFF, sum = 0
6399 18:03:52.966906 5, 0xFFFF, sum = 0
6400 18:03:52.970064 6, 0xFFFF, sum = 0
6401 18:03:52.970164 7, 0xFFFF, sum = 0
6402 18:03:52.973643 8, 0xFFFF, sum = 0
6403 18:03:52.973725 9, 0xFFFF, sum = 0
6404 18:03:52.977082 10, 0xFFFF, sum = 0
6405 18:03:52.977164 11, 0xFFFF, sum = 0
6406 18:03:52.980003 12, 0xFFFF, sum = 0
6407 18:03:52.980085 13, 0x0, sum = 1
6408 18:03:52.983290 14, 0x0, sum = 2
6409 18:03:52.983374 15, 0x0, sum = 3
6410 18:03:52.986957 16, 0x0, sum = 4
6411 18:03:52.987032 best_step = 14
6412 18:03:52.987093
6413 18:03:52.987151 ==
6414 18:03:52.989984 Dram Type= 6, Freq= 0, CH_0, rank 0
6415 18:03:52.996826 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6416 18:03:52.996935 ==
6417 18:03:52.997049 RX Vref Scan: 1
6418 18:03:52.997111
6419 18:03:52.999806 RX Vref 0 -> 0, step: 1
6420 18:03:52.999880
6421 18:03:53.003468 RX Delay -343 -> 252, step: 8
6422 18:03:53.003550
6423 18:03:53.006724 Set Vref, RX VrefLevel [Byte0]: 53
6424 18:03:53.010022 [Byte1]: 51
6425 18:03:53.010103
6426 18:03:53.013393 Final RX Vref Byte 0 = 53 to rank0
6427 18:03:53.016432 Final RX Vref Byte 1 = 51 to rank0
6428 18:03:53.020259 Final RX Vref Byte 0 = 53 to rank1
6429 18:03:53.023538 Final RX Vref Byte 1 = 51 to rank1==
6430 18:03:53.026511 Dram Type= 6, Freq= 0, CH_0, rank 0
6431 18:03:53.029963 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6432 18:03:53.033467 ==
6433 18:03:53.033548 DQS Delay:
6434 18:03:53.033612 DQS0 = 44, DQS1 = 60
6435 18:03:53.036566 DQM Delay:
6436 18:03:53.036647 DQM0 = 11, DQM1 = 14
6437 18:03:53.039774 DQ Delay:
6438 18:03:53.039881 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8
6439 18:03:53.043436 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6440 18:03:53.046257 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =8
6441 18:03:53.050096 DQ12 =24, DQ13 =20, DQ14 =28, DQ15 =24
6442 18:03:53.050177
6443 18:03:53.050241
6444 18:03:53.059474 [DQSOSCAuto] RK0, (LSB)MR18= 0x7d4c, (MSB)MR19= 0xc0c, tDQSOscB0 = 400 ps tDQSOscB1 = 394 ps
6445 18:03:53.062899 CH0 RK0: MR19=C0C, MR18=7D4C
6446 18:03:53.069552 CH0_RK0: MR19=0xC0C, MR18=0x7D4C, DQSOSC=394, MR23=63, INC=380, DEC=253
6447 18:03:53.069636 ==
6448 18:03:53.072939 Dram Type= 6, Freq= 0, CH_0, rank 1
6449 18:03:53.076396 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6450 18:03:53.076478 ==
6451 18:03:53.079943 [Gating] SW mode calibration
6452 18:03:53.086256 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6453 18:03:53.089725 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6454 18:03:53.096585 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6455 18:03:53.099603 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6456 18:03:53.102890 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6457 18:03:53.109757 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6458 18:03:53.112877 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6459 18:03:53.116039 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6460 18:03:53.122886 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6461 18:03:53.126181 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6462 18:03:53.129547 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6463 18:03:53.133226 Total UI for P1: 0, mck2ui 16
6464 18:03:53.136111 best dqsien dly found for B0: ( 0, 14, 24)
6465 18:03:53.139818 Total UI for P1: 0, mck2ui 16
6466 18:03:53.142681 best dqsien dly found for B1: ( 0, 14, 24)
6467 18:03:53.146033 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6468 18:03:53.149461 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6469 18:03:53.149541
6470 18:03:53.156509 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6471 18:03:53.159365 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6472 18:03:53.159445 [Gating] SW calibration Done
6473 18:03:53.163102 ==
6474 18:03:53.166364 Dram Type= 6, Freq= 0, CH_0, rank 1
6475 18:03:53.169594 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6476 18:03:53.169670 ==
6477 18:03:53.169731 RX Vref Scan: 0
6478 18:03:53.169796
6479 18:03:53.173292 RX Vref 0 -> 0, step: 1
6480 18:03:53.173364
6481 18:03:53.176066 RX Delay -410 -> 252, step: 16
6482 18:03:53.179641 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6483 18:03:53.182879 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6484 18:03:53.189837 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6485 18:03:53.193239 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6486 18:03:53.196167 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6487 18:03:53.199466 iDelay=230, Bit 5, Center -43 (-282 ~ 197) 480
6488 18:03:53.206187 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6489 18:03:53.210113 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6490 18:03:53.212832 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6491 18:03:53.216317 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6492 18:03:53.223152 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6493 18:03:53.226264 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6494 18:03:53.229930 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6495 18:03:53.233249 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6496 18:03:53.239675 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6497 18:03:53.242989 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6498 18:03:53.243068 ==
6499 18:03:53.246525 Dram Type= 6, Freq= 0, CH_0, rank 1
6500 18:03:53.249670 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6501 18:03:53.249743 ==
6502 18:03:53.253336 DQS Delay:
6503 18:03:53.253424 DQS0 = 43, DQS1 = 51
6504 18:03:53.256746 DQM Delay:
6505 18:03:53.256865 DQM0 = 11, DQM1 = 10
6506 18:03:53.256971 DQ Delay:
6507 18:03:53.259589 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6508 18:03:53.263241 DQ4 =8, DQ5 =0, DQ6 =24, DQ7 =24
6509 18:03:53.266385 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6510 18:03:53.269857 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6511 18:03:53.269937
6512 18:03:53.270002
6513 18:03:53.270061 ==
6514 18:03:53.273456 Dram Type= 6, Freq= 0, CH_0, rank 1
6515 18:03:53.276784 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6516 18:03:53.279480 ==
6517 18:03:53.279559
6518 18:03:53.279622
6519 18:03:53.279696 TX Vref Scan disable
6520 18:03:53.282697 == TX Byte 0 ==
6521 18:03:53.286470 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6522 18:03:53.289460 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6523 18:03:53.292832 == TX Byte 1 ==
6524 18:03:53.296613 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6525 18:03:53.299503 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6526 18:03:53.299585 ==
6527 18:03:53.302950 Dram Type= 6, Freq= 0, CH_0, rank 1
6528 18:03:53.305845 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6529 18:03:53.309413 ==
6530 18:03:53.309493
6531 18:03:53.309556
6532 18:03:53.309616 TX Vref Scan disable
6533 18:03:53.312848 == TX Byte 0 ==
6534 18:03:53.315913 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6535 18:03:53.319919 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6536 18:03:53.322872 == TX Byte 1 ==
6537 18:03:53.326105 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6538 18:03:53.329356 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6539 18:03:53.329465
6540 18:03:53.329551 [DATLAT]
6541 18:03:53.332784 Freq=400, CH0 RK1
6542 18:03:53.332856
6543 18:03:53.336357 DATLAT Default: 0xe
6544 18:03:53.336437 0, 0xFFFF, sum = 0
6545 18:03:53.339259 1, 0xFFFF, sum = 0
6546 18:03:53.339336 2, 0xFFFF, sum = 0
6547 18:03:53.342925 3, 0xFFFF, sum = 0
6548 18:03:53.342997 4, 0xFFFF, sum = 0
6549 18:03:53.346124 5, 0xFFFF, sum = 0
6550 18:03:53.346196 6, 0xFFFF, sum = 0
6551 18:03:53.349437 7, 0xFFFF, sum = 0
6552 18:03:53.349526 8, 0xFFFF, sum = 0
6553 18:03:53.353401 9, 0xFFFF, sum = 0
6554 18:03:53.353477 10, 0xFFFF, sum = 0
6555 18:03:53.356525 11, 0xFFFF, sum = 0
6556 18:03:53.356624 12, 0xFFFF, sum = 0
6557 18:03:53.359587 13, 0x0, sum = 1
6558 18:03:53.359660 14, 0x0, sum = 2
6559 18:03:53.362824 15, 0x0, sum = 3
6560 18:03:53.362900 16, 0x0, sum = 4
6561 18:03:53.366129 best_step = 14
6562 18:03:53.366199
6563 18:03:53.366263 ==
6564 18:03:53.369899 Dram Type= 6, Freq= 0, CH_0, rank 1
6565 18:03:53.373007 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6566 18:03:53.373092 ==
6567 18:03:53.376051 RX Vref Scan: 0
6568 18:03:53.376128
6569 18:03:53.376205 RX Vref 0 -> 0, step: 1
6570 18:03:53.376266
6571 18:03:53.379426 RX Delay -343 -> 252, step: 8
6572 18:03:53.387054 iDelay=217, Bit 0, Center -32 (-271 ~ 208) 480
6573 18:03:53.390506 iDelay=217, Bit 1, Center -32 (-271 ~ 208) 480
6574 18:03:53.393710 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6575 18:03:53.396934 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6576 18:03:53.403752 iDelay=217, Bit 4, Center -36 (-271 ~ 200) 472
6577 18:03:53.407419 iDelay=217, Bit 5, Center -48 (-287 ~ 192) 480
6578 18:03:53.410465 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6579 18:03:53.413718 iDelay=217, Bit 7, Center -32 (-271 ~ 208) 480
6580 18:03:53.420591 iDelay=217, Bit 8, Center -56 (-295 ~ 184) 480
6581 18:03:53.424044 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6582 18:03:53.427294 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6583 18:03:53.430830 iDelay=217, Bit 11, Center -56 (-295 ~ 184) 480
6584 18:03:53.437135 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6585 18:03:53.440403 iDelay=217, Bit 13, Center -40 (-279 ~ 200) 480
6586 18:03:53.444004 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6587 18:03:53.447349 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6588 18:03:53.450415 ==
6589 18:03:53.453915 Dram Type= 6, Freq= 0, CH_0, rank 1
6590 18:03:53.457767 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6591 18:03:53.457848 ==
6592 18:03:53.457913 DQS Delay:
6593 18:03:53.460631 DQS0 = 48, DQS1 = 60
6594 18:03:53.460710 DQM Delay:
6595 18:03:53.464057 DQM0 = 12, DQM1 = 13
6596 18:03:53.464136 DQ Delay:
6597 18:03:53.467939 DQ0 =16, DQ1 =16, DQ2 =8, DQ3 =12
6598 18:03:53.470538 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6599 18:03:53.474303 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =4
6600 18:03:53.477661 DQ12 =16, DQ13 =20, DQ14 =24, DQ15 =24
6601 18:03:53.477741
6602 18:03:53.477805
6603 18:03:53.484125 [DQSOSCAuto] RK1, (LSB)MR18= 0x8c5e, (MSB)MR19= 0xc0c, tDQSOscB0 = 397 ps tDQSOscB1 = 392 ps
6604 18:03:53.487421 CH0 RK1: MR19=C0C, MR18=8C5E
6605 18:03:53.494374 CH0_RK1: MR19=0xC0C, MR18=0x8C5E, DQSOSC=392, MR23=63, INC=384, DEC=256
6606 18:03:53.497299 [RxdqsGatingPostProcess] freq 400
6607 18:03:53.500707 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6608 18:03:53.504043 best DQS0 dly(2T, 0.5T) = (0, 10)
6609 18:03:53.507298 best DQS1 dly(2T, 0.5T) = (0, 10)
6610 18:03:53.510611 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6611 18:03:53.514325 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6612 18:03:53.517530 best DQS0 dly(2T, 0.5T) = (0, 10)
6613 18:03:53.521157 best DQS1 dly(2T, 0.5T) = (0, 10)
6614 18:03:53.523905 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6615 18:03:53.527397 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6616 18:03:53.530754 Pre-setting of DQS Precalculation
6617 18:03:53.534087 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6618 18:03:53.534167 ==
6619 18:03:53.537504 Dram Type= 6, Freq= 0, CH_1, rank 0
6620 18:03:53.544398 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6621 18:03:53.544479 ==
6622 18:03:53.547191 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6623 18:03:53.553793 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6624 18:03:53.557585 [CA 0] Center 36 (8~64) winsize 57
6625 18:03:53.560700 [CA 1] Center 36 (8~64) winsize 57
6626 18:03:53.564211 [CA 2] Center 36 (8~64) winsize 57
6627 18:03:53.567736 [CA 3] Center 36 (8~64) winsize 57
6628 18:03:53.570595 [CA 4] Center 36 (8~64) winsize 57
6629 18:03:53.573953 [CA 5] Center 36 (8~64) winsize 57
6630 18:03:53.574059
6631 18:03:53.577681 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6632 18:03:53.577761
6633 18:03:53.580403 [CATrainingPosCal] consider 1 rank data
6634 18:03:53.584105 u2DelayCellTimex100 = 270/100 ps
6635 18:03:53.587001 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6636 18:03:53.590859 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6637 18:03:53.594117 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6638 18:03:53.597179 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6639 18:03:53.600629 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6640 18:03:53.604072 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6641 18:03:53.607148
6642 18:03:53.610488 CA PerBit enable=1, Macro0, CA PI delay=36
6643 18:03:53.610567
6644 18:03:53.616717 [CBTSetCACLKResult] CA Dly = 36
6645 18:03:53.616822 CS Dly: 1 (0~32)
6646 18:03:53.616918 ==
6647 18:03:53.617233 Dram Type= 6, Freq= 0, CH_1, rank 1
6648 18:03:53.620431 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6649 18:03:53.620512 ==
6650 18:03:53.626917 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6651 18:03:53.634123 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6652 18:03:53.636824 [CA 0] Center 36 (8~64) winsize 57
6653 18:03:53.640848 [CA 1] Center 36 (8~64) winsize 57
6654 18:03:53.644117 [CA 2] Center 36 (8~64) winsize 57
6655 18:03:53.647052 [CA 3] Center 36 (8~64) winsize 57
6656 18:03:53.647133 [CA 4] Center 36 (8~64) winsize 57
6657 18:03:53.650531 [CA 5] Center 36 (8~64) winsize 57
6658 18:03:53.650623
6659 18:03:53.657284 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6660 18:03:53.657366
6661 18:03:53.660568 [CATrainingPosCal] consider 2 rank data
6662 18:03:53.663650 u2DelayCellTimex100 = 270/100 ps
6663 18:03:53.666882 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6664 18:03:53.670350 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6665 18:03:53.673312 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6666 18:03:53.676851 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6667 18:03:53.680295 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6668 18:03:53.683584 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6669 18:03:53.683665
6670 18:03:53.686598 CA PerBit enable=1, Macro0, CA PI delay=36
6671 18:03:53.686677
6672 18:03:53.690141 [CBTSetCACLKResult] CA Dly = 36
6673 18:03:53.693545 CS Dly: 1 (0~32)
6674 18:03:53.693650
6675 18:03:53.696810 ----->DramcWriteLeveling(PI) begin...
6676 18:03:53.696888 ==
6677 18:03:53.700189 Dram Type= 6, Freq= 0, CH_1, rank 0
6678 18:03:53.703190 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6679 18:03:53.703277 ==
6680 18:03:53.706736 Write leveling (Byte 0): 40 => 8
6681 18:03:53.710259 Write leveling (Byte 1): 40 => 8
6682 18:03:53.713854 DramcWriteLeveling(PI) end<-----
6683 18:03:53.713927
6684 18:03:53.713988 ==
6685 18:03:53.716719 Dram Type= 6, Freq= 0, CH_1, rank 0
6686 18:03:53.720129 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6687 18:03:53.720210 ==
6688 18:03:53.723564 [Gating] SW mode calibration
6689 18:03:53.729896 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6690 18:03:53.736922 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6691 18:03:53.740041 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6692 18:03:53.743387 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6693 18:03:53.750075 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6694 18:03:53.753527 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6695 18:03:53.757178 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6696 18:03:53.763903 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6697 18:03:53.767149 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6698 18:03:53.770269 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6699 18:03:53.776907 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6700 18:03:53.777021 Total UI for P1: 0, mck2ui 16
6701 18:03:53.783680 best dqsien dly found for B0: ( 0, 14, 24)
6702 18:03:53.783767 Total UI for P1: 0, mck2ui 16
6703 18:03:53.790273 best dqsien dly found for B1: ( 0, 14, 24)
6704 18:03:53.793837 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6705 18:03:53.796754 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6706 18:03:53.796834
6707 18:03:53.800086 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6708 18:03:53.803169 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6709 18:03:53.806511 [Gating] SW calibration Done
6710 18:03:53.806592 ==
6711 18:03:53.810326 Dram Type= 6, Freq= 0, CH_1, rank 0
6712 18:03:53.813435 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6713 18:03:53.813519 ==
6714 18:03:53.816874 RX Vref Scan: 0
6715 18:03:53.816986
6716 18:03:53.817098 RX Vref 0 -> 0, step: 1
6717 18:03:53.817176
6718 18:03:53.820445 RX Delay -410 -> 252, step: 16
6719 18:03:53.827021 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6720 18:03:53.829883 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6721 18:03:53.833574 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6722 18:03:53.836951 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6723 18:03:53.843329 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6724 18:03:53.846576 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6725 18:03:53.850144 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6726 18:03:53.853078 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6727 18:03:53.856573 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6728 18:03:53.863442 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6729 18:03:53.866835 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6730 18:03:53.870463 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6731 18:03:53.876964 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6732 18:03:53.879855 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6733 18:03:53.883312 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6734 18:03:53.886929 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6735 18:03:53.887010 ==
6736 18:03:53.889993 Dram Type= 6, Freq= 0, CH_1, rank 0
6737 18:03:53.896857 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6738 18:03:53.896944 ==
6739 18:03:53.897049 DQS Delay:
6740 18:03:53.900317 DQS0 = 51, DQS1 = 59
6741 18:03:53.900398 DQM Delay:
6742 18:03:53.900467 DQM0 = 19, DQM1 = 16
6743 18:03:53.903561 DQ Delay:
6744 18:03:53.906476 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6745 18:03:53.910216 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6746 18:03:53.913434 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6747 18:03:53.916656 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6748 18:03:53.916757
6749 18:03:53.916847
6750 18:03:53.916933 ==
6751 18:03:53.919819 Dram Type= 6, Freq= 0, CH_1, rank 0
6752 18:03:53.923253 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6753 18:03:53.923327 ==
6754 18:03:53.923388
6755 18:03:53.923445
6756 18:03:53.926931 TX Vref Scan disable
6757 18:03:53.927010 == TX Byte 0 ==
6758 18:03:53.933389 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6759 18:03:53.936796 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6760 18:03:53.936877 == TX Byte 1 ==
6761 18:03:53.940162 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6762 18:03:53.947101 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6763 18:03:53.947182 ==
6764 18:03:53.949909 Dram Type= 6, Freq= 0, CH_1, rank 0
6765 18:03:53.953313 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6766 18:03:53.953393 ==
6767 18:03:53.953456
6768 18:03:53.953515
6769 18:03:53.956622 TX Vref Scan disable
6770 18:03:53.956727 == TX Byte 0 ==
6771 18:03:53.960203 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6772 18:03:53.966603 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6773 18:03:53.966684 == TX Byte 1 ==
6774 18:03:53.969976 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6775 18:03:53.976513 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6776 18:03:53.976595
6777 18:03:53.976658 [DATLAT]
6778 18:03:53.976718 Freq=400, CH1 RK0
6779 18:03:53.980079
6780 18:03:53.980158 DATLAT Default: 0xf
6781 18:03:53.983339 0, 0xFFFF, sum = 0
6782 18:03:53.983425 1, 0xFFFF, sum = 0
6783 18:03:53.986830 2, 0xFFFF, sum = 0
6784 18:03:53.986911 3, 0xFFFF, sum = 0
6785 18:03:53.990576 4, 0xFFFF, sum = 0
6786 18:03:53.990682 5, 0xFFFF, sum = 0
6787 18:03:53.993170 6, 0xFFFF, sum = 0
6788 18:03:53.993251 7, 0xFFFF, sum = 0
6789 18:03:53.996739 8, 0xFFFF, sum = 0
6790 18:03:53.996821 9, 0xFFFF, sum = 0
6791 18:03:54.000011 10, 0xFFFF, sum = 0
6792 18:03:54.000094 11, 0xFFFF, sum = 0
6793 18:03:54.003498 12, 0xFFFF, sum = 0
6794 18:03:54.003573 13, 0x0, sum = 1
6795 18:03:54.006576 14, 0x0, sum = 2
6796 18:03:54.006657 15, 0x0, sum = 3
6797 18:03:54.009870 16, 0x0, sum = 4
6798 18:03:54.009951 best_step = 14
6799 18:03:54.010013
6800 18:03:54.010072 ==
6801 18:03:54.013106 Dram Type= 6, Freq= 0, CH_1, rank 0
6802 18:03:54.019600 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6803 18:03:54.019705 ==
6804 18:03:54.019775 RX Vref Scan: 1
6805 18:03:54.019835
6806 18:03:54.023200 RX Vref 0 -> 0, step: 1
6807 18:03:54.023280
6808 18:03:54.026919 RX Delay -359 -> 252, step: 8
6809 18:03:54.026999
6810 18:03:54.029509 Set Vref, RX VrefLevel [Byte0]: 56
6811 18:03:54.032895 [Byte1]: 53
6812 18:03:54.033005
6813 18:03:54.036462 Final RX Vref Byte 0 = 56 to rank0
6814 18:03:54.040003 Final RX Vref Byte 1 = 53 to rank0
6815 18:03:54.043020 Final RX Vref Byte 0 = 56 to rank1
6816 18:03:54.046341 Final RX Vref Byte 1 = 53 to rank1==
6817 18:03:54.049807 Dram Type= 6, Freq= 0, CH_1, rank 0
6818 18:03:54.053243 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6819 18:03:54.056196 ==
6820 18:03:54.056302 DQS Delay:
6821 18:03:54.056402 DQS0 = 48, DQS1 = 60
6822 18:03:54.060138 DQM Delay:
6823 18:03:54.060220 DQM0 = 12, DQM1 = 13
6824 18:03:54.063244 DQ Delay:
6825 18:03:54.063327 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6826 18:03:54.066259 DQ4 =12, DQ5 =20, DQ6 =24, DQ7 =8
6827 18:03:54.069495 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =12
6828 18:03:54.072972 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20
6829 18:03:54.073121
6830 18:03:54.073221
6831 18:03:54.083035 [DQSOSCAuto] RK0, (LSB)MR18= 0x8028, (MSB)MR19= 0xc0c, tDQSOscB0 = 404 ps tDQSOscB1 = 393 ps
6832 18:03:54.086408 CH1 RK0: MR19=C0C, MR18=8028
6833 18:03:54.092951 CH1_RK0: MR19=0xC0C, MR18=0x8028, DQSOSC=393, MR23=63, INC=382, DEC=254
6834 18:03:54.093062 ==
6835 18:03:54.096134 Dram Type= 6, Freq= 0, CH_1, rank 1
6836 18:03:54.099889 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6837 18:03:54.099975 ==
6838 18:03:54.103057 [Gating] SW mode calibration
6839 18:03:54.109789 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6840 18:03:54.113359 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6841 18:03:54.119555 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6842 18:03:54.123797 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6843 18:03:54.126543 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6844 18:03:54.133412 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6845 18:03:54.136642 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6846 18:03:54.139748 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6847 18:03:54.146240 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6848 18:03:54.149698 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6849 18:03:54.153219 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6850 18:03:54.156045 Total UI for P1: 0, mck2ui 16
6851 18:03:54.159412 best dqsien dly found for B0: ( 0, 14, 24)
6852 18:03:54.162969 Total UI for P1: 0, mck2ui 16
6853 18:03:54.166255 best dqsien dly found for B1: ( 0, 14, 24)
6854 18:03:54.169441 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6855 18:03:54.172915 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6856 18:03:54.173060
6857 18:03:54.179860 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6858 18:03:54.182622 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6859 18:03:54.186082 [Gating] SW calibration Done
6860 18:03:54.186170 ==
6861 18:03:54.189174 Dram Type= 6, Freq= 0, CH_1, rank 1
6862 18:03:54.192451 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6863 18:03:54.192535 ==
6864 18:03:54.192619 RX Vref Scan: 0
6865 18:03:54.192697
6866 18:03:54.195947 RX Vref 0 -> 0, step: 1
6867 18:03:54.196029
6868 18:03:54.199499 RX Delay -410 -> 252, step: 16
6869 18:03:54.202463 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6870 18:03:54.209295 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6871 18:03:54.212752 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6872 18:03:54.215548 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6873 18:03:54.219107 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6874 18:03:54.225836 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6875 18:03:54.229336 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6876 18:03:54.232132 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6877 18:03:54.235553 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6878 18:03:54.238898 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6879 18:03:54.245532 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6880 18:03:54.248904 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6881 18:03:54.252542 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6882 18:03:54.259307 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6883 18:03:54.262190 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6884 18:03:54.265603 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6885 18:03:54.265703 ==
6886 18:03:54.269066 Dram Type= 6, Freq= 0, CH_1, rank 1
6887 18:03:54.272251 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6888 18:03:54.275879 ==
6889 18:03:54.275958 DQS Delay:
6890 18:03:54.276022 DQS0 = 43, DQS1 = 59
6891 18:03:54.279086 DQM Delay:
6892 18:03:54.279165 DQM0 = 10, DQM1 = 20
6893 18:03:54.282398 DQ Delay:
6894 18:03:54.282478 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6895 18:03:54.285927 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6896 18:03:54.289294 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6897 18:03:54.292539 DQ12 =24, DQ13 =32, DQ14 =32, DQ15 =32
6898 18:03:54.292625
6899 18:03:54.292690
6900 18:03:54.292748 ==
6901 18:03:54.295697 Dram Type= 6, Freq= 0, CH_1, rank 1
6902 18:03:54.302689 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6903 18:03:54.302778 ==
6904 18:03:54.302843
6905 18:03:54.302902
6906 18:03:54.302958 TX Vref Scan disable
6907 18:03:54.305648 == TX Byte 0 ==
6908 18:03:54.309005 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6909 18:03:54.312535 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6910 18:03:54.315837 == TX Byte 1 ==
6911 18:03:54.319141 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6912 18:03:54.322765 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6913 18:03:54.322839 ==
6914 18:03:54.325840 Dram Type= 6, Freq= 0, CH_1, rank 1
6915 18:03:54.332815 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6916 18:03:54.332917 ==
6917 18:03:54.333048
6918 18:03:54.333134
6919 18:03:54.333219 TX Vref Scan disable
6920 18:03:54.335583 == TX Byte 0 ==
6921 18:03:54.339407 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6922 18:03:54.342805 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6923 18:03:54.345819 == TX Byte 1 ==
6924 18:03:54.349421 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6925 18:03:54.352583 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6926 18:03:54.352657
6927 18:03:54.355869 [DATLAT]
6928 18:03:54.355966 Freq=400, CH1 RK1
6929 18:03:54.356057
6930 18:03:54.359087 DATLAT Default: 0xe
6931 18:03:54.359160 0, 0xFFFF, sum = 0
6932 18:03:54.362705 1, 0xFFFF, sum = 0
6933 18:03:54.362781 2, 0xFFFF, sum = 0
6934 18:03:54.366264 3, 0xFFFF, sum = 0
6935 18:03:54.366337 4, 0xFFFF, sum = 0
6936 18:03:54.368978 5, 0xFFFF, sum = 0
6937 18:03:54.369061 6, 0xFFFF, sum = 0
6938 18:03:54.372487 7, 0xFFFF, sum = 0
6939 18:03:54.372567 8, 0xFFFF, sum = 0
6940 18:03:54.375800 9, 0xFFFF, sum = 0
6941 18:03:54.375880 10, 0xFFFF, sum = 0
6942 18:03:54.379365 11, 0xFFFF, sum = 0
6943 18:03:54.379473 12, 0xFFFF, sum = 0
6944 18:03:54.382650 13, 0x0, sum = 1
6945 18:03:54.382730 14, 0x0, sum = 2
6946 18:03:54.386214 15, 0x0, sum = 3
6947 18:03:54.386295 16, 0x0, sum = 4
6948 18:03:54.389124 best_step = 14
6949 18:03:54.389204
6950 18:03:54.389267 ==
6951 18:03:54.392432 Dram Type= 6, Freq= 0, CH_1, rank 1
6952 18:03:54.395874 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6953 18:03:54.395955 ==
6954 18:03:54.399413 RX Vref Scan: 0
6955 18:03:54.399495
6956 18:03:54.399558 RX Vref 0 -> 0, step: 1
6957 18:03:54.399639
6958 18:03:54.402553 RX Delay -359 -> 252, step: 8
6959 18:03:54.410648 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6960 18:03:54.414117 iDelay=217, Bit 1, Center -44 (-287 ~ 200) 488
6961 18:03:54.416963 iDelay=217, Bit 2, Center -52 (-295 ~ 192) 488
6962 18:03:54.420429 iDelay=217, Bit 3, Center -44 (-287 ~ 200) 488
6963 18:03:54.427339 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6964 18:03:54.430454 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6965 18:03:54.433765 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6966 18:03:54.436986 iDelay=217, Bit 7, Center -44 (-287 ~ 200) 488
6967 18:03:54.443878 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
6968 18:03:54.447002 iDelay=217, Bit 9, Center -56 (-303 ~ 192) 496
6969 18:03:54.450340 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6970 18:03:54.456913 iDelay=217, Bit 11, Center -56 (-303 ~ 192) 496
6971 18:03:54.460351 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6972 18:03:54.463632 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6973 18:03:54.466895 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6974 18:03:54.473727 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6975 18:03:54.473834 ==
6976 18:03:54.477250 Dram Type= 6, Freq= 0, CH_1, rank 1
6977 18:03:54.480620 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6978 18:03:54.480702 ==
6979 18:03:54.480765 DQS Delay:
6980 18:03:54.483559 DQS0 = 52, DQS1 = 56
6981 18:03:54.483640 DQM Delay:
6982 18:03:54.487248 DQM0 = 13, DQM1 = 8
6983 18:03:54.487329 DQ Delay:
6984 18:03:54.490838 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6985 18:03:54.494230 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =8
6986 18:03:54.497160 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6987 18:03:54.500729 DQ12 =12, DQ13 =16, DQ14 =16, DQ15 =16
6988 18:03:54.500838
6989 18:03:54.500929
6990 18:03:54.507475 [DQSOSCAuto] RK1, (LSB)MR18= 0x6e83, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 395 ps
6991 18:03:54.510876 CH1 RK1: MR19=C0C, MR18=6E83
6992 18:03:54.517131 CH1_RK1: MR19=0xC0C, MR18=0x6E83, DQSOSC=393, MR23=63, INC=382, DEC=254
6993 18:03:54.520607 [RxdqsGatingPostProcess] freq 400
6994 18:03:54.523843 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6995 18:03:54.527307 best DQS0 dly(2T, 0.5T) = (0, 10)
6996 18:03:54.530834 best DQS1 dly(2T, 0.5T) = (0, 10)
6997 18:03:54.534126 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6998 18:03:54.537507 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6999 18:03:54.540826 best DQS0 dly(2T, 0.5T) = (0, 10)
7000 18:03:54.543945 best DQS1 dly(2T, 0.5T) = (0, 10)
7001 18:03:54.547154 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7002 18:03:54.551209 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7003 18:03:54.553788 Pre-setting of DQS Precalculation
7004 18:03:54.557417 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7005 18:03:54.567155 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7006 18:03:54.574159 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7007 18:03:54.574247
7008 18:03:54.574310
7009 18:03:54.577312 [Calibration Summary] 800 Mbps
7010 18:03:54.577393 CH 0, Rank 0
7011 18:03:54.580689 SW Impedance : PASS
7012 18:03:54.580776 DUTY Scan : NO K
7013 18:03:54.583671 ZQ Calibration : PASS
7014 18:03:54.587244 Jitter Meter : NO K
7015 18:03:54.587352 CBT Training : PASS
7016 18:03:54.590654 Write leveling : PASS
7017 18:03:54.590727 RX DQS gating : PASS
7018 18:03:54.593994 RX DQ/DQS(RDDQC) : PASS
7019 18:03:54.597343 TX DQ/DQS : PASS
7020 18:03:54.597450 RX DATLAT : PASS
7021 18:03:54.600939 RX DQ/DQS(Engine): PASS
7022 18:03:54.604524 TX OE : NO K
7023 18:03:54.604612 All Pass.
7024 18:03:54.604704
7025 18:03:54.604791 CH 0, Rank 1
7026 18:03:54.607329 SW Impedance : PASS
7027 18:03:54.610750 DUTY Scan : NO K
7028 18:03:54.610830 ZQ Calibration : PASS
7029 18:03:54.614238 Jitter Meter : NO K
7030 18:03:54.617651 CBT Training : PASS
7031 18:03:54.617732 Write leveling : NO K
7032 18:03:54.620762 RX DQS gating : PASS
7033 18:03:54.623871 RX DQ/DQS(RDDQC) : PASS
7034 18:03:54.623951 TX DQ/DQS : PASS
7035 18:03:54.627813 RX DATLAT : PASS
7036 18:03:54.627887 RX DQ/DQS(Engine): PASS
7037 18:03:54.630757 TX OE : NO K
7038 18:03:54.630831 All Pass.
7039 18:03:54.630891
7040 18:03:54.634097 CH 1, Rank 0
7041 18:03:54.634176 SW Impedance : PASS
7042 18:03:54.637353 DUTY Scan : NO K
7043 18:03:54.640726 ZQ Calibration : PASS
7044 18:03:54.640805 Jitter Meter : NO K
7045 18:03:54.644146 CBT Training : PASS
7046 18:03:54.647162 Write leveling : PASS
7047 18:03:54.647242 RX DQS gating : PASS
7048 18:03:54.650713 RX DQ/DQS(RDDQC) : PASS
7049 18:03:54.654160 TX DQ/DQS : PASS
7050 18:03:54.654241 RX DATLAT : PASS
7051 18:03:54.657115 RX DQ/DQS(Engine): PASS
7052 18:03:54.660819 TX OE : NO K
7053 18:03:54.660924 All Pass.
7054 18:03:54.661044
7055 18:03:54.661105 CH 1, Rank 1
7056 18:03:54.663963 SW Impedance : PASS
7057 18:03:54.667109 DUTY Scan : NO K
7058 18:03:54.667189 ZQ Calibration : PASS
7059 18:03:54.671104 Jitter Meter : NO K
7060 18:03:54.671184 CBT Training : PASS
7061 18:03:54.673977 Write leveling : NO K
7062 18:03:54.677625 RX DQS gating : PASS
7063 18:03:54.677704 RX DQ/DQS(RDDQC) : PASS
7064 18:03:54.680858 TX DQ/DQS : PASS
7065 18:03:54.683785 RX DATLAT : PASS
7066 18:03:54.683865 RX DQ/DQS(Engine): PASS
7067 18:03:54.687463 TX OE : NO K
7068 18:03:54.687546 All Pass.
7069 18:03:54.687629
7070 18:03:54.690892 DramC Write-DBI off
7071 18:03:54.693728 PER_BANK_REFRESH: Hybrid Mode
7072 18:03:54.693810 TX_TRACKING: ON
7073 18:03:54.704304 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7074 18:03:54.707820 [FAST_K] Save calibration result to emmc
7075 18:03:54.710601 dramc_set_vcore_voltage set vcore to 725000
7076 18:03:54.714143 Read voltage for 1600, 0
7077 18:03:54.714228 Vio18 = 0
7078 18:03:54.714295 Vcore = 725000
7079 18:03:54.717580 Vdram = 0
7080 18:03:54.717659 Vddq = 0
7081 18:03:54.717722 Vmddr = 0
7082 18:03:54.723958 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7083 18:03:54.727159 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7084 18:03:54.730838 MEM_TYPE=3, freq_sel=13
7085 18:03:54.733843 sv_algorithm_assistance_LP4_3733
7086 18:03:54.737400 ============ PULL DRAM RESETB DOWN ============
7087 18:03:54.740825 ========== PULL DRAM RESETB DOWN end =========
7088 18:03:54.747536 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7089 18:03:54.750830 ===================================
7090 18:03:54.753809 LPDDR4 DRAM CONFIGURATION
7091 18:03:54.757179 ===================================
7092 18:03:54.757342 EX_ROW_EN[0] = 0x0
7093 18:03:54.760601 EX_ROW_EN[1] = 0x0
7094 18:03:54.760750 LP4Y_EN = 0x0
7095 18:03:54.764149 WORK_FSP = 0x1
7096 18:03:54.764251 WL = 0x5
7097 18:03:54.768133 RL = 0x5
7098 18:03:54.768275 BL = 0x2
7099 18:03:54.770906 RPST = 0x0
7100 18:03:54.771136 RD_PRE = 0x0
7101 18:03:54.773961 WR_PRE = 0x1
7102 18:03:54.774105 WR_PST = 0x1
7103 18:03:54.777614 DBI_WR = 0x0
7104 18:03:54.777696 DBI_RD = 0x0
7105 18:03:54.780887 OTF = 0x1
7106 18:03:54.783922 ===================================
7107 18:03:54.787198 ===================================
7108 18:03:54.787313 ANA top config
7109 18:03:54.790787 ===================================
7110 18:03:54.794161 DLL_ASYNC_EN = 0
7111 18:03:54.797583 ALL_SLAVE_EN = 0
7112 18:03:54.800690 NEW_RANK_MODE = 1
7113 18:03:54.800802 DLL_IDLE_MODE = 1
7114 18:03:54.804318 LP45_APHY_COMB_EN = 1
7115 18:03:54.807614 TX_ODT_DIS = 0
7116 18:03:54.810658 NEW_8X_MODE = 1
7117 18:03:54.814284 ===================================
7118 18:03:54.817313 ===================================
7119 18:03:54.820614 data_rate = 3200
7120 18:03:54.820694 CKR = 1
7121 18:03:54.823953 DQ_P2S_RATIO = 8
7122 18:03:54.827408 ===================================
7123 18:03:54.830920 CA_P2S_RATIO = 8
7124 18:03:54.833831 DQ_CA_OPEN = 0
7125 18:03:54.837289 DQ_SEMI_OPEN = 0
7126 18:03:54.837371 CA_SEMI_OPEN = 0
7127 18:03:54.840469 CA_FULL_RATE = 0
7128 18:03:54.844377 DQ_CKDIV4_EN = 0
7129 18:03:54.847901 CA_CKDIV4_EN = 0
7130 18:03:54.850512 CA_PREDIV_EN = 0
7131 18:03:54.854034 PH8_DLY = 12
7132 18:03:54.857394 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7133 18:03:54.857475 DQ_AAMCK_DIV = 4
7134 18:03:54.860378 CA_AAMCK_DIV = 4
7135 18:03:54.863991 CA_ADMCK_DIV = 4
7136 18:03:54.867284 DQ_TRACK_CA_EN = 0
7137 18:03:54.870488 CA_PICK = 1600
7138 18:03:54.873737 CA_MCKIO = 1600
7139 18:03:54.873818 MCKIO_SEMI = 0
7140 18:03:54.877491 PLL_FREQ = 3068
7141 18:03:54.880398 DQ_UI_PI_RATIO = 32
7142 18:03:54.883984 CA_UI_PI_RATIO = 0
7143 18:03:54.887311 ===================================
7144 18:03:54.890626 ===================================
7145 18:03:54.894060 memory_type:LPDDR4
7146 18:03:54.894146 GP_NUM : 10
7147 18:03:54.896914 SRAM_EN : 1
7148 18:03:54.900370 MD32_EN : 0
7149 18:03:54.903663 ===================================
7150 18:03:54.903747 [ANA_INIT] >>>>>>>>>>>>>>
7151 18:03:54.906917 <<<<<< [CONFIGURE PHASE]: ANA_TX
7152 18:03:54.910286 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7153 18:03:54.913617 ===================================
7154 18:03:54.917284 data_rate = 3200,PCW = 0X7600
7155 18:03:54.920304 ===================================
7156 18:03:54.923767 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7157 18:03:54.930253 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7158 18:03:54.933652 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7159 18:03:54.940555 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7160 18:03:54.943355 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7161 18:03:54.947110 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7162 18:03:54.947209 [ANA_INIT] flow start
7163 18:03:54.950261 [ANA_INIT] PLL >>>>>>>>
7164 18:03:54.953794 [ANA_INIT] PLL <<<<<<<<
7165 18:03:54.956849 [ANA_INIT] MIDPI >>>>>>>>
7166 18:03:54.956949 [ANA_INIT] MIDPI <<<<<<<<
7167 18:03:54.960188 [ANA_INIT] DLL >>>>>>>>
7168 18:03:54.963424 [ANA_INIT] DLL <<<<<<<<
7169 18:03:54.963500 [ANA_INIT] flow end
7170 18:03:54.966863 ============ LP4 DIFF to SE enter ============
7171 18:03:54.973918 ============ LP4 DIFF to SE exit ============
7172 18:03:54.974001 [ANA_INIT] <<<<<<<<<<<<<
7173 18:03:54.976853 [Flow] Enable top DCM control >>>>>
7174 18:03:54.980346 [Flow] Enable top DCM control <<<<<
7175 18:03:54.983150 Enable DLL master slave shuffle
7176 18:03:54.990062 ==============================================================
7177 18:03:54.990138 Gating Mode config
7178 18:03:54.996793 ==============================================================
7179 18:03:55.000208 Config description:
7180 18:03:55.010336 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7181 18:03:55.017122 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7182 18:03:55.019854 SELPH_MODE 0: By rank 1: By Phase
7183 18:03:55.026594 ==============================================================
7184 18:03:55.029849 GAT_TRACK_EN = 1
7185 18:03:55.029931 RX_GATING_MODE = 2
7186 18:03:55.033263 RX_GATING_TRACK_MODE = 2
7187 18:03:55.037323 SELPH_MODE = 1
7188 18:03:55.040045 PICG_EARLY_EN = 1
7189 18:03:55.043645 VALID_LAT_VALUE = 1
7190 18:03:55.049987 ==============================================================
7191 18:03:55.053497 Enter into Gating configuration >>>>
7192 18:03:55.056815 Exit from Gating configuration <<<<
7193 18:03:55.060107 Enter into DVFS_PRE_config >>>>>
7194 18:03:55.070169 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7195 18:03:55.073843 Exit from DVFS_PRE_config <<<<<
7196 18:03:55.077308 Enter into PICG configuration >>>>
7197 18:03:55.080252 Exit from PICG configuration <<<<
7198 18:03:55.083626 [RX_INPUT] configuration >>>>>
7199 18:03:55.083710 [RX_INPUT] configuration <<<<<
7200 18:03:55.090462 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7201 18:03:55.096959 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7202 18:03:55.099994 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7203 18:03:55.106747 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7204 18:03:55.113666 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7205 18:03:55.120357 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7206 18:03:55.123289 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7207 18:03:55.126489 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7208 18:03:55.133646 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7209 18:03:55.136526 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7210 18:03:55.140380 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7211 18:03:55.146726 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7212 18:03:55.150248 ===================================
7213 18:03:55.150328 LPDDR4 DRAM CONFIGURATION
7214 18:03:55.153452 ===================================
7215 18:03:55.156909 EX_ROW_EN[0] = 0x0
7216 18:03:55.157046 EX_ROW_EN[1] = 0x0
7217 18:03:55.160347 LP4Y_EN = 0x0
7218 18:03:55.160427 WORK_FSP = 0x1
7219 18:03:55.163147 WL = 0x5
7220 18:03:55.163227 RL = 0x5
7221 18:03:55.166565 BL = 0x2
7222 18:03:55.166670 RPST = 0x0
7223 18:03:55.170233 RD_PRE = 0x0
7224 18:03:55.173500 WR_PRE = 0x1
7225 18:03:55.173583 WR_PST = 0x1
7226 18:03:55.177160 DBI_WR = 0x0
7227 18:03:55.177240 DBI_RD = 0x0
7228 18:03:55.180467 OTF = 0x1
7229 18:03:55.183375 ===================================
7230 18:03:55.186857 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7231 18:03:55.190299 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7232 18:03:55.193865 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7233 18:03:55.196655 ===================================
7234 18:03:55.200296 LPDDR4 DRAM CONFIGURATION
7235 18:03:55.203289 ===================================
7236 18:03:55.206767 EX_ROW_EN[0] = 0x10
7237 18:03:55.206873 EX_ROW_EN[1] = 0x0
7238 18:03:55.210313 LP4Y_EN = 0x0
7239 18:03:55.210400 WORK_FSP = 0x1
7240 18:03:55.213608 WL = 0x5
7241 18:03:55.213687 RL = 0x5
7242 18:03:55.216841 BL = 0x2
7243 18:03:55.216920 RPST = 0x0
7244 18:03:55.220134 RD_PRE = 0x0
7245 18:03:55.220214 WR_PRE = 0x1
7246 18:03:55.223439 WR_PST = 0x1
7247 18:03:55.223519 DBI_WR = 0x0
7248 18:03:55.226895 DBI_RD = 0x0
7249 18:03:55.226974 OTF = 0x1
7250 18:03:55.230030 ===================================
7251 18:03:55.236716 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7252 18:03:55.236799 ==
7253 18:03:55.239964 Dram Type= 6, Freq= 0, CH_0, rank 0
7254 18:03:55.246530 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7255 18:03:55.246613 ==
7256 18:03:55.246676 [Duty_Offset_Calibration]
7257 18:03:55.250002 B0:2 B1:-1 CA:1
7258 18:03:55.250082
7259 18:03:55.253531 [DutyScan_Calibration_Flow] k_type=0
7260 18:03:55.261997
7261 18:03:55.262078 ==CLK 0==
7262 18:03:55.265058 Final CLK duty delay cell = -4
7263 18:03:55.268637 [-4] MAX Duty = 5031%(X100), DQS PI = 22
7264 18:03:55.272036 [-4] MIN Duty = 4844%(X100), DQS PI = 38
7265 18:03:55.275027 [-4] AVG Duty = 4937%(X100)
7266 18:03:55.275106
7267 18:03:55.278459 CH0 CLK Duty spec in!! Max-Min= 187%
7268 18:03:55.282073 [DutyScan_Calibration_Flow] ====Done====
7269 18:03:55.282153
7270 18:03:55.285029 [DutyScan_Calibration_Flow] k_type=1
7271 18:03:55.301381
7272 18:03:55.301481 ==DQS 0 ==
7273 18:03:55.305004 Final DQS duty delay cell = 0
7274 18:03:55.308190 [0] MAX Duty = 5125%(X100), DQS PI = 20
7275 18:03:55.311111 [0] MIN Duty = 5000%(X100), DQS PI = 16
7276 18:03:55.314576 [0] AVG Duty = 5062%(X100)
7277 18:03:55.314656
7278 18:03:55.314718 ==DQS 1 ==
7279 18:03:55.318237 Final DQS duty delay cell = -4
7280 18:03:55.321655 [-4] MAX Duty = 5093%(X100), DQS PI = 0
7281 18:03:55.324808 [-4] MIN Duty = 5000%(X100), DQS PI = 40
7282 18:03:55.328369 [-4] AVG Duty = 5046%(X100)
7283 18:03:55.328453
7284 18:03:55.331836 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7285 18:03:55.331915
7286 18:03:55.334515 CH0 DQS 1 Duty spec in!! Max-Min= 93%
7287 18:03:55.337944 [DutyScan_Calibration_Flow] ====Done====
7288 18:03:55.338023
7289 18:03:55.341268 [DutyScan_Calibration_Flow] k_type=3
7290 18:03:55.358624
7291 18:03:55.358710 ==DQM 0 ==
7292 18:03:55.362118 Final DQM duty delay cell = 0
7293 18:03:55.365012 [0] MAX Duty = 5000%(X100), DQS PI = 18
7294 18:03:55.368840 [0] MIN Duty = 4875%(X100), DQS PI = 4
7295 18:03:55.368948 [0] AVG Duty = 4937%(X100)
7296 18:03:55.371825
7297 18:03:55.371907 ==DQM 1 ==
7298 18:03:55.375158 Final DQM duty delay cell = 0
7299 18:03:55.378669 [0] MAX Duty = 5187%(X100), DQS PI = 58
7300 18:03:55.382056 [0] MIN Duty = 4969%(X100), DQS PI = 18
7301 18:03:55.384941 [0] AVG Duty = 5078%(X100)
7302 18:03:55.385067
7303 18:03:55.388427 CH0 DQM 0 Duty spec in!! Max-Min= 125%
7304 18:03:55.388506
7305 18:03:55.391898 CH0 DQM 1 Duty spec in!! Max-Min= 218%
7306 18:03:55.395742 [DutyScan_Calibration_Flow] ====Done====
7307 18:03:55.395821
7308 18:03:55.398804 [DutyScan_Calibration_Flow] k_type=2
7309 18:03:55.414977
7310 18:03:55.415066 ==DQ 0 ==
7311 18:03:55.418279 Final DQ duty delay cell = -4
7312 18:03:55.421819 [-4] MAX Duty = 5000%(X100), DQS PI = 0
7313 18:03:55.425204 [-4] MIN Duty = 4844%(X100), DQS PI = 12
7314 18:03:55.428351 [-4] AVG Duty = 4922%(X100)
7315 18:03:55.428462
7316 18:03:55.428525 ==DQ 1 ==
7317 18:03:55.431749 Final DQ duty delay cell = 0
7318 18:03:55.435132 [0] MAX Duty = 5031%(X100), DQS PI = 30
7319 18:03:55.438182 [0] MIN Duty = 4907%(X100), DQS PI = 18
7320 18:03:55.438253 [0] AVG Duty = 4969%(X100)
7321 18:03:55.441522
7322 18:03:55.444897 CH0 DQ 0 Duty spec in!! Max-Min= 156%
7323 18:03:55.444999
7324 18:03:55.448442 CH0 DQ 1 Duty spec in!! Max-Min= 124%
7325 18:03:55.451825 [DutyScan_Calibration_Flow] ====Done====
7326 18:03:55.451904 ==
7327 18:03:55.454854 Dram Type= 6, Freq= 0, CH_1, rank 0
7328 18:03:55.458298 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7329 18:03:55.458404 ==
7330 18:03:55.461767 [Duty_Offset_Calibration]
7331 18:03:55.461872 B0:1 B1:1 CA:2
7332 18:03:55.461963
7333 18:03:55.465008 [DutyScan_Calibration_Flow] k_type=0
7334 18:03:55.475154
7335 18:03:55.475233 ==CLK 0==
7336 18:03:55.478464 Final CLK duty delay cell = 0
7337 18:03:55.482280 [0] MAX Duty = 5187%(X100), DQS PI = 24
7338 18:03:55.485923 [0] MIN Duty = 4938%(X100), DQS PI = 50
7339 18:03:55.486003 [0] AVG Duty = 5062%(X100)
7340 18:03:55.488807
7341 18:03:55.492079 CH1 CLK Duty spec in!! Max-Min= 249%
7342 18:03:55.495488 [DutyScan_Calibration_Flow] ====Done====
7343 18:03:55.495568
7344 18:03:55.498684 [DutyScan_Calibration_Flow] k_type=1
7345 18:03:55.515103
7346 18:03:55.515213 ==DQS 0 ==
7347 18:03:55.518698 Final DQS duty delay cell = 0
7348 18:03:55.521513 [0] MAX Duty = 5062%(X100), DQS PI = 20
7349 18:03:55.524964 [0] MIN Duty = 4813%(X100), DQS PI = 50
7350 18:03:55.528470 [0] AVG Duty = 4937%(X100)
7351 18:03:55.528549
7352 18:03:55.528612 ==DQS 1 ==
7353 18:03:55.532026 Final DQS duty delay cell = 0
7354 18:03:55.535234 [0] MAX Duty = 5031%(X100), DQS PI = 34
7355 18:03:55.538126 [0] MIN Duty = 4938%(X100), DQS PI = 12
7356 18:03:55.542137 [0] AVG Duty = 4984%(X100)
7357 18:03:55.542217
7358 18:03:55.544961 CH1 DQS 0 Duty spec in!! Max-Min= 249%
7359 18:03:55.545063
7360 18:03:55.548266 CH1 DQS 1 Duty spec in!! Max-Min= 93%
7361 18:03:55.551727 [DutyScan_Calibration_Flow] ====Done====
7362 18:03:55.551807
7363 18:03:55.555092 [DutyScan_Calibration_Flow] k_type=3
7364 18:03:55.571942
7365 18:03:55.572034 ==DQM 0 ==
7366 18:03:55.575270 Final DQM duty delay cell = 0
7367 18:03:55.578723 [0] MAX Duty = 5156%(X100), DQS PI = 20
7368 18:03:55.582170 [0] MIN Duty = 4844%(X100), DQS PI = 50
7369 18:03:55.585395 [0] AVG Duty = 5000%(X100)
7370 18:03:55.585475
7371 18:03:55.585538 ==DQM 1 ==
7372 18:03:55.588755 Final DQM duty delay cell = 0
7373 18:03:55.591763 [0] MAX Duty = 5125%(X100), DQS PI = 8
7374 18:03:55.595111 [0] MIN Duty = 4875%(X100), DQS PI = 22
7375 18:03:55.595191 [0] AVG Duty = 5000%(X100)
7376 18:03:55.598465
7377 18:03:55.602018 CH1 DQM 0 Duty spec in!! Max-Min= 312%
7378 18:03:55.602100
7379 18:03:55.605331 CH1 DQM 1 Duty spec in!! Max-Min= 250%
7380 18:03:55.608702 [DutyScan_Calibration_Flow] ====Done====
7381 18:03:55.608805
7382 18:03:55.611855 [DutyScan_Calibration_Flow] k_type=2
7383 18:03:55.628599
7384 18:03:55.628693 ==DQ 0 ==
7385 18:03:55.632109 Final DQ duty delay cell = 0
7386 18:03:55.635272 [0] MAX Duty = 5156%(X100), DQS PI = 22
7387 18:03:55.638589 [0] MIN Duty = 4907%(X100), DQS PI = 52
7388 18:03:55.638685 [0] AVG Duty = 5031%(X100)
7389 18:03:55.642253
7390 18:03:55.642385 ==DQ 1 ==
7391 18:03:55.645401 Final DQ duty delay cell = 0
7392 18:03:55.648339 [0] MAX Duty = 5093%(X100), DQS PI = 8
7393 18:03:55.651741 [0] MIN Duty = 5031%(X100), DQS PI = 0
7394 18:03:55.651822 [0] AVG Duty = 5062%(X100)
7395 18:03:55.651886
7396 18:03:55.655290 CH1 DQ 0 Duty spec in!! Max-Min= 249%
7397 18:03:55.655369
7398 18:03:55.658922 CH1 DQ 1 Duty spec in!! Max-Min= 62%
7399 18:03:55.665102 [DutyScan_Calibration_Flow] ====Done====
7400 18:03:55.668837 nWR fixed to 30
7401 18:03:55.668943 [ModeRegInit_LP4] CH0 RK0
7402 18:03:55.671676 [ModeRegInit_LP4] CH0 RK1
7403 18:03:55.675195 [ModeRegInit_LP4] CH1 RK0
7404 18:03:55.675300 [ModeRegInit_LP4] CH1 RK1
7405 18:03:55.678689 match AC timing 5
7406 18:03:55.681843 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7407 18:03:55.685353 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7408 18:03:55.692202 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7409 18:03:55.695461 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7410 18:03:55.701828 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7411 18:03:55.701911 [MiockJmeterHQA]
7412 18:03:55.701979
7413 18:03:55.705221 [DramcMiockJmeter] u1RxGatingPI = 0
7414 18:03:55.705301 0 : 4255, 4029
7415 18:03:55.708993 4 : 4254, 4029
7416 18:03:55.709094 8 : 4260, 4032
7417 18:03:55.712523 12 : 4257, 4030
7418 18:03:55.712631 16 : 4250, 4027
7419 18:03:55.715894 20 : 4365, 4142
7420 18:03:55.715975 24 : 4253, 4026
7421 18:03:55.716038 28 : 4254, 4030
7422 18:03:55.718987 32 : 4255, 4029
7423 18:03:55.719067 36 : 4366, 4139
7424 18:03:55.722068 40 : 4254, 4030
7425 18:03:55.722149 44 : 4252, 4027
7426 18:03:55.725370 48 : 4250, 4027
7427 18:03:55.725451 52 : 4252, 4030
7428 18:03:55.728856 56 : 4255, 4029
7429 18:03:55.728963 60 : 4252, 4029
7430 18:03:55.729067 64 : 4360, 4137
7431 18:03:55.732330 68 : 4253, 4029
7432 18:03:55.732411 72 : 4250, 4027
7433 18:03:55.735845 76 : 4360, 4138
7434 18:03:55.735926 80 : 4365, 4140
7435 18:03:55.739266 84 : 4255, 4029
7436 18:03:55.739347 88 : 4253, 4029
7437 18:03:55.739410 92 : 4250, 4026
7438 18:03:55.742042 96 : 4252, 3379
7439 18:03:55.742132 100 : 4255, 0
7440 18:03:55.745677 104 : 4365, 0
7441 18:03:55.745758 108 : 4250, 0
7442 18:03:55.745821 112 : 4249, 0
7443 18:03:55.749311 116 : 4250, 0
7444 18:03:55.749392 120 : 4253, 0
7445 18:03:55.752069 124 : 4252, 0
7446 18:03:55.752150 128 : 4257, 0
7447 18:03:55.752213 132 : 4250, 0
7448 18:03:55.755664 136 : 4254, 0
7449 18:03:55.755744 140 : 4255, 0
7450 18:03:55.759152 144 : 4250, 0
7451 18:03:55.759232 148 : 4360, 0
7452 18:03:55.759296 152 : 4250, 0
7453 18:03:55.761994 156 : 4360, 0
7454 18:03:55.762096 160 : 4250, 0
7455 18:03:55.765891 164 : 4254, 0
7456 18:03:55.765972 168 : 4363, 0
7457 18:03:55.766036 172 : 4252, 0
7458 18:03:55.768907 176 : 4254, 0
7459 18:03:55.769044 180 : 4363, 0
7460 18:03:55.769110 184 : 4363, 0
7461 18:03:55.772069 188 : 4255, 0
7462 18:03:55.772149 192 : 4250, 0
7463 18:03:55.775824 196 : 4250, 0
7464 18:03:55.775918 200 : 4252, 0
7465 18:03:55.775999 204 : 4253, 0
7466 18:03:55.778799 208 : 4363, 0
7467 18:03:55.778876 212 : 4253, 50
7468 18:03:55.782428 216 : 4253, 3514
7469 18:03:55.782497 220 : 4361, 4138
7470 18:03:55.785836 224 : 4253, 4029
7471 18:03:55.785918 228 : 4249, 4027
7472 18:03:55.785983 232 : 4255, 4029
7473 18:03:55.788843 236 : 4253, 4029
7474 18:03:55.788924 240 : 4360, 4137
7475 18:03:55.792370 244 : 4363, 4137
7476 18:03:55.792451 248 : 4255, 4029
7477 18:03:55.795832 252 : 4250, 4027
7478 18:03:55.795913 256 : 4360, 4138
7479 18:03:55.798808 260 : 4363, 4140
7480 18:03:55.798888 264 : 4363, 4138
7481 18:03:55.802525 268 : 4250, 4027
7482 18:03:55.802605 272 : 4252, 4026
7483 18:03:55.805771 276 : 4252, 4029
7484 18:03:55.805852 280 : 4253, 4029
7485 18:03:55.809130 284 : 4249, 4027
7486 18:03:55.809211 288 : 4363, 4140
7487 18:03:55.809276 292 : 4250, 4026
7488 18:03:55.811982 296 : 4250, 4027
7489 18:03:55.812063 300 : 4255, 4029
7490 18:03:55.815772 304 : 4249, 4027
7491 18:03:55.815852 308 : 4250, 4027
7492 18:03:55.819199 312 : 4250, 4027
7493 18:03:55.819280 316 : 4255, 4029
7494 18:03:55.822294 320 : 4249, 4027
7495 18:03:55.822375 324 : 4250, 4027
7496 18:03:55.825423 328 : 4250, 4026
7497 18:03:55.825503 332 : 4249, 3082
7498 18:03:55.828587 336 : 4255, 62
7499 18:03:55.828668
7500 18:03:55.828731 MIOCK jitter meter ch=0
7501 18:03:55.828790
7502 18:03:55.832296 1T = (336-100) = 236 dly cells
7503 18:03:55.839206 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7504 18:03:55.839287 ==
7505 18:03:55.842111 Dram Type= 6, Freq= 0, CH_0, rank 0
7506 18:03:55.845552 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7507 18:03:55.845633 ==
7508 18:03:55.852880 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7509 18:03:55.855400 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7510 18:03:55.859152 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7511 18:03:55.865805 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7512 18:03:55.874933 [CA 0] Center 44 (14~75) winsize 62
7513 18:03:55.878257 [CA 1] Center 44 (14~75) winsize 62
7514 18:03:55.881642 [CA 2] Center 40 (11~69) winsize 59
7515 18:03:55.885137 [CA 3] Center 39 (10~69) winsize 60
7516 18:03:55.888764 [CA 4] Center 38 (8~68) winsize 61
7517 18:03:55.891825 [CA 5] Center 37 (7~67) winsize 61
7518 18:03:55.891906
7519 18:03:55.895396 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7520 18:03:55.895476
7521 18:03:55.898324 [CATrainingPosCal] consider 1 rank data
7522 18:03:55.901956 u2DelayCellTimex100 = 275/100 ps
7523 18:03:55.905292 CA0 delay=44 (14~75),Diff = 7 PI (24 cell)
7524 18:03:55.911982 CA1 delay=44 (14~75),Diff = 7 PI (24 cell)
7525 18:03:55.915153 CA2 delay=40 (11~69),Diff = 3 PI (10 cell)
7526 18:03:55.918584 CA3 delay=39 (10~69),Diff = 2 PI (7 cell)
7527 18:03:55.921972 CA4 delay=38 (8~68),Diff = 1 PI (3 cell)
7528 18:03:55.925123 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7529 18:03:55.925204
7530 18:03:55.928417 CA PerBit enable=1, Macro0, CA PI delay=37
7531 18:03:55.928497
7532 18:03:55.931772 [CBTSetCACLKResult] CA Dly = 37
7533 18:03:55.935037 CS Dly: 11 (0~42)
7534 18:03:55.938297 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7535 18:03:55.941593 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7536 18:03:55.941674 ==
7537 18:03:55.945158 Dram Type= 6, Freq= 0, CH_0, rank 1
7538 18:03:55.948407 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7539 18:03:55.951784 ==
7540 18:03:55.955172 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7541 18:03:55.958751 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7542 18:03:55.964880 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7543 18:03:55.971686 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7544 18:03:55.979157 [CA 0] Center 44 (14~75) winsize 62
7545 18:03:55.982030 [CA 1] Center 44 (14~75) winsize 62
7546 18:03:55.985642 [CA 2] Center 40 (11~69) winsize 59
7547 18:03:55.988873 [CA 3] Center 39 (10~69) winsize 60
7548 18:03:55.992396 [CA 4] Center 38 (9~68) winsize 60
7549 18:03:55.995872 [CA 5] Center 37 (7~67) winsize 61
7550 18:03:55.995954
7551 18:03:55.999066 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7552 18:03:55.999151
7553 18:03:56.002155 [CATrainingPosCal] consider 2 rank data
7554 18:03:56.005588 u2DelayCellTimex100 = 275/100 ps
7555 18:03:56.008919 CA0 delay=44 (14~75),Diff = 7 PI (24 cell)
7556 18:03:56.015672 CA1 delay=44 (14~75),Diff = 7 PI (24 cell)
7557 18:03:56.018852 CA2 delay=40 (11~69),Diff = 3 PI (10 cell)
7558 18:03:56.022423 CA3 delay=39 (10~69),Diff = 2 PI (7 cell)
7559 18:03:56.025351 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
7560 18:03:56.028838 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7561 18:03:56.028965
7562 18:03:56.032320 CA PerBit enable=1, Macro0, CA PI delay=37
7563 18:03:56.032403
7564 18:03:56.035453 [CBTSetCACLKResult] CA Dly = 37
7565 18:03:56.038792 CS Dly: 12 (0~44)
7566 18:03:56.042167 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7567 18:03:56.045302 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7568 18:03:56.045377
7569 18:03:56.048877 ----->DramcWriteLeveling(PI) begin...
7570 18:03:56.048952 ==
7571 18:03:56.052093 Dram Type= 6, Freq= 0, CH_0, rank 0
7572 18:03:56.058708 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7573 18:03:56.058786 ==
7574 18:03:56.062120 Write leveling (Byte 0): 33 => 33
7575 18:03:56.062192 Write leveling (Byte 1): 28 => 28
7576 18:03:56.065463 DramcWriteLeveling(PI) end<-----
7577 18:03:56.065543
7578 18:03:56.065606 ==
7579 18:03:56.068828 Dram Type= 6, Freq= 0, CH_0, rank 0
7580 18:03:56.075306 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7581 18:03:56.075388 ==
7582 18:03:56.078715 [Gating] SW mode calibration
7583 18:03:56.085288 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7584 18:03:56.088708 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7585 18:03:56.095534 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7586 18:03:56.098491 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7587 18:03:56.101958 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7588 18:03:56.108768 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7589 18:03:56.112001 1 4 16 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
7590 18:03:56.115411 1 4 20 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
7591 18:03:56.118758 1 4 24 | B1->B0 | 2e2e 3434 | 1 1 | (1 1) (1 1)
7592 18:03:56.125777 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7593 18:03:56.128778 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7594 18:03:56.131942 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7595 18:03:56.138712 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7596 18:03:56.142114 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7597 18:03:56.145498 1 5 16 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
7598 18:03:56.152469 1 5 20 | B1->B0 | 3434 2424 | 1 0 | (1 0) (0 0)
7599 18:03:56.155532 1 5 24 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
7600 18:03:56.158888 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7601 18:03:56.165377 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7602 18:03:56.168729 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7603 18:03:56.172007 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7604 18:03:56.179073 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7605 18:03:56.182910 1 6 16 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (0 0)
7606 18:03:56.185601 1 6 20 | B1->B0 | 2e2e 4646 | 0 0 | (0 0) (0 0)
7607 18:03:56.191952 1 6 24 | B1->B0 | 3d3d 4646 | 1 0 | (0 0) (0 0)
7608 18:03:56.195324 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7609 18:03:56.199181 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7610 18:03:56.205768 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7611 18:03:56.209090 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7612 18:03:56.212053 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7613 18:03:56.215371 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7614 18:03:56.222303 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7615 18:03:56.225710 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7616 18:03:56.228969 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7617 18:03:56.235741 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7618 18:03:56.239150 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7619 18:03:56.242365 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7620 18:03:56.249013 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7621 18:03:56.252961 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7622 18:03:56.256016 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7623 18:03:56.262655 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7624 18:03:56.266053 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7625 18:03:56.269516 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7626 18:03:56.272696 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7627 18:03:56.279177 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7628 18:03:56.282340 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7629 18:03:56.285952 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7630 18:03:56.292355 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7631 18:03:56.296119 Total UI for P1: 0, mck2ui 16
7632 18:03:56.299190 best dqsien dly found for B0: ( 1, 9, 16)
7633 18:03:56.302467 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7634 18:03:56.305972 Total UI for P1: 0, mck2ui 16
7635 18:03:56.309422 best dqsien dly found for B1: ( 1, 9, 18)
7636 18:03:56.313090 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
7637 18:03:56.315928 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7638 18:03:56.316008
7639 18:03:56.319452 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
7640 18:03:56.322810 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7641 18:03:56.326263 [Gating] SW calibration Done
7642 18:03:56.326368 ==
7643 18:03:56.329153 Dram Type= 6, Freq= 0, CH_0, rank 0
7644 18:03:56.335867 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7645 18:03:56.335950 ==
7646 18:03:56.336017 RX Vref Scan: 0
7647 18:03:56.336077
7648 18:03:56.339103 RX Vref 0 -> 0, step: 1
7649 18:03:56.339184
7650 18:03:56.342796 RX Delay 0 -> 252, step: 8
7651 18:03:56.346043 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
7652 18:03:56.349228 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
7653 18:03:56.352666 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7654 18:03:56.355650 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7655 18:03:56.362339 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7656 18:03:56.365631 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7657 18:03:56.369088 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
7658 18:03:56.372455 iDelay=200, Bit 7, Center 139 (88 ~ 191) 104
7659 18:03:56.375864 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7660 18:03:56.379356 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7661 18:03:56.386100 iDelay=200, Bit 10, Center 119 (64 ~ 175) 112
7662 18:03:56.389209 iDelay=200, Bit 11, Center 119 (72 ~ 167) 96
7663 18:03:56.392797 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7664 18:03:56.396084 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
7665 18:03:56.399446 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7666 18:03:56.405992 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7667 18:03:56.406075 ==
7668 18:03:56.409353 Dram Type= 6, Freq= 0, CH_0, rank 0
7669 18:03:56.413016 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7670 18:03:56.413098 ==
7671 18:03:56.413163 DQS Delay:
7672 18:03:56.416359 DQS0 = 0, DQS1 = 0
7673 18:03:56.416438 DQM Delay:
7674 18:03:56.419170 DQM0 = 132, DQM1 = 124
7675 18:03:56.419254 DQ Delay:
7676 18:03:56.422746 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
7677 18:03:56.426157 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =139
7678 18:03:56.429241 DQ8 =111, DQ9 =115, DQ10 =119, DQ11 =119
7679 18:03:56.432538 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
7680 18:03:56.432615
7681 18:03:56.435891
7682 18:03:56.435964 ==
7683 18:03:56.439408 Dram Type= 6, Freq= 0, CH_0, rank 0
7684 18:03:56.442423 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7685 18:03:56.442504 ==
7686 18:03:56.442569
7687 18:03:56.442628
7688 18:03:56.445849 TX Vref Scan disable
7689 18:03:56.445930 == TX Byte 0 ==
7690 18:03:56.452737 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7691 18:03:56.456023 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7692 18:03:56.456104 == TX Byte 1 ==
7693 18:03:56.462830 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7694 18:03:56.466378 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7695 18:03:56.466462 ==
7696 18:03:56.469796 Dram Type= 6, Freq= 0, CH_0, rank 0
7697 18:03:56.472598 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7698 18:03:56.472680 ==
7699 18:03:56.487551
7700 18:03:56.490835 TX Vref early break, caculate TX vref
7701 18:03:56.494158 TX Vref=16, minBit 4, minWin=21, winSum=360
7702 18:03:56.497580 TX Vref=18, minBit 0, minWin=22, winSum=376
7703 18:03:56.500810 TX Vref=20, minBit 0, minWin=22, winSum=373
7704 18:03:56.504276 TX Vref=22, minBit 3, minWin=22, winSum=387
7705 18:03:56.507830 TX Vref=24, minBit 4, minWin=22, winSum=399
7706 18:03:56.514536 TX Vref=26, minBit 0, minWin=24, winSum=409
7707 18:03:56.517493 TX Vref=28, minBit 4, minWin=24, winSum=414
7708 18:03:56.520949 TX Vref=30, minBit 7, minWin=24, winSum=417
7709 18:03:56.524268 TX Vref=32, minBit 4, minWin=23, winSum=413
7710 18:03:56.527452 TX Vref=34, minBit 0, minWin=24, winSum=401
7711 18:03:56.530840 TX Vref=36, minBit 0, minWin=23, winSum=388
7712 18:03:56.537570 [TxChooseVref] Worse bit 7, Min win 24, Win sum 417, Final Vref 30
7713 18:03:56.537680
7714 18:03:56.540884 Final TX Range 0 Vref 30
7715 18:03:56.541015
7716 18:03:56.541096 ==
7717 18:03:56.544162 Dram Type= 6, Freq= 0, CH_0, rank 0
7718 18:03:56.547314 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7719 18:03:56.547397 ==
7720 18:03:56.547462
7721 18:03:56.547522
7722 18:03:56.551190 TX Vref Scan disable
7723 18:03:56.557299 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7724 18:03:56.557385 == TX Byte 0 ==
7725 18:03:56.560874 u2DelayCellOfst[0]=14 cells (4 PI)
7726 18:03:56.563928 u2DelayCellOfst[1]=17 cells (5 PI)
7727 18:03:56.567798 u2DelayCellOfst[2]=10 cells (3 PI)
7728 18:03:56.570790 u2DelayCellOfst[3]=10 cells (3 PI)
7729 18:03:56.574530 u2DelayCellOfst[4]=10 cells (3 PI)
7730 18:03:56.577655 u2DelayCellOfst[5]=0 cells (0 PI)
7731 18:03:56.580566 u2DelayCellOfst[6]=17 cells (5 PI)
7732 18:03:56.584256 u2DelayCellOfst[7]=17 cells (5 PI)
7733 18:03:56.587537 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7734 18:03:56.590872 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7735 18:03:56.594227 == TX Byte 1 ==
7736 18:03:56.594322 u2DelayCellOfst[8]=0 cells (0 PI)
7737 18:03:56.597601 u2DelayCellOfst[9]=0 cells (0 PI)
7738 18:03:56.601062 u2DelayCellOfst[10]=7 cells (2 PI)
7739 18:03:56.604560 u2DelayCellOfst[11]=0 cells (0 PI)
7740 18:03:56.607787 u2DelayCellOfst[12]=14 cells (4 PI)
7741 18:03:56.610901 u2DelayCellOfst[13]=14 cells (4 PI)
7742 18:03:56.614490 u2DelayCellOfst[14]=17 cells (5 PI)
7743 18:03:56.617782 u2DelayCellOfst[15]=14 cells (4 PI)
7744 18:03:56.620875 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7745 18:03:56.627961 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7746 18:03:56.628046 DramC Write-DBI on
7747 18:03:56.628111 ==
7748 18:03:56.630810 Dram Type= 6, Freq= 0, CH_0, rank 0
7749 18:03:56.634071 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7750 18:03:56.637577 ==
7751 18:03:56.637658
7752 18:03:56.637722
7753 18:03:56.637781 TX Vref Scan disable
7754 18:03:56.641066 == TX Byte 0 ==
7755 18:03:56.644555 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
7756 18:03:56.647702 == TX Byte 1 ==
7757 18:03:56.650896 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
7758 18:03:56.654181 DramC Write-DBI off
7759 18:03:56.654262
7760 18:03:56.654326 [DATLAT]
7761 18:03:56.654385 Freq=1600, CH0 RK0
7762 18:03:56.654443
7763 18:03:56.657831 DATLAT Default: 0xf
7764 18:03:56.657941 0, 0xFFFF, sum = 0
7765 18:03:56.661070 1, 0xFFFF, sum = 0
7766 18:03:56.664187 2, 0xFFFF, sum = 0
7767 18:03:56.664269 3, 0xFFFF, sum = 0
7768 18:03:56.667554 4, 0xFFFF, sum = 0
7769 18:03:56.667637 5, 0xFFFF, sum = 0
7770 18:03:56.670675 6, 0xFFFF, sum = 0
7771 18:03:56.670757 7, 0xFFFF, sum = 0
7772 18:03:56.674080 8, 0xFFFF, sum = 0
7773 18:03:56.674164 9, 0xFFFF, sum = 0
7774 18:03:56.677372 10, 0xFFFF, sum = 0
7775 18:03:56.677457 11, 0xFFFF, sum = 0
7776 18:03:56.680696 12, 0xFFFF, sum = 0
7777 18:03:56.680778 13, 0xFFFF, sum = 0
7778 18:03:56.684237 14, 0x0, sum = 1
7779 18:03:56.684318 15, 0x0, sum = 2
7780 18:03:56.687430 16, 0x0, sum = 3
7781 18:03:56.687514 17, 0x0, sum = 4
7782 18:03:56.690875 best_step = 15
7783 18:03:56.690957
7784 18:03:56.691021 ==
7785 18:03:56.694290 Dram Type= 6, Freq= 0, CH_0, rank 0
7786 18:03:56.697780 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7787 18:03:56.697931 ==
7788 18:03:56.698025 RX Vref Scan: 1
7789 18:03:56.700954
7790 18:03:56.701081 Set Vref Range= 24 -> 127
7791 18:03:56.701149
7792 18:03:56.704544 RX Vref 24 -> 127, step: 1
7793 18:03:56.704667
7794 18:03:56.707914 RX Delay 11 -> 252, step: 4
7795 18:03:56.708035
7796 18:03:56.711043 Set Vref, RX VrefLevel [Byte0]: 24
7797 18:03:56.714494 [Byte1]: 24
7798 18:03:56.714739
7799 18:03:56.717691 Set Vref, RX VrefLevel [Byte0]: 25
7800 18:03:56.721129 [Byte1]: 25
7801 18:03:56.721233
7802 18:03:56.724153 Set Vref, RX VrefLevel [Byte0]: 26
7803 18:03:56.727682 [Byte1]: 26
7804 18:03:56.731582
7805 18:03:56.731757 Set Vref, RX VrefLevel [Byte0]: 27
7806 18:03:56.734745 [Byte1]: 27
7807 18:03:56.739094
7808 18:03:56.739247 Set Vref, RX VrefLevel [Byte0]: 28
7809 18:03:56.742310 [Byte1]: 28
7810 18:03:56.746360
7811 18:03:56.746542 Set Vref, RX VrefLevel [Byte0]: 29
7812 18:03:56.749993 [Byte1]: 29
7813 18:03:56.754066
7814 18:03:56.754211 Set Vref, RX VrefLevel [Byte0]: 30
7815 18:03:56.757554 [Byte1]: 30
7816 18:03:56.761918
7817 18:03:56.762031 Set Vref, RX VrefLevel [Byte0]: 31
7818 18:03:56.764951 [Byte1]: 31
7819 18:03:56.769158
7820 18:03:56.769260 Set Vref, RX VrefLevel [Byte0]: 32
7821 18:03:56.772941 [Byte1]: 32
7822 18:03:56.777256
7823 18:03:56.777341 Set Vref, RX VrefLevel [Byte0]: 33
7824 18:03:56.780631 [Byte1]: 33
7825 18:03:56.784607
7826 18:03:56.784715 Set Vref, RX VrefLevel [Byte0]: 34
7827 18:03:56.788051 [Byte1]: 34
7828 18:03:56.792091
7829 18:03:56.792176 Set Vref, RX VrefLevel [Byte0]: 35
7830 18:03:56.795544 [Byte1]: 35
7831 18:03:56.800101
7832 18:03:56.800186 Set Vref, RX VrefLevel [Byte0]: 36
7833 18:03:56.803441 [Byte1]: 36
7834 18:03:56.807656
7835 18:03:56.807745 Set Vref, RX VrefLevel [Byte0]: 37
7836 18:03:56.810693 [Byte1]: 37
7837 18:03:56.815116
7838 18:03:56.815197 Set Vref, RX VrefLevel [Byte0]: 38
7839 18:03:56.818570 [Byte1]: 38
7840 18:03:56.822705
7841 18:03:56.822796 Set Vref, RX VrefLevel [Byte0]: 39
7842 18:03:56.825878 [Byte1]: 39
7843 18:03:56.830717
7844 18:03:56.830807 Set Vref, RX VrefLevel [Byte0]: 40
7845 18:03:56.833533 [Byte1]: 40
7846 18:03:56.838119
7847 18:03:56.838193 Set Vref, RX VrefLevel [Byte0]: 41
7848 18:03:56.841408 [Byte1]: 41
7849 18:03:56.845759
7850 18:03:56.845843 Set Vref, RX VrefLevel [Byte0]: 42
7851 18:03:56.849080 [Byte1]: 42
7852 18:03:56.853197
7853 18:03:56.853280 Set Vref, RX VrefLevel [Byte0]: 43
7854 18:03:56.856662 [Byte1]: 43
7855 18:03:56.860693
7856 18:03:56.860776 Set Vref, RX VrefLevel [Byte0]: 44
7857 18:03:56.864036 [Byte1]: 44
7858 18:03:56.868445
7859 18:03:56.868531 Set Vref, RX VrefLevel [Byte0]: 45
7860 18:03:56.871536 [Byte1]: 45
7861 18:03:56.875926
7862 18:03:56.876010 Set Vref, RX VrefLevel [Byte0]: 46
7863 18:03:56.879243 [Byte1]: 46
7864 18:03:56.883424
7865 18:03:56.883513 Set Vref, RX VrefLevel [Byte0]: 47
7866 18:03:56.887002 [Byte1]: 47
7867 18:03:56.891148
7868 18:03:56.891230 Set Vref, RX VrefLevel [Byte0]: 48
7869 18:03:56.894512 [Byte1]: 48
7870 18:03:56.898654
7871 18:03:56.898736 Set Vref, RX VrefLevel [Byte0]: 49
7872 18:03:56.902084 [Byte1]: 49
7873 18:03:56.906515
7874 18:03:56.906629 Set Vref, RX VrefLevel [Byte0]: 50
7875 18:03:56.909598 [Byte1]: 50
7876 18:03:56.914258
7877 18:03:56.914344 Set Vref, RX VrefLevel [Byte0]: 51
7878 18:03:56.917068 [Byte1]: 51
7879 18:03:56.921789
7880 18:03:56.921871 Set Vref, RX VrefLevel [Byte0]: 52
7881 18:03:56.925351 [Byte1]: 52
7882 18:03:56.929349
7883 18:03:56.929456 Set Vref, RX VrefLevel [Byte0]: 53
7884 18:03:56.932708 [Byte1]: 53
7885 18:03:56.937323
7886 18:03:56.937404 Set Vref, RX VrefLevel [Byte0]: 54
7887 18:03:56.940086 [Byte1]: 54
7888 18:03:56.944700
7889 18:03:56.944782 Set Vref, RX VrefLevel [Byte0]: 55
7890 18:03:56.948216 [Byte1]: 55
7891 18:03:56.952114
7892 18:03:56.952207 Set Vref, RX VrefLevel [Byte0]: 56
7893 18:03:56.955514 [Byte1]: 56
7894 18:03:56.959770
7895 18:03:56.959881 Set Vref, RX VrefLevel [Byte0]: 57
7896 18:03:56.962880 [Byte1]: 57
7897 18:03:56.967163
7898 18:03:56.967253 Set Vref, RX VrefLevel [Byte0]: 58
7899 18:03:56.970462 [Byte1]: 58
7900 18:03:56.975085
7901 18:03:56.975161 Set Vref, RX VrefLevel [Byte0]: 59
7902 18:03:56.978332 [Byte1]: 59
7903 18:03:56.982820
7904 18:03:56.982901 Set Vref, RX VrefLevel [Byte0]: 60
7905 18:03:56.985825 [Byte1]: 60
7906 18:03:56.990116
7907 18:03:56.990204 Set Vref, RX VrefLevel [Byte0]: 61
7908 18:03:56.993703 [Byte1]: 61
7909 18:03:56.997888
7910 18:03:56.997969 Set Vref, RX VrefLevel [Byte0]: 62
7911 18:03:57.001121 [Byte1]: 62
7912 18:03:57.005543
7913 18:03:57.005631 Set Vref, RX VrefLevel [Byte0]: 63
7914 18:03:57.008913 [Byte1]: 63
7915 18:03:57.013214
7916 18:03:57.013300 Set Vref, RX VrefLevel [Byte0]: 64
7917 18:03:57.016570 [Byte1]: 64
7918 18:03:57.020692
7919 18:03:57.020776 Set Vref, RX VrefLevel [Byte0]: 65
7920 18:03:57.023791 [Byte1]: 65
7921 18:03:57.028326
7922 18:03:57.028411 Set Vref, RX VrefLevel [Byte0]: 66
7923 18:03:57.031912 [Byte1]: 66
7924 18:03:57.035975
7925 18:03:57.036061 Set Vref, RX VrefLevel [Byte0]: 67
7926 18:03:57.039523 [Byte1]: 67
7927 18:03:57.043348
7928 18:03:57.043436 Set Vref, RX VrefLevel [Byte0]: 68
7929 18:03:57.046941 [Byte1]: 68
7930 18:03:57.050830
7931 18:03:57.050911 Set Vref, RX VrefLevel [Byte0]: 69
7932 18:03:57.054262 [Byte1]: 69
7933 18:03:57.058485
7934 18:03:57.058567 Set Vref, RX VrefLevel [Byte0]: 70
7935 18:03:57.061870 [Byte1]: 70
7936 18:03:57.066391
7937 18:03:57.066472 Set Vref, RX VrefLevel [Byte0]: 71
7938 18:03:57.069955 [Byte1]: 71
7939 18:03:57.073912
7940 18:03:57.073994 Set Vref, RX VrefLevel [Byte0]: 72
7941 18:03:57.077143 [Byte1]: 72
7942 18:03:57.081813
7943 18:03:57.081889 Set Vref, RX VrefLevel [Byte0]: 73
7944 18:03:57.084964 [Byte1]: 73
7945 18:03:57.089217
7946 18:03:57.089339 Set Vref, RX VrefLevel [Byte0]: 74
7947 18:03:57.123411 [Byte1]: 74
7948 18:03:57.124158
7949 18:03:57.124463 Set Vref, RX VrefLevel [Byte0]: 75
7950 18:03:57.124732 [Byte1]: 75
7951 18:03:57.125037
7952 18:03:57.125361 Set Vref, RX VrefLevel [Byte0]: 76
7953 18:03:57.125762 [Byte1]: 76
7954 18:03:57.126130
7955 18:03:57.126506 Final RX Vref Byte 0 = 57 to rank0
7956 18:03:57.126873 Final RX Vref Byte 1 = 60 to rank0
7957 18:03:57.127267 Final RX Vref Byte 0 = 57 to rank1
7958 18:03:57.127667 Final RX Vref Byte 1 = 60 to rank1==
7959 18:03:57.128112 Dram Type= 6, Freq= 0, CH_0, rank 0
7960 18:03:57.132456 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7961 18:03:57.133048 ==
7962 18:03:57.133464 DQS Delay:
7963 18:03:57.133807 DQS0 = 0, DQS1 = 0
7964 18:03:57.135960 DQM Delay:
7965 18:03:57.136430 DQM0 = 129, DQM1 = 122
7966 18:03:57.139535 DQ Delay:
7967 18:03:57.142258 DQ0 =128, DQ1 =132, DQ2 =126, DQ3 =126
7968 18:03:57.145857 DQ4 =132, DQ5 =120, DQ6 =136, DQ7 =138
7969 18:03:57.149048 DQ8 =110, DQ9 =110, DQ10 =122, DQ11 =118
7970 18:03:57.152154 DQ12 =128, DQ13 =126, DQ14 =132, DQ15 =132
7971 18:03:57.152363
7972 18:03:57.152573
7973 18:03:57.152770
7974 18:03:57.155492 [DramC_TX_OE_Calibration] TA2
7975 18:03:57.159038 Original DQ_B0 (3 6) =30, OEN = 27
7976 18:03:57.161926 Original DQ_B1 (3 6) =30, OEN = 27
7977 18:03:57.165301 24, 0x0, End_B0=24 End_B1=24
7978 18:03:57.165558 25, 0x0, End_B0=25 End_B1=25
7979 18:03:57.168745 26, 0x0, End_B0=26 End_B1=26
7980 18:03:57.172038 27, 0x0, End_B0=27 End_B1=27
7981 18:03:57.175617 28, 0x0, End_B0=28 End_B1=28
7982 18:03:57.175795 29, 0x0, End_B0=29 End_B1=29
7983 18:03:57.179023 30, 0x0, End_B0=30 End_B1=30
7984 18:03:57.182368 31, 0x5151, End_B0=30 End_B1=30
7985 18:03:57.185646 Byte0 end_step=30 best_step=27
7986 18:03:57.188967 Byte1 end_step=30 best_step=27
7987 18:03:57.192501 Byte0 TX OE(2T, 0.5T) = (3, 3)
7988 18:03:57.192628 Byte1 TX OE(2T, 0.5T) = (3, 3)
7989 18:03:57.192700
7990 18:03:57.192762
7991 18:03:57.202430 [DQSOSCAuto] RK0, (LSB)MR18= 0x1004, (MSB)MR19= 0x303, tDQSOscB0 = 408 ps tDQSOscB1 = 401 ps
7992 18:03:57.205378 CH0 RK0: MR19=303, MR18=1004
7993 18:03:57.209018 CH0_RK0: MR19=0x303, MR18=0x1004, DQSOSC=401, MR23=63, INC=22, DEC=15
7994 18:03:57.211983
7995 18:03:57.215372 ----->DramcWriteLeveling(PI) begin...
7996 18:03:57.215455 ==
7997 18:03:57.218811 Dram Type= 6, Freq= 0, CH_0, rank 1
7998 18:03:57.222189 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7999 18:03:57.222273 ==
8000 18:03:57.225601 Write leveling (Byte 0): 33 => 33
8001 18:03:57.228919 Write leveling (Byte 1): 26 => 26
8002 18:03:57.232451 DramcWriteLeveling(PI) end<-----
8003 18:03:57.232587
8004 18:03:57.232673 ==
8005 18:03:57.235642 Dram Type= 6, Freq= 0, CH_0, rank 1
8006 18:03:57.238848 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8007 18:03:57.238974 ==
8008 18:03:57.241911 [Gating] SW mode calibration
8009 18:03:57.248861 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8010 18:03:57.255743 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8011 18:03:57.258826 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8012 18:03:57.262015 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8013 18:03:57.269184 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8014 18:03:57.272379 1 4 12 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
8015 18:03:57.275695 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8016 18:03:57.281941 1 4 20 | B1->B0 | 2929 3434 | 0 1 | (0 0) (1 1)
8017 18:03:57.285203 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8018 18:03:57.288924 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8019 18:03:57.291994 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8020 18:03:57.298740 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8021 18:03:57.302391 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8022 18:03:57.305324 1 5 12 | B1->B0 | 3434 2c2c | 1 0 | (1 1) (0 1)
8023 18:03:57.311856 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
8024 18:03:57.315303 1 5 20 | B1->B0 | 2e2e 2323 | 0 0 | (0 1) (0 0)
8025 18:03:57.318932 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8026 18:03:57.325244 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8027 18:03:57.328867 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8028 18:03:57.332341 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8029 18:03:57.338704 1 6 8 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
8030 18:03:57.342139 1 6 12 | B1->B0 | 2323 3f3f | 0 0 | (0 0) (0 0)
8031 18:03:57.345181 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8032 18:03:57.352030 1 6 20 | B1->B0 | 3636 4646 | 1 0 | (0 0) (0 0)
8033 18:03:57.355445 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8034 18:03:57.358594 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8035 18:03:57.365520 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8036 18:03:57.368939 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8037 18:03:57.371753 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8038 18:03:57.378648 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8039 18:03:57.382192 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8040 18:03:57.385374 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8041 18:03:57.388926 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8042 18:03:57.395471 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8043 18:03:57.399021 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8044 18:03:57.401837 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8045 18:03:57.408513 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8046 18:03:57.412225 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8047 18:03:57.415533 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8048 18:03:57.421873 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8049 18:03:57.425080 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8050 18:03:57.428506 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8051 18:03:57.435287 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8052 18:03:57.438740 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8053 18:03:57.442246 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8054 18:03:57.448491 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8055 18:03:57.451836 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8056 18:03:57.455550 Total UI for P1: 0, mck2ui 16
8057 18:03:57.458724 best dqsien dly found for B0: ( 1, 9, 10)
8058 18:03:57.462245 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8059 18:03:57.468747 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8060 18:03:57.471855 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8061 18:03:57.475413 Total UI for P1: 0, mck2ui 16
8062 18:03:57.478822 best dqsien dly found for B1: ( 1, 9, 20)
8063 18:03:57.481795 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8064 18:03:57.485830 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
8065 18:03:57.485907
8066 18:03:57.488622 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8067 18:03:57.491939 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
8068 18:03:57.495357 [Gating] SW calibration Done
8069 18:03:57.495442 ==
8070 18:03:57.498633 Dram Type= 6, Freq= 0, CH_0, rank 1
8071 18:03:57.501974 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8072 18:03:57.502058 ==
8073 18:03:57.505491 RX Vref Scan: 0
8074 18:03:57.505575
8075 18:03:57.508559 RX Vref 0 -> 0, step: 1
8076 18:03:57.508641
8077 18:03:57.508705 RX Delay 0 -> 252, step: 8
8078 18:03:57.515211 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8079 18:03:57.518660 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8080 18:03:57.521900 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8081 18:03:57.525342 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8082 18:03:57.528770 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8083 18:03:57.531927 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8084 18:03:57.538953 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8085 18:03:57.542522 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8086 18:03:57.545368 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8087 18:03:57.548859 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8088 18:03:57.552447 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8089 18:03:57.559389 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8090 18:03:57.562261 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8091 18:03:57.565539 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8092 18:03:57.568920 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8093 18:03:57.575625 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8094 18:03:57.575712 ==
8095 18:03:57.579034 Dram Type= 6, Freq= 0, CH_0, rank 1
8096 18:03:57.582377 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8097 18:03:57.582459 ==
8098 18:03:57.582523 DQS Delay:
8099 18:03:57.585763 DQS0 = 0, DQS1 = 0
8100 18:03:57.585844 DQM Delay:
8101 18:03:57.588762 DQM0 = 131, DQM1 = 124
8102 18:03:57.588842 DQ Delay:
8103 18:03:57.592396 DQ0 =131, DQ1 =131, DQ2 =127, DQ3 =131
8104 18:03:57.595677 DQ4 =131, DQ5 =119, DQ6 =139, DQ7 =139
8105 18:03:57.599026 DQ8 =119, DQ9 =111, DQ10 =123, DQ11 =119
8106 18:03:57.602385 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =131
8107 18:03:57.602465
8108 18:03:57.602528
8109 18:03:57.602592 ==
8110 18:03:57.605559 Dram Type= 6, Freq= 0, CH_0, rank 1
8111 18:03:57.612081 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8112 18:03:57.612171 ==
8113 18:03:57.612236
8114 18:03:57.612294
8115 18:03:57.612351 TX Vref Scan disable
8116 18:03:57.615857 == TX Byte 0 ==
8117 18:03:57.619382 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8118 18:03:57.625920 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8119 18:03:57.626023 == TX Byte 1 ==
8120 18:03:57.628938 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8121 18:03:57.636181 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8122 18:03:57.636289 ==
8123 18:03:57.639352 Dram Type= 6, Freq= 0, CH_0, rank 1
8124 18:03:57.642164 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8125 18:03:57.642236 ==
8126 18:03:57.657283
8127 18:03:57.660269 TX Vref early break, caculate TX vref
8128 18:03:57.663600 TX Vref=16, minBit 4, minWin=22, winSum=368
8129 18:03:57.666876 TX Vref=18, minBit 1, minWin=23, winSum=374
8130 18:03:57.670237 TX Vref=20, minBit 1, minWin=23, winSum=386
8131 18:03:57.673666 TX Vref=22, minBit 1, minWin=24, winSum=392
8132 18:03:57.676965 TX Vref=24, minBit 9, minWin=23, winSum=400
8133 18:03:57.683281 TX Vref=26, minBit 0, minWin=25, winSum=412
8134 18:03:57.686765 TX Vref=28, minBit 0, minWin=25, winSum=413
8135 18:03:57.690114 TX Vref=30, minBit 1, minWin=25, winSum=415
8136 18:03:57.693367 TX Vref=32, minBit 0, minWin=25, winSum=409
8137 18:03:57.696865 TX Vref=34, minBit 1, minWin=24, winSum=398
8138 18:03:57.700065 TX Vref=36, minBit 2, minWin=23, winSum=393
8139 18:03:57.707021 [TxChooseVref] Worse bit 1, Min win 25, Win sum 415, Final Vref 30
8140 18:03:57.707109
8141 18:03:57.710563 Final TX Range 0 Vref 30
8142 18:03:57.710646
8143 18:03:57.710750 ==
8144 18:03:57.713261 Dram Type= 6, Freq= 0, CH_0, rank 1
8145 18:03:57.716882 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8146 18:03:57.716964 ==
8147 18:03:57.717065
8148 18:03:57.717125
8149 18:03:57.720107 TX Vref Scan disable
8150 18:03:57.726673 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8151 18:03:57.726754 == TX Byte 0 ==
8152 18:03:57.729968 u2DelayCellOfst[0]=14 cells (4 PI)
8153 18:03:57.733798 u2DelayCellOfst[1]=17 cells (5 PI)
8154 18:03:57.736745 u2DelayCellOfst[2]=10 cells (3 PI)
8155 18:03:57.740142 u2DelayCellOfst[3]=10 cells (3 PI)
8156 18:03:57.743646 u2DelayCellOfst[4]=10 cells (3 PI)
8157 18:03:57.747171 u2DelayCellOfst[5]=0 cells (0 PI)
8158 18:03:57.750020 u2DelayCellOfst[6]=21 cells (6 PI)
8159 18:03:57.753777 u2DelayCellOfst[7]=21 cells (6 PI)
8160 18:03:57.757016 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
8161 18:03:57.760041 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8162 18:03:57.763341 == TX Byte 1 ==
8163 18:03:57.766897 u2DelayCellOfst[8]=0 cells (0 PI)
8164 18:03:57.767086 u2DelayCellOfst[9]=0 cells (0 PI)
8165 18:03:57.770091 u2DelayCellOfst[10]=7 cells (2 PI)
8166 18:03:57.773457 u2DelayCellOfst[11]=0 cells (0 PI)
8167 18:03:57.776746 u2DelayCellOfst[12]=10 cells (3 PI)
8168 18:03:57.780242 u2DelayCellOfst[13]=10 cells (3 PI)
8169 18:03:57.783520 u2DelayCellOfst[14]=14 cells (4 PI)
8170 18:03:57.786840 u2DelayCellOfst[15]=10 cells (3 PI)
8171 18:03:57.790374 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8172 18:03:57.796876 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8173 18:03:57.796960 DramC Write-DBI on
8174 18:03:57.797051 ==
8175 18:03:57.800088 Dram Type= 6, Freq= 0, CH_0, rank 1
8176 18:03:57.803639 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8177 18:03:57.806833 ==
8178 18:03:57.806916
8179 18:03:57.806980
8180 18:03:57.807040 TX Vref Scan disable
8181 18:03:57.810395 == TX Byte 0 ==
8182 18:03:57.813821 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
8183 18:03:57.817187 == TX Byte 1 ==
8184 18:03:57.820562 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8185 18:03:57.820647 DramC Write-DBI off
8186 18:03:57.823585
8187 18:03:57.823665 [DATLAT]
8188 18:03:57.823728 Freq=1600, CH0 RK1
8189 18:03:57.823787
8190 18:03:57.827087 DATLAT Default: 0xf
8191 18:03:57.827167 0, 0xFFFF, sum = 0
8192 18:03:57.830271 1, 0xFFFF, sum = 0
8193 18:03:57.830381 2, 0xFFFF, sum = 0
8194 18:03:57.833509 3, 0xFFFF, sum = 0
8195 18:03:57.837437 4, 0xFFFF, sum = 0
8196 18:03:57.837519 5, 0xFFFF, sum = 0
8197 18:03:57.840324 6, 0xFFFF, sum = 0
8198 18:03:57.840414 7, 0xFFFF, sum = 0
8199 18:03:57.844012 8, 0xFFFF, sum = 0
8200 18:03:57.844093 9, 0xFFFF, sum = 0
8201 18:03:57.846823 10, 0xFFFF, sum = 0
8202 18:03:57.846904 11, 0xFFFF, sum = 0
8203 18:03:57.850305 12, 0xFFFF, sum = 0
8204 18:03:57.850386 13, 0xFFFF, sum = 0
8205 18:03:57.853536 14, 0x0, sum = 1
8206 18:03:57.853617 15, 0x0, sum = 2
8207 18:03:57.857000 16, 0x0, sum = 3
8208 18:03:57.857096 17, 0x0, sum = 4
8209 18:03:57.860439 best_step = 15
8210 18:03:57.860519
8211 18:03:57.860581 ==
8212 18:03:57.863839 Dram Type= 6, Freq= 0, CH_0, rank 1
8213 18:03:57.866784 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8214 18:03:57.866871 ==
8215 18:03:57.866939 RX Vref Scan: 0
8216 18:03:57.866999
8217 18:03:57.870320 RX Vref 0 -> 0, step: 1
8218 18:03:57.870457
8219 18:03:57.874105 RX Delay 11 -> 252, step: 4
8220 18:03:57.876951 iDelay=191, Bit 0, Center 126 (71 ~ 182) 112
8221 18:03:57.883423 iDelay=191, Bit 1, Center 130 (75 ~ 186) 112
8222 18:03:57.886966 iDelay=191, Bit 2, Center 122 (67 ~ 178) 112
8223 18:03:57.890174 iDelay=191, Bit 3, Center 126 (71 ~ 182) 112
8224 18:03:57.893598 iDelay=191, Bit 4, Center 124 (71 ~ 178) 108
8225 18:03:57.897136 iDelay=191, Bit 5, Center 114 (59 ~ 170) 112
8226 18:03:57.903395 iDelay=191, Bit 6, Center 134 (79 ~ 190) 112
8227 18:03:57.906883 iDelay=191, Bit 7, Center 134 (79 ~ 190) 112
8228 18:03:57.910672 iDelay=191, Bit 8, Center 112 (59 ~ 166) 108
8229 18:03:57.913684 iDelay=191, Bit 9, Center 110 (55 ~ 166) 112
8230 18:03:57.916723 iDelay=191, Bit 10, Center 122 (67 ~ 178) 112
8231 18:03:57.923245 iDelay=191, Bit 11, Center 116 (63 ~ 170) 108
8232 18:03:57.926810 iDelay=191, Bit 12, Center 126 (75 ~ 178) 104
8233 18:03:57.930209 iDelay=191, Bit 13, Center 128 (75 ~ 182) 108
8234 18:03:57.933394 iDelay=191, Bit 14, Center 134 (79 ~ 190) 112
8235 18:03:57.936609 iDelay=191, Bit 15, Center 132 (79 ~ 186) 108
8236 18:03:57.939986 ==
8237 18:03:57.943222 Dram Type= 6, Freq= 0, CH_0, rank 1
8238 18:03:57.946731 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8239 18:03:57.946812 ==
8240 18:03:57.946904 DQS Delay:
8241 18:03:57.950027 DQS0 = 0, DQS1 = 0
8242 18:03:57.950106 DQM Delay:
8243 18:03:57.953335 DQM0 = 126, DQM1 = 122
8244 18:03:57.953414 DQ Delay:
8245 18:03:57.956756 DQ0 =126, DQ1 =130, DQ2 =122, DQ3 =126
8246 18:03:57.960225 DQ4 =124, DQ5 =114, DQ6 =134, DQ7 =134
8247 18:03:57.963173 DQ8 =112, DQ9 =110, DQ10 =122, DQ11 =116
8248 18:03:57.966658 DQ12 =126, DQ13 =128, DQ14 =134, DQ15 =132
8249 18:03:57.966738
8250 18:03:57.966805
8251 18:03:57.966864
8252 18:03:57.969973 [DramC_TX_OE_Calibration] TA2
8253 18:03:57.973422 Original DQ_B0 (3 6) =30, OEN = 27
8254 18:03:57.976851 Original DQ_B1 (3 6) =30, OEN = 27
8255 18:03:57.979982 24, 0x0, End_B0=24 End_B1=24
8256 18:03:57.983529 25, 0x0, End_B0=25 End_B1=25
8257 18:03:57.983610 26, 0x0, End_B0=26 End_B1=26
8258 18:03:57.986756 27, 0x0, End_B0=27 End_B1=27
8259 18:03:57.990113 28, 0x0, End_B0=28 End_B1=28
8260 18:03:57.993459 29, 0x0, End_B0=29 End_B1=29
8261 18:03:57.993541 30, 0x0, End_B0=30 End_B1=30
8262 18:03:57.996359 31, 0x4141, End_B0=30 End_B1=30
8263 18:03:57.999854 Byte0 end_step=30 best_step=27
8264 18:03:58.003226 Byte1 end_step=30 best_step=27
8265 18:03:58.006292 Byte0 TX OE(2T, 0.5T) = (3, 3)
8266 18:03:58.009725 Byte1 TX OE(2T, 0.5T) = (3, 3)
8267 18:03:58.009833
8268 18:03:58.009899
8269 18:03:58.016557 [DQSOSCAuto] RK1, (LSB)MR18= 0x1409, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 399 ps
8270 18:03:58.019579 CH0 RK1: MR19=303, MR18=1409
8271 18:03:58.026618 CH0_RK1: MR19=0x303, MR18=0x1409, DQSOSC=399, MR23=63, INC=23, DEC=15
8272 18:03:58.029850 [RxdqsGatingPostProcess] freq 1600
8273 18:03:58.032902 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8274 18:03:58.036354 best DQS0 dly(2T, 0.5T) = (1, 1)
8275 18:03:58.040123 best DQS1 dly(2T, 0.5T) = (1, 1)
8276 18:03:58.043420 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8277 18:03:58.046533 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8278 18:03:58.049672 best DQS0 dly(2T, 0.5T) = (1, 1)
8279 18:03:58.053169 best DQS1 dly(2T, 0.5T) = (1, 1)
8280 18:03:58.056569 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8281 18:03:58.059743 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8282 18:03:58.063222 Pre-setting of DQS Precalculation
8283 18:03:58.066532 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8284 18:03:58.066613 ==
8285 18:03:58.069945 Dram Type= 6, Freq= 0, CH_1, rank 0
8286 18:03:58.073364 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8287 18:03:58.076180 ==
8288 18:03:58.079766 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8289 18:03:58.082971 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8290 18:03:58.089641 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8291 18:03:58.096031 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8292 18:03:58.103441 [CA 0] Center 42 (13~71) winsize 59
8293 18:03:58.107030 [CA 1] Center 42 (13~71) winsize 59
8294 18:03:58.110473 [CA 2] Center 37 (8~66) winsize 59
8295 18:03:58.113843 [CA 3] Center 36 (7~65) winsize 59
8296 18:03:58.116672 [CA 4] Center 36 (7~66) winsize 60
8297 18:03:58.120181 [CA 5] Center 36 (7~66) winsize 60
8298 18:03:58.120260
8299 18:03:58.123749 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8300 18:03:58.123828
8301 18:03:58.127239 [CATrainingPosCal] consider 1 rank data
8302 18:03:58.130624 u2DelayCellTimex100 = 275/100 ps
8303 18:03:58.133540 CA0 delay=42 (13~71),Diff = 6 PI (21 cell)
8304 18:03:58.139895 CA1 delay=42 (13~71),Diff = 6 PI (21 cell)
8305 18:03:58.143500 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8306 18:03:58.146787 CA3 delay=36 (7~65),Diff = 0 PI (0 cell)
8307 18:03:58.150469 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
8308 18:03:58.153162 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8309 18:03:58.153248
8310 18:03:58.156865 CA PerBit enable=1, Macro0, CA PI delay=36
8311 18:03:58.157006
8312 18:03:58.159897 [CBTSetCACLKResult] CA Dly = 36
8313 18:03:58.163206 CS Dly: 9 (0~40)
8314 18:03:58.166630 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8315 18:03:58.169797 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8316 18:03:58.169876 ==
8317 18:03:58.173370 Dram Type= 6, Freq= 0, CH_1, rank 1
8318 18:03:58.176692 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8319 18:03:58.176771 ==
8320 18:03:58.183300 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8321 18:03:58.186814 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8322 18:03:58.193310 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8323 18:03:58.196714 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8324 18:03:58.206270 [CA 0] Center 43 (14~72) winsize 59
8325 18:03:58.210206 [CA 1] Center 43 (14~72) winsize 59
8326 18:03:58.213277 [CA 2] Center 38 (9~67) winsize 59
8327 18:03:58.216818 [CA 3] Center 36 (7~66) winsize 60
8328 18:03:58.220138 [CA 4] Center 37 (8~67) winsize 60
8329 18:03:58.223046 [CA 5] Center 36 (7~66) winsize 60
8330 18:03:58.223126
8331 18:03:58.226597 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8332 18:03:58.226679
8333 18:03:58.229834 [CATrainingPosCal] consider 2 rank data
8334 18:03:58.233502 u2DelayCellTimex100 = 275/100 ps
8335 18:03:58.236557 CA0 delay=42 (14~71),Diff = 6 PI (21 cell)
8336 18:03:58.243127 CA1 delay=42 (14~71),Diff = 6 PI (21 cell)
8337 18:03:58.246980 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8338 18:03:58.250426 CA3 delay=36 (7~65),Diff = 0 PI (0 cell)
8339 18:03:58.253163 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
8340 18:03:58.256640 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8341 18:03:58.256723
8342 18:03:58.260187 CA PerBit enable=1, Macro0, CA PI delay=36
8343 18:03:58.260270
8344 18:03:58.263518 [CBTSetCACLKResult] CA Dly = 36
8345 18:03:58.263601 CS Dly: 11 (0~44)
8346 18:03:58.269833 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8347 18:03:58.273526 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8348 18:03:58.273610
8349 18:03:58.276711 ----->DramcWriteLeveling(PI) begin...
8350 18:03:58.276795 ==
8351 18:03:58.280088 Dram Type= 6, Freq= 0, CH_1, rank 0
8352 18:03:58.283628 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8353 18:03:58.283712 ==
8354 18:03:58.286808 Write leveling (Byte 0): 25 => 25
8355 18:03:58.289945 Write leveling (Byte 1): 29 => 29
8356 18:03:58.293476 DramcWriteLeveling(PI) end<-----
8357 18:03:58.293559
8358 18:03:58.293643 ==
8359 18:03:58.296925 Dram Type= 6, Freq= 0, CH_1, rank 0
8360 18:03:58.303386 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8361 18:03:58.303470 ==
8362 18:03:58.303554 [Gating] SW mode calibration
8363 18:03:58.313587 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8364 18:03:58.316801 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8365 18:03:58.320110 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8366 18:03:58.326762 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8367 18:03:58.330283 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8368 18:03:58.333780 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8369 18:03:58.340011 1 4 16 | B1->B0 | 2a2a 2424 | 1 0 | (1 1) (0 0)
8370 18:03:58.343788 1 4 20 | B1->B0 | 3434 3333 | 0 0 | (0 0) (0 0)
8371 18:03:58.346994 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8372 18:03:58.353998 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8373 18:03:58.356839 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8374 18:03:58.360260 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8375 18:03:58.366670 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8376 18:03:58.370208 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8377 18:03:58.373647 1 5 16 | B1->B0 | 2424 2f2f | 0 1 | (1 0) (1 0)
8378 18:03:58.376856 1 5 20 | B1->B0 | 2424 2424 | 1 0 | (1 0) (0 0)
8379 18:03:58.383640 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8380 18:03:58.387034 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8381 18:03:58.390378 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8382 18:03:58.397180 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8383 18:03:58.400139 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8384 18:03:58.403380 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8385 18:03:58.410362 1 6 16 | B1->B0 | 3f3f 3737 | 0 0 | (0 0) (0 0)
8386 18:03:58.413333 1 6 20 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
8387 18:03:58.416668 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8388 18:03:58.423571 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8389 18:03:58.426932 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8390 18:03:58.429951 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8391 18:03:58.436823 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8392 18:03:58.440222 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8393 18:03:58.443645 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8394 18:03:58.450509 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8395 18:03:58.453618 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8396 18:03:58.456925 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8397 18:03:58.463728 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8398 18:03:58.466675 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8399 18:03:58.470085 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8400 18:03:58.473545 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8401 18:03:58.480391 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8402 18:03:58.483348 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8403 18:03:58.486882 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8404 18:03:58.493329 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8405 18:03:58.496856 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8406 18:03:58.499994 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8407 18:03:58.506642 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8408 18:03:58.510025 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8409 18:03:58.513587 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8410 18:03:58.519916 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8411 18:03:58.523390 Total UI for P1: 0, mck2ui 16
8412 18:03:58.526829 best dqsien dly found for B0: ( 1, 9, 14)
8413 18:03:58.526908 Total UI for P1: 0, mck2ui 16
8414 18:03:58.533299 best dqsien dly found for B1: ( 1, 9, 14)
8415 18:03:58.536388 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8416 18:03:58.539681 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8417 18:03:58.539812
8418 18:03:58.543332 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8419 18:03:58.546951 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8420 18:03:58.550269 [Gating] SW calibration Done
8421 18:03:58.550354 ==
8422 18:03:58.553161 Dram Type= 6, Freq= 0, CH_1, rank 0
8423 18:03:58.556644 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8424 18:03:58.556727 ==
8425 18:03:58.560066 RX Vref Scan: 0
8426 18:03:58.560149
8427 18:03:58.560232 RX Vref 0 -> 0, step: 1
8428 18:03:58.560310
8429 18:03:58.563631 RX Delay 0 -> 252, step: 8
8430 18:03:58.566587 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8431 18:03:58.573100 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8432 18:03:58.576392 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8433 18:03:58.579978 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8434 18:03:58.583278 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8435 18:03:58.586468 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8436 18:03:58.593469 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
8437 18:03:58.596690 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8438 18:03:58.600035 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8439 18:03:58.603341 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
8440 18:03:58.606181 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8441 18:03:58.613439 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8442 18:03:58.616253 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8443 18:03:58.619722 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8444 18:03:58.623127 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8445 18:03:58.626581 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8446 18:03:58.629685 ==
8447 18:03:58.633180 Dram Type= 6, Freq= 0, CH_1, rank 0
8448 18:03:58.636310 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8449 18:03:58.636394 ==
8450 18:03:58.636477 DQS Delay:
8451 18:03:58.639551 DQS0 = 0, DQS1 = 0
8452 18:03:58.639634 DQM Delay:
8453 18:03:58.642900 DQM0 = 134, DQM1 = 127
8454 18:03:58.642982 DQ Delay:
8455 18:03:58.646399 DQ0 =139, DQ1 =127, DQ2 =123, DQ3 =135
8456 18:03:58.649526 DQ4 =135, DQ5 =143, DQ6 =143, DQ7 =127
8457 18:03:58.652727 DQ8 =111, DQ9 =115, DQ10 =127, DQ11 =123
8458 18:03:58.655960 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8459 18:03:58.656042
8460 18:03:58.656127
8461 18:03:58.656205 ==
8462 18:03:58.659407 Dram Type= 6, Freq= 0, CH_1, rank 0
8463 18:03:58.665970 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8464 18:03:58.666051 ==
8465 18:03:58.666113
8466 18:03:58.666172
8467 18:03:58.666227 TX Vref Scan disable
8468 18:03:58.670133 == TX Byte 0 ==
8469 18:03:58.673249 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8470 18:03:58.680266 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8471 18:03:58.680346 == TX Byte 1 ==
8472 18:03:58.683089 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8473 18:03:58.686476 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8474 18:03:58.689836 ==
8475 18:03:58.693127 Dram Type= 6, Freq= 0, CH_1, rank 0
8476 18:03:58.696607 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8477 18:03:58.696688 ==
8478 18:03:58.708754
8479 18:03:58.712143 TX Vref early break, caculate TX vref
8480 18:03:58.715618 TX Vref=16, minBit 8, minWin=21, winSum=362
8481 18:03:58.719237 TX Vref=18, minBit 8, minWin=21, winSum=370
8482 18:03:58.722151 TX Vref=20, minBit 8, minWin=22, winSum=378
8483 18:03:58.725820 TX Vref=22, minBit 8, minWin=23, winSum=393
8484 18:03:58.728640 TX Vref=24, minBit 8, minWin=24, winSum=405
8485 18:03:58.735350 TX Vref=26, minBit 11, minWin=24, winSum=409
8486 18:03:58.738899 TX Vref=28, minBit 8, minWin=24, winSum=414
8487 18:03:58.742174 TX Vref=30, minBit 1, minWin=25, winSum=416
8488 18:03:58.746035 TX Vref=32, minBit 8, minWin=24, winSum=407
8489 18:03:58.749318 TX Vref=34, minBit 8, minWin=23, winSum=390
8490 18:03:58.755645 [TxChooseVref] Worse bit 1, Min win 25, Win sum 416, Final Vref 30
8491 18:03:58.755727
8492 18:03:58.759174 Final TX Range 0 Vref 30
8493 18:03:58.759255
8494 18:03:58.759318 ==
8495 18:03:58.762352 Dram Type= 6, Freq= 0, CH_1, rank 0
8496 18:03:58.765497 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8497 18:03:58.765613 ==
8498 18:03:58.765682
8499 18:03:58.765740
8500 18:03:58.768946 TX Vref Scan disable
8501 18:03:58.775921 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8502 18:03:58.776006 == TX Byte 0 ==
8503 18:03:58.778861 u2DelayCellOfst[0]=17 cells (5 PI)
8504 18:03:58.782407 u2DelayCellOfst[1]=10 cells (3 PI)
8505 18:03:58.785610 u2DelayCellOfst[2]=0 cells (0 PI)
8506 18:03:58.788732 u2DelayCellOfst[3]=7 cells (2 PI)
8507 18:03:58.792229 u2DelayCellOfst[4]=7 cells (2 PI)
8508 18:03:58.796104 u2DelayCellOfst[5]=17 cells (5 PI)
8509 18:03:58.796188 u2DelayCellOfst[6]=17 cells (5 PI)
8510 18:03:58.798885 u2DelayCellOfst[7]=7 cells (2 PI)
8511 18:03:58.805821 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8512 18:03:58.809195 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8513 18:03:58.809278 == TX Byte 1 ==
8514 18:03:58.812643 u2DelayCellOfst[8]=0 cells (0 PI)
8515 18:03:58.815558 u2DelayCellOfst[9]=3 cells (1 PI)
8516 18:03:58.818997 u2DelayCellOfst[10]=7 cells (2 PI)
8517 18:03:58.822200 u2DelayCellOfst[11]=3 cells (1 PI)
8518 18:03:58.826026 u2DelayCellOfst[12]=10 cells (3 PI)
8519 18:03:58.828999 u2DelayCellOfst[13]=14 cells (4 PI)
8520 18:03:58.832424 u2DelayCellOfst[14]=14 cells (4 PI)
8521 18:03:58.835981 u2DelayCellOfst[15]=17 cells (5 PI)
8522 18:03:58.839352 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8523 18:03:58.842381 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8524 18:03:58.845527 DramC Write-DBI on
8525 18:03:58.845628 ==
8526 18:03:58.849304 Dram Type= 6, Freq= 0, CH_1, rank 0
8527 18:03:58.852948 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8528 18:03:58.853052 ==
8529 18:03:58.853120
8530 18:03:58.853179
8531 18:03:58.855943 TX Vref Scan disable
8532 18:03:58.859136 == TX Byte 0 ==
8533 18:03:58.862712 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8534 18:03:58.862822 == TX Byte 1 ==
8535 18:03:58.869203 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8536 18:03:58.869299 DramC Write-DBI off
8537 18:03:58.869364
8538 18:03:58.869423 [DATLAT]
8539 18:03:58.872621 Freq=1600, CH1 RK0
8540 18:03:58.872717
8541 18:03:58.875669 DATLAT Default: 0xf
8542 18:03:58.875756 0, 0xFFFF, sum = 0
8543 18:03:58.879290 1, 0xFFFF, sum = 0
8544 18:03:58.879373 2, 0xFFFF, sum = 0
8545 18:03:58.882730 3, 0xFFFF, sum = 0
8546 18:03:58.882813 4, 0xFFFF, sum = 0
8547 18:03:58.885944 5, 0xFFFF, sum = 0
8548 18:03:58.886027 6, 0xFFFF, sum = 0
8549 18:03:58.889612 7, 0xFFFF, sum = 0
8550 18:03:58.889695 8, 0xFFFF, sum = 0
8551 18:03:58.892939 9, 0xFFFF, sum = 0
8552 18:03:58.893049 10, 0xFFFF, sum = 0
8553 18:03:58.896098 11, 0xFFFF, sum = 0
8554 18:03:58.896190 12, 0xFFFF, sum = 0
8555 18:03:58.899289 13, 0xFFFF, sum = 0
8556 18:03:58.899374 14, 0x0, sum = 1
8557 18:03:58.902751 15, 0x0, sum = 2
8558 18:03:58.902835 16, 0x0, sum = 3
8559 18:03:58.906140 17, 0x0, sum = 4
8560 18:03:58.906228 best_step = 15
8561 18:03:58.906292
8562 18:03:58.906352 ==
8563 18:03:58.909036 Dram Type= 6, Freq= 0, CH_1, rank 0
8564 18:03:58.915823 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8565 18:03:58.915906 ==
8566 18:03:58.915969 RX Vref Scan: 1
8567 18:03:58.916032
8568 18:03:58.919070 Set Vref Range= 24 -> 127
8569 18:03:58.919150
8570 18:03:58.922189 RX Vref 24 -> 127, step: 1
8571 18:03:58.922270
8572 18:03:58.922333 RX Delay 11 -> 252, step: 4
8573 18:03:58.926197
8574 18:03:58.926277 Set Vref, RX VrefLevel [Byte0]: 24
8575 18:03:58.928795 [Byte1]: 24
8576 18:03:58.933346
8577 18:03:58.933429 Set Vref, RX VrefLevel [Byte0]: 25
8578 18:03:58.936347 [Byte1]: 25
8579 18:03:58.940816
8580 18:03:58.940896 Set Vref, RX VrefLevel [Byte0]: 26
8581 18:03:58.944526 [Byte1]: 26
8582 18:03:58.948361
8583 18:03:58.948441 Set Vref, RX VrefLevel [Byte0]: 27
8584 18:03:58.951669 [Byte1]: 27
8585 18:03:58.956090
8586 18:03:58.956170 Set Vref, RX VrefLevel [Byte0]: 28
8587 18:03:58.959493 [Byte1]: 28
8588 18:03:58.963838
8589 18:03:58.963919 Set Vref, RX VrefLevel [Byte0]: 29
8590 18:03:58.967162 [Byte1]: 29
8591 18:03:58.971112
8592 18:03:58.971193 Set Vref, RX VrefLevel [Byte0]: 30
8593 18:03:58.974583 [Byte1]: 30
8594 18:03:58.978841
8595 18:03:58.978920 Set Vref, RX VrefLevel [Byte0]: 31
8596 18:03:58.982178 [Byte1]: 31
8597 18:03:58.986454
8598 18:03:58.986534 Set Vref, RX VrefLevel [Byte0]: 32
8599 18:03:58.989917 [Byte1]: 32
8600 18:03:58.993978
8601 18:03:58.994064 Set Vref, RX VrefLevel [Byte0]: 33
8602 18:03:58.997496 [Byte1]: 33
8603 18:03:59.001939
8604 18:03:59.002022 Set Vref, RX VrefLevel [Byte0]: 34
8605 18:03:59.005242 [Byte1]: 34
8606 18:03:59.009698
8607 18:03:59.009798 Set Vref, RX VrefLevel [Byte0]: 35
8608 18:03:59.012969 [Byte1]: 35
8609 18:03:59.017014
8610 18:03:59.017108 Set Vref, RX VrefLevel [Byte0]: 36
8611 18:03:59.020553 [Byte1]: 36
8612 18:03:59.024509
8613 18:03:59.024589 Set Vref, RX VrefLevel [Byte0]: 37
8614 18:03:59.028067 [Byte1]: 37
8615 18:03:59.032052
8616 18:03:59.032133 Set Vref, RX VrefLevel [Byte0]: 38
8617 18:03:59.035697 [Byte1]: 38
8618 18:03:59.040138
8619 18:03:59.040219 Set Vref, RX VrefLevel [Byte0]: 39
8620 18:03:59.043218 [Byte1]: 39
8621 18:03:59.047654
8622 18:03:59.047734 Set Vref, RX VrefLevel [Byte0]: 40
8623 18:03:59.050627 [Byte1]: 40
8624 18:03:59.054919
8625 18:03:59.054999 Set Vref, RX VrefLevel [Byte0]: 41
8626 18:03:59.058349 [Byte1]: 41
8627 18:03:59.062888
8628 18:03:59.062969 Set Vref, RX VrefLevel [Byte0]: 42
8629 18:03:59.065967 [Byte1]: 42
8630 18:03:59.070564
8631 18:03:59.070644 Set Vref, RX VrefLevel [Byte0]: 43
8632 18:03:59.073877 [Byte1]: 43
8633 18:03:59.077816
8634 18:03:59.077898 Set Vref, RX VrefLevel [Byte0]: 44
8635 18:03:59.081167 [Byte1]: 44
8636 18:03:59.085706
8637 18:03:59.085789 Set Vref, RX VrefLevel [Byte0]: 45
8638 18:03:59.089110 [Byte1]: 45
8639 18:03:59.093172
8640 18:03:59.093256 Set Vref, RX VrefLevel [Byte0]: 46
8641 18:03:59.096433 [Byte1]: 46
8642 18:03:59.101012
8643 18:03:59.101107 Set Vref, RX VrefLevel [Byte0]: 47
8644 18:03:59.103898 [Byte1]: 47
8645 18:03:59.108450
8646 18:03:59.108532 Set Vref, RX VrefLevel [Byte0]: 48
8647 18:03:59.111784 [Byte1]: 48
8648 18:03:59.116086
8649 18:03:59.116167 Set Vref, RX VrefLevel [Byte0]: 49
8650 18:03:59.119081 [Byte1]: 49
8651 18:03:59.123342
8652 18:03:59.123424 Set Vref, RX VrefLevel [Byte0]: 50
8653 18:03:59.126615 [Byte1]: 50
8654 18:03:59.131235
8655 18:03:59.131316 Set Vref, RX VrefLevel [Byte0]: 51
8656 18:03:59.134749 [Byte1]: 51
8657 18:03:59.138899
8658 18:03:59.138982 Set Vref, RX VrefLevel [Byte0]: 52
8659 18:03:59.142046 [Byte1]: 52
8660 18:03:59.146434
8661 18:03:59.146516 Set Vref, RX VrefLevel [Byte0]: 53
8662 18:03:59.149948 [Byte1]: 53
8663 18:03:59.153984
8664 18:03:59.154065 Set Vref, RX VrefLevel [Byte0]: 54
8665 18:03:59.157144 [Byte1]: 54
8666 18:03:59.161656
8667 18:03:59.161749 Set Vref, RX VrefLevel [Byte0]: 55
8668 18:03:59.164857 [Byte1]: 55
8669 18:03:59.169684
8670 18:03:59.169765 Set Vref, RX VrefLevel [Byte0]: 56
8671 18:03:59.172354 [Byte1]: 56
8672 18:03:59.177104
8673 18:03:59.177184 Set Vref, RX VrefLevel [Byte0]: 57
8674 18:03:59.180181 [Byte1]: 57
8675 18:03:59.184296
8676 18:03:59.184375 Set Vref, RX VrefLevel [Byte0]: 58
8677 18:03:59.187591 [Byte1]: 58
8678 18:03:59.192195
8679 18:03:59.192301 Set Vref, RX VrefLevel [Byte0]: 59
8680 18:03:59.195657 [Byte1]: 59
8681 18:03:59.199711
8682 18:03:59.199793 Set Vref, RX VrefLevel [Byte0]: 60
8683 18:03:59.202950 [Byte1]: 60
8684 18:03:59.207447
8685 18:03:59.207532 Set Vref, RX VrefLevel [Byte0]: 61
8686 18:03:59.210458 [Byte1]: 61
8687 18:03:59.215000
8688 18:03:59.215082 Set Vref, RX VrefLevel [Byte0]: 62
8689 18:03:59.218260 [Byte1]: 62
8690 18:03:59.223058
8691 18:03:59.223140 Set Vref, RX VrefLevel [Byte0]: 63
8692 18:03:59.225991 [Byte1]: 63
8693 18:03:59.230445
8694 18:03:59.230525 Set Vref, RX VrefLevel [Byte0]: 64
8695 18:03:59.233477 [Byte1]: 64
8696 18:03:59.237898
8697 18:03:59.237977 Set Vref, RX VrefLevel [Byte0]: 65
8698 18:03:59.241190 [Byte1]: 65
8699 18:03:59.245254
8700 18:03:59.245334 Set Vref, RX VrefLevel [Byte0]: 66
8701 18:03:59.248879 [Byte1]: 66
8702 18:03:59.252938
8703 18:03:59.253065 Set Vref, RX VrefLevel [Byte0]: 67
8704 18:03:59.256309 [Byte1]: 67
8705 18:03:59.260844
8706 18:03:59.260925 Set Vref, RX VrefLevel [Byte0]: 68
8707 18:03:59.264185 [Byte1]: 68
8708 18:03:59.268025
8709 18:03:59.268109 Set Vref, RX VrefLevel [Byte0]: 69
8710 18:03:59.271481 [Byte1]: 69
8711 18:03:59.276112
8712 18:03:59.276202 Set Vref, RX VrefLevel [Byte0]: 70
8713 18:03:59.278984 [Byte1]: 70
8714 18:03:59.283411
8715 18:03:59.283494 Set Vref, RX VrefLevel [Byte0]: 71
8716 18:03:59.286907 [Byte1]: 71
8717 18:03:59.291349
8718 18:03:59.291435 Set Vref, RX VrefLevel [Byte0]: 72
8719 18:03:59.294135 [Byte1]: 72
8720 18:03:59.298738
8721 18:03:59.298824 Set Vref, RX VrefLevel [Byte0]: 73
8722 18:03:59.302234 [Byte1]: 73
8723 18:03:59.306280
8724 18:03:59.306364 Set Vref, RX VrefLevel [Byte0]: 74
8725 18:03:59.312890 [Byte1]: 74
8726 18:03:59.313048
8727 18:03:59.316284 Set Vref, RX VrefLevel [Byte0]: 75
8728 18:03:59.319154 [Byte1]: 75
8729 18:03:59.319241
8730 18:03:59.322833 Set Vref, RX VrefLevel [Byte0]: 76
8731 18:03:59.326297 [Byte1]: 76
8732 18:03:59.326386
8733 18:03:59.329225 Final RX Vref Byte 0 = 61 to rank0
8734 18:03:59.332859 Final RX Vref Byte 1 = 54 to rank0
8735 18:03:59.336491 Final RX Vref Byte 0 = 61 to rank1
8736 18:03:59.339455 Final RX Vref Byte 1 = 54 to rank1==
8737 18:03:59.342774 Dram Type= 6, Freq= 0, CH_1, rank 0
8738 18:03:59.345685 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8739 18:03:59.349425 ==
8740 18:03:59.349508 DQS Delay:
8741 18:03:59.349571 DQS0 = 0, DQS1 = 0
8742 18:03:59.352669 DQM Delay:
8743 18:03:59.352751 DQM0 = 131, DQM1 = 124
8744 18:03:59.356235 DQ Delay:
8745 18:03:59.359304 DQ0 =134, DQ1 =126, DQ2 =120, DQ3 =128
8746 18:03:59.362851 DQ4 =130, DQ5 =142, DQ6 =142, DQ7 =126
8747 18:03:59.366126 DQ8 =112, DQ9 =112, DQ10 =126, DQ11 =118
8748 18:03:59.369270 DQ12 =132, DQ13 =132, DQ14 =132, DQ15 =132
8749 18:03:59.369352
8750 18:03:59.369415
8751 18:03:59.369475
8752 18:03:59.372593 [DramC_TX_OE_Calibration] TA2
8753 18:03:59.376018 Original DQ_B0 (3 6) =30, OEN = 27
8754 18:03:59.379624 Original DQ_B1 (3 6) =30, OEN = 27
8755 18:03:59.379705 24, 0x0, End_B0=24 End_B1=24
8756 18:03:59.382911 25, 0x0, End_B0=25 End_B1=25
8757 18:03:59.386351 26, 0x0, End_B0=26 End_B1=26
8758 18:03:59.389605 27, 0x0, End_B0=27 End_B1=27
8759 18:03:59.392925 28, 0x0, End_B0=28 End_B1=28
8760 18:03:59.393028 29, 0x0, End_B0=29 End_B1=29
8761 18:03:59.396266 30, 0x0, End_B0=30 End_B1=30
8762 18:03:59.399295 31, 0x4141, End_B0=30 End_B1=30
8763 18:03:59.402652 Byte0 end_step=30 best_step=27
8764 18:03:59.405984 Byte1 end_step=30 best_step=27
8765 18:03:59.406065 Byte0 TX OE(2T, 0.5T) = (3, 3)
8766 18:03:59.409461 Byte1 TX OE(2T, 0.5T) = (3, 3)
8767 18:03:59.409547
8768 18:03:59.409612
8769 18:03:59.419370 [DQSOSCAuto] RK0, (LSB)MR18= 0x1600, (MSB)MR19= 0x303, tDQSOscB0 = 410 ps tDQSOscB1 = 398 ps
8770 18:03:59.423038 CH1 RK0: MR19=303, MR18=1600
8771 18:03:59.426233 CH1_RK0: MR19=0x303, MR18=0x1600, DQSOSC=398, MR23=63, INC=23, DEC=15
8772 18:03:59.429712
8773 18:03:59.433001 ----->DramcWriteLeveling(PI) begin...
8774 18:03:59.433103 ==
8775 18:03:59.435922 Dram Type= 6, Freq= 0, CH_1, rank 1
8776 18:03:59.439126 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8777 18:03:59.439209 ==
8778 18:03:59.442843 Write leveling (Byte 0): 27 => 27
8779 18:03:59.446366 Write leveling (Byte 1): 28 => 28
8780 18:03:59.449315 DramcWriteLeveling(PI) end<-----
8781 18:03:59.449409
8782 18:03:59.449474 ==
8783 18:03:59.452685 Dram Type= 6, Freq= 0, CH_1, rank 1
8784 18:03:59.456143 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8785 18:03:59.456262 ==
8786 18:03:59.459523 [Gating] SW mode calibration
8787 18:03:59.466141 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8788 18:03:59.472523 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8789 18:03:59.475837 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8790 18:03:59.479175 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8791 18:03:59.486132 1 4 8 | B1->B0 | 2323 2727 | 0 1 | (0 0) (0 0)
8792 18:03:59.489738 1 4 12 | B1->B0 | 2525 3434 | 0 1 | (0 0) (1 1)
8793 18:03:59.492935 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8794 18:03:59.495838 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8795 18:03:59.502741 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8796 18:03:59.505999 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8797 18:03:59.509447 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8798 18:03:59.515827 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8799 18:03:59.519143 1 5 8 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (1 0)
8800 18:03:59.522359 1 5 12 | B1->B0 | 3131 2424 | 1 0 | (1 0) (0 0)
8801 18:03:59.529214 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8802 18:03:59.533861 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8803 18:03:59.536230 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8804 18:03:59.543280 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8805 18:03:59.545970 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8806 18:03:59.549715 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8807 18:03:59.556091 1 6 8 | B1->B0 | 2323 3837 | 0 1 | (0 0) (0 0)
8808 18:03:59.559189 1 6 12 | B1->B0 | 3737 4545 | 0 0 | (0 0) (0 0)
8809 18:03:59.562917 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8810 18:03:59.569626 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8811 18:03:59.572512 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8812 18:03:59.575884 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8813 18:03:59.582994 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8814 18:03:59.586058 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8815 18:03:59.589259 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8816 18:03:59.593199 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8817 18:03:59.599211 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8818 18:03:59.603226 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8819 18:03:59.606027 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8820 18:03:59.612789 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8821 18:03:59.615884 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8822 18:03:59.619265 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8823 18:03:59.625985 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8824 18:03:59.629476 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8825 18:03:59.632412 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8826 18:03:59.639608 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8827 18:03:59.642329 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8828 18:03:59.646045 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8829 18:03:59.652763 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8830 18:03:59.656063 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8831 18:03:59.659075 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8832 18:03:59.662412 Total UI for P1: 0, mck2ui 16
8833 18:03:59.665776 best dqsien dly found for B0: ( 1, 9, 4)
8834 18:03:59.672350 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8835 18:03:59.675933 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8836 18:03:59.679161 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8837 18:03:59.682518 Total UI for P1: 0, mck2ui 16
8838 18:03:59.685962 best dqsien dly found for B1: ( 1, 9, 12)
8839 18:03:59.689445 best DQS0 dly(MCK, UI, PI) = (1, 9, 4)
8840 18:03:59.692811 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8841 18:03:59.692928
8842 18:03:59.696144 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 4)
8843 18:03:59.702716 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8844 18:03:59.702804 [Gating] SW calibration Done
8845 18:03:59.702869 ==
8846 18:03:59.706146 Dram Type= 6, Freq= 0, CH_1, rank 1
8847 18:03:59.712647 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8848 18:03:59.712733 ==
8849 18:03:59.712799 RX Vref Scan: 0
8850 18:03:59.712858
8851 18:03:59.716101 RX Vref 0 -> 0, step: 1
8852 18:03:59.716258
8853 18:03:59.719091 RX Delay 0 -> 252, step: 8
8854 18:03:59.722494 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8855 18:03:59.726266 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8856 18:03:59.729596 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8857 18:03:59.732343 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8858 18:03:59.739128 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8859 18:03:59.742569 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8860 18:03:59.745886 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8861 18:03:59.749451 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8862 18:03:59.752557 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8863 18:03:59.759588 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8864 18:03:59.762774 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8865 18:03:59.766035 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8866 18:03:59.769371 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8867 18:03:59.772648 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8868 18:03:59.779395 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8869 18:03:59.783037 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8870 18:03:59.783139 ==
8871 18:03:59.785872 Dram Type= 6, Freq= 0, CH_1, rank 1
8872 18:03:59.789302 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8873 18:03:59.789397 ==
8874 18:03:59.792956 DQS Delay:
8875 18:03:59.793069 DQS0 = 0, DQS1 = 0
8876 18:03:59.793134 DQM Delay:
8877 18:03:59.796445 DQM0 = 132, DQM1 = 127
8878 18:03:59.796532 DQ Delay:
8879 18:03:59.799683 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8880 18:03:59.802846 DQ4 =127, DQ5 =147, DQ6 =143, DQ7 =127
8881 18:03:59.806196 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =119
8882 18:03:59.812669 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8883 18:03:59.812801
8884 18:03:59.812871
8885 18:03:59.812930 ==
8886 18:03:59.815844 Dram Type= 6, Freq= 0, CH_1, rank 1
8887 18:03:59.819074 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8888 18:03:59.819204 ==
8889 18:03:59.819291
8890 18:03:59.819386
8891 18:03:59.822770 TX Vref Scan disable
8892 18:03:59.822886 == TX Byte 0 ==
8893 18:03:59.829203 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8894 18:03:59.832780 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8895 18:03:59.832864 == TX Byte 1 ==
8896 18:03:59.839181 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8897 18:03:59.842839 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8898 18:03:59.842923 ==
8899 18:03:59.845893 Dram Type= 6, Freq= 0, CH_1, rank 1
8900 18:03:59.849462 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8901 18:03:59.849551 ==
8902 18:03:59.863636
8903 18:03:59.867199 TX Vref early break, caculate TX vref
8904 18:03:59.870622 TX Vref=16, minBit 8, minWin=22, winSum=369
8905 18:03:59.873985 TX Vref=18, minBit 9, minWin=22, winSum=378
8906 18:03:59.877184 TX Vref=20, minBit 8, minWin=23, winSum=390
8907 18:03:59.880282 TX Vref=22, minBit 8, minWin=23, winSum=395
8908 18:03:59.883673 TX Vref=24, minBit 15, minWin=24, winSum=406
8909 18:03:59.890319 TX Vref=26, minBit 5, minWin=25, winSum=413
8910 18:03:59.893899 TX Vref=28, minBit 5, minWin=25, winSum=420
8911 18:03:59.896790 TX Vref=30, minBit 5, minWin=24, winSum=416
8912 18:03:59.900144 TX Vref=32, minBit 0, minWin=24, winSum=409
8913 18:03:59.903886 TX Vref=34, minBit 5, minWin=24, winSum=401
8914 18:03:59.907188 TX Vref=36, minBit 0, minWin=24, winSum=390
8915 18:03:59.914052 [TxChooseVref] Worse bit 5, Min win 25, Win sum 420, Final Vref 28
8916 18:03:59.914189
8917 18:03:59.916874 Final TX Range 0 Vref 28
8918 18:03:59.917016
8919 18:03:59.917116 ==
8920 18:03:59.920211 Dram Type= 6, Freq= 0, CH_1, rank 1
8921 18:03:59.923842 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8922 18:03:59.923941 ==
8923 18:03:59.924029
8924 18:03:59.924108
8925 18:03:59.927236 TX Vref Scan disable
8926 18:03:59.933769 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8927 18:03:59.933891 == TX Byte 0 ==
8928 18:03:59.936769 u2DelayCellOfst[0]=17 cells (5 PI)
8929 18:03:59.940594 u2DelayCellOfst[1]=10 cells (3 PI)
8930 18:03:59.943584 u2DelayCellOfst[2]=0 cells (0 PI)
8931 18:03:59.946868 u2DelayCellOfst[3]=7 cells (2 PI)
8932 18:03:59.950677 u2DelayCellOfst[4]=10 cells (3 PI)
8933 18:03:59.953569 u2DelayCellOfst[5]=21 cells (6 PI)
8934 18:03:59.957069 u2DelayCellOfst[6]=17 cells (5 PI)
8935 18:03:59.960515 u2DelayCellOfst[7]=7 cells (2 PI)
8936 18:03:59.963404 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8937 18:03:59.967046 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8938 18:03:59.970282 == TX Byte 1 ==
8939 18:03:59.970365 u2DelayCellOfst[8]=0 cells (0 PI)
8940 18:03:59.973953 u2DelayCellOfst[9]=7 cells (2 PI)
8941 18:03:59.977292 u2DelayCellOfst[10]=10 cells (3 PI)
8942 18:03:59.980133 u2DelayCellOfst[11]=7 cells (2 PI)
8943 18:03:59.983662 u2DelayCellOfst[12]=14 cells (4 PI)
8944 18:03:59.986990 u2DelayCellOfst[13]=17 cells (5 PI)
8945 18:03:59.990512 u2DelayCellOfst[14]=17 cells (5 PI)
8946 18:03:59.993543 u2DelayCellOfst[15]=17 cells (5 PI)
8947 18:03:59.996925 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8948 18:04:00.003583 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8949 18:04:00.003675 DramC Write-DBI on
8950 18:04:00.003758 ==
8951 18:04:00.006749 Dram Type= 6, Freq= 0, CH_1, rank 1
8952 18:04:00.010488 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8953 18:04:00.014019 ==
8954 18:04:00.014103
8955 18:04:00.014185
8956 18:04:00.014263 TX Vref Scan disable
8957 18:04:00.016861 == TX Byte 0 ==
8958 18:04:00.020366 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8959 18:04:00.023947 == TX Byte 1 ==
8960 18:04:00.027270 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8961 18:04:00.030656 DramC Write-DBI off
8962 18:04:00.030739
8963 18:04:00.030821 [DATLAT]
8964 18:04:00.030899 Freq=1600, CH1 RK1
8965 18:04:00.030975
8966 18:04:00.033582 DATLAT Default: 0xf
8967 18:04:00.033680 0, 0xFFFF, sum = 0
8968 18:04:00.037179 1, 0xFFFF, sum = 0
8969 18:04:00.037263 2, 0xFFFF, sum = 0
8970 18:04:00.040263 3, 0xFFFF, sum = 0
8971 18:04:00.040364 4, 0xFFFF, sum = 0
8972 18:04:00.043581 5, 0xFFFF, sum = 0
8973 18:04:00.047199 6, 0xFFFF, sum = 0
8974 18:04:00.047282 7, 0xFFFF, sum = 0
8975 18:04:00.050665 8, 0xFFFF, sum = 0
8976 18:04:00.050749 9, 0xFFFF, sum = 0
8977 18:04:00.053947 10, 0xFFFF, sum = 0
8978 18:04:00.054056 11, 0xFFFF, sum = 0
8979 18:04:00.057241 12, 0xFFFF, sum = 0
8980 18:04:00.057361 13, 0xFFFF, sum = 0
8981 18:04:00.060511 14, 0x0, sum = 1
8982 18:04:00.060592 15, 0x0, sum = 2
8983 18:04:00.063756 16, 0x0, sum = 3
8984 18:04:00.063836 17, 0x0, sum = 4
8985 18:04:00.067039 best_step = 15
8986 18:04:00.067119
8987 18:04:00.067181 ==
8988 18:04:00.070391 Dram Type= 6, Freq= 0, CH_1, rank 1
8989 18:04:00.073841 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8990 18:04:00.073922 ==
8991 18:04:00.073985 RX Vref Scan: 0
8992 18:04:00.074044
8993 18:04:00.077189 RX Vref 0 -> 0, step: 1
8994 18:04:00.077269
8995 18:04:00.080876 RX Delay 11 -> 252, step: 4
8996 18:04:00.084208 iDelay=191, Bit 0, Center 132 (83 ~ 182) 100
8997 18:04:00.090585 iDelay=191, Bit 1, Center 124 (71 ~ 178) 108
8998 18:04:00.094119 iDelay=191, Bit 2, Center 118 (67 ~ 170) 104
8999 18:04:00.096887 iDelay=191, Bit 3, Center 128 (75 ~ 182) 108
9000 18:04:00.100172 iDelay=191, Bit 4, Center 130 (79 ~ 182) 104
9001 18:04:00.103860 iDelay=191, Bit 5, Center 142 (95 ~ 190) 96
9002 18:04:00.110443 iDelay=191, Bit 6, Center 138 (87 ~ 190) 104
9003 18:04:00.113866 iDelay=191, Bit 7, Center 126 (75 ~ 178) 104
9004 18:04:00.117082 iDelay=191, Bit 8, Center 112 (55 ~ 170) 116
9005 18:04:00.120403 iDelay=191, Bit 9, Center 114 (59 ~ 170) 112
9006 18:04:00.123790 iDelay=191, Bit 10, Center 128 (75 ~ 182) 108
9007 18:04:00.127240 iDelay=191, Bit 11, Center 116 (63 ~ 170) 108
9008 18:04:00.133712 iDelay=191, Bit 12, Center 134 (83 ~ 186) 104
9009 18:04:00.137357 iDelay=191, Bit 13, Center 136 (83 ~ 190) 108
9010 18:04:00.140348 iDelay=191, Bit 14, Center 134 (83 ~ 186) 104
9011 18:04:00.143928 iDelay=191, Bit 15, Center 134 (83 ~ 186) 104
9012 18:04:00.144009 ==
9013 18:04:00.147234 Dram Type= 6, Freq= 0, CH_1, rank 1
9014 18:04:00.153804 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9015 18:04:00.153889 ==
9016 18:04:00.153953 DQS Delay:
9017 18:04:00.156908 DQS0 = 0, DQS1 = 0
9018 18:04:00.157013 DQM Delay:
9019 18:04:00.157078 DQM0 = 129, DQM1 = 126
9020 18:04:00.160967 DQ Delay:
9021 18:04:00.163742 DQ0 =132, DQ1 =124, DQ2 =118, DQ3 =128
9022 18:04:00.166913 DQ4 =130, DQ5 =142, DQ6 =138, DQ7 =126
9023 18:04:00.170751 DQ8 =112, DQ9 =114, DQ10 =128, DQ11 =116
9024 18:04:00.173970 DQ12 =134, DQ13 =136, DQ14 =134, DQ15 =134
9025 18:04:00.174049
9026 18:04:00.174111
9027 18:04:00.174170
9028 18:04:00.177410 [DramC_TX_OE_Calibration] TA2
9029 18:04:00.180828 Original DQ_B0 (3 6) =30, OEN = 27
9030 18:04:00.183750 Original DQ_B1 (3 6) =30, OEN = 27
9031 18:04:00.187371 24, 0x0, End_B0=24 End_B1=24
9032 18:04:00.187453 25, 0x0, End_B0=25 End_B1=25
9033 18:04:00.190688 26, 0x0, End_B0=26 End_B1=26
9034 18:04:00.193744 27, 0x0, End_B0=27 End_B1=27
9035 18:04:00.197355 28, 0x0, End_B0=28 End_B1=28
9036 18:04:00.200645 29, 0x0, End_B0=29 End_B1=29
9037 18:04:00.200727 30, 0x0, End_B0=30 End_B1=30
9038 18:04:00.203915 31, 0x4141, End_B0=30 End_B1=30
9039 18:04:00.207322 Byte0 end_step=30 best_step=27
9040 18:04:00.210741 Byte1 end_step=30 best_step=27
9041 18:04:00.213964 Byte0 TX OE(2T, 0.5T) = (3, 3)
9042 18:04:00.214114 Byte1 TX OE(2T, 0.5T) = (3, 3)
9043 18:04:00.217715
9044 18:04:00.217829
9045 18:04:00.224196 [DQSOSCAuto] RK1, (LSB)MR18= 0x1116, (MSB)MR19= 0x303, tDQSOscB0 = 398 ps tDQSOscB1 = 401 ps
9046 18:04:00.227132 CH1 RK1: MR19=303, MR18=1116
9047 18:04:00.233875 CH1_RK1: MR19=0x303, MR18=0x1116, DQSOSC=398, MR23=63, INC=23, DEC=15
9048 18:04:00.237406 [RxdqsGatingPostProcess] freq 1600
9049 18:04:00.240704 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9050 18:04:00.244346 best DQS0 dly(2T, 0.5T) = (1, 1)
9051 18:04:00.247033 best DQS1 dly(2T, 0.5T) = (1, 1)
9052 18:04:00.250303 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9053 18:04:00.253825 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9054 18:04:00.257194 best DQS0 dly(2T, 0.5T) = (1, 1)
9055 18:04:00.260680 best DQS1 dly(2T, 0.5T) = (1, 1)
9056 18:04:00.264299 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9057 18:04:00.267650 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9058 18:04:00.267731 Pre-setting of DQS Precalculation
9059 18:04:00.273802 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9060 18:04:00.280646 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9061 18:04:00.287641 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9062 18:04:00.287723
9063 18:04:00.287787
9064 18:04:00.290972 [Calibration Summary] 3200 Mbps
9065 18:04:00.293877 CH 0, Rank 0
9066 18:04:00.293957 SW Impedance : PASS
9067 18:04:00.297357 DUTY Scan : NO K
9068 18:04:00.300948 ZQ Calibration : PASS
9069 18:04:00.301043 Jitter Meter : NO K
9070 18:04:00.303896 CBT Training : PASS
9071 18:04:00.303977 Write leveling : PASS
9072 18:04:00.307202 RX DQS gating : PASS
9073 18:04:00.310650 RX DQ/DQS(RDDQC) : PASS
9074 18:04:00.310735 TX DQ/DQS : PASS
9075 18:04:00.313960 RX DATLAT : PASS
9076 18:04:00.317425 RX DQ/DQS(Engine): PASS
9077 18:04:00.317513 TX OE : PASS
9078 18:04:00.320811 All Pass.
9079 18:04:00.320919
9080 18:04:00.321044 CH 0, Rank 1
9081 18:04:00.324224 SW Impedance : PASS
9082 18:04:00.324310 DUTY Scan : NO K
9083 18:04:00.327564 ZQ Calibration : PASS
9084 18:04:00.330906 Jitter Meter : NO K
9085 18:04:00.330989 CBT Training : PASS
9086 18:04:00.334135 Write leveling : PASS
9087 18:04:00.337607 RX DQS gating : PASS
9088 18:04:00.337694 RX DQ/DQS(RDDQC) : PASS
9089 18:04:00.340867 TX DQ/DQS : PASS
9090 18:04:00.340990 RX DATLAT : PASS
9091 18:04:00.344004 RX DQ/DQS(Engine): PASS
9092 18:04:00.347463 TX OE : PASS
9093 18:04:00.347558 All Pass.
9094 18:04:00.347623
9095 18:04:00.347683 CH 1, Rank 0
9096 18:04:00.350792 SW Impedance : PASS
9097 18:04:00.354237 DUTY Scan : NO K
9098 18:04:00.354319 ZQ Calibration : PASS
9099 18:04:00.357268 Jitter Meter : NO K
9100 18:04:00.360614 CBT Training : PASS
9101 18:04:00.360696 Write leveling : PASS
9102 18:04:00.364043 RX DQS gating : PASS
9103 18:04:00.367550 RX DQ/DQS(RDDQC) : PASS
9104 18:04:00.367633 TX DQ/DQS : PASS
9105 18:04:00.370799 RX DATLAT : PASS
9106 18:04:00.373831 RX DQ/DQS(Engine): PASS
9107 18:04:00.373942 TX OE : PASS
9108 18:04:00.377372 All Pass.
9109 18:04:00.377453
9110 18:04:00.377516 CH 1, Rank 1
9111 18:04:00.380539 SW Impedance : PASS
9112 18:04:00.380620 DUTY Scan : NO K
9113 18:04:00.384265 ZQ Calibration : PASS
9114 18:04:00.387306 Jitter Meter : NO K
9115 18:04:00.387388 CBT Training : PASS
9116 18:04:00.390600 Write leveling : PASS
9117 18:04:00.390680 RX DQS gating : PASS
9118 18:04:00.394332 RX DQ/DQS(RDDQC) : PASS
9119 18:04:00.397377 TX DQ/DQS : PASS
9120 18:04:00.397459 RX DATLAT : PASS
9121 18:04:00.400894 RX DQ/DQS(Engine): PASS
9122 18:04:00.403699 TX OE : PASS
9123 18:04:00.403779 All Pass.
9124 18:04:00.403842
9125 18:04:00.407368 DramC Write-DBI on
9126 18:04:00.407449 PER_BANK_REFRESH: Hybrid Mode
9127 18:04:00.410637 TX_TRACKING: ON
9128 18:04:00.420601 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9129 18:04:00.427041 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9130 18:04:00.434024 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9131 18:04:00.436982 [FAST_K] Save calibration result to emmc
9132 18:04:00.440444 sync common calibartion params.
9133 18:04:00.443959 sync cbt_mode0:1, 1:1
9134 18:04:00.444040 dram_init: ddr_geometry: 2
9135 18:04:00.447472 dram_init: ddr_geometry: 2
9136 18:04:00.450475 dram_init: ddr_geometry: 2
9137 18:04:00.450589 0:dram_rank_size:100000000
9138 18:04:00.454166 1:dram_rank_size:100000000
9139 18:04:00.460793 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9140 18:04:00.464005 DFS_SHUFFLE_HW_MODE: ON
9141 18:04:00.467568 dramc_set_vcore_voltage set vcore to 725000
9142 18:04:00.467649 Read voltage for 1600, 0
9143 18:04:00.470951 Vio18 = 0
9144 18:04:00.471032 Vcore = 725000
9145 18:04:00.471096 Vdram = 0
9146 18:04:00.474253 Vddq = 0
9147 18:04:00.474333 Vmddr = 0
9148 18:04:00.477295 switch to 3200 Mbps bootup
9149 18:04:00.477376 [DramcRunTimeConfig]
9150 18:04:00.477440 PHYPLL
9151 18:04:00.481365 DPM_CONTROL_AFTERK: ON
9152 18:04:00.484218 PER_BANK_REFRESH: ON
9153 18:04:00.484298 REFRESH_OVERHEAD_REDUCTION: ON
9154 18:04:00.487130 CMD_PICG_NEW_MODE: OFF
9155 18:04:00.490508 XRTWTW_NEW_MODE: ON
9156 18:04:00.490588 XRTRTR_NEW_MODE: ON
9157 18:04:00.493908 TX_TRACKING: ON
9158 18:04:00.493990 RDSEL_TRACKING: OFF
9159 18:04:00.497742 DQS Precalculation for DVFS: ON
9160 18:04:00.497823 RX_TRACKING: OFF
9161 18:04:00.500538 HW_GATING DBG: ON
9162 18:04:00.500618 ZQCS_ENABLE_LP4: ON
9163 18:04:00.503774 RX_PICG_NEW_MODE: ON
9164 18:04:00.507336 TX_PICG_NEW_MODE: ON
9165 18:04:00.507416 ENABLE_RX_DCM_DPHY: ON
9166 18:04:00.510823 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9167 18:04:00.514451 DUMMY_READ_FOR_TRACKING: OFF
9168 18:04:00.517103 !!! SPM_CONTROL_AFTERK: OFF
9169 18:04:00.520513 !!! SPM could not control APHY
9170 18:04:00.520669 IMPEDANCE_TRACKING: ON
9171 18:04:00.523929 TEMP_SENSOR: ON
9172 18:04:00.524083 HW_SAVE_FOR_SR: OFF
9173 18:04:00.527415 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9174 18:04:00.530893 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9175 18:04:00.533905 Read ODT Tracking: ON
9176 18:04:00.534058 Refresh Rate DeBounce: ON
9177 18:04:00.537392 DFS_NO_QUEUE_FLUSH: ON
9178 18:04:00.540870 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9179 18:04:00.544207 ENABLE_DFS_RUNTIME_MRW: OFF
9180 18:04:00.544288 DDR_RESERVE_NEW_MODE: ON
9181 18:04:00.547787 MR_CBT_SWITCH_FREQ: ON
9182 18:04:00.550588 =========================
9183 18:04:00.568316 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9184 18:04:00.571816 dram_init: ddr_geometry: 2
9185 18:04:00.590250 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9186 18:04:00.593859 dram_init: dram init end (result: 0)
9187 18:04:00.599817 DRAM-K: Full calibration passed in 24618 msecs
9188 18:04:00.603301 MRC: failed to locate region type 0.
9189 18:04:00.603444 DRAM rank0 size:0x100000000,
9190 18:04:00.606572 DRAM rank1 size=0x100000000
9191 18:04:00.616399 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9192 18:04:00.623215 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9193 18:04:00.630224 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9194 18:04:00.636313 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9195 18:04:00.639995 DRAM rank0 size:0x100000000,
9196 18:04:00.643212 DRAM rank1 size=0x100000000
9197 18:04:00.643293 CBMEM:
9198 18:04:00.646733 IMD: root @ 0xfffff000 254 entries.
9199 18:04:00.649555 IMD: root @ 0xffffec00 62 entries.
9200 18:04:00.652844 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9201 18:04:00.656367 WARNING: RO_VPD is uninitialized or empty.
9202 18:04:00.662758 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9203 18:04:00.670238 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9204 18:04:00.682979 read SPI 0x42894 0xe01e: 6226 us, 9215 KB/s, 73.720 Mbps
9205 18:04:00.694065 BS: romstage times (exec / console): total (unknown) / 24118 ms
9206 18:04:00.694146
9207 18:04:00.694210
9208 18:04:00.704264 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9209 18:04:00.707616 ARM64: Exception handlers installed.
9210 18:04:00.711124 ARM64: Testing exception
9211 18:04:00.711235 ARM64: Done test exception
9212 18:04:00.714234 Enumerating buses...
9213 18:04:00.718073 Show all devs... Before device enumeration.
9214 18:04:00.720858 Root Device: enabled 1
9215 18:04:00.724149 CPU_CLUSTER: 0: enabled 1
9216 18:04:00.724229 CPU: 00: enabled 1
9217 18:04:00.727862 Compare with tree...
9218 18:04:00.727941 Root Device: enabled 1
9219 18:04:00.730981 CPU_CLUSTER: 0: enabled 1
9220 18:04:00.734379 CPU: 00: enabled 1
9221 18:04:00.734461 Root Device scanning...
9222 18:04:00.737621 scan_static_bus for Root Device
9223 18:04:00.740837 CPU_CLUSTER: 0 enabled
9224 18:04:00.744338 scan_static_bus for Root Device done
9225 18:04:00.748448 scan_bus: bus Root Device finished in 8 msecs
9226 18:04:00.748612 done
9227 18:04:00.754494 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9228 18:04:00.757845 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9229 18:04:00.764307 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9230 18:04:00.767707 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9231 18:04:00.771284 Allocating resources...
9232 18:04:00.771364 Reading resources...
9233 18:04:00.774695 Root Device read_resources bus 0 link: 0
9234 18:04:00.778026 DRAM rank0 size:0x100000000,
9235 18:04:00.780880 DRAM rank1 size=0x100000000
9236 18:04:00.784255 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9237 18:04:00.787687 CPU: 00 missing read_resources
9238 18:04:00.791189 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9239 18:04:00.797959 Root Device read_resources bus 0 link: 0 done
9240 18:04:00.798042 Done reading resources.
9241 18:04:00.804147 Show resources in subtree (Root Device)...After reading.
9242 18:04:00.807796 Root Device child on link 0 CPU_CLUSTER: 0
9243 18:04:00.810968 CPU_CLUSTER: 0 child on link 0 CPU: 00
9244 18:04:00.821423 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9245 18:04:00.821505 CPU: 00
9246 18:04:00.825004 Root Device assign_resources, bus 0 link: 0
9247 18:04:00.827986 CPU_CLUSTER: 0 missing set_resources
9248 18:04:00.830966 Root Device assign_resources, bus 0 link: 0 done
9249 18:04:00.834933 Done setting resources.
9250 18:04:00.841021 Show resources in subtree (Root Device)...After assigning values.
9251 18:04:00.844387 Root Device child on link 0 CPU_CLUSTER: 0
9252 18:04:00.848307 CPU_CLUSTER: 0 child on link 0 CPU: 00
9253 18:04:00.857668 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9254 18:04:00.857755 CPU: 00
9255 18:04:00.861316 Done allocating resources.
9256 18:04:00.864349 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9257 18:04:00.867965 Enabling resources...
9258 18:04:00.868045 done.
9259 18:04:00.871370 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9260 18:04:00.874251 Initializing devices...
9261 18:04:00.874330 Root Device init
9262 18:04:00.877772 init hardware done!
9263 18:04:00.881069 0x00000018: ctrlr->caps
9264 18:04:00.881151 52.000 MHz: ctrlr->f_max
9265 18:04:00.884548 0.400 MHz: ctrlr->f_min
9266 18:04:00.888027 0x40ff8080: ctrlr->voltages
9267 18:04:00.888124 sclk: 390625
9268 18:04:00.891252 Bus Width = 1
9269 18:04:00.891324 sclk: 390625
9270 18:04:00.891385 Bus Width = 1
9271 18:04:00.894521 Early init status = 3
9272 18:04:00.897703 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9273 18:04:00.901906 in-header: 03 fc 00 00 01 00 00 00
9274 18:04:00.905262 in-data: 00
9275 18:04:00.908314 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9276 18:04:00.913781 in-header: 03 fd 00 00 00 00 00 00
9277 18:04:00.916825 in-data:
9278 18:04:00.919899 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9279 18:04:00.924134 in-header: 03 fc 00 00 01 00 00 00
9280 18:04:00.927962 in-data: 00
9281 18:04:00.930894 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9282 18:04:00.936646 in-header: 03 fd 00 00 00 00 00 00
9283 18:04:00.939836 in-data:
9284 18:04:00.943143 [SSUSB] Setting up USB HOST controller...
9285 18:04:00.946593 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9286 18:04:00.949941 [SSUSB] phy power-on done.
9287 18:04:00.953305 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9288 18:04:00.960276 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9289 18:04:00.963313 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9290 18:04:00.969818 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9291 18:04:00.976618 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9292 18:04:00.983641 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9293 18:04:00.990227 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9294 18:04:00.996737 read SPI 0x705bc 0x1f6a: 925 us, 8694 KB/s, 69.552 Mbps
9295 18:04:00.996838 SPM: binary array size = 0x9dc
9296 18:04:01.003341 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9297 18:04:01.010377 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9298 18:04:01.016669 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9299 18:04:01.020014 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9300 18:04:01.023232 configure_display: Starting display init
9301 18:04:01.060106 anx7625_power_on_init: Init interface.
9302 18:04:01.063034 anx7625_disable_pd_protocol: Disabled PD feature.
9303 18:04:01.066296 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9304 18:04:01.094467 anx7625_start_dp_work: Secure OCM version=00
9305 18:04:01.097429 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9306 18:04:01.112300 sp_tx_get_edid_block: EDID Block = 1
9307 18:04:01.214979 Extracted contents:
9308 18:04:01.218398 header: 00 ff ff ff ff ff ff 00
9309 18:04:01.221963 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9310 18:04:01.225185 version: 01 04
9311 18:04:01.228171 basic params: 95 1f 11 78 0a
9312 18:04:01.232014 chroma info: 76 90 94 55 54 90 27 21 50 54
9313 18:04:01.234866 established: 00 00 00
9314 18:04:01.241651 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9315 18:04:01.244950 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9316 18:04:01.251947 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9317 18:04:01.258315 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9318 18:04:01.264943 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9319 18:04:01.268085 extensions: 00
9320 18:04:01.268165 checksum: fb
9321 18:04:01.268229
9322 18:04:01.271626 Manufacturer: IVO Model 57d Serial Number 0
9323 18:04:01.274751 Made week 0 of 2020
9324 18:04:01.274835 EDID version: 1.4
9325 18:04:01.278522 Digital display
9326 18:04:01.281396 6 bits per primary color channel
9327 18:04:01.281506 DisplayPort interface
9328 18:04:01.284651 Maximum image size: 31 cm x 17 cm
9329 18:04:01.287943 Gamma: 220%
9330 18:04:01.288023 Check DPMS levels
9331 18:04:01.291603 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9332 18:04:01.294918 First detailed timing is preferred timing
9333 18:04:01.298237 Established timings supported:
9334 18:04:01.301538 Standard timings supported:
9335 18:04:01.301619 Detailed timings
9336 18:04:01.308104 Hex of detail: 383680a07038204018303c0035ae10000019
9337 18:04:01.311427 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9338 18:04:01.318348 0780 0798 07c8 0820 hborder 0
9339 18:04:01.321288 0438 043b 0447 0458 vborder 0
9340 18:04:01.321382 -hsync -vsync
9341 18:04:01.324400 Did detailed timing
9342 18:04:01.327767 Hex of detail: 000000000000000000000000000000000000
9343 18:04:01.331646 Manufacturer-specified data, tag 0
9344 18:04:01.338047 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9345 18:04:01.338128 ASCII string: InfoVision
9346 18:04:01.344736 Hex of detail: 000000fe00523134304e574635205248200a
9347 18:04:01.344845 ASCII string: R140NWF5 RH
9348 18:04:01.347976 Checksum
9349 18:04:01.348056 Checksum: 0xfb (valid)
9350 18:04:01.355025 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9351 18:04:01.357905 DSI data_rate: 832800000 bps
9352 18:04:01.361701 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9353 18:04:01.364937 anx7625_parse_edid: pixelclock(138800).
9354 18:04:01.371442 hactive(1920), hsync(48), hfp(24), hbp(88)
9355 18:04:01.374796 vactive(1080), vsync(12), vfp(3), vbp(17)
9356 18:04:01.377853 anx7625_dsi_config: config dsi.
9357 18:04:01.384765 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9358 18:04:01.396807 anx7625_dsi_config: success to config DSI
9359 18:04:01.400265 anx7625_dp_start: MIPI phy setup OK.
9360 18:04:01.403756 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9361 18:04:01.406947 mtk_ddp_mode_set invalid vrefresh 60
9362 18:04:01.410279 main_disp_path_setup
9363 18:04:01.410400 ovl_layer_smi_id_en
9364 18:04:01.413717 ovl_layer_smi_id_en
9365 18:04:01.413813 ccorr_config
9366 18:04:01.413893 aal_config
9367 18:04:01.416796 gamma_config
9368 18:04:01.416915 postmask_config
9369 18:04:01.420524 dither_config
9370 18:04:01.423361 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9371 18:04:01.430320 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9372 18:04:01.433661 Root Device init finished in 553 msecs
9373 18:04:01.433742 CPU_CLUSTER: 0 init
9374 18:04:01.443774 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9375 18:04:01.447098 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9376 18:04:01.450072 APU_MBOX 0x190000b0 = 0x10001
9377 18:04:01.453207 APU_MBOX 0x190001b0 = 0x10001
9378 18:04:01.456662 APU_MBOX 0x190005b0 = 0x10001
9379 18:04:01.460228 APU_MBOX 0x190006b0 = 0x10001
9380 18:04:01.463122 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9381 18:04:01.476069 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9382 18:04:01.488300 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9383 18:04:01.494955 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9384 18:04:01.506809 read SPI 0x61c74 0xe8ef: 6411 us, 9301 KB/s, 74.408 Mbps
9385 18:04:01.515801 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9386 18:04:01.518882 CPU_CLUSTER: 0 init finished in 81 msecs
9387 18:04:01.522727 Devices initialized
9388 18:04:01.525663 Show all devs... After init.
9389 18:04:01.525745 Root Device: enabled 1
9390 18:04:01.529161 CPU_CLUSTER: 0: enabled 1
9391 18:04:01.529242 CPU: 00: enabled 1
9392 18:04:01.536171 BS: BS_DEV_INIT run times (exec / console): 212 / 447 ms
9393 18:04:01.539049 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9394 18:04:01.542937 ELOG: NV offset 0x57f000 size 0x1000
9395 18:04:01.549243 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9396 18:04:01.555669 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9397 18:04:01.559017 ELOG: Event(17) added with size 13 at 2024-06-11 18:04:00 UTC
9398 18:04:01.562484 out: cmd=0x121: 03 db 21 01 00 00 00 00
9399 18:04:01.566549 in-header: 03 ad 00 00 2c 00 00 00
9400 18:04:01.579837 in-data: b2 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9401 18:04:01.586651 ELOG: Event(A1) added with size 10 at 2024-06-11 18:04:00 UTC
9402 18:04:01.592891 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9403 18:04:01.599632 ELOG: Event(A0) added with size 9 at 2024-06-11 18:04:00 UTC
9404 18:04:01.603001 elog_add_boot_reason: Logged dev mode boot
9405 18:04:01.606387 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9406 18:04:01.609910 Finalize devices...
9407 18:04:01.609991 Devices finalized
9408 18:04:01.616314 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9409 18:04:01.619693 Writing coreboot table at 0xffe64000
9410 18:04:01.622901 0. 000000000010a000-0000000000113fff: RAMSTAGE
9411 18:04:01.626345 1. 0000000040000000-00000000400fffff: RAM
9412 18:04:01.629603 2. 0000000040100000-000000004032afff: RAMSTAGE
9413 18:04:01.636606 3. 000000004032b000-00000000545fffff: RAM
9414 18:04:01.639863 4. 0000000054600000-000000005465ffff: BL31
9415 18:04:01.643244 5. 0000000054660000-00000000ffe63fff: RAM
9416 18:04:01.646580 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9417 18:04:01.652938 7. 0000000100000000-000000023fffffff: RAM
9418 18:04:01.653057 Passing 5 GPIOs to payload:
9419 18:04:01.659928 NAME | PORT | POLARITY | VALUE
9420 18:04:01.663263 EC in RW | 0x000000aa | low | undefined
9421 18:04:01.669403 EC interrupt | 0x00000005 | low | undefined
9422 18:04:01.672701 TPM interrupt | 0x000000ab | high | undefined
9423 18:04:01.676201 SD card detect | 0x00000011 | high | undefined
9424 18:04:01.683101 speaker enable | 0x00000093 | high | undefined
9425 18:04:01.686252 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9426 18:04:01.689672 in-header: 03 f9 00 00 02 00 00 00
9427 18:04:01.689753 in-data: 02 00
9428 18:04:01.693335 ADC[4]: Raw value=900221 ID=7
9429 18:04:01.695953 ADC[3]: Raw value=213336 ID=1
9430 18:04:01.696034 RAM Code: 0x71
9431 18:04:01.699484 ADC[6]: Raw value=74926 ID=0
9432 18:04:01.702959 ADC[5]: Raw value=211860 ID=1
9433 18:04:01.703054 SKU Code: 0x1
9434 18:04:01.709630 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 738d
9435 18:04:01.713073 coreboot table: 964 bytes.
9436 18:04:01.716351 IMD ROOT 0. 0xfffff000 0x00001000
9437 18:04:01.719325 IMD SMALL 1. 0xffffe000 0x00001000
9438 18:04:01.723035 RO MCACHE 2. 0xffffc000 0x00001104
9439 18:04:01.726260 CONSOLE 3. 0xfff7c000 0x00080000
9440 18:04:01.729973 FMAP 4. 0xfff7b000 0x00000452
9441 18:04:01.733168 TIME STAMP 5. 0xfff7a000 0x00000910
9442 18:04:01.736600 VBOOT WORK 6. 0xfff66000 0x00014000
9443 18:04:01.739851 RAMOOPS 7. 0xffe66000 0x00100000
9444 18:04:01.742722 COREBOOT 8. 0xffe64000 0x00002000
9445 18:04:01.742797 IMD small region:
9446 18:04:01.746111 IMD ROOT 0. 0xffffec00 0x00000400
9447 18:04:01.749500 VPD 1. 0xffffeb80 0x0000006c
9448 18:04:01.752931 MMC STATUS 2. 0xffffeb60 0x00000004
9449 18:04:01.759439 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9450 18:04:01.759521 Probing TPM: done!
9451 18:04:01.766262 Connected to device vid:did:rid of 1ae0:0028:00
9452 18:04:01.773081 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9453 18:04:01.776624 Initialized TPM device CR50 revision 0
9454 18:04:01.780173 Checking cr50 for pending updates
9455 18:04:01.786076 Reading cr50 TPM mode
9456 18:04:01.794441 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9457 18:04:01.801236 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9458 18:04:01.841747 read SPI 0x3990ec 0x4f1b0: 34854 us, 9296 KB/s, 74.368 Mbps
9459 18:04:01.845257 Checking segment from ROM address 0x40100000
9460 18:04:01.847976 Checking segment from ROM address 0x4010001c
9461 18:04:01.854564 Loading segment from ROM address 0x40100000
9462 18:04:01.854653 code (compression=0)
9463 18:04:01.861677 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9464 18:04:01.871390 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9465 18:04:01.871471 it's not compressed!
9466 18:04:01.877917 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9467 18:04:01.881700 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9468 18:04:01.901990 Loading segment from ROM address 0x4010001c
9469 18:04:01.902089 Entry Point 0x80000000
9470 18:04:01.905364 Loaded segments
9471 18:04:01.908545 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9472 18:04:01.915295 Jumping to boot code at 0x80000000(0xffe64000)
9473 18:04:01.921954 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9474 18:04:01.928479 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9475 18:04:01.935913 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9476 18:04:01.939345 Checking segment from ROM address 0x40100000
9477 18:04:01.942891 Checking segment from ROM address 0x4010001c
9478 18:04:01.950097 Loading segment from ROM address 0x40100000
9479 18:04:01.950180 code (compression=1)
9480 18:04:01.956341 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9481 18:04:01.966012 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9482 18:04:01.966094 using LZMA
9483 18:04:01.974525 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9484 18:04:01.980995 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9485 18:04:01.984457 Loading segment from ROM address 0x4010001c
9486 18:04:01.984585 Entry Point 0x54601000
9487 18:04:01.988062 Loaded segments
9488 18:04:01.991083 NOTICE: MT8192 bl31_setup
9489 18:04:01.998192 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9490 18:04:02.001373 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9491 18:04:02.004833 WARNING: region 0:
9492 18:04:02.008374 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9493 18:04:02.008486 WARNING: region 1:
9494 18:04:02.014551 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9495 18:04:02.018400 WARNING: region 2:
9496 18:04:02.021622 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9497 18:04:02.024755 WARNING: region 3:
9498 18:04:02.028183 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9499 18:04:02.031842 WARNING: region 4:
9500 18:04:02.035030 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9501 18:04:02.038161 WARNING: region 5:
9502 18:04:02.041607 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9503 18:04:02.045209 WARNING: region 6:
9504 18:04:02.048513 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9505 18:04:02.048615 WARNING: region 7:
9506 18:04:02.054896 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9507 18:04:02.061896 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9508 18:04:02.065472 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9509 18:04:02.068857 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9510 18:04:02.072212 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9511 18:04:02.078459 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9512 18:04:02.081903 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9513 18:04:02.088544 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9514 18:04:02.092418 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9515 18:04:02.095460 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9516 18:04:02.102017 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9517 18:04:02.105372 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9518 18:04:02.108740 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9519 18:04:02.115846 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9520 18:04:02.118860 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9521 18:04:02.122291 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9522 18:04:02.128795 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9523 18:04:02.132066 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9524 18:04:02.139222 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9525 18:04:02.142798 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9526 18:04:02.145918 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9527 18:04:02.152842 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9528 18:04:02.156400 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9529 18:04:02.159402 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9530 18:04:02.166016 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9531 18:04:02.169362 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9532 18:04:02.175878 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9533 18:04:02.179282 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9534 18:04:02.182937 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9535 18:04:02.189691 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9536 18:04:02.193254 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9537 18:04:02.199447 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9538 18:04:02.203312 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9539 18:04:02.206308 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9540 18:04:02.210066 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9541 18:04:02.216771 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9542 18:04:02.219815 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9543 18:04:02.223350 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9544 18:04:02.227227 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9545 18:04:02.233310 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9546 18:04:02.236863 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9547 18:04:02.240214 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9548 18:04:02.243122 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9549 18:04:02.246610 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9550 18:04:02.253393 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9551 18:04:02.257028 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9552 18:04:02.260580 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9553 18:04:02.267100 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9554 18:04:02.270135 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9555 18:04:02.273703 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9556 18:04:02.280522 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9557 18:04:02.283905 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9558 18:04:02.287371 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9559 18:04:02.293515 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9560 18:04:02.297117 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9561 18:04:02.303562 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9562 18:04:02.307357 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9563 18:04:02.310845 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9564 18:04:02.317280 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9565 18:04:02.320588 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9566 18:04:02.327081 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9567 18:04:02.330596 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9568 18:04:02.337076 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9569 18:04:02.340921 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9570 18:04:02.347297 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9571 18:04:02.350844 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9572 18:04:02.354168 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9573 18:04:02.360610 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9574 18:04:02.363676 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9575 18:04:02.370552 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9576 18:04:02.374198 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9577 18:04:02.377210 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9578 18:04:02.384020 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9579 18:04:02.387318 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9580 18:04:02.394048 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9581 18:04:02.397261 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9582 18:04:02.404673 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9583 18:04:02.407639 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9584 18:04:02.411094 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9585 18:04:02.417883 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9586 18:04:02.421075 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9587 18:04:02.427814 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9588 18:04:02.431137 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9589 18:04:02.437591 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9590 18:04:02.441119 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9591 18:04:02.444280 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9592 18:04:02.451237 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9593 18:04:02.454239 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9594 18:04:02.461169 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9595 18:04:02.464670 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9596 18:04:02.470981 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9597 18:04:02.474634 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9598 18:04:02.478210 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9599 18:04:02.484515 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9600 18:04:02.487877 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9601 18:04:02.494585 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9602 18:04:02.498066 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9603 18:04:02.501439 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9604 18:04:02.508064 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9605 18:04:02.511432 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9606 18:04:02.514459 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9607 18:04:02.518007 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9608 18:04:02.524448 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9609 18:04:02.528004 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9610 18:04:02.535153 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9611 18:04:02.537985 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9612 18:04:02.541625 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9613 18:04:02.548693 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9614 18:04:02.552002 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9615 18:04:02.555796 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9616 18:04:02.561785 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9617 18:04:02.565371 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9618 18:04:02.571672 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9619 18:04:02.575315 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9620 18:04:02.578083 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9621 18:04:02.585271 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9622 18:04:02.588725 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9623 18:04:02.591658 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9624 18:04:02.598554 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9625 18:04:02.602109 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9626 18:04:02.605597 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9627 18:04:02.608847 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9628 18:04:02.615290 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9629 18:04:02.618676 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9630 18:04:02.622561 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9631 18:04:02.628830 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9632 18:04:02.632448 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9633 18:04:02.635230 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9634 18:04:02.641800 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9635 18:04:02.645463 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9636 18:04:02.651826 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9637 18:04:02.655717 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9638 18:04:02.658617 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9639 18:04:02.665624 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9640 18:04:02.668537 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9641 18:04:02.672014 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9642 18:04:02.678603 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9643 18:04:02.682218 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9644 18:04:02.688778 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9645 18:04:02.691977 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9646 18:04:02.695757 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9647 18:04:02.702587 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9648 18:04:02.705626 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9649 18:04:02.712594 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9650 18:04:02.715617 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9651 18:04:02.719181 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9652 18:04:02.725447 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9653 18:04:02.729014 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9654 18:04:02.732445 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9655 18:04:02.738860 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9656 18:04:02.742422 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9657 18:04:02.749184 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9658 18:04:02.752446 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9659 18:04:02.755559 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9660 18:04:02.762378 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9661 18:04:02.765693 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9662 18:04:02.769306 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9663 18:04:02.775797 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9664 18:04:02.779307 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9665 18:04:02.782336 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9666 18:04:02.789362 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9667 18:04:02.793031 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9668 18:04:02.799129 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9669 18:04:02.802741 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9670 18:04:02.806213 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9671 18:04:02.812714 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9672 18:04:02.816412 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9673 18:04:02.822397 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9674 18:04:02.826149 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9675 18:04:02.829012 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9676 18:04:02.836014 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9677 18:04:02.839026 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9678 18:04:02.846059 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9679 18:04:02.849321 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9680 18:04:02.852657 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9681 18:04:02.859555 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9682 18:04:02.862544 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9683 18:04:02.866060 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9684 18:04:02.872427 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9685 18:04:02.875993 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9686 18:04:02.882458 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9687 18:04:02.886274 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9688 18:04:02.889857 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9689 18:04:02.895844 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9690 18:04:02.899356 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9691 18:04:02.906062 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9692 18:04:02.909364 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9693 18:04:02.912627 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9694 18:04:02.919555 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9695 18:04:02.922989 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9696 18:04:02.926539 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9697 18:04:02.933046 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9698 18:04:02.935848 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9699 18:04:02.943212 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9700 18:04:02.946036 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9701 18:04:02.949724 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9702 18:04:02.956151 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9703 18:04:02.959352 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9704 18:04:02.966135 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9705 18:04:02.969568 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9706 18:04:02.975980 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9707 18:04:02.979557 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9708 18:04:02.982723 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9709 18:04:02.989194 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9710 18:04:02.993199 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9711 18:04:02.999241 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9712 18:04:03.002713 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9713 18:04:03.009101 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9714 18:04:03.012522 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9715 18:04:03.016372 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9716 18:04:03.022406 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9717 18:04:03.026153 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9718 18:04:03.032555 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9719 18:04:03.036193 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9720 18:04:03.039904 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9721 18:04:03.046271 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9722 18:04:03.049216 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9723 18:04:03.056187 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9724 18:04:03.059456 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9725 18:04:03.063001 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9726 18:04:03.069453 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9727 18:04:03.073107 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9728 18:04:03.079570 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9729 18:04:03.082967 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9730 18:04:03.086145 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9731 18:04:03.092892 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9732 18:04:03.096281 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9733 18:04:03.102449 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9734 18:04:03.105983 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9735 18:04:03.109376 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9736 18:04:03.116482 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9737 18:04:03.119342 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9738 18:04:03.122742 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9739 18:04:03.125990 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9740 18:04:03.132787 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9741 18:04:03.135961 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9742 18:04:03.139485 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9743 18:04:03.146357 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9744 18:04:03.149881 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9745 18:04:03.152941 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9746 18:04:03.159370 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9747 18:04:03.163061 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9748 18:04:03.169484 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9749 18:04:03.172319 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9750 18:04:03.175858 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9751 18:04:03.182814 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9752 18:04:03.186001 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9753 18:04:03.189189 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9754 18:04:03.196008 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9755 18:04:03.198987 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9756 18:04:03.202620 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9757 18:04:03.209407 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9758 18:04:03.212583 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9759 18:04:03.219685 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9760 18:04:03.223287 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9761 18:04:03.225925 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9762 18:04:03.232637 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9763 18:04:03.235960 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9764 18:04:03.239230 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9765 18:04:03.245903 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9766 18:04:03.249327 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9767 18:04:03.252836 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9768 18:04:03.259303 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9769 18:04:03.262882 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9770 18:04:03.266024 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9771 18:04:03.272575 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9772 18:04:03.276016 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9773 18:04:03.282278 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9774 18:04:03.285808 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9775 18:04:03.289289 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9776 18:04:03.292365 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9777 18:04:03.299316 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9778 18:04:03.302812 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9779 18:04:03.306078 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9780 18:04:03.309490 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9781 18:04:03.315908 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9782 18:04:03.319197 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9783 18:04:03.322797 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9784 18:04:03.325771 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9785 18:04:03.329466 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9786 18:04:03.335924 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9787 18:04:03.339563 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9788 18:04:03.342658 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9789 18:04:03.349239 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9790 18:04:03.352782 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9791 18:04:03.359167 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9792 18:04:03.362723 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9793 18:04:03.366088 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9794 18:04:03.372680 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9795 18:04:03.376296 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9796 18:04:03.382730 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9797 18:04:03.385827 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9798 18:04:03.389285 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9799 18:04:03.395820 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9800 18:04:03.399042 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9801 18:04:03.405735 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9802 18:04:03.409576 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9803 18:04:03.416199 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9804 18:04:03.418971 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9805 18:04:03.422906 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9806 18:04:03.429492 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9807 18:04:03.432555 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9808 18:04:03.435918 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9809 18:04:03.442327 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9810 18:04:03.445811 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9811 18:04:03.452329 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9812 18:04:03.455797 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9813 18:04:03.458845 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9814 18:04:03.465855 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9815 18:04:03.468883 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9816 18:04:03.476307 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9817 18:04:03.478938 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9818 18:04:03.486160 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9819 18:04:03.488992 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9820 18:04:03.492537 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9821 18:04:03.499196 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9822 18:04:03.502272 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9823 18:04:03.509448 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9824 18:04:03.512359 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9825 18:04:03.515772 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9826 18:04:03.522586 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9827 18:04:03.525593 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9828 18:04:03.529063 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9829 18:04:03.535932 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9830 18:04:03.538792 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9831 18:04:03.545605 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9832 18:04:03.549051 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9833 18:04:03.556228 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9834 18:04:03.558936 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9835 18:04:03.562450 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9836 18:04:03.569051 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9837 18:04:03.571927 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9838 18:04:03.579245 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9839 18:04:03.581990 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9840 18:04:03.585639 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9841 18:04:03.592123 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9842 18:04:03.595696 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9843 18:04:03.602163 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9844 18:04:03.605785 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9845 18:04:03.609337 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9846 18:04:03.616143 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9847 18:04:03.618772 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9848 18:04:03.625434 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9849 18:04:03.629049 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9850 18:04:03.632598 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9851 18:04:03.639215 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9852 18:04:03.642498 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9853 18:04:03.649258 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9854 18:04:03.652678 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9855 18:04:03.655642 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9856 18:04:03.662553 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9857 18:04:03.665598 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9858 18:04:03.672451 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9859 18:04:03.675399 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9860 18:04:03.678723 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9861 18:04:03.685218 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9862 18:04:03.688712 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9863 18:04:03.695316 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9864 18:04:03.698716 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9865 18:04:03.704945 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9866 18:04:03.708271 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9867 18:04:03.715137 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9868 18:04:03.718694 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9869 18:04:03.721995 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9870 18:04:03.728951 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9871 18:04:03.732287 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9872 18:04:03.738686 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9873 18:04:03.742416 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9874 18:04:03.749234 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9875 18:04:03.752181 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9876 18:04:03.755712 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9877 18:04:03.762523 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9878 18:04:03.765499 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9879 18:04:03.772082 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9880 18:04:03.775558 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9881 18:04:03.782063 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9882 18:04:03.785360 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9883 18:04:03.788867 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9884 18:04:03.795607 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9885 18:04:03.798767 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9886 18:04:03.805641 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9887 18:04:03.808922 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9888 18:04:03.811950 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9889 18:04:03.818798 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9890 18:04:03.822304 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9891 18:04:03.828849 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9892 18:04:03.831811 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9893 18:04:03.838355 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9894 18:04:03.841798 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9895 18:04:03.845015 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9896 18:04:03.851968 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9897 18:04:03.855399 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9898 18:04:03.862066 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9899 18:04:03.865349 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9900 18:04:03.871776 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9901 18:04:03.875692 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9902 18:04:03.879306 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9903 18:04:03.885600 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9904 18:04:03.888960 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9905 18:04:03.896100 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9906 18:04:03.899223 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9907 18:04:03.905909 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9908 18:04:03.908773 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9909 18:04:03.912132 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9910 18:04:03.919170 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9911 18:04:03.922487 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9912 18:04:03.928924 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9913 18:04:03.932274 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9914 18:04:03.938820 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9915 18:04:03.942281 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9916 18:04:03.948618 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9917 18:04:03.952027 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9918 18:04:03.958730 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9919 18:04:03.961842 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9920 18:04:03.965340 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9921 18:04:03.971799 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9922 18:04:03.974945 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9923 18:04:03.981969 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9924 18:04:03.985488 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9925 18:04:03.991997 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9926 18:04:03.995576 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9927 18:04:04.002191 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9928 18:04:04.005727 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9929 18:04:04.012166 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9930 18:04:04.015302 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9931 18:04:04.022413 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9932 18:04:04.025317 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9933 18:04:04.032024 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9934 18:04:04.035746 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9935 18:04:04.042057 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9936 18:04:04.045493 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9937 18:04:04.051912 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9938 18:04:04.055444 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9939 18:04:04.062123 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9940 18:04:04.065253 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9941 18:04:04.071638 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9942 18:04:04.072059 INFO: [APUAPC] vio 0
9943 18:04:04.078599 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9944 18:04:04.081634 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9945 18:04:04.084602 INFO: [APUAPC] D0_APC_0: 0x400510
9946 18:04:04.088394 INFO: [APUAPC] D0_APC_1: 0x0
9947 18:04:04.091335 INFO: [APUAPC] D0_APC_2: 0x1540
9948 18:04:04.095070 INFO: [APUAPC] D0_APC_3: 0x0
9949 18:04:04.098040 INFO: [APUAPC] D1_APC_0: 0xffffffff
9950 18:04:04.101719 INFO: [APUAPC] D1_APC_1: 0xffffffff
9951 18:04:04.104938 INFO: [APUAPC] D1_APC_2: 0x3fffff
9952 18:04:04.111735 INFO: [APUAPC] D1_APC_3: 0x0
9953 18:04:04.111858 INFO: [APUAPC] D2_APC_0: 0xffffffff
9954 18:04:04.115067 INFO: [APUAPC] D2_APC_1: 0xffffffff
9955 18:04:04.118334 INFO: [APUAPC] D2_APC_2: 0x3fffff
9956 18:04:04.121349 INFO: [APUAPC] D2_APC_3: 0x0
9957 18:04:04.125331 INFO: [APUAPC] D3_APC_0: 0xffffffff
9958 18:04:04.127991 INFO: [APUAPC] D3_APC_1: 0xffffffff
9959 18:04:04.131601 INFO: [APUAPC] D3_APC_2: 0x3fffff
9960 18:04:04.131695 INFO: [APUAPC] D3_APC_3: 0x0
9961 18:04:04.135128 INFO: [APUAPC] D4_APC_0: 0xffffffff
9962 18:04:04.141281 INFO: [APUAPC] D4_APC_1: 0xffffffff
9963 18:04:04.144899 INFO: [APUAPC] D4_APC_2: 0x3fffff
9964 18:04:04.145111 INFO: [APUAPC] D4_APC_3: 0x0
9965 18:04:04.148383 INFO: [APUAPC] D5_APC_0: 0xffffffff
9966 18:04:04.151424 INFO: [APUAPC] D5_APC_1: 0xffffffff
9967 18:04:04.155064 INFO: [APUAPC] D5_APC_2: 0x3fffff
9968 18:04:04.158452 INFO: [APUAPC] D5_APC_3: 0x0
9969 18:04:04.161313 INFO: [APUAPC] D6_APC_0: 0xffffffff
9970 18:04:04.164890 INFO: [APUAPC] D6_APC_1: 0xffffffff
9971 18:04:04.168215 INFO: [APUAPC] D6_APC_2: 0x3fffff
9972 18:04:04.171291 INFO: [APUAPC] D6_APC_3: 0x0
9973 18:04:04.175145 INFO: [APUAPC] D7_APC_0: 0xffffffff
9974 18:04:04.178359 INFO: [APUAPC] D7_APC_1: 0xffffffff
9975 18:04:04.182154 INFO: [APUAPC] D7_APC_2: 0x3fffff
9976 18:04:04.185033 INFO: [APUAPC] D7_APC_3: 0x0
9977 18:04:04.188461 INFO: [APUAPC] D8_APC_0: 0xffffffff
9978 18:04:04.191632 INFO: [APUAPC] D8_APC_1: 0xffffffff
9979 18:04:04.195089 INFO: [APUAPC] D8_APC_2: 0x3fffff
9980 18:04:04.198492 INFO: [APUAPC] D8_APC_3: 0x0
9981 18:04:04.201397 INFO: [APUAPC] D9_APC_0: 0xffffffff
9982 18:04:04.204870 INFO: [APUAPC] D9_APC_1: 0xffffffff
9983 18:04:04.208551 INFO: [APUAPC] D9_APC_2: 0x3fffff
9984 18:04:04.211379 INFO: [APUAPC] D9_APC_3: 0x0
9985 18:04:04.214984 INFO: [APUAPC] D10_APC_0: 0xffffffff
9986 18:04:04.218404 INFO: [APUAPC] D10_APC_1: 0xffffffff
9987 18:04:04.221722 INFO: [APUAPC] D10_APC_2: 0x3fffff
9988 18:04:04.225159 INFO: [APUAPC] D10_APC_3: 0x0
9989 18:04:04.228022 INFO: [APUAPC] D11_APC_0: 0xffffffff
9990 18:04:04.231263 INFO: [APUAPC] D11_APC_1: 0xffffffff
9991 18:04:04.234765 INFO: [APUAPC] D11_APC_2: 0x3fffff
9992 18:04:04.238202 INFO: [APUAPC] D11_APC_3: 0x0
9993 18:04:04.241424 INFO: [APUAPC] D12_APC_0: 0xffffffff
9994 18:04:04.244651 INFO: [APUAPC] D12_APC_1: 0xffffffff
9995 18:04:04.248336 INFO: [APUAPC] D12_APC_2: 0x3fffff
9996 18:04:04.251375 INFO: [APUAPC] D12_APC_3: 0x0
9997 18:04:04.254830 INFO: [APUAPC] D13_APC_0: 0xffffffff
9998 18:04:04.258486 INFO: [APUAPC] D13_APC_1: 0xffffffff
9999 18:04:04.261903 INFO: [APUAPC] D13_APC_2: 0x3fffff
10000 18:04:04.265070 INFO: [APUAPC] D13_APC_3: 0x0
10001 18:04:04.268517 INFO: [APUAPC] D14_APC_0: 0xffffffff
10002 18:04:04.271705 INFO: [APUAPC] D14_APC_1: 0xffffffff
10003 18:04:04.275247 INFO: [APUAPC] D14_APC_2: 0x3fffff
10004 18:04:04.278493 INFO: [APUAPC] D14_APC_3: 0x0
10005 18:04:04.281793 INFO: [APUAPC] D15_APC_0: 0xffffffff
10006 18:04:04.285060 INFO: [APUAPC] D15_APC_1: 0xffffffff
10007 18:04:04.288517 INFO: [APUAPC] D15_APC_2: 0x3fffff
10008 18:04:04.291958 INFO: [APUAPC] D15_APC_3: 0x0
10009 18:04:04.294986 INFO: [APUAPC] APC_CON: 0x4
10010 18:04:04.298712 INFO: [NOCDAPC] D0_APC_0: 0x0
10011 18:04:04.299127 INFO: [NOCDAPC] D0_APC_1: 0x0
10012 18:04:04.301994 INFO: [NOCDAPC] D1_APC_0: 0x0
10013 18:04:04.305111 INFO: [NOCDAPC] D1_APC_1: 0xfff
10014 18:04:04.308642 INFO: [NOCDAPC] D2_APC_0: 0x0
10015 18:04:04.311857 INFO: [NOCDAPC] D2_APC_1: 0xfff
10016 18:04:04.314974 INFO: [NOCDAPC] D3_APC_0: 0x0
10017 18:04:04.318539 INFO: [NOCDAPC] D3_APC_1: 0xfff
10018 18:04:04.321682 INFO: [NOCDAPC] D4_APC_0: 0x0
10019 18:04:04.325091 INFO: [NOCDAPC] D4_APC_1: 0xfff
10020 18:04:04.328252 INFO: [NOCDAPC] D5_APC_0: 0x0
10021 18:04:04.331701 INFO: [NOCDAPC] D5_APC_1: 0xfff
10022 18:04:04.332111 INFO: [NOCDAPC] D6_APC_0: 0x0
10023 18:04:04.335231 INFO: [NOCDAPC] D6_APC_1: 0xfff
10024 18:04:04.338625 INFO: [NOCDAPC] D7_APC_0: 0x0
10025 18:04:04.341736 INFO: [NOCDAPC] D7_APC_1: 0xfff
10026 18:04:04.345202 INFO: [NOCDAPC] D8_APC_0: 0x0
10027 18:04:04.348427 INFO: [NOCDAPC] D8_APC_1: 0xfff
10028 18:04:04.351655 INFO: [NOCDAPC] D9_APC_0: 0x0
10029 18:04:04.355412 INFO: [NOCDAPC] D9_APC_1: 0xfff
10030 18:04:04.358129 INFO: [NOCDAPC] D10_APC_0: 0x0
10031 18:04:04.361704 INFO: [NOCDAPC] D10_APC_1: 0xfff
10032 18:04:04.364538 INFO: [NOCDAPC] D11_APC_0: 0x0
10033 18:04:04.364686 INFO: [NOCDAPC] D11_APC_1: 0xfff
10034 18:04:04.368061 INFO: [NOCDAPC] D12_APC_0: 0x0
10035 18:04:04.371804 INFO: [NOCDAPC] D12_APC_1: 0xfff
10036 18:04:04.375434 INFO: [NOCDAPC] D13_APC_0: 0x0
10037 18:04:04.378142 INFO: [NOCDAPC] D13_APC_1: 0xfff
10038 18:04:04.381688 INFO: [NOCDAPC] D14_APC_0: 0x0
10039 18:04:04.385277 INFO: [NOCDAPC] D14_APC_1: 0xfff
10040 18:04:04.388175 INFO: [NOCDAPC] D15_APC_0: 0x0
10041 18:04:04.391520 INFO: [NOCDAPC] D15_APC_1: 0xfff
10042 18:04:04.395455 INFO: [NOCDAPC] APC_CON: 0x4
10043 18:04:04.398358 INFO: [APUAPC] set_apusys_apc done
10044 18:04:04.401346 INFO: [DEVAPC] devapc_init done
10045 18:04:04.404912 INFO: GICv3 without legacy support detected.
10046 18:04:04.408451 INFO: ARM GICv3 driver initialized in EL3
10047 18:04:04.411319 INFO: Maximum SPI INTID supported: 639
10048 18:04:04.418326 INFO: BL31: Initializing runtime services
10049 18:04:04.421593 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10050 18:04:04.424850 INFO: SPM: enable CPC mode
10051 18:04:04.431483 INFO: mcdi ready for mcusys-off-idle and system suspend
10052 18:04:04.435017 INFO: BL31: Preparing for EL3 exit to normal world
10053 18:04:04.437788 INFO: Entry point address = 0x80000000
10054 18:04:04.441066 INFO: SPSR = 0x8
10055 18:04:04.446389
10056 18:04:04.446800
10057 18:04:04.447129
10058 18:04:04.449726 Starting depthcharge on Spherion...
10059 18:04:04.450282
10060 18:04:04.450847 Wipe memory regions:
10061 18:04:04.451344
10062 18:04:04.454869 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10063 18:04:04.455613 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10064 18:04:04.456110 Setting prompt string to ['asurada:']
10065 18:04:04.456503 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10066 18:04:04.457186 [0x00000040000000, 0x00000054600000)
10067 18:04:04.575360
10068 18:04:04.575861 [0x00000054660000, 0x00000080000000)
10069 18:04:04.836336
10070 18:04:04.836959 [0x000000821a7280, 0x000000ffe64000)
10071 18:04:05.580620
10072 18:04:05.581232 [0x00000100000000, 0x00000240000000)
10073 18:04:07.471520
10074 18:04:07.474218 Initializing XHCI USB controller at 0x11200000.
10075 18:04:08.512338
10076 18:04:08.515577 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10077 18:04:08.515784
10078 18:04:08.515995
10079 18:04:08.516492 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10081 18:04:08.617298 asurada: tftpboot 192.168.201.1 14291408/tftp-deploy-n4a6lwod/kernel/image.itb 14291408/tftp-deploy-n4a6lwod/kernel/cmdline
10082 18:04:08.617881 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10083 18:04:08.618330 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10084 18:04:08.623459 tftpboot 192.168.201.1 14291408/tftp-deploy-n4a6lwod/kernel/image.ittp-deploy-n4a6lwod/kernel/cmdline
10085 18:04:08.623876
10086 18:04:08.624285 Waiting for link
10087 18:04:08.783809
10088 18:04:08.784314 R8152: Initializing
10089 18:04:08.784696
10090 18:04:08.786659 Version 6 (ocp_data = 5c30)
10091 18:04:08.787093
10092 18:04:08.790474 R8152: Done initializing
10093 18:04:08.790881
10094 18:04:08.791199 Adding net device
10095 18:04:10.769697
10096 18:04:10.770205 done.
10097 18:04:10.770618
10098 18:04:10.770935 MAC: 00:24:32:30:78:52
10099 18:04:10.771326
10100 18:04:10.773121 Sending DHCP discover... done.
10101 18:04:10.773529
10102 18:04:10.775983 Waiting for reply... done.
10103 18:04:10.776450
10104 18:04:10.779371 Sending DHCP request... done.
10105 18:04:10.779786
10106 18:04:10.784614 Waiting for reply... done.
10107 18:04:10.785054
10108 18:04:10.785389 My ip is 192.168.201.14
10109 18:04:10.785694
10110 18:04:10.788196 The DHCP server ip is 192.168.201.1
10111 18:04:10.788605
10112 18:04:10.794981 TFTP server IP predefined by user: 192.168.201.1
10113 18:04:10.795507
10114 18:04:10.801307 Bootfile predefined by user: 14291408/tftp-deploy-n4a6lwod/kernel/image.itb
10115 18:04:10.801725
10116 18:04:10.802072 Sending tftp read request... done.
10117 18:04:10.804618
10118 18:04:10.811394 Waiting for the transfer...
10119 18:04:10.811915
10120 18:04:11.516862 00000000 ################################################################
10121 18:04:11.517419
10122 18:04:12.223263 00080000 ################################################################
10123 18:04:12.223777
10124 18:04:12.920592 00100000 ################################################################
10125 18:04:12.921304
10126 18:04:13.611880 00180000 ################################################################
10127 18:04:13.612382
10128 18:04:14.284836 00200000 ################################################################
10129 18:04:14.285384
10130 18:04:14.952964 00280000 ################################################################
10131 18:04:14.953241
10132 18:04:15.619982 00300000 ################################################################
10133 18:04:15.620662
10134 18:04:16.294872 00380000 ################################################################
10135 18:04:16.295229
10136 18:04:16.922372 00400000 ################################################################
10137 18:04:16.922891
10138 18:04:17.595613 00480000 ################################################################
10139 18:04:17.596288
10140 18:04:18.275117 00500000 ################################################################
10141 18:04:18.275644
10142 18:04:18.945164 00580000 ################################################################
10143 18:04:18.945298
10144 18:04:19.578801 00600000 ################################################################
10145 18:04:19.579436
10146 18:04:20.200690 00680000 ################################################################
10147 18:04:20.200826
10148 18:04:20.832237 00700000 ################################################################
10149 18:04:20.832366
10150 18:04:21.527029 00780000 ################################################################
10151 18:04:21.527543
10152 18:04:22.220891 00800000 ################################################################
10153 18:04:22.221079
10154 18:04:22.778414 00880000 ################################################################
10155 18:04:22.778563
10156 18:04:23.344683 00900000 ################################################################
10157 18:04:23.344829
10158 18:04:23.894240 00980000 ################################################################
10159 18:04:23.894384
10160 18:04:24.463120 00a00000 ################################################################
10161 18:04:24.463252
10162 18:04:25.023389 00a80000 ################################################################
10163 18:04:25.023530
10164 18:04:25.575797 00b00000 ################################################################
10165 18:04:25.575937
10166 18:04:26.127455 00b80000 ################################################################
10167 18:04:26.127602
10168 18:04:26.675453 00c00000 ################################################################
10169 18:04:26.675587
10170 18:04:27.230951 00c80000 ################################################################
10171 18:04:27.231125
10172 18:04:27.777498 00d00000 ################################################################
10173 18:04:27.777631
10174 18:04:28.317695 00d80000 ################################################################
10175 18:04:28.317874
10176 18:04:28.859578 00e00000 ################################################################
10177 18:04:28.859714
10178 18:04:29.401701 00e80000 ################################################################
10179 18:04:29.401864
10180 18:04:29.952928 00f00000 ################################################################
10181 18:04:29.953113
10182 18:04:30.501483 00f80000 ################################################################
10183 18:04:30.501630
10184 18:04:31.046041 01000000 ################################################################
10185 18:04:31.046205
10186 18:04:31.595621 01080000 ################################################################
10187 18:04:31.595772
10188 18:04:32.142350 01100000 ################################################################
10189 18:04:32.142492
10190 18:04:32.686708 01180000 ################################################################
10191 18:04:32.686846
10192 18:04:33.228521 01200000 ################################################################
10193 18:04:33.228668
10194 18:04:33.756339 01280000 ################################################################
10195 18:04:33.756493
10196 18:04:34.291840 01300000 ################################################################
10197 18:04:34.291972
10198 18:04:34.845235 01380000 ################################################################
10199 18:04:34.845366
10200 18:04:35.405021 01400000 ################################################################
10201 18:04:35.405158
10202 18:04:35.959257 01480000 ################################################################
10203 18:04:35.959407
10204 18:04:36.531162 01500000 ################################################################
10205 18:04:36.531323
10206 18:04:37.107679 01580000 ################################################################
10207 18:04:37.107824
10208 18:04:37.668704 01600000 ################################################################
10209 18:04:37.668839
10210 18:04:38.223326 01680000 ################################################################
10211 18:04:38.223491
10212 18:04:38.793717 01700000 ################################################################
10213 18:04:38.793855
10214 18:04:39.361938 01780000 ################################################################
10215 18:04:39.362363
10216 18:04:39.944306 01800000 ################################################################
10217 18:04:39.944444
10218 18:04:40.516452 01880000 ################################################################
10219 18:04:40.516583
10220 18:04:41.171091 01900000 ################################################################
10221 18:04:41.171574
10222 18:04:41.879904 01980000 ################################################################
10223 18:04:41.880445
10224 18:04:42.554083 01a00000 ################################################################
10225 18:04:42.554575
10226 18:04:43.260707 01a80000 ################################################################
10227 18:04:43.261356
10228 18:04:43.918161 01b00000 ################################################################
10229 18:04:43.918655
10230 18:04:44.557160 01b80000 ################################################################
10231 18:04:44.557333
10232 18:04:45.152416 01c00000 ################################################################
10233 18:04:45.152568
10234 18:04:45.806341 01c80000 ################################################################
10235 18:04:45.806882
10236 18:04:46.513363 01d00000 ################################################################
10237 18:04:46.513846
10238 18:04:47.162589 01d80000 ################################################################
10239 18:04:47.162874
10240 18:04:47.750398 01e00000 ################################################################
10241 18:04:47.750533
10242 18:04:48.298492 01e80000 ################################################################
10243 18:04:48.298669
10244 18:04:48.865255 01f00000 ################################################################
10245 18:04:48.865389
10246 18:04:49.433178 01f80000 ################################################################
10247 18:04:49.433315
10248 18:04:50.014312 02000000 ################################################################
10249 18:04:50.014443
10250 18:04:50.586160 02080000 ################################################################
10251 18:04:50.586293
10252 18:04:51.176958 02100000 ################################################################
10253 18:04:51.177109
10254 18:04:51.778647 02180000 ################################################################
10255 18:04:51.778806
10256 18:04:52.376673 02200000 ################################################################
10257 18:04:52.377211
10258 18:04:53.064109 02280000 ################################################################
10259 18:04:53.064601
10260 18:04:53.745771 02300000 ################################################################
10261 18:04:53.746547
10262 18:04:54.423553 02380000 ################################################################
10263 18:04:54.423697
10264 18:04:55.050716 02400000 ################################################################
10265 18:04:55.051210
10266 18:04:55.742085 02480000 ################################################################
10267 18:04:55.742563
10268 18:04:56.392004 02500000 ################################################################
10269 18:04:56.392163
10270 18:04:56.947757 02580000 ################################################################
10271 18:04:56.947896
10272 18:04:57.492214 02600000 ################################################################
10273 18:04:57.492457
10274 18:04:58.042664 02680000 ################################################################
10275 18:04:58.042801
10276 18:04:58.671174 02700000 ################################################################
10277 18:04:58.671691
10278 18:04:59.224791 02780000 ################################################################
10279 18:04:59.224931
10280 18:04:59.788049 02800000 ################################################################
10281 18:04:59.788216
10282 18:05:00.369726 02880000 ################################################################
10283 18:05:00.369877
10284 18:05:01.029142 02900000 ################################################################
10285 18:05:01.029286
10286 18:05:01.644278 02980000 ################################################################
10287 18:05:01.644419
10288 18:05:02.256808 02a00000 ################################################################
10289 18:05:02.257432
10290 18:05:02.923953 02a80000 ################################################################
10291 18:05:02.924456
10292 18:05:03.591665 02b00000 ################################################################
10293 18:05:03.592228
10294 18:05:04.265850 02b80000 ################################################################
10295 18:05:04.266366
10296 18:05:04.873442 02c00000 ################################################################
10297 18:05:04.873637
10298 18:05:05.527476 02c80000 ################################################################
10299 18:05:05.528021
10300 18:05:06.179758 02d00000 ################################################################
10301 18:05:06.180255
10302 18:05:06.769450 02d80000 ################################################################
10303 18:05:06.769591
10304 18:05:07.387905 02e00000 ################################################################
10305 18:05:07.388455
10306 18:05:08.040751 02e80000 ################################################################
10307 18:05:08.041305
10308 18:05:08.712292 02f00000 ################################################################
10309 18:05:08.712959
10310 18:05:09.369599 02f80000 ################################################################
10311 18:05:09.370086
10312 18:05:09.924458 03000000 ################################################################
10313 18:05:09.924588
10314 18:05:10.454455 03080000 ################################################################
10315 18:05:10.454638
10316 18:05:11.011407 03100000 ################################################################
10317 18:05:11.011593
10318 18:05:11.559403 03180000 ################################################################
10319 18:05:11.559545
10320 18:05:12.089134 03200000 ################################################################
10321 18:05:12.089282
10322 18:05:12.625601 03280000 ################################################################
10323 18:05:12.625741
10324 18:05:13.153314 03300000 ################################################################
10325 18:05:13.153451
10326 18:05:13.541730 03380000 ################################################ done.
10327 18:05:13.541870
10328 18:05:13.544855 The bootfile was 54391018 bytes long.
10329 18:05:13.544949
10330 18:05:13.548840 Sending tftp read request... done.
10331 18:05:13.548930
10332 18:05:13.549006 Waiting for the transfer...
10333 18:05:13.549069
10334 18:05:13.551852 00000000 # done.
10335 18:05:13.551938
10336 18:05:13.558875 Command line loaded dynamically from TFTP file: 14291408/tftp-deploy-n4a6lwod/kernel/cmdline
10337 18:05:13.558962
10338 18:05:13.571710 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10339 18:05:13.571804
10340 18:05:13.575010 Loading FIT.
10341 18:05:13.575094
10342 18:05:13.578419 Image ramdisk-1 has 41216624 bytes.
10343 18:05:13.578500
10344 18:05:13.578565 Image fdt-1 has 47258 bytes.
10345 18:05:13.578626
10346 18:05:13.581875 Image kernel-1 has 13125101 bytes.
10347 18:05:13.581955
10348 18:05:13.591716 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10349 18:05:13.591802
10350 18:05:13.608329 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10351 18:05:13.608434
10352 18:05:13.614963 Choosing best match conf-1 for compat google,spherion-rev2.
10353 18:05:13.618872
10354 18:05:13.623923 Connected to device vid:did:rid of 1ae0:0028:00
10355 18:05:13.631656
10356 18:05:13.635223 tpm_get_response: command 0x17b, return code 0x0
10357 18:05:13.635307
10358 18:05:13.638335 ec_init: CrosEC protocol v3 supported (256, 248)
10359 18:05:13.643673
10360 18:05:13.647244 tpm_cleanup: add release locality here.
10361 18:05:13.647326
10362 18:05:13.647390 Shutting down all USB controllers.
10363 18:05:13.647451
10364 18:05:13.650588 Removing current net device
10365 18:05:13.650675
10366 18:05:13.656845 Exiting depthcharge with code 4 at timestamp: 98650853
10367 18:05:13.656963
10368 18:05:13.660258 LZMA decompressing kernel-1 to 0x821a6718
10369 18:05:13.660339
10370 18:05:13.663890 LZMA decompressing kernel-1 to 0x40000000
10371 18:05:15.280854
10372 18:05:15.281023 jumping to kernel
10373 18:05:15.281612 end: 2.2.4 bootloader-commands (duration 00:01:11) [common]
10374 18:05:15.281719 start: 2.2.5 auto-login-action (timeout 00:03:14) [common]
10375 18:05:15.281800 Setting prompt string to ['Linux version [0-9]']
10376 18:05:15.281870 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10377 18:05:15.281979 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10378 18:05:15.363086
10379 18:05:15.366674 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10380 18:05:15.370047 start: 2.2.5.1 login-action (timeout 00:03:14) [common]
10381 18:05:15.370141 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10382 18:05:15.370217 Setting prompt string to []
10383 18:05:15.370294 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10384 18:05:15.370367 Using line separator: #'\n'#
10385 18:05:15.370427 No login prompt set.
10386 18:05:15.370490 Parsing kernel messages
10387 18:05:15.370545 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10388 18:05:15.370648 [login-action] Waiting for messages, (timeout 00:03:14)
10389 18:05:15.370714 Waiting using forced prompt support (timeout 00:01:37)
10390 18:05:15.390051 [ 0.000000] Linux version 6.1.92-cip22 (KernelCI@build-j225340-arm64-gcc-10-defconfig-arm64-chromebook-x2t4v) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue Jun 11 17:44:14 UTC 2024
10391 18:05:15.392966 [ 0.000000] random: crng init done
10392 18:05:15.396540 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10393 18:05:15.399875 [ 0.000000] efi: UEFI not found.
10394 18:05:15.410113 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10395 18:05:15.416302 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10396 18:05:15.426293 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10397 18:05:15.436403 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10398 18:05:15.442938 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10399 18:05:15.446537 [ 0.000000] printk: bootconsole [mtk8250] enabled
10400 18:05:15.454816 [ 0.000000] NUMA: No NUMA configuration found
10401 18:05:15.461832 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10402 18:05:15.468244 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10403 18:05:15.468359 [ 0.000000] Zone ranges:
10404 18:05:15.474890 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10405 18:05:15.478504 [ 0.000000] DMA32 empty
10406 18:05:15.485049 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10407 18:05:15.488587 [ 0.000000] Movable zone start for each node
10408 18:05:15.491974 [ 0.000000] Early memory node ranges
10409 18:05:15.498454 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10410 18:05:15.504842 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10411 18:05:15.511768 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10412 18:05:15.518268 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10413 18:05:15.524894 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10414 18:05:15.531528 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10415 18:05:15.588264 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10416 18:05:15.594671 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10417 18:05:15.600971 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10418 18:05:15.604525 [ 0.000000] psci: probing for conduit method from DT.
10419 18:05:15.611436 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10420 18:05:15.614368 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10421 18:05:15.620823 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10422 18:05:15.624501 [ 0.000000] psci: SMC Calling Convention v1.2
10423 18:05:15.631131 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10424 18:05:15.634316 [ 0.000000] Detected VIPT I-cache on CPU0
10425 18:05:15.640774 [ 0.000000] CPU features: detected: GIC system register CPU interface
10426 18:05:15.647597 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10427 18:05:15.654183 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10428 18:05:15.660658 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10429 18:05:15.667635 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10430 18:05:15.674143 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10431 18:05:15.680849 [ 0.000000] alternatives: applying boot alternatives
10432 18:05:15.684234 [ 0.000000] Fallback order for Node 0: 0
10433 18:05:15.693891 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10434 18:05:15.693976 [ 0.000000] Policy zone: Normal
10435 18:05:15.710769 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10436 18:05:15.720547 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10437 18:05:15.732012 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10438 18:05:15.741950 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10439 18:05:15.749150 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10440 18:05:15.752094 <6>[ 0.000000] software IO TLB: area num 8.
10441 18:05:15.808492 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10442 18:05:15.957956 <6>[ 0.000000] Memory: 7923812K/8385536K available (18112K kernel code, 4120K rwdata, 22644K rodata, 8512K init, 616K bss, 428956K reserved, 32768K cma-reserved)
10443 18:05:15.964401 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10444 18:05:15.971116 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10445 18:05:15.974692 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10446 18:05:15.981382 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10447 18:05:15.987951 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10448 18:05:15.991443 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10449 18:05:16.000849 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10450 18:05:16.007485 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10451 18:05:16.011109 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10452 18:05:16.018917 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10453 18:05:16.021911 <6>[ 0.000000] GICv3: 608 SPIs implemented
10454 18:05:16.028803 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10455 18:05:16.032243 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10456 18:05:16.035443 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10457 18:05:16.045168 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10458 18:05:16.055447 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10459 18:05:16.068574 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10460 18:05:16.075380 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10461 18:05:16.084451 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10462 18:05:16.097682 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10463 18:05:16.104357 <6>[ 0.000001] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10464 18:05:16.110906 <6>[ 0.009177] Console: colour dummy device 80x25
10465 18:05:16.120924 <6>[ 0.013907] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10466 18:05:16.123940 <6>[ 0.024414] pid_max: default: 32768 minimum: 301
10467 18:05:16.130655 <6>[ 0.029286] LSM: Security Framework initializing
10468 18:05:16.137197 <6>[ 0.034225] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10469 18:05:16.147485 <6>[ 0.042040] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10470 18:05:16.153921 <6>[ 0.051464] cblist_init_generic: Setting adjustable number of callback queues.
10471 18:05:16.160640 <6>[ 0.058909] cblist_init_generic: Setting shift to 3 and lim to 1.
10472 18:05:16.167244 <6>[ 0.065247] cblist_init_generic: Setting adjustable number of callback queues.
10473 18:05:16.174151 <6>[ 0.072674] cblist_init_generic: Setting shift to 3 and lim to 1.
10474 18:05:16.181005 <6>[ 0.079113] rcu: Hierarchical SRCU implementation.
10475 18:05:16.187751 <6>[ 0.084128] rcu: Max phase no-delay instances is 1000.
10476 18:05:16.190643 <6>[ 0.091187] EFI services will not be available.
10477 18:05:16.197217 <6>[ 0.096146] smp: Bringing up secondary CPUs ...
10478 18:05:16.205177 <6>[ 0.101195] Detected VIPT I-cache on CPU1
10479 18:05:16.211721 <6>[ 0.101269] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10480 18:05:16.218242 <6>[ 0.101301] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10481 18:05:16.221836 <6>[ 0.101633] Detected VIPT I-cache on CPU2
10482 18:05:16.228061 <6>[ 0.101684] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10483 18:05:16.234632 <6>[ 0.101700] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10484 18:05:16.241223 <6>[ 0.101957] Detected VIPT I-cache on CPU3
10485 18:05:16.248224 <6>[ 0.102004] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10486 18:05:16.254659 <6>[ 0.102018] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10487 18:05:16.258454 <6>[ 0.102322] CPU features: detected: Spectre-v4
10488 18:05:16.264899 <6>[ 0.102328] CPU features: detected: Spectre-BHB
10489 18:05:16.268444 <6>[ 0.102333] Detected PIPT I-cache on CPU4
10490 18:05:16.274481 <6>[ 0.102391] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10491 18:05:16.281346 <6>[ 0.102408] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10492 18:05:16.287890 <6>[ 0.102698] Detected PIPT I-cache on CPU5
10493 18:05:16.294611 <6>[ 0.102761] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10494 18:05:16.301150 <6>[ 0.102776] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10495 18:05:16.304944 <6>[ 0.103060] Detected PIPT I-cache on CPU6
10496 18:05:16.311538 <6>[ 0.103124] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10497 18:05:16.318093 <6>[ 0.103140] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10498 18:05:16.321972 <6>[ 0.103436] Detected PIPT I-cache on CPU7
10499 18:05:16.331756 <6>[ 0.103502] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10500 18:05:16.338316 <6>[ 0.103518] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10501 18:05:16.341304 <6>[ 0.103566] smp: Brought up 1 node, 8 CPUs
10502 18:05:16.344945 <6>[ 0.244987] SMP: Total of 8 processors activated.
10503 18:05:16.351522 <6>[ 0.249909] CPU features: detected: 32-bit EL0 Support
10504 18:05:16.361207 <6>[ 0.255272] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10505 18:05:16.367826 <6>[ 0.264073] CPU features: detected: Common not Private translations
10506 18:05:16.371303 <6>[ 0.270548] CPU features: detected: CRC32 instructions
10507 18:05:16.377696 <6>[ 0.275899] CPU features: detected: RCpc load-acquire (LDAPR)
10508 18:05:16.384282 <6>[ 0.281896] CPU features: detected: LSE atomic instructions
10509 18:05:16.391357 <6>[ 0.287678] CPU features: detected: Privileged Access Never
10510 18:05:16.394760 <6>[ 0.293493] CPU features: detected: RAS Extension Support
10511 18:05:16.401296 <6>[ 0.299102] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10512 18:05:16.407710 <6>[ 0.306322] CPU: All CPU(s) started at EL2
10513 18:05:16.414203 <6>[ 0.310638] alternatives: applying system-wide alternatives
10514 18:05:16.423073 <6>[ 0.321509] devtmpfs: initialized
10515 18:05:16.435283 <6>[ 0.330427] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10516 18:05:16.445180 <6>[ 0.340384] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10517 18:05:16.448203 <6>[ 0.348248] pinctrl core: initialized pinctrl subsystem
10518 18:05:16.456509 <6>[ 0.354936] DMI not present or invalid.
10519 18:05:16.463197 <6>[ 0.359351] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10520 18:05:16.469969 <6>[ 0.366208] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10521 18:05:16.479463 <6>[ 0.373797] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10522 18:05:16.486648 <6>[ 0.382017] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10523 18:05:16.493154 <6>[ 0.390261] audit: initializing netlink subsys (disabled)
10524 18:05:16.499843 <5>[ 0.395954] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10525 18:05:16.506605 <6>[ 0.396672] thermal_sys: Registered thermal governor 'step_wise'
10526 18:05:16.512670 <6>[ 0.403921] thermal_sys: Registered thermal governor 'power_allocator'
10527 18:05:16.516071 <6>[ 0.410176] cpuidle: using governor menu
10528 18:05:16.523188 <6>[ 0.421138] NET: Registered PF_QIPCRTR protocol family
10529 18:05:16.529643 <6>[ 0.426612] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10530 18:05:16.536436 <6>[ 0.433716] ASID allocator initialised with 32768 entries
10531 18:05:16.539359 <6>[ 0.440300] Serial: AMBA PL011 UART driver
10532 18:05:16.550468 <4>[ 0.449125] Trying to register duplicate clock ID: 134
10533 18:05:16.608484 <6>[ 0.510567] KASLR enabled
10534 18:05:16.623141 <6>[ 0.518296] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10535 18:05:16.629926 <6>[ 0.525312] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10536 18:05:16.636467 <6>[ 0.531800] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10537 18:05:16.642900 <6>[ 0.538805] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10538 18:05:16.649852 <6>[ 0.545294] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10539 18:05:16.656691 <6>[ 0.552297] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10540 18:05:16.662892 <6>[ 0.558785] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10541 18:05:16.669676 <6>[ 0.565791] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10542 18:05:16.672762 <6>[ 0.573322] ACPI: Interpreter disabled.
10543 18:05:16.681141 <6>[ 0.579754] iommu: Default domain type: Translated
10544 18:05:16.687708 <6>[ 0.584865] iommu: DMA domain TLB invalidation policy: strict mode
10545 18:05:16.691148 <5>[ 0.591528] SCSI subsystem initialized
10546 18:05:16.697853 <6>[ 0.595695] usbcore: registered new interface driver usbfs
10547 18:05:16.704566 <6>[ 0.601428] usbcore: registered new interface driver hub
10548 18:05:16.707667 <6>[ 0.606979] usbcore: registered new device driver usb
10549 18:05:16.714143 <6>[ 0.613080] pps_core: LinuxPPS API ver. 1 registered
10550 18:05:16.724406 <6>[ 0.618273] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10551 18:05:16.727349 <6>[ 0.627621] PTP clock support registered
10552 18:05:16.730925 <6>[ 0.631865] EDAC MC: Ver: 3.0.0
10553 18:05:16.738668 <6>[ 0.637017] FPGA manager framework
10554 18:05:16.741616 <6>[ 0.640706] Advanced Linux Sound Architecture Driver Initialized.
10555 18:05:16.745577 <6>[ 0.647493] vgaarb: loaded
10556 18:05:16.752018 <6>[ 0.650650] clocksource: Switched to clocksource arch_sys_counter
10557 18:05:16.758602 <5>[ 0.657096] VFS: Disk quotas dquot_6.6.0
10558 18:05:16.765841 <6>[ 0.661283] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10559 18:05:16.768872 <6>[ 0.668474] pnp: PnP ACPI: disabled
10560 18:05:16.776541 <6>[ 0.675309] NET: Registered PF_INET protocol family
10561 18:05:16.786544 <6>[ 0.680909] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10562 18:05:16.797734 <6>[ 0.693246] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10563 18:05:16.807884 <6>[ 0.702060] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10564 18:05:16.814709 <6>[ 0.710029] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10565 18:05:16.821159 <6>[ 0.718731] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10566 18:05:16.833625 <6>[ 0.728481] TCP: Hash tables configured (established 65536 bind 65536)
10567 18:05:16.840304 <6>[ 0.735352] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10568 18:05:16.846912 <6>[ 0.742549] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10569 18:05:16.853579 <6>[ 0.750227] NET: Registered PF_UNIX/PF_LOCAL protocol family
10570 18:05:16.859967 <6>[ 0.756304] RPC: Registered named UNIX socket transport module.
10571 18:05:16.863316 <6>[ 0.762453] RPC: Registered udp transport module.
10572 18:05:16.869912 <6>[ 0.767385] RPC: Registered tcp transport module.
10573 18:05:16.876802 <6>[ 0.772318] RPC: Registered tcp NFSv4.1 backchannel transport module.
10574 18:05:16.879774 <6>[ 0.778982] PCI: CLS 0 bytes, default 64
10575 18:05:16.883251 <6>[ 0.783325] Unpacking initramfs...
10576 18:05:16.907282 <6>[ 0.802769] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10577 18:05:16.917298 <6>[ 0.811423] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10578 18:05:16.920957 <6>[ 0.820263] kvm [1]: IPA Size Limit: 40 bits
10579 18:05:16.927420 <6>[ 0.824792] kvm [1]: GICv3: no GICV resource entry
10580 18:05:16.930721 <6>[ 0.829814] kvm [1]: disabling GICv2 emulation
10581 18:05:16.937316 <6>[ 0.834501] kvm [1]: GIC system register CPU interface enabled
10582 18:05:16.940365 <6>[ 0.840657] kvm [1]: vgic interrupt IRQ18
10583 18:05:16.947020 <6>[ 0.845009] kvm [1]: VHE mode initialized successfully
10584 18:05:16.953698 <5>[ 0.851283] Initialise system trusted keyrings
10585 18:05:16.960272 <6>[ 0.856155] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10586 18:05:16.967650 <6>[ 0.866251] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10587 18:05:16.974192 <5>[ 0.872666] NFS: Registering the id_resolver key type
10588 18:05:16.977331 <5>[ 0.877963] Key type id_resolver registered
10589 18:05:16.983941 <5>[ 0.882378] Key type id_legacy registered
10590 18:05:16.991033 <6>[ 0.886669] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10591 18:05:16.997644 <6>[ 0.893591] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10592 18:05:17.003919 <6>[ 0.901294] 9p: Installing v9fs 9p2000 file system support
10593 18:05:17.039571 <5>[ 0.938437] Key type asymmetric registered
10594 18:05:17.042898 <5>[ 0.942768] Asymmetric key parser 'x509' registered
10595 18:05:17.053076 <6>[ 0.947914] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10596 18:05:17.056678 <6>[ 0.955529] io scheduler mq-deadline registered
10597 18:05:17.059743 <6>[ 0.960293] io scheduler kyber registered
10598 18:05:17.078408 <6>[ 0.977258] EINJ: ACPI disabled.
10599 18:05:17.110348 <4>[ 1.002603] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10600 18:05:17.120478 <4>[ 1.013287] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10601 18:05:17.135630 <6>[ 1.034491] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10602 18:05:17.143977 <6>[ 1.042522] printk: console [ttyS0] disabled
10603 18:05:17.171621 <6>[ 1.067170] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10604 18:05:17.178300 <6>[ 1.076646] printk: console [ttyS0] enabled
10605 18:05:17.181740 <6>[ 1.076646] printk: console [ttyS0] enabled
10606 18:05:17.188501 <6>[ 1.085537] printk: bootconsole [mtk8250] disabled
10607 18:05:17.191593 <6>[ 1.085537] printk: bootconsole [mtk8250] disabled
10608 18:05:17.198214 <6>[ 1.096907] SuperH (H)SCI(F) driver initialized
10609 18:05:17.201657 <6>[ 1.102198] msm_serial: driver initialized
10610 18:05:17.215885 <6>[ 1.111190] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10611 18:05:17.226172 <6>[ 1.119735] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10612 18:05:17.232598 <6>[ 1.128276] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10613 18:05:17.242204 <6>[ 1.136906] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10614 18:05:17.249119 <6>[ 1.145613] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10615 18:05:17.259194 <6>[ 1.154347] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10616 18:05:17.269095 <6>[ 1.162888] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10617 18:05:17.275461 <6>[ 1.171699] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10618 18:05:17.285903 <6>[ 1.180245] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10619 18:05:17.297248 <6>[ 1.196078] loop: module loaded
10620 18:05:17.303798 <6>[ 1.202175] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10621 18:05:17.327305 <4>[ 1.225870] mtk-pmic-keys: Failed to locate of_node [id: -1]
10622 18:05:17.334161 <6>[ 1.232994] megasas: 07.719.03.00-rc1
10623 18:05:17.344308 <6>[ 1.242786] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10624 18:05:17.351124 <6>[ 1.250018] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10625 18:05:17.368001 <6>[ 1.266450] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10626 18:05:17.423369 <6>[ 1.315454] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10627 18:05:18.601204 <6>[ 2.500110] Freeing initrd memory: 40244K
10628 18:05:18.612920 <6>[ 2.511877] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10629 18:05:18.624086 <6>[ 2.522815] tun: Universal TUN/TAP device driver, 1.6
10630 18:05:18.627073 <6>[ 2.528862] thunder_xcv, ver 1.0
10631 18:05:18.630487 <6>[ 2.532369] thunder_bgx, ver 1.0
10632 18:05:18.633990 <6>[ 2.535865] nicpf, ver 1.0
10633 18:05:18.644508 <6>[ 2.539870] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10634 18:05:18.647514 <6>[ 2.547345] hns3: Copyright (c) 2017 Huawei Corporation.
10635 18:05:18.651088 <6>[ 2.552934] hclge is initializing
10636 18:05:18.658041 <6>[ 2.556512] e1000: Intel(R) PRO/1000 Network Driver
10637 18:05:18.664486 <6>[ 2.561642] e1000: Copyright (c) 1999-2006 Intel Corporation.
10638 18:05:18.668074 <6>[ 2.567654] e1000e: Intel(R) PRO/1000 Network Driver
10639 18:05:18.674523 <6>[ 2.572869] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10640 18:05:18.680733 <6>[ 2.579054] igb: Intel(R) Gigabit Ethernet Network Driver
10641 18:05:18.687776 <6>[ 2.584704] igb: Copyright (c) 2007-2014 Intel Corporation.
10642 18:05:18.694109 <6>[ 2.590543] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10643 18:05:18.701054 <6>[ 2.597061] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10644 18:05:18.703999 <6>[ 2.603516] sky2: driver version 1.30
10645 18:05:18.711015 <6>[ 2.608435] usbcore: registered new device driver r8152-cfgselector
10646 18:05:18.717471 <6>[ 2.614969] usbcore: registered new interface driver r8152
10647 18:05:18.720738 <6>[ 2.620787] VFIO - User Level meta-driver version: 0.3
10648 18:05:18.730418 <6>[ 2.628995] usbcore: registered new interface driver usb-storage
10649 18:05:18.736729 <6>[ 2.635437] usbcore: registered new device driver onboard-usb-hub
10650 18:05:18.745874 <6>[ 2.644552] mt6397-rtc mt6359-rtc: registered as rtc0
10651 18:05:18.755841 <6>[ 2.650016] mt6397-rtc mt6359-rtc: setting system clock to 2024-06-11T18:05:18 UTC (1718129118)
10652 18:05:18.758737 <6>[ 2.659577] i2c_dev: i2c /dev entries driver
10653 18:05:18.772731 <4>[ 2.671617] cpu cpu0: supply cpu not found, using dummy regulator
10654 18:05:18.779214 <4>[ 2.678041] cpu cpu1: supply cpu not found, using dummy regulator
10655 18:05:18.786526 <4>[ 2.684448] cpu cpu2: supply cpu not found, using dummy regulator
10656 18:05:18.792909 <4>[ 2.690846] cpu cpu3: supply cpu not found, using dummy regulator
10657 18:05:18.799428 <4>[ 2.697264] cpu cpu4: supply cpu not found, using dummy regulator
10658 18:05:18.806184 <4>[ 2.703665] cpu cpu5: supply cpu not found, using dummy regulator
10659 18:05:18.813017 <4>[ 2.710063] cpu cpu6: supply cpu not found, using dummy regulator
10660 18:05:18.819497 <4>[ 2.716460] cpu cpu7: supply cpu not found, using dummy regulator
10661 18:05:18.839107 <6>[ 2.738121] cpu cpu0: EM: created perf domain
10662 18:05:18.842473 <6>[ 2.743061] cpu cpu4: EM: created perf domain
10663 18:05:18.849903 <6>[ 2.748631] sdhci: Secure Digital Host Controller Interface driver
10664 18:05:18.856217 <6>[ 2.755063] sdhci: Copyright(c) Pierre Ossman
10665 18:05:18.863277 <6>[ 2.760014] Synopsys Designware Multimedia Card Interface Driver
10666 18:05:18.869698 <6>[ 2.766656] sdhci-pltfm: SDHCI platform and OF driver helper
10667 18:05:18.873300 <6>[ 2.766786] mmc0: CQHCI version 5.10
10668 18:05:18.879963 <6>[ 2.776642] ledtrig-cpu: registered to indicate activity on CPUs
10669 18:05:18.886392 <6>[ 2.783765] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10670 18:05:18.892652 <6>[ 2.790831] usbcore: registered new interface driver usbhid
10671 18:05:18.896002 <6>[ 2.796652] usbhid: USB HID core driver
10672 18:05:18.902852 <6>[ 2.800845] spi_master spi0: will run message pump with realtime priority
10673 18:05:18.947412 <6>[ 2.839489] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10674 18:05:18.963071 <6>[ 2.855336] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10675 18:05:18.970027 <6>[ 2.867969] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x17414
10676 18:05:18.977183 <6>[ 2.875735] cros-ec-spi spi0.0: Chrome EC device registered
10677 18:05:18.983748 <6>[ 2.881731] mmc0: Command Queue Engine enabled
10678 18:05:18.990372 <6>[ 2.886475] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10679 18:05:18.993199 <6>[ 2.894161] mmcblk0: mmc0:0001 DA4128 116 GiB
10680 18:05:19.003697 <6>[ 2.902679] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10681 18:05:19.011014 <6>[ 2.910029] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10682 18:05:19.017984 <6>[ 2.916059] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10683 18:05:19.027738 <6>[ 2.921131] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10684 18:05:19.034848 <6>[ 2.921958] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10685 18:05:19.037836 <6>[ 2.931968] NET: Registered PF_PACKET protocol family
10686 18:05:19.044570 <6>[ 2.942512] 9pnet: Installing 9P2000 support
10687 18:05:19.047904 <5>[ 2.947078] Key type dns_resolver registered
10688 18:05:19.050848 <6>[ 2.952063] registered taskstats version 1
10689 18:05:19.057313 <5>[ 2.956453] Loading compiled-in X.509 certificates
10690 18:05:19.087978 <4>[ 2.980007] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10691 18:05:19.097465 <4>[ 2.990803] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10692 18:05:19.112295 <6>[ 3.010814] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10693 18:05:19.119398 <6>[ 3.017886] xhci-mtk 11200000.usb: xHCI Host Controller
10694 18:05:19.125510 <6>[ 3.023410] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10695 18:05:19.135837 <6>[ 3.031291] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10696 18:05:19.142497 <6>[ 3.040741] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10697 18:05:19.148922 <6>[ 3.046902] xhci-mtk 11200000.usb: xHCI Host Controller
10698 18:05:19.155552 <6>[ 3.052398] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10699 18:05:19.162092 <6>[ 3.060052] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10700 18:05:19.169171 <6>[ 3.067888] hub 1-0:1.0: USB hub found
10701 18:05:19.172428 <6>[ 3.071910] hub 1-0:1.0: 1 port detected
10702 18:05:19.179368 <6>[ 3.076202] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10703 18:05:19.185888 <6>[ 3.084916] hub 2-0:1.0: USB hub found
10704 18:05:19.189557 <6>[ 3.088938] hub 2-0:1.0: 1 port detected
10705 18:05:19.196564 <6>[ 3.095701] mtk-msdc 11f70000.mmc: Got CD GPIO
10706 18:05:19.211057 <6>[ 3.106281] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10707 18:05:19.220703 <6>[ 3.114682] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10708 18:05:19.227051 <6>[ 3.123024] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10709 18:05:19.237568 <6>[ 3.131364] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10710 18:05:19.244129 <6>[ 3.139704] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10711 18:05:19.253594 <6>[ 3.148042] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10712 18:05:19.260488 <6>[ 3.156381] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10713 18:05:19.270141 <6>[ 3.164729] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10714 18:05:19.276807 <6>[ 3.173069] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10715 18:05:19.287342 <6>[ 3.181406] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10716 18:05:19.293703 <6>[ 3.189743] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10717 18:05:19.303345 <6>[ 3.198091] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10718 18:05:19.310473 <6>[ 3.206429] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10719 18:05:19.320105 <6>[ 3.214766] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10720 18:05:19.327133 <6>[ 3.223103] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10721 18:05:19.333598 <6>[ 3.231829] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10722 18:05:19.339845 <6>[ 3.238996] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10723 18:05:19.346716 <6>[ 3.245760] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10724 18:05:19.356905 <6>[ 3.252564] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10725 18:05:19.363518 <6>[ 3.259504] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10726 18:05:19.370285 <6>[ 3.266376] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10727 18:05:19.380104 <6>[ 3.275515] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10728 18:05:19.390141 <6>[ 3.284637] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10729 18:05:19.400120 <6>[ 3.293932] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10730 18:05:19.410272 <6>[ 3.303399] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10731 18:05:19.416777 <6>[ 3.312866] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10732 18:05:19.426688 <6>[ 3.321985] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10733 18:05:19.436661 <6>[ 3.331452] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10734 18:05:19.446390 <6>[ 3.340570] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10735 18:05:19.456474 <6>[ 3.349864] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10736 18:05:19.465916 <6>[ 3.360024] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10737 18:05:19.476277 <6>[ 3.371997] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10738 18:05:19.603058 <6>[ 3.498832] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10739 18:05:19.757770 <6>[ 3.656865] hub 1-1:1.0: USB hub found
10740 18:05:19.761280 <6>[ 3.661376] hub 1-1:1.0: 4 ports detected
10741 18:05:19.773689 <6>[ 3.672456] hub 1-1:1.0: USB hub found
10742 18:05:19.776482 <6>[ 3.676819] hub 1-1:1.0: 4 ports detected
10743 18:05:19.883612 <6>[ 3.779346] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10744 18:05:19.911316 <6>[ 3.809929] hub 2-1:1.0: USB hub found
10745 18:05:19.914262 <6>[ 3.814514] hub 2-1:1.0: 3 ports detected
10746 18:05:19.926046 <6>[ 3.825215] hub 2-1:1.0: USB hub found
10747 18:05:19.929572 <6>[ 3.829568] hub 2-1:1.0: 3 ports detected
10748 18:05:20.099122 <6>[ 3.995021] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10749 18:05:20.231517 <6>[ 4.130291] hub 1-1.4:1.0: USB hub found
10750 18:05:20.234326 <6>[ 4.134910] hub 1-1.4:1.0: 2 ports detected
10751 18:05:20.247155 <6>[ 4.146034] hub 1-1.4:1.0: USB hub found
10752 18:05:20.250107 <6>[ 4.150601] hub 1-1.4:1.0: 2 ports detected
10753 18:05:20.311533 <6>[ 4.207081] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10754 18:05:20.419602 <6>[ 4.315343] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10755 18:05:20.451697 <4>[ 4.347474] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10756 18:05:20.461817 <4>[ 4.356575] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10757 18:05:20.496998 <6>[ 4.396035] r8152 2-1.3:1.0 eth0: v1.12.13
10758 18:05:20.547255 <6>[ 4.442975] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10759 18:05:20.743336 <6>[ 4.638993] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10760 18:05:22.194611 <6>[ 6.094055] r8152 2-1.3:1.0 eth0: carrier on
10761 18:05:22.243873 <5>[ 6.118768] Sending DHCP requests ., OK
10762 18:05:22.250258 <6>[ 6.147095] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.14
10763 18:05:22.253797 <6>[ 6.155386] IP-Config: Complete:
10764 18:05:22.266697 <6>[ 6.158880] device=eth0, hwaddr=00:24:32:30:78:52, ipaddr=192.168.201.14, mask=255.255.255.0, gw=192.168.201.1
10765 18:05:22.273869 <6>[ 6.169586] host=mt8192-asurada-spherion-r0-cbg-3, domain=lava-rack, nis-domain=(none)
10766 18:05:22.280273 <6>[ 6.178198] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10767 18:05:22.287016 <6>[ 6.178207] nameserver0=192.168.201.1
10768 18:05:22.290302 <6>[ 6.190341] clk: Disabling unused clocks
10769 18:05:22.293803 <6>[ 6.195713] ALSA device list:
10770 18:05:22.296596 <6>[ 6.199097] No soundcards found.
10771 18:05:22.307309 <6>[ 6.206598] Freeing unused kernel memory: 8512K
10772 18:05:22.310793 <6>[ 6.211639] Run /init as init process
10773 18:05:22.340898 <6>[ 6.240183] NET: Registered PF_INET6 protocol family
10774 18:05:22.347356 <6>[ 6.246689] Segment Routing with IPv6
10775 18:05:22.350869 <6>[ 6.250665] In-situ OAM (IOAM) with IPv6
10776 18:05:22.390841 <30>[ 6.263587] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10777 18:05:22.397425 <30>[ 6.296680] systemd[1]: Detected architecture arm64.
10778 18:05:22.397573
10779 18:05:22.404257 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10780 18:05:22.404378
10781 18:05:22.416177 <30>[ 6.315013] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10782 18:05:22.536650 <30>[ 6.432730] systemd[1]: Queued start job for default target graphical.target.
10783 18:05:22.568546 <30>[ 6.464209] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10784 18:05:22.574583 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10785 18:05:22.595993 <30>[ 6.491612] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10786 18:05:22.602702 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10787 18:05:22.624130 <30>[ 6.519772] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10788 18:05:22.633491 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10789 18:05:22.651669 <30>[ 6.547634] systemd[1]: Created slice user.slice - User and Session Slice.
10790 18:05:22.657952 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10791 18:05:22.678432 <30>[ 6.570975] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10792 18:05:22.684904 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10793 18:05:22.706938 <30>[ 6.599530] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10794 18:05:22.713420 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10795 18:05:22.740866 <30>[ 6.627288] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10796 18:05:22.751054 <30>[ 6.647139] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10797 18:05:22.757796 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10798 18:05:22.775358 <30>[ 6.671167] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10799 18:05:22.782059 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10800 18:05:22.799078 <30>[ 6.694942] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10801 18:05:22.808606 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10802 18:05:22.823844 <30>[ 6.723045] systemd[1]: Reached target paths.target - Path Units.
10803 18:05:22.833554 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10804 18:05:22.851269 <30>[ 6.747412] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10805 18:05:22.857923 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10806 18:05:22.871688 <30>[ 6.770937] systemd[1]: Reached target slices.target - Slice Units.
10807 18:05:22.881329 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10808 18:05:22.895913 <30>[ 6.795424] systemd[1]: Reached target swap.target - Swaps.
10809 18:05:22.902472 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10810 18:05:22.923594 <30>[ 6.819459] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10811 18:05:22.933725 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10812 18:05:22.951320 <30>[ 6.847438] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10813 18:05:22.961568 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10814 18:05:22.980816 <30>[ 6.877080] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10815 18:05:22.991040 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10816 18:05:23.007816 <30>[ 6.903553] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10817 18:05:23.017726 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10818 18:05:23.035391 <30>[ 6.931611] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10819 18:05:23.041974 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10820 18:05:23.059441 <30>[ 6.955649] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10821 18:05:23.069516 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10822 18:05:23.088076 <30>[ 6.983774] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10823 18:05:23.097473 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10824 18:05:23.116146 <30>[ 7.012064] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10825 18:05:23.125796 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10826 18:05:23.166840 <30>[ 7.063023] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10827 18:05:23.173339 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10828 18:05:23.199592 <30>[ 7.095392] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10829 18:05:23.206007 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10830 18:05:23.235571 <30>[ 7.131416] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10831 18:05:23.241731 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10832 18:05:23.269738 <30>[ 7.159498] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10833 18:05:23.284106 <30>[ 7.180199] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10834 18:05:23.294111 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10835 18:05:23.316312 <30>[ 7.212538] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10836 18:05:23.322823 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10837 18:05:23.371437 <30>[ 7.267642] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10838 18:05:23.381716 Startin<6>[ 7.277032] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10839 18:05:23.388278 g [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10840 18:05:23.412142 <30>[ 7.308390] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10841 18:05:23.418832 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10842 18:05:23.471177 <30>[ 7.367569] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10843 18:05:23.481437 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10844 18:05:23.504257 <30>[ 7.400480] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10845 18:05:23.511273 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10846 18:05:23.563490 <30>[ 7.459697] systemd[1]: Starting systemd-journald.service - Journal Service...
10847 18:05:23.570339 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10848 18:05:23.593327 <30>[ 7.489338] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10849 18:05:23.599732 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10850 18:05:23.627649 <30>[ 7.520344] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10851 18:05:23.633981 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10852 18:05:23.660199 <30>[ 7.556422] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10853 18:05:23.670464 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10854 18:05:23.743654 <30>[ 7.640013] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10855 18:05:23.750741 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10856 18:05:23.772826 <30>[ 7.669095] systemd[1]: Started systemd-journald.service - Journal Service.
10857 18:05:23.779786 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10858 18:05:23.805354 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10859 18:05:23.823473 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10860 18:05:23.839373 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10861 18:05:23.855304 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10862 18:05:23.877687 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10863 18:05:23.901592 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10864 18:05:23.926146 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10865 18:05:23.946000 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10866 18:05:23.967969 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10867 18:05:23.992825 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10868 18:05:24.016583 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10869 18:05:24.037263 [[0;1;31mFAILED[0m] Failed to start [0;1;39msystemd-re…ount Root and Kernel File Systems.
10870 18:05:24.051859 See 'systemctl status systemd-remount-fs.service' for details.
10871 18:05:24.072494 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10872 18:05:24.093440 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10873 18:05:24.139313 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10874 18:05:24.159338 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10875 18:05:24.180925 <46>[ 8.077364] systemd-journald[197]: Received client request to flush runtime journal.
10876 18:05:24.199219 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10877 18:05:24.219250 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10878 18:05:24.239117 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10879 18:05:24.260993 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10880 18:05:24.280180 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10881 18:05:24.300368 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10882 18:05:24.320483 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10883 18:05:24.340395 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10884 18:05:24.395345 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10885 18:05:24.422629 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10886 18:05:24.439730 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10887 18:05:24.459139 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10888 18:05:24.495004 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10889 18:05:24.515246 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10890 18:05:24.538402 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10891 18:05:24.596313 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10892 18:05:24.621918 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10893 18:05:24.643737 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10894 18:05:24.704261 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10895 18:05:24.729063 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10896 18:05:24.765570 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10897 18:05:24.861194 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10898 18:05:24.879725 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10899 18:05:24.899876 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
10900 18:05:24.925760 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
10901 18:05:24.947011 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
10902 18:05:24.968004 <6>[ 8.864394] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10903 18:05:24.981137 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bu<6>[ 8.877552] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10904 18:05:24.991411 s System Message<6>[ 8.880345] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10905 18:05:24.991493 Bus Socket.
10906 18:05:25.001291 <6>[ 8.886470] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10907 18:05:25.007742 <6>[ 8.895264] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10908 18:05:25.017612 <4>[ 8.905237] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10909 18:05:25.027483 <6>[ 8.913303] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10910 18:05:25.034153 <6>[ 8.921054] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10911 18:05:25.040967 <6>[ 8.927894] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10912 18:05:25.047517 <6>[ 8.928237] remoteproc remoteproc0: scp is available
10913 18:05:25.051151 <6>[ 8.929037] remoteproc remoteproc0: powering up scp
10914 18:05:25.060757 <6>[ 8.929043] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10915 18:05:25.067363 <6>[ 8.929073] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10916 18:05:25.073900 <3>[ 8.932518] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10917 18:05:25.080959 <6>[ 8.938183] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10918 18:05:25.090765 <6>[ 8.941648] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10919 18:05:25.097292 <3>[ 8.946559] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10920 18:05:25.107461 <6>[ 8.951625] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10921 18:05:25.113751 <4>[ 8.953817] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10922 18:05:25.117398 <6>[ 8.954922] mc: Linux media interface: v0.10
10923 18:05:25.127622 <3>[ 8.956791] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10924 18:05:25.135212 <4>[ 8.965658] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10925 18:05:25.141695 <6>[ 8.972024] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10926 18:05:25.148471 <3>[ 8.979564] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10927 18:05:25.158441 <6>[ 8.981496] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10928 18:05:25.164870 <6>[ 8.987029] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10929 18:05:25.172002 <6>[ 8.989288] videodev: Linux video capture interface: v2.00
10930 18:05:25.179273 <3>[ 8.994951] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10931 18:05:25.189484 <4>[ 9.014043] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10932 18:05:25.192489 <4>[ 9.014043] Fallback method does not support PEC.
10933 18:05:25.202841 <3>[ 9.018237] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10934 18:05:25.209472 <3>[ 9.039011] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10935 18:05:25.219420 <3>[ 9.045907] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10936 18:05:25.225831 <3>[ 9.045911] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10937 18:05:25.236442 <3>[ 9.045983] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10938 18:05:25.239973 <6>[ 9.050489] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10939 18:05:25.251412 <6>[ 9.050543] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10940 18:05:25.257940 <6>[ 9.050551] remoteproc remoteproc0: remote processor scp is now up
10941 18:05:25.264487 <6>[ 9.055978] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10942 18:05:25.270948 <3>[ 9.061688] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10943 18:05:25.281506 <6>[ 9.062621] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10944 18:05:25.288511 <6>[ 9.064593] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10945 18:05:25.295340 <6>[ 9.070773] pci_bus 0000:00: root bus resource [bus 00-ff]
10946 18:05:25.305606 <6>[ 9.075189] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10947 18:05:25.311577 <6>[ 9.075522] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10948 18:05:25.322395 <3>[ 9.076505] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10949 18:05:25.329283 <3>[ 9.084061] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10950 18:05:25.335902 <6>[ 9.084586] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10951 18:05:25.346630 <6>[ 9.084589] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10952 18:05:25.353174 <6>[ 9.084624] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10953 18:05:25.363058 <3>[ 9.084897] power_supply sbs-5-000b: driver failed to report `current_avg' property: -6
10954 18:05:25.369644 <6>[ 9.089620] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10955 18:05:25.376999 <3>[ 9.098230] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10956 18:05:25.387284 <6>[ 9.107107] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10957 18:05:25.394012 <3>[ 9.115179] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10958 18:05:25.397331 <6>[ 9.123294] pci 0000:00:00.0: supports D1 D2
10959 18:05:25.404642 <6>[ 9.127479] Bluetooth: Core ver 2.22
10960 18:05:25.407961 <6>[ 9.127537] NET: Registered PF_BLUETOOTH protocol family
10961 18:05:25.414697 <6>[ 9.127539] Bluetooth: HCI device and connection manager initialized
10962 18:05:25.421295 <6>[ 9.127552] Bluetooth: HCI socket layer initialized
10963 18:05:25.424890 <6>[ 9.127556] Bluetooth: L2CAP socket layer initialized
10964 18:05:25.431419 <6>[ 9.127563] Bluetooth: SCO socket layer initialized
10965 18:05:25.438360 <3>[ 9.131267] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10966 18:05:25.444848 <6>[ 9.139346] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10967 18:05:25.455673 <3>[ 9.143913] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10968 18:05:25.462409 <3>[ 9.144679] power_supply sbs-5-000b: driver failed to report `health' property: -6
10969 18:05:25.469046 <3>[ 9.146392] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10970 18:05:25.478946 <3>[ 9.153266] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10971 18:05:25.485748 <3>[ 9.155688] power_supply sbs-5-000b: driver failed to report `status' property: -6
10972 18:05:25.495240 <6>[ 9.155807] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10973 18:05:25.501952 <6>[ 9.155897] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10974 18:05:25.508413 <6>[ 9.155923] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10975 18:05:25.515384 <6>[ 9.155940] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10976 18:05:25.525428 <6>[ 9.155955] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10977 18:05:25.528429 <6>[ 9.156059] pci 0000:01:00.0: supports D1 D2
10978 18:05:25.535306 <6>[ 9.156061] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10979 18:05:25.541817 <3>[ 9.161324] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10980 18:05:25.551467 <3>[ 9.161328] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10981 18:05:25.558286 <3>[ 9.161362] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10982 18:05:25.565034 <6>[ 9.163180] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10983 18:05:25.578302 <6>[ 9.164158] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10984 18:05:25.584901 <6>[ 9.164262] usbcore: registered new interface driver uvcvideo
10985 18:05:25.591497 <6>[ 9.166407] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10986 18:05:25.598229 <6>[ 9.166435] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10987 18:05:25.608254 <6>[ 9.166438] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10988 18:05:25.614494 <6>[ 9.166446] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10989 18:05:25.624798 <6>[ 9.166458] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10990 18:05:25.630961 <6>[ 9.166471] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10991 18:05:25.637923 <6>[ 9.166483] pci 0000:00:00.0: PCI bridge to [bus 01]
10992 18:05:25.644392 <6>[ 9.166489] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10993 18:05:25.650974 <6>[ 9.166610] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10994 18:05:25.657600 <6>[ 9.167058] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10995 18:05:25.664113 <6>[ 9.167325] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10996 18:05:25.671045 <3>[ 9.191343] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10997 18:05:25.677865 <6>[ 9.194406] usbcore: registered new interface driver btusb
10998 18:05:25.684142 <5>[ 9.195292] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10999 18:05:25.697419 <4>[ 9.196058] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
11000 18:05:25.700349 <3>[ 9.196076] Bluetooth: hci0: Failed to load firmware file (-2)
11001 18:05:25.706978 <3>[ 9.196080] Bluetooth: hci0: Failed to set up firmware (-2)
11002 18:05:25.717360 <4>[ 9.196086] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
11003 18:05:25.723872 <5>[ 9.207490] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
11004 18:05:25.730469 <6>[ 9.218311] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
11005 18:05:25.739996 <5>[ 9.225990] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
11006 18:05:25.749889 <3>[ 9.227744] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11007 18:05:25.756841 <3>[ 9.247924] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11008 18:05:25.766762 <4>[ 9.251617] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
11009 18:05:25.773088 <6>[ 9.351457] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
11010 18:05:25.779973 <6>[ 9.358816] cfg80211: failed to load regulatory.db
11011 18:05:25.786455 <6>[ 9.366981] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
11012 18:05:25.793332 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
11013 18:05:25.810086 <6>[ 9.709863] mt7921e 0000:01:00.0: ASIC revision: 79610010
11014 18:05:25.841595 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
11015 18:05:25.860269 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
11016 18:05:25.879879 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11017 18:05:25.911785 <6>[ 9.808190] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
11018 18:05:25.915170 <6>[ 9.808190]
11019 18:05:25.950625 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11020 18:05:25.970397 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
11021 18:05:25.988294 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11022 18:05:26.059394 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11023 18:05:26.081697 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
11024 18:05:26.101471 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
11025 18:05:26.117701 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
11026 18:05:26.136250 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11027 18:05:26.180842 <6>[ 10.077270] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
11028 18:05:26.192378 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
11029 18:05:26.215999 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11030 18:05:26.237642 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11031 18:05:26.259249 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11032 18:05:26.300492 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11033 18:05:26.347155 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11034 18:05:26.366331 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11035 18:05:26.381414 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11036 18:05:26.400796 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11037 18:05:26.444833 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11038 18:05:26.469630 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11039 18:05:26.490656 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11040 18:05:26.531303 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11041 18:05:26.560729
11042 18:05:26.564368 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11043 18:05:26.564441
11044 18:05:26.567472 debian-bookworm-arm64 login: root (automatic login)
11045 18:05:26.567545
11046 18:05:26.581867 Linux debian-bookworm-arm64 6.1.92-cip22 #1 SMP PREEMPT Tue Jun 11 17:44:14 UTC 2024 aarch64
11047 18:05:26.581943
11048 18:05:26.588389 The programs included with the Debian GNU/Linux system are free software;
11049 18:05:26.594633 the exact distribution terms for each program are described in the
11050 18:05:26.598333 individual files in /usr/share/doc/*/copyright.
11051 18:05:26.598408
11052 18:05:26.604997 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11053 18:05:26.607972 permitted by applicable law.
11054 18:05:26.608578 Matched prompt #10: / #
11056 18:05:26.608878 Setting prompt string to ['/ #']
11057 18:05:26.609034 end: 2.2.5.1 login-action (duration 00:00:11) [common]
11059 18:05:26.609329 end: 2.2.5 auto-login-action (duration 00:00:11) [common]
11060 18:05:26.609447 start: 2.2.6 expect-shell-connection (timeout 00:03:03) [common]
11061 18:05:26.609546 Setting prompt string to ['/ #']
11062 18:05:26.609635 Forcing a shell prompt, looking for ['/ #']
11064 18:05:26.659899 / #
11065 18:05:26.660011 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11066 18:05:26.660089 Waiting using forced prompt support (timeout 00:02:30)
11067 18:05:26.665004
11068 18:05:26.665305 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11069 18:05:26.665402 start: 2.2.7 export-device-env (timeout 00:03:03) [common]
11070 18:05:26.665492 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11071 18:05:26.665579 end: 2.2 depthcharge-retry (duration 00:01:57) [common]
11072 18:05:26.665662 end: 2 depthcharge-action (duration 00:01:57) [common]
11073 18:05:26.665750 start: 3 lava-test-retry (timeout 00:07:41) [common]
11074 18:05:26.665836 start: 3.1 lava-test-shell (timeout 00:07:41) [common]
11075 18:05:26.665945 Using namespace: common
11077 18:05:26.766213 / # #
11078 18:05:26.766346 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11079 18:05:26.771882 #
11080 18:05:26.772173 Using /lava-14291408
11082 18:05:26.872463 / # export SHELL=/bin/sh
11083 18:05:26.877786 export SHELL=/bin/sh
11085 18:05:26.978337 / # . /lava-14291408/environment
11086 18:05:26.983679 . /lava-14291408/environment
11088 18:05:27.084162 / # /lava-14291408/bin/lava-test-runner /lava-14291408/0
11089 18:05:27.084352 Test shell timeout: 10s (minimum of the action and connection timeout)
11090 18:05:27.084712 /lava-14291408/bin/lava-test-runner /lava-14291408/0<6>[ 10.958805] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11091 18:05:27.089459
11092 18:05:27.133086 + export TESTRUN_ID=0_v4l2-compliance-uvc
11093 18:05:27.133182 + cd /lava-14291408/0/tests/0_v4l2-compliance-uvc
11094 18:05:27.133250 + cat uuid
11095 18:05:27.133311 + UUID=14291408_1.5.2.3.1
11096 18:05:27.133370 + set +x
11097 18:05:27.133428 <LAVA_SIGNAL_STARTRUN 0_v4l2-compliance-uvc 14291408_1.5.2.3.1>
11098 18:05:27.133483 + /usr/bin/v4l2-parser.sh -d uvcvideo
11099 18:05:27.133719 Received signal: <STARTRUN> 0_v4l2-compliance-uvc 14291408_1.5.2.3.1
11100 18:05:27.133789 Starting test lava.0_v4l2-compliance-uvc (14291408_1.5.2.3.1)
11101 18:05:27.133871 Skipping test definition patterns.
11102 18:05:27.137221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=device-presence RESULT=pass>
11103 18:05:27.137293 device: /dev/video0
11104 18:05:27.137522 Received signal: <TESTCASE> TEST_CASE_ID=device-presence RESULT=pass
11106 18:05:33.563148 v4l2-compliance 1.27.0-1, 64 bits, 64-bit time_t
11107 18:05:33.576015 v4l2-compliance SHA: a18611d8960f 2024-03-08 13:09:54
11108 18:05:33.582372
11109 18:05:33.598864 Compliance test for uvcvideo device /dev/video0:
11110 18:05:33.606202
11111 18:05:33.619191 Driver Info:
11112 18:05:33.629050 Driver name : uvcvideo
11113 18:05:33.646534 Card type : HD User Facing: HD User Facing
11114 18:05:33.657356 Bus info : usb-11200000.usb-1.4.1
11115 18:05:33.665910 Driver version : 6.1.92
11116 18:05:33.677179 Capabilities : 0x84a00001
11117 18:05:33.695356 Metadata Capture
11118 18:05:33.706903 Streaming
11119 18:05:33.717234 Extended Pix Format
11120 18:05:33.727727 Device Capabilities
11121 18:05:33.740278 Device Caps : 0x04200001
11122 18:05:33.753991 Streaming
11123 18:05:33.764185 Extended Pix Format
11124 18:05:33.779320 Media Driver Info:
11125 18:05:33.790402 Driver name : uvcvideo
11126 18:05:33.807408 Model : HD User Facing: HD User Facing
11127 18:05:33.816486 Serial : 200901010001
11128 18:05:33.830394 Bus info : usb-11200000.usb-1.4.1
11129 18:05:33.839564 Media version : 6.1.92
11130 18:05:33.856377 Hardware revision: 0x00009758 (38744)
11131 18:05:33.865404 Driver version : 6.1.92
11132 18:05:33.878736 Interface Info:
11133 18:05:33.893352 <LAVA_SIGNAL_TESTSET START Interface-Info>
11134 18:05:33.893790 ID : 0x03000002
11135 18:05:33.894512 Received signal: <TESTSET> START Interface-Info
11136 18:05:33.894990 Starting test_set Interface-Info
11137 18:05:33.902951 Type : V4L Video
11138 18:05:33.916023 Entity Info:
11139 18:05:33.923369 <LAVA_SIGNAL_TESTSET STOP>
11140 18:05:33.924086 Received signal: <TESTSET> STOP
11141 18:05:33.924683 Closing test_set Interface-Info
11142 18:05:33.933248 <LAVA_SIGNAL_TESTSET START Entity-Info>
11143 18:05:33.934155 Received signal: <TESTSET> START Entity-Info
11144 18:05:33.934675 Starting test_set Entity-Info
11145 18:05:33.936080 ID : 0x00000001 (1)
11146 18:05:33.947820 Name : HD User Facing: HD User Facing
11147 18:05:33.954562 Function : V4L2 I/O
11148 18:05:33.969605 Flags : default
11149 18:05:33.980741 Pad 0x01000007 : 0: Sink
11150 18:05:34.004522 Link 0x02000013: from remote pad 0x100000a of entity 'Realtek Extended Controls Unit' (Video Pixel Formatter): Data, Enabled, Immutable
11151 18:05:34.004972
11152 18:05:34.018063 Required ioctls:
11153 18:05:34.025802 <LAVA_SIGNAL_TESTSET STOP>
11154 18:05:34.026481 Received signal: <TESTSET> STOP
11155 18:05:34.026830 Closing test_set Entity-Info
11156 18:05:34.035099 <LAVA_SIGNAL_TESTSET START Required-ioctls>
11157 18:05:34.035760 Received signal: <TESTSET> START Required-ioctls
11158 18:05:34.036207 Starting test_set Required-ioctls
11159 18:05:34.038420 test MC information (see 'Media Driver Info' above): OK
11160 18:05:34.064688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MC-information-see-Media-Driver-Info-above RESULT=pass>
11161 18:05:34.065455 Received signal: <TESTCASE> TEST_CASE_ID=MC-information-see-Media-Driver-Info-above RESULT=pass
11163 18:05:34.067921 test VIDIOC_QUERYCAP: OK
11164 18:05:34.085210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11165 18:05:34.086183 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11167 18:05:34.088552 test invalid ioctls: OK
11168 18:05:34.110285 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-ioctls RESULT=pass>
11169 18:05:34.110737
11170 18:05:34.111502 Received signal: <TESTCASE> TEST_CASE_ID=invalid-ioctls RESULT=pass
11172 18:05:34.120302 Allow for multiple opens:
11173 18:05:34.127552 <LAVA_SIGNAL_TESTSET STOP>
11174 18:05:34.128255 Received signal: <TESTSET> STOP
11175 18:05:34.128606 Closing test_set Required-ioctls
11176 18:05:34.136700 <LAVA_SIGNAL_TESTSET START Allow-for-multiple-opens>
11177 18:05:34.137275 Received signal: <TESTSET> START Allow-for-multiple-opens
11178 18:05:34.137553 Starting test_set Allow-for-multiple-opens
11179 18:05:34.140185 test second /dev/video0 open: OK
11180 18:05:34.162128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=second-/dev/video0-open RESULT=pass>
11181 18:05:34.162596 Received signal: <TESTCASE> TEST_CASE_ID=second-/dev/video0-open RESULT=pass
11183 18:05:34.165446 test VIDIOC_QUERYCAP: OK
11184 18:05:34.185760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11185 18:05:34.186176 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11187 18:05:34.188948 test VIDIOC_G/S_PRIORITY: OK
11188 18:05:34.212215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass>
11189 18:05:34.212943 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass
11191 18:05:34.215406 test for unlimited opens: OK
11192 18:05:34.242197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=for-unlimited-opens RESULT=pass>
11193 18:05:34.242752
11194 18:05:34.243478 Received signal: <TESTCASE> TEST_CASE_ID=for-unlimited-opens RESULT=pass
11196 18:05:34.256637 Debug ioctls:
11197 18:05:34.263954 <LAVA_SIGNAL_TESTSET STOP>
11198 18:05:34.264886 Received signal: <TESTSET> STOP
11199 18:05:34.265461 Closing test_set Allow-for-multiple-opens
11200 18:05:34.273845 <LAVA_SIGNAL_TESTSET START Debug-ioctls>
11201 18:05:34.274795 Received signal: <TESTSET> START Debug-ioctls
11202 18:05:34.275307 Starting test_set Debug-ioctls
11203 18:05:34.276854 test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
11204 18:05:34.296915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass>
11205 18:05:34.297837 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass
11207 18:05:34.303367 test VIDIOC_LOG_STATUS: OK (Not Supported)
11208 18:05:34.325854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass>
11209 18:05:34.326174
11210 18:05:34.326570 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass
11212 18:05:34.340267 Input ioctls:
11213 18:05:34.347184 <LAVA_SIGNAL_TESTSET STOP>
11214 18:05:34.347694 Received signal: <TESTSET> STOP
11215 18:05:34.347918 Closing test_set Debug-ioctls
11216 18:05:34.356734 <LAVA_SIGNAL_TESTSET START Input-ioctls>
11217 18:05:34.357250 Received signal: <TESTSET> START Input-ioctls
11218 18:05:34.357447 Starting test_set Input-ioctls
11219 18:05:34.359765 test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
11220 18:05:34.385365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass>
11221 18:05:34.385885 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass
11223 18:05:34.388806 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11224 18:05:34.407418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11225 18:05:34.407892 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11227 18:05:34.414220 test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
11228 18:05:34.432663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass>
11229 18:05:34.433103 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass
11231 18:05:34.435875 test VIDIOC_ENUMAUDIO: OK (Not Supported)
11232 18:05:34.458122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass>
11233 18:05:34.458554 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass
11235 18:05:34.461654 test VIDIOC_G/S/ENUMINPUT: OK
11236 18:05:34.486618 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass>
11237 18:05:34.487332 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass
11239 18:05:34.490091 test VIDIOC_G/S_AUDIO: OK (Not Supported)
11240 18:05:34.516574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass>
11241 18:05:34.517307 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass
11243 18:05:34.519319 Inputs: 1 Audio Inputs: 0 Tuners: 0
11244 18:05:34.526744
11245 18:05:34.542695 test VIDIOC_G/S_MODULATOR: OK (Not Supported)
11246 18:05:34.564680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass>
11247 18:05:34.565543 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass
11249 18:05:34.571294 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11250 18:05:34.589828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11251 18:05:34.590641 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11253 18:05:34.596665 test VIDIOC_ENUMAUDOUT: OK (Not Supported)
11254 18:05:34.612343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass>
11255 18:05:34.613204 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass
11257 18:05:34.619078 test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
11258 18:05:34.638092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass>
11259 18:05:34.638905 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass
11261 18:05:34.644663 test VIDIOC_G/S_AUDOUT: OK (Not Supported)
11262 18:05:34.663085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass>
11263 18:05:34.664060 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass
11265 18:05:34.666377
11266 18:05:34.682160 test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
11267 18:05:34.707299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass>
11268 18:05:34.708073 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass
11270 18:05:34.713871 test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
11271 18:05:34.739270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass>
11272 18:05:34.740074 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass
11274 18:05:34.742141 test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
11275 18:05:34.764633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass>
11276 18:05:34.765419 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass
11278 18:05:34.767861 test VIDIOC_G/S_EDID: OK (Not Supported)
11279 18:05:34.789902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass>
11280 18:05:34.790387
11281 18:05:34.790983 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass
11283 18:05:34.800726 Control ioctls (Input 0):
11284 18:05:34.807364 <LAVA_SIGNAL_TESTSET STOP>
11285 18:05:34.808043 Received signal: <TESTSET> STOP
11286 18:05:34.808393 Closing test_set Input-ioctls
11287 18:05:34.817509 <LAVA_SIGNAL_TESTSET START Control-ioctls-Input-0>
11288 18:05:34.818252 Received signal: <TESTSET> START Control-ioctls-Input-0
11289 18:05:34.818609 Starting test_set Control-ioctls-Input-0
11290 18:05:34.821148 test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
11291 18:05:34.849124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass>
11292 18:05:34.849605 test VIDIOC_QUERYCTRL: OK
11293 18:05:34.850233 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass
11295 18:05:34.869499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass>
11296 18:05:34.870203 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass
11298 18:05:34.872901 test VIDIOC_G/S_CTRL: OK
11299 18:05:34.898755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass>
11300 18:05:34.899436 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass
11302 18:05:34.902415 test VIDIOC_G/S/TRY_EXT_CTRLS: OK
11303 18:05:34.923975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass>
11304 18:05:34.924796 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass
11306 18:05:34.930760 test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: OK
11307 18:05:34.952475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=pass>
11308 18:05:34.953524 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=pass
11310 18:05:34.955389 test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
11311 18:05:34.976275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass>
11312 18:05:34.977095 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass
11314 18:05:34.979100 Standard Controls: 16 Private Controls: 0
11315 18:05:34.987148
11316 18:05:34.997716 Format ioctls (Input 0):
11317 18:05:35.004437 <LAVA_SIGNAL_TESTSET STOP>
11318 18:05:35.005222 Received signal: <TESTSET> STOP
11319 18:05:35.005598 Closing test_set Control-ioctls-Input-0
11320 18:05:35.014279 <LAVA_SIGNAL_TESTSET START Format-ioctls-Input-0>
11321 18:05:35.015105 Received signal: <TESTSET> START Format-ioctls-Input-0
11322 18:05:35.015519 Starting test_set Format-ioctls-Input-0
11323 18:05:35.017879 test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
11324 18:05:35.042077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass>
11325 18:05:35.042886 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass
11327 18:05:35.045140 test VIDIOC_G/S_PARM: OK
11328 18:05:35.063147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass>
11329 18:05:35.063897 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass
11331 18:05:35.066865 test VIDIOC_G_FBUF: OK (Not Supported)
11332 18:05:35.090358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass>
11333 18:05:35.091249 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass
11335 18:05:35.093957 test VIDIOC_G_FMT: OK
11336 18:05:35.119964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass>
11337 18:05:35.120784 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass
11339 18:05:35.123035 test VIDIOC_TRY_FMT: OK
11340 18:05:35.144108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass>
11341 18:05:35.144930 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass
11343 18:05:35.150981 warn: v4l2-test-formats.cpp(1046): Could not set fmt2
11344 18:05:35.154917 test VIDIOC_S_FMT: OK
11345 18:05:35.181139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_FMT RESULT=pass>
11346 18:05:35.182289 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_FMT RESULT=pass
11348 18:05:35.183946 test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
11349 18:05:35.218947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass>
11350 18:05:35.219739 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass
11352 18:05:35.221861 test Cropping: OK (Not Supported)
11353 18:05:35.245116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Cropping RESULT=pass>
11354 18:05:35.246032 Received signal: <TESTCASE> TEST_CASE_ID=Cropping RESULT=pass
11356 18:05:35.248053 test Composing: OK (Not Supported)
11357 18:05:35.268779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Composing RESULT=pass>
11358 18:05:35.269731 Received signal: <TESTCASE> TEST_CASE_ID=Composing RESULT=pass
11360 18:05:35.272318 test Scaling: OK (Not Supported)
11361 18:05:35.292890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Scaling RESULT=pass>
11362 18:05:35.293424
11363 18:05:35.294012 Received signal: <TESTCASE> TEST_CASE_ID=Scaling RESULT=pass
11365 18:05:35.304478 Codec ioctls (Input 0):
11366 18:05:35.310462 <LAVA_SIGNAL_TESTSET STOP>
11367 18:05:35.311139 Received signal: <TESTSET> STOP
11368 18:05:35.311492 Closing test_set Format-ioctls-Input-0
11369 18:05:35.320784 <LAVA_SIGNAL_TESTSET START Codec-ioctls-Input-0>
11370 18:05:35.321547 Received signal: <TESTSET> START Codec-ioctls-Input-0
11371 18:05:35.321950 Starting test_set Codec-ioctls-Input-0
11372 18:05:35.323875 test VIDIOC_(TRY_)ENCODER_CMD: OK (Not Supported)
11373 18:05:35.343721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass>
11374 18:05:35.344436 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass
11376 18:05:35.350194 test VIDIOC_G_ENC_INDEX: OK (Not Supported)
11377 18:05:35.369693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass>
11378 18:05:35.370432 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass
11380 18:05:35.376195 test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
11381 18:05:35.396449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass>
11382 18:05:35.396875
11383 18:05:35.397500 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass
11385 18:05:35.408093 Buffer ioctls (Input 0):
11386 18:05:35.415988 <LAVA_SIGNAL_TESTSET STOP>
11387 18:05:35.416795 Received signal: <TESTSET> STOP
11388 18:05:35.417217 Closing test_set Codec-ioctls-Input-0
11389 18:05:35.425457 <LAVA_SIGNAL_TESTSET START Buffer-ioctls-Input-0>
11390 18:05:35.426131 Received signal: <TESTSET> START Buffer-ioctls-Input-0
11391 18:05:35.426484 Starting test_set Buffer-ioctls-Input-0
11392 18:05:35.429046 test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
11393 18:05:35.457946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass>
11394 18:05:35.458655 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass
11396 18:05:35.461141 test CREATE_BUFS maximum buffers: OK
11397 18:05:35.480418 Received signal: <TESTCASE> TEST_CASE_ID=CREATE_BUFS-maximum-buffers RESULT=pass
11399 18:05:35.483097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CREATE_BUFS-maximum-buffers RESULT=pass>
11400 18:05:35.483632 test VIDIOC_EXPBUF: OK
11401 18:05:35.504032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass>
11402 18:05:35.504813 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass
11404 18:05:35.507387 test Requests: OK (Not Supported)
11405 18:05:35.529184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Requests RESULT=pass>
11406 18:05:35.529675
11407 18:05:35.530378 Received signal: <TESTCASE> TEST_CASE_ID=Requests RESULT=pass
11409 18:05:35.543408 Test input 0:
11410 18:05:35.552826
11411 18:05:35.563900 Streaming ioctls:
11412 18:05:35.573270 <LAVA_SIGNAL_TESTSET STOP>
11413 18:05:35.574085 Received signal: <TESTSET> STOP
11414 18:05:35.574610 Closing test_set Buffer-ioctls-Input-0
11415 18:05:35.583936 <LAVA_SIGNAL_TESTSET START Streaming-ioctls_Test-input-0>
11416 18:05:35.584609 Received signal: <TESTSET> START Streaming-ioctls_Test-input-0
11417 18:05:35.584963 Starting test_set Streaming-ioctls_Test-input-0
11418 18:05:35.587610 test read/write: OK (Not Supported)
11419 18:05:35.609595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=read/write RESULT=pass>
11420 18:05:35.610350 Received signal: <TESTCASE> TEST_CASE_ID=read/write RESULT=pass
11422 18:05:35.612513 test blocking wait: OK
11423 18:05:35.638725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blocking-wait RESULT=pass>
11424 18:05:35.639510 Received signal: <TESTCASE> TEST_CASE_ID=blocking-wait RESULT=pass
11426 18:05:35.645572 fail: v4l2-test-buffers.cpp(1377): node->streamon(q.g_type()) != EINVAL
11427 18:05:35.653494 test MMAP (no poll): FAIL
11428 18:05:35.678662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-no-poll RESULT=fail>
11429 18:05:35.679471 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-no-poll RESULT=fail
11431 18:05:35.685273 fail: v4l2-test-buffers.cpp(1377): node->streamon(q.g_type()) != EINVAL
11432 18:05:35.690571 test MMAP (select): FAIL
11433 18:05:35.718334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-select RESULT=fail>
11434 18:05:35.719131 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-select RESULT=fail
11436 18:05:35.725002 fail: v4l2-test-buffers.cpp(1377): node->streamon(q.g_type()) != EINVAL
11437 18:05:35.731007 test MMAP (epoll): FAIL
11438 18:05:35.755708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-epoll RESULT=fail>
11439 18:05:35.756195
11440 18:05:35.756783 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-epoll RESULT=fail
11442 18:05:35.770153
11443 18:05:35.956501
11444 18:05:35.964736 test USERPTR (no poll): OK
11445 18:05:35.994919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-no-poll RESULT=pass>
11446 18:05:35.995491
11447 18:05:35.996135 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-no-poll RESULT=pass
11449 18:05:36.012874
11450 18:05:36.198272
11451 18:05:36.206683 test USERPTR (select): OK
11452 18:05:36.235239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-select RESULT=pass>
11453 18:05:36.236038 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-select RESULT=pass
11455 18:05:36.241345 test DMABUF: Cannot test, specify --expbuf-device
11456 18:05:36.245548
11457 18:05:36.265630 Total for uvcvideo device /dev/video0: 54, Succeeded: 51, Failed: 3, Warnings: 3
11458 18:05:36.270912 <LAVA_TEST_RUNNER EXIT>
11459 18:05:36.271589 ok: lava_test_shell seems to have completed
11460 18:05:36.271977 Marking unfinished test run as failed
11462 18:05:36.276916 CREATE_BUFS-maximum-buffers:
result: pass
set: Buffer-ioctls-Input-0
Composing:
result: pass
set: Format-ioctls-Input-0
Cropping:
result: pass
set: Format-ioctls-Input-0
MC-information-see-Media-Driver-Info-above:
result: pass
set: Required-ioctls
MMAP-epoll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-no-poll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-select:
result: fail
set: Streaming-ioctls_Test-input-0
Requests:
result: pass
set: Buffer-ioctls-Input-0
Scaling:
result: pass
set: Format-ioctls-Input-0
USERPTR-no-poll:
result: pass
set: Streaming-ioctls_Test-input-0
USERPTR-select:
result: pass
set: Streaming-ioctls_Test-input-0
VIDIOC_DBG_G/S_REGISTER:
result: pass
set: Debug-ioctls
VIDIOC_DV_TIMINGS_CAP:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_STD:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDIO:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDOUT:
result: pass
set: Input-ioctls
VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS:
result: pass
set: Format-ioctls-Input-0
VIDIOC_EXPBUF:
result: pass
set: Buffer-ioctls-Input-0
VIDIOC_G/S/ENUMINPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/ENUMOUTPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/TRY_EXT_CTRLS:
result: pass
set: Control-ioctls-Input-0
VIDIOC_G/S_AUDIO:
result: pass
set: Input-ioctls
VIDIOC_G/S_AUDOUT:
result: pass
set: Input-ioctls
VIDIOC_G/S_CTRL:
result: pass
set: Control-ioctls-Input-0
VIDIOC_G/S_EDID:
result: pass
set: Input-ioctls
VIDIOC_G/S_FREQUENCY:
result: pass
set: Input-ioctls
VIDIOC_G/S_JPEGCOMP:
result: pass
set: Control-ioctls-Input-0
VIDIOC_G/S_MODULATOR:
result: pass
set: Input-ioctls
VIDIOC_G/S_PARM:
result: pass
set: Format-ioctls-Input-0
VIDIOC_G/S_PRIORITY:
result: pass
set: Allow-for-multiple-opens
VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS:
result: pass
set: Input-ioctls
VIDIOC_G_ENC_INDEX:
result: pass
set: Codec-ioctls-Input-0
VIDIOC_G_FBUF:
result: pass
set: Format-ioctls-Input-0
VIDIOC_G_FMT:
result: pass
set: Format-ioctls-Input-0
VIDIOC_G_SLICED_VBI_CAP:
result: pass
set: Format-ioctls-Input-0
VIDIOC_LOG_STATUS:
result: pass
set: Debug-ioctls
VIDIOC_QUERYCAP:
result: pass
set: Allow-for-multiple-opens
VIDIOC_QUERYCTRL:
result: pass
set: Control-ioctls-Input-0
VIDIOC_QUERY_EXT_CTRL/QUERYMENU:
result: pass
set: Control-ioctls-Input-0
VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF:
result: pass
set: Buffer-ioctls-Input-0
VIDIOC_S_FMT:
result: pass
set: Format-ioctls-Input-0
VIDIOC_S_HW_FREQ_SEEK:
result: pass
set: Input-ioctls
VIDIOC_TRY_DECODER_CMD:
result: pass
set: Codec-ioctls-Input-0
VIDIOC_TRY_ENCODER_CMD:
result: pass
set: Codec-ioctls-Input-0
VIDIOC_TRY_FMT:
result: pass
set: Format-ioctls-Input-0
VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT:
result: pass
set: Control-ioctls-Input-0
blocking-wait:
result: pass
set: Streaming-ioctls_Test-input-0
device-presence: pass
for-unlimited-opens:
result: pass
set: Allow-for-multiple-opens
invalid-ioctls:
result: pass
set: Required-ioctls
read/write:
result: pass
set: Streaming-ioctls_Test-input-0
second-/dev/video0-open:
result: pass
set: Allow-for-multiple-opens
11463 18:05:36.277577 end: 3.1 lava-test-shell (duration 00:00:10) [common]
11464 18:05:36.278027 end: 3 lava-test-retry (duration 00:00:10) [common]
11465 18:05:36.278468 start: 4 finalize (timeout 00:07:31) [common]
11466 18:05:36.278928 start: 4.1 power-off (timeout 00:00:30) [common]
11467 18:05:36.279670 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-3', '--port=1', '--command=off']
11468 18:05:36.396851 >> Command sent successfully.
11469 18:05:36.400432 Returned 0 in 0 seconds
11470 18:05:36.501323 end: 4.1 power-off (duration 00:00:00) [common]
11472 18:05:36.502751 start: 4.2 read-feedback (timeout 00:07:31) [common]
11473 18:05:36.503996 Listened to connection for namespace 'common' for up to 1s
11474 18:05:37.504790 Finalising connection for namespace 'common'
11475 18:05:37.505550 Disconnecting from shell: Finalise
11476 18:05:37.506203 / #
11477 18:05:37.607444 end: 4.2 read-feedback (duration 00:00:01) [common]
11478 18:05:37.608230 end: 4 finalize (duration 00:00:01) [common]
11479 18:05:37.609144 Cleaning after the job
11480 18:05:37.609837 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14291408/tftp-deploy-n4a6lwod/ramdisk
11481 18:05:37.629329 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14291408/tftp-deploy-n4a6lwod/kernel
11482 18:05:37.658751 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14291408/tftp-deploy-n4a6lwod/dtb
11483 18:05:37.659044 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14291408/tftp-deploy-n4a6lwod/modules
11484 18:05:37.666321 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14291408
11485 18:05:37.729679 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14291408
11486 18:05:37.729859 Job finished correctly