Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 33
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 25
1 18:00:07.104932 lava-dispatcher, installed at version: 2024.03
2 18:00:07.105149 start: 0 validate
3 18:00:07.105282 Start time: 2024-06-11 18:00:07.105275+00:00 (UTC)
4 18:00:07.105403 Using caching service: 'http://localhost/cache/?uri=%s'
5 18:00:07.105539 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 18:00:07.373653 Using caching service: 'http://localhost/cache/?uri=%s'
7 18:00:07.373831 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22-17-g24b63cdc814f%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 18:00:19.641846 Using caching service: 'http://localhost/cache/?uri=%s'
9 18:00:19.642063 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22-17-g24b63cdc814f%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 18:00:19.908958 Using caching service: 'http://localhost/cache/?uri=%s'
11 18:00:19.909678 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 18:00:20.172229 Using caching service: 'http://localhost/cache/?uri=%s'
13 18:00:20.172431 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22-17-g24b63cdc814f%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 18:00:23.676669 validate duration: 16.57
16 18:00:23.677059 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 18:00:23.677207 start: 1.1 download-retry (timeout 00:10:00) [common]
18 18:00:23.677335 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 18:00:23.677464 Not decompressing ramdisk as can be used compressed.
20 18:00:23.677551 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm/20240313.0/arm64/initrd.cpio.gz
21 18:00:23.677619 saving as /var/lib/lava/dispatcher/tmp/14291394/tftp-deploy-qqp_ono5/ramdisk/initrd.cpio.gz
22 18:00:23.677684 total size: 5628182 (5 MB)
23 18:00:23.679044 progress 0 % (0 MB)
24 18:00:23.680740 progress 5 % (0 MB)
25 18:00:23.682431 progress 10 % (0 MB)
26 18:00:23.683894 progress 15 % (0 MB)
27 18:00:23.685712 progress 20 % (1 MB)
28 18:00:23.687214 progress 25 % (1 MB)
29 18:00:23.688830 progress 30 % (1 MB)
30 18:00:23.690512 progress 35 % (1 MB)
31 18:00:23.691952 progress 40 % (2 MB)
32 18:00:23.693593 progress 45 % (2 MB)
33 18:00:23.695011 progress 50 % (2 MB)
34 18:00:23.696748 progress 55 % (2 MB)
35 18:00:23.698413 progress 60 % (3 MB)
36 18:00:23.699865 progress 65 % (3 MB)
37 18:00:23.701508 progress 70 % (3 MB)
38 18:00:23.703071 progress 75 % (4 MB)
39 18:00:23.704688 progress 80 % (4 MB)
40 18:00:23.706146 progress 85 % (4 MB)
41 18:00:23.707777 progress 90 % (4 MB)
42 18:00:23.709405 progress 95 % (5 MB)
43 18:00:23.710896 progress 100 % (5 MB)
44 18:00:23.711140 5 MB downloaded in 0.03 s (160.44 MB/s)
45 18:00:23.711444 end: 1.1.1 http-download (duration 00:00:00) [common]
47 18:00:23.711834 end: 1.1 download-retry (duration 00:00:00) [common]
48 18:00:23.711970 start: 1.2 download-retry (timeout 00:10:00) [common]
49 18:00:23.712098 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 18:00:23.712251 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-17-g24b63cdc814f/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 18:00:23.712328 saving as /var/lib/lava/dispatcher/tmp/14291394/tftp-deploy-qqp_ono5/kernel/Image
52 18:00:23.712427 total size: 54813184 (52 MB)
53 18:00:23.712531 No compression specified
54 18:00:23.714205 progress 0 % (0 MB)
55 18:00:23.728918 progress 5 % (2 MB)
56 18:00:23.744012 progress 10 % (5 MB)
57 18:00:23.758866 progress 15 % (7 MB)
58 18:00:23.773952 progress 20 % (10 MB)
59 18:00:23.788424 progress 25 % (13 MB)
60 18:00:23.802805 progress 30 % (15 MB)
61 18:00:23.817182 progress 35 % (18 MB)
62 18:00:23.831494 progress 40 % (20 MB)
63 18:00:23.845801 progress 45 % (23 MB)
64 18:00:23.860210 progress 50 % (26 MB)
65 18:00:23.874695 progress 55 % (28 MB)
66 18:00:23.888882 progress 60 % (31 MB)
67 18:00:23.903159 progress 65 % (34 MB)
68 18:00:23.917133 progress 70 % (36 MB)
69 18:00:23.931540 progress 75 % (39 MB)
70 18:00:23.945713 progress 80 % (41 MB)
71 18:00:23.960332 progress 85 % (44 MB)
72 18:00:23.975534 progress 90 % (47 MB)
73 18:00:23.990764 progress 95 % (49 MB)
74 18:00:24.005203 progress 100 % (52 MB)
75 18:00:24.005522 52 MB downloaded in 0.29 s (178.35 MB/s)
76 18:00:24.005702 end: 1.2.1 http-download (duration 00:00:00) [common]
78 18:00:24.005970 end: 1.2 download-retry (duration 00:00:00) [common]
79 18:00:24.006075 start: 1.3 download-retry (timeout 00:10:00) [common]
80 18:00:24.006202 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 18:00:24.006381 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-17-g24b63cdc814f/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 18:00:24.006483 saving as /var/lib/lava/dispatcher/tmp/14291394/tftp-deploy-qqp_ono5/dtb/mt8192-asurada-spherion-r0.dtb
83 18:00:24.006581 total size: 47258 (0 MB)
84 18:00:24.006682 No compression specified
85 18:00:24.008492 progress 69 % (0 MB)
86 18:00:24.008795 progress 100 % (0 MB)
87 18:00:24.009026 0 MB downloaded in 0.00 s (18.46 MB/s)
88 18:00:24.009168 end: 1.3.1 http-download (duration 00:00:00) [common]
90 18:00:24.009423 end: 1.3 download-retry (duration 00:00:00) [common]
91 18:00:24.009553 start: 1.4 download-retry (timeout 00:10:00) [common]
92 18:00:24.009677 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 18:00:24.009839 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm/20240313.0/arm64/full.rootfs.tar.xz
94 18:00:24.009937 saving as /var/lib/lava/dispatcher/tmp/14291394/tftp-deploy-qqp_ono5/nfsrootfs/full.rootfs.tar
95 18:00:24.010041 total size: 107552908 (102 MB)
96 18:00:24.010142 Using unxz to decompress xz
97 18:00:24.014372 progress 0 % (0 MB)
98 18:00:24.300280 progress 5 % (5 MB)
99 18:00:24.621479 progress 10 % (10 MB)
100 18:00:24.940253 progress 15 % (15 MB)
101 18:00:25.273496 progress 20 % (20 MB)
102 18:00:25.564333 progress 25 % (25 MB)
103 18:00:25.871173 progress 30 % (30 MB)
104 18:00:26.207380 progress 35 % (35 MB)
105 18:00:26.376851 progress 40 % (41 MB)
106 18:00:26.587185 progress 45 % (46 MB)
107 18:00:26.898815 progress 50 % (51 MB)
108 18:00:27.203037 progress 55 % (56 MB)
109 18:00:27.538099 progress 60 % (61 MB)
110 18:00:27.876709 progress 65 % (66 MB)
111 18:00:28.212055 progress 70 % (71 MB)
112 18:00:28.566766 progress 75 % (76 MB)
113 18:00:28.881878 progress 80 % (82 MB)
114 18:00:29.213623 progress 85 % (87 MB)
115 18:00:29.543287 progress 90 % (92 MB)
116 18:00:29.851551 progress 95 % (97 MB)
117 18:00:30.174100 progress 100 % (102 MB)
118 18:00:30.179420 102 MB downloaded in 6.17 s (16.63 MB/s)
119 18:00:30.179705 end: 1.4.1 http-download (duration 00:00:06) [common]
121 18:00:30.179983 end: 1.4 download-retry (duration 00:00:06) [common]
122 18:00:30.180074 start: 1.5 download-retry (timeout 00:09:53) [common]
123 18:00:30.180164 start: 1.5.1 http-download (timeout 00:09:53) [common]
124 18:00:30.180319 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-17-g24b63cdc814f/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 18:00:30.180392 saving as /var/lib/lava/dispatcher/tmp/14291394/tftp-deploy-qqp_ono5/modules/modules.tar
126 18:00:30.180455 total size: 8618176 (8 MB)
127 18:00:30.180519 Using unxz to decompress xz
128 18:00:30.184465 progress 0 % (0 MB)
129 18:00:30.205040 progress 5 % (0 MB)
130 18:00:30.234231 progress 10 % (0 MB)
131 18:00:30.264891 progress 15 % (1 MB)
132 18:00:30.289602 progress 20 % (1 MB)
133 18:00:30.313719 progress 25 % (2 MB)
134 18:00:30.338282 progress 30 % (2 MB)
135 18:00:30.365716 progress 35 % (2 MB)
136 18:00:30.392649 progress 40 % (3 MB)
137 18:00:30.417052 progress 45 % (3 MB)
138 18:00:30.442737 progress 50 % (4 MB)
139 18:00:30.468835 progress 55 % (4 MB)
140 18:00:30.494026 progress 60 % (4 MB)
141 18:00:30.519533 progress 65 % (5 MB)
142 18:00:30.547440 progress 70 % (5 MB)
143 18:00:30.572182 progress 75 % (6 MB)
144 18:00:30.599029 progress 80 % (6 MB)
145 18:00:30.624366 progress 85 % (7 MB)
146 18:00:30.650626 progress 90 % (7 MB)
147 18:00:30.677185 progress 95 % (7 MB)
148 18:00:30.706502 progress 100 % (8 MB)
149 18:00:30.711286 8 MB downloaded in 0.53 s (15.48 MB/s)
150 18:00:30.711614 end: 1.5.1 http-download (duration 00:00:01) [common]
152 18:00:30.712052 end: 1.5 download-retry (duration 00:00:01) [common]
153 18:00:30.712173 start: 1.6 prepare-tftp-overlay (timeout 00:09:53) [common]
154 18:00:30.712280 start: 1.6.1 extract-nfsrootfs (timeout 00:09:53) [common]
155 18:00:33.126454 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/14291394/extract-nfsrootfs-zajh3fwr
156 18:00:33.126664 end: 1.6.1 extract-nfsrootfs (duration 00:00:02) [common]
157 18:00:33.126766 start: 1.6.2 lava-overlay (timeout 00:09:51) [common]
158 18:00:33.126945 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14291394/lava-overlay-0_74jpds
159 18:00:33.127074 makedir: /var/lib/lava/dispatcher/tmp/14291394/lava-overlay-0_74jpds/lava-14291394/bin
160 18:00:33.127185 makedir: /var/lib/lava/dispatcher/tmp/14291394/lava-overlay-0_74jpds/lava-14291394/tests
161 18:00:33.127282 makedir: /var/lib/lava/dispatcher/tmp/14291394/lava-overlay-0_74jpds/lava-14291394/results
162 18:00:33.127390 Creating /var/lib/lava/dispatcher/tmp/14291394/lava-overlay-0_74jpds/lava-14291394/bin/lava-add-keys
163 18:00:33.127534 Creating /var/lib/lava/dispatcher/tmp/14291394/lava-overlay-0_74jpds/lava-14291394/bin/lava-add-sources
164 18:00:33.127674 Creating /var/lib/lava/dispatcher/tmp/14291394/lava-overlay-0_74jpds/lava-14291394/bin/lava-background-process-start
165 18:00:33.127802 Creating /var/lib/lava/dispatcher/tmp/14291394/lava-overlay-0_74jpds/lava-14291394/bin/lava-background-process-stop
166 18:00:33.127935 Creating /var/lib/lava/dispatcher/tmp/14291394/lava-overlay-0_74jpds/lava-14291394/bin/lava-common-functions
167 18:00:33.128067 Creating /var/lib/lava/dispatcher/tmp/14291394/lava-overlay-0_74jpds/lava-14291394/bin/lava-echo-ipv4
168 18:00:33.128192 Creating /var/lib/lava/dispatcher/tmp/14291394/lava-overlay-0_74jpds/lava-14291394/bin/lava-install-packages
169 18:00:33.128323 Creating /var/lib/lava/dispatcher/tmp/14291394/lava-overlay-0_74jpds/lava-14291394/bin/lava-installed-packages
170 18:00:33.128446 Creating /var/lib/lava/dispatcher/tmp/14291394/lava-overlay-0_74jpds/lava-14291394/bin/lava-os-build
171 18:00:33.128578 Creating /var/lib/lava/dispatcher/tmp/14291394/lava-overlay-0_74jpds/lava-14291394/bin/lava-probe-channel
172 18:00:33.128702 Creating /var/lib/lava/dispatcher/tmp/14291394/lava-overlay-0_74jpds/lava-14291394/bin/lava-probe-ip
173 18:00:33.128833 Creating /var/lib/lava/dispatcher/tmp/14291394/lava-overlay-0_74jpds/lava-14291394/bin/lava-target-ip
174 18:00:33.128957 Creating /var/lib/lava/dispatcher/tmp/14291394/lava-overlay-0_74jpds/lava-14291394/bin/lava-target-mac
175 18:00:33.129098 Creating /var/lib/lava/dispatcher/tmp/14291394/lava-overlay-0_74jpds/lava-14291394/bin/lava-target-storage
176 18:00:33.129225 Creating /var/lib/lava/dispatcher/tmp/14291394/lava-overlay-0_74jpds/lava-14291394/bin/lava-test-case
177 18:00:33.129360 Creating /var/lib/lava/dispatcher/tmp/14291394/lava-overlay-0_74jpds/lava-14291394/bin/lava-test-event
178 18:00:33.129484 Creating /var/lib/lava/dispatcher/tmp/14291394/lava-overlay-0_74jpds/lava-14291394/bin/lava-test-feedback
179 18:00:33.129615 Creating /var/lib/lava/dispatcher/tmp/14291394/lava-overlay-0_74jpds/lava-14291394/bin/lava-test-raise
180 18:00:33.129739 Creating /var/lib/lava/dispatcher/tmp/14291394/lava-overlay-0_74jpds/lava-14291394/bin/lava-test-reference
181 18:00:33.129869 Creating /var/lib/lava/dispatcher/tmp/14291394/lava-overlay-0_74jpds/lava-14291394/bin/lava-test-runner
182 18:00:33.129999 Creating /var/lib/lava/dispatcher/tmp/14291394/lava-overlay-0_74jpds/lava-14291394/bin/lava-test-set
183 18:00:33.130123 Creating /var/lib/lava/dispatcher/tmp/14291394/lava-overlay-0_74jpds/lava-14291394/bin/lava-test-shell
184 18:00:33.130256 Updating /var/lib/lava/dispatcher/tmp/14291394/lava-overlay-0_74jpds/lava-14291394/bin/lava-install-packages (oe)
185 18:00:33.130408 Updating /var/lib/lava/dispatcher/tmp/14291394/lava-overlay-0_74jpds/lava-14291394/bin/lava-installed-packages (oe)
186 18:00:33.130534 Creating /var/lib/lava/dispatcher/tmp/14291394/lava-overlay-0_74jpds/lava-14291394/environment
187 18:00:33.130628 LAVA metadata
188 18:00:33.130694 - LAVA_JOB_ID=14291394
189 18:00:33.130762 - LAVA_DISPATCHER_IP=192.168.201.1
190 18:00:33.130867 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:51) [common]
191 18:00:33.130935 skipped lava-vland-overlay
192 18:00:33.131016 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
193 18:00:33.131096 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:51) [common]
194 18:00:33.131157 skipped lava-multinode-overlay
195 18:00:33.131234 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
196 18:00:33.131312 start: 1.6.2.3 test-definition (timeout 00:09:51) [common]
197 18:00:33.131386 Loading test definitions
198 18:00:33.131478 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:51) [common]
199 18:00:33.131549 Using /lava-14291394 at stage 0
200 18:00:33.131869 uuid=14291394_1.6.2.3.1 testdef=None
201 18:00:33.131965 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
202 18:00:33.132053 start: 1.6.2.3.2 test-overlay (timeout 00:09:51) [common]
203 18:00:33.132580 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
205 18:00:33.132809 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:51) [common]
206 18:00:33.133560 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
208 18:00:33.133802 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:51) [common]
209 18:00:33.134435 runner path: /var/lib/lava/dispatcher/tmp/14291394/lava-overlay-0_74jpds/lava-14291394/0/tests/0_dmesg test_uuid 14291394_1.6.2.3.1
210 18:00:33.134603 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
212 18:00:33.134812 Creating lava-test-runner.conf files
213 18:00:33.134877 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14291394/lava-overlay-0_74jpds/lava-14291394/0 for stage 0
214 18:00:33.134974 - 0_dmesg
215 18:00:33.135074 end: 1.6.2.3 test-definition (duration 00:00:00) [common]
216 18:00:33.135162 start: 1.6.2.4 compress-overlay (timeout 00:09:51) [common]
217 18:00:33.141288 end: 1.6.2.4 compress-overlay (duration 00:00:00) [common]
218 18:00:33.141416 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:51) [common]
219 18:00:33.141507 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
220 18:00:33.141596 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
221 18:00:33.141684 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:51) [common]
222 18:00:33.310579 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
223 18:00:33.310973 start: 1.6.4 extract-modules (timeout 00:09:50) [common]
224 18:00:33.311097 extracting modules file /var/lib/lava/dispatcher/tmp/14291394/tftp-deploy-qqp_ono5/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14291394/extract-nfsrootfs-zajh3fwr
225 18:00:33.537746 extracting modules file /var/lib/lava/dispatcher/tmp/14291394/tftp-deploy-qqp_ono5/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14291394/extract-overlay-ramdisk-c9q_94vc/ramdisk
226 18:00:33.763389 end: 1.6.4 extract-modules (duration 00:00:00) [common]
227 18:00:33.763568 start: 1.6.5 apply-overlay-tftp (timeout 00:09:50) [common]
228 18:00:33.763675 [common] Applying overlay to NFS
229 18:00:33.763749 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14291394/compress-overlay-dboayyae/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14291394/extract-nfsrootfs-zajh3fwr
230 18:00:33.770415 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
231 18:00:33.770554 start: 1.6.6 configure-preseed-file (timeout 00:09:50) [common]
232 18:00:33.770655 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
233 18:00:33.770748 start: 1.6.7 compress-ramdisk (timeout 00:09:50) [common]
234 18:00:33.770836 Building ramdisk /var/lib/lava/dispatcher/tmp/14291394/extract-overlay-ramdisk-c9q_94vc/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14291394/extract-overlay-ramdisk-c9q_94vc/ramdisk
235 18:00:34.097682 >> 130400 blocks
236 18:00:36.280342 rename /var/lib/lava/dispatcher/tmp/14291394/extract-overlay-ramdisk-c9q_94vc/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14291394/tftp-deploy-qqp_ono5/ramdisk/ramdisk.cpio.gz
237 18:00:36.280847 end: 1.6.7 compress-ramdisk (duration 00:00:03) [common]
238 18:00:36.281030 start: 1.6.8 prepare-kernel (timeout 00:09:47) [common]
239 18:00:36.281169 start: 1.6.8.1 prepare-fit (timeout 00:09:47) [common]
240 18:00:36.281321 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14291394/tftp-deploy-qqp_ono5/kernel/Image']
241 18:00:50.871685 Returned 0 in 14 seconds
242 18:00:50.972299 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14291394/tftp-deploy-qqp_ono5/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14291394/tftp-deploy-qqp_ono5/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14291394/tftp-deploy-qqp_ono5/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14291394/tftp-deploy-qqp_ono5/kernel/image.itb
243 18:00:51.333705 output: FIT description: Kernel Image image with one or more FDT blobs
244 18:00:51.334066 output: Created: Tue Jun 11 19:00:51 2024
245 18:00:51.334141 output: Image 0 (kernel-1)
246 18:00:51.334209 output: Description:
247 18:00:51.334294 output: Created: Tue Jun 11 19:00:51 2024
248 18:00:51.334368 output: Type: Kernel Image
249 18:00:51.334448 output: Compression: lzma compressed
250 18:00:51.334511 output: Data Size: 13125101 Bytes = 12817.48 KiB = 12.52 MiB
251 18:00:51.334574 output: Architecture: AArch64
252 18:00:51.334658 output: OS: Linux
253 18:00:51.334738 output: Load Address: 0x00000000
254 18:00:51.334816 output: Entry Point: 0x00000000
255 18:00:51.334889 output: Hash algo: crc32
256 18:00:51.334945 output: Hash value: 7a9e9d3e
257 18:00:51.334999 output: Image 1 (fdt-1)
258 18:00:51.335059 output: Description: mt8192-asurada-spherion-r0
259 18:00:51.335122 output: Created: Tue Jun 11 19:00:51 2024
260 18:00:51.335185 output: Type: Flat Device Tree
261 18:00:51.335241 output: Compression: uncompressed
262 18:00:51.335295 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
263 18:00:51.335349 output: Architecture: AArch64
264 18:00:51.335403 output: Hash algo: crc32
265 18:00:51.335460 output: Hash value: 0f8e4d2e
266 18:00:51.335521 output: Image 2 (ramdisk-1)
267 18:00:51.335581 output: Description: unavailable
268 18:00:51.335642 output: Created: Tue Jun 11 19:00:51 2024
269 18:00:51.335702 output: Type: RAMDisk Image
270 18:00:51.335762 output: Compression: Unknown Compression
271 18:00:51.335844 output: Data Size: 18731806 Bytes = 18292.78 KiB = 17.86 MiB
272 18:00:51.335935 output: Architecture: AArch64
273 18:00:51.336006 output: OS: Linux
274 18:00:51.336061 output: Load Address: unavailable
275 18:00:51.336114 output: Entry Point: unavailable
276 18:00:51.336168 output: Hash algo: crc32
277 18:00:51.336221 output: Hash value: 3ace10c9
278 18:00:51.336274 output: Default Configuration: 'conf-1'
279 18:00:51.336326 output: Configuration 0 (conf-1)
280 18:00:51.336379 output: Description: mt8192-asurada-spherion-r0
281 18:00:51.336431 output: Kernel: kernel-1
282 18:00:51.336517 output: Init Ramdisk: ramdisk-1
283 18:00:51.336570 output: FDT: fdt-1
284 18:00:51.336622 output: Loadables: kernel-1
285 18:00:51.336675 output:
286 18:00:51.336874 end: 1.6.8.1 prepare-fit (duration 00:00:15) [common]
287 18:00:51.336968 end: 1.6.8 prepare-kernel (duration 00:00:15) [common]
288 18:00:51.337117 end: 1.6 prepare-tftp-overlay (duration 00:00:21) [common]
289 18:00:51.337203 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:32) [common]
290 18:00:51.337280 No LXC device requested
291 18:00:51.337358 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
292 18:00:51.337440 start: 1.8 deploy-device-env (timeout 00:09:32) [common]
293 18:00:51.337516 end: 1.8 deploy-device-env (duration 00:00:00) [common]
294 18:00:51.337581 Checking files for TFTP limit of 4294967296 bytes.
295 18:00:51.338080 end: 1 tftp-deploy (duration 00:00:28) [common]
296 18:00:51.338237 start: 2 depthcharge-action (timeout 00:05:00) [common]
297 18:00:51.338338 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
298 18:00:51.338462 substitutions:
299 18:00:51.338529 - {DTB}: 14291394/tftp-deploy-qqp_ono5/dtb/mt8192-asurada-spherion-r0.dtb
300 18:00:51.338593 - {INITRD}: 14291394/tftp-deploy-qqp_ono5/ramdisk/ramdisk.cpio.gz
301 18:00:51.338651 - {KERNEL}: 14291394/tftp-deploy-qqp_ono5/kernel/Image
302 18:00:51.338709 - {LAVA_MAC}: None
303 18:00:51.338764 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/14291394/extract-nfsrootfs-zajh3fwr
304 18:00:51.338819 - {NFS_SERVER_IP}: 192.168.201.1
305 18:00:51.338874 - {PRESEED_CONFIG}: None
306 18:00:51.338928 - {PRESEED_LOCAL}: None
307 18:00:51.338981 - {RAMDISK}: 14291394/tftp-deploy-qqp_ono5/ramdisk/ramdisk.cpio.gz
308 18:00:51.339035 - {ROOT_PART}: None
309 18:00:51.339088 - {ROOT}: None
310 18:00:51.339141 - {SERVER_IP}: 192.168.201.1
311 18:00:51.339194 - {TEE}: None
312 18:00:51.339246 Parsed boot commands:
313 18:00:51.339299 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
314 18:00:51.339480 Parsed boot commands: tftpboot 192.168.201.1 14291394/tftp-deploy-qqp_ono5/kernel/image.itb 14291394/tftp-deploy-qqp_ono5/kernel/cmdline
315 18:00:51.339569 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
316 18:00:51.339655 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
317 18:00:51.339746 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
318 18:00:51.339832 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
319 18:00:51.339905 Not connected, no need to disconnect.
320 18:00:51.339979 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
321 18:00:51.340060 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
322 18:00:51.340129 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-3'
323 18:00:51.343682 Setting prompt string to ['lava-test: # ']
324 18:00:51.344045 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
325 18:00:51.344168 end: 2.2.1 reset-connection (duration 00:00:00) [common]
326 18:00:51.344281 start: 2.2.2 reset-device (timeout 00:05:00) [common]
327 18:00:51.344373 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
328 18:00:51.344633 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-3', '--port=1', '--command=reboot']
329 18:00:56.476154 >> Command sent successfully.
330 18:00:56.478517 Returned 0 in 5 seconds
331 18:00:56.579059 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
333 18:00:56.579381 end: 2.2.2 reset-device (duration 00:00:05) [common]
334 18:00:56.579476 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
335 18:00:56.579563 Setting prompt string to 'Starting depthcharge on Spherion...'
336 18:00:56.579631 Changing prompt to 'Starting depthcharge on Spherion...'
337 18:00:56.579702 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
338 18:00:56.580091 [Enter `^Ec?' for help]
339 18:00:56.978769
340 18:00:56.978913
341 18:00:56.978987 F0: 102B 0000
342 18:00:56.979052
343 18:00:56.979114 F3: 1001 0000 [0200]
344 18:00:56.981777
345 18:00:56.981865 F3: 1001 0000
346 18:00:56.981933
347 18:00:56.981994 F7: 102D 0000
348 18:00:56.982053
349 18:00:56.984816 F1: 0000 0000
350 18:00:56.984925
351 18:00:56.985020 V0: 0000 0000 [0001]
352 18:00:56.985083
353 18:00:56.988484 00: 0007 8000
354 18:00:56.988590
355 18:00:56.988681 01: 0000 0000
356 18:00:56.988775
357 18:00:56.991864 BP: 0C00 0209 [0000]
358 18:00:56.991947
359 18:00:56.992013 G0: 1182 0000
360 18:00:56.992074
361 18:00:56.995018 EC: 0000 0021 [4000]
362 18:00:56.995100
363 18:00:56.995165 S7: 0000 0000 [0000]
364 18:00:56.995226
365 18:00:56.998553 CC: 0000 0000 [0001]
366 18:00:56.998638
367 18:00:56.998703 T0: 0000 0040 [010F]
368 18:00:56.998771
369 18:00:57.001422 Jump to BL
370 18:00:57.001504
371 18:00:57.025377
372 18:00:57.025464
373 18:00:57.035265 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
374 18:00:57.039099 ARM64: Exception handlers installed.
375 18:00:57.039183 ARM64: Testing exception
376 18:00:57.042272 ARM64: Done test exception
377 18:00:57.048721 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
378 18:00:57.058889 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
379 18:00:57.065719 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
380 18:00:57.076016 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
381 18:00:57.082779 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
382 18:00:57.093498 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
383 18:00:57.103309 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
384 18:00:57.109750 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
385 18:00:57.128225 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
386 18:00:57.131980 WDT: Last reset was cold boot
387 18:00:57.135108 SPI1(PAD0) initialized at 2873684 Hz
388 18:00:57.138198 SPI5(PAD0) initialized at 992727 Hz
389 18:00:57.141966 VBOOT: Loading verstage.
390 18:00:57.148096 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
391 18:00:57.151731 FMAP: Found "FLASH" version 1.1 at 0x20000.
392 18:00:57.155425 FMAP: base = 0x0 size = 0x800000 #areas = 25
393 18:00:57.158488 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
394 18:00:57.166099 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
395 18:00:57.172281 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
396 18:00:57.183051 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
397 18:00:57.183136
398 18:00:57.183202
399 18:00:57.193444 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
400 18:00:57.196400 ARM64: Exception handlers installed.
401 18:00:57.199843 ARM64: Testing exception
402 18:00:57.199917 ARM64: Done test exception
403 18:00:57.206734 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
404 18:00:57.210184 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
405 18:00:57.224592 Probing TPM: . done!
406 18:00:57.224724 TPM ready after 0 ms
407 18:00:57.230734 Connected to device vid:did:rid of 1ae0:0028:00
408 18:00:57.237675 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
409 18:00:57.299990 Initialized TPM device CR50 revision 0
410 18:00:57.324701 tlcl_send_startup: Startup return code is 0
411 18:00:57.324832 TPM: setup succeeded
412 18:00:57.339234 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
413 18:00:57.348568 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
414 18:00:57.360851 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
415 18:00:57.371635 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
416 18:00:57.374738 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
417 18:00:57.378493 in-header: 03 07 00 00 08 00 00 00
418 18:00:57.382397 in-data: aa e4 47 04 13 02 00 00
419 18:00:57.382482 Chrome EC: UHEPI supported
420 18:00:57.389142 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
421 18:00:57.399547 in-header: 03 ad 00 00 08 00 00 00
422 18:00:57.403431 in-data: 00 20 20 08 00 00 00 00
423 18:00:57.403534 Phase 1
424 18:00:57.409908 FMAP: area GBB found @ 3f5000 (12032 bytes)
425 18:00:57.414188 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
426 18:00:57.421761 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
427 18:00:57.425524 Recovery requested (1009000e)
428 18:00:57.432262 TPM: Extending digest for VBOOT: boot mode into PCR 0
429 18:00:57.438038 tlcl_extend: response is 0
430 18:00:57.449410 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
431 18:00:57.453134 tlcl_extend: response is 0
432 18:00:57.459608 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
433 18:00:57.480336 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
434 18:00:57.487423 BS: bootblock times (exec / console): total (unknown) / 148 ms
435 18:00:57.487525
436 18:00:57.487595
437 18:00:57.497956 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
438 18:00:57.500777 ARM64: Exception handlers installed.
439 18:00:57.500882 ARM64: Testing exception
440 18:00:57.504408 ARM64: Done test exception
441 18:00:57.524644 pmic_efuse_setting: Set efuses in 11 msecs
442 18:00:57.528504 pmwrap_interface_init: Select PMIF_VLD_RDY
443 18:00:57.535319 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
444 18:00:57.537878 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
445 18:00:57.544654 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
446 18:00:57.548279 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
447 18:00:57.554790 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
448 18:00:57.558351 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
449 18:00:57.561483 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
450 18:00:57.568589 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
451 18:00:57.571934 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
452 18:00:57.578427 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
453 18:00:57.581573 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
454 18:00:57.585324 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
455 18:00:57.591493 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
456 18:00:57.598324 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
457 18:00:57.602026 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
458 18:00:57.609066 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
459 18:00:57.615144 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
460 18:00:57.618982 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
461 18:00:57.625417 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
462 18:00:57.632549 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
463 18:00:57.635688 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
464 18:00:57.642623 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
465 18:00:57.648898 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
466 18:00:57.652057 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
467 18:00:57.659239 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
468 18:00:57.665526 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
469 18:00:57.668966 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
470 18:00:57.672324 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
471 18:00:57.679266 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
472 18:00:57.682477 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
473 18:00:57.688927 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
474 18:00:57.692537 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
475 18:00:57.699478 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
476 18:00:57.702690 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
477 18:00:57.709596 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
478 18:00:57.712536 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
479 18:00:57.719153 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
480 18:00:57.722920 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
481 18:00:57.729522 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
482 18:00:57.733191 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
483 18:00:57.736045 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
484 18:00:57.742962 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
485 18:00:57.746060 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
486 18:00:57.749797 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
487 18:00:57.752885 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
488 18:00:57.759662 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
489 18:00:57.763418 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
490 18:00:57.766440 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
491 18:00:57.773065 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
492 18:00:57.776591 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
493 18:00:57.780156 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
494 18:00:57.786312 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
495 18:00:57.796712 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
496 18:00:57.799845 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
497 18:00:57.809666 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
498 18:00:57.816351 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
499 18:00:57.822908 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
500 18:00:57.826611 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
501 18:00:57.829834 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
502 18:00:57.837533 [RTC]rtc_enable_dcxo,68: con=0x406, osc32con=0xde6f, sec=0x34
503 18:00:57.844328 [RTC]rtc_check_state,173: con=406, pwrkey1=a357, pwrkey2=67d2
504 18:00:57.847448 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
505 18:00:57.851124 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
506 18:00:57.862286 [RTC]rtc_get_frequency_meter,154: input=15, output=789
507 18:00:57.871706 [RTC]rtc_get_frequency_meter,154: input=23, output=978
508 18:00:57.881374 [RTC]rtc_get_frequency_meter,154: input=19, output=884
509 18:00:57.890950 [RTC]rtc_get_frequency_meter,154: input=17, output=837
510 18:00:57.899931 [RTC]rtc_get_frequency_meter,154: input=16, output=814
511 18:00:57.909460 [RTC]rtc_get_frequency_meter,154: input=15, output=790
512 18:00:57.919329 [RTC]rtc_get_frequency_meter,154: input=16, output=814
513 18:00:57.922599 [RTC]rtc_eosc_cali,47: left: 15, middle: 15, right: 16
514 18:00:57.929643 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
515 18:00:57.933179 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
516 18:00:57.936313 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
517 18:00:57.943518 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
518 18:00:57.946560 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
519 18:00:57.950159 ADC[4]: Raw value=901697 ID=7
520 18:00:57.950243 ADC[3]: Raw value=213336 ID=1
521 18:00:57.953218 RAM Code: 0x71
522 18:00:57.956332 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
523 18:00:57.963185 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
524 18:00:57.970111 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
525 18:00:57.976383 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
526 18:00:57.980158 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
527 18:00:57.983284 in-header: 03 07 00 00 08 00 00 00
528 18:00:57.986263 in-data: aa e4 47 04 13 02 00 00
529 18:00:57.989708 Chrome EC: UHEPI supported
530 18:00:57.996375 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
531 18:00:58.000074 in-header: 03 ed 00 00 08 00 00 00
532 18:00:58.003172 in-data: 80 20 60 08 00 00 00 00
533 18:00:58.006946 MRC: failed to locate region type 0.
534 18:00:58.013366 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
535 18:00:58.016515 DRAM-K: Running full calibration
536 18:00:58.023330 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
537 18:00:58.023419 header.status = 0x0
538 18:00:58.026903 header.version = 0x6 (expected: 0x6)
539 18:00:58.030414 header.size = 0xd00 (expected: 0xd00)
540 18:00:58.030552 header.flags = 0x0
541 18:00:58.037706 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
542 18:00:58.056153 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
543 18:00:58.063469 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
544 18:00:58.066634 dram_init: ddr_geometry: 2
545 18:00:58.066714 [EMI] MDL number = 2
546 18:00:58.070289 [EMI] Get MDL freq = 0
547 18:00:58.070361 dram_init: ddr_type: 0
548 18:00:58.073561 is_discrete_lpddr4: 1
549 18:00:58.076658 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
550 18:00:58.076731
551 18:00:58.076801
552 18:00:58.080457 [Bian_co] ETT version 0.0.0.1
553 18:00:58.083579 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
554 18:00:58.083653
555 18:00:58.087302 dramc_set_vcore_voltage set vcore to 650000
556 18:00:58.090372 Read voltage for 800, 4
557 18:00:58.090460 Vio18 = 0
558 18:00:58.093757 Vcore = 650000
559 18:00:58.093857 Vdram = 0
560 18:00:58.093957 Vddq = 0
561 18:00:58.097350 Vmddr = 0
562 18:00:58.097424 dram_init: config_dvfs: 1
563 18:00:58.103564 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
564 18:00:58.107382 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
565 18:00:58.113665 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=10
566 18:00:58.116898 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=10
567 18:00:58.120662 [SwImpedanceCal] DRVP=12, DRVN=25, ODTN=9
568 18:00:58.123946 freq_region=1, Reg: DRVP=12, DRVN=25, ODTN=9
569 18:00:58.127633 MEM_TYPE=3, freq_sel=18
570 18:00:58.130579 sv_algorithm_assistance_LP4_1600
571 18:00:58.136181 ============ PULL DRAM RESETB DOWN ============
572 18:00:58.137353 ========== PULL DRAM RESETB DOWN end =========
573 18:00:58.141159 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
574 18:00:58.144397 ===================================
575 18:00:58.147337 LPDDR4 DRAM CONFIGURATION
576 18:00:58.151001 ===================================
577 18:00:58.154442 EX_ROW_EN[0] = 0x0
578 18:00:58.154528 EX_ROW_EN[1] = 0x0
579 18:00:58.157860 LP4Y_EN = 0x0
580 18:00:58.157945 WORK_FSP = 0x0
581 18:00:58.160596 WL = 0x2
582 18:00:58.160712 RL = 0x2
583 18:00:58.164383 BL = 0x2
584 18:00:58.164485 RPST = 0x0
585 18:00:58.167427 RD_PRE = 0x0
586 18:00:58.167527 WR_PRE = 0x1
587 18:00:58.170930 WR_PST = 0x0
588 18:00:58.171033 DBI_WR = 0x0
589 18:00:58.174403 DBI_RD = 0x0
590 18:00:58.174509 OTF = 0x1
591 18:00:58.177443 ===================================
592 18:00:58.181149 ===================================
593 18:00:58.184330 ANA top config
594 18:00:58.187543 ===================================
595 18:00:58.187629 DLL_ASYNC_EN = 0
596 18:00:58.191318 ALL_SLAVE_EN = 1
597 18:00:58.194354 NEW_RANK_MODE = 1
598 18:00:58.197963 DLL_IDLE_MODE = 1
599 18:00:58.201090 LP45_APHY_COMB_EN = 1
600 18:00:58.201202 TX_ODT_DIS = 1
601 18:00:58.204625 NEW_8X_MODE = 1
602 18:00:58.207812 ===================================
603 18:00:58.211661 ===================================
604 18:00:58.214725 data_rate = 1600
605 18:00:58.217866 CKR = 1
606 18:00:58.221551 DQ_P2S_RATIO = 8
607 18:00:58.225321 ===================================
608 18:00:58.225412 CA_P2S_RATIO = 8
609 18:00:58.228556 DQ_CA_OPEN = 0
610 18:00:58.232241 DQ_SEMI_OPEN = 0
611 18:00:58.235270 CA_SEMI_OPEN = 0
612 18:00:58.235355 CA_FULL_RATE = 0
613 18:00:58.238828 DQ_CKDIV4_EN = 1
614 18:00:58.242229 CA_CKDIV4_EN = 1
615 18:00:58.245639 CA_PREDIV_EN = 0
616 18:00:58.248765 PH8_DLY = 0
617 18:00:58.252468 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
618 18:00:58.252554 DQ_AAMCK_DIV = 4
619 18:00:58.255601 CA_AAMCK_DIV = 4
620 18:00:58.258654 CA_ADMCK_DIV = 4
621 18:00:58.262361 DQ_TRACK_CA_EN = 0
622 18:00:58.265625 CA_PICK = 800
623 18:00:58.268722 CA_MCKIO = 800
624 18:00:58.268807 MCKIO_SEMI = 0
625 18:00:58.272206 PLL_FREQ = 3068
626 18:00:58.275881 DQ_UI_PI_RATIO = 32
627 18:00:58.279316 CA_UI_PI_RATIO = 0
628 18:00:58.282657 ===================================
629 18:00:58.285924 ===================================
630 18:00:58.289296 memory_type:LPDDR4
631 18:00:58.289382 GP_NUM : 10
632 18:00:58.292391 SRAM_EN : 1
633 18:00:58.295603 MD32_EN : 0
634 18:00:58.295688 ===================================
635 18:00:58.299307 [ANA_INIT] >>>>>>>>>>>>>>
636 18:00:58.302238 <<<<<< [CONFIGURE PHASE]: ANA_TX
637 18:00:58.305984 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
638 18:00:58.308896 ===================================
639 18:00:58.312681 data_rate = 1600,PCW = 0X7600
640 18:00:58.315810 ===================================
641 18:00:58.318920 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
642 18:00:58.325859 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
643 18:00:58.329098 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
644 18:00:58.335929 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
645 18:00:58.339040 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
646 18:00:58.342724 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
647 18:00:58.342810 [ANA_INIT] flow start
648 18:00:58.345875 [ANA_INIT] PLL >>>>>>>>
649 18:00:58.349435 [ANA_INIT] PLL <<<<<<<<
650 18:00:58.349520 [ANA_INIT] MIDPI >>>>>>>>
651 18:00:58.353032 [ANA_INIT] MIDPI <<<<<<<<
652 18:00:58.356288 [ANA_INIT] DLL >>>>>>>>
653 18:00:58.356390 [ANA_INIT] flow end
654 18:00:58.359755 ============ LP4 DIFF to SE enter ============
655 18:00:58.366481 ============ LP4 DIFF to SE exit ============
656 18:00:58.366570 [ANA_INIT] <<<<<<<<<<<<<
657 18:00:58.370222 [Flow] Enable top DCM control >>>>>
658 18:00:58.373227 [Flow] Enable top DCM control <<<<<
659 18:00:58.376810 Enable DLL master slave shuffle
660 18:00:58.383135 ==============================================================
661 18:00:58.383264 Gating Mode config
662 18:00:58.389842 ==============================================================
663 18:00:58.393290 Config description:
664 18:00:58.400280 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
665 18:00:58.406983 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
666 18:00:58.413380 SELPH_MODE 0: By rank 1: By Phase
667 18:00:58.416421 ==============================================================
668 18:00:58.420162 GAT_TRACK_EN = 1
669 18:00:58.423232 RX_GATING_MODE = 2
670 18:00:58.426960 RX_GATING_TRACK_MODE = 2
671 18:00:58.429994 SELPH_MODE = 1
672 18:00:58.433638 PICG_EARLY_EN = 1
673 18:00:58.436809 VALID_LAT_VALUE = 1
674 18:00:58.443549 ==============================================================
675 18:00:58.446658 Enter into Gating configuration >>>>
676 18:00:58.449909 Exit from Gating configuration <<<<
677 18:00:58.449994 Enter into DVFS_PRE_config >>>>>
678 18:00:58.463585 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
679 18:00:58.466900 Exit from DVFS_PRE_config <<<<<
680 18:00:58.470778 Enter into PICG configuration >>>>
681 18:00:58.470930 Exit from PICG configuration <<<<
682 18:00:58.473984 [RX_INPUT] configuration >>>>>
683 18:00:58.477546 [RX_INPUT] configuration <<<<<
684 18:00:58.484276 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
685 18:00:58.488072 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
686 18:00:58.495487 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
687 18:00:58.499226 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
688 18:00:58.506103 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
689 18:00:58.513401 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
690 18:00:58.516887 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
691 18:00:58.520526 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
692 18:00:58.524299 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
693 18:00:58.531106 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
694 18:00:58.534885 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
695 18:00:58.538643 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
696 18:00:58.541776 ===================================
697 18:00:58.541931 LPDDR4 DRAM CONFIGURATION
698 18:00:58.545593 ===================================
699 18:00:58.548924 EX_ROW_EN[0] = 0x0
700 18:00:58.551847 EX_ROW_EN[1] = 0x0
701 18:00:58.551925 LP4Y_EN = 0x0
702 18:00:58.555571 WORK_FSP = 0x0
703 18:00:58.555656 WL = 0x2
704 18:00:58.558623 RL = 0x2
705 18:00:58.558727 BL = 0x2
706 18:00:58.561937 RPST = 0x0
707 18:00:58.562032 RD_PRE = 0x0
708 18:00:58.565688 WR_PRE = 0x1
709 18:00:58.565765 WR_PST = 0x0
710 18:00:58.568787 DBI_WR = 0x0
711 18:00:58.568870 DBI_RD = 0x0
712 18:00:58.572356 OTF = 0x1
713 18:00:58.575410 ===================================
714 18:00:58.578898 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
715 18:00:58.582337 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
716 18:00:58.589698 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
717 18:00:58.589783 ===================================
718 18:00:58.592805 LPDDR4 DRAM CONFIGURATION
719 18:00:58.596540 ===================================
720 18:00:58.600320 EX_ROW_EN[0] = 0x10
721 18:00:58.600404 EX_ROW_EN[1] = 0x0
722 18:00:58.604045 LP4Y_EN = 0x0
723 18:00:58.604129 WORK_FSP = 0x0
724 18:00:58.607603 WL = 0x2
725 18:00:58.607688 RL = 0x2
726 18:00:58.607754 BL = 0x2
727 18:00:58.610939 RPST = 0x0
728 18:00:58.611025 RD_PRE = 0x0
729 18:00:58.614485 WR_PRE = 0x1
730 18:00:58.614568 WR_PST = 0x0
731 18:00:58.618669 DBI_WR = 0x0
732 18:00:58.618756 DBI_RD = 0x0
733 18:00:58.621772 OTF = 0x1
734 18:00:58.625873 ===================================
735 18:00:58.629006 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
736 18:00:58.634616 nWR fixed to 40
737 18:00:58.638553 [ModeRegInit_LP4] CH0 RK0
738 18:00:58.638637 [ModeRegInit_LP4] CH0 RK1
739 18:00:58.642072 [ModeRegInit_LP4] CH1 RK0
740 18:00:58.642159 [ModeRegInit_LP4] CH1 RK1
741 18:00:58.645777 match AC timing 13
742 18:00:58.649430 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
743 18:00:58.653174 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
744 18:00:58.660510 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
745 18:00:58.663676 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
746 18:00:58.667460 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
747 18:00:58.667547 [EMI DOE] emi_dcm 0
748 18:00:58.674855 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
749 18:00:58.674942 ==
750 18:00:58.678735 Dram Type= 6, Freq= 0, CH_0, rank 0
751 18:00:58.681986 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
752 18:00:58.682072 ==
753 18:00:58.686362 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
754 18:00:58.693320 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
755 18:00:58.702081 [CA 0] Center 37 (7~68) winsize 62
756 18:00:58.705563 [CA 1] Center 37 (6~68) winsize 63
757 18:00:58.709918 [CA 2] Center 35 (4~66) winsize 63
758 18:00:58.713625 [CA 3] Center 34 (4~65) winsize 62
759 18:00:58.717341 [CA 4] Center 34 (3~65) winsize 63
760 18:00:58.717427 [CA 5] Center 33 (3~64) winsize 62
761 18:00:58.720369
762 18:00:58.723959 [CmdBusTrainingLP45] Vref(ca) range 1: 34
763 18:00:58.724077
764 18:00:58.727319 [CATrainingPosCal] consider 1 rank data
765 18:00:58.730898 u2DelayCellTimex100 = 270/100 ps
766 18:00:58.733895 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
767 18:00:58.737646 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
768 18:00:58.740745 CA2 delay=35 (4~66),Diff = 2 PI (14 cell)
769 18:00:58.744468 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
770 18:00:58.747590 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
771 18:00:58.750662 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
772 18:00:58.750759
773 18:00:58.754400 CA PerBit enable=1, Macro0, CA PI delay=33
774 18:00:58.754498
775 18:00:58.757534 [CBTSetCACLKResult] CA Dly = 33
776 18:00:58.760964 CS Dly: 5 (0~36)
777 18:00:58.761106 ==
778 18:00:58.763998 Dram Type= 6, Freq= 0, CH_0, rank 1
779 18:00:58.767668 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
780 18:00:58.767773 ==
781 18:00:58.773958 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
782 18:00:58.777673 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
783 18:00:58.788721 [CA 0] Center 37 (6~68) winsize 63
784 18:00:58.791925 [CA 1] Center 37 (7~68) winsize 62
785 18:00:58.795509 [CA 2] Center 35 (5~66) winsize 62
786 18:00:58.799262 [CA 3] Center 35 (4~66) winsize 63
787 18:00:58.803015 [CA 4] Center 34 (3~65) winsize 63
788 18:00:58.806677 [CA 5] Center 33 (3~64) winsize 62
789 18:00:58.806758
790 18:00:58.810136 [CmdBusTrainingLP45] Vref(ca) range 1: 34
791 18:00:58.810241
792 18:00:58.813911 [CATrainingPosCal] consider 2 rank data
793 18:00:58.813993 u2DelayCellTimex100 = 270/100 ps
794 18:00:58.817915 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
795 18:00:58.824734 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
796 18:00:58.828607 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
797 18:00:58.828689 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
798 18:00:58.832115 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
799 18:00:58.835859 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
800 18:00:58.840003
801 18:00:58.840111 CA PerBit enable=1, Macro0, CA PI delay=33
802 18:00:58.843726
803 18:00:58.843833 [CBTSetCACLKResult] CA Dly = 33
804 18:00:58.847512 CS Dly: 5 (0~37)
805 18:00:58.847599
806 18:00:58.851410 ----->DramcWriteLeveling(PI) begin...
807 18:00:58.851496 ==
808 18:00:58.854600 Dram Type= 6, Freq= 0, CH_0, rank 0
809 18:00:58.859065 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
810 18:00:58.859150 ==
811 18:00:58.862873 Write leveling (Byte 0): 29 => 29
812 18:00:58.862986 Write leveling (Byte 1): 30 => 30
813 18:00:58.866539 DramcWriteLeveling(PI) end<-----
814 18:00:58.866627
815 18:00:58.866693 ==
816 18:00:58.870045 Dram Type= 6, Freq= 0, CH_0, rank 0
817 18:00:58.873804 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
818 18:00:58.873890 ==
819 18:00:58.877830 [Gating] SW mode calibration
820 18:00:58.883772 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
821 18:00:58.890892 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
822 18:00:58.894044 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
823 18:00:58.897288 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
824 18:00:58.901530 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
825 18:00:58.908410 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
826 18:00:58.911681 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 18:00:58.915348 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 18:00:58.918955 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
829 18:00:58.926236 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
830 18:00:58.930299 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
831 18:00:58.933465 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
832 18:00:58.937097 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
833 18:00:58.940757 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
834 18:00:58.947871 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
835 18:00:58.951660 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
836 18:00:58.955357 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
837 18:00:58.959104 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
838 18:00:58.963518 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
839 18:00:58.967428 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
840 18:00:58.974413 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
841 18:00:58.978047 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
842 18:00:58.981843 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
843 18:00:58.985027 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
844 18:00:58.989228 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
845 18:00:58.996664 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
846 18:00:59.000649 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
847 18:00:59.003893 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
848 18:00:59.007611 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
849 18:00:59.010932 0 9 12 | B1->B0 | 2929 3333 | 0 1 | (0 0) (1 1)
850 18:00:59.018268 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
851 18:00:59.022581 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
852 18:00:59.026295 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
853 18:00:59.029986 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
854 18:00:59.033845 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
855 18:00:59.037430 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
856 18:00:59.045092 0 10 8 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 1)
857 18:00:59.048573 0 10 12 | B1->B0 | 2e2e 2323 | 1 0 | (1 0) (1 0)
858 18:00:59.052403 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 18:00:59.055903 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 18:00:59.059866 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 18:00:59.063848 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 18:00:59.071206 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 18:00:59.075109 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 18:00:59.078186 0 11 8 | B1->B0 | 2424 2d2d | 0 1 | (0 0) (0 0)
865 18:00:59.082411 0 11 12 | B1->B0 | 3636 3e3e | 1 0 | (0 0) (0 0)
866 18:00:59.085550 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
867 18:00:59.092808 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
868 18:00:59.097269 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
869 18:00:59.100953 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
870 18:00:59.104072 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
871 18:00:59.107760 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
872 18:00:59.115305 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
873 18:00:59.119048 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
874 18:00:59.122904 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
875 18:00:59.126536 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
876 18:00:59.130333 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
877 18:00:59.133845 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
878 18:00:59.141648 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
879 18:00:59.145382 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
880 18:00:59.149136 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
881 18:00:59.152625 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
882 18:00:59.156518 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
883 18:00:59.164390 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
884 18:00:59.167412 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
885 18:00:59.171619 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
886 18:00:59.175017 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
887 18:00:59.178966 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
888 18:00:59.182324 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
889 18:00:59.189597 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
890 18:00:59.193581 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
891 18:00:59.197632 Total UI for P1: 0, mck2ui 16
892 18:00:59.201398 best dqsien dly found for B0: ( 0, 14, 8)
893 18:00:59.201480 Total UI for P1: 0, mck2ui 16
894 18:00:59.204605 best dqsien dly found for B1: ( 0, 14, 10)
895 18:00:59.208342 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
896 18:00:59.211993 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
897 18:00:59.212098
898 18:00:59.215549 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
899 18:00:59.219315 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
900 18:00:59.223119 [Gating] SW calibration Done
901 18:00:59.223210 ==
902 18:00:59.226260 Dram Type= 6, Freq= 0, CH_0, rank 0
903 18:00:59.230618 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
904 18:00:59.230696 ==
905 18:00:59.234343 RX Vref Scan: 0
906 18:00:59.234428
907 18:00:59.234495 RX Vref 0 -> 0, step: 1
908 18:00:59.234558
909 18:00:59.238065 RX Delay -130 -> 252, step: 16
910 18:00:59.241313 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
911 18:00:59.245688 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
912 18:00:59.248871 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
913 18:00:59.252848 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
914 18:00:59.256516 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
915 18:00:59.260216 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
916 18:00:59.267475 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
917 18:00:59.271124 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
918 18:00:59.275317 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
919 18:00:59.278517 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
920 18:00:59.282237 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
921 18:00:59.286377 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
922 18:00:59.289646 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
923 18:00:59.293659 iDelay=222, Bit 13, Center 77 (-34 ~ 189) 224
924 18:00:59.297829 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
925 18:00:59.301210 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
926 18:00:59.301295 ==
927 18:00:59.305404 Dram Type= 6, Freq= 0, CH_0, rank 0
928 18:00:59.308392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
929 18:00:59.308477 ==
930 18:00:59.312341 DQS Delay:
931 18:00:59.312426 DQS0 = 0, DQS1 = 0
932 18:00:59.312493 DQM Delay:
933 18:00:59.316107 DQM0 = 85, DQM1 = 77
934 18:00:59.316193 DQ Delay:
935 18:00:59.320332 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =77
936 18:00:59.324079 DQ4 =85, DQ5 =69, DQ6 =101, DQ7 =93
937 18:00:59.327276 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
938 18:00:59.331022 DQ12 =85, DQ13 =77, DQ14 =85, DQ15 =85
939 18:00:59.331138
940 18:00:59.331232
941 18:00:59.331322 ==
942 18:00:59.334843 Dram Type= 6, Freq= 0, CH_0, rank 0
943 18:00:59.338456 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
944 18:00:59.338542 ==
945 18:00:59.338609
946 18:00:59.338671
947 18:00:59.342125 TX Vref Scan disable
948 18:00:59.342209 == TX Byte 0 ==
949 18:00:59.345799 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
950 18:00:59.349691 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
951 18:00:59.352797 == TX Byte 1 ==
952 18:00:59.356491 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
953 18:00:59.359634 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
954 18:00:59.359719 ==
955 18:00:59.363394 Dram Type= 6, Freq= 0, CH_0, rank 0
956 18:00:59.370132 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
957 18:00:59.370217 ==
958 18:00:59.381417 TX Vref=22, minBit 7, minWin=26, winSum=437
959 18:00:59.385086 TX Vref=24, minBit 3, minWin=27, winSum=442
960 18:00:59.388153 TX Vref=26, minBit 5, minWin=27, winSum=447
961 18:00:59.391905 TX Vref=28, minBit 0, minWin=28, winSum=450
962 18:00:59.394896 TX Vref=30, minBit 2, minWin=28, winSum=453
963 18:00:59.398426 TX Vref=32, minBit 1, minWin=28, winSum=451
964 18:00:59.405155 [TxChooseVref] Worse bit 2, Min win 28, Win sum 453, Final Vref 30
965 18:00:59.405235
966 18:00:59.408215 Final TX Range 1 Vref 30
967 18:00:59.408317
968 18:00:59.408409 ==
969 18:00:59.411844 Dram Type= 6, Freq= 0, CH_0, rank 0
970 18:00:59.415370 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
971 18:00:59.415472 ==
972 18:00:59.415566
973 18:00:59.415659
974 18:00:59.418670 TX Vref Scan disable
975 18:00:59.422073 == TX Byte 0 ==
976 18:00:59.425130 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
977 18:00:59.428757 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
978 18:00:59.431955 == TX Byte 1 ==
979 18:00:59.435068 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
980 18:00:59.438827 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
981 18:00:59.438912
982 18:00:59.441829 [DATLAT]
983 18:00:59.441914 Freq=800, CH0 RK0
984 18:00:59.441981
985 18:00:59.445458 DATLAT Default: 0xa
986 18:00:59.445542 0, 0xFFFF, sum = 0
987 18:00:59.448435 1, 0xFFFF, sum = 0
988 18:00:59.448524 2, 0xFFFF, sum = 0
989 18:00:59.452268 3, 0xFFFF, sum = 0
990 18:00:59.452355 4, 0xFFFF, sum = 0
991 18:00:59.455411 5, 0xFFFF, sum = 0
992 18:00:59.455496 6, 0xFFFF, sum = 0
993 18:00:59.458720 7, 0xFFFF, sum = 0
994 18:00:59.458805 8, 0xFFFF, sum = 0
995 18:00:59.462299 9, 0x0, sum = 1
996 18:00:59.462384 10, 0x0, sum = 2
997 18:00:59.465601 11, 0x0, sum = 3
998 18:00:59.465686 12, 0x0, sum = 4
999 18:00:59.468927 best_step = 10
1000 18:00:59.469048
1001 18:00:59.469116 ==
1002 18:00:59.472586 Dram Type= 6, Freq= 0, CH_0, rank 0
1003 18:00:59.475796 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1004 18:00:59.475881 ==
1005 18:00:59.475947 RX Vref Scan: 1
1006 18:00:59.476010
1007 18:00:59.479469 Set Vref Range= 32 -> 127
1008 18:00:59.479553
1009 18:00:59.482617 RX Vref 32 -> 127, step: 1
1010 18:00:59.482701
1011 18:00:59.486338 RX Delay -95 -> 252, step: 8
1012 18:00:59.486422
1013 18:00:59.489313 Set Vref, RX VrefLevel [Byte0]: 32
1014 18:00:59.492596 [Byte1]: 32
1015 18:00:59.492679
1016 18:00:59.495718 Set Vref, RX VrefLevel [Byte0]: 33
1017 18:00:59.499264 [Byte1]: 33
1018 18:00:59.499349
1019 18:00:59.502320 Set Vref, RX VrefLevel [Byte0]: 34
1020 18:00:59.506032 [Byte1]: 34
1021 18:00:59.509654
1022 18:00:59.509738 Set Vref, RX VrefLevel [Byte0]: 35
1023 18:00:59.512499 [Byte1]: 35
1024 18:00:59.516892
1025 18:00:59.517003 Set Vref, RX VrefLevel [Byte0]: 36
1026 18:00:59.520057 [Byte1]: 36
1027 18:00:59.524436
1028 18:00:59.524520 Set Vref, RX VrefLevel [Byte0]: 37
1029 18:00:59.527858 [Byte1]: 37
1030 18:00:59.532315
1031 18:00:59.532398 Set Vref, RX VrefLevel [Byte0]: 38
1032 18:00:59.535454 [Byte1]: 38
1033 18:00:59.540138
1034 18:00:59.540220 Set Vref, RX VrefLevel [Byte0]: 39
1035 18:00:59.543219 [Byte1]: 39
1036 18:00:59.547430
1037 18:00:59.547512 Set Vref, RX VrefLevel [Byte0]: 40
1038 18:00:59.550403 [Byte1]: 40
1039 18:00:59.554731
1040 18:00:59.554813 Set Vref, RX VrefLevel [Byte0]: 41
1041 18:00:59.557941 [Byte1]: 41
1042 18:00:59.562369
1043 18:00:59.562451 Set Vref, RX VrefLevel [Byte0]: 42
1044 18:00:59.565601 [Byte1]: 42
1045 18:00:59.570123
1046 18:00:59.570205 Set Vref, RX VrefLevel [Byte0]: 43
1047 18:00:59.573183 [Byte1]: 43
1048 18:00:59.577731
1049 18:00:59.577813 Set Vref, RX VrefLevel [Byte0]: 44
1050 18:00:59.580844 [Byte1]: 44
1051 18:00:59.585238
1052 18:00:59.585321 Set Vref, RX VrefLevel [Byte0]: 45
1053 18:00:59.588864 [Byte1]: 45
1054 18:00:59.593229
1055 18:00:59.593311 Set Vref, RX VrefLevel [Byte0]: 46
1056 18:00:59.596351 [Byte1]: 46
1057 18:00:59.600578
1058 18:00:59.600661 Set Vref, RX VrefLevel [Byte0]: 47
1059 18:00:59.603848 [Byte1]: 47
1060 18:00:59.608113
1061 18:00:59.608195 Set Vref, RX VrefLevel [Byte0]: 48
1062 18:00:59.611151 [Byte1]: 48
1063 18:00:59.615560
1064 18:00:59.615642 Set Vref, RX VrefLevel [Byte0]: 49
1065 18:00:59.619035 [Byte1]: 49
1066 18:00:59.623197
1067 18:00:59.623281 Set Vref, RX VrefLevel [Byte0]: 50
1068 18:00:59.626907 [Byte1]: 50
1069 18:00:59.630667
1070 18:00:59.630750 Set Vref, RX VrefLevel [Byte0]: 51
1071 18:00:59.633871 [Byte1]: 51
1072 18:00:59.638813
1073 18:00:59.638895 Set Vref, RX VrefLevel [Byte0]: 52
1074 18:00:59.641848 [Byte1]: 52
1075 18:00:59.645795
1076 18:00:59.645878 Set Vref, RX VrefLevel [Byte0]: 53
1077 18:00:59.649182 [Byte1]: 53
1078 18:00:59.653704
1079 18:00:59.653787 Set Vref, RX VrefLevel [Byte0]: 54
1080 18:00:59.657269 [Byte1]: 54
1081 18:00:59.661188
1082 18:00:59.664227 Set Vref, RX VrefLevel [Byte0]: 55
1083 18:00:59.664310 [Byte1]: 55
1084 18:00:59.668651
1085 18:00:59.668733 Set Vref, RX VrefLevel [Byte0]: 56
1086 18:00:59.671914 [Byte1]: 56
1087 18:00:59.676141
1088 18:00:59.676223 Set Vref, RX VrefLevel [Byte0]: 57
1089 18:00:59.679886 [Byte1]: 57
1090 18:00:59.684158
1091 18:00:59.684240 Set Vref, RX VrefLevel [Byte0]: 58
1092 18:00:59.687305 [Byte1]: 58
1093 18:00:59.691648
1094 18:00:59.691730 Set Vref, RX VrefLevel [Byte0]: 59
1095 18:00:59.694841 [Byte1]: 59
1096 18:00:59.699343
1097 18:00:59.699426 Set Vref, RX VrefLevel [Byte0]: 60
1098 18:00:59.702477 [Byte1]: 60
1099 18:00:59.706841
1100 18:00:59.706924 Set Vref, RX VrefLevel [Byte0]: 61
1101 18:00:59.709909 [Byte1]: 61
1102 18:00:59.714653
1103 18:00:59.714735 Set Vref, RX VrefLevel [Byte0]: 62
1104 18:00:59.717520 [Byte1]: 62
1105 18:00:59.722236
1106 18:00:59.722373 Set Vref, RX VrefLevel [Byte0]: 63
1107 18:00:59.725575 [Byte1]: 63
1108 18:00:59.729631
1109 18:00:59.729715 Set Vref, RX VrefLevel [Byte0]: 64
1110 18:00:59.733039 [Byte1]: 64
1111 18:00:59.737054
1112 18:00:59.737143 Set Vref, RX VrefLevel [Byte0]: 65
1113 18:00:59.740646 [Byte1]: 65
1114 18:00:59.745069
1115 18:00:59.745178 Set Vref, RX VrefLevel [Byte0]: 66
1116 18:00:59.748140 [Byte1]: 66
1117 18:00:59.752438
1118 18:00:59.752541 Set Vref, RX VrefLevel [Byte0]: 67
1119 18:00:59.755575 [Byte1]: 67
1120 18:00:59.759706
1121 18:00:59.759809 Set Vref, RX VrefLevel [Byte0]: 68
1122 18:00:59.763204 [Byte1]: 68
1123 18:00:59.767670
1124 18:00:59.767774 Set Vref, RX VrefLevel [Byte0]: 69
1125 18:00:59.771080 [Byte1]: 69
1126 18:00:59.774979
1127 18:00:59.775083 Set Vref, RX VrefLevel [Byte0]: 70
1128 18:00:59.778363 [Byte1]: 70
1129 18:00:59.782672
1130 18:00:59.782773 Set Vref, RX VrefLevel [Byte0]: 71
1131 18:00:59.785884 [Byte1]: 71
1132 18:00:59.790279
1133 18:00:59.790359 Set Vref, RX VrefLevel [Byte0]: 72
1134 18:00:59.793415 [Byte1]: 72
1135 18:00:59.797885
1136 18:00:59.797987 Set Vref, RX VrefLevel [Byte0]: 73
1137 18:00:59.801087 [Byte1]: 73
1138 18:00:59.805397
1139 18:00:59.805471 Set Vref, RX VrefLevel [Byte0]: 74
1140 18:00:59.809093 [Byte1]: 74
1141 18:00:59.812871
1142 18:00:59.812992 Set Vref, RX VrefLevel [Byte0]: 75
1143 18:00:59.816766 [Byte1]: 75
1144 18:00:59.820817
1145 18:00:59.820921 Set Vref, RX VrefLevel [Byte0]: 76
1146 18:00:59.823862 [Byte1]: 76
1147 18:00:59.828412
1148 18:00:59.828495 Set Vref, RX VrefLevel [Byte0]: 77
1149 18:00:59.831475 [Byte1]: 77
1150 18:00:59.835619
1151 18:00:59.835703 Final RX Vref Byte 0 = 60 to rank0
1152 18:00:59.839349 Final RX Vref Byte 1 = 59 to rank0
1153 18:00:59.842445 Final RX Vref Byte 0 = 60 to rank1
1154 18:00:59.845846 Final RX Vref Byte 1 = 59 to rank1==
1155 18:00:59.849449 Dram Type= 6, Freq= 0, CH_0, rank 0
1156 18:00:59.852625 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1157 18:00:59.856435 ==
1158 18:00:59.856519 DQS Delay:
1159 18:00:59.856584 DQS0 = 0, DQS1 = 0
1160 18:00:59.859666 DQM Delay:
1161 18:00:59.859751 DQM0 = 87, DQM1 = 78
1162 18:00:59.863420 DQ Delay:
1163 18:00:59.863574 DQ0 =88, DQ1 =92, DQ2 =84, DQ3 =84
1164 18:00:59.867095 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =92
1165 18:00:59.871334 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =76
1166 18:00:59.874379 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =88
1167 18:00:59.874462
1168 18:00:59.874544
1169 18:00:59.881543 [DQSOSCAuto] RK0, (LSB)MR18= 0x2c13, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 398 ps
1170 18:00:59.885101 CH0 RK0: MR19=606, MR18=2C13
1171 18:00:59.892395 CH0_RK0: MR19=0x606, MR18=0x2C13, DQSOSC=398, MR23=63, INC=93, DEC=62
1172 18:00:59.892498
1173 18:00:59.895519 ----->DramcWriteLeveling(PI) begin...
1174 18:00:59.895637 ==
1175 18:00:59.899355 Dram Type= 6, Freq= 0, CH_0, rank 1
1176 18:00:59.902479 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1177 18:00:59.902563 ==
1178 18:00:59.905611 Write leveling (Byte 0): 31 => 31
1179 18:00:59.908897 Write leveling (Byte 1): 31 => 31
1180 18:00:59.912543 DramcWriteLeveling(PI) end<-----
1181 18:00:59.912625
1182 18:00:59.912690 ==
1183 18:00:59.915725 Dram Type= 6, Freq= 0, CH_0, rank 1
1184 18:00:59.918949 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1185 18:00:59.919033 ==
1186 18:00:59.922709 [Gating] SW mode calibration
1187 18:00:59.929459 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1188 18:00:59.935881 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1189 18:00:59.939088 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1190 18:00:59.942921 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1191 18:00:59.949548 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1192 18:00:59.953102 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 18:00:59.956586 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 18:00:59.962815 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1195 18:00:59.966578 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1196 18:00:59.969707 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1197 18:00:59.972705 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1198 18:00:59.979557 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1199 18:00:59.983116 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1200 18:00:59.986032 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1201 18:00:59.992742 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1202 18:00:59.996573 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1203 18:01:00.000235 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1204 18:01:00.006368 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1205 18:01:00.009930 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1206 18:01:00.013121 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1207 18:01:00.019993 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1208 18:01:00.023112 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1209 18:01:00.026807 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1210 18:01:00.033000 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1211 18:01:00.036697 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1212 18:01:00.039796 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1213 18:01:00.043001 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1214 18:01:00.049625 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1215 18:01:00.053062 0 9 8 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
1216 18:01:00.056381 0 9 12 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
1217 18:01:00.063109 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1218 18:01:00.066889 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1219 18:01:00.070020 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1220 18:01:00.077116 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1221 18:01:00.080089 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1222 18:01:00.083222 0 10 4 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 0)
1223 18:01:00.089889 0 10 8 | B1->B0 | 3333 2828 | 0 0 | (0 0) (0 0)
1224 18:01:00.093605 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 18:01:00.096816 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 18:01:00.103591 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 18:01:00.106611 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 18:01:00.110305 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 18:01:00.113294 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 18:01:00.120127 0 11 4 | B1->B0 | 2323 2727 | 0 1 | (0 0) (0 0)
1231 18:01:00.123414 0 11 8 | B1->B0 | 2d2d 4040 | 0 0 | (0 0) (0 0)
1232 18:01:00.127019 0 11 12 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
1233 18:01:00.133746 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1234 18:01:00.136930 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1235 18:01:00.140006 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1236 18:01:00.146886 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1237 18:01:00.150036 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1238 18:01:00.153692 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1239 18:01:00.160374 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1240 18:01:00.163986 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1241 18:01:00.166765 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1242 18:01:00.174173 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1243 18:01:00.177420 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1244 18:01:00.180542 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1245 18:01:00.183722 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1246 18:01:00.190529 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1247 18:01:00.194187 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1248 18:01:00.197302 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1249 18:01:00.204131 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1250 18:01:00.207271 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1251 18:01:00.210321 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1252 18:01:00.217246 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1253 18:01:00.220968 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1254 18:01:00.224054 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1255 18:01:00.230578 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1256 18:01:00.230763 Total UI for P1: 0, mck2ui 16
1257 18:01:00.237300 best dqsien dly found for B0: ( 0, 14, 4)
1258 18:01:00.237460 Total UI for P1: 0, mck2ui 16
1259 18:01:00.240813 best dqsien dly found for B1: ( 0, 14, 6)
1260 18:01:00.243763 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1261 18:01:00.250780 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1262 18:01:00.250868
1263 18:01:00.253922 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1264 18:01:00.257801 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1265 18:01:00.260563 [Gating] SW calibration Done
1266 18:01:00.260675 ==
1267 18:01:00.264067 Dram Type= 6, Freq= 0, CH_0, rank 1
1268 18:01:00.267250 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1269 18:01:00.267371 ==
1270 18:01:00.267464 RX Vref Scan: 0
1271 18:01:00.270883
1272 18:01:00.270965 RX Vref 0 -> 0, step: 1
1273 18:01:00.271030
1274 18:01:00.273872 RX Delay -130 -> 252, step: 16
1275 18:01:00.277429 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1276 18:01:00.280547 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1277 18:01:00.287264 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1278 18:01:00.290954 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1279 18:01:00.294118 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1280 18:01:00.297288 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1281 18:01:00.300949 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1282 18:01:00.307857 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1283 18:01:00.311008 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
1284 18:01:00.314144 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1285 18:01:00.317355 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1286 18:01:00.321172 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1287 18:01:00.327437 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
1288 18:01:00.331224 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1289 18:01:00.334386 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1290 18:01:00.337548 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1291 18:01:00.337636 ==
1292 18:01:00.341002 Dram Type= 6, Freq= 0, CH_0, rank 1
1293 18:01:00.344479 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1294 18:01:00.347999 ==
1295 18:01:00.348096 DQS Delay:
1296 18:01:00.348197 DQS0 = 0, DQS1 = 0
1297 18:01:00.351155 DQM Delay:
1298 18:01:00.351291 DQM0 = 86, DQM1 = 75
1299 18:01:00.354535 DQ Delay:
1300 18:01:00.354653 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
1301 18:01:00.357741 DQ4 =85, DQ5 =69, DQ6 =101, DQ7 =93
1302 18:01:00.361534 DQ8 =61, DQ9 =69, DQ10 =69, DQ11 =69
1303 18:01:00.364359 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =85
1304 18:01:00.364470
1305 18:01:00.368080
1306 18:01:00.368171 ==
1307 18:01:00.371162 Dram Type= 6, Freq= 0, CH_0, rank 1
1308 18:01:00.374848 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1309 18:01:00.374938 ==
1310 18:01:00.375006
1311 18:01:00.375068
1312 18:01:00.377977 TX Vref Scan disable
1313 18:01:00.378062 == TX Byte 0 ==
1314 18:01:00.384652 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1315 18:01:00.387657 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1316 18:01:00.387768 == TX Byte 1 ==
1317 18:01:00.394736 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1318 18:01:00.397801 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1319 18:01:00.397908 ==
1320 18:01:00.401512 Dram Type= 6, Freq= 0, CH_0, rank 1
1321 18:01:00.404486 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1322 18:01:00.404595 ==
1323 18:01:00.418059 TX Vref=22, minBit 0, minWin=27, winSum=446
1324 18:01:00.421373 TX Vref=24, minBit 9, minWin=27, winSum=450
1325 18:01:00.424375 TX Vref=26, minBit 9, minWin=27, winSum=452
1326 18:01:00.427697 TX Vref=28, minBit 5, minWin=28, winSum=458
1327 18:01:00.431364 TX Vref=30, minBit 4, minWin=28, winSum=456
1328 18:01:00.434528 TX Vref=32, minBit 4, minWin=28, winSum=456
1329 18:01:00.441424 [TxChooseVref] Worse bit 5, Min win 28, Win sum 458, Final Vref 28
1330 18:01:00.441547
1331 18:01:00.444594 Final TX Range 1 Vref 28
1332 18:01:00.444682
1333 18:01:00.444780 ==
1334 18:01:00.447775 Dram Type= 6, Freq= 0, CH_0, rank 1
1335 18:01:00.451435 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1336 18:01:00.451532 ==
1337 18:01:00.451600
1338 18:01:00.451663
1339 18:01:00.454995 TX Vref Scan disable
1340 18:01:00.458044 == TX Byte 0 ==
1341 18:01:00.461400 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1342 18:01:00.464601 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1343 18:01:00.468175 == TX Byte 1 ==
1344 18:01:00.471486 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1345 18:01:00.474747 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1346 18:01:00.474860
1347 18:01:00.478177 [DATLAT]
1348 18:01:00.478261 Freq=800, CH0 RK1
1349 18:01:00.478362
1350 18:01:00.481768 DATLAT Default: 0xa
1351 18:01:00.481880 0, 0xFFFF, sum = 0
1352 18:01:00.484809 1, 0xFFFF, sum = 0
1353 18:01:00.484914 2, 0xFFFF, sum = 0
1354 18:01:00.488572 3, 0xFFFF, sum = 0
1355 18:01:00.488679 4, 0xFFFF, sum = 0
1356 18:01:00.491763 5, 0xFFFF, sum = 0
1357 18:01:00.491876 6, 0xFFFF, sum = 0
1358 18:01:00.494854 7, 0xFFFF, sum = 0
1359 18:01:00.494965 8, 0xFFFF, sum = 0
1360 18:01:00.498478 9, 0x0, sum = 1
1361 18:01:00.498593 10, 0x0, sum = 2
1362 18:01:00.501487 11, 0x0, sum = 3
1363 18:01:00.501600 12, 0x0, sum = 4
1364 18:01:00.505189 best_step = 10
1365 18:01:00.505297
1366 18:01:00.505391 ==
1367 18:01:00.508680 Dram Type= 6, Freq= 0, CH_0, rank 1
1368 18:01:00.511578 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1369 18:01:00.511663 ==
1370 18:01:00.511728 RX Vref Scan: 0
1371 18:01:00.514826
1372 18:01:00.514901 RX Vref 0 -> 0, step: 1
1373 18:01:00.514964
1374 18:01:00.518626 RX Delay -95 -> 252, step: 8
1375 18:01:00.521941 iDelay=209, Bit 0, Center 84 (-31 ~ 200) 232
1376 18:01:00.528867 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1377 18:01:00.532510 iDelay=209, Bit 2, Center 84 (-31 ~ 200) 232
1378 18:01:00.536151 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1379 18:01:00.540096 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1380 18:01:00.543805 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1381 18:01:00.547575 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1382 18:01:00.550824 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1383 18:01:00.555207 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
1384 18:01:00.558303 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1385 18:01:00.562092 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1386 18:01:00.565902 iDelay=209, Bit 11, Center 68 (-39 ~ 176) 216
1387 18:01:00.572720 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1388 18:01:00.575688 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1389 18:01:00.579427 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1390 18:01:00.582674 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1391 18:01:00.582756 ==
1392 18:01:00.585779 Dram Type= 6, Freq= 0, CH_0, rank 1
1393 18:01:00.589394 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1394 18:01:00.592567 ==
1395 18:01:00.592650 DQS Delay:
1396 18:01:00.592715 DQS0 = 0, DQS1 = 0
1397 18:01:00.596135 DQM Delay:
1398 18:01:00.596216 DQM0 = 87, DQM1 = 78
1399 18:01:00.599590 DQ Delay:
1400 18:01:00.599672 DQ0 =84, DQ1 =88, DQ2 =84, DQ3 =84
1401 18:01:00.602636 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1402 18:01:00.606213 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1403 18:01:00.609356 DQ12 =84, DQ13 =84, DQ14 =88, DQ15 =88
1404 18:01:00.609438
1405 18:01:00.609502
1406 18:01:00.619283 [DQSOSCAuto] RK1, (LSB)MR18= 0x2b15, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 398 ps
1407 18:01:00.623006 CH0 RK1: MR19=606, MR18=2B15
1408 18:01:00.629299 CH0_RK1: MR19=0x606, MR18=0x2B15, DQSOSC=398, MR23=63, INC=93, DEC=62
1409 18:01:00.629384 [RxdqsGatingPostProcess] freq 800
1410 18:01:00.636265 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1411 18:01:00.639965 Pre-setting of DQS Precalculation
1412 18:01:00.643193 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1413 18:01:00.646355 ==
1414 18:01:00.646437 Dram Type= 6, Freq= 0, CH_1, rank 0
1415 18:01:00.653210 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1416 18:01:00.653293 ==
1417 18:01:00.656329 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1418 18:01:00.663266 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1419 18:01:00.672651 [CA 0] Center 36 (6~67) winsize 62
1420 18:01:00.675790 [CA 1] Center 36 (6~67) winsize 62
1421 18:01:00.679039 [CA 2] Center 34 (4~65) winsize 62
1422 18:01:00.682842 [CA 3] Center 34 (3~65) winsize 63
1423 18:01:00.685941 [CA 4] Center 34 (4~65) winsize 62
1424 18:01:00.689633 [CA 5] Center 33 (3~64) winsize 62
1425 18:01:00.689716
1426 18:01:00.692658 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1427 18:01:00.692740
1428 18:01:00.696465 [CATrainingPosCal] consider 1 rank data
1429 18:01:00.699542 u2DelayCellTimex100 = 270/100 ps
1430 18:01:00.702642 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1431 18:01:00.706113 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1432 18:01:00.709725 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1433 18:01:00.716287 CA3 delay=34 (3~65),Diff = 1 PI (7 cell)
1434 18:01:00.719410 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1435 18:01:00.722774 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1436 18:01:00.722857
1437 18:01:00.726294 CA PerBit enable=1, Macro0, CA PI delay=33
1438 18:01:00.726377
1439 18:01:00.729664 [CBTSetCACLKResult] CA Dly = 33
1440 18:01:00.729746 CS Dly: 5 (0~36)
1441 18:01:00.729828 ==
1442 18:01:00.733153 Dram Type= 6, Freq= 0, CH_1, rank 1
1443 18:01:00.739570 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1444 18:01:00.739681 ==
1445 18:01:00.742766 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1446 18:01:00.749511 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1447 18:01:00.758406 [CA 0] Center 36 (6~66) winsize 61
1448 18:01:00.762213 [CA 1] Center 36 (6~66) winsize 61
1449 18:01:00.765444 [CA 2] Center 34 (4~65) winsize 62
1450 18:01:00.768637 [CA 3] Center 33 (3~64) winsize 62
1451 18:01:00.771803 [CA 4] Center 34 (4~65) winsize 62
1452 18:01:00.775585 [CA 5] Center 33 (3~64) winsize 62
1453 18:01:00.775667
1454 18:01:00.778753 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1455 18:01:00.778836
1456 18:01:00.782061 [CATrainingPosCal] consider 2 rank data
1457 18:01:00.785160 u2DelayCellTimex100 = 270/100 ps
1458 18:01:00.788862 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1459 18:01:00.792060 CA1 delay=36 (6~66),Diff = 3 PI (21 cell)
1460 18:01:00.798713 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1461 18:01:00.801958 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1462 18:01:00.805695 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1463 18:01:00.808800 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1464 18:01:00.808876
1465 18:01:00.811984 CA PerBit enable=1, Macro0, CA PI delay=33
1466 18:01:00.812055
1467 18:01:00.815556 [CBTSetCACLKResult] CA Dly = 33
1468 18:01:00.815637 CS Dly: 5 (0~36)
1469 18:01:00.815702
1470 18:01:00.819146 ----->DramcWriteLeveling(PI) begin...
1471 18:01:00.819229 ==
1472 18:01:00.822189 Dram Type= 6, Freq= 0, CH_1, rank 0
1473 18:01:00.828849 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1474 18:01:00.828933 ==
1475 18:01:00.832041 Write leveling (Byte 0): 28 => 28
1476 18:01:00.835599 Write leveling (Byte 1): 32 => 32
1477 18:01:00.835681 DramcWriteLeveling(PI) end<-----
1478 18:01:00.835746
1479 18:01:00.839003 ==
1480 18:01:00.842446 Dram Type= 6, Freq= 0, CH_1, rank 0
1481 18:01:00.845859 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1482 18:01:00.845942 ==
1483 18:01:00.848945 [Gating] SW mode calibration
1484 18:01:00.855582 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1485 18:01:00.859016 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1486 18:01:00.865961 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1487 18:01:00.868923 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1488 18:01:00.872831 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1489 18:01:00.879008 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 18:01:00.882649 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 18:01:00.885820 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 18:01:00.888861 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 18:01:00.895848 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1494 18:01:00.898999 0 7 0 | B1->B0 | 2322 2323 | 1 0 | (0 0) (0 0)
1495 18:01:00.902611 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1496 18:01:00.909346 0 7 8 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1497 18:01:00.912592 0 7 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1498 18:01:00.915769 0 7 16 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1499 18:01:00.922656 0 7 20 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1500 18:01:00.925836 0 7 24 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1501 18:01:00.929315 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1502 18:01:00.936111 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1503 18:01:00.939340 0 8 4 | B1->B0 | 2424 2323 | 0 0 | (0 1) (1 1)
1504 18:01:00.942478 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1505 18:01:00.949307 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1506 18:01:00.952836 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1507 18:01:00.955853 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1508 18:01:00.962686 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1509 18:01:00.966241 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1510 18:01:00.969535 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1511 18:01:00.972746 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1512 18:01:00.979434 0 9 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1513 18:01:00.982866 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1514 18:01:00.985994 0 9 16 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1515 18:01:00.992733 0 9 20 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1516 18:01:00.995959 0 9 24 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1517 18:01:00.999646 0 9 28 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1518 18:01:01.006292 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1519 18:01:01.009393 0 10 4 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 0)
1520 18:01:01.012949 0 10 8 | B1->B0 | 2b2b 2c2c | 1 1 | (1 1) (1 0)
1521 18:01:01.019871 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 18:01:01.023118 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 18:01:01.026387 0 10 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1524 18:01:01.030078 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 18:01:01.036770 0 10 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1526 18:01:01.039960 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 18:01:01.043023 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 18:01:01.049882 0 11 8 | B1->B0 | 3333 2e2e | 0 1 | (0 0) (0 0)
1529 18:01:01.053524 0 11 12 | B1->B0 | 4545 4646 | 1 0 | (0 0) (0 0)
1530 18:01:01.057080 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1531 18:01:01.063784 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1532 18:01:01.066877 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1533 18:01:01.070109 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1534 18:01:01.076880 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1535 18:01:01.080427 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1536 18:01:01.083834 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1537 18:01:01.087155 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1538 18:01:01.093808 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1539 18:01:01.097192 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1540 18:01:01.100710 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1541 18:01:01.106930 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1542 18:01:01.110673 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1543 18:01:01.114537 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1544 18:01:01.117567 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1545 18:01:01.124469 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1546 18:01:01.128397 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1547 18:01:01.131433 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1548 18:01:01.138335 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1549 18:01:01.141397 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1550 18:01:01.144354 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1551 18:01:01.151490 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1552 18:01:01.154714 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1553 18:01:01.158298 Total UI for P1: 0, mck2ui 16
1554 18:01:01.161149 best dqsien dly found for B0: ( 0, 14, 4)
1555 18:01:01.164730 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1556 18:01:01.168379 Total UI for P1: 0, mck2ui 16
1557 18:01:01.171413 best dqsien dly found for B1: ( 0, 14, 6)
1558 18:01:01.174645 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1559 18:01:01.178457 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1560 18:01:01.178539
1561 18:01:01.181561 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1562 18:01:01.184788 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1563 18:01:01.188019 [Gating] SW calibration Done
1564 18:01:01.188100 ==
1565 18:01:01.191833 Dram Type= 6, Freq= 0, CH_1, rank 0
1566 18:01:01.198515 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1567 18:01:01.198605 ==
1568 18:01:01.198698 RX Vref Scan: 0
1569 18:01:01.198762
1570 18:01:01.201677 RX Vref 0 -> 0, step: 1
1571 18:01:01.201759
1572 18:01:01.205187 RX Delay -130 -> 252, step: 16
1573 18:01:01.208724 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1574 18:01:01.211801 iDelay=206, Bit 1, Center 69 (-50 ~ 189) 240
1575 18:01:01.215050 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1576 18:01:01.218574 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1577 18:01:01.225377 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1578 18:01:01.228304 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1579 18:01:01.232106 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1580 18:01:01.235064 iDelay=206, Bit 7, Center 69 (-50 ~ 189) 240
1581 18:01:01.238870 iDelay=206, Bit 8, Center 61 (-66 ~ 189) 256
1582 18:01:01.241859 iDelay=206, Bit 9, Center 61 (-50 ~ 173) 224
1583 18:01:01.248686 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1584 18:01:01.251719 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1585 18:01:01.254937 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1586 18:01:01.258730 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1587 18:01:01.265570 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1588 18:01:01.268484 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1589 18:01:01.268570 ==
1590 18:01:01.272111 Dram Type= 6, Freq= 0, CH_1, rank 0
1591 18:01:01.275304 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1592 18:01:01.275397 ==
1593 18:01:01.275462 DQS Delay:
1594 18:01:01.278539 DQS0 = 0, DQS1 = 0
1595 18:01:01.278622 DQM Delay:
1596 18:01:01.282371 DQM0 = 81, DQM1 = 75
1597 18:01:01.282457 DQ Delay:
1598 18:01:01.285547 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =85
1599 18:01:01.288652 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =69
1600 18:01:01.292362 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =69
1601 18:01:01.295384 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1602 18:01:01.295469
1603 18:01:01.295533
1604 18:01:01.295593 ==
1605 18:01:01.299152 Dram Type= 6, Freq= 0, CH_1, rank 0
1606 18:01:01.302226 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1607 18:01:01.302313 ==
1608 18:01:01.302377
1609 18:01:01.305825
1610 18:01:01.305909 TX Vref Scan disable
1611 18:01:01.309004 == TX Byte 0 ==
1612 18:01:01.312183 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1613 18:01:01.315966 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1614 18:01:01.318855 == TX Byte 1 ==
1615 18:01:01.322374 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1616 18:01:01.325596 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1617 18:01:01.325744 ==
1618 18:01:01.328902 Dram Type= 6, Freq= 0, CH_1, rank 0
1619 18:01:01.335379 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1620 18:01:01.335503 ==
1621 18:01:01.347551 TX Vref=22, minBit 10, minWin=26, winSum=437
1622 18:01:01.351251 TX Vref=24, minBit 0, minWin=27, winSum=445
1623 18:01:01.354492 TX Vref=26, minBit 0, minWin=27, winSum=445
1624 18:01:01.357659 TX Vref=28, minBit 8, minWin=27, winSum=450
1625 18:01:01.361293 TX Vref=30, minBit 0, minWin=27, winSum=455
1626 18:01:01.364487 TX Vref=32, minBit 1, minWin=28, winSum=456
1627 18:01:01.371322 [TxChooseVref] Worse bit 1, Min win 28, Win sum 456, Final Vref 32
1628 18:01:01.371405
1629 18:01:01.374305 Final TX Range 1 Vref 32
1630 18:01:01.374380
1631 18:01:01.374442 ==
1632 18:01:01.377882 Dram Type= 6, Freq= 0, CH_1, rank 0
1633 18:01:01.381479 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1634 18:01:01.381568 ==
1635 18:01:01.381636
1636 18:01:01.381698
1637 18:01:01.384646 TX Vref Scan disable
1638 18:01:01.388396 == TX Byte 0 ==
1639 18:01:01.391366 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1640 18:01:01.394545 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1641 18:01:01.398279 == TX Byte 1 ==
1642 18:01:01.401436 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1643 18:01:01.404496 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1644 18:01:01.404582
1645 18:01:01.408125 [DATLAT]
1646 18:01:01.408209 Freq=800, CH1 RK0
1647 18:01:01.408278
1648 18:01:01.411214 DATLAT Default: 0xa
1649 18:01:01.411299 0, 0xFFFF, sum = 0
1650 18:01:01.414977 1, 0xFFFF, sum = 0
1651 18:01:01.415063 2, 0xFFFF, sum = 0
1652 18:01:01.418095 3, 0xFFFF, sum = 0
1653 18:01:01.418181 4, 0xFFFF, sum = 0
1654 18:01:01.421300 5, 0xFFFF, sum = 0
1655 18:01:01.421385 6, 0xFFFF, sum = 0
1656 18:01:01.425064 7, 0xFFFF, sum = 0
1657 18:01:01.425150 8, 0xFFFF, sum = 0
1658 18:01:01.428077 9, 0x0, sum = 1
1659 18:01:01.428163 10, 0x0, sum = 2
1660 18:01:01.431778 11, 0x0, sum = 3
1661 18:01:01.431896 12, 0x0, sum = 4
1662 18:01:01.435009 best_step = 10
1663 18:01:01.435093
1664 18:01:01.435159 ==
1665 18:01:01.438044 Dram Type= 6, Freq= 0, CH_1, rank 0
1666 18:01:01.441789 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1667 18:01:01.441875 ==
1668 18:01:01.441942 RX Vref Scan: 1
1669 18:01:01.445368
1670 18:01:01.445452 Set Vref Range= 32 -> 127
1671 18:01:01.445519
1672 18:01:01.448160 RX Vref 32 -> 127, step: 1
1673 18:01:01.448244
1674 18:01:01.451585 RX Delay -111 -> 252, step: 8
1675 18:01:01.451670
1676 18:01:01.454895 Set Vref, RX VrefLevel [Byte0]: 32
1677 18:01:01.458593 [Byte1]: 32
1678 18:01:01.458677
1679 18:01:01.461679 Set Vref, RX VrefLevel [Byte0]: 33
1680 18:01:01.464855 [Byte1]: 33
1681 18:01:01.464966
1682 18:01:01.468074 Set Vref, RX VrefLevel [Byte0]: 34
1683 18:01:01.471861 [Byte1]: 34
1684 18:01:01.475651
1685 18:01:01.475764 Set Vref, RX VrefLevel [Byte0]: 35
1686 18:01:01.478907 [Byte1]: 35
1687 18:01:01.483200
1688 18:01:01.483283 Set Vref, RX VrefLevel [Byte0]: 36
1689 18:01:01.490015 [Byte1]: 36
1690 18:01:01.490098
1691 18:01:01.492970 Set Vref, RX VrefLevel [Byte0]: 37
1692 18:01:01.496779 [Byte1]: 37
1693 18:01:01.496865
1694 18:01:01.499901 Set Vref, RX VrefLevel [Byte0]: 38
1695 18:01:01.503082 [Byte1]: 38
1696 18:01:01.503190
1697 18:01:01.506650 Set Vref, RX VrefLevel [Byte0]: 39
1698 18:01:01.510255 [Byte1]: 39
1699 18:01:01.513926
1700 18:01:01.514010 Set Vref, RX VrefLevel [Byte0]: 40
1701 18:01:01.517123 [Byte1]: 40
1702 18:01:01.521471
1703 18:01:01.521567 Set Vref, RX VrefLevel [Byte0]: 41
1704 18:01:01.525150 [Byte1]: 41
1705 18:01:01.529197
1706 18:01:01.529279 Set Vref, RX VrefLevel [Byte0]: 42
1707 18:01:01.532690 [Byte1]: 42
1708 18:01:01.537079
1709 18:01:01.537162 Set Vref, RX VrefLevel [Byte0]: 43
1710 18:01:01.540136 [Byte1]: 43
1711 18:01:01.544603
1712 18:01:01.544685 Set Vref, RX VrefLevel [Byte0]: 44
1713 18:01:01.547600 [Byte1]: 44
1714 18:01:01.551867
1715 18:01:01.551949 Set Vref, RX VrefLevel [Byte0]: 45
1716 18:01:01.555646 [Byte1]: 45
1717 18:01:01.559838
1718 18:01:01.559920 Set Vref, RX VrefLevel [Byte0]: 46
1719 18:01:01.562875 [Byte1]: 46
1720 18:01:01.567337
1721 18:01:01.567419 Set Vref, RX VrefLevel [Byte0]: 47
1722 18:01:01.570445 [Byte1]: 47
1723 18:01:01.575259
1724 18:01:01.575366 Set Vref, RX VrefLevel [Byte0]: 48
1725 18:01:01.578370 [Byte1]: 48
1726 18:01:01.582648
1727 18:01:01.582730 Set Vref, RX VrefLevel [Byte0]: 49
1728 18:01:01.585816 [Byte1]: 49
1729 18:01:01.590407
1730 18:01:01.590489 Set Vref, RX VrefLevel [Byte0]: 50
1731 18:01:01.593395 [Byte1]: 50
1732 18:01:01.597801
1733 18:01:01.597883 Set Vref, RX VrefLevel [Byte0]: 51
1734 18:01:01.601487 [Byte1]: 51
1735 18:01:01.605852
1736 18:01:01.605934 Set Vref, RX VrefLevel [Byte0]: 52
1737 18:01:01.608928 [Byte1]: 52
1738 18:01:01.613822
1739 18:01:01.613904 Set Vref, RX VrefLevel [Byte0]: 53
1740 18:01:01.616809 [Byte1]: 53
1741 18:01:01.621191
1742 18:01:01.621273 Set Vref, RX VrefLevel [Byte0]: 54
1743 18:01:01.624344 [Byte1]: 54
1744 18:01:01.628834
1745 18:01:01.628954 Set Vref, RX VrefLevel [Byte0]: 55
1746 18:01:01.631880 [Byte1]: 55
1747 18:01:01.636222
1748 18:01:01.636305 Set Vref, RX VrefLevel [Byte0]: 56
1749 18:01:01.639347 [Byte1]: 56
1750 18:01:01.643705
1751 18:01:01.643786 Set Vref, RX VrefLevel [Byte0]: 57
1752 18:01:01.647176 [Byte1]: 57
1753 18:01:01.651428
1754 18:01:01.651509 Set Vref, RX VrefLevel [Byte0]: 58
1755 18:01:01.655118 [Byte1]: 58
1756 18:01:01.659366
1757 18:01:01.659450 Set Vref, RX VrefLevel [Byte0]: 59
1758 18:01:01.662461 [Byte1]: 59
1759 18:01:01.666864
1760 18:01:01.666947 Set Vref, RX VrefLevel [Byte0]: 60
1761 18:01:01.670512 [Byte1]: 60
1762 18:01:01.674575
1763 18:01:01.674658 Set Vref, RX VrefLevel [Byte0]: 61
1764 18:01:01.678164 [Byte1]: 61
1765 18:01:01.682361
1766 18:01:01.682438 Set Vref, RX VrefLevel [Byte0]: 62
1767 18:01:01.685399 [Byte1]: 62
1768 18:01:01.689797
1769 18:01:01.689879 Set Vref, RX VrefLevel [Byte0]: 63
1770 18:01:01.692907 [Byte1]: 63
1771 18:01:01.697760
1772 18:01:01.697844 Set Vref, RX VrefLevel [Byte0]: 64
1773 18:01:01.700764 [Byte1]: 64
1774 18:01:01.704984
1775 18:01:01.705082 Set Vref, RX VrefLevel [Byte0]: 65
1776 18:01:01.708210 [Byte1]: 65
1777 18:01:01.712720
1778 18:01:01.712824 Set Vref, RX VrefLevel [Byte0]: 66
1779 18:01:01.716010 [Byte1]: 66
1780 18:01:01.720255
1781 18:01:01.720338 Set Vref, RX VrefLevel [Byte0]: 67
1782 18:01:01.723982 [Byte1]: 67
1783 18:01:01.728473
1784 18:01:01.728586 Set Vref, RX VrefLevel [Byte0]: 68
1785 18:01:01.731562 [Byte1]: 68
1786 18:01:01.735911
1787 18:01:01.735993 Set Vref, RX VrefLevel [Byte0]: 69
1788 18:01:01.739181 [Byte1]: 69
1789 18:01:01.743468
1790 18:01:01.743582 Set Vref, RX VrefLevel [Byte0]: 70
1791 18:01:01.746620 [Byte1]: 70
1792 18:01:01.750973
1793 18:01:01.751055 Set Vref, RX VrefLevel [Byte0]: 71
1794 18:01:01.754515 [Byte1]: 71
1795 18:01:01.758734
1796 18:01:01.758842 Set Vref, RX VrefLevel [Byte0]: 72
1797 18:01:01.761691 [Byte1]: 72
1798 18:01:01.766625
1799 18:01:01.766710 Set Vref, RX VrefLevel [Byte0]: 73
1800 18:01:01.769681 [Byte1]: 73
1801 18:01:01.774166
1802 18:01:01.774247 Set Vref, RX VrefLevel [Byte0]: 74
1803 18:01:01.777127 [Byte1]: 74
1804 18:01:01.781822
1805 18:01:01.781905 Set Vref, RX VrefLevel [Byte0]: 75
1806 18:01:01.784945 [Byte1]: 75
1807 18:01:01.789093
1808 18:01:01.789175 Set Vref, RX VrefLevel [Byte0]: 76
1809 18:01:01.792608 [Byte1]: 76
1810 18:01:01.797138
1811 18:01:01.797220 Set Vref, RX VrefLevel [Byte0]: 77
1812 18:01:01.800186 [Byte1]: 77
1813 18:01:01.804678
1814 18:01:01.804785 Set Vref, RX VrefLevel [Byte0]: 78
1815 18:01:01.808090 [Byte1]: 78
1816 18:01:01.812263
1817 18:01:01.812345 Set Vref, RX VrefLevel [Byte0]: 79
1818 18:01:01.815314 [Byte1]: 79
1819 18:01:01.819709
1820 18:01:01.819790 Final RX Vref Byte 0 = 57 to rank0
1821 18:01:01.823424 Final RX Vref Byte 1 = 59 to rank0
1822 18:01:01.826301 Final RX Vref Byte 0 = 57 to rank1
1823 18:01:01.830149 Final RX Vref Byte 1 = 59 to rank1==
1824 18:01:01.833373 Dram Type= 6, Freq= 0, CH_1, rank 0
1825 18:01:01.836436 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1826 18:01:01.840134 ==
1827 18:01:01.840215 DQS Delay:
1828 18:01:01.840279 DQS0 = 0, DQS1 = 0
1829 18:01:01.843288 DQM Delay:
1830 18:01:01.843369 DQM0 = 83, DQM1 = 74
1831 18:01:01.846336 DQ Delay:
1832 18:01:01.850082 DQ0 =88, DQ1 =76, DQ2 =72, DQ3 =84
1833 18:01:01.850164 DQ4 =84, DQ5 =92, DQ6 =96, DQ7 =76
1834 18:01:01.853142 DQ8 =60, DQ9 =60, DQ10 =76, DQ11 =72
1835 18:01:01.856383 DQ12 =84, DQ13 =84, DQ14 =80, DQ15 =76
1836 18:01:01.856467
1837 18:01:01.860118
1838 18:01:01.866543 [DQSOSCAuto] RK0, (LSB)MR18= 0x2d02, (MSB)MR19= 0x606, tDQSOscB0 = 409 ps tDQSOscB1 = 398 ps
1839 18:01:01.869959 CH1 RK0: MR19=606, MR18=2D02
1840 18:01:01.876830 CH1_RK0: MR19=0x606, MR18=0x2D02, DQSOSC=398, MR23=63, INC=93, DEC=62
1841 18:01:01.876913
1842 18:01:01.879897 ----->DramcWriteLeveling(PI) begin...
1843 18:01:01.880059 ==
1844 18:01:01.883540 Dram Type= 6, Freq= 0, CH_1, rank 1
1845 18:01:01.886645 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1846 18:01:01.886728 ==
1847 18:01:01.890439 Write leveling (Byte 0): 29 => 29
1848 18:01:01.893457 Write leveling (Byte 1): 29 => 29
1849 18:01:01.896843 DramcWriteLeveling(PI) end<-----
1850 18:01:01.896949
1851 18:01:01.897066 ==
1852 18:01:01.900414 Dram Type= 6, Freq= 0, CH_1, rank 1
1853 18:01:01.903659 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1854 18:01:01.903740 ==
1855 18:01:01.906696 [Gating] SW mode calibration
1856 18:01:01.913625 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1857 18:01:01.920700 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1858 18:01:01.923711 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1859 18:01:01.926919 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1860 18:01:01.930500 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1861 18:01:01.937244 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1862 18:01:01.940397 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1863 18:01:01.944111 0 6 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1864 18:01:01.950393 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1865 18:01:01.954124 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1866 18:01:01.957121 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1867 18:01:01.964245 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1868 18:01:01.967406 0 7 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1869 18:01:01.970525 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1870 18:01:01.977479 0 7 16 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1871 18:01:01.980530 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1872 18:01:01.984300 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1873 18:01:01.987377 0 7 28 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1874 18:01:01.994092 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1875 18:01:01.997477 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1876 18:01:02.001133 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1877 18:01:02.007364 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1878 18:01:02.011211 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 18:01:02.014316 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 18:01:02.021240 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 18:01:02.024352 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 18:01:02.027797 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 18:01:02.034249 0 9 4 | B1->B0 | 2424 2c2c | 0 0 | (0 0) (0 0)
1884 18:01:02.037605 0 9 8 | B1->B0 | 2828 3434 | 1 1 | (1 1) (1 1)
1885 18:01:02.041401 0 9 12 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1886 18:01:02.047759 0 9 16 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1887 18:01:02.050945 0 9 20 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1888 18:01:02.054120 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1889 18:01:02.057872 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1890 18:01:02.064342 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1891 18:01:02.068055 0 10 4 | B1->B0 | 3030 2c2c | 1 1 | (1 1) (1 0)
1892 18:01:02.071116 0 10 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1893 18:01:02.077761 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1894 18:01:02.081403 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1895 18:01:02.084838 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1896 18:01:02.091677 0 10 24 | B1->B0 | 2423 2323 | 1 0 | (0 0) (0 0)
1897 18:01:02.094832 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1898 18:01:02.097998 0 11 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1899 18:01:02.105001 0 11 4 | B1->B0 | 2626 3131 | 0 0 | (0 0) (0 0)
1900 18:01:02.108275 0 11 8 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
1901 18:01:02.111210 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1902 18:01:02.118584 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1903 18:01:02.121683 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1904 18:01:02.124784 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1905 18:01:02.128608 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1906 18:01:02.134994 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1907 18:01:02.138022 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1908 18:01:02.141597 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1909 18:01:02.148249 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1910 18:01:02.151354 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1911 18:01:02.155216 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1912 18:01:02.161965 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1913 18:01:02.165216 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1914 18:01:02.168385 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1915 18:01:02.175229 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1916 18:01:02.178348 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1917 18:01:02.182147 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1918 18:01:02.185313 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1919 18:01:02.191931 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1920 18:01:02.195422 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1921 18:01:02.198529 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1922 18:01:02.205351 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1923 18:01:02.208636 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1924 18:01:02.212246 Total UI for P1: 0, mck2ui 16
1925 18:01:02.215142 best dqsien dly found for B0: ( 0, 14, 0)
1926 18:01:02.218706 Total UI for P1: 0, mck2ui 16
1927 18:01:02.222109 best dqsien dly found for B1: ( 0, 14, 2)
1928 18:01:02.225653 best DQS0 dly(MCK, UI, PI) = (0, 14, 0)
1929 18:01:02.228825 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1930 18:01:02.228936
1931 18:01:02.231893 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 0)
1932 18:01:02.235713 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1933 18:01:02.238870 [Gating] SW calibration Done
1934 18:01:02.238945 ==
1935 18:01:02.242395 Dram Type= 6, Freq= 0, CH_1, rank 1
1936 18:01:02.245260 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1937 18:01:02.245337 ==
1938 18:01:02.248693 RX Vref Scan: 0
1939 18:01:02.248769
1940 18:01:02.252172 RX Vref 0 -> 0, step: 1
1941 18:01:02.252249
1942 18:01:02.252312 RX Delay -130 -> 252, step: 16
1943 18:01:02.258598 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1944 18:01:02.261892 iDelay=206, Bit 1, Center 69 (-50 ~ 189) 240
1945 18:01:02.265375 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1946 18:01:02.268656 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1947 18:01:02.272529 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1948 18:01:02.279436 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1949 18:01:02.282571 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1950 18:01:02.285628 iDelay=206, Bit 7, Center 77 (-34 ~ 189) 224
1951 18:01:02.289383 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1952 18:01:02.292578 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1953 18:01:02.295558 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
1954 18:01:02.302629 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1955 18:01:02.305841 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1956 18:01:02.308846 iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224
1957 18:01:02.312140 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1958 18:01:02.319023 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1959 18:01:02.319107 ==
1960 18:01:02.322611 Dram Type= 6, Freq= 0, CH_1, rank 1
1961 18:01:02.325644 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1962 18:01:02.325726 ==
1963 18:01:02.325790 DQS Delay:
1964 18:01:02.329212 DQS0 = 0, DQS1 = 0
1965 18:01:02.329296 DQM Delay:
1966 18:01:02.332266 DQM0 = 82, DQM1 = 79
1967 18:01:02.332347 DQ Delay:
1968 18:01:02.335945 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =85
1969 18:01:02.339053 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =77
1970 18:01:02.342892 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1971 18:01:02.346029 DQ12 =85, DQ13 =93, DQ14 =85, DQ15 =85
1972 18:01:02.346112
1973 18:01:02.346178
1974 18:01:02.346239 ==
1975 18:01:02.348963 Dram Type= 6, Freq= 0, CH_1, rank 1
1976 18:01:02.352638 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1977 18:01:02.352721 ==
1978 18:01:02.352814
1979 18:01:02.352877
1980 18:01:02.356183 TX Vref Scan disable
1981 18:01:02.359273 == TX Byte 0 ==
1982 18:01:02.362666 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1983 18:01:02.366369 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1984 18:01:02.369503 == TX Byte 1 ==
1985 18:01:02.372657 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1986 18:01:02.375798 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1987 18:01:02.375879 ==
1988 18:01:02.379548 Dram Type= 6, Freq= 0, CH_1, rank 1
1989 18:01:02.382849 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1990 18:01:02.385812 ==
1991 18:01:02.397332 TX Vref=22, minBit 1, minWin=27, winSum=444
1992 18:01:02.400529 TX Vref=24, minBit 1, minWin=27, winSum=445
1993 18:01:02.403655 TX Vref=26, minBit 0, minWin=28, winSum=449
1994 18:01:02.406793 TX Vref=28, minBit 0, minWin=28, winSum=452
1995 18:01:02.410480 TX Vref=30, minBit 0, minWin=28, winSum=451
1996 18:01:02.413930 TX Vref=32, minBit 1, minWin=27, winSum=452
1997 18:01:02.420499 [TxChooseVref] Worse bit 0, Min win 28, Win sum 452, Final Vref 28
1998 18:01:02.420581
1999 18:01:02.424088 Final TX Range 1 Vref 28
2000 18:01:02.424181
2001 18:01:02.424320 ==
2002 18:01:02.427046 Dram Type= 6, Freq= 0, CH_1, rank 1
2003 18:01:02.430683 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2004 18:01:02.430764 ==
2005 18:01:02.430827
2006 18:01:02.430885
2007 18:01:02.433716 TX Vref Scan disable
2008 18:01:02.437250 == TX Byte 0 ==
2009 18:01:02.440929 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2010 18:01:02.444107 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2011 18:01:02.447346 == TX Byte 1 ==
2012 18:01:02.450464 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2013 18:01:02.454199 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2014 18:01:02.454280
2015 18:01:02.457398 [DATLAT]
2016 18:01:02.457479 Freq=800, CH1 RK1
2017 18:01:02.457543
2018 18:01:02.461184 DATLAT Default: 0xa
2019 18:01:02.461321 0, 0xFFFF, sum = 0
2020 18:01:02.464253 1, 0xFFFF, sum = 0
2021 18:01:02.464342 2, 0xFFFF, sum = 0
2022 18:01:02.467466 3, 0xFFFF, sum = 0
2023 18:01:02.467582 4, 0xFFFF, sum = 0
2024 18:01:02.470799 5, 0xFFFF, sum = 0
2025 18:01:02.470874 6, 0xFFFF, sum = 0
2026 18:01:02.474342 7, 0xFFFF, sum = 0
2027 18:01:02.474414 8, 0xFFFF, sum = 0
2028 18:01:02.477555 9, 0x0, sum = 1
2029 18:01:02.477627 10, 0x0, sum = 2
2030 18:01:02.481383 11, 0x0, sum = 3
2031 18:01:02.481459 12, 0x0, sum = 4
2032 18:01:02.484635 best_step = 10
2033 18:01:02.484706
2034 18:01:02.484766 ==
2035 18:01:02.487521 Dram Type= 6, Freq= 0, CH_1, rank 1
2036 18:01:02.491149 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2037 18:01:02.491224 ==
2038 18:01:02.491285 RX Vref Scan: 0
2039 18:01:02.491343
2040 18:01:02.494083 RX Vref 0 -> 0, step: 1
2041 18:01:02.494200
2042 18:01:02.497942 RX Delay -95 -> 252, step: 8
2043 18:01:02.501150 iDelay=209, Bit 0, Center 84 (-31 ~ 200) 232
2044 18:01:02.507461 iDelay=209, Bit 1, Center 72 (-47 ~ 192) 240
2045 18:01:02.511310 iDelay=209, Bit 2, Center 68 (-47 ~ 184) 232
2046 18:01:02.514315 iDelay=209, Bit 3, Center 76 (-39 ~ 192) 232
2047 18:01:02.518007 iDelay=209, Bit 4, Center 80 (-39 ~ 200) 240
2048 18:01:02.520966 iDelay=209, Bit 5, Center 92 (-23 ~ 208) 232
2049 18:01:02.527784 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
2050 18:01:02.531269 iDelay=209, Bit 7, Center 76 (-39 ~ 192) 232
2051 18:01:02.534254 iDelay=209, Bit 8, Center 64 (-55 ~ 184) 240
2052 18:01:02.538006 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
2053 18:01:02.540943 iDelay=209, Bit 10, Center 76 (-39 ~ 192) 232
2054 18:01:02.547892 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
2055 18:01:02.550992 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
2056 18:01:02.554744 iDelay=209, Bit 13, Center 84 (-31 ~ 200) 232
2057 18:01:02.557981 iDelay=209, Bit 14, Center 84 (-31 ~ 200) 232
2058 18:01:02.561247 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
2059 18:01:02.564374 ==
2060 18:01:02.564457 Dram Type= 6, Freq= 0, CH_1, rank 1
2061 18:01:02.571269 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2062 18:01:02.571357 ==
2063 18:01:02.571431 DQS Delay:
2064 18:01:02.574363 DQS0 = 0, DQS1 = 0
2065 18:01:02.574441 DQM Delay:
2066 18:01:02.574503 DQM0 = 80, DQM1 = 75
2067 18:01:02.577995 DQ Delay:
2068 18:01:02.581477 DQ0 =84, DQ1 =72, DQ2 =68, DQ3 =76
2069 18:01:02.584159 DQ4 =80, DQ5 =92, DQ6 =92, DQ7 =76
2070 18:01:02.587622 DQ8 =64, DQ9 =64, DQ10 =76, DQ11 =68
2071 18:01:02.591125 DQ12 =80, DQ13 =84, DQ14 =84, DQ15 =84
2072 18:01:02.591203
2073 18:01:02.591266
2074 18:01:02.598411 [DQSOSCAuto] RK1, (LSB)MR18= 0x1d28, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 402 ps
2075 18:01:02.601306 CH1 RK1: MR19=606, MR18=1D28
2076 18:01:02.608310 CH1_RK1: MR19=0x606, MR18=0x1D28, DQSOSC=399, MR23=63, INC=92, DEC=61
2077 18:01:02.611528 [RxdqsGatingPostProcess] freq 800
2078 18:01:02.614652 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2079 18:01:02.618494 Pre-setting of DQS Precalculation
2080 18:01:02.624717 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2081 18:01:02.631625 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2082 18:01:02.637943 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2083 18:01:02.638027
2084 18:01:02.638091
2085 18:01:02.641350 [Calibration Summary] 1600 Mbps
2086 18:01:02.641432 CH 0, Rank 0
2087 18:01:02.644593 SW Impedance : PASS
2088 18:01:02.648089 DUTY Scan : NO K
2089 18:01:02.648171 ZQ Calibration : PASS
2090 18:01:02.651720 Jitter Meter : NO K
2091 18:01:02.654828 CBT Training : PASS
2092 18:01:02.654911 Write leveling : PASS
2093 18:01:02.658046 RX DQS gating : PASS
2094 18:01:02.658129 RX DQ/DQS(RDDQC) : PASS
2095 18:01:02.661916 TX DQ/DQS : PASS
2096 18:01:02.665106 RX DATLAT : PASS
2097 18:01:02.665186 RX DQ/DQS(Engine): PASS
2098 18:01:02.668347 TX OE : NO K
2099 18:01:02.668422 All Pass.
2100 18:01:02.668484
2101 18:01:02.672225 CH 0, Rank 1
2102 18:01:02.672307 SW Impedance : PASS
2103 18:01:02.675261 DUTY Scan : NO K
2104 18:01:02.678418 ZQ Calibration : PASS
2105 18:01:02.678500 Jitter Meter : NO K
2106 18:01:02.681552 CBT Training : PASS
2107 18:01:02.685374 Write leveling : PASS
2108 18:01:02.685456 RX DQS gating : PASS
2109 18:01:02.688383 RX DQ/DQS(RDDQC) : PASS
2110 18:01:02.688464 TX DQ/DQS : PASS
2111 18:01:02.691565 RX DATLAT : PASS
2112 18:01:02.695532 RX DQ/DQS(Engine): PASS
2113 18:01:02.695614 TX OE : NO K
2114 18:01:02.698904 All Pass.
2115 18:01:02.699047
2116 18:01:02.699128 CH 1, Rank 0
2117 18:01:02.701868 SW Impedance : PASS
2118 18:01:02.701949 DUTY Scan : NO K
2119 18:01:02.705290 ZQ Calibration : PASS
2120 18:01:02.708731 Jitter Meter : NO K
2121 18:01:02.708813 CBT Training : PASS
2122 18:01:02.712406 Write leveling : PASS
2123 18:01:02.715499 RX DQS gating : PASS
2124 18:01:02.715581 RX DQ/DQS(RDDQC) : PASS
2125 18:01:02.718541 TX DQ/DQS : PASS
2126 18:01:02.722143 RX DATLAT : PASS
2127 18:01:02.722225 RX DQ/DQS(Engine): PASS
2128 18:01:02.725335 TX OE : NO K
2129 18:01:02.725418 All Pass.
2130 18:01:02.725482
2131 18:01:02.728453 CH 1, Rank 1
2132 18:01:02.728536 SW Impedance : PASS
2133 18:01:02.731703 DUTY Scan : NO K
2134 18:01:02.731785 ZQ Calibration : PASS
2135 18:01:02.735453 Jitter Meter : NO K
2136 18:01:02.738520 CBT Training : PASS
2137 18:01:02.738603 Write leveling : PASS
2138 18:01:02.742166 RX DQS gating : PASS
2139 18:01:02.745478 RX DQ/DQS(RDDQC) : PASS
2140 18:01:02.745583 TX DQ/DQS : PASS
2141 18:01:02.749084 RX DATLAT : PASS
2142 18:01:02.751809 RX DQ/DQS(Engine): PASS
2143 18:01:02.751892 TX OE : NO K
2144 18:01:02.755227 All Pass.
2145 18:01:02.755309
2146 18:01:02.755374 DramC Write-DBI off
2147 18:01:02.758692 PER_BANK_REFRESH: Hybrid Mode
2148 18:01:02.758778 TX_TRACKING: ON
2149 18:01:02.762392 [GetDramInforAfterCalByMRR] Vendor 6.
2150 18:01:02.765802 [GetDramInforAfterCalByMRR] Revision 606.
2151 18:01:02.772035 [GetDramInforAfterCalByMRR] Revision 2 0.
2152 18:01:02.772118 MR0 0x3b3b
2153 18:01:02.772182 MR8 0x5151
2154 18:01:02.775552 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2155 18:01:02.775635
2156 18:01:02.778778 MR0 0x3b3b
2157 18:01:02.778859 MR8 0x5151
2158 18:01:02.782511 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2159 18:01:02.782594
2160 18:01:02.792487 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2161 18:01:02.795593 [FAST_K] Save calibration result to emmc
2162 18:01:02.799205 [FAST_K] Save calibration result to emmc
2163 18:01:02.802192 dram_init: config_dvfs: 1
2164 18:01:02.805744 dramc_set_vcore_voltage set vcore to 662500
2165 18:01:02.805827 Read voltage for 1200, 2
2166 18:01:02.809457 Vio18 = 0
2167 18:01:02.809536 Vcore = 662500
2168 18:01:02.809599 Vdram = 0
2169 18:01:02.812291 Vddq = 0
2170 18:01:02.812393 Vmddr = 0
2171 18:01:02.815861 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2172 18:01:02.822366 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2173 18:01:02.826115 MEM_TYPE=3, freq_sel=15
2174 18:01:02.829201 sv_algorithm_assistance_LP4_1600
2175 18:01:02.832433 ============ PULL DRAM RESETB DOWN ============
2176 18:01:02.836287 ========== PULL DRAM RESETB DOWN end =========
2177 18:01:02.839385 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2178 18:01:02.842547 ===================================
2179 18:01:02.846353 LPDDR4 DRAM CONFIGURATION
2180 18:01:02.849543 ===================================
2181 18:01:02.853090 EX_ROW_EN[0] = 0x0
2182 18:01:02.853168 EX_ROW_EN[1] = 0x0
2183 18:01:02.856163 LP4Y_EN = 0x0
2184 18:01:02.856241 WORK_FSP = 0x0
2185 18:01:02.859706 WL = 0x4
2186 18:01:02.859778 RL = 0x4
2187 18:01:02.862579 BL = 0x2
2188 18:01:02.862657 RPST = 0x0
2189 18:01:02.865957 RD_PRE = 0x0
2190 18:01:02.866033 WR_PRE = 0x1
2191 18:01:02.869584 WR_PST = 0x0
2192 18:01:02.869661 DBI_WR = 0x0
2193 18:01:02.872570 DBI_RD = 0x0
2194 18:01:02.872645 OTF = 0x1
2195 18:01:02.876321 ===================================
2196 18:01:02.879335 ===================================
2197 18:01:02.882644 ANA top config
2198 18:01:02.886554 ===================================
2199 18:01:02.889695 DLL_ASYNC_EN = 0
2200 18:01:02.889777 ALL_SLAVE_EN = 0
2201 18:01:02.892705 NEW_RANK_MODE = 1
2202 18:01:02.896476 DLL_IDLE_MODE = 1
2203 18:01:02.899647 LP45_APHY_COMB_EN = 1
2204 18:01:02.899729 TX_ODT_DIS = 1
2205 18:01:02.903332 NEW_8X_MODE = 1
2206 18:01:02.906269 ===================================
2207 18:01:02.909741 ===================================
2208 18:01:02.913342 data_rate = 2400
2209 18:01:02.916418 CKR = 1
2210 18:01:02.919707 DQ_P2S_RATIO = 8
2211 18:01:02.923193 ===================================
2212 18:01:02.923301 CA_P2S_RATIO = 8
2213 18:01:02.926783 DQ_CA_OPEN = 0
2214 18:01:02.929867 DQ_SEMI_OPEN = 0
2215 18:01:02.933124 CA_SEMI_OPEN = 0
2216 18:01:02.936802 CA_FULL_RATE = 0
2217 18:01:02.939997 DQ_CKDIV4_EN = 0
2218 18:01:02.940079 CA_CKDIV4_EN = 0
2219 18:01:02.943183 CA_PREDIV_EN = 0
2220 18:01:02.946359 PH8_DLY = 17
2221 18:01:02.949630 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2222 18:01:02.953472 DQ_AAMCK_DIV = 4
2223 18:01:02.956507 CA_AAMCK_DIV = 4
2224 18:01:02.956616 CA_ADMCK_DIV = 4
2225 18:01:02.960119 DQ_TRACK_CA_EN = 0
2226 18:01:02.963414 CA_PICK = 1200
2227 18:01:02.966586 CA_MCKIO = 1200
2228 18:01:02.970201 MCKIO_SEMI = 0
2229 18:01:02.973528 PLL_FREQ = 2366
2230 18:01:02.976681 DQ_UI_PI_RATIO = 32
2231 18:01:02.976796 CA_UI_PI_RATIO = 0
2232 18:01:02.980191 ===================================
2233 18:01:02.983712 ===================================
2234 18:01:02.986894 memory_type:LPDDR4
2235 18:01:02.990097 GP_NUM : 10
2236 18:01:02.990187 SRAM_EN : 1
2237 18:01:02.993350 MD32_EN : 0
2238 18:01:02.997136 ===================================
2239 18:01:03.000415 [ANA_INIT] >>>>>>>>>>>>>>
2240 18:01:03.000489 <<<<<< [CONFIGURE PHASE]: ANA_TX
2241 18:01:03.003506 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2242 18:01:03.007108 ===================================
2243 18:01:03.010411 data_rate = 2400,PCW = 0X5b00
2244 18:01:03.013571 ===================================
2245 18:01:03.017224 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2246 18:01:03.023640 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2247 18:01:03.027319 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2248 18:01:03.033918 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2249 18:01:03.037196 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2250 18:01:03.041240 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2251 18:01:03.041322 [ANA_INIT] flow start
2252 18:01:03.044328 [ANA_INIT] PLL >>>>>>>>
2253 18:01:03.047576 [ANA_INIT] PLL <<<<<<<<
2254 18:01:03.050762 [ANA_INIT] MIDPI >>>>>>>>
2255 18:01:03.050846 [ANA_INIT] MIDPI <<<<<<<<
2256 18:01:03.054031 [ANA_INIT] DLL >>>>>>>>
2257 18:01:03.057765 [ANA_INIT] DLL <<<<<<<<
2258 18:01:03.057847 [ANA_INIT] flow end
2259 18:01:03.060856 ============ LP4 DIFF to SE enter ============
2260 18:01:03.067606 ============ LP4 DIFF to SE exit ============
2261 18:01:03.067715 [ANA_INIT] <<<<<<<<<<<<<
2262 18:01:03.070805 [Flow] Enable top DCM control >>>>>
2263 18:01:03.074618 [Flow] Enable top DCM control <<<<<
2264 18:01:03.077773 Enable DLL master slave shuffle
2265 18:01:03.084229 ==============================================================
2266 18:01:03.084340 Gating Mode config
2267 18:01:03.091128 ==============================================================
2268 18:01:03.097452 Config description:
2269 18:01:03.101166 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2270 18:01:03.108190 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2271 18:01:03.114367 SELPH_MODE 0: By rank 1: By Phase
2272 18:01:03.118063 ==============================================================
2273 18:01:03.121135 GAT_TRACK_EN = 1
2274 18:01:03.124773 RX_GATING_MODE = 2
2275 18:01:03.127645 RX_GATING_TRACK_MODE = 2
2276 18:01:03.131233 SELPH_MODE = 1
2277 18:01:03.134538 PICG_EARLY_EN = 1
2278 18:01:03.138012 VALID_LAT_VALUE = 1
2279 18:01:03.144508 ==============================================================
2280 18:01:03.148069 Enter into Gating configuration >>>>
2281 18:01:03.151238 Exit from Gating configuration <<<<
2282 18:01:03.151321 Enter into DVFS_PRE_config >>>>>
2283 18:01:03.165082 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2284 18:01:03.168151 Exit from DVFS_PRE_config <<<<<
2285 18:01:03.171330 Enter into PICG configuration >>>>
2286 18:01:03.174514 Exit from PICG configuration <<<<
2287 18:01:03.174593 [RX_INPUT] configuration >>>>>
2288 18:01:03.178326 [RX_INPUT] configuration <<<<<
2289 18:01:03.184725 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2290 18:01:03.188252 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2291 18:01:03.194857 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2292 18:01:03.201809 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2293 18:01:03.208502 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2294 18:01:03.215433 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2295 18:01:03.218431 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2296 18:01:03.221742 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2297 18:01:03.224964 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2298 18:01:03.232071 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2299 18:01:03.235175 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2300 18:01:03.238800 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2301 18:01:03.241861 ===================================
2302 18:01:03.245374 LPDDR4 DRAM CONFIGURATION
2303 18:01:03.248286 ===================================
2304 18:01:03.248370 EX_ROW_EN[0] = 0x0
2305 18:01:03.251671 EX_ROW_EN[1] = 0x0
2306 18:01:03.255181 LP4Y_EN = 0x0
2307 18:01:03.255263 WORK_FSP = 0x0
2308 18:01:03.258794 WL = 0x4
2309 18:01:03.258878 RL = 0x4
2310 18:01:03.261966 BL = 0x2
2311 18:01:03.262048 RPST = 0x0
2312 18:01:03.265229 RD_PRE = 0x0
2313 18:01:03.265311 WR_PRE = 0x1
2314 18:01:03.268689 WR_PST = 0x0
2315 18:01:03.268771 DBI_WR = 0x0
2316 18:01:03.271699 DBI_RD = 0x0
2317 18:01:03.271782 OTF = 0x1
2318 18:01:03.275477 ===================================
2319 18:01:03.278622 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2320 18:01:03.285480 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2321 18:01:03.288611 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2322 18:01:03.292298 ===================================
2323 18:01:03.295369 LPDDR4 DRAM CONFIGURATION
2324 18:01:03.298836 ===================================
2325 18:01:03.298918 EX_ROW_EN[0] = 0x10
2326 18:01:03.301867 EX_ROW_EN[1] = 0x0
2327 18:01:03.301950 LP4Y_EN = 0x0
2328 18:01:03.305459 WORK_FSP = 0x0
2329 18:01:03.305539 WL = 0x4
2330 18:01:03.308983 RL = 0x4
2331 18:01:03.309091 BL = 0x2
2332 18:01:03.312099 RPST = 0x0
2333 18:01:03.312182 RD_PRE = 0x0
2334 18:01:03.315341 WR_PRE = 0x1
2335 18:01:03.315442 WR_PST = 0x0
2336 18:01:03.319023 DBI_WR = 0x0
2337 18:01:03.319102 DBI_RD = 0x0
2338 18:01:03.322189 OTF = 0x1
2339 18:01:03.325252 ===================================
2340 18:01:03.332251 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2341 18:01:03.332339 ==
2342 18:01:03.335337 Dram Type= 6, Freq= 0, CH_0, rank 0
2343 18:01:03.339266 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2344 18:01:03.339350 ==
2345 18:01:03.342323 [Duty_Offset_Calibration]
2346 18:01:03.342426 B0:2 B1:-1 CA:1
2347 18:01:03.342516
2348 18:01:03.345590 [DutyScan_Calibration_Flow] k_type=0
2349 18:01:03.355226
2350 18:01:03.355329 ==CLK 0==
2351 18:01:03.358917 Final CLK duty delay cell = -4
2352 18:01:03.362475 [-4] MAX Duty = 5031%(X100), DQS PI = 4
2353 18:01:03.365483 [-4] MIN Duty = 4875%(X100), DQS PI = 30
2354 18:01:03.369144 [-4] AVG Duty = 4953%(X100)
2355 18:01:03.369218
2356 18:01:03.372116 CH0 CLK Duty spec in!! Max-Min= 156%
2357 18:01:03.375732 [DutyScan_Calibration_Flow] ====Done====
2358 18:01:03.375831
2359 18:01:03.378847 [DutyScan_Calibration_Flow] k_type=1
2360 18:01:03.394220
2361 18:01:03.394302 ==DQS 0 ==
2362 18:01:03.397867 Final DQS duty delay cell = 0
2363 18:01:03.401088 [0] MAX Duty = 5125%(X100), DQS PI = 46
2364 18:01:03.404061 [0] MIN Duty = 5000%(X100), DQS PI = 14
2365 18:01:03.404143 [0] AVG Duty = 5062%(X100)
2366 18:01:03.407510
2367 18:01:03.407582 ==DQS 1 ==
2368 18:01:03.411160 Final DQS duty delay cell = -4
2369 18:01:03.414297 [-4] MAX Duty = 5093%(X100), DQS PI = 6
2370 18:01:03.417847 [-4] MIN Duty = 5000%(X100), DQS PI = 44
2371 18:01:03.417923 [-4] AVG Duty = 5046%(X100)
2372 18:01:03.420937
2373 18:01:03.424688 CH0 DQS 0 Duty spec in!! Max-Min= 125%
2374 18:01:03.424787
2375 18:01:03.428015 CH0 DQS 1 Duty spec in!! Max-Min= 93%
2376 18:01:03.431055 [DutyScan_Calibration_Flow] ====Done====
2377 18:01:03.431166
2378 18:01:03.434264 [DutyScan_Calibration_Flow] k_type=3
2379 18:01:03.451046
2380 18:01:03.451128 ==DQM 0 ==
2381 18:01:03.454590 Final DQM duty delay cell = 0
2382 18:01:03.457766 [0] MAX Duty = 5000%(X100), DQS PI = 56
2383 18:01:03.461387 [0] MIN Duty = 4907%(X100), DQS PI = 2
2384 18:01:03.461464 [0] AVG Duty = 4953%(X100)
2385 18:01:03.464579
2386 18:01:03.464684 ==DQM 1 ==
2387 18:01:03.467586 Final DQM duty delay cell = 0
2388 18:01:03.471059 [0] MAX Duty = 5156%(X100), DQS PI = 62
2389 18:01:03.474414 [0] MIN Duty = 4969%(X100), DQS PI = 10
2390 18:01:03.474492 [0] AVG Duty = 5062%(X100)
2391 18:01:03.477444
2392 18:01:03.481263 CH0 DQM 0 Duty spec in!! Max-Min= 93%
2393 18:01:03.481339
2394 18:01:03.484417 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2395 18:01:03.487555 [DutyScan_Calibration_Flow] ====Done====
2396 18:01:03.487654
2397 18:01:03.491124 [DutyScan_Calibration_Flow] k_type=2
2398 18:01:03.506774
2399 18:01:03.506879 ==DQ 0 ==
2400 18:01:03.509799 Final DQ duty delay cell = -4
2401 18:01:03.513275 [-4] MAX Duty = 5062%(X100), DQS PI = 54
2402 18:01:03.516440 [-4] MIN Duty = 4844%(X100), DQS PI = 18
2403 18:01:03.520081 [-4] AVG Duty = 4953%(X100)
2404 18:01:03.520163
2405 18:01:03.520228 ==DQ 1 ==
2406 18:01:03.523752 Final DQ duty delay cell = 0
2407 18:01:03.526781 [0] MAX Duty = 5031%(X100), DQS PI = 26
2408 18:01:03.529936 [0] MIN Duty = 4907%(X100), DQS PI = 46
2409 18:01:03.530023 [0] AVG Duty = 4969%(X100)
2410 18:01:03.533642
2411 18:01:03.536851 CH0 DQ 0 Duty spec in!! Max-Min= 218%
2412 18:01:03.536951
2413 18:01:03.540528 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2414 18:01:03.543703 [DutyScan_Calibration_Flow] ====Done====
2415 18:01:03.543786 ==
2416 18:01:03.546827 Dram Type= 6, Freq= 0, CH_1, rank 0
2417 18:01:03.550530 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2418 18:01:03.550632 ==
2419 18:01:03.553751 [Duty_Offset_Calibration]
2420 18:01:03.553833 B0:1 B1:1 CA:2
2421 18:01:03.553898
2422 18:01:03.557001 [DutyScan_Calibration_Flow] k_type=0
2423 18:01:03.567239
2424 18:01:03.567324 ==CLK 0==
2425 18:01:03.570339 Final CLK duty delay cell = 0
2426 18:01:03.573421 [0] MAX Duty = 5156%(X100), DQS PI = 24
2427 18:01:03.576920 [0] MIN Duty = 4938%(X100), DQS PI = 40
2428 18:01:03.577028 [0] AVG Duty = 5047%(X100)
2429 18:01:03.580336
2430 18:01:03.580463 CH1 CLK Duty spec in!! Max-Min= 218%
2431 18:01:03.587139 [DutyScan_Calibration_Flow] ====Done====
2432 18:01:03.587238
2433 18:01:03.590205 [DutyScan_Calibration_Flow] k_type=1
2434 18:01:03.606035
2435 18:01:03.606129 ==DQS 0 ==
2436 18:01:03.609654 Final DQS duty delay cell = 0
2437 18:01:03.612940 [0] MAX Duty = 5031%(X100), DQS PI = 18
2438 18:01:03.616085 [0] MIN Duty = 4813%(X100), DQS PI = 50
2439 18:01:03.619525 [0] AVG Duty = 4922%(X100)
2440 18:01:03.619632
2441 18:01:03.619695 ==DQS 1 ==
2442 18:01:03.623029 Final DQS duty delay cell = 0
2443 18:01:03.626531 [0] MAX Duty = 5062%(X100), DQS PI = 36
2444 18:01:03.629444 [0] MIN Duty = 4907%(X100), DQS PI = 14
2445 18:01:03.629571 [0] AVG Duty = 4984%(X100)
2446 18:01:03.633172
2447 18:01:03.636281 CH1 DQS 0 Duty spec in!! Max-Min= 218%
2448 18:01:03.636365
2449 18:01:03.639381 CH1 DQS 1 Duty spec in!! Max-Min= 155%
2450 18:01:03.643250 [DutyScan_Calibration_Flow] ====Done====
2451 18:01:03.643342
2452 18:01:03.646326 [DutyScan_Calibration_Flow] k_type=3
2453 18:01:03.662753
2454 18:01:03.662855 ==DQM 0 ==
2455 18:01:03.666190 Final DQM duty delay cell = 0
2456 18:01:03.669624 [0] MAX Duty = 5093%(X100), DQS PI = 16
2457 18:01:03.672773 [0] MIN Duty = 4875%(X100), DQS PI = 48
2458 18:01:03.672878 [0] AVG Duty = 4984%(X100)
2459 18:01:03.675883
2460 18:01:03.675959 ==DQM 1 ==
2461 18:01:03.679606 Final DQM duty delay cell = 0
2462 18:01:03.682722 [0] MAX Duty = 5125%(X100), DQS PI = 0
2463 18:01:03.686472 [0] MIN Duty = 4938%(X100), DQS PI = 24
2464 18:01:03.686584 [0] AVG Duty = 5031%(X100)
2465 18:01:03.686676
2466 18:01:03.692706 CH1 DQM 0 Duty spec in!! Max-Min= 218%
2467 18:01:03.692812
2468 18:01:03.696059 CH1 DQM 1 Duty spec in!! Max-Min= 187%
2469 18:01:03.699642 [DutyScan_Calibration_Flow] ====Done====
2470 18:01:03.699753
2471 18:01:03.702925 [DutyScan_Calibration_Flow] k_type=2
2472 18:01:03.719063
2473 18:01:03.719173 ==DQ 0 ==
2474 18:01:03.722688 Final DQ duty delay cell = 0
2475 18:01:03.726168 [0] MAX Duty = 5093%(X100), DQS PI = 18
2476 18:01:03.729158 [0] MIN Duty = 4907%(X100), DQS PI = 50
2477 18:01:03.729266 [0] AVG Duty = 5000%(X100)
2478 18:01:03.729371
2479 18:01:03.732783 ==DQ 1 ==
2480 18:01:03.736199 Final DQ duty delay cell = 0
2481 18:01:03.739224 [0] MAX Duty = 5093%(X100), DQS PI = 10
2482 18:01:03.742769 [0] MIN Duty = 5000%(X100), DQS PI = 2
2483 18:01:03.742848 [0] AVG Duty = 5046%(X100)
2484 18:01:03.742931
2485 18:01:03.745876 CH1 DQ 0 Duty spec in!! Max-Min= 186%
2486 18:01:03.745955
2487 18:01:03.749487 CH1 DQ 1 Duty spec in!! Max-Min= 93%
2488 18:01:03.756338 [DutyScan_Calibration_Flow] ====Done====
2489 18:01:03.759443 nWR fixed to 30
2490 18:01:03.759548 [ModeRegInit_LP4] CH0 RK0
2491 18:01:03.762545 [ModeRegInit_LP4] CH0 RK1
2492 18:01:03.766280 [ModeRegInit_LP4] CH1 RK0
2493 18:01:03.766359 [ModeRegInit_LP4] CH1 RK1
2494 18:01:03.769432 match AC timing 7
2495 18:01:03.772458 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2496 18:01:03.775994 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2497 18:01:03.782996 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2498 18:01:03.786063 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2499 18:01:03.792927 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2500 18:01:03.793029 ==
2501 18:01:03.795885 Dram Type= 6, Freq= 0, CH_0, rank 0
2502 18:01:03.799529 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2503 18:01:03.799632 ==
2504 18:01:03.806239 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2505 18:01:03.809627 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2506 18:01:03.818891 [CA 0] Center 40 (10~71) winsize 62
2507 18:01:03.822350 [CA 1] Center 39 (9~70) winsize 62
2508 18:01:03.826049 [CA 2] Center 36 (6~67) winsize 62
2509 18:01:03.829050 [CA 3] Center 36 (5~67) winsize 63
2510 18:01:03.832514 [CA 4] Center 35 (5~65) winsize 61
2511 18:01:03.836139 [CA 5] Center 34 (4~64) winsize 61
2512 18:01:03.836241
2513 18:01:03.839165 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2514 18:01:03.839240
2515 18:01:03.842680 [CATrainingPosCal] consider 1 rank data
2516 18:01:03.846141 u2DelayCellTimex100 = 270/100 ps
2517 18:01:03.849582 CA0 delay=40 (10~71),Diff = 6 PI (28 cell)
2518 18:01:03.852746 CA1 delay=39 (9~70),Diff = 5 PI (24 cell)
2519 18:01:03.859540 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2520 18:01:03.862790 CA3 delay=36 (5~67),Diff = 2 PI (9 cell)
2521 18:01:03.865819 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
2522 18:01:03.869605 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2523 18:01:03.869707
2524 18:01:03.872762 CA PerBit enable=1, Macro0, CA PI delay=34
2525 18:01:03.872861
2526 18:01:03.875939 [CBTSetCACLKResult] CA Dly = 34
2527 18:01:03.876031 CS Dly: 7 (0~38)
2528 18:01:03.876109 ==
2529 18:01:03.879545 Dram Type= 6, Freq= 0, CH_0, rank 1
2530 18:01:03.886099 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2531 18:01:03.886205 ==
2532 18:01:03.889322 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2533 18:01:03.896239 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2534 18:01:03.905370 [CA 0] Center 39 (9~70) winsize 62
2535 18:01:03.908488 [CA 1] Center 40 (10~70) winsize 61
2536 18:01:03.911925 [CA 2] Center 36 (6~67) winsize 62
2537 18:01:03.914981 [CA 3] Center 36 (5~67) winsize 63
2538 18:01:03.918572 [CA 4] Center 34 (4~65) winsize 62
2539 18:01:03.921752 [CA 5] Center 34 (4~64) winsize 61
2540 18:01:03.921854
2541 18:01:03.925323 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2542 18:01:03.925426
2543 18:01:03.928759 [CATrainingPosCal] consider 2 rank data
2544 18:01:03.932080 u2DelayCellTimex100 = 270/100 ps
2545 18:01:03.935631 CA0 delay=40 (10~70),Diff = 6 PI (28 cell)
2546 18:01:03.941796 CA1 delay=40 (10~70),Diff = 6 PI (28 cell)
2547 18:01:03.945551 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2548 18:01:03.948724 CA3 delay=36 (5~67),Diff = 2 PI (9 cell)
2549 18:01:03.951815 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
2550 18:01:03.955286 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2551 18:01:03.955363
2552 18:01:03.958832 CA PerBit enable=1, Macro0, CA PI delay=34
2553 18:01:03.958935
2554 18:01:03.962316 [CBTSetCACLKResult] CA Dly = 34
2555 18:01:03.962394 CS Dly: 8 (0~41)
2556 18:01:03.962458
2557 18:01:03.965314 ----->DramcWriteLeveling(PI) begin...
2558 18:01:03.968600 ==
2559 18:01:03.968707 Dram Type= 6, Freq= 0, CH_0, rank 0
2560 18:01:03.975226 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2561 18:01:03.975331 ==
2562 18:01:03.978925 Write leveling (Byte 0): 31 => 31
2563 18:01:03.981984 Write leveling (Byte 1): 30 => 30
2564 18:01:03.982090 DramcWriteLeveling(PI) end<-----
2565 18:01:03.985519
2566 18:01:03.985618 ==
2567 18:01:03.989118 Dram Type= 6, Freq= 0, CH_0, rank 0
2568 18:01:03.992227 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2569 18:01:03.992326 ==
2570 18:01:03.995227 [Gating] SW mode calibration
2571 18:01:04.002029 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2572 18:01:04.005787 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2573 18:01:04.012021 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2574 18:01:04.015634 0 15 4 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (1 1)
2575 18:01:04.018504 0 15 8 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
2576 18:01:04.025246 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2577 18:01:04.029160 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2578 18:01:04.032362 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2579 18:01:04.039077 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2580 18:01:04.042500 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2581 18:01:04.045874 1 0 0 | B1->B0 | 3434 3131 | 0 0 | (0 1) (0 1)
2582 18:01:04.052388 1 0 4 | B1->B0 | 2d2d 2323 | 0 0 | (0 1) (0 0)
2583 18:01:04.055622 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2584 18:01:04.058811 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2585 18:01:04.065905 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2586 18:01:04.068835 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2587 18:01:04.072383 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2588 18:01:04.075637 1 0 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2589 18:01:04.082375 1 1 0 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
2590 18:01:04.085457 1 1 4 | B1->B0 | 3d3d 4545 | 1 0 | (0 0) (0 0)
2591 18:01:04.089152 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2592 18:01:04.095582 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2593 18:01:04.099511 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2594 18:01:04.102526 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2595 18:01:04.109427 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2596 18:01:04.112674 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2597 18:01:04.115775 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2598 18:01:04.122620 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2599 18:01:04.126039 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2600 18:01:04.129110 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2601 18:01:04.132858 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2602 18:01:04.139229 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2603 18:01:04.142923 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2604 18:01:04.145968 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2605 18:01:04.152708 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2606 18:01:04.156272 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2607 18:01:04.159535 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2608 18:01:04.166357 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2609 18:01:04.169310 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2610 18:01:04.172896 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2611 18:01:04.179474 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2612 18:01:04.183046 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2613 18:01:04.186134 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2614 18:01:04.193209 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2615 18:01:04.193303 Total UI for P1: 0, mck2ui 16
2616 18:01:04.196223 best dqsien dly found for B0: ( 1, 4, 0)
2617 18:01:04.202836 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2618 18:01:04.206048 Total UI for P1: 0, mck2ui 16
2619 18:01:04.209887 best dqsien dly found for B1: ( 1, 4, 2)
2620 18:01:04.213061 best DQS0 dly(MCK, UI, PI) = (1, 4, 0)
2621 18:01:04.216295 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2622 18:01:04.216402
2623 18:01:04.219338 best DQS0 P1 dly(MCK, UI, PI) = (1, 8, 0)
2624 18:01:04.223175 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2625 18:01:04.226328 [Gating] SW calibration Done
2626 18:01:04.226430 ==
2627 18:01:04.229947 Dram Type= 6, Freq= 0, CH_0, rank 0
2628 18:01:04.232956 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2629 18:01:04.233082 ==
2630 18:01:04.236125 RX Vref Scan: 0
2631 18:01:04.236214
2632 18:01:04.236279 RX Vref 0 -> 0, step: 1
2633 18:01:04.236340
2634 18:01:04.239874 RX Delay -40 -> 252, step: 8
2635 18:01:04.242988 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2636 18:01:04.249722 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2637 18:01:04.253433 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2638 18:01:04.256722 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2639 18:01:04.259931 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2640 18:01:04.263024 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2641 18:01:04.269580 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2642 18:01:04.272875 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2643 18:01:04.276669 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2644 18:01:04.279924 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2645 18:01:04.283144 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2646 18:01:04.286376 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2647 18:01:04.293204 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2648 18:01:04.296563 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2649 18:01:04.300138 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2650 18:01:04.303158 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2651 18:01:04.303258 ==
2652 18:01:04.306520 Dram Type= 6, Freq= 0, CH_0, rank 0
2653 18:01:04.313442 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2654 18:01:04.313521 ==
2655 18:01:04.313615 DQS Delay:
2656 18:01:04.313709 DQS0 = 0, DQS1 = 0
2657 18:01:04.316627 DQM Delay:
2658 18:01:04.316726 DQM0 = 115, DQM1 = 107
2659 18:01:04.320483 DQ Delay:
2660 18:01:04.323624 DQ0 =115, DQ1 =115, DQ2 =111, DQ3 =111
2661 18:01:04.326804 DQ4 =115, DQ5 =111, DQ6 =123, DQ7 =123
2662 18:01:04.329904 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =103
2663 18:01:04.333412 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =115
2664 18:01:04.333514
2665 18:01:04.333619
2666 18:01:04.333710 ==
2667 18:01:04.336473 Dram Type= 6, Freq= 0, CH_0, rank 0
2668 18:01:04.340017 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2669 18:01:04.340106 ==
2670 18:01:04.343807
2671 18:01:04.343908
2672 18:01:04.344009 TX Vref Scan disable
2673 18:01:04.347014 == TX Byte 0 ==
2674 18:01:04.350204 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2675 18:01:04.353795 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2676 18:01:04.356812 == TX Byte 1 ==
2677 18:01:04.359998 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2678 18:01:04.363705 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2679 18:01:04.363813 ==
2680 18:01:04.366869 Dram Type= 6, Freq= 0, CH_0, rank 0
2681 18:01:04.373590 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2682 18:01:04.373696 ==
2683 18:01:04.383906 TX Vref=22, minBit 1, minWin=25, winSum=419
2684 18:01:04.387526 TX Vref=24, minBit 1, minWin=25, winSum=424
2685 18:01:04.390492 TX Vref=26, minBit 12, minWin=25, winSum=427
2686 18:01:04.393920 TX Vref=28, minBit 4, minWin=26, winSum=434
2687 18:01:04.397105 TX Vref=30, minBit 7, minWin=26, winSum=435
2688 18:01:04.400555 TX Vref=32, minBit 4, minWin=26, winSum=434
2689 18:01:04.407394 [TxChooseVref] Worse bit 7, Min win 26, Win sum 435, Final Vref 30
2690 18:01:04.407507
2691 18:01:04.410719 Final TX Range 1 Vref 30
2692 18:01:04.410795
2693 18:01:04.410862 ==
2694 18:01:04.413749 Dram Type= 6, Freq= 0, CH_0, rank 0
2695 18:01:04.417631 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2696 18:01:04.417727 ==
2697 18:01:04.417799
2698 18:01:04.420441
2699 18:01:04.420536 TX Vref Scan disable
2700 18:01:04.424218 == TX Byte 0 ==
2701 18:01:04.427276 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2702 18:01:04.431066 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2703 18:01:04.434119 == TX Byte 1 ==
2704 18:01:04.437212 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2705 18:01:04.440775 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2706 18:01:04.440874
2707 18:01:04.444329 [DATLAT]
2708 18:01:04.444401 Freq=1200, CH0 RK0
2709 18:01:04.444463
2710 18:01:04.447454 DATLAT Default: 0xd
2711 18:01:04.447560 0, 0xFFFF, sum = 0
2712 18:01:04.451310 1, 0xFFFF, sum = 0
2713 18:01:04.451391 2, 0xFFFF, sum = 0
2714 18:01:04.454344 3, 0xFFFF, sum = 0
2715 18:01:04.454449 4, 0xFFFF, sum = 0
2716 18:01:04.457404 5, 0xFFFF, sum = 0
2717 18:01:04.457507 6, 0xFFFF, sum = 0
2718 18:01:04.461309 7, 0xFFFF, sum = 0
2719 18:01:04.461415 8, 0xFFFF, sum = 0
2720 18:01:04.464414 9, 0xFFFF, sum = 0
2721 18:01:04.464523 10, 0xFFFF, sum = 0
2722 18:01:04.467542 11, 0xFFFF, sum = 0
2723 18:01:04.467648 12, 0x0, sum = 1
2724 18:01:04.471352 13, 0x0, sum = 2
2725 18:01:04.471472 14, 0x0, sum = 3
2726 18:01:04.474615 15, 0x0, sum = 4
2727 18:01:04.474735 best_step = 13
2728 18:01:04.474832
2729 18:01:04.474920 ==
2730 18:01:04.477717 Dram Type= 6, Freq= 0, CH_0, rank 0
2731 18:01:04.484323 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2732 18:01:04.484426 ==
2733 18:01:04.484519 RX Vref Scan: 1
2734 18:01:04.484648
2735 18:01:04.487986 Set Vref Range= 32 -> 127
2736 18:01:04.488091
2737 18:01:04.491041 RX Vref 32 -> 127, step: 1
2738 18:01:04.491144
2739 18:01:04.491234 RX Delay -21 -> 252, step: 4
2740 18:01:04.494280
2741 18:01:04.494384 Set Vref, RX VrefLevel [Byte0]: 32
2742 18:01:04.497938 [Byte1]: 32
2743 18:01:04.502076
2744 18:01:04.502182 Set Vref, RX VrefLevel [Byte0]: 33
2745 18:01:04.505552 [Byte1]: 33
2746 18:01:04.510066
2747 18:01:04.510172 Set Vref, RX VrefLevel [Byte0]: 34
2748 18:01:04.513663 [Byte1]: 34
2749 18:01:04.517917
2750 18:01:04.518018 Set Vref, RX VrefLevel [Byte0]: 35
2751 18:01:04.521400 [Byte1]: 35
2752 18:01:04.525946
2753 18:01:04.526045 Set Vref, RX VrefLevel [Byte0]: 36
2754 18:01:04.529415 [Byte1]: 36
2755 18:01:04.533936
2756 18:01:04.534041 Set Vref, RX VrefLevel [Byte0]: 37
2757 18:01:04.537219 [Byte1]: 37
2758 18:01:04.542135
2759 18:01:04.542222 Set Vref, RX VrefLevel [Byte0]: 38
2760 18:01:04.545212 [Byte1]: 38
2761 18:01:04.549896
2762 18:01:04.549997 Set Vref, RX VrefLevel [Byte0]: 39
2763 18:01:04.553014 [Byte1]: 39
2764 18:01:04.558144
2765 18:01:04.558251 Set Vref, RX VrefLevel [Byte0]: 40
2766 18:01:04.561214 [Byte1]: 40
2767 18:01:04.565450
2768 18:01:04.565558 Set Vref, RX VrefLevel [Byte0]: 41
2769 18:01:04.569289 [Byte1]: 41
2770 18:01:04.573649
2771 18:01:04.573747 Set Vref, RX VrefLevel [Byte0]: 42
2772 18:01:04.576870 [Byte1]: 42
2773 18:01:04.581889
2774 18:01:04.581995 Set Vref, RX VrefLevel [Byte0]: 43
2775 18:01:04.584904 [Byte1]: 43
2776 18:01:04.589243
2777 18:01:04.589314 Set Vref, RX VrefLevel [Byte0]: 44
2778 18:01:04.592836 [Byte1]: 44
2779 18:01:04.597271
2780 18:01:04.597341 Set Vref, RX VrefLevel [Byte0]: 45
2781 18:01:04.600898 [Byte1]: 45
2782 18:01:04.605312
2783 18:01:04.605408 Set Vref, RX VrefLevel [Byte0]: 46
2784 18:01:04.608403 [Byte1]: 46
2785 18:01:04.613098
2786 18:01:04.613198 Set Vref, RX VrefLevel [Byte0]: 47
2787 18:01:04.616558 [Byte1]: 47
2788 18:01:04.620850
2789 18:01:04.620964 Set Vref, RX VrefLevel [Byte0]: 48
2790 18:01:04.624662 [Byte1]: 48
2791 18:01:04.628917
2792 18:01:04.629058 Set Vref, RX VrefLevel [Byte0]: 49
2793 18:01:04.632616 [Byte1]: 49
2794 18:01:04.637024
2795 18:01:04.637120 Set Vref, RX VrefLevel [Byte0]: 50
2796 18:01:04.640579 [Byte1]: 50
2797 18:01:04.644875
2798 18:01:04.645009 Set Vref, RX VrefLevel [Byte0]: 51
2799 18:01:04.648036 [Byte1]: 51
2800 18:01:04.652680
2801 18:01:04.652793 Set Vref, RX VrefLevel [Byte0]: 52
2802 18:01:04.656347 [Byte1]: 52
2803 18:01:04.660552
2804 18:01:04.660659 Set Vref, RX VrefLevel [Byte0]: 53
2805 18:01:04.664199 [Byte1]: 53
2806 18:01:04.668820
2807 18:01:04.668937 Set Vref, RX VrefLevel [Byte0]: 54
2808 18:01:04.672075 [Byte1]: 54
2809 18:01:04.676412
2810 18:01:04.676519 Set Vref, RX VrefLevel [Byte0]: 55
2811 18:01:04.680177 [Byte1]: 55
2812 18:01:04.684488
2813 18:01:04.684587 Set Vref, RX VrefLevel [Byte0]: 56
2814 18:01:04.688233 [Byte1]: 56
2815 18:01:04.692441
2816 18:01:04.692546 Set Vref, RX VrefLevel [Byte0]: 57
2817 18:01:04.695514 [Byte1]: 57
2818 18:01:04.700492
2819 18:01:04.700605 Set Vref, RX VrefLevel [Byte0]: 58
2820 18:01:04.703546 [Byte1]: 58
2821 18:01:04.708616
2822 18:01:04.708756 Set Vref, RX VrefLevel [Byte0]: 59
2823 18:01:04.711874 [Byte1]: 59
2824 18:01:04.716363
2825 18:01:04.716483 Set Vref, RX VrefLevel [Byte0]: 60
2826 18:01:04.719536 [Byte1]: 60
2827 18:01:04.724387
2828 18:01:04.724489 Set Vref, RX VrefLevel [Byte0]: 61
2829 18:01:04.727772 [Byte1]: 61
2830 18:01:04.732327
2831 18:01:04.732442 Set Vref, RX VrefLevel [Byte0]: 62
2832 18:01:04.735486 [Byte1]: 62
2833 18:01:04.739816
2834 18:01:04.739917 Set Vref, RX VrefLevel [Byte0]: 63
2835 18:01:04.743477 [Byte1]: 63
2836 18:01:04.747821
2837 18:01:04.747916 Set Vref, RX VrefLevel [Byte0]: 64
2838 18:01:04.751612 [Byte1]: 64
2839 18:01:04.755798
2840 18:01:04.755904 Set Vref, RX VrefLevel [Byte0]: 65
2841 18:01:04.758862 [Byte1]: 65
2842 18:01:04.763931
2843 18:01:04.764024 Set Vref, RX VrefLevel [Byte0]: 66
2844 18:01:04.767493 [Byte1]: 66
2845 18:01:04.771926
2846 18:01:04.772024 Set Vref, RX VrefLevel [Byte0]: 67
2847 18:01:04.775168 [Byte1]: 67
2848 18:01:04.779550
2849 18:01:04.779649 Set Vref, RX VrefLevel [Byte0]: 68
2850 18:01:04.783118 [Byte1]: 68
2851 18:01:04.787644
2852 18:01:04.787784 Set Vref, RX VrefLevel [Byte0]: 69
2853 18:01:04.790762 [Byte1]: 69
2854 18:01:04.795582
2855 18:01:04.795655 Final RX Vref Byte 0 = 52 to rank0
2856 18:01:04.798549 Final RX Vref Byte 1 = 52 to rank0
2857 18:01:04.802072 Final RX Vref Byte 0 = 52 to rank1
2858 18:01:04.805248 Final RX Vref Byte 1 = 52 to rank1==
2859 18:01:04.809214 Dram Type= 6, Freq= 0, CH_0, rank 0
2860 18:01:04.812330 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2861 18:01:04.815430 ==
2862 18:01:04.815505 DQS Delay:
2863 18:01:04.815570 DQS0 = 0, DQS1 = 0
2864 18:01:04.819105 DQM Delay:
2865 18:01:04.819193 DQM0 = 114, DQM1 = 104
2866 18:01:04.822243 DQ Delay:
2867 18:01:04.825426 DQ0 =112, DQ1 =114, DQ2 =112, DQ3 =114
2868 18:01:04.829196 DQ4 =116, DQ5 =108, DQ6 =122, DQ7 =120
2869 18:01:04.832223 DQ8 =92, DQ9 =90, DQ10 =106, DQ11 =96
2870 18:01:04.835781 DQ12 =112, DQ13 =110, DQ14 =118, DQ15 =114
2871 18:01:04.835880
2872 18:01:04.835972
2873 18:01:04.842898 [DQSOSCAuto] RK0, (LSB)MR18= 0xfaea, (MSB)MR19= 0x303, tDQSOscB0 = 419 ps tDQSOscB1 = 412 ps
2874 18:01:04.846051 CH0 RK0: MR19=303, MR18=FAEA
2875 18:01:04.852373 CH0_RK0: MR19=0x303, MR18=0xFAEA, DQSOSC=412, MR23=63, INC=38, DEC=25
2876 18:01:04.852476
2877 18:01:04.856041 ----->DramcWriteLeveling(PI) begin...
2878 18:01:04.856143 ==
2879 18:01:04.859182 Dram Type= 6, Freq= 0, CH_0, rank 1
2880 18:01:04.862782 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2881 18:01:04.862866 ==
2882 18:01:04.865901 Write leveling (Byte 0): 32 => 32
2883 18:01:04.869397 Write leveling (Byte 1): 29 => 29
2884 18:01:04.872605 DramcWriteLeveling(PI) end<-----
2885 18:01:04.872728
2886 18:01:04.872792 ==
2887 18:01:04.875733 Dram Type= 6, Freq= 0, CH_0, rank 1
2888 18:01:04.879292 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2889 18:01:04.879394 ==
2890 18:01:04.882792 [Gating] SW mode calibration
2891 18:01:04.889265 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2892 18:01:04.895612 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2893 18:01:04.899146 0 15 0 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
2894 18:01:04.905734 0 15 4 | B1->B0 | 2b2b 3434 | 0 1 | (0 0) (1 1)
2895 18:01:04.909093 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2896 18:01:04.912678 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2897 18:01:04.919696 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2898 18:01:04.922803 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2899 18:01:04.926013 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2900 18:01:04.929625 0 15 28 | B1->B0 | 3434 2828 | 1 1 | (1 1) (1 0)
2901 18:01:04.936260 1 0 0 | B1->B0 | 2a2a 2323 | 1 0 | (1 1) (0 0)
2902 18:01:04.939353 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2903 18:01:04.943043 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2904 18:01:04.949869 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2905 18:01:04.953064 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2906 18:01:04.956113 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2907 18:01:04.962907 1 0 24 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
2908 18:01:04.966108 1 0 28 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
2909 18:01:04.969772 1 1 0 | B1->B0 | 2626 3b3b | 0 1 | (0 0) (0 0)
2910 18:01:04.976133 1 1 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
2911 18:01:04.979974 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2912 18:01:04.983062 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2913 18:01:04.989411 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2914 18:01:04.992911 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2915 18:01:04.996692 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2916 18:01:04.999702 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2917 18:01:05.006771 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2918 18:01:05.009728 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2919 18:01:05.013103 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2920 18:01:05.019775 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2921 18:01:05.022848 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2922 18:01:05.026651 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2923 18:01:05.033508 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2924 18:01:05.036655 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2925 18:01:05.039640 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2926 18:01:05.046647 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2927 18:01:05.050326 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2928 18:01:05.053271 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2929 18:01:05.056782 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2930 18:01:05.063707 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2931 18:01:05.066728 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2932 18:01:05.070051 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2933 18:01:05.076911 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2934 18:01:05.079895 Total UI for P1: 0, mck2ui 16
2935 18:01:05.083447 best dqsien dly found for B0: ( 1, 3, 28)
2936 18:01:05.086885 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2937 18:01:05.090030 Total UI for P1: 0, mck2ui 16
2938 18:01:05.093234 best dqsien dly found for B1: ( 1, 3, 30)
2939 18:01:05.096583 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2940 18:01:05.099906 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2941 18:01:05.099999
2942 18:01:05.103683 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2943 18:01:05.107251 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2944 18:01:05.110214 [Gating] SW calibration Done
2945 18:01:05.110308 ==
2946 18:01:05.113907 Dram Type= 6, Freq= 0, CH_0, rank 1
2947 18:01:05.116892 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2948 18:01:05.120516 ==
2949 18:01:05.120618 RX Vref Scan: 0
2950 18:01:05.120708
2951 18:01:05.124079 RX Vref 0 -> 0, step: 1
2952 18:01:05.124174
2953 18:01:05.124264 RX Delay -40 -> 252, step: 8
2954 18:01:05.130231 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2955 18:01:05.133953 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2956 18:01:05.137104 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2957 18:01:05.140779 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2958 18:01:05.143800 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2959 18:01:05.150785 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2960 18:01:05.153976 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2961 18:01:05.157080 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2962 18:01:05.160563 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2963 18:01:05.164161 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2964 18:01:05.167672 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2965 18:01:05.173981 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2966 18:01:05.177824 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2967 18:01:05.180972 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2968 18:01:05.184145 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2969 18:01:05.190497 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2970 18:01:05.190601 ==
2971 18:01:05.193983 Dram Type= 6, Freq= 0, CH_0, rank 1
2972 18:01:05.197724 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2973 18:01:05.197827 ==
2974 18:01:05.197922 DQS Delay:
2975 18:01:05.200919 DQS0 = 0, DQS1 = 0
2976 18:01:05.201078 DQM Delay:
2977 18:01:05.204407 DQM0 = 115, DQM1 = 106
2978 18:01:05.204498 DQ Delay:
2979 18:01:05.207803 DQ0 =115, DQ1 =115, DQ2 =111, DQ3 =115
2980 18:01:05.211137 DQ4 =115, DQ5 =107, DQ6 =123, DQ7 =123
2981 18:01:05.214390 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =99
2982 18:01:05.217878 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =111
2983 18:01:05.217964
2984 18:01:05.218051
2985 18:01:05.218165 ==
2986 18:01:05.221193 Dram Type= 6, Freq= 0, CH_0, rank 1
2987 18:01:05.224442 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2988 18:01:05.228007 ==
2989 18:01:05.228112
2990 18:01:05.228202
2991 18:01:05.228293 TX Vref Scan disable
2992 18:01:05.230954 == TX Byte 0 ==
2993 18:01:05.234481 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2994 18:01:05.237594 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2995 18:01:05.241433 == TX Byte 1 ==
2996 18:01:05.244581 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2997 18:01:05.248042 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2998 18:01:05.248120 ==
2999 18:01:05.251220 Dram Type= 6, Freq= 0, CH_0, rank 1
3000 18:01:05.258126 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3001 18:01:05.258214 ==
3002 18:01:05.268798 TX Vref=22, minBit 3, minWin=25, winSum=420
3003 18:01:05.272366 TX Vref=24, minBit 0, minWin=26, winSum=428
3004 18:01:05.275603 TX Vref=26, minBit 0, minWin=26, winSum=429
3005 18:01:05.279314 TX Vref=28, minBit 0, minWin=27, winSum=437
3006 18:01:05.282450 TX Vref=30, minBit 7, minWin=26, winSum=437
3007 18:01:05.285581 TX Vref=32, minBit 12, minWin=26, winSum=437
3008 18:01:05.292470 [TxChooseVref] Worse bit 0, Min win 27, Win sum 437, Final Vref 28
3009 18:01:05.292579
3010 18:01:05.295440 Final TX Range 1 Vref 28
3011 18:01:05.295543
3012 18:01:05.295638 ==
3013 18:01:05.298875 Dram Type= 6, Freq= 0, CH_0, rank 1
3014 18:01:05.302491 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3015 18:01:05.302596 ==
3016 18:01:05.302696
3017 18:01:05.302790
3018 18:01:05.305665 TX Vref Scan disable
3019 18:01:05.309271 == TX Byte 0 ==
3020 18:01:05.312274 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
3021 18:01:05.315500 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
3022 18:01:05.319164 == TX Byte 1 ==
3023 18:01:05.322692 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3024 18:01:05.325635 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3025 18:01:05.325709
3026 18:01:05.329176 [DATLAT]
3027 18:01:05.329248 Freq=1200, CH0 RK1
3028 18:01:05.329320
3029 18:01:05.332663 DATLAT Default: 0xd
3030 18:01:05.332766 0, 0xFFFF, sum = 0
3031 18:01:05.335898 1, 0xFFFF, sum = 0
3032 18:01:05.336001 2, 0xFFFF, sum = 0
3033 18:01:05.339252 3, 0xFFFF, sum = 0
3034 18:01:05.339358 4, 0xFFFF, sum = 0
3035 18:01:05.342730 5, 0xFFFF, sum = 0
3036 18:01:05.342833 6, 0xFFFF, sum = 0
3037 18:01:05.346278 7, 0xFFFF, sum = 0
3038 18:01:05.346383 8, 0xFFFF, sum = 0
3039 18:01:05.349356 9, 0xFFFF, sum = 0
3040 18:01:05.349432 10, 0xFFFF, sum = 0
3041 18:01:05.353128 11, 0xFFFF, sum = 0
3042 18:01:05.353229 12, 0x0, sum = 1
3043 18:01:05.356286 13, 0x0, sum = 2
3044 18:01:05.356361 14, 0x0, sum = 3
3045 18:01:05.359501 15, 0x0, sum = 4
3046 18:01:05.359586 best_step = 13
3047 18:01:05.359652
3048 18:01:05.359712 ==
3049 18:01:05.362496 Dram Type= 6, Freq= 0, CH_0, rank 1
3050 18:01:05.369513 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3051 18:01:05.369597 ==
3052 18:01:05.369662 RX Vref Scan: 0
3053 18:01:05.369723
3054 18:01:05.373082 RX Vref 0 -> 0, step: 1
3055 18:01:05.373174
3056 18:01:05.375934 RX Delay -21 -> 252, step: 4
3057 18:01:05.379430 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3058 18:01:05.383087 iDelay=195, Bit 1, Center 114 (43 ~ 186) 144
3059 18:01:05.386211 iDelay=195, Bit 2, Center 110 (39 ~ 182) 144
3060 18:01:05.393112 iDelay=195, Bit 3, Center 114 (43 ~ 186) 144
3061 18:01:05.396370 iDelay=195, Bit 4, Center 114 (47 ~ 182) 136
3062 18:01:05.399480 iDelay=195, Bit 5, Center 104 (35 ~ 174) 140
3063 18:01:05.403221 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3064 18:01:05.406306 iDelay=195, Bit 7, Center 122 (51 ~ 194) 144
3065 18:01:05.412821 iDelay=195, Bit 8, Center 94 (27 ~ 162) 136
3066 18:01:05.416464 iDelay=195, Bit 9, Center 92 (23 ~ 162) 140
3067 18:01:05.420120 iDelay=195, Bit 10, Center 106 (39 ~ 174) 136
3068 18:01:05.423306 iDelay=195, Bit 11, Center 94 (27 ~ 162) 136
3069 18:01:05.426392 iDelay=195, Bit 12, Center 110 (43 ~ 178) 136
3070 18:01:05.433202 iDelay=195, Bit 13, Center 110 (43 ~ 178) 136
3071 18:01:05.436788 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
3072 18:01:05.439901 iDelay=195, Bit 15, Center 112 (47 ~ 178) 132
3073 18:01:05.439984 ==
3074 18:01:05.443626 Dram Type= 6, Freq= 0, CH_0, rank 1
3075 18:01:05.446339 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3076 18:01:05.446423 ==
3077 18:01:05.450042 DQS Delay:
3078 18:01:05.450124 DQS0 = 0, DQS1 = 0
3079 18:01:05.450189 DQM Delay:
3080 18:01:05.453214 DQM0 = 114, DQM1 = 104
3081 18:01:05.453299 DQ Delay:
3082 18:01:05.456670 DQ0 =114, DQ1 =114, DQ2 =110, DQ3 =114
3083 18:01:05.459822 DQ4 =114, DQ5 =104, DQ6 =122, DQ7 =122
3084 18:01:05.463030 DQ8 =94, DQ9 =92, DQ10 =106, DQ11 =94
3085 18:01:05.469882 DQ12 =110, DQ13 =110, DQ14 =116, DQ15 =112
3086 18:01:05.469966
3087 18:01:05.470031
3088 18:01:05.476857 [DQSOSCAuto] RK1, (LSB)MR18= 0x4f5, (MSB)MR19= 0x403, tDQSOscB0 = 414 ps tDQSOscB1 = 408 ps
3089 18:01:05.479978 CH0 RK1: MR19=403, MR18=4F5
3090 18:01:05.486669 CH0_RK1: MR19=0x403, MR18=0x4F5, DQSOSC=408, MR23=63, INC=39, DEC=26
3091 18:01:05.489953 [RxdqsGatingPostProcess] freq 1200
3092 18:01:05.493165 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3093 18:01:05.496916 best DQS0 dly(2T, 0.5T) = (0, 12)
3094 18:01:05.500266 best DQS1 dly(2T, 0.5T) = (0, 12)
3095 18:01:05.503374 best DQS0 P1 dly(2T, 0.5T) = (1, 0)
3096 18:01:05.506607 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3097 18:01:05.509787 best DQS0 dly(2T, 0.5T) = (0, 11)
3098 18:01:05.513649 best DQS1 dly(2T, 0.5T) = (0, 11)
3099 18:01:05.516628 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3100 18:01:05.519853 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3101 18:01:05.523377 Pre-setting of DQS Precalculation
3102 18:01:05.526463 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3103 18:01:05.526630 ==
3104 18:01:05.530253 Dram Type= 6, Freq= 0, CH_1, rank 0
3105 18:01:05.533255 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3106 18:01:05.533377 ==
3107 18:01:05.540012 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3108 18:01:05.546757 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3109 18:01:05.554876 [CA 0] Center 38 (9~68) winsize 60
3110 18:01:05.557744 [CA 1] Center 38 (8~68) winsize 61
3111 18:01:05.561439 [CA 2] Center 35 (5~65) winsize 61
3112 18:01:05.564638 [CA 3] Center 34 (4~65) winsize 62
3113 18:01:05.568193 [CA 4] Center 34 (4~65) winsize 62
3114 18:01:05.571510 [CA 5] Center 34 (4~64) winsize 61
3115 18:01:05.571622
3116 18:01:05.574639 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3117 18:01:05.574725
3118 18:01:05.577807 [CATrainingPosCal] consider 1 rank data
3119 18:01:05.581515 u2DelayCellTimex100 = 270/100 ps
3120 18:01:05.584677 CA0 delay=38 (9~68),Diff = 4 PI (19 cell)
3121 18:01:05.587902 CA1 delay=38 (8~68),Diff = 4 PI (19 cell)
3122 18:01:05.591468 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3123 18:01:05.598442 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
3124 18:01:05.601638 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3125 18:01:05.604777 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3126 18:01:05.604905
3127 18:01:05.607970 CA PerBit enable=1, Macro0, CA PI delay=34
3128 18:01:05.608067
3129 18:01:05.611621 [CBTSetCACLKResult] CA Dly = 34
3130 18:01:05.611718 CS Dly: 6 (0~37)
3131 18:01:05.611788 ==
3132 18:01:05.614777 Dram Type= 6, Freq= 0, CH_1, rank 1
3133 18:01:05.621533 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3134 18:01:05.621647 ==
3135 18:01:05.625210 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3136 18:01:05.631239 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3137 18:01:05.640160 [CA 0] Center 38 (8~68) winsize 61
3138 18:01:05.643866 [CA 1] Center 38 (9~68) winsize 60
3139 18:01:05.647010 [CA 2] Center 34 (4~65) winsize 62
3140 18:01:05.650160 [CA 3] Center 34 (4~65) winsize 62
3141 18:01:05.653324 [CA 4] Center 34 (4~65) winsize 62
3142 18:01:05.657312 [CA 5] Center 33 (3~64) winsize 62
3143 18:01:05.657428
3144 18:01:05.660167 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3145 18:01:05.660272
3146 18:01:05.663349 [CATrainingPosCal] consider 2 rank data
3147 18:01:05.666945 u2DelayCellTimex100 = 270/100 ps
3148 18:01:05.670576 CA0 delay=38 (9~68),Diff = 4 PI (19 cell)
3149 18:01:05.673465 CA1 delay=38 (9~68),Diff = 4 PI (19 cell)
3150 18:01:05.677262 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3151 18:01:05.684005 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
3152 18:01:05.687165 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3153 18:01:05.690416 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3154 18:01:05.690502
3155 18:01:05.693483 CA PerBit enable=1, Macro0, CA PI delay=34
3156 18:01:05.693560
3157 18:01:05.697236 [CBTSetCACLKResult] CA Dly = 34
3158 18:01:05.697356 CS Dly: 7 (0~40)
3159 18:01:05.697456
3160 18:01:05.700179 ----->DramcWriteLeveling(PI) begin...
3161 18:01:05.700309 ==
3162 18:01:05.703626 Dram Type= 6, Freq= 0, CH_1, rank 0
3163 18:01:05.710245 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3164 18:01:05.710400 ==
3165 18:01:05.714067 Write leveling (Byte 0): 25 => 25
3166 18:01:05.717231 Write leveling (Byte 1): 29 => 29
3167 18:01:05.717353 DramcWriteLeveling(PI) end<-----
3168 18:01:05.717451
3169 18:01:05.720376 ==
3170 18:01:05.724206 Dram Type= 6, Freq= 0, CH_1, rank 0
3171 18:01:05.727359 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3172 18:01:05.727474 ==
3173 18:01:05.730430 [Gating] SW mode calibration
3174 18:01:05.737095 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3175 18:01:05.740607 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3176 18:01:05.747190 0 15 0 | B1->B0 | 2525 2424 | 0 0 | (0 0) (0 0)
3177 18:01:05.750442 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3178 18:01:05.753617 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3179 18:01:05.760449 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3180 18:01:05.764184 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3181 18:01:05.767183 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3182 18:01:05.774046 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3183 18:01:05.777206 0 15 28 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 0)
3184 18:01:05.780811 1 0 0 | B1->B0 | 2525 2727 | 0 0 | (0 0) (0 0)
3185 18:01:05.783801 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3186 18:01:05.790805 1 0 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3187 18:01:05.794099 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3188 18:01:05.797800 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3189 18:01:05.803958 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3190 18:01:05.807640 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3191 18:01:05.811104 1 0 28 | B1->B0 | 2b2b 2424 | 0 0 | (0 0) (0 0)
3192 18:01:05.817571 1 1 0 | B1->B0 | 4242 3232 | 0 0 | (0 0) (0 0)
3193 18:01:05.820660 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3194 18:01:05.824535 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3195 18:01:05.830718 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3196 18:01:05.834538 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3197 18:01:05.837680 1 1 20 | B1->B0 | 4645 4646 | 1 0 | (0 0) (0 0)
3198 18:01:05.841361 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3199 18:01:05.847565 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3200 18:01:05.851333 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3201 18:01:05.854332 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3202 18:01:05.860828 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3203 18:01:05.864674 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3204 18:01:05.867776 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3205 18:01:05.874516 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3206 18:01:05.878101 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3207 18:01:05.881241 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3208 18:01:05.888225 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3209 18:01:05.891185 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3210 18:01:05.894921 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3211 18:01:05.901201 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3212 18:01:05.904947 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3213 18:01:05.908361 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3214 18:01:05.911503 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3215 18:01:05.918283 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3216 18:01:05.921705 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3217 18:01:05.924778 Total UI for P1: 0, mck2ui 16
3218 18:01:05.928642 best dqsien dly found for B0: ( 1, 3, 28)
3219 18:01:05.931854 Total UI for P1: 0, mck2ui 16
3220 18:01:05.934925 best dqsien dly found for B1: ( 1, 3, 28)
3221 18:01:05.938834 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3222 18:01:05.941955 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3223 18:01:05.942057
3224 18:01:05.945054 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3225 18:01:05.948160 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3226 18:01:05.952005 [Gating] SW calibration Done
3227 18:01:05.952095 ==
3228 18:01:05.955172 Dram Type= 6, Freq= 0, CH_1, rank 0
3229 18:01:05.958248 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3230 18:01:05.961362 ==
3231 18:01:05.961466 RX Vref Scan: 0
3232 18:01:05.961559
3233 18:01:05.965224 RX Vref 0 -> 0, step: 1
3234 18:01:05.965325
3235 18:01:05.968338 RX Delay -40 -> 252, step: 8
3236 18:01:05.971935 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3237 18:01:05.975051 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3238 18:01:05.978556 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3239 18:01:05.981518 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3240 18:01:05.985094 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3241 18:01:05.991453 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3242 18:01:05.995086 iDelay=200, Bit 6, Center 123 (56 ~ 191) 136
3243 18:01:05.998186 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3244 18:01:06.001859 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3245 18:01:06.004935 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3246 18:01:06.011806 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
3247 18:01:06.015265 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3248 18:01:06.018548 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3249 18:01:06.022119 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
3250 18:01:06.025174 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3251 18:01:06.032198 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3252 18:01:06.032316 ==
3253 18:01:06.035307 Dram Type= 6, Freq= 0, CH_1, rank 0
3254 18:01:06.038439 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3255 18:01:06.038550 ==
3256 18:01:06.038644 DQS Delay:
3257 18:01:06.042198 DQS0 = 0, DQS1 = 0
3258 18:01:06.042301 DQM Delay:
3259 18:01:06.045307 DQM0 = 116, DQM1 = 108
3260 18:01:06.045407 DQ Delay:
3261 18:01:06.048440 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =119
3262 18:01:06.051679 DQ4 =111, DQ5 =127, DQ6 =123, DQ7 =115
3263 18:01:06.055453 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =107
3264 18:01:06.058483 DQ12 =123, DQ13 =115, DQ14 =111, DQ15 =111
3265 18:01:06.058587
3266 18:01:06.058681
3267 18:01:06.058770 ==
3268 18:01:06.061694 Dram Type= 6, Freq= 0, CH_1, rank 0
3269 18:01:06.068325 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3270 18:01:06.068432 ==
3271 18:01:06.068527
3272 18:01:06.068616
3273 18:01:06.068706 TX Vref Scan disable
3274 18:01:06.072157 == TX Byte 0 ==
3275 18:01:06.075793 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3276 18:01:06.078968 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3277 18:01:06.082853 == TX Byte 1 ==
3278 18:01:06.086010 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3279 18:01:06.089159 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3280 18:01:06.092333 ==
3281 18:01:06.096091 Dram Type= 6, Freq= 0, CH_1, rank 0
3282 18:01:06.099088 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3283 18:01:06.099200 ==
3284 18:01:06.110172 TX Vref=22, minBit 1, minWin=25, winSum=410
3285 18:01:06.113367 TX Vref=24, minBit 1, minWin=25, winSum=416
3286 18:01:06.116793 TX Vref=26, minBit 1, minWin=25, winSum=421
3287 18:01:06.120492 TX Vref=28, minBit 1, minWin=26, winSum=426
3288 18:01:06.123994 TX Vref=30, minBit 1, minWin=26, winSum=426
3289 18:01:06.130579 TX Vref=32, minBit 13, minWin=25, winSum=428
3290 18:01:06.133825 [TxChooseVref] Worse bit 1, Min win 26, Win sum 426, Final Vref 28
3291 18:01:06.133915
3292 18:01:06.137161 Final TX Range 1 Vref 28
3293 18:01:06.137264
3294 18:01:06.137357 ==
3295 18:01:06.140267 Dram Type= 6, Freq= 0, CH_1, rank 0
3296 18:01:06.143943 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3297 18:01:06.144048 ==
3298 18:01:06.144140
3299 18:01:06.146996
3300 18:01:06.147098 TX Vref Scan disable
3301 18:01:06.150166 == TX Byte 0 ==
3302 18:01:06.153870 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3303 18:01:06.157004 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3304 18:01:06.160681 == TX Byte 1 ==
3305 18:01:06.163879 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3306 18:01:06.167053 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3307 18:01:06.167160
3308 18:01:06.170804 [DATLAT]
3309 18:01:06.170910 Freq=1200, CH1 RK0
3310 18:01:06.171004
3311 18:01:06.173775 DATLAT Default: 0xd
3312 18:01:06.173849 0, 0xFFFF, sum = 0
3313 18:01:06.176989 1, 0xFFFF, sum = 0
3314 18:01:06.177065 2, 0xFFFF, sum = 0
3315 18:01:06.180571 3, 0xFFFF, sum = 0
3316 18:01:06.180672 4, 0xFFFF, sum = 0
3317 18:01:06.183917 5, 0xFFFF, sum = 0
3318 18:01:06.184025 6, 0xFFFF, sum = 0
3319 18:01:06.187396 7, 0xFFFF, sum = 0
3320 18:01:06.187503 8, 0xFFFF, sum = 0
3321 18:01:06.190549 9, 0xFFFF, sum = 0
3322 18:01:06.193951 10, 0xFFFF, sum = 0
3323 18:01:06.194030 11, 0xFFFF, sum = 0
3324 18:01:06.197042 12, 0x0, sum = 1
3325 18:01:06.197147 13, 0x0, sum = 2
3326 18:01:06.197241 14, 0x0, sum = 3
3327 18:01:06.200258 15, 0x0, sum = 4
3328 18:01:06.200361 best_step = 13
3329 18:01:06.200451
3330 18:01:06.200540 ==
3331 18:01:06.204002 Dram Type= 6, Freq= 0, CH_1, rank 0
3332 18:01:06.210924 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3333 18:01:06.211041 ==
3334 18:01:06.211145 RX Vref Scan: 1
3335 18:01:06.211242
3336 18:01:06.213989 Set Vref Range= 32 -> 127
3337 18:01:06.214066
3338 18:01:06.217458 RX Vref 32 -> 127, step: 1
3339 18:01:06.217536
3340 18:01:06.220770 RX Delay -21 -> 252, step: 4
3341 18:01:06.220881
3342 18:01:06.223981 Set Vref, RX VrefLevel [Byte0]: 32
3343 18:01:06.227068 [Byte1]: 32
3344 18:01:06.227175
3345 18:01:06.230911 Set Vref, RX VrefLevel [Byte0]: 33
3346 18:01:06.234098 [Byte1]: 33
3347 18:01:06.234205
3348 18:01:06.237578 Set Vref, RX VrefLevel [Byte0]: 34
3349 18:01:06.240368 [Byte1]: 34
3350 18:01:06.244569
3351 18:01:06.244672 Set Vref, RX VrefLevel [Byte0]: 35
3352 18:01:06.247705 [Byte1]: 35
3353 18:01:06.252563
3354 18:01:06.252642 Set Vref, RX VrefLevel [Byte0]: 36
3355 18:01:06.255697 [Byte1]: 36
3356 18:01:06.260204
3357 18:01:06.260307 Set Vref, RX VrefLevel [Byte0]: 37
3358 18:01:06.263941 [Byte1]: 37
3359 18:01:06.268256
3360 18:01:06.268336 Set Vref, RX VrefLevel [Byte0]: 38
3361 18:01:06.271374 [Byte1]: 38
3362 18:01:06.276374
3363 18:01:06.276461 Set Vref, RX VrefLevel [Byte0]: 39
3364 18:01:06.279544 [Byte1]: 39
3365 18:01:06.283944
3366 18:01:06.284053 Set Vref, RX VrefLevel [Byte0]: 40
3367 18:01:06.287587 [Byte1]: 40
3368 18:01:06.291906
3369 18:01:06.292009 Set Vref, RX VrefLevel [Byte0]: 41
3370 18:01:06.295241 [Byte1]: 41
3371 18:01:06.300099
3372 18:01:06.300172 Set Vref, RX VrefLevel [Byte0]: 42
3373 18:01:06.303273 [Byte1]: 42
3374 18:01:06.307819
3375 18:01:06.307920 Set Vref, RX VrefLevel [Byte0]: 43
3376 18:01:06.311042 [Byte1]: 43
3377 18:01:06.315924
3378 18:01:06.316002 Set Vref, RX VrefLevel [Byte0]: 44
3379 18:01:06.319015 [Byte1]: 44
3380 18:01:06.324024
3381 18:01:06.324137 Set Vref, RX VrefLevel [Byte0]: 45
3382 18:01:06.327092 [Byte1]: 45
3383 18:01:06.331918
3384 18:01:06.331998 Set Vref, RX VrefLevel [Byte0]: 46
3385 18:01:06.335122 [Byte1]: 46
3386 18:01:06.339550
3387 18:01:06.339667 Set Vref, RX VrefLevel [Byte0]: 47
3388 18:01:06.343026 [Byte1]: 47
3389 18:01:06.347712
3390 18:01:06.347841 Set Vref, RX VrefLevel [Byte0]: 48
3391 18:01:06.350871 [Byte1]: 48
3392 18:01:06.355616
3393 18:01:06.355753 Set Vref, RX VrefLevel [Byte0]: 49
3394 18:01:06.358480 [Byte1]: 49
3395 18:01:06.363421
3396 18:01:06.363557 Set Vref, RX VrefLevel [Byte0]: 50
3397 18:01:06.366441 [Byte1]: 50
3398 18:01:06.371165
3399 18:01:06.371287 Set Vref, RX VrefLevel [Byte0]: 51
3400 18:01:06.374579 [Byte1]: 51
3401 18:01:06.378979
3402 18:01:06.379082 Set Vref, RX VrefLevel [Byte0]: 52
3403 18:01:06.382513 [Byte1]: 52
3404 18:01:06.386768
3405 18:01:06.386872 Set Vref, RX VrefLevel [Byte0]: 53
3406 18:01:06.390371 [Byte1]: 53
3407 18:01:06.394738
3408 18:01:06.394845 Set Vref, RX VrefLevel [Byte0]: 54
3409 18:01:06.398596 [Byte1]: 54
3410 18:01:06.402897
3411 18:01:06.403019 Set Vref, RX VrefLevel [Byte0]: 55
3412 18:01:06.406022 [Byte1]: 55
3413 18:01:06.411069
3414 18:01:06.411174 Set Vref, RX VrefLevel [Byte0]: 56
3415 18:01:06.414209 [Byte1]: 56
3416 18:01:06.419070
3417 18:01:06.419184 Set Vref, RX VrefLevel [Byte0]: 57
3418 18:01:06.422073 [Byte1]: 57
3419 18:01:06.426476
3420 18:01:06.426579 Set Vref, RX VrefLevel [Byte0]: 58
3421 18:01:06.430272 [Byte1]: 58
3422 18:01:06.434551
3423 18:01:06.434662 Set Vref, RX VrefLevel [Byte0]: 59
3424 18:01:06.438165 [Byte1]: 59
3425 18:01:06.442305
3426 18:01:06.442413 Set Vref, RX VrefLevel [Byte0]: 60
3427 18:01:06.445752 [Byte1]: 60
3428 18:01:06.450371
3429 18:01:06.450489 Set Vref, RX VrefLevel [Byte0]: 61
3430 18:01:06.453853 [Byte1]: 61
3431 18:01:06.458403
3432 18:01:06.458544 Set Vref, RX VrefLevel [Byte0]: 62
3433 18:01:06.461604 [Byte1]: 62
3434 18:01:06.466504
3435 18:01:06.466616 Set Vref, RX VrefLevel [Byte0]: 63
3436 18:01:06.469692 [Byte1]: 63
3437 18:01:06.474391
3438 18:01:06.474499 Set Vref, RX VrefLevel [Byte0]: 64
3439 18:01:06.477763 [Byte1]: 64
3440 18:01:06.481769
3441 18:01:06.481852 Set Vref, RX VrefLevel [Byte0]: 65
3442 18:01:06.485406 [Byte1]: 65
3443 18:01:06.489720
3444 18:01:06.489805 Set Vref, RX VrefLevel [Byte0]: 66
3445 18:01:06.493555 [Byte1]: 66
3446 18:01:06.498011
3447 18:01:06.498120 Set Vref, RX VrefLevel [Byte0]: 67
3448 18:01:06.501144 [Byte1]: 67
3449 18:01:06.506003
3450 18:01:06.506106 Set Vref, RX VrefLevel [Byte0]: 68
3451 18:01:06.509286 [Byte1]: 68
3452 18:01:06.513681
3453 18:01:06.513756 Set Vref, RX VrefLevel [Byte0]: 69
3454 18:01:06.516817 [Byte1]: 69
3455 18:01:06.521855
3456 18:01:06.521944 Set Vref, RX VrefLevel [Byte0]: 70
3457 18:01:06.524918 [Byte1]: 70
3458 18:01:06.529853
3459 18:01:06.529966 Final RX Vref Byte 0 = 60 to rank0
3460 18:01:06.533077 Final RX Vref Byte 1 = 52 to rank0
3461 18:01:06.536256 Final RX Vref Byte 0 = 60 to rank1
3462 18:01:06.539404 Final RX Vref Byte 1 = 52 to rank1==
3463 18:01:06.542662 Dram Type= 6, Freq= 0, CH_1, rank 0
3464 18:01:06.550054 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3465 18:01:06.550172 ==
3466 18:01:06.550272 DQS Delay:
3467 18:01:06.550372 DQS0 = 0, DQS1 = 0
3468 18:01:06.552889 DQM Delay:
3469 18:01:06.553018 DQM0 = 116, DQM1 = 109
3470 18:01:06.556217 DQ Delay:
3471 18:01:06.559833 DQ0 =118, DQ1 =112, DQ2 =106, DQ3 =116
3472 18:01:06.562820 DQ4 =116, DQ5 =124, DQ6 =128, DQ7 =114
3473 18:01:06.566446 DQ8 =98, DQ9 =98, DQ10 =110, DQ11 =104
3474 18:01:06.570096 DQ12 =116, DQ13 =116, DQ14 =116, DQ15 =114
3475 18:01:06.570202
3476 18:01:06.570295
3477 18:01:06.576388 [DQSOSCAuto] RK0, (LSB)MR18= 0xfadf, (MSB)MR19= 0x303, tDQSOscB0 = 423 ps tDQSOscB1 = 412 ps
3478 18:01:06.579921 CH1 RK0: MR19=303, MR18=FADF
3479 18:01:06.586626 CH1_RK0: MR19=0x303, MR18=0xFADF, DQSOSC=412, MR23=63, INC=38, DEC=25
3480 18:01:06.586741
3481 18:01:06.589751 ----->DramcWriteLeveling(PI) begin...
3482 18:01:06.589855 ==
3483 18:01:06.593335 Dram Type= 6, Freq= 0, CH_1, rank 1
3484 18:01:06.596801 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3485 18:01:06.596908 ==
3486 18:01:06.600169 Write leveling (Byte 0): 25 => 25
3487 18:01:06.603594 Write leveling (Byte 1): 27 => 27
3488 18:01:06.606322 DramcWriteLeveling(PI) end<-----
3489 18:01:06.606424
3490 18:01:06.606524 ==
3491 18:01:06.610000 Dram Type= 6, Freq= 0, CH_1, rank 1
3492 18:01:06.613203 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3493 18:01:06.616622 ==
3494 18:01:06.616729 [Gating] SW mode calibration
3495 18:01:06.626684 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3496 18:01:06.629842 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3497 18:01:06.633013 0 15 0 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
3498 18:01:06.639954 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3499 18:01:06.643163 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3500 18:01:06.646311 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3501 18:01:06.653311 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3502 18:01:06.656505 0 15 20 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 0)
3503 18:01:06.659595 0 15 24 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 0)
3504 18:01:06.666533 0 15 28 | B1->B0 | 2828 2323 | 0 0 | (0 1) (0 0)
3505 18:01:06.670088 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3506 18:01:06.673113 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3507 18:01:06.679833 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3508 18:01:06.682838 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3509 18:01:06.686590 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3510 18:01:06.692852 1 0 20 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
3511 18:01:06.695970 1 0 24 | B1->B0 | 2424 3b3b | 0 0 | (0 0) (0 0)
3512 18:01:06.699752 1 0 28 | B1->B0 | 4141 4646 | 1 0 | (0 0) (0 0)
3513 18:01:06.705910 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3514 18:01:06.709374 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3515 18:01:06.713124 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3516 18:01:06.719751 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3517 18:01:06.722901 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3518 18:01:06.726168 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3519 18:01:06.732772 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3520 18:01:06.735982 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3521 18:01:06.739709 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3522 18:01:06.742807 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3523 18:01:06.749614 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3524 18:01:06.752756 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3525 18:01:06.755942 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3526 18:01:06.762887 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3527 18:01:06.765943 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3528 18:01:06.769610 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3529 18:01:06.776050 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3530 18:01:06.779044 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3531 18:01:06.782919 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3532 18:01:06.789339 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3533 18:01:06.792484 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3534 18:01:06.796308 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3535 18:01:06.803067 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3536 18:01:06.806222 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3537 18:01:06.809475 Total UI for P1: 0, mck2ui 16
3538 18:01:06.813045 best dqsien dly found for B0: ( 1, 3, 24)
3539 18:01:06.816265 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3540 18:01:06.819467 Total UI for P1: 0, mck2ui 16
3541 18:01:06.822595 best dqsien dly found for B1: ( 1, 3, 28)
3542 18:01:06.826270 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3543 18:01:06.829732 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3544 18:01:06.829814
3545 18:01:06.832435 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3546 18:01:06.839482 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3547 18:01:06.839597 [Gating] SW calibration Done
3548 18:01:06.839710 ==
3549 18:01:06.842592 Dram Type= 6, Freq= 0, CH_1, rank 1
3550 18:01:06.849621 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3551 18:01:06.849711 ==
3552 18:01:06.849794 RX Vref Scan: 0
3553 18:01:06.849882
3554 18:01:06.852832 RX Vref 0 -> 0, step: 1
3555 18:01:06.852942
3556 18:01:06.855889 RX Delay -40 -> 252, step: 8
3557 18:01:06.859054 iDelay=192, Bit 0, Center 111 (40 ~ 183) 144
3558 18:01:06.862803 iDelay=192, Bit 1, Center 111 (40 ~ 183) 144
3559 18:01:06.865959 iDelay=192, Bit 2, Center 103 (32 ~ 175) 144
3560 18:01:06.872484 iDelay=192, Bit 3, Center 115 (48 ~ 183) 136
3561 18:01:06.876219 iDelay=192, Bit 4, Center 111 (40 ~ 183) 144
3562 18:01:06.879100 iDelay=192, Bit 5, Center 123 (56 ~ 191) 136
3563 18:01:06.882830 iDelay=192, Bit 6, Center 119 (48 ~ 191) 144
3564 18:01:06.886070 iDelay=192, Bit 7, Center 107 (40 ~ 175) 136
3565 18:01:06.889716 iDelay=192, Bit 8, Center 103 (32 ~ 175) 144
3566 18:01:06.896147 iDelay=192, Bit 9, Center 95 (24 ~ 167) 144
3567 18:01:06.899295 iDelay=192, Bit 10, Center 111 (40 ~ 183) 144
3568 18:01:06.902947 iDelay=192, Bit 11, Center 103 (32 ~ 175) 144
3569 18:01:06.906066 iDelay=192, Bit 12, Center 115 (48 ~ 183) 136
3570 18:01:06.909344 iDelay=192, Bit 13, Center 119 (48 ~ 191) 144
3571 18:01:06.916317 iDelay=192, Bit 14, Center 119 (48 ~ 191) 144
3572 18:01:06.919344 iDelay=192, Bit 15, Center 119 (48 ~ 191) 144
3573 18:01:06.919457 ==
3574 18:01:06.922990 Dram Type= 6, Freq= 0, CH_1, rank 1
3575 18:01:06.926007 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3576 18:01:06.926114 ==
3577 18:01:06.929550 DQS Delay:
3578 18:01:06.929662 DQS0 = 0, DQS1 = 0
3579 18:01:06.929759 DQM Delay:
3580 18:01:06.932668 DQM0 = 112, DQM1 = 110
3581 18:01:06.932776 DQ Delay:
3582 18:01:06.936246 DQ0 =111, DQ1 =111, DQ2 =103, DQ3 =115
3583 18:01:06.939596 DQ4 =111, DQ5 =123, DQ6 =119, DQ7 =107
3584 18:01:06.942876 DQ8 =103, DQ9 =95, DQ10 =111, DQ11 =103
3585 18:01:06.949432 DQ12 =115, DQ13 =119, DQ14 =119, DQ15 =119
3586 18:01:06.949544
3587 18:01:06.949637
3588 18:01:06.949710 ==
3589 18:01:06.952521 Dram Type= 6, Freq= 0, CH_1, rank 1
3590 18:01:06.956233 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3591 18:01:06.956341 ==
3592 18:01:06.956440
3593 18:01:06.956531
3594 18:01:06.959389 TX Vref Scan disable
3595 18:01:06.959493 == TX Byte 0 ==
3596 18:01:06.966455 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3597 18:01:06.969561 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3598 18:01:06.969673 == TX Byte 1 ==
3599 18:01:06.976534 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3600 18:01:06.979708 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3601 18:01:06.979822 ==
3602 18:01:06.982826 Dram Type= 6, Freq= 0, CH_1, rank 1
3603 18:01:06.986032 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3604 18:01:06.986148 ==
3605 18:01:06.998810 TX Vref=22, minBit 0, minWin=25, winSum=418
3606 18:01:07.002126 TX Vref=24, minBit 3, minWin=25, winSum=421
3607 18:01:07.005482 TX Vref=26, minBit 3, minWin=25, winSum=424
3608 18:01:07.008803 TX Vref=28, minBit 3, minWin=26, winSum=427
3609 18:01:07.012032 TX Vref=30, minBit 1, minWin=26, winSum=432
3610 18:01:07.015844 TX Vref=32, minBit 9, minWin=26, winSum=433
3611 18:01:07.022079 [TxChooseVref] Worse bit 9, Min win 26, Win sum 433, Final Vref 32
3612 18:01:07.022171
3613 18:01:07.025274 Final TX Range 1 Vref 32
3614 18:01:07.025368
3615 18:01:07.025459 ==
3616 18:01:07.028995 Dram Type= 6, Freq= 0, CH_1, rank 1
3617 18:01:07.032039 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3618 18:01:07.032151 ==
3619 18:01:07.032263
3620 18:01:07.035463
3621 18:01:07.035585 TX Vref Scan disable
3622 18:01:07.038678 == TX Byte 0 ==
3623 18:01:07.042414 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3624 18:01:07.045224 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3625 18:01:07.048726 == TX Byte 1 ==
3626 18:01:07.052244 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3627 18:01:07.055266 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3628 18:01:07.055370
3629 18:01:07.058956 [DATLAT]
3630 18:01:07.059066 Freq=1200, CH1 RK1
3631 18:01:07.059170
3632 18:01:07.062162 DATLAT Default: 0xd
3633 18:01:07.062274 0, 0xFFFF, sum = 0
3634 18:01:07.065221 1, 0xFFFF, sum = 0
3635 18:01:07.065333 2, 0xFFFF, sum = 0
3636 18:01:07.069088 3, 0xFFFF, sum = 0
3637 18:01:07.069192 4, 0xFFFF, sum = 0
3638 18:01:07.072211 5, 0xFFFF, sum = 0
3639 18:01:07.072320 6, 0xFFFF, sum = 0
3640 18:01:07.075331 7, 0xFFFF, sum = 0
3641 18:01:07.075433 8, 0xFFFF, sum = 0
3642 18:01:07.079057 9, 0xFFFF, sum = 0
3643 18:01:07.082038 10, 0xFFFF, sum = 0
3644 18:01:07.082151 11, 0xFFFF, sum = 0
3645 18:01:07.085806 12, 0x0, sum = 1
3646 18:01:07.085910 13, 0x0, sum = 2
3647 18:01:07.086003 14, 0x0, sum = 3
3648 18:01:07.088942 15, 0x0, sum = 4
3649 18:01:07.089053 best_step = 13
3650 18:01:07.089122
3651 18:01:07.089184 ==
3652 18:01:07.092227 Dram Type= 6, Freq= 0, CH_1, rank 1
3653 18:01:07.098955 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3654 18:01:07.099064 ==
3655 18:01:07.099167 RX Vref Scan: 0
3656 18:01:07.099258
3657 18:01:07.102037 RX Vref 0 -> 0, step: 1
3658 18:01:07.102135
3659 18:01:07.105445 RX Delay -21 -> 252, step: 4
3660 18:01:07.108873 iDelay=191, Bit 0, Center 114 (47 ~ 182) 136
3661 18:01:07.111985 iDelay=191, Bit 1, Center 108 (43 ~ 174) 132
3662 18:01:07.118809 iDelay=191, Bit 2, Center 104 (39 ~ 170) 132
3663 18:01:07.122065 iDelay=191, Bit 3, Center 112 (47 ~ 178) 132
3664 18:01:07.125508 iDelay=191, Bit 4, Center 114 (51 ~ 178) 128
3665 18:01:07.128560 iDelay=191, Bit 5, Center 124 (59 ~ 190) 132
3666 18:01:07.132308 iDelay=191, Bit 6, Center 120 (55 ~ 186) 132
3667 18:01:07.139064 iDelay=191, Bit 7, Center 110 (47 ~ 174) 128
3668 18:01:07.142142 iDelay=191, Bit 8, Center 96 (31 ~ 162) 132
3669 18:01:07.145651 iDelay=191, Bit 9, Center 98 (35 ~ 162) 128
3670 18:01:07.148543 iDelay=191, Bit 10, Center 110 (43 ~ 178) 136
3671 18:01:07.152323 iDelay=191, Bit 11, Center 102 (35 ~ 170) 136
3672 18:01:07.158690 iDelay=191, Bit 12, Center 114 (51 ~ 178) 128
3673 18:01:07.162347 iDelay=191, Bit 13, Center 120 (55 ~ 186) 132
3674 18:01:07.165497 iDelay=191, Bit 14, Center 118 (55 ~ 182) 128
3675 18:01:07.168533 iDelay=191, Bit 15, Center 118 (55 ~ 182) 128
3676 18:01:07.168636 ==
3677 18:01:07.172221 Dram Type= 6, Freq= 0, CH_1, rank 1
3678 18:01:07.178693 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3679 18:01:07.178793 ==
3680 18:01:07.178861 DQS Delay:
3681 18:01:07.178924 DQS0 = 0, DQS1 = 0
3682 18:01:07.182372 DQM Delay:
3683 18:01:07.182478 DQM0 = 113, DQM1 = 109
3684 18:01:07.185478 DQ Delay:
3685 18:01:07.188617 DQ0 =114, DQ1 =108, DQ2 =104, DQ3 =112
3686 18:01:07.192284 DQ4 =114, DQ5 =124, DQ6 =120, DQ7 =110
3687 18:01:07.195385 DQ8 =96, DQ9 =98, DQ10 =110, DQ11 =102
3688 18:01:07.198591 DQ12 =114, DQ13 =120, DQ14 =118, DQ15 =118
3689 18:01:07.198675
3690 18:01:07.198745
3691 18:01:07.205310 [DQSOSCAuto] RK1, (LSB)MR18= 0xf900, (MSB)MR19= 0x304, tDQSOscB0 = 410 ps tDQSOscB1 = 412 ps
3692 18:01:07.208360 CH1 RK1: MR19=304, MR18=F900
3693 18:01:07.215322 CH1_RK1: MR19=0x304, MR18=0xF900, DQSOSC=410, MR23=63, INC=39, DEC=26
3694 18:01:07.218500 [RxdqsGatingPostProcess] freq 1200
3695 18:01:07.225332 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3696 18:01:07.228903 best DQS0 dly(2T, 0.5T) = (0, 11)
3697 18:01:07.229019 best DQS1 dly(2T, 0.5T) = (0, 11)
3698 18:01:07.231809 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3699 18:01:07.235306 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3700 18:01:07.238495 best DQS0 dly(2T, 0.5T) = (0, 11)
3701 18:01:07.242132 best DQS1 dly(2T, 0.5T) = (0, 11)
3702 18:01:07.245762 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3703 18:01:07.248850 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3704 18:01:07.251890 Pre-setting of DQS Precalculation
3705 18:01:07.258868 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3706 18:01:07.265858 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3707 18:01:07.272599 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3708 18:01:07.272705
3709 18:01:07.272806
3710 18:01:07.275640 [Calibration Summary] 2400 Mbps
3711 18:01:07.275748 CH 0, Rank 0
3712 18:01:07.278898 SW Impedance : PASS
3713 18:01:07.279001 DUTY Scan : NO K
3714 18:01:07.282242 ZQ Calibration : PASS
3715 18:01:07.286009 Jitter Meter : NO K
3716 18:01:07.286114 CBT Training : PASS
3717 18:01:07.289274 Write leveling : PASS
3718 18:01:07.292382 RX DQS gating : PASS
3719 18:01:07.292493 RX DQ/DQS(RDDQC) : PASS
3720 18:01:07.295572 TX DQ/DQS : PASS
3721 18:01:07.298827 RX DATLAT : PASS
3722 18:01:07.298943 RX DQ/DQS(Engine): PASS
3723 18:01:07.302588 TX OE : NO K
3724 18:01:07.302698 All Pass.
3725 18:01:07.302790
3726 18:01:07.305749 CH 0, Rank 1
3727 18:01:07.305858 SW Impedance : PASS
3728 18:01:07.308859 DUTY Scan : NO K
3729 18:01:07.312559 ZQ Calibration : PASS
3730 18:01:07.312662 Jitter Meter : NO K
3731 18:01:07.315571 CBT Training : PASS
3732 18:01:07.319153 Write leveling : PASS
3733 18:01:07.319237 RX DQS gating : PASS
3734 18:01:07.322309 RX DQ/DQS(RDDQC) : PASS
3735 18:01:07.322418 TX DQ/DQS : PASS
3736 18:01:07.325436 RX DATLAT : PASS
3737 18:01:07.329282 RX DQ/DQS(Engine): PASS
3738 18:01:07.329366 TX OE : NO K
3739 18:01:07.332375 All Pass.
3740 18:01:07.332458
3741 18:01:07.332524 CH 1, Rank 0
3742 18:01:07.335524 SW Impedance : PASS
3743 18:01:07.335609 DUTY Scan : NO K
3744 18:01:07.338842 ZQ Calibration : PASS
3745 18:01:07.342535 Jitter Meter : NO K
3746 18:01:07.342618 CBT Training : PASS
3747 18:01:07.345544 Write leveling : PASS
3748 18:01:07.348858 RX DQS gating : PASS
3749 18:01:07.348967 RX DQ/DQS(RDDQC) : PASS
3750 18:01:07.352113 TX DQ/DQS : PASS
3751 18:01:07.355867 RX DATLAT : PASS
3752 18:01:07.355951 RX DQ/DQS(Engine): PASS
3753 18:01:07.359239 TX OE : NO K
3754 18:01:07.359323 All Pass.
3755 18:01:07.359389
3756 18:01:07.362217 CH 1, Rank 1
3757 18:01:07.362300 SW Impedance : PASS
3758 18:01:07.365719 DUTY Scan : NO K
3759 18:01:07.369150 ZQ Calibration : PASS
3760 18:01:07.369235 Jitter Meter : NO K
3761 18:01:07.372232 CBT Training : PASS
3762 18:01:07.372315 Write leveling : PASS
3763 18:01:07.375464 RX DQS gating : PASS
3764 18:01:07.378927 RX DQ/DQS(RDDQC) : PASS
3765 18:01:07.379011 TX DQ/DQS : PASS
3766 18:01:07.382261 RX DATLAT : PASS
3767 18:01:07.385848 RX DQ/DQS(Engine): PASS
3768 18:01:07.385932 TX OE : NO K
3769 18:01:07.388897 All Pass.
3770 18:01:07.388986
3771 18:01:07.389053 DramC Write-DBI off
3772 18:01:07.392032 PER_BANK_REFRESH: Hybrid Mode
3773 18:01:07.392119 TX_TRACKING: ON
3774 18:01:07.402258 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3775 18:01:07.405444 [FAST_K] Save calibration result to emmc
3776 18:01:07.408487 dramc_set_vcore_voltage set vcore to 650000
3777 18:01:07.412261 Read voltage for 600, 5
3778 18:01:07.412349 Vio18 = 0
3779 18:01:07.415394 Vcore = 650000
3780 18:01:07.415478 Vdram = 0
3781 18:01:07.415544 Vddq = 0
3782 18:01:07.419002 Vmddr = 0
3783 18:01:07.421892 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3784 18:01:07.429048 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3785 18:01:07.429167 MEM_TYPE=3, freq_sel=19
3786 18:01:07.432166 sv_algorithm_assistance_LP4_1600
3787 18:01:07.439047 ============ PULL DRAM RESETB DOWN ============
3788 18:01:07.442099 ========== PULL DRAM RESETB DOWN end =========
3789 18:01:07.445317 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3790 18:01:07.448458 ===================================
3791 18:01:07.452233 LPDDR4 DRAM CONFIGURATION
3792 18:01:07.455388 ===================================
3793 18:01:07.455504 EX_ROW_EN[0] = 0x0
3794 18:01:07.458932 EX_ROW_EN[1] = 0x0
3795 18:01:07.461951 LP4Y_EN = 0x0
3796 18:01:07.462069 WORK_FSP = 0x0
3797 18:01:07.465633 WL = 0x2
3798 18:01:07.465753 RL = 0x2
3799 18:01:07.468699 BL = 0x2
3800 18:01:07.468799 RPST = 0x0
3801 18:01:07.472235 RD_PRE = 0x0
3802 18:01:07.472364 WR_PRE = 0x1
3803 18:01:07.475145 WR_PST = 0x0
3804 18:01:07.475264 DBI_WR = 0x0
3805 18:01:07.478949 DBI_RD = 0x0
3806 18:01:07.479076 OTF = 0x1
3807 18:01:07.481899 ===================================
3808 18:01:07.485237 ===================================
3809 18:01:07.489037 ANA top config
3810 18:01:07.492206 ===================================
3811 18:01:07.492296 DLL_ASYNC_EN = 0
3812 18:01:07.495346 ALL_SLAVE_EN = 1
3813 18:01:07.498724 NEW_RANK_MODE = 1
3814 18:01:07.502246 DLL_IDLE_MODE = 1
3815 18:01:07.502328 LP45_APHY_COMB_EN = 1
3816 18:01:07.505812 TX_ODT_DIS = 1
3817 18:01:07.509076 NEW_8X_MODE = 1
3818 18:01:07.512209 ===================================
3819 18:01:07.515274 ===================================
3820 18:01:07.519102 data_rate = 1200
3821 18:01:07.522246 CKR = 1
3822 18:01:07.525238 DQ_P2S_RATIO = 8
3823 18:01:07.528856 ===================================
3824 18:01:07.528958 CA_P2S_RATIO = 8
3825 18:01:07.531905 DQ_CA_OPEN = 0
3826 18:01:07.535425 DQ_SEMI_OPEN = 0
3827 18:01:07.538610 CA_SEMI_OPEN = 0
3828 18:01:07.542398 CA_FULL_RATE = 0
3829 18:01:07.542500 DQ_CKDIV4_EN = 1
3830 18:01:07.545628 CA_CKDIV4_EN = 1
3831 18:01:07.548762 CA_PREDIV_EN = 0
3832 18:01:07.552429 PH8_DLY = 0
3833 18:01:07.555514 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3834 18:01:07.558606 DQ_AAMCK_DIV = 4
3835 18:01:07.558712 CA_AAMCK_DIV = 4
3836 18:01:07.561804 CA_ADMCK_DIV = 4
3837 18:01:07.565362 DQ_TRACK_CA_EN = 0
3838 18:01:07.569154 CA_PICK = 600
3839 18:01:07.572333 CA_MCKIO = 600
3840 18:01:07.575484 MCKIO_SEMI = 0
3841 18:01:07.578705 PLL_FREQ = 2288
3842 18:01:07.578814 DQ_UI_PI_RATIO = 32
3843 18:01:07.582469 CA_UI_PI_RATIO = 0
3844 18:01:07.585419 ===================================
3845 18:01:07.588798 ===================================
3846 18:01:07.592107 memory_type:LPDDR4
3847 18:01:07.595354 GP_NUM : 10
3848 18:01:07.595471 SRAM_EN : 1
3849 18:01:07.598757 MD32_EN : 0
3850 18:01:07.602252 ===================================
3851 18:01:07.602344 [ANA_INIT] >>>>>>>>>>>>>>
3852 18:01:07.605829 <<<<<< [CONFIGURE PHASE]: ANA_TX
3853 18:01:07.608572 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3854 18:01:07.612293 ===================================
3855 18:01:07.615105 data_rate = 1200,PCW = 0X5800
3856 18:01:07.618553 ===================================
3857 18:01:07.621768 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3858 18:01:07.628904 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3859 18:01:07.635470 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3860 18:01:07.638398 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3861 18:01:07.642149 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3862 18:01:07.645319 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3863 18:01:07.648382 [ANA_INIT] flow start
3864 18:01:07.648486 [ANA_INIT] PLL >>>>>>>>
3865 18:01:07.652351 [ANA_INIT] PLL <<<<<<<<
3866 18:01:07.655443 [ANA_INIT] MIDPI >>>>>>>>
3867 18:01:07.655554 [ANA_INIT] MIDPI <<<<<<<<
3868 18:01:07.658622 [ANA_INIT] DLL >>>>>>>>
3869 18:01:07.661959 [ANA_INIT] flow end
3870 18:01:07.664919 ============ LP4 DIFF to SE enter ============
3871 18:01:07.668497 ============ LP4 DIFF to SE exit ============
3872 18:01:07.671681 [ANA_INIT] <<<<<<<<<<<<<
3873 18:01:07.674795 [Flow] Enable top DCM control >>>>>
3874 18:01:07.678597 [Flow] Enable top DCM control <<<<<
3875 18:01:07.681786 Enable DLL master slave shuffle
3876 18:01:07.684952 ==============================================================
3877 18:01:07.688168 Gating Mode config
3878 18:01:07.694915 ==============================================================
3879 18:01:07.695042 Config description:
3880 18:01:07.704791 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3881 18:01:07.711749 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3882 18:01:07.714757 SELPH_MODE 0: By rank 1: By Phase
3883 18:01:07.721617 ==============================================================
3884 18:01:07.725188 GAT_TRACK_EN = 1
3885 18:01:07.728185 RX_GATING_MODE = 2
3886 18:01:07.731600 RX_GATING_TRACK_MODE = 2
3887 18:01:07.734806 SELPH_MODE = 1
3888 18:01:07.737884 PICG_EARLY_EN = 1
3889 18:01:07.741437 VALID_LAT_VALUE = 1
3890 18:01:07.744789 ==============================================================
3891 18:01:07.747971 Enter into Gating configuration >>>>
3892 18:01:07.751834 Exit from Gating configuration <<<<
3893 18:01:07.754894 Enter into DVFS_PRE_config >>>>>
3894 18:01:07.768143 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3895 18:01:07.768255 Exit from DVFS_PRE_config <<<<<
3896 18:01:07.771750 Enter into PICG configuration >>>>
3897 18:01:07.774782 Exit from PICG configuration <<<<
3898 18:01:07.777932 [RX_INPUT] configuration >>>>>
3899 18:01:07.781614 [RX_INPUT] configuration <<<<<
3900 18:01:07.788014 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3901 18:01:07.791168 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3902 18:01:07.798274 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3903 18:01:07.804857 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3904 18:01:07.811594 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3905 18:01:07.817967 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3906 18:01:07.821152 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3907 18:01:07.824441 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3908 18:01:07.828102 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3909 18:01:07.834693 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3910 18:01:07.837746 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3911 18:01:07.840756 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3912 18:01:07.844651 ===================================
3913 18:01:07.847853 LPDDR4 DRAM CONFIGURATION
3914 18:01:07.851027 ===================================
3915 18:01:07.851117 EX_ROW_EN[0] = 0x0
3916 18:01:07.854480 EX_ROW_EN[1] = 0x0
3917 18:01:07.857633 LP4Y_EN = 0x0
3918 18:01:07.857718 WORK_FSP = 0x0
3919 18:01:07.860873 WL = 0x2
3920 18:01:07.860955 RL = 0x2
3921 18:01:07.864537 BL = 0x2
3922 18:01:07.864661 RPST = 0x0
3923 18:01:07.867717 RD_PRE = 0x0
3924 18:01:07.867835 WR_PRE = 0x1
3925 18:01:07.870939 WR_PST = 0x0
3926 18:01:07.871048 DBI_WR = 0x0
3927 18:01:07.874651 DBI_RD = 0x0
3928 18:01:07.874730 OTF = 0x1
3929 18:01:07.877623 ===================================
3930 18:01:07.881465 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3931 18:01:07.887811 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3932 18:01:07.891526 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3933 18:01:07.894730 ===================================
3934 18:01:07.897836 LPDDR4 DRAM CONFIGURATION
3935 18:01:07.901733 ===================================
3936 18:01:07.901815 EX_ROW_EN[0] = 0x10
3937 18:01:07.904781 EX_ROW_EN[1] = 0x0
3938 18:01:07.904855 LP4Y_EN = 0x0
3939 18:01:07.907856 WORK_FSP = 0x0
3940 18:01:07.907941 WL = 0x2
3941 18:01:07.910994 RL = 0x2
3942 18:01:07.911076 BL = 0x2
3943 18:01:07.914442 RPST = 0x0
3944 18:01:07.918132 RD_PRE = 0x0
3945 18:01:07.918215 WR_PRE = 0x1
3946 18:01:07.921183 WR_PST = 0x0
3947 18:01:07.921270 DBI_WR = 0x0
3948 18:01:07.924729 DBI_RD = 0x0
3949 18:01:07.924833 OTF = 0x1
3950 18:01:07.927774 ===================================
3951 18:01:07.934470 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3952 18:01:07.938396 nWR fixed to 30
3953 18:01:07.941397 [ModeRegInit_LP4] CH0 RK0
3954 18:01:07.941483 [ModeRegInit_LP4] CH0 RK1
3955 18:01:07.945154 [ModeRegInit_LP4] CH1 RK0
3956 18:01:07.948307 [ModeRegInit_LP4] CH1 RK1
3957 18:01:07.948392 match AC timing 17
3958 18:01:07.954920 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3959 18:01:07.958275 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3960 18:01:07.961542 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3961 18:01:07.968060 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3962 18:01:07.971430 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3963 18:01:07.971517 ==
3964 18:01:07.974995 Dram Type= 6, Freq= 0, CH_0, rank 0
3965 18:01:07.977961 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3966 18:01:07.978052 ==
3967 18:01:07.984828 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3968 18:01:07.991716 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3969 18:01:07.994989 [CA 0] Center 36 (6~67) winsize 62
3970 18:01:07.998128 [CA 1] Center 36 (6~66) winsize 61
3971 18:01:08.001298 [CA 2] Center 34 (4~65) winsize 62
3972 18:01:08.005109 [CA 3] Center 34 (4~65) winsize 62
3973 18:01:08.008248 [CA 4] Center 33 (3~64) winsize 62
3974 18:01:08.011474 [CA 5] Center 33 (3~64) winsize 62
3975 18:01:08.011567
3976 18:01:08.014686 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3977 18:01:08.014767
3978 18:01:08.018301 [CATrainingPosCal] consider 1 rank data
3979 18:01:08.021674 u2DelayCellTimex100 = 270/100 ps
3980 18:01:08.024756 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3981 18:01:08.028300 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3982 18:01:08.031403 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3983 18:01:08.034945 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3984 18:01:08.038021 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3985 18:01:08.041813 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3986 18:01:08.041902
3987 18:01:08.048241 CA PerBit enable=1, Macro0, CA PI delay=33
3988 18:01:08.048336
3989 18:01:08.048409 [CBTSetCACLKResult] CA Dly = 33
3990 18:01:08.052072 CS Dly: 5 (0~36)
3991 18:01:08.052206 ==
3992 18:01:08.055275 Dram Type= 6, Freq= 0, CH_0, rank 1
3993 18:01:08.058460 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3994 18:01:08.058598 ==
3995 18:01:08.065305 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3996 18:01:08.071619 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3997 18:01:08.075065 [CA 0] Center 36 (6~66) winsize 61
3998 18:01:08.078279 [CA 1] Center 36 (6~66) winsize 61
3999 18:01:08.081778 [CA 2] Center 34 (4~65) winsize 62
4000 18:01:08.085360 [CA 3] Center 34 (4~65) winsize 62
4001 18:01:08.088372 [CA 4] Center 33 (3~64) winsize 62
4002 18:01:08.091764 [CA 5] Center 33 (3~64) winsize 62
4003 18:01:08.091866
4004 18:01:08.095429 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4005 18:01:08.095523
4006 18:01:08.098521 [CATrainingPosCal] consider 2 rank data
4007 18:01:08.101665 u2DelayCellTimex100 = 270/100 ps
4008 18:01:08.104796 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4009 18:01:08.108599 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4010 18:01:08.111836 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4011 18:01:08.115050 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4012 18:01:08.118247 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4013 18:01:08.121929 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4014 18:01:08.122006
4015 18:01:08.128018 CA PerBit enable=1, Macro0, CA PI delay=33
4016 18:01:08.128098
4017 18:01:08.128167 [CBTSetCACLKResult] CA Dly = 33
4018 18:01:08.131487 CS Dly: 5 (0~36)
4019 18:01:08.131564
4020 18:01:08.134857 ----->DramcWriteLeveling(PI) begin...
4021 18:01:08.134937 ==
4022 18:01:08.138364 Dram Type= 6, Freq= 0, CH_0, rank 0
4023 18:01:08.141883 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4024 18:01:08.141969 ==
4025 18:01:08.145348 Write leveling (Byte 0): 31 => 31
4026 18:01:08.148440 Write leveling (Byte 1): 28 => 28
4027 18:01:08.151531 DramcWriteLeveling(PI) end<-----
4028 18:01:08.151656
4029 18:01:08.151753 ==
4030 18:01:08.154867 Dram Type= 6, Freq= 0, CH_0, rank 0
4031 18:01:08.158069 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4032 18:01:08.161926 ==
4033 18:01:08.162011 [Gating] SW mode calibration
4034 18:01:08.168198 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4035 18:01:08.174886 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4036 18:01:08.178182 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4037 18:01:08.185144 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4038 18:01:08.188871 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4039 18:01:08.191769 0 9 12 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
4040 18:01:08.198383 0 9 16 | B1->B0 | 3030 2d2d | 1 0 | (1 0) (1 1)
4041 18:01:08.202022 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4042 18:01:08.204954 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4043 18:01:08.208494 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4044 18:01:08.215442 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4045 18:01:08.218634 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4046 18:01:08.221762 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4047 18:01:08.228773 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4048 18:01:08.231986 0 10 16 | B1->B0 | 2f2f 3d3d | 1 0 | (1 1) (0 0)
4049 18:01:08.235126 0 10 20 | B1->B0 | 4545 4646 | 1 0 | (0 0) (0 0)
4050 18:01:08.241986 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4051 18:01:08.245119 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4052 18:01:08.248768 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4053 18:01:08.255052 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4054 18:01:08.258793 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4055 18:01:08.261747 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4056 18:01:08.268274 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4057 18:01:08.272043 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4058 18:01:08.275223 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4059 18:01:08.282224 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4060 18:01:08.285399 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4061 18:01:08.288498 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4062 18:01:08.295379 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4063 18:01:08.298475 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4064 18:01:08.301658 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4065 18:01:08.304861 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4066 18:01:08.311698 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4067 18:01:08.315031 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4068 18:01:08.318546 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4069 18:01:08.324970 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4070 18:01:08.328682 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4071 18:01:08.331520 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4072 18:01:08.338412 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4073 18:01:08.342101 Total UI for P1: 0, mck2ui 16
4074 18:01:08.345096 best dqsien dly found for B0: ( 0, 13, 14)
4075 18:01:08.348780 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4076 18:01:08.351725 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4077 18:01:08.355057 Total UI for P1: 0, mck2ui 16
4078 18:01:08.358782 best dqsien dly found for B1: ( 0, 13, 18)
4079 18:01:08.361850 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4080 18:01:08.364949 best DQS1 dly(MCK, UI, PI) = (0, 13, 18)
4081 18:01:08.365078
4082 18:01:08.372049 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4083 18:01:08.374926 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 18)
4084 18:01:08.375015 [Gating] SW calibration Done
4085 18:01:08.378639 ==
4086 18:01:08.381870 Dram Type= 6, Freq= 0, CH_0, rank 0
4087 18:01:08.384912 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4088 18:01:08.385003 ==
4089 18:01:08.385073 RX Vref Scan: 0
4090 18:01:08.385135
4091 18:01:08.388768 RX Vref 0 -> 0, step: 1
4092 18:01:08.388853
4093 18:01:08.391791 RX Delay -230 -> 252, step: 16
4094 18:01:08.394965 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4095 18:01:08.398718 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4096 18:01:08.404923 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4097 18:01:08.408701 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4098 18:01:08.411852 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4099 18:01:08.414941 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4100 18:01:08.418728 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4101 18:01:08.425317 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4102 18:01:08.428912 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4103 18:01:08.431810 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4104 18:01:08.435367 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4105 18:01:08.441936 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4106 18:01:08.445251 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4107 18:01:08.448390 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4108 18:01:08.452019 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4109 18:01:08.458798 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4110 18:01:08.458883 ==
4111 18:01:08.461815 Dram Type= 6, Freq= 0, CH_0, rank 0
4112 18:01:08.464943 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4113 18:01:08.465038 ==
4114 18:01:08.465106 DQS Delay:
4115 18:01:08.468278 DQS0 = 0, DQS1 = 0
4116 18:01:08.468362 DQM Delay:
4117 18:01:08.471976 DQM0 = 40, DQM1 = 33
4118 18:01:08.472060 DQ Delay:
4119 18:01:08.475146 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =33
4120 18:01:08.478588 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4121 18:01:08.482096 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4122 18:01:08.485660 DQ12 =41, DQ13 =33, DQ14 =49, DQ15 =41
4123 18:01:08.485770
4124 18:01:08.485844
4125 18:01:08.485908 ==
4126 18:01:08.488811 Dram Type= 6, Freq= 0, CH_0, rank 0
4127 18:01:08.491992 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4128 18:01:08.492110 ==
4129 18:01:08.492212
4130 18:01:08.492316
4131 18:01:08.495142 TX Vref Scan disable
4132 18:01:08.498904 == TX Byte 0 ==
4133 18:01:08.502101 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4134 18:01:08.505800 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4135 18:01:08.508941 == TX Byte 1 ==
4136 18:01:08.512162 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4137 18:01:08.515264 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4138 18:01:08.515351 ==
4139 18:01:08.519015 Dram Type= 6, Freq= 0, CH_0, rank 0
4140 18:01:08.522332 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4141 18:01:08.525524 ==
4142 18:01:08.525609
4143 18:01:08.525675
4144 18:01:08.525737 TX Vref Scan disable
4145 18:01:08.529026 == TX Byte 0 ==
4146 18:01:08.532637 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4147 18:01:08.539518 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4148 18:01:08.539606 == TX Byte 1 ==
4149 18:01:08.542608 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4150 18:01:08.549111 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4151 18:01:08.549198
4152 18:01:08.549265 [DATLAT]
4153 18:01:08.549345 Freq=600, CH0 RK0
4154 18:01:08.549409
4155 18:01:08.552573 DATLAT Default: 0x9
4156 18:01:08.552662 0, 0xFFFF, sum = 0
4157 18:01:08.555963 1, 0xFFFF, sum = 0
4158 18:01:08.556049 2, 0xFFFF, sum = 0
4159 18:01:08.559345 3, 0xFFFF, sum = 0
4160 18:01:08.562502 4, 0xFFFF, sum = 0
4161 18:01:08.562589 5, 0xFFFF, sum = 0
4162 18:01:08.566242 6, 0xFFFF, sum = 0
4163 18:01:08.566329 7, 0xFFFF, sum = 0
4164 18:01:08.566398 8, 0x0, sum = 1
4165 18:01:08.569523 9, 0x0, sum = 2
4166 18:01:08.569610 10, 0x0, sum = 3
4167 18:01:08.572470 11, 0x0, sum = 4
4168 18:01:08.572560 best_step = 9
4169 18:01:08.572627
4170 18:01:08.572717 ==
4171 18:01:08.575893 Dram Type= 6, Freq= 0, CH_0, rank 0
4172 18:01:08.582824 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4173 18:01:08.582912 ==
4174 18:01:08.582979 RX Vref Scan: 1
4175 18:01:08.583042
4176 18:01:08.585765 RX Vref 0 -> 0, step: 1
4177 18:01:08.585850
4178 18:01:08.589301 RX Delay -195 -> 252, step: 8
4179 18:01:08.589387
4180 18:01:08.592709 Set Vref, RX VrefLevel [Byte0]: 52
4181 18:01:08.595935 [Byte1]: 52
4182 18:01:08.596027
4183 18:01:08.599122 Final RX Vref Byte 0 = 52 to rank0
4184 18:01:08.602886 Final RX Vref Byte 1 = 52 to rank0
4185 18:01:08.606246 Final RX Vref Byte 0 = 52 to rank1
4186 18:01:08.609077 Final RX Vref Byte 1 = 52 to rank1==
4187 18:01:08.612936 Dram Type= 6, Freq= 0, CH_0, rank 0
4188 18:01:08.616058 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4189 18:01:08.616144 ==
4190 18:01:08.619247 DQS Delay:
4191 18:01:08.619332 DQS0 = 0, DQS1 = 0
4192 18:01:08.619399 DQM Delay:
4193 18:01:08.622995 DQM0 = 42, DQM1 = 34
4194 18:01:08.623079 DQ Delay:
4195 18:01:08.626081 DQ0 =44, DQ1 =40, DQ2 =36, DQ3 =40
4196 18:01:08.629305 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =52
4197 18:01:08.632897 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =32
4198 18:01:08.635861 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =44
4199 18:01:08.635942
4200 18:01:08.636011
4201 18:01:08.646212 [DQSOSCAuto] RK0, (LSB)MR18= 0x4120, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 397 ps
4202 18:01:08.646307 CH0 RK0: MR19=808, MR18=4120
4203 18:01:08.652385 CH0_RK0: MR19=0x808, MR18=0x4120, DQSOSC=397, MR23=63, INC=166, DEC=110
4204 18:01:08.652477
4205 18:01:08.656055 ----->DramcWriteLeveling(PI) begin...
4206 18:01:08.659164 ==
4207 18:01:08.659244 Dram Type= 6, Freq= 0, CH_0, rank 1
4208 18:01:08.666303 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4209 18:01:08.666393 ==
4210 18:01:08.669588 Write leveling (Byte 0): 35 => 35
4211 18:01:08.672800 Write leveling (Byte 1): 29 => 29
4212 18:01:08.672890 DramcWriteLeveling(PI) end<-----
4213 18:01:08.675830
4214 18:01:08.675913 ==
4215 18:01:08.679561 Dram Type= 6, Freq= 0, CH_0, rank 1
4216 18:01:08.682605 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4217 18:01:08.682686 ==
4218 18:01:08.686152 [Gating] SW mode calibration
4219 18:01:08.692720 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4220 18:01:08.695770 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4221 18:01:08.702667 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4222 18:01:08.705814 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4223 18:01:08.709653 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4224 18:01:08.715870 0 9 12 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 1)
4225 18:01:08.719543 0 9 16 | B1->B0 | 3030 2323 | 0 0 | (0 1) (0 0)
4226 18:01:08.722637 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4227 18:01:08.729653 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4228 18:01:08.732824 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4229 18:01:08.735987 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4230 18:01:08.742799 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4231 18:01:08.746226 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4232 18:01:08.749242 0 10 12 | B1->B0 | 2323 2d2c | 0 1 | (0 0) (0 0)
4233 18:01:08.756204 0 10 16 | B1->B0 | 3434 4646 | 0 0 | (0 0) (0 0)
4234 18:01:08.759305 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4235 18:01:08.762500 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4236 18:01:08.766188 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4237 18:01:08.772449 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4238 18:01:08.776145 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4239 18:01:08.779225 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4240 18:01:08.785856 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4241 18:01:08.788920 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4242 18:01:08.792453 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4243 18:01:08.799786 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4244 18:01:08.802456 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4245 18:01:08.805782 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4246 18:01:08.812545 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4247 18:01:08.816149 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4248 18:01:08.819355 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4249 18:01:08.825791 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4250 18:01:08.828862 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4251 18:01:08.831974 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4252 18:01:08.838995 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4253 18:01:08.842043 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4254 18:01:08.845767 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4255 18:01:08.852546 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4256 18:01:08.855905 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4257 18:01:08.859097 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4258 18:01:08.862033 Total UI for P1: 0, mck2ui 16
4259 18:01:08.865354 best dqsien dly found for B0: ( 0, 13, 14)
4260 18:01:08.868969 Total UI for P1: 0, mck2ui 16
4261 18:01:08.872239 best dqsien dly found for B1: ( 0, 13, 14)
4262 18:01:08.875285 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4263 18:01:08.879108 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4264 18:01:08.879226
4265 18:01:08.885320 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4266 18:01:08.889112 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4267 18:01:08.889198 [Gating] SW calibration Done
4268 18:01:08.892044 ==
4269 18:01:08.895451 Dram Type= 6, Freq= 0, CH_0, rank 1
4270 18:01:08.898763 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4271 18:01:08.898849 ==
4272 18:01:08.898915 RX Vref Scan: 0
4273 18:01:08.898976
4274 18:01:08.902032 RX Vref 0 -> 0, step: 1
4275 18:01:08.902144
4276 18:01:08.905526 RX Delay -230 -> 252, step: 16
4277 18:01:08.909052 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4278 18:01:08.912573 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4279 18:01:08.918932 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4280 18:01:08.922536 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4281 18:01:08.925572 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4282 18:01:08.928606 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4283 18:01:08.932432 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4284 18:01:08.938876 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4285 18:01:08.941979 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4286 18:01:08.945897 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4287 18:01:08.948954 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4288 18:01:08.955294 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4289 18:01:08.959106 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4290 18:01:08.962090 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4291 18:01:08.965415 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4292 18:01:08.971895 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4293 18:01:08.971982 ==
4294 18:01:08.975736 Dram Type= 6, Freq= 0, CH_0, rank 1
4295 18:01:08.978957 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4296 18:01:08.979043 ==
4297 18:01:08.979110 DQS Delay:
4298 18:01:08.982615 DQS0 = 0, DQS1 = 0
4299 18:01:08.982700 DQM Delay:
4300 18:01:08.985637 DQM0 = 41, DQM1 = 32
4301 18:01:08.985722 DQ Delay:
4302 18:01:08.988865 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4303 18:01:08.992043 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4304 18:01:08.995845 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =25
4305 18:01:08.998842 DQ12 =33, DQ13 =33, DQ14 =41, DQ15 =41
4306 18:01:08.998927
4307 18:01:08.998994
4308 18:01:08.999055 ==
4309 18:01:09.002292 Dram Type= 6, Freq= 0, CH_0, rank 1
4310 18:01:09.005968 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4311 18:01:09.006071 ==
4312 18:01:09.006145
4313 18:01:09.006208
4314 18:01:09.008764 TX Vref Scan disable
4315 18:01:09.012242 == TX Byte 0 ==
4316 18:01:09.015727 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4317 18:01:09.019262 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4318 18:01:09.022628 == TX Byte 1 ==
4319 18:01:09.025596 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4320 18:01:09.029097 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4321 18:01:09.029208 ==
4322 18:01:09.032136 Dram Type= 6, Freq= 0, CH_0, rank 1
4323 18:01:09.039056 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4324 18:01:09.039146 ==
4325 18:01:09.039214
4326 18:01:09.039276
4327 18:01:09.039336 TX Vref Scan disable
4328 18:01:09.042968 == TX Byte 0 ==
4329 18:01:09.046712 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4330 18:01:09.049835 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4331 18:01:09.053020 == TX Byte 1 ==
4332 18:01:09.056602 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4333 18:01:09.059714 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4334 18:01:09.062827
4335 18:01:09.062910 [DATLAT]
4336 18:01:09.062980 Freq=600, CH0 RK1
4337 18:01:09.063044
4338 18:01:09.066556 DATLAT Default: 0x9
4339 18:01:09.066639 0, 0xFFFF, sum = 0
4340 18:01:09.069596 1, 0xFFFF, sum = 0
4341 18:01:09.069672 2, 0xFFFF, sum = 0
4342 18:01:09.072970 3, 0xFFFF, sum = 0
4343 18:01:09.073056 4, 0xFFFF, sum = 0
4344 18:01:09.076222 5, 0xFFFF, sum = 0
4345 18:01:09.079531 6, 0xFFFF, sum = 0
4346 18:01:09.079611 7, 0xFFFF, sum = 0
4347 18:01:09.079677 8, 0x0, sum = 1
4348 18:01:09.083262 9, 0x0, sum = 2
4349 18:01:09.083352 10, 0x0, sum = 3
4350 18:01:09.086383 11, 0x0, sum = 4
4351 18:01:09.086470 best_step = 9
4352 18:01:09.086534
4353 18:01:09.086594 ==
4354 18:01:09.089524 Dram Type= 6, Freq= 0, CH_0, rank 1
4355 18:01:09.096386 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4356 18:01:09.096472 ==
4357 18:01:09.096539 RX Vref Scan: 0
4358 18:01:09.096610
4359 18:01:09.099530 RX Vref 0 -> 0, step: 1
4360 18:01:09.099645
4361 18:01:09.103252 RX Delay -179 -> 252, step: 8
4362 18:01:09.106228 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4363 18:01:09.112823 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4364 18:01:09.116366 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4365 18:01:09.119326 iDelay=205, Bit 3, Center 36 (-123 ~ 196) 320
4366 18:01:09.123173 iDelay=205, Bit 4, Center 36 (-115 ~ 188) 304
4367 18:01:09.126184 iDelay=205, Bit 5, Center 28 (-123 ~ 180) 304
4368 18:01:09.132985 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4369 18:01:09.136447 iDelay=205, Bit 7, Center 44 (-107 ~ 196) 304
4370 18:01:09.139867 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4371 18:01:09.143356 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4372 18:01:09.146525 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4373 18:01:09.153562 iDelay=205, Bit 11, Center 24 (-123 ~ 172) 296
4374 18:01:09.156644 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4375 18:01:09.159867 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4376 18:01:09.163049 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4377 18:01:09.169830 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4378 18:01:09.169912 ==
4379 18:01:09.172899 Dram Type= 6, Freq= 0, CH_0, rank 1
4380 18:01:09.176598 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4381 18:01:09.176670 ==
4382 18:01:09.176737 DQS Delay:
4383 18:01:09.179690 DQS0 = 0, DQS1 = 0
4384 18:01:09.179774 DQM Delay:
4385 18:01:09.183217 DQM0 = 39, DQM1 = 32
4386 18:01:09.183287 DQ Delay:
4387 18:01:09.186452 DQ0 =40, DQ1 =44, DQ2 =36, DQ3 =36
4388 18:01:09.189871 DQ4 =36, DQ5 =28, DQ6 =48, DQ7 =44
4389 18:01:09.193140 DQ8 =24, DQ9 =24, DQ10 =32, DQ11 =24
4390 18:01:09.196195 DQ12 =36, DQ13 =36, DQ14 =40, DQ15 =40
4391 18:01:09.196283
4392 18:01:09.196348
4393 18:01:09.203289 [DQSOSCAuto] RK1, (LSB)MR18= 0x4326, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 397 ps
4394 18:01:09.206406 CH0 RK1: MR19=808, MR18=4326
4395 18:01:09.213099 CH0_RK1: MR19=0x808, MR18=0x4326, DQSOSC=397, MR23=63, INC=166, DEC=110
4396 18:01:09.216616 [RxdqsGatingPostProcess] freq 600
4397 18:01:09.223336 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4398 18:01:09.226260 Pre-setting of DQS Precalculation
4399 18:01:09.229968 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4400 18:01:09.230053 ==
4401 18:01:09.233123 Dram Type= 6, Freq= 0, CH_1, rank 0
4402 18:01:09.236720 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4403 18:01:09.236837 ==
4404 18:01:09.243263 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4405 18:01:09.249650 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4406 18:01:09.252993 [CA 0] Center 35 (5~66) winsize 62
4407 18:01:09.256641 [CA 1] Center 35 (5~66) winsize 62
4408 18:01:09.259740 [CA 2] Center 34 (4~65) winsize 62
4409 18:01:09.263448 [CA 3] Center 33 (3~64) winsize 62
4410 18:01:09.266683 [CA 4] Center 34 (3~65) winsize 63
4411 18:01:09.269847 [CA 5] Center 33 (2~64) winsize 63
4412 18:01:09.269964
4413 18:01:09.272986 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4414 18:01:09.273071
4415 18:01:09.276759 [CATrainingPosCal] consider 1 rank data
4416 18:01:09.280006 u2DelayCellTimex100 = 270/100 ps
4417 18:01:09.283204 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4418 18:01:09.286390 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4419 18:01:09.289994 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4420 18:01:09.292921 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4421 18:01:09.296480 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4422 18:01:09.299858 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4423 18:01:09.303089
4424 18:01:09.306292 CA PerBit enable=1, Macro0, CA PI delay=33
4425 18:01:09.306377
4426 18:01:09.310095 [CBTSetCACLKResult] CA Dly = 33
4427 18:01:09.310171 CS Dly: 5 (0~36)
4428 18:01:09.310234 ==
4429 18:01:09.313298 Dram Type= 6, Freq= 0, CH_1, rank 1
4430 18:01:09.316358 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4431 18:01:09.316432 ==
4432 18:01:09.322887 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4433 18:01:09.329555 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4434 18:01:09.333143 [CA 0] Center 35 (5~66) winsize 62
4435 18:01:09.336194 [CA 1] Center 36 (6~66) winsize 61
4436 18:01:09.340078 [CA 2] Center 34 (3~65) winsize 63
4437 18:01:09.343284 [CA 3] Center 34 (3~65) winsize 63
4438 18:01:09.346148 [CA 4] Center 34 (3~65) winsize 63
4439 18:01:09.349810 [CA 5] Center 33 (3~64) winsize 62
4440 18:01:09.349900
4441 18:01:09.352853 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4442 18:01:09.352954
4443 18:01:09.356420 [CATrainingPosCal] consider 2 rank data
4444 18:01:09.359878 u2DelayCellTimex100 = 270/100 ps
4445 18:01:09.362723 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4446 18:01:09.366479 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4447 18:01:09.369644 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4448 18:01:09.372767 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4449 18:01:09.376559 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4450 18:01:09.382794 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4451 18:01:09.382884
4452 18:01:09.386602 CA PerBit enable=1, Macro0, CA PI delay=33
4453 18:01:09.386722
4454 18:01:09.389772 [CBTSetCACLKResult] CA Dly = 33
4455 18:01:09.389856 CS Dly: 5 (0~36)
4456 18:01:09.389923
4457 18:01:09.392892 ----->DramcWriteLeveling(PI) begin...
4458 18:01:09.393007 ==
4459 18:01:09.396551 Dram Type= 6, Freq= 0, CH_1, rank 0
4460 18:01:09.399917 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4461 18:01:09.403082 ==
4462 18:01:09.403167 Write leveling (Byte 0): 29 => 29
4463 18:01:09.406572 Write leveling (Byte 1): 31 => 31
4464 18:01:09.410065 DramcWriteLeveling(PI) end<-----
4465 18:01:09.410161
4466 18:01:09.410257 ==
4467 18:01:09.413090 Dram Type= 6, Freq= 0, CH_1, rank 0
4468 18:01:09.419842 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4469 18:01:09.419928 ==
4470 18:01:09.420005 [Gating] SW mode calibration
4471 18:01:09.430001 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4472 18:01:09.433338 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4473 18:01:09.436512 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4474 18:01:09.443213 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4475 18:01:09.446486 0 9 8 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
4476 18:01:09.449601 0 9 12 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 0)
4477 18:01:09.456221 0 9 16 | B1->B0 | 2b2b 2828 | 1 0 | (1 1) (0 0)
4478 18:01:09.459857 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4479 18:01:09.463062 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4480 18:01:09.469950 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4481 18:01:09.472943 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4482 18:01:09.476129 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4483 18:01:09.482973 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4484 18:01:09.486758 0 10 12 | B1->B0 | 2626 2f2f | 0 0 | (0 0) (0 0)
4485 18:01:09.489828 0 10 16 | B1->B0 | 3737 4343 | 0 0 | (0 0) (0 0)
4486 18:01:09.496235 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4487 18:01:09.499955 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4488 18:01:09.503014 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4489 18:01:09.510219 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4490 18:01:09.513243 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4491 18:01:09.516588 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4492 18:01:09.520036 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4493 18:01:09.527019 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4494 18:01:09.530244 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4495 18:01:09.533294 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4496 18:01:09.540178 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4497 18:01:09.543557 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4498 18:01:09.546894 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4499 18:01:09.553522 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4500 18:01:09.556619 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4501 18:01:09.559822 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4502 18:01:09.566231 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4503 18:01:09.569942 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4504 18:01:09.573094 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4505 18:01:09.580085 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4506 18:01:09.583219 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4507 18:01:09.586475 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4508 18:01:09.593412 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4509 18:01:09.596504 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4510 18:01:09.599708 Total UI for P1: 0, mck2ui 16
4511 18:01:09.603574 best dqsien dly found for B0: ( 0, 13, 14)
4512 18:01:09.606561 Total UI for P1: 0, mck2ui 16
4513 18:01:09.610124 best dqsien dly found for B1: ( 0, 13, 14)
4514 18:01:09.613083 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4515 18:01:09.616822 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4516 18:01:09.616929
4517 18:01:09.620020 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4518 18:01:09.622974 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4519 18:01:09.626349 [Gating] SW calibration Done
4520 18:01:09.626460 ==
4521 18:01:09.630180 Dram Type= 6, Freq= 0, CH_1, rank 0
4522 18:01:09.633193 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4523 18:01:09.633300 ==
4524 18:01:09.636352 RX Vref Scan: 0
4525 18:01:09.636441
4526 18:01:09.640155 RX Vref 0 -> 0, step: 1
4527 18:01:09.640277
4528 18:01:09.640380 RX Delay -230 -> 252, step: 16
4529 18:01:09.646332 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4530 18:01:09.649906 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4531 18:01:09.652864 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4532 18:01:09.656694 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4533 18:01:09.662886 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4534 18:01:09.666610 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4535 18:01:09.669577 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4536 18:01:09.673269 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4537 18:01:09.676274 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4538 18:01:09.683180 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4539 18:01:09.686510 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4540 18:01:09.690117 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4541 18:01:09.693158 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4542 18:01:09.699993 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4543 18:01:09.703171 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4544 18:01:09.706247 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4545 18:01:09.706359 ==
4546 18:01:09.710014 Dram Type= 6, Freq= 0, CH_1, rank 0
4547 18:01:09.713074 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4548 18:01:09.713177 ==
4549 18:01:09.716109 DQS Delay:
4550 18:01:09.716209 DQS0 = 0, DQS1 = 0
4551 18:01:09.719739 DQM Delay:
4552 18:01:09.719846 DQM0 = 43, DQM1 = 35
4553 18:01:09.719952 DQ Delay:
4554 18:01:09.722849 DQ0 =41, DQ1 =41, DQ2 =25, DQ3 =41
4555 18:01:09.726609 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4556 18:01:09.729620 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =33
4557 18:01:09.733054 DQ12 =49, DQ13 =41, DQ14 =41, DQ15 =41
4558 18:01:09.733139
4559 18:01:09.733206
4560 18:01:09.736455 ==
4561 18:01:09.739624 Dram Type= 6, Freq= 0, CH_1, rank 0
4562 18:01:09.742815 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4563 18:01:09.742927 ==
4564 18:01:09.743023
4565 18:01:09.743114
4566 18:01:09.746506 TX Vref Scan disable
4567 18:01:09.746616 == TX Byte 0 ==
4568 18:01:09.752791 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4569 18:01:09.756361 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4570 18:01:09.756468 == TX Byte 1 ==
4571 18:01:09.763036 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4572 18:01:09.766524 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4573 18:01:09.766637 ==
4574 18:01:09.769925 Dram Type= 6, Freq= 0, CH_1, rank 0
4575 18:01:09.772881 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4576 18:01:09.772994 ==
4577 18:01:09.773090
4578 18:01:09.773179
4579 18:01:09.776280 TX Vref Scan disable
4580 18:01:09.779504 == TX Byte 0 ==
4581 18:01:09.783196 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4582 18:01:09.786223 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4583 18:01:09.789288 == TX Byte 1 ==
4584 18:01:09.792785 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4585 18:01:09.796205 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4586 18:01:09.796315
4587 18:01:09.799725 [DATLAT]
4588 18:01:09.799836 Freq=600, CH1 RK0
4589 18:01:09.799933
4590 18:01:09.802789 DATLAT Default: 0x9
4591 18:01:09.802897 0, 0xFFFF, sum = 0
4592 18:01:09.806538 1, 0xFFFF, sum = 0
4593 18:01:09.806647 2, 0xFFFF, sum = 0
4594 18:01:09.809756 3, 0xFFFF, sum = 0
4595 18:01:09.809842 4, 0xFFFF, sum = 0
4596 18:01:09.812727 5, 0xFFFF, sum = 0
4597 18:01:09.812836 6, 0xFFFF, sum = 0
4598 18:01:09.816435 7, 0xFFFF, sum = 0
4599 18:01:09.816549 8, 0x0, sum = 1
4600 18:01:09.819519 9, 0x0, sum = 2
4601 18:01:09.819649 10, 0x0, sum = 3
4602 18:01:09.823208 11, 0x0, sum = 4
4603 18:01:09.823318 best_step = 9
4604 18:01:09.823412
4605 18:01:09.823502 ==
4606 18:01:09.826389 Dram Type= 6, Freq= 0, CH_1, rank 0
4607 18:01:09.829663 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4608 18:01:09.829775 ==
4609 18:01:09.832816 RX Vref Scan: 1
4610 18:01:09.832920
4611 18:01:09.836604 RX Vref 0 -> 0, step: 1
4612 18:01:09.836715
4613 18:01:09.836819 RX Delay -195 -> 252, step: 8
4614 18:01:09.839566
4615 18:01:09.839679 Set Vref, RX VrefLevel [Byte0]: 60
4616 18:01:09.842981 [Byte1]: 52
4617 18:01:09.847966
4618 18:01:09.848074 Final RX Vref Byte 0 = 60 to rank0
4619 18:01:09.851128 Final RX Vref Byte 1 = 52 to rank0
4620 18:01:09.854338 Final RX Vref Byte 0 = 60 to rank1
4621 18:01:09.858062 Final RX Vref Byte 1 = 52 to rank1==
4622 18:01:09.861035 Dram Type= 6, Freq= 0, CH_1, rank 0
4623 18:01:09.867847 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4624 18:01:09.867966 ==
4625 18:01:09.868063 DQS Delay:
4626 18:01:09.868153 DQS0 = 0, DQS1 = 0
4627 18:01:09.870917 DQM Delay:
4628 18:01:09.871027 DQM0 = 40, DQM1 = 32
4629 18:01:09.874539 DQ Delay:
4630 18:01:09.877579 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =40
4631 18:01:09.880860 DQ4 =40, DQ5 =48, DQ6 =52, DQ7 =36
4632 18:01:09.884501 DQ8 =20, DQ9 =24, DQ10 =32, DQ11 =24
4633 18:01:09.887387 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4634 18:01:09.887493
4635 18:01:09.887587
4636 18:01:09.894122 [DQSOSCAuto] RK0, (LSB)MR18= 0x4208, (MSB)MR19= 0x808, tDQSOscB0 = 408 ps tDQSOscB1 = 397 ps
4637 18:01:09.897913 CH1 RK0: MR19=808, MR18=4208
4638 18:01:09.904250 CH1_RK0: MR19=0x808, MR18=0x4208, DQSOSC=397, MR23=63, INC=166, DEC=110
4639 18:01:09.904358
4640 18:01:09.907589 ----->DramcWriteLeveling(PI) begin...
4641 18:01:09.907697 ==
4642 18:01:09.910652 Dram Type= 6, Freq= 0, CH_1, rank 1
4643 18:01:09.914469 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4644 18:01:09.914561 ==
4645 18:01:09.917471 Write leveling (Byte 0): 32 => 32
4646 18:01:09.920619 Write leveling (Byte 1): 31 => 31
4647 18:01:09.924286 DramcWriteLeveling(PI) end<-----
4648 18:01:09.924392
4649 18:01:09.924485 ==
4650 18:01:09.927372 Dram Type= 6, Freq= 0, CH_1, rank 1
4651 18:01:09.931088 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4652 18:01:09.931207 ==
4653 18:01:09.934239 [Gating] SW mode calibration
4654 18:01:09.941089 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4655 18:01:09.947269 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4656 18:01:09.950465 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4657 18:01:09.957147 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4658 18:01:09.961010 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4659 18:01:09.964092 0 9 12 | B1->B0 | 3232 2828 | 0 1 | (0 0) (1 0)
4660 18:01:09.967068 0 9 16 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
4661 18:01:09.973876 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4662 18:01:09.977393 0 9 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4663 18:01:09.980488 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4664 18:01:09.987215 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4665 18:01:09.990395 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4666 18:01:09.994140 0 10 8 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
4667 18:01:10.000653 0 10 12 | B1->B0 | 3333 3939 | 0 0 | (0 0) (0 0)
4668 18:01:10.004079 0 10 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4669 18:01:10.006929 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4670 18:01:10.013861 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4671 18:01:10.017526 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4672 18:01:10.020528 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4673 18:01:10.027378 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4674 18:01:10.030399 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4675 18:01:10.034225 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4676 18:01:10.040478 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4677 18:01:10.043582 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4678 18:01:10.047450 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4679 18:01:10.053605 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4680 18:01:10.056936 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4681 18:01:10.060395 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4682 18:01:10.067119 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4683 18:01:10.070841 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4684 18:01:10.073913 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4685 18:01:10.077554 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4686 18:01:10.083753 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4687 18:01:10.087266 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4688 18:01:10.090472 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4689 18:01:10.097558 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4690 18:01:10.100542 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4691 18:01:10.104352 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4692 18:01:10.107303 Total UI for P1: 0, mck2ui 16
4693 18:01:10.110731 best dqsien dly found for B0: ( 0, 13, 10)
4694 18:01:10.114132 Total UI for P1: 0, mck2ui 16
4695 18:01:10.117482 best dqsien dly found for B1: ( 0, 13, 10)
4696 18:01:10.120524 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4697 18:01:10.123932 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4698 18:01:10.124018
4699 18:01:10.130634 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4700 18:01:10.134346 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4701 18:01:10.137311 [Gating] SW calibration Done
4702 18:01:10.137396 ==
4703 18:01:10.140453 Dram Type= 6, Freq= 0, CH_1, rank 1
4704 18:01:10.144231 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4705 18:01:10.144319 ==
4706 18:01:10.144387 RX Vref Scan: 0
4707 18:01:10.144448
4708 18:01:10.147369 RX Vref 0 -> 0, step: 1
4709 18:01:10.147454
4710 18:01:10.150547 RX Delay -230 -> 252, step: 16
4711 18:01:10.153700 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4712 18:01:10.157432 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4713 18:01:10.164294 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4714 18:01:10.167067 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4715 18:01:10.170285 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4716 18:01:10.174080 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4717 18:01:10.180767 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4718 18:01:10.183839 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4719 18:01:10.187634 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4720 18:01:10.190640 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4721 18:01:10.194129 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4722 18:01:10.200269 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4723 18:01:10.204011 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4724 18:01:10.207044 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4725 18:01:10.210765 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4726 18:01:10.217362 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4727 18:01:10.217455 ==
4728 18:01:10.220408 Dram Type= 6, Freq= 0, CH_1, rank 1
4729 18:01:10.223875 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4730 18:01:10.223960 ==
4731 18:01:10.224027 DQS Delay:
4732 18:01:10.227103 DQS0 = 0, DQS1 = 0
4733 18:01:10.227188 DQM Delay:
4734 18:01:10.230512 DQM0 = 42, DQM1 = 36
4735 18:01:10.230597 DQ Delay:
4736 18:01:10.233995 DQ0 =41, DQ1 =33, DQ2 =25, DQ3 =41
4737 18:01:10.236967 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4738 18:01:10.240789 DQ8 =17, DQ9 =25, DQ10 =41, DQ11 =25
4739 18:01:10.244056 DQ12 =41, DQ13 =49, DQ14 =41, DQ15 =49
4740 18:01:10.244148
4741 18:01:10.244244
4742 18:01:10.244349 ==
4743 18:01:10.247262 Dram Type= 6, Freq= 0, CH_1, rank 1
4744 18:01:10.250304 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4745 18:01:10.250390 ==
4746 18:01:10.250458
4747 18:01:10.250520
4748 18:01:10.254074 TX Vref Scan disable
4749 18:01:10.257264 == TX Byte 0 ==
4750 18:01:10.260379 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4751 18:01:10.263637 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4752 18:01:10.267640 == TX Byte 1 ==
4753 18:01:10.270644 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4754 18:01:10.274047 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4755 18:01:10.274134 ==
4756 18:01:10.277385 Dram Type= 6, Freq= 0, CH_1, rank 1
4757 18:01:10.284078 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4758 18:01:10.284166 ==
4759 18:01:10.284266
4760 18:01:10.284364
4761 18:01:10.284459 TX Vref Scan disable
4762 18:01:10.288505 == TX Byte 0 ==
4763 18:01:10.291623 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4764 18:01:10.298011 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4765 18:01:10.298100 == TX Byte 1 ==
4766 18:01:10.301637 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4767 18:01:10.305181 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4768 18:01:10.308199
4769 18:01:10.308279 [DATLAT]
4770 18:01:10.308345 Freq=600, CH1 RK1
4771 18:01:10.308407
4772 18:01:10.311366 DATLAT Default: 0x9
4773 18:01:10.311451 0, 0xFFFF, sum = 0
4774 18:01:10.315147 1, 0xFFFF, sum = 0
4775 18:01:10.315253 2, 0xFFFF, sum = 0
4776 18:01:10.318273 3, 0xFFFF, sum = 0
4777 18:01:10.318359 4, 0xFFFF, sum = 0
4778 18:01:10.321294 5, 0xFFFF, sum = 0
4779 18:01:10.325058 6, 0xFFFF, sum = 0
4780 18:01:10.325149 7, 0xFFFF, sum = 0
4781 18:01:10.325219 8, 0x0, sum = 1
4782 18:01:10.328072 9, 0x0, sum = 2
4783 18:01:10.328157 10, 0x0, sum = 3
4784 18:01:10.331663 11, 0x0, sum = 4
4785 18:01:10.331749 best_step = 9
4786 18:01:10.331816
4787 18:01:10.331878 ==
4788 18:01:10.334563 Dram Type= 6, Freq= 0, CH_1, rank 1
4789 18:01:10.341578 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4790 18:01:10.341671 ==
4791 18:01:10.341740 RX Vref Scan: 0
4792 18:01:10.341803
4793 18:01:10.344570 RX Vref 0 -> 0, step: 1
4794 18:01:10.344655
4795 18:01:10.348042 RX Delay -195 -> 252, step: 8
4796 18:01:10.351142 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4797 18:01:10.358022 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4798 18:01:10.361263 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4799 18:01:10.364999 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4800 18:01:10.368039 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312
4801 18:01:10.371367 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4802 18:01:10.378198 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4803 18:01:10.381363 iDelay=205, Bit 7, Center 32 (-115 ~ 180) 296
4804 18:01:10.385002 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4805 18:01:10.388031 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4806 18:01:10.394452 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4807 18:01:10.398200 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4808 18:01:10.401430 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4809 18:01:10.404476 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4810 18:01:10.411583 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4811 18:01:10.414884 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4812 18:01:10.414971 ==
4813 18:01:10.418040 Dram Type= 6, Freq= 0, CH_1, rank 1
4814 18:01:10.421123 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4815 18:01:10.421210 ==
4816 18:01:10.421278 DQS Delay:
4817 18:01:10.424610 DQS0 = 0, DQS1 = 0
4818 18:01:10.424721 DQM Delay:
4819 18:01:10.428271 DQM0 = 37, DQM1 = 34
4820 18:01:10.428358 DQ Delay:
4821 18:01:10.431239 DQ0 =40, DQ1 =32, DQ2 =24, DQ3 =36
4822 18:01:10.434964 DQ4 =40, DQ5 =48, DQ6 =48, DQ7 =32
4823 18:01:10.438050 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =24
4824 18:01:10.441852 DQ12 =44, DQ13 =40, DQ14 =44, DQ15 =40
4825 18:01:10.441940
4826 18:01:10.442008
4827 18:01:10.451335 [DQSOSCAuto] RK1, (LSB)MR18= 0x3a48, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 398 ps
4828 18:01:10.451422 CH1 RK1: MR19=808, MR18=3A48
4829 18:01:10.458418 CH1_RK1: MR19=0x808, MR18=0x3A48, DQSOSC=396, MR23=63, INC=167, DEC=111
4830 18:01:10.461588 [RxdqsGatingPostProcess] freq 600
4831 18:01:10.468303 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4832 18:01:10.471420 Pre-setting of DQS Precalculation
4833 18:01:10.475184 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4834 18:01:10.481408 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4835 18:01:10.488405 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4836 18:01:10.488495
4837 18:01:10.488585
4838 18:01:10.491705 [Calibration Summary] 1200 Mbps
4839 18:01:10.494861 CH 0, Rank 0
4840 18:01:10.494946 SW Impedance : PASS
4841 18:01:10.498354 DUTY Scan : NO K
4842 18:01:10.501714 ZQ Calibration : PASS
4843 18:01:10.501799 Jitter Meter : NO K
4844 18:01:10.504842 CBT Training : PASS
4845 18:01:10.508121 Write leveling : PASS
4846 18:01:10.508206 RX DQS gating : PASS
4847 18:01:10.511823 RX DQ/DQS(RDDQC) : PASS
4848 18:01:10.514705 TX DQ/DQS : PASS
4849 18:01:10.514793 RX DATLAT : PASS
4850 18:01:10.518316 RX DQ/DQS(Engine): PASS
4851 18:01:10.518401 TX OE : NO K
4852 18:01:10.521604 All Pass.
4853 18:01:10.521688
4854 18:01:10.521754 CH 0, Rank 1
4855 18:01:10.524856 SW Impedance : PASS
4856 18:01:10.524983 DUTY Scan : NO K
4857 18:01:10.528002 ZQ Calibration : PASS
4858 18:01:10.531620 Jitter Meter : NO K
4859 18:01:10.531707 CBT Training : PASS
4860 18:01:10.534564 Write leveling : PASS
4861 18:01:10.538279 RX DQS gating : PASS
4862 18:01:10.538367 RX DQ/DQS(RDDQC) : PASS
4863 18:01:10.541509 TX DQ/DQS : PASS
4864 18:01:10.544666 RX DATLAT : PASS
4865 18:01:10.544778 RX DQ/DQS(Engine): PASS
4866 18:01:10.548358 TX OE : NO K
4867 18:01:10.548443 All Pass.
4868 18:01:10.548510
4869 18:01:10.551478 CH 1, Rank 0
4870 18:01:10.551588 SW Impedance : PASS
4871 18:01:10.554581 DUTY Scan : NO K
4872 18:01:10.558297 ZQ Calibration : PASS
4873 18:01:10.558408 Jitter Meter : NO K
4874 18:01:10.561497 CBT Training : PASS
4875 18:01:10.561582 Write leveling : PASS
4876 18:01:10.564924 RX DQS gating : PASS
4877 18:01:10.568478 RX DQ/DQS(RDDQC) : PASS
4878 18:01:10.568587 TX DQ/DQS : PASS
4879 18:01:10.571301 RX DATLAT : PASS
4880 18:01:10.574746 RX DQ/DQS(Engine): PASS
4881 18:01:10.574853 TX OE : NO K
4882 18:01:10.578062 All Pass.
4883 18:01:10.578165
4884 18:01:10.578266 CH 1, Rank 1
4885 18:01:10.581836 SW Impedance : PASS
4886 18:01:10.581949 DUTY Scan : NO K
4887 18:01:10.584963 ZQ Calibration : PASS
4888 18:01:10.588069 Jitter Meter : NO K
4889 18:01:10.588174 CBT Training : PASS
4890 18:01:10.591781 Write leveling : PASS
4891 18:01:10.594926 RX DQS gating : PASS
4892 18:01:10.595036 RX DQ/DQS(RDDQC) : PASS
4893 18:01:10.598741 TX DQ/DQS : PASS
4894 18:01:10.598848 RX DATLAT : PASS
4895 18:01:10.601844 RX DQ/DQS(Engine): PASS
4896 18:01:10.605027 TX OE : NO K
4897 18:01:10.605109 All Pass.
4898 18:01:10.605181
4899 18:01:10.608072 DramC Write-DBI off
4900 18:01:10.608167 PER_BANK_REFRESH: Hybrid Mode
4901 18:01:10.611637 TX_TRACKING: ON
4902 18:01:10.618245 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4903 18:01:10.625099 [FAST_K] Save calibration result to emmc
4904 18:01:10.628683 dramc_set_vcore_voltage set vcore to 662500
4905 18:01:10.628789 Read voltage for 933, 3
4906 18:01:10.631751 Vio18 = 0
4907 18:01:10.631852 Vcore = 662500
4908 18:01:10.631947 Vdram = 0
4909 18:01:10.635603 Vddq = 0
4910 18:01:10.635688 Vmddr = 0
4911 18:01:10.638575 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4912 18:01:10.645289 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4913 18:01:10.648520 MEM_TYPE=3, freq_sel=17
4914 18:01:10.652173 sv_algorithm_assistance_LP4_1600
4915 18:01:10.655388 ============ PULL DRAM RESETB DOWN ============
4916 18:01:10.658564 ========== PULL DRAM RESETB DOWN end =========
4917 18:01:10.661696 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4918 18:01:10.665642 ===================================
4919 18:01:10.668730 LPDDR4 DRAM CONFIGURATION
4920 18:01:10.671788 ===================================
4921 18:01:10.675384 EX_ROW_EN[0] = 0x0
4922 18:01:10.675487 EX_ROW_EN[1] = 0x0
4923 18:01:10.678550 LP4Y_EN = 0x0
4924 18:01:10.678649 WORK_FSP = 0x0
4925 18:01:10.682145 WL = 0x3
4926 18:01:10.682244 RL = 0x3
4927 18:01:10.685107 BL = 0x2
4928 18:01:10.685180 RPST = 0x0
4929 18:01:10.688524 RD_PRE = 0x0
4930 18:01:10.688628 WR_PRE = 0x1
4931 18:01:10.691963 WR_PST = 0x0
4932 18:01:10.692068 DBI_WR = 0x0
4933 18:01:10.695291 DBI_RD = 0x0
4934 18:01:10.695399 OTF = 0x1
4935 18:01:10.699081 ===================================
4936 18:01:10.702228 ===================================
4937 18:01:10.705345 ANA top config
4938 18:01:10.708508 ===================================
4939 18:01:10.711673 DLL_ASYNC_EN = 0
4940 18:01:10.711776 ALL_SLAVE_EN = 1
4941 18:01:10.715520 NEW_RANK_MODE = 1
4942 18:01:10.718567 DLL_IDLE_MODE = 1
4943 18:01:10.721599 LP45_APHY_COMB_EN = 1
4944 18:01:10.725173 TX_ODT_DIS = 1
4945 18:01:10.725282 NEW_8X_MODE = 1
4946 18:01:10.728734 ===================================
4947 18:01:10.732024 ===================================
4948 18:01:10.735535 data_rate = 1866
4949 18:01:10.738447 CKR = 1
4950 18:01:10.742156 DQ_P2S_RATIO = 8
4951 18:01:10.745125 ===================================
4952 18:01:10.748600 CA_P2S_RATIO = 8
4953 18:01:10.748713 DQ_CA_OPEN = 0
4954 18:01:10.751892 DQ_SEMI_OPEN = 0
4955 18:01:10.754972 CA_SEMI_OPEN = 0
4956 18:01:10.758837 CA_FULL_RATE = 0
4957 18:01:10.761914 DQ_CKDIV4_EN = 1
4958 18:01:10.765059 CA_CKDIV4_EN = 1
4959 18:01:10.765136 CA_PREDIV_EN = 0
4960 18:01:10.768846 PH8_DLY = 0
4961 18:01:10.771938 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4962 18:01:10.775197 DQ_AAMCK_DIV = 4
4963 18:01:10.778831 CA_AAMCK_DIV = 4
4964 18:01:10.781949 CA_ADMCK_DIV = 4
4965 18:01:10.782054 DQ_TRACK_CA_EN = 0
4966 18:01:10.785077 CA_PICK = 933
4967 18:01:10.788842 CA_MCKIO = 933
4968 18:01:10.791954 MCKIO_SEMI = 0
4969 18:01:10.794999 PLL_FREQ = 3732
4970 18:01:10.798668 DQ_UI_PI_RATIO = 32
4971 18:01:10.802025 CA_UI_PI_RATIO = 0
4972 18:01:10.805359 ===================================
4973 18:01:10.805463 ===================================
4974 18:01:10.808902 memory_type:LPDDR4
4975 18:01:10.812059 GP_NUM : 10
4976 18:01:10.812166 SRAM_EN : 1
4977 18:01:10.815247 MD32_EN : 0
4978 18:01:10.818365 ===================================
4979 18:01:10.822127 [ANA_INIT] >>>>>>>>>>>>>>
4980 18:01:10.825246 <<<<<< [CONFIGURE PHASE]: ANA_TX
4981 18:01:10.828818 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4982 18:01:10.832004 ===================================
4983 18:01:10.832106 data_rate = 1866,PCW = 0X8f00
4984 18:01:10.835636 ===================================
4985 18:01:10.838555 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4986 18:01:10.845012 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4987 18:01:10.851925 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4988 18:01:10.855557 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4989 18:01:10.858790 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4990 18:01:10.862075 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4991 18:01:10.865120 [ANA_INIT] flow start
4992 18:01:10.865208 [ANA_INIT] PLL >>>>>>>>
4993 18:01:10.868836 [ANA_INIT] PLL <<<<<<<<
4994 18:01:10.871983 [ANA_INIT] MIDPI >>>>>>>>
4995 18:01:10.875150 [ANA_INIT] MIDPI <<<<<<<<
4996 18:01:10.875260 [ANA_INIT] DLL >>>>>>>>
4997 18:01:10.878919 [ANA_INIT] flow end
4998 18:01:10.881949 ============ LP4 DIFF to SE enter ============
4999 18:01:10.885627 ============ LP4 DIFF to SE exit ============
5000 18:01:10.888705 [ANA_INIT] <<<<<<<<<<<<<
5001 18:01:10.891919 [Flow] Enable top DCM control >>>>>
5002 18:01:10.895690 [Flow] Enable top DCM control <<<<<
5003 18:01:10.898702 Enable DLL master slave shuffle
5004 18:01:10.905378 ==============================================================
5005 18:01:10.905484 Gating Mode config
5006 18:01:10.911977 ==============================================================
5007 18:01:10.912080 Config description:
5008 18:01:10.922721 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5009 18:01:10.928807 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5010 18:01:10.935493 SELPH_MODE 0: By rank 1: By Phase
5011 18:01:10.938757 ==============================================================
5012 18:01:10.941845 GAT_TRACK_EN = 1
5013 18:01:10.945471 RX_GATING_MODE = 2
5014 18:01:10.948986 RX_GATING_TRACK_MODE = 2
5015 18:01:10.951962 SELPH_MODE = 1
5016 18:01:10.955417 PICG_EARLY_EN = 1
5017 18:01:10.958898 VALID_LAT_VALUE = 1
5018 18:01:10.962344 ==============================================================
5019 18:01:10.965620 Enter into Gating configuration >>>>
5020 18:01:10.968684 Exit from Gating configuration <<<<
5021 18:01:10.972488 Enter into DVFS_PRE_config >>>>>
5022 18:01:10.985580 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5023 18:01:10.985699 Exit from DVFS_PRE_config <<<<<
5024 18:01:10.988665 Enter into PICG configuration >>>>
5025 18:01:10.992345 Exit from PICG configuration <<<<
5026 18:01:10.995565 [RX_INPUT] configuration >>>>>
5027 18:01:10.998713 [RX_INPUT] configuration <<<<<
5028 18:01:11.005660 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5029 18:01:11.008757 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5030 18:01:11.015376 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5031 18:01:11.022040 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5032 18:01:11.028345 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5033 18:01:11.035145 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5034 18:01:11.038241 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5035 18:01:11.042026 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5036 18:01:11.045073 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5037 18:01:11.051874 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5038 18:01:11.054729 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5039 18:01:11.058296 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5040 18:01:11.062082 ===================================
5041 18:01:11.065197 LPDDR4 DRAM CONFIGURATION
5042 18:01:11.068723 ===================================
5043 18:01:11.068828 EX_ROW_EN[0] = 0x0
5044 18:01:11.071740 EX_ROW_EN[1] = 0x0
5045 18:01:11.075211 LP4Y_EN = 0x0
5046 18:01:11.075324 WORK_FSP = 0x0
5047 18:01:11.078519 WL = 0x3
5048 18:01:11.078623 RL = 0x3
5049 18:01:11.081792 BL = 0x2
5050 18:01:11.081897 RPST = 0x0
5051 18:01:11.085072 RD_PRE = 0x0
5052 18:01:11.085176 WR_PRE = 0x1
5053 18:01:11.088577 WR_PST = 0x0
5054 18:01:11.088680 DBI_WR = 0x0
5055 18:01:11.092305 DBI_RD = 0x0
5056 18:01:11.092410 OTF = 0x1
5057 18:01:11.095471 ===================================
5058 18:01:11.098818 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5059 18:01:11.105461 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5060 18:01:11.108712 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5061 18:01:11.111777 ===================================
5062 18:01:11.115473 LPDDR4 DRAM CONFIGURATION
5063 18:01:11.118459 ===================================
5064 18:01:11.118570 EX_ROW_EN[0] = 0x10
5065 18:01:11.122205 EX_ROW_EN[1] = 0x0
5066 18:01:11.122322 LP4Y_EN = 0x0
5067 18:01:11.125268 WORK_FSP = 0x0
5068 18:01:11.125368 WL = 0x3
5069 18:01:11.128966 RL = 0x3
5070 18:01:11.129082 BL = 0x2
5071 18:01:11.132121 RPST = 0x0
5072 18:01:11.135231 RD_PRE = 0x0
5073 18:01:11.135337 WR_PRE = 0x1
5074 18:01:11.138823 WR_PST = 0x0
5075 18:01:11.138936 DBI_WR = 0x0
5076 18:01:11.141866 DBI_RD = 0x0
5077 18:01:11.141970 OTF = 0x1
5078 18:01:11.145601 ===================================
5079 18:01:11.151875 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5080 18:01:11.155562 nWR fixed to 30
5081 18:01:11.158674 [ModeRegInit_LP4] CH0 RK0
5082 18:01:11.158777 [ModeRegInit_LP4] CH0 RK1
5083 18:01:11.162215 [ModeRegInit_LP4] CH1 RK0
5084 18:01:11.165356 [ModeRegInit_LP4] CH1 RK1
5085 18:01:11.165432 match AC timing 9
5086 18:01:11.172210 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5087 18:01:11.175458 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5088 18:01:11.179270 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5089 18:01:11.185486 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5090 18:01:11.189094 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5091 18:01:11.189185 ==
5092 18:01:11.192469 Dram Type= 6, Freq= 0, CH_0, rank 0
5093 18:01:11.195304 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5094 18:01:11.195414 ==
5095 18:01:11.202122 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5096 18:01:11.208953 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5097 18:01:11.212166 [CA 0] Center 38 (8~69) winsize 62
5098 18:01:11.215856 [CA 1] Center 38 (8~69) winsize 62
5099 18:01:11.218899 [CA 2] Center 35 (5~66) winsize 62
5100 18:01:11.222492 [CA 3] Center 35 (5~66) winsize 62
5101 18:01:11.225303 [CA 4] Center 34 (4~64) winsize 61
5102 18:01:11.229044 [CA 5] Center 34 (4~64) winsize 61
5103 18:01:11.229121
5104 18:01:11.232273 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5105 18:01:11.232350
5106 18:01:11.235852 [CATrainingPosCal] consider 1 rank data
5107 18:01:11.238933 u2DelayCellTimex100 = 270/100 ps
5108 18:01:11.241930 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5109 18:01:11.245542 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5110 18:01:11.248851 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5111 18:01:11.251940 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
5112 18:01:11.255802 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5113 18:01:11.258912 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5114 18:01:11.259013
5115 18:01:11.265740 CA PerBit enable=1, Macro0, CA PI delay=34
5116 18:01:11.265847
5117 18:01:11.265954 [CBTSetCACLKResult] CA Dly = 34
5118 18:01:11.268745 CS Dly: 6 (0~37)
5119 18:01:11.268849 ==
5120 18:01:11.272470 Dram Type= 6, Freq= 0, CH_0, rank 1
5121 18:01:11.275594 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5122 18:01:11.275700 ==
5123 18:01:11.281906 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5124 18:01:11.288780 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5125 18:01:11.291886 [CA 0] Center 38 (7~69) winsize 63
5126 18:01:11.295820 [CA 1] Center 38 (7~69) winsize 63
5127 18:01:11.298900 [CA 2] Center 35 (5~66) winsize 62
5128 18:01:11.301962 [CA 3] Center 35 (5~65) winsize 61
5129 18:01:11.305637 [CA 4] Center 34 (3~65) winsize 63
5130 18:01:11.308706 [CA 5] Center 33 (3~64) winsize 62
5131 18:01:11.308786
5132 18:01:11.312226 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5133 18:01:11.312305
5134 18:01:11.315702 [CATrainingPosCal] consider 2 rank data
5135 18:01:11.318994 u2DelayCellTimex100 = 270/100 ps
5136 18:01:11.322400 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5137 18:01:11.325516 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5138 18:01:11.328866 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5139 18:01:11.332219 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5140 18:01:11.335861 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5141 18:01:11.338806 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5142 18:01:11.338887
5143 18:01:11.345696 CA PerBit enable=1, Macro0, CA PI delay=34
5144 18:01:11.345789
5145 18:01:11.345857 [CBTSetCACLKResult] CA Dly = 34
5146 18:01:11.348745 CS Dly: 7 (0~39)
5147 18:01:11.348848
5148 18:01:11.351839 ----->DramcWriteLeveling(PI) begin...
5149 18:01:11.351946 ==
5150 18:01:11.355444 Dram Type= 6, Freq= 0, CH_0, rank 0
5151 18:01:11.358700 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5152 18:01:11.358813 ==
5153 18:01:11.362393 Write leveling (Byte 0): 31 => 31
5154 18:01:11.365553 Write leveling (Byte 1): 26 => 26
5155 18:01:11.368675 DramcWriteLeveling(PI) end<-----
5156 18:01:11.368777
5157 18:01:11.368871 ==
5158 18:01:11.372265 Dram Type= 6, Freq= 0, CH_0, rank 0
5159 18:01:11.375258 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5160 18:01:11.378811 ==
5161 18:01:11.378919 [Gating] SW mode calibration
5162 18:01:11.385166 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5163 18:01:11.391981 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5164 18:01:11.395746 0 14 0 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (1 1)
5165 18:01:11.401921 0 14 4 | B1->B0 | 2d2c 3434 | 1 1 | (0 0) (1 1)
5166 18:01:11.405221 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5167 18:01:11.408625 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5168 18:01:11.415589 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5169 18:01:11.418677 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5170 18:01:11.421780 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5171 18:01:11.428842 0 14 28 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
5172 18:01:11.431710 0 15 0 | B1->B0 | 3434 2727 | 0 0 | (0 0) (0 0)
5173 18:01:11.435099 0 15 4 | B1->B0 | 2828 2323 | 0 0 | (1 0) (0 0)
5174 18:01:11.441620 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5175 18:01:11.445439 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5176 18:01:11.448486 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5177 18:01:11.455366 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5178 18:01:11.458598 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5179 18:01:11.461693 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5180 18:01:11.465495 1 0 0 | B1->B0 | 3333 4040 | 0 0 | (0 0) (0 0)
5181 18:01:11.471608 1 0 4 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
5182 18:01:11.475340 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5183 18:01:11.478297 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5184 18:01:11.485527 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5185 18:01:11.488562 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5186 18:01:11.491823 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5187 18:01:11.498582 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5188 18:01:11.501854 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5189 18:01:11.505633 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5190 18:01:11.511765 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5191 18:01:11.515451 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5192 18:01:11.518530 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5193 18:01:11.524921 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5194 18:01:11.528582 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5195 18:01:11.531553 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5196 18:01:11.538529 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5197 18:01:11.541604 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5198 18:01:11.544758 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5199 18:01:11.551363 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5200 18:01:11.554989 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5201 18:01:11.558279 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5202 18:01:11.565048 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5203 18:01:11.568381 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5204 18:01:11.571575 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5205 18:01:11.578325 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5206 18:01:11.578440 Total UI for P1: 0, mck2ui 16
5207 18:01:11.581491 best dqsien dly found for B0: ( 1, 3, 0)
5208 18:01:11.585137 Total UI for P1: 0, mck2ui 16
5209 18:01:11.588194 best dqsien dly found for B1: ( 1, 3, 0)
5210 18:01:11.591555 best DQS0 dly(MCK, UI, PI) = (1, 3, 0)
5211 18:01:11.595237 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5212 18:01:11.595346
5213 18:01:11.601349 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 0)
5214 18:01:11.605143 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5215 18:01:11.608351 [Gating] SW calibration Done
5216 18:01:11.608451 ==
5217 18:01:11.611445 Dram Type= 6, Freq= 0, CH_0, rank 0
5218 18:01:11.615225 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5219 18:01:11.615328 ==
5220 18:01:11.615422 RX Vref Scan: 0
5221 18:01:11.615522
5222 18:01:11.618171 RX Vref 0 -> 0, step: 1
5223 18:01:11.618284
5224 18:01:11.621880 RX Delay -80 -> 252, step: 8
5225 18:01:11.625081 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5226 18:01:11.628354 iDelay=200, Bit 1, Center 99 (0 ~ 199) 200
5227 18:01:11.631528 iDelay=200, Bit 2, Center 95 (0 ~ 191) 192
5228 18:01:11.635126 iDelay=200, Bit 3, Center 91 (-8 ~ 191) 200
5229 18:01:11.642137 iDelay=200, Bit 4, Center 99 (0 ~ 199) 200
5230 18:01:11.645136 iDelay=200, Bit 5, Center 87 (-8 ~ 183) 192
5231 18:01:11.648277 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5232 18:01:11.651921 iDelay=200, Bit 7, Center 103 (8 ~ 199) 192
5233 18:01:11.655044 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5234 18:01:11.661906 iDelay=200, Bit 9, Center 75 (-16 ~ 167) 184
5235 18:01:11.665425 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5236 18:01:11.668275 iDelay=200, Bit 11, Center 79 (-16 ~ 175) 192
5237 18:01:11.671938 iDelay=200, Bit 12, Center 91 (-8 ~ 191) 200
5238 18:01:11.674978 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5239 18:01:11.678604 iDelay=200, Bit 14, Center 99 (8 ~ 191) 184
5240 18:01:11.685272 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5241 18:01:11.685361 ==
5242 18:01:11.688514 Dram Type= 6, Freq= 0, CH_0, rank 0
5243 18:01:11.691976 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5244 18:01:11.692062 ==
5245 18:01:11.692130 DQS Delay:
5246 18:01:11.695040 DQS0 = 0, DQS1 = 0
5247 18:01:11.695125 DQM Delay:
5248 18:01:11.698335 DQM0 = 97, DQM1 = 87
5249 18:01:11.698421 DQ Delay:
5250 18:01:11.701805 DQ0 =95, DQ1 =99, DQ2 =95, DQ3 =91
5251 18:01:11.705500 DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =103
5252 18:01:11.708674 DQ8 =79, DQ9 =75, DQ10 =87, DQ11 =79
5253 18:01:11.711981 DQ12 =91, DQ13 =95, DQ14 =99, DQ15 =95
5254 18:01:11.712059
5255 18:01:11.712134
5256 18:01:11.712196 ==
5257 18:01:11.715290 Dram Type= 6, Freq= 0, CH_0, rank 0
5258 18:01:11.718530 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5259 18:01:11.718613 ==
5260 18:01:11.718707
5261 18:01:11.718788
5262 18:01:11.722025 TX Vref Scan disable
5263 18:01:11.725662 == TX Byte 0 ==
5264 18:01:11.728824 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5265 18:01:11.732048 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5266 18:01:11.735775 == TX Byte 1 ==
5267 18:01:11.738733 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5268 18:01:11.742406 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5269 18:01:11.742493 ==
5270 18:01:11.745591 Dram Type= 6, Freq= 0, CH_0, rank 0
5271 18:01:11.748846 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5272 18:01:11.751944 ==
5273 18:01:11.752028
5274 18:01:11.752093
5275 18:01:11.752153 TX Vref Scan disable
5276 18:01:11.756079 == TX Byte 0 ==
5277 18:01:11.759192 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5278 18:01:11.762880 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5279 18:01:11.766003 == TX Byte 1 ==
5280 18:01:11.769168 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5281 18:01:11.776201 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5282 18:01:11.776324
5283 18:01:11.776397 [DATLAT]
5284 18:01:11.776491 Freq=933, CH0 RK0
5285 18:01:11.776582
5286 18:01:11.779253 DATLAT Default: 0xd
5287 18:01:11.779363 0, 0xFFFF, sum = 0
5288 18:01:11.782259 1, 0xFFFF, sum = 0
5289 18:01:11.782371 2, 0xFFFF, sum = 0
5290 18:01:11.785965 3, 0xFFFF, sum = 0
5291 18:01:11.786084 4, 0xFFFF, sum = 0
5292 18:01:11.788927 5, 0xFFFF, sum = 0
5293 18:01:11.792786 6, 0xFFFF, sum = 0
5294 18:01:11.792898 7, 0xFFFF, sum = 0
5295 18:01:11.795769 8, 0xFFFF, sum = 0
5296 18:01:11.795876 9, 0xFFFF, sum = 0
5297 18:01:11.799184 10, 0x0, sum = 1
5298 18:01:11.799288 11, 0x0, sum = 2
5299 18:01:11.799356 12, 0x0, sum = 3
5300 18:01:11.802603 13, 0x0, sum = 4
5301 18:01:11.802708 best_step = 11
5302 18:01:11.802810
5303 18:01:11.805937 ==
5304 18:01:11.806047 Dram Type= 6, Freq= 0, CH_0, rank 0
5305 18:01:11.812706 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5306 18:01:11.812820 ==
5307 18:01:11.812914 RX Vref Scan: 1
5308 18:01:11.813021
5309 18:01:11.815477 RX Vref 0 -> 0, step: 1
5310 18:01:11.815588
5311 18:01:11.819200 RX Delay -61 -> 252, step: 4
5312 18:01:11.819280
5313 18:01:11.822203 Set Vref, RX VrefLevel [Byte0]: 52
5314 18:01:11.825990 [Byte1]: 52
5315 18:01:11.826094
5316 18:01:11.829083 Final RX Vref Byte 0 = 52 to rank0
5317 18:01:11.832129 Final RX Vref Byte 1 = 52 to rank0
5318 18:01:11.835904 Final RX Vref Byte 0 = 52 to rank1
5319 18:01:11.838993 Final RX Vref Byte 1 = 52 to rank1==
5320 18:01:11.842773 Dram Type= 6, Freq= 0, CH_0, rank 0
5321 18:01:11.845676 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5322 18:01:11.845776 ==
5323 18:01:11.849526 DQS Delay:
5324 18:01:11.849604 DQS0 = 0, DQS1 = 0
5325 18:01:11.852500 DQM Delay:
5326 18:01:11.852607 DQM0 = 96, DQM1 = 88
5327 18:01:11.852674 DQ Delay:
5328 18:01:11.855632 DQ0 =98, DQ1 =98, DQ2 =94, DQ3 =94
5329 18:01:11.859415 DQ4 =98, DQ5 =84, DQ6 =106, DQ7 =102
5330 18:01:11.862462 DQ8 =80, DQ9 =76, DQ10 =90, DQ11 =80
5331 18:01:11.866202 DQ12 =94, DQ13 =90, DQ14 =102, DQ15 =98
5332 18:01:11.866309
5333 18:01:11.866394
5334 18:01:11.876181 [DQSOSCAuto] RK0, (LSB)MR18= 0x1601, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 414 ps
5335 18:01:11.879321 CH0 RK0: MR19=505, MR18=1601
5336 18:01:11.885765 CH0_RK0: MR19=0x505, MR18=0x1601, DQSOSC=414, MR23=63, INC=63, DEC=42
5337 18:01:11.885888
5338 18:01:11.889298 ----->DramcWriteLeveling(PI) begin...
5339 18:01:11.889376 ==
5340 18:01:11.892365 Dram Type= 6, Freq= 0, CH_0, rank 1
5341 18:01:11.895508 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5342 18:01:11.895610 ==
5343 18:01:11.899317 Write leveling (Byte 0): 32 => 32
5344 18:01:11.902433 Write leveling (Byte 1): 32 => 32
5345 18:01:11.905587 DramcWriteLeveling(PI) end<-----
5346 18:01:11.905658
5347 18:01:11.905719 ==
5348 18:01:11.908813 Dram Type= 6, Freq= 0, CH_0, rank 1
5349 18:01:11.912532 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5350 18:01:11.912646 ==
5351 18:01:11.915666 [Gating] SW mode calibration
5352 18:01:11.922280 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5353 18:01:11.929195 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5354 18:01:11.932241 0 14 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
5355 18:01:11.935656 0 14 4 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
5356 18:01:11.942262 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5357 18:01:11.945861 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5358 18:01:11.948851 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5359 18:01:11.952570 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5360 18:01:11.959160 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5361 18:01:11.962322 0 14 28 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
5362 18:01:11.965998 0 15 0 | B1->B0 | 3030 2323 | 1 0 | (0 0) (0 0)
5363 18:01:11.972604 0 15 4 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
5364 18:01:11.975886 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5365 18:01:11.979533 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5366 18:01:11.985862 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5367 18:01:11.989572 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5368 18:01:11.992527 0 15 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5369 18:01:11.999454 0 15 28 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
5370 18:01:12.002575 1 0 0 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
5371 18:01:12.005852 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5372 18:01:12.012664 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5373 18:01:12.016443 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5374 18:01:12.019528 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5375 18:01:12.022596 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5376 18:01:12.029643 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5377 18:01:12.033056 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5378 18:01:12.036033 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5379 18:01:12.043110 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5380 18:01:12.046509 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5381 18:01:12.049784 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5382 18:01:12.056071 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5383 18:01:12.059421 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5384 18:01:12.063128 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5385 18:01:12.069892 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5386 18:01:12.072929 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5387 18:01:12.076467 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5388 18:01:12.082786 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5389 18:01:12.086605 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5390 18:01:12.089786 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5391 18:01:12.096569 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5392 18:01:12.099846 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5393 18:01:12.102784 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5394 18:01:12.106024 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5395 18:01:12.109411 Total UI for P1: 0, mck2ui 16
5396 18:01:12.113252 best dqsien dly found for B0: ( 1, 2, 28)
5397 18:01:12.119780 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5398 18:01:12.123022 Total UI for P1: 0, mck2ui 16
5399 18:01:12.126150 best dqsien dly found for B1: ( 1, 3, 0)
5400 18:01:12.129817 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5401 18:01:12.132920 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5402 18:01:12.133031
5403 18:01:12.136121 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5404 18:01:12.139290 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5405 18:01:12.142687 [Gating] SW calibration Done
5406 18:01:12.142794 ==
5407 18:01:12.146491 Dram Type= 6, Freq= 0, CH_0, rank 1
5408 18:01:12.149560 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5409 18:01:12.149649 ==
5410 18:01:12.152700 RX Vref Scan: 0
5411 18:01:12.152799
5412 18:01:12.152893 RX Vref 0 -> 0, step: 1
5413 18:01:12.152990
5414 18:01:12.156241 RX Delay -80 -> 252, step: 8
5415 18:01:12.159755 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5416 18:01:12.165958 iDelay=200, Bit 1, Center 95 (0 ~ 191) 192
5417 18:01:12.169479 iDelay=200, Bit 2, Center 95 (0 ~ 191) 192
5418 18:01:12.173059 iDelay=200, Bit 3, Center 91 (-8 ~ 191) 200
5419 18:01:12.176491 iDelay=200, Bit 4, Center 99 (8 ~ 191) 184
5420 18:01:12.179756 iDelay=200, Bit 5, Center 87 (-8 ~ 183) 192
5421 18:01:12.182868 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5422 18:01:12.186749 iDelay=200, Bit 7, Center 103 (8 ~ 199) 192
5423 18:01:12.192779 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5424 18:01:12.196580 iDelay=200, Bit 9, Center 75 (-16 ~ 167) 184
5425 18:01:12.199669 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5426 18:01:12.202947 iDelay=200, Bit 11, Center 79 (-16 ~ 175) 192
5427 18:01:12.206720 iDelay=200, Bit 12, Center 91 (0 ~ 183) 184
5428 18:01:12.212846 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5429 18:01:12.216328 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5430 18:01:12.219475 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5431 18:01:12.219588 ==
5432 18:01:12.223463 Dram Type= 6, Freq= 0, CH_0, rank 1
5433 18:01:12.226419 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5434 18:01:12.226530 ==
5435 18:01:12.229730 DQS Delay:
5436 18:01:12.229838 DQS0 = 0, DQS1 = 0
5437 18:01:12.229939 DQM Delay:
5438 18:01:12.233378 DQM0 = 96, DQM1 = 87
5439 18:01:12.233480 DQ Delay:
5440 18:01:12.236589 DQ0 =95, DQ1 =95, DQ2 =95, DQ3 =91
5441 18:01:12.239776 DQ4 =99, DQ5 =87, DQ6 =103, DQ7 =103
5442 18:01:12.242997 DQ8 =79, DQ9 =75, DQ10 =87, DQ11 =79
5443 18:01:12.246866 DQ12 =91, DQ13 =95, DQ14 =95, DQ15 =95
5444 18:01:12.246973
5445 18:01:12.247067
5446 18:01:12.247158 ==
5447 18:01:12.250013 Dram Type= 6, Freq= 0, CH_0, rank 1
5448 18:01:12.256293 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5449 18:01:12.256401 ==
5450 18:01:12.256494
5451 18:01:12.256587
5452 18:01:12.256676 TX Vref Scan disable
5453 18:01:12.260196 == TX Byte 0 ==
5454 18:01:12.263077 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5455 18:01:12.266629 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5456 18:01:12.269764 == TX Byte 1 ==
5457 18:01:12.273388 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5458 18:01:12.276518 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5459 18:01:12.279771 ==
5460 18:01:12.282896 Dram Type= 6, Freq= 0, CH_0, rank 1
5461 18:01:12.286450 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5462 18:01:12.286556 ==
5463 18:01:12.286654
5464 18:01:12.286745
5465 18:01:12.289845 TX Vref Scan disable
5466 18:01:12.289947 == TX Byte 0 ==
5467 18:01:12.296841 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5468 18:01:12.300017 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5469 18:01:12.300107 == TX Byte 1 ==
5470 18:01:12.306216 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5471 18:01:12.310019 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5472 18:01:12.310131
5473 18:01:12.310227 [DATLAT]
5474 18:01:12.313205 Freq=933, CH0 RK1
5475 18:01:12.313314
5476 18:01:12.313408 DATLAT Default: 0xb
5477 18:01:12.316357 0, 0xFFFF, sum = 0
5478 18:01:12.316462 1, 0xFFFF, sum = 0
5479 18:01:12.319510 2, 0xFFFF, sum = 0
5480 18:01:12.319615 3, 0xFFFF, sum = 0
5481 18:01:12.323492 4, 0xFFFF, sum = 0
5482 18:01:12.323591 5, 0xFFFF, sum = 0
5483 18:01:12.326514 6, 0xFFFF, sum = 0
5484 18:01:12.326624 7, 0xFFFF, sum = 0
5485 18:01:12.330037 8, 0xFFFF, sum = 0
5486 18:01:12.330115 9, 0xFFFF, sum = 0
5487 18:01:12.333437 10, 0x0, sum = 1
5488 18:01:12.333515 11, 0x0, sum = 2
5489 18:01:12.336440 12, 0x0, sum = 3
5490 18:01:12.336546 13, 0x0, sum = 4
5491 18:01:12.340156 best_step = 11
5492 18:01:12.340259
5493 18:01:12.340366 ==
5494 18:01:12.343291 Dram Type= 6, Freq= 0, CH_0, rank 1
5495 18:01:12.346397 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5496 18:01:12.346483 ==
5497 18:01:12.350172 RX Vref Scan: 0
5498 18:01:12.350284
5499 18:01:12.350352 RX Vref 0 -> 0, step: 1
5500 18:01:12.350413
5501 18:01:12.353321 RX Delay -61 -> 252, step: 4
5502 18:01:12.360273 iDelay=199, Bit 0, Center 96 (3 ~ 190) 188
5503 18:01:12.363522 iDelay=199, Bit 1, Center 96 (3 ~ 190) 188
5504 18:01:12.367192 iDelay=199, Bit 2, Center 92 (-1 ~ 186) 188
5505 18:01:12.370075 iDelay=199, Bit 3, Center 94 (-1 ~ 190) 192
5506 18:01:12.373700 iDelay=199, Bit 4, Center 96 (7 ~ 186) 180
5507 18:01:12.376663 iDelay=199, Bit 5, Center 84 (-9 ~ 178) 188
5508 18:01:12.383668 iDelay=199, Bit 6, Center 106 (15 ~ 198) 184
5509 18:01:12.386922 iDelay=199, Bit 7, Center 102 (11 ~ 194) 184
5510 18:01:12.389844 iDelay=199, Bit 8, Center 80 (-9 ~ 170) 180
5511 18:01:12.393510 iDelay=199, Bit 9, Center 78 (-9 ~ 166) 176
5512 18:01:12.396663 iDelay=199, Bit 10, Center 88 (-1 ~ 178) 180
5513 18:01:12.400327 iDelay=199, Bit 11, Center 78 (-9 ~ 166) 176
5514 18:01:12.407164 iDelay=199, Bit 12, Center 90 (-1 ~ 182) 184
5515 18:01:12.410027 iDelay=199, Bit 13, Center 92 (3 ~ 182) 180
5516 18:01:12.413446 iDelay=199, Bit 14, Center 100 (15 ~ 186) 172
5517 18:01:12.416821 iDelay=199, Bit 15, Center 92 (3 ~ 182) 180
5518 18:01:12.416908 ==
5519 18:01:12.420485 Dram Type= 6, Freq= 0, CH_0, rank 1
5520 18:01:12.423614 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5521 18:01:12.426914 ==
5522 18:01:12.427040 DQS Delay:
5523 18:01:12.427138 DQS0 = 0, DQS1 = 0
5524 18:01:12.430176 DQM Delay:
5525 18:01:12.430256 DQM0 = 95, DQM1 = 87
5526 18:01:12.433931 DQ Delay:
5527 18:01:12.434009 DQ0 =96, DQ1 =96, DQ2 =92, DQ3 =94
5528 18:01:12.437045 DQ4 =96, DQ5 =84, DQ6 =106, DQ7 =102
5529 18:01:12.440162 DQ8 =80, DQ9 =78, DQ10 =88, DQ11 =78
5530 18:01:12.443738 DQ12 =90, DQ13 =92, DQ14 =100, DQ15 =92
5531 18:01:12.447083
5532 18:01:12.447192
5533 18:01:12.453509 [DQSOSCAuto] RK1, (LSB)MR18= 0x1c09, (MSB)MR19= 0x505, tDQSOscB0 = 419 ps tDQSOscB1 = 412 ps
5534 18:01:12.457205 CH0 RK1: MR19=505, MR18=1C09
5535 18:01:12.463866 CH0_RK1: MR19=0x505, MR18=0x1C09, DQSOSC=412, MR23=63, INC=63, DEC=42
5536 18:01:12.467083 [RxdqsGatingPostProcess] freq 933
5537 18:01:12.470339 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5538 18:01:12.473965 best DQS0 dly(2T, 0.5T) = (0, 11)
5539 18:01:12.477369 best DQS1 dly(2T, 0.5T) = (0, 11)
5540 18:01:12.480333 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
5541 18:01:12.483825 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5542 18:01:12.487118 best DQS0 dly(2T, 0.5T) = (0, 10)
5543 18:01:12.490947 best DQS1 dly(2T, 0.5T) = (0, 11)
5544 18:01:12.493993 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5545 18:01:12.497184 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5546 18:01:12.500332 Pre-setting of DQS Precalculation
5547 18:01:12.504099 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5548 18:01:12.504189 ==
5549 18:01:12.507283 Dram Type= 6, Freq= 0, CH_1, rank 0
5550 18:01:12.510377 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5551 18:01:12.510457 ==
5552 18:01:12.517645 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5553 18:01:12.524296 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5554 18:01:12.527222 [CA 0] Center 36 (6~67) winsize 62
5555 18:01:12.530595 [CA 1] Center 36 (6~67) winsize 62
5556 18:01:12.533888 [CA 2] Center 34 (4~64) winsize 61
5557 18:01:12.537548 [CA 3] Center 33 (3~64) winsize 62
5558 18:01:12.540840 [CA 4] Center 34 (4~65) winsize 62
5559 18:01:12.544140 [CA 5] Center 33 (3~63) winsize 61
5560 18:01:12.544227
5561 18:01:12.547184 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5562 18:01:12.547263
5563 18:01:12.550835 [CATrainingPosCal] consider 1 rank data
5564 18:01:12.553907 u2DelayCellTimex100 = 270/100 ps
5565 18:01:12.557442 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5566 18:01:12.560888 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5567 18:01:12.564080 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5568 18:01:12.567251 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5569 18:01:12.570500 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5570 18:01:12.574413 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5571 18:01:12.574496
5572 18:01:12.580579 CA PerBit enable=1, Macro0, CA PI delay=33
5573 18:01:12.580688
5574 18:01:12.584091 [CBTSetCACLKResult] CA Dly = 33
5575 18:01:12.584200 CS Dly: 5 (0~36)
5576 18:01:12.584294 ==
5577 18:01:12.587415 Dram Type= 6, Freq= 0, CH_1, rank 1
5578 18:01:12.590486 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5579 18:01:12.590596 ==
5580 18:01:12.597233 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5581 18:01:12.603980 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5582 18:01:12.607738 [CA 0] Center 36 (6~67) winsize 62
5583 18:01:12.610951 [CA 1] Center 37 (7~67) winsize 61
5584 18:01:12.614092 [CA 2] Center 33 (3~64) winsize 62
5585 18:01:12.617708 [CA 3] Center 34 (4~64) winsize 61
5586 18:01:12.620835 [CA 4] Center 34 (4~65) winsize 62
5587 18:01:12.624063 [CA 5] Center 32 (2~63) winsize 62
5588 18:01:12.624171
5589 18:01:12.627361 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5590 18:01:12.627468
5591 18:01:12.631064 [CATrainingPosCal] consider 2 rank data
5592 18:01:12.634242 u2DelayCellTimex100 = 270/100 ps
5593 18:01:12.637391 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5594 18:01:12.640907 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5595 18:01:12.644118 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5596 18:01:12.647723 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5597 18:01:12.650572 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5598 18:01:12.654197 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5599 18:01:12.654309
5600 18:01:12.660963 CA PerBit enable=1, Macro0, CA PI delay=33
5601 18:01:12.661090
5602 18:01:12.664248 [CBTSetCACLKResult] CA Dly = 33
5603 18:01:12.664334 CS Dly: 6 (0~38)
5604 18:01:12.664407
5605 18:01:12.667228 ----->DramcWriteLeveling(PI) begin...
5606 18:01:12.667314 ==
5607 18:01:12.670788 Dram Type= 6, Freq= 0, CH_1, rank 0
5608 18:01:12.674088 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5609 18:01:12.674167 ==
5610 18:01:12.677415 Write leveling (Byte 0): 25 => 25
5611 18:01:12.680560 Write leveling (Byte 1): 26 => 26
5612 18:01:12.684331 DramcWriteLeveling(PI) end<-----
5613 18:01:12.684411
5614 18:01:12.684486 ==
5615 18:01:12.687244 Dram Type= 6, Freq= 0, CH_1, rank 0
5616 18:01:12.690886 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5617 18:01:12.694206 ==
5618 18:01:12.694292 [Gating] SW mode calibration
5619 18:01:12.704139 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5620 18:01:12.707280 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5621 18:01:12.711112 0 14 0 | B1->B0 | 3030 3232 | 1 1 | (1 1) (1 1)
5622 18:01:12.717396 0 14 4 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5623 18:01:12.720595 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5624 18:01:12.723843 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5625 18:01:12.730878 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5626 18:01:12.734691 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5627 18:01:12.737861 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5628 18:01:12.744215 0 14 28 | B1->B0 | 2f2f 3333 | 0 0 | (1 0) (0 0)
5629 18:01:12.747804 0 15 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5630 18:01:12.750867 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5631 18:01:12.757676 0 15 8 | B1->B0 | 2423 2323 | 1 0 | (0 0) (0 0)
5632 18:01:12.760774 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5633 18:01:12.764289 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5634 18:01:12.770724 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5635 18:01:12.774162 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5636 18:01:12.777275 0 15 28 | B1->B0 | 2c2c 2e2e | 0 0 | (0 0) (0 0)
5637 18:01:12.784274 1 0 0 | B1->B0 | 4242 3d3d | 0 0 | (0 0) (0 0)
5638 18:01:12.787492 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5639 18:01:12.790538 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5640 18:01:12.797131 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5641 18:01:12.800571 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5642 18:01:12.803691 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5643 18:01:12.807216 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5644 18:01:12.814196 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5645 18:01:12.817269 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5646 18:01:12.820376 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5647 18:01:12.826829 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5648 18:01:12.830709 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5649 18:01:12.833988 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5650 18:01:12.840461 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5651 18:01:12.843545 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5652 18:01:12.847279 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5653 18:01:12.853658 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5654 18:01:12.856868 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5655 18:01:12.860742 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5656 18:01:12.867018 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5657 18:01:12.870287 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5658 18:01:12.873904 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5659 18:01:12.880602 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5660 18:01:12.884002 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5661 18:01:12.887193 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5662 18:01:12.890278 Total UI for P1: 0, mck2ui 16
5663 18:01:12.893842 best dqsien dly found for B0: ( 1, 2, 26)
5664 18:01:12.897184 Total UI for P1: 0, mck2ui 16
5665 18:01:12.900381 best dqsien dly found for B1: ( 1, 2, 28)
5666 18:01:12.904097 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5667 18:01:12.907190 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5668 18:01:12.907300
5669 18:01:12.910523 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5670 18:01:12.917248 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5671 18:01:12.917335 [Gating] SW calibration Done
5672 18:01:12.917415 ==
5673 18:01:12.920261 Dram Type= 6, Freq= 0, CH_1, rank 0
5674 18:01:12.927306 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5675 18:01:12.927415 ==
5676 18:01:12.927483 RX Vref Scan: 0
5677 18:01:12.927545
5678 18:01:12.930465 RX Vref 0 -> 0, step: 1
5679 18:01:12.930541
5680 18:01:12.933621 RX Delay -80 -> 252, step: 8
5681 18:01:12.936784 iDelay=200, Bit 0, Center 99 (8 ~ 191) 184
5682 18:01:12.940593 iDelay=200, Bit 1, Center 87 (-8 ~ 183) 192
5683 18:01:12.943848 iDelay=200, Bit 2, Center 83 (-8 ~ 175) 184
5684 18:01:12.946892 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5685 18:01:12.953629 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5686 18:01:12.956876 iDelay=200, Bit 5, Center 103 (8 ~ 199) 192
5687 18:01:12.960472 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5688 18:01:12.963538 iDelay=200, Bit 7, Center 91 (-8 ~ 191) 200
5689 18:01:12.967266 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5690 18:01:12.970557 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5691 18:01:12.976907 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5692 18:01:12.980576 iDelay=200, Bit 11, Center 83 (-16 ~ 183) 200
5693 18:01:12.983695 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5694 18:01:12.986848 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5695 18:01:12.990495 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5696 18:01:12.997342 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5697 18:01:12.997433 ==
5698 18:01:13.000487 Dram Type= 6, Freq= 0, CH_1, rank 0
5699 18:01:13.003761 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5700 18:01:13.003848 ==
5701 18:01:13.003915 DQS Delay:
5702 18:01:13.006746 DQS0 = 0, DQS1 = 0
5703 18:01:13.006829 DQM Delay:
5704 18:01:13.010210 DQM0 = 95, DQM1 = 88
5705 18:01:13.010320 DQ Delay:
5706 18:01:13.013436 DQ0 =99, DQ1 =87, DQ2 =83, DQ3 =95
5707 18:01:13.016766 DQ4 =95, DQ5 =103, DQ6 =107, DQ7 =91
5708 18:01:13.020084 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =83
5709 18:01:13.023662 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5710 18:01:13.023738
5711 18:01:13.023801
5712 18:01:13.023861 ==
5713 18:01:13.026825 Dram Type= 6, Freq= 0, CH_1, rank 0
5714 18:01:13.030148 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5715 18:01:13.030260 ==
5716 18:01:13.030354
5717 18:01:13.030436
5718 18:01:13.033547 TX Vref Scan disable
5719 18:01:13.036721 == TX Byte 0 ==
5720 18:01:13.039912 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5721 18:01:13.043724 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5722 18:01:13.046844 == TX Byte 1 ==
5723 18:01:13.050629 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5724 18:01:13.053783 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5725 18:01:13.053868 ==
5726 18:01:13.056860 Dram Type= 6, Freq= 0, CH_1, rank 0
5727 18:01:13.059984 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5728 18:01:13.063792 ==
5729 18:01:13.063902
5730 18:01:13.063996
5731 18:01:13.064086 TX Vref Scan disable
5732 18:01:13.067456 == TX Byte 0 ==
5733 18:01:13.070431 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5734 18:01:13.074108 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5735 18:01:13.077267 == TX Byte 1 ==
5736 18:01:13.080406 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5737 18:01:13.084213 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5738 18:01:13.087403
5739 18:01:13.087506 [DATLAT]
5740 18:01:13.087600 Freq=933, CH1 RK0
5741 18:01:13.087690
5742 18:01:13.090400 DATLAT Default: 0xd
5743 18:01:13.090475 0, 0xFFFF, sum = 0
5744 18:01:13.094060 1, 0xFFFF, sum = 0
5745 18:01:13.094137 2, 0xFFFF, sum = 0
5746 18:01:13.097141 3, 0xFFFF, sum = 0
5747 18:01:13.097251 4, 0xFFFF, sum = 0
5748 18:01:13.100701 5, 0xFFFF, sum = 0
5749 18:01:13.103867 6, 0xFFFF, sum = 0
5750 18:01:13.103944 7, 0xFFFF, sum = 0
5751 18:01:13.107076 8, 0xFFFF, sum = 0
5752 18:01:13.107151 9, 0xFFFF, sum = 0
5753 18:01:13.110326 10, 0x0, sum = 1
5754 18:01:13.110401 11, 0x0, sum = 2
5755 18:01:13.110463 12, 0x0, sum = 3
5756 18:01:13.114208 13, 0x0, sum = 4
5757 18:01:13.114283 best_step = 11
5758 18:01:13.114344
5759 18:01:13.117257 ==
5760 18:01:13.117350 Dram Type= 6, Freq= 0, CH_1, rank 0
5761 18:01:13.123918 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5762 18:01:13.124025 ==
5763 18:01:13.124130 RX Vref Scan: 1
5764 18:01:13.124222
5765 18:01:13.126943 RX Vref 0 -> 0, step: 1
5766 18:01:13.127050
5767 18:01:13.130504 RX Delay -61 -> 252, step: 4
5768 18:01:13.130602
5769 18:01:13.133751 Set Vref, RX VrefLevel [Byte0]: 60
5770 18:01:13.136932 [Byte1]: 52
5771 18:01:13.137031
5772 18:01:13.140117 Final RX Vref Byte 0 = 60 to rank0
5773 18:01:13.143885 Final RX Vref Byte 1 = 52 to rank0
5774 18:01:13.147212 Final RX Vref Byte 0 = 60 to rank1
5775 18:01:13.150232 Final RX Vref Byte 1 = 52 to rank1==
5776 18:01:13.154048 Dram Type= 6, Freq= 0, CH_1, rank 0
5777 18:01:13.157201 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5778 18:01:13.157283 ==
5779 18:01:13.160296 DQS Delay:
5780 18:01:13.160372 DQS0 = 0, DQS1 = 0
5781 18:01:13.163521 DQM Delay:
5782 18:01:13.163608 DQM0 = 97, DQM1 = 90
5783 18:01:13.163691 DQ Delay:
5784 18:01:13.167329 DQ0 =100, DQ1 =92, DQ2 =88, DQ3 =96
5785 18:01:13.170372 DQ4 =96, DQ5 =106, DQ6 =108, DQ7 =94
5786 18:01:13.173530 DQ8 =80, DQ9 =80, DQ10 =92, DQ11 =86
5787 18:01:13.176978 DQ12 =98, DQ13 =96, DQ14 =98, DQ15 =94
5788 18:01:13.177087
5789 18:01:13.177191
5790 18:01:13.187455 [DQSOSCAuto] RK0, (LSB)MR18= 0x16f3, (MSB)MR19= 0x504, tDQSOscB0 = 426 ps tDQSOscB1 = 414 ps
5791 18:01:13.190527 CH1 RK0: MR19=504, MR18=16F3
5792 18:01:13.193632 CH1_RK0: MR19=0x504, MR18=0x16F3, DQSOSC=414, MR23=63, INC=63, DEC=42
5793 18:01:13.197367
5794 18:01:13.200522 ----->DramcWriteLeveling(PI) begin...
5795 18:01:13.200631 ==
5796 18:01:13.204051 Dram Type= 6, Freq= 0, CH_1, rank 1
5797 18:01:13.206923 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5798 18:01:13.207039 ==
5799 18:01:13.210630 Write leveling (Byte 0): 26 => 26
5800 18:01:13.213841 Write leveling (Byte 1): 28 => 28
5801 18:01:13.216979 DramcWriteLeveling(PI) end<-----
5802 18:01:13.217078
5803 18:01:13.217162 ==
5804 18:01:13.220910 Dram Type= 6, Freq= 0, CH_1, rank 1
5805 18:01:13.224043 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5806 18:01:13.224152 ==
5807 18:01:13.227141 [Gating] SW mode calibration
5808 18:01:13.233951 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5809 18:01:13.240761 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5810 18:01:13.243745 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5811 18:01:13.247199 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5812 18:01:13.254003 0 14 8 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5813 18:01:13.257157 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5814 18:01:13.260369 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5815 18:01:13.263854 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5816 18:01:13.270564 0 14 24 | B1->B0 | 3232 2f2f | 0 1 | (0 0) (1 0)
5817 18:01:13.273776 0 14 28 | B1->B0 | 2a2a 2323 | 1 0 | (1 0) (0 0)
5818 18:01:13.276926 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5819 18:01:13.284048 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5820 18:01:13.287525 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5821 18:01:13.290477 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5822 18:01:13.296943 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5823 18:01:13.300707 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5824 18:01:13.303759 0 15 24 | B1->B0 | 2929 3737 | 0 0 | (0 0) (0 0)
5825 18:01:13.310513 0 15 28 | B1->B0 | 3a3a 4646 | 1 0 | (0 0) (0 0)
5826 18:01:13.313618 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5827 18:01:13.317340 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5828 18:01:13.323600 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5829 18:01:13.326840 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5830 18:01:13.330638 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5831 18:01:13.337200 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5832 18:01:13.340388 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5833 18:01:13.343527 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5834 18:01:13.350624 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5835 18:01:13.353653 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5836 18:01:13.357336 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5837 18:01:13.363894 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5838 18:01:13.367282 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5839 18:01:13.370610 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5840 18:01:13.373713 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5841 18:01:13.380545 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5842 18:01:13.384146 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5843 18:01:13.387346 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5844 18:01:13.393785 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5845 18:01:13.396943 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5846 18:01:13.400795 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5847 18:01:13.407503 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5848 18:01:13.410638 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5849 18:01:13.413687 Total UI for P1: 0, mck2ui 16
5850 18:01:13.417249 best dqsien dly found for B0: ( 1, 2, 22)
5851 18:01:13.420329 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5852 18:01:13.427297 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5853 18:01:13.427383 Total UI for P1: 0, mck2ui 16
5854 18:01:13.430556 best dqsien dly found for B1: ( 1, 2, 26)
5855 18:01:13.437078 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5856 18:01:13.440257 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5857 18:01:13.440336
5858 18:01:13.443943 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5859 18:01:13.447349 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5860 18:01:13.450467 [Gating] SW calibration Done
5861 18:01:13.450553 ==
5862 18:01:13.454152 Dram Type= 6, Freq= 0, CH_1, rank 1
5863 18:01:13.457357 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5864 18:01:13.457441 ==
5865 18:01:13.460552 RX Vref Scan: 0
5866 18:01:13.460661
5867 18:01:13.460756 RX Vref 0 -> 0, step: 1
5868 18:01:13.460846
5869 18:01:13.464345 RX Delay -80 -> 252, step: 8
5870 18:01:13.467206 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5871 18:01:13.470304 iDelay=200, Bit 1, Center 87 (-8 ~ 183) 192
5872 18:01:13.477064 iDelay=200, Bit 2, Center 87 (-8 ~ 183) 192
5873 18:01:13.480758 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5874 18:01:13.483690 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5875 18:01:13.487245 iDelay=200, Bit 5, Center 103 (8 ~ 199) 192
5876 18:01:13.490637 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5877 18:01:13.493969 iDelay=200, Bit 7, Center 91 (0 ~ 183) 184
5878 18:01:13.500407 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5879 18:01:13.503865 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5880 18:01:13.507394 iDelay=200, Bit 10, Center 91 (-8 ~ 191) 200
5881 18:01:13.510402 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5882 18:01:13.513899 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5883 18:01:13.517071 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5884 18:01:13.523781 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5885 18:01:13.529903 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5886 18:01:13.530012 ==
5887 18:01:13.530496 Dram Type= 6, Freq= 0, CH_1, rank 1
5888 18:01:13.534005 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5889 18:01:13.534082 ==
5890 18:01:13.537005 DQS Delay:
5891 18:01:13.537078 DQS0 = 0, DQS1 = 0
5892 18:01:13.537143 DQM Delay:
5893 18:01:13.540592 DQM0 = 94, DQM1 = 89
5894 18:01:13.540668 DQ Delay:
5895 18:01:13.544183 DQ0 =95, DQ1 =87, DQ2 =87, DQ3 =95
5896 18:01:13.547279 DQ4 =95, DQ5 =103, DQ6 =103, DQ7 =91
5897 18:01:13.550379 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =83
5898 18:01:13.553835 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5899 18:01:13.553914
5900 18:01:13.553977
5901 18:01:13.554038 ==
5902 18:01:13.557044 Dram Type= 6, Freq= 0, CH_1, rank 1
5903 18:01:13.563912 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5904 18:01:13.563994 ==
5905 18:01:13.564059
5906 18:01:13.564119
5907 18:01:13.564180 TX Vref Scan disable
5908 18:01:13.566898 == TX Byte 0 ==
5909 18:01:13.570402 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5910 18:01:13.573897 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5911 18:01:13.577043 == TX Byte 1 ==
5912 18:01:13.580215 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5913 18:01:13.586807 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5914 18:01:13.586906 ==
5915 18:01:13.590514 Dram Type= 6, Freq= 0, CH_1, rank 1
5916 18:01:13.593468 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5917 18:01:13.593541 ==
5918 18:01:13.593604
5919 18:01:13.593662
5920 18:01:13.597063 TX Vref Scan disable
5921 18:01:13.597140 == TX Byte 0 ==
5922 18:01:13.603470 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5923 18:01:13.606952 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5924 18:01:13.607028 == TX Byte 1 ==
5925 18:01:13.613612 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5926 18:01:13.616784 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5927 18:01:13.616888
5928 18:01:13.616993 [DATLAT]
5929 18:01:13.620268 Freq=933, CH1 RK1
5930 18:01:13.620367
5931 18:01:13.620453 DATLAT Default: 0xb
5932 18:01:13.623466 0, 0xFFFF, sum = 0
5933 18:01:13.623543 1, 0xFFFF, sum = 0
5934 18:01:13.627111 2, 0xFFFF, sum = 0
5935 18:01:13.627187 3, 0xFFFF, sum = 0
5936 18:01:13.630425 4, 0xFFFF, sum = 0
5937 18:01:13.630519 5, 0xFFFF, sum = 0
5938 18:01:13.633424 6, 0xFFFF, sum = 0
5939 18:01:13.633502 7, 0xFFFF, sum = 0
5940 18:01:13.637292 8, 0xFFFF, sum = 0
5941 18:01:13.637430 9, 0xFFFF, sum = 0
5942 18:01:13.640168 10, 0x0, sum = 1
5943 18:01:13.640299 11, 0x0, sum = 2
5944 18:01:13.643793 12, 0x0, sum = 3
5945 18:01:13.643916 13, 0x0, sum = 4
5946 18:01:13.646894 best_step = 11
5947 18:01:13.647004
5948 18:01:13.647139 ==
5949 18:01:13.650459 Dram Type= 6, Freq= 0, CH_1, rank 1
5950 18:01:13.654094 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5951 18:01:13.654196 ==
5952 18:01:13.657101 RX Vref Scan: 0
5953 18:01:13.657238
5954 18:01:13.657302 RX Vref 0 -> 0, step: 1
5955 18:01:13.657361
5956 18:01:13.660046 RX Delay -61 -> 252, step: 4
5957 18:01:13.667494 iDelay=195, Bit 0, Center 98 (7 ~ 190) 184
5958 18:01:13.670631 iDelay=195, Bit 1, Center 90 (-1 ~ 182) 184
5959 18:01:13.674209 iDelay=195, Bit 2, Center 84 (-5 ~ 174) 180
5960 18:01:13.677200 iDelay=195, Bit 3, Center 94 (3 ~ 186) 184
5961 18:01:13.680824 iDelay=195, Bit 4, Center 96 (7 ~ 186) 180
5962 18:01:13.683814 iDelay=195, Bit 5, Center 104 (15 ~ 194) 180
5963 18:01:13.690930 iDelay=195, Bit 6, Center 102 (11 ~ 194) 184
5964 18:01:13.694082 iDelay=195, Bit 7, Center 90 (3 ~ 178) 176
5965 18:01:13.697319 iDelay=195, Bit 8, Center 80 (-13 ~ 174) 188
5966 18:01:13.700763 iDelay=195, Bit 9, Center 78 (-13 ~ 170) 184
5967 18:01:13.704457 iDelay=195, Bit 10, Center 92 (-1 ~ 186) 188
5968 18:01:13.707274 iDelay=195, Bit 11, Center 82 (-9 ~ 174) 184
5969 18:01:13.713971 iDelay=195, Bit 12, Center 98 (11 ~ 186) 176
5970 18:01:13.717562 iDelay=195, Bit 13, Center 100 (11 ~ 190) 180
5971 18:01:13.721247 iDelay=195, Bit 14, Center 100 (11 ~ 190) 180
5972 18:01:13.723992 iDelay=195, Bit 15, Center 100 (11 ~ 190) 180
5973 18:01:13.724131 ==
5974 18:01:13.727102 Dram Type= 6, Freq= 0, CH_1, rank 1
5975 18:01:13.734346 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5976 18:01:13.734502 ==
5977 18:01:13.734631 DQS Delay:
5978 18:01:13.737659 DQS0 = 0, DQS1 = 0
5979 18:01:13.737797 DQM Delay:
5980 18:01:13.737923 DQM0 = 94, DQM1 = 91
5981 18:01:13.740912 DQ Delay:
5982 18:01:13.743976 DQ0 =98, DQ1 =90, DQ2 =84, DQ3 =94
5983 18:01:13.747580 DQ4 =96, DQ5 =104, DQ6 =102, DQ7 =90
5984 18:01:13.750599 DQ8 =80, DQ9 =78, DQ10 =92, DQ11 =82
5985 18:01:13.754257 DQ12 =98, DQ13 =100, DQ14 =100, DQ15 =100
5986 18:01:13.754366
5987 18:01:13.754461
5988 18:01:13.760950 [DQSOSCAuto] RK1, (LSB)MR18= 0xe16, (MSB)MR19= 0x505, tDQSOscB0 = 414 ps tDQSOscB1 = 417 ps
5989 18:01:13.764032 CH1 RK1: MR19=505, MR18=E16
5990 18:01:13.771189 CH1_RK1: MR19=0x505, MR18=0xE16, DQSOSC=414, MR23=63, INC=63, DEC=42
5991 18:01:13.774055 [RxdqsGatingPostProcess] freq 933
5992 18:01:13.777696 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5993 18:01:13.780609 best DQS0 dly(2T, 0.5T) = (0, 10)
5994 18:01:13.784238 best DQS1 dly(2T, 0.5T) = (0, 10)
5995 18:01:13.787368 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5996 18:01:13.791013 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5997 18:01:13.793871 best DQS0 dly(2T, 0.5T) = (0, 10)
5998 18:01:13.797536 best DQS1 dly(2T, 0.5T) = (0, 10)
5999 18:01:13.800661 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6000 18:01:13.804228 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6001 18:01:13.807315 Pre-setting of DQS Precalculation
6002 18:01:13.810827 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6003 18:01:13.820556 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6004 18:01:13.827216 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6005 18:01:13.827330
6006 18:01:13.827424
6007 18:01:13.830979 [Calibration Summary] 1866 Mbps
6008 18:01:13.831085 CH 0, Rank 0
6009 18:01:13.834368 SW Impedance : PASS
6010 18:01:13.834472 DUTY Scan : NO K
6011 18:01:13.837796 ZQ Calibration : PASS
6012 18:01:13.840583 Jitter Meter : NO K
6013 18:01:13.840685 CBT Training : PASS
6014 18:01:13.843942 Write leveling : PASS
6015 18:01:13.844046 RX DQS gating : PASS
6016 18:01:13.847410 RX DQ/DQS(RDDQC) : PASS
6017 18:01:13.850728 TX DQ/DQS : PASS
6018 18:01:13.850843 RX DATLAT : PASS
6019 18:01:13.853864 RX DQ/DQS(Engine): PASS
6020 18:01:13.857388 TX OE : NO K
6021 18:01:13.857475 All Pass.
6022 18:01:13.857542
6023 18:01:13.857604 CH 0, Rank 1
6024 18:01:13.860967 SW Impedance : PASS
6025 18:01:13.864227 DUTY Scan : NO K
6026 18:01:13.864303 ZQ Calibration : PASS
6027 18:01:13.867158 Jitter Meter : NO K
6028 18:01:13.870825 CBT Training : PASS
6029 18:01:13.870931 Write leveling : PASS
6030 18:01:13.873875 RX DQS gating : PASS
6031 18:01:13.877561 RX DQ/DQS(RDDQC) : PASS
6032 18:01:13.877674 TX DQ/DQS : PASS
6033 18:01:13.880930 RX DATLAT : PASS
6034 18:01:13.881028 RX DQ/DQS(Engine): PASS
6035 18:01:13.884160 TX OE : NO K
6036 18:01:13.884237 All Pass.
6037 18:01:13.884317
6038 18:01:13.887527 CH 1, Rank 0
6039 18:01:13.887640 SW Impedance : PASS
6040 18:01:13.891167 DUTY Scan : NO K
6041 18:01:13.894224 ZQ Calibration : PASS
6042 18:01:13.894327 Jitter Meter : NO K
6043 18:01:13.897764 CBT Training : PASS
6044 18:01:13.900814 Write leveling : PASS
6045 18:01:13.900916 RX DQS gating : PASS
6046 18:01:13.904439 RX DQ/DQS(RDDQC) : PASS
6047 18:01:13.907550 TX DQ/DQS : PASS
6048 18:01:13.907659 RX DATLAT : PASS
6049 18:01:13.910578 RX DQ/DQS(Engine): PASS
6050 18:01:13.914191 TX OE : NO K
6051 18:01:13.914306 All Pass.
6052 18:01:13.914400
6053 18:01:13.914493 CH 1, Rank 1
6054 18:01:13.917805 SW Impedance : PASS
6055 18:01:13.920886 DUTY Scan : NO K
6056 18:01:13.920999 ZQ Calibration : PASS
6057 18:01:13.923922 Jitter Meter : NO K
6058 18:01:13.927542 CBT Training : PASS
6059 18:01:13.927648 Write leveling : PASS
6060 18:01:13.930525 RX DQS gating : PASS
6061 18:01:13.930628 RX DQ/DQS(RDDQC) : PASS
6062 18:01:13.934274 TX DQ/DQS : PASS
6063 18:01:13.937405 RX DATLAT : PASS
6064 18:01:13.937511 RX DQ/DQS(Engine): PASS
6065 18:01:13.940928 TX OE : NO K
6066 18:01:13.941045 All Pass.
6067 18:01:13.941138
6068 18:01:13.944434 DramC Write-DBI off
6069 18:01:13.947772 PER_BANK_REFRESH: Hybrid Mode
6070 18:01:13.947894 TX_TRACKING: ON
6071 18:01:13.957872 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6072 18:01:13.960812 [FAST_K] Save calibration result to emmc
6073 18:01:13.964179 dramc_set_vcore_voltage set vcore to 650000
6074 18:01:13.967427 Read voltage for 400, 6
6075 18:01:13.967540 Vio18 = 0
6076 18:01:13.967646 Vcore = 650000
6077 18:01:13.970683 Vdram = 0
6078 18:01:13.970786 Vddq = 0
6079 18:01:13.970878 Vmddr = 0
6080 18:01:13.977337 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6081 18:01:13.981062 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6082 18:01:13.984154 MEM_TYPE=3, freq_sel=20
6083 18:01:13.987522 sv_algorithm_assistance_LP4_800
6084 18:01:13.991003 ============ PULL DRAM RESETB DOWN ============
6085 18:01:13.994235 ========== PULL DRAM RESETB DOWN end =========
6086 18:01:14.000991 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6087 18:01:14.004115 ===================================
6088 18:01:14.004209 LPDDR4 DRAM CONFIGURATION
6089 18:01:14.007288 ===================================
6090 18:01:14.010925 EX_ROW_EN[0] = 0x0
6091 18:01:14.014000 EX_ROW_EN[1] = 0x0
6092 18:01:14.014085 LP4Y_EN = 0x0
6093 18:01:14.017576 WORK_FSP = 0x0
6094 18:01:14.017659 WL = 0x2
6095 18:01:14.020509 RL = 0x2
6096 18:01:14.020592 BL = 0x2
6097 18:01:14.024014 RPST = 0x0
6098 18:01:14.024119 RD_PRE = 0x0
6099 18:01:14.027801 WR_PRE = 0x1
6100 18:01:14.027900 WR_PST = 0x0
6101 18:01:14.030806 DBI_WR = 0x0
6102 18:01:14.030903 DBI_RD = 0x0
6103 18:01:14.033910 OTF = 0x1
6104 18:01:14.037528 ===================================
6105 18:01:14.040703 ===================================
6106 18:01:14.040802 ANA top config
6107 18:01:14.044278 ===================================
6108 18:01:14.047310 DLL_ASYNC_EN = 0
6109 18:01:14.051025 ALL_SLAVE_EN = 1
6110 18:01:14.053720 NEW_RANK_MODE = 1
6111 18:01:14.053831 DLL_IDLE_MODE = 1
6112 18:01:14.057347 LP45_APHY_COMB_EN = 1
6113 18:01:14.060529 TX_ODT_DIS = 1
6114 18:01:14.064242 NEW_8X_MODE = 1
6115 18:01:14.067215 ===================================
6116 18:01:14.070840 ===================================
6117 18:01:14.073826 data_rate = 800
6118 18:01:14.073927 CKR = 1
6119 18:01:14.077350 DQ_P2S_RATIO = 4
6120 18:01:14.080735 ===================================
6121 18:01:14.083856 CA_P2S_RATIO = 4
6122 18:01:14.087481 DQ_CA_OPEN = 0
6123 18:01:14.090656 DQ_SEMI_OPEN = 1
6124 18:01:14.093737 CA_SEMI_OPEN = 1
6125 18:01:14.093807 CA_FULL_RATE = 0
6126 18:01:14.097114 DQ_CKDIV4_EN = 0
6127 18:01:14.100723 CA_CKDIV4_EN = 1
6128 18:01:14.103918 CA_PREDIV_EN = 0
6129 18:01:14.107369 PH8_DLY = 0
6130 18:01:14.107438 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6131 18:01:14.110670 DQ_AAMCK_DIV = 0
6132 18:01:14.114036 CA_AAMCK_DIV = 0
6133 18:01:14.117368 CA_ADMCK_DIV = 4
6134 18:01:14.120397 DQ_TRACK_CA_EN = 0
6135 18:01:14.124134 CA_PICK = 800
6136 18:01:14.127351 CA_MCKIO = 400
6137 18:01:14.127458 MCKIO_SEMI = 400
6138 18:01:14.130484 PLL_FREQ = 3016
6139 18:01:14.134151 DQ_UI_PI_RATIO = 32
6140 18:01:14.137187 CA_UI_PI_RATIO = 32
6141 18:01:14.140907 ===================================
6142 18:01:14.143991 ===================================
6143 18:01:14.147133 memory_type:LPDDR4
6144 18:01:14.147242 GP_NUM : 10
6145 18:01:14.150729 SRAM_EN : 1
6146 18:01:14.153915 MD32_EN : 0
6147 18:01:14.157584 ===================================
6148 18:01:14.157683 [ANA_INIT] >>>>>>>>>>>>>>
6149 18:01:14.160290 <<<<<< [CONFIGURE PHASE]: ANA_TX
6150 18:01:14.163772 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6151 18:01:14.167210 ===================================
6152 18:01:14.170795 data_rate = 800,PCW = 0X7400
6153 18:01:14.173550 ===================================
6154 18:01:14.177214 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6155 18:01:14.183938 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6156 18:01:14.193772 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6157 18:01:14.196877 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6158 18:01:14.203917 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6159 18:01:14.207036 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6160 18:01:14.207150 [ANA_INIT] flow start
6161 18:01:14.210690 [ANA_INIT] PLL >>>>>>>>
6162 18:01:14.213664 [ANA_INIT] PLL <<<<<<<<
6163 18:01:14.213771 [ANA_INIT] MIDPI >>>>>>>>
6164 18:01:14.217336 [ANA_INIT] MIDPI <<<<<<<<
6165 18:01:14.220750 [ANA_INIT] DLL >>>>>>>>
6166 18:01:14.220828 [ANA_INIT] flow end
6167 18:01:14.223668 ============ LP4 DIFF to SE enter ============
6168 18:01:14.230254 ============ LP4 DIFF to SE exit ============
6169 18:01:14.230365 [ANA_INIT] <<<<<<<<<<<<<
6170 18:01:14.233842 [Flow] Enable top DCM control >>>>>
6171 18:01:14.236885 [Flow] Enable top DCM control <<<<<
6172 18:01:14.240506 Enable DLL master slave shuffle
6173 18:01:14.247253 ==============================================================
6174 18:01:14.247363 Gating Mode config
6175 18:01:14.253925 ==============================================================
6176 18:01:14.257035 Config description:
6177 18:01:14.267403 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6178 18:01:14.273494 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6179 18:01:14.277122 SELPH_MODE 0: By rank 1: By Phase
6180 18:01:14.283931 ==============================================================
6181 18:01:14.286984 GAT_TRACK_EN = 0
6182 18:01:14.287092 RX_GATING_MODE = 2
6183 18:01:14.290603 RX_GATING_TRACK_MODE = 2
6184 18:01:14.293736 SELPH_MODE = 1
6185 18:01:14.296857 PICG_EARLY_EN = 1
6186 18:01:14.300404 VALID_LAT_VALUE = 1
6187 18:01:14.306927 ==============================================================
6188 18:01:14.310099 Enter into Gating configuration >>>>
6189 18:01:14.313667 Exit from Gating configuration <<<<
6190 18:01:14.317135 Enter into DVFS_PRE_config >>>>>
6191 18:01:14.327270 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6192 18:01:14.330195 Exit from DVFS_PRE_config <<<<<
6193 18:01:14.333860 Enter into PICG configuration >>>>
6194 18:01:14.337136 Exit from PICG configuration <<<<
6195 18:01:14.340505 [RX_INPUT] configuration >>>>>
6196 18:01:14.340581 [RX_INPUT] configuration <<<<<
6197 18:01:14.347079 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6198 18:01:14.353828 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6199 18:01:14.356970 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6200 18:01:14.363780 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6201 18:01:14.370875 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6202 18:01:14.377337 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6203 18:01:14.380311 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6204 18:01:14.383898 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6205 18:01:14.390828 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6206 18:01:14.393864 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6207 18:01:14.397523 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6208 18:01:14.400654 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6209 18:01:14.403805 ===================================
6210 18:01:14.407448 LPDDR4 DRAM CONFIGURATION
6211 18:01:14.410596 ===================================
6212 18:01:14.414238 EX_ROW_EN[0] = 0x0
6213 18:01:14.414317 EX_ROW_EN[1] = 0x0
6214 18:01:14.417340 LP4Y_EN = 0x0
6215 18:01:14.417415 WORK_FSP = 0x0
6216 18:01:14.420824 WL = 0x2
6217 18:01:14.420923 RL = 0x2
6218 18:01:14.424195 BL = 0x2
6219 18:01:14.424298 RPST = 0x0
6220 18:01:14.427159 RD_PRE = 0x0
6221 18:01:14.427236 WR_PRE = 0x1
6222 18:01:14.430700 WR_PST = 0x0
6223 18:01:14.430812 DBI_WR = 0x0
6224 18:01:14.433848 DBI_RD = 0x0
6225 18:01:14.437284 OTF = 0x1
6226 18:01:14.440838 ===================================
6227 18:01:14.444185 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6228 18:01:14.447672 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6229 18:01:14.451030 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6230 18:01:14.454105 ===================================
6231 18:01:14.457751 LPDDR4 DRAM CONFIGURATION
6232 18:01:14.460777 ===================================
6233 18:01:14.463837 EX_ROW_EN[0] = 0x10
6234 18:01:14.463948 EX_ROW_EN[1] = 0x0
6235 18:01:14.467480 LP4Y_EN = 0x0
6236 18:01:14.467583 WORK_FSP = 0x0
6237 18:01:14.470604 WL = 0x2
6238 18:01:14.470706 RL = 0x2
6239 18:01:14.474091 BL = 0x2
6240 18:01:14.474166 RPST = 0x0
6241 18:01:14.477595 RD_PRE = 0x0
6242 18:01:14.477698 WR_PRE = 0x1
6243 18:01:14.480640 WR_PST = 0x0
6244 18:01:14.480744 DBI_WR = 0x0
6245 18:01:14.483730 DBI_RD = 0x0
6246 18:01:14.483834 OTF = 0x1
6247 18:01:14.487382 ===================================
6248 18:01:14.494005 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6249 18:01:14.498682 nWR fixed to 30
6250 18:01:14.501679 [ModeRegInit_LP4] CH0 RK0
6251 18:01:14.501758 [ModeRegInit_LP4] CH0 RK1
6252 18:01:14.505361 [ModeRegInit_LP4] CH1 RK0
6253 18:01:14.508864 [ModeRegInit_LP4] CH1 RK1
6254 18:01:14.508968 match AC timing 19
6255 18:01:14.515034 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6256 18:01:14.518606 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6257 18:01:14.521829 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6258 18:01:14.528641 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6259 18:01:14.531657 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6260 18:01:14.531768 ==
6261 18:01:14.535128 Dram Type= 6, Freq= 0, CH_0, rank 0
6262 18:01:14.538245 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6263 18:01:14.538324 ==
6264 18:01:14.545632 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6265 18:01:14.552059 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6266 18:01:14.554989 [CA 0] Center 36 (8~64) winsize 57
6267 18:01:14.558284 [CA 1] Center 36 (8~64) winsize 57
6268 18:01:14.558368 [CA 2] Center 36 (8~64) winsize 57
6269 18:01:14.561597 [CA 3] Center 36 (8~64) winsize 57
6270 18:01:14.565006 [CA 4] Center 36 (8~64) winsize 57
6271 18:01:14.568771 [CA 5] Center 36 (8~64) winsize 57
6272 18:01:14.568877
6273 18:01:14.571552 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6274 18:01:14.575190
6275 18:01:14.578604 [CATrainingPosCal] consider 1 rank data
6276 18:01:14.578721 u2DelayCellTimex100 = 270/100 ps
6277 18:01:14.585238 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6278 18:01:14.588800 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6279 18:01:14.591899 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6280 18:01:14.594991 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6281 18:01:14.598529 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6282 18:01:14.601593 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6283 18:01:14.601696
6284 18:01:14.605109 CA PerBit enable=1, Macro0, CA PI delay=36
6285 18:01:14.605190
6286 18:01:14.608658 [CBTSetCACLKResult] CA Dly = 36
6287 18:01:14.611734 CS Dly: 1 (0~32)
6288 18:01:14.611808 ==
6289 18:01:14.614913 Dram Type= 6, Freq= 0, CH_0, rank 1
6290 18:01:14.618577 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6291 18:01:14.618680 ==
6292 18:01:14.625331 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6293 18:01:14.628293 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6294 18:01:14.631466 [CA 0] Center 36 (8~64) winsize 57
6295 18:01:14.635145 [CA 1] Center 36 (8~64) winsize 57
6296 18:01:14.638220 [CA 2] Center 36 (8~64) winsize 57
6297 18:01:14.641957 [CA 3] Center 36 (8~64) winsize 57
6298 18:01:14.644965 [CA 4] Center 36 (8~64) winsize 57
6299 18:01:14.648139 [CA 5] Center 36 (8~64) winsize 57
6300 18:01:14.648245
6301 18:01:14.651889 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6302 18:01:14.651966
6303 18:01:14.654705 [CATrainingPosCal] consider 2 rank data
6304 18:01:14.658561 u2DelayCellTimex100 = 270/100 ps
6305 18:01:14.661838 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6306 18:01:14.664773 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6307 18:01:14.668227 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6308 18:01:14.671810 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6309 18:01:14.678269 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6310 18:01:14.681870 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6311 18:01:14.682000
6312 18:01:14.684857 CA PerBit enable=1, Macro0, CA PI delay=36
6313 18:01:14.684964
6314 18:01:14.688310 [CBTSetCACLKResult] CA Dly = 36
6315 18:01:14.688413 CS Dly: 1 (0~32)
6316 18:01:14.688504
6317 18:01:14.691324 ----->DramcWriteLeveling(PI) begin...
6318 18:01:14.691430 ==
6319 18:01:14.694856 Dram Type= 6, Freq= 0, CH_0, rank 0
6320 18:01:14.701833 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6321 18:01:14.701940 ==
6322 18:01:14.704733 Write leveling (Byte 0): 40 => 8
6323 18:01:14.704829 Write leveling (Byte 1): 32 => 0
6324 18:01:14.708380 DramcWriteLeveling(PI) end<-----
6325 18:01:14.708485
6326 18:01:14.708580 ==
6327 18:01:14.711403 Dram Type= 6, Freq= 0, CH_0, rank 0
6328 18:01:14.718256 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6329 18:01:14.718349 ==
6330 18:01:14.721427 [Gating] SW mode calibration
6331 18:01:14.728390 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6332 18:01:14.731553 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6333 18:01:14.738428 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6334 18:01:14.741622 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6335 18:01:14.745289 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6336 18:01:14.748432 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6337 18:01:14.755214 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6338 18:01:14.758527 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6339 18:01:14.761618 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6340 18:01:14.768247 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6341 18:01:14.771429 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6342 18:01:14.774744 Total UI for P1: 0, mck2ui 16
6343 18:01:14.778353 best dqsien dly found for B0: ( 0, 14, 24)
6344 18:01:14.781333 Total UI for P1: 0, mck2ui 16
6345 18:01:14.785147 best dqsien dly found for B1: ( 0, 14, 24)
6346 18:01:14.788164 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6347 18:01:14.791932 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6348 18:01:14.792017
6349 18:01:14.795086 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6350 18:01:14.798082 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6351 18:01:14.801502 [Gating] SW calibration Done
6352 18:01:14.801584 ==
6353 18:01:14.804711 Dram Type= 6, Freq= 0, CH_0, rank 0
6354 18:01:14.811567 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6355 18:01:14.811654 ==
6356 18:01:14.811723 RX Vref Scan: 0
6357 18:01:14.811785
6358 18:01:14.814607 RX Vref 0 -> 0, step: 1
6359 18:01:14.814693
6360 18:01:14.818331 RX Delay -410 -> 252, step: 16
6361 18:01:14.821427 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6362 18:01:14.824807 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6363 18:01:14.831426 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6364 18:01:14.834787 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6365 18:01:14.838171 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6366 18:01:14.841527 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6367 18:01:14.847711 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6368 18:01:14.851459 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6369 18:01:14.854434 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6370 18:01:14.858198 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6371 18:01:14.864879 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6372 18:01:14.867949 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6373 18:01:14.871565 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6374 18:01:14.874540 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6375 18:01:14.881118 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6376 18:01:14.884373 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6377 18:01:14.884449 ==
6378 18:01:14.888056 Dram Type= 6, Freq= 0, CH_0, rank 0
6379 18:01:14.891134 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6380 18:01:14.891221 ==
6381 18:01:14.894753 DQS Delay:
6382 18:01:14.894829 DQS0 = 35, DQS1 = 51
6383 18:01:14.897916 DQM Delay:
6384 18:01:14.897987 DQM0 = 6, DQM1 = 10
6385 18:01:14.898052 DQ Delay:
6386 18:01:14.900889 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =0
6387 18:01:14.904484 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6388 18:01:14.908171 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6389 18:01:14.911255 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6390 18:01:14.911324
6391 18:01:14.911384
6392 18:01:14.911442 ==
6393 18:01:14.914282 Dram Type= 6, Freq= 0, CH_0, rank 0
6394 18:01:14.917857 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6395 18:01:14.920872 ==
6396 18:01:14.920969
6397 18:01:14.921078
6398 18:01:14.921138 TX Vref Scan disable
6399 18:01:14.924401 == TX Byte 0 ==
6400 18:01:14.927349 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6401 18:01:14.931070 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6402 18:01:14.934377 == TX Byte 1 ==
6403 18:01:14.937755 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6404 18:01:14.940790 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6405 18:01:14.940862 ==
6406 18:01:14.944420 Dram Type= 6, Freq= 0, CH_0, rank 0
6407 18:01:14.947709 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6408 18:01:14.950682 ==
6409 18:01:14.950764
6410 18:01:14.950850
6411 18:01:14.950915 TX Vref Scan disable
6412 18:01:14.954328 == TX Byte 0 ==
6413 18:01:14.957748 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6414 18:01:14.960877 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6415 18:01:14.964389 == TX Byte 1 ==
6416 18:01:14.968011 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6417 18:01:14.971236 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6418 18:01:14.971312
6419 18:01:14.974245 [DATLAT]
6420 18:01:14.974319 Freq=400, CH0 RK0
6421 18:01:14.974381
6422 18:01:14.977926 DATLAT Default: 0xf
6423 18:01:14.978009 0, 0xFFFF, sum = 0
6424 18:01:14.980927 1, 0xFFFF, sum = 0
6425 18:01:14.981025 2, 0xFFFF, sum = 0
6426 18:01:14.984126 3, 0xFFFF, sum = 0
6427 18:01:14.984198 4, 0xFFFF, sum = 0
6428 18:01:14.987728 5, 0xFFFF, sum = 0
6429 18:01:14.987802 6, 0xFFFF, sum = 0
6430 18:01:14.991068 7, 0xFFFF, sum = 0
6431 18:01:14.991135 8, 0xFFFF, sum = 0
6432 18:01:14.994741 9, 0xFFFF, sum = 0
6433 18:01:14.994813 10, 0xFFFF, sum = 0
6434 18:01:14.997756 11, 0xFFFF, sum = 0
6435 18:01:14.997828 12, 0xFFFF, sum = 0
6436 18:01:15.000784 13, 0x0, sum = 1
6437 18:01:15.000850 14, 0x0, sum = 2
6438 18:01:15.004503 15, 0x0, sum = 3
6439 18:01:15.004575 16, 0x0, sum = 4
6440 18:01:15.007611 best_step = 14
6441 18:01:15.007684
6442 18:01:15.007743 ==
6443 18:01:15.011330 Dram Type= 6, Freq= 0, CH_0, rank 0
6444 18:01:15.014353 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6445 18:01:15.014424 ==
6446 18:01:15.017999 RX Vref Scan: 1
6447 18:01:15.018071
6448 18:01:15.018135 RX Vref 0 -> 0, step: 1
6449 18:01:15.018193
6450 18:01:15.021139 RX Delay -343 -> 252, step: 8
6451 18:01:15.021207
6452 18:01:15.024593 Set Vref, RX VrefLevel [Byte0]: 52
6453 18:01:15.027514 [Byte1]: 52
6454 18:01:15.032177
6455 18:01:15.032263 Final RX Vref Byte 0 = 52 to rank0
6456 18:01:15.035944 Final RX Vref Byte 1 = 52 to rank0
6457 18:01:15.038909 Final RX Vref Byte 0 = 52 to rank1
6458 18:01:15.042579 Final RX Vref Byte 1 = 52 to rank1==
6459 18:01:15.045581 Dram Type= 6, Freq= 0, CH_0, rank 0
6460 18:01:15.052070 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6461 18:01:15.052163 ==
6462 18:01:15.052272 DQS Delay:
6463 18:01:15.052335 DQS0 = 44, DQS1 = 60
6464 18:01:15.055971 DQM Delay:
6465 18:01:15.056056 DQM0 = 10, DQM1 = 15
6466 18:01:15.058781 DQ Delay:
6467 18:01:15.062207 DQ0 =12, DQ1 =12, DQ2 =4, DQ3 =8
6468 18:01:15.062284 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =20
6469 18:01:15.065720 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =12
6470 18:01:15.068922 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =24
6471 18:01:15.069026
6472 18:01:15.072429
6473 18:01:15.079064 [DQSOSCAuto] RK0, (LSB)MR18= 0x8453, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 393 ps
6474 18:01:15.082224 CH0 RK0: MR19=C0C, MR18=8453
6475 18:01:15.089256 CH0_RK0: MR19=0xC0C, MR18=0x8453, DQSOSC=393, MR23=63, INC=382, DEC=254
6476 18:01:15.089351 ==
6477 18:01:15.092322 Dram Type= 6, Freq= 0, CH_0, rank 1
6478 18:01:15.095867 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6479 18:01:15.095946 ==
6480 18:01:15.099143 [Gating] SW mode calibration
6481 18:01:15.105900 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6482 18:01:15.109012 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6483 18:01:15.115745 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6484 18:01:15.118833 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6485 18:01:15.121959 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6486 18:01:15.128802 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6487 18:01:15.132307 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6488 18:01:15.135272 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6489 18:01:15.141982 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6490 18:01:15.145657 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6491 18:01:15.148661 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6492 18:01:15.152445 Total UI for P1: 0, mck2ui 16
6493 18:01:15.155522 best dqsien dly found for B0: ( 0, 14, 24)
6494 18:01:15.159001 Total UI for P1: 0, mck2ui 16
6495 18:01:15.161922 best dqsien dly found for B1: ( 0, 14, 24)
6496 18:01:15.165315 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6497 18:01:15.168604 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6498 18:01:15.168684
6499 18:01:15.175571 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6500 18:01:15.178640 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6501 18:01:15.181764 [Gating] SW calibration Done
6502 18:01:15.181836 ==
6503 18:01:15.185455 Dram Type= 6, Freq= 0, CH_0, rank 1
6504 18:01:15.188567 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6505 18:01:15.188645 ==
6506 18:01:15.188707 RX Vref Scan: 0
6507 18:01:15.188766
6508 18:01:15.192127 RX Vref 0 -> 0, step: 1
6509 18:01:15.192195
6510 18:01:15.195406 RX Delay -410 -> 252, step: 16
6511 18:01:15.198642 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6512 18:01:15.205507 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6513 18:01:15.209501 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6514 18:01:15.212032 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6515 18:01:15.215095 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6516 18:01:15.222212 iDelay=230, Bit 5, Center -43 (-282 ~ 197) 480
6517 18:01:15.225233 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6518 18:01:15.228958 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6519 18:01:15.232123 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6520 18:01:15.238682 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6521 18:01:15.241826 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6522 18:01:15.244911 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6523 18:01:15.248553 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6524 18:01:15.255309 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6525 18:01:15.258287 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6526 18:01:15.261893 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6527 18:01:15.261972 ==
6528 18:01:15.264757 Dram Type= 6, Freq= 0, CH_0, rank 1
6529 18:01:15.271556 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6530 18:01:15.271635 ==
6531 18:01:15.271700 DQS Delay:
6532 18:01:15.271764 DQS0 = 43, DQS1 = 51
6533 18:01:15.275144 DQM Delay:
6534 18:01:15.275218 DQM0 = 11, DQM1 = 10
6535 18:01:15.277949 DQ Delay:
6536 18:01:15.281396 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6537 18:01:15.281474 DQ4 =8, DQ5 =0, DQ6 =24, DQ7 =24
6538 18:01:15.284897 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6539 18:01:15.287981 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6540 18:01:15.288054
6541 18:01:15.288120
6542 18:01:15.291528 ==
6543 18:01:15.291605 Dram Type= 6, Freq= 0, CH_0, rank 1
6544 18:01:15.298236 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6545 18:01:15.298313 ==
6546 18:01:15.298375
6547 18:01:15.298450
6548 18:01:15.301249 TX Vref Scan disable
6549 18:01:15.301321 == TX Byte 0 ==
6550 18:01:15.304819 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6551 18:01:15.311488 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6552 18:01:15.311567 == TX Byte 1 ==
6553 18:01:15.314528 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6554 18:01:15.317946 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6555 18:01:15.321702 ==
6556 18:01:15.324940 Dram Type= 6, Freq= 0, CH_0, rank 1
6557 18:01:15.328506 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6558 18:01:15.328581 ==
6559 18:01:15.328644
6560 18:01:15.328705
6561 18:01:15.331318 TX Vref Scan disable
6562 18:01:15.331397 == TX Byte 0 ==
6563 18:01:15.334916 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6564 18:01:15.338219 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6565 18:01:15.341492 == TX Byte 1 ==
6566 18:01:15.345091 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6567 18:01:15.348015 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6568 18:01:15.348099
6569 18:01:15.351709 [DATLAT]
6570 18:01:15.351784 Freq=400, CH0 RK1
6571 18:01:15.351886
6572 18:01:15.354790 DATLAT Default: 0xe
6573 18:01:15.354870 0, 0xFFFF, sum = 0
6574 18:01:15.358520 1, 0xFFFF, sum = 0
6575 18:01:15.358601 2, 0xFFFF, sum = 0
6576 18:01:15.361513 3, 0xFFFF, sum = 0
6577 18:01:15.361587 4, 0xFFFF, sum = 0
6578 18:01:15.364671 5, 0xFFFF, sum = 0
6579 18:01:15.364751 6, 0xFFFF, sum = 0
6580 18:01:15.368250 7, 0xFFFF, sum = 0
6581 18:01:15.368339 8, 0xFFFF, sum = 0
6582 18:01:15.371273 9, 0xFFFF, sum = 0
6583 18:01:15.374588 10, 0xFFFF, sum = 0
6584 18:01:15.374664 11, 0xFFFF, sum = 0
6585 18:01:15.377920 12, 0xFFFF, sum = 0
6586 18:01:15.378001 13, 0x0, sum = 1
6587 18:01:15.381546 14, 0x0, sum = 2
6588 18:01:15.381625 15, 0x0, sum = 3
6589 18:01:15.381693 16, 0x0, sum = 4
6590 18:01:15.385121 best_step = 14
6591 18:01:15.385204
6592 18:01:15.385271 ==
6593 18:01:15.387988 Dram Type= 6, Freq= 0, CH_0, rank 1
6594 18:01:15.391580 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6595 18:01:15.391662 ==
6596 18:01:15.394573 RX Vref Scan: 0
6597 18:01:15.394654
6598 18:01:15.398265 RX Vref 0 -> 0, step: 1
6599 18:01:15.398339
6600 18:01:15.398406 RX Delay -343 -> 252, step: 8
6601 18:01:15.406623 iDelay=217, Bit 0, Center -32 (-271 ~ 208) 480
6602 18:01:15.409753 iDelay=217, Bit 1, Center -32 (-271 ~ 208) 480
6603 18:01:15.413317 iDelay=217, Bit 2, Center -36 (-271 ~ 200) 472
6604 18:01:15.416863 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6605 18:01:15.423566 iDelay=217, Bit 4, Center -36 (-271 ~ 200) 472
6606 18:01:15.426638 iDelay=217, Bit 5, Center -48 (-287 ~ 192) 480
6607 18:01:15.430408 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6608 18:01:15.433276 iDelay=217, Bit 7, Center -32 (-271 ~ 208) 480
6609 18:01:15.439847 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6610 18:01:15.443441 iDelay=217, Bit 9, Center -56 (-295 ~ 184) 480
6611 18:01:15.446785 iDelay=217, Bit 10, Center -40 (-279 ~ 200) 480
6612 18:01:15.449928 iDelay=217, Bit 11, Center -56 (-295 ~ 184) 480
6613 18:01:15.456476 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6614 18:01:15.459736 iDelay=217, Bit 13, Center -40 (-279 ~ 200) 480
6615 18:01:15.462995 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6616 18:01:15.470054 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6617 18:01:15.470143 ==
6618 18:01:15.473038 Dram Type= 6, Freq= 0, CH_0, rank 1
6619 18:01:15.476039 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6620 18:01:15.476121 ==
6621 18:01:15.476187 DQS Delay:
6622 18:01:15.479500 DQS0 = 48, DQS1 = 60
6623 18:01:15.479574 DQM Delay:
6624 18:01:15.482891 DQM0 = 13, DQM1 = 14
6625 18:01:15.482974 DQ Delay:
6626 18:01:15.486204 DQ0 =16, DQ1 =16, DQ2 =12, DQ3 =12
6627 18:01:15.489800 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6628 18:01:15.492765 DQ8 =0, DQ9 =4, DQ10 =20, DQ11 =4
6629 18:01:15.496361 DQ12 =16, DQ13 =20, DQ14 =24, DQ15 =24
6630 18:01:15.496443
6631 18:01:15.496509
6632 18:01:15.502991 [DQSOSCAuto] RK1, (LSB)MR18= 0x9265, (MSB)MR19= 0xc0c, tDQSOscB0 = 397 ps tDQSOscB1 = 391 ps
6633 18:01:15.506076 CH0 RK1: MR19=C0C, MR18=9265
6634 18:01:15.512732 CH0_RK1: MR19=0xC0C, MR18=0x9265, DQSOSC=391, MR23=63, INC=386, DEC=257
6635 18:01:15.516344 [RxdqsGatingPostProcess] freq 400
6636 18:01:15.522979 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6637 18:01:15.526045 best DQS0 dly(2T, 0.5T) = (0, 10)
6638 18:01:15.526118 best DQS1 dly(2T, 0.5T) = (0, 10)
6639 18:01:15.529730 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6640 18:01:15.532712 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6641 18:01:15.536315 best DQS0 dly(2T, 0.5T) = (0, 10)
6642 18:01:15.539382 best DQS1 dly(2T, 0.5T) = (0, 10)
6643 18:01:15.543068 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6644 18:01:15.545972 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6645 18:01:15.549276 Pre-setting of DQS Precalculation
6646 18:01:15.556050 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6647 18:01:15.556130 ==
6648 18:01:15.559730 Dram Type= 6, Freq= 0, CH_1, rank 0
6649 18:01:15.562629 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6650 18:01:15.562705 ==
6651 18:01:15.568970 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6652 18:01:15.572413 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6653 18:01:15.575770 [CA 0] Center 36 (8~64) winsize 57
6654 18:01:15.578936 [CA 1] Center 36 (8~64) winsize 57
6655 18:01:15.582697 [CA 2] Center 36 (8~64) winsize 57
6656 18:01:15.585865 [CA 3] Center 36 (8~64) winsize 57
6657 18:01:15.589613 [CA 4] Center 36 (8~64) winsize 57
6658 18:01:15.592501 [CA 5] Center 36 (8~64) winsize 57
6659 18:01:15.592576
6660 18:01:15.596373 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6661 18:01:15.596445
6662 18:01:15.599305 [CATrainingPosCal] consider 1 rank data
6663 18:01:15.602552 u2DelayCellTimex100 = 270/100 ps
6664 18:01:15.606002 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6665 18:01:15.609281 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6666 18:01:15.612709 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6667 18:01:15.616266 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6668 18:01:15.622892 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6669 18:01:15.625836 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6670 18:01:15.625911
6671 18:01:15.629405 CA PerBit enable=1, Macro0, CA PI delay=36
6672 18:01:15.629473
6673 18:01:15.632522 [CBTSetCACLKResult] CA Dly = 36
6674 18:01:15.632595 CS Dly: 1 (0~32)
6675 18:01:15.632656 ==
6676 18:01:15.636139 Dram Type= 6, Freq= 0, CH_1, rank 1
6677 18:01:15.642856 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6678 18:01:15.642935 ==
6679 18:01:15.645911 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6680 18:01:15.652484 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6681 18:01:15.656030 [CA 0] Center 36 (8~64) winsize 57
6682 18:01:15.659006 [CA 1] Center 36 (8~64) winsize 57
6683 18:01:15.662768 [CA 2] Center 36 (8~64) winsize 57
6684 18:01:15.665726 [CA 3] Center 36 (8~64) winsize 57
6685 18:01:15.669326 [CA 4] Center 36 (8~64) winsize 57
6686 18:01:15.672331 [CA 5] Center 36 (8~64) winsize 57
6687 18:01:15.672404
6688 18:01:15.675904 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6689 18:01:15.675979
6690 18:01:15.679017 [CATrainingPosCal] consider 2 rank data
6691 18:01:15.682672 u2DelayCellTimex100 = 270/100 ps
6692 18:01:15.685621 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6693 18:01:15.689138 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6694 18:01:15.692497 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6695 18:01:15.695544 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6696 18:01:15.699063 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6697 18:01:15.702728 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6698 18:01:15.702802
6699 18:01:15.709189 CA PerBit enable=1, Macro0, CA PI delay=36
6700 18:01:15.709270
6701 18:01:15.709335 [CBTSetCACLKResult] CA Dly = 36
6702 18:01:15.712582 CS Dly: 1 (0~32)
6703 18:01:15.712664
6704 18:01:15.715447 ----->DramcWriteLeveling(PI) begin...
6705 18:01:15.715523 ==
6706 18:01:15.719082 Dram Type= 6, Freq= 0, CH_1, rank 0
6707 18:01:15.722263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6708 18:01:15.722338 ==
6709 18:01:15.725748 Write leveling (Byte 0): 40 => 8
6710 18:01:15.728898 Write leveling (Byte 1): 40 => 8
6711 18:01:15.732374 DramcWriteLeveling(PI) end<-----
6712 18:01:15.732453
6713 18:01:15.732520 ==
6714 18:01:15.735721 Dram Type= 6, Freq= 0, CH_1, rank 0
6715 18:01:15.739292 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6716 18:01:15.739371 ==
6717 18:01:15.742489 [Gating] SW mode calibration
6718 18:01:15.748963 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6719 18:01:15.755644 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6720 18:01:15.759014 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6721 18:01:15.765650 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6722 18:01:15.769335 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6723 18:01:15.772261 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6724 18:01:15.778788 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6725 18:01:15.782417 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6726 18:01:15.785978 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6727 18:01:15.792050 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6728 18:01:15.795410 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6729 18:01:15.799127 Total UI for P1: 0, mck2ui 16
6730 18:01:15.802183 best dqsien dly found for B0: ( 0, 14, 24)
6731 18:01:15.805703 Total UI for P1: 0, mck2ui 16
6732 18:01:15.809309 best dqsien dly found for B1: ( 0, 14, 24)
6733 18:01:15.812208 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6734 18:01:15.815738 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6735 18:01:15.815835
6736 18:01:15.818785 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6737 18:01:15.822279 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6738 18:01:15.825992 [Gating] SW calibration Done
6739 18:01:15.826067 ==
6740 18:01:15.829030 Dram Type= 6, Freq= 0, CH_1, rank 0
6741 18:01:15.832442 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6742 18:01:15.832524 ==
6743 18:01:15.835797 RX Vref Scan: 0
6744 18:01:15.835869
6745 18:01:15.835930 RX Vref 0 -> 0, step: 1
6746 18:01:15.839057
6747 18:01:15.839126 RX Delay -410 -> 252, step: 16
6748 18:01:15.845884 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6749 18:01:15.849168 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6750 18:01:15.852618 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6751 18:01:15.855898 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6752 18:01:15.862385 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6753 18:01:15.866250 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6754 18:01:15.869309 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6755 18:01:15.873110 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6756 18:01:15.878883 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6757 18:01:15.882468 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6758 18:01:15.886205 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6759 18:01:15.888997 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6760 18:01:15.895732 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6761 18:01:15.899238 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6762 18:01:15.902828 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6763 18:01:15.905862 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6764 18:01:15.905934 ==
6765 18:01:15.909534 Dram Type= 6, Freq= 0, CH_1, rank 0
6766 18:01:15.916234 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6767 18:01:15.916310 ==
6768 18:01:15.916373 DQS Delay:
6769 18:01:15.919137 DQS0 = 51, DQS1 = 59
6770 18:01:15.919243 DQM Delay:
6771 18:01:15.922814 DQM0 = 19, DQM1 = 17
6772 18:01:15.922889 DQ Delay:
6773 18:01:15.925802 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6774 18:01:15.929429 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6775 18:01:15.932441 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6776 18:01:15.936088 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6777 18:01:15.936161
6778 18:01:15.936222
6779 18:01:15.936288 ==
6780 18:01:15.939516 Dram Type= 6, Freq= 0, CH_1, rank 0
6781 18:01:15.942330 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6782 18:01:15.942406 ==
6783 18:01:15.942471
6784 18:01:15.942529
6785 18:01:15.945813 TX Vref Scan disable
6786 18:01:15.945887 == TX Byte 0 ==
6787 18:01:15.952492 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6788 18:01:15.955909 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6789 18:01:15.955992 == TX Byte 1 ==
6790 18:01:15.962822 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6791 18:01:15.965675 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6792 18:01:15.965758 ==
6793 18:01:15.968961 Dram Type= 6, Freq= 0, CH_1, rank 0
6794 18:01:15.972365 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6795 18:01:15.972448 ==
6796 18:01:15.972512
6797 18:01:15.972571
6798 18:01:15.976041 TX Vref Scan disable
6799 18:01:15.976123 == TX Byte 0 ==
6800 18:01:15.982630 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6801 18:01:15.986055 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6802 18:01:15.986138 == TX Byte 1 ==
6803 18:01:15.992678 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6804 18:01:15.995688 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6805 18:01:15.995788
6806 18:01:15.995853 [DATLAT]
6807 18:01:15.999311 Freq=400, CH1 RK0
6808 18:01:15.999441
6809 18:01:15.999535 DATLAT Default: 0xf
6810 18:01:16.002221 0, 0xFFFF, sum = 0
6811 18:01:16.002304 1, 0xFFFF, sum = 0
6812 18:01:16.005641 2, 0xFFFF, sum = 0
6813 18:01:16.005723 3, 0xFFFF, sum = 0
6814 18:01:16.009279 4, 0xFFFF, sum = 0
6815 18:01:16.009378 5, 0xFFFF, sum = 0
6816 18:01:16.012267 6, 0xFFFF, sum = 0
6817 18:01:16.012364 7, 0xFFFF, sum = 0
6818 18:01:16.015833 8, 0xFFFF, sum = 0
6819 18:01:16.015917 9, 0xFFFF, sum = 0
6820 18:01:16.018883 10, 0xFFFF, sum = 0
6821 18:01:16.018959 11, 0xFFFF, sum = 0
6822 18:01:16.022530 12, 0xFFFF, sum = 0
6823 18:01:16.022785 13, 0x0, sum = 1
6824 18:01:16.025898 14, 0x0, sum = 2
6825 18:01:16.025975 15, 0x0, sum = 3
6826 18:01:16.029609 16, 0x0, sum = 4
6827 18:01:16.029749 best_step = 14
6828 18:01:16.029817
6829 18:01:16.029877 ==
6830 18:01:16.032696 Dram Type= 6, Freq= 0, CH_1, rank 0
6831 18:01:16.039570 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6832 18:01:16.039761 ==
6833 18:01:16.039865 RX Vref Scan: 1
6834 18:01:16.039960
6835 18:01:16.042385 RX Vref 0 -> 0, step: 1
6836 18:01:16.042456
6837 18:01:16.045787 RX Delay -359 -> 252, step: 8
6838 18:01:16.045885
6839 18:01:16.049182 Set Vref, RX VrefLevel [Byte0]: 60
6840 18:01:16.052557 [Byte1]: 52
6841 18:01:16.055488
6842 18:01:16.055565 Final RX Vref Byte 0 = 60 to rank0
6843 18:01:16.059148 Final RX Vref Byte 1 = 52 to rank0
6844 18:01:16.062194 Final RX Vref Byte 0 = 60 to rank1
6845 18:01:16.065669 Final RX Vref Byte 1 = 52 to rank1==
6846 18:01:16.068924 Dram Type= 6, Freq= 0, CH_1, rank 0
6847 18:01:16.075668 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6848 18:01:16.075756 ==
6849 18:01:16.075857 DQS Delay:
6850 18:01:16.079212 DQS0 = 48, DQS1 = 60
6851 18:01:16.079318 DQM Delay:
6852 18:01:16.079385 DQM0 = 12, DQM1 = 13
6853 18:01:16.082102 DQ Delay:
6854 18:01:16.085472 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6855 18:01:16.085556 DQ4 =8, DQ5 =20, DQ6 =24, DQ7 =12
6856 18:01:16.089298 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =12
6857 18:01:16.092366 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20
6858 18:01:16.092447
6859 18:01:16.095715
6860 18:01:16.102320 [DQSOSCAuto] RK0, (LSB)MR18= 0x842b, (MSB)MR19= 0xc0c, tDQSOscB0 = 404 ps tDQSOscB1 = 393 ps
6861 18:01:16.105997 CH1 RK0: MR19=C0C, MR18=842B
6862 18:01:16.112381 CH1_RK0: MR19=0xC0C, MR18=0x842B, DQSOSC=393, MR23=63, INC=382, DEC=254
6863 18:01:16.112463 ==
6864 18:01:16.115404 Dram Type= 6, Freq= 0, CH_1, rank 1
6865 18:01:16.119074 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6866 18:01:16.119153 ==
6867 18:01:16.122625 [Gating] SW mode calibration
6868 18:01:16.128797 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6869 18:01:16.132259 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6870 18:01:16.138870 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6871 18:01:16.142485 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6872 18:01:16.145565 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6873 18:01:16.152500 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6874 18:01:16.155887 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6875 18:01:16.158830 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6876 18:01:16.165614 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6877 18:01:16.169059 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6878 18:01:16.172007 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6879 18:01:16.175829 Total UI for P1: 0, mck2ui 16
6880 18:01:16.178946 best dqsien dly found for B0: ( 0, 14, 24)
6881 18:01:16.182522 Total UI for P1: 0, mck2ui 16
6882 18:01:16.185468 best dqsien dly found for B1: ( 0, 14, 24)
6883 18:01:16.189244 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6884 18:01:16.192327 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6885 18:01:16.192409
6886 18:01:16.199162 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6887 18:01:16.202469 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6888 18:01:16.205401 [Gating] SW calibration Done
6889 18:01:16.205477 ==
6890 18:01:16.208854 Dram Type= 6, Freq= 0, CH_1, rank 1
6891 18:01:16.212229 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6892 18:01:16.212344 ==
6893 18:01:16.212485 RX Vref Scan: 0
6894 18:01:16.212585
6895 18:01:16.215343 RX Vref 0 -> 0, step: 1
6896 18:01:16.215442
6897 18:01:16.218694 RX Delay -410 -> 252, step: 16
6898 18:01:16.222541 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6899 18:01:16.226054 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6900 18:01:16.232746 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6901 18:01:16.235708 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6902 18:01:16.239189 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6903 18:01:16.242606 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6904 18:01:16.249193 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6905 18:01:16.252258 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6906 18:01:16.255864 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6907 18:01:16.259254 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6908 18:01:16.266003 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6909 18:01:16.269081 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6910 18:01:16.272175 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6911 18:01:16.275757 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6912 18:01:16.282362 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6913 18:01:16.285963 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6914 18:01:16.286045 ==
6915 18:01:16.289161 Dram Type= 6, Freq= 0, CH_1, rank 1
6916 18:01:16.292498 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6917 18:01:16.292587 ==
6918 18:01:16.295595 DQS Delay:
6919 18:01:16.295670 DQS0 = 51, DQS1 = 59
6920 18:01:16.299250 DQM Delay:
6921 18:01:16.299327 DQM0 = 17, DQM1 = 18
6922 18:01:16.299389 DQ Delay:
6923 18:01:16.302310 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =16
6924 18:01:16.305394 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6925 18:01:16.308831 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6926 18:01:16.312405 DQ12 =24, DQ13 =32, DQ14 =32, DQ15 =32
6927 18:01:16.312479
6928 18:01:16.312548
6929 18:01:16.312611 ==
6930 18:01:16.315710 Dram Type= 6, Freq= 0, CH_1, rank 1
6931 18:01:16.322085 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6932 18:01:16.322167 ==
6933 18:01:16.322237
6934 18:01:16.322298
6935 18:01:16.322356 TX Vref Scan disable
6936 18:01:16.325873 == TX Byte 0 ==
6937 18:01:16.328965 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6938 18:01:16.332244 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6939 18:01:16.335829 == TX Byte 1 ==
6940 18:01:16.338927 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6941 18:01:16.342400 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6942 18:01:16.342473 ==
6943 18:01:16.346100 Dram Type= 6, Freq= 0, CH_1, rank 1
6944 18:01:16.352509 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6945 18:01:16.352602 ==
6946 18:01:16.352669
6947 18:01:16.352731
6948 18:01:16.352797 TX Vref Scan disable
6949 18:01:16.356232 == TX Byte 0 ==
6950 18:01:16.359456 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6951 18:01:16.362481 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6952 18:01:16.365982 == TX Byte 1 ==
6953 18:01:16.369348 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6954 18:01:16.372250 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6955 18:01:16.372328
6956 18:01:16.375845 [DATLAT]
6957 18:01:16.375918 Freq=400, CH1 RK1
6958 18:01:16.375987
6959 18:01:16.378870 DATLAT Default: 0xe
6960 18:01:16.378942 0, 0xFFFF, sum = 0
6961 18:01:16.382447 1, 0xFFFF, sum = 0
6962 18:01:16.382526 2, 0xFFFF, sum = 0
6963 18:01:16.386028 3, 0xFFFF, sum = 0
6964 18:01:16.386104 4, 0xFFFF, sum = 0
6965 18:01:16.389034 5, 0xFFFF, sum = 0
6966 18:01:16.389107 6, 0xFFFF, sum = 0
6967 18:01:16.392706 7, 0xFFFF, sum = 0
6968 18:01:16.392783 8, 0xFFFF, sum = 0
6969 18:01:16.395620 9, 0xFFFF, sum = 0
6970 18:01:16.395704 10, 0xFFFF, sum = 0
6971 18:01:16.398934 11, 0xFFFF, sum = 0
6972 18:01:16.399008 12, 0xFFFF, sum = 0
6973 18:01:16.402295 13, 0x0, sum = 1
6974 18:01:16.402373 14, 0x0, sum = 2
6975 18:01:16.405869 15, 0x0, sum = 3
6976 18:01:16.405948 16, 0x0, sum = 4
6977 18:01:16.409420 best_step = 14
6978 18:01:16.409491
6979 18:01:16.409552 ==
6980 18:01:16.412383 Dram Type= 6, Freq= 0, CH_1, rank 1
6981 18:01:16.415525 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6982 18:01:16.415603 ==
6983 18:01:16.419108 RX Vref Scan: 0
6984 18:01:16.419209
6985 18:01:16.419280 RX Vref 0 -> 0, step: 1
6986 18:01:16.419358
6987 18:01:16.422139 RX Delay -359 -> 252, step: 8
6988 18:01:16.430227 iDelay=217, Bit 0, Center -32 (-271 ~ 208) 480
6989 18:01:16.433557 iDelay=217, Bit 1, Center -44 (-287 ~ 200) 488
6990 18:01:16.437229 iDelay=217, Bit 2, Center -52 (-295 ~ 192) 488
6991 18:01:16.440410 iDelay=217, Bit 3, Center -44 (-287 ~ 200) 488
6992 18:01:16.446928 iDelay=217, Bit 4, Center -40 (-279 ~ 200) 480
6993 18:01:16.450597 iDelay=217, Bit 5, Center -24 (-263 ~ 216) 480
6994 18:01:16.454236 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6995 18:01:16.457135 iDelay=217, Bit 7, Center -44 (-287 ~ 200) 488
6996 18:01:16.463685 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
6997 18:01:16.467253 iDelay=217, Bit 9, Center -56 (-303 ~ 192) 496
6998 18:01:16.470207 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6999 18:01:16.473767 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
7000 18:01:16.480553 iDelay=217, Bit 12, Center -40 (-279 ~ 200) 480
7001 18:01:16.483711 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
7002 18:01:16.487330 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
7003 18:01:16.490332 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
7004 18:01:16.493975 ==
7005 18:01:16.497099 Dram Type= 6, Freq= 0, CH_1, rank 1
7006 18:01:16.500666 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7007 18:01:16.500748 ==
7008 18:01:16.500812 DQS Delay:
7009 18:01:16.504108 DQS0 = 52, DQS1 = 56
7010 18:01:16.504188 DQM Delay:
7011 18:01:16.507445 DQM0 = 13, DQM1 = 9
7012 18:01:16.507530 DQ Delay:
7013 18:01:16.510912 DQ0 =20, DQ1 =8, DQ2 =0, DQ3 =8
7014 18:01:16.513992 DQ4 =12, DQ5 =28, DQ6 =24, DQ7 =8
7015 18:01:16.517606 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
7016 18:01:16.520624 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
7017 18:01:16.520706
7018 18:01:16.520769
7019 18:01:16.527368 [DQSOSCAuto] RK1, (LSB)MR18= 0x6f84, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 395 ps
7020 18:01:16.531120 CH1 RK1: MR19=C0C, MR18=6F84
7021 18:01:16.537180 CH1_RK1: MR19=0xC0C, MR18=0x6F84, DQSOSC=393, MR23=63, INC=382, DEC=254
7022 18:01:16.540585 [RxdqsGatingPostProcess] freq 400
7023 18:01:16.544087 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7024 18:01:16.547360 best DQS0 dly(2T, 0.5T) = (0, 10)
7025 18:01:16.550521 best DQS1 dly(2T, 0.5T) = (0, 10)
7026 18:01:16.553954 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7027 18:01:16.557285 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7028 18:01:16.560606 best DQS0 dly(2T, 0.5T) = (0, 10)
7029 18:01:16.563994 best DQS1 dly(2T, 0.5T) = (0, 10)
7030 18:01:16.567304 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7031 18:01:16.570577 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7032 18:01:16.573924 Pre-setting of DQS Precalculation
7033 18:01:16.577658 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7034 18:01:16.583812 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7035 18:01:16.593814 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7036 18:01:16.593894
7037 18:01:16.593959
7038 18:01:16.594025 [Calibration Summary] 800 Mbps
7039 18:01:16.597321 CH 0, Rank 0
7040 18:01:16.600328 SW Impedance : PASS
7041 18:01:16.600405 DUTY Scan : NO K
7042 18:01:16.604016 ZQ Calibration : PASS
7043 18:01:16.604103 Jitter Meter : NO K
7044 18:01:16.607050 CBT Training : PASS
7045 18:01:16.610505 Write leveling : PASS
7046 18:01:16.610586 RX DQS gating : PASS
7047 18:01:16.614073 RX DQ/DQS(RDDQC) : PASS
7048 18:01:16.617474 TX DQ/DQS : PASS
7049 18:01:16.617568 RX DATLAT : PASS
7050 18:01:16.620399 RX DQ/DQS(Engine): PASS
7051 18:01:16.623970 TX OE : NO K
7052 18:01:16.624045 All Pass.
7053 18:01:16.624106
7054 18:01:16.624164 CH 0, Rank 1
7055 18:01:16.627505 SW Impedance : PASS
7056 18:01:16.630492 DUTY Scan : NO K
7057 18:01:16.630578 ZQ Calibration : PASS
7058 18:01:16.633590 Jitter Meter : NO K
7059 18:01:16.637263 CBT Training : PASS
7060 18:01:16.637344 Write leveling : NO K
7061 18:01:16.640266 RX DQS gating : PASS
7062 18:01:16.643842 RX DQ/DQS(RDDQC) : PASS
7063 18:01:16.643923 TX DQ/DQS : PASS
7064 18:01:16.646902 RX DATLAT : PASS
7065 18:01:16.646983 RX DQ/DQS(Engine): PASS
7066 18:01:16.650462 TX OE : NO K
7067 18:01:16.650545 All Pass.
7068 18:01:16.650609
7069 18:01:16.654032 CH 1, Rank 0
7070 18:01:16.654113 SW Impedance : PASS
7071 18:01:16.657172 DUTY Scan : NO K
7072 18:01:16.660373 ZQ Calibration : PASS
7073 18:01:16.660458 Jitter Meter : NO K
7074 18:01:16.663961 CBT Training : PASS
7075 18:01:16.666852 Write leveling : PASS
7076 18:01:16.666935 RX DQS gating : PASS
7077 18:01:16.670256 RX DQ/DQS(RDDQC) : PASS
7078 18:01:16.673894 TX DQ/DQS : PASS
7079 18:01:16.673975 RX DATLAT : PASS
7080 18:01:16.676784 RX DQ/DQS(Engine): PASS
7081 18:01:16.680724 TX OE : NO K
7082 18:01:16.680798 All Pass.
7083 18:01:16.680860
7084 18:01:16.680926 CH 1, Rank 1
7085 18:01:16.683504 SW Impedance : PASS
7086 18:01:16.686950 DUTY Scan : NO K
7087 18:01:16.687035 ZQ Calibration : PASS
7088 18:01:16.690365 Jitter Meter : NO K
7089 18:01:16.693679 CBT Training : PASS
7090 18:01:16.693759 Write leveling : NO K
7091 18:01:16.697166 RX DQS gating : PASS
7092 18:01:16.697249 RX DQ/DQS(RDDQC) : PASS
7093 18:01:16.700281 TX DQ/DQS : PASS
7094 18:01:16.703760 RX DATLAT : PASS
7095 18:01:16.703836 RX DQ/DQS(Engine): PASS
7096 18:01:16.706951 TX OE : NO K
7097 18:01:16.707026 All Pass.
7098 18:01:16.707090
7099 18:01:16.710530 DramC Write-DBI off
7100 18:01:16.713618 PER_BANK_REFRESH: Hybrid Mode
7101 18:01:16.713702 TX_TRACKING: ON
7102 18:01:16.723685 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7103 18:01:16.726965 [FAST_K] Save calibration result to emmc
7104 18:01:16.730399 dramc_set_vcore_voltage set vcore to 725000
7105 18:01:16.734096 Read voltage for 1600, 0
7106 18:01:16.734178 Vio18 = 0
7107 18:01:16.734242 Vcore = 725000
7108 18:01:16.737147 Vdram = 0
7109 18:01:16.737228 Vddq = 0
7110 18:01:16.737292 Vmddr = 0
7111 18:01:16.743941 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7112 18:01:16.746947 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7113 18:01:16.750646 MEM_TYPE=3, freq_sel=13
7114 18:01:16.753700 sv_algorithm_assistance_LP4_3733
7115 18:01:16.757359 ============ PULL DRAM RESETB DOWN ============
7116 18:01:16.760333 ========== PULL DRAM RESETB DOWN end =========
7117 18:01:16.766778 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7118 18:01:16.770082 ===================================
7119 18:01:16.773872 LPDDR4 DRAM CONFIGURATION
7120 18:01:16.777185 ===================================
7121 18:01:16.777268 EX_ROW_EN[0] = 0x0
7122 18:01:16.780235 EX_ROW_EN[1] = 0x0
7123 18:01:16.780317 LP4Y_EN = 0x0
7124 18:01:16.783859 WORK_FSP = 0x1
7125 18:01:16.783941 WL = 0x5
7126 18:01:16.786793 RL = 0x5
7127 18:01:16.786880 BL = 0x2
7128 18:01:16.790449 RPST = 0x0
7129 18:01:16.790529 RD_PRE = 0x0
7130 18:01:16.793974 WR_PRE = 0x1
7131 18:01:16.794049 WR_PST = 0x1
7132 18:01:16.796842 DBI_WR = 0x0
7133 18:01:16.796924 DBI_RD = 0x0
7134 18:01:16.800456 OTF = 0x1
7135 18:01:16.804169 ===================================
7136 18:01:16.807436 ===================================
7137 18:01:16.807518 ANA top config
7138 18:01:16.810382 ===================================
7139 18:01:16.813870 DLL_ASYNC_EN = 0
7140 18:01:16.816895 ALL_SLAVE_EN = 0
7141 18:01:16.820506 NEW_RANK_MODE = 1
7142 18:01:16.820588 DLL_IDLE_MODE = 1
7143 18:01:16.824076 LP45_APHY_COMB_EN = 1
7144 18:01:16.827014 TX_ODT_DIS = 0
7145 18:01:16.830589 NEW_8X_MODE = 1
7146 18:01:16.833992 ===================================
7147 18:01:16.837342 ===================================
7148 18:01:16.840379 data_rate = 3200
7149 18:01:16.840461 CKR = 1
7150 18:01:16.844107 DQ_P2S_RATIO = 8
7151 18:01:16.847260 ===================================
7152 18:01:16.850495 CA_P2S_RATIO = 8
7153 18:01:16.854261 DQ_CA_OPEN = 0
7154 18:01:16.857216 DQ_SEMI_OPEN = 0
7155 18:01:16.857298 CA_SEMI_OPEN = 0
7156 18:01:16.860267 CA_FULL_RATE = 0
7157 18:01:16.863901 DQ_CKDIV4_EN = 0
7158 18:01:16.867477 CA_CKDIV4_EN = 0
7159 18:01:16.870489 CA_PREDIV_EN = 0
7160 18:01:16.874092 PH8_DLY = 12
7161 18:01:16.874173 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7162 18:01:16.876943 DQ_AAMCK_DIV = 4
7163 18:01:16.880466 CA_AAMCK_DIV = 4
7164 18:01:16.883842 CA_ADMCK_DIV = 4
7165 18:01:16.887408 DQ_TRACK_CA_EN = 0
7166 18:01:16.890697 CA_PICK = 1600
7167 18:01:16.894221 CA_MCKIO = 1600
7168 18:01:16.894303 MCKIO_SEMI = 0
7169 18:01:16.897281 PLL_FREQ = 3068
7170 18:01:16.900854 DQ_UI_PI_RATIO = 32
7171 18:01:16.903886 CA_UI_PI_RATIO = 0
7172 18:01:16.907235 ===================================
7173 18:01:16.911105 ===================================
7174 18:01:16.913906 memory_type:LPDDR4
7175 18:01:16.913988 GP_NUM : 10
7176 18:01:16.917138 SRAM_EN : 1
7177 18:01:16.920804 MD32_EN : 0
7178 18:01:16.920885 ===================================
7179 18:01:16.924039 [ANA_INIT] >>>>>>>>>>>>>>
7180 18:01:16.927657 <<<<<< [CONFIGURE PHASE]: ANA_TX
7181 18:01:16.930692 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7182 18:01:16.934293 ===================================
7183 18:01:16.937230 data_rate = 3200,PCW = 0X7600
7184 18:01:16.940788 ===================================
7185 18:01:16.944075 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7186 18:01:16.950554 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7187 18:01:16.954264 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7188 18:01:16.960780 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7189 18:01:16.963961 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7190 18:01:16.967696 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7191 18:01:16.967806 [ANA_INIT] flow start
7192 18:01:16.970636 [ANA_INIT] PLL >>>>>>>>
7193 18:01:16.974221 [ANA_INIT] PLL <<<<<<<<
7194 18:01:16.974303 [ANA_INIT] MIDPI >>>>>>>>
7195 18:01:16.977238 [ANA_INIT] MIDPI <<<<<<<<
7196 18:01:16.980821 [ANA_INIT] DLL >>>>>>>>
7197 18:01:16.980930 [ANA_INIT] DLL <<<<<<<<
7198 18:01:16.984301 [ANA_INIT] flow end
7199 18:01:16.987359 ============ LP4 DIFF to SE enter ============
7200 18:01:16.990919 ============ LP4 DIFF to SE exit ============
7201 18:01:16.993954 [ANA_INIT] <<<<<<<<<<<<<
7202 18:01:16.997337 [Flow] Enable top DCM control >>>>>
7203 18:01:17.000997 [Flow] Enable top DCM control <<<<<
7204 18:01:17.004454 Enable DLL master slave shuffle
7205 18:01:17.011258 ==============================================================
7206 18:01:17.011341 Gating Mode config
7207 18:01:17.017886 ==============================================================
7208 18:01:17.017995 Config description:
7209 18:01:17.027359 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7210 18:01:17.034266 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7211 18:01:17.040839 SELPH_MODE 0: By rank 1: By Phase
7212 18:01:17.044290 ==============================================================
7213 18:01:17.047751 GAT_TRACK_EN = 1
7214 18:01:17.051372 RX_GATING_MODE = 2
7215 18:01:17.054014 RX_GATING_TRACK_MODE = 2
7216 18:01:17.057543 SELPH_MODE = 1
7217 18:01:17.060612 PICG_EARLY_EN = 1
7218 18:01:17.064371 VALID_LAT_VALUE = 1
7219 18:01:17.067536 ==============================================================
7220 18:01:17.071058 Enter into Gating configuration >>>>
7221 18:01:17.074253 Exit from Gating configuration <<<<
7222 18:01:17.077349 Enter into DVFS_PRE_config >>>>>
7223 18:01:17.090552 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7224 18:01:17.094260 Exit from DVFS_PRE_config <<<<<
7225 18:01:17.097403 Enter into PICG configuration >>>>
7226 18:01:17.097485 Exit from PICG configuration <<<<
7227 18:01:17.100610 [RX_INPUT] configuration >>>>>
7228 18:01:17.104342 [RX_INPUT] configuration <<<<<
7229 18:01:17.110698 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7230 18:01:17.113947 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7231 18:01:17.121113 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7232 18:01:17.127388 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7233 18:01:17.134105 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7234 18:01:17.140901 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7235 18:01:17.143864 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7236 18:01:17.147204 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7237 18:01:17.151007 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7238 18:01:17.157379 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7239 18:01:17.160765 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7240 18:01:17.164073 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7241 18:01:17.167372 ===================================
7242 18:01:17.171035 LPDDR4 DRAM CONFIGURATION
7243 18:01:17.174132 ===================================
7244 18:01:17.177929 EX_ROW_EN[0] = 0x0
7245 18:01:17.178013 EX_ROW_EN[1] = 0x0
7246 18:01:17.180929 LP4Y_EN = 0x0
7247 18:01:17.181033 WORK_FSP = 0x1
7248 18:01:17.183936 WL = 0x5
7249 18:01:17.184051 RL = 0x5
7250 18:01:17.187534 BL = 0x2
7251 18:01:17.187645 RPST = 0x0
7252 18:01:17.191225 RD_PRE = 0x0
7253 18:01:17.191309 WR_PRE = 0x1
7254 18:01:17.194307 WR_PST = 0x1
7255 18:01:17.194392 DBI_WR = 0x0
7256 18:01:17.197407 DBI_RD = 0x0
7257 18:01:17.197491 OTF = 0x1
7258 18:01:17.201187 ===================================
7259 18:01:17.204341 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7260 18:01:17.210929 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7261 18:01:17.214528 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7262 18:01:17.217624 ===================================
7263 18:01:17.220648 LPDDR4 DRAM CONFIGURATION
7264 18:01:17.224017 ===================================
7265 18:01:17.224105 EX_ROW_EN[0] = 0x10
7266 18:01:17.227632 EX_ROW_EN[1] = 0x0
7267 18:01:17.227720 LP4Y_EN = 0x0
7268 18:01:17.231162 WORK_FSP = 0x1
7269 18:01:17.231248 WL = 0x5
7270 18:01:17.234066 RL = 0x5
7271 18:01:17.234152 BL = 0x2
7272 18:01:17.238043 RPST = 0x0
7273 18:01:17.241117 RD_PRE = 0x0
7274 18:01:17.241230 WR_PRE = 0x1
7275 18:01:17.244273 WR_PST = 0x1
7276 18:01:17.244356 DBI_WR = 0x0
7277 18:01:17.247998 DBI_RD = 0x0
7278 18:01:17.248084 OTF = 0x1
7279 18:01:17.251107 ===================================
7280 18:01:17.257701 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7281 18:01:17.257789 ==
7282 18:01:17.261130 Dram Type= 6, Freq= 0, CH_0, rank 0
7283 18:01:17.264368 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7284 18:01:17.264480 ==
7285 18:01:17.268034 [Duty_Offset_Calibration]
7286 18:01:17.268119 B0:2 B1:-1 CA:1
7287 18:01:17.271117
7288 18:01:17.271201 [DutyScan_Calibration_Flow] k_type=0
7289 18:01:17.281432
7290 18:01:17.281521 ==CLK 0==
7291 18:01:17.284853 Final CLK duty delay cell = -4
7292 18:01:17.288684 [-4] MAX Duty = 5031%(X100), DQS PI = 22
7293 18:01:17.291800 [-4] MIN Duty = 4844%(X100), DQS PI = 32
7294 18:01:17.294955 [-4] AVG Duty = 4937%(X100)
7295 18:01:17.295041
7296 18:01:17.298653 CH0 CLK Duty spec in!! Max-Min= 187%
7297 18:01:17.301909 [DutyScan_Calibration_Flow] ====Done====
7298 18:01:17.301997
7299 18:01:17.305077 [DutyScan_Calibration_Flow] k_type=1
7300 18:01:17.321182
7301 18:01:17.321292 ==DQS 0 ==
7302 18:01:17.324322 Final DQS duty delay cell = 0
7303 18:01:17.327985 [0] MAX Duty = 5125%(X100), DQS PI = 20
7304 18:01:17.331127 [0] MIN Duty = 5000%(X100), DQS PI = 14
7305 18:01:17.331246 [0] AVG Duty = 5062%(X100)
7306 18:01:17.334492
7307 18:01:17.334604 ==DQS 1 ==
7308 18:01:17.338002 Final DQS duty delay cell = -4
7309 18:01:17.341301 [-4] MAX Duty = 5093%(X100), DQS PI = 0
7310 18:01:17.344677 [-4] MIN Duty = 5000%(X100), DQS PI = 40
7311 18:01:17.347795 [-4] AVG Duty = 5046%(X100)
7312 18:01:17.347879
7313 18:01:17.351462 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7314 18:01:17.351548
7315 18:01:17.354787 CH0 DQS 1 Duty spec in!! Max-Min= 93%
7316 18:01:17.357980 [DutyScan_Calibration_Flow] ====Done====
7317 18:01:17.358064
7318 18:01:17.360960 [DutyScan_Calibration_Flow] k_type=3
7319 18:01:17.378739
7320 18:01:17.378829 ==DQM 0 ==
7321 18:01:17.382353 Final DQM duty delay cell = 0
7322 18:01:17.385199 [0] MAX Duty = 5000%(X100), DQS PI = 20
7323 18:01:17.388702 [0] MIN Duty = 4875%(X100), DQS PI = 4
7324 18:01:17.388787 [0] AVG Duty = 4937%(X100)
7325 18:01:17.391920
7326 18:01:17.392003 ==DQM 1 ==
7327 18:01:17.395342 Final DQM duty delay cell = 0
7328 18:01:17.398579 [0] MAX Duty = 5187%(X100), DQS PI = 58
7329 18:01:17.401998 [0] MIN Duty = 4969%(X100), DQS PI = 18
7330 18:01:17.405083 [0] AVG Duty = 5078%(X100)
7331 18:01:17.405167
7332 18:01:17.408684 CH0 DQM 0 Duty spec in!! Max-Min= 125%
7333 18:01:17.408766
7334 18:01:17.411815 CH0 DQM 1 Duty spec in!! Max-Min= 218%
7335 18:01:17.415356 [DutyScan_Calibration_Flow] ====Done====
7336 18:01:17.415438
7337 18:01:17.418458 [DutyScan_Calibration_Flow] k_type=2
7338 18:01:17.434708
7339 18:01:17.434793 ==DQ 0 ==
7340 18:01:17.438349 Final DQ duty delay cell = -4
7341 18:01:17.441816 [-4] MAX Duty = 5031%(X100), DQS PI = 56
7342 18:01:17.445199 [-4] MIN Duty = 4844%(X100), DQS PI = 12
7343 18:01:17.448267 [-4] AVG Duty = 4937%(X100)
7344 18:01:17.448373
7345 18:01:17.448469 ==DQ 1 ==
7346 18:01:17.451825 Final DQ duty delay cell = 0
7347 18:01:17.454747 [0] MAX Duty = 5031%(X100), DQS PI = 30
7348 18:01:17.458552 [0] MIN Duty = 4907%(X100), DQS PI = 18
7349 18:01:17.458646 [0] AVG Duty = 4969%(X100)
7350 18:01:17.461733
7351 18:01:17.464832 CH0 DQ 0 Duty spec in!! Max-Min= 187%
7352 18:01:17.464915
7353 18:01:17.468454 CH0 DQ 1 Duty spec in!! Max-Min= 124%
7354 18:01:17.471960 [DutyScan_Calibration_Flow] ====Done====
7355 18:01:17.472043 ==
7356 18:01:17.474860 Dram Type= 6, Freq= 0, CH_1, rank 0
7357 18:01:17.478539 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7358 18:01:17.478620 ==
7359 18:01:17.481600 [Duty_Offset_Calibration]
7360 18:01:17.481740 B0:1 B1:1 CA:2
7361 18:01:17.481872
7362 18:01:17.485228 [DutyScan_Calibration_Flow] k_type=0
7363 18:01:17.495815
7364 18:01:17.495901 ==CLK 0==
7365 18:01:17.498783 Final CLK duty delay cell = 0
7366 18:01:17.502191 [0] MAX Duty = 5187%(X100), DQS PI = 24
7367 18:01:17.505327 [0] MIN Duty = 4938%(X100), DQS PI = 52
7368 18:01:17.505408 [0] AVG Duty = 5062%(X100)
7369 18:01:17.508726
7370 18:01:17.508808 CH1 CLK Duty spec in!! Max-Min= 249%
7371 18:01:17.515912 [DutyScan_Calibration_Flow] ====Done====
7372 18:01:17.515994
7373 18:01:17.519051 [DutyScan_Calibration_Flow] k_type=1
7374 18:01:17.535229
7375 18:01:17.535315 ==DQS 0 ==
7376 18:01:17.538284 Final DQS duty delay cell = 0
7377 18:01:17.541969 [0] MAX Duty = 5031%(X100), DQS PI = 20
7378 18:01:17.544929 [0] MIN Duty = 4813%(X100), DQS PI = 52
7379 18:01:17.548579 [0] AVG Duty = 4922%(X100)
7380 18:01:17.548660
7381 18:01:17.548725 ==DQS 1 ==
7382 18:01:17.552035 Final DQS duty delay cell = 0
7383 18:01:17.555065 [0] MAX Duty = 5031%(X100), DQS PI = 34
7384 18:01:17.558510 [0] MIN Duty = 4938%(X100), DQS PI = 0
7385 18:01:17.558592 [0] AVG Duty = 4984%(X100)
7386 18:01:17.562139
7387 18:01:17.565244 CH1 DQS 0 Duty spec in!! Max-Min= 218%
7388 18:01:17.565362
7389 18:01:17.568311 CH1 DQS 1 Duty spec in!! Max-Min= 93%
7390 18:01:17.572187 [DutyScan_Calibration_Flow] ====Done====
7391 18:01:17.572313
7392 18:01:17.575133 [DutyScan_Calibration_Flow] k_type=3
7393 18:01:17.592097
7394 18:01:17.592206 ==DQM 0 ==
7395 18:01:17.595228 Final DQM duty delay cell = 0
7396 18:01:17.598454 [0] MAX Duty = 5156%(X100), DQS PI = 20
7397 18:01:17.602180 [0] MIN Duty = 4844%(X100), DQS PI = 50
7398 18:01:17.605193 [0] AVG Duty = 5000%(X100)
7399 18:01:17.605275
7400 18:01:17.605369 ==DQM 1 ==
7401 18:01:17.608401 Final DQM duty delay cell = 0
7402 18:01:17.611938 [0] MAX Duty = 5156%(X100), DQS PI = 60
7403 18:01:17.615372 [0] MIN Duty = 4907%(X100), DQS PI = 20
7404 18:01:17.618656 [0] AVG Duty = 5031%(X100)
7405 18:01:17.618739
7406 18:01:17.622240 CH1 DQM 0 Duty spec in!! Max-Min= 312%
7407 18:01:17.622322
7408 18:01:17.625316 CH1 DQM 1 Duty spec in!! Max-Min= 249%
7409 18:01:17.628391 [DutyScan_Calibration_Flow] ====Done====
7410 18:01:17.628472
7411 18:01:17.632094 [DutyScan_Calibration_Flow] k_type=2
7412 18:01:17.649102
7413 18:01:17.649189 ==DQ 0 ==
7414 18:01:17.652138 Final DQ duty delay cell = 0
7415 18:01:17.655527 [0] MAX Duty = 5156%(X100), DQS PI = 20
7416 18:01:17.658763 [0] MIN Duty = 4907%(X100), DQS PI = 52
7417 18:01:17.658846 [0] AVG Duty = 5031%(X100)
7418 18:01:17.662262
7419 18:01:17.662344 ==DQ 1 ==
7420 18:01:17.665814 Final DQ duty delay cell = 0
7421 18:01:17.668778 [0] MAX Duty = 5093%(X100), DQS PI = 6
7422 18:01:17.672288 [0] MIN Duty = 5031%(X100), DQS PI = 0
7423 18:01:17.672372 [0] AVG Duty = 5062%(X100)
7424 18:01:17.672438
7425 18:01:17.675364 CH1 DQ 0 Duty spec in!! Max-Min= 249%
7426 18:01:17.675451
7427 18:01:17.679111 CH1 DQ 1 Duty spec in!! Max-Min= 62%
7428 18:01:17.685399 [DutyScan_Calibration_Flow] ====Done====
7429 18:01:17.688828 nWR fixed to 30
7430 18:01:17.688914 [ModeRegInit_LP4] CH0 RK0
7431 18:01:17.691817 [ModeRegInit_LP4] CH0 RK1
7432 18:01:17.695391 [ModeRegInit_LP4] CH1 RK0
7433 18:01:17.695474 [ModeRegInit_LP4] CH1 RK1
7434 18:01:17.699198 match AC timing 5
7435 18:01:17.701880 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7436 18:01:17.705580 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7437 18:01:17.712306 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7438 18:01:17.715312 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7439 18:01:17.722143 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7440 18:01:17.722229 [MiockJmeterHQA]
7441 18:01:17.722295
7442 18:01:17.725589 [DramcMiockJmeter] u1RxGatingPI = 0
7443 18:01:17.729093 0 : 4363, 4137
7444 18:01:17.729179 4 : 4252, 4027
7445 18:01:17.729259 8 : 4363, 4138
7446 18:01:17.731930 12 : 4363, 4138
7447 18:01:17.732016 16 : 4362, 4137
7448 18:01:17.735343 20 : 4252, 4027
7449 18:01:17.735468 24 : 4253, 4027
7450 18:01:17.739115 28 : 4253, 4026
7451 18:01:17.739211 32 : 4252, 4027
7452 18:01:17.739297 36 : 4255, 4029
7453 18:01:17.742265 40 : 4363, 4137
7454 18:01:17.742354 44 : 4252, 4027
7455 18:01:17.745841 48 : 4252, 4027
7456 18:01:17.745930 52 : 4253, 4027
7457 18:01:17.749059 56 : 4255, 4029
7458 18:01:17.749148 60 : 4250, 4027
7459 18:01:17.749237 64 : 4360, 4138
7460 18:01:17.752299 68 : 4360, 4137
7461 18:01:17.752414 72 : 4250, 4027
7462 18:01:17.755506 76 : 4250, 4027
7463 18:01:17.755591 80 : 4250, 4026
7464 18:01:17.758560 84 : 4250, 4027
7465 18:01:17.758673 88 : 4252, 4029
7466 18:01:17.762413 92 : 4361, 4137
7467 18:01:17.762499 96 : 4250, 3294
7468 18:01:17.762566 100 : 4250, 0
7469 18:01:17.765357 104 : 4253, 0
7470 18:01:17.765443 108 : 4250, 0
7471 18:01:17.768935 112 : 4250, 0
7472 18:01:17.769039 116 : 4252, 0
7473 18:01:17.769107 120 : 4250, 0
7474 18:01:17.772078 124 : 4250, 0
7475 18:01:17.772196 128 : 4252, 0
7476 18:01:17.772267 132 : 4360, 0
7477 18:01:17.775615 136 : 4361, 0
7478 18:01:17.775730 140 : 4363, 0
7479 18:01:17.778495 144 : 4250, 0
7480 18:01:17.778607 148 : 4250, 0
7481 18:01:17.778706 152 : 4250, 0
7482 18:01:17.782120 156 : 4250, 0
7483 18:01:17.782210 160 : 4250, 0
7484 18:01:17.785825 164 : 4250, 0
7485 18:01:17.785915 168 : 4253, 0
7486 18:01:17.786005 172 : 4250, 0
7487 18:01:17.788868 176 : 4250, 0
7488 18:01:17.788988 180 : 4250, 0
7489 18:01:17.792265 184 : 4360, 0
7490 18:01:17.792355 188 : 4361, 0
7491 18:01:17.792458 192 : 4250, 0
7492 18:01:17.795504 196 : 4250, 0
7493 18:01:17.795590 200 : 4250, 0
7494 18:01:17.795658 204 : 4250, 0
7495 18:01:17.799170 208 : 4252, 0
7496 18:01:17.799256 212 : 4250, 99
7497 18:01:17.802235 216 : 4362, 3789
7498 18:01:17.802346 220 : 4250, 4026
7499 18:01:17.805457 224 : 4250, 4027
7500 18:01:17.805570 228 : 4250, 4026
7501 18:01:17.808765 232 : 4253, 4029
7502 18:01:17.808875 236 : 4250, 4026
7503 18:01:17.811846 240 : 4250, 4027
7504 18:01:17.811961 244 : 4360, 4138
7505 18:01:17.812033 248 : 4250, 4027
7506 18:01:17.815567 252 : 4250, 4026
7507 18:01:17.815653 256 : 4361, 4137
7508 18:01:17.818656 260 : 4250, 4027
7509 18:01:17.818768 264 : 4250, 4027
7510 18:01:17.822339 268 : 4362, 4140
7511 18:01:17.822464 272 : 4250, 4026
7512 18:01:17.825409 276 : 4250, 4027
7513 18:01:17.825516 280 : 4250, 4027
7514 18:01:17.828951 284 : 4252, 4029
7515 18:01:17.829050 288 : 4250, 4026
7516 18:01:17.831775 292 : 4250, 4027
7517 18:01:17.831885 296 : 4360, 4138
7518 18:01:17.835454 300 : 4249, 4027
7519 18:01:17.835560 304 : 4250, 4026
7520 18:01:17.835661 308 : 4361, 4137
7521 18:01:17.838567 312 : 4250, 4027
7522 18:01:17.838653 316 : 4250, 4027
7523 18:01:17.842039 320 : 4362, 4140
7524 18:01:17.842148 324 : 4250, 4026
7525 18:01:17.845527 328 : 4250, 4027
7526 18:01:17.845637 332 : 4250, 2739
7527 18:01:17.848551 336 : 4252, 28
7528 18:01:17.848652
7529 18:01:17.848747 MIOCK jitter meter ch=0
7530 18:01:17.848836
7531 18:01:17.852443 1T = (336-100) = 236 dly cells
7532 18:01:17.858825 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7533 18:01:17.858937 ==
7534 18:01:17.862015 Dram Type= 6, Freq= 0, CH_0, rank 0
7535 18:01:17.865697 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7536 18:01:17.865808 ==
7537 18:01:17.872035 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7538 18:01:17.875561 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7539 18:01:17.882222 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7540 18:01:17.885157 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7541 18:01:17.895123 [CA 0] Center 44 (14~75) winsize 62
7542 18:01:17.898702 [CA 1] Center 44 (14~75) winsize 62
7543 18:01:17.902127 [CA 2] Center 40 (11~69) winsize 59
7544 18:01:17.904945 [CA 3] Center 39 (10~69) winsize 60
7545 18:01:17.908359 [CA 4] Center 38 (8~68) winsize 61
7546 18:01:17.911540 [CA 5] Center 37 (7~67) winsize 61
7547 18:01:17.911644
7548 18:01:17.915262 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7549 18:01:17.915341
7550 18:01:17.918361 [CATrainingPosCal] consider 1 rank data
7551 18:01:17.922098 u2DelayCellTimex100 = 275/100 ps
7552 18:01:17.928277 CA0 delay=44 (14~75),Diff = 7 PI (24 cell)
7553 18:01:17.932063 CA1 delay=44 (14~75),Diff = 7 PI (24 cell)
7554 18:01:17.934961 CA2 delay=40 (11~69),Diff = 3 PI (10 cell)
7555 18:01:17.938406 CA3 delay=39 (10~69),Diff = 2 PI (7 cell)
7556 18:01:17.942142 CA4 delay=38 (8~68),Diff = 1 PI (3 cell)
7557 18:01:17.945211 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7558 18:01:17.945317
7559 18:01:17.948233 CA PerBit enable=1, Macro0, CA PI delay=37
7560 18:01:17.948338
7561 18:01:17.951820 [CBTSetCACLKResult] CA Dly = 37
7562 18:01:17.955134 CS Dly: 10 (0~41)
7563 18:01:17.958113 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7564 18:01:17.961858 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7565 18:01:17.961964 ==
7566 18:01:17.965344 Dram Type= 6, Freq= 0, CH_0, rank 1
7567 18:01:17.971928 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7568 18:01:17.972035 ==
7569 18:01:17.975024 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7570 18:01:17.978644 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7571 18:01:17.985162 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7572 18:01:17.991699 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7573 18:01:17.999250 [CA 0] Center 44 (14~75) winsize 62
7574 18:01:18.002225 [CA 1] Center 43 (13~74) winsize 62
7575 18:01:18.006100 [CA 2] Center 39 (10~69) winsize 60
7576 18:01:18.009066 [CA 3] Center 38 (9~68) winsize 60
7577 18:01:18.012406 [CA 4] Center 37 (7~67) winsize 61
7578 18:01:18.015786 [CA 5] Center 37 (7~67) winsize 61
7579 18:01:18.015866
7580 18:01:18.019183 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7581 18:01:18.019289
7582 18:01:18.022889 [CATrainingPosCal] consider 2 rank data
7583 18:01:18.025762 u2DelayCellTimex100 = 275/100 ps
7584 18:01:18.029438 CA0 delay=44 (14~75),Diff = 7 PI (24 cell)
7585 18:01:18.035736 CA1 delay=44 (14~74),Diff = 7 PI (24 cell)
7586 18:01:18.039411 CA2 delay=40 (11~69),Diff = 3 PI (10 cell)
7587 18:01:18.042287 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7588 18:01:18.045836 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7589 18:01:18.049362 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7590 18:01:18.049468
7591 18:01:18.052633 CA PerBit enable=1, Macro0, CA PI delay=37
7592 18:01:18.052742
7593 18:01:18.055693 [CBTSetCACLKResult] CA Dly = 37
7594 18:01:18.059299 CS Dly: 11 (0~44)
7595 18:01:18.062819 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7596 18:01:18.065868 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7597 18:01:18.065977
7598 18:01:18.068906 ----->DramcWriteLeveling(PI) begin...
7599 18:01:18.069019 ==
7600 18:01:18.072720 Dram Type= 6, Freq= 0, CH_0, rank 0
7601 18:01:18.075910 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7602 18:01:18.079464 ==
7603 18:01:18.079573 Write leveling (Byte 0): 31 => 31
7604 18:01:18.082640 Write leveling (Byte 1): 28 => 28
7605 18:01:18.085715 DramcWriteLeveling(PI) end<-----
7606 18:01:18.085822
7607 18:01:18.085921 ==
7608 18:01:18.089461 Dram Type= 6, Freq= 0, CH_0, rank 0
7609 18:01:18.096205 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7610 18:01:18.096316 ==
7611 18:01:18.099203 [Gating] SW mode calibration
7612 18:01:18.105450 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7613 18:01:18.109334 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7614 18:01:18.115952 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7615 18:01:18.119011 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7616 18:01:18.122308 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7617 18:01:18.128788 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7618 18:01:18.132431 1 4 16 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
7619 18:01:18.135529 1 4 20 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
7620 18:01:18.142492 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7621 18:01:18.145386 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7622 18:01:18.148876 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7623 18:01:18.152523 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7624 18:01:18.159204 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7625 18:01:18.162227 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7626 18:01:18.165283 1 5 16 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
7627 18:01:18.171917 1 5 20 | B1->B0 | 3434 2424 | 1 0 | (1 0) (1 0)
7628 18:01:18.175488 1 5 24 | B1->B0 | 2e2e 2323 | 1 0 | (1 0) (0 0)
7629 18:01:18.178824 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7630 18:01:18.185722 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7631 18:01:18.188839 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7632 18:01:18.191979 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7633 18:01:18.198500 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7634 18:01:18.202223 1 6 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (0 0)
7635 18:01:18.205734 1 6 20 | B1->B0 | 2323 4242 | 0 1 | (0 0) (0 0)
7636 18:01:18.211897 1 6 24 | B1->B0 | 3939 4646 | 1 0 | (0 0) (0 0)
7637 18:01:18.215552 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7638 18:01:18.218700 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7639 18:01:18.225509 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7640 18:01:18.228627 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7641 18:01:18.231983 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7642 18:01:18.238728 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7643 18:01:18.242095 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7644 18:01:18.245114 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7645 18:01:18.251962 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7646 18:01:18.255638 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7647 18:01:18.258531 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7648 18:01:18.261822 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7649 18:01:18.269005 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7650 18:01:18.272013 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7651 18:01:18.275471 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7652 18:01:18.282373 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7653 18:01:18.285418 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7654 18:01:18.288547 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7655 18:01:18.294976 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7656 18:01:18.298658 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7657 18:01:18.301930 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7658 18:01:18.308810 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7659 18:01:18.311701 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7660 18:01:18.315391 Total UI for P1: 0, mck2ui 16
7661 18:01:18.318590 best dqsien dly found for B0: ( 1, 9, 14)
7662 18:01:18.322296 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7663 18:01:18.325437 Total UI for P1: 0, mck2ui 16
7664 18:01:18.328512 best dqsien dly found for B1: ( 1, 9, 20)
7665 18:01:18.332196 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
7666 18:01:18.335455 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7667 18:01:18.335563
7668 18:01:18.342040 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
7669 18:01:18.345322 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7670 18:01:18.345437 [Gating] SW calibration Done
7671 18:01:18.348687 ==
7672 18:01:18.352217 Dram Type= 6, Freq= 0, CH_0, rank 0
7673 18:01:18.355451 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7674 18:01:18.355534 ==
7675 18:01:18.355601 RX Vref Scan: 0
7676 18:01:18.355663
7677 18:01:18.359140 RX Vref 0 -> 0, step: 1
7678 18:01:18.359214
7679 18:01:18.362196 RX Delay 0 -> 252, step: 8
7680 18:01:18.365280 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
7681 18:01:18.368604 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
7682 18:01:18.371963 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7683 18:01:18.378916 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7684 18:01:18.381900 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7685 18:01:18.385653 iDelay=200, Bit 5, Center 115 (56 ~ 175) 120
7686 18:01:18.388824 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
7687 18:01:18.392446 iDelay=200, Bit 7, Center 139 (88 ~ 191) 104
7688 18:01:18.395550 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7689 18:01:18.402337 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7690 18:01:18.405396 iDelay=200, Bit 10, Center 119 (64 ~ 175) 112
7691 18:01:18.408682 iDelay=200, Bit 11, Center 115 (64 ~ 167) 104
7692 18:01:18.412196 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7693 18:01:18.418858 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
7694 18:01:18.421897 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7695 18:01:18.425644 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7696 18:01:18.425751 ==
7697 18:01:18.429216 Dram Type= 6, Freq= 0, CH_0, rank 0
7698 18:01:18.432232 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7699 18:01:18.432342 ==
7700 18:01:18.435265 DQS Delay:
7701 18:01:18.435380 DQS0 = 0, DQS1 = 0
7702 18:01:18.435476 DQM Delay:
7703 18:01:18.439094 DQM0 = 131, DQM1 = 123
7704 18:01:18.439209 DQ Delay:
7705 18:01:18.442347 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
7706 18:01:18.445501 DQ4 =135, DQ5 =115, DQ6 =143, DQ7 =139
7707 18:01:18.452261 DQ8 =111, DQ9 =111, DQ10 =119, DQ11 =115
7708 18:01:18.455320 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
7709 18:01:18.455425
7710 18:01:18.455522
7711 18:01:18.455612 ==
7712 18:01:18.459002 Dram Type= 6, Freq= 0, CH_0, rank 0
7713 18:01:18.462054 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7714 18:01:18.462157 ==
7715 18:01:18.462250
7716 18:01:18.462341
7717 18:01:18.465649 TX Vref Scan disable
7718 18:01:18.465749 == TX Byte 0 ==
7719 18:01:18.472341 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7720 18:01:18.475930 Update DQM dly =988 (3 ,6, 28) DQM OEN =(3 ,3)
7721 18:01:18.476006 == TX Byte 1 ==
7722 18:01:18.482731 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7723 18:01:18.485918 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7724 18:01:18.486030 ==
7725 18:01:18.489196 Dram Type= 6, Freq= 0, CH_0, rank 0
7726 18:01:18.492642 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7727 18:01:18.492749 ==
7728 18:01:18.507293
7729 18:01:18.511047 TX Vref early break, caculate TX vref
7730 18:01:18.514085 TX Vref=16, minBit 0, minWin=21, winSum=352
7731 18:01:18.517199 TX Vref=18, minBit 7, minWin=21, winSum=370
7732 18:01:18.520648 TX Vref=20, minBit 1, minWin=22, winSum=377
7733 18:01:18.524394 TX Vref=22, minBit 7, minWin=22, winSum=394
7734 18:01:18.527278 TX Vref=24, minBit 2, minWin=23, winSum=400
7735 18:01:18.534594 TX Vref=26, minBit 7, minWin=23, winSum=409
7736 18:01:18.537705 TX Vref=28, minBit 1, minWin=24, winSum=417
7737 18:01:18.540817 TX Vref=30, minBit 1, minWin=25, winSum=418
7738 18:01:18.544426 TX Vref=32, minBit 4, minWin=23, winSum=411
7739 18:01:18.547797 TX Vref=34, minBit 4, minWin=23, winSum=402
7740 18:01:18.550690 TX Vref=36, minBit 0, minWin=23, winSum=389
7741 18:01:18.557550 [TxChooseVref] Worse bit 1, Min win 25, Win sum 418, Final Vref 30
7742 18:01:18.557660
7743 18:01:18.560986 Final TX Range 0 Vref 30
7744 18:01:18.561067
7745 18:01:18.561132 ==
7746 18:01:18.564511 Dram Type= 6, Freq= 0, CH_0, rank 0
7747 18:01:18.567637 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7748 18:01:18.567740 ==
7749 18:01:18.567835
7750 18:01:18.567927
7751 18:01:18.570787 TX Vref Scan disable
7752 18:01:18.577648 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7753 18:01:18.577727 == TX Byte 0 ==
7754 18:01:18.580906 u2DelayCellOfst[0]=14 cells (4 PI)
7755 18:01:18.584620 u2DelayCellOfst[1]=17 cells (5 PI)
7756 18:01:18.587606 u2DelayCellOfst[2]=10 cells (3 PI)
7757 18:01:18.591091 u2DelayCellOfst[3]=14 cells (4 PI)
7758 18:01:18.594535 u2DelayCellOfst[4]=10 cells (3 PI)
7759 18:01:18.597433 u2DelayCellOfst[5]=0 cells (0 PI)
7760 18:01:18.600832 u2DelayCellOfst[6]=17 cells (5 PI)
7761 18:01:18.604467 u2DelayCellOfst[7]=21 cells (6 PI)
7762 18:01:18.607409 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
7763 18:01:18.610941 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
7764 18:01:18.614089 == TX Byte 1 ==
7765 18:01:18.614194 u2DelayCellOfst[8]=0 cells (0 PI)
7766 18:01:18.617617 u2DelayCellOfst[9]=3 cells (1 PI)
7767 18:01:18.621329 u2DelayCellOfst[10]=10 cells (3 PI)
7768 18:01:18.624331 u2DelayCellOfst[11]=0 cells (0 PI)
7769 18:01:18.627340 u2DelayCellOfst[12]=14 cells (4 PI)
7770 18:01:18.630939 u2DelayCellOfst[13]=14 cells (4 PI)
7771 18:01:18.634439 u2DelayCellOfst[14]=17 cells (5 PI)
7772 18:01:18.637616 u2DelayCellOfst[15]=10 cells (3 PI)
7773 18:01:18.640734 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7774 18:01:18.648042 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7775 18:01:18.648149 DramC Write-DBI on
7776 18:01:18.648245 ==
7777 18:01:18.651048 Dram Type= 6, Freq= 0, CH_0, rank 0
7778 18:01:18.654853 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7779 18:01:18.654960 ==
7780 18:01:18.658041
7781 18:01:18.658139
7782 18:01:18.658232 TX Vref Scan disable
7783 18:01:18.661543 == TX Byte 0 ==
7784 18:01:18.664389 Update DQM dly =732 (2 ,6, 28) DQM OEN =(3 ,3)
7785 18:01:18.667655 == TX Byte 1 ==
7786 18:01:18.671339 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
7787 18:01:18.671421 DramC Write-DBI off
7788 18:01:18.671486
7789 18:01:18.674259 [DATLAT]
7790 18:01:18.674370 Freq=1600, CH0 RK0
7791 18:01:18.674475
7792 18:01:18.678071 DATLAT Default: 0xf
7793 18:01:18.678174 0, 0xFFFF, sum = 0
7794 18:01:18.681004 1, 0xFFFF, sum = 0
7795 18:01:18.681082 2, 0xFFFF, sum = 0
7796 18:01:18.684680 3, 0xFFFF, sum = 0
7797 18:01:18.684805 4, 0xFFFF, sum = 0
7798 18:01:18.687796 5, 0xFFFF, sum = 0
7799 18:01:18.690974 6, 0xFFFF, sum = 0
7800 18:01:18.691105 7, 0xFFFF, sum = 0
7801 18:01:18.694506 8, 0xFFFF, sum = 0
7802 18:01:18.694592 9, 0xFFFF, sum = 0
7803 18:01:18.698045 10, 0xFFFF, sum = 0
7804 18:01:18.698130 11, 0xFFFF, sum = 0
7805 18:01:18.701003 12, 0xFFFF, sum = 0
7806 18:01:18.701088 13, 0xFFFF, sum = 0
7807 18:01:18.704631 14, 0x0, sum = 1
7808 18:01:18.704716 15, 0x0, sum = 2
7809 18:01:18.707964 16, 0x0, sum = 3
7810 18:01:18.708049 17, 0x0, sum = 4
7811 18:01:18.711216 best_step = 15
7812 18:01:18.711311
7813 18:01:18.711377 ==
7814 18:01:18.714181 Dram Type= 6, Freq= 0, CH_0, rank 0
7815 18:01:18.717517 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7816 18:01:18.717628 ==
7817 18:01:18.717727 RX Vref Scan: 1
7818 18:01:18.717822
7819 18:01:18.720875 Set Vref Range= 24 -> 127
7820 18:01:18.720989
7821 18:01:18.724505 RX Vref 24 -> 127, step: 1
7822 18:01:18.724584
7823 18:01:18.727471 RX Delay 11 -> 252, step: 4
7824 18:01:18.727574
7825 18:01:18.731085 Set Vref, RX VrefLevel [Byte0]: 24
7826 18:01:18.734621 [Byte1]: 24
7827 18:01:18.734726
7828 18:01:18.737619 Set Vref, RX VrefLevel [Byte0]: 25
7829 18:01:18.740954 [Byte1]: 25
7830 18:01:18.741066
7831 18:01:18.744192 Set Vref, RX VrefLevel [Byte0]: 26
7832 18:01:18.747620 [Byte1]: 26
7833 18:01:18.751178
7834 18:01:18.751281 Set Vref, RX VrefLevel [Byte0]: 27
7835 18:01:18.754695 [Byte1]: 27
7836 18:01:18.758995
7837 18:01:18.759101 Set Vref, RX VrefLevel [Byte0]: 28
7838 18:01:18.762575 [Byte1]: 28
7839 18:01:18.766593
7840 18:01:18.766697 Set Vref, RX VrefLevel [Byte0]: 29
7841 18:01:18.770255 [Byte1]: 29
7842 18:01:18.774359
7843 18:01:18.774452 Set Vref, RX VrefLevel [Byte0]: 30
7844 18:01:18.777865 [Byte1]: 30
7845 18:01:18.781699
7846 18:01:18.781806 Set Vref, RX VrefLevel [Byte0]: 31
7847 18:01:18.785295 [Byte1]: 31
7848 18:01:18.789435
7849 18:01:18.789541 Set Vref, RX VrefLevel [Byte0]: 32
7850 18:01:18.793172 [Byte1]: 32
7851 18:01:18.797373
7852 18:01:18.797479 Set Vref, RX VrefLevel [Byte0]: 33
7853 18:01:18.800452 [Byte1]: 33
7854 18:01:18.804791
7855 18:01:18.804904 Set Vref, RX VrefLevel [Byte0]: 34
7856 18:01:18.807794 [Byte1]: 34
7857 18:01:18.812110
7858 18:01:18.812221 Set Vref, RX VrefLevel [Byte0]: 35
7859 18:01:18.815470 [Byte1]: 35
7860 18:01:18.819846
7861 18:01:18.819929 Set Vref, RX VrefLevel [Byte0]: 36
7862 18:01:18.823419 [Byte1]: 36
7863 18:01:18.827450
7864 18:01:18.827560 Set Vref, RX VrefLevel [Byte0]: 37
7865 18:01:18.831027 [Byte1]: 37
7866 18:01:18.835174
7867 18:01:18.835278 Set Vref, RX VrefLevel [Byte0]: 38
7868 18:01:18.838961 [Byte1]: 38
7869 18:01:18.842993
7870 18:01:18.843067 Set Vref, RX VrefLevel [Byte0]: 39
7871 18:01:18.845904 [Byte1]: 39
7872 18:01:18.850642
7873 18:01:18.850726 Set Vref, RX VrefLevel [Byte0]: 40
7874 18:01:18.853622 [Byte1]: 40
7875 18:01:18.857814
7876 18:01:18.857897 Set Vref, RX VrefLevel [Byte0]: 41
7877 18:01:18.861374 [Byte1]: 41
7878 18:01:18.865606
7879 18:01:18.865689 Set Vref, RX VrefLevel [Byte0]: 42
7880 18:01:18.868534 [Byte1]: 42
7881 18:01:18.873247
7882 18:01:18.873330 Set Vref, RX VrefLevel [Byte0]: 43
7883 18:01:18.876790 [Byte1]: 43
7884 18:01:18.881107
7885 18:01:18.881188 Set Vref, RX VrefLevel [Byte0]: 44
7886 18:01:18.883936 [Byte1]: 44
7887 18:01:18.888365
7888 18:01:18.888446 Set Vref, RX VrefLevel [Byte0]: 45
7889 18:01:18.891959 [Byte1]: 45
7890 18:01:18.896194
7891 18:01:18.896275 Set Vref, RX VrefLevel [Byte0]: 46
7892 18:01:18.899250 [Byte1]: 46
7893 18:01:18.903474
7894 18:01:18.903555 Set Vref, RX VrefLevel [Byte0]: 47
7895 18:01:18.907010 [Byte1]: 47
7896 18:01:18.911256
7897 18:01:18.911338 Set Vref, RX VrefLevel [Byte0]: 48
7898 18:01:18.914833 [Byte1]: 48
7899 18:01:18.918974
7900 18:01:18.919055 Set Vref, RX VrefLevel [Byte0]: 49
7901 18:01:18.921975 [Byte1]: 49
7902 18:01:18.926266
7903 18:01:18.926348 Set Vref, RX VrefLevel [Byte0]: 50
7904 18:01:18.929524 [Byte1]: 50
7905 18:01:18.934264
7906 18:01:18.934345 Set Vref, RX VrefLevel [Byte0]: 51
7907 18:01:18.937247 [Byte1]: 51
7908 18:01:18.941556
7909 18:01:18.941696 Set Vref, RX VrefLevel [Byte0]: 52
7910 18:01:18.945077 [Byte1]: 52
7911 18:01:18.949192
7912 18:01:18.949298 Set Vref, RX VrefLevel [Byte0]: 53
7913 18:01:18.952707 [Byte1]: 53
7914 18:01:18.956866
7915 18:01:18.956971 Set Vref, RX VrefLevel [Byte0]: 54
7916 18:01:18.960584 [Byte1]: 54
7917 18:01:18.964312
7918 18:01:18.964414 Set Vref, RX VrefLevel [Byte0]: 55
7919 18:01:18.967910 [Byte1]: 55
7920 18:01:18.972175
7921 18:01:18.972252 Set Vref, RX VrefLevel [Byte0]: 56
7922 18:01:18.975708 [Byte1]: 56
7923 18:01:18.980072
7924 18:01:18.980208 Set Vref, RX VrefLevel [Byte0]: 57
7925 18:01:18.983215 [Byte1]: 57
7926 18:01:18.987348
7927 18:01:18.987452 Set Vref, RX VrefLevel [Byte0]: 58
7928 18:01:18.990957 [Byte1]: 58
7929 18:01:18.995151
7930 18:01:18.995255 Set Vref, RX VrefLevel [Byte0]: 59
7931 18:01:18.998191 [Byte1]: 59
7932 18:01:19.002370
7933 18:01:19.002465 Set Vref, RX VrefLevel [Byte0]: 60
7934 18:01:19.005973 [Byte1]: 60
7935 18:01:19.010361
7936 18:01:19.010496 Set Vref, RX VrefLevel [Byte0]: 61
7937 18:01:19.013435 [Byte1]: 61
7938 18:01:19.017913
7939 18:01:19.018015 Set Vref, RX VrefLevel [Byte0]: 62
7940 18:01:19.021115 [Byte1]: 62
7941 18:01:19.025381
7942 18:01:19.025486 Set Vref, RX VrefLevel [Byte0]: 63
7943 18:01:19.028588 [Byte1]: 63
7944 18:01:19.033370
7945 18:01:19.033479 Set Vref, RX VrefLevel [Byte0]: 64
7946 18:01:19.036258 [Byte1]: 64
7947 18:01:19.040730
7948 18:01:19.040834 Set Vref, RX VrefLevel [Byte0]: 65
7949 18:01:19.044013 [Byte1]: 65
7950 18:01:19.048086
7951 18:01:19.048196 Set Vref, RX VrefLevel [Byte0]: 66
7952 18:01:19.051546 [Byte1]: 66
7953 18:01:19.055648
7954 18:01:19.055760 Set Vref, RX VrefLevel [Byte0]: 67
7955 18:01:19.059131 [Byte1]: 67
7956 18:01:19.063266
7957 18:01:19.063420 Set Vref, RX VrefLevel [Byte0]: 68
7958 18:01:19.066942 [Byte1]: 68
7959 18:01:19.070830
7960 18:01:19.070947 Set Vref, RX VrefLevel [Byte0]: 69
7961 18:01:19.074578 [Byte1]: 69
7962 18:01:19.078821
7963 18:01:19.078926 Set Vref, RX VrefLevel [Byte0]: 70
7964 18:01:19.081810 [Byte1]: 70
7965 18:01:19.086045
7966 18:01:19.086121 Set Vref, RX VrefLevel [Byte0]: 71
7967 18:01:19.089921 [Byte1]: 71
7968 18:01:19.094239
7969 18:01:19.094351 Set Vref, RX VrefLevel [Byte0]: 72
7970 18:01:19.097435 [Byte1]: 72
7971 18:01:19.101703
7972 18:01:19.101812 Set Vref, RX VrefLevel [Byte0]: 73
7973 18:01:19.104639 [Byte1]: 73
7974 18:01:19.109016
7975 18:01:19.109116 Set Vref, RX VrefLevel [Byte0]: 74
7976 18:01:19.112552 [Byte1]: 74
7977 18:01:19.116822
7978 18:01:19.116939 Set Vref, RX VrefLevel [Byte0]: 75
7979 18:01:19.120196 [Byte1]: 75
7980 18:01:19.124480
7981 18:01:19.124588 Set Vref, RX VrefLevel [Byte0]: 76
7982 18:01:19.127571 [Byte1]: 76
7983 18:01:19.132106
7984 18:01:19.132223 Set Vref, RX VrefLevel [Byte0]: 77
7985 18:01:19.135230 [Byte1]: 77
7986 18:01:19.139738
7987 18:01:19.139847 Final RX Vref Byte 0 = 61 to rank0
7988 18:01:19.142775 Final RX Vref Byte 1 = 62 to rank0
7989 18:01:19.145972 Final RX Vref Byte 0 = 61 to rank1
7990 18:01:19.149589 Final RX Vref Byte 1 = 62 to rank1==
7991 18:01:19.152916 Dram Type= 6, Freq= 0, CH_0, rank 0
7992 18:01:19.159384 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7993 18:01:19.159497 ==
7994 18:01:19.159594 DQS Delay:
7995 18:01:19.159686 DQS0 = 0, DQS1 = 0
7996 18:01:19.162788 DQM Delay:
7997 18:01:19.162902 DQM0 = 129, DQM1 = 121
7998 18:01:19.166426 DQ Delay:
7999 18:01:19.169404 DQ0 =130, DQ1 =132, DQ2 =124, DQ3 =126
8000 18:01:19.172864 DQ4 =132, DQ5 =118, DQ6 =136, DQ7 =138
8001 18:01:19.175965 DQ8 =110, DQ9 =108, DQ10 =122, DQ11 =116
8002 18:01:19.179619 DQ12 =126, DQ13 =126, DQ14 =132, DQ15 =132
8003 18:01:19.179705
8004 18:01:19.179773
8005 18:01:19.179833
8006 18:01:19.182702 [DramC_TX_OE_Calibration] TA2
8007 18:01:19.186275 Original DQ_B0 (3 6) =30, OEN = 27
8008 18:01:19.189297 Original DQ_B1 (3 6) =30, OEN = 27
8009 18:01:19.192921 24, 0x0, End_B0=24 End_B1=24
8010 18:01:19.193035 25, 0x0, End_B0=25 End_B1=25
8011 18:01:19.195980 26, 0x0, End_B0=26 End_B1=26
8012 18:01:19.199762 27, 0x0, End_B0=27 End_B1=27
8013 18:01:19.202883 28, 0x0, End_B0=28 End_B1=28
8014 18:01:19.202963 29, 0x0, End_B0=29 End_B1=29
8015 18:01:19.205833 30, 0x0, End_B0=30 End_B1=30
8016 18:01:19.209469 31, 0x4545, End_B0=30 End_B1=30
8017 18:01:19.212917 Byte0 end_step=30 best_step=27
8018 18:01:19.216295 Byte1 end_step=30 best_step=27
8019 18:01:19.219726 Byte0 TX OE(2T, 0.5T) = (3, 3)
8020 18:01:19.219808 Byte1 TX OE(2T, 0.5T) = (3, 3)
8021 18:01:19.222564
8022 18:01:19.222634
8023 18:01:19.229412 [DQSOSCAuto] RK0, (LSB)MR18= 0x1408, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 399 ps
8024 18:01:19.232971 CH0 RK0: MR19=303, MR18=1408
8025 18:01:19.239656 CH0_RK0: MR19=0x303, MR18=0x1408, DQSOSC=399, MR23=63, INC=23, DEC=15
8026 18:01:19.239767
8027 18:01:19.242823 ----->DramcWriteLeveling(PI) begin...
8028 18:01:19.242930 ==
8029 18:01:19.245940 Dram Type= 6, Freq= 0, CH_0, rank 1
8030 18:01:19.249400 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8031 18:01:19.249481 ==
8032 18:01:19.252870 Write leveling (Byte 0): 33 => 33
8033 18:01:19.255848 Write leveling (Byte 1): 28 => 28
8034 18:01:19.259352 DramcWriteLeveling(PI) end<-----
8035 18:01:19.259463
8036 18:01:19.259574 ==
8037 18:01:19.262788 Dram Type= 6, Freq= 0, CH_0, rank 1
8038 18:01:19.266031 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8039 18:01:19.266137 ==
8040 18:01:19.269414 [Gating] SW mode calibration
8041 18:01:19.276482 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8042 18:01:19.282530 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8043 18:01:19.286204 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8044 18:01:19.289321 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8045 18:01:19.295714 1 4 8 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
8046 18:01:19.299450 1 4 12 | B1->B0 | 2323 3131 | 0 1 | (0 0) (1 1)
8047 18:01:19.302579 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8048 18:01:19.309486 1 4 20 | B1->B0 | 2c2c 3434 | 1 1 | (1 1) (1 1)
8049 18:01:19.312710 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8050 18:01:19.315887 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8051 18:01:19.322890 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8052 18:01:19.325751 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8053 18:01:19.329094 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8054 18:01:19.335818 1 5 12 | B1->B0 | 3434 2626 | 1 0 | (1 1) (0 0)
8055 18:01:19.339593 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
8056 18:01:19.342769 1 5 20 | B1->B0 | 3232 2323 | 0 0 | (1 0) (0 0)
8057 18:01:19.348988 1 5 24 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
8058 18:01:19.352760 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8059 18:01:19.355783 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8060 18:01:19.359367 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8061 18:01:19.365494 1 6 8 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
8062 18:01:19.369080 1 6 12 | B1->B0 | 2323 4444 | 0 0 | (0 0) (0 0)
8063 18:01:19.372801 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8064 18:01:19.378965 1 6 20 | B1->B0 | 2f2f 4646 | 0 0 | (0 0) (0 0)
8065 18:01:19.382700 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8066 18:01:19.385631 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8067 18:01:19.392217 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8068 18:01:19.395674 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8069 18:01:19.399069 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8070 18:01:19.405993 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8071 18:01:19.409218 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8072 18:01:19.412454 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8073 18:01:19.418822 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8074 18:01:19.422796 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8075 18:01:19.425985 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8076 18:01:19.432074 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8077 18:01:19.435670 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8078 18:01:19.438966 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8079 18:01:19.445871 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8080 18:01:19.448868 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8081 18:01:19.452449 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8082 18:01:19.458913 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8083 18:01:19.462020 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8084 18:01:19.465513 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8085 18:01:19.469126 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8086 18:01:19.475425 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8087 18:01:19.478873 Total UI for P1: 0, mck2ui 16
8088 18:01:19.482464 best dqsien dly found for B0: ( 1, 9, 8)
8089 18:01:19.485829 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8090 18:01:19.489010 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8091 18:01:19.495721 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8092 18:01:19.498828 Total UI for P1: 0, mck2ui 16
8093 18:01:19.502256 best dqsien dly found for B1: ( 1, 9, 18)
8094 18:01:19.505519 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8095 18:01:19.508834 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8096 18:01:19.508956
8097 18:01:19.512100 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8098 18:01:19.515861 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8099 18:01:19.519098 [Gating] SW calibration Done
8100 18:01:19.519206 ==
8101 18:01:19.522183 Dram Type= 6, Freq= 0, CH_0, rank 1
8102 18:01:19.525998 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8103 18:01:19.526093 ==
8104 18:01:19.528985 RX Vref Scan: 0
8105 18:01:19.529070
8106 18:01:19.529135 RX Vref 0 -> 0, step: 1
8107 18:01:19.529196
8108 18:01:19.532696 RX Delay 0 -> 252, step: 8
8109 18:01:19.535819 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8110 18:01:19.542789 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8111 18:01:19.545846 iDelay=200, Bit 2, Center 131 (72 ~ 191) 120
8112 18:01:19.549272 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8113 18:01:19.552664 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8114 18:01:19.555783 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8115 18:01:19.562495 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8116 18:01:19.565462 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8117 18:01:19.568900 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8118 18:01:19.572611 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8119 18:01:19.575812 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8120 18:01:19.582901 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8121 18:01:19.585589 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8122 18:01:19.589016 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8123 18:01:19.592585 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8124 18:01:19.595946 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8125 18:01:19.596035 ==
8126 18:01:19.598991 Dram Type= 6, Freq= 0, CH_0, rank 1
8127 18:01:19.606201 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8128 18:01:19.606287 ==
8129 18:01:19.606369 DQS Delay:
8130 18:01:19.609139 DQS0 = 0, DQS1 = 0
8131 18:01:19.609218 DQM Delay:
8132 18:01:19.612701 DQM0 = 131, DQM1 = 123
8133 18:01:19.612786 DQ Delay:
8134 18:01:19.615929 DQ0 =131, DQ1 =131, DQ2 =131, DQ3 =131
8135 18:01:19.618942 DQ4 =131, DQ5 =119, DQ6 =139, DQ7 =139
8136 18:01:19.622604 DQ8 =115, DQ9 =115, DQ10 =123, DQ11 =115
8137 18:01:19.625681 DQ12 =127, DQ13 =131, DQ14 =131, DQ15 =131
8138 18:01:19.625766
8139 18:01:19.625832
8140 18:01:19.625894 ==
8141 18:01:19.629226 Dram Type= 6, Freq= 0, CH_0, rank 1
8142 18:01:19.632926 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8143 18:01:19.635983 ==
8144 18:01:19.636067
8145 18:01:19.636152
8146 18:01:19.636215 TX Vref Scan disable
8147 18:01:19.639142 == TX Byte 0 ==
8148 18:01:19.642729 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8149 18:01:19.645907 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8150 18:01:19.649581 == TX Byte 1 ==
8151 18:01:19.652605 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8152 18:01:19.656118 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8153 18:01:19.659216 ==
8154 18:01:19.659295 Dram Type= 6, Freq= 0, CH_0, rank 1
8155 18:01:19.666126 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8156 18:01:19.666224 ==
8157 18:01:19.679645
8158 18:01:19.683143 TX Vref early break, caculate TX vref
8159 18:01:19.686150 TX Vref=16, minBit 1, minWin=22, winSum=369
8160 18:01:19.689220 TX Vref=18, minBit 0, minWin=23, winSum=382
8161 18:01:19.692824 TX Vref=20, minBit 2, minWin=23, winSum=394
8162 18:01:19.696262 TX Vref=22, minBit 0, minWin=24, winSum=400
8163 18:01:19.699147 TX Vref=24, minBit 1, minWin=24, winSum=406
8164 18:01:19.705940 TX Vref=26, minBit 0, minWin=25, winSum=416
8165 18:01:19.709878 TX Vref=28, minBit 1, minWin=25, winSum=420
8166 18:01:19.712815 TX Vref=30, minBit 4, minWin=25, winSum=421
8167 18:01:19.715940 TX Vref=32, minBit 0, minWin=24, winSum=418
8168 18:01:19.719477 TX Vref=34, minBit 0, minWin=24, winSum=399
8169 18:01:19.722932 TX Vref=36, minBit 4, minWin=23, winSum=393
8170 18:01:19.729463 [TxChooseVref] Worse bit 4, Min win 25, Win sum 421, Final Vref 30
8171 18:01:19.729549
8172 18:01:19.733189 Final TX Range 0 Vref 30
8173 18:01:19.733281
8174 18:01:19.733380 ==
8175 18:01:19.736294 Dram Type= 6, Freq= 0, CH_0, rank 1
8176 18:01:19.739348 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8177 18:01:19.739427 ==
8178 18:01:19.739501
8179 18:01:19.739563
8180 18:01:19.742920 TX Vref Scan disable
8181 18:01:19.749740 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8182 18:01:19.749822 == TX Byte 0 ==
8183 18:01:19.752821 u2DelayCellOfst[0]=14 cells (4 PI)
8184 18:01:19.755866 u2DelayCellOfst[1]=17 cells (5 PI)
8185 18:01:19.759579 u2DelayCellOfst[2]=10 cells (3 PI)
8186 18:01:19.762612 u2DelayCellOfst[3]=10 cells (3 PI)
8187 18:01:19.766336 u2DelayCellOfst[4]=10 cells (3 PI)
8188 18:01:19.769432 u2DelayCellOfst[5]=0 cells (0 PI)
8189 18:01:19.772840 u2DelayCellOfst[6]=17 cells (5 PI)
8190 18:01:19.776151 u2DelayCellOfst[7]=17 cells (5 PI)
8191 18:01:19.779166 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
8192 18:01:19.782579 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8193 18:01:19.785874 == TX Byte 1 ==
8194 18:01:19.789258 u2DelayCellOfst[8]=0 cells (0 PI)
8195 18:01:19.789343 u2DelayCellOfst[9]=0 cells (0 PI)
8196 18:01:19.792846 u2DelayCellOfst[10]=7 cells (2 PI)
8197 18:01:19.795901 u2DelayCellOfst[11]=0 cells (0 PI)
8198 18:01:19.799530 u2DelayCellOfst[12]=14 cells (4 PI)
8199 18:01:19.802911 u2DelayCellOfst[13]=14 cells (4 PI)
8200 18:01:19.806086 u2DelayCellOfst[14]=14 cells (4 PI)
8201 18:01:19.809191 u2DelayCellOfst[15]=14 cells (4 PI)
8202 18:01:19.812738 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8203 18:01:19.819343 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8204 18:01:19.819444 DramC Write-DBI on
8205 18:01:19.819525 ==
8206 18:01:19.822748 Dram Type= 6, Freq= 0, CH_0, rank 1
8207 18:01:19.825777 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8208 18:01:19.829214 ==
8209 18:01:19.829297
8210 18:01:19.829361
8211 18:01:19.829421 TX Vref Scan disable
8212 18:01:19.832674 == TX Byte 0 ==
8213 18:01:19.836515 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
8214 18:01:19.839808 == TX Byte 1 ==
8215 18:01:19.842890 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
8216 18:01:19.842982 DramC Write-DBI off
8217 18:01:19.846623
8218 18:01:19.846699 [DATLAT]
8219 18:01:19.846763 Freq=1600, CH0 RK1
8220 18:01:19.846828
8221 18:01:19.849720 DATLAT Default: 0xf
8222 18:01:19.849795 0, 0xFFFF, sum = 0
8223 18:01:19.852807 1, 0xFFFF, sum = 0
8224 18:01:19.852890 2, 0xFFFF, sum = 0
8225 18:01:19.856408 3, 0xFFFF, sum = 0
8226 18:01:19.856489 4, 0xFFFF, sum = 0
8227 18:01:19.859500 5, 0xFFFF, sum = 0
8228 18:01:19.859585 6, 0xFFFF, sum = 0
8229 18:01:19.863002 7, 0xFFFF, sum = 0
8230 18:01:19.866177 8, 0xFFFF, sum = 0
8231 18:01:19.866261 9, 0xFFFF, sum = 0
8232 18:01:19.869838 10, 0xFFFF, sum = 0
8233 18:01:19.869916 11, 0xFFFF, sum = 0
8234 18:01:19.872866 12, 0xFFFF, sum = 0
8235 18:01:19.872969 13, 0xFFFF, sum = 0
8236 18:01:19.876512 14, 0x0, sum = 1
8237 18:01:19.876607 15, 0x0, sum = 2
8238 18:01:19.879584 16, 0x0, sum = 3
8239 18:01:19.879661 17, 0x0, sum = 4
8240 18:01:19.882983 best_step = 15
8241 18:01:19.883058
8242 18:01:19.883121 ==
8243 18:01:19.886449 Dram Type= 6, Freq= 0, CH_0, rank 1
8244 18:01:19.889498 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8245 18:01:19.889583 ==
8246 18:01:19.889657 RX Vref Scan: 0
8247 18:01:19.889723
8248 18:01:19.892866 RX Vref 0 -> 0, step: 1
8249 18:01:19.892954
8250 18:01:19.896263 RX Delay 11 -> 252, step: 4
8251 18:01:19.899266 iDelay=195, Bit 0, Center 126 (71 ~ 182) 112
8252 18:01:19.905954 iDelay=195, Bit 1, Center 130 (75 ~ 186) 112
8253 18:01:19.909481 iDelay=195, Bit 2, Center 126 (71 ~ 182) 112
8254 18:01:19.913029 iDelay=195, Bit 3, Center 126 (71 ~ 182) 112
8255 18:01:19.915834 iDelay=195, Bit 4, Center 126 (71 ~ 182) 112
8256 18:01:19.919486 iDelay=195, Bit 5, Center 116 (63 ~ 170) 108
8257 18:01:19.926156 iDelay=195, Bit 6, Center 136 (79 ~ 194) 116
8258 18:01:19.929650 iDelay=195, Bit 7, Center 134 (79 ~ 190) 112
8259 18:01:19.933091 iDelay=195, Bit 8, Center 112 (59 ~ 166) 108
8260 18:01:19.935980 iDelay=195, Bit 9, Center 110 (55 ~ 166) 112
8261 18:01:19.939537 iDelay=195, Bit 10, Center 122 (67 ~ 178) 112
8262 18:01:19.942963 iDelay=195, Bit 11, Center 116 (63 ~ 170) 108
8263 18:01:19.949609 iDelay=195, Bit 12, Center 126 (75 ~ 178) 104
8264 18:01:19.953231 iDelay=195, Bit 13, Center 126 (71 ~ 182) 112
8265 18:01:19.956247 iDelay=195, Bit 14, Center 134 (79 ~ 190) 112
8266 18:01:19.959909 iDelay=195, Bit 15, Center 130 (75 ~ 186) 112
8267 18:01:19.959990 ==
8268 18:01:19.962867 Dram Type= 6, Freq= 0, CH_0, rank 1
8269 18:01:19.969526 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8270 18:01:19.969607 ==
8271 18:01:19.969673 DQS Delay:
8272 18:01:19.973210 DQS0 = 0, DQS1 = 0
8273 18:01:19.973293 DQM Delay:
8274 18:01:19.976192 DQM0 = 127, DQM1 = 122
8275 18:01:19.976271 DQ Delay:
8276 18:01:19.979470 DQ0 =126, DQ1 =130, DQ2 =126, DQ3 =126
8277 18:01:19.982693 DQ4 =126, DQ5 =116, DQ6 =136, DQ7 =134
8278 18:01:19.986412 DQ8 =112, DQ9 =110, DQ10 =122, DQ11 =116
8279 18:01:19.989669 DQ12 =126, DQ13 =126, DQ14 =134, DQ15 =130
8280 18:01:19.989779
8281 18:01:19.989872
8282 18:01:19.989936
8283 18:01:19.992761 [DramC_TX_OE_Calibration] TA2
8284 18:01:19.996541 Original DQ_B0 (3 6) =30, OEN = 27
8285 18:01:19.999437 Original DQ_B1 (3 6) =30, OEN = 27
8286 18:01:20.002886 24, 0x0, End_B0=24 End_B1=24
8287 18:01:20.002973 25, 0x0, End_B0=25 End_B1=25
8288 18:01:20.006162 26, 0x0, End_B0=26 End_B1=26
8289 18:01:20.009625 27, 0x0, End_B0=27 End_B1=27
8290 18:01:20.012836 28, 0x0, End_B0=28 End_B1=28
8291 18:01:20.016494 29, 0x0, End_B0=29 End_B1=29
8292 18:01:20.016580 30, 0x0, End_B0=30 End_B1=30
8293 18:01:20.019641 31, 0x4141, End_B0=30 End_B1=30
8294 18:01:20.022898 Byte0 end_step=30 best_step=27
8295 18:01:20.026204 Byte1 end_step=30 best_step=27
8296 18:01:20.029507 Byte0 TX OE(2T, 0.5T) = (3, 3)
8297 18:01:20.033167 Byte1 TX OE(2T, 0.5T) = (3, 3)
8298 18:01:20.033280
8299 18:01:20.033374
8300 18:01:20.039823 [DQSOSCAuto] RK1, (LSB)MR18= 0x1509, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 399 ps
8301 18:01:20.042674 CH0 RK1: MR19=303, MR18=1509
8302 18:01:20.049723 CH0_RK1: MR19=0x303, MR18=0x1509, DQSOSC=399, MR23=63, INC=23, DEC=15
8303 18:01:20.052785 [RxdqsGatingPostProcess] freq 1600
8304 18:01:20.056503 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8305 18:01:20.059650 best DQS0 dly(2T, 0.5T) = (1, 1)
8306 18:01:20.062878 best DQS1 dly(2T, 0.5T) = (1, 1)
8307 18:01:20.066030 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8308 18:01:20.069805 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8309 18:01:20.073055 best DQS0 dly(2T, 0.5T) = (1, 1)
8310 18:01:20.076050 best DQS1 dly(2T, 0.5T) = (1, 1)
8311 18:01:20.079833 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8312 18:01:20.082982 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8313 18:01:20.086012 Pre-setting of DQS Precalculation
8314 18:01:20.089838 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8315 18:01:20.089951 ==
8316 18:01:20.092851 Dram Type= 6, Freq= 0, CH_1, rank 0
8317 18:01:20.096106 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8318 18:01:20.096191 ==
8319 18:01:20.103031 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8320 18:01:20.106307 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8321 18:01:20.113109 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8322 18:01:20.116125 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8323 18:01:20.125965 [CA 0] Center 42 (14~70) winsize 57
8324 18:01:20.129212 [CA 1] Center 42 (14~71) winsize 58
8325 18:01:20.132616 [CA 2] Center 37 (8~66) winsize 59
8326 18:01:20.135999 [CA 3] Center 36 (7~66) winsize 60
8327 18:01:20.138943 [CA 4] Center 36 (7~66) winsize 60
8328 18:01:20.142329 [CA 5] Center 36 (7~66) winsize 60
8329 18:01:20.142414
8330 18:01:20.146040 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8331 18:01:20.146122
8332 18:01:20.149197 [CATrainingPosCal] consider 1 rank data
8333 18:01:20.152502 u2DelayCellTimex100 = 275/100 ps
8334 18:01:20.155689 CA0 delay=42 (14~70),Diff = 6 PI (21 cell)
8335 18:01:20.162346 CA1 delay=42 (14~71),Diff = 6 PI (21 cell)
8336 18:01:20.165764 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8337 18:01:20.169324 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8338 18:01:20.173044 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
8339 18:01:20.176169 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8340 18:01:20.176258
8341 18:01:20.179286 CA PerBit enable=1, Macro0, CA PI delay=36
8342 18:01:20.179392
8343 18:01:20.183112 [CBTSetCACLKResult] CA Dly = 36
8344 18:01:20.183216 CS Dly: 9 (0~40)
8345 18:01:20.189288 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8346 18:01:20.192545 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8347 18:01:20.192658 ==
8348 18:01:20.196189 Dram Type= 6, Freq= 0, CH_1, rank 1
8349 18:01:20.199277 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8350 18:01:20.199366 ==
8351 18:01:20.206201 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8352 18:01:20.209427 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8353 18:01:20.216060 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8354 18:01:20.219048 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8355 18:01:20.229180 [CA 0] Center 43 (14~72) winsize 59
8356 18:01:20.232258 [CA 1] Center 43 (14~72) winsize 59
8357 18:01:20.236010 [CA 2] Center 38 (9~67) winsize 59
8358 18:01:20.238871 [CA 3] Center 37 (8~67) winsize 60
8359 18:01:20.242269 [CA 4] Center 38 (8~68) winsize 61
8360 18:01:20.245566 [CA 5] Center 37 (8~66) winsize 59
8361 18:01:20.245646
8362 18:01:20.249031 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8363 18:01:20.249147
8364 18:01:20.252136 [CATrainingPosCal] consider 2 rank data
8365 18:01:20.256148 u2DelayCellTimex100 = 275/100 ps
8366 18:01:20.259221 CA0 delay=42 (14~70),Diff = 5 PI (17 cell)
8367 18:01:20.265777 CA1 delay=42 (14~71),Diff = 5 PI (17 cell)
8368 18:01:20.268761 CA2 delay=37 (9~66),Diff = 0 PI (0 cell)
8369 18:01:20.272097 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8370 18:01:20.275295 CA4 delay=37 (8~66),Diff = 0 PI (0 cell)
8371 18:01:20.278804 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8372 18:01:20.278879
8373 18:01:20.281939 CA PerBit enable=1, Macro0, CA PI delay=37
8374 18:01:20.282016
8375 18:01:20.285311 [CBTSetCACLKResult] CA Dly = 37
8376 18:01:20.288958 CS Dly: 11 (0~44)
8377 18:01:20.292153 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8378 18:01:20.295286 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8379 18:01:20.295386
8380 18:01:20.298544 ----->DramcWriteLeveling(PI) begin...
8381 18:01:20.298636 ==
8382 18:01:20.302273 Dram Type= 6, Freq= 0, CH_1, rank 0
8383 18:01:20.308549 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8384 18:01:20.308628 ==
8385 18:01:20.312205 Write leveling (Byte 0): 24 => 24
8386 18:01:20.312285 Write leveling (Byte 1): 28 => 28
8387 18:01:20.315432 DramcWriteLeveling(PI) end<-----
8388 18:01:20.315512
8389 18:01:20.315574 ==
8390 18:01:20.318531 Dram Type= 6, Freq= 0, CH_1, rank 0
8391 18:01:20.325177 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8392 18:01:20.325262 ==
8393 18:01:20.328858 [Gating] SW mode calibration
8394 18:01:20.335049 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8395 18:01:20.338767 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8396 18:01:20.345380 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8397 18:01:20.348341 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8398 18:01:20.351837 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8399 18:01:20.358574 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8400 18:01:20.361957 1 4 16 | B1->B0 | 2727 2424 | 0 0 | (0 0) (0 0)
8401 18:01:20.364884 1 4 20 | B1->B0 | 3434 3333 | 1 1 | (0 0) (1 1)
8402 18:01:20.371697 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8403 18:01:20.374876 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8404 18:01:20.378419 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8405 18:01:20.384984 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8406 18:01:20.388555 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8407 18:01:20.391443 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8408 18:01:20.395180 1 5 16 | B1->B0 | 2b2b 3434 | 0 0 | (1 0) (0 1)
8409 18:01:20.401705 1 5 20 | B1->B0 | 2424 2626 | 0 0 | (0 0) (0 0)
8410 18:01:20.404826 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8411 18:01:20.408147 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8412 18:01:20.414868 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8413 18:01:20.417979 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8414 18:01:20.421721 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8415 18:01:20.428379 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8416 18:01:20.431428 1 6 16 | B1->B0 | 4242 3838 | 0 0 | (0 0) (0 0)
8417 18:01:20.435109 1 6 20 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8418 18:01:20.441348 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8419 18:01:20.445072 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8420 18:01:20.448084 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8421 18:01:20.455059 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8422 18:01:20.458151 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8423 18:01:20.461388 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8424 18:01:20.468224 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8425 18:01:20.471656 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8426 18:01:20.474490 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8427 18:01:20.481164 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8428 18:01:20.484633 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8429 18:01:20.488235 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8430 18:01:20.495058 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8431 18:01:20.498074 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8432 18:01:20.501568 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8433 18:01:20.505024 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8434 18:01:20.511271 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8435 18:01:20.514942 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8436 18:01:20.518043 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8437 18:01:20.524682 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8438 18:01:20.528094 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8439 18:01:20.531752 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8440 18:01:20.537872 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8441 18:01:20.541432 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8442 18:01:20.544483 Total UI for P1: 0, mck2ui 16
8443 18:01:20.547985 best dqsien dly found for B0: ( 1, 9, 16)
8444 18:01:20.551704 Total UI for P1: 0, mck2ui 16
8445 18:01:20.554650 best dqsien dly found for B1: ( 1, 9, 16)
8446 18:01:20.558478 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
8447 18:01:20.561164 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8448 18:01:20.561253
8449 18:01:20.564727 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
8450 18:01:20.568262 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8451 18:01:20.571839 [Gating] SW calibration Done
8452 18:01:20.571918 ==
8453 18:01:20.574849 Dram Type= 6, Freq= 0, CH_1, rank 0
8454 18:01:20.577839 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8455 18:01:20.581375 ==
8456 18:01:20.581453 RX Vref Scan: 0
8457 18:01:20.581539
8458 18:01:20.584640 RX Vref 0 -> 0, step: 1
8459 18:01:20.584754
8460 18:01:20.587863 RX Delay 0 -> 252, step: 8
8461 18:01:20.591307 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8462 18:01:20.595108 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8463 18:01:20.598057 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8464 18:01:20.601798 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8465 18:01:20.604765 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8466 18:01:20.611997 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8467 18:01:20.614797 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
8468 18:01:20.617939 iDelay=200, Bit 7, Center 131 (80 ~ 183) 104
8469 18:01:20.621277 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8470 18:01:20.624863 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
8471 18:01:20.631334 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8472 18:01:20.634776 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8473 18:01:20.638501 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8474 18:01:20.641409 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8475 18:01:20.644857 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8476 18:01:20.651492 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8477 18:01:20.651572 ==
8478 18:01:20.654578 Dram Type= 6, Freq= 0, CH_1, rank 0
8479 18:01:20.658242 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8480 18:01:20.658349 ==
8481 18:01:20.658458 DQS Delay:
8482 18:01:20.661392 DQS0 = 0, DQS1 = 0
8483 18:01:20.661468 DQM Delay:
8484 18:01:20.664827 DQM0 = 134, DQM1 = 127
8485 18:01:20.664930 DQ Delay:
8486 18:01:20.668497 DQ0 =139, DQ1 =127, DQ2 =123, DQ3 =135
8487 18:01:20.671510 DQ4 =135, DQ5 =143, DQ6 =143, DQ7 =131
8488 18:01:20.674883 DQ8 =115, DQ9 =115, DQ10 =127, DQ11 =123
8489 18:01:20.678144 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8490 18:01:20.678254
8491 18:01:20.678345
8492 18:01:20.681753 ==
8493 18:01:20.684812 Dram Type= 6, Freq= 0, CH_1, rank 0
8494 18:01:20.688494 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8495 18:01:20.688593 ==
8496 18:01:20.688682
8497 18:01:20.688782
8498 18:01:20.691460 TX Vref Scan disable
8499 18:01:20.691569 == TX Byte 0 ==
8500 18:01:20.694683 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8501 18:01:20.701407 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8502 18:01:20.701586 == TX Byte 1 ==
8503 18:01:20.704926 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8504 18:01:20.711480 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8505 18:01:20.711562 ==
8506 18:01:20.715095 Dram Type= 6, Freq= 0, CH_1, rank 0
8507 18:01:20.718161 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8508 18:01:20.718259 ==
8509 18:01:20.732583
8510 18:01:20.735930 TX Vref early break, caculate TX vref
8511 18:01:20.739266 TX Vref=16, minBit 8, minWin=21, winSum=364
8512 18:01:20.742383 TX Vref=18, minBit 8, minWin=21, winSum=368
8513 18:01:20.746011 TX Vref=20, minBit 8, minWin=22, winSum=386
8514 18:01:20.749095 TX Vref=22, minBit 8, minWin=22, winSum=393
8515 18:01:20.752794 TX Vref=24, minBit 8, minWin=23, winSum=404
8516 18:01:20.758894 TX Vref=26, minBit 8, minWin=24, winSum=413
8517 18:01:20.762628 TX Vref=28, minBit 0, minWin=25, winSum=417
8518 18:01:20.765698 TX Vref=30, minBit 8, minWin=25, winSum=416
8519 18:01:20.768785 TX Vref=32, minBit 0, minWin=25, winSum=411
8520 18:01:20.772400 TX Vref=34, minBit 8, minWin=23, winSum=396
8521 18:01:20.775478 TX Vref=36, minBit 0, minWin=23, winSum=385
8522 18:01:20.782537 [TxChooseVref] Worse bit 0, Min win 25, Win sum 417, Final Vref 28
8523 18:01:20.782621
8524 18:01:20.785898 Final TX Range 0 Vref 28
8525 18:01:20.785982
8526 18:01:20.786048 ==
8527 18:01:20.789531 Dram Type= 6, Freq= 0, CH_1, rank 0
8528 18:01:20.792557 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8529 18:01:20.792642 ==
8530 18:01:20.792707
8531 18:01:20.792768
8532 18:01:20.795481 TX Vref Scan disable
8533 18:01:20.802793 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8534 18:01:20.802877 == TX Byte 0 ==
8535 18:01:20.805978 u2DelayCellOfst[0]=17 cells (5 PI)
8536 18:01:20.808878 u2DelayCellOfst[1]=10 cells (3 PI)
8537 18:01:20.812677 u2DelayCellOfst[2]=0 cells (0 PI)
8538 18:01:20.815694 u2DelayCellOfst[3]=7 cells (2 PI)
8539 18:01:20.819311 u2DelayCellOfst[4]=7 cells (2 PI)
8540 18:01:20.822294 u2DelayCellOfst[5]=17 cells (5 PI)
8541 18:01:20.825998 u2DelayCellOfst[6]=17 cells (5 PI)
8542 18:01:20.829107 u2DelayCellOfst[7]=7 cells (2 PI)
8543 18:01:20.832202 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8544 18:01:20.836061 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8545 18:01:20.838962 == TX Byte 1 ==
8546 18:01:20.839049 u2DelayCellOfst[8]=0 cells (0 PI)
8547 18:01:20.842337 u2DelayCellOfst[9]=3 cells (1 PI)
8548 18:01:20.845475 u2DelayCellOfst[10]=10 cells (3 PI)
8549 18:01:20.848920 u2DelayCellOfst[11]=10 cells (3 PI)
8550 18:01:20.852386 u2DelayCellOfst[12]=14 cells (4 PI)
8551 18:01:20.855515 u2DelayCellOfst[13]=17 cells (5 PI)
8552 18:01:20.858804 u2DelayCellOfst[14]=17 cells (5 PI)
8553 18:01:20.862075 u2DelayCellOfst[15]=17 cells (5 PI)
8554 18:01:20.865796 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8555 18:01:20.872562 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8556 18:01:20.872678 DramC Write-DBI on
8557 18:01:20.872783 ==
8558 18:01:20.875621 Dram Type= 6, Freq= 0, CH_1, rank 0
8559 18:01:20.879301 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8560 18:01:20.882335 ==
8561 18:01:20.882440
8562 18:01:20.882540
8563 18:01:20.882640 TX Vref Scan disable
8564 18:01:20.886040 == TX Byte 0 ==
8565 18:01:20.889042 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8566 18:01:20.892416 == TX Byte 1 ==
8567 18:01:20.896051 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8568 18:01:20.899306 DramC Write-DBI off
8569 18:01:20.899386
8570 18:01:20.899468 [DATLAT]
8571 18:01:20.899549 Freq=1600, CH1 RK0
8572 18:01:20.899655
8573 18:01:20.902361 DATLAT Default: 0xf
8574 18:01:20.902439 0, 0xFFFF, sum = 0
8575 18:01:20.905649 1, 0xFFFF, sum = 0
8576 18:01:20.905729 2, 0xFFFF, sum = 0
8577 18:01:20.909091 3, 0xFFFF, sum = 0
8578 18:01:20.912639 4, 0xFFFF, sum = 0
8579 18:01:20.912751 5, 0xFFFF, sum = 0
8580 18:01:20.915639 6, 0xFFFF, sum = 0
8581 18:01:20.915744 7, 0xFFFF, sum = 0
8582 18:01:20.919038 8, 0xFFFF, sum = 0
8583 18:01:20.919142 9, 0xFFFF, sum = 0
8584 18:01:20.922368 10, 0xFFFF, sum = 0
8585 18:01:20.922475 11, 0xFFFF, sum = 0
8586 18:01:20.925502 12, 0xFFFF, sum = 0
8587 18:01:20.925582 13, 0xFFFF, sum = 0
8588 18:01:20.929186 14, 0x0, sum = 1
8589 18:01:20.929267 15, 0x0, sum = 2
8590 18:01:20.932299 16, 0x0, sum = 3
8591 18:01:20.932404 17, 0x0, sum = 4
8592 18:01:20.935396 best_step = 15
8593 18:01:20.935497
8594 18:01:20.935595 ==
8595 18:01:20.939040 Dram Type= 6, Freq= 0, CH_1, rank 0
8596 18:01:20.942218 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8597 18:01:20.942304 ==
8598 18:01:20.942369 RX Vref Scan: 1
8599 18:01:20.945811
8600 18:01:20.945893 Set Vref Range= 24 -> 127
8601 18:01:20.945959
8602 18:01:20.948865 RX Vref 24 -> 127, step: 1
8603 18:01:20.948983
8604 18:01:20.952296 RX Delay 19 -> 252, step: 4
8605 18:01:20.952379
8606 18:01:20.955805 Set Vref, RX VrefLevel [Byte0]: 24
8607 18:01:20.959083 [Byte1]: 24
8608 18:01:20.959190
8609 18:01:20.962326 Set Vref, RX VrefLevel [Byte0]: 25
8610 18:01:20.965514 [Byte1]: 25
8611 18:01:20.965626
8612 18:01:20.968861 Set Vref, RX VrefLevel [Byte0]: 26
8613 18:01:20.972573 [Byte1]: 26
8614 18:01:20.975765
8615 18:01:20.975847 Set Vref, RX VrefLevel [Byte0]: 27
8616 18:01:20.979442 [Byte1]: 27
8617 18:01:20.983813
8618 18:01:20.983899 Set Vref, RX VrefLevel [Byte0]: 28
8619 18:01:20.986849 [Byte1]: 28
8620 18:01:20.991138
8621 18:01:20.991236 Set Vref, RX VrefLevel [Byte0]: 29
8622 18:01:20.994307 [Byte1]: 29
8623 18:01:20.998504
8624 18:01:20.998586 Set Vref, RX VrefLevel [Byte0]: 30
8625 18:01:21.001942 [Byte1]: 30
8626 18:01:21.006305
8627 18:01:21.006388 Set Vref, RX VrefLevel [Byte0]: 31
8628 18:01:21.009952 [Byte1]: 31
8629 18:01:21.013780
8630 18:01:21.013878 Set Vref, RX VrefLevel [Byte0]: 32
8631 18:01:21.017273 [Byte1]: 32
8632 18:01:21.021331
8633 18:01:21.021413 Set Vref, RX VrefLevel [Byte0]: 33
8634 18:01:21.024825 [Byte1]: 33
8635 18:01:21.028847
8636 18:01:21.028931 Set Vref, RX VrefLevel [Byte0]: 34
8637 18:01:21.032534 [Byte1]: 34
8638 18:01:21.036830
8639 18:01:21.036935 Set Vref, RX VrefLevel [Byte0]: 35
8640 18:01:21.039875 [Byte1]: 35
8641 18:01:21.044186
8642 18:01:21.044267 Set Vref, RX VrefLevel [Byte0]: 36
8643 18:01:21.047239 [Byte1]: 36
8644 18:01:21.052058
8645 18:01:21.052163 Set Vref, RX VrefLevel [Byte0]: 37
8646 18:01:21.055082 [Byte1]: 37
8647 18:01:21.059197
8648 18:01:21.059279 Set Vref, RX VrefLevel [Byte0]: 38
8649 18:01:21.062683 [Byte1]: 38
8650 18:01:21.066939
8651 18:01:21.067023 Set Vref, RX VrefLevel [Byte0]: 39
8652 18:01:21.070330 [Byte1]: 39
8653 18:01:21.074485
8654 18:01:21.074561 Set Vref, RX VrefLevel [Byte0]: 40
8655 18:01:21.077663 [Byte1]: 40
8656 18:01:21.082014
8657 18:01:21.082094 Set Vref, RX VrefLevel [Byte0]: 41
8658 18:01:21.085063 [Byte1]: 41
8659 18:01:21.089421
8660 18:01:21.089505 Set Vref, RX VrefLevel [Byte0]: 42
8661 18:01:21.093175 [Byte1]: 42
8662 18:01:21.096837
8663 18:01:21.096921 Set Vref, RX VrefLevel [Byte0]: 43
8664 18:01:21.100474 [Byte1]: 43
8665 18:01:21.104836
8666 18:01:21.104947 Set Vref, RX VrefLevel [Byte0]: 44
8667 18:01:21.107825 [Byte1]: 44
8668 18:01:21.112401
8669 18:01:21.112506 Set Vref, RX VrefLevel [Byte0]: 45
8670 18:01:21.115731 [Byte1]: 45
8671 18:01:21.119774
8672 18:01:21.119863 Set Vref, RX VrefLevel [Byte0]: 46
8673 18:01:21.123179 [Byte1]: 46
8674 18:01:21.127225
8675 18:01:21.127310 Set Vref, RX VrefLevel [Byte0]: 47
8676 18:01:21.130746 [Byte1]: 47
8677 18:01:21.134819
8678 18:01:21.134902 Set Vref, RX VrefLevel [Byte0]: 48
8679 18:01:21.138381 [Byte1]: 48
8680 18:01:21.142740
8681 18:01:21.142830 Set Vref, RX VrefLevel [Byte0]: 49
8682 18:01:21.146253 [Byte1]: 49
8683 18:01:21.150507
8684 18:01:21.150591 Set Vref, RX VrefLevel [Byte0]: 50
8685 18:01:21.153539 [Byte1]: 50
8686 18:01:21.157704
8687 18:01:21.157789 Set Vref, RX VrefLevel [Byte0]: 51
8688 18:01:21.161234 [Byte1]: 51
8689 18:01:21.165306
8690 18:01:21.165389 Set Vref, RX VrefLevel [Byte0]: 52
8691 18:01:21.168795 [Byte1]: 52
8692 18:01:21.173097
8693 18:01:21.173181 Set Vref, RX VrefLevel [Byte0]: 53
8694 18:01:21.175966 [Byte1]: 53
8695 18:01:21.180239
8696 18:01:21.180352 Set Vref, RX VrefLevel [Byte0]: 54
8697 18:01:21.183534 [Byte1]: 54
8698 18:01:21.188255
8699 18:01:21.188338 Set Vref, RX VrefLevel [Byte0]: 55
8700 18:01:21.191408 [Byte1]: 55
8701 18:01:21.195464
8702 18:01:21.195547 Set Vref, RX VrefLevel [Byte0]: 56
8703 18:01:21.199185 [Byte1]: 56
8704 18:01:21.203464
8705 18:01:21.203560 Set Vref, RX VrefLevel [Byte0]: 57
8706 18:01:21.206494 [Byte1]: 57
8707 18:01:21.210789
8708 18:01:21.210900 Set Vref, RX VrefLevel [Byte0]: 58
8709 18:01:21.213870 [Byte1]: 58
8710 18:01:21.217999
8711 18:01:21.218114 Set Vref, RX VrefLevel [Byte0]: 59
8712 18:01:21.221663 [Byte1]: 59
8713 18:01:21.225659
8714 18:01:21.225741 Set Vref, RX VrefLevel [Byte0]: 60
8715 18:01:21.229319 [Byte1]: 60
8716 18:01:21.233461
8717 18:01:21.233563 Set Vref, RX VrefLevel [Byte0]: 61
8718 18:01:21.236558 [Byte1]: 61
8719 18:01:21.240819
8720 18:01:21.240901 Set Vref, RX VrefLevel [Byte0]: 62
8721 18:01:21.244605 [Byte1]: 62
8722 18:01:21.248737
8723 18:01:21.248835 Set Vref, RX VrefLevel [Byte0]: 63
8724 18:01:21.251901 [Byte1]: 63
8725 18:01:21.255991
8726 18:01:21.256113 Set Vref, RX VrefLevel [Byte0]: 64
8727 18:01:21.259690 [Byte1]: 64
8728 18:01:21.263847
8729 18:01:21.263958 Set Vref, RX VrefLevel [Byte0]: 65
8730 18:01:21.266971 [Byte1]: 65
8731 18:01:21.271207
8732 18:01:21.271333 Set Vref, RX VrefLevel [Byte0]: 66
8733 18:01:21.274721 [Byte1]: 66
8734 18:01:21.278869
8735 18:01:21.278980 Set Vref, RX VrefLevel [Byte0]: 67
8736 18:01:21.281909 [Byte1]: 67
8737 18:01:21.286805
8738 18:01:21.286906 Set Vref, RX VrefLevel [Byte0]: 68
8739 18:01:21.289788 [Byte1]: 68
8740 18:01:21.293962
8741 18:01:21.294038 Set Vref, RX VrefLevel [Byte0]: 69
8742 18:01:21.297357 [Byte1]: 69
8743 18:01:21.302099
8744 18:01:21.302200 Set Vref, RX VrefLevel [Byte0]: 70
8745 18:01:21.304749 [Byte1]: 70
8746 18:01:21.309477
8747 18:01:21.309565 Set Vref, RX VrefLevel [Byte0]: 71
8748 18:01:21.312431 [Byte1]: 71
8749 18:01:21.316764
8750 18:01:21.316865 Set Vref, RX VrefLevel [Byte0]: 72
8751 18:01:21.319894 [Byte1]: 72
8752 18:01:21.324541
8753 18:01:21.324617 Set Vref, RX VrefLevel [Byte0]: 73
8754 18:01:21.327608 [Byte1]: 73
8755 18:01:21.331899
8756 18:01:21.331973 Set Vref, RX VrefLevel [Byte0]: 74
8757 18:01:21.335322 [Byte1]: 74
8758 18:01:21.339341
8759 18:01:21.339418 Final RX Vref Byte 0 = 63 to rank0
8760 18:01:21.342824 Final RX Vref Byte 1 = 59 to rank0
8761 18:01:21.345780 Final RX Vref Byte 0 = 63 to rank1
8762 18:01:21.349380 Final RX Vref Byte 1 = 59 to rank1==
8763 18:01:21.352743 Dram Type= 6, Freq= 0, CH_1, rank 0
8764 18:01:21.359354 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8765 18:01:21.359468 ==
8766 18:01:21.359572 DQS Delay:
8767 18:01:21.359663 DQS0 = 0, DQS1 = 0
8768 18:01:21.362924 DQM Delay:
8769 18:01:21.363024 DQM0 = 131, DQM1 = 124
8770 18:01:21.365993 DQ Delay:
8771 18:01:21.369663 DQ0 =136, DQ1 =126, DQ2 =120, DQ3 =128
8772 18:01:21.372826 DQ4 =130, DQ5 =142, DQ6 =142, DQ7 =126
8773 18:01:21.375868 DQ8 =110, DQ9 =112, DQ10 =126, DQ11 =118
8774 18:01:21.379438 DQ12 =134, DQ13 =132, DQ14 =130, DQ15 =132
8775 18:01:21.379538
8776 18:01:21.379626
8777 18:01:21.379722
8778 18:01:21.382944 [DramC_TX_OE_Calibration] TA2
8779 18:01:21.385913 Original DQ_B0 (3 6) =30, OEN = 27
8780 18:01:21.389487 Original DQ_B1 (3 6) =30, OEN = 27
8781 18:01:21.392551 24, 0x0, End_B0=24 End_B1=24
8782 18:01:21.392657 25, 0x0, End_B0=25 End_B1=25
8783 18:01:21.396194 26, 0x0, End_B0=26 End_B1=26
8784 18:01:21.399700 27, 0x0, End_B0=27 End_B1=27
8785 18:01:21.402415 28, 0x0, End_B0=28 End_B1=28
8786 18:01:21.402488 29, 0x0, End_B0=29 End_B1=29
8787 18:01:21.406023 30, 0x0, End_B0=30 End_B1=30
8788 18:01:21.409628 31, 0x4141, End_B0=30 End_B1=30
8789 18:01:21.412454 Byte0 end_step=30 best_step=27
8790 18:01:21.415904 Byte1 end_step=30 best_step=27
8791 18:01:21.419603 Byte0 TX OE(2T, 0.5T) = (3, 3)
8792 18:01:21.419700 Byte1 TX OE(2T, 0.5T) = (3, 3)
8793 18:01:21.422655
8794 18:01:21.422737
8795 18:01:21.429174 [DQSOSCAuto] RK0, (LSB)MR18= 0x1701, (MSB)MR19= 0x303, tDQSOscB0 = 409 ps tDQSOscB1 = 398 ps
8796 18:01:21.432807 CH1 RK0: MR19=303, MR18=1701
8797 18:01:21.439390 CH1_RK0: MR19=0x303, MR18=0x1701, DQSOSC=398, MR23=63, INC=23, DEC=15
8798 18:01:21.439509
8799 18:01:21.443054 ----->DramcWriteLeveling(PI) begin...
8800 18:01:21.443176 ==
8801 18:01:21.445930 Dram Type= 6, Freq= 0, CH_1, rank 1
8802 18:01:21.449485 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8803 18:01:21.449564 ==
8804 18:01:21.452496 Write leveling (Byte 0): 25 => 25
8805 18:01:21.456166 Write leveling (Byte 1): 28 => 28
8806 18:01:21.459092 DramcWriteLeveling(PI) end<-----
8807 18:01:21.459228
8808 18:01:21.459323 ==
8809 18:01:21.462362 Dram Type= 6, Freq= 0, CH_1, rank 1
8810 18:01:21.465844 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8811 18:01:21.465946 ==
8812 18:01:21.468960 [Gating] SW mode calibration
8813 18:01:21.476039 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8814 18:01:21.482881 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8815 18:01:21.485797 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8816 18:01:21.489291 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8817 18:01:21.495891 1 4 8 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
8818 18:01:21.499530 1 4 12 | B1->B0 | 2828 3434 | 1 1 | (0 0) (1 1)
8819 18:01:21.502581 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8820 18:01:21.508993 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8821 18:01:21.512637 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8822 18:01:21.516257 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8823 18:01:21.522565 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8824 18:01:21.525652 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8825 18:01:21.529409 1 5 8 | B1->B0 | 3434 3131 | 1 1 | (1 0) (1 0)
8826 18:01:21.535508 1 5 12 | B1->B0 | 2828 2323 | 0 0 | (1 0) (0 0)
8827 18:01:21.539397 1 5 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8828 18:01:21.542267 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8829 18:01:21.548876 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8830 18:01:21.552611 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8831 18:01:21.555553 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8832 18:01:21.559206 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8833 18:01:21.565694 1 6 8 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
8834 18:01:21.569285 1 6 12 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
8835 18:01:21.572382 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8836 18:01:21.579066 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8837 18:01:21.582522 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8838 18:01:21.585958 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8839 18:01:21.592576 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8840 18:01:21.596005 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8841 18:01:21.599513 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8842 18:01:21.606217 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8843 18:01:21.609186 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8844 18:01:21.612736 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8845 18:01:21.619030 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8846 18:01:21.622554 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8847 18:01:21.626208 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8848 18:01:21.632850 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8849 18:01:21.635864 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8850 18:01:21.639404 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8851 18:01:21.642527 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8852 18:01:21.649298 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8853 18:01:21.652776 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8854 18:01:21.655902 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8855 18:01:21.662617 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8856 18:01:21.666238 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8857 18:01:21.669351 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8858 18:01:21.676346 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8859 18:01:21.676435 Total UI for P1: 0, mck2ui 16
8860 18:01:21.683084 best dqsien dly found for B0: ( 1, 9, 6)
8861 18:01:21.685945 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8862 18:01:21.689491 Total UI for P1: 0, mck2ui 16
8863 18:01:21.692881 best dqsien dly found for B1: ( 1, 9, 10)
8864 18:01:21.695852 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8865 18:01:21.699542 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8866 18:01:21.699630
8867 18:01:21.703032 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8868 18:01:21.705877 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8869 18:01:21.709547 [Gating] SW calibration Done
8870 18:01:21.709629 ==
8871 18:01:21.713165 Dram Type= 6, Freq= 0, CH_1, rank 1
8872 18:01:21.716119 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8873 18:01:21.716201 ==
8874 18:01:21.719519 RX Vref Scan: 0
8875 18:01:21.719638
8876 18:01:21.722577 RX Vref 0 -> 0, step: 1
8877 18:01:21.722736
8878 18:01:21.722829 RX Delay 0 -> 252, step: 8
8879 18:01:21.729281 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8880 18:01:21.732774 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8881 18:01:21.736329 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8882 18:01:21.739238 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8883 18:01:21.742949 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8884 18:01:21.749557 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8885 18:01:21.752574 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8886 18:01:21.756077 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8887 18:01:21.759182 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8888 18:01:21.762759 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8889 18:01:21.769591 iDelay=200, Bit 10, Center 135 (80 ~ 191) 112
8890 18:01:21.772535 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8891 18:01:21.776080 iDelay=200, Bit 12, Center 139 (80 ~ 199) 120
8892 18:01:21.779279 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8893 18:01:21.782894 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120
8894 18:01:21.789662 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8895 18:01:21.789745 ==
8896 18:01:21.792662 Dram Type= 6, Freq= 0, CH_1, rank 1
8897 18:01:21.796062 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8898 18:01:21.796148 ==
8899 18:01:21.796214 DQS Delay:
8900 18:01:21.799623 DQS0 = 0, DQS1 = 0
8901 18:01:21.799705 DQM Delay:
8902 18:01:21.803060 DQM0 = 132, DQM1 = 129
8903 18:01:21.803142 DQ Delay:
8904 18:01:21.806052 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =135
8905 18:01:21.809348 DQ4 =131, DQ5 =147, DQ6 =139, DQ7 =127
8906 18:01:21.812986 DQ8 =115, DQ9 =115, DQ10 =135, DQ11 =123
8907 18:01:21.816109 DQ12 =139, DQ13 =135, DQ14 =139, DQ15 =135
8908 18:01:21.816191
8909 18:01:21.816256
8910 18:01:21.819765 ==
8911 18:01:21.819847 Dram Type= 6, Freq= 0, CH_1, rank 1
8912 18:01:21.826324 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8913 18:01:21.826406 ==
8914 18:01:21.826471
8915 18:01:21.826531
8916 18:01:21.829229 TX Vref Scan disable
8917 18:01:21.829356 == TX Byte 0 ==
8918 18:01:21.832724 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8919 18:01:21.839294 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8920 18:01:21.839376 == TX Byte 1 ==
8921 18:01:21.842967 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8922 18:01:21.849695 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8923 18:01:21.849777 ==
8924 18:01:21.852742 Dram Type= 6, Freq= 0, CH_1, rank 1
8925 18:01:21.856289 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8926 18:01:21.856371 ==
8927 18:01:21.869961
8928 18:01:21.873556 TX Vref early break, caculate TX vref
8929 18:01:21.876611 TX Vref=16, minBit 8, minWin=22, winSum=376
8930 18:01:21.880147 TX Vref=18, minBit 8, minWin=23, winSum=388
8931 18:01:21.883162 TX Vref=20, minBit 8, minWin=23, winSum=396
8932 18:01:21.886887 TX Vref=22, minBit 5, minWin=24, winSum=402
8933 18:01:21.890255 TX Vref=24, minBit 8, minWin=24, winSum=412
8934 18:01:21.896957 TX Vref=26, minBit 6, minWin=25, winSum=416
8935 18:01:21.899902 TX Vref=28, minBit 1, minWin=26, winSum=423
8936 18:01:21.903365 TX Vref=30, minBit 0, minWin=25, winSum=419
8937 18:01:21.906889 TX Vref=32, minBit 0, minWin=25, winSum=412
8938 18:01:21.909922 TX Vref=34, minBit 8, minWin=24, winSum=402
8939 18:01:21.913395 TX Vref=36, minBit 0, minWin=24, winSum=396
8940 18:01:21.920040 [TxChooseVref] Worse bit 1, Min win 26, Win sum 423, Final Vref 28
8941 18:01:21.920122
8942 18:01:21.923560 Final TX Range 0 Vref 28
8943 18:01:21.923642
8944 18:01:21.923706 ==
8945 18:01:21.926481 Dram Type= 6, Freq= 0, CH_1, rank 1
8946 18:01:21.930217 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8947 18:01:21.930299 ==
8948 18:01:21.930363
8949 18:01:21.930423
8950 18:01:21.933188 TX Vref Scan disable
8951 18:01:21.939650 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8952 18:01:21.939733 == TX Byte 0 ==
8953 18:01:21.942988 u2DelayCellOfst[0]=14 cells (4 PI)
8954 18:01:21.946276 u2DelayCellOfst[1]=14 cells (4 PI)
8955 18:01:21.949775 u2DelayCellOfst[2]=0 cells (0 PI)
8956 18:01:21.953502 u2DelayCellOfst[3]=7 cells (2 PI)
8957 18:01:21.956374 u2DelayCellOfst[4]=10 cells (3 PI)
8958 18:01:21.960040 u2DelayCellOfst[5]=21 cells (6 PI)
8959 18:01:21.963677 u2DelayCellOfst[6]=17 cells (5 PI)
8960 18:01:21.966509 u2DelayCellOfst[7]=7 cells (2 PI)
8961 18:01:21.969979 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8962 18:01:21.973676 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8963 18:01:21.976645 == TX Byte 1 ==
8964 18:01:21.976743 u2DelayCellOfst[8]=0 cells (0 PI)
8965 18:01:21.979747 u2DelayCellOfst[9]=7 cells (2 PI)
8966 18:01:21.983160 u2DelayCellOfst[10]=10 cells (3 PI)
8967 18:01:21.986787 u2DelayCellOfst[11]=7 cells (2 PI)
8968 18:01:21.989899 u2DelayCellOfst[12]=14 cells (4 PI)
8969 18:01:21.993723 u2DelayCellOfst[13]=14 cells (4 PI)
8970 18:01:21.996641 u2DelayCellOfst[14]=17 cells (5 PI)
8971 18:01:22.000229 u2DelayCellOfst[15]=17 cells (5 PI)
8972 18:01:22.003209 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8973 18:01:22.010254 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8974 18:01:22.010339 DramC Write-DBI on
8975 18:01:22.010425 ==
8976 18:01:22.013300 Dram Type= 6, Freq= 0, CH_1, rank 1
8977 18:01:22.017065 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8978 18:01:22.017150 ==
8979 18:01:22.020016
8980 18:01:22.020100
8981 18:01:22.020213 TX Vref Scan disable
8982 18:01:22.023464 == TX Byte 0 ==
8983 18:01:22.026498 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8984 18:01:22.030128 == TX Byte 1 ==
8985 18:01:22.033115 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8986 18:01:22.033200 DramC Write-DBI off
8987 18:01:22.036811
8988 18:01:22.036919 [DATLAT]
8989 18:01:22.037049 Freq=1600, CH1 RK1
8990 18:01:22.037130
8991 18:01:22.039779 DATLAT Default: 0xf
8992 18:01:22.039863 0, 0xFFFF, sum = 0
8993 18:01:22.043375 1, 0xFFFF, sum = 0
8994 18:01:22.043461 2, 0xFFFF, sum = 0
8995 18:01:22.046421 3, 0xFFFF, sum = 0
8996 18:01:22.046507 4, 0xFFFF, sum = 0
8997 18:01:22.049707 5, 0xFFFF, sum = 0
8998 18:01:22.053162 6, 0xFFFF, sum = 0
8999 18:01:22.053245 7, 0xFFFF, sum = 0
9000 18:01:22.056359 8, 0xFFFF, sum = 0
9001 18:01:22.056442 9, 0xFFFF, sum = 0
9002 18:01:22.059904 10, 0xFFFF, sum = 0
9003 18:01:22.059987 11, 0xFFFF, sum = 0
9004 18:01:22.063454 12, 0xFFFF, sum = 0
9005 18:01:22.063541 13, 0xFFFF, sum = 0
9006 18:01:22.066497 14, 0x0, sum = 1
9007 18:01:22.066597 15, 0x0, sum = 2
9008 18:01:22.070110 16, 0x0, sum = 3
9009 18:01:22.070196 17, 0x0, sum = 4
9010 18:01:22.073003 best_step = 15
9011 18:01:22.073101
9012 18:01:22.073186 ==
9013 18:01:22.076631 Dram Type= 6, Freq= 0, CH_1, rank 1
9014 18:01:22.080293 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9015 18:01:22.080378 ==
9016 18:01:22.080464 RX Vref Scan: 0
9017 18:01:22.080545
9018 18:01:22.083237 RX Vref 0 -> 0, step: 1
9019 18:01:22.083322
9020 18:01:22.086834 RX Delay 11 -> 252, step: 4
9021 18:01:22.089858 iDelay=191, Bit 0, Center 134 (83 ~ 186) 104
9022 18:01:22.093386 iDelay=191, Bit 1, Center 124 (71 ~ 178) 108
9023 18:01:22.100132 iDelay=191, Bit 2, Center 118 (67 ~ 170) 104
9024 18:01:22.103599 iDelay=191, Bit 3, Center 128 (75 ~ 182) 108
9025 18:01:22.106548 iDelay=191, Bit 4, Center 130 (79 ~ 182) 104
9026 18:01:22.110117 iDelay=191, Bit 5, Center 142 (95 ~ 190) 96
9027 18:01:22.113746 iDelay=191, Bit 6, Center 138 (87 ~ 190) 104
9028 18:01:22.120098 iDelay=191, Bit 7, Center 124 (75 ~ 174) 100
9029 18:01:22.123689 iDelay=191, Bit 8, Center 114 (59 ~ 170) 112
9030 18:01:22.127061 iDelay=191, Bit 9, Center 112 (59 ~ 166) 108
9031 18:01:22.129935 iDelay=191, Bit 10, Center 128 (75 ~ 182) 108
9032 18:01:22.133631 iDelay=191, Bit 11, Center 118 (63 ~ 174) 112
9033 18:01:22.140321 iDelay=191, Bit 12, Center 134 (83 ~ 186) 104
9034 18:01:22.143462 iDelay=191, Bit 13, Center 134 (83 ~ 186) 104
9035 18:01:22.146549 iDelay=191, Bit 14, Center 134 (79 ~ 190) 112
9036 18:01:22.150124 iDelay=191, Bit 15, Center 136 (83 ~ 190) 108
9037 18:01:22.150216 ==
9038 18:01:22.153750 Dram Type= 6, Freq= 0, CH_1, rank 1
9039 18:01:22.160232 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9040 18:01:22.160310 ==
9041 18:01:22.160378 DQS Delay:
9042 18:01:22.160437 DQS0 = 0, DQS1 = 0
9043 18:01:22.163454 DQM Delay:
9044 18:01:22.163547 DQM0 = 129, DQM1 = 126
9045 18:01:22.166916 DQ Delay:
9046 18:01:22.170189 DQ0 =134, DQ1 =124, DQ2 =118, DQ3 =128
9047 18:01:22.173550 DQ4 =130, DQ5 =142, DQ6 =138, DQ7 =124
9048 18:01:22.176895 DQ8 =114, DQ9 =112, DQ10 =128, DQ11 =118
9049 18:01:22.180010 DQ12 =134, DQ13 =134, DQ14 =134, DQ15 =136
9050 18:01:22.180084
9051 18:01:22.180146
9052 18:01:22.180208
9053 18:01:22.183705 [DramC_TX_OE_Calibration] TA2
9054 18:01:22.186829 Original DQ_B0 (3 6) =30, OEN = 27
9055 18:01:22.190391 Original DQ_B1 (3 6) =30, OEN = 27
9056 18:01:22.193308 24, 0x0, End_B0=24 End_B1=24
9057 18:01:22.193395 25, 0x0, End_B0=25 End_B1=25
9058 18:01:22.196912 26, 0x0, End_B0=26 End_B1=26
9059 18:01:22.200035 27, 0x0, End_B0=27 End_B1=27
9060 18:01:22.203636 28, 0x0, End_B0=28 End_B1=28
9061 18:01:22.203722 29, 0x0, End_B0=29 End_B1=29
9062 18:01:22.207096 30, 0x0, End_B0=30 End_B1=30
9063 18:01:22.210170 31, 0x5151, End_B0=30 End_B1=30
9064 18:01:22.213144 Byte0 end_step=30 best_step=27
9065 18:01:22.216749 Byte1 end_step=30 best_step=27
9066 18:01:22.220215 Byte0 TX OE(2T, 0.5T) = (3, 3)
9067 18:01:22.220305 Byte1 TX OE(2T, 0.5T) = (3, 3)
9068 18:01:22.223300
9069 18:01:22.223413
9070 18:01:22.230012 [DQSOSCAuto] RK1, (LSB)MR18= 0x1016, (MSB)MR19= 0x303, tDQSOscB0 = 398 ps tDQSOscB1 = 401 ps
9071 18:01:22.233602 CH1 RK1: MR19=303, MR18=1016
9072 18:01:22.239838 CH1_RK1: MR19=0x303, MR18=0x1016, DQSOSC=398, MR23=63, INC=23, DEC=15
9073 18:01:22.243340 [RxdqsGatingPostProcess] freq 1600
9074 18:01:22.246492 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9075 18:01:22.250114 best DQS0 dly(2T, 0.5T) = (1, 1)
9076 18:01:22.253256 best DQS1 dly(2T, 0.5T) = (1, 1)
9077 18:01:22.256868 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9078 18:01:22.259991 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9079 18:01:22.263006 best DQS0 dly(2T, 0.5T) = (1, 1)
9080 18:01:22.266611 best DQS1 dly(2T, 0.5T) = (1, 1)
9081 18:01:22.270150 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9082 18:01:22.273138 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9083 18:01:22.276696 Pre-setting of DQS Precalculation
9084 18:01:22.279783 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9085 18:01:22.286803 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9086 18:01:22.293203 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9087 18:01:22.293290
9088 18:01:22.293376
9089 18:01:22.296477 [Calibration Summary] 3200 Mbps
9090 18:01:22.300056 CH 0, Rank 0
9091 18:01:22.300192 SW Impedance : PASS
9092 18:01:22.303019 DUTY Scan : NO K
9093 18:01:22.306720 ZQ Calibration : PASS
9094 18:01:22.306802 Jitter Meter : NO K
9095 18:01:22.309808 CBT Training : PASS
9096 18:01:22.313353 Write leveling : PASS
9097 18:01:22.313435 RX DQS gating : PASS
9098 18:01:22.316463 RX DQ/DQS(RDDQC) : PASS
9099 18:01:22.320005 TX DQ/DQS : PASS
9100 18:01:22.320088 RX DATLAT : PASS
9101 18:01:22.322906 RX DQ/DQS(Engine): PASS
9102 18:01:22.322995 TX OE : PASS
9103 18:01:22.326478 All Pass.
9104 18:01:22.326559
9105 18:01:22.326664 CH 0, Rank 1
9106 18:01:22.329964 SW Impedance : PASS
9107 18:01:22.330046 DUTY Scan : NO K
9108 18:01:22.333038 ZQ Calibration : PASS
9109 18:01:22.336654 Jitter Meter : NO K
9110 18:01:22.336735 CBT Training : PASS
9111 18:01:22.339635 Write leveling : PASS
9112 18:01:22.343176 RX DQS gating : PASS
9113 18:01:22.343258 RX DQ/DQS(RDDQC) : PASS
9114 18:01:22.346806 TX DQ/DQS : PASS
9115 18:01:22.349645 RX DATLAT : PASS
9116 18:01:22.349727 RX DQ/DQS(Engine): PASS
9117 18:01:22.353171 TX OE : PASS
9118 18:01:22.353253 All Pass.
9119 18:01:22.353317
9120 18:01:22.356154 CH 1, Rank 0
9121 18:01:22.356235 SW Impedance : PASS
9122 18:01:22.359742 DUTY Scan : NO K
9123 18:01:22.363428 ZQ Calibration : PASS
9124 18:01:22.363510 Jitter Meter : NO K
9125 18:01:22.366487 CBT Training : PASS
9126 18:01:22.366569 Write leveling : PASS
9127 18:01:22.369945 RX DQS gating : PASS
9128 18:01:22.373383 RX DQ/DQS(RDDQC) : PASS
9129 18:01:22.373465 TX DQ/DQS : PASS
9130 18:01:22.377269 RX DATLAT : PASS
9131 18:01:22.379952 RX DQ/DQS(Engine): PASS
9132 18:01:22.380033 TX OE : PASS
9133 18:01:22.382999 All Pass.
9134 18:01:22.383081
9135 18:01:22.383145 CH 1, Rank 1
9136 18:01:22.386554 SW Impedance : PASS
9137 18:01:22.386635 DUTY Scan : NO K
9138 18:01:22.389588 ZQ Calibration : PASS
9139 18:01:22.393455 Jitter Meter : NO K
9140 18:01:22.393538 CBT Training : PASS
9141 18:01:22.396415 Write leveling : PASS
9142 18:01:22.399672 RX DQS gating : PASS
9143 18:01:22.399754 RX DQ/DQS(RDDQC) : PASS
9144 18:01:22.402924 TX DQ/DQS : PASS
9145 18:01:22.403006 RX DATLAT : PASS
9146 18:01:22.406580 RX DQ/DQS(Engine): PASS
9147 18:01:22.409797 TX OE : PASS
9148 18:01:22.409879 All Pass.
9149 18:01:22.409943
9150 18:01:22.413301 DramC Write-DBI on
9151 18:01:22.413383 PER_BANK_REFRESH: Hybrid Mode
9152 18:01:22.416537 TX_TRACKING: ON
9153 18:01:22.426429 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9154 18:01:22.433386 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9155 18:01:22.440026 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9156 18:01:22.442990 [FAST_K] Save calibration result to emmc
9157 18:01:22.446603 sync common calibartion params.
9158 18:01:22.449589 sync cbt_mode0:1, 1:1
9159 18:01:22.449672 dram_init: ddr_geometry: 2
9160 18:01:22.453242 dram_init: ddr_geometry: 2
9161 18:01:22.456708 dram_init: ddr_geometry: 2
9162 18:01:22.459654 0:dram_rank_size:100000000
9163 18:01:22.459739 1:dram_rank_size:100000000
9164 18:01:22.466327 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9165 18:01:22.470118 DFS_SHUFFLE_HW_MODE: ON
9166 18:01:22.473002 dramc_set_vcore_voltage set vcore to 725000
9167 18:01:22.473098 Read voltage for 1600, 0
9168 18:01:22.476464 Vio18 = 0
9169 18:01:22.476561 Vcore = 725000
9170 18:01:22.476639 Vdram = 0
9171 18:01:22.480064 Vddq = 0
9172 18:01:22.480162 Vmddr = 0
9173 18:01:22.483192 switch to 3200 Mbps bootup
9174 18:01:22.483273 [DramcRunTimeConfig]
9175 18:01:22.483338 PHYPLL
9176 18:01:22.489547 DPM_CONTROL_AFTERK: ON
9177 18:01:22.489923 PER_BANK_REFRESH: ON
9178 18:01:22.490004 REFRESH_OVERHEAD_REDUCTION: ON
9179 18:01:22.493576 CMD_PICG_NEW_MODE: OFF
9180 18:01:22.496495 XRTWTW_NEW_MODE: ON
9181 18:01:22.496586 XRTRTR_NEW_MODE: ON
9182 18:01:22.500139 TX_TRACKING: ON
9183 18:01:22.500221 RDSEL_TRACKING: OFF
9184 18:01:22.503232 DQS Precalculation for DVFS: ON
9185 18:01:22.503314 RX_TRACKING: OFF
9186 18:01:22.506754 HW_GATING DBG: ON
9187 18:01:22.509686 ZQCS_ENABLE_LP4: ON
9188 18:01:22.509768 RX_PICG_NEW_MODE: ON
9189 18:01:22.513125 TX_PICG_NEW_MODE: ON
9190 18:01:22.513208 ENABLE_RX_DCM_DPHY: ON
9191 18:01:22.516498 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9192 18:01:22.519924 DUMMY_READ_FOR_TRACKING: OFF
9193 18:01:22.523409 !!! SPM_CONTROL_AFTERK: OFF
9194 18:01:22.526732 !!! SPM could not control APHY
9195 18:01:22.526818 IMPEDANCE_TRACKING: ON
9196 18:01:22.530286 TEMP_SENSOR: ON
9197 18:01:22.530368 HW_SAVE_FOR_SR: OFF
9198 18:01:22.533379 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9199 18:01:22.536337 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9200 18:01:22.539750 Read ODT Tracking: ON
9201 18:01:22.539833 Refresh Rate DeBounce: ON
9202 18:01:22.543279 DFS_NO_QUEUE_FLUSH: ON
9203 18:01:22.546338 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9204 18:01:22.550044 ENABLE_DFS_RUNTIME_MRW: OFF
9205 18:01:22.550126 DDR_RESERVE_NEW_MODE: ON
9206 18:01:22.553152 MR_CBT_SWITCH_FREQ: ON
9207 18:01:22.556249 =========================
9208 18:01:22.574731 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9209 18:01:22.577751 dram_init: ddr_geometry: 2
9210 18:01:22.596296 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9211 18:01:22.599853 dram_init: dram init end (result: 0)
9212 18:01:22.606518 DRAM-K: Full calibration passed in 24578 msecs
9213 18:01:22.609456 MRC: failed to locate region type 0.
9214 18:01:22.609538 DRAM rank0 size:0x100000000,
9215 18:01:22.613250 DRAM rank1 size=0x100000000
9216 18:01:22.623041 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9217 18:01:22.629588 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9218 18:01:22.636487 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9219 18:01:22.642914 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9220 18:01:22.646399 DRAM rank0 size:0x100000000,
9221 18:01:22.649500 DRAM rank1 size=0x100000000
9222 18:01:22.649587 CBMEM:
9223 18:01:22.653076 IMD: root @ 0xfffff000 254 entries.
9224 18:01:22.656204 IMD: root @ 0xffffec00 62 entries.
9225 18:01:22.659762 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9226 18:01:22.662750 WARNING: RO_VPD is uninitialized or empty.
9227 18:01:22.669217 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9228 18:01:22.676387 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9229 18:01:22.688774 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9230 18:01:22.700249 BS: romstage times (exec / console): total (unknown) / 24080 ms
9231 18:01:22.700334
9232 18:01:22.700399
9233 18:01:22.710150 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9234 18:01:22.713622 ARM64: Exception handlers installed.
9235 18:01:22.717256 ARM64: Testing exception
9236 18:01:22.720273 ARM64: Done test exception
9237 18:01:22.720382 Enumerating buses...
9238 18:01:22.723914 Show all devs... Before device enumeration.
9239 18:01:22.727335 Root Device: enabled 1
9240 18:01:22.730259 CPU_CLUSTER: 0: enabled 1
9241 18:01:22.730344 CPU: 00: enabled 1
9242 18:01:22.733652 Compare with tree...
9243 18:01:22.733741 Root Device: enabled 1
9244 18:01:22.737113 CPU_CLUSTER: 0: enabled 1
9245 18:01:22.740700 CPU: 00: enabled 1
9246 18:01:22.740782 Root Device scanning...
9247 18:01:22.744232 scan_static_bus for Root Device
9248 18:01:22.747146 CPU_CLUSTER: 0 enabled
9249 18:01:22.750545 scan_static_bus for Root Device done
9250 18:01:22.754008 scan_bus: bus Root Device finished in 8 msecs
9251 18:01:22.754118 done
9252 18:01:22.760723 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9253 18:01:22.763731 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9254 18:01:22.770362 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9255 18:01:22.773875 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9256 18:01:22.777435 Allocating resources...
9257 18:01:22.777525 Reading resources...
9258 18:01:22.783923 Root Device read_resources bus 0 link: 0
9259 18:01:22.784032 DRAM rank0 size:0x100000000,
9260 18:01:22.786952 DRAM rank1 size=0x100000000
9261 18:01:22.790446 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9262 18:01:22.793980 CPU: 00 missing read_resources
9263 18:01:22.797091 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9264 18:01:22.803699 Root Device read_resources bus 0 link: 0 done
9265 18:01:22.803785 Done reading resources.
9266 18:01:22.810258 Show resources in subtree (Root Device)...After reading.
9267 18:01:22.814024 Root Device child on link 0 CPU_CLUSTER: 0
9268 18:01:22.817011 CPU_CLUSTER: 0 child on link 0 CPU: 00
9269 18:01:22.826950 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9270 18:01:22.827104 CPU: 00
9271 18:01:22.830770 Root Device assign_resources, bus 0 link: 0
9272 18:01:22.834003 CPU_CLUSTER: 0 missing set_resources
9273 18:01:22.836911 Root Device assign_resources, bus 0 link: 0 done
9274 18:01:22.840520 Done setting resources.
9275 18:01:22.847266 Show resources in subtree (Root Device)...After assigning values.
9276 18:01:22.850749 Root Device child on link 0 CPU_CLUSTER: 0
9277 18:01:22.853876 CPU_CLUSTER: 0 child on link 0 CPU: 00
9278 18:01:22.863818 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9279 18:01:22.863910 CPU: 00
9280 18:01:22.866870 Done allocating resources.
9281 18:01:22.870585 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9282 18:01:22.873497 Enabling resources...
9283 18:01:22.873608 done.
9284 18:01:22.877233 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9285 18:01:22.880687 Initializing devices...
9286 18:01:22.883628 Root Device init
9287 18:01:22.883736 init hardware done!
9288 18:01:22.887262 0x00000018: ctrlr->caps
9289 18:01:22.887349 52.000 MHz: ctrlr->f_max
9290 18:01:22.890405 0.400 MHz: ctrlr->f_min
9291 18:01:22.893829 0x40ff8080: ctrlr->voltages
9292 18:01:22.893916 sclk: 390625
9293 18:01:22.897329 Bus Width = 1
9294 18:01:22.897414 sclk: 390625
9295 18:01:22.897499 Bus Width = 1
9296 18:01:22.900354 Early init status = 3
9297 18:01:22.904054 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9298 18:01:22.908863 in-header: 03 fc 00 00 01 00 00 00
9299 18:01:22.912434 in-data: 00
9300 18:01:22.915501 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9301 18:01:22.921014 in-header: 03 fd 00 00 00 00 00 00
9302 18:01:22.924595 in-data:
9303 18:01:22.927821 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9304 18:01:22.932070 in-header: 03 fc 00 00 01 00 00 00
9305 18:01:22.935590 in-data: 00
9306 18:01:22.939025 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9307 18:01:22.944639 in-header: 03 fd 00 00 00 00 00 00
9308 18:01:22.948017 in-data:
9309 18:01:22.951448 [SSUSB] Setting up USB HOST controller...
9310 18:01:22.954300 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9311 18:01:22.957902 [SSUSB] phy power-on done.
9312 18:01:22.960869 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9313 18:01:22.967908 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9314 18:01:22.971440 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9315 18:01:22.978292 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9316 18:01:22.984848 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9317 18:01:22.991288 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9318 18:01:22.997944 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9319 18:01:23.004362 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9320 18:01:23.004447 SPM: binary array size = 0x9dc
9321 18:01:23.011025 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9322 18:01:23.018199 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9323 18:01:23.024895 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9324 18:01:23.027690 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9325 18:01:23.031278 configure_display: Starting display init
9326 18:01:23.068067 anx7625_power_on_init: Init interface.
9327 18:01:23.070885 anx7625_disable_pd_protocol: Disabled PD feature.
9328 18:01:23.074362 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9329 18:01:23.102047 anx7625_start_dp_work: Secure OCM version=00
9330 18:01:23.105541 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9331 18:01:23.120427 sp_tx_get_edid_block: EDID Block = 1
9332 18:01:23.222855 Extracted contents:
9333 18:01:23.225890 header: 00 ff ff ff ff ff ff 00
9334 18:01:23.229564 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9335 18:01:23.232617 version: 01 04
9336 18:01:23.236215 basic params: 95 1f 11 78 0a
9337 18:01:23.239136 chroma info: 76 90 94 55 54 90 27 21 50 54
9338 18:01:23.242854 established: 00 00 00
9339 18:01:23.249468 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9340 18:01:23.252947 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9341 18:01:23.259529 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9342 18:01:23.265664 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9343 18:01:23.272571 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9344 18:01:23.276078 extensions: 00
9345 18:01:23.276164 checksum: fb
9346 18:01:23.276249
9347 18:01:23.279165 Manufacturer: IVO Model 57d Serial Number 0
9348 18:01:23.282156 Made week 0 of 2020
9349 18:01:23.282241 EDID version: 1.4
9350 18:01:23.285645 Digital display
9351 18:01:23.288914 6 bits per primary color channel
9352 18:01:23.289033 DisplayPort interface
9353 18:01:23.292616 Maximum image size: 31 cm x 17 cm
9354 18:01:23.295882 Gamma: 220%
9355 18:01:23.295968 Check DPMS levels
9356 18:01:23.299033 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9357 18:01:23.302141 First detailed timing is preferred timing
9358 18:01:23.305851 Established timings supported:
9359 18:01:23.308820 Standard timings supported:
9360 18:01:23.312495 Detailed timings
9361 18:01:23.315413 Hex of detail: 383680a07038204018303c0035ae10000019
9362 18:01:23.318883 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9363 18:01:23.325360 0780 0798 07c8 0820 hborder 0
9364 18:01:23.328933 0438 043b 0447 0458 vborder 0
9365 18:01:23.332490 -hsync -vsync
9366 18:01:23.332579 Did detailed timing
9367 18:01:23.339133 Hex of detail: 000000000000000000000000000000000000
9368 18:01:23.339219 Manufacturer-specified data, tag 0
9369 18:01:23.346087 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9370 18:01:23.348897 ASCII string: InfoVision
9371 18:01:23.351949 Hex of detail: 000000fe00523134304e574635205248200a
9372 18:01:23.355557 ASCII string: R140NWF5 RH
9373 18:01:23.355694 Checksum
9374 18:01:23.358570 Checksum: 0xfb (valid)
9375 18:01:23.362302 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9376 18:01:23.365317 DSI data_rate: 832800000 bps
9377 18:01:23.371989 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9378 18:01:23.375504 anx7625_parse_edid: pixelclock(138800).
9379 18:01:23.378468 hactive(1920), hsync(48), hfp(24), hbp(88)
9380 18:01:23.381823 vactive(1080), vsync(12), vfp(3), vbp(17)
9381 18:01:23.385206 anx7625_dsi_config: config dsi.
9382 18:01:23.391861 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9383 18:01:23.404645 anx7625_dsi_config: success to config DSI
9384 18:01:23.408457 anx7625_dp_start: MIPI phy setup OK.
9385 18:01:23.411387 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9386 18:01:23.415035 mtk_ddp_mode_set invalid vrefresh 60
9387 18:01:23.418136 main_disp_path_setup
9388 18:01:23.418245 ovl_layer_smi_id_en
9389 18:01:23.421239 ovl_layer_smi_id_en
9390 18:01:23.421323 ccorr_config
9391 18:01:23.421408 aal_config
9392 18:01:23.424925 gamma_config
9393 18:01:23.425100 postmask_config
9394 18:01:23.427852 dither_config
9395 18:01:23.431467 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9396 18:01:23.438254 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9397 18:01:23.441167 Root Device init finished in 555 msecs
9398 18:01:23.445207 CPU_CLUSTER: 0 init
9399 18:01:23.451040 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9400 18:01:23.454704 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9401 18:01:23.458182 APU_MBOX 0x190000b0 = 0x10001
9402 18:01:23.461100 APU_MBOX 0x190001b0 = 0x10001
9403 18:01:23.464646 APU_MBOX 0x190005b0 = 0x10001
9404 18:01:23.467677 APU_MBOX 0x190006b0 = 0x10001
9405 18:01:23.471244 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9406 18:01:23.483917 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9407 18:01:23.496219 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9408 18:01:23.502939 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9409 18:01:23.514323 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9410 18:01:23.523563 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9411 18:01:23.527211 CPU_CLUSTER: 0 init finished in 81 msecs
9412 18:01:23.530214 Devices initialized
9413 18:01:23.533857 Show all devs... After init.
9414 18:01:23.533941 Root Device: enabled 1
9415 18:01:23.536793 CPU_CLUSTER: 0: enabled 1
9416 18:01:23.540484 CPU: 00: enabled 1
9417 18:01:23.543468 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9418 18:01:23.546934 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9419 18:01:23.549931 ELOG: NV offset 0x57f000 size 0x1000
9420 18:01:23.556634 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9421 18:01:23.563374 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9422 18:01:23.566798 ELOG: Event(17) added with size 13 at 2024-06-11 18:01:22 UTC
9423 18:01:23.570075 out: cmd=0x121: 03 db 21 01 00 00 00 00
9424 18:01:23.574130 in-header: 03 dc 00 00 2c 00 00 00
9425 18:01:23.587765 in-data: 82 69 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9426 18:01:23.594258 ELOG: Event(A1) added with size 10 at 2024-06-11 18:01:22 UTC
9427 18:01:23.600702 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9428 18:01:23.607850 ELOG: Event(A0) added with size 9 at 2024-06-11 18:01:22 UTC
9429 18:01:23.610864 elog_add_boot_reason: Logged dev mode boot
9430 18:01:23.614022 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9431 18:01:23.617533 Finalize devices...
9432 18:01:23.617640 Devices finalized
9433 18:01:23.624052 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9434 18:01:23.627495 Writing coreboot table at 0xffe64000
9435 18:01:23.630893 0. 000000000010a000-0000000000113fff: RAMSTAGE
9436 18:01:23.633882 1. 0000000040000000-00000000400fffff: RAM
9437 18:01:23.637523 2. 0000000040100000-000000004032afff: RAMSTAGE
9438 18:01:23.644171 3. 000000004032b000-00000000545fffff: RAM
9439 18:01:23.647871 4. 0000000054600000-000000005465ffff: BL31
9440 18:01:23.650957 5. 0000000054660000-00000000ffe63fff: RAM
9441 18:01:23.653913 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9442 18:01:23.660602 7. 0000000100000000-000000023fffffff: RAM
9443 18:01:23.660729 Passing 5 GPIOs to payload:
9444 18:01:23.667673 NAME | PORT | POLARITY | VALUE
9445 18:01:23.670701 EC in RW | 0x000000aa | low | undefined
9446 18:01:23.677272 EC interrupt | 0x00000005 | low | undefined
9447 18:01:23.680809 TPM interrupt | 0x000000ab | high | undefined
9448 18:01:23.683973 SD card detect | 0x00000011 | high | undefined
9449 18:01:23.690551 speaker enable | 0x00000093 | high | undefined
9450 18:01:23.694283 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9451 18:01:23.697065 in-header: 03 f9 00 00 02 00 00 00
9452 18:01:23.697148 in-data: 02 00
9453 18:01:23.700740 ADC[4]: Raw value=899483 ID=7
9454 18:01:23.704297 ADC[3]: Raw value=213336 ID=1
9455 18:01:23.704380 RAM Code: 0x71
9456 18:01:23.707066 ADC[6]: Raw value=74926 ID=0
9457 18:01:23.710520 ADC[5]: Raw value=212229 ID=1
9458 18:01:23.710602 SKU Code: 0x1
9459 18:01:23.717125 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 738d
9460 18:01:23.720214 coreboot table: 964 bytes.
9461 18:01:23.723926 IMD ROOT 0. 0xfffff000 0x00001000
9462 18:01:23.727117 IMD SMALL 1. 0xffffe000 0x00001000
9463 18:01:23.730878 RO MCACHE 2. 0xffffc000 0x00001104
9464 18:01:23.733579 CONSOLE 3. 0xfff7c000 0x00080000
9465 18:01:23.737122 FMAP 4. 0xfff7b000 0x00000452
9466 18:01:23.740618 TIME STAMP 5. 0xfff7a000 0x00000910
9467 18:01:23.743662 VBOOT WORK 6. 0xfff66000 0x00014000
9468 18:01:23.747220 RAMOOPS 7. 0xffe66000 0x00100000
9469 18:01:23.750240 COREBOOT 8. 0xffe64000 0x00002000
9470 18:01:23.750321 IMD small region:
9471 18:01:23.753900 IMD ROOT 0. 0xffffec00 0x00000400
9472 18:01:23.756906 VPD 1. 0xffffeb80 0x0000006c
9473 18:01:23.760446 MMC STATUS 2. 0xffffeb60 0x00000004
9474 18:01:23.767013 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9475 18:01:23.770097 Probing TPM: done!
9476 18:01:23.773820 Connected to device vid:did:rid of 1ae0:0028:00
9477 18:01:23.783526 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9478 18:01:23.787157 Initialized TPM device CR50 revision 0
9479 18:01:23.790822 Checking cr50 for pending updates
9480 18:01:23.793761 Reading cr50 TPM mode
9481 18:01:23.802548 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9482 18:01:23.809046 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9483 18:01:23.849307 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9484 18:01:23.852380 Checking segment from ROM address 0x40100000
9485 18:01:23.855487 Checking segment from ROM address 0x4010001c
9486 18:01:23.862236 Loading segment from ROM address 0x40100000
9487 18:01:23.862323 code (compression=0)
9488 18:01:23.872372 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9489 18:01:23.878998 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9490 18:01:23.879082 it's not compressed!
9491 18:01:23.885687 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9492 18:01:23.889371 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9493 18:01:23.909420 Loading segment from ROM address 0x4010001c
9494 18:01:23.909508 Entry Point 0x80000000
9495 18:01:23.912755 Loaded segments
9496 18:01:23.916234 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9497 18:01:23.922686 Jumping to boot code at 0x80000000(0xffe64000)
9498 18:01:23.929453 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9499 18:01:23.936120 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9500 18:01:23.944079 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9501 18:01:23.947092 Checking segment from ROM address 0x40100000
9502 18:01:23.950724 Checking segment from ROM address 0x4010001c
9503 18:01:23.957419 Loading segment from ROM address 0x40100000
9504 18:01:23.957502 code (compression=1)
9505 18:01:23.964034 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9506 18:01:23.974180 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9507 18:01:23.974279 using LZMA
9508 18:01:23.982444 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9509 18:01:23.989229 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9510 18:01:23.992295 Loading segment from ROM address 0x4010001c
9511 18:01:23.992382 Entry Point 0x54601000
9512 18:01:23.996009 Loaded segments
9513 18:01:23.999067 NOTICE: MT8192 bl31_setup
9514 18:01:24.005700 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9515 18:01:24.009524 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9516 18:01:24.012538 WARNING: region 0:
9517 18:01:24.016012 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9518 18:01:24.016096 WARNING: region 1:
9519 18:01:24.022478 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9520 18:01:24.025885 WARNING: region 2:
9521 18:01:24.029550 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9522 18:01:24.032552 WARNING: region 3:
9523 18:01:24.036315 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9524 18:01:24.039254 WARNING: region 4:
9525 18:01:24.042521 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9526 18:01:24.045944 WARNING: region 5:
9527 18:01:24.049181 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9528 18:01:24.052945 WARNING: region 6:
9529 18:01:24.056121 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9530 18:01:24.056224 WARNING: region 7:
9531 18:01:24.062717 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9532 18:01:24.069353 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9533 18:01:24.072967 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9534 18:01:24.076124 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9535 18:01:24.083185 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9536 18:01:24.086139 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9537 18:01:24.089228 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9538 18:01:24.095866 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9539 18:01:24.099677 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9540 18:01:24.103263 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9541 18:01:24.110069 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9542 18:01:24.113207 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9543 18:01:24.116774 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9544 18:01:24.123316 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9545 18:01:24.126184 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9546 18:01:24.133255 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9547 18:01:24.136450 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9548 18:01:24.140166 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9549 18:01:24.146799 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9550 18:01:24.149884 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9551 18:01:24.153323 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9552 18:01:24.160005 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9553 18:01:24.163237 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9554 18:01:24.169962 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9555 18:01:24.173373 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9556 18:01:24.176570 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9557 18:01:24.183146 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9558 18:01:24.186977 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9559 18:01:24.190447 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9560 18:01:24.197094 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9561 18:01:24.200077 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9562 18:01:24.206977 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9563 18:01:24.210598 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9564 18:01:24.213601 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9565 18:01:24.217193 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9566 18:01:24.223773 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9567 18:01:24.226972 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9568 18:01:24.230521 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9569 18:01:24.234147 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9570 18:01:24.240330 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9571 18:01:24.243774 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9572 18:01:24.247233 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9573 18:01:24.250190 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9574 18:01:24.257334 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9575 18:01:24.260791 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9576 18:01:24.263717 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9577 18:01:24.267375 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9578 18:01:24.273819 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9579 18:01:24.277418 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9580 18:01:24.280417 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9581 18:01:24.287413 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9582 18:01:24.290498 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9583 18:01:24.297197 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9584 18:01:24.300997 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9585 18:01:24.304133 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9586 18:01:24.310760 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9587 18:01:24.313960 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9588 18:01:24.320591 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9589 18:01:24.324295 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9590 18:01:24.327317 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9591 18:01:24.334117 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9592 18:01:24.337732 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9593 18:01:24.344536 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9594 18:01:24.347882 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9595 18:01:24.354546 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9596 18:01:24.358228 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9597 18:01:24.361238 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9598 18:01:24.367687 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9599 18:01:24.371174 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9600 18:01:24.377479 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9601 18:01:24.381204 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9602 18:01:24.387746 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9603 18:01:24.391185 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9604 18:01:24.394676 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9605 18:01:24.401373 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9606 18:01:24.404336 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9607 18:01:24.411207 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9608 18:01:24.414691 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9609 18:01:24.421562 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9610 18:01:24.424600 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9611 18:01:24.428071 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9612 18:01:24.434720 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9613 18:01:24.437792 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9614 18:01:24.444359 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9615 18:01:24.447906 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9616 18:01:24.454871 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9617 18:01:24.457794 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9618 18:01:24.461676 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9619 18:01:24.468194 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9620 18:01:24.471331 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9621 18:01:24.478234 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9622 18:01:24.481223 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9623 18:01:24.488357 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9624 18:01:24.491296 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9625 18:01:24.494790 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9626 18:01:24.501823 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9627 18:01:24.504864 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9628 18:01:24.511514 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9629 18:01:24.514938 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9630 18:01:24.518036 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9631 18:01:24.521658 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9632 18:01:24.525011 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9633 18:01:24.531791 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9634 18:01:24.534790 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9635 18:01:24.541569 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9636 18:01:24.545143 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9637 18:01:24.548162 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9638 18:01:24.555258 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9639 18:01:24.558619 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9640 18:01:24.564901 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9641 18:01:24.568265 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9642 18:01:24.571999 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9643 18:01:24.578805 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9644 18:01:24.582302 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9645 18:01:24.589125 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9646 18:01:24.592611 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9647 18:01:24.595597 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9648 18:01:24.599535 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9649 18:01:24.606389 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9650 18:01:24.608854 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9651 18:01:24.612841 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9652 18:01:24.619055 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9653 18:01:24.622558 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9654 18:01:24.625943 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9655 18:01:24.628965 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9656 18:01:24.635864 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9657 18:01:24.639159 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9658 18:01:24.645840 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9659 18:01:24.649841 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9660 18:01:24.652597 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9661 18:01:24.659649 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9662 18:01:24.662604 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9663 18:01:24.666203 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9664 18:01:24.672921 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9665 18:01:24.676272 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9666 18:01:24.682738 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9667 18:01:24.686444 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9668 18:01:24.689647 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9669 18:01:24.696485 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9670 18:01:24.700052 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9671 18:01:24.702932 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9672 18:01:24.709677 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9673 18:01:24.713076 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9674 18:01:24.719541 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9675 18:01:24.722944 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9676 18:01:24.726030 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9677 18:01:24.732649 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9678 18:01:24.736601 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9679 18:01:24.743178 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9680 18:01:24.746265 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9681 18:01:24.749972 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9682 18:01:24.756114 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9683 18:01:24.759484 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9684 18:01:24.763198 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9685 18:01:24.769757 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9686 18:01:24.773467 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9687 18:01:24.780263 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9688 18:01:24.783017 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9689 18:01:24.786406 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9690 18:01:24.793059 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9691 18:01:24.796708 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9692 18:01:24.803339 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9693 18:01:24.806172 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9694 18:01:24.809568 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9695 18:01:24.816439 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9696 18:01:24.819941 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9697 18:01:24.822722 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9698 18:01:24.829838 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9699 18:01:24.832933 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9700 18:01:24.839510 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9701 18:01:24.843258 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9702 18:01:24.846347 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9703 18:01:24.853063 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9704 18:01:24.856088 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9705 18:01:24.862942 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9706 18:01:24.866348 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9707 18:01:24.869798 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9708 18:01:24.876389 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9709 18:01:24.879838 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9710 18:01:24.883607 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9711 18:01:24.889946 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9712 18:01:24.893286 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9713 18:01:24.899651 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9714 18:01:24.903273 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9715 18:01:24.906440 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9716 18:01:24.913283 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9717 18:01:24.916345 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9718 18:01:24.919851 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9719 18:01:24.926361 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9720 18:01:24.929896 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9721 18:01:24.936307 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9722 18:01:24.939786 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9723 18:01:24.946909 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9724 18:01:24.949699 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9725 18:01:24.952754 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9726 18:01:24.959605 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9727 18:01:24.963044 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9728 18:01:24.969586 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9729 18:01:24.973322 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9730 18:01:24.976121 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9731 18:01:24.982794 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9732 18:01:24.986581 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9733 18:01:24.992955 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9734 18:01:24.995962 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9735 18:01:25.002729 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9736 18:01:25.006007 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9737 18:01:25.009608 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9738 18:01:25.016048 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9739 18:01:25.019714 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9740 18:01:25.026164 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9741 18:01:25.029442 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9742 18:01:25.033056 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9743 18:01:25.039161 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9744 18:01:25.042900 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9745 18:01:25.049512 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9746 18:01:25.052523 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9747 18:01:25.059112 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9748 18:01:25.062748 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9749 18:01:25.065899 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9750 18:01:25.072527 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9751 18:01:25.076127 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9752 18:01:25.082944 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9753 18:01:25.085851 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9754 18:01:25.089429 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9755 18:01:25.095840 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9756 18:01:25.099533 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9757 18:01:25.106217 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9758 18:01:25.109632 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9759 18:01:25.113078 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9760 18:01:25.119985 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9761 18:01:25.122935 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9762 18:01:25.125669 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9763 18:01:25.129590 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9764 18:01:25.136314 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9765 18:01:25.139194 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9766 18:01:25.142856 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9767 18:01:25.149204 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9768 18:01:25.152686 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9769 18:01:25.159261 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9770 18:01:25.162298 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9771 18:01:25.165856 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9772 18:01:25.169545 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9773 18:01:25.176148 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9774 18:01:25.179349 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9775 18:01:25.186013 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9776 18:01:25.189535 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9777 18:01:25.192524 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9778 18:01:25.199177 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9779 18:01:25.202819 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9780 18:01:25.205861 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9781 18:01:25.212332 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9782 18:01:25.216095 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9783 18:01:25.222633 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9784 18:01:25.225805 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9785 18:01:25.228897 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9786 18:01:25.236206 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9787 18:01:25.239381 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9788 18:01:25.242348 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9789 18:01:25.249046 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9790 18:01:25.252650 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9791 18:01:25.256047 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9792 18:01:25.262224 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9793 18:01:25.265677 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9794 18:01:25.272149 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9795 18:01:25.275586 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9796 18:01:25.279570 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9797 18:01:25.285956 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9798 18:01:25.289034 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9799 18:01:25.292608 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9800 18:01:25.299262 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9801 18:01:25.302318 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9802 18:01:25.305494 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9803 18:01:25.309078 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9804 18:01:25.312194 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9805 18:01:25.319250 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9806 18:01:25.322329 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9807 18:01:25.325642 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9808 18:01:25.329147 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9809 18:01:25.335636 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9810 18:01:25.338856 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9811 18:01:25.342450 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9812 18:01:25.349137 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9813 18:01:25.352621 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9814 18:01:25.355582 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9815 18:01:25.362528 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9816 18:01:25.365372 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9817 18:01:25.368910 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9818 18:01:25.375765 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9819 18:01:25.378673 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9820 18:01:25.385083 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9821 18:01:25.388864 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9822 18:01:25.392817 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9823 18:01:25.398637 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9824 18:01:25.402237 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9825 18:01:25.409022 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9826 18:01:25.412515 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9827 18:01:25.419012 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9828 18:01:25.421993 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9829 18:01:25.425270 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9830 18:01:25.431692 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9831 18:01:25.435107 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9832 18:01:25.441952 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9833 18:01:25.445364 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9834 18:01:25.449087 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9835 18:01:25.455001 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9836 18:01:25.458567 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9837 18:01:25.465360 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9838 18:01:25.468572 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9839 18:01:25.471500 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9840 18:01:25.478266 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9841 18:01:25.481339 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9842 18:01:25.488415 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9843 18:01:25.491805 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9844 18:01:25.498661 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9845 18:01:25.501569 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9846 18:01:25.505268 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9847 18:01:25.511426 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9848 18:01:25.515035 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9849 18:01:25.521754 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9850 18:01:25.524709 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9851 18:01:25.528317 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9852 18:01:25.534486 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9853 18:01:25.538441 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9854 18:01:25.544750 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9855 18:01:25.548317 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9856 18:01:25.551840 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9857 18:01:25.558505 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9858 18:01:25.561274 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9859 18:01:25.567822 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9860 18:01:25.571573 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9861 18:01:25.574871 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9862 18:01:25.581443 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9863 18:01:25.584797 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9864 18:01:25.591568 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9865 18:01:25.595007 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9866 18:01:25.598479 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9867 18:01:25.605142 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9868 18:01:25.608114 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9869 18:01:25.614815 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9870 18:01:25.618322 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9871 18:01:25.621708 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9872 18:01:25.628418 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9873 18:01:25.631427 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9874 18:01:25.637895 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9875 18:01:25.641676 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9876 18:01:25.645156 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9877 18:01:25.651732 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9878 18:01:25.655049 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9879 18:01:25.661495 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9880 18:01:25.665123 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9881 18:01:25.668329 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9882 18:01:25.674985 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9883 18:01:25.678478 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9884 18:01:25.684824 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9885 18:01:25.688311 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9886 18:01:25.691316 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9887 18:01:25.698063 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9888 18:01:25.701273 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9889 18:01:25.707884 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9890 18:01:25.711460 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9891 18:01:25.717578 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9892 18:01:25.721263 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9893 18:01:25.724220 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9894 18:01:25.731049 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9895 18:01:25.734550 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9896 18:01:25.741367 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9897 18:01:25.744379 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9898 18:01:25.751119 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9899 18:01:25.754442 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9900 18:01:25.761175 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9901 18:01:25.764230 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9902 18:01:25.767933 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9903 18:01:25.774231 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9904 18:01:25.777950 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9905 18:01:25.784616 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9906 18:01:25.787687 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9907 18:01:25.794802 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9908 18:01:25.797906 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9909 18:01:25.801607 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9910 18:01:25.808442 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9911 18:01:25.811690 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9912 18:01:25.818154 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9913 18:01:25.821725 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9914 18:01:25.824734 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9915 18:01:25.831496 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9916 18:01:25.835027 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9917 18:01:25.841640 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9918 18:01:25.844574 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9919 18:01:25.851220 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9920 18:01:25.854805 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9921 18:01:25.858396 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9922 18:01:25.865003 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9923 18:01:25.868020 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9924 18:01:25.874790 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9925 18:01:25.877818 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9926 18:01:25.884917 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9927 18:01:25.888087 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9928 18:01:25.891762 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9929 18:01:25.898363 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9930 18:01:25.901417 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9931 18:01:25.908066 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9932 18:01:25.911474 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9933 18:01:25.917958 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9934 18:01:25.921219 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9935 18:01:25.924472 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9936 18:01:25.931101 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9937 18:01:25.934738 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9938 18:01:25.940791 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9939 18:01:25.944402 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9940 18:01:25.951560 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9941 18:01:25.954241 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9942 18:01:25.960809 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9943 18:01:25.964047 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9944 18:01:25.970687 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9945 18:01:25.974449 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9946 18:01:25.980725 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9947 18:01:25.984310 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9948 18:01:25.990452 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9949 18:01:25.994335 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9950 18:01:26.000878 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9951 18:01:26.004336 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9952 18:01:26.010401 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9953 18:01:26.013857 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9954 18:01:26.020488 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9955 18:01:26.024043 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9956 18:01:26.027237 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9957 18:01:26.033733 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9958 18:01:26.040437 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9959 18:01:26.043590 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9960 18:01:26.047566 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9961 18:01:26.054041 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9962 18:01:26.060732 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9963 18:01:26.063766 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9964 18:01:26.070445 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9965 18:01:26.073967 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9966 18:01:26.077232 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9967 18:01:26.080313 INFO: [APUAPC] vio 0
9968 18:01:26.083392 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9969 18:01:26.090671 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9970 18:01:26.093673 INFO: [APUAPC] D0_APC_0: 0x400510
9971 18:01:26.097405 INFO: [APUAPC] D0_APC_1: 0x0
9972 18:01:26.100708 INFO: [APUAPC] D0_APC_2: 0x1540
9973 18:01:26.101108 INFO: [APUAPC] D0_APC_3: 0x0
9974 18:01:26.104737 INFO: [APUAPC] D1_APC_0: 0xffffffff
9975 18:01:26.107496 INFO: [APUAPC] D1_APC_1: 0xffffffff
9976 18:01:26.110500 INFO: [APUAPC] D1_APC_2: 0x3fffff
9977 18:01:26.113905 INFO: [APUAPC] D1_APC_3: 0x0
9978 18:01:26.117324 INFO: [APUAPC] D2_APC_0: 0xffffffff
9979 18:01:26.120690 INFO: [APUAPC] D2_APC_1: 0xffffffff
9980 18:01:26.123738 INFO: [APUAPC] D2_APC_2: 0x3fffff
9981 18:01:26.127334 INFO: [APUAPC] D2_APC_3: 0x0
9982 18:01:26.130763 INFO: [APUAPC] D3_APC_0: 0xffffffff
9983 18:01:26.134379 INFO: [APUAPC] D3_APC_1: 0xffffffff
9984 18:01:26.137312 INFO: [APUAPC] D3_APC_2: 0x3fffff
9985 18:01:26.140489 INFO: [APUAPC] D3_APC_3: 0x0
9986 18:01:26.143863 INFO: [APUAPC] D4_APC_0: 0xffffffff
9987 18:01:26.147543 INFO: [APUAPC] D4_APC_1: 0xffffffff
9988 18:01:26.150985 INFO: [APUAPC] D4_APC_2: 0x3fffff
9989 18:01:26.153850 INFO: [APUAPC] D4_APC_3: 0x0
9990 18:01:26.157457 INFO: [APUAPC] D5_APC_0: 0xffffffff
9991 18:01:26.160690 INFO: [APUAPC] D5_APC_1: 0xffffffff
9992 18:01:26.164125 INFO: [APUAPC] D5_APC_2: 0x3fffff
9993 18:01:26.167336 INFO: [APUAPC] D5_APC_3: 0x0
9994 18:01:26.170913 INFO: [APUAPC] D6_APC_0: 0xffffffff
9995 18:01:26.173991 INFO: [APUAPC] D6_APC_1: 0xffffffff
9996 18:01:26.177439 INFO: [APUAPC] D6_APC_2: 0x3fffff
9997 18:01:26.180899 INFO: [APUAPC] D6_APC_3: 0x0
9998 18:01:26.183893 INFO: [APUAPC] D7_APC_0: 0xffffffff
9999 18:01:26.187569 INFO: [APUAPC] D7_APC_1: 0xffffffff
10000 18:01:26.190577 INFO: [APUAPC] D7_APC_2: 0x3fffff
10001 18:01:26.193708 INFO: [APUAPC] D7_APC_3: 0x0
10002 18:01:26.197357 INFO: [APUAPC] D8_APC_0: 0xffffffff
10003 18:01:26.200404 INFO: [APUAPC] D8_APC_1: 0xffffffff
10004 18:01:26.203908 INFO: [APUAPC] D8_APC_2: 0x3fffff
10005 18:01:26.207101 INFO: [APUAPC] D8_APC_3: 0x0
10006 18:01:26.210630 INFO: [APUAPC] D9_APC_0: 0xffffffff
10007 18:01:26.213648 INFO: [APUAPC] D9_APC_1: 0xffffffff
10008 18:01:26.217210 INFO: [APUAPC] D9_APC_2: 0x3fffff
10009 18:01:26.220205 INFO: [APUAPC] D9_APC_3: 0x0
10010 18:01:26.223884 INFO: [APUAPC] D10_APC_0: 0xffffffff
10011 18:01:26.227377 INFO: [APUAPC] D10_APC_1: 0xffffffff
10012 18:01:26.230165 INFO: [APUAPC] D10_APC_2: 0x3fffff
10013 18:01:26.233602 INFO: [APUAPC] D10_APC_3: 0x0
10014 18:01:26.237232 INFO: [APUAPC] D11_APC_0: 0xffffffff
10015 18:01:26.240699 INFO: [APUAPC] D11_APC_1: 0xffffffff
10016 18:01:26.243788 INFO: [APUAPC] D11_APC_2: 0x3fffff
10017 18:01:26.246861 INFO: [APUAPC] D11_APC_3: 0x0
10018 18:01:26.250556 INFO: [APUAPC] D12_APC_0: 0xffffffff
10019 18:01:26.253972 INFO: [APUAPC] D12_APC_1: 0xffffffff
10020 18:01:26.256882 INFO: [APUAPC] D12_APC_2: 0x3fffff
10021 18:01:26.260398 INFO: [APUAPC] D12_APC_3: 0x0
10022 18:01:26.263717 INFO: [APUAPC] D13_APC_0: 0xffffffff
10023 18:01:26.267008 INFO: [APUAPC] D13_APC_1: 0xffffffff
10024 18:01:26.270204 INFO: [APUAPC] D13_APC_2: 0x3fffff
10025 18:01:26.273808 INFO: [APUAPC] D13_APC_3: 0x0
10026 18:01:26.277492 INFO: [APUAPC] D14_APC_0: 0xffffffff
10027 18:01:26.280445 INFO: [APUAPC] D14_APC_1: 0xffffffff
10028 18:01:26.284113 INFO: [APUAPC] D14_APC_2: 0x3fffff
10029 18:01:26.286953 INFO: [APUAPC] D14_APC_3: 0x0
10030 18:01:26.290391 INFO: [APUAPC] D15_APC_0: 0xffffffff
10031 18:01:26.293595 INFO: [APUAPC] D15_APC_1: 0xffffffff
10032 18:01:26.297410 INFO: [APUAPC] D15_APC_2: 0x3fffff
10033 18:01:26.300205 INFO: [APUAPC] D15_APC_3: 0x0
10034 18:01:26.300660 INFO: [APUAPC] APC_CON: 0x4
10035 18:01:26.303944 INFO: [NOCDAPC] D0_APC_0: 0x0
10036 18:01:26.306992 INFO: [NOCDAPC] D0_APC_1: 0x0
10037 18:01:26.310556 INFO: [NOCDAPC] D1_APC_0: 0x0
10038 18:01:26.314208 INFO: [NOCDAPC] D1_APC_1: 0xfff
10039 18:01:26.317050 INFO: [NOCDAPC] D2_APC_0: 0x0
10040 18:01:26.320230 INFO: [NOCDAPC] D2_APC_1: 0xfff
10041 18:01:26.323980 INFO: [NOCDAPC] D3_APC_0: 0x0
10042 18:01:26.327438 INFO: [NOCDAPC] D3_APC_1: 0xfff
10043 18:01:26.330785 INFO: [NOCDAPC] D4_APC_0: 0x0
10044 18:01:26.331230 INFO: [NOCDAPC] D4_APC_1: 0xfff
10045 18:01:26.333661 INFO: [NOCDAPC] D5_APC_0: 0x0
10046 18:01:26.337268 INFO: [NOCDAPC] D5_APC_1: 0xfff
10047 18:01:26.340235 INFO: [NOCDAPC] D6_APC_0: 0x0
10048 18:01:26.343695 INFO: [NOCDAPC] D6_APC_1: 0xfff
10049 18:01:26.346974 INFO: [NOCDAPC] D7_APC_0: 0x0
10050 18:01:26.350619 INFO: [NOCDAPC] D7_APC_1: 0xfff
10051 18:01:26.354087 INFO: [NOCDAPC] D8_APC_0: 0x0
10052 18:01:26.357358 INFO: [NOCDAPC] D8_APC_1: 0xfff
10053 18:01:26.360621 INFO: [NOCDAPC] D9_APC_0: 0x0
10054 18:01:26.361129 INFO: [NOCDAPC] D9_APC_1: 0xfff
10055 18:01:26.363719 INFO: [NOCDAPC] D10_APC_0: 0x0
10056 18:01:26.367391 INFO: [NOCDAPC] D10_APC_1: 0xfff
10057 18:01:26.370217 INFO: [NOCDAPC] D11_APC_0: 0x0
10058 18:01:26.373858 INFO: [NOCDAPC] D11_APC_1: 0xfff
10059 18:01:26.377510 INFO: [NOCDAPC] D12_APC_0: 0x0
10060 18:01:26.380502 INFO: [NOCDAPC] D12_APC_1: 0xfff
10061 18:01:26.383821 INFO: [NOCDAPC] D13_APC_0: 0x0
10062 18:01:26.387347 INFO: [NOCDAPC] D13_APC_1: 0xfff
10063 18:01:26.390593 INFO: [NOCDAPC] D14_APC_0: 0x0
10064 18:01:26.394173 INFO: [NOCDAPC] D14_APC_1: 0xfff
10065 18:01:26.397306 INFO: [NOCDAPC] D15_APC_0: 0x0
10066 18:01:26.400245 INFO: [NOCDAPC] D15_APC_1: 0xfff
10067 18:01:26.404172 INFO: [NOCDAPC] APC_CON: 0x4
10068 18:01:26.407206 INFO: [APUAPC] set_apusys_apc done
10069 18:01:26.407812 INFO: [DEVAPC] devapc_init done
10070 18:01:26.413781 INFO: GICv3 without legacy support detected.
10071 18:01:26.416890 INFO: ARM GICv3 driver initialized in EL3
10072 18:01:26.420515 INFO: Maximum SPI INTID supported: 639
10073 18:01:26.423540 INFO: BL31: Initializing runtime services
10074 18:01:26.430462 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10075 18:01:26.433538 INFO: SPM: enable CPC mode
10076 18:01:26.436590 INFO: mcdi ready for mcusys-off-idle and system suspend
10077 18:01:26.443884 INFO: BL31: Preparing for EL3 exit to normal world
10078 18:01:26.446751 INFO: Entry point address = 0x80000000
10079 18:01:26.447223 INFO: SPSR = 0x8
10080 18:01:26.454958
10081 18:01:26.455588
10082 18:01:26.455945
10083 18:01:26.457541 Starting depthcharge on Spherion...
10084 18:01:26.457958
10085 18:01:26.458287 Wipe memory regions:
10086 18:01:26.458592
10087 18:01:26.460948 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10088 18:01:26.461458 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10089 18:01:26.461854 Setting prompt string to ['asurada:']
10090 18:01:26.462254 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10091 18:01:26.462898 [0x00000040000000, 0x00000054600000)
10092 18:01:26.583094
10093 18:01:26.583661 [0x00000054660000, 0x00000080000000)
10094 18:01:26.843800
10095 18:01:26.843963 [0x000000821a7280, 0x000000ffe64000)
10096 18:01:27.588897
10097 18:01:27.589448 [0x00000100000000, 0x00000240000000)
10098 18:01:29.479415
10099 18:01:29.482166 Initializing XHCI USB controller at 0x11200000.
10100 18:01:30.520887
10101 18:01:30.524140 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10102 18:01:30.524670
10103 18:01:30.525226
10104 18:01:30.526007 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10106 18:01:30.627302 asurada: tftpboot 192.168.201.1 14291394/tftp-deploy-qqp_ono5/kernel/image.itb 14291394/tftp-deploy-qqp_ono5/kernel/cmdline
10107 18:01:30.629143 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10108 18:01:30.629664 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10109 18:01:30.633936 tftpboot 192.168.201.1 14291394/tftp-deploy-qqp_ono5/kernel/image.ittp-deploy-qqp_ono5/kernel/cmdline
10110 18:01:30.634419
10111 18:01:30.634928 Waiting for link
10112 18:01:30.792060
10113 18:01:30.792553 R8152: Initializing
10114 18:01:30.792898
10115 18:01:30.795989 Version 6 (ocp_data = 5c30)
10116 18:01:30.796523
10117 18:01:30.798526 R8152: Done initializing
10118 18:01:30.798920
10119 18:01:30.799250 Adding net device
10120 18:01:32.699431
10121 18:01:32.699995 done.
10122 18:01:32.700362
10123 18:01:32.700705 MAC: 00:24:32:30:78:52
10124 18:01:32.701089
10125 18:01:32.702679 Sending DHCP discover... done.
10126 18:01:32.703272
10127 18:01:35.810458 Waiting for reply... done.
10128 18:01:35.810963
10129 18:01:35.811309 Sending DHCP request... done.
10130 18:01:35.811625
10131 18:01:35.814125 Waiting for reply... done.
10132 18:01:35.814552
10133 18:01:35.817114 My ip is 192.168.201.14
10134 18:01:35.817537
10135 18:01:35.820675 The DHCP server ip is 192.168.201.1
10136 18:01:35.821126
10137 18:01:35.823655 TFTP server IP predefined by user: 192.168.201.1
10138 18:01:35.824077
10139 18:01:35.830840 Bootfile predefined by user: 14291394/tftp-deploy-qqp_ono5/kernel/image.itb
10140 18:01:35.831370
10141 18:01:35.833738 Sending tftp read request... done.
10142 18:01:35.834232
10143 18:01:35.842692 Waiting for the transfer...
10144 18:01:35.843120
10145 18:01:36.463530 00000000 ################################################################
10146 18:01:36.463873
10147 18:01:37.055376 00080000 ################################################################
10148 18:01:37.055878
10149 18:01:37.726413 00100000 ################################################################
10150 18:01:37.726553
10151 18:01:38.289104 00180000 ################################################################
10152 18:01:38.289236
10153 18:01:38.871250 00200000 ################################################################
10154 18:01:38.871401
10155 18:01:39.419645 00280000 ################################################################
10156 18:01:39.419778
10157 18:01:39.965882 00300000 ################################################################
10158 18:01:39.966020
10159 18:01:40.537132 00380000 ################################################################
10160 18:01:40.537626
10161 18:01:41.195189 00400000 ################################################################
10162 18:01:41.195335
10163 18:01:41.795241 00480000 ################################################################
10164 18:01:41.795554
10165 18:01:42.403531 00500000 ################################################################
10166 18:01:42.403672
10167 18:01:43.042363 00580000 ################################################################
10168 18:01:43.042989
10169 18:01:43.721984 00600000 ################################################################
10170 18:01:43.722495
10171 18:01:44.360811 00680000 ################################################################
10172 18:01:44.360947
10173 18:01:45.039981 00700000 ################################################################
10174 18:01:45.040513
10175 18:01:45.738927 00780000 ################################################################
10176 18:01:45.739122
10177 18:01:46.341940 00800000 ################################################################
10178 18:01:46.342111
10179 18:01:46.967768 00880000 ################################################################
10180 18:01:46.968292
10181 18:01:47.657923 00900000 ################################################################
10182 18:01:47.658419
10183 18:01:48.348483 00980000 ################################################################
10184 18:01:48.349025
10185 18:01:49.037598 00a00000 ################################################################
10186 18:01:49.038127
10187 18:01:49.658915 00a80000 ################################################################
10188 18:01:49.659056
10189 18:01:50.221649 00b00000 ################################################################
10190 18:01:50.221800
10191 18:01:50.783264 00b80000 ################################################################
10192 18:01:50.783432
10193 18:01:51.325516 00c00000 ################################################################
10194 18:01:51.325664
10195 18:01:51.891942 00c80000 ################################################################
10196 18:01:51.892097
10197 18:01:52.429398 00d00000 ################################################################
10198 18:01:52.429551
10199 18:01:52.960882 00d80000 ################################################################
10200 18:01:52.961070
10201 18:01:53.490703 00e00000 ################################################################
10202 18:01:53.490853
10203 18:01:54.054275 00e80000 ################################################################
10204 18:01:54.054423
10205 18:01:54.617221 00f00000 ################################################################
10206 18:01:54.617375
10207 18:01:55.174117 00f80000 ################################################################
10208 18:01:55.174270
10209 18:01:55.738057 01000000 ################################################################
10210 18:01:55.738204
10211 18:01:56.313007 01080000 ################################################################
10212 18:01:56.313201
10213 18:01:56.890969 01100000 ################################################################
10214 18:01:56.891120
10215 18:01:57.459512 01180000 ################################################################
10216 18:01:57.459658
10217 18:01:58.036008 01200000 ################################################################
10218 18:01:58.036137
10219 18:01:58.625952 01280000 ################################################################
10220 18:01:58.626107
10221 18:01:59.212265 01300000 ################################################################
10222 18:01:59.212424
10223 18:01:59.771958 01380000 ################################################################
10224 18:01:59.772105
10225 18:02:00.344333 01400000 ################################################################
10226 18:02:00.344489
10227 18:02:00.921811 01480000 ################################################################
10228 18:02:00.921965
10229 18:02:01.502154 01500000 ################################################################
10230 18:02:01.502303
10231 18:02:02.105954 01580000 ################################################################
10232 18:02:02.106101
10233 18:02:02.780789 01600000 ################################################################
10234 18:02:02.781319
10235 18:02:03.472601 01680000 ################################################################
10236 18:02:03.473135
10237 18:02:04.178978 01700000 ################################################################
10238 18:02:04.179547
10239 18:02:04.886133 01780000 ################################################################
10240 18:02:04.886679
10241 18:02:05.595724 01800000 ################################################################
10242 18:02:05.596262
10243 18:02:06.300956 01880000 ################################################################
10244 18:02:06.301525
10245 18:02:06.928812 01900000 ################################################################
10246 18:02:06.929388
10247 18:02:07.628710 01980000 ################################################################
10248 18:02:07.629276
10249 18:02:08.318447 01a00000 ################################################################
10250 18:02:08.318995
10251 18:02:09.018875 01a80000 ################################################################
10252 18:02:09.019398
10253 18:02:09.721653 01b00000 ################################################################
10254 18:02:09.722176
10255 18:02:10.423067 01b80000 ################################################################
10256 18:02:10.423678
10257 18:02:11.015618 01c00000 ################################################################
10258 18:02:11.015756
10259 18:02:11.549318 01c80000 ################################################################
10260 18:02:11.549465
10261 18:02:12.095107 01d00000 ################################################################
10262 18:02:12.095253
10263 18:02:12.625403 01d80000 ################################################################
10264 18:02:12.625556
10265 18:02:13.092216 01e00000 ####################################################### done.
10266 18:02:13.092367
10267 18:02:13.095792 The bootfile was 31906202 bytes long.
10268 18:02:13.095919
10269 18:02:13.099278 Sending tftp read request... done.
10270 18:02:13.099396
10271 18:02:13.099486 Waiting for the transfer...
10272 18:02:13.099610
10273 18:02:13.102259 00000000 # done.
10274 18:02:13.102357
10275 18:02:13.108801 Command line loaded dynamically from TFTP file: 14291394/tftp-deploy-qqp_ono5/kernel/cmdline
10276 18:02:13.108927
10277 18:02:13.132437 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14291394/extract-nfsrootfs-zajh3fwr,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10278 18:02:13.132603
10279 18:02:13.132692 Loading FIT.
10280 18:02:13.132753
10281 18:02:13.135786 Image ramdisk-1 has 18731806 bytes.
10282 18:02:13.135869
10283 18:02:13.139100 Image fdt-1 has 47258 bytes.
10284 18:02:13.139183
10285 18:02:13.142477 Image kernel-1 has 13125101 bytes.
10286 18:02:13.142560
10287 18:02:13.152147 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10288 18:02:13.152235
10289 18:02:13.168766 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10290 18:02:13.168869
10291 18:02:13.175345 Choosing best match conf-1 for compat google,spherion-rev2.
10292 18:02:13.175430
10293 18:02:13.179565 Connected to device vid:did:rid of 1ae0:0028:00
10294 18:02:13.189472
10295 18:02:13.192857 tpm_get_response: command 0x17b, return code 0x0
10296 18:02:13.192968
10297 18:02:13.196469 ec_init: CrosEC protocol v3 supported (256, 248)
10298 18:02:13.200030
10299 18:02:13.203603 tpm_cleanup: add release locality here.
10300 18:02:13.203688
10301 18:02:13.206616 Shutting down all USB controllers.
10302 18:02:13.206700
10303 18:02:13.206766 Removing current net device
10304 18:02:13.206827
10305 18:02:13.213196 Exiting depthcharge with code 4 at timestamp: 76184647
10306 18:02:13.213280
10307 18:02:13.216628 LZMA decompressing kernel-1 to 0x821a6718
10308 18:02:13.216738
10309 18:02:13.220216 LZMA decompressing kernel-1 to 0x40000000
10310 18:02:14.837550
10311 18:02:14.837688 jumping to kernel
10312 18:02:14.838272 end: 2.2.4 bootloader-commands (duration 00:00:48) [common]
10313 18:02:14.838374 start: 2.2.5 auto-login-action (timeout 00:03:36) [common]
10314 18:02:14.838457 Setting prompt string to ['Linux version [0-9]']
10315 18:02:14.838529 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10316 18:02:14.838597 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10317 18:02:14.919203
10318 18:02:14.922340 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10319 18:02:14.926200 start: 2.2.5.1 login-action (timeout 00:03:36) [common]
10320 18:02:14.926337 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10321 18:02:14.926417 Setting prompt string to []
10322 18:02:14.926491 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10323 18:02:14.926568 Using line separator: #'\n'#
10324 18:02:14.926659 No login prompt set.
10325 18:02:14.926750 Parsing kernel messages
10326 18:02:14.926834 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10327 18:02:14.927013 [login-action] Waiting for messages, (timeout 00:03:36)
10328 18:02:14.927115 Waiting using forced prompt support (timeout 00:01:48)
10329 18:02:14.945740 [ 0.000000] Linux version 6.1.92-cip22 (KernelCI@build-j225340-arm64-gcc-10-defconfig-arm64-chromebook-x2t4v) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue Jun 11 17:44:14 UTC 2024
10330 18:02:14.949320 [ 0.000000] random: crng init done
10331 18:02:14.955592 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10332 18:02:14.959071 [ 0.000000] efi: UEFI not found.
10333 18:02:14.965479 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10334 18:02:14.972292 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10335 18:02:14.982163 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10336 18:02:14.992361 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10337 18:02:14.998967 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10338 18:02:15.005543 [ 0.000000] printk: bootconsole [mtk8250] enabled
10339 18:02:15.011899 [ 0.000000] NUMA: No NUMA configuration found
10340 18:02:15.018583 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10341 18:02:15.022196 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10342 18:02:15.025263 [ 0.000000] Zone ranges:
10343 18:02:15.032099 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10344 18:02:15.035618 [ 0.000000] DMA32 empty
10345 18:02:15.042028 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10346 18:02:15.045453 [ 0.000000] Movable zone start for each node
10347 18:02:15.048655 [ 0.000000] Early memory node ranges
10348 18:02:15.055319 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10349 18:02:15.062235 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10350 18:02:15.068514 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10351 18:02:15.072168 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10352 18:02:15.078765 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10353 18:02:15.085295 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10354 18:02:15.144165 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10355 18:02:15.150733 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10356 18:02:15.157084 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10357 18:02:15.160190 [ 0.000000] psci: probing for conduit method from DT.
10358 18:02:15.167454 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10359 18:02:15.170502 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10360 18:02:15.177019 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10361 18:02:15.180380 [ 0.000000] psci: SMC Calling Convention v1.2
10362 18:02:15.187514 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10363 18:02:15.190670 [ 0.000000] Detected VIPT I-cache on CPU0
10364 18:02:15.197134 [ 0.000000] CPU features: detected: GIC system register CPU interface
10365 18:02:15.203721 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10366 18:02:15.210255 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10367 18:02:15.217796 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10368 18:02:15.223764 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10369 18:02:15.230268 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10370 18:02:15.236826 [ 0.000000] alternatives: applying boot alternatives
10371 18:02:15.240678 [ 0.000000] Fallback order for Node 0: 0
10372 18:02:15.247056 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10373 18:02:15.250107 [ 0.000000] Policy zone: Normal
10374 18:02:15.273470 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14291394/extract-nfsrootfs-zajh3fwr,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10375 18:02:15.286782 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10376 18:02:15.296967 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10377 18:02:15.307032 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10378 18:02:15.313543 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10379 18:02:15.316883 <6>[ 0.000000] software IO TLB: area num 8.
10380 18:02:15.373731 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10381 18:02:15.522904 <6>[ 0.000000] Memory: 7945768K/8385536K available (18112K kernel code, 4120K rwdata, 22644K rodata, 8512K init, 616K bss, 407000K reserved, 32768K cma-reserved)
10382 18:02:15.529526 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10383 18:02:15.536168 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10384 18:02:15.539754 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10385 18:02:15.546359 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10386 18:02:15.552763 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10387 18:02:15.556285 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10388 18:02:15.566217 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10389 18:02:15.573182 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10390 18:02:15.576607 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10391 18:02:15.583746 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10392 18:02:15.587602 <6>[ 0.000000] GICv3: 608 SPIs implemented
10393 18:02:15.594249 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10394 18:02:15.597246 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10395 18:02:15.600774 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10396 18:02:15.610502 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10397 18:02:15.620856 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10398 18:02:15.634130 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10399 18:02:15.640685 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10400 18:02:15.649667 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10401 18:02:15.662959 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10402 18:02:15.669562 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10403 18:02:15.676083 <6>[ 0.009234] Console: colour dummy device 80x25
10404 18:02:15.686136 <6>[ 0.013994] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10405 18:02:15.689790 <6>[ 0.024436] pid_max: default: 32768 minimum: 301
10406 18:02:15.696212 <6>[ 0.029307] LSM: Security Framework initializing
10407 18:02:15.703106 <6>[ 0.034274] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10408 18:02:15.712699 <6>[ 0.042138] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10409 18:02:15.719641 <6>[ 0.051558] cblist_init_generic: Setting adjustable number of callback queues.
10410 18:02:15.726373 <6>[ 0.059002] cblist_init_generic: Setting shift to 3 and lim to 1.
10411 18:02:15.736071 <6>[ 0.065382] cblist_init_generic: Setting adjustable number of callback queues.
10412 18:02:15.739690 <6>[ 0.072808] cblist_init_generic: Setting shift to 3 and lim to 1.
10413 18:02:15.746234 <6>[ 0.079247] rcu: Hierarchical SRCU implementation.
10414 18:02:15.752893 <6>[ 0.084262] rcu: Max phase no-delay instances is 1000.
10415 18:02:15.759357 <6>[ 0.091332] EFI services will not be available.
10416 18:02:15.762470 <6>[ 0.096285] smp: Bringing up secondary CPUs ...
10417 18:02:15.770196 <6>[ 0.101336] Detected VIPT I-cache on CPU1
10418 18:02:15.777453 <6>[ 0.101410] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10419 18:02:15.783630 <6>[ 0.101442] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10420 18:02:15.787199 <6>[ 0.101785] Detected VIPT I-cache on CPU2
10421 18:02:15.793926 <6>[ 0.101838] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10422 18:02:15.800824 <6>[ 0.101857] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10423 18:02:15.807350 <6>[ 0.102104] Detected VIPT I-cache on CPU3
10424 18:02:15.814055 <6>[ 0.102146] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10425 18:02:15.820721 <6>[ 0.102160] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10426 18:02:15.823990 <6>[ 0.102452] CPU features: detected: Spectre-v4
10427 18:02:15.830673 <6>[ 0.102458] CPU features: detected: Spectre-BHB
10428 18:02:15.834036 <6>[ 0.102463] Detected PIPT I-cache on CPU4
10429 18:02:15.840790 <6>[ 0.102524] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10430 18:02:15.847112 <6>[ 0.102540] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10431 18:02:15.850616 <6>[ 0.102835] Detected PIPT I-cache on CPU5
10432 18:02:15.860726 <6>[ 0.102897] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10433 18:02:15.867319 <6>[ 0.102913] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10434 18:02:15.870220 <6>[ 0.103198] Detected PIPT I-cache on CPU6
10435 18:02:15.876780 <6>[ 0.103263] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10436 18:02:15.883409 <6>[ 0.103279] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10437 18:02:15.886994 <6>[ 0.103576] Detected PIPT I-cache on CPU7
10438 18:02:15.897276 <6>[ 0.103641] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10439 18:02:15.903578 <6>[ 0.103658] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10440 18:02:15.907043 <6>[ 0.103706] smp: Brought up 1 node, 8 CPUs
10441 18:02:15.913728 <6>[ 0.245095] SMP: Total of 8 processors activated.
10442 18:02:15.916733 <6>[ 0.250047] CPU features: detected: 32-bit EL0 Support
10443 18:02:15.926931 <6>[ 0.255443] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10444 18:02:15.933596 <6>[ 0.264243] CPU features: detected: Common not Private translations
10445 18:02:15.936593 <6>[ 0.270719] CPU features: detected: CRC32 instructions
10446 18:02:15.943268 <6>[ 0.276070] CPU features: detected: RCpc load-acquire (LDAPR)
10447 18:02:15.950103 <6>[ 0.282067] CPU features: detected: LSE atomic instructions
10448 18:02:15.956765 <6>[ 0.287884] CPU features: detected: Privileged Access Never
10449 18:02:15.960300 <6>[ 0.293699] CPU features: detected: RAS Extension Support
10450 18:02:15.966709 <6>[ 0.299308] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10451 18:02:15.973535 <6>[ 0.306528] CPU: All CPU(s) started at EL2
10452 18:02:15.977098 <6>[ 0.310845] alternatives: applying system-wide alternatives
10453 18:02:15.988385 <6>[ 0.321692] devtmpfs: initialized
10454 18:02:16.000538 <6>[ 0.330644] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10455 18:02:16.010743 <6>[ 0.340603] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10456 18:02:16.017162 <6>[ 0.348610] pinctrl core: initialized pinctrl subsystem
10457 18:02:16.020785 <6>[ 0.355299] DMI not present or invalid.
10458 18:02:16.027419 <6>[ 0.359710] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10459 18:02:16.037104 <6>[ 0.366570] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10460 18:02:16.044017 <6>[ 0.374161] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10461 18:02:16.054040 <6>[ 0.382378] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10462 18:02:16.057548 <6>[ 0.390620] audit: initializing netlink subsys (disabled)
10463 18:02:16.067113 <5>[ 0.396312] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10464 18:02:16.073832 <6>[ 0.397039] thermal_sys: Registered thermal governor 'step_wise'
10465 18:02:16.080843 <6>[ 0.404280] thermal_sys: Registered thermal governor 'power_allocator'
10466 18:02:16.084068 <6>[ 0.410534] cpuidle: using governor menu
10467 18:02:16.086864 <6>[ 0.421496] NET: Registered PF_QIPCRTR protocol family
10468 18:02:16.096928 <6>[ 0.426979] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10469 18:02:16.100481 <6>[ 0.434085] ASID allocator initialised with 32768 entries
10470 18:02:16.107197 <6>[ 0.440678] Serial: AMBA PL011 UART driver
10471 18:02:16.116386 <4>[ 0.449549] Trying to register duplicate clock ID: 134
10472 18:02:16.176199 <6>[ 0.513033] KASLR enabled
10473 18:02:16.190755 <6>[ 0.520797] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10474 18:02:16.197454 <6>[ 0.527813] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10475 18:02:16.203993 <6>[ 0.534304] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10476 18:02:16.210639 <6>[ 0.541311] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10477 18:02:16.217684 <6>[ 0.547797] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10478 18:02:16.224165 <6>[ 0.554803] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10479 18:02:16.230811 <6>[ 0.561290] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10480 18:02:16.237324 <6>[ 0.568294] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10481 18:02:16.240897 <6>[ 0.575814] ACPI: Interpreter disabled.
10482 18:02:16.248836 <6>[ 0.582243] iommu: Default domain type: Translated
10483 18:02:16.255861 <6>[ 0.587354] iommu: DMA domain TLB invalidation policy: strict mode
10484 18:02:16.258760 <5>[ 0.594014] SCSI subsystem initialized
10485 18:02:16.265637 <6>[ 0.598183] usbcore: registered new interface driver usbfs
10486 18:02:16.272075 <6>[ 0.603917] usbcore: registered new interface driver hub
10487 18:02:16.275246 <6>[ 0.609469] usbcore: registered new device driver usb
10488 18:02:16.282072 <6>[ 0.615577] pps_core: LinuxPPS API ver. 1 registered
10489 18:02:16.292338 <6>[ 0.620770] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10490 18:02:16.295962 <6>[ 0.630118] PTP clock support registered
10491 18:02:16.299037 <6>[ 0.634362] EDAC MC: Ver: 3.0.0
10492 18:02:16.306426 <6>[ 0.639502] FPGA manager framework
10493 18:02:16.312835 <6>[ 0.643189] Advanced Linux Sound Architecture Driver Initialized.
10494 18:02:16.315988 <6>[ 0.649968] vgaarb: loaded
10495 18:02:16.322642 <6>[ 0.653136] clocksource: Switched to clocksource arch_sys_counter
10496 18:02:16.326190 <5>[ 0.659581] VFS: Disk quotas dquot_6.6.0
10497 18:02:16.332834 <6>[ 0.663766] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10498 18:02:16.335804 <6>[ 0.670958] pnp: PnP ACPI: disabled
10499 18:02:16.344675 <6>[ 0.677700] NET: Registered PF_INET protocol family
10500 18:02:16.354147 <6>[ 0.683292] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10501 18:02:16.365819 <6>[ 0.695600] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10502 18:02:16.375882 <6>[ 0.704411] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10503 18:02:16.382209 <6>[ 0.712383] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10504 18:02:16.388964 <6>[ 0.721084] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10505 18:02:16.401248 <6>[ 0.730842] TCP: Hash tables configured (established 65536 bind 65536)
10506 18:02:16.407794 <6>[ 0.737706] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10507 18:02:16.414202 <6>[ 0.744905] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10508 18:02:16.420797 <6>[ 0.752611] NET: Registered PF_UNIX/PF_LOCAL protocol family
10509 18:02:16.427324 <6>[ 0.758766] RPC: Registered named UNIX socket transport module.
10510 18:02:16.430752 <6>[ 0.764921] RPC: Registered udp transport module.
10511 18:02:16.437293 <6>[ 0.769854] RPC: Registered tcp transport module.
10512 18:02:16.444334 <6>[ 0.774789] RPC: Registered tcp NFSv4.1 backchannel transport module.
10513 18:02:16.447734 <6>[ 0.781456] PCI: CLS 0 bytes, default 64
10514 18:02:16.450867 <6>[ 0.785782] Unpacking initramfs...
10515 18:02:16.467728 <6>[ 0.797645] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10516 18:02:16.478041 <6>[ 0.806258] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10517 18:02:16.481258 <6>[ 0.815081] kvm [1]: IPA Size Limit: 40 bits
10518 18:02:16.487891 <6>[ 0.819611] kvm [1]: GICv3: no GICV resource entry
10519 18:02:16.490755 <6>[ 0.824633] kvm [1]: disabling GICv2 emulation
10520 18:02:16.497445 <6>[ 0.829322] kvm [1]: GIC system register CPU interface enabled
10521 18:02:16.501098 <6>[ 0.835478] kvm [1]: vgic interrupt IRQ18
10522 18:02:16.507795 <6>[ 0.839833] kvm [1]: VHE mode initialized successfully
10523 18:02:16.514260 <5>[ 0.846340] Initialise system trusted keyrings
10524 18:02:16.520614 <6>[ 0.851146] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10525 18:02:16.527857 <6>[ 0.861262] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10526 18:02:16.534482 <5>[ 0.867647] NFS: Registering the id_resolver key type
10527 18:02:16.538003 <5>[ 0.872942] Key type id_resolver registered
10528 18:02:16.544505 <5>[ 0.877357] Key type id_legacy registered
10529 18:02:16.551206 <6>[ 0.881639] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10530 18:02:16.557984 <6>[ 0.888560] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10531 18:02:16.564829 <6>[ 0.896299] 9p: Installing v9fs 9p2000 file system support
10532 18:02:16.600785 <5>[ 0.933963] Key type asymmetric registered
10533 18:02:16.604171 <5>[ 0.938296] Asymmetric key parser 'x509' registered
10534 18:02:16.613843 <6>[ 0.943442] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10535 18:02:16.617322 <6>[ 0.951058] io scheduler mq-deadline registered
10536 18:02:16.620283 <6>[ 0.955838] io scheduler kyber registered
10537 18:02:16.639434 <6>[ 0.972984] EINJ: ACPI disabled.
10538 18:02:16.672742 <4>[ 0.999458] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10539 18:02:16.682801 <4>[ 1.010108] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10540 18:02:16.697553 <6>[ 1.031112] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10541 18:02:16.705719 <6>[ 1.039170] printk: console [ttyS0] disabled
10542 18:02:16.733740 <6>[ 1.063804] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10543 18:02:16.740308 <6>[ 1.073278] printk: console [ttyS0] enabled
10544 18:02:16.744005 <6>[ 1.073278] printk: console [ttyS0] enabled
10545 18:02:16.750583 <6>[ 1.082171] printk: bootconsole [mtk8250] disabled
10546 18:02:16.754103 <6>[ 1.082171] printk: bootconsole [mtk8250] disabled
10547 18:02:16.760575 <6>[ 1.093228] SuperH (H)SCI(F) driver initialized
10548 18:02:16.764084 <6>[ 1.098497] msm_serial: driver initialized
10549 18:02:16.777817 <6>[ 1.107439] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10550 18:02:16.787633 <6>[ 1.115986] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10551 18:02:16.793977 <6>[ 1.124529] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10552 18:02:16.804053 <6>[ 1.133157] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10553 18:02:16.810679 <6>[ 1.141863] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10554 18:02:16.820534 <6>[ 1.150582] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10555 18:02:16.830510 <6>[ 1.159125] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10556 18:02:16.837442 <6>[ 1.167923] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10557 18:02:16.846974 <6>[ 1.176464] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10558 18:02:16.858387 <6>[ 1.191780] loop: module loaded
10559 18:02:16.865264 <6>[ 1.197789] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10560 18:02:16.887983 <4>[ 1.221111] mtk-pmic-keys: Failed to locate of_node [id: -1]
10561 18:02:16.894648 <6>[ 1.227874] megasas: 07.719.03.00-rc1
10562 18:02:16.904196 <6>[ 1.237420] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10563 18:02:16.915456 <6>[ 1.248532] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10564 18:02:16.932010 <6>[ 1.265225] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10565 18:02:16.988427 <6>[ 1.315144] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10566 18:02:17.244688 <6>[ 1.578305] Freeing initrd memory: 18288K
10567 18:02:17.256697 <6>[ 1.589969] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10568 18:02:17.267522 <6>[ 1.600862] tun: Universal TUN/TAP device driver, 1.6
10569 18:02:17.271014 <6>[ 1.606911] thunder_xcv, ver 1.0
10570 18:02:17.274430 <6>[ 1.610417] thunder_bgx, ver 1.0
10571 18:02:17.277855 <6>[ 1.613915] nicpf, ver 1.0
10572 18:02:17.287805 <6>[ 1.617931] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10573 18:02:17.291401 <6>[ 1.625407] hns3: Copyright (c) 2017 Huawei Corporation.
10574 18:02:17.294444 <6>[ 1.630995] hclge is initializing
10575 18:02:17.301482 <6>[ 1.634574] e1000: Intel(R) PRO/1000 Network Driver
10576 18:02:17.308208 <6>[ 1.639704] e1000: Copyright (c) 1999-2006 Intel Corporation.
10577 18:02:17.311090 <6>[ 1.645717] e1000e: Intel(R) PRO/1000 Network Driver
10578 18:02:17.317876 <6>[ 1.650932] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10579 18:02:17.324760 <6>[ 1.657117] igb: Intel(R) Gigabit Ethernet Network Driver
10580 18:02:17.331227 <6>[ 1.662768] igb: Copyright (c) 2007-2014 Intel Corporation.
10581 18:02:17.338042 <6>[ 1.668603] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10582 18:02:17.341479 <6>[ 1.675120] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10583 18:02:17.348207 <6>[ 1.681582] sky2: driver version 1.30
10584 18:02:17.354692 <6>[ 1.686508] usbcore: registered new device driver r8152-cfgselector
10585 18:02:17.361819 <6>[ 1.693045] usbcore: registered new interface driver r8152
10586 18:02:17.364940 <6>[ 1.698858] VFIO - User Level meta-driver version: 0.3
10587 18:02:17.373924 <6>[ 1.707089] usbcore: registered new interface driver usb-storage
10588 18:02:17.380323 <6>[ 1.713530] usbcore: registered new device driver onboard-usb-hub
10589 18:02:17.389528 <6>[ 1.722676] mt6397-rtc mt6359-rtc: registered as rtc0
10590 18:02:17.399689 <6>[ 1.728142] mt6397-rtc mt6359-rtc: setting system clock to 2024-06-11T18:02:16 UTC (1718128936)
10591 18:02:17.402661 <6>[ 1.737733] i2c_dev: i2c /dev entries driver
10592 18:02:17.416500 <4>[ 1.749857] cpu cpu0: supply cpu not found, using dummy regulator
10593 18:02:17.423232 <4>[ 1.756285] cpu cpu1: supply cpu not found, using dummy regulator
10594 18:02:17.429637 <4>[ 1.762690] cpu cpu2: supply cpu not found, using dummy regulator
10595 18:02:17.436712 <4>[ 1.769093] cpu cpu3: supply cpu not found, using dummy regulator
10596 18:02:17.443496 <4>[ 1.775493] cpu cpu4: supply cpu not found, using dummy regulator
10597 18:02:17.449626 <4>[ 1.781912] cpu cpu5: supply cpu not found, using dummy regulator
10598 18:02:17.456622 <4>[ 1.788308] cpu cpu6: supply cpu not found, using dummy regulator
10599 18:02:17.463127 <4>[ 1.794700] cpu cpu7: supply cpu not found, using dummy regulator
10600 18:02:17.481964 <6>[ 1.815355] cpu cpu0: EM: created perf domain
10601 18:02:17.485357 <6>[ 1.820296] cpu cpu4: EM: created perf domain
10602 18:02:17.492781 <6>[ 1.825906] sdhci: Secure Digital Host Controller Interface driver
10603 18:02:17.499201 <6>[ 1.832337] sdhci: Copyright(c) Pierre Ossman
10604 18:02:17.505798 <6>[ 1.837295] Synopsys Designware Multimedia Card Interface Driver
10605 18:02:17.512436 <6>[ 1.843942] sdhci-pltfm: SDHCI platform and OF driver helper
10606 18:02:17.515993 <6>[ 1.843962] mmc0: CQHCI version 5.10
10607 18:02:17.522438 <6>[ 1.854181] ledtrig-cpu: registered to indicate activity on CPUs
10608 18:02:17.528796 <6>[ 1.861223] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10609 18:02:17.536173 <6>[ 1.868288] usbcore: registered new interface driver usbhid
10610 18:02:17.539091 <6>[ 1.874110] usbhid: USB HID core driver
10611 18:02:17.546134 <6>[ 1.878291] spi_master spi0: will run message pump with realtime priority
10612 18:02:17.591576 <6>[ 1.918170] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10613 18:02:17.606981 <6>[ 1.933543] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10614 18:02:17.614348 <6>[ 1.946386] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x16c14
10615 18:02:17.621516 <6>[ 1.949343] cros-ec-spi spi0.0: Chrome EC device registered
10616 18:02:17.624564 <6>[ 1.959001] mmc0: Command Queue Engine enabled
10617 18:02:17.631444 <6>[ 1.963755] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10618 18:02:17.638026 <6>[ 1.971068] mmcblk0: mmc0:0001 DA4128 116 GiB
10619 18:02:17.648215 <6>[ 1.973483] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10620 18:02:17.651746 <6>[ 1.979523] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10621 18:02:17.657881 <6>[ 1.986227] NET: Registered PF_PACKET protocol family
10622 18:02:17.664398 <6>[ 1.992662] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10623 18:02:17.667858 <6>[ 1.996363] 9pnet: Installing 9P2000 support
10624 18:02:17.671412 <6>[ 2.002220] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10625 18:02:17.677924 <5>[ 2.006076] Key type dns_resolver registered
10626 18:02:17.684757 <6>[ 2.011903] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10627 18:02:17.688450 <6>[ 2.016241] registered taskstats version 1
10628 18:02:17.694961 <5>[ 2.026671] Loading compiled-in X.509 certificates
10629 18:02:17.721801 <4>[ 2.048800] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10630 18:02:17.731898 <4>[ 2.059508] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10631 18:02:17.745796 <6>[ 2.079266] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10632 18:02:17.752938 <6>[ 2.086195] xhci-mtk 11200000.usb: xHCI Host Controller
10633 18:02:17.759335 <6>[ 2.091713] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10634 18:02:17.769655 <6>[ 2.099569] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10635 18:02:17.776373 <6>[ 2.109003] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10636 18:02:17.782626 <6>[ 2.115182] xhci-mtk 11200000.usb: xHCI Host Controller
10637 18:02:17.789490 <6>[ 2.120675] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10638 18:02:17.796064 <6>[ 2.128329] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10639 18:02:17.802734 <6>[ 2.136152] hub 1-0:1.0: USB hub found
10640 18:02:17.806034 <6>[ 2.140179] hub 1-0:1.0: 1 port detected
10641 18:02:17.812474 <6>[ 2.144478] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10642 18:02:17.819989 <6>[ 2.153277] hub 2-0:1.0: USB hub found
10643 18:02:17.822906 <6>[ 2.157299] hub 2-0:1.0: 1 port detected
10644 18:02:17.830565 <6>[ 2.164302] mtk-msdc 11f70000.mmc: Got CD GPIO
10645 18:02:17.844759 <6>[ 2.174881] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10646 18:02:17.851337 <6>[ 2.183277] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10647 18:02:17.861500 <6>[ 2.191617] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10648 18:02:17.867977 <6>[ 2.199956] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10649 18:02:17.878405 <6>[ 2.208295] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10650 18:02:17.887901 <6>[ 2.216633] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10651 18:02:17.894668 <6>[ 2.224977] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10652 18:02:17.901767 <6>[ 2.233315] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10653 18:02:17.911800 <6>[ 2.241653] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10654 18:02:17.918018 <6>[ 2.249992] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10655 18:02:17.928668 <6>[ 2.258330] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10656 18:02:17.935188 <6>[ 2.266668] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10657 18:02:17.944797 <6>[ 2.275011] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10658 18:02:17.955253 <6>[ 2.283352] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10659 18:02:17.961896 <6>[ 2.291689] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10660 18:02:17.968530 <6>[ 2.300370] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10661 18:02:17.974924 <6>[ 2.307510] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10662 18:02:17.981828 <6>[ 2.314267] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10663 18:02:17.988565 <6>[ 2.321049] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10664 18:02:17.994968 <6>[ 2.327979] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10665 18:02:18.004824 <6>[ 2.334832] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10666 18:02:18.015046 <6>[ 2.343967] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10667 18:02:18.024827 <6>[ 2.353089] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10668 18:02:18.034647 <6>[ 2.362383] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10669 18:02:18.041182 <6>[ 2.371849] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10670 18:02:18.051403 <6>[ 2.381322] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10671 18:02:18.061412 <6>[ 2.390442] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10672 18:02:18.070968 <6>[ 2.399908] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10673 18:02:18.081099 <6>[ 2.409026] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10674 18:02:18.090838 <6>[ 2.418320] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10675 18:02:18.100921 <6>[ 2.428480] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10676 18:02:18.110856 <6>[ 2.440597] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10677 18:02:18.118015 <6>[ 2.451727] Trying to probe devices needed for running init ...
10678 18:02:18.128560 <3>[ 2.458990] mt8192-audio 11210000.syscon:mt8192-afe-pcm: could not get audiosys reset:-517
10679 18:02:18.231002 <6>[ 2.561416] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10680 18:02:18.385557 <6>[ 2.719386] hub 1-1:1.0: USB hub found
10681 18:02:18.389091 <6>[ 2.723942] hub 1-1:1.0: 4 ports detected
10682 18:02:18.400929 <6>[ 2.734588] hub 1-1:1.0: USB hub found
10683 18:02:18.404420 <6>[ 2.739023] hub 1-1:1.0: 4 ports detected
10684 18:02:18.511201 <6>[ 2.841623] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10685 18:02:18.538050 <6>[ 2.871577] hub 2-1:1.0: USB hub found
10686 18:02:18.541441 <6>[ 2.876070] hub 2-1:1.0: 3 ports detected
10687 18:02:18.553638 <6>[ 2.886979] hub 2-1:1.0: USB hub found
10688 18:02:18.556430 <6>[ 2.891492] hub 2-1:1.0: 3 ports detected
10689 18:02:18.727215 <6>[ 3.057454] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10690 18:02:18.859101 <6>[ 3.192705] hub 1-1.4:1.0: USB hub found
10691 18:02:18.862496 <6>[ 3.197276] hub 1-1.4:1.0: 2 ports detected
10692 18:02:18.876335 <6>[ 3.210051] hub 1-1.4:1.0: USB hub found
10693 18:02:18.879517 <6>[ 3.214684] hub 1-1.4:1.0: 2 ports detected
10694 18:02:18.946982 <6>[ 3.277664] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10695 18:02:19.055973 <6>[ 3.386092] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10696 18:02:19.092723 <4>[ 3.422674] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10697 18:02:19.101979 <4>[ 3.431895] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10698 18:02:19.140901 <6>[ 3.474772] r8152 2-1.3:1.0 eth0: v1.12.13
10699 18:02:19.190843 <6>[ 3.521323] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10700 18:02:19.383342 <6>[ 3.713472] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10701 18:02:20.796721 <6>[ 5.130350] r8152 2-1.3:1.0 eth0: carrier on
10702 18:02:22.919325 <5>[ 5.161195] Sending DHCP requests .., OK
10703 18:02:22.925741 <6>[ 7.257524] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.14
10704 18:02:22.929014 <6>[ 7.265817] IP-Config: Complete:
10705 18:02:22.942411 <6>[ 7.269311] device=eth0, hwaddr=00:24:32:30:78:52, ipaddr=192.168.201.14, mask=255.255.255.0, gw=192.168.201.1
10706 18:02:22.949509 <6>[ 7.280031] host=mt8192-asurada-spherion-r0-cbg-3, domain=lava-rack, nis-domain=(none)
10707 18:02:22.955899 <6>[ 7.288650] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10708 18:02:22.962427 <6>[ 7.288659] nameserver0=192.168.201.1
10709 18:02:22.965977 <6>[ 7.300811] clk: Disabling unused clocks
10710 18:02:22.969457 <6>[ 7.306332] ALSA device list:
10711 18:02:22.972392 <6>[ 7.309583] No soundcards found.
10712 18:02:22.982922 <6>[ 7.316810] Freeing unused kernel memory: 8512K
10713 18:02:22.986240 <6>[ 7.321781] Run /init as init process
10714 18:02:22.995726 Loading, please wait...
10715 18:02:23.024533 Starting systemd-udevd version 252.22-1~deb12u1
10716 18:02:23.313679 <6>[ 7.644011] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10717 18:02:23.319732 <6>[ 7.645426] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10718 18:02:23.329797 <6>[ 7.653340] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10719 18:02:23.339918 <6>[ 7.669068] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10720 18:02:23.346443 <6>[ 7.669794] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10721 18:02:23.352864 <6>[ 7.685819] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10722 18:02:23.362925 <4>[ 7.689699] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10723 18:02:23.370061 <4>[ 7.693929] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10724 18:02:23.379537 <6>[ 7.695155] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10725 18:02:23.386331 <3>[ 7.702732] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10726 18:02:23.389591 <6>[ 7.702962] mc: Linux media interface: v0.10
10727 18:02:23.399770 <4>[ 7.703111] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10728 18:02:23.406270 <6>[ 7.703188] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10729 18:02:23.412835 <6>[ 7.710736] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10730 18:02:23.423127 <3>[ 7.717384] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10731 18:02:23.426441 <6>[ 7.717513] remoteproc remoteproc0: scp is available
10732 18:02:23.434223 <6>[ 7.717648] remoteproc remoteproc0: powering up scp
10733 18:02:23.440873 <6>[ 7.717654] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10734 18:02:23.447912 <6>[ 7.717672] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10735 18:02:23.454522 <6>[ 7.725612] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10736 18:02:23.464888 <3>[ 7.730069] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10737 18:02:23.471298 <6>[ 7.739358] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10738 18:02:23.478300 <3>[ 7.753822] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10739 18:02:23.488016 <4>[ 7.756542] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10740 18:02:23.491493 <4>[ 7.756542] Fallback method does not support PEC.
10741 18:02:23.501136 <6>[ 7.761223] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10742 18:02:23.508370 <6>[ 7.761234] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10743 18:02:23.517867 <6>[ 7.761243] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10744 18:02:23.524387 <6>[ 7.764126] videodev: Linux video capture interface: v2.00
10745 18:02:23.531132 <3>[ 7.766873] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10746 18:02:23.541508 <3>[ 7.772619] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10747 18:02:23.548039 <3>[ 7.780670] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10748 18:02:23.554535 <6>[ 7.802520] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10749 18:02:23.564632 <3>[ 7.807798] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10750 18:02:23.571067 <3>[ 7.810049] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10751 18:02:23.581408 <3>[ 7.810053] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10752 18:02:23.587524 <3>[ 7.810098] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10753 18:02:23.597522 <6>[ 7.811977] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10754 18:02:23.604479 <6>[ 7.818140] pci_bus 0000:00: root bus resource [bus 00-ff]
10755 18:02:23.610808 <3>[ 7.831797] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10756 18:02:23.617534 <6>[ 7.839162] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10757 18:02:23.627766 <6>[ 7.839264] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10758 18:02:23.634236 <6>[ 7.839271] remoteproc remoteproc0: remote processor scp is now up
10759 18:02:23.641113 <6>[ 7.839584] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10760 18:02:23.647692 <3>[ 7.847400] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10761 18:02:23.657242 <6>[ 7.856516] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10762 18:02:23.667529 <6>[ 7.857842] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10763 18:02:23.677478 <6>[ 7.858192] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10764 18:02:23.683906 <3>[ 7.862251] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10765 18:02:23.690946 <6>[ 7.870379] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10766 18:02:23.700457 <6>[ 7.872215] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10767 18:02:23.707124 <6>[ 7.874100] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10768 18:02:23.717187 <3>[ 7.879152] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10769 18:02:23.723894 <6>[ 7.887194] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10770 18:02:23.730490 <3>[ 7.894063] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10771 18:02:23.737667 <6>[ 7.902914] pci 0000:00:00.0: supports D1 D2
10772 18:02:23.740624 <6>[ 7.903447] Bluetooth: Core ver 2.22
10773 18:02:23.747087 <6>[ 7.903563] NET: Registered PF_BLUETOOTH protocol family
10774 18:02:23.754021 <6>[ 7.903566] Bluetooth: HCI device and connection manager initialized
10775 18:02:23.757573 <6>[ 7.903596] Bluetooth: HCI socket layer initialized
10776 18:02:23.763811 <6>[ 7.903603] Bluetooth: L2CAP socket layer initialized
10777 18:02:23.767441 <6>[ 7.903614] Bluetooth: SCO socket layer initialized
10778 18:02:23.777512 <3>[ 7.911003] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10779 18:02:23.783696 <3>[ 7.911018] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10780 18:02:23.793877 <3>[ 7.911025] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10781 18:02:23.800242 <3>[ 7.911089] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10782 18:02:23.807337 <6>[ 7.919259] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10783 18:02:23.813969 <6>[ 7.928146] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10784 18:02:23.823357 <6>[ 7.938035] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10785 18:02:23.833730 <6>[ 7.943722] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10786 18:02:23.840206 <6>[ 7.950608] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10787 18:02:23.846859 <6>[ 7.958029] usbcore: registered new interface driver uvcvideo
10788 18:02:23.853396 <6>[ 7.966063] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10789 18:02:23.860443 <6>[ 7.967277] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10790 18:02:23.866569 <6>[ 7.980104] usbcore: registered new interface driver btusb
10791 18:02:23.876866 <4>[ 7.980630] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10792 18:02:23.883420 <3>[ 7.980639] Bluetooth: hci0: Failed to load firmware file (-2)
10793 18:02:23.890033 <3>[ 7.980643] Bluetooth: hci0: Failed to set up firmware (-2)
10794 18:02:23.899721 <4>[ 7.980646] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10795 18:02:23.906241 <6>[ 7.987687] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10796 18:02:23.916548 <6>[ 8.246272] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10797 18:02:23.919635 <6>[ 8.253849] pci 0000:01:00.0: supports D1 D2
10798 18:02:23.926042 <6>[ 8.258369] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10799 18:02:23.950460 <6>[ 8.281278] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10800 18:02:23.956955 <6>[ 8.288194] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10801 18:02:23.964157 <6>[ 8.296273] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10802 18:02:23.973647 <6>[ 8.304274] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10803 18:02:23.980149 <6>[ 8.312275] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10804 18:02:23.990862 <6>[ 8.320276] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10805 18:02:23.993810 <6>[ 8.328275] pci 0000:00:00.0: PCI bridge to [bus 01]
10806 18:02:24.003985 <6>[ 8.333492] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10807 18:02:24.010220 <6>[ 8.341612] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10808 18:02:24.014053 <6>[ 8.348421] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10809 18:02:24.020760 <6>[ 8.354956] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10810 18:02:24.042068 <5>[ 8.373116] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10811 18:02:24.061404 <5>[ 8.392494] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10812 18:02:24.068031 <5>[ 8.399999] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10813 18:02:24.078128 <4>[ 8.408478] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10814 18:02:24.084467 <6>[ 8.417382] cfg80211: failed to load regulatory.db
10815 18:02:24.140119 <6>[ 8.471093] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10816 18:02:24.146641 <6>[ 8.478641] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10817 18:02:24.171632 <6>[ 8.505683] mt7921e 0000:01:00.0: ASIC revision: 79610010
10818 18:02:24.274708 <6>[ 8.605696] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10819 18:02:24.278233 <6>[ 8.605696]
10820 18:02:24.286521 Begin: Loading essential drivers ... done.
10821 18:02:24.290181 Begin: Running /scripts/init-premount ... done.
10822 18:02:24.296721 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10823 18:02:24.306324 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10824 18:02:24.310097 Device /sys/class/net/eth0 found
10825 18:02:24.310237 done.
10826 18:02:24.316691 Begin: Waiting up to 180 secs for any network device to become available ... done.
10827 18:02:24.359017 IP-Config: eth0 hardware address 00:24:32:30:78:52 mtu 1500 DHCP
10828 18:02:24.365900 IP-Config: eth0 complete (dhcp from 192.168.201.1):
10829 18:02:24.372130 address: 192.168.201.14 broadcast: 192.168.201.255 netmask: 255.255.255.0
10830 18:02:24.379350 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10831 18:02:24.385853 host : mt8192-asurada-spherion-r0-cbg-3
10832 18:02:24.392367 domain : lava-rack
10833 18:02:24.395922 rootserver: 192.168.201.1 rootpath:
10834 18:02:24.398892 filename :
10835 18:02:24.543204 <6>[ 8.874244] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10836 18:02:24.543395 done.
10837 18:02:24.554265 Begin: Running /scripts/nfs-bottom ... done.
10838 18:02:24.573756 Begin: Running /scripts/init-bottom ... done.
10839 18:02:25.931173 <6>[ 10.265794] NET: Registered PF_INET6 protocol family
10840 18:02:25.938663 <6>[ 10.272833] Segment Routing with IPv6
10841 18:02:25.941606 <6>[ 10.276813] In-situ OAM (IOAM) with IPv6
10842 18:02:26.115688 <30>[ 10.423442] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10843 18:02:26.122438 <30>[ 10.456669] systemd[1]: Detected architecture arm64.
10844 18:02:26.131458
10845 18:02:26.134843 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10846 18:02:26.134980
10847 18:02:26.164487 <30>[ 10.498960] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10848 18:02:27.224558 <30>[ 11.555705] systemd[1]: Queued start job for default target graphical.target.
10849 18:02:27.271553 <30>[ 11.602579] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10850 18:02:27.277929 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10851 18:02:27.300298 <30>[ 11.631262] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10852 18:02:27.309750 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10853 18:02:27.327674 <30>[ 11.659146] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10854 18:02:27.338002 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10855 18:02:27.356370 <30>[ 11.687670] systemd[1]: Created slice user.slice - User and Session Slice.
10856 18:02:27.362938 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10857 18:02:27.386538 <30>[ 11.714319] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10858 18:02:27.396602 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10859 18:02:27.417604 <30>[ 11.745703] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10860 18:02:27.424634 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10861 18:02:27.453004 <30>[ 11.774056] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10862 18:02:27.462592 <30>[ 11.793947] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10863 18:02:27.469204 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10864 18:02:27.486731 <30>[ 11.817719] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10865 18:02:27.493298 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10866 18:02:27.514982 <30>[ 11.845982] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10867 18:02:27.524286 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10868 18:02:27.539060 <30>[ 11.873956] systemd[1]: Reached target paths.target - Path Units.
10869 18:02:27.549442 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10870 18:02:27.566693 <30>[ 11.897885] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10871 18:02:27.573451 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10872 18:02:27.586740 <30>[ 11.921426] systemd[1]: Reached target slices.target - Slice Units.
10873 18:02:27.596889 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10874 18:02:27.611205 <30>[ 11.945830] systemd[1]: Reached target swap.target - Swaps.
10875 18:02:27.618003 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10876 18:02:27.639035 <30>[ 11.969915] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10877 18:02:27.648966 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10878 18:02:27.666682 <30>[ 11.997891] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10879 18:02:27.676366 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10880 18:02:27.697909 <30>[ 12.028890] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10881 18:02:27.707549 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10882 18:02:27.723777 <30>[ 12.054904] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10883 18:02:27.733316 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10884 18:02:27.750831 <30>[ 12.082078] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10885 18:02:27.757380 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10886 18:02:27.775577 <30>[ 12.107037] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10887 18:02:27.785588 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10888 18:02:27.804876 <30>[ 12.136138] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10889 18:02:27.814666 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10890 18:02:27.831223 <30>[ 12.162486] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10891 18:02:27.841267 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10892 18:02:27.882018 <30>[ 12.213460] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10893 18:02:27.888867 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10894 18:02:27.910683 <30>[ 12.241876] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10895 18:02:27.917277 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10896 18:02:27.978915 <30>[ 12.309839] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10897 18:02:27.985271 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10898 18:02:28.013516 <30>[ 12.338049] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10899 18:02:28.028678 <30>[ 12.359853] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10900 18:02:28.038393 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10901 18:02:28.059359 <30>[ 12.390969] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10902 18:02:28.066489 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10903 18:02:28.090331 <30>[ 12.421371] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10904 18:02:28.096830 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10905 18:02:28.123453 <30>[ 12.454876] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10906 18:02:28.133602 Startin<6>[ 12.463995] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10907 18:02:28.140089 g [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10908 18:02:28.164019 <30>[ 12.495298] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10909 18:02:28.174116 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10910 18:02:28.195783 <30>[ 12.526997] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10911 18:02:28.202308 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10912 18:02:28.226065 <30>[ 12.557574] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10913 18:02:28.236182 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop..<6>[ 12.572178] fuse: init (API version 7.37)
10914 18:02:28.236318 .
10915 18:02:28.262342 <30>[ 12.593648] systemd[1]: Starting systemd-journald.service - Journal Service...
10916 18:02:28.268714 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10917 18:02:28.347300 <30>[ 12.678500] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10918 18:02:28.353653 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10919 18:02:28.385833 <30>[ 12.713754] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10920 18:02:28.392031 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10921 18:02:28.413517 <3>[ 12.744890] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10922 18:02:28.423548 <30>[ 12.746960] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10923 18:02:28.430742 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10924 18:02:28.446376 <3>[ 12.777585] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10925 18:02:28.460730 <30>[ 12.791665] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10926 18:02:28.466727 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10927 18:02:28.491708 <30>[ 12.822494] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
10928 18:02:28.501802 [[0;32m OK [0m] Mounted [0;<3>[ 12.832822] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10929 18:02:28.508554 1;39mdev-hugepages.mount[0m - Huge Pages File System.
10930 18:02:28.527318 <30>[ 12.858272] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
10931 18:02:28.534647 <3>[ 12.864651] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10932 18:02:28.544272 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10933 18:02:28.562829 <30>[ 12.894020] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
10934 18:02:28.569372 <3>[ 12.897532] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10935 18:02:28.579777 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10936 18:02:28.600079 <30>[ 12.930554] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
10937 18:02:28.609657 <3>[ 12.936039] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10938 18:02:28.616264 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10939 18:02:28.636050 <30>[ 12.967188] systemd[1]: modprobe@configfs.service: Deactivated successfully.
10940 18:02:28.642894 <3>[ 12.970826] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10941 18:02:28.652972 <30>[ 12.975483] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
10942 18:02:28.659731 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10943 18:02:28.677097 <3>[ 13.008265] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10944 18:02:28.687141 <30>[ 13.018312] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
10945 18:02:28.696964 <30>[ 13.026821] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
10946 18:02:28.704589 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10947 18:02:28.714255 <3>[ 13.044490] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10948 18:02:28.728038 <30>[ 13.059653] systemd[1]: modprobe@drm.service: Deactivated successfully.
10949 18:02:28.735793 <30>[ 13.067834] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
10950 18:02:28.748954 [[0;32m OK [0m] Finished [0;1;39mmodprobe@d<3>[ 13.078857] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10951 18:02:28.751980 rm.service[0m - Load Kernel Module drm.
10952 18:02:28.773504 <30>[ 13.104276] systemd[1]: modprobe@efi_pstore.service: Deactivated successfully.
10953 18:02:28.783371 <30>[ 13.112914] systemd[1]: Finished modprobe@efi_pstore.service - Load Kernel Module efi_pstore.
10954 18:02:28.789971 <3>[ 13.116756] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10955 18:02:28.800012 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10956 18:02:28.820736 <30>[ 13.151846] systemd[1]: modprobe@fuse.service: Deactivated successfully.
10957 18:02:28.827293 <30>[ 13.160084] systemd[1]: Finished modprobe@fuse.service - Load Kernel Module fuse.
10958 18:02:28.837442 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
10959 18:02:28.854718 <30>[ 13.186384] systemd[1]: Started systemd-journald.service - Journal Service.
10960 18:02:28.861519 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10961 18:02:28.883572 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10962 18:02:28.904286 <4>[ 13.228593] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10963 18:02:28.910835 <3>[ 13.244254] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10964 18:02:28.920613 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10965 18:02:28.941048 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10966 18:02:28.960009 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
10967 18:02:28.979700 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10968 18:02:29.001017 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10969 18:02:29.051286 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
10970 18:02:29.078079 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10971 18:02:29.103706 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10972 18:02:29.133806 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10973 18:02:29.163702 <46>[ 13.494929] systemd-journald[308]: Received client request to flush runtime journal.
10974 18:02:29.170156 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10975 18:02:29.204033 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10976 18:02:29.502552 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
10977 18:02:29.527242 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10978 18:02:29.547782 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10979 18:02:29.568529 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10980 18:02:30.574415 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10981 18:02:30.591501 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10982 18:02:30.655264 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10983 18:02:30.745108 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10984 18:02:30.762566 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10985 18:02:30.781917 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10986 18:02:30.835769 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10987 18:02:30.861072 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10988 18:02:31.080249 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10989 18:02:31.133160 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
10990 18:02:31.207292 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10991 18:02:31.394557 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10992 18:02:31.471834 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10993 18:02:31.503466 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10994 18:02:31.535607 <6>[ 15.869867] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10995 18:02:31.562733 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
10996 18:02:31.586674 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
10997 18:02:31.651893 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
10998 18:02:31.699111 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
10999 18:02:31.743689 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11000 18:02:31.768341 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
11001 18:02:31.798404 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11002 18:02:31.835837 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
11003 18:02:31.858347 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11004 18:02:31.878641 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
11005 18:02:31.885115 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
11006 18:02:31.906825 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
11007 18:02:31.926576 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
11008 18:02:31.945720 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
11009 18:02:31.971148 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
11010 18:02:31.993156 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
11011 18:02:32.009898 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
11012 18:02:32.029325 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
11013 18:02:32.072382 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
11014 18:02:32.090083 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
11015 18:02:32.107944 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
11016 18:02:32.125740 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
11017 18:02:32.141757 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
11018 18:02:32.191442 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11019 18:02:32.224689 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
11020 18:02:32.294526 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11021 18:02:32.326703 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11022 18:02:32.392940 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11023 18:02:32.452506 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11024 18:02:32.499753 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11025 18:02:32.522420 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11026 18:02:32.538484 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11027 18:02:32.576623 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11028 18:02:32.764012 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
11029 18:02:32.786711 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11030 18:02:32.810448 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11031 18:02:32.887380 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11032 18:02:32.932948 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11033 18:02:33.008414
11034 18:02:33.012037 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11035 18:02:33.012156
11036 18:02:33.015092 debian-bookworm-arm64 login: root (automatic login)
11037 18:02:33.015175
11038 18:02:33.291537 Linux debian-bookworm-arm64 6.1.92-cip22 #1 SMP PREEMPT Tue Jun 11 17:44:14 UTC 2024 aarch64
11039 18:02:33.291749
11040 18:02:33.297552 The programs included with the Debian GNU/Linux system are free software;
11041 18:02:33.304585 the exact distribution terms for each program are described in the
11042 18:02:33.307540 individual files in /usr/share/doc/*/copyright.
11043 18:02:33.307626
11044 18:02:33.314347 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11045 18:02:33.317888 permitted by applicable law.
11046 18:02:33.446979 Matched prompt #10: / #
11048 18:02:33.448084 Setting prompt string to ['/ #']
11049 18:02:33.448514 end: 2.2.5.1 login-action (duration 00:00:19) [common]
11051 18:02:33.449530 end: 2.2.5 auto-login-action (duration 00:00:19) [common]
11052 18:02:33.449967 start: 2.2.6 expect-shell-connection (timeout 00:03:18) [common]
11053 18:02:33.450318 Setting prompt string to ['/ #']
11054 18:02:33.450627 Forcing a shell prompt, looking for ['/ #']
11056 18:02:33.501432 / #
11057 18:02:33.502090 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11058 18:02:33.502534 Waiting using forced prompt support (timeout 00:02:30)
11059 18:02:33.507951
11060 18:02:33.508900 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11061 18:02:33.509492 start: 2.2.7 export-device-env (timeout 00:03:18) [common]
11063 18:02:33.610803 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14291394/extract-nfsrootfs-zajh3fwr'
11064 18:02:33.617553 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14291394/extract-nfsrootfs-zajh3fwr'
11066 18:02:33.719317 / # export NFS_SERVER_IP='192.168.201.1'
11067 18:02:33.726442 export NFS_SERVER_IP='192.168.201.1'
11068 18:02:33.727423 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11069 18:02:33.727991 end: 2.2 depthcharge-retry (duration 00:01:42) [common]
11070 18:02:33.728570 end: 2 depthcharge-action (duration 00:01:42) [common]
11071 18:02:33.729203 start: 3 lava-test-retry (timeout 00:01:00) [common]
11072 18:02:33.729760 start: 3.1 lava-test-shell (timeout 00:01:00) [common]
11073 18:02:33.730233 Using namespace: common
11075 18:02:33.831540 / # #
11076 18:02:33.831729 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
11077 18:02:33.836958 #
11078 18:02:33.837356 Using /lava-14291394
11080 18:02:33.938063 / # export SHELL=/bin/sh
11081 18:02:33.944747 export SHELL=/bin/sh
11083 18:02:34.046676 / # . /lava-14291394/environment
11084 18:02:34.053713 . /lava-14291394/environment
11086 18:02:34.162048 / # /lava-14291394/bin/lava-test-runner /lava-14291394/0
11087 18:02:34.162682 Test shell timeout: 10s (minimum of the action and connection timeout)
11088 18:02:34.168289 /lava-14291394/bin/lava-test-runner /lava-14291394/0
11089 18:02:34.448084 + export TESTRUN_ID=0_dmesg
11090 18:02:34.451330 + cd /lava-14291394/0/tests/0_dmesg
11091 18:02:34.454987 + cat uuid
11092 18:02:34.472734 + UUID=14291394_<8>[ 18.804663] <LAVA_SIGNAL_STARTRUN 0_dmesg 14291394_1.6.2.3.1>
11093 18:02:34.473240 1.6.2.3.1
11094 18:02:34.473593 + set +x
11095 18:02:34.474202 Received signal: <STARTRUN> 0_dmesg 14291394_1.6.2.3.1
11096 18:02:34.474550 Starting test lava.0_dmesg (14291394_1.6.2.3.1)
11097 18:02:34.474948 Skipping test definition patterns.
11098 18:02:34.479557 + KERNELCI_LAVA=y /bin/sh /opt/kernelci/dmesg.sh
11099 18:02:34.617839 <8>[ 18.949396] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0>
11100 18:02:34.618607 Received signal: <TESTCASE> TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0
11102 18:02:34.717104 <8>[ 19.048766] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0>
11103 18:02:34.717887 Received signal: <TESTCASE> TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0
11105 18:02:34.819628 <8>[ 19.151303] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0>
11106 18:02:34.820002 Received signal: <TESTCASE> TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0
11108 18:02:34.822657 + set +x
11109 18:02:34.826336 <8>[ 19.160724] <LAVA_SIGNAL_ENDRUN 0_dmesg 14291394_1.6.2.3.1>
11110 18:02:34.826597 Received signal: <ENDRUN> 0_dmesg 14291394_1.6.2.3.1
11111 18:02:34.826688 Ending use of test pattern.
11112 18:02:34.826763 Ending test lava.0_dmesg (14291394_1.6.2.3.1), duration 0.35
11114 18:02:34.834034 <LAVA_TEST_RUNNER EXIT>
11115 18:02:34.834729 ok: lava_test_shell seems to have completed
11116 18:02:34.835366 alert: pass
crit: pass
emerg: pass
11117 18:02:34.835844 end: 3.1 lava-test-shell (duration 00:00:01) [common]
11118 18:02:34.836338 end: 3 lava-test-retry (duration 00:00:01) [common]
11119 18:02:34.836878 start: 4 finalize (timeout 00:07:49) [common]
11120 18:02:34.837450 start: 4.1 power-off (timeout 00:00:30) [common]
11121 18:02:34.838292 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-3', '--port=1', '--command=off']
11122 18:02:34.956543 >> Command sent successfully.
11123 18:02:34.960258 Returned 0 in 0 seconds
11124 18:02:35.061241 end: 4.1 power-off (duration 00:00:00) [common]
11126 18:02:35.062865 start: 4.2 read-feedback (timeout 00:07:49) [common]
11127 18:02:35.064255 Listened to connection for namespace 'common' for up to 1s
11128 18:02:36.064939 Finalising connection for namespace 'common'
11129 18:02:36.065611 Disconnecting from shell: Finalise
11130 18:02:36.066141 / #
11131 18:02:36.167159 end: 4.2 read-feedback (duration 00:00:01) [common]
11132 18:02:36.167865 end: 4 finalize (duration 00:00:01) [common]
11133 18:02:36.168682 Cleaning after the job
11134 18:02:36.169454 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14291394/tftp-deploy-qqp_ono5/ramdisk
11135 18:02:36.181913 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14291394/tftp-deploy-qqp_ono5/kernel
11136 18:02:36.210339 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14291394/tftp-deploy-qqp_ono5/dtb
11137 18:02:36.210663 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14291394/tftp-deploy-qqp_ono5/nfsrootfs
11138 18:02:36.271085 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14291394/tftp-deploy-qqp_ono5/modules
11139 18:02:36.276554 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14291394
11140 18:02:36.595114 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14291394
11141 18:02:36.595289 Job finished correctly