Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 28
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 23
1 18:06:06.877041 lava-dispatcher, installed at version: 2024.03
2 18:06:06.877265 start: 0 validate
3 18:06:06.877401 Start time: 2024-06-11 18:06:06.877394+00:00 (UTC)
4 18:06:06.877521 Using caching service: 'http://localhost/cache/?uri=%s'
5 18:06:06.877644 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-igt%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 18:06:07.146139 Using caching service: 'http://localhost/cache/?uri=%s'
7 18:06:07.146315 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22-17-g24b63cdc814f%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 18:06:07.412675 Using caching service: 'http://localhost/cache/?uri=%s'
9 18:06:07.412855 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22-17-g24b63cdc814f%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 18:06:07.678513 Using caching service: 'http://localhost/cache/?uri=%s'
11 18:06:07.678675 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22-17-g24b63cdc814f%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 18:06:07.945992 validate duration: 1.07
14 18:06:07.946331 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 18:06:07.946463 start: 1.1 download-retry (timeout 00:10:00) [common]
16 18:06:07.946580 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 18:06:07.946717 Not decompressing ramdisk as can be used compressed.
18 18:06:07.946813 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-igt/20240313.0/arm64/rootfs.cpio.gz
19 18:06:07.946886 saving as /var/lib/lava/dispatcher/tmp/14291445/tftp-deploy-dii3sy_s/ramdisk/rootfs.cpio.gz
20 18:06:07.946957 total size: 47897469 (45 MB)
21 18:06:07.948145 progress 0 % (0 MB)
22 18:06:07.962201 progress 5 % (2 MB)
23 18:06:07.974317 progress 10 % (4 MB)
24 18:06:07.986436 progress 15 % (6 MB)
25 18:06:07.998555 progress 20 % (9 MB)
26 18:06:08.010722 progress 25 % (11 MB)
27 18:06:08.022870 progress 30 % (13 MB)
28 18:06:08.035078 progress 35 % (16 MB)
29 18:06:08.047137 progress 40 % (18 MB)
30 18:06:08.059329 progress 45 % (20 MB)
31 18:06:08.071469 progress 50 % (22 MB)
32 18:06:08.083560 progress 55 % (25 MB)
33 18:06:08.095894 progress 60 % (27 MB)
34 18:06:08.107976 progress 65 % (29 MB)
35 18:06:08.120147 progress 70 % (32 MB)
36 18:06:08.132360 progress 75 % (34 MB)
37 18:06:08.144570 progress 80 % (36 MB)
38 18:06:08.156641 progress 85 % (38 MB)
39 18:06:08.168790 progress 90 % (41 MB)
40 18:06:08.180734 progress 95 % (43 MB)
41 18:06:08.192583 progress 100 % (45 MB)
42 18:06:08.192801 45 MB downloaded in 0.25 s (185.80 MB/s)
43 18:06:08.192960 end: 1.1.1 http-download (duration 00:00:00) [common]
45 18:06:08.193231 end: 1.1 download-retry (duration 00:00:00) [common]
46 18:06:08.193318 start: 1.2 download-retry (timeout 00:10:00) [common]
47 18:06:08.193401 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 18:06:08.193535 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-17-g24b63cdc814f/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 18:06:08.193607 saving as /var/lib/lava/dispatcher/tmp/14291445/tftp-deploy-dii3sy_s/kernel/Image
50 18:06:08.193666 total size: 54813184 (52 MB)
51 18:06:08.193725 No compression specified
52 18:06:08.194879 progress 0 % (0 MB)
53 18:06:08.208649 progress 5 % (2 MB)
54 18:06:08.222582 progress 10 % (5 MB)
55 18:06:08.236368 progress 15 % (7 MB)
56 18:06:08.250393 progress 20 % (10 MB)
57 18:06:08.264553 progress 25 % (13 MB)
58 18:06:08.278356 progress 30 % (15 MB)
59 18:06:08.292326 progress 35 % (18 MB)
60 18:06:08.306337 progress 40 % (20 MB)
61 18:06:08.319970 progress 45 % (23 MB)
62 18:06:08.333860 progress 50 % (26 MB)
63 18:06:08.347651 progress 55 % (28 MB)
64 18:06:08.361352 progress 60 % (31 MB)
65 18:06:08.375425 progress 65 % (34 MB)
66 18:06:08.389190 progress 70 % (36 MB)
67 18:06:08.403051 progress 75 % (39 MB)
68 18:06:08.416971 progress 80 % (41 MB)
69 18:06:08.430715 progress 85 % (44 MB)
70 18:06:08.444543 progress 90 % (47 MB)
71 18:06:08.458334 progress 95 % (49 MB)
72 18:06:08.471794 progress 100 % (52 MB)
73 18:06:08.472042 52 MB downloaded in 0.28 s (187.78 MB/s)
74 18:06:08.472210 end: 1.2.1 http-download (duration 00:00:00) [common]
76 18:06:08.472473 end: 1.2 download-retry (duration 00:00:00) [common]
77 18:06:08.472575 start: 1.3 download-retry (timeout 00:09:59) [common]
78 18:06:08.472675 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 18:06:08.472823 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-17-g24b63cdc814f/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 18:06:08.472902 saving as /var/lib/lava/dispatcher/tmp/14291445/tftp-deploy-dii3sy_s/dtb/mt8192-asurada-spherion-r0.dtb
81 18:06:08.473043 total size: 47258 (0 MB)
82 18:06:08.473144 No compression specified
83 18:06:08.474837 progress 69 % (0 MB)
84 18:06:08.475139 progress 100 % (0 MB)
85 18:06:08.475331 0 MB downloaded in 0.00 s (19.72 MB/s)
86 18:06:08.475472 end: 1.3.1 http-download (duration 00:00:00) [common]
88 18:06:08.475718 end: 1.3 download-retry (duration 00:00:00) [common]
89 18:06:08.475842 start: 1.4 download-retry (timeout 00:09:59) [common]
90 18:06:08.475965 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 18:06:08.476118 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-17-g24b63cdc814f/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 18:06:08.476216 saving as /var/lib/lava/dispatcher/tmp/14291445/tftp-deploy-dii3sy_s/modules/modules.tar
93 18:06:08.476314 total size: 8618176 (8 MB)
94 18:06:08.476414 Using unxz to decompress xz
95 18:06:08.480722 progress 0 % (0 MB)
96 18:06:08.499600 progress 5 % (0 MB)
97 18:06:08.526973 progress 10 % (0 MB)
98 18:06:08.557256 progress 15 % (1 MB)
99 18:06:08.581667 progress 20 % (1 MB)
100 18:06:08.605059 progress 25 % (2 MB)
101 18:06:08.628318 progress 30 % (2 MB)
102 18:06:08.654292 progress 35 % (2 MB)
103 18:06:08.678866 progress 40 % (3 MB)
104 18:06:08.701580 progress 45 % (3 MB)
105 18:06:08.725085 progress 50 % (4 MB)
106 18:06:08.749696 progress 55 % (4 MB)
107 18:06:08.773818 progress 60 % (4 MB)
108 18:06:08.797905 progress 65 % (5 MB)
109 18:06:08.824376 progress 70 % (5 MB)
110 18:06:08.847764 progress 75 % (6 MB)
111 18:06:08.873367 progress 80 % (6 MB)
112 18:06:08.897753 progress 85 % (7 MB)
113 18:06:08.923112 progress 90 % (7 MB)
114 18:06:08.948457 progress 95 % (7 MB)
115 18:06:08.975176 progress 100 % (8 MB)
116 18:06:08.979538 8 MB downloaded in 0.50 s (16.33 MB/s)
117 18:06:08.979780 end: 1.4.1 http-download (duration 00:00:01) [common]
119 18:06:08.980041 end: 1.4 download-retry (duration 00:00:01) [common]
120 18:06:08.980135 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 18:06:08.980230 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 18:06:08.980313 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 18:06:08.980400 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 18:06:08.980636 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14291445/lava-overlay-iyenjuq7
125 18:06:08.980767 makedir: /var/lib/lava/dispatcher/tmp/14291445/lava-overlay-iyenjuq7/lava-14291445/bin
126 18:06:08.980872 makedir: /var/lib/lava/dispatcher/tmp/14291445/lava-overlay-iyenjuq7/lava-14291445/tests
127 18:06:08.980970 makedir: /var/lib/lava/dispatcher/tmp/14291445/lava-overlay-iyenjuq7/lava-14291445/results
128 18:06:08.981133 Creating /var/lib/lava/dispatcher/tmp/14291445/lava-overlay-iyenjuq7/lava-14291445/bin/lava-add-keys
129 18:06:08.981279 Creating /var/lib/lava/dispatcher/tmp/14291445/lava-overlay-iyenjuq7/lava-14291445/bin/lava-add-sources
130 18:06:08.981413 Creating /var/lib/lava/dispatcher/tmp/14291445/lava-overlay-iyenjuq7/lava-14291445/bin/lava-background-process-start
131 18:06:08.981545 Creating /var/lib/lava/dispatcher/tmp/14291445/lava-overlay-iyenjuq7/lava-14291445/bin/lava-background-process-stop
132 18:06:08.981674 Creating /var/lib/lava/dispatcher/tmp/14291445/lava-overlay-iyenjuq7/lava-14291445/bin/lava-common-functions
133 18:06:08.981800 Creating /var/lib/lava/dispatcher/tmp/14291445/lava-overlay-iyenjuq7/lava-14291445/bin/lava-echo-ipv4
134 18:06:08.981927 Creating /var/lib/lava/dispatcher/tmp/14291445/lava-overlay-iyenjuq7/lava-14291445/bin/lava-install-packages
135 18:06:08.982052 Creating /var/lib/lava/dispatcher/tmp/14291445/lava-overlay-iyenjuq7/lava-14291445/bin/lava-installed-packages
136 18:06:08.982177 Creating /var/lib/lava/dispatcher/tmp/14291445/lava-overlay-iyenjuq7/lava-14291445/bin/lava-os-build
137 18:06:08.982304 Creating /var/lib/lava/dispatcher/tmp/14291445/lava-overlay-iyenjuq7/lava-14291445/bin/lava-probe-channel
138 18:06:08.982427 Creating /var/lib/lava/dispatcher/tmp/14291445/lava-overlay-iyenjuq7/lava-14291445/bin/lava-probe-ip
139 18:06:08.982552 Creating /var/lib/lava/dispatcher/tmp/14291445/lava-overlay-iyenjuq7/lava-14291445/bin/lava-target-ip
140 18:06:08.982687 Creating /var/lib/lava/dispatcher/tmp/14291445/lava-overlay-iyenjuq7/lava-14291445/bin/lava-target-mac
141 18:06:08.982816 Creating /var/lib/lava/dispatcher/tmp/14291445/lava-overlay-iyenjuq7/lava-14291445/bin/lava-target-storage
142 18:06:08.982944 Creating /var/lib/lava/dispatcher/tmp/14291445/lava-overlay-iyenjuq7/lava-14291445/bin/lava-test-case
143 18:06:08.983069 Creating /var/lib/lava/dispatcher/tmp/14291445/lava-overlay-iyenjuq7/lava-14291445/bin/lava-test-event
144 18:06:08.983193 Creating /var/lib/lava/dispatcher/tmp/14291445/lava-overlay-iyenjuq7/lava-14291445/bin/lava-test-feedback
145 18:06:08.983317 Creating /var/lib/lava/dispatcher/tmp/14291445/lava-overlay-iyenjuq7/lava-14291445/bin/lava-test-raise
146 18:06:08.983441 Creating /var/lib/lava/dispatcher/tmp/14291445/lava-overlay-iyenjuq7/lava-14291445/bin/lava-test-reference
147 18:06:08.983565 Creating /var/lib/lava/dispatcher/tmp/14291445/lava-overlay-iyenjuq7/lava-14291445/bin/lava-test-runner
148 18:06:08.983690 Creating /var/lib/lava/dispatcher/tmp/14291445/lava-overlay-iyenjuq7/lava-14291445/bin/lava-test-set
149 18:06:08.983817 Creating /var/lib/lava/dispatcher/tmp/14291445/lava-overlay-iyenjuq7/lava-14291445/bin/lava-test-shell
150 18:06:08.983945 Updating /var/lib/lava/dispatcher/tmp/14291445/lava-overlay-iyenjuq7/lava-14291445/bin/lava-install-packages (oe)
151 18:06:08.984097 Updating /var/lib/lava/dispatcher/tmp/14291445/lava-overlay-iyenjuq7/lava-14291445/bin/lava-installed-packages (oe)
152 18:06:08.984224 Creating /var/lib/lava/dispatcher/tmp/14291445/lava-overlay-iyenjuq7/lava-14291445/environment
153 18:06:08.984328 LAVA metadata
154 18:06:08.984402 - LAVA_JOB_ID=14291445
155 18:06:08.984468 - LAVA_DISPATCHER_IP=192.168.201.1
156 18:06:08.984566 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 18:06:08.984634 skipped lava-vland-overlay
158 18:06:08.984708 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 18:06:08.984789 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 18:06:08.984863 skipped lava-multinode-overlay
161 18:06:08.984936 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 18:06:08.985065 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 18:06:08.985138 Loading test definitions
164 18:06:08.985227 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 18:06:08.985299 Using /lava-14291445 at stage 0
166 18:06:08.985622 uuid=14291445_1.5.2.3.1 testdef=None
167 18:06:08.985713 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 18:06:08.985797 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 18:06:08.986308 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 18:06:08.986532 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 18:06:08.987144 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 18:06:08.987374 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 18:06:08.987965 runner path: /var/lib/lava/dispatcher/tmp/14291445/lava-overlay-iyenjuq7/lava-14291445/0/tests/0_igt-gpu-panfrost test_uuid 14291445_1.5.2.3.1
176 18:06:08.988125 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 18:06:08.988331 Creating lava-test-runner.conf files
179 18:06:08.988395 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14291445/lava-overlay-iyenjuq7/lava-14291445/0 for stage 0
180 18:06:08.988484 - 0_igt-gpu-panfrost
181 18:06:08.988580 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 18:06:08.988667 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 18:06:08.995911 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 18:06:08.996016 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 18:06:08.996102 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 18:06:08.996188 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 18:06:08.996274 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 18:06:10.761156 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:02) [common]
189 18:06:10.761526 start: 1.5.4 extract-modules (timeout 00:09:57) [common]
190 18:06:10.761640 extracting modules file /var/lib/lava/dispatcher/tmp/14291445/tftp-deploy-dii3sy_s/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14291445/extract-overlay-ramdisk-90mgm_0g/ramdisk
191 18:06:10.983162 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 18:06:10.983344 start: 1.5.5 apply-overlay-tftp (timeout 00:09:57) [common]
193 18:06:10.983434 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14291445/compress-overlay-05fq_zfr/overlay-1.5.2.4.tar.gz to ramdisk
194 18:06:10.983504 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14291445/compress-overlay-05fq_zfr/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14291445/extract-overlay-ramdisk-90mgm_0g/ramdisk
195 18:06:10.990292 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 18:06:10.990420 start: 1.5.6 configure-preseed-file (timeout 00:09:57) [common]
197 18:06:10.990514 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 18:06:10.990604 start: 1.5.7 compress-ramdisk (timeout 00:09:57) [common]
199 18:06:10.990685 Building ramdisk /var/lib/lava/dispatcher/tmp/14291445/extract-overlay-ramdisk-90mgm_0g/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14291445/extract-overlay-ramdisk-90mgm_0g/ramdisk
200 18:06:12.248482 >> 465983 blocks
201 18:06:18.590384 rename /var/lib/lava/dispatcher/tmp/14291445/extract-overlay-ramdisk-90mgm_0g/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14291445/tftp-deploy-dii3sy_s/ramdisk/ramdisk.cpio.gz
202 18:06:18.590828 end: 1.5.7 compress-ramdisk (duration 00:00:08) [common]
203 18:06:18.590950 start: 1.5.8 prepare-kernel (timeout 00:09:49) [common]
204 18:06:18.591051 start: 1.5.8.1 prepare-fit (timeout 00:09:49) [common]
205 18:06:18.591159 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14291445/tftp-deploy-dii3sy_s/kernel/Image']
206 18:06:31.891714 Returned 0 in 13 seconds
207 18:06:31.992349 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14291445/tftp-deploy-dii3sy_s/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14291445/tftp-deploy-dii3sy_s/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14291445/tftp-deploy-dii3sy_s/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14291445/tftp-deploy-dii3sy_s/kernel/image.itb
208 18:06:32.846968 output: FIT description: Kernel Image image with one or more FDT blobs
209 18:06:32.847323 output: Created: Tue Jun 11 19:06:32 2024
210 18:06:32.847426 output: Image 0 (kernel-1)
211 18:06:32.847512 output: Description:
212 18:06:32.847594 output: Created: Tue Jun 11 19:06:32 2024
213 18:06:32.847676 output: Type: Kernel Image
214 18:06:32.847761 output: Compression: lzma compressed
215 18:06:32.847843 output: Data Size: 13125101 Bytes = 12817.48 KiB = 12.52 MiB
216 18:06:32.847944 output: Architecture: AArch64
217 18:06:32.848043 output: OS: Linux
218 18:06:32.848142 output: Load Address: 0x00000000
219 18:06:32.848241 output: Entry Point: 0x00000000
220 18:06:32.848339 output: Hash algo: crc32
221 18:06:32.848436 output: Hash value: 7a9e9d3e
222 18:06:32.848529 output: Image 1 (fdt-1)
223 18:06:32.848623 output: Description: mt8192-asurada-spherion-r0
224 18:06:32.848719 output: Created: Tue Jun 11 19:06:32 2024
225 18:06:32.848816 output: Type: Flat Device Tree
226 18:06:32.848908 output: Compression: uncompressed
227 18:06:32.849038 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
228 18:06:32.849129 output: Architecture: AArch64
229 18:06:32.849223 output: Hash algo: crc32
230 18:06:32.849332 output: Hash value: 0f8e4d2e
231 18:06:32.849431 output: Image 2 (ramdisk-1)
232 18:06:32.849525 output: Description: unavailable
233 18:06:32.849610 output: Created: Tue Jun 11 19:06:32 2024
234 18:06:32.849693 output: Type: RAMDisk Image
235 18:06:32.849776 output: Compression: Unknown Compression
236 18:06:32.849859 output: Data Size: 61001459 Bytes = 59571.74 KiB = 58.18 MiB
237 18:06:32.849942 output: Architecture: AArch64
238 18:06:32.850024 output: OS: Linux
239 18:06:32.850106 output: Load Address: unavailable
240 18:06:32.850188 output: Entry Point: unavailable
241 18:06:32.850270 output: Hash algo: crc32
242 18:06:32.850352 output: Hash value: 8e29706c
243 18:06:32.850434 output: Default Configuration: 'conf-1'
244 18:06:32.850516 output: Configuration 0 (conf-1)
245 18:06:32.850598 output: Description: mt8192-asurada-spherion-r0
246 18:06:32.850680 output: Kernel: kernel-1
247 18:06:32.850762 output: Init Ramdisk: ramdisk-1
248 18:06:32.850843 output: FDT: fdt-1
249 18:06:32.850925 output: Loadables: kernel-1
250 18:06:32.851007 output:
251 18:06:32.851251 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
252 18:06:32.851382 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
253 18:06:32.851516 end: 1.5 prepare-tftp-overlay (duration 00:00:24) [common]
254 18:06:32.851642 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:35) [common]
255 18:06:32.851749 No LXC device requested
256 18:06:32.851860 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 18:06:32.852015 start: 1.7 deploy-device-env (timeout 00:09:35) [common]
258 18:06:32.852121 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 18:06:32.852219 Checking files for TFTP limit of 4294967296 bytes.
260 18:06:32.852890 end: 1 tftp-deploy (duration 00:00:25) [common]
261 18:06:32.853072 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 18:06:32.853168 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 18:06:32.853296 substitutions:
264 18:06:32.853363 - {DTB}: 14291445/tftp-deploy-dii3sy_s/dtb/mt8192-asurada-spherion-r0.dtb
265 18:06:32.853428 - {INITRD}: 14291445/tftp-deploy-dii3sy_s/ramdisk/ramdisk.cpio.gz
266 18:06:32.853488 - {KERNEL}: 14291445/tftp-deploy-dii3sy_s/kernel/Image
267 18:06:32.853547 - {LAVA_MAC}: None
268 18:06:32.853605 - {PRESEED_CONFIG}: None
269 18:06:32.853660 - {PRESEED_LOCAL}: None
270 18:06:32.853715 - {RAMDISK}: 14291445/tftp-deploy-dii3sy_s/ramdisk/ramdisk.cpio.gz
271 18:06:32.853771 - {ROOT_PART}: None
272 18:06:32.853826 - {ROOT}: None
273 18:06:32.853881 - {SERVER_IP}: 192.168.201.1
274 18:06:32.853935 - {TEE}: None
275 18:06:32.853989 Parsed boot commands:
276 18:06:32.854042 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 18:06:32.854218 Parsed boot commands: tftpboot 192.168.201.1 14291445/tftp-deploy-dii3sy_s/kernel/image.itb 14291445/tftp-deploy-dii3sy_s/kernel/cmdline
278 18:06:32.854308 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 18:06:32.854395 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 18:06:32.854483 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 18:06:32.854575 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 18:06:32.854646 Not connected, no need to disconnect.
283 18:06:32.854731 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 18:06:32.854814 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 18:06:32.854881 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-3'
286 18:06:32.858764 Setting prompt string to ['lava-test: # ']
287 18:06:32.859331 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 18:06:32.859446 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 18:06:32.859598 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 18:06:32.859726 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 18:06:32.859958 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-3', '--port=1', '--command=reboot']
292 18:06:37.996601 >> Command sent successfully.
293 18:06:37.999770 Returned 0 in 5 seconds
294 18:06:38.100200 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 18:06:38.100702 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 18:06:38.100853 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 18:06:38.101013 Setting prompt string to 'Starting depthcharge on Spherion...'
299 18:06:38.101139 Changing prompt to 'Starting depthcharge on Spherion...'
300 18:06:38.101250 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 18:06:38.101854 [Enter `^Ec?' for help]
302 18:06:38.273044
303 18:06:38.273244
304 18:06:38.273365 F0: 102B 0000
305 18:06:38.273470
306 18:06:38.273571 F3: 1001 0000 [0200]
307 18:06:38.273674
308 18:06:38.276069 F3: 1001 0000
309 18:06:38.276184
310 18:06:38.276285 F7: 102D 0000
311 18:06:38.276393
312 18:06:38.276492 F1: 0000 0000
313 18:06:38.279897
314 18:06:38.280024 V0: 0000 0000 [0001]
315 18:06:38.280132
316 18:06:38.280233 00: 0007 8000
317 18:06:38.280340
318 18:06:38.283617 01: 0000 0000
319 18:06:38.283743
320 18:06:38.283846 BP: 0C00 0209 [0000]
321 18:06:38.283944
322 18:06:38.287591 G0: 1182 0000
323 18:06:38.287717
324 18:06:38.287822 EC: 0000 0021 [4000]
325 18:06:38.287926
326 18:06:38.290651 S7: 0000 0000 [0000]
327 18:06:38.290756
328 18:06:38.290824 CC: 0000 0000 [0001]
329 18:06:38.290886
330 18:06:38.294062 T0: 0000 0040 [010F]
331 18:06:38.294142
332 18:06:38.294204 Jump to BL
333 18:06:38.294263
334 18:06:38.319252
335 18:06:38.319407
336 18:06:38.326889 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
337 18:06:38.330453 ARM64: Exception handlers installed.
338 18:06:38.334516 ARM64: Testing exception
339 18:06:38.338103 ARM64: Done test exception
340 18:06:38.342012 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
341 18:06:38.353465 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
342 18:06:38.360237 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
343 18:06:38.370244 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
344 18:06:38.376628 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
345 18:06:38.386990 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
346 18:06:38.398021 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
347 18:06:38.403969 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
348 18:06:38.422147 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
349 18:06:38.425320 WDT: Last reset was cold boot
350 18:06:38.428942 SPI1(PAD0) initialized at 2873684 Hz
351 18:06:38.432295 SPI5(PAD0) initialized at 992727 Hz
352 18:06:38.435573 VBOOT: Loading verstage.
353 18:06:38.442171 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
354 18:06:38.445797 FMAP: Found "FLASH" version 1.1 at 0x20000.
355 18:06:38.449022 FMAP: base = 0x0 size = 0x800000 #areas = 25
356 18:06:38.452095 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
357 18:06:38.459825 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
358 18:06:38.466249 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
359 18:06:38.477211 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
360 18:06:38.477378
361 18:06:38.477482
362 18:06:38.487145 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
363 18:06:38.491034 ARM64: Exception handlers installed.
364 18:06:38.493808 ARM64: Testing exception
365 18:06:38.493904 ARM64: Done test exception
366 18:06:38.500510 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
367 18:06:38.504825 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
368 18:06:38.518126 Probing TPM: . done!
369 18:06:38.518278 TPM ready after 0 ms
370 18:06:38.526239 Connected to device vid:did:rid of 1ae0:0028:00
371 18:06:38.532401 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
372 18:06:38.590120 Initialized TPM device CR50 revision 0
373 18:06:38.601313 tlcl_send_startup: Startup return code is 0
374 18:06:38.601485 TPM: setup succeeded
375 18:06:38.613328 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
376 18:06:38.621832 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
377 18:06:38.634738 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
378 18:06:38.643133 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
379 18:06:38.646586 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
380 18:06:38.653595 in-header: 03 07 00 00 08 00 00 00
381 18:06:38.656915 in-data: aa e4 47 04 13 02 00 00
382 18:06:38.660792 Chrome EC: UHEPI supported
383 18:06:38.667866 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
384 18:06:38.672016 in-header: 03 ad 00 00 08 00 00 00
385 18:06:38.672152 in-data: 00 20 20 08 00 00 00 00
386 18:06:38.675740 Phase 1
387 18:06:38.679492 FMAP: area GBB found @ 3f5000 (12032 bytes)
388 18:06:38.682961 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
389 18:06:38.690289 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
390 18:06:38.694286 Recovery requested (1009000e)
391 18:06:38.702270 TPM: Extending digest for VBOOT: boot mode into PCR 0
392 18:06:38.707465 tlcl_extend: response is 0
393 18:06:38.717069 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
394 18:06:38.722441 tlcl_extend: response is 0
395 18:06:38.729512 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
396 18:06:38.749452 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
397 18:06:38.755866 BS: bootblock times (exec / console): total (unknown) / 148 ms
398 18:06:38.756001
399 18:06:38.756086
400 18:06:38.766609 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
401 18:06:38.770213 ARM64: Exception handlers installed.
402 18:06:38.770331 ARM64: Testing exception
403 18:06:38.773725 ARM64: Done test exception
404 18:06:38.794294 pmic_efuse_setting: Set efuses in 11 msecs
405 18:06:38.798345 pmwrap_interface_init: Select PMIF_VLD_RDY
406 18:06:38.804944 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
407 18:06:38.808537 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
408 18:06:38.814823 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
409 18:06:38.818951 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
410 18:06:38.823016 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
411 18:06:38.826409 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
412 18:06:38.834154 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
413 18:06:38.837343 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
414 18:06:38.841334 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
415 18:06:38.845580 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
416 18:06:38.852954 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
417 18:06:38.856449 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
418 18:06:38.860659 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
419 18:06:38.867989 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
420 18:06:38.871904 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
421 18:06:38.879397 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
422 18:06:38.882423 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
423 18:06:38.890119 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
424 18:06:38.894174 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
425 18:06:38.901301 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
426 18:06:38.904900 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
427 18:06:38.912159 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
428 18:06:38.919373 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
429 18:06:38.923718 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
430 18:06:38.927513 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
431 18:06:38.934566 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
432 18:06:38.938446 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
433 18:06:38.945633 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
434 18:06:38.949210 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
435 18:06:38.952665 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
436 18:06:38.960644 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
437 18:06:38.964420 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
438 18:06:38.967549 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
439 18:06:38.974939 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
440 18:06:38.979234 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
441 18:06:38.982467 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
442 18:06:38.990485 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
443 18:06:38.993987 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
444 18:06:38.997757 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
445 18:06:39.001635 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
446 18:06:39.008948 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
447 18:06:39.012445 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
448 18:06:39.015676 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
449 18:06:39.019578 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
450 18:06:39.023532 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
451 18:06:39.027589 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
452 18:06:39.034592 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
453 18:06:39.038730 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
454 18:06:39.041909 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
455 18:06:39.046203 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
456 18:06:39.049538 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
457 18:06:39.057026 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
458 18:06:39.064415 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
459 18:06:39.072139 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
460 18:06:39.079120 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
461 18:06:39.086696 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
462 18:06:39.090263 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
463 18:06:39.097836 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
464 18:06:39.101754 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 18:06:39.109284 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x34
466 18:06:39.112659 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
467 18:06:39.119648 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
468 18:06:39.123276 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
469 18:06:39.132079 [RTC]rtc_get_frequency_meter,154: input=15, output=790
470 18:06:39.142289 [RTC]rtc_get_frequency_meter,154: input=23, output=977
471 18:06:39.151336 [RTC]rtc_get_frequency_meter,154: input=19, output=884
472 18:06:39.160574 [RTC]rtc_get_frequency_meter,154: input=17, output=836
473 18:06:39.170400 [RTC]rtc_get_frequency_meter,154: input=16, output=813
474 18:06:39.179455 [RTC]rtc_get_frequency_meter,154: input=15, output=790
475 18:06:39.189874 [RTC]rtc_get_frequency_meter,154: input=16, output=813
476 18:06:39.194037 [RTC]rtc_eosc_cali,47: left: 15, middle: 15, right: 16
477 18:06:39.197573 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
478 18:06:39.201456 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
479 18:06:39.208539 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
480 18:06:39.212169 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
481 18:06:39.216200 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
482 18:06:39.219316 ADC[4]: Raw value=901697 ID=7
483 18:06:39.219435 ADC[3]: Raw value=213336 ID=1
484 18:06:39.223390 RAM Code: 0x71
485 18:06:39.226944 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
486 18:06:39.230772 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
487 18:06:39.241756 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
488 18:06:39.245389 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
489 18:06:39.248933 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
490 18:06:39.252649 in-header: 03 07 00 00 08 00 00 00
491 18:06:39.256223 in-data: aa e4 47 04 13 02 00 00
492 18:06:39.260127 Chrome EC: UHEPI supported
493 18:06:39.267723 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
494 18:06:39.271598 in-header: 03 ed 00 00 08 00 00 00
495 18:06:39.271738 in-data: 80 20 60 08 00 00 00 00
496 18:06:39.274900 MRC: failed to locate region type 0.
497 18:06:39.282704 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
498 18:06:39.285759 DRAM-K: Running full calibration
499 18:06:39.293448 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
500 18:06:39.293596 header.status = 0x0
501 18:06:39.297180 header.version = 0x6 (expected: 0x6)
502 18:06:39.300946 header.size = 0xd00 (expected: 0xd00)
503 18:06:39.301091 header.flags = 0x0
504 18:06:39.307862 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
505 18:06:39.326316 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
506 18:06:39.334268 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
507 18:06:39.334422 dram_init: ddr_geometry: 2
508 18:06:39.338155 [EMI] MDL number = 2
509 18:06:39.338278 [EMI] Get MDL freq = 0
510 18:06:39.341929 dram_init: ddr_type: 0
511 18:06:39.345817 is_discrete_lpddr4: 1
512 18:06:39.345972 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
513 18:06:39.346079
514 18:06:39.346146
515 18:06:39.349551 [Bian_co] ETT version 0.0.0.1
516 18:06:39.352532 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
517 18:06:39.356622
518 18:06:39.360099 dramc_set_vcore_voltage set vcore to 650000
519 18:06:39.360209 Read voltage for 800, 4
520 18:06:39.363049 Vio18 = 0
521 18:06:39.363147 Vcore = 650000
522 18:06:39.363215 Vdram = 0
523 18:06:39.363278 Vddq = 0
524 18:06:39.366678 Vmddr = 0
525 18:06:39.366767 dram_init: config_dvfs: 1
526 18:06:39.373195 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
527 18:06:39.379872 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
528 18:06:39.383402 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=10
529 18:06:39.387064 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=10
530 18:06:39.389865 [SwImpedanceCal] DRVP=12, DRVN=25, ODTN=9
531 18:06:39.393332 freq_region=1, Reg: DRVP=12, DRVN=25, ODTN=9
532 18:06:39.396616 MEM_TYPE=3, freq_sel=18
533 18:06:39.399985 sv_algorithm_assistance_LP4_1600
534 18:06:39.403527 ============ PULL DRAM RESETB DOWN ============
535 18:06:39.406723 ========== PULL DRAM RESETB DOWN end =========
536 18:06:39.413642 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
537 18:06:39.417169 ===================================
538 18:06:39.417290 LPDDR4 DRAM CONFIGURATION
539 18:06:39.420204 ===================================
540 18:06:39.423401 EX_ROW_EN[0] = 0x0
541 18:06:39.423504 EX_ROW_EN[1] = 0x0
542 18:06:39.427262 LP4Y_EN = 0x0
543 18:06:39.427359 WORK_FSP = 0x0
544 18:06:39.429858 WL = 0x2
545 18:06:39.429978 RL = 0x2
546 18:06:39.433191 BL = 0x2
547 18:06:39.433274 RPST = 0x0
548 18:06:39.436707 RD_PRE = 0x0
549 18:06:39.439965 WR_PRE = 0x1
550 18:06:39.440069 WR_PST = 0x0
551 18:06:39.443214 DBI_WR = 0x0
552 18:06:39.443346 DBI_RD = 0x0
553 18:06:39.446639 OTF = 0x1
554 18:06:39.450072 ===================================
555 18:06:39.453376 ===================================
556 18:06:39.453548 ANA top config
557 18:06:39.456894 ===================================
558 18:06:39.461096 DLL_ASYNC_EN = 0
559 18:06:39.461226 ALL_SLAVE_EN = 1
560 18:06:39.463647 NEW_RANK_MODE = 1
561 18:06:39.466728 DLL_IDLE_MODE = 1
562 18:06:39.471028 LP45_APHY_COMB_EN = 1
563 18:06:39.473723 TX_ODT_DIS = 1
564 18:06:39.473819 NEW_8X_MODE = 1
565 18:06:39.477266 ===================================
566 18:06:39.480257 ===================================
567 18:06:39.483883 data_rate = 1600
568 18:06:39.486893 CKR = 1
569 18:06:39.490902 DQ_P2S_RATIO = 8
570 18:06:39.493625 ===================================
571 18:06:39.497235 CA_P2S_RATIO = 8
572 18:06:39.497338 DQ_CA_OPEN = 0
573 18:06:39.500469 DQ_SEMI_OPEN = 0
574 18:06:39.503885 CA_SEMI_OPEN = 0
575 18:06:39.507493 CA_FULL_RATE = 0
576 18:06:39.510527 DQ_CKDIV4_EN = 1
577 18:06:39.513683 CA_CKDIV4_EN = 1
578 18:06:39.513852 CA_PREDIV_EN = 0
579 18:06:39.517387 PH8_DLY = 0
580 18:06:39.520987 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
581 18:06:39.523960 DQ_AAMCK_DIV = 4
582 18:06:39.527105 CA_AAMCK_DIV = 4
583 18:06:39.527270 CA_ADMCK_DIV = 4
584 18:06:39.530760 DQ_TRACK_CA_EN = 0
585 18:06:39.534283 CA_PICK = 800
586 18:06:39.537510 CA_MCKIO = 800
587 18:06:39.540728 MCKIO_SEMI = 0
588 18:06:39.544374 PLL_FREQ = 3068
589 18:06:39.547819 DQ_UI_PI_RATIO = 32
590 18:06:39.547981 CA_UI_PI_RATIO = 0
591 18:06:39.551585 ===================================
592 18:06:39.555345 ===================================
593 18:06:39.558888 memory_type:LPDDR4
594 18:06:39.559058 GP_NUM : 10
595 18:06:39.562740 SRAM_EN : 1
596 18:06:39.562907 MD32_EN : 0
597 18:06:39.566109 ===================================
598 18:06:39.570081 [ANA_INIT] >>>>>>>>>>>>>>
599 18:06:39.573533 <<<<<< [CONFIGURE PHASE]: ANA_TX
600 18:06:39.576922 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
601 18:06:39.581503 ===================================
602 18:06:39.581696 data_rate = 1600,PCW = 0X7600
603 18:06:39.584490 ===================================
604 18:06:39.587578 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
605 18:06:39.594968 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
606 18:06:39.601000 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 18:06:39.604328 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
608 18:06:39.607736 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
609 18:06:39.611167 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
610 18:06:39.614317 [ANA_INIT] flow start
611 18:06:39.614418 [ANA_INIT] PLL >>>>>>>>
612 18:06:39.617729 [ANA_INIT] PLL <<<<<<<<
613 18:06:39.620837 [ANA_INIT] MIDPI >>>>>>>>
614 18:06:39.620988 [ANA_INIT] MIDPI <<<<<<<<
615 18:06:39.624309 [ANA_INIT] DLL >>>>>>>>
616 18:06:39.627808 [ANA_INIT] flow end
617 18:06:39.631493 ============ LP4 DIFF to SE enter ============
618 18:06:39.634582 ============ LP4 DIFF to SE exit ============
619 18:06:39.638042 [ANA_INIT] <<<<<<<<<<<<<
620 18:06:39.641456 [Flow] Enable top DCM control >>>>>
621 18:06:39.644605 [Flow] Enable top DCM control <<<<<
622 18:06:39.647880 Enable DLL master slave shuffle
623 18:06:39.651644 ==============================================================
624 18:06:39.655404 Gating Mode config
625 18:06:39.661773 ==============================================================
626 18:06:39.661903 Config description:
627 18:06:39.671096 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
628 18:06:39.678423 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
629 18:06:39.681605 SELPH_MODE 0: By rank 1: By Phase
630 18:06:39.688343 ==============================================================
631 18:06:39.691792 GAT_TRACK_EN = 1
632 18:06:39.695121 RX_GATING_MODE = 2
633 18:06:39.698604 RX_GATING_TRACK_MODE = 2
634 18:06:39.701344 SELPH_MODE = 1
635 18:06:39.704647 PICG_EARLY_EN = 1
636 18:06:39.704768 VALID_LAT_VALUE = 1
637 18:06:39.711528 ==============================================================
638 18:06:39.715673 Enter into Gating configuration >>>>
639 18:06:39.718561 Exit from Gating configuration <<<<
640 18:06:39.721753 Enter into DVFS_PRE_config >>>>>
641 18:06:39.731868 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
642 18:06:39.735635 Exit from DVFS_PRE_config <<<<<
643 18:06:39.738482 Enter into PICG configuration >>>>
644 18:06:39.742095 Exit from PICG configuration <<<<
645 18:06:39.745704 [RX_INPUT] configuration >>>>>
646 18:06:39.748842 [RX_INPUT] configuration <<<<<
647 18:06:39.751692 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
648 18:06:39.758689 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
649 18:06:39.765762 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
650 18:06:39.769525 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
651 18:06:39.775746 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
652 18:06:39.782735 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
653 18:06:39.786258 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
654 18:06:39.789616 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
655 18:06:39.796250 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
656 18:06:39.799299 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
657 18:06:39.802669 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
658 18:06:39.809513 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
659 18:06:39.809665 ===================================
660 18:06:39.812872 LPDDR4 DRAM CONFIGURATION
661 18:06:39.816565 ===================================
662 18:06:39.820005 EX_ROW_EN[0] = 0x0
663 18:06:39.820156 EX_ROW_EN[1] = 0x0
664 18:06:39.823407 LP4Y_EN = 0x0
665 18:06:39.823565 WORK_FSP = 0x0
666 18:06:39.826073 WL = 0x2
667 18:06:39.826184 RL = 0x2
668 18:06:39.829659 BL = 0x2
669 18:06:39.829791 RPST = 0x0
670 18:06:39.832747 RD_PRE = 0x0
671 18:06:39.832864 WR_PRE = 0x1
672 18:06:39.836672 WR_PST = 0x0
673 18:06:39.836831 DBI_WR = 0x0
674 18:06:39.840343 DBI_RD = 0x0
675 18:06:39.840466 OTF = 0x1
676 18:06:39.842896 ===================================
677 18:06:39.849516 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
678 18:06:39.853247 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
679 18:06:39.856682 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
680 18:06:39.860129 ===================================
681 18:06:39.863418 LPDDR4 DRAM CONFIGURATION
682 18:06:39.866531 ===================================
683 18:06:39.869650 EX_ROW_EN[0] = 0x10
684 18:06:39.869790 EX_ROW_EN[1] = 0x0
685 18:06:39.873503 LP4Y_EN = 0x0
686 18:06:39.873638 WORK_FSP = 0x0
687 18:06:39.876417 WL = 0x2
688 18:06:39.876542 RL = 0x2
689 18:06:39.879619 BL = 0x2
690 18:06:39.879757 RPST = 0x0
691 18:06:39.883469 RD_PRE = 0x0
692 18:06:39.883598 WR_PRE = 0x1
693 18:06:39.886361 WR_PST = 0x0
694 18:06:39.886471 DBI_WR = 0x0
695 18:06:39.889792 DBI_RD = 0x0
696 18:06:39.889922 OTF = 0x1
697 18:06:39.893164 ===================================
698 18:06:39.899739 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
699 18:06:39.904270 nWR fixed to 40
700 18:06:39.907277 [ModeRegInit_LP4] CH0 RK0
701 18:06:39.907419 [ModeRegInit_LP4] CH0 RK1
702 18:06:39.910676 [ModeRegInit_LP4] CH1 RK0
703 18:06:39.914255 [ModeRegInit_LP4] CH1 RK1
704 18:06:39.914403 match AC timing 13
705 18:06:39.921235 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
706 18:06:39.924337 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
707 18:06:39.928277 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
708 18:06:39.934451 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
709 18:06:39.937526 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
710 18:06:39.937646 [EMI DOE] emi_dcm 0
711 18:06:39.944555 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
712 18:06:39.944713 ==
713 18:06:39.947892 Dram Type= 6, Freq= 0, CH_0, rank 0
714 18:06:39.951536 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
715 18:06:39.951691 ==
716 18:06:39.958338 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
717 18:06:39.961311 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
718 18:06:39.971652 [CA 0] Center 37 (7~68) winsize 62
719 18:06:39.975108 [CA 1] Center 37 (6~68) winsize 63
720 18:06:39.978712 [CA 2] Center 35 (5~66) winsize 62
721 18:06:39.981731 [CA 3] Center 34 (4~65) winsize 62
722 18:06:39.984910 [CA 4] Center 34 (4~65) winsize 62
723 18:06:39.989280 [CA 5] Center 33 (3~64) winsize 62
724 18:06:39.989435
725 18:06:39.991835 [CmdBusTrainingLP45] Vref(ca) range 1: 34
726 18:06:39.991960
727 18:06:39.995194 [CATrainingPosCal] consider 1 rank data
728 18:06:39.998714 u2DelayCellTimex100 = 270/100 ps
729 18:06:40.001795 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
730 18:06:40.005276 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
731 18:06:40.008449 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
732 18:06:40.015373 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
733 18:06:40.018781 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
734 18:06:40.022130 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
735 18:06:40.022242
736 18:06:40.025448 CA PerBit enable=1, Macro0, CA PI delay=33
737 18:06:40.025555
738 18:06:40.028811 [CBTSetCACLKResult] CA Dly = 33
739 18:06:40.028946 CS Dly: 5 (0~36)
740 18:06:40.029039 ==
741 18:06:40.031945 Dram Type= 6, Freq= 0, CH_0, rank 1
742 18:06:40.038875 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
743 18:06:40.039036 ==
744 18:06:40.042524 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
745 18:06:40.048942 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
746 18:06:40.057996 [CA 0] Center 37 (6~68) winsize 63
747 18:06:40.061562 [CA 1] Center 37 (7~68) winsize 62
748 18:06:40.064587 [CA 2] Center 35 (4~66) winsize 63
749 18:06:40.067914 [CA 3] Center 35 (4~66) winsize 63
750 18:06:40.071504 [CA 4] Center 34 (3~65) winsize 63
751 18:06:40.074709 [CA 5] Center 33 (3~64) winsize 62
752 18:06:40.074842
753 18:06:40.078164 [CmdBusTrainingLP45] Vref(ca) range 1: 34
754 18:06:40.078317
755 18:06:40.082060 [CATrainingPosCal] consider 2 rank data
756 18:06:40.085082 u2DelayCellTimex100 = 270/100 ps
757 18:06:40.088052 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
758 18:06:40.091951 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
759 18:06:40.094902 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
760 18:06:40.101819 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
761 18:06:40.105099 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
762 18:06:40.108378 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
763 18:06:40.108561
764 18:06:40.111880 CA PerBit enable=1, Macro0, CA PI delay=33
765 18:06:40.112008
766 18:06:40.114952 [CBTSetCACLKResult] CA Dly = 33
767 18:06:40.115040 CS Dly: 5 (0~37)
768 18:06:40.115105
769 18:06:40.118430 ----->DramcWriteLeveling(PI) begin...
770 18:06:40.118532 ==
771 18:06:40.121975 Dram Type= 6, Freq= 0, CH_0, rank 0
772 18:06:40.128896 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
773 18:06:40.129123 ==
774 18:06:40.129197 Write leveling (Byte 0): 30 => 30
775 18:06:40.132625 Write leveling (Byte 1): 29 => 29
776 18:06:40.136238 DramcWriteLeveling(PI) end<-----
777 18:06:40.136492
778 18:06:40.136660 ==
779 18:06:40.139894 Dram Type= 6, Freq= 0, CH_0, rank 0
780 18:06:40.143854 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
781 18:06:40.144100 ==
782 18:06:40.147439 [Gating] SW mode calibration
783 18:06:40.153661 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
784 18:06:40.161098 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
785 18:06:40.165274 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
786 18:06:40.168407 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
787 18:06:40.171538 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
788 18:06:40.178203 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
789 18:06:40.181356 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 18:06:40.184958 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 18:06:40.191264 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 18:06:40.194878 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 18:06:40.198460 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 18:06:40.201966 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 18:06:40.208335 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 18:06:40.211651 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 18:06:40.215012 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 18:06:40.222053 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 18:06:40.225487 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 18:06:40.228446 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 18:06:40.235407 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 18:06:40.238496 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 18:06:40.241926 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 1)
804 18:06:40.248481 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
805 18:06:40.252445 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 18:06:40.255188 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 18:06:40.261915 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 18:06:40.265334 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 18:06:40.268751 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 18:06:40.272147 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 18:06:40.278915 0 9 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
812 18:06:40.282344 0 9 12 | B1->B0 | 2a2a 3333 | 1 1 | (1 1) (1 1)
813 18:06:40.285328 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
814 18:06:40.292616 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 18:06:40.295364 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 18:06:40.298607 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 18:06:40.305361 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 18:06:40.308704 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 18:06:40.312153 0 10 8 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 0)
820 18:06:40.318871 0 10 12 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
821 18:06:40.322164 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 18:06:40.325610 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 18:06:40.332221 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 18:06:40.335540 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 18:06:40.338844 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 18:06:40.342384 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 18:06:40.349217 0 11 8 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
828 18:06:40.352458 0 11 12 | B1->B0 | 3636 4040 | 0 0 | (0 0) (0 0)
829 18:06:40.355907 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
830 18:06:40.362685 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 18:06:40.365902 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 18:06:40.369460 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 18:06:40.376078 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 18:06:40.379507 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 18:06:40.382805 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
836 18:06:40.389117 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
837 18:06:40.392839 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 18:06:40.395923 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 18:06:40.399244 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 18:06:40.406126 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 18:06:40.409390 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 18:06:40.412794 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 18:06:40.419711 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 18:06:40.422698 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 18:06:40.426595 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 18:06:40.432961 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 18:06:40.436297 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 18:06:40.439510 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 18:06:40.446682 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 18:06:40.449774 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 18:06:40.453074 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
852 18:06:40.459929 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
853 18:06:40.463322 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
854 18:06:40.466855 Total UI for P1: 0, mck2ui 16
855 18:06:40.470064 best dqsien dly found for B0: ( 0, 14, 10)
856 18:06:40.473380 Total UI for P1: 0, mck2ui 16
857 18:06:40.476936 best dqsien dly found for B1: ( 0, 14, 10)
858 18:06:40.479770 best DQS0 dly(MCK, UI, PI) = (0, 14, 10)
859 18:06:40.483534 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
860 18:06:40.483684
861 18:06:40.486650 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 10)
862 18:06:40.490293 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
863 18:06:40.493483 [Gating] SW calibration Done
864 18:06:40.493611 ==
865 18:06:40.496501 Dram Type= 6, Freq= 0, CH_0, rank 0
866 18:06:40.499945 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
867 18:06:40.500068 ==
868 18:06:40.503890 RX Vref Scan: 0
869 18:06:40.503990
870 18:06:40.504058 RX Vref 0 -> 0, step: 1
871 18:06:40.504121
872 18:06:40.506733 RX Delay -130 -> 252, step: 16
873 18:06:40.513522 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
874 18:06:40.516763 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
875 18:06:40.520281 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
876 18:06:40.523481 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
877 18:06:40.527019 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
878 18:06:40.530273 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
879 18:06:40.536916 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
880 18:06:40.540461 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
881 18:06:40.543688 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
882 18:06:40.546763 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
883 18:06:40.550655 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
884 18:06:40.557198 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
885 18:06:40.560322 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
886 18:06:40.563698 iDelay=222, Bit 13, Center 77 (-34 ~ 189) 224
887 18:06:40.567061 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
888 18:06:40.570525 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
889 18:06:40.573843 ==
890 18:06:40.573983 Dram Type= 6, Freq= 0, CH_0, rank 0
891 18:06:40.580956 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
892 18:06:40.581090 ==
893 18:06:40.581168 DQS Delay:
894 18:06:40.583984 DQS0 = 0, DQS1 = 0
895 18:06:40.584086 DQM Delay:
896 18:06:40.584157 DQM0 = 83, DQM1 = 75
897 18:06:40.587454 DQ Delay:
898 18:06:40.590666 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =85
899 18:06:40.594118 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =85
900 18:06:40.597906 DQ8 =69, DQ9 =69, DQ10 =69, DQ11 =69
901 18:06:40.600815 DQ12 =77, DQ13 =77, DQ14 =85, DQ15 =85
902 18:06:40.600925
903 18:06:40.601023
904 18:06:40.601089 ==
905 18:06:40.603991 Dram Type= 6, Freq= 0, CH_0, rank 0
906 18:06:40.607542 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
907 18:06:40.607659 ==
908 18:06:40.607731
909 18:06:40.607794
910 18:06:40.610901 TX Vref Scan disable
911 18:06:40.611001 == TX Byte 0 ==
912 18:06:40.617217 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
913 18:06:40.620438 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
914 18:06:40.620582 == TX Byte 1 ==
915 18:06:40.627767 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
916 18:06:40.631016 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
917 18:06:40.631147 ==
918 18:06:40.634444 Dram Type= 6, Freq= 0, CH_0, rank 0
919 18:06:40.637495 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
920 18:06:40.637619 ==
921 18:06:40.651688 TX Vref=22, minBit 5, minWin=27, winSum=439
922 18:06:40.655039 TX Vref=24, minBit 12, minWin=27, winSum=447
923 18:06:40.658303 TX Vref=26, minBit 5, minWin=27, winSum=448
924 18:06:40.661764 TX Vref=28, minBit 3, minWin=27, winSum=450
925 18:06:40.664579 TX Vref=30, minBit 1, minWin=28, winSum=453
926 18:06:40.668005 TX Vref=32, minBit 1, minWin=28, winSum=451
927 18:06:40.674881 [TxChooseVref] Worse bit 1, Min win 28, Win sum 453, Final Vref 30
928 18:06:40.675058
929 18:06:40.678436 Final TX Range 1 Vref 30
930 18:06:40.678574
931 18:06:40.678686 ==
932 18:06:40.681903 Dram Type= 6, Freq= 0, CH_0, rank 0
933 18:06:40.685262 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 18:06:40.685398 ==
935 18:06:40.685512
936 18:06:40.685622
937 18:06:40.688698 TX Vref Scan disable
938 18:06:40.691871 == TX Byte 0 ==
939 18:06:40.695166 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
940 18:06:40.698516 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
941 18:06:40.702074 == TX Byte 1 ==
942 18:06:40.705383 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
943 18:06:40.708684 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
944 18:06:40.708845
945 18:06:40.712588 [DATLAT]
946 18:06:40.712766 Freq=800, CH0 RK0
947 18:06:40.712908
948 18:06:40.715594 DATLAT Default: 0xa
949 18:06:40.715735 0, 0xFFFF, sum = 0
950 18:06:40.718981 1, 0xFFFF, sum = 0
951 18:06:40.719145 2, 0xFFFF, sum = 0
952 18:06:40.722500 3, 0xFFFF, sum = 0
953 18:06:40.722678 4, 0xFFFF, sum = 0
954 18:06:40.725743 5, 0xFFFF, sum = 0
955 18:06:40.725914 6, 0xFFFF, sum = 0
956 18:06:40.728811 7, 0xFFFF, sum = 0
957 18:06:40.729024 8, 0xFFFF, sum = 0
958 18:06:40.732534 9, 0x0, sum = 1
959 18:06:40.732733 10, 0x0, sum = 2
960 18:06:40.735825 11, 0x0, sum = 3
961 18:06:40.736030 12, 0x0, sum = 4
962 18:06:40.738632 best_step = 10
963 18:06:40.738800
964 18:06:40.738932 ==
965 18:06:40.742681 Dram Type= 6, Freq= 0, CH_0, rank 0
966 18:06:40.745527 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
967 18:06:40.745705 ==
968 18:06:40.745880 RX Vref Scan: 1
969 18:06:40.749113
970 18:06:40.749281 Set Vref Range= 32 -> 127
971 18:06:40.749422
972 18:06:40.752030 RX Vref 32 -> 127, step: 1
973 18:06:40.752183
974 18:06:40.755577 RX Delay -95 -> 252, step: 8
975 18:06:40.755772
976 18:06:40.758881 Set Vref, RX VrefLevel [Byte0]: 32
977 18:06:40.762625 [Byte1]: 32
978 18:06:40.762828
979 18:06:40.766369 Set Vref, RX VrefLevel [Byte0]: 33
980 18:06:40.769514 [Byte1]: 33
981 18:06:40.769653
982 18:06:40.772970 Set Vref, RX VrefLevel [Byte0]: 34
983 18:06:40.776282 [Byte1]: 34
984 18:06:40.779364
985 18:06:40.779534 Set Vref, RX VrefLevel [Byte0]: 35
986 18:06:40.782816 [Byte1]: 35
987 18:06:40.787015
988 18:06:40.787178 Set Vref, RX VrefLevel [Byte0]: 36
989 18:06:40.790546 [Byte1]: 36
990 18:06:40.795048
991 18:06:40.795201 Set Vref, RX VrefLevel [Byte0]: 37
992 18:06:40.798397 [Byte1]: 37
993 18:06:40.803136
994 18:06:40.803291 Set Vref, RX VrefLevel [Byte0]: 38
995 18:06:40.805790 [Byte1]: 38
996 18:06:40.810117
997 18:06:40.810290 Set Vref, RX VrefLevel [Byte0]: 39
998 18:06:40.813790 [Byte1]: 39
999 18:06:40.818256
1000 18:06:40.818439 Set Vref, RX VrefLevel [Byte0]: 40
1001 18:06:40.821715 [Byte1]: 40
1002 18:06:40.825764
1003 18:06:40.825942 Set Vref, RX VrefLevel [Byte0]: 41
1004 18:06:40.829033 [Byte1]: 41
1005 18:06:40.832649
1006 18:06:40.832820 Set Vref, RX VrefLevel [Byte0]: 42
1007 18:06:40.836511 [Byte1]: 42
1008 18:06:40.840450
1009 18:06:40.840634 Set Vref, RX VrefLevel [Byte0]: 43
1010 18:06:40.843722 [Byte1]: 43
1011 18:06:40.848288
1012 18:06:40.848476 Set Vref, RX VrefLevel [Byte0]: 44
1013 18:06:40.851006 [Byte1]: 44
1014 18:06:40.856015
1015 18:06:40.856205 Set Vref, RX VrefLevel [Byte0]: 45
1016 18:06:40.859083 [Byte1]: 45
1017 18:06:40.862955
1018 18:06:40.863139 Set Vref, RX VrefLevel [Byte0]: 46
1019 18:06:40.866433 [Byte1]: 46
1020 18:06:40.870809
1021 18:06:40.871009 Set Vref, RX VrefLevel [Byte0]: 47
1022 18:06:40.874183 [Byte1]: 47
1023 18:06:40.878308
1024 18:06:40.878479 Set Vref, RX VrefLevel [Byte0]: 48
1025 18:06:40.881847 [Byte1]: 48
1026 18:06:40.885811
1027 18:06:40.885977 Set Vref, RX VrefLevel [Byte0]: 49
1028 18:06:40.889030 [Byte1]: 49
1029 18:06:40.893336
1030 18:06:40.893520 Set Vref, RX VrefLevel [Byte0]: 50
1031 18:06:40.896856 [Byte1]: 50
1032 18:06:40.901224
1033 18:06:40.901339 Set Vref, RX VrefLevel [Byte0]: 51
1034 18:06:40.904259 [Byte1]: 51
1035 18:06:40.908605
1036 18:06:40.908718 Set Vref, RX VrefLevel [Byte0]: 52
1037 18:06:40.912283 [Byte1]: 52
1038 18:06:40.915970
1039 18:06:40.916074 Set Vref, RX VrefLevel [Byte0]: 53
1040 18:06:40.919234 [Byte1]: 53
1041 18:06:40.923777
1042 18:06:40.923944 Set Vref, RX VrefLevel [Byte0]: 54
1043 18:06:40.926855 [Byte1]: 54
1044 18:06:40.931191
1045 18:06:40.931293 Set Vref, RX VrefLevel [Byte0]: 55
1046 18:06:40.934646 [Byte1]: 55
1047 18:06:40.938960
1048 18:06:40.939076 Set Vref, RX VrefLevel [Byte0]: 56
1049 18:06:40.942341 [Byte1]: 56
1050 18:06:40.946635
1051 18:06:40.946742 Set Vref, RX VrefLevel [Byte0]: 57
1052 18:06:40.950153 [Byte1]: 57
1053 18:06:40.954293
1054 18:06:40.954396 Set Vref, RX VrefLevel [Byte0]: 58
1055 18:06:40.957862 [Byte1]: 58
1056 18:06:40.961914
1057 18:06:40.962014 Set Vref, RX VrefLevel [Byte0]: 59
1058 18:06:40.965203 [Byte1]: 59
1059 18:06:40.969769
1060 18:06:40.969904 Set Vref, RX VrefLevel [Byte0]: 60
1061 18:06:40.972646 [Byte1]: 60
1062 18:06:40.976612
1063 18:06:40.976730 Set Vref, RX VrefLevel [Byte0]: 61
1064 18:06:40.980492 [Byte1]: 61
1065 18:06:40.984522
1066 18:06:40.984629 Set Vref, RX VrefLevel [Byte0]: 62
1067 18:06:40.988031 [Byte1]: 62
1068 18:06:40.992072
1069 18:06:40.992205 Set Vref, RX VrefLevel [Byte0]: 63
1070 18:06:40.995276 [Byte1]: 63
1071 18:06:40.999601
1072 18:06:40.999720 Set Vref, RX VrefLevel [Byte0]: 64
1073 18:06:41.003309 [Byte1]: 64
1074 18:06:41.007473
1075 18:06:41.007636 Set Vref, RX VrefLevel [Byte0]: 65
1076 18:06:41.010774 [Byte1]: 65
1077 18:06:41.015040
1078 18:06:41.015177 Set Vref, RX VrefLevel [Byte0]: 66
1079 18:06:41.018308 [Byte1]: 66
1080 18:06:41.022156
1081 18:06:41.022284 Set Vref, RX VrefLevel [Byte0]: 67
1082 18:06:41.025732 [Byte1]: 67
1083 18:06:41.029971
1084 18:06:41.030075 Set Vref, RX VrefLevel [Byte0]: 68
1085 18:06:41.033195 [Byte1]: 68
1086 18:06:41.037374
1087 18:06:41.037528 Set Vref, RX VrefLevel [Byte0]: 69
1088 18:06:41.040968 [Byte1]: 69
1089 18:06:41.044961
1090 18:06:41.045128 Set Vref, RX VrefLevel [Byte0]: 70
1091 18:06:41.048737 [Byte1]: 70
1092 18:06:41.053393
1093 18:06:41.053571 Set Vref, RX VrefLevel [Byte0]: 71
1094 18:06:41.056170 [Byte1]: 71
1095 18:06:41.060750
1096 18:06:41.060879 Set Vref, RX VrefLevel [Byte0]: 72
1097 18:06:41.064149 [Byte1]: 72
1098 18:06:41.067894
1099 18:06:41.068016 Set Vref, RX VrefLevel [Byte0]: 73
1100 18:06:41.071560 [Byte1]: 73
1101 18:06:41.075599
1102 18:06:41.075723 Set Vref, RX VrefLevel [Byte0]: 74
1103 18:06:41.078822 [Byte1]: 74
1104 18:06:41.083116
1105 18:06:41.083215 Set Vref, RX VrefLevel [Byte0]: 75
1106 18:06:41.086545 [Byte1]: 75
1107 18:06:41.090585
1108 18:06:41.090689 Set Vref, RX VrefLevel [Byte0]: 76
1109 18:06:41.094494 [Byte1]: 76
1110 18:06:41.098391
1111 18:06:41.098518 Final RX Vref Byte 0 = 60 to rank0
1112 18:06:41.101837 Final RX Vref Byte 1 = 60 to rank0
1113 18:06:41.104936 Final RX Vref Byte 0 = 60 to rank1
1114 18:06:41.108065 Final RX Vref Byte 1 = 60 to rank1==
1115 18:06:41.111567 Dram Type= 6, Freq= 0, CH_0, rank 0
1116 18:06:41.115282 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1117 18:06:41.118405 ==
1118 18:06:41.118538 DQS Delay:
1119 18:06:41.118635 DQS0 = 0, DQS1 = 0
1120 18:06:41.122037 DQM Delay:
1121 18:06:41.122130 DQM0 = 87, DQM1 = 78
1122 18:06:41.125170 DQ Delay:
1123 18:06:41.125261 DQ0 =88, DQ1 =92, DQ2 =84, DQ3 =84
1124 18:06:41.128780 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =96
1125 18:06:41.132036 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =72
1126 18:06:41.135283 DQ12 =84, DQ13 =80, DQ14 =88, DQ15 =88
1127 18:06:41.135377
1128 18:06:41.139088
1129 18:06:41.145525 [DQSOSCAuto] RK0, (LSB)MR18= 0x280f, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 399 ps
1130 18:06:41.148468 CH0 RK0: MR19=606, MR18=280F
1131 18:06:41.155301 CH0_RK0: MR19=0x606, MR18=0x280F, DQSOSC=399, MR23=63, INC=92, DEC=61
1132 18:06:41.155422
1133 18:06:41.158496 ----->DramcWriteLeveling(PI) begin...
1134 18:06:41.158618 ==
1135 18:06:41.162303 Dram Type= 6, Freq= 0, CH_0, rank 1
1136 18:06:41.165210 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1137 18:06:41.165303 ==
1138 18:06:41.168815 Write leveling (Byte 0): 29 => 29
1139 18:06:41.172192 Write leveling (Byte 1): 29 => 29
1140 18:06:41.175455 DramcWriteLeveling(PI) end<-----
1141 18:06:41.175549
1142 18:06:41.175615 ==
1143 18:06:41.178876 Dram Type= 6, Freq= 0, CH_0, rank 1
1144 18:06:41.182167 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1145 18:06:41.182261 ==
1146 18:06:41.185748 [Gating] SW mode calibration
1147 18:06:41.192344 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1148 18:06:41.198605 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1149 18:06:41.202069 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1150 18:06:41.205436 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1151 18:06:41.249735 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1152 18:06:41.250083 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1153 18:06:41.250679 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1154 18:06:41.250762 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1155 18:06:41.251014 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 18:06:41.251267 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 18:06:41.251346 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 18:06:41.252165 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 18:06:41.252248 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 18:06:41.252921 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 18:06:41.256591 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 18:06:41.259834 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 18:06:41.263424 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 18:06:41.266447 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 18:06:41.273606 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 18:06:41.276363 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1167 18:06:41.280140 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
1168 18:06:41.286317 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 18:06:41.289536 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 18:06:41.293490 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 18:06:41.300256 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 18:06:41.303309 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 18:06:41.306681 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 18:06:41.309977 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 18:06:41.317250 0 9 8 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (0 0)
1176 18:06:41.320857 0 9 12 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
1177 18:06:41.323635 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1178 18:06:41.330045 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1179 18:06:41.333188 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1180 18:06:41.336737 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1181 18:06:41.343396 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1182 18:06:41.346986 0 10 4 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
1183 18:06:41.350097 0 10 8 | B1->B0 | 3030 2323 | 1 0 | (1 0) (1 0)
1184 18:06:41.356883 0 10 12 | B1->B0 | 2525 2323 | 1 0 | (1 0) (0 0)
1185 18:06:41.360531 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 18:06:41.364162 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 18:06:41.370443 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 18:06:41.373782 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 18:06:41.377596 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 18:06:41.380914 0 11 4 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
1191 18:06:41.384909 0 11 8 | B1->B0 | 2c2c 4343 | 1 0 | (0 0) (0 0)
1192 18:06:41.392446 0 11 12 | B1->B0 | 3d3c 4646 | 1 0 | (1 1) (0 0)
1193 18:06:41.395426 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1194 18:06:41.399174 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1195 18:06:41.402101 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1196 18:06:41.409203 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1197 18:06:41.413212 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1198 18:06:41.415875 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1199 18:06:41.422597 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1200 18:06:41.425963 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1201 18:06:41.429587 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1202 18:06:41.436575 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 18:06:41.439514 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 18:06:41.443133 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 18:06:41.446517 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 18:06:41.452667 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 18:06:41.456322 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 18:06:41.459919 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 18:06:41.466314 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 18:06:41.469362 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 18:06:41.472956 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 18:06:41.479581 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 18:06:41.482922 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 18:06:41.486514 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1215 18:06:41.493338 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1216 18:06:41.493456 Total UI for P1: 0, mck2ui 16
1217 18:06:41.499682 best dqsien dly found for B0: ( 0, 14, 4)
1218 18:06:41.503037 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1219 18:06:41.506464 Total UI for P1: 0, mck2ui 16
1220 18:06:41.510044 best dqsien dly found for B1: ( 0, 14, 8)
1221 18:06:41.512791 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1222 18:06:41.516317 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1223 18:06:41.516411
1224 18:06:41.519953 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1225 18:06:41.522839 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1226 18:06:41.526204 [Gating] SW calibration Done
1227 18:06:41.526301 ==
1228 18:06:41.529754 Dram Type= 6, Freq= 0, CH_0, rank 1
1229 18:06:41.532758 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1230 18:06:41.532873 ==
1231 18:06:41.536155 RX Vref Scan: 0
1232 18:06:41.536242
1233 18:06:41.540127 RX Vref 0 -> 0, step: 1
1234 18:06:41.540233
1235 18:06:41.540335 RX Delay -130 -> 252, step: 16
1236 18:06:41.546099 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1237 18:06:41.549617 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1238 18:06:41.553099 iDelay=206, Bit 2, Center 85 (-34 ~ 205) 240
1239 18:06:41.556617 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1240 18:06:41.559618 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1241 18:06:41.566238 iDelay=206, Bit 5, Center 69 (-50 ~ 189) 240
1242 18:06:41.569566 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1243 18:06:41.573173 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1244 18:06:41.576560 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1245 18:06:41.579954 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1246 18:06:41.586381 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1247 18:06:41.589944 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1248 18:06:41.593207 iDelay=206, Bit 12, Center 69 (-50 ~ 189) 240
1249 18:06:41.596509 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1250 18:06:41.599881 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1251 18:06:41.606529 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1252 18:06:41.606651 ==
1253 18:06:41.609995 Dram Type= 6, Freq= 0, CH_0, rank 1
1254 18:06:41.613160 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1255 18:06:41.613260 ==
1256 18:06:41.613329 DQS Delay:
1257 18:06:41.616857 DQS0 = 0, DQS1 = 0
1258 18:06:41.616949 DQM Delay:
1259 18:06:41.620300 DQM0 = 85, DQM1 = 75
1260 18:06:41.620390 DQ Delay:
1261 18:06:41.623494 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
1262 18:06:41.627017 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
1263 18:06:41.629872 DQ8 =69, DQ9 =69, DQ10 =69, DQ11 =69
1264 18:06:41.633407 DQ12 =69, DQ13 =85, DQ14 =85, DQ15 =85
1265 18:06:41.633501
1266 18:06:41.633568
1267 18:06:41.633630 ==
1268 18:06:41.637240 Dram Type= 6, Freq= 0, CH_0, rank 1
1269 18:06:41.640544 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1270 18:06:41.640652 ==
1271 18:06:41.640722
1272 18:06:41.640783
1273 18:06:41.643692 TX Vref Scan disable
1274 18:06:41.646808 == TX Byte 0 ==
1275 18:06:41.649925 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1276 18:06:41.654118 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1277 18:06:41.657134 == TX Byte 1 ==
1278 18:06:41.660151 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1279 18:06:41.663800 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1280 18:06:41.663920 ==
1281 18:06:41.667030 Dram Type= 6, Freq= 0, CH_0, rank 1
1282 18:06:41.670292 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1283 18:06:41.670390 ==
1284 18:06:41.684504 TX Vref=22, minBit 2, minWin=27, winSum=443
1285 18:06:41.687850 TX Vref=24, minBit 6, minWin=27, winSum=447
1286 18:06:41.691438 TX Vref=26, minBit 7, minWin=27, winSum=450
1287 18:06:41.694607 TX Vref=28, minBit 0, minWin=28, winSum=454
1288 18:06:41.698030 TX Vref=30, minBit 0, minWin=28, winSum=451
1289 18:06:41.701456 TX Vref=32, minBit 0, minWin=28, winSum=455
1290 18:06:41.708189 [TxChooseVref] Worse bit 0, Min win 28, Win sum 455, Final Vref 32
1291 18:06:41.708340
1292 18:06:41.711394 Final TX Range 1 Vref 32
1293 18:06:41.711510
1294 18:06:41.711578 ==
1295 18:06:41.715347 Dram Type= 6, Freq= 0, CH_0, rank 1
1296 18:06:41.718026 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1297 18:06:41.718138 ==
1298 18:06:41.718206
1299 18:06:41.718287
1300 18:06:41.721581 TX Vref Scan disable
1301 18:06:41.725854 == TX Byte 0 ==
1302 18:06:41.728885 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1303 18:06:41.731658 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1304 18:06:41.734563 == TX Byte 1 ==
1305 18:06:41.738060 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1306 18:06:41.741238 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1307 18:06:41.741352
1308 18:06:41.744626 [DATLAT]
1309 18:06:41.744716 Freq=800, CH0 RK1
1310 18:06:41.744783
1311 18:06:41.748194 DATLAT Default: 0xa
1312 18:06:41.748283 0, 0xFFFF, sum = 0
1313 18:06:41.751848 1, 0xFFFF, sum = 0
1314 18:06:41.751941 2, 0xFFFF, sum = 0
1315 18:06:41.754628 3, 0xFFFF, sum = 0
1316 18:06:41.754716 4, 0xFFFF, sum = 0
1317 18:06:41.758357 5, 0xFFFF, sum = 0
1318 18:06:41.758447 6, 0xFFFF, sum = 0
1319 18:06:41.761750 7, 0xFFFF, sum = 0
1320 18:06:41.761849 8, 0xFFFF, sum = 0
1321 18:06:41.765248 9, 0x0, sum = 1
1322 18:06:41.765336 10, 0x0, sum = 2
1323 18:06:41.768529 11, 0x0, sum = 3
1324 18:06:41.768617 12, 0x0, sum = 4
1325 18:06:41.771815 best_step = 10
1326 18:06:41.771904
1327 18:06:41.771982 ==
1328 18:06:41.775216 Dram Type= 6, Freq= 0, CH_0, rank 1
1329 18:06:41.778513 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1330 18:06:41.778615 ==
1331 18:06:41.778682 RX Vref Scan: 0
1332 18:06:41.781758
1333 18:06:41.781849 RX Vref 0 -> 0, step: 1
1334 18:06:41.781914
1335 18:06:41.785218 RX Delay -95 -> 252, step: 8
1336 18:06:41.788799 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1337 18:06:41.795184 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1338 18:06:41.798364 iDelay=209, Bit 2, Center 84 (-31 ~ 200) 232
1339 18:06:41.802021 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1340 18:06:41.805213 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1341 18:06:41.808384 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1342 18:06:41.815599 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1343 18:06:41.818576 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1344 18:06:41.821947 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
1345 18:06:41.825334 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1346 18:06:41.828708 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1347 18:06:41.835232 iDelay=209, Bit 11, Center 68 (-39 ~ 176) 216
1348 18:06:41.838582 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1349 18:06:41.841755 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1350 18:06:41.845613 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1351 18:06:41.848791 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1352 18:06:41.848885 ==
1353 18:06:41.852423 Dram Type= 6, Freq= 0, CH_0, rank 1
1354 18:06:41.859178 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1355 18:06:41.859317 ==
1356 18:06:41.859384 DQS Delay:
1357 18:06:41.862159 DQS0 = 0, DQS1 = 0
1358 18:06:41.862254 DQM Delay:
1359 18:06:41.862319 DQM0 = 87, DQM1 = 78
1360 18:06:41.865996 DQ Delay:
1361 18:06:41.869354 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =84
1362 18:06:41.872302 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1363 18:06:41.875526 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1364 18:06:41.878925 DQ12 =84, DQ13 =84, DQ14 =88, DQ15 =88
1365 18:06:41.879040
1366 18:06:41.879106
1367 18:06:41.885500 [DQSOSCAuto] RK1, (LSB)MR18= 0x311b, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 397 ps
1368 18:06:41.889073 CH0 RK1: MR19=606, MR18=311B
1369 18:06:41.895692 CH0_RK1: MR19=0x606, MR18=0x311B, DQSOSC=397, MR23=63, INC=93, DEC=62
1370 18:06:41.899236 [RxdqsGatingPostProcess] freq 800
1371 18:06:41.902501 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1372 18:06:41.906164 Pre-setting of DQS Precalculation
1373 18:06:41.912956 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1374 18:06:41.913120 ==
1375 18:06:41.916336 Dram Type= 6, Freq= 0, CH_1, rank 0
1376 18:06:41.919531 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1377 18:06:41.919657 ==
1378 18:06:41.922813 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1379 18:06:41.929287 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1380 18:06:41.939370 [CA 0] Center 36 (6~66) winsize 61
1381 18:06:41.942561 [CA 1] Center 36 (6~67) winsize 62
1382 18:06:41.946129 [CA 2] Center 35 (5~65) winsize 61
1383 18:06:41.949001 [CA 3] Center 33 (3~64) winsize 62
1384 18:06:41.952604 [CA 4] Center 34 (4~65) winsize 62
1385 18:06:41.955846 [CA 5] Center 33 (3~64) winsize 62
1386 18:06:41.955947
1387 18:06:41.959606 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1388 18:06:41.959698
1389 18:06:41.962517 [CATrainingPosCal] consider 1 rank data
1390 18:06:41.965896 u2DelayCellTimex100 = 270/100 ps
1391 18:06:41.969166 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1392 18:06:41.972908 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1393 18:06:41.979574 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
1394 18:06:41.982935 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1395 18:06:41.986900 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1396 18:06:41.989356 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1397 18:06:41.989459
1398 18:06:41.992918 CA PerBit enable=1, Macro0, CA PI delay=33
1399 18:06:41.993035
1400 18:06:41.996636 [CBTSetCACLKResult] CA Dly = 33
1401 18:06:41.996732 CS Dly: 5 (0~36)
1402 18:06:41.996819 ==
1403 18:06:42.000014 Dram Type= 6, Freq= 0, CH_1, rank 1
1404 18:06:42.006813 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1405 18:06:42.006942 ==
1406 18:06:42.009541 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1407 18:06:42.016340 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1408 18:06:42.025509 [CA 0] Center 36 (6~66) winsize 61
1409 18:06:42.028782 [CA 1] Center 36 (6~66) winsize 61
1410 18:06:42.032319 [CA 2] Center 33 (3~64) winsize 62
1411 18:06:42.035441 [CA 3] Center 33 (3~64) winsize 62
1412 18:06:42.038968 [CA 4] Center 34 (4~65) winsize 62
1413 18:06:42.042231 [CA 5] Center 33 (3~64) winsize 62
1414 18:06:42.042361
1415 18:06:42.045755 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1416 18:06:42.045847
1417 18:06:42.049460 [CATrainingPosCal] consider 2 rank data
1418 18:06:42.053411 u2DelayCellTimex100 = 270/100 ps
1419 18:06:42.057019 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1420 18:06:42.060829 CA1 delay=36 (6~66),Diff = 3 PI (21 cell)
1421 18:06:42.064375 CA2 delay=34 (5~64),Diff = 1 PI (7 cell)
1422 18:06:42.068665 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1423 18:06:42.071775 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1424 18:06:42.075304 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1425 18:06:42.075446
1426 18:06:42.079025 CA PerBit enable=1, Macro0, CA PI delay=33
1427 18:06:42.079164
1428 18:06:42.083282 [CBTSetCACLKResult] CA Dly = 33
1429 18:06:42.083421 CS Dly: 5 (0~37)
1430 18:06:42.083519
1431 18:06:42.085569 ----->DramcWriteLeveling(PI) begin...
1432 18:06:42.085689 ==
1433 18:06:42.089176 Dram Type= 6, Freq= 0, CH_1, rank 0
1434 18:06:42.096691 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1435 18:06:42.096862 ==
1436 18:06:42.099690 Write leveling (Byte 0): 25 => 25
1437 18:06:42.099811 Write leveling (Byte 1): 30 => 30
1438 18:06:42.102842 DramcWriteLeveling(PI) end<-----
1439 18:06:42.102957
1440 18:06:42.106011 ==
1441 18:06:42.106122 Dram Type= 6, Freq= 0, CH_1, rank 0
1442 18:06:42.112600 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1443 18:06:42.112741 ==
1444 18:06:42.116162 [Gating] SW mode calibration
1445 18:06:42.123443 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1446 18:06:42.126209 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1447 18:06:42.132879 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1448 18:06:42.135951 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1449 18:06:42.139374 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1450 18:06:42.143074 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1451 18:06:42.149292 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1452 18:06:42.152753 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1453 18:06:42.156210 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 18:06:42.163043 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 18:06:42.166247 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 18:06:42.169443 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 18:06:42.175968 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 18:06:42.179993 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 18:06:42.183217 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 18:06:42.189667 0 7 20 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1461 18:06:42.192835 0 7 24 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1462 18:06:42.196607 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 18:06:42.200075 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 18:06:42.206689 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1465 18:06:42.209945 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1466 18:06:42.213545 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 18:06:42.219826 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 18:06:42.223023 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 18:06:42.226685 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 18:06:42.233200 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 18:06:42.236836 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 18:06:42.240217 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 18:06:42.246639 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 18:06:42.250392 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1475 18:06:42.253235 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1476 18:06:42.260595 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1477 18:06:42.263734 0 9 24 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1478 18:06:42.266830 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1479 18:06:42.270360 0 10 0 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1480 18:06:42.276808 0 10 4 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 0)
1481 18:06:42.280487 0 10 8 | B1->B0 | 2e2e 2e2e | 0 0 | (1 1) (1 1)
1482 18:06:42.283560 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1483 18:06:42.290108 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 18:06:42.293480 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 18:06:42.296708 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 18:06:42.303934 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 18:06:42.306835 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 18:06:42.310719 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 18:06:42.316911 0 11 8 | B1->B0 | 3333 3737 | 0 0 | (0 0) (0 0)
1490 18:06:42.320714 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1491 18:06:42.323943 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1492 18:06:42.330717 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1493 18:06:42.333738 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1494 18:06:42.337406 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1495 18:06:42.340792 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1496 18:06:42.347245 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1497 18:06:42.350534 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1498 18:06:42.354296 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1499 18:06:42.360455 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1500 18:06:42.364039 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1501 18:06:42.367410 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 18:06:42.373556 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 18:06:42.377202 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 18:06:42.380456 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 18:06:42.387491 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 18:06:42.390682 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 18:06:42.393849 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 18:06:42.400681 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 18:06:42.403978 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 18:06:42.407304 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 18:06:42.410767 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 18:06:42.417811 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 18:06:42.420915 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1514 18:06:42.424378 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1515 18:06:42.427875 Total UI for P1: 0, mck2ui 16
1516 18:06:42.430866 best dqsien dly found for B0: ( 0, 14, 8)
1517 18:06:42.434350 Total UI for P1: 0, mck2ui 16
1518 18:06:42.437482 best dqsien dly found for B1: ( 0, 14, 8)
1519 18:06:42.441133 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1520 18:06:42.444229 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1521 18:06:42.444354
1522 18:06:42.447404 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1523 18:06:42.455138 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1524 18:06:42.455295 [Gating] SW calibration Done
1525 18:06:42.455392 ==
1526 18:06:42.457941 Dram Type= 6, Freq= 0, CH_1, rank 0
1527 18:06:42.464473 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1528 18:06:42.464624 ==
1529 18:06:42.464723 RX Vref Scan: 0
1530 18:06:42.464814
1531 18:06:42.467944 RX Vref 0 -> 0, step: 1
1532 18:06:42.468055
1533 18:06:42.471208 RX Delay -130 -> 252, step: 16
1534 18:06:42.474312 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
1535 18:06:42.477899 iDelay=206, Bit 1, Center 77 (-34 ~ 189) 224
1536 18:06:42.481174 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1537 18:06:42.484855 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1538 18:06:42.491937 iDelay=206, Bit 4, Center 77 (-34 ~ 189) 224
1539 18:06:42.495082 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1540 18:06:42.498244 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1541 18:06:42.501889 iDelay=206, Bit 7, Center 77 (-34 ~ 189) 224
1542 18:06:42.505530 iDelay=206, Bit 8, Center 61 (-66 ~ 189) 256
1543 18:06:42.511390 iDelay=206, Bit 9, Center 53 (-66 ~ 173) 240
1544 18:06:42.514643 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1545 18:06:42.517953 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1546 18:06:42.521534 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1547 18:06:42.524710 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1548 18:06:42.531850 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1549 18:06:42.535088 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1550 18:06:42.535207 ==
1551 18:06:42.538317 Dram Type= 6, Freq= 0, CH_1, rank 0
1552 18:06:42.541727 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1553 18:06:42.541871 ==
1554 18:06:42.544929 DQS Delay:
1555 18:06:42.545063 DQS0 = 0, DQS1 = 0
1556 18:06:42.545154 DQM Delay:
1557 18:06:42.548574 DQM0 = 83, DQM1 = 74
1558 18:06:42.548683 DQ Delay:
1559 18:06:42.551715 DQ0 =93, DQ1 =77, DQ2 =69, DQ3 =85
1560 18:06:42.555267 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1561 18:06:42.558473 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =69
1562 18:06:42.561970 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1563 18:06:42.562079
1564 18:06:42.562178
1565 18:06:42.562265 ==
1566 18:06:42.564937 Dram Type= 6, Freq= 0, CH_1, rank 0
1567 18:06:42.571379 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1568 18:06:42.571521 ==
1569 18:06:42.571618
1570 18:06:42.571713
1571 18:06:42.571801 TX Vref Scan disable
1572 18:06:42.574844 == TX Byte 0 ==
1573 18:06:42.578768 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1574 18:06:42.581574 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1575 18:06:42.584812 == TX Byte 1 ==
1576 18:06:42.588769 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1577 18:06:42.591752 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1578 18:06:42.595256 ==
1579 18:06:42.598345 Dram Type= 6, Freq= 0, CH_1, rank 0
1580 18:06:42.601661 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1581 18:06:42.601782 ==
1582 18:06:42.614992 TX Vref=22, minBit 0, minWin=27, winSum=438
1583 18:06:42.617978 TX Vref=24, minBit 1, minWin=27, winSum=440
1584 18:06:42.621371 TX Vref=26, minBit 1, minWin=27, winSum=443
1585 18:06:42.624717 TX Vref=28, minBit 4, minWin=27, winSum=447
1586 18:06:42.628225 TX Vref=30, minBit 0, minWin=27, winSum=446
1587 18:06:42.632076 TX Vref=32, minBit 0, minWin=28, winSum=452
1588 18:06:42.639499 [TxChooseVref] Worse bit 0, Min win 28, Win sum 452, Final Vref 32
1589 18:06:42.639645
1590 18:06:42.642726 Final TX Range 1 Vref 32
1591 18:06:42.642882
1592 18:06:42.642981 ==
1593 18:06:42.646081 Dram Type= 6, Freq= 0, CH_1, rank 0
1594 18:06:42.649369 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1595 18:06:42.649508 ==
1596 18:06:42.649606
1597 18:06:42.649696
1598 18:06:42.652246 TX Vref Scan disable
1599 18:06:42.655513 == TX Byte 0 ==
1600 18:06:42.658809 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1601 18:06:42.662246 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1602 18:06:42.666142 == TX Byte 1 ==
1603 18:06:42.668870 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1604 18:06:42.672191 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1605 18:06:42.672309
1606 18:06:42.672402 [DATLAT]
1607 18:06:42.676016 Freq=800, CH1 RK0
1608 18:06:42.676132
1609 18:06:42.676224 DATLAT Default: 0xa
1610 18:06:42.678866 0, 0xFFFF, sum = 0
1611 18:06:42.682312 1, 0xFFFF, sum = 0
1612 18:06:42.682464 2, 0xFFFF, sum = 0
1613 18:06:42.685814 3, 0xFFFF, sum = 0
1614 18:06:42.685913 4, 0xFFFF, sum = 0
1615 18:06:42.689226 5, 0xFFFF, sum = 0
1616 18:06:42.689327 6, 0xFFFF, sum = 0
1617 18:06:42.692615 7, 0xFFFF, sum = 0
1618 18:06:42.692718 8, 0xFFFF, sum = 0
1619 18:06:42.696230 9, 0x0, sum = 1
1620 18:06:42.696410 10, 0x0, sum = 2
1621 18:06:42.696554 11, 0x0, sum = 3
1622 18:06:42.698892 12, 0x0, sum = 4
1623 18:06:42.699034 best_step = 10
1624 18:06:42.699131
1625 18:06:42.702563 ==
1626 18:06:42.702682 Dram Type= 6, Freq= 0, CH_1, rank 0
1627 18:06:42.709059 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1628 18:06:42.709197 ==
1629 18:06:42.709270 RX Vref Scan: 1
1630 18:06:42.709330
1631 18:06:42.712417 Set Vref Range= 32 -> 127
1632 18:06:42.712498
1633 18:06:42.715680 RX Vref 32 -> 127, step: 1
1634 18:06:42.715767
1635 18:06:42.719251 RX Delay -111 -> 252, step: 8
1636 18:06:42.719373
1637 18:06:42.722441 Set Vref, RX VrefLevel [Byte0]: 32
1638 18:06:42.725969 [Byte1]: 32
1639 18:06:42.726069
1640 18:06:42.729164 Set Vref, RX VrefLevel [Byte0]: 33
1641 18:06:42.732385 [Byte1]: 33
1642 18:06:42.732475
1643 18:06:42.736206 Set Vref, RX VrefLevel [Byte0]: 34
1644 18:06:42.739244 [Byte1]: 34
1645 18:06:42.742507
1646 18:06:42.742606 Set Vref, RX VrefLevel [Byte0]: 35
1647 18:06:42.745839 [Byte1]: 35
1648 18:06:42.749974
1649 18:06:42.750077 Set Vref, RX VrefLevel [Byte0]: 36
1650 18:06:42.753410 [Byte1]: 36
1651 18:06:42.757963
1652 18:06:42.758063 Set Vref, RX VrefLevel [Byte0]: 37
1653 18:06:42.761324 [Byte1]: 37
1654 18:06:42.765320
1655 18:06:42.765411 Set Vref, RX VrefLevel [Byte0]: 38
1656 18:06:42.768871 [Byte1]: 38
1657 18:06:42.773350
1658 18:06:42.773449 Set Vref, RX VrefLevel [Byte0]: 39
1659 18:06:42.776794 [Byte1]: 39
1660 18:06:42.780890
1661 18:06:42.781046 Set Vref, RX VrefLevel [Byte0]: 40
1662 18:06:42.784267 [Byte1]: 40
1663 18:06:42.788356
1664 18:06:42.788445 Set Vref, RX VrefLevel [Byte0]: 41
1665 18:06:42.791872 [Byte1]: 41
1666 18:06:42.795936
1667 18:06:42.796025 Set Vref, RX VrefLevel [Byte0]: 42
1668 18:06:42.799325 [Byte1]: 42
1669 18:06:42.803940
1670 18:06:42.804029 Set Vref, RX VrefLevel [Byte0]: 43
1671 18:06:42.806816 [Byte1]: 43
1672 18:06:42.811398
1673 18:06:42.811490 Set Vref, RX VrefLevel [Byte0]: 44
1674 18:06:42.814825 [Byte1]: 44
1675 18:06:42.818694
1676 18:06:42.818781 Set Vref, RX VrefLevel [Byte0]: 45
1677 18:06:42.822415 [Byte1]: 45
1678 18:06:42.826476
1679 18:06:42.826565 Set Vref, RX VrefLevel [Byte0]: 46
1680 18:06:42.830045 [Byte1]: 46
1681 18:06:42.834617
1682 18:06:42.834722 Set Vref, RX VrefLevel [Byte0]: 47
1683 18:06:42.837599 [Byte1]: 47
1684 18:06:42.842045
1685 18:06:42.842173 Set Vref, RX VrefLevel [Byte0]: 48
1686 18:06:42.844923 [Byte1]: 48
1687 18:06:42.849383
1688 18:06:42.849472 Set Vref, RX VrefLevel [Byte0]: 49
1689 18:06:42.852988 [Byte1]: 49
1690 18:06:42.857067
1691 18:06:42.857187 Set Vref, RX VrefLevel [Byte0]: 50
1692 18:06:42.860723 [Byte1]: 50
1693 18:06:42.864735
1694 18:06:42.864825 Set Vref, RX VrefLevel [Byte0]: 51
1695 18:06:42.868123 [Byte1]: 51
1696 18:06:42.872592
1697 18:06:42.872687 Set Vref, RX VrefLevel [Byte0]: 52
1698 18:06:42.876054 [Byte1]: 52
1699 18:06:42.880379
1700 18:06:42.880474 Set Vref, RX VrefLevel [Byte0]: 53
1701 18:06:42.883713 [Byte1]: 53
1702 18:06:42.887750
1703 18:06:42.887840 Set Vref, RX VrefLevel [Byte0]: 54
1704 18:06:42.891201 [Byte1]: 54
1705 18:06:42.895371
1706 18:06:42.895460 Set Vref, RX VrefLevel [Byte0]: 55
1707 18:06:42.898851 [Byte1]: 55
1708 18:06:42.902927
1709 18:06:42.903015 Set Vref, RX VrefLevel [Byte0]: 56
1710 18:06:42.906230 [Byte1]: 56
1711 18:06:42.910785
1712 18:06:42.910877 Set Vref, RX VrefLevel [Byte0]: 57
1713 18:06:42.914271 [Byte1]: 57
1714 18:06:42.918388
1715 18:06:42.918477 Set Vref, RX VrefLevel [Byte0]: 58
1716 18:06:42.921878 [Byte1]: 58
1717 18:06:42.925758
1718 18:06:42.925843 Set Vref, RX VrefLevel [Byte0]: 59
1719 18:06:42.929450 [Byte1]: 59
1720 18:06:42.933396
1721 18:06:42.933486 Set Vref, RX VrefLevel [Byte0]: 60
1722 18:06:42.936854 [Byte1]: 60
1723 18:06:42.941529
1724 18:06:42.941629 Set Vref, RX VrefLevel [Byte0]: 61
1725 18:06:42.944447 [Byte1]: 61
1726 18:06:42.948922
1727 18:06:42.949067 Set Vref, RX VrefLevel [Byte0]: 62
1728 18:06:42.952431 [Byte1]: 62
1729 18:06:42.956447
1730 18:06:42.956536 Set Vref, RX VrefLevel [Byte0]: 63
1731 18:06:42.959991 [Byte1]: 63
1732 18:06:42.964446
1733 18:06:42.964537 Set Vref, RX VrefLevel [Byte0]: 64
1734 18:06:42.967358 [Byte1]: 64
1735 18:06:42.972051
1736 18:06:42.972141 Set Vref, RX VrefLevel [Byte0]: 65
1737 18:06:42.975509 [Byte1]: 65
1738 18:06:42.979624
1739 18:06:42.979712 Set Vref, RX VrefLevel [Byte0]: 66
1740 18:06:42.982643 [Byte1]: 66
1741 18:06:42.987180
1742 18:06:42.987273 Set Vref, RX VrefLevel [Byte0]: 67
1743 18:06:42.990232 [Byte1]: 67
1744 18:06:42.994586
1745 18:06:42.994672 Set Vref, RX VrefLevel [Byte0]: 68
1746 18:06:42.998173 [Byte1]: 68
1747 18:06:43.002312
1748 18:06:43.002402 Set Vref, RX VrefLevel [Byte0]: 69
1749 18:06:43.005610 [Byte1]: 69
1750 18:06:43.010123
1751 18:06:43.010214 Set Vref, RX VrefLevel [Byte0]: 70
1752 18:06:43.013446 [Byte1]: 70
1753 18:06:43.017989
1754 18:06:43.018082 Set Vref, RX VrefLevel [Byte0]: 71
1755 18:06:43.020914 [Byte1]: 71
1756 18:06:43.025602
1757 18:06:43.025690 Set Vref, RX VrefLevel [Byte0]: 72
1758 18:06:43.028601 [Byte1]: 72
1759 18:06:43.033061
1760 18:06:43.033149 Set Vref, RX VrefLevel [Byte0]: 73
1761 18:06:43.036370 [Byte1]: 73
1762 18:06:43.040447
1763 18:06:43.040538 Set Vref, RX VrefLevel [Byte0]: 74
1764 18:06:43.043898 [Byte1]: 74
1765 18:06:43.048522
1766 18:06:43.048614 Set Vref, RX VrefLevel [Byte0]: 75
1767 18:06:43.052348 [Byte1]: 75
1768 18:06:43.055885
1769 18:06:43.055974 Set Vref, RX VrefLevel [Byte0]: 76
1770 18:06:43.059359 [Byte1]: 76
1771 18:06:43.063995
1772 18:06:43.064085 Set Vref, RX VrefLevel [Byte0]: 77
1773 18:06:43.067360 [Byte1]: 77
1774 18:06:43.071399
1775 18:06:43.071486 Set Vref, RX VrefLevel [Byte0]: 78
1776 18:06:43.074948 [Byte1]: 78
1777 18:06:43.078973
1778 18:06:43.079058 Set Vref, RX VrefLevel [Byte0]: 79
1779 18:06:43.082331 [Byte1]: 79
1780 18:06:43.086368
1781 18:06:43.086455 Set Vref, RX VrefLevel [Byte0]: 80
1782 18:06:43.090012 [Byte1]: 80
1783 18:06:43.094045
1784 18:06:43.094134 Final RX Vref Byte 0 = 62 to rank0
1785 18:06:43.097510 Final RX Vref Byte 1 = 58 to rank0
1786 18:06:43.100864 Final RX Vref Byte 0 = 62 to rank1
1787 18:06:43.104389 Final RX Vref Byte 1 = 58 to rank1==
1788 18:06:43.107858 Dram Type= 6, Freq= 0, CH_1, rank 0
1789 18:06:43.110848 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1790 18:06:43.114401 ==
1791 18:06:43.114489 DQS Delay:
1792 18:06:43.114554 DQS0 = 0, DQS1 = 0
1793 18:06:43.117583 DQM Delay:
1794 18:06:43.117665 DQM0 = 84, DQM1 = 74
1795 18:06:43.120783 DQ Delay:
1796 18:06:43.124176 DQ0 =88, DQ1 =76, DQ2 =76, DQ3 =84
1797 18:06:43.124259 DQ4 =80, DQ5 =96, DQ6 =92, DQ7 =80
1798 18:06:43.127964 DQ8 =60, DQ9 =60, DQ10 =76, DQ11 =72
1799 18:06:43.131321 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =76
1800 18:06:43.131407
1801 18:06:43.134755
1802 18:06:43.141221 [DQSOSCAuto] RK0, (LSB)MR18= 0x24fa, (MSB)MR19= 0x605, tDQSOscB0 = 411 ps tDQSOscB1 = 400 ps
1803 18:06:43.144443 CH1 RK0: MR19=605, MR18=24FA
1804 18:06:43.151179 CH1_RK0: MR19=0x605, MR18=0x24FA, DQSOSC=400, MR23=63, INC=92, DEC=61
1805 18:06:43.151292
1806 18:06:43.154866 ----->DramcWriteLeveling(PI) begin...
1807 18:06:43.154956 ==
1808 18:06:43.157779 Dram Type= 6, Freq= 0, CH_1, rank 1
1809 18:06:43.160901 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1810 18:06:43.161050 ==
1811 18:06:43.164490 Write leveling (Byte 0): 26 => 26
1812 18:06:43.167903 Write leveling (Byte 1): 26 => 26
1813 18:06:43.171230 DramcWriteLeveling(PI) end<-----
1814 18:06:43.171317
1815 18:06:43.171380 ==
1816 18:06:43.174726 Dram Type= 6, Freq= 0, CH_1, rank 1
1817 18:06:43.177642 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1818 18:06:43.177732 ==
1819 18:06:43.181181 [Gating] SW mode calibration
1820 18:06:43.187994 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1821 18:06:43.194392 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1822 18:06:43.197873 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1823 18:06:43.201349 0 6 4 | B1->B0 | 2322 2323 | 1 0 | (1 0) (0 0)
1824 18:06:43.208264 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 18:06:43.211639 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 18:06:43.214496 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 18:06:43.217829 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 18:06:43.224744 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 18:06:43.228197 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 18:06:43.231362 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 18:06:43.238268 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 18:06:43.241413 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 18:06:43.244833 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 18:06:43.251821 0 7 16 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1835 18:06:43.255292 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 18:06:43.258404 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 18:06:43.264872 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 18:06:43.268831 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1839 18:06:43.271668 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1840 18:06:43.275078 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 18:06:43.281589 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 18:06:43.284999 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 18:06:43.288484 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1844 18:06:43.295449 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1845 18:06:43.298756 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1846 18:06:43.301700 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1847 18:06:43.308612 0 9 4 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
1848 18:06:43.312245 0 9 8 | B1->B0 | 2c2c 3434 | 1 1 | (1 1) (1 1)
1849 18:06:43.315627 0 9 12 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
1850 18:06:43.322338 0 9 16 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1851 18:06:43.325348 0 9 20 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1852 18:06:43.328679 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1853 18:06:43.332218 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1854 18:06:43.339211 0 10 0 | B1->B0 | 3535 3434 | 1 0 | (0 0) (0 0)
1855 18:06:43.342366 0 10 4 | B1->B0 | 3131 2e2e | 0 1 | (0 0) (1 0)
1856 18:06:43.345903 0 10 8 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
1857 18:06:43.352382 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1858 18:06:43.355851 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1859 18:06:43.359164 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1860 18:06:43.366310 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1861 18:06:43.369185 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1862 18:06:43.372378 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1863 18:06:43.379342 0 11 4 | B1->B0 | 2d2d 3737 | 0 0 | (0 0) (0 0)
1864 18:06:43.382514 0 11 8 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
1865 18:06:43.386084 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1866 18:06:43.389820 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1867 18:06:43.396233 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1868 18:06:43.399615 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1869 18:06:43.403048 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1870 18:06:43.409438 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1871 18:06:43.413086 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1872 18:06:43.415936 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 18:06:43.422790 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 18:06:43.426282 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 18:06:43.429724 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 18:06:43.436105 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1877 18:06:43.439621 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1878 18:06:43.443059 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1879 18:06:43.449827 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1880 18:06:43.453195 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1881 18:06:43.456597 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1882 18:06:43.459727 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1883 18:06:43.466445 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1884 18:06:43.469917 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1885 18:06:43.472921 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1886 18:06:43.479707 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1887 18:06:43.483400 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1888 18:06:43.486600 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1889 18:06:43.489855 Total UI for P1: 0, mck2ui 16
1890 18:06:43.493219 best dqsien dly found for B0: ( 0, 14, 4)
1891 18:06:43.500109 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1892 18:06:43.500272 Total UI for P1: 0, mck2ui 16
1893 18:06:43.503222 best dqsien dly found for B1: ( 0, 14, 8)
1894 18:06:43.509922 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1895 18:06:43.513422 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1896 18:06:43.513517
1897 18:06:43.516958 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1898 18:06:43.519930 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1899 18:06:43.523199 [Gating] SW calibration Done
1900 18:06:43.523289 ==
1901 18:06:43.526669 Dram Type= 6, Freq= 0, CH_1, rank 1
1902 18:06:43.530329 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1903 18:06:43.530437 ==
1904 18:06:43.530504 RX Vref Scan: 0
1905 18:06:43.530579
1906 18:06:43.533650 RX Vref 0 -> 0, step: 1
1907 18:06:43.533732
1908 18:06:43.536985 RX Delay -130 -> 252, step: 16
1909 18:06:43.540432 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1910 18:06:43.543943 iDelay=206, Bit 1, Center 69 (-50 ~ 189) 240
1911 18:06:43.550539 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1912 18:06:43.553868 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1913 18:06:43.557310 iDelay=206, Bit 4, Center 77 (-34 ~ 189) 224
1914 18:06:43.560848 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1915 18:06:43.564015 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1916 18:06:43.567138 iDelay=206, Bit 7, Center 77 (-34 ~ 189) 224
1917 18:06:43.574036 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1918 18:06:43.577620 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1919 18:06:43.580518 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1920 18:06:43.583805 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1921 18:06:43.587320 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1922 18:06:43.594095 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1923 18:06:43.597552 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1924 18:06:43.600865 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1925 18:06:43.600959 ==
1926 18:06:43.604154 Dram Type= 6, Freq= 0, CH_1, rank 1
1927 18:06:43.607641 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1928 18:06:43.607732 ==
1929 18:06:43.610474 DQS Delay:
1930 18:06:43.610557 DQS0 = 0, DQS1 = 0
1931 18:06:43.614398 DQM Delay:
1932 18:06:43.614483 DQM0 = 81, DQM1 = 77
1933 18:06:43.614549 DQ Delay:
1934 18:06:43.617489 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =85
1935 18:06:43.620847 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1936 18:06:43.624342 DQ8 =69, DQ9 =69, DQ10 =69, DQ11 =69
1937 18:06:43.627547 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1938 18:06:43.627635
1939 18:06:43.627701
1940 18:06:43.627763 ==
1941 18:06:43.630960 Dram Type= 6, Freq= 0, CH_1, rank 1
1942 18:06:43.637778 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1943 18:06:43.637887 ==
1944 18:06:43.637954
1945 18:06:43.638015
1946 18:06:43.638072 TX Vref Scan disable
1947 18:06:43.641177 == TX Byte 0 ==
1948 18:06:43.644730 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1949 18:06:43.648216 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1950 18:06:43.651606 == TX Byte 1 ==
1951 18:06:43.654961 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1952 18:06:43.657896 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1953 18:06:43.661350 ==
1954 18:06:43.664861 Dram Type= 6, Freq= 0, CH_1, rank 1
1955 18:06:43.668127 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1956 18:06:43.668216 ==
1957 18:06:43.680099 TX Vref=22, minBit 15, minWin=26, winSum=442
1958 18:06:43.683477 TX Vref=24, minBit 5, minWin=27, winSum=442
1959 18:06:43.686898 TX Vref=26, minBit 1, minWin=27, winSum=446
1960 18:06:43.690410 TX Vref=28, minBit 12, minWin=27, winSum=449
1961 18:06:43.693940 TX Vref=30, minBit 0, minWin=28, winSum=451
1962 18:06:43.700203 TX Vref=32, minBit 0, minWin=28, winSum=450
1963 18:06:43.703542 [TxChooseVref] Worse bit 0, Min win 28, Win sum 451, Final Vref 30
1964 18:06:43.703635
1965 18:06:43.706784 Final TX Range 1 Vref 30
1966 18:06:43.706866
1967 18:06:43.706929 ==
1968 18:06:43.710274 Dram Type= 6, Freq= 0, CH_1, rank 1
1969 18:06:43.713484 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1970 18:06:43.713571 ==
1971 18:06:43.713635
1972 18:06:43.717080
1973 18:06:43.717161 TX Vref Scan disable
1974 18:06:43.720617 == TX Byte 0 ==
1975 18:06:43.723676 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1976 18:06:43.727133 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1977 18:06:43.730828 == TX Byte 1 ==
1978 18:06:43.733649 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1979 18:06:43.736876 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1980 18:06:43.736963
1981 18:06:43.740602 [DATLAT]
1982 18:06:43.740719 Freq=800, CH1 RK1
1983 18:06:43.740797
1984 18:06:43.744039 DATLAT Default: 0xa
1985 18:06:43.744142 0, 0xFFFF, sum = 0
1986 18:06:43.747525 1, 0xFFFF, sum = 0
1987 18:06:43.747609 2, 0xFFFF, sum = 0
1988 18:06:43.750458 3, 0xFFFF, sum = 0
1989 18:06:43.750542 4, 0xFFFF, sum = 0
1990 18:06:43.753864 5, 0xFFFF, sum = 0
1991 18:06:43.753949 6, 0xFFFF, sum = 0
1992 18:06:43.757257 7, 0xFFFF, sum = 0
1993 18:06:43.757340 8, 0xFFFF, sum = 0
1994 18:06:43.760532 9, 0x0, sum = 1
1995 18:06:43.760615 10, 0x0, sum = 2
1996 18:06:43.764031 11, 0x0, sum = 3
1997 18:06:43.764116 12, 0x0, sum = 4
1998 18:06:43.767603 best_step = 10
1999 18:06:43.767685
2000 18:06:43.767748 ==
2001 18:06:43.770936 Dram Type= 6, Freq= 0, CH_1, rank 1
2002 18:06:43.774325 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2003 18:06:43.774416 ==
2004 18:06:43.777756 RX Vref Scan: 0
2005 18:06:43.777837
2006 18:06:43.777900 RX Vref 0 -> 0, step: 1
2007 18:06:43.777960
2008 18:06:43.780634 RX Delay -95 -> 252, step: 8
2009 18:06:43.787754 iDelay=209, Bit 0, Center 84 (-31 ~ 200) 232
2010 18:06:43.790957 iDelay=209, Bit 1, Center 76 (-39 ~ 192) 232
2011 18:06:43.793999 iDelay=209, Bit 2, Center 68 (-47 ~ 184) 232
2012 18:06:43.797570 iDelay=209, Bit 3, Center 76 (-39 ~ 192) 232
2013 18:06:43.801112 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
2014 18:06:43.804416 iDelay=209, Bit 5, Center 92 (-15 ~ 200) 216
2015 18:06:43.810765 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
2016 18:06:43.814188 iDelay=209, Bit 7, Center 76 (-39 ~ 192) 232
2017 18:06:43.817394 iDelay=209, Bit 8, Center 64 (-55 ~ 184) 240
2018 18:06:43.820956 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
2019 18:06:43.824228 iDelay=209, Bit 10, Center 76 (-39 ~ 192) 232
2020 18:06:43.830774 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
2021 18:06:43.834224 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
2022 18:06:43.837675 iDelay=209, Bit 13, Center 84 (-31 ~ 200) 232
2023 18:06:43.841018 iDelay=209, Bit 14, Center 84 (-31 ~ 200) 232
2024 18:06:43.845111 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
2025 18:06:43.847877 ==
2026 18:06:43.847969 Dram Type= 6, Freq= 0, CH_1, rank 1
2027 18:06:43.854469 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2028 18:06:43.854572 ==
2029 18:06:43.854637 DQS Delay:
2030 18:06:43.858171 DQS0 = 0, DQS1 = 0
2031 18:06:43.858257 DQM Delay:
2032 18:06:43.858321 DQM0 = 81, DQM1 = 75
2033 18:06:43.861645 DQ Delay:
2034 18:06:43.864857 DQ0 =84, DQ1 =76, DQ2 =68, DQ3 =76
2035 18:06:43.867768 DQ4 =84, DQ5 =92, DQ6 =92, DQ7 =76
2036 18:06:43.871282 DQ8 =64, DQ9 =64, DQ10 =76, DQ11 =68
2037 18:06:43.874676 DQ12 =80, DQ13 =84, DQ14 =84, DQ15 =84
2038 18:06:43.874753
2039 18:06:43.874815
2040 18:06:43.881131 [DQSOSCAuto] RK1, (LSB)MR18= 0x1a25, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 403 ps
2041 18:06:43.884531 CH1 RK1: MR19=606, MR18=1A25
2042 18:06:43.891593 CH1_RK1: MR19=0x606, MR18=0x1A25, DQSOSC=400, MR23=63, INC=92, DEC=61
2043 18:06:43.894839 [RxdqsGatingPostProcess] freq 800
2044 18:06:43.898185 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2045 18:06:43.901608 Pre-setting of DQS Precalculation
2046 18:06:43.908079 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2047 18:06:43.914951 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2048 18:06:43.922029 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2049 18:06:43.922147
2050 18:06:43.922212
2051 18:06:43.925405 [Calibration Summary] 1600 Mbps
2052 18:06:43.925489 CH 0, Rank 0
2053 18:06:43.928617 SW Impedance : PASS
2054 18:06:43.931746 DUTY Scan : NO K
2055 18:06:43.931831 ZQ Calibration : PASS
2056 18:06:43.935032 Jitter Meter : NO K
2057 18:06:43.935117 CBT Training : PASS
2058 18:06:43.938671 Write leveling : PASS
2059 18:06:43.942286 RX DQS gating : PASS
2060 18:06:43.942373 RX DQ/DQS(RDDQC) : PASS
2061 18:06:43.945211 TX DQ/DQS : PASS
2062 18:06:43.948697 RX DATLAT : PASS
2063 18:06:43.948782 RX DQ/DQS(Engine): PASS
2064 18:06:43.952054 TX OE : NO K
2065 18:06:43.952138 All Pass.
2066 18:06:43.952202
2067 18:06:43.955020 CH 0, Rank 1
2068 18:06:43.955112 SW Impedance : PASS
2069 18:06:43.958377 DUTY Scan : NO K
2070 18:06:43.962154 ZQ Calibration : PASS
2071 18:06:43.962239 Jitter Meter : NO K
2072 18:06:43.965457 CBT Training : PASS
2073 18:06:43.968996 Write leveling : PASS
2074 18:06:43.969095 RX DQS gating : PASS
2075 18:06:43.972222 RX DQ/DQS(RDDQC) : PASS
2076 18:06:43.972304 TX DQ/DQS : PASS
2077 18:06:43.975119 RX DATLAT : PASS
2078 18:06:43.978795 RX DQ/DQS(Engine): PASS
2079 18:06:43.978879 TX OE : NO K
2080 18:06:43.982253 All Pass.
2081 18:06:43.982338
2082 18:06:43.982402 CH 1, Rank 0
2083 18:06:43.985512 SW Impedance : PASS
2084 18:06:43.985595 DUTY Scan : NO K
2085 18:06:43.988450 ZQ Calibration : PASS
2086 18:06:43.991915 Jitter Meter : NO K
2087 18:06:43.991998 CBT Training : PASS
2088 18:06:43.995398 Write leveling : PASS
2089 18:06:43.998702 RX DQS gating : PASS
2090 18:06:43.998788 RX DQ/DQS(RDDQC) : PASS
2091 18:06:44.002256 TX DQ/DQS : PASS
2092 18:06:44.005545 RX DATLAT : PASS
2093 18:06:44.005632 RX DQ/DQS(Engine): PASS
2094 18:06:44.008937 TX OE : NO K
2095 18:06:44.009052 All Pass.
2096 18:06:44.009117
2097 18:06:44.009205 CH 1, Rank 1
2098 18:06:44.011963 SW Impedance : PASS
2099 18:06:44.015493 DUTY Scan : NO K
2100 18:06:44.015579 ZQ Calibration : PASS
2101 18:06:44.018975 Jitter Meter : NO K
2102 18:06:44.022412 CBT Training : PASS
2103 18:06:44.022495 Write leveling : PASS
2104 18:06:44.025882 RX DQS gating : PASS
2105 18:06:44.028900 RX DQ/DQS(RDDQC) : PASS
2106 18:06:44.029042 TX DQ/DQS : PASS
2107 18:06:44.032252 RX DATLAT : PASS
2108 18:06:44.035586 RX DQ/DQS(Engine): PASS
2109 18:06:44.035670 TX OE : NO K
2110 18:06:44.035735 All Pass.
2111 18:06:44.038903
2112 18:06:44.039026 DramC Write-DBI off
2113 18:06:44.042532 PER_BANK_REFRESH: Hybrid Mode
2114 18:06:44.042642 TX_TRACKING: ON
2115 18:06:44.045814 [GetDramInforAfterCalByMRR] Vendor 6.
2116 18:06:44.049342 [GetDramInforAfterCalByMRR] Revision 606.
2117 18:06:44.055577 [GetDramInforAfterCalByMRR] Revision 2 0.
2118 18:06:44.055708 MR0 0x3b3b
2119 18:06:44.055809 MR8 0x5151
2120 18:06:44.058969 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2121 18:06:44.059077
2122 18:06:44.062390 MR0 0x3b3b
2123 18:06:44.062497 MR8 0x5151
2124 18:06:44.065837 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2125 18:06:44.065945
2126 18:06:44.076083 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2127 18:06:44.079484 [FAST_K] Save calibration result to emmc
2128 18:06:44.082801 [FAST_K] Save calibration result to emmc
2129 18:06:44.086687 dram_init: config_dvfs: 1
2130 18:06:44.089715 dramc_set_vcore_voltage set vcore to 662500
2131 18:06:44.089829 Read voltage for 1200, 2
2132 18:06:44.092739 Vio18 = 0
2133 18:06:44.092864 Vcore = 662500
2134 18:06:44.092960 Vdram = 0
2135 18:06:44.095842 Vddq = 0
2136 18:06:44.095947 Vmddr = 0
2137 18:06:44.099721 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2138 18:06:44.105767 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2139 18:06:44.109293 MEM_TYPE=3, freq_sel=15
2140 18:06:44.112447 sv_algorithm_assistance_LP4_1600
2141 18:06:44.115917 ============ PULL DRAM RESETB DOWN ============
2142 18:06:44.119362 ========== PULL DRAM RESETB DOWN end =========
2143 18:06:44.122858 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2144 18:06:44.125819 ===================================
2145 18:06:44.129380 LPDDR4 DRAM CONFIGURATION
2146 18:06:44.132882 ===================================
2147 18:06:44.136321 EX_ROW_EN[0] = 0x0
2148 18:06:44.136436 EX_ROW_EN[1] = 0x0
2149 18:06:44.139736 LP4Y_EN = 0x0
2150 18:06:44.139843 WORK_FSP = 0x0
2151 18:06:44.143109 WL = 0x4
2152 18:06:44.143229 RL = 0x4
2153 18:06:44.146543 BL = 0x2
2154 18:06:44.146651 RPST = 0x0
2155 18:06:44.149965 RD_PRE = 0x0
2156 18:06:44.150072 WR_PRE = 0x1
2157 18:06:44.153100 WR_PST = 0x0
2158 18:06:44.153207 DBI_WR = 0x0
2159 18:06:44.156455 DBI_RD = 0x0
2160 18:06:44.156564 OTF = 0x1
2161 18:06:44.159877 ===================================
2162 18:06:44.163142 ===================================
2163 18:06:44.166622 ANA top config
2164 18:06:44.169546 ===================================
2165 18:06:44.173203 DLL_ASYNC_EN = 0
2166 18:06:44.173316 ALL_SLAVE_EN = 0
2167 18:06:44.176482 NEW_RANK_MODE = 1
2168 18:06:44.179988 DLL_IDLE_MODE = 1
2169 18:06:44.183434 LP45_APHY_COMB_EN = 1
2170 18:06:44.183546 TX_ODT_DIS = 1
2171 18:06:44.186783 NEW_8X_MODE = 1
2172 18:06:44.189742 ===================================
2173 18:06:44.193120 ===================================
2174 18:06:44.196510 data_rate = 2400
2175 18:06:44.199932 CKR = 1
2176 18:06:44.203356 DQ_P2S_RATIO = 8
2177 18:06:44.206679 ===================================
2178 18:06:44.206794 CA_P2S_RATIO = 8
2179 18:06:44.209796 DQ_CA_OPEN = 0
2180 18:06:44.213355 DQ_SEMI_OPEN = 0
2181 18:06:44.217317 CA_SEMI_OPEN = 0
2182 18:06:44.220387 CA_FULL_RATE = 0
2183 18:06:44.223289 DQ_CKDIV4_EN = 0
2184 18:06:44.223405 CA_CKDIV4_EN = 0
2185 18:06:44.227015 CA_PREDIV_EN = 0
2186 18:06:44.229794 PH8_DLY = 17
2187 18:06:44.233373 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2188 18:06:44.236875 DQ_AAMCK_DIV = 4
2189 18:06:44.240317 CA_AAMCK_DIV = 4
2190 18:06:44.240429 CA_ADMCK_DIV = 4
2191 18:06:44.243281 DQ_TRACK_CA_EN = 0
2192 18:06:44.246520 CA_PICK = 1200
2193 18:06:44.250082 CA_MCKIO = 1200
2194 18:06:44.253458 MCKIO_SEMI = 0
2195 18:06:44.256918 PLL_FREQ = 2366
2196 18:06:44.260276 DQ_UI_PI_RATIO = 32
2197 18:06:44.260391 CA_UI_PI_RATIO = 0
2198 18:06:44.263709 ===================================
2199 18:06:44.266939 ===================================
2200 18:06:44.270413 memory_type:LPDDR4
2201 18:06:44.273443 GP_NUM : 10
2202 18:06:44.273553 SRAM_EN : 1
2203 18:06:44.276830 MD32_EN : 0
2204 18:06:44.280208 ===================================
2205 18:06:44.283611 [ANA_INIT] >>>>>>>>>>>>>>
2206 18:06:44.283725 <<<<<< [CONFIGURE PHASE]: ANA_TX
2207 18:06:44.290241 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2208 18:06:44.290374 ===================================
2209 18:06:44.293787 data_rate = 2400,PCW = 0X5b00
2210 18:06:44.297235 ===================================
2211 18:06:44.300027 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2212 18:06:44.306908 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2213 18:06:44.313730 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2214 18:06:44.317061 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2215 18:06:44.320524 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2216 18:06:44.324033 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2217 18:06:44.327401 [ANA_INIT] flow start
2218 18:06:44.327517 [ANA_INIT] PLL >>>>>>>>
2219 18:06:44.330316 [ANA_INIT] PLL <<<<<<<<
2220 18:06:44.333937 [ANA_INIT] MIDPI >>>>>>>>
2221 18:06:44.334050 [ANA_INIT] MIDPI <<<<<<<<
2222 18:06:44.337038 [ANA_INIT] DLL >>>>>>>>
2223 18:06:44.340512 [ANA_INIT] DLL <<<<<<<<
2224 18:06:44.340624 [ANA_INIT] flow end
2225 18:06:44.347217 ============ LP4 DIFF to SE enter ============
2226 18:06:44.350542 ============ LP4 DIFF to SE exit ============
2227 18:06:44.350649 [ANA_INIT] <<<<<<<<<<<<<
2228 18:06:44.354100 [Flow] Enable top DCM control >>>>>
2229 18:06:44.357388 [Flow] Enable top DCM control <<<<<
2230 18:06:44.360867 Enable DLL master slave shuffle
2231 18:06:44.367449 ==============================================================
2232 18:06:44.367563 Gating Mode config
2233 18:06:44.374171 ==============================================================
2234 18:06:44.377505 Config description:
2235 18:06:44.387263 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2236 18:06:44.394156 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2237 18:06:44.397711 SELPH_MODE 0: By rank 1: By Phase
2238 18:06:44.403968 ==============================================================
2239 18:06:44.407469 GAT_TRACK_EN = 1
2240 18:06:44.407566 RX_GATING_MODE = 2
2241 18:06:44.411000 RX_GATING_TRACK_MODE = 2
2242 18:06:44.414543 SELPH_MODE = 1
2243 18:06:44.417343 PICG_EARLY_EN = 1
2244 18:06:44.420769 VALID_LAT_VALUE = 1
2245 18:06:44.427548 ==============================================================
2246 18:06:44.431120 Enter into Gating configuration >>>>
2247 18:06:44.434467 Exit from Gating configuration <<<<
2248 18:06:44.437976 Enter into DVFS_PRE_config >>>>>
2249 18:06:44.448138 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2250 18:06:44.451427 Exit from DVFS_PRE_config <<<<<
2251 18:06:44.454538 Enter into PICG configuration >>>>
2252 18:06:44.457609 Exit from PICG configuration <<<<
2253 18:06:44.461436 [RX_INPUT] configuration >>>>>
2254 18:06:44.461536 [RX_INPUT] configuration <<<<<
2255 18:06:44.467823 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2256 18:06:44.471101 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2257 18:06:44.477839 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2258 18:06:44.484668 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2259 18:06:44.491376 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2260 18:06:44.498225 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2261 18:06:44.501678 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2262 18:06:44.504549 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2263 18:06:44.508100 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2264 18:06:44.514973 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2265 18:06:44.517965 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2266 18:06:44.521885 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2267 18:06:44.525169 ===================================
2268 18:06:44.527984 LPDDR4 DRAM CONFIGURATION
2269 18:06:44.531507 ===================================
2270 18:06:44.535075 EX_ROW_EN[0] = 0x0
2271 18:06:44.535167 EX_ROW_EN[1] = 0x0
2272 18:06:44.538515 LP4Y_EN = 0x0
2273 18:06:44.538600 WORK_FSP = 0x0
2274 18:06:44.541488 WL = 0x4
2275 18:06:44.541593 RL = 0x4
2276 18:06:44.544984 BL = 0x2
2277 18:06:44.545087 RPST = 0x0
2278 18:06:44.548505 RD_PRE = 0x0
2279 18:06:44.548590 WR_PRE = 0x1
2280 18:06:44.551973 WR_PST = 0x0
2281 18:06:44.552056 DBI_WR = 0x0
2282 18:06:44.555034 DBI_RD = 0x0
2283 18:06:44.555119 OTF = 0x1
2284 18:06:44.558535 ===================================
2285 18:06:44.562017 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2286 18:06:44.568206 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2287 18:06:44.572068 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2288 18:06:44.575090 ===================================
2289 18:06:44.578456 LPDDR4 DRAM CONFIGURATION
2290 18:06:44.582045 ===================================
2291 18:06:44.582163 EX_ROW_EN[0] = 0x10
2292 18:06:44.585095 EX_ROW_EN[1] = 0x0
2293 18:06:44.585181 LP4Y_EN = 0x0
2294 18:06:44.588683 WORK_FSP = 0x0
2295 18:06:44.588776 WL = 0x4
2296 18:06:44.591848 RL = 0x4
2297 18:06:44.595118 BL = 0x2
2298 18:06:44.595210 RPST = 0x0
2299 18:06:44.598777 RD_PRE = 0x0
2300 18:06:44.598865 WR_PRE = 0x1
2301 18:06:44.601804 WR_PST = 0x0
2302 18:06:44.601889 DBI_WR = 0x0
2303 18:06:44.605115 DBI_RD = 0x0
2304 18:06:44.605200 OTF = 0x1
2305 18:06:44.608415 ===================================
2306 18:06:44.615215 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2307 18:06:44.615327 ==
2308 18:06:44.618761 Dram Type= 6, Freq= 0, CH_0, rank 0
2309 18:06:44.621938 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2310 18:06:44.622068 ==
2311 18:06:44.625661 [Duty_Offset_Calibration]
2312 18:06:44.625749 B0:2 B1:-1 CA:1
2313 18:06:44.628943
2314 18:06:44.632207 [DutyScan_Calibration_Flow] k_type=0
2315 18:06:44.640012
2316 18:06:44.640184 ==CLK 0==
2317 18:06:44.642501 Final CLK duty delay cell = -4
2318 18:06:44.645418 [-4] MAX Duty = 5031%(X100), DQS PI = 4
2319 18:06:44.648952 [-4] MIN Duty = 4875%(X100), DQS PI = 32
2320 18:06:44.652443 [-4] AVG Duty = 4953%(X100)
2321 18:06:44.652558
2322 18:06:44.655923 CH0 CLK Duty spec in!! Max-Min= 156%
2323 18:06:44.658964 [DutyScan_Calibration_Flow] ====Done====
2324 18:06:44.659074
2325 18:06:44.662455 [DutyScan_Calibration_Flow] k_type=1
2326 18:06:44.677504
2327 18:06:44.677616 ==DQS 0 ==
2328 18:06:44.681476 Final DQS duty delay cell = 0
2329 18:06:44.684697 [0] MAX Duty = 5125%(X100), DQS PI = 46
2330 18:06:44.687845 [0] MIN Duty = 5000%(X100), DQS PI = 12
2331 18:06:44.691296 [0] AVG Duty = 5062%(X100)
2332 18:06:44.691394
2333 18:06:44.691480 ==DQS 1 ==
2334 18:06:44.694767 Final DQS duty delay cell = -4
2335 18:06:44.698114 [-4] MAX Duty = 5093%(X100), DQS PI = 4
2336 18:06:44.701150 [-4] MIN Duty = 5000%(X100), DQS PI = 44
2337 18:06:44.704529 [-4] AVG Duty = 5046%(X100)
2338 18:06:44.704639
2339 18:06:44.708570 CH0 DQS 0 Duty spec in!! Max-Min= 125%
2340 18:06:44.708675
2341 18:06:44.711528 CH0 DQS 1 Duty spec in!! Max-Min= 93%
2342 18:06:44.716021 [DutyScan_Calibration_Flow] ====Done====
2343 18:06:44.716127
2344 18:06:44.718834 [DutyScan_Calibration_Flow] k_type=3
2345 18:06:44.734507
2346 18:06:44.734662 ==DQM 0 ==
2347 18:06:44.737848 Final DQM duty delay cell = 0
2348 18:06:44.741175 [0] MAX Duty = 5031%(X100), DQS PI = 54
2349 18:06:44.744951 [0] MIN Duty = 4875%(X100), DQS PI = 2
2350 18:06:44.745102 [0] AVG Duty = 4953%(X100)
2351 18:06:44.748013
2352 18:06:44.748119 ==DQM 1 ==
2353 18:06:44.751473 Final DQM duty delay cell = 0
2354 18:06:44.754400 [0] MAX Duty = 5156%(X100), DQS PI = 62
2355 18:06:44.757903 [0] MIN Duty = 4969%(X100), DQS PI = 10
2356 18:06:44.758007 [0] AVG Duty = 5062%(X100)
2357 18:06:44.761368
2358 18:06:44.764800 CH0 DQM 0 Duty spec in!! Max-Min= 156%
2359 18:06:44.764904
2360 18:06:44.768171 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2361 18:06:44.771152 [DutyScan_Calibration_Flow] ====Done====
2362 18:06:44.771252
2363 18:06:44.774756 [DutyScan_Calibration_Flow] k_type=2
2364 18:06:44.790229
2365 18:06:44.790336 ==DQ 0 ==
2366 18:06:44.793358 Final DQ duty delay cell = -4
2367 18:06:44.797302 [-4] MAX Duty = 5031%(X100), DQS PI = 38
2368 18:06:44.800224 [-4] MIN Duty = 4844%(X100), DQS PI = 18
2369 18:06:44.803641 [-4] AVG Duty = 4937%(X100)
2370 18:06:44.803747
2371 18:06:44.803840 ==DQ 1 ==
2372 18:06:44.807044 Final DQ duty delay cell = 0
2373 18:06:44.810537 [0] MAX Duty = 5031%(X100), DQS PI = 18
2374 18:06:44.814037 [0] MIN Duty = 4907%(X100), DQS PI = 46
2375 18:06:44.814143 [0] AVG Duty = 4969%(X100)
2376 18:06:44.814236
2377 18:06:44.820342 CH0 DQ 0 Duty spec in!! Max-Min= 187%
2378 18:06:44.820448
2379 18:06:44.823945 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2380 18:06:44.827327 [DutyScan_Calibration_Flow] ====Done====
2381 18:06:44.827432 ==
2382 18:06:44.830736 Dram Type= 6, Freq= 0, CH_1, rank 0
2383 18:06:44.833952 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2384 18:06:44.834055 ==
2385 18:06:44.837338 [Duty_Offset_Calibration]
2386 18:06:44.837441 B0:1 B1:1 CA:2
2387 18:06:44.837532
2388 18:06:44.840664 [DutyScan_Calibration_Flow] k_type=0
2389 18:06:44.850744
2390 18:06:44.850856 ==CLK 0==
2391 18:06:44.854551 Final CLK duty delay cell = 0
2392 18:06:44.857778 [0] MAX Duty = 5094%(X100), DQS PI = 56
2393 18:06:44.860361 [0] MIN Duty = 4938%(X100), DQS PI = 24
2394 18:06:44.860438 [0] AVG Duty = 5016%(X100)
2395 18:06:44.863901
2396 18:06:44.864001 CH1 CLK Duty spec in!! Max-Min= 156%
2397 18:06:44.870479 [DutyScan_Calibration_Flow] ====Done====
2398 18:06:44.870556
2399 18:06:44.873621 [DutyScan_Calibration_Flow] k_type=1
2400 18:06:44.889916
2401 18:06:44.890019 ==DQS 0 ==
2402 18:06:44.893356 Final DQS duty delay cell = 0
2403 18:06:44.896334 [0] MAX Duty = 5031%(X100), DQS PI = 50
2404 18:06:44.900056 [0] MIN Duty = 4844%(X100), DQS PI = 62
2405 18:06:44.903294 [0] AVG Duty = 4937%(X100)
2406 18:06:44.903395
2407 18:06:44.903486 ==DQS 1 ==
2408 18:06:44.906618 Final DQS duty delay cell = 0
2409 18:06:44.909856 [0] MAX Duty = 5031%(X100), DQS PI = 20
2410 18:06:44.913276 [0] MIN Duty = 4907%(X100), DQS PI = 0
2411 18:06:44.913378 [0] AVG Duty = 4969%(X100)
2412 18:06:44.913466
2413 18:06:44.920198 CH1 DQS 0 Duty spec in!! Max-Min= 187%
2414 18:06:44.920297
2415 18:06:44.923770 CH1 DQS 1 Duty spec in!! Max-Min= 124%
2416 18:06:44.927265 [DutyScan_Calibration_Flow] ====Done====
2417 18:06:44.927361
2418 18:06:44.930031 [DutyScan_Calibration_Flow] k_type=3
2419 18:06:44.946355
2420 18:06:44.946463 ==DQM 0 ==
2421 18:06:44.949547 Final DQM duty delay cell = 0
2422 18:06:44.952927 [0] MAX Duty = 5093%(X100), DQS PI = 6
2423 18:06:44.956434 [0] MIN Duty = 4907%(X100), DQS PI = 18
2424 18:06:44.956517 [0] AVG Duty = 5000%(X100)
2425 18:06:44.959946
2426 18:06:44.960047 ==DQM 1 ==
2427 18:06:44.962880 Final DQM duty delay cell = 0
2428 18:06:44.966428 [0] MAX Duty = 5156%(X100), DQS PI = 30
2429 18:06:44.969674 [0] MIN Duty = 4938%(X100), DQS PI = 56
2430 18:06:44.969753 [0] AVG Duty = 5047%(X100)
2431 18:06:44.972883
2432 18:06:44.976358 CH1 DQM 0 Duty spec in!! Max-Min= 186%
2433 18:06:44.976457
2434 18:06:44.979767 CH1 DQM 1 Duty spec in!! Max-Min= 218%
2435 18:06:44.983564 [DutyScan_Calibration_Flow] ====Done====
2436 18:06:44.983634
2437 18:06:44.986313 [DutyScan_Calibration_Flow] k_type=2
2438 18:06:45.002887
2439 18:06:45.003007 ==DQ 0 ==
2440 18:06:45.006275 Final DQ duty delay cell = 0
2441 18:06:45.009795 [0] MAX Duty = 5124%(X100), DQS PI = 50
2442 18:06:45.012917 [0] MIN Duty = 4969%(X100), DQS PI = 16
2443 18:06:45.013059 [0] AVG Duty = 5046%(X100)
2444 18:06:45.013151
2445 18:06:45.016603 ==DQ 1 ==
2446 18:06:45.019548 Final DQ duty delay cell = 0
2447 18:06:45.022876 [0] MAX Duty = 5124%(X100), DQS PI = 26
2448 18:06:45.026328 [0] MIN Duty = 5000%(X100), DQS PI = 18
2449 18:06:45.026434 [0] AVG Duty = 5062%(X100)
2450 18:06:45.026525
2451 18:06:45.029795 CH1 DQ 0 Duty spec in!! Max-Min= 155%
2452 18:06:45.029898
2453 18:06:45.033264 CH1 DQ 1 Duty spec in!! Max-Min= 124%
2454 18:06:45.039579 [DutyScan_Calibration_Flow] ====Done====
2455 18:06:45.042968 nWR fixed to 30
2456 18:06:45.043071 [ModeRegInit_LP4] CH0 RK0
2457 18:06:45.046245 [ModeRegInit_LP4] CH0 RK1
2458 18:06:45.049530 [ModeRegInit_LP4] CH1 RK0
2459 18:06:45.049635 [ModeRegInit_LP4] CH1 RK1
2460 18:06:45.053334 match AC timing 7
2461 18:06:45.056746 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2462 18:06:45.059634 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2463 18:06:45.066697 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2464 18:06:45.070143 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2465 18:06:45.076889 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2466 18:06:45.077016 ==
2467 18:06:45.080369 Dram Type= 6, Freq= 0, CH_0, rank 0
2468 18:06:45.083343 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2469 18:06:45.083448 ==
2470 18:06:45.090070 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2471 18:06:45.093087 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2472 18:06:45.103155 [CA 0] Center 40 (10~71) winsize 62
2473 18:06:45.106391 [CA 1] Center 39 (9~70) winsize 62
2474 18:06:45.109592 [CA 2] Center 36 (6~67) winsize 62
2475 18:06:45.113045 [CA 3] Center 36 (5~67) winsize 63
2476 18:06:45.116217 [CA 4] Center 35 (5~65) winsize 61
2477 18:06:45.119879 [CA 5] Center 34 (4~65) winsize 62
2478 18:06:45.119967
2479 18:06:45.123010 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2480 18:06:45.123083
2481 18:06:45.126283 [CATrainingPosCal] consider 1 rank data
2482 18:06:45.129800 u2DelayCellTimex100 = 270/100 ps
2483 18:06:45.132689 CA0 delay=40 (10~71),Diff = 6 PI (28 cell)
2484 18:06:45.139733 CA1 delay=39 (9~70),Diff = 5 PI (24 cell)
2485 18:06:45.143237 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2486 18:06:45.146358 CA3 delay=36 (5~67),Diff = 2 PI (9 cell)
2487 18:06:45.149997 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
2488 18:06:45.152855 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
2489 18:06:45.152953
2490 18:06:45.156345 CA PerBit enable=1, Macro0, CA PI delay=34
2491 18:06:45.156422
2492 18:06:45.159622 [CBTSetCACLKResult] CA Dly = 34
2493 18:06:45.159719 CS Dly: 7 (0~38)
2494 18:06:45.159808 ==
2495 18:06:45.162888 Dram Type= 6, Freq= 0, CH_0, rank 1
2496 18:06:45.170067 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2497 18:06:45.170169 ==
2498 18:06:45.173043 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2499 18:06:45.179794 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2500 18:06:45.189170 [CA 0] Center 39 (9~70) winsize 62
2501 18:06:45.192115 [CA 1] Center 40 (10~70) winsize 61
2502 18:06:45.195595 [CA 2] Center 36 (6~67) winsize 62
2503 18:06:45.199354 [CA 3] Center 35 (5~66) winsize 62
2504 18:06:45.202141 [CA 4] Center 34 (4~65) winsize 62
2505 18:06:45.205928 [CA 5] Center 34 (4~64) winsize 61
2506 18:06:45.206010
2507 18:06:45.208687 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2508 18:06:45.208783
2509 18:06:45.212083 [CATrainingPosCal] consider 2 rank data
2510 18:06:45.215663 u2DelayCellTimex100 = 270/100 ps
2511 18:06:45.219183 CA0 delay=40 (10~70),Diff = 6 PI (28 cell)
2512 18:06:45.222554 CA1 delay=40 (10~70),Diff = 6 PI (28 cell)
2513 18:06:45.229357 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2514 18:06:45.232391 CA3 delay=35 (5~66),Diff = 1 PI (4 cell)
2515 18:06:45.236052 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
2516 18:06:45.239086 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2517 18:06:45.239160
2518 18:06:45.242519 CA PerBit enable=1, Macro0, CA PI delay=34
2519 18:06:45.242590
2520 18:06:45.246045 [CBTSetCACLKResult] CA Dly = 34
2521 18:06:45.246146 CS Dly: 8 (0~41)
2522 18:06:45.246235
2523 18:06:45.249285 ----->DramcWriteLeveling(PI) begin...
2524 18:06:45.252726 ==
2525 18:06:45.252826 Dram Type= 6, Freq= 0, CH_0, rank 0
2526 18:06:45.259637 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2527 18:06:45.259743 ==
2528 18:06:45.262393 Write leveling (Byte 0): 31 => 31
2529 18:06:45.265708 Write leveling (Byte 1): 29 => 29
2530 18:06:45.265781 DramcWriteLeveling(PI) end<-----
2531 18:06:45.269474
2532 18:06:45.269547 ==
2533 18:06:45.272514 Dram Type= 6, Freq= 0, CH_0, rank 0
2534 18:06:45.276027 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2535 18:06:45.276101 ==
2536 18:06:45.279333 [Gating] SW mode calibration
2537 18:06:45.286212 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2538 18:06:45.289568 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2539 18:06:45.296004 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2540 18:06:45.299448 0 15 4 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
2541 18:06:45.302755 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2542 18:06:45.309329 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2543 18:06:45.312640 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2544 18:06:45.316071 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2545 18:06:45.322836 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2546 18:06:45.326157 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2547 18:06:45.329789 1 0 0 | B1->B0 | 3434 3030 | 1 1 | (1 0) (1 0)
2548 18:06:45.332915 1 0 4 | B1->B0 | 2e2e 2323 | 0 0 | (0 1) (0 0)
2549 18:06:45.339394 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2550 18:06:45.343287 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2551 18:06:45.346274 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2552 18:06:45.352900 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2553 18:06:45.356323 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2554 18:06:45.359999 1 0 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2555 18:06:45.366769 1 1 0 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
2556 18:06:45.369557 1 1 4 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
2557 18:06:45.372924 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2558 18:06:45.379641 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2559 18:06:45.383144 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2560 18:06:45.386505 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2561 18:06:45.393601 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2562 18:06:45.396543 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2563 18:06:45.400151 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2564 18:06:45.403635 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 18:06:45.410124 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2566 18:06:45.413075 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2567 18:06:45.416822 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2568 18:06:45.423538 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2569 18:06:45.426987 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2570 18:06:45.429980 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2571 18:06:45.436833 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2572 18:06:45.439973 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2573 18:06:45.443474 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2574 18:06:45.450378 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2575 18:06:45.453319 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2576 18:06:45.456740 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2577 18:06:45.463357 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2578 18:06:45.466677 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2579 18:06:45.470230 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2580 18:06:45.473704 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2581 18:06:45.477133 Total UI for P1: 0, mck2ui 16
2582 18:06:45.480492 best dqsien dly found for B0: ( 1, 4, 0)
2583 18:06:45.483335 Total UI for P1: 0, mck2ui 16
2584 18:06:45.486749 best dqsien dly found for B1: ( 1, 4, 2)
2585 18:06:45.490170 best DQS0 dly(MCK, UI, PI) = (1, 4, 0)
2586 18:06:45.493703 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2587 18:06:45.493778
2588 18:06:45.500102 best DQS0 P1 dly(MCK, UI, PI) = (1, 8, 0)
2589 18:06:45.503587 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2590 18:06:45.503690 [Gating] SW calibration Done
2591 18:06:45.507162 ==
2592 18:06:45.510340 Dram Type= 6, Freq= 0, CH_0, rank 0
2593 18:06:45.513827 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2594 18:06:45.513932 ==
2595 18:06:45.514021 RX Vref Scan: 0
2596 18:06:45.514108
2597 18:06:45.517297 RX Vref 0 -> 0, step: 1
2598 18:06:45.517368
2599 18:06:45.520163 RX Delay -40 -> 252, step: 8
2600 18:06:45.523941 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2601 18:06:45.526848 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2602 18:06:45.530793 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2603 18:06:45.537167 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2604 18:06:45.540730 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2605 18:06:45.543899 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2606 18:06:45.547310 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2607 18:06:45.550870 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2608 18:06:45.553746 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2609 18:06:45.560540 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2610 18:06:45.563919 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2611 18:06:45.567292 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2612 18:06:45.570853 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2613 18:06:45.573836 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2614 18:06:45.580761 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2615 18:06:45.583943 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2616 18:06:45.584068 ==
2617 18:06:45.587312 Dram Type= 6, Freq= 0, CH_0, rank 0
2618 18:06:45.590635 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2619 18:06:45.590755 ==
2620 18:06:45.594416 DQS Delay:
2621 18:06:45.594529 DQS0 = 0, DQS1 = 0
2622 18:06:45.594618 DQM Delay:
2623 18:06:45.597482 DQM0 = 116, DQM1 = 107
2624 18:06:45.597590 DQ Delay:
2625 18:06:45.600993 DQ0 =115, DQ1 =115, DQ2 =115, DQ3 =111
2626 18:06:45.604514 DQ4 =115, DQ5 =111, DQ6 =123, DQ7 =123
2627 18:06:45.607537 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =99
2628 18:06:45.611148 DQ12 =115, DQ13 =115, DQ14 =119, DQ15 =111
2629 18:06:45.611235
2630 18:06:45.614432
2631 18:06:45.614546 ==
2632 18:06:45.617959 Dram Type= 6, Freq= 0, CH_0, rank 0
2633 18:06:45.621448 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2634 18:06:45.621558 ==
2635 18:06:45.621622
2636 18:06:45.621683
2637 18:06:45.624242 TX Vref Scan disable
2638 18:06:45.624343 == TX Byte 0 ==
2639 18:06:45.627979 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2640 18:06:45.634233 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2641 18:06:45.634343 == TX Byte 1 ==
2642 18:06:45.637861 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2643 18:06:45.644731 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2644 18:06:45.644853 ==
2645 18:06:45.648138 Dram Type= 6, Freq= 0, CH_0, rank 0
2646 18:06:45.651297 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2647 18:06:45.651399 ==
2648 18:06:45.663269 TX Vref=22, minBit 7, minWin=24, winSum=420
2649 18:06:45.666706 TX Vref=24, minBit 5, minWin=25, winSum=423
2650 18:06:45.670208 TX Vref=26, minBit 1, minWin=26, winSum=430
2651 18:06:45.673974 TX Vref=28, minBit 1, minWin=26, winSum=431
2652 18:06:45.676581 TX Vref=30, minBit 7, minWin=26, winSum=438
2653 18:06:45.679996 TX Vref=32, minBit 4, minWin=26, winSum=435
2654 18:06:45.686649 [TxChooseVref] Worse bit 7, Min win 26, Win sum 438, Final Vref 30
2655 18:06:45.686756
2656 18:06:45.690309 Final TX Range 1 Vref 30
2657 18:06:45.690385
2658 18:06:45.690448 ==
2659 18:06:45.693307 Dram Type= 6, Freq= 0, CH_0, rank 0
2660 18:06:45.696821 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2661 18:06:45.696924 ==
2662 18:06:45.697023
2663 18:06:45.697112
2664 18:06:45.700495 TX Vref Scan disable
2665 18:06:45.703403 == TX Byte 0 ==
2666 18:06:45.706868 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2667 18:06:45.710227 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2668 18:06:45.713826 == TX Byte 1 ==
2669 18:06:45.717323 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2670 18:06:45.720555 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2671 18:06:45.720660
2672 18:06:45.723486 [DATLAT]
2673 18:06:45.723587 Freq=1200, CH0 RK0
2674 18:06:45.723678
2675 18:06:45.726835 DATLAT Default: 0xd
2676 18:06:45.726920 0, 0xFFFF, sum = 0
2677 18:06:45.730271 1, 0xFFFF, sum = 0
2678 18:06:45.730370 2, 0xFFFF, sum = 0
2679 18:06:45.733438 3, 0xFFFF, sum = 0
2680 18:06:45.733512 4, 0xFFFF, sum = 0
2681 18:06:45.736866 5, 0xFFFF, sum = 0
2682 18:06:45.736964 6, 0xFFFF, sum = 0
2683 18:06:45.740120 7, 0xFFFF, sum = 0
2684 18:06:45.740218 8, 0xFFFF, sum = 0
2685 18:06:45.743528 9, 0xFFFF, sum = 0
2686 18:06:45.743627 10, 0xFFFF, sum = 0
2687 18:06:45.747071 11, 0xFFFF, sum = 0
2688 18:06:45.747180 12, 0x0, sum = 1
2689 18:06:45.750472 13, 0x0, sum = 2
2690 18:06:45.750576 14, 0x0, sum = 3
2691 18:06:45.753904 15, 0x0, sum = 4
2692 18:06:45.754004 best_step = 13
2693 18:06:45.754094
2694 18:06:45.754179 ==
2695 18:06:45.757246 Dram Type= 6, Freq= 0, CH_0, rank 0
2696 18:06:45.763668 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2697 18:06:45.763791 ==
2698 18:06:45.763888 RX Vref Scan: 1
2699 18:06:45.763976
2700 18:06:45.766951 Set Vref Range= 32 -> 127
2701 18:06:45.767053
2702 18:06:45.770410 RX Vref 32 -> 127, step: 1
2703 18:06:45.770513
2704 18:06:45.770605 RX Delay -21 -> 252, step: 4
2705 18:06:45.770691
2706 18:06:45.773957 Set Vref, RX VrefLevel [Byte0]: 32
2707 18:06:45.776949 [Byte1]: 32
2708 18:06:45.781696
2709 18:06:45.781773 Set Vref, RX VrefLevel [Byte0]: 33
2710 18:06:45.784521 [Byte1]: 33
2711 18:06:45.789525
2712 18:06:45.789624 Set Vref, RX VrefLevel [Byte0]: 34
2713 18:06:45.792950 [Byte1]: 34
2714 18:06:45.797562
2715 18:06:45.797646 Set Vref, RX VrefLevel [Byte0]: 35
2716 18:06:45.800910 [Byte1]: 35
2717 18:06:45.805405
2718 18:06:45.805489 Set Vref, RX VrefLevel [Byte0]: 36
2719 18:06:45.808632 [Byte1]: 36
2720 18:06:45.813174
2721 18:06:45.813282 Set Vref, RX VrefLevel [Byte0]: 37
2722 18:06:45.816261 [Byte1]: 37
2723 18:06:45.821264
2724 18:06:45.821347 Set Vref, RX VrefLevel [Byte0]: 38
2725 18:06:45.824333 [Byte1]: 38
2726 18:06:45.829174
2727 18:06:45.829254 Set Vref, RX VrefLevel [Byte0]: 39
2728 18:06:45.832144 [Byte1]: 39
2729 18:06:45.837207
2730 18:06:45.837325 Set Vref, RX VrefLevel [Byte0]: 40
2731 18:06:45.840220 [Byte1]: 40
2732 18:06:45.844992
2733 18:06:45.845109 Set Vref, RX VrefLevel [Byte0]: 41
2734 18:06:45.848467 [Byte1]: 41
2735 18:06:45.852605
2736 18:06:45.852687 Set Vref, RX VrefLevel [Byte0]: 42
2737 18:06:45.856006 [Byte1]: 42
2738 18:06:45.860647
2739 18:06:45.860742 Set Vref, RX VrefLevel [Byte0]: 43
2740 18:06:45.863927 [Byte1]: 43
2741 18:06:45.868478
2742 18:06:45.868586 Set Vref, RX VrefLevel [Byte0]: 44
2743 18:06:45.871856 [Byte1]: 44
2744 18:06:45.876518
2745 18:06:45.876600 Set Vref, RX VrefLevel [Byte0]: 45
2746 18:06:45.880034 [Byte1]: 45
2747 18:06:45.884597
2748 18:06:45.884717 Set Vref, RX VrefLevel [Byte0]: 46
2749 18:06:45.888137 [Byte1]: 46
2750 18:06:45.892661
2751 18:06:45.892750 Set Vref, RX VrefLevel [Byte0]: 47
2752 18:06:45.896015 [Byte1]: 47
2753 18:06:45.900698
2754 18:06:45.900784 Set Vref, RX VrefLevel [Byte0]: 48
2755 18:06:45.903938 [Byte1]: 48
2756 18:06:45.908364
2757 18:06:45.908494 Set Vref, RX VrefLevel [Byte0]: 49
2758 18:06:45.911857 [Byte1]: 49
2759 18:06:45.916398
2760 18:06:45.916513 Set Vref, RX VrefLevel [Byte0]: 50
2761 18:06:45.919366 [Byte1]: 50
2762 18:06:45.923930
2763 18:06:45.924012 Set Vref, RX VrefLevel [Byte0]: 51
2764 18:06:45.927320 [Byte1]: 51
2765 18:06:45.931987
2766 18:06:45.932094 Set Vref, RX VrefLevel [Byte0]: 52
2767 18:06:45.935506 [Byte1]: 52
2768 18:06:45.940484
2769 18:06:45.940564 Set Vref, RX VrefLevel [Byte0]: 53
2770 18:06:45.943360 [Byte1]: 53
2771 18:06:45.947750
2772 18:06:45.947837 Set Vref, RX VrefLevel [Byte0]: 54
2773 18:06:45.951305 [Byte1]: 54
2774 18:06:45.955946
2775 18:06:45.956030 Set Vref, RX VrefLevel [Byte0]: 55
2776 18:06:45.959137 [Byte1]: 55
2777 18:06:45.963722
2778 18:06:45.963806 Set Vref, RX VrefLevel [Byte0]: 56
2779 18:06:45.967080 [Byte1]: 56
2780 18:06:45.971509
2781 18:06:45.971591 Set Vref, RX VrefLevel [Byte0]: 57
2782 18:06:45.974814 [Byte1]: 57
2783 18:06:45.979928
2784 18:06:45.980011 Set Vref, RX VrefLevel [Byte0]: 58
2785 18:06:45.982828 [Byte1]: 58
2786 18:06:45.988025
2787 18:06:45.988105 Set Vref, RX VrefLevel [Byte0]: 59
2788 18:06:45.990883 [Byte1]: 59
2789 18:06:45.995841
2790 18:06:45.995921 Set Vref, RX VrefLevel [Byte0]: 60
2791 18:06:45.998664 [Byte1]: 60
2792 18:06:46.003385
2793 18:06:46.003465 Set Vref, RX VrefLevel [Byte0]: 61
2794 18:06:46.006772 [Byte1]: 61
2795 18:06:46.011267
2796 18:06:46.011407 Set Vref, RX VrefLevel [Byte0]: 62
2797 18:06:46.014781 [Byte1]: 62
2798 18:06:46.019318
2799 18:06:46.019427 Set Vref, RX VrefLevel [Byte0]: 63
2800 18:06:46.022631 [Byte1]: 63
2801 18:06:46.027248
2802 18:06:46.027329 Set Vref, RX VrefLevel [Byte0]: 64
2803 18:06:46.030578 [Byte1]: 64
2804 18:06:46.035216
2805 18:06:46.035298 Set Vref, RX VrefLevel [Byte0]: 65
2806 18:06:46.038621 [Byte1]: 65
2807 18:06:46.043547
2808 18:06:46.043637 Set Vref, RX VrefLevel [Byte0]: 66
2809 18:06:46.046540 [Byte1]: 66
2810 18:06:46.050961
2811 18:06:46.051047 Set Vref, RX VrefLevel [Byte0]: 67
2812 18:06:46.054328 [Byte1]: 67
2813 18:06:46.058940
2814 18:06:46.059058 Set Vref, RX VrefLevel [Byte0]: 68
2815 18:06:46.061998 [Byte1]: 68
2816 18:06:46.066961
2817 18:06:46.067043 Final RX Vref Byte 0 = 51 to rank0
2818 18:06:46.070084 Final RX Vref Byte 1 = 51 to rank0
2819 18:06:46.074025 Final RX Vref Byte 0 = 51 to rank1
2820 18:06:46.077190 Final RX Vref Byte 1 = 51 to rank1==
2821 18:06:46.080310 Dram Type= 6, Freq= 0, CH_0, rank 0
2822 18:06:46.083883 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2823 18:06:46.087264 ==
2824 18:06:46.087345 DQS Delay:
2825 18:06:46.087409 DQS0 = 0, DQS1 = 0
2826 18:06:46.090777 DQM Delay:
2827 18:06:46.090856 DQM0 = 115, DQM1 = 104
2828 18:06:46.093771 DQ Delay:
2829 18:06:46.097231 DQ0 =116, DQ1 =114, DQ2 =112, DQ3 =114
2830 18:06:46.101044 DQ4 =116, DQ5 =108, DQ6 =120, DQ7 =122
2831 18:06:46.103781 DQ8 =92, DQ9 =90, DQ10 =104, DQ11 =96
2832 18:06:46.107494 DQ12 =112, DQ13 =110, DQ14 =118, DQ15 =114
2833 18:06:46.107593
2834 18:06:46.107683
2835 18:06:46.114239 [DQSOSCAuto] RK0, (LSB)MR18= 0xfeee, (MSB)MR19= 0x303, tDQSOscB0 = 417 ps tDQSOscB1 = 410 ps
2836 18:06:46.117719 CH0 RK0: MR19=303, MR18=FEEE
2837 18:06:46.123943 CH0_RK0: MR19=0x303, MR18=0xFEEE, DQSOSC=410, MR23=63, INC=39, DEC=26
2838 18:06:46.124050
2839 18:06:46.127316 ----->DramcWriteLeveling(PI) begin...
2840 18:06:46.127389 ==
2841 18:06:46.130852 Dram Type= 6, Freq= 0, CH_0, rank 1
2842 18:06:46.134208 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2843 18:06:46.134280 ==
2844 18:06:46.137652 Write leveling (Byte 0): 32 => 32
2845 18:06:46.140526 Write leveling (Byte 1): 29 => 29
2846 18:06:46.144122 DramcWriteLeveling(PI) end<-----
2847 18:06:46.144218
2848 18:06:46.144305 ==
2849 18:06:46.147846 Dram Type= 6, Freq= 0, CH_0, rank 1
2850 18:06:46.151127 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2851 18:06:46.151227 ==
2852 18:06:46.154406 [Gating] SW mode calibration
2853 18:06:46.160897 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2854 18:06:46.167851 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2855 18:06:46.171303 0 15 0 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (1 1)
2856 18:06:46.174599 0 15 4 | B1->B0 | 2929 3434 | 1 1 | (0 0) (1 1)
2857 18:06:46.181179 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2858 18:06:46.184741 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2859 18:06:46.188236 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2860 18:06:46.194619 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2861 18:06:46.197755 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
2862 18:06:46.201251 0 15 28 | B1->B0 | 3434 2525 | 1 0 | (1 1) (0 1)
2863 18:06:46.207705 1 0 0 | B1->B0 | 2c2c 2424 | 0 0 | (0 0) (0 0)
2864 18:06:46.211191 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2865 18:06:46.214565 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2866 18:06:46.221312 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2867 18:06:46.224756 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2868 18:06:46.228303 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2869 18:06:46.231166 1 0 24 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
2870 18:06:46.237971 1 0 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
2871 18:06:46.241986 1 1 0 | B1->B0 | 2a2a 3d3d | 0 0 | (0 0) (0 0)
2872 18:06:46.244842 1 1 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
2873 18:06:46.251807 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2874 18:06:46.254753 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2875 18:06:46.258750 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2876 18:06:46.264831 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2877 18:06:46.268455 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2878 18:06:46.271834 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2879 18:06:46.278441 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2880 18:06:46.281988 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2881 18:06:46.284926 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2882 18:06:46.291610 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2883 18:06:46.295127 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2884 18:06:46.298406 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2885 18:06:46.302082 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2886 18:06:46.308775 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2887 18:06:46.311936 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2888 18:06:46.315474 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2889 18:06:46.322089 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2890 18:06:46.325020 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2891 18:06:46.328527 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2892 18:06:46.335030 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2893 18:06:46.338352 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2894 18:06:46.341716 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2895 18:06:46.348724 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2896 18:06:46.348851 Total UI for P1: 0, mck2ui 16
2897 18:06:46.355156 best dqsien dly found for B0: ( 1, 3, 28)
2898 18:06:46.358606 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2899 18:06:46.362155 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2900 18:06:46.365399 Total UI for P1: 0, mck2ui 16
2901 18:06:46.368815 best dqsien dly found for B1: ( 1, 4, 2)
2902 18:06:46.371641 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2903 18:06:46.375108 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2904 18:06:46.375190
2905 18:06:46.378690 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2906 18:06:46.385171 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2907 18:06:46.385257 [Gating] SW calibration Done
2908 18:06:46.385321 ==
2909 18:06:46.388666 Dram Type= 6, Freq= 0, CH_0, rank 1
2910 18:06:46.395621 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2911 18:06:46.395715 ==
2912 18:06:46.395780 RX Vref Scan: 0
2913 18:06:46.395839
2914 18:06:46.398984 RX Vref 0 -> 0, step: 1
2915 18:06:46.399066
2916 18:06:46.401823 RX Delay -40 -> 252, step: 8
2917 18:06:46.405237 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2918 18:06:46.408781 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2919 18:06:46.412203 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2920 18:06:46.415131 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2921 18:06:46.422228 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2922 18:06:46.425516 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2923 18:06:46.428614 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2924 18:06:46.431842 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2925 18:06:46.435205 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2926 18:06:46.438912 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2927 18:06:46.445761 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2928 18:06:46.449507 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2929 18:06:46.452442 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2930 18:06:46.455577 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2931 18:06:46.462574 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2932 18:06:46.465429 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2933 18:06:46.465551 ==
2934 18:06:46.468790 Dram Type= 6, Freq= 0, CH_0, rank 1
2935 18:06:46.472293 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2936 18:06:46.472367 ==
2937 18:06:46.472428 DQS Delay:
2938 18:06:46.475973 DQS0 = 0, DQS1 = 0
2939 18:06:46.476041 DQM Delay:
2940 18:06:46.479393 DQM0 = 115, DQM1 = 106
2941 18:06:46.479461 DQ Delay:
2942 18:06:46.482814 DQ0 =115, DQ1 =115, DQ2 =111, DQ3 =115
2943 18:06:46.485673 DQ4 =115, DQ5 =103, DQ6 =123, DQ7 =123
2944 18:06:46.489120 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =99
2945 18:06:46.492537 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =111
2946 18:06:46.492616
2947 18:06:46.492694
2948 18:06:46.492769 ==
2949 18:06:46.495897 Dram Type= 6, Freq= 0, CH_0, rank 1
2950 18:06:46.502793 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2951 18:06:46.502876 ==
2952 18:06:46.502963
2953 18:06:46.503039
2954 18:06:46.503113 TX Vref Scan disable
2955 18:06:46.506238 == TX Byte 0 ==
2956 18:06:46.509525 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2957 18:06:46.513100 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2958 18:06:46.516502 == TX Byte 1 ==
2959 18:06:46.520005 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2960 18:06:46.522915 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2961 18:06:46.526280 ==
2962 18:06:46.529716 Dram Type= 6, Freq= 0, CH_0, rank 1
2963 18:06:46.532829 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2964 18:06:46.532904 ==
2965 18:06:46.544769 TX Vref=22, minBit 1, minWin=25, winSum=422
2966 18:06:46.547753 TX Vref=24, minBit 1, minWin=25, winSum=428
2967 18:06:46.551167 TX Vref=26, minBit 3, minWin=26, winSum=434
2968 18:06:46.554517 TX Vref=28, minBit 3, minWin=26, winSum=433
2969 18:06:46.557814 TX Vref=30, minBit 12, minWin=26, winSum=438
2970 18:06:46.561492 TX Vref=32, minBit 12, minWin=26, winSum=435
2971 18:06:46.568194 [TxChooseVref] Worse bit 12, Min win 26, Win sum 438, Final Vref 30
2972 18:06:46.568274
2973 18:06:46.571327 Final TX Range 1 Vref 30
2974 18:06:46.571401
2975 18:06:46.571485 ==
2976 18:06:46.574464 Dram Type= 6, Freq= 0, CH_0, rank 1
2977 18:06:46.577971 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2978 18:06:46.578045 ==
2979 18:06:46.578123
2980 18:06:46.581379
2981 18:06:46.581450 TX Vref Scan disable
2982 18:06:46.584450 == TX Byte 0 ==
2983 18:06:46.588119 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2984 18:06:46.591243 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2985 18:06:46.594617 == TX Byte 1 ==
2986 18:06:46.597995 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2987 18:06:46.601370 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2988 18:06:46.601446
2989 18:06:46.604869 [DATLAT]
2990 18:06:46.604946 Freq=1200, CH0 RK1
2991 18:06:46.605064
2992 18:06:46.608432 DATLAT Default: 0xd
2993 18:06:46.608502 0, 0xFFFF, sum = 0
2994 18:06:46.611885 1, 0xFFFF, sum = 0
2995 18:06:46.611957 2, 0xFFFF, sum = 0
2996 18:06:46.615175 3, 0xFFFF, sum = 0
2997 18:06:46.615248 4, 0xFFFF, sum = 0
2998 18:06:46.618495 5, 0xFFFF, sum = 0
2999 18:06:46.618575 6, 0xFFFF, sum = 0
3000 18:06:46.621382 7, 0xFFFF, sum = 0
3001 18:06:46.621455 8, 0xFFFF, sum = 0
3002 18:06:46.625272 9, 0xFFFF, sum = 0
3003 18:06:46.625351 10, 0xFFFF, sum = 0
3004 18:06:46.628236 11, 0xFFFF, sum = 0
3005 18:06:46.628307 12, 0x0, sum = 1
3006 18:06:46.631879 13, 0x0, sum = 2
3007 18:06:46.631951 14, 0x0, sum = 3
3008 18:06:46.635150 15, 0x0, sum = 4
3009 18:06:46.635227 best_step = 13
3010 18:06:46.635303
3011 18:06:46.635377 ==
3012 18:06:46.638398 Dram Type= 6, Freq= 0, CH_0, rank 1
3013 18:06:46.644955 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3014 18:06:46.645071 ==
3015 18:06:46.645155 RX Vref Scan: 0
3016 18:06:46.645230
3017 18:06:46.648621 RX Vref 0 -> 0, step: 1
3018 18:06:46.648704
3019 18:06:46.651503 RX Delay -21 -> 252, step: 4
3020 18:06:46.654927 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3021 18:06:46.658347 iDelay=195, Bit 1, Center 114 (43 ~ 186) 144
3022 18:06:46.664866 iDelay=195, Bit 2, Center 110 (39 ~ 182) 144
3023 18:06:46.668209 iDelay=195, Bit 3, Center 114 (43 ~ 186) 144
3024 18:06:46.671712 iDelay=195, Bit 4, Center 114 (47 ~ 182) 136
3025 18:06:46.675178 iDelay=195, Bit 5, Center 104 (35 ~ 174) 140
3026 18:06:46.678168 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3027 18:06:46.681467 iDelay=195, Bit 7, Center 120 (51 ~ 190) 140
3028 18:06:46.688565 iDelay=195, Bit 8, Center 94 (27 ~ 162) 136
3029 18:06:46.691671 iDelay=195, Bit 9, Center 92 (23 ~ 162) 140
3030 18:06:46.694898 iDelay=195, Bit 10, Center 106 (39 ~ 174) 136
3031 18:06:46.698616 iDelay=195, Bit 11, Center 94 (27 ~ 162) 136
3032 18:06:46.701616 iDelay=195, Bit 12, Center 110 (43 ~ 178) 136
3033 18:06:46.708264 iDelay=195, Bit 13, Center 110 (43 ~ 178) 136
3034 18:06:46.711589 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
3035 18:06:46.715300 iDelay=195, Bit 15, Center 112 (47 ~ 178) 132
3036 18:06:46.715374 ==
3037 18:06:46.718211 Dram Type= 6, Freq= 0, CH_0, rank 1
3038 18:06:46.721794 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3039 18:06:46.721870 ==
3040 18:06:46.725360 DQS Delay:
3041 18:06:46.725438 DQS0 = 0, DQS1 = 0
3042 18:06:46.728630 DQM Delay:
3043 18:06:46.728701 DQM0 = 114, DQM1 = 104
3044 18:06:46.728778 DQ Delay:
3045 18:06:46.735449 DQ0 =114, DQ1 =114, DQ2 =110, DQ3 =114
3046 18:06:46.738390 DQ4 =114, DQ5 =104, DQ6 =122, DQ7 =120
3047 18:06:46.742241 DQ8 =94, DQ9 =92, DQ10 =106, DQ11 =94
3048 18:06:46.745191 DQ12 =110, DQ13 =110, DQ14 =116, DQ15 =112
3049 18:06:46.745271
3050 18:06:46.745357
3051 18:06:46.752329 [DQSOSCAuto] RK1, (LSB)MR18= 0xfff0, (MSB)MR19= 0x303, tDQSOscB0 = 416 ps tDQSOscB1 = 410 ps
3052 18:06:46.755731 CH0 RK1: MR19=303, MR18=FFF0
3053 18:06:46.762173 CH0_RK1: MR19=0x303, MR18=0xFFF0, DQSOSC=410, MR23=63, INC=39, DEC=26
3054 18:06:46.765615 [RxdqsGatingPostProcess] freq 1200
3055 18:06:46.768707 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3056 18:06:46.772471 best DQS0 dly(2T, 0.5T) = (0, 12)
3057 18:06:46.775974 best DQS1 dly(2T, 0.5T) = (0, 12)
3058 18:06:46.778709 best DQS0 P1 dly(2T, 0.5T) = (1, 0)
3059 18:06:46.782306 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3060 18:06:46.785797 best DQS0 dly(2T, 0.5T) = (0, 11)
3061 18:06:46.788784 best DQS1 dly(2T, 0.5T) = (0, 12)
3062 18:06:46.792246 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3063 18:06:46.795698 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3064 18:06:46.799209 Pre-setting of DQS Precalculation
3065 18:06:46.802749 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3066 18:06:46.802821 ==
3067 18:06:46.805469 Dram Type= 6, Freq= 0, CH_1, rank 0
3068 18:06:46.809174 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3069 18:06:46.812322 ==
3070 18:06:46.815918 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3071 18:06:46.822993 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3072 18:06:46.830459 [CA 0] Center 38 (9~68) winsize 60
3073 18:06:46.833870 [CA 1] Center 38 (9~68) winsize 60
3074 18:06:46.837129 [CA 2] Center 35 (6~65) winsize 60
3075 18:06:46.840395 [CA 3] Center 34 (4~65) winsize 62
3076 18:06:46.843874 [CA 4] Center 34 (4~65) winsize 62
3077 18:06:46.847180 [CA 5] Center 34 (4~64) winsize 61
3078 18:06:46.847253
3079 18:06:46.850597 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3080 18:06:46.850682
3081 18:06:46.853976 [CATrainingPosCal] consider 1 rank data
3082 18:06:46.857416 u2DelayCellTimex100 = 270/100 ps
3083 18:06:46.860826 CA0 delay=38 (9~68),Diff = 4 PI (19 cell)
3084 18:06:46.864209 CA1 delay=38 (9~68),Diff = 4 PI (19 cell)
3085 18:06:46.867714 CA2 delay=35 (6~65),Diff = 1 PI (4 cell)
3086 18:06:46.874034 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
3087 18:06:46.877309 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3088 18:06:46.880702 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3089 18:06:46.880804
3090 18:06:46.884123 CA PerBit enable=1, Macro0, CA PI delay=34
3091 18:06:46.884237
3092 18:06:46.887649 [CBTSetCACLKResult] CA Dly = 34
3093 18:06:46.887731 CS Dly: 6 (0~37)
3094 18:06:46.887818 ==
3095 18:06:46.891031 Dram Type= 6, Freq= 0, CH_1, rank 1
3096 18:06:46.894405 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3097 18:06:46.897948 ==
3098 18:06:46.901443 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3099 18:06:46.907800 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3100 18:06:46.916190 [CA 0] Center 38 (9~68) winsize 60
3101 18:06:46.919711 [CA 1] Center 38 (9~68) winsize 60
3102 18:06:46.922581 [CA 2] Center 34 (4~65) winsize 62
3103 18:06:46.925827 [CA 3] Center 34 (4~65) winsize 62
3104 18:06:46.929474 [CA 4] Center 35 (5~65) winsize 61
3105 18:06:46.932770 [CA 5] Center 33 (3~64) winsize 62
3106 18:06:46.932850
3107 18:06:46.936223 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3108 18:06:46.936303
3109 18:06:46.939476 [CATrainingPosCal] consider 2 rank data
3110 18:06:46.942941 u2DelayCellTimex100 = 270/100 ps
3111 18:06:46.946444 CA0 delay=38 (9~68),Diff = 4 PI (19 cell)
3112 18:06:46.949447 CA1 delay=38 (9~68),Diff = 4 PI (19 cell)
3113 18:06:46.952817 CA2 delay=35 (6~65),Diff = 1 PI (4 cell)
3114 18:06:46.959942 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
3115 18:06:46.962788 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
3116 18:06:46.966801 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3117 18:06:46.966881
3118 18:06:46.969806 CA PerBit enable=1, Macro0, CA PI delay=34
3119 18:06:46.969881
3120 18:06:46.973050 [CBTSetCACLKResult] CA Dly = 34
3121 18:06:46.973128 CS Dly: 8 (0~41)
3122 18:06:46.973208
3123 18:06:46.976483 ----->DramcWriteLeveling(PI) begin...
3124 18:06:46.976557 ==
3125 18:06:46.979972 Dram Type= 6, Freq= 0, CH_1, rank 0
3126 18:06:46.986568 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3127 18:06:46.986653 ==
3128 18:06:46.990094 Write leveling (Byte 0): 27 => 27
3129 18:06:46.993032 Write leveling (Byte 1): 29 => 29
3130 18:06:46.993108 DramcWriteLeveling(PI) end<-----
3131 18:06:46.993187
3132 18:06:46.996519 ==
3133 18:06:47.000016 Dram Type= 6, Freq= 0, CH_1, rank 0
3134 18:06:47.002928 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3135 18:06:47.003007 ==
3136 18:06:47.006527 [Gating] SW mode calibration
3137 18:06:47.012895 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3138 18:06:47.016273 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3139 18:06:47.023352 0 15 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3140 18:06:47.026854 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3141 18:06:47.029783 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3142 18:06:47.036446 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3143 18:06:47.040119 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3144 18:06:47.043697 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3145 18:06:47.046628 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3146 18:06:47.053438 0 15 28 | B1->B0 | 3333 3434 | 1 1 | (1 0) (1 0)
3147 18:06:47.056799 1 0 0 | B1->B0 | 2929 2d2d | 1 0 | (1 0) (0 1)
3148 18:06:47.060307 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3149 18:06:47.066788 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3150 18:06:47.070379 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3151 18:06:47.073321 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3152 18:06:47.080246 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3153 18:06:47.083650 1 0 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3154 18:06:47.086826 1 0 28 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
3155 18:06:47.093725 1 1 0 | B1->B0 | 3d3d 3131 | 0 1 | (1 1) (0 0)
3156 18:06:47.096677 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3157 18:06:47.100753 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3158 18:06:47.107246 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3159 18:06:47.110119 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3160 18:06:47.113561 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3161 18:06:47.120473 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3162 18:06:47.123794 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3163 18:06:47.126701 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3164 18:06:47.130216 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3165 18:06:47.137237 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3166 18:06:47.140558 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3167 18:06:47.143857 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3168 18:06:47.150501 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3169 18:06:47.153890 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3170 18:06:47.157385 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3171 18:06:47.164138 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3172 18:06:47.167074 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3173 18:06:47.170536 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3174 18:06:47.177485 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3175 18:06:47.180895 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3176 18:06:47.184193 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3177 18:06:47.187151 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3178 18:06:47.193634 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3179 18:06:47.197146 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3180 18:06:47.200359 Total UI for P1: 0, mck2ui 16
3181 18:06:47.204379 best dqsien dly found for B0: ( 1, 3, 28)
3182 18:06:47.207475 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3183 18:06:47.210867 Total UI for P1: 0, mck2ui 16
3184 18:06:47.213879 best dqsien dly found for B1: ( 1, 4, 0)
3185 18:06:47.217181 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3186 18:06:47.220744 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
3187 18:06:47.220817
3188 18:06:47.227269 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3189 18:06:47.230758 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
3190 18:06:47.230831 [Gating] SW calibration Done
3191 18:06:47.234191 ==
3192 18:06:47.234263 Dram Type= 6, Freq= 0, CH_1, rank 0
3193 18:06:47.240602 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3194 18:06:47.240719 ==
3195 18:06:47.240781 RX Vref Scan: 0
3196 18:06:47.240839
3197 18:06:47.244045 RX Vref 0 -> 0, step: 1
3198 18:06:47.244119
3199 18:06:47.247666 RX Delay -40 -> 252, step: 8
3200 18:06:47.250943 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3201 18:06:47.254176 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3202 18:06:47.257903 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3203 18:06:47.264190 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3204 18:06:47.267688 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3205 18:06:47.270934 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3206 18:06:47.274458 iDelay=200, Bit 6, Center 127 (64 ~ 191) 128
3207 18:06:47.278089 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3208 18:06:47.281167 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3209 18:06:47.287619 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3210 18:06:47.291074 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
3211 18:06:47.294510 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3212 18:06:47.297705 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3213 18:06:47.301325 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
3214 18:06:47.308042 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3215 18:06:47.311494 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3216 18:06:47.311574 ==
3217 18:06:47.314745 Dram Type= 6, Freq= 0, CH_1, rank 0
3218 18:06:47.317846 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3219 18:06:47.317962 ==
3220 18:06:47.321742 DQS Delay:
3221 18:06:47.321812 DQS0 = 0, DQS1 = 0
3222 18:06:47.321878 DQM Delay:
3223 18:06:47.324759 DQM0 = 116, DQM1 = 108
3224 18:06:47.324829 DQ Delay:
3225 18:06:47.328566 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =119
3226 18:06:47.331582 DQ4 =111, DQ5 =127, DQ6 =127, DQ7 =115
3227 18:06:47.334785 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =107
3228 18:06:47.338084 DQ12 =123, DQ13 =115, DQ14 =111, DQ15 =111
3229 18:06:47.341450
3230 18:06:47.341518
3231 18:06:47.341582 ==
3232 18:06:47.344491 Dram Type= 6, Freq= 0, CH_1, rank 0
3233 18:06:47.348049 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3234 18:06:47.348115 ==
3235 18:06:47.348172
3236 18:06:47.348233
3237 18:06:47.351514 TX Vref Scan disable
3238 18:06:47.351591 == TX Byte 0 ==
3239 18:06:47.358120 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3240 18:06:47.361371 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3241 18:06:47.361510 == TX Byte 1 ==
3242 18:06:47.368229 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3243 18:06:47.371605 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3244 18:06:47.371692 ==
3245 18:06:47.374614 Dram Type= 6, Freq= 0, CH_1, rank 0
3246 18:06:47.378012 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3247 18:06:47.378092 ==
3248 18:06:47.390385 TX Vref=22, minBit 0, minWin=25, winSum=406
3249 18:06:47.393795 TX Vref=24, minBit 1, minWin=25, winSum=417
3250 18:06:47.396760 TX Vref=26, minBit 2, minWin=25, winSum=424
3251 18:06:47.400214 TX Vref=28, minBit 0, minWin=26, winSum=425
3252 18:06:47.403513 TX Vref=30, minBit 1, minWin=26, winSum=428
3253 18:06:47.407090 TX Vref=32, minBit 3, minWin=25, winSum=424
3254 18:06:47.413974 [TxChooseVref] Worse bit 1, Min win 26, Win sum 428, Final Vref 30
3255 18:06:47.414076
3256 18:06:47.417526 Final TX Range 1 Vref 30
3257 18:06:47.417609
3258 18:06:47.417673 ==
3259 18:06:47.420406 Dram Type= 6, Freq= 0, CH_1, rank 0
3260 18:06:47.423981 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3261 18:06:47.424064 ==
3262 18:06:47.424129
3263 18:06:47.424188
3264 18:06:47.427484 TX Vref Scan disable
3265 18:06:47.430876 == TX Byte 0 ==
3266 18:06:47.434121 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3267 18:06:47.437196 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3268 18:06:47.440638 == TX Byte 1 ==
3269 18:06:47.444139 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3270 18:06:47.447519 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3271 18:06:47.447604
3272 18:06:47.450978 [DATLAT]
3273 18:06:47.451065 Freq=1200, CH1 RK0
3274 18:06:47.451180
3275 18:06:47.454329 DATLAT Default: 0xd
3276 18:06:47.454409 0, 0xFFFF, sum = 0
3277 18:06:47.457308 1, 0xFFFF, sum = 0
3278 18:06:47.457392 2, 0xFFFF, sum = 0
3279 18:06:47.460725 3, 0xFFFF, sum = 0
3280 18:06:47.460808 4, 0xFFFF, sum = 0
3281 18:06:47.464141 5, 0xFFFF, sum = 0
3282 18:06:47.464256 6, 0xFFFF, sum = 0
3283 18:06:47.467463 7, 0xFFFF, sum = 0
3284 18:06:47.467546 8, 0xFFFF, sum = 0
3285 18:06:47.470807 9, 0xFFFF, sum = 0
3286 18:06:47.470890 10, 0xFFFF, sum = 0
3287 18:06:47.474252 11, 0xFFFF, sum = 0
3288 18:06:47.474334 12, 0x0, sum = 1
3289 18:06:47.477926 13, 0x0, sum = 2
3290 18:06:47.478010 14, 0x0, sum = 3
3291 18:06:47.480884 15, 0x0, sum = 4
3292 18:06:47.481030 best_step = 13
3293 18:06:47.481097
3294 18:06:47.481158 ==
3295 18:06:47.484411 Dram Type= 6, Freq= 0, CH_1, rank 0
3296 18:06:47.491189 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3297 18:06:47.491308 ==
3298 18:06:47.491403 RX Vref Scan: 1
3299 18:06:47.491491
3300 18:06:47.494260 Set Vref Range= 32 -> 127
3301 18:06:47.494341
3302 18:06:47.497744 RX Vref 32 -> 127, step: 1
3303 18:06:47.497842
3304 18:06:47.497943 RX Delay -21 -> 252, step: 4
3305 18:06:47.498019
3306 18:06:47.501175 Set Vref, RX VrefLevel [Byte0]: 32
3307 18:06:47.504057 [Byte1]: 32
3308 18:06:47.508747
3309 18:06:47.508832 Set Vref, RX VrefLevel [Byte0]: 33
3310 18:06:47.512124 [Byte1]: 33
3311 18:06:47.516379
3312 18:06:47.516468 Set Vref, RX VrefLevel [Byte0]: 34
3313 18:06:47.519580 [Byte1]: 34
3314 18:06:47.524522
3315 18:06:47.524608 Set Vref, RX VrefLevel [Byte0]: 35
3316 18:06:47.527953 [Byte1]: 35
3317 18:06:47.532610
3318 18:06:47.532695 Set Vref, RX VrefLevel [Byte0]: 36
3319 18:06:47.536036 [Byte1]: 36
3320 18:06:47.540243
3321 18:06:47.540324 Set Vref, RX VrefLevel [Byte0]: 37
3322 18:06:47.543551 [Byte1]: 37
3323 18:06:47.548284
3324 18:06:47.548365 Set Vref, RX VrefLevel [Byte0]: 38
3325 18:06:47.551597 [Byte1]: 38
3326 18:06:47.556212
3327 18:06:47.556293 Set Vref, RX VrefLevel [Byte0]: 39
3328 18:06:47.559621 [Byte1]: 39
3329 18:06:47.563837
3330 18:06:47.563920 Set Vref, RX VrefLevel [Byte0]: 40
3331 18:06:47.567329 [Byte1]: 40
3332 18:06:47.571970
3333 18:06:47.572052 Set Vref, RX VrefLevel [Byte0]: 41
3334 18:06:47.575115 [Byte1]: 41
3335 18:06:47.579770
3336 18:06:47.579854 Set Vref, RX VrefLevel [Byte0]: 42
3337 18:06:47.582913 [Byte1]: 42
3338 18:06:47.587604
3339 18:06:47.587705 Set Vref, RX VrefLevel [Byte0]: 43
3340 18:06:47.591036 [Byte1]: 43
3341 18:06:47.595466
3342 18:06:47.595542 Set Vref, RX VrefLevel [Byte0]: 44
3343 18:06:47.598973 [Byte1]: 44
3344 18:06:47.603571
3345 18:06:47.603651 Set Vref, RX VrefLevel [Byte0]: 45
3346 18:06:47.607104 [Byte1]: 45
3347 18:06:47.611159
3348 18:06:47.611232 Set Vref, RX VrefLevel [Byte0]: 46
3349 18:06:47.614688 [Byte1]: 46
3350 18:06:47.619623
3351 18:06:47.619703 Set Vref, RX VrefLevel [Byte0]: 47
3352 18:06:47.622454 [Byte1]: 47
3353 18:06:47.627282
3354 18:06:47.627354 Set Vref, RX VrefLevel [Byte0]: 48
3355 18:06:47.630940 [Byte1]: 48
3356 18:06:47.635008
3357 18:06:47.635081 Set Vref, RX VrefLevel [Byte0]: 49
3358 18:06:47.638482 [Byte1]: 49
3359 18:06:47.643050
3360 18:06:47.643121 Set Vref, RX VrefLevel [Byte0]: 50
3361 18:06:47.646500 [Byte1]: 50
3362 18:06:47.651059
3363 18:06:47.651139 Set Vref, RX VrefLevel [Byte0]: 51
3364 18:06:47.654549 [Byte1]: 51
3365 18:06:47.659253
3366 18:06:47.659332 Set Vref, RX VrefLevel [Byte0]: 52
3367 18:06:47.662154 [Byte1]: 52
3368 18:06:47.667154
3369 18:06:47.667231 Set Vref, RX VrefLevel [Byte0]: 53
3370 18:06:47.670197 [Byte1]: 53
3371 18:06:47.674861
3372 18:06:47.674935 Set Vref, RX VrefLevel [Byte0]: 54
3373 18:06:47.678295 [Byte1]: 54
3374 18:06:47.682667
3375 18:06:47.682747 Set Vref, RX VrefLevel [Byte0]: 55
3376 18:06:47.686476 [Byte1]: 55
3377 18:06:47.690554
3378 18:06:47.690624 Set Vref, RX VrefLevel [Byte0]: 56
3379 18:06:47.694067 [Byte1]: 56
3380 18:06:47.698763
3381 18:06:47.698842 Set Vref, RX VrefLevel [Byte0]: 57
3382 18:06:47.701708 [Byte1]: 57
3383 18:06:47.706616
3384 18:06:47.706687 Set Vref, RX VrefLevel [Byte0]: 58
3385 18:06:47.709772 [Byte1]: 58
3386 18:06:47.714433
3387 18:06:47.714551 Set Vref, RX VrefLevel [Byte0]: 59
3388 18:06:47.717744 [Byte1]: 59
3389 18:06:47.722331
3390 18:06:47.722411 Set Vref, RX VrefLevel [Byte0]: 60
3391 18:06:47.725731 [Byte1]: 60
3392 18:06:47.730094
3393 18:06:47.730182 Set Vref, RX VrefLevel [Byte0]: 61
3394 18:06:47.733351 [Byte1]: 61
3395 18:06:47.738243
3396 18:06:47.738326 Set Vref, RX VrefLevel [Byte0]: 62
3397 18:06:47.744512 [Byte1]: 62
3398 18:06:47.744593
3399 18:06:47.747993 Set Vref, RX VrefLevel [Byte0]: 63
3400 18:06:47.751500 [Byte1]: 63
3401 18:06:47.751618
3402 18:06:47.754438 Set Vref, RX VrefLevel [Byte0]: 64
3403 18:06:47.757903 [Byte1]: 64
3404 18:06:47.761956
3405 18:06:47.762061 Set Vref, RX VrefLevel [Byte0]: 65
3406 18:06:47.765464 [Byte1]: 65
3407 18:06:47.769870
3408 18:06:47.769989 Set Vref, RX VrefLevel [Byte0]: 66
3409 18:06:47.773432 [Byte1]: 66
3410 18:06:47.777683
3411 18:06:47.777806 Set Vref, RX VrefLevel [Byte0]: 67
3412 18:06:47.780936 [Byte1]: 67
3413 18:06:47.785589
3414 18:06:47.785680 Set Vref, RX VrefLevel [Byte0]: 68
3415 18:06:47.789047 [Byte1]: 68
3416 18:06:47.793802
3417 18:06:47.793888 Set Vref, RX VrefLevel [Byte0]: 69
3418 18:06:47.797172 [Byte1]: 69
3419 18:06:47.801663
3420 18:06:47.801752 Set Vref, RX VrefLevel [Byte0]: 70
3421 18:06:47.804876 [Byte1]: 70
3422 18:06:47.809536
3423 18:06:47.809626 Set Vref, RX VrefLevel [Byte0]: 71
3424 18:06:47.813170 [Byte1]: 71
3425 18:06:47.817464
3426 18:06:47.817548 Final RX Vref Byte 0 = 58 to rank0
3427 18:06:47.820928 Final RX Vref Byte 1 = 52 to rank0
3428 18:06:47.824116 Final RX Vref Byte 0 = 58 to rank1
3429 18:06:47.827445 Final RX Vref Byte 1 = 52 to rank1==
3430 18:06:47.831009 Dram Type= 6, Freq= 0, CH_1, rank 0
3431 18:06:47.834210 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3432 18:06:47.837562 ==
3433 18:06:47.837662 DQS Delay:
3434 18:06:47.837726 DQS0 = 0, DQS1 = 0
3435 18:06:47.840863 DQM Delay:
3436 18:06:47.840950 DQM0 = 116, DQM1 = 109
3437 18:06:47.844103 DQ Delay:
3438 18:06:47.847839 DQ0 =118, DQ1 =110, DQ2 =106, DQ3 =114
3439 18:06:47.850820 DQ4 =116, DQ5 =124, DQ6 =126, DQ7 =114
3440 18:06:47.854326 DQ8 =98, DQ9 =98, DQ10 =114, DQ11 =106
3441 18:06:47.857858 DQ12 =116, DQ13 =114, DQ14 =116, DQ15 =114
3442 18:06:47.857943
3443 18:06:47.858008
3444 18:06:47.864236 [DQSOSCAuto] RK0, (LSB)MR18= 0xe5, (MSB)MR19= 0x403, tDQSOscB0 = 421 ps tDQSOscB1 = 410 ps
3445 18:06:47.867705 CH1 RK0: MR19=403, MR18=E5
3446 18:06:47.874397 CH1_RK0: MR19=0x403, MR18=0xE5, DQSOSC=410, MR23=63, INC=39, DEC=26
3447 18:06:47.874494
3448 18:06:47.877948 ----->DramcWriteLeveling(PI) begin...
3449 18:06:47.878033 ==
3450 18:06:47.881388 Dram Type= 6, Freq= 0, CH_1, rank 1
3451 18:06:47.884350 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3452 18:06:47.884434 ==
3453 18:06:47.888321 Write leveling (Byte 0): 27 => 27
3454 18:06:47.891144 Write leveling (Byte 1): 27 => 27
3455 18:06:47.894467 DramcWriteLeveling(PI) end<-----
3456 18:06:47.894553
3457 18:06:47.894617 ==
3458 18:06:47.898092 Dram Type= 6, Freq= 0, CH_1, rank 1
3459 18:06:47.901577 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3460 18:06:47.901715 ==
3461 18:06:47.904475 [Gating] SW mode calibration
3462 18:06:47.911280 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3463 18:06:47.917958 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3464 18:06:47.921499 0 15 0 | B1->B0 | 2a2a 3434 | 1 1 | (1 1) (1 1)
3465 18:06:47.925033 0 15 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
3466 18:06:47.931231 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3467 18:06:47.934567 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3468 18:06:47.937890 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3469 18:06:47.944864 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3470 18:06:47.947855 0 15 24 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 1)
3471 18:06:47.951526 0 15 28 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
3472 18:06:47.957770 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3473 18:06:47.961312 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3474 18:06:47.964814 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3475 18:06:47.971762 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3476 18:06:47.974817 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3477 18:06:47.978103 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3478 18:06:47.981560 1 0 24 | B1->B0 | 2424 4343 | 0 0 | (0 0) (0 0)
3479 18:06:47.988461 1 0 28 | B1->B0 | 4141 4646 | 1 0 | (0 0) (0 0)
3480 18:06:47.991341 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3481 18:06:47.994842 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3482 18:06:48.001806 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3483 18:06:48.004753 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3484 18:06:48.008282 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3485 18:06:48.014699 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3486 18:06:48.018297 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3487 18:06:48.021460 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
3488 18:06:48.028447 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3489 18:06:48.031346 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3490 18:06:48.034864 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3491 18:06:48.041800 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3492 18:06:48.045121 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3493 18:06:48.048081 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3494 18:06:48.055070 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3495 18:06:48.058019 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3496 18:06:48.061395 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3497 18:06:48.067849 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3498 18:06:48.071438 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3499 18:06:48.074926 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3500 18:06:48.078263 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3501 18:06:48.084765 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3502 18:06:48.088297 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3503 18:06:48.091598 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3504 18:06:48.094873 Total UI for P1: 0, mck2ui 16
3505 18:06:48.098157 best dqsien dly found for B0: ( 1, 3, 22)
3506 18:06:48.104950 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3507 18:06:48.105071 Total UI for P1: 0, mck2ui 16
3508 18:06:48.111478 best dqsien dly found for B1: ( 1, 3, 28)
3509 18:06:48.114898 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3510 18:06:48.118458 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3511 18:06:48.118535
3512 18:06:48.121916 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3513 18:06:48.125253 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3514 18:06:48.128454 [Gating] SW calibration Done
3515 18:06:48.128524 ==
3516 18:06:48.131813 Dram Type= 6, Freq= 0, CH_1, rank 1
3517 18:06:48.134679 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3518 18:06:48.134766 ==
3519 18:06:48.138256 RX Vref Scan: 0
3520 18:06:48.138327
3521 18:06:48.138387 RX Vref 0 -> 0, step: 1
3522 18:06:48.138444
3523 18:06:48.141640 RX Delay -40 -> 252, step: 8
3524 18:06:48.145254 iDelay=192, Bit 0, Center 111 (40 ~ 183) 144
3525 18:06:48.151886 iDelay=192, Bit 1, Center 111 (40 ~ 183) 144
3526 18:06:48.154707 iDelay=192, Bit 2, Center 103 (32 ~ 175) 144
3527 18:06:48.158140 iDelay=192, Bit 3, Center 115 (48 ~ 183) 136
3528 18:06:48.161754 iDelay=192, Bit 4, Center 111 (40 ~ 183) 144
3529 18:06:48.164695 iDelay=192, Bit 5, Center 123 (56 ~ 191) 136
3530 18:06:48.171381 iDelay=192, Bit 6, Center 119 (48 ~ 191) 144
3531 18:06:48.174755 iDelay=192, Bit 7, Center 107 (40 ~ 175) 136
3532 18:06:48.178179 iDelay=192, Bit 8, Center 103 (32 ~ 175) 144
3533 18:06:48.181443 iDelay=192, Bit 9, Center 95 (24 ~ 167) 144
3534 18:06:48.184877 iDelay=192, Bit 10, Center 111 (40 ~ 183) 144
3535 18:06:48.191452 iDelay=192, Bit 11, Center 103 (32 ~ 175) 144
3536 18:06:48.194687 iDelay=192, Bit 12, Center 115 (48 ~ 183) 136
3537 18:06:48.198234 iDelay=192, Bit 13, Center 123 (56 ~ 191) 136
3538 18:06:48.201234 iDelay=192, Bit 14, Center 119 (48 ~ 191) 144
3539 18:06:48.207886 iDelay=192, Bit 15, Center 119 (48 ~ 191) 144
3540 18:06:48.207968 ==
3541 18:06:48.211068 Dram Type= 6, Freq= 0, CH_1, rank 1
3542 18:06:48.215273 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3543 18:06:48.215351 ==
3544 18:06:48.215414 DQS Delay:
3545 18:06:48.218057 DQS0 = 0, DQS1 = 0
3546 18:06:48.218152 DQM Delay:
3547 18:06:48.220900 DQM0 = 112, DQM1 = 111
3548 18:06:48.221031 DQ Delay:
3549 18:06:48.224404 DQ0 =111, DQ1 =111, DQ2 =103, DQ3 =115
3550 18:06:48.227757 DQ4 =111, DQ5 =123, DQ6 =119, DQ7 =107
3551 18:06:48.231263 DQ8 =103, DQ9 =95, DQ10 =111, DQ11 =103
3552 18:06:48.234456 DQ12 =115, DQ13 =123, DQ14 =119, DQ15 =119
3553 18:06:48.234532
3554 18:06:48.234599
3555 18:06:48.234656 ==
3556 18:06:48.237738 Dram Type= 6, Freq= 0, CH_1, rank 1
3557 18:06:48.244561 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3558 18:06:48.244644 ==
3559 18:06:48.244706
3560 18:06:48.244762
3561 18:06:48.247443 TX Vref Scan disable
3562 18:06:48.247513 == TX Byte 0 ==
3563 18:06:48.250918 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3564 18:06:48.257786 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3565 18:06:48.257874 == TX Byte 1 ==
3566 18:06:48.260705 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3567 18:06:48.267723 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3568 18:06:48.267809 ==
3569 18:06:48.270619 Dram Type= 6, Freq= 0, CH_1, rank 1
3570 18:06:48.273993 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3571 18:06:48.274114 ==
3572 18:06:48.286269 TX Vref=22, minBit 1, minWin=25, winSum=414
3573 18:06:48.289214 TX Vref=24, minBit 3, minWin=25, winSum=415
3574 18:06:48.292597 TX Vref=26, minBit 2, minWin=26, winSum=428
3575 18:06:48.295874 TX Vref=28, minBit 3, minWin=25, winSum=428
3576 18:06:48.299009 TX Vref=30, minBit 2, minWin=26, winSum=430
3577 18:06:48.302316 TX Vref=32, minBit 2, minWin=26, winSum=426
3578 18:06:48.309259 [TxChooseVref] Worse bit 2, Min win 26, Win sum 430, Final Vref 30
3579 18:06:48.309359
3580 18:06:48.312394 Final TX Range 1 Vref 30
3581 18:06:48.312476
3582 18:06:48.312540 ==
3583 18:06:48.315932 Dram Type= 6, Freq= 0, CH_1, rank 1
3584 18:06:48.318795 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3585 18:06:48.318878 ==
3586 18:06:48.322571
3587 18:06:48.322652
3588 18:06:48.322716 TX Vref Scan disable
3589 18:06:48.325622 == TX Byte 0 ==
3590 18:06:48.329072 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3591 18:06:48.332840 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3592 18:06:48.336097 == TX Byte 1 ==
3593 18:06:48.339039 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3594 18:06:48.342594 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3595 18:06:48.342683
3596 18:06:48.345843 [DATLAT]
3597 18:06:48.345951 Freq=1200, CH1 RK1
3598 18:06:48.346043
3599 18:06:48.349295 DATLAT Default: 0xd
3600 18:06:48.349397 0, 0xFFFF, sum = 0
3601 18:06:48.352272 1, 0xFFFF, sum = 0
3602 18:06:48.352399 2, 0xFFFF, sum = 0
3603 18:06:48.355810 3, 0xFFFF, sum = 0
3604 18:06:48.355893 4, 0xFFFF, sum = 0
3605 18:06:48.359060 5, 0xFFFF, sum = 0
3606 18:06:48.359142 6, 0xFFFF, sum = 0
3607 18:06:48.362494 7, 0xFFFF, sum = 0
3608 18:06:48.362578 8, 0xFFFF, sum = 0
3609 18:06:48.366003 9, 0xFFFF, sum = 0
3610 18:06:48.366126 10, 0xFFFF, sum = 0
3611 18:06:48.369418 11, 0xFFFF, sum = 0
3612 18:06:48.369520 12, 0x0, sum = 1
3613 18:06:48.372452 13, 0x0, sum = 2
3614 18:06:48.372535 14, 0x0, sum = 3
3615 18:06:48.375930 15, 0x0, sum = 4
3616 18:06:48.376015 best_step = 13
3617 18:06:48.376079
3618 18:06:48.376138 ==
3619 18:06:48.379594 Dram Type= 6, Freq= 0, CH_1, rank 1
3620 18:06:48.386235 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3621 18:06:48.386327 ==
3622 18:06:48.386392 RX Vref Scan: 0
3623 18:06:48.386452
3624 18:06:48.389674 RX Vref 0 -> 0, step: 1
3625 18:06:48.389758
3626 18:06:48.392564 RX Delay -21 -> 252, step: 4
3627 18:06:48.396069 iDelay=191, Bit 0, Center 112 (43 ~ 182) 140
3628 18:06:48.399615 iDelay=191, Bit 1, Center 108 (43 ~ 174) 132
3629 18:06:48.406158 iDelay=191, Bit 2, Center 106 (43 ~ 170) 128
3630 18:06:48.409958 iDelay=191, Bit 3, Center 112 (47 ~ 178) 132
3631 18:06:48.413034 iDelay=191, Bit 4, Center 112 (47 ~ 178) 132
3632 18:06:48.416467 iDelay=191, Bit 5, Center 124 (59 ~ 190) 132
3633 18:06:48.419940 iDelay=191, Bit 6, Center 122 (55 ~ 190) 136
3634 18:06:48.423029 iDelay=191, Bit 7, Center 110 (47 ~ 174) 128
3635 18:06:48.429581 iDelay=191, Bit 8, Center 96 (31 ~ 162) 132
3636 18:06:48.432912 iDelay=191, Bit 9, Center 98 (35 ~ 162) 128
3637 18:06:48.436314 iDelay=191, Bit 10, Center 110 (43 ~ 178) 136
3638 18:06:48.439737 iDelay=191, Bit 11, Center 104 (39 ~ 170) 132
3639 18:06:48.442646 iDelay=191, Bit 12, Center 114 (51 ~ 178) 128
3640 18:06:48.449838 iDelay=191, Bit 13, Center 120 (55 ~ 186) 132
3641 18:06:48.453214 iDelay=191, Bit 14, Center 118 (55 ~ 182) 128
3642 18:06:48.456408 iDelay=191, Bit 15, Center 118 (55 ~ 182) 128
3643 18:06:48.456490 ==
3644 18:06:48.459890 Dram Type= 6, Freq= 0, CH_1, rank 1
3645 18:06:48.463238 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3646 18:06:48.463335 ==
3647 18:06:48.466777 DQS Delay:
3648 18:06:48.466861 DQS0 = 0, DQS1 = 0
3649 18:06:48.469686 DQM Delay:
3650 18:06:48.469787 DQM0 = 113, DQM1 = 109
3651 18:06:48.469880 DQ Delay:
3652 18:06:48.476111 DQ0 =112, DQ1 =108, DQ2 =106, DQ3 =112
3653 18:06:48.479702 DQ4 =112, DQ5 =124, DQ6 =122, DQ7 =110
3654 18:06:48.483303 DQ8 =96, DQ9 =98, DQ10 =110, DQ11 =104
3655 18:06:48.486370 DQ12 =114, DQ13 =120, DQ14 =118, DQ15 =118
3656 18:06:48.486451
3657 18:06:48.486515
3658 18:06:48.492841 [DQSOSCAuto] RK1, (LSB)MR18= 0xfa01, (MSB)MR19= 0x304, tDQSOscB0 = 409 ps tDQSOscB1 = 412 ps
3659 18:06:48.496345 CH1 RK1: MR19=304, MR18=FA01
3660 18:06:48.503272 CH1_RK1: MR19=0x304, MR18=0xFA01, DQSOSC=409, MR23=63, INC=39, DEC=26
3661 18:06:48.506248 [RxdqsGatingPostProcess] freq 1200
3662 18:06:48.509531 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3663 18:06:48.512904 best DQS0 dly(2T, 0.5T) = (0, 11)
3664 18:06:48.516665 best DQS1 dly(2T, 0.5T) = (0, 12)
3665 18:06:48.519513 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3666 18:06:48.522982 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3667 18:06:48.526257 best DQS0 dly(2T, 0.5T) = (0, 11)
3668 18:06:48.529767 best DQS1 dly(2T, 0.5T) = (0, 11)
3669 18:06:48.533355 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3670 18:06:48.536738 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3671 18:06:48.539573 Pre-setting of DQS Precalculation
3672 18:06:48.543062 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3673 18:06:48.552961 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3674 18:06:48.559607 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3675 18:06:48.559696
3676 18:06:48.559761
3677 18:06:48.563690 [Calibration Summary] 2400 Mbps
3678 18:06:48.563772 CH 0, Rank 0
3679 18:06:48.566453 SW Impedance : PASS
3680 18:06:48.566534 DUTY Scan : NO K
3681 18:06:48.569874 ZQ Calibration : PASS
3682 18:06:48.572766 Jitter Meter : NO K
3683 18:06:48.572847 CBT Training : PASS
3684 18:06:48.576483 Write leveling : PASS
3685 18:06:48.579533 RX DQS gating : PASS
3686 18:06:48.579615 RX DQ/DQS(RDDQC) : PASS
3687 18:06:48.583046 TX DQ/DQS : PASS
3688 18:06:48.586459 RX DATLAT : PASS
3689 18:06:48.586540 RX DQ/DQS(Engine): PASS
3690 18:06:48.589948 TX OE : NO K
3691 18:06:48.590030 All Pass.
3692 18:06:48.590094
3693 18:06:48.592875 CH 0, Rank 1
3694 18:06:48.592955 SW Impedance : PASS
3695 18:06:48.596323 DUTY Scan : NO K
3696 18:06:48.596403 ZQ Calibration : PASS
3697 18:06:48.599805 Jitter Meter : NO K
3698 18:06:48.603252 CBT Training : PASS
3699 18:06:48.603334 Write leveling : PASS
3700 18:06:48.606153 RX DQS gating : PASS
3701 18:06:48.609658 RX DQ/DQS(RDDQC) : PASS
3702 18:06:48.609739 TX DQ/DQS : PASS
3703 18:06:48.613190 RX DATLAT : PASS
3704 18:06:48.616669 RX DQ/DQS(Engine): PASS
3705 18:06:48.616750 TX OE : NO K
3706 18:06:48.619949 All Pass.
3707 18:06:48.620030
3708 18:06:48.620094 CH 1, Rank 0
3709 18:06:48.622985 SW Impedance : PASS
3710 18:06:48.623067 DUTY Scan : NO K
3711 18:06:48.626388 ZQ Calibration : PASS
3712 18:06:48.629455 Jitter Meter : NO K
3713 18:06:48.629535 CBT Training : PASS
3714 18:06:48.632968 Write leveling : PASS
3715 18:06:48.633084 RX DQS gating : PASS
3716 18:06:48.636570 RX DQ/DQS(RDDQC) : PASS
3717 18:06:48.639995 TX DQ/DQS : PASS
3718 18:06:48.640077 RX DATLAT : PASS
3719 18:06:48.642889 RX DQ/DQS(Engine): PASS
3720 18:06:48.646304 TX OE : NO K
3721 18:06:48.646386 All Pass.
3722 18:06:48.646450
3723 18:06:48.646510 CH 1, Rank 1
3724 18:06:48.649769 SW Impedance : PASS
3725 18:06:48.653278 DUTY Scan : NO K
3726 18:06:48.653365 ZQ Calibration : PASS
3727 18:06:48.656151 Jitter Meter : NO K
3728 18:06:48.659723 CBT Training : PASS
3729 18:06:48.659827 Write leveling : PASS
3730 18:06:48.662926 RX DQS gating : PASS
3731 18:06:48.666703 RX DQ/DQS(RDDQC) : PASS
3732 18:06:48.666803 TX DQ/DQS : PASS
3733 18:06:48.669758 RX DATLAT : PASS
3734 18:06:48.673095 RX DQ/DQS(Engine): PASS
3735 18:06:48.673199 TX OE : NO K
3736 18:06:48.673320 All Pass.
3737 18:06:48.676338
3738 18:06:48.676410 DramC Write-DBI off
3739 18:06:48.679493 PER_BANK_REFRESH: Hybrid Mode
3740 18:06:48.679598 TX_TRACKING: ON
3741 18:06:48.690094 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3742 18:06:48.693175 [FAST_K] Save calibration result to emmc
3743 18:06:48.696680 dramc_set_vcore_voltage set vcore to 650000
3744 18:06:48.700243 Read voltage for 600, 5
3745 18:06:48.700321 Vio18 = 0
3746 18:06:48.703234 Vcore = 650000
3747 18:06:48.703322 Vdram = 0
3748 18:06:48.703382 Vddq = 0
3749 18:06:48.703439 Vmddr = 0
3750 18:06:48.709814 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3751 18:06:48.713168 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3752 18:06:48.716170 MEM_TYPE=3, freq_sel=19
3753 18:06:48.719648 sv_algorithm_assistance_LP4_1600
3754 18:06:48.723254 ============ PULL DRAM RESETB DOWN ============
3755 18:06:48.729831 ========== PULL DRAM RESETB DOWN end =========
3756 18:06:48.732879 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3757 18:06:48.736445 ===================================
3758 18:06:48.740288 LPDDR4 DRAM CONFIGURATION
3759 18:06:48.743039 ===================================
3760 18:06:48.743170 EX_ROW_EN[0] = 0x0
3761 18:06:48.746683 EX_ROW_EN[1] = 0x0
3762 18:06:48.746828 LP4Y_EN = 0x0
3763 18:06:48.749507 WORK_FSP = 0x0
3764 18:06:48.749576 WL = 0x2
3765 18:06:48.752911 RL = 0x2
3766 18:06:48.753051 BL = 0x2
3767 18:06:48.756136 RPST = 0x0
3768 18:06:48.756219 RD_PRE = 0x0
3769 18:06:48.759778 WR_PRE = 0x1
3770 18:06:48.759860 WR_PST = 0x0
3771 18:06:48.762829 DBI_WR = 0x0
3772 18:06:48.762910 DBI_RD = 0x0
3773 18:06:48.766262 OTF = 0x1
3774 18:06:48.769860 ===================================
3775 18:06:48.772876 ===================================
3776 18:06:48.772957 ANA top config
3777 18:06:48.776430 ===================================
3778 18:06:48.779949 DLL_ASYNC_EN = 0
3779 18:06:48.783161 ALL_SLAVE_EN = 1
3780 18:06:48.786180 NEW_RANK_MODE = 1
3781 18:06:48.786289 DLL_IDLE_MODE = 1
3782 18:06:48.789567 LP45_APHY_COMB_EN = 1
3783 18:06:48.793305 TX_ODT_DIS = 1
3784 18:06:48.796347 NEW_8X_MODE = 1
3785 18:06:48.799950 ===================================
3786 18:06:48.803249 ===================================
3787 18:06:48.806952 data_rate = 1200
3788 18:06:48.807055 CKR = 1
3789 18:06:48.809890 DQ_P2S_RATIO = 8
3790 18:06:48.813208 ===================================
3791 18:06:48.816467 CA_P2S_RATIO = 8
3792 18:06:48.819973 DQ_CA_OPEN = 0
3793 18:06:48.822842 DQ_SEMI_OPEN = 0
3794 18:06:48.826364 CA_SEMI_OPEN = 0
3795 18:06:48.826433 CA_FULL_RATE = 0
3796 18:06:48.829834 DQ_CKDIV4_EN = 1
3797 18:06:48.832773 CA_CKDIV4_EN = 1
3798 18:06:48.836574 CA_PREDIV_EN = 0
3799 18:06:48.839823 PH8_DLY = 0
3800 18:06:48.843054 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3801 18:06:48.843124 DQ_AAMCK_DIV = 4
3802 18:06:48.846912 CA_AAMCK_DIV = 4
3803 18:06:48.849798 CA_ADMCK_DIV = 4
3804 18:06:48.853404 DQ_TRACK_CA_EN = 0
3805 18:06:48.856323 CA_PICK = 600
3806 18:06:48.859835 CA_MCKIO = 600
3807 18:06:48.859940 MCKIO_SEMI = 0
3808 18:06:48.863275 PLL_FREQ = 2288
3809 18:06:48.866280 DQ_UI_PI_RATIO = 32
3810 18:06:48.869694 CA_UI_PI_RATIO = 0
3811 18:06:48.872633 ===================================
3812 18:06:48.876236 ===================================
3813 18:06:48.879473 memory_type:LPDDR4
3814 18:06:48.879574 GP_NUM : 10
3815 18:06:48.883057 SRAM_EN : 1
3816 18:06:48.886561 MD32_EN : 0
3817 18:06:48.889377 ===================================
3818 18:06:48.889478 [ANA_INIT] >>>>>>>>>>>>>>
3819 18:06:48.892923 <<<<<< [CONFIGURE PHASE]: ANA_TX
3820 18:06:48.896396 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3821 18:06:48.899417 ===================================
3822 18:06:48.902981 data_rate = 1200,PCW = 0X5800
3823 18:06:48.906310 ===================================
3824 18:06:48.909276 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3825 18:06:48.916749 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3826 18:06:48.919589 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3827 18:06:48.926145 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3828 18:06:48.929432 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3829 18:06:48.932694 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3830 18:06:48.932769 [ANA_INIT] flow start
3831 18:06:48.936213 [ANA_INIT] PLL >>>>>>>>
3832 18:06:48.939712 [ANA_INIT] PLL <<<<<<<<
3833 18:06:48.942532 [ANA_INIT] MIDPI >>>>>>>>
3834 18:06:48.942606 [ANA_INIT] MIDPI <<<<<<<<
3835 18:06:48.945806 [ANA_INIT] DLL >>>>>>>>
3836 18:06:48.945879 [ANA_INIT] flow end
3837 18:06:48.952736 ============ LP4 DIFF to SE enter ============
3838 18:06:48.956348 ============ LP4 DIFF to SE exit ============
3839 18:06:48.959163 [ANA_INIT] <<<<<<<<<<<<<
3840 18:06:48.962658 [Flow] Enable top DCM control >>>>>
3841 18:06:48.966411 [Flow] Enable top DCM control <<<<<
3842 18:06:48.966493 Enable DLL master slave shuffle
3843 18:06:48.972746 ==============================================================
3844 18:06:48.976141 Gating Mode config
3845 18:06:48.979127 ==============================================================
3846 18:06:48.982652 Config description:
3847 18:06:48.992471 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3848 18:06:48.999409 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3849 18:06:49.002920 SELPH_MODE 0: By rank 1: By Phase
3850 18:06:49.009767 ==============================================================
3851 18:06:49.012840 GAT_TRACK_EN = 1
3852 18:06:49.016242 RX_GATING_MODE = 2
3853 18:06:49.019565 RX_GATING_TRACK_MODE = 2
3854 18:06:49.019646 SELPH_MODE = 1
3855 18:06:49.023122 PICG_EARLY_EN = 1
3856 18:06:49.026441 VALID_LAT_VALUE = 1
3857 18:06:49.032597 ==============================================================
3858 18:06:49.036083 Enter into Gating configuration >>>>
3859 18:06:49.039475 Exit from Gating configuration <<<<
3860 18:06:49.042643 Enter into DVFS_PRE_config >>>>>
3861 18:06:49.053084 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3862 18:06:49.056144 Exit from DVFS_PRE_config <<<<<
3863 18:06:49.059744 Enter into PICG configuration >>>>
3864 18:06:49.063182 Exit from PICG configuration <<<<
3865 18:06:49.066587 [RX_INPUT] configuration >>>>>
3866 18:06:49.069399 [RX_INPUT] configuration <<<<<
3867 18:06:49.072821 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3868 18:06:49.079328 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3869 18:06:49.086266 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3870 18:06:49.092593 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3871 18:06:49.096104 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3872 18:06:49.103038 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3873 18:06:49.106018 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3874 18:06:49.112863 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3875 18:06:49.115953 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3876 18:06:49.119388 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3877 18:06:49.122886 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3878 18:06:49.129223 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3879 18:06:49.132619 ===================================
3880 18:06:49.136317 LPDDR4 DRAM CONFIGURATION
3881 18:06:49.136414 ===================================
3882 18:06:49.139452 EX_ROW_EN[0] = 0x0
3883 18:06:49.142683 EX_ROW_EN[1] = 0x0
3884 18:06:49.142825 LP4Y_EN = 0x0
3885 18:06:49.145817 WORK_FSP = 0x0
3886 18:06:49.145981 WL = 0x2
3887 18:06:49.149472 RL = 0x2
3888 18:06:49.149594 BL = 0x2
3889 18:06:49.152941 RPST = 0x0
3890 18:06:49.153078 RD_PRE = 0x0
3891 18:06:49.155956 WR_PRE = 0x1
3892 18:06:49.156139 WR_PST = 0x0
3893 18:06:49.159267 DBI_WR = 0x0
3894 18:06:49.159400 DBI_RD = 0x0
3895 18:06:49.162543 OTF = 0x1
3896 18:06:49.166110 ===================================
3897 18:06:49.169256 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3898 18:06:49.172949 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3899 18:06:49.179435 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3900 18:06:49.182877 ===================================
3901 18:06:49.183006 LPDDR4 DRAM CONFIGURATION
3902 18:06:49.185794 ===================================
3903 18:06:49.189239 EX_ROW_EN[0] = 0x10
3904 18:06:49.192668 EX_ROW_EN[1] = 0x0
3905 18:06:49.192762 LP4Y_EN = 0x0
3906 18:06:49.196133 WORK_FSP = 0x0
3907 18:06:49.196226 WL = 0x2
3908 18:06:49.199489 RL = 0x2
3909 18:06:49.199592 BL = 0x2
3910 18:06:49.202483 RPST = 0x0
3911 18:06:49.202603 RD_PRE = 0x0
3912 18:06:49.205975 WR_PRE = 0x1
3913 18:06:49.206097 WR_PST = 0x0
3914 18:06:49.209547 DBI_WR = 0x0
3915 18:06:49.209676 DBI_RD = 0x0
3916 18:06:49.213116 OTF = 0x1
3917 18:06:49.216086 ===================================
3918 18:06:49.222902 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3919 18:06:49.225819 nWR fixed to 30
3920 18:06:49.225941 [ModeRegInit_LP4] CH0 RK0
3921 18:06:49.229286 [ModeRegInit_LP4] CH0 RK1
3922 18:06:49.232942 [ModeRegInit_LP4] CH1 RK0
3923 18:06:49.233074 [ModeRegInit_LP4] CH1 RK1
3924 18:06:49.235686 match AC timing 17
3925 18:06:49.239428 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3926 18:06:49.245820 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3927 18:06:49.249523 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3928 18:06:49.252833 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3929 18:06:49.259259 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3930 18:06:49.259356 ==
3931 18:06:49.263080 Dram Type= 6, Freq= 0, CH_0, rank 0
3932 18:06:49.265805 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3933 18:06:49.265922 ==
3934 18:06:49.272873 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3935 18:06:49.276027 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3936 18:06:49.280408 [CA 0] Center 36 (6~66) winsize 61
3937 18:06:49.283869 [CA 1] Center 36 (6~66) winsize 61
3938 18:06:49.287257 [CA 2] Center 34 (4~65) winsize 62
3939 18:06:49.290786 [CA 3] Center 34 (4~65) winsize 62
3940 18:06:49.293657 [CA 4] Center 34 (4~64) winsize 61
3941 18:06:49.297088 [CA 5] Center 33 (3~64) winsize 62
3942 18:06:49.297172
3943 18:06:49.300643 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3944 18:06:49.300730
3945 18:06:49.304196 [CATrainingPosCal] consider 1 rank data
3946 18:06:49.307072 u2DelayCellTimex100 = 270/100 ps
3947 18:06:49.310536 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3948 18:06:49.314080 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3949 18:06:49.317614 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3950 18:06:49.323924 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3951 18:06:49.327477 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
3952 18:06:49.330360 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3953 18:06:49.330443
3954 18:06:49.333930 CA PerBit enable=1, Macro0, CA PI delay=33
3955 18:06:49.334013
3956 18:06:49.337328 [CBTSetCACLKResult] CA Dly = 33
3957 18:06:49.337411 CS Dly: 4 (0~35)
3958 18:06:49.337476 ==
3959 18:06:49.340729 Dram Type= 6, Freq= 0, CH_0, rank 1
3960 18:06:49.347027 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3961 18:06:49.347122 ==
3962 18:06:49.350670 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3963 18:06:49.357280 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3964 18:06:49.360652 [CA 0] Center 36 (6~67) winsize 62
3965 18:06:49.363739 [CA 1] Center 36 (6~66) winsize 61
3966 18:06:49.367137 [CA 2] Center 34 (4~65) winsize 62
3967 18:06:49.370487 [CA 3] Center 34 (4~65) winsize 62
3968 18:06:49.373754 [CA 4] Center 33 (3~64) winsize 62
3969 18:06:49.377191 [CA 5] Center 33 (3~64) winsize 62
3970 18:06:49.377273
3971 18:06:49.380605 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3972 18:06:49.380718
3973 18:06:49.383636 [CATrainingPosCal] consider 2 rank data
3974 18:06:49.387336 u2DelayCellTimex100 = 270/100 ps
3975 18:06:49.390288 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3976 18:06:49.393822 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3977 18:06:49.400309 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3978 18:06:49.403633 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3979 18:06:49.407190 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
3980 18:06:49.410145 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3981 18:06:49.410224
3982 18:06:49.413643 CA PerBit enable=1, Macro0, CA PI delay=33
3983 18:06:49.413718
3984 18:06:49.417138 [CBTSetCACLKResult] CA Dly = 33
3985 18:06:49.417217 CS Dly: 4 (0~36)
3986 18:06:49.417279
3987 18:06:49.420120 ----->DramcWriteLeveling(PI) begin...
3988 18:06:49.423724 ==
3989 18:06:49.427124 Dram Type= 6, Freq= 0, CH_0, rank 0
3990 18:06:49.430762 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3991 18:06:49.430842 ==
3992 18:06:49.433547 Write leveling (Byte 0): 32 => 32
3993 18:06:49.437135 Write leveling (Byte 1): 29 => 29
3994 18:06:49.440650 DramcWriteLeveling(PI) end<-----
3995 18:06:49.440730
3996 18:06:49.440793 ==
3997 18:06:49.443532 Dram Type= 6, Freq= 0, CH_0, rank 0
3998 18:06:49.447086 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3999 18:06:49.447164 ==
4000 18:06:49.450526 [Gating] SW mode calibration
4001 18:06:49.456940 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4002 18:06:49.460600 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4003 18:06:49.467179 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4004 18:06:49.470463 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4005 18:06:49.473971 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4006 18:06:49.480524 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4007 18:06:49.483841 0 9 16 | B1->B0 | 3131 2d2d | 0 0 | (0 0) (1 0)
4008 18:06:49.487349 0 9 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4009 18:06:49.493944 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4010 18:06:49.496885 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4011 18:06:49.500242 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4012 18:06:49.506812 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4013 18:06:49.510119 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4014 18:06:49.513444 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4015 18:06:49.520204 0 10 16 | B1->B0 | 3333 4040 | 0 1 | (0 0) (0 0)
4016 18:06:49.523784 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4017 18:06:49.526700 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4018 18:06:49.533760 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4019 18:06:49.536807 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4020 18:06:49.540203 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4021 18:06:49.546713 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4022 18:06:49.550200 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4023 18:06:49.553772 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4024 18:06:49.560211 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4025 18:06:49.563803 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4026 18:06:49.566870 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4027 18:06:49.570657 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4028 18:06:49.577031 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4029 18:06:49.580075 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4030 18:06:49.583731 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4031 18:06:49.590585 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4032 18:06:49.593952 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4033 18:06:49.597759 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4034 18:06:49.603888 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4035 18:06:49.606880 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4036 18:06:49.610234 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4037 18:06:49.616803 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4038 18:06:49.620225 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4039 18:06:49.623742 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4040 18:06:49.626791 Total UI for P1: 0, mck2ui 16
4041 18:06:49.630242 best dqsien dly found for B0: ( 0, 13, 14)
4042 18:06:49.636626 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4043 18:06:49.640029 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4044 18:06:49.643595 Total UI for P1: 0, mck2ui 16
4045 18:06:49.647135 best dqsien dly found for B1: ( 0, 13, 18)
4046 18:06:49.650516 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4047 18:06:49.653992 best DQS1 dly(MCK, UI, PI) = (0, 13, 18)
4048 18:06:49.654095
4049 18:06:49.656900 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4050 18:06:49.659880 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 18)
4051 18:06:49.663369 [Gating] SW calibration Done
4052 18:06:49.663444 ==
4053 18:06:49.666768 Dram Type= 6, Freq= 0, CH_0, rank 0
4054 18:06:49.670104 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4055 18:06:49.673389 ==
4056 18:06:49.673470 RX Vref Scan: 0
4057 18:06:49.673534
4058 18:06:49.676596 RX Vref 0 -> 0, step: 1
4059 18:06:49.676696
4060 18:06:49.679926 RX Delay -230 -> 252, step: 16
4061 18:06:49.683484 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4062 18:06:49.686931 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4063 18:06:49.689905 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4064 18:06:49.696548 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4065 18:06:49.700044 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4066 18:06:49.703526 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4067 18:06:49.706461 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4068 18:06:49.709824 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4069 18:06:49.717308 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4070 18:06:49.720077 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4071 18:06:49.723154 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4072 18:06:49.726712 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4073 18:06:49.729949 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4074 18:06:49.736583 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4075 18:06:49.740118 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4076 18:06:49.743442 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4077 18:06:49.743523 ==
4078 18:06:49.746972 Dram Type= 6, Freq= 0, CH_0, rank 0
4079 18:06:49.753416 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4080 18:06:49.753496 ==
4081 18:06:49.753564 DQS Delay:
4082 18:06:49.753624 DQS0 = 0, DQS1 = 0
4083 18:06:49.756389 DQM Delay:
4084 18:06:49.756489 DQM0 = 40, DQM1 = 31
4085 18:06:49.759792 DQ Delay:
4086 18:06:49.763370 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =33
4087 18:06:49.763444 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4088 18:06:49.766801 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4089 18:06:49.769750 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =41
4090 18:06:49.773332
4091 18:06:49.773407
4092 18:06:49.773468 ==
4093 18:06:49.776794 Dram Type= 6, Freq= 0, CH_0, rank 0
4094 18:06:49.779678 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4095 18:06:49.779755 ==
4096 18:06:49.779816
4097 18:06:49.779873
4098 18:06:49.783400 TX Vref Scan disable
4099 18:06:49.783496 == TX Byte 0 ==
4100 18:06:49.790176 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4101 18:06:49.793488 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4102 18:06:49.793560 == TX Byte 1 ==
4103 18:06:49.800091 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4104 18:06:49.803169 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4105 18:06:49.803269 ==
4106 18:06:49.806538 Dram Type= 6, Freq= 0, CH_0, rank 0
4107 18:06:49.810088 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4108 18:06:49.810158 ==
4109 18:06:49.810218
4110 18:06:49.810274
4111 18:06:49.813567 TX Vref Scan disable
4112 18:06:49.816514 == TX Byte 0 ==
4113 18:06:49.819916 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4114 18:06:49.823286 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4115 18:06:49.826817 == TX Byte 1 ==
4116 18:06:49.830255 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4117 18:06:49.833560 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4118 18:06:49.833678
4119 18:06:49.836826 [DATLAT]
4120 18:06:49.836899 Freq=600, CH0 RK0
4121 18:06:49.836958
4122 18:06:49.839950 DATLAT Default: 0x9
4123 18:06:49.840044 0, 0xFFFF, sum = 0
4124 18:06:49.843729 1, 0xFFFF, sum = 0
4125 18:06:49.843829 2, 0xFFFF, sum = 0
4126 18:06:49.846560 3, 0xFFFF, sum = 0
4127 18:06:49.846632 4, 0xFFFF, sum = 0
4128 18:06:49.850389 5, 0xFFFF, sum = 0
4129 18:06:49.850464 6, 0xFFFF, sum = 0
4130 18:06:49.853494 7, 0xFFFF, sum = 0
4131 18:06:49.853593 8, 0x0, sum = 1
4132 18:06:49.856558 9, 0x0, sum = 2
4133 18:06:49.856635 10, 0x0, sum = 3
4134 18:06:49.860085 11, 0x0, sum = 4
4135 18:06:49.860161 best_step = 9
4136 18:06:49.860224
4137 18:06:49.860280 ==
4138 18:06:49.863555 Dram Type= 6, Freq= 0, CH_0, rank 0
4139 18:06:49.866491 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4140 18:06:49.869946 ==
4141 18:06:49.870014 RX Vref Scan: 1
4142 18:06:49.870104
4143 18:06:49.873362 RX Vref 0 -> 0, step: 1
4144 18:06:49.873431
4145 18:06:49.876913 RX Delay -195 -> 252, step: 8
4146 18:06:49.877016
4147 18:06:49.879782 Set Vref, RX VrefLevel [Byte0]: 51
4148 18:06:49.883163 [Byte1]: 51
4149 18:06:49.883236
4150 18:06:49.886580 Final RX Vref Byte 0 = 51 to rank0
4151 18:06:49.889878 Final RX Vref Byte 1 = 51 to rank0
4152 18:06:49.893442 Final RX Vref Byte 0 = 51 to rank1
4153 18:06:49.896892 Final RX Vref Byte 1 = 51 to rank1==
4154 18:06:49.900303 Dram Type= 6, Freq= 0, CH_0, rank 0
4155 18:06:49.903146 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4156 18:06:49.903227 ==
4157 18:06:49.903290 DQS Delay:
4158 18:06:49.907106 DQS0 = 0, DQS1 = 0
4159 18:06:49.907234 DQM Delay:
4160 18:06:49.910159 DQM0 = 42, DQM1 = 33
4161 18:06:49.910225 DQ Delay:
4162 18:06:49.913318 DQ0 =44, DQ1 =44, DQ2 =36, DQ3 =40
4163 18:06:49.916883 DQ4 =44, DQ5 =32, DQ6 =52, DQ7 =48
4164 18:06:49.920251 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =28
4165 18:06:49.923175 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =44
4166 18:06:49.923248
4167 18:06:49.923312
4168 18:06:49.933478 [DQSOSCAuto] RK0, (LSB)MR18= 0x3c1b, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 398 ps
4169 18:06:49.933575 CH0 RK0: MR19=808, MR18=3C1B
4170 18:06:49.939822 CH0_RK0: MR19=0x808, MR18=0x3C1B, DQSOSC=398, MR23=63, INC=165, DEC=110
4171 18:06:49.939904
4172 18:06:49.943178 ----->DramcWriteLeveling(PI) begin...
4173 18:06:49.943251 ==
4174 18:06:49.946524 Dram Type= 6, Freq= 0, CH_0, rank 1
4175 18:06:49.953540 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4176 18:06:49.953622 ==
4177 18:06:49.956873 Write leveling (Byte 0): 33 => 33
4178 18:06:49.960204 Write leveling (Byte 1): 29 => 29
4179 18:06:49.960278 DramcWriteLeveling(PI) end<-----
4180 18:06:49.960338
4181 18:06:49.963339 ==
4182 18:06:49.963414 Dram Type= 6, Freq= 0, CH_0, rank 1
4183 18:06:49.969807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4184 18:06:49.969886 ==
4185 18:06:49.973329 [Gating] SW mode calibration
4186 18:06:49.980145 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4187 18:06:49.982982 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4188 18:06:49.990114 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4189 18:06:49.993497 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4190 18:06:49.996808 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4191 18:06:50.003383 0 9 12 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 1)
4192 18:06:50.006696 0 9 16 | B1->B0 | 2f2f 2424 | 1 0 | (1 0) (0 0)
4193 18:06:50.010135 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4194 18:06:50.016302 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4195 18:06:50.019946 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4196 18:06:50.023321 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4197 18:06:50.026868 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4198 18:06:50.033215 0 10 8 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
4199 18:06:50.036744 0 10 12 | B1->B0 | 2323 3232 | 0 1 | (0 0) (0 0)
4200 18:06:50.040030 0 10 16 | B1->B0 | 3535 4646 | 1 0 | (0 0) (0 0)
4201 18:06:50.046425 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4202 18:06:50.049870 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4203 18:06:50.053241 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4204 18:06:50.060175 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4205 18:06:50.063660 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4206 18:06:50.066623 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4207 18:06:50.073628 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4208 18:06:50.076726 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4209 18:06:50.080070 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4210 18:06:50.086912 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4211 18:06:50.090012 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4212 18:06:50.093162 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4213 18:06:50.099742 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4214 18:06:50.103247 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4215 18:06:50.106960 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4216 18:06:50.113441 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4217 18:06:50.116799 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4218 18:06:50.120244 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4219 18:06:50.126393 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4220 18:06:50.130089 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4221 18:06:50.133346 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4222 18:06:50.136358 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4223 18:06:50.143253 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4224 18:06:50.146574 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4225 18:06:50.149923 Total UI for P1: 0, mck2ui 16
4226 18:06:50.152966 best dqsien dly found for B0: ( 0, 13, 12)
4227 18:06:50.156465 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4228 18:06:50.159856 Total UI for P1: 0, mck2ui 16
4229 18:06:50.163375 best dqsien dly found for B1: ( 0, 13, 16)
4230 18:06:50.166876 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4231 18:06:50.169786 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4232 18:06:50.173261
4233 18:06:50.176160 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4234 18:06:50.179585 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4235 18:06:50.183146 [Gating] SW calibration Done
4236 18:06:50.183215 ==
4237 18:06:50.186485 Dram Type= 6, Freq= 0, CH_0, rank 1
4238 18:06:50.190190 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4239 18:06:50.190275 ==
4240 18:06:50.190342 RX Vref Scan: 0
4241 18:06:50.190398
4242 18:06:50.192840 RX Vref 0 -> 0, step: 1
4243 18:06:50.192905
4244 18:06:50.196214 RX Delay -230 -> 252, step: 16
4245 18:06:50.199531 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4246 18:06:50.203084 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4247 18:06:50.209487 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4248 18:06:50.213002 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4249 18:06:50.216560 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4250 18:06:50.219742 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4251 18:06:50.226661 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4252 18:06:50.229653 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4253 18:06:50.232874 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4254 18:06:50.236558 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4255 18:06:50.239827 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4256 18:06:50.246772 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4257 18:06:50.249973 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4258 18:06:50.253197 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4259 18:06:50.256627 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4260 18:06:50.263106 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4261 18:06:50.263188 ==
4262 18:06:50.266358 Dram Type= 6, Freq= 0, CH_0, rank 1
4263 18:06:50.269913 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4264 18:06:50.270017 ==
4265 18:06:50.270107 DQS Delay:
4266 18:06:50.273091 DQS0 = 0, DQS1 = 0
4267 18:06:50.273161 DQM Delay:
4268 18:06:50.276129 DQM0 = 39, DQM1 = 31
4269 18:06:50.276198 DQ Delay:
4270 18:06:50.279695 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =33
4271 18:06:50.283318 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4272 18:06:50.286202 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4273 18:06:50.289689 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =41
4274 18:06:50.289761
4275 18:06:50.289820
4276 18:06:50.289875 ==
4277 18:06:50.293158 Dram Type= 6, Freq= 0, CH_0, rank 1
4278 18:06:50.296423 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4279 18:06:50.296525 ==
4280 18:06:50.299750
4281 18:06:50.299820
4282 18:06:50.299878 TX Vref Scan disable
4283 18:06:50.303171 == TX Byte 0 ==
4284 18:06:50.306077 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4285 18:06:50.309450 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4286 18:06:50.312776 == TX Byte 1 ==
4287 18:06:50.316464 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4288 18:06:50.319501 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4289 18:06:50.319573 ==
4290 18:06:50.322989 Dram Type= 6, Freq= 0, CH_0, rank 1
4291 18:06:50.329932 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4292 18:06:50.330020 ==
4293 18:06:50.330100
4294 18:06:50.330162
4295 18:06:50.330217 TX Vref Scan disable
4296 18:06:50.334210 == TX Byte 0 ==
4297 18:06:50.338017 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4298 18:06:50.340819 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4299 18:06:50.344451 == TX Byte 1 ==
4300 18:06:50.348276 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4301 18:06:50.351028 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4302 18:06:50.354587
4303 18:06:50.354657 [DATLAT]
4304 18:06:50.354720 Freq=600, CH0 RK1
4305 18:06:50.354779
4306 18:06:50.357894 DATLAT Default: 0x9
4307 18:06:50.357971 0, 0xFFFF, sum = 0
4308 18:06:50.361358 1, 0xFFFF, sum = 0
4309 18:06:50.361431 2, 0xFFFF, sum = 0
4310 18:06:50.364264 3, 0xFFFF, sum = 0
4311 18:06:50.364340 4, 0xFFFF, sum = 0
4312 18:06:50.367705 5, 0xFFFF, sum = 0
4313 18:06:50.367772 6, 0xFFFF, sum = 0
4314 18:06:50.371267 7, 0xFFFF, sum = 0
4315 18:06:50.371340 8, 0x0, sum = 1
4316 18:06:50.374545 9, 0x0, sum = 2
4317 18:06:50.374648 10, 0x0, sum = 3
4318 18:06:50.377893 11, 0x0, sum = 4
4319 18:06:50.377968 best_step = 9
4320 18:06:50.378028
4321 18:06:50.378088 ==
4322 18:06:50.381288 Dram Type= 6, Freq= 0, CH_0, rank 1
4323 18:06:50.387775 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4324 18:06:50.387850 ==
4325 18:06:50.387912 RX Vref Scan: 0
4326 18:06:50.387967
4327 18:06:50.391178 RX Vref 0 -> 0, step: 1
4328 18:06:50.391243
4329 18:06:50.394111 RX Delay -195 -> 252, step: 8
4330 18:06:50.397749 iDelay=205, Bit 0, Center 44 (-107 ~ 196) 304
4331 18:06:50.404196 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4332 18:06:50.407743 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4333 18:06:50.410656 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4334 18:06:50.413970 iDelay=205, Bit 4, Center 40 (-107 ~ 188) 296
4335 18:06:50.417516 iDelay=205, Bit 5, Center 28 (-123 ~ 180) 304
4336 18:06:50.424550 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4337 18:06:50.427249 iDelay=205, Bit 7, Center 44 (-107 ~ 196) 304
4338 18:06:50.431035 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4339 18:06:50.434088 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4340 18:06:50.441041 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4341 18:06:50.444313 iDelay=205, Bit 11, Center 24 (-123 ~ 172) 296
4342 18:06:50.447392 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4343 18:06:50.450662 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4344 18:06:50.457202 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4345 18:06:50.460298 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4346 18:06:50.460407 ==
4347 18:06:50.463708 Dram Type= 6, Freq= 0, CH_0, rank 1
4348 18:06:50.467198 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4349 18:06:50.467272 ==
4350 18:06:50.470514 DQS Delay:
4351 18:06:50.470587 DQS0 = 0, DQS1 = 0
4352 18:06:50.470652 DQM Delay:
4353 18:06:50.473884 DQM0 = 40, DQM1 = 33
4354 18:06:50.473957 DQ Delay:
4355 18:06:50.477157 DQ0 =44, DQ1 =44, DQ2 =36, DQ3 =40
4356 18:06:50.480741 DQ4 =40, DQ5 =28, DQ6 =48, DQ7 =44
4357 18:06:50.484069 DQ8 =24, DQ9 =24, DQ10 =32, DQ11 =24
4358 18:06:50.486909 DQ12 =36, DQ13 =40, DQ14 =44, DQ15 =40
4359 18:06:50.486981
4360 18:06:50.487041
4361 18:06:50.496871 [DQSOSCAuto] RK1, (LSB)MR18= 0x482c, (MSB)MR19= 0x808, tDQSOscB0 = 401 ps tDQSOscB1 = 396 ps
4362 18:06:50.496983 CH0 RK1: MR19=808, MR18=482C
4363 18:06:50.503805 CH0_RK1: MR19=0x808, MR18=0x482C, DQSOSC=396, MR23=63, INC=167, DEC=111
4364 18:06:50.507293 [RxdqsGatingPostProcess] freq 600
4365 18:06:50.513666 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4366 18:06:50.517226 Pre-setting of DQS Precalculation
4367 18:06:50.520108 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4368 18:06:50.520205 ==
4369 18:06:50.523459 Dram Type= 6, Freq= 0, CH_1, rank 0
4370 18:06:50.530450 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4371 18:06:50.530528 ==
4372 18:06:50.533788 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4373 18:06:50.540474 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4374 18:06:50.543845 [CA 0] Center 35 (5~66) winsize 62
4375 18:06:50.546777 [CA 1] Center 35 (5~66) winsize 62
4376 18:06:50.550250 [CA 2] Center 34 (3~65) winsize 63
4377 18:06:50.553734 [CA 3] Center 33 (3~64) winsize 62
4378 18:06:50.556949 [CA 4] Center 34 (3~65) winsize 63
4379 18:06:50.560251 [CA 5] Center 33 (3~64) winsize 62
4380 18:06:50.560346
4381 18:06:50.563625 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4382 18:06:50.563698
4383 18:06:50.567151 [CATrainingPosCal] consider 1 rank data
4384 18:06:50.569960 u2DelayCellTimex100 = 270/100 ps
4385 18:06:50.573452 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4386 18:06:50.576933 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4387 18:06:50.580041 CA2 delay=34 (3~65),Diff = 1 PI (9 cell)
4388 18:06:50.586918 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4389 18:06:50.590191 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4390 18:06:50.593451 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4391 18:06:50.593525
4392 18:06:50.596908 CA PerBit enable=1, Macro0, CA PI delay=33
4393 18:06:50.597048
4394 18:06:50.600452 [CBTSetCACLKResult] CA Dly = 33
4395 18:06:50.600527 CS Dly: 5 (0~36)
4396 18:06:50.600592 ==
4397 18:06:50.603466 Dram Type= 6, Freq= 0, CH_1, rank 1
4398 18:06:50.610341 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4399 18:06:50.610461 ==
4400 18:06:50.613787 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4401 18:06:50.620133 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4402 18:06:50.623561 [CA 0] Center 35 (5~66) winsize 62
4403 18:06:50.626591 [CA 1] Center 36 (6~66) winsize 61
4404 18:06:50.629959 [CA 2] Center 34 (4~65) winsize 62
4405 18:06:50.633379 [CA 3] Center 34 (3~65) winsize 63
4406 18:06:50.636798 [CA 4] Center 33 (3~64) winsize 62
4407 18:06:50.640190 [CA 5] Center 33 (3~64) winsize 62
4408 18:06:50.640272
4409 18:06:50.643334 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4410 18:06:50.643409
4411 18:06:50.646613 [CATrainingPosCal] consider 2 rank data
4412 18:06:50.650063 u2DelayCellTimex100 = 270/100 ps
4413 18:06:50.653595 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4414 18:06:50.656577 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4415 18:06:50.663292 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4416 18:06:50.666609 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4417 18:06:50.670115 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4418 18:06:50.673427 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4419 18:06:50.673505
4420 18:06:50.676538 CA PerBit enable=1, Macro0, CA PI delay=33
4421 18:06:50.676691
4422 18:06:50.679995 [CBTSetCACLKResult] CA Dly = 33
4423 18:06:50.680079 CS Dly: 4 (0~35)
4424 18:06:50.680143
4425 18:06:50.683458 ----->DramcWriteLeveling(PI) begin...
4426 18:06:50.686461 ==
4427 18:06:50.690058 Dram Type= 6, Freq= 0, CH_1, rank 0
4428 18:06:50.692920 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4429 18:06:50.693036 ==
4430 18:06:50.696479 Write leveling (Byte 0): 27 => 27
4431 18:06:50.699885 Write leveling (Byte 1): 28 => 28
4432 18:06:50.703086 DramcWriteLeveling(PI) end<-----
4433 18:06:50.703188
4434 18:06:50.703277 ==
4435 18:06:50.706618 Dram Type= 6, Freq= 0, CH_1, rank 0
4436 18:06:50.709735 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4437 18:06:50.709836 ==
4438 18:06:50.713120 [Gating] SW mode calibration
4439 18:06:50.719753 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4440 18:06:50.723237 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4441 18:06:50.729978 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4442 18:06:50.733472 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4443 18:06:50.736888 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4444 18:06:50.743225 0 9 12 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
4445 18:06:50.746562 0 9 16 | B1->B0 | 2c2c 2727 | 0 0 | (0 0) (0 0)
4446 18:06:50.749729 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4447 18:06:50.756359 0 9 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4448 18:06:50.759774 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4449 18:06:50.763209 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4450 18:06:50.769906 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4451 18:06:50.773285 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4452 18:06:50.776246 0 10 12 | B1->B0 | 2727 2b2b | 0 0 | (0 0) (0 0)
4453 18:06:50.783260 0 10 16 | B1->B0 | 3e3e 4545 | 0 0 | (0 0) (0 0)
4454 18:06:50.786803 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4455 18:06:50.790224 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4456 18:06:50.796304 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4457 18:06:50.799790 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4458 18:06:50.803290 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4459 18:06:50.809881 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4460 18:06:50.813174 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4461 18:06:50.816491 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4462 18:06:50.819995 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4463 18:06:50.826724 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4464 18:06:50.829737 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4465 18:06:50.833384 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4466 18:06:50.840182 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4467 18:06:50.843006 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4468 18:06:50.846336 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4469 18:06:50.853226 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4470 18:06:50.856498 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4471 18:06:50.860194 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4472 18:06:50.866466 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4473 18:06:50.869615 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4474 18:06:50.873397 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4475 18:06:50.879768 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4476 18:06:50.883374 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4477 18:06:50.886828 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4478 18:06:50.890323 Total UI for P1: 0, mck2ui 16
4479 18:06:50.893279 best dqsien dly found for B1: ( 0, 13, 14)
4480 18:06:50.896792 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4481 18:06:50.899968 Total UI for P1: 0, mck2ui 16
4482 18:06:50.903345 best dqsien dly found for B0: ( 0, 13, 16)
4483 18:06:50.906764 best DQS0 dly(MCK, UI, PI) = (0, 13, 16)
4484 18:06:50.913618 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4485 18:06:50.913692
4486 18:06:50.916472 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 16)
4487 18:06:50.919962 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4488 18:06:50.923308 [Gating] SW calibration Done
4489 18:06:50.923379 ==
4490 18:06:50.926481 Dram Type= 6, Freq= 0, CH_1, rank 0
4491 18:06:50.929737 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4492 18:06:50.929839 ==
4493 18:06:50.933447 RX Vref Scan: 0
4494 18:06:50.933523
4495 18:06:50.933584 RX Vref 0 -> 0, step: 1
4496 18:06:50.933642
4497 18:06:50.936785 RX Delay -230 -> 252, step: 16
4498 18:06:50.939734 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4499 18:06:50.947004 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4500 18:06:50.949932 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4501 18:06:50.953188 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4502 18:06:50.956768 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4503 18:06:50.963088 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4504 18:06:50.966592 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4505 18:06:50.969696 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4506 18:06:50.973196 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4507 18:06:50.976189 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4508 18:06:50.983057 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4509 18:06:50.985963 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4510 18:06:50.989360 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4511 18:06:50.992851 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4512 18:06:50.999762 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4513 18:06:51.003631 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4514 18:06:51.003733 ==
4515 18:06:51.006009 Dram Type= 6, Freq= 0, CH_1, rank 0
4516 18:06:51.009473 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4517 18:06:51.009546 ==
4518 18:06:51.012926 DQS Delay:
4519 18:06:51.013055 DQS0 = 0, DQS1 = 0
4520 18:06:51.013116 DQM Delay:
4521 18:06:51.016352 DQM0 = 45, DQM1 = 36
4522 18:06:51.016423 DQ Delay:
4523 18:06:51.019832 DQ0 =49, DQ1 =41, DQ2 =33, DQ3 =41
4524 18:06:51.023218 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4525 18:06:51.026152 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4526 18:06:51.029500 DQ12 =49, DQ13 =41, DQ14 =41, DQ15 =41
4527 18:06:51.029571
4528 18:06:51.029630
4529 18:06:51.029690 ==
4530 18:06:51.033277 Dram Type= 6, Freq= 0, CH_1, rank 0
4531 18:06:51.036379 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4532 18:06:51.040033 ==
4533 18:06:51.040104
4534 18:06:51.040164
4535 18:06:51.040221 TX Vref Scan disable
4536 18:06:51.042984 == TX Byte 0 ==
4537 18:06:51.046262 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4538 18:06:51.049815 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4539 18:06:51.053335 == TX Byte 1 ==
4540 18:06:51.056340 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4541 18:06:51.059958 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4542 18:06:51.063271 ==
4543 18:06:51.066204 Dram Type= 6, Freq= 0, CH_1, rank 0
4544 18:06:51.069901 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4545 18:06:51.070004 ==
4546 18:06:51.070098
4547 18:06:51.070186
4548 18:06:51.072812 TX Vref Scan disable
4549 18:06:51.072907 == TX Byte 0 ==
4550 18:06:51.080071 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4551 18:06:51.082896 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4552 18:06:51.082972 == TX Byte 1 ==
4553 18:06:51.089757 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4554 18:06:51.093170 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4555 18:06:51.093267
4556 18:06:51.093333 [DATLAT]
4557 18:06:51.096362 Freq=600, CH1 RK0
4558 18:06:51.096436
4559 18:06:51.096501 DATLAT Default: 0x9
4560 18:06:51.099829 0, 0xFFFF, sum = 0
4561 18:06:51.099901 1, 0xFFFF, sum = 0
4562 18:06:51.103376 2, 0xFFFF, sum = 0
4563 18:06:51.103448 3, 0xFFFF, sum = 0
4564 18:06:51.106280 4, 0xFFFF, sum = 0
4565 18:06:51.106360 5, 0xFFFF, sum = 0
4566 18:06:51.109717 6, 0xFFFF, sum = 0
4567 18:06:51.113033 7, 0xFFFF, sum = 0
4568 18:06:51.113107 8, 0x0, sum = 1
4569 18:06:51.113167 9, 0x0, sum = 2
4570 18:06:51.116405 10, 0x0, sum = 3
4571 18:06:51.116473 11, 0x0, sum = 4
4572 18:06:51.119900 best_step = 9
4573 18:06:51.119969
4574 18:06:51.120028 ==
4575 18:06:51.122800 Dram Type= 6, Freq= 0, CH_1, rank 0
4576 18:06:51.126280 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4577 18:06:51.126355 ==
4578 18:06:51.129731 RX Vref Scan: 1
4579 18:06:51.129800
4580 18:06:51.129857 RX Vref 0 -> 0, step: 1
4581 18:06:51.129917
4582 18:06:51.133191 RX Delay -179 -> 252, step: 8
4583 18:06:51.133258
4584 18:06:51.136132 Set Vref, RX VrefLevel [Byte0]: 58
4585 18:06:51.139444 [Byte1]: 52
4586 18:06:51.143329
4587 18:06:51.143401 Final RX Vref Byte 0 = 58 to rank0
4588 18:06:51.146767 Final RX Vref Byte 1 = 52 to rank0
4589 18:06:51.149964 Final RX Vref Byte 0 = 58 to rank1
4590 18:06:51.153476 Final RX Vref Byte 1 = 52 to rank1==
4591 18:06:51.157047 Dram Type= 6, Freq= 0, CH_1, rank 0
4592 18:06:51.160416 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4593 18:06:51.163314 ==
4594 18:06:51.163389 DQS Delay:
4595 18:06:51.163452 DQS0 = 0, DQS1 = 0
4596 18:06:51.166888 DQM Delay:
4597 18:06:51.166993 DQM0 = 40, DQM1 = 33
4598 18:06:51.170234 DQ Delay:
4599 18:06:51.173417 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =40
4600 18:06:51.173491 DQ4 =40, DQ5 =48, DQ6 =52, DQ7 =36
4601 18:06:51.176607 DQ8 =20, DQ9 =24, DQ10 =36, DQ11 =28
4602 18:06:51.180770 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4603 18:06:51.180844
4604 18:06:51.183480
4605 18:06:51.190302 [DQSOSCAuto] RK0, (LSB)MR18= 0x4209, (MSB)MR19= 0x808, tDQSOscB0 = 408 ps tDQSOscB1 = 397 ps
4606 18:06:51.193805 CH1 RK0: MR19=808, MR18=4209
4607 18:06:51.200215 CH1_RK0: MR19=0x808, MR18=0x4209, DQSOSC=397, MR23=63, INC=166, DEC=110
4608 18:06:51.200320
4609 18:06:51.203712 ----->DramcWriteLeveling(PI) begin...
4610 18:06:51.203817 ==
4611 18:06:51.207345 Dram Type= 6, Freq= 0, CH_1, rank 1
4612 18:06:51.210471 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4613 18:06:51.210547 ==
4614 18:06:51.213783 Write leveling (Byte 0): 29 => 29
4615 18:06:51.217201 Write leveling (Byte 1): 29 => 29
4616 18:06:51.220133 DramcWriteLeveling(PI) end<-----
4617 18:06:51.220207
4618 18:06:51.220269 ==
4619 18:06:51.223644 Dram Type= 6, Freq= 0, CH_1, rank 1
4620 18:06:51.227094 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4621 18:06:51.227166 ==
4622 18:06:51.230592 [Gating] SW mode calibration
4623 18:06:51.236873 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4624 18:06:51.243592 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4625 18:06:51.246959 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4626 18:06:51.250382 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4627 18:06:51.256921 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4628 18:06:51.260784 0 9 12 | B1->B0 | 3130 2a2a | 1 0 | (0 0) (1 0)
4629 18:06:51.263709 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4630 18:06:51.270541 0 9 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4631 18:06:51.273506 0 9 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4632 18:06:51.277181 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4633 18:06:51.283654 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4634 18:06:51.287217 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4635 18:06:51.289940 0 10 8 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
4636 18:06:51.297246 0 10 12 | B1->B0 | 3131 3b3b | 0 0 | (0 0) (0 0)
4637 18:06:51.300426 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4638 18:06:51.303858 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4639 18:06:51.307240 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4640 18:06:51.313285 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4641 18:06:51.316878 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4642 18:06:51.320260 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4643 18:06:51.326951 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4644 18:06:51.330002 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4645 18:06:51.333417 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4646 18:06:51.340450 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4647 18:06:51.343317 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4648 18:06:51.346704 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4649 18:06:51.353506 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4650 18:06:51.356355 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4651 18:06:51.359712 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4652 18:06:51.366461 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4653 18:06:51.369928 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4654 18:06:51.373424 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4655 18:06:51.380169 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4656 18:06:51.383078 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4657 18:06:51.386495 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4658 18:06:51.393192 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4659 18:06:51.396725 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4660 18:06:51.399642 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4661 18:06:51.403014 Total UI for P1: 0, mck2ui 16
4662 18:06:51.406402 best dqsien dly found for B0: ( 0, 13, 8)
4663 18:06:51.413261 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4664 18:06:51.413378 Total UI for P1: 0, mck2ui 16
4665 18:06:51.416601 best dqsien dly found for B1: ( 0, 13, 12)
4666 18:06:51.423443 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4667 18:06:51.426276 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4668 18:06:51.426352
4669 18:06:51.429914 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4670 18:06:51.433461 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4671 18:06:51.436685 [Gating] SW calibration Done
4672 18:06:51.436755 ==
4673 18:06:51.439978 Dram Type= 6, Freq= 0, CH_1, rank 1
4674 18:06:51.443530 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4675 18:06:51.443603 ==
4676 18:06:51.446258 RX Vref Scan: 0
4677 18:06:51.446344
4678 18:06:51.446436 RX Vref 0 -> 0, step: 1
4679 18:06:51.446523
4680 18:06:51.449610 RX Delay -230 -> 252, step: 16
4681 18:06:51.453471 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4682 18:06:51.459899 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4683 18:06:51.463398 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4684 18:06:51.466172 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4685 18:06:51.469903 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4686 18:06:51.472851 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4687 18:06:51.480102 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4688 18:06:51.483000 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4689 18:06:51.486420 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4690 18:06:51.489833 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4691 18:06:51.496534 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4692 18:06:51.500028 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4693 18:06:51.502932 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4694 18:06:51.506334 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4695 18:06:51.513427 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4696 18:06:51.516225 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4697 18:06:51.516295 ==
4698 18:06:51.519779 Dram Type= 6, Freq= 0, CH_1, rank 1
4699 18:06:51.522887 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4700 18:06:51.522956 ==
4701 18:06:51.523017 DQS Delay:
4702 18:06:51.526671 DQS0 = 0, DQS1 = 0
4703 18:06:51.526742 DQM Delay:
4704 18:06:51.529782 DQM0 = 41, DQM1 = 36
4705 18:06:51.529852 DQ Delay:
4706 18:06:51.532826 DQ0 =41, DQ1 =33, DQ2 =25, DQ3 =41
4707 18:06:51.536570 DQ4 =41, DQ5 =57, DQ6 =49, DQ7 =41
4708 18:06:51.539825 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4709 18:06:51.543307 DQ12 =41, DQ13 =49, DQ14 =41, DQ15 =41
4710 18:06:51.543378
4711 18:06:51.543437
4712 18:06:51.543502 ==
4713 18:06:51.546163 Dram Type= 6, Freq= 0, CH_1, rank 1
4714 18:06:51.550146 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4715 18:06:51.553031 ==
4716 18:06:51.553101
4717 18:06:51.553160
4718 18:06:51.553216 TX Vref Scan disable
4719 18:06:51.556364 == TX Byte 0 ==
4720 18:06:51.559840 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4721 18:06:51.562845 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4722 18:06:51.566303 == TX Byte 1 ==
4723 18:06:51.569792 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4724 18:06:51.573266 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4725 18:06:51.576663 ==
4726 18:06:51.576734 Dram Type= 6, Freq= 0, CH_1, rank 1
4727 18:06:51.583259 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4728 18:06:51.583336 ==
4729 18:06:51.583405
4730 18:06:51.583462
4731 18:06:51.586221 TX Vref Scan disable
4732 18:06:51.586290 == TX Byte 0 ==
4733 18:06:51.592980 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4734 18:06:51.596524 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4735 18:06:51.596598 == TX Byte 1 ==
4736 18:06:51.603415 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4737 18:06:51.606432 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4738 18:06:51.606503
4739 18:06:51.606564 [DATLAT]
4740 18:06:51.609813 Freq=600, CH1 RK1
4741 18:06:51.609879
4742 18:06:51.609937 DATLAT Default: 0x9
4743 18:06:51.612785 0, 0xFFFF, sum = 0
4744 18:06:51.612850 1, 0xFFFF, sum = 0
4745 18:06:51.616292 2, 0xFFFF, sum = 0
4746 18:06:51.616359 3, 0xFFFF, sum = 0
4747 18:06:51.619869 4, 0xFFFF, sum = 0
4748 18:06:51.619952 5, 0xFFFF, sum = 0
4749 18:06:51.623234 6, 0xFFFF, sum = 0
4750 18:06:51.623301 7, 0xFFFF, sum = 0
4751 18:06:51.626479 8, 0x0, sum = 1
4752 18:06:51.626547 9, 0x0, sum = 2
4753 18:06:51.630034 10, 0x0, sum = 3
4754 18:06:51.630105 11, 0x0, sum = 4
4755 18:06:51.633308 best_step = 9
4756 18:06:51.633371
4757 18:06:51.633427 ==
4758 18:06:51.636620 Dram Type= 6, Freq= 0, CH_1, rank 1
4759 18:06:51.639576 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4760 18:06:51.639645 ==
4761 18:06:51.643092 RX Vref Scan: 0
4762 18:06:51.643163
4763 18:06:51.643265 RX Vref 0 -> 0, step: 1
4764 18:06:51.643337
4765 18:06:51.646452 RX Delay -179 -> 252, step: 8
4766 18:06:51.653234 iDelay=205, Bit 0, Center 44 (-107 ~ 196) 304
4767 18:06:51.656372 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4768 18:06:51.659611 iDelay=205, Bit 2, Center 28 (-123 ~ 180) 304
4769 18:06:51.663111 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4770 18:06:51.669926 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312
4771 18:06:51.673324 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4772 18:06:51.676181 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4773 18:06:51.679628 iDelay=205, Bit 7, Center 36 (-115 ~ 188) 304
4774 18:06:51.683098 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4775 18:06:51.689880 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4776 18:06:51.693324 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4777 18:06:51.696236 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4778 18:06:51.699724 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4779 18:06:51.706457 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4780 18:06:51.709992 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4781 18:06:51.713307 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4782 18:06:51.713409 ==
4783 18:06:51.716274 Dram Type= 6, Freq= 0, CH_1, rank 1
4784 18:06:51.719820 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4785 18:06:51.723278 ==
4786 18:06:51.723383 DQS Delay:
4787 18:06:51.723473 DQS0 = 0, DQS1 = 0
4788 18:06:51.726751 DQM Delay:
4789 18:06:51.726827 DQM0 = 39, DQM1 = 33
4790 18:06:51.730005 DQ Delay:
4791 18:06:51.730111 DQ0 =44, DQ1 =32, DQ2 =28, DQ3 =36
4792 18:06:51.733241 DQ4 =40, DQ5 =48, DQ6 =48, DQ7 =36
4793 18:06:51.736667 DQ8 =20, DQ9 =24, DQ10 =36, DQ11 =24
4794 18:06:51.740003 DQ12 =44, DQ13 =40, DQ14 =40, DQ15 =40
4795 18:06:51.740102
4796 18:06:51.743107
4797 18:06:51.750174 [DQSOSCAuto] RK1, (LSB)MR18= 0x303f, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 400 ps
4798 18:06:51.753344 CH1 RK1: MR19=808, MR18=303F
4799 18:06:51.759957 CH1_RK1: MR19=0x808, MR18=0x303F, DQSOSC=397, MR23=63, INC=166, DEC=110
4800 18:06:51.760059 [RxdqsGatingPostProcess] freq 600
4801 18:06:51.766708 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4802 18:06:51.769905 Pre-setting of DQS Precalculation
4803 18:06:51.773512 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4804 18:06:51.783648 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4805 18:06:51.789853 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4806 18:06:51.789942
4807 18:06:51.790037
4808 18:06:51.793282 [Calibration Summary] 1200 Mbps
4809 18:06:51.793358 CH 0, Rank 0
4810 18:06:51.796875 SW Impedance : PASS
4811 18:06:51.796981 DUTY Scan : NO K
4812 18:06:51.800174 ZQ Calibration : PASS
4813 18:06:51.803552 Jitter Meter : NO K
4814 18:06:51.803633 CBT Training : PASS
4815 18:06:51.806951 Write leveling : PASS
4816 18:06:51.810334 RX DQS gating : PASS
4817 18:06:51.810413 RX DQ/DQS(RDDQC) : PASS
4818 18:06:51.813224 TX DQ/DQS : PASS
4819 18:06:51.813304 RX DATLAT : PASS
4820 18:06:51.816819 RX DQ/DQS(Engine): PASS
4821 18:06:51.820237 TX OE : NO K
4822 18:06:51.820315 All Pass.
4823 18:06:51.820396
4824 18:06:51.820495 CH 0, Rank 1
4825 18:06:51.823304 SW Impedance : PASS
4826 18:06:51.826723 DUTY Scan : NO K
4827 18:06:51.826814 ZQ Calibration : PASS
4828 18:06:51.830216 Jitter Meter : NO K
4829 18:06:51.833649 CBT Training : PASS
4830 18:06:51.833730 Write leveling : PASS
4831 18:06:51.836967 RX DQS gating : PASS
4832 18:06:51.840437 RX DQ/DQS(RDDQC) : PASS
4833 18:06:51.840512 TX DQ/DQS : PASS
4834 18:06:51.843815 RX DATLAT : PASS
4835 18:06:51.847074 RX DQ/DQS(Engine): PASS
4836 18:06:51.847166 TX OE : NO K
4837 18:06:51.847259 All Pass.
4838 18:06:51.850610
4839 18:06:51.850685 CH 1, Rank 0
4840 18:06:51.853669 SW Impedance : PASS
4841 18:06:51.853744 DUTY Scan : NO K
4842 18:06:51.856923 ZQ Calibration : PASS
4843 18:06:51.857042 Jitter Meter : NO K
4844 18:06:51.860298 CBT Training : PASS
4845 18:06:51.863709 Write leveling : PASS
4846 18:06:51.863819 RX DQS gating : PASS
4847 18:06:51.866807 RX DQ/DQS(RDDQC) : PASS
4848 18:06:51.870398 TX DQ/DQS : PASS
4849 18:06:51.870493 RX DATLAT : PASS
4850 18:06:51.873968 RX DQ/DQS(Engine): PASS
4851 18:06:51.876529 TX OE : NO K
4852 18:06:51.876631 All Pass.
4853 18:06:51.876705
4854 18:06:51.876777 CH 1, Rank 1
4855 18:06:51.879881 SW Impedance : PASS
4856 18:06:51.883507 DUTY Scan : NO K
4857 18:06:51.883592 ZQ Calibration : PASS
4858 18:06:51.886652 Jitter Meter : NO K
4859 18:06:51.890110 CBT Training : PASS
4860 18:06:51.890188 Write leveling : PASS
4861 18:06:51.893486 RX DQS gating : PASS
4862 18:06:51.896883 RX DQ/DQS(RDDQC) : PASS
4863 18:06:51.896998 TX DQ/DQS : PASS
4864 18:06:51.900174 RX DATLAT : PASS
4865 18:06:51.900256 RX DQ/DQS(Engine): PASS
4866 18:06:51.903754 TX OE : NO K
4867 18:06:51.903832 All Pass.
4868 18:06:51.903895
4869 18:06:51.906812 DramC Write-DBI off
4870 18:06:51.910056 PER_BANK_REFRESH: Hybrid Mode
4871 18:06:51.910142 TX_TRACKING: ON
4872 18:06:51.919945 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4873 18:06:51.923441 [FAST_K] Save calibration result to emmc
4874 18:06:51.926904 dramc_set_vcore_voltage set vcore to 662500
4875 18:06:51.930365 Read voltage for 933, 3
4876 18:06:51.930443 Vio18 = 0
4877 18:06:51.930506 Vcore = 662500
4878 18:06:51.933910 Vdram = 0
4879 18:06:51.933991 Vddq = 0
4880 18:06:51.934055 Vmddr = 0
4881 18:06:51.940165 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4882 18:06:51.943582 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4883 18:06:51.946909 MEM_TYPE=3, freq_sel=17
4884 18:06:51.950273 sv_algorithm_assistance_LP4_1600
4885 18:06:51.953392 ============ PULL DRAM RESETB DOWN ============
4886 18:06:51.957191 ========== PULL DRAM RESETB DOWN end =========
4887 18:06:51.963465 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4888 18:06:51.967232 ===================================
4889 18:06:51.967322 LPDDR4 DRAM CONFIGURATION
4890 18:06:51.970534 ===================================
4891 18:06:51.973724 EX_ROW_EN[0] = 0x0
4892 18:06:51.977124 EX_ROW_EN[1] = 0x0
4893 18:06:51.977233 LP4Y_EN = 0x0
4894 18:06:51.980548 WORK_FSP = 0x0
4895 18:06:51.980627 WL = 0x3
4896 18:06:51.983696 RL = 0x3
4897 18:06:51.983772 BL = 0x2
4898 18:06:51.987436 RPST = 0x0
4899 18:06:51.987507 RD_PRE = 0x0
4900 18:06:51.990346 WR_PRE = 0x1
4901 18:06:51.990416 WR_PST = 0x0
4902 18:06:51.993865 DBI_WR = 0x0
4903 18:06:51.993964 DBI_RD = 0x0
4904 18:06:51.997316 OTF = 0x1
4905 18:06:52.000685 ===================================
4906 18:06:52.003950 ===================================
4907 18:06:52.004026 ANA top config
4908 18:06:52.007380 ===================================
4909 18:06:52.010287 DLL_ASYNC_EN = 0
4910 18:06:52.014153 ALL_SLAVE_EN = 1
4911 18:06:52.017048 NEW_RANK_MODE = 1
4912 18:06:52.017132 DLL_IDLE_MODE = 1
4913 18:06:52.020436 LP45_APHY_COMB_EN = 1
4914 18:06:52.024050 TX_ODT_DIS = 1
4915 18:06:52.027502 NEW_8X_MODE = 1
4916 18:06:52.030562 ===================================
4917 18:06:52.034109 ===================================
4918 18:06:52.034179 data_rate = 1866
4919 18:06:52.037506 CKR = 1
4920 18:06:52.040445 DQ_P2S_RATIO = 8
4921 18:06:52.043714 ===================================
4922 18:06:52.047229 CA_P2S_RATIO = 8
4923 18:06:52.050764 DQ_CA_OPEN = 0
4924 18:06:52.054357 DQ_SEMI_OPEN = 0
4925 18:06:52.054429 CA_SEMI_OPEN = 0
4926 18:06:52.057317 CA_FULL_RATE = 0
4927 18:06:52.060662 DQ_CKDIV4_EN = 1
4928 18:06:52.064168 CA_CKDIV4_EN = 1
4929 18:06:52.067337 CA_PREDIV_EN = 0
4930 18:06:52.070496 PH8_DLY = 0
4931 18:06:52.070590 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4932 18:06:52.074155 DQ_AAMCK_DIV = 4
4933 18:06:52.077415 CA_AAMCK_DIV = 4
4934 18:06:52.080600 CA_ADMCK_DIV = 4
4935 18:06:52.083927 DQ_TRACK_CA_EN = 0
4936 18:06:52.084012 CA_PICK = 933
4937 18:06:52.087574 CA_MCKIO = 933
4938 18:06:52.091007 MCKIO_SEMI = 0
4939 18:06:52.093972 PLL_FREQ = 3732
4940 18:06:52.097377 DQ_UI_PI_RATIO = 32
4941 18:06:52.101127 CA_UI_PI_RATIO = 0
4942 18:06:52.104269 ===================================
4943 18:06:52.107280 ===================================
4944 18:06:52.110747 memory_type:LPDDR4
4945 18:06:52.110821 GP_NUM : 10
4946 18:06:52.113900 SRAM_EN : 1
4947 18:06:52.113972 MD32_EN : 0
4948 18:06:52.117273 ===================================
4949 18:06:52.120810 [ANA_INIT] >>>>>>>>>>>>>>
4950 18:06:52.124307 <<<<<< [CONFIGURE PHASE]: ANA_TX
4951 18:06:52.127281 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4952 18:06:52.130730 ===================================
4953 18:06:52.133695 data_rate = 1866,PCW = 0X8f00
4954 18:06:52.137217 ===================================
4955 18:06:52.140739 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4956 18:06:52.143610 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4957 18:06:52.150724 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4958 18:06:52.153611 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4959 18:06:52.160695 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4960 18:06:52.164170 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4961 18:06:52.164245 [ANA_INIT] flow start
4962 18:06:52.167193 [ANA_INIT] PLL >>>>>>>>
4963 18:06:52.170669 [ANA_INIT] PLL <<<<<<<<
4964 18:06:52.170741 [ANA_INIT] MIDPI >>>>>>>>
4965 18:06:52.174008 [ANA_INIT] MIDPI <<<<<<<<
4966 18:06:52.177496 [ANA_INIT] DLL >>>>>>>>
4967 18:06:52.177565 [ANA_INIT] flow end
4968 18:06:52.180537 ============ LP4 DIFF to SE enter ============
4969 18:06:52.187204 ============ LP4 DIFF to SE exit ============
4970 18:06:52.187277 [ANA_INIT] <<<<<<<<<<<<<
4971 18:06:52.190605 [Flow] Enable top DCM control >>>>>
4972 18:06:52.193990 [Flow] Enable top DCM control <<<<<
4973 18:06:52.197411 Enable DLL master slave shuffle
4974 18:06:52.203799 ==============================================================
4975 18:06:52.203873 Gating Mode config
4976 18:06:52.210998 ==============================================================
4977 18:06:52.213878 Config description:
4978 18:06:52.223670 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4979 18:06:52.230599 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4980 18:06:52.233761 SELPH_MODE 0: By rank 1: By Phase
4981 18:06:52.240729 ==============================================================
4982 18:06:52.243685 GAT_TRACK_EN = 1
4983 18:06:52.243769 RX_GATING_MODE = 2
4984 18:06:52.247250 RX_GATING_TRACK_MODE = 2
4985 18:06:52.250812 SELPH_MODE = 1
4986 18:06:52.253628 PICG_EARLY_EN = 1
4987 18:06:52.257035 VALID_LAT_VALUE = 1
4988 18:06:52.264066 ==============================================================
4989 18:06:52.267034 Enter into Gating configuration >>>>
4990 18:06:52.270811 Exit from Gating configuration <<<<
4991 18:06:52.273968 Enter into DVFS_PRE_config >>>>>
4992 18:06:52.284020 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4993 18:06:52.287358 Exit from DVFS_PRE_config <<<<<
4994 18:06:52.290256 Enter into PICG configuration >>>>
4995 18:06:52.294124 Exit from PICG configuration <<<<
4996 18:06:52.297347 [RX_INPUT] configuration >>>>>
4997 18:06:52.297445 [RX_INPUT] configuration <<<<<
4998 18:06:52.304191 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4999 18:06:52.310860 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5000 18:06:52.313898 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5001 18:06:52.320884 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5002 18:06:52.327334 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5003 18:06:52.334081 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5004 18:06:52.337134 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5005 18:06:52.340521 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5006 18:06:52.347204 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5007 18:06:52.350498 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5008 18:06:52.354160 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5009 18:06:52.357512 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5010 18:06:52.361039 ===================================
5011 18:06:52.364055 LPDDR4 DRAM CONFIGURATION
5012 18:06:52.367600 ===================================
5013 18:06:52.370698 EX_ROW_EN[0] = 0x0
5014 18:06:52.370768 EX_ROW_EN[1] = 0x0
5015 18:06:52.374093 LP4Y_EN = 0x0
5016 18:06:52.374172 WORK_FSP = 0x0
5017 18:06:52.377807 WL = 0x3
5018 18:06:52.377883 RL = 0x3
5019 18:06:52.380671 BL = 0x2
5020 18:06:52.380768 RPST = 0x0
5021 18:06:52.384355 RD_PRE = 0x0
5022 18:06:52.384425 WR_PRE = 0x1
5023 18:06:52.387352 WR_PST = 0x0
5024 18:06:52.387425 DBI_WR = 0x0
5025 18:06:52.390876 DBI_RD = 0x0
5026 18:06:52.394304 OTF = 0x1
5027 18:06:52.394378 ===================================
5028 18:06:52.400812 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5029 18:06:52.404291 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5030 18:06:52.407728 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5031 18:06:52.410943 ===================================
5032 18:06:52.414252 LPDDR4 DRAM CONFIGURATION
5033 18:06:52.417476 ===================================
5034 18:06:52.420912 EX_ROW_EN[0] = 0x10
5035 18:06:52.421040 EX_ROW_EN[1] = 0x0
5036 18:06:52.424096 LP4Y_EN = 0x0
5037 18:06:52.424174 WORK_FSP = 0x0
5038 18:06:52.427679 WL = 0x3
5039 18:06:52.427750 RL = 0x3
5040 18:06:52.430671 BL = 0x2
5041 18:06:52.430741 RPST = 0x0
5042 18:06:52.434301 RD_PRE = 0x0
5043 18:06:52.434373 WR_PRE = 0x1
5044 18:06:52.437728 WR_PST = 0x0
5045 18:06:52.437798 DBI_WR = 0x0
5046 18:06:52.440701 DBI_RD = 0x0
5047 18:06:52.440768 OTF = 0x1
5048 18:06:52.444094 ===================================
5049 18:06:52.450590 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5050 18:06:52.455174 nWR fixed to 30
5051 18:06:52.458719 [ModeRegInit_LP4] CH0 RK0
5052 18:06:52.458812 [ModeRegInit_LP4] CH0 RK1
5053 18:06:52.461781 [ModeRegInit_LP4] CH1 RK0
5054 18:06:52.465266 [ModeRegInit_LP4] CH1 RK1
5055 18:06:52.465340 match AC timing 9
5056 18:06:52.472063 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5057 18:06:52.475043 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5058 18:06:52.478540 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5059 18:06:52.484945 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5060 18:06:52.488510 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5061 18:06:52.488610 ==
5062 18:06:52.491617 Dram Type= 6, Freq= 0, CH_0, rank 0
5063 18:06:52.495096 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5064 18:06:52.495203 ==
5065 18:06:52.502124 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5066 18:06:52.508811 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5067 18:06:52.511734 [CA 0] Center 38 (8~69) winsize 62
5068 18:06:52.515115 [CA 1] Center 38 (8~68) winsize 61
5069 18:06:52.518632 [CA 2] Center 35 (5~66) winsize 62
5070 18:06:52.521986 [CA 3] Center 34 (4~65) winsize 62
5071 18:06:52.525232 [CA 4] Center 34 (4~65) winsize 62
5072 18:06:52.528562 [CA 5] Center 34 (4~64) winsize 61
5073 18:06:52.528662
5074 18:06:52.532231 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5075 18:06:52.532328
5076 18:06:52.535486 [CATrainingPosCal] consider 1 rank data
5077 18:06:52.538546 u2DelayCellTimex100 = 270/100 ps
5078 18:06:52.542120 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5079 18:06:52.545742 CA1 delay=38 (8~68),Diff = 4 PI (24 cell)
5080 18:06:52.548773 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5081 18:06:52.552285 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5082 18:06:52.555802 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5083 18:06:52.558803 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5084 18:06:52.558929
5085 18:06:52.562310 CA PerBit enable=1, Macro0, CA PI delay=34
5086 18:06:52.565600
5087 18:06:52.565675 [CBTSetCACLKResult] CA Dly = 34
5088 18:06:52.568970 CS Dly: 6 (0~37)
5089 18:06:52.569084 ==
5090 18:06:52.572102 Dram Type= 6, Freq= 0, CH_0, rank 1
5091 18:06:52.575479 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5092 18:06:52.575579 ==
5093 18:06:52.582434 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5094 18:06:52.589065 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5095 18:06:52.592093 [CA 0] Center 38 (8~69) winsize 62
5096 18:06:52.595570 [CA 1] Center 38 (8~69) winsize 62
5097 18:06:52.599201 [CA 2] Center 35 (5~66) winsize 62
5098 18:06:52.602074 [CA 3] Center 35 (4~66) winsize 63
5099 18:06:52.605353 [CA 4] Center 34 (4~65) winsize 62
5100 18:06:52.608884 [CA 5] Center 33 (3~64) winsize 62
5101 18:06:52.608959
5102 18:06:52.612536 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5103 18:06:52.612640
5104 18:06:52.615368 [CATrainingPosCal] consider 2 rank data
5105 18:06:52.618646 u2DelayCellTimex100 = 270/100 ps
5106 18:06:52.622469 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5107 18:06:52.625844 CA1 delay=38 (8~68),Diff = 4 PI (24 cell)
5108 18:06:52.629381 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5109 18:06:52.632256 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5110 18:06:52.635744 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5111 18:06:52.638982 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5112 18:06:52.639086
5113 18:06:52.642501 CA PerBit enable=1, Macro0, CA PI delay=34
5114 18:06:52.642600
5115 18:06:52.645620 [CBTSetCACLKResult] CA Dly = 34
5116 18:06:52.649175 CS Dly: 7 (0~39)
5117 18:06:52.649251
5118 18:06:52.652583 ----->DramcWriteLeveling(PI) begin...
5119 18:06:52.652687 ==
5120 18:06:52.655785 Dram Type= 6, Freq= 0, CH_0, rank 0
5121 18:06:52.659073 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5122 18:06:52.659250 ==
5123 18:06:52.662591 Write leveling (Byte 0): 32 => 32
5124 18:06:52.666102 Write leveling (Byte 1): 24 => 24
5125 18:06:52.669483 DramcWriteLeveling(PI) end<-----
5126 18:06:52.669568
5127 18:06:52.669652 ==
5128 18:06:52.672346 Dram Type= 6, Freq= 0, CH_0, rank 0
5129 18:06:52.675877 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5130 18:06:52.675960 ==
5131 18:06:52.679237 [Gating] SW mode calibration
5132 18:06:52.685556 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5133 18:06:52.692354 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5134 18:06:52.695675 0 14 0 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
5135 18:06:52.699135 0 14 4 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
5136 18:06:52.705860 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5137 18:06:52.709166 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5138 18:06:52.712304 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5139 18:06:52.718786 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5140 18:06:52.722244 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5141 18:06:52.725793 0 14 28 | B1->B0 | 3434 3232 | 1 0 | (1 0) (1 0)
5142 18:06:52.732311 0 15 0 | B1->B0 | 3232 2929 | 1 1 | (1 1) (1 0)
5143 18:06:52.735755 0 15 4 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
5144 18:06:52.738772 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5145 18:06:52.745604 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5146 18:06:52.748962 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5147 18:06:52.752486 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5148 18:06:52.758905 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5149 18:06:52.762466 0 15 28 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
5150 18:06:52.765941 1 0 0 | B1->B0 | 3333 3b3b | 0 0 | (0 0) (0 0)
5151 18:06:52.772359 1 0 4 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
5152 18:06:52.775964 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5153 18:06:52.778997 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5154 18:06:52.785430 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5155 18:06:52.788958 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5156 18:06:52.792288 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5157 18:06:52.795534 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5158 18:06:52.802209 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5159 18:06:52.805491 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5160 18:06:52.809167 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5161 18:06:52.815776 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5162 18:06:52.819196 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5163 18:06:52.822059 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5164 18:06:52.828929 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5165 18:06:52.832412 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5166 18:06:52.835909 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5167 18:06:52.842285 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5168 18:06:52.845714 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5169 18:06:52.849220 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5170 18:06:52.855397 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5171 18:06:52.858985 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5172 18:06:52.862501 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5173 18:06:52.868790 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5174 18:06:52.872268 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5175 18:06:52.875765 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5176 18:06:52.878765 Total UI for P1: 0, mck2ui 16
5177 18:06:52.882220 best dqsien dly found for B0: ( 1, 2, 30)
5178 18:06:52.888653 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5179 18:06:52.888734 Total UI for P1: 0, mck2ui 16
5180 18:06:52.892255 best dqsien dly found for B1: ( 1, 3, 0)
5181 18:06:52.895790 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5182 18:06:52.899334 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5183 18:06:52.902248
5184 18:06:52.905574 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5185 18:06:52.909171 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5186 18:06:52.912413 [Gating] SW calibration Done
5187 18:06:52.912520 ==
5188 18:06:52.915627 Dram Type= 6, Freq= 0, CH_0, rank 0
5189 18:06:52.918796 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5190 18:06:52.918879 ==
5191 18:06:52.918942 RX Vref Scan: 0
5192 18:06:52.919001
5193 18:06:52.922188 RX Vref 0 -> 0, step: 1
5194 18:06:52.922284
5195 18:06:52.925585 RX Delay -80 -> 252, step: 8
5196 18:06:52.928941 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5197 18:06:52.932432 iDelay=208, Bit 1, Center 103 (8 ~ 199) 192
5198 18:06:52.935978 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5199 18:06:52.942335 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5200 18:06:52.945840 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5201 18:06:52.949368 iDelay=208, Bit 5, Center 83 (-16 ~ 183) 200
5202 18:06:52.952853 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5203 18:06:52.955778 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5204 18:06:52.959173 iDelay=208, Bit 8, Center 75 (-16 ~ 167) 184
5205 18:06:52.966128 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5206 18:06:52.969015 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5207 18:06:52.972494 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5208 18:06:52.975984 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5209 18:06:52.978962 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5210 18:06:52.985804 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5211 18:06:52.989291 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5212 18:06:52.989367 ==
5213 18:06:52.992833 Dram Type= 6, Freq= 0, CH_0, rank 0
5214 18:06:52.995837 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5215 18:06:52.995918 ==
5216 18:06:52.995983 DQS Delay:
5217 18:06:52.999437 DQS0 = 0, DQS1 = 0
5218 18:06:52.999518 DQM Delay:
5219 18:06:53.002720 DQM0 = 97, DQM1 = 86
5220 18:06:53.002818 DQ Delay:
5221 18:06:53.005726 DQ0 =95, DQ1 =103, DQ2 =95, DQ3 =91
5222 18:06:53.009186 DQ4 =103, DQ5 =83, DQ6 =107, DQ7 =103
5223 18:06:53.012614 DQ8 =75, DQ9 =75, DQ10 =87, DQ11 =79
5224 18:06:53.016012 DQ12 =91, DQ13 =95, DQ14 =95, DQ15 =95
5225 18:06:53.016109
5226 18:06:53.016205
5227 18:06:53.016279 ==
5228 18:06:53.019353 Dram Type= 6, Freq= 0, CH_0, rank 0
5229 18:06:53.022765 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5230 18:06:53.025963 ==
5231 18:06:53.026059
5232 18:06:53.026124
5233 18:06:53.026183 TX Vref Scan disable
5234 18:06:53.029240 == TX Byte 0 ==
5235 18:06:53.032377 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5236 18:06:53.035736 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5237 18:06:53.039619 == TX Byte 1 ==
5238 18:06:53.042624 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5239 18:06:53.046077 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5240 18:06:53.049422 ==
5241 18:06:53.049503 Dram Type= 6, Freq= 0, CH_0, rank 0
5242 18:06:53.055902 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5243 18:06:53.055992 ==
5244 18:06:53.056058
5245 18:06:53.056118
5246 18:06:53.059457 TX Vref Scan disable
5247 18:06:53.059560 == TX Byte 0 ==
5248 18:06:53.065785 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5249 18:06:53.069010 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5250 18:06:53.069106 == TX Byte 1 ==
5251 18:06:53.075963 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5252 18:06:53.079308 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5253 18:06:53.079389
5254 18:06:53.079454 [DATLAT]
5255 18:06:53.082763 Freq=933, CH0 RK0
5256 18:06:53.082843
5257 18:06:53.082908 DATLAT Default: 0xd
5258 18:06:53.085693 0, 0xFFFF, sum = 0
5259 18:06:53.085776 1, 0xFFFF, sum = 0
5260 18:06:53.089190 2, 0xFFFF, sum = 0
5261 18:06:53.089272 3, 0xFFFF, sum = 0
5262 18:06:53.092712 4, 0xFFFF, sum = 0
5263 18:06:53.092794 5, 0xFFFF, sum = 0
5264 18:06:53.095670 6, 0xFFFF, sum = 0
5265 18:06:53.095752 7, 0xFFFF, sum = 0
5266 18:06:53.099146 8, 0xFFFF, sum = 0
5267 18:06:53.099229 9, 0xFFFF, sum = 0
5268 18:06:53.102586 10, 0x0, sum = 1
5269 18:06:53.102669 11, 0x0, sum = 2
5270 18:06:53.106037 12, 0x0, sum = 3
5271 18:06:53.106119 13, 0x0, sum = 4
5272 18:06:53.109581 best_step = 11
5273 18:06:53.109661
5274 18:06:53.109724 ==
5275 18:06:53.112475 Dram Type= 6, Freq= 0, CH_0, rank 0
5276 18:06:53.115896 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5277 18:06:53.115993 ==
5278 18:06:53.119565 RX Vref Scan: 1
5279 18:06:53.119661
5280 18:06:53.119756 RX Vref 0 -> 0, step: 1
5281 18:06:53.119847
5282 18:06:53.122916 RX Delay -61 -> 252, step: 4
5283 18:06:53.123001
5284 18:06:53.126295 Set Vref, RX VrefLevel [Byte0]: 51
5285 18:06:53.129158 [Byte1]: 51
5286 18:06:53.132961
5287 18:06:53.133081 Final RX Vref Byte 0 = 51 to rank0
5288 18:06:53.136782 Final RX Vref Byte 1 = 51 to rank0
5289 18:06:53.139521 Final RX Vref Byte 0 = 51 to rank1
5290 18:06:53.143549 Final RX Vref Byte 1 = 51 to rank1==
5291 18:06:53.146461 Dram Type= 6, Freq= 0, CH_0, rank 0
5292 18:06:53.153336 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5293 18:06:53.153422 ==
5294 18:06:53.153486 DQS Delay:
5295 18:06:53.153545 DQS0 = 0, DQS1 = 0
5296 18:06:53.156778 DQM Delay:
5297 18:06:53.156872 DQM0 = 96, DQM1 = 88
5298 18:06:53.159960 DQ Delay:
5299 18:06:53.163415 DQ0 =98, DQ1 =98, DQ2 =92, DQ3 =94
5300 18:06:53.166516 DQ4 =98, DQ5 =86, DQ6 =104, DQ7 =104
5301 18:06:53.170131 DQ8 =78, DQ9 =78, DQ10 =88, DQ11 =80
5302 18:06:53.172925 DQ12 =94, DQ13 =90, DQ14 =98, DQ15 =98
5303 18:06:53.173036
5304 18:06:53.173100
5305 18:06:53.179945 [DQSOSCAuto] RK0, (LSB)MR18= 0x11fc, (MSB)MR19= 0x504, tDQSOscB0 = 423 ps tDQSOscB1 = 416 ps
5306 18:06:53.183398 CH0 RK0: MR19=504, MR18=11FC
5307 18:06:53.189942 CH0_RK0: MR19=0x504, MR18=0x11FC, DQSOSC=416, MR23=63, INC=62, DEC=41
5308 18:06:53.190021
5309 18:06:53.193335 ----->DramcWriteLeveling(PI) begin...
5310 18:06:53.193412 ==
5311 18:06:53.196693 Dram Type= 6, Freq= 0, CH_0, rank 1
5312 18:06:53.199779 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5313 18:06:53.199855 ==
5314 18:06:53.203256 Write leveling (Byte 0): 33 => 33
5315 18:06:53.206272 Write leveling (Byte 1): 28 => 28
5316 18:06:53.209770 DramcWriteLeveling(PI) end<-----
5317 18:06:53.209841
5318 18:06:53.209902 ==
5319 18:06:53.213274 Dram Type= 6, Freq= 0, CH_0, rank 1
5320 18:06:53.216153 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5321 18:06:53.216233 ==
5322 18:06:53.219464 [Gating] SW mode calibration
5323 18:06:53.226463 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5324 18:06:53.232938 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5325 18:06:53.236551 0 14 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
5326 18:06:53.239674 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5327 18:06:53.246319 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5328 18:06:53.249788 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5329 18:06:53.253232 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5330 18:06:53.259592 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5331 18:06:53.263090 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
5332 18:06:53.266349 0 14 28 | B1->B0 | 3434 2e2e | 0 0 | (0 0) (0 0)
5333 18:06:53.273316 0 15 0 | B1->B0 | 2e2e 2323 | 0 0 | (0 1) (0 0)
5334 18:06:53.276204 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5335 18:06:53.279631 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5336 18:06:53.286669 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5337 18:06:53.289893 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5338 18:06:53.293339 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5339 18:06:53.299815 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5340 18:06:53.302887 0 15 28 | B1->B0 | 2424 3636 | 0 0 | (0 0) (0 0)
5341 18:06:53.306303 1 0 0 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
5342 18:06:53.309984 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5343 18:06:53.316314 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5344 18:06:53.319913 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5345 18:06:53.323549 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5346 18:06:53.329592 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5347 18:06:53.333171 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5348 18:06:53.336138 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5349 18:06:53.343362 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5350 18:06:53.346184 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5351 18:06:53.349940 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5352 18:06:53.356278 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5353 18:06:53.360115 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5354 18:06:53.363060 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5355 18:06:53.369539 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5356 18:06:53.373295 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5357 18:06:53.376226 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5358 18:06:53.383332 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5359 18:06:53.386674 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5360 18:06:53.390052 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5361 18:06:53.396177 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5362 18:06:53.399638 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5363 18:06:53.403168 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5364 18:06:53.409556 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5365 18:06:53.413250 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5366 18:06:53.416334 Total UI for P1: 0, mck2ui 16
5367 18:06:53.419642 best dqsien dly found for B0: ( 1, 2, 26)
5368 18:06:53.423105 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5369 18:06:53.426455 Total UI for P1: 0, mck2ui 16
5370 18:06:53.430061 best dqsien dly found for B1: ( 1, 3, 0)
5371 18:06:53.432996 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5372 18:06:53.436483 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5373 18:06:53.436563
5374 18:06:53.440091 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5375 18:06:53.443078 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5376 18:06:53.446194 [Gating] SW calibration Done
5377 18:06:53.446275 ==
5378 18:06:53.449716 Dram Type= 6, Freq= 0, CH_0, rank 1
5379 18:06:53.456270 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5380 18:06:53.456351 ==
5381 18:06:53.456416 RX Vref Scan: 0
5382 18:06:53.456501
5383 18:06:53.459723 RX Vref 0 -> 0, step: 1
5384 18:06:53.459804
5385 18:06:53.463213 RX Delay -80 -> 252, step: 8
5386 18:06:53.466169 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5387 18:06:53.469690 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5388 18:06:53.473306 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5389 18:06:53.476202 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5390 18:06:53.479454 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5391 18:06:53.486523 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5392 18:06:53.490528 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5393 18:06:53.493018 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5394 18:06:53.496403 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5395 18:06:53.499675 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5396 18:06:53.503088 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5397 18:06:53.509774 iDelay=208, Bit 11, Center 75 (-16 ~ 167) 184
5398 18:06:53.513317 iDelay=208, Bit 12, Center 87 (-8 ~ 183) 192
5399 18:06:53.516299 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5400 18:06:53.519961 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5401 18:06:53.523312 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5402 18:06:53.523422 ==
5403 18:06:53.526786 Dram Type= 6, Freq= 0, CH_0, rank 1
5404 18:06:53.533120 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5405 18:06:53.533201 ==
5406 18:06:53.533303 DQS Delay:
5407 18:06:53.536609 DQS0 = 0, DQS1 = 0
5408 18:06:53.536689 DQM Delay:
5409 18:06:53.536792 DQM0 = 96, DQM1 = 86
5410 18:06:53.540024 DQ Delay:
5411 18:06:53.542833 DQ0 =95, DQ1 =99, DQ2 =95, DQ3 =91
5412 18:06:53.546388 DQ4 =95, DQ5 =87, DQ6 =107, DQ7 =103
5413 18:06:53.550024 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =75
5414 18:06:53.552910 DQ12 =87, DQ13 =95, DQ14 =95, DQ15 =95
5415 18:06:53.553038
5416 18:06:53.553106
5417 18:06:53.553165 ==
5418 18:06:53.556426 Dram Type= 6, Freq= 0, CH_0, rank 1
5419 18:06:53.559902 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5420 18:06:53.560009 ==
5421 18:06:53.560100
5422 18:06:53.560259
5423 18:06:53.562813 TX Vref Scan disable
5424 18:06:53.566447 == TX Byte 0 ==
5425 18:06:53.569380 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5426 18:06:53.572907 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5427 18:06:53.575974 == TX Byte 1 ==
5428 18:06:53.579558 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5429 18:06:53.582642 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5430 18:06:53.582725 ==
5431 18:06:53.586126 Dram Type= 6, Freq= 0, CH_0, rank 1
5432 18:06:53.589659 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5433 18:06:53.589743 ==
5434 18:06:53.589827
5435 18:06:53.593128
5436 18:06:53.593210 TX Vref Scan disable
5437 18:06:53.596045 == TX Byte 0 ==
5438 18:06:53.599623 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5439 18:06:53.603237 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5440 18:06:53.606148 == TX Byte 1 ==
5441 18:06:53.609685 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5442 18:06:53.612804 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5443 18:06:53.616192
5444 18:06:53.616302 [DATLAT]
5445 18:06:53.616400 Freq=933, CH0 RK1
5446 18:06:53.616497
5447 18:06:53.619631 DATLAT Default: 0xb
5448 18:06:53.619731 0, 0xFFFF, sum = 0
5449 18:06:53.622704 1, 0xFFFF, sum = 0
5450 18:06:53.622785 2, 0xFFFF, sum = 0
5451 18:06:53.626182 3, 0xFFFF, sum = 0
5452 18:06:53.626286 4, 0xFFFF, sum = 0
5453 18:06:53.629687 5, 0xFFFF, sum = 0
5454 18:06:53.629796 6, 0xFFFF, sum = 0
5455 18:06:53.633269 7, 0xFFFF, sum = 0
5456 18:06:53.635981 8, 0xFFFF, sum = 0
5457 18:06:53.636062 9, 0xFFFF, sum = 0
5458 18:06:53.639748 10, 0x0, sum = 1
5459 18:06:53.639829 11, 0x0, sum = 2
5460 18:06:53.639893 12, 0x0, sum = 3
5461 18:06:53.643150 13, 0x0, sum = 4
5462 18:06:53.643232 best_step = 11
5463 18:06:53.643295
5464 18:06:53.643354 ==
5465 18:06:53.646145 Dram Type= 6, Freq= 0, CH_0, rank 1
5466 18:06:53.653049 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5467 18:06:53.653129 ==
5468 18:06:53.653192 RX Vref Scan: 0
5469 18:06:53.653251
5470 18:06:53.656059 RX Vref 0 -> 0, step: 1
5471 18:06:53.656166
5472 18:06:53.659657 RX Delay -61 -> 252, step: 4
5473 18:06:53.662730 iDelay=199, Bit 0, Center 96 (3 ~ 190) 188
5474 18:06:53.665974 iDelay=199, Bit 1, Center 96 (3 ~ 190) 188
5475 18:06:53.673126 iDelay=199, Bit 2, Center 92 (-1 ~ 186) 188
5476 18:06:53.676016 iDelay=199, Bit 3, Center 94 (-1 ~ 190) 192
5477 18:06:53.679655 iDelay=199, Bit 4, Center 96 (7 ~ 186) 180
5478 18:06:53.682569 iDelay=199, Bit 5, Center 84 (-9 ~ 178) 188
5479 18:06:53.686165 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5480 18:06:53.689680 iDelay=199, Bit 7, Center 102 (11 ~ 194) 184
5481 18:06:53.696351 iDelay=199, Bit 8, Center 80 (-9 ~ 170) 180
5482 18:06:53.699262 iDelay=199, Bit 9, Center 78 (-9 ~ 166) 176
5483 18:06:53.702734 iDelay=199, Bit 10, Center 88 (-1 ~ 178) 180
5484 18:06:53.705989 iDelay=199, Bit 11, Center 78 (-9 ~ 166) 176
5485 18:06:53.709621 iDelay=199, Bit 12, Center 92 (3 ~ 182) 180
5486 18:06:53.715889 iDelay=199, Bit 13, Center 94 (7 ~ 182) 176
5487 18:06:53.719296 iDelay=199, Bit 14, Center 96 (7 ~ 186) 180
5488 18:06:53.722663 iDelay=199, Bit 15, Center 94 (7 ~ 182) 176
5489 18:06:53.722743 ==
5490 18:06:53.726159 Dram Type= 6, Freq= 0, CH_0, rank 1
5491 18:06:53.729240 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5492 18:06:53.729321 ==
5493 18:06:53.732806 DQS Delay:
5494 18:06:53.732885 DQS0 = 0, DQS1 = 0
5495 18:06:53.732948 DQM Delay:
5496 18:06:53.735937 DQM0 = 95, DQM1 = 87
5497 18:06:53.736017 DQ Delay:
5498 18:06:53.739626 DQ0 =96, DQ1 =96, DQ2 =92, DQ3 =94
5499 18:06:53.742960 DQ4 =96, DQ5 =84, DQ6 =104, DQ7 =102
5500 18:06:53.746245 DQ8 =80, DQ9 =78, DQ10 =88, DQ11 =78
5501 18:06:53.750008 DQ12 =92, DQ13 =94, DQ14 =96, DQ15 =94
5502 18:06:53.750089
5503 18:06:53.750153
5504 18:06:53.759492 [DQSOSCAuto] RK1, (LSB)MR18= 0x1a09, (MSB)MR19= 0x505, tDQSOscB0 = 419 ps tDQSOscB1 = 413 ps
5505 18:06:53.759575 CH0 RK1: MR19=505, MR18=1A09
5506 18:06:53.766092 CH0_RK1: MR19=0x505, MR18=0x1A09, DQSOSC=413, MR23=63, INC=63, DEC=42
5507 18:06:53.769507 [RxdqsGatingPostProcess] freq 933
5508 18:06:53.776776 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5509 18:06:53.780140 best DQS0 dly(2T, 0.5T) = (0, 10)
5510 18:06:53.783392 best DQS1 dly(2T, 0.5T) = (0, 11)
5511 18:06:53.786250 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5512 18:06:53.789592 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5513 18:06:53.792957 best DQS0 dly(2T, 0.5T) = (0, 10)
5514 18:06:53.793084 best DQS1 dly(2T, 0.5T) = (0, 11)
5515 18:06:53.796575 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5516 18:06:53.799449 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5517 18:06:53.803006 Pre-setting of DQS Precalculation
5518 18:06:53.809661 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5519 18:06:53.809785 ==
5520 18:06:53.813167 Dram Type= 6, Freq= 0, CH_1, rank 0
5521 18:06:53.816443 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5522 18:06:53.816598 ==
5523 18:06:53.823430 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5524 18:06:53.829575 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5525 18:06:53.832936 [CA 0] Center 36 (6~67) winsize 62
5526 18:06:53.836425 [CA 1] Center 36 (6~67) winsize 62
5527 18:06:53.839732 [CA 2] Center 34 (4~64) winsize 61
5528 18:06:53.843205 [CA 3] Center 33 (3~64) winsize 62
5529 18:06:53.846363 [CA 4] Center 34 (4~65) winsize 62
5530 18:06:53.846489 [CA 5] Center 33 (3~64) winsize 62
5531 18:06:53.849836
5532 18:06:53.852857 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5533 18:06:53.852966
5534 18:06:53.856303 [CATrainingPosCal] consider 1 rank data
5535 18:06:53.859532 u2DelayCellTimex100 = 270/100 ps
5536 18:06:53.863100 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5537 18:06:53.866615 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5538 18:06:53.870054 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5539 18:06:53.872991 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5540 18:06:53.876643 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5541 18:06:53.880095 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5542 18:06:53.880319
5543 18:06:53.883125 CA PerBit enable=1, Macro0, CA PI delay=33
5544 18:06:53.883363
5545 18:06:53.886499 [CBTSetCACLKResult] CA Dly = 33
5546 18:06:53.889667 CS Dly: 4 (0~35)
5547 18:06:53.889902 ==
5548 18:06:53.893300 Dram Type= 6, Freq= 0, CH_1, rank 1
5549 18:06:53.896910 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5550 18:06:53.897199 ==
5551 18:06:53.903512 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5552 18:06:53.906554 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5553 18:06:53.910825 [CA 0] Center 36 (6~67) winsize 62
5554 18:06:53.914363 [CA 1] Center 37 (7~67) winsize 61
5555 18:06:53.918108 [CA 2] Center 33 (3~64) winsize 62
5556 18:06:53.921423 [CA 3] Center 33 (2~64) winsize 63
5557 18:06:53.924553 [CA 4] Center 34 (4~64) winsize 61
5558 18:06:53.927584 [CA 5] Center 33 (2~64) winsize 63
5559 18:06:53.927998
5560 18:06:53.931065 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5561 18:06:53.931566
5562 18:06:53.934425 [CATrainingPosCal] consider 2 rank data
5563 18:06:53.938103 u2DelayCellTimex100 = 270/100 ps
5564 18:06:53.941678 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5565 18:06:53.944353 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5566 18:06:53.951553 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5567 18:06:53.954522 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5568 18:06:53.957653 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5569 18:06:53.961016 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5570 18:06:53.961433
5571 18:06:53.964257 CA PerBit enable=1, Macro0, CA PI delay=33
5572 18:06:53.964815
5573 18:06:53.967842 [CBTSetCACLKResult] CA Dly = 33
5574 18:06:53.968365 CS Dly: 5 (0~38)
5575 18:06:53.968841
5576 18:06:53.971081 ----->DramcWriteLeveling(PI) begin...
5577 18:06:53.974709 ==
5578 18:06:53.975248 Dram Type= 6, Freq= 0, CH_1, rank 0
5579 18:06:53.981093 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5580 18:06:53.981616 ==
5581 18:06:53.984659 Write leveling (Byte 0): 28 => 28
5582 18:06:53.987652 Write leveling (Byte 1): 30 => 30
5583 18:06:53.991135 DramcWriteLeveling(PI) end<-----
5584 18:06:53.991699
5585 18:06:53.992257 ==
5586 18:06:53.994579 Dram Type= 6, Freq= 0, CH_1, rank 0
5587 18:06:53.997885 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5588 18:06:53.998424 ==
5589 18:06:54.001314 [Gating] SW mode calibration
5590 18:06:54.007876 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5591 18:06:54.011351 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5592 18:06:54.017857 0 14 0 | B1->B0 | 3131 2f2f | 1 1 | (1 1) (1 1)
5593 18:06:54.021558 0 14 4 | B1->B0 | 3535 3434 | 1 1 | (0 0) (1 1)
5594 18:06:54.024483 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5595 18:06:54.031324 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5596 18:06:54.034704 0 14 16 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5597 18:06:54.038047 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5598 18:06:54.044333 0 14 24 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5599 18:06:54.047796 0 14 28 | B1->B0 | 3131 3030 | 0 0 | (0 1) (0 0)
5600 18:06:54.051135 0 15 0 | B1->B0 | 2525 2929 | 1 0 | (1 0) (0 0)
5601 18:06:54.057666 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5602 18:06:54.061023 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5603 18:06:54.064087 0 15 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5604 18:06:54.071035 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5605 18:06:54.073986 0 15 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5606 18:06:54.077375 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5607 18:06:54.084619 0 15 28 | B1->B0 | 2e2e 2e2e | 0 0 | (0 0) (0 0)
5608 18:06:54.087408 1 0 0 | B1->B0 | 4443 4040 | 1 0 | (1 1) (0 0)
5609 18:06:54.091004 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5610 18:06:54.097440 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5611 18:06:54.100813 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5612 18:06:54.104222 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5613 18:06:54.107634 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5614 18:06:54.114553 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5615 18:06:54.117918 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5616 18:06:54.121480 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5617 18:06:54.128016 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5618 18:06:54.131081 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5619 18:06:54.134515 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5620 18:06:54.141243 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5621 18:06:54.144621 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5622 18:06:54.147687 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5623 18:06:54.154505 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5624 18:06:54.158113 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5625 18:06:54.161082 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5626 18:06:54.167631 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5627 18:06:54.171006 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5628 18:06:54.174652 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5629 18:06:54.181234 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5630 18:06:54.184640 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5631 18:06:54.187551 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5632 18:06:54.194660 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5633 18:06:54.195066 Total UI for P1: 0, mck2ui 16
5634 18:06:54.197834 best dqsien dly found for B0: ( 1, 2, 26)
5635 18:06:54.201002 Total UI for P1: 0, mck2ui 16
5636 18:06:54.204223 best dqsien dly found for B1: ( 1, 2, 26)
5637 18:06:54.207631 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5638 18:06:54.214890 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5639 18:06:54.215381
5640 18:06:54.217816 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5641 18:06:54.221068 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5642 18:06:54.224566 [Gating] SW calibration Done
5643 18:06:54.225002 ==
5644 18:06:54.228172 Dram Type= 6, Freq= 0, CH_1, rank 0
5645 18:06:54.230973 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5646 18:06:54.231381 ==
5647 18:06:54.231704 RX Vref Scan: 0
5648 18:06:54.234698
5649 18:06:54.235105 RX Vref 0 -> 0, step: 1
5650 18:06:54.235429
5651 18:06:54.237642 RX Delay -80 -> 252, step: 8
5652 18:06:54.241441 iDelay=200, Bit 0, Center 99 (8 ~ 191) 184
5653 18:06:54.244675 iDelay=200, Bit 1, Center 91 (0 ~ 183) 184
5654 18:06:54.251433 iDelay=200, Bit 2, Center 83 (-8 ~ 175) 184
5655 18:06:54.254203 iDelay=200, Bit 3, Center 99 (8 ~ 191) 184
5656 18:06:54.257539 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5657 18:06:54.261045 iDelay=200, Bit 5, Center 103 (8 ~ 199) 192
5658 18:06:54.263948 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5659 18:06:54.267614 iDelay=200, Bit 7, Center 95 (0 ~ 191) 192
5660 18:06:54.271408 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5661 18:06:54.277555 iDelay=200, Bit 9, Center 75 (-24 ~ 175) 200
5662 18:06:54.281147 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5663 18:06:54.284794 iDelay=200, Bit 11, Center 83 (-16 ~ 183) 200
5664 18:06:54.287906 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5665 18:06:54.291115 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5666 18:06:54.297849 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5667 18:06:54.301031 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5668 18:06:54.301440 ==
5669 18:06:54.304570 Dram Type= 6, Freq= 0, CH_1, rank 0
5670 18:06:54.307452 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5671 18:06:54.307861 ==
5672 18:06:54.308186 DQS Delay:
5673 18:06:54.311098 DQS0 = 0, DQS1 = 0
5674 18:06:54.311505 DQM Delay:
5675 18:06:54.314500 DQM0 = 96, DQM1 = 88
5676 18:06:54.314903 DQ Delay:
5677 18:06:54.317946 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =99
5678 18:06:54.321086 DQ4 =95, DQ5 =103, DQ6 =107, DQ7 =95
5679 18:06:54.324192 DQ8 =79, DQ9 =75, DQ10 =87, DQ11 =83
5680 18:06:54.327814 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5681 18:06:54.328331
5682 18:06:54.328665
5683 18:06:54.328967 ==
5684 18:06:54.331110 Dram Type= 6, Freq= 0, CH_1, rank 0
5685 18:06:54.334290 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5686 18:06:54.337511 ==
5687 18:06:54.337934
5688 18:06:54.338300
5689 18:06:54.338625 TX Vref Scan disable
5690 18:06:54.340916 == TX Byte 0 ==
5691 18:06:54.344451 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5692 18:06:54.347373 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5693 18:06:54.351680 == TX Byte 1 ==
5694 18:06:54.354334 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5695 18:06:54.357605 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5696 18:06:54.358074 ==
5697 18:06:54.361052 Dram Type= 6, Freq= 0, CH_1, rank 0
5698 18:06:54.367998 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5699 18:06:54.368416 ==
5700 18:06:54.368742
5701 18:06:54.369092
5702 18:06:54.369394 TX Vref Scan disable
5703 18:06:54.372151 == TX Byte 0 ==
5704 18:06:54.375600 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5705 18:06:54.382264 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5706 18:06:54.382674 == TX Byte 1 ==
5707 18:06:54.385320 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5708 18:06:54.392058 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5709 18:06:54.392473
5710 18:06:54.392792 [DATLAT]
5711 18:06:54.393203 Freq=933, CH1 RK0
5712 18:06:54.393678
5713 18:06:54.395615 DATLAT Default: 0xd
5714 18:06:54.396313 0, 0xFFFF, sum = 0
5715 18:06:54.398763 1, 0xFFFF, sum = 0
5716 18:06:54.399365 2, 0xFFFF, sum = 0
5717 18:06:54.401768 3, 0xFFFF, sum = 0
5718 18:06:54.402396 4, 0xFFFF, sum = 0
5719 18:06:54.405252 5, 0xFFFF, sum = 0
5720 18:06:54.408872 6, 0xFFFF, sum = 0
5721 18:06:54.409362 7, 0xFFFF, sum = 0
5722 18:06:54.411931 8, 0xFFFF, sum = 0
5723 18:06:54.412418 9, 0xFFFF, sum = 0
5724 18:06:54.415393 10, 0x0, sum = 1
5725 18:06:54.415923 11, 0x0, sum = 2
5726 18:06:54.416363 12, 0x0, sum = 3
5727 18:06:54.418764 13, 0x0, sum = 4
5728 18:06:54.419183 best_step = 11
5729 18:06:54.419510
5730 18:06:54.422364 ==
5731 18:06:54.422772 Dram Type= 6, Freq= 0, CH_1, rank 0
5732 18:06:54.428767 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5733 18:06:54.429230 ==
5734 18:06:54.429747 RX Vref Scan: 1
5735 18:06:54.430077
5736 18:06:54.431819 RX Vref 0 -> 0, step: 1
5737 18:06:54.432228
5738 18:06:54.435383 RX Delay -69 -> 252, step: 4
5739 18:06:54.435795
5740 18:06:54.439057 Set Vref, RX VrefLevel [Byte0]: 58
5741 18:06:54.442124 [Byte1]: 52
5742 18:06:54.442537
5743 18:06:54.445289 Final RX Vref Byte 0 = 58 to rank0
5744 18:06:54.448825 Final RX Vref Byte 1 = 52 to rank0
5745 18:06:54.452153 Final RX Vref Byte 0 = 58 to rank1
5746 18:06:54.455992 Final RX Vref Byte 1 = 52 to rank1==
5747 18:06:54.458649 Dram Type= 6, Freq= 0, CH_1, rank 0
5748 18:06:54.462067 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5749 18:06:54.462763 ==
5750 18:06:54.465227 DQS Delay:
5751 18:06:54.465756 DQS0 = 0, DQS1 = 0
5752 18:06:54.468925 DQM Delay:
5753 18:06:54.469381 DQM0 = 97, DQM1 = 90
5754 18:06:54.469884 DQ Delay:
5755 18:06:54.472167 DQ0 =100, DQ1 =90, DQ2 =86, DQ3 =96
5756 18:06:54.475167 DQ4 =96, DQ5 =108, DQ6 =108, DQ7 =92
5757 18:06:54.478754 DQ8 =78, DQ9 =78, DQ10 =90, DQ11 =88
5758 18:06:54.482434 DQ12 =96, DQ13 =98, DQ14 =96, DQ15 =96
5759 18:06:54.482867
5760 18:06:54.483206
5761 18:06:54.491747 [DQSOSCAuto] RK0, (LSB)MR18= 0x10ec, (MSB)MR19= 0x504, tDQSOscB0 = 428 ps tDQSOscB1 = 416 ps
5762 18:06:54.495499 CH1 RK0: MR19=504, MR18=10EC
5763 18:06:54.502038 CH1_RK0: MR19=0x504, MR18=0x10EC, DQSOSC=416, MR23=63, INC=62, DEC=41
5764 18:06:54.502450
5765 18:06:54.505554 ----->DramcWriteLeveling(PI) begin...
5766 18:06:54.505993 ==
5767 18:06:54.508464 Dram Type= 6, Freq= 0, CH_1, rank 1
5768 18:06:54.511787 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5769 18:06:54.512337 ==
5770 18:06:54.515245 Write leveling (Byte 0): 26 => 26
5771 18:06:54.518779 Write leveling (Byte 1): 25 => 25
5772 18:06:54.521759 DramcWriteLeveling(PI) end<-----
5773 18:06:54.522207
5774 18:06:54.522534 ==
5775 18:06:54.525115 Dram Type= 6, Freq= 0, CH_1, rank 1
5776 18:06:54.528142 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5777 18:06:54.528733 ==
5778 18:06:54.531650 [Gating] SW mode calibration
5779 18:06:54.538858 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5780 18:06:54.545420 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5781 18:06:54.548403 0 14 0 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5782 18:06:54.551964 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5783 18:06:54.558200 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5784 18:06:54.561997 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5785 18:06:54.565369 0 14 16 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5786 18:06:54.571763 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5787 18:06:54.575545 0 14 24 | B1->B0 | 3232 2e2e | 0 0 | (0 0) (0 0)
5788 18:06:54.578480 0 14 28 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
5789 18:06:54.585320 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5790 18:06:54.588335 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5791 18:06:54.591839 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5792 18:06:54.595497 0 15 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5793 18:06:54.601794 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5794 18:06:54.605281 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5795 18:06:54.608830 0 15 24 | B1->B0 | 2525 3030 | 0 0 | (0 0) (0 0)
5796 18:06:54.615210 0 15 28 | B1->B0 | 3636 4545 | 0 0 | (0 0) (0 0)
5797 18:06:54.618635 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5798 18:06:54.621624 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5799 18:06:54.628582 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5800 18:06:54.631491 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5801 18:06:54.635090 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5802 18:06:54.641842 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5803 18:06:54.645275 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5804 18:06:54.648470 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5805 18:06:54.655466 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5806 18:06:54.658652 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5807 18:06:54.662331 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5808 18:06:54.668537 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5809 18:06:54.671727 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5810 18:06:54.675367 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5811 18:06:54.678341 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5812 18:06:54.685468 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5813 18:06:54.688490 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5814 18:06:54.691890 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5815 18:06:54.698994 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5816 18:06:54.702179 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5817 18:06:54.705220 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5818 18:06:54.712146 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5819 18:06:54.715320 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5820 18:06:54.718542 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5821 18:06:54.721960 Total UI for P1: 0, mck2ui 16
5822 18:06:54.725046 best dqsien dly found for B0: ( 1, 2, 22)
5823 18:06:54.728457 Total UI for P1: 0, mck2ui 16
5824 18:06:54.731845 best dqsien dly found for B1: ( 1, 2, 24)
5825 18:06:54.735252 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5826 18:06:54.738698 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5827 18:06:54.739109
5828 18:06:54.745275 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5829 18:06:54.748876 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5830 18:06:54.749357 [Gating] SW calibration Done
5831 18:06:54.751950 ==
5832 18:06:54.752381 Dram Type= 6, Freq= 0, CH_1, rank 1
5833 18:06:54.758522 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5834 18:06:54.758933 ==
5835 18:06:54.759309 RX Vref Scan: 0
5836 18:06:54.759621
5837 18:06:54.762066 RX Vref 0 -> 0, step: 1
5838 18:06:54.762471
5839 18:06:54.765439 RX Delay -80 -> 252, step: 8
5840 18:06:54.768302 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5841 18:06:54.772184 iDelay=200, Bit 1, Center 87 (-8 ~ 183) 192
5842 18:06:54.775315 iDelay=200, Bit 2, Center 87 (-8 ~ 183) 192
5843 18:06:54.778656 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5844 18:06:54.785533 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5845 18:06:54.788622 iDelay=200, Bit 5, Center 103 (8 ~ 199) 192
5846 18:06:54.792356 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5847 18:06:54.795247 iDelay=200, Bit 7, Center 91 (0 ~ 183) 184
5848 18:06:54.798796 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5849 18:06:54.802342 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5850 18:06:54.808956 iDelay=200, Bit 10, Center 91 (-8 ~ 191) 200
5851 18:06:54.812286 iDelay=200, Bit 11, Center 79 (-16 ~ 175) 192
5852 18:06:54.815457 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5853 18:06:54.818587 iDelay=200, Bit 13, Center 99 (0 ~ 199) 200
5854 18:06:54.821914 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5855 18:06:54.825519 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5856 18:06:54.828963 ==
5857 18:06:54.832279 Dram Type= 6, Freq= 0, CH_1, rank 1
5858 18:06:54.835443 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5859 18:06:54.835852 ==
5860 18:06:54.836174 DQS Delay:
5861 18:06:54.838909 DQS0 = 0, DQS1 = 0
5862 18:06:54.839318 DQM Delay:
5863 18:06:54.842020 DQM0 = 94, DQM1 = 89
5864 18:06:54.842442 DQ Delay:
5865 18:06:54.845545 DQ0 =95, DQ1 =87, DQ2 =87, DQ3 =95
5866 18:06:54.848972 DQ4 =95, DQ5 =103, DQ6 =103, DQ7 =91
5867 18:06:54.852545 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =79
5868 18:06:54.855363 DQ12 =95, DQ13 =99, DQ14 =95, DQ15 =95
5869 18:06:54.855919
5870 18:06:54.856398
5871 18:06:54.856722 ==
5872 18:06:54.858609 Dram Type= 6, Freq= 0, CH_1, rank 1
5873 18:06:54.862248 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5874 18:06:54.862658 ==
5875 18:06:54.862979
5876 18:06:54.863274
5877 18:06:54.865566 TX Vref Scan disable
5878 18:06:54.868599 == TX Byte 0 ==
5879 18:06:54.872270 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5880 18:06:54.875734 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5881 18:06:54.878746 == TX Byte 1 ==
5882 18:06:54.882281 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5883 18:06:54.885625 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5884 18:06:54.886087 ==
5885 18:06:54.888792 Dram Type= 6, Freq= 0, CH_1, rank 1
5886 18:06:54.892355 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5887 18:06:54.895774 ==
5888 18:06:54.896194
5889 18:06:54.896520
5890 18:06:54.896820 TX Vref Scan disable
5891 18:06:54.898953 == TX Byte 0 ==
5892 18:06:54.902298 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5893 18:06:54.905756 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5894 18:06:54.909329 == TX Byte 1 ==
5895 18:06:54.912206 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5896 18:06:54.916072 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5897 18:06:54.918933
5898 18:06:54.919340 [DATLAT]
5899 18:06:54.919665 Freq=933, CH1 RK1
5900 18:06:54.919972
5901 18:06:54.922188 DATLAT Default: 0xb
5902 18:06:54.922615 0, 0xFFFF, sum = 0
5903 18:06:54.925511 1, 0xFFFF, sum = 0
5904 18:06:54.925964 2, 0xFFFF, sum = 0
5905 18:06:54.929027 3, 0xFFFF, sum = 0
5906 18:06:54.932337 4, 0xFFFF, sum = 0
5907 18:06:54.932753 5, 0xFFFF, sum = 0
5908 18:06:54.936070 6, 0xFFFF, sum = 0
5909 18:06:54.936584 7, 0xFFFF, sum = 0
5910 18:06:54.939079 8, 0xFFFF, sum = 0
5911 18:06:54.939615 9, 0xFFFF, sum = 0
5912 18:06:54.942353 10, 0x0, sum = 1
5913 18:06:54.942793 11, 0x0, sum = 2
5914 18:06:54.943129 12, 0x0, sum = 3
5915 18:06:54.945619 13, 0x0, sum = 4
5916 18:06:54.946175 best_step = 11
5917 18:06:54.946604
5918 18:06:54.949090 ==
5919 18:06:54.949523 Dram Type= 6, Freq= 0, CH_1, rank 1
5920 18:06:54.955483 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5921 18:06:54.955972 ==
5922 18:06:54.956304 RX Vref Scan: 0
5923 18:06:54.956610
5924 18:06:54.958298 RX Vref 0 -> 0, step: 1
5925 18:06:54.958706
5926 18:06:54.962357 RX Delay -61 -> 252, step: 4
5927 18:06:54.965384 iDelay=195, Bit 0, Center 96 (3 ~ 190) 188
5928 18:06:54.972125 iDelay=195, Bit 1, Center 90 (-1 ~ 182) 184
5929 18:06:54.975534 iDelay=195, Bit 2, Center 84 (-5 ~ 174) 180
5930 18:06:54.979014 iDelay=195, Bit 3, Center 94 (3 ~ 186) 184
5931 18:06:54.981740 iDelay=195, Bit 4, Center 96 (7 ~ 186) 180
5932 18:06:54.985348 iDelay=195, Bit 5, Center 104 (15 ~ 194) 180
5933 18:06:54.988458 iDelay=195, Bit 6, Center 102 (11 ~ 194) 184
5934 18:06:54.995217 iDelay=195, Bit 7, Center 90 (3 ~ 178) 176
5935 18:06:54.998442 iDelay=195, Bit 8, Center 80 (-13 ~ 174) 188
5936 18:06:55.002025 iDelay=195, Bit 9, Center 78 (-13 ~ 170) 184
5937 18:06:55.004961 iDelay=195, Bit 10, Center 94 (3 ~ 186) 184
5938 18:06:55.008446 iDelay=195, Bit 11, Center 82 (-9 ~ 174) 184
5939 18:06:55.011632 iDelay=195, Bit 12, Center 96 (7 ~ 186) 180
5940 18:06:55.018676 iDelay=195, Bit 13, Center 96 (3 ~ 190) 188
5941 18:06:55.022096 iDelay=195, Bit 14, Center 98 (7 ~ 190) 184
5942 18:06:55.025367 iDelay=195, Bit 15, Center 98 (7 ~ 190) 184
5943 18:06:55.025778 ==
5944 18:06:55.028679 Dram Type= 6, Freq= 0, CH_1, rank 1
5945 18:06:55.032061 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5946 18:06:55.032474 ==
5947 18:06:55.035439 DQS Delay:
5948 18:06:55.035852 DQS0 = 0, DQS1 = 0
5949 18:06:55.036182 DQM Delay:
5950 18:06:55.038823 DQM0 = 94, DQM1 = 90
5951 18:06:55.039232 DQ Delay:
5952 18:06:55.042176 DQ0 =96, DQ1 =90, DQ2 =84, DQ3 =94
5953 18:06:55.045245 DQ4 =96, DQ5 =104, DQ6 =102, DQ7 =90
5954 18:06:55.048616 DQ8 =80, DQ9 =78, DQ10 =94, DQ11 =82
5955 18:06:55.052039 DQ12 =96, DQ13 =96, DQ14 =98, DQ15 =98
5956 18:06:55.052482
5957 18:06:55.052816
5958 18:06:55.061939 [DQSOSCAuto] RK1, (LSB)MR18= 0x812, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 419 ps
5959 18:06:55.062355 CH1 RK1: MR19=505, MR18=812
5960 18:06:55.068357 CH1_RK1: MR19=0x505, MR18=0x812, DQSOSC=416, MR23=63, INC=62, DEC=41
5961 18:06:55.071879 [RxdqsGatingPostProcess] freq 933
5962 18:06:55.078646 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5963 18:06:55.082011 best DQS0 dly(2T, 0.5T) = (0, 10)
5964 18:06:55.085091 best DQS1 dly(2T, 0.5T) = (0, 10)
5965 18:06:55.088497 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5966 18:06:55.091862 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5967 18:06:55.095469 best DQS0 dly(2T, 0.5T) = (0, 10)
5968 18:06:55.095880 best DQS1 dly(2T, 0.5T) = (0, 10)
5969 18:06:55.098454 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5970 18:06:55.101899 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5971 18:06:55.105653 Pre-setting of DQS Precalculation
5972 18:06:55.112112 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5973 18:06:55.118691 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5974 18:06:55.125658 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5975 18:06:55.126071
5976 18:06:55.126395
5977 18:06:55.128785 [Calibration Summary] 1866 Mbps
5978 18:06:55.129227 CH 0, Rank 0
5979 18:06:55.132238 SW Impedance : PASS
5980 18:06:55.135390 DUTY Scan : NO K
5981 18:06:55.135803 ZQ Calibration : PASS
5982 18:06:55.138862 Jitter Meter : NO K
5983 18:06:55.142595 CBT Training : PASS
5984 18:06:55.143009 Write leveling : PASS
5985 18:06:55.145534 RX DQS gating : PASS
5986 18:06:55.149050 RX DQ/DQS(RDDQC) : PASS
5987 18:06:55.149461 TX DQ/DQS : PASS
5988 18:06:55.152029 RX DATLAT : PASS
5989 18:06:55.155549 RX DQ/DQS(Engine): PASS
5990 18:06:55.155956 TX OE : NO K
5991 18:06:55.156282 All Pass.
5992 18:06:55.159057
5993 18:06:55.159478 CH 0, Rank 1
5994 18:06:55.162237 SW Impedance : PASS
5995 18:06:55.162650 DUTY Scan : NO K
5996 18:06:55.165468 ZQ Calibration : PASS
5997 18:06:55.165880 Jitter Meter : NO K
5998 18:06:55.168924 CBT Training : PASS
5999 18:06:55.171960 Write leveling : PASS
6000 18:06:55.172417 RX DQS gating : PASS
6001 18:06:55.175527 RX DQ/DQS(RDDQC) : PASS
6002 18:06:55.179126 TX DQ/DQS : PASS
6003 18:06:55.179578 RX DATLAT : PASS
6004 18:06:55.182388 RX DQ/DQS(Engine): PASS
6005 18:06:55.185821 TX OE : NO K
6006 18:06:55.186234 All Pass.
6007 18:06:55.186561
6008 18:06:55.186862 CH 1, Rank 0
6009 18:06:55.188801 SW Impedance : PASS
6010 18:06:55.192375 DUTY Scan : NO K
6011 18:06:55.192784 ZQ Calibration : PASS
6012 18:06:55.195900 Jitter Meter : NO K
6013 18:06:55.199373 CBT Training : PASS
6014 18:06:55.199906 Write leveling : PASS
6015 18:06:55.202232 RX DQS gating : PASS
6016 18:06:55.202641 RX DQ/DQS(RDDQC) : PASS
6017 18:06:55.205753 TX DQ/DQS : PASS
6018 18:06:55.208796 RX DATLAT : PASS
6019 18:06:55.209353 RX DQ/DQS(Engine): PASS
6020 18:06:55.212511 TX OE : NO K
6021 18:06:55.212925 All Pass.
6022 18:06:55.213388
6023 18:06:55.215666 CH 1, Rank 1
6024 18:06:55.216109 SW Impedance : PASS
6025 18:06:55.219286 DUTY Scan : NO K
6026 18:06:55.222209 ZQ Calibration : PASS
6027 18:06:55.222622 Jitter Meter : NO K
6028 18:06:55.225770 CBT Training : PASS
6029 18:06:55.229424 Write leveling : PASS
6030 18:06:55.229919 RX DQS gating : PASS
6031 18:06:55.232400 RX DQ/DQS(RDDQC) : PASS
6032 18:06:55.235763 TX DQ/DQS : PASS
6033 18:06:55.236287 RX DATLAT : PASS
6034 18:06:55.238929 RX DQ/DQS(Engine): PASS
6035 18:06:55.242176 TX OE : NO K
6036 18:06:55.242593 All Pass.
6037 18:06:55.242919
6038 18:06:55.243325 DramC Write-DBI off
6039 18:06:55.245498 PER_BANK_REFRESH: Hybrid Mode
6040 18:06:55.248893 TX_TRACKING: ON
6041 18:06:55.255521 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6042 18:06:55.258984 [FAST_K] Save calibration result to emmc
6043 18:06:55.262590 dramc_set_vcore_voltage set vcore to 650000
6044 18:06:55.266156 Read voltage for 400, 6
6045 18:06:55.266567 Vio18 = 0
6046 18:06:55.268845 Vcore = 650000
6047 18:06:55.269422 Vdram = 0
6048 18:06:55.269805 Vddq = 0
6049 18:06:55.272447 Vmddr = 0
6050 18:06:55.275623 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6051 18:06:55.282219 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6052 18:06:55.282639 MEM_TYPE=3, freq_sel=20
6053 18:06:55.285760 sv_algorithm_assistance_LP4_800
6054 18:06:55.292295 ============ PULL DRAM RESETB DOWN ============
6055 18:06:55.296003 ========== PULL DRAM RESETB DOWN end =========
6056 18:06:55.299048 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6057 18:06:55.302544 ===================================
6058 18:06:55.305485 LPDDR4 DRAM CONFIGURATION
6059 18:06:55.308903 ===================================
6060 18:06:55.309161 EX_ROW_EN[0] = 0x0
6061 18:06:55.312074 EX_ROW_EN[1] = 0x0
6062 18:06:55.315887 LP4Y_EN = 0x0
6063 18:06:55.316074 WORK_FSP = 0x0
6064 18:06:55.319150 WL = 0x2
6065 18:06:55.319298 RL = 0x2
6066 18:06:55.322450 BL = 0x2
6067 18:06:55.322580 RPST = 0x0
6068 18:06:55.325802 RD_PRE = 0x0
6069 18:06:55.325981 WR_PRE = 0x1
6070 18:06:55.329235 WR_PST = 0x0
6071 18:06:55.329348 DBI_WR = 0x0
6072 18:06:55.332401 DBI_RD = 0x0
6073 18:06:55.332791 OTF = 0x1
6074 18:06:55.335967 ===================================
6075 18:06:55.339061 ===================================
6076 18:06:55.342664 ANA top config
6077 18:06:55.345534 ===================================
6078 18:06:55.345771 DLL_ASYNC_EN = 0
6079 18:06:55.348716 ALL_SLAVE_EN = 1
6080 18:06:55.352278 NEW_RANK_MODE = 1
6081 18:06:55.355732 DLL_IDLE_MODE = 1
6082 18:06:55.359211 LP45_APHY_COMB_EN = 1
6083 18:06:55.359475 TX_ODT_DIS = 1
6084 18:06:55.362407 NEW_8X_MODE = 1
6085 18:06:55.365918 ===================================
6086 18:06:55.368627 ===================================
6087 18:06:55.372368 data_rate = 800
6088 18:06:55.375664 CKR = 1
6089 18:06:55.379476 DQ_P2S_RATIO = 4
6090 18:06:55.382963 ===================================
6091 18:06:55.383393 CA_P2S_RATIO = 4
6092 18:06:55.385901 DQ_CA_OPEN = 0
6093 18:06:55.388774 DQ_SEMI_OPEN = 1
6094 18:06:55.392414 CA_SEMI_OPEN = 1
6095 18:06:55.395609 CA_FULL_RATE = 0
6096 18:06:55.399415 DQ_CKDIV4_EN = 0
6097 18:06:55.400072 CA_CKDIV4_EN = 1
6098 18:06:55.402233 CA_PREDIV_EN = 0
6099 18:06:55.405710 PH8_DLY = 0
6100 18:06:55.409382 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6101 18:06:55.412270 DQ_AAMCK_DIV = 0
6102 18:06:55.415929 CA_AAMCK_DIV = 0
6103 18:06:55.416439 CA_ADMCK_DIV = 4
6104 18:06:55.419110 DQ_TRACK_CA_EN = 0
6105 18:06:55.422452 CA_PICK = 800
6106 18:06:55.425470 CA_MCKIO = 400
6107 18:06:55.428694 MCKIO_SEMI = 400
6108 18:06:55.432394 PLL_FREQ = 3016
6109 18:06:55.435333 DQ_UI_PI_RATIO = 32
6110 18:06:55.435745 CA_UI_PI_RATIO = 32
6111 18:06:55.439026 ===================================
6112 18:06:55.442395 ===================================
6113 18:06:55.445734 memory_type:LPDDR4
6114 18:06:55.448806 GP_NUM : 10
6115 18:06:55.449239 SRAM_EN : 1
6116 18:06:55.452277 MD32_EN : 0
6117 18:06:55.455686 ===================================
6118 18:06:55.459081 [ANA_INIT] >>>>>>>>>>>>>>
6119 18:06:55.462111 <<<<<< [CONFIGURE PHASE]: ANA_TX
6120 18:06:55.465306 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6121 18:06:55.468820 ===================================
6122 18:06:55.469308 data_rate = 800,PCW = 0X7400
6123 18:06:55.472343 ===================================
6124 18:06:55.475239 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6125 18:06:55.482070 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6126 18:06:55.492479 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6127 18:06:55.498710 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6128 18:06:55.502426 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6129 18:06:55.505237 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6130 18:06:55.508802 [ANA_INIT] flow start
6131 18:06:55.509238 [ANA_INIT] PLL >>>>>>>>
6132 18:06:55.512284 [ANA_INIT] PLL <<<<<<<<
6133 18:06:55.515633 [ANA_INIT] MIDPI >>>>>>>>
6134 18:06:55.516143 [ANA_INIT] MIDPI <<<<<<<<
6135 18:06:55.519078 [ANA_INIT] DLL >>>>>>>>
6136 18:06:55.522669 [ANA_INIT] flow end
6137 18:06:55.525537 ============ LP4 DIFF to SE enter ============
6138 18:06:55.529011 ============ LP4 DIFF to SE exit ============
6139 18:06:55.532118 [ANA_INIT] <<<<<<<<<<<<<
6140 18:06:55.535467 [Flow] Enable top DCM control >>>>>
6141 18:06:55.539284 [Flow] Enable top DCM control <<<<<
6142 18:06:55.541958 Enable DLL master slave shuffle
6143 18:06:55.545558 ==============================================================
6144 18:06:55.548733 Gating Mode config
6145 18:06:55.552157 ==============================================================
6146 18:06:55.555631 Config description:
6147 18:06:55.565741 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6148 18:06:55.572272 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6149 18:06:55.575909 SELPH_MODE 0: By rank 1: By Phase
6150 18:06:55.582440 ==============================================================
6151 18:06:55.585480 GAT_TRACK_EN = 0
6152 18:06:55.589122 RX_GATING_MODE = 2
6153 18:06:55.592501 RX_GATING_TRACK_MODE = 2
6154 18:06:55.595751 SELPH_MODE = 1
6155 18:06:55.596309 PICG_EARLY_EN = 1
6156 18:06:55.598650 VALID_LAT_VALUE = 1
6157 18:06:55.605770 ==============================================================
6158 18:06:55.608733 Enter into Gating configuration >>>>
6159 18:06:55.612134 Exit from Gating configuration <<<<
6160 18:06:55.615492 Enter into DVFS_PRE_config >>>>>
6161 18:06:55.625770 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6162 18:06:55.628719 Exit from DVFS_PRE_config <<<<<
6163 18:06:55.632097 Enter into PICG configuration >>>>
6164 18:06:55.635089 Exit from PICG configuration <<<<
6165 18:06:55.638898 [RX_INPUT] configuration >>>>>
6166 18:06:55.641979 [RX_INPUT] configuration <<<<<
6167 18:06:55.645589 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6168 18:06:55.651930 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6169 18:06:55.658674 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6170 18:06:55.665395 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6171 18:06:55.672175 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6172 18:06:55.675363 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6173 18:06:55.682418 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6174 18:06:55.685515 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6175 18:06:55.688887 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6176 18:06:55.692214 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6177 18:06:55.695576 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6178 18:06:55.702104 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6179 18:06:55.705896 ===================================
6180 18:06:55.709302 LPDDR4 DRAM CONFIGURATION
6181 18:06:55.709852 ===================================
6182 18:06:55.712135 EX_ROW_EN[0] = 0x0
6183 18:06:55.715683 EX_ROW_EN[1] = 0x0
6184 18:06:55.716264 LP4Y_EN = 0x0
6185 18:06:55.718927 WORK_FSP = 0x0
6186 18:06:55.719474 WL = 0x2
6187 18:06:55.722155 RL = 0x2
6188 18:06:55.722587 BL = 0x2
6189 18:06:55.725627 RPST = 0x0
6190 18:06:55.726176 RD_PRE = 0x0
6191 18:06:55.728747 WR_PRE = 0x1
6192 18:06:55.729309 WR_PST = 0x0
6193 18:06:55.732281 DBI_WR = 0x0
6194 18:06:55.732796 DBI_RD = 0x0
6195 18:06:55.735891 OTF = 0x1
6196 18:06:55.739036 ===================================
6197 18:06:55.742441 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6198 18:06:55.746049 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6199 18:06:55.752730 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6200 18:06:55.755736 ===================================
6201 18:06:55.756285 LPDDR4 DRAM CONFIGURATION
6202 18:06:55.759517 ===================================
6203 18:06:55.762514 EX_ROW_EN[0] = 0x10
6204 18:06:55.765914 EX_ROW_EN[1] = 0x0
6205 18:06:55.766330 LP4Y_EN = 0x0
6206 18:06:55.769045 WORK_FSP = 0x0
6207 18:06:55.769671 WL = 0x2
6208 18:06:55.772579 RL = 0x2
6209 18:06:55.773169 BL = 0x2
6210 18:06:55.775532 RPST = 0x0
6211 18:06:55.776084 RD_PRE = 0x0
6212 18:06:55.778842 WR_PRE = 0x1
6213 18:06:55.779257 WR_PST = 0x0
6214 18:06:55.782476 DBI_WR = 0x0
6215 18:06:55.782890 DBI_RD = 0x0
6216 18:06:55.786004 OTF = 0x1
6217 18:06:55.788791 ===================================
6218 18:06:55.795602 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6219 18:06:55.799254 nWR fixed to 30
6220 18:06:55.799678 [ModeRegInit_LP4] CH0 RK0
6221 18:06:55.802322 [ModeRegInit_LP4] CH0 RK1
6222 18:06:55.806434 [ModeRegInit_LP4] CH1 RK0
6223 18:06:55.806872 [ModeRegInit_LP4] CH1 RK1
6224 18:06:55.809032 match AC timing 19
6225 18:06:55.811969 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6226 18:06:55.818791 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6227 18:06:55.822417 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6228 18:06:55.825550 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6229 18:06:55.832469 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6230 18:06:55.833035 ==
6231 18:06:55.835891 Dram Type= 6, Freq= 0, CH_0, rank 0
6232 18:06:55.838901 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6233 18:06:55.839322 ==
6234 18:06:55.845470 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6235 18:06:55.848936 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6236 18:06:55.852086 [CA 0] Center 36 (8~64) winsize 57
6237 18:06:55.855715 [CA 1] Center 36 (8~64) winsize 57
6238 18:06:55.858802 [CA 2] Center 36 (8~64) winsize 57
6239 18:06:55.862258 [CA 3] Center 36 (8~64) winsize 57
6240 18:06:55.865386 [CA 4] Center 36 (8~64) winsize 57
6241 18:06:55.868857 [CA 5] Center 36 (8~64) winsize 57
6242 18:06:55.869343
6243 18:06:55.871929 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6244 18:06:55.872504
6245 18:06:55.875484 [CATrainingPosCal] consider 1 rank data
6246 18:06:55.879038 u2DelayCellTimex100 = 270/100 ps
6247 18:06:55.881807 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6248 18:06:55.885442 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6249 18:06:55.892383 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6250 18:06:55.895270 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6251 18:06:55.898947 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6252 18:06:55.902020 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6253 18:06:55.902443
6254 18:06:55.905559 CA PerBit enable=1, Macro0, CA PI delay=36
6255 18:06:55.905976
6256 18:06:55.908554 [CBTSetCACLKResult] CA Dly = 36
6257 18:06:55.909082 CS Dly: 1 (0~32)
6258 18:06:55.909463 ==
6259 18:06:55.912286 Dram Type= 6, Freq= 0, CH_0, rank 1
6260 18:06:55.918850 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6261 18:06:55.919269 ==
6262 18:06:55.922065 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6263 18:06:55.928947 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6264 18:06:55.932324 [CA 0] Center 36 (8~64) winsize 57
6265 18:06:55.935701 [CA 1] Center 36 (8~64) winsize 57
6266 18:06:55.938621 [CA 2] Center 36 (8~64) winsize 57
6267 18:06:55.941907 [CA 3] Center 36 (8~64) winsize 57
6268 18:06:55.945305 [CA 4] Center 36 (8~64) winsize 57
6269 18:06:55.948524 [CA 5] Center 36 (8~64) winsize 57
6270 18:06:55.949095
6271 18:06:55.951849 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6272 18:06:55.952343
6273 18:06:55.955263 [CATrainingPosCal] consider 2 rank data
6274 18:06:55.958890 u2DelayCellTimex100 = 270/100 ps
6275 18:06:55.962108 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6276 18:06:55.965710 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6277 18:06:55.968684 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6278 18:06:55.972304 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6279 18:06:55.975260 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6280 18:06:55.978903 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6281 18:06:55.979331
6282 18:06:55.985393 CA PerBit enable=1, Macro0, CA PI delay=36
6283 18:06:55.985920
6284 18:06:55.986377 [CBTSetCACLKResult] CA Dly = 36
6285 18:06:55.989034 CS Dly: 1 (0~32)
6286 18:06:55.989487
6287 18:06:55.992005 ----->DramcWriteLeveling(PI) begin...
6288 18:06:55.992433 ==
6289 18:06:55.995535 Dram Type= 6, Freq= 0, CH_0, rank 0
6290 18:06:55.998576 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6291 18:06:55.999005 ==
6292 18:06:56.002176 Write leveling (Byte 0): 40 => 8
6293 18:06:56.005844 Write leveling (Byte 1): 32 => 0
6294 18:06:56.008716 DramcWriteLeveling(PI) end<-----
6295 18:06:56.009172
6296 18:06:56.009618 ==
6297 18:06:56.012299 Dram Type= 6, Freq= 0, CH_0, rank 0
6298 18:06:56.015410 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6299 18:06:56.015878 ==
6300 18:06:56.018919 [Gating] SW mode calibration
6301 18:06:56.025428 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6302 18:06:56.031522 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6303 18:06:56.035330 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6304 18:06:56.041737 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6305 18:06:56.044763 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6306 18:06:56.048434 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6307 18:06:56.054886 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6308 18:06:56.058359 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6309 18:06:56.061819 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6310 18:06:56.068590 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6311 18:06:56.071964 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6312 18:06:56.075051 Total UI for P1: 0, mck2ui 16
6313 18:06:56.078282 best dqsien dly found for B0: ( 0, 14, 24)
6314 18:06:56.081669 Total UI for P1: 0, mck2ui 16
6315 18:06:56.084812 best dqsien dly found for B1: ( 0, 14, 24)
6316 18:06:56.088533 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6317 18:06:56.091648 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6318 18:06:56.091851
6319 18:06:56.095319 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6320 18:06:56.098302 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6321 18:06:56.101804 [Gating] SW calibration Done
6322 18:06:56.101982 ==
6323 18:06:56.104795 Dram Type= 6, Freq= 0, CH_0, rank 0
6324 18:06:56.108454 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6325 18:06:56.108633 ==
6326 18:06:56.111488 RX Vref Scan: 0
6327 18:06:56.111681
6328 18:06:56.115039 RX Vref 0 -> 0, step: 1
6329 18:06:56.115219
6330 18:06:56.115362 RX Delay -410 -> 252, step: 16
6331 18:06:56.121594 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6332 18:06:56.125117 iDelay=230, Bit 1, Center -27 (-282 ~ 229) 512
6333 18:06:56.128303 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6334 18:06:56.131833 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6335 18:06:56.138616 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6336 18:06:56.141668 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6337 18:06:56.145265 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6338 18:06:56.148261 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6339 18:06:56.154967 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6340 18:06:56.158434 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6341 18:06:56.161954 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6342 18:06:56.164977 iDelay=230, Bit 11, Center -43 (-282 ~ 197) 480
6343 18:06:56.171630 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6344 18:06:56.175235 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6345 18:06:56.178430 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6346 18:06:56.181532 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6347 18:06:56.184938 ==
6348 18:06:56.188466 Dram Type= 6, Freq= 0, CH_0, rank 0
6349 18:06:56.191871 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6350 18:06:56.191980 ==
6351 18:06:56.192064 DQS Delay:
6352 18:06:56.194930 DQS0 = 35, DQS1 = 51
6353 18:06:56.195038 DQM Delay:
6354 18:06:56.198882 DQM0 = 7, DQM1 = 11
6355 18:06:56.199010 DQ Delay:
6356 18:06:56.201639 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =0
6357 18:06:56.205277 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6358 18:06:56.208620 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6359 18:06:56.211774 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6360 18:06:56.211940
6361 18:06:56.212071
6362 18:06:56.212192 ==
6363 18:06:56.215502 Dram Type= 6, Freq= 0, CH_0, rank 0
6364 18:06:56.218716 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6365 18:06:56.218920 ==
6366 18:06:56.219154
6367 18:06:56.219376
6368 18:06:56.221815 TX Vref Scan disable
6369 18:06:56.222040 == TX Byte 0 ==
6370 18:06:56.225299 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6371 18:06:56.232049 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6372 18:06:56.232497 == TX Byte 1 ==
6373 18:06:56.234975 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6374 18:06:56.242096 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6375 18:06:56.242526 ==
6376 18:06:56.245484 Dram Type= 6, Freq= 0, CH_0, rank 0
6377 18:06:56.248393 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6378 18:06:56.248917 ==
6379 18:06:56.249354
6380 18:06:56.249712
6381 18:06:56.252122 TX Vref Scan disable
6382 18:06:56.252585 == TX Byte 0 ==
6383 18:06:56.258784 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6384 18:06:56.262295 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6385 18:06:56.262709 == TX Byte 1 ==
6386 18:06:56.268783 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6387 18:06:56.272336 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6388 18:06:56.272786
6389 18:06:56.273262 [DATLAT]
6390 18:06:56.275432 Freq=400, CH0 RK0
6391 18:06:56.275867
6392 18:06:56.276304 DATLAT Default: 0xf
6393 18:06:56.278955 0, 0xFFFF, sum = 0
6394 18:06:56.279443 1, 0xFFFF, sum = 0
6395 18:06:56.282592 2, 0xFFFF, sum = 0
6396 18:06:56.283029 3, 0xFFFF, sum = 0
6397 18:06:56.285962 4, 0xFFFF, sum = 0
6398 18:06:56.286394 5, 0xFFFF, sum = 0
6399 18:06:56.289028 6, 0xFFFF, sum = 0
6400 18:06:56.289469 7, 0xFFFF, sum = 0
6401 18:06:56.292042 8, 0xFFFF, sum = 0
6402 18:06:56.292588 9, 0xFFFF, sum = 0
6403 18:06:56.295141 10, 0xFFFF, sum = 0
6404 18:06:56.295536 11, 0xFFFF, sum = 0
6405 18:06:56.298659 12, 0xFFFF, sum = 0
6406 18:06:56.299128 13, 0x0, sum = 1
6407 18:06:56.302018 14, 0x0, sum = 2
6408 18:06:56.302531 15, 0x0, sum = 3
6409 18:06:56.305717 16, 0x0, sum = 4
6410 18:06:56.306187 best_step = 14
6411 18:06:56.306546
6412 18:06:56.306904 ==
6413 18:06:56.308621 Dram Type= 6, Freq= 0, CH_0, rank 0
6414 18:06:56.315420 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6415 18:06:56.315910 ==
6416 18:06:56.316306 RX Vref Scan: 1
6417 18:06:56.316631
6418 18:06:56.318522 RX Vref 0 -> 0, step: 1
6419 18:06:56.318942
6420 18:06:56.321633 RX Delay -343 -> 252, step: 8
6421 18:06:56.321932
6422 18:06:56.325417 Set Vref, RX VrefLevel [Byte0]: 51
6423 18:06:56.328787 [Byte1]: 51
6424 18:06:56.329099
6425 18:06:56.331819 Final RX Vref Byte 0 = 51 to rank0
6426 18:06:56.335535 Final RX Vref Byte 1 = 51 to rank0
6427 18:06:56.338768 Final RX Vref Byte 0 = 51 to rank1
6428 18:06:56.341841 Final RX Vref Byte 1 = 51 to rank1==
6429 18:06:56.345431 Dram Type= 6, Freq= 0, CH_0, rank 0
6430 18:06:56.348276 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6431 18:06:56.351764 ==
6432 18:06:56.352127 DQS Delay:
6433 18:06:56.352365 DQS0 = 44, DQS1 = 60
6434 18:06:56.355180 DQM Delay:
6435 18:06:56.355472 DQM0 = 10, DQM1 = 15
6436 18:06:56.358788 DQ Delay:
6437 18:06:56.359142 DQ0 =12, DQ1 =12, DQ2 =4, DQ3 =8
6438 18:06:56.362302 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =16
6439 18:06:56.365315 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6440 18:06:56.368846 DQ12 =20, DQ13 =20, DQ14 =28, DQ15 =28
6441 18:06:56.369218
6442 18:06:56.369494
6443 18:06:56.379081 [DQSOSCAuto] RK0, (LSB)MR18= 0x8656, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 393 ps
6444 18:06:56.381999 CH0 RK0: MR19=C0C, MR18=8656
6445 18:06:56.385614 CH0_RK0: MR19=0xC0C, MR18=0x8656, DQSOSC=393, MR23=63, INC=382, DEC=254
6446 18:06:56.388918 ==
6447 18:06:56.392269 Dram Type= 6, Freq= 0, CH_0, rank 1
6448 18:06:56.395458 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6449 18:06:56.395755 ==
6450 18:06:56.398453 [Gating] SW mode calibration
6451 18:06:56.405247 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6452 18:06:56.408890 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6453 18:06:56.415690 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6454 18:06:56.418579 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6455 18:06:56.422128 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6456 18:06:56.428607 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6457 18:06:56.432314 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6458 18:06:56.435219 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6459 18:06:56.441989 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6460 18:06:56.445555 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6461 18:06:56.448599 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6462 18:06:56.452301 Total UI for P1: 0, mck2ui 16
6463 18:06:56.455734 best dqsien dly found for B0: ( 0, 14, 24)
6464 18:06:56.458609 Total UI for P1: 0, mck2ui 16
6465 18:06:56.462140 best dqsien dly found for B1: ( 0, 14, 24)
6466 18:06:56.465555 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6467 18:06:56.468900 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6468 18:06:56.469223
6469 18:06:56.472193 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6470 18:06:56.478742 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6471 18:06:56.479039 [Gating] SW calibration Done
6472 18:06:56.479275 ==
6473 18:06:56.482242 Dram Type= 6, Freq= 0, CH_0, rank 1
6474 18:06:56.488812 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6475 18:06:56.489183 ==
6476 18:06:56.489487 RX Vref Scan: 0
6477 18:06:56.489714
6478 18:06:56.491970 RX Vref 0 -> 0, step: 1
6479 18:06:56.492265
6480 18:06:56.495334 RX Delay -410 -> 252, step: 16
6481 18:06:56.498752 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6482 18:06:56.501934 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6483 18:06:56.508739 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6484 18:06:56.512421 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6485 18:06:56.515279 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6486 18:06:56.518955 iDelay=230, Bit 5, Center -43 (-282 ~ 197) 480
6487 18:06:56.525563 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6488 18:06:56.528920 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6489 18:06:56.532017 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6490 18:06:56.535524 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6491 18:06:56.542106 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6492 18:06:56.545598 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6493 18:06:56.548777 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6494 18:06:56.552345 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6495 18:06:56.558713 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6496 18:06:56.562076 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6497 18:06:56.562392 ==
6498 18:06:56.565678 Dram Type= 6, Freq= 0, CH_0, rank 1
6499 18:06:56.568787 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6500 18:06:56.569179 ==
6501 18:06:56.572080 DQS Delay:
6502 18:06:56.572395 DQS0 = 43, DQS1 = 51
6503 18:06:56.572679 DQM Delay:
6504 18:06:56.575535 DQM0 = 11, DQM1 = 10
6505 18:06:56.575833 DQ Delay:
6506 18:06:56.578966 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6507 18:06:56.581961 DQ4 =8, DQ5 =0, DQ6 =24, DQ7 =24
6508 18:06:56.585185 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6509 18:06:56.588763 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6510 18:06:56.589165
6511 18:06:56.589463
6512 18:06:56.589696 ==
6513 18:06:56.591917 Dram Type= 6, Freq= 0, CH_0, rank 1
6514 18:06:56.595280 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6515 18:06:56.595588 ==
6516 18:06:56.598346
6517 18:06:56.598640
6518 18:06:56.598978 TX Vref Scan disable
6519 18:06:56.601859 == TX Byte 0 ==
6520 18:06:56.605154 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6521 18:06:56.608315 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6522 18:06:56.612050 == TX Byte 1 ==
6523 18:06:56.615481 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6524 18:06:56.618513 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6525 18:06:56.618936 ==
6526 18:06:56.622207 Dram Type= 6, Freq= 0, CH_0, rank 1
6527 18:06:56.625211 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6528 18:06:56.628289 ==
6529 18:06:56.628583
6530 18:06:56.628932
6531 18:06:56.629277 TX Vref Scan disable
6532 18:06:56.631783 == TX Byte 0 ==
6533 18:06:56.635340 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6534 18:06:56.638273 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6535 18:06:56.641784 == TX Byte 1 ==
6536 18:06:56.645342 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6537 18:06:56.648858 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6538 18:06:56.649213
6539 18:06:56.649477 [DATLAT]
6540 18:06:56.651695 Freq=400, CH0 RK1
6541 18:06:56.651986
6542 18:06:56.655370 DATLAT Default: 0xe
6543 18:06:56.655661 0, 0xFFFF, sum = 0
6544 18:06:56.658911 1, 0xFFFF, sum = 0
6545 18:06:56.659265 2, 0xFFFF, sum = 0
6546 18:06:56.661921 3, 0xFFFF, sum = 0
6547 18:06:56.662322 4, 0xFFFF, sum = 0
6548 18:06:56.665278 5, 0xFFFF, sum = 0
6549 18:06:56.665584 6, 0xFFFF, sum = 0
6550 18:06:56.668630 7, 0xFFFF, sum = 0
6551 18:06:56.669114 8, 0xFFFF, sum = 0
6552 18:06:56.672277 9, 0xFFFF, sum = 0
6553 18:06:56.672594 10, 0xFFFF, sum = 0
6554 18:06:56.675311 11, 0xFFFF, sum = 0
6555 18:06:56.675606 12, 0xFFFF, sum = 0
6556 18:06:56.678887 13, 0x0, sum = 1
6557 18:06:56.679180 14, 0x0, sum = 2
6558 18:06:56.681876 15, 0x0, sum = 3
6559 18:06:56.682171 16, 0x0, sum = 4
6560 18:06:56.685573 best_step = 14
6561 18:06:56.685862
6562 18:06:56.686090 ==
6563 18:06:56.688344 Dram Type= 6, Freq= 0, CH_0, rank 1
6564 18:06:56.691708 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6565 18:06:56.692067 ==
6566 18:06:56.692305 RX Vref Scan: 0
6567 18:06:56.695172
6568 18:06:56.695461 RX Vref 0 -> 0, step: 1
6569 18:06:56.695696
6570 18:06:56.698382 RX Delay -343 -> 252, step: 8
6571 18:06:56.705890 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6572 18:06:56.709052 iDelay=217, Bit 1, Center -32 (-271 ~ 208) 480
6573 18:06:56.712470 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6574 18:06:56.715906 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6575 18:06:56.722684 iDelay=217, Bit 4, Center -36 (-271 ~ 200) 472
6576 18:06:56.726291 iDelay=217, Bit 5, Center -48 (-287 ~ 192) 480
6577 18:06:56.729326 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6578 18:06:56.732890 iDelay=217, Bit 7, Center -32 (-271 ~ 208) 480
6579 18:06:56.739326 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6580 18:06:56.743018 iDelay=217, Bit 9, Center -56 (-295 ~ 184) 480
6581 18:06:56.745946 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6582 18:06:56.749239 iDelay=217, Bit 11, Center -56 (-295 ~ 184) 480
6583 18:06:56.755911 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6584 18:06:56.759413 iDelay=217, Bit 13, Center -40 (-279 ~ 200) 480
6585 18:06:56.762653 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6586 18:06:56.766212 iDelay=217, Bit 15, Center -40 (-279 ~ 200) 480
6587 18:06:56.769254 ==
6588 18:06:56.772828 Dram Type= 6, Freq= 0, CH_0, rank 1
6589 18:06:56.776029 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6590 18:06:56.776322 ==
6591 18:06:56.776554 DQS Delay:
6592 18:06:56.779324 DQS0 = 48, DQS1 = 60
6593 18:06:56.779623 DQM Delay:
6594 18:06:56.782456 DQM0 = 12, DQM1 = 13
6595 18:06:56.782752 DQ Delay:
6596 18:06:56.786283 DQ0 =12, DQ1 =16, DQ2 =8, DQ3 =12
6597 18:06:56.789309 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6598 18:06:56.792850 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =4
6599 18:06:56.796358 DQ12 =16, DQ13 =20, DQ14 =24, DQ15 =20
6600 18:06:56.796657
6601 18:06:56.796892
6602 18:06:56.802939 [DQSOSCAuto] RK1, (LSB)MR18= 0x8c5e, (MSB)MR19= 0xc0c, tDQSOscB0 = 397 ps tDQSOscB1 = 392 ps
6603 18:06:56.805969 CH0 RK1: MR19=C0C, MR18=8C5E
6604 18:06:56.812799 CH0_RK1: MR19=0xC0C, MR18=0x8C5E, DQSOSC=392, MR23=63, INC=384, DEC=256
6605 18:06:56.816512 [RxdqsGatingPostProcess] freq 400
6606 18:06:56.819263 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6607 18:06:56.822900 best DQS0 dly(2T, 0.5T) = (0, 10)
6608 18:06:56.826510 best DQS1 dly(2T, 0.5T) = (0, 10)
6609 18:06:56.829910 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6610 18:06:56.832847 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6611 18:06:56.836377 best DQS0 dly(2T, 0.5T) = (0, 10)
6612 18:06:56.839519 best DQS1 dly(2T, 0.5T) = (0, 10)
6613 18:06:56.842885 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6614 18:06:56.846657 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6615 18:06:56.849493 Pre-setting of DQS Precalculation
6616 18:06:56.853065 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6617 18:06:56.853441 ==
6618 18:06:56.856612 Dram Type= 6, Freq= 0, CH_1, rank 0
6619 18:06:56.862947 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6620 18:06:56.863338 ==
6621 18:06:56.866139 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6622 18:06:56.873008 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6623 18:06:56.876568 [CA 0] Center 36 (8~64) winsize 57
6624 18:06:56.879523 [CA 1] Center 36 (8~64) winsize 57
6625 18:06:56.882819 [CA 2] Center 36 (8~64) winsize 57
6626 18:06:56.886088 [CA 3] Center 36 (8~64) winsize 57
6627 18:06:56.889675 [CA 4] Center 36 (8~64) winsize 57
6628 18:06:56.893333 [CA 5] Center 36 (8~64) winsize 57
6629 18:06:56.893631
6630 18:06:56.896362 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6631 18:06:56.896658
6632 18:06:56.899878 [CATrainingPosCal] consider 1 rank data
6633 18:06:56.903122 u2DelayCellTimex100 = 270/100 ps
6634 18:06:56.906129 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6635 18:06:56.909623 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6636 18:06:56.913240 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6637 18:06:56.916167 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6638 18:06:56.919745 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6639 18:06:56.923296 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6640 18:06:56.923703
6641 18:06:56.926307 CA PerBit enable=1, Macro0, CA PI delay=36
6642 18:06:56.929956
6643 18:06:56.930360 [CBTSetCACLKResult] CA Dly = 36
6644 18:06:56.933080 CS Dly: 1 (0~32)
6645 18:06:56.933375 ==
6646 18:06:56.936347 Dram Type= 6, Freq= 0, CH_1, rank 1
6647 18:06:56.940025 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6648 18:06:56.940447 ==
6649 18:06:56.946683 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6650 18:06:56.953166 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6651 18:06:56.956587 [CA 0] Center 36 (8~64) winsize 57
6652 18:06:56.959538 [CA 1] Center 36 (8~64) winsize 57
6653 18:06:56.959826 [CA 2] Center 36 (8~64) winsize 57
6654 18:06:56.963276 [CA 3] Center 36 (8~64) winsize 57
6655 18:06:56.966228 [CA 4] Center 36 (8~64) winsize 57
6656 18:06:56.969747 [CA 5] Center 36 (8~64) winsize 57
6657 18:06:56.970159
6658 18:06:56.973194 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6659 18:06:56.973603
6660 18:06:56.976438 [CATrainingPosCal] consider 2 rank data
6661 18:06:56.980138 u2DelayCellTimex100 = 270/100 ps
6662 18:06:56.983699 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6663 18:06:56.989987 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6664 18:06:56.993235 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6665 18:06:56.996738 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6666 18:06:56.999815 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6667 18:06:57.003790 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6668 18:06:57.004160
6669 18:06:57.006192 CA PerBit enable=1, Macro0, CA PI delay=36
6670 18:06:57.006486
6671 18:06:57.009706 [CBTSetCACLKResult] CA Dly = 36
6672 18:06:57.010097 CS Dly: 1 (0~32)
6673 18:06:57.013361
6674 18:06:57.016804 ----->DramcWriteLeveling(PI) begin...
6675 18:06:57.017130 ==
6676 18:06:57.019638 Dram Type= 6, Freq= 0, CH_1, rank 0
6677 18:06:57.023353 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6678 18:06:57.023647 ==
6679 18:06:57.026281 Write leveling (Byte 0): 40 => 8
6680 18:06:57.029902 Write leveling (Byte 1): 40 => 8
6681 18:06:57.032900 DramcWriteLeveling(PI) end<-----
6682 18:06:57.033272
6683 18:06:57.033514 ==
6684 18:06:57.036580 Dram Type= 6, Freq= 0, CH_1, rank 0
6685 18:06:57.039667 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6686 18:06:57.039959 ==
6687 18:06:57.043261 [Gating] SW mode calibration
6688 18:06:57.050185 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6689 18:06:57.056079 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6690 18:06:57.059853 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6691 18:06:57.063156 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6692 18:06:57.066355 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6693 18:06:57.073120 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6694 18:06:57.075988 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6695 18:06:57.079881 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6696 18:06:57.086182 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6697 18:06:57.089735 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6698 18:06:57.092871 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6699 18:06:57.096371 Total UI for P1: 0, mck2ui 16
6700 18:06:57.099730 best dqsien dly found for B0: ( 0, 14, 24)
6701 18:06:57.102973 Total UI for P1: 0, mck2ui 16
6702 18:06:57.105952 best dqsien dly found for B1: ( 0, 14, 24)
6703 18:06:57.109266 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6704 18:06:57.116293 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6705 18:06:57.116656
6706 18:06:57.119306 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6707 18:06:57.122659 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6708 18:06:57.126161 [Gating] SW calibration Done
6709 18:06:57.126494 ==
6710 18:06:57.129621 Dram Type= 6, Freq= 0, CH_1, rank 0
6711 18:06:57.132739 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6712 18:06:57.133153 ==
6713 18:06:57.133521 RX Vref Scan: 0
6714 18:06:57.135826
6715 18:06:57.136139 RX Vref 0 -> 0, step: 1
6716 18:06:57.136469
6717 18:06:57.139504 RX Delay -410 -> 252, step: 16
6718 18:06:57.143031 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6719 18:06:57.149334 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6720 18:06:57.153010 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6721 18:06:57.156078 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6722 18:06:57.159624 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6723 18:06:57.166087 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6724 18:06:57.169211 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6725 18:06:57.172730 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6726 18:06:57.175967 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6727 18:06:57.183112 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6728 18:06:57.185703 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6729 18:06:57.189035 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6730 18:06:57.192711 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6731 18:06:57.199260 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6732 18:06:57.202487 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6733 18:06:57.206026 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6734 18:06:57.206434 ==
6735 18:06:57.209452 Dram Type= 6, Freq= 0, CH_1, rank 0
6736 18:06:57.212777 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6737 18:06:57.216242 ==
6738 18:06:57.216577 DQS Delay:
6739 18:06:57.216873 DQS0 = 51, DQS1 = 59
6740 18:06:57.219145 DQM Delay:
6741 18:06:57.219523 DQM0 = 19, DQM1 = 16
6742 18:06:57.222622 DQ Delay:
6743 18:06:57.226163 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6744 18:06:57.226528 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6745 18:06:57.229735 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6746 18:06:57.232777 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6747 18:06:57.233200
6748 18:06:57.233443
6749 18:06:57.235977 ==
6750 18:06:57.239476 Dram Type= 6, Freq= 0, CH_1, rank 0
6751 18:06:57.242608 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6752 18:06:57.243011 ==
6753 18:06:57.243256
6754 18:06:57.243471
6755 18:06:57.246081 TX Vref Scan disable
6756 18:06:57.246494 == TX Byte 0 ==
6757 18:06:57.249206 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6758 18:06:57.255801 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6759 18:06:57.256203 == TX Byte 1 ==
6760 18:06:57.259495 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6761 18:06:57.266086 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6762 18:06:57.266386 ==
6763 18:06:57.269359 Dram Type= 6, Freq= 0, CH_1, rank 0
6764 18:06:57.272693 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6765 18:06:57.272916 ==
6766 18:06:57.273119
6767 18:06:57.273286
6768 18:06:57.276216 TX Vref Scan disable
6769 18:06:57.276402 == TX Byte 0 ==
6770 18:06:57.279343 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6771 18:06:57.285701 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6772 18:06:57.285857 == TX Byte 1 ==
6773 18:06:57.289279 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6774 18:06:57.295738 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6775 18:06:57.295854
6776 18:06:57.295944 [DATLAT]
6777 18:06:57.296026 Freq=400, CH1 RK0
6778 18:06:57.296113
6779 18:06:57.298909 DATLAT Default: 0xf
6780 18:06:57.299009 0, 0xFFFF, sum = 0
6781 18:06:57.302486 1, 0xFFFF, sum = 0
6782 18:06:57.305957 2, 0xFFFF, sum = 0
6783 18:06:57.306107 3, 0xFFFF, sum = 0
6784 18:06:57.308877 4, 0xFFFF, sum = 0
6785 18:06:57.309018 5, 0xFFFF, sum = 0
6786 18:06:57.312522 6, 0xFFFF, sum = 0
6787 18:06:57.312624 7, 0xFFFF, sum = 0
6788 18:06:57.315844 8, 0xFFFF, sum = 0
6789 18:06:57.315946 9, 0xFFFF, sum = 0
6790 18:06:57.319333 10, 0xFFFF, sum = 0
6791 18:06:57.319435 11, 0xFFFF, sum = 0
6792 18:06:57.322542 12, 0xFFFF, sum = 0
6793 18:06:57.322644 13, 0x0, sum = 1
6794 18:06:57.326038 14, 0x0, sum = 2
6795 18:06:57.326148 15, 0x0, sum = 3
6796 18:06:57.329339 16, 0x0, sum = 4
6797 18:06:57.329486 best_step = 14
6798 18:06:57.329613
6799 18:06:57.329698 ==
6800 18:06:57.332629 Dram Type= 6, Freq= 0, CH_1, rank 0
6801 18:06:57.335766 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6802 18:06:57.335887 ==
6803 18:06:57.339226 RX Vref Scan: 1
6804 18:06:57.339358
6805 18:06:57.342999 RX Vref 0 -> 0, step: 1
6806 18:06:57.343232
6807 18:06:57.343383 RX Delay -359 -> 252, step: 8
6808 18:06:57.345779
6809 18:06:57.345939 Set Vref, RX VrefLevel [Byte0]: 58
6810 18:06:57.349285 [Byte1]: 52
6811 18:06:57.354953
6812 18:06:57.355230 Final RX Vref Byte 0 = 58 to rank0
6813 18:06:57.358565 Final RX Vref Byte 1 = 52 to rank0
6814 18:06:57.361515 Final RX Vref Byte 0 = 58 to rank1
6815 18:06:57.365156 Final RX Vref Byte 1 = 52 to rank1==
6816 18:06:57.368872 Dram Type= 6, Freq= 0, CH_1, rank 0
6817 18:06:57.375280 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6818 18:06:57.375701 ==
6819 18:06:57.376163 DQS Delay:
6820 18:06:57.378057 DQS0 = 48, DQS1 = 60
6821 18:06:57.378462 DQM Delay:
6822 18:06:57.378796 DQM0 = 11, DQM1 = 13
6823 18:06:57.381887 DQ Delay:
6824 18:06:57.384853 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6825 18:06:57.385298 DQ4 =8, DQ5 =20, DQ6 =24, DQ7 =4
6826 18:06:57.388222 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =12
6827 18:06:57.391830 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20
6828 18:06:57.392239
6829 18:06:57.394933
6830 18:06:57.401457 [DQSOSCAuto] RK0, (LSB)MR18= 0x842c, (MSB)MR19= 0xc0c, tDQSOscB0 = 404 ps tDQSOscB1 = 393 ps
6831 18:06:57.404869 CH1 RK0: MR19=C0C, MR18=842C
6832 18:06:57.411484 CH1_RK0: MR19=0xC0C, MR18=0x842C, DQSOSC=393, MR23=63, INC=382, DEC=254
6833 18:06:57.412067 ==
6834 18:06:57.415102 Dram Type= 6, Freq= 0, CH_1, rank 1
6835 18:06:57.418457 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6836 18:06:57.418881 ==
6837 18:06:57.421360 [Gating] SW mode calibration
6838 18:06:57.428397 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6839 18:06:57.434622 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6840 18:06:57.438641 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6841 18:06:57.441358 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6842 18:06:57.444700 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6843 18:06:57.451307 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6844 18:06:57.454639 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6845 18:06:57.458056 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6846 18:06:57.465272 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6847 18:06:57.468341 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6848 18:06:57.471959 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6849 18:06:57.474894 Total UI for P1: 0, mck2ui 16
6850 18:06:57.478220 best dqsien dly found for B0: ( 0, 14, 24)
6851 18:06:57.481733 Total UI for P1: 0, mck2ui 16
6852 18:06:57.485280 best dqsien dly found for B1: ( 0, 14, 24)
6853 18:06:57.488417 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6854 18:06:57.491852 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6855 18:06:57.492283
6856 18:06:57.498405 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6857 18:06:57.501910 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6858 18:06:57.502373 [Gating] SW calibration Done
6859 18:06:57.504800 ==
6860 18:06:57.508696 Dram Type= 6, Freq= 0, CH_1, rank 1
6861 18:06:57.511728 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6862 18:06:57.512184 ==
6863 18:06:57.512601 RX Vref Scan: 0
6864 18:06:57.513105
6865 18:06:57.515368 RX Vref 0 -> 0, step: 1
6866 18:06:57.515784
6867 18:06:57.518420 RX Delay -410 -> 252, step: 16
6868 18:06:57.521922 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6869 18:06:57.525103 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6870 18:06:57.531505 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6871 18:06:57.534930 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6872 18:06:57.538587 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6873 18:06:57.542029 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6874 18:06:57.548464 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6875 18:06:57.551558 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6876 18:06:57.555019 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6877 18:06:57.558474 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6878 18:06:57.564919 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6879 18:06:57.568630 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6880 18:06:57.571618 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6881 18:06:57.574977 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6882 18:06:57.581659 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6883 18:06:57.585177 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6884 18:06:57.585594 ==
6885 18:06:57.588330 Dram Type= 6, Freq= 0, CH_1, rank 1
6886 18:06:57.591671 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6887 18:06:57.592087 ==
6888 18:06:57.595148 DQS Delay:
6889 18:06:57.595563 DQS0 = 43, DQS1 = 59
6890 18:06:57.598289 DQM Delay:
6891 18:06:57.598844 DQM0 = 9, DQM1 = 19
6892 18:06:57.599204 DQ Delay:
6893 18:06:57.601712 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =8
6894 18:06:57.605072 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6895 18:06:57.608124 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6896 18:06:57.611765 DQ12 =24, DQ13 =32, DQ14 =24, DQ15 =32
6897 18:06:57.612176
6898 18:06:57.612500
6899 18:06:57.612809 ==
6900 18:06:57.615455 Dram Type= 6, Freq= 0, CH_1, rank 1
6901 18:06:57.618450 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6902 18:06:57.621987 ==
6903 18:06:57.622398
6904 18:06:57.622727
6905 18:06:57.623050 TX Vref Scan disable
6906 18:06:57.624856 == TX Byte 0 ==
6907 18:06:57.628510 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6908 18:06:57.632028 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6909 18:06:57.635502 == TX Byte 1 ==
6910 18:06:57.638673 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6911 18:06:57.642116 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6912 18:06:57.642639 ==
6913 18:06:57.645077 Dram Type= 6, Freq= 0, CH_1, rank 1
6914 18:06:57.648684 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6915 18:06:57.652123 ==
6916 18:06:57.652644
6917 18:06:57.653189
6918 18:06:57.653759 TX Vref Scan disable
6919 18:06:57.655549 == TX Byte 0 ==
6920 18:06:57.658647 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6921 18:06:57.662059 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6922 18:06:57.665123 == TX Byte 1 ==
6923 18:06:57.668639 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6924 18:06:57.671539 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6925 18:06:57.672027
6926 18:06:57.672561 [DATLAT]
6927 18:06:57.675339 Freq=400, CH1 RK1
6928 18:06:57.675916
6929 18:06:57.678791 DATLAT Default: 0xe
6930 18:06:57.679386 0, 0xFFFF, sum = 0
6931 18:06:57.681804 1, 0xFFFF, sum = 0
6932 18:06:57.682399 2, 0xFFFF, sum = 0
6933 18:06:57.684923 3, 0xFFFF, sum = 0
6934 18:06:57.685513 4, 0xFFFF, sum = 0
6935 18:06:57.688345 5, 0xFFFF, sum = 0
6936 18:06:57.688766 6, 0xFFFF, sum = 0
6937 18:06:57.691596 7, 0xFFFF, sum = 0
6938 18:06:57.692011 8, 0xFFFF, sum = 0
6939 18:06:57.695265 9, 0xFFFF, sum = 0
6940 18:06:57.695563 10, 0xFFFF, sum = 0
6941 18:06:57.698377 11, 0xFFFF, sum = 0
6942 18:06:57.698805 12, 0xFFFF, sum = 0
6943 18:06:57.701562 13, 0x0, sum = 1
6944 18:06:57.701955 14, 0x0, sum = 2
6945 18:06:57.705015 15, 0x0, sum = 3
6946 18:06:57.705428 16, 0x0, sum = 4
6947 18:06:57.708299 best_step = 14
6948 18:06:57.708592
6949 18:06:57.708833 ==
6950 18:06:57.711829 Dram Type= 6, Freq= 0, CH_1, rank 1
6951 18:06:57.714901 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6952 18:06:57.715212 ==
6953 18:06:57.715464 RX Vref Scan: 0
6954 18:06:57.718718
6955 18:06:57.719023 RX Vref 0 -> 0, step: 1
6956 18:06:57.719272
6957 18:06:57.721956 RX Delay -359 -> 252, step: 8
6958 18:06:57.729160 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6959 18:06:57.733024 iDelay=217, Bit 1, Center -44 (-287 ~ 200) 488
6960 18:06:57.736059 iDelay=217, Bit 2, Center -52 (-295 ~ 192) 488
6961 18:06:57.739076 iDelay=217, Bit 3, Center -40 (-279 ~ 200) 480
6962 18:06:57.745993 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6963 18:06:57.749206 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6964 18:06:57.752257 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6965 18:06:57.755913 iDelay=217, Bit 7, Center -44 (-287 ~ 200) 488
6966 18:06:57.762222 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
6967 18:06:57.765949 iDelay=217, Bit 9, Center -56 (-303 ~ 192) 496
6968 18:06:57.769429 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6969 18:06:57.772364 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6970 18:06:57.778795 iDelay=217, Bit 12, Center -40 (-279 ~ 200) 480
6971 18:06:57.782853 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6972 18:06:57.785731 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6973 18:06:57.792402 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6974 18:06:57.792793 ==
6975 18:06:57.795992 Dram Type= 6, Freq= 0, CH_1, rank 1
6976 18:06:57.798986 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6977 18:06:57.799373 ==
6978 18:06:57.799715 DQS Delay:
6979 18:06:57.802362 DQS0 = 52, DQS1 = 56
6980 18:06:57.802739 DQM Delay:
6981 18:06:57.805882 DQM0 = 13, DQM1 = 9
6982 18:06:57.806222 DQ Delay:
6983 18:06:57.809210 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6984 18:06:57.812523 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =8
6985 18:06:57.815613 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
6986 18:06:57.819008 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6987 18:06:57.819580
6988 18:06:57.820041
6989 18:06:57.825787 [DQSOSCAuto] RK1, (LSB)MR18= 0x768c, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 394 ps
6990 18:06:57.828771 CH1 RK1: MR19=C0C, MR18=768C
6991 18:06:57.836009 CH1_RK1: MR19=0xC0C, MR18=0x768C, DQSOSC=392, MR23=63, INC=384, DEC=256
6992 18:06:57.839134 [RxdqsGatingPostProcess] freq 400
6993 18:06:57.845656 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6994 18:06:57.846191 best DQS0 dly(2T, 0.5T) = (0, 10)
6995 18:06:57.848819 best DQS1 dly(2T, 0.5T) = (0, 10)
6996 18:06:57.852363 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6997 18:06:57.855958 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6998 18:06:57.858940 best DQS0 dly(2T, 0.5T) = (0, 10)
6999 18:06:57.862590 best DQS1 dly(2T, 0.5T) = (0, 10)
7000 18:06:57.865673 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7001 18:06:57.869083 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7002 18:06:57.872844 Pre-setting of DQS Precalculation
7003 18:06:57.875350 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7004 18:06:57.885426 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7005 18:06:57.892331 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7006 18:06:57.892877
7007 18:06:57.893399
7008 18:06:57.895326 [Calibration Summary] 800 Mbps
7009 18:06:57.895842 CH 0, Rank 0
7010 18:06:57.898971 SW Impedance : PASS
7011 18:06:57.899385 DUTY Scan : NO K
7012 18:06:57.902471 ZQ Calibration : PASS
7013 18:06:57.905490 Jitter Meter : NO K
7014 18:06:57.905913 CBT Training : PASS
7015 18:06:57.908583 Write leveling : PASS
7016 18:06:57.912089 RX DQS gating : PASS
7017 18:06:57.912515 RX DQ/DQS(RDDQC) : PASS
7018 18:06:57.915786 TX DQ/DQS : PASS
7019 18:06:57.918721 RX DATLAT : PASS
7020 18:06:57.919418 RX DQ/DQS(Engine): PASS
7021 18:06:57.922417 TX OE : NO K
7022 18:06:57.922952 All Pass.
7023 18:06:57.923576
7024 18:06:57.925714 CH 0, Rank 1
7025 18:06:57.926159 SW Impedance : PASS
7026 18:06:57.929335 DUTY Scan : NO K
7027 18:06:57.929848 ZQ Calibration : PASS
7028 18:06:57.932240 Jitter Meter : NO K
7029 18:06:57.936145 CBT Training : PASS
7030 18:06:57.936423 Write leveling : NO K
7031 18:06:57.938744 RX DQS gating : PASS
7032 18:06:57.942080 RX DQ/DQS(RDDQC) : PASS
7033 18:06:57.942379 TX DQ/DQS : PASS
7034 18:06:57.945674 RX DATLAT : PASS
7035 18:06:57.948693 RX DQ/DQS(Engine): PASS
7036 18:06:57.948934 TX OE : NO K
7037 18:06:57.952346 All Pass.
7038 18:06:57.952542
7039 18:06:57.952723 CH 1, Rank 0
7040 18:06:57.955461 SW Impedance : PASS
7041 18:06:57.955658 DUTY Scan : NO K
7042 18:06:57.958664 ZQ Calibration : PASS
7043 18:06:57.962558 Jitter Meter : NO K
7044 18:06:57.962696 CBT Training : PASS
7045 18:06:57.965673 Write leveling : PASS
7046 18:06:57.965785 RX DQS gating : PASS
7047 18:06:57.968733 RX DQ/DQS(RDDQC) : PASS
7048 18:06:57.972235 TX DQ/DQS : PASS
7049 18:06:57.972335 RX DATLAT : PASS
7050 18:06:57.975583 RX DQ/DQS(Engine): PASS
7051 18:06:57.979120 TX OE : NO K
7052 18:06:57.979225 All Pass.
7053 18:06:57.979330
7054 18:06:57.979429 CH 1, Rank 1
7055 18:06:57.981959 SW Impedance : PASS
7056 18:06:57.985601 DUTY Scan : NO K
7057 18:06:57.985706 ZQ Calibration : PASS
7058 18:06:57.988606 Jitter Meter : NO K
7059 18:06:57.992057 CBT Training : PASS
7060 18:06:57.992194 Write leveling : NO K
7061 18:06:57.995506 RX DQS gating : PASS
7062 18:06:57.999242 RX DQ/DQS(RDDQC) : PASS
7063 18:06:57.999376 TX DQ/DQS : PASS
7064 18:06:58.002354 RX DATLAT : PASS
7065 18:06:58.002499 RX DQ/DQS(Engine): PASS
7066 18:06:58.005368 TX OE : NO K
7067 18:06:58.005476 All Pass.
7068 18:06:58.005562
7069 18:06:58.009166 DramC Write-DBI off
7070 18:06:58.012612 PER_BANK_REFRESH: Hybrid Mode
7071 18:06:58.012792 TX_TRACKING: ON
7072 18:06:58.022431 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7073 18:06:58.026042 [FAST_K] Save calibration result to emmc
7074 18:06:58.029032 dramc_set_vcore_voltage set vcore to 725000
7075 18:06:58.032209 Read voltage for 1600, 0
7076 18:06:58.032501 Vio18 = 0
7077 18:06:58.035901 Vcore = 725000
7078 18:06:58.036205 Vdram = 0
7079 18:06:58.036495 Vddq = 0
7080 18:06:58.036751 Vmddr = 0
7081 18:06:58.042376 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7082 18:06:58.046067 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7083 18:06:58.049343 MEM_TYPE=3, freq_sel=13
7084 18:06:58.052697 sv_algorithm_assistance_LP4_3733
7085 18:06:58.056165 ============ PULL DRAM RESETB DOWN ============
7086 18:06:58.059553 ========== PULL DRAM RESETB DOWN end =========
7087 18:06:58.066142 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7088 18:06:58.069473 ===================================
7089 18:06:58.072664 LPDDR4 DRAM CONFIGURATION
7090 18:06:58.076196 ===================================
7091 18:06:58.076561 EX_ROW_EN[0] = 0x0
7092 18:06:58.079312 EX_ROW_EN[1] = 0x0
7093 18:06:58.079833 LP4Y_EN = 0x0
7094 18:06:58.082366 WORK_FSP = 0x1
7095 18:06:58.082748 WL = 0x5
7096 18:06:58.086320 RL = 0x5
7097 18:06:58.086696 BL = 0x2
7098 18:06:58.089118 RPST = 0x0
7099 18:06:58.089498 RD_PRE = 0x0
7100 18:06:58.092549 WR_PRE = 0x1
7101 18:06:58.092928 WR_PST = 0x1
7102 18:06:58.095690 DBI_WR = 0x0
7103 18:06:58.096071 DBI_RD = 0x0
7104 18:06:58.099039 OTF = 0x1
7105 18:06:58.102319 ===================================
7106 18:06:58.105940 ===================================
7107 18:06:58.106322 ANA top config
7108 18:06:58.108908 ===================================
7109 18:06:58.112734 DLL_ASYNC_EN = 0
7110 18:06:58.115785 ALL_SLAVE_EN = 0
7111 18:06:58.119352 NEW_RANK_MODE = 1
7112 18:06:58.119824 DLL_IDLE_MODE = 1
7113 18:06:58.122470 LP45_APHY_COMB_EN = 1
7114 18:06:58.126068 TX_ODT_DIS = 0
7115 18:06:58.129080 NEW_8X_MODE = 1
7116 18:06:58.132736 ===================================
7117 18:06:58.135743 ===================================
7118 18:06:58.139284 data_rate = 3200
7119 18:06:58.139667 CKR = 1
7120 18:06:58.142565 DQ_P2S_RATIO = 8
7121 18:06:58.145609 ===================================
7122 18:06:58.148875 CA_P2S_RATIO = 8
7123 18:06:58.152210 DQ_CA_OPEN = 0
7124 18:06:58.155677 DQ_SEMI_OPEN = 0
7125 18:06:58.159026 CA_SEMI_OPEN = 0
7126 18:06:58.159408 CA_FULL_RATE = 0
7127 18:06:58.162554 DQ_CKDIV4_EN = 0
7128 18:06:58.165731 CA_CKDIV4_EN = 0
7129 18:06:58.169439 CA_PREDIV_EN = 0
7130 18:06:58.172560 PH8_DLY = 12
7131 18:06:58.190876 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7132 18:06:58.191266 DQ_AAMCK_DIV = 4
7133 18:06:58.191900 CA_AAMCK_DIV = 4
7134 18:06:58.192325 CA_ADMCK_DIV = 4
7135 18:06:58.192628 DQ_TRACK_CA_EN = 0
7136 18:06:58.192904 CA_PICK = 1600
7137 18:06:58.193286 CA_MCKIO = 1600
7138 18:06:58.195783 MCKIO_SEMI = 0
7139 18:06:58.196249 PLL_FREQ = 3068
7140 18:06:58.199327 DQ_UI_PI_RATIO = 32
7141 18:06:58.202382 CA_UI_PI_RATIO = 0
7142 18:06:58.206326 ===================================
7143 18:06:58.209063 ===================================
7144 18:06:58.212620 memory_type:LPDDR4
7145 18:06:58.213191 GP_NUM : 10
7146 18:06:58.215929 SRAM_EN : 1
7147 18:06:58.218962 MD32_EN : 0
7148 18:06:58.222716 ===================================
7149 18:06:58.223138 [ANA_INIT] >>>>>>>>>>>>>>
7150 18:06:58.225618 <<<<<< [CONFIGURE PHASE]: ANA_TX
7151 18:06:58.229306 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7152 18:06:58.232258 ===================================
7153 18:06:58.235898 data_rate = 3200,PCW = 0X7600
7154 18:06:58.238978 ===================================
7155 18:06:58.242372 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7156 18:06:58.249075 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7157 18:06:58.252610 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7158 18:06:58.258891 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7159 18:06:58.262040 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7160 18:06:58.265589 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7161 18:06:58.265877 [ANA_INIT] flow start
7162 18:06:58.268642 [ANA_INIT] PLL >>>>>>>>
7163 18:06:58.272751 [ANA_INIT] PLL <<<<<<<<
7164 18:06:58.275489 [ANA_INIT] MIDPI >>>>>>>>
7165 18:06:58.275879 [ANA_INIT] MIDPI <<<<<<<<
7166 18:06:58.279096 [ANA_INIT] DLL >>>>>>>>
7167 18:06:58.282156 [ANA_INIT] DLL <<<<<<<<
7168 18:06:58.282519 [ANA_INIT] flow end
7169 18:06:58.285863 ============ LP4 DIFF to SE enter ============
7170 18:06:58.292125 ============ LP4 DIFF to SE exit ============
7171 18:06:58.292403 [ANA_INIT] <<<<<<<<<<<<<
7172 18:06:58.295561 [Flow] Enable top DCM control >>>>>
7173 18:06:58.298983 [Flow] Enable top DCM control <<<<<
7174 18:06:58.302448 Enable DLL master slave shuffle
7175 18:06:58.308733 ==============================================================
7176 18:06:58.309037 Gating Mode config
7177 18:06:58.315918 ==============================================================
7178 18:06:58.319031 Config description:
7179 18:06:58.325803 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7180 18:06:58.332056 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7181 18:06:58.338775 SELPH_MODE 0: By rank 1: By Phase
7182 18:06:58.342422 ==============================================================
7183 18:06:58.346021 GAT_TRACK_EN = 1
7184 18:06:58.349585 RX_GATING_MODE = 2
7185 18:06:58.352752 RX_GATING_TRACK_MODE = 2
7186 18:06:58.355862 SELPH_MODE = 1
7187 18:06:58.359411 PICG_EARLY_EN = 1
7188 18:06:58.363014 VALID_LAT_VALUE = 1
7189 18:06:58.369210 ==============================================================
7190 18:06:58.372486 Enter into Gating configuration >>>>
7191 18:06:58.375919 Exit from Gating configuration <<<<
7192 18:06:58.378979 Enter into DVFS_PRE_config >>>>>
7193 18:06:58.389312 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7194 18:06:58.392293 Exit from DVFS_PRE_config <<<<<
7195 18:06:58.396036 Enter into PICG configuration >>>>
7196 18:06:58.399469 Exit from PICG configuration <<<<
7197 18:06:58.399760 [RX_INPUT] configuration >>>>>
7198 18:06:58.402959 [RX_INPUT] configuration <<<<<
7199 18:06:58.409132 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7200 18:06:58.412619 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7201 18:06:58.419167 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7202 18:06:58.426021 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7203 18:06:58.432612 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7204 18:06:58.439528 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7205 18:06:58.442998 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7206 18:06:58.446144 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7207 18:06:58.452800 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7208 18:06:58.456307 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7209 18:06:58.459487 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7210 18:06:58.462424 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7211 18:06:58.466058 ===================================
7212 18:06:58.469595 LPDDR4 DRAM CONFIGURATION
7213 18:06:58.472529 ===================================
7214 18:06:58.476114 EX_ROW_EN[0] = 0x0
7215 18:06:58.476384 EX_ROW_EN[1] = 0x0
7216 18:06:58.479672 LP4Y_EN = 0x0
7217 18:06:58.479955 WORK_FSP = 0x1
7218 18:06:58.482589 WL = 0x5
7219 18:06:58.482878 RL = 0x5
7220 18:06:58.486333 BL = 0x2
7221 18:06:58.486695 RPST = 0x0
7222 18:06:58.489077 RD_PRE = 0x0
7223 18:06:58.489352 WR_PRE = 0x1
7224 18:06:58.492542 WR_PST = 0x1
7225 18:06:58.492808 DBI_WR = 0x0
7226 18:06:58.496315 DBI_RD = 0x0
7227 18:06:58.496581 OTF = 0x1
7228 18:06:58.499444 ===================================
7229 18:06:58.505804 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7230 18:06:58.508866 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7231 18:06:58.512458 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7232 18:06:58.515887 ===================================
7233 18:06:58.519163 LPDDR4 DRAM CONFIGURATION
7234 18:06:58.522430 ===================================
7235 18:06:58.526178 EX_ROW_EN[0] = 0x10
7236 18:06:58.526531 EX_ROW_EN[1] = 0x0
7237 18:06:58.528915 LP4Y_EN = 0x0
7238 18:06:58.529216 WORK_FSP = 0x1
7239 18:06:58.532273 WL = 0x5
7240 18:06:58.532541 RL = 0x5
7241 18:06:58.535773 BL = 0x2
7242 18:06:58.536059 RPST = 0x0
7243 18:06:58.539480 RD_PRE = 0x0
7244 18:06:58.539753 WR_PRE = 0x1
7245 18:06:58.542405 WR_PST = 0x1
7246 18:06:58.542678 DBI_WR = 0x0
7247 18:06:58.545670 DBI_RD = 0x0
7248 18:06:58.545941 OTF = 0x1
7249 18:06:58.548867 ===================================
7250 18:06:58.555821 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7251 18:06:58.556092 ==
7252 18:06:58.558870 Dram Type= 6, Freq= 0, CH_0, rank 0
7253 18:06:58.562146 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7254 18:06:58.565963 ==
7255 18:06:58.566235 [Duty_Offset_Calibration]
7256 18:06:58.568961 B0:2 B1:-1 CA:1
7257 18:06:58.569337
7258 18:06:58.572419 [DutyScan_Calibration_Flow] k_type=0
7259 18:06:58.580621
7260 18:06:58.580742 ==CLK 0==
7261 18:06:58.583688 Final CLK duty delay cell = -4
7262 18:06:58.587371 [-4] MAX Duty = 5031%(X100), DQS PI = 22
7263 18:06:58.590404 [-4] MIN Duty = 4844%(X100), DQS PI = 32
7264 18:06:58.593942 [-4] AVG Duty = 4937%(X100)
7265 18:06:58.594021
7266 18:06:58.597182 CH0 CLK Duty spec in!! Max-Min= 187%
7267 18:06:58.600326 [DutyScan_Calibration_Flow] ====Done====
7268 18:06:58.600431
7269 18:06:58.603810 [DutyScan_Calibration_Flow] k_type=1
7270 18:06:58.620047
7271 18:06:58.620180 ==DQS 0 ==
7272 18:06:58.622938 Final DQS duty delay cell = 0
7273 18:06:58.626516 [0] MAX Duty = 5125%(X100), DQS PI = 22
7274 18:06:58.630029 [0] MIN Duty = 5000%(X100), DQS PI = 32
7275 18:06:58.632913 [0] AVG Duty = 5062%(X100)
7276 18:06:58.633037
7277 18:06:58.633131 ==DQS 1 ==
7278 18:06:58.636228 Final DQS duty delay cell = -4
7279 18:06:58.640141 [-4] MAX Duty = 5093%(X100), DQS PI = 0
7280 18:06:58.643234 [-4] MIN Duty = 5000%(X100), DQS PI = 40
7281 18:06:58.646314 [-4] AVG Duty = 5046%(X100)
7282 18:06:58.646402
7283 18:06:58.649781 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7284 18:06:58.649860
7285 18:06:58.653358 CH0 DQS 1 Duty spec in!! Max-Min= 93%
7286 18:06:58.656661 [DutyScan_Calibration_Flow] ====Done====
7287 18:06:58.656736
7288 18:06:58.659641 [DutyScan_Calibration_Flow] k_type=3
7289 18:06:58.677561
7290 18:06:58.677665 ==DQM 0 ==
7291 18:06:58.680572 Final DQM duty delay cell = 0
7292 18:06:58.684226 [0] MAX Duty = 5000%(X100), DQS PI = 18
7293 18:06:58.687252 [0] MIN Duty = 4875%(X100), DQS PI = 4
7294 18:06:58.687359 [0] AVG Duty = 4937%(X100)
7295 18:06:58.690432
7296 18:06:58.690544 ==DQM 1 ==
7297 18:06:58.694015 Final DQM duty delay cell = 0
7298 18:06:58.697088 [0] MAX Duty = 5218%(X100), DQS PI = 58
7299 18:06:58.700662 [0] MIN Duty = 4969%(X100), DQS PI = 18
7300 18:06:58.700836 [0] AVG Duty = 5093%(X100)
7301 18:06:58.703934
7302 18:06:58.707620 CH0 DQM 0 Duty spec in!! Max-Min= 125%
7303 18:06:58.707764
7304 18:06:58.711253 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7305 18:06:58.714190 [DutyScan_Calibration_Flow] ====Done====
7306 18:06:58.714411
7307 18:06:58.717662 [DutyScan_Calibration_Flow] k_type=2
7308 18:06:58.734349
7309 18:06:58.734545 ==DQ 0 ==
7310 18:06:58.738045 Final DQ duty delay cell = 0
7311 18:06:58.741370 [0] MAX Duty = 5156%(X100), DQS PI = 0
7312 18:06:58.744516 [0] MIN Duty = 5031%(X100), DQS PI = 4
7313 18:06:58.744721 [0] AVG Duty = 5093%(X100)
7314 18:06:58.744879
7315 18:06:58.748275 ==DQ 1 ==
7316 18:06:58.751350 Final DQ duty delay cell = 0
7317 18:06:58.754479 [0] MAX Duty = 5031%(X100), DQS PI = 30
7318 18:06:58.758014 [0] MIN Duty = 4907%(X100), DQS PI = 18
7319 18:06:58.758211 [0] AVG Duty = 4969%(X100)
7320 18:06:58.758368
7321 18:06:58.761000 CH0 DQ 0 Duty spec in!! Max-Min= 125%
7322 18:06:58.761198
7323 18:06:58.764654 CH0 DQ 1 Duty spec in!! Max-Min= 124%
7324 18:06:58.771240 [DutyScan_Calibration_Flow] ====Done====
7325 18:06:58.771435 ==
7326 18:06:58.775150 Dram Type= 6, Freq= 0, CH_1, rank 0
7327 18:06:58.778098 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7328 18:06:58.778294 ==
7329 18:06:58.781097 [Duty_Offset_Calibration]
7330 18:06:58.781295 B0:1 B1:1 CA:2
7331 18:06:58.781464
7332 18:06:58.784645 [DutyScan_Calibration_Flow] k_type=0
7333 18:06:58.794693
7334 18:06:58.794889 ==CLK 0==
7335 18:06:58.797812 Final CLK duty delay cell = 0
7336 18:06:58.801352 [0] MAX Duty = 5187%(X100), DQS PI = 24
7337 18:06:58.805142 [0] MIN Duty = 4969%(X100), DQS PI = 0
7338 18:06:58.805415 [0] AVG Duty = 5078%(X100)
7339 18:06:58.808029
7340 18:06:58.811325 CH1 CLK Duty spec in!! Max-Min= 218%
7341 18:06:58.814634 [DutyScan_Calibration_Flow] ====Done====
7342 18:06:58.814874
7343 18:06:58.817776 [DutyScan_Calibration_Flow] k_type=1
7344 18:06:58.834171
7345 18:06:58.834366 ==DQS 0 ==
7346 18:06:58.837646 Final DQS duty delay cell = 0
7347 18:06:58.840998 [0] MAX Duty = 5062%(X100), DQS PI = 22
7348 18:06:58.844509 [0] MIN Duty = 4813%(X100), DQS PI = 52
7349 18:06:58.848286 [0] AVG Duty = 4937%(X100)
7350 18:06:58.848576
7351 18:06:58.848803 ==DQS 1 ==
7352 18:06:58.850911 Final DQS duty delay cell = 0
7353 18:06:58.854660 [0] MAX Duty = 5031%(X100), DQS PI = 34
7354 18:06:58.857725 [0] MIN Duty = 4938%(X100), DQS PI = 12
7355 18:06:58.861351 [0] AVG Duty = 4984%(X100)
7356 18:06:58.861710
7357 18:06:58.864472 CH1 DQS 0 Duty spec in!! Max-Min= 249%
7358 18:06:58.864855
7359 18:06:58.868056 CH1 DQS 1 Duty spec in!! Max-Min= 93%
7360 18:06:58.871144 [DutyScan_Calibration_Flow] ====Done====
7361 18:06:58.871514
7362 18:06:58.874512 [DutyScan_Calibration_Flow] k_type=3
7363 18:06:58.891356
7364 18:06:58.891649 ==DQM 0 ==
7365 18:06:58.894379 Final DQM duty delay cell = 0
7366 18:06:58.898033 [0] MAX Duty = 5156%(X100), DQS PI = 20
7367 18:06:58.901308 [0] MIN Duty = 4844%(X100), DQS PI = 50
7368 18:06:58.904778 [0] AVG Duty = 5000%(X100)
7369 18:06:58.905095
7370 18:06:58.905334 ==DQM 1 ==
7371 18:06:58.907796 Final DQM duty delay cell = 0
7372 18:06:58.911015 [0] MAX Duty = 5156%(X100), DQS PI = 60
7373 18:06:58.914744 [0] MIN Duty = 4907%(X100), DQS PI = 20
7374 18:06:58.917692 [0] AVG Duty = 5031%(X100)
7375 18:06:58.918089
7376 18:06:58.920867 CH1 DQM 0 Duty spec in!! Max-Min= 312%
7377 18:06:58.921289
7378 18:06:58.924262 CH1 DQM 1 Duty spec in!! Max-Min= 249%
7379 18:06:58.928031 [DutyScan_Calibration_Flow] ====Done====
7380 18:06:58.928340
7381 18:06:58.930898 [DutyScan_Calibration_Flow] k_type=2
7382 18:06:58.948160
7383 18:06:58.948477 ==DQ 0 ==
7384 18:06:58.951590 Final DQ duty delay cell = 0
7385 18:06:58.955112 [0] MAX Duty = 5125%(X100), DQS PI = 22
7386 18:06:58.958599 [0] MIN Duty = 4875%(X100), DQS PI = 52
7387 18:06:58.958938 [0] AVG Duty = 5000%(X100)
7388 18:06:58.959267
7389 18:06:58.961954 ==DQ 1 ==
7390 18:06:58.965030 Final DQ duty delay cell = 0
7391 18:06:58.968546 [0] MAX Duty = 5093%(X100), DQS PI = 6
7392 18:06:58.971762 [0] MIN Duty = 5031%(X100), DQS PI = 0
7393 18:06:58.972071 [0] AVG Duty = 5062%(X100)
7394 18:06:58.972387
7395 18:06:58.974776 CH1 DQ 0 Duty spec in!! Max-Min= 250%
7396 18:06:58.975092
7397 18:06:58.978512 CH1 DQ 1 Duty spec in!! Max-Min= 62%
7398 18:06:58.984915 [DutyScan_Calibration_Flow] ====Done====
7399 18:06:58.987878 nWR fixed to 30
7400 18:06:58.988186 [ModeRegInit_LP4] CH0 RK0
7401 18:06:58.991553 [ModeRegInit_LP4] CH0 RK1
7402 18:06:58.994611 [ModeRegInit_LP4] CH1 RK0
7403 18:06:58.994941 [ModeRegInit_LP4] CH1 RK1
7404 18:06:58.998480 match AC timing 5
7405 18:06:59.001297 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7406 18:06:59.004923 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7407 18:06:59.011362 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7408 18:06:59.014855 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7409 18:06:59.021577 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7410 18:06:59.021955 [MiockJmeterHQA]
7411 18:06:59.022195
7412 18:06:59.024688 [DramcMiockJmeter] u1RxGatingPI = 0
7413 18:06:59.028133 0 : 4252, 4027
7414 18:06:59.028455 4 : 4252, 4027
7415 18:06:59.028836 8 : 4260, 4031
7416 18:06:59.031495 12 : 4253, 4026
7417 18:06:59.031910 16 : 4252, 4027
7418 18:06:59.034940 20 : 4365, 4140
7419 18:06:59.035238 24 : 4252, 4027
7420 18:06:59.038456 28 : 4253, 4027
7421 18:06:59.038753 32 : 4252, 4027
7422 18:06:59.038993 36 : 4255, 4029
7423 18:06:59.041093 40 : 4252, 4027
7424 18:06:59.041394 44 : 4364, 4137
7425 18:06:59.044912 48 : 4363, 4137
7426 18:06:59.045240 52 : 4255, 4029
7427 18:06:59.047955 56 : 4252, 4026
7428 18:06:59.048257 60 : 4252, 4027
7429 18:06:59.048497 64 : 4253, 4029
7430 18:06:59.051488 68 : 4252, 4029
7431 18:06:59.051786 72 : 4360, 4138
7432 18:06:59.054972 76 : 4250, 4027
7433 18:06:59.055272 80 : 4250, 4027
7434 18:06:59.058203 84 : 4250, 4027
7435 18:06:59.058502 88 : 4252, 4029
7436 18:06:59.061681 92 : 4250, 4027
7437 18:06:59.062097 96 : 4360, 3417
7438 18:06:59.062485 100 : 4360, 0
7439 18:06:59.064626 104 : 4250, 0
7440 18:06:59.065064 108 : 4252, 0
7441 18:06:59.068059 112 : 4360, 0
7442 18:06:59.068479 116 : 4250, 0
7443 18:06:59.068827 120 : 4250, 0
7444 18:06:59.071686 124 : 4250, 0
7445 18:06:59.071988 128 : 4252, 0
7446 18:06:59.074597 132 : 4250, 0
7447 18:06:59.074979 136 : 4250, 0
7448 18:06:59.075269 140 : 4252, 0
7449 18:06:59.078259 144 : 4361, 0
7450 18:06:59.078666 148 : 4361, 0
7451 18:06:59.078915 152 : 4363, 0
7452 18:06:59.081277 156 : 4250, 0
7453 18:06:59.081580 160 : 4250, 0
7454 18:06:59.084812 164 : 4250, 0
7455 18:06:59.085253 168 : 4249, 0
7456 18:06:59.085639 172 : 4250, 0
7457 18:06:59.087992 176 : 4250, 0
7458 18:06:59.088410 180 : 4252, 0
7459 18:06:59.090995 184 : 4249, 0
7460 18:06:59.091399 188 : 4250, 0
7461 18:06:59.091705 192 : 4252, 0
7462 18:06:59.094739 196 : 4250, 0
7463 18:06:59.095137 200 : 4250, 0
7464 18:06:59.098315 204 : 4363, 0
7465 18:06:59.098721 208 : 4361, 0
7466 18:06:59.098967 212 : 4361, 109
7467 18:06:59.101272 216 : 4250, 3650
7468 18:06:59.101676 220 : 4360, 4137
7469 18:06:59.104355 224 : 4250, 4026
7470 18:06:59.104654 228 : 4250, 4027
7471 18:06:59.107929 232 : 4250, 4027
7472 18:06:59.108228 236 : 4253, 4029
7473 18:06:59.110966 240 : 4250, 4027
7474 18:06:59.111372 244 : 4252, 4027
7475 18:06:59.114348 248 : 4360, 4138
7476 18:06:59.114772 252 : 4250, 4027
7477 18:06:59.117923 256 : 4250, 4027
7478 18:06:59.118327 260 : 4361, 4137
7479 18:06:59.118577 264 : 4250, 4027
7480 18:06:59.120884 268 : 4250, 4027
7481 18:06:59.121316 272 : 4363, 4140
7482 18:06:59.124272 276 : 4250, 4027
7483 18:06:59.124573 280 : 4250, 4027
7484 18:06:59.127705 284 : 4250, 4027
7485 18:06:59.128002 288 : 4252, 4029
7486 18:06:59.131392 292 : 4250, 4027
7487 18:06:59.131787 296 : 4250, 4027
7488 18:06:59.134562 300 : 4361, 4138
7489 18:06:59.134886 304 : 4250, 4027
7490 18:06:59.138080 308 : 4250, 4026
7491 18:06:59.138378 312 : 4361, 4137
7492 18:06:59.138617 316 : 4252, 4027
7493 18:06:59.141185 320 : 4249, 4027
7494 18:06:59.141486 324 : 4363, 4140
7495 18:06:59.144324 328 : 4250, 4027
7496 18:06:59.144670 332 : 4250, 3162
7497 18:06:59.147888 336 : 4250, 29
7498 18:06:59.148227
7499 18:06:59.148466 MIOCK jitter meter ch=0
7500 18:06:59.150877
7501 18:06:59.151233 1T = (336-100) = 236 dly cells
7502 18:06:59.157858 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7503 18:06:59.158154 ==
7504 18:06:59.161275 Dram Type= 6, Freq= 0, CH_0, rank 0
7505 18:06:59.164435 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7506 18:06:59.164775 ==
7507 18:06:59.171109 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7508 18:06:59.174091 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7509 18:06:59.180709 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7510 18:06:59.184215 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7511 18:06:59.194592 [CA 0] Center 44 (14~75) winsize 62
7512 18:06:59.198417 [CA 1] Center 44 (14~75) winsize 62
7513 18:06:59.201537 [CA 2] Center 40 (11~69) winsize 59
7514 18:06:59.204605 [CA 3] Center 39 (10~69) winsize 60
7515 18:06:59.208413 [CA 4] Center 37 (8~67) winsize 60
7516 18:06:59.211546 [CA 5] Center 37 (7~67) winsize 61
7517 18:06:59.212097
7518 18:06:59.215096 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7519 18:06:59.215563
7520 18:06:59.218097 [CATrainingPosCal] consider 1 rank data
7521 18:06:59.221215 u2DelayCellTimex100 = 275/100 ps
7522 18:06:59.224575 CA0 delay=44 (14~75),Diff = 7 PI (24 cell)
7523 18:06:59.231322 CA1 delay=44 (14~75),Diff = 7 PI (24 cell)
7524 18:06:59.234907 CA2 delay=40 (11~69),Diff = 3 PI (10 cell)
7525 18:06:59.238166 CA3 delay=39 (10~69),Diff = 2 PI (7 cell)
7526 18:06:59.241367 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7527 18:06:59.244510 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7528 18:06:59.244922
7529 18:06:59.248366 CA PerBit enable=1, Macro0, CA PI delay=37
7530 18:06:59.248811
7531 18:06:59.251293 [CBTSetCACLKResult] CA Dly = 37
7532 18:06:59.254769 CS Dly: 10 (0~41)
7533 18:06:59.257805 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7534 18:06:59.261341 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7535 18:06:59.261886 ==
7536 18:06:59.264711 Dram Type= 6, Freq= 0, CH_0, rank 1
7537 18:06:59.268138 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7538 18:06:59.271351 ==
7539 18:06:59.274596 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7540 18:06:59.277780 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7541 18:06:59.284416 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7542 18:06:59.288205 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7543 18:06:59.298471 [CA 0] Center 44 (14~75) winsize 62
7544 18:06:59.301749 [CA 1] Center 44 (14~75) winsize 62
7545 18:06:59.305301 [CA 2] Center 40 (11~69) winsize 59
7546 18:06:59.308310 [CA 3] Center 39 (10~69) winsize 60
7547 18:06:59.312127 [CA 4] Center 38 (9~68) winsize 60
7548 18:06:59.315285 [CA 5] Center 37 (7~67) winsize 61
7549 18:06:59.315699
7550 18:06:59.318222 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7551 18:06:59.318643
7552 18:06:59.321794 [CATrainingPosCal] consider 2 rank data
7553 18:06:59.325009 u2DelayCellTimex100 = 275/100 ps
7554 18:06:59.328379 CA0 delay=44 (14~75),Diff = 7 PI (24 cell)
7555 18:06:59.335057 CA1 delay=44 (14~75),Diff = 7 PI (24 cell)
7556 18:06:59.338595 CA2 delay=40 (11~69),Diff = 3 PI (10 cell)
7557 18:06:59.341625 CA3 delay=39 (10~69),Diff = 2 PI (7 cell)
7558 18:06:59.345392 CA4 delay=38 (9~67),Diff = 1 PI (3 cell)
7559 18:06:59.348413 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7560 18:06:59.348884
7561 18:06:59.351885 CA PerBit enable=1, Macro0, CA PI delay=37
7562 18:06:59.352305
7563 18:06:59.355200 [CBTSetCACLKResult] CA Dly = 37
7564 18:06:59.358216 CS Dly: 11 (0~44)
7565 18:06:59.361765 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7566 18:06:59.365004 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7567 18:06:59.365115
7568 18:06:59.368421 ----->DramcWriteLeveling(PI) begin...
7569 18:06:59.368505 ==
7570 18:06:59.371658 Dram Type= 6, Freq= 0, CH_0, rank 0
7571 18:06:59.378311 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7572 18:06:59.378395 ==
7573 18:06:59.381627 Write leveling (Byte 0): 35 => 35
7574 18:06:59.381730 Write leveling (Byte 1): 29 => 29
7575 18:06:59.385123 DramcWriteLeveling(PI) end<-----
7576 18:06:59.385207
7577 18:06:59.385272 ==
7578 18:06:59.388606 Dram Type= 6, Freq= 0, CH_0, rank 0
7579 18:06:59.394868 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7580 18:06:59.394952 ==
7581 18:06:59.395017 [Gating] SW mode calibration
7582 18:06:59.404935 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7583 18:06:59.408171 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7584 18:06:59.411732 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7585 18:06:59.418450 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7586 18:06:59.421721 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7587 18:06:59.425162 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7588 18:06:59.431827 1 4 16 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
7589 18:06:59.435394 1 4 20 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
7590 18:06:59.438490 1 4 24 | B1->B0 | 2c2c 3434 | 1 1 | (0 0) (1 1)
7591 18:06:59.444900 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7592 18:06:59.448765 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7593 18:06:59.451879 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7594 18:06:59.458034 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7595 18:06:59.461635 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7596 18:06:59.464860 1 5 16 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 1)
7597 18:06:59.471799 1 5 20 | B1->B0 | 3434 2323 | 1 0 | (1 0) (1 0)
7598 18:06:59.474923 1 5 24 | B1->B0 | 2e2e 2323 | 0 0 | (1 0) (0 0)
7599 18:06:59.478750 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7600 18:06:59.485245 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7601 18:06:59.488354 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7602 18:06:59.491847 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7603 18:06:59.498156 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7604 18:06:59.501855 1 6 16 | B1->B0 | 2323 2e2d | 0 1 | (0 0) (0 0)
7605 18:06:59.505159 1 6 20 | B1->B0 | 2525 4545 | 0 0 | (0 0) (0 0)
7606 18:06:59.511844 1 6 24 | B1->B0 | 3c3c 4646 | 1 0 | (0 0) (0 0)
7607 18:06:59.514730 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7608 18:06:59.518349 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7609 18:06:59.524482 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7610 18:06:59.528332 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7611 18:06:59.531419 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7612 18:06:59.537910 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7613 18:06:59.541708 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7614 18:06:59.544680 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7615 18:06:59.548341 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7616 18:06:59.555103 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7617 18:06:59.558049 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7618 18:06:59.561711 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7619 18:06:59.568409 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7620 18:06:59.571378 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7621 18:06:59.574640 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7622 18:06:59.581254 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7623 18:06:59.584755 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7624 18:06:59.588245 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7625 18:06:59.594752 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7626 18:06:59.598281 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7627 18:06:59.601306 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7628 18:06:59.608155 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7629 18:06:59.611248 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7630 18:06:59.614720 Total UI for P1: 0, mck2ui 16
7631 18:06:59.617980 best dqsien dly found for B0: ( 1, 9, 16)
7632 18:06:59.621422 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7633 18:06:59.628379 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7634 18:06:59.628582 Total UI for P1: 0, mck2ui 16
7635 18:06:59.632102 best dqsien dly found for B1: ( 1, 9, 22)
7636 18:06:59.635026 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
7637 18:06:59.641626 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7638 18:06:59.641921
7639 18:06:59.645209 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
7640 18:06:59.648736 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7641 18:06:59.651603 [Gating] SW calibration Done
7642 18:06:59.652017 ==
7643 18:06:59.655258 Dram Type= 6, Freq= 0, CH_0, rank 0
7644 18:06:59.658810 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7645 18:06:59.659229 ==
7646 18:06:59.661765 RX Vref Scan: 0
7647 18:06:59.662178
7648 18:06:59.662507 RX Vref 0 -> 0, step: 1
7649 18:06:59.662818
7650 18:06:59.665452 RX Delay 0 -> 252, step: 8
7651 18:06:59.668530 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
7652 18:06:59.671611 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
7653 18:06:59.678517 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7654 18:06:59.681981 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7655 18:06:59.685143 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7656 18:06:59.688416 iDelay=200, Bit 5, Center 115 (56 ~ 175) 120
7657 18:06:59.691497 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
7658 18:06:59.698553 iDelay=200, Bit 7, Center 139 (88 ~ 191) 104
7659 18:06:59.701639 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7660 18:06:59.704840 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7661 18:06:59.708500 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
7662 18:06:59.711397 iDelay=200, Bit 11, Center 119 (72 ~ 167) 96
7663 18:06:59.718063 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7664 18:06:59.721390 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
7665 18:06:59.724670 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7666 18:06:59.728187 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7667 18:06:59.728364 ==
7668 18:06:59.731360 Dram Type= 6, Freq= 0, CH_0, rank 0
7669 18:06:59.738194 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7670 18:06:59.738456 ==
7671 18:06:59.738681 DQS Delay:
7672 18:06:59.738896 DQS0 = 0, DQS1 = 0
7673 18:06:59.741459 DQM Delay:
7674 18:06:59.741640 DQM0 = 131, DQM1 = 125
7675 18:06:59.744763 DQ Delay:
7676 18:06:59.747955 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
7677 18:06:59.751549 DQ4 =135, DQ5 =115, DQ6 =143, DQ7 =139
7678 18:06:59.755028 DQ8 =111, DQ9 =115, DQ10 =123, DQ11 =119
7679 18:06:59.758533 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
7680 18:06:59.758868
7681 18:06:59.759235
7682 18:06:59.759551 ==
7683 18:06:59.761469 Dram Type= 6, Freq= 0, CH_0, rank 0
7684 18:06:59.765125 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7685 18:06:59.765608 ==
7686 18:06:59.768190
7687 18:06:59.768643
7688 18:06:59.769071 TX Vref Scan disable
7689 18:06:59.771593 == TX Byte 0 ==
7690 18:06:59.774745 Update DQ dly =994 (3 ,6, 34) DQ OEN =(3 ,3)
7691 18:06:59.778414 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
7692 18:06:59.781302 == TX Byte 1 ==
7693 18:06:59.784964 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7694 18:06:59.788670 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7695 18:06:59.789120 ==
7696 18:06:59.791605 Dram Type= 6, Freq= 0, CH_0, rank 0
7697 18:06:59.798060 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7698 18:06:59.798422 ==
7699 18:06:59.811913
7700 18:06:59.815476 TX Vref early break, caculate TX vref
7701 18:06:59.818629 TX Vref=16, minBit 7, minWin=21, winSum=366
7702 18:06:59.822282 TX Vref=18, minBit 7, minWin=22, winSum=379
7703 18:06:59.825687 TX Vref=20, minBit 2, minWin=23, winSum=389
7704 18:06:59.828842 TX Vref=22, minBit 4, minWin=24, winSum=400
7705 18:06:59.831574 TX Vref=24, minBit 1, minWin=24, winSum=411
7706 18:06:59.838821 TX Vref=26, minBit 4, minWin=25, winSum=424
7707 18:06:59.842332 TX Vref=28, minBit 4, minWin=26, winSum=428
7708 18:06:59.845594 TX Vref=30, minBit 4, minWin=25, winSum=425
7709 18:06:59.848682 TX Vref=32, minBit 4, minWin=25, winSum=418
7710 18:06:59.852261 TX Vref=34, minBit 0, minWin=24, winSum=407
7711 18:06:59.855322 TX Vref=36, minBit 0, minWin=24, winSum=395
7712 18:06:59.862113 [TxChooseVref] Worse bit 4, Min win 26, Win sum 428, Final Vref 28
7713 18:06:59.862443
7714 18:06:59.865229 Final TX Range 0 Vref 28
7715 18:06:59.865632
7716 18:06:59.865956 ==
7717 18:06:59.868972 Dram Type= 6, Freq= 0, CH_0, rank 0
7718 18:06:59.871937 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7719 18:06:59.872299 ==
7720 18:06:59.872634
7721 18:06:59.873049
7722 18:06:59.875596 TX Vref Scan disable
7723 18:06:59.881798 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7724 18:06:59.882166 == TX Byte 0 ==
7725 18:06:59.885463 u2DelayCellOfst[0]=14 cells (4 PI)
7726 18:06:59.888660 u2DelayCellOfst[1]=21 cells (6 PI)
7727 18:06:59.892144 u2DelayCellOfst[2]=10 cells (3 PI)
7728 18:06:59.895345 u2DelayCellOfst[3]=14 cells (4 PI)
7729 18:06:59.898936 u2DelayCellOfst[4]=10 cells (3 PI)
7730 18:06:59.902134 u2DelayCellOfst[5]=0 cells (0 PI)
7731 18:06:59.905632 u2DelayCellOfst[6]=21 cells (6 PI)
7732 18:06:59.908967 u2DelayCellOfst[7]=21 cells (6 PI)
7733 18:06:59.912003 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7734 18:06:59.915028 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7735 18:06:59.918296 == TX Byte 1 ==
7736 18:06:59.921652 u2DelayCellOfst[8]=0 cells (0 PI)
7737 18:06:59.922051 u2DelayCellOfst[9]=0 cells (0 PI)
7738 18:06:59.925447 u2DelayCellOfst[10]=7 cells (2 PI)
7739 18:06:59.928367 u2DelayCellOfst[11]=0 cells (0 PI)
7740 18:06:59.932650 u2DelayCellOfst[12]=10 cells (3 PI)
7741 18:06:59.935333 u2DelayCellOfst[13]=10 cells (3 PI)
7742 18:06:59.938679 u2DelayCellOfst[14]=14 cells (4 PI)
7743 18:06:59.941635 u2DelayCellOfst[15]=10 cells (3 PI)
7744 18:06:59.944832 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7745 18:06:59.951767 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7746 18:06:59.952183 DramC Write-DBI on
7747 18:06:59.952487 ==
7748 18:06:59.954840 Dram Type= 6, Freq= 0, CH_0, rank 0
7749 18:06:59.961557 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7750 18:06:59.961900 ==
7751 18:06:59.962186
7752 18:06:59.962480
7753 18:06:59.962785 TX Vref Scan disable
7754 18:06:59.965283 == TX Byte 0 ==
7755 18:06:59.968554 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
7756 18:06:59.972167 == TX Byte 1 ==
7757 18:06:59.975433 Update DQM dly =728 (2 ,6, 24) DQM OEN =(3 ,3)
7758 18:06:59.978695 DramC Write-DBI off
7759 18:06:59.979130
7760 18:06:59.979460 [DATLAT]
7761 18:06:59.979775 Freq=1600, CH0 RK0
7762 18:06:59.980148
7763 18:06:59.981959 DATLAT Default: 0xf
7764 18:06:59.982357 0, 0xFFFF, sum = 0
7765 18:06:59.985313 1, 0xFFFF, sum = 0
7766 18:06:59.985750 2, 0xFFFF, sum = 0
7767 18:06:59.989204 3, 0xFFFF, sum = 0
7768 18:06:59.992170 4, 0xFFFF, sum = 0
7769 18:06:59.992507 5, 0xFFFF, sum = 0
7770 18:06:59.995233 6, 0xFFFF, sum = 0
7771 18:06:59.995564 7, 0xFFFF, sum = 0
7772 18:06:59.999238 8, 0xFFFF, sum = 0
7773 18:06:59.999571 9, 0xFFFF, sum = 0
7774 18:07:00.002235 10, 0xFFFF, sum = 0
7775 18:07:00.002577 11, 0xFFFF, sum = 0
7776 18:07:00.005324 12, 0xFFFF, sum = 0
7777 18:07:00.005666 13, 0xFFFF, sum = 0
7778 18:07:00.008971 14, 0x0, sum = 1
7779 18:07:00.009501 15, 0x0, sum = 2
7780 18:07:00.012572 16, 0x0, sum = 3
7781 18:07:00.013020 17, 0x0, sum = 4
7782 18:07:00.013290 best_step = 15
7783 18:07:00.015622
7784 18:07:00.015938 ==
7785 18:07:00.018940 Dram Type= 6, Freq= 0, CH_0, rank 0
7786 18:07:00.022052 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7787 18:07:00.022497 ==
7788 18:07:00.022875 RX Vref Scan: 1
7789 18:07:00.023241
7790 18:07:00.025774 Set Vref Range= 24 -> 127
7791 18:07:00.026203
7792 18:07:00.028825 RX Vref 24 -> 127, step: 1
7793 18:07:00.029317
7794 18:07:00.032388 RX Delay 11 -> 252, step: 4
7795 18:07:00.032840
7796 18:07:00.035391 Set Vref, RX VrefLevel [Byte0]: 24
7797 18:07:00.038900 [Byte1]: 24
7798 18:07:00.039401
7799 18:07:00.041979 Set Vref, RX VrefLevel [Byte0]: 25
7800 18:07:00.045678 [Byte1]: 25
7801 18:07:00.046129
7802 18:07:00.048751 Set Vref, RX VrefLevel [Byte0]: 26
7803 18:07:00.052307 [Byte1]: 26
7804 18:07:00.055597
7805 18:07:00.056046 Set Vref, RX VrefLevel [Byte0]: 27
7806 18:07:00.059079 [Byte1]: 27
7807 18:07:00.063418
7808 18:07:00.063785 Set Vref, RX VrefLevel [Byte0]: 28
7809 18:07:00.066711 [Byte1]: 28
7810 18:07:00.071175
7811 18:07:00.071590 Set Vref, RX VrefLevel [Byte0]: 29
7812 18:07:00.074259 [Byte1]: 29
7813 18:07:00.078690
7814 18:07:00.079123 Set Vref, RX VrefLevel [Byte0]: 30
7815 18:07:00.081634 [Byte1]: 30
7816 18:07:00.086065
7817 18:07:00.086529 Set Vref, RX VrefLevel [Byte0]: 31
7818 18:07:00.089669 [Byte1]: 31
7819 18:07:00.093943
7820 18:07:00.094457 Set Vref, RX VrefLevel [Byte0]: 32
7821 18:07:00.097071 [Byte1]: 32
7822 18:07:00.101799
7823 18:07:00.102253 Set Vref, RX VrefLevel [Byte0]: 33
7824 18:07:00.104494 [Byte1]: 33
7825 18:07:00.108854
7826 18:07:00.109316 Set Vref, RX VrefLevel [Byte0]: 34
7827 18:07:00.112612 [Byte1]: 34
7828 18:07:00.116394
7829 18:07:00.116724 Set Vref, RX VrefLevel [Byte0]: 35
7830 18:07:00.120003 [Byte1]: 35
7831 18:07:00.124516
7832 18:07:00.124836 Set Vref, RX VrefLevel [Byte0]: 36
7833 18:07:00.127560 [Byte1]: 36
7834 18:07:00.131770
7835 18:07:00.132086 Set Vref, RX VrefLevel [Byte0]: 37
7836 18:07:00.135300 [Byte1]: 37
7837 18:07:00.139377
7838 18:07:00.139694 Set Vref, RX VrefLevel [Byte0]: 38
7839 18:07:00.143015 [Byte1]: 38
7840 18:07:00.147495
7841 18:07:00.147813 Set Vref, RX VrefLevel [Byte0]: 39
7842 18:07:00.150540 [Byte1]: 39
7843 18:07:00.154831
7844 18:07:00.155160 Set Vref, RX VrefLevel [Byte0]: 40
7845 18:07:00.158039 [Byte1]: 40
7846 18:07:00.162464
7847 18:07:00.162901 Set Vref, RX VrefLevel [Byte0]: 41
7848 18:07:00.165486 [Byte1]: 41
7849 18:07:00.170059
7850 18:07:00.170496 Set Vref, RX VrefLevel [Byte0]: 42
7851 18:07:00.172949 [Byte1]: 42
7852 18:07:00.177756
7853 18:07:00.178197 Set Vref, RX VrefLevel [Byte0]: 43
7854 18:07:00.180877 [Byte1]: 43
7855 18:07:00.185028
7856 18:07:00.185511 Set Vref, RX VrefLevel [Byte0]: 44
7857 18:07:00.188530 [Byte1]: 44
7858 18:07:00.193042
7859 18:07:00.193394 Set Vref, RX VrefLevel [Byte0]: 45
7860 18:07:00.195873 [Byte1]: 45
7861 18:07:00.200428
7862 18:07:00.200804 Set Vref, RX VrefLevel [Byte0]: 46
7863 18:07:00.203935 [Byte1]: 46
7864 18:07:00.207958
7865 18:07:00.208282 Set Vref, RX VrefLevel [Byte0]: 47
7866 18:07:00.211261 [Byte1]: 47
7867 18:07:00.215680
7868 18:07:00.216120 Set Vref, RX VrefLevel [Byte0]: 48
7869 18:07:00.218578 [Byte1]: 48
7870 18:07:00.222986
7871 18:07:00.223443 Set Vref, RX VrefLevel [Byte0]: 49
7872 18:07:00.226440 [Byte1]: 49
7873 18:07:00.231147
7874 18:07:00.231599 Set Vref, RX VrefLevel [Byte0]: 50
7875 18:07:00.234416 [Byte1]: 50
7876 18:07:00.238535
7877 18:07:00.238946 Set Vref, RX VrefLevel [Byte0]: 51
7878 18:07:00.242306 [Byte1]: 51
7879 18:07:00.246289
7880 18:07:00.246702 Set Vref, RX VrefLevel [Byte0]: 52
7881 18:07:00.249428 [Byte1]: 52
7882 18:07:00.253734
7883 18:07:00.254243 Set Vref, RX VrefLevel [Byte0]: 53
7884 18:07:00.257326 [Byte1]: 53
7885 18:07:00.261341
7886 18:07:00.261803 Set Vref, RX VrefLevel [Byte0]: 54
7887 18:07:00.264940 [Byte1]: 54
7888 18:07:00.269081
7889 18:07:00.269494 Set Vref, RX VrefLevel [Byte0]: 55
7890 18:07:00.272317 [Byte1]: 55
7891 18:07:00.276835
7892 18:07:00.277455 Set Vref, RX VrefLevel [Byte0]: 56
7893 18:07:00.280075 [Byte1]: 56
7894 18:07:00.284415
7895 18:07:00.285044 Set Vref, RX VrefLevel [Byte0]: 57
7896 18:07:00.287534 [Byte1]: 57
7897 18:07:00.291737
7898 18:07:00.292217 Set Vref, RX VrefLevel [Byte0]: 58
7899 18:07:00.294922 [Byte1]: 58
7900 18:07:00.299138
7901 18:07:00.299787 Set Vref, RX VrefLevel [Byte0]: 59
7902 18:07:00.302537 [Byte1]: 59
7903 18:07:00.307039
7904 18:07:00.307643 Set Vref, RX VrefLevel [Byte0]: 60
7905 18:07:00.310559 [Byte1]: 60
7906 18:07:00.314582
7907 18:07:00.314998 Set Vref, RX VrefLevel [Byte0]: 61
7908 18:07:00.318266 [Byte1]: 61
7909 18:07:00.322106
7910 18:07:00.322557 Set Vref, RX VrefLevel [Byte0]: 62
7911 18:07:00.325639 [Byte1]: 62
7912 18:07:00.330040
7913 18:07:00.330597 Set Vref, RX VrefLevel [Byte0]: 63
7914 18:07:00.333088 [Byte1]: 63
7915 18:07:00.337461
7916 18:07:00.337869 Set Vref, RX VrefLevel [Byte0]: 64
7917 18:07:00.340576 [Byte1]: 64
7918 18:07:00.345278
7919 18:07:00.345766 Set Vref, RX VrefLevel [Byte0]: 65
7920 18:07:00.348391 [Byte1]: 65
7921 18:07:00.352697
7922 18:07:00.353234 Set Vref, RX VrefLevel [Byte0]: 66
7923 18:07:00.355926 [Byte1]: 66
7924 18:07:00.360296
7925 18:07:00.360733 Set Vref, RX VrefLevel [Byte0]: 67
7926 18:07:00.363942 [Byte1]: 67
7927 18:07:00.368304
7928 18:07:00.368737 Set Vref, RX VrefLevel [Byte0]: 68
7929 18:07:00.371232 [Byte1]: 68
7930 18:07:00.375459
7931 18:07:00.375846 Set Vref, RX VrefLevel [Byte0]: 69
7932 18:07:00.378449 [Byte1]: 69
7933 18:07:00.383148
7934 18:07:00.383550 Set Vref, RX VrefLevel [Byte0]: 70
7935 18:07:00.386459 [Byte1]: 70
7936 18:07:00.390636
7937 18:07:00.390925 Set Vref, RX VrefLevel [Byte0]: 71
7938 18:07:00.394233 [Byte1]: 71
7939 18:07:00.398528
7940 18:07:00.398926 Set Vref, RX VrefLevel [Byte0]: 72
7941 18:07:00.401418 [Byte1]: 72
7942 18:07:00.405668
7943 18:07:00.405989 Set Vref, RX VrefLevel [Byte0]: 73
7944 18:07:00.409377 [Byte1]: 73
7945 18:07:00.413736
7946 18:07:00.414173 Set Vref, RX VrefLevel [Byte0]: 74
7947 18:07:00.416799 [Byte1]: 74
7948 18:07:00.421097
7949 18:07:00.421393 Set Vref, RX VrefLevel [Byte0]: 75
7950 18:07:00.424157 [Byte1]: 75
7951 18:07:00.429241
7952 18:07:00.429535 Final RX Vref Byte 0 = 62 to rank0
7953 18:07:00.432235 Final RX Vref Byte 1 = 62 to rank0
7954 18:07:00.435329 Final RX Vref Byte 0 = 62 to rank1
7955 18:07:00.438930 Final RX Vref Byte 1 = 62 to rank1==
7956 18:07:00.442429 Dram Type= 6, Freq= 0, CH_0, rank 0
7957 18:07:00.449112 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7958 18:07:00.449497 ==
7959 18:07:00.449756 DQS Delay:
7960 18:07:00.449992 DQS0 = 0, DQS1 = 0
7961 18:07:00.452131 DQM Delay:
7962 18:07:00.452417 DQM0 = 129, DQM1 = 122
7963 18:07:00.455743 DQ Delay:
7964 18:07:00.459063 DQ0 =130, DQ1 =132, DQ2 =126, DQ3 =126
7965 18:07:00.462289 DQ4 =132, DQ5 =118, DQ6 =136, DQ7 =138
7966 18:07:00.465445 DQ8 =112, DQ9 =110, DQ10 =122, DQ11 =116
7967 18:07:00.469243 DQ12 =128, DQ13 =128, DQ14 =132, DQ15 =134
7968 18:07:00.469544
7969 18:07:00.469851
7970 18:07:00.470137
7971 18:07:00.472327 [DramC_TX_OE_Calibration] TA2
7972 18:07:00.475688 Original DQ_B0 (3 6) =30, OEN = 27
7973 18:07:00.478992 Original DQ_B1 (3 6) =30, OEN = 27
7974 18:07:00.482851 24, 0x0, End_B0=24 End_B1=24
7975 18:07:00.483158 25, 0x0, End_B0=25 End_B1=25
7976 18:07:00.485803 26, 0x0, End_B0=26 End_B1=26
7977 18:07:00.488905 27, 0x0, End_B0=27 End_B1=27
7978 18:07:00.492474 28, 0x0, End_B0=28 End_B1=28
7979 18:07:00.492787 29, 0x0, End_B0=29 End_B1=29
7980 18:07:00.495848 30, 0x0, End_B0=30 End_B1=30
7981 18:07:00.498751 31, 0x4141, End_B0=30 End_B1=30
7982 18:07:00.502331 Byte0 end_step=30 best_step=27
7983 18:07:00.505665 Byte1 end_step=30 best_step=27
7984 18:07:00.509378 Byte0 TX OE(2T, 0.5T) = (3, 3)
7985 18:07:00.509684 Byte1 TX OE(2T, 0.5T) = (3, 3)
7986 18:07:00.509990
7987 18:07:00.510279
7988 18:07:00.518964 [DQSOSCAuto] RK0, (LSB)MR18= 0x1004, (MSB)MR19= 0x303, tDQSOscB0 = 408 ps tDQSOscB1 = 401 ps
7989 18:07:00.522653 CH0 RK0: MR19=303, MR18=1004
7990 18:07:00.525549 CH0_RK0: MR19=0x303, MR18=0x1004, DQSOSC=401, MR23=63, INC=22, DEC=15
7991 18:07:00.528917
7992 18:07:00.532304 ----->DramcWriteLeveling(PI) begin...
7993 18:07:00.532596 ==
7994 18:07:00.535413 Dram Type= 6, Freq= 0, CH_0, rank 1
7995 18:07:00.538853 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7996 18:07:00.539189 ==
7997 18:07:00.542438 Write leveling (Byte 0): 34 => 34
7998 18:07:00.545455 Write leveling (Byte 1): 26 => 26
7999 18:07:00.549002 DramcWriteLeveling(PI) end<-----
8000 18:07:00.549299
8001 18:07:00.549553 ==
8002 18:07:00.552329 Dram Type= 6, Freq= 0, CH_0, rank 1
8003 18:07:00.555795 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8004 18:07:00.556090 ==
8005 18:07:00.558917 [Gating] SW mode calibration
8006 18:07:00.565598 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8007 18:07:00.572069 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8008 18:07:00.575066 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8009 18:07:00.578801 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8010 18:07:00.585391 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8011 18:07:00.589179 1 4 12 | B1->B0 | 2323 3333 | 0 1 | (0 0) (1 1)
8012 18:07:00.592241 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8013 18:07:00.599204 1 4 20 | B1->B0 | 2726 3434 | 1 1 | (0 0) (1 1)
8014 18:07:00.601852 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8015 18:07:00.605691 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8016 18:07:00.609139 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8017 18:07:00.615773 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8018 18:07:00.618789 1 5 8 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
8019 18:07:00.622376 1 5 12 | B1->B0 | 3434 2828 | 1 1 | (1 1) (1 0)
8020 18:07:00.628998 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
8021 18:07:00.632005 1 5 20 | B1->B0 | 3030 2323 | 0 0 | (0 1) (0 0)
8022 18:07:00.635727 1 5 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8023 18:07:00.641977 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8024 18:07:00.645570 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8025 18:07:00.648680 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8026 18:07:00.655246 1 6 8 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
8027 18:07:00.658691 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8028 18:07:00.662193 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8029 18:07:00.668717 1 6 20 | B1->B0 | 3939 4646 | 1 0 | (0 0) (0 0)
8030 18:07:00.672085 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8031 18:07:00.675673 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8032 18:07:00.682487 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8033 18:07:00.685924 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8034 18:07:00.688903 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8035 18:07:00.691976 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8036 18:07:00.699041 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8037 18:07:00.702294 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8038 18:07:00.705595 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8039 18:07:00.712526 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8040 18:07:00.715804 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8041 18:07:00.718856 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8042 18:07:00.725426 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8043 18:07:00.728709 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8044 18:07:00.732255 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8045 18:07:00.738835 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8046 18:07:00.742524 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8047 18:07:00.745519 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8048 18:07:00.752128 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8049 18:07:00.755314 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8050 18:07:00.758580 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8051 18:07:00.765445 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8052 18:07:00.765522 Total UI for P1: 0, mck2ui 16
8053 18:07:00.771991 best dqsien dly found for B0: ( 1, 9, 6)
8054 18:07:00.775578 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8055 18:07:00.778979 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8056 18:07:00.782111 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8057 18:07:00.788799 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8058 18:07:00.791917 Total UI for P1: 0, mck2ui 16
8059 18:07:00.795534 best dqsien dly found for B1: ( 1, 9, 20)
8060 18:07:00.798605 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8061 18:07:00.802234 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
8062 18:07:00.802314
8063 18:07:00.805302 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8064 18:07:00.809085 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
8065 18:07:00.812040 [Gating] SW calibration Done
8066 18:07:00.812116 ==
8067 18:07:00.815634 Dram Type= 6, Freq= 0, CH_0, rank 1
8068 18:07:00.818775 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8069 18:07:00.818860 ==
8070 18:07:00.822392 RX Vref Scan: 0
8071 18:07:00.822499
8072 18:07:00.822607 RX Vref 0 -> 0, step: 1
8073 18:07:00.825440
8074 18:07:00.825548 RX Delay 0 -> 252, step: 8
8075 18:07:00.828815 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8076 18:07:00.835925 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8077 18:07:00.839441 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8078 18:07:00.842307 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8079 18:07:00.845603 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8080 18:07:00.848948 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8081 18:07:00.855375 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8082 18:07:00.859184 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8083 18:07:00.862233 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8084 18:07:00.865721 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8085 18:07:00.868921 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8086 18:07:00.875495 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8087 18:07:00.878710 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8088 18:07:00.882341 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8089 18:07:00.885323 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8090 18:07:00.888985 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8091 18:07:00.892010 ==
8092 18:07:00.892118 Dram Type= 6, Freq= 0, CH_0, rank 1
8093 18:07:00.898791 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8094 18:07:00.898873 ==
8095 18:07:00.898936 DQS Delay:
8096 18:07:00.902407 DQS0 = 0, DQS1 = 0
8097 18:07:00.902488 DQM Delay:
8098 18:07:00.905993 DQM0 = 130, DQM1 = 125
8099 18:07:00.906074 DQ Delay:
8100 18:07:00.908963 DQ0 =131, DQ1 =131, DQ2 =127, DQ3 =127
8101 18:07:00.912493 DQ4 =131, DQ5 =119, DQ6 =139, DQ7 =139
8102 18:07:00.915519 DQ8 =119, DQ9 =115, DQ10 =123, DQ11 =119
8103 18:07:00.919133 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =131
8104 18:07:00.919214
8105 18:07:00.919278
8106 18:07:00.919336 ==
8107 18:07:00.922365 Dram Type= 6, Freq= 0, CH_0, rank 1
8108 18:07:00.929012 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8109 18:07:00.929094 ==
8110 18:07:00.929158
8111 18:07:00.929218
8112 18:07:00.929275 TX Vref Scan disable
8113 18:07:00.932518 == TX Byte 0 ==
8114 18:07:00.935588 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8115 18:07:00.939180 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8116 18:07:00.942240 == TX Byte 1 ==
8117 18:07:00.945905 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8118 18:07:00.948876 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8119 18:07:00.952350 ==
8120 18:07:00.955855 Dram Type= 6, Freq= 0, CH_0, rank 1
8121 18:07:00.958785 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8122 18:07:00.958875 ==
8123 18:07:00.973356
8124 18:07:00.976586 TX Vref early break, caculate TX vref
8125 18:07:00.979986 TX Vref=16, minBit 8, minWin=22, winSum=375
8126 18:07:00.983258 TX Vref=18, minBit 9, minWin=22, winSum=375
8127 18:07:00.986682 TX Vref=20, minBit 8, minWin=23, winSum=387
8128 18:07:00.990127 TX Vref=22, minBit 9, minWin=23, winSum=398
8129 18:07:00.993473 TX Vref=24, minBit 9, minWin=23, winSum=403
8130 18:07:01.000007 TX Vref=26, minBit 3, minWin=25, winSum=415
8131 18:07:01.003498 TX Vref=28, minBit 3, minWin=25, winSum=418
8132 18:07:01.006690 TX Vref=30, minBit 10, minWin=25, winSum=420
8133 18:07:01.010285 TX Vref=32, minBit 2, minWin=25, winSum=411
8134 18:07:01.013883 TX Vref=34, minBit 8, minWin=24, winSum=403
8135 18:07:01.016829 TX Vref=36, minBit 10, minWin=23, winSum=398
8136 18:07:01.023523 [TxChooseVref] Worse bit 10, Min win 25, Win sum 420, Final Vref 30
8137 18:07:01.023603
8138 18:07:01.026643 Final TX Range 0 Vref 30
8139 18:07:01.026718
8140 18:07:01.026778 ==
8141 18:07:01.030308 Dram Type= 6, Freq= 0, CH_0, rank 1
8142 18:07:01.033371 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8143 18:07:01.033451 ==
8144 18:07:01.033514
8145 18:07:01.033571
8146 18:07:01.036958 TX Vref Scan disable
8147 18:07:01.043834 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8148 18:07:01.043913 == TX Byte 0 ==
8149 18:07:01.046768 u2DelayCellOfst[0]=14 cells (4 PI)
8150 18:07:01.050565 u2DelayCellOfst[1]=21 cells (6 PI)
8151 18:07:01.053515 u2DelayCellOfst[2]=10 cells (3 PI)
8152 18:07:01.056950 u2DelayCellOfst[3]=14 cells (4 PI)
8153 18:07:01.060187 u2DelayCellOfst[4]=10 cells (3 PI)
8154 18:07:01.063659 u2DelayCellOfst[5]=0 cells (0 PI)
8155 18:07:01.067021 u2DelayCellOfst[6]=21 cells (6 PI)
8156 18:07:01.070682 u2DelayCellOfst[7]=21 cells (6 PI)
8157 18:07:01.073983 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
8158 18:07:01.077329 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8159 18:07:01.080808 == TX Byte 1 ==
8160 18:07:01.080883 u2DelayCellOfst[8]=0 cells (0 PI)
8161 18:07:01.083773 u2DelayCellOfst[9]=0 cells (0 PI)
8162 18:07:01.087412 u2DelayCellOfst[10]=7 cells (2 PI)
8163 18:07:01.090664 u2DelayCellOfst[11]=0 cells (0 PI)
8164 18:07:01.094273 u2DelayCellOfst[12]=10 cells (3 PI)
8165 18:07:01.097391 u2DelayCellOfst[13]=10 cells (3 PI)
8166 18:07:01.100414 u2DelayCellOfst[14]=14 cells (4 PI)
8167 18:07:01.103760 u2DelayCellOfst[15]=10 cells (3 PI)
8168 18:07:01.107135 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8169 18:07:01.114036 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8170 18:07:01.114124 DramC Write-DBI on
8171 18:07:01.114187 ==
8172 18:07:01.117136 Dram Type= 6, Freq= 0, CH_0, rank 1
8173 18:07:01.120814 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8174 18:07:01.123770 ==
8175 18:07:01.123868
8176 18:07:01.123956
8177 18:07:01.124041 TX Vref Scan disable
8178 18:07:01.127397 == TX Byte 0 ==
8179 18:07:01.130420 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
8180 18:07:01.133981 == TX Byte 1 ==
8181 18:07:01.137147 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8182 18:07:01.140740 DramC Write-DBI off
8183 18:07:01.140819
8184 18:07:01.140882 [DATLAT]
8185 18:07:01.140940 Freq=1600, CH0 RK1
8186 18:07:01.141036
8187 18:07:01.143710 DATLAT Default: 0xf
8188 18:07:01.143788 0, 0xFFFF, sum = 0
8189 18:07:01.146732 1, 0xFFFF, sum = 0
8190 18:07:01.150247 2, 0xFFFF, sum = 0
8191 18:07:01.150351 3, 0xFFFF, sum = 0
8192 18:07:01.154086 4, 0xFFFF, sum = 0
8193 18:07:01.154160 5, 0xFFFF, sum = 0
8194 18:07:01.156954 6, 0xFFFF, sum = 0
8195 18:07:01.157064 7, 0xFFFF, sum = 0
8196 18:07:01.160495 8, 0xFFFF, sum = 0
8197 18:07:01.160567 9, 0xFFFF, sum = 0
8198 18:07:01.164112 10, 0xFFFF, sum = 0
8199 18:07:01.164219 11, 0xFFFF, sum = 0
8200 18:07:01.166952 12, 0xFFFF, sum = 0
8201 18:07:01.167054 13, 0xFFFF, sum = 0
8202 18:07:01.170437 14, 0x0, sum = 1
8203 18:07:01.170514 15, 0x0, sum = 2
8204 18:07:01.173976 16, 0x0, sum = 3
8205 18:07:01.174051 17, 0x0, sum = 4
8206 18:07:01.176912 best_step = 15
8207 18:07:01.177045
8208 18:07:01.177127 ==
8209 18:07:01.180622 Dram Type= 6, Freq= 0, CH_0, rank 1
8210 18:07:01.183665 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8211 18:07:01.183752 ==
8212 18:07:01.183833 RX Vref Scan: 0
8213 18:07:01.187034
8214 18:07:01.187133 RX Vref 0 -> 0, step: 1
8215 18:07:01.187214
8216 18:07:01.190544 RX Delay 11 -> 252, step: 4
8217 18:07:01.194050 iDelay=191, Bit 0, Center 126 (71 ~ 182) 112
8218 18:07:01.200547 iDelay=191, Bit 1, Center 130 (75 ~ 186) 112
8219 18:07:01.203917 iDelay=191, Bit 2, Center 122 (67 ~ 178) 112
8220 18:07:01.206975 iDelay=191, Bit 3, Center 126 (71 ~ 182) 112
8221 18:07:01.210439 iDelay=191, Bit 4, Center 128 (75 ~ 182) 108
8222 18:07:01.213516 iDelay=191, Bit 5, Center 116 (63 ~ 170) 108
8223 18:07:01.220603 iDelay=191, Bit 6, Center 136 (83 ~ 190) 108
8224 18:07:01.223721 iDelay=191, Bit 7, Center 136 (83 ~ 190) 108
8225 18:07:01.227347 iDelay=191, Bit 8, Center 112 (59 ~ 166) 108
8226 18:07:01.230289 iDelay=191, Bit 9, Center 112 (59 ~ 166) 108
8227 18:07:01.233746 iDelay=191, Bit 10, Center 122 (67 ~ 178) 112
8228 18:07:01.237325 iDelay=191, Bit 11, Center 116 (63 ~ 170) 108
8229 18:07:01.244015 iDelay=191, Bit 12, Center 126 (75 ~ 178) 104
8230 18:07:01.246988 iDelay=191, Bit 13, Center 128 (75 ~ 182) 108
8231 18:07:01.250665 iDelay=191, Bit 14, Center 134 (79 ~ 190) 112
8232 18:07:01.253728 iDelay=191, Bit 15, Center 130 (75 ~ 186) 112
8233 18:07:01.253801 ==
8234 18:07:01.257413 Dram Type= 6, Freq= 0, CH_0, rank 1
8235 18:07:01.263876 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8236 18:07:01.263946 ==
8237 18:07:01.264005 DQS Delay:
8238 18:07:01.267277 DQS0 = 0, DQS1 = 0
8239 18:07:01.267357 DQM Delay:
8240 18:07:01.267419 DQM0 = 127, DQM1 = 122
8241 18:07:01.270929 DQ Delay:
8242 18:07:01.273947 DQ0 =126, DQ1 =130, DQ2 =122, DQ3 =126
8243 18:07:01.277394 DQ4 =128, DQ5 =116, DQ6 =136, DQ7 =136
8244 18:07:01.280809 DQ8 =112, DQ9 =112, DQ10 =122, DQ11 =116
8245 18:07:01.283833 DQ12 =126, DQ13 =128, DQ14 =134, DQ15 =130
8246 18:07:01.283945
8247 18:07:01.284048
8248 18:07:01.284141
8249 18:07:01.287407 [DramC_TX_OE_Calibration] TA2
8250 18:07:01.290803 Original DQ_B0 (3 6) =30, OEN = 27
8251 18:07:01.293904 Original DQ_B1 (3 6) =30, OEN = 27
8252 18:07:01.297419 24, 0x0, End_B0=24 End_B1=24
8253 18:07:01.297508 25, 0x0, End_B0=25 End_B1=25
8254 18:07:01.300796 26, 0x0, End_B0=26 End_B1=26
8255 18:07:01.303847 27, 0x0, End_B0=27 End_B1=27
8256 18:07:01.307076 28, 0x0, End_B0=28 End_B1=28
8257 18:07:01.310598 29, 0x0, End_B0=29 End_B1=29
8258 18:07:01.310679 30, 0x0, End_B0=30 End_B1=30
8259 18:07:01.314028 31, 0x4545, End_B0=30 End_B1=30
8260 18:07:01.316912 Byte0 end_step=30 best_step=27
8261 18:07:01.320422 Byte1 end_step=30 best_step=27
8262 18:07:01.323717 Byte0 TX OE(2T, 0.5T) = (3, 3)
8263 18:07:01.327171 Byte1 TX OE(2T, 0.5T) = (3, 3)
8264 18:07:01.327262
8265 18:07:01.327339
8266 18:07:01.333945 [DQSOSCAuto] RK1, (LSB)MR18= 0x160c, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 398 ps
8267 18:07:01.336992 CH0 RK1: MR19=303, MR18=160C
8268 18:07:01.343902 CH0_RK1: MR19=0x303, MR18=0x160C, DQSOSC=398, MR23=63, INC=23, DEC=15
8269 18:07:01.347619 [RxdqsGatingPostProcess] freq 1600
8270 18:07:01.350498 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8271 18:07:01.354100 best DQS0 dly(2T, 0.5T) = (1, 1)
8272 18:07:01.357133 best DQS1 dly(2T, 0.5T) = (1, 1)
8273 18:07:01.360887 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8274 18:07:01.363837 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8275 18:07:01.367498 best DQS0 dly(2T, 0.5T) = (1, 1)
8276 18:07:01.371073 best DQS1 dly(2T, 0.5T) = (1, 1)
8277 18:07:01.373953 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8278 18:07:01.377598 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8279 18:07:01.380850 Pre-setting of DQS Precalculation
8280 18:07:01.384446 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8281 18:07:01.384536 ==
8282 18:07:01.387443 Dram Type= 6, Freq= 0, CH_1, rank 0
8283 18:07:01.390419 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8284 18:07:01.390504 ==
8285 18:07:01.397353 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8286 18:07:01.400367 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8287 18:07:01.407568 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8288 18:07:01.410313 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8289 18:07:01.420354 [CA 0] Center 42 (13~71) winsize 59
8290 18:07:01.423964 [CA 1] Center 42 (13~71) winsize 59
8291 18:07:01.427095 [CA 2] Center 37 (8~66) winsize 59
8292 18:07:01.430623 [CA 3] Center 36 (7~66) winsize 60
8293 18:07:01.434054 [CA 4] Center 37 (8~66) winsize 59
8294 18:07:01.436758 [CA 5] Center 36 (7~66) winsize 60
8295 18:07:01.437059
8296 18:07:01.440429 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8297 18:07:01.440622
8298 18:07:01.443884 [CATrainingPosCal] consider 1 rank data
8299 18:07:01.446918 u2DelayCellTimex100 = 275/100 ps
8300 18:07:01.450257 CA0 delay=42 (13~71),Diff = 6 PI (21 cell)
8301 18:07:01.457063 CA1 delay=42 (13~71),Diff = 6 PI (21 cell)
8302 18:07:01.460472 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8303 18:07:01.463639 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8304 18:07:01.467016 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
8305 18:07:01.470720 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8306 18:07:01.471131
8307 18:07:01.474034 CA PerBit enable=1, Macro0, CA PI delay=36
8308 18:07:01.474457
8309 18:07:01.477570 [CBTSetCACLKResult] CA Dly = 36
8310 18:07:01.477984 CS Dly: 8 (0~39)
8311 18:07:01.484128 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8312 18:07:01.487037 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8313 18:07:01.487556 ==
8314 18:07:01.490584 Dram Type= 6, Freq= 0, CH_1, rank 1
8315 18:07:01.494114 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8316 18:07:01.494535 ==
8317 18:07:01.500583 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8318 18:07:01.504306 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8319 18:07:01.510944 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8320 18:07:01.513731 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8321 18:07:01.523631 [CA 0] Center 43 (14~73) winsize 60
8322 18:07:01.527161 [CA 1] Center 43 (14~72) winsize 59
8323 18:07:01.530485 [CA 2] Center 38 (9~67) winsize 59
8324 18:07:01.534068 [CA 3] Center 37 (8~66) winsize 59
8325 18:07:01.537250 [CA 4] Center 38 (9~68) winsize 60
8326 18:07:01.540154 [CA 5] Center 36 (7~66) winsize 60
8327 18:07:01.540559
8328 18:07:01.543717 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8329 18:07:01.544122
8330 18:07:01.547201 [CATrainingPosCal] consider 2 rank data
8331 18:07:01.550357 u2DelayCellTimex100 = 275/100 ps
8332 18:07:01.553965 CA0 delay=42 (14~71),Diff = 6 PI (21 cell)
8333 18:07:01.560758 CA1 delay=42 (14~71),Diff = 6 PI (21 cell)
8334 18:07:01.563577 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8335 18:07:01.567515 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8336 18:07:01.570321 CA4 delay=37 (9~66),Diff = 1 PI (3 cell)
8337 18:07:01.573923 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8338 18:07:01.574329
8339 18:07:01.576896 CA PerBit enable=1, Macro0, CA PI delay=36
8340 18:07:01.577340
8341 18:07:01.580127 [CBTSetCACLKResult] CA Dly = 36
8342 18:07:01.583880 CS Dly: 10 (0~44)
8343 18:07:01.587137 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8344 18:07:01.590121 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8345 18:07:01.590530
8346 18:07:01.593647 ----->DramcWriteLeveling(PI) begin...
8347 18:07:01.594059 ==
8348 18:07:01.597108 Dram Type= 6, Freq= 0, CH_1, rank 0
8349 18:07:01.600734 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8350 18:07:01.601193 ==
8351 18:07:01.603613 Write leveling (Byte 0): 26 => 26
8352 18:07:01.606936 Write leveling (Byte 1): 27 => 27
8353 18:07:01.610361 DramcWriteLeveling(PI) end<-----
8354 18:07:01.610767
8355 18:07:01.611082 ==
8356 18:07:01.613985 Dram Type= 6, Freq= 0, CH_1, rank 0
8357 18:07:01.620482 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8358 18:07:01.620916 ==
8359 18:07:01.621320 [Gating] SW mode calibration
8360 18:07:01.630611 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8361 18:07:01.633500 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8362 18:07:01.637476 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8363 18:07:01.643892 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8364 18:07:01.646829 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8365 18:07:01.650488 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8366 18:07:01.656967 1 4 16 | B1->B0 | 2f2f 2929 | 0 0 | (0 0) (1 1)
8367 18:07:01.660678 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8368 18:07:01.663583 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8369 18:07:01.670390 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8370 18:07:01.674028 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8371 18:07:01.677609 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8372 18:07:01.683820 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8373 18:07:01.687132 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8374 18:07:01.690741 1 5 16 | B1->B0 | 2828 3232 | 1 0 | (1 0) (0 1)
8375 18:07:01.697107 1 5 20 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8376 18:07:01.700593 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8377 18:07:01.704208 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8378 18:07:01.707078 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8379 18:07:01.713819 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8380 18:07:01.717473 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8381 18:07:01.721081 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8382 18:07:01.727039 1 6 16 | B1->B0 | 3c3c 2f2f | 0 1 | (0 0) (0 0)
8383 18:07:01.730439 1 6 20 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
8384 18:07:01.734473 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8385 18:07:01.740947 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8386 18:07:01.744407 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8387 18:07:01.747437 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8388 18:07:01.754655 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8389 18:07:01.757662 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8390 18:07:01.761128 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8391 18:07:01.767969 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8392 18:07:01.770686 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8393 18:07:01.774364 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8394 18:07:01.781095 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8395 18:07:01.784399 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8396 18:07:01.787401 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8397 18:07:01.790723 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8398 18:07:01.797290 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8399 18:07:01.801139 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8400 18:07:01.804099 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8401 18:07:01.811224 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8402 18:07:01.814075 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8403 18:07:01.817610 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8404 18:07:01.824415 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8405 18:07:01.827620 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8406 18:07:01.831032 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8407 18:07:01.837382 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8408 18:07:01.837818 Total UI for P1: 0, mck2ui 16
8409 18:07:01.844060 best dqsien dly found for B0: ( 1, 9, 14)
8410 18:07:01.844485 Total UI for P1: 0, mck2ui 16
8411 18:07:01.851100 best dqsien dly found for B1: ( 1, 9, 16)
8412 18:07:01.854042 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8413 18:07:01.857559 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8414 18:07:01.858007
8415 18:07:01.860656 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8416 18:07:01.864237 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8417 18:07:01.867774 [Gating] SW calibration Done
8418 18:07:01.868200 ==
8419 18:07:01.870808 Dram Type= 6, Freq= 0, CH_1, rank 0
8420 18:07:01.874343 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8421 18:07:01.874792 ==
8422 18:07:01.877812 RX Vref Scan: 0
8423 18:07:01.878218
8424 18:07:01.878571 RX Vref 0 -> 0, step: 1
8425 18:07:01.878874
8426 18:07:01.880802 RX Delay 0 -> 252, step: 8
8427 18:07:01.884321 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8428 18:07:01.887663 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8429 18:07:01.894471 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8430 18:07:01.897340 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8431 18:07:01.900820 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8432 18:07:01.904290 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8433 18:07:01.907732 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
8434 18:07:01.914268 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8435 18:07:01.917831 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8436 18:07:01.920712 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8437 18:07:01.924121 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8438 18:07:01.927524 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8439 18:07:01.934054 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8440 18:07:01.937591 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8441 18:07:01.941107 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8442 18:07:01.944356 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8443 18:07:01.944763 ==
8444 18:07:01.947421 Dram Type= 6, Freq= 0, CH_1, rank 0
8445 18:07:01.954091 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8446 18:07:01.954501 ==
8447 18:07:01.954822 DQS Delay:
8448 18:07:01.957582 DQS0 = 0, DQS1 = 0
8449 18:07:01.958086 DQM Delay:
8450 18:07:01.958415 DQM0 = 133, DQM1 = 126
8451 18:07:01.960729 DQ Delay:
8452 18:07:01.964201 DQ0 =139, DQ1 =127, DQ2 =119, DQ3 =135
8453 18:07:01.967763 DQ4 =135, DQ5 =143, DQ6 =143, DQ7 =127
8454 18:07:01.970710 DQ8 =111, DQ9 =111, DQ10 =127, DQ11 =123
8455 18:07:01.974278 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8456 18:07:01.974686
8457 18:07:01.975008
8458 18:07:01.975306 ==
8459 18:07:01.977314 Dram Type= 6, Freq= 0, CH_1, rank 0
8460 18:07:01.980937 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8461 18:07:01.983856 ==
8462 18:07:01.984264
8463 18:07:01.984586
8464 18:07:01.984889 TX Vref Scan disable
8465 18:07:01.987311 == TX Byte 0 ==
8466 18:07:01.990932 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8467 18:07:01.994526 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8468 18:07:01.997424 == TX Byte 1 ==
8469 18:07:02.000947 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8470 18:07:02.004229 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8471 18:07:02.004639 ==
8472 18:07:02.007432 Dram Type= 6, Freq= 0, CH_1, rank 0
8473 18:07:02.014067 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8474 18:07:02.014484 ==
8475 18:07:02.026766
8476 18:07:02.030470 TX Vref early break, caculate TX vref
8477 18:07:02.033751 TX Vref=16, minBit 8, minWin=21, winSum=363
8478 18:07:02.036688 TX Vref=18, minBit 8, minWin=21, winSum=370
8479 18:07:02.040219 TX Vref=20, minBit 8, minWin=21, winSum=381
8480 18:07:02.043711 TX Vref=22, minBit 8, minWin=22, winSum=390
8481 18:07:02.046789 TX Vref=24, minBit 5, minWin=23, winSum=402
8482 18:07:02.053414 TX Vref=26, minBit 11, minWin=24, winSum=413
8483 18:07:02.057070 TX Vref=28, minBit 8, minWin=24, winSum=415
8484 18:07:02.060096 TX Vref=30, minBit 8, minWin=25, winSum=418
8485 18:07:02.063503 TX Vref=32, minBit 0, minWin=25, winSum=413
8486 18:07:02.066736 TX Vref=34, minBit 3, minWin=24, winSum=399
8487 18:07:02.070310 TX Vref=36, minBit 3, minWin=23, winSum=388
8488 18:07:02.076691 [TxChooseVref] Worse bit 8, Min win 25, Win sum 418, Final Vref 30
8489 18:07:02.077127
8490 18:07:02.080171 Final TX Range 0 Vref 30
8491 18:07:02.080582
8492 18:07:02.080909 ==
8493 18:07:02.083676 Dram Type= 6, Freq= 0, CH_1, rank 0
8494 18:07:02.086630 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8495 18:07:02.087041 ==
8496 18:07:02.087363
8497 18:07:02.087662
8498 18:07:02.090198 TX Vref Scan disable
8499 18:07:02.096542 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8500 18:07:02.096953 == TX Byte 0 ==
8501 18:07:02.100186 u2DelayCellOfst[0]=17 cells (5 PI)
8502 18:07:02.103691 u2DelayCellOfst[1]=14 cells (4 PI)
8503 18:07:02.106650 u2DelayCellOfst[2]=0 cells (0 PI)
8504 18:07:02.110240 u2DelayCellOfst[3]=7 cells (2 PI)
8505 18:07:02.113134 u2DelayCellOfst[4]=10 cells (3 PI)
8506 18:07:02.116633 u2DelayCellOfst[5]=21 cells (6 PI)
8507 18:07:02.119858 u2DelayCellOfst[6]=17 cells (5 PI)
8508 18:07:02.123501 u2DelayCellOfst[7]=7 cells (2 PI)
8509 18:07:02.126919 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8510 18:07:02.129971 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8511 18:07:02.133364 == TX Byte 1 ==
8512 18:07:02.136786 u2DelayCellOfst[8]=0 cells (0 PI)
8513 18:07:02.137233 u2DelayCellOfst[9]=7 cells (2 PI)
8514 18:07:02.140177 u2DelayCellOfst[10]=14 cells (4 PI)
8515 18:07:02.143202 u2DelayCellOfst[11]=10 cells (3 PI)
8516 18:07:02.146584 u2DelayCellOfst[12]=17 cells (5 PI)
8517 18:07:02.149793 u2DelayCellOfst[13]=17 cells (5 PI)
8518 18:07:02.153460 u2DelayCellOfst[14]=24 cells (7 PI)
8519 18:07:02.156738 u2DelayCellOfst[15]=21 cells (6 PI)
8520 18:07:02.160258 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8521 18:07:02.166873 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8522 18:07:02.167285 DramC Write-DBI on
8523 18:07:02.167611 ==
8524 18:07:02.169827 Dram Type= 6, Freq= 0, CH_1, rank 0
8525 18:07:02.173734 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8526 18:07:02.176473 ==
8527 18:07:02.176880
8528 18:07:02.177237
8529 18:07:02.177542 TX Vref Scan disable
8530 18:07:02.180328 == TX Byte 0 ==
8531 18:07:02.183321 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8532 18:07:02.186955 == TX Byte 1 ==
8533 18:07:02.190500 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8534 18:07:02.193705 DramC Write-DBI off
8535 18:07:02.194114
8536 18:07:02.194463 [DATLAT]
8537 18:07:02.194765 Freq=1600, CH1 RK0
8538 18:07:02.195086
8539 18:07:02.197026 DATLAT Default: 0xf
8540 18:07:02.197568 0, 0xFFFF, sum = 0
8541 18:07:02.200497 1, 0xFFFF, sum = 0
8542 18:07:02.200909 2, 0xFFFF, sum = 0
8543 18:07:02.203453 3, 0xFFFF, sum = 0
8544 18:07:02.206966 4, 0xFFFF, sum = 0
8545 18:07:02.207415 5, 0xFFFF, sum = 0
8546 18:07:02.210529 6, 0xFFFF, sum = 0
8547 18:07:02.210979 7, 0xFFFF, sum = 0
8548 18:07:02.213391 8, 0xFFFF, sum = 0
8549 18:07:02.213957 9, 0xFFFF, sum = 0
8550 18:07:02.217174 10, 0xFFFF, sum = 0
8551 18:07:02.217730 11, 0xFFFF, sum = 0
8552 18:07:02.220256 12, 0xFFFF, sum = 0
8553 18:07:02.220742 13, 0xFFFF, sum = 0
8554 18:07:02.223713 14, 0x0, sum = 1
8555 18:07:02.224274 15, 0x0, sum = 2
8556 18:07:02.227288 16, 0x0, sum = 3
8557 18:07:02.227715 17, 0x0, sum = 4
8558 18:07:02.230620 best_step = 15
8559 18:07:02.231052
8560 18:07:02.231373 ==
8561 18:07:02.233855 Dram Type= 6, Freq= 0, CH_1, rank 0
8562 18:07:02.236870 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8563 18:07:02.237454 ==
8564 18:07:02.237830 RX Vref Scan: 1
8565 18:07:02.238138
8566 18:07:02.240051 Set Vref Range= 24 -> 127
8567 18:07:02.240475
8568 18:07:02.243347 RX Vref 24 -> 127, step: 1
8569 18:07:02.243830
8570 18:07:02.246907 RX Delay 11 -> 252, step: 4
8571 18:07:02.247339
8572 18:07:02.249996 Set Vref, RX VrefLevel [Byte0]: 24
8573 18:07:02.253568 [Byte1]: 24
8574 18:07:02.254006
8575 18:07:02.257166 Set Vref, RX VrefLevel [Byte0]: 25
8576 18:07:02.259930 [Byte1]: 25
8577 18:07:02.260341
8578 18:07:02.263494 Set Vref, RX VrefLevel [Byte0]: 26
8579 18:07:02.267116 [Byte1]: 26
8580 18:07:02.270784
8581 18:07:02.271195 Set Vref, RX VrefLevel [Byte0]: 27
8582 18:07:02.273668 [Byte1]: 27
8583 18:07:02.278502
8584 18:07:02.278911 Set Vref, RX VrefLevel [Byte0]: 28
8585 18:07:02.282053 [Byte1]: 28
8586 18:07:02.285989
8587 18:07:02.286420 Set Vref, RX VrefLevel [Byte0]: 29
8588 18:07:02.289200 [Byte1]: 29
8589 18:07:02.293608
8590 18:07:02.294082 Set Vref, RX VrefLevel [Byte0]: 30
8591 18:07:02.299905 [Byte1]: 30
8592 18:07:02.300323
8593 18:07:02.303384 Set Vref, RX VrefLevel [Byte0]: 31
8594 18:07:02.307015 [Byte1]: 31
8595 18:07:02.307425
8596 18:07:02.310347 Set Vref, RX VrefLevel [Byte0]: 32
8597 18:07:02.313108 [Byte1]: 32
8598 18:07:02.313531
8599 18:07:02.316663 Set Vref, RX VrefLevel [Byte0]: 33
8600 18:07:02.319769 [Byte1]: 33
8601 18:07:02.323936
8602 18:07:02.324340 Set Vref, RX VrefLevel [Byte0]: 34
8603 18:07:02.327445 [Byte1]: 34
8604 18:07:02.331681
8605 18:07:02.332101 Set Vref, RX VrefLevel [Byte0]: 35
8606 18:07:02.334666 [Byte1]: 35
8607 18:07:02.339500
8608 18:07:02.339905 Set Vref, RX VrefLevel [Byte0]: 36
8609 18:07:02.342141 [Byte1]: 36
8610 18:07:02.346936
8611 18:07:02.347358 Set Vref, RX VrefLevel [Byte0]: 37
8612 18:07:02.349949 [Byte1]: 37
8613 18:07:02.354946
8614 18:07:02.355382 Set Vref, RX VrefLevel [Byte0]: 38
8615 18:07:02.357437 [Byte1]: 38
8616 18:07:02.361854
8617 18:07:02.362277 Set Vref, RX VrefLevel [Byte0]: 39
8618 18:07:02.365381 [Byte1]: 39
8619 18:07:02.369536
8620 18:07:02.370083 Set Vref, RX VrefLevel [Byte0]: 40
8621 18:07:02.372875 [Byte1]: 40
8622 18:07:02.377033
8623 18:07:02.377453 Set Vref, RX VrefLevel [Byte0]: 41
8624 18:07:02.380702 [Byte1]: 41
8625 18:07:02.384889
8626 18:07:02.385343 Set Vref, RX VrefLevel [Byte0]: 42
8627 18:07:02.387957 [Byte1]: 42
8628 18:07:02.392644
8629 18:07:02.393105 Set Vref, RX VrefLevel [Byte0]: 43
8630 18:07:02.395465 [Byte1]: 43
8631 18:07:02.400269
8632 18:07:02.400676 Set Vref, RX VrefLevel [Byte0]: 44
8633 18:07:02.403228 [Byte1]: 44
8634 18:07:02.407696
8635 18:07:02.408243 Set Vref, RX VrefLevel [Byte0]: 45
8636 18:07:02.411493 [Byte1]: 45
8637 18:07:02.415145
8638 18:07:02.415620 Set Vref, RX VrefLevel [Byte0]: 46
8639 18:07:02.418723 [Byte1]: 46
8640 18:07:02.423129
8641 18:07:02.423659 Set Vref, RX VrefLevel [Byte0]: 47
8642 18:07:02.426433 [Byte1]: 47
8643 18:07:02.430579
8644 18:07:02.431017 Set Vref, RX VrefLevel [Byte0]: 48
8645 18:07:02.434121 [Byte1]: 48
8646 18:07:02.438179
8647 18:07:02.438718 Set Vref, RX VrefLevel [Byte0]: 49
8648 18:07:02.441254 [Byte1]: 49
8649 18:07:02.445826
8650 18:07:02.446366 Set Vref, RX VrefLevel [Byte0]: 50
8651 18:07:02.449367 [Byte1]: 50
8652 18:07:02.453392
8653 18:07:02.453812 Set Vref, RX VrefLevel [Byte0]: 51
8654 18:07:02.456946 [Byte1]: 51
8655 18:07:02.460907
8656 18:07:02.461372 Set Vref, RX VrefLevel [Byte0]: 52
8657 18:07:02.464467 [Byte1]: 52
8658 18:07:02.468639
8659 18:07:02.469186 Set Vref, RX VrefLevel [Byte0]: 53
8660 18:07:02.471712 [Byte1]: 53
8661 18:07:02.476220
8662 18:07:02.476648 Set Vref, RX VrefLevel [Byte0]: 54
8663 18:07:02.479633 [Byte1]: 54
8664 18:07:02.483617
8665 18:07:02.484058 Set Vref, RX VrefLevel [Byte0]: 55
8666 18:07:02.487174 [Byte1]: 55
8667 18:07:02.491294
8668 18:07:02.491703 Set Vref, RX VrefLevel [Byte0]: 56
8669 18:07:02.495008 [Byte1]: 56
8670 18:07:02.499141
8671 18:07:02.499550 Set Vref, RX VrefLevel [Byte0]: 57
8672 18:07:02.502119 [Byte1]: 57
8673 18:07:02.506882
8674 18:07:02.507316 Set Vref, RX VrefLevel [Byte0]: 58
8675 18:07:02.509737 [Byte1]: 58
8676 18:07:02.514214
8677 18:07:02.514622 Set Vref, RX VrefLevel [Byte0]: 59
8678 18:07:02.517700 [Byte1]: 59
8679 18:07:02.521969
8680 18:07:02.522494 Set Vref, RX VrefLevel [Byte0]: 60
8681 18:07:02.524892 [Byte1]: 60
8682 18:07:02.529217
8683 18:07:02.529626 Set Vref, RX VrefLevel [Byte0]: 61
8684 18:07:02.533155 [Byte1]: 61
8685 18:07:02.536918
8686 18:07:02.537364 Set Vref, RX VrefLevel [Byte0]: 62
8687 18:07:02.540318 [Byte1]: 62
8688 18:07:02.544463
8689 18:07:02.544874 Set Vref, RX VrefLevel [Byte0]: 63
8690 18:07:02.548025 [Byte1]: 63
8691 18:07:02.551922
8692 18:07:02.552454 Set Vref, RX VrefLevel [Byte0]: 64
8693 18:07:02.555415 [Byte1]: 64
8694 18:07:02.559615
8695 18:07:02.560053 Set Vref, RX VrefLevel [Byte0]: 65
8696 18:07:02.563369 [Byte1]: 65
8697 18:07:02.567493
8698 18:07:02.568051 Set Vref, RX VrefLevel [Byte0]: 66
8699 18:07:02.570845 [Byte1]: 66
8700 18:07:02.575120
8701 18:07:02.575750 Set Vref, RX VrefLevel [Byte0]: 67
8702 18:07:02.578629 [Byte1]: 67
8703 18:07:02.582633
8704 18:07:02.583102 Set Vref, RX VrefLevel [Byte0]: 68
8705 18:07:02.586169 [Byte1]: 68
8706 18:07:02.590192
8707 18:07:02.590611 Set Vref, RX VrefLevel [Byte0]: 69
8708 18:07:02.593485 [Byte1]: 69
8709 18:07:02.597790
8710 18:07:02.598414 Set Vref, RX VrefLevel [Byte0]: 70
8711 18:07:02.601431 [Byte1]: 70
8712 18:07:02.605657
8713 18:07:02.606133 Set Vref, RX VrefLevel [Byte0]: 71
8714 18:07:02.608708 [Byte1]: 71
8715 18:07:02.612886
8716 18:07:02.613415 Set Vref, RX VrefLevel [Byte0]: 72
8717 18:07:02.616577 [Byte1]: 72
8718 18:07:02.620699
8719 18:07:02.621329 Set Vref, RX VrefLevel [Byte0]: 73
8720 18:07:02.624122 [Byte1]: 73
8721 18:07:02.628186
8722 18:07:02.628778 Set Vref, RX VrefLevel [Byte0]: 74
8723 18:07:02.631780 [Byte1]: 74
8724 18:07:02.635689
8725 18:07:02.636103 Set Vref, RX VrefLevel [Byte0]: 75
8726 18:07:02.639233 [Byte1]: 75
8727 18:07:02.643805
8728 18:07:02.644214 Final RX Vref Byte 0 = 58 to rank0
8729 18:07:02.647021 Final RX Vref Byte 1 = 54 to rank0
8730 18:07:02.650462 Final RX Vref Byte 0 = 58 to rank1
8731 18:07:02.653646 Final RX Vref Byte 1 = 54 to rank1==
8732 18:07:02.656938 Dram Type= 6, Freq= 0, CH_1, rank 0
8733 18:07:02.663494 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8734 18:07:02.663907 ==
8735 18:07:02.664230 DQS Delay:
8736 18:07:02.664528 DQS0 = 0, DQS1 = 0
8737 18:07:02.667027 DQM Delay:
8738 18:07:02.667173 DQM0 = 131, DQM1 = 124
8739 18:07:02.670230 DQ Delay:
8740 18:07:02.673084 DQ0 =134, DQ1 =124, DQ2 =118, DQ3 =130
8741 18:07:02.676585 DQ4 =130, DQ5 =142, DQ6 =142, DQ7 =128
8742 18:07:02.680159 DQ8 =112, DQ9 =112, DQ10 =126, DQ11 =118
8743 18:07:02.683116 DQ12 =132, DQ13 =132, DQ14 =130, DQ15 =132
8744 18:07:02.683196
8745 18:07:02.683258
8746 18:07:02.683316
8747 18:07:02.686605 [DramC_TX_OE_Calibration] TA2
8748 18:07:02.689578 Original DQ_B0 (3 6) =30, OEN = 27
8749 18:07:02.693169 Original DQ_B1 (3 6) =30, OEN = 27
8750 18:07:02.696675 24, 0x0, End_B0=24 End_B1=24
8751 18:07:02.696793 25, 0x0, End_B0=25 End_B1=25
8752 18:07:02.700101 26, 0x0, End_B0=26 End_B1=26
8753 18:07:02.703221 27, 0x0, End_B0=27 End_B1=27
8754 18:07:02.706811 28, 0x0, End_B0=28 End_B1=28
8755 18:07:02.706892 29, 0x0, End_B0=29 End_B1=29
8756 18:07:02.709652 30, 0x0, End_B0=30 End_B1=30
8757 18:07:02.713323 31, 0x4141, End_B0=30 End_B1=30
8758 18:07:02.716776 Byte0 end_step=30 best_step=27
8759 18:07:02.719677 Byte1 end_step=30 best_step=27
8760 18:07:02.723288 Byte0 TX OE(2T, 0.5T) = (3, 3)
8761 18:07:02.723361 Byte1 TX OE(2T, 0.5T) = (3, 3)
8762 18:07:02.723456
8763 18:07:02.726332
8764 18:07:02.733269 [DQSOSCAuto] RK0, (LSB)MR18= 0x12fe, (MSB)MR19= 0x302, tDQSOscB0 = 411 ps tDQSOscB1 = 400 ps
8765 18:07:02.736349 CH1 RK0: MR19=302, MR18=12FE
8766 18:07:02.742917 CH1_RK0: MR19=0x302, MR18=0x12FE, DQSOSC=400, MR23=63, INC=23, DEC=15
8767 18:07:02.743022
8768 18:07:02.746249 ----->DramcWriteLeveling(PI) begin...
8769 18:07:02.746323 ==
8770 18:07:02.749977 Dram Type= 6, Freq= 0, CH_1, rank 1
8771 18:07:02.752808 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8772 18:07:02.752904 ==
8773 18:07:02.756387 Write leveling (Byte 0): 24 => 24
8774 18:07:02.759678 Write leveling (Byte 1): 27 => 27
8775 18:07:02.763383 DramcWriteLeveling(PI) end<-----
8776 18:07:02.763519
8777 18:07:02.763607 ==
8778 18:07:02.766776 Dram Type= 6, Freq= 0, CH_1, rank 1
8779 18:07:02.769530 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8780 18:07:02.769640 ==
8781 18:07:02.772985 [Gating] SW mode calibration
8782 18:07:02.779677 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8783 18:07:02.786701 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8784 18:07:02.789677 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8785 18:07:02.793121 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8786 18:07:02.799692 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8787 18:07:02.803260 1 4 12 | B1->B0 | 2a2a 3434 | 1 1 | (1 1) (1 1)
8788 18:07:02.806773 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8789 18:07:02.813188 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8790 18:07:02.816386 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8791 18:07:02.820025 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8792 18:07:02.823485 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8793 18:07:02.830150 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8794 18:07:02.833682 1 5 8 | B1->B0 | 3434 2d2d | 1 1 | (1 1) (1 0)
8795 18:07:02.837135 1 5 12 | B1->B0 | 2e2e 2323 | 0 0 | (0 1) (0 0)
8796 18:07:02.843653 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8797 18:07:02.846628 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8798 18:07:02.850091 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8799 18:07:02.856440 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8800 18:07:02.860170 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8801 18:07:02.863352 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8802 18:07:02.869794 1 6 8 | B1->B0 | 2323 3333 | 0 1 | (0 0) (0 0)
8803 18:07:02.873692 1 6 12 | B1->B0 | 3a3a 4646 | 0 0 | (1 1) (0 0)
8804 18:07:02.876569 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8805 18:07:02.883270 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8806 18:07:02.886812 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8807 18:07:02.890359 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8808 18:07:02.896857 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8809 18:07:02.900470 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8810 18:07:02.903403 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8811 18:07:02.907013 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8812 18:07:02.913401 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8813 18:07:02.916621 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8814 18:07:02.920172 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8815 18:07:02.926642 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8816 18:07:02.930057 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8817 18:07:02.933415 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8818 18:07:02.940343 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8819 18:07:02.943387 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8820 18:07:02.946541 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8821 18:07:02.953651 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8822 18:07:02.956555 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8823 18:07:02.960040 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8824 18:07:02.966962 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8825 18:07:02.969944 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8826 18:07:02.973618 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8827 18:07:02.979821 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8828 18:07:02.979908 Total UI for P1: 0, mck2ui 16
8829 18:07:02.986873 best dqsien dly found for B0: ( 1, 9, 6)
8830 18:07:02.989844 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8831 18:07:02.993004 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8832 18:07:02.996494 Total UI for P1: 0, mck2ui 16
8833 18:07:03.000362 best dqsien dly found for B1: ( 1, 9, 14)
8834 18:07:03.003266 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8835 18:07:03.006761 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8836 18:07:03.006840
8837 18:07:03.010061 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8838 18:07:03.016633 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8839 18:07:03.016717 [Gating] SW calibration Done
8840 18:07:03.016798 ==
8841 18:07:03.019699 Dram Type= 6, Freq= 0, CH_1, rank 1
8842 18:07:03.026877 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8843 18:07:03.026954 ==
8844 18:07:03.027045 RX Vref Scan: 0
8845 18:07:03.027121
8846 18:07:03.029934 RX Vref 0 -> 0, step: 1
8847 18:07:03.030008
8848 18:07:03.033554 RX Delay 0 -> 252, step: 8
8849 18:07:03.037093 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8850 18:07:03.040065 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8851 18:07:03.043498 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8852 18:07:03.046576 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8853 18:07:03.053394 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8854 18:07:03.056653 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8855 18:07:03.059988 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8856 18:07:03.063159 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8857 18:07:03.066323 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8858 18:07:03.073309 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8859 18:07:03.076307 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8860 18:07:03.079702 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8861 18:07:03.082941 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8862 18:07:03.086245 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8863 18:07:03.093127 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8864 18:07:03.096606 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8865 18:07:03.096714 ==
8866 18:07:03.099581 Dram Type= 6, Freq= 0, CH_1, rank 1
8867 18:07:03.103050 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8868 18:07:03.103145 ==
8869 18:07:03.106323 DQS Delay:
8870 18:07:03.106419 DQS0 = 0, DQS1 = 0
8871 18:07:03.106506 DQM Delay:
8872 18:07:03.109701 DQM0 = 131, DQM1 = 127
8873 18:07:03.109783 DQ Delay:
8874 18:07:03.113289 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =127
8875 18:07:03.116272 DQ4 =127, DQ5 =147, DQ6 =143, DQ7 =127
8876 18:07:03.122929 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =119
8877 18:07:03.126401 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8878 18:07:03.126480
8879 18:07:03.126561
8880 18:07:03.126641 ==
8881 18:07:03.129365 Dram Type= 6, Freq= 0, CH_1, rank 1
8882 18:07:03.132907 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8883 18:07:03.133031 ==
8884 18:07:03.133117
8885 18:07:03.133193
8886 18:07:03.136534 TX Vref Scan disable
8887 18:07:03.139605 == TX Byte 0 ==
8888 18:07:03.143212 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8889 18:07:03.146107 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8890 18:07:03.149655 == TX Byte 1 ==
8891 18:07:03.153230 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8892 18:07:03.156299 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8893 18:07:03.156376 ==
8894 18:07:03.159854 Dram Type= 6, Freq= 0, CH_1, rank 1
8895 18:07:03.162839 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8896 18:07:03.162913 ==
8897 18:07:03.178195
8898 18:07:03.181524 TX Vref early break, caculate TX vref
8899 18:07:03.184997 TX Vref=16, minBit 8, minWin=22, winSum=380
8900 18:07:03.188354 TX Vref=18, minBit 0, minWin=24, winSum=391
8901 18:07:03.191754 TX Vref=20, minBit 8, minWin=23, winSum=395
8902 18:07:03.194594 TX Vref=22, minBit 13, minWin=24, winSum=405
8903 18:07:03.198884 TX Vref=24, minBit 6, minWin=25, winSum=416
8904 18:07:03.205097 TX Vref=26, minBit 0, minWin=25, winSum=422
8905 18:07:03.208114 TX Vref=28, minBit 8, minWin=25, winSum=427
8906 18:07:03.211463 TX Vref=30, minBit 15, minWin=25, winSum=425
8907 18:07:03.215139 TX Vref=32, minBit 0, minWin=24, winSum=415
8908 18:07:03.218478 TX Vref=34, minBit 0, minWin=24, winSum=407
8909 18:07:03.222212 TX Vref=36, minBit 0, minWin=23, winSum=398
8910 18:07:03.228305 [TxChooseVref] Worse bit 8, Min win 25, Win sum 427, Final Vref 28
8911 18:07:03.228416
8912 18:07:03.232008 Final TX Range 0 Vref 28
8913 18:07:03.232079
8914 18:07:03.232139 ==
8915 18:07:03.234954 Dram Type= 6, Freq= 0, CH_1, rank 1
8916 18:07:03.238431 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8917 18:07:03.238508 ==
8918 18:07:03.238595
8919 18:07:03.238671
8920 18:07:03.241924 TX Vref Scan disable
8921 18:07:03.248537 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8922 18:07:03.248615 == TX Byte 0 ==
8923 18:07:03.252023 u2DelayCellOfst[0]=17 cells (5 PI)
8924 18:07:03.254995 u2DelayCellOfst[1]=10 cells (3 PI)
8925 18:07:03.258489 u2DelayCellOfst[2]=0 cells (0 PI)
8926 18:07:03.261361 u2DelayCellOfst[3]=7 cells (2 PI)
8927 18:07:03.264832 u2DelayCellOfst[4]=7 cells (2 PI)
8928 18:07:03.268583 u2DelayCellOfst[5]=17 cells (5 PI)
8929 18:07:03.271433 u2DelayCellOfst[6]=17 cells (5 PI)
8930 18:07:03.275082 u2DelayCellOfst[7]=7 cells (2 PI)
8931 18:07:03.278664 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8932 18:07:03.281564 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8933 18:07:03.285010 == TX Byte 1 ==
8934 18:07:03.285101 u2DelayCellOfst[8]=0 cells (0 PI)
8935 18:07:03.288279 u2DelayCellOfst[9]=7 cells (2 PI)
8936 18:07:03.291308 u2DelayCellOfst[10]=10 cells (3 PI)
8937 18:07:03.294699 u2DelayCellOfst[11]=7 cells (2 PI)
8938 18:07:03.298298 u2DelayCellOfst[12]=14 cells (4 PI)
8939 18:07:03.301210 u2DelayCellOfst[13]=14 cells (4 PI)
8940 18:07:03.304720 u2DelayCellOfst[14]=17 cells (5 PI)
8941 18:07:03.308113 u2DelayCellOfst[15]=17 cells (5 PI)
8942 18:07:03.311277 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8943 18:07:03.318112 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8944 18:07:03.318192 DramC Write-DBI on
8945 18:07:03.318273 ==
8946 18:07:03.321281 Dram Type= 6, Freq= 0, CH_1, rank 1
8947 18:07:03.327699 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8948 18:07:03.327778 ==
8949 18:07:03.327859
8950 18:07:03.327945
8951 18:07:03.328020 TX Vref Scan disable
8952 18:07:03.331485 == TX Byte 0 ==
8953 18:07:03.334674 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8954 18:07:03.338067 == TX Byte 1 ==
8955 18:07:03.341364 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8956 18:07:03.341444 DramC Write-DBI off
8957 18:07:03.344772
8958 18:07:03.344868 [DATLAT]
8959 18:07:03.344978 Freq=1600, CH1 RK1
8960 18:07:03.345056
8961 18:07:03.348271 DATLAT Default: 0xf
8962 18:07:03.348349 0, 0xFFFF, sum = 0
8963 18:07:03.351400 1, 0xFFFF, sum = 0
8964 18:07:03.351480 2, 0xFFFF, sum = 0
8965 18:07:03.354876 3, 0xFFFF, sum = 0
8966 18:07:03.354976 4, 0xFFFF, sum = 0
8967 18:07:03.358515 5, 0xFFFF, sum = 0
8968 18:07:03.361457 6, 0xFFFF, sum = 0
8969 18:07:03.361551 7, 0xFFFF, sum = 0
8970 18:07:03.365086 8, 0xFFFF, sum = 0
8971 18:07:03.365180 9, 0xFFFF, sum = 0
8972 18:07:03.367983 10, 0xFFFF, sum = 0
8973 18:07:03.368064 11, 0xFFFF, sum = 0
8974 18:07:03.371621 12, 0xFFFF, sum = 0
8975 18:07:03.371703 13, 0xFFFF, sum = 0
8976 18:07:03.375092 14, 0x0, sum = 1
8977 18:07:03.375172 15, 0x0, sum = 2
8978 18:07:03.378092 16, 0x0, sum = 3
8979 18:07:03.378185 17, 0x0, sum = 4
8980 18:07:03.381736 best_step = 15
8981 18:07:03.381815
8982 18:07:03.381878 ==
8983 18:07:03.384694 Dram Type= 6, Freq= 0, CH_1, rank 1
8984 18:07:03.388215 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8985 18:07:03.388295 ==
8986 18:07:03.388357 RX Vref Scan: 0
8987 18:07:03.388415
8988 18:07:03.391670 RX Vref 0 -> 0, step: 1
8989 18:07:03.391763
8990 18:07:03.395060 RX Delay 11 -> 252, step: 4
8991 18:07:03.398075 iDelay=191, Bit 0, Center 132 (83 ~ 182) 100
8992 18:07:03.405063 iDelay=191, Bit 1, Center 124 (71 ~ 178) 108
8993 18:07:03.408443 iDelay=191, Bit 2, Center 118 (67 ~ 170) 104
8994 18:07:03.411862 iDelay=191, Bit 3, Center 128 (79 ~ 178) 100
8995 18:07:03.414642 iDelay=191, Bit 4, Center 130 (79 ~ 182) 104
8996 18:07:03.418290 iDelay=191, Bit 5, Center 142 (95 ~ 190) 96
8997 18:07:03.421411 iDelay=191, Bit 6, Center 138 (87 ~ 190) 104
8998 18:07:03.428167 iDelay=191, Bit 7, Center 124 (71 ~ 178) 108
8999 18:07:03.431807 iDelay=191, Bit 8, Center 114 (59 ~ 170) 112
9000 18:07:03.434683 iDelay=191, Bit 9, Center 114 (59 ~ 170) 112
9001 18:07:03.438014 iDelay=191, Bit 10, Center 128 (75 ~ 182) 108
9002 18:07:03.441295 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
9003 18:07:03.448512 iDelay=191, Bit 12, Center 134 (83 ~ 186) 104
9004 18:07:03.451319 iDelay=191, Bit 13, Center 136 (83 ~ 190) 108
9005 18:07:03.454843 iDelay=191, Bit 14, Center 134 (83 ~ 186) 104
9006 18:07:03.458207 iDelay=191, Bit 15, Center 134 (83 ~ 186) 104
9007 18:07:03.458317 ==
9008 18:07:03.461828 Dram Type= 6, Freq= 0, CH_1, rank 1
9009 18:07:03.468225 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9010 18:07:03.468333 ==
9011 18:07:03.468427 DQS Delay:
9012 18:07:03.471866 DQS0 = 0, DQS1 = 0
9013 18:07:03.471975 DQM Delay:
9014 18:07:03.472067 DQM0 = 129, DQM1 = 126
9015 18:07:03.474835 DQ Delay:
9016 18:07:03.478481 DQ0 =132, DQ1 =124, DQ2 =118, DQ3 =128
9017 18:07:03.481484 DQ4 =130, DQ5 =142, DQ6 =138, DQ7 =124
9018 18:07:03.485124 DQ8 =114, DQ9 =114, DQ10 =128, DQ11 =118
9019 18:07:03.488180 DQ12 =134, DQ13 =136, DQ14 =134, DQ15 =134
9020 18:07:03.488266
9021 18:07:03.488332
9022 18:07:03.488392
9023 18:07:03.491363 [DramC_TX_OE_Calibration] TA2
9024 18:07:03.494846 Original DQ_B0 (3 6) =30, OEN = 27
9025 18:07:03.498435 Original DQ_B1 (3 6) =30, OEN = 27
9026 18:07:03.501254 24, 0x0, End_B0=24 End_B1=24
9027 18:07:03.501338 25, 0x0, End_B0=25 End_B1=25
9028 18:07:03.504758 26, 0x0, End_B0=26 End_B1=26
9029 18:07:03.508301 27, 0x0, End_B0=27 End_B1=27
9030 18:07:03.511685 28, 0x0, End_B0=28 End_B1=28
9031 18:07:03.514632 29, 0x0, End_B0=29 End_B1=29
9032 18:07:03.514709 30, 0x0, End_B0=30 End_B1=30
9033 18:07:03.518110 31, 0x4141, End_B0=30 End_B1=30
9034 18:07:03.521265 Byte0 end_step=30 best_step=27
9035 18:07:03.524702 Byte1 end_step=30 best_step=27
9036 18:07:03.528117 Byte0 TX OE(2T, 0.5T) = (3, 3)
9037 18:07:03.531586 Byte1 TX OE(2T, 0.5T) = (3, 3)
9038 18:07:03.531696
9039 18:07:03.531788
9040 18:07:03.538127 [DQSOSCAuto] RK1, (LSB)MR18= 0xe13, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 402 ps
9041 18:07:03.541401 CH1 RK1: MR19=303, MR18=E13
9042 18:07:03.547889 CH1_RK1: MR19=0x303, MR18=0xE13, DQSOSC=400, MR23=63, INC=23, DEC=15
9043 18:07:03.551623 [RxdqsGatingPostProcess] freq 1600
9044 18:07:03.554794 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9045 18:07:03.558087 best DQS0 dly(2T, 0.5T) = (1, 1)
9046 18:07:03.561582 best DQS1 dly(2T, 0.5T) = (1, 1)
9047 18:07:03.564820 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9048 18:07:03.568184 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9049 18:07:03.571726 best DQS0 dly(2T, 0.5T) = (1, 1)
9050 18:07:03.574772 best DQS1 dly(2T, 0.5T) = (1, 1)
9051 18:07:03.578293 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9052 18:07:03.581156 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9053 18:07:03.581237 Pre-setting of DQS Precalculation
9054 18:07:03.588441 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9055 18:07:03.594877 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9056 18:07:03.601167 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9057 18:07:03.601252
9058 18:07:03.601316
9059 18:07:03.604842 [Calibration Summary] 3200 Mbps
9060 18:07:03.608299 CH 0, Rank 0
9061 18:07:03.608379 SW Impedance : PASS
9062 18:07:03.611336 DUTY Scan : NO K
9063 18:07:03.614688 ZQ Calibration : PASS
9064 18:07:03.614769 Jitter Meter : NO K
9065 18:07:03.618272 CBT Training : PASS
9066 18:07:03.618352 Write leveling : PASS
9067 18:07:03.621224 RX DQS gating : PASS
9068 18:07:03.624706 RX DQ/DQS(RDDQC) : PASS
9069 18:07:03.624785 TX DQ/DQS : PASS
9070 18:07:03.628091 RX DATLAT : PASS
9071 18:07:03.631565 RX DQ/DQS(Engine): PASS
9072 18:07:03.631645 TX OE : PASS
9073 18:07:03.634949 All Pass.
9074 18:07:03.635029
9075 18:07:03.635092 CH 0, Rank 1
9076 18:07:03.637945 SW Impedance : PASS
9077 18:07:03.638025 DUTY Scan : NO K
9078 18:07:03.641323 ZQ Calibration : PASS
9079 18:07:03.644856 Jitter Meter : NO K
9080 18:07:03.644928 CBT Training : PASS
9081 18:07:03.647816 Write leveling : PASS
9082 18:07:03.651233 RX DQS gating : PASS
9083 18:07:03.651303 RX DQ/DQS(RDDQC) : PASS
9084 18:07:03.654545 TX DQ/DQS : PASS
9085 18:07:03.658281 RX DATLAT : PASS
9086 18:07:03.658350 RX DQ/DQS(Engine): PASS
9087 18:07:03.661329 TX OE : PASS
9088 18:07:03.661427 All Pass.
9089 18:07:03.661515
9090 18:07:03.664620 CH 1, Rank 0
9091 18:07:03.664708 SW Impedance : PASS
9092 18:07:03.667855 DUTY Scan : NO K
9093 18:07:03.667924 ZQ Calibration : PASS
9094 18:07:03.671114 Jitter Meter : NO K
9095 18:07:03.674461 CBT Training : PASS
9096 18:07:03.674540 Write leveling : PASS
9097 18:07:03.678018 RX DQS gating : PASS
9098 18:07:03.681260 RX DQ/DQS(RDDQC) : PASS
9099 18:07:03.681336 TX DQ/DQS : PASS
9100 18:07:03.684842 RX DATLAT : PASS
9101 18:07:03.688416 RX DQ/DQS(Engine): PASS
9102 18:07:03.688485 TX OE : PASS
9103 18:07:03.691387 All Pass.
9104 18:07:03.691455
9105 18:07:03.691512 CH 1, Rank 1
9106 18:07:03.694985 SW Impedance : PASS
9107 18:07:03.695064 DUTY Scan : NO K
9108 18:07:03.698019 ZQ Calibration : PASS
9109 18:07:03.701616 Jitter Meter : NO K
9110 18:07:03.701724 CBT Training : PASS
9111 18:07:03.704885 Write leveling : PASS
9112 18:07:03.707861 RX DQS gating : PASS
9113 18:07:03.707940 RX DQ/DQS(RDDQC) : PASS
9114 18:07:03.711323 TX DQ/DQS : PASS
9115 18:07:03.711403 RX DATLAT : PASS
9116 18:07:03.714881 RX DQ/DQS(Engine): PASS
9117 18:07:03.717717 TX OE : PASS
9118 18:07:03.717797 All Pass.
9119 18:07:03.717860
9120 18:07:03.721200 DramC Write-DBI on
9121 18:07:03.721310 PER_BANK_REFRESH: Hybrid Mode
9122 18:07:03.724834 TX_TRACKING: ON
9123 18:07:03.734762 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9124 18:07:03.741553 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9125 18:07:03.747813 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9126 18:07:03.751312 [FAST_K] Save calibration result to emmc
9127 18:07:03.754811 sync common calibartion params.
9128 18:07:03.757659 sync cbt_mode0:1, 1:1
9129 18:07:03.757739 dram_init: ddr_geometry: 2
9130 18:07:03.761191 dram_init: ddr_geometry: 2
9131 18:07:03.764732 dram_init: ddr_geometry: 2
9132 18:07:03.768171 0:dram_rank_size:100000000
9133 18:07:03.768252 1:dram_rank_size:100000000
9134 18:07:03.774565 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9135 18:07:03.778029 DFS_SHUFFLE_HW_MODE: ON
9136 18:07:03.781306 dramc_set_vcore_voltage set vcore to 725000
9137 18:07:03.781385 Read voltage for 1600, 0
9138 18:07:03.784605 Vio18 = 0
9139 18:07:03.784710 Vcore = 725000
9140 18:07:03.784800 Vdram = 0
9141 18:07:03.788226 Vddq = 0
9142 18:07:03.788305 Vmddr = 0
9143 18:07:03.791247 switch to 3200 Mbps bootup
9144 18:07:03.791326 [DramcRunTimeConfig]
9145 18:07:03.791388 PHYPLL
9146 18:07:03.794723 DPM_CONTROL_AFTERK: ON
9147 18:07:03.798295 PER_BANK_REFRESH: ON
9148 18:07:03.798391 REFRESH_OVERHEAD_REDUCTION: ON
9149 18:07:03.801348 CMD_PICG_NEW_MODE: OFF
9150 18:07:03.804864 XRTWTW_NEW_MODE: ON
9151 18:07:03.804969 XRTRTR_NEW_MODE: ON
9152 18:07:03.807712 TX_TRACKING: ON
9153 18:07:03.807791 RDSEL_TRACKING: OFF
9154 18:07:03.811171 DQS Precalculation for DVFS: ON
9155 18:07:03.811250 RX_TRACKING: OFF
9156 18:07:03.814704 HW_GATING DBG: ON
9157 18:07:03.814783 ZQCS_ENABLE_LP4: ON
9158 18:07:03.818281 RX_PICG_NEW_MODE: ON
9159 18:07:03.821168 TX_PICG_NEW_MODE: ON
9160 18:07:03.821247 ENABLE_RX_DCM_DPHY: ON
9161 18:07:03.824568 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9162 18:07:03.827943 DUMMY_READ_FOR_TRACKING: OFF
9163 18:07:03.831036 !!! SPM_CONTROL_AFTERK: OFF
9164 18:07:03.834758 !!! SPM could not control APHY
9165 18:07:03.834838 IMPEDANCE_TRACKING: ON
9166 18:07:03.838198 TEMP_SENSOR: ON
9167 18:07:03.838277 HW_SAVE_FOR_SR: OFF
9168 18:07:03.840953 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9169 18:07:03.844931 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9170 18:07:03.847865 Read ODT Tracking: ON
9171 18:07:03.847944 Refresh Rate DeBounce: ON
9172 18:07:03.851151 DFS_NO_QUEUE_FLUSH: ON
9173 18:07:03.854805 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9174 18:07:03.857714 ENABLE_DFS_RUNTIME_MRW: OFF
9175 18:07:03.857795 DDR_RESERVE_NEW_MODE: ON
9176 18:07:03.860914 MR_CBT_SWITCH_FREQ: ON
9177 18:07:03.864532 =========================
9178 18:07:03.882697 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9179 18:07:03.886119 dram_init: ddr_geometry: 2
9180 18:07:03.904342 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9181 18:07:03.907518 dram_init: dram init end (result: 0)
9182 18:07:03.914425 DRAM-K: Full calibration passed in 24617 msecs
9183 18:07:03.917349 MRC: failed to locate region type 0.
9184 18:07:03.917429 DRAM rank0 size:0x100000000,
9185 18:07:03.920822 DRAM rank1 size=0x100000000
9186 18:07:03.930760 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9187 18:07:03.937971 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9188 18:07:03.944262 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9189 18:07:03.950775 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9190 18:07:03.954572 DRAM rank0 size:0x100000000,
9191 18:07:03.957526 DRAM rank1 size=0x100000000
9192 18:07:03.957600 CBMEM:
9193 18:07:03.961120 IMD: root @ 0xfffff000 254 entries.
9194 18:07:03.964537 IMD: root @ 0xffffec00 62 entries.
9195 18:07:03.967910 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9196 18:07:03.970900 WARNING: RO_VPD is uninitialized or empty.
9197 18:07:03.977224 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9198 18:07:03.984334 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9199 18:07:03.996698 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9200 18:07:04.008374 BS: romstage times (exec / console): total (unknown) / 24114 ms
9201 18:07:04.008504
9202 18:07:04.008598
9203 18:07:04.018701 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9204 18:07:04.021575 ARM64: Exception handlers installed.
9205 18:07:04.025251 ARM64: Testing exception
9206 18:07:04.028690 ARM64: Done test exception
9207 18:07:04.028798 Enumerating buses...
9208 18:07:04.032055 Show all devs... Before device enumeration.
9209 18:07:04.035060 Root Device: enabled 1
9210 18:07:04.038569 CPU_CLUSTER: 0: enabled 1
9211 18:07:04.038667 CPU: 00: enabled 1
9212 18:07:04.042129 Compare with tree...
9213 18:07:04.042225 Root Device: enabled 1
9214 18:07:04.045155 CPU_CLUSTER: 0: enabled 1
9215 18:07:04.048671 CPU: 00: enabled 1
9216 18:07:04.048801 Root Device scanning...
9217 18:07:04.051717 scan_static_bus for Root Device
9218 18:07:04.055089 CPU_CLUSTER: 0 enabled
9219 18:07:04.058755 scan_static_bus for Root Device done
9220 18:07:04.062047 scan_bus: bus Root Device finished in 8 msecs
9221 18:07:04.062145 done
9222 18:07:04.068437 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9223 18:07:04.071922 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9224 18:07:04.078429 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9225 18:07:04.082116 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9226 18:07:04.085126 Allocating resources...
9227 18:07:04.085251 Reading resources...
9228 18:07:04.088622 Root Device read_resources bus 0 link: 0
9229 18:07:04.091626 DRAM rank0 size:0x100000000,
9230 18:07:04.095241 DRAM rank1 size=0x100000000
9231 18:07:04.098591 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9232 18:07:04.101693 CPU: 00 missing read_resources
9233 18:07:04.105191 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9234 18:07:04.111985 Root Device read_resources bus 0 link: 0 done
9235 18:07:04.112098 Done reading resources.
9236 18:07:04.118326 Show resources in subtree (Root Device)...After reading.
9237 18:07:04.121917 Root Device child on link 0 CPU_CLUSTER: 0
9238 18:07:04.125410 CPU_CLUSTER: 0 child on link 0 CPU: 00
9239 18:07:04.135184 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9240 18:07:04.135273 CPU: 00
9241 18:07:04.138353 Root Device assign_resources, bus 0 link: 0
9242 18:07:04.141825 CPU_CLUSTER: 0 missing set_resources
9243 18:07:04.145388 Root Device assign_resources, bus 0 link: 0 done
9244 18:07:04.148264 Done setting resources.
9245 18:07:04.154819 Show resources in subtree (Root Device)...After assigning values.
9246 18:07:04.158397 Root Device child on link 0 CPU_CLUSTER: 0
9247 18:07:04.161177 CPU_CLUSTER: 0 child on link 0 CPU: 00
9248 18:07:04.171593 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9249 18:07:04.171702 CPU: 00
9250 18:07:04.175037 Done allocating resources.
9251 18:07:04.177890 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9252 18:07:04.181516 Enabling resources...
9253 18:07:04.181598 done.
9254 18:07:04.188068 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9255 18:07:04.188151 Initializing devices...
9256 18:07:04.191584 Root Device init
9257 18:07:04.191666 init hardware done!
9258 18:07:04.194627 0x00000018: ctrlr->caps
9259 18:07:04.198170 52.000 MHz: ctrlr->f_max
9260 18:07:04.198257 0.400 MHz: ctrlr->f_min
9261 18:07:04.201206 0x40ff8080: ctrlr->voltages
9262 18:07:04.201290 sclk: 390625
9263 18:07:04.204673 Bus Width = 1
9264 18:07:04.204755 sclk: 390625
9265 18:07:04.204852 Bus Width = 1
9266 18:07:04.208096 Early init status = 3
9267 18:07:04.214695 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9268 18:07:04.218239 in-header: 03 fc 00 00 01 00 00 00
9269 18:07:04.218350 in-data: 00
9270 18:07:04.224494 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9271 18:07:04.228366 in-header: 03 fd 00 00 00 00 00 00
9272 18:07:04.232265 in-data:
9273 18:07:04.235021 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9274 18:07:04.239731 in-header: 03 fc 00 00 01 00 00 00
9275 18:07:04.243128 in-data: 00
9276 18:07:04.246151 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9277 18:07:04.251949 in-header: 03 fd 00 00 00 00 00 00
9278 18:07:04.255143 in-data:
9279 18:07:04.258581 [SSUSB] Setting up USB HOST controller...
9280 18:07:04.261898 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9281 18:07:04.265330 [SSUSB] phy power-on done.
9282 18:07:04.268326 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9283 18:07:04.275165 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9284 18:07:04.278372 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9285 18:07:04.285366 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9286 18:07:04.292104 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9287 18:07:04.298535 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9288 18:07:04.304918 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9289 18:07:04.311672 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9290 18:07:04.311755 SPM: binary array size = 0x9dc
9291 18:07:04.318634 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9292 18:07:04.325175 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9293 18:07:04.331735 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9294 18:07:04.334827 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9295 18:07:04.341507 configure_display: Starting display init
9296 18:07:04.375206 anx7625_power_on_init: Init interface.
9297 18:07:04.378625 anx7625_disable_pd_protocol: Disabled PD feature.
9298 18:07:04.381493 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9299 18:07:04.409703 anx7625_start_dp_work: Secure OCM version=00
9300 18:07:04.412612 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9301 18:07:04.427644 sp_tx_get_edid_block: EDID Block = 1
9302 18:07:04.530192 Extracted contents:
9303 18:07:04.533713 header: 00 ff ff ff ff ff ff 00
9304 18:07:04.536636 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9305 18:07:04.540301 version: 01 04
9306 18:07:04.543344 basic params: 95 1f 11 78 0a
9307 18:07:04.546834 chroma info: 76 90 94 55 54 90 27 21 50 54
9308 18:07:04.549845 established: 00 00 00
9309 18:07:04.556454 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9310 18:07:04.560033 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9311 18:07:04.566657 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9312 18:07:04.573644 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9313 18:07:04.580127 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9314 18:07:04.583243 extensions: 00
9315 18:07:04.583322 checksum: fb
9316 18:07:04.583384
9317 18:07:04.586794 Manufacturer: IVO Model 57d Serial Number 0
9318 18:07:04.590135 Made week 0 of 2020
9319 18:07:04.590213 EDID version: 1.4
9320 18:07:04.593496 Digital display
9321 18:07:04.596760 6 bits per primary color channel
9322 18:07:04.596872 DisplayPort interface
9323 18:07:04.600085 Maximum image size: 31 cm x 17 cm
9324 18:07:04.603706 Gamma: 220%
9325 18:07:04.603786 Check DPMS levels
9326 18:07:04.606439 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9327 18:07:04.610279 First detailed timing is preferred timing
9328 18:07:04.613441 Established timings supported:
9329 18:07:04.616738 Standard timings supported:
9330 18:07:04.616818 Detailed timings
9331 18:07:04.623343 Hex of detail: 383680a07038204018303c0035ae10000019
9332 18:07:04.626772 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9333 18:07:04.630247 0780 0798 07c8 0820 hborder 0
9334 18:07:04.636576 0438 043b 0447 0458 vborder 0
9335 18:07:04.636657 -hsync -vsync
9336 18:07:04.640124 Did detailed timing
9337 18:07:04.643093 Hex of detail: 000000000000000000000000000000000000
9338 18:07:04.646735 Manufacturer-specified data, tag 0
9339 18:07:04.653382 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9340 18:07:04.653462 ASCII string: InfoVision
9341 18:07:04.659955 Hex of detail: 000000fe00523134304e574635205248200a
9342 18:07:04.660035 ASCII string: R140NWF5 RH
9343 18:07:04.663345 Checksum
9344 18:07:04.663426 Checksum: 0xfb (valid)
9345 18:07:04.669960 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9346 18:07:04.670042 DSI data_rate: 832800000 bps
9347 18:07:04.677936 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9348 18:07:04.681103 anx7625_parse_edid: pixelclock(138800).
9349 18:07:04.684486 hactive(1920), hsync(48), hfp(24), hbp(88)
9350 18:07:04.687970 vactive(1080), vsync(12), vfp(3), vbp(17)
9351 18:07:04.691212 anx7625_dsi_config: config dsi.
9352 18:07:04.697966 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9353 18:07:04.712164 anx7625_dsi_config: success to config DSI
9354 18:07:04.715447 anx7625_dp_start: MIPI phy setup OK.
9355 18:07:04.718614 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9356 18:07:04.722401 mtk_ddp_mode_set invalid vrefresh 60
9357 18:07:04.725722 main_disp_path_setup
9358 18:07:04.725803 ovl_layer_smi_id_en
9359 18:07:04.729148 ovl_layer_smi_id_en
9360 18:07:04.729229 ccorr_config
9361 18:07:04.729293 aal_config
9362 18:07:04.732041 gamma_config
9363 18:07:04.732139 postmask_config
9364 18:07:04.735543 dither_config
9365 18:07:04.739082 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9366 18:07:04.745598 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9367 18:07:04.749253 Root Device init finished in 554 msecs
9368 18:07:04.749334 CPU_CLUSTER: 0 init
9369 18:07:04.758727 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9370 18:07:04.762310 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9371 18:07:04.765881 APU_MBOX 0x190000b0 = 0x10001
9372 18:07:04.768971 APU_MBOX 0x190001b0 = 0x10001
9373 18:07:04.771992 APU_MBOX 0x190005b0 = 0x10001
9374 18:07:04.775551 APU_MBOX 0x190006b0 = 0x10001
9375 18:07:04.778617 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9376 18:07:04.791369 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9377 18:07:04.803750 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9378 18:07:04.810284 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9379 18:07:04.821869 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9380 18:07:04.831265 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9381 18:07:04.834431 CPU_CLUSTER: 0 init finished in 81 msecs
9382 18:07:04.837468 Devices initialized
9383 18:07:04.841185 Show all devs... After init.
9384 18:07:04.841275 Root Device: enabled 1
9385 18:07:04.844332 CPU_CLUSTER: 0: enabled 1
9386 18:07:04.847720 CPU: 00: enabled 1
9387 18:07:04.851383 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9388 18:07:04.854374 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9389 18:07:04.857879 ELOG: NV offset 0x57f000 size 0x1000
9390 18:07:04.864448 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9391 18:07:04.871050 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9392 18:07:04.874746 ELOG: Event(17) added with size 13 at 2024-06-11 18:07:04 UTC
9393 18:07:04.877739 out: cmd=0x121: 03 db 21 01 00 00 00 00
9394 18:07:04.881893 in-header: 03 af 00 00 2c 00 00 00
9395 18:07:04.894984 in-data: b0 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9396 18:07:04.902122 ELOG: Event(A1) added with size 10 at 2024-06-11 18:07:04 UTC
9397 18:07:04.908693 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9398 18:07:04.911951 ELOG: Event(A0) added with size 9 at 2024-06-11 18:07:04 UTC
9399 18:07:04.918756 elog_add_boot_reason: Logged dev mode boot
9400 18:07:04.922179 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9401 18:07:04.925441 Finalize devices...
9402 18:07:04.925518 Devices finalized
9403 18:07:04.932273 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9404 18:07:04.935139 Writing coreboot table at 0xffe64000
9405 18:07:04.938628 0. 000000000010a000-0000000000113fff: RAMSTAGE
9406 18:07:04.941877 1. 0000000040000000-00000000400fffff: RAM
9407 18:07:04.945588 2. 0000000040100000-000000004032afff: RAMSTAGE
9408 18:07:04.948678 3. 000000004032b000-00000000545fffff: RAM
9409 18:07:04.955295 4. 0000000054600000-000000005465ffff: BL31
9410 18:07:04.958762 5. 0000000054660000-00000000ffe63fff: RAM
9411 18:07:04.961942 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9412 18:07:04.965636 7. 0000000100000000-000000023fffffff: RAM
9413 18:07:04.968607 Passing 5 GPIOs to payload:
9414 18:07:04.975823 NAME | PORT | POLARITY | VALUE
9415 18:07:04.978732 EC in RW | 0x000000aa | low | undefined
9416 18:07:04.982341 EC interrupt | 0x00000005 | low | undefined
9417 18:07:04.988883 TPM interrupt | 0x000000ab | high | undefined
9418 18:07:04.992018 SD card detect | 0x00000011 | high | undefined
9419 18:07:04.998741 speaker enable | 0x00000093 | high | undefined
9420 18:07:05.002246 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9421 18:07:05.005229 in-header: 03 f9 00 00 02 00 00 00
9422 18:07:05.005349 in-data: 02 00
9423 18:07:05.008674 ADC[4]: Raw value=899483 ID=7
9424 18:07:05.012282 ADC[3]: Raw value=213336 ID=1
9425 18:07:05.012364 RAM Code: 0x71
9426 18:07:05.015591 ADC[6]: Raw value=74557 ID=0
9427 18:07:05.018662 ADC[5]: Raw value=211860 ID=1
9428 18:07:05.018744 SKU Code: 0x1
9429 18:07:05.025234 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 738d
9430 18:07:05.028575 coreboot table: 964 bytes.
9431 18:07:05.032105 IMD ROOT 0. 0xfffff000 0x00001000
9432 18:07:05.035571 IMD SMALL 1. 0xffffe000 0x00001000
9433 18:07:05.038726 RO MCACHE 2. 0xffffc000 0x00001104
9434 18:07:05.041936 CONSOLE 3. 0xfff7c000 0x00080000
9435 18:07:05.045031 FMAP 4. 0xfff7b000 0x00000452
9436 18:07:05.048574 TIME STAMP 5. 0xfff7a000 0x00000910
9437 18:07:05.052288 VBOOT WORK 6. 0xfff66000 0x00014000
9438 18:07:05.055099 RAMOOPS 7. 0xffe66000 0x00100000
9439 18:07:05.055181 COREBOOT 8. 0xffe64000 0x00002000
9440 18:07:05.058634 IMD small region:
9441 18:07:05.061981 IMD ROOT 0. 0xffffec00 0x00000400
9442 18:07:05.065390 VPD 1. 0xffffeb80 0x0000006c
9443 18:07:05.068330 MMC STATUS 2. 0xffffeb60 0x00000004
9444 18:07:05.075087 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9445 18:07:05.075169 Probing TPM: done!
9446 18:07:05.081921 Connected to device vid:did:rid of 1ae0:0028:00
9447 18:07:05.088894 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9448 18:07:05.092370 Initialized TPM device CR50 revision 0
9449 18:07:05.095436 Checking cr50 for pending updates
9450 18:07:05.101215 Reading cr50 TPM mode
9451 18:07:05.110059 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9452 18:07:05.116540 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9453 18:07:05.156438 read SPI 0x3990ec 0x4f1b0: 34847 us, 9298 KB/s, 74.384 Mbps
9454 18:07:05.159817 Checking segment from ROM address 0x40100000
9455 18:07:05.163331 Checking segment from ROM address 0x4010001c
9456 18:07:05.169821 Loading segment from ROM address 0x40100000
9457 18:07:05.169905 code (compression=0)
9458 18:07:05.176823 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9459 18:07:05.186993 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9460 18:07:05.187076 it's not compressed!
9461 18:07:05.193417 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9462 18:07:05.196622 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9463 18:07:05.217092 Loading segment from ROM address 0x4010001c
9464 18:07:05.217243 Entry Point 0x80000000
9465 18:07:05.220421 Loaded segments
9466 18:07:05.224063 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9467 18:07:05.230306 Jumping to boot code at 0x80000000(0xffe64000)
9468 18:07:05.237447 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9469 18:07:05.243655 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9470 18:07:05.251704 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9471 18:07:05.255185 Checking segment from ROM address 0x40100000
9472 18:07:05.257989 Checking segment from ROM address 0x4010001c
9473 18:07:05.264860 Loading segment from ROM address 0x40100000
9474 18:07:05.264942 code (compression=1)
9475 18:07:05.271345 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9476 18:07:05.281479 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9477 18:07:05.281563 using LZMA
9478 18:07:05.289723 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9479 18:07:05.296891 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9480 18:07:05.299712 Loading segment from ROM address 0x4010001c
9481 18:07:05.299797 Entry Point 0x54601000
9482 18:07:05.303716 Loaded segments
9483 18:07:05.306366 NOTICE: MT8192 bl31_setup
9484 18:07:05.313461 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9485 18:07:05.316922 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9486 18:07:05.319944 WARNING: region 0:
9487 18:07:05.323486 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9488 18:07:05.323568 WARNING: region 1:
9489 18:07:05.330502 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9490 18:07:05.333441 WARNING: region 2:
9491 18:07:05.336788 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9492 18:07:05.340606 WARNING: region 3:
9493 18:07:05.343950 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9494 18:07:05.346799 WARNING: region 4:
9495 18:07:05.350129 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9496 18:07:05.354091 WARNING: region 5:
9497 18:07:05.357080 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9498 18:07:05.360488 WARNING: region 6:
9499 18:07:05.364040 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9500 18:07:05.364150 WARNING: region 7:
9501 18:07:05.370350 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9502 18:07:05.376982 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9503 18:07:05.380608 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9504 18:07:05.384151 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9505 18:07:05.387178 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9506 18:07:05.393805 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9507 18:07:05.397309 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9508 18:07:05.403890 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9509 18:07:05.407442 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9510 18:07:05.411026 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9511 18:07:05.417501 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9512 18:07:05.420627 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9513 18:07:05.424354 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9514 18:07:05.430700 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9515 18:07:05.433932 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9516 18:07:05.441089 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9517 18:07:05.444154 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9518 18:07:05.447445 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9519 18:07:05.454155 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9520 18:07:05.457526 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9521 18:07:05.461182 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9522 18:07:05.467966 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9523 18:07:05.470899 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9524 18:07:05.474548 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9525 18:07:05.481116 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9526 18:07:05.484515 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9527 18:07:05.491545 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9528 18:07:05.494647 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9529 18:07:05.498195 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9530 18:07:05.504765 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9531 18:07:05.508288 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9532 18:07:05.514875 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9533 18:07:05.518415 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9534 18:07:05.521391 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9535 18:07:05.524846 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9536 18:07:05.531776 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9537 18:07:05.534988 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9538 18:07:05.538442 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9539 18:07:05.541802 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9540 18:07:05.548637 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9541 18:07:05.551457 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9542 18:07:05.554850 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9543 18:07:05.558395 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9544 18:07:05.564870 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9545 18:07:05.568611 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9546 18:07:05.571701 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9547 18:07:05.574951 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9548 18:07:05.581883 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9549 18:07:05.585126 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9550 18:07:05.588569 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9551 18:07:05.595091 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9552 18:07:05.598603 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9553 18:07:05.602135 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9554 18:07:05.608727 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9555 18:07:05.612149 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9556 18:07:05.618668 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9557 18:07:05.622243 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9558 18:07:05.628439 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9559 18:07:05.632034 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9560 18:07:05.635525 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9561 18:07:05.641994 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9562 18:07:05.645647 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9563 18:07:05.652236 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9564 18:07:05.655653 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9565 18:07:05.662234 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9566 18:07:05.665345 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9567 18:07:05.668845 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9568 18:07:05.675438 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9569 18:07:05.678858 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9570 18:07:05.685834 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9571 18:07:05.689138 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9572 18:07:05.692382 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9573 18:07:05.699408 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9574 18:07:05.702257 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9575 18:07:05.708828 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9576 18:07:05.712524 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9577 18:07:05.719471 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9578 18:07:05.722371 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9579 18:07:05.725930 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9580 18:07:05.732895 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9581 18:07:05.736203 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9582 18:07:05.743001 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9583 18:07:05.746025 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9584 18:07:05.752741 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9585 18:07:05.756356 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9586 18:07:05.759468 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9587 18:07:05.766125 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9588 18:07:05.769131 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9589 18:07:05.776243 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9590 18:07:05.779708 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9591 18:07:05.786390 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9592 18:07:05.789579 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9593 18:07:05.792944 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9594 18:07:05.799372 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9595 18:07:05.802851 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9596 18:07:05.809327 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9597 18:07:05.812968 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9598 18:07:05.816080 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9599 18:07:05.822766 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9600 18:07:05.826346 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9601 18:07:05.829904 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9602 18:07:05.832828 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9603 18:07:05.840019 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9604 18:07:05.842879 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9605 18:07:05.850006 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9606 18:07:05.852960 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9607 18:07:05.856631 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9608 18:07:05.863235 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9609 18:07:05.866758 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9610 18:07:05.873179 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9611 18:07:05.876461 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9612 18:07:05.879857 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9613 18:07:05.886987 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9614 18:07:05.889934 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9615 18:07:05.893229 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9616 18:07:05.900061 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9617 18:07:05.903424 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9618 18:07:05.906884 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9619 18:07:05.913539 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9620 18:07:05.916783 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9621 18:07:05.919805 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9622 18:07:05.926882 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9623 18:07:05.929960 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9624 18:07:05.933600 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9625 18:07:05.936580 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9626 18:07:05.943638 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9627 18:07:05.946948 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9628 18:07:05.950431 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9629 18:07:05.956729 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9630 18:07:05.960319 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9631 18:07:05.966898 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9632 18:07:05.970469 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9633 18:07:05.973870 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9634 18:07:05.980318 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9635 18:07:05.983732 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9636 18:07:05.987374 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9637 18:07:05.993797 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9638 18:07:05.996997 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9639 18:07:06.003705 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9640 18:07:06.007000 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9641 18:07:06.010460 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9642 18:07:06.017125 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9643 18:07:06.020794 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9644 18:07:06.023766 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9645 18:07:06.030815 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9646 18:07:06.033895 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9647 18:07:06.040487 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9648 18:07:06.044000 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9649 18:07:06.047620 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9650 18:07:06.054526 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9651 18:07:06.057838 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9652 18:07:06.060760 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9653 18:07:06.067827 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9654 18:07:06.070787 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9655 18:07:06.077943 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9656 18:07:06.080724 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9657 18:07:06.084125 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9658 18:07:06.091159 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9659 18:07:06.094191 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9660 18:07:06.097841 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9661 18:07:06.104298 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9662 18:07:06.107237 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9663 18:07:06.114403 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9664 18:07:06.117250 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9665 18:07:06.124224 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9666 18:07:06.127558 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9667 18:07:06.130679 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9668 18:07:06.137213 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9669 18:07:06.140535 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9670 18:07:06.144261 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9671 18:07:06.150766 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9672 18:07:06.153882 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9673 18:07:06.160851 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9674 18:07:06.163670 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9675 18:07:06.167041 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9676 18:07:06.174088 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9677 18:07:06.177048 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9678 18:07:06.183658 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9679 18:07:06.187027 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9680 18:07:06.190507 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9681 18:07:06.197096 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9682 18:07:06.200661 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9683 18:07:06.203632 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9684 18:07:06.210333 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9685 18:07:06.213813 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9686 18:07:06.220320 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9687 18:07:06.223725 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9688 18:07:06.227263 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9689 18:07:06.233810 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9690 18:07:06.236932 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9691 18:07:06.243781 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9692 18:07:06.246902 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9693 18:07:06.253794 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9694 18:07:06.256758 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9695 18:07:06.260120 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9696 18:07:06.267193 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9697 18:07:06.270742 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9698 18:07:06.277303 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9699 18:07:06.280314 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9700 18:07:06.283615 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9701 18:07:06.290877 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9702 18:07:06.293680 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9703 18:07:06.300690 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9704 18:07:06.303654 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9705 18:07:06.307135 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9706 18:07:06.313710 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9707 18:07:06.317387 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9708 18:07:06.324020 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9709 18:07:06.327115 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9710 18:07:06.330381 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9711 18:07:06.337239 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9712 18:07:06.340724 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9713 18:07:06.347354 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9714 18:07:06.350930 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9715 18:07:06.357445 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9716 18:07:06.360306 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9717 18:07:06.364189 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9718 18:07:06.370638 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9719 18:07:06.373615 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9720 18:07:06.380421 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9721 18:07:06.383700 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9722 18:07:06.386971 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9723 18:07:06.393876 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9724 18:07:06.397299 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9725 18:07:06.403712 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9726 18:07:06.407320 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9727 18:07:06.410296 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9728 18:07:06.417486 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9729 18:07:06.420441 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9730 18:07:06.427015 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9731 18:07:06.430432 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9732 18:07:06.433766 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9733 18:07:06.437406 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9734 18:07:06.440286 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9735 18:07:06.446910 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9736 18:07:06.450779 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9737 18:07:06.453968 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9738 18:07:06.460599 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9739 18:07:06.463522 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9740 18:07:06.467225 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9741 18:07:06.473917 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9742 18:07:06.476852 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9743 18:07:06.483986 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9744 18:07:06.487369 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9745 18:07:06.490813 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9746 18:07:06.497463 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9747 18:07:06.500487 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9748 18:07:06.504032 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9749 18:07:06.510432 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9750 18:07:06.514059 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9751 18:07:06.517344 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9752 18:07:06.523817 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9753 18:07:06.527433 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9754 18:07:06.534099 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9755 18:07:06.537111 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9756 18:07:06.540561 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9757 18:07:06.547272 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9758 18:07:06.550767 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9759 18:07:06.554126 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9760 18:07:06.560627 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9761 18:07:06.563765 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9762 18:07:06.567268 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9763 18:07:06.573859 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9764 18:07:06.577354 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9765 18:07:06.580244 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9766 18:07:06.587409 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9767 18:07:06.590513 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9768 18:07:06.596936 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9769 18:07:06.600449 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9770 18:07:06.603444 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9771 18:07:06.610411 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9772 18:07:06.613766 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9773 18:07:06.616946 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9774 18:07:06.620414 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9775 18:07:06.623418 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9776 18:07:06.630241 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9777 18:07:06.633544 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9778 18:07:06.636918 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9779 18:07:06.640189 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9780 18:07:06.646630 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9781 18:07:06.650042 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9782 18:07:06.653726 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9783 18:07:06.660081 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9784 18:07:06.663564 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9785 18:07:06.666787 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9786 18:07:06.673824 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9787 18:07:06.676726 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9788 18:07:06.683909 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9789 18:07:06.686859 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9790 18:07:06.690396 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9791 18:07:06.697032 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9792 18:07:06.700235 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9793 18:07:06.706777 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9794 18:07:06.710230 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9795 18:07:06.713900 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9796 18:07:06.720476 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9797 18:07:06.723339 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9798 18:07:06.730506 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9799 18:07:06.733393 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9800 18:07:06.737189 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9801 18:07:06.743323 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9802 18:07:06.746879 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9803 18:07:06.753395 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9804 18:07:06.757169 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9805 18:07:06.760223 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9806 18:07:06.767022 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9807 18:07:06.769999 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9808 18:07:06.776687 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9809 18:07:06.780317 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9810 18:07:06.783426 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9811 18:07:06.790147 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9812 18:07:06.793673 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9813 18:07:06.800283 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9814 18:07:06.803782 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9815 18:07:06.806861 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9816 18:07:06.813699 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9817 18:07:06.816693 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9818 18:07:06.823865 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9819 18:07:06.826720 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9820 18:07:06.830130 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9821 18:07:06.836827 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9822 18:07:06.840423 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9823 18:07:06.846800 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9824 18:07:06.850480 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9825 18:07:06.853988 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9826 18:07:06.859936 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9827 18:07:06.863579 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9828 18:07:06.870197 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9829 18:07:06.873635 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9830 18:07:06.880593 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9831 18:07:06.883842 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9832 18:07:06.887084 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9833 18:07:06.893605 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9834 18:07:06.896668 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9835 18:07:06.900243 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9836 18:07:06.906887 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9837 18:07:06.910397 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9838 18:07:06.916888 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9839 18:07:06.920132 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9840 18:07:06.923298 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9841 18:07:06.930415 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9842 18:07:06.933406 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9843 18:07:06.940032 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9844 18:07:06.943621 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9845 18:07:06.949991 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9846 18:07:06.953421 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9847 18:07:06.956602 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9848 18:07:06.963207 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9849 18:07:06.966658 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9850 18:07:06.973603 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9851 18:07:06.976484 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9852 18:07:06.980051 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9853 18:07:06.986609 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9854 18:07:06.990072 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9855 18:07:06.993451 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9856 18:07:07.000556 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9857 18:07:07.003491 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9858 18:07:07.010169 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9859 18:07:07.013620 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9860 18:07:07.020142 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9861 18:07:07.023469 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9862 18:07:07.030654 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9863 18:07:07.033640 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9864 18:07:07.037182 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9865 18:07:07.043187 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9866 18:07:07.046695 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9867 18:07:07.053850 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9868 18:07:07.057122 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9869 18:07:07.063861 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9870 18:07:07.066779 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9871 18:07:07.070118 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9872 18:07:07.076878 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9873 18:07:07.080431 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9874 18:07:07.087072 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9875 18:07:07.089897 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9876 18:07:07.096664 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9877 18:07:07.100204 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9878 18:07:07.103595 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9879 18:07:07.109905 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9880 18:07:07.113661 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9881 18:07:07.120053 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9882 18:07:07.123611 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9883 18:07:07.130072 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9884 18:07:07.133313 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9885 18:07:07.137012 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9886 18:07:07.143257 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9887 18:07:07.146804 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9888 18:07:07.153255 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9889 18:07:07.156954 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9890 18:07:07.163372 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9891 18:07:07.166937 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9892 18:07:07.170088 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9893 18:07:07.176823 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9894 18:07:07.180383 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9895 18:07:07.186755 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9896 18:07:07.190153 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9897 18:07:07.196697 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9898 18:07:07.200048 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9899 18:07:07.203490 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9900 18:07:07.209873 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9901 18:07:07.213419 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9902 18:07:07.220022 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9903 18:07:07.223451 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9904 18:07:07.226701 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9905 18:07:07.233427 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9906 18:07:07.236944 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9907 18:07:07.243418 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9908 18:07:07.246531 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9909 18:07:07.253263 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9910 18:07:07.256948 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9911 18:07:07.263619 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9912 18:07:07.266360 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9913 18:07:07.273201 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9914 18:07:07.276851 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9915 18:07:07.283246 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9916 18:07:07.286600 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9917 18:07:07.293270 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9918 18:07:07.296095 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9919 18:07:07.302756 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9920 18:07:07.306137 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9921 18:07:07.309415 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9922 18:07:07.316347 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9923 18:07:07.319300 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9924 18:07:07.326122 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9925 18:07:07.329341 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9926 18:07:07.336232 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9927 18:07:07.339903 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9928 18:07:07.346321 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9929 18:07:07.349906 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9930 18:07:07.356260 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9931 18:07:07.359240 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9932 18:07:07.366348 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9933 18:07:07.369752 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9934 18:07:07.376118 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9935 18:07:07.379656 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9936 18:07:07.386364 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9937 18:07:07.386449 INFO: [APUAPC] vio 0
9938 18:07:07.393262 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9939 18:07:07.396389 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9940 18:07:07.399970 INFO: [APUAPC] D0_APC_0: 0x400510
9941 18:07:07.403065 INFO: [APUAPC] D0_APC_1: 0x0
9942 18:07:07.406490 INFO: [APUAPC] D0_APC_2: 0x1540
9943 18:07:07.410069 INFO: [APUAPC] D0_APC_3: 0x0
9944 18:07:07.413409 INFO: [APUAPC] D1_APC_0: 0xffffffff
9945 18:07:07.416658 INFO: [APUAPC] D1_APC_1: 0xffffffff
9946 18:07:07.420081 INFO: [APUAPC] D1_APC_2: 0x3fffff
9947 18:07:07.423077 INFO: [APUAPC] D1_APC_3: 0x0
9948 18:07:07.426763 INFO: [APUAPC] D2_APC_0: 0xffffffff
9949 18:07:07.429708 INFO: [APUAPC] D2_APC_1: 0xffffffff
9950 18:07:07.433245 INFO: [APUAPC] D2_APC_2: 0x3fffff
9951 18:07:07.436709 INFO: [APUAPC] D2_APC_3: 0x0
9952 18:07:07.439874 INFO: [APUAPC] D3_APC_0: 0xffffffff
9953 18:07:07.443105 INFO: [APUAPC] D3_APC_1: 0xffffffff
9954 18:07:07.446523 INFO: [APUAPC] D3_APC_2: 0x3fffff
9955 18:07:07.446629 INFO: [APUAPC] D3_APC_3: 0x0
9956 18:07:07.450079 INFO: [APUAPC] D4_APC_0: 0xffffffff
9957 18:07:07.456776 INFO: [APUAPC] D4_APC_1: 0xffffffff
9958 18:07:07.456869 INFO: [APUAPC] D4_APC_2: 0x3fffff
9959 18:07:07.460168 INFO: [APUAPC] D4_APC_3: 0x0
9960 18:07:07.463048 INFO: [APUAPC] D5_APC_0: 0xffffffff
9961 18:07:07.466401 INFO: [APUAPC] D5_APC_1: 0xffffffff
9962 18:07:07.470044 INFO: [APUAPC] D5_APC_2: 0x3fffff
9963 18:07:07.473216 INFO: [APUAPC] D5_APC_3: 0x0
9964 18:07:07.476373 INFO: [APUAPC] D6_APC_0: 0xffffffff
9965 18:07:07.479775 INFO: [APUAPC] D6_APC_1: 0xffffffff
9966 18:07:07.483632 INFO: [APUAPC] D6_APC_2: 0x3fffff
9967 18:07:07.486798 INFO: [APUAPC] D6_APC_3: 0x0
9968 18:07:07.490170 INFO: [APUAPC] D7_APC_0: 0xffffffff
9969 18:07:07.493553 INFO: [APUAPC] D7_APC_1: 0xffffffff
9970 18:07:07.496826 INFO: [APUAPC] D7_APC_2: 0x3fffff
9971 18:07:07.499885 INFO: [APUAPC] D7_APC_3: 0x0
9972 18:07:07.503378 INFO: [APUAPC] D8_APC_0: 0xffffffff
9973 18:07:07.506425 INFO: [APUAPC] D8_APC_1: 0xffffffff
9974 18:07:07.510070 INFO: [APUAPC] D8_APC_2: 0x3fffff
9975 18:07:07.513573 INFO: [APUAPC] D8_APC_3: 0x0
9976 18:07:07.516521 INFO: [APUAPC] D9_APC_0: 0xffffffff
9977 18:07:07.519903 INFO: [APUAPC] D9_APC_1: 0xffffffff
9978 18:07:07.523143 INFO: [APUAPC] D9_APC_2: 0x3fffff
9979 18:07:07.526655 INFO: [APUAPC] D9_APC_3: 0x0
9980 18:07:07.529566 INFO: [APUAPC] D10_APC_0: 0xffffffff
9981 18:07:07.533130 INFO: [APUAPC] D10_APC_1: 0xffffffff
9982 18:07:07.536786 INFO: [APUAPC] D10_APC_2: 0x3fffff
9983 18:07:07.539750 INFO: [APUAPC] D10_APC_3: 0x0
9984 18:07:07.543259 INFO: [APUAPC] D11_APC_0: 0xffffffff
9985 18:07:07.546662 INFO: [APUAPC] D11_APC_1: 0xffffffff
9986 18:07:07.549974 INFO: [APUAPC] D11_APC_2: 0x3fffff
9987 18:07:07.553397 INFO: [APUAPC] D11_APC_3: 0x0
9988 18:07:07.556438 INFO: [APUAPC] D12_APC_0: 0xffffffff
9989 18:07:07.560020 INFO: [APUAPC] D12_APC_1: 0xffffffff
9990 18:07:07.562925 INFO: [APUAPC] D12_APC_2: 0x3fffff
9991 18:07:07.566607 INFO: [APUAPC] D12_APC_3: 0x0
9992 18:07:07.569567 INFO: [APUAPC] D13_APC_0: 0xffffffff
9993 18:07:07.573048 INFO: [APUAPC] D13_APC_1: 0xffffffff
9994 18:07:07.576514 INFO: [APUAPC] D13_APC_2: 0x3fffff
9995 18:07:07.579655 INFO: [APUAPC] D13_APC_3: 0x0
9996 18:07:07.583353 INFO: [APUAPC] D14_APC_0: 0xffffffff
9997 18:07:07.586554 INFO: [APUAPC] D14_APC_1: 0xffffffff
9998 18:07:07.589959 INFO: [APUAPC] D14_APC_2: 0x3fffff
9999 18:07:07.593323 INFO: [APUAPC] D14_APC_3: 0x0
10000 18:07:07.596487 INFO: [APUAPC] D15_APC_0: 0xffffffff
10001 18:07:07.599707 INFO: [APUAPC] D15_APC_1: 0xffffffff
10002 18:07:07.603273 INFO: [APUAPC] D15_APC_2: 0x3fffff
10003 18:07:07.606509 INFO: [APUAPC] D15_APC_3: 0x0
10004 18:07:07.610016 INFO: [APUAPC] APC_CON: 0x4
10005 18:07:07.612932 INFO: [NOCDAPC] D0_APC_0: 0x0
10006 18:07:07.616544 INFO: [NOCDAPC] D0_APC_1: 0x0
10007 18:07:07.616651 INFO: [NOCDAPC] D1_APC_0: 0x0
10008 18:07:07.620062 INFO: [NOCDAPC] D1_APC_1: 0xfff
10009 18:07:07.623027 INFO: [NOCDAPC] D2_APC_0: 0x0
10010 18:07:07.626589 INFO: [NOCDAPC] D2_APC_1: 0xfff
10011 18:07:07.629803 INFO: [NOCDAPC] D3_APC_0: 0x0
10012 18:07:07.632729 INFO: [NOCDAPC] D3_APC_1: 0xfff
10013 18:07:07.636375 INFO: [NOCDAPC] D4_APC_0: 0x0
10014 18:07:07.639264 INFO: [NOCDAPC] D4_APC_1: 0xfff
10015 18:07:07.642834 INFO: [NOCDAPC] D5_APC_0: 0x0
10016 18:07:07.646435 INFO: [NOCDAPC] D5_APC_1: 0xfff
10017 18:07:07.649479 INFO: [NOCDAPC] D6_APC_0: 0x0
10018 18:07:07.649559 INFO: [NOCDAPC] D6_APC_1: 0xfff
10019 18:07:07.652968 INFO: [NOCDAPC] D7_APC_0: 0x0
10020 18:07:07.655876 INFO: [NOCDAPC] D7_APC_1: 0xfff
10021 18:07:07.659173 INFO: [NOCDAPC] D8_APC_0: 0x0
10022 18:07:07.662590 INFO: [NOCDAPC] D8_APC_1: 0xfff
10023 18:07:07.666093 INFO: [NOCDAPC] D9_APC_0: 0x0
10024 18:07:07.669366 INFO: [NOCDAPC] D9_APC_1: 0xfff
10025 18:07:07.672805 INFO: [NOCDAPC] D10_APC_0: 0x0
10026 18:07:07.675934 INFO: [NOCDAPC] D10_APC_1: 0xfff
10027 18:07:07.679530 INFO: [NOCDAPC] D11_APC_0: 0x0
10028 18:07:07.683425 INFO: [NOCDAPC] D11_APC_1: 0xfff
10029 18:07:07.686276 INFO: [NOCDAPC] D12_APC_0: 0x0
10030 18:07:07.686377 INFO: [NOCDAPC] D12_APC_1: 0xfff
10031 18:07:07.689387 INFO: [NOCDAPC] D13_APC_0: 0x0
10032 18:07:07.692798 INFO: [NOCDAPC] D13_APC_1: 0xfff
10033 18:07:07.695997 INFO: [NOCDAPC] D14_APC_0: 0x0
10034 18:07:07.699673 INFO: [NOCDAPC] D14_APC_1: 0xfff
10035 18:07:07.702949 INFO: [NOCDAPC] D15_APC_0: 0x0
10036 18:07:07.705759 INFO: [NOCDAPC] D15_APC_1: 0xfff
10037 18:07:07.709496 INFO: [NOCDAPC] APC_CON: 0x4
10038 18:07:07.712769 INFO: [APUAPC] set_apusys_apc done
10039 18:07:07.715797 INFO: [DEVAPC] devapc_init done
10040 18:07:07.719582 INFO: GICv3 without legacy support detected.
10041 18:07:07.723022 INFO: ARM GICv3 driver initialized in EL3
10042 18:07:07.726105 INFO: Maximum SPI INTID supported: 639
10043 18:07:07.732900 INFO: BL31: Initializing runtime services
10044 18:07:07.736127 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10045 18:07:07.739632 INFO: SPM: enable CPC mode
10046 18:07:07.746228 INFO: mcdi ready for mcusys-off-idle and system suspend
10047 18:07:07.749143 INFO: BL31: Preparing for EL3 exit to normal world
10048 18:07:07.752633 INFO: Entry point address = 0x80000000
10049 18:07:07.755714 INFO: SPSR = 0x8
10050 18:07:07.760962
10051 18:07:07.761046
10052 18:07:07.761109
10053 18:07:07.764839 Starting depthcharge on Spherion...
10054 18:07:07.764914
10055 18:07:07.764983 Wipe memory regions:
10056 18:07:07.765043
10057 18:07:07.765722 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10058 18:07:07.765824 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10059 18:07:07.765908 Setting prompt string to ['asurada:']
10060 18:07:07.765986 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10061 18:07:07.767671 [0x00000040000000, 0x00000054600000)
10062 18:07:07.890120
10063 18:07:07.890262 [0x00000054660000, 0x00000080000000)
10064 18:07:08.150725
10065 18:07:08.153983 [0x000000821a7280, 0x000000ffe64000)
10066 18:07:08.895456
10067 18:07:08.895619 [0x00000100000000, 0x00000240000000)
10068 18:07:10.786169
10069 18:07:10.789637 Initializing XHCI USB controller at 0x11200000.
10070 18:07:11.827746
10071 18:07:11.831008 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10072 18:07:11.831125
10073 18:07:11.831218
10074 18:07:11.831555 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10076 18:07:11.931942 asurada: tftpboot 192.168.201.1 14291445/tftp-deploy-dii3sy_s/kernel/image.itb 14291445/tftp-deploy-dii3sy_s/kernel/cmdline
10077 18:07:11.932122 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10078 18:07:11.932216 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10079 18:07:11.936674 tftpboot 192.168.201.1 14291445/tftp-deploy-dii3sy_s/kernel/image.ittp-deploy-dii3sy_s/kernel/cmdline
10080 18:07:11.936756
10081 18:07:11.936819 Waiting for link
10082 18:07:12.096913
10083 18:07:12.097063 R8152: Initializing
10084 18:07:12.097132
10085 18:07:12.100346 Version 6 (ocp_data = 5c30)
10086 18:07:12.100426
10087 18:07:12.103742 R8152: Done initializing
10088 18:07:12.103836
10089 18:07:12.103899 Adding net device
10090 18:07:14.069299
10091 18:07:14.069446 done.
10092 18:07:14.069511
10093 18:07:14.069571 MAC: 00:24:32:30:78:52
10094 18:07:14.069629
10095 18:07:14.072180 Sending DHCP discover... done.
10096 18:07:14.072260
10097 18:07:14.075865 Waiting for reply... done.
10098 18:07:14.075945
10099 18:07:14.079255 Sending DHCP request... done.
10100 18:07:14.079348
10101 18:07:14.082131 Waiting for reply... done.
10102 18:07:14.082211
10103 18:07:14.082274 My ip is 192.168.201.14
10104 18:07:14.082333
10105 18:07:14.085862 The DHCP server ip is 192.168.201.1
10106 18:07:14.085943
10107 18:07:14.092196 TFTP server IP predefined by user: 192.168.201.1
10108 18:07:14.092276
10109 18:07:14.098850 Bootfile predefined by user: 14291445/tftp-deploy-dii3sy_s/kernel/image.itb
10110 18:07:14.098930
10111 18:07:14.098994 Sending tftp read request... done.
10112 18:07:14.099053
10113 18:07:14.105988 Waiting for the transfer...
10114 18:07:14.106070
10115 18:07:14.624309 00000000 ################################################################
10116 18:07:14.624479
10117 18:07:15.145089 00080000 ################################################################
10118 18:07:15.145250
10119 18:07:15.661900 00100000 ################################################################
10120 18:07:15.662073
10121 18:07:16.177660 00180000 ################################################################
10122 18:07:16.177800
10123 18:07:16.697508 00200000 ################################################################
10124 18:07:16.697682
10125 18:07:17.219694 00280000 ################################################################
10126 18:07:17.219825
10127 18:07:17.755384 00300000 ################################################################
10128 18:07:17.755527
10129 18:07:18.383291 00380000 ################################################################
10130 18:07:18.383422
10131 18:07:19.014894 00400000 ################################################################
10132 18:07:19.015031
10133 18:07:19.562139 00480000 ################################################################
10134 18:07:19.562272
10135 18:07:20.110964 00500000 ################################################################
10136 18:07:20.111156
10137 18:07:20.658901 00580000 ################################################################
10138 18:07:20.659049
10139 18:07:21.192257 00600000 ################################################################
10140 18:07:21.192413
10141 18:07:21.713555 00680000 ################################################################
10142 18:07:21.713708
10143 18:07:22.236363 00700000 ################################################################
10144 18:07:22.236517
10145 18:07:22.755825 00780000 ################################################################
10146 18:07:22.755984
10147 18:07:23.287847 00800000 ################################################################
10148 18:07:23.287989
10149 18:07:23.808527 00880000 ################################################################
10150 18:07:23.808673
10151 18:07:24.329138 00900000 ################################################################
10152 18:07:24.329284
10153 18:07:24.856162 00980000 ################################################################
10154 18:07:24.856305
10155 18:07:25.389633 00a00000 ################################################################
10156 18:07:25.389805
10157 18:07:25.924450 00a80000 ################################################################
10158 18:07:25.924651
10159 18:07:26.451427 00b00000 ################################################################
10160 18:07:26.451573
10161 18:07:26.973568 00b80000 ################################################################
10162 18:07:26.973732
10163 18:07:27.493878 00c00000 ################################################################
10164 18:07:27.494016
10165 18:07:28.017233 00c80000 ################################################################
10166 18:07:28.017366
10167 18:07:28.637677 00d00000 ################################################################
10168 18:07:28.637819
10169 18:07:29.259763 00d80000 ################################################################
10170 18:07:29.259907
10171 18:07:29.820711 00e00000 ################################################################
10172 18:07:29.820891
10173 18:07:30.350442 00e80000 ################################################################
10174 18:07:30.350579
10175 18:07:30.886354 00f00000 ################################################################
10176 18:07:30.886489
10177 18:07:31.423347 00f80000 ################################################################
10178 18:07:31.423489
10179 18:07:31.952232 01000000 ################################################################
10180 18:07:31.952372
10181 18:07:32.478078 01080000 ################################################################
10182 18:07:32.478216
10183 18:07:33.007491 01100000 ################################################################
10184 18:07:33.007712
10185 18:07:33.533504 01180000 ################################################################
10186 18:07:33.533636
10187 18:07:34.064259 01200000 ################################################################
10188 18:07:34.064415
10189 18:07:34.596584 01280000 ################################################################
10190 18:07:34.596713
10191 18:07:35.121846 01300000 ################################################################
10192 18:07:35.121977
10193 18:07:35.645539 01380000 ################################################################
10194 18:07:35.645708
10195 18:07:36.181965 01400000 ################################################################
10196 18:07:36.182126
10197 18:07:36.739849 01480000 ################################################################
10198 18:07:36.740025
10199 18:07:37.296728 01500000 ################################################################
10200 18:07:37.296894
10201 18:07:37.844919 01580000 ################################################################
10202 18:07:37.845095
10203 18:07:38.371437 01600000 ################################################################
10204 18:07:38.371603
10205 18:07:38.890765 01680000 ################################################################
10206 18:07:38.890927
10207 18:07:39.414530 01700000 ################################################################
10208 18:07:39.414664
10209 18:07:39.979405 01780000 ################################################################
10210 18:07:39.979559
10211 18:07:40.556311 01800000 ################################################################
10212 18:07:40.556447
10213 18:07:41.123226 01880000 ################################################################
10214 18:07:41.123370
10215 18:07:41.691129 01900000 ################################################################
10216 18:07:41.691288
10217 18:07:42.239101 01980000 ################################################################
10218 18:07:42.239231
10219 18:07:42.801991 01a00000 ################################################################
10220 18:07:42.802122
10221 18:07:43.362635 01a80000 ################################################################
10222 18:07:43.362768
10223 18:07:43.938557 01b00000 ################################################################
10224 18:07:43.938692
10225 18:07:44.498452 01b80000 ################################################################
10226 18:07:44.498591
10227 18:07:45.057122 01c00000 ################################################################
10228 18:07:45.057255
10229 18:07:45.694015 01c80000 ################################################################
10230 18:07:45.694149
10231 18:07:46.266906 01d00000 ################################################################
10232 18:07:46.267050
10233 18:07:46.936281 01d80000 ################################################################
10234 18:07:46.936436
10235 18:07:47.572716 01e00000 ################################################################
10236 18:07:47.573239
10237 18:07:48.175890 01e80000 ################################################################
10238 18:07:48.176031
10239 18:07:48.722911 01f00000 ################################################################
10240 18:07:48.723045
10241 18:07:49.359171 01f80000 ################################################################
10242 18:07:49.359304
10243 18:07:49.914974 02000000 ################################################################
10244 18:07:49.915104
10245 18:07:50.457537 02080000 ################################################################
10246 18:07:50.457667
10247 18:07:51.009603 02100000 ################################################################
10248 18:07:51.009734
10249 18:07:51.569424 02180000 ################################################################
10250 18:07:51.569579
10251 18:07:52.167103 02200000 ################################################################
10252 18:07:52.167239
10253 18:07:52.736038 02280000 ################################################################
10254 18:07:52.736206
10255 18:07:53.326310 02300000 ################################################################
10256 18:07:53.326448
10257 18:07:53.977508 02380000 ################################################################
10258 18:07:53.978217
10259 18:07:54.578724 02400000 ################################################################
10260 18:07:54.578861
10261 18:07:55.192823 02480000 ################################################################
10262 18:07:55.192961
10263 18:07:55.780043 02500000 ################################################################
10264 18:07:55.780282
10265 18:07:56.464125 02580000 ################################################################
10266 18:07:56.464638
10267 18:07:57.176866 02600000 ################################################################
10268 18:07:57.177446
10269 18:07:57.806429 02680000 ################################################################
10270 18:07:57.806568
10271 18:07:58.503873 02700000 ################################################################
10272 18:07:58.504361
10273 18:07:59.174078 02780000 ################################################################
10274 18:07:59.174216
10275 18:07:59.860361 02800000 ################################################################
10276 18:07:59.860846
10277 18:08:00.522320 02880000 ################################################################
10278 18:08:00.522462
10279 18:08:01.157526 02900000 ################################################################
10280 18:08:01.158010
10281 18:08:01.851124 02980000 ################################################################
10282 18:08:01.851708
10283 18:08:02.512001 02a00000 ################################################################
10284 18:08:02.512648
10285 18:08:03.205342 02a80000 ################################################################
10286 18:08:03.205952
10287 18:08:03.855143 02b00000 ################################################################
10288 18:08:03.855633
10289 18:08:04.543984 02b80000 ################################################################
10290 18:08:04.544600
10291 18:08:05.197387 02c00000 ################################################################
10292 18:08:05.197528
10293 18:08:05.882938 02c80000 ################################################################
10294 18:08:05.883562
10295 18:08:06.481199 02d00000 ################################################################
10296 18:08:06.481336
10297 18:08:07.093575 02d80000 ################################################################
10298 18:08:07.094192
10299 18:08:07.757199 02e00000 ################################################################
10300 18:08:07.757333
10301 18:08:08.382553 02e80000 ################################################################
10302 18:08:08.383044
10303 18:08:09.096118 02f00000 ################################################################
10304 18:08:09.096644
10305 18:08:09.746978 02f80000 ################################################################
10306 18:08:09.747125
10307 18:08:10.310532 03000000 ################################################################
10308 18:08:10.310706
10309 18:08:10.864667 03080000 ################################################################
10310 18:08:10.864796
10311 18:08:11.421747 03100000 ################################################################
10312 18:08:11.421922
10313 18:08:11.960392 03180000 ################################################################
10314 18:08:11.960561
10315 18:08:12.512300 03200000 ################################################################
10316 18:08:12.512437
10317 18:08:13.053141 03280000 ################################################################
10318 18:08:13.053275
10319 18:08:13.572402 03300000 ################################################################
10320 18:08:13.572561
10321 18:08:14.094520 03380000 ################################################################
10322 18:08:14.094655
10323 18:08:14.625851 03400000 ################################################################
10324 18:08:14.625986
10325 18:08:15.148687 03480000 ################################################################
10326 18:08:15.148854
10327 18:08:15.674186 03500000 ################################################################
10328 18:08:15.674345
10329 18:08:16.242807 03580000 ################################################################
10330 18:08:16.242948
10331 18:08:16.813754 03600000 ################################################################
10332 18:08:16.813888
10333 18:08:17.344604 03680000 ################################################################
10334 18:08:17.344738
10335 18:08:17.872887 03700000 ################################################################
10336 18:08:17.873045
10337 18:08:18.408687 03780000 ################################################################
10338 18:08:18.408883
10339 18:08:18.959502 03800000 ################################################################
10340 18:08:18.959641
10341 18:08:19.506268 03880000 ################################################################
10342 18:08:19.506398
10343 18:08:20.056733 03900000 ################################################################
10344 18:08:20.056901
10345 18:08:20.595191 03980000 ################################################################
10346 18:08:20.595330
10347 18:08:21.152148 03a00000 ################################################################
10348 18:08:21.152311
10349 18:08:21.703496 03a80000 ################################################################
10350 18:08:21.703646
10351 18:08:22.280187 03b00000 ################################################################
10352 18:08:22.280334
10353 18:08:22.854486 03b80000 ################################################################
10354 18:08:22.854617
10355 18:08:23.433238 03c00000 ################################################################
10356 18:08:23.433384
10357 18:08:23.996767 03c80000 ################################################################
10358 18:08:23.996968
10359 18:08:24.565050 03d00000 ################################################################
10360 18:08:24.565211
10361 18:08:25.125190 03d80000 ################################################################
10362 18:08:25.125355
10363 18:08:25.694458 03e00000 ################################################################
10364 18:08:25.694654
10365 18:08:26.258298 03e80000 ################################################################
10366 18:08:26.258446
10367 18:08:26.812258 03f00000 ################################################################
10368 18:08:26.812451
10369 18:08:27.374802 03f80000 ################################################################
10370 18:08:27.374991
10371 18:08:27.925668 04000000 ################################################################
10372 18:08:27.925833
10373 18:08:28.483634 04080000 ################################################################
10374 18:08:28.483781
10375 18:08:29.047868 04100000 ################################################################
10376 18:08:29.048013
10377 18:08:29.609952 04180000 ################################################################
10378 18:08:29.610104
10379 18:08:30.185296 04200000 ################################################################
10380 18:08:30.185482
10381 18:08:30.803687 04280000 ################################################################
10382 18:08:30.803883
10383 18:08:31.441241 04300000 ################################################################
10384 18:08:31.441372
10385 18:08:32.109353 04380000 ################################################################
10386 18:08:32.109990
10387 18:08:32.732837 04400000 ################################################################
10388 18:08:32.732979
10389 18:08:33.352443 04480000 ################################################################
10390 18:08:33.353147
10391 18:08:33.976657 04500000 ################################################################
10392 18:08:33.976804
10393 18:08:34.593383 04580000 ################################################################
10394 18:08:34.593586
10395 18:08:35.248041 04600000 ################################################################
10396 18:08:35.248385
10397 18:08:35.551508 04680000 ############################### done.
10398 18:08:35.551999
10399 18:08:35.554745 The bootfile was 74175854 bytes long.
10400 18:08:35.555204
10401 18:08:35.558347 Sending tftp read request... done.
10402 18:08:35.558666
10403 18:08:35.558980 Waiting for the transfer...
10404 18:08:35.559279
10405 18:08:35.561321 00000000 # done.
10406 18:08:35.561639
10407 18:08:35.568232 Command line loaded dynamically from TFTP file: 14291445/tftp-deploy-dii3sy_s/kernel/cmdline
10408 18:08:35.568613
10409 18:08:35.581704 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10410 18:08:35.582071
10411 18:08:35.584903 Loading FIT.
10412 18:08:35.585296
10413 18:08:35.588199 Image ramdisk-1 has 61001459 bytes.
10414 18:08:35.588553
10415 18:08:35.588797 Image fdt-1 has 47258 bytes.
10416 18:08:35.591734
10417 18:08:35.592027 Image kernel-1 has 13125101 bytes.
10418 18:08:35.592324
10419 18:08:35.601504 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10420 18:08:35.601875
10421 18:08:35.617866 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10422 18:08:35.618245
10423 18:08:35.624689 Choosing best match conf-1 for compat google,spherion-rev2.
10424 18:08:35.629474
10425 18:08:35.634046 Connected to device vid:did:rid of 1ae0:0028:00
10426 18:08:35.641537
10427 18:08:35.645363 tpm_get_response: command 0x17b, return code 0x0
10428 18:08:35.645720
10429 18:08:35.648384 ec_init: CrosEC protocol v3 supported (256, 248)
10430 18:08:35.652138
10431 18:08:35.655846 tpm_cleanup: add release locality here.
10432 18:08:35.656200
10433 18:08:35.656431 Shutting down all USB controllers.
10434 18:08:35.659280
10435 18:08:35.659631 Removing current net device
10436 18:08:35.659875
10437 18:08:35.665757 Exiting depthcharge with code 4 at timestamp: 117342724
10438 18:08:35.666101
10439 18:08:35.669355 LZMA decompressing kernel-1 to 0x821a6718
10440 18:08:35.669647
10441 18:08:35.672146 LZMA decompressing kernel-1 to 0x40000000
10442 18:08:37.289785
10443 18:08:37.290273 jumping to kernel
10444 18:08:37.292261 end: 2.2.4 bootloader-commands (duration 00:01:30) [common]
10445 18:08:37.292737 start: 2.2.5 auto-login-action (timeout 00:02:56) [common]
10446 18:08:37.293141 Setting prompt string to ['Linux version [0-9]']
10447 18:08:37.293488 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10448 18:08:37.293927 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10449 18:08:37.371986
10450 18:08:37.375132 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10451 18:08:37.379056 start: 2.2.5.1 login-action (timeout 00:02:55) [common]
10452 18:08:37.379402 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10453 18:08:37.379665 Setting prompt string to []
10454 18:08:37.379938 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10455 18:08:37.380201 Using line separator: #'\n'#
10456 18:08:37.380417 No login prompt set.
10457 18:08:37.380637 Parsing kernel messages
10458 18:08:37.380942 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10459 18:08:37.381381 [login-action] Waiting for messages, (timeout 00:02:55)
10460 18:08:37.381911 Waiting using forced prompt support (timeout 00:01:28)
10461 18:08:37.398475 [ 0.000000] Linux version 6.1.92-cip22 (KernelCI@build-j225340-arm64-gcc-10-defconfig-arm64-chromebook-x2t4v) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue Jun 11 17:44:14 UTC 2024
10462 18:08:37.402003 [ 0.000000] random: crng init done
10463 18:08:37.408662 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10464 18:08:37.409191 [ 0.000000] efi: UEFI not found.
10465 18:08:37.418772 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10466 18:08:37.425527 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10467 18:08:37.435303 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10468 18:08:37.445315 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10469 18:08:37.451441 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10470 18:08:37.454850 [ 0.000000] printk: bootconsole [mtk8250] enabled
10471 18:08:37.463722 [ 0.000000] NUMA: No NUMA configuration found
10472 18:08:37.470404 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10473 18:08:37.477045 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10474 18:08:37.477219 [ 0.000000] Zone ranges:
10475 18:08:37.484000 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10476 18:08:37.487330 [ 0.000000] DMA32 empty
10477 18:08:37.493776 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10478 18:08:37.497253 [ 0.000000] Movable zone start for each node
10479 18:08:37.500716 [ 0.000000] Early memory node ranges
10480 18:08:37.507150 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10481 18:08:37.514102 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10482 18:08:37.521123 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10483 18:08:37.527282 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10484 18:08:37.533464 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10485 18:08:37.540024 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10486 18:08:37.596507 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10487 18:08:37.602963 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10488 18:08:37.610036 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10489 18:08:37.612953 [ 0.000000] psci: probing for conduit method from DT.
10490 18:08:37.619584 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10491 18:08:37.622865 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10492 18:08:37.630369 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10493 18:08:37.633098 [ 0.000000] psci: SMC Calling Convention v1.2
10494 18:08:37.640304 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10495 18:08:37.643665 [ 0.000000] Detected VIPT I-cache on CPU0
10496 18:08:37.650087 [ 0.000000] CPU features: detected: GIC system register CPU interface
10497 18:08:37.656573 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10498 18:08:37.663086 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10499 18:08:37.670002 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10500 18:08:37.676569 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10501 18:08:37.683017 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10502 18:08:37.689822 [ 0.000000] alternatives: applying boot alternatives
10503 18:08:37.693292 [ 0.000000] Fallback order for Node 0: 0
10504 18:08:37.703104 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10505 18:08:37.703406 [ 0.000000] Policy zone: Normal
10506 18:08:37.719486 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10507 18:08:37.729399 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10508 18:08:37.741475 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10509 18:08:37.751139 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10510 18:08:37.757830 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10511 18:08:37.761412 <6>[ 0.000000] software IO TLB: area num 8.
10512 18:08:37.817287 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10513 18:08:37.967287 <6>[ 0.000000] Memory: 7904488K/8385536K available (18112K kernel code, 4120K rwdata, 22644K rodata, 8512K init, 616K bss, 448280K reserved, 32768K cma-reserved)
10514 18:08:37.974118 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10515 18:08:37.980449 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10516 18:08:37.983645 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10517 18:08:37.990846 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10518 18:08:37.997485 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10519 18:08:38.000827 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10520 18:08:38.010608 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10521 18:08:38.017153 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10522 18:08:38.020478 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10523 18:08:38.028149 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10524 18:08:38.031692 <6>[ 0.000000] GICv3: 608 SPIs implemented
10525 18:08:38.038366 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10526 18:08:38.041683 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10527 18:08:38.044917 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10528 18:08:38.054651 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10529 18:08:38.065156 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10530 18:08:38.078550 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10531 18:08:38.084831 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10532 18:08:38.093903 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10533 18:08:38.107534 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10534 18:08:38.114179 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10535 18:08:38.120869 <6>[ 0.009180] Console: colour dummy device 80x25
10536 18:08:38.130540 <6>[ 0.013909] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10537 18:08:38.133829 <6>[ 0.024416] pid_max: default: 32768 minimum: 301
10538 18:08:38.140822 <6>[ 0.029287] LSM: Security Framework initializing
10539 18:08:38.147113 <6>[ 0.034225] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10540 18:08:38.157224 <6>[ 0.042087] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10541 18:08:38.163712 <6>[ 0.051509] cblist_init_generic: Setting adjustable number of callback queues.
10542 18:08:38.170559 <6>[ 0.058953] cblist_init_generic: Setting shift to 3 and lim to 1.
10543 18:08:38.177022 <6>[ 0.065332] cblist_init_generic: Setting adjustable number of callback queues.
10544 18:08:38.183715 <6>[ 0.072759] cblist_init_generic: Setting shift to 3 and lim to 1.
10545 18:08:38.190793 <6>[ 0.079162] rcu: Hierarchical SRCU implementation.
10546 18:08:38.193938 <6>[ 0.084177] rcu: Max phase no-delay instances is 1000.
10547 18:08:38.202357 <6>[ 0.091235] EFI services will not be available.
10548 18:08:38.205725 <6>[ 0.096192] smp: Bringing up secondary CPUs ...
10549 18:08:38.214736 <6>[ 0.101243] Detected VIPT I-cache on CPU1
10550 18:08:38.221222 <6>[ 0.101313] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10551 18:08:38.227871 <6>[ 0.101345] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10552 18:08:38.231525 <6>[ 0.101677] Detected VIPT I-cache on CPU2
10553 18:08:38.237891 <6>[ 0.101730] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10554 18:08:38.244740 <6>[ 0.101749] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10555 18:08:38.251068 <6>[ 0.102005] Detected VIPT I-cache on CPU3
10556 18:08:38.258001 <6>[ 0.102052] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10557 18:08:38.264572 <6>[ 0.102066] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10558 18:08:38.267764 <6>[ 0.102371] CPU features: detected: Spectre-v4
10559 18:08:38.274517 <6>[ 0.102377] CPU features: detected: Spectre-BHB
10560 18:08:38.278028 <6>[ 0.102382] Detected PIPT I-cache on CPU4
10561 18:08:38.284400 <6>[ 0.102439] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10562 18:08:38.291174 <6>[ 0.102455] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10563 18:08:38.298072 <6>[ 0.102749] Detected PIPT I-cache on CPU5
10564 18:08:38.304492 <6>[ 0.102810] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10565 18:08:38.311272 <6>[ 0.102827] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10566 18:08:38.314290 <6>[ 0.103111] Detected PIPT I-cache on CPU6
10567 18:08:38.321043 <6>[ 0.103170] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10568 18:08:38.327749 <6>[ 0.103186] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10569 18:08:38.331105 <6>[ 0.103470] Detected PIPT I-cache on CPU7
10570 18:08:38.341393 <6>[ 0.103528] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10571 18:08:38.348074 <6>[ 0.103544] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10572 18:08:38.351444 <6>[ 0.103591] smp: Brought up 1 node, 8 CPUs
10573 18:08:38.354460 <6>[ 0.244970] SMP: Total of 8 processors activated.
10574 18:08:38.361391 <6>[ 0.249891] CPU features: detected: 32-bit EL0 Support
10575 18:08:38.371747 <6>[ 0.255288] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10576 18:08:38.377983 <6>[ 0.264089] CPU features: detected: Common not Private translations
10577 18:08:38.381468 <6>[ 0.270565] CPU features: detected: CRC32 instructions
10578 18:08:38.387777 <6>[ 0.275916] CPU features: detected: RCpc load-acquire (LDAPR)
10579 18:08:38.394725 <6>[ 0.281876] CPU features: detected: LSE atomic instructions
10580 18:08:38.397783 <6>[ 0.287694] CPU features: detected: Privileged Access Never
10581 18:08:38.404972 <6>[ 0.293473] CPU features: detected: RAS Extension Support
10582 18:08:38.411474 <6>[ 0.299082] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10583 18:08:38.417921 <6>[ 0.306302] CPU: All CPU(s) started at EL2
10584 18:08:38.421012 <6>[ 0.310645] alternatives: applying system-wide alternatives
10585 18:08:38.432289 <6>[ 0.321439] devtmpfs: initialized
10586 18:08:38.444619 <6>[ 0.330367] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10587 18:08:38.454594 <6>[ 0.340327] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10588 18:08:38.461241 <6>[ 0.348341] pinctrl core: initialized pinctrl subsystem
10589 18:08:38.464718 <6>[ 0.354976] DMI not present or invalid.
10590 18:08:38.471226 <6>[ 0.359391] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10591 18:08:38.477782 <6>[ 0.366249] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10592 18:08:38.487986 <6>[ 0.373838] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10593 18:08:38.494494 <6>[ 0.382058] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10594 18:08:38.501265 <6>[ 0.390301] audit: initializing netlink subsys (disabled)
10595 18:08:38.511041 <5>[ 0.395994] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10596 18:08:38.514701 <6>[ 0.396716] thermal_sys: Registered thermal governor 'step_wise'
10597 18:08:38.521186 <6>[ 0.403963] thermal_sys: Registered thermal governor 'power_allocator'
10598 18:08:38.527942 <6>[ 0.410217] cpuidle: using governor menu
10599 18:08:38.531044 <6>[ 0.421183] NET: Registered PF_QIPCRTR protocol family
10600 18:08:38.541530 <6>[ 0.426666] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10601 18:08:38.544418 <6>[ 0.433768] ASID allocator initialised with 32768 entries
10602 18:08:38.551367 <6>[ 0.440350] Serial: AMBA PL011 UART driver
10603 18:08:38.560175 <4>[ 0.449186] Trying to register duplicate clock ID: 134
10604 18:08:38.619876 <6>[ 0.512344] KASLR enabled
10605 18:08:38.634458 <6>[ 0.520107] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10606 18:08:38.641172 <6>[ 0.527119] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10607 18:08:38.647893 <6>[ 0.533607] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10608 18:08:38.654298 <6>[ 0.540612] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10609 18:08:38.661231 <6>[ 0.547099] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10610 18:08:38.667745 <6>[ 0.554103] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10611 18:08:38.674330 <6>[ 0.560592] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10612 18:08:38.680954 <6>[ 0.567595] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10613 18:08:38.684355 <6>[ 0.575117] ACPI: Interpreter disabled.
10614 18:08:38.692677 <6>[ 0.581560] iommu: Default domain type: Translated
10615 18:08:38.698950 <6>[ 0.586672] iommu: DMA domain TLB invalidation policy: strict mode
10616 18:08:38.702431 <5>[ 0.593333] SCSI subsystem initialized
10617 18:08:38.709004 <6>[ 0.597501] usbcore: registered new interface driver usbfs
10618 18:08:38.715936 <6>[ 0.603234] usbcore: registered new interface driver hub
10619 18:08:38.719228 <6>[ 0.608783] usbcore: registered new device driver usb
10620 18:08:38.726217 <6>[ 0.614889] pps_core: LinuxPPS API ver. 1 registered
10621 18:08:38.735816 <6>[ 0.620083] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10622 18:08:38.739078 <6>[ 0.629430] PTP clock support registered
10623 18:08:38.742682 <6>[ 0.633671] EDAC MC: Ver: 3.0.0
10624 18:08:38.749618 <6>[ 0.638830] FPGA manager framework
10625 18:08:38.753333 <6>[ 0.642516] Advanced Linux Sound Architecture Driver Initialized.
10626 18:08:38.756938 <6>[ 0.649308] vgaarb: loaded
10627 18:08:38.763655 <6>[ 0.652452] clocksource: Switched to clocksource arch_sys_counter
10628 18:08:38.770135 <5>[ 0.658902] VFS: Disk quotas dquot_6.6.0
10629 18:08:38.777924 <6>[ 0.663089] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10630 18:08:38.780461 <6>[ 0.670282] pnp: PnP ACPI: disabled
10631 18:08:38.787938 <6>[ 0.677054] NET: Registered PF_INET protocol family
10632 18:08:38.794562 <6>[ 0.682643] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10633 18:08:38.809040 <6>[ 0.694967] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10634 18:08:38.819652 <6>[ 0.703781] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10635 18:08:38.825789 <6>[ 0.711754] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10636 18:08:38.832812 <6>[ 0.720457] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10637 18:08:38.844501 <6>[ 0.730213] TCP: Hash tables configured (established 65536 bind 65536)
10638 18:08:38.851474 <6>[ 0.737079] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10639 18:08:38.857984 <6>[ 0.744278] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10640 18:08:38.864643 <6>[ 0.751982] NET: Registered PF_UNIX/PF_LOCAL protocol family
10641 18:08:38.870911 <6>[ 0.758130] RPC: Registered named UNIX socket transport module.
10642 18:08:38.874533 <6>[ 0.764285] RPC: Registered udp transport module.
10643 18:08:38.880925 <6>[ 0.769220] RPC: Registered tcp transport module.
10644 18:08:38.887900 <6>[ 0.774154] RPC: Registered tcp NFSv4.1 backchannel transport module.
10645 18:08:38.891217 <6>[ 0.780821] PCI: CLS 0 bytes, default 64
10646 18:08:38.894124 <6>[ 0.785126] Unpacking initramfs...
10647 18:08:38.915668 <6>[ 0.801037] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10648 18:08:38.925263 <6>[ 0.809677] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10649 18:08:38.928899 <6>[ 0.818534] kvm [1]: IPA Size Limit: 40 bits
10650 18:08:38.934982 <6>[ 0.823057] kvm [1]: GICv3: no GICV resource entry
10651 18:08:38.938726 <6>[ 0.828079] kvm [1]: disabling GICv2 emulation
10652 18:08:38.945038 <6>[ 0.832767] kvm [1]: GIC system register CPU interface enabled
10653 18:08:38.948243 <6>[ 0.838922] kvm [1]: vgic interrupt IRQ18
10654 18:08:38.955087 <6>[ 0.843278] kvm [1]: VHE mode initialized successfully
10655 18:08:38.961611 <5>[ 0.849660] Initialise system trusted keyrings
10656 18:08:38.968374 <6>[ 0.854472] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10657 18:08:38.975769 <6>[ 0.864675] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10658 18:08:38.982263 <5>[ 0.871125] NFS: Registering the id_resolver key type
10659 18:08:38.985564 <5>[ 0.876432] Key type id_resolver registered
10660 18:08:38.992484 <5>[ 0.880851] Key type id_legacy registered
10661 18:08:38.999063 <6>[ 0.885128] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10662 18:08:39.005445 <6>[ 0.892052] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10663 18:08:39.011848 <6>[ 0.899828] 9p: Installing v9fs 9p2000 file system support
10664 18:08:39.048388 <5>[ 0.937545] Key type asymmetric registered
10665 18:08:39.051507 <5>[ 0.941879] Asymmetric key parser 'x509' registered
10666 18:08:39.061780 <6>[ 0.947015] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10667 18:08:39.065271 <6>[ 0.954628] io scheduler mq-deadline registered
10668 18:08:39.068234 <6>[ 0.959415] io scheduler kyber registered
10669 18:08:39.087790 <6>[ 0.976631] EINJ: ACPI disabled.
10670 18:08:39.121073 <4>[ 1.003388] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10671 18:08:39.131046 <4>[ 1.014013] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10672 18:08:39.145952 <6>[ 1.034960] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10673 18:08:39.153441 <6>[ 1.042842] printk: console [ttyS0] disabled
10674 18:08:39.181844 <6>[ 1.067481] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10675 18:08:39.188734 <6>[ 1.076959] printk: console [ttyS0] enabled
10676 18:08:39.191798 <6>[ 1.076959] printk: console [ttyS0] enabled
10677 18:08:39.195177 <6>[ 1.085855] printk: bootconsole [mtk8250] disabled
10678 18:08:39.202201 <6>[ 1.085855] printk: bootconsole [mtk8250] disabled
10679 18:08:39.208888 <6>[ 1.097125] SuperH (H)SCI(F) driver initialized
10680 18:08:39.211761 <6>[ 1.102410] msm_serial: driver initialized
10681 18:08:39.225721 <6>[ 1.111348] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10682 18:08:39.235732 <6>[ 1.119894] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10683 18:08:39.242571 <6>[ 1.128436] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10684 18:08:39.252415 <6>[ 1.137068] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10685 18:08:39.258904 <6>[ 1.145775] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10686 18:08:39.268687 <6>[ 1.154496] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10687 18:08:39.278821 <6>[ 1.163037] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10688 18:08:39.285230 <6>[ 1.171843] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10689 18:08:39.295199 <6>[ 1.180386] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10690 18:08:39.307169 <6>[ 1.196004] loop: module loaded
10691 18:08:39.313366 <6>[ 1.202037] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10692 18:08:39.336258 <4>[ 1.225617] mtk-pmic-keys: Failed to locate of_node [id: -1]
10693 18:08:39.344013 <6>[ 1.232534] megasas: 07.719.03.00-rc1
10694 18:08:39.353117 <6>[ 1.242147] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10695 18:08:39.362951 <6>[ 1.251830] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10696 18:08:39.379484 <6>[ 1.268350] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10697 18:08:39.436188 <6>[ 1.318349] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10698 18:08:41.610296 <6>[ 3.499562] Freeing initrd memory: 59568K
10699 18:08:41.621734 <6>[ 3.510956] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10700 18:08:41.632404 <6>[ 3.521852] tun: Universal TUN/TAP device driver, 1.6
10701 18:08:41.635927 <6>[ 3.527911] thunder_xcv, ver 1.0
10702 18:08:41.639449 <6>[ 3.531419] thunder_bgx, ver 1.0
10703 18:08:41.642344 <6>[ 3.534918] nicpf, ver 1.0
10704 18:08:41.653028 <6>[ 3.538935] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10705 18:08:41.656554 <6>[ 3.546411] hns3: Copyright (c) 2017 Huawei Corporation.
10706 18:08:41.659349 <6>[ 3.551999] hclge is initializing
10707 18:08:41.666095 <6>[ 3.555575] e1000: Intel(R) PRO/1000 Network Driver
10708 18:08:41.673050 <6>[ 3.560704] e1000: Copyright (c) 1999-2006 Intel Corporation.
10709 18:08:41.675931 <6>[ 3.566716] e1000e: Intel(R) PRO/1000 Network Driver
10710 18:08:41.682699 <6>[ 3.571932] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10711 18:08:41.689501 <6>[ 3.578116] igb: Intel(R) Gigabit Ethernet Network Driver
10712 18:08:41.695952 <6>[ 3.583766] igb: Copyright (c) 2007-2014 Intel Corporation.
10713 18:08:41.702855 <6>[ 3.589603] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10714 18:08:41.709247 <6>[ 3.596121] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10715 18:08:41.712550 <6>[ 3.602582] sky2: driver version 1.30
10716 18:08:41.719260 <6>[ 3.607504] usbcore: registered new device driver r8152-cfgselector
10717 18:08:41.726108 <6>[ 3.614042] usbcore: registered new interface driver r8152
10718 18:08:41.728993 <6>[ 3.619852] VFIO - User Level meta-driver version: 0.3
10719 18:08:41.738362 <6>[ 3.628110] usbcore: registered new interface driver usb-storage
10720 18:08:41.745067 <6>[ 3.634559] usbcore: registered new device driver onboard-usb-hub
10721 18:08:41.754406 <6>[ 3.643682] mt6397-rtc mt6359-rtc: registered as rtc0
10722 18:08:41.764517 <6>[ 3.649150] mt6397-rtc mt6359-rtc: setting system clock to 2024-06-11T18:08:41 UTC (1718129321)
10723 18:08:41.767980 <6>[ 3.658709] i2c_dev: i2c /dev entries driver
10724 18:08:41.781592 <4>[ 3.670708] cpu cpu0: supply cpu not found, using dummy regulator
10725 18:08:41.788247 <4>[ 3.677135] cpu cpu1: supply cpu not found, using dummy regulator
10726 18:08:41.794680 <4>[ 3.683539] cpu cpu2: supply cpu not found, using dummy regulator
10727 18:08:41.801446 <4>[ 3.689936] cpu cpu3: supply cpu not found, using dummy regulator
10728 18:08:41.808146 <4>[ 3.696347] cpu cpu4: supply cpu not found, using dummy regulator
10729 18:08:41.814415 <4>[ 3.702749] cpu cpu5: supply cpu not found, using dummy regulator
10730 18:08:41.821004 <4>[ 3.709145] cpu cpu6: supply cpu not found, using dummy regulator
10731 18:08:41.827421 <4>[ 3.715542] cpu cpu7: supply cpu not found, using dummy regulator
10732 18:08:41.847673 <6>[ 3.737201] cpu cpu0: EM: created perf domain
10733 18:08:41.850898 <6>[ 3.742125] cpu cpu4: EM: created perf domain
10734 18:08:41.858236 <6>[ 3.747706] sdhci: Secure Digital Host Controller Interface driver
10735 18:08:41.864825 <6>[ 3.754138] sdhci: Copyright(c) Pierre Ossman
10736 18:08:41.871517 <6>[ 3.759092] Synopsys Designware Multimedia Card Interface Driver
10737 18:08:41.878253 <6>[ 3.765727] sdhci-pltfm: SDHCI platform and OF driver helper
10738 18:08:41.881642 <6>[ 3.765750] mmc0: CQHCI version 5.10
10739 18:08:41.887892 <6>[ 3.775652] ledtrig-cpu: registered to indicate activity on CPUs
10740 18:08:41.894734 <6>[ 3.782633] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10741 18:08:41.900994 <6>[ 3.789689] usbcore: registered new interface driver usbhid
10742 18:08:41.904355 <6>[ 3.795510] usbhid: USB HID core driver
10743 18:08:41.911402 <6>[ 3.799704] spi_master spi0: will run message pump with realtime priority
10744 18:08:41.957670 <6>[ 3.840320] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10745 18:08:41.977424 <6>[ 3.856628] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10746 18:08:41.980248 <6>[ 3.866325] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x16014
10747 18:08:41.987622 <6>[ 3.877035] cros-ec-spi spi0.0: Chrome EC device registered
10748 18:08:41.994410 <6>[ 3.883064] mmc0: Command Queue Engine enabled
10749 18:08:42.001281 <6>[ 3.887846] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10750 18:08:42.004210 <6>[ 3.895495] mmcblk0: mmc0:0001 DA4128 116 GiB
10751 18:08:42.014734 <6>[ 3.904248] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10752 18:08:42.022950 <6>[ 3.912051] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10753 18:08:42.029317 <6>[ 3.918103] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10754 18:08:42.039502 <6>[ 3.918232] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10755 18:08:42.045770 <6>[ 3.923978] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10756 18:08:42.048970 <6>[ 3.934033] NET: Registered PF_PACKET protocol family
10757 18:08:42.056306 <6>[ 3.944564] 9pnet: Installing 9P2000 support
10758 18:08:42.059174 <5>[ 3.949126] Key type dns_resolver registered
10759 18:08:42.062603 <6>[ 3.954117] registered taskstats version 1
10760 18:08:42.069509 <5>[ 3.958501] Loading compiled-in X.509 certificates
10761 18:08:42.099056 <4>[ 3.982072] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10762 18:08:42.109403 <4>[ 3.992798] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10763 18:08:42.128090 <6>[ 4.018061] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10764 18:08:42.135545 <6>[ 4.024998] xhci-mtk 11200000.usb: xHCI Host Controller
10765 18:08:42.141956 <6>[ 4.030504] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10766 18:08:42.151794 <6>[ 4.038364] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10767 18:08:42.158534 <6>[ 4.047797] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10768 18:08:42.165176 <6>[ 4.053970] xhci-mtk 11200000.usb: xHCI Host Controller
10769 18:08:42.172182 <6>[ 4.059463] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10770 18:08:42.178357 <6>[ 4.067115] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10771 18:08:42.185265 <6>[ 4.074923] hub 1-0:1.0: USB hub found
10772 18:08:42.188779 <6>[ 4.078946] hub 1-0:1.0: 1 port detected
10773 18:08:42.198935 <6>[ 4.083229] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10774 18:08:42.201952 <6>[ 4.091904] hub 2-0:1.0: USB hub found
10775 18:08:42.205196 <6>[ 4.095921] hub 2-0:1.0: 1 port detected
10776 18:08:42.213289 <6>[ 4.103149] mtk-msdc 11f70000.mmc: Got CD GPIO
10777 18:08:42.230820 <6>[ 4.117271] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10778 18:08:42.240959 <6>[ 4.125705] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10779 18:08:42.247944 <6>[ 4.134048] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10780 18:08:42.257870 <6>[ 4.142401] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10781 18:08:42.264290 <6>[ 4.150740] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10782 18:08:42.274297 <6>[ 4.159089] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10783 18:08:42.280863 <6>[ 4.167429] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10784 18:08:42.291039 <6>[ 4.175777] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10785 18:08:42.297986 <6>[ 4.184118] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10786 18:08:42.307705 <6>[ 4.192468] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10787 18:08:42.314349 <6>[ 4.200810] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10788 18:08:42.324047 <6>[ 4.209159] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10789 18:08:42.331005 <6>[ 4.217497] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10790 18:08:42.340616 <6>[ 4.225846] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10791 18:08:42.347397 <6>[ 4.234185] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10792 18:08:42.353912 <6>[ 4.242772] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10793 18:08:42.360645 <6>[ 4.249938] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10794 18:08:42.367217 <6>[ 4.256746] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10795 18:08:42.374127 <6>[ 4.263505] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10796 18:08:42.383946 <6>[ 4.270432] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10797 18:08:42.390838 <6>[ 4.277298] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10798 18:08:42.400700 <6>[ 4.286428] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10799 18:08:42.410718 <6>[ 4.295548] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10800 18:08:42.420675 <6>[ 4.304842] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10801 18:08:42.430799 <6>[ 4.314309] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10802 18:08:42.436893 <6>[ 4.323776] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10803 18:08:42.447349 <6>[ 4.332896] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10804 18:08:42.457197 <6>[ 4.342363] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10805 18:08:42.467155 <6>[ 4.351481] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10806 18:08:42.476904 <6>[ 4.360779] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10807 18:08:42.486554 <6>[ 4.370962] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10808 18:08:42.496441 <6>[ 4.382132] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10809 18:08:42.594781 <6>[ 4.481000] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10810 18:08:42.623532 <6>[ 4.512944] hub 2-1:1.0: USB hub found
10811 18:08:42.626421 <6>[ 4.517445] hub 2-1:1.0: 3 ports detected
10812 18:08:42.636819 <6>[ 4.526392] hub 2-1:1.0: USB hub found
10813 18:08:42.640136 <6>[ 4.530747] hub 2-1:1.0: 3 ports detected
10814 18:08:42.745946 <6>[ 4.632579] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10815 18:08:42.900285 <6>[ 4.790316] hub 1-1:1.0: USB hub found
10816 18:08:42.903762 <6>[ 4.794791] hub 1-1:1.0: 4 ports detected
10817 18:08:42.915490 <6>[ 4.805454] hub 1-1:1.0: USB hub found
10818 18:08:42.918945 <6>[ 4.809860] hub 1-1:1.0: 4 ports detected
10819 18:08:42.978305 <6>[ 4.864987] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10820 18:08:43.086737 <6>[ 4.973412] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10821 18:08:43.123572 <4>[ 5.010316] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10822 18:08:43.133492 <4>[ 5.019451] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10823 18:08:43.172474 <6>[ 5.062308] r8152 2-1.3:1.0 eth0: v1.12.13
10824 18:08:43.238306 <6>[ 5.124771] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10825 18:08:43.370863 <6>[ 5.260745] hub 1-1.4:1.0: USB hub found
10826 18:08:43.374112 <6>[ 5.265416] hub 1-1.4:1.0: 2 ports detected
10827 18:08:43.389157 <6>[ 5.278745] hub 1-1.4:1.0: USB hub found
10828 18:08:43.392021 <6>[ 5.283337] hub 1-1.4:1.0: 2 ports detected
10829 18:08:43.690113 <6>[ 5.576772] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10830 18:08:43.886230 <6>[ 5.772702] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10831 18:08:44.810904 <6>[ 6.701146] r8152 2-1.3:1.0 eth0: carrier on
10832 18:08:47.414286 <5>[ 6.728503] Sending DHCP requests .., OK
10833 18:08:47.421178 <6>[ 9.308923] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.14
10834 18:08:47.424089 <6>[ 9.317216] IP-Config: Complete:
10835 18:08:47.437541 <6>[ 9.320715] device=eth0, hwaddr=00:24:32:30:78:52, ipaddr=192.168.201.14, mask=255.255.255.0, gw=192.168.201.1
10836 18:08:47.443904 <6>[ 9.331423] host=mt8192-asurada-spherion-r0-cbg-3, domain=lava-rack, nis-domain=(none)
10837 18:08:47.450422 <6>[ 9.340041] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10838 18:08:47.457111 <6>[ 9.340050] nameserver0=192.168.201.1
10839 18:08:47.460589 <6>[ 9.352201] clk: Disabling unused clocks
10840 18:08:47.463619 <6>[ 9.357736] ALSA device list:
10841 18:08:47.470431 <6>[ 9.361022] No soundcards found.
10842 18:08:47.478107 <6>[ 9.368728] Freeing unused kernel memory: 8512K
10843 18:08:47.481544 <6>[ 9.373632] Run /init as init process
10844 18:08:47.511660 <6>[ 9.401970] NET: Registered PF_INET6 protocol family
10845 18:08:47.518564 <6>[ 9.408834] Segment Routing with IPv6
10846 18:08:47.521439 <6>[ 9.412778] In-situ OAM (IOAM) with IPv6
10847 18:08:47.562529 <30>[ 9.426345] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10848 18:08:47.569325 <30>[ 9.459381] systemd[1]: Detected architecture arm64.
10849 18:08:47.569409
10850 18:08:47.575822 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10851 18:08:47.575899
10852 18:08:47.594201 <30>[ 9.484736] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10853 18:08:47.718175 <30>[ 9.605413] systemd[1]: Queued start job for default target graphical.target.
10854 18:08:47.771382 <30>[ 9.658269] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10855 18:08:47.777951 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10856 18:08:47.798204 <30>[ 9.685252] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10857 18:08:47.807771 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10858 18:08:47.826233 <30>[ 9.713527] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10859 18:08:47.835925 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10860 18:08:47.854469 <30>[ 9.741632] systemd[1]: Created slice user.slice - User and Session Slice.
10861 18:08:47.860904 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10862 18:08:47.881069 <30>[ 9.764901] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10863 18:08:47.887601 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10864 18:08:47.909160 <30>[ 9.792968] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10865 18:08:47.915568 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10866 18:08:47.943738 <30>[ 9.820833] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10867 18:08:47.953450 <30>[ 9.840626] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10868 18:08:47.960318 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10869 18:08:47.978103 <30>[ 9.865182] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10870 18:08:47.987692 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10871 18:08:48.005845 <30>[ 9.893209] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10872 18:08:48.015905 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10873 18:08:48.030448 <30>[ 9.921285] systemd[1]: Reached target paths.target - Path Units.
10874 18:08:48.040647 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10875 18:08:48.058115 <30>[ 9.945205] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10876 18:08:48.064598 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10877 18:08:48.078027 <30>[ 9.968738] systemd[1]: Reached target slices.target - Slice Units.
10878 18:08:48.088147 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10879 18:08:48.102712 <30>[ 9.993238] systemd[1]: Reached target swap.target - Swaps.
10880 18:08:48.109314 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10881 18:08:48.129865 <30>[ 10.017272] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10882 18:08:48.140339 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10883 18:08:48.157922 <30>[ 10.045251] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10884 18:08:48.168068 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10885 18:08:48.187746 <30>[ 10.074962] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10886 18:08:48.197783 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10887 18:08:48.214306 <30>[ 10.101391] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10888 18:08:48.223880 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10889 18:08:48.242134 <30>[ 10.129452] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10890 18:08:48.248957 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10891 18:08:48.270408 <30>[ 10.157432] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10892 18:08:48.280188 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10893 18:08:48.298723 <30>[ 10.185893] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10894 18:08:48.308411 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10895 18:08:48.357975 <30>[ 10.244975] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10896 18:08:48.364137 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10897 18:08:48.377272 <30>[ 10.264395] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10898 18:08:48.383727 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10899 18:08:48.405487 <30>[ 10.292838] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10900 18:08:48.412402 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10901 18:08:48.436065 <30>[ 10.316990] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10902 18:08:48.490158 <30>[ 10.377185] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10903 18:08:48.499781 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10904 18:08:48.522647 <30>[ 10.409573] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10905 18:08:48.528971 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10906 18:08:48.554789 <30>[ 10.441905] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10907 18:08:48.567733 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel<6>[ 10.455351] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10908 18:08:48.570975 Module dm_mod...
10909 18:08:48.594345 <30>[ 10.481719] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10910 18:08:48.601162 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10911 18:08:48.626423 <30>[ 10.513830] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10912 18:08:48.632885 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10913 18:08:48.655933 <30>[ 10.543316] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10914 18:08:48.662425 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10915 18:08:48.725920 <30>[ 10.613525] systemd[1]: Starting systemd-journald.service - Journal Service...
10916 18:08:48.732959 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10917 18:08:48.755430 <30>[ 10.642949] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10918 18:08:48.762320 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10919 18:08:48.787936 <30>[ 10.671638] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10920 18:08:48.794450 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10921 18:08:48.818501 <30>[ 10.705627] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10922 18:08:48.828331 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10923 18:08:48.850776 <30>[ 10.737742] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10924 18:08:48.857021 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10925 18:08:48.881430 <30>[ 10.768599] systemd[1]: Started systemd-journald.service - Journal Service.
10926 18:08:48.888158 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10927 18:08:48.909751 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10928 18:08:48.926373 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10929 18:08:48.946255 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10930 18:08:48.966503 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10931 18:08:48.987753 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10932 18:08:49.012456 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10933 18:08:49.032198 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10934 18:08:49.056818 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10935 18:08:49.076444 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10936 18:08:49.096623 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10937 18:08:49.119558 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10938 18:08:49.143884 [[0;1;31mFAILED[0m] Failed to start [0;1;39msystemd-re…ount Root and Kernel File Systems.
10939 18:08:49.150620 See 'systemctl status systemd-remount-fs.service' for details.
10940 18:08:49.160278 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10941 18:08:49.180114 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10942 18:08:49.226171 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10943 18:08:49.246737 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10944 18:08:49.265924 <46>[ 11.153220] systemd-journald[189]: Received client request to flush runtime journal.
10945 18:08:49.272587 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10946 18:08:49.297731 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10947 18:08:49.321987 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10948 18:08:49.343960 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10949 18:08:49.362900 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10950 18:08:49.383111 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10951 18:08:49.402729 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10952 18:08:49.422264 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10953 18:08:49.482385 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10954 18:08:49.517069 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10955 18:08:49.534197 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10956 18:08:49.549400 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10957 18:08:49.610668 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10958 18:08:49.635387 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10959 18:08:49.657605 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10960 18:08:49.681807 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10961 18:08:49.704797 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10962 18:08:49.718965 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10963 18:08:49.758735 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10964 18:08:49.791423 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10965 18:08:49.823942 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10966 18:08:49.918417 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10967 18:08:49.942488 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10968 18:08:49.962400 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
10969 18:08:49.982165 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
10970 18:08:50.001650 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
10971 18:08:50.019954 <6>[ 11.907567] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10972 18:08:50.027152 <6>[ 11.915429] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10973 18:08:50.037078 <6>[ 11.923510] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10974 18:08:50.043664 <6>[ 11.925734] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10975 18:08:50.057853 [[0;32m OK [0m] Listening on<3>[ 11.943351] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10976 18:08:50.067616 [0;1;39mdbus.s<6>[ 11.947594] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10977 18:08:50.073955 <3>[ 11.952611] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10978 18:08:50.081176 ocket[…- D-Bu<6>[ 11.952930] mc: Linux media interface: v0.10
10979 18:08:50.087339 s System Message<4>[ 11.953834] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10980 18:08:50.090823 Bus Socket.
10981 18:08:50.097317 <4>[ 11.954179] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10982 18:08:50.104262 <6>[ 11.961323] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10983 18:08:50.113940 <6>[ 11.961933] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10984 18:08:50.120664 <3>[ 11.970003] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10985 18:08:50.127439 <6>[ 11.994959] videodev: Linux video capture interface: v2.00
10986 18:08:50.134173 <4>[ 12.000914] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10987 18:08:50.140750 <6>[ 12.001219] remoteproc remoteproc0: scp is available
10988 18:08:50.147598 <6>[ 12.001403] remoteproc remoteproc0: powering up scp
10989 18:08:50.154217 <6>[ 12.001411] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10990 18:08:50.160677 <6>[ 12.001449] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10991 18:08:50.167165 <3>[ 12.004104] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10992 18:08:50.177448 <3>[ 12.004130] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10993 18:08:50.184521 <3>[ 12.004135] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10994 18:08:50.191539 <3>[ 12.004143] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10995 18:08:50.201294 <3>[ 12.004147] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10996 18:08:50.208018 <3>[ 12.011002] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10997 18:08:50.217669 <6>[ 12.017037] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10998 18:08:50.224428 <3>[ 12.027122] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10999 18:08:50.234118 <6>[ 12.031723] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
11000 18:08:50.240942 <3>[ 12.036705] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11001 18:08:50.247521 <3>[ 12.036718] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11002 18:08:50.257697 <6>[ 12.039093] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
11003 18:08:50.264210 <3>[ 12.042378] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11004 18:08:50.273865 <6>[ 12.046341] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
11005 18:08:50.280477 <6>[ 12.046375] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
11006 18:08:50.287476 <6>[ 12.046379] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
11007 18:08:50.297401 <6>[ 12.046385] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
11008 18:08:50.303791 <6>[ 12.065044] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
11009 18:08:50.313995 <4>[ 12.066779] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
11010 18:08:50.317162 <4>[ 12.066779] Fallback method does not support PEC.
11011 18:08:50.327074 <6>[ 12.068741] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
11012 18:08:50.337040 <3>[ 12.072359] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11013 18:08:50.340386 <6>[ 12.080309] pci_bus 0000:00: root bus resource [bus 00-ff]
11014 18:08:50.347111 <6>[ 12.080315] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
11015 18:08:50.356877 <6>[ 12.080318] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
11016 18:08:50.363368 <6>[ 12.080367] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
11017 18:08:50.373122 <6>[ 12.080385] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
11018 18:08:50.376851 <6>[ 12.080466] pci 0000:00:00.0: supports D1 D2
11019 18:08:50.386665 <6>[ 12.080994] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
11020 18:08:50.396682 <6>[ 12.081347] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
11021 18:08:50.403180 <3>[ 12.083486] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11022 18:08:50.412932 <3>[ 12.088636] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11023 18:08:50.419764 <6>[ 12.096969] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
11024 18:08:50.426352 <3>[ 12.104709] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11025 18:08:50.436058 <3>[ 12.104725] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11026 18:08:50.439326 <6>[ 12.113891] Bluetooth: Core ver 2.22
11027 18:08:50.446267 <6>[ 12.113966] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
11028 18:08:50.452644 <6>[ 12.114153] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
11029 18:08:50.463100 <6>[ 12.114186] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
11030 18:08:50.469439 <6>[ 12.114207] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
11031 18:08:50.475975 <6>[ 12.114222] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
11032 18:08:50.479248 <6>[ 12.114332] pci 0000:01:00.0: supports D1 D2
11033 18:08:50.486589 <6>[ 12.114335] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
11034 18:08:50.497485 <3>[ 12.121191] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11035 18:08:50.505154 <6>[ 12.122936] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
11036 18:08:50.511264 <6>[ 12.123042] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
11037 18:08:50.518120 <6>[ 12.123048] remoteproc remoteproc0: remote processor scp is now up
11038 18:08:50.524472 <6>[ 12.128525] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
11039 18:08:50.531459 <6>[ 12.128551] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
11040 18:08:50.541528 <6>[ 12.128554] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
11041 18:08:50.547774 <6>[ 12.128562] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
11042 18:08:50.557991 <6>[ 12.128575] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
11043 18:08:50.564097 <6>[ 12.128588] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
11044 18:08:50.571181 <6>[ 12.128600] pci 0000:00:00.0: PCI bridge to [bus 01]
11045 18:08:50.578592 <6>[ 12.128605] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
11046 18:08:50.585672 <6>[ 12.128733] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
11047 18:08:50.588663 <6>[ 12.128923] NET: Registered PF_BLUETOOTH protocol family
11048 18:08:50.595145 <6>[ 12.129446] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
11049 18:08:50.602023 <6>[ 12.129769] pcieport 0000:00:00.0: AER: enabled with IRQ 282
11050 18:08:50.611694 <6>[ 12.131133] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
11051 18:08:50.618047 <6>[ 12.137215] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
11052 18:08:50.624880 <6>[ 12.144982] Bluetooth: HCI device and connection manager initialized
11053 18:08:50.631276 <6>[ 12.145014] Bluetooth: HCI socket layer initialized
11054 18:08:50.634745 <6>[ 12.145023] Bluetooth: L2CAP socket layer initialized
11055 18:08:50.641461 <6>[ 12.147687] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
11056 18:08:50.651489 <5>[ 12.148834] cfg80211: Loading compiled-in X.509 certificates for regulatory database
11057 18:08:50.664573 <6>[ 12.149571] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
11058 18:08:50.668039 <6>[ 12.149782] usbcore: registered new interface driver uvcvideo
11059 18:08:50.674514 <6>[ 12.165079] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
11060 18:08:50.681093 <5>[ 12.165088] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
11061 18:08:50.691862 <5>[ 12.165335] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
11062 18:08:50.698645 <4>[ 12.165462] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
11063 18:08:50.705348 <6>[ 12.165467] cfg80211: failed to load regulatory.db
11064 18:08:50.708598 <6>[ 12.168935] Bluetooth: SCO socket layer initialized
11065 18:08:50.718559 <6>[ 12.263817] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
11066 18:08:50.721886 <6>[ 12.335812] usbcore: registered new interface driver btusb
11067 18:08:50.735207 <4>[ 12.336785] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
11068 18:08:50.738572 <3>[ 12.336796] Bluetooth: hci0: Failed to load firmware file (-2)
11069 18:08:50.745416 <3>[ 12.336798] Bluetooth: hci0: Failed to set up firmware (-2)
11070 18:08:50.755367 <4>[ 12.336800] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
11071 18:08:50.761557 <6>[ 12.343569] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
11072 18:08:50.771570 <3>[ 12.395261] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11073 18:08:50.781493 <3>[ 12.396078] power_supply sbs-5-000b: driver failed to report `capacity_error_margin' property: -6
11074 18:08:50.788393 <3>[ 12.396803] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11075 18:08:50.798303 <3>[ 12.399325] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
11076 18:08:50.804645 <6>[ 12.416413] mt7921e 0000:01:00.0: ASIC revision: 79610010
11077 18:08:50.811460 <3>[ 12.470720] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11078 18:08:50.821479 <6>[ 12.563253] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
11079 18:08:50.821561 <6>[ 12.563253]
11080 18:08:50.831063 <3>[ 12.585576] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11081 18:08:50.838123 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
11082 18:08:50.862546 [[0;32m OK [0m] Reached target [0;1;39mbasi<3>[ 12.749400] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11083 18:08:50.865921 c.target[0m - Basic System.
11084 18:08:50.892609 <3>[ 12.779971] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11085 18:08:50.902296 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11086 18:08:50.922239 <3>[ 12.809667] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11087 18:08:50.935094 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11088 18:08:50.958348 Starting [0;1;39msystemd-user-sess…v<6>[ 12.846444] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
11089 18:08:50.961664 ice[0m - Permit User Sessions...
11090 18:08:50.983626 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11091 18:08:51.037152 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice<46>[ 12.908912] systemd-journald[189]: Data hash table of /var/log/journal/c3f909ee3e324895ab90ff2613af9260/system.journal has a fill level at 75.1 (1538 of 2047 items, 524288 file size, 340 bytes per hash table item), suggesting rotation.
11092 18:08:51.050884 [0m - Permit Us<46>[ 12.931498] systemd-journald[189]: /var/log/journal/c3f909ee3e324895ab90ff2613af9260/system.journal: Journal header limits reached or header out-of-date, rotating.
11093 18:08:51.053711 er Sessions.
11094 18:08:51.109692 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11095 18:08:51.130680 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
11096 18:08:51.149849 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
11097 18:08:51.169639 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11098 18:08:51.220433 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11099 18:08:51.241867 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11100 18:08:51.259156 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11101 18:08:51.274299 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11102 18:08:51.293843 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11103 18:08:51.345461 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
11104 18:08:51.369552 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11105 18:08:51.394057 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11106 18:08:51.455171 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11107 18:08:51.474399 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11108 18:08:51.501981 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11109 18:08:51.543250
11110 18:08:51.546746 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11111 18:08:51.546830
11112 18:08:51.549669 debian-bookworm-arm64 login: root (automatic login)
11113 18:08:51.549750
11114 18:08:51.563426 Linux debian-bookworm-arm64 6.1.92-cip22 #1 SMP PREEMPT Tue Jun 11 17:44:14 UTC 2024 aarch64
11115 18:08:51.563508
11116 18:08:51.570198 The programs included with the Debian GNU/Linux system are free software;
11117 18:08:51.576473 the exact distribution terms for each program are described in the
11118 18:08:51.580213 individual files in /usr/share/doc/*/copyright.
11119 18:08:51.580294
11120 18:08:51.586865 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11121 18:08:51.589927 permitted by applicable law.
11122 18:08:51.590316 Matched prompt #10: / #
11124 18:08:51.590518 Setting prompt string to ['/ #']
11125 18:08:51.590610 end: 2.2.5.1 login-action (duration 00:00:14) [common]
11127 18:08:51.590799 end: 2.2.5 auto-login-action (duration 00:00:14) [common]
11128 18:08:51.590883 start: 2.2.6 expect-shell-connection (timeout 00:02:41) [common]
11129 18:08:51.590952 Setting prompt string to ['/ #']
11130 18:08:51.591011 Forcing a shell prompt, looking for ['/ #']
11132 18:08:51.641193 / #
11133 18:08:51.641314 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11134 18:08:51.641402 Waiting using forced prompt support (timeout 00:02:30)
11135 18:08:51.646491
11136 18:08:51.646758 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11137 18:08:51.646848 start: 2.2.7 export-device-env (timeout 00:02:41) [common]
11138 18:08:51.646944 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11139 18:08:51.647035 end: 2.2 depthcharge-retry (duration 00:02:19) [common]
11140 18:08:51.647128 end: 2 depthcharge-action (duration 00:02:19) [common]
11141 18:08:51.647214 start: 3 lava-test-retry (timeout 00:07:16) [common]
11142 18:08:51.647311 start: 3.1 lava-test-shell (timeout 00:07:16) [common]
11143 18:08:51.647389 Using namespace: common
11145 18:08:51.747667 / # #
11146 18:08:51.747833 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11147 18:08:51.753085 #
11148 18:08:51.753343 Using /lava-14291445
11150 18:08:51.853630 / # export SHELL=/bin/sh
11151 18:08:51.853883 export SHELL=/bin/sh<6>[ 13.705713] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11152 18:08:51.858880
11154 18:08:51.959441 / # . /lava-14291445/environment
11155 18:08:51.964983 . /lava-14291445/environment
11157 18:08:52.065579 / # /lava-14291445/bin/lava-test-runner /lava-14291445/0
11158 18:08:52.065754 Test shell timeout: 10s (minimum of the action and connection timeout)
11159 18:08:52.070752 /lava-14291445/bin/lava-test-runner /lava-14291445/0
11160 18:08:52.099021 + export TESTRUN_ID=0_igt-gpu-pa<8>[ 13.988206] <LAVA_SIGNAL_STARTRUN 0_igt-gpu-panfrost 14291445_1.5.2.3.1>
11161 18:08:52.099293 Received signal: <STARTRUN> 0_igt-gpu-panfrost 14291445_1.5.2.3.1
11162 18:08:52.099369 Starting test lava.0_igt-gpu-panfrost (14291445_1.5.2.3.1)
11163 18:08:52.099450 Skipping test definition patterns.
11164 18:08:52.102418 nfrost
11165 18:08:52.105679 + cd /lava-14291445/0/tests/0_igt-gpu-panfrost
11166 18:08:52.105779 + cat uuid
11167 18:08:52.108910 + UUID=14291445_1.5.2.3.1
11168 18:08:52.109043 + set +x
11169 18:08:52.119123 + IGT_FORCE_DRIVER=panfrost /usr/bin/igt-parser.sh panfrost_gem_new panfrost_get_param panfrost_prime panfrost_submit
11170 18:08:52.125465 <8>[ 14.014629] <LAVA_SIGNAL_TESTSET START panfrost_gem_new>
11171 18:08:52.125747 Received signal: <TESTSET> START panfrost_gem_new
11172 18:08:52.125846 Starting test_set panfrost_gem_new
11173 18:08:52.154624 <14>[ 14.045752] [IGT] panfrost_gem_new: executing
11174 18:08:52.164857 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1<14>[ 14.053974] [IGT] panfrost_gem_new: exiting, ret=77
11175 18:08:52.164988 .92-cip22 aarch64)
11176 18:08:52.171397 Using IGT_SRANDOM=1718129331 for randomisation
11177 18:08:52.177659 Test require<8>[ 14.065846] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-new-4096 RESULT=skip>
11178 18:08:52.177951 Received signal: <TESTCASE> TEST_CASE_ID=gem-new-4096 RESULT=skip
11180 18:08:52.184707 ment not met in function drm_open_driver, file ../lib/drmtest.c:694:
11181 18:08:52.187642 Test requirement: !(fd<0)
11182 18:08:52.191381 No known gpu found for chipset flags 0x32 (panfrost)
11183 18:08:52.194476 Last errno: 2, No such file or directory
11184 18:08:52.197988 [1mSubtest gem-new-4096: SKIP (0.000s)[0m
11185 18:08:52.211959 <14>[ 14.102874] [IGT] panfrost_gem_new: executing
11186 18:08:52.222082 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1<14>[ 14.111320] [IGT] panfrost_gem_new: exiting, ret=77
11187 18:08:52.222199 .92-cip22 aarch64)
11188 18:08:52.228452 Using IGT_SRANDOM=1718129332 for randomisation
11189 18:08:52.235315 Test require<8>[ 14.123165] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-new-0 RESULT=skip>
11190 18:08:52.235599 Received signal: <TESTCASE> TEST_CASE_ID=gem-new-0 RESULT=skip
11192 18:08:52.241842 ment not met in function drm_open_driver, file ../lib/drmtest.c:694:
11193 18:08:52.245314 Test requirement: !(fd<0)
11194 18:08:52.248804 No known gpu found for chipset flags 0x32 (panfrost)
11195 18:08:52.255130 Last errn<14>[ 14.144938] [IGT] panfrost_gem_new: executing
11196 18:08:52.255233 o: 2, No such file or directory
11197 18:08:52.262045 <14>[ 14.151931] [IGT] panfrost_gem_new: exiting, ret=77
11198 18:08:52.262161
11199 18:08:52.265024 [1mSubtest gem-new-0: SKIP (0.000s)[0m
11200 18:08:52.275130 IGT-Version: 1.28-ga4<8>[ 14.163251] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-new-zeroed RESULT=skip>
11201 18:08:52.275483 Received signal: <TESTCASE> TEST_CASE_ID=gem-new-zeroed RESULT=skip
11203 18:08:52.281898 4ebfe (aarch64) (Linux: 6.1.92-c<8>[ 14.171873] <LAVA_SIGNAL_TESTSET STOP>
11204 18:08:52.281999 ip22 aarch64)
11205 18:08:52.282240 Received signal: <TESTSET> STOP
11206 18:08:52.282313 Closing test_set panfrost_gem_new
11207 18:08:52.288225 Using IGT_SRANDOM=1718129332 for randomisation
11208 18:08:52.295207 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
11209 18:08:52.295344 Test requirement: !(fd<0)
11210 18:08:52.305058 No known gpu found f<8>[ 14.193859] <LAVA_SIGNAL_TESTSET START panfrost_get_param>
11211 18:08:52.305439 Received signal: <TESTSET> START panfrost_get_param
11212 18:08:52.305561 Starting test_set panfrost_get_param
11213 18:08:52.308427 or chipset flags 0x32 (panfrost)
11214 18:08:52.311479 Last errno: 2, No such file or directory
11215 18:08:52.314828 [1mSubtest gem-new-zeroed: SKIP (0.000s)[0m
11216 18:08:52.322403 <14>[ 14.213284] [IGT] panfrost_get_param: executing
11217 18:08:52.329030 IGT-Version: 1.28-ga44ebfe (aarc<14>[ 14.220363] [IGT] panfrost_get_param: exiting, ret=77
11218 18:08:52.332257 h64) (Linux: 6.1.92-cip22 aarch64)
11219 18:08:52.342409 Using IGT_SRANDOM=1718129332<8>[ 14.231140] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=base-params RESULT=skip>
11220 18:08:52.342756 Received signal: <TESTCASE> TEST_CASE_ID=base-params RESULT=skip
11222 18:08:52.345782 for randomisation
11223 18:08:52.351946 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
11224 18:08:52.355533 Test requirement: !(fd<0)
11225 18:08:52.362056 No known gpu found for chipset <14>[ 14.252307] [IGT] panfrost_get_param: executing
11226 18:08:52.362171 flags 0x32 (panfrost)
11227 18:08:52.368617 Last errn<14>[ 14.260000] [IGT] panfrost_get_param: exiting, ret=77
11228 18:08:52.372245 o: 2, No such file or directory
11229 18:08:52.381753 [1mSubtest base-params: SKIP (<8>[ 14.270809] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=get-bad-param RESULT=skip>
11230 18:08:52.382157 Received signal: <TESTCASE> TEST_CASE_ID=get-bad-param RESULT=skip
11232 18:08:52.385581 0.000s)[0m
11233 18:08:52.388489 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11234 18:08:52.395454 Using IGT_SRANDOM=1718129332 for randomisation
11235 18:08:52.401961 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
11236 18:08:52.402073 Test requirement: !(fd<0)
11237 18:08:52.412098 No known gpu found for chipset flags 0x32 (panfros<14>[ 14.303066] [IGT] panfrost_get_param: executing
11238 18:08:52.412253 t)
11239 18:08:52.414940 Last errno: 2, No such file or directory
11240 18:08:52.421770 [<14>[ 14.312150] [IGT] panfrost_get_param: exiting, ret=77
11241 18:08:52.425419 1mSubtest get-bad-param: SKIP (0.000s)[0m
11242 18:08:52.438269 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-<8>[ 14.325464] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=get-bad-padding RESULT=skip>
11243 18:08:52.438398 cip22 aarch64)
11244 18:08:52.438644 Received signal: <TESTCASE> TEST_CASE_ID=get-bad-padding RESULT=skip
11246 18:08:52.445009 Using IGT_SRANDO<8>[ 14.335217] <LAVA_SIGNAL_TESTSET STOP>
11247 18:08:52.445273 Received signal: <TESTSET> STOP
11248 18:08:52.445342 Closing test_set panfrost_get_param
11249 18:08:52.448512 M=1718129332 for randomisation
11250 18:08:52.455098 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
11251 18:08:52.458533 Test requirement: !(fd<0)
11252 18:08:52.465274 Received signal: <TESTSET> START panfrost_prime
11253 18:08:52.465358 Starting test_set panfrost_prime
11254 18:08:52.467959 No known gpu found for chipset flags 0x32 (panfrost<8>[ 14.357215] <LAVA_SIGNAL_TESTSET START panfrost_prime>
11255 18:08:52.468042 )
11256 18:08:52.471247 Last errno: 2, No such file or directory
11257 18:08:52.475085 [1mSubtest get-bad-padding: SKIP (0.000s)[0m
11258 18:08:52.485186 <14>[ 14.376061] [IGT] panfrost_prime: executing
11259 18:08:52.491778 IGT-Version: 1.28-ga44ebfe (aarc<14>[ 14.383005] [IGT] panfrost_prime: exiting, ret=77
11260 18:08:52.495213 h64) (Linux: 6.1.92-cip22 aarch64)
11261 18:08:52.507994 Using IGT_SRANDOM=1718129332 for randomisati<8>[ 14.394361] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-prime-import RESULT=skip>
11262 18:08:52.508076 on
11263 18:08:52.508312 Received signal: <TESTCASE> TEST_CASE_ID=gem-prime-import RESULT=skip
11265 18:08:52.514702 Test requirement not met in <8>[ 14.404319] <LAVA_SIGNAL_TESTSET STOP>
11266 18:08:52.514952 Received signal: <TESTSET> STOP
11267 18:08:52.515019 Closing test_set panfrost_prime
11268 18:08:52.518381 function drm_open_driver, file ../lib/drmtest.c:694:
11269 18:08:52.521367 Test requirement: !(fd<0)
11270 18:08:52.524905 No known gpu found for chipset flags 0x32 (panfrost)
11271 18:08:52.528144 Last errno: 2, No such file or directory
11272 18:08:52.534703 [1mSubtest gem<8>[ 14.425662] <LAVA_SIGNAL_TESTSET START panfrost_submit>
11273 18:08:52.534956 Received signal: <TESTSET> START panfrost_submit
11274 18:08:52.535024 Starting test_set panfrost_submit
11275 18:08:52.537972 -prime-import: SKIP (0.000s)[0m
11276 18:08:52.554086 <14>[ 14.445259] [IGT] panfrost_submit: executing
11277 18:08:52.561150 IGT-Version: 1.28-ga44ebfe (aarc<14>[ 14.452270] [IGT] panfrost_submit: exiting, ret=77
11278 18:08:52.564211 h64) (Linux: 6.1.92-cip22 aarch64)
11279 18:08:52.574441 Using IGT_SRANDOM=1718129332 for randomisati<8>[ 14.463867] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit RESULT=skip>
11280 18:08:52.574701 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit RESULT=skip
11282 18:08:52.577503 on
11283 18:08:52.584160 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
11284 18:08:52.584244 Test requirement: !(fd<0)
11285 18:08:52.591123 No known gpu found for chipset flags 0x32 (panfrost)
11286 18:08:52.593800 Last errn<14>[ 14.486033] [IGT] panfrost_submit: executing
11287 18:08:52.597162 o: 2, No such file or directory
11288 18:08:52.604087 <14>[ 14.493860] [IGT] panfrost_submit: exiting, ret=77
11289 18:08:52.604170
11290 18:08:52.607581 [1mSubtest pan-submit: SKIP (0.000s)[0m
11291 18:08:52.617428 IGT-Version: 1.28-ga44ebfe (aarch64)<8>[ 14.505462] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-no-jc RESULT=skip>
11292 18:08:52.617685 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-no-jc RESULT=skip
11294 18:08:52.620801 (Linux: 6.1.92-cip22 aarch64)
11295 18:08:52.623598 Using IGT_SRANDOM=1718129332 for randomisation
11296 18:08:52.637189 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:<14>[ 14.527880] [IGT] panfrost_submit: executing
11297 18:08:52.637278
11298 18:08:52.640720 Test requirement: !(fd<0)
11299 18:08:52.644045 No <14>[ 14.535406] [IGT] panfrost_submit: exiting, ret=77
11300 18:08:52.650915 known gpu found for chipset flags 0x32 (panfrost)
11301 18:08:52.660537 Last errno: 2, No such file o<8>[ 14.547560] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-in-syncs RESULT=skip>
11302 18:08:52.661005 r directory
11303 18:08:52.661780 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-in-syncs RESULT=skip
11305 18:08:52.667396 [1mSubtest pan-submit-error-no-jc: SKIP (0.000s)[0m
11306 18:08:52.674133 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11307 18:08:52.680578 Using IGT_SRANDOM=171812<14>[ 14.570195] [IGT] panfrost_submit: executing
11308 18:08:52.681034 9332 for randomisation
11309 18:08:52.687467 Test req<14>[ 14.577456] [IGT] panfrost_submit: exiting, ret=77
11310 18:08:52.700799 uirement not met in function drm_open_driver, file ../lib/drmtes<8>[ 14.587500] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-bo-handles RESULT=skip>
11311 18:08:52.701643 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-bo-handles RESULT=skip
11313 18:08:52.704004 t.c:694:
11314 18:08:52.704477 Test requirement: !(fd<0)
11315 18:08:52.710394 No known gpu found for chipset flags 0x32 (panfrost)
11316 18:08:52.713843 Last errno: 2, No such file or directory
11317 18:08:52.717307 [1mSubtest pan-submit-error-bad-in-syncs: SKIP (0.000s)[0m
11318 18:08:52.723779 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11319 18:08:52.730656 Using IGT_SRANDOM=1718129<14>[ 14.621487] [IGT] panfrost_submit: executing
11320 18:08:52.733819 332 for randomisation
11321 18:08:52.740584 Test requirement not met <14>[ 14.630447] [IGT] panfrost_submit: exiting, ret=77
11322 18:08:52.747060 in function drm_open_driver, file ../lib/drmtest.c:694:
11323 18:08:52.747485 Test requirement: !(fd<0)
11324 18:08:52.756973 No known gpu<8>[ 14.643391] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-requirements RESULT=skip>
11325 18:08:52.757698 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-requirements RESULT=skip
11327 18:08:52.760269 found for chipset flags 0x32 (panfrost)
11328 18:08:52.763531 Last errno: 2, No such file or directory
11329 18:08:52.770581 [1mSubtest pan-submit-error-bad-bo-handles: SKIP (0.000s)[0m
11330 18:08:52.776636 IGT-Version: 1.28-ga44ebfe (<14>[ 14.667598] [IGT] panfrost_submit: executing
11331 18:08:52.787000 aarch64) (Linux: 6.1.92-cip22 aa<14>[ 14.675684] [IGT] panfrost_submit: exiting, ret=77
11332 18:08:52.787424 rch64)
11333 18:08:52.790564 Using IGT_SRANDOM=1718129332 for randomisation
11334 18:08:52.800671 Test req<8>[ 14.686793] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-out-sync RESULT=skip>
11335 18:08:52.801513 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-out-sync RESULT=skip
11337 18:08:52.807075 uirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
11338 18:08:52.810037 Test requirement: !(fd<0)
11339 18:08:52.813516 No known gpu found for chipset flags 0x32 (panfrost)
11340 18:08:52.820246 Last errno: 2, No suc<14>[ 14.709552] [IGT] panfrost_submit: executing
11341 18:08:52.820668 h file or directory
11342 18:08:52.826738 [1mSubtest<14>[ 14.717710] [IGT] panfrost_submit: exiting, ret=77
11343 18:08:52.833584 pan-submit-error-bad-requirements: SKIP (0.000s)[0m
11344 18:08:52.839670 IGT-Versi<8>[ 14.728809] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-reset RESULT=skip>
11345 18:08:52.840517 Received signal: <TESTCASE> TEST_CASE_ID=pan-reset RESULT=skip
11347 18:08:52.846871 on: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11348 18:08:52.849801 Using IGT_SRANDOM=1718129332 for randomisation
11349 18:08:52.856665 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
11350 18:08:52.860042 Tes<14>[ 14.751693] [IGT] panfrost_submit: executing
11351 18:08:52.862894 t requirement: !(fd<0)
11352 18:08:52.869610 No known<14>[ 14.759120] [IGT] panfrost_submit: exiting, ret=77
11353 18:08:52.872831 gpu found for chipset flags 0x32 (panfrost)
11354 18:08:52.883182 Last errno: 2, No <8>[ 14.770509] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-and-close RESULT=skip>
11355 18:08:52.883858 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-and-close RESULT=skip
11357 18:08:52.886485 such file or directory
11358 18:08:52.889634 [1mSubtest pan-submit-error-bad-out-sync: SKIP (0.000s)[0m
11359 18:08:52.896421 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11360 18:08:52.899422 Using <14>[ 14.791822] [IGT] panfrost_submit: executing
11361 18:08:52.909546 IGT_SRANDOM=1718129332 for rando<14>[ 14.798905] [IGT] panfrost_submit: exiting, ret=77
11362 18:08:52.910080 misation
11363 18:08:52.922540 Test requirement not met in function drm_open_driver, file ../lib/drmt<8>[ 14.810518] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-unhandled-pagefault RESULT=skip>
11364 18:08:52.923302 Received signal: <TESTCASE> TEST_CASE_ID=pan-unhandled-pagefault RESULT=skip
11366 18:08:52.926081 est.c:694:
11367 18:08:52.929574 Test requirement: !(<8>[ 14.821472] <LAVA_SIGNAL_TESTSET STOP>
11368 18:08:52.930292 Received signal: <TESTSET> STOP
11369 18:08:52.930642 Closing test_set panfrost_submit
11370 18:08:52.932517 fd<0)
11371 18:08:52.939777 No known <8>[ 14.827335] <LAVA_SIGNAL_ENDRUN 0_igt-gpu-panfrost 14291445_1.5.2.3.1>
11372 18:08:52.940552 Received signal: <ENDRUN> 0_igt-gpu-panfrost 14291445_1.5.2.3.1
11373 18:08:52.940957 Ending use of test pattern.
11374 18:08:52.941338 Ending test lava.0_igt-gpu-panfrost (14291445_1.5.2.3.1), duration 0.84
11376 18:08:52.942885 gpu found for chipset flags 0x32 (panfrost)
11377 18:08:52.946361 Last errno: 2, No such file or directory
11378 18:08:52.949629 [1mSubtest pan-reset: SKIP (0.000s)[0m
11379 18:08:52.956039 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11380 18:08:52.959485 Using IGT_SRANDOM=1718129332 for randomisation
11381 18:08:52.965696 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
11382 18:08:52.969255 Test requirement: !(fd<0)
11383 18:08:52.975528 No known gpu found for chipset flags 0x32 (panfrost)
11384 18:08:52.979220 Last errno: 2, No such file or directory
11385 18:08:52.982708 [1mSubtest pan-submit-and-close: SKIP (0.000s)[0m
11386 18:08:52.988969 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11387 18:08:52.992427 Using IGT_SRANDOM=1718129332 for randomisation
11388 18:08:52.999011 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
11389 18:08:53.002485 Test requirement: !(fd<0)
11390 18:08:53.005797 No known gpu found for chipset flags 0x32 (panfrost)
11391 18:08:53.009347 Last errno: 2, No such file or directory
11392 18:08:53.015608 [1mSubtest pan-unhandled-pagefault: SKIP (0.000s)[0m
11393 18:08:53.016172 + set +x
11394 18:08:53.019025 <LAVA_TEST_RUNNER EXIT>
11395 18:08:53.019901 ok: lava_test_shell seems to have completed
11396 18:08:53.021932 base-params:
result: skip
set: panfrost_get_param
gem-new-0:
result: skip
set: panfrost_gem_new
gem-new-4096:
result: skip
set: panfrost_gem_new
gem-new-zeroed:
result: skip
set: panfrost_gem_new
gem-prime-import:
result: skip
set: panfrost_prime
get-bad-padding:
result: skip
set: panfrost_get_param
get-bad-param:
result: skip
set: panfrost_get_param
pan-reset:
result: skip
set: panfrost_submit
pan-submit:
result: skip
set: panfrost_submit
pan-submit-and-close:
result: skip
set: panfrost_submit
pan-submit-error-bad-bo-handles:
result: skip
set: panfrost_submit
pan-submit-error-bad-in-syncs:
result: skip
set: panfrost_submit
pan-submit-error-bad-out-sync:
result: skip
set: panfrost_submit
pan-submit-error-bad-requirements:
result: skip
set: panfrost_submit
pan-submit-error-no-jc:
result: skip
set: panfrost_submit
pan-unhandled-pagefault:
result: skip
set: panfrost_submit
11397 18:08:53.022564 end: 3.1 lava-test-shell (duration 00:00:01) [common]
11398 18:08:53.023006 end: 3 lava-test-retry (duration 00:00:01) [common]
11399 18:08:53.023460 start: 4 finalize (timeout 00:07:15) [common]
11400 18:08:53.023915 start: 4.1 power-off (timeout 00:00:30) [common]
11401 18:08:53.024875 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-3', '--port=1', '--command=off']
11402 18:08:53.140185 >> Command sent successfully.
11403 18:08:53.143997 Returned 0 in 0 seconds
11404 18:08:53.244912 end: 4.1 power-off (duration 00:00:00) [common]
11406 18:08:53.247059 start: 4.2 read-feedback (timeout 00:07:15) [common]
11407 18:08:53.248286 Listened to connection for namespace 'common' for up to 1s
11408 18:08:54.249082 Finalising connection for namespace 'common'
11409 18:08:54.249698 Disconnecting from shell: Finalise
11410 18:08:54.250254 / #
11411 18:08:54.351086 end: 4.2 read-feedback (duration 00:00:01) [common]
11412 18:08:54.351336 end: 4 finalize (duration 00:00:01) [common]
11413 18:08:54.351536 Cleaning after the job
11414 18:08:54.351719 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14291445/tftp-deploy-dii3sy_s/ramdisk
11415 18:08:54.362648 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14291445/tftp-deploy-dii3sy_s/kernel
11416 18:08:54.386219 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14291445/tftp-deploy-dii3sy_s/dtb
11417 18:08:54.386493 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14291445/tftp-deploy-dii3sy_s/modules
11418 18:08:54.393082 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14291445
11419 18:08:54.505748 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14291445
11420 18:08:54.505909 Job finished correctly