Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 21
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 24
1 18:01:42.641115 lava-dispatcher, installed at version: 2024.03
2 18:01:42.641352 start: 0 validate
3 18:01:42.641504 Start time: 2024-06-11 18:01:42.641496+00:00 (UTC)
4 18:01:42.641638 Using caching service: 'http://localhost/cache/?uri=%s'
5 18:01:42.641803 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 18:01:42.908770 Using caching service: 'http://localhost/cache/?uri=%s'
7 18:01:42.908948 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22-17-g24b63cdc814f%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 18:01:43.174179 Using caching service: 'http://localhost/cache/?uri=%s'
9 18:01:43.174342 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22-17-g24b63cdc814f%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 18:01:43.440404 Using caching service: 'http://localhost/cache/?uri=%s'
11 18:01:43.440740 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 18:01:43.967828 Using caching service: 'http://localhost/cache/?uri=%s'
13 18:01:43.968024 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22-17-g24b63cdc814f%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 18:01:43.971456 validate duration: 1.33
16 18:01:43.971794 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 18:01:43.971930 start: 1.1 download-retry (timeout 00:10:00) [common]
18 18:01:43.972051 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 18:01:43.972213 Not decompressing ramdisk as can be used compressed.
20 18:01:43.972334 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 18:01:43.972431 saving as /var/lib/lava/dispatcher/tmp/14291372/tftp-deploy-hgwt2mnh/ramdisk/initrd.cpio.gz
22 18:01:43.972530 total size: 5628169 (5 MB)
23 18:01:43.974083 progress 0 % (0 MB)
24 18:01:43.975717 progress 5 % (0 MB)
25 18:01:43.977301 progress 10 % (0 MB)
26 18:01:43.978713 progress 15 % (0 MB)
27 18:01:43.980293 progress 20 % (1 MB)
28 18:01:43.981715 progress 25 % (1 MB)
29 18:01:43.983297 progress 30 % (1 MB)
30 18:01:43.984859 progress 35 % (1 MB)
31 18:01:43.986248 progress 40 % (2 MB)
32 18:01:43.987790 progress 45 % (2 MB)
33 18:01:43.989223 progress 50 % (2 MB)
34 18:01:43.990779 progress 55 % (2 MB)
35 18:01:43.992375 progress 60 % (3 MB)
36 18:01:43.993808 progress 65 % (3 MB)
37 18:01:43.995363 progress 70 % (3 MB)
38 18:01:43.996785 progress 75 % (4 MB)
39 18:01:43.998327 progress 80 % (4 MB)
40 18:01:43.999706 progress 85 % (4 MB)
41 18:01:44.001263 progress 90 % (4 MB)
42 18:01:44.002808 progress 95 % (5 MB)
43 18:01:44.004219 progress 100 % (5 MB)
44 18:01:44.004452 5 MB downloaded in 0.03 s (168.15 MB/s)
45 18:01:44.004644 end: 1.1.1 http-download (duration 00:00:00) [common]
47 18:01:44.004895 end: 1.1 download-retry (duration 00:00:00) [common]
48 18:01:44.004990 start: 1.2 download-retry (timeout 00:10:00) [common]
49 18:01:44.005078 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 18:01:44.005217 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-17-g24b63cdc814f/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 18:01:44.005293 saving as /var/lib/lava/dispatcher/tmp/14291372/tftp-deploy-hgwt2mnh/kernel/Image
52 18:01:44.005357 total size: 54813184 (52 MB)
53 18:01:44.005421 No compression specified
54 18:01:44.006531 progress 0 % (0 MB)
55 18:01:44.020692 progress 5 % (2 MB)
56 18:01:44.034927 progress 10 % (5 MB)
57 18:01:44.048860 progress 15 % (7 MB)
58 18:01:44.062999 progress 20 % (10 MB)
59 18:01:44.078317 progress 25 % (13 MB)
60 18:01:44.094067 progress 30 % (15 MB)
61 18:01:44.109994 progress 35 % (18 MB)
62 18:01:44.125610 progress 40 % (20 MB)
63 18:01:44.139679 progress 45 % (23 MB)
64 18:01:44.155376 progress 50 % (26 MB)
65 18:01:44.171706 progress 55 % (28 MB)
66 18:01:44.186540 progress 60 % (31 MB)
67 18:01:44.200645 progress 65 % (34 MB)
68 18:01:44.214638 progress 70 % (36 MB)
69 18:01:44.228701 progress 75 % (39 MB)
70 18:01:44.243872 progress 80 % (41 MB)
71 18:01:44.258825 progress 85 % (44 MB)
72 18:01:44.274004 progress 90 % (47 MB)
73 18:01:44.287968 progress 95 % (49 MB)
74 18:01:44.301613 progress 100 % (52 MB)
75 18:01:44.301873 52 MB downloaded in 0.30 s (176.30 MB/s)
76 18:01:44.302040 end: 1.2.1 http-download (duration 00:00:00) [common]
78 18:01:44.302276 end: 1.2 download-retry (duration 00:00:00) [common]
79 18:01:44.302367 start: 1.3 download-retry (timeout 00:10:00) [common]
80 18:01:44.302457 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 18:01:44.302603 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-17-g24b63cdc814f/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 18:01:44.302677 saving as /var/lib/lava/dispatcher/tmp/14291372/tftp-deploy-hgwt2mnh/dtb/mt8192-asurada-spherion-r0.dtb
83 18:01:44.302741 total size: 47258 (0 MB)
84 18:01:44.302807 No compression specified
85 18:01:44.303925 progress 69 % (0 MB)
86 18:01:44.304206 progress 100 % (0 MB)
87 18:01:44.304365 0 MB downloaded in 0.00 s (27.79 MB/s)
88 18:01:44.304496 end: 1.3.1 http-download (duration 00:00:00) [common]
90 18:01:44.304744 end: 1.3 download-retry (duration 00:00:00) [common]
91 18:01:44.304834 start: 1.4 download-retry (timeout 00:10:00) [common]
92 18:01:44.304920 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 18:01:44.305036 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 18:01:44.305107 saving as /var/lib/lava/dispatcher/tmp/14291372/tftp-deploy-hgwt2mnh/nfsrootfs/full.rootfs.tar
95 18:01:44.305170 total size: 120894716 (115 MB)
96 18:01:44.305233 Using unxz to decompress xz
97 18:01:44.308740 progress 0 % (0 MB)
98 18:01:44.696373 progress 5 % (5 MB)
99 18:01:45.071368 progress 10 % (11 MB)
100 18:01:45.433205 progress 15 % (17 MB)
101 18:01:45.803900 progress 20 % (23 MB)
102 18:01:46.102455 progress 25 % (28 MB)
103 18:01:46.467292 progress 30 % (34 MB)
104 18:01:46.807986 progress 35 % (40 MB)
105 18:01:46.975998 progress 40 % (46 MB)
106 18:01:47.165102 progress 45 % (51 MB)
107 18:01:47.486405 progress 50 % (57 MB)
108 18:01:47.861534 progress 55 % (63 MB)
109 18:01:48.206521 progress 60 % (69 MB)
110 18:01:48.555420 progress 65 % (74 MB)
111 18:01:48.903400 progress 70 % (80 MB)
112 18:01:49.264308 progress 75 % (86 MB)
113 18:01:49.611523 progress 80 % (92 MB)
114 18:01:49.960379 progress 85 % (98 MB)
115 18:01:50.320168 progress 90 % (103 MB)
116 18:01:50.656785 progress 95 % (109 MB)
117 18:01:51.021131 progress 100 % (115 MB)
118 18:01:51.026659 115 MB downloaded in 6.72 s (17.15 MB/s)
119 18:01:51.026998 end: 1.4.1 http-download (duration 00:00:07) [common]
121 18:01:51.027411 end: 1.4 download-retry (duration 00:00:07) [common]
122 18:01:51.027553 start: 1.5 download-retry (timeout 00:09:53) [common]
123 18:01:51.027688 start: 1.5.1 http-download (timeout 00:09:53) [common]
124 18:01:51.027902 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-17-g24b63cdc814f/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 18:01:51.028014 saving as /var/lib/lava/dispatcher/tmp/14291372/tftp-deploy-hgwt2mnh/modules/modules.tar
126 18:01:51.028112 total size: 8618176 (8 MB)
127 18:01:51.028215 Using unxz to decompress xz
128 18:01:51.296030 progress 0 % (0 MB)
129 18:01:51.315569 progress 5 % (0 MB)
130 18:01:51.343719 progress 10 % (0 MB)
131 18:01:51.374304 progress 15 % (1 MB)
132 18:01:51.399932 progress 20 % (1 MB)
133 18:01:51.423764 progress 25 % (2 MB)
134 18:01:51.448204 progress 30 % (2 MB)
135 18:01:51.476248 progress 35 % (2 MB)
136 18:01:51.502575 progress 40 % (3 MB)
137 18:01:51.529030 progress 45 % (3 MB)
138 18:01:51.553596 progress 50 % (4 MB)
139 18:01:51.579241 progress 55 % (4 MB)
140 18:01:51.604176 progress 60 % (4 MB)
141 18:01:51.628681 progress 65 % (5 MB)
142 18:01:51.657677 progress 70 % (5 MB)
143 18:01:51.683618 progress 75 % (6 MB)
144 18:01:51.712322 progress 80 % (6 MB)
145 18:01:51.739581 progress 85 % (7 MB)
146 18:01:51.766943 progress 90 % (7 MB)
147 18:01:51.794675 progress 95 % (7 MB)
148 18:01:51.823657 progress 100 % (8 MB)
149 18:01:51.828261 8 MB downloaded in 0.80 s (10.27 MB/s)
150 18:01:51.828501 end: 1.5.1 http-download (duration 00:00:01) [common]
152 18:01:51.828805 end: 1.5 download-retry (duration 00:00:01) [common]
153 18:01:51.828900 start: 1.6 prepare-tftp-overlay (timeout 00:09:52) [common]
154 18:01:51.828993 start: 1.6.1 extract-nfsrootfs (timeout 00:09:52) [common]
155 18:01:55.631084 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/14291372/extract-nfsrootfs-6eprz0iq
156 18:01:55.631314 end: 1.6.1 extract-nfsrootfs (duration 00:00:04) [common]
157 18:01:55.631425 start: 1.6.2 lava-overlay (timeout 00:09:48) [common]
158 18:01:55.631597 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14291372/lava-overlay-8g2683u8
159 18:01:55.631727 makedir: /var/lib/lava/dispatcher/tmp/14291372/lava-overlay-8g2683u8/lava-14291372/bin
160 18:01:55.631827 makedir: /var/lib/lava/dispatcher/tmp/14291372/lava-overlay-8g2683u8/lava-14291372/tests
161 18:01:55.631928 makedir: /var/lib/lava/dispatcher/tmp/14291372/lava-overlay-8g2683u8/lava-14291372/results
162 18:01:55.632027 Creating /var/lib/lava/dispatcher/tmp/14291372/lava-overlay-8g2683u8/lava-14291372/bin/lava-add-keys
163 18:01:55.632169 Creating /var/lib/lava/dispatcher/tmp/14291372/lava-overlay-8g2683u8/lava-14291372/bin/lava-add-sources
164 18:01:55.632300 Creating /var/lib/lava/dispatcher/tmp/14291372/lava-overlay-8g2683u8/lava-14291372/bin/lava-background-process-start
165 18:01:55.632424 Creating /var/lib/lava/dispatcher/tmp/14291372/lava-overlay-8g2683u8/lava-14291372/bin/lava-background-process-stop
166 18:01:55.632554 Creating /var/lib/lava/dispatcher/tmp/14291372/lava-overlay-8g2683u8/lava-14291372/bin/lava-common-functions
167 18:01:55.632713 Creating /var/lib/lava/dispatcher/tmp/14291372/lava-overlay-8g2683u8/lava-14291372/bin/lava-echo-ipv4
168 18:01:55.632833 Creating /var/lib/lava/dispatcher/tmp/14291372/lava-overlay-8g2683u8/lava-14291372/bin/lava-install-packages
169 18:01:55.632952 Creating /var/lib/lava/dispatcher/tmp/14291372/lava-overlay-8g2683u8/lava-14291372/bin/lava-installed-packages
170 18:01:55.633071 Creating /var/lib/lava/dispatcher/tmp/14291372/lava-overlay-8g2683u8/lava-14291372/bin/lava-os-build
171 18:01:55.633189 Creating /var/lib/lava/dispatcher/tmp/14291372/lava-overlay-8g2683u8/lava-14291372/bin/lava-probe-channel
172 18:01:55.633322 Creating /var/lib/lava/dispatcher/tmp/14291372/lava-overlay-8g2683u8/lava-14291372/bin/lava-probe-ip
173 18:01:55.633451 Creating /var/lib/lava/dispatcher/tmp/14291372/lava-overlay-8g2683u8/lava-14291372/bin/lava-target-ip
174 18:01:55.633571 Creating /var/lib/lava/dispatcher/tmp/14291372/lava-overlay-8g2683u8/lava-14291372/bin/lava-target-mac
175 18:01:55.633690 Creating /var/lib/lava/dispatcher/tmp/14291372/lava-overlay-8g2683u8/lava-14291372/bin/lava-target-storage
176 18:01:55.633810 Creating /var/lib/lava/dispatcher/tmp/14291372/lava-overlay-8g2683u8/lava-14291372/bin/lava-test-case
177 18:01:55.633928 Creating /var/lib/lava/dispatcher/tmp/14291372/lava-overlay-8g2683u8/lava-14291372/bin/lava-test-event
178 18:01:55.634044 Creating /var/lib/lava/dispatcher/tmp/14291372/lava-overlay-8g2683u8/lava-14291372/bin/lava-test-feedback
179 18:01:55.634164 Creating /var/lib/lava/dispatcher/tmp/14291372/lava-overlay-8g2683u8/lava-14291372/bin/lava-test-raise
180 18:01:55.634286 Creating /var/lib/lava/dispatcher/tmp/14291372/lava-overlay-8g2683u8/lava-14291372/bin/lava-test-reference
181 18:01:55.634408 Creating /var/lib/lava/dispatcher/tmp/14291372/lava-overlay-8g2683u8/lava-14291372/bin/lava-test-runner
182 18:01:55.634527 Creating /var/lib/lava/dispatcher/tmp/14291372/lava-overlay-8g2683u8/lava-14291372/bin/lava-test-set
183 18:01:55.634647 Creating /var/lib/lava/dispatcher/tmp/14291372/lava-overlay-8g2683u8/lava-14291372/bin/lava-test-shell
184 18:01:55.634767 Updating /var/lib/lava/dispatcher/tmp/14291372/lava-overlay-8g2683u8/lava-14291372/bin/lava-add-keys (debian)
185 18:01:55.634913 Updating /var/lib/lava/dispatcher/tmp/14291372/lava-overlay-8g2683u8/lava-14291372/bin/lava-add-sources (debian)
186 18:01:55.635056 Updating /var/lib/lava/dispatcher/tmp/14291372/lava-overlay-8g2683u8/lava-14291372/bin/lava-install-packages (debian)
187 18:01:55.635189 Updating /var/lib/lava/dispatcher/tmp/14291372/lava-overlay-8g2683u8/lava-14291372/bin/lava-installed-packages (debian)
188 18:01:55.635327 Updating /var/lib/lava/dispatcher/tmp/14291372/lava-overlay-8g2683u8/lava-14291372/bin/lava-os-build (debian)
189 18:01:55.635448 Creating /var/lib/lava/dispatcher/tmp/14291372/lava-overlay-8g2683u8/lava-14291372/environment
190 18:01:55.635544 LAVA metadata
191 18:01:55.635609 - LAVA_JOB_ID=14291372
192 18:01:55.635670 - LAVA_DISPATCHER_IP=192.168.201.1
193 18:01:55.635768 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:48) [common]
194 18:01:55.635834 skipped lava-vland-overlay
195 18:01:55.635941 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 18:01:55.636022 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:48) [common]
197 18:01:55.636082 skipped lava-multinode-overlay
198 18:01:55.636153 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 18:01:55.636231 start: 1.6.2.3 test-definition (timeout 00:09:48) [common]
200 18:01:55.636302 Loading test definitions
201 18:01:55.636390 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:48) [common]
202 18:01:55.636459 Using /lava-14291372 at stage 0
203 18:01:55.636768 uuid=14291372_1.6.2.3.1 testdef=None
204 18:01:55.636855 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 18:01:55.636939 start: 1.6.2.3.2 test-overlay (timeout 00:09:48) [common]
206 18:01:55.637373 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 18:01:55.637589 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:48) [common]
209 18:01:55.638131 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 18:01:55.638356 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:48) [common]
212 18:01:55.638875 runner path: /var/lib/lava/dispatcher/tmp/14291372/lava-overlay-8g2683u8/lava-14291372/0/tests/0_timesync-off test_uuid 14291372_1.6.2.3.1
213 18:01:55.639027 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 18:01:55.639248 start: 1.6.2.3.5 git-repo-action (timeout 00:09:48) [common]
216 18:01:55.639319 Using /lava-14291372 at stage 0
217 18:01:55.639413 Fetching tests from https://github.com/kernelci/test-definitions.git
218 18:01:55.639498 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/14291372/lava-overlay-8g2683u8/lava-14291372/0/tests/1_kselftest-alsa'
219 18:01:57.702466 Running '/usr/bin/git checkout kernelci.org
220 18:01:57.862356 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/14291372/lava-overlay-8g2683u8/lava-14291372/0/tests/1_kselftest-alsa/automated/linux/kselftest/kselftest.yaml
221 18:01:57.863408 uuid=14291372_1.6.2.3.5 testdef=None
222 18:01:57.863602 end: 1.6.2.3.5 git-repo-action (duration 00:00:02) [common]
224 18:01:57.863897 start: 1.6.2.3.6 test-overlay (timeout 00:09:46) [common]
225 18:01:57.864957 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 18:01:57.865203 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:46) [common]
228 18:01:57.866250 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 18:01:57.866514 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:46) [common]
231 18:01:57.867811 runner path: /var/lib/lava/dispatcher/tmp/14291372/lava-overlay-8g2683u8/lava-14291372/0/tests/1_kselftest-alsa test_uuid 14291372_1.6.2.3.5
232 18:01:57.867946 BOARD='mt8192-asurada-spherion-r0'
233 18:01:57.868042 BRANCH='cip'
234 18:01:57.868139 SKIPFILE='/dev/null'
235 18:01:57.868232 SKIP_INSTALL='True'
236 18:01:57.868320 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-17-g24b63cdc814f/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 18:01:57.868419 TST_CASENAME=''
238 18:01:57.868515 TST_CMDFILES='alsa'
239 18:01:57.868735 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 18:01:57.868957 Creating lava-test-runner.conf files
242 18:01:57.869025 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14291372/lava-overlay-8g2683u8/lava-14291372/0 for stage 0
243 18:01:57.869122 - 0_timesync-off
244 18:01:57.869192 - 1_kselftest-alsa
245 18:01:57.869291 end: 1.6.2.3 test-definition (duration 00:00:02) [common]
246 18:01:57.869391 start: 1.6.2.4 compress-overlay (timeout 00:09:46) [common]
247 18:02:05.713208 end: 1.6.2.4 compress-overlay (duration 00:00:08) [common]
248 18:02:05.713403 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:38) [common]
249 18:02:05.713557 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 18:02:05.713746 end: 1.6.2 lava-overlay (duration 00:00:10) [common]
251 18:02:05.713899 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:38) [common]
252 18:02:05.877871 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 18:02:05.878254 start: 1.6.4 extract-modules (timeout 00:09:38) [common]
254 18:02:05.878369 extracting modules file /var/lib/lava/dispatcher/tmp/14291372/tftp-deploy-hgwt2mnh/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14291372/extract-nfsrootfs-6eprz0iq
255 18:02:06.088390 extracting modules file /var/lib/lava/dispatcher/tmp/14291372/tftp-deploy-hgwt2mnh/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14291372/extract-overlay-ramdisk-mtlvyg9q/ramdisk
256 18:02:06.302466 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 18:02:06.302637 start: 1.6.5 apply-overlay-tftp (timeout 00:09:38) [common]
258 18:02:06.302741 [common] Applying overlay to NFS
259 18:02:06.302815 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14291372/compress-overlay-kpd_g38j/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14291372/extract-nfsrootfs-6eprz0iq
260 18:02:07.442552 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 18:02:07.442773 start: 1.6.6 configure-preseed-file (timeout 00:09:37) [common]
262 18:02:07.442913 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 18:02:07.443040 start: 1.6.7 compress-ramdisk (timeout 00:09:37) [common]
264 18:02:07.443156 Building ramdisk /var/lib/lava/dispatcher/tmp/14291372/extract-overlay-ramdisk-mtlvyg9q/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14291372/extract-overlay-ramdisk-mtlvyg9q/ramdisk
265 18:02:07.833967 >> 130400 blocks
266 18:02:10.115985 rename /var/lib/lava/dispatcher/tmp/14291372/extract-overlay-ramdisk-mtlvyg9q/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14291372/tftp-deploy-hgwt2mnh/ramdisk/ramdisk.cpio.gz
267 18:02:10.116439 end: 1.6.7 compress-ramdisk (duration 00:00:03) [common]
268 18:02:10.116640 start: 1.6.8 prepare-kernel (timeout 00:09:34) [common]
269 18:02:10.116777 start: 1.6.8.1 prepare-fit (timeout 00:09:34) [common]
270 18:02:10.116916 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14291372/tftp-deploy-hgwt2mnh/kernel/Image']
271 18:02:23.811076 Returned 0 in 13 seconds
272 18:02:23.911678 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14291372/tftp-deploy-hgwt2mnh/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14291372/tftp-deploy-hgwt2mnh/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14291372/tftp-deploy-hgwt2mnh/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14291372/tftp-deploy-hgwt2mnh/kernel/image.itb
273 18:02:24.259251 output: FIT description: Kernel Image image with one or more FDT blobs
274 18:02:24.259600 output: Created: Tue Jun 11 19:02:24 2024
275 18:02:24.259677 output: Image 0 (kernel-1)
276 18:02:24.259743 output: Description:
277 18:02:24.259806 output: Created: Tue Jun 11 19:02:24 2024
278 18:02:24.259866 output: Type: Kernel Image
279 18:02:24.259925 output: Compression: lzma compressed
280 18:02:24.259985 output: Data Size: 13125101 Bytes = 12817.48 KiB = 12.52 MiB
281 18:02:24.260045 output: Architecture: AArch64
282 18:02:24.260102 output: OS: Linux
283 18:02:24.260157 output: Load Address: 0x00000000
284 18:02:24.260211 output: Entry Point: 0x00000000
285 18:02:24.260282 output: Hash algo: crc32
286 18:02:24.260381 output: Hash value: 7a9e9d3e
287 18:02:24.260436 output: Image 1 (fdt-1)
288 18:02:24.260490 output: Description: mt8192-asurada-spherion-r0
289 18:02:24.260544 output: Created: Tue Jun 11 19:02:24 2024
290 18:02:24.260641 output: Type: Flat Device Tree
291 18:02:24.260694 output: Compression: uncompressed
292 18:02:24.260747 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
293 18:02:24.260799 output: Architecture: AArch64
294 18:02:24.260852 output: Hash algo: crc32
295 18:02:24.260905 output: Hash value: 0f8e4d2e
296 18:02:24.260957 output: Image 2 (ramdisk-1)
297 18:02:24.261009 output: Description: unavailable
298 18:02:24.261061 output: Created: Tue Jun 11 19:02:24 2024
299 18:02:24.261113 output: Type: RAMDisk Image
300 18:02:24.261165 output: Compression: Unknown Compression
301 18:02:24.261217 output: Data Size: 18740570 Bytes = 18301.34 KiB = 17.87 MiB
302 18:02:24.261270 output: Architecture: AArch64
303 18:02:24.261321 output: OS: Linux
304 18:02:24.261374 output: Load Address: unavailable
305 18:02:24.261426 output: Entry Point: unavailable
306 18:02:24.261478 output: Hash algo: crc32
307 18:02:24.261529 output: Hash value: 06d5ac5d
308 18:02:24.261581 output: Default Configuration: 'conf-1'
309 18:02:24.261633 output: Configuration 0 (conf-1)
310 18:02:24.261685 output: Description: mt8192-asurada-spherion-r0
311 18:02:24.261737 output: Kernel: kernel-1
312 18:02:24.261788 output: Init Ramdisk: ramdisk-1
313 18:02:24.261840 output: FDT: fdt-1
314 18:02:24.261892 output: Loadables: kernel-1
315 18:02:24.261944 output:
316 18:02:24.262127 end: 1.6.8.1 prepare-fit (duration 00:00:14) [common]
317 18:02:24.262223 end: 1.6.8 prepare-kernel (duration 00:00:14) [common]
318 18:02:24.262330 end: 1.6 prepare-tftp-overlay (duration 00:00:32) [common]
319 18:02:24.262424 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:20) [common]
320 18:02:24.262497 No LXC device requested
321 18:02:24.262573 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 18:02:24.262658 start: 1.8 deploy-device-env (timeout 00:09:20) [common]
323 18:02:24.262736 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 18:02:24.262803 Checking files for TFTP limit of 4294967296 bytes.
325 18:02:24.263288 end: 1 tftp-deploy (duration 00:00:40) [common]
326 18:02:24.263397 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 18:02:24.263488 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 18:02:24.263612 substitutions:
329 18:02:24.263684 - {DTB}: 14291372/tftp-deploy-hgwt2mnh/dtb/mt8192-asurada-spherion-r0.dtb
330 18:02:24.263745 - {INITRD}: 14291372/tftp-deploy-hgwt2mnh/ramdisk/ramdisk.cpio.gz
331 18:02:24.263804 - {KERNEL}: 14291372/tftp-deploy-hgwt2mnh/kernel/Image
332 18:02:24.263862 - {LAVA_MAC}: None
333 18:02:24.263917 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/14291372/extract-nfsrootfs-6eprz0iq
334 18:02:24.263972 - {NFS_SERVER_IP}: 192.168.201.1
335 18:02:24.264027 - {PRESEED_CONFIG}: None
336 18:02:24.264081 - {PRESEED_LOCAL}: None
337 18:02:24.264133 - {RAMDISK}: 14291372/tftp-deploy-hgwt2mnh/ramdisk/ramdisk.cpio.gz
338 18:02:24.264187 - {ROOT_PART}: None
339 18:02:24.264240 - {ROOT}: None
340 18:02:24.264294 - {SERVER_IP}: 192.168.201.1
341 18:02:24.264347 - {TEE}: None
342 18:02:24.264400 Parsed boot commands:
343 18:02:24.264452 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 18:02:24.264659 Parsed boot commands: tftpboot 192.168.201.1 14291372/tftp-deploy-hgwt2mnh/kernel/image.itb 14291372/tftp-deploy-hgwt2mnh/kernel/cmdline
345 18:02:24.264748 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 18:02:24.264832 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 18:02:24.264920 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 18:02:24.265011 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 18:02:24.265084 Not connected, no need to disconnect.
350 18:02:24.265157 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 18:02:24.265240 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 18:02:24.265307 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-1'
353 18:02:24.268413 Setting prompt string to ['lava-test: # ']
354 18:02:24.268796 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 18:02:24.268939 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 18:02:24.269054 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 18:02:24.269210 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 18:02:24.269426 Calling: ['/usr/local/bin/chromebook-reboot.sh', 'mt8192-asurada-spherion-r0-cbg-1']
359 18:02:37.784172 Returned 0 in 13 seconds
360 18:02:37.884823 end: 2.2.2.1 pdu-reboot (duration 00:00:14) [common]
362 18:02:37.885268 end: 2.2.2 reset-device (duration 00:00:14) [common]
363 18:02:37.885415 start: 2.2.3 depthcharge-start (timeout 00:04:46) [common]
364 18:02:37.885565 Setting prompt string to 'Starting depthcharge on Spherion...'
365 18:02:37.885677 Changing prompt to 'Starting depthcharge on Spherion...'
366 18:02:37.885778 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
367 18:02:37.886385 [Enter `^Ec?' for help]
368 18:02:37.886494
369 18:02:37.886602
370 18:02:37.886714 F0: 102B 0000
371 18:02:37.886836
372 18:02:37.886927 F3: 1001 0000 [0200]
373 18:02:37.887022
374 18:02:37.887122 F3: 1001 0000
375 18:02:37.887210
376 18:02:37.887305 F7: 102D 0000
377 18:02:37.887391
378 18:02:37.887486 F1: 0000 0000
379 18:02:37.887578
380 18:02:37.887662 V0: 0000 0000 [0001]
381 18:02:37.887785
382 18:02:37.887912 00: 0007 8000
383 18:02:37.888034
384 18:02:37.888127 01: 0000 0000
385 18:02:37.888234
386 18:02:37.888323 BP: 0C00 0209 [0000]
387 18:02:37.888411
388 18:02:37.888504 G0: 1182 0000
389 18:02:37.888626
390 18:02:37.888697 EC: 0000 0021 [4000]
391 18:02:37.888784
392 18:02:37.888868 S7: 0000 0000 [0000]
393 18:02:37.888967
394 18:02:37.889054 CC: 0000 0000 [0001]
395 18:02:37.889143
396 18:02:37.889235 T0: 0000 0040 [010F]
397 18:02:37.889325
398 18:02:37.889417 Jump to BL
399 18:02:37.889502
400 18:02:37.889589
401 18:02:37.889684
402 18:02:37.889770 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
403 18:02:37.889871 ARM64: Exception handlers installed.
404 18:02:37.889958 ARM64: Testing exception
405 18:02:37.890051 ARM64: Done test exception
406 18:02:37.890145 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
407 18:02:37.890232 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
408 18:02:37.890328 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
409 18:02:37.890417 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
410 18:02:37.890549 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
411 18:02:37.890638 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
412 18:02:37.890728 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
413 18:02:37.890825 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
414 18:02:37.890914 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
415 18:02:37.891004 WDT: Last reset was cold boot
416 18:02:37.891096 SPI1(PAD0) initialized at 2873684 Hz
417 18:02:37.891189 SPI5(PAD0) initialized at 992727 Hz
418 18:02:37.891280 VBOOT: Loading verstage.
419 18:02:37.891366 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
420 18:02:37.891482 FMAP: Found "FLASH" version 1.1 at 0x20000.
421 18:02:37.891577 FMAP: base = 0x0 size = 0x800000 #areas = 25
422 18:02:37.891685 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
423 18:02:37.891779 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
424 18:02:37.891872 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
425 18:02:37.891973 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
426 18:02:37.892059
427 18:02:37.892149
428 18:02:37.892242 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
429 18:02:37.892341 ARM64: Exception handlers installed.
430 18:02:37.892426 ARM64: Testing exception
431 18:02:37.892517 ARM64: Done test exception
432 18:02:37.892661 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
433 18:02:37.892759 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
434 18:02:37.892846 Probing TPM: . done!
435 18:02:37.892929 TPM ready after 0 ms
436 18:02:37.893025 Connected to device vid:did:rid of 1ae0:0028:00
437 18:02:37.893111 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
438 18:02:37.893206 Initialized TPM device CR50 revision 0
439 18:02:37.893292 tlcl_send_startup: Startup return code is 0
440 18:02:37.893381 TPM: setup succeeded
441 18:02:37.893477 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
442 18:02:37.893563 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
443 18:02:37.893653 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
444 18:02:37.893749 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 18:02:37.893833 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
446 18:02:37.893928 in-header: 03 07 00 00 08 00 00 00
447 18:02:37.894013 in-data: aa e4 47 04 13 02 00 00
448 18:02:37.894110 Chrome EC: UHEPI supported
449 18:02:37.894204 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
450 18:02:37.894289 in-header: 03 a9 00 00 08 00 00 00
451 18:02:37.894382 in-data: 84 60 60 08 00 00 00 00
452 18:02:37.894467 Phase 1
453 18:02:37.894617 FMAP: area GBB found @ 3f5000 (12032 bytes)
454 18:02:37.894736 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
455 18:02:37.894855 VB2:vb2_check_recovery() Recovery was requested manually
456 18:02:37.894945 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x7
457 18:02:37.895034 Recovery requested (1009000e)
458 18:02:37.895126 TPM: Extending digest for VBOOT: boot mode into PCR 0
459 18:02:37.895223 tlcl_extend: response is 0
460 18:02:37.895312 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
461 18:02:37.895403 tlcl_extend: response is 0
462 18:02:37.895495 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
463 18:02:37.895595 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
464 18:02:37.895683 BS: bootblock times (exec / console): total (unknown) / 148 ms
465 18:02:37.895770
466 18:02:37.895860
467 18:02:37.895953 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
468 18:02:37.896045 ARM64: Exception handlers installed.
469 18:02:37.896140 ARM64: Testing exception
470 18:02:37.896226 ARM64: Done test exception
471 18:02:37.896311 pmic_efuse_setting: Set efuses in 11 msecs
472 18:02:37.896406 pmwrap_interface_init: Select PMIF_VLD_RDY
473 18:02:37.896491 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
474 18:02:37.896650 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
475 18:02:37.896936 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
476 18:02:37.897028 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
477 18:02:37.897125 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
478 18:02:37.897211 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
479 18:02:37.897320 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
480 18:02:37.897425 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
481 18:02:37.897513 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
482 18:02:37.897608 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
483 18:02:37.897693 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
484 18:02:37.897800 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
485 18:02:37.897907 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
486 18:02:37.898029 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
487 18:02:37.898122 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
488 18:02:37.898230 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
489 18:02:37.898340 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
490 18:02:37.898429 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
491 18:02:37.898515 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
492 18:02:37.898607 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
493 18:02:37.898700 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
494 18:02:37.898792 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
495 18:02:37.898882 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
496 18:02:37.898972 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
497 18:02:37.899064 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
498 18:02:37.899153 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
499 18:02:37.899243 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
500 18:02:37.899336 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
501 18:02:37.899425 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
502 18:02:37.899522 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
503 18:02:37.899609 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
504 18:02:37.899698 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
505 18:02:37.899790 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
506 18:02:37.899879 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
507 18:02:37.899973 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
508 18:02:37.900062 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
509 18:02:37.900152 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
510 18:02:37.900249 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
511 18:02:37.900334 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
512 18:02:37.900423 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
513 18:02:37.900515 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
514 18:02:37.900648 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
515 18:02:37.900743 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
516 18:02:37.900831 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
517 18:02:37.900917 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
518 18:02:37.901010 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
519 18:02:37.901099 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
520 18:02:37.901183 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
521 18:02:37.901278 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
522 18:02:37.901448 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
523 18:02:37.901574 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
524 18:02:37.901674 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
525 18:02:37.901800 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
526 18:02:37.901887 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
527 18:02:37.902018 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
528 18:02:37.902108 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
529 18:02:37.902204 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
530 18:02:37.902291 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
531 18:02:37.902379 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 18:02:37.902475 [RTC]rtc_enable_dcxo,68: con=0x406, osc32con=0xde70, sec=0x1a
533 18:02:37.902562 [RTC]rtc_check_state,173: con=406, pwrkey1=a357, pwrkey2=67d2
534 18:02:37.902634 [RTC]rtc_osc_init,62: osc32con val = 0xde70
535 18:02:37.902704 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
536 18:02:37.902760 [RTC]rtc_get_frequency_meter,154: input=15, output=770
537 18:02:37.902826 [RTC]rtc_get_frequency_meter,154: input=23, output=955
538 18:02:37.902918 [RTC]rtc_get_frequency_meter,154: input=19, output=865
539 18:02:37.902975 [RTC]rtc_get_frequency_meter,154: input=17, output=816
540 18:02:37.903030 [RTC]rtc_get_frequency_meter,154: input=16, output=794
541 18:02:37.903093 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
542 18:02:37.903174 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
543 18:02:37.903259 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
544 18:02:37.903343 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
545 18:02:37.903630 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
546 18:02:37.903722 ADC[4]: Raw value=903245 ID=7
547 18:02:37.903815 ADC[3]: Raw value=213179 ID=1
548 18:02:37.903906 RAM Code: 0x71
549 18:02:37.903996 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
550 18:02:37.904092 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
551 18:02:37.904179 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
552 18:02:37.904271 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
553 18:02:37.904368 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
554 18:02:37.904459 in-header: 03 07 00 00 08 00 00 00
555 18:02:37.904544 in-data: aa e4 47 04 13 02 00 00
556 18:02:37.904675 Chrome EC: UHEPI supported
557 18:02:37.904734 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
558 18:02:37.904790 in-header: 03 a9 00 00 08 00 00 00
559 18:02:37.904869 in-data: 84 60 60 08 00 00 00 00
560 18:02:37.904925 MRC: failed to locate region type 0.
561 18:02:37.904980 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
562 18:02:37.905067 DRAM-K: Running full calibration
563 18:02:37.905132 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
564 18:02:37.905187 header.status = 0x0
565 18:02:37.905240 header.version = 0x6 (expected: 0x6)
566 18:02:37.905313 header.size = 0xd00 (expected: 0xd00)
567 18:02:37.905382 header.flags = 0x0
568 18:02:37.905436 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
569 18:02:37.905490 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
570 18:02:37.905557 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
571 18:02:37.905616 dram_init: ddr_geometry: 2
572 18:02:37.905669 [EMI] MDL number = 2
573 18:02:37.905725 [EMI] Get MDL freq = 0
574 18:02:37.905793 dram_init: ddr_type: 0
575 18:02:37.905857 is_discrete_lpddr4: 1
576 18:02:37.905911 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
577 18:02:37.905964
578 18:02:37.906050
579 18:02:37.906135 [Bian_co] ETT version 0.0.0.1
580 18:02:37.906258 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
581 18:02:37.906350
582 18:02:37.906435 dramc_set_vcore_voltage set vcore to 650000
583 18:02:37.906527 Read voltage for 800, 4
584 18:02:37.906620 Vio18 = 0
585 18:02:37.906709 Vcore = 650000
586 18:02:37.906800 Vdram = 0
587 18:02:37.906889 Vddq = 0
588 18:02:37.906978 Vmddr = 0
589 18:02:37.907070 dram_init: config_dvfs: 1
590 18:02:37.907159 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
591 18:02:37.907250 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
592 18:02:37.907342 [SwImpedanceCal] DRVP=10, DRVN=17, ODTN=10
593 18:02:37.907431 freq_region=0, Reg: DRVP=10, DRVN=17, ODTN=10
594 18:02:37.907524 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
595 18:02:37.907616 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
596 18:02:37.907705 MEM_TYPE=3, freq_sel=18
597 18:02:37.907815 sv_algorithm_assistance_LP4_1600
598 18:02:37.907946 ============ PULL DRAM RESETB DOWN ============
599 18:02:37.908077 ========== PULL DRAM RESETB DOWN end =========
600 18:02:37.908185 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
601 18:02:37.908279 ===================================
602 18:02:37.908373 LPDDR4 DRAM CONFIGURATION
603 18:02:37.908460 ===================================
604 18:02:37.908562 EX_ROW_EN[0] = 0x0
605 18:02:37.908635 EX_ROW_EN[1] = 0x0
606 18:02:37.908689 LP4Y_EN = 0x0
607 18:02:37.908759 WORK_FSP = 0x0
608 18:02:37.908826 WL = 0x2
609 18:02:37.908881 RL = 0x2
610 18:02:37.908934 BL = 0x2
611 18:02:37.909003 RPST = 0x0
612 18:02:37.909069 RD_PRE = 0x0
613 18:02:37.909125 WR_PRE = 0x1
614 18:02:37.909178 WR_PST = 0x0
615 18:02:37.909252 DBI_WR = 0x0
616 18:02:37.909308 DBI_RD = 0x0
617 18:02:37.909361 OTF = 0x1
618 18:02:37.909415 ===================================
619 18:02:37.909495 ===================================
620 18:02:37.909583 ANA top config
621 18:02:37.909667 ===================================
622 18:02:37.909764 DLL_ASYNC_EN = 0
623 18:02:37.909851 ALL_SLAVE_EN = 1
624 18:02:37.909934 NEW_RANK_MODE = 1
625 18:02:37.910030 DLL_IDLE_MODE = 1
626 18:02:37.910131 LP45_APHY_COMB_EN = 1
627 18:02:37.910244 TX_ODT_DIS = 1
628 18:02:37.910329 NEW_8X_MODE = 1
629 18:02:37.910420 ===================================
630 18:02:37.910508 ===================================
631 18:02:37.910595 data_rate = 1600
632 18:02:37.910690 CKR = 1
633 18:02:37.910775 DQ_P2S_RATIO = 8
634 18:02:37.910866 ===================================
635 18:02:37.910959 CA_P2S_RATIO = 8
636 18:02:37.911043 DQ_CA_OPEN = 0
637 18:02:37.911137 DQ_SEMI_OPEN = 0
638 18:02:37.911251 CA_SEMI_OPEN = 0
639 18:02:37.911379 CA_FULL_RATE = 0
640 18:02:37.911497 DQ_CKDIV4_EN = 1
641 18:02:37.911606 CA_CKDIV4_EN = 1
642 18:02:37.911740 CA_PREDIV_EN = 0
643 18:02:37.911846 PH8_DLY = 0
644 18:02:37.911950 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
645 18:02:37.912055 DQ_AAMCK_DIV = 4
646 18:02:37.912195 CA_AAMCK_DIV = 4
647 18:02:37.912297 CA_ADMCK_DIV = 4
648 18:02:37.912403 DQ_TRACK_CA_EN = 0
649 18:02:37.912509 CA_PICK = 800
650 18:02:37.912628 CA_MCKIO = 800
651 18:02:37.912714 MCKIO_SEMI = 0
652 18:02:37.912857 PLL_FREQ = 3068
653 18:02:37.912958 DQ_UI_PI_RATIO = 32
654 18:02:37.913064 CA_UI_PI_RATIO = 0
655 18:02:37.913199 ===================================
656 18:02:37.913286 ===================================
657 18:02:37.913409 memory_type:LPDDR4
658 18:02:37.913512 GP_NUM : 10
659 18:02:37.913651 SRAM_EN : 1
660 18:02:37.913737 MD32_EN : 0
661 18:02:37.913860 ===================================
662 18:02:37.913978 [ANA_INIT] >>>>>>>>>>>>>>
663 18:02:37.914084 <<<<<< [CONFIGURE PHASE]: ANA_TX
664 18:02:37.914176 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
665 18:02:37.914266 ===================================
666 18:02:37.914592 data_rate = 1600,PCW = 0X7600
667 18:02:37.914661 ===================================
668 18:02:37.914719 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
669 18:02:37.914781 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
670 18:02:37.914856 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
671 18:02:37.914915 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
672 18:02:37.914971 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
673 18:02:37.915037 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
674 18:02:37.915115 [ANA_INIT] flow start
675 18:02:37.915171 [ANA_INIT] PLL >>>>>>>>
676 18:02:37.915228 [ANA_INIT] PLL <<<<<<<<
677 18:02:37.915299 [ANA_INIT] MIDPI >>>>>>>>
678 18:02:37.915363 [ANA_INIT] MIDPI <<<<<<<<
679 18:02:37.915418 [ANA_INIT] DLL >>>>>>>>
680 18:02:37.915472 [ANA_INIT] flow end
681 18:02:37.915547 ============ LP4 DIFF to SE enter ============
682 18:02:37.915605 ============ LP4 DIFF to SE exit ============
683 18:02:37.915660 [ANA_INIT] <<<<<<<<<<<<<
684 18:02:37.915733 [Flow] Enable top DCM control >>>>>
685 18:02:37.915831 [Flow] Enable top DCM control <<<<<
686 18:02:37.915922 Enable DLL master slave shuffle
687 18:02:37.916020 ==============================================================
688 18:02:37.916108 Gating Mode config
689 18:02:37.916213 ==============================================================
690 18:02:37.916307 Config description:
691 18:02:37.916393 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
692 18:02:37.916489 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
693 18:02:37.916616 SELPH_MODE 0: By rank 1: By Phase
694 18:02:37.916702 ==============================================================
695 18:02:37.916787 GAT_TRACK_EN = 1
696 18:02:37.916849 RX_GATING_MODE = 2
697 18:02:37.916915 RX_GATING_TRACK_MODE = 2
698 18:02:37.916970 SELPH_MODE = 1
699 18:02:37.917040 PICG_EARLY_EN = 1
700 18:02:37.917104 VALID_LAT_VALUE = 1
701 18:02:37.917196 ==============================================================
702 18:02:37.917289 Enter into Gating configuration >>>>
703 18:02:37.917378 Exit from Gating configuration <<<<
704 18:02:37.917462 Enter into DVFS_PRE_config >>>>>
705 18:02:37.917552 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
706 18:02:37.917625 Exit from DVFS_PRE_config <<<<<
707 18:02:37.917728 Enter into PICG configuration >>>>
708 18:02:37.917807 Exit from PICG configuration <<<<
709 18:02:37.917895 [RX_INPUT] configuration >>>>>
710 18:02:37.917988 [RX_INPUT] configuration <<<<<
711 18:02:37.918094 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
712 18:02:37.918179 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
713 18:02:37.918275 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
714 18:02:37.918366 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
715 18:02:37.918452 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
716 18:02:37.918548 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
717 18:02:37.918632 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
718 18:02:37.918728 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
719 18:02:37.918814 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
720 18:02:37.918903 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
721 18:02:37.918994 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
722 18:02:37.919084 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
723 18:02:37.919179 ===================================
724 18:02:37.919266 LPDDR4 DRAM CONFIGURATION
725 18:02:37.919353 ===================================
726 18:02:37.919450 EX_ROW_EN[0] = 0x0
727 18:02:37.919534 EX_ROW_EN[1] = 0x0
728 18:02:37.919626 LP4Y_EN = 0x0
729 18:02:37.919712 WORK_FSP = 0x0
730 18:02:37.919801 WL = 0x2
731 18:02:37.919896 RL = 0x2
732 18:02:37.919979 BL = 0x2
733 18:02:37.920071 RPST = 0x0
734 18:02:37.920158 RD_PRE = 0x0
735 18:02:37.920246 WR_PRE = 0x1
736 18:02:37.920338 WR_PST = 0x0
737 18:02:37.920423 DBI_WR = 0x0
738 18:02:37.920511 DBI_RD = 0x0
739 18:02:37.920635 OTF = 0x1
740 18:02:37.920693 ===================================
741 18:02:37.920747 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
742 18:02:37.920814 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
743 18:02:37.920889 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
744 18:02:37.920945 ===================================
745 18:02:37.921014 LPDDR4 DRAM CONFIGURATION
746 18:02:37.921094 ===================================
747 18:02:37.921152 EX_ROW_EN[0] = 0x10
748 18:02:37.921207 EX_ROW_EN[1] = 0x0
749 18:02:37.921270 LP4Y_EN = 0x0
750 18:02:37.921352 WORK_FSP = 0x0
751 18:02:37.921421 WL = 0x2
752 18:02:37.921474 RL = 0x2
753 18:02:37.921568 BL = 0x2
754 18:02:37.921653 RPST = 0x0
755 18:02:37.921743 RD_PRE = 0x0
756 18:02:37.921834 WR_PRE = 0x1
757 18:02:37.921919 WR_PST = 0x0
758 18:02:37.922006 DBI_WR = 0x0
759 18:02:37.922100 DBI_RD = 0x0
760 18:02:37.922189 OTF = 0x1
761 18:02:37.922275 ===================================
762 18:02:37.922370 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
763 18:02:37.922455 nWR fixed to 40
764 18:02:37.922548 [ModeRegInit_LP4] CH0 RK0
765 18:02:37.922634 [ModeRegInit_LP4] CH0 RK1
766 18:02:37.922717 [ModeRegInit_LP4] CH1 RK0
767 18:02:37.922816 [ModeRegInit_LP4] CH1 RK1
768 18:02:37.922900 match AC timing 13
769 18:02:37.922986 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
770 18:02:37.923084 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
771 18:02:37.923169 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
772 18:02:37.923257 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
773 18:02:37.923554 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
774 18:02:37.923647 [EMI DOE] emi_dcm 0
775 18:02:37.923754 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
776 18:02:37.923845 ==
777 18:02:37.923938 Dram Type= 6, Freq= 0, CH_0, rank 0
778 18:02:37.924037 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
779 18:02:37.924155 ==
780 18:02:37.924250 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
781 18:02:37.924340 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
782 18:02:37.924436 [CA 0] Center 38 (7~69) winsize 63
783 18:02:37.924528 [CA 1] Center 38 (7~69) winsize 63
784 18:02:37.924652 [CA 2] Center 35 (5~66) winsize 62
785 18:02:37.924744 [CA 3] Center 35 (5~66) winsize 62
786 18:02:37.924829 [CA 4] Center 35 (4~66) winsize 63
787 18:02:37.924923 [CA 5] Center 33 (3~64) winsize 62
788 18:02:37.925009
789 18:02:37.925093 [CmdBusTrainingLP45] Vref(ca) range 1: 32
790 18:02:37.925219
791 18:02:37.925358 [CATrainingPosCal] consider 1 rank data
792 18:02:37.925462 u2DelayCellTimex100 = 270/100 ps
793 18:02:37.925551 CA0 delay=38 (7~69),Diff = 5 PI (36 cell)
794 18:02:37.925646 CA1 delay=38 (7~69),Diff = 5 PI (36 cell)
795 18:02:37.925733 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
796 18:02:37.925817 CA3 delay=35 (5~66),Diff = 2 PI (14 cell)
797 18:02:37.925912 CA4 delay=35 (4~66),Diff = 2 PI (14 cell)
798 18:02:37.926001 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
799 18:02:37.926093
800 18:02:37.926181 CA PerBit enable=1, Macro0, CA PI delay=33
801 18:02:37.926265
802 18:02:37.926362 [CBTSetCACLKResult] CA Dly = 33
803 18:02:37.926448 CS Dly: 6 (0~37)
804 18:02:37.926531 ==
805 18:02:37.926626 Dram Type= 6, Freq= 0, CH_0, rank 1
806 18:02:37.926716 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
807 18:02:37.926808 ==
808 18:02:37.926897 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
809 18:02:37.926982 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
810 18:02:37.927077 [CA 0] Center 38 (7~69) winsize 63
811 18:02:37.927182 [CA 1] Center 38 (7~69) winsize 63
812 18:02:37.927276 [CA 2] Center 36 (5~67) winsize 63
813 18:02:37.927368 [CA 3] Center 35 (5~66) winsize 62
814 18:02:37.927467 [CA 4] Center 35 (4~66) winsize 63
815 18:02:37.927561 [CA 5] Center 34 (4~65) winsize 62
816 18:02:37.927647
817 18:02:37.927737 [CmdBusTrainingLP45] Vref(ca) range 1: 32
818 18:02:37.927848
819 18:02:37.927936 [CATrainingPosCal] consider 2 rank data
820 18:02:37.928022 u2DelayCellTimex100 = 270/100 ps
821 18:02:37.928120 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
822 18:02:37.928223 CA1 delay=38 (7~69),Diff = 4 PI (28 cell)
823 18:02:37.928318 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
824 18:02:37.928408 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
825 18:02:37.928495 CA4 delay=35 (4~66),Diff = 1 PI (7 cell)
826 18:02:37.928631 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
827 18:02:37.928717
828 18:02:37.928804 CA PerBit enable=1, Macro0, CA PI delay=34
829 18:02:37.928868
830 18:02:37.928955 [CBTSetCACLKResult] CA Dly = 34
831 18:02:37.929050 CS Dly: 6 (0~38)
832 18:02:37.929139
833 18:02:37.929311 ----->DramcWriteLeveling(PI) begin...
834 18:02:37.929418 ==
835 18:02:37.929507 Dram Type= 6, Freq= 0, CH_0, rank 0
836 18:02:37.929600 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
837 18:02:37.929688 ==
838 18:02:37.929778 Write leveling (Byte 0): 32 => 32
839 18:02:37.929890 Write leveling (Byte 1): 32 => 32
840 18:02:37.929982 DramcWriteLeveling(PI) end<-----
841 18:02:37.930088
842 18:02:37.930182 ==
843 18:02:37.930271 Dram Type= 6, Freq= 0, CH_0, rank 0
844 18:02:37.930364 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
845 18:02:37.930452 ==
846 18:02:37.930573 [Gating] SW mode calibration
847 18:02:37.930665 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
848 18:02:37.930758 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
849 18:02:37.930852 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
850 18:02:37.930940 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
851 18:02:37.931029 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
852 18:02:37.931142 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
853 18:02:37.931236 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
854 18:02:37.931342 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
855 18:02:37.931433 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 18:02:37.931520 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 18:02:37.931613 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 18:02:37.931706 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 18:02:37.931793 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 18:02:37.931887 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 18:02:37.931976 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 18:02:37.932063 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 18:02:37.932156 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 18:02:37.932265 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 18:02:37.932359 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 18:02:37.932449 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
867 18:02:37.932540 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
868 18:02:37.932669 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 18:02:37.932758 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 18:02:37.932849 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
871 18:02:37.932942 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
872 18:02:37.933044 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 18:02:37.933142 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 18:02:37.933245 0 9 4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
875 18:02:37.933339 0 9 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
876 18:02:37.933428 0 9 12 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
877 18:02:37.933513 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
878 18:02:37.933609 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
879 18:02:37.933696 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
880 18:02:37.933780 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
881 18:02:37.934083 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 18:02:37.934178 0 10 4 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (1 0)
883 18:02:37.934287 0 10 8 | B1->B0 | 3131 2323 | 1 0 | (1 0) (0 0)
884 18:02:37.934385 0 10 12 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
885 18:02:37.934473 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
886 18:02:37.934570 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
887 18:02:37.934673 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
888 18:02:37.934758 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
889 18:02:37.934854 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 18:02:37.934940 0 11 4 | B1->B0 | 2323 3535 | 0 1 | (0 0) (0 0)
891 18:02:37.935032 0 11 8 | B1->B0 | 2828 4646 | 0 0 | (0 0) (0 0)
892 18:02:37.935122 0 11 12 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
893 18:02:37.935206 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
894 18:02:37.935301 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
895 18:02:37.935389 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
896 18:02:37.935474 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
897 18:02:37.935571 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 18:02:37.935657 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 18:02:37.935748 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
900 18:02:37.935839 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
901 18:02:37.935923 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
902 18:02:37.936019 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
903 18:02:37.936106 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
904 18:02:37.936215 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 18:02:37.936310 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 18:02:37.936399 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 18:02:37.936502 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 18:02:37.936609 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 18:02:37.936705 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 18:02:37.936800 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 18:02:37.936887 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 18:02:37.936987 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 18:02:37.937077 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 18:02:37.937164 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
915 18:02:37.937261 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
916 18:02:37.937349 Total UI for P1: 0, mck2ui 16
917 18:02:37.937436 best dqsien dly found for B0: ( 0, 14, 4)
918 18:02:37.937535 Total UI for P1: 0, mck2ui 16
919 18:02:37.937627 best dqsien dly found for B1: ( 0, 14, 6)
920 18:02:37.937723 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
921 18:02:37.937815 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
922 18:02:37.937912
923 18:02:37.938010 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
924 18:02:37.938127 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
925 18:02:37.938253 [Gating] SW calibration Done
926 18:02:37.938341 ==
927 18:02:37.938429 Dram Type= 6, Freq= 0, CH_0, rank 0
928 18:02:37.938524 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
929 18:02:37.938609 ==
930 18:02:37.938701 RX Vref Scan: 0
931 18:02:37.938819
932 18:02:37.938943 RX Vref 0 -> 0, step: 1
933 18:02:37.939048
934 18:02:37.939170 RX Delay -130 -> 252, step: 16
935 18:02:37.939274 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
936 18:02:37.939359 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
937 18:02:37.939453 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
938 18:02:37.939540 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
939 18:02:37.939623 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
940 18:02:37.939717 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
941 18:02:37.939804 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
942 18:02:37.939925 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
943 18:02:37.940016 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
944 18:02:37.940132 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
945 18:02:37.940226 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
946 18:02:37.940313 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
947 18:02:37.940432 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
948 18:02:37.940521 iDelay=222, Bit 13, Center 77 (-34 ~ 189) 224
949 18:02:37.940596 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
950 18:02:37.940694 iDelay=222, Bit 15, Center 77 (-34 ~ 189) 224
951 18:02:37.940799 ==
952 18:02:37.940887 Dram Type= 6, Freq= 0, CH_0, rank 0
953 18:02:37.940983 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
954 18:02:37.941082 ==
955 18:02:37.941175 DQS Delay:
956 18:02:37.941262 DQS0 = 0, DQS1 = 0
957 18:02:37.941346 DQM Delay:
958 18:02:37.941433 DQM0 = 88, DQM1 = 77
959 18:02:37.941519 DQ Delay:
960 18:02:37.941606 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
961 18:02:37.941701 DQ4 =85, DQ5 =77, DQ6 =101, DQ7 =101
962 18:02:37.941787 DQ8 =77, DQ9 =61, DQ10 =77, DQ11 =77
963 18:02:37.941872 DQ12 =77, DQ13 =77, DQ14 =93, DQ15 =77
964 18:02:37.941967
965 18:02:37.942050
966 18:02:37.942140 ==
967 18:02:37.942229 Dram Type= 6, Freq= 0, CH_0, rank 0
968 18:02:37.942313 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
969 18:02:37.942407 ==
970 18:02:37.942492
971 18:02:37.942582
972 18:02:37.942676 TX Vref Scan disable
973 18:02:37.942761 == TX Byte 0 ==
974 18:02:37.942845 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
975 18:02:37.942940 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
976 18:02:37.943029 == TX Byte 1 ==
977 18:02:37.943122 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
978 18:02:37.943210 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
979 18:02:37.943297 ==
980 18:02:37.943392 Dram Type= 6, Freq= 0, CH_0, rank 0
981 18:02:37.943478 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
982 18:02:37.943580 ==
983 18:02:37.943689 TX Vref=22, minBit 6, minWin=27, winSum=439
984 18:02:37.943776 TX Vref=24, minBit 8, minWin=27, winSum=445
985 18:02:37.943868 TX Vref=26, minBit 8, minWin=27, winSum=451
986 18:02:37.943957 TX Vref=28, minBit 0, minWin=28, winSum=456
987 18:02:37.944041 TX Vref=30, minBit 5, minWin=28, winSum=459
988 18:02:37.944152 TX Vref=32, minBit 1, minWin=28, winSum=457
989 18:02:37.944455 [TxChooseVref] Worse bit 5, Min win 28, Win sum 459, Final Vref 30
990 18:02:37.944555
991 18:02:37.944667 Final TX Range 1 Vref 30
992 18:02:37.944757
993 18:02:37.944848 ==
994 18:02:37.944937 Dram Type= 6, Freq= 0, CH_0, rank 0
995 18:02:37.945022 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
996 18:02:37.945117 ==
997 18:02:37.945205
998 18:02:37.945287
999 18:02:37.945398 TX Vref Scan disable
1000 18:02:37.945501 == TX Byte 0 ==
1001 18:02:37.945593 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1002 18:02:37.945682 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1003 18:02:37.945766 == TX Byte 1 ==
1004 18:02:37.945861 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1005 18:02:37.945948 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1006 18:02:37.946038
1007 18:02:37.946133 [DATLAT]
1008 18:02:37.946218 Freq=800, CH0 RK0
1009 18:02:37.946303
1010 18:02:37.946394 DATLAT Default: 0xa
1011 18:02:37.946484 0, 0xFFFF, sum = 0
1012 18:02:37.946580 1, 0xFFFF, sum = 0
1013 18:02:37.946669 2, 0xFFFF, sum = 0
1014 18:02:37.946755 3, 0xFFFF, sum = 0
1015 18:02:37.946874 4, 0xFFFF, sum = 0
1016 18:02:37.946969 5, 0xFFFF, sum = 0
1017 18:02:37.947068 6, 0xFFFF, sum = 0
1018 18:02:37.947174 7, 0xFFFF, sum = 0
1019 18:02:37.947263 8, 0xFFFF, sum = 0
1020 18:02:37.947360 9, 0x0, sum = 1
1021 18:02:37.947465 10, 0x0, sum = 2
1022 18:02:37.947563 11, 0x0, sum = 3
1023 18:02:37.947653 12, 0x0, sum = 4
1024 18:02:37.947744 best_step = 10
1025 18:02:37.947858
1026 18:02:37.947944 ==
1027 18:02:37.948035 Dram Type= 6, Freq= 0, CH_0, rank 0
1028 18:02:37.948148 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1029 18:02:37.948235 ==
1030 18:02:37.948331 RX Vref Scan: 1
1031 18:02:37.948430
1032 18:02:37.948516 Set Vref Range= 32 -> 127
1033 18:02:37.948653
1034 18:02:37.948738 RX Vref 32 -> 127, step: 1
1035 18:02:37.948811
1036 18:02:37.948868 RX Delay -95 -> 252, step: 8
1037 18:02:37.948921
1038 18:02:37.948974 Set Vref, RX VrefLevel [Byte0]: 32
1039 18:02:37.949053 [Byte1]: 32
1040 18:02:37.949135
1041 18:02:37.949231 Set Vref, RX VrefLevel [Byte0]: 33
1042 18:02:37.949306 [Byte1]: 33
1043 18:02:37.949369
1044 18:02:37.949453 Set Vref, RX VrefLevel [Byte0]: 34
1045 18:02:37.949538 [Byte1]: 34
1046 18:02:37.949622
1047 18:02:37.949708 Set Vref, RX VrefLevel [Byte0]: 35
1048 18:02:37.949803 [Byte1]: 35
1049 18:02:37.949887
1050 18:02:37.949981 Set Vref, RX VrefLevel [Byte0]: 36
1051 18:02:37.950068 [Byte1]: 36
1052 18:02:37.950155
1053 18:02:37.950247 Set Vref, RX VrefLevel [Byte0]: 37
1054 18:02:37.950335 [Byte1]: 37
1055 18:02:37.950421
1056 18:02:37.950510 Set Vref, RX VrefLevel [Byte0]: 38
1057 18:02:37.950597 [Byte1]: 38
1058 18:02:37.950704
1059 18:02:37.950791 Set Vref, RX VrefLevel [Byte0]: 39
1060 18:02:37.950878 [Byte1]: 39
1061 18:02:37.950984
1062 18:02:37.951069 Set Vref, RX VrefLevel [Byte0]: 40
1063 18:02:37.951152 [Byte1]: 40
1064 18:02:37.951245
1065 18:02:37.951329 Set Vref, RX VrefLevel [Byte0]: 41
1066 18:02:37.951418 [Byte1]: 41
1067 18:02:37.951505
1068 18:02:37.951591 Set Vref, RX VrefLevel [Byte0]: 42
1069 18:02:37.951683 [Byte1]: 42
1070 18:02:37.951784
1071 18:02:37.951881 Set Vref, RX VrefLevel [Byte0]: 43
1072 18:02:37.951994 [Byte1]: 43
1073 18:02:37.952079
1074 18:02:37.952167 Set Vref, RX VrefLevel [Byte0]: 44
1075 18:02:37.952270 [Byte1]: 44
1076 18:02:37.952351
1077 18:02:37.952438 Set Vref, RX VrefLevel [Byte0]: 45
1078 18:02:37.952522 [Byte1]: 45
1079 18:02:37.952632
1080 18:02:37.952712 Set Vref, RX VrefLevel [Byte0]: 46
1081 18:02:37.952794 [Byte1]: 46
1082 18:02:37.952885
1083 18:02:37.952955 Set Vref, RX VrefLevel [Byte0]: 47
1084 18:02:37.953039 [Byte1]: 47
1085 18:02:37.953126
1086 18:02:37.953186 Set Vref, RX VrefLevel [Byte0]: 48
1087 18:02:37.953268 [Byte1]: 48
1088 18:02:37.953358
1089 18:02:37.953445 Set Vref, RX VrefLevel [Byte0]: 49
1090 18:02:37.953527 [Byte1]: 49
1091 18:02:37.953619
1092 18:02:37.953704 Set Vref, RX VrefLevel [Byte0]: 50
1093 18:02:37.953803 [Byte1]: 50
1094 18:02:37.953897
1095 18:02:37.953982 Set Vref, RX VrefLevel [Byte0]: 51
1096 18:02:37.954073 [Byte1]: 51
1097 18:02:37.954162
1098 18:02:37.954258 Set Vref, RX VrefLevel [Byte0]: 52
1099 18:02:37.954349 [Byte1]: 52
1100 18:02:37.954434
1101 18:02:37.954516 Set Vref, RX VrefLevel [Byte0]: 53
1102 18:02:37.954608 [Byte1]: 53
1103 18:02:37.954691
1104 18:02:37.954776 Set Vref, RX VrefLevel [Byte0]: 54
1105 18:02:37.954865 [Byte1]: 54
1106 18:02:37.954948
1107 18:02:37.955039 Set Vref, RX VrefLevel [Byte0]: 55
1108 18:02:37.955124 [Byte1]: 55
1109 18:02:37.955206
1110 18:02:37.955298 Set Vref, RX VrefLevel [Byte0]: 56
1111 18:02:37.955382 [Byte1]: 56
1112 18:02:37.955468
1113 18:02:37.955556 Set Vref, RX VrefLevel [Byte0]: 57
1114 18:02:37.955647 [Byte1]: 57
1115 18:02:37.955740
1116 18:02:37.955826 Set Vref, RX VrefLevel [Byte0]: 58
1117 18:02:37.955908 [Byte1]: 58
1118 18:02:37.956000
1119 18:02:37.956083 Set Vref, RX VrefLevel [Byte0]: 59
1120 18:02:37.956173 [Byte1]: 59
1121 18:02:37.956259
1122 18:02:37.956341 Set Vref, RX VrefLevel [Byte0]: 60
1123 18:02:37.956434 [Byte1]: 60
1124 18:02:37.956518
1125 18:02:37.956649 Set Vref, RX VrefLevel [Byte0]: 61
1126 18:02:37.956736 [Byte1]: 61
1127 18:02:37.956818
1128 18:02:37.956910 Set Vref, RX VrefLevel [Byte0]: 62
1129 18:02:37.956995 [Byte1]: 62
1130 18:02:37.957076
1131 18:02:37.957168 Set Vref, RX VrefLevel [Byte0]: 63
1132 18:02:37.957252 [Byte1]: 63
1133 18:02:37.957341
1134 18:02:37.957426 Set Vref, RX VrefLevel [Byte0]: 64
1135 18:02:37.957510 [Byte1]: 64
1136 18:02:37.957616
1137 18:02:37.957714 Set Vref, RX VrefLevel [Byte0]: 65
1138 18:02:37.957820 [Byte1]: 65
1139 18:02:37.957921
1140 18:02:37.958009 Set Vref, RX VrefLevel [Byte0]: 66
1141 18:02:37.958100 [Byte1]: 66
1142 18:02:37.958187
1143 18:02:37.958269 Set Vref, RX VrefLevel [Byte0]: 67
1144 18:02:37.958359 [Byte1]: 67
1145 18:02:37.958445
1146 18:02:37.958528 Set Vref, RX VrefLevel [Byte0]: 68
1147 18:02:37.958620 [Byte1]: 68
1148 18:02:37.958703
1149 18:02:37.958785 Set Vref, RX VrefLevel [Byte0]: 69
1150 18:02:37.958877 [Byte1]: 69
1151 18:02:37.958961
1152 18:02:37.959043 Set Vref, RX VrefLevel [Byte0]: 70
1153 18:02:37.959135 [Byte1]: 70
1154 18:02:37.959218
1155 18:02:37.959300 Set Vref, RX VrefLevel [Byte0]: 71
1156 18:02:37.959411 [Byte1]: 71
1157 18:02:37.959496
1158 18:02:37.959588 Set Vref, RX VrefLevel [Byte0]: 72
1159 18:02:37.959688 [Byte1]: 72
1160 18:02:37.959769
1161 18:02:37.959861 Set Vref, RX VrefLevel [Byte0]: 73
1162 18:02:37.960144 [Byte1]: 73
1163 18:02:37.960235
1164 18:02:37.960357 Set Vref, RX VrefLevel [Byte0]: 74
1165 18:02:37.960427 [Byte1]: 74
1166 18:02:37.960508
1167 18:02:37.960631 Set Vref, RX VrefLevel [Byte0]: 75
1168 18:02:37.960691 [Byte1]: 75
1169 18:02:37.960773
1170 18:02:37.960913 Set Vref, RX VrefLevel [Byte0]: 76
1171 18:02:37.961033 [Byte1]: 76
1172 18:02:37.961128
1173 18:02:37.961252 Set Vref, RX VrefLevel [Byte0]: 77
1174 18:02:37.961337 [Byte1]: 77
1175 18:02:37.961420
1176 18:02:37.961512 Set Vref, RX VrefLevel [Byte0]: 78
1177 18:02:37.961596 [Byte1]: 78
1178 18:02:37.961684
1179 18:02:37.961771 Set Vref, RX VrefLevel [Byte0]: 79
1180 18:02:37.961855 [Byte1]: 79
1181 18:02:37.961944
1182 18:02:37.962031 Set Vref, RX VrefLevel [Byte0]: 80
1183 18:02:37.962115 [Byte1]: 80
1184 18:02:37.962205
1185 18:02:37.962287 Final RX Vref Byte 0 = 59 to rank0
1186 18:02:37.962373 Final RX Vref Byte 1 = 56 to rank0
1187 18:02:37.962465 Final RX Vref Byte 0 = 59 to rank1
1188 18:02:37.962548 Final RX Vref Byte 1 = 56 to rank1==
1189 18:02:37.962657 Dram Type= 6, Freq= 0, CH_0, rank 0
1190 18:02:37.962757 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1191 18:02:37.962839 ==
1192 18:02:37.962929 DQS Delay:
1193 18:02:37.963015 DQS0 = 0, DQS1 = 0
1194 18:02:37.963097 DQM Delay:
1195 18:02:37.963224 DQM0 = 93, DQM1 = 81
1196 18:02:37.963340 DQ Delay:
1197 18:02:37.963451 DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =88
1198 18:02:37.963539 DQ4 =96, DQ5 =80, DQ6 =104, DQ7 =104
1199 18:02:37.963621 DQ8 =76, DQ9 =72, DQ10 =80, DQ11 =76
1200 18:02:37.963725 DQ12 =84, DQ13 =84, DQ14 =92, DQ15 =88
1201 18:02:37.963811
1202 18:02:37.963900
1203 18:02:37.963989 [DQSOSCAuto] RK0, (LSB)MR18= 0x3935, (MSB)MR19= 0x606, tDQSOscB0 = 396 ps tDQSOscB1 = 395 ps
1204 18:02:37.964074 CH0 RK0: MR19=606, MR18=3935
1205 18:02:37.964182 CH0_RK0: MR19=0x606, MR18=0x3935, DQSOSC=395, MR23=63, INC=94, DEC=63
1206 18:02:37.964269
1207 18:02:37.964353 ----->DramcWriteLeveling(PI) begin...
1208 18:02:37.964449 ==
1209 18:02:37.964536 Dram Type= 6, Freq= 0, CH_0, rank 1
1210 18:02:37.964624 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1211 18:02:37.964719 ==
1212 18:02:37.964817 Write leveling (Byte 0): 32 => 32
1213 18:02:37.964905 Write leveling (Byte 1): 31 => 31
1214 18:02:37.964985 DramcWriteLeveling(PI) end<-----
1215 18:02:37.965068
1216 18:02:37.965156 ==
1217 18:02:37.965233 Dram Type= 6, Freq= 0, CH_0, rank 1
1218 18:02:37.965317 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1219 18:02:37.965406 ==
1220 18:02:37.965490 [Gating] SW mode calibration
1221 18:02:37.965574 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1222 18:02:37.965671 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1223 18:02:37.965756 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1224 18:02:37.965840 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1225 18:02:37.965933 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1226 18:02:37.966019 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 18:02:37.966101 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 18:02:37.966194 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 18:02:37.966279 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 18:02:37.966361 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 18:02:37.966455 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 18:02:37.966540 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 18:02:37.966625 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 18:02:37.966714 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 18:02:37.966798 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 18:02:37.966888 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1237 18:02:37.966975 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1238 18:02:37.967057 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1239 18:02:37.967148 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1240 18:02:37.967234 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1241 18:02:37.967317 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1242 18:02:37.967409 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1243 18:02:37.967510 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1244 18:02:37.967615 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1245 18:02:37.967703 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1246 18:02:37.967785 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1247 18:02:37.967877 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1248 18:02:37.967962 0 9 4 | B1->B0 | 2323 2524 | 0 1 | (0 0) (1 1)
1249 18:02:37.968045 0 9 8 | B1->B0 | 2b2b 3333 | 1 1 | (1 1) (1 1)
1250 18:02:37.968137 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1251 18:02:37.968222 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1252 18:02:37.968304 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1253 18:02:37.968395 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1254 18:02:37.968498 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1255 18:02:37.968610 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1256 18:02:37.968697 0 10 4 | B1->B0 | 3333 2f2f | 1 1 | (0 0) (1 0)
1257 18:02:37.968780 0 10 8 | B1->B0 | 2d2d 2525 | 0 0 | (1 0) (0 0)
1258 18:02:37.968871 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1259 18:02:37.968958 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1260 18:02:37.969042 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1261 18:02:37.969132 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1262 18:02:37.969218 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1263 18:02:37.969305 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1264 18:02:37.969394 0 11 4 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
1265 18:02:37.969477 0 11 8 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
1266 18:02:37.969569 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1267 18:02:37.969654 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1268 18:02:37.969737 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1269 18:02:37.970030 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1270 18:02:37.970126 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1271 18:02:37.970212 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1272 18:02:37.970302 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1273 18:02:37.970389 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1274 18:02:37.970474 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1275 18:02:37.970566 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1276 18:02:37.970649 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1277 18:02:37.970737 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1278 18:02:37.970826 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1279 18:02:37.970908 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1280 18:02:37.971000 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1281 18:02:37.971086 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1282 18:02:37.971168 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1283 18:02:37.971261 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1284 18:02:37.971348 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1285 18:02:37.971431 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1286 18:02:37.971525 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1287 18:02:37.971609 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1288 18:02:37.971695 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1289 18:02:37.971785 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1290 18:02:37.971871 Total UI for P1: 0, mck2ui 16
1291 18:02:37.971961 best dqsien dly found for B0: ( 0, 14, 4)
1292 18:02:37.972047 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1293 18:02:37.972129 Total UI for P1: 0, mck2ui 16
1294 18:02:37.972223 best dqsien dly found for B1: ( 0, 14, 8)
1295 18:02:37.972301 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1296 18:02:37.972356 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1297 18:02:37.972421
1298 18:02:37.972527 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1299 18:02:37.972612 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1300 18:02:37.972686 [Gating] SW calibration Done
1301 18:02:37.972772 ==
1302 18:02:37.972855 Dram Type= 6, Freq= 0, CH_0, rank 1
1303 18:02:37.972946 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1304 18:02:37.973033 ==
1305 18:02:37.973115 RX Vref Scan: 0
1306 18:02:37.973198
1307 18:02:37.973284 RX Vref 0 -> 0, step: 1
1308 18:02:37.973348
1309 18:02:37.973421 RX Delay -130 -> 252, step: 16
1310 18:02:37.973504 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1311 18:02:37.973569 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1312 18:02:37.973638 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1313 18:02:37.973713 iDelay=222, Bit 3, Center 77 (-34 ~ 189) 224
1314 18:02:37.973796 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1315 18:02:37.973890 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
1316 18:02:37.973975 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1317 18:02:37.974057 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1318 18:02:37.974191 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1319 18:02:37.974274 iDelay=222, Bit 9, Center 69 (-34 ~ 173) 208
1320 18:02:37.974365 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1321 18:02:37.974452 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1322 18:02:37.974537 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1323 18:02:37.974629 iDelay=222, Bit 13, Center 77 (-34 ~ 189) 224
1324 18:02:37.974712 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1325 18:02:37.974799 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1326 18:02:37.974888 ==
1327 18:02:37.974971 Dram Type= 6, Freq= 0, CH_0, rank 1
1328 18:02:37.975063 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1329 18:02:37.975148 ==
1330 18:02:37.975230 DQS Delay:
1331 18:02:37.975322 DQS0 = 0, DQS1 = 0
1332 18:02:37.975406 DQM Delay:
1333 18:02:37.975487 DQM0 = 88, DQM1 = 81
1334 18:02:37.975578 DQ Delay:
1335 18:02:37.975664 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =77
1336 18:02:37.975754 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =101
1337 18:02:37.975839 DQ8 =77, DQ9 =69, DQ10 =77, DQ11 =77
1338 18:02:37.975925 DQ12 =85, DQ13 =77, DQ14 =93, DQ15 =93
1339 18:02:37.976014
1340 18:02:37.976098
1341 18:02:37.976179 ==
1342 18:02:37.976272 Dram Type= 6, Freq= 0, CH_0, rank 1
1343 18:02:37.976357 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1344 18:02:37.976440 ==
1345 18:02:37.976531
1346 18:02:37.976632
1347 18:02:37.976686 TX Vref Scan disable
1348 18:02:37.976758 == TX Byte 0 ==
1349 18:02:37.976818 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1350 18:02:37.976901 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1351 18:02:37.976990 == TX Byte 1 ==
1352 18:02:37.977074 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1353 18:02:37.977157 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1354 18:02:37.977242 ==
1355 18:02:37.977327 Dram Type= 6, Freq= 0, CH_0, rank 1
1356 18:02:37.977410 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1357 18:02:37.977523 ==
1358 18:02:37.977623 TX Vref=22, minBit 8, minWin=27, winSum=448
1359 18:02:37.977714 TX Vref=24, minBit 8, minWin=27, winSum=450
1360 18:02:37.977802 TX Vref=26, minBit 8, minWin=27, winSum=452
1361 18:02:37.977885 TX Vref=28, minBit 8, minWin=27, winSum=455
1362 18:02:37.977974 TX Vref=30, minBit 14, minWin=27, winSum=456
1363 18:02:37.978061 TX Vref=32, minBit 6, minWin=28, winSum=457
1364 18:02:37.978143 [TxChooseVref] Worse bit 6, Min win 28, Win sum 457, Final Vref 32
1365 18:02:37.978232
1366 18:02:37.978317 Final TX Range 1 Vref 32
1367 18:02:37.978397
1368 18:02:37.978485 ==
1369 18:02:37.978569 Dram Type= 6, Freq= 0, CH_0, rank 1
1370 18:02:37.978651 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1371 18:02:37.978739 ==
1372 18:02:37.978823
1373 18:02:37.978903
1374 18:02:37.978992 TX Vref Scan disable
1375 18:02:37.979077 == TX Byte 0 ==
1376 18:02:37.979158 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1377 18:02:37.979247 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1378 18:02:37.979332 == TX Byte 1 ==
1379 18:02:37.979415 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1380 18:02:37.979504 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1381 18:02:37.979587
1382 18:02:37.979669 [DATLAT]
1383 18:02:37.979757 Freq=800, CH0 RK1
1384 18:02:37.979839
1385 18:02:37.979922 DATLAT Default: 0xa
1386 18:02:37.980012 0, 0xFFFF, sum = 0
1387 18:02:37.980095 1, 0xFFFF, sum = 0
1388 18:02:37.980185 2, 0xFFFF, sum = 0
1389 18:02:37.980272 3, 0xFFFF, sum = 0
1390 18:02:37.980354 4, 0xFFFF, sum = 0
1391 18:02:37.980466 5, 0xFFFF, sum = 0
1392 18:02:37.980568 6, 0xFFFF, sum = 0
1393 18:02:37.980716 7, 0xFFFF, sum = 0
1394 18:02:37.981033 8, 0xFFFF, sum = 0
1395 18:02:37.981125 9, 0x0, sum = 1
1396 18:02:37.981233 10, 0x0, sum = 2
1397 18:02:37.981324 11, 0x0, sum = 3
1398 18:02:37.981422 12, 0x0, sum = 4
1399 18:02:37.981509 best_step = 10
1400 18:02:37.981597
1401 18:02:37.981694 ==
1402 18:02:37.981786 Dram Type= 6, Freq= 0, CH_0, rank 1
1403 18:02:37.981882 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1404 18:02:37.981970 ==
1405 18:02:37.982053 RX Vref Scan: 0
1406 18:02:37.982145
1407 18:02:37.982230 RX Vref 0 -> 0, step: 1
1408 18:02:37.982312
1409 18:02:37.982405 RX Delay -79 -> 252, step: 8
1410 18:02:37.982491 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1411 18:02:37.982574 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1412 18:02:37.982668 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1413 18:02:37.982753 iDelay=209, Bit 3, Center 84 (-23 ~ 192) 216
1414 18:02:37.982842 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1415 18:02:37.982930 iDelay=209, Bit 5, Center 84 (-23 ~ 192) 216
1416 18:02:37.983015 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1417 18:02:37.983105 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1418 18:02:37.983189 iDelay=209, Bit 8, Center 72 (-31 ~ 176) 208
1419 18:02:37.983275 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1420 18:02:37.983367 iDelay=209, Bit 10, Center 80 (-23 ~ 184) 208
1421 18:02:37.983451 iDelay=209, Bit 11, Center 80 (-23 ~ 184) 208
1422 18:02:37.983537 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1423 18:02:37.983615 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1424 18:02:37.983673 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1425 18:02:37.983726 iDelay=209, Bit 15, Center 84 (-23 ~ 192) 216
1426 18:02:37.983778 ==
1427 18:02:37.983872 Dram Type= 6, Freq= 0, CH_0, rank 1
1428 18:02:37.983958 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1429 18:02:37.984041 ==
1430 18:02:37.984133 DQS Delay:
1431 18:02:37.984217 DQS0 = 0, DQS1 = 0
1432 18:02:37.984300 DQM Delay:
1433 18:02:37.984392 DQM0 = 91, DQM1 = 80
1434 18:02:37.984477 DQ Delay:
1435 18:02:37.984572 DQ0 =88, DQ1 =92, DQ2 =88, DQ3 =84
1436 18:02:37.984665 DQ4 =92, DQ5 =84, DQ6 =100, DQ7 =100
1437 18:02:37.984748 DQ8 =72, DQ9 =68, DQ10 =80, DQ11 =80
1438 18:02:37.984837 DQ12 =84, DQ13 =84, DQ14 =92, DQ15 =84
1439 18:02:37.984925
1440 18:02:37.985008
1441 18:02:37.985099 [DQSOSCAuto] RK1, (LSB)MR18= 0x3d17, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 394 ps
1442 18:02:37.985188 CH0 RK1: MR19=606, MR18=3D17
1443 18:02:37.985275 CH0_RK1: MR19=0x606, MR18=0x3D17, DQSOSC=394, MR23=63, INC=95, DEC=63
1444 18:02:37.985367 [RxdqsGatingPostProcess] freq 800
1445 18:02:37.985454 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1446 18:02:37.985540 Pre-setting of DQS Precalculation
1447 18:02:37.985622 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1448 18:02:37.985707 ==
1449 18:02:37.985799 Dram Type= 6, Freq= 0, CH_1, rank 0
1450 18:02:37.985883 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1451 18:02:37.985968 ==
1452 18:02:37.986053 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1453 18:02:37.986146 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1454 18:02:37.986230 [CA 0] Center 36 (6~67) winsize 62
1455 18:02:37.986322 [CA 1] Center 36 (6~67) winsize 62
1456 18:02:37.986408 [CA 2] Center 34 (4~65) winsize 62
1457 18:02:37.986491 [CA 3] Center 34 (3~65) winsize 63
1458 18:02:37.986583 [CA 4] Center 34 (4~65) winsize 62
1459 18:02:37.986668 [CA 5] Center 33 (3~64) winsize 62
1460 18:02:37.986749
1461 18:02:37.986842 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1462 18:02:37.986926
1463 18:02:37.987008 [CATrainingPosCal] consider 1 rank data
1464 18:02:37.987100 u2DelayCellTimex100 = 270/100 ps
1465 18:02:37.987186 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1466 18:02:37.987276 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1467 18:02:37.987361 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1468 18:02:37.987447 CA3 delay=34 (3~65),Diff = 1 PI (7 cell)
1469 18:02:37.987539 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1470 18:02:37.987622 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1471 18:02:37.987705
1472 18:02:37.987797 CA PerBit enable=1, Macro0, CA PI delay=33
1473 18:02:37.987881
1474 18:02:37.987969 [CBTSetCACLKResult] CA Dly = 33
1475 18:02:37.988057 CS Dly: 6 (0~37)
1476 18:02:37.988140 ==
1477 18:02:37.988230 Dram Type= 6, Freq= 0, CH_1, rank 1
1478 18:02:37.988318 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1479 18:02:37.988401 ==
1480 18:02:37.988493 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1481 18:02:37.988588 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1482 18:02:37.988672 [CA 0] Center 36 (6~67) winsize 62
1483 18:02:37.988766 [CA 1] Center 37 (6~68) winsize 63
1484 18:02:37.988851 [CA 2] Center 35 (5~66) winsize 62
1485 18:02:37.988934 [CA 3] Center 34 (4~65) winsize 62
1486 18:02:37.989026 [CA 4] Center 34 (4~65) winsize 62
1487 18:02:37.989111 [CA 5] Center 33 (3~64) winsize 62
1488 18:02:37.989192
1489 18:02:37.989286 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1490 18:02:37.989370
1491 18:02:37.989453 [CATrainingPosCal] consider 2 rank data
1492 18:02:37.989545 u2DelayCellTimex100 = 270/100 ps
1493 18:02:37.989629 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1494 18:02:37.989719 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1495 18:02:37.989805 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
1496 18:02:37.989889 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1497 18:02:37.989981 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1498 18:02:37.990068 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1499 18:02:37.990150
1500 18:02:37.990241 CA PerBit enable=1, Macro0, CA PI delay=33
1501 18:02:37.990327
1502 18:02:37.990411 [CBTSetCACLKResult] CA Dly = 33
1503 18:02:37.990501 CS Dly: 6 (0~38)
1504 18:02:37.990586
1505 18:02:37.990671 ----->DramcWriteLeveling(PI) begin...
1506 18:02:37.990763 ==
1507 18:02:37.990846 Dram Type= 6, Freq= 0, CH_1, rank 0
1508 18:02:37.990932 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1509 18:02:37.991024 ==
1510 18:02:37.991107 Write leveling (Byte 0): 27 => 27
1511 18:02:37.991199 Write leveling (Byte 1): 28 => 28
1512 18:02:37.991285 DramcWriteLeveling(PI) end<-----
1513 18:02:37.991367
1514 18:02:37.991457 ==
1515 18:02:37.991544 Dram Type= 6, Freq= 0, CH_1, rank 0
1516 18:02:37.991627 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1517 18:02:37.991717 ==
1518 18:02:37.991804 [Gating] SW mode calibration
1519 18:02:37.991888 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1520 18:02:37.991981 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1521 18:02:37.992277 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1522 18:02:37.992369 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1523 18:02:37.992461 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 18:02:37.992556 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 18:02:37.992643 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 18:02:37.992736 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 18:02:37.992822 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 18:02:37.992905 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 18:02:37.992999 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 18:02:37.993085 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 18:02:37.993168 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 18:02:37.993262 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 18:02:37.993347 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 18:02:37.993438 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1535 18:02:37.993528 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1536 18:02:37.993614 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1537 18:02:37.993704 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1538 18:02:37.993791 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1539 18:02:37.993879 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1540 18:02:37.993971 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1541 18:02:37.994057 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1542 18:02:37.994150 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1543 18:02:37.994237 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1544 18:02:37.994325 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1545 18:02:37.994416 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1546 18:02:37.994502 0 9 4 | B1->B0 | 2525 2b2b | 0 0 | (0 0) (0 0)
1547 18:02:37.994585 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1548 18:02:37.994678 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1549 18:02:37.994763 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1550 18:02:37.994848 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1551 18:02:37.994940 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1552 18:02:37.995024 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1553 18:02:37.995113 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1554 18:02:37.995200 0 10 4 | B1->B0 | 2f2f 2d2d | 0 0 | (0 1) (1 1)
1555 18:02:37.995286 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1556 18:02:37.995376 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1557 18:02:37.995463 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1558 18:02:37.995547 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1559 18:02:37.995639 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1560 18:02:37.995726 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1561 18:02:37.995809 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1562 18:02:37.995894 0 11 4 | B1->B0 | 3030 3535 | 0 0 | (0 0) (1 1)
1563 18:02:37.995986 0 11 8 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
1564 18:02:37.996072 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1565 18:02:37.996156 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1566 18:02:37.996243 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1567 18:02:37.996325 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1568 18:02:37.996416 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1569 18:02:37.996503 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1570 18:02:37.996608 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1571 18:02:37.996694 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1572 18:02:37.996781 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1573 18:02:37.996875 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1574 18:02:37.996959 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1575 18:02:37.997045 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1576 18:02:37.997137 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1577 18:02:37.997221 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1578 18:02:37.997312 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1579 18:02:37.997398 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1580 18:02:37.997482 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1581 18:02:37.997574 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1582 18:02:37.997659 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1583 18:02:37.997742 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1584 18:02:37.997835 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1585 18:02:37.997921 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1586 18:02:37.998004 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1587 18:02:37.998098 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1588 18:02:37.998183 Total UI for P1: 0, mck2ui 16
1589 18:02:37.998274 best dqsien dly found for B0: ( 0, 14, 2)
1590 18:02:37.998362 Total UI for P1: 0, mck2ui 16
1591 18:02:37.998447 best dqsien dly found for B1: ( 0, 14, 6)
1592 18:02:37.998539 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1593 18:02:37.998624 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1594 18:02:37.998710
1595 18:02:37.998800 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1596 18:02:37.998883 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1597 18:02:37.998976 [Gating] SW calibration Done
1598 18:02:37.999061 ==
1599 18:02:37.999143 Dram Type= 6, Freq= 0, CH_1, rank 0
1600 18:02:37.999236 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1601 18:02:37.999321 ==
1602 18:02:37.999403 RX Vref Scan: 0
1603 18:02:37.999495
1604 18:02:37.999579 RX Vref 0 -> 0, step: 1
1605 18:02:37.999661
1606 18:02:37.999754 RX Delay -130 -> 252, step: 16
1607 18:02:37.999840 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1608 18:02:37.999922 iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224
1609 18:02:38.000016 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1610 18:02:38.000101 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1611 18:02:38.000382 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1612 18:02:38.000479 iDelay=222, Bit 5, Center 101 (-2 ~ 205) 208
1613 18:02:38.000600 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1614 18:02:38.000685 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1615 18:02:38.000780 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1616 18:02:38.000865 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1617 18:02:38.000953 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1618 18:02:38.001042 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1619 18:02:38.001127 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1620 18:02:38.001217 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1621 18:02:38.001302 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1622 18:02:38.001388 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1623 18:02:38.001480 ==
1624 18:02:38.001563 Dram Type= 6, Freq= 0, CH_1, rank 0
1625 18:02:38.001649 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1626 18:02:38.001741 ==
1627 18:02:38.001826 DQS Delay:
1628 18:02:38.001912 DQS0 = 0, DQS1 = 0
1629 18:02:38.002000 DQM Delay:
1630 18:02:38.002083 DQM0 = 88, DQM1 = 80
1631 18:02:38.002173 DQ Delay:
1632 18:02:38.002259 DQ0 =93, DQ1 =77, DQ2 =77, DQ3 =85
1633 18:02:38.002343 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1634 18:02:38.002434 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
1635 18:02:38.002521 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1636 18:02:38.002604
1637 18:02:38.002695
1638 18:02:38.002779 ==
1639 18:02:38.002869 Dram Type= 6, Freq= 0, CH_1, rank 0
1640 18:02:38.002955 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1641 18:02:38.003037 ==
1642 18:02:38.003130
1643 18:02:38.003214
1644 18:02:38.003296 TX Vref Scan disable
1645 18:02:38.003388 == TX Byte 0 ==
1646 18:02:38.003473 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1647 18:02:38.003557 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1648 18:02:38.003650 == TX Byte 1 ==
1649 18:02:38.003735 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1650 18:02:38.003819 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1651 18:02:38.003910 ==
1652 18:02:38.003996 Dram Type= 6, Freq= 0, CH_1, rank 0
1653 18:02:38.004085 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1654 18:02:38.004173 ==
1655 18:02:38.004259 TX Vref=22, minBit 8, minWin=27, winSum=450
1656 18:02:38.004349 TX Vref=24, minBit 15, minWin=27, winSum=453
1657 18:02:38.004438 TX Vref=26, minBit 15, minWin=27, winSum=454
1658 18:02:38.004523 TX Vref=28, minBit 15, minWin=27, winSum=458
1659 18:02:38.004624 TX Vref=30, minBit 8, minWin=28, winSum=460
1660 18:02:38.004712 TX Vref=32, minBit 8, minWin=28, winSum=460
1661 18:02:38.004796 [TxChooseVref] Worse bit 8, Min win 28, Win sum 460, Final Vref 30
1662 18:02:38.004887
1663 18:02:38.004975 Final TX Range 1 Vref 30
1664 18:02:38.005057
1665 18:02:38.005149 ==
1666 18:02:38.005235 Dram Type= 6, Freq= 0, CH_1, rank 0
1667 18:02:38.005320 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1668 18:02:38.005411 ==
1669 18:02:38.005496
1670 18:02:38.005583
1671 18:02:38.005672 TX Vref Scan disable
1672 18:02:38.005757 == TX Byte 0 ==
1673 18:02:38.005849 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1674 18:02:38.005938 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1675 18:02:38.006023 == TX Byte 1 ==
1676 18:02:38.006114 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1677 18:02:38.006202 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1678 18:02:38.006285
1679 18:02:38.006375 [DATLAT]
1680 18:02:38.006461 Freq=800, CH1 RK0
1681 18:02:38.006546
1682 18:02:38.006628 DATLAT Default: 0xa
1683 18:02:38.006719 0, 0xFFFF, sum = 0
1684 18:02:38.006808 1, 0xFFFF, sum = 0
1685 18:02:38.006893 2, 0xFFFF, sum = 0
1686 18:02:38.006981 3, 0xFFFF, sum = 0
1687 18:02:38.007070 4, 0xFFFF, sum = 0
1688 18:02:38.007159 5, 0xFFFF, sum = 0
1689 18:02:38.007247 6, 0xFFFF, sum = 0
1690 18:02:38.007331 7, 0xFFFF, sum = 0
1691 18:02:38.007415 8, 0xFFFF, sum = 0
1692 18:02:38.007509 9, 0x0, sum = 1
1693 18:02:38.007595 10, 0x0, sum = 2
1694 18:02:38.007686 11, 0x0, sum = 3
1695 18:02:38.007762 12, 0x0, sum = 4
1696 18:02:38.007847 best_step = 10
1697 18:02:38.007937
1698 18:02:38.008023 ==
1699 18:02:38.008106 Dram Type= 6, Freq= 0, CH_1, rank 0
1700 18:02:38.008200 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1701 18:02:38.008285 ==
1702 18:02:38.008367 RX Vref Scan: 1
1703 18:02:38.008459
1704 18:02:38.008543 Set Vref Range= 32 -> 127
1705 18:02:38.008633
1706 18:02:38.008727 RX Vref 32 -> 127, step: 1
1707 18:02:38.008811
1708 18:02:38.008896 RX Delay -95 -> 252, step: 8
1709 18:02:38.008986
1710 18:02:38.009070 Set Vref, RX VrefLevel [Byte0]: 32
1711 18:02:38.009160 [Byte1]: 32
1712 18:02:38.009247
1713 18:02:38.009331 Set Vref, RX VrefLevel [Byte0]: 33
1714 18:02:38.009422 [Byte1]: 33
1715 18:02:38.009508
1716 18:02:38.009591 Set Vref, RX VrefLevel [Byte0]: 34
1717 18:02:38.009683 [Byte1]: 34
1718 18:02:38.009768
1719 18:02:38.009850 Set Vref, RX VrefLevel [Byte0]: 35
1720 18:02:38.009942 [Byte1]: 35
1721 18:02:38.010025
1722 18:02:38.010108 Set Vref, RX VrefLevel [Byte0]: 36
1723 18:02:38.010201 [Byte1]: 36
1724 18:02:38.010285
1725 18:02:38.010373 Set Vref, RX VrefLevel [Byte0]: 37
1726 18:02:38.010461 [Byte1]: 37
1727 18:02:38.010544
1728 18:02:38.010633 Set Vref, RX VrefLevel [Byte0]: 38
1729 18:02:38.010720 [Byte1]: 38
1730 18:02:38.010802
1731 18:02:38.010892 Set Vref, RX VrefLevel [Byte0]: 39
1732 18:02:38.010979 [Byte1]: 39
1733 18:02:38.011060
1734 18:02:38.011152 Set Vref, RX VrefLevel [Byte0]: 40
1735 18:02:38.011237 [Byte1]: 40
1736 18:02:38.011319
1737 18:02:38.011412 Set Vref, RX VrefLevel [Byte0]: 41
1738 18:02:38.011496 [Byte1]: 41
1739 18:02:38.011582
1740 18:02:38.011670 Set Vref, RX VrefLevel [Byte0]: 42
1741 18:02:38.011754 [Byte1]: 42
1742 18:02:38.011844
1743 18:02:38.011930 Set Vref, RX VrefLevel [Byte0]: 43
1744 18:02:38.012013 [Byte1]: 43
1745 18:02:38.012102
1746 18:02:38.012188 Set Vref, RX VrefLevel [Byte0]: 44
1747 18:02:38.012271 [Byte1]: 44
1748 18:02:38.012361
1749 18:02:38.012447 Set Vref, RX VrefLevel [Byte0]: 45
1750 18:02:38.012530 [Byte1]: 45
1751 18:02:38.012622
1752 18:02:38.012696 Set Vref, RX VrefLevel [Byte0]: 46
1753 18:02:38.012779 [Byte1]: 46
1754 18:02:38.012860
1755 18:02:38.012944 Set Vref, RX VrefLevel [Byte0]: 47
1756 18:02:38.013028 [Byte1]: 47
1757 18:02:38.013109
1758 18:02:38.013192 Set Vref, RX VrefLevel [Byte0]: 48
1759 18:02:38.013275 [Byte1]: 48
1760 18:02:38.013351
1761 18:02:38.013435 Set Vref, RX VrefLevel [Byte0]: 49
1762 18:02:38.013517 [Byte1]: 49
1763 18:02:38.013600
1764 18:02:38.013669 Set Vref, RX VrefLevel [Byte0]: 50
1765 18:02:38.013752 [Byte1]: 50
1766 18:02:38.013844
1767 18:02:38.013928 Set Vref, RX VrefLevel [Byte0]: 51
1768 18:02:38.014210 [Byte1]: 51
1769 18:02:38.014308
1770 18:02:38.014396 Set Vref, RX VrefLevel [Byte0]: 52
1771 18:02:38.014479 [Byte1]: 52
1772 18:02:38.014572
1773 18:02:38.014657 Set Vref, RX VrefLevel [Byte0]: 53
1774 18:02:38.014747 [Byte1]: 53
1775 18:02:38.014838
1776 18:02:38.014922 Set Vref, RX VrefLevel [Byte0]: 54
1777 18:02:38.015018 [Byte1]: 54
1778 18:02:38.015106
1779 18:02:38.015189 Set Vref, RX VrefLevel [Byte0]: 55
1780 18:02:38.015284 [Byte1]: 55
1781 18:02:38.015371
1782 18:02:38.015462 Set Vref, RX VrefLevel [Byte0]: 56
1783 18:02:38.015549 [Byte1]: 56
1784 18:02:38.015638
1785 18:02:38.015729 Set Vref, RX VrefLevel [Byte0]: 57
1786 18:02:38.015815 [Byte1]: 57
1787 18:02:38.015902
1788 18:02:38.015994 Set Vref, RX VrefLevel [Byte0]: 58
1789 18:02:38.016083 [Byte1]: 58
1790 18:02:38.016179
1791 18:02:38.016267 Set Vref, RX VrefLevel [Byte0]: 59
1792 18:02:38.016352 [Byte1]: 59
1793 18:02:38.016443
1794 18:02:38.016530 Set Vref, RX VrefLevel [Byte0]: 60
1795 18:02:38.016607 [Byte1]: 60
1796 18:02:38.016700
1797 18:02:38.016788 Set Vref, RX VrefLevel [Byte0]: 61
1798 18:02:38.016876 [Byte1]: 61
1799 18:02:38.016958
1800 18:02:38.017037 Set Vref, RX VrefLevel [Byte0]: 62
1801 18:02:38.017123 [Byte1]: 62
1802 18:02:38.017204
1803 18:02:38.017273 Set Vref, RX VrefLevel [Byte0]: 63
1804 18:02:38.017350 [Byte1]: 63
1805 18:02:38.017433
1806 18:02:38.017513 Set Vref, RX VrefLevel [Byte0]: 64
1807 18:02:38.017600 [Byte1]: 64
1808 18:02:38.017687
1809 18:02:38.017769 Set Vref, RX VrefLevel [Byte0]: 65
1810 18:02:38.017860 [Byte1]: 65
1811 18:02:38.017948
1812 18:02:38.018034 Set Vref, RX VrefLevel [Byte0]: 66
1813 18:02:38.018121 [Byte1]: 66
1814 18:02:38.018205
1815 18:02:38.018296 Set Vref, RX VrefLevel [Byte0]: 67
1816 18:02:38.018384 [Byte1]: 67
1817 18:02:38.018475
1818 18:02:38.018563 Set Vref, RX VrefLevel [Byte0]: 68
1819 18:02:38.018651 [Byte1]: 68
1820 18:02:38.018741
1821 18:02:38.018825 Set Vref, RX VrefLevel [Byte0]: 69
1822 18:02:38.018914 [Byte1]: 69
1823 18:02:38.019005
1824 18:02:38.019092 Set Vref, RX VrefLevel [Byte0]: 70
1825 18:02:38.019180 [Byte1]: 70
1826 18:02:38.019277
1827 18:02:38.019361 Set Vref, RX VrefLevel [Byte0]: 71
1828 18:02:38.019450 [Byte1]: 71
1829 18:02:38.019533
1830 18:02:38.019623 Set Vref, RX VrefLevel [Byte0]: 72
1831 18:02:38.019712 [Byte1]: 72
1832 18:02:38.019796
1833 18:02:38.019887 Set Vref, RX VrefLevel [Byte0]: 73
1834 18:02:38.019977 [Byte1]: 73
1835 18:02:38.020061
1836 18:02:38.020153 Set Vref, RX VrefLevel [Byte0]: 74
1837 18:02:38.020240 [Byte1]: 74
1838 18:02:38.020328
1839 18:02:38.020416 Set Vref, RX VrefLevel [Byte0]: 75
1840 18:02:38.020504 [Byte1]: 75
1841 18:02:38.020603
1842 18:02:38.020689 Set Vref, RX VrefLevel [Byte0]: 76
1843 18:02:38.020752 [Byte1]: 76
1844 18:02:38.020843
1845 18:02:38.020903 Set Vref, RX VrefLevel [Byte0]: 77
1846 18:02:38.020974 [Byte1]: 77
1847 18:02:38.021057
1848 18:02:38.021139 Final RX Vref Byte 0 = 51 to rank0
1849 18:02:38.021214 Final RX Vref Byte 1 = 61 to rank0
1850 18:02:38.021298 Final RX Vref Byte 0 = 51 to rank1
1851 18:02:38.021382 Final RX Vref Byte 1 = 61 to rank1==
1852 18:02:38.021443 Dram Type= 6, Freq= 0, CH_1, rank 0
1853 18:02:38.021529 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1854 18:02:38.021622 ==
1855 18:02:38.021709 DQS Delay:
1856 18:02:38.021793 DQS0 = 0, DQS1 = 0
1857 18:02:38.021885 DQM Delay:
1858 18:02:38.021971 DQM0 = 92, DQM1 = 82
1859 18:02:38.022055 DQ Delay:
1860 18:02:38.022147 DQ0 =96, DQ1 =84, DQ2 =84, DQ3 =88
1861 18:02:38.022235 DQ4 =92, DQ5 =104, DQ6 =100, DQ7 =88
1862 18:02:38.022322 DQ8 =72, DQ9 =68, DQ10 =84, DQ11 =76
1863 18:02:38.022412 DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =88
1864 18:02:38.022501
1865 18:02:38.022600
1866 18:02:38.022689 [DQSOSCAuto] RK0, (LSB)MR18= 0x304d, (MSB)MR19= 0x606, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
1867 18:02:38.022775 CH1 RK0: MR19=606, MR18=304D
1868 18:02:38.022869 CH1_RK0: MR19=0x606, MR18=0x304D, DQSOSC=390, MR23=63, INC=97, DEC=64
1869 18:02:38.022956
1870 18:02:38.023045 ----->DramcWriteLeveling(PI) begin...
1871 18:02:38.023135 ==
1872 18:02:38.023223 Dram Type= 6, Freq= 0, CH_1, rank 1
1873 18:02:38.023315 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1874 18:02:38.023403 ==
1875 18:02:38.023489 Write leveling (Byte 0): 30 => 30
1876 18:02:38.023582 Write leveling (Byte 1): 30 => 30
1877 18:02:38.023668 DramcWriteLeveling(PI) end<-----
1878 18:02:38.023752
1879 18:02:38.023844 ==
1880 18:02:38.023931 Dram Type= 6, Freq= 0, CH_1, rank 1
1881 18:02:38.024019 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1882 18:02:38.024110 ==
1883 18:02:38.024197 [Gating] SW mode calibration
1884 18:02:38.024289 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1885 18:02:38.024376 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1886 18:02:38.024465 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1887 18:02:38.024564 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1888 18:02:38.024650 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 18:02:38.024709 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 18:02:38.024801 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 18:02:38.024886 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 18:02:38.024952 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1893 18:02:38.025044 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1894 18:02:38.025130 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1895 18:02:38.025224 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1896 18:02:38.025312 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1897 18:02:38.025398 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1898 18:02:38.025491 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1899 18:02:38.025581 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1900 18:02:38.025666 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1901 18:02:38.025758 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1902 18:02:38.025852 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1903 18:02:38.025938 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1904 18:02:38.026235 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 1)
1905 18:02:38.026336 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1906 18:02:38.026422 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1907 18:02:38.026509 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1908 18:02:38.026603 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1909 18:02:38.026690 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1910 18:02:38.026777 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1911 18:02:38.026872 0 9 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1912 18:02:38.026956 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1913 18:02:38.027051 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1914 18:02:38.027138 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1915 18:02:38.027225 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1916 18:02:38.027319 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1917 18:02:38.027403 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1918 18:02:38.027494 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
1919 18:02:38.027583 0 10 4 | B1->B0 | 2f2f 2f2f | 1 1 | (1 1) (1 1)
1920 18:02:38.027667 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1921 18:02:38.027760 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1922 18:02:38.027848 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1923 18:02:38.027933 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1924 18:02:38.028024 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1925 18:02:38.028111 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1926 18:02:38.028205 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1927 18:02:38.028291 0 11 4 | B1->B0 | 3434 2e2e | 0 0 | (1 1) (0 0)
1928 18:02:38.028374 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1929 18:02:38.028469 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1930 18:02:38.028571 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1931 18:02:38.028667 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1932 18:02:38.028754 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1933 18:02:38.028837 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1934 18:02:38.028921 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1935 18:02:38.029007 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1936 18:02:38.029089 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1937 18:02:38.029173 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1938 18:02:38.029258 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1939 18:02:38.029341 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1940 18:02:38.029419 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1941 18:02:38.029482 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1942 18:02:38.029565 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1943 18:02:38.029653 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1944 18:02:38.029714 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1945 18:02:38.029797 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1946 18:02:38.029890 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1947 18:02:38.029977 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1948 18:02:38.030061 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1949 18:02:38.030156 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1950 18:02:38.030242 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1951 18:02:38.030325 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1952 18:02:38.030421 Total UI for P1: 0, mck2ui 16
1953 18:02:38.030507 best dqsien dly found for B0: ( 0, 14, 2)
1954 18:02:38.030597 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1955 18:02:38.030688 Total UI for P1: 0, mck2ui 16
1956 18:02:38.030772 best dqsien dly found for B1: ( 0, 14, 4)
1957 18:02:38.030865 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1958 18:02:38.030951 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1959 18:02:38.031033
1960 18:02:38.031127 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1961 18:02:38.031213 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1962 18:02:38.031299 [Gating] SW calibration Done
1963 18:02:38.031393 ==
1964 18:02:38.031478 Dram Type= 6, Freq= 0, CH_1, rank 1
1965 18:02:38.031570 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1966 18:02:38.031656 ==
1967 18:02:38.031744 RX Vref Scan: 0
1968 18:02:38.031836
1969 18:02:38.031921 RX Vref 0 -> 0, step: 1
1970 18:02:38.032003
1971 18:02:38.032096 RX Delay -130 -> 252, step: 16
1972 18:02:38.032181 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
1973 18:02:38.032272 iDelay=206, Bit 1, Center 85 (-18 ~ 189) 208
1974 18:02:38.032360 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1975 18:02:38.032447 iDelay=206, Bit 3, Center 93 (-18 ~ 205) 224
1976 18:02:38.032540 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1977 18:02:38.032606 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1978 18:02:38.032660 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1979 18:02:38.032713 iDelay=206, Bit 7, Center 85 (-18 ~ 189) 208
1980 18:02:38.032790 iDelay=206, Bit 8, Center 77 (-34 ~ 189) 224
1981 18:02:38.032850 iDelay=206, Bit 9, Center 77 (-34 ~ 189) 224
1982 18:02:38.032902 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1983 18:02:38.032955 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1984 18:02:38.033018 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1985 18:02:38.033080 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1986 18:02:38.208353 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1987 18:02:38.208566 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1988 18:02:38.208690 ==
1989 18:02:38.208787 Dram Type= 6, Freq= 0, CH_1, rank 1
1990 18:02:38.208879 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1991 18:02:38.208966 ==
1992 18:02:38.209055 DQS Delay:
1993 18:02:38.209143 DQS0 = 0, DQS1 = 0
1994 18:02:38.209227 DQM Delay:
1995 18:02:38.209316 DQM0 = 89, DQM1 = 82
1996 18:02:38.209401 DQ Delay:
1997 18:02:38.209487 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1998 18:02:38.209568 DQ4 =93, DQ5 =93, DQ6 =93, DQ7 =85
1999 18:02:38.209659 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =77
2000 18:02:38.209743 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
2001 18:02:38.209825
2002 18:02:38.209915
2003 18:02:38.209998 ==
2004 18:02:38.210304 Dram Type= 6, Freq= 0, CH_1, rank 1
2005 18:02:38.210414 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2006 18:02:38.210501 ==
2007 18:02:38.210620
2008 18:02:38.210705
2009 18:02:38.210787 TX Vref Scan disable
2010 18:02:38.210877 == TX Byte 0 ==
2011 18:02:38.210962 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
2012 18:02:38.211044 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
2013 18:02:38.211133 == TX Byte 1 ==
2014 18:02:38.211218 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2015 18:02:38.211337 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2016 18:02:38.211438 ==
2017 18:02:38.211534 Dram Type= 6, Freq= 0, CH_1, rank 1
2018 18:02:38.211628 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2019 18:02:38.211712 ==
2020 18:02:38.211798 TX Vref=22, minBit 6, minWin=27, winSum=447
2021 18:02:38.211884 TX Vref=24, minBit 13, minWin=27, winSum=451
2022 18:02:38.211969 TX Vref=26, minBit 13, minWin=27, winSum=455
2023 18:02:38.212055 TX Vref=28, minBit 8, minWin=28, winSum=459
2024 18:02:38.212140 TX Vref=30, minBit 8, minWin=28, winSum=460
2025 18:02:38.212225 TX Vref=32, minBit 8, minWin=28, winSum=461
2026 18:02:38.212321 [TxChooseVref] Worse bit 8, Min win 28, Win sum 461, Final Vref 32
2027 18:02:38.212459
2028 18:02:38.212567 Final TX Range 1 Vref 32
2029 18:02:38.212630
2030 18:02:38.212685 ==
2031 18:02:38.212751 Dram Type= 6, Freq= 0, CH_1, rank 1
2032 18:02:38.212810 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2033 18:02:38.212865 ==
2034 18:02:38.212920
2035 18:02:38.212971
2036 18:02:38.213027 TX Vref Scan disable
2037 18:02:38.213082 == TX Byte 0 ==
2038 18:02:38.213133 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2039 18:02:38.213189 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2040 18:02:38.213240 == TX Byte 1 ==
2041 18:02:38.213296 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2042 18:02:38.213352 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2043 18:02:38.213406
2044 18:02:38.213488 [DATLAT]
2045 18:02:38.213544 Freq=800, CH1 RK1
2046 18:02:38.213616
2047 18:02:38.213682 DATLAT Default: 0xa
2048 18:02:38.213735 0, 0xFFFF, sum = 0
2049 18:02:38.213788 1, 0xFFFF, sum = 0
2050 18:02:38.213842 2, 0xFFFF, sum = 0
2051 18:02:38.213900 3, 0xFFFF, sum = 0
2052 18:02:38.213955 4, 0xFFFF, sum = 0
2053 18:02:38.214008 5, 0xFFFF, sum = 0
2054 18:02:38.214063 6, 0xFFFF, sum = 0
2055 18:02:38.214116 7, 0xFFFF, sum = 0
2056 18:02:38.214174 8, 0xFFFF, sum = 0
2057 18:02:38.214228 9, 0x0, sum = 1
2058 18:02:38.214283 10, 0x0, sum = 2
2059 18:02:38.214338 11, 0x0, sum = 3
2060 18:02:38.214390 12, 0x0, sum = 4
2061 18:02:38.214448 best_step = 10
2062 18:02:38.214504
2063 18:02:38.214559 ==
2064 18:02:38.214612 Dram Type= 6, Freq= 0, CH_1, rank 1
2065 18:02:38.214664 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2066 18:02:38.214722 ==
2067 18:02:38.214778 RX Vref Scan: 0
2068 18:02:38.214833
2069 18:02:38.214887 RX Vref 0 -> 0, step: 1
2070 18:02:38.214939
2071 18:02:38.214994 RX Delay -79 -> 252, step: 8
2072 18:02:38.215053 iDelay=209, Bit 0, Center 96 (-7 ~ 200) 208
2073 18:02:38.215109 iDelay=209, Bit 1, Center 84 (-15 ~ 184) 200
2074 18:02:38.215162 iDelay=209, Bit 2, Center 80 (-23 ~ 184) 208
2075 18:02:38.215216 iDelay=209, Bit 3, Center 88 (-15 ~ 192) 208
2076 18:02:38.215269 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
2077 18:02:38.215330 iDelay=209, Bit 5, Center 100 (-7 ~ 208) 216
2078 18:02:38.215383 iDelay=209, Bit 6, Center 96 (-7 ~ 200) 208
2079 18:02:38.215435 iDelay=209, Bit 7, Center 88 (-15 ~ 192) 208
2080 18:02:38.215489 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
2081 18:02:38.215548 iDelay=209, Bit 9, Center 72 (-39 ~ 184) 224
2082 18:02:38.215603 iDelay=209, Bit 10, Center 88 (-23 ~ 200) 224
2083 18:02:38.215655 iDelay=209, Bit 11, Center 80 (-31 ~ 192) 224
2084 18:02:38.215709 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
2085 18:02:38.215762 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
2086 18:02:38.215821 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2087 18:02:38.215874 iDelay=209, Bit 15, Center 96 (-15 ~ 208) 224
2088 18:02:38.215929 ==
2089 18:02:38.215984 Dram Type= 6, Freq= 0, CH_1, rank 1
2090 18:02:38.216038 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2091 18:02:38.216096 ==
2092 18:02:38.216151 DQS Delay:
2093 18:02:38.216222 DQS0 = 0, DQS1 = 0
2094 18:02:38.216290 DQM Delay:
2095 18:02:38.216362 DQM0 = 90, DQM1 = 84
2096 18:02:38.216432 DQ Delay:
2097 18:02:38.216488 DQ0 =96, DQ1 =84, DQ2 =80, DQ3 =88
2098 18:02:38.216541 DQ4 =92, DQ5 =100, DQ6 =96, DQ7 =88
2099 18:02:38.216632 DQ8 =68, DQ9 =72, DQ10 =88, DQ11 =80
2100 18:02:38.216688 DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =96
2101 18:02:38.216743
2102 18:02:38.216796
2103 18:02:38.216884 [DQSOSCAuto] RK1, (LSB)MR18= 0x370d, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 395 ps
2104 18:02:38.216964 CH1 RK1: MR19=606, MR18=370D
2105 18:02:38.217051 CH1_RK1: MR19=0x606, MR18=0x370D, DQSOSC=395, MR23=63, INC=94, DEC=63
2106 18:02:38.217104 [RxdqsGatingPostProcess] freq 800
2107 18:02:38.217162 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2108 18:02:38.217218 Pre-setting of DQS Precalculation
2109 18:02:38.217274 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2110 18:02:38.217328 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2111 18:02:38.217382 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2112 18:02:38.217466
2113 18:02:38.217605
2114 18:02:38.217659 [Calibration Summary] 1600 Mbps
2115 18:02:38.217718 CH 0, Rank 0
2116 18:02:38.217771 SW Impedance : PASS
2117 18:02:38.217826 DUTY Scan : NO K
2118 18:02:38.217880 ZQ Calibration : PASS
2119 18:02:38.217935 Jitter Meter : NO K
2120 18:02:38.217987 CBT Training : PASS
2121 18:02:38.218045 Write leveling : PASS
2122 18:02:38.218101 RX DQS gating : PASS
2123 18:02:38.218156 RX DQ/DQS(RDDQC) : PASS
2124 18:02:38.218209 TX DQ/DQS : PASS
2125 18:02:38.218261 RX DATLAT : PASS
2126 18:02:38.218320 RX DQ/DQS(Engine): PASS
2127 18:02:38.218375 TX OE : NO K
2128 18:02:38.218431 All Pass.
2129 18:02:38.218483
2130 18:02:38.218539 CH 0, Rank 1
2131 18:02:38.218596 SW Impedance : PASS
2132 18:02:38.218651 DUTY Scan : NO K
2133 18:02:38.218704 ZQ Calibration : PASS
2134 18:02:38.218757 Jitter Meter : NO K
2135 18:02:38.218816 CBT Training : PASS
2136 18:02:38.218872 Write leveling : PASS
2137 18:02:38.218927 RX DQS gating : PASS
2138 18:02:38.218981 RX DQ/DQS(RDDQC) : PASS
2139 18:02:38.219038 TX DQ/DQS : PASS
2140 18:02:38.219094 RX DATLAT : PASS
2141 18:02:38.219149 RX DQ/DQS(Engine): PASS
2142 18:02:38.219202 TX OE : NO K
2143 18:02:38.219255 All Pass.
2144 18:02:38.219310
2145 18:02:38.219370 CH 1, Rank 0
2146 18:02:38.219426 SW Impedance : PASS
2147 18:02:38.219478 DUTY Scan : NO K
2148 18:02:38.219532 ZQ Calibration : PASS
2149 18:02:38.219586 Jitter Meter : NO K
2150 18:02:38.219645 CBT Training : PASS
2151 18:02:38.219900 Write leveling : PASS
2152 18:02:38.219963 RX DQS gating : PASS
2153 18:02:38.220020 RX DQ/DQS(RDDQC) : PASS
2154 18:02:38.220076 TX DQ/DQS : PASS
2155 18:02:38.220138 RX DATLAT : PASS
2156 18:02:38.220192 RX DQ/DQS(Engine): PASS
2157 18:02:38.220247 TX OE : NO K
2158 18:02:38.220301 All Pass.
2159 18:02:38.220359
2160 18:02:38.220414 CH 1, Rank 1
2161 18:02:38.220469 SW Impedance : PASS
2162 18:02:38.220523 DUTY Scan : NO K
2163 18:02:38.220621 ZQ Calibration : PASS
2164 18:02:38.220675 Jitter Meter : NO K
2165 18:02:38.220730 CBT Training : PASS
2166 18:02:38.220784 Write leveling : PASS
2167 18:02:38.220842 RX DQS gating : PASS
2168 18:02:38.220899 RX DQ/DQS(RDDQC) : PASS
2169 18:02:38.220951 TX DQ/DQS : PASS
2170 18:02:38.221006 RX DATLAT : PASS
2171 18:02:38.221078 RX DQ/DQS(Engine): PASS
2172 18:02:38.221138 TX OE : NO K
2173 18:02:38.221191 All Pass.
2174 18:02:38.221247
2175 18:02:38.221301 DramC Write-DBI off
2176 18:02:38.221360 PER_BANK_REFRESH: Hybrid Mode
2177 18:02:38.221416 TX_TRACKING: ON
2178 18:02:38.221473 [GetDramInforAfterCalByMRR] Vendor 6.
2179 18:02:38.221527 [GetDramInforAfterCalByMRR] Revision 606.
2180 18:02:38.221586 [GetDramInforAfterCalByMRR] Revision 2 0.
2181 18:02:38.221642 MR0 0x3b3b
2182 18:02:38.221694 MR8 0x5151
2183 18:02:38.221749 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2184 18:02:38.221804
2185 18:02:38.221865 MR0 0x3b3b
2186 18:02:38.221918 MR8 0x5151
2187 18:02:38.221972 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2188 18:02:38.222026
2189 18:02:38.222084 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2190 18:02:38.222141 [FAST_K] Save calibration result to emmc
2191 18:02:38.222194 [FAST_K] Save calibration result to emmc
2192 18:02:38.222249 dram_init: config_dvfs: 1
2193 18:02:38.222303 dramc_set_vcore_voltage set vcore to 662500
2194 18:02:38.222362 Read voltage for 1200, 2
2195 18:02:38.222417 Vio18 = 0
2196 18:02:38.222473 Vcore = 662500
2197 18:02:38.222526 Vdram = 0
2198 18:02:38.222585 Vddq = 0
2199 18:02:38.222640 Vmddr = 0
2200 18:02:38.222695 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2201 18:02:38.222750 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2202 18:02:38.222808 MEM_TYPE=3, freq_sel=15
2203 18:02:38.222864 sv_algorithm_assistance_LP4_1600
2204 18:02:38.222919 ============ PULL DRAM RESETB DOWN ============
2205 18:02:38.222975 ========== PULL DRAM RESETB DOWN end =========
2206 18:02:38.223033 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2207 18:02:38.223089 ===================================
2208 18:02:38.223144 LPDDR4 DRAM CONFIGURATION
2209 18:02:38.223197 ===================================
2210 18:02:38.223251 EX_ROW_EN[0] = 0x0
2211 18:02:38.223309 EX_ROW_EN[1] = 0x0
2212 18:02:38.223364 LP4Y_EN = 0x0
2213 18:02:38.223419 WORK_FSP = 0x0
2214 18:02:38.223473 WL = 0x4
2215 18:02:38.223531 RL = 0x4
2216 18:02:38.223617 BL = 0x2
2217 18:02:38.223670 RPST = 0x0
2218 18:02:38.223723 RD_PRE = 0x0
2219 18:02:38.223781 WR_PRE = 0x1
2220 18:02:38.223836 WR_PST = 0x0
2221 18:02:38.223891 DBI_WR = 0x0
2222 18:02:38.223945 DBI_RD = 0x0
2223 18:02:38.224001 OTF = 0x1
2224 18:02:38.224058 ===================================
2225 18:02:38.224113 ===================================
2226 18:02:38.224168 ANA top config
2227 18:02:38.224220 ===================================
2228 18:02:38.224278 DLL_ASYNC_EN = 0
2229 18:02:38.224333 ALL_SLAVE_EN = 0
2230 18:02:38.224388 NEW_RANK_MODE = 1
2231 18:02:38.224443 DLL_IDLE_MODE = 1
2232 18:02:38.224499 LP45_APHY_COMB_EN = 1
2233 18:02:38.224585 TX_ODT_DIS = 1
2234 18:02:38.224657 NEW_8X_MODE = 1
2235 18:02:38.224711 ===================================
2236 18:02:38.224771 ===================================
2237 18:02:38.224848 data_rate = 2400
2238 18:02:38.224905 CKR = 1
2239 18:02:38.224962 DQ_P2S_RATIO = 8
2240 18:02:38.225019 ===================================
2241 18:02:38.225074 CA_P2S_RATIO = 8
2242 18:02:38.225128 DQ_CA_OPEN = 0
2243 18:02:38.225181 DQ_SEMI_OPEN = 0
2244 18:02:38.225240 CA_SEMI_OPEN = 0
2245 18:02:38.225295 CA_FULL_RATE = 0
2246 18:02:38.225352 DQ_CKDIV4_EN = 0
2247 18:02:38.225404 CA_CKDIV4_EN = 0
2248 18:02:38.225462 CA_PREDIV_EN = 0
2249 18:02:38.225517 PH8_DLY = 17
2250 18:02:38.225572 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2251 18:02:38.225626 DQ_AAMCK_DIV = 4
2252 18:02:38.225678 CA_AAMCK_DIV = 4
2253 18:02:38.225739 CA_ADMCK_DIV = 4
2254 18:02:38.225793 DQ_TRACK_CA_EN = 0
2255 18:02:38.225848 CA_PICK = 1200
2256 18:02:38.225900 CA_MCKIO = 1200
2257 18:02:38.225958 MCKIO_SEMI = 0
2258 18:02:38.226013 PLL_FREQ = 2366
2259 18:02:38.226068 DQ_UI_PI_RATIO = 32
2260 18:02:38.226122 CA_UI_PI_RATIO = 0
2261 18:02:38.226179 ===================================
2262 18:02:38.226235 ===================================
2263 18:02:38.226291 memory_type:LPDDR4
2264 18:02:38.226345 GP_NUM : 10
2265 18:02:38.226398 SRAM_EN : 1
2266 18:02:38.226456 MD32_EN : 0
2267 18:02:38.226511 ===================================
2268 18:02:38.226566 [ANA_INIT] >>>>>>>>>>>>>>
2269 18:02:38.226620 <<<<<< [CONFIGURE PHASE]: ANA_TX
2270 18:02:38.226673 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2271 18:02:38.226733 ===================================
2272 18:02:38.226788 data_rate = 2400,PCW = 0X5b00
2273 18:02:38.226842 ===================================
2274 18:02:38.226895 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2275 18:02:38.226954 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2276 18:02:38.227011 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2277 18:02:38.227067 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2278 18:02:38.227121 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2279 18:02:38.227200 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2280 18:02:38.227258 [ANA_INIT] flow start
2281 18:02:38.227314 [ANA_INIT] PLL >>>>>>>>
2282 18:02:38.227368 [ANA_INIT] PLL <<<<<<<<
2283 18:02:38.227426 [ANA_INIT] MIDPI >>>>>>>>
2284 18:02:38.227483 [ANA_INIT] MIDPI <<<<<<<<
2285 18:02:38.227538 [ANA_INIT] DLL >>>>>>>>
2286 18:02:38.227593 [ANA_INIT] DLL <<<<<<<<
2287 18:02:38.227645 [ANA_INIT] flow end
2288 18:02:38.227704 ============ LP4 DIFF to SE enter ============
2289 18:02:38.227959 ============ LP4 DIFF to SE exit ============
2290 18:02:38.228021 [ANA_INIT] <<<<<<<<<<<<<
2291 18:02:38.228079 [Flow] Enable top DCM control >>>>>
2292 18:02:38.228134 [Flow] Enable top DCM control <<<<<
2293 18:02:38.228191 Enable DLL master slave shuffle
2294 18:02:38.228248 ==============================================================
2295 18:02:38.228305 Gating Mode config
2296 18:02:38.228359 ==============================================================
2297 18:02:38.228416 Config description:
2298 18:02:38.228473 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2299 18:02:38.228529 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2300 18:02:38.228617 SELPH_MODE 0: By rank 1: By Phase
2301 18:02:38.228676 ==============================================================
2302 18:02:38.228733 GAT_TRACK_EN = 1
2303 18:02:38.228788 RX_GATING_MODE = 2
2304 18:02:38.228842 RX_GATING_TRACK_MODE = 2
2305 18:02:38.228894 SELPH_MODE = 1
2306 18:02:38.228954 PICG_EARLY_EN = 1
2307 18:02:38.229009 VALID_LAT_VALUE = 1
2308 18:02:38.229063 ==============================================================
2309 18:02:38.229116 Enter into Gating configuration >>>>
2310 18:02:38.229199 Exit from Gating configuration <<<<
2311 18:02:38.229328 Enter into DVFS_PRE_config >>>>>
2312 18:02:38.229390 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2313 18:02:38.229449 Exit from DVFS_PRE_config <<<<<
2314 18:02:38.229505 Enter into PICG configuration >>>>
2315 18:02:38.229559 Exit from PICG configuration <<<<
2316 18:02:38.229616 [RX_INPUT] configuration >>>>>
2317 18:02:38.229672 [RX_INPUT] configuration <<<<<
2318 18:02:38.229728 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2319 18:02:38.229782 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2320 18:02:38.229835 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2321 18:02:38.229894 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2322 18:02:38.229950 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2323 18:02:38.230006 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2324 18:02:38.230059 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2325 18:02:38.230118 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2326 18:02:38.230174 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2327 18:02:38.230231 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2328 18:02:38.230283 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2329 18:02:38.230341 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2330 18:02:38.230397 ===================================
2331 18:02:38.230453 LPDDR4 DRAM CONFIGURATION
2332 18:02:38.230506 ===================================
2333 18:02:38.230563 EX_ROW_EN[0] = 0x0
2334 18:02:38.230619 EX_ROW_EN[1] = 0x0
2335 18:02:38.230673 LP4Y_EN = 0x0
2336 18:02:38.230727 WORK_FSP = 0x0
2337 18:02:38.230779 WL = 0x4
2338 18:02:38.230837 RL = 0x4
2339 18:02:38.230892 BL = 0x2
2340 18:02:38.230947 RPST = 0x0
2341 18:02:38.231000 RD_PRE = 0x0
2342 18:02:38.231052 WR_PRE = 0x1
2343 18:02:38.231113 WR_PST = 0x0
2344 18:02:38.231168 DBI_WR = 0x0
2345 18:02:38.231221 DBI_RD = 0x0
2346 18:02:38.231273 OTF = 0x1
2347 18:02:38.231332 ===================================
2348 18:02:38.231387 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2349 18:02:38.231443 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2350 18:02:38.231497 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2351 18:02:38.231555 ===================================
2352 18:02:38.231611 LPDDR4 DRAM CONFIGURATION
2353 18:02:38.231666 ===================================
2354 18:02:38.231720 EX_ROW_EN[0] = 0x10
2355 18:02:38.231773 EX_ROW_EN[1] = 0x0
2356 18:02:38.231833 LP4Y_EN = 0x0
2357 18:02:38.231888 WORK_FSP = 0x0
2358 18:02:38.231942 WL = 0x4
2359 18:02:38.231994 RL = 0x4
2360 18:02:38.232051 BL = 0x2
2361 18:02:38.232106 RPST = 0x0
2362 18:02:38.232159 RD_PRE = 0x0
2363 18:02:38.232211 WR_PRE = 0x1
2364 18:02:38.232267 WR_PST = 0x0
2365 18:02:38.232321 DBI_WR = 0x0
2366 18:02:38.232374 DBI_RD = 0x0
2367 18:02:38.232427 OTF = 0x1
2368 18:02:38.232478 ===================================
2369 18:02:38.232562 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2370 18:02:38.232630 ==
2371 18:02:38.232683 Dram Type= 6, Freq= 0, CH_0, rank 0
2372 18:02:38.232734 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2373 18:02:38.232794 ==
2374 18:02:38.232848 [Duty_Offset_Calibration]
2375 18:02:38.232900 B0:2 B1:0 CA:1
2376 18:02:38.232950
2377 18:02:38.233007 [DutyScan_Calibration_Flow] k_type=0
2378 18:02:38.233074
2379 18:02:38.233132 ==CLK 0==
2380 18:02:38.233184 Final CLK duty delay cell = -4
2381 18:02:38.233242 [-4] MAX Duty = 5031%(X100), DQS PI = 26
2382 18:02:38.233298 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2383 18:02:38.233351 [-4] AVG Duty = 4953%(X100)
2384 18:02:38.233404
2385 18:02:38.233461 CH0 CLK Duty spec in!! Max-Min= 156%
2386 18:02:38.233517 [DutyScan_Calibration_Flow] ====Done====
2387 18:02:38.233570
2388 18:02:38.233622 [DutyScan_Calibration_Flow] k_type=1
2389 18:02:38.233678
2390 18:02:38.233733 ==DQS 0 ==
2391 18:02:38.233784 Final DQS duty delay cell = 0
2392 18:02:38.233839 [0] MAX Duty = 5187%(X100), DQS PI = 30
2393 18:02:38.233890 [0] MIN Duty = 4938%(X100), DQS PI = 0
2394 18:02:38.233948 [0] AVG Duty = 5062%(X100)
2395 18:02:38.234002
2396 18:02:38.234057 ==DQS 1 ==
2397 18:02:38.234107 Final DQS duty delay cell = -4
2398 18:02:38.234165 [-4] MAX Duty = 5124%(X100), DQS PI = 32
2399 18:02:38.234219 [-4] MIN Duty = 4876%(X100), DQS PI = 8
2400 18:02:38.234273 [-4] AVG Duty = 5000%(X100)
2401 18:02:38.234325
2402 18:02:38.234380 CH0 DQS 0 Duty spec in!! Max-Min= 249%
2403 18:02:38.234435
2404 18:02:38.234490 CH0 DQS 1 Duty spec in!! Max-Min= 248%
2405 18:02:38.234543 [DutyScan_Calibration_Flow] ====Done====
2406 18:02:38.234594
2407 18:02:38.234652 [DutyScan_Calibration_Flow] k_type=3
2408 18:02:38.234706
2409 18:02:38.234758 ==DQM 0 ==
2410 18:02:38.234811 Final DQM duty delay cell = 0
2411 18:02:38.235063 [0] MAX Duty = 5062%(X100), DQS PI = 24
2412 18:02:38.235130 [0] MIN Duty = 4813%(X100), DQS PI = 0
2413 18:02:38.235204 [0] AVG Duty = 4937%(X100)
2414 18:02:38.235271
2415 18:02:38.235328 ==DQM 1 ==
2416 18:02:38.235383 Final DQM duty delay cell = 0
2417 18:02:38.235437 [0] MAX Duty = 5187%(X100), DQS PI = 48
2418 18:02:38.235490 [0] MIN Duty = 5000%(X100), DQS PI = 12
2419 18:02:38.235541 [0] AVG Duty = 5093%(X100)
2420 18:02:38.235599
2421 18:02:38.235653 CH0 DQM 0 Duty spec in!! Max-Min= 249%
2422 18:02:38.235708
2423 18:02:38.235758 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2424 18:02:38.235835 [DutyScan_Calibration_Flow] ====Done====
2425 18:02:38.235907
2426 18:02:38.235959 [DutyScan_Calibration_Flow] k_type=2
2427 18:02:38.236011
2428 18:02:38.236067 ==DQ 0 ==
2429 18:02:38.236122 Final DQ duty delay cell = 0
2430 18:02:38.236176 [0] MAX Duty = 5156%(X100), DQS PI = 34
2431 18:02:38.236229 [0] MIN Duty = 5000%(X100), DQS PI = 0
2432 18:02:38.236280 [0] AVG Duty = 5078%(X100)
2433 18:02:38.236337
2434 18:02:38.236391 ==DQ 1 ==
2435 18:02:38.236445 Final DQ duty delay cell = 4
2436 18:02:38.236498 [4] MAX Duty = 5093%(X100), DQS PI = 4
2437 18:02:38.236580 [4] MIN Duty = 5000%(X100), DQS PI = 18
2438 18:02:38.236652 [4] AVG Duty = 5046%(X100)
2439 18:02:38.236705
2440 18:02:38.236757 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2441 18:02:38.236808
2442 18:02:38.236866 CH0 DQ 1 Duty spec in!! Max-Min= 93%
2443 18:02:38.236940 [DutyScan_Calibration_Flow] ====Done====
2444 18:02:38.236996 ==
2445 18:02:38.237048 Dram Type= 6, Freq= 0, CH_1, rank 0
2446 18:02:38.237107 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2447 18:02:38.237162 ==
2448 18:02:38.237217 [Duty_Offset_Calibration]
2449 18:02:38.237268 B0:0 B1:-1 CA:2
2450 18:02:38.237325
2451 18:02:38.237379 [DutyScan_Calibration_Flow] k_type=0
2452 18:02:38.237433
2453 18:02:38.237485 ==CLK 0==
2454 18:02:38.237543 Final CLK duty delay cell = 0
2455 18:02:38.237599 [0] MAX Duty = 5156%(X100), DQS PI = 16
2456 18:02:38.237653 [0] MIN Duty = 4938%(X100), DQS PI = 44
2457 18:02:38.237705 [0] AVG Duty = 5047%(X100)
2458 18:02:38.237755
2459 18:02:38.237808 CH1 CLK Duty spec in!! Max-Min= 218%
2460 18:02:38.237867 [DutyScan_Calibration_Flow] ====Done====
2461 18:02:38.237925
2462 18:02:38.237977 [DutyScan_Calibration_Flow] k_type=1
2463 18:02:38.238031
2464 18:02:38.238082 ==DQS 0 ==
2465 18:02:38.238138 Final DQS duty delay cell = 0
2466 18:02:38.238191 [0] MAX Duty = 5093%(X100), DQS PI = 26
2467 18:02:38.238244 [0] MIN Duty = 4969%(X100), DQS PI = 0
2468 18:02:38.238298 [0] AVG Duty = 5031%(X100)
2469 18:02:38.238349
2470 18:02:38.238399 ==DQS 1 ==
2471 18:02:38.238457 Final DQS duty delay cell = 0
2472 18:02:38.238512 [0] MAX Duty = 5156%(X100), DQS PI = 0
2473 18:02:38.238566 [0] MIN Duty = 4813%(X100), DQS PI = 36
2474 18:02:38.238617 [0] AVG Duty = 4984%(X100)
2475 18:02:38.238668
2476 18:02:38.238719 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2477 18:02:38.238776
2478 18:02:38.238829 CH1 DQS 1 Duty spec in!! Max-Min= 343%
2479 18:02:38.238882 [DutyScan_Calibration_Flow] ====Done====
2480 18:02:38.238932
2481 18:02:38.238983 [DutyScan_Calibration_Flow] k_type=3
2482 18:02:38.239033
2483 18:02:38.239090 ==DQM 0 ==
2484 18:02:38.239144 Final DQM duty delay cell = 4
2485 18:02:38.239196 [4] MAX Duty = 5093%(X100), DQS PI = 20
2486 18:02:38.239249 [4] MIN Duty = 4938%(X100), DQS PI = 30
2487 18:02:38.239300 [4] AVG Duty = 5015%(X100)
2488 18:02:38.239351
2489 18:02:38.239411 ==DQM 1 ==
2490 18:02:38.239491 Final DQM duty delay cell = 0
2491 18:02:38.239575 [0] MAX Duty = 5249%(X100), DQS PI = 0
2492 18:02:38.239650 [0] MIN Duty = 4875%(X100), DQS PI = 36
2493 18:02:38.239704 [0] AVG Duty = 5062%(X100)
2494 18:02:38.239757
2495 18:02:38.239808 CH1 DQM 0 Duty spec in!! Max-Min= 155%
2496 18:02:38.239865
2497 18:02:38.239918 CH1 DQM 1 Duty spec in!! Max-Min= 374%
2498 18:02:38.239972 [DutyScan_Calibration_Flow] ====Done====
2499 18:02:38.240024
2500 18:02:38.240081 [DutyScan_Calibration_Flow] k_type=2
2501 18:02:38.240135
2502 18:02:38.240188 ==DQ 0 ==
2503 18:02:38.240240 Final DQ duty delay cell = 0
2504 18:02:38.240291 [0] MAX Duty = 5031%(X100), DQS PI = 18
2505 18:02:38.240349 [0] MIN Duty = 4938%(X100), DQS PI = 28
2506 18:02:38.240405 [0] AVG Duty = 4984%(X100)
2507 18:02:38.240456
2508 18:02:38.240508 ==DQ 1 ==
2509 18:02:38.240599 Final DQ duty delay cell = 0
2510 18:02:38.240671 [0] MAX Duty = 5031%(X100), DQS PI = 2
2511 18:02:38.240724 [0] MIN Duty = 4813%(X100), DQS PI = 34
2512 18:02:38.240776 [0] AVG Duty = 4922%(X100)
2513 18:02:38.240832
2514 18:02:38.240887 CH1 DQ 0 Duty spec in!! Max-Min= 93%
2515 18:02:38.240940
2516 18:02:38.241006 CH1 DQ 1 Duty spec in!! Max-Min= 218%
2517 18:02:38.241067 [DutyScan_Calibration_Flow] ====Done====
2518 18:02:38.241123 nWR fixed to 30
2519 18:02:38.241177 [ModeRegInit_LP4] CH0 RK0
2520 18:02:38.241230 [ModeRegInit_LP4] CH0 RK1
2521 18:02:38.241281 [ModeRegInit_LP4] CH1 RK0
2522 18:02:38.241338 [ModeRegInit_LP4] CH1 RK1
2523 18:02:38.241393 match AC timing 7
2524 18:02:38.241446 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2525 18:02:38.241500 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2526 18:02:38.241551 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2527 18:02:38.241611 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2528 18:02:38.241665 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2529 18:02:38.241718 ==
2530 18:02:38.241769 Dram Type= 6, Freq= 0, CH_0, rank 0
2531 18:02:38.241828 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2532 18:02:38.241884 ==
2533 18:02:38.241938 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2534 18:02:38.241990 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2535 18:02:38.242048 [CA 0] Center 38 (7~69) winsize 63
2536 18:02:38.242103 [CA 1] Center 38 (8~69) winsize 62
2537 18:02:38.242157 [CA 2] Center 35 (5~66) winsize 62
2538 18:02:38.242210 [CA 3] Center 35 (4~66) winsize 63
2539 18:02:38.242261 [CA 4] Center 34 (4~65) winsize 62
2540 18:02:38.242322 [CA 5] Center 33 (3~63) winsize 61
2541 18:02:38.242375
2542 18:02:38.242428 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2543 18:02:38.242479
2544 18:02:38.242537 [CATrainingPosCal] consider 1 rank data
2545 18:02:38.242592 u2DelayCellTimex100 = 270/100 ps
2546 18:02:38.242646 CA0 delay=38 (7~69),Diff = 5 PI (24 cell)
2547 18:02:38.242699 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2548 18:02:38.242756 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2549 18:02:38.242810 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2550 18:02:38.242864 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2551 18:02:38.242916 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2552 18:02:38.242967
2553 18:02:38.243024 CA PerBit enable=1, Macro0, CA PI delay=33
2554 18:02:38.243079
2555 18:02:38.243133 [CBTSetCACLKResult] CA Dly = 33
2556 18:02:38.243183 CS Dly: 6 (0~37)
2557 18:02:38.243239 ==
2558 18:02:38.243294 Dram Type= 6, Freq= 0, CH_0, rank 1
2559 18:02:38.243562 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2560 18:02:38.243638 ==
2561 18:02:38.243691 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2562 18:02:38.243753 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2563 18:02:38.243805 [CA 0] Center 39 (8~70) winsize 63
2564 18:02:38.243862 [CA 1] Center 38 (8~69) winsize 62
2565 18:02:38.243913 [CA 2] Center 35 (5~66) winsize 62
2566 18:02:38.243990 [CA 3] Center 35 (5~66) winsize 62
2567 18:02:38.244059 [CA 4] Center 34 (4~65) winsize 62
2568 18:02:38.244112 [CA 5] Center 34 (4~64) winsize 61
2569 18:02:38.244163
2570 18:02:38.244220 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2571 18:02:38.244275
2572 18:02:38.244329 [CATrainingPosCal] consider 2 rank data
2573 18:02:38.244381 u2DelayCellTimex100 = 270/100 ps
2574 18:02:38.244432 CA0 delay=38 (8~69),Diff = 5 PI (24 cell)
2575 18:02:38.244492 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2576 18:02:38.244577 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2577 18:02:38.244683 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2578 18:02:38.244766 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2579 18:02:38.244839 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
2580 18:02:38.244896
2581 18:02:38.244952 CA PerBit enable=1, Macro0, CA PI delay=33
2582 18:02:38.245011
2583 18:02:38.245067 [CBTSetCACLKResult] CA Dly = 33
2584 18:02:38.245121 CS Dly: 7 (0~39)
2585 18:02:38.245174
2586 18:02:38.245226 ----->DramcWriteLeveling(PI) begin...
2587 18:02:38.245280 ==
2588 18:02:38.245339 Dram Type= 6, Freq= 0, CH_0, rank 0
2589 18:02:38.245392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2590 18:02:38.245445 ==
2591 18:02:38.245496 Write leveling (Byte 0): 37 => 37
2592 18:02:38.245548 Write leveling (Byte 1): 30 => 30
2593 18:02:38.245606 DramcWriteLeveling(PI) end<-----
2594 18:02:38.245659
2595 18:02:38.245711 ==
2596 18:02:38.245762 Dram Type= 6, Freq= 0, CH_0, rank 0
2597 18:02:38.245813 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2598 18:02:38.245865 ==
2599 18:02:38.245923 [Gating] SW mode calibration
2600 18:02:38.245976 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2601 18:02:38.246029 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2602 18:02:38.246081 0 15 0 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
2603 18:02:38.246133 0 15 4 | B1->B0 | 2b2b 3434 | 1 1 | (1 1) (1 1)
2604 18:02:38.246191 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2605 18:02:38.246244 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2606 18:02:38.246296 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2607 18:02:38.246348 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2608 18:02:38.246400 0 15 24 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
2609 18:02:38.246457 0 15 28 | B1->B0 | 3434 2323 | 1 0 | (1 0) (1 0)
2610 18:02:38.246510 1 0 0 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (1 0)
2611 18:02:38.246562 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2612 18:02:38.246614 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2613 18:02:38.246666 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2614 18:02:38.246718 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2615 18:02:38.246777 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2616 18:02:38.246830 1 0 24 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
2617 18:02:38.246881 1 0 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
2618 18:02:38.246966 1 1 0 | B1->B0 | 2f2f 4646 | 0 0 | (1 1) (0 0)
2619 18:02:38.247018 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2620 18:02:38.247075 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2621 18:02:38.247127 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2622 18:02:38.247179 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2623 18:02:38.247230 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2624 18:02:38.247281 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2625 18:02:38.247359 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2626 18:02:38.247442 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2627 18:02:38.247524 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2628 18:02:38.247607 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2629 18:02:38.247690 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2630 18:02:38.247772 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2631 18:02:38.247853 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2632 18:02:38.247938 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2633 18:02:38.248020 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2634 18:02:38.248101 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2635 18:02:38.248185 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2636 18:02:38.248268 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2637 18:02:38.248349 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2638 18:02:38.248430 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2639 18:02:38.248515 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2640 18:02:38.248635 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2641 18:02:38.248718 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2642 18:02:38.248804 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2643 18:02:38.248888 Total UI for P1: 0, mck2ui 16
2644 18:02:38.248971 best dqsien dly found for B0: ( 1, 3, 26)
2645 18:02:38.249053 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2646 18:02:38.249138 Total UI for P1: 0, mck2ui 16
2647 18:02:38.249220 best dqsien dly found for B1: ( 1, 3, 30)
2648 18:02:38.249278 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2649 18:02:38.249331 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2650 18:02:38.249382
2651 18:02:38.249439 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2652 18:02:38.249493 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2653 18:02:38.249560 [Gating] SW calibration Done
2654 18:02:38.249642 ==
2655 18:02:38.249739 Dram Type= 6, Freq= 0, CH_0, rank 0
2656 18:02:38.249839 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2657 18:02:38.249921 ==
2658 18:02:38.250002 RX Vref Scan: 0
2659 18:02:38.250086
2660 18:02:38.250169 RX Vref 0 -> 0, step: 1
2661 18:02:38.250249
2662 18:02:38.250362 RX Delay -40 -> 252, step: 8
2663 18:02:38.250444 iDelay=208, Bit 0, Center 119 (48 ~ 191) 144
2664 18:02:38.250525 iDelay=208, Bit 1, Center 123 (56 ~ 191) 136
2665 18:02:38.250813 iDelay=208, Bit 2, Center 119 (48 ~ 191) 144
2666 18:02:38.250874 iDelay=208, Bit 3, Center 119 (48 ~ 191) 144
2667 18:02:38.250927 iDelay=208, Bit 4, Center 127 (56 ~ 199) 144
2668 18:02:38.250979 iDelay=208, Bit 5, Center 115 (48 ~ 183) 136
2669 18:02:38.251038 iDelay=208, Bit 6, Center 131 (56 ~ 207) 152
2670 18:02:38.251091 iDelay=208, Bit 7, Center 127 (56 ~ 199) 144
2671 18:02:38.251143 iDelay=208, Bit 8, Center 103 (40 ~ 167) 128
2672 18:02:38.251195 iDelay=208, Bit 9, Center 99 (32 ~ 167) 136
2673 18:02:38.251251 iDelay=208, Bit 10, Center 107 (40 ~ 175) 136
2674 18:02:38.251306 iDelay=208, Bit 11, Center 107 (40 ~ 175) 136
2675 18:02:38.251357 iDelay=208, Bit 12, Center 115 (48 ~ 183) 136
2676 18:02:38.251409 iDelay=208, Bit 13, Center 111 (48 ~ 175) 128
2677 18:02:38.251460 iDelay=208, Bit 14, Center 123 (56 ~ 191) 136
2678 18:02:38.251518 iDelay=208, Bit 15, Center 115 (48 ~ 183) 136
2679 18:02:38.251569 ==
2680 18:02:38.251622 Dram Type= 6, Freq= 0, CH_0, rank 0
2681 18:02:38.251673 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2682 18:02:38.251743 ==
2683 18:02:38.251854 DQS Delay:
2684 18:02:38.251909 DQS0 = 0, DQS1 = 0
2685 18:02:38.251961 DQM Delay:
2686 18:02:38.252017 DQM0 = 122, DQM1 = 110
2687 18:02:38.252071 DQ Delay:
2688 18:02:38.252123 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2689 18:02:38.252177 DQ4 =127, DQ5 =115, DQ6 =131, DQ7 =127
2690 18:02:38.252237 DQ8 =103, DQ9 =99, DQ10 =107, DQ11 =107
2691 18:02:38.252295 DQ12 =115, DQ13 =111, DQ14 =123, DQ15 =115
2692 18:02:38.252346
2693 18:02:38.252397
2694 18:02:38.252448 ==
2695 18:02:38.252499 Dram Type= 6, Freq= 0, CH_0, rank 0
2696 18:02:38.252610 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2697 18:02:38.252664 ==
2698 18:02:38.252715
2699 18:02:38.252766
2700 18:02:38.252823 TX Vref Scan disable
2701 18:02:38.252875 == TX Byte 0 ==
2702 18:02:38.252926 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
2703 18:02:38.252979 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
2704 18:02:38.253035 == TX Byte 1 ==
2705 18:02:38.253088 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2706 18:02:38.253140 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2707 18:02:38.253191 ==
2708 18:02:38.253242 Dram Type= 6, Freq= 0, CH_0, rank 0
2709 18:02:38.253299 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2710 18:02:38.253352 ==
2711 18:02:38.253402 TX Vref=22, minBit 6, minWin=24, winSum=415
2712 18:02:38.253454 TX Vref=24, minBit 5, minWin=24, winSum=420
2713 18:02:38.253557 TX Vref=26, minBit 0, minWin=26, winSum=427
2714 18:02:38.253623 TX Vref=28, minBit 5, minWin=25, winSum=426
2715 18:02:38.253676 TX Vref=30, minBit 5, minWin=26, winSum=435
2716 18:02:38.253727 TX Vref=32, minBit 3, minWin=26, winSum=432
2717 18:02:38.253783 [TxChooseVref] Worse bit 5, Min win 26, Win sum 435, Final Vref 30
2718 18:02:38.253837
2719 18:02:38.253888 Final TX Range 1 Vref 30
2720 18:02:38.253939
2721 18:02:38.253990 ==
2722 18:02:38.254042 Dram Type= 6, Freq= 0, CH_0, rank 0
2723 18:02:38.254101 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2724 18:02:38.254154 ==
2725 18:02:38.254246
2726 18:02:38.254297
2727 18:02:38.254353 TX Vref Scan disable
2728 18:02:38.254404 == TX Byte 0 ==
2729 18:02:38.254455 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
2730 18:02:38.254507 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
2731 18:02:38.254565 == TX Byte 1 ==
2732 18:02:38.254647 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2733 18:02:38.254728 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2734 18:02:38.254809
2735 18:02:38.254892 [DATLAT]
2736 18:02:38.254973 Freq=1200, CH0 RK0
2737 18:02:38.255053
2738 18:02:38.255137 DATLAT Default: 0xd
2739 18:02:38.255217 0, 0xFFFF, sum = 0
2740 18:02:38.255300 1, 0xFFFF, sum = 0
2741 18:02:38.255387 2, 0xFFFF, sum = 0
2742 18:02:38.255469 3, 0xFFFF, sum = 0
2743 18:02:38.255551 4, 0xFFFF, sum = 0
2744 18:02:38.255635 5, 0xFFFF, sum = 0
2745 18:02:38.255719 6, 0xFFFF, sum = 0
2746 18:02:38.255802 7, 0xFFFF, sum = 0
2747 18:02:38.255884 8, 0xFFFF, sum = 0
2748 18:02:38.255988 9, 0xFFFF, sum = 0
2749 18:02:38.256099 10, 0xFFFF, sum = 0
2750 18:02:38.256155 11, 0xFFFF, sum = 0
2751 18:02:38.256209 12, 0x0, sum = 1
2752 18:02:38.256296 13, 0x0, sum = 2
2753 18:02:38.256381 14, 0x0, sum = 3
2754 18:02:38.256468 15, 0x0, sum = 4
2755 18:02:38.256561 best_step = 13
2756 18:02:38.256617
2757 18:02:38.256670 ==
2758 18:02:38.256728 Dram Type= 6, Freq= 0, CH_0, rank 0
2759 18:02:38.256782 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2760 18:02:38.256836 ==
2761 18:02:38.256888 RX Vref Scan: 1
2762 18:02:38.256940
2763 18:02:38.256993 Set Vref Range= 32 -> 127
2764 18:02:38.257051
2765 18:02:38.257104 RX Vref 32 -> 127, step: 1
2766 18:02:38.257155
2767 18:02:38.257208 RX Delay -13 -> 252, step: 4
2768 18:02:38.257264
2769 18:02:38.257319 Set Vref, RX VrefLevel [Byte0]: 32
2770 18:02:38.257371 [Byte1]: 32
2771 18:02:38.257423
2772 18:02:38.257476 Set Vref, RX VrefLevel [Byte0]: 33
2773 18:02:38.257537 [Byte1]: 33
2774 18:02:38.257590
2775 18:02:38.257642 Set Vref, RX VrefLevel [Byte0]: 34
2776 18:02:38.257694 [Byte1]: 34
2777 18:02:38.257747
2778 18:02:38.257805 Set Vref, RX VrefLevel [Byte0]: 35
2779 18:02:38.257857 [Byte1]: 35
2780 18:02:38.257910
2781 18:02:38.257962 Set Vref, RX VrefLevel [Byte0]: 36
2782 18:02:38.258015 [Byte1]: 36
2783 18:02:38.258071
2784 18:02:38.258125 Set Vref, RX VrefLevel [Byte0]: 37
2785 18:02:38.258178 [Byte1]: 37
2786 18:02:38.258230
2787 18:02:38.258282 Set Vref, RX VrefLevel [Byte0]: 38
2788 18:02:38.258342 [Byte1]: 38
2789 18:02:38.258396
2790 18:02:38.258448 Set Vref, RX VrefLevel [Byte0]: 39
2791 18:02:38.258501 [Byte1]: 39
2792 18:02:38.258553
2793 18:02:38.258614 Set Vref, RX VrefLevel [Byte0]: 40
2794 18:02:38.258698 [Byte1]: 40
2795 18:02:38.258780
2796 18:02:38.258862 Set Vref, RX VrefLevel [Byte0]: 41
2797 18:02:38.258948 [Byte1]: 41
2798 18:02:38.259030
2799 18:02:38.259113 Set Vref, RX VrefLevel [Byte0]: 42
2800 18:02:38.259199 [Byte1]: 42
2801 18:02:38.259281
2802 18:02:38.259363 Set Vref, RX VrefLevel [Byte0]: 43
2803 18:02:38.259449 [Byte1]: 43
2804 18:02:38.259532
2805 18:02:38.259614 Set Vref, RX VrefLevel [Byte0]: 44
2806 18:02:38.259700 [Byte1]: 44
2807 18:02:38.259782
2808 18:02:38.259864 Set Vref, RX VrefLevel [Byte0]: 45
2809 18:02:38.259950 [Byte1]: 45
2810 18:02:38.260033
2811 18:02:38.260115 Set Vref, RX VrefLevel [Byte0]: 46
2812 18:02:38.260208 [Byte1]: 46
2813 18:02:38.260293
2814 18:02:38.260376 Set Vref, RX VrefLevel [Byte0]: 47
2815 18:02:38.260461 [Byte1]: 47
2816 18:02:38.260544
2817 18:02:38.260632 Set Vref, RX VrefLevel [Byte0]: 48
2818 18:02:38.260719 [Byte1]: 48
2819 18:02:38.260805
2820 18:02:38.260888 Set Vref, RX VrefLevel [Byte0]: 49
2821 18:02:38.261169 [Byte1]: 49
2822 18:02:38.261259
2823 18:02:38.261344 Set Vref, RX VrefLevel [Byte0]: 50
2824 18:02:38.261430 [Byte1]: 50
2825 18:02:38.261513
2826 18:02:38.261596 Set Vref, RX VrefLevel [Byte0]: 51
2827 18:02:38.261682 [Byte1]: 51
2828 18:02:38.261765
2829 18:02:38.261847 Set Vref, RX VrefLevel [Byte0]: 52
2830 18:02:38.261932 [Byte1]: 52
2831 18:02:38.262014
2832 18:02:38.262097 Set Vref, RX VrefLevel [Byte0]: 53
2833 18:02:38.262180 [Byte1]: 53
2834 18:02:38.262236
2835 18:02:38.262289 Set Vref, RX VrefLevel [Byte0]: 54
2836 18:02:38.262342 [Byte1]: 54
2837 18:02:38.262394
2838 18:02:38.262451 Set Vref, RX VrefLevel [Byte0]: 55
2839 18:02:38.262506 [Byte1]: 55
2840 18:02:38.262558
2841 18:02:38.262611 Set Vref, RX VrefLevel [Byte0]: 56
2842 18:02:38.262663 [Byte1]: 56
2843 18:02:38.262746
2844 18:02:38.262829 Set Vref, RX VrefLevel [Byte0]: 57
2845 18:02:38.262912 [Byte1]: 57
2846 18:02:38.262997
2847 18:02:38.263080 Set Vref, RX VrefLevel [Byte0]: 58
2848 18:02:38.263163 [Byte1]: 58
2849 18:02:38.263249
2850 18:02:38.263331 Set Vref, RX VrefLevel [Byte0]: 59
2851 18:02:38.263414 [Byte1]: 59
2852 18:02:38.263500
2853 18:02:38.263583 Set Vref, RX VrefLevel [Byte0]: 60
2854 18:02:38.263665 [Byte1]: 60
2855 18:02:38.263751
2856 18:02:38.263833 Set Vref, RX VrefLevel [Byte0]: 61
2857 18:02:38.263916 [Byte1]: 61
2858 18:02:38.263997
2859 18:02:38.264083 Set Vref, RX VrefLevel [Byte0]: 62
2860 18:02:38.264165 [Byte1]: 62
2861 18:02:38.264250
2862 18:02:38.264333 Set Vref, RX VrefLevel [Byte0]: 63
2863 18:02:38.264415 [Byte1]: 63
2864 18:02:38.264499
2865 18:02:38.264594 Set Vref, RX VrefLevel [Byte0]: 64
2866 18:02:38.264651 [Byte1]: 64
2867 18:02:38.264704
2868 18:02:38.264764 Set Vref, RX VrefLevel [Byte0]: 65
2869 18:02:38.264819 [Byte1]: 65
2870 18:02:38.264871
2871 18:02:38.264923 Set Vref, RX VrefLevel [Byte0]: 66
2872 18:02:38.264980 [Byte1]: 66
2873 18:02:38.265035
2874 18:02:38.265087 Set Vref, RX VrefLevel [Byte0]: 67
2875 18:02:38.265140 [Byte1]: 67
2876 18:02:38.265192
2877 18:02:38.265252 Set Vref, RX VrefLevel [Byte0]: 68
2878 18:02:38.265305 [Byte1]: 68
2879 18:02:38.265358
2880 18:02:38.265409 Set Vref, RX VrefLevel [Byte0]: 69
2881 18:02:38.265465 [Byte1]: 69
2882 18:02:38.265520
2883 18:02:38.265573 Set Vref, RX VrefLevel [Byte0]: 70
2884 18:02:38.265626 [Byte1]: 70
2885 18:02:38.265678
2886 18:02:38.265734 Final RX Vref Byte 0 = 57 to rank0
2887 18:02:38.265789 Final RX Vref Byte 1 = 49 to rank0
2888 18:02:38.265842 Final RX Vref Byte 0 = 57 to rank1
2889 18:02:38.265895 Final RX Vref Byte 1 = 49 to rank1==
2890 18:02:38.265947 Dram Type= 6, Freq= 0, CH_0, rank 0
2891 18:02:38.266032 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2892 18:02:38.266115 ==
2893 18:02:38.266197 DQS Delay:
2894 18:02:38.266284 DQS0 = 0, DQS1 = 0
2895 18:02:38.266367 DQM Delay:
2896 18:02:38.266449 DQM0 = 122, DQM1 = 109
2897 18:02:38.266532 DQ Delay:
2898 18:02:38.266617 DQ0 =122, DQ1 =122, DQ2 =118, DQ3 =118
2899 18:02:38.266699 DQ4 =126, DQ5 =116, DQ6 =130, DQ7 =128
2900 18:02:38.266782 DQ8 =100, DQ9 =94, DQ10 =110, DQ11 =106
2901 18:02:38.266868 DQ12 =116, DQ13 =110, DQ14 =122, DQ15 =116
2902 18:02:38.266950
2903 18:02:38.267031
2904 18:02:38.267118 [DQSOSCAuto] RK0, (LSB)MR18= 0xb08, (MSB)MR19= 0x404, tDQSOscB0 = 406 ps tDQSOscB1 = 405 ps
2905 18:02:38.267202 CH0 RK0: MR19=404, MR18=B08
2906 18:02:38.267286 CH0_RK0: MR19=0x404, MR18=0xB08, DQSOSC=405, MR23=63, INC=39, DEC=26
2907 18:02:38.267368
2908 18:02:38.267454 ----->DramcWriteLeveling(PI) begin...
2909 18:02:38.267538 ==
2910 18:02:38.267621 Dram Type= 6, Freq= 0, CH_0, rank 1
2911 18:02:38.267708 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2912 18:02:38.267790 ==
2913 18:02:38.267873 Write leveling (Byte 0): 36 => 36
2914 18:02:38.267959 Write leveling (Byte 1): 31 => 31
2915 18:02:38.268042 DramcWriteLeveling(PI) end<-----
2916 18:02:38.268124
2917 18:02:38.268209 ==
2918 18:02:38.268292 Dram Type= 6, Freq= 0, CH_0, rank 1
2919 18:02:38.268375 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2920 18:02:38.268461 ==
2921 18:02:38.268543 [Gating] SW mode calibration
2922 18:02:38.268634 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2923 18:02:38.268721 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2924 18:02:38.268805 0 15 0 | B1->B0 | 3030 3434 | 1 0 | (0 0) (0 0)
2925 18:02:38.268897 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2926 18:02:38.268982 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2927 18:02:38.269069 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2928 18:02:38.269152 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2929 18:02:38.269236 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2930 18:02:38.269321 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2931 18:02:38.269404 0 15 28 | B1->B0 | 3030 2e2e | 1 1 | (1 1) (1 0)
2932 18:02:38.269487 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2933 18:02:38.269575 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2934 18:02:38.269658 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2935 18:02:38.269742 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2936 18:02:38.269827 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2937 18:02:38.269911 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2938 18:02:38.269994 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2939 18:02:38.270077 1 0 28 | B1->B0 | 3636 3c3c | 0 1 | (0 0) (0 0)
2940 18:02:38.270163 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2941 18:02:38.270246 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2942 18:02:38.270332 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2943 18:02:38.270420 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2944 18:02:38.270503 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2945 18:02:38.270586 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2946 18:02:38.270672 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2947 18:02:38.270755 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
2948 18:02:38.270838 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2949 18:02:38.271116 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2950 18:02:38.271206 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2951 18:02:38.271270 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2952 18:02:38.271325 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2953 18:02:38.271378 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2954 18:02:38.271431 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2955 18:02:38.271489 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2956 18:02:38.271544 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2957 18:02:38.271596 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2958 18:02:38.271649 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2959 18:02:38.271702 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2960 18:02:38.271787 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2961 18:02:38.271870 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2962 18:02:38.271956 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2963 18:02:38.272040 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2964 18:02:38.272129 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
2965 18:02:38.272191 Total UI for P1: 0, mck2ui 16
2966 18:02:38.272247 best dqsien dly found for B1: ( 1, 3, 28)
2967 18:02:38.272302 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2968 18:02:38.272374 Total UI for P1: 0, mck2ui 16
2969 18:02:38.272464 best dqsien dly found for B0: ( 1, 3, 30)
2970 18:02:38.272562 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2971 18:02:38.272621 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2972 18:02:38.272674
2973 18:02:38.272735 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2974 18:02:38.272789 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2975 18:02:38.272841 [Gating] SW calibration Done
2976 18:02:38.272895 ==
2977 18:02:38.272955 Dram Type= 6, Freq= 0, CH_0, rank 1
2978 18:02:38.273027 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2979 18:02:38.273083 ==
2980 18:02:38.273136 RX Vref Scan: 0
2981 18:02:38.273189
2982 18:02:38.273249 RX Vref 0 -> 0, step: 1
2983 18:02:38.273302
2984 18:02:38.273354 RX Delay -40 -> 252, step: 8
2985 18:02:38.273408 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2986 18:02:38.273460 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2987 18:02:38.273521 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2988 18:02:38.273574 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2989 18:02:38.273627 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2990 18:02:38.273679 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2991 18:02:38.273737 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2992 18:02:38.273790 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2993 18:02:38.273843 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2994 18:02:38.273896 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2995 18:02:38.273949 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2996 18:02:38.274005 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2997 18:02:38.274060 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2998 18:02:38.274112 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2999 18:02:38.274165 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3000 18:02:38.274217 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
3001 18:02:38.274269 ==
3002 18:02:38.274330 Dram Type= 6, Freq= 0, CH_0, rank 1
3003 18:02:38.274384 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3004 18:02:38.274438 ==
3005 18:02:38.528487 DQS Delay:
3006 18:02:38.528653 DQS0 = 0, DQS1 = 0
3007 18:02:38.528722 DQM Delay:
3008 18:02:38.528781 DQM0 = 120, DQM1 = 108
3009 18:02:38.528838 DQ Delay:
3010 18:02:38.528893 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =115
3011 18:02:38.528948 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
3012 18:02:38.529009 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =107
3013 18:02:38.529064 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =115
3014 18:02:38.529118
3015 18:02:38.529171
3016 18:02:38.529243 ==
3017 18:02:38.529306 Dram Type= 6, Freq= 0, CH_0, rank 1
3018 18:02:38.529360 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3019 18:02:38.529413 ==
3020 18:02:38.529465
3021 18:02:38.529516
3022 18:02:38.529572 TX Vref Scan disable
3023 18:02:38.529626 == TX Byte 0 ==
3024 18:02:38.529678 Update DQ dly =855 (3 ,2, 23) DQ OEN =(2 ,7)
3025 18:02:38.529731 Update DQM dly =855 (3 ,2, 23) DQM OEN =(2 ,7)
3026 18:02:38.529812 == TX Byte 1 ==
3027 18:02:38.529869 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3028 18:02:38.529923 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3029 18:02:38.529975 ==
3030 18:02:38.530026 Dram Type= 6, Freq= 0, CH_0, rank 1
3031 18:02:38.530078 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3032 18:02:38.530135 ==
3033 18:02:38.530188 TX Vref=22, minBit 1, minWin=25, winSum=417
3034 18:02:38.530241 TX Vref=24, minBit 1, minWin=25, winSum=423
3035 18:02:38.530293 TX Vref=26, minBit 1, minWin=26, winSum=428
3036 18:02:38.530345 TX Vref=28, minBit 3, minWin=25, winSum=425
3037 18:02:38.530404 TX Vref=30, minBit 5, minWin=25, winSum=429
3038 18:02:38.530457 TX Vref=32, minBit 5, minWin=25, winSum=429
3039 18:02:38.530509 [TxChooseVref] Worse bit 1, Min win 26, Win sum 428, Final Vref 26
3040 18:02:38.530561
3041 18:02:38.530612 Final TX Range 1 Vref 26
3042 18:02:38.530673
3043 18:02:38.530725 ==
3044 18:02:38.530794 Dram Type= 6, Freq= 0, CH_0, rank 1
3045 18:02:38.530910 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3046 18:02:38.530978 ==
3047 18:02:38.531030
3048 18:02:38.531081
3049 18:02:38.531132 TX Vref Scan disable
3050 18:02:38.531189 == TX Byte 0 ==
3051 18:02:38.531242 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
3052 18:02:38.531294 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
3053 18:02:38.531346 == TX Byte 1 ==
3054 18:02:38.531398 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3055 18:02:38.531477 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3056 18:02:38.531558
3057 18:02:38.531638 [DATLAT]
3058 18:02:38.531722 Freq=1200, CH0 RK1
3059 18:02:38.531838
3060 18:02:38.531920 DATLAT Default: 0xd
3061 18:02:38.532038 0, 0xFFFF, sum = 0
3062 18:02:38.532121 1, 0xFFFF, sum = 0
3063 18:02:38.532204 2, 0xFFFF, sum = 0
3064 18:02:38.532290 3, 0xFFFF, sum = 0
3065 18:02:38.532373 4, 0xFFFF, sum = 0
3066 18:02:38.532455 5, 0xFFFF, sum = 0
3067 18:02:38.532542 6, 0xFFFF, sum = 0
3068 18:02:38.532658 7, 0xFFFF, sum = 0
3069 18:02:38.532740 8, 0xFFFF, sum = 0
3070 18:02:38.532830 9, 0xFFFF, sum = 0
3071 18:02:38.532914 10, 0xFFFF, sum = 0
3072 18:02:38.532997 11, 0xFFFF, sum = 0
3073 18:02:38.533082 12, 0x0, sum = 1
3074 18:02:38.533166 13, 0x0, sum = 2
3075 18:02:38.533248 14, 0x0, sum = 3
3076 18:02:38.533330 15, 0x0, sum = 4
3077 18:02:38.533417 best_step = 13
3078 18:02:38.533497
3079 18:02:38.533577 ==
3080 18:02:38.533661 Dram Type= 6, Freq= 0, CH_0, rank 1
3081 18:02:38.533743 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3082 18:02:38.533865 ==
3083 18:02:38.534229 RX Vref Scan: 0
3084 18:02:38.534327
3085 18:02:38.534395 RX Vref 0 -> 0, step: 1
3086 18:02:38.534462
3087 18:02:38.534577 RX Delay -21 -> 252, step: 4
3088 18:02:38.534643 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3089 18:02:38.534695 iDelay=195, Bit 1, Center 122 (55 ~ 190) 136
3090 18:02:38.534747 iDelay=195, Bit 2, Center 116 (51 ~ 182) 132
3091 18:02:38.534831 iDelay=195, Bit 3, Center 114 (51 ~ 178) 128
3092 18:02:38.534898 iDelay=195, Bit 4, Center 120 (55 ~ 186) 132
3093 18:02:38.534951 iDelay=195, Bit 5, Center 114 (51 ~ 178) 128
3094 18:02:38.535005 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3095 18:02:38.535095 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3096 18:02:38.535149 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3097 18:02:38.535202 iDelay=195, Bit 9, Center 94 (31 ~ 158) 128
3098 18:02:38.535255 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3099 18:02:38.535316 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3100 18:02:38.535369 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
3101 18:02:38.535422 iDelay=195, Bit 13, Center 110 (47 ~ 174) 128
3102 18:02:38.535475 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3103 18:02:38.535528 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
3104 18:02:38.535589 ==
3105 18:02:38.535643 Dram Type= 6, Freq= 0, CH_0, rank 1
3106 18:02:38.535696 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3107 18:02:38.535749 ==
3108 18:02:38.535807 DQS Delay:
3109 18:02:38.535893 DQS0 = 0, DQS1 = 0
3110 18:02:38.535982 DQM Delay:
3111 18:02:38.536072 DQM0 = 119, DQM1 = 107
3112 18:02:38.536155 DQ Delay:
3113 18:02:38.536238 DQ0 =118, DQ1 =122, DQ2 =116, DQ3 =114
3114 18:02:38.536321 DQ4 =120, DQ5 =114, DQ6 =126, DQ7 =126
3115 18:02:38.536407 DQ8 =98, DQ9 =94, DQ10 =110, DQ11 =106
3116 18:02:38.536490 DQ12 =112, DQ13 =110, DQ14 =118, DQ15 =114
3117 18:02:38.536596
3118 18:02:38.536694
3119 18:02:38.536777 [DQSOSCAuto] RK1, (LSB)MR18= 0x9f1, (MSB)MR19= 0x403, tDQSOscB0 = 416 ps tDQSOscB1 = 406 ps
3120 18:02:38.536860 CH0 RK1: MR19=403, MR18=9F1
3121 18:02:38.536948 CH0_RK1: MR19=0x403, MR18=0x9F1, DQSOSC=406, MR23=63, INC=39, DEC=26
3122 18:02:38.537031 [RxdqsGatingPostProcess] freq 1200
3123 18:02:38.537114 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3124 18:02:38.537199 best DQS0 dly(2T, 0.5T) = (0, 11)
3125 18:02:38.537283 best DQS1 dly(2T, 0.5T) = (0, 11)
3126 18:02:38.537365 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3127 18:02:38.537447 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3128 18:02:38.537533 best DQS0 dly(2T, 0.5T) = (0, 11)
3129 18:02:38.537644 best DQS1 dly(2T, 0.5T) = (0, 11)
3130 18:02:38.537758 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3131 18:02:38.537841 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3132 18:02:38.537922 Pre-setting of DQS Precalculation
3133 18:02:38.538008 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3134 18:02:38.538091 ==
3135 18:02:38.538174 Dram Type= 6, Freq= 0, CH_1, rank 0
3136 18:02:38.538287 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3137 18:02:38.538384 ==
3138 18:02:38.538480 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3139 18:02:38.538571 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3140 18:02:38.538656 [CA 0] Center 37 (7~68) winsize 62
3141 18:02:38.538714 [CA 1] Center 37 (7~68) winsize 62
3142 18:02:38.538772 [CA 2] Center 35 (5~65) winsize 61
3143 18:02:38.538826 [CA 3] Center 34 (4~65) winsize 62
3144 18:02:38.538894 [CA 4] Center 34 (4~65) winsize 62
3145 18:02:38.538947 [CA 5] Center 33 (3~64) winsize 62
3146 18:02:38.539031
3147 18:02:38.539113 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3148 18:02:38.539197
3149 18:02:38.539280 [CATrainingPosCal] consider 1 rank data
3150 18:02:38.539362 u2DelayCellTimex100 = 270/100 ps
3151 18:02:38.539448 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3152 18:02:38.539507 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3153 18:02:38.539561 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3154 18:02:38.539615 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3155 18:02:38.539674 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3156 18:02:38.539729 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3157 18:02:38.539783
3158 18:02:38.539834 CA PerBit enable=1, Macro0, CA PI delay=33
3159 18:02:38.539893
3160 18:02:38.539947 [CBTSetCACLKResult] CA Dly = 33
3161 18:02:38.540000 CS Dly: 5 (0~36)
3162 18:02:38.540052 ==
3163 18:02:38.540104 Dram Type= 6, Freq= 0, CH_1, rank 1
3164 18:02:38.540158 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3165 18:02:38.540217 ==
3166 18:02:38.540272 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3167 18:02:38.540325 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3168 18:02:38.540378 [CA 0] Center 38 (8~68) winsize 61
3169 18:02:38.540431 [CA 1] Center 38 (7~69) winsize 63
3170 18:02:38.540516 [CA 2] Center 35 (5~66) winsize 62
3171 18:02:38.540617 [CA 3] Center 35 (5~65) winsize 61
3172 18:02:38.540674 [CA 4] Center 35 (5~65) winsize 61
3173 18:02:38.540731 [CA 5] Center 34 (4~64) winsize 61
3174 18:02:38.540798
3175 18:02:38.540865 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3176 18:02:38.540922
3177 18:02:38.540977 [CATrainingPosCal] consider 2 rank data
3178 18:02:38.541029 u2DelayCellTimex100 = 270/100 ps
3179 18:02:38.541082 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3180 18:02:38.541134 CA1 delay=37 (7~68),Diff = 3 PI (14 cell)
3181 18:02:38.541195 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3182 18:02:38.541248 CA3 delay=35 (5~65),Diff = 1 PI (4 cell)
3183 18:02:38.541301 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
3184 18:02:38.541354 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3185 18:02:38.541415
3186 18:02:38.541469 CA PerBit enable=1, Macro0, CA PI delay=34
3187 18:02:38.541526
3188 18:02:38.541583 [CBTSetCACLKResult] CA Dly = 34
3189 18:02:38.541645 CS Dly: 6 (0~39)
3190 18:02:38.541698
3191 18:02:38.541751 ----->DramcWriteLeveling(PI) begin...
3192 18:02:38.541805 ==
3193 18:02:38.541863 Dram Type= 6, Freq= 0, CH_1, rank 0
3194 18:02:38.541918 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3195 18:02:38.542001 ==
3196 18:02:38.542053 Write leveling (Byte 0): 25 => 25
3197 18:02:38.542114 Write leveling (Byte 1): 28 => 28
3198 18:02:38.542168 DramcWriteLeveling(PI) end<-----
3199 18:02:38.542221
3200 18:02:38.542273 ==
3201 18:02:38.542346 Dram Type= 6, Freq= 0, CH_1, rank 0
3202 18:02:38.542442 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3203 18:02:38.542525 ==
3204 18:02:38.542584 [Gating] SW mode calibration
3205 18:02:38.542866 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3206 18:02:38.542930 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3207 18:02:38.542985 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3208 18:02:38.543041 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3209 18:02:38.543114 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3210 18:02:38.543169 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3211 18:02:38.543223 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3212 18:02:38.543277 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3213 18:02:38.543339 0 15 24 | B1->B0 | 3232 2929 | 0 0 | (0 0) (1 0)
3214 18:02:38.543395 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3215 18:02:38.543450 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3216 18:02:38.543504 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3217 18:02:38.543603 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3218 18:02:38.543687 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3219 18:02:38.543787 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3220 18:02:38.543888 1 0 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
3221 18:02:38.543944 1 0 24 | B1->B0 | 3737 4242 | 1 0 | (0 0) (0 0)
3222 18:02:38.543999 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3223 18:02:38.544099 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3224 18:02:38.544166 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3225 18:02:38.544234 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3226 18:02:38.544335 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3227 18:02:38.544389 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3228 18:02:38.544442 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3229 18:02:38.544495 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3230 18:02:38.544629 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3231 18:02:38.544699 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3232 18:02:38.544753 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3233 18:02:38.544842 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3234 18:02:38.544896 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3235 18:02:38.544949 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3236 18:02:38.545002 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3237 18:02:38.545089 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3238 18:02:38.545172 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3239 18:02:38.545225 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3240 18:02:38.545300 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3241 18:02:38.545368 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3242 18:02:38.545421 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3243 18:02:38.545474 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3244 18:02:38.545547 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3245 18:02:38.545616 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3246 18:02:38.545669 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3247 18:02:38.545721 Total UI for P1: 0, mck2ui 16
3248 18:02:38.545823 best dqsien dly found for B0: ( 1, 3, 22)
3249 18:02:38.545912 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3250 18:02:38.546001 Total UI for P1: 0, mck2ui 16
3251 18:02:38.546062 best dqsien dly found for B1: ( 1, 3, 26)
3252 18:02:38.546116 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3253 18:02:38.546170 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3254 18:02:38.546224
3255 18:02:38.546328 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3256 18:02:38.546418 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3257 18:02:38.546472 [Gating] SW calibration Done
3258 18:02:38.546533 ==
3259 18:02:38.546586 Dram Type= 6, Freq= 0, CH_1, rank 0
3260 18:02:38.546639 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3261 18:02:38.546693 ==
3262 18:02:38.546751 RX Vref Scan: 0
3263 18:02:38.546805
3264 18:02:38.546858 RX Vref 0 -> 0, step: 1
3265 18:02:38.546911
3266 18:02:38.546963 RX Delay -40 -> 252, step: 8
3267 18:02:38.547025 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3268 18:02:38.547078 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3269 18:02:38.547132 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3270 18:02:38.547184 iDelay=200, Bit 3, Center 123 (56 ~ 191) 136
3271 18:02:38.547237 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3272 18:02:38.547332 iDelay=200, Bit 5, Center 127 (64 ~ 191) 128
3273 18:02:38.547385 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3274 18:02:38.547439 iDelay=200, Bit 7, Center 119 (56 ~ 183) 128
3275 18:02:38.547492 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3276 18:02:38.547549 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3277 18:02:38.547603 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3278 18:02:38.547656 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3279 18:02:38.547709 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3280 18:02:38.547761 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3281 18:02:38.547818 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3282 18:02:38.547872 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3283 18:02:38.547925 ==
3284 18:02:38.547978 Dram Type= 6, Freq= 0, CH_1, rank 0
3285 18:02:38.548032 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3286 18:02:38.548090 ==
3287 18:02:38.548144 DQS Delay:
3288 18:02:38.548197 DQS0 = 0, DQS1 = 0
3289 18:02:38.548250 DQM Delay:
3290 18:02:38.548302 DQM0 = 119, DQM1 = 112
3291 18:02:38.548363 DQ Delay:
3292 18:02:38.548416 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =123
3293 18:02:38.548469 DQ4 =115, DQ5 =127, DQ6 =127, DQ7 =119
3294 18:02:38.548523 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3295 18:02:38.548620 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =119
3296 18:02:38.548675
3297 18:02:38.548727
3298 18:02:38.548779 ==
3299 18:02:38.548832 Dram Type= 6, Freq= 0, CH_1, rank 0
3300 18:02:38.548893 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3301 18:02:38.548947 ==
3302 18:02:38.548999
3303 18:02:38.549052
3304 18:02:38.549105 TX Vref Scan disable
3305 18:02:38.549163 == TX Byte 0 ==
3306 18:02:38.549217 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3307 18:02:38.549270 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3308 18:02:38.549323 == TX Byte 1 ==
3309 18:02:38.549376 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3310 18:02:38.549626 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3311 18:02:38.549725 ==
3312 18:02:38.549780 Dram Type= 6, Freq= 0, CH_1, rank 0
3313 18:02:38.549833 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3314 18:02:38.549887 ==
3315 18:02:38.549975 TX Vref=22, minBit 10, minWin=24, winSum=407
3316 18:02:38.550030 TX Vref=24, minBit 1, minWin=24, winSum=408
3317 18:02:38.550084 TX Vref=26, minBit 8, minWin=25, winSum=415
3318 18:02:38.550136 TX Vref=28, minBit 10, minWin=25, winSum=419
3319 18:02:38.550189 TX Vref=30, minBit 9, minWin=25, winSum=421
3320 18:02:38.550249 TX Vref=32, minBit 9, minWin=25, winSum=423
3321 18:02:38.550303 [TxChooseVref] Worse bit 9, Min win 25, Win sum 423, Final Vref 32
3322 18:02:38.550356
3323 18:02:38.550409 Final TX Range 1 Vref 32
3324 18:02:38.550463
3325 18:02:38.550562 ==
3326 18:02:38.550619 Dram Type= 6, Freq= 0, CH_1, rank 0
3327 18:02:38.550688 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3328 18:02:38.550777 ==
3329 18:02:38.550873
3330 18:02:38.550926
3331 18:02:38.551012 TX Vref Scan disable
3332 18:02:38.551067 == TX Byte 0 ==
3333 18:02:38.551120 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3334 18:02:38.551190 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3335 18:02:38.551282 == TX Byte 1 ==
3336 18:02:38.551350 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3337 18:02:38.551403 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3338 18:02:38.551456
3339 18:02:38.551531 [DATLAT]
3340 18:02:38.551629 Freq=1200, CH1 RK0
3341 18:02:38.551711
3342 18:02:38.551811 DATLAT Default: 0xd
3343 18:02:38.551895 0, 0xFFFF, sum = 0
3344 18:02:38.551983 1, 0xFFFF, sum = 0
3345 18:02:38.552114 2, 0xFFFF, sum = 0
3346 18:02:38.552228 3, 0xFFFF, sum = 0
3347 18:02:38.552332 4, 0xFFFF, sum = 0
3348 18:02:38.552431 5, 0xFFFF, sum = 0
3349 18:02:38.552533 6, 0xFFFF, sum = 0
3350 18:02:38.552642 7, 0xFFFF, sum = 0
3351 18:02:38.552727 8, 0xFFFF, sum = 0
3352 18:02:38.552810 9, 0xFFFF, sum = 0
3353 18:02:38.552897 10, 0xFFFF, sum = 0
3354 18:02:38.552982 11, 0xFFFF, sum = 0
3355 18:02:38.553067 12, 0x0, sum = 1
3356 18:02:38.553153 13, 0x0, sum = 2
3357 18:02:38.553238 14, 0x0, sum = 3
3358 18:02:38.553321 15, 0x0, sum = 4
3359 18:02:38.553408 best_step = 13
3360 18:02:38.553490
3361 18:02:38.553570 ==
3362 18:02:38.553655 Dram Type= 6, Freq= 0, CH_1, rank 0
3363 18:02:38.553738 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3364 18:02:38.553819 ==
3365 18:02:38.553906 RX Vref Scan: 1
3366 18:02:38.553988
3367 18:02:38.554069 Set Vref Range= 32 -> 127
3368 18:02:38.554153
3369 18:02:38.554234 RX Vref 32 -> 127, step: 1
3370 18:02:38.554314
3371 18:02:38.554410 RX Delay -13 -> 252, step: 4
3372 18:02:38.554462
3373 18:02:38.554514 Set Vref, RX VrefLevel [Byte0]: 32
3374 18:02:38.554566 [Byte1]: 32
3375 18:02:38.554627
3376 18:02:38.554709 Set Vref, RX VrefLevel [Byte0]: 33
3377 18:02:38.554799 [Byte1]: 33
3378 18:02:38.554884
3379 18:02:38.554980 Set Vref, RX VrefLevel [Byte0]: 34
3380 18:02:38.555063 [Byte1]: 34
3381 18:02:38.555152
3382 18:02:38.555250 Set Vref, RX VrefLevel [Byte0]: 35
3383 18:02:38.555332 [Byte1]: 35
3384 18:02:38.555415
3385 18:02:38.555496 Set Vref, RX VrefLevel [Byte0]: 36
3386 18:02:38.555576 [Byte1]: 36
3387 18:02:38.555631
3388 18:02:38.555682 Set Vref, RX VrefLevel [Byte0]: 37
3389 18:02:38.555733 [Byte1]: 37
3390 18:02:38.555784
3391 18:02:38.555842 Set Vref, RX VrefLevel [Byte0]: 38
3392 18:02:38.555896 [Byte1]: 38
3393 18:02:38.555984
3394 18:02:38.556076 Set Vref, RX VrefLevel [Byte0]: 39
3395 18:02:38.556190 [Byte1]: 39
3396 18:02:38.556272
3397 18:02:38.556355 Set Vref, RX VrefLevel [Byte0]: 40
3398 18:02:38.556452 [Byte1]: 40
3399 18:02:38.556540
3400 18:02:38.556602 Set Vref, RX VrefLevel [Byte0]: 41
3401 18:02:38.556656 [Byte1]: 41
3402 18:02:38.556722
3403 18:02:38.556797 Set Vref, RX VrefLevel [Byte0]: 42
3404 18:02:38.556864 [Byte1]: 42
3405 18:02:38.556918
3406 18:02:38.556969 Set Vref, RX VrefLevel [Byte0]: 43
3407 18:02:38.557028 [Byte1]: 43
3408 18:02:38.557081
3409 18:02:38.557132 Set Vref, RX VrefLevel [Byte0]: 44
3410 18:02:38.557183 [Byte1]: 44
3411 18:02:38.557277
3412 18:02:38.557331 Set Vref, RX VrefLevel [Byte0]: 45
3413 18:02:38.557383 [Byte1]: 45
3414 18:02:38.557469
3415 18:02:38.557522 Set Vref, RX VrefLevel [Byte0]: 46
3416 18:02:38.557590 [Byte1]: 46
3417 18:02:38.557656
3418 18:02:38.557730 Set Vref, RX VrefLevel [Byte0]: 47
3419 18:02:38.557812 [Byte1]: 47
3420 18:02:38.557877
3421 18:02:38.557932 Set Vref, RX VrefLevel [Byte0]: 48
3422 18:02:38.558000 [Byte1]: 48
3423 18:02:38.558065
3424 18:02:38.558116 Set Vref, RX VrefLevel [Byte0]: 49
3425 18:02:38.558168 [Byte1]: 49
3426 18:02:38.558225
3427 18:02:38.558278 Set Vref, RX VrefLevel [Byte0]: 50
3428 18:02:38.558329 [Byte1]: 50
3429 18:02:38.558380
3430 18:02:38.558437 Set Vref, RX VrefLevel [Byte0]: 51
3431 18:02:38.558489 [Byte1]: 51
3432 18:02:38.558557
3433 18:02:38.558649 Set Vref, RX VrefLevel [Byte0]: 52
3434 18:02:38.558807 [Byte1]: 52
3435 18:02:38.558906
3436 18:02:38.558988 Set Vref, RX VrefLevel [Byte0]: 53
3437 18:02:38.559069 [Byte1]: 53
3438 18:02:38.559156
3439 18:02:38.559237 Set Vref, RX VrefLevel [Byte0]: 54
3440 18:02:38.559320 [Byte1]: 54
3441 18:02:38.559400
3442 18:02:38.559484 Set Vref, RX VrefLevel [Byte0]: 55
3443 18:02:38.559566 [Byte1]: 55
3444 18:02:38.559648
3445 18:02:38.559729 Set Vref, RX VrefLevel [Byte0]: 56
3446 18:02:38.559810 [Byte1]: 56
3447 18:02:38.559895
3448 18:02:38.560005 Set Vref, RX VrefLevel [Byte0]: 57
3449 18:02:38.560059 [Byte1]: 57
3450 18:02:38.560111
3451 18:02:38.560163 Set Vref, RX VrefLevel [Byte0]: 58
3452 18:02:38.560221 [Byte1]: 58
3453 18:02:38.560274
3454 18:02:38.560338 Set Vref, RX VrefLevel [Byte0]: 59
3455 18:02:38.560404 [Byte1]: 59
3456 18:02:38.560487
3457 18:02:38.560617 Set Vref, RX VrefLevel [Byte0]: 60
3458 18:02:38.560703 [Byte1]: 60
3459 18:02:38.560851
3460 18:02:38.560935 Set Vref, RX VrefLevel [Byte0]: 61
3461 18:02:38.561019 [Byte1]: 61
3462 18:02:38.561075
3463 18:02:38.561135 Set Vref, RX VrefLevel [Byte0]: 62
3464 18:02:38.561238 [Byte1]: 62
3465 18:02:38.561305
3466 18:02:38.561363 Set Vref, RX VrefLevel [Byte0]: 63
3467 18:02:38.561416 [Byte1]: 63
3468 18:02:38.561467
3469 18:02:38.561567 Set Vref, RX VrefLevel [Byte0]: 64
3470 18:02:38.561637 [Byte1]: 64
3471 18:02:38.561689
3472 18:02:38.561740 Set Vref, RX VrefLevel [Byte0]: 65
3473 18:02:38.561792 [Byte1]: 65
3474 18:02:38.561851
3475 18:02:38.561903 Set Vref, RX VrefLevel [Byte0]: 66
3476 18:02:38.561955 [Byte1]: 66
3477 18:02:38.562220
3478 18:02:38.562279 Set Vref, RX VrefLevel [Byte0]: 67
3479 18:02:38.562338 [Byte1]: 67
3480 18:02:38.562409
3481 18:02:38.562462 Final RX Vref Byte 0 = 53 to rank0
3482 18:02:38.562514 Final RX Vref Byte 1 = 52 to rank0
3483 18:02:38.562574 Final RX Vref Byte 0 = 53 to rank1
3484 18:02:38.562627 Final RX Vref Byte 1 = 52 to rank1==
3485 18:02:38.562695 Dram Type= 6, Freq= 0, CH_1, rank 0
3486 18:02:38.562751 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3487 18:02:38.562809 ==
3488 18:02:38.562875 DQS Delay:
3489 18:02:38.562927 DQS0 = 0, DQS1 = 0
3490 18:02:38.562982 DQM Delay:
3491 18:02:38.563034 DQM0 = 119, DQM1 = 112
3492 18:02:38.563086 DQ Delay:
3493 18:02:38.563137 DQ0 =120, DQ1 =112, DQ2 =112, DQ3 =118
3494 18:02:38.563189 DQ4 =118, DQ5 =128, DQ6 =130, DQ7 =118
3495 18:02:38.563247 DQ8 =102, DQ9 =100, DQ10 =114, DQ11 =106
3496 18:02:38.563300 DQ12 =122, DQ13 =118, DQ14 =118, DQ15 =118
3497 18:02:38.563351
3498 18:02:38.563401
3499 18:02:38.563457 [DQSOSCAuto] RK0, (LSB)MR18= 0xff12, (MSB)MR19= 0x304, tDQSOscB0 = 403 ps tDQSOscB1 = 410 ps
3500 18:02:38.563526 CH1 RK0: MR19=304, MR18=FF12
3501 18:02:38.563579 CH1_RK0: MR19=0x304, MR18=0xFF12, DQSOSC=403, MR23=63, INC=40, DEC=26
3502 18:02:38.563632
3503 18:02:38.563706 ----->DramcWriteLeveling(PI) begin...
3504 18:02:38.563760 ==
3505 18:02:38.563812 Dram Type= 6, Freq= 0, CH_1, rank 1
3506 18:02:38.563864 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3507 18:02:38.563923 ==
3508 18:02:38.563975 Write leveling (Byte 0): 25 => 25
3509 18:02:38.564027 Write leveling (Byte 1): 29 => 29
3510 18:02:38.564079 DramcWriteLeveling(PI) end<-----
3511 18:02:38.564136
3512 18:02:38.564217 ==
3513 18:02:38.564298 Dram Type= 6, Freq= 0, CH_1, rank 1
3514 18:02:38.564382 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3515 18:02:38.564464 ==
3516 18:02:38.564544 [Gating] SW mode calibration
3517 18:02:38.564648 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3518 18:02:38.564702 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3519 18:02:38.564755 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3520 18:02:38.564806 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3521 18:02:38.564863 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3522 18:02:38.564917 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3523 18:02:38.564968 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3524 18:02:38.565021 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3525 18:02:38.565072 0 15 24 | B1->B0 | 2525 3232 | 0 1 | (0 0) (1 0)
3526 18:02:38.565132 0 15 28 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
3527 18:02:38.565184 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3528 18:02:38.565237 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3529 18:02:38.565289 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3530 18:02:38.565346 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3531 18:02:38.565399 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3532 18:02:38.565451 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3533 18:02:38.565503 1 0 24 | B1->B0 | 3a3a 2828 | 0 0 | (0 0) (0 0)
3534 18:02:38.565556 1 0 28 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
3535 18:02:38.565615 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3536 18:02:38.565667 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3537 18:02:38.565718 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3538 18:02:38.565770 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3539 18:02:38.565827 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3540 18:02:38.565879 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3541 18:02:38.565931 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3542 18:02:38.565983 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3543 18:02:38.566034 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3544 18:02:38.566093 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3545 18:02:38.566145 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3546 18:02:38.566197 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3547 18:02:38.566248 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3548 18:02:38.566304 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3549 18:02:38.566357 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3550 18:02:38.566408 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3551 18:02:38.566459 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3552 18:02:38.566510 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3553 18:02:38.566592 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3554 18:02:38.566674 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3555 18:02:38.566756 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3556 18:02:38.566849 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3557 18:02:38.566931 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3558 18:02:38.567015 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3559 18:02:38.567098 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3560 18:02:38.567178 Total UI for P1: 0, mck2ui 16
3561 18:02:38.567264 best dqsien dly found for B0: ( 1, 3, 26)
3562 18:02:38.567346 Total UI for P1: 0, mck2ui 16
3563 18:02:38.567428 best dqsien dly found for B1: ( 1, 3, 26)
3564 18:02:38.567514 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3565 18:02:38.567595 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3566 18:02:38.567675
3567 18:02:38.567760 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3568 18:02:38.567841 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3569 18:02:38.567922 [Gating] SW calibration Done
3570 18:02:38.568006 ==
3571 18:02:38.568088 Dram Type= 6, Freq= 0, CH_1, rank 1
3572 18:02:38.568169 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3573 18:02:38.568253 ==
3574 18:02:38.568335 RX Vref Scan: 0
3575 18:02:38.568415
3576 18:02:38.568499 RX Vref 0 -> 0, step: 1
3577 18:02:38.568615
3578 18:02:38.568694 RX Delay -40 -> 252, step: 8
3579 18:02:38.568749 iDelay=200, Bit 0, Center 123 (64 ~ 183) 120
3580 18:02:38.568801 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3581 18:02:38.568853 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3582 18:02:38.568905 iDelay=200, Bit 3, Center 123 (56 ~ 191) 136
3583 18:02:38.569166 iDelay=200, Bit 4, Center 119 (56 ~ 183) 128
3584 18:02:38.569229 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3585 18:02:38.569282 iDelay=200, Bit 6, Center 123 (56 ~ 191) 136
3586 18:02:38.569337 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3587 18:02:38.569408 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3588 18:02:38.569492 iDelay=200, Bit 9, Center 103 (40 ~ 167) 128
3589 18:02:38.569574 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3590 18:02:38.569656 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3591 18:02:38.569741 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3592 18:02:38.569823 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3593 18:02:38.569905 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3594 18:02:38.569990 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3595 18:02:38.570070 ==
3596 18:02:38.570154 Dram Type= 6, Freq= 0, CH_1, rank 1
3597 18:02:38.570237 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3598 18:02:38.570317 ==
3599 18:02:38.570431 DQS Delay:
3600 18:02:38.570536 DQS0 = 0, DQS1 = 0
3601 18:02:38.570637 DQM Delay:
3602 18:02:38.570719 DQM0 = 119, DQM1 = 113
3603 18:02:38.570799 DQ Delay:
3604 18:02:38.570884 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =123
3605 18:02:38.570966 DQ4 =119, DQ5 =131, DQ6 =123, DQ7 =115
3606 18:02:38.571047 DQ8 =99, DQ9 =103, DQ10 =115, DQ11 =107
3607 18:02:38.571133 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =123
3608 18:02:38.571214
3609 18:02:38.571294
3610 18:02:38.571377 ==
3611 18:02:38.571459 Dram Type= 6, Freq= 0, CH_1, rank 1
3612 18:02:38.571541 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3613 18:02:38.571609 ==
3614 18:02:38.571663
3615 18:02:38.571714
3616 18:02:38.571765 TX Vref Scan disable
3617 18:02:38.571821 == TX Byte 0 ==
3618 18:02:38.571875 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3619 18:02:38.571927 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3620 18:02:38.571979 == TX Byte 1 ==
3621 18:02:38.572030 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3622 18:02:38.572111 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3623 18:02:38.572192 ==
3624 18:02:38.572273 Dram Type= 6, Freq= 0, CH_1, rank 1
3625 18:02:38.572358 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3626 18:02:38.572439 ==
3627 18:02:38.572524 TX Vref=22, minBit 1, minWin=25, winSum=414
3628 18:02:38.572626 TX Vref=24, minBit 1, minWin=25, winSum=420
3629 18:02:38.572679 TX Vref=26, minBit 1, minWin=26, winSum=426
3630 18:02:38.572731 TX Vref=28, minBit 8, minWin=26, winSum=429
3631 18:02:38.572791 TX Vref=30, minBit 1, minWin=26, winSum=428
3632 18:02:38.572844 TX Vref=32, minBit 1, minWin=26, winSum=427
3633 18:02:38.572896 [TxChooseVref] Worse bit 8, Min win 26, Win sum 429, Final Vref 28
3634 18:02:38.572949
3635 18:02:38.573004 Final TX Range 1 Vref 28
3636 18:02:38.573058
3637 18:02:38.573109 ==
3638 18:02:38.573161 Dram Type= 6, Freq= 0, CH_1, rank 1
3639 18:02:38.573212 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3640 18:02:38.573271 ==
3641 18:02:38.573323
3642 18:02:38.573374
3643 18:02:38.573425 TX Vref Scan disable
3644 18:02:38.573482 == TX Byte 0 ==
3645 18:02:38.573535 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3646 18:02:38.573587 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3647 18:02:38.573637 == TX Byte 1 ==
3648 18:02:38.573688 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3649 18:02:38.573746 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3650 18:02:38.573799
3651 18:02:38.573850 [DATLAT]
3652 18:02:38.573901 Freq=1200, CH1 RK1
3653 18:02:38.573960
3654 18:02:38.574012 DATLAT Default: 0xd
3655 18:02:38.574064 0, 0xFFFF, sum = 0
3656 18:02:38.574117 1, 0xFFFF, sum = 0
3657 18:02:38.574176 2, 0xFFFF, sum = 0
3658 18:02:38.574259 3, 0xFFFF, sum = 0
3659 18:02:38.574341 4, 0xFFFF, sum = 0
3660 18:02:38.574427 5, 0xFFFF, sum = 0
3661 18:02:38.574510 6, 0xFFFF, sum = 0
3662 18:02:38.574620 7, 0xFFFF, sum = 0
3663 18:02:38.574698 8, 0xFFFF, sum = 0
3664 18:02:38.574752 9, 0xFFFF, sum = 0
3665 18:02:38.574804 10, 0xFFFF, sum = 0
3666 18:02:38.574856 11, 0xFFFF, sum = 0
3667 18:02:38.574913 12, 0x0, sum = 1
3668 18:02:38.574967 13, 0x0, sum = 2
3669 18:02:38.575019 14, 0x0, sum = 3
3670 18:02:38.575071 15, 0x0, sum = 4
3671 18:02:38.575123 best_step = 13
3672 18:02:38.575182
3673 18:02:38.575233 ==
3674 18:02:38.575285 Dram Type= 6, Freq= 0, CH_1, rank 1
3675 18:02:38.575337 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3676 18:02:38.575394 ==
3677 18:02:38.575447 RX Vref Scan: 0
3678 18:02:38.575497
3679 18:02:38.575548 RX Vref 0 -> 0, step: 1
3680 18:02:38.575599
3681 18:02:38.575656 RX Delay -13 -> 252, step: 4
3682 18:02:38.575708 iDelay=195, Bit 0, Center 122 (63 ~ 182) 120
3683 18:02:38.575759 iDelay=195, Bit 1, Center 114 (55 ~ 174) 120
3684 18:02:38.575811 iDelay=195, Bit 2, Center 108 (51 ~ 166) 116
3685 18:02:38.575870 iDelay=195, Bit 3, Center 116 (55 ~ 178) 124
3686 18:02:38.575923 iDelay=195, Bit 4, Center 122 (63 ~ 182) 120
3687 18:02:38.575975 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3688 18:02:38.576026 iDelay=195, Bit 6, Center 126 (67 ~ 186) 120
3689 18:02:38.576077 iDelay=195, Bit 7, Center 116 (55 ~ 178) 124
3690 18:02:38.576135 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3691 18:02:38.576187 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3692 18:02:38.576239 iDelay=195, Bit 10, Center 112 (47 ~ 178) 132
3693 18:02:38.576291 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3694 18:02:38.576351 iDelay=195, Bit 12, Center 122 (59 ~ 186) 128
3695 18:02:38.576403 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3696 18:02:38.576455 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3697 18:02:38.576507 iDelay=195, Bit 15, Center 124 (59 ~ 190) 132
3698 18:02:38.576607 ==
3699 18:02:38.576690 Dram Type= 6, Freq= 0, CH_1, rank 1
3700 18:02:38.576772 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3701 18:02:38.576856 ==
3702 18:02:38.576937 DQS Delay:
3703 18:02:38.577018 DQS0 = 0, DQS1 = 0
3704 18:02:38.577102 DQM Delay:
3705 18:02:38.577183 DQM0 = 119, DQM1 = 113
3706 18:02:38.577263 DQ Delay:
3707 18:02:38.577348 DQ0 =122, DQ1 =114, DQ2 =108, DQ3 =116
3708 18:02:38.577429 DQ4 =122, DQ5 =130, DQ6 =126, DQ7 =116
3709 18:02:38.577510 DQ8 =98, DQ9 =102, DQ10 =112, DQ11 =106
3710 18:02:38.577595 DQ12 =122, DQ13 =118, DQ14 =122, DQ15 =124
3711 18:02:38.577676
3712 18:02:38.577755
3713 18:02:38.577842 [DQSOSCAuto] RK1, (LSB)MR18= 0x8ed, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 406 ps
3714 18:02:38.577924 CH1 RK1: MR19=403, MR18=8ED
3715 18:02:38.578008 CH1_RK1: MR19=0x403, MR18=0x8ED, DQSOSC=406, MR23=63, INC=39, DEC=26
3716 18:02:38.578091 [RxdqsGatingPostProcess] freq 1200
3717 18:02:38.578172 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3718 18:02:38.578257 best DQS0 dly(2T, 0.5T) = (0, 11)
3719 18:02:38.578338 best DQS1 dly(2T, 0.5T) = (0, 11)
3720 18:02:38.578421 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3721 18:02:38.578702 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3722 18:02:38.578791 best DQS0 dly(2T, 0.5T) = (0, 11)
3723 18:02:38.578874 best DQS1 dly(2T, 0.5T) = (0, 11)
3724 18:02:38.578959 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3725 18:02:38.579042 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3726 18:02:38.579123 Pre-setting of DQS Precalculation
3727 18:02:38.579208 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3728 18:02:38.579292 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3729 18:02:38.579375 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3730 18:02:38.579459
3731 18:02:38.579540
3732 18:02:38.579620 [Calibration Summary] 2400 Mbps
3733 18:02:38.579705 CH 0, Rank 0
3734 18:02:38.579786 SW Impedance : PASS
3735 18:02:38.579870 DUTY Scan : NO K
3736 18:02:38.579952 ZQ Calibration : PASS
3737 18:02:38.580033 Jitter Meter : NO K
3738 18:02:38.580117 CBT Training : PASS
3739 18:02:38.580198 Write leveling : PASS
3740 18:02:38.580279 RX DQS gating : PASS
3741 18:02:38.580363 RX DQ/DQS(RDDQC) : PASS
3742 18:02:38.580444 TX DQ/DQS : PASS
3743 18:02:38.580526 RX DATLAT : PASS
3744 18:02:38.580646 RX DQ/DQS(Engine): PASS
3745 18:02:38.580728 TX OE : NO K
3746 18:02:38.580811 All Pass.
3747 18:02:38.580892
3748 18:02:38.580972 CH 0, Rank 1
3749 18:02:38.581055 SW Impedance : PASS
3750 18:02:38.581137 DUTY Scan : NO K
3751 18:02:38.581232 ZQ Calibration : PASS
3752 18:02:38.581319 Jitter Meter : NO K
3753 18:02:38.581401 CBT Training : PASS
3754 18:02:38.581484 Write leveling : PASS
3755 18:02:38.581570 RX DQS gating : PASS
3756 18:02:38.581653 RX DQ/DQS(RDDQC) : PASS
3757 18:02:38.581740 TX DQ/DQS : PASS
3758 18:02:38.581841 RX DATLAT : PASS
3759 18:02:38.581932 RX DQ/DQS(Engine): PASS
3760 18:02:38.582019 TX OE : NO K
3761 18:02:38.582102 All Pass.
3762 18:02:38.582188
3763 18:02:38.582281 CH 1, Rank 0
3764 18:02:38.582364 SW Impedance : PASS
3765 18:02:38.582447 DUTY Scan : NO K
3766 18:02:38.582543 ZQ Calibration : PASS
3767 18:02:38.582635 Jitter Meter : NO K
3768 18:02:38.582725 CBT Training : PASS
3769 18:02:38.582809 Write leveling : PASS
3770 18:02:38.582892 RX DQS gating : PASS
3771 18:02:38.582977 RX DQ/DQS(RDDQC) : PASS
3772 18:02:38.583060 TX DQ/DQS : PASS
3773 18:02:38.583143 RX DATLAT : PASS
3774 18:02:38.583229 RX DQ/DQS(Engine): PASS
3775 18:02:38.583311 TX OE : NO K
3776 18:02:38.583394 All Pass.
3777 18:02:38.583480
3778 18:02:38.583562 CH 1, Rank 1
3779 18:02:38.583645 SW Impedance : PASS
3780 18:02:38.583710 DUTY Scan : NO K
3781 18:02:38.583763 ZQ Calibration : PASS
3782 18:02:38.583816 Jitter Meter : NO K
3783 18:02:38.583868 CBT Training : PASS
3784 18:02:38.583928 Write leveling : PASS
3785 18:02:38.583981 RX DQS gating : PASS
3786 18:02:38.584034 RX DQ/DQS(RDDQC) : PASS
3787 18:02:38.584086 TX DQ/DQS : PASS
3788 18:02:38.584148 RX DATLAT : PASS
3789 18:02:38.584232 RX DQ/DQS(Engine): PASS
3790 18:02:38.584314 TX OE : NO K
3791 18:02:38.584400 All Pass.
3792 18:02:38.584483
3793 18:02:38.584572 DramC Write-DBI off
3794 18:02:38.584659 PER_BANK_REFRESH: Hybrid Mode
3795 18:02:38.584753 TX_TRACKING: ON
3796 18:02:38.584850 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3797 18:02:38.584938 [FAST_K] Save calibration result to emmc
3798 18:02:38.585022 dramc_set_vcore_voltage set vcore to 650000
3799 18:02:38.585103 Read voltage for 600, 5
3800 18:02:38.585158 Vio18 = 0
3801 18:02:38.585211 Vcore = 650000
3802 18:02:38.585262 Vdram = 0
3803 18:02:38.585318 Vddq = 0
3804 18:02:38.585374 Vmddr = 0
3805 18:02:38.585426 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3806 18:02:38.585479 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3807 18:02:38.585532 MEM_TYPE=3, freq_sel=19
3808 18:02:38.585615 sv_algorithm_assistance_LP4_1600
3809 18:02:38.585700 ============ PULL DRAM RESETB DOWN ============
3810 18:02:38.585786 ========== PULL DRAM RESETB DOWN end =========
3811 18:02:38.585871 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3812 18:02:38.585967 ===================================
3813 18:02:38.586057 LPDDR4 DRAM CONFIGURATION
3814 18:02:38.586141 ===================================
3815 18:02:38.586223 EX_ROW_EN[0] = 0x0
3816 18:02:38.586310 EX_ROW_EN[1] = 0x0
3817 18:02:38.586392 LP4Y_EN = 0x0
3818 18:02:38.586475 WORK_FSP = 0x0
3819 18:02:38.586561 WL = 0x2
3820 18:02:38.586643 RL = 0x2
3821 18:02:38.586728 BL = 0x2
3822 18:02:38.586812 RPST = 0x0
3823 18:02:38.586894 RD_PRE = 0x0
3824 18:02:38.586979 WR_PRE = 0x1
3825 18:02:38.587062 WR_PST = 0x0
3826 18:02:38.587145 DBI_WR = 0x0
3827 18:02:38.587230 DBI_RD = 0x0
3828 18:02:38.587313 OTF = 0x1
3829 18:02:38.587396 ===================================
3830 18:02:38.587483 ===================================
3831 18:02:38.587565 ANA top config
3832 18:02:38.587648 ===================================
3833 18:02:38.587716 DLL_ASYNC_EN = 0
3834 18:02:38.587770 ALL_SLAVE_EN = 1
3835 18:02:38.587824 NEW_RANK_MODE = 1
3836 18:02:38.587877 DLL_IDLE_MODE = 1
3837 18:02:38.587946 LP45_APHY_COMB_EN = 1
3838 18:02:38.588029 TX_ODT_DIS = 1
3839 18:02:38.588112 NEW_8X_MODE = 1
3840 18:02:38.588199 ===================================
3841 18:02:38.588282 ===================================
3842 18:02:38.588365 data_rate = 1200
3843 18:02:38.588452 CKR = 1
3844 18:02:38.588535 DQ_P2S_RATIO = 8
3845 18:02:38.588626 ===================================
3846 18:02:38.588683 CA_P2S_RATIO = 8
3847 18:02:38.588736 DQ_CA_OPEN = 0
3848 18:02:38.588788 DQ_SEMI_OPEN = 0
3849 18:02:38.588841 CA_SEMI_OPEN = 0
3850 18:02:38.588901 CA_FULL_RATE = 0
3851 18:02:38.588955 DQ_CKDIV4_EN = 1
3852 18:02:38.589007 CA_CKDIV4_EN = 1
3853 18:02:38.589059 CA_PREDIV_EN = 0
3854 18:02:38.589118 PH8_DLY = 0
3855 18:02:38.589172 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3856 18:02:38.589224 DQ_AAMCK_DIV = 4
3857 18:02:38.589276 CA_AAMCK_DIV = 4
3858 18:02:38.589333 CA_ADMCK_DIV = 4
3859 18:02:38.589387 DQ_TRACK_CA_EN = 0
3860 18:02:38.589440 CA_PICK = 600
3861 18:02:38.589492 CA_MCKIO = 600
3862 18:02:38.589545 MCKIO_SEMI = 0
3863 18:02:38.589631 PLL_FREQ = 2288
3864 18:02:38.589722 DQ_UI_PI_RATIO = 32
3865 18:02:38.589810 CA_UI_PI_RATIO = 0
3866 18:02:38.589894 ===================================
3867 18:02:38.590174 ===================================
3868 18:02:38.590264 memory_type:LPDDR4
3869 18:02:38.590350 GP_NUM : 10
3870 18:02:38.590434 SRAM_EN : 1
3871 18:02:38.590520 MD32_EN : 0
3872 18:02:38.590604 ===================================
3873 18:02:38.590688 [ANA_INIT] >>>>>>>>>>>>>>
3874 18:02:38.590775 <<<<<< [CONFIGURE PHASE]: ANA_TX
3875 18:02:38.590859 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3876 18:02:38.590942 ===================================
3877 18:02:38.591029 data_rate = 1200,PCW = 0X5800
3878 18:02:38.591112 ===================================
3879 18:02:38.591195 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3880 18:02:38.591283 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3881 18:02:38.591367 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3882 18:02:38.591454 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3883 18:02:38.591537 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3884 18:02:38.591620 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3885 18:02:38.591707 [ANA_INIT] flow start
3886 18:02:38.591790 [ANA_INIT] PLL >>>>>>>>
3887 18:02:38.591872 [ANA_INIT] PLL <<<<<<<<
3888 18:02:38.591958 [ANA_INIT] MIDPI >>>>>>>>
3889 18:02:38.592042 [ANA_INIT] MIDPI <<<<<<<<
3890 18:02:38.592125 [ANA_INIT] DLL >>>>>>>>
3891 18:02:38.592210 [ANA_INIT] flow end
3892 18:02:38.592293 ============ LP4 DIFF to SE enter ============
3893 18:02:38.592377 ============ LP4 DIFF to SE exit ============
3894 18:02:38.592464 [ANA_INIT] <<<<<<<<<<<<<
3895 18:02:38.592562 [Flow] Enable top DCM control >>>>>
3896 18:02:38.592646 [Flow] Enable top DCM control <<<<<
3897 18:02:38.592702 Enable DLL master slave shuffle
3898 18:02:38.592755 ==============================================================
3899 18:02:38.592808 Gating Mode config
3900 18:02:38.592865 ==============================================================
3901 18:02:38.592920 Config description:
3902 18:02:38.592973 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3903 18:02:38.593027 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3904 18:02:38.593080 SELPH_MODE 0: By rank 1: By Phase
3905 18:02:38.593139 ==============================================================
3906 18:02:38.593193 GAT_TRACK_EN = 1
3907 18:02:38.593245 RX_GATING_MODE = 2
3908 18:02:38.593297 RX_GATING_TRACK_MODE = 2
3909 18:02:38.593357 SELPH_MODE = 1
3910 18:02:38.593438 PICG_EARLY_EN = 1
3911 18:02:38.593522 VALID_LAT_VALUE = 1
3912 18:02:38.593609 ==============================================================
3913 18:02:38.593693 Enter into Gating configuration >>>>
3914 18:02:38.593776 Exit from Gating configuration <<<<
3915 18:02:38.593863 Enter into DVFS_PRE_config >>>>>
3916 18:02:38.593948 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3917 18:02:38.594033 Exit from DVFS_PRE_config <<<<<
3918 18:02:38.594118 Enter into PICG configuration >>>>
3919 18:02:38.594201 Exit from PICG configuration <<<<
3920 18:02:38.594286 [RX_INPUT] configuration >>>>>
3921 18:02:38.594369 [RX_INPUT] configuration <<<<<
3922 18:02:38.594468 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3923 18:02:38.594764 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3924 18:02:38.601356 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3925 18:02:38.607914 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3926 18:02:38.614430 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3927 18:02:38.621379 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3928 18:02:38.624561 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3929 18:02:38.628185 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3930 18:02:38.631196 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3931 18:02:38.638016 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3932 18:02:38.641096 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3933 18:02:38.644379 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3934 18:02:38.648146 ===================================
3935 18:02:38.651021 LPDDR4 DRAM CONFIGURATION
3936 18:02:38.654678 ===================================
3937 18:02:38.657831 EX_ROW_EN[0] = 0x0
3938 18:02:38.657910 EX_ROW_EN[1] = 0x0
3939 18:02:38.660992 LP4Y_EN = 0x0
3940 18:02:38.661092 WORK_FSP = 0x0
3941 18:02:38.664295 WL = 0x2
3942 18:02:38.664395 RL = 0x2
3943 18:02:38.667631 BL = 0x2
3944 18:02:38.667706 RPST = 0x0
3945 18:02:38.670880 RD_PRE = 0x0
3946 18:02:38.670983 WR_PRE = 0x1
3947 18:02:38.674192 WR_PST = 0x0
3948 18:02:38.674267 DBI_WR = 0x0
3949 18:02:38.677314 DBI_RD = 0x0
3950 18:02:38.677414 OTF = 0x1
3951 18:02:38.681010 ===================================
3952 18:02:38.687702 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3953 18:02:38.691020 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3954 18:02:38.694347 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3955 18:02:38.697786 ===================================
3956 18:02:38.700514 LPDDR4 DRAM CONFIGURATION
3957 18:02:38.704460 ===================================
3958 18:02:38.707603 EX_ROW_EN[0] = 0x10
3959 18:02:38.707701 EX_ROW_EN[1] = 0x0
3960 18:02:38.710827 LP4Y_EN = 0x0
3961 18:02:38.710928 WORK_FSP = 0x0
3962 18:02:38.714002 WL = 0x2
3963 18:02:38.714080 RL = 0x2
3964 18:02:38.717315 BL = 0x2
3965 18:02:38.717415 RPST = 0x0
3966 18:02:38.720434 RD_PRE = 0x0
3967 18:02:38.720533 WR_PRE = 0x1
3968 18:02:38.723788 WR_PST = 0x0
3969 18:02:38.723861 DBI_WR = 0x0
3970 18:02:38.727135 DBI_RD = 0x0
3971 18:02:38.727236 OTF = 0x1
3972 18:02:38.730456 ===================================
3973 18:02:38.737061 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3974 18:02:38.741834 nWR fixed to 30
3975 18:02:38.745226 [ModeRegInit_LP4] CH0 RK0
3976 18:02:38.745307 [ModeRegInit_LP4] CH0 RK1
3977 18:02:38.748551 [ModeRegInit_LP4] CH1 RK0
3978 18:02:38.751664 [ModeRegInit_LP4] CH1 RK1
3979 18:02:38.751738 match AC timing 17
3980 18:02:38.758124 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3981 18:02:38.761350 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3982 18:02:38.764901 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3983 18:02:38.771362 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3984 18:02:38.775192 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3985 18:02:38.775296 ==
3986 18:02:38.778392 Dram Type= 6, Freq= 0, CH_0, rank 0
3987 18:02:38.781494 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3988 18:02:38.781599 ==
3989 18:02:38.788012 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3990 18:02:38.794858 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3991 18:02:38.798157 [CA 0] Center 36 (6~67) winsize 62
3992 18:02:38.801386 [CA 1] Center 36 (6~67) winsize 62
3993 18:02:38.804702 [CA 2] Center 34 (4~65) winsize 62
3994 18:02:38.807940 [CA 3] Center 34 (4~65) winsize 62
3995 18:02:38.811317 [CA 4] Center 33 (3~64) winsize 62
3996 18:02:38.814739 [CA 5] Center 33 (3~64) winsize 62
3997 18:02:38.814844
3998 18:02:38.818088 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3999 18:02:38.818159
4000 18:02:38.821364 [CATrainingPosCal] consider 1 rank data
4001 18:02:38.824701 u2DelayCellTimex100 = 270/100 ps
4002 18:02:38.879416 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
4003 18:02:38.879517 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
4004 18:02:38.879585 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4005 18:02:38.879658 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4006 18:02:38.879715 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4007 18:02:38.879787 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4008 18:02:38.879854
4009 18:02:38.879907 CA PerBit enable=1, Macro0, CA PI delay=33
4010 18:02:38.879959
4011 18:02:38.880027 [CBTSetCACLKResult] CA Dly = 33
4012 18:02:38.880093 CS Dly: 5 (0~36)
4013 18:02:38.880146 ==
4014 18:02:38.880199 Dram Type= 6, Freq= 0, CH_0, rank 1
4015 18:02:38.880268 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4016 18:02:38.880335 ==
4017 18:02:38.880386 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4018 18:02:38.880438 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4019 18:02:38.880490 [CA 0] Center 36 (6~67) winsize 62
4020 18:02:38.880791 [CA 1] Center 36 (6~67) winsize 62
4021 18:02:38.884012 [CA 2] Center 34 (4~65) winsize 62
4022 18:02:38.887493 [CA 3] Center 34 (4~65) winsize 62
4023 18:02:38.890802 [CA 4] Center 34 (3~65) winsize 63
4024 18:02:38.893891 [CA 5] Center 33 (3~64) winsize 62
4025 18:02:38.894013
4026 18:02:38.897104 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4027 18:02:38.897210
4028 18:02:38.900469 [CATrainingPosCal] consider 2 rank data
4029 18:02:38.903756 u2DelayCellTimex100 = 270/100 ps
4030 18:02:38.907519 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
4031 18:02:38.910781 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
4032 18:02:38.917235 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4033 18:02:38.920508 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4034 18:02:38.923684 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4035 18:02:38.927063 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4036 18:02:38.927144
4037 18:02:38.930246 CA PerBit enable=1, Macro0, CA PI delay=33
4038 18:02:38.930328
4039 18:02:38.933563 [CBTSetCACLKResult] CA Dly = 33
4040 18:02:38.933644 CS Dly: 5 (0~36)
4041 18:02:38.933708
4042 18:02:38.936835 ----->DramcWriteLeveling(PI) begin...
4043 18:02:38.940517 ==
4044 18:02:38.943603 Dram Type= 6, Freq= 0, CH_0, rank 0
4045 18:02:38.947177 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4046 18:02:38.947275 ==
4047 18:02:38.950570 Write leveling (Byte 0): 33 => 33
4048 18:02:38.953506 Write leveling (Byte 1): 30 => 30
4049 18:02:38.956785 DramcWriteLeveling(PI) end<-----
4050 18:02:38.956858
4051 18:02:38.956920 ==
4052 18:02:38.960053 Dram Type= 6, Freq= 0, CH_0, rank 0
4053 18:02:38.963810 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4054 18:02:38.963911 ==
4055 18:02:38.967104 [Gating] SW mode calibration
4056 18:02:38.973460 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4057 18:02:38.979921 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4058 18:02:38.983698 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4059 18:02:38.987019 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4060 18:02:38.990233 0 9 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
4061 18:02:38.996892 0 9 12 | B1->B0 | 3232 2d2d | 1 0 | (1 0) (1 0)
4062 18:02:38.999997 0 9 16 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
4063 18:02:39.003332 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4064 18:02:39.009911 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4065 18:02:39.013303 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4066 18:02:39.016535 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4067 18:02:39.023209 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4068 18:02:39.026844 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4069 18:02:39.030279 0 10 12 | B1->B0 | 2323 3636 | 0 0 | (0 0) (0 0)
4070 18:02:39.036907 0 10 16 | B1->B0 | 4141 4646 | 1 0 | (0 0) (0 0)
4071 18:02:39.039982 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4072 18:02:39.043289 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4073 18:02:39.049922 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4074 18:02:39.053169 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4075 18:02:39.056406 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4076 18:02:39.063334 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4077 18:02:39.066627 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4078 18:02:39.069981 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4079 18:02:39.076275 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4080 18:02:39.080001 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4081 18:02:39.083080 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4082 18:02:39.089740 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4083 18:02:39.092955 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4084 18:02:39.096163 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4085 18:02:39.103274 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4086 18:02:39.106444 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4087 18:02:39.109731 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4088 18:02:39.116242 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4089 18:02:39.119503 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4090 18:02:39.122838 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4091 18:02:39.129393 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4092 18:02:39.132658 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4093 18:02:39.136439 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4094 18:02:39.139645 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4095 18:02:39.142765 Total UI for P1: 0, mck2ui 16
4096 18:02:39.146116 best dqsien dly found for B0: ( 0, 13, 12)
4097 18:02:39.152426 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4098 18:02:39.156054 Total UI for P1: 0, mck2ui 16
4099 18:02:39.159368 best dqsien dly found for B1: ( 0, 13, 16)
4100 18:02:39.162321 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4101 18:02:39.165680 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4102 18:02:39.165802
4103 18:02:39.168906 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4104 18:02:39.172125 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4105 18:02:39.175903 [Gating] SW calibration Done
4106 18:02:39.176014 ==
4107 18:02:39.179191 Dram Type= 6, Freq= 0, CH_0, rank 0
4108 18:02:39.182258 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4109 18:02:39.182356 ==
4110 18:02:39.185662 RX Vref Scan: 0
4111 18:02:39.185776
4112 18:02:39.188915 RX Vref 0 -> 0, step: 1
4113 18:02:39.189019
4114 18:02:39.192143 RX Delay -230 -> 252, step: 16
4115 18:02:39.195502 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4116 18:02:39.199144 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4117 18:02:39.202523 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4118 18:02:39.205754 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4119 18:02:39.212434 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4120 18:02:39.215688 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4121 18:02:39.219289 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4122 18:02:39.222422 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4123 18:02:39.228790 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4124 18:02:39.232122 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4125 18:02:39.235305 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4126 18:02:39.238493 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4127 18:02:39.245471 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4128 18:02:39.248599 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4129 18:02:39.251960 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4130 18:02:39.255132 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4131 18:02:39.255217 ==
4132 18:02:39.258796 Dram Type= 6, Freq= 0, CH_0, rank 0
4133 18:02:39.265234 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4134 18:02:39.265320 ==
4135 18:02:39.265384 DQS Delay:
4136 18:02:39.268859 DQS0 = 0, DQS1 = 0
4137 18:02:39.268991 DQM Delay:
4138 18:02:39.269063 DQM0 = 50, DQM1 = 39
4139 18:02:39.271639 DQ Delay:
4140 18:02:39.275352 DQ0 =49, DQ1 =57, DQ2 =41, DQ3 =41
4141 18:02:39.278652 DQ4 =57, DQ5 =41, DQ6 =57, DQ7 =57
4142 18:02:39.281893 DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =33
4143 18:02:39.284930 DQ12 =41, DQ13 =41, DQ14 =57, DQ15 =41
4144 18:02:39.285042
4145 18:02:39.285132
4146 18:02:39.285213 ==
4147 18:02:39.288664 Dram Type= 6, Freq= 0, CH_0, rank 0
4148 18:02:39.291724 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4149 18:02:39.291820 ==
4150 18:02:39.291907
4151 18:02:39.291987
4152 18:02:39.294934 TX Vref Scan disable
4153 18:02:39.295024 == TX Byte 0 ==
4154 18:02:39.301554 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4155 18:02:39.305157 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4156 18:02:39.305257 == TX Byte 1 ==
4157 18:02:39.311819 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4158 18:02:39.314900 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4159 18:02:39.315025 ==
4160 18:02:39.318203 Dram Type= 6, Freq= 0, CH_0, rank 0
4161 18:02:39.321396 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4162 18:02:39.321514 ==
4163 18:02:39.324630
4164 18:02:39.324747
4165 18:02:39.324845 TX Vref Scan disable
4166 18:02:39.328330 == TX Byte 0 ==
4167 18:02:39.331991 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4168 18:02:39.338505 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4169 18:02:39.338634 == TX Byte 1 ==
4170 18:02:39.341685 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4171 18:02:39.348101 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4172 18:02:39.348223
4173 18:02:39.348319 [DATLAT]
4174 18:02:39.348415 Freq=600, CH0 RK0
4175 18:02:39.348507
4176 18:02:39.351521 DATLAT Default: 0x9
4177 18:02:39.351631 0, 0xFFFF, sum = 0
4178 18:02:39.354855 1, 0xFFFF, sum = 0
4179 18:02:39.354965 2, 0xFFFF, sum = 0
4180 18:02:39.358531 3, 0xFFFF, sum = 0
4181 18:02:39.361766 4, 0xFFFF, sum = 0
4182 18:02:39.361891 5, 0xFFFF, sum = 0
4183 18:02:39.364991 6, 0xFFFF, sum = 0
4184 18:02:39.365115 7, 0xFFFF, sum = 0
4185 18:02:39.368251 8, 0x0, sum = 1
4186 18:02:39.368360 9, 0x0, sum = 2
4187 18:02:39.368461 10, 0x0, sum = 3
4188 18:02:39.371429 11, 0x0, sum = 4
4189 18:02:39.371547 best_step = 9
4190 18:02:39.371641
4191 18:02:39.371736 ==
4192 18:02:39.375199 Dram Type= 6, Freq= 0, CH_0, rank 0
4193 18:02:39.381369 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4194 18:02:39.381519 ==
4195 18:02:39.381625 RX Vref Scan: 1
4196 18:02:39.381721
4197 18:02:39.384656 RX Vref 0 -> 0, step: 1
4198 18:02:39.384783
4199 18:02:39.388323 RX Delay -179 -> 252, step: 8
4200 18:02:39.388448
4201 18:02:39.391658 Set Vref, RX VrefLevel [Byte0]: 57
4202 18:02:39.394744 [Byte1]: 49
4203 18:02:39.394860
4204 18:02:39.398061 Final RX Vref Byte 0 = 57 to rank0
4205 18:02:39.401306 Final RX Vref Byte 1 = 49 to rank0
4206 18:02:39.404706 Final RX Vref Byte 0 = 57 to rank1
4207 18:02:39.407789 Final RX Vref Byte 1 = 49 to rank1==
4208 18:02:39.411095 Dram Type= 6, Freq= 0, CH_0, rank 0
4209 18:02:39.414373 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4210 18:02:39.414478 ==
4211 18:02:39.418185 DQS Delay:
4212 18:02:39.418298 DQS0 = 0, DQS1 = 0
4213 18:02:39.421442 DQM Delay:
4214 18:02:39.421557 DQM0 = 49, DQM1 = 37
4215 18:02:39.421656 DQ Delay:
4216 18:02:39.424601 DQ0 =48, DQ1 =48, DQ2 =48, DQ3 =48
4217 18:02:39.427839 DQ4 =48, DQ5 =40, DQ6 =56, DQ7 =60
4218 18:02:39.431226 DQ8 =32, DQ9 =24, DQ10 =36, DQ11 =32
4219 18:02:39.434377 DQ12 =44, DQ13 =40, DQ14 =48, DQ15 =44
4220 18:02:39.434491
4221 18:02:39.434588
4222 18:02:39.444432 [DQSOSCAuto] RK0, (LSB)MR18= 0x5c56, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 392 ps
4223 18:02:39.447743 CH0 RK0: MR19=808, MR18=5C56
4224 18:02:39.454407 CH0_RK0: MR19=0x808, MR18=0x5C56, DQSOSC=392, MR23=63, INC=170, DEC=113
4225 18:02:39.454520
4226 18:02:39.457611 ----->DramcWriteLeveling(PI) begin...
4227 18:02:39.457724 ==
4228 18:02:39.461395 Dram Type= 6, Freq= 0, CH_0, rank 1
4229 18:02:39.464529 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4230 18:02:39.464621 ==
4231 18:02:39.467591 Write leveling (Byte 0): 34 => 34
4232 18:02:39.470845 Write leveling (Byte 1): 29 => 29
4233 18:02:39.474548 DramcWriteLeveling(PI) end<-----
4234 18:02:39.474662
4235 18:02:39.474759 ==
4236 18:02:39.477932 Dram Type= 6, Freq= 0, CH_0, rank 1
4237 18:02:39.481290 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4238 18:02:39.481399 ==
4239 18:02:39.484560 [Gating] SW mode calibration
4240 18:02:39.490918 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4241 18:02:39.497478 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4242 18:02:39.500774 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4243 18:02:39.504018 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4244 18:02:39.511183 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4245 18:02:39.514401 0 9 12 | B1->B0 | 3232 3333 | 0 1 | (0 0) (1 0)
4246 18:02:39.517692 0 9 16 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
4247 18:02:39.524234 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4248 18:02:39.527296 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4249 18:02:39.530545 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4250 18:02:39.537548 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4251 18:02:39.540897 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4252 18:02:39.544186 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4253 18:02:39.550486 0 10 12 | B1->B0 | 2f2f 2e2e | 0 1 | (0 0) (0 0)
4254 18:02:39.553721 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4255 18:02:39.557057 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4256 18:02:39.564016 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4257 18:02:39.567294 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4258 18:02:39.570437 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4259 18:02:39.574046 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4260 18:02:39.580667 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4261 18:02:39.584003 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4262 18:02:39.586810 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4263 18:02:39.593873 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4264 18:02:39.597044 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4265 18:02:39.600282 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4266 18:02:39.606816 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4267 18:02:39.610214 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4268 18:02:39.613811 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4269 18:02:39.620495 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4270 18:02:39.623746 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4271 18:02:39.626973 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4272 18:02:39.633621 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4273 18:02:39.636798 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4274 18:02:39.640138 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4275 18:02:39.647018 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4276 18:02:39.650291 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4277 18:02:39.653482 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4278 18:02:39.659793 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4279 18:02:39.659880 Total UI for P1: 0, mck2ui 16
4280 18:02:39.666958 best dqsien dly found for B0: ( 0, 13, 12)
4281 18:02:39.667044 Total UI for P1: 0, mck2ui 16
4282 18:02:39.673450 best dqsien dly found for B1: ( 0, 13, 12)
4283 18:02:39.676913 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4284 18:02:39.680092 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4285 18:02:39.680216
4286 18:02:39.683332 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4287 18:02:39.686486 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4288 18:02:39.690080 [Gating] SW calibration Done
4289 18:02:39.690164 ==
4290 18:02:39.693353 Dram Type= 6, Freq= 0, CH_0, rank 1
4291 18:02:39.696516 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4292 18:02:39.696653 ==
4293 18:02:39.699833 RX Vref Scan: 0
4294 18:02:39.699914
4295 18:02:39.699978 RX Vref 0 -> 0, step: 1
4296 18:02:39.702832
4297 18:02:39.702908 RX Delay -230 -> 252, step: 16
4298 18:02:39.709791 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4299 18:02:39.712994 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4300 18:02:39.716332 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4301 18:02:39.719641 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4302 18:02:39.726091 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4303 18:02:39.729331 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4304 18:02:39.733121 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4305 18:02:39.736347 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4306 18:02:39.739613 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4307 18:02:39.746148 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4308 18:02:39.749422 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4309 18:02:39.752727 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4310 18:02:39.756419 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4311 18:02:39.763000 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4312 18:02:39.766224 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4313 18:02:39.769437 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4314 18:02:39.769511 ==
4315 18:02:39.772727 Dram Type= 6, Freq= 0, CH_0, rank 1
4316 18:02:39.776404 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4317 18:02:39.776486 ==
4318 18:02:39.779539 DQS Delay:
4319 18:02:39.779628 DQS0 = 0, DQS1 = 0
4320 18:02:39.782682 DQM Delay:
4321 18:02:39.782764 DQM0 = 48, DQM1 = 42
4322 18:02:39.782829 DQ Delay:
4323 18:02:39.786312 DQ0 =49, DQ1 =49, DQ2 =41, DQ3 =41
4324 18:02:39.789552 DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =57
4325 18:02:39.792780 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =41
4326 18:02:39.795914 DQ12 =41, DQ13 =49, DQ14 =49, DQ15 =49
4327 18:02:39.795990
4328 18:02:39.796060
4329 18:02:39.799179 ==
4330 18:02:39.802468 Dram Type= 6, Freq= 0, CH_0, rank 1
4331 18:02:39.806112 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4332 18:02:39.806194 ==
4333 18:02:39.806258
4334 18:02:39.806316
4335 18:02:39.809166 TX Vref Scan disable
4336 18:02:39.809243 == TX Byte 0 ==
4337 18:02:39.815768 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4338 18:02:39.819015 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4339 18:02:39.819097 == TX Byte 1 ==
4340 18:02:39.825801 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4341 18:02:39.828971 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4342 18:02:39.829048 ==
4343 18:02:39.832285 Dram Type= 6, Freq= 0, CH_0, rank 1
4344 18:02:39.835498 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4345 18:02:39.835580 ==
4346 18:02:39.835642
4347 18:02:39.835701
4348 18:02:39.839160 TX Vref Scan disable
4349 18:02:39.842286 == TX Byte 0 ==
4350 18:02:39.845574 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4351 18:02:39.848829 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4352 18:02:39.852469 == TX Byte 1 ==
4353 18:02:39.855194 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4354 18:02:39.862418 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4355 18:02:39.862502
4356 18:02:39.862566 [DATLAT]
4357 18:02:39.862625 Freq=600, CH0 RK1
4358 18:02:39.862683
4359 18:02:39.865661 DATLAT Default: 0x9
4360 18:02:39.865748 0, 0xFFFF, sum = 0
4361 18:02:39.868796 1, 0xFFFF, sum = 0
4362 18:02:39.868876 2, 0xFFFF, sum = 0
4363 18:02:39.872172 3, 0xFFFF, sum = 0
4364 18:02:39.875415 4, 0xFFFF, sum = 0
4365 18:02:39.875491 5, 0xFFFF, sum = 0
4366 18:02:39.878473 6, 0xFFFF, sum = 0
4367 18:02:39.878549 7, 0xFFFF, sum = 0
4368 18:02:39.878619 8, 0x0, sum = 1
4369 18:02:39.882133 9, 0x0, sum = 2
4370 18:02:39.882246 10, 0x0, sum = 3
4371 18:02:39.885416 11, 0x0, sum = 4
4372 18:02:39.885525 best_step = 9
4373 18:02:39.885615
4374 18:02:39.885702 ==
4375 18:02:39.888658 Dram Type= 6, Freq= 0, CH_0, rank 1
4376 18:02:39.895509 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4377 18:02:39.895618 ==
4378 18:02:39.895709 RX Vref Scan: 0
4379 18:02:39.895796
4380 18:02:39.898801 RX Vref 0 -> 0, step: 1
4381 18:02:39.898881
4382 18:02:39.902206 RX Delay -163 -> 252, step: 8
4383 18:02:39.905262 iDelay=205, Bit 0, Center 48 (-99 ~ 196) 296
4384 18:02:39.908662 iDelay=205, Bit 1, Center 52 (-91 ~ 196) 288
4385 18:02:39.915546 iDelay=205, Bit 2, Center 44 (-99 ~ 188) 288
4386 18:02:39.918723 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4387 18:02:39.922073 iDelay=205, Bit 4, Center 52 (-91 ~ 196) 288
4388 18:02:39.925455 iDelay=205, Bit 5, Center 40 (-107 ~ 188) 296
4389 18:02:39.931902 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4390 18:02:39.935317 iDelay=205, Bit 7, Center 52 (-91 ~ 196) 288
4391 18:02:39.938452 iDelay=205, Bit 8, Center 36 (-107 ~ 180) 288
4392 18:02:39.941704 iDelay=205, Bit 9, Center 28 (-115 ~ 172) 288
4393 18:02:39.944756 iDelay=205, Bit 10, Center 40 (-107 ~ 188) 296
4394 18:02:39.951843 iDelay=205, Bit 11, Center 36 (-107 ~ 180) 288
4395 18:02:39.955008 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4396 18:02:39.958221 iDelay=205, Bit 13, Center 44 (-99 ~ 188) 288
4397 18:02:39.961869 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4398 18:02:39.968406 iDelay=205, Bit 15, Center 48 (-91 ~ 188) 280
4399 18:02:39.968513 ==
4400 18:02:39.971667 Dram Type= 6, Freq= 0, CH_0, rank 1
4401 18:02:39.974921 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4402 18:02:39.975004 ==
4403 18:02:39.975067 DQS Delay:
4404 18:02:39.978211 DQS0 = 0, DQS1 = 0
4405 18:02:39.978317 DQM Delay:
4406 18:02:39.981524 DQM0 = 49, DQM1 = 41
4407 18:02:39.981604 DQ Delay:
4408 18:02:39.984690 DQ0 =48, DQ1 =52, DQ2 =44, DQ3 =44
4409 18:02:39.988459 DQ4 =52, DQ5 =40, DQ6 =60, DQ7 =52
4410 18:02:39.991529 DQ8 =36, DQ9 =28, DQ10 =40, DQ11 =36
4411 18:02:39.994798 DQ12 =48, DQ13 =44, DQ14 =52, DQ15 =48
4412 18:02:39.994871
4413 18:02:39.994932
4414 18:02:40.001577 [DQSOSCAuto] RK1, (LSB)MR18= 0x5b29, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 392 ps
4415 18:02:40.004945 CH0 RK1: MR19=808, MR18=5B29
4416 18:02:40.011543 CH0_RK1: MR19=0x808, MR18=0x5B29, DQSOSC=392, MR23=63, INC=170, DEC=113
4417 18:02:40.014749 [RxdqsGatingPostProcess] freq 600
4418 18:02:40.021640 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4419 18:02:40.021739 Pre-setting of DQS Precalculation
4420 18:02:40.028186 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4421 18:02:40.028276 ==
4422 18:02:40.031720 Dram Type= 6, Freq= 0, CH_1, rank 0
4423 18:02:40.034720 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4424 18:02:40.034858 ==
4425 18:02:40.041489 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4426 18:02:40.048398 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4427 18:02:40.051562 [CA 0] Center 35 (5~66) winsize 62
4428 18:02:40.054823 [CA 1] Center 35 (5~66) winsize 62
4429 18:02:40.058065 [CA 2] Center 34 (4~65) winsize 62
4430 18:02:40.061739 [CA 3] Center 33 (3~64) winsize 62
4431 18:02:40.064957 [CA 4] Center 34 (3~65) winsize 63
4432 18:02:40.068298 [CA 5] Center 33 (3~64) winsize 62
4433 18:02:40.068381
4434 18:02:40.071518 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4435 18:02:40.071600
4436 18:02:40.074792 [CATrainingPosCal] consider 1 rank data
4437 18:02:40.078186 u2DelayCellTimex100 = 270/100 ps
4438 18:02:40.081343 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4439 18:02:40.084446 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4440 18:02:40.087767 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4441 18:02:40.091161 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4442 18:02:40.094792 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4443 18:02:40.097959 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4444 18:02:40.098052
4445 18:02:40.104712 CA PerBit enable=1, Macro0, CA PI delay=33
4446 18:02:40.104793
4447 18:02:40.108075 [CBTSetCACLKResult] CA Dly = 33
4448 18:02:40.108149 CS Dly: 3 (0~34)
4449 18:02:40.108210 ==
4450 18:02:40.111355 Dram Type= 6, Freq= 0, CH_1, rank 1
4451 18:02:40.114850 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4452 18:02:40.114946 ==
4453 18:02:40.121315 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4454 18:02:40.127884 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4455 18:02:40.131183 [CA 0] Center 35 (5~66) winsize 62
4456 18:02:40.134474 [CA 1] Center 35 (5~66) winsize 62
4457 18:02:40.138231 [CA 2] Center 34 (4~65) winsize 62
4458 18:02:40.140947 [CA 3] Center 34 (4~65) winsize 62
4459 18:02:40.144220 [CA 4] Center 34 (4~65) winsize 62
4460 18:02:40.147981 [CA 5] Center 34 (4~65) winsize 62
4461 18:02:40.148070
4462 18:02:40.151443 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4463 18:02:40.151516
4464 18:02:40.154672 [CATrainingPosCal] consider 2 rank data
4465 18:02:40.157572 u2DelayCellTimex100 = 270/100 ps
4466 18:02:40.161428 CA0 delay=35 (5~66),Diff = 1 PI (9 cell)
4467 18:02:40.164655 CA1 delay=35 (5~66),Diff = 1 PI (9 cell)
4468 18:02:40.167997 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4469 18:02:40.171416 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
4470 18:02:40.174795 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4471 18:02:40.177969 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4472 18:02:40.181287
4473 18:02:40.184433 CA PerBit enable=1, Macro0, CA PI delay=34
4474 18:02:40.184568
4475 18:02:40.187921 [CBTSetCACLKResult] CA Dly = 34
4476 18:02:40.188013 CS Dly: 4 (0~37)
4477 18:02:40.188090
4478 18:02:40.191155 ----->DramcWriteLeveling(PI) begin...
4479 18:02:40.191264 ==
4480 18:02:40.194326 Dram Type= 6, Freq= 0, CH_1, rank 0
4481 18:02:40.197521 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4482 18:02:40.200909 ==
4483 18:02:40.200986 Write leveling (Byte 0): 29 => 29
4484 18:02:40.204175 Write leveling (Byte 1): 32 => 32
4485 18:02:40.207879 DramcWriteLeveling(PI) end<-----
4486 18:02:40.207955
4487 18:02:40.208034 ==
4488 18:02:40.211042 Dram Type= 6, Freq= 0, CH_1, rank 0
4489 18:02:40.217548 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4490 18:02:40.217650 ==
4491 18:02:40.217760 [Gating] SW mode calibration
4492 18:02:40.227889 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4493 18:02:40.231056 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4494 18:02:40.237190 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4495 18:02:40.240873 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4496 18:02:40.244184 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4497 18:02:40.247510 0 9 12 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
4498 18:02:40.254063 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4499 18:02:40.257233 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4500 18:02:40.260463 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4501 18:02:40.267256 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4502 18:02:40.270428 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4503 18:02:40.273741 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4504 18:02:40.280252 0 10 8 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
4505 18:02:40.283564 0 10 12 | B1->B0 | 3939 3a3a | 0 0 | (0 0) (0 0)
4506 18:02:40.287252 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4507 18:02:40.293759 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4508 18:02:40.297094 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4509 18:02:40.300329 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4510 18:02:40.306705 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4511 18:02:40.310374 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4512 18:02:40.313820 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4513 18:02:40.320204 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4514 18:02:40.323554 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4515 18:02:40.326751 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4516 18:02:40.333637 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4517 18:02:40.336863 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4518 18:02:40.340009 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4519 18:02:40.347087 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4520 18:02:40.350449 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4521 18:02:40.353042 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4522 18:02:40.360212 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4523 18:02:40.363067 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4524 18:02:40.366564 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4525 18:02:40.373362 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4526 18:02:40.376552 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4527 18:02:40.379753 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4528 18:02:40.386495 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4529 18:02:40.389737 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4530 18:02:40.393009 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4531 18:02:40.396051 Total UI for P1: 0, mck2ui 16
4532 18:02:40.399383 best dqsien dly found for B0: ( 0, 13, 12)
4533 18:02:40.403081 Total UI for P1: 0, mck2ui 16
4534 18:02:40.406290 best dqsien dly found for B1: ( 0, 13, 12)
4535 18:02:40.409549 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4536 18:02:40.412687 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4537 18:02:40.412873
4538 18:02:40.419237 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4539 18:02:40.422934 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4540 18:02:40.426421 [Gating] SW calibration Done
4541 18:02:40.426764 ==
4542 18:02:40.429632 Dram Type= 6, Freq= 0, CH_1, rank 0
4543 18:02:40.432696 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4544 18:02:40.433154 ==
4545 18:02:40.433503 RX Vref Scan: 0
4546 18:02:40.433842
4547 18:02:40.436494 RX Vref 0 -> 0, step: 1
4548 18:02:40.437163
4549 18:02:40.439694 RX Delay -230 -> 252, step: 16
4550 18:02:40.442933 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4551 18:02:40.446047 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4552 18:02:40.452367 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4553 18:02:40.455412 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4554 18:02:40.458643 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4555 18:02:40.462414 iDelay=218, Bit 5, Center 57 (-86 ~ 201) 288
4556 18:02:40.468947 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4557 18:02:40.471961 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4558 18:02:40.475656 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4559 18:02:40.478834 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4560 18:02:40.485160 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4561 18:02:40.488355 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4562 18:02:40.492227 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4563 18:02:40.495475 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4564 18:02:40.501622 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4565 18:02:40.505009 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4566 18:02:40.505088 ==
4567 18:02:40.508315 Dram Type= 6, Freq= 0, CH_1, rank 0
4568 18:02:40.511953 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4569 18:02:40.512033 ==
4570 18:02:40.515320 DQS Delay:
4571 18:02:40.515394 DQS0 = 0, DQS1 = 0
4572 18:02:40.515455 DQM Delay:
4573 18:02:40.518466 DQM0 = 49, DQM1 = 40
4574 18:02:40.518543 DQ Delay:
4575 18:02:40.521538 DQ0 =49, DQ1 =49, DQ2 =33, DQ3 =49
4576 18:02:40.525208 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49
4577 18:02:40.528456 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =41
4578 18:02:40.531710 DQ12 =57, DQ13 =49, DQ14 =41, DQ15 =41
4579 18:02:40.531786
4580 18:02:40.531850
4581 18:02:40.531908 ==
4582 18:02:40.534964 Dram Type= 6, Freq= 0, CH_1, rank 0
4583 18:02:40.541413 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4584 18:02:40.541492 ==
4585 18:02:40.541557
4586 18:02:40.541615
4587 18:02:40.541673 TX Vref Scan disable
4588 18:02:40.545345 == TX Byte 0 ==
4589 18:02:40.548603 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4590 18:02:40.555260 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4591 18:02:40.555347 == TX Byte 1 ==
4592 18:02:40.558526 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4593 18:02:40.565009 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4594 18:02:40.565095 ==
4595 18:02:40.568279 Dram Type= 6, Freq= 0, CH_1, rank 0
4596 18:02:40.571613 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4597 18:02:40.571700 ==
4598 18:02:40.571776
4599 18:02:40.571877
4600 18:02:40.574780 TX Vref Scan disable
4601 18:02:40.578129 == TX Byte 0 ==
4602 18:02:40.581339 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4603 18:02:40.584711 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4604 18:02:40.587993 == TX Byte 1 ==
4605 18:02:40.591289 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4606 18:02:40.594583 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4607 18:02:40.594666
4608 18:02:40.594731 [DATLAT]
4609 18:02:40.597907 Freq=600, CH1 RK0
4610 18:02:40.597989
4611 18:02:40.601251 DATLAT Default: 0x9
4612 18:02:40.601357 0, 0xFFFF, sum = 0
4613 18:02:40.604457 1, 0xFFFF, sum = 0
4614 18:02:40.604589 2, 0xFFFF, sum = 0
4615 18:02:40.607887 3, 0xFFFF, sum = 0
4616 18:02:40.607971 4, 0xFFFF, sum = 0
4617 18:02:40.611233 5, 0xFFFF, sum = 0
4618 18:02:40.611317 6, 0xFFFF, sum = 0
4619 18:02:40.614364 7, 0xFFFF, sum = 0
4620 18:02:40.614448 8, 0x0, sum = 1
4621 18:02:40.617881 9, 0x0, sum = 2
4622 18:02:40.617965 10, 0x0, sum = 3
4623 18:02:40.621245 11, 0x0, sum = 4
4624 18:02:40.621345 best_step = 9
4625 18:02:40.621416
4626 18:02:40.621477 ==
4627 18:02:40.624389 Dram Type= 6, Freq= 0, CH_1, rank 0
4628 18:02:40.627921 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4629 18:02:40.628004 ==
4630 18:02:40.631301 RX Vref Scan: 1
4631 18:02:40.631401
4632 18:02:40.634536 RX Vref 0 -> 0, step: 1
4633 18:02:40.634621
4634 18:02:40.634688 RX Delay -179 -> 252, step: 8
4635 18:02:40.634750
4636 18:02:40.637846 Set Vref, RX VrefLevel [Byte0]: 53
4637 18:02:40.641006 [Byte1]: 52
4638 18:02:40.645418
4639 18:02:40.645533 Final RX Vref Byte 0 = 53 to rank0
4640 18:02:40.649146 Final RX Vref Byte 1 = 52 to rank0
4641 18:02:40.652482 Final RX Vref Byte 0 = 53 to rank1
4642 18:02:40.655748 Final RX Vref Byte 1 = 52 to rank1==
4643 18:02:40.659162 Dram Type= 6, Freq= 0, CH_1, rank 0
4644 18:02:40.665594 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4645 18:02:40.665678 ==
4646 18:02:40.665744 DQS Delay:
4647 18:02:40.665804 DQS0 = 0, DQS1 = 0
4648 18:02:40.668788 DQM Delay:
4649 18:02:40.668870 DQM0 = 47, DQM1 = 40
4650 18:02:40.672164 DQ Delay:
4651 18:02:40.675912 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4652 18:02:40.675998 DQ4 =44, DQ5 =60, DQ6 =56, DQ7 =44
4653 18:02:40.679162 DQ8 =28, DQ9 =28, DQ10 =44, DQ11 =32
4654 18:02:40.685609 DQ12 =48, DQ13 =48, DQ14 =44, DQ15 =48
4655 18:02:40.685744
4656 18:02:40.685869
4657 18:02:40.692086 [DQSOSCAuto] RK0, (LSB)MR18= 0x476e, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
4658 18:02:40.695589 CH1 RK0: MR19=808, MR18=476E
4659 18:02:40.758731 CH1_RK0: MR19=0x808, MR18=0x476E, DQSOSC=389, MR23=63, INC=173, DEC=115
4660 18:02:40.758872
4661 18:02:40.758947 ----->DramcWriteLeveling(PI) begin...
4662 18:02:40.759013 ==
4663 18:02:40.759074 Dram Type= 6, Freq= 0, CH_1, rank 1
4664 18:02:40.759134 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4665 18:02:40.759210 ==
4666 18:02:40.759302 Write leveling (Byte 0): 29 => 29
4667 18:02:40.759393 Write leveling (Byte 1): 30 => 30
4668 18:02:40.759485 DramcWriteLeveling(PI) end<-----
4669 18:02:40.759571
4670 18:02:40.759656 ==
4671 18:02:40.759743 Dram Type= 6, Freq= 0, CH_1, rank 1
4672 18:02:40.759831 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4673 18:02:40.759919 ==
4674 18:02:40.760005 [Gating] SW mode calibration
4675 18:02:40.760105 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4676 18:02:40.760200 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4677 18:02:40.760289 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4678 18:02:40.760378 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4679 18:02:40.760465 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4680 18:02:40.761526 0 9 12 | B1->B0 | 2c2c 2f2f | 0 1 | (1 0) (0 0)
4681 18:02:40.768432 0 9 16 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4682 18:02:40.771644 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4683 18:02:40.774918 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4684 18:02:40.778710 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4685 18:02:40.785149 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4686 18:02:40.788406 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4687 18:02:40.791919 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4688 18:02:40.798522 0 10 12 | B1->B0 | 3838 2626 | 0 1 | (0 0) (0 0)
4689 18:02:40.801858 0 10 16 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
4690 18:02:40.805206 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4691 18:02:40.811649 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4692 18:02:40.814966 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4693 18:02:40.818280 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4694 18:02:40.824630 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4695 18:02:40.828383 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4696 18:02:40.831573 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4697 18:02:40.838074 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4698 18:02:40.841400 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4699 18:02:40.844690 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4700 18:02:40.850994 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4701 18:02:40.854728 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4702 18:02:40.857924 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4703 18:02:40.864567 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4704 18:02:40.867781 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4705 18:02:40.871391 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4706 18:02:40.877922 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4707 18:02:40.881026 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4708 18:02:40.884407 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4709 18:02:40.890899 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4710 18:02:40.894624 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4711 18:02:40.897809 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4712 18:02:40.904332 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4713 18:02:40.907640 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4714 18:02:40.911001 Total UI for P1: 0, mck2ui 16
4715 18:02:40.914397 best dqsien dly found for B0: ( 0, 13, 12)
4716 18:02:40.917762 Total UI for P1: 0, mck2ui 16
4717 18:02:40.920900 best dqsien dly found for B1: ( 0, 13, 12)
4718 18:02:40.924195 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4719 18:02:40.927387 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4720 18:02:40.927534
4721 18:02:40.930920 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4722 18:02:40.933928 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4723 18:02:40.937570 [Gating] SW calibration Done
4724 18:02:40.937662 ==
4725 18:02:40.940708 Dram Type= 6, Freq= 0, CH_1, rank 1
4726 18:02:40.944136 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4727 18:02:40.944243 ==
4728 18:02:40.947392 RX Vref Scan: 0
4729 18:02:40.947492
4730 18:02:40.950643 RX Vref 0 -> 0, step: 1
4731 18:02:40.950742
4732 18:02:40.954417 RX Delay -230 -> 252, step: 16
4733 18:02:40.957531 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4734 18:02:40.961057 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4735 18:02:40.964331 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4736 18:02:40.967608 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4737 18:02:40.974159 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4738 18:02:40.977543 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4739 18:02:40.980857 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4740 18:02:40.984066 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4741 18:02:40.987385 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4742 18:02:40.994070 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4743 18:02:40.997249 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4744 18:02:41.000506 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4745 18:02:41.004239 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4746 18:02:41.010715 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4747 18:02:41.014006 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4748 18:02:41.017332 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4749 18:02:41.017440 ==
4750 18:02:41.020679 Dram Type= 6, Freq= 0, CH_1, rank 1
4751 18:02:41.024047 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4752 18:02:41.027246 ==
4753 18:02:41.027348 DQS Delay:
4754 18:02:41.027439 DQS0 = 0, DQS1 = 0
4755 18:02:41.031029 DQM Delay:
4756 18:02:41.031136 DQM0 = 52, DQM1 = 46
4757 18:02:41.034105 DQ Delay:
4758 18:02:41.034214 DQ0 =57, DQ1 =49, DQ2 =33, DQ3 =49
4759 18:02:41.037334 DQ4 =49, DQ5 =65, DQ6 =65, DQ7 =49
4760 18:02:41.040506 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =41
4761 18:02:41.044320 DQ12 =57, DQ13 =49, DQ14 =57, DQ15 =57
4762 18:02:41.044428
4763 18:02:41.047457
4764 18:02:41.047556 ==
4765 18:02:41.050739 Dram Type= 6, Freq= 0, CH_1, rank 1
4766 18:02:41.054081 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4767 18:02:41.054190 ==
4768 18:02:41.054284
4769 18:02:41.054375
4770 18:02:41.057153 TX Vref Scan disable
4771 18:02:41.057267 == TX Byte 0 ==
4772 18:02:41.064111 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4773 18:02:41.067214 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4774 18:02:41.067320 == TX Byte 1 ==
4775 18:02:41.073696 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4776 18:02:41.076929 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4777 18:02:41.077037 ==
4778 18:02:41.080183 Dram Type= 6, Freq= 0, CH_1, rank 1
4779 18:02:41.083486 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4780 18:02:41.083594 ==
4781 18:02:41.083686
4782 18:02:41.083813
4783 18:02:41.086829 TX Vref Scan disable
4784 18:02:41.090558 == TX Byte 0 ==
4785 18:02:41.093754 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4786 18:02:41.097008 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4787 18:02:41.100322 == TX Byte 1 ==
4788 18:02:41.103472 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4789 18:02:41.106704 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4790 18:02:41.106812
4791 18:02:41.110484 [DATLAT]
4792 18:02:41.110586 Freq=600, CH1 RK1
4793 18:02:41.110680
4794 18:02:41.113711 DATLAT Default: 0x9
4795 18:02:41.113793 0, 0xFFFF, sum = 0
4796 18:02:41.116889 1, 0xFFFF, sum = 0
4797 18:02:41.116972 2, 0xFFFF, sum = 0
4798 18:02:41.120189 3, 0xFFFF, sum = 0
4799 18:02:41.120272 4, 0xFFFF, sum = 0
4800 18:02:41.123483 5, 0xFFFF, sum = 0
4801 18:02:41.123567 6, 0xFFFF, sum = 0
4802 18:02:41.126744 7, 0xFFFF, sum = 0
4803 18:02:41.126828 8, 0x0, sum = 1
4804 18:02:41.129997 9, 0x0, sum = 2
4805 18:02:41.130081 10, 0x0, sum = 3
4806 18:02:41.133363 11, 0x0, sum = 4
4807 18:02:41.133446 best_step = 9
4808 18:02:41.133511
4809 18:02:41.133571 ==
4810 18:02:41.137151 Dram Type= 6, Freq= 0, CH_1, rank 1
4811 18:02:41.143689 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4812 18:02:41.143796 ==
4813 18:02:41.143890 RX Vref Scan: 0
4814 18:02:41.143951
4815 18:02:41.146797 RX Vref 0 -> 0, step: 1
4816 18:02:41.146892
4817 18:02:41.150482 RX Delay -163 -> 252, step: 8
4818 18:02:41.153834 iDelay=205, Bit 0, Center 56 (-83 ~ 196) 280
4819 18:02:41.156527 iDelay=205, Bit 1, Center 40 (-99 ~ 180) 280
4820 18:02:41.163279 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4821 18:02:41.166956 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4822 18:02:41.170173 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4823 18:02:41.173289 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4824 18:02:41.176474 iDelay=205, Bit 6, Center 52 (-91 ~ 196) 288
4825 18:02:41.183054 iDelay=205, Bit 7, Center 44 (-99 ~ 188) 288
4826 18:02:41.186798 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4827 18:02:41.189781 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4828 18:02:41.192965 iDelay=205, Bit 10, Center 40 (-107 ~ 188) 296
4829 18:02:41.200040 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4830 18:02:41.203346 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4831 18:02:41.206655 iDelay=205, Bit 13, Center 48 (-99 ~ 196) 296
4832 18:02:41.209792 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4833 18:02:41.213208 iDelay=205, Bit 15, Center 52 (-99 ~ 204) 304
4834 18:02:41.216404 ==
4835 18:02:41.219808 Dram Type= 6, Freq= 0, CH_1, rank 1
4836 18:02:41.223142 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4837 18:02:41.223267 ==
4838 18:02:41.223364 DQS Delay:
4839 18:02:41.226381 DQS0 = 0, DQS1 = 0
4840 18:02:41.226508 DQM Delay:
4841 18:02:41.229604 DQM0 = 47, DQM1 = 42
4842 18:02:41.229699 DQ Delay:
4843 18:02:41.232842 DQ0 =56, DQ1 =40, DQ2 =36, DQ3 =44
4844 18:02:41.236143 DQ4 =48, DQ5 =60, DQ6 =52, DQ7 =44
4845 18:02:41.239324 DQ8 =32, DQ9 =32, DQ10 =40, DQ11 =40
4846 18:02:41.243033 DQ12 =48, DQ13 =48, DQ14 =48, DQ15 =52
4847 18:02:41.243156
4848 18:02:41.243254
4849 18:02:41.249706 [DQSOSCAuto] RK1, (LSB)MR18= 0x561e, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 393 ps
4850 18:02:41.252800 CH1 RK1: MR19=808, MR18=561E
4851 18:02:41.259489 CH1_RK1: MR19=0x808, MR18=0x561E, DQSOSC=393, MR23=63, INC=169, DEC=113
4852 18:02:41.262639 [RxdqsGatingPostProcess] freq 600
4853 18:02:41.269626 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4854 18:02:41.269711 Pre-setting of DQS Precalculation
4855 18:02:41.276007 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4856 18:02:41.282465 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4857 18:02:41.289475 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4858 18:02:41.289559
4859 18:02:41.289625
4860 18:02:41.292631 [Calibration Summary] 1200 Mbps
4861 18:02:41.296007 CH 0, Rank 0
4862 18:02:41.296113 SW Impedance : PASS
4863 18:02:41.299324 DUTY Scan : NO K
4864 18:02:41.302567 ZQ Calibration : PASS
4865 18:02:41.302680 Jitter Meter : NO K
4866 18:02:41.305943 CBT Training : PASS
4867 18:02:41.306025 Write leveling : PASS
4868 18:02:41.309026 RX DQS gating : PASS
4869 18:02:41.312677 RX DQ/DQS(RDDQC) : PASS
4870 18:02:41.312769 TX DQ/DQS : PASS
4871 18:02:41.315846 RX DATLAT : PASS
4872 18:02:41.319152 RX DQ/DQS(Engine): PASS
4873 18:02:41.319234 TX OE : NO K
4874 18:02:41.322530 All Pass.
4875 18:02:41.322612
4876 18:02:41.322676 CH 0, Rank 1
4877 18:02:41.325867 SW Impedance : PASS
4878 18:02:41.325948 DUTY Scan : NO K
4879 18:02:41.329058 ZQ Calibration : PASS
4880 18:02:41.332279 Jitter Meter : NO K
4881 18:02:41.332360 CBT Training : PASS
4882 18:02:41.335675 Write leveling : PASS
4883 18:02:41.338914 RX DQS gating : PASS
4884 18:02:41.338995 RX DQ/DQS(RDDQC) : PASS
4885 18:02:41.342205 TX DQ/DQS : PASS
4886 18:02:41.345563 RX DATLAT : PASS
4887 18:02:41.345656 RX DQ/DQS(Engine): PASS
4888 18:02:41.349148 TX OE : NO K
4889 18:02:41.349230 All Pass.
4890 18:02:41.349300
4891 18:02:41.352513 CH 1, Rank 0
4892 18:02:41.352640 SW Impedance : PASS
4893 18:02:41.355502 DUTY Scan : NO K
4894 18:02:41.358806 ZQ Calibration : PASS
4895 18:02:41.358882 Jitter Meter : NO K
4896 18:02:41.362109 CBT Training : PASS
4897 18:02:41.365549 Write leveling : PASS
4898 18:02:41.365623 RX DQS gating : PASS
4899 18:02:41.368780 RX DQ/DQS(RDDQC) : PASS
4900 18:02:41.368855 TX DQ/DQS : PASS
4901 18:02:41.371959 RX DATLAT : PASS
4902 18:02:41.375248 RX DQ/DQS(Engine): PASS
4903 18:02:41.375338 TX OE : NO K
4904 18:02:41.378890 All Pass.
4905 18:02:41.378968
4906 18:02:41.379033 CH 1, Rank 1
4907 18:02:41.382093 SW Impedance : PASS
4908 18:02:41.382183 DUTY Scan : NO K
4909 18:02:41.385217 ZQ Calibration : PASS
4910 18:02:41.388667 Jitter Meter : NO K
4911 18:02:41.388766 CBT Training : PASS
4912 18:02:41.391970 Write leveling : PASS
4913 18:02:41.395195 RX DQS gating : PASS
4914 18:02:41.395275 RX DQ/DQS(RDDQC) : PASS
4915 18:02:41.398538 TX DQ/DQS : PASS
4916 18:02:41.401768 RX DATLAT : PASS
4917 18:02:41.401852 RX DQ/DQS(Engine): PASS
4918 18:02:41.405165 TX OE : NO K
4919 18:02:41.405277 All Pass.
4920 18:02:41.405342
4921 18:02:41.408430 DramC Write-DBI off
4922 18:02:41.412163 PER_BANK_REFRESH: Hybrid Mode
4923 18:02:41.412239 TX_TRACKING: ON
4924 18:02:41.422216 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4925 18:02:41.425459 [FAST_K] Save calibration result to emmc
4926 18:02:41.428654 dramc_set_vcore_voltage set vcore to 662500
4927 18:02:41.431955 Read voltage for 933, 3
4928 18:02:41.432052 Vio18 = 0
4929 18:02:41.432142 Vcore = 662500
4930 18:02:41.435222 Vdram = 0
4931 18:02:41.435313 Vddq = 0
4932 18:02:41.435390 Vmddr = 0
4933 18:02:41.442028 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4934 18:02:41.445279 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4935 18:02:41.448124 MEM_TYPE=3, freq_sel=17
4936 18:02:41.451687 sv_algorithm_assistance_LP4_1600
4937 18:02:41.454901 ============ PULL DRAM RESETB DOWN ============
4938 18:02:41.458550 ========== PULL DRAM RESETB DOWN end =========
4939 18:02:41.464723 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4940 18:02:41.468523 ===================================
4941 18:02:41.468621 LPDDR4 DRAM CONFIGURATION
4942 18:02:41.471712 ===================================
4943 18:02:41.475017 EX_ROW_EN[0] = 0x0
4944 18:02:41.478234 EX_ROW_EN[1] = 0x0
4945 18:02:41.478308 LP4Y_EN = 0x0
4946 18:02:41.481295 WORK_FSP = 0x0
4947 18:02:41.481414 WL = 0x3
4948 18:02:41.484512 RL = 0x3
4949 18:02:41.484628 BL = 0x2
4950 18:02:41.488233 RPST = 0x0
4951 18:02:41.488339 RD_PRE = 0x0
4952 18:02:41.491203 WR_PRE = 0x1
4953 18:02:41.491303 WR_PST = 0x0
4954 18:02:41.494447 DBI_WR = 0x0
4955 18:02:41.494556 DBI_RD = 0x0
4956 18:02:41.497723 OTF = 0x1
4957 18:02:41.501461 ===================================
4958 18:02:41.504612 ===================================
4959 18:02:41.504696 ANA top config
4960 18:02:41.507916 ===================================
4961 18:02:41.511251 DLL_ASYNC_EN = 0
4962 18:02:41.514445 ALL_SLAVE_EN = 1
4963 18:02:41.517592 NEW_RANK_MODE = 1
4964 18:02:41.517706 DLL_IDLE_MODE = 1
4965 18:02:41.521378 LP45_APHY_COMB_EN = 1
4966 18:02:41.524601 TX_ODT_DIS = 1
4967 18:02:41.527943 NEW_8X_MODE = 1
4968 18:02:41.531274 ===================================
4969 18:02:41.534539 ===================================
4970 18:02:41.537767 data_rate = 1866
4971 18:02:41.537850 CKR = 1
4972 18:02:41.541050 DQ_P2S_RATIO = 8
4973 18:02:41.544624 ===================================
4974 18:02:41.548055 CA_P2S_RATIO = 8
4975 18:02:41.550908 DQ_CA_OPEN = 0
4976 18:02:41.554710 DQ_SEMI_OPEN = 0
4977 18:02:41.557677 CA_SEMI_OPEN = 0
4978 18:02:41.557788 CA_FULL_RATE = 0
4979 18:02:41.560846 DQ_CKDIV4_EN = 1
4980 18:02:41.564124 CA_CKDIV4_EN = 1
4981 18:02:41.568148 CA_PREDIV_EN = 0
4982 18:02:41.571370 PH8_DLY = 0
4983 18:02:41.574691 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4984 18:02:41.574769 DQ_AAMCK_DIV = 4
4985 18:02:41.577517 CA_AAMCK_DIV = 4
4986 18:02:41.581236 CA_ADMCK_DIV = 4
4987 18:02:41.584349 DQ_TRACK_CA_EN = 0
4988 18:02:41.587735 CA_PICK = 933
4989 18:02:41.590922 CA_MCKIO = 933
4990 18:02:41.591029 MCKIO_SEMI = 0
4991 18:02:41.594566 PLL_FREQ = 3732
4992 18:02:41.597678 DQ_UI_PI_RATIO = 32
4993 18:02:41.600994 CA_UI_PI_RATIO = 0
4994 18:02:41.604279 ===================================
4995 18:02:41.607506 ===================================
4996 18:02:41.610755 memory_type:LPDDR4
4997 18:02:41.610840 GP_NUM : 10
4998 18:02:41.614207 SRAM_EN : 1
4999 18:02:41.617461 MD32_EN : 0
5000 18:02:41.620702 ===================================
5001 18:02:41.620787 [ANA_INIT] >>>>>>>>>>>>>>
5002 18:02:41.624336 <<<<<< [CONFIGURE PHASE]: ANA_TX
5003 18:02:41.627579 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5004 18:02:41.631009 ===================================
5005 18:02:41.634366 data_rate = 1866,PCW = 0X8f00
5006 18:02:41.637659 ===================================
5007 18:02:41.640824 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5008 18:02:41.647600 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5009 18:02:41.650913 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5010 18:02:41.657553 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5011 18:02:41.660623 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5012 18:02:41.664703 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5013 18:02:41.664788 [ANA_INIT] flow start
5014 18:02:41.667350 [ANA_INIT] PLL >>>>>>>>
5015 18:02:41.670493 [ANA_INIT] PLL <<<<<<<<
5016 18:02:41.674206 [ANA_INIT] MIDPI >>>>>>>>
5017 18:02:41.674289 [ANA_INIT] MIDPI <<<<<<<<
5018 18:02:41.677410 [ANA_INIT] DLL >>>>>>>>
5019 18:02:41.680598 [ANA_INIT] flow end
5020 18:02:41.683681 ============ LP4 DIFF to SE enter ============
5021 18:02:41.686749 ============ LP4 DIFF to SE exit ============
5022 18:02:41.690603 [ANA_INIT] <<<<<<<<<<<<<
5023 18:02:41.693801 [Flow] Enable top DCM control >>>>>
5024 18:02:41.696927 [Flow] Enable top DCM control <<<<<
5025 18:02:41.700052 Enable DLL master slave shuffle
5026 18:02:41.703355 ==============================================================
5027 18:02:41.707120 Gating Mode config
5028 18:02:41.713544 ==============================================================
5029 18:02:41.713645 Config description:
5030 18:02:41.723576 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5031 18:02:41.729886 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5032 18:02:41.733672 SELPH_MODE 0: By rank 1: By Phase
5033 18:02:41.740251 ==============================================================
5034 18:02:41.743533 GAT_TRACK_EN = 1
5035 18:02:41.746851 RX_GATING_MODE = 2
5036 18:02:41.750075 RX_GATING_TRACK_MODE = 2
5037 18:02:41.753394 SELPH_MODE = 1
5038 18:02:41.756749 PICG_EARLY_EN = 1
5039 18:02:41.760093 VALID_LAT_VALUE = 1
5040 18:02:41.763388 ==============================================================
5041 18:02:41.766553 Enter into Gating configuration >>>>
5042 18:02:41.769856 Exit from Gating configuration <<<<
5043 18:02:41.773495 Enter into DVFS_PRE_config >>>>>
5044 18:02:41.786507 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5045 18:02:41.786600 Exit from DVFS_PRE_config <<<<<
5046 18:02:41.789552 Enter into PICG configuration >>>>
5047 18:02:41.792954 Exit from PICG configuration <<<<
5048 18:02:41.796585 [RX_INPUT] configuration >>>>>
5049 18:02:41.799957 [RX_INPUT] configuration <<<<<
5050 18:02:41.806147 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5051 18:02:41.809409 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5052 18:02:41.816328 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5053 18:02:41.822944 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5054 18:02:41.829392 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5055 18:02:41.836192 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5056 18:02:41.839538 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5057 18:02:41.842756 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5058 18:02:41.846109 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5059 18:02:41.852598 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5060 18:02:41.855788 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5061 18:02:41.859330 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5062 18:02:41.862650 ===================================
5063 18:02:41.865957 LPDDR4 DRAM CONFIGURATION
5064 18:02:41.869185 ===================================
5065 18:02:41.872439 EX_ROW_EN[0] = 0x0
5066 18:02:41.872555 EX_ROW_EN[1] = 0x0
5067 18:02:41.875552 LP4Y_EN = 0x0
5068 18:02:41.875636 WORK_FSP = 0x0
5069 18:02:41.879200 WL = 0x3
5070 18:02:41.879285 RL = 0x3
5071 18:02:41.882303 BL = 0x2
5072 18:02:41.882405 RPST = 0x0
5073 18:02:41.885470 RD_PRE = 0x0
5074 18:02:41.885555 WR_PRE = 0x1
5075 18:02:41.888839 WR_PST = 0x0
5076 18:02:41.888926 DBI_WR = 0x0
5077 18:02:41.892186 DBI_RD = 0x0
5078 18:02:41.892270 OTF = 0x1
5079 18:02:41.895413 ===================================
5080 18:02:41.899075 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5081 18:02:41.905534 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5082 18:02:41.909178 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5083 18:02:41.911869 ===================================
5084 18:02:41.915245 LPDDR4 DRAM CONFIGURATION
5085 18:02:41.919043 ===================================
5086 18:02:41.919126 EX_ROW_EN[0] = 0x10
5087 18:02:41.922292 EX_ROW_EN[1] = 0x0
5088 18:02:41.925669 LP4Y_EN = 0x0
5089 18:02:41.925752 WORK_FSP = 0x0
5090 18:02:41.928947 WL = 0x3
5091 18:02:41.929029 RL = 0x3
5092 18:02:41.931754 BL = 0x2
5093 18:02:41.931864 RPST = 0x0
5094 18:02:41.935232 RD_PRE = 0x0
5095 18:02:41.935359 WR_PRE = 0x1
5096 18:02:41.938885 WR_PST = 0x0
5097 18:02:41.939000 DBI_WR = 0x0
5098 18:02:41.941864 DBI_RD = 0x0
5099 18:02:41.941946 OTF = 0x1
5100 18:02:41.945640 ===================================
5101 18:02:41.952138 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5102 18:02:41.956452 nWR fixed to 30
5103 18:02:41.959806 [ModeRegInit_LP4] CH0 RK0
5104 18:02:41.959896 [ModeRegInit_LP4] CH0 RK1
5105 18:02:41.962752 [ModeRegInit_LP4] CH1 RK0
5106 18:02:41.966503 [ModeRegInit_LP4] CH1 RK1
5107 18:02:41.966639 match AC timing 9
5108 18:02:41.973187 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5109 18:02:41.976361 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5110 18:02:41.979539 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5111 18:02:41.986163 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5112 18:02:41.989540 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5113 18:02:41.989648 ==
5114 18:02:41.992748 Dram Type= 6, Freq= 0, CH_0, rank 0
5115 18:02:41.996044 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5116 18:02:41.996143 ==
5117 18:02:42.002804 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5118 18:02:42.009578 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5119 18:02:42.012824 [CA 0] Center 38 (7~69) winsize 63
5120 18:02:42.015975 [CA 1] Center 38 (8~69) winsize 62
5121 18:02:42.019125 [CA 2] Center 35 (5~66) winsize 62
5122 18:02:42.022467 [CA 3] Center 35 (5~65) winsize 61
5123 18:02:42.026368 [CA 4] Center 34 (4~64) winsize 61
5124 18:02:42.029677 [CA 5] Center 33 (3~64) winsize 62
5125 18:02:42.029761
5126 18:02:42.032947 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5127 18:02:42.033056
5128 18:02:42.036123 [CATrainingPosCal] consider 1 rank data
5129 18:02:42.039461 u2DelayCellTimex100 = 270/100 ps
5130 18:02:42.042543 CA0 delay=38 (7~69),Diff = 5 PI (31 cell)
5131 18:02:42.046076 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5132 18:02:42.049231 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5133 18:02:42.052466 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5134 18:02:42.055833 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5135 18:02:42.062537 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5136 18:02:42.062648
5137 18:02:42.065912 CA PerBit enable=1, Macro0, CA PI delay=33
5138 18:02:42.065996
5139 18:02:42.069159 [CBTSetCACLKResult] CA Dly = 33
5140 18:02:42.069242 CS Dly: 7 (0~38)
5141 18:02:42.069307 ==
5142 18:02:42.072491 Dram Type= 6, Freq= 0, CH_0, rank 1
5143 18:02:42.075993 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5144 18:02:42.078972 ==
5145 18:02:42.082347 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5146 18:02:42.088855 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5147 18:02:42.092449 [CA 0] Center 38 (7~69) winsize 63
5148 18:02:42.095695 [CA 1] Center 38 (8~69) winsize 62
5149 18:02:42.098824 [CA 2] Center 36 (6~66) winsize 61
5150 18:02:42.102211 [CA 3] Center 35 (5~66) winsize 62
5151 18:02:42.105447 [CA 4] Center 34 (4~65) winsize 62
5152 18:02:42.108552 [CA 5] Center 34 (4~64) winsize 61
5153 18:02:42.108641
5154 18:02:42.112169 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5155 18:02:42.112254
5156 18:02:42.115429 [CATrainingPosCal] consider 2 rank data
5157 18:02:42.118873 u2DelayCellTimex100 = 270/100 ps
5158 18:02:42.122105 CA0 delay=38 (7~69),Diff = 4 PI (24 cell)
5159 18:02:42.125363 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5160 18:02:42.128835 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5161 18:02:42.135264 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5162 18:02:42.138515 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5163 18:02:42.141734 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5164 18:02:42.141811
5165 18:02:42.145523 CA PerBit enable=1, Macro0, CA PI delay=34
5166 18:02:42.145598
5167 18:02:42.148581 [CBTSetCACLKResult] CA Dly = 34
5168 18:02:42.148685 CS Dly: 7 (0~39)
5169 18:02:42.148778
5170 18:02:42.152023 ----->DramcWriteLeveling(PI) begin...
5171 18:02:42.152108 ==
5172 18:02:42.154842 Dram Type= 6, Freq= 0, CH_0, rank 0
5173 18:02:42.161963 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5174 18:02:42.162051 ==
5175 18:02:42.165291 Write leveling (Byte 0): 32 => 32
5176 18:02:42.168526 Write leveling (Byte 1): 31 => 31
5177 18:02:42.171845 DramcWriteLeveling(PI) end<-----
5178 18:02:42.171915
5179 18:02:42.171976 ==
5180 18:02:42.175121 Dram Type= 6, Freq= 0, CH_0, rank 0
5181 18:02:42.178384 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5182 18:02:42.178454 ==
5183 18:02:42.181635 [Gating] SW mode calibration
5184 18:02:42.188449 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5185 18:02:42.191642 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5186 18:02:42.197936 0 14 0 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
5187 18:02:42.201207 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5188 18:02:42.204612 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5189 18:02:42.211551 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5190 18:02:42.214839 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5191 18:02:42.218250 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5192 18:02:42.224746 0 14 24 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)
5193 18:02:42.227978 0 14 28 | B1->B0 | 3333 2323 | 0 0 | (0 1) (1 0)
5194 18:02:42.231308 0 15 0 | B1->B0 | 2d2d 2323 | 0 0 | (1 0) (0 0)
5195 18:02:42.237981 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5196 18:02:42.241294 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5197 18:02:42.244527 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5198 18:02:42.251068 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5199 18:02:42.254643 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5200 18:02:42.257921 0 15 24 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
5201 18:02:42.264544 0 15 28 | B1->B0 | 2e2e 4646 | 1 0 | (1 1) (0 0)
5202 18:02:42.267807 1 0 0 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
5203 18:02:42.271085 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5204 18:02:42.277577 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5205 18:02:42.280921 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5206 18:02:42.284258 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5207 18:02:42.291047 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5208 18:02:42.294506 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5209 18:02:42.297635 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
5210 18:02:42.304351 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5211 18:02:42.307677 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5212 18:02:42.310848 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5213 18:02:42.317418 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5214 18:02:42.321002 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5215 18:02:42.324642 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5216 18:02:42.330896 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5217 18:02:42.334202 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5218 18:02:42.337418 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5219 18:02:42.340781 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5220 18:02:42.347819 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5221 18:02:42.351095 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5222 18:02:42.354283 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5223 18:02:42.360691 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5224 18:02:42.363996 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5225 18:02:42.367246 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5226 18:02:42.373877 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5227 18:02:42.377193 Total UI for P1: 0, mck2ui 16
5228 18:02:42.380981 best dqsien dly found for B0: ( 1, 2, 26)
5229 18:02:42.383732 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5230 18:02:42.387436 Total UI for P1: 0, mck2ui 16
5231 18:02:42.390638 best dqsien dly found for B1: ( 1, 3, 0)
5232 18:02:42.393932 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5233 18:02:42.396937 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5234 18:02:42.397086
5235 18:02:42.400467 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5236 18:02:42.404084 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5237 18:02:42.407057 [Gating] SW calibration Done
5238 18:02:42.407168 ==
5239 18:02:42.410384 Dram Type= 6, Freq= 0, CH_0, rank 0
5240 18:02:42.417296 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5241 18:02:42.417381 ==
5242 18:02:42.417458 RX Vref Scan: 0
5243 18:02:42.417521
5244 18:02:42.420623 RX Vref 0 -> 0, step: 1
5245 18:02:42.420727
5246 18:02:42.423627 RX Delay -80 -> 252, step: 8
5247 18:02:42.426933 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5248 18:02:42.430682 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5249 18:02:42.433934 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5250 18:02:42.437304 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5251 18:02:42.443846 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5252 18:02:42.447161 iDelay=208, Bit 5, Center 99 (8 ~ 191) 184
5253 18:02:42.450373 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5254 18:02:42.453493 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5255 18:02:42.456744 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5256 18:02:42.460074 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5257 18:02:42.466960 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5258 18:02:42.470224 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5259 18:02:42.473489 iDelay=208, Bit 12, Center 95 (8 ~ 183) 176
5260 18:02:42.476777 iDelay=208, Bit 13, Center 95 (8 ~ 183) 176
5261 18:02:42.479959 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5262 18:02:42.483348 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5263 18:02:42.486648 ==
5264 18:02:42.489759 Dram Type= 6, Freq= 0, CH_0, rank 0
5265 18:02:42.493639 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5266 18:02:42.493725 ==
5267 18:02:42.493791 DQS Delay:
5268 18:02:42.496329 DQS0 = 0, DQS1 = 0
5269 18:02:42.496423 DQM Delay:
5270 18:02:42.500110 DQM0 = 106, DQM1 = 91
5271 18:02:42.500220 DQ Delay:
5272 18:02:42.503133 DQ0 =107, DQ1 =107, DQ2 =99, DQ3 =99
5273 18:02:42.506342 DQ4 =107, DQ5 =99, DQ6 =115, DQ7 =115
5274 18:02:42.510018 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =87
5275 18:02:42.513089 DQ12 =95, DQ13 =95, DQ14 =99, DQ15 =99
5276 18:02:42.513167
5277 18:02:42.513230
5278 18:02:42.513296 ==
5279 18:02:42.516245 Dram Type= 6, Freq= 0, CH_0, rank 0
5280 18:02:42.519538 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5281 18:02:42.519646 ==
5282 18:02:42.522961
5283 18:02:42.523042
5284 18:02:42.523106 TX Vref Scan disable
5285 18:02:42.526706 == TX Byte 0 ==
5286 18:02:42.529958 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5287 18:02:42.533141 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5288 18:02:42.536682 == TX Byte 1 ==
5289 18:02:42.539850 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5290 18:02:42.543253 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5291 18:02:42.543334 ==
5292 18:02:42.546437 Dram Type= 6, Freq= 0, CH_0, rank 0
5293 18:02:42.552999 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5294 18:02:42.553105 ==
5295 18:02:42.553197
5296 18:02:42.553281
5297 18:02:42.553339 TX Vref Scan disable
5298 18:02:42.557453 == TX Byte 0 ==
5299 18:02:42.560562 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5300 18:02:42.563921 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5301 18:02:42.567184 == TX Byte 1 ==
5302 18:02:42.570797 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5303 18:02:42.574091 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5304 18:02:42.577546
5305 18:02:42.577626 [DATLAT]
5306 18:02:42.577691 Freq=933, CH0 RK0
5307 18:02:42.577749
5308 18:02:42.580816 DATLAT Default: 0xd
5309 18:02:42.580896 0, 0xFFFF, sum = 0
5310 18:02:42.584124 1, 0xFFFF, sum = 0
5311 18:02:42.584233 2, 0xFFFF, sum = 0
5312 18:02:42.587369 3, 0xFFFF, sum = 0
5313 18:02:42.587468 4, 0xFFFF, sum = 0
5314 18:02:42.590555 5, 0xFFFF, sum = 0
5315 18:02:42.593784 6, 0xFFFF, sum = 0
5316 18:02:42.593867 7, 0xFFFF, sum = 0
5317 18:02:42.596923 8, 0xFFFF, sum = 0
5318 18:02:42.597020 9, 0xFFFF, sum = 0
5319 18:02:42.600194 10, 0x0, sum = 1
5320 18:02:42.600316 11, 0x0, sum = 2
5321 18:02:42.603395 12, 0x0, sum = 3
5322 18:02:42.603517 13, 0x0, sum = 4
5323 18:02:42.603630 best_step = 11
5324 18:02:42.603739
5325 18:02:42.607131 ==
5326 18:02:42.610173 Dram Type= 6, Freq= 0, CH_0, rank 0
5327 18:02:42.613400 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5328 18:02:42.613506 ==
5329 18:02:42.613597 RX Vref Scan: 1
5330 18:02:42.613701
5331 18:02:42.616876 RX Vref 0 -> 0, step: 1
5332 18:02:42.616976
5333 18:02:42.619981 RX Delay -53 -> 252, step: 4
5334 18:02:42.620077
5335 18:02:42.623262 Set Vref, RX VrefLevel [Byte0]: 57
5336 18:02:42.626582 [Byte1]: 49
5337 18:02:42.626679
5338 18:02:42.629798 Final RX Vref Byte 0 = 57 to rank0
5339 18:02:42.633046 Final RX Vref Byte 1 = 49 to rank0
5340 18:02:42.636888 Final RX Vref Byte 0 = 57 to rank1
5341 18:02:42.640107 Final RX Vref Byte 1 = 49 to rank1==
5342 18:02:42.643115 Dram Type= 6, Freq= 0, CH_0, rank 0
5343 18:02:42.646491 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5344 18:02:42.649735 ==
5345 18:02:42.649874 DQS Delay:
5346 18:02:42.649993 DQS0 = 0, DQS1 = 0
5347 18:02:42.653127 DQM Delay:
5348 18:02:42.653235 DQM0 = 108, DQM1 = 92
5349 18:02:42.656456 DQ Delay:
5350 18:02:42.659708 DQ0 =108, DQ1 =108, DQ2 =104, DQ3 =106
5351 18:02:42.663007 DQ4 =108, DQ5 =98, DQ6 =116, DQ7 =116
5352 18:02:42.666415 DQ8 =86, DQ9 =78, DQ10 =92, DQ11 =90
5353 18:02:42.669700 DQ12 =96, DQ13 =94, DQ14 =102, DQ15 =100
5354 18:02:42.669782
5355 18:02:42.669846
5356 18:02:42.676773 [DQSOSCAuto] RK0, (LSB)MR18= 0x211d, (MSB)MR19= 0x505, tDQSOscB0 = 412 ps tDQSOscB1 = 411 ps
5357 18:02:42.679585 CH0 RK0: MR19=505, MR18=211D
5358 18:02:42.686489 CH0_RK0: MR19=0x505, MR18=0x211D, DQSOSC=411, MR23=63, INC=64, DEC=42
5359 18:02:42.686597
5360 18:02:42.689666 ----->DramcWriteLeveling(PI) begin...
5361 18:02:42.689771 ==
5362 18:02:42.692923 Dram Type= 6, Freq= 0, CH_0, rank 1
5363 18:02:42.696140 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5364 18:02:42.696237 ==
5365 18:02:42.699513 Write leveling (Byte 0): 34 => 34
5366 18:02:42.703357 Write leveling (Byte 1): 31 => 31
5367 18:02:42.706698 DramcWriteLeveling(PI) end<-----
5368 18:02:42.706799
5369 18:02:42.706888 ==
5370 18:02:42.709928 Dram Type= 6, Freq= 0, CH_0, rank 1
5371 18:02:42.713054 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5372 18:02:42.713137 ==
5373 18:02:42.716504 [Gating] SW mode calibration
5374 18:02:42.723282 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5375 18:02:42.729660 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5376 18:02:42.732894 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5377 18:02:42.740505 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5378 18:02:42.743066 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5379 18:02:42.746315 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5380 18:02:42.752870 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5381 18:02:42.756166 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5382 18:02:42.759525 0 14 24 | B1->B0 | 3434 3131 | 0 1 | (0 0) (1 0)
5383 18:02:42.765967 0 14 28 | B1->B0 | 2e2e 2626 | 0 0 | (0 1) (0 0)
5384 18:02:42.769318 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5385 18:02:42.772617 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5386 18:02:42.779322 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5387 18:02:42.782499 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5388 18:02:42.785737 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5389 18:02:42.792714 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5390 18:02:42.795892 0 15 24 | B1->B0 | 2323 2727 | 0 0 | (0 0) (1 1)
5391 18:02:42.799250 0 15 28 | B1->B0 | 3939 4545 | 1 0 | (0 0) (0 0)
5392 18:02:42.802379 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5393 18:02:42.809465 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5394 18:02:42.812800 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5395 18:02:42.815936 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5396 18:02:42.822398 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5397 18:02:42.826049 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5398 18:02:42.829006 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5399 18:02:42.835820 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5400 18:02:42.839078 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5401 18:02:42.842429 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5402 18:02:42.848919 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5403 18:02:42.852502 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5404 18:02:42.855833 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5405 18:02:42.862224 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5406 18:02:42.865434 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5407 18:02:42.868906 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5408 18:02:42.875846 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5409 18:02:42.879061 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5410 18:02:42.882292 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5411 18:02:42.888784 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5412 18:02:42.892190 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5413 18:02:42.895539 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5414 18:02:42.902210 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5415 18:02:42.905462 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5416 18:02:42.908716 Total UI for P1: 0, mck2ui 16
5417 18:02:42.912043 best dqsien dly found for B0: ( 1, 2, 26)
5418 18:02:42.915494 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5419 18:02:42.918659 Total UI for P1: 0, mck2ui 16
5420 18:02:42.921752 best dqsien dly found for B1: ( 1, 2, 28)
5421 18:02:42.925263 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5422 18:02:42.928444 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5423 18:02:42.928526
5424 18:02:42.934848 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5425 18:02:42.938617 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5426 18:02:42.938723 [Gating] SW calibration Done
5427 18:02:42.941895 ==
5428 18:02:42.945398 Dram Type= 6, Freq= 0, CH_0, rank 1
5429 18:02:42.948407 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5430 18:02:42.948492 ==
5431 18:02:42.948634 RX Vref Scan: 0
5432 18:02:42.948714
5433 18:02:42.951665 RX Vref 0 -> 0, step: 1
5434 18:02:42.951747
5435 18:02:42.954891 RX Delay -80 -> 252, step: 8
5436 18:02:42.958119 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5437 18:02:42.961452 iDelay=208, Bit 1, Center 103 (8 ~ 199) 192
5438 18:02:42.965139 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5439 18:02:42.971425 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5440 18:02:42.974632 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5441 18:02:42.978020 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5442 18:02:42.981265 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5443 18:02:42.985109 iDelay=208, Bit 7, Center 119 (32 ~ 207) 176
5444 18:02:42.991414 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5445 18:02:42.994834 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5446 18:02:42.998156 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5447 18:02:43.001574 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5448 18:02:43.004901 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5449 18:02:43.007946 iDelay=208, Bit 13, Center 95 (8 ~ 183) 176
5450 18:02:43.014653 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5451 18:02:43.017812 iDelay=208, Bit 15, Center 95 (8 ~ 183) 176
5452 18:02:43.017894 ==
5453 18:02:43.021067 Dram Type= 6, Freq= 0, CH_0, rank 1
5454 18:02:43.024718 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5455 18:02:43.024795 ==
5456 18:02:43.024867 DQS Delay:
5457 18:02:43.027774 DQS0 = 0, DQS1 = 0
5458 18:02:43.027847 DQM Delay:
5459 18:02:43.031246 DQM0 = 105, DQM1 = 91
5460 18:02:43.031319 DQ Delay:
5461 18:02:43.034423 DQ0 =107, DQ1 =103, DQ2 =99, DQ3 =99
5462 18:02:43.038081 DQ4 =107, DQ5 =95, DQ6 =111, DQ7 =119
5463 18:02:43.041583 DQ8 =83, DQ9 =83, DQ10 =91, DQ11 =87
5464 18:02:43.044516 DQ12 =95, DQ13 =95, DQ14 =99, DQ15 =95
5465 18:02:43.044641
5466 18:02:43.044707
5467 18:02:43.044765 ==
5468 18:02:43.047811 Dram Type= 6, Freq= 0, CH_0, rank 1
5469 18:02:43.054258 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5470 18:02:43.054339 ==
5471 18:02:43.054401
5472 18:02:43.054460
5473 18:02:43.054519 TX Vref Scan disable
5474 18:02:43.058068 == TX Byte 0 ==
5475 18:02:43.061288 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5476 18:02:43.067811 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5477 18:02:43.067896 == TX Byte 1 ==
5478 18:02:43.071217 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5479 18:02:43.077774 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5480 18:02:43.077849 ==
5481 18:02:43.081121 Dram Type= 6, Freq= 0, CH_0, rank 1
5482 18:02:43.084429 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5483 18:02:43.084528 ==
5484 18:02:43.084650
5485 18:02:43.084710
5486 18:02:43.087734 TX Vref Scan disable
5487 18:02:43.087809 == TX Byte 0 ==
5488 18:02:43.094266 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5489 18:02:43.098067 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5490 18:02:43.098145 == TX Byte 1 ==
5491 18:02:43.104490 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5492 18:02:43.107679 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5493 18:02:43.107774
5494 18:02:43.107853 [DATLAT]
5495 18:02:43.110883 Freq=933, CH0 RK1
5496 18:02:43.110957
5497 18:02:43.111018 DATLAT Default: 0xb
5498 18:02:43.114576 0, 0xFFFF, sum = 0
5499 18:02:43.114655 1, 0xFFFF, sum = 0
5500 18:02:43.117943 2, 0xFFFF, sum = 0
5501 18:02:43.118052 3, 0xFFFF, sum = 0
5502 18:02:43.121304 4, 0xFFFF, sum = 0
5503 18:02:43.121379 5, 0xFFFF, sum = 0
5504 18:02:43.124528 6, 0xFFFF, sum = 0
5505 18:02:43.124651 7, 0xFFFF, sum = 0
5506 18:02:43.127710 8, 0xFFFF, sum = 0
5507 18:02:43.127788 9, 0xFFFF, sum = 0
5508 18:02:43.131258 10, 0x0, sum = 1
5509 18:02:43.131357 11, 0x0, sum = 2
5510 18:02:43.134277 12, 0x0, sum = 3
5511 18:02:43.134353 13, 0x0, sum = 4
5512 18:02:43.137780 best_step = 11
5513 18:02:43.137852
5514 18:02:43.137920 ==
5515 18:02:43.141027 Dram Type= 6, Freq= 0, CH_0, rank 1
5516 18:02:43.144686 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5517 18:02:43.144787 ==
5518 18:02:43.147647 RX Vref Scan: 0
5519 18:02:43.147747
5520 18:02:43.147837 RX Vref 0 -> 0, step: 1
5521 18:02:43.147924
5522 18:02:43.150819 RX Delay -53 -> 252, step: 4
5523 18:02:43.158414 iDelay=199, Bit 0, Center 104 (19 ~ 190) 172
5524 18:02:43.161797 iDelay=199, Bit 1, Center 106 (19 ~ 194) 176
5525 18:02:43.165004 iDelay=199, Bit 2, Center 102 (19 ~ 186) 168
5526 18:02:43.168051 iDelay=199, Bit 3, Center 100 (19 ~ 182) 164
5527 18:02:43.171726 iDelay=199, Bit 4, Center 104 (19 ~ 190) 172
5528 18:02:43.178476 iDelay=199, Bit 5, Center 98 (11 ~ 186) 176
5529 18:02:43.181355 iDelay=199, Bit 6, Center 110 (23 ~ 198) 176
5530 18:02:43.185170 iDelay=199, Bit 7, Center 110 (23 ~ 198) 176
5531 18:02:43.188341 iDelay=199, Bit 8, Center 86 (3 ~ 170) 168
5532 18:02:43.191644 iDelay=199, Bit 9, Center 80 (-1 ~ 162) 164
5533 18:02:43.194842 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5534 18:02:43.201477 iDelay=199, Bit 11, Center 90 (7 ~ 174) 168
5535 18:02:43.205202 iDelay=199, Bit 12, Center 96 (11 ~ 182) 172
5536 18:02:43.207926 iDelay=199, Bit 13, Center 94 (11 ~ 178) 168
5537 18:02:43.211741 iDelay=199, Bit 14, Center 100 (15 ~ 186) 172
5538 18:02:43.214960 iDelay=199, Bit 15, Center 100 (19 ~ 182) 164
5539 18:02:43.218315 ==
5540 18:02:43.221589 Dram Type= 6, Freq= 0, CH_0, rank 1
5541 18:02:43.224878 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5542 18:02:43.224961 ==
5543 18:02:43.225026 DQS Delay:
5544 18:02:43.228241 DQS0 = 0, DQS1 = 0
5545 18:02:43.228324 DQM Delay:
5546 18:02:43.231596 DQM0 = 104, DQM1 = 92
5547 18:02:43.231679 DQ Delay:
5548 18:02:43.234995 DQ0 =104, DQ1 =106, DQ2 =102, DQ3 =100
5549 18:02:43.238038 DQ4 =104, DQ5 =98, DQ6 =110, DQ7 =110
5550 18:02:43.241671 DQ8 =86, DQ9 =80, DQ10 =94, DQ11 =90
5551 18:02:43.244894 DQ12 =96, DQ13 =94, DQ14 =100, DQ15 =100
5552 18:02:43.244976
5553 18:02:43.245040
5554 18:02:43.254536 [DQSOSCAuto] RK1, (LSB)MR18= 0x2406, (MSB)MR19= 0x505, tDQSOscB0 = 420 ps tDQSOscB1 = 410 ps
5555 18:02:43.254620 CH0 RK1: MR19=505, MR18=2406
5556 18:02:43.261516 CH0_RK1: MR19=0x505, MR18=0x2406, DQSOSC=410, MR23=63, INC=64, DEC=42
5557 18:02:43.264714 [RxdqsGatingPostProcess] freq 933
5558 18:02:43.271166 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5559 18:02:43.274721 best DQS0 dly(2T, 0.5T) = (0, 10)
5560 18:02:43.278010 best DQS1 dly(2T, 0.5T) = (0, 11)
5561 18:02:43.281373 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5562 18:02:43.284712 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5563 18:02:43.284794 best DQS0 dly(2T, 0.5T) = (0, 10)
5564 18:02:43.287849 best DQS1 dly(2T, 0.5T) = (0, 10)
5565 18:02:43.291363 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5566 18:02:43.294596 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5567 18:02:43.298031 Pre-setting of DQS Precalculation
5568 18:02:43.304609 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5569 18:02:43.304693 ==
5570 18:02:43.307889 Dram Type= 6, Freq= 0, CH_1, rank 0
5571 18:02:43.311342 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5572 18:02:43.311425 ==
5573 18:02:43.318020 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5574 18:02:43.324596 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5575 18:02:43.327841 [CA 0] Center 37 (7~68) winsize 62
5576 18:02:43.331160 [CA 1] Center 37 (7~68) winsize 62
5577 18:02:43.334414 [CA 2] Center 35 (6~65) winsize 60
5578 18:02:43.337810 [CA 3] Center 34 (4~65) winsize 62
5579 18:02:43.340961 [CA 4] Center 35 (5~66) winsize 62
5580 18:02:43.344032 [CA 5] Center 34 (4~65) winsize 62
5581 18:02:43.344115
5582 18:02:43.347649 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5583 18:02:43.347732
5584 18:02:43.350545 [CATrainingPosCal] consider 1 rank data
5585 18:02:43.354274 u2DelayCellTimex100 = 270/100 ps
5586 18:02:43.357465 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5587 18:02:43.360759 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5588 18:02:43.363856 CA2 delay=35 (6~65),Diff = 1 PI (6 cell)
5589 18:02:43.367237 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5590 18:02:43.370457 CA4 delay=35 (5~66),Diff = 1 PI (6 cell)
5591 18:02:43.374114 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
5592 18:02:43.374196
5593 18:02:43.380460 CA PerBit enable=1, Macro0, CA PI delay=34
5594 18:02:43.380543
5595 18:02:43.380648 [CBTSetCACLKResult] CA Dly = 34
5596 18:02:43.384314 CS Dly: 6 (0~37)
5597 18:02:43.384395 ==
5598 18:02:43.387176 Dram Type= 6, Freq= 0, CH_1, rank 1
5599 18:02:43.390897 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5600 18:02:43.390981 ==
5601 18:02:43.397514 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5602 18:02:43.403978 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5603 18:02:43.407197 [CA 0] Center 38 (7~69) winsize 63
5604 18:02:43.410504 [CA 1] Center 38 (7~69) winsize 63
5605 18:02:43.413856 [CA 2] Center 36 (6~66) winsize 61
5606 18:02:43.417166 [CA 3] Center 35 (6~65) winsize 60
5607 18:02:43.420450 [CA 4] Center 35 (6~65) winsize 60
5608 18:02:43.423809 [CA 5] Center 35 (5~65) winsize 61
5609 18:02:43.423891
5610 18:02:43.427023 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5611 18:02:43.427105
5612 18:02:43.430445 [CATrainingPosCal] consider 2 rank data
5613 18:02:43.433772 u2DelayCellTimex100 = 270/100 ps
5614 18:02:43.437006 CA0 delay=37 (7~68),Diff = 2 PI (12 cell)
5615 18:02:43.440351 CA1 delay=37 (7~68),Diff = 2 PI (12 cell)
5616 18:02:43.443551 CA2 delay=35 (6~65),Diff = 0 PI (0 cell)
5617 18:02:43.446824 CA3 delay=35 (6~65),Diff = 0 PI (0 cell)
5618 18:02:43.450434 CA4 delay=35 (6~65),Diff = 0 PI (0 cell)
5619 18:02:43.453454 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
5620 18:02:43.453565
5621 18:02:43.460489 CA PerBit enable=1, Macro0, CA PI delay=35
5622 18:02:43.460594
5623 18:02:43.463716 [CBTSetCACLKResult] CA Dly = 35
5624 18:02:43.463797 CS Dly: 7 (0~39)
5625 18:02:43.463860
5626 18:02:43.466945 ----->DramcWriteLeveling(PI) begin...
5627 18:02:43.467027 ==
5628 18:02:43.470275 Dram Type= 6, Freq= 0, CH_1, rank 0
5629 18:02:43.473457 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5630 18:02:43.473538 ==
5631 18:02:43.476606 Write leveling (Byte 0): 28 => 28
5632 18:02:43.479967 Write leveling (Byte 1): 28 => 28
5633 18:02:43.483493 DramcWriteLeveling(PI) end<-----
5634 18:02:43.483605
5635 18:02:43.483705 ==
5636 18:02:43.486830 Dram Type= 6, Freq= 0, CH_1, rank 0
5637 18:02:43.493483 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5638 18:02:43.493565 ==
5639 18:02:43.493629 [Gating] SW mode calibration
5640 18:02:43.503453 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5641 18:02:43.506684 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5642 18:02:43.509842 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5643 18:02:43.516958 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5644 18:02:43.520121 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5645 18:02:43.523422 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5646 18:02:43.530196 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5647 18:02:43.533425 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5648 18:02:43.536813 0 14 24 | B1->B0 | 3434 3030 | 0 0 | (0 0) (0 1)
5649 18:02:43.543206 0 14 28 | B1->B0 | 2727 2323 | 0 0 | (1 0) (1 0)
5650 18:02:43.546414 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5651 18:02:43.549761 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5652 18:02:43.556458 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5653 18:02:43.559516 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5654 18:02:43.562812 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5655 18:02:43.569693 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5656 18:02:43.572859 0 15 24 | B1->B0 | 2727 2e2e | 0 0 | (0 0) (0 0)
5657 18:02:43.575921 0 15 28 | B1->B0 | 3b3b 4242 | 0 0 | (0 0) (0 0)
5658 18:02:43.582546 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5659 18:02:43.586158 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5660 18:02:43.589459 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5661 18:02:43.595960 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5662 18:02:43.599235 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5663 18:02:43.602479 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5664 18:02:43.609276 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5665 18:02:43.612591 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5666 18:02:43.615995 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5667 18:02:43.622460 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5668 18:02:43.626230 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5669 18:02:43.629526 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5670 18:02:43.636088 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5671 18:02:43.639398 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5672 18:02:43.642781 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5673 18:02:43.649178 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5674 18:02:43.652471 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5675 18:02:43.655842 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5676 18:02:43.662205 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5677 18:02:43.666524 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5678 18:02:43.669078 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5679 18:02:43.675681 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5680 18:02:43.678998 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5681 18:02:43.682229 Total UI for P1: 0, mck2ui 16
5682 18:02:43.685362 best dqsien dly found for B0: ( 1, 2, 22)
5683 18:02:43.688721 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5684 18:02:43.692445 Total UI for P1: 0, mck2ui 16
5685 18:02:43.695771 best dqsien dly found for B1: ( 1, 2, 24)
5686 18:02:43.699107 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5687 18:02:43.702487 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5688 18:02:43.702565
5689 18:02:43.705273 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5690 18:02:43.711976 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5691 18:02:43.712082 [Gating] SW calibration Done
5692 18:02:43.712170 ==
5693 18:02:43.715203 Dram Type= 6, Freq= 0, CH_1, rank 0
5694 18:02:43.721746 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5695 18:02:43.721825 ==
5696 18:02:43.721913 RX Vref Scan: 0
5697 18:02:43.721991
5698 18:02:43.725105 RX Vref 0 -> 0, step: 1
5699 18:02:43.725183
5700 18:02:43.728325 RX Delay -80 -> 252, step: 8
5701 18:02:43.731955 iDelay=208, Bit 0, Center 107 (24 ~ 191) 168
5702 18:02:43.735338 iDelay=208, Bit 1, Center 95 (8 ~ 183) 176
5703 18:02:43.738554 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5704 18:02:43.741886 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5705 18:02:43.748456 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5706 18:02:43.751705 iDelay=208, Bit 5, Center 111 (24 ~ 199) 176
5707 18:02:43.754996 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5708 18:02:43.758245 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5709 18:02:43.761441 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5710 18:02:43.768389 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5711 18:02:43.771614 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5712 18:02:43.774785 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5713 18:02:43.777964 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5714 18:02:43.781304 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5715 18:02:43.784909 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5716 18:02:43.791615 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5717 18:02:43.791692 ==
5718 18:02:43.794717 Dram Type= 6, Freq= 0, CH_1, rank 0
5719 18:02:43.798118 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5720 18:02:43.798189 ==
5721 18:02:43.798258 DQS Delay:
5722 18:02:43.801320 DQS0 = 0, DQS1 = 0
5723 18:02:43.801390 DQM Delay:
5724 18:02:43.804754 DQM0 = 101, DQM1 = 95
5725 18:02:43.804825 DQ Delay:
5726 18:02:43.808203 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =99
5727 18:02:43.811276 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =99
5728 18:02:43.814560 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =91
5729 18:02:43.817727 DQ12 =103, DQ13 =103, DQ14 =99, DQ15 =103
5730 18:02:43.817797
5731 18:02:43.817857
5732 18:02:43.817919 ==
5733 18:02:43.821652 Dram Type= 6, Freq= 0, CH_1, rank 0
5734 18:02:43.827968 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5735 18:02:43.828080 ==
5736 18:02:43.828176
5737 18:02:43.828263
5738 18:02:43.828357 TX Vref Scan disable
5739 18:02:43.831430 == TX Byte 0 ==
5740 18:02:43.834666 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5741 18:02:43.841222 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5742 18:02:43.841318 == TX Byte 1 ==
5743 18:02:43.844417 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5744 18:02:43.850785 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5745 18:02:43.850866 ==
5746 18:02:43.854023 Dram Type= 6, Freq= 0, CH_1, rank 0
5747 18:02:43.857547 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5748 18:02:43.857624 ==
5749 18:02:43.857686
5750 18:02:43.857752
5751 18:02:43.860672 TX Vref Scan disable
5752 18:02:43.860741 == TX Byte 0 ==
5753 18:02:43.867747 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5754 18:02:43.870835 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5755 18:02:43.870912 == TX Byte 1 ==
5756 18:02:43.877660 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5757 18:02:43.880805 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5758 18:02:43.880884
5759 18:02:43.880950 [DATLAT]
5760 18:02:43.884089 Freq=933, CH1 RK0
5761 18:02:43.884168
5762 18:02:43.884232 DATLAT Default: 0xd
5763 18:02:43.887689 0, 0xFFFF, sum = 0
5764 18:02:43.887771 1, 0xFFFF, sum = 0
5765 18:02:43.890893 2, 0xFFFF, sum = 0
5766 18:02:43.893814 3, 0xFFFF, sum = 0
5767 18:02:43.893893 4, 0xFFFF, sum = 0
5768 18:02:43.897575 5, 0xFFFF, sum = 0
5769 18:02:43.897665 6, 0xFFFF, sum = 0
5770 18:02:43.900833 7, 0xFFFF, sum = 0
5771 18:02:43.900913 8, 0xFFFF, sum = 0
5772 18:02:43.903945 9, 0xFFFF, sum = 0
5773 18:02:43.904024 10, 0x0, sum = 1
5774 18:02:43.907301 11, 0x0, sum = 2
5775 18:02:43.907377 12, 0x0, sum = 3
5776 18:02:43.907441 13, 0x0, sum = 4
5777 18:02:43.910603 best_step = 11
5778 18:02:43.910682
5779 18:02:43.910748 ==
5780 18:02:43.913954 Dram Type= 6, Freq= 0, CH_1, rank 0
5781 18:02:43.917276 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5782 18:02:43.917348 ==
5783 18:02:43.920486 RX Vref Scan: 1
5784 18:02:43.920565
5785 18:02:43.920627 RX Vref 0 -> 0, step: 1
5786 18:02:43.924180
5787 18:02:43.924250 RX Delay -53 -> 252, step: 4
5788 18:02:43.924310
5789 18:02:43.927486 Set Vref, RX VrefLevel [Byte0]: 53
5790 18:02:43.930818 [Byte1]: 52
5791 18:02:43.935225
5792 18:02:43.935300 Final RX Vref Byte 0 = 53 to rank0
5793 18:02:43.938521 Final RX Vref Byte 1 = 52 to rank0
5794 18:02:43.941878 Final RX Vref Byte 0 = 53 to rank1
5795 18:02:43.945200 Final RX Vref Byte 1 = 52 to rank1==
5796 18:02:43.948456 Dram Type= 6, Freq= 0, CH_1, rank 0
5797 18:02:43.955263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5798 18:02:43.955341 ==
5799 18:02:43.955406 DQS Delay:
5800 18:02:43.955465 DQS0 = 0, DQS1 = 0
5801 18:02:43.958201 DQM Delay:
5802 18:02:43.958268 DQM0 = 104, DQM1 = 97
5803 18:02:43.961858 DQ Delay:
5804 18:02:43.965290 DQ0 =108, DQ1 =98, DQ2 =96, DQ3 =102
5805 18:02:43.968437 DQ4 =104, DQ5 =112, DQ6 =114, DQ7 =102
5806 18:02:43.971784 DQ8 =88, DQ9 =86, DQ10 =100, DQ11 =92
5807 18:02:43.974904 DQ12 =106, DQ13 =102, DQ14 =102, DQ15 =102
5808 18:02:43.974982
5809 18:02:43.975044
5810 18:02:43.981702 [DQSOSCAuto] RK0, (LSB)MR18= 0x1831, (MSB)MR19= 0x505, tDQSOscB0 = 406 ps tDQSOscB1 = 414 ps
5811 18:02:43.984768 CH1 RK0: MR19=505, MR18=1831
5812 18:02:43.991861 CH1_RK0: MR19=0x505, MR18=0x1831, DQSOSC=406, MR23=63, INC=65, DEC=43
5813 18:02:43.991944
5814 18:02:43.994958 ----->DramcWriteLeveling(PI) begin...
5815 18:02:43.995040 ==
5816 18:02:43.998234 Dram Type= 6, Freq= 0, CH_1, rank 1
5817 18:02:44.001512 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5818 18:02:44.001587 ==
5819 18:02:44.004586 Write leveling (Byte 0): 27 => 27
5820 18:02:44.008297 Write leveling (Byte 1): 28 => 28
5821 18:02:44.011689 DramcWriteLeveling(PI) end<-----
5822 18:02:44.011758
5823 18:02:44.011824 ==
5824 18:02:44.014921 Dram Type= 6, Freq= 0, CH_1, rank 1
5825 18:02:44.018153 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5826 18:02:44.021475 ==
5827 18:02:44.021543 [Gating] SW mode calibration
5828 18:02:44.031713 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5829 18:02:44.034996 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5830 18:02:44.038201 0 14 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5831 18:02:44.044901 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5832 18:02:44.048108 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5833 18:02:44.051408 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5834 18:02:44.057827 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5835 18:02:44.061154 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5836 18:02:44.064421 0 14 24 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 0)
5837 18:02:44.071043 0 14 28 | B1->B0 | 2424 2828 | 0 0 | (0 0) (1 0)
5838 18:02:44.074334 0 15 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5839 18:02:44.077618 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5840 18:02:44.084661 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5841 18:02:44.087668 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5842 18:02:44.090771 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5843 18:02:44.097864 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5844 18:02:44.100857 0 15 24 | B1->B0 | 2d2d 2424 | 0 1 | (0 0) (0 0)
5845 18:02:44.104103 0 15 28 | B1->B0 | 4444 3d3d | 0 0 | (0 0) (1 1)
5846 18:02:44.110580 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5847 18:02:44.114434 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5848 18:02:44.117547 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5849 18:02:44.124111 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5850 18:02:44.127533 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5851 18:02:44.130733 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5852 18:02:44.137286 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5853 18:02:44.140504 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5854 18:02:44.143826 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5855 18:02:44.150459 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5856 18:02:44.153873 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5857 18:02:44.157192 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5858 18:02:44.163701 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5859 18:02:44.167080 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5860 18:02:44.170290 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5861 18:02:44.176938 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5862 18:02:44.180161 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5863 18:02:44.183764 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5864 18:02:44.190098 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5865 18:02:44.193698 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5866 18:02:44.196908 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5867 18:02:44.203255 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5868 18:02:44.206922 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5869 18:02:44.210204 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5870 18:02:44.213371 Total UI for P1: 0, mck2ui 16
5871 18:02:44.216737 best dqsien dly found for B0: ( 1, 2, 24)
5872 18:02:44.220396 Total UI for P1: 0, mck2ui 16
5873 18:02:44.223147 best dqsien dly found for B1: ( 1, 2, 24)
5874 18:02:44.226873 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5875 18:02:44.230245 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5876 18:02:44.230324
5877 18:02:44.233471 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5878 18:02:44.239854 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5879 18:02:44.239931 [Gating] SW calibration Done
5880 18:02:44.240018 ==
5881 18:02:44.243308 Dram Type= 6, Freq= 0, CH_1, rank 1
5882 18:02:44.249835 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5883 18:02:44.249921 ==
5884 18:02:44.250001 RX Vref Scan: 0
5885 18:02:44.250077
5886 18:02:44.253182 RX Vref 0 -> 0, step: 1
5887 18:02:44.253255
5888 18:02:44.256486 RX Delay -80 -> 252, step: 8
5889 18:02:44.260313 iDelay=208, Bit 0, Center 107 (24 ~ 191) 168
5890 18:02:44.263190 iDelay=208, Bit 1, Center 95 (8 ~ 183) 176
5891 18:02:44.266390 iDelay=208, Bit 2, Center 87 (0 ~ 175) 176
5892 18:02:44.269615 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5893 18:02:44.276684 iDelay=208, Bit 4, Center 103 (16 ~ 191) 176
5894 18:02:44.280021 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5895 18:02:44.283465 iDelay=208, Bit 6, Center 111 (24 ~ 199) 176
5896 18:02:44.286458 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5897 18:02:44.289969 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5898 18:02:44.293247 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5899 18:02:44.299468 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5900 18:02:44.302746 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5901 18:02:44.306096 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5902 18:02:44.309719 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5903 18:02:44.313103 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5904 18:02:44.319513 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5905 18:02:44.319595 ==
5906 18:02:44.322874 Dram Type= 6, Freq= 0, CH_1, rank 1
5907 18:02:44.326306 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5908 18:02:44.326389 ==
5909 18:02:44.326453 DQS Delay:
5910 18:02:44.329394 DQS0 = 0, DQS1 = 0
5911 18:02:44.329476 DQM Delay:
5912 18:02:44.332738 DQM0 = 102, DQM1 = 95
5913 18:02:44.332820 DQ Delay:
5914 18:02:44.336032 DQ0 =107, DQ1 =95, DQ2 =87, DQ3 =99
5915 18:02:44.339292 DQ4 =103, DQ5 =115, DQ6 =111, DQ7 =99
5916 18:02:44.342594 DQ8 =83, DQ9 =87, DQ10 =95, DQ11 =87
5917 18:02:44.346239 DQ12 =103, DQ13 =103, DQ14 =99, DQ15 =103
5918 18:02:44.346320
5919 18:02:44.346407
5920 18:02:44.346481 ==
5921 18:02:44.349650 Dram Type= 6, Freq= 0, CH_1, rank 1
5922 18:02:44.355764 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5923 18:02:44.355846 ==
5924 18:02:44.355911
5925 18:02:44.355971
5926 18:02:44.356028 TX Vref Scan disable
5927 18:02:44.359150 == TX Byte 0 ==
5928 18:02:44.363047 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5929 18:02:44.369122 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5930 18:02:44.369204 == TX Byte 1 ==
5931 18:02:44.372811 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5932 18:02:44.379280 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5933 18:02:44.379400 ==
5934 18:02:44.382775 Dram Type= 6, Freq= 0, CH_1, rank 1
5935 18:02:44.385611 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5936 18:02:44.385692 ==
5937 18:02:44.385756
5938 18:02:44.385815
5939 18:02:44.389339 TX Vref Scan disable
5940 18:02:44.389420 == TX Byte 0 ==
5941 18:02:44.395698 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5942 18:02:44.399006 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5943 18:02:44.399088 == TX Byte 1 ==
5944 18:02:44.405685 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5945 18:02:44.409047 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5946 18:02:44.409128
5947 18:02:44.409191 [DATLAT]
5948 18:02:44.412476 Freq=933, CH1 RK1
5949 18:02:44.412619
5950 18:02:44.412685 DATLAT Default: 0xb
5951 18:02:44.415583 0, 0xFFFF, sum = 0
5952 18:02:44.415666 1, 0xFFFF, sum = 0
5953 18:02:44.419374 2, 0xFFFF, sum = 0
5954 18:02:44.419483 3, 0xFFFF, sum = 0
5955 18:02:44.422686 4, 0xFFFF, sum = 0
5956 18:02:44.425686 5, 0xFFFF, sum = 0
5957 18:02:44.425766 6, 0xFFFF, sum = 0
5958 18:02:44.428944 7, 0xFFFF, sum = 0
5959 18:02:44.429019 8, 0xFFFF, sum = 0
5960 18:02:44.432234 9, 0xFFFF, sum = 0
5961 18:02:44.432308 10, 0x0, sum = 1
5962 18:02:44.435558 11, 0x0, sum = 2
5963 18:02:44.435643 12, 0x0, sum = 3
5964 18:02:44.435727 13, 0x0, sum = 4
5965 18:02:44.438826 best_step = 11
5966 18:02:44.438935
5967 18:02:44.439042 ==
5968 18:02:44.442077 Dram Type= 6, Freq= 0, CH_1, rank 1
5969 18:02:44.445414 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5970 18:02:44.445495 ==
5971 18:02:44.448477 RX Vref Scan: 0
5972 18:02:44.448555
5973 18:02:44.452102 RX Vref 0 -> 0, step: 1
5974 18:02:44.452173
5975 18:02:44.452249 RX Delay -53 -> 252, step: 4
5976 18:02:44.459399 iDelay=199, Bit 0, Center 110 (35 ~ 186) 152
5977 18:02:44.462715 iDelay=199, Bit 1, Center 98 (19 ~ 178) 160
5978 18:02:44.466541 iDelay=199, Bit 2, Center 94 (15 ~ 174) 160
5979 18:02:44.469421 iDelay=199, Bit 3, Center 102 (19 ~ 186) 168
5980 18:02:44.472583 iDelay=199, Bit 4, Center 106 (23 ~ 190) 168
5981 18:02:44.479203 iDelay=199, Bit 5, Center 114 (31 ~ 198) 168
5982 18:02:44.483169 iDelay=199, Bit 6, Center 112 (31 ~ 194) 164
5983 18:02:44.486509 iDelay=199, Bit 7, Center 104 (27 ~ 182) 156
5984 18:02:44.489761 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5985 18:02:44.492962 iDelay=199, Bit 9, Center 88 (3 ~ 174) 172
5986 18:02:44.496253 iDelay=199, Bit 10, Center 98 (15 ~ 182) 168
5987 18:02:44.503001 iDelay=199, Bit 11, Center 92 (7 ~ 178) 172
5988 18:02:44.506088 iDelay=199, Bit 12, Center 108 (23 ~ 194) 172
5989 18:02:44.509578 iDelay=199, Bit 13, Center 102 (15 ~ 190) 176
5990 18:02:44.512863 iDelay=199, Bit 14, Center 106 (19 ~ 194) 176
5991 18:02:44.519462 iDelay=199, Bit 15, Center 108 (23 ~ 194) 172
5992 18:02:44.519569 ==
5993 18:02:44.522502 Dram Type= 6, Freq= 0, CH_1, rank 1
5994 18:02:44.526171 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5995 18:02:44.526269 ==
5996 18:02:44.526359 DQS Delay:
5997 18:02:44.529541 DQS0 = 0, DQS1 = 0
5998 18:02:44.529648 DQM Delay:
5999 18:02:44.532743 DQM0 = 105, DQM1 = 98
6000 18:02:44.532841 DQ Delay:
6001 18:02:44.536000 DQ0 =110, DQ1 =98, DQ2 =94, DQ3 =102
6002 18:02:44.539285 DQ4 =106, DQ5 =114, DQ6 =112, DQ7 =104
6003 18:02:44.543118 DQ8 =84, DQ9 =88, DQ10 =98, DQ11 =92
6004 18:02:44.546350 DQ12 =108, DQ13 =102, DQ14 =106, DQ15 =108
6005 18:02:44.546450
6006 18:02:44.546540
6007 18:02:44.555928 [DQSOSCAuto] RK1, (LSB)MR18= 0x22ff, (MSB)MR19= 0x504, tDQSOscB0 = 422 ps tDQSOscB1 = 411 ps
6008 18:02:44.556037 CH1 RK1: MR19=504, MR18=22FF
6009 18:02:44.562478 CH1_RK1: MR19=0x504, MR18=0x22FF, DQSOSC=411, MR23=63, INC=64, DEC=42
6010 18:02:44.565870 [RxdqsGatingPostProcess] freq 933
6011 18:02:44.572459 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6012 18:02:44.575710 best DQS0 dly(2T, 0.5T) = (0, 10)
6013 18:02:44.579113 best DQS1 dly(2T, 0.5T) = (0, 10)
6014 18:02:44.582432 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6015 18:02:44.585764 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6016 18:02:44.588991 best DQS0 dly(2T, 0.5T) = (0, 10)
6017 18:02:44.592302 best DQS1 dly(2T, 0.5T) = (0, 10)
6018 18:02:44.595598 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6019 18:02:44.595701 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6020 18:02:44.598876 Pre-setting of DQS Precalculation
6021 18:02:44.605719 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6022 18:02:44.612211 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6023 18:02:44.619101 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6024 18:02:44.619209
6025 18:02:44.619302
6026 18:02:44.622343 [Calibration Summary] 1866 Mbps
6027 18:02:44.625534 CH 0, Rank 0
6028 18:02:44.625635 SW Impedance : PASS
6029 18:02:44.628822 DUTY Scan : NO K
6030 18:02:44.631972 ZQ Calibration : PASS
6031 18:02:44.632073 Jitter Meter : NO K
6032 18:02:44.635338 CBT Training : PASS
6033 18:02:44.635436 Write leveling : PASS
6034 18:02:44.639144 RX DQS gating : PASS
6035 18:02:44.642451 RX DQ/DQS(RDDQC) : PASS
6036 18:02:44.642558 TX DQ/DQS : PASS
6037 18:02:44.645682 RX DATLAT : PASS
6038 18:02:44.648967 RX DQ/DQS(Engine): PASS
6039 18:02:44.649067 TX OE : NO K
6040 18:02:44.652192 All Pass.
6041 18:02:44.652276
6042 18:02:44.652341 CH 0, Rank 1
6043 18:02:44.655318 SW Impedance : PASS
6044 18:02:44.655417 DUTY Scan : NO K
6045 18:02:44.658711 ZQ Calibration : PASS
6046 18:02:44.662462 Jitter Meter : NO K
6047 18:02:44.662570 CBT Training : PASS
6048 18:02:44.665221 Write leveling : PASS
6049 18:02:44.668982 RX DQS gating : PASS
6050 18:02:44.669082 RX DQ/DQS(RDDQC) : PASS
6051 18:02:44.672235 TX DQ/DQS : PASS
6052 18:02:44.675544 RX DATLAT : PASS
6053 18:02:44.675652 RX DQ/DQS(Engine): PASS
6054 18:02:44.678853 TX OE : NO K
6055 18:02:44.678975 All Pass.
6056 18:02:44.679077
6057 18:02:44.681783 CH 1, Rank 0
6058 18:02:44.681881 SW Impedance : PASS
6059 18:02:44.685136 DUTY Scan : NO K
6060 18:02:44.685251 ZQ Calibration : PASS
6061 18:02:44.688370 Jitter Meter : NO K
6062 18:02:44.691762 CBT Training : PASS
6063 18:02:44.691848 Write leveling : PASS
6064 18:02:44.695095 RX DQS gating : PASS
6065 18:02:44.698950 RX DQ/DQS(RDDQC) : PASS
6066 18:02:44.699032 TX DQ/DQS : PASS
6067 18:02:44.701672 RX DATLAT : PASS
6068 18:02:44.705443 RX DQ/DQS(Engine): PASS
6069 18:02:44.705527 TX OE : NO K
6070 18:02:44.708530 All Pass.
6071 18:02:44.708634
6072 18:02:44.708699 CH 1, Rank 1
6073 18:02:44.711592 SW Impedance : PASS
6074 18:02:44.711674 DUTY Scan : NO K
6075 18:02:44.715156 ZQ Calibration : PASS
6076 18:02:44.718305 Jitter Meter : NO K
6077 18:02:44.718439 CBT Training : PASS
6078 18:02:44.722121 Write leveling : PASS
6079 18:02:44.725248 RX DQS gating : PASS
6080 18:02:44.725394 RX DQ/DQS(RDDQC) : PASS
6081 18:02:44.762911 TX DQ/DQS : PASS
6082 18:02:44.763306 RX DATLAT : PASS
6083 18:02:44.763443 RX DQ/DQS(Engine): PASS
6084 18:02:44.763541 TX OE : NO K
6085 18:02:44.763646 All Pass.
6086 18:02:44.763763
6087 18:02:44.763876 DramC Write-DBI off
6088 18:02:44.763989 PER_BANK_REFRESH: Hybrid Mode
6089 18:02:44.764102 TX_TRACKING: ON
6090 18:02:44.764214 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6091 18:02:44.764304 [FAST_K] Save calibration result to emmc
6092 18:02:44.764391 dramc_set_vcore_voltage set vcore to 650000
6093 18:02:44.764486 Read voltage for 400, 6
6094 18:02:44.764594 Vio18 = 0
6095 18:02:44.764702 Vcore = 650000
6096 18:02:44.765095 Vdram = 0
6097 18:02:44.765204 Vddq = 0
6098 18:02:44.765313 Vmddr = 0
6099 18:02:44.771616 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6100 18:02:44.775198 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6101 18:02:44.778247 MEM_TYPE=3, freq_sel=20
6102 18:02:44.781486 sv_algorithm_assistance_LP4_800
6103 18:02:44.784742 ============ PULL DRAM RESETB DOWN ============
6104 18:02:44.788091 ========== PULL DRAM RESETB DOWN end =========
6105 18:02:44.794718 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6106 18:02:44.797913 ===================================
6107 18:02:44.798011 LPDDR4 DRAM CONFIGURATION
6108 18:02:44.801226 ===================================
6109 18:02:44.804974 EX_ROW_EN[0] = 0x0
6110 18:02:44.808215 EX_ROW_EN[1] = 0x0
6111 18:02:44.808334 LP4Y_EN = 0x0
6112 18:02:44.811489 WORK_FSP = 0x0
6113 18:02:44.811578 WL = 0x2
6114 18:02:44.814569 RL = 0x2
6115 18:02:44.814654 BL = 0x2
6116 18:02:44.818177 RPST = 0x0
6117 18:02:44.818267 RD_PRE = 0x0
6118 18:02:44.821423 WR_PRE = 0x1
6119 18:02:44.821534 WR_PST = 0x0
6120 18:02:44.824296 DBI_WR = 0x0
6121 18:02:44.824408 DBI_RD = 0x0
6122 18:02:44.827697 OTF = 0x1
6123 18:02:44.831402 ===================================
6124 18:02:44.834210 ===================================
6125 18:02:44.834288 ANA top config
6126 18:02:44.837605 ===================================
6127 18:02:44.840998 DLL_ASYNC_EN = 0
6128 18:02:44.844278 ALL_SLAVE_EN = 1
6129 18:02:44.847494 NEW_RANK_MODE = 1
6130 18:02:44.847608 DLL_IDLE_MODE = 1
6131 18:02:44.851144 LP45_APHY_COMB_EN = 1
6132 18:02:44.854034 TX_ODT_DIS = 1
6133 18:02:44.857824 NEW_8X_MODE = 1
6134 18:02:44.861155 ===================================
6135 18:02:44.864361 ===================================
6136 18:02:44.867608 data_rate = 800
6137 18:02:44.867687 CKR = 1
6138 18:02:44.870849 DQ_P2S_RATIO = 4
6139 18:02:44.874101 ===================================
6140 18:02:44.877455 CA_P2S_RATIO = 4
6141 18:02:44.880710 DQ_CA_OPEN = 0
6142 18:02:44.883982 DQ_SEMI_OPEN = 1
6143 18:02:44.887215 CA_SEMI_OPEN = 1
6144 18:02:44.887292 CA_FULL_RATE = 0
6145 18:02:44.890657 DQ_CKDIV4_EN = 0
6146 18:02:44.893906 CA_CKDIV4_EN = 1
6147 18:02:44.897205 CA_PREDIV_EN = 0
6148 18:02:44.900442 PH8_DLY = 0
6149 18:02:44.904173 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6150 18:02:44.904249 DQ_AAMCK_DIV = 0
6151 18:02:44.907008 CA_AAMCK_DIV = 0
6152 18:02:44.910875 CA_ADMCK_DIV = 4
6153 18:02:44.914008 DQ_TRACK_CA_EN = 0
6154 18:02:44.917286 CA_PICK = 800
6155 18:02:44.920349 CA_MCKIO = 400
6156 18:02:44.924018 MCKIO_SEMI = 400
6157 18:02:44.924132 PLL_FREQ = 3016
6158 18:02:44.927118 DQ_UI_PI_RATIO = 32
6159 18:02:44.930378 CA_UI_PI_RATIO = 32
6160 18:02:44.933524 ===================================
6161 18:02:44.937478 ===================================
6162 18:02:44.940518 memory_type:LPDDR4
6163 18:02:44.940635 GP_NUM : 10
6164 18:02:44.943876 SRAM_EN : 1
6165 18:02:44.947227 MD32_EN : 0
6166 18:02:44.950508 ===================================
6167 18:02:44.950593 [ANA_INIT] >>>>>>>>>>>>>>
6168 18:02:44.953654 <<<<<< [CONFIGURE PHASE]: ANA_TX
6169 18:02:44.956946 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6170 18:02:44.960102 ===================================
6171 18:02:44.963365 data_rate = 800,PCW = 0X7400
6172 18:02:44.966668 ===================================
6173 18:02:44.970011 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6174 18:02:44.976801 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6175 18:02:44.986645 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6176 18:02:44.993286 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6177 18:02:44.996659 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6178 18:02:44.999921 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6179 18:02:45.000009 [ANA_INIT] flow start
6180 18:02:45.003192 [ANA_INIT] PLL >>>>>>>>
6181 18:02:45.006476 [ANA_INIT] PLL <<<<<<<<
6182 18:02:45.006562 [ANA_INIT] MIDPI >>>>>>>>
6183 18:02:45.009702 [ANA_INIT] MIDPI <<<<<<<<
6184 18:02:45.013531 [ANA_INIT] DLL >>>>>>>>
6185 18:02:45.013617 [ANA_INIT] flow end
6186 18:02:45.020138 ============ LP4 DIFF to SE enter ============
6187 18:02:45.023287 ============ LP4 DIFF to SE exit ============
6188 18:02:45.026677 [ANA_INIT] <<<<<<<<<<<<<
6189 18:02:45.030004 [Flow] Enable top DCM control >>>>>
6190 18:02:45.033131 [Flow] Enable top DCM control <<<<<
6191 18:02:45.033215 Enable DLL master slave shuffle
6192 18:02:45.039617 ==============================================================
6193 18:02:45.043451 Gating Mode config
6194 18:02:45.046752 ==============================================================
6195 18:02:45.049877 Config description:
6196 18:02:45.059665 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6197 18:02:45.066291 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6198 18:02:45.069632 SELPH_MODE 0: By rank 1: By Phase
6199 18:02:45.076631 ==============================================================
6200 18:02:45.079596 GAT_TRACK_EN = 0
6201 18:02:45.082726 RX_GATING_MODE = 2
6202 18:02:45.085979 RX_GATING_TRACK_MODE = 2
6203 18:02:45.089821 SELPH_MODE = 1
6204 18:02:45.089903 PICG_EARLY_EN = 1
6205 18:02:45.093081 VALID_LAT_VALUE = 1
6206 18:02:45.099654 ==============================================================
6207 18:02:45.102972 Enter into Gating configuration >>>>
6208 18:02:45.106159 Exit from Gating configuration <<<<
6209 18:02:45.109453 Enter into DVFS_PRE_config >>>>>
6210 18:02:45.119268 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6211 18:02:45.122462 Exit from DVFS_PRE_config <<<<<
6212 18:02:45.126161 Enter into PICG configuration >>>>
6213 18:02:45.129335 Exit from PICG configuration <<<<
6214 18:02:45.132333 [RX_INPUT] configuration >>>>>
6215 18:02:45.136205 [RX_INPUT] configuration <<<<<
6216 18:02:45.139073 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6217 18:02:45.146090 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6218 18:02:45.152534 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6219 18:02:45.159052 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6220 18:02:45.165644 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6221 18:02:45.172235 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6222 18:02:45.175580 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6223 18:02:45.178776 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6224 18:02:45.182531 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6225 18:02:45.188909 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6226 18:02:45.192145 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6227 18:02:45.195383 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6228 18:02:45.198767 ===================================
6229 18:02:45.202042 LPDDR4 DRAM CONFIGURATION
6230 18:02:45.205348 ===================================
6231 18:02:45.205432 EX_ROW_EN[0] = 0x0
6232 18:02:45.208569 EX_ROW_EN[1] = 0x0
6233 18:02:45.208693 LP4Y_EN = 0x0
6234 18:02:45.212050 WORK_FSP = 0x0
6235 18:02:45.212133 WL = 0x2
6236 18:02:45.215217 RL = 0x2
6237 18:02:45.218570 BL = 0x2
6238 18:02:45.218653 RPST = 0x0
6239 18:02:45.222385 RD_PRE = 0x0
6240 18:02:45.222468 WR_PRE = 0x1
6241 18:02:45.225218 WR_PST = 0x0
6242 18:02:45.225301 DBI_WR = 0x0
6243 18:02:45.228489 DBI_RD = 0x0
6244 18:02:45.228613 OTF = 0x1
6245 18:02:45.232180 ===================================
6246 18:02:45.235184 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6247 18:02:45.242044 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6248 18:02:45.245518 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6249 18:02:45.248802 ===================================
6250 18:02:45.251870 LPDDR4 DRAM CONFIGURATION
6251 18:02:45.255195 ===================================
6252 18:02:45.255280 EX_ROW_EN[0] = 0x10
6253 18:02:45.258885 EX_ROW_EN[1] = 0x0
6254 18:02:45.258968 LP4Y_EN = 0x0
6255 18:02:45.261686 WORK_FSP = 0x0
6256 18:02:45.261769 WL = 0x2
6257 18:02:45.265054 RL = 0x2
6258 18:02:45.265162 BL = 0x2
6259 18:02:45.268333 RPST = 0x0
6260 18:02:45.271599 RD_PRE = 0x0
6261 18:02:45.271682 WR_PRE = 0x1
6262 18:02:45.275497 WR_PST = 0x0
6263 18:02:45.275580 DBI_WR = 0x0
6264 18:02:45.278309 DBI_RD = 0x0
6265 18:02:45.278393 OTF = 0x1
6266 18:02:45.281584 ===================================
6267 18:02:45.288509 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6268 18:02:45.292175 nWR fixed to 30
6269 18:02:45.295538 [ModeRegInit_LP4] CH0 RK0
6270 18:02:45.295620 [ModeRegInit_LP4] CH0 RK1
6271 18:02:45.298879 [ModeRegInit_LP4] CH1 RK0
6272 18:02:45.302095 [ModeRegInit_LP4] CH1 RK1
6273 18:02:45.302174 match AC timing 19
6274 18:02:45.308895 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6275 18:02:45.312113 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6276 18:02:45.315211 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6277 18:02:45.321764 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6278 18:02:45.325644 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6279 18:02:45.325722 ==
6280 18:02:45.328913 Dram Type= 6, Freq= 0, CH_0, rank 0
6281 18:02:45.332347 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6282 18:02:45.332430 ==
6283 18:02:45.338679 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6284 18:02:45.345510 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6285 18:02:45.348459 [CA 0] Center 36 (8~64) winsize 57
6286 18:02:45.351742 [CA 1] Center 36 (8~64) winsize 57
6287 18:02:45.355335 [CA 2] Center 36 (8~64) winsize 57
6288 18:02:45.358566 [CA 3] Center 36 (8~64) winsize 57
6289 18:02:45.358648 [CA 4] Center 36 (8~64) winsize 57
6290 18:02:45.361826 [CA 5] Center 36 (8~64) winsize 57
6291 18:02:45.361909
6292 18:02:45.368262 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6293 18:02:45.368344
6294 18:02:45.371469 [CATrainingPosCal] consider 1 rank data
6295 18:02:45.374903 u2DelayCellTimex100 = 270/100 ps
6296 18:02:45.378240 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6297 18:02:45.381444 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6298 18:02:45.384807 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6299 18:02:45.387988 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6300 18:02:45.391242 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6301 18:02:45.394478 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6302 18:02:45.394592
6303 18:02:45.397724 CA PerBit enable=1, Macro0, CA PI delay=36
6304 18:02:45.397837
6305 18:02:45.401111 [CBTSetCACLKResult] CA Dly = 36
6306 18:02:45.404336 CS Dly: 1 (0~32)
6307 18:02:45.404441 ==
6308 18:02:45.407613 Dram Type= 6, Freq= 0, CH_0, rank 1
6309 18:02:45.410972 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6310 18:02:45.411084 ==
6311 18:02:45.418005 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6312 18:02:45.424515 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6313 18:02:45.427985 [CA 0] Center 36 (8~64) winsize 57
6314 18:02:45.428077 [CA 1] Center 36 (8~64) winsize 57
6315 18:02:45.431229 [CA 2] Center 36 (8~64) winsize 57
6316 18:02:45.434441 [CA 3] Center 36 (8~64) winsize 57
6317 18:02:45.437784 [CA 4] Center 36 (8~64) winsize 57
6318 18:02:45.441001 [CA 5] Center 36 (8~64) winsize 57
6319 18:02:45.441081
6320 18:02:45.444060 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6321 18:02:45.447543
6322 18:02:45.450837 [CATrainingPosCal] consider 2 rank data
6323 18:02:45.450910 u2DelayCellTimex100 = 270/100 ps
6324 18:02:45.457699 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6325 18:02:45.460803 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6326 18:02:45.464132 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6327 18:02:45.466947 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6328 18:02:45.470483 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6329 18:02:45.473812 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6330 18:02:45.473889
6331 18:02:45.477079 CA PerBit enable=1, Macro0, CA PI delay=36
6332 18:02:45.477161
6333 18:02:45.480345 [CBTSetCACLKResult] CA Dly = 36
6334 18:02:45.483612 CS Dly: 1 (0~32)
6335 18:02:45.483697
6336 18:02:45.486802 ----->DramcWriteLeveling(PI) begin...
6337 18:02:45.486886 ==
6338 18:02:45.490459 Dram Type= 6, Freq= 0, CH_0, rank 0
6339 18:02:45.493757 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6340 18:02:45.493844 ==
6341 18:02:45.496901 Write leveling (Byte 0): 40 => 8
6342 18:02:45.500077 Write leveling (Byte 1): 32 => 0
6343 18:02:45.503407 DramcWriteLeveling(PI) end<-----
6344 18:02:45.503489
6345 18:02:45.503554 ==
6346 18:02:45.506727 Dram Type= 6, Freq= 0, CH_0, rank 0
6347 18:02:45.509967 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6348 18:02:45.510046 ==
6349 18:02:45.513240 [Gating] SW mode calibration
6350 18:02:45.520361 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6351 18:02:45.526979 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6352 18:02:45.529782 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6353 18:02:45.533025 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6354 18:02:45.540051 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6355 18:02:45.543268 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6356 18:02:45.546543 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6357 18:02:45.553261 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6358 18:02:45.556304 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6359 18:02:45.560094 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6360 18:02:45.566163 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6361 18:02:45.569463 Total UI for P1: 0, mck2ui 16
6362 18:02:45.573135 best dqsien dly found for B0: ( 0, 14, 24)
6363 18:02:45.576104 Total UI for P1: 0, mck2ui 16
6364 18:02:45.579438 best dqsien dly found for B1: ( 0, 14, 24)
6365 18:02:45.582753 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6366 18:02:45.586045 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6367 18:02:45.586116
6368 18:02:45.589254 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6369 18:02:45.592493 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6370 18:02:45.595847 [Gating] SW calibration Done
6371 18:02:45.595922 ==
6372 18:02:45.599029 Dram Type= 6, Freq= 0, CH_0, rank 0
6373 18:02:45.602582 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6374 18:02:45.602670 ==
6375 18:02:45.605904 RX Vref Scan: 0
6376 18:02:45.605979
6377 18:02:45.609297 RX Vref 0 -> 0, step: 1
6378 18:02:45.609371
6379 18:02:45.609432 RX Delay -410 -> 252, step: 16
6380 18:02:45.615977 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6381 18:02:45.619199 iDelay=230, Bit 1, Center -3 (-234 ~ 229) 464
6382 18:02:45.623003 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6383 18:02:45.626276 iDelay=230, Bit 3, Center -11 (-234 ~ 213) 448
6384 18:02:45.632416 iDelay=230, Bit 4, Center -3 (-234 ~ 229) 464
6385 18:02:45.635999 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6386 18:02:45.639214 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6387 18:02:45.642464 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6388 18:02:45.649210 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6389 18:02:45.652352 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6390 18:02:45.655862 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6391 18:02:45.659029 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6392 18:02:45.665793 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6393 18:02:45.669180 iDelay=230, Bit 13, Center -27 (-266 ~ 213) 480
6394 18:02:45.672118 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6395 18:02:45.679135 iDelay=230, Bit 15, Center -27 (-266 ~ 213) 480
6396 18:02:45.679212 ==
6397 18:02:45.682284 Dram Type= 6, Freq= 0, CH_0, rank 0
6398 18:02:45.685583 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6399 18:02:45.685667 ==
6400 18:02:45.685732 DQS Delay:
6401 18:02:45.688761 DQS0 = 27, DQS1 = 43
6402 18:02:45.688841 DQM Delay:
6403 18:02:45.692169 DQM0 = 16, DQM1 = 12
6404 18:02:45.692252 DQ Delay:
6405 18:02:45.695317 DQ0 =8, DQ1 =24, DQ2 =8, DQ3 =16
6406 18:02:45.699196 DQ4 =24, DQ5 =0, DQ6 =24, DQ7 =24
6407 18:02:45.702331 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6408 18:02:45.705560 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6409 18:02:45.705640
6410 18:02:45.705703
6411 18:02:45.705761 ==
6412 18:02:45.708880 Dram Type= 6, Freq= 0, CH_0, rank 0
6413 18:02:45.712187 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6414 18:02:45.712268 ==
6415 18:02:45.712331
6416 18:02:45.712389
6417 18:02:45.715552 TX Vref Scan disable
6418 18:02:45.715632 == TX Byte 0 ==
6419 18:02:45.722189 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6420 18:02:45.725237 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6421 18:02:45.725317 == TX Byte 1 ==
6422 18:02:45.731749 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6423 18:02:45.734941 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6424 18:02:45.735022 ==
6425 18:02:45.738743 Dram Type= 6, Freq= 0, CH_0, rank 0
6426 18:02:45.741951 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6427 18:02:45.742027 ==
6428 18:02:45.742088
6429 18:02:45.745257
6430 18:02:45.745325 TX Vref Scan disable
6431 18:02:45.748505 == TX Byte 0 ==
6432 18:02:45.751822 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6433 18:02:45.755194 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6434 18:02:45.758396 == TX Byte 1 ==
6435 18:02:45.761927 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6436 18:02:45.765016 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6437 18:02:45.765095
6438 18:02:45.765157 [DATLAT]
6439 18:02:45.768334 Freq=400, CH0 RK0
6440 18:02:45.768439
6441 18:02:45.771385 DATLAT Default: 0xf
6442 18:02:45.771487 0, 0xFFFF, sum = 0
6443 18:02:45.775021 1, 0xFFFF, sum = 0
6444 18:02:45.775132 2, 0xFFFF, sum = 0
6445 18:02:45.778174 3, 0xFFFF, sum = 0
6446 18:02:45.778280 4, 0xFFFF, sum = 0
6447 18:02:45.781567 5, 0xFFFF, sum = 0
6448 18:02:45.781676 6, 0xFFFF, sum = 0
6449 18:02:45.784636 7, 0xFFFF, sum = 0
6450 18:02:45.784717 8, 0xFFFF, sum = 0
6451 18:02:45.787875 9, 0xFFFF, sum = 0
6452 18:02:45.787983 10, 0xFFFF, sum = 0
6453 18:02:45.791815 11, 0xFFFF, sum = 0
6454 18:02:45.791896 12, 0xFFFF, sum = 0
6455 18:02:45.794891 13, 0x0, sum = 1
6456 18:02:45.794973 14, 0x0, sum = 2
6457 18:02:45.798259 15, 0x0, sum = 3
6458 18:02:45.798332 16, 0x0, sum = 4
6459 18:02:45.801626 best_step = 14
6460 18:02:45.801696
6461 18:02:45.801755 ==
6462 18:02:45.804754 Dram Type= 6, Freq= 0, CH_0, rank 0
6463 18:02:45.808025 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6464 18:02:45.808111 ==
6465 18:02:45.811339 RX Vref Scan: 1
6466 18:02:45.811438
6467 18:02:45.811528 RX Vref 0 -> 0, step: 1
6468 18:02:45.811615
6469 18:02:45.814561 RX Delay -327 -> 252, step: 8
6470 18:02:45.814632
6471 18:02:45.818005 Set Vref, RX VrefLevel [Byte0]: 57
6472 18:02:45.821288 [Byte1]: 49
6473 18:02:45.825709
6474 18:02:45.825789 Final RX Vref Byte 0 = 57 to rank0
6475 18:02:45.828910 Final RX Vref Byte 1 = 49 to rank0
6476 18:02:45.832166 Final RX Vref Byte 0 = 57 to rank1
6477 18:02:45.835554 Final RX Vref Byte 1 = 49 to rank1==
6478 18:02:45.839319 Dram Type= 6, Freq= 0, CH_0, rank 0
6479 18:02:45.845662 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6480 18:02:45.845746 ==
6481 18:02:45.845811 DQS Delay:
6482 18:02:45.848880 DQS0 = 24, DQS1 = 48
6483 18:02:45.848962 DQM Delay:
6484 18:02:45.849028 DQM0 = 8, DQM1 = 15
6485 18:02:45.852166 DQ Delay:
6486 18:02:45.855478 DQ0 =8, DQ1 =8, DQ2 =4, DQ3 =4
6487 18:02:45.855561 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6488 18:02:45.859166 DQ8 =8, DQ9 =0, DQ10 =12, DQ11 =12
6489 18:02:45.862401 DQ12 =20, DQ13 =20, DQ14 =28, DQ15 =24
6490 18:02:45.862485
6491 18:02:45.862550
6492 18:02:45.872310 [DQSOSCAuto] RK0, (LSB)MR18= 0xaca4, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 388 ps
6493 18:02:45.875540 CH0 RK0: MR19=C0C, MR18=ACA4
6494 18:02:45.882038 CH0_RK0: MR19=0xC0C, MR18=0xACA4, DQSOSC=388, MR23=63, INC=392, DEC=261
6495 18:02:45.882122 ==
6496 18:02:45.885245 Dram Type= 6, Freq= 0, CH_0, rank 1
6497 18:02:45.888468 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6498 18:02:45.888573 ==
6499 18:02:45.892025 [Gating] SW mode calibration
6500 18:02:45.898573 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6501 18:02:45.905481 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6502 18:02:45.908453 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6503 18:02:45.911729 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6504 18:02:45.918680 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6505 18:02:45.921953 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6506 18:02:45.925369 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6507 18:02:45.928636 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6508 18:02:45.935354 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6509 18:02:45.938624 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6510 18:02:45.941818 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6511 18:02:45.945123 Total UI for P1: 0, mck2ui 16
6512 18:02:45.948311 best dqsien dly found for B0: ( 0, 14, 24)
6513 18:02:45.952131 Total UI for P1: 0, mck2ui 16
6514 18:02:45.955352 best dqsien dly found for B1: ( 0, 14, 24)
6515 18:02:45.958618 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6516 18:02:45.962001 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6517 18:02:45.965151
6518 18:02:45.968107 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6519 18:02:45.971892 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6520 18:02:45.975022 [Gating] SW calibration Done
6521 18:02:45.975112 ==
6522 18:02:45.978108 Dram Type= 6, Freq= 0, CH_0, rank 1
6523 18:02:45.981896 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6524 18:02:45.981984 ==
6525 18:02:45.982050 RX Vref Scan: 0
6526 18:02:45.984877
6527 18:02:45.984976 RX Vref 0 -> 0, step: 1
6528 18:02:45.985074
6529 18:02:45.988134 RX Delay -410 -> 252, step: 16
6530 18:02:45.991480 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6531 18:02:45.998228 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6532 18:02:46.001243 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6533 18:02:46.005196 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6534 18:02:46.007885 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6535 18:02:46.014517 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6536 18:02:46.018191 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6537 18:02:46.021512 iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480
6538 18:02:46.024833 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6539 18:02:46.031301 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6540 18:02:46.034887 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6541 18:02:46.037720 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6542 18:02:46.041101 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6543 18:02:46.047724 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6544 18:02:46.051052 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6545 18:02:46.054270 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6546 18:02:46.054345 ==
6547 18:02:46.057560 Dram Type= 6, Freq= 0, CH_0, rank 1
6548 18:02:46.064316 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6549 18:02:46.064392 ==
6550 18:02:46.064456 DQS Delay:
6551 18:02:46.068092 DQS0 = 27, DQS1 = 43
6552 18:02:46.068165 DQM Delay:
6553 18:02:46.068226 DQM0 = 10, DQM1 = 15
6554 18:02:46.071141 DQ Delay:
6555 18:02:46.074463 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6556 18:02:46.074536 DQ4 =8, DQ5 =0, DQ6 =24, DQ7 =16
6557 18:02:46.077553 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6558 18:02:46.081317 DQ12 =16, DQ13 =24, DQ14 =24, DQ15 =24
6559 18:02:46.081394
6560 18:02:46.081469
6561 18:02:46.084508 ==
6562 18:02:46.084633 Dram Type= 6, Freq= 0, CH_0, rank 1
6563 18:02:46.091037 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6564 18:02:46.091113 ==
6565 18:02:46.091176
6566 18:02:46.091234
6567 18:02:46.094340 TX Vref Scan disable
6568 18:02:46.094417 == TX Byte 0 ==
6569 18:02:46.097548 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6570 18:02:46.104160 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6571 18:02:46.104239 == TX Byte 1 ==
6572 18:02:46.107511 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6573 18:02:46.110870 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6574 18:02:46.114051 ==
6575 18:02:46.117910 Dram Type= 6, Freq= 0, CH_0, rank 1
6576 18:02:46.120560 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6577 18:02:46.120647 ==
6578 18:02:46.120710
6579 18:02:46.120769
6580 18:02:46.124410 TX Vref Scan disable
6581 18:02:46.124506 == TX Byte 0 ==
6582 18:02:46.127547 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6583 18:02:46.134121 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6584 18:02:46.134196 == TX Byte 1 ==
6585 18:02:46.137702 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6586 18:02:46.144245 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6587 18:02:46.144321
6588 18:02:46.144383 [DATLAT]
6589 18:02:46.144442 Freq=400, CH0 RK1
6590 18:02:46.144537
6591 18:02:46.147554 DATLAT Default: 0xe
6592 18:02:46.147629 0, 0xFFFF, sum = 0
6593 18:02:46.150774 1, 0xFFFF, sum = 0
6594 18:02:46.154019 2, 0xFFFF, sum = 0
6595 18:02:46.154118 3, 0xFFFF, sum = 0
6596 18:02:46.157150 4, 0xFFFF, sum = 0
6597 18:02:46.157261 5, 0xFFFF, sum = 0
6598 18:02:46.160490 6, 0xFFFF, sum = 0
6599 18:02:46.160609 7, 0xFFFF, sum = 0
6600 18:02:46.163813 8, 0xFFFF, sum = 0
6601 18:02:46.163895 9, 0xFFFF, sum = 0
6602 18:02:46.167613 10, 0xFFFF, sum = 0
6603 18:02:46.167725 11, 0xFFFF, sum = 0
6604 18:02:46.170798 12, 0xFFFF, sum = 0
6605 18:02:46.170870 13, 0x0, sum = 1
6606 18:02:46.174002 14, 0x0, sum = 2
6607 18:02:46.174083 15, 0x0, sum = 3
6608 18:02:46.177228 16, 0x0, sum = 4
6609 18:02:46.177310 best_step = 14
6610 18:02:46.177373
6611 18:02:46.177432 ==
6612 18:02:46.180471 Dram Type= 6, Freq= 0, CH_0, rank 1
6613 18:02:46.183612 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6614 18:02:46.187273 ==
6615 18:02:46.187386 RX Vref Scan: 0
6616 18:02:46.187480
6617 18:02:46.190388 RX Vref 0 -> 0, step: 1
6618 18:02:46.190457
6619 18:02:46.193486 RX Delay -327 -> 252, step: 8
6620 18:02:46.200185 iDelay=217, Bit 0, Center -20 (-247 ~ 208) 456
6621 18:02:46.203471 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6622 18:02:46.207145 iDelay=217, Bit 2, Center -24 (-247 ~ 200) 448
6623 18:02:46.210441 iDelay=217, Bit 3, Center -20 (-239 ~ 200) 440
6624 18:02:46.217010 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6625 18:02:46.220271 iDelay=217, Bit 5, Center -28 (-255 ~ 200) 456
6626 18:02:46.223453 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6627 18:02:46.226815 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6628 18:02:46.229854 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6629 18:02:46.236632 iDelay=217, Bit 9, Center -44 (-271 ~ 184) 456
6630 18:02:46.240020 iDelay=217, Bit 10, Center -28 (-255 ~ 200) 456
6631 18:02:46.243183 iDelay=217, Bit 11, Center -36 (-263 ~ 192) 456
6632 18:02:46.249688 iDelay=217, Bit 12, Center -24 (-247 ~ 200) 448
6633 18:02:46.253103 iDelay=217, Bit 13, Center -24 (-247 ~ 200) 448
6634 18:02:46.256315 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
6635 18:02:46.259682 iDelay=217, Bit 15, Center -24 (-247 ~ 200) 448
6636 18:02:46.259772 ==
6637 18:02:46.263092 Dram Type= 6, Freq= 0, CH_0, rank 1
6638 18:02:46.269569 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6639 18:02:46.269721 ==
6640 18:02:46.269869 DQS Delay:
6641 18:02:46.272794 DQS0 = 28, DQS1 = 44
6642 18:02:46.272889 DQM Delay:
6643 18:02:46.276089 DQM0 = 10, DQM1 = 14
6644 18:02:46.276210 DQ Delay:
6645 18:02:46.279781 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =8
6646 18:02:46.282952 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6647 18:02:46.286210 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6648 18:02:46.289291 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =20
6649 18:02:46.289373
6650 18:02:46.289448
6651 18:02:46.296199 [DQSOSCAuto] RK1, (LSB)MR18= 0xb96a, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 386 ps
6652 18:02:46.299441 CH0 RK1: MR19=C0C, MR18=B96A
6653 18:02:46.305869 CH0_RK1: MR19=0xC0C, MR18=0xB96A, DQSOSC=386, MR23=63, INC=396, DEC=264
6654 18:02:46.309199 [RxdqsGatingPostProcess] freq 400
6655 18:02:46.312476 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6656 18:02:46.315760 best DQS0 dly(2T, 0.5T) = (0, 10)
6657 18:02:46.319082 best DQS1 dly(2T, 0.5T) = (0, 10)
6658 18:02:46.322428 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6659 18:02:46.325787 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6660 18:02:46.329049 best DQS0 dly(2T, 0.5T) = (0, 10)
6661 18:02:46.332218 best DQS1 dly(2T, 0.5T) = (0, 10)
6662 18:02:46.335870 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6663 18:02:46.339210 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6664 18:02:46.342491 Pre-setting of DQS Precalculation
6665 18:02:46.345803 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6666 18:02:46.348959 ==
6667 18:02:46.349037 Dram Type= 6, Freq= 0, CH_1, rank 0
6668 18:02:46.355999 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6669 18:02:46.356086 ==
6670 18:02:46.359429 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6671 18:02:46.365978 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6672 18:02:46.369158 [CA 0] Center 36 (8~64) winsize 57
6673 18:02:46.372531 [CA 1] Center 36 (8~64) winsize 57
6674 18:02:46.375619 [CA 2] Center 36 (8~64) winsize 57
6675 18:02:46.379051 [CA 3] Center 36 (8~64) winsize 57
6676 18:02:46.382190 [CA 4] Center 36 (8~64) winsize 57
6677 18:02:46.385960 [CA 5] Center 36 (8~64) winsize 57
6678 18:02:46.386041
6679 18:02:46.389203 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6680 18:02:46.389279
6681 18:02:46.392191 [CATrainingPosCal] consider 1 rank data
6682 18:02:46.395585 u2DelayCellTimex100 = 270/100 ps
6683 18:02:46.398930 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6684 18:02:46.402722 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6685 18:02:46.405913 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6686 18:02:46.409159 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6687 18:02:46.412486 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6688 18:02:46.418989 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6689 18:02:46.419104
6690 18:02:46.422362 CA PerBit enable=1, Macro0, CA PI delay=36
6691 18:02:46.422444
6692 18:02:46.425613 [CBTSetCACLKResult] CA Dly = 36
6693 18:02:46.425689 CS Dly: 1 (0~32)
6694 18:02:46.425750 ==
6695 18:02:46.429103 Dram Type= 6, Freq= 0, CH_1, rank 1
6696 18:02:46.432460 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6697 18:02:46.435667 ==
6698 18:02:46.438849 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6699 18:02:46.445423 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6700 18:02:46.448789 [CA 0] Center 36 (8~64) winsize 57
6701 18:02:46.451820 [CA 1] Center 36 (8~64) winsize 57
6702 18:02:46.455131 [CA 2] Center 36 (8~64) winsize 57
6703 18:02:46.458913 [CA 3] Center 36 (8~64) winsize 57
6704 18:02:46.462232 [CA 4] Center 36 (8~64) winsize 57
6705 18:02:46.465565 [CA 5] Center 36 (8~64) winsize 57
6706 18:02:46.465644
6707 18:02:46.468798 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6708 18:02:46.468875
6709 18:02:46.472161 [CATrainingPosCal] consider 2 rank data
6710 18:02:46.475367 u2DelayCellTimex100 = 270/100 ps
6711 18:02:46.478556 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6712 18:02:46.481941 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6713 18:02:46.485413 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6714 18:02:46.488677 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6715 18:02:46.492305 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6716 18:02:46.495530 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6717 18:02:46.495653
6718 18:02:46.498531 CA PerBit enable=1, Macro0, CA PI delay=36
6719 18:02:46.498626
6720 18:02:46.501733 [CBTSetCACLKResult] CA Dly = 36
6721 18:02:46.505364 CS Dly: 1 (0~32)
6722 18:02:46.505503
6723 18:02:46.508584 ----->DramcWriteLeveling(PI) begin...
6724 18:02:46.508690 ==
6725 18:02:46.511885 Dram Type= 6, Freq= 0, CH_1, rank 0
6726 18:02:46.515162 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6727 18:02:46.515247 ==
6728 18:02:46.518436 Write leveling (Byte 0): 40 => 8
6729 18:02:46.522038 Write leveling (Byte 1): 32 => 0
6730 18:02:46.525244 DramcWriteLeveling(PI) end<-----
6731 18:02:46.525325
6732 18:02:46.525391 ==
6733 18:02:46.528424 Dram Type= 6, Freq= 0, CH_1, rank 0
6734 18:02:46.531750 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6735 18:02:46.531835 ==
6736 18:02:46.535083 [Gating] SW mode calibration
6737 18:02:46.541969 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6738 18:02:46.548397 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6739 18:02:46.551732 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6740 18:02:46.558114 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6741 18:02:46.561595 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6742 18:02:46.564715 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6743 18:02:46.571317 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6744 18:02:46.574710 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6745 18:02:46.578013 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6746 18:02:46.584690 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6747 18:02:46.587949 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6748 18:02:46.591307 Total UI for P1: 0, mck2ui 16
6749 18:02:46.594896 best dqsien dly found for B0: ( 0, 14, 24)
6750 18:02:46.598079 Total UI for P1: 0, mck2ui 16
6751 18:02:46.601214 best dqsien dly found for B1: ( 0, 14, 24)
6752 18:02:46.604509 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6753 18:02:46.607786 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6754 18:02:46.607869
6755 18:02:46.611409 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6756 18:02:46.614530 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6757 18:02:46.618207 [Gating] SW calibration Done
6758 18:02:46.618328 ==
6759 18:02:46.621529 Dram Type= 6, Freq= 0, CH_1, rank 0
6760 18:02:46.624743 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6761 18:02:46.624820 ==
6762 18:02:46.627992 RX Vref Scan: 0
6763 18:02:46.628082
6764 18:02:46.631671 RX Vref 0 -> 0, step: 1
6765 18:02:46.631749
6766 18:02:46.631813 RX Delay -410 -> 252, step: 16
6767 18:02:46.638267 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6768 18:02:46.641568 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6769 18:02:46.644807 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6770 18:02:46.647982 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6771 18:02:46.654532 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6772 18:02:46.657725 iDelay=230, Bit 5, Center -11 (-250 ~ 229) 480
6773 18:02:46.661452 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6774 18:02:46.668071 iDelay=230, Bit 7, Center -27 (-266 ~ 213) 480
6775 18:02:46.671308 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6776 18:02:46.674631 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6777 18:02:46.677932 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6778 18:02:46.684401 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6779 18:02:46.687747 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6780 18:02:46.690950 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6781 18:02:46.694028 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6782 18:02:46.700634 iDelay=230, Bit 15, Center -19 (-266 ~ 229) 496
6783 18:02:46.700719 ==
6784 18:02:46.704467 Dram Type= 6, Freq= 0, CH_1, rank 0
6785 18:02:46.707598 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6786 18:02:46.707674 ==
6787 18:02:46.707744 DQS Delay:
6788 18:02:46.710673 DQS0 = 27, DQS1 = 43
6789 18:02:46.710751 DQM Delay:
6790 18:02:46.714141 DQM0 = 8, DQM1 = 16
6791 18:02:46.714218 DQ Delay:
6792 18:02:46.717347 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6793 18:02:46.721028 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =0
6794 18:02:46.724178 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6795 18:02:46.727439 DQ12 =32, DQ13 =24, DQ14 =16, DQ15 =24
6796 18:02:46.727522
6797 18:02:46.727591
6798 18:02:46.727652 ==
6799 18:02:46.730614 Dram Type= 6, Freq= 0, CH_1, rank 0
6800 18:02:46.734167 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6801 18:02:46.734247 ==
6802 18:02:46.734323
6803 18:02:46.734386
6804 18:02:46.737465 TX Vref Scan disable
6805 18:02:46.740627 == TX Byte 0 ==
6806 18:02:46.743861 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6807 18:02:46.747188 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6808 18:02:46.747276 == TX Byte 1 ==
6809 18:02:46.753677 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6810 18:02:46.757088 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6811 18:02:46.757170 ==
6812 18:02:46.760324 Dram Type= 6, Freq= 0, CH_1, rank 0
6813 18:02:46.763516 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6814 18:02:46.763599 ==
6815 18:02:46.767320
6816 18:02:46.767404
6817 18:02:46.767473 TX Vref Scan disable
6818 18:02:46.770113 == TX Byte 0 ==
6819 18:02:46.773937 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6820 18:02:46.777237 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6821 18:02:46.780500 == TX Byte 1 ==
6822 18:02:46.783934 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6823 18:02:46.787194 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6824 18:02:46.787310
6825 18:02:46.790458 [DATLAT]
6826 18:02:46.790544 Freq=400, CH1 RK0
6827 18:02:46.790621
6828 18:02:46.793758 DATLAT Default: 0xf
6829 18:02:46.793856 0, 0xFFFF, sum = 0
6830 18:02:46.797141 1, 0xFFFF, sum = 0
6831 18:02:46.797220 2, 0xFFFF, sum = 0
6832 18:02:46.800381 3, 0xFFFF, sum = 0
6833 18:02:46.800491 4, 0xFFFF, sum = 0
6834 18:02:46.803605 5, 0xFFFF, sum = 0
6835 18:02:46.803717 6, 0xFFFF, sum = 0
6836 18:02:46.807250 7, 0xFFFF, sum = 0
6837 18:02:46.807360 8, 0xFFFF, sum = 0
6838 18:02:46.810453 9, 0xFFFF, sum = 0
6839 18:02:46.810532 10, 0xFFFF, sum = 0
6840 18:02:46.813495 11, 0xFFFF, sum = 0
6841 18:02:46.813576 12, 0xFFFF, sum = 0
6842 18:02:46.816659 13, 0x0, sum = 1
6843 18:02:46.816773 14, 0x0, sum = 2
6844 18:02:46.820428 15, 0x0, sum = 3
6845 18:02:46.820538 16, 0x0, sum = 4
6846 18:02:46.823671 best_step = 14
6847 18:02:46.823774
6848 18:02:46.823869 ==
6849 18:02:46.826988 Dram Type= 6, Freq= 0, CH_1, rank 0
6850 18:02:46.830307 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6851 18:02:46.830388 ==
6852 18:02:46.833643 RX Vref Scan: 1
6853 18:02:46.833728
6854 18:02:46.833795 RX Vref 0 -> 0, step: 1
6855 18:02:46.833857
6856 18:02:46.836718 RX Delay -327 -> 252, step: 8
6857 18:02:46.836803
6858 18:02:46.840044 Set Vref, RX VrefLevel [Byte0]: 53
6859 18:02:46.843326 [Byte1]: 52
6860 18:02:46.847822
6861 18:02:46.847899 Final RX Vref Byte 0 = 53 to rank0
6862 18:02:46.851127 Final RX Vref Byte 1 = 52 to rank0
6863 18:02:46.854411 Final RX Vref Byte 0 = 53 to rank1
6864 18:02:46.858227 Final RX Vref Byte 1 = 52 to rank1==
6865 18:02:46.861481 Dram Type= 6, Freq= 0, CH_1, rank 0
6866 18:02:46.867785 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6867 18:02:46.867888 ==
6868 18:02:46.867959 DQS Delay:
6869 18:02:46.870927 DQS0 = 32, DQS1 = 40
6870 18:02:46.871011 DQM Delay:
6871 18:02:46.871078 DQM0 = 11, DQM1 = 12
6872 18:02:46.874654 DQ Delay:
6873 18:02:46.877914 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6874 18:02:46.878006 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =8
6875 18:02:46.881221 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6876 18:02:46.884377 DQ12 =20, DQ13 =20, DQ14 =16, DQ15 =20
6877 18:02:46.884460
6878 18:02:46.887677
6879 18:02:46.894181 [DQSOSCAuto] RK0, (LSB)MR18= 0x95cf, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 391 ps
6880 18:02:46.897538 CH1 RK0: MR19=C0C, MR18=95CF
6881 18:02:46.904108 CH1_RK0: MR19=0xC0C, MR18=0x95CF, DQSOSC=384, MR23=63, INC=400, DEC=267
6882 18:02:46.904276 ==
6883 18:02:46.907664 Dram Type= 6, Freq= 0, CH_1, rank 1
6884 18:02:46.910839 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6885 18:02:46.910930 ==
6886 18:02:46.913991 [Gating] SW mode calibration
6887 18:02:46.921210 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6888 18:02:46.927385 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6889 18:02:46.930555 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6890 18:02:46.934470 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6891 18:02:46.940840 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6892 18:02:46.944133 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6893 18:02:46.947387 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6894 18:02:46.953955 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6895 18:02:46.957335 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6896 18:02:46.960490 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6897 18:02:46.963908 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6898 18:02:46.967138 Total UI for P1: 0, mck2ui 16
6899 18:02:46.970813 best dqsien dly found for B0: ( 0, 14, 24)
6900 18:02:46.973747 Total UI for P1: 0, mck2ui 16
6901 18:02:46.977046 best dqsien dly found for B1: ( 0, 14, 24)
6902 18:02:46.980879 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6903 18:02:46.987562 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6904 18:02:46.987642
6905 18:02:46.990846 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6906 18:02:46.994092 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6907 18:02:46.997415 [Gating] SW calibration Done
6908 18:02:46.997499 ==
6909 18:02:47.000732 Dram Type= 6, Freq= 0, CH_1, rank 1
6910 18:02:47.003951 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6911 18:02:47.004037 ==
6912 18:02:47.004103 RX Vref Scan: 0
6913 18:02:47.007155
6914 18:02:47.007230 RX Vref 0 -> 0, step: 1
6915 18:02:47.007293
6916 18:02:47.010464 RX Delay -410 -> 252, step: 16
6917 18:02:47.014134 iDelay=230, Bit 0, Center -11 (-234 ~ 213) 448
6918 18:02:47.020537 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6919 18:02:47.023568 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6920 18:02:47.027421 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6921 18:02:47.030535 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6922 18:02:47.036954 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6923 18:02:47.040287 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6924 18:02:47.043556 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6925 18:02:47.046879 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6926 18:02:47.053563 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6927 18:02:47.056957 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6928 18:02:47.060401 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6929 18:02:47.063639 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6930 18:02:47.070042 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6931 18:02:47.073459 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6932 18:02:47.076654 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6933 18:02:47.076733 ==
6934 18:02:47.080271 Dram Type= 6, Freq= 0, CH_1, rank 1
6935 18:02:47.086810 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6936 18:02:47.086895 ==
6937 18:02:47.086960 DQS Delay:
6938 18:02:47.090099 DQS0 = 35, DQS1 = 43
6939 18:02:47.090179 DQM Delay:
6940 18:02:47.090245 DQM0 = 18, DQM1 = 18
6941 18:02:47.093325 DQ Delay:
6942 18:02:47.096495 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6943 18:02:47.099749 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16
6944 18:02:47.103589 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6945 18:02:47.106910 DQ12 =32, DQ13 =24, DQ14 =16, DQ15 =32
6946 18:02:47.106988
6947 18:02:47.107052
6948 18:02:47.107123 ==
6949 18:02:47.110103 Dram Type= 6, Freq= 0, CH_1, rank 1
6950 18:02:47.113037 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6951 18:02:47.113142 ==
6952 18:02:47.113241
6953 18:02:47.113339
6954 18:02:47.116509 TX Vref Scan disable
6955 18:02:47.116615 == TX Byte 0 ==
6956 18:02:47.120009 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6957 18:02:47.126341 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6958 18:02:47.126421 == TX Byte 1 ==
6959 18:02:47.130120 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6960 18:02:47.136410 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6961 18:02:47.136521 ==
6962 18:02:47.139988 Dram Type= 6, Freq= 0, CH_1, rank 1
6963 18:02:47.143344 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6964 18:02:47.143425 ==
6965 18:02:47.143492
6966 18:02:47.143553
6967 18:02:47.146670 TX Vref Scan disable
6968 18:02:47.146746 == TX Byte 0 ==
6969 18:02:47.153391 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6970 18:02:47.156283 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6971 18:02:47.156364 == TX Byte 1 ==
6972 18:02:47.159975 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6973 18:02:47.166592 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6974 18:02:47.166670
6975 18:02:47.166745 [DATLAT]
6976 18:02:47.169710 Freq=400, CH1 RK1
6977 18:02:47.169792
6978 18:02:47.169859 DATLAT Default: 0xe
6979 18:02:47.172923 0, 0xFFFF, sum = 0
6980 18:02:47.173004 1, 0xFFFF, sum = 0
6981 18:02:47.176147 2, 0xFFFF, sum = 0
6982 18:02:47.176224 3, 0xFFFF, sum = 0
6983 18:02:47.179402 4, 0xFFFF, sum = 0
6984 18:02:47.179479 5, 0xFFFF, sum = 0
6985 18:02:47.183082 6, 0xFFFF, sum = 0
6986 18:02:47.183159 7, 0xFFFF, sum = 0
6987 18:02:47.186161 8, 0xFFFF, sum = 0
6988 18:02:47.186238 9, 0xFFFF, sum = 0
6989 18:02:47.189427 10, 0xFFFF, sum = 0
6990 18:02:47.189516 11, 0xFFFF, sum = 0
6991 18:02:47.192647 12, 0xFFFF, sum = 0
6992 18:02:47.192754 13, 0x0, sum = 1
6993 18:02:47.195983 14, 0x0, sum = 2
6994 18:02:47.196091 15, 0x0, sum = 3
6995 18:02:47.199273 16, 0x0, sum = 4
6996 18:02:47.199379 best_step = 14
6997 18:02:47.199470
6998 18:02:47.199561 ==
6999 18:02:47.202490 Dram Type= 6, Freq= 0, CH_1, rank 1
7000 18:02:47.209458 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7001 18:02:47.209559 ==
7002 18:02:47.209655 RX Vref Scan: 0
7003 18:02:47.209743
7004 18:02:47.212860 RX Vref 0 -> 0, step: 1
7005 18:02:47.212958
7006 18:02:47.216088 RX Delay -327 -> 252, step: 8
7007 18:02:47.222521 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
7008 18:02:47.226193 iDelay=217, Bit 1, Center -24 (-247 ~ 200) 448
7009 18:02:47.229057 iDelay=217, Bit 2, Center -32 (-255 ~ 192) 448
7010 18:02:47.232676 iDelay=217, Bit 3, Center -16 (-239 ~ 208) 448
7011 18:02:47.239137 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
7012 18:02:47.242766 iDelay=217, Bit 5, Center -8 (-231 ~ 216) 448
7013 18:02:47.245944 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
7014 18:02:47.249237 iDelay=217, Bit 7, Center -20 (-239 ~ 200) 440
7015 18:02:47.255613 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
7016 18:02:47.259406 iDelay=217, Bit 9, Center -36 (-263 ~ 192) 456
7017 18:02:47.262605 iDelay=217, Bit 10, Center -24 (-247 ~ 200) 448
7018 18:02:47.265874 iDelay=217, Bit 11, Center -28 (-255 ~ 200) 456
7019 18:02:47.272216 iDelay=217, Bit 12, Center -20 (-247 ~ 208) 456
7020 18:02:47.275837 iDelay=217, Bit 13, Center -20 (-247 ~ 208) 456
7021 18:02:47.279211 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
7022 18:02:47.285596 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
7023 18:02:47.285700 ==
7024 18:02:47.289302 Dram Type= 6, Freq= 0, CH_1, rank 1
7025 18:02:47.292406 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7026 18:02:47.292506 ==
7027 18:02:47.292605 DQS Delay:
7028 18:02:47.295649 DQS0 = 32, DQS1 = 36
7029 18:02:47.295738 DQM Delay:
7030 18:02:47.298993 DQM0 = 14, DQM1 = 11
7031 18:02:47.299080 DQ Delay:
7032 18:02:47.302340 DQ0 =20, DQ1 =8, DQ2 =0, DQ3 =16
7033 18:02:47.305488 DQ4 =16, DQ5 =24, DQ6 =20, DQ7 =12
7034 18:02:47.308665 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =8
7035 18:02:47.312491 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =24
7036 18:02:47.312591
7037 18:02:47.312676
7038 18:02:47.319156 [DQSOSCAuto] RK1, (LSB)MR18= 0xa14b, (MSB)MR19= 0xc0c, tDQSOscB0 = 400 ps tDQSOscB1 = 389 ps
7039 18:02:47.322223 CH1 RK1: MR19=C0C, MR18=A14B
7040 18:02:47.328966 CH1_RK1: MR19=0xC0C, MR18=0xA14B, DQSOSC=389, MR23=63, INC=390, DEC=260
7041 18:02:47.332199 [RxdqsGatingPostProcess] freq 400
7042 18:02:47.338877 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7043 18:02:47.338969 best DQS0 dly(2T, 0.5T) = (0, 10)
7044 18:02:47.342207 best DQS1 dly(2T, 0.5T) = (0, 10)
7045 18:02:47.345326 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7046 18:02:47.348906 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7047 18:02:47.352217 best DQS0 dly(2T, 0.5T) = (0, 10)
7048 18:02:47.355400 best DQS1 dly(2T, 0.5T) = (0, 10)
7049 18:02:47.358601 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7050 18:02:47.361950 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7051 18:02:47.365273 Pre-setting of DQS Precalculation
7052 18:02:47.372317 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7053 18:02:47.378734 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7054 18:02:47.385178 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7055 18:02:47.385265
7056 18:02:47.385331
7057 18:02:47.388421 [Calibration Summary] 800 Mbps
7058 18:02:47.388496 CH 0, Rank 0
7059 18:02:47.392163 SW Impedance : PASS
7060 18:02:47.392236 DUTY Scan : NO K
7061 18:02:47.395421 ZQ Calibration : PASS
7062 18:02:47.398539 Jitter Meter : NO K
7063 18:02:47.398624 CBT Training : PASS
7064 18:02:47.401911 Write leveling : PASS
7065 18:02:47.405217 RX DQS gating : PASS
7066 18:02:47.405295 RX DQ/DQS(RDDQC) : PASS
7067 18:02:47.408491 TX DQ/DQS : PASS
7068 18:02:47.411723 RX DATLAT : PASS
7069 18:02:47.411802 RX DQ/DQS(Engine): PASS
7070 18:02:47.415106 TX OE : NO K
7071 18:02:47.415184 All Pass.
7072 18:02:47.415255
7073 18:02:47.418335 CH 0, Rank 1
7074 18:02:47.418418 SW Impedance : PASS
7075 18:02:47.421574 DUTY Scan : NO K
7076 18:02:47.424904 ZQ Calibration : PASS
7077 18:02:47.424989 Jitter Meter : NO K
7078 18:02:47.428124 CBT Training : PASS
7079 18:02:47.431711 Write leveling : NO K
7080 18:02:47.431796 RX DQS gating : PASS
7081 18:02:47.434818 RX DQ/DQS(RDDQC) : PASS
7082 18:02:47.438073 TX DQ/DQS : PASS
7083 18:02:47.438152 RX DATLAT : PASS
7084 18:02:47.441660 RX DQ/DQS(Engine): PASS
7085 18:02:47.444898 TX OE : NO K
7086 18:02:47.444976 All Pass.
7087 18:02:47.445039
7088 18:02:47.445107 CH 1, Rank 0
7089 18:02:47.448105 SW Impedance : PASS
7090 18:02:47.451334 DUTY Scan : NO K
7091 18:02:47.451424 ZQ Calibration : PASS
7092 18:02:47.454926 Jitter Meter : NO K
7093 18:02:47.455003 CBT Training : PASS
7094 18:02:47.458271 Write leveling : PASS
7095 18:02:47.461492 RX DQS gating : PASS
7096 18:02:47.461575 RX DQ/DQS(RDDQC) : PASS
7097 18:02:47.464680 TX DQ/DQS : PASS
7098 18:02:47.468010 RX DATLAT : PASS
7099 18:02:47.468093 RX DQ/DQS(Engine): PASS
7100 18:02:47.471299 TX OE : NO K
7101 18:02:47.471380 All Pass.
7102 18:02:47.471444
7103 18:02:47.474706 CH 1, Rank 1
7104 18:02:47.474786 SW Impedance : PASS
7105 18:02:47.477895 DUTY Scan : NO K
7106 18:02:47.481330 ZQ Calibration : PASS
7107 18:02:47.481435 Jitter Meter : NO K
7108 18:02:47.484502 CBT Training : PASS
7109 18:02:47.488456 Write leveling : NO K
7110 18:02:47.488570 RX DQS gating : PASS
7111 18:02:47.491142 RX DQ/DQS(RDDQC) : PASS
7112 18:02:47.494871 TX DQ/DQS : PASS
7113 18:02:47.494954 RX DATLAT : PASS
7114 18:02:47.498153 RX DQ/DQS(Engine): PASS
7115 18:02:47.498234 TX OE : NO K
7116 18:02:47.501283 All Pass.
7117 18:02:47.501381
7118 18:02:47.501448 DramC Write-DBI off
7119 18:02:47.504465 PER_BANK_REFRESH: Hybrid Mode
7120 18:02:47.507772 TX_TRACKING: ON
7121 18:02:47.514304 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7122 18:02:47.518183 [FAST_K] Save calibration result to emmc
7123 18:02:47.524335 dramc_set_vcore_voltage set vcore to 725000
7124 18:02:47.524422 Read voltage for 1600, 0
7125 18:02:47.527592 Vio18 = 0
7126 18:02:47.527667 Vcore = 725000
7127 18:02:47.527740 Vdram = 0
7128 18:02:47.527804 Vddq = 0
7129 18:02:47.531319 Vmddr = 0
7130 18:02:47.534549 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7131 18:02:47.540836 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7132 18:02:47.544539 MEM_TYPE=3, freq_sel=13
7133 18:02:47.544634 sv_algorithm_assistance_LP4_3733
7134 18:02:47.550895 ============ PULL DRAM RESETB DOWN ============
7135 18:02:47.554463 ========== PULL DRAM RESETB DOWN end =========
7136 18:02:47.557683 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7137 18:02:47.560959 ===================================
7138 18:02:47.564225 LPDDR4 DRAM CONFIGURATION
7139 18:02:47.567452 ===================================
7140 18:02:47.571320 EX_ROW_EN[0] = 0x0
7141 18:02:47.571396 EX_ROW_EN[1] = 0x0
7142 18:02:47.574075 LP4Y_EN = 0x0
7143 18:02:47.574152 WORK_FSP = 0x1
7144 18:02:47.577827 WL = 0x5
7145 18:02:47.577913 RL = 0x5
7146 18:02:47.581103 BL = 0x2
7147 18:02:47.581180 RPST = 0x0
7148 18:02:47.584310 RD_PRE = 0x0
7149 18:02:47.584399 WR_PRE = 0x1
7150 18:02:47.587469 WR_PST = 0x1
7151 18:02:47.587558 DBI_WR = 0x0
7152 18:02:47.591035 DBI_RD = 0x0
7153 18:02:47.591126 OTF = 0x1
7154 18:02:47.594300 ===================================
7155 18:02:47.597622 ===================================
7156 18:02:47.600870 ANA top config
7157 18:02:47.604495 ===================================
7158 18:02:47.607727 DLL_ASYNC_EN = 0
7159 18:02:47.607803 ALL_SLAVE_EN = 0
7160 18:02:47.611022 NEW_RANK_MODE = 1
7161 18:02:47.614283 DLL_IDLE_MODE = 1
7162 18:02:47.618012 LP45_APHY_COMB_EN = 1
7163 18:02:47.618179 TX_ODT_DIS = 0
7164 18:02:47.621305 NEW_8X_MODE = 1
7165 18:02:47.624574 ===================================
7166 18:02:47.627888 ===================================
7167 18:02:47.631241 data_rate = 3200
7168 18:02:47.634568 CKR = 1
7169 18:02:47.637714 DQ_P2S_RATIO = 8
7170 18:02:47.640810 ===================================
7171 18:02:47.644068 CA_P2S_RATIO = 8
7172 18:02:47.644157 DQ_CA_OPEN = 0
7173 18:02:47.647587 DQ_SEMI_OPEN = 0
7174 18:02:47.651177 CA_SEMI_OPEN = 0
7175 18:02:47.654129 CA_FULL_RATE = 0
7176 18:02:47.657405 DQ_CKDIV4_EN = 0
7177 18:02:47.660492 CA_CKDIV4_EN = 0
7178 18:02:47.660636 CA_PREDIV_EN = 0
7179 18:02:47.664269 PH8_DLY = 12
7180 18:02:47.667127 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7181 18:02:47.670864 DQ_AAMCK_DIV = 4
7182 18:02:47.674314 CA_AAMCK_DIV = 4
7183 18:02:47.677067 CA_ADMCK_DIV = 4
7184 18:02:47.677201 DQ_TRACK_CA_EN = 0
7185 18:02:47.680426 CA_PICK = 1600
7186 18:02:47.683716 CA_MCKIO = 1600
7187 18:02:47.687073 MCKIO_SEMI = 0
7188 18:02:47.690363 PLL_FREQ = 3068
7189 18:02:47.693750 DQ_UI_PI_RATIO = 32
7190 18:02:47.696967 CA_UI_PI_RATIO = 0
7191 18:02:47.700306 ===================================
7192 18:02:47.704204 ===================================
7193 18:02:47.704307 memory_type:LPDDR4
7194 18:02:47.707407 GP_NUM : 10
7195 18:02:47.710570 SRAM_EN : 1
7196 18:02:47.710673 MD32_EN : 0
7197 18:02:47.713682 ===================================
7198 18:02:47.716987 [ANA_INIT] >>>>>>>>>>>>>>
7199 18:02:47.720338 <<<<<< [CONFIGURE PHASE]: ANA_TX
7200 18:02:47.723708 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7201 18:02:47.727031 ===================================
7202 18:02:47.730249 data_rate = 3200,PCW = 0X7600
7203 18:02:47.733595 ===================================
7204 18:02:47.737034 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7205 18:02:47.740243 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7206 18:02:47.746766 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7207 18:02:47.750285 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7208 18:02:47.753441 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7209 18:02:47.760155 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7210 18:02:47.760246 [ANA_INIT] flow start
7211 18:02:47.763243 [ANA_INIT] PLL >>>>>>>>
7212 18:02:47.766377 [ANA_INIT] PLL <<<<<<<<
7213 18:02:47.766461 [ANA_INIT] MIDPI >>>>>>>>
7214 18:02:47.770157 [ANA_INIT] MIDPI <<<<<<<<
7215 18:02:47.773432 [ANA_INIT] DLL >>>>>>>>
7216 18:02:47.773515 [ANA_INIT] DLL <<<<<<<<
7217 18:02:47.776837 [ANA_INIT] flow end
7218 18:02:47.780157 ============ LP4 DIFF to SE enter ============
7219 18:02:47.783207 ============ LP4 DIFF to SE exit ============
7220 18:02:47.786539 [ANA_INIT] <<<<<<<<<<<<<
7221 18:02:47.789925 [Flow] Enable top DCM control >>>>>
7222 18:02:47.793216 [Flow] Enable top DCM control <<<<<
7223 18:02:47.796283 Enable DLL master slave shuffle
7224 18:02:47.803155 ==============================================================
7225 18:02:47.803266 Gating Mode config
7226 18:02:47.809573 ==============================================================
7227 18:02:47.809667 Config description:
7228 18:02:47.819952 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7229 18:02:47.826341 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7230 18:02:47.832897 SELPH_MODE 0: By rank 1: By Phase
7231 18:02:47.836213 ==============================================================
7232 18:02:47.839367 GAT_TRACK_EN = 1
7233 18:02:47.842740 RX_GATING_MODE = 2
7234 18:02:47.845985 RX_GATING_TRACK_MODE = 2
7235 18:02:47.849296 SELPH_MODE = 1
7236 18:02:47.852942 PICG_EARLY_EN = 1
7237 18:02:47.856109 VALID_LAT_VALUE = 1
7238 18:02:47.862824 ==============================================================
7239 18:02:47.866169 Enter into Gating configuration >>>>
7240 18:02:47.869421 Exit from Gating configuration <<<<
7241 18:02:47.873091 Enter into DVFS_PRE_config >>>>>
7242 18:02:47.882817 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7243 18:02:47.885982 Exit from DVFS_PRE_config <<<<<
7244 18:02:47.889368 Enter into PICG configuration >>>>
7245 18:02:47.892818 Exit from PICG configuration <<<<
7246 18:02:47.892900 [RX_INPUT] configuration >>>>>
7247 18:02:47.896140 [RX_INPUT] configuration <<<<<
7248 18:02:47.902529 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7249 18:02:47.909461 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7250 18:02:47.912768 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7251 18:02:47.919162 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7252 18:02:47.925542 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7253 18:02:47.932191 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7254 18:02:47.935533 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7255 18:02:47.938882 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7256 18:02:47.945395 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7257 18:02:47.948645 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7258 18:02:47.951995 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7259 18:02:47.958734 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7260 18:02:47.962004 ===================================
7261 18:02:47.962118 LPDDR4 DRAM CONFIGURATION
7262 18:02:47.965174 ===================================
7263 18:02:47.968834 EX_ROW_EN[0] = 0x0
7264 18:02:47.968936 EX_ROW_EN[1] = 0x0
7265 18:02:47.972085 LP4Y_EN = 0x0
7266 18:02:47.972160 WORK_FSP = 0x1
7267 18:02:47.975340 WL = 0x5
7268 18:02:47.978551 RL = 0x5
7269 18:02:47.978636 BL = 0x2
7270 18:02:47.981892 RPST = 0x0
7271 18:02:47.981979 RD_PRE = 0x0
7272 18:02:47.985320 WR_PRE = 0x1
7273 18:02:47.985405 WR_PST = 0x1
7274 18:02:47.988386 DBI_WR = 0x0
7275 18:02:47.988494 DBI_RD = 0x0
7276 18:02:47.991586 OTF = 0x1
7277 18:02:47.994945 ===================================
7278 18:02:47.998290 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7279 18:02:48.002252 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7280 18:02:48.005359 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7281 18:02:48.008567 ===================================
7282 18:02:48.011837 LPDDR4 DRAM CONFIGURATION
7283 18:02:48.015089 ===================================
7284 18:02:48.018340 EX_ROW_EN[0] = 0x10
7285 18:02:48.018449 EX_ROW_EN[1] = 0x0
7286 18:02:48.021567 LP4Y_EN = 0x0
7287 18:02:48.021671 WORK_FSP = 0x1
7288 18:02:48.025097 WL = 0x5
7289 18:02:48.025201 RL = 0x5
7290 18:02:48.028244 BL = 0x2
7291 18:02:48.031539 RPST = 0x0
7292 18:02:48.031643 RD_PRE = 0x0
7293 18:02:48.034833 WR_PRE = 0x1
7294 18:02:48.034938 WR_PST = 0x1
7295 18:02:48.038297 DBI_WR = 0x0
7296 18:02:48.038399 DBI_RD = 0x0
7297 18:02:48.041387 OTF = 0x1
7298 18:02:48.044716 ===================================
7299 18:02:48.048117 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7300 18:02:48.051347 ==
7301 18:02:48.054690 Dram Type= 6, Freq= 0, CH_0, rank 0
7302 18:02:48.057767 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7303 18:02:48.057877 ==
7304 18:02:48.061379 [Duty_Offset_Calibration]
7305 18:02:48.061487 B0:2 B1:0 CA:1
7306 18:02:48.061586
7307 18:02:48.064607 [DutyScan_Calibration_Flow] k_type=0
7308 18:02:48.074593
7309 18:02:48.074737 ==CLK 0==
7310 18:02:48.077894 Final CLK duty delay cell = 0
7311 18:02:48.081223 [0] MAX Duty = 5187%(X100), DQS PI = 20
7312 18:02:48.084854 [0] MIN Duty = 5031%(X100), DQS PI = 0
7313 18:02:48.084941 [0] AVG Duty = 5109%(X100)
7314 18:02:48.088106
7315 18:02:48.091299 CH0 CLK Duty spec in!! Max-Min= 156%
7316 18:02:48.094423 [DutyScan_Calibration_Flow] ====Done====
7317 18:02:48.094510
7318 18:02:48.097790 [DutyScan_Calibration_Flow] k_type=1
7319 18:02:48.113892
7320 18:02:48.113984 ==DQS 0 ==
7321 18:02:48.117069 Final DQS duty delay cell = 0
7322 18:02:48.120374 [0] MAX Duty = 5218%(X100), DQS PI = 32
7323 18:02:48.123766 [0] MIN Duty = 4938%(X100), DQS PI = 0
7324 18:02:48.123863 [0] AVG Duty = 5078%(X100)
7325 18:02:48.126935
7326 18:02:48.127021 ==DQS 1 ==
7327 18:02:48.130605 Final DQS duty delay cell = -4
7328 18:02:48.133938 [-4] MAX Duty = 5094%(X100), DQS PI = 28
7329 18:02:48.137288 [-4] MIN Duty = 4844%(X100), DQS PI = 6
7330 18:02:48.140465 [-4] AVG Duty = 4969%(X100)
7331 18:02:48.140559
7332 18:02:48.143691 CH0 DQS 0 Duty spec in!! Max-Min= 280%
7333 18:02:48.143778
7334 18:02:48.146947 CH0 DQS 1 Duty spec in!! Max-Min= 250%
7335 18:02:48.150156 [DutyScan_Calibration_Flow] ====Done====
7336 18:02:48.150243
7337 18:02:48.153415 [DutyScan_Calibration_Flow] k_type=3
7338 18:02:48.171099
7339 18:02:48.171210 ==DQM 0 ==
7340 18:02:48.174323 Final DQM duty delay cell = 0
7341 18:02:48.177924 [0] MAX Duty = 5093%(X100), DQS PI = 26
7342 18:02:48.181192 [0] MIN Duty = 4813%(X100), DQS PI = 50
7343 18:02:48.184327 [0] AVG Duty = 4953%(X100)
7344 18:02:48.184404
7345 18:02:48.184468 ==DQM 1 ==
7346 18:02:48.187578 Final DQM duty delay cell = 0
7347 18:02:48.190946 [0] MAX Duty = 5249%(X100), DQS PI = 44
7348 18:02:48.194183 [0] MIN Duty = 5000%(X100), DQS PI = 20
7349 18:02:48.198016 [0] AVG Duty = 5124%(X100)
7350 18:02:48.198100
7351 18:02:48.201315 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7352 18:02:48.201401
7353 18:02:48.204406 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7354 18:02:48.207718 [DutyScan_Calibration_Flow] ====Done====
7355 18:02:48.207806
7356 18:02:48.210929 [DutyScan_Calibration_Flow] k_type=2
7357 18:02:48.228447
7358 18:02:48.228528 ==DQ 0 ==
7359 18:02:48.231739 Final DQ duty delay cell = 0
7360 18:02:48.235276 [0] MAX Duty = 5124%(X100), DQS PI = 34
7361 18:02:48.238801 [0] MIN Duty = 5000%(X100), DQS PI = 0
7362 18:02:48.238879 [0] AVG Duty = 5062%(X100)
7363 18:02:48.238942
7364 18:02:48.241469 ==DQ 1 ==
7365 18:02:48.245250 Final DQ duty delay cell = 0
7366 18:02:48.248450 [0] MAX Duty = 4969%(X100), DQS PI = 44
7367 18:02:48.251717 [0] MIN Duty = 4875%(X100), DQS PI = 8
7368 18:02:48.251794 [0] AVG Duty = 4922%(X100)
7369 18:02:48.251866
7370 18:02:48.254970 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7371 18:02:48.258227
7372 18:02:48.261551 CH0 DQ 1 Duty spec in!! Max-Min= 94%
7373 18:02:48.264783 [DutyScan_Calibration_Flow] ====Done====
7374 18:02:48.264866 ==
7375 18:02:48.268470 Dram Type= 6, Freq= 0, CH_1, rank 0
7376 18:02:48.271505 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7377 18:02:48.271591 ==
7378 18:02:48.274994 [Duty_Offset_Calibration]
7379 18:02:48.275071 B0:0 B1:-1 CA:2
7380 18:02:48.275144
7381 18:02:48.278097 [DutyScan_Calibration_Flow] k_type=0
7382 18:02:48.288741
7383 18:02:48.288820 ==CLK 0==
7384 18:02:48.292116 Final CLK duty delay cell = 0
7385 18:02:48.295089 [0] MAX Duty = 5156%(X100), DQS PI = 10
7386 18:02:48.298408 [0] MIN Duty = 4906%(X100), DQS PI = 46
7387 18:02:48.298496 [0] AVG Duty = 5031%(X100)
7388 18:02:48.301644
7389 18:02:48.305399 CH1 CLK Duty spec in!! Max-Min= 250%
7390 18:02:48.308540 [DutyScan_Calibration_Flow] ====Done====
7391 18:02:48.308639
7392 18:02:48.311959 [DutyScan_Calibration_Flow] k_type=1
7393 18:02:48.328152
7394 18:02:48.328269 ==DQS 0 ==
7395 18:02:48.331390 Final DQS duty delay cell = 0
7396 18:02:48.335164 [0] MAX Duty = 5093%(X100), DQS PI = 24
7397 18:02:48.338361 [0] MIN Duty = 4969%(X100), DQS PI = 16
7398 18:02:48.341493 [0] AVG Duty = 5031%(X100)
7399 18:02:48.341569
7400 18:02:48.341633 ==DQS 1 ==
7401 18:02:48.344761 Final DQS duty delay cell = 0
7402 18:02:48.348142 [0] MAX Duty = 5187%(X100), DQS PI = 0
7403 18:02:48.351252 [0] MIN Duty = 4844%(X100), DQS PI = 32
7404 18:02:48.354596 [0] AVG Duty = 5015%(X100)
7405 18:02:48.354678
7406 18:02:48.357833 CH1 DQS 0 Duty spec in!! Max-Min= 124%
7407 18:02:48.357907
7408 18:02:48.361262 CH1 DQS 1 Duty spec in!! Max-Min= 343%
7409 18:02:48.364649 [DutyScan_Calibration_Flow] ====Done====
7410 18:02:48.364722
7411 18:02:48.367938 [DutyScan_Calibration_Flow] k_type=3
7412 18:02:48.385951
7413 18:02:48.386069 ==DQM 0 ==
7414 18:02:48.389097 Final DQM duty delay cell = 4
7415 18:02:48.392307 [4] MAX Duty = 5125%(X100), DQS PI = 22
7416 18:02:48.395565 [4] MIN Duty = 4969%(X100), DQS PI = 32
7417 18:02:48.398958 [4] AVG Duty = 5047%(X100)
7418 18:02:48.399042
7419 18:02:48.399108 ==DQM 1 ==
7420 18:02:48.402703 Final DQM duty delay cell = 0
7421 18:02:48.405968 [0] MAX Duty = 5281%(X100), DQS PI = 58
7422 18:02:48.409377 [0] MIN Duty = 4844%(X100), DQS PI = 34
7423 18:02:48.412493 [0] AVG Duty = 5062%(X100)
7424 18:02:48.412600
7425 18:02:48.415923 CH1 DQM 0 Duty spec in!! Max-Min= 156%
7426 18:02:48.416007
7427 18:02:48.419281 CH1 DQM 1 Duty spec in!! Max-Min= 437%
7428 18:02:48.422514 [DutyScan_Calibration_Flow] ====Done====
7429 18:02:48.422599
7430 18:02:48.425691 [DutyScan_Calibration_Flow] k_type=2
7431 18:02:48.442685
7432 18:02:48.442771 ==DQ 0 ==
7433 18:02:48.445982 Final DQ duty delay cell = 0
7434 18:02:48.449687 [0] MAX Duty = 5093%(X100), DQS PI = 22
7435 18:02:48.452911 [0] MIN Duty = 4969%(X100), DQS PI = 0
7436 18:02:48.452997 [0] AVG Duty = 5031%(X100)
7437 18:02:48.453064
7438 18:02:48.456227 ==DQ 1 ==
7439 18:02:48.459515 Final DQ duty delay cell = 0
7440 18:02:48.462815 [0] MAX Duty = 5062%(X100), DQS PI = 2
7441 18:02:48.466196 [0] MIN Duty = 4813%(X100), DQS PI = 32
7442 18:02:48.466285 [0] AVG Duty = 4937%(X100)
7443 18:02:48.466351
7444 18:02:48.469481 CH1 DQ 0 Duty spec in!! Max-Min= 124%
7445 18:02:48.469580
7446 18:02:48.472697 CH1 DQ 1 Duty spec in!! Max-Min= 249%
7447 18:02:48.479688 [DutyScan_Calibration_Flow] ====Done====
7448 18:02:48.482688 nWR fixed to 30
7449 18:02:48.482774 [ModeRegInit_LP4] CH0 RK0
7450 18:02:48.486271 [ModeRegInit_LP4] CH0 RK1
7451 18:02:48.489475 [ModeRegInit_LP4] CH1 RK0
7452 18:02:48.489560 [ModeRegInit_LP4] CH1 RK1
7453 18:02:48.492585 match AC timing 5
7454 18:02:48.495850 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7455 18:02:48.499154 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7456 18:02:48.506228 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7457 18:02:48.509488 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7458 18:02:48.516002 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7459 18:02:48.516116 [MiockJmeterHQA]
7460 18:02:48.516216
7461 18:02:48.519301 [DramcMiockJmeter] u1RxGatingPI = 0
7462 18:02:48.522656 0 : 4253, 4026
7463 18:02:48.522732 4 : 4252, 4027
7464 18:02:48.522803 8 : 4252, 4027
7465 18:02:48.525928 12 : 4253, 4026
7466 18:02:48.526005 16 : 4253, 4027
7467 18:02:48.529263 20 : 4363, 4137
7468 18:02:48.529340 24 : 4252, 4027
7469 18:02:48.532384 28 : 4253, 4026
7470 18:02:48.532463 32 : 4252, 4027
7471 18:02:48.535509 36 : 4254, 4029
7472 18:02:48.535585 40 : 4252, 4027
7473 18:02:48.535656 44 : 4363, 4138
7474 18:02:48.539209 48 : 4363, 4137
7475 18:02:48.539291 52 : 4253, 4027
7476 18:02:48.542516 56 : 4252, 4026
7477 18:02:48.542627 60 : 4252, 4027
7478 18:02:48.545644 64 : 4253, 4027
7479 18:02:48.545721 68 : 4253, 4029
7480 18:02:48.548893 72 : 4361, 4137
7481 18:02:48.548968 76 : 4250, 4027
7482 18:02:48.549031 80 : 4250, 4027
7483 18:02:48.552518 84 : 4250, 4027
7484 18:02:48.552640 88 : 4252, 3499
7485 18:02:48.555895 92 : 4250, 0
7486 18:02:48.555981 96 : 4251, 0
7487 18:02:48.556084 100 : 4252, 0
7488 18:02:48.559297 104 : 4363, 0
7489 18:02:48.559401 108 : 4250, 0
7490 18:02:48.562104 112 : 4360, 0
7491 18:02:48.562189 116 : 4250, 0
7492 18:02:48.562256 120 : 4252, 0
7493 18:02:48.565798 124 : 4250, 0
7494 18:02:48.565883 128 : 4250, 0
7495 18:02:48.569109 132 : 4250, 0
7496 18:02:48.569194 136 : 4250, 0
7497 18:02:48.569261 140 : 4363, 0
7498 18:02:48.572259 144 : 4250, 0
7499 18:02:48.572375 148 : 4250, 0
7500 18:02:48.572480 152 : 4252, 0
7501 18:02:48.575535 156 : 4250, 0
7502 18:02:48.575609 160 : 4361, 0
7503 18:02:48.578841 164 : 4361, 0
7504 18:02:48.578926 168 : 4249, 0
7505 18:02:48.578993 172 : 4250, 0
7506 18:02:48.582119 176 : 4250, 0
7507 18:02:48.582204 180 : 4249, 0
7508 18:02:48.585302 184 : 4250, 0
7509 18:02:48.585387 188 : 4250, 0
7510 18:02:48.585454 192 : 4252, 0
7511 18:02:48.588937 196 : 4250, 0
7512 18:02:48.589048 200 : 4250, 10
7513 18:02:48.592197 204 : 4252, 2754
7514 18:02:48.592279 208 : 4361, 4137
7515 18:02:48.595760 212 : 4250, 4026
7516 18:02:48.595872 216 : 4250, 4027
7517 18:02:48.595970 220 : 4249, 4027
7518 18:02:48.598991 224 : 4252, 4029
7519 18:02:48.599115 228 : 4250, 4026
7520 18:02:48.602037 232 : 4250, 4027
7521 18:02:48.602115 236 : 4360, 4138
7522 18:02:48.605361 240 : 4250, 4027
7523 18:02:48.605437 244 : 4250, 4026
7524 18:02:48.608665 248 : 4361, 4137
7525 18:02:48.608741 252 : 4250, 4027
7526 18:02:48.612392 256 : 4249, 4027
7527 18:02:48.612496 260 : 4363, 4140
7528 18:02:48.615431 264 : 4250, 4026
7529 18:02:48.615535 268 : 4250, 4027
7530 18:02:48.618729 272 : 4250, 4027
7531 18:02:48.618808 276 : 4252, 4029
7532 18:02:48.622083 280 : 4250, 4026
7533 18:02:48.622159 284 : 4250, 4027
7534 18:02:48.622250 288 : 4361, 4138
7535 18:02:48.625239 292 : 4250, 4027
7536 18:02:48.625334 296 : 4250, 4026
7537 18:02:48.628504 300 : 4361, 4137
7538 18:02:48.628600 304 : 4250, 4027
7539 18:02:48.631740 308 : 4250, 4027
7540 18:02:48.631816 312 : 4363, 4050
7541 18:02:48.635413 316 : 4250, 1875
7542 18:02:48.635488
7543 18:02:48.635580 MIOCK jitter meter ch=0
7544 18:02:48.638430
7545 18:02:48.638500 1T = (316-92) = 224 dly cells
7546 18:02:48.645352 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7547 18:02:48.645430 ==
7548 18:02:48.648650 Dram Type= 6, Freq= 0, CH_0, rank 0
7549 18:02:48.651673 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7550 18:02:48.651746 ==
7551 18:02:48.658670 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7552 18:02:48.661956 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7553 18:02:48.665337 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7554 18:02:48.671852 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7555 18:02:48.681813 [CA 0] Center 43 (13~73) winsize 61
7556 18:02:48.685023 [CA 1] Center 43 (13~74) winsize 62
7557 18:02:48.688379 [CA 2] Center 38 (8~68) winsize 61
7558 18:02:48.691508 [CA 3] Center 37 (8~67) winsize 60
7559 18:02:48.694811 [CA 4] Center 37 (7~67) winsize 61
7560 18:02:48.698474 [CA 5] Center 36 (6~66) winsize 61
7561 18:02:48.698577
7562 18:02:48.701738 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7563 18:02:48.701823
7564 18:02:48.704827 [CATrainingPosCal] consider 1 rank data
7565 18:02:48.708014 u2DelayCellTimex100 = 290/100 ps
7566 18:02:48.714639 CA0 delay=43 (13~73),Diff = 7 PI (23 cell)
7567 18:02:48.718411 CA1 delay=43 (13~74),Diff = 7 PI (23 cell)
7568 18:02:48.721474 CA2 delay=38 (8~68),Diff = 2 PI (6 cell)
7569 18:02:48.724691 CA3 delay=37 (8~67),Diff = 1 PI (3 cell)
7570 18:02:48.727913 CA4 delay=37 (7~67),Diff = 1 PI (3 cell)
7571 18:02:48.731271 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7572 18:02:48.731352
7573 18:02:48.734560 CA PerBit enable=1, Macro0, CA PI delay=36
7574 18:02:48.734643
7575 18:02:48.738158 [CBTSetCACLKResult] CA Dly = 36
7576 18:02:48.741437 CS Dly: 9 (0~40)
7577 18:02:48.744512 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7578 18:02:48.747835 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7579 18:02:48.747918 ==
7580 18:02:48.751018 Dram Type= 6, Freq= 0, CH_0, rank 1
7581 18:02:48.754584 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7582 18:02:48.757576 ==
7583 18:02:48.761355 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7584 18:02:48.764492 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7585 18:02:48.771077 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7586 18:02:48.777538 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7587 18:02:48.785146 [CA 0] Center 43 (13~74) winsize 62
7588 18:02:48.788410 [CA 1] Center 43 (13~73) winsize 61
7589 18:02:48.791646 [CA 2] Center 38 (8~68) winsize 61
7590 18:02:48.794751 [CA 3] Center 38 (9~68) winsize 60
7591 18:02:48.798540 [CA 4] Center 36 (7~66) winsize 60
7592 18:02:48.801734 [CA 5] Center 36 (6~66) winsize 61
7593 18:02:48.801818
7594 18:02:48.804780 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7595 18:02:48.804865
7596 18:02:48.808463 [CATrainingPosCal] consider 2 rank data
7597 18:02:48.811703 u2DelayCellTimex100 = 290/100 ps
7598 18:02:48.814956 CA0 delay=43 (13~73),Diff = 7 PI (23 cell)
7599 18:02:48.821489 CA1 delay=43 (13~73),Diff = 7 PI (23 cell)
7600 18:02:48.825123 CA2 delay=38 (8~68),Diff = 2 PI (6 cell)
7601 18:02:48.828205 CA3 delay=38 (9~67),Diff = 2 PI (6 cell)
7602 18:02:48.831563 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7603 18:02:48.834717 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7604 18:02:48.834801
7605 18:02:48.838477 CA PerBit enable=1, Macro0, CA PI delay=36
7606 18:02:48.838560
7607 18:02:48.841623 [CBTSetCACLKResult] CA Dly = 36
7608 18:02:48.844853 CS Dly: 10 (0~43)
7609 18:02:48.848430 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7610 18:02:48.851509 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7611 18:02:48.851593
7612 18:02:48.854960 ----->DramcWriteLeveling(PI) begin...
7613 18:02:48.855044 ==
7614 18:02:48.858123 Dram Type= 6, Freq= 0, CH_0, rank 0
7615 18:02:48.861363 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7616 18:02:48.864940 ==
7617 18:02:48.868139 Write leveling (Byte 0): 36 => 36
7618 18:02:48.868222 Write leveling (Byte 1): 32 => 32
7619 18:02:48.871572 DramcWriteLeveling(PI) end<-----
7620 18:02:48.871656
7621 18:02:48.871721 ==
7622 18:02:48.874878 Dram Type= 6, Freq= 0, CH_0, rank 0
7623 18:02:48.881387 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7624 18:02:48.881492 ==
7625 18:02:48.884518 [Gating] SW mode calibration
7626 18:02:48.891575 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7627 18:02:48.894733 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7628 18:02:48.901537 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7629 18:02:48.904661 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7630 18:02:48.907686 1 4 8 | B1->B0 | 2323 2a2a | 0 1 | (0 0) (1 1)
7631 18:02:48.914415 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7632 18:02:48.918204 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7633 18:02:48.921483 1 4 20 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
7634 18:02:48.924689 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7635 18:02:48.931288 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7636 18:02:48.934527 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7637 18:02:48.937858 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7638 18:02:48.944397 1 5 8 | B1->B0 | 3434 2d2d | 1 0 | (1 1) (1 0)
7639 18:02:48.947699 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
7640 18:02:48.950961 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7641 18:02:48.957288 1 5 20 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
7642 18:02:48.961207 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7643 18:02:48.964359 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7644 18:02:48.970985 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7645 18:02:48.974215 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7646 18:02:48.977859 1 6 8 | B1->B0 | 2323 3737 | 0 0 | (0 0) (0 0)
7647 18:02:48.984246 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7648 18:02:48.987354 1 6 16 | B1->B0 | 2a2a 4646 | 0 0 | (0 0) (0 0)
7649 18:02:48.990730 1 6 20 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
7650 18:02:48.997305 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7651 18:02:49.000654 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7652 18:02:49.004349 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7653 18:02:49.010647 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7654 18:02:49.014131 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7655 18:02:49.017360 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7656 18:02:49.024260 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7657 18:02:49.027420 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7658 18:02:49.030622 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7659 18:02:49.037031 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7660 18:02:49.040892 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7661 18:02:49.044038 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7662 18:02:49.050752 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7663 18:02:49.053892 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7664 18:02:49.057117 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7665 18:02:49.064048 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7666 18:02:49.067245 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7667 18:02:49.070394 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7668 18:02:49.077060 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7669 18:02:49.080270 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7670 18:02:49.083606 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7671 18:02:49.086913 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7672 18:02:49.093490 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7673 18:02:49.096793 Total UI for P1: 0, mck2ui 16
7674 18:02:49.100553 best dqsien dly found for B0: ( 1, 9, 10)
7675 18:02:49.103988 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7676 18:02:49.107167 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7677 18:02:49.110343 Total UI for P1: 0, mck2ui 16
7678 18:02:49.113518 best dqsien dly found for B1: ( 1, 9, 20)
7679 18:02:49.116996 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7680 18:02:49.120309 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7681 18:02:49.124116
7682 18:02:49.127161 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7683 18:02:49.130359 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7684 18:02:49.133607 [Gating] SW calibration Done
7685 18:02:49.133694 ==
7686 18:02:49.136872 Dram Type= 6, Freq= 0, CH_0, rank 0
7687 18:02:49.140220 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7688 18:02:49.140308 ==
7689 18:02:49.140395 RX Vref Scan: 0
7690 18:02:49.143621
7691 18:02:49.143707 RX Vref 0 -> 0, step: 1
7692 18:02:49.143795
7693 18:02:49.146741 RX Delay 0 -> 252, step: 8
7694 18:02:49.150043 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
7695 18:02:49.153172 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7696 18:02:49.160108 iDelay=200, Bit 2, Center 135 (88 ~ 183) 96
7697 18:02:49.163330 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7698 18:02:49.166485 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7699 18:02:49.170320 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
7700 18:02:49.173121 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7701 18:02:49.180074 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7702 18:02:49.183354 iDelay=200, Bit 8, Center 123 (72 ~ 175) 104
7703 18:02:49.186653 iDelay=200, Bit 9, Center 119 (72 ~ 167) 96
7704 18:02:49.189899 iDelay=200, Bit 10, Center 127 (80 ~ 175) 96
7705 18:02:49.193149 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
7706 18:02:49.199532 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7707 18:02:49.203388 iDelay=200, Bit 13, Center 131 (88 ~ 175) 88
7708 18:02:49.206662 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7709 18:02:49.209832 iDelay=200, Bit 15, Center 135 (88 ~ 183) 96
7710 18:02:49.209917 ==
7711 18:02:49.212866 Dram Type= 6, Freq= 0, CH_0, rank 0
7712 18:02:49.219677 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7713 18:02:49.219755 ==
7714 18:02:49.219822 DQS Delay:
7715 18:02:49.219883 DQS0 = 0, DQS1 = 0
7716 18:02:49.222777 DQM Delay:
7717 18:02:49.222853 DQM0 = 138, DQM1 = 129
7718 18:02:49.226314 DQ Delay:
7719 18:02:49.229503 DQ0 =139, DQ1 =139, DQ2 =135, DQ3 =131
7720 18:02:49.232745 DQ4 =139, DQ5 =127, DQ6 =147, DQ7 =147
7721 18:02:49.236137 DQ8 =123, DQ9 =119, DQ10 =127, DQ11 =127
7722 18:02:49.239518 DQ12 =131, DQ13 =131, DQ14 =139, DQ15 =135
7723 18:02:49.239593
7724 18:02:49.239683
7725 18:02:49.239779 ==
7726 18:02:49.243227 Dram Type= 6, Freq= 0, CH_0, rank 0
7727 18:02:49.246477 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7728 18:02:49.249743 ==
7729 18:02:49.249842
7730 18:02:49.249942
7731 18:02:49.250032 TX Vref Scan disable
7732 18:02:49.253121 == TX Byte 0 ==
7733 18:02:49.256293 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7734 18:02:49.259678 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7735 18:02:49.262821 == TX Byte 1 ==
7736 18:02:49.265932 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7737 18:02:49.269425 Update DQM dly =988 (3 ,6, 28) DQM OEN =(3 ,3)
7738 18:02:49.269497 ==
7739 18:02:49.272657 Dram Type= 6, Freq= 0, CH_0, rank 0
7740 18:02:49.279142 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7741 18:02:49.279220 ==
7742 18:02:49.291743
7743 18:02:49.294872 TX Vref early break, caculate TX vref
7744 18:02:49.298182 TX Vref=16, minBit 8, minWin=22, winSum=377
7745 18:02:49.301226 TX Vref=18, minBit 6, minWin=23, winSum=385
7746 18:02:49.304433 TX Vref=20, minBit 0, minWin=24, winSum=392
7747 18:02:49.307779 TX Vref=22, minBit 0, minWin=25, winSum=405
7748 18:02:49.311213 TX Vref=24, minBit 0, minWin=25, winSum=413
7749 18:02:49.317945 TX Vref=26, minBit 2, minWin=25, winSum=424
7750 18:02:49.321570 TX Vref=28, minBit 1, minWin=26, winSum=429
7751 18:02:49.324617 TX Vref=30, minBit 0, minWin=25, winSum=420
7752 18:02:49.327789 TX Vref=32, minBit 0, minWin=25, winSum=414
7753 18:02:49.331068 TX Vref=34, minBit 2, minWin=24, winSum=405
7754 18:02:49.337906 [TxChooseVref] Worse bit 1, Min win 26, Win sum 429, Final Vref 28
7755 18:02:49.337981
7756 18:02:49.341063 Final TX Range 0 Vref 28
7757 18:02:49.341172
7758 18:02:49.341289 ==
7759 18:02:49.344284 Dram Type= 6, Freq= 0, CH_0, rank 0
7760 18:02:49.347849 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7761 18:02:49.347965 ==
7762 18:02:49.348073
7763 18:02:49.348158
7764 18:02:49.351083 TX Vref Scan disable
7765 18:02:49.357519 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7766 18:02:49.357589 == TX Byte 0 ==
7767 18:02:49.361251 u2DelayCellOfst[0]=10 cells (3 PI)
7768 18:02:49.364590 u2DelayCellOfst[1]=16 cells (5 PI)
7769 18:02:49.367848 u2DelayCellOfst[2]=10 cells (3 PI)
7770 18:02:49.371004 u2DelayCellOfst[3]=10 cells (3 PI)
7771 18:02:49.374104 u2DelayCellOfst[4]=6 cells (2 PI)
7772 18:02:49.377374 u2DelayCellOfst[5]=0 cells (0 PI)
7773 18:02:49.380752 u2DelayCellOfst[6]=16 cells (5 PI)
7774 18:02:49.383956 u2DelayCellOfst[7]=13 cells (4 PI)
7775 18:02:49.387782 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7776 18:02:49.391117 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7777 18:02:49.394416 == TX Byte 1 ==
7778 18:02:49.394517 u2DelayCellOfst[8]=0 cells (0 PI)
7779 18:02:49.397269 u2DelayCellOfst[9]=0 cells (0 PI)
7780 18:02:49.401159 u2DelayCellOfst[10]=6 cells (2 PI)
7781 18:02:49.404296 u2DelayCellOfst[11]=3 cells (1 PI)
7782 18:02:49.407477 u2DelayCellOfst[12]=13 cells (4 PI)
7783 18:02:49.410841 u2DelayCellOfst[13]=10 cells (3 PI)
7784 18:02:49.414122 u2DelayCellOfst[14]=13 cells (4 PI)
7785 18:02:49.417521 u2DelayCellOfst[15]=13 cells (4 PI)
7786 18:02:49.420697 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7787 18:02:49.427529 Update DQM dly =987 (3 ,6, 27) DQM OEN =(3 ,3)
7788 18:02:49.427654 DramC Write-DBI on
7789 18:02:49.427759 ==
7790 18:02:49.430759 Dram Type= 6, Freq= 0, CH_0, rank 0
7791 18:02:49.433953 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7792 18:02:49.437087 ==
7793 18:02:49.437170
7794 18:02:49.437252
7795 18:02:49.437317 TX Vref Scan disable
7796 18:02:49.440763 == TX Byte 0 ==
7797 18:02:49.444040 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7798 18:02:49.447375 == TX Byte 1 ==
7799 18:02:49.450538 Update DQM dly =728 (2 ,6, 24) DQM OEN =(3 ,3)
7800 18:02:49.453956 DramC Write-DBI off
7801 18:02:49.454066
7802 18:02:49.454169 [DATLAT]
7803 18:02:49.454261 Freq=1600, CH0 RK0
7804 18:02:49.454361
7805 18:02:49.457793 DATLAT Default: 0xf
7806 18:02:49.457902 0, 0xFFFF, sum = 0
7807 18:02:49.460936 1, 0xFFFF, sum = 0
7808 18:02:49.461026 2, 0xFFFF, sum = 0
7809 18:02:49.464272 3, 0xFFFF, sum = 0
7810 18:02:49.467437 4, 0xFFFF, sum = 0
7811 18:02:49.467546 5, 0xFFFF, sum = 0
7812 18:02:49.470648 6, 0xFFFF, sum = 0
7813 18:02:49.470751 7, 0xFFFF, sum = 0
7814 18:02:49.473982 8, 0xFFFF, sum = 0
7815 18:02:49.474092 9, 0xFFFF, sum = 0
7816 18:02:49.477212 10, 0xFFFF, sum = 0
7817 18:02:49.477292 11, 0xFFFF, sum = 0
7818 18:02:49.480960 12, 0xFFFF, sum = 0
7819 18:02:49.481046 13, 0xFFFF, sum = 0
7820 18:02:49.483622 14, 0x0, sum = 1
7821 18:02:49.483736 15, 0x0, sum = 2
7822 18:02:49.487010 16, 0x0, sum = 3
7823 18:02:49.487095 17, 0x0, sum = 4
7824 18:02:49.490752 best_step = 15
7825 18:02:49.490837
7826 18:02:49.490904 ==
7827 18:02:49.494234 Dram Type= 6, Freq= 0, CH_0, rank 0
7828 18:02:49.497426 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7829 18:02:49.497529 ==
7830 18:02:49.497626 RX Vref Scan: 1
7831 18:02:49.500509
7832 18:02:49.500617 Set Vref Range= 24 -> 127
7833 18:02:49.500686
7834 18:02:49.503949 RX Vref 24 -> 127, step: 1
7835 18:02:49.504034
7836 18:02:49.507186 RX Delay 27 -> 252, step: 4
7837 18:02:49.507271
7838 18:02:49.510475 Set Vref, RX VrefLevel [Byte0]: 24
7839 18:02:49.513742 [Byte1]: 24
7840 18:02:49.513835
7841 18:02:49.517163 Set Vref, RX VrefLevel [Byte0]: 25
7842 18:02:49.520480 [Byte1]: 25
7843 18:02:49.520573
7844 18:02:49.523570 Set Vref, RX VrefLevel [Byte0]: 26
7845 18:02:49.527345 [Byte1]: 26
7846 18:02:49.531208
7847 18:02:49.531292 Set Vref, RX VrefLevel [Byte0]: 27
7848 18:02:49.534177 [Byte1]: 27
7849 18:02:49.538357
7850 18:02:49.538441 Set Vref, RX VrefLevel [Byte0]: 28
7851 18:02:49.541905 [Byte1]: 28
7852 18:02:49.545816
7853 18:02:49.545900 Set Vref, RX VrefLevel [Byte0]: 29
7854 18:02:49.549564 [Byte1]: 29
7855 18:02:49.553231
7856 18:02:49.553316 Set Vref, RX VrefLevel [Byte0]: 30
7857 18:02:49.556834 [Byte1]: 30
7858 18:02:49.561026
7859 18:02:49.561105 Set Vref, RX VrefLevel [Byte0]: 31
7860 18:02:49.564153 [Byte1]: 31
7861 18:02:49.568517
7862 18:02:49.568634 Set Vref, RX VrefLevel [Byte0]: 32
7863 18:02:49.571746 [Byte1]: 32
7864 18:02:49.575977
7865 18:02:49.576088 Set Vref, RX VrefLevel [Byte0]: 33
7866 18:02:49.579380 [Byte1]: 33
7867 18:02:49.583596
7868 18:02:49.583679 Set Vref, RX VrefLevel [Byte0]: 34
7869 18:02:49.586824 [Byte1]: 34
7870 18:02:49.591151
7871 18:02:49.591257 Set Vref, RX VrefLevel [Byte0]: 35
7872 18:02:49.594413 [Byte1]: 35
7873 18:02:49.598811
7874 18:02:49.598931 Set Vref, RX VrefLevel [Byte0]: 36
7875 18:02:49.602110 [Byte1]: 36
7876 18:02:49.606100
7877 18:02:49.606209 Set Vref, RX VrefLevel [Byte0]: 37
7878 18:02:49.609717 [Byte1]: 37
7879 18:02:49.613643
7880 18:02:49.613753 Set Vref, RX VrefLevel [Byte0]: 38
7881 18:02:49.616793 [Byte1]: 38
7882 18:02:49.621335
7883 18:02:49.621446 Set Vref, RX VrefLevel [Byte0]: 39
7884 18:02:49.624633 [Byte1]: 39
7885 18:02:49.628932
7886 18:02:49.629015 Set Vref, RX VrefLevel [Byte0]: 40
7887 18:02:49.631971 [Byte1]: 40
7888 18:02:49.636424
7889 18:02:49.636533 Set Vref, RX VrefLevel [Byte0]: 41
7890 18:02:49.639545 [Byte1]: 41
7891 18:02:49.643987
7892 18:02:49.644062 Set Vref, RX VrefLevel [Byte0]: 42
7893 18:02:49.647162 [Byte1]: 42
7894 18:02:49.651483
7895 18:02:49.651559 Set Vref, RX VrefLevel [Byte0]: 43
7896 18:02:49.654796 [Byte1]: 43
7897 18:02:49.659037
7898 18:02:49.659112 Set Vref, RX VrefLevel [Byte0]: 44
7899 18:02:49.662267 [Byte1]: 44
7900 18:02:49.666441
7901 18:02:49.666519 Set Vref, RX VrefLevel [Byte0]: 45
7902 18:02:49.669739 [Byte1]: 45
7903 18:02:49.674085
7904 18:02:49.674160 Set Vref, RX VrefLevel [Byte0]: 46
7905 18:02:49.677320 [Byte1]: 46
7906 18:02:49.681653
7907 18:02:49.681739 Set Vref, RX VrefLevel [Byte0]: 47
7908 18:02:49.684907 [Byte1]: 47
7909 18:02:49.689124
7910 18:02:49.689234 Set Vref, RX VrefLevel [Byte0]: 48
7911 18:02:49.692259 [Byte1]: 48
7912 18:02:49.696498
7913 18:02:49.696617 Set Vref, RX VrefLevel [Byte0]: 49
7914 18:02:49.699883 [Byte1]: 49
7915 18:02:49.704317
7916 18:02:49.704401 Set Vref, RX VrefLevel [Byte0]: 50
7917 18:02:49.707566 [Byte1]: 50
7918 18:02:49.711794
7919 18:02:49.711884 Set Vref, RX VrefLevel [Byte0]: 51
7920 18:02:49.715008 [Byte1]: 51
7921 18:02:49.719427
7922 18:02:49.719512 Set Vref, RX VrefLevel [Byte0]: 52
7923 18:02:49.722715 [Byte1]: 52
7924 18:02:49.727133
7925 18:02:49.727217 Set Vref, RX VrefLevel [Byte0]: 53
7926 18:02:49.729949 [Byte1]: 53
7927 18:02:49.734310
7928 18:02:49.734420 Set Vref, RX VrefLevel [Byte0]: 54
7929 18:02:49.737456 [Byte1]: 54
7930 18:02:49.741640
7931 18:02:49.741746 Set Vref, RX VrefLevel [Byte0]: 55
7932 18:02:49.745165 [Byte1]: 55
7933 18:02:49.749380
7934 18:02:49.749485 Set Vref, RX VrefLevel [Byte0]: 56
7935 18:02:49.752476 [Byte1]: 56
7936 18:02:49.756800
7937 18:02:49.756899 Set Vref, RX VrefLevel [Byte0]: 57
7938 18:02:49.760109 [Byte1]: 57
7939 18:02:49.764512
7940 18:02:49.764630 Set Vref, RX VrefLevel [Byte0]: 58
7941 18:02:49.767528 [Byte1]: 58
7942 18:02:49.771834
7943 18:02:49.771937 Set Vref, RX VrefLevel [Byte0]: 59
7944 18:02:49.775094 [Byte1]: 59
7945 18:02:49.779339
7946 18:02:49.779447 Set Vref, RX VrefLevel [Byte0]: 60
7947 18:02:49.782590 [Byte1]: 60
7948 18:02:49.787085
7949 18:02:49.787168 Set Vref, RX VrefLevel [Byte0]: 61
7950 18:02:49.790242 [Byte1]: 61
7951 18:02:49.794493
7952 18:02:49.794576 Set Vref, RX VrefLevel [Byte0]: 62
7953 18:02:49.798212 [Byte1]: 62
7954 18:02:49.802157
7955 18:02:49.802240 Set Vref, RX VrefLevel [Byte0]: 63
7956 18:02:49.805376 [Byte1]: 63
7957 18:02:49.809843
7958 18:02:49.809926 Set Vref, RX VrefLevel [Byte0]: 64
7959 18:02:49.812990 [Byte1]: 64
7960 18:02:49.816978
7961 18:02:49.817109 Set Vref, RX VrefLevel [Byte0]: 65
7962 18:02:49.820243 [Byte1]: 65
7963 18:02:49.824651
7964 18:02:49.824764 Set Vref, RX VrefLevel [Byte0]: 66
7965 18:02:49.827839 [Byte1]: 66
7966 18:02:49.832161
7967 18:02:49.832282 Set Vref, RX VrefLevel [Byte0]: 67
7968 18:02:49.835450 [Byte1]: 67
7969 18:02:49.839586
7970 18:02:49.839668 Set Vref, RX VrefLevel [Byte0]: 68
7971 18:02:49.843231 [Byte1]: 68
7972 18:02:49.847142
7973 18:02:49.847224 Set Vref, RX VrefLevel [Byte0]: 69
7974 18:02:49.850657 [Byte1]: 69
7975 18:02:49.854831
7976 18:02:49.854961 Set Vref, RX VrefLevel [Byte0]: 70
7977 18:02:49.857867 [Byte1]: 70
7978 18:02:49.862173
7979 18:02:49.862272 Set Vref, RX VrefLevel [Byte0]: 71
7980 18:02:49.865411 [Byte1]: 71
7981 18:02:49.869661
7982 18:02:49.869744 Set Vref, RX VrefLevel [Byte0]: 72
7983 18:02:49.872961 [Byte1]: 72
7984 18:02:49.877289
7985 18:02:49.877399 Set Vref, RX VrefLevel [Byte0]: 73
7986 18:02:49.880498 [Byte1]: 73
7987 18:02:49.884909
7988 18:02:49.884988 Set Vref, RX VrefLevel [Byte0]: 74
7989 18:02:49.888300 [Byte1]: 74
7990 18:02:49.892676
7991 18:02:49.892752 Set Vref, RX VrefLevel [Byte0]: 75
7992 18:02:49.895988 [Byte1]: 75
7993 18:02:49.900269
7994 18:02:49.900372 Set Vref, RX VrefLevel [Byte0]: 76
7995 18:02:49.903389 [Byte1]: 76
7996 18:02:49.907326
7997 18:02:49.907398 Set Vref, RX VrefLevel [Byte0]: 77
7998 18:02:49.911145 [Byte1]: 77
7999 18:02:49.914925
8000 18:02:49.914997 Set Vref, RX VrefLevel [Byte0]: 78
8001 18:02:49.918259 [Byte1]: 78
8002 18:02:49.922348
8003 18:02:49.922430 Final RX Vref Byte 0 = 61 to rank0
8004 18:02:49.925667 Final RX Vref Byte 1 = 62 to rank0
8005 18:02:49.929015 Final RX Vref Byte 0 = 61 to rank1
8006 18:02:49.932584 Final RX Vref Byte 1 = 62 to rank1==
8007 18:02:49.935932 Dram Type= 6, Freq= 0, CH_0, rank 0
8008 18:02:49.942324 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8009 18:02:49.942403 ==
8010 18:02:49.942468 DQS Delay:
8011 18:02:49.942531 DQS0 = 0, DQS1 = 0
8012 18:02:49.945944 DQM Delay:
8013 18:02:49.946045 DQM0 = 134, DQM1 = 127
8014 18:02:49.949171 DQ Delay:
8015 18:02:49.952467 DQ0 =134, DQ1 =134, DQ2 =130, DQ3 =132
8016 18:02:49.955619 DQ4 =136, DQ5 =124, DQ6 =144, DQ7 =140
8017 18:02:49.958858 DQ8 =118, DQ9 =114, DQ10 =130, DQ11 =122
8018 18:02:49.962588 DQ12 =130, DQ13 =130, DQ14 =138, DQ15 =136
8019 18:02:49.962662
8020 18:02:49.962724
8021 18:02:49.962782
8022 18:02:49.965772 [DramC_TX_OE_Calibration] TA2
8023 18:02:49.968796 Original DQ_B0 (3 6) =30, OEN = 27
8024 18:02:49.972086 Original DQ_B1 (3 6) =30, OEN = 27
8025 18:02:49.975805 24, 0x0, End_B0=24 End_B1=24
8026 18:02:49.975906 25, 0x0, End_B0=25 End_B1=25
8027 18:02:49.979198 26, 0x0, End_B0=26 End_B1=26
8028 18:02:49.982384 27, 0x0, End_B0=27 End_B1=27
8029 18:02:49.985469 28, 0x0, End_B0=28 End_B1=28
8030 18:02:49.988795 29, 0x0, End_B0=29 End_B1=29
8031 18:02:49.988904 30, 0x0, End_B0=30 End_B1=30
8032 18:02:49.992052 31, 0x4545, End_B0=30 End_B1=30
8033 18:02:49.995324 Byte0 end_step=30 best_step=27
8034 18:02:49.998723 Byte1 end_step=30 best_step=27
8035 18:02:50.002433 Byte0 TX OE(2T, 0.5T) = (3, 3)
8036 18:02:50.005586 Byte1 TX OE(2T, 0.5T) = (3, 3)
8037 18:02:50.005661
8038 18:02:50.005724
8039 18:02:50.012288 [DQSOSCAuto] RK0, (LSB)MR18= 0x1e1d, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 394 ps
8040 18:02:50.015541 CH0 RK0: MR19=303, MR18=1E1D
8041 18:02:50.022079 CH0_RK0: MR19=0x303, MR18=0x1E1D, DQSOSC=394, MR23=63, INC=23, DEC=15
8042 18:02:50.022160
8043 18:02:50.025334 ----->DramcWriteLeveling(PI) begin...
8044 18:02:50.025411 ==
8045 18:02:50.028570 Dram Type= 6, Freq= 0, CH_0, rank 1
8046 18:02:50.032100 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8047 18:02:50.032200 ==
8048 18:02:50.035551 Write leveling (Byte 0): 38 => 38
8049 18:02:50.038781 Write leveling (Byte 1): 29 => 29
8050 18:02:50.042025 DramcWriteLeveling(PI) end<-----
8051 18:02:50.042126
8052 18:02:50.042223 ==
8053 18:02:50.045288 Dram Type= 6, Freq= 0, CH_0, rank 1
8054 18:02:50.048490 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8055 18:02:50.048597 ==
8056 18:02:50.052102 [Gating] SW mode calibration
8057 18:02:50.058445 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8058 18:02:50.065118 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8059 18:02:50.068243 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8060 18:02:50.075108 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8061 18:02:50.078401 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8062 18:02:50.081616 1 4 12 | B1->B0 | 2424 3131 | 0 1 | (0 0) (1 1)
8063 18:02:50.085307 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8064 18:02:50.091858 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8065 18:02:50.095234 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8066 18:02:50.098502 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8067 18:02:50.104966 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8068 18:02:50.108304 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8069 18:02:50.111541 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8070 18:02:50.118510 1 5 12 | B1->B0 | 3434 2c2c | 1 0 | (1 1) (0 1)
8071 18:02:50.121716 1 5 16 | B1->B0 | 2c2c 2323 | 0 0 | (1 0) (0 0)
8072 18:02:50.124941 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8073 18:02:50.131611 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8074 18:02:50.134780 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8075 18:02:50.138016 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8076 18:02:50.144691 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8077 18:02:50.148088 1 6 8 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
8078 18:02:50.151404 1 6 12 | B1->B0 | 2e2e 4242 | 1 1 | (0 0) (0 0)
8079 18:02:50.158098 1 6 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8080 18:02:50.161243 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8081 18:02:50.164761 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8082 18:02:50.171147 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8083 18:02:50.174498 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8084 18:02:50.177934 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8085 18:02:50.184640 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8086 18:02:50.187545 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8087 18:02:50.190900 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8088 18:02:50.197944 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8089 18:02:50.201232 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8090 18:02:50.204468 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8091 18:02:50.210958 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8092 18:02:50.214148 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8093 18:02:50.217452 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8094 18:02:50.224172 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8095 18:02:50.227479 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8096 18:02:50.230798 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8097 18:02:50.237339 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8098 18:02:50.240629 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8099 18:02:50.243956 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8100 18:02:50.250566 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8101 18:02:50.253842 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8102 18:02:50.257086 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8103 18:02:50.260774 Total UI for P1: 0, mck2ui 16
8104 18:02:50.263997 best dqsien dly found for B0: ( 1, 9, 8)
8105 18:02:50.270708 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8106 18:02:50.274217 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8107 18:02:50.277488 Total UI for P1: 0, mck2ui 16
8108 18:02:50.280521 best dqsien dly found for B1: ( 1, 9, 14)
8109 18:02:50.284174 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8110 18:02:50.287453 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8111 18:02:50.287527
8112 18:02:50.290524 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8113 18:02:50.294246 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8114 18:02:50.297494 [Gating] SW calibration Done
8115 18:02:50.297567 ==
8116 18:02:50.300381 Dram Type= 6, Freq= 0, CH_0, rank 1
8117 18:02:50.304092 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8118 18:02:50.304167 ==
8119 18:02:50.307212 RX Vref Scan: 0
8120 18:02:50.307294
8121 18:02:50.310491 RX Vref 0 -> 0, step: 1
8122 18:02:50.310574
8123 18:02:50.310638 RX Delay 0 -> 252, step: 8
8124 18:02:50.317131 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8125 18:02:50.320452 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8126 18:02:50.323645 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8127 18:02:50.326933 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
8128 18:02:50.330206 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8129 18:02:50.336863 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8130 18:02:50.340690 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8131 18:02:50.343825 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8132 18:02:50.347160 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
8133 18:02:50.350407 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
8134 18:02:50.353718 iDelay=200, Bit 10, Center 127 (80 ~ 175) 96
8135 18:02:50.360216 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8136 18:02:50.363352 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
8137 18:02:50.366984 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
8138 18:02:50.370051 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8139 18:02:50.376732 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8140 18:02:50.376818 ==
8141 18:02:50.380418 Dram Type= 6, Freq= 0, CH_0, rank 1
8142 18:02:50.383626 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8143 18:02:50.383708 ==
8144 18:02:50.383778 DQS Delay:
8145 18:02:50.386840 DQS0 = 0, DQS1 = 0
8146 18:02:50.386924 DQM Delay:
8147 18:02:50.390077 DQM0 = 135, DQM1 = 127
8148 18:02:50.390155 DQ Delay:
8149 18:02:50.393294 DQ0 =135, DQ1 =135, DQ2 =135, DQ3 =131
8150 18:02:50.397045 DQ4 =135, DQ5 =127, DQ6 =143, DQ7 =143
8151 18:02:50.400289 DQ8 =119, DQ9 =115, DQ10 =127, DQ11 =123
8152 18:02:50.403407 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
8153 18:02:50.403489
8154 18:02:50.403555
8155 18:02:50.406682 ==
8156 18:02:50.406755 Dram Type= 6, Freq= 0, CH_0, rank 1
8157 18:02:50.413878 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8158 18:02:50.413959 ==
8159 18:02:50.414031
8160 18:02:50.414096
8161 18:02:50.414156 TX Vref Scan disable
8162 18:02:50.417185 == TX Byte 0 ==
8163 18:02:50.420890 Update DQ dly =994 (3 ,6, 34) DQ OEN =(3 ,3)
8164 18:02:50.427449 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
8165 18:02:50.427531 == TX Byte 1 ==
8166 18:02:50.430708 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8167 18:02:50.437201 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8168 18:02:50.437314 ==
8169 18:02:50.440454 Dram Type= 6, Freq= 0, CH_0, rank 1
8170 18:02:50.443721 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8171 18:02:50.443804 ==
8172 18:02:50.458738
8173 18:02:50.462005 TX Vref early break, caculate TX vref
8174 18:02:50.465357 TX Vref=16, minBit 2, minWin=23, winSum=389
8175 18:02:50.468456 TX Vref=18, minBit 8, minWin=23, winSum=399
8176 18:02:50.471647 TX Vref=20, minBit 0, minWin=24, winSum=403
8177 18:02:50.474916 TX Vref=22, minBit 0, minWin=25, winSum=412
8178 18:02:50.478574 TX Vref=24, minBit 0, minWin=25, winSum=426
8179 18:02:50.485383 TX Vref=26, minBit 0, minWin=26, winSum=428
8180 18:02:50.488112 TX Vref=28, minBit 0, minWin=26, winSum=431
8181 18:02:50.491540 TX Vref=30, minBit 0, minWin=26, winSum=427
8182 18:02:50.494827 TX Vref=32, minBit 8, minWin=25, winSum=420
8183 18:02:50.498081 TX Vref=34, minBit 0, minWin=25, winSum=409
8184 18:02:50.501673 TX Vref=36, minBit 2, minWin=24, winSum=399
8185 18:02:50.508514 [TxChooseVref] Worse bit 0, Min win 26, Win sum 431, Final Vref 28
8186 18:02:50.508611
8187 18:02:50.511416 Final TX Range 0 Vref 28
8188 18:02:50.511516
8189 18:02:50.511602 ==
8190 18:02:50.514651 Dram Type= 6, Freq= 0, CH_0, rank 1
8191 18:02:50.518104 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8192 18:02:50.518189 ==
8193 18:02:50.518255
8194 18:02:50.518325
8195 18:02:50.521431 TX Vref Scan disable
8196 18:02:50.528466 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8197 18:02:50.528541 == TX Byte 0 ==
8198 18:02:50.531350 u2DelayCellOfst[0]=13 cells (4 PI)
8199 18:02:50.535116 u2DelayCellOfst[1]=20 cells (6 PI)
8200 18:02:50.538427 u2DelayCellOfst[2]=13 cells (4 PI)
8201 18:02:50.541625 u2DelayCellOfst[3]=13 cells (4 PI)
8202 18:02:50.544831 u2DelayCellOfst[4]=10 cells (3 PI)
8203 18:02:50.548158 u2DelayCellOfst[5]=0 cells (0 PI)
8204 18:02:50.551373 u2DelayCellOfst[6]=20 cells (6 PI)
8205 18:02:50.554565 u2DelayCellOfst[7]=16 cells (5 PI)
8206 18:02:50.558363 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8207 18:02:50.561168 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
8208 18:02:50.564935 == TX Byte 1 ==
8209 18:02:50.568270 u2DelayCellOfst[8]=0 cells (0 PI)
8210 18:02:50.571550 u2DelayCellOfst[9]=0 cells (0 PI)
8211 18:02:50.571635 u2DelayCellOfst[10]=6 cells (2 PI)
8212 18:02:50.574657 u2DelayCellOfst[11]=0 cells (0 PI)
8213 18:02:50.578203 u2DelayCellOfst[12]=10 cells (3 PI)
8214 18:02:50.581336 u2DelayCellOfst[13]=10 cells (3 PI)
8215 18:02:50.584444 u2DelayCellOfst[14]=13 cells (4 PI)
8216 18:02:50.588126 u2DelayCellOfst[15]=6 cells (2 PI)
8217 18:02:50.594338 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8218 18:02:50.597951 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8219 18:02:50.598055 DramC Write-DBI on
8220 18:02:50.598155 ==
8221 18:02:50.601267 Dram Type= 6, Freq= 0, CH_0, rank 1
8222 18:02:50.608176 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8223 18:02:50.608280 ==
8224 18:02:50.608379
8225 18:02:50.608470
8226 18:02:50.608561 TX Vref Scan disable
8227 18:02:50.611942 == TX Byte 0 ==
8228 18:02:50.615296 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
8229 18:02:50.618383 == TX Byte 1 ==
8230 18:02:50.621750 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8231 18:02:50.625084 DramC Write-DBI off
8232 18:02:50.625156
8233 18:02:50.625232 [DATLAT]
8234 18:02:50.625297 Freq=1600, CH0 RK1
8235 18:02:50.625355
8236 18:02:50.628806 DATLAT Default: 0xf
8237 18:02:50.628878 0, 0xFFFF, sum = 0
8238 18:02:50.631746 1, 0xFFFF, sum = 0
8239 18:02:50.635166 2, 0xFFFF, sum = 0
8240 18:02:50.635252 3, 0xFFFF, sum = 0
8241 18:02:50.638546 4, 0xFFFF, sum = 0
8242 18:02:50.638620 5, 0xFFFF, sum = 0
8243 18:02:50.641731 6, 0xFFFF, sum = 0
8244 18:02:50.641823 7, 0xFFFF, sum = 0
8245 18:02:50.644959 8, 0xFFFF, sum = 0
8246 18:02:50.645066 9, 0xFFFF, sum = 0
8247 18:02:50.648710 10, 0xFFFF, sum = 0
8248 18:02:50.648788 11, 0xFFFF, sum = 0
8249 18:02:50.651935 12, 0xFFFF, sum = 0
8250 18:02:50.652012 13, 0xFFFF, sum = 0
8251 18:02:50.655346 14, 0x0, sum = 1
8252 18:02:50.655451 15, 0x0, sum = 2
8253 18:02:50.658595 16, 0x0, sum = 3
8254 18:02:50.658705 17, 0x0, sum = 4
8255 18:02:50.661820 best_step = 15
8256 18:02:50.661898
8257 18:02:50.661975 ==
8258 18:02:50.665122 Dram Type= 6, Freq= 0, CH_0, rank 1
8259 18:02:50.668312 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8260 18:02:50.668410 ==
8261 18:02:50.671633 RX Vref Scan: 0
8262 18:02:50.671706
8263 18:02:50.671765 RX Vref 0 -> 0, step: 1
8264 18:02:50.671824
8265 18:02:50.674922 RX Delay 19 -> 252, step: 4
8266 18:02:50.678139 iDelay=191, Bit 0, Center 130 (79 ~ 182) 104
8267 18:02:50.684902 iDelay=191, Bit 1, Center 134 (83 ~ 186) 104
8268 18:02:50.688025 iDelay=191, Bit 2, Center 128 (79 ~ 178) 100
8269 18:02:50.691749 iDelay=191, Bit 3, Center 130 (83 ~ 178) 96
8270 18:02:50.694637 iDelay=191, Bit 4, Center 132 (83 ~ 182) 100
8271 18:02:50.698277 iDelay=191, Bit 5, Center 124 (75 ~ 174) 100
8272 18:02:50.704538 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8273 18:02:50.707859 iDelay=191, Bit 7, Center 138 (87 ~ 190) 104
8274 18:02:50.711496 iDelay=191, Bit 8, Center 116 (71 ~ 162) 92
8275 18:02:50.714677 iDelay=191, Bit 9, Center 114 (67 ~ 162) 96
8276 18:02:50.717991 iDelay=191, Bit 10, Center 126 (83 ~ 170) 88
8277 18:02:50.724531 iDelay=191, Bit 11, Center 120 (75 ~ 166) 92
8278 18:02:50.727712 iDelay=191, Bit 12, Center 128 (79 ~ 178) 100
8279 18:02:50.731057 iDelay=191, Bit 13, Center 130 (83 ~ 178) 96
8280 18:02:50.734740 iDelay=191, Bit 14, Center 134 (83 ~ 186) 104
8281 18:02:50.737923 iDelay=191, Bit 15, Center 132 (83 ~ 182) 100
8282 18:02:50.741333 ==
8283 18:02:50.741419 Dram Type= 6, Freq= 0, CH_0, rank 1
8284 18:02:50.747801 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8285 18:02:50.747888 ==
8286 18:02:50.747973 DQS Delay:
8287 18:02:50.750955 DQS0 = 0, DQS1 = 0
8288 18:02:50.751050 DQM Delay:
8289 18:02:50.754251 DQM0 = 132, DQM1 = 125
8290 18:02:50.754335 DQ Delay:
8291 18:02:50.757540 DQ0 =130, DQ1 =134, DQ2 =128, DQ3 =130
8292 18:02:50.761449 DQ4 =132, DQ5 =124, DQ6 =140, DQ7 =138
8293 18:02:50.764470 DQ8 =116, DQ9 =114, DQ10 =126, DQ11 =120
8294 18:02:50.767767 DQ12 =128, DQ13 =130, DQ14 =134, DQ15 =132
8295 18:02:50.767852
8296 18:02:50.767917
8297 18:02:50.767978
8298 18:02:50.770998 [DramC_TX_OE_Calibration] TA2
8299 18:02:50.774479 Original DQ_B0 (3 6) =30, OEN = 27
8300 18:02:50.777631 Original DQ_B1 (3 6) =30, OEN = 27
8301 18:02:50.780889 24, 0x0, End_B0=24 End_B1=24
8302 18:02:50.784080 25, 0x0, End_B0=25 End_B1=25
8303 18:02:50.784153 26, 0x0, End_B0=26 End_B1=26
8304 18:02:50.787727 27, 0x0, End_B0=27 End_B1=27
8305 18:02:50.791109 28, 0x0, End_B0=28 End_B1=28
8306 18:02:50.794268 29, 0x0, End_B0=29 End_B1=29
8307 18:02:50.794340 30, 0x0, End_B0=30 End_B1=30
8308 18:02:50.797428 31, 0x4141, End_B0=30 End_B1=30
8309 18:02:50.800923 Byte0 end_step=30 best_step=27
8310 18:02:50.804194 Byte1 end_step=30 best_step=27
8311 18:02:50.807786 Byte0 TX OE(2T, 0.5T) = (3, 3)
8312 18:02:50.811049 Byte1 TX OE(2T, 0.5T) = (3, 3)
8313 18:02:50.811135
8314 18:02:50.811201
8315 18:02:50.817245 [DQSOSCAuto] RK1, (LSB)MR18= 0x1f0c, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 394 ps
8316 18:02:50.820982 CH0 RK1: MR19=303, MR18=1F0C
8317 18:02:50.827372 CH0_RK1: MR19=0x303, MR18=0x1F0C, DQSOSC=394, MR23=63, INC=23, DEC=15
8318 18:02:50.830670 [RxdqsGatingPostProcess] freq 1600
8319 18:02:50.834374 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8320 18:02:50.837603 best DQS0 dly(2T, 0.5T) = (1, 1)
8321 18:02:50.840862 best DQS1 dly(2T, 0.5T) = (1, 1)
8322 18:02:50.844144 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8323 18:02:50.847419 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8324 18:02:50.850648 best DQS0 dly(2T, 0.5T) = (1, 1)
8325 18:02:50.854330 best DQS1 dly(2T, 0.5T) = (1, 1)
8326 18:02:50.857623 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8327 18:02:50.860962 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8328 18:02:50.863894 Pre-setting of DQS Precalculation
8329 18:02:50.867467 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8330 18:02:50.867544 ==
8331 18:02:50.870670 Dram Type= 6, Freq= 0, CH_1, rank 0
8332 18:02:50.877208 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8333 18:02:50.877288 ==
8334 18:02:50.880972 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8335 18:02:50.886904 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8336 18:02:50.890547 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8337 18:02:50.896907 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8338 18:02:50.904775 [CA 0] Center 42 (12~72) winsize 61
8339 18:02:50.907941 [CA 1] Center 42 (12~72) winsize 61
8340 18:02:50.911501 [CA 2] Center 38 (9~68) winsize 60
8341 18:02:50.914659 [CA 3] Center 37 (8~67) winsize 60
8342 18:02:50.917995 [CA 4] Center 37 (8~67) winsize 60
8343 18:02:50.921090 [CA 5] Center 37 (7~67) winsize 61
8344 18:02:50.921192
8345 18:02:50.924636 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8346 18:02:50.924717
8347 18:02:50.927948 [CATrainingPosCal] consider 1 rank data
8348 18:02:50.931402 u2DelayCellTimex100 = 290/100 ps
8349 18:02:50.934722 CA0 delay=42 (12~72),Diff = 5 PI (16 cell)
8350 18:02:50.941182 CA1 delay=42 (12~72),Diff = 5 PI (16 cell)
8351 18:02:50.944384 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8352 18:02:50.947580 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8353 18:02:50.950919 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
8354 18:02:50.954553 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
8355 18:02:50.954652
8356 18:02:50.957886 CA PerBit enable=1, Macro0, CA PI delay=37
8357 18:02:50.957989
8358 18:02:50.961355 [CBTSetCACLKResult] CA Dly = 37
8359 18:02:50.964632 CS Dly: 9 (0~40)
8360 18:02:50.967875 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8361 18:02:50.971203 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8362 18:02:50.971275 ==
8363 18:02:50.974391 Dram Type= 6, Freq= 0, CH_1, rank 1
8364 18:02:50.977618 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8365 18:02:50.977689 ==
8366 18:02:50.984115 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8367 18:02:50.987293 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8368 18:02:50.994326 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8369 18:02:50.997694 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8370 18:02:51.007614 [CA 0] Center 42 (13~72) winsize 60
8371 18:02:51.010765 [CA 1] Center 42 (12~72) winsize 61
8372 18:02:51.014466 [CA 2] Center 38 (9~67) winsize 59
8373 18:02:51.017585 [CA 3] Center 37 (8~67) winsize 60
8374 18:02:51.020902 [CA 4] Center 38 (9~67) winsize 59
8375 18:02:51.024186 [CA 5] Center 37 (7~67) winsize 61
8376 18:02:51.024294
8377 18:02:51.027411 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8378 18:02:51.027510
8379 18:02:51.030553 [CATrainingPosCal] consider 2 rank data
8380 18:02:51.034076 u2DelayCellTimex100 = 290/100 ps
8381 18:02:51.037208 CA0 delay=42 (13~72),Diff = 5 PI (16 cell)
8382 18:02:51.043934 CA1 delay=42 (12~72),Diff = 5 PI (16 cell)
8383 18:02:51.047202 CA2 delay=38 (9~67),Diff = 1 PI (3 cell)
8384 18:02:51.050939 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8385 18:02:51.053727 CA4 delay=38 (9~67),Diff = 1 PI (3 cell)
8386 18:02:51.057047 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
8387 18:02:51.057153
8388 18:02:51.060452 CA PerBit enable=1, Macro0, CA PI delay=37
8389 18:02:51.060567
8390 18:02:51.063741 [CBTSetCACLKResult] CA Dly = 37
8391 18:02:51.067206 CS Dly: 10 (0~42)
8392 18:02:51.070422 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8393 18:02:51.073821 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8394 18:02:51.073905
8395 18:02:51.076977 ----->DramcWriteLeveling(PI) begin...
8396 18:02:51.077078 ==
8397 18:02:51.080284 Dram Type= 6, Freq= 0, CH_1, rank 0
8398 18:02:51.086853 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8399 18:02:51.086926 ==
8400 18:02:51.090148 Write leveling (Byte 0): 24 => 24
8401 18:02:51.090218 Write leveling (Byte 1): 28 => 28
8402 18:02:51.093487 DramcWriteLeveling(PI) end<-----
8403 18:02:51.093564
8404 18:02:51.097338 ==
8405 18:02:51.097445 Dram Type= 6, Freq= 0, CH_1, rank 0
8406 18:02:51.103529 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8407 18:02:51.103636 ==
8408 18:02:51.106834 [Gating] SW mode calibration
8409 18:02:51.113461 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8410 18:02:51.117327 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8411 18:02:51.123440 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8412 18:02:51.127217 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8413 18:02:51.130636 1 4 8 | B1->B0 | 2424 2c2c | 1 0 | (0 0) (0 0)
8414 18:02:51.136854 1 4 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8415 18:02:51.140086 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8416 18:02:51.143637 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8417 18:02:51.150159 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8418 18:02:51.153270 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8419 18:02:51.156454 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8420 18:02:51.163454 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8421 18:02:51.166691 1 5 8 | B1->B0 | 2d2d 2626 | 0 0 | (0 0) (1 0)
8422 18:02:51.170066 1 5 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8423 18:02:51.176562 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8424 18:02:51.179832 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8425 18:02:51.183043 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8426 18:02:51.190086 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8427 18:02:51.193808 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8428 18:02:51.196501 1 6 4 | B1->B0 | 2424 2626 | 0 0 | (0 0) (0 0)
8429 18:02:51.202932 1 6 8 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
8430 18:02:51.206411 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8431 18:02:51.209663 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8432 18:02:51.213328 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8433 18:02:51.219462 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8434 18:02:51.222659 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8435 18:02:51.226275 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8436 18:02:51.232651 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8437 18:02:51.235940 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8438 18:02:51.239538 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8439 18:02:51.246027 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8440 18:02:51.249439 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8441 18:02:51.252692 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8442 18:02:51.259552 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8443 18:02:51.262857 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8444 18:02:51.266117 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8445 18:02:51.272999 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8446 18:02:51.276130 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8447 18:02:51.279403 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8448 18:02:51.285998 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8449 18:02:51.289333 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8450 18:02:51.292564 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8451 18:02:51.299188 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8452 18:02:51.302781 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8453 18:02:51.306170 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8454 18:02:51.312406 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8455 18:02:51.312509 Total UI for P1: 0, mck2ui 16
8456 18:02:51.319101 best dqsien dly found for B0: ( 1, 9, 8)
8457 18:02:51.322271 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8458 18:02:51.325851 Total UI for P1: 0, mck2ui 16
8459 18:02:51.329097 best dqsien dly found for B1: ( 1, 9, 10)
8460 18:02:51.332185 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8461 18:02:51.335677 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8462 18:02:51.335780
8463 18:02:51.339408 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8464 18:02:51.342131 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8465 18:02:51.345744 [Gating] SW calibration Done
8466 18:02:51.345844 ==
8467 18:02:51.349119 Dram Type= 6, Freq= 0, CH_1, rank 0
8468 18:02:51.352446 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8469 18:02:51.355824 ==
8470 18:02:51.355923 RX Vref Scan: 0
8471 18:02:51.356025
8472 18:02:51.358907 RX Vref 0 -> 0, step: 1
8473 18:02:51.359005
8474 18:02:51.359103 RX Delay 0 -> 252, step: 8
8475 18:02:51.365548 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8476 18:02:51.368842 iDelay=200, Bit 1, Center 135 (88 ~ 183) 96
8477 18:02:51.372132 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8478 18:02:51.375383 iDelay=200, Bit 3, Center 139 (88 ~ 191) 104
8479 18:02:51.378597 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8480 18:02:51.385590 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8481 18:02:51.388818 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8482 18:02:51.392045 iDelay=200, Bit 7, Center 135 (88 ~ 183) 96
8483 18:02:51.395167 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8484 18:02:51.398863 iDelay=200, Bit 9, Center 119 (72 ~ 167) 96
8485 18:02:51.405070 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8486 18:02:51.408137 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8487 18:02:51.411459 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8488 18:02:51.415146 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8489 18:02:51.421725 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8490 18:02:51.424699 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8491 18:02:51.424800 ==
8492 18:02:51.428328 Dram Type= 6, Freq= 0, CH_1, rank 0
8493 18:02:51.431369 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8494 18:02:51.431471 ==
8495 18:02:51.431565 DQS Delay:
8496 18:02:51.435070 DQS0 = 0, DQS1 = 0
8497 18:02:51.435171 DQM Delay:
8498 18:02:51.438391 DQM0 = 138, DQM1 = 129
8499 18:02:51.438502 DQ Delay:
8500 18:02:51.441697 DQ0 =143, DQ1 =135, DQ2 =123, DQ3 =139
8501 18:02:51.444731 DQ4 =135, DQ5 =147, DQ6 =147, DQ7 =135
8502 18:02:51.447953 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
8503 18:02:51.454845 DQ12 =139, DQ13 =135, DQ14 =135, DQ15 =135
8504 18:02:51.454947
8505 18:02:51.455042
8506 18:02:51.455131 ==
8507 18:02:51.458227 Dram Type= 6, Freq= 0, CH_1, rank 0
8508 18:02:51.461575 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8509 18:02:51.461687 ==
8510 18:02:51.461785
8511 18:02:51.461877
8512 18:02:51.464326 TX Vref Scan disable
8513 18:02:51.464424 == TX Byte 0 ==
8514 18:02:51.471407 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8515 18:02:51.474733 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8516 18:02:51.474852 == TX Byte 1 ==
8517 18:02:51.481487 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8518 18:02:51.484263 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8519 18:02:51.484363 ==
8520 18:02:51.487696 Dram Type= 6, Freq= 0, CH_1, rank 0
8521 18:02:51.491125 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8522 18:02:51.491224 ==
8523 18:02:51.505087
8524 18:02:51.507860 TX Vref early break, caculate TX vref
8525 18:02:51.511188 TX Vref=16, minBit 10, minWin=21, winSum=366
8526 18:02:51.514628 TX Vref=18, minBit 9, minWin=22, winSum=372
8527 18:02:51.518069 TX Vref=20, minBit 10, minWin=22, winSum=385
8528 18:02:51.521462 TX Vref=22, minBit 8, minWin=24, winSum=398
8529 18:02:51.524544 TX Vref=24, minBit 10, minWin=23, winSum=405
8530 18:02:51.531305 TX Vref=26, minBit 10, minWin=25, winSum=420
8531 18:02:51.534272 TX Vref=28, minBit 13, minWin=24, winSum=417
8532 18:02:51.537952 TX Vref=30, minBit 9, minWin=24, winSum=412
8533 18:02:51.541224 TX Vref=32, minBit 13, minWin=23, winSum=403
8534 18:02:51.544635 TX Vref=34, minBit 8, minWin=23, winSum=395
8535 18:02:51.551239 [TxChooseVref] Worse bit 10, Min win 25, Win sum 420, Final Vref 26
8536 18:02:51.551358
8537 18:02:51.554395 Final TX Range 0 Vref 26
8538 18:02:51.554471
8539 18:02:51.554538 ==
8540 18:02:51.558196 Dram Type= 6, Freq= 0, CH_1, rank 0
8541 18:02:51.561009 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8542 18:02:51.561084 ==
8543 18:02:51.561145
8544 18:02:51.561202
8545 18:02:51.564747 TX Vref Scan disable
8546 18:02:51.571121 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8547 18:02:51.571198 == TX Byte 0 ==
8548 18:02:51.574353 u2DelayCellOfst[0]=16 cells (5 PI)
8549 18:02:51.578010 u2DelayCellOfst[1]=10 cells (3 PI)
8550 18:02:51.581250 u2DelayCellOfst[2]=0 cells (0 PI)
8551 18:02:51.584462 u2DelayCellOfst[3]=3 cells (1 PI)
8552 18:02:51.587844 u2DelayCellOfst[4]=6 cells (2 PI)
8553 18:02:51.591130 u2DelayCellOfst[5]=16 cells (5 PI)
8554 18:02:51.594393 u2DelayCellOfst[6]=16 cells (5 PI)
8555 18:02:51.597595 u2DelayCellOfst[7]=6 cells (2 PI)
8556 18:02:51.601276 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8557 18:02:51.604580 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8558 18:02:51.607910 == TX Byte 1 ==
8559 18:02:51.611203 u2DelayCellOfst[8]=0 cells (0 PI)
8560 18:02:51.611304 u2DelayCellOfst[9]=3 cells (1 PI)
8561 18:02:51.614434 u2DelayCellOfst[10]=10 cells (3 PI)
8562 18:02:51.617597 u2DelayCellOfst[11]=3 cells (1 PI)
8563 18:02:51.621203 u2DelayCellOfst[12]=16 cells (5 PI)
8564 18:02:51.624256 u2DelayCellOfst[13]=16 cells (5 PI)
8565 18:02:51.628062 u2DelayCellOfst[14]=20 cells (6 PI)
8566 18:02:51.631136 u2DelayCellOfst[15]=16 cells (5 PI)
8567 18:02:51.634225 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8568 18:02:51.641095 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8569 18:02:51.641199 DramC Write-DBI on
8570 18:02:51.641295 ==
8571 18:02:51.644274 Dram Type= 6, Freq= 0, CH_1, rank 0
8572 18:02:51.651146 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8573 18:02:51.651230 ==
8574 18:02:51.651296
8575 18:02:51.651358
8576 18:02:51.651416 TX Vref Scan disable
8577 18:02:51.654446 == TX Byte 0 ==
8578 18:02:51.658139 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8579 18:02:51.661509 == TX Byte 1 ==
8580 18:02:51.664814 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8581 18:02:51.667985 DramC Write-DBI off
8582 18:02:51.668068
8583 18:02:51.668134 [DATLAT]
8584 18:02:51.668195 Freq=1600, CH1 RK0
8585 18:02:51.668255
8586 18:02:51.671170 DATLAT Default: 0xf
8587 18:02:51.671267 0, 0xFFFF, sum = 0
8588 18:02:51.674466 1, 0xFFFF, sum = 0
8589 18:02:51.678028 2, 0xFFFF, sum = 0
8590 18:02:51.678112 3, 0xFFFF, sum = 0
8591 18:02:51.681198 4, 0xFFFF, sum = 0
8592 18:02:51.681318 5, 0xFFFF, sum = 0
8593 18:02:51.684441 6, 0xFFFF, sum = 0
8594 18:02:51.684556 7, 0xFFFF, sum = 0
8595 18:02:51.687698 8, 0xFFFF, sum = 0
8596 18:02:51.687781 9, 0xFFFF, sum = 0
8597 18:02:51.690930 10, 0xFFFF, sum = 0
8598 18:02:51.691021 11, 0xFFFF, sum = 0
8599 18:02:51.694249 12, 0xFFFF, sum = 0
8600 18:02:51.694332 13, 0xFFFF, sum = 0
8601 18:02:51.698000 14, 0x0, sum = 1
8602 18:02:51.698092 15, 0x0, sum = 2
8603 18:02:51.701092 16, 0x0, sum = 3
8604 18:02:51.701174 17, 0x0, sum = 4
8605 18:02:51.704232 best_step = 15
8606 18:02:51.704339
8607 18:02:51.704429 ==
8608 18:02:51.707461 Dram Type= 6, Freq= 0, CH_1, rank 0
8609 18:02:51.710795 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8610 18:02:51.710898 ==
8611 18:02:51.714214 RX Vref Scan: 1
8612 18:02:51.714288
8613 18:02:51.714349 Set Vref Range= 24 -> 127
8614 18:02:51.714445
8615 18:02:51.717442 RX Vref 24 -> 127, step: 1
8616 18:02:51.717542
8617 18:02:51.720676 RX Delay 19 -> 252, step: 4
8618 18:02:51.720772
8619 18:02:51.724385 Set Vref, RX VrefLevel [Byte0]: 24
8620 18:02:51.727513 [Byte1]: 24
8621 18:02:51.727612
8622 18:02:51.730707 Set Vref, RX VrefLevel [Byte0]: 25
8623 18:02:51.734466 [Byte1]: 25
8624 18:02:51.734539
8625 18:02:51.737445 Set Vref, RX VrefLevel [Byte0]: 26
8626 18:02:51.740561 [Byte1]: 26
8627 18:02:51.745004
8628 18:02:51.745101 Set Vref, RX VrefLevel [Byte0]: 27
8629 18:02:51.748197 [Byte1]: 27
8630 18:02:51.752476
8631 18:02:51.752612 Set Vref, RX VrefLevel [Byte0]: 28
8632 18:02:51.755707 [Byte1]: 28
8633 18:02:51.760117
8634 18:02:51.760190 Set Vref, RX VrefLevel [Byte0]: 29
8635 18:02:51.763274 [Byte1]: 29
8636 18:02:51.767699
8637 18:02:51.767782 Set Vref, RX VrefLevel [Byte0]: 30
8638 18:02:51.770843 [Byte1]: 30
8639 18:02:51.775148
8640 18:02:51.775229 Set Vref, RX VrefLevel [Byte0]: 31
8641 18:02:51.778493 [Byte1]: 31
8642 18:02:51.782779
8643 18:02:51.782860 Set Vref, RX VrefLevel [Byte0]: 32
8644 18:02:51.786005 [Byte1]: 32
8645 18:02:51.790307
8646 18:02:51.790389 Set Vref, RX VrefLevel [Byte0]: 33
8647 18:02:51.793516 [Byte1]: 33
8648 18:02:51.797980
8649 18:02:51.801294 Set Vref, RX VrefLevel [Byte0]: 34
8650 18:02:51.801376 [Byte1]: 34
8651 18:02:51.805521
8652 18:02:51.805602 Set Vref, RX VrefLevel [Byte0]: 35
8653 18:02:51.808804 [Byte1]: 35
8654 18:02:51.813239
8655 18:02:51.813325 Set Vref, RX VrefLevel [Byte0]: 36
8656 18:02:51.816431 [Byte1]: 36
8657 18:02:51.820953
8658 18:02:51.821034 Set Vref, RX VrefLevel [Byte0]: 37
8659 18:02:51.824036 [Byte1]: 37
8660 18:02:51.828415
8661 18:02:51.828497 Set Vref, RX VrefLevel [Byte0]: 38
8662 18:02:51.831530 [Byte1]: 38
8663 18:02:51.835758
8664 18:02:51.835840 Set Vref, RX VrefLevel [Byte0]: 39
8665 18:02:51.839034 [Byte1]: 39
8666 18:02:51.843534
8667 18:02:51.843615 Set Vref, RX VrefLevel [Byte0]: 40
8668 18:02:51.846617 [Byte1]: 40
8669 18:02:51.850734
8670 18:02:51.850806 Set Vref, RX VrefLevel [Byte0]: 41
8671 18:02:51.854653 [Byte1]: 41
8672 18:02:51.858330
8673 18:02:51.858401 Set Vref, RX VrefLevel [Byte0]: 42
8674 18:02:51.862236 [Byte1]: 42
8675 18:02:51.866093
8676 18:02:51.866163 Set Vref, RX VrefLevel [Byte0]: 43
8677 18:02:51.869477 [Byte1]: 43
8678 18:02:51.873769
8679 18:02:51.873842 Set Vref, RX VrefLevel [Byte0]: 44
8680 18:02:51.877055 [Byte1]: 44
8681 18:02:51.881367
8682 18:02:51.881439 Set Vref, RX VrefLevel [Byte0]: 45
8683 18:02:51.884556 [Byte1]: 45
8684 18:02:51.888795
8685 18:02:51.888866 Set Vref, RX VrefLevel [Byte0]: 46
8686 18:02:51.891888 [Byte1]: 46
8687 18:02:51.896340
8688 18:02:51.896415 Set Vref, RX VrefLevel [Byte0]: 47
8689 18:02:51.899498 [Byte1]: 47
8690 18:02:51.903926
8691 18:02:51.904002 Set Vref, RX VrefLevel [Byte0]: 48
8692 18:02:51.907244 [Byte1]: 48
8693 18:02:51.911470
8694 18:02:51.911543 Set Vref, RX VrefLevel [Byte0]: 49
8695 18:02:51.914850 [Byte1]: 49
8696 18:02:51.919137
8697 18:02:51.919208 Set Vref, RX VrefLevel [Byte0]: 50
8698 18:02:51.922564 [Byte1]: 50
8699 18:02:51.926423
8700 18:02:51.926494 Set Vref, RX VrefLevel [Byte0]: 51
8701 18:02:51.929623 [Byte1]: 51
8702 18:02:51.934435
8703 18:02:51.934505 Set Vref, RX VrefLevel [Byte0]: 52
8704 18:02:51.937468 [Byte1]: 52
8705 18:02:51.941779
8706 18:02:51.941849 Set Vref, RX VrefLevel [Byte0]: 53
8707 18:02:51.945069 [Byte1]: 53
8708 18:02:51.949219
8709 18:02:51.949290 Set Vref, RX VrefLevel [Byte0]: 54
8710 18:02:51.952724 [Byte1]: 54
8711 18:02:51.956843
8712 18:02:51.956914 Set Vref, RX VrefLevel [Byte0]: 55
8713 18:02:51.960065 [Byte1]: 55
8714 18:02:51.964409
8715 18:02:51.964508 Set Vref, RX VrefLevel [Byte0]: 56
8716 18:02:51.967656 [Byte1]: 56
8717 18:02:51.972165
8718 18:02:51.972239 Set Vref, RX VrefLevel [Byte0]: 57
8719 18:02:51.975362 [Byte1]: 57
8720 18:02:51.979760
8721 18:02:51.979831 Set Vref, RX VrefLevel [Byte0]: 58
8722 18:02:51.983015 [Byte1]: 58
8723 18:02:51.987410
8724 18:02:51.987483 Set Vref, RX VrefLevel [Byte0]: 59
8725 18:02:51.990598 [Byte1]: 59
8726 18:02:51.994739
8727 18:02:51.994816 Set Vref, RX VrefLevel [Byte0]: 60
8728 18:02:51.998042 [Byte1]: 60
8729 18:02:52.002512
8730 18:02:52.002624 Set Vref, RX VrefLevel [Byte0]: 61
8731 18:02:52.005626 [Byte1]: 61
8732 18:02:52.009987
8733 18:02:52.010061 Set Vref, RX VrefLevel [Byte0]: 62
8734 18:02:52.013247 [Byte1]: 62
8735 18:02:52.017588
8736 18:02:52.017660 Set Vref, RX VrefLevel [Byte0]: 63
8737 18:02:52.020895 [Byte1]: 63
8738 18:02:52.025167
8739 18:02:52.025242 Set Vref, RX VrefLevel [Byte0]: 64
8740 18:02:52.028378 [Byte1]: 64
8741 18:02:52.032743
8742 18:02:52.032815 Set Vref, RX VrefLevel [Byte0]: 65
8743 18:02:52.035966 [Byte1]: 65
8744 18:02:52.040205
8745 18:02:52.040276 Set Vref, RX VrefLevel [Byte0]: 66
8746 18:02:52.043736 [Byte1]: 66
8747 18:02:52.047517
8748 18:02:52.047592 Set Vref, RX VrefLevel [Byte0]: 67
8749 18:02:52.050868 [Byte1]: 67
8750 18:02:52.055394
8751 18:02:52.055468 Set Vref, RX VrefLevel [Byte0]: 68
8752 18:02:52.058492 [Byte1]: 68
8753 18:02:52.063182
8754 18:02:52.063251 Set Vref, RX VrefLevel [Byte0]: 69
8755 18:02:52.066505 [Byte1]: 69
8756 18:02:52.070332
8757 18:02:52.070402 Set Vref, RX VrefLevel [Byte0]: 70
8758 18:02:52.073579 [Byte1]: 70
8759 18:02:52.078434
8760 18:02:52.078506 Set Vref, RX VrefLevel [Byte0]: 71
8761 18:02:52.081623 [Byte1]: 71
8762 18:02:52.085770
8763 18:02:52.085849 Set Vref, RX VrefLevel [Byte0]: 72
8764 18:02:52.088993 [Byte1]: 72
8765 18:02:52.093379
8766 18:02:52.093452 Set Vref, RX VrefLevel [Byte0]: 73
8767 18:02:52.096511 [Byte1]: 73
8768 18:02:52.100706
8769 18:02:52.100781 Final RX Vref Byte 0 = 53 to rank0
8770 18:02:52.103866 Final RX Vref Byte 1 = 61 to rank0
8771 18:02:52.107628 Final RX Vref Byte 0 = 53 to rank1
8772 18:02:52.110851 Final RX Vref Byte 1 = 61 to rank1==
8773 18:02:52.114220 Dram Type= 6, Freq= 0, CH_1, rank 0
8774 18:02:52.120649 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8775 18:02:52.120726 ==
8776 18:02:52.120789 DQS Delay:
8777 18:02:52.120847 DQS0 = 0, DQS1 = 0
8778 18:02:52.123856 DQM Delay:
8779 18:02:52.123922 DQM0 = 133, DQM1 = 129
8780 18:02:52.127211 DQ Delay:
8781 18:02:52.130454 DQ0 =136, DQ1 =130, DQ2 =122, DQ3 =132
8782 18:02:52.133615 DQ4 =132, DQ5 =144, DQ6 =144, DQ7 =130
8783 18:02:52.137472 DQ8 =116, DQ9 =120, DQ10 =132, DQ11 =122
8784 18:02:52.140235 DQ12 =140, DQ13 =134, DQ14 =136, DQ15 =134
8785 18:02:52.140305
8786 18:02:52.140364
8787 18:02:52.140420
8788 18:02:52.143882 [DramC_TX_OE_Calibration] TA2
8789 18:02:52.147023 Original DQ_B0 (3 6) =30, OEN = 27
8790 18:02:52.150605 Original DQ_B1 (3 6) =30, OEN = 27
8791 18:02:52.153847 24, 0x0, End_B0=24 End_B1=24
8792 18:02:52.153921 25, 0x0, End_B0=25 End_B1=25
8793 18:02:52.156902 26, 0x0, End_B0=26 End_B1=26
8794 18:02:52.160507 27, 0x0, End_B0=27 End_B1=27
8795 18:02:52.163616 28, 0x0, End_B0=28 End_B1=28
8796 18:02:52.166603 29, 0x0, End_B0=29 End_B1=29
8797 18:02:52.166728 30, 0x0, End_B0=30 End_B1=30
8798 18:02:52.170518 31, 0x5151, End_B0=30 End_B1=30
8799 18:02:52.173385 Byte0 end_step=30 best_step=27
8800 18:02:52.177112 Byte1 end_step=30 best_step=27
8801 18:02:52.180156 Byte0 TX OE(2T, 0.5T) = (3, 3)
8802 18:02:52.183401 Byte1 TX OE(2T, 0.5T) = (3, 3)
8803 18:02:52.183483
8804 18:02:52.183548
8805 18:02:52.190319 [DQSOSCAuto] RK0, (LSB)MR18= 0x1624, (MSB)MR19= 0x303, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
8806 18:02:52.193597 CH1 RK0: MR19=303, MR18=1624
8807 18:02:52.200071 CH1_RK0: MR19=0x303, MR18=0x1624, DQSOSC=391, MR23=63, INC=24, DEC=16
8808 18:02:52.200154
8809 18:02:52.203231 ----->DramcWriteLeveling(PI) begin...
8810 18:02:52.203315 ==
8811 18:02:52.206453 Dram Type= 6, Freq= 0, CH_1, rank 1
8812 18:02:52.210093 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8813 18:02:52.210194 ==
8814 18:02:52.213249 Write leveling (Byte 0): 23 => 23
8815 18:02:52.216448 Write leveling (Byte 1): 29 => 29
8816 18:02:52.220205 DramcWriteLeveling(PI) end<-----
8817 18:02:52.220287
8818 18:02:52.220350 ==
8819 18:02:52.223448 Dram Type= 6, Freq= 0, CH_1, rank 1
8820 18:02:52.226550 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8821 18:02:52.226638 ==
8822 18:02:52.229832 [Gating] SW mode calibration
8823 18:02:52.236438 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8824 18:02:52.243125 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8825 18:02:52.246285 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8826 18:02:52.253056 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8827 18:02:52.256430 1 4 8 | B1->B0 | 3030 2323 | 1 0 | (1 1) (0 0)
8828 18:02:52.259559 1 4 12 | B1->B0 | 3434 2828 | 1 0 | (1 1) (0 0)
8829 18:02:52.266211 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8830 18:02:52.269385 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8831 18:02:52.272519 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8832 18:02:52.279552 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8833 18:02:52.282663 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8834 18:02:52.285881 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8835 18:02:52.292748 1 5 8 | B1->B0 | 2424 3434 | 0 1 | (1 0) (1 0)
8836 18:02:52.296018 1 5 12 | B1->B0 | 2323 2b2b | 0 1 | (1 0) (1 0)
8837 18:02:52.299374 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8838 18:02:52.305842 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8839 18:02:52.308941 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8840 18:02:52.312581 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8841 18:02:52.319161 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8842 18:02:52.322424 1 6 4 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
8843 18:02:52.325713 1 6 8 | B1->B0 | 4646 2323 | 0 0 | (0 0) (0 0)
8844 18:02:52.328878 1 6 12 | B1->B0 | 4646 4343 | 0 0 | (0 0) (0 0)
8845 18:02:52.335578 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8846 18:02:52.339260 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8847 18:02:52.342441 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8848 18:02:52.348859 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8849 18:02:52.352200 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8850 18:02:52.355893 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8851 18:02:52.362495 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8852 18:02:52.365511 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8853 18:02:52.368618 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8854 18:02:52.375412 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8855 18:02:52.378587 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8856 18:02:52.381837 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8857 18:02:52.388738 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8858 18:02:52.392047 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8859 18:02:52.395214 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8860 18:02:52.402360 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8861 18:02:52.405154 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8862 18:02:52.408942 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8863 18:02:52.415228 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8864 18:02:52.418334 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8865 18:02:52.421566 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8866 18:02:52.428302 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8867 18:02:52.431495 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8868 18:02:52.435300 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8869 18:02:52.441826 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8870 18:02:52.441901 Total UI for P1: 0, mck2ui 16
8871 18:02:52.448359 best dqsien dly found for B0: ( 1, 9, 10)
8872 18:02:52.448435 Total UI for P1: 0, mck2ui 16
8873 18:02:52.455375 best dqsien dly found for B1: ( 1, 9, 10)
8874 18:02:52.458487 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8875 18:02:52.461561 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8876 18:02:52.461639
8877 18:02:52.464862 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8878 18:02:52.468083 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8879 18:02:52.471578 [Gating] SW calibration Done
8880 18:02:52.471648 ==
8881 18:02:52.474729 Dram Type= 6, Freq= 0, CH_1, rank 1
8882 18:02:52.478377 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8883 18:02:52.478453 ==
8884 18:02:52.481415 RX Vref Scan: 0
8885 18:02:52.481545
8886 18:02:52.481664 RX Vref 0 -> 0, step: 1
8887 18:02:52.481780
8888 18:02:52.484706 RX Delay 0 -> 252, step: 8
8889 18:02:52.488015 iDelay=200, Bit 0, Center 139 (96 ~ 183) 88
8890 18:02:52.494856 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8891 18:02:52.498082 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8892 18:02:52.501452 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8893 18:02:52.504837 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8894 18:02:52.508053 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8895 18:02:52.515164 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
8896 18:02:52.518474 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8897 18:02:52.521415 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8898 18:02:52.524593 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8899 18:02:52.527942 iDelay=200, Bit 10, Center 135 (80 ~ 191) 112
8900 18:02:52.534769 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8901 18:02:52.537940 iDelay=200, Bit 12, Center 143 (88 ~ 199) 112
8902 18:02:52.541365 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8903 18:02:52.544537 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8904 18:02:52.547915 iDelay=200, Bit 15, Center 139 (80 ~ 199) 120
8905 18:02:52.551653 ==
8906 18:02:52.551769 Dram Type= 6, Freq= 0, CH_1, rank 1
8907 18:02:52.558070 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8908 18:02:52.558156 ==
8909 18:02:52.558258 DQS Delay:
8910 18:02:52.561381 DQS0 = 0, DQS1 = 0
8911 18:02:52.561466 DQM Delay:
8912 18:02:52.564418 DQM0 = 135, DQM1 = 131
8913 18:02:52.564505 DQ Delay:
8914 18:02:52.568079 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8915 18:02:52.571384 DQ4 =135, DQ5 =147, DQ6 =139, DQ7 =135
8916 18:02:52.574317 DQ8 =115, DQ9 =119, DQ10 =135, DQ11 =127
8917 18:02:52.577844 DQ12 =143, DQ13 =139, DQ14 =135, DQ15 =139
8918 18:02:52.577944
8919 18:02:52.578042
8920 18:02:52.578137 ==
8921 18:02:52.581378 Dram Type= 6, Freq= 0, CH_1, rank 1
8922 18:02:52.587739 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8923 18:02:52.587839 ==
8924 18:02:52.587923
8925 18:02:52.588002
8926 18:02:52.588080 TX Vref Scan disable
8927 18:02:52.591469 == TX Byte 0 ==
8928 18:02:52.594740 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8929 18:02:52.601523 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8930 18:02:52.601608 == TX Byte 1 ==
8931 18:02:52.604462 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8932 18:02:52.611427 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8933 18:02:52.611513 ==
8934 18:02:52.614686 Dram Type= 6, Freq= 0, CH_1, rank 1
8935 18:02:52.617918 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8936 18:02:52.618003 ==
8937 18:02:52.631604
8938 18:02:52.634962 TX Vref early break, caculate TX vref
8939 18:02:52.638148 TX Vref=16, minBit 9, minWin=22, winSum=378
8940 18:02:52.641889 TX Vref=18, minBit 8, minWin=22, winSum=383
8941 18:02:52.645249 TX Vref=20, minBit 10, minWin=22, winSum=395
8942 18:02:52.648369 TX Vref=22, minBit 9, minWin=24, winSum=402
8943 18:02:52.651593 TX Vref=24, minBit 9, minWin=24, winSum=412
8944 18:02:52.658564 TX Vref=26, minBit 11, minWin=24, winSum=417
8945 18:02:52.661949 TX Vref=28, minBit 11, minWin=24, winSum=418
8946 18:02:52.665237 TX Vref=30, minBit 8, minWin=24, winSum=410
8947 18:02:52.668384 TX Vref=32, minBit 9, minWin=24, winSum=407
8948 18:02:52.671537 TX Vref=34, minBit 8, minWin=24, winSum=398
8949 18:02:52.674787 TX Vref=36, minBit 8, minWin=22, winSum=387
8950 18:02:52.681576 [TxChooseVref] Worse bit 11, Min win 24, Win sum 418, Final Vref 28
8951 18:02:52.681666
8952 18:02:52.684728 Final TX Range 0 Vref 28
8953 18:02:52.684801
8954 18:02:52.684877 ==
8955 18:02:52.688266 Dram Type= 6, Freq= 0, CH_1, rank 1
8956 18:02:52.691441 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8957 18:02:52.691516 ==
8958 18:02:52.695066
8959 18:02:52.695138
8960 18:02:52.695198 TX Vref Scan disable
8961 18:02:52.701247 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8962 18:02:52.701330 == TX Byte 0 ==
8963 18:02:52.704817 u2DelayCellOfst[0]=16 cells (5 PI)
8964 18:02:52.707906 u2DelayCellOfst[1]=10 cells (3 PI)
8965 18:02:52.711227 u2DelayCellOfst[2]=0 cells (0 PI)
8966 18:02:52.714444 u2DelayCellOfst[3]=6 cells (2 PI)
8967 18:02:52.717670 u2DelayCellOfst[4]=6 cells (2 PI)
8968 18:02:52.721320 u2DelayCellOfst[5]=16 cells (5 PI)
8969 18:02:52.724624 u2DelayCellOfst[6]=16 cells (5 PI)
8970 18:02:52.728052 u2DelayCellOfst[7]=3 cells (1 PI)
8971 18:02:52.731133 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8972 18:02:52.734441 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8973 18:02:52.737707 == TX Byte 1 ==
8974 18:02:52.741110 u2DelayCellOfst[8]=0 cells (0 PI)
8975 18:02:52.744493 u2DelayCellOfst[9]=3 cells (1 PI)
8976 18:02:52.747426 u2DelayCellOfst[10]=10 cells (3 PI)
8977 18:02:52.751167 u2DelayCellOfst[11]=0 cells (0 PI)
8978 18:02:52.754473 u2DelayCellOfst[12]=13 cells (4 PI)
8979 18:02:52.754542 u2DelayCellOfst[13]=16 cells (5 PI)
8980 18:02:52.757797 u2DelayCellOfst[14]=16 cells (5 PI)
8981 18:02:52.761095 u2DelayCellOfst[15]=16 cells (5 PI)
8982 18:02:52.767741 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8983 18:02:52.771016 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8984 18:02:52.771086 DramC Write-DBI on
8985 18:02:52.774045 ==
8986 18:02:52.777275 Dram Type= 6, Freq= 0, CH_1, rank 1
8987 18:02:52.780442 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8988 18:02:52.780527 ==
8989 18:02:52.780654
8990 18:02:52.780730
8991 18:02:52.784101 TX Vref Scan disable
8992 18:02:52.784215 == TX Byte 0 ==
8993 18:02:52.790396 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
8994 18:02:52.790485 == TX Byte 1 ==
8995 18:02:52.793996 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8996 18:02:52.797327 DramC Write-DBI off
8997 18:02:52.797403
8998 18:02:52.797464 [DATLAT]
8999 18:02:52.800579 Freq=1600, CH1 RK1
9000 18:02:52.800663
9001 18:02:52.800722 DATLAT Default: 0xf
9002 18:02:52.803913 0, 0xFFFF, sum = 0
9003 18:02:52.804016 1, 0xFFFF, sum = 0
9004 18:02:52.807150 2, 0xFFFF, sum = 0
9005 18:02:52.807280 3, 0xFFFF, sum = 0
9006 18:02:52.810361 4, 0xFFFF, sum = 0
9007 18:02:52.810492 5, 0xFFFF, sum = 0
9008 18:02:52.813613 6, 0xFFFF, sum = 0
9009 18:02:52.816824 7, 0xFFFF, sum = 0
9010 18:02:52.816910 8, 0xFFFF, sum = 0
9011 18:02:52.820111 9, 0xFFFF, sum = 0
9012 18:02:52.820211 10, 0xFFFF, sum = 0
9013 18:02:52.823364 11, 0xFFFF, sum = 0
9014 18:02:52.823479 12, 0xFFFF, sum = 0
9015 18:02:52.827168 13, 0xFFFF, sum = 0
9016 18:02:52.827268 14, 0x0, sum = 1
9017 18:02:52.830557 15, 0x0, sum = 2
9018 18:02:52.830655 16, 0x0, sum = 3
9019 18:02:52.833751 17, 0x0, sum = 4
9020 18:02:52.833849 best_step = 15
9021 18:02:52.833946
9022 18:02:52.834068 ==
9023 18:02:52.836994 Dram Type= 6, Freq= 0, CH_1, rank 1
9024 18:02:52.840327 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9025 18:02:52.843495 ==
9026 18:02:52.843594 RX Vref Scan: 0
9027 18:02:52.843691
9028 18:02:52.846819 RX Vref 0 -> 0, step: 1
9029 18:02:52.846917
9030 18:02:52.847012 RX Delay 19 -> 252, step: 4
9031 18:02:52.853943 iDelay=195, Bit 0, Center 138 (95 ~ 182) 88
9032 18:02:52.857659 iDelay=195, Bit 1, Center 132 (87 ~ 178) 92
9033 18:02:52.860850 iDelay=195, Bit 2, Center 120 (71 ~ 170) 100
9034 18:02:52.864134 iDelay=195, Bit 3, Center 132 (83 ~ 182) 100
9035 18:02:52.867558 iDelay=195, Bit 4, Center 134 (87 ~ 182) 96
9036 18:02:52.874044 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
9037 18:02:52.877216 iDelay=195, Bit 6, Center 140 (91 ~ 190) 100
9038 18:02:52.880739 iDelay=195, Bit 7, Center 130 (83 ~ 178) 96
9039 18:02:52.883976 iDelay=195, Bit 8, Center 112 (63 ~ 162) 100
9040 18:02:52.887171 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
9041 18:02:52.890683 iDelay=195, Bit 10, Center 130 (79 ~ 182) 104
9042 18:02:52.897535 iDelay=195, Bit 11, Center 126 (75 ~ 178) 104
9043 18:02:52.900680 iDelay=195, Bit 12, Center 138 (87 ~ 190) 104
9044 18:02:52.903777 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
9045 18:02:52.907579 iDelay=195, Bit 14, Center 138 (91 ~ 186) 96
9046 18:02:52.913885 iDelay=195, Bit 15, Center 140 (87 ~ 194) 108
9047 18:02:52.913968 ==
9048 18:02:52.917281 Dram Type= 6, Freq= 0, CH_1, rank 1
9049 18:02:52.920435 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9050 18:02:52.920540 ==
9051 18:02:52.920648 DQS Delay:
9052 18:02:52.924198 DQS0 = 0, DQS1 = 0
9053 18:02:52.924281 DQM Delay:
9054 18:02:52.927479 DQM0 = 134, DQM1 = 130
9055 18:02:52.927552 DQ Delay:
9056 18:02:52.930614 DQ0 =138, DQ1 =132, DQ2 =120, DQ3 =132
9057 18:02:52.933829 DQ4 =134, DQ5 =146, DQ6 =140, DQ7 =130
9058 18:02:52.937040 DQ8 =112, DQ9 =118, DQ10 =130, DQ11 =126
9059 18:02:52.940863 DQ12 =138, DQ13 =138, DQ14 =138, DQ15 =140
9060 18:02:52.940934
9061 18:02:52.940995
9062 18:02:52.941056
9063 18:02:52.944014 [DramC_TX_OE_Calibration] TA2
9064 18:02:52.947317 Original DQ_B0 (3 6) =30, OEN = 27
9065 18:02:52.950576 Original DQ_B1 (3 6) =30, OEN = 27
9066 18:02:52.953911 24, 0x0, End_B0=24 End_B1=24
9067 18:02:52.957183 25, 0x0, End_B0=25 End_B1=25
9068 18:02:52.957258 26, 0x0, End_B0=26 End_B1=26
9069 18:02:52.960915 27, 0x0, End_B0=27 End_B1=27
9070 18:02:52.964201 28, 0x0, End_B0=28 End_B1=28
9071 18:02:52.967455 29, 0x0, End_B0=29 End_B1=29
9072 18:02:52.970362 30, 0x0, End_B0=30 End_B1=30
9073 18:02:52.970463 31, 0x4545, End_B0=30 End_B1=30
9074 18:02:52.974147 Byte0 end_step=30 best_step=27
9075 18:02:52.977302 Byte1 end_step=30 best_step=27
9076 18:02:52.980480 Byte0 TX OE(2T, 0.5T) = (3, 3)
9077 18:02:52.984150 Byte1 TX OE(2T, 0.5T) = (3, 3)
9078 18:02:52.984250
9079 18:02:52.984339
9080 18:02:52.990638 [DQSOSCAuto] RK1, (LSB)MR18= 0x1905, (MSB)MR19= 0x303, tDQSOscB0 = 407 ps tDQSOscB1 = 397 ps
9081 18:02:52.993822 CH1 RK1: MR19=303, MR18=1905
9082 18:02:53.000427 CH1_RK1: MR19=0x303, MR18=0x1905, DQSOSC=397, MR23=63, INC=23, DEC=15
9083 18:02:53.003506 [RxdqsGatingPostProcess] freq 1600
9084 18:02:53.010523 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9085 18:02:53.010629 best DQS0 dly(2T, 0.5T) = (1, 1)
9086 18:02:53.013882 best DQS1 dly(2T, 0.5T) = (1, 1)
9087 18:02:53.017037 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9088 18:02:53.020244 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9089 18:02:53.023939 best DQS0 dly(2T, 0.5T) = (1, 1)
9090 18:02:53.027079 best DQS1 dly(2T, 0.5T) = (1, 1)
9091 18:02:53.030395 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9092 18:02:53.033702 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9093 18:02:53.037098 Pre-setting of DQS Precalculation
9094 18:02:53.040231 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9095 18:02:53.050186 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9096 18:02:53.056795 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9097 18:02:53.056870
9098 18:02:53.056932
9099 18:02:53.060155 [Calibration Summary] 3200 Mbps
9100 18:02:53.060265 CH 0, Rank 0
9101 18:02:53.063345 SW Impedance : PASS
9102 18:02:53.063456 DUTY Scan : NO K
9103 18:02:53.066656 ZQ Calibration : PASS
9104 18:02:53.069978 Jitter Meter : NO K
9105 18:02:53.070089 CBT Training : PASS
9106 18:02:53.073218 Write leveling : PASS
9107 18:02:53.076515 RX DQS gating : PASS
9108 18:02:53.076619 RX DQ/DQS(RDDQC) : PASS
9109 18:02:53.079827 TX DQ/DQS : PASS
9110 18:02:53.083156 RX DATLAT : PASS
9111 18:02:53.083240 RX DQ/DQS(Engine): PASS
9112 18:02:53.087248 TX OE : PASS
9113 18:02:53.087358 All Pass.
9114 18:02:53.087448
9115 18:02:53.089922 CH 0, Rank 1
9116 18:02:53.090033 SW Impedance : PASS
9117 18:02:53.093191 DUTY Scan : NO K
9118 18:02:53.096496 ZQ Calibration : PASS
9119 18:02:53.096606 Jitter Meter : NO K
9120 18:02:53.100096 CBT Training : PASS
9121 18:02:53.100226 Write leveling : PASS
9122 18:02:53.103163 RX DQS gating : PASS
9123 18:02:53.106687 RX DQ/DQS(RDDQC) : PASS
9124 18:02:53.106791 TX DQ/DQS : PASS
9125 18:02:53.109803 RX DATLAT : PASS
9126 18:02:53.112987 RX DQ/DQS(Engine): PASS
9127 18:02:53.113063 TX OE : PASS
9128 18:02:53.116731 All Pass.
9129 18:02:53.116841
9130 18:02:53.116915 CH 1, Rank 0
9131 18:02:53.120077 SW Impedance : PASS
9132 18:02:53.120172 DUTY Scan : NO K
9133 18:02:53.123333 ZQ Calibration : PASS
9134 18:02:53.126327 Jitter Meter : NO K
9135 18:02:53.126423 CBT Training : PASS
9136 18:02:53.129804 Write leveling : PASS
9137 18:02:53.132833 RX DQS gating : PASS
9138 18:02:53.132906 RX DQ/DQS(RDDQC) : PASS
9139 18:02:53.136178 TX DQ/DQS : PASS
9140 18:02:53.139457 RX DATLAT : PASS
9141 18:02:53.139551 RX DQ/DQS(Engine): PASS
9142 18:02:53.142867 TX OE : PASS
9143 18:02:53.142959 All Pass.
9144 18:02:53.143047
9145 18:02:53.146180 CH 1, Rank 1
9146 18:02:53.146246 SW Impedance : PASS
9147 18:02:53.149800 DUTY Scan : NO K
9148 18:02:53.153148 ZQ Calibration : PASS
9149 18:02:53.153217 Jitter Meter : NO K
9150 18:02:53.156422 CBT Training : PASS
9151 18:02:53.156532 Write leveling : PASS
9152 18:02:53.159681 RX DQS gating : PASS
9153 18:02:53.163125 RX DQ/DQS(RDDQC) : PASS
9154 18:02:53.163279 TX DQ/DQS : PASS
9155 18:02:53.166377 RX DATLAT : PASS
9156 18:02:53.169628 RX DQ/DQS(Engine): PASS
9157 18:02:53.169711 TX OE : PASS
9158 18:02:53.172935 All Pass.
9159 18:02:53.173030
9160 18:02:53.173117 DramC Write-DBI on
9161 18:02:53.176259 PER_BANK_REFRESH: Hybrid Mode
9162 18:02:53.176329 TX_TRACKING: ON
9163 18:02:53.185917 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9164 18:02:53.195918 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9165 18:02:53.202681 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9166 18:02:53.206049 [FAST_K] Save calibration result to emmc
9167 18:02:53.209521 sync common calibartion params.
9168 18:02:53.209596 sync cbt_mode0:1, 1:1
9169 18:02:53.212430 dram_init: ddr_geometry: 2
9170 18:02:53.216117 dram_init: ddr_geometry: 2
9171 18:02:53.219407 dram_init: ddr_geometry: 2
9172 18:02:53.219505 0:dram_rank_size:100000000
9173 18:02:53.222749 1:dram_rank_size:100000000
9174 18:02:53.229221 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9175 18:02:53.229294 DFS_SHUFFLE_HW_MODE: ON
9176 18:02:53.232461 dramc_set_vcore_voltage set vcore to 725000
9177 18:02:53.235668 Read voltage for 1600, 0
9178 18:02:53.235763 Vio18 = 0
9179 18:02:53.239435 Vcore = 725000
9180 18:02:53.239505 Vdram = 0
9181 18:02:53.239564 Vddq = 0
9182 18:02:53.242223 Vmddr = 0
9183 18:02:53.242290 switch to 3200 Mbps bootup
9184 18:02:53.245563 [DramcRunTimeConfig]
9185 18:02:53.245630 PHYPLL
9186 18:02:53.249361 DPM_CONTROL_AFTERK: ON
9187 18:02:53.249428 PER_BANK_REFRESH: ON
9188 18:02:53.252776 REFRESH_OVERHEAD_REDUCTION: ON
9189 18:02:53.255931 CMD_PICG_NEW_MODE: OFF
9190 18:02:53.256026 XRTWTW_NEW_MODE: ON
9191 18:02:53.259291 XRTRTR_NEW_MODE: ON
9192 18:02:53.259383 TX_TRACKING: ON
9193 18:02:53.262378 RDSEL_TRACKING: OFF
9194 18:02:53.265747 DQS Precalculation for DVFS: ON
9195 18:02:53.265816 RX_TRACKING: OFF
9196 18:02:53.268926 HW_GATING DBG: ON
9197 18:02:53.268997 ZQCS_ENABLE_LP4: ON
9198 18:02:53.272663 RX_PICG_NEW_MODE: ON
9199 18:02:53.272756 TX_PICG_NEW_MODE: ON
9200 18:02:53.275446 ENABLE_RX_DCM_DPHY: ON
9201 18:02:53.279188 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9202 18:02:53.282509 DUMMY_READ_FOR_TRACKING: OFF
9203 18:02:53.282603 !!! SPM_CONTROL_AFTERK: OFF
9204 18:02:53.285831 !!! SPM could not control APHY
9205 18:02:53.289024 IMPEDANCE_TRACKING: ON
9206 18:02:53.289126 TEMP_SENSOR: ON
9207 18:02:53.292314 HW_SAVE_FOR_SR: OFF
9208 18:02:53.295578 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9209 18:02:53.298846 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9210 18:02:53.302138 Read ODT Tracking: ON
9211 18:02:53.302245 Refresh Rate DeBounce: ON
9212 18:02:53.305789 DFS_NO_QUEUE_FLUSH: ON
9213 18:02:53.308854 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9214 18:02:53.312378 ENABLE_DFS_RUNTIME_MRW: OFF
9215 18:02:53.312489 DDR_RESERVE_NEW_MODE: ON
9216 18:02:53.315598 MR_CBT_SWITCH_FREQ: ON
9217 18:02:53.318748 =========================
9218 18:02:53.336134 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9219 18:02:53.339368 dram_init: ddr_geometry: 2
9220 18:02:53.357838 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9221 18:02:53.361114 dram_init: dram init end (result: 0)
9222 18:02:53.367587 DRAM-K: Full calibration passed in 24519 msecs
9223 18:02:53.371232 MRC: failed to locate region type 0.
9224 18:02:53.371330 DRAM rank0 size:0x100000000,
9225 18:02:53.374405 DRAM rank1 size=0x100000000
9226 18:02:53.384660 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9227 18:02:53.391195 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9228 18:02:53.397663 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9229 18:02:53.404218 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9230 18:02:53.407938 DRAM rank0 size:0x100000000,
9231 18:02:53.411019 DRAM rank1 size=0x100000000
9232 18:02:53.411116 CBMEM:
9233 18:02:53.414411 IMD: root @ 0xfffff000 254 entries.
9234 18:02:53.417548 IMD: root @ 0xffffec00 62 entries.
9235 18:02:53.420751 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9236 18:02:53.424446 WARNING: RO_VPD is uninitialized or empty.
9237 18:02:53.430739 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9238 18:02:53.437651 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9239 18:02:53.450340 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9240 18:02:53.462330 BS: romstage times (exec / console): total (unknown) / 24015 ms
9241 18:02:53.462431
9242 18:02:53.462521
9243 18:02:53.472225 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9244 18:02:53.475420 ARM64: Exception handlers installed.
9245 18:02:53.478624 ARM64: Testing exception
9246 18:02:53.481958 ARM64: Done test exception
9247 18:02:53.482046 Enumerating buses...
9248 18:02:53.485240 Show all devs... Before device enumeration.
9249 18:02:53.488513 Root Device: enabled 1
9250 18:02:53.491743 CPU_CLUSTER: 0: enabled 1
9251 18:02:53.491812 CPU: 00: enabled 1
9252 18:02:53.495019 Compare with tree...
9253 18:02:53.495090 Root Device: enabled 1
9254 18:02:53.498794 CPU_CLUSTER: 0: enabled 1
9255 18:02:53.502042 CPU: 00: enabled 1
9256 18:02:53.502112 Root Device scanning...
9257 18:02:53.505126 scan_static_bus for Root Device
9258 18:02:53.508526 CPU_CLUSTER: 0 enabled
9259 18:02:53.511778 scan_static_bus for Root Device done
9260 18:02:53.515281 scan_bus: bus Root Device finished in 8 msecs
9261 18:02:53.515353 done
9262 18:02:53.521930 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9263 18:02:53.525285 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9264 18:02:53.532008 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9265 18:02:53.535381 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9266 18:02:53.538423 Allocating resources...
9267 18:02:53.541762 Reading resources...
9268 18:02:53.545005 Root Device read_resources bus 0 link: 0
9269 18:02:53.545084 DRAM rank0 size:0x100000000,
9270 18:02:53.548348 DRAM rank1 size=0x100000000
9271 18:02:53.551871 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9272 18:02:53.555294 CPU: 00 missing read_resources
9273 18:02:53.558096 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9274 18:02:53.565146 Root Device read_resources bus 0 link: 0 done
9275 18:02:53.565235 Done reading resources.
9276 18:02:53.571375 Show resources in subtree (Root Device)...After reading.
9277 18:02:53.574688 Root Device child on link 0 CPU_CLUSTER: 0
9278 18:02:53.578469 CPU_CLUSTER: 0 child on link 0 CPU: 00
9279 18:02:53.588353 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9280 18:02:53.588460 CPU: 00
9281 18:02:53.591636 Root Device assign_resources, bus 0 link: 0
9282 18:02:53.594854 CPU_CLUSTER: 0 missing set_resources
9283 18:02:53.601609 Root Device assign_resources, bus 0 link: 0 done
9284 18:02:53.601685 Done setting resources.
9285 18:02:53.608402 Show resources in subtree (Root Device)...After assigning values.
9286 18:02:53.611633 Root Device child on link 0 CPU_CLUSTER: 0
9287 18:02:53.614922 CPU_CLUSTER: 0 child on link 0 CPU: 00
9288 18:02:53.625034 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9289 18:02:53.625113 CPU: 00
9290 18:02:53.628228 Done allocating resources.
9291 18:02:53.631425 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9292 18:02:53.634703 Enabling resources...
9293 18:02:53.634772 done.
9294 18:02:53.641074 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9295 18:02:53.641157 Initializing devices...
9296 18:02:53.644797 Root Device init
9297 18:02:53.644866 init hardware done!
9298 18:02:53.648024 0x00000018: ctrlr->caps
9299 18:02:53.651193 52.000 MHz: ctrlr->f_max
9300 18:02:53.651284 0.400 MHz: ctrlr->f_min
9301 18:02:53.654628 0x40ff8080: ctrlr->voltages
9302 18:02:53.654729 sclk: 390625
9303 18:02:53.657780 Bus Width = 1
9304 18:02:53.657879 sclk: 390625
9305 18:02:53.661062 Bus Width = 1
9306 18:02:53.661160 Early init status = 3
9307 18:02:53.668140 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9308 18:02:53.671269 in-header: 03 fc 00 00 01 00 00 00
9309 18:02:53.674421 in-data: 00
9310 18:02:53.677724 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9311 18:02:53.683144 in-header: 03 fd 00 00 00 00 00 00
9312 18:02:53.686392 in-data:
9313 18:02:53.689808 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9314 18:02:53.694207 in-header: 03 fc 00 00 01 00 00 00
9315 18:02:53.697452 in-data: 00
9316 18:02:53.700654 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9317 18:02:53.706224 in-header: 03 fd 00 00 00 00 00 00
9318 18:02:53.709883 in-data:
9319 18:02:53.713068 [SSUSB] Setting up USB HOST controller...
9320 18:02:53.716201 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9321 18:02:53.719950 [SSUSB] phy power-on done.
9322 18:02:53.723167 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9323 18:02:53.729872 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9324 18:02:53.733088 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9325 18:02:53.739486 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9326 18:02:53.746278 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9327 18:02:53.752836 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9328 18:02:53.759422 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9329 18:02:53.766240 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9330 18:02:53.769446 SPM: binary array size = 0x9dc
9331 18:02:53.772760 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9332 18:02:53.779632 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9333 18:02:53.786215 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9334 18:02:53.789614 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9335 18:02:53.792800 configure_display: Starting display init
9336 18:02:53.829506 anx7625_power_on_init: Init interface.
9337 18:02:53.833207 anx7625_disable_pd_protocol: Disabled PD feature.
9338 18:02:53.836412 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9339 18:02:53.863773 anx7625_start_dp_work: Secure OCM version=00
9340 18:02:53.867003 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9341 18:02:53.881893 sp_tx_get_edid_block: EDID Block = 1
9342 18:02:53.984829 Extracted contents:
9343 18:02:53.988107 header: 00 ff ff ff ff ff ff 00
9344 18:02:53.991063 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9345 18:02:53.994864 version: 01 04
9346 18:02:53.998080 basic params: 95 1f 11 78 0a
9347 18:02:54.001343 chroma info: 76 90 94 55 54 90 27 21 50 54
9348 18:02:54.004699 established: 00 00 00
9349 18:02:54.011352 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9350 18:02:54.014717 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9351 18:02:54.021450 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9352 18:02:54.027799 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9353 18:02:54.034398 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9354 18:02:54.037887 extensions: 00
9355 18:02:54.037965 checksum: fb
9356 18:02:54.038036
9357 18:02:54.041077 Manufacturer: IVO Model 57d Serial Number 0
9358 18:02:54.044539 Made week 0 of 2020
9359 18:02:54.044622 EDID version: 1.4
9360 18:02:54.047397 Digital display
9361 18:02:54.051135 6 bits per primary color channel
9362 18:02:54.051206 DisplayPort interface
9363 18:02:54.054314 Maximum image size: 31 cm x 17 cm
9364 18:02:54.057668 Gamma: 220%
9365 18:02:54.057737 Check DPMS levels
9366 18:02:54.060650 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9367 18:02:54.064462 First detailed timing is preferred timing
9368 18:02:54.067789 Established timings supported:
9369 18:02:54.070767 Standard timings supported:
9370 18:02:54.074060 Detailed timings
9371 18:02:54.077361 Hex of detail: 383680a07038204018303c0035ae10000019
9372 18:02:54.081141 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9373 18:02:54.087645 0780 0798 07c8 0820 hborder 0
9374 18:02:54.091022 0438 043b 0447 0458 vborder 0
9375 18:02:54.094154 -hsync -vsync
9376 18:02:54.094235 Did detailed timing
9377 18:02:54.100617 Hex of detail: 000000000000000000000000000000000000
9378 18:02:54.100697 Manufacturer-specified data, tag 0
9379 18:02:54.107256 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9380 18:02:54.110684 ASCII string: InfoVision
9381 18:02:54.114083 Hex of detail: 000000fe00523134304e574635205248200a
9382 18:02:54.117504 ASCII string: R140NWF5 RH
9383 18:02:54.117590 Checksum
9384 18:02:54.117652 Checksum: 0xfb (valid)
9385 18:02:54.124241 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9386 18:02:54.126983 DSI data_rate: 832800000 bps
9387 18:02:54.133994 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9388 18:02:54.137296 anx7625_parse_edid: pixelclock(138800).
9389 18:02:54.140743 hactive(1920), hsync(48), hfp(24), hbp(88)
9390 18:02:54.144012 vactive(1080), vsync(12), vfp(3), vbp(17)
9391 18:02:54.147200 anx7625_dsi_config: config dsi.
9392 18:02:54.153996 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9393 18:02:54.166460 anx7625_dsi_config: success to config DSI
9394 18:02:54.170376 anx7625_dp_start: MIPI phy setup OK.
9395 18:02:54.173677 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9396 18:02:54.176877 mtk_ddp_mode_set invalid vrefresh 60
9397 18:02:54.180232 main_disp_path_setup
9398 18:02:54.180338 ovl_layer_smi_id_en
9399 18:02:54.183515 ovl_layer_smi_id_en
9400 18:02:54.183595 ccorr_config
9401 18:02:54.183659 aal_config
9402 18:02:54.186596 gamma_config
9403 18:02:54.186666 postmask_config
9404 18:02:54.190162 dither_config
9405 18:02:54.193462 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9406 18:02:54.200616 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9407 18:02:54.203823 Root Device init finished in 555 msecs
9408 18:02:54.204337 CPU_CLUSTER: 0 init
9409 18:02:54.213628 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9410 18:02:54.216921 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9411 18:02:54.220642 APU_MBOX 0x190000b0 = 0x10001
9412 18:02:54.223517 APU_MBOX 0x190001b0 = 0x10001
9413 18:02:54.227218 APU_MBOX 0x190005b0 = 0x10001
9414 18:02:54.230578 APU_MBOX 0x190006b0 = 0x10001
9415 18:02:54.233689 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9416 18:02:54.245878 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9417 18:02:54.258630 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9418 18:02:54.264965 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9419 18:02:54.276850 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9420 18:02:54.285210 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9421 18:02:54.288515 CPU_CLUSTER: 0 init finished in 81 msecs
9422 18:02:54.291963 Devices initialized
9423 18:02:54.295366 Show all devs... After init.
9424 18:02:54.295471 Root Device: enabled 1
9425 18:02:54.298711 CPU_CLUSTER: 0: enabled 1
9426 18:02:54.302023 CPU: 00: enabled 1
9427 18:02:54.305247 BS: BS_DEV_INIT run times (exec / console): 214 / 447 ms
9428 18:02:54.308570 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9429 18:02:54.312139 ELOG: NV offset 0x57f000 size 0x1000
9430 18:02:54.318788 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9431 18:02:54.325170 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9432 18:02:54.328387 ELOG: Event(17) added with size 13 at 2024-06-11 18:01:28 UTC
9433 18:02:54.335315 out: cmd=0x121: 03 db 21 01 00 00 00 00
9434 18:02:54.338474 in-header: 03 31 00 00 2c 00 00 00
9435 18:02:54.351964 in-data: 0d 71 00 00 00 00 00 00 0a 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9436 18:02:54.355069 ELOG: Event(A1) added with size 10 at 2024-06-11 18:01:28 UTC
9437 18:02:54.361622 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
9438 18:02:54.368841 ELOG: Event(A0) added with size 9 at 2024-06-11 18:01:28 UTC
9439 18:02:54.371496 elog_add_boot_reason: Logged dev mode boot
9440 18:02:54.378893 BS: BS_POST_DEVICE entry times (exec / console): 3 / 64 ms
9441 18:02:54.379522 Finalize devices...
9442 18:02:54.381913 Devices finalized
9443 18:02:54.385100 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9444 18:02:54.388474 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
9445 18:02:54.391698 in-header: 03 07 00 00 08 00 00 00
9446 18:02:54.395092 in-data: aa e4 47 04 13 02 00 00
9447 18:02:54.398709 Chrome EC: UHEPI supported
9448 18:02:54.404881 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
9449 18:02:54.408171 in-header: 03 a9 00 00 08 00 00 00
9450 18:02:54.411549 in-data: 84 60 60 08 00 00 00 00
9451 18:02:54.418260 ELOG: Event(91) added with size 10 at 2024-06-11 18:01:28 UTC
9452 18:02:54.421565 Chrome EC: clear events_b mask to 0x0000000020004000
9453 18:02:54.428324 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
9454 18:02:54.432203 in-header: 03 fd 00 00 00 00 00 00
9455 18:02:54.435513 in-data:
9456 18:02:54.438643 BS: BS_WRITE_TABLES entry times (exec / console): 2 / 46 ms
9457 18:02:54.441991 Writing coreboot table at 0xffe64000
9458 18:02:54.445297 0. 000000000010a000-0000000000113fff: RAMSTAGE
9459 18:02:54.451926 1. 0000000040000000-00000000400fffff: RAM
9460 18:02:54.455309 2. 0000000040100000-000000004032afff: RAMSTAGE
9461 18:02:54.458592 3. 000000004032b000-00000000545fffff: RAM
9462 18:02:54.461898 4. 0000000054600000-000000005465ffff: BL31
9463 18:02:54.465672 5. 0000000054660000-00000000ffe63fff: RAM
9464 18:02:54.471859 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9465 18:02:54.475329 7. 0000000100000000-000000023fffffff: RAM
9466 18:02:54.478384 Passing 5 GPIOs to payload:
9467 18:02:54.481617 NAME | PORT | POLARITY | VALUE
9468 18:02:54.488371 EC in RW | 0x000000aa | low | undefined
9469 18:02:54.491511 EC interrupt | 0x00000005 | low | undefined
9470 18:02:54.494867 TPM interrupt | 0x000000ab | high | undefined
9471 18:02:54.501389 SD card detect | 0x00000011 | high | undefined
9472 18:02:54.504685 speaker enable | 0x00000093 | high | undefined
9473 18:02:54.507988 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9474 18:02:54.511416 in-header: 03 f9 00 00 02 00 00 00
9475 18:02:54.514789 in-data: 02 00
9476 18:02:54.518241 ADC[4]: Raw value=900663 ID=7
9477 18:02:54.518357 ADC[3]: Raw value=213179 ID=1
9478 18:02:54.521265 RAM Code: 0x71
9479 18:02:54.524962 ADC[6]: Raw value=74502 ID=0
9480 18:02:54.525036 ADC[5]: Raw value=212441 ID=1
9481 18:02:54.528352 SKU Code: 0x1
9482 18:02:54.531222 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 4b17
9483 18:02:54.534526 coreboot table: 964 bytes.
9484 18:02:54.537868 IMD ROOT 0. 0xfffff000 0x00001000
9485 18:02:54.541158 IMD SMALL 1. 0xffffe000 0x00001000
9486 18:02:54.544661 RO MCACHE 2. 0xffffc000 0x00001104
9487 18:02:54.547775 CONSOLE 3. 0xfff7c000 0x00080000
9488 18:02:54.551167 FMAP 4. 0xfff7b000 0x00000452
9489 18:02:54.554305 TIME STAMP 5. 0xfff7a000 0x00000910
9490 18:02:54.557804 VBOOT WORK 6. 0xfff66000 0x00014000
9491 18:02:54.561141 RAMOOPS 7. 0xffe66000 0x00100000
9492 18:02:54.564506 COREBOOT 8. 0xffe64000 0x00002000
9493 18:02:54.567652 IMD small region:
9494 18:02:54.570864 IMD ROOT 0. 0xffffec00 0x00000400
9495 18:02:54.574474 VPD 1. 0xffffeb80 0x0000006c
9496 18:02:54.577494 MMC STATUS 2. 0xffffeb60 0x00000004
9497 18:02:54.580764 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9498 18:02:54.587348 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9499 18:02:54.628579 read SPI 0x3990ec 0x4f1b0: 34846 us, 9298 KB/s, 74.384 Mbps
9500 18:02:54.631778 Checking segment from ROM address 0x40100000
9501 18:02:54.635203 Checking segment from ROM address 0x4010001c
9502 18:02:54.642027 Loading segment from ROM address 0x40100000
9503 18:02:54.642142 code (compression=0)
9504 18:02:54.652170 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9505 18:02:54.658544 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9506 18:02:54.658719 it's not compressed!
9507 18:02:54.665063 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9508 18:02:54.671680 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9509 18:02:54.689014 Loading segment from ROM address 0x4010001c
9510 18:02:54.689181 Entry Point 0x80000000
9511 18:02:54.692318 Loaded segments
9512 18:02:54.695684 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9513 18:02:54.702433 Jumping to boot code at 0x80000000(0xffe64000)
9514 18:02:54.709020 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9515 18:02:54.715557 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9516 18:02:54.723348 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9517 18:02:54.726855 Checking segment from ROM address 0x40100000
9518 18:02:54.729908 Checking segment from ROM address 0x4010001c
9519 18:02:54.736757 Loading segment from ROM address 0x40100000
9520 18:02:54.736862 code (compression=1)
9521 18:02:54.743519 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9522 18:02:54.753735 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9523 18:02:54.753906 using LZMA
9524 18:02:54.762242 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9525 18:02:54.768223 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9526 18:02:54.771928 Loading segment from ROM address 0x4010001c
9527 18:02:54.772037 Entry Point 0x54601000
9528 18:02:54.775163 Loaded segments
9529 18:02:54.778225 NOTICE: MT8192 bl31_setup
9530 18:02:54.785238 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9531 18:02:54.788641 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9532 18:02:54.791872 WARNING: region 0:
9533 18:02:54.795171 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9534 18:02:54.795248 WARNING: region 1:
9535 18:02:54.802026 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9536 18:02:54.805318 WARNING: region 2:
9537 18:02:54.808732 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9538 18:02:54.812040 WARNING: region 3:
9539 18:02:54.815052 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9540 18:02:54.818219 WARNING: region 4:
9541 18:02:54.825309 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9542 18:02:54.825391 WARNING: region 5:
9543 18:02:54.828210 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9544 18:02:54.831616 WARNING: region 6:
9545 18:02:54.834899 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9546 18:02:54.838149 WARNING: region 7:
9547 18:02:54.841460 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9548 18:02:54.848228 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9549 18:02:54.851407 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9550 18:02:54.854702 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9551 18:02:54.861602 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9552 18:02:54.864733 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9553 18:02:54.871499 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9554 18:02:54.874425 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9555 18:02:54.878065 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9556 18:02:54.884906 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9557 18:02:54.888231 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9558 18:02:54.891404 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9559 18:02:54.897822 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9560 18:02:54.901275 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9561 18:02:54.907875 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9562 18:02:54.911365 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9563 18:02:54.914772 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9564 18:02:54.921563 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9565 18:02:54.924429 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9566 18:02:54.927554 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9567 18:02:54.934419 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9568 18:02:54.937737 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9569 18:02:54.944661 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9570 18:02:54.947859 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9571 18:02:54.951308 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9572 18:02:54.957546 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9573 18:02:54.960811 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9574 18:02:54.967342 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9575 18:02:54.971261 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9576 18:02:54.977489 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9577 18:02:54.980761 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9578 18:02:54.984157 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9579 18:02:54.990738 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9580 18:02:54.994259 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9581 18:02:54.997512 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9582 18:02:55.000848 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9583 18:02:55.007490 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9584 18:02:55.010754 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9585 18:02:55.014145 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9586 18:02:55.017447 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9587 18:02:55.024065 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9588 18:02:55.027377 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9589 18:02:55.030814 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9590 18:02:55.034208 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9591 18:02:55.040527 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9592 18:02:55.043964 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9593 18:02:55.047292 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9594 18:02:55.050528 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9595 18:02:55.057333 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9596 18:02:55.060831 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9597 18:02:55.067029 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9598 18:02:55.070231 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9599 18:02:55.073839 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9600 18:02:55.080640 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9601 18:02:55.084105 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9602 18:02:55.090218 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9603 18:02:55.094108 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9604 18:02:55.100424 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9605 18:02:55.103667 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9606 18:02:55.106891 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9607 18:02:55.113817 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9608 18:02:55.117169 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9609 18:02:55.123751 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9610 18:02:55.127013 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9611 18:02:55.133535 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9612 18:02:55.136906 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9613 18:02:55.143537 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9614 18:02:55.147213 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9615 18:02:55.149976 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9616 18:02:55.156967 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9617 18:02:55.160242 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9618 18:02:55.167055 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9619 18:02:55.169787 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9620 18:02:55.176517 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9621 18:02:55.179993 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9622 18:02:55.183249 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9623 18:02:55.190045 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9624 18:02:55.193389 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9625 18:02:55.199807 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9626 18:02:55.202962 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9627 18:02:55.209869 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9628 18:02:55.212874 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9629 18:02:55.219917 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9630 18:02:55.223563 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9631 18:02:55.230151 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9632 18:02:55.233271 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9633 18:02:55.236379 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9634 18:02:55.242994 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9635 18:02:55.246855 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9636 18:02:55.252965 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9637 18:02:55.256111 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9638 18:02:55.262868 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9639 18:02:55.266093 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9640 18:02:55.269506 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9641 18:02:55.276157 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9642 18:02:55.279398 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9643 18:02:55.286270 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9644 18:02:55.289492 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9645 18:02:55.292847 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9646 18:02:55.299265 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9647 18:02:55.302541 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9648 18:02:55.306056 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9649 18:02:55.312603 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9650 18:02:55.315927 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9651 18:02:55.319133 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9652 18:02:55.325840 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9653 18:02:55.329230 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9654 18:02:55.332461 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9655 18:02:55.339049 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9656 18:02:55.342279 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9657 18:02:55.349313 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9658 18:02:55.352381 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9659 18:02:55.355669 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9660 18:02:55.362271 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9661 18:02:55.366124 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9662 18:02:55.372434 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9663 18:02:55.375801 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9664 18:02:55.379129 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9665 18:02:55.385626 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9666 18:02:55.388835 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9667 18:02:55.392122 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9668 18:02:55.395468 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9669 18:02:55.402087 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9670 18:02:55.405813 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9671 18:02:55.409083 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9672 18:02:55.415788 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9673 18:02:55.418959 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9674 18:02:55.422318 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9675 18:02:55.428934 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9676 18:02:55.432357 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9677 18:02:55.438922 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9678 18:02:55.442226 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9679 18:02:55.445468 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9680 18:02:55.451909 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9681 18:02:55.455347 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9682 18:02:55.461712 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9683 18:02:55.465136 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9684 18:02:55.468519 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9685 18:02:55.475333 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9686 18:02:55.478641 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9687 18:02:55.484837 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9688 18:02:55.488135 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9689 18:02:55.491312 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9690 18:02:55.498121 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9691 18:02:55.501522 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9692 18:02:55.504757 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9693 18:02:55.511769 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9694 18:02:55.515062 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9695 18:02:55.521578 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9696 18:02:55.525268 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9697 18:02:55.531778 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9698 18:02:55.535012 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9699 18:02:55.538311 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9700 18:02:55.544832 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9701 18:02:55.548152 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9702 18:02:55.554794 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9703 18:02:55.557932 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9704 18:02:55.561461 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9705 18:02:55.567804 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9706 18:02:55.571774 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9707 18:02:55.574449 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9708 18:02:55.581503 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9709 18:02:55.584810 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9710 18:02:55.591356 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9711 18:02:55.594501 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9712 18:02:55.598101 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9713 18:02:55.604659 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9714 18:02:55.607836 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9715 18:02:55.614359 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9716 18:02:55.617524 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9717 18:02:55.621347 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9718 18:02:55.627733 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9719 18:02:55.631305 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9720 18:02:55.637875 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9721 18:02:55.640988 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9722 18:02:55.644314 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9723 18:02:55.651286 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9724 18:02:55.654552 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9725 18:02:55.660803 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9726 18:02:55.664505 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9727 18:02:55.667722 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9728 18:02:55.674124 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9729 18:02:55.677355 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9730 18:02:55.681205 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9731 18:02:55.687834 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9732 18:02:55.690623 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9733 18:02:55.697528 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9734 18:02:55.700662 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9735 18:02:55.704495 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9736 18:02:55.711124 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9737 18:02:55.714283 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9738 18:02:55.721043 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9739 18:02:55.724149 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9740 18:02:55.727430 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9741 18:02:55.734072 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9742 18:02:55.737331 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9743 18:02:55.744086 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9744 18:02:55.747310 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9745 18:02:55.753983 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9746 18:02:55.757306 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9747 18:02:55.760682 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9748 18:02:55.767056 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9749 18:02:55.770709 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9750 18:02:55.777536 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9751 18:02:55.780863 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9752 18:02:55.783600 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9753 18:02:55.790355 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9754 18:02:55.793772 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9755 18:02:55.800115 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9756 18:02:55.803626 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9757 18:02:55.810057 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9758 18:02:55.813492 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9759 18:02:55.816816 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9760 18:02:55.823409 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9761 18:02:55.826612 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9762 18:02:55.833498 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9763 18:02:55.836747 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9764 18:02:55.840113 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9765 18:02:55.846700 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9766 18:02:55.850189 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9767 18:02:55.856766 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9768 18:02:55.860139 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9769 18:02:55.863370 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9770 18:02:55.870102 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9771 18:02:55.873301 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9772 18:02:55.880040 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9773 18:02:55.883331 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9774 18:02:55.890107 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9775 18:02:55.893611 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9776 18:02:55.896721 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9777 18:02:55.903452 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9778 18:02:55.906908 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9779 18:02:55.910043 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9780 18:02:55.913452 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9781 18:02:55.916652 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9782 18:02:55.923363 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9783 18:02:55.926765 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9784 18:02:55.932866 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9785 18:02:55.936457 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9786 18:02:55.939549 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9787 18:02:55.946554 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9788 18:02:55.949448 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9789 18:02:55.956741 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9790 18:02:55.959816 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9791 18:02:55.963603 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9792 18:02:55.969988 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9793 18:02:55.973601 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9794 18:02:55.976741 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9795 18:02:55.983650 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9796 18:02:55.986996 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9797 18:02:55.990086 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9798 18:02:55.996651 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9799 18:02:55.999901 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9800 18:02:56.006811 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9801 18:02:56.010146 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9802 18:02:56.013131 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9803 18:02:56.019735 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9804 18:02:56.022971 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9805 18:02:56.026327 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9806 18:02:56.033393 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9807 18:02:56.036607 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9808 18:02:56.039725 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9809 18:02:56.046645 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9810 18:02:56.049977 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9811 18:02:56.052789 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9812 18:02:56.059545 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9813 18:02:56.062814 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9814 18:02:56.069429 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9815 18:02:56.073132 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9816 18:02:56.075959 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9817 18:02:56.079444 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9818 18:02:56.086157 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9819 18:02:56.089595 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9820 18:02:56.092426 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9821 18:02:56.096261 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9822 18:02:56.102374 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9823 18:02:56.106165 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9824 18:02:56.109226 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9825 18:02:56.112431 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9826 18:02:56.119189 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9827 18:02:56.122344 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9828 18:02:56.125579 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9829 18:02:56.128975 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9830 18:02:56.135457 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9831 18:02:56.139210 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9832 18:02:56.145478 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9833 18:02:56.149196 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9834 18:02:56.155560 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9835 18:02:56.159029 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9836 18:02:56.161822 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9837 18:02:56.168526 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9838 18:02:56.171832 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9839 18:02:56.178679 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9840 18:02:56.182105 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9841 18:02:56.188123 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9842 18:02:56.191492 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9843 18:02:57.348480 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9844 18:02:57.349876 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9845 18:02:57.350458 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9846 18:02:57.351029 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9847 18:02:57.351681 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9848 18:02:57.352176 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9849 18:02:57.352544 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9850 18:02:57.352939 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9851 18:02:57.353267 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9852 18:02:57.353588 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9853 18:02:57.353904 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9854 18:02:57.354048 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9855 18:02:57.354135 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9856 18:02:57.354223 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9857 18:02:57.354279 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9858 18:02:57.354365 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9859 18:02:57.354434 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9860 18:02:57.354506 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9861 18:02:57.354592 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9862 18:02:57.354678 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9863 18:02:57.354764 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9864 18:02:57.354819 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9865 18:02:57.354873 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9866 18:02:57.354928 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9867 18:02:57.354983 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9868 18:02:57.355038 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9869 18:02:57.355093 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9870 18:02:57.355148 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9871 18:02:57.355203 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9872 18:02:57.355257 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9873 18:02:57.355312 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9874 18:02:57.355367 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9875 18:02:57.355422 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9876 18:02:57.355477 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9877 18:02:57.355531 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9878 18:02:57.355586 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9879 18:02:57.355641 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9880 18:02:57.355696 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9881 18:02:57.355750 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9882 18:02:57.355804 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9883 18:02:57.355859 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9884 18:02:57.355913 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9885 18:02:57.355968 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9886 18:02:57.356022 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9887 18:02:57.356077 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9888 18:02:57.356131 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9889 18:02:57.356186 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9890 18:02:57.356240 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9891 18:02:57.356295 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9892 18:02:57.356349 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9893 18:02:57.356404 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9894 18:02:57.356458 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9895 18:02:57.356512 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9896 18:02:57.356581 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9897 18:02:57.356699 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9898 18:02:57.356832 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9899 18:02:57.356908 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9900 18:02:57.357002 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9901 18:02:57.357088 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9902 18:02:57.357143 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9903 18:02:57.357230 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9904 18:02:57.357315 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9905 18:02:57.357370 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9906 18:02:57.357425 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9907 18:02:57.357480 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9908 18:02:57.357535 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9909 18:02:57.357589 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9910 18:02:57.357644 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9911 18:02:57.357699 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9912 18:02:57.357754 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9913 18:02:57.357809 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9914 18:02:57.357863 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9915 18:02:57.357918 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9916 18:02:57.357973 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9917 18:02:57.358028 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9918 18:02:57.358082 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9919 18:02:57.358342 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9920 18:02:57.358411 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9921 18:02:57.358470 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9922 18:02:57.358526 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9923 18:02:57.358582 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9924 18:02:57.358637 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9925 18:02:57.358693 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9926 18:02:57.358748 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9927 18:02:57.358802 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9928 18:02:57.358857 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9929 18:02:57.358912 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9930 18:02:57.358967 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9931 18:02:57.359021 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9932 18:02:57.359076 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9933 18:02:57.359131 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9934 18:02:57.359185 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9935 18:02:57.359240 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9936 18:02:57.359294 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9937 18:02:57.359348 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9938 18:02:57.359403 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9939 18:02:57.359457 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9940 18:02:57.359512 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9941 18:02:57.359566 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9942 18:02:57.359621 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9943 18:02:57.359675 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9944 18:02:57.359730 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9945 18:02:57.359789 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9946 18:02:57.359845 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9947 18:02:57.359900 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9948 18:02:57.359955 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9949 18:02:57.360010 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9950 18:02:57.360065 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9951 18:02:57.360120 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9952 18:02:57.360174 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9953 18:02:57.360229 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9954 18:02:57.360284 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9955 18:02:57.360340 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9956 18:02:57.360394 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9957 18:02:57.360449 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9958 18:02:57.360504 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9959 18:02:57.360568 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9960 18:02:57.360625 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9961 18:02:57.360680 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9962 18:02:57.360734 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9963 18:02:57.360789 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9964 18:02:57.360844 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9965 18:02:57.360899 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9966 18:02:57.360953 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9967 18:02:57.361008 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9968 18:02:57.361062 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9969 18:02:57.361117 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9970 18:02:57.361171 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9971 18:02:57.361226 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9972 18:02:57.361281 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9973 18:02:57.361335 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9974 18:02:57.361390 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9975 18:02:57.361445 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9976 18:02:57.361500 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9977 18:02:57.361554 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9978 18:02:57.361608 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9979 18:02:57.361663 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9980 18:02:57.361720 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9981 18:02:57.361778 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9982 18:02:57.361865 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9983 18:02:57.361923 INFO: [APUAPC] vio 0
9984 18:02:57.361978 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9985 18:02:57.362033 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9986 18:02:57.362088 INFO: [APUAPC] D0_APC_0: 0x400510
9987 18:02:57.362142 INFO: [APUAPC] D0_APC_1: 0x0
9988 18:02:57.362197 INFO: [APUAPC] D0_APC_2: 0x1540
9989 18:02:57.362251 INFO: [APUAPC] D0_APC_3: 0x0
9990 18:02:57.362306 INFO: [APUAPC] D1_APC_0: 0xffffffff
9991 18:02:57.362361 INFO: [APUAPC] D1_APC_1: 0xffffffff
9992 18:02:57.362415 INFO: [APUAPC] D1_APC_2: 0x3fffff
9993 18:02:57.362469 INFO: [APUAPC] D1_APC_3: 0x0
9994 18:02:57.362523 INFO: [APUAPC] D2_APC_0: 0xffffffff
9995 18:02:57.362578 INFO: [APUAPC] D2_APC_1: 0xffffffff
9996 18:02:57.362827 INFO: [APUAPC] D2_APC_2: 0x3fffff
9997 18:02:57.362889 INFO: [APUAPC] D2_APC_3: 0x0
9998 18:02:57.362946 INFO: [APUAPC] D3_APC_0: 0xffffffff
9999 18:02:57.363000 INFO: [APUAPC] D3_APC_1: 0xffffffff
10000 18:02:57.363054 INFO: [APUAPC] D3_APC_2: 0x3fffff
10001 18:02:57.363108 INFO: [APUAPC] D3_APC_3: 0x0
10002 18:02:57.363162 INFO: [APUAPC] D4_APC_0: 0xffffffff
10003 18:02:57.363216 INFO: [APUAPC] D4_APC_1: 0xffffffff
10004 18:02:57.363270 INFO: [APUAPC] D4_APC_2: 0x3fffff
10005 18:02:57.363323 INFO: [APUAPC] D4_APC_3: 0x0
10006 18:02:57.363377 INFO: [APUAPC] D5_APC_0: 0xffffffff
10007 18:02:57.363431 INFO: [APUAPC] D5_APC_1: 0xffffffff
10008 18:02:57.363486 INFO: [APUAPC] D5_APC_2: 0x3fffff
10009 18:02:57.363540 INFO: [APUAPC] D5_APC_3: 0x0
10010 18:02:57.363595 INFO: [APUAPC] D6_APC_0: 0xffffffff
10011 18:02:57.363650 INFO: [APUAPC] D6_APC_1: 0xffffffff
10012 18:02:57.363703 INFO: [APUAPC] D6_APC_2: 0x3fffff
10013 18:02:57.363758 INFO: [APUAPC] D6_APC_3: 0x0
10014 18:02:57.363821 INFO: [APUAPC] D7_APC_0: 0xffffffff
10015 18:02:57.363877 INFO: [APUAPC] D7_APC_1: 0xffffffff
10016 18:02:57.363931 INFO: [APUAPC] D7_APC_2: 0x3fffff
10017 18:02:57.363986 INFO: [APUAPC] D7_APC_3: 0x0
10018 18:02:57.364040 INFO: [APUAPC] D8_APC_0: 0xffffffff
10019 18:02:57.364095 INFO: [APUAPC] D8_APC_1: 0xffffffff
10020 18:02:57.364149 INFO: [APUAPC] D8_APC_2: 0x3fffff
10021 18:02:57.364203 INFO: [APUAPC] D8_APC_3: 0x0
10022 18:02:57.364258 INFO: [APUAPC] D9_APC_0: 0xffffffff
10023 18:02:57.364312 INFO: [APUAPC] D9_APC_1: 0xffffffff
10024 18:02:57.364367 INFO: [APUAPC] D9_APC_2: 0x3fffff
10025 18:02:57.364421 INFO: [APUAPC] D9_APC_3: 0x0
10026 18:02:57.364476 INFO: [APUAPC] D10_APC_0: 0xffffffff
10027 18:02:57.364530 INFO: [APUAPC] D10_APC_1: 0xffffffff
10028 18:02:57.364597 INFO: [APUAPC] D10_APC_2: 0x3fffff
10029 18:02:57.364652 INFO: [APUAPC] D10_APC_3: 0x0
10030 18:02:57.364707 INFO: [APUAPC] D11_APC_0: 0xffffffff
10031 18:02:57.364761 INFO: [APUAPC] D11_APC_1: 0xffffffff
10032 18:02:57.364816 INFO: [APUAPC] D11_APC_2: 0x3fffff
10033 18:02:57.364870 INFO: [APUAPC] D11_APC_3: 0x0
10034 18:02:57.364924 INFO: [APUAPC] D12_APC_0: 0xffffffff
10035 18:02:57.364978 INFO: [APUAPC] D12_APC_1: 0xffffffff
10036 18:02:57.365033 INFO: [APUAPC] D12_APC_2: 0x3fffff
10037 18:02:57.365087 INFO: [APUAPC] D12_APC_3: 0x0
10038 18:02:57.365141 INFO: [APUAPC] D13_APC_0: 0xffffffff
10039 18:02:57.365195 INFO: [APUAPC] D13_APC_1: 0xffffffff
10040 18:02:57.365250 INFO: [APUAPC] D13_APC_2: 0x3fffff
10041 18:02:57.365304 INFO: [APUAPC] D13_APC_3: 0x0
10042 18:02:57.365358 INFO: [APUAPC] D14_APC_0: 0xffffffff
10043 18:02:57.365412 INFO: [APUAPC] D14_APC_1: 0xffffffff
10044 18:02:57.365467 INFO: [APUAPC] D14_APC_2: 0x3fffff
10045 18:02:57.365553 INFO: [APUAPC] D14_APC_3: 0x0
10046 18:02:57.365611 INFO: [APUAPC] D15_APC_0: 0xffffffff
10047 18:02:57.365667 INFO: [APUAPC] D15_APC_1: 0xffffffff
10048 18:02:57.365721 INFO: [APUAPC] D15_APC_2: 0x3fffff
10049 18:02:57.365776 INFO: [APUAPC] D15_APC_3: 0x0
10050 18:02:57.365831 INFO: [APUAPC] APC_CON: 0x4
10051 18:02:57.365886 INFO: [NOCDAPC] D0_APC_0: 0x0
10052 18:02:57.365940 INFO: [NOCDAPC] D0_APC_1: 0x0
10053 18:02:57.365995 INFO: [NOCDAPC] D1_APC_0: 0x0
10054 18:02:57.366053 INFO: [NOCDAPC] D1_APC_1: 0xfff
10055 18:02:57.366108 INFO: [NOCDAPC] D2_APC_0: 0x0
10056 18:02:57.366161 INFO: [NOCDAPC] D2_APC_1: 0xfff
10057 18:02:57.366215 INFO: [NOCDAPC] D3_APC_0: 0x0
10058 18:02:57.366268 INFO: [NOCDAPC] D3_APC_1: 0xfff
10059 18:02:57.366322 INFO: [NOCDAPC] D4_APC_0: 0x0
10060 18:02:57.366375 INFO: [NOCDAPC] D4_APC_1: 0xfff
10061 18:02:57.366429 INFO: [NOCDAPC] D5_APC_0: 0x0
10062 18:02:57.366482 INFO: [NOCDAPC] D5_APC_1: 0xfff
10063 18:02:57.366537 INFO: [NOCDAPC] D6_APC_0: 0x0
10064 18:02:57.366590 INFO: [NOCDAPC] D6_APC_1: 0xfff
10065 18:02:57.366644 INFO: [NOCDAPC] D7_APC_0: 0x0
10066 18:02:57.366697 INFO: [NOCDAPC] D7_APC_1: 0xfff
10067 18:02:57.366752 INFO: [NOCDAPC] D8_APC_0: 0x0
10068 18:02:57.366806 INFO: [NOCDAPC] D8_APC_1: 0xfff
10069 18:02:57.366860 INFO: [NOCDAPC] D9_APC_0: 0x0
10070 18:02:57.366914 INFO: [NOCDAPC] D9_APC_1: 0xfff
10071 18:02:57.366969 INFO: [NOCDAPC] D10_APC_0: 0x0
10072 18:02:57.367023 INFO: [NOCDAPC] D10_APC_1: 0xfff
10073 18:02:57.367077 INFO: [NOCDAPC] D11_APC_0: 0x0
10074 18:02:57.367132 INFO: [NOCDAPC] D11_APC_1: 0xfff
10075 18:02:57.367187 INFO: [NOCDAPC] D12_APC_0: 0x0
10076 18:02:57.367241 INFO: [NOCDAPC] D12_APC_1: 0xfff
10077 18:02:57.367295 INFO: [NOCDAPC] D13_APC_0: 0x0
10078 18:02:57.367350 INFO: [NOCDAPC] D13_APC_1: 0xfff
10079 18:02:57.367404 INFO: [NOCDAPC] D14_APC_0: 0x0
10080 18:02:57.367458 INFO: [NOCDAPC] D14_APC_1: 0xfff
10081 18:02:57.367513 INFO: [NOCDAPC] D15_APC_0: 0x0
10082 18:02:57.367567 INFO: [NOCDAPC] D15_APC_1: 0xfff
10083 18:02:57.367621 INFO: [NOCDAPC] APC_CON: 0x4
10084 18:02:57.367675 INFO: [APUAPC] set_apusys_apc done
10085 18:02:57.367730 INFO: [DEVAPC] devapc_init done
10086 18:02:57.367784 INFO: GICv3 without legacy support detected.
10087 18:02:57.367839 INFO: ARM GICv3 driver initialized in EL3
10088 18:02:57.367894 INFO: Maximum SPI INTID supported: 639
10089 18:02:57.367948 INFO: BL31: Initializing runtime services
10090 18:02:57.368003 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10091 18:02:57.368058 INFO: SPM: enable CPC mode
10092 18:02:57.368113 INFO: mcdi ready for mcusys-off-idle and system suspend
10093 18:02:57.368167 INFO: BL31: Preparing for EL3 exit to normal world
10094 18:02:57.368225 INFO: Entry point address = 0x80000000
10095 18:02:57.368280 INFO: SPSR = 0x8
10096 18:02:57.368334
10097 18:02:57.368389
10098 18:02:57.368443
10099 18:02:57.368497 Starting depthcharge on Spherion...
10100 18:02:57.368559
10101 18:02:57.368614 Wipe memory regions:
10102 18:02:57.368669
10103 18:02:57.368723 [0x00000040000000, 0x00000054600000)
10104 18:02:57.368778
10105 18:02:57.368832 [0x00000054660000, 0x00000080000000)
10106 18:02:57.369441 end: 2.2.3 depthcharge-start (duration 00:00:19) [common]
10107 18:02:57.369545 start: 2.2.4 bootloader-commands (timeout 00:04:27) [common]
10108 18:02:57.369631 Setting prompt string to ['asurada:']
10109 18:02:57.369717 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:27)
10110 18:02:57.623191
10111 18:02:57.623758 [0x000000821a7280, 0x000000ffe64000)
10112 18:02:59.090366
10113 18:02:59.090584 [0x00000100000000, 0x00000240000000)
10114 18:03:00.257438
10115 18:03:00.260685 Initializing XHCI USB controller at 0x11200000.
10116 18:03:01.299203
10117 18:03:01.302274 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10118 18:03:01.302372
10119 18:03:01.302438
10120 18:03:01.302726 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10122 18:03:01.403060 asurada: tftpboot 192.168.201.1 14291372/tftp-deploy-hgwt2mnh/kernel/image.itb 14291372/tftp-deploy-hgwt2mnh/kernel/cmdline
10123 18:03:01.403200 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10124 18:03:01.403282 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:23)
10125 18:03:01.407267 tftpboot 192.168.201.1 14291372/tftp-deploy-hgwt2mnh/kernel/image.itp-deploy-hgwt2mnh/kernel/cmdline
10126 18:03:01.407353
10127 18:03:01.407418 Waiting for link
10128 18:03:01.565307
10129 18:03:01.565456 R8152: Initializing
10130 18:03:01.565525
10131 18:03:01.568532 Version 9 (ocp_data = 6010)
10132 18:03:01.568633
10133 18:03:01.572187 R8152: Done initializing
10134 18:03:01.572271
10135 18:03:01.572336 Adding net device
10136 18:03:03.520696
10137 18:03:03.520829 done.
10138 18:03:03.520900
10139 18:03:03.520961 MAC: 00:e0:4c:72:2d:d6
10140 18:03:03.521019
10141 18:03:03.523920 Sending DHCP discover... done.
10142 18:03:03.524004
10143 18:03:03.527289 Waiting for reply... done.
10144 18:03:03.527372
10145 18:03:03.530461 Sending DHCP request... done.
10146 18:03:03.530554
10147 18:03:03.534442 Waiting for reply... done.
10148 18:03:03.534554
10149 18:03:03.534648 My ip is 192.168.201.21
10150 18:03:03.534738
10151 18:03:03.537795 The DHCP server ip is 192.168.201.1
10152 18:03:03.537965
10153 18:03:03.544657 TFTP server IP predefined by user: 192.168.201.1
10154 18:03:03.544743
10155 18:03:03.551203 Bootfile predefined by user: 14291372/tftp-deploy-hgwt2mnh/kernel/image.itb
10156 18:03:03.551319
10157 18:03:03.551417 Sending tftp read request... done.
10158 18:03:03.554611
10159 18:03:03.554693 Waiting for the transfer...
10160 18:03:03.554758
10161 18:03:03.803068 00000000 ################################################################
10162 18:03:03.803232
10163 18:03:04.046134 00080000 ################################################################
10164 18:03:04.046312
10165 18:03:04.288677 00100000 ################################################################
10166 18:03:04.288853
10167 18:03:04.531139 00180000 ################################################################
10168 18:03:04.531318
10169 18:03:04.776501 00200000 ################################################################
10170 18:03:04.776660
10171 18:03:05.021218 00280000 ################################################################
10172 18:03:05.021358
10173 18:03:05.267972 00300000 ################################################################
10174 18:03:05.268173
10175 18:03:05.527518 00380000 ################################################################
10176 18:03:05.527679
10177 18:03:05.777415 00400000 ################################################################
10178 18:03:05.777576
10179 18:03:06.022087 00480000 ################################################################
10180 18:03:06.022235
10181 18:03:06.269468 00500000 ################################################################
10182 18:03:06.269621
10183 18:03:06.526707 00580000 ################################################################
10184 18:03:06.526858
10185 18:03:06.784968 00600000 ################################################################
10186 18:03:06.785113
10187 18:03:07.042878 00680000 ################################################################
10188 18:03:07.043060
10189 18:03:07.298061 00700000 ################################################################
10190 18:03:07.298194
10191 18:03:07.550001 00780000 ################################################################
10192 18:03:07.550141
10193 18:03:07.809183 00800000 ################################################################
10194 18:03:07.809358
10195 18:03:08.058891 00880000 ################################################################
10196 18:03:08.059064
10197 18:03:08.312348 00900000 ################################################################
10198 18:03:08.312564
10199 18:03:08.559477 00980000 ################################################################
10200 18:03:08.559657
10201 18:03:08.810481 00a00000 ################################################################
10202 18:03:08.810626
10203 18:03:09.059348 00a80000 ################################################################
10204 18:03:09.059482
10205 18:03:09.325301 00b00000 ################################################################
10206 18:03:09.325470
10207 18:03:09.575324 00b80000 ################################################################
10208 18:03:09.575463
10209 18:03:09.829120 00c00000 ################################################################
10210 18:03:09.829279
10211 18:03:10.078717 00c80000 ################################################################
10212 18:03:10.078881
10213 18:03:10.331940 00d00000 ################################################################
10214 18:03:10.332112
10215 18:03:10.586993 00d80000 ################################################################
10216 18:03:10.587138
10217 18:03:10.841931 00e00000 ################################################################
10218 18:03:10.842064
10219 18:03:11.139922 00e80000 ################################################################
10220 18:03:11.140086
10221 18:03:11.481983 00f00000 ################################################################
10222 18:03:11.482121
10223 18:03:11.808099 00f80000 ################################################################
10224 18:03:11.808240
10225 18:03:12.126823 01000000 ################################################################
10226 18:03:12.126958
10227 18:03:12.447390 01080000 ################################################################
10228 18:03:12.447532
10229 18:03:12.694499 01100000 ################################################################
10230 18:03:12.694640
10231 18:03:12.954956 01180000 ################################################################
10232 18:03:12.955093
10233 18:03:13.221907 01200000 ################################################################
10234 18:03:13.222040
10235 18:03:13.477976 01280000 ################################################################
10236 18:03:13.478135
10237 18:03:13.737673 01300000 ################################################################
10238 18:03:13.737837
10239 18:03:13.998602 01380000 ################################################################
10240 18:03:13.998738
10241 18:03:14.256659 01400000 ################################################################
10242 18:03:14.256792
10243 18:03:14.512966 01480000 ################################################################
10244 18:03:14.513108
10245 18:03:14.773088 01500000 ################################################################
10246 18:03:14.773230
10247 18:03:15.026087 01580000 ################################################################
10248 18:03:15.026270
10249 18:03:15.294971 01600000 ################################################################
10250 18:03:15.295145
10251 18:03:15.544311 01680000 ################################################################
10252 18:03:15.544447
10253 18:03:15.809947 01700000 ################################################################
10254 18:03:15.810089
10255 18:03:16.079510 01780000 ################################################################
10256 18:03:16.079661
10257 18:03:16.350551 01800000 ################################################################
10258 18:03:16.350685
10259 18:03:16.601188 01880000 ################################################################
10260 18:03:16.601354
10261 18:03:16.863079 01900000 ################################################################
10262 18:03:16.863218
10263 18:03:17.115602 01980000 ################################################################
10264 18:03:17.115742
10265 18:03:17.367650 01a00000 ################################################################
10266 18:03:17.367828
10267 18:03:17.615159 01a80000 ################################################################
10268 18:03:17.615336
10269 18:03:17.884486 01b00000 ################################################################
10270 18:03:17.884651
10271 18:03:18.150343 01b80000 ################################################################
10272 18:03:18.150479
10273 18:03:18.400973 01c00000 ################################################################
10274 18:03:18.401108
10275 18:03:18.654139 01c80000 ################################################################
10276 18:03:18.654274
10277 18:03:18.937131 01d00000 ################################################################
10278 18:03:18.937269
10279 18:03:19.209001 01d80000 ################################################################
10280 18:03:19.209159
10281 18:03:19.457958 01e00000 ######################################################## done.
10282 18:03:19.458096
10283 18:03:19.461234 The bootfile was 31914966 bytes long.
10284 18:03:19.461324
10285 18:03:19.464498 Sending tftp read request... done.
10286 18:03:19.464624
10287 18:03:19.464720 Waiting for the transfer...
10288 18:03:19.464821
10289 18:03:19.468268 00000000 # done.
10290 18:03:19.468387
10291 18:03:19.474617 Command line loaded dynamically from TFTP file: 14291372/tftp-deploy-hgwt2mnh/kernel/cmdline
10292 18:03:19.474711
10293 18:03:19.498227 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14291372/extract-nfsrootfs-6eprz0iq,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10294 18:03:19.498388
10295 18:03:19.498460 Loading FIT.
10296 18:03:19.498523
10297 18:03:19.501928 Image ramdisk-1 has 18740570 bytes.
10298 18:03:19.502013
10299 18:03:19.505218 Image fdt-1 has 47258 bytes.
10300 18:03:19.505301
10301 18:03:19.508338 Image kernel-1 has 13125101 bytes.
10302 18:03:19.508422
10303 18:03:19.518215 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10304 18:03:19.518301
10305 18:03:19.535252 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10306 18:03:19.535340
10307 18:03:19.538542 Choosing best match conf-1 for compat google,spherion-rev2.
10308 18:03:19.543985
10309 18:03:19.548868 Connected to device vid:did:rid of 1ae0:0028:00
10310 18:03:19.555770
10311 18:03:19.559172 tpm_get_response: command 0x17b, return code 0x0
10312 18:03:19.559256
10313 18:03:19.562547 ec_init: CrosEC protocol v3 supported (256, 248)
10314 18:03:19.567412
10315 18:03:19.571168 tpm_cleanup: add release locality here.
10316 18:03:19.571263
10317 18:03:19.571337 Shutting down all USB controllers.
10318 18:03:19.574244
10319 18:03:19.574337 Removing current net device
10320 18:03:19.574411
10321 18:03:19.580893 Exiting depthcharge with code 4 at timestamp: 51693776
10322 18:03:19.581005
10323 18:03:19.584027 LZMA decompressing kernel-1 to 0x821a6718
10324 18:03:19.584138
10325 18:03:19.587866 LZMA decompressing kernel-1 to 0x40000000
10326 18:03:21.205052
10327 18:03:21.205267 jumping to kernel
10328 18:03:21.206102 end: 2.2.4 bootloader-commands (duration 00:00:24) [common]
10329 18:03:21.206299 start: 2.2.5 auto-login-action (timeout 00:04:03) [common]
10330 18:03:21.206502 Setting prompt string to ['Linux version [0-9]']
10331 18:03:21.206641 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10332 18:03:21.206835 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10333 18:03:21.287697
10334 18:03:21.290745 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10335 18:03:21.294678 start: 2.2.5.1 login-action (timeout 00:04:03) [common]
10336 18:03:21.294778 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10337 18:03:21.294851 Setting prompt string to []
10338 18:03:21.294927 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10339 18:03:21.295003 Using line separator: #'\n'#
10340 18:03:21.295062 No login prompt set.
10341 18:03:21.295161 Parsing kernel messages
10342 18:03:21.295272 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10343 18:03:21.295380 [login-action] Waiting for messages, (timeout 00:04:03)
10344 18:03:21.295447 Waiting using forced prompt support (timeout 00:02:01)
10345 18:03:21.313880 [ 0.000000] Linux version 6.1.92-cip22 (KernelCI@build-j225340-arm64-gcc-10-defconfig-arm64-chromebook-x2t4v) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue Jun 11 17:44:14 UTC 2024
10346 18:03:21.317274 [ 0.000000] random: crng init done
10347 18:03:21.323857 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10348 18:03:21.327146 [ 0.000000] efi: UEFI not found.
10349 18:03:21.334193 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10350 18:03:21.340706 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10351 18:03:21.350876 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10352 18:03:21.360905 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10353 18:03:21.367241 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10354 18:03:21.370572 [ 0.000000] printk: bootconsole [mtk8250] enabled
10355 18:03:21.379359 [ 0.000000] NUMA: No NUMA configuration found
10356 18:03:21.386457 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10357 18:03:21.392663 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10358 18:03:21.392769 [ 0.000000] Zone ranges:
10359 18:03:21.399355 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10360 18:03:21.402764 [ 0.000000] DMA32 empty
10361 18:03:21.409390 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10362 18:03:21.412597 [ 0.000000] Movable zone start for each node
10363 18:03:21.416201 [ 0.000000] Early memory node ranges
10364 18:03:21.422981 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10365 18:03:21.429514 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10366 18:03:21.435812 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10367 18:03:21.442960 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10368 18:03:21.449523 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10369 18:03:21.456013 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10370 18:03:21.512068 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10371 18:03:21.518863 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10372 18:03:21.525486 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10373 18:03:21.528898 [ 0.000000] psci: probing for conduit method from DT.
10374 18:03:21.535374 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10375 18:03:21.538530 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10376 18:03:21.545251 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10377 18:03:21.548512 [ 0.000000] psci: SMC Calling Convention v1.2
10378 18:03:21.555593 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10379 18:03:21.558837 [ 0.000000] Detected VIPT I-cache on CPU0
10380 18:03:21.565334 [ 0.000000] CPU features: detected: GIC system register CPU interface
10381 18:03:21.571925 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10382 18:03:21.578520 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10383 18:03:21.585635 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10384 18:03:21.592202 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10385 18:03:21.598757 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10386 18:03:21.604910 [ 0.000000] alternatives: applying boot alternatives
10387 18:03:21.608084 [ 0.000000] Fallback order for Node 0: 0
10388 18:03:21.618188 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10389 18:03:21.618302 [ 0.000000] Policy zone: Normal
10390 18:03:21.644886 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14291372/extract-nfsrootfs-6eprz0iq,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10391 18:03:21.654739 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10392 18:03:21.665474 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10393 18:03:21.675856 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10394 18:03:21.682472 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10395 18:03:21.685826 <6>[ 0.000000] software IO TLB: area num 8.
10396 18:03:21.741992 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10397 18:03:21.891489 <6>[ 0.000000] Memory: 7945760K/8385536K available (18112K kernel code, 4120K rwdata, 22644K rodata, 8512K init, 616K bss, 407008K reserved, 32768K cma-reserved)
10398 18:03:21.898478 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10399 18:03:21.904953 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10400 18:03:21.908264 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10401 18:03:21.914741 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10402 18:03:21.921256 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10403 18:03:21.924786 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10404 18:03:21.934647 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10405 18:03:21.941244 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10406 18:03:21.944693 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10407 18:03:21.952887 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10408 18:03:21.956128 <6>[ 0.000000] GICv3: 608 SPIs implemented
10409 18:03:21.962702 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10410 18:03:21.965875 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10411 18:03:21.969123 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10412 18:03:21.979240 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10413 18:03:21.989523 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10414 18:03:22.002559 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10415 18:03:22.009167 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10416 18:03:22.018401 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10417 18:03:22.031690 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10418 18:03:22.038256 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10419 18:03:22.045096 <6>[ 0.009234] Console: colour dummy device 80x25
10420 18:03:22.055218 <6>[ 0.013954] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10421 18:03:22.058361 <6>[ 0.024461] pid_max: default: 32768 minimum: 301
10422 18:03:22.065007 <6>[ 0.029361] LSM: Security Framework initializing
10423 18:03:22.071812 <6>[ 0.034331] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10424 18:03:22.081999 <6>[ 0.042145] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10425 18:03:22.088463 <6>[ 0.051560] cblist_init_generic: Setting adjustable number of callback queues.
10426 18:03:22.095206 <6>[ 0.059049] cblist_init_generic: Setting shift to 3 and lim to 1.
10427 18:03:22.101384 <6>[ 0.065426] cblist_init_generic: Setting adjustable number of callback queues.
10428 18:03:22.108112 <6>[ 0.072853] cblist_init_generic: Setting shift to 3 and lim to 1.
10429 18:03:22.115240 <6>[ 0.079255] rcu: Hierarchical SRCU implementation.
10430 18:03:22.121648 <6>[ 0.084269] rcu: Max phase no-delay instances is 1000.
10431 18:03:22.125090 <6>[ 0.091302] EFI services will not be available.
10432 18:03:22.131634 <6>[ 0.096260] smp: Bringing up secondary CPUs ...
10433 18:03:22.139344 <6>[ 0.101311] Detected VIPT I-cache on CPU1
10434 18:03:22.145920 <6>[ 0.101384] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10435 18:03:22.152514 <6>[ 0.101414] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10436 18:03:22.155880 <6>[ 0.101753] Detected VIPT I-cache on CPU2
10437 18:03:22.162208 <6>[ 0.101809] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10438 18:03:22.168897 <6>[ 0.101827] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10439 18:03:22.175703 <6>[ 0.102086] Detected VIPT I-cache on CPU3
10440 18:03:22.182049 <6>[ 0.102134] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10441 18:03:22.189058 <6>[ 0.102148] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10442 18:03:22.192292 <6>[ 0.102450] CPU features: detected: Spectre-v4
10443 18:03:22.198950 <6>[ 0.102456] CPU features: detected: Spectre-BHB
10444 18:03:22.202357 <6>[ 0.102460] Detected PIPT I-cache on CPU4
10445 18:03:22.208854 <6>[ 0.102520] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10446 18:03:22.215615 <6>[ 0.102536] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10447 18:03:22.222065 <6>[ 0.102828] Detected PIPT I-cache on CPU5
10448 18:03:22.228622 <6>[ 0.102891] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10449 18:03:22.235610 <6>[ 0.102908] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10450 18:03:22.238752 <6>[ 0.103189] Detected PIPT I-cache on CPU6
10451 18:03:22.245612 <6>[ 0.103252] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10452 18:03:22.252225 <6>[ 0.103268] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10453 18:03:22.255394 <6>[ 0.103568] Detected PIPT I-cache on CPU7
10454 18:03:22.265645 <6>[ 0.103634] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10455 18:03:22.272323 <6>[ 0.103650] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10456 18:03:22.275828 <6>[ 0.103697] smp: Brought up 1 node, 8 CPUs
10457 18:03:22.278749 <6>[ 0.244852] SMP: Total of 8 processors activated.
10458 18:03:22.285288 <6>[ 0.249774] CPU features: detected: 32-bit EL0 Support
10459 18:03:22.295514 <6>[ 0.255137] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10460 18:03:22.301993 <6>[ 0.263937] CPU features: detected: Common not Private translations
10461 18:03:22.305436 <6>[ 0.270413] CPU features: detected: CRC32 instructions
10462 18:03:22.312307 <6>[ 0.275765] CPU features: detected: RCpc load-acquire (LDAPR)
10463 18:03:22.318943 <6>[ 0.281725] CPU features: detected: LSE atomic instructions
10464 18:03:22.322266 <6>[ 0.287507] CPU features: detected: Privileged Access Never
10465 18:03:22.328912 <6>[ 0.293322] CPU features: detected: RAS Extension Support
10466 18:03:22.335637 <6>[ 0.298931] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10467 18:03:22.342308 <6>[ 0.306152] CPU: All CPU(s) started at EL2
10468 18:03:22.346152 <6>[ 0.310469] alternatives: applying system-wide alternatives
10469 18:03:22.356777 <6>[ 0.321327] devtmpfs: initialized
10470 18:03:22.369769 <6>[ 0.330301] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10471 18:03:22.379335 <6>[ 0.340266] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10472 18:03:22.386137 <6>[ 0.348293] pinctrl core: initialized pinctrl subsystem
10473 18:03:22.389536 <6>[ 0.354983] DMI not present or invalid.
10474 18:03:22.396188 <6>[ 0.359396] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10475 18:03:22.406058 <6>[ 0.366184] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10476 18:03:22.412311 <6>[ 0.373775] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10477 18:03:22.422988 <6>[ 0.381999] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10478 18:03:22.426206 <6>[ 0.390242] audit: initializing netlink subsys (disabled)
10479 18:03:22.436043 <5>[ 0.395935] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10480 18:03:22.442551 <6>[ 0.396655] thermal_sys: Registered thermal governor 'step_wise'
10481 18:03:22.448936 <6>[ 0.403903] thermal_sys: Registered thermal governor 'power_allocator'
10482 18:03:22.452809 <6>[ 0.410161] cpuidle: using governor menu
10483 18:03:22.455826 <6>[ 0.421126] NET: Registered PF_QIPCRTR protocol family
10484 18:03:22.465783 <6>[ 0.426612] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10485 18:03:22.468930 <6>[ 0.433716] ASID allocator initialised with 32768 entries
10486 18:03:22.475922 <6>[ 0.440307] Serial: AMBA PL011 UART driver
10487 18:03:22.484874 <4>[ 0.449174] Trying to register duplicate clock ID: 134
10488 18:03:22.544506 <6>[ 0.512496] KASLR enabled
10489 18:03:22.559174 <6>[ 0.520185] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10490 18:03:22.565934 <6>[ 0.527196] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10491 18:03:22.572370 <6>[ 0.533684] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10492 18:03:22.579431 <6>[ 0.540691] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10493 18:03:22.585569 <6>[ 0.547180] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10494 18:03:22.592713 <6>[ 0.554186] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10495 18:03:22.599063 <6>[ 0.560672] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10496 18:03:22.605506 <6>[ 0.567678] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10497 18:03:22.608709 <6>[ 0.575158] ACPI: Interpreter disabled.
10498 18:03:22.616868 <6>[ 0.581590] iommu: Default domain type: Translated
10499 18:03:22.623742 <6>[ 0.586739] iommu: DMA domain TLB invalidation policy: strict mode
10500 18:03:22.627010 <5>[ 0.593400] SCSI subsystem initialized
10501 18:03:22.633760 <6>[ 0.597654] usbcore: registered new interface driver usbfs
10502 18:03:22.640291 <6>[ 0.603381] usbcore: registered new interface driver hub
10503 18:03:22.643566 <6>[ 0.608933] usbcore: registered new device driver usb
10504 18:03:22.650742 <6>[ 0.615056] pps_core: LinuxPPS API ver. 1 registered
10505 18:03:22.660406 <6>[ 0.620249] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10506 18:03:22.663684 <6>[ 0.629593] PTP clock support registered
10507 18:03:22.666903 <6>[ 0.633830] EDAC MC: Ver: 3.0.0
10508 18:03:22.674644 <6>[ 0.639025] FPGA manager framework
10509 18:03:22.681029 <6>[ 0.642703] Advanced Linux Sound Architecture Driver Initialized.
10510 18:03:22.684173 <6>[ 0.649486] vgaarb: loaded
10511 18:03:22.691172 <6>[ 0.652643] clocksource: Switched to clocksource arch_sys_counter
10512 18:03:22.694405 <5>[ 0.659091] VFS: Disk quotas dquot_6.6.0
10513 18:03:22.700764 <6>[ 0.663278] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10514 18:03:22.704136 <6>[ 0.670471] pnp: PnP ACPI: disabled
10515 18:03:22.712778 <6>[ 0.677223] NET: Registered PF_INET protocol family
10516 18:03:22.722451 <6>[ 0.682814] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10517 18:03:22.733803 <6>[ 0.695124] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10518 18:03:22.744036 <6>[ 0.703936] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10519 18:03:22.750382 <6>[ 0.711908] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10520 18:03:22.756981 <6>[ 0.720609] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10521 18:03:22.769262 <6>[ 0.730360] TCP: Hash tables configured (established 65536 bind 65536)
10522 18:03:22.775842 <6>[ 0.737230] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10523 18:03:22.782416 <6>[ 0.744428] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10524 18:03:22.789011 <6>[ 0.752137] NET: Registered PF_UNIX/PF_LOCAL protocol family
10525 18:03:22.795585 <6>[ 0.758289] RPC: Registered named UNIX socket transport module.
10526 18:03:22.798915 <6>[ 0.764442] RPC: Registered udp transport module.
10527 18:03:22.805520 <6>[ 0.769375] RPC: Registered tcp transport module.
10528 18:03:22.812159 <6>[ 0.774307] RPC: Registered tcp NFSv4.1 backchannel transport module.
10529 18:03:22.815275 <6>[ 0.780976] PCI: CLS 0 bytes, default 64
10530 18:03:22.818789 <6>[ 0.785340] Unpacking initramfs...
10531 18:03:22.828828 <6>[ 0.789061] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10532 18:03:22.835101 <6>[ 0.797692] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10533 18:03:22.841763 <6>[ 0.806499] kvm [1]: IPA Size Limit: 40 bits
10534 18:03:22.845052 <6>[ 0.811026] kvm [1]: GICv3: no GICV resource entry
10535 18:03:22.852020 <6>[ 0.816047] kvm [1]: disabling GICv2 emulation
10536 18:03:22.858436 <6>[ 0.820732] kvm [1]: GIC system register CPU interface enabled
10537 18:03:22.861985 <6>[ 0.826894] kvm [1]: vgic interrupt IRQ18
10538 18:03:22.868258 <6>[ 0.832705] kvm [1]: VHE mode initialized successfully
10539 18:03:22.875017 <5>[ 0.839090] Initialise system trusted keyrings
10540 18:03:22.881646 <6>[ 0.843887] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10541 18:03:22.889202 <6>[ 0.853837] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10542 18:03:22.895910 <5>[ 0.860214] NFS: Registering the id_resolver key type
10543 18:03:22.899179 <5>[ 0.865510] Key type id_resolver registered
10544 18:03:22.905562 <5>[ 0.869923] Key type id_legacy registered
10545 18:03:22.912019 <6>[ 0.874206] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10546 18:03:22.918999 <6>[ 0.881127] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10547 18:03:22.925363 <6>[ 0.888836] 9p: Installing v9fs 9p2000 file system support
10548 18:03:22.962304 <5>[ 0.926816] Key type asymmetric registered
10549 18:03:22.965482 <5>[ 0.931148] Asymmetric key parser 'x509' registered
10550 18:03:22.975258 <6>[ 0.936282] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10551 18:03:22.979011 <6>[ 0.943893] io scheduler mq-deadline registered
10552 18:03:22.981821 <6>[ 0.948653] io scheduler kyber registered
10553 18:03:23.000989 <6>[ 0.965702] EINJ: ACPI disabled.
10554 18:03:23.034514 <4>[ 0.992262] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10555 18:03:23.044271 <4>[ 1.002866] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10556 18:03:23.059229 <6>[ 1.023812] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10557 18:03:23.066861 <6>[ 1.031783] printk: console [ttyS0] disabled
10558 18:03:23.095285 <6>[ 1.056409] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10559 18:03:23.101553 <6>[ 1.065889] printk: console [ttyS0] enabled
10560 18:03:23.105091 <6>[ 1.065889] printk: console [ttyS0] enabled
10561 18:03:23.111534 <6>[ 1.074781] printk: bootconsole [mtk8250] disabled
10562 18:03:23.114776 <6>[ 1.074781] printk: bootconsole [mtk8250] disabled
10563 18:03:23.121534 <6>[ 1.085812] SuperH (H)SCI(F) driver initialized
10564 18:03:23.124872 <6>[ 1.091099] msm_serial: driver initialized
10565 18:03:23.138813 <6>[ 1.100007] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10566 18:03:23.148738 <6>[ 1.108554] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10567 18:03:23.155141 <6>[ 1.117097] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10568 18:03:23.164945 <6>[ 1.125724] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10569 18:03:23.175477 <6>[ 1.134430] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10570 18:03:23.181991 <6>[ 1.143146] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10571 18:03:23.191626 <6>[ 1.151686] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10572 18:03:23.198072 <6>[ 1.160479] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10573 18:03:23.208166 <6>[ 1.169021] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10574 18:03:23.220032 <6>[ 1.184705] loop: module loaded
10575 18:03:23.227043 <6>[ 1.190702] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10576 18:03:23.249714 <4>[ 1.213970] mtk-pmic-keys: Failed to locate of_node [id: -1]
10577 18:03:23.256239 <6>[ 1.220684] megasas: 07.719.03.00-rc1
10578 18:03:23.265970 <6>[ 1.230249] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10579 18:03:23.275921 <6>[ 1.240017] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10580 18:03:23.292405 <6>[ 1.256715] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10581 18:03:23.348858 <6>[ 1.306520] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10582 18:03:23.611043 <6>[ 1.575551] Freeing initrd memory: 18296K
10583 18:03:23.622885 <6>[ 1.587229] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10584 18:03:23.633762 <6>[ 1.598048] tun: Universal TUN/TAP device driver, 1.6
10585 18:03:23.637225 <6>[ 1.604092] thunder_xcv, ver 1.0
10586 18:03:23.640479 <6>[ 1.607599] thunder_bgx, ver 1.0
10587 18:03:23.643717 <6>[ 1.611095] nicpf, ver 1.0
10588 18:03:23.653955 <6>[ 1.615109] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10589 18:03:23.657741 <6>[ 1.622585] hns3: Copyright (c) 2017 Huawei Corporation.
10590 18:03:23.660868 <6>[ 1.628177] hclge is initializing
10591 18:03:23.667463 <6>[ 1.631751] e1000: Intel(R) PRO/1000 Network Driver
10592 18:03:23.674077 <6>[ 1.636879] e1000: Copyright (c) 1999-2006 Intel Corporation.
10593 18:03:23.677772 <6>[ 1.642893] e1000e: Intel(R) PRO/1000 Network Driver
10594 18:03:23.684261 <6>[ 1.648109] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10595 18:03:23.690966 <6>[ 1.654295] igb: Intel(R) Gigabit Ethernet Network Driver
10596 18:03:23.697347 <6>[ 1.659946] igb: Copyright (c) 2007-2014 Intel Corporation.
10597 18:03:23.703941 <6>[ 1.665783] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10598 18:03:23.710743 <6>[ 1.672300] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10599 18:03:23.713854 <6>[ 1.678762] sky2: driver version 1.30
10600 18:03:23.720413 <6>[ 1.683690] usbcore: registered new device driver r8152-cfgselector
10601 18:03:23.727483 <6>[ 1.690225] usbcore: registered new interface driver r8152
10602 18:03:23.730489 <6>[ 1.696048] VFIO - User Level meta-driver version: 0.3
10603 18:03:23.739782 <6>[ 1.704261] usbcore: registered new interface driver usb-storage
10604 18:03:23.746330 <6>[ 1.710707] usbcore: registered new device driver onboard-usb-hub
10605 18:03:23.755538 <6>[ 1.719849] mt6397-rtc mt6359-rtc: registered as rtc0
10606 18:03:23.765611 <6>[ 1.725317] mt6397-rtc mt6359-rtc: setting system clock to 2024-06-11T18:01:58 UTC (1718128918)
10607 18:03:23.768877 <6>[ 1.734879] i2c_dev: i2c /dev entries driver
10608 18:03:23.782537 <4>[ 1.746808] cpu cpu0: supply cpu not found, using dummy regulator
10609 18:03:23.789154 <4>[ 1.753239] cpu cpu1: supply cpu not found, using dummy regulator
10610 18:03:23.795990 <4>[ 1.759645] cpu cpu2: supply cpu not found, using dummy regulator
10611 18:03:23.802560 <4>[ 1.766044] cpu cpu3: supply cpu not found, using dummy regulator
10612 18:03:23.809025 <4>[ 1.772464] cpu cpu4: supply cpu not found, using dummy regulator
10613 18:03:23.815927 <4>[ 1.778863] cpu cpu5: supply cpu not found, using dummy regulator
10614 18:03:23.822691 <4>[ 1.785262] cpu cpu6: supply cpu not found, using dummy regulator
10615 18:03:23.829579 <4>[ 1.791656] cpu cpu7: supply cpu not found, using dummy regulator
10616 18:03:23.847748 <6>[ 1.812306] cpu cpu0: EM: created perf domain
10617 18:03:23.850956 <6>[ 1.817243] cpu cpu4: EM: created perf domain
10618 18:03:23.858137 <6>[ 1.822785] sdhci: Secure Digital Host Controller Interface driver
10619 18:03:23.865150 <6>[ 1.829215] sdhci: Copyright(c) Pierre Ossman
10620 18:03:23.871622 <6>[ 1.834164] Synopsys Designware Multimedia Card Interface Driver
10621 18:03:23.878656 <6>[ 1.840786] sdhci-pltfm: SDHCI platform and OF driver helper
10622 18:03:23.881910 <6>[ 1.840873] mmc0: CQHCI version 5.10
10623 18:03:23.888496 <6>[ 1.851308] ledtrig-cpu: registered to indicate activity on CPUs
10624 18:03:23.895337 <6>[ 1.858335] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10625 18:03:23.901723 <6>[ 1.865392] usbcore: registered new interface driver usbhid
10626 18:03:23.904938 <6>[ 1.871227] usbhid: USB HID core driver
10627 18:03:23.911659 <6>[ 1.875416] spi_master spi0: will run message pump with realtime priority
10628 18:03:23.958729 <6>[ 1.916429] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10629 18:03:23.978109 <6>[ 1.932603] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10630 18:03:23.981422 <6>[ 1.937961] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x16c14
10631 18:03:23.990662 <6>[ 1.955002] cros-ec-spi spi0.0: Chrome EC device registered
10632 18:03:23.997158 <6>[ 1.960995] mmc0: Command Queue Engine enabled
10633 18:03:24.003633 <6>[ 1.965726] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10634 18:03:24.006970 <6>[ 1.973265] mmcblk0: mmc0:0001 DA4128 116 GiB
10635 18:03:24.019374 <6>[ 1.984032] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10636 18:03:24.029487 <6>[ 1.988188] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10637 18:03:24.036156 <6>[ 1.991318] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10638 18:03:24.039522 <6>[ 2.000655] NET: Registered PF_PACKET protocol family
10639 18:03:24.046550 <6>[ 2.005199] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10640 18:03:24.049669 <6>[ 2.009890] 9pnet: Installing 9P2000 support
10641 18:03:24.056229 <6>[ 2.015706] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10642 18:03:24.062768 <5>[ 2.019598] Key type dns_resolver registered
10643 18:03:24.065944 <6>[ 2.031106] registered taskstats version 1
10644 18:03:24.072347 <5>[ 2.035498] Loading compiled-in X.509 certificates
10645 18:03:24.101017 <4>[ 2.058474] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10646 18:03:24.110426 <4>[ 2.069232] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10647 18:03:24.125035 <6>[ 2.089555] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10648 18:03:24.132192 <6>[ 2.096419] xhci-mtk 11200000.usb: xHCI Host Controller
10649 18:03:24.138572 <6>[ 2.101931] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10650 18:03:24.148674 <6>[ 2.109789] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10651 18:03:24.155420 <6>[ 2.119323] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10652 18:03:24.162353 <6>[ 2.125408] xhci-mtk 11200000.usb: xHCI Host Controller
10653 18:03:24.168938 <6>[ 2.130896] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10654 18:03:24.175601 <6>[ 2.138554] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10655 18:03:24.181831 <6>[ 2.146405] hub 1-0:1.0: USB hub found
10656 18:03:24.185425 <6>[ 2.150430] hub 1-0:1.0: 1 port detected
10657 18:03:24.195516 <6>[ 2.154725] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10658 18:03:24.198797 <6>[ 2.163469] hub 2-0:1.0: USB hub found
10659 18:03:24.202177 <6>[ 2.167496] hub 2-0:1.0: 1 port detected
10660 18:03:24.210250 <6>[ 2.174682] mtk-msdc 11f70000.mmc: Got CD GPIO
10661 18:03:24.229259 <6>[ 2.190383] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10662 18:03:24.239363 <6>[ 2.198772] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10663 18:03:24.245940 <6>[ 2.207116] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10664 18:03:24.255746 <6>[ 2.215456] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10665 18:03:24.262524 <6>[ 2.223796] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10666 18:03:24.272801 <6>[ 2.232137] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10667 18:03:24.279372 <6>[ 2.240476] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10668 18:03:24.289457 <6>[ 2.248814] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10669 18:03:24.296279 <6>[ 2.257152] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10670 18:03:24.306289 <6>[ 2.265491] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10671 18:03:24.312725 <6>[ 2.273837] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10672 18:03:24.322735 <6>[ 2.282175] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10673 18:03:24.329148 <6>[ 2.290513] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10674 18:03:24.339183 <6>[ 2.298851] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10675 18:03:24.345669 <6>[ 2.307189] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10676 18:03:24.352681 <6>[ 2.315946] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10677 18:03:24.358817 <6>[ 2.323180] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10678 18:03:24.365486 <6>[ 2.329963] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10679 18:03:24.375364 <6>[ 2.336755] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10680 18:03:24.382057 <6>[ 2.343715] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10681 18:03:24.388968 <6>[ 2.350570] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10682 18:03:24.399041 <6>[ 2.359702] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10683 18:03:24.409047 <6>[ 2.368821] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10684 18:03:24.418783 <6>[ 2.378118] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10685 18:03:24.428513 <6>[ 2.387584] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10686 18:03:24.435256 <6>[ 2.397052] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10687 18:03:24.445275 <6>[ 2.406171] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10688 18:03:24.455369 <6>[ 2.415637] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10689 18:03:24.464933 <6>[ 2.424757] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10690 18:03:24.474967 <6>[ 2.434056] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10691 18:03:24.485029 <6>[ 2.444217] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10692 18:03:24.494976 <6>[ 2.455797] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10693 18:03:24.502741 <6>[ 2.467033] Trying to probe devices needed for running init ...
10694 18:03:24.513023 <3>[ 2.474329] mt8192-audio 11210000.syscon:mt8192-afe-pcm: could not get audiosys reset:-517
10695 18:03:24.592239 <6>[ 2.553184] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10696 18:03:24.619956 <6>[ 2.584627] hub 2-1:1.0: USB hub found
10697 18:03:24.623238 <6>[ 2.589153] hub 2-1:1.0: 3 ports detected
10698 18:03:24.634427 <6>[ 2.598710] hub 2-1:1.0: USB hub found
10699 18:03:24.637581 <6>[ 2.603149] hub 2-1:1.0: 3 ports detected
10700 18:03:24.743617 <6>[ 2.704938] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10701 18:03:24.898982 <6>[ 2.862858] hub 1-1:1.0: USB hub found
10702 18:03:24.901711 <6>[ 2.867362] hub 1-1:1.0: 4 ports detected
10703 18:03:24.915067 <6>[ 2.879664] hub 1-1:1.0: USB hub found
10704 18:03:24.918436 <6>[ 2.884075] hub 1-1:1.0: 4 ports detected
10705 18:03:24.975734 <6>[ 2.937164] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10706 18:03:25.084160 <6>[ 3.045564] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10707 18:03:25.119965 <4>[ 3.081326] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10708 18:03:25.129837 <4>[ 3.090502] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10709 18:03:25.173741 <6>[ 3.138511] r8152 2-1.3:1.0 eth0: v1.12.13
10710 18:03:25.243283 <6>[ 3.204960] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10711 18:03:25.376304 <6>[ 3.340808] hub 1-1.4:1.0: USB hub found
10712 18:03:25.379140 <6>[ 3.345470] hub 1-1.4:1.0: 2 ports detected
10713 18:03:25.393965 <6>[ 3.358337] hub 1-1.4:1.0: USB hub found
10714 18:03:25.397452 <6>[ 3.362969] hub 1-1.4:1.0: 2 ports detected
10715 18:03:25.694973 <6>[ 3.656799] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10716 18:03:25.887253 <6>[ 3.848800] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10717 18:03:26.825602 <6>[ 4.790729] r8152 2-1.3:1.0 eth0: carrier on
10718 18:03:29.395536 <5>[ 4.816755] Sending DHCP requests .., OK
10719 18:03:29.401890 <6>[ 7.365156] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.21
10720 18:03:29.405173 <6>[ 7.373478] IP-Config: Complete:
10721 18:03:29.418936 <6>[ 7.376975] device=eth0, hwaddr=00:e0:4c:72:2d:d6, ipaddr=192.168.201.21, mask=255.255.255.0, gw=192.168.201.1
10722 18:03:29.425397 <6>[ 7.387684] host=mt8192-asurada-spherion-r0-cbg-1, domain=lava-rack, nis-domain=(none)
10723 18:03:29.431804 <6>[ 7.396301] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10724 18:03:29.438372 <6>[ 7.396310] nameserver0=192.168.201.1
10725 18:03:29.441705 <6>[ 7.408477] clk: Disabling unused clocks
10726 18:03:29.445633 <6>[ 7.413943] ALSA device list:
10727 18:03:29.451962 <6>[ 7.417245] No soundcards found.
10728 18:03:29.459627 <6>[ 7.424865] Freeing unused kernel memory: 8512K
10729 18:03:29.462879 <6>[ 7.429795] Run /init as init process
10730 18:03:29.473324 Loading, please wait...
10731 18:03:29.508729 Starting systemd-udevd version 252.22-1~deb12u1
10732 18:03:29.738837 <6>[ 7.700875] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10733 18:03:29.755512 <6>[ 7.717163] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10734 18:03:29.761867 <6>[ 7.720722] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10735 18:03:29.771469 <6>[ 7.725256] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10736 18:03:29.778509 <4>[ 7.725697] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10737 18:03:29.784938 <6>[ 7.736668] remoteproc remoteproc0: scp is available
10738 18:03:29.791545 <6>[ 7.741737] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10739 18:03:29.798129 <6>[ 7.749831] remoteproc remoteproc0: powering up scp
10740 18:03:29.804863 <6>[ 7.751129] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10741 18:03:29.814963 <6>[ 7.751168] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10742 18:03:29.821422 <6>[ 7.751178] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10743 18:03:29.831208 <6>[ 7.754833] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10744 18:03:29.838098 <3>[ 7.757273] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10745 18:03:29.848230 <3>[ 7.757281] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10746 18:03:29.854653 <3>[ 7.757284] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10747 18:03:29.864465 <3>[ 7.761430] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10748 18:03:29.871071 <3>[ 7.761441] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10749 18:03:29.877549 <3>[ 7.761445] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10750 18:03:29.887900 <3>[ 7.761451] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10751 18:03:29.894416 <3>[ 7.761454] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10752 18:03:29.903975 <3>[ 7.761481] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10753 18:03:29.910763 <3>[ 7.761505] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10754 18:03:29.920466 <3>[ 7.761508] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10755 18:03:29.927350 <3>[ 7.761511] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10756 18:03:29.937267 <3>[ 7.761530] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10757 18:03:29.943688 <3>[ 7.761533] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10758 18:03:29.953433 <3>[ 7.761536] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10759 18:03:29.960574 <3>[ 7.761538] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10760 18:03:29.966874 <3>[ 7.761541] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10761 18:03:29.977144 <3>[ 7.761554] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10762 18:03:29.983714 <6>[ 7.764438] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10763 18:03:29.993567 <6>[ 7.768276] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10764 18:03:30.000209 <6>[ 7.775631] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10765 18:03:30.006530 <6>[ 7.784315] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10766 18:03:30.013015 <4>[ 7.800111] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10767 18:03:30.022969 <6>[ 7.800940] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10768 18:03:30.029532 <4>[ 7.809618] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10769 18:03:30.033340 <6>[ 7.812542] mc: Linux media interface: v0.10
10770 18:03:30.042868 <6>[ 7.817110] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10771 18:03:30.049726 <6>[ 7.823895] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10772 18:03:30.059558 <6>[ 7.869092] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10773 18:03:30.066124 <6>[ 7.870052] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10774 18:03:30.072693 <6>[ 7.870062] pci_bus 0000:00: root bus resource [bus 00-ff]
10775 18:03:30.079372 <6>[ 7.870073] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10776 18:03:30.089503 <6>[ 7.870080] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10777 18:03:30.096310 <6>[ 7.870123] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10778 18:03:30.102800 <6>[ 7.870147] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10779 18:03:30.109214 <6>[ 7.870225] pci 0000:00:00.0: supports D1 D2
10780 18:03:30.115855 <6>[ 7.870229] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10781 18:03:30.122261 <6>[ 7.871917] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10782 18:03:30.129255 <6>[ 7.872038] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10783 18:03:30.135841 <6>[ 7.872069] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10784 18:03:30.145698 <6>[ 7.872090] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10785 18:03:30.152346 <6>[ 7.872108] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10786 18:03:30.155574 <6>[ 7.872225] pci 0000:01:00.0: supports D1 D2
10787 18:03:30.161936 <6>[ 7.872229] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10788 18:03:30.168470 <6>[ 7.884881] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10789 18:03:30.178845 <6>[ 7.890769] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10790 18:03:30.188818 <6>[ 7.898453] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10791 18:03:30.195100 <4>[ 7.914324] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10792 18:03:30.201709 <4>[ 7.914324] Fallback method does not support PEC.
10793 18:03:30.208415 <6>[ 7.914674] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10794 18:03:30.215353 <6>[ 7.918973] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10795 18:03:30.224799 <6>[ 7.919049] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10796 18:03:30.231741 <6>[ 7.919062] remoteproc remoteproc0: remote processor scp is now up
10797 18:03:30.241368 <6>[ 7.932801] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10798 18:03:30.247916 <6>[ 7.938951] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10799 18:03:30.254515 <6>[ 7.965039] videodev: Linux video capture interface: v2.00
10800 18:03:30.261637 <6>[ 7.969155] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10801 18:03:30.264905 <6>[ 7.984822] Bluetooth: Core ver 2.22
10802 18:03:30.274531 <6>[ 7.986228] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10803 18:03:30.281084 <6>[ 7.991932] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10804 18:03:30.291045 <6>[ 7.994289] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10805 18:03:30.294328 <6>[ 7.999279] NET: Registered PF_BLUETOOTH protocol family
10806 18:03:30.301446 <6>[ 8.003753] pci 0000:00:00.0: PCI bridge to [bus 01]
10807 18:03:30.307988 <6>[ 8.012965] Bluetooth: HCI device and connection manager initialized
10808 18:03:30.314528 <6>[ 8.020519] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10809 18:03:30.321328 <6>[ 8.030626] Bluetooth: HCI socket layer initialized
10810 18:03:30.327495 <6>[ 8.037652] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10811 18:03:30.334107 <6>[ 8.038835] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10812 18:03:30.347290 <6>[ 8.039838] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10813 18:03:30.350889 <6>[ 8.039928] usbcore: registered new interface driver uvcvideo
10814 18:03:30.357209 <6>[ 8.044149] Bluetooth: L2CAP socket layer initialized
10815 18:03:30.363585 <6>[ 8.051070] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10816 18:03:30.370795 <6>[ 8.051554] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10817 18:03:30.376958 <6>[ 8.051759] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10818 18:03:30.380757 <6>[ 8.060259] Bluetooth: SCO socket layer initialized
10819 18:03:30.390307 <5>[ 8.068841] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10820 18:03:30.393711 <6>[ 8.122679] usbcore: registered new interface driver btusb
10821 18:03:30.406752 <4>[ 8.123571] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10822 18:03:30.410085 <3>[ 8.123588] Bluetooth: hci0: Failed to load firmware file (-2)
10823 18:03:30.416600 <3>[ 8.123595] Bluetooth: hci0: Failed to set up firmware (-2)
10824 18:03:30.426751 <4>[ 8.123602] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10825 18:03:30.433154 <5>[ 8.140183] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10826 18:03:30.442929 <5>[ 8.405296] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10827 18:03:30.453215 <4>[ 8.413715] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10828 18:03:30.456255 <6>[ 8.422592] cfg80211: failed to load regulatory.db
10829 18:03:30.498112 <6>[ 8.460347] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10830 18:03:30.504664 <6>[ 8.467850] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10831 18:03:30.528932 <6>[ 8.494498] mt7921e 0000:01:00.0: ASIC revision: 79610010
10832 18:03:30.630007 <6>[ 8.592319] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10833 18:03:30.633297 <6>[ 8.592319]
10834 18:03:30.644187 Begin: Loading essential drivers ... done.
10835 18:03:30.647500 Begin: Running /scripts/init-premount ... done.
10836 18:03:30.654427 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10837 18:03:30.664397 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10838 18:03:30.667609 Device /sys/class/net/eth0 found
10839 18:03:30.667692 done.
10840 18:03:30.695405 Begin: Waiting up to 180 secs for any network device to become available ... done.
10841 18:03:30.759231 IP-Config: eth0 hardware address 00:e0:4c:72:2d:d6 mtu 1500 DHCP
10842 18:03:30.944764 <6>[ 8.860014] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10843 18:03:30.957177 IP-Config: eth0 complete (dhcp from 192.168.201.1):
10844 18:03:30.963659 address: 192.168.201.21 broadcast: 192.168.201.255 netmask: 255.255.255.0
10845 18:03:30.969830 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10846 18:03:30.976927 host : mt8192-asurada-spherion-r0-cbg-1
10847 18:03:30.983183 domain : lava-rack
10848 18:03:30.986279 rootserver: 192.168.201.1 rootpath:
10849 18:03:30.989415 filename :
10850 18:03:31.097348 done.
10851 18:03:31.100487 Begin: Running /scripts/nfs-bottom ... done.
10852 18:03:31.123334 Begin: Running /scripts/init-bottom ... done.
10853 18:03:32.427152 <6>[ 10.392696] NET: Registered PF_INET6 protocol family
10854 18:03:32.434835 <6>[ 10.400313] Segment Routing with IPv6
10855 18:03:32.437564 <6>[ 10.404313] In-situ OAM (IOAM) with IPv6
10856 18:03:32.605740 <30>[ 10.545176] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10857 18:03:32.613135 <30>[ 10.578768] systemd[1]: Detected architecture arm64.
10858 18:03:32.620404
10859 18:03:32.623738 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10860 18:03:32.623821
10861 18:03:32.648235 <30>[ 10.613810] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10862 18:03:33.623098 <30>[ 11.585580] systemd[1]: Queued start job for default target graphical.target.
10863 18:03:33.675091 <30>[ 11.637789] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10864 18:03:33.681544 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10865 18:03:33.704247 <30>[ 11.666739] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10866 18:03:33.714297 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10867 18:03:33.732108 <30>[ 11.694664] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10868 18:03:33.742222 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10869 18:03:33.760469 <30>[ 11.723128] systemd[1]: Created slice user.slice - User and Session Slice.
10870 18:03:33.767051 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10871 18:03:33.790120 <30>[ 11.749291] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10872 18:03:33.796880 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10873 18:03:33.818112 <30>[ 11.777169] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10874 18:03:33.824452 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10875 18:03:33.852799 <30>[ 11.805589] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10876 18:03:33.863125 <30>[ 11.825506] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10877 18:03:33.869765 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10878 18:03:33.886406 <30>[ 11.848926] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10879 18:03:33.893133 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10880 18:03:33.910303 <30>[ 11.872977] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10881 18:03:33.920145 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10882 18:03:33.935370 <30>[ 11.901050] systemd[1]: Reached target paths.target - Path Units.
10883 18:03:33.945239 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10884 18:03:33.962700 <30>[ 11.925277] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10885 18:03:33.969080 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10886 18:03:33.983147 <30>[ 11.948923] systemd[1]: Reached target slices.target - Slice Units.
10887 18:03:33.992878 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10888 18:03:34.007473 <30>[ 11.973451] systemd[1]: Reached target swap.target - Swaps.
10889 18:03:34.013930 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10890 18:03:34.035169 <30>[ 11.997426] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10891 18:03:34.044990 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10892 18:03:34.063064 <30>[ 12.025457] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10893 18:03:34.073194 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10894 18:03:34.093352 <30>[ 12.055802] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10895 18:03:34.103009 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10896 18:03:34.119755 <30>[ 12.082257] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10897 18:03:34.129706 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10898 18:03:34.147900 <30>[ 12.110240] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10899 18:03:34.154405 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10900 18:03:34.176019 <30>[ 12.138360] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10901 18:03:34.185831 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10902 18:03:34.204722 <30>[ 12.167431] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10903 18:03:34.214832 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10904 18:03:34.230688 <30>[ 12.193422] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10905 18:03:34.240670 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10906 18:03:34.282410 <30>[ 12.245080] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10907 18:03:34.289076 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10908 18:03:34.310905 <30>[ 12.273644] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10909 18:03:34.317645 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10910 18:03:34.343208 <30>[ 12.305695] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10911 18:03:34.349717 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10912 18:03:34.377640 <30>[ 12.333473] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10913 18:03:34.415004 <30>[ 12.377435] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10914 18:03:34.424833 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10915 18:03:34.447526 <30>[ 12.410273] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10916 18:03:34.454208 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10917 18:03:34.523131 <30>[ 12.485728] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10918 18:03:34.529934 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10919 18:03:34.553847 <30>[ 12.516441] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10920 18:03:34.567008 Starting [0;1;39mmodpr<6>[ 12.526699] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10921 18:03:34.570283 obe@drm.service[0m - Load Kernel Module drm...
10922 18:03:34.595703 <30>[ 12.558397] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10923 18:03:34.602677 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10924 18:03:34.626467 <30>[ 12.588912] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10925 18:03:34.632815 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10926 18:03:34.656425 <30>[ 12.618216] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10927 18:03:34.662176 Startin<6>[ 12.626968] fuse: init (API version 7.37)
10928 18:03:34.665817 g [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10929 18:03:34.694911 <30>[ 12.657390] systemd[1]: Starting systemd-journald.service - Journal Service...
10930 18:03:34.701471 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10931 18:03:34.732378 <30>[ 12.695229] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10932 18:03:34.739533 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10933 18:03:34.766158 <30>[ 12.725482] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10934 18:03:34.772536 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10935 18:03:34.799891 <30>[ 12.762576] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10936 18:03:34.810187 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10937 18:03:34.837575 <30>[ 12.799946] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10938 18:03:34.847051 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10939 18:03:34.871154 <30>[ 12.833909] systemd[1]: Started systemd-journald.service - Journal Service.
10940 18:03:34.877978 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10941 18:03:34.898834 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10942 18:03:34.915313 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10943 18:03:34.936080 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10944 18:03:34.956028 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10945 18:03:34.977368 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10946 18:03:34.996241 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10947 18:03:35.015874 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10948 18:03:35.035579 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10949 18:03:35.057075 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
10950 18:03:35.077257 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10951 18:03:35.096033 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10952 18:03:35.116177 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10953 18:03:35.135741 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
10954 18:03:35.156895 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10955 18:03:35.211328 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
10956 18:03:35.232686 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10957 18:03:35.260555 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10958 18:03:35.283565 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10959 18:03:35.310964 <46>[ 13.273726] systemd-journald[307]: Received client request to flush runtime journal.
10960 18:03:35.317608 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10961 18:03:35.348427 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10962 18:03:35.620252 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10963 18:03:35.639572 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
10964 18:03:35.659325 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10965 18:03:35.680253 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10966 18:03:36.175053 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10967 18:03:36.711204 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10968 18:03:36.736264 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10969 18:03:36.787601 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10970 18:03:36.855983 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10971 18:03:36.874666 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10972 18:03:36.890221 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10973 18:03:36.954611 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10974 18:03:36.978407 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10975 18:03:37.170216 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10976 18:03:37.256503 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
10977 18:03:37.280965 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10978 18:03:37.318078 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10979 18:03:37.496960 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10980 18:03:37.535276 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10981 18:03:37.645884 <6>[ 15.612016] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10982 18:03:37.706723 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10983 18:03:37.756029 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
10984 18:03:37.778763 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
10985 18:03:37.834339 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
10986 18:03:37.850776 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
10987 18:03:37.884847 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10988 18:03:37.910841 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
10989 18:03:37.934100 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
10990 18:03:37.954453 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
10991 18:03:37.971752 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
10992 18:03:37.994979 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10993 18:03:38.022061 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
10994 18:03:38.040860 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
10995 18:03:38.058126 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
10996 18:03:38.081403 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
10997 18:03:38.105088 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
10998 18:03:38.126041 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10999 18:03:38.142150 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
11000 18:03:38.169820 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
11001 18:03:38.190275 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
11002 18:03:38.196907 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
11003 18:03:38.259645 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11004 18:03:38.291436 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
11005 18:03:38.379924 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11006 18:03:38.405951 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11007 18:03:38.432259 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11008 18:03:38.507000 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11009 18:03:38.531346 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11010 18:03:38.568902 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11011 18:03:38.623443 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11012 18:03:38.641246 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11013 18:03:38.658652 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11014 18:03:38.675746 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11015 18:03:38.772662 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
11016 18:03:38.796098 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11017 18:03:38.819680 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11018 18:03:38.881348 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11019 18:03:38.921395 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11020 18:03:38.982991
11021 18:03:38.986142 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11022 18:03:38.986235
11023 18:03:38.989466 debian-bookworm-arm64 login: root (automatic login)
11024 18:03:38.989556
11025 18:03:39.258419 Linux debian-bookworm-arm64 6.1.92-cip22 #1 SMP PREEMPT Tue Jun 11 17:44:14 UTC 2024 aarch64
11026 18:03:39.258584
11027 18:03:39.264800 The programs included with the Debian GNU/Linux system are free software;
11028 18:03:39.271865 the exact distribution terms for each program are described in the
11029 18:03:39.274958 individual files in /usr/share/doc/*/copyright.
11030 18:03:39.275074
11031 18:03:39.281606 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11032 18:03:39.284793 permitted by applicable law.
11033 18:03:40.272755 Matched prompt #10: / #
11035 18:03:40.273031 Setting prompt string to ['/ #']
11036 18:03:40.273156 end: 2.2.5.1 login-action (duration 00:00:19) [common]
11038 18:03:40.273341 end: 2.2.5 auto-login-action (duration 00:00:19) [common]
11039 18:03:40.273428 start: 2.2.6 expect-shell-connection (timeout 00:03:44) [common]
11040 18:03:40.273498 Setting prompt string to ['/ #']
11041 18:03:40.273557 Forcing a shell prompt, looking for ['/ #']
11043 18:03:40.323887 / #
11044 18:03:40.324148 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11045 18:03:40.324292 Waiting using forced prompt support (timeout 00:02:30)
11046 18:03:40.329284
11047 18:03:40.329744 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11048 18:03:40.329959 start: 2.2.7 export-device-env (timeout 00:03:44) [common]
11050 18:03:40.430634 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14291372/extract-nfsrootfs-6eprz0iq'
11051 18:03:40.436514 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14291372/extract-nfsrootfs-6eprz0iq'
11053 18:03:40.538054 / # export NFS_SERVER_IP='192.168.201.1'
11054 18:03:40.544159 export NFS_SERVER_IP='192.168.201.1'
11055 18:03:40.544974 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11056 18:03:40.545543 end: 2.2 depthcharge-retry (duration 00:01:16) [common]
11057 18:03:40.546101 end: 2 depthcharge-action (duration 00:01:16) [common]
11058 18:03:40.546633 start: 3 lava-test-retry (timeout 00:08:03) [common]
11059 18:03:40.547158 start: 3.1 lava-test-shell (timeout 00:08:03) [common]
11060 18:03:40.547601 Using namespace: common
11062 18:03:40.648733 / # #
11063 18:03:40.649295 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11064 18:03:40.655051 #
11065 18:03:40.655777 Using /lava-14291372
11067 18:03:40.757026 / # export SHELL=/bin/bash
11068 18:03:40.762751 export SHELL=/bin/bash
11070 18:03:40.864215 / # . /lava-14291372/environment
11071 18:03:40.870769 . /lava-14291372/environment
11073 18:03:40.978191 / # /lava-14291372/bin/lava-test-runner /lava-14291372/0
11074 18:03:40.978819 Test shell timeout: 10s (minimum of the action and connection timeout)
11075 18:03:40.984593 /lava-14291372/bin/lava-test-runner /lava-14291372/0
11076 18:03:41.228799 + export TESTRUN_ID=0_timesync-off
11077 18:03:41.232167 + TESTRUN_ID=0_timesync-off
11078 18:03:41.235471 + cd /lava-14291372/0/tests/0_timesync-off
11079 18:03:41.238436 ++ cat uuid
11080 18:03:41.242184 + UUID=14291372_1.6.2.3.1
11081 18:03:41.242271 + set +x
11082 18:03:41.245471 <LAVA_SIGNAL_STARTRUN 0_timesync-off 14291372_1.6.2.3.1>
11083 18:03:41.245737 Received signal: <STARTRUN> 0_timesync-off 14291372_1.6.2.3.1
11084 18:03:41.245825 Starting test lava.0_timesync-off (14291372_1.6.2.3.1)
11085 18:03:41.245934 Skipping test definition patterns.
11086 18:03:41.248827 + systemctl stop systemd-timesyncd
11087 18:03:41.313590 + set +x
11088 18:03:41.316724 <LAVA_SIGNAL_ENDRUN 0_timesync-off 14291372_1.6.2.3.1>
11089 18:03:41.317404 Received signal: <ENDRUN> 0_timesync-off 14291372_1.6.2.3.1
11090 18:03:41.317809 Ending use of test pattern.
11091 18:03:41.318178 Ending test lava.0_timesync-off (14291372_1.6.2.3.1), duration 0.07
11093 18:03:41.384098 + export TESTRUN_ID=1_kselftest-alsa
11094 18:03:41.386965 + TESTRUN_ID=1_kselftest-alsa
11095 18:03:41.393539 + cd /lava-14291372/0/tests/1_kselftest-alsa
11096 18:03:41.393987 ++ cat uuid
11097 18:03:41.398372 + UUID=14291372_1.6.2.3.5
11098 18:03:41.398803 + set +x
11099 18:03:41.404722 <LAVA_SIGNAL_STARTRUN 1_kselftest-alsa 14291372_1.6.2.3.5>
11100 18:03:41.405400 Received signal: <STARTRUN> 1_kselftest-alsa 14291372_1.6.2.3.5
11101 18:03:41.405750 Starting test lava.1_kselftest-alsa (14291372_1.6.2.3.5)
11102 18:03:41.406154 Skipping test definition patterns.
11103 18:03:41.408037 + cd ./automated/linux/kselftest/
11104 18:03:41.434581 + ./kselftest.sh -c alsa -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-17-g24b63cdc814f/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11105 18:03:41.476801 INFO: install_deps skipped
11106 18:03:41.978361 --2024-06-11 18:02:16-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-17-g24b63cdc814f/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11107 18:03:41.984927 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11108 18:03:42.113692 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11109 18:03:42.246981 HTTP request sent, awaiting response... 200 OK
11110 18:03:42.250780 Length: 1647744 (1.6M) [application/octet-stream]
11111 18:03:42.253883 Saving to: 'kselftest_armhf.tar.gz'
11112 18:03:42.254444
11113 18:03:42.254810
11114 18:03:42.512565 kselftest_armhf.tar 0%[ ] 0 --.-KB/s
11115 18:03:42.778884 kselftest_armhf.tar 2%[ ] 47.81K 180KB/s
11116 18:03:43.092111 kselftest_armhf.tar 13%[=> ] 217.50K 409KB/s
11117 18:03:43.228940 kselftest_armhf.tar 49%[========> ] 793.02K 938KB/s
11118 18:03:43.235112 kselftest_armhf.tar 100%[===================>] 1.57M 1.60MB/s in 1.0s
11119 18:03:43.235196
11120 18:03:43.379857 2024-06-11 18:02:17 (1.60 MB/s) - 'kselftest_armhf.tar.gz' saved [1647744/1647744]
11121 18:03:43.379987
11122 18:03:47.019898 skiplist:
11123 18:03:47.022989 ========================================
11124 18:03:47.026236 ========================================
11125 18:03:47.065393 alsa:mixer-test
11126 18:03:47.083021 ============== Tests to run ===============
11127 18:03:47.083133 alsa:mixer-test
11128 18:03:47.086749 ===========End Tests to run ===============
11129 18:03:47.089948 shardfile-alsa pass
11130 18:03:47.183752 <12>[ 25.151062] kselftest: Running tests in alsa
11131 18:03:47.190962 TAP version 13
11132 18:03:47.203831 1..1
11133 18:03:47.216265 # selftests: alsa: mixer-test
11134 18:03:47.713427 # TAP version 13
11135 18:03:47.714092 # 1..0
11136 18:03:47.720055 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:0 error:0
11137 18:03:47.723193 ok 1 selftests: alsa: mixer-test
11138 18:03:49.141102 alsa_mixer-test pass
11139 18:03:49.245433 + ../../utils/send-to-lava.sh ./output/result.txt
11140 18:03:49.332683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-alsa RESULT=pass>
11141 18:03:49.333031 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-alsa RESULT=pass
11143 18:03:49.406084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test RESULT=pass>
11144 18:03:49.406249 + set +x
11145 18:03:49.406538 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test RESULT=pass
11147 18:03:49.413121 <LAVA_SIGNAL_ENDRUN 1_kselftest-alsa 14291372_1.6.2.3.5>
11148 18:03:49.413397 Received signal: <ENDRUN> 1_kselftest-alsa 14291372_1.6.2.3.5
11149 18:03:49.413477 Ending use of test pattern.
11150 18:03:49.413540 Ending test lava.1_kselftest-alsa (14291372_1.6.2.3.5), duration 8.01
11152 18:03:49.416235 <LAVA_TEST_RUNNER EXIT>
11153 18:03:49.416514 ok: lava_test_shell seems to have completed
11154 18:03:49.416657 alsa_mixer-test: pass
shardfile-alsa: pass
11155 18:03:49.416751 end: 3.1 lava-test-shell (duration 00:00:09) [common]
11156 18:03:49.416839 end: 3 lava-test-retry (duration 00:00:09) [common]
11157 18:03:49.416928 start: 4 finalize (timeout 00:07:55) [common]
11158 18:03:49.417017 start: 4.1 power-off (timeout 00:00:30) [common]
11159 18:03:49.417168 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-1', '--port=1', '--command=off']
11160 18:03:49.627439 >> Command sent successfully.
11161 18:03:49.634823 Returned 0 in 0 seconds
11162 18:03:49.735545 end: 4.1 power-off (duration 00:00:00) [common]
11164 18:03:49.736245 start: 4.2 read-feedback (timeout 00:07:54) [common]
11165 18:03:49.736744 Listened to connection for namespace 'common' for up to 1s
11166 18:03:50.736608 Finalising connection for namespace 'common'
11167 18:03:50.736794 Disconnecting from shell: Finalise
11168 18:03:50.736903 / #
11169 18:03:50.837223 end: 4.2 read-feedback (duration 00:00:01) [common]
11170 18:03:50.837416 end: 4 finalize (duration 00:00:01) [common]
11171 18:03:50.837560 Cleaning after the job
11172 18:03:50.837688 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14291372/tftp-deploy-hgwt2mnh/ramdisk
11173 18:03:50.839821 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14291372/tftp-deploy-hgwt2mnh/kernel
11174 18:03:50.850800 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14291372/tftp-deploy-hgwt2mnh/dtb
11175 18:03:50.851017 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14291372/tftp-deploy-hgwt2mnh/nfsrootfs
11176 18:03:50.913759 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14291372/tftp-deploy-hgwt2mnh/modules
11177 18:03:50.919258 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14291372
11178 18:03:51.462935 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14291372
11179 18:03:51.463125 Job finished correctly