Boot log: mt8192-asurada-spherion-r0
- Errors: 1
- Kernel Errors: 30
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 22
1 00:42:06.416604 lava-dispatcher, installed at version: 2024.03
2 00:42:06.416841 start: 0 validate
3 00:42:06.416953 Start time: 2024-06-16 00:42:06.416948+00:00 (UTC)
4 00:42:06.417094 Using caching service: 'http://localhost/cache/?uri=%s'
5 00:42:06.417233 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-cros-ec%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 00:42:06.671713 Using caching service: 'http://localhost/cache/?uri=%s'
7 00:42:06.672475 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22-24-g0315de64ea248%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 00:42:06.925491 Using caching service: 'http://localhost/cache/?uri=%s'
9 00:42:06.926461 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22-24-g0315de64ea248%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 00:42:07.180672 Using caching service: 'http://localhost/cache/?uri=%s'
11 00:42:07.181313 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22-24-g0315de64ea248%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 00:42:07.443680 validate duration: 1.03
14 00:42:07.444898 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 00:42:07.445446 start: 1.1 download-retry (timeout 00:10:00) [common]
16 00:42:07.445916 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 00:42:07.446726 Not decompressing ramdisk as can be used compressed.
18 00:42:07.447251 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-cros-ec/20240313.0/arm64/rootfs.cpio.gz
19 00:42:07.447662 saving as /var/lib/lava/dispatcher/tmp/14368387/tftp-deploy-2edglom8/ramdisk/rootfs.cpio.gz
20 00:42:07.448072 total size: 39026414 (37 MB)
21 00:42:07.452927 progress 0 % (0 MB)
22 00:42:07.485979 progress 5 % (1 MB)
23 00:42:07.500404 progress 10 % (3 MB)
24 00:42:07.511181 progress 15 % (5 MB)
25 00:42:07.521333 progress 20 % (7 MB)
26 00:42:07.531337 progress 25 % (9 MB)
27 00:42:07.541297 progress 30 % (11 MB)
28 00:42:07.551059 progress 35 % (13 MB)
29 00:42:07.560843 progress 40 % (14 MB)
30 00:42:07.570661 progress 45 % (16 MB)
31 00:42:07.580507 progress 50 % (18 MB)
32 00:42:07.590399 progress 55 % (20 MB)
33 00:42:07.600156 progress 60 % (22 MB)
34 00:42:07.610217 progress 65 % (24 MB)
35 00:42:07.620072 progress 70 % (26 MB)
36 00:42:07.629888 progress 75 % (27 MB)
37 00:42:07.639872 progress 80 % (29 MB)
38 00:42:07.650061 progress 85 % (31 MB)
39 00:42:07.659815 progress 90 % (33 MB)
40 00:42:07.669565 progress 95 % (35 MB)
41 00:42:07.679038 progress 100 % (37 MB)
42 00:42:07.679297 37 MB downloaded in 0.23 s (160.96 MB/s)
43 00:42:07.679491 end: 1.1.1 http-download (duration 00:00:00) [common]
45 00:42:07.679729 end: 1.1 download-retry (duration 00:00:00) [common]
46 00:42:07.679810 start: 1.2 download-retry (timeout 00:10:00) [common]
47 00:42:07.679886 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 00:42:07.680016 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-24-g0315de64ea248/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 00:42:07.680082 saving as /var/lib/lava/dispatcher/tmp/14368387/tftp-deploy-2edglom8/kernel/Image
50 00:42:07.680136 total size: 54813184 (52 MB)
51 00:42:07.680190 No compression specified
52 00:42:07.681197 progress 0 % (0 MB)
53 00:42:07.695016 progress 5 % (2 MB)
54 00:42:07.708855 progress 10 % (5 MB)
55 00:42:07.722644 progress 15 % (7 MB)
56 00:42:07.736461 progress 20 % (10 MB)
57 00:42:07.750214 progress 25 % (13 MB)
58 00:42:07.764025 progress 30 % (15 MB)
59 00:42:07.777945 progress 35 % (18 MB)
60 00:42:07.791936 progress 40 % (20 MB)
61 00:42:07.805697 progress 45 % (23 MB)
62 00:42:07.819711 progress 50 % (26 MB)
63 00:42:07.833600 progress 55 % (28 MB)
64 00:42:07.847301 progress 60 % (31 MB)
65 00:42:07.861027 progress 65 % (34 MB)
66 00:42:07.874684 progress 70 % (36 MB)
67 00:42:07.888731 progress 75 % (39 MB)
68 00:42:07.902722 progress 80 % (41 MB)
69 00:42:07.916394 progress 85 % (44 MB)
70 00:42:07.930048 progress 90 % (47 MB)
71 00:42:07.943625 progress 95 % (49 MB)
72 00:42:07.956834 progress 100 % (52 MB)
73 00:42:07.957067 52 MB downloaded in 0.28 s (188.76 MB/s)
74 00:42:07.957217 end: 1.2.1 http-download (duration 00:00:00) [common]
76 00:42:07.957425 end: 1.2 download-retry (duration 00:00:00) [common]
77 00:42:07.957506 start: 1.3 download-retry (timeout 00:09:59) [common]
78 00:42:07.957581 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 00:42:07.957710 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-24-g0315de64ea248/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 00:42:07.957771 saving as /var/lib/lava/dispatcher/tmp/14368387/tftp-deploy-2edglom8/dtb/mt8192-asurada-spherion-r0.dtb
81 00:42:07.957825 total size: 47258 (0 MB)
82 00:42:07.957878 No compression specified
83 00:42:07.958910 progress 69 % (0 MB)
84 00:42:07.959168 progress 100 % (0 MB)
85 00:42:07.959316 0 MB downloaded in 0.00 s (30.27 MB/s)
86 00:42:07.959428 end: 1.3.1 http-download (duration 00:00:00) [common]
88 00:42:07.959627 end: 1.3 download-retry (duration 00:00:00) [common]
89 00:42:07.959702 start: 1.4 download-retry (timeout 00:09:59) [common]
90 00:42:07.959777 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 00:42:07.959877 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-24-g0315de64ea248/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 00:42:07.959938 saving as /var/lib/lava/dispatcher/tmp/14368387/tftp-deploy-2edglom8/modules/modules.tar
93 00:42:07.959990 total size: 8608736 (8 MB)
94 00:42:07.960044 Using unxz to decompress xz
95 00:42:07.961356 progress 0 % (0 MB)
96 00:42:07.979843 progress 5 % (0 MB)
97 00:42:08.005755 progress 10 % (0 MB)
98 00:42:08.033902 progress 15 % (1 MB)
99 00:42:08.057258 progress 20 % (1 MB)
100 00:42:08.080198 progress 25 % (2 MB)
101 00:42:08.103373 progress 30 % (2 MB)
102 00:42:08.127533 progress 35 % (2 MB)
103 00:42:08.153845 progress 40 % (3 MB)
104 00:42:08.176194 progress 45 % (3 MB)
105 00:42:08.199604 progress 50 % (4 MB)
106 00:42:08.224110 progress 55 % (4 MB)
107 00:42:08.248076 progress 60 % (4 MB)
108 00:42:08.271822 progress 65 % (5 MB)
109 00:42:08.296227 progress 70 % (5 MB)
110 00:42:08.321485 progress 75 % (6 MB)
111 00:42:08.346623 progress 80 % (6 MB)
112 00:42:08.370173 progress 85 % (7 MB)
113 00:42:08.394279 progress 90 % (7 MB)
114 00:42:08.419335 progress 95 % (7 MB)
115 00:42:08.443290 progress 100 % (8 MB)
116 00:42:08.448589 8 MB downloaded in 0.49 s (16.80 MB/s)
117 00:42:08.448750 end: 1.4.1 http-download (duration 00:00:00) [common]
119 00:42:08.448962 end: 1.4 download-retry (duration 00:00:00) [common]
120 00:42:08.449043 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 00:42:08.449121 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 00:42:08.449193 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 00:42:08.449265 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 00:42:08.449427 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14368387/lava-overlay-muktlp0y
125 00:42:08.449544 makedir: /var/lib/lava/dispatcher/tmp/14368387/lava-overlay-muktlp0y/lava-14368387/bin
126 00:42:08.449638 makedir: /var/lib/lava/dispatcher/tmp/14368387/lava-overlay-muktlp0y/lava-14368387/tests
127 00:42:08.449726 makedir: /var/lib/lava/dispatcher/tmp/14368387/lava-overlay-muktlp0y/lava-14368387/results
128 00:42:08.449812 Creating /var/lib/lava/dispatcher/tmp/14368387/lava-overlay-muktlp0y/lava-14368387/bin/lava-add-keys
129 00:42:08.449941 Creating /var/lib/lava/dispatcher/tmp/14368387/lava-overlay-muktlp0y/lava-14368387/bin/lava-add-sources
130 00:42:08.450059 Creating /var/lib/lava/dispatcher/tmp/14368387/lava-overlay-muktlp0y/lava-14368387/bin/lava-background-process-start
131 00:42:08.450177 Creating /var/lib/lava/dispatcher/tmp/14368387/lava-overlay-muktlp0y/lava-14368387/bin/lava-background-process-stop
132 00:42:08.450337 Creating /var/lib/lava/dispatcher/tmp/14368387/lava-overlay-muktlp0y/lava-14368387/bin/lava-common-functions
133 00:42:08.450456 Creating /var/lib/lava/dispatcher/tmp/14368387/lava-overlay-muktlp0y/lava-14368387/bin/lava-echo-ipv4
134 00:42:08.450570 Creating /var/lib/lava/dispatcher/tmp/14368387/lava-overlay-muktlp0y/lava-14368387/bin/lava-install-packages
135 00:42:08.450684 Creating /var/lib/lava/dispatcher/tmp/14368387/lava-overlay-muktlp0y/lava-14368387/bin/lava-installed-packages
136 00:42:08.450797 Creating /var/lib/lava/dispatcher/tmp/14368387/lava-overlay-muktlp0y/lava-14368387/bin/lava-os-build
137 00:42:08.450909 Creating /var/lib/lava/dispatcher/tmp/14368387/lava-overlay-muktlp0y/lava-14368387/bin/lava-probe-channel
138 00:42:08.451021 Creating /var/lib/lava/dispatcher/tmp/14368387/lava-overlay-muktlp0y/lava-14368387/bin/lava-probe-ip
139 00:42:08.451133 Creating /var/lib/lava/dispatcher/tmp/14368387/lava-overlay-muktlp0y/lava-14368387/bin/lava-target-ip
140 00:42:08.451245 Creating /var/lib/lava/dispatcher/tmp/14368387/lava-overlay-muktlp0y/lava-14368387/bin/lava-target-mac
141 00:42:08.451356 Creating /var/lib/lava/dispatcher/tmp/14368387/lava-overlay-muktlp0y/lava-14368387/bin/lava-target-storage
142 00:42:08.451472 Creating /var/lib/lava/dispatcher/tmp/14368387/lava-overlay-muktlp0y/lava-14368387/bin/lava-test-case
143 00:42:08.451586 Creating /var/lib/lava/dispatcher/tmp/14368387/lava-overlay-muktlp0y/lava-14368387/bin/lava-test-event
144 00:42:08.451697 Creating /var/lib/lava/dispatcher/tmp/14368387/lava-overlay-muktlp0y/lava-14368387/bin/lava-test-feedback
145 00:42:08.451809 Creating /var/lib/lava/dispatcher/tmp/14368387/lava-overlay-muktlp0y/lava-14368387/bin/lava-test-raise
146 00:42:08.451920 Creating /var/lib/lava/dispatcher/tmp/14368387/lava-overlay-muktlp0y/lava-14368387/bin/lava-test-reference
147 00:42:08.452033 Creating /var/lib/lava/dispatcher/tmp/14368387/lava-overlay-muktlp0y/lava-14368387/bin/lava-test-runner
148 00:42:08.452145 Creating /var/lib/lava/dispatcher/tmp/14368387/lava-overlay-muktlp0y/lava-14368387/bin/lava-test-set
149 00:42:08.452257 Creating /var/lib/lava/dispatcher/tmp/14368387/lava-overlay-muktlp0y/lava-14368387/bin/lava-test-shell
150 00:42:08.452371 Updating /var/lib/lava/dispatcher/tmp/14368387/lava-overlay-muktlp0y/lava-14368387/bin/lava-install-packages (oe)
151 00:42:08.452512 Updating /var/lib/lava/dispatcher/tmp/14368387/lava-overlay-muktlp0y/lava-14368387/bin/lava-installed-packages (oe)
152 00:42:08.452622 Creating /var/lib/lava/dispatcher/tmp/14368387/lava-overlay-muktlp0y/lava-14368387/environment
153 00:42:08.452708 LAVA metadata
154 00:42:08.452780 - LAVA_JOB_ID=14368387
155 00:42:08.452838 - LAVA_DISPATCHER_IP=192.168.201.1
156 00:42:08.452931 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 00:42:08.453009 skipped lava-vland-overlay
158 00:42:08.453118 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 00:42:08.453193 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 00:42:08.453247 skipped lava-multinode-overlay
161 00:42:08.453313 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 00:42:08.453384 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 00:42:08.453447 Loading test definitions
164 00:42:08.453523 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 00:42:08.453582 Using /lava-14368387 at stage 0
166 00:42:08.453879 uuid=14368387_1.5.2.3.1 testdef=None
167 00:42:08.453961 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 00:42:08.454038 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 00:42:08.454509 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 00:42:08.454710 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 00:42:08.455255 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 00:42:08.455462 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 00:42:08.456746 runner path: /var/lib/lava/dispatcher/tmp/14368387/lava-overlay-muktlp0y/lava-14368387/0/tests/0_cros-ec test_uuid 14368387_1.5.2.3.1
176 00:42:08.456892 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 00:42:08.457083 Creating lava-test-runner.conf files
179 00:42:08.457140 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14368387/lava-overlay-muktlp0y/lava-14368387/0 for stage 0
180 00:42:08.457221 - 0_cros-ec
181 00:42:08.457314 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 00:42:08.457392 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 00:42:08.463503 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 00:42:08.463604 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 00:42:08.463684 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 00:42:08.463762 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 00:42:08.463840 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 00:42:09.645464 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 00:42:09.645612 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 00:42:09.645697 extracting modules file /var/lib/lava/dispatcher/tmp/14368387/tftp-deploy-2edglom8/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14368387/extract-overlay-ramdisk-fzsd7gr9/ramdisk
191 00:42:09.872509 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 00:42:09.872652 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
193 00:42:09.872737 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14368387/compress-overlay-nr7z5ysq/overlay-1.5.2.4.tar.gz to ramdisk
194 00:42:09.872799 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14368387/compress-overlay-nr7z5ysq/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14368387/extract-overlay-ramdisk-fzsd7gr9/ramdisk
195 00:42:09.879124 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 00:42:09.879223 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
197 00:42:09.879307 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 00:42:09.879386 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
199 00:42:09.879463 Building ramdisk /var/lib/lava/dispatcher/tmp/14368387/extract-overlay-ramdisk-fzsd7gr9/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14368387/extract-overlay-ramdisk-fzsd7gr9/ramdisk
200 00:42:10.742547 >> 335941 blocks
201 00:42:16.006290 rename /var/lib/lava/dispatcher/tmp/14368387/extract-overlay-ramdisk-fzsd7gr9/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14368387/tftp-deploy-2edglom8/ramdisk/ramdisk.cpio.gz
202 00:42:16.006524 end: 1.5.7 compress-ramdisk (duration 00:00:06) [common]
203 00:42:16.006663 start: 1.5.8 prepare-kernel (timeout 00:09:51) [common]
204 00:42:16.006799 start: 1.5.8.1 prepare-fit (timeout 00:09:51) [common]
205 00:42:16.006922 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14368387/tftp-deploy-2edglom8/kernel/Image']
206 00:42:29.532574 Returned 0 in 13 seconds
207 00:42:29.633102 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14368387/tftp-deploy-2edglom8/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14368387/tftp-deploy-2edglom8/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14368387/tftp-deploy-2edglom8/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14368387/tftp-deploy-2edglom8/kernel/image.itb
208 00:42:30.465639 output: FIT description: Kernel Image image with one or more FDT blobs
209 00:42:30.465775 output: Created: Sun Jun 16 01:42:30 2024
210 00:42:30.465840 output: Image 0 (kernel-1)
211 00:42:30.465914 output: Description:
212 00:42:30.465969 output: Created: Sun Jun 16 01:42:30 2024
213 00:42:30.466027 output: Type: Kernel Image
214 00:42:30.466086 output: Compression: lzma compressed
215 00:42:30.466147 output: Data Size: 13126376 Bytes = 12818.73 KiB = 12.52 MiB
216 00:42:30.466204 output: Architecture: AArch64
217 00:42:30.466298 output: OS: Linux
218 00:42:30.466356 output: Load Address: 0x00000000
219 00:42:30.466411 output: Entry Point: 0x00000000
220 00:42:30.466468 output: Hash algo: crc32
221 00:42:30.466523 output: Hash value: c791a20a
222 00:42:30.466575 output: Image 1 (fdt-1)
223 00:42:30.466624 output: Description: mt8192-asurada-spherion-r0
224 00:42:30.466674 output: Created: Sun Jun 16 01:42:30 2024
225 00:42:30.466723 output: Type: Flat Device Tree
226 00:42:30.466772 output: Compression: uncompressed
227 00:42:30.466820 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
228 00:42:30.466870 output: Architecture: AArch64
229 00:42:30.466917 output: Hash algo: crc32
230 00:42:30.466963 output: Hash value: 0f8e4d2e
231 00:42:30.467010 output: Image 2 (ramdisk-1)
232 00:42:30.467057 output: Description: unavailable
233 00:42:30.467104 output: Created: Sun Jun 16 01:42:30 2024
234 00:42:30.467151 output: Type: RAMDisk Image
235 00:42:30.467198 output: Compression: uncompressed
236 00:42:30.467246 output: Data Size: 52138269 Bytes = 50916.28 KiB = 49.72 MiB
237 00:42:30.467293 output: Architecture: AArch64
238 00:42:30.467357 output: OS: Linux
239 00:42:30.467407 output: Load Address: unavailable
240 00:42:30.467454 output: Entry Point: unavailable
241 00:42:30.467502 output: Hash algo: crc32
242 00:42:30.467549 output: Hash value: 00d270bd
243 00:42:30.467595 output: Default Configuration: 'conf-1'
244 00:42:30.467641 output: Configuration 0 (conf-1)
245 00:42:30.467688 output: Description: mt8192-asurada-spherion-r0
246 00:42:30.467734 output: Kernel: kernel-1
247 00:42:30.467781 output: Init Ramdisk: ramdisk-1
248 00:42:30.467829 output: FDT: fdt-1
249 00:42:30.467902 output: Loadables: kernel-1
250 00:42:30.467978 output:
251 00:42:30.468116 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
252 00:42:30.468202 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
253 00:42:30.468290 end: 1.5 prepare-tftp-overlay (duration 00:00:22) [common]
254 00:42:30.468370 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:37) [common]
255 00:42:30.468437 No LXC device requested
256 00:42:30.468510 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 00:42:30.468587 start: 1.7 deploy-device-env (timeout 00:09:37) [common]
258 00:42:30.468655 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 00:42:30.468717 Checking files for TFTP limit of 4294967296 bytes.
260 00:42:30.469153 end: 1 tftp-deploy (duration 00:00:23) [common]
261 00:42:30.469250 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 00:42:30.469331 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 00:42:30.469441 substitutions:
264 00:42:30.469503 - {DTB}: 14368387/tftp-deploy-2edglom8/dtb/mt8192-asurada-spherion-r0.dtb
265 00:42:30.469563 - {INITRD}: 14368387/tftp-deploy-2edglom8/ramdisk/ramdisk.cpio.gz
266 00:42:30.469616 - {KERNEL}: 14368387/tftp-deploy-2edglom8/kernel/Image
267 00:42:30.469667 - {LAVA_MAC}: None
268 00:42:30.469717 - {PRESEED_CONFIG}: None
269 00:42:30.469768 - {PRESEED_LOCAL}: None
270 00:42:30.469817 - {RAMDISK}: 14368387/tftp-deploy-2edglom8/ramdisk/ramdisk.cpio.gz
271 00:42:30.469872 - {ROOT_PART}: None
272 00:42:30.469923 - {ROOT}: None
273 00:42:30.469973 - {SERVER_IP}: 192.168.201.1
274 00:42:30.470021 - {TEE}: None
275 00:42:30.470071 Parsed boot commands:
276 00:42:30.470118 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 00:42:30.470306 Parsed boot commands: tftpboot 192.168.201.1 14368387/tftp-deploy-2edglom8/kernel/image.itb 14368387/tftp-deploy-2edglom8/kernel/cmdline
278 00:42:30.470388 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 00:42:30.470463 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 00:42:30.470542 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 00:42:30.470615 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 00:42:30.470674 Not connected, no need to disconnect.
283 00:42:30.470740 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 00:42:30.470812 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 00:42:30.470871 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-4'
286 00:42:30.474164 Setting prompt string to ['lava-test: # ']
287 00:42:30.474513 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 00:42:30.474604 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 00:42:30.474694 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 00:42:30.474771 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 00:42:30.474988 Calling: ['/usr/local/bin/chromebook-reboot.sh', 'mt8192-asurada-spherion-r0-cbg-4']
292 00:42:43.994207 Returned 0 in 13 seconds
293 00:42:44.094774 end: 2.2.2.1 pdu-reboot (duration 00:00:14) [common]
295 00:42:44.095094 end: 2.2.2 reset-device (duration 00:00:14) [common]
296 00:42:44.095207 start: 2.2.3 depthcharge-start (timeout 00:04:46) [common]
297 00:42:44.095308 Setting prompt string to 'Starting depthcharge on Spherion...'
298 00:42:44.095378 Changing prompt to 'Starting depthcharge on Spherion...'
299 00:42:44.095462 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
300 00:42:44.095970 [Enter `^Ec?' for help]
301 00:42:44.096072
302 00:42:44.096174
303 00:42:44.096273 F0: 102B 0000
304 00:42:44.096371
305 00:42:44.096468 F3: 1001 0000 [0200]
306 00:42:44.096565
307 00:42:44.096664 F3: 1001 0000
308 00:42:44.096760
309 00:42:44.096853 F7: 102D 0000
310 00:42:44.096946
311 00:42:44.097035 F1: 0000 0000
312 00:42:44.097125
313 00:42:44.097214 V0: 0000 0000 [0001]
314 00:42:44.097301
315 00:42:44.097388 00: 0007 8000
316 00:42:44.097477
317 00:42:44.097562 01: 0000 0000
318 00:42:44.097650
319 00:42:44.097734 BP: 0C00 0209 [0000]
320 00:42:44.097819
321 00:42:44.097903 G0: 1182 0000
322 00:42:44.097988
323 00:42:44.098072 EC: 0000 0021 [4000]
324 00:42:44.098157
325 00:42:44.098292 S7: 0000 0000 [0000]
326 00:42:44.098377
327 00:42:44.098462 CC: 0000 0000 [0001]
328 00:42:44.098564
329 00:42:44.098662 T0: 0000 0040 [010F]
330 00:42:44.098750
331 00:42:44.098834 Jump to BL
332 00:42:44.098919
333 00:42:44.099003
334 00:42:44.099088
335 00:42:44.099173 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
336 00:42:44.099262 ARM64: Exception handlers installed.
337 00:42:44.099348 ARM64: Testing exception
338 00:42:44.099433 ARM64: Done test exception
339 00:42:44.099519 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
340 00:42:44.099605 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
341 00:42:44.099694 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
342 00:42:44.099780 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
343 00:42:44.099866 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
344 00:42:44.099952 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
345 00:42:44.100038 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
346 00:42:44.100124 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
347 00:42:44.100209 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
348 00:42:44.100295 WDT: Last reset was cold boot
349 00:42:44.100380 SPI1(PAD0) initialized at 2873684 Hz
350 00:42:44.100465 SPI5(PAD0) initialized at 992727 Hz
351 00:42:44.100551 VBOOT: Loading verstage.
352 00:42:44.100636 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
353 00:42:44.100721 FMAP: Found "FLASH" version 1.1 at 0x20000.
354 00:42:44.100807 FMAP: base = 0x0 size = 0x800000 #areas = 25
355 00:42:44.100893 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
356 00:42:44.100978 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
357 00:42:44.101064 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
358 00:42:44.101150 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
359 00:42:44.101235
360 00:42:44.101319
361 00:42:44.101403 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
362 00:42:44.101489 ARM64: Exception handlers installed.
363 00:42:44.101574 ARM64: Testing exception
364 00:42:44.101659 ARM64: Done test exception
365 00:42:44.101744 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
366 00:42:44.101830 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
367 00:42:44.101916 Probing TPM: . done!
368 00:42:44.102001 TPM ready after 0 ms
369 00:42:44.102087 Connected to device vid:did:rid of 1ae0:0028:00
370 00:42:44.102172 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
371 00:42:44.102270 Initialized TPM device CR50 revision 0
372 00:42:44.102356 tlcl_send_startup: Startup return code is 0
373 00:42:44.102442 TPM: setup succeeded
374 00:42:44.102527 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
375 00:42:44.102613 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
376 00:42:44.102698 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
377 00:42:44.102783 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 00:42:44.102869 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
379 00:42:44.102955 in-header: 03 07 00 00 08 00 00 00
380 00:42:44.103040 in-data: aa e4 47 04 13 02 00 00
381 00:42:44.103125 Chrome EC: UHEPI supported
382 00:42:44.103209 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
383 00:42:44.103295 in-header: 03 a9 00 00 08 00 00 00
384 00:42:44.103379 in-data: 84 60 60 08 00 00 00 00
385 00:42:44.103464 Phase 1
386 00:42:44.103549 FMAP: area GBB found @ 3f5000 (12032 bytes)
387 00:42:44.103635 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
388 00:42:44.103720 VB2:vb2_check_recovery() Recovery was requested manually
389 00:42:44.103806 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x7
390 00:42:44.103891 Recovery requested (1009000e)
391 00:42:44.103976 TPM: Extending digest for VBOOT: boot mode into PCR 0
392 00:42:44.104062 tlcl_extend: response is 0
393 00:42:44.104148 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
394 00:42:44.104233 tlcl_extend: response is 0
395 00:42:44.104318 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
396 00:42:44.104404 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
397 00:42:44.104489 BS: bootblock times (exec / console): total (unknown) / 148 ms
398 00:42:44.104574
399 00:42:44.104658
400 00:42:44.104743 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
401 00:42:44.104828 ARM64: Exception handlers installed.
402 00:42:44.104913 ARM64: Testing exception
403 00:42:44.104998 ARM64: Done test exception
404 00:42:44.105083 pmic_efuse_setting: Set efuses in 11 msecs
405 00:42:44.105168 pmwrap_interface_init: Select PMIF_VLD_RDY
406 00:42:44.105253 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
407 00:42:44.105338 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
408 00:42:44.105621 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
409 00:42:44.105707 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
410 00:42:44.105793 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
411 00:42:44.105878 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
412 00:42:44.105963 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
413 00:42:44.106048 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
414 00:42:44.106133 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
415 00:42:44.106242 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
416 00:42:44.106342 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
417 00:42:44.106427 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
418 00:42:44.106512 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
419 00:42:44.106596 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
420 00:42:44.106682 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
421 00:42:44.106768 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
422 00:42:44.106853 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
423 00:42:44.106938 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
424 00:42:44.107023 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
425 00:42:44.107108 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
426 00:42:44.107193 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
427 00:42:44.107278 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
428 00:42:44.107363 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
429 00:42:44.107448 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
430 00:42:44.107533 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
431 00:42:44.107618 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
432 00:42:44.107703 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
433 00:42:44.107787 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
434 00:42:44.107872 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
435 00:42:44.107957 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
436 00:42:44.108042 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
437 00:42:44.108127 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
438 00:42:44.108212 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
439 00:42:44.108297 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
440 00:42:44.108381 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
441 00:42:44.108466 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
442 00:42:44.108551 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
443 00:42:44.108636 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
444 00:42:44.108720 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
445 00:42:44.108805 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
446 00:42:44.108889 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
447 00:42:44.108974 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
448 00:42:44.109058 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
449 00:42:44.109143 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
450 00:42:44.109227 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
451 00:42:44.109312 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
452 00:42:44.109397 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
453 00:42:44.109481 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
454 00:42:44.109566 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
455 00:42:44.109651 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
456 00:42:44.109735 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
457 00:42:44.109820 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x6b6d 0x5bf0 0x8100 0x4c 0xf0f 0x9248
458 00:42:44.109906 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
459 00:42:44.109991 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
460 00:42:44.110076 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
461 00:42:44.110162 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
462 00:42:44.110259 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
463 00:42:44.110345 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
464 00:42:44.110430 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 00:42:44.110515 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x4
466 00:42:44.110600 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
467 00:42:44.110685 [RTC]rtc_osc_init,62: osc32con val = 0xde70
468 00:42:44.110770 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
469 00:42:44.110855 [RTC]rtc_get_frequency_meter,154: input=15, output=765
470 00:42:44.110940 [RTC]rtc_get_frequency_meter,154: input=23, output=949
471 00:42:44.111024 [RTC]rtc_get_frequency_meter,154: input=19, output=856
472 00:42:44.111109 [RTC]rtc_get_frequency_meter,154: input=17, output=811
473 00:42:44.111194 [RTC]rtc_get_frequency_meter,154: input=16, output=788
474 00:42:44.111278 [RTC]rtc_get_frequency_meter,154: input=16, output=788
475 00:42:44.111363 [RTC]rtc_get_frequency_meter,154: input=17, output=811
476 00:42:44.111447 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
477 00:42:44.111532 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
478 00:42:44.111809 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
479 00:42:44.111895 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
480 00:42:44.111982 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
481 00:42:44.112067 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
482 00:42:44.112153 ADC[4]: Raw value=670432 ID=5
483 00:42:44.112238 ADC[3]: Raw value=212549 ID=1
484 00:42:44.112323 RAM Code: 0x51
485 00:42:44.112408 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
486 00:42:44.112494 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
487 00:42:44.112580 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-4GB' @0x75180 size 0x8 in mcache @0x00107f9c
488 00:42:44.112666 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
489 00:42:44.112751 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
490 00:42:44.112837 in-header: 03 07 00 00 08 00 00 00
491 00:42:44.112922 in-data: aa e4 47 04 13 02 00 00
492 00:42:44.113006 Chrome EC: UHEPI supported
493 00:42:44.113091 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
494 00:42:44.113176 in-header: 03 a9 00 00 08 00 00 00
495 00:42:44.113261 in-data: 84 60 60 08 00 00 00 00
496 00:42:44.113346 MRC: failed to locate region type 0.
497 00:42:44.113431 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
498 00:42:44.113515 DRAM-K: Running full calibration
499 00:42:44.113600 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
500 00:42:44.113685 header.status = 0x0
501 00:42:44.113769 header.version = 0x6 (expected: 0x6)
502 00:42:44.113854 header.size = 0xd00 (expected: 0xd00)
503 00:42:44.113939 header.flags = 0x0
504 00:42:44.114024 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
505 00:42:44.114140 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
506 00:42:44.114267 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
507 00:42:44.114354 dram_init: ddr_geometry: 0
508 00:42:44.114438 [EMI] MDL number = 0
509 00:42:44.114523 [EMI] Get MDL freq = 0
510 00:42:44.114608 dram_init: ddr_type: 0
511 00:42:44.114696 is_discrete_lpddr4: 1
512 00:42:44.114781 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
513 00:42:44.114866
514 00:42:44.114950
515 00:42:44.115035 [Bian_co] ETT version 0.0.0.1
516 00:42:44.115120 dram_type 6, R0 cbt_mode 0, R1 cbt_mode 0 VENDOR=6
517 00:42:44.115205
518 00:42:44.115289 dramc_set_vcore_voltage set vcore to 650000
519 00:42:44.115375 Read voltage for 800, 4
520 00:42:44.115459 Vio18 = 0
521 00:42:44.115544 Vcore = 650000
522 00:42:44.115629 Vdram = 0
523 00:42:44.115714 Vddq = 0
524 00:42:44.115798 Vmddr = 0
525 00:42:44.115882 dram_init: config_dvfs: 1
526 00:42:44.115968 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
527 00:42:44.116053 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
528 00:42:44.116139 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
529 00:42:44.116223 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
530 00:42:44.116309 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
531 00:42:44.116393 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
532 00:42:44.116478 MEM_TYPE=3, freq_sel=18
533 00:42:44.116563 sv_algorithm_assistance_LP4_1600
534 00:42:44.116648 ============ PULL DRAM RESETB DOWN ============
535 00:42:44.116738 ========== PULL DRAM RESETB DOWN end =========
536 00:42:44.116823 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
537 00:42:44.116908 ===================================
538 00:42:44.116993 LPDDR4 DRAM CONFIGURATION
539 00:42:44.117078 ===================================
540 00:42:44.117163 EX_ROW_EN[0] = 0x0
541 00:42:44.117248 EX_ROW_EN[1] = 0x0
542 00:42:44.117332 LP4Y_EN = 0x0
543 00:42:44.117417 WORK_FSP = 0x0
544 00:42:44.117501 WL = 0x2
545 00:42:44.117585 RL = 0x2
546 00:42:44.117670 BL = 0x2
547 00:42:44.117755 RPST = 0x0
548 00:42:44.117840 RD_PRE = 0x0
549 00:42:44.117924 WR_PRE = 0x1
550 00:42:44.118008 WR_PST = 0x0
551 00:42:44.118093 DBI_WR = 0x0
552 00:42:44.118177 DBI_RD = 0x0
553 00:42:44.118272 OTF = 0x1
554 00:42:44.118358 ===================================
555 00:42:44.118444 ===================================
556 00:42:44.118529 ANA top config
557 00:42:44.118613 ===================================
558 00:42:44.118698 DLL_ASYNC_EN = 0
559 00:42:44.118783 ALL_SLAVE_EN = 1
560 00:42:44.118867 NEW_RANK_MODE = 1
561 00:42:44.118953 DLL_IDLE_MODE = 1
562 00:42:44.119037 LP45_APHY_COMB_EN = 1
563 00:42:44.119122 TX_ODT_DIS = 1
564 00:42:44.119207 NEW_8X_MODE = 1
565 00:42:44.119292 ===================================
566 00:42:44.119377 ===================================
567 00:42:44.119462 data_rate = 1600
568 00:42:44.119547 CKR = 1
569 00:42:44.119631 DQ_P2S_RATIO = 8
570 00:42:44.119715 ===================================
571 00:42:44.119800 CA_P2S_RATIO = 8
572 00:42:44.119884 DQ_CA_OPEN = 0
573 00:42:44.119968 DQ_SEMI_OPEN = 0
574 00:42:44.120052 CA_SEMI_OPEN = 0
575 00:42:44.120137 CA_FULL_RATE = 0
576 00:42:44.120221 DQ_CKDIV4_EN = 1
577 00:42:44.120305 CA_CKDIV4_EN = 1
578 00:42:44.120389 CA_PREDIV_EN = 0
579 00:42:44.120473 PH8_DLY = 0
580 00:42:44.120557 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
581 00:42:44.120641 DQ_AAMCK_DIV = 4
582 00:42:44.120726 CA_AAMCK_DIV = 4
583 00:42:44.120809 CA_ADMCK_DIV = 4
584 00:42:44.120893 DQ_TRACK_CA_EN = 0
585 00:42:44.120978 CA_PICK = 800
586 00:42:44.121062 CA_MCKIO = 800
587 00:42:44.121146 MCKIO_SEMI = 0
588 00:42:44.121229 PLL_FREQ = 3068
589 00:42:44.121315 DQ_UI_PI_RATIO = 32
590 00:42:44.121399 CA_UI_PI_RATIO = 0
591 00:42:44.121484 ===================================
592 00:42:44.121569 ===================================
593 00:42:44.121654 memory_type:LPDDR4
594 00:42:44.121739 GP_NUM : 10
595 00:42:44.121823 SRAM_EN : 1
596 00:42:44.121908 MD32_EN : 0
597 00:42:44.121992 ===================================
598 00:42:44.122278 [ANA_INIT] >>>>>>>>>>>>>>
599 00:42:44.122364 <<<<<< [CONFIGURE PHASE]: ANA_TX
600 00:42:44.122457 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
601 00:42:44.122542 ===================================
602 00:42:44.122628 data_rate = 1600,PCW = 0X7600
603 00:42:44.122714 ===================================
604 00:42:44.122799 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
605 00:42:44.122885 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
606 00:42:44.122971 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 00:42:44.123056 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
608 00:42:44.123142 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
609 00:42:44.123227 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
610 00:42:44.123312 [ANA_INIT] flow start
611 00:42:44.123397 [ANA_INIT] PLL >>>>>>>>
612 00:42:44.123482 [ANA_INIT] PLL <<<<<<<<
613 00:42:44.123566 [ANA_INIT] MIDPI >>>>>>>>
614 00:42:44.123650 [ANA_INIT] MIDPI <<<<<<<<
615 00:42:44.123734 [ANA_INIT] DLL >>>>>>>>
616 00:42:44.123818 [ANA_INIT] flow end
617 00:42:44.123903 ============ LP4 DIFF to SE enter ============
618 00:42:44.123988 ============ LP4 DIFF to SE exit ============
619 00:42:44.124074 [ANA_INIT] <<<<<<<<<<<<<
620 00:42:44.124158 [Flow] Enable top DCM control >>>>>
621 00:42:44.124243 [Flow] Enable top DCM control <<<<<
622 00:42:44.124328 Enable DLL master slave shuffle
623 00:42:44.124413 ==============================================================
624 00:42:44.124498 Gating Mode config
625 00:42:44.124583 ==============================================================
626 00:42:44.124667 Config description:
627 00:42:44.124752 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
628 00:42:44.124838 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
629 00:42:44.124923 SELPH_MODE 0: By rank 1: By Phase
630 00:42:44.125008 ==============================================================
631 00:42:44.125094 GAT_TRACK_EN = 1
632 00:42:44.125179 RX_GATING_MODE = 2
633 00:42:44.125263 RX_GATING_TRACK_MODE = 2
634 00:42:44.125348 SELPH_MODE = 1
635 00:42:44.125432 PICG_EARLY_EN = 1
636 00:42:44.125516 VALID_LAT_VALUE = 1
637 00:42:44.125601 ==============================================================
638 00:42:44.125686 Enter into Gating configuration >>>>
639 00:42:44.125771 Exit from Gating configuration <<<<
640 00:42:44.125856 Enter into DVFS_PRE_config >>>>>
641 00:42:44.125941 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
642 00:42:44.126031 Exit from DVFS_PRE_config <<<<<
643 00:42:44.126116 Enter into PICG configuration >>>>
644 00:42:44.126200 Exit from PICG configuration <<<<
645 00:42:44.126328 [RX_INPUT] configuration >>>>>
646 00:42:44.126412 [RX_INPUT] configuration <<<<<
647 00:42:44.126497 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
648 00:42:44.126583 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
649 00:42:44.126668 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
650 00:42:44.126753 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
651 00:42:44.126837 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
652 00:42:44.126922 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
653 00:42:44.127007 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
654 00:42:44.127092 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
655 00:42:44.127176 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
656 00:42:44.127261 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
657 00:42:44.127345 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
658 00:42:44.127430 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
659 00:42:44.127514 ===================================
660 00:42:44.127599 LPDDR4 DRAM CONFIGURATION
661 00:42:44.127684 ===================================
662 00:42:44.127768 EX_ROW_EN[0] = 0x0
663 00:42:44.127853 EX_ROW_EN[1] = 0x0
664 00:42:44.127937 LP4Y_EN = 0x0
665 00:42:44.128021 WORK_FSP = 0x0
666 00:42:44.128105 WL = 0x2
667 00:42:44.128189 RL = 0x2
668 00:42:44.128273 BL = 0x2
669 00:42:44.128356 RPST = 0x0
670 00:42:44.128441 RD_PRE = 0x0
671 00:42:44.128524 WR_PRE = 0x1
672 00:42:44.128608 WR_PST = 0x0
673 00:42:44.128693 DBI_WR = 0x0
674 00:42:44.128778 DBI_RD = 0x0
675 00:42:44.128862 OTF = 0x1
676 00:42:44.128947 ===================================
677 00:42:44.129032 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
678 00:42:44.129116 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
679 00:42:44.129201 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
680 00:42:44.129286 ===================================
681 00:42:44.129371 LPDDR4 DRAM CONFIGURATION
682 00:42:44.129455 ===================================
683 00:42:44.129540 EX_ROW_EN[0] = 0x10
684 00:42:44.129624 EX_ROW_EN[1] = 0x0
685 00:42:44.129708 LP4Y_EN = 0x0
686 00:42:44.129792 WORK_FSP = 0x0
687 00:42:44.129876 WL = 0x2
688 00:42:44.129960 RL = 0x2
689 00:42:44.130044 BL = 0x2
690 00:42:44.130129 RPST = 0x0
691 00:42:44.130216 RD_PRE = 0x0
692 00:42:44.130302 WR_PRE = 0x1
693 00:42:44.130386 WR_PST = 0x0
694 00:42:44.130471 DBI_WR = 0x0
695 00:42:44.130555 DBI_RD = 0x0
696 00:42:44.130639 OTF = 0x1
697 00:42:44.130724 ===================================
698 00:42:44.130809 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
699 00:42:44.130894 nWR fixed to 40
700 00:42:44.130979 [ModeRegInit_LP4] CH0 RK0
701 00:42:44.131063 [ModeRegInit_LP4] CH0 RK1
702 00:42:44.131148 [ModeRegInit_LP4] CH1 RK0
703 00:42:44.131231 [ModeRegInit_LP4] CH1 RK1
704 00:42:44.131315 match AC timing 12
705 00:42:44.131400 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 0
706 00:42:44.131485 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
707 00:42:44.131772 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
708 00:42:44.131858 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
709 00:42:44.131945 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
710 00:42:44.132031 [EMI DOE] emi_dcm 0
711 00:42:44.132117 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
712 00:42:44.132201 ==
713 00:42:44.132287 Dram Type= 6, Freq= 0, CH_0, rank 0
714 00:42:44.132372 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
715 00:42:44.132458 ==
716 00:42:44.132543 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
717 00:42:44.132628 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
718 00:42:44.132714 [CA 0] Center 37 (7~68) winsize 62
719 00:42:44.132799 [CA 1] Center 37 (7~68) winsize 62
720 00:42:44.132884 [CA 2] Center 35 (5~66) winsize 62
721 00:42:44.132968 [CA 3] Center 35 (4~66) winsize 63
722 00:42:44.133053 [CA 4] Center 34 (4~65) winsize 62
723 00:42:44.133137 [CA 5] Center 34 (4~64) winsize 61
724 00:42:44.133222
725 00:42:44.133307 [CmdBusTrainingLP45] Vref(ca) range 1: 32
726 00:42:44.133392
727 00:42:44.133476 [CATrainingPosCal] consider 1 rank data
728 00:42:44.133561 u2DelayCellTimex100 = 270/100 ps
729 00:42:44.133646 CA0 delay=37 (7~68),Diff = 3 PI (21 cell)
730 00:42:44.133731 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
731 00:42:44.133816 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
732 00:42:44.133901 CA3 delay=35 (4~66),Diff = 1 PI (7 cell)
733 00:42:44.133985 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
734 00:42:44.134070 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
735 00:42:44.134154
736 00:42:44.134246 CA PerBit enable=1, Macro0, CA PI delay=34
737 00:42:44.134331
738 00:42:44.134416 [CBTSetCACLKResult] CA Dly = 34
739 00:42:44.134501 CS Dly: 6 (0~37)
740 00:42:44.134585 ==
741 00:42:44.134670 Dram Type= 6, Freq= 0, CH_0, rank 1
742 00:42:44.134754 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
743 00:42:44.134840 ==
744 00:42:44.134925 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
745 00:42:44.135011 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
746 00:42:44.135095 [CA 0] Center 37 (7~68) winsize 62
747 00:42:44.135180 [CA 1] Center 37 (6~68) winsize 63
748 00:42:44.135265 [CA 2] Center 35 (4~66) winsize 63
749 00:42:44.135350 [CA 3] Center 34 (4~65) winsize 62
750 00:42:44.135435 [CA 4] Center 33 (3~64) winsize 62
751 00:42:44.135519 [CA 5] Center 33 (3~64) winsize 62
752 00:42:44.135603
753 00:42:44.135687 [CmdBusTrainingLP45] Vref(ca) range 1: 34
754 00:42:44.135772
755 00:42:44.135856 [CATrainingPosCal] consider 2 rank data
756 00:42:44.135941 u2DelayCellTimex100 = 270/100 ps
757 00:42:44.136027 CA0 delay=37 (7~68),Diff = 3 PI (21 cell)
758 00:42:44.136112 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
759 00:42:44.136198 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
760 00:42:44.136282 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
761 00:42:44.136367 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
762 00:42:44.136452 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
763 00:42:44.136536
764 00:42:44.136620 CA PerBit enable=1, Macro0, CA PI delay=34
765 00:42:44.136706
766 00:42:44.136790 [CBTSetCACLKResult] CA Dly = 34
767 00:42:44.136874 CS Dly: 6 (0~38)
768 00:42:44.136959
769 00:42:44.137043 ----->DramcWriteLeveling(PI) begin...
770 00:42:44.137129 ==
771 00:42:44.137215 Dram Type= 6, Freq= 0, CH_0, rank 0
772 00:42:44.137300 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
773 00:42:44.137385 ==
774 00:42:44.137470 Write leveling (Byte 0): 27 => 27
775 00:42:44.137555 Write leveling (Byte 1): 27 => 27
776 00:42:44.137640 DramcWriteLeveling(PI) end<-----
777 00:42:44.137725
778 00:42:44.137809 ==
779 00:42:44.137894 Dram Type= 6, Freq= 0, CH_0, rank 0
780 00:42:44.137979 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
781 00:42:44.138064 ==
782 00:42:44.138148 [Gating] SW mode calibration
783 00:42:44.138238 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
784 00:42:44.138324 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
785 00:42:44.138410 0 6 0 | B1->B0 | 3232 3131 | 0 0 | (0 1) (0 1)
786 00:42:44.138495 0 6 4 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
787 00:42:44.138580 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
788 00:42:44.138665 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 00:42:44.138750 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 00:42:44.138835 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 00:42:44.138920 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 00:42:44.139004 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 00:42:44.139089 0 7 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
794 00:42:44.139173 0 7 4 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
795 00:42:44.139258 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
796 00:42:44.139342 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
797 00:42:44.139427 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
798 00:42:44.139511 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
799 00:42:44.139596 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
800 00:42:44.139682 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
801 00:42:44.139767 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
802 00:42:44.139853 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
803 00:42:44.139938 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
804 00:42:44.140023 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
805 00:42:44.140107 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
806 00:42:44.140192 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
807 00:42:44.140277 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
808 00:42:44.140362 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
809 00:42:44.140446 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
810 00:42:44.140531 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
811 00:42:44.140616 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
812 00:42:44.140701 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
813 00:42:44.140786 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
814 00:42:44.140870 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
815 00:42:44.141163 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
816 00:42:44.141248 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
817 00:42:44.141335 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
818 00:42:44.141420 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
819 00:42:44.141505 Total UI for P1: 0, mck2ui 16
820 00:42:44.141591 best dqsien dly found for B1: ( 0, 10, 0)
821 00:42:44.141677 0 10 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
822 00:42:44.141762 Total UI for P1: 0, mck2ui 16
823 00:42:44.141847 best dqsien dly found for B0: ( 0, 10, 2)
824 00:42:44.141934 best DQS0 dly(MCK, UI, PI) = (0, 10, 2)
825 00:42:44.142019 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
826 00:42:44.142103
827 00:42:44.142189 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 2)
828 00:42:44.142317 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
829 00:42:44.142402 [Gating] SW calibration Done
830 00:42:44.142487 ==
831 00:42:44.142572 Dram Type= 6, Freq= 0, CH_0, rank 0
832 00:42:44.142657 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
833 00:42:44.142742 ==
834 00:42:44.142827 RX Vref Scan: 0
835 00:42:44.142912
836 00:42:44.142996 RX Vref 0 -> 0, step: 1
837 00:42:44.143080
838 00:42:44.143165 RX Delay -130 -> 252, step: 16
839 00:42:44.143250 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
840 00:42:44.143335 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
841 00:42:44.143421 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
842 00:42:44.143506 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
843 00:42:44.143591 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
844 00:42:44.143676 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
845 00:42:44.143766 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
846 00:42:44.143852 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
847 00:42:44.143937 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
848 00:42:44.144022 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
849 00:42:44.144107 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
850 00:42:44.144192 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
851 00:42:44.144277 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
852 00:42:44.144362 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
853 00:42:44.144446 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
854 00:42:44.144531 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
855 00:42:44.144616 ==
856 00:42:44.144701 Dram Type= 6, Freq= 0, CH_0, rank 0
857 00:42:44.144786 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
858 00:42:44.144871 ==
859 00:42:44.144955 DQS Delay:
860 00:42:44.145039 DQS0 = 0, DQS1 = 0
861 00:42:44.145124 DQM Delay:
862 00:42:44.145209 DQM0 = 88, DQM1 = 74
863 00:42:44.145294 DQ Delay:
864 00:42:44.145379 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
865 00:42:44.145463 DQ4 =85, DQ5 =77, DQ6 =101, DQ7 =101
866 00:42:44.145547 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =69
867 00:42:44.145632 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
868 00:42:44.145715
869 00:42:44.145799
870 00:42:44.145883 ==
871 00:42:44.145968 Dram Type= 6, Freq= 0, CH_0, rank 0
872 00:42:44.146053 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
873 00:42:44.146138 ==
874 00:42:44.146245
875 00:42:44.146343
876 00:42:44.146427 TX Vref Scan disable
877 00:42:44.146513 == TX Byte 0 ==
878 00:42:44.146597 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
879 00:42:44.146685 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
880 00:42:44.146770 == TX Byte 1 ==
881 00:42:44.146854 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
882 00:42:44.146939 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
883 00:42:44.147024 ==
884 00:42:44.147109 Dram Type= 6, Freq= 0, CH_0, rank 0
885 00:42:44.147194 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
886 00:42:44.147280 ==
887 00:42:44.147365 TX Vref=22, minBit 2, minWin=27, winSum=444
888 00:42:44.147451 TX Vref=24, minBit 2, minWin=27, winSum=446
889 00:42:44.147536 TX Vref=26, minBit 11, minWin=27, winSum=447
890 00:42:44.147621 TX Vref=28, minBit 4, minWin=27, winSum=449
891 00:42:44.147706 TX Vref=30, minBit 11, minWin=27, winSum=451
892 00:42:44.147791 TX Vref=32, minBit 0, minWin=27, winSum=449
893 00:42:44.147876 [TxChooseVref] Worse bit 11, Min win 27, Win sum 451, Final Vref 30
894 00:42:44.147961
895 00:42:44.148046 Final TX Range 1 Vref 30
896 00:42:44.148131
897 00:42:44.148216 ==
898 00:42:44.148300 Dram Type= 6, Freq= 0, CH_0, rank 0
899 00:42:44.148385 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
900 00:42:44.148470 ==
901 00:42:44.148554
902 00:42:44.148638
903 00:42:44.148722 TX Vref Scan disable
904 00:42:44.148806 == TX Byte 0 ==
905 00:42:44.148890 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
906 00:42:44.148975 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
907 00:42:44.149059 == TX Byte 1 ==
908 00:42:44.149142 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
909 00:42:44.149227 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
910 00:42:44.149310
911 00:42:44.149395 [DATLAT]
912 00:42:44.149479 Freq=800, CH0 RK0
913 00:42:44.149564
914 00:42:44.149648 DATLAT Default: 0xa
915 00:42:44.149732 0, 0xFFFF, sum = 0
916 00:42:44.149819 1, 0xFFFF, sum = 0
917 00:42:44.149906 2, 0xFFFF, sum = 0
918 00:42:44.149992 3, 0xFFFF, sum = 0
919 00:42:44.150079 4, 0xFFFF, sum = 0
920 00:42:44.150165 5, 0xFFFF, sum = 0
921 00:42:44.150292 6, 0xFFFF, sum = 0
922 00:42:44.150378 7, 0xFFFF, sum = 0
923 00:42:44.150464 8, 0x0, sum = 1
924 00:42:44.150550 9, 0x0, sum = 2
925 00:42:44.150637 10, 0x0, sum = 3
926 00:42:44.150724 11, 0x0, sum = 4
927 00:42:44.150811 best_step = 9
928 00:42:44.150895
929 00:42:44.150980 ==
930 00:42:44.151064 Dram Type= 6, Freq= 0, CH_0, rank 0
931 00:42:44.151150 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
932 00:42:44.151235 ==
933 00:42:44.151320 RX Vref Scan: 1
934 00:42:44.151404
935 00:42:44.151489 Set Vref Range= 32 -> 127
936 00:42:44.151573
937 00:42:44.151657 RX Vref 32 -> 127, step: 1
938 00:42:44.151742
939 00:42:44.151850 RX Delay -111 -> 252, step: 8
940 00:42:44.151949
941 00:42:44.152033 Set Vref, RX VrefLevel [Byte0]: 32
942 00:42:44.152118 [Byte1]: 32
943 00:42:44.152203
944 00:42:44.152288 Set Vref, RX VrefLevel [Byte0]: 33
945 00:42:44.152373 [Byte1]: 33
946 00:42:44.152457
947 00:42:44.152542 Set Vref, RX VrefLevel [Byte0]: 34
948 00:42:44.152627 [Byte1]: 34
949 00:42:44.152712
950 00:42:44.152796 Set Vref, RX VrefLevel [Byte0]: 35
951 00:42:44.152881 [Byte1]: 35
952 00:42:44.152965
953 00:42:44.153050 Set Vref, RX VrefLevel [Byte0]: 36
954 00:42:44.153134 [Byte1]: 36
955 00:42:44.153219
956 00:42:44.153303 Set Vref, RX VrefLevel [Byte0]: 37
957 00:42:44.153388 [Byte1]: 37
958 00:42:44.153472
959 00:42:44.153556 Set Vref, RX VrefLevel [Byte0]: 38
960 00:42:44.153641 [Byte1]: 38
961 00:42:44.153725
962 00:42:44.153809 Set Vref, RX VrefLevel [Byte0]: 39
963 00:42:44.154133 [Byte1]: 39
964 00:42:44.154242
965 00:42:44.154342 Set Vref, RX VrefLevel [Byte0]: 40
966 00:42:44.154428 [Byte1]: 40
967 00:42:44.154514
968 00:42:44.154599 Set Vref, RX VrefLevel [Byte0]: 41
969 00:42:44.154685 [Byte1]: 41
970 00:42:44.154770
971 00:42:44.154854 Set Vref, RX VrefLevel [Byte0]: 42
972 00:42:44.154939 [Byte1]: 42
973 00:42:44.155024
974 00:42:44.155109 Set Vref, RX VrefLevel [Byte0]: 43
975 00:42:44.155194 [Byte1]: 43
976 00:42:44.155278
977 00:42:44.155363 Set Vref, RX VrefLevel [Byte0]: 44
978 00:42:44.155448 [Byte1]: 44
979 00:42:44.155532
980 00:42:44.155616 Set Vref, RX VrefLevel [Byte0]: 45
981 00:42:44.155704 [Byte1]: 45
982 00:42:44.155787
983 00:42:44.155865 Set Vref, RX VrefLevel [Byte0]: 46
984 00:42:44.155942 [Byte1]: 46
985 00:42:44.156019
986 00:42:44.156095 Set Vref, RX VrefLevel [Byte0]: 47
987 00:42:44.156172 [Byte1]: 47
988 00:42:44.156248
989 00:42:44.156327 Set Vref, RX VrefLevel [Byte0]: 48
990 00:42:44.156406 [Byte1]: 48
991 00:42:44.156482
992 00:42:44.156558 Set Vref, RX VrefLevel [Byte0]: 49
993 00:42:44.156635 [Byte1]: 49
994 00:42:44.156711
995 00:42:44.156788 Set Vref, RX VrefLevel [Byte0]: 50
996 00:42:44.156865 [Byte1]: 50
997 00:42:44.156941
998 00:42:44.157017 Set Vref, RX VrefLevel [Byte0]: 51
999 00:42:44.157094 [Byte1]: 51
1000 00:42:44.157170
1001 00:42:44.157247 Set Vref, RX VrefLevel [Byte0]: 52
1002 00:42:44.157323 [Byte1]: 52
1003 00:42:44.157400
1004 00:42:44.157476 Set Vref, RX VrefLevel [Byte0]: 53
1005 00:42:44.157553 [Byte1]: 53
1006 00:42:44.157629
1007 00:42:44.157706 Set Vref, RX VrefLevel [Byte0]: 54
1008 00:42:44.157783 [Byte1]: 54
1009 00:42:44.157859
1010 00:42:44.157936 Set Vref, RX VrefLevel [Byte0]: 55
1011 00:42:44.158013 [Byte1]: 55
1012 00:42:44.158089
1013 00:42:44.158168 Set Vref, RX VrefLevel [Byte0]: 56
1014 00:42:44.158269 [Byte1]: 56
1015 00:42:44.158352
1016 00:42:44.158419 Set Vref, RX VrefLevel [Byte0]: 57
1017 00:42:44.158487 [Byte1]: 57
1018 00:42:44.158553
1019 00:42:44.158620 Set Vref, RX VrefLevel [Byte0]: 58
1020 00:42:44.158704 [Byte1]: 58
1021 00:42:44.158789
1022 00:42:44.158876 Set Vref, RX VrefLevel [Byte0]: 59
1023 00:42:44.158962 [Byte1]: 59
1024 00:42:44.159047
1025 00:42:44.159132 Set Vref, RX VrefLevel [Byte0]: 60
1026 00:42:44.159218 [Byte1]: 60
1027 00:42:44.159302
1028 00:42:44.159387 Set Vref, RX VrefLevel [Byte0]: 61
1029 00:42:44.159472 [Byte1]: 61
1030 00:42:44.159556
1031 00:42:44.159641 Set Vref, RX VrefLevel [Byte0]: 62
1032 00:42:44.159725 [Byte1]: 62
1033 00:42:44.159827
1034 00:42:44.159925 Set Vref, RX VrefLevel [Byte0]: 63
1035 00:42:44.160011 [Byte1]: 63
1036 00:42:44.160095
1037 00:42:44.160179 Set Vref, RX VrefLevel [Byte0]: 64
1038 00:42:44.160264 [Byte1]: 64
1039 00:42:44.160349
1040 00:42:44.160433 Set Vref, RX VrefLevel [Byte0]: 65
1041 00:42:44.160518 [Byte1]: 65
1042 00:42:44.160602
1043 00:42:44.160686 Set Vref, RX VrefLevel [Byte0]: 66
1044 00:42:44.160770 [Byte1]: 66
1045 00:42:44.160854
1046 00:42:44.160939 Set Vref, RX VrefLevel [Byte0]: 67
1047 00:42:44.161024 [Byte1]: 67
1048 00:42:44.161108
1049 00:42:44.161192 Set Vref, RX VrefLevel [Byte0]: 68
1050 00:42:44.161277 [Byte1]: 68
1051 00:42:44.161361
1052 00:42:44.161446 Set Vref, RX VrefLevel [Byte0]: 69
1053 00:42:44.161530 [Byte1]: 69
1054 00:42:44.161614
1055 00:42:44.161699 Set Vref, RX VrefLevel [Byte0]: 70
1056 00:42:44.161783 [Byte1]: 70
1057 00:42:44.161931
1058 00:42:44.162015 Set Vref, RX VrefLevel [Byte0]: 71
1059 00:42:44.162100 [Byte1]: 71
1060 00:42:44.162184
1061 00:42:44.162309 Set Vref, RX VrefLevel [Byte0]: 72
1062 00:42:44.162394 [Byte1]: 72
1063 00:42:44.162478
1064 00:42:44.162562 Set Vref, RX VrefLevel [Byte0]: 73
1065 00:42:44.162647 [Byte1]: 73
1066 00:42:44.162731
1067 00:42:44.162815 Set Vref, RX VrefLevel [Byte0]: 74
1068 00:42:44.162899 [Byte1]: 74
1069 00:42:44.162983
1070 00:42:44.163067 Set Vref, RX VrefLevel [Byte0]: 75
1071 00:42:44.163151 [Byte1]: 75
1072 00:42:44.163235
1073 00:42:44.163319 Set Vref, RX VrefLevel [Byte0]: 76
1074 00:42:44.163403 [Byte1]: 76
1075 00:42:44.163487
1076 00:42:44.163571 Final RX Vref Byte 0 = 50 to rank0
1077 00:42:44.163655 Final RX Vref Byte 1 = 49 to rank0
1078 00:42:44.163740 Final RX Vref Byte 0 = 50 to rank1
1079 00:42:44.163825 Final RX Vref Byte 1 = 49 to rank1==
1080 00:42:44.163909 Dram Type= 6, Freq= 0, CH_0, rank 0
1081 00:42:44.163994 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1082 00:42:44.164078 ==
1083 00:42:44.164163 DQS Delay:
1084 00:42:44.164247 DQS0 = 0, DQS1 = 0
1085 00:42:44.164331 DQM Delay:
1086 00:42:44.164416 DQM0 = 84, DQM1 = 73
1087 00:42:44.164500 DQ Delay:
1088 00:42:44.164584 DQ0 =80, DQ1 =84, DQ2 =84, DQ3 =80
1089 00:42:44.164668 DQ4 =88, DQ5 =72, DQ6 =92, DQ7 =92
1090 00:42:44.164752 DQ8 =64, DQ9 =56, DQ10 =72, DQ11 =64
1091 00:42:44.164837 DQ12 =80, DQ13 =84, DQ14 =84, DQ15 =84
1092 00:42:44.164920
1093 00:42:44.165005
1094 00:42:44.165090 [DQSOSCAuto] RK0, (LSB)MR18= 0x3a3a, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 395 ps
1095 00:42:44.165175 CH0 RK0: MR19=606, MR18=3A3A
1096 00:42:44.165261 CH0_RK0: MR19=0x606, MR18=0x3A3A, DQSOSC=395, MR23=63, INC=94, DEC=63
1097 00:42:44.165345
1098 00:42:44.165430 ----->DramcWriteLeveling(PI) begin...
1099 00:42:44.165517 ==
1100 00:42:44.165601 Dram Type= 6, Freq= 0, CH_0, rank 1
1101 00:42:44.165686 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1102 00:42:44.165772 ==
1103 00:42:44.165856 Write leveling (Byte 0): 30 => 30
1104 00:42:44.165941 Write leveling (Byte 1): 29 => 29
1105 00:42:44.166025 DramcWriteLeveling(PI) end<-----
1106 00:42:44.166109
1107 00:42:44.166193 ==
1108 00:42:44.166318 Dram Type= 6, Freq= 0, CH_0, rank 1
1109 00:42:44.166403 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1110 00:42:44.166488 ==
1111 00:42:44.166572 [Gating] SW mode calibration
1112 00:42:44.166657 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1113 00:42:44.166743 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1114 00:42:44.166828 0 6 0 | B1->B0 | 3333 3030 | 0 0 | (0 0) (0 0)
1115 00:42:44.167116 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1116 00:42:44.167202 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1117 00:42:44.167288 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1118 00:42:44.167374 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1119 00:42:44.167459 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1120 00:42:44.167543 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1121 00:42:44.167629 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1122 00:42:44.167714 0 7 0 | B1->B0 | 2b2b 2f2f | 0 0 | (0 0) (0 0)
1123 00:42:44.167799 0 7 4 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
1124 00:42:44.167922 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1125 00:42:44.168007 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1126 00:42:44.168091 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1127 00:42:44.168176 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1128 00:42:44.168261 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1129 00:42:44.168346 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1130 00:42:44.168430 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1131 00:42:44.168515 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1132 00:42:44.168600 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1133 00:42:44.168684 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1134 00:42:44.168768 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1135 00:42:44.168853 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1136 00:42:44.168938 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1137 00:42:44.169022 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1138 00:42:44.169107 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1139 00:42:44.169191 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1140 00:42:44.169276 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1141 00:42:44.169360 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1142 00:42:44.169445 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1143 00:42:44.169529 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1144 00:42:44.169613 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1145 00:42:44.169698 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1146 00:42:44.169782 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1147 00:42:44.169867 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1148 00:42:44.169951 Total UI for P1: 0, mck2ui 16
1149 00:42:44.170036 best dqsien dly found for B0: ( 0, 10, 0)
1150 00:42:44.170121 Total UI for P1: 0, mck2ui 16
1151 00:42:44.170206 best dqsien dly found for B1: ( 0, 10, 0)
1152 00:42:44.170334 best DQS0 dly(MCK, UI, PI) = (0, 10, 0)
1153 00:42:44.170419 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
1154 00:42:44.170504
1155 00:42:44.170589 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 0)
1156 00:42:44.170674 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
1157 00:42:44.170758 [Gating] SW calibration Done
1158 00:42:44.170843 ==
1159 00:42:44.170928 Dram Type= 6, Freq= 0, CH_0, rank 1
1160 00:42:44.171012 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1161 00:42:44.171097 ==
1162 00:42:44.171182 RX Vref Scan: 0
1163 00:42:44.171267
1164 00:42:44.171352 RX Vref 0 -> 0, step: 1
1165 00:42:44.171437
1166 00:42:44.171521 RX Delay -130 -> 252, step: 16
1167 00:42:44.171606 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1168 00:42:44.171692 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1169 00:42:44.171778 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1170 00:42:44.171864 iDelay=222, Bit 3, Center 77 (-34 ~ 189) 224
1171 00:42:44.171948 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1172 00:42:44.172032 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1173 00:42:44.172117 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1174 00:42:44.172202 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1175 00:42:44.172286 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
1176 00:42:44.172370 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1177 00:42:44.172456 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1178 00:42:44.172541 iDelay=222, Bit 11, Center 61 (-50 ~ 173) 224
1179 00:42:44.172626 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
1180 00:42:44.172710 iDelay=222, Bit 13, Center 77 (-34 ~ 189) 224
1181 00:42:44.172795 iDelay=222, Bit 14, Center 77 (-34 ~ 189) 224
1182 00:42:44.172879 iDelay=222, Bit 15, Center 77 (-34 ~ 189) 224
1183 00:42:44.172964 ==
1184 00:42:44.173049 Dram Type= 6, Freq= 0, CH_0, rank 1
1185 00:42:44.173134 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1186 00:42:44.173219 ==
1187 00:42:44.173304 DQS Delay:
1188 00:42:44.173388 DQS0 = 0, DQS1 = 0
1189 00:42:44.173473 DQM Delay:
1190 00:42:44.173557 DQM0 = 83, DQM1 = 69
1191 00:42:44.173642 DQ Delay:
1192 00:42:44.173726 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =77
1193 00:42:44.173838 DQ4 =85, DQ5 =69, DQ6 =85, DQ7 =93
1194 00:42:44.173954 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
1195 00:42:44.174045 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1196 00:42:44.174162
1197 00:42:44.174263
1198 00:42:44.174340 ==
1199 00:42:44.174455 Dram Type= 6, Freq= 0, CH_0, rank 1
1200 00:42:44.174532 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1201 00:42:44.174609 ==
1202 00:42:44.174688
1203 00:42:44.174811
1204 00:42:44.174901 TX Vref Scan disable
1205 00:42:44.175007 == TX Byte 0 ==
1206 00:42:44.175085 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1207 00:42:44.175163 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1208 00:42:44.175240 == TX Byte 1 ==
1209 00:42:44.175317 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1210 00:42:44.175394 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1211 00:42:44.175474 ==
1212 00:42:44.175552 Dram Type= 6, Freq= 0, CH_0, rank 1
1213 00:42:44.175629 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1214 00:42:44.175706 ==
1215 00:42:44.175785 TX Vref=22, minBit 0, minWin=27, winSum=448
1216 00:42:44.175953 TX Vref=24, minBit 0, minWin=28, winSum=453
1217 00:42:44.176059 TX Vref=26, minBit 2, minWin=28, winSum=457
1218 00:42:44.176153 TX Vref=28, minBit 2, minWin=28, winSum=457
1219 00:42:44.176238 TX Vref=30, minBit 2, minWin=28, winSum=458
1220 00:42:44.176317 TX Vref=32, minBit 2, minWin=28, winSum=459
1221 00:42:44.176397 [TxChooseVref] Worse bit 2, Min win 28, Win sum 459, Final Vref 32
1222 00:42:44.176477
1223 00:42:44.176591 Final TX Range 1 Vref 32
1224 00:42:44.176683
1225 00:42:44.176804 ==
1226 00:42:44.177092 Dram Type= 6, Freq= 0, CH_0, rank 1
1227 00:42:44.177259 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1228 00:42:44.177340 ==
1229 00:42:44.177418
1230 00:42:44.177497
1231 00:42:44.177574 TX Vref Scan disable
1232 00:42:44.177653 == TX Byte 0 ==
1233 00:42:44.177732 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1234 00:42:44.177813 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1235 00:42:44.177900 == TX Byte 1 ==
1236 00:42:44.177987 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1237 00:42:44.178075 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1238 00:42:44.178163
1239 00:42:44.178270 [DATLAT]
1240 00:42:44.178356 Freq=800, CH0 RK1
1241 00:42:44.178441
1242 00:42:44.178525 DATLAT Default: 0x9
1243 00:42:44.178609 0, 0xFFFF, sum = 0
1244 00:42:44.178696 1, 0xFFFF, sum = 0
1245 00:42:44.178782 2, 0xFFFF, sum = 0
1246 00:42:44.178921 3, 0xFFFF, sum = 0
1247 00:42:44.179007 4, 0xFFFF, sum = 0
1248 00:42:44.179161 5, 0xFFFF, sum = 0
1249 00:42:44.179239 6, 0xFFFF, sum = 0
1250 00:42:44.179318 7, 0xFFFF, sum = 0
1251 00:42:44.179396 8, 0x0, sum = 1
1252 00:42:44.179475 9, 0x0, sum = 2
1253 00:42:44.179553 10, 0x0, sum = 3
1254 00:42:44.179632 11, 0x0, sum = 4
1255 00:42:44.179711 best_step = 9
1256 00:42:44.179787
1257 00:42:44.179862 ==
1258 00:42:44.179939 Dram Type= 6, Freq= 0, CH_0, rank 1
1259 00:42:44.180016 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1260 00:42:44.180093 ==
1261 00:42:44.180170 RX Vref Scan: 0
1262 00:42:44.180247
1263 00:42:44.180323 RX Vref 0 -> 0, step: 1
1264 00:42:44.180399
1265 00:42:44.180476 RX Delay -111 -> 252, step: 8
1266 00:42:44.180557 iDelay=209, Bit 0, Center 84 (-31 ~ 200) 232
1267 00:42:44.180639 iDelay=209, Bit 1, Center 88 (-31 ~ 208) 240
1268 00:42:44.180717 iDelay=209, Bit 2, Center 84 (-31 ~ 200) 232
1269 00:42:44.180795 iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224
1270 00:42:44.180872 iDelay=209, Bit 4, Center 92 (-23 ~ 208) 232
1271 00:42:44.180949 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1272 00:42:44.181026 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
1273 00:42:44.181103 iDelay=209, Bit 7, Center 92 (-23 ~ 208) 232
1274 00:42:44.181180 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
1275 00:42:44.181257 iDelay=209, Bit 9, Center 60 (-47 ~ 168) 216
1276 00:42:44.181350 iDelay=209, Bit 10, Center 76 (-39 ~ 192) 232
1277 00:42:44.181441 iDelay=209, Bit 11, Center 64 (-47 ~ 176) 224
1278 00:42:44.181518 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1279 00:42:44.181595 iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224
1280 00:42:44.181672 iDelay=209, Bit 14, Center 80 (-31 ~ 192) 224
1281 00:42:44.181749 iDelay=209, Bit 15, Center 84 (-23 ~ 192) 216
1282 00:42:44.181825 ==
1283 00:42:44.181903 Dram Type= 6, Freq= 0, CH_0, rank 1
1284 00:42:44.181980 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1285 00:42:44.182057 ==
1286 00:42:44.182149 DQS Delay:
1287 00:42:44.182256 DQS0 = 0, DQS1 = 0
1288 00:42:44.182336 DQM Delay:
1289 00:42:44.182443 DQM0 = 86, DQM1 = 74
1290 00:42:44.182520 DQ Delay:
1291 00:42:44.182597 DQ0 =84, DQ1 =88, DQ2 =84, DQ3 =80
1292 00:42:44.182674 DQ4 =92, DQ5 =76, DQ6 =92, DQ7 =92
1293 00:42:44.182752 DQ8 =68, DQ9 =60, DQ10 =76, DQ11 =64
1294 00:42:44.182828 DQ12 =84, DQ13 =80, DQ14 =80, DQ15 =84
1295 00:42:44.182904
1296 00:42:44.182979
1297 00:42:44.183056 [DQSOSCAuto] RK1, (LSB)MR18= 0x4545, (MSB)MR19= 0x606, tDQSOscB0 = 392 ps tDQSOscB1 = 392 ps
1298 00:42:44.183134 CH0 RK1: MR19=606, MR18=4545
1299 00:42:44.183211 CH0_RK1: MR19=0x606, MR18=0x4545, DQSOSC=392, MR23=63, INC=96, DEC=64
1300 00:42:44.183288 [RxdqsGatingPostProcess] freq 800
1301 00:42:44.183365 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1302 00:42:44.183442 Pre-setting of DQS Precalculation
1303 00:42:44.183519 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1304 00:42:44.183595 ==
1305 00:42:44.183672 Dram Type= 6, Freq= 0, CH_1, rank 0
1306 00:42:44.183749 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1307 00:42:44.183825 ==
1308 00:42:44.183902 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1309 00:42:44.183979 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1310 00:42:44.184055 [CA 0] Center 37 (6~68) winsize 63
1311 00:42:44.184131 [CA 1] Center 37 (6~68) winsize 63
1312 00:42:44.184207 [CA 2] Center 34 (4~65) winsize 62
1313 00:42:44.184283 [CA 3] Center 34 (4~65) winsize 62
1314 00:42:44.184359 [CA 4] Center 33 (2~64) winsize 63
1315 00:42:44.184435 [CA 5] Center 33 (3~64) winsize 62
1316 00:42:44.184510
1317 00:42:44.184586 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1318 00:42:44.184662
1319 00:42:44.184767 [CATrainingPosCal] consider 1 rank data
1320 00:42:44.184843 u2DelayCellTimex100 = 270/100 ps
1321 00:42:44.184919 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
1322 00:42:44.184996 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1323 00:42:44.185072 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1324 00:42:44.185148 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1325 00:42:44.185224 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
1326 00:42:44.185300 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1327 00:42:44.185375
1328 00:42:44.185450 CA PerBit enable=1, Macro0, CA PI delay=33
1329 00:42:44.185525
1330 00:42:44.185600 [CBTSetCACLKResult] CA Dly = 33
1331 00:42:44.185676 CS Dly: 4 (0~35)
1332 00:42:44.185752 ==
1333 00:42:44.185828 Dram Type= 6, Freq= 0, CH_1, rank 1
1334 00:42:44.185904 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1335 00:42:44.185980 ==
1336 00:42:44.186056 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1337 00:42:44.186134 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1338 00:42:44.186215 [CA 0] Center 36 (6~67) winsize 62
1339 00:42:44.186301 [CA 1] Center 37 (6~68) winsize 63
1340 00:42:44.186349 [CA 2] Center 34 (4~65) winsize 62
1341 00:42:44.186398 [CA 3] Center 34 (4~65) winsize 62
1342 00:42:44.186446 [CA 4] Center 33 (3~64) winsize 62
1343 00:42:44.186495 [CA 5] Center 33 (3~64) winsize 62
1344 00:42:44.186543
1345 00:42:44.186592 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1346 00:42:44.186641
1347 00:42:44.186689 [CATrainingPosCal] consider 2 rank data
1348 00:42:44.186739 u2DelayCellTimex100 = 270/100 ps
1349 00:42:44.186787 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1350 00:42:44.186835 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1351 00:42:44.186884 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1352 00:42:44.186933 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1353 00:42:44.186982 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1354 00:42:44.187030 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1355 00:42:44.187078
1356 00:42:44.187144 CA PerBit enable=1, Macro0, CA PI delay=33
1357 00:42:44.187202
1358 00:42:44.187252 [CBTSetCACLKResult] CA Dly = 33
1359 00:42:44.187301 CS Dly: 4 (0~36)
1360 00:42:44.187350
1361 00:42:44.187593 ----->DramcWriteLeveling(PI) begin...
1362 00:42:44.187649 ==
1363 00:42:44.187699 Dram Type= 6, Freq= 0, CH_1, rank 0
1364 00:42:44.187748 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1365 00:42:44.187797 ==
1366 00:42:44.187846 Write leveling (Byte 0): 24 => 24
1367 00:42:44.187895 Write leveling (Byte 1): 24 => 24
1368 00:42:44.187944 DramcWriteLeveling(PI) end<-----
1369 00:42:44.188010
1370 00:42:44.188059 ==
1371 00:42:44.188108 Dram Type= 6, Freq= 0, CH_1, rank 0
1372 00:42:44.188172 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1373 00:42:44.188223 ==
1374 00:42:44.188271 [Gating] SW mode calibration
1375 00:42:44.188319 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1376 00:42:44.188368 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1377 00:42:44.188417 0 6 0 | B1->B0 | 3030 2828 | 0 0 | (0 0) (0 0)
1378 00:42:44.188465 0 6 4 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
1379 00:42:44.188513 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1380 00:42:44.188561 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1381 00:42:44.188610 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1382 00:42:44.188658 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1383 00:42:44.188706 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1384 00:42:44.188754 0 6 28 | B1->B0 | 2323 2828 | 0 1 | (0 0) (0 0)
1385 00:42:44.188803 0 7 0 | B1->B0 | 3232 4242 | 0 0 | (0 0) (0 0)
1386 00:42:44.188851 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1387 00:42:44.188900 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1388 00:42:44.188948 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1389 00:42:44.188996 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1390 00:42:44.189045 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1391 00:42:44.189093 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1392 00:42:44.189141 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1393 00:42:44.189189 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1394 00:42:44.189237 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1395 00:42:44.189286 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1396 00:42:44.189334 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1397 00:42:44.189382 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1398 00:42:44.189431 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1399 00:42:44.189479 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1400 00:42:44.189527 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1401 00:42:44.189575 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1402 00:42:44.189623 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1403 00:42:44.189672 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1404 00:42:44.189720 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1405 00:42:44.189768 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1406 00:42:44.189816 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1407 00:42:44.189866 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1408 00:42:44.189914 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1409 00:42:44.189961 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1410 00:42:44.190010 Total UI for P1: 0, mck2ui 16
1411 00:42:44.190058 best dqsien dly found for B0: ( 0, 9, 28)
1412 00:42:44.190107 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1413 00:42:44.190155 Total UI for P1: 0, mck2ui 16
1414 00:42:44.190203 best dqsien dly found for B1: ( 0, 9, 30)
1415 00:42:44.190290 best DQS0 dly(MCK, UI, PI) = (0, 9, 28)
1416 00:42:44.190339 best DQS1 dly(MCK, UI, PI) = (0, 9, 30)
1417 00:42:44.190386
1418 00:42:44.190433 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 28)
1419 00:42:44.190481 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 30)
1420 00:42:44.190529 [Gating] SW calibration Done
1421 00:42:44.190577 ==
1422 00:42:44.190626 Dram Type= 6, Freq= 0, CH_1, rank 0
1423 00:42:44.190674 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1424 00:42:44.190722 ==
1425 00:42:44.190771 RX Vref Scan: 0
1426 00:42:44.190818
1427 00:42:44.190865 RX Vref 0 -> 0, step: 1
1428 00:42:44.190913
1429 00:42:44.190961 RX Delay -130 -> 252, step: 16
1430 00:42:44.191010 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1431 00:42:44.191060 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1432 00:42:44.191108 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1433 00:42:44.191156 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1434 00:42:44.191204 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1435 00:42:44.191253 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1436 00:42:44.191301 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1437 00:42:44.191349 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1438 00:42:44.191427 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1439 00:42:44.191475 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1440 00:42:44.191523 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1441 00:42:44.191571 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1442 00:42:44.191619 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1443 00:42:44.191668 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1444 00:42:44.191716 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1445 00:42:44.191765 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1446 00:42:44.191813 ==
1447 00:42:44.191862 Dram Type= 6, Freq= 0, CH_1, rank 0
1448 00:42:44.191910 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1449 00:42:44.191958 ==
1450 00:42:44.192006 DQS Delay:
1451 00:42:44.192054 DQS0 = 0, DQS1 = 0
1452 00:42:44.192101 DQM Delay:
1453 00:42:44.192149 DQM0 = 85, DQM1 = 74
1454 00:42:44.192197 DQ Delay:
1455 00:42:44.192276 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =85
1456 00:42:44.192348 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =85
1457 00:42:44.192402 DQ8 =53, DQ9 =61, DQ10 =77, DQ11 =61
1458 00:42:44.192450 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1459 00:42:44.192528
1460 00:42:44.192576
1461 00:42:44.192624 ==
1462 00:42:44.192672 Dram Type= 6, Freq= 0, CH_1, rank 0
1463 00:42:44.192721 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1464 00:42:44.192769 ==
1465 00:42:44.192818
1466 00:42:44.192865
1467 00:42:44.192913 TX Vref Scan disable
1468 00:42:44.192962 == TX Byte 0 ==
1469 00:42:44.193010 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1470 00:42:44.193059 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1471 00:42:44.193108 == TX Byte 1 ==
1472 00:42:44.193363 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1473 00:42:44.193432 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1474 00:42:44.193481 ==
1475 00:42:44.193530 Dram Type= 6, Freq= 0, CH_1, rank 0
1476 00:42:44.193580 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1477 00:42:44.193628 ==
1478 00:42:44.193677 TX Vref=22, minBit 3, minWin=27, winSum=448
1479 00:42:44.193726 TX Vref=24, minBit 3, minWin=27, winSum=449
1480 00:42:44.193775 TX Vref=26, minBit 0, minWin=28, winSum=454
1481 00:42:44.193824 TX Vref=28, minBit 0, minWin=28, winSum=456
1482 00:42:44.193874 TX Vref=30, minBit 0, minWin=28, winSum=457
1483 00:42:44.193922 TX Vref=32, minBit 9, minWin=27, winSum=456
1484 00:42:44.193970 [TxChooseVref] Worse bit 0, Min win 28, Win sum 457, Final Vref 30
1485 00:42:44.194020
1486 00:42:44.194069 Final TX Range 1 Vref 30
1487 00:42:44.194118
1488 00:42:44.194166 ==
1489 00:42:44.194222 Dram Type= 6, Freq= 0, CH_1, rank 0
1490 00:42:44.194303 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1491 00:42:44.194351 ==
1492 00:42:44.194400
1493 00:42:44.194447
1494 00:42:44.194494 TX Vref Scan disable
1495 00:42:44.194543 == TX Byte 0 ==
1496 00:42:44.194591 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1497 00:42:44.194640 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1498 00:42:44.194688 == TX Byte 1 ==
1499 00:42:44.194736 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1500 00:42:44.194815 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1501 00:42:44.194863
1502 00:42:44.194910 [DATLAT]
1503 00:42:44.194958 Freq=800, CH1 RK0
1504 00:42:44.195007
1505 00:42:44.195054 DATLAT Default: 0xa
1506 00:42:44.195103 0, 0xFFFF, sum = 0
1507 00:42:44.195152 1, 0xFFFF, sum = 0
1508 00:42:44.195200 2, 0xFFFF, sum = 0
1509 00:42:44.195248 3, 0xFFFF, sum = 0
1510 00:42:44.195297 4, 0xFFFF, sum = 0
1511 00:42:44.195346 5, 0xFFFF, sum = 0
1512 00:42:44.195395 6, 0xFFFF, sum = 0
1513 00:42:44.195444 7, 0xFFFF, sum = 0
1514 00:42:44.195493 8, 0x0, sum = 1
1515 00:42:44.195542 9, 0x0, sum = 2
1516 00:42:44.195590 10, 0x0, sum = 3
1517 00:42:44.195639 11, 0x0, sum = 4
1518 00:42:44.195688 best_step = 9
1519 00:42:44.195737
1520 00:42:44.195785 ==
1521 00:42:44.195833 Dram Type= 6, Freq= 0, CH_1, rank 0
1522 00:42:44.195882 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1523 00:42:44.195930 ==
1524 00:42:44.195977 RX Vref Scan: 1
1525 00:42:44.196025
1526 00:42:44.196072 Set Vref Range= 32 -> 127
1527 00:42:44.196121
1528 00:42:44.196168 RX Vref 32 -> 127, step: 1
1529 00:42:44.196216
1530 00:42:44.196264 RX Delay -111 -> 252, step: 8
1531 00:42:44.196313
1532 00:42:44.196361 Set Vref, RX VrefLevel [Byte0]: 32
1533 00:42:44.196410 [Byte1]: 32
1534 00:42:44.196459
1535 00:42:44.196506 Set Vref, RX VrefLevel [Byte0]: 33
1536 00:42:44.196554 [Byte1]: 33
1537 00:42:44.196602
1538 00:42:44.196650 Set Vref, RX VrefLevel [Byte0]: 34
1539 00:42:44.196698 [Byte1]: 34
1540 00:42:44.196746
1541 00:42:44.196794 Set Vref, RX VrefLevel [Byte0]: 35
1542 00:42:44.196842 [Byte1]: 35
1543 00:42:44.196890
1544 00:42:44.196937 Set Vref, RX VrefLevel [Byte0]: 36
1545 00:42:44.196985 [Byte1]: 36
1546 00:42:44.197033
1547 00:42:44.197081 Set Vref, RX VrefLevel [Byte0]: 37
1548 00:42:44.197130 [Byte1]: 37
1549 00:42:44.197178
1550 00:42:44.197226 Set Vref, RX VrefLevel [Byte0]: 38
1551 00:42:44.197274 [Byte1]: 38
1552 00:42:44.197322
1553 00:42:44.197370 Set Vref, RX VrefLevel [Byte0]: 39
1554 00:42:44.197418 [Byte1]: 39
1555 00:42:44.197466
1556 00:42:44.197603 Set Vref, RX VrefLevel [Byte0]: 40
1557 00:42:44.197678 [Byte1]: 40
1558 00:42:44.197728
1559 00:42:44.197807 Set Vref, RX VrefLevel [Byte0]: 41
1560 00:42:44.197856 [Byte1]: 41
1561 00:42:44.197904
1562 00:42:44.197953 Set Vref, RX VrefLevel [Byte0]: 42
1563 00:42:44.198001 [Byte1]: 42
1564 00:42:44.198049
1565 00:42:44.198097 Set Vref, RX VrefLevel [Byte0]: 43
1566 00:42:44.198146 [Byte1]: 43
1567 00:42:44.198194
1568 00:42:44.198278 Set Vref, RX VrefLevel [Byte0]: 44
1569 00:42:44.198328 [Byte1]: 44
1570 00:42:44.198376
1571 00:42:44.198425 Set Vref, RX VrefLevel [Byte0]: 45
1572 00:42:44.198473 [Byte1]: 45
1573 00:42:44.198521
1574 00:42:44.198570 Set Vref, RX VrefLevel [Byte0]: 46
1575 00:42:44.198618 [Byte1]: 46
1576 00:42:44.198667
1577 00:42:44.198715 Set Vref, RX VrefLevel [Byte0]: 47
1578 00:42:44.198763 [Byte1]: 47
1579 00:42:44.198812
1580 00:42:44.198860 Set Vref, RX VrefLevel [Byte0]: 48
1581 00:42:44.198908 [Byte1]: 48
1582 00:42:44.198956
1583 00:42:44.199004 Set Vref, RX VrefLevel [Byte0]: 49
1584 00:42:44.199052 [Byte1]: 49
1585 00:42:44.199099
1586 00:42:44.199147 Set Vref, RX VrefLevel [Byte0]: 50
1587 00:42:44.199195 [Byte1]: 50
1588 00:42:44.199243
1589 00:42:44.199291 Set Vref, RX VrefLevel [Byte0]: 51
1590 00:42:44.199340 [Byte1]: 51
1591 00:42:44.199388
1592 00:42:44.199435 Set Vref, RX VrefLevel [Byte0]: 52
1593 00:42:44.199482 [Byte1]: 52
1594 00:42:44.199530
1595 00:42:44.199577 Set Vref, RX VrefLevel [Byte0]: 53
1596 00:42:44.199625 [Byte1]: 53
1597 00:42:44.199674
1598 00:42:44.199722 Set Vref, RX VrefLevel [Byte0]: 54
1599 00:42:44.199771 [Byte1]: 54
1600 00:42:44.199819
1601 00:42:44.199867 Set Vref, RX VrefLevel [Byte0]: 55
1602 00:42:44.199915 [Byte1]: 55
1603 00:42:44.199963
1604 00:42:44.200011 Set Vref, RX VrefLevel [Byte0]: 56
1605 00:42:44.200059 [Byte1]: 56
1606 00:42:44.200107
1607 00:42:44.200155 Set Vref, RX VrefLevel [Byte0]: 57
1608 00:42:44.200204 [Byte1]: 57
1609 00:42:44.200251
1610 00:42:44.200299 Set Vref, RX VrefLevel [Byte0]: 58
1611 00:42:44.200348 [Byte1]: 58
1612 00:42:44.200396
1613 00:42:44.200443 Set Vref, RX VrefLevel [Byte0]: 59
1614 00:42:44.200491 [Byte1]: 59
1615 00:42:44.200540
1616 00:42:44.200588 Set Vref, RX VrefLevel [Byte0]: 60
1617 00:42:44.200637 [Byte1]: 60
1618 00:42:44.200685
1619 00:42:44.200734 Set Vref, RX VrefLevel [Byte0]: 61
1620 00:42:44.200782 [Byte1]: 61
1621 00:42:44.200830
1622 00:42:44.200877 Set Vref, RX VrefLevel [Byte0]: 62
1623 00:42:44.200924 [Byte1]: 62
1624 00:42:44.200972
1625 00:42:44.201020 Set Vref, RX VrefLevel [Byte0]: 63
1626 00:42:44.201068 [Byte1]: 63
1627 00:42:44.201116
1628 00:42:44.201163 Set Vref, RX VrefLevel [Byte0]: 64
1629 00:42:44.201211 [Byte1]: 64
1630 00:42:44.201259
1631 00:42:44.201307 Set Vref, RX VrefLevel [Byte0]: 65
1632 00:42:44.201354 [Byte1]: 65
1633 00:42:44.201402
1634 00:42:44.201449 Set Vref, RX VrefLevel [Byte0]: 66
1635 00:42:44.201498 [Byte1]: 66
1636 00:42:44.201546
1637 00:42:44.201594 Set Vref, RX VrefLevel [Byte0]: 67
1638 00:42:44.201835 [Byte1]: 67
1639 00:42:44.201893
1640 00:42:44.201942 Set Vref, RX VrefLevel [Byte0]: 68
1641 00:42:44.201991 [Byte1]: 68
1642 00:42:44.202040
1643 00:42:44.202088 Set Vref, RX VrefLevel [Byte0]: 69
1644 00:42:44.202137 [Byte1]: 69
1645 00:42:44.202185
1646 00:42:44.202270 Set Vref, RX VrefLevel [Byte0]: 70
1647 00:42:44.202334 [Byte1]: 70
1648 00:42:44.202382
1649 00:42:44.202431 Set Vref, RX VrefLevel [Byte0]: 71
1650 00:42:44.202479 [Byte1]: 71
1651 00:42:44.202527
1652 00:42:44.202575 Set Vref, RX VrefLevel [Byte0]: 72
1653 00:42:44.202623 [Byte1]: 72
1654 00:42:44.202672
1655 00:42:44.202719 Set Vref, RX VrefLevel [Byte0]: 73
1656 00:42:44.202767 [Byte1]: 73
1657 00:42:44.202817
1658 00:42:44.202891 Set Vref, RX VrefLevel [Byte0]: 74
1659 00:42:44.202945 [Byte1]: 74
1660 00:42:44.202994
1661 00:42:44.203042 Set Vref, RX VrefLevel [Byte0]: 75
1662 00:42:44.203092 [Byte1]: 75
1663 00:42:44.203141
1664 00:42:44.203189 Final RX Vref Byte 0 = 60 to rank0
1665 00:42:44.203238 Final RX Vref Byte 1 = 53 to rank0
1666 00:42:44.203287 Final RX Vref Byte 0 = 60 to rank1
1667 00:42:44.203336 Final RX Vref Byte 1 = 53 to rank1==
1668 00:42:44.203385 Dram Type= 6, Freq= 0, CH_1, rank 0
1669 00:42:44.203433 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1670 00:42:44.203482 ==
1671 00:42:44.203531 DQS Delay:
1672 00:42:44.203579 DQS0 = 0, DQS1 = 0
1673 00:42:44.203627 DQM Delay:
1674 00:42:44.203676 DQM0 = 81, DQM1 = 75
1675 00:42:44.203725 DQ Delay:
1676 00:42:44.203773 DQ0 =88, DQ1 =76, DQ2 =72, DQ3 =76
1677 00:42:44.203822 DQ4 =80, DQ5 =92, DQ6 =88, DQ7 =76
1678 00:42:44.203870 DQ8 =60, DQ9 =64, DQ10 =76, DQ11 =64
1679 00:42:44.203917 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =84
1680 00:42:44.203965
1681 00:42:44.204014
1682 00:42:44.204063 [DQSOSCAuto] RK0, (LSB)MR18= 0x5858, (MSB)MR19= 0x606, tDQSOscB0 = 387 ps tDQSOscB1 = 387 ps
1683 00:42:44.204113 CH1 RK0: MR19=606, MR18=5858
1684 00:42:44.204162 CH1_RK0: MR19=0x606, MR18=0x5858, DQSOSC=387, MR23=63, INC=98, DEC=65
1685 00:42:44.204211
1686 00:42:44.204259 ----->DramcWriteLeveling(PI) begin...
1687 00:42:44.204308 ==
1688 00:42:44.204356 Dram Type= 6, Freq= 0, CH_1, rank 1
1689 00:42:44.204405 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1690 00:42:44.204454 ==
1691 00:42:44.204502 Write leveling (Byte 0): 26 => 26
1692 00:42:44.204551 Write leveling (Byte 1): 26 => 26
1693 00:42:44.204599 DramcWriteLeveling(PI) end<-----
1694 00:42:44.204647
1695 00:42:44.204695 ==
1696 00:42:44.204744 Dram Type= 6, Freq= 0, CH_1, rank 1
1697 00:42:44.204792 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1698 00:42:44.204841 ==
1699 00:42:44.204890 [Gating] SW mode calibration
1700 00:42:44.204939 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1701 00:42:44.204988 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1702 00:42:44.205038 0 6 0 | B1->B0 | 2c2c 2323 | 1 0 | (1 0) (0 0)
1703 00:42:44.205087 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1704 00:42:44.205136 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1705 00:42:44.205184 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1706 00:42:44.205232 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1707 00:42:44.205281 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1708 00:42:44.205329 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1709 00:42:44.205378 0 6 28 | B1->B0 | 2323 3131 | 1 1 | (0 0) (0 0)
1710 00:42:44.205426 0 7 0 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0)
1711 00:42:44.205474 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1712 00:42:44.205523 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1713 00:42:44.205571 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1714 00:42:44.205619 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1715 00:42:44.205666 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1716 00:42:44.205715 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1717 00:42:44.205764 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1718 00:42:44.205812 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1719 00:42:44.205861 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1720 00:42:44.205909 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1721 00:42:44.205958 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1722 00:42:44.206006 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1723 00:42:44.206055 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1724 00:42:44.206103 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1725 00:42:44.206151 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1726 00:42:44.206199 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1727 00:42:44.206255 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1728 00:42:44.206305 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1729 00:42:44.206353 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1730 00:42:44.206402 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1731 00:42:44.206450 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1732 00:42:44.206503 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1733 00:42:44.206552 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1734 00:42:44.206636 Total UI for P1: 0, mck2ui 16
1735 00:42:44.206689 best dqsien dly found for B0: ( 0, 9, 26)
1736 00:42:44.206750 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1737 00:42:44.206802 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1738 00:42:44.206857 Total UI for P1: 0, mck2ui 16
1739 00:42:44.206907 best dqsien dly found for B1: ( 0, 9, 30)
1740 00:42:44.206977 best DQS0 dly(MCK, UI, PI) = (0, 9, 26)
1741 00:42:44.207034 best DQS1 dly(MCK, UI, PI) = (0, 9, 30)
1742 00:42:44.207083
1743 00:42:44.207131 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 26)
1744 00:42:44.207180 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 30)
1745 00:42:44.207229 [Gating] SW calibration Done
1746 00:42:44.207277 ==
1747 00:42:44.207325 Dram Type= 6, Freq= 0, CH_1, rank 1
1748 00:42:44.207374 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1749 00:42:44.207422 ==
1750 00:42:44.207471 RX Vref Scan: 0
1751 00:42:44.207519
1752 00:42:44.207568 RX Vref 0 -> 0, step: 1
1753 00:42:44.207616
1754 00:42:44.207664 RX Delay -130 -> 252, step: 16
1755 00:42:44.207902 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1756 00:42:44.207957 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1757 00:42:44.208007 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1758 00:42:44.208056 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1759 00:42:44.208105 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1760 00:42:44.208153 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1761 00:42:44.208202 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1762 00:42:44.208250 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1763 00:42:44.208298 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1764 00:42:44.208363 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1765 00:42:44.208435 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1766 00:42:44.208508 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1767 00:42:44.208559 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1768 00:42:44.208607 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1769 00:42:44.208656 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1770 00:42:44.208706 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1771 00:42:44.208755 ==
1772 00:42:44.208803 Dram Type= 6, Freq= 0, CH_1, rank 1
1773 00:42:44.208853 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1774 00:42:44.208901 ==
1775 00:42:44.208949 DQS Delay:
1776 00:42:44.208997 DQS0 = 0, DQS1 = 0
1777 00:42:44.209046 DQM Delay:
1778 00:42:44.209093 DQM0 = 86, DQM1 = 73
1779 00:42:44.209143 DQ Delay:
1780 00:42:44.209191 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =85
1781 00:42:44.209239 DQ4 =85, DQ5 =101, DQ6 =85, DQ7 =85
1782 00:42:44.209287 DQ8 =53, DQ9 =61, DQ10 =69, DQ11 =61
1783 00:42:44.209336 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1784 00:42:44.209384
1785 00:42:44.209432
1786 00:42:44.209480 ==
1787 00:42:44.209528 Dram Type= 6, Freq= 0, CH_1, rank 1
1788 00:42:44.209577 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1789 00:42:44.209626 ==
1790 00:42:44.209674
1791 00:42:44.209720
1792 00:42:44.209768 TX Vref Scan disable
1793 00:42:44.209816 == TX Byte 0 ==
1794 00:42:44.209865 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1795 00:42:44.209914 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1796 00:42:44.209962 == TX Byte 1 ==
1797 00:42:44.210010 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1798 00:42:44.210058 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1799 00:42:44.210106 ==
1800 00:42:44.210153 Dram Type= 6, Freq= 0, CH_1, rank 1
1801 00:42:44.210202 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1802 00:42:44.210277 ==
1803 00:42:44.210340 TX Vref=22, minBit 0, minWin=27, winSum=447
1804 00:42:44.210389 TX Vref=24, minBit 0, minWin=28, winSum=453
1805 00:42:44.210438 TX Vref=26, minBit 8, minWin=27, winSum=455
1806 00:42:44.210487 TX Vref=28, minBit 0, minWin=28, winSum=458
1807 00:42:44.210536 TX Vref=30, minBit 0, minWin=28, winSum=455
1808 00:42:44.210585 TX Vref=32, minBit 3, minWin=28, winSum=455
1809 00:42:44.210633 [TxChooseVref] Worse bit 0, Min win 28, Win sum 458, Final Vref 28
1810 00:42:44.210682
1811 00:42:44.210731 Final TX Range 1 Vref 28
1812 00:42:44.210780
1813 00:42:44.210828 ==
1814 00:42:44.210875 Dram Type= 6, Freq= 0, CH_1, rank 1
1815 00:42:44.210924 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1816 00:42:44.210973 ==
1817 00:42:44.211021
1818 00:42:44.211068
1819 00:42:44.211115 TX Vref Scan disable
1820 00:42:44.211162 == TX Byte 0 ==
1821 00:42:44.211211 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1822 00:42:44.211260 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1823 00:42:44.211308 == TX Byte 1 ==
1824 00:42:44.211357 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1825 00:42:44.211405 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1826 00:42:44.211454
1827 00:42:44.211501 [DATLAT]
1828 00:42:44.211549 Freq=800, CH1 RK1
1829 00:42:44.211597
1830 00:42:44.211645 DATLAT Default: 0x9
1831 00:42:44.211693 0, 0xFFFF, sum = 0
1832 00:42:44.211743 1, 0xFFFF, sum = 0
1833 00:42:44.211792 2, 0xFFFF, sum = 0
1834 00:42:44.211840 3, 0xFFFF, sum = 0
1835 00:42:44.211889 4, 0xFFFF, sum = 0
1836 00:42:44.211937 5, 0xFFFF, sum = 0
1837 00:42:44.211986 6, 0xFFFF, sum = 0
1838 00:42:44.212034 7, 0xFFFF, sum = 0
1839 00:42:44.212082 8, 0x0, sum = 1
1840 00:42:44.212131 9, 0x0, sum = 2
1841 00:42:44.212180 10, 0x0, sum = 3
1842 00:42:44.212229 11, 0x0, sum = 4
1843 00:42:44.212277 best_step = 9
1844 00:42:44.212326
1845 00:42:44.212372 ==
1846 00:42:44.212419 Dram Type= 6, Freq= 0, CH_1, rank 1
1847 00:42:44.212468 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1848 00:42:44.212516 ==
1849 00:42:44.212566 RX Vref Scan: 0
1850 00:42:44.212614
1851 00:42:44.212662 RX Vref 0 -> 0, step: 1
1852 00:42:44.212710
1853 00:42:44.212758 RX Delay -111 -> 252, step: 8
1854 00:42:44.212807 iDelay=209, Bit 0, Center 84 (-31 ~ 200) 232
1855 00:42:44.212855 iDelay=209, Bit 1, Center 76 (-39 ~ 192) 232
1856 00:42:44.212903 iDelay=209, Bit 2, Center 72 (-47 ~ 192) 240
1857 00:42:44.212953 iDelay=209, Bit 3, Center 80 (-39 ~ 200) 240
1858 00:42:44.213001 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
1859 00:42:44.213049 iDelay=209, Bit 5, Center 92 (-23 ~ 208) 232
1860 00:42:44.213097 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
1861 00:42:44.213146 iDelay=209, Bit 7, Center 80 (-39 ~ 200) 240
1862 00:42:44.213194 iDelay=209, Bit 8, Center 60 (-55 ~ 176) 232
1863 00:42:44.213243 iDelay=209, Bit 9, Center 60 (-55 ~ 176) 232
1864 00:42:44.213308 iDelay=209, Bit 10, Center 76 (-39 ~ 192) 232
1865 00:42:44.213388 iDelay=209, Bit 11, Center 64 (-55 ~ 184) 240
1866 00:42:44.213447 iDelay=209, Bit 12, Center 84 (-31 ~ 200) 232
1867 00:42:44.213496 iDelay=209, Bit 13, Center 84 (-31 ~ 200) 232
1868 00:42:44.213545 iDelay=209, Bit 14, Center 84 (-31 ~ 200) 232
1869 00:42:44.213594 iDelay=209, Bit 15, Center 80 (-31 ~ 192) 224
1870 00:42:44.213642 ==
1871 00:42:44.213690 Dram Type= 6, Freq= 0, CH_1, rank 1
1872 00:42:44.213739 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1873 00:42:44.213787 ==
1874 00:42:44.213835 DQS Delay:
1875 00:42:44.213884 DQS0 = 0, DQS1 = 0
1876 00:42:44.213932 DQM Delay:
1877 00:42:44.213981 DQM0 = 82, DQM1 = 74
1878 00:42:44.214030 DQ Delay:
1879 00:42:44.214078 DQ0 =84, DQ1 =76, DQ2 =72, DQ3 =80
1880 00:42:44.214127 DQ4 =84, DQ5 =92, DQ6 =92, DQ7 =80
1881 00:42:44.214175 DQ8 =60, DQ9 =60, DQ10 =76, DQ11 =64
1882 00:42:44.214254 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =80
1883 00:42:44.214319
1884 00:42:44.214367
1885 00:42:44.214416 [DQSOSCAuto] RK1, (LSB)MR18= 0x3a3a, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 395 ps
1886 00:42:44.214466 CH1 RK1: MR19=606, MR18=3A3A
1887 00:42:44.214515 CH1_RK1: MR19=0x606, MR18=0x3A3A, DQSOSC=395, MR23=63, INC=94, DEC=63
1888 00:42:44.214565 [RxdqsGatingPostProcess] freq 800
1889 00:42:44.214613 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1890 00:42:44.214662 Pre-setting of DQS Precalculation
1891 00:42:44.214900 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1892 00:42:44.214957 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
1893 00:42:44.215008 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
1894 00:42:44.215058
1895 00:42:44.215106
1896 00:42:44.215154 [Calibration Summary] 1600 Mbps
1897 00:42:44.215203 CH 0, Rank 0
1898 00:42:44.215251 SW Impedance : PASS
1899 00:42:44.215300 DUTY Scan : NO K
1900 00:42:44.215349 ZQ Calibration : PASS
1901 00:42:44.215397 Jitter Meter : NO K
1902 00:42:44.215446 CBT Training : PASS
1903 00:42:44.215524 Write leveling : PASS
1904 00:42:44.215587 RX DQS gating : PASS
1905 00:42:44.215639 RX DQ/DQS(RDDQC) : PASS
1906 00:42:44.215694 TX DQ/DQS : PASS
1907 00:42:44.215752 RX DATLAT : PASS
1908 00:42:44.215818 RX DQ/DQS(Engine): PASS
1909 00:42:44.215875 TX OE : NO K
1910 00:42:44.215926 All Pass.
1911 00:42:44.215975
1912 00:42:44.216043 CH 0, Rank 1
1913 00:42:44.216100 SW Impedance : PASS
1914 00:42:44.216152 DUTY Scan : NO K
1915 00:42:44.216199 ZQ Calibration : PASS
1916 00:42:44.216247 Jitter Meter : NO K
1917 00:42:44.216295 CBT Training : PASS
1918 00:42:44.216343 Write leveling : PASS
1919 00:42:44.216392 RX DQS gating : PASS
1920 00:42:44.216440 RX DQ/DQS(RDDQC) : PASS
1921 00:42:44.216488 TX DQ/DQS : PASS
1922 00:42:44.216536 RX DATLAT : PASS
1923 00:42:44.216585 RX DQ/DQS(Engine): PASS
1924 00:42:44.216633 TX OE : NO K
1925 00:42:44.216681 All Pass.
1926 00:42:44.216729
1927 00:42:44.216777 CH 1, Rank 0
1928 00:42:44.216825 SW Impedance : PASS
1929 00:42:44.216874 DUTY Scan : NO K
1930 00:42:44.216922 ZQ Calibration : PASS
1931 00:42:44.216970 Jitter Meter : NO K
1932 00:42:44.217018 CBT Training : PASS
1933 00:42:44.217067 Write leveling : PASS
1934 00:42:44.217116 RX DQS gating : PASS
1935 00:42:44.217164 RX DQ/DQS(RDDQC) : PASS
1936 00:42:44.351478 TX DQ/DQS : PASS
1937 00:42:44.351601 RX DATLAT : PASS
1938 00:42:44.351662 RX DQ/DQS(Engine): PASS
1939 00:42:44.351718 TX OE : NO K
1940 00:42:44.351771 All Pass.
1941 00:42:44.351823
1942 00:42:44.351875 CH 1, Rank 1
1943 00:42:44.351925 SW Impedance : PASS
1944 00:42:44.351975 DUTY Scan : NO K
1945 00:42:44.352025 ZQ Calibration : PASS
1946 00:42:44.352075 Jitter Meter : NO K
1947 00:42:44.352125 CBT Training : PASS
1948 00:42:44.352175 Write leveling : PASS
1949 00:42:44.352224 RX DQS gating : PASS
1950 00:42:44.352273 RX DQ/DQS(RDDQC) : PASS
1951 00:42:44.352322 TX DQ/DQS : PASS
1952 00:42:44.352371 RX DATLAT : PASS
1953 00:42:44.352419 RX DQ/DQS(Engine): PASS
1954 00:42:44.352467 TX OE : NO K
1955 00:42:44.352516 All Pass.
1956 00:42:44.352565
1957 00:42:44.352614 DramC Write-DBI off
1958 00:42:44.352663 PER_BANK_REFRESH: Hybrid Mode
1959 00:42:44.352712 TX_TRACKING: ON
1960 00:42:44.352761 [GetDramInforAfterCalByMRR] Vendor 6.
1961 00:42:44.352810 [GetDramInforAfterCalByMRR] Revision 606.
1962 00:42:44.352860 [GetDramInforAfterCalByMRR] Revision 2 0.
1963 00:42:44.352908 MR0 0x3939
1964 00:42:44.352956 MR8 0x1111
1965 00:42:44.353004 RK0, DieNum 1, Density 16Gb, RKsize 16Gb.
1966 00:42:44.353052
1967 00:42:44.353100 MR0 0x3939
1968 00:42:44.353148 MR8 0x1111
1969 00:42:44.353196 RK1, DieNum 1, Density 16Gb, RKsize 16Gb.
1970 00:42:44.353244
1971 00:42:44.353293 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
1972 00:42:44.353343 [FAST_K] Save calibration result to emmc
1973 00:42:44.353391 [FAST_K] Save calibration result to emmc
1974 00:42:44.353439 dram_init: config_dvfs: 1
1975 00:42:44.353517 dramc_set_vcore_voltage set vcore to 662500
1976 00:42:44.353567 Read voltage for 1200, 2
1977 00:42:44.353615 Vio18 = 0
1978 00:42:44.353663 Vcore = 662500
1979 00:42:44.353710 Vdram = 0
1980 00:42:44.353758 Vddq = 0
1981 00:42:44.353806 Vmddr = 0
1982 00:42:44.353871 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
1983 00:42:44.353933 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
1984 00:42:44.353982 MEM_TYPE=3, freq_sel=15
1985 00:42:44.354030 sv_algorithm_assistance_LP4_1600
1986 00:42:44.354079 ============ PULL DRAM RESETB DOWN ============
1987 00:42:44.354128 ========== PULL DRAM RESETB DOWN end =========
1988 00:42:44.354176 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
1989 00:42:44.354257 ===================================
1990 00:42:44.354322 LPDDR4 DRAM CONFIGURATION
1991 00:42:44.354370 ===================================
1992 00:42:44.354419 EX_ROW_EN[0] = 0x0
1993 00:42:44.354467 EX_ROW_EN[1] = 0x0
1994 00:42:44.354516 LP4Y_EN = 0x0
1995 00:42:44.354570 WORK_FSP = 0x0
1996 00:42:44.354638 WL = 0x4
1997 00:42:44.354700 RL = 0x4
1998 00:42:44.354748 BL = 0x2
1999 00:42:44.354795 RPST = 0x0
2000 00:42:44.354872 RD_PRE = 0x0
2001 00:42:44.354919 WR_PRE = 0x1
2002 00:42:44.354967 WR_PST = 0x0
2003 00:42:44.355016 DBI_WR = 0x0
2004 00:42:44.355063 DBI_RD = 0x0
2005 00:42:44.355111 OTF = 0x1
2006 00:42:44.355158 ===================================
2007 00:42:44.355207 ===================================
2008 00:42:44.355255 ANA top config
2009 00:42:44.355303 ===================================
2010 00:42:44.355352 DLL_ASYNC_EN = 0
2011 00:42:44.355400 ALL_SLAVE_EN = 0
2012 00:42:44.355447 NEW_RANK_MODE = 1
2013 00:42:44.355495 DLL_IDLE_MODE = 1
2014 00:42:44.355543 LP45_APHY_COMB_EN = 1
2015 00:42:44.355591 TX_ODT_DIS = 1
2016 00:42:44.355639 NEW_8X_MODE = 1
2017 00:42:44.355689 ===================================
2018 00:42:44.355738 ===================================
2019 00:42:44.355786 data_rate = 2400
2020 00:42:44.355835 CKR = 1
2021 00:42:44.355882 DQ_P2S_RATIO = 8
2022 00:42:44.355930 ===================================
2023 00:42:44.355987 CA_P2S_RATIO = 8
2024 00:42:44.356045 DQ_CA_OPEN = 0
2025 00:42:44.356095 DQ_SEMI_OPEN = 0
2026 00:42:44.356144 CA_SEMI_OPEN = 0
2027 00:42:44.356193 CA_FULL_RATE = 0
2028 00:42:44.356242 DQ_CKDIV4_EN = 0
2029 00:42:44.356290 CA_CKDIV4_EN = 0
2030 00:42:44.356338 CA_PREDIV_EN = 0
2031 00:42:44.356387 PH8_DLY = 17
2032 00:42:44.356436 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2033 00:42:44.356484 DQ_AAMCK_DIV = 4
2034 00:42:44.356533 CA_AAMCK_DIV = 4
2035 00:42:44.356601 CA_ADMCK_DIV = 4
2036 00:42:44.356652 DQ_TRACK_CA_EN = 0
2037 00:42:44.356702 CA_PICK = 1200
2038 00:42:44.356752 CA_MCKIO = 1200
2039 00:42:44.356802 MCKIO_SEMI = 0
2040 00:42:44.356851 PLL_FREQ = 2366
2041 00:42:44.357127 DQ_UI_PI_RATIO = 32
2042 00:42:44.357237 CA_UI_PI_RATIO = 0
2043 00:42:44.357289 ===================================
2044 00:42:44.357339 ===================================
2045 00:42:44.357392 memory_type:LPDDR4
2046 00:42:44.357444 GP_NUM : 10
2047 00:42:44.357495 SRAM_EN : 1
2048 00:42:44.357545 MD32_EN : 0
2049 00:42:44.357596 ===================================
2050 00:42:44.357646 [ANA_INIT] >>>>>>>>>>>>>>
2051 00:42:44.357696 <<<<<< [CONFIGURE PHASE]: ANA_TX
2052 00:42:44.357759 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2053 00:42:44.357808 ===================================
2054 00:42:44.357857 data_rate = 2400,PCW = 0X5b00
2055 00:42:44.357906 ===================================
2056 00:42:44.357956 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2057 00:42:44.358005 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2058 00:42:44.358054 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2059 00:42:44.358104 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2060 00:42:44.358153 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2061 00:42:44.358207 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2062 00:42:44.358313 [ANA_INIT] flow start
2063 00:42:44.358383 [ANA_INIT] PLL >>>>>>>>
2064 00:42:44.358451 [ANA_INIT] PLL <<<<<<<<
2065 00:42:44.358518 [ANA_INIT] MIDPI >>>>>>>>
2066 00:42:44.358585 [ANA_INIT] MIDPI <<<<<<<<
2067 00:42:44.358651 [ANA_INIT] DLL >>>>>>>>
2068 00:42:44.358735 [ANA_INIT] DLL <<<<<<<<
2069 00:42:44.358820 [ANA_INIT] flow end
2070 00:42:44.358905 ============ LP4 DIFF to SE enter ============
2071 00:42:44.358990 ============ LP4 DIFF to SE exit ============
2072 00:42:44.359075 [ANA_INIT] <<<<<<<<<<<<<
2073 00:42:44.359160 [Flow] Enable top DCM control >>>>>
2074 00:42:44.359245 [Flow] Enable top DCM control <<<<<
2075 00:42:44.359329 Enable DLL master slave shuffle
2076 00:42:44.359414 ==============================================================
2077 00:42:44.359499 Gating Mode config
2078 00:42:44.359600 ==============================================================
2079 00:42:44.359732 Config description:
2080 00:42:44.359816 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2081 00:42:44.359902 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2082 00:42:44.359988 SELPH_MODE 0: By rank 1: By Phase
2083 00:42:44.360072 ==============================================================
2084 00:42:44.360157 GAT_TRACK_EN = 1
2085 00:42:44.360242 RX_GATING_MODE = 2
2086 00:42:44.360326 RX_GATING_TRACK_MODE = 2
2087 00:42:44.360410 SELPH_MODE = 1
2088 00:42:44.360494 PICG_EARLY_EN = 1
2089 00:42:44.360579 VALID_LAT_VALUE = 1
2090 00:42:44.360663 ==============================================================
2091 00:42:44.360748 Enter into Gating configuration >>>>
2092 00:42:44.360832 Exit from Gating configuration <<<<
2093 00:42:44.360916 Enter into DVFS_PRE_config >>>>>
2094 00:42:44.361001 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2095 00:42:44.361087 Exit from DVFS_PRE_config <<<<<
2096 00:42:44.361171 Enter into PICG configuration >>>>
2097 00:42:44.361256 Exit from PICG configuration <<<<
2098 00:42:44.361340 [RX_INPUT] configuration >>>>>
2099 00:42:44.361425 [RX_INPUT] configuration <<<<<
2100 00:42:44.361509 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2101 00:42:44.361595 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2102 00:42:44.361680 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2103 00:42:44.361764 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2104 00:42:44.361849 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2105 00:42:44.361934 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2106 00:42:44.362020 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2107 00:42:44.362104 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2108 00:42:44.362189 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2109 00:42:44.362279 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2110 00:42:44.362365 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2111 00:42:44.362449 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2112 00:42:44.362534 ===================================
2113 00:42:44.362619 LPDDR4 DRAM CONFIGURATION
2114 00:42:44.362703 ===================================
2115 00:42:44.362789 EX_ROW_EN[0] = 0x0
2116 00:42:44.362874 EX_ROW_EN[1] = 0x0
2117 00:42:44.362958 LP4Y_EN = 0x0
2118 00:42:44.363042 WORK_FSP = 0x0
2119 00:42:44.363127 WL = 0x4
2120 00:42:44.363211 RL = 0x4
2121 00:42:44.363295 BL = 0x2
2122 00:42:44.363380 RPST = 0x0
2123 00:42:44.363464 RD_PRE = 0x0
2124 00:42:44.363548 WR_PRE = 0x1
2125 00:42:44.363632 WR_PST = 0x0
2126 00:42:44.363716 DBI_WR = 0x0
2127 00:42:44.363800 DBI_RD = 0x0
2128 00:42:44.363884 OTF = 0x1
2129 00:42:44.363969 ===================================
2130 00:42:44.364054 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2131 00:42:44.364139 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2132 00:42:44.364224 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2133 00:42:44.364309 ===================================
2134 00:42:44.364394 LPDDR4 DRAM CONFIGURATION
2135 00:42:44.364478 ===================================
2136 00:42:44.364563 EX_ROW_EN[0] = 0x10
2137 00:42:44.364647 EX_ROW_EN[1] = 0x0
2138 00:42:44.364731 LP4Y_EN = 0x0
2139 00:42:44.364815 WORK_FSP = 0x0
2140 00:42:44.364899 WL = 0x4
2141 00:42:44.364983 RL = 0x4
2142 00:42:44.365067 BL = 0x2
2143 00:42:44.365151 RPST = 0x0
2144 00:42:44.365236 RD_PRE = 0x0
2145 00:42:44.365320 WR_PRE = 0x1
2146 00:42:44.365404 WR_PST = 0x0
2147 00:42:44.365488 DBI_WR = 0x0
2148 00:42:44.365572 DBI_RD = 0x0
2149 00:42:44.365657 OTF = 0x1
2150 00:42:44.365741 ===================================
2151 00:42:44.366024 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2152 00:42:44.366117 ==
2153 00:42:44.366204 Dram Type= 6, Freq= 0, CH_0, rank 0
2154 00:42:44.366328 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2155 00:42:44.366415 ==
2156 00:42:44.366500 [Duty_Offset_Calibration]
2157 00:42:44.366586 B0:0 B1:2 CA:1
2158 00:42:44.366671
2159 00:42:44.366755 [DutyScan_Calibration_Flow] k_type=0
2160 00:42:44.366840
2161 00:42:44.366924 ==CLK 0==
2162 00:42:44.367009 Final CLK duty delay cell = 0
2163 00:42:44.367094 [0] MAX Duty = 5093%(X100), DQS PI = 12
2164 00:42:44.367179 [0] MIN Duty = 4938%(X100), DQS PI = 54
2165 00:42:44.367264 [0] AVG Duty = 5015%(X100)
2166 00:42:44.367348
2167 00:42:44.367432 CH0 CLK Duty spec in!! Max-Min= 155%
2168 00:42:44.367517 [DutyScan_Calibration_Flow] ====Done====
2169 00:42:44.367602
2170 00:42:44.367685 [DutyScan_Calibration_Flow] k_type=1
2171 00:42:44.367770
2172 00:42:44.367854 ==DQS 0 ==
2173 00:42:44.367939 Final DQS duty delay cell = 0
2174 00:42:44.368024 [0] MAX Duty = 5125%(X100), DQS PI = 34
2175 00:42:44.368108 [0] MIN Duty = 5031%(X100), DQS PI = 4
2176 00:42:44.368193 [0] AVG Duty = 5078%(X100)
2177 00:42:44.368277
2178 00:42:44.368361 ==DQS 1 ==
2179 00:42:44.368446 Final DQS duty delay cell = 0
2180 00:42:44.368531 [0] MAX Duty = 5031%(X100), DQS PI = 52
2181 00:42:44.368616 [0] MIN Duty = 4875%(X100), DQS PI = 20
2182 00:42:44.368701 [0] AVG Duty = 4953%(X100)
2183 00:42:44.368785
2184 00:42:44.368869 CH0 DQS 0 Duty spec in!! Max-Min= 94%
2185 00:42:44.368954
2186 00:42:44.369039 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2187 00:42:44.369124 [DutyScan_Calibration_Flow] ====Done====
2188 00:42:44.369208
2189 00:42:44.369292 [DutyScan_Calibration_Flow] k_type=3
2190 00:42:44.369377
2191 00:42:44.369462 ==DQM 0 ==
2192 00:42:44.369546 Final DQM duty delay cell = 0
2193 00:42:44.369632 [0] MAX Duty = 5124%(X100), DQS PI = 20
2194 00:42:44.369717 [0] MIN Duty = 4969%(X100), DQS PI = 40
2195 00:42:44.369802 [0] AVG Duty = 5046%(X100)
2196 00:42:44.369886
2197 00:42:44.369970 ==DQM 1 ==
2198 00:42:44.370060 Final DQM duty delay cell = 4
2199 00:42:44.370165 [4] MAX Duty = 5187%(X100), DQS PI = 52
2200 00:42:44.370268 [4] MIN Duty = 5000%(X100), DQS PI = 18
2201 00:42:44.370347 [4] AVG Duty = 5093%(X100)
2202 00:42:44.370423
2203 00:42:44.370501 CH0 DQM 0 Duty spec in!! Max-Min= 155%
2204 00:42:44.370577
2205 00:42:44.370654 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2206 00:42:44.370731 [DutyScan_Calibration_Flow] ====Done====
2207 00:42:44.370808
2208 00:42:44.370884 [DutyScan_Calibration_Flow] k_type=2
2209 00:42:44.370961
2210 00:42:44.371036 ==DQ 0 ==
2211 00:42:44.371113 Final DQ duty delay cell = -4
2212 00:42:44.371191 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2213 00:42:44.371268 [-4] MIN Duty = 4813%(X100), DQS PI = 44
2214 00:42:44.371345 [-4] AVG Duty = 4937%(X100)
2215 00:42:44.371421
2216 00:42:44.371497 ==DQ 1 ==
2217 00:42:44.371574 Final DQ duty delay cell = -4
2218 00:42:44.371652 [-4] MAX Duty = 5062%(X100), DQS PI = 6
2219 00:42:44.371729 [-4] MIN Duty = 4876%(X100), DQS PI = 62
2220 00:42:44.371806 [-4] AVG Duty = 4969%(X100)
2221 00:42:44.371882
2222 00:42:44.371958 CH0 DQ 0 Duty spec in!! Max-Min= 249%
2223 00:42:44.372035
2224 00:42:44.372111 CH0 DQ 1 Duty spec in!! Max-Min= 186%
2225 00:42:44.372189 [DutyScan_Calibration_Flow] ====Done====
2226 00:42:44.372265 ==
2227 00:42:44.372342 Dram Type= 6, Freq= 0, CH_1, rank 0
2228 00:42:44.372420 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2229 00:42:44.372497 ==
2230 00:42:44.372575 [Duty_Offset_Calibration]
2231 00:42:44.372652 B0:0 B1:4 CA:-5
2232 00:42:44.372728
2233 00:42:44.372805 [DutyScan_Calibration_Flow] k_type=0
2234 00:42:44.372881
2235 00:42:44.372957 ==CLK 0==
2236 00:42:44.373033 Final CLK duty delay cell = 0
2237 00:42:44.373111 [0] MAX Duty = 5093%(X100), DQS PI = 42
2238 00:42:44.373188 [0] MIN Duty = 4907%(X100), DQS PI = 10
2239 00:42:44.373265 [0] AVG Duty = 5000%(X100)
2240 00:42:44.373341
2241 00:42:44.373418 CH1 CLK Duty spec in!! Max-Min= 186%
2242 00:42:44.373497 [DutyScan_Calibration_Flow] ====Done====
2243 00:42:44.373581
2244 00:42:44.373665 [DutyScan_Calibration_Flow] k_type=1
2245 00:42:44.373750
2246 00:42:44.373835 ==DQS 0 ==
2247 00:42:44.373919 Final DQS duty delay cell = 0
2248 00:42:44.374005 [0] MAX Duty = 5124%(X100), DQS PI = 48
2249 00:42:44.374090 [0] MIN Duty = 4875%(X100), DQS PI = 8
2250 00:42:44.374175 [0] AVG Duty = 4999%(X100)
2251 00:42:44.374291
2252 00:42:44.374390 ==DQS 1 ==
2253 00:42:44.374480 Final DQS duty delay cell = -4
2254 00:42:44.374564 [-4] MAX Duty = 5031%(X100), DQS PI = 38
2255 00:42:44.374643 [-4] MIN Duty = 4907%(X100), DQS PI = 2
2256 00:42:44.374720 [-4] AVG Duty = 4969%(X100)
2257 00:42:44.374796
2258 00:42:44.374873 CH1 DQS 0 Duty spec in!! Max-Min= 249%
2259 00:42:44.374950
2260 00:42:44.375026 CH1 DQS 1 Duty spec in!! Max-Min= 124%
2261 00:42:44.375104 [DutyScan_Calibration_Flow] ====Done====
2262 00:42:44.375180
2263 00:42:44.375257 [DutyScan_Calibration_Flow] k_type=3
2264 00:42:44.375333
2265 00:42:44.375408 ==DQM 0 ==
2266 00:42:44.375485 Final DQM duty delay cell = -4
2267 00:42:44.375563 [-4] MAX Duty = 5062%(X100), DQS PI = 0
2268 00:42:44.375656 [-4] MIN Duty = 4844%(X100), DQS PI = 8
2269 00:42:44.375779 [-4] AVG Duty = 4953%(X100)
2270 00:42:44.375863
2271 00:42:44.375948 ==DQM 1 ==
2272 00:42:44.376033 Final DQM duty delay cell = -4
2273 00:42:44.376129 [-4] MAX Duty = 5062%(X100), DQS PI = 36
2274 00:42:44.376215 [-4] MIN Duty = 4875%(X100), DQS PI = 26
2275 00:42:44.376300 [-4] AVG Duty = 4968%(X100)
2276 00:42:44.376384
2277 00:42:44.376469 CH1 DQM 0 Duty spec in!! Max-Min= 218%
2278 00:42:44.376553
2279 00:42:44.376637 CH1 DQM 1 Duty spec in!! Max-Min= 187%
2280 00:42:44.376722 [DutyScan_Calibration_Flow] ====Done====
2281 00:42:44.376807
2282 00:42:44.376890 [DutyScan_Calibration_Flow] k_type=2
2283 00:42:44.376975
2284 00:42:44.377059 ==DQ 0 ==
2285 00:42:44.377144 Final DQ duty delay cell = 0
2286 00:42:44.377229 [0] MAX Duty = 5093%(X100), DQS PI = 32
2287 00:42:44.377314 [0] MIN Duty = 4969%(X100), DQS PI = 10
2288 00:42:44.377398 [0] AVG Duty = 5031%(X100)
2289 00:42:44.377482
2290 00:42:44.377567 ==DQ 1 ==
2291 00:42:44.377652 Final DQ duty delay cell = 0
2292 00:42:44.377737 [0] MAX Duty = 5031%(X100), DQS PI = 38
2293 00:42:44.377821 [0] MIN Duty = 4875%(X100), DQS PI = 30
2294 00:42:44.377903 [0] AVG Duty = 4953%(X100)
2295 00:42:44.377983
2296 00:42:44.378061 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2297 00:42:44.378142
2298 00:42:44.378245 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2299 00:42:44.378338 [DutyScan_Calibration_Flow] ====Done====
2300 00:42:44.378414 nWR fixed to 30
2301 00:42:44.378491 [ModeRegInit_LP4] CH0 RK0
2302 00:42:44.378567 [ModeRegInit_LP4] CH0 RK1
2303 00:42:44.378641 [ModeRegInit_LP4] CH1 RK0
2304 00:42:44.378715 [ModeRegInit_LP4] CH1 RK1
2305 00:42:44.378789 match AC timing 6
2306 00:42:44.378864 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 0
2307 00:42:44.378939 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2308 00:42:44.379014 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2309 00:42:44.379297 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2310 00:42:44.379385 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2311 00:42:44.379464 ==
2312 00:42:44.379540 Dram Type= 6, Freq= 0, CH_0, rank 0
2313 00:42:44.379616 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2314 00:42:44.379692 ==
2315 00:42:44.379768 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2316 00:42:44.379844 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2317 00:42:44.379920 [CA 0] Center 39 (9~70) winsize 62
2318 00:42:44.379995 [CA 1] Center 39 (9~70) winsize 62
2319 00:42:44.380070 [CA 2] Center 36 (5~67) winsize 63
2320 00:42:44.380144 [CA 3] Center 35 (4~66) winsize 63
2321 00:42:44.380219 [CA 4] Center 34 (3~65) winsize 63
2322 00:42:44.380294 [CA 5] Center 33 (3~64) winsize 62
2323 00:42:44.380369
2324 00:42:44.380442 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2325 00:42:44.380516
2326 00:42:44.380590 [CATrainingPosCal] consider 1 rank data
2327 00:42:44.380728 u2DelayCellTimex100 = 270/100 ps
2328 00:42:44.380802 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2329 00:42:44.380877 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2330 00:42:44.380951 CA2 delay=36 (5~67),Diff = 3 PI (14 cell)
2331 00:42:44.381025 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2332 00:42:44.381099 CA4 delay=34 (3~65),Diff = 1 PI (4 cell)
2333 00:42:44.381174 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2334 00:42:44.381248
2335 00:42:44.381321 CA PerBit enable=1, Macro0, CA PI delay=33
2336 00:42:44.381395
2337 00:42:44.381467 [CBTSetCACLKResult] CA Dly = 33
2338 00:42:44.381541 CS Dly: 7 (0~38)
2339 00:42:44.381615 ==
2340 00:42:44.381688 Dram Type= 6, Freq= 0, CH_0, rank 1
2341 00:42:44.381763 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2342 00:42:44.381838 ==
2343 00:42:44.381912 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2344 00:42:44.381986 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2345 00:42:44.382062 [CA 0] Center 39 (8~70) winsize 63
2346 00:42:44.382136 [CA 1] Center 39 (8~70) winsize 63
2347 00:42:44.382230 [CA 2] Center 36 (5~67) winsize 63
2348 00:42:44.382320 [CA 3] Center 35 (4~66) winsize 63
2349 00:42:44.382395 [CA 4] Center 33 (3~64) winsize 62
2350 00:42:44.382469 [CA 5] Center 34 (3~65) winsize 63
2351 00:42:44.382542
2352 00:42:44.382615 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2353 00:42:44.382690
2354 00:42:44.382764 [CATrainingPosCal] consider 2 rank data
2355 00:42:44.382838 u2DelayCellTimex100 = 270/100 ps
2356 00:42:44.382913 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2357 00:42:44.382988 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2358 00:42:44.383062 CA2 delay=36 (5~67),Diff = 3 PI (14 cell)
2359 00:42:44.383137 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2360 00:42:44.383211 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2361 00:42:44.383285 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2362 00:42:44.383358
2363 00:42:44.383431 CA PerBit enable=1, Macro0, CA PI delay=33
2364 00:42:44.383505
2365 00:42:44.383579 [CBTSetCACLKResult] CA Dly = 33
2366 00:42:44.383652 CS Dly: 7 (0~39)
2367 00:42:44.383726
2368 00:42:44.383799 ----->DramcWriteLeveling(PI) begin...
2369 00:42:44.383874 ==
2370 00:42:44.383949 Dram Type= 6, Freq= 0, CH_0, rank 0
2371 00:42:44.384023 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2372 00:42:44.384098 ==
2373 00:42:44.384172 Write leveling (Byte 0): 27 => 27
2374 00:42:44.384247 Write leveling (Byte 1): 27 => 27
2375 00:42:44.384322 DramcWriteLeveling(PI) end<-----
2376 00:42:44.384395
2377 00:42:44.384468 ==
2378 00:42:44.384541 Dram Type= 6, Freq= 0, CH_0, rank 0
2379 00:42:44.384616 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2380 00:42:44.384690 ==
2381 00:42:44.384763 [Gating] SW mode calibration
2382 00:42:44.384836 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2383 00:42:44.384910 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2384 00:42:44.384983 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2385 00:42:44.385056 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2386 00:42:44.385134 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2387 00:42:44.385214 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2388 00:42:44.385293 0 11 16 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
2389 00:42:44.385371 0 11 20 | B1->B0 | 2c2c 2a2a | 1 0 | (1 0) (0 0)
2390 00:42:44.385450 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2391 00:42:44.385530 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2392 00:42:44.385609 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2393 00:42:44.385687 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2394 00:42:44.385764 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2395 00:42:44.385842 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2396 00:42:44.385918 0 12 16 | B1->B0 | 2424 2828 | 0 0 | (0 0) (0 0)
2397 00:42:44.385993 0 12 20 | B1->B0 | 3636 3f3f | 0 1 | (0 0) (0 0)
2398 00:42:44.386073 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2399 00:42:44.386156 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2400 00:42:44.386274 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2401 00:42:44.386361 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2402 00:42:44.386448 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2403 00:42:44.386532 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2404 00:42:44.386620 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2405 00:42:44.386716 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2406 00:42:44.386801 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2407 00:42:44.386883 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2408 00:42:44.386963 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2409 00:42:44.387041 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2410 00:42:44.387119 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2411 00:42:44.387196 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2412 00:42:44.387273 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2413 00:42:44.387350 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2414 00:42:44.387427 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2415 00:42:44.387503 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2416 00:42:44.387580 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2417 00:42:44.387852 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2418 00:42:44.387934 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2419 00:42:44.388012 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2420 00:42:44.388091 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2421 00:42:44.388199 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2422 00:42:44.388275 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2423 00:42:44.388352 Total UI for P1: 0, mck2ui 16
2424 00:42:44.388429 best dqsien dly found for B0: ( 0, 15, 18)
2425 00:42:44.388506 Total UI for P1: 0, mck2ui 16
2426 00:42:44.388583 best dqsien dly found for B1: ( 0, 15, 18)
2427 00:42:44.388659 best DQS0 dly(MCK, UI, PI) = (0, 15, 18)
2428 00:42:44.388736 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
2429 00:42:44.388811
2430 00:42:44.388888 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 18)
2431 00:42:44.388965 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
2432 00:42:44.389041 [Gating] SW calibration Done
2433 00:42:44.389116 ==
2434 00:42:44.389192 Dram Type= 6, Freq= 0, CH_0, rank 0
2435 00:42:44.389269 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2436 00:42:44.389344 ==
2437 00:42:44.389421 RX Vref Scan: 0
2438 00:42:44.389497
2439 00:42:44.389573 RX Vref 0 -> 0, step: 1
2440 00:42:44.389648
2441 00:42:44.389723 RX Delay -40 -> 252, step: 8
2442 00:42:44.389800 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2443 00:42:44.389877 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2444 00:42:44.389954 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2445 00:42:44.390031 iDelay=200, Bit 3, Center 111 (32 ~ 191) 160
2446 00:42:44.390113 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2447 00:42:44.390190 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2448 00:42:44.390286 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2449 00:42:44.390336 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2450 00:42:44.390384 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2451 00:42:44.390433 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2452 00:42:44.390482 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2453 00:42:44.390530 iDelay=200, Bit 11, Center 103 (40 ~ 167) 128
2454 00:42:44.390578 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2455 00:42:44.390627 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2456 00:42:44.390675 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
2457 00:42:44.390724 iDelay=200, Bit 15, Center 115 (40 ~ 191) 152
2458 00:42:44.390772 ==
2459 00:42:44.390820 Dram Type= 6, Freq= 0, CH_0, rank 0
2460 00:42:44.390869 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2461 00:42:44.390917 ==
2462 00:42:44.390965 DQS Delay:
2463 00:42:44.391012 DQS0 = 0, DQS1 = 0
2464 00:42:44.391059 DQM Delay:
2465 00:42:44.391107 DQM0 = 115, DQM1 = 106
2466 00:42:44.391156 DQ Delay:
2467 00:42:44.391204 DQ0 =111, DQ1 =115, DQ2 =115, DQ3 =111
2468 00:42:44.391252 DQ4 =123, DQ5 =103, DQ6 =123, DQ7 =123
2469 00:42:44.391300 DQ8 =95, DQ9 =91, DQ10 =103, DQ11 =103
2470 00:42:44.391348 DQ12 =111, DQ13 =115, DQ14 =115, DQ15 =115
2471 00:42:44.391397
2472 00:42:44.391445
2473 00:42:44.391492 ==
2474 00:42:44.391539 Dram Type= 6, Freq= 0, CH_0, rank 0
2475 00:42:44.391588 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2476 00:42:44.391636 ==
2477 00:42:44.391684
2478 00:42:44.391731
2479 00:42:44.391779 TX Vref Scan disable
2480 00:42:44.391827 == TX Byte 0 ==
2481 00:42:44.391875 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2482 00:42:44.391924 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2483 00:42:44.391971 == TX Byte 1 ==
2484 00:42:44.392019 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2485 00:42:44.392068 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2486 00:42:44.392117 ==
2487 00:42:44.392165 Dram Type= 6, Freq= 0, CH_0, rank 0
2488 00:42:44.392213 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2489 00:42:44.392262 ==
2490 00:42:44.392310 TX Vref=22, minBit 9, minWin=25, winSum=419
2491 00:42:44.392359 TX Vref=24, minBit 10, minWin=25, winSum=425
2492 00:42:44.392407 TX Vref=26, minBit 13, minWin=25, winSum=429
2493 00:42:44.392456 TX Vref=28, minBit 8, minWin=26, winSum=436
2494 00:42:44.392504 TX Vref=30, minBit 10, minWin=26, winSum=436
2495 00:42:44.392552 TX Vref=32, minBit 12, minWin=26, winSum=435
2496 00:42:44.392600 [TxChooseVref] Worse bit 8, Min win 26, Win sum 436, Final Vref 28
2497 00:42:44.392649
2498 00:42:44.392696 Final TX Range 1 Vref 28
2499 00:42:44.392745
2500 00:42:44.392792 ==
2501 00:42:44.392840 Dram Type= 6, Freq= 0, CH_0, rank 0
2502 00:42:44.392887 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2503 00:42:44.392935 ==
2504 00:42:44.392982
2505 00:42:44.393029
2506 00:42:44.393076 TX Vref Scan disable
2507 00:42:44.393124 == TX Byte 0 ==
2508 00:42:44.393171 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2509 00:42:44.393220 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2510 00:42:44.393268 == TX Byte 1 ==
2511 00:42:44.393315 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
2512 00:42:44.393362 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
2513 00:42:44.393410
2514 00:42:44.393457 [DATLAT]
2515 00:42:44.393505 Freq=1200, CH0 RK0
2516 00:42:44.393553
2517 00:42:44.393599 DATLAT Default: 0xd
2518 00:42:44.393647 0, 0xFFFF, sum = 0
2519 00:42:44.393696 1, 0xFFFF, sum = 0
2520 00:42:44.393745 2, 0xFFFF, sum = 0
2521 00:42:44.393794 3, 0xFFFF, sum = 0
2522 00:42:44.393843 4, 0xFFFF, sum = 0
2523 00:42:44.393892 5, 0xFFFF, sum = 0
2524 00:42:44.393941 6, 0xFFFF, sum = 0
2525 00:42:44.393989 7, 0xFFFF, sum = 0
2526 00:42:44.394038 8, 0xFFFF, sum = 0
2527 00:42:44.394088 9, 0xFFFF, sum = 0
2528 00:42:44.394137 10, 0xFFFF, sum = 0
2529 00:42:44.394186 11, 0x0, sum = 1
2530 00:42:44.394282 12, 0x0, sum = 2
2531 00:42:44.394333 13, 0x0, sum = 3
2532 00:42:44.394382 14, 0x0, sum = 4
2533 00:42:44.394430 best_step = 12
2534 00:42:44.394478
2535 00:42:44.394526 ==
2536 00:42:44.394573 Dram Type= 6, Freq= 0, CH_0, rank 0
2537 00:42:44.394621 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2538 00:42:44.394669 ==
2539 00:42:44.394717 RX Vref Scan: 1
2540 00:42:44.394766
2541 00:42:44.394814 Set Vref Range= 32 -> 127
2542 00:42:44.394862
2543 00:42:44.394910 RX Vref 32 -> 127, step: 1
2544 00:42:44.394958
2545 00:42:44.395005 RX Delay -21 -> 252, step: 4
2546 00:42:44.395053
2547 00:42:44.395100 Set Vref, RX VrefLevel [Byte0]: 32
2548 00:42:44.395148 [Byte1]: 32
2549 00:42:44.395196
2550 00:42:44.395244 Set Vref, RX VrefLevel [Byte0]: 33
2551 00:42:44.395292 [Byte1]: 33
2552 00:42:44.395340
2553 00:42:44.395387 Set Vref, RX VrefLevel [Byte0]: 34
2554 00:42:44.395435 [Byte1]: 34
2555 00:42:44.395483
2556 00:42:44.395532 Set Vref, RX VrefLevel [Byte0]: 35
2557 00:42:44.395579 [Byte1]: 35
2558 00:42:44.395627
2559 00:42:44.395675 Set Vref, RX VrefLevel [Byte0]: 36
2560 00:42:44.395723 [Byte1]: 36
2561 00:42:44.395771
2562 00:42:44.395818 Set Vref, RX VrefLevel [Byte0]: 37
2563 00:42:44.395867 [Byte1]: 37
2564 00:42:44.396110
2565 00:42:44.396175 Set Vref, RX VrefLevel [Byte0]: 38
2566 00:42:44.396233 [Byte1]: 38
2567 00:42:44.396282
2568 00:42:44.396340 Set Vref, RX VrefLevel [Byte0]: 39
2569 00:42:44.396391 [Byte1]: 39
2570 00:42:44.396448
2571 00:42:44.396505 Set Vref, RX VrefLevel [Byte0]: 40
2572 00:42:44.396559 [Byte1]: 40
2573 00:42:44.396616
2574 00:42:44.396667 Set Vref, RX VrefLevel [Byte0]: 41
2575 00:42:44.396716 [Byte1]: 41
2576 00:42:44.396763
2577 00:42:44.396812 Set Vref, RX VrefLevel [Byte0]: 42
2578 00:42:44.396868 [Byte1]: 42
2579 00:42:44.396916
2580 00:42:44.396971 Set Vref, RX VrefLevel [Byte0]: 43
2581 00:42:44.397026 [Byte1]: 43
2582 00:42:44.397074
2583 00:42:44.397122 Set Vref, RX VrefLevel [Byte0]: 44
2584 00:42:44.397170 [Byte1]: 44
2585 00:42:44.397225
2586 00:42:44.397273 Set Vref, RX VrefLevel [Byte0]: 45
2587 00:42:44.397329 [Byte1]: 45
2588 00:42:44.397378
2589 00:42:44.397433 Set Vref, RX VrefLevel [Byte0]: 46
2590 00:42:44.397485 [Byte1]: 46
2591 00:42:44.397533
2592 00:42:44.397581 Set Vref, RX VrefLevel [Byte0]: 47
2593 00:42:44.397637 [Byte1]: 47
2594 00:42:44.397686
2595 00:42:44.397740 Set Vref, RX VrefLevel [Byte0]: 48
2596 00:42:44.397795 [Byte1]: 48
2597 00:42:44.397843
2598 00:42:44.397891 Set Vref, RX VrefLevel [Byte0]: 49
2599 00:42:44.397939 [Byte1]: 49
2600 00:42:44.397994
2601 00:42:44.398042 Set Vref, RX VrefLevel [Byte0]: 50
2602 00:42:44.398101 [Byte1]: 50
2603 00:42:44.398155
2604 00:42:44.398203 Set Vref, RX VrefLevel [Byte0]: 51
2605 00:42:44.398307 [Byte1]: 51
2606 00:42:44.398357
2607 00:42:44.398414 Set Vref, RX VrefLevel [Byte0]: 52
2608 00:42:44.398465 [Byte1]: 52
2609 00:42:44.398519
2610 00:42:44.398567 Set Vref, RX VrefLevel [Byte0]: 53
2611 00:42:44.398616 [Byte1]: 53
2612 00:42:44.398679
2613 00:42:44.398729 Set Vref, RX VrefLevel [Byte0]: 54
2614 00:42:44.398779 [Byte1]: 54
2615 00:42:44.398827
2616 00:42:44.398875 Set Vref, RX VrefLevel [Byte0]: 55
2617 00:42:44.398924 [Byte1]: 55
2618 00:42:44.398971
2619 00:42:44.399019 Set Vref, RX VrefLevel [Byte0]: 56
2620 00:42:44.399068 [Byte1]: 56
2621 00:42:44.399116
2622 00:42:44.399164 Set Vref, RX VrefLevel [Byte0]: 57
2623 00:42:44.399212 [Byte1]: 57
2624 00:42:44.399259
2625 00:42:44.399307 Set Vref, RX VrefLevel [Byte0]: 58
2626 00:42:44.399356 [Byte1]: 58
2627 00:42:44.399404
2628 00:42:44.399451 Set Vref, RX VrefLevel [Byte0]: 59
2629 00:42:44.399500 [Byte1]: 59
2630 00:42:44.399547
2631 00:42:44.399595 Set Vref, RX VrefLevel [Byte0]: 60
2632 00:42:44.399642 [Byte1]: 60
2633 00:42:44.399690
2634 00:42:44.399738 Set Vref, RX VrefLevel [Byte0]: 61
2635 00:42:44.399786 [Byte1]: 61
2636 00:42:44.399835
2637 00:42:44.399882 Set Vref, RX VrefLevel [Byte0]: 62
2638 00:42:44.399930 [Byte1]: 62
2639 00:42:44.399977
2640 00:42:44.400025 Set Vref, RX VrefLevel [Byte0]: 63
2641 00:42:44.400074 [Byte1]: 63
2642 00:42:44.400124
2643 00:42:44.400188 Set Vref, RX VrefLevel [Byte0]: 64
2644 00:42:44.400249 [Byte1]: 64
2645 00:42:44.400296
2646 00:42:44.400344 Set Vref, RX VrefLevel [Byte0]: 65
2647 00:42:44.400393 [Byte1]: 65
2648 00:42:44.400440
2649 00:42:44.400488 Set Vref, RX VrefLevel [Byte0]: 66
2650 00:42:44.400536 [Byte1]: 66
2651 00:42:44.400584
2652 00:42:44.400632 Final RX Vref Byte 0 = 46 to rank0
2653 00:42:44.400680 Final RX Vref Byte 1 = 49 to rank0
2654 00:42:44.400728 Final RX Vref Byte 0 = 46 to rank1
2655 00:42:44.400777 Final RX Vref Byte 1 = 49 to rank1==
2656 00:42:44.400826 Dram Type= 6, Freq= 0, CH_0, rank 0
2657 00:42:44.400875 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2658 00:42:44.400924 ==
2659 00:42:44.400972 DQS Delay:
2660 00:42:44.401020 DQS0 = 0, DQS1 = 0
2661 00:42:44.401069 DQM Delay:
2662 00:42:44.401117 DQM0 = 114, DQM1 = 105
2663 00:42:44.401165 DQ Delay:
2664 00:42:44.401213 DQ0 =110, DQ1 =114, DQ2 =112, DQ3 =108
2665 00:42:44.401261 DQ4 =118, DQ5 =106, DQ6 =124, DQ7 =120
2666 00:42:44.401309 DQ8 =94, DQ9 =88, DQ10 =106, DQ11 =96
2667 00:42:44.401358 DQ12 =114, DQ13 =112, DQ14 =118, DQ15 =116
2668 00:42:44.401406
2669 00:42:44.401453
2670 00:42:44.401500 [DQSOSCAuto] RK0, (LSB)MR18= 0x808, (MSB)MR19= 0x404, tDQSOscB0 = 406 ps tDQSOscB1 = 406 ps
2671 00:42:44.401550 CH0 RK0: MR19=404, MR18=808
2672 00:42:44.401597 CH0_RK0: MR19=0x404, MR18=0x808, DQSOSC=406, MR23=63, INC=39, DEC=26
2673 00:42:44.401645
2674 00:42:44.401692 ----->DramcWriteLeveling(PI) begin...
2675 00:42:44.401743 ==
2676 00:42:44.401791 Dram Type= 6, Freq= 0, CH_0, rank 1
2677 00:42:44.401840 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2678 00:42:44.401888 ==
2679 00:42:44.401936 Write leveling (Byte 0): 27 => 27
2680 00:42:44.401984 Write leveling (Byte 1): 26 => 26
2681 00:42:44.402032 DramcWriteLeveling(PI) end<-----
2682 00:42:44.402079
2683 00:42:44.402126 ==
2684 00:42:44.402174 Dram Type= 6, Freq= 0, CH_0, rank 1
2685 00:42:44.402252 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2686 00:42:44.402317 ==
2687 00:42:44.402365 [Gating] SW mode calibration
2688 00:42:44.402414 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2689 00:42:44.402464 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2690 00:42:44.402514 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2691 00:42:44.402562 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2692 00:42:44.402610 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2693 00:42:44.402659 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
2694 00:42:44.402707 0 11 16 | B1->B0 | 3434 3333 | 1 0 | (1 0) (0 0)
2695 00:42:44.402756 0 11 20 | B1->B0 | 2d2d 2424 | 0 0 | (0 1) (1 0)
2696 00:42:44.402805 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2697 00:42:44.402853 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2698 00:42:44.402901 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2699 00:42:44.402949 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2700 00:42:44.402997 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2701 00:42:44.403045 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2702 00:42:44.403093 0 12 16 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (1 1)
2703 00:42:44.403333 0 12 20 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
2704 00:42:44.403387 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2705 00:42:44.403436 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2706 00:42:44.403485 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2707 00:42:44.403534 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2708 00:42:44.403582 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2709 00:42:44.403631 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2710 00:42:44.403680 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2711 00:42:44.403728 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2712 00:42:44.403776 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2713 00:42:44.403824 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2714 00:42:44.403872 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2715 00:42:44.403920 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2716 00:42:44.403968 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2717 00:42:44.404016 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2718 00:42:44.404065 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2719 00:42:44.404114 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2720 00:42:44.404162 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2721 00:42:44.404210 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2722 00:42:44.404259 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2723 00:42:44.404306 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2724 00:42:44.404354 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2725 00:42:44.404402 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2726 00:42:44.404451 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2727 00:42:44.404499 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2728 00:42:44.404548 Total UI for P1: 0, mck2ui 16
2729 00:42:44.404597 best dqsien dly found for B0: ( 0, 15, 16)
2730 00:42:44.404645 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2731 00:42:44.404694 Total UI for P1: 0, mck2ui 16
2732 00:42:44.404742 best dqsien dly found for B1: ( 0, 15, 20)
2733 00:42:44.404789 best DQS0 dly(MCK, UI, PI) = (0, 15, 16)
2734 00:42:44.404837 best DQS1 dly(MCK, UI, PI) = (0, 15, 20)
2735 00:42:44.404885
2736 00:42:44.404933 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 16)
2737 00:42:44.404982 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 20)
2738 00:42:44.405029 [Gating] SW calibration Done
2739 00:42:44.405078 ==
2740 00:42:44.405125 Dram Type= 6, Freq= 0, CH_0, rank 1
2741 00:42:44.405174 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2742 00:42:44.405222 ==
2743 00:42:44.405270 RX Vref Scan: 0
2744 00:42:44.405318
2745 00:42:44.405367 RX Vref 0 -> 0, step: 1
2746 00:42:44.405414
2747 00:42:44.405461 RX Delay -40 -> 252, step: 8
2748 00:42:44.405509 iDelay=200, Bit 0, Center 107 (32 ~ 183) 152
2749 00:42:44.405558 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2750 00:42:44.405606 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2751 00:42:44.405653 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2752 00:42:44.405701 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2753 00:42:44.405749 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2754 00:42:44.405797 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
2755 00:42:44.405845 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2756 00:42:44.405893 iDelay=200, Bit 8, Center 91 (24 ~ 159) 136
2757 00:42:44.405941 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2758 00:42:44.405988 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
2759 00:42:44.406037 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2760 00:42:44.406084 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2761 00:42:44.406132 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2762 00:42:44.406179 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2763 00:42:44.406257 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2764 00:42:44.406320 ==
2765 00:42:44.406368 Dram Type= 6, Freq= 0, CH_0, rank 1
2766 00:42:44.406418 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2767 00:42:44.406467 ==
2768 00:42:44.406515 DQS Delay:
2769 00:42:44.406562 DQS0 = 0, DQS1 = 0
2770 00:42:44.406609 DQM Delay:
2771 00:42:44.406657 DQM0 = 114, DQM1 = 107
2772 00:42:44.406705 DQ Delay:
2773 00:42:44.406754 DQ0 =107, DQ1 =115, DQ2 =115, DQ3 =111
2774 00:42:44.406803 DQ4 =115, DQ5 =107, DQ6 =119, DQ7 =123
2775 00:42:44.406851 DQ8 =91, DQ9 =95, DQ10 =107, DQ11 =99
2776 00:42:44.406900 DQ12 =115, DQ13 =115, DQ14 =119, DQ15 =115
2777 00:42:44.406948
2778 00:42:44.406995
2779 00:42:44.407042 ==
2780 00:42:44.407090 Dram Type= 6, Freq= 0, CH_0, rank 1
2781 00:42:44.407138 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2782 00:42:44.407186 ==
2783 00:42:44.407233
2784 00:42:44.407280
2785 00:42:44.407328 TX Vref Scan disable
2786 00:42:44.407375 == TX Byte 0 ==
2787 00:42:44.407424 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2788 00:42:44.407472 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2789 00:42:44.407520 == TX Byte 1 ==
2790 00:42:44.407568 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
2791 00:42:44.407616 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
2792 00:42:44.407664 ==
2793 00:42:44.407712 Dram Type= 6, Freq= 0, CH_0, rank 1
2794 00:42:44.407760 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2795 00:42:44.407809 ==
2796 00:42:44.407856 TX Vref=22, minBit 5, minWin=25, winSum=419
2797 00:42:44.407905 TX Vref=24, minBit 8, minWin=25, winSum=421
2798 00:42:44.407953 TX Vref=26, minBit 10, minWin=25, winSum=431
2799 00:42:44.408001 TX Vref=28, minBit 10, minWin=26, winSum=432
2800 00:42:44.408049 TX Vref=30, minBit 9, minWin=26, winSum=432
2801 00:42:44.408098 TX Vref=32, minBit 10, minWin=26, winSum=436
2802 00:42:44.408147 [TxChooseVref] Worse bit 10, Min win 26, Win sum 436, Final Vref 32
2803 00:42:44.408195
2804 00:42:44.408243 Final TX Range 1 Vref 32
2805 00:42:44.408291
2806 00:42:44.408339 ==
2807 00:42:44.408387 Dram Type= 6, Freq= 0, CH_0, rank 1
2808 00:42:44.408435 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2809 00:42:44.408483 ==
2810 00:42:44.408531
2811 00:42:44.408578
2812 00:42:44.408626 TX Vref Scan disable
2813 00:42:44.408674 == TX Byte 0 ==
2814 00:42:44.408722 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2815 00:42:44.408770 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2816 00:42:44.408819 == TX Byte 1 ==
2817 00:42:44.408867 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
2818 00:42:44.408915 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
2819 00:42:44.408962
2820 00:42:44.409010 [DATLAT]
2821 00:42:44.409058 Freq=1200, CH0 RK1
2822 00:42:44.409107
2823 00:42:44.409343 DATLAT Default: 0xc
2824 00:42:44.409397 0, 0xFFFF, sum = 0
2825 00:42:44.409448 1, 0xFFFF, sum = 0
2826 00:42:44.409497 2, 0xFFFF, sum = 0
2827 00:42:44.409546 3, 0xFFFF, sum = 0
2828 00:42:44.409596 4, 0xFFFF, sum = 0
2829 00:42:44.409645 5, 0xFFFF, sum = 0
2830 00:42:44.409695 6, 0xFFFF, sum = 0
2831 00:42:44.409744 7, 0xFFFF, sum = 0
2832 00:42:44.409792 8, 0xFFFF, sum = 0
2833 00:42:44.409841 9, 0xFFFF, sum = 0
2834 00:42:44.409889 10, 0xFFFF, sum = 0
2835 00:42:44.409937 11, 0x0, sum = 1
2836 00:42:44.409987 12, 0x0, sum = 2
2837 00:42:44.410035 13, 0x0, sum = 3
2838 00:42:44.410135 14, 0x0, sum = 4
2839 00:42:44.410185 best_step = 12
2840 00:42:44.410255
2841 00:42:44.410304 ==
2842 00:42:44.410351 Dram Type= 6, Freq= 0, CH_0, rank 1
2843 00:42:44.410400 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2844 00:42:44.410449 ==
2845 00:42:44.410497 RX Vref Scan: 0
2846 00:42:44.410544
2847 00:42:44.410592 RX Vref 0 -> 0, step: 1
2848 00:42:44.410640
2849 00:42:44.410687 RX Delay -21 -> 252, step: 4
2850 00:42:44.410735 iDelay=195, Bit 0, Center 110 (39 ~ 182) 144
2851 00:42:44.410783 iDelay=195, Bit 1, Center 116 (43 ~ 190) 148
2852 00:42:44.410832 iDelay=195, Bit 2, Center 112 (43 ~ 182) 140
2853 00:42:44.410881 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
2854 00:42:44.410929 iDelay=195, Bit 4, Center 118 (47 ~ 190) 144
2855 00:42:44.410977 iDelay=195, Bit 5, Center 108 (39 ~ 178) 140
2856 00:42:44.411025 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
2857 00:42:44.411074 iDelay=195, Bit 7, Center 124 (55 ~ 194) 140
2858 00:42:44.411123 iDelay=195, Bit 8, Center 94 (31 ~ 158) 128
2859 00:42:44.411171 iDelay=195, Bit 9, Center 90 (27 ~ 154) 128
2860 00:42:44.411219 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
2861 00:42:44.411267 iDelay=195, Bit 11, Center 96 (35 ~ 158) 124
2862 00:42:44.411316 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
2863 00:42:44.411364 iDelay=195, Bit 13, Center 112 (47 ~ 178) 132
2864 00:42:44.411413 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
2865 00:42:44.411461 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
2866 00:42:44.411509 ==
2867 00:42:44.411558 Dram Type= 6, Freq= 0, CH_0, rank 1
2868 00:42:44.411606 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2869 00:42:44.411654 ==
2870 00:42:44.411702 DQS Delay:
2871 00:42:44.411751 DQS0 = 0, DQS1 = 0
2872 00:42:44.411800 DQM Delay:
2873 00:42:44.411847 DQM0 = 114, DQM1 = 105
2874 00:42:44.411895 DQ Delay:
2875 00:42:44.411943 DQ0 =110, DQ1 =116, DQ2 =112, DQ3 =108
2876 00:42:44.411991 DQ4 =118, DQ5 =108, DQ6 =122, DQ7 =124
2877 00:42:44.412039 DQ8 =94, DQ9 =90, DQ10 =110, DQ11 =96
2878 00:42:44.412112 DQ12 =112, DQ13 =112, DQ14 =118, DQ15 =114
2879 00:42:44.412173
2880 00:42:44.412220
2881 00:42:44.412267 [DQSOSCAuto] RK1, (LSB)MR18= 0x1010, (MSB)MR19= 0x404, tDQSOscB0 = 403 ps tDQSOscB1 = 403 ps
2882 00:42:44.412317 CH0 RK1: MR19=404, MR18=1010
2883 00:42:44.412365 CH0_RK1: MR19=0x404, MR18=0x1010, DQSOSC=403, MR23=63, INC=40, DEC=26
2884 00:42:44.412413 [RxdqsGatingPostProcess] freq 1200
2885 00:42:44.412461 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2886 00:42:44.412510 Pre-setting of DQS Precalculation
2887 00:42:44.412558 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
2888 00:42:44.412606 ==
2889 00:42:44.412654 Dram Type= 6, Freq= 0, CH_1, rank 0
2890 00:42:44.412703 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2891 00:42:44.412752 ==
2892 00:42:44.412800 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2893 00:42:44.412848 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2894 00:42:44.412897 [CA 0] Center 37 (7~67) winsize 61
2895 00:42:44.412946 [CA 1] Center 37 (7~68) winsize 62
2896 00:42:44.412993 [CA 2] Center 34 (3~65) winsize 63
2897 00:42:44.413041 [CA 3] Center 33 (3~64) winsize 62
2898 00:42:44.413090 [CA 4] Center 32 (1~63) winsize 63
2899 00:42:44.413139 [CA 5] Center 32 (2~63) winsize 62
2900 00:42:44.413187
2901 00:42:44.413234 [CmdBusTrainingLP45] Vref(ca) range 1: 39
2902 00:42:44.413282
2903 00:42:44.413329 [CATrainingPosCal] consider 1 rank data
2904 00:42:44.413378 u2DelayCellTimex100 = 270/100 ps
2905 00:42:44.413426 CA0 delay=37 (7~67),Diff = 5 PI (24 cell)
2906 00:42:44.413474 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
2907 00:42:44.413522 CA2 delay=34 (3~65),Diff = 2 PI (9 cell)
2908 00:42:44.413570 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2909 00:42:44.413619 CA4 delay=32 (1~63),Diff = 0 PI (0 cell)
2910 00:42:44.413668 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
2911 00:42:44.413716
2912 00:42:44.413763 CA PerBit enable=1, Macro0, CA PI delay=32
2913 00:42:44.413812
2914 00:42:44.413860 [CBTSetCACLKResult] CA Dly = 32
2915 00:42:44.413908 CS Dly: 6 (0~37)
2916 00:42:44.413955 ==
2917 00:42:44.414002 Dram Type= 6, Freq= 0, CH_1, rank 1
2918 00:42:44.414050 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2919 00:42:44.414099 ==
2920 00:42:44.414146 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2921 00:42:44.414195 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2922 00:42:44.414277 [CA 0] Center 36 (6~67) winsize 62
2923 00:42:44.414326 [CA 1] Center 37 (6~68) winsize 63
2924 00:42:44.414374 [CA 2] Center 33 (3~64) winsize 62
2925 00:42:44.414421 [CA 3] Center 33 (3~64) winsize 62
2926 00:42:44.414468 [CA 4] Center 32 (2~63) winsize 62
2927 00:42:44.414516 [CA 5] Center 32 (1~63) winsize 63
2928 00:42:44.414563
2929 00:42:44.541208 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2930 00:42:44.541379
2931 00:42:44.541480 [CATrainingPosCal] consider 2 rank data
2932 00:42:44.541578 u2DelayCellTimex100 = 270/100 ps
2933 00:42:44.541673 CA0 delay=37 (7~67),Diff = 5 PI (24 cell)
2934 00:42:44.541767 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
2935 00:42:44.541860 CA2 delay=33 (3~64),Diff = 1 PI (4 cell)
2936 00:42:44.541951 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2937 00:42:44.542042 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
2938 00:42:44.542131 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
2939 00:42:44.542337
2940 00:42:44.542432 CA PerBit enable=1, Macro0, CA PI delay=32
2941 00:42:44.542525
2942 00:42:44.542616 [CBTSetCACLKResult] CA Dly = 32
2943 00:42:44.542709 CS Dly: 6 (0~38)
2944 00:42:44.542808
2945 00:42:44.542918 ----->DramcWriteLeveling(PI) begin...
2946 00:42:44.543012 ==
2947 00:42:44.543102 Dram Type= 6, Freq= 0, CH_1, rank 0
2948 00:42:44.543193 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2949 00:42:44.543283 ==
2950 00:42:44.543373 Write leveling (Byte 0): 22 => 22
2951 00:42:44.543463 Write leveling (Byte 1): 24 => 24
2952 00:42:44.543552 DramcWriteLeveling(PI) end<-----
2953 00:42:44.543641
2954 00:42:44.543733 ==
2955 00:42:44.543825 Dram Type= 6, Freq= 0, CH_1, rank 0
2956 00:42:44.544137 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2957 00:42:44.544244 ==
2958 00:42:44.544345 [Gating] SW mode calibration
2959 00:42:44.544440 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2960 00:42:44.544533 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2961 00:42:44.544623 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2962 00:42:44.544714 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2963 00:42:44.544804 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2964 00:42:44.544893 0 11 12 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
2965 00:42:44.544983 0 11 16 | B1->B0 | 2d2d 2424 | 0 0 | (0 1) (1 0)
2966 00:42:44.545071 0 11 20 | B1->B0 | 2424 2323 | 1 0 | (1 0) (0 0)
2967 00:42:44.545160 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2968 00:42:44.545249 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2969 00:42:44.545338 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2970 00:42:44.545427 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2971 00:42:44.545516 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2972 00:42:44.545603 0 12 12 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
2973 00:42:44.545691 0 12 16 | B1->B0 | 2e2e 4646 | 0 0 | (0 0) (0 0)
2974 00:42:44.545779 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2975 00:42:44.545867 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2976 00:42:44.545954 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2977 00:42:44.546041 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2978 00:42:44.546129 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2979 00:42:44.546239 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2980 00:42:44.546341 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2981 00:42:44.546429 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2982 00:42:44.546517 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2983 00:42:44.546605 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2984 00:42:44.546693 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2985 00:42:44.546780 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2986 00:42:44.546869 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2987 00:42:44.546956 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2988 00:42:44.547045 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2989 00:42:44.547132 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2990 00:42:44.547220 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2991 00:42:44.547308 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2992 00:42:44.547396 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2993 00:42:44.547485 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2994 00:42:44.547573 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2995 00:42:44.547660 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2996 00:42:44.547748 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2997 00:42:44.547837 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2998 00:42:44.547924 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2999 00:42:44.548027 Total UI for P1: 0, mck2ui 16
3000 00:42:44.548130 best dqsien dly found for B0: ( 0, 15, 16)
3001 00:42:44.548219 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3002 00:42:44.548307 Total UI for P1: 0, mck2ui 16
3003 00:42:44.548396 best dqsien dly found for B1: ( 0, 15, 20)
3004 00:42:44.548484 best DQS0 dly(MCK, UI, PI) = (0, 15, 16)
3005 00:42:44.548572 best DQS1 dly(MCK, UI, PI) = (0, 15, 20)
3006 00:42:44.548659
3007 00:42:44.548745 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 16)
3008 00:42:44.548832 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 20)
3009 00:42:44.548919 [Gating] SW calibration Done
3010 00:42:44.549005 ==
3011 00:42:44.549093 Dram Type= 6, Freq= 0, CH_1, rank 0
3012 00:42:44.549181 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3013 00:42:44.549269 ==
3014 00:42:44.549356 RX Vref Scan: 0
3015 00:42:44.549443
3016 00:42:44.549531 RX Vref 0 -> 0, step: 1
3017 00:42:44.549618
3018 00:42:44.549705 RX Delay -40 -> 252, step: 8
3019 00:42:44.549793 iDelay=208, Bit 0, Center 119 (40 ~ 199) 160
3020 00:42:44.549882 iDelay=208, Bit 1, Center 107 (32 ~ 183) 152
3021 00:42:44.549971 iDelay=208, Bit 2, Center 103 (24 ~ 183) 160
3022 00:42:44.550058 iDelay=208, Bit 3, Center 111 (32 ~ 191) 160
3023 00:42:44.550146 iDelay=208, Bit 4, Center 111 (32 ~ 191) 160
3024 00:42:44.550270 iDelay=208, Bit 5, Center 127 (48 ~ 207) 160
3025 00:42:44.550341 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3026 00:42:44.550409 iDelay=208, Bit 7, Center 111 (32 ~ 191) 160
3027 00:42:44.550477 iDelay=208, Bit 8, Center 91 (24 ~ 159) 136
3028 00:42:44.550544 iDelay=208, Bit 9, Center 95 (24 ~ 167) 144
3029 00:42:44.550629 iDelay=208, Bit 10, Center 107 (32 ~ 183) 152
3030 00:42:44.550715 iDelay=208, Bit 11, Center 99 (32 ~ 167) 136
3031 00:42:44.550800 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3032 00:42:44.550885 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3033 00:42:44.550970 iDelay=208, Bit 14, Center 119 (48 ~ 191) 144
3034 00:42:44.551055 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3035 00:42:44.551139 ==
3036 00:42:44.551224 Dram Type= 6, Freq= 0, CH_1, rank 0
3037 00:42:44.551309 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3038 00:42:44.551394 ==
3039 00:42:44.551479 DQS Delay:
3040 00:42:44.551563 DQS0 = 0, DQS1 = 0
3041 00:42:44.551648 DQM Delay:
3042 00:42:44.551733 DQM0 = 114, DQM1 = 108
3043 00:42:44.551818 DQ Delay:
3044 00:42:44.551902 DQ0 =119, DQ1 =107, DQ2 =103, DQ3 =111
3045 00:42:44.551987 DQ4 =111, DQ5 =127, DQ6 =123, DQ7 =111
3046 00:42:44.552072 DQ8 =91, DQ9 =95, DQ10 =107, DQ11 =99
3047 00:42:44.552157 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3048 00:42:44.552283
3049 00:42:44.552367
3050 00:42:44.552451 ==
3051 00:42:44.552535 Dram Type= 6, Freq= 0, CH_1, rank 0
3052 00:42:44.552619 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3053 00:42:44.552704 ==
3054 00:42:44.552808
3055 00:42:44.552912
3056 00:42:44.552998 TX Vref Scan disable
3057 00:42:44.553083 == TX Byte 0 ==
3058 00:42:44.553176 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3059 00:42:44.553276 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3060 00:42:44.553362 == TX Byte 1 ==
3061 00:42:44.553642 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3062 00:42:44.553726 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3063 00:42:44.553812 ==
3064 00:42:44.553898 Dram Type= 6, Freq= 0, CH_1, rank 0
3065 00:42:44.553983 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3066 00:42:44.554068 ==
3067 00:42:44.554154 TX Vref=22, minBit 8, minWin=25, winSum=414
3068 00:42:44.554266 TX Vref=24, minBit 9, minWin=25, winSum=417
3069 00:42:44.554355 TX Vref=26, minBit 15, minWin=25, winSum=428
3070 00:42:44.554442 TX Vref=28, minBit 15, minWin=25, winSum=428
3071 00:42:44.554529 TX Vref=30, minBit 8, minWin=26, winSum=430
3072 00:42:44.554617 TX Vref=32, minBit 8, minWin=26, winSum=430
3073 00:42:44.554704 [TxChooseVref] Worse bit 8, Min win 26, Win sum 430, Final Vref 30
3074 00:42:44.554791
3075 00:42:44.554878 Final TX Range 1 Vref 30
3076 00:42:44.554964
3077 00:42:44.555050 ==
3078 00:42:44.555138 Dram Type= 6, Freq= 0, CH_1, rank 0
3079 00:42:44.555225 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3080 00:42:44.555312 ==
3081 00:42:44.555398
3082 00:42:44.555484
3083 00:42:44.555570 TX Vref Scan disable
3084 00:42:44.555656 == TX Byte 0 ==
3085 00:42:44.555743 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3086 00:42:44.555830 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3087 00:42:44.555917 == TX Byte 1 ==
3088 00:42:44.556004 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3089 00:42:44.556106 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3090 00:42:44.556208
3091 00:42:44.556296 [DATLAT]
3092 00:42:44.556383 Freq=1200, CH1 RK0
3093 00:42:44.556484
3094 00:42:44.556568 DATLAT Default: 0xd
3095 00:42:44.556653 0, 0xFFFF, sum = 0
3096 00:42:44.556739 1, 0xFFFF, sum = 0
3097 00:42:44.556829 2, 0xFFFF, sum = 0
3098 00:42:44.556912 3, 0xFFFF, sum = 0
3099 00:42:44.556992 4, 0xFFFF, sum = 0
3100 00:42:44.557070 5, 0xFFFF, sum = 0
3101 00:42:44.557149 6, 0xFFFF, sum = 0
3102 00:42:44.557227 7, 0xFFFF, sum = 0
3103 00:42:44.557306 8, 0xFFFF, sum = 0
3104 00:42:44.557384 9, 0xFFFF, sum = 0
3105 00:42:44.557462 10, 0xFFFF, sum = 0
3106 00:42:44.557540 11, 0x0, sum = 1
3107 00:42:44.557619 12, 0x0, sum = 2
3108 00:42:44.557697 13, 0x0, sum = 3
3109 00:42:44.557776 14, 0x0, sum = 4
3110 00:42:44.557855 best_step = 12
3111 00:42:44.557931
3112 00:42:44.558007 ==
3113 00:42:44.558084 Dram Type= 6, Freq= 0, CH_1, rank 0
3114 00:42:44.558178 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3115 00:42:44.558266 ==
3116 00:42:44.558368 RX Vref Scan: 1
3117 00:42:44.558455
3118 00:42:44.558540 Set Vref Range= 32 -> 127
3119 00:42:44.558625
3120 00:42:44.558709 RX Vref 32 -> 127, step: 1
3121 00:42:44.558794
3122 00:42:44.558878 RX Delay -21 -> 252, step: 4
3123 00:42:44.558963
3124 00:42:44.559047 Set Vref, RX VrefLevel [Byte0]: 32
3125 00:42:44.559132 [Byte1]: 32
3126 00:42:44.559216
3127 00:42:44.559301 Set Vref, RX VrefLevel [Byte0]: 33
3128 00:42:44.559385 [Byte1]: 33
3129 00:42:44.559470
3130 00:42:44.559554 Set Vref, RX VrefLevel [Byte0]: 34
3131 00:42:44.559640 [Byte1]: 34
3132 00:42:44.559724
3133 00:42:44.559807 Set Vref, RX VrefLevel [Byte0]: 35
3134 00:42:44.559892 [Byte1]: 35
3135 00:42:44.559976
3136 00:42:44.560059 Set Vref, RX VrefLevel [Byte0]: 36
3137 00:42:44.560144 [Byte1]: 36
3138 00:42:44.560228
3139 00:42:44.560313 Set Vref, RX VrefLevel [Byte0]: 37
3140 00:42:44.560398 [Byte1]: 37
3141 00:42:44.560482
3142 00:42:44.560567 Set Vref, RX VrefLevel [Byte0]: 38
3143 00:42:44.560652 [Byte1]: 38
3144 00:42:44.560736
3145 00:42:44.560820 Set Vref, RX VrefLevel [Byte0]: 39
3146 00:42:44.560905 [Byte1]: 39
3147 00:42:44.560989
3148 00:42:44.561074 Set Vref, RX VrefLevel [Byte0]: 40
3149 00:42:44.561158 [Byte1]: 40
3150 00:42:44.561242
3151 00:42:44.561326 Set Vref, RX VrefLevel [Byte0]: 41
3152 00:42:44.561411 [Byte1]: 41
3153 00:42:44.561495
3154 00:42:44.561579 Set Vref, RX VrefLevel [Byte0]: 42
3155 00:42:44.561664 [Byte1]: 42
3156 00:42:44.561748
3157 00:42:44.561833 Set Vref, RX VrefLevel [Byte0]: 43
3158 00:42:44.561917 [Byte1]: 43
3159 00:42:44.562002
3160 00:42:44.562086 Set Vref, RX VrefLevel [Byte0]: 44
3161 00:42:44.562170 [Byte1]: 44
3162 00:42:44.562293
3163 00:42:44.562378 Set Vref, RX VrefLevel [Byte0]: 45
3164 00:42:44.562462 [Byte1]: 45
3165 00:42:44.562547
3166 00:42:44.562631 Set Vref, RX VrefLevel [Byte0]: 46
3167 00:42:44.562716 [Byte1]: 46
3168 00:42:44.562799
3169 00:42:44.562883 Set Vref, RX VrefLevel [Byte0]: 47
3170 00:42:44.562968 [Byte1]: 47
3171 00:42:44.563053
3172 00:42:44.563136 Set Vref, RX VrefLevel [Byte0]: 48
3173 00:42:44.563221 [Byte1]: 48
3174 00:42:44.563305
3175 00:42:44.563389 Set Vref, RX VrefLevel [Byte0]: 49
3176 00:42:44.563473 [Byte1]: 49
3177 00:42:44.563557
3178 00:42:44.563641 Set Vref, RX VrefLevel [Byte0]: 50
3179 00:42:44.563726 [Byte1]: 50
3180 00:42:44.563810
3181 00:42:44.563895 Set Vref, RX VrefLevel [Byte0]: 51
3182 00:42:44.563979 [Byte1]: 51
3183 00:42:44.564063
3184 00:42:44.564147 Set Vref, RX VrefLevel [Byte0]: 52
3185 00:42:44.564231 [Byte1]: 52
3186 00:42:44.564315
3187 00:42:44.564400 Set Vref, RX VrefLevel [Byte0]: 53
3188 00:42:44.564484 [Byte1]: 53
3189 00:42:44.564568
3190 00:42:44.564652 Set Vref, RX VrefLevel [Byte0]: 54
3191 00:42:44.564736 [Byte1]: 54
3192 00:42:44.564820
3193 00:42:44.564905 Set Vref, RX VrefLevel [Byte0]: 55
3194 00:42:44.564990 [Byte1]: 55
3195 00:42:44.565074
3196 00:42:44.565157 Set Vref, RX VrefLevel [Byte0]: 56
3197 00:42:44.565242 [Byte1]: 56
3198 00:42:44.565326
3199 00:42:44.565411 Set Vref, RX VrefLevel [Byte0]: 57
3200 00:42:44.565495 [Byte1]: 57
3201 00:42:44.565580
3202 00:42:44.565664 Set Vref, RX VrefLevel [Byte0]: 58
3203 00:42:44.565748 [Byte1]: 58
3204 00:42:44.565832
3205 00:42:44.565916 Set Vref, RX VrefLevel [Byte0]: 59
3206 00:42:44.566001 [Byte1]: 59
3207 00:42:44.566084
3208 00:42:44.566169 Set Vref, RX VrefLevel [Byte0]: 60
3209 00:42:44.566289 [Byte1]: 60
3210 00:42:44.566374
3211 00:42:44.566458 Set Vref, RX VrefLevel [Byte0]: 61
3212 00:42:44.566543 [Byte1]: 61
3213 00:42:44.566627
3214 00:42:44.566712 Set Vref, RX VrefLevel [Byte0]: 62
3215 00:42:44.566797 [Byte1]: 62
3216 00:42:44.566881
3217 00:42:44.566966 Set Vref, RX VrefLevel [Byte0]: 63
3218 00:42:44.567050 [Byte1]: 63
3219 00:42:44.567134
3220 00:42:44.567218 Set Vref, RX VrefLevel [Byte0]: 64
3221 00:42:44.567302 [Byte1]: 64
3222 00:42:44.567386
3223 00:42:44.567470 Set Vref, RX VrefLevel [Byte0]: 65
3224 00:42:44.567555 [Byte1]: 65
3225 00:42:44.567639
3226 00:42:44.567723 Set Vref, RX VrefLevel [Byte0]: 66
3227 00:42:44.568010 [Byte1]: 66
3228 00:42:44.568093
3229 00:42:44.568179 Set Vref, RX VrefLevel [Byte0]: 67
3230 00:42:44.568264 [Byte1]: 67
3231 00:42:44.568349
3232 00:42:44.568434 Final RX Vref Byte 0 = 52 to rank0
3233 00:42:44.568520 Final RX Vref Byte 1 = 49 to rank0
3234 00:42:44.568605 Final RX Vref Byte 0 = 52 to rank1
3235 00:42:44.568691 Final RX Vref Byte 1 = 49 to rank1==
3236 00:42:44.568776 Dram Type= 6, Freq= 0, CH_1, rank 0
3237 00:42:44.568861 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3238 00:42:44.568947 ==
3239 00:42:44.569032 DQS Delay:
3240 00:42:44.569117 DQS0 = 0, DQS1 = 0
3241 00:42:44.569201 DQM Delay:
3242 00:42:44.569286 DQM0 = 113, DQM1 = 104
3243 00:42:44.569371 DQ Delay:
3244 00:42:44.569455 DQ0 =116, DQ1 =108, DQ2 =104, DQ3 =112
3245 00:42:44.569540 DQ4 =112, DQ5 =126, DQ6 =120, DQ7 =110
3246 00:42:44.569625 DQ8 =86, DQ9 =94, DQ10 =108, DQ11 =96
3247 00:42:44.569709 DQ12 =114, DQ13 =116, DQ14 =112, DQ15 =112
3248 00:42:44.569793
3249 00:42:44.569878
3250 00:42:44.569962 [DQSOSCAuto] RK0, (LSB)MR18= 0x1e1e, (MSB)MR19= 0x404, tDQSOscB0 = 398 ps tDQSOscB1 = 398 ps
3251 00:42:44.570048 CH1 RK0: MR19=404, MR18=1E1E
3252 00:42:44.570133 CH1_RK0: MR19=0x404, MR18=0x1E1E, DQSOSC=398, MR23=63, INC=41, DEC=27
3253 00:42:44.570224
3254 00:42:44.570344 ----->DramcWriteLeveling(PI) begin...
3255 00:42:44.570430 ==
3256 00:42:44.570515 Dram Type= 6, Freq= 0, CH_1, rank 1
3257 00:42:44.570599 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3258 00:42:44.570684 ==
3259 00:42:44.570768 Write leveling (Byte 0): 21 => 21
3260 00:42:44.570853 Write leveling (Byte 1): 21 => 21
3261 00:42:44.570937 DramcWriteLeveling(PI) end<-----
3262 00:42:44.571021
3263 00:42:44.571106 ==
3264 00:42:44.571190 Dram Type= 6, Freq= 0, CH_1, rank 1
3265 00:42:44.571274 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3266 00:42:44.571359 ==
3267 00:42:44.571444 [Gating] SW mode calibration
3268 00:42:44.571529 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3269 00:42:44.571615 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
3270 00:42:44.571700 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3271 00:42:44.571785 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3272 00:42:44.571870 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3273 00:42:44.571955 0 11 12 | B1->B0 | 3434 2f2f | 1 1 | (1 0) (1 0)
3274 00:42:44.572039 0 11 16 | B1->B0 | 2f2f 2323 | 0 0 | (0 1) (0 0)
3275 00:42:44.572124 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3276 00:42:44.572208 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3277 00:42:44.572294 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3278 00:42:44.572379 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3279 00:42:44.572464 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3280 00:42:44.572548 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3281 00:42:44.572632 0 12 12 | B1->B0 | 2323 3c3c | 0 0 | (0 0) (0 0)
3282 00:42:44.572717 0 12 16 | B1->B0 | 3535 4545 | 0 0 | (0 0) (0 0)
3283 00:42:44.572802 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3284 00:42:44.572887 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3285 00:42:44.572971 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3286 00:42:44.573056 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3287 00:42:44.573141 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3288 00:42:44.573225 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3289 00:42:44.573310 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3290 00:42:44.573394 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3291 00:42:44.573479 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3292 00:42:44.573563 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3293 00:42:44.573648 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3294 00:42:44.573733 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3295 00:42:44.573812 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3296 00:42:44.573891 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3297 00:42:44.573971 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3298 00:42:44.574055 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3299 00:42:44.574134 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3300 00:42:44.574229 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3301 00:42:44.574323 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3302 00:42:44.574400 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3303 00:42:44.574475 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3304 00:42:44.574550 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3305 00:42:44.574625 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3306 00:42:44.574717 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3307 00:42:44.574837 Total UI for P1: 0, mck2ui 16
3308 00:42:44.574914 best dqsien dly found for B0: ( 0, 15, 12)
3309 00:42:44.574989 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3310 00:42:44.575064 Total UI for P1: 0, mck2ui 16
3311 00:42:44.575138 best dqsien dly found for B1: ( 0, 15, 16)
3312 00:42:44.575212 best DQS0 dly(MCK, UI, PI) = (0, 15, 12)
3313 00:42:44.575287 best DQS1 dly(MCK, UI, PI) = (0, 15, 16)
3314 00:42:44.575361
3315 00:42:44.575435 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 12)
3316 00:42:44.575510 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 16)
3317 00:42:44.575584 [Gating] SW calibration Done
3318 00:42:44.575658 ==
3319 00:42:44.575732 Dram Type= 6, Freq= 0, CH_1, rank 1
3320 00:42:44.575806 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3321 00:42:44.575881 ==
3322 00:42:44.575955 RX Vref Scan: 0
3323 00:42:44.576028
3324 00:42:44.576106 RX Vref 0 -> 0, step: 1
3325 00:42:44.576180
3326 00:42:44.576256 RX Delay -40 -> 252, step: 8
3327 00:42:44.576332 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3328 00:42:44.576407 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3329 00:42:44.576482 iDelay=200, Bit 2, Center 107 (32 ~ 183) 152
3330 00:42:44.576560 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3331 00:42:44.576641 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3332 00:42:44.576716 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3333 00:42:44.576795 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3334 00:42:44.576870 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3335 00:42:44.577155 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
3336 00:42:44.577242 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3337 00:42:44.577321 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
3338 00:42:44.577398 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3339 00:42:44.577473 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3340 00:42:44.577549 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3341 00:42:44.577624 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
3342 00:42:44.577699 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
3343 00:42:44.577773 ==
3344 00:42:44.577848 Dram Type= 6, Freq= 0, CH_1, rank 1
3345 00:42:44.577922 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3346 00:42:44.577997 ==
3347 00:42:44.578072 DQS Delay:
3348 00:42:44.578146 DQS0 = 0, DQS1 = 0
3349 00:42:44.578228 DQM Delay:
3350 00:42:44.578338 DQM0 = 117, DQM1 = 107
3351 00:42:44.578412 DQ Delay:
3352 00:42:44.578486 DQ0 =119, DQ1 =111, DQ2 =107, DQ3 =119
3353 00:42:44.578562 DQ4 =119, DQ5 =123, DQ6 =123, DQ7 =115
3354 00:42:44.578637 DQ8 =91, DQ9 =95, DQ10 =103, DQ11 =103
3355 00:42:44.578712 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =115
3356 00:42:44.578786
3357 00:42:44.578859
3358 00:42:44.578955 ==
3359 00:42:44.579052 Dram Type= 6, Freq= 0, CH_1, rank 1
3360 00:42:44.579134 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3361 00:42:44.579211 ==
3362 00:42:44.579287
3363 00:42:44.579361
3364 00:42:44.579442 TX Vref Scan disable
3365 00:42:44.579534 == TX Byte 0 ==
3366 00:42:44.579610 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3367 00:42:44.579686 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3368 00:42:44.579762 == TX Byte 1 ==
3369 00:42:44.579836 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3370 00:42:44.579911 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3371 00:42:44.579986 ==
3372 00:42:44.580060 Dram Type= 6, Freq= 0, CH_1, rank 1
3373 00:42:44.580135 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3374 00:42:44.580210 ==
3375 00:42:44.580285 TX Vref=22, minBit 0, minWin=26, winSum=423
3376 00:42:44.580360 TX Vref=24, minBit 1, minWin=26, winSum=426
3377 00:42:44.580434 TX Vref=26, minBit 3, minWin=26, winSum=430
3378 00:42:44.580509 TX Vref=28, minBit 0, minWin=26, winSum=432
3379 00:42:44.580583 TX Vref=30, minBit 9, minWin=26, winSum=433
3380 00:42:44.580657 TX Vref=32, minBit 0, minWin=26, winSum=434
3381 00:42:44.580730 [TxChooseVref] Worse bit 0, Min win 26, Win sum 434, Final Vref 32
3382 00:42:44.580803
3383 00:42:44.580876 Final TX Range 1 Vref 32
3384 00:42:44.580948
3385 00:42:44.581020 ==
3386 00:42:44.581094 Dram Type= 6, Freq= 0, CH_1, rank 1
3387 00:42:44.581168 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3388 00:42:44.581242 ==
3389 00:42:44.581318
3390 00:42:44.581395
3391 00:42:44.581472 TX Vref Scan disable
3392 00:42:44.581549 == TX Byte 0 ==
3393 00:42:44.581627 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3394 00:42:44.581705 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3395 00:42:44.581783 == TX Byte 1 ==
3396 00:42:44.581859 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3397 00:42:44.581933 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3398 00:42:44.582010
3399 00:42:44.582091 [DATLAT]
3400 00:42:44.582175 Freq=1200, CH1 RK1
3401 00:42:44.582297
3402 00:42:44.582384 DATLAT Default: 0xc
3403 00:42:44.582496 0, 0xFFFF, sum = 0
3404 00:42:44.582607 1, 0xFFFF, sum = 0
3405 00:42:44.582704 2, 0xFFFF, sum = 0
3406 00:42:44.582801 3, 0xFFFF, sum = 0
3407 00:42:44.582889 4, 0xFFFF, sum = 0
3408 00:42:44.582971 5, 0xFFFF, sum = 0
3409 00:42:44.583050 6, 0xFFFF, sum = 0
3410 00:42:44.583129 7, 0xFFFF, sum = 0
3411 00:42:44.583207 8, 0xFFFF, sum = 0
3412 00:42:44.583285 9, 0xFFFF, sum = 0
3413 00:42:44.583364 10, 0xFFFF, sum = 0
3414 00:42:44.583443 11, 0x0, sum = 1
3415 00:42:44.583521 12, 0x0, sum = 2
3416 00:42:44.583598 13, 0x0, sum = 3
3417 00:42:44.583676 14, 0x0, sum = 4
3418 00:42:44.583753 best_step = 12
3419 00:42:44.583828
3420 00:42:44.583924 ==
3421 00:42:44.584002 Dram Type= 6, Freq= 0, CH_1, rank 1
3422 00:42:44.584079 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3423 00:42:44.584155 ==
3424 00:42:44.584231 RX Vref Scan: 0
3425 00:42:44.584307
3426 00:42:44.584382 RX Vref 0 -> 0, step: 1
3427 00:42:44.584457
3428 00:42:44.584532 RX Delay -29 -> 252, step: 4
3429 00:42:44.584608 iDelay=199, Bit 0, Center 116 (47 ~ 186) 140
3430 00:42:44.584685 iDelay=199, Bit 1, Center 110 (43 ~ 178) 136
3431 00:42:44.584762 iDelay=199, Bit 2, Center 108 (39 ~ 178) 140
3432 00:42:44.584838 iDelay=199, Bit 3, Center 112 (43 ~ 182) 140
3433 00:42:44.584915 iDelay=199, Bit 4, Center 116 (47 ~ 186) 140
3434 00:42:44.584991 iDelay=199, Bit 5, Center 126 (55 ~ 198) 144
3435 00:42:44.585067 iDelay=199, Bit 6, Center 124 (55 ~ 194) 140
3436 00:42:44.585143 iDelay=199, Bit 7, Center 112 (43 ~ 182) 140
3437 00:42:44.585220 iDelay=199, Bit 8, Center 88 (23 ~ 154) 132
3438 00:42:44.585296 iDelay=199, Bit 9, Center 90 (23 ~ 158) 136
3439 00:42:44.585372 iDelay=199, Bit 10, Center 106 (39 ~ 174) 136
3440 00:42:44.585448 iDelay=199, Bit 11, Center 98 (31 ~ 166) 136
3441 00:42:44.585525 iDelay=199, Bit 12, Center 114 (47 ~ 182) 136
3442 00:42:44.585601 iDelay=199, Bit 13, Center 112 (47 ~ 178) 132
3443 00:42:44.585677 iDelay=199, Bit 14, Center 114 (47 ~ 182) 136
3444 00:42:44.585752 iDelay=199, Bit 15, Center 112 (47 ~ 178) 132
3445 00:42:44.585829 ==
3446 00:42:44.585905 Dram Type= 6, Freq= 0, CH_1, rank 1
3447 00:42:44.585982 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3448 00:42:44.586058 ==
3449 00:42:44.586133 DQS Delay:
3450 00:42:44.586214 DQS0 = 0, DQS1 = 0
3451 00:42:44.586325 DQM Delay:
3452 00:42:44.586401 DQM0 = 115, DQM1 = 104
3453 00:42:44.586477 DQ Delay:
3454 00:42:44.586554 DQ0 =116, DQ1 =110, DQ2 =108, DQ3 =112
3455 00:42:44.586631 DQ4 =116, DQ5 =126, DQ6 =124, DQ7 =112
3456 00:42:44.586707 DQ8 =88, DQ9 =90, DQ10 =106, DQ11 =98
3457 00:42:44.586783 DQ12 =114, DQ13 =112, DQ14 =114, DQ15 =112
3458 00:42:44.586858
3459 00:42:44.586933
3460 00:42:44.587010 [DQSOSCAuto] RK1, (LSB)MR18= 0xe0e, (MSB)MR19= 0x404, tDQSOscB0 = 404 ps tDQSOscB1 = 404 ps
3461 00:42:44.587087 CH1 RK1: MR19=404, MR18=E0E
3462 00:42:44.587165 CH1_RK1: MR19=0x404, MR18=0xE0E, DQSOSC=404, MR23=63, INC=40, DEC=26
3463 00:42:44.587241 [RxdqsGatingPostProcess] freq 1200
3464 00:42:44.587318 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
3465 00:42:44.587394 Pre-setting of DQS Precalculation
3466 00:42:44.587470 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
3467 00:42:44.587548 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3468 00:42:44.587626 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3469 00:42:44.587701
3470 00:42:44.587776
3471 00:42:44.587851 [Calibration Summary] 2400 Mbps
3472 00:42:44.588128 CH 0, Rank 0
3473 00:42:44.588211 SW Impedance : PASS
3474 00:42:44.588289 DUTY Scan : NO K
3475 00:42:44.588370 ZQ Calibration : PASS
3476 00:42:44.588455 Jitter Meter : NO K
3477 00:42:44.588614 CBT Training : PASS
3478 00:42:44.588713 Write leveling : PASS
3479 00:42:44.588806 RX DQS gating : PASS
3480 00:42:44.588887 RX DQ/DQS(RDDQC) : PASS
3481 00:42:44.589043 TX DQ/DQS : PASS
3482 00:42:44.589153 RX DATLAT : PASS
3483 00:42:44.589242 RX DQ/DQS(Engine): PASS
3484 00:42:44.589320 TX OE : NO K
3485 00:42:44.589396 All Pass.
3486 00:42:44.589471
3487 00:42:44.589547 CH 0, Rank 1
3488 00:42:44.589624 SW Impedance : PASS
3489 00:42:44.589699 DUTY Scan : NO K
3490 00:42:44.589775 ZQ Calibration : PASS
3491 00:42:44.589851 Jitter Meter : NO K
3492 00:42:44.589927 CBT Training : PASS
3493 00:42:44.590002 Write leveling : PASS
3494 00:42:44.590079 RX DQS gating : PASS
3495 00:42:44.590155 RX DQ/DQS(RDDQC) : PASS
3496 00:42:44.590249 TX DQ/DQS : PASS
3497 00:42:44.590315 RX DATLAT : PASS
3498 00:42:44.590364 RX DQ/DQS(Engine): PASS
3499 00:42:44.590412 TX OE : NO K
3500 00:42:44.590461 All Pass.
3501 00:42:44.590510
3502 00:42:44.590557 CH 1, Rank 0
3503 00:42:44.590605 SW Impedance : PASS
3504 00:42:44.590653 DUTY Scan : NO K
3505 00:42:44.590701 ZQ Calibration : PASS
3506 00:42:44.590750 Jitter Meter : NO K
3507 00:42:44.590797 CBT Training : PASS
3508 00:42:44.590845 Write leveling : PASS
3509 00:42:44.590893 RX DQS gating : PASS
3510 00:42:44.590941 RX DQ/DQS(RDDQC) : PASS
3511 00:42:44.590989 TX DQ/DQS : PASS
3512 00:42:44.591037 RX DATLAT : PASS
3513 00:42:44.591084 RX DQ/DQS(Engine): PASS
3514 00:42:44.591132 TX OE : NO K
3515 00:42:44.591180 All Pass.
3516 00:42:44.591228
3517 00:42:44.591284 CH 1, Rank 1
3518 00:42:44.591343 SW Impedance : PASS
3519 00:42:44.591399 DUTY Scan : NO K
3520 00:42:44.591469 ZQ Calibration : PASS
3521 00:42:44.591525 Jitter Meter : NO K
3522 00:42:44.591587 CBT Training : PASS
3523 00:42:44.591725 Write leveling : PASS
3524 00:42:44.591856 RX DQS gating : PASS
3525 00:42:44.591940 RX DQ/DQS(RDDQC) : PASS
3526 00:42:44.591992 TX DQ/DQS : PASS
3527 00:42:44.592048 RX DATLAT : PASS
3528 00:42:44.592103 RX DQ/DQS(Engine): PASS
3529 00:42:44.592162 TX OE : NO K
3530 00:42:44.592219 All Pass.
3531 00:42:44.592281
3532 00:42:44.592336 DramC Write-DBI off
3533 00:42:44.592394 PER_BANK_REFRESH: Hybrid Mode
3534 00:42:44.592451 TX_TRACKING: ON
3535 00:42:44.592507 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3536 00:42:44.592570 [FAST_K] Save calibration result to emmc
3537 00:42:44.592628 dramc_set_vcore_voltage set vcore to 650000
3538 00:42:44.592684 Read voltage for 600, 5
3539 00:42:44.592741 Vio18 = 0
3540 00:42:44.592796 Vcore = 650000
3541 00:42:44.592852 Vdram = 0
3542 00:42:44.592913 Vddq = 0
3543 00:42:44.592962 Vmddr = 0
3544 00:42:44.593030 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3545 00:42:44.593088 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3546 00:42:44.593147 MEM_TYPE=3, freq_sel=19
3547 00:42:44.593203 sv_algorithm_assistance_LP4_1600
3548 00:42:44.593261 ============ PULL DRAM RESETB DOWN ============
3549 00:42:44.593318 ========== PULL DRAM RESETB DOWN end =========
3550 00:42:44.593374 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3551 00:42:44.593432 ===================================
3552 00:42:44.593487 LPDDR4 DRAM CONFIGURATION
3553 00:42:44.593544 ===================================
3554 00:42:44.593606 EX_ROW_EN[0] = 0x0
3555 00:42:44.593660 EX_ROW_EN[1] = 0x0
3556 00:42:44.593712 LP4Y_EN = 0x0
3557 00:42:44.593760 WORK_FSP = 0x0
3558 00:42:44.593809 WL = 0x2
3559 00:42:44.593857 RL = 0x2
3560 00:42:44.593911 BL = 0x2
3561 00:42:44.593966 RPST = 0x0
3562 00:42:44.594022 RD_PRE = 0x0
3563 00:42:44.594077 WR_PRE = 0x1
3564 00:42:44.594132 WR_PST = 0x0
3565 00:42:44.594188 DBI_WR = 0x0
3566 00:42:44.594278 DBI_RD = 0x0
3567 00:42:44.594353 OTF = 0x1
3568 00:42:44.594409 ===================================
3569 00:42:44.594465 ===================================
3570 00:42:44.594524 ANA top config
3571 00:42:44.594580 ===================================
3572 00:42:44.594645 DLL_ASYNC_EN = 0
3573 00:42:44.594702 ALL_SLAVE_EN = 1
3574 00:42:44.594760 NEW_RANK_MODE = 1
3575 00:42:44.594817 DLL_IDLE_MODE = 1
3576 00:42:44.594873 LP45_APHY_COMB_EN = 1
3577 00:42:44.594928 TX_ODT_DIS = 1
3578 00:42:44.594986 NEW_8X_MODE = 1
3579 00:42:44.595045 ===================================
3580 00:42:44.595101 ===================================
3581 00:42:44.595158 data_rate = 1200
3582 00:42:44.595213 CKR = 1
3583 00:42:44.595269 DQ_P2S_RATIO = 8
3584 00:42:44.595329 ===================================
3585 00:42:44.595386 CA_P2S_RATIO = 8
3586 00:42:44.595437 DQ_CA_OPEN = 0
3587 00:42:44.595496 DQ_SEMI_OPEN = 0
3588 00:42:44.595637 CA_SEMI_OPEN = 0
3589 00:42:44.595776 CA_FULL_RATE = 0
3590 00:42:44.595875 DQ_CKDIV4_EN = 1
3591 00:42:44.596028 CA_CKDIV4_EN = 1
3592 00:42:44.596124 CA_PREDIV_EN = 0
3593 00:42:44.596180 PH8_DLY = 0
3594 00:42:44.596238 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3595 00:42:44.596301 DQ_AAMCK_DIV = 4
3596 00:42:44.596352 CA_AAMCK_DIV = 4
3597 00:42:44.596401 CA_ADMCK_DIV = 4
3598 00:42:44.596449 DQ_TRACK_CA_EN = 0
3599 00:42:44.596498 CA_PICK = 600
3600 00:42:44.596546 CA_MCKIO = 600
3601 00:42:44.596595 MCKIO_SEMI = 0
3602 00:42:44.596644 PLL_FREQ = 2288
3603 00:42:44.596692 DQ_UI_PI_RATIO = 32
3604 00:42:44.596740 CA_UI_PI_RATIO = 0
3605 00:42:44.596789 ===================================
3606 00:42:44.596838 ===================================
3607 00:42:44.596887 memory_type:LPDDR4
3608 00:42:44.596935 GP_NUM : 10
3609 00:42:44.596984 SRAM_EN : 1
3610 00:42:44.597031 MD32_EN : 0
3611 00:42:44.597080 ===================================
3612 00:42:44.597128 [ANA_INIT] >>>>>>>>>>>>>>
3613 00:42:44.597177 <<<<<< [CONFIGURE PHASE]: ANA_TX
3614 00:42:44.597226 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3615 00:42:44.597275 ===================================
3616 00:42:44.597323 data_rate = 1200,PCW = 0X5800
3617 00:42:44.597373 ===================================
3618 00:42:44.597421 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3619 00:42:44.597470 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3620 00:42:44.597713 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3621 00:42:44.597771 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3622 00:42:44.597823 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3623 00:42:44.597872 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3624 00:42:44.597921 [ANA_INIT] flow start
3625 00:42:44.597969 [ANA_INIT] PLL >>>>>>>>
3626 00:42:44.598018 [ANA_INIT] PLL <<<<<<<<
3627 00:42:44.598068 [ANA_INIT] MIDPI >>>>>>>>
3628 00:42:44.598116 [ANA_INIT] MIDPI <<<<<<<<
3629 00:42:44.598164 [ANA_INIT] DLL >>>>>>>>
3630 00:42:44.598218 [ANA_INIT] flow end
3631 00:42:44.598301 ============ LP4 DIFF to SE enter ============
3632 00:42:44.598351 ============ LP4 DIFF to SE exit ============
3633 00:42:44.598400 [ANA_INIT] <<<<<<<<<<<<<
3634 00:42:44.598449 [Flow] Enable top DCM control >>>>>
3635 00:42:44.598498 [Flow] Enable top DCM control <<<<<
3636 00:42:44.598568 Enable DLL master slave shuffle
3637 00:42:44.598619 ==============================================================
3638 00:42:44.598692 Gating Mode config
3639 00:42:44.598855 ==============================================================
3640 00:42:44.598954 Config description:
3641 00:42:44.599025 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3642 00:42:44.599087 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3643 00:42:44.599150 SELPH_MODE 0: By rank 1: By Phase
3644 00:42:44.599211 ==============================================================
3645 00:42:44.599262 GAT_TRACK_EN = 1
3646 00:42:44.599310 RX_GATING_MODE = 2
3647 00:42:44.599359 RX_GATING_TRACK_MODE = 2
3648 00:42:44.599407 SELPH_MODE = 1
3649 00:42:44.599455 PICG_EARLY_EN = 1
3650 00:42:44.599503 VALID_LAT_VALUE = 1
3651 00:42:44.599551 ==============================================================
3652 00:42:44.599601 Enter into Gating configuration >>>>
3653 00:42:44.599651 Exit from Gating configuration <<<<
3654 00:42:44.599700 Enter into DVFS_PRE_config >>>>>
3655 00:42:44.599749 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3656 00:42:44.599800 Exit from DVFS_PRE_config <<<<<
3657 00:42:44.599848 Enter into PICG configuration >>>>
3658 00:42:44.599897 Exit from PICG configuration <<<<
3659 00:42:44.599945 [RX_INPUT] configuration >>>>>
3660 00:42:44.599994 [RX_INPUT] configuration <<<<<
3661 00:42:44.600042 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3662 00:42:44.600091 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3663 00:42:44.600140 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3664 00:42:44.600190 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3665 00:42:44.600239 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3666 00:42:44.600288 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3667 00:42:44.600337 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3668 00:42:44.600386 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3669 00:42:44.600435 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3670 00:42:44.600484 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3671 00:42:44.600532 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3672 00:42:44.600580 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3673 00:42:44.600628 ===================================
3674 00:42:44.600677 LPDDR4 DRAM CONFIGURATION
3675 00:42:44.600725 ===================================
3676 00:42:44.600773 EX_ROW_EN[0] = 0x0
3677 00:42:44.600822 EX_ROW_EN[1] = 0x0
3678 00:42:44.600870 LP4Y_EN = 0x0
3679 00:42:44.600918 WORK_FSP = 0x0
3680 00:42:44.600966 WL = 0x2
3681 00:42:44.601014 RL = 0x2
3682 00:42:44.601061 BL = 0x2
3683 00:42:44.601110 RPST = 0x0
3684 00:42:44.601158 RD_PRE = 0x0
3685 00:42:44.601205 WR_PRE = 0x1
3686 00:42:44.601253 WR_PST = 0x0
3687 00:42:44.601302 DBI_WR = 0x0
3688 00:42:44.601350 DBI_RD = 0x0
3689 00:42:44.601399 OTF = 0x1
3690 00:42:44.601448 ===================================
3691 00:42:44.601497 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3692 00:42:44.601546 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3693 00:42:44.601594 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3694 00:42:44.601643 ===================================
3695 00:42:44.601692 LPDDR4 DRAM CONFIGURATION
3696 00:42:44.601739 ===================================
3697 00:42:44.601789 EX_ROW_EN[0] = 0x10
3698 00:42:44.601837 EX_ROW_EN[1] = 0x0
3699 00:42:44.601885 LP4Y_EN = 0x0
3700 00:42:44.601933 WORK_FSP = 0x0
3701 00:42:44.601992 WL = 0x2
3702 00:42:44.602146 RL = 0x2
3703 00:42:44.602277 BL = 0x2
3704 00:42:44.602336 RPST = 0x0
3705 00:42:44.602387 RD_PRE = 0x0
3706 00:42:44.602436 WR_PRE = 0x1
3707 00:42:44.602483 WR_PST = 0x0
3708 00:42:44.602531 DBI_WR = 0x0
3709 00:42:44.602579 DBI_RD = 0x0
3710 00:42:44.602627 OTF = 0x1
3711 00:42:44.602676 ===================================
3712 00:42:44.602725 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3713 00:42:44.602774 nWR fixed to 30
3714 00:42:44.602822 [ModeRegInit_LP4] CH0 RK0
3715 00:42:44.602871 [ModeRegInit_LP4] CH0 RK1
3716 00:42:44.602918 [ModeRegInit_LP4] CH1 RK0
3717 00:42:44.602966 [ModeRegInit_LP4] CH1 RK1
3718 00:42:44.603015 match AC timing 16
3719 00:42:44.603063 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 0
3720 00:42:44.603112 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3721 00:42:44.603161 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3722 00:42:44.603209 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3723 00:42:44.603258 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3724 00:42:44.603306 ==
3725 00:42:44.603354 Dram Type= 6, Freq= 0, CH_0, rank 0
3726 00:42:44.603402 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3727 00:42:44.603451 ==
3728 00:42:44.603691 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3729 00:42:44.603746 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3730 00:42:44.603797 [CA 0] Center 36 (6~66) winsize 61
3731 00:42:44.603846 [CA 1] Center 35 (5~66) winsize 62
3732 00:42:44.603895 [CA 2] Center 34 (4~65) winsize 62
3733 00:42:44.603944 [CA 3] Center 34 (3~65) winsize 63
3734 00:42:44.603993 [CA 4] Center 33 (3~64) winsize 62
3735 00:42:44.604042 [CA 5] Center 33 (2~64) winsize 63
3736 00:42:44.604090
3737 00:42:44.604138 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3738 00:42:44.604186
3739 00:42:44.604234 [CATrainingPosCal] consider 1 rank data
3740 00:42:44.604283 u2DelayCellTimex100 = 270/100 ps
3741 00:42:44.604330 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3742 00:42:44.604379 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3743 00:42:44.604428 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3744 00:42:44.604477 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3745 00:42:44.604525 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3746 00:42:44.604573 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
3747 00:42:44.604621
3748 00:42:44.604669 CA PerBit enable=1, Macro0, CA PI delay=33
3749 00:42:44.604718
3750 00:42:44.604765 [CBTSetCACLKResult] CA Dly = 33
3751 00:42:44.604813 CS Dly: 5 (0~36)
3752 00:42:44.604861 ==
3753 00:42:44.604910 Dram Type= 6, Freq= 0, CH_0, rank 1
3754 00:42:44.604959 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3755 00:42:44.605008 ==
3756 00:42:44.605056 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3757 00:42:44.605104 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3758 00:42:44.605153 [CA 0] Center 35 (5~66) winsize 62
3759 00:42:44.605201 [CA 1] Center 35 (5~66) winsize 62
3760 00:42:44.605248 [CA 2] Center 34 (4~65) winsize 62
3761 00:42:44.605296 [CA 3] Center 34 (4~65) winsize 62
3762 00:42:44.605345 [CA 4] Center 33 (3~64) winsize 62
3763 00:42:44.605393 [CA 5] Center 33 (3~64) winsize 62
3764 00:42:44.605441
3765 00:42:44.605488 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3766 00:42:44.605536
3767 00:42:44.605584 [CATrainingPosCal] consider 2 rank data
3768 00:42:44.605633 u2DelayCellTimex100 = 270/100 ps
3769 00:42:44.605681 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3770 00:42:44.605730 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3771 00:42:44.605778 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3772 00:42:44.605827 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3773 00:42:44.605875 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3774 00:42:44.605923 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3775 00:42:44.605971
3776 00:42:44.606019 CA PerBit enable=1, Macro0, CA PI delay=33
3777 00:42:44.606067
3778 00:42:44.606115 [CBTSetCACLKResult] CA Dly = 33
3779 00:42:44.606163 CS Dly: 4 (0~35)
3780 00:42:44.606215
3781 00:42:44.606304 ----->DramcWriteLeveling(PI) begin...
3782 00:42:44.606355 ==
3783 00:42:44.606403 Dram Type= 6, Freq= 0, CH_0, rank 0
3784 00:42:44.606451 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3785 00:42:44.606500 ==
3786 00:42:44.606549 Write leveling (Byte 0): 30 => 30
3787 00:42:44.606598 Write leveling (Byte 1): 31 => 31
3788 00:42:44.606646 DramcWriteLeveling(PI) end<-----
3789 00:42:44.606695
3790 00:42:44.606742 ==
3791 00:42:44.606790 Dram Type= 6, Freq= 0, CH_0, rank 0
3792 00:42:44.606839 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3793 00:42:44.606887 ==
3794 00:42:44.606935 [Gating] SW mode calibration
3795 00:42:44.606984 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3796 00:42:44.607033 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
3797 00:42:44.607081 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3798 00:42:44.607130 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3799 00:42:44.607179 0 5 8 | B1->B0 | 3131 3030 | 0 0 | (0 1) (0 1)
3800 00:42:44.607228 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3801 00:42:44.607277 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3802 00:42:44.607326 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3803 00:42:44.607375 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3804 00:42:44.607423 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3805 00:42:44.607471 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3806 00:42:44.607520 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3807 00:42:44.607569 0 6 8 | B1->B0 | 2727 3030 | 0 0 | (0 0) (0 0)
3808 00:42:44.607618 0 6 12 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
3809 00:42:44.607667 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3810 00:42:44.607716 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3811 00:42:44.607764 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3812 00:42:44.607813 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3813 00:42:44.607861 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3814 00:42:44.607909 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3815 00:42:44.607957 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3816 00:42:44.608006 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3817 00:42:44.608054 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3818 00:42:44.608102 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3819 00:42:44.608151 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3820 00:42:44.608199 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3821 00:42:44.608246 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3822 00:42:44.608295 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3823 00:42:44.608344 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3824 00:42:44.608392 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3825 00:42:44.608441 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3826 00:42:44.608489 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3827 00:42:44.608537 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3828 00:42:44.608585 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3829 00:42:44.608633 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3830 00:42:44.608681 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3831 00:42:44.608730 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3832 00:42:44.608778 Total UI for P1: 0, mck2ui 16
3833 00:42:44.608827 best dqsien dly found for B0: ( 0, 9, 6)
3834 00:42:44.609062 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3835 00:42:44.609118 Total UI for P1: 0, mck2ui 16
3836 00:42:44.609168 best dqsien dly found for B1: ( 0, 9, 8)
3837 00:42:44.609217 best DQS0 dly(MCK, UI, PI) = (0, 9, 6)
3838 00:42:44.609267 best DQS1 dly(MCK, UI, PI) = (0, 9, 8)
3839 00:42:44.609315
3840 00:42:44.609363 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 6)
3841 00:42:44.609412 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 8)
3842 00:42:44.609461 [Gating] SW calibration Done
3843 00:42:44.609508 ==
3844 00:42:44.609556 Dram Type= 6, Freq= 0, CH_0, rank 0
3845 00:42:44.609604 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3846 00:42:44.609653 ==
3847 00:42:44.609701 RX Vref Scan: 0
3848 00:42:44.609748
3849 00:42:44.609796 RX Vref 0 -> 0, step: 1
3850 00:42:44.609844
3851 00:42:44.609892 RX Delay -230 -> 252, step: 16
3852 00:42:44.609941 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
3853 00:42:44.609989 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
3854 00:42:44.610037 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
3855 00:42:44.616145 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
3856 00:42:44.619328 iDelay=218, Bit 4, Center 41 (-134 ~ 217) 352
3857 00:42:44.622574 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
3858 00:42:44.625829 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
3859 00:42:44.629462 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
3860 00:42:44.636344 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
3861 00:42:44.639283 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
3862 00:42:44.643004 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
3863 00:42:44.646267 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
3864 00:42:44.652643 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
3865 00:42:44.655970 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
3866 00:42:44.659193 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
3867 00:42:44.662861 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
3868 00:42:44.663204 ==
3869 00:42:44.666035 Dram Type= 6, Freq= 0, CH_0, rank 0
3870 00:42:44.672798 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3871 00:42:44.673616 ==
3872 00:42:44.674173 DQS Delay:
3873 00:42:44.675928 DQS0 = 0, DQS1 = 0
3874 00:42:44.676258 DQM Delay:
3875 00:42:44.676515 DQM0 = 38, DQM1 = 33
3876 00:42:44.679194 DQ Delay:
3877 00:42:44.682724 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
3878 00:42:44.686171 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
3879 00:42:44.689371 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
3880 00:42:44.692744 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
3881 00:42:44.693084
3882 00:42:44.693342
3883 00:42:44.693568 ==
3884 00:42:44.695813 Dram Type= 6, Freq= 0, CH_0, rank 0
3885 00:42:44.699011 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3886 00:42:44.699164 ==
3887 00:42:44.699262
3888 00:42:44.699353
3889 00:42:44.702132 TX Vref Scan disable
3890 00:42:44.705338 == TX Byte 0 ==
3891 00:42:44.708620 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
3892 00:42:44.712126 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
3893 00:42:44.715369 == TX Byte 1 ==
3894 00:42:44.718657 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
3895 00:42:44.722199 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
3896 00:42:44.722294 ==
3897 00:42:44.725324 Dram Type= 6, Freq= 0, CH_0, rank 0
3898 00:42:44.728600 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3899 00:42:44.731946 ==
3900 00:42:44.732042
3901 00:42:44.732103
3902 00:42:44.732157 TX Vref Scan disable
3903 00:42:44.735622 == TX Byte 0 ==
3904 00:42:44.739055 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
3905 00:42:44.745700 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
3906 00:42:44.745791 == TX Byte 1 ==
3907 00:42:44.748938 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
3908 00:42:44.755740 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
3909 00:42:44.755817
3910 00:42:44.755875 [DATLAT]
3911 00:42:44.755930 Freq=600, CH0 RK0
3912 00:42:44.755983
3913 00:42:44.759289 DATLAT Default: 0x9
3914 00:42:44.759365 0, 0xFFFF, sum = 0
3915 00:42:44.762504 1, 0xFFFF, sum = 0
3916 00:42:44.762581 2, 0xFFFF, sum = 0
3917 00:42:44.765624 3, 0xFFFF, sum = 0
3918 00:42:44.768900 4, 0xFFFF, sum = 0
3919 00:42:44.768978 5, 0xFFFF, sum = 0
3920 00:42:44.772244 6, 0xFFFF, sum = 0
3921 00:42:44.772322 7, 0x0, sum = 1
3922 00:42:44.772381 8, 0x0, sum = 2
3923 00:42:44.775911 9, 0x0, sum = 3
3924 00:42:44.846381 10, 0x0, sum = 4
3925 00:42:44.846692 best_step = 8
3926 00:42:44.846757
3927 00:42:44.846817 ==
3928 00:42:44.846871 Dram Type= 6, Freq= 0, CH_0, rank 0
3929 00:42:44.846923 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3930 00:42:44.846975 ==
3931 00:42:44.847025 RX Vref Scan: 1
3932 00:42:44.847074
3933 00:42:44.847124 RX Vref 0 -> 0, step: 1
3934 00:42:44.847172
3935 00:42:44.847222 RX Delay -195 -> 252, step: 8
3936 00:42:44.847271
3937 00:42:44.847318 Set Vref, RX VrefLevel [Byte0]: 46
3938 00:42:44.847367 [Byte1]: 49
3939 00:42:44.847415
3940 00:42:44.847464 Final RX Vref Byte 0 = 46 to rank0
3941 00:42:44.847513 Final RX Vref Byte 1 = 49 to rank0
3942 00:42:44.847561 Final RX Vref Byte 0 = 46 to rank1
3943 00:42:44.847626 Final RX Vref Byte 1 = 49 to rank1==
3944 00:42:44.847675 Dram Type= 6, Freq= 0, CH_0, rank 0
3945 00:42:44.847724 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3946 00:42:44.847773 ==
3947 00:42:44.847821 DQS Delay:
3948 00:42:44.847869 DQS0 = 0, DQS1 = 0
3949 00:42:44.847917 DQM Delay:
3950 00:42:44.847966 DQM0 = 40, DQM1 = 30
3951 00:42:44.848013 DQ Delay:
3952 00:42:44.848061 DQ0 =36, DQ1 =40, DQ2 =36, DQ3 =36
3953 00:42:44.848109 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =48
3954 00:42:44.848157 DQ8 =20, DQ9 =16, DQ10 =28, DQ11 =20
3955 00:42:44.848204 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
3956 00:42:44.848251
3957 00:42:44.848299
3958 00:42:44.848984 [DQSOSCAuto] RK0, (LSB)MR18= 0x6060, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 391 ps
3959 00:42:44.852242 CH0 RK0: MR19=808, MR18=6060
3960 00:42:44.858861 CH0_RK0: MR19=0x808, MR18=0x6060, DQSOSC=391, MR23=63, INC=171, DEC=114
3961 00:42:44.858938
3962 00:42:44.862186 ----->DramcWriteLeveling(PI) begin...
3963 00:42:44.862272 ==
3964 00:42:44.865468 Dram Type= 6, Freq= 0, CH_0, rank 1
3965 00:42:44.868694 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3966 00:42:44.868771 ==
3967 00:42:44.872131 Write leveling (Byte 0): 32 => 32
3968 00:42:44.875350 Write leveling (Byte 1): 29 => 29
3969 00:42:44.878684 DramcWriteLeveling(PI) end<-----
3970 00:42:44.878761
3971 00:42:44.878820 ==
3972 00:42:44.881931 Dram Type= 6, Freq= 0, CH_0, rank 1
3973 00:42:44.885213 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3974 00:42:44.888541 ==
3975 00:42:44.888618 [Gating] SW mode calibration
3976 00:42:44.895359 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3977 00:42:44.901772 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
3978 00:42:44.905101 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3979 00:42:44.911784 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3980 00:42:44.915041 0 5 8 | B1->B0 | 3434 3131 | 0 0 | (0 1) (0 1)
3981 00:42:44.918335 0 5 12 | B1->B0 | 2424 2424 | 0 0 | (0 0) (0 0)
3982 00:42:44.925063 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3983 00:42:44.928364 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3984 00:42:44.932025 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3985 00:42:44.938304 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3986 00:42:44.941509 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3987 00:42:44.944960 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3988 00:42:44.951757 0 6 8 | B1->B0 | 2626 3333 | 0 0 | (0 0) (0 0)
3989 00:42:44.955252 0 6 12 | B1->B0 | 4444 4646 | 0 0 | (1 1) (0 0)
3990 00:42:44.958134 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3991 00:42:44.964666 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3992 00:42:44.968012 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3993 00:42:44.971409 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3994 00:42:44.978058 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3995 00:42:44.981359 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3996 00:42:44.984654 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3997 00:42:44.991224 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3998 00:42:44.994442 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3999 00:42:44.997813 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4000 00:42:45.004424 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4001 00:42:45.008178 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4002 00:42:45.011030 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4003 00:42:45.014464 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4004 00:42:45.021006 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4005 00:42:45.024590 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4006 00:42:45.028001 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4007 00:42:45.034464 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4008 00:42:45.037836 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4009 00:42:45.041041 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4010 00:42:45.047702 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4011 00:42:45.051524 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4012 00:42:45.054299 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4013 00:42:45.060761 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4014 00:42:45.064421 Total UI for P1: 0, mck2ui 16
4015 00:42:45.067450 best dqsien dly found for B0: ( 0, 9, 10)
4016 00:42:45.070710 Total UI for P1: 0, mck2ui 16
4017 00:42:45.074028 best dqsien dly found for B1: ( 0, 9, 8)
4018 00:42:45.077364 best DQS0 dly(MCK, UI, PI) = (0, 9, 10)
4019 00:42:45.080736 best DQS1 dly(MCK, UI, PI) = (0, 9, 8)
4020 00:42:45.080824
4021 00:42:45.084058 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 10)
4022 00:42:45.087606 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 8)
4023 00:42:45.090785 [Gating] SW calibration Done
4024 00:42:45.090864 ==
4025 00:42:45.093820 Dram Type= 6, Freq= 0, CH_0, rank 1
4026 00:42:45.097384 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4027 00:42:45.097463 ==
4028 00:42:45.100599 RX Vref Scan: 0
4029 00:42:45.100677
4030 00:42:45.100738 RX Vref 0 -> 0, step: 1
4031 00:42:45.103922
4032 00:42:45.104000 RX Delay -230 -> 252, step: 16
4033 00:42:45.110421 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4034 00:42:45.113956 iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336
4035 00:42:45.117162 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4036 00:42:45.120438 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4037 00:42:45.126961 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
4038 00:42:45.130377 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4039 00:42:45.133801 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4040 00:42:45.137222 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4041 00:42:45.140376 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4042 00:42:45.146784 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4043 00:42:45.150136 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4044 00:42:45.153542 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4045 00:42:45.156703 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4046 00:42:45.163715 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4047 00:42:45.167019 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4048 00:42:45.170335 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4049 00:42:45.170415 ==
4050 00:42:45.173369 Dram Type= 6, Freq= 0, CH_0, rank 1
4051 00:42:45.177118 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4052 00:42:45.180458 ==
4053 00:42:45.180603 DQS Delay:
4054 00:42:45.180680 DQS0 = 0, DQS1 = 0
4055 00:42:45.183768 DQM Delay:
4056 00:42:45.183913 DQM0 = 44, DQM1 = 33
4057 00:42:45.187077 DQ Delay:
4058 00:42:45.187208 DQ0 =41, DQ1 =49, DQ2 =41, DQ3 =41
4059 00:42:45.190294 DQ4 =49, DQ5 =33, DQ6 =49, DQ7 =49
4060 00:42:45.193920 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
4061 00:42:45.197646 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4062 00:42:45.198134
4063 00:42:45.200288
4064 00:42:45.200696 ==
4065 00:42:45.203701 Dram Type= 6, Freq= 0, CH_0, rank 1
4066 00:42:45.206854 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4067 00:42:45.207399 ==
4068 00:42:45.207854
4069 00:42:45.208278
4070 00:42:45.210391 TX Vref Scan disable
4071 00:42:45.210897 == TX Byte 0 ==
4072 00:42:45.216886 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4073 00:42:45.220230 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4074 00:42:45.220645 == TX Byte 1 ==
4075 00:42:45.226906 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4076 00:42:45.230441 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4077 00:42:45.230903 ==
4078 00:42:45.233566 Dram Type= 6, Freq= 0, CH_0, rank 1
4079 00:42:45.237230 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4080 00:42:45.237590 ==
4081 00:42:45.237810
4082 00:42:45.238013
4083 00:42:45.240452 TX Vref Scan disable
4084 00:42:45.243427 == TX Byte 0 ==
4085 00:42:45.247070 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4086 00:42:45.250099 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4087 00:42:45.253540 == TX Byte 1 ==
4088 00:42:45.256664 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4089 00:42:45.260213 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4090 00:42:45.260338
4091 00:42:45.263325 [DATLAT]
4092 00:42:45.263448 Freq=600, CH0 RK1
4093 00:42:45.263537
4094 00:42:45.266584 DATLAT Default: 0x8
4095 00:42:45.266694 0, 0xFFFF, sum = 0
4096 00:42:45.269979 1, 0xFFFF, sum = 0
4097 00:42:45.270078 2, 0xFFFF, sum = 0
4098 00:42:45.273685 3, 0xFFFF, sum = 0
4099 00:42:45.273778 4, 0xFFFF, sum = 0
4100 00:42:45.276514 5, 0xFFFF, sum = 0
4101 00:42:45.276613 6, 0xFFFF, sum = 0
4102 00:42:45.279744 7, 0x0, sum = 1
4103 00:42:45.279826 8, 0x0, sum = 2
4104 00:42:45.282993 9, 0x0, sum = 3
4105 00:42:45.283073 10, 0x0, sum = 4
4106 00:42:45.286541 best_step = 8
4107 00:42:45.286620
4108 00:42:45.286680 ==
4109 00:42:45.290204 Dram Type= 6, Freq= 0, CH_0, rank 1
4110 00:42:45.293009 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4111 00:42:45.293092 ==
4112 00:42:45.296234 RX Vref Scan: 0
4113 00:42:45.296313
4114 00:42:45.296373 RX Vref 0 -> 0, step: 1
4115 00:42:45.296430
4116 00:42:45.299471 RX Delay -195 -> 252, step: 8
4117 00:42:45.306536 iDelay=205, Bit 0, Center 36 (-115 ~ 188) 304
4118 00:42:45.309838 iDelay=205, Bit 1, Center 40 (-115 ~ 196) 312
4119 00:42:45.313252 iDelay=205, Bit 2, Center 40 (-115 ~ 196) 312
4120 00:42:45.316268 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4121 00:42:45.322919 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4122 00:42:45.326239 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4123 00:42:45.329721 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4124 00:42:45.332675 iDelay=205, Bit 7, Center 52 (-99 ~ 204) 304
4125 00:42:45.339527 iDelay=205, Bit 8, Center 20 (-131 ~ 172) 304
4126 00:42:45.342873 iDelay=205, Bit 9, Center 20 (-131 ~ 172) 304
4127 00:42:45.346251 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4128 00:42:45.349278 iDelay=205, Bit 11, Center 24 (-123 ~ 172) 296
4129 00:42:45.355840 iDelay=205, Bit 12, Center 40 (-107 ~ 188) 296
4130 00:42:45.359210 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4131 00:42:45.362592 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4132 00:42:45.365889 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4133 00:42:45.365989 ==
4134 00:42:45.369225 Dram Type= 6, Freq= 0, CH_0, rank 1
4135 00:42:45.375793 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4136 00:42:45.375900 ==
4137 00:42:45.375961 DQS Delay:
4138 00:42:45.376018 DQS0 = 0, DQS1 = 0
4139 00:42:45.379437 DQM Delay:
4140 00:42:45.379517 DQM0 = 41, DQM1 = 33
4141 00:42:45.382614 DQ Delay:
4142 00:42:45.386110 DQ0 =36, DQ1 =40, DQ2 =40, DQ3 =36
4143 00:42:45.389384 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =52
4144 00:42:45.392905 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =24
4145 00:42:45.395780 DQ12 =40, DQ13 =40, DQ14 =44, DQ15 =44
4146 00:42:45.395912
4147 00:42:45.395979
4148 00:42:45.402675 [DQSOSCAuto] RK1, (LSB)MR18= 0x6969, (MSB)MR19= 0x808, tDQSOscB0 = 390 ps tDQSOscB1 = 390 ps
4149 00:42:45.406011 CH0 RK1: MR19=808, MR18=6969
4150 00:42:45.412500 CH0_RK1: MR19=0x808, MR18=0x6969, DQSOSC=390, MR23=63, INC=172, DEC=114
4151 00:42:45.415895 [RxdqsGatingPostProcess] freq 600
4152 00:42:45.418997 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4153 00:42:45.422526 Pre-setting of DQS Precalculation
4154 00:42:45.429146 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4155 00:42:45.429309 ==
4156 00:42:45.432142 Dram Type= 6, Freq= 0, CH_1, rank 0
4157 00:42:45.435889 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4158 00:42:45.436060 ==
4159 00:42:45.442106 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4160 00:42:45.448797 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
4161 00:42:45.452044 [CA 0] Center 35 (5~66) winsize 62
4162 00:42:45.455442 [CA 1] Center 35 (5~66) winsize 62
4163 00:42:45.458469 [CA 2] Center 33 (3~64) winsize 62
4164 00:42:45.461838 [CA 3] Center 33 (3~64) winsize 62
4165 00:42:45.465230 [CA 4] Center 33 (2~64) winsize 63
4166 00:42:45.468647 [CA 5] Center 33 (2~64) winsize 63
4167 00:42:45.468928
4168 00:42:45.472199 [CmdBusTrainingLP45] Vref(ca) range 1: 39
4169 00:42:45.472618
4170 00:42:45.475479 [CATrainingPosCal] consider 1 rank data
4171 00:42:45.478980 u2DelayCellTimex100 = 270/100 ps
4172 00:42:45.481901 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4173 00:42:45.485195 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4174 00:42:45.488849 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
4175 00:42:45.492078 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4176 00:42:45.494874 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
4177 00:42:45.498191 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4178 00:42:45.498770
4179 00:42:45.504927 CA PerBit enable=1, Macro0, CA PI delay=33
4180 00:42:45.505459
4181 00:42:45.508379 [CBTSetCACLKResult] CA Dly = 33
4182 00:42:45.508883 CS Dly: 3 (0~34)
4183 00:42:45.509320 ==
4184 00:42:45.511487 Dram Type= 6, Freq= 0, CH_1, rank 1
4185 00:42:45.514991 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4186 00:42:45.515393 ==
4187 00:42:45.521397 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4188 00:42:45.528034 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4189 00:42:45.531465 [CA 0] Center 35 (5~66) winsize 62
4190 00:42:45.534754 [CA 1] Center 34 (4~65) winsize 62
4191 00:42:45.537735 [CA 2] Center 33 (3~64) winsize 62
4192 00:42:45.541518 [CA 3] Center 33 (3~64) winsize 62
4193 00:42:45.544786 [CA 4] Center 32 (2~63) winsize 62
4194 00:42:45.547924 [CA 5] Center 32 (2~63) winsize 62
4195 00:42:45.548448
4196 00:42:45.551205 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4197 00:42:45.551595
4198 00:42:45.554722 [CATrainingPosCal] consider 2 rank data
4199 00:42:45.558007 u2DelayCellTimex100 = 270/100 ps
4200 00:42:45.561000 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
4201 00:42:45.564326 CA1 delay=35 (5~65),Diff = 3 PI (28 cell)
4202 00:42:45.567688 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
4203 00:42:45.570834 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
4204 00:42:45.577413 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
4205 00:42:45.581373 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
4206 00:42:45.581774
4207 00:42:45.584196 CA PerBit enable=1, Macro0, CA PI delay=32
4208 00:42:45.584595
4209 00:42:45.587756 [CBTSetCACLKResult] CA Dly = 32
4210 00:42:45.588154 CS Dly: 3 (0~35)
4211 00:42:45.588465
4212 00:42:45.590901 ----->DramcWriteLeveling(PI) begin...
4213 00:42:45.591303 ==
4214 00:42:45.594333 Dram Type= 6, Freq= 0, CH_1, rank 0
4215 00:42:45.600683 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4216 00:42:45.601130 ==
4217 00:42:45.603939 Write leveling (Byte 0): 30 => 30
4218 00:42:45.607465 Write leveling (Byte 1): 29 => 29
4219 00:42:45.607858 DramcWriteLeveling(PI) end<-----
4220 00:42:45.608165
4221 00:42:45.610693 ==
4222 00:42:45.614355 Dram Type= 6, Freq= 0, CH_1, rank 0
4223 00:42:45.617471 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4224 00:42:45.617948 ==
4225 00:42:45.621033 [Gating] SW mode calibration
4226 00:42:45.627302 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4227 00:42:45.630414 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4228 00:42:45.637345 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4229 00:42:45.640575 0 5 4 | B1->B0 | 3434 3131 | 1 1 | (1 1) (0 1)
4230 00:42:45.643617 0 5 8 | B1->B0 | 3030 2424 | 0 0 | (0 0) (0 0)
4231 00:42:45.650920 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4232 00:42:45.653774 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4233 00:42:45.657177 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4234 00:42:45.663638 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4235 00:42:45.667240 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4236 00:42:45.670144 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4237 00:42:45.676864 0 6 4 | B1->B0 | 2424 3131 | 0 1 | (0 0) (0 0)
4238 00:42:45.680244 0 6 8 | B1->B0 | 3636 4242 | 0 0 | (0 0) (0 0)
4239 00:42:45.683589 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4240 00:42:45.690000 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4241 00:42:45.694207 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4242 00:42:45.696538 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4243 00:42:45.703346 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4244 00:42:45.706580 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4245 00:42:45.709925 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4246 00:42:45.716255 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4247 00:42:45.719736 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4248 00:42:45.723001 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4249 00:42:45.729638 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4250 00:42:45.733007 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4251 00:42:45.736132 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4252 00:42:45.743101 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4253 00:42:45.746264 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4254 00:42:45.749546 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4255 00:42:45.756272 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4256 00:42:45.759415 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4257 00:42:45.763040 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4258 00:42:45.769424 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4259 00:42:45.772767 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4260 00:42:45.775960 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4261 00:42:45.782807 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4262 00:42:45.786095 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4263 00:42:45.789534 Total UI for P1: 0, mck2ui 16
4264 00:42:45.792496 best dqsien dly found for B0: ( 0, 9, 4)
4265 00:42:45.796321 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4266 00:42:45.799572 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4267 00:42:45.802528 Total UI for P1: 0, mck2ui 16
4268 00:42:45.806091 best dqsien dly found for B1: ( 0, 9, 10)
4269 00:42:45.808971 best DQS0 dly(MCK, UI, PI) = (0, 9, 4)
4270 00:42:45.816016 best DQS1 dly(MCK, UI, PI) = (0, 9, 10)
4271 00:42:45.816505
4272 00:42:45.819134 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 4)
4273 00:42:45.822320 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 10)
4274 00:42:45.825363 [Gating] SW calibration Done
4275 00:42:45.825997 ==
4276 00:42:45.828979 Dram Type= 6, Freq= 0, CH_1, rank 0
4277 00:42:45.832323 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4278 00:42:45.832720 ==
4279 00:42:45.835754 RX Vref Scan: 0
4280 00:42:45.836148
4281 00:42:45.836454 RX Vref 0 -> 0, step: 1
4282 00:42:45.836740
4283 00:42:45.838677 RX Delay -230 -> 252, step: 16
4284 00:42:45.842677 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4285 00:42:45.848698 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4286 00:42:45.851963 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4287 00:42:45.855454 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4288 00:42:45.858912 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4289 00:42:45.865276 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4290 00:42:45.869476 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4291 00:42:45.872189 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4292 00:42:45.875274 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4293 00:42:45.878374 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4294 00:42:45.885166 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4295 00:42:45.888603 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4296 00:42:45.891567 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4297 00:42:45.895444 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4298 00:42:45.901606 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4299 00:42:45.905403 iDelay=218, Bit 15, Center 41 (-134 ~ 217) 352
4300 00:42:45.905885 ==
4301 00:42:45.908819 Dram Type= 6, Freq= 0, CH_1, rank 0
4302 00:42:45.911692 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4303 00:42:45.912136 ==
4304 00:42:45.914810 DQS Delay:
4305 00:42:45.915199 DQS0 = 0, DQS1 = 0
4306 00:42:45.918401 DQM Delay:
4307 00:42:45.918791 DQM0 = 39, DQM1 = 30
4308 00:42:45.919101 DQ Delay:
4309 00:42:45.921482 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =33
4310 00:42:45.924965 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4311 00:42:45.928338 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4312 00:42:45.932101 DQ12 =33, DQ13 =49, DQ14 =33, DQ15 =41
4313 00:42:45.932497
4314 00:42:45.932803
4315 00:42:45.933084 ==
4316 00:42:45.935168 Dram Type= 6, Freq= 0, CH_1, rank 0
4317 00:42:45.941611 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4318 00:42:45.942008 ==
4319 00:42:45.942350
4320 00:42:45.942638
4321 00:42:45.945327 TX Vref Scan disable
4322 00:42:45.945804 == TX Byte 0 ==
4323 00:42:45.948069 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4324 00:42:45.954849 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4325 00:42:45.955354 == TX Byte 1 ==
4326 00:42:45.958009 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4327 00:42:45.964570 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4328 00:42:45.965052 ==
4329 00:42:45.968195 Dram Type= 6, Freq= 0, CH_1, rank 0
4330 00:42:45.971650 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4331 00:42:45.972135 ==
4332 00:42:45.972450
4333 00:42:45.972827
4334 00:42:45.974352 TX Vref Scan disable
4335 00:42:45.978275 == TX Byte 0 ==
4336 00:42:45.981208 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4337 00:42:45.984594 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4338 00:42:45.987646 == TX Byte 1 ==
4339 00:42:45.991512 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4340 00:42:45.994181 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4341 00:42:45.994609
4342 00:42:45.997927 [DATLAT]
4343 00:42:45.998455 Freq=600, CH1 RK0
4344 00:42:45.998774
4345 00:42:46.001293 DATLAT Default: 0x9
4346 00:42:46.001685 0, 0xFFFF, sum = 0
4347 00:42:46.004304 1, 0xFFFF, sum = 0
4348 00:42:46.004704 2, 0xFFFF, sum = 0
4349 00:42:46.008025 3, 0xFFFF, sum = 0
4350 00:42:46.008511 4, 0xFFFF, sum = 0
4351 00:42:46.011568 5, 0xFFFF, sum = 0
4352 00:42:46.011967 6, 0xFFFF, sum = 0
4353 00:42:46.014530 7, 0x0, sum = 1
4354 00:42:46.014930 8, 0x0, sum = 2
4355 00:42:46.017542 9, 0x0, sum = 3
4356 00:42:46.017941 10, 0x0, sum = 4
4357 00:42:46.021069 best_step = 8
4358 00:42:46.021461
4359 00:42:46.021764 ==
4360 00:42:46.024714 Dram Type= 6, Freq= 0, CH_1, rank 0
4361 00:42:46.027519 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4362 00:42:46.028057 ==
4363 00:42:46.028534 RX Vref Scan: 1
4364 00:42:46.029008
4365 00:42:46.031287 RX Vref 0 -> 0, step: 1
4366 00:42:46.031759
4367 00:42:46.034126 RX Delay -195 -> 252, step: 8
4368 00:42:46.034568
4369 00:42:46.037668 Set Vref, RX VrefLevel [Byte0]: 52
4370 00:42:46.040691 [Byte1]: 49
4371 00:42:46.044012
4372 00:42:46.044403 Final RX Vref Byte 0 = 52 to rank0
4373 00:42:46.047611 Final RX Vref Byte 1 = 49 to rank0
4374 00:42:46.050705 Final RX Vref Byte 0 = 52 to rank1
4375 00:42:46.053789 Final RX Vref Byte 1 = 49 to rank1==
4376 00:42:46.057316 Dram Type= 6, Freq= 0, CH_1, rank 0
4377 00:42:46.063817 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4378 00:42:46.064386 ==
4379 00:42:46.064898 DQS Delay:
4380 00:42:46.065370 DQS0 = 0, DQS1 = 0
4381 00:42:46.067150 DQM Delay:
4382 00:42:46.067694 DQM0 = 37, DQM1 = 31
4383 00:42:46.070487 DQ Delay:
4384 00:42:46.073981 DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =36
4385 00:42:46.077384 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =36
4386 00:42:46.080687 DQ8 =12, DQ9 =20, DQ10 =32, DQ11 =24
4387 00:42:46.083810 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4388 00:42:46.084281
4389 00:42:46.084598
4390 00:42:46.090477 [DQSOSCAuto] RK0, (LSB)MR18= 0x8080, (MSB)MR19= 0x808, tDQSOscB0 = 386 ps tDQSOscB1 = 386 ps
4391 00:42:46.093947 CH1 RK0: MR19=808, MR18=8080
4392 00:42:46.100623 CH1_RK0: MR19=0x808, MR18=0x8080, DQSOSC=386, MR23=63, INC=176, DEC=117
4393 00:42:46.101081
4394 00:42:46.103704 ----->DramcWriteLeveling(PI) begin...
4395 00:42:46.104128 ==
4396 00:42:46.106940 Dram Type= 6, Freq= 0, CH_1, rank 1
4397 00:42:46.110286 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4398 00:42:46.110859 ==
4399 00:42:46.113623 Write leveling (Byte 0): 29 => 29
4400 00:42:46.116848 Write leveling (Byte 1): 29 => 29
4401 00:42:46.120410 DramcWriteLeveling(PI) end<-----
4402 00:42:46.121078
4403 00:42:46.121413 ==
4404 00:42:46.124034 Dram Type= 6, Freq= 0, CH_1, rank 1
4405 00:42:46.126725 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4406 00:42:46.127127 ==
4407 00:42:46.130314 [Gating] SW mode calibration
4408 00:42:46.137013 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4409 00:42:46.143863 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4410 00:42:46.146850 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4411 00:42:46.153524 0 5 4 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 0)
4412 00:42:46.156680 0 5 8 | B1->B0 | 3030 2323 | 0 0 | (0 1) (0 0)
4413 00:42:46.160008 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4414 00:42:46.166556 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4415 00:42:46.169896 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4416 00:42:46.173411 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4417 00:42:46.179663 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4418 00:42:46.183029 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4419 00:42:46.186386 0 6 4 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
4420 00:42:46.192987 0 6 8 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
4421 00:42:46.196526 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4422 00:42:46.199613 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4423 00:42:46.206514 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4424 00:42:46.209859 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4425 00:42:46.213093 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4426 00:42:46.219601 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4427 00:42:46.222915 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4428 00:42:46.226572 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4429 00:42:46.229819 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4430 00:42:46.236081 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4431 00:42:46.239227 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4432 00:42:46.242832 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4433 00:42:46.249503 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4434 00:42:46.252561 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4435 00:42:46.256035 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4436 00:42:46.263237 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4437 00:42:46.265906 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4438 00:42:46.269459 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4439 00:42:46.276462 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4440 00:42:46.279153 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4441 00:42:46.282531 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4442 00:42:46.289505 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4443 00:42:46.292747 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4444 00:42:46.296302 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4445 00:42:46.299270 Total UI for P1: 0, mck2ui 16
4446 00:42:46.302415 best dqsien dly found for B0: ( 0, 9, 4)
4447 00:42:46.309035 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4448 00:42:46.309509 Total UI for P1: 0, mck2ui 16
4449 00:42:46.315765 best dqsien dly found for B1: ( 0, 9, 8)
4450 00:42:46.318875 best DQS0 dly(MCK, UI, PI) = (0, 9, 4)
4451 00:42:46.322428 best DQS1 dly(MCK, UI, PI) = (0, 9, 8)
4452 00:42:46.322907
4453 00:42:46.325692 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 4)
4454 00:42:46.328931 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 8)
4455 00:42:46.332374 [Gating] SW calibration Done
4456 00:42:46.332908 ==
4457 00:42:46.335485 Dram Type= 6, Freq= 0, CH_1, rank 1
4458 00:42:46.338805 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4459 00:42:46.339205 ==
4460 00:42:46.342559 RX Vref Scan: 0
4461 00:42:46.343036
4462 00:42:46.343345 RX Vref 0 -> 0, step: 1
4463 00:42:46.343629
4464 00:42:46.345427 RX Delay -230 -> 252, step: 16
4465 00:42:46.352034 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4466 00:42:46.355247 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4467 00:42:46.358885 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4468 00:42:46.362174 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4469 00:42:46.365583 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4470 00:42:46.372440 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4471 00:42:46.375467 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4472 00:42:46.379109 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4473 00:42:46.382043 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4474 00:42:46.388686 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4475 00:42:46.391922 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4476 00:42:46.395072 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4477 00:42:46.398551 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4478 00:42:46.405161 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4479 00:42:46.408837 iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352
4480 00:42:46.411791 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4481 00:42:46.412195 ==
4482 00:42:46.414912 Dram Type= 6, Freq= 0, CH_1, rank 1
4483 00:42:46.418827 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4484 00:42:46.419324 ==
4485 00:42:46.421795 DQS Delay:
4486 00:42:46.422186 DQS0 = 0, DQS1 = 0
4487 00:42:46.425030 DQM Delay:
4488 00:42:46.425521 DQM0 = 41, DQM1 = 33
4489 00:42:46.425842 DQ Delay:
4490 00:42:46.428189 DQ0 =41, DQ1 =33, DQ2 =33, DQ3 =41
4491 00:42:46.432110 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4492 00:42:46.435222 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4493 00:42:46.438569 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =41
4494 00:42:46.439046
4495 00:42:46.439353
4496 00:42:46.441550 ==
4497 00:42:46.444838 Dram Type= 6, Freq= 0, CH_1, rank 1
4498 00:42:46.447966 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4499 00:42:46.448381 ==
4500 00:42:46.448795
4501 00:42:46.449086
4502 00:42:46.451452 TX Vref Scan disable
4503 00:42:46.451844 == TX Byte 0 ==
4504 00:42:46.454702 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4505 00:42:46.461587 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4506 00:42:46.461985 == TX Byte 1 ==
4507 00:42:46.467988 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4508 00:42:46.471511 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4509 00:42:46.471910 ==
4510 00:42:46.474683 Dram Type= 6, Freq= 0, CH_1, rank 1
4511 00:42:46.477774 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4512 00:42:46.478168 ==
4513 00:42:46.478524
4514 00:42:46.478810
4515 00:42:46.481092 TX Vref Scan disable
4516 00:42:46.484608 == TX Byte 0 ==
4517 00:42:46.487763 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4518 00:42:46.491719 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4519 00:42:46.494410 == TX Byte 1 ==
4520 00:42:46.497896 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4521 00:42:46.500986 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4522 00:42:46.501378
4523 00:42:46.504608 [DATLAT]
4524 00:42:46.505118 Freq=600, CH1 RK1
4525 00:42:46.505438
4526 00:42:46.508046 DATLAT Default: 0x8
4527 00:42:46.508378 0, 0xFFFF, sum = 0
4528 00:42:46.511570 1, 0xFFFF, sum = 0
4529 00:42:46.512064 2, 0xFFFF, sum = 0
4530 00:42:46.514663 3, 0xFFFF, sum = 0
4531 00:42:46.515060 4, 0xFFFF, sum = 0
4532 00:42:46.517763 5, 0xFFFF, sum = 0
4533 00:42:46.518157 6, 0xFFFF, sum = 0
4534 00:42:46.521107 7, 0x0, sum = 1
4535 00:42:46.521519 8, 0x0, sum = 2
4536 00:42:46.524926 9, 0x0, sum = 3
4537 00:42:46.525425 10, 0x0, sum = 4
4538 00:42:46.528016 best_step = 8
4539 00:42:46.528489
4540 00:42:46.528799 ==
4541 00:42:46.531034 Dram Type= 6, Freq= 0, CH_1, rank 1
4542 00:42:46.534759 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4543 00:42:46.535257 ==
4544 00:42:46.535578 RX Vref Scan: 0
4545 00:42:46.537942
4546 00:42:46.538372 RX Vref 0 -> 0, step: 1
4547 00:42:46.538687
4548 00:42:46.540914 RX Delay -195 -> 252, step: 8
4549 00:42:46.547462 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4550 00:42:46.550843 iDelay=205, Bit 1, Center 36 (-115 ~ 188) 304
4551 00:42:46.554136 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4552 00:42:46.557470 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4553 00:42:46.564328 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312
4554 00:42:46.567786 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4555 00:42:46.570854 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4556 00:42:46.574468 iDelay=205, Bit 7, Center 36 (-115 ~ 188) 304
4557 00:42:46.577708 iDelay=205, Bit 8, Center 16 (-139 ~ 172) 312
4558 00:42:46.584143 iDelay=205, Bit 9, Center 16 (-139 ~ 172) 312
4559 00:42:46.587269 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4560 00:42:46.590679 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4561 00:42:46.593950 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4562 00:42:46.600675 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4563 00:42:46.603863 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4564 00:42:46.607927 iDelay=205, Bit 15, Center 36 (-115 ~ 188) 304
4565 00:42:46.608406 ==
4566 00:42:46.610721 Dram Type= 6, Freq= 0, CH_1, rank 1
4567 00:42:46.614586 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4568 00:42:46.617196 ==
4569 00:42:46.617584 DQS Delay:
4570 00:42:46.617889 DQS0 = 0, DQS1 = 0
4571 00:42:46.620852 DQM Delay:
4572 00:42:46.621324 DQM0 = 37, DQM1 = 29
4573 00:42:46.624159 DQ Delay:
4574 00:42:46.624631 DQ0 =40, DQ1 =36, DQ2 =24, DQ3 =32
4575 00:42:46.627313 DQ4 =40, DQ5 =48, DQ6 =44, DQ7 =36
4576 00:42:46.630865 DQ8 =16, DQ9 =16, DQ10 =32, DQ11 =20
4577 00:42:46.633951 DQ12 =40, DQ13 =40, DQ14 =36, DQ15 =36
4578 00:42:46.637495
4579 00:42:46.637966
4580 00:42:46.643973 [DQSOSCAuto] RK1, (LSB)MR18= 0x6464, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 391 ps
4581 00:42:46.647214 CH1 RK1: MR19=808, MR18=6464
4582 00:42:46.653862 CH1_RK1: MR19=0x808, MR18=0x6464, DQSOSC=391, MR23=63, INC=171, DEC=114
4583 00:42:46.656992 [RxdqsGatingPostProcess] freq 600
4584 00:42:46.660451 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4585 00:42:46.663954 Pre-setting of DQS Precalculation
4586 00:42:46.670111 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4587 00:42:46.676963 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4588 00:42:46.684050 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4589 00:42:46.684519
4590 00:42:46.684826
4591 00:42:46.686872 [Calibration Summary] 1200 Mbps
4592 00:42:46.687263 CH 0, Rank 0
4593 00:42:46.690163 SW Impedance : PASS
4594 00:42:46.694104 DUTY Scan : NO K
4595 00:42:46.694638 ZQ Calibration : PASS
4596 00:42:46.697095 Jitter Meter : NO K
4597 00:42:46.700710 CBT Training : PASS
4598 00:42:46.701186 Write leveling : PASS
4599 00:42:46.703307 RX DQS gating : PASS
4600 00:42:46.706738 RX DQ/DQS(RDDQC) : PASS
4601 00:42:46.707131 TX DQ/DQS : PASS
4602 00:42:46.710205 RX DATLAT : PASS
4603 00:42:46.710711 RX DQ/DQS(Engine): PASS
4604 00:42:46.713554 TX OE : NO K
4605 00:42:46.714069 All Pass.
4606 00:42:46.714479
4607 00:42:46.717370 CH 0, Rank 1
4608 00:42:46.717871 SW Impedance : PASS
4609 00:42:46.720063 DUTY Scan : NO K
4610 00:42:46.723945 ZQ Calibration : PASS
4611 00:42:46.724422 Jitter Meter : NO K
4612 00:42:46.726761 CBT Training : PASS
4613 00:42:46.730041 Write leveling : PASS
4614 00:42:46.730572 RX DQS gating : PASS
4615 00:42:46.733527 RX DQ/DQS(RDDQC) : PASS
4616 00:42:46.736861 TX DQ/DQS : PASS
4617 00:42:46.737336 RX DATLAT : PASS
4618 00:42:46.740010 RX DQ/DQS(Engine): PASS
4619 00:42:46.743569 TX OE : NO K
4620 00:42:46.743961 All Pass.
4621 00:42:46.744275
4622 00:42:46.744561 CH 1, Rank 0
4623 00:42:46.747054 SW Impedance : PASS
4624 00:42:46.749930 DUTY Scan : NO K
4625 00:42:46.750410 ZQ Calibration : PASS
4626 00:42:46.753808 Jitter Meter : NO K
4627 00:42:46.754199 CBT Training : PASS
4628 00:42:46.756936 Write leveling : PASS
4629 00:42:46.759958 RX DQS gating : PASS
4630 00:42:46.760353 RX DQ/DQS(RDDQC) : PASS
4631 00:42:46.763189 TX DQ/DQS : PASS
4632 00:42:46.766688 RX DATLAT : PASS
4633 00:42:46.767078 RX DQ/DQS(Engine): PASS
4634 00:42:46.770145 TX OE : NO K
4635 00:42:46.770557 All Pass.
4636 00:42:46.770863
4637 00:42:46.773424 CH 1, Rank 1
4638 00:42:46.773898 SW Impedance : PASS
4639 00:42:46.776854 DUTY Scan : NO K
4640 00:42:46.780159 ZQ Calibration : PASS
4641 00:42:46.780635 Jitter Meter : NO K
4642 00:42:46.783115 CBT Training : PASS
4643 00:42:46.786636 Write leveling : PASS
4644 00:42:46.787071 RX DQS gating : PASS
4645 00:42:46.790193 RX DQ/DQS(RDDQC) : PASS
4646 00:42:46.793332 TX DQ/DQS : PASS
4647 00:42:46.793804 RX DATLAT : PASS
4648 00:42:46.796711 RX DQ/DQS(Engine): PASS
4649 00:42:46.800145 TX OE : NO K
4650 00:42:46.800631 All Pass.
4651 00:42:46.800935
4652 00:42:46.801220 DramC Write-DBI off
4653 00:42:46.803215 PER_BANK_REFRESH: Hybrid Mode
4654 00:42:46.806341 TX_TRACKING: ON
4655 00:42:46.813223 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4656 00:42:46.817070 [FAST_K] Save calibration result to emmc
4657 00:42:46.822845 dramc_set_vcore_voltage set vcore to 662500
4658 00:42:46.823239 Read voltage for 933, 3
4659 00:42:46.823549 Vio18 = 0
4660 00:42:46.826543 Vcore = 662500
4661 00:42:46.827019 Vdram = 0
4662 00:42:46.827329 Vddq = 0
4663 00:42:46.829686 Vmddr = 0
4664 00:42:46.833111 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4665 00:42:46.839468 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4666 00:42:46.842835 MEM_TYPE=3, freq_sel=17
4667 00:42:46.843266 sv_algorithm_assistance_LP4_1600
4668 00:42:46.849680 ============ PULL DRAM RESETB DOWN ============
4669 00:42:46.853253 ========== PULL DRAM RESETB DOWN end =========
4670 00:42:46.856200 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4671 00:42:46.859739 ===================================
4672 00:42:46.862826 LPDDR4 DRAM CONFIGURATION
4673 00:42:46.866368 ===================================
4674 00:42:46.869744 EX_ROW_EN[0] = 0x0
4675 00:42:46.870253 EX_ROW_EN[1] = 0x0
4676 00:42:46.872817 LP4Y_EN = 0x0
4677 00:42:46.873211 WORK_FSP = 0x0
4678 00:42:46.876097 WL = 0x3
4679 00:42:46.876550 RL = 0x3
4680 00:42:46.879438 BL = 0x2
4681 00:42:46.879780 RPST = 0x0
4682 00:42:46.882984 RD_PRE = 0x0
4683 00:42:46.883380 WR_PRE = 0x1
4684 00:42:46.886630 WR_PST = 0x0
4685 00:42:46.887023 DBI_WR = 0x0
4686 00:42:46.889556 DBI_RD = 0x0
4687 00:42:46.889947 OTF = 0x1
4688 00:42:46.893018 ===================================
4689 00:42:46.896395 ===================================
4690 00:42:46.899717 ANA top config
4691 00:42:46.903118 ===================================
4692 00:42:46.906160 DLL_ASYNC_EN = 0
4693 00:42:46.906700 ALL_SLAVE_EN = 1
4694 00:42:46.909891 NEW_RANK_MODE = 1
4695 00:42:46.912830 DLL_IDLE_MODE = 1
4696 00:42:46.916085 LP45_APHY_COMB_EN = 1
4697 00:42:46.916480 TX_ODT_DIS = 1
4698 00:42:46.919465 NEW_8X_MODE = 1
4699 00:42:46.922714 ===================================
4700 00:42:46.925959 ===================================
4701 00:42:46.929555 data_rate = 1866
4702 00:42:46.932630 CKR = 1
4703 00:42:46.935884 DQ_P2S_RATIO = 8
4704 00:42:46.939436 ===================================
4705 00:42:46.942809 CA_P2S_RATIO = 8
4706 00:42:46.943207 DQ_CA_OPEN = 0
4707 00:42:46.945886 DQ_SEMI_OPEN = 0
4708 00:42:46.949272 CA_SEMI_OPEN = 0
4709 00:42:46.952241 CA_FULL_RATE = 0
4710 00:42:46.955905 DQ_CKDIV4_EN = 1
4711 00:42:46.958924 CA_CKDIV4_EN = 1
4712 00:42:46.959322 CA_PREDIV_EN = 0
4713 00:42:46.962393 PH8_DLY = 0
4714 00:42:46.965442 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4715 00:42:46.968984 DQ_AAMCK_DIV = 4
4716 00:42:46.972501 CA_AAMCK_DIV = 4
4717 00:42:46.975902 CA_ADMCK_DIV = 4
4718 00:42:46.976320 DQ_TRACK_CA_EN = 0
4719 00:42:46.979049 CA_PICK = 933
4720 00:42:46.982286 CA_MCKIO = 933
4721 00:42:46.985547 MCKIO_SEMI = 0
4722 00:42:46.988850 PLL_FREQ = 3732
4723 00:42:46.992079 DQ_UI_PI_RATIO = 32
4724 00:42:46.995419 CA_UI_PI_RATIO = 0
4725 00:42:46.998874 ===================================
4726 00:42:47.001947 ===================================
4727 00:42:47.002454 memory_type:LPDDR4
4728 00:42:47.005504 GP_NUM : 10
4729 00:42:47.008889 SRAM_EN : 1
4730 00:42:47.009284 MD32_EN : 0
4731 00:42:47.011760 ===================================
4732 00:42:47.015118 [ANA_INIT] >>>>>>>>>>>>>>
4733 00:42:47.018680 <<<<<< [CONFIGURE PHASE]: ANA_TX
4734 00:42:47.021751 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4735 00:42:47.025230 ===================================
4736 00:42:47.028338 data_rate = 1866,PCW = 0X8f00
4737 00:42:47.031574 ===================================
4738 00:42:47.035066 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4739 00:42:47.038697 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4740 00:42:47.045235 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4741 00:42:47.048264 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4742 00:42:47.054659 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4743 00:42:47.058737 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4744 00:42:47.059220 [ANA_INIT] flow start
4745 00:42:47.061801 [ANA_INIT] PLL >>>>>>>>
4746 00:42:47.064742 [ANA_INIT] PLL <<<<<<<<
4747 00:42:47.065143 [ANA_INIT] MIDPI >>>>>>>>
4748 00:42:47.068341 [ANA_INIT] MIDPI <<<<<<<<
4749 00:42:47.071800 [ANA_INIT] DLL >>>>>>>>
4750 00:42:47.072195 [ANA_INIT] flow end
4751 00:42:47.074957 ============ LP4 DIFF to SE enter ============
4752 00:42:47.081557 ============ LP4 DIFF to SE exit ============
4753 00:42:47.082051 [ANA_INIT] <<<<<<<<<<<<<
4754 00:42:47.084738 [Flow] Enable top DCM control >>>>>
4755 00:42:47.087746 [Flow] Enable top DCM control <<<<<
4756 00:42:47.091288 Enable DLL master slave shuffle
4757 00:42:47.098206 ==============================================================
4758 00:42:47.101339 Gating Mode config
4759 00:42:47.104434 ==============================================================
4760 00:42:47.107808 Config description:
4761 00:42:47.117577 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4762 00:42:47.124748 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4763 00:42:47.127709 SELPH_MODE 0: By rank 1: By Phase
4764 00:42:47.133933 ==============================================================
4765 00:42:47.144572 GAT_TRACK_EN = 1
4766 00:42:47.144995 RX_GATING_MODE = 2
4767 00:42:47.145399 RX_GATING_TRACK_MODE = 2
4768 00:42:47.147179 SELPH_MODE = 1
4769 00:42:47.147583 PICG_EARLY_EN = 1
4770 00:42:47.150163 VALID_LAT_VALUE = 1
4771 00:42:47.156882 ==============================================================
4772 00:42:47.160088 Enter into Gating configuration >>>>
4773 00:42:47.163245 Exit from Gating configuration <<<<
4774 00:42:47.166621 Enter into DVFS_PRE_config >>>>>
4775 00:42:47.176412 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4776 00:42:47.179940 Exit from DVFS_PRE_config <<<<<
4777 00:42:47.183147 Enter into PICG configuration >>>>
4778 00:42:47.186590 Exit from PICG configuration <<<<
4779 00:42:47.189626 [RX_INPUT] configuration >>>>>
4780 00:42:47.192942 [RX_INPUT] configuration <<<<<
4781 00:42:47.196557 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4782 00:42:47.203445 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4783 00:42:47.210152 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4784 00:42:47.216378 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4785 00:42:47.222822 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4786 00:42:47.229508 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4787 00:42:47.232909 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4788 00:42:47.236300 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4789 00:42:47.239935 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4790 00:42:47.245966 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4791 00:42:47.249401 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4792 00:42:47.252884 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4793 00:42:47.256201 ===================================
4794 00:42:47.259327 LPDDR4 DRAM CONFIGURATION
4795 00:42:47.262671 ===================================
4796 00:42:47.262862 EX_ROW_EN[0] = 0x0
4797 00:42:47.266006 EX_ROW_EN[1] = 0x0
4798 00:42:47.266230 LP4Y_EN = 0x0
4799 00:42:47.269164 WORK_FSP = 0x0
4800 00:42:47.272392 WL = 0x3
4801 00:42:47.272609 RL = 0x3
4802 00:42:47.275760 BL = 0x2
4803 00:42:47.275926 RPST = 0x0
4804 00:42:47.279318 RD_PRE = 0x0
4805 00:42:47.279541 WR_PRE = 0x1
4806 00:42:47.282861 WR_PST = 0x0
4807 00:42:47.283140 DBI_WR = 0x0
4808 00:42:47.285725 DBI_RD = 0x0
4809 00:42:47.286004 OTF = 0x1
4810 00:42:47.289674 ===================================
4811 00:42:47.292341 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4812 00:42:47.299090 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4813 00:42:47.302436 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4814 00:42:47.306042 ===================================
4815 00:42:47.309241 LPDDR4 DRAM CONFIGURATION
4816 00:42:47.312501 ===================================
4817 00:42:47.312995 EX_ROW_EN[0] = 0x10
4818 00:42:47.315671 EX_ROW_EN[1] = 0x0
4819 00:42:47.316061 LP4Y_EN = 0x0
4820 00:42:47.319025 WORK_FSP = 0x0
4821 00:42:47.322208 WL = 0x3
4822 00:42:47.322640 RL = 0x3
4823 00:42:47.325791 BL = 0x2
4824 00:42:47.326181 RPST = 0x0
4825 00:42:47.328812 RD_PRE = 0x0
4826 00:42:47.329200 WR_PRE = 0x1
4827 00:42:47.332739 WR_PST = 0x0
4828 00:42:47.333233 DBI_WR = 0x0
4829 00:42:47.335376 DBI_RD = 0x0
4830 00:42:47.335766 OTF = 0x1
4831 00:42:47.338610 ===================================
4832 00:42:47.345366 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
4833 00:42:47.349677 nWR fixed to 30
4834 00:42:47.352969 [ModeRegInit_LP4] CH0 RK0
4835 00:42:47.353358 [ModeRegInit_LP4] CH0 RK1
4836 00:42:47.356327 [ModeRegInit_LP4] CH1 RK0
4837 00:42:47.359247 [ModeRegInit_LP4] CH1 RK1
4838 00:42:47.359634 match AC timing 8
4839 00:42:47.366131 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 0
4840 00:42:47.369684 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
4841 00:42:47.373132 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
4842 00:42:47.379423 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
4843 00:42:47.382870 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
4844 00:42:47.383347 ==
4845 00:42:47.385732 Dram Type= 6, Freq= 0, CH_0, rank 0
4846 00:42:47.389315 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4847 00:42:47.389712 ==
4848 00:42:47.396208 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4849 00:42:47.402709 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4850 00:42:47.405871 [CA 0] Center 38 (8~69) winsize 62
4851 00:42:47.409323 [CA 1] Center 38 (8~69) winsize 62
4852 00:42:47.412756 [CA 2] Center 36 (6~67) winsize 62
4853 00:42:47.416049 [CA 3] Center 36 (6~67) winsize 62
4854 00:42:47.419091 [CA 4] Center 34 (4~65) winsize 62
4855 00:42:47.422665 [CA 5] Center 34 (4~65) winsize 62
4856 00:42:47.423070
4857 00:42:47.426089 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4858 00:42:47.426525
4859 00:42:47.429493 [CATrainingPosCal] consider 1 rank data
4860 00:42:47.432479 u2DelayCellTimex100 = 270/100 ps
4861 00:42:47.436022 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4862 00:42:47.438935 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4863 00:42:47.442413 CA2 delay=36 (6~67),Diff = 2 PI (12 cell)
4864 00:42:47.445626 CA3 delay=36 (6~67),Diff = 2 PI (12 cell)
4865 00:42:47.449001 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4866 00:42:47.455615 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4867 00:42:47.456018
4868 00:42:47.459009 CA PerBit enable=1, Macro0, CA PI delay=34
4869 00:42:47.459415
4870 00:42:47.462374 [CBTSetCACLKResult] CA Dly = 34
4871 00:42:47.462781 CS Dly: 7 (0~38)
4872 00:42:47.463182 ==
4873 00:42:47.465726 Dram Type= 6, Freq= 0, CH_0, rank 1
4874 00:42:47.469014 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4875 00:42:47.472508 ==
4876 00:42:47.475636 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4877 00:42:47.482667 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4878 00:42:47.485397 [CA 0] Center 38 (8~69) winsize 62
4879 00:42:47.489061 [CA 1] Center 38 (8~69) winsize 62
4880 00:42:47.492067 [CA 2] Center 36 (6~67) winsize 62
4881 00:42:47.495776 [CA 3] Center 35 (5~66) winsize 62
4882 00:42:47.498641 [CA 4] Center 34 (4~64) winsize 61
4883 00:42:47.502034 [CA 5] Center 34 (4~65) winsize 62
4884 00:42:47.502500
4885 00:42:47.505054 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4886 00:42:47.505447
4887 00:42:47.508479 [CATrainingPosCal] consider 2 rank data
4888 00:42:47.511811 u2DelayCellTimex100 = 270/100 ps
4889 00:42:47.515073 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4890 00:42:47.518542 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4891 00:42:47.521655 CA2 delay=36 (6~67),Diff = 2 PI (12 cell)
4892 00:42:47.528378 CA3 delay=36 (6~66),Diff = 2 PI (12 cell)
4893 00:42:47.531539 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
4894 00:42:47.534839 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4895 00:42:47.535234
4896 00:42:47.538520 CA PerBit enable=1, Macro0, CA PI delay=34
4897 00:42:47.538913
4898 00:42:47.541402 [CBTSetCACLKResult] CA Dly = 34
4899 00:42:47.541794 CS Dly: 7 (0~39)
4900 00:42:47.542098
4901 00:42:47.544601 ----->DramcWriteLeveling(PI) begin...
4902 00:42:47.547858 ==
4903 00:42:47.548069 Dram Type= 6, Freq= 0, CH_0, rank 0
4904 00:42:47.554626 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4905 00:42:47.554802 ==
4906 00:42:47.557651 Write leveling (Byte 0): 28 => 28
4907 00:42:47.561787 Write leveling (Byte 1): 25 => 25
4908 00:42:47.564820 DramcWriteLeveling(PI) end<-----
4909 00:42:47.564989
4910 00:42:47.565120 ==
4911 00:42:47.568103 Dram Type= 6, Freq= 0, CH_0, rank 0
4912 00:42:47.571147 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4913 00:42:47.571327 ==
4914 00:42:47.574402 [Gating] SW mode calibration
4915 00:42:47.581479 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
4916 00:42:47.587674 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
4917 00:42:47.590831 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4918 00:42:47.594011 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4919 00:42:47.597618 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4920 00:42:47.604153 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4921 00:42:47.607639 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
4922 00:42:47.610885 0 10 20 | B1->B0 | 3232 3030 | 1 0 | (1 0) (0 1)
4923 00:42:47.617478 0 10 24 | B1->B0 | 2e2e 2727 | 0 0 | (0 0) (0 0)
4924 00:42:47.620699 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4925 00:42:47.624002 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4926 00:42:47.630454 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4927 00:42:47.634036 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4928 00:42:47.637272 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4929 00:42:47.643884 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4930 00:42:47.647542 0 11 20 | B1->B0 | 2424 2f2f | 0 0 | (0 0) (0 0)
4931 00:42:47.650460 0 11 24 | B1->B0 | 3737 4545 | 0 0 | (0 0) (0 0)
4932 00:42:47.656931 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4933 00:42:47.660366 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4934 00:42:47.663541 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4935 00:42:47.670501 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4936 00:42:47.673493 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4937 00:42:47.676759 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4938 00:42:47.683769 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4939 00:42:47.687106 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4940 00:42:47.690064 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4941 00:42:47.697004 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4942 00:42:47.700240 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4943 00:42:47.703281 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4944 00:42:47.710117 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4945 00:42:47.713348 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4946 00:42:47.716865 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4947 00:42:47.723550 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4948 00:42:47.726721 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4949 00:42:47.729926 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4950 00:42:47.736712 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4951 00:42:47.740061 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4952 00:42:47.743410 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4953 00:42:47.749817 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4954 00:42:47.753017 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4955 00:42:47.756416 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4956 00:42:47.759610 Total UI for P1: 0, mck2ui 16
4957 00:42:47.763149 best dqsien dly found for B0: ( 0, 14, 22)
4958 00:42:47.766223 Total UI for P1: 0, mck2ui 16
4959 00:42:47.769668 best dqsien dly found for B1: ( 0, 14, 22)
4960 00:42:47.772859 best DQS0 dly(MCK, UI, PI) = (0, 14, 22)
4961 00:42:47.776326 best DQS1 dly(MCK, UI, PI) = (0, 14, 22)
4962 00:42:47.776407
4963 00:42:47.783047 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 22)
4964 00:42:47.786189 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 22)
4965 00:42:47.786280 [Gating] SW calibration Done
4966 00:42:47.789346 ==
4967 00:42:47.792954 Dram Type= 6, Freq= 0, CH_0, rank 0
4968 00:42:47.796488 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4969 00:42:47.796883 ==
4970 00:42:47.797192 RX Vref Scan: 0
4971 00:42:47.797478
4972 00:42:47.799705 RX Vref 0 -> 0, step: 1
4973 00:42:47.800118
4974 00:42:47.802979 RX Delay -80 -> 252, step: 8
4975 00:42:47.806321 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
4976 00:42:47.809565 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
4977 00:42:47.812825 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
4978 00:42:47.819286 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
4979 00:42:47.822674 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
4980 00:42:47.825944 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
4981 00:42:47.829203 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
4982 00:42:47.832621 iDelay=208, Bit 7, Center 99 (0 ~ 199) 200
4983 00:42:47.835942 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
4984 00:42:47.842886 iDelay=208, Bit 9, Center 67 (-32 ~ 167) 200
4985 00:42:47.845985 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
4986 00:42:47.849144 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
4987 00:42:47.852384 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
4988 00:42:47.859081 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
4989 00:42:47.862288 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
4990 00:42:47.865532 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
4991 00:42:47.865711 ==
4992 00:42:47.869237 Dram Type= 6, Freq= 0, CH_0, rank 0
4993 00:42:47.872882 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4994 00:42:47.873032 ==
4995 00:42:47.875962 DQS Delay:
4996 00:42:47.876190 DQS0 = 0, DQS1 = 0
4997 00:42:47.876338 DQM Delay:
4998 00:42:47.878975 DQM0 = 94, DQM1 = 83
4999 00:42:47.879144 DQ Delay:
5000 00:42:47.882342 DQ0 =91, DQ1 =91, DQ2 =91, DQ3 =91
5001 00:42:47.885807 DQ4 =99, DQ5 =87, DQ6 =103, DQ7 =99
5002 00:42:47.888906 DQ8 =75, DQ9 =67, DQ10 =87, DQ11 =75
5003 00:42:47.892415 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
5004 00:42:47.892543
5005 00:42:47.892642
5006 00:42:47.892735 ==
5007 00:42:47.895489 Dram Type= 6, Freq= 0, CH_0, rank 0
5008 00:42:47.902083 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5009 00:42:47.902223 ==
5010 00:42:47.902328
5011 00:42:47.902420
5012 00:42:47.902506 TX Vref Scan disable
5013 00:42:47.905674 == TX Byte 0 ==
5014 00:42:47.909028 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5015 00:42:47.915807 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5016 00:42:47.915934 == TX Byte 1 ==
5017 00:42:47.919161 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5018 00:42:47.925732 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5019 00:42:47.925861 ==
5020 00:42:47.928922 Dram Type= 6, Freq= 0, CH_0, rank 0
5021 00:42:47.932493 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5022 00:42:47.932622 ==
5023 00:42:47.932721
5024 00:42:47.932813
5025 00:42:47.935676 TX Vref Scan disable
5026 00:42:47.935803 == TX Byte 0 ==
5027 00:42:47.942262 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5028 00:42:47.945658 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5029 00:42:47.945784 == TX Byte 1 ==
5030 00:42:47.952520 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5031 00:42:47.956056 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5032 00:42:47.956494
5033 00:42:47.957005 [DATLAT]
5034 00:42:47.959370 Freq=933, CH0 RK0
5035 00:42:47.959878
5036 00:42:47.960319 DATLAT Default: 0xd
5037 00:42:47.962890 0, 0xFFFF, sum = 0
5038 00:42:47.963292 1, 0xFFFF, sum = 0
5039 00:42:47.966094 2, 0xFFFF, sum = 0
5040 00:42:47.966626 3, 0xFFFF, sum = 0
5041 00:42:47.969478 4, 0xFFFF, sum = 0
5042 00:42:47.969877 5, 0xFFFF, sum = 0
5043 00:42:47.972790 6, 0xFFFF, sum = 0
5044 00:42:47.973191 7, 0xFFFF, sum = 0
5045 00:42:47.975933 8, 0xFFFF, sum = 0
5046 00:42:47.979332 9, 0xFFFF, sum = 0
5047 00:42:47.979737 10, 0x0, sum = 1
5048 00:42:47.980054 11, 0x0, sum = 2
5049 00:42:47.982612 12, 0x0, sum = 3
5050 00:42:47.982899 13, 0x0, sum = 4
5051 00:42:47.986462 best_step = 11
5052 00:42:47.986744
5053 00:42:47.986965 ==
5054 00:42:47.989231 Dram Type= 6, Freq= 0, CH_0, rank 0
5055 00:42:47.992170 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5056 00:42:47.992386 ==
5057 00:42:47.995432 RX Vref Scan: 1
5058 00:42:47.995604
5059 00:42:47.995738 RX Vref 0 -> 0, step: 1
5060 00:42:47.995862
5061 00:42:47.998668 RX Delay -77 -> 252, step: 4
5062 00:42:47.998812
5063 00:42:48.002186 Set Vref, RX VrefLevel [Byte0]: 46
5064 00:42:48.005366 [Byte1]: 49
5065 00:42:48.009926
5066 00:42:48.010049 Final RX Vref Byte 0 = 46 to rank0
5067 00:42:48.013381 Final RX Vref Byte 1 = 49 to rank0
5068 00:42:48.016381 Final RX Vref Byte 0 = 46 to rank1
5069 00:42:48.020029 Final RX Vref Byte 1 = 49 to rank1==
5070 00:42:48.023247 Dram Type= 6, Freq= 0, CH_0, rank 0
5071 00:42:48.029995 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5072 00:42:48.030177 ==
5073 00:42:48.030304 DQS Delay:
5074 00:42:48.030402 DQS0 = 0, DQS1 = 0
5075 00:42:48.033530 DQM Delay:
5076 00:42:48.033736 DQM0 = 97, DQM1 = 86
5077 00:42:48.036579 DQ Delay:
5078 00:42:48.039680 DQ0 =92, DQ1 =98, DQ2 =96, DQ3 =92
5079 00:42:48.042955 DQ4 =100, DQ5 =90, DQ6 =104, DQ7 =104
5080 00:42:48.046593 DQ8 =76, DQ9 =72, DQ10 =84, DQ11 =78
5081 00:42:48.049577 DQ12 =94, DQ13 =94, DQ14 =98, DQ15 =96
5082 00:42:48.049790
5083 00:42:48.049956
5084 00:42:48.056205 [DQSOSCAuto] RK0, (LSB)MR18= 0x2121, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 411 ps
5085 00:42:48.059776 CH0 RK0: MR19=505, MR18=2121
5086 00:42:48.066353 CH0_RK0: MR19=0x505, MR18=0x2121, DQSOSC=411, MR23=63, INC=64, DEC=42
5087 00:42:48.066812
5088 00:42:48.069499 ----->DramcWriteLeveling(PI) begin...
5089 00:42:48.069900 ==
5090 00:42:48.072940 Dram Type= 6, Freq= 0, CH_0, rank 1
5091 00:42:48.076113 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5092 00:42:48.076770 ==
5093 00:42:48.079364 Write leveling (Byte 0): 29 => 29
5094 00:42:48.082773 Write leveling (Byte 1): 26 => 26
5095 00:42:48.085977 DramcWriteLeveling(PI) end<-----
5096 00:42:48.086408
5097 00:42:48.086724 ==
5098 00:42:48.089304 Dram Type= 6, Freq= 0, CH_0, rank 1
5099 00:42:48.092524 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5100 00:42:48.095774 ==
5101 00:42:48.096167 [Gating] SW mode calibration
5102 00:42:48.105673 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5103 00:42:48.109148 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5104 00:42:48.112489 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5105 00:42:48.118844 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5106 00:42:48.122608 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5107 00:42:48.125477 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5108 00:42:48.132554 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5109 00:42:48.135435 0 10 20 | B1->B0 | 3131 2f2f | 0 0 | (0 1) (1 0)
5110 00:42:48.138949 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5111 00:42:48.145707 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5112 00:42:48.148801 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5113 00:42:48.152098 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5114 00:42:48.158716 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5115 00:42:48.162109 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5116 00:42:48.165290 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5117 00:42:48.171914 0 11 20 | B1->B0 | 2c2c 3b3b | 0 0 | (0 0) (1 1)
5118 00:42:48.175388 0 11 24 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
5119 00:42:48.178559 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5120 00:42:48.185118 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5121 00:42:48.188382 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5122 00:42:48.191824 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5123 00:42:48.198357 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5124 00:42:48.201567 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5125 00:42:48.205174 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5126 00:42:48.211411 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5127 00:42:48.214654 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5128 00:42:48.218179 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5129 00:42:48.225017 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5130 00:42:48.228153 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5131 00:42:48.231298 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5132 00:42:48.238074 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5133 00:42:48.241421 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5134 00:42:48.244655 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5135 00:42:48.251373 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5136 00:42:48.255093 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5137 00:42:48.258409 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5138 00:42:48.264814 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5139 00:42:48.268041 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5140 00:42:48.271310 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5141 00:42:48.278277 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5142 00:42:48.281154 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5143 00:42:48.285217 Total UI for P1: 0, mck2ui 16
5144 00:42:48.287784 best dqsien dly found for B0: ( 0, 14, 20)
5145 00:42:48.291334 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5146 00:42:48.294259 Total UI for P1: 0, mck2ui 16
5147 00:42:48.297866 best dqsien dly found for B1: ( 0, 14, 22)
5148 00:42:48.301360 best DQS0 dly(MCK, UI, PI) = (0, 14, 20)
5149 00:42:48.304460 best DQS1 dly(MCK, UI, PI) = (0, 14, 22)
5150 00:42:48.304854
5151 00:42:48.307667 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 20)
5152 00:42:48.314780 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 22)
5153 00:42:48.315177 [Gating] SW calibration Done
5154 00:42:48.315487 ==
5155 00:42:48.317600 Dram Type= 6, Freq= 0, CH_0, rank 1
5156 00:42:48.324532 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5157 00:42:48.325008 ==
5158 00:42:48.325378 RX Vref Scan: 0
5159 00:42:48.325669
5160 00:42:48.327969 RX Vref 0 -> 0, step: 1
5161 00:42:48.328456
5162 00:42:48.330926 RX Delay -80 -> 252, step: 8
5163 00:42:48.334599 iDelay=200, Bit 0, Center 91 (-8 ~ 191) 200
5164 00:42:48.337544 iDelay=200, Bit 1, Center 99 (0 ~ 199) 200
5165 00:42:48.341138 iDelay=200, Bit 2, Center 95 (0 ~ 191) 192
5166 00:42:48.344524 iDelay=200, Bit 3, Center 87 (-8 ~ 183) 192
5167 00:42:48.351161 iDelay=200, Bit 4, Center 99 (0 ~ 199) 200
5168 00:42:48.354192 iDelay=200, Bit 5, Center 87 (-16 ~ 191) 208
5169 00:42:48.357489 iDelay=200, Bit 6, Center 99 (0 ~ 199) 200
5170 00:42:48.360804 iDelay=200, Bit 7, Center 103 (8 ~ 199) 192
5171 00:42:48.364305 iDelay=200, Bit 8, Center 71 (-24 ~ 167) 192
5172 00:42:48.370914 iDelay=200, Bit 9, Center 71 (-24 ~ 167) 192
5173 00:42:48.374250 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5174 00:42:48.377250 iDelay=200, Bit 11, Center 75 (-24 ~ 175) 200
5175 00:42:48.380795 iDelay=200, Bit 12, Center 91 (-8 ~ 191) 200
5176 00:42:48.384404 iDelay=200, Bit 13, Center 91 (-8 ~ 191) 200
5177 00:42:48.387483 iDelay=200, Bit 14, Center 91 (-8 ~ 191) 200
5178 00:42:48.394494 iDelay=200, Bit 15, Center 91 (-8 ~ 191) 200
5179 00:42:48.394894 ==
5180 00:42:48.397350 Dram Type= 6, Freq= 0, CH_0, rank 1
5181 00:42:48.401318 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5182 00:42:48.401977 ==
5183 00:42:48.402472 DQS Delay:
5184 00:42:48.404047 DQS0 = 0, DQS1 = 0
5185 00:42:48.404441 DQM Delay:
5186 00:42:48.407747 DQM0 = 95, DQM1 = 83
5187 00:42:48.408141 DQ Delay:
5188 00:42:48.410801 DQ0 =91, DQ1 =99, DQ2 =95, DQ3 =87
5189 00:42:48.414193 DQ4 =99, DQ5 =87, DQ6 =99, DQ7 =103
5190 00:42:48.417620 DQ8 =71, DQ9 =71, DQ10 =87, DQ11 =75
5191 00:42:48.421114 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
5192 00:42:48.421587
5193 00:42:48.421895
5194 00:42:48.422180 ==
5195 00:42:48.424527 Dram Type= 6, Freq= 0, CH_0, rank 1
5196 00:42:48.427634 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5197 00:42:48.430893 ==
5198 00:42:48.431291
5199 00:42:48.431597
5200 00:42:48.431882 TX Vref Scan disable
5201 00:42:48.434243 == TX Byte 0 ==
5202 00:42:48.437560 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5203 00:42:48.440877 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5204 00:42:48.444088 == TX Byte 1 ==
5205 00:42:48.447359 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5206 00:42:48.450588 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5207 00:42:48.453806 ==
5208 00:42:48.454206 Dram Type= 6, Freq= 0, CH_0, rank 1
5209 00:42:48.460860 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5210 00:42:48.461372 ==
5211 00:42:48.461710
5212 00:42:48.462006
5213 00:42:48.463725 TX Vref Scan disable
5214 00:42:48.464151 == TX Byte 0 ==
5215 00:42:48.470374 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5216 00:42:48.474132 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5217 00:42:48.474685 == TX Byte 1 ==
5218 00:42:48.480691 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5219 00:42:48.483793 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5220 00:42:48.484313
5221 00:42:48.484648 [DATLAT]
5222 00:42:48.487406 Freq=933, CH0 RK1
5223 00:42:48.487926
5224 00:42:48.488259 DATLAT Default: 0xb
5225 00:42:48.490312 0, 0xFFFF, sum = 0
5226 00:42:48.490723 1, 0xFFFF, sum = 0
5227 00:42:48.493858 2, 0xFFFF, sum = 0
5228 00:42:48.494427 3, 0xFFFF, sum = 0
5229 00:42:48.497342 4, 0xFFFF, sum = 0
5230 00:42:48.497929 5, 0xFFFF, sum = 0
5231 00:42:48.500344 6, 0xFFFF, sum = 0
5232 00:42:48.503279 7, 0xFFFF, sum = 0
5233 00:42:48.503719 8, 0xFFFF, sum = 0
5234 00:42:48.506646 9, 0xFFFF, sum = 0
5235 00:42:48.507140 10, 0x0, sum = 1
5236 00:42:48.509793 11, 0x0, sum = 2
5237 00:42:48.510332 12, 0x0, sum = 3
5238 00:42:48.510712 13, 0x0, sum = 4
5239 00:42:48.513262 best_step = 11
5240 00:42:48.513715
5241 00:42:48.514046 ==
5242 00:42:48.516614 Dram Type= 6, Freq= 0, CH_0, rank 1
5243 00:42:48.520152 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5244 00:42:48.520589 ==
5245 00:42:48.523521 RX Vref Scan: 0
5246 00:42:48.523910
5247 00:42:48.524213 RX Vref 0 -> 0, step: 1
5248 00:42:48.526910
5249 00:42:48.527439 RX Delay -69 -> 252, step: 4
5250 00:42:48.534393 iDelay=199, Bit 0, Center 96 (7 ~ 186) 180
5251 00:42:48.537529 iDelay=199, Bit 1, Center 98 (3 ~ 194) 192
5252 00:42:48.540789 iDelay=199, Bit 2, Center 96 (3 ~ 190) 188
5253 00:42:48.544394 iDelay=199, Bit 3, Center 92 (3 ~ 182) 180
5254 00:42:48.547451 iDelay=199, Bit 4, Center 102 (11 ~ 194) 184
5255 00:42:48.550654 iDelay=199, Bit 5, Center 88 (-5 ~ 182) 188
5256 00:42:48.557291 iDelay=199, Bit 6, Center 104 (15 ~ 194) 180
5257 00:42:48.560562 iDelay=199, Bit 7, Center 106 (15 ~ 198) 184
5258 00:42:48.564016 iDelay=199, Bit 8, Center 78 (-9 ~ 166) 176
5259 00:42:48.567381 iDelay=199, Bit 9, Center 72 (-17 ~ 162) 180
5260 00:42:48.570480 iDelay=199, Bit 10, Center 88 (-5 ~ 182) 188
5261 00:42:48.577340 iDelay=199, Bit 11, Center 78 (-9 ~ 166) 176
5262 00:42:48.580768 iDelay=199, Bit 12, Center 92 (3 ~ 182) 180
5263 00:42:48.583683 iDelay=199, Bit 13, Center 90 (-1 ~ 182) 184
5264 00:42:48.587281 iDelay=199, Bit 14, Center 98 (7 ~ 190) 184
5265 00:42:48.590500 iDelay=199, Bit 15, Center 94 (3 ~ 186) 184
5266 00:42:48.590958 ==
5267 00:42:48.593782 Dram Type= 6, Freq= 0, CH_0, rank 1
5268 00:42:48.600735 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5269 00:42:48.601226 ==
5270 00:42:48.601544 DQS Delay:
5271 00:42:48.603813 DQS0 = 0, DQS1 = 0
5272 00:42:48.604290 DQM Delay:
5273 00:42:48.604595 DQM0 = 97, DQM1 = 86
5274 00:42:48.607106 DQ Delay:
5275 00:42:48.610583 DQ0 =96, DQ1 =98, DQ2 =96, DQ3 =92
5276 00:42:48.613740 DQ4 =102, DQ5 =88, DQ6 =104, DQ7 =106
5277 00:42:48.616918 DQ8 =78, DQ9 =72, DQ10 =88, DQ11 =78
5278 00:42:48.620103 DQ12 =92, DQ13 =90, DQ14 =98, DQ15 =94
5279 00:42:48.620495
5280 00:42:48.620798
5281 00:42:48.627170 [DQSOSCAuto] RK1, (LSB)MR18= 0x3333, (MSB)MR19= 0x505, tDQSOscB0 = 405 ps tDQSOscB1 = 405 ps
5282 00:42:48.630445 CH0 RK1: MR19=505, MR18=3333
5283 00:42:48.637214 CH0_RK1: MR19=0x505, MR18=0x3333, DQSOSC=405, MR23=63, INC=66, DEC=44
5284 00:42:48.640215 [RxdqsGatingPostProcess] freq 933
5285 00:42:48.643539 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5286 00:42:48.646656 Pre-setting of DQS Precalculation
5287 00:42:48.653327 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5288 00:42:48.653843 ==
5289 00:42:48.656691 Dram Type= 6, Freq= 0, CH_1, rank 0
5290 00:42:48.660018 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5291 00:42:48.660413 ==
5292 00:42:48.666845 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5293 00:42:48.673494 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
5294 00:42:48.676762 [CA 0] Center 37 (7~68) winsize 62
5295 00:42:48.680117 [CA 1] Center 37 (6~68) winsize 63
5296 00:42:48.683421 [CA 2] Center 34 (4~65) winsize 62
5297 00:42:48.686399 [CA 3] Center 34 (4~65) winsize 62
5298 00:42:48.690021 [CA 4] Center 33 (2~64) winsize 63
5299 00:42:48.693156 [CA 5] Center 33 (3~64) winsize 62
5300 00:42:48.693454
5301 00:42:48.696590 [CmdBusTrainingLP45] Vref(ca) range 1: 39
5302 00:42:48.696942
5303 00:42:48.700251 [CATrainingPosCal] consider 1 rank data
5304 00:42:48.703651 u2DelayCellTimex100 = 270/100 ps
5305 00:42:48.706258 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5306 00:42:48.709564 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5307 00:42:48.713208 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5308 00:42:48.716636 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5309 00:42:48.720139 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
5310 00:42:48.723191 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5311 00:42:48.723580
5312 00:42:48.729791 CA PerBit enable=1, Macro0, CA PI delay=33
5313 00:42:48.730360
5314 00:42:48.730690 [CBTSetCACLKResult] CA Dly = 33
5315 00:42:48.732946 CS Dly: 5 (0~36)
5316 00:42:48.733335 ==
5317 00:42:48.736196 Dram Type= 6, Freq= 0, CH_1, rank 1
5318 00:42:48.739688 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5319 00:42:48.740162 ==
5320 00:42:48.746525 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5321 00:42:48.753145 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5322 00:42:48.756179 [CA 0] Center 37 (7~68) winsize 62
5323 00:42:48.759365 [CA 1] Center 37 (6~68) winsize 63
5324 00:42:48.762758 [CA 2] Center 34 (4~65) winsize 62
5325 00:42:48.766438 [CA 3] Center 34 (4~65) winsize 62
5326 00:42:48.769313 [CA 4] Center 33 (2~64) winsize 63
5327 00:42:48.772817 [CA 5] Center 33 (2~64) winsize 63
5328 00:42:48.773295
5329 00:42:48.775881 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5330 00:42:48.776308
5331 00:42:48.779224 [CATrainingPosCal] consider 2 rank data
5332 00:42:48.782710 u2DelayCellTimex100 = 270/100 ps
5333 00:42:48.786298 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5334 00:42:48.789451 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5335 00:42:48.792817 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5336 00:42:48.795938 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5337 00:42:48.799436 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
5338 00:42:48.802778 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5339 00:42:48.803169
5340 00:42:48.809267 CA PerBit enable=1, Macro0, CA PI delay=33
5341 00:42:48.809657
5342 00:42:48.813075 [CBTSetCACLKResult] CA Dly = 33
5343 00:42:48.813551 CS Dly: 5 (0~37)
5344 00:42:48.813860
5345 00:42:48.815958 ----->DramcWriteLeveling(PI) begin...
5346 00:42:48.816434 ==
5347 00:42:48.819525 Dram Type= 6, Freq= 0, CH_1, rank 0
5348 00:42:48.822413 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5349 00:42:48.825737 ==
5350 00:42:48.826164 Write leveling (Byte 0): 26 => 26
5351 00:42:48.829118 Write leveling (Byte 1): 25 => 25
5352 00:42:48.832278 DramcWriteLeveling(PI) end<-----
5353 00:42:48.832732
5354 00:42:48.833069 ==
5355 00:42:48.835453 Dram Type= 6, Freq= 0, CH_1, rank 0
5356 00:42:48.842255 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5357 00:42:48.842756 ==
5358 00:42:48.843092 [Gating] SW mode calibration
5359 00:42:48.852441 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5360 00:42:48.855444 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5361 00:42:48.862100 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5362 00:42:48.865489 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5363 00:42:48.868546 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5364 00:42:48.875376 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5365 00:42:48.878842 0 10 16 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 1)
5366 00:42:48.882044 0 10 20 | B1->B0 | 3030 2323 | 0 0 | (0 1) (1 0)
5367 00:42:48.888774 0 10 24 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
5368 00:42:48.891709 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5369 00:42:48.895105 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5370 00:42:48.902033 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5371 00:42:48.904876 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5372 00:42:48.908154 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5373 00:42:48.911530 0 11 16 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
5374 00:42:48.918627 0 11 20 | B1->B0 | 2b2b 4646 | 0 0 | (1 1) (0 0)
5375 00:42:48.921861 0 11 24 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
5376 00:42:48.925121 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5377 00:42:48.931574 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5378 00:42:48.934870 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5379 00:42:48.938326 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5380 00:42:48.944680 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5381 00:42:48.948289 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5382 00:42:48.951476 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5383 00:42:48.958005 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5384 00:42:48.961376 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5385 00:42:48.964887 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5386 00:42:48.970969 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5387 00:42:48.974407 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5388 00:42:48.977871 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5389 00:42:48.984760 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5390 00:42:48.988216 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5391 00:42:48.991122 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5392 00:42:48.997631 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5393 00:42:49.001020 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5394 00:42:49.004249 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5395 00:42:49.010821 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5396 00:42:49.014346 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5397 00:42:49.017548 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5398 00:42:49.024406 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5399 00:42:49.027542 Total UI for P1: 0, mck2ui 16
5400 00:42:49.030899 best dqsien dly found for B0: ( 0, 14, 16)
5401 00:42:49.034252 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5402 00:42:49.037135 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5403 00:42:49.040601 Total UI for P1: 0, mck2ui 16
5404 00:42:49.043831 best dqsien dly found for B1: ( 0, 14, 22)
5405 00:42:49.047172 best DQS0 dly(MCK, UI, PI) = (0, 14, 16)
5406 00:42:49.050733 best DQS1 dly(MCK, UI, PI) = (0, 14, 22)
5407 00:42:49.053831
5408 00:42:49.057181 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 16)
5409 00:42:49.060675 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 22)
5410 00:42:49.063840 [Gating] SW calibration Done
5411 00:42:49.064237 ==
5412 00:42:49.067039 Dram Type= 6, Freq= 0, CH_1, rank 0
5413 00:42:49.070309 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5414 00:42:49.070712 ==
5415 00:42:49.071026 RX Vref Scan: 0
5416 00:42:49.073701
5417 00:42:49.074092 RX Vref 0 -> 0, step: 1
5418 00:42:49.074453
5419 00:42:49.077009 RX Delay -80 -> 252, step: 8
5420 00:42:49.080747 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5421 00:42:49.083612 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5422 00:42:49.089965 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5423 00:42:49.093356 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5424 00:42:49.097234 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5425 00:42:49.100051 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5426 00:42:49.103280 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5427 00:42:49.106697 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5428 00:42:49.113581 iDelay=208, Bit 8, Center 71 (-24 ~ 167) 192
5429 00:42:49.116973 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5430 00:42:49.120294 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5431 00:42:49.123464 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5432 00:42:49.126925 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5433 00:42:49.133717 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5434 00:42:49.136381 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5435 00:42:49.139645 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5436 00:42:49.140090 ==
5437 00:42:49.142875 Dram Type= 6, Freq= 0, CH_1, rank 0
5438 00:42:49.146492 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5439 00:42:49.147014 ==
5440 00:42:49.149510 DQS Delay:
5441 00:42:49.149945 DQS0 = 0, DQS1 = 0
5442 00:42:49.153102 DQM Delay:
5443 00:42:49.153624 DQM0 = 95, DQM1 = 89
5444 00:42:49.153970 DQ Delay:
5445 00:42:49.156154 DQ0 =99, DQ1 =91, DQ2 =87, DQ3 =91
5446 00:42:49.159646 DQ4 =91, DQ5 =107, DQ6 =103, DQ7 =91
5447 00:42:49.162569 DQ8 =71, DQ9 =79, DQ10 =91, DQ11 =83
5448 00:42:49.166114 DQ12 =95, DQ13 =99, DQ14 =95, DQ15 =99
5449 00:42:49.166582
5450 00:42:49.166922
5451 00:42:49.169294 ==
5452 00:42:49.172489 Dram Type= 6, Freq= 0, CH_1, rank 0
5453 00:42:49.175903 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5454 00:42:49.176382 ==
5455 00:42:49.176840
5456 00:42:49.177253
5457 00:42:49.179213 TX Vref Scan disable
5458 00:42:49.179663 == TX Byte 0 ==
5459 00:42:49.182467 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5460 00:42:49.189232 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5461 00:42:49.189648 == TX Byte 1 ==
5462 00:42:49.192432 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5463 00:42:49.199514 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5464 00:42:49.199913 ==
5465 00:42:49.202424 Dram Type= 6, Freq= 0, CH_1, rank 0
5466 00:42:49.206003 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5467 00:42:49.206531 ==
5468 00:42:49.206847
5469 00:42:49.207207
5470 00:42:49.209039 TX Vref Scan disable
5471 00:42:49.212640 == TX Byte 0 ==
5472 00:42:49.216041 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5473 00:42:49.219454 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5474 00:42:49.222534 == TX Byte 1 ==
5475 00:42:49.225859 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5476 00:42:49.228853 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5477 00:42:49.229345
5478 00:42:49.232239 [DATLAT]
5479 00:42:49.232710 Freq=933, CH1 RK0
5480 00:42:49.233020
5481 00:42:49.235564 DATLAT Default: 0xd
5482 00:42:49.235956 0, 0xFFFF, sum = 0
5483 00:42:49.238966 1, 0xFFFF, sum = 0
5484 00:42:49.239368 2, 0xFFFF, sum = 0
5485 00:42:49.241898 3, 0xFFFF, sum = 0
5486 00:42:49.242336 4, 0xFFFF, sum = 0
5487 00:42:49.245485 5, 0xFFFF, sum = 0
5488 00:42:49.246168 6, 0xFFFF, sum = 0
5489 00:42:49.249208 7, 0xFFFF, sum = 0
5490 00:42:49.249700 8, 0xFFFF, sum = 0
5491 00:42:49.251871 9, 0xFFFF, sum = 0
5492 00:42:49.252271 10, 0x0, sum = 1
5493 00:42:49.255040 11, 0x0, sum = 2
5494 00:42:49.255469 12, 0x0, sum = 3
5495 00:42:49.258468 13, 0x0, sum = 4
5496 00:42:49.258871 best_step = 11
5497 00:42:49.259183
5498 00:42:49.259471 ==
5499 00:42:49.261790 Dram Type= 6, Freq= 0, CH_1, rank 0
5500 00:42:49.268427 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5501 00:42:49.268827 ==
5502 00:42:49.269139 RX Vref Scan: 1
5503 00:42:49.269428
5504 00:42:49.271735 RX Vref 0 -> 0, step: 1
5505 00:42:49.272132
5506 00:42:49.274978 RX Delay -69 -> 252, step: 4
5507 00:42:49.275377
5508 00:42:49.278153 Set Vref, RX VrefLevel [Byte0]: 52
5509 00:42:49.281984 [Byte1]: 49
5510 00:42:49.282557
5511 00:42:49.284968 Final RX Vref Byte 0 = 52 to rank0
5512 00:42:49.288245 Final RX Vref Byte 1 = 49 to rank0
5513 00:42:49.291735 Final RX Vref Byte 0 = 52 to rank1
5514 00:42:49.294694 Final RX Vref Byte 1 = 49 to rank1==
5515 00:42:49.298071 Dram Type= 6, Freq= 0, CH_1, rank 0
5516 00:42:49.301594 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5517 00:42:49.302066 ==
5518 00:42:49.304686 DQS Delay:
5519 00:42:49.305116 DQS0 = 0, DQS1 = 0
5520 00:42:49.308010 DQM Delay:
5521 00:42:49.308461 DQM0 = 94, DQM1 = 87
5522 00:42:49.308770 DQ Delay:
5523 00:42:49.311360 DQ0 =98, DQ1 =88, DQ2 =86, DQ3 =90
5524 00:42:49.314755 DQ4 =94, DQ5 =104, DQ6 =102, DQ7 =92
5525 00:42:49.318155 DQ8 =70, DQ9 =76, DQ10 =88, DQ11 =80
5526 00:42:49.321091 DQ12 =94, DQ13 =98, DQ14 =96, DQ15 =94
5527 00:42:49.321569
5528 00:42:49.322007
5529 00:42:49.331650 [DQSOSCAuto] RK0, (LSB)MR18= 0x3636, (MSB)MR19= 0x505, tDQSOscB0 = 404 ps tDQSOscB1 = 404 ps
5530 00:42:49.334542 CH1 RK0: MR19=505, MR18=3636
5531 00:42:49.340956 CH1_RK0: MR19=0x505, MR18=0x3636, DQSOSC=404, MR23=63, INC=66, DEC=44
5532 00:42:49.341350
5533 00:42:49.344334 ----->DramcWriteLeveling(PI) begin...
5534 00:42:49.344847 ==
5535 00:42:49.347843 Dram Type= 6, Freq= 0, CH_1, rank 1
5536 00:42:49.350766 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5537 00:42:49.351163 ==
5538 00:42:49.354411 Write leveling (Byte 0): 22 => 22
5539 00:42:49.357971 Write leveling (Byte 1): 22 => 22
5540 00:42:49.360916 DramcWriteLeveling(PI) end<-----
5541 00:42:49.361484
5542 00:42:49.361915 ==
5543 00:42:49.363972 Dram Type= 6, Freq= 0, CH_1, rank 1
5544 00:42:49.367296 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5545 00:42:49.367743 ==
5546 00:42:49.370637 [Gating] SW mode calibration
5547 00:42:49.377524 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5548 00:42:49.384593 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5549 00:42:49.387584 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5550 00:42:49.390689 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5551 00:42:49.397409 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5552 00:42:49.400607 0 10 12 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
5553 00:42:49.404216 0 10 16 | B1->B0 | 3434 2626 | 1 0 | (1 0) (0 0)
5554 00:42:49.410672 0 10 20 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
5555 00:42:49.413765 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5556 00:42:49.417055 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5557 00:42:49.423985 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5558 00:42:49.426826 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5559 00:42:49.430316 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5560 00:42:49.437066 0 11 12 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
5561 00:42:49.440305 0 11 16 | B1->B0 | 2323 3d3d | 0 0 | (0 0) (1 1)
5562 00:42:49.443479 0 11 20 | B1->B0 | 3838 4646 | 1 0 | (0 0) (0 0)
5563 00:42:49.450333 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5564 00:42:49.453625 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5565 00:42:49.456925 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5566 00:42:49.463502 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5567 00:42:49.466821 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5568 00:42:49.469964 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5569 00:42:49.476538 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5570 00:42:49.480383 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5571 00:42:49.483580 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5572 00:42:49.490476 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5573 00:42:49.493424 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5574 00:42:49.496435 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5575 00:42:49.503119 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5576 00:42:49.506802 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5577 00:42:49.509582 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5578 00:42:49.516718 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5579 00:42:49.519888 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5580 00:42:49.522816 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5581 00:42:49.529439 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5582 00:42:49.532945 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5583 00:42:49.536446 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5584 00:42:49.542867 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5585 00:42:49.546026 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5586 00:42:49.549580 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5587 00:42:49.552734 Total UI for P1: 0, mck2ui 16
5588 00:42:49.555897 best dqsien dly found for B0: ( 0, 14, 14)
5589 00:42:49.559284 Total UI for P1: 0, mck2ui 16
5590 00:42:49.562720 best dqsien dly found for B1: ( 0, 14, 18)
5591 00:42:49.566112 best DQS0 dly(MCK, UI, PI) = (0, 14, 14)
5592 00:42:49.569471 best DQS1 dly(MCK, UI, PI) = (0, 14, 18)
5593 00:42:49.569985
5594 00:42:49.575958 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 14)
5595 00:42:49.579118 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 18)
5596 00:42:49.579565 [Gating] SW calibration Done
5597 00:42:49.582414 ==
5598 00:42:49.585887 Dram Type= 6, Freq= 0, CH_1, rank 1
5599 00:42:49.589607 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5600 00:42:49.590267 ==
5601 00:42:49.590642 RX Vref Scan: 0
5602 00:42:49.591062
5603 00:42:49.592098 RX Vref 0 -> 0, step: 1
5604 00:42:49.592605
5605 00:42:49.595655 RX Delay -80 -> 252, step: 8
5606 00:42:49.598681 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5607 00:42:49.602371 iDelay=208, Bit 1, Center 87 (-8 ~ 183) 192
5608 00:42:49.605632 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5609 00:42:49.612318 iDelay=208, Bit 3, Center 91 (0 ~ 183) 184
5610 00:42:49.615321 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5611 00:42:49.619028 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5612 00:42:49.622377 iDelay=208, Bit 6, Center 99 (0 ~ 199) 200
5613 00:42:49.625625 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5614 00:42:49.628920 iDelay=208, Bit 8, Center 71 (-24 ~ 167) 192
5615 00:42:49.635119 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5616 00:42:49.638580 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5617 00:42:49.641969 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5618 00:42:49.645683 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5619 00:42:49.648971 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5620 00:42:49.655171 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5621 00:42:49.658237 iDelay=208, Bit 15, Center 91 (0 ~ 183) 184
5622 00:42:49.658680 ==
5623 00:42:49.661621 Dram Type= 6, Freq= 0, CH_1, rank 1
5624 00:42:49.665463 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5625 00:42:49.665984 ==
5626 00:42:49.668252 DQS Delay:
5627 00:42:49.668685 DQS0 = 0, DQS1 = 0
5628 00:42:49.669027 DQM Delay:
5629 00:42:49.671601 DQM0 = 94, DQM1 = 85
5630 00:42:49.672039 DQ Delay:
5631 00:42:49.674977 DQ0 =95, DQ1 =87, DQ2 =87, DQ3 =91
5632 00:42:49.678392 DQ4 =95, DQ5 =107, DQ6 =99, DQ7 =91
5633 00:42:49.681928 DQ8 =71, DQ9 =75, DQ10 =87, DQ11 =75
5634 00:42:49.685441 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =91
5635 00:42:49.685954
5636 00:42:49.686339
5637 00:42:49.686662 ==
5638 00:42:49.688516 Dram Type= 6, Freq= 0, CH_1, rank 1
5639 00:42:49.695109 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5640 00:42:49.695650 ==
5641 00:42:49.696184
5642 00:42:49.696680
5643 00:42:49.697009 TX Vref Scan disable
5644 00:42:49.698101 == TX Byte 0 ==
5645 00:42:49.701971 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5646 00:42:49.707985 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5647 00:42:49.708428 == TX Byte 1 ==
5648 00:42:49.711359 Update DQ dly =705 (2 ,5, 33) DQ OEN =(2 ,2)
5649 00:42:49.718049 Update DQM dly =705 (2 ,5, 33) DQM OEN =(2 ,2)
5650 00:42:49.718514 ==
5651 00:42:49.721364 Dram Type= 6, Freq= 0, CH_1, rank 1
5652 00:42:49.725023 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5653 00:42:49.725539 ==
5654 00:42:49.725877
5655 00:42:49.726183
5656 00:42:49.728085 TX Vref Scan disable
5657 00:42:49.728534 == TX Byte 0 ==
5658 00:42:49.734597 Update DQ dly =705 (2 ,5, 33) DQ OEN =(2 ,2)
5659 00:42:49.738481 Update DQM dly =705 (2 ,5, 33) DQM OEN =(2 ,2)
5660 00:42:49.739000 == TX Byte 1 ==
5661 00:42:49.745108 Update DQ dly =705 (2 ,5, 33) DQ OEN =(2 ,2)
5662 00:42:49.747924 Update DQM dly =705 (2 ,5, 33) DQM OEN =(2 ,2)
5663 00:42:49.748361
5664 00:42:49.748700 [DATLAT]
5665 00:42:49.751144 Freq=933, CH1 RK1
5666 00:42:49.751580
5667 00:42:49.751919 DATLAT Default: 0xb
5668 00:42:49.754450 0, 0xFFFF, sum = 0
5669 00:42:49.754891 1, 0xFFFF, sum = 0
5670 00:42:49.757709 2, 0xFFFF, sum = 0
5671 00:42:49.758150 3, 0xFFFF, sum = 0
5672 00:42:49.761146 4, 0xFFFF, sum = 0
5673 00:42:49.764636 5, 0xFFFF, sum = 0
5674 00:42:49.765159 6, 0xFFFF, sum = 0
5675 00:42:49.767665 7, 0xFFFF, sum = 0
5676 00:42:49.768108 8, 0xFFFF, sum = 0
5677 00:42:49.770888 9, 0xFFFF, sum = 0
5678 00:42:49.771344 10, 0x0, sum = 1
5679 00:42:49.774464 11, 0x0, sum = 2
5680 00:42:49.774987 12, 0x0, sum = 3
5681 00:42:49.775337 13, 0x0, sum = 4
5682 00:42:49.777455 best_step = 11
5683 00:42:49.777887
5684 00:42:49.778268 ==
5685 00:42:49.781093 Dram Type= 6, Freq= 0, CH_1, rank 1
5686 00:42:49.784451 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5687 00:42:49.784966 ==
5688 00:42:49.787597 RX Vref Scan: 0
5689 00:42:49.788060
5690 00:42:49.791114 RX Vref 0 -> 0, step: 1
5691 00:42:49.791546
5692 00:42:49.791881 RX Delay -69 -> 252, step: 4
5693 00:42:49.798705 iDelay=203, Bit 0, Center 96 (7 ~ 186) 180
5694 00:42:49.801940 iDelay=203, Bit 1, Center 92 (3 ~ 182) 180
5695 00:42:49.805146 iDelay=203, Bit 2, Center 86 (-5 ~ 178) 184
5696 00:42:49.808709 iDelay=203, Bit 3, Center 92 (3 ~ 182) 180
5697 00:42:49.811777 iDelay=203, Bit 4, Center 96 (3 ~ 190) 188
5698 00:42:49.814934 iDelay=203, Bit 5, Center 108 (15 ~ 202) 188
5699 00:42:49.821740 iDelay=203, Bit 6, Center 104 (11 ~ 198) 188
5700 00:42:49.825139 iDelay=203, Bit 7, Center 94 (3 ~ 186) 184
5701 00:42:49.828338 iDelay=203, Bit 8, Center 72 (-17 ~ 162) 180
5702 00:42:49.831928 iDelay=203, Bit 9, Center 74 (-17 ~ 166) 184
5703 00:42:49.835034 iDelay=203, Bit 10, Center 86 (-5 ~ 178) 184
5704 00:42:49.841769 iDelay=203, Bit 11, Center 80 (-9 ~ 170) 180
5705 00:42:49.844968 iDelay=203, Bit 12, Center 94 (3 ~ 186) 184
5706 00:42:49.848451 iDelay=203, Bit 13, Center 96 (7 ~ 186) 180
5707 00:42:49.851735 iDelay=203, Bit 14, Center 96 (3 ~ 190) 188
5708 00:42:49.854883 iDelay=203, Bit 15, Center 96 (7 ~ 186) 180
5709 00:42:49.855318 ==
5710 00:42:49.858183 Dram Type= 6, Freq= 0, CH_1, rank 1
5711 00:42:49.864620 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5712 00:42:49.865078 ==
5713 00:42:49.865422 DQS Delay:
5714 00:42:49.868375 DQS0 = 0, DQS1 = 0
5715 00:42:49.868806 DQM Delay:
5716 00:42:49.869147 DQM0 = 96, DQM1 = 86
5717 00:42:49.871465 DQ Delay:
5718 00:42:49.874791 DQ0 =96, DQ1 =92, DQ2 =86, DQ3 =92
5719 00:42:49.877957 DQ4 =96, DQ5 =108, DQ6 =104, DQ7 =94
5720 00:42:49.881577 DQ8 =72, DQ9 =74, DQ10 =86, DQ11 =80
5721 00:42:49.884496 DQ12 =94, DQ13 =96, DQ14 =96, DQ15 =96
5722 00:42:49.884930
5723 00:42:49.885264
5724 00:42:49.891055 [DQSOSCAuto] RK1, (LSB)MR18= 0x2929, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 408 ps
5725 00:42:49.894593 CH1 RK1: MR19=505, MR18=2929
5726 00:42:49.901658 CH1_RK1: MR19=0x505, MR18=0x2929, DQSOSC=408, MR23=63, INC=65, DEC=43
5727 00:42:49.904489 [RxdqsGatingPostProcess] freq 933
5728 00:42:49.908258 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5729 00:42:49.911202 Pre-setting of DQS Precalculation
5730 00:42:49.918026 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5731 00:42:49.924619 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5732 00:42:49.931222 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5733 00:42:49.931723
5734 00:42:49.932060
5735 00:42:49.934677 [Calibration Summary] 1866 Mbps
5736 00:42:49.935213 CH 0, Rank 0
5737 00:42:49.938470 SW Impedance : PASS
5738 00:42:49.941408 DUTY Scan : NO K
5739 00:42:49.941843 ZQ Calibration : PASS
5740 00:42:49.944643 Jitter Meter : NO K
5741 00:42:49.947787 CBT Training : PASS
5742 00:42:49.948225 Write leveling : PASS
5743 00:42:49.951281 RX DQS gating : PASS
5744 00:42:49.954557 RX DQ/DQS(RDDQC) : PASS
5745 00:42:49.954991 TX DQ/DQS : PASS
5746 00:42:49.957879 RX DATLAT : PASS
5747 00:42:49.960841 RX DQ/DQS(Engine): PASS
5748 00:42:49.961272 TX OE : NO K
5749 00:42:49.964719 All Pass.
5750 00:42:49.965236
5751 00:42:49.965600 CH 0, Rank 1
5752 00:42:49.967668 SW Impedance : PASS
5753 00:42:49.968102 DUTY Scan : NO K
5754 00:42:49.971077 ZQ Calibration : PASS
5755 00:42:49.974403 Jitter Meter : NO K
5756 00:42:49.974840 CBT Training : PASS
5757 00:42:49.977691 Write leveling : PASS
5758 00:42:49.978202 RX DQS gating : PASS
5759 00:42:49.980931 RX DQ/DQS(RDDQC) : PASS
5760 00:42:49.984518 TX DQ/DQS : PASS
5761 00:42:49.985032 RX DATLAT : PASS
5762 00:42:49.987807 RX DQ/DQS(Engine): PASS
5763 00:42:49.991009 TX OE : NO K
5764 00:42:49.991442 All Pass.
5765 00:42:49.991816
5766 00:42:49.992243 CH 1, Rank 0
5767 00:42:49.993930 SW Impedance : PASS
5768 00:42:49.997270 DUTY Scan : NO K
5769 00:42:49.997948 ZQ Calibration : PASS
5770 00:42:50.000921 Jitter Meter : NO K
5771 00:42:50.004177 CBT Training : PASS
5772 00:42:50.004609 Write leveling : PASS
5773 00:42:50.007498 RX DQS gating : PASS
5774 00:42:50.010907 RX DQ/DQS(RDDQC) : PASS
5775 00:42:50.011346 TX DQ/DQS : PASS
5776 00:42:50.013909 RX DATLAT : PASS
5777 00:42:50.017209 RX DQ/DQS(Engine): PASS
5778 00:42:50.017644 TX OE : NO K
5779 00:42:50.020686 All Pass.
5780 00:42:50.021198
5781 00:42:50.021535 CH 1, Rank 1
5782 00:42:50.023758 SW Impedance : PASS
5783 00:42:50.024362 DUTY Scan : NO K
5784 00:42:50.027194 ZQ Calibration : PASS
5785 00:42:50.030417 Jitter Meter : NO K
5786 00:42:50.030854 CBT Training : PASS
5787 00:42:50.034015 Write leveling : PASS
5788 00:42:50.037024 RX DQS gating : PASS
5789 00:42:50.037460 RX DQ/DQS(RDDQC) : PASS
5790 00:42:50.040471 TX DQ/DQS : PASS
5791 00:42:50.043647 RX DATLAT : PASS
5792 00:42:50.044081 RX DQ/DQS(Engine): PASS
5793 00:42:50.047559 TX OE : NO K
5794 00:42:50.047998 All Pass.
5795 00:42:50.048337
5796 00:42:50.050123 DramC Write-DBI off
5797 00:42:50.053920 PER_BANK_REFRESH: Hybrid Mode
5798 00:42:50.054404 TX_TRACKING: ON
5799 00:42:50.063549 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
5800 00:42:50.067212 [FAST_K] Save calibration result to emmc
5801 00:42:50.070056 dramc_set_vcore_voltage set vcore to 650000
5802 00:42:50.073462 Read voltage for 400, 6
5803 00:42:50.073858 Vio18 = 0
5804 00:42:50.074165 Vcore = 650000
5805 00:42:50.076506 Vdram = 0
5806 00:42:50.076899 Vddq = 0
5807 00:42:50.077202 Vmddr = 0
5808 00:42:50.083512 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
5809 00:42:50.086525 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
5810 00:42:50.090341 MEM_TYPE=3, freq_sel=20
5811 00:42:50.093296 sv_algorithm_assistance_LP4_800
5812 00:42:50.096571 ============ PULL DRAM RESETB DOWN ============
5813 00:42:50.099780 ========== PULL DRAM RESETB DOWN end =========
5814 00:42:50.106713 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5815 00:42:50.109930 ===================================
5816 00:42:50.110351 LPDDR4 DRAM CONFIGURATION
5817 00:42:50.113339 ===================================
5818 00:42:50.116476 EX_ROW_EN[0] = 0x0
5819 00:42:50.119857 EX_ROW_EN[1] = 0x0
5820 00:42:50.120250 LP4Y_EN = 0x0
5821 00:42:50.123470 WORK_FSP = 0x0
5822 00:42:50.123862 WL = 0x2
5823 00:42:50.126321 RL = 0x2
5824 00:42:50.126717 BL = 0x2
5825 00:42:50.129590 RPST = 0x0
5826 00:42:50.129985 RD_PRE = 0x0
5827 00:42:50.133040 WR_PRE = 0x1
5828 00:42:50.133451 WR_PST = 0x0
5829 00:42:50.136106 DBI_WR = 0x0
5830 00:42:50.136514 DBI_RD = 0x0
5831 00:42:50.139619 OTF = 0x1
5832 00:42:50.142940 ===================================
5833 00:42:50.146146 ===================================
5834 00:42:50.146643 ANA top config
5835 00:42:50.149370 ===================================
5836 00:42:50.152809 DLL_ASYNC_EN = 0
5837 00:42:50.156185 ALL_SLAVE_EN = 1
5838 00:42:50.159634 NEW_RANK_MODE = 1
5839 00:42:50.160151 DLL_IDLE_MODE = 1
5840 00:42:50.162620 LP45_APHY_COMB_EN = 1
5841 00:42:50.165864 TX_ODT_DIS = 1
5842 00:42:50.169496 NEW_8X_MODE = 1
5843 00:42:50.172508 ===================================
5844 00:42:50.176262 ===================================
5845 00:42:50.179540 data_rate = 800
5846 00:42:50.180017 CKR = 1
5847 00:42:50.182520 DQ_P2S_RATIO = 4
5848 00:42:50.186143 ===================================
5849 00:42:50.189199 CA_P2S_RATIO = 4
5850 00:42:50.192338 DQ_CA_OPEN = 0
5851 00:42:50.195856 DQ_SEMI_OPEN = 1
5852 00:42:50.199320 CA_SEMI_OPEN = 1
5853 00:42:50.199732 CA_FULL_RATE = 0
5854 00:42:50.202401 DQ_CKDIV4_EN = 0
5855 00:42:50.205668 CA_CKDIV4_EN = 1
5856 00:42:50.209260 CA_PREDIV_EN = 0
5857 00:42:50.212370 PH8_DLY = 0
5858 00:42:50.215530 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
5859 00:42:50.215920 DQ_AAMCK_DIV = 0
5860 00:42:50.219146 CA_AAMCK_DIV = 0
5861 00:42:50.222119 CA_ADMCK_DIV = 4
5862 00:42:50.225553 DQ_TRACK_CA_EN = 0
5863 00:42:50.228912 CA_PICK = 800
5864 00:42:50.232352 CA_MCKIO = 400
5865 00:42:50.235921 MCKIO_SEMI = 400
5866 00:42:50.236313 PLL_FREQ = 3016
5867 00:42:50.239389 DQ_UI_PI_RATIO = 32
5868 00:42:50.242277 CA_UI_PI_RATIO = 32
5869 00:42:50.245657 ===================================
5870 00:42:50.248823 ===================================
5871 00:42:50.251959 memory_type:LPDDR4
5872 00:42:50.255217 GP_NUM : 10
5873 00:42:50.255651 SRAM_EN : 1
5874 00:42:50.258615 MD32_EN : 0
5875 00:42:50.262117 ===================================
5876 00:42:50.262626 [ANA_INIT] >>>>>>>>>>>>>>
5877 00:42:50.265218 <<<<<< [CONFIGURE PHASE]: ANA_TX
5878 00:42:50.268817 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5879 00:42:50.272039 ===================================
5880 00:42:50.275125 data_rate = 800,PCW = 0X7400
5881 00:42:50.278607 ===================================
5882 00:42:50.281835 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5883 00:42:50.288329 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5884 00:42:50.298664 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5885 00:42:50.305185 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5886 00:42:50.308472 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5887 00:42:50.311631 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5888 00:42:50.312083 [ANA_INIT] flow start
5889 00:42:50.315018 [ANA_INIT] PLL >>>>>>>>
5890 00:42:50.318544 [ANA_INIT] PLL <<<<<<<<
5891 00:42:50.318936 [ANA_INIT] MIDPI >>>>>>>>
5892 00:42:50.321942 [ANA_INIT] MIDPI <<<<<<<<
5893 00:42:50.324976 [ANA_INIT] DLL >>>>>>>>
5894 00:42:50.325368 [ANA_INIT] flow end
5895 00:42:50.332246 ============ LP4 DIFF to SE enter ============
5896 00:42:50.335196 ============ LP4 DIFF to SE exit ============
5897 00:42:50.338534 [ANA_INIT] <<<<<<<<<<<<<
5898 00:42:50.341675 [Flow] Enable top DCM control >>>>>
5899 00:42:50.344998 [Flow] Enable top DCM control <<<<<
5900 00:42:50.345517 Enable DLL master slave shuffle
5901 00:42:50.351992 ==============================================================
5902 00:42:50.355025 Gating Mode config
5903 00:42:50.358322 ==============================================================
5904 00:42:50.361348 Config description:
5905 00:42:50.371684 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5906 00:42:50.377965 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5907 00:42:50.381345 SELPH_MODE 0: By rank 1: By Phase
5908 00:42:50.387977 ==============================================================
5909 00:42:50.391460 GAT_TRACK_EN = 0
5910 00:42:50.394418 RX_GATING_MODE = 2
5911 00:42:50.397702 RX_GATING_TRACK_MODE = 2
5912 00:42:50.401124 SELPH_MODE = 1
5913 00:42:50.404833 PICG_EARLY_EN = 1
5914 00:42:50.405355 VALID_LAT_VALUE = 1
5915 00:42:50.410983 ==============================================================
5916 00:42:50.414328 Enter into Gating configuration >>>>
5917 00:42:50.417642 Exit from Gating configuration <<<<
5918 00:42:50.420926 Enter into DVFS_PRE_config >>>>>
5919 00:42:50.431047 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5920 00:42:50.434578 Exit from DVFS_PRE_config <<<<<
5921 00:42:50.437876 Enter into PICG configuration >>>>
5922 00:42:50.440918 Exit from PICG configuration <<<<
5923 00:42:50.444064 [RX_INPUT] configuration >>>>>
5924 00:42:50.447878 [RX_INPUT] configuration <<<<<
5925 00:42:50.450906 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5926 00:42:50.457785 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5927 00:42:50.464719 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5928 00:42:50.470826 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5929 00:42:50.477452 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5930 00:42:50.484283 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5931 00:42:50.487637 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5932 00:42:50.490433 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5933 00:42:50.494127 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5934 00:42:50.500439 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5935 00:42:50.504232 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5936 00:42:50.507188 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5937 00:42:50.510600 ===================================
5938 00:42:50.513806 LPDDR4 DRAM CONFIGURATION
5939 00:42:50.517154 ===================================
5940 00:42:50.517599 EX_ROW_EN[0] = 0x0
5941 00:42:50.520280 EX_ROW_EN[1] = 0x0
5942 00:42:50.520721 LP4Y_EN = 0x0
5943 00:42:50.523682 WORK_FSP = 0x0
5944 00:42:50.526980 WL = 0x2
5945 00:42:50.527463 RL = 0x2
5946 00:42:50.530157 BL = 0x2
5947 00:42:50.530585 RPST = 0x0
5948 00:42:50.533457 RD_PRE = 0x0
5949 00:42:50.533850 WR_PRE = 0x1
5950 00:42:50.536989 WR_PST = 0x0
5951 00:42:50.537390 DBI_WR = 0x0
5952 00:42:50.540167 DBI_RD = 0x0
5953 00:42:50.540651 OTF = 0x1
5954 00:42:50.543466 ===================================
5955 00:42:50.546863 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5956 00:42:50.553444 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5957 00:42:50.556910 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5958 00:42:50.559910 ===================================
5959 00:42:50.563292 LPDDR4 DRAM CONFIGURATION
5960 00:42:50.566834 ===================================
5961 00:42:50.567633 EX_ROW_EN[0] = 0x10
5962 00:42:50.569862 EX_ROW_EN[1] = 0x0
5963 00:42:50.570280 LP4Y_EN = 0x0
5964 00:42:50.573369 WORK_FSP = 0x0
5965 00:42:50.573764 WL = 0x2
5966 00:42:50.576822 RL = 0x2
5967 00:42:50.580325 BL = 0x2
5968 00:42:50.580719 RPST = 0x0
5969 00:42:50.583592 RD_PRE = 0x0
5970 00:42:50.584072 WR_PRE = 0x1
5971 00:42:50.586416 WR_PST = 0x0
5972 00:42:50.586813 DBI_WR = 0x0
5973 00:42:50.589840 DBI_RD = 0x0
5974 00:42:50.590256 OTF = 0x1
5975 00:42:50.592968 ===================================
5976 00:42:50.599731 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5977 00:42:50.603691 nWR fixed to 30
5978 00:42:50.607126 [ModeRegInit_LP4] CH0 RK0
5979 00:42:50.607538 [ModeRegInit_LP4] CH0 RK1
5980 00:42:50.610470 [ModeRegInit_LP4] CH1 RK0
5981 00:42:50.614113 [ModeRegInit_LP4] CH1 RK1
5982 00:42:50.614553 match AC timing 18
5983 00:42:50.620421 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 0
5984 00:42:50.623626 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5985 00:42:50.627135 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
5986 00:42:50.633943 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
5987 00:42:50.636805 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
5988 00:42:50.637206 ==
5989 00:42:50.640291 Dram Type= 6, Freq= 0, CH_0, rank 0
5990 00:42:50.643694 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
5991 00:42:50.644193 ==
5992 00:42:50.649987 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
5993 00:42:50.656837 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5994 00:42:50.659951 [CA 0] Center 36 (8~64) winsize 57
5995 00:42:50.663308 [CA 1] Center 36 (8~64) winsize 57
5996 00:42:50.666651 [CA 2] Center 36 (8~64) winsize 57
5997 00:42:50.670325 [CA 3] Center 36 (8~64) winsize 57
5998 00:42:50.670851 [CA 4] Center 36 (8~64) winsize 57
5999 00:42:50.673942 [CA 5] Center 36 (8~64) winsize 57
6000 00:42:50.674414
6001 00:42:50.680107 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6002 00:42:50.680616
6003 00:42:50.683408 [CATrainingPosCal] consider 1 rank data
6004 00:42:50.686852 u2DelayCellTimex100 = 270/100 ps
6005 00:42:50.690336 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6006 00:42:50.693410 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6007 00:42:50.696503 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6008 00:42:50.699736 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6009 00:42:50.703643 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6010 00:42:50.706705 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6011 00:42:50.707217
6012 00:42:50.710009 CA PerBit enable=1, Macro0, CA PI delay=36
6013 00:42:50.710497
6014 00:42:50.712929 [CBTSetCACLKResult] CA Dly = 36
6015 00:42:50.716858 CS Dly: 1 (0~32)
6016 00:42:50.717379 ==
6017 00:42:50.719784 Dram Type= 6, Freq= 0, CH_0, rank 1
6018 00:42:50.723152 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6019 00:42:50.723594 ==
6020 00:42:50.729986 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6021 00:42:50.736483 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6022 00:42:50.737019 [CA 0] Center 36 (8~64) winsize 57
6023 00:42:50.739929 [CA 1] Center 36 (8~64) winsize 57
6024 00:42:50.742894 [CA 2] Center 36 (8~64) winsize 57
6025 00:42:50.746284 [CA 3] Center 36 (8~64) winsize 57
6026 00:42:50.749599 [CA 4] Center 36 (8~64) winsize 57
6027 00:42:50.753311 [CA 5] Center 36 (8~64) winsize 57
6028 00:42:50.753750
6029 00:42:50.756419 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6030 00:42:50.756856
6031 00:42:50.759604 [CATrainingPosCal] consider 2 rank data
6032 00:42:50.762963 u2DelayCellTimex100 = 270/100 ps
6033 00:42:50.766395 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6034 00:42:50.772842 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6035 00:42:50.776209 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6036 00:42:50.779632 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6037 00:42:50.782932 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6038 00:42:50.786474 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6039 00:42:50.787026
6040 00:42:50.789163 CA PerBit enable=1, Macro0, CA PI delay=36
6041 00:42:50.789602
6042 00:42:50.792957 [CBTSetCACLKResult] CA Dly = 36
6043 00:42:50.793479 CS Dly: 1 (0~32)
6044 00:42:50.795888
6045 00:42:50.799187 ----->DramcWriteLeveling(PI) begin...
6046 00:42:50.799706 ==
6047 00:42:50.802558 Dram Type= 6, Freq= 0, CH_0, rank 0
6048 00:42:50.805701 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6049 00:42:50.806145 ==
6050 00:42:50.809205 Write leveling (Byte 0): 32 => 0
6051 00:42:50.812395 Write leveling (Byte 1): 32 => 0
6052 00:42:50.815765 DramcWriteLeveling(PI) end<-----
6053 00:42:50.816202
6054 00:42:50.816547 ==
6055 00:42:50.819066 Dram Type= 6, Freq= 0, CH_0, rank 0
6056 00:42:50.822666 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6057 00:42:50.823109 ==
6058 00:42:50.825717 [Gating] SW mode calibration
6059 00:42:50.832668 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6060 00:42:50.839167 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6061 00:42:50.842545 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6062 00:42:50.845673 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6063 00:42:50.852172 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6064 00:42:50.855363 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6065 00:42:50.858884 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6066 00:42:50.865694 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6067 00:42:50.868979 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6068 00:42:50.871997 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6069 00:42:50.878678 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6070 00:42:50.879221 Total UI for P1: 0, mck2ui 16
6071 00:42:50.882130 best dqsien dly found for B0: ( 0, 10, 16)
6072 00:42:50.885475 Total UI for P1: 0, mck2ui 16
6073 00:42:50.888776 best dqsien dly found for B1: ( 0, 10, 16)
6074 00:42:50.892263 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6075 00:42:50.899194 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6076 00:42:50.899711
6077 00:42:50.902047 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6078 00:42:50.905441 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6079 00:42:50.908408 [Gating] SW calibration Done
6080 00:42:50.908852 ==
6081 00:42:50.911699 Dram Type= 6, Freq= 0, CH_0, rank 0
6082 00:42:50.915194 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6083 00:42:50.915665 ==
6084 00:42:50.918546 RX Vref Scan: 0
6085 00:42:50.918975
6086 00:42:50.919313 RX Vref 0 -> 0, step: 1
6087 00:42:50.919630
6088 00:42:50.921802 RX Delay -410 -> 252, step: 16
6089 00:42:50.928456 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6090 00:42:50.931724 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6091 00:42:50.935129 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6092 00:42:50.938624 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6093 00:42:50.944949 iDelay=230, Bit 4, Center -35 (-298 ~ 229) 528
6094 00:42:50.948417 iDelay=230, Bit 5, Center -51 (-298 ~ 197) 496
6095 00:42:50.951650 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6096 00:42:50.954789 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6097 00:42:50.958306 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6098 00:42:50.964936 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6099 00:42:50.968303 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6100 00:42:50.971481 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6101 00:42:50.978340 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6102 00:42:50.981806 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6103 00:42:50.985160 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6104 00:42:50.988041 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6105 00:42:50.988478 ==
6106 00:42:50.991644 Dram Type= 6, Freq= 0, CH_0, rank 0
6107 00:42:50.998279 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6108 00:42:50.998805 ==
6109 00:42:50.999148 DQS Delay:
6110 00:42:51.001464 DQS0 = 51, DQS1 = 59
6111 00:42:51.001895 DQM Delay:
6112 00:42:51.004718 DQM0 = 12, DQM1 = 11
6113 00:42:51.005155 DQ Delay:
6114 00:42:51.008017 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6115 00:42:51.011368 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6116 00:42:51.015257 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6117 00:42:51.018405 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6118 00:42:51.018980
6119 00:42:51.019334
6120 00:42:51.019647 ==
6121 00:42:51.021371 Dram Type= 6, Freq= 0, CH_0, rank 0
6122 00:42:51.024736 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6123 00:42:51.025256 ==
6124 00:42:51.025602
6125 00:42:51.025918
6126 00:42:51.028212 TX Vref Scan disable
6127 00:42:51.028821 == TX Byte 0 ==
6128 00:42:51.034760 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6129 00:42:51.038078 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6130 00:42:51.038627 == TX Byte 1 ==
6131 00:42:51.044510 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6132 00:42:51.048209 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6133 00:42:51.048736 ==
6134 00:42:51.051117 Dram Type= 6, Freq= 0, CH_0, rank 0
6135 00:42:51.054579 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6136 00:42:51.055100 ==
6137 00:42:51.055441
6138 00:42:51.055756
6139 00:42:51.057804 TX Vref Scan disable
6140 00:42:51.058286 == TX Byte 0 ==
6141 00:42:51.064140 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6142 00:42:51.067745 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6143 00:42:51.068262 == TX Byte 1 ==
6144 00:42:51.074464 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6145 00:42:51.077762 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6146 00:42:51.078337
6147 00:42:51.078697 [DATLAT]
6148 00:42:51.080732 Freq=400, CH0 RK0
6149 00:42:51.081166
6150 00:42:51.081506 DATLAT Default: 0xf
6151 00:42:51.084227 0, 0xFFFF, sum = 0
6152 00:42:51.084857 1, 0xFFFF, sum = 0
6153 00:42:51.087491 2, 0xFFFF, sum = 0
6154 00:42:51.090714 3, 0xFFFF, sum = 0
6155 00:42:51.091161 4, 0xFFFF, sum = 0
6156 00:42:51.094063 5, 0xFFFF, sum = 0
6157 00:42:51.094535 6, 0xFFFF, sum = 0
6158 00:42:51.097329 7, 0xFFFF, sum = 0
6159 00:42:51.097768 8, 0xFFFF, sum = 0
6160 00:42:51.100916 9, 0xFFFF, sum = 0
6161 00:42:51.101362 10, 0xFFFF, sum = 0
6162 00:42:51.104145 11, 0xFFFF, sum = 0
6163 00:42:51.104874 12, 0x0, sum = 1
6164 00:42:51.107305 13, 0x0, sum = 2
6165 00:42:51.107789 14, 0x0, sum = 3
6166 00:42:51.110909 15, 0x0, sum = 4
6167 00:42:51.111408 best_step = 13
6168 00:42:51.111763
6169 00:42:51.112079 ==
6170 00:42:51.113931 Dram Type= 6, Freq= 0, CH_0, rank 0
6171 00:42:51.117441 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6172 00:42:51.118003 ==
6173 00:42:51.121088 RX Vref Scan: 1
6174 00:42:51.121602
6175 00:42:51.123916 RX Vref 0 -> 0, step: 1
6176 00:42:51.124376
6177 00:42:51.124721 RX Delay -359 -> 252, step: 8
6178 00:42:51.127819
6179 00:42:51.128332 Set Vref, RX VrefLevel [Byte0]: 46
6180 00:42:51.130535 [Byte1]: 49
6181 00:42:51.136469
6182 00:42:51.136980 Final RX Vref Byte 0 = 46 to rank0
6183 00:42:51.139636 Final RX Vref Byte 1 = 49 to rank0
6184 00:42:51.143166 Final RX Vref Byte 0 = 46 to rank1
6185 00:42:51.146295 Final RX Vref Byte 1 = 49 to rank1==
6186 00:42:51.149760 Dram Type= 6, Freq= 0, CH_0, rank 0
6187 00:42:51.156088 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6188 00:42:51.156534 ==
6189 00:42:51.156882 DQS Delay:
6190 00:42:51.159407 DQS0 = 52, DQS1 = 68
6191 00:42:51.159844 DQM Delay:
6192 00:42:51.160233 DQM0 = 8, DQM1 = 17
6193 00:42:51.162877 DQ Delay:
6194 00:42:51.166153 DQ0 =4, DQ1 =8, DQ2 =4, DQ3 =4
6195 00:42:51.166711 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =20
6196 00:42:51.169380 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6197 00:42:51.172953 DQ12 =24, DQ13 =24, DQ14 =28, DQ15 =28
6198 00:42:51.173392
6199 00:42:51.175918
6200 00:42:51.182290 [DQSOSCAuto] RK0, (LSB)MR18= 0xb7b7, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 387 ps
6201 00:42:51.185921 CH0 RK0: MR19=C0C, MR18=B7B7
6202 00:42:51.192913 CH0_RK0: MR19=0xC0C, MR18=0xB7B7, DQSOSC=387, MR23=63, INC=394, DEC=262
6203 00:42:51.193432 ==
6204 00:42:51.195952 Dram Type= 6, Freq= 0, CH_0, rank 1
6205 00:42:51.198992 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6206 00:42:51.199434 ==
6207 00:42:51.202564 [Gating] SW mode calibration
6208 00:42:51.209041 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6209 00:42:51.215679 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6210 00:42:51.219061 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6211 00:42:51.222054 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6212 00:42:51.225575 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6213 00:42:51.232326 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
6214 00:42:51.235720 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6215 00:42:51.239195 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6216 00:42:51.245657 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6217 00:42:51.249353 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6218 00:42:51.252105 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6219 00:42:51.255677 Total UI for P1: 0, mck2ui 16
6220 00:42:51.259088 best dqsien dly found for B0: ( 0, 10, 16)
6221 00:42:51.262146 Total UI for P1: 0, mck2ui 16
6222 00:42:51.265534 best dqsien dly found for B1: ( 0, 10, 16)
6223 00:42:51.269247 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6224 00:42:51.275758 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6225 00:42:51.276212
6226 00:42:51.278914 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6227 00:42:51.282126 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6228 00:42:51.285816 [Gating] SW calibration Done
6229 00:42:51.286393 ==
6230 00:42:51.288723 Dram Type= 6, Freq= 0, CH_0, rank 1
6231 00:42:51.291984 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6232 00:42:51.292435 ==
6233 00:42:51.295259 RX Vref Scan: 0
6234 00:42:51.295693
6235 00:42:51.296030 RX Vref 0 -> 0, step: 1
6236 00:42:51.296346
6237 00:42:51.298782 RX Delay -410 -> 252, step: 16
6238 00:42:51.302087 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6239 00:42:51.308735 iDelay=230, Bit 1, Center -35 (-298 ~ 229) 528
6240 00:42:51.311896 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6241 00:42:51.315174 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6242 00:42:51.318237 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6243 00:42:51.325055 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6244 00:42:51.328456 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6245 00:42:51.331616 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6246 00:42:51.334799 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6247 00:42:51.342274 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6248 00:42:51.345024 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6249 00:42:51.348496 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6250 00:42:51.355231 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6251 00:42:51.358103 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6252 00:42:51.361552 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6253 00:42:51.364812 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6254 00:42:51.365365 ==
6255 00:42:51.368058 Dram Type= 6, Freq= 0, CH_0, rank 1
6256 00:42:51.374827 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6257 00:42:51.375411 ==
6258 00:42:51.375765 DQS Delay:
6259 00:42:51.377840 DQS0 = 43, DQS1 = 59
6260 00:42:51.378319 DQM Delay:
6261 00:42:51.381302 DQM0 = 7, DQM1 = 15
6262 00:42:51.381748 DQ Delay:
6263 00:42:51.385216 DQ0 =0, DQ1 =8, DQ2 =0, DQ3 =0
6264 00:42:51.388051 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6265 00:42:51.388487 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6266 00:42:51.394484 DQ12 =24, DQ13 =16, DQ14 =24, DQ15 =24
6267 00:42:51.394983
6268 00:42:51.395318
6269 00:42:51.395714 ==
6270 00:42:51.397844 Dram Type= 6, Freq= 0, CH_0, rank 1
6271 00:42:51.401283 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6272 00:42:51.401845 ==
6273 00:42:51.402191
6274 00:42:51.402563
6275 00:42:51.404277 TX Vref Scan disable
6276 00:42:51.404710 == TX Byte 0 ==
6277 00:42:51.407962 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6278 00:42:51.414709 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6279 00:42:51.415144 == TX Byte 1 ==
6280 00:42:51.417856 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6281 00:42:51.424232 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6282 00:42:51.424734 ==
6283 00:42:51.428080 Dram Type= 6, Freq= 0, CH_0, rank 1
6284 00:42:51.430811 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6285 00:42:51.431250 ==
6286 00:42:51.431591
6287 00:42:51.431903
6288 00:42:51.434672 TX Vref Scan disable
6289 00:42:51.435115 == TX Byte 0 ==
6290 00:42:51.440889 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6291 00:42:51.444139 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6292 00:42:51.444665 == TX Byte 1 ==
6293 00:42:51.450555 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6294 00:42:51.454083 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6295 00:42:51.454635
6296 00:42:51.454972 [DATLAT]
6297 00:42:51.457349 Freq=400, CH0 RK1
6298 00:42:51.457774
6299 00:42:51.458101 DATLAT Default: 0xd
6300 00:42:51.460466 0, 0xFFFF, sum = 0
6301 00:42:51.460906 1, 0xFFFF, sum = 0
6302 00:42:51.463845 2, 0xFFFF, sum = 0
6303 00:42:51.464145 3, 0xFFFF, sum = 0
6304 00:42:51.467170 4, 0xFFFF, sum = 0
6305 00:42:51.467498 5, 0xFFFF, sum = 0
6306 00:42:51.470481 6, 0xFFFF, sum = 0
6307 00:42:51.470710 7, 0xFFFF, sum = 0
6308 00:42:51.473675 8, 0xFFFF, sum = 0
6309 00:42:51.473856 9, 0xFFFF, sum = 0
6310 00:42:51.477135 10, 0xFFFF, sum = 0
6311 00:42:51.480088 11, 0xFFFF, sum = 0
6312 00:42:51.480344 12, 0x0, sum = 1
6313 00:42:51.480522 13, 0x0, sum = 2
6314 00:42:51.484055 14, 0x0, sum = 3
6315 00:42:51.484237 15, 0x0, sum = 4
6316 00:42:51.486799 best_step = 13
6317 00:42:51.487038
6318 00:42:51.487178 ==
6319 00:42:51.490005 Dram Type= 6, Freq= 0, CH_0, rank 1
6320 00:42:51.493456 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6321 00:42:51.493635 ==
6322 00:42:51.496718 RX Vref Scan: 0
6323 00:42:51.496894
6324 00:42:51.497029 RX Vref 0 -> 0, step: 1
6325 00:42:51.497158
6326 00:42:51.499865 RX Delay -359 -> 252, step: 8
6327 00:42:51.508101 iDelay=217, Bit 0, Center -48 (-295 ~ 200) 496
6328 00:42:51.511541 iDelay=217, Bit 1, Center -40 (-295 ~ 216) 512
6329 00:42:51.514982 iDelay=217, Bit 2, Center -44 (-295 ~ 208) 504
6330 00:42:51.518133 iDelay=217, Bit 3, Center -44 (-287 ~ 200) 488
6331 00:42:51.524984 iDelay=217, Bit 4, Center -40 (-287 ~ 208) 496
6332 00:42:51.528196 iDelay=217, Bit 5, Center -52 (-303 ~ 200) 504
6333 00:42:51.531832 iDelay=217, Bit 6, Center -32 (-279 ~ 216) 496
6334 00:42:51.535128 iDelay=217, Bit 7, Center -32 (-279 ~ 216) 496
6335 00:42:51.541651 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6336 00:42:51.545176 iDelay=217, Bit 9, Center -64 (-311 ~ 184) 496
6337 00:42:51.548777 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6338 00:42:51.555327 iDelay=217, Bit 11, Center -60 (-303 ~ 184) 488
6339 00:42:51.557962 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6340 00:42:51.561695 iDelay=217, Bit 13, Center -44 (-295 ~ 208) 504
6341 00:42:51.564807 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6342 00:42:51.571725 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6343 00:42:51.572235 ==
6344 00:42:51.574778 Dram Type= 6, Freq= 0, CH_0, rank 1
6345 00:42:51.577933 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6346 00:42:51.578402 ==
6347 00:42:51.578740 DQS Delay:
6348 00:42:51.581413 DQS0 = 52, DQS1 = 64
6349 00:42:51.581836 DQM Delay:
6350 00:42:51.584872 DQM0 = 10, DQM1 = 14
6351 00:42:51.585387 DQ Delay:
6352 00:42:51.588041 DQ0 =4, DQ1 =12, DQ2 =8, DQ3 =8
6353 00:42:51.591531 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6354 00:42:51.594852 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =4
6355 00:42:51.598163 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =24
6356 00:42:51.598637
6357 00:42:51.598975
6358 00:42:51.604320 [DQSOSCAuto] RK1, (LSB)MR18= 0xd1d1, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 384 ps
6359 00:42:51.607836 CH0 RK1: MR19=C0C, MR18=D1D1
6360 00:42:51.614374 CH0_RK1: MR19=0xC0C, MR18=0xD1D1, DQSOSC=384, MR23=63, INC=400, DEC=267
6361 00:42:51.617909 [RxdqsGatingPostProcess] freq 400
6362 00:42:51.624373 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6363 00:42:51.627415 Pre-setting of DQS Precalculation
6364 00:42:51.630766 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6365 00:42:51.631197 ==
6366 00:42:51.634049 Dram Type= 6, Freq= 0, CH_1, rank 0
6367 00:42:51.637418 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6368 00:42:51.640898 ==
6369 00:42:51.644319 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6370 00:42:51.650917 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
6371 00:42:51.653956 [CA 0] Center 36 (8~64) winsize 57
6372 00:42:51.657345 [CA 1] Center 36 (8~64) winsize 57
6373 00:42:51.660380 [CA 2] Center 36 (8~64) winsize 57
6374 00:42:51.663701 [CA 3] Center 36 (8~64) winsize 57
6375 00:42:51.667016 [CA 4] Center 36 (8~64) winsize 57
6376 00:42:51.670465 [CA 5] Center 36 (8~64) winsize 57
6377 00:42:51.670895
6378 00:42:51.673525 [CmdBusTrainingLP45] Vref(ca) range 1: 39
6379 00:42:51.673953
6380 00:42:51.676794 [CATrainingPosCal] consider 1 rank data
6381 00:42:51.680290 u2DelayCellTimex100 = 270/100 ps
6382 00:42:51.683623 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6383 00:42:51.686876 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6384 00:42:51.690572 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6385 00:42:51.693367 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6386 00:42:51.696630 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6387 00:42:51.700220 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6388 00:42:51.700647
6389 00:42:51.706334 CA PerBit enable=1, Macro0, CA PI delay=36
6390 00:42:51.706727
6391 00:42:51.709774 [CBTSetCACLKResult] CA Dly = 36
6392 00:42:51.710164 CS Dly: 1 (0~32)
6393 00:42:51.710518 ==
6394 00:42:51.712891 Dram Type= 6, Freq= 0, CH_1, rank 1
6395 00:42:51.716396 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6396 00:42:51.716791 ==
6397 00:42:51.722991 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6398 00:42:51.729933 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6399 00:42:51.732772 [CA 0] Center 36 (8~64) winsize 57
6400 00:42:51.736434 [CA 1] Center 36 (8~64) winsize 57
6401 00:42:51.739300 [CA 2] Center 36 (8~64) winsize 57
6402 00:42:51.742894 [CA 3] Center 36 (8~64) winsize 57
6403 00:42:51.746253 [CA 4] Center 36 (8~64) winsize 57
6404 00:42:51.746655 [CA 5] Center 36 (8~64) winsize 57
6405 00:42:51.749437
6406 00:42:51.753274 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6407 00:42:51.753773
6408 00:42:51.756228 [CATrainingPosCal] consider 2 rank data
6409 00:42:51.759304 u2DelayCellTimex100 = 270/100 ps
6410 00:42:51.762653 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6411 00:42:51.766045 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6412 00:42:51.769494 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6413 00:42:51.772602 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6414 00:42:51.775916 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6415 00:42:51.779525 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6416 00:42:51.780187
6417 00:42:51.782402 CA PerBit enable=1, Macro0, CA PI delay=36
6418 00:42:51.782797
6419 00:42:51.785716 [CBTSetCACLKResult] CA Dly = 36
6420 00:42:51.789732 CS Dly: 1 (0~32)
6421 00:42:51.790126
6422 00:42:51.792698 ----->DramcWriteLeveling(PI) begin...
6423 00:42:51.793095 ==
6424 00:42:51.795830 Dram Type= 6, Freq= 0, CH_1, rank 0
6425 00:42:51.799316 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6426 00:42:51.799782 ==
6427 00:42:51.802391 Write leveling (Byte 0): 32 => 0
6428 00:42:51.805773 Write leveling (Byte 1): 32 => 0
6429 00:42:51.809344 DramcWriteLeveling(PI) end<-----
6430 00:42:51.809878
6431 00:42:51.810367 ==
6432 00:42:51.812692 Dram Type= 6, Freq= 0, CH_1, rank 0
6433 00:42:51.815872 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6434 00:42:51.816359 ==
6435 00:42:51.819041 [Gating] SW mode calibration
6436 00:42:51.825343 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6437 00:42:51.832130 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6438 00:42:51.836042 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6439 00:42:51.842422 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6440 00:42:51.845869 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6441 00:42:51.848795 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6442 00:42:51.855864 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6443 00:42:51.858838 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6444 00:42:51.862308 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6445 00:42:51.865351 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6446 00:42:51.872005 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6447 00:42:51.875637 Total UI for P1: 0, mck2ui 16
6448 00:42:51.878522 best dqsien dly found for B0: ( 0, 10, 16)
6449 00:42:51.882176 Total UI for P1: 0, mck2ui 16
6450 00:42:51.885362 best dqsien dly found for B1: ( 0, 10, 16)
6451 00:42:51.889136 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6452 00:42:51.892107 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6453 00:42:51.892628
6454 00:42:51.895727 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6455 00:42:51.898793 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6456 00:42:51.902190 [Gating] SW calibration Done
6457 00:42:51.902746 ==
6458 00:42:51.905694 Dram Type= 6, Freq= 0, CH_1, rank 0
6459 00:42:51.908450 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6460 00:42:51.908891 ==
6461 00:42:51.912063 RX Vref Scan: 0
6462 00:42:51.912499
6463 00:42:51.915165 RX Vref 0 -> 0, step: 1
6464 00:42:51.915600
6465 00:42:51.918691 RX Delay -410 -> 252, step: 16
6466 00:42:51.921890 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6467 00:42:51.925358 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6468 00:42:51.928534 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6469 00:42:51.935092 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6470 00:42:51.938337 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6471 00:42:51.941769 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6472 00:42:51.945747 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6473 00:42:51.951980 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6474 00:42:51.954926 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6475 00:42:51.958548 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6476 00:42:51.961430 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6477 00:42:51.968314 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6478 00:42:51.971311 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6479 00:42:51.974911 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6480 00:42:51.978272 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6481 00:42:51.984866 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6482 00:42:51.985406 ==
6483 00:42:51.988430 Dram Type= 6, Freq= 0, CH_1, rank 0
6484 00:42:51.991209 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6485 00:42:51.991653 ==
6486 00:42:51.992001 DQS Delay:
6487 00:42:51.994859 DQS0 = 43, DQS1 = 59
6488 00:42:51.995296 DQM Delay:
6489 00:42:51.997971 DQM0 = 6, DQM1 = 15
6490 00:42:51.998506 DQ Delay:
6491 00:42:52.001200 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0
6492 00:42:52.004723 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6493 00:42:52.007923 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6494 00:42:52.011161 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =32
6495 00:42:52.011655
6496 00:42:52.012013
6497 00:42:52.012328 ==
6498 00:42:52.014143 Dram Type= 6, Freq= 0, CH_1, rank 0
6499 00:42:52.018048 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6500 00:42:52.018624 ==
6501 00:42:52.021160
6502 00:42:52.021692
6503 00:42:52.022038 TX Vref Scan disable
6504 00:42:52.024356 == TX Byte 0 ==
6505 00:42:52.027734 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6506 00:42:52.031112 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6507 00:42:52.034420 == TX Byte 1 ==
6508 00:42:52.037797 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6509 00:42:52.040739 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6510 00:42:52.041179 ==
6511 00:42:52.044230 Dram Type= 6, Freq= 0, CH_1, rank 0
6512 00:42:52.050873 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6513 00:42:52.051400 ==
6514 00:42:52.051827
6515 00:42:52.052165
6516 00:42:52.052471 TX Vref Scan disable
6517 00:42:52.053923 == TX Byte 0 ==
6518 00:42:52.057314 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6519 00:42:52.060902 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6520 00:42:52.063923 == TX Byte 1 ==
6521 00:42:52.067233 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6522 00:42:52.070430 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6523 00:42:52.070871
6524 00:42:52.074146 [DATLAT]
6525 00:42:52.074720 Freq=400, CH1 RK0
6526 00:42:52.075069
6527 00:42:52.077231 DATLAT Default: 0xf
6528 00:42:52.077706 0, 0xFFFF, sum = 0
6529 00:42:52.080579 1, 0xFFFF, sum = 0
6530 00:42:52.081100 2, 0xFFFF, sum = 0
6531 00:42:52.084074 3, 0xFFFF, sum = 0
6532 00:42:52.084521 4, 0xFFFF, sum = 0
6533 00:42:52.087315 5, 0xFFFF, sum = 0
6534 00:42:52.087949 6, 0xFFFF, sum = 0
6535 00:42:52.090473 7, 0xFFFF, sum = 0
6536 00:42:52.090921 8, 0xFFFF, sum = 0
6537 00:42:52.093818 9, 0xFFFF, sum = 0
6538 00:42:52.097509 10, 0xFFFF, sum = 0
6539 00:42:52.097958 11, 0xFFFF, sum = 0
6540 00:42:52.100583 12, 0x0, sum = 1
6541 00:42:52.101110 13, 0x0, sum = 2
6542 00:42:52.101459 14, 0x0, sum = 3
6543 00:42:52.103717 15, 0x0, sum = 4
6544 00:42:52.104165 best_step = 13
6545 00:42:52.104510
6546 00:42:52.106883 ==
6547 00:42:52.110113 Dram Type= 6, Freq= 0, CH_1, rank 0
6548 00:42:52.113530 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6549 00:42:52.113972 ==
6550 00:42:52.114359 RX Vref Scan: 1
6551 00:42:52.114686
6552 00:42:52.117006 RX Vref 0 -> 0, step: 1
6553 00:42:52.117444
6554 00:42:52.120845 RX Delay -359 -> 252, step: 8
6555 00:42:52.121369
6556 00:42:52.123684 Set Vref, RX VrefLevel [Byte0]: 52
6557 00:42:52.126893 [Byte1]: 49
6558 00:42:52.130396
6559 00:42:52.130835 Final RX Vref Byte 0 = 52 to rank0
6560 00:42:52.133794 Final RX Vref Byte 1 = 49 to rank0
6561 00:42:52.137162 Final RX Vref Byte 0 = 52 to rank1
6562 00:42:52.140995 Final RX Vref Byte 1 = 49 to rank1==
6563 00:42:52.144165 Dram Type= 6, Freq= 0, CH_1, rank 0
6564 00:42:52.150531 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6565 00:42:52.151048 ==
6566 00:42:52.151392 DQS Delay:
6567 00:42:52.153675 DQS0 = 48, DQS1 = 64
6568 00:42:52.154114 DQM Delay:
6569 00:42:52.154498 DQM0 = 9, DQM1 = 16
6570 00:42:52.156818 DQ Delay:
6571 00:42:52.160540 DQ0 =8, DQ1 =4, DQ2 =0, DQ3 =8
6572 00:42:52.161080 DQ4 =8, DQ5 =20, DQ6 =16, DQ7 =8
6573 00:42:52.163847 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6574 00:42:52.167063 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6575 00:42:52.167495
6576 00:42:52.167830
6577 00:42:52.177026 [DQSOSCAuto] RK0, (LSB)MR18= 0xdcdc, (MSB)MR19= 0xc0c, tDQSOscB0 = 382 ps tDQSOscB1 = 382 ps
6578 00:42:52.180308 CH1 RK0: MR19=C0C, MR18=DCDC
6579 00:42:52.186589 CH1_RK0: MR19=0xC0C, MR18=0xDCDC, DQSOSC=382, MR23=63, INC=404, DEC=269
6580 00:42:52.187023 ==
6581 00:42:52.190341 Dram Type= 6, Freq= 0, CH_1, rank 1
6582 00:42:52.193627 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6583 00:42:52.194148 ==
6584 00:42:52.196796 [Gating] SW mode calibration
6585 00:42:52.203215 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6586 00:42:52.209990 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6587 00:42:52.213266 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6588 00:42:52.216804 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6589 00:42:52.219754 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6590 00:42:52.226612 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6591 00:42:52.230013 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6592 00:42:52.233270 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6593 00:42:52.240071 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6594 00:42:52.242909 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6595 00:42:52.246502 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6596 00:42:52.249867 Total UI for P1: 0, mck2ui 16
6597 00:42:52.253020 best dqsien dly found for B0: ( 0, 10, 16)
6598 00:42:52.256964 Total UI for P1: 0, mck2ui 16
6599 00:42:52.259619 best dqsien dly found for B1: ( 0, 10, 16)
6600 00:42:52.262802 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6601 00:42:52.269975 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6602 00:42:52.270527
6603 00:42:52.272817 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6604 00:42:52.276382 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6605 00:42:52.279640 [Gating] SW calibration Done
6606 00:42:52.280074 ==
6607 00:42:52.283124 Dram Type= 6, Freq= 0, CH_1, rank 1
6608 00:42:52.286189 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6609 00:42:52.286654 ==
6610 00:42:52.289799 RX Vref Scan: 0
6611 00:42:52.290368
6612 00:42:52.290722 RX Vref 0 -> 0, step: 1
6613 00:42:52.291042
6614 00:42:52.293062 RX Delay -410 -> 252, step: 16
6615 00:42:52.296098 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6616 00:42:52.302829 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6617 00:42:52.306122 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6618 00:42:52.309518 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6619 00:42:52.312647 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6620 00:42:52.319296 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6621 00:42:52.323050 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6622 00:42:52.325867 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6623 00:42:52.329438 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6624 00:42:52.336265 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6625 00:42:52.339437 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6626 00:42:52.342730 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6627 00:42:52.345870 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6628 00:42:52.352528 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6629 00:42:52.355693 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6630 00:42:52.359356 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6631 00:42:52.359874 ==
6632 00:42:52.362483 Dram Type= 6, Freq= 0, CH_1, rank 1
6633 00:42:52.369355 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6634 00:42:52.369876 ==
6635 00:42:52.370263 DQS Delay:
6636 00:42:52.372560 DQS0 = 35, DQS1 = 59
6637 00:42:52.373212 DQM Delay:
6638 00:42:52.373576 DQM0 = 3, DQM1 = 17
6639 00:42:52.375628 DQ Delay:
6640 00:42:52.378833 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6641 00:42:52.379506 DQ4 =0, DQ5 =16, DQ6 =8, DQ7 =0
6642 00:42:52.382272 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6643 00:42:52.385632 DQ12 =32, DQ13 =24, DQ14 =32, DQ15 =24
6644 00:42:52.386313
6645 00:42:52.386768
6646 00:42:52.389218 ==
6647 00:42:52.392483 Dram Type= 6, Freq= 0, CH_1, rank 1
6648 00:42:52.395563 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6649 00:42:52.396205 ==
6650 00:42:52.396802
6651 00:42:52.397343
6652 00:42:52.398902 TX Vref Scan disable
6653 00:42:52.399342 == TX Byte 0 ==
6654 00:42:52.402747 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6655 00:42:52.408950 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6656 00:42:52.409392 == TX Byte 1 ==
6657 00:42:52.412163 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6658 00:42:52.418706 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6659 00:42:52.419143 ==
6660 00:42:52.421998 Dram Type= 6, Freq= 0, CH_1, rank 1
6661 00:42:52.425738 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6662 00:42:52.426284 ==
6663 00:42:52.426623
6664 00:42:52.426909
6665 00:42:52.428875 TX Vref Scan disable
6666 00:42:52.429273 == TX Byte 0 ==
6667 00:42:52.431902 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6668 00:42:52.438931 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6669 00:42:52.439393 == TX Byte 1 ==
6670 00:42:52.442095 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6671 00:42:52.448748 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6672 00:42:52.449208
6673 00:42:52.449518 [DATLAT]
6674 00:42:52.449804 Freq=400, CH1 RK1
6675 00:42:52.450081
6676 00:42:52.451941 DATLAT Default: 0xd
6677 00:42:52.455432 0, 0xFFFF, sum = 0
6678 00:42:52.455919 1, 0xFFFF, sum = 0
6679 00:42:52.458600 2, 0xFFFF, sum = 0
6680 00:42:52.459045 3, 0xFFFF, sum = 0
6681 00:42:52.461775 4, 0xFFFF, sum = 0
6682 00:42:52.462175 5, 0xFFFF, sum = 0
6683 00:42:52.465198 6, 0xFFFF, sum = 0
6684 00:42:52.465596 7, 0xFFFF, sum = 0
6685 00:42:52.468684 8, 0xFFFF, sum = 0
6686 00:42:52.469085 9, 0xFFFF, sum = 0
6687 00:42:52.471643 10, 0xFFFF, sum = 0
6688 00:42:52.472041 11, 0xFFFF, sum = 0
6689 00:42:52.475038 12, 0x0, sum = 1
6690 00:42:52.475437 13, 0x0, sum = 2
6691 00:42:52.478185 14, 0x0, sum = 3
6692 00:42:52.478619 15, 0x0, sum = 4
6693 00:42:52.481591 best_step = 13
6694 00:42:52.481981
6695 00:42:52.482316 ==
6696 00:42:52.485295 Dram Type= 6, Freq= 0, CH_1, rank 1
6697 00:42:52.488613 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6698 00:42:52.489097 ==
6699 00:42:52.491856 RX Vref Scan: 0
6700 00:42:52.492250
6701 00:42:52.492556 RX Vref 0 -> 0, step: 1
6702 00:42:52.492844
6703 00:42:52.494727 RX Delay -359 -> 252, step: 8
6704 00:42:52.502553 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6705 00:42:52.506306 iDelay=217, Bit 1, Center -44 (-287 ~ 200) 488
6706 00:42:52.509544 iDelay=217, Bit 2, Center -44 (-287 ~ 200) 488
6707 00:42:52.512488 iDelay=217, Bit 3, Center -44 (-287 ~ 200) 488
6708 00:42:52.519157 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6709 00:42:52.522525 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6710 00:42:52.526158 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6711 00:42:52.529277 iDelay=217, Bit 7, Center -44 (-287 ~ 200) 488
6712 00:42:52.535862 iDelay=217, Bit 8, Center -64 (-311 ~ 184) 496
6713 00:42:52.539613 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6714 00:42:52.542804 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6715 00:42:52.546149 iDelay=217, Bit 11, Center -56 (-303 ~ 192) 496
6716 00:42:52.552827 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6717 00:42:52.555848 iDelay=217, Bit 13, Center -36 (-279 ~ 208) 488
6718 00:42:52.559251 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6719 00:42:52.565554 iDelay=217, Bit 15, Center -44 (-287 ~ 200) 488
6720 00:42:52.566005 ==
6721 00:42:52.569145 Dram Type= 6, Freq= 0, CH_1, rank 1
6722 00:42:52.572438 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6723 00:42:52.573130 ==
6724 00:42:52.573671 DQS Delay:
6725 00:42:52.576028 DQS0 = 44, DQS1 = 64
6726 00:42:52.576468 DQM Delay:
6727 00:42:52.578797 DQM0 = 6, DQM1 = 15
6728 00:42:52.579235 DQ Delay:
6729 00:42:52.582461 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =0
6730 00:42:52.585611 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =0
6731 00:42:52.588539 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6732 00:42:52.592728 DQ12 =24, DQ13 =28, DQ14 =24, DQ15 =20
6733 00:42:52.593247
6734 00:42:52.593592
6735 00:42:52.598868 [DQSOSCAuto] RK1, (LSB)MR18= 0xb3b3, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 387 ps
6736 00:42:52.602012 CH1 RK1: MR19=C0C, MR18=B3B3
6737 00:42:52.608687 CH1_RK1: MR19=0xC0C, MR18=0xB3B3, DQSOSC=387, MR23=63, INC=394, DEC=262
6738 00:42:52.611745 [RxdqsGatingPostProcess] freq 400
6739 00:42:52.618564 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6740 00:42:52.621621 Pre-setting of DQS Precalculation
6741 00:42:52.625323 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6742 00:42:52.632016 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6743 00:42:52.638688 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6744 00:42:52.639217
6745 00:42:52.639551
6746 00:42:52.641793 [Calibration Summary] 800 Mbps
6747 00:42:52.645039 CH 0, Rank 0
6748 00:42:52.645548 SW Impedance : PASS
6749 00:42:52.648676 DUTY Scan : NO K
6750 00:42:52.651925 ZQ Calibration : PASS
6751 00:42:52.652545 Jitter Meter : NO K
6752 00:42:52.654823 CBT Training : PASS
6753 00:42:52.655252 Write leveling : PASS
6754 00:42:52.658571 RX DQS gating : PASS
6755 00:42:52.661938 RX DQ/DQS(RDDQC) : PASS
6756 00:42:52.662602 TX DQ/DQS : PASS
6757 00:42:52.664915 RX DATLAT : PASS
6758 00:42:52.668444 RX DQ/DQS(Engine): PASS
6759 00:42:52.668977 TX OE : NO K
6760 00:42:52.671469 All Pass.
6761 00:42:52.671910
6762 00:42:52.672355 CH 0, Rank 1
6763 00:42:52.674929 SW Impedance : PASS
6764 00:42:52.675406 DUTY Scan : NO K
6765 00:42:52.677921 ZQ Calibration : PASS
6766 00:42:52.681705 Jitter Meter : NO K
6767 00:42:52.682304 CBT Training : PASS
6768 00:42:52.684836 Write leveling : NO K
6769 00:42:52.688585 RX DQS gating : PASS
6770 00:42:52.689105 RX DQ/DQS(RDDQC) : PASS
6771 00:42:52.691864 TX DQ/DQS : PASS
6772 00:42:52.694605 RX DATLAT : PASS
6773 00:42:52.695038 RX DQ/DQS(Engine): PASS
6774 00:42:52.698133 TX OE : NO K
6775 00:42:52.698606 All Pass.
6776 00:42:52.698943
6777 00:42:52.701409 CH 1, Rank 0
6778 00:42:52.702050 SW Impedance : PASS
6779 00:42:52.704539 DUTY Scan : NO K
6780 00:42:52.707941 ZQ Calibration : PASS
6781 00:42:52.708472 Jitter Meter : NO K
6782 00:42:52.711495 CBT Training : PASS
6783 00:42:52.714567 Write leveling : PASS
6784 00:42:52.715034 RX DQS gating : PASS
6785 00:42:52.717889 RX DQ/DQS(RDDQC) : PASS
6786 00:42:52.721156 TX DQ/DQS : PASS
6787 00:42:52.721674 RX DATLAT : PASS
6788 00:42:52.724785 RX DQ/DQS(Engine): PASS
6789 00:42:52.725305 TX OE : NO K
6790 00:42:52.727689 All Pass.
6791 00:42:52.728122
6792 00:42:52.728459 CH 1, Rank 1
6793 00:42:52.731077 SW Impedance : PASS
6794 00:42:52.731509 DUTY Scan : NO K
6795 00:42:52.734290 ZQ Calibration : PASS
6796 00:42:52.737877 Jitter Meter : NO K
6797 00:42:52.738445 CBT Training : PASS
6798 00:42:52.741370 Write leveling : NO K
6799 00:42:52.744416 RX DQS gating : PASS
6800 00:42:52.744926 RX DQ/DQS(RDDQC) : PASS
6801 00:42:52.747701 TX DQ/DQS : PASS
6802 00:42:52.751181 RX DATLAT : PASS
6803 00:42:52.751695 RX DQ/DQS(Engine): PASS
6804 00:42:52.754454 TX OE : NO K
6805 00:42:52.754977 All Pass.
6806 00:42:52.755318
6807 00:42:52.757923 DramC Write-DBI off
6808 00:42:52.760901 PER_BANK_REFRESH: Hybrid Mode
6809 00:42:52.761334 TX_TRACKING: ON
6810 00:42:52.770791 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
6811 00:42:52.774410 [FAST_K] Save calibration result to emmc
6812 00:42:52.777369 dramc_set_vcore_voltage set vcore to 725000
6813 00:42:52.780676 Read voltage for 1600, 0
6814 00:42:52.781109 Vio18 = 0
6815 00:42:52.781444 Vcore = 725000
6816 00:42:52.783938 Vdram = 0
6817 00:42:52.784363 Vddq = 0
6818 00:42:52.784697 Vmddr = 0
6819 00:42:52.790853 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
6820 00:42:52.794208 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6821 00:42:52.797566 MEM_TYPE=3, freq_sel=13
6822 00:42:52.801121 sv_algorithm_assistance_LP4_3733
6823 00:42:52.803888 ============ PULL DRAM RESETB DOWN ============
6824 00:42:52.807379 ========== PULL DRAM RESETB DOWN end =========
6825 00:42:52.813745 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6826 00:42:52.817006 ===================================
6827 00:42:52.820235 LPDDR4 DRAM CONFIGURATION
6828 00:42:52.823671 ===================================
6829 00:42:52.824107 EX_ROW_EN[0] = 0x0
6830 00:42:52.827466 EX_ROW_EN[1] = 0x0
6831 00:42:52.827895 LP4Y_EN = 0x0
6832 00:42:52.830512 WORK_FSP = 0x1
6833 00:42:52.830945 WL = 0x5
6834 00:42:52.833889 RL = 0x5
6835 00:42:52.834358 BL = 0x2
6836 00:42:52.837094 RPST = 0x0
6837 00:42:52.837521 RD_PRE = 0x0
6838 00:42:52.840583 WR_PRE = 0x1
6839 00:42:52.841095 WR_PST = 0x1
6840 00:42:52.843641 DBI_WR = 0x0
6841 00:42:52.844068 DBI_RD = 0x0
6842 00:42:52.847265 OTF = 0x1
6843 00:42:52.850404 ===================================
6844 00:42:52.853437 ===================================
6845 00:42:52.853867 ANA top config
6846 00:42:52.857498 ===================================
6847 00:42:52.860158 DLL_ASYNC_EN = 0
6848 00:42:52.863713 ALL_SLAVE_EN = 0
6849 00:42:52.866978 NEW_RANK_MODE = 1
6850 00:42:52.867415 DLL_IDLE_MODE = 1
6851 00:42:52.870252 LP45_APHY_COMB_EN = 1
6852 00:42:52.873621 TX_ODT_DIS = 0
6853 00:42:52.877167 NEW_8X_MODE = 1
6854 00:42:52.880284 ===================================
6855 00:42:52.883652 ===================================
6856 00:42:52.886871 data_rate = 3200
6857 00:42:52.890570 CKR = 1
6858 00:42:52.891102 DQ_P2S_RATIO = 8
6859 00:42:52.893860 ===================================
6860 00:42:52.896878 CA_P2S_RATIO = 8
6861 00:42:52.900531 DQ_CA_OPEN = 0
6862 00:42:52.903508 DQ_SEMI_OPEN = 0
6863 00:42:52.906891 CA_SEMI_OPEN = 0
6864 00:42:52.907326 CA_FULL_RATE = 0
6865 00:42:52.910310 DQ_CKDIV4_EN = 0
6866 00:42:52.913477 CA_CKDIV4_EN = 0
6867 00:42:52.916892 CA_PREDIV_EN = 0
6868 00:42:52.920421 PH8_DLY = 12
6869 00:42:52.923321 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
6870 00:42:52.923756 DQ_AAMCK_DIV = 4
6871 00:42:52.926860 CA_AAMCK_DIV = 4
6872 00:42:52.930091 CA_ADMCK_DIV = 4
6873 00:42:52.933992 DQ_TRACK_CA_EN = 0
6874 00:42:52.936835 CA_PICK = 1600
6875 00:42:52.940348 CA_MCKIO = 1600
6876 00:42:52.943185 MCKIO_SEMI = 0
6877 00:42:52.946492 PLL_FREQ = 3068
6878 00:42:52.946926 DQ_UI_PI_RATIO = 32
6879 00:42:52.949770 CA_UI_PI_RATIO = 0
6880 00:42:52.953730 ===================================
6881 00:42:52.956935 ===================================
6882 00:42:52.959975 memory_type:LPDDR4
6883 00:42:52.963241 GP_NUM : 10
6884 00:42:52.963673 SRAM_EN : 1
6885 00:42:52.966459 MD32_EN : 0
6886 00:42:52.969817 ===================================
6887 00:42:52.970309 [ANA_INIT] >>>>>>>>>>>>>>
6888 00:42:52.973061 <<<<<< [CONFIGURE PHASE]: ANA_TX
6889 00:42:52.976465 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6890 00:42:52.979881 ===================================
6891 00:42:52.983330 data_rate = 3200,PCW = 0X7600
6892 00:42:52.986723 ===================================
6893 00:42:52.990036 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6894 00:42:52.996568 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6895 00:42:53.002795 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6896 00:42:53.006268 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6897 00:42:53.009818 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6898 00:42:53.012940 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6899 00:42:53.016143 [ANA_INIT] flow start
6900 00:42:53.016562 [ANA_INIT] PLL >>>>>>>>
6901 00:42:53.019597 [ANA_INIT] PLL <<<<<<<<
6902 00:42:53.022687 [ANA_INIT] MIDPI >>>>>>>>
6903 00:42:53.023085 [ANA_INIT] MIDPI <<<<<<<<
6904 00:42:53.026312 [ANA_INIT] DLL >>>>>>>>
6905 00:42:53.029835 [ANA_INIT] DLL <<<<<<<<
6906 00:42:53.030267 [ANA_INIT] flow end
6907 00:42:53.036149 ============ LP4 DIFF to SE enter ============
6908 00:42:53.039579 ============ LP4 DIFF to SE exit ============
6909 00:42:53.042753 [ANA_INIT] <<<<<<<<<<<<<
6910 00:42:53.045903 [Flow] Enable top DCM control >>>>>
6911 00:42:53.049467 [Flow] Enable top DCM control <<<<<
6912 00:42:53.049864 Enable DLL master slave shuffle
6913 00:42:53.055839 ==============================================================
6914 00:42:53.059351 Gating Mode config
6915 00:42:53.062776 ==============================================================
6916 00:42:53.066026 Config description:
6917 00:42:53.075842 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6918 00:42:53.082865 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6919 00:42:53.085831 SELPH_MODE 0: By rank 1: By Phase
6920 00:42:53.092480 ==============================================================
6921 00:42:53.096040 GAT_TRACK_EN = 1
6922 00:42:53.098893 RX_GATING_MODE = 2
6923 00:42:53.102156 RX_GATING_TRACK_MODE = 2
6924 00:42:53.105663 SELPH_MODE = 1
6925 00:42:53.106113 PICG_EARLY_EN = 1
6926 00:42:53.108953 VALID_LAT_VALUE = 1
6927 00:42:53.115643 ==============================================================
6928 00:42:53.119232 Enter into Gating configuration >>>>
6929 00:42:53.122332 Exit from Gating configuration <<<<
6930 00:42:53.125485 Enter into DVFS_PRE_config >>>>>
6931 00:42:53.135859 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6932 00:42:53.138947 Exit from DVFS_PRE_config <<<<<
6933 00:42:53.142372 Enter into PICG configuration >>>>
6934 00:42:53.145488 Exit from PICG configuration <<<<
6935 00:42:53.148850 [RX_INPUT] configuration >>>>>
6936 00:42:53.152324 [RX_INPUT] configuration <<<<<
6937 00:42:53.155613 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6938 00:42:53.162457 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6939 00:42:53.168570 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6940 00:42:53.175116 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6941 00:42:53.181891 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6942 00:42:53.185214 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6943 00:42:53.191910 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6944 00:42:53.195263 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6945 00:42:53.198590 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6946 00:42:53.201676 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6947 00:42:53.208409 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6948 00:42:53.211649 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6949 00:42:53.214939 ===================================
6950 00:42:53.218158 LPDDR4 DRAM CONFIGURATION
6951 00:42:53.221706 ===================================
6952 00:42:53.221838 EX_ROW_EN[0] = 0x0
6953 00:42:53.224908 EX_ROW_EN[1] = 0x0
6954 00:42:53.225042 LP4Y_EN = 0x0
6955 00:42:53.228268 WORK_FSP = 0x1
6956 00:42:53.228398 WL = 0x5
6957 00:42:53.231400 RL = 0x5
6958 00:42:53.231531 BL = 0x2
6959 00:42:53.234800 RPST = 0x0
6960 00:42:53.234931 RD_PRE = 0x0
6961 00:42:53.238415 WR_PRE = 0x1
6962 00:42:53.241615 WR_PST = 0x1
6963 00:42:53.241745 DBI_WR = 0x0
6964 00:42:53.244903 DBI_RD = 0x0
6965 00:42:53.245035 OTF = 0x1
6966 00:42:53.248064 ===================================
6967 00:42:53.251288 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6968 00:42:53.254907 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6969 00:42:53.261647 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6970 00:42:53.264909 ===================================
6971 00:42:53.268486 LPDDR4 DRAM CONFIGURATION
6972 00:42:53.271498 ===================================
6973 00:42:53.271937 EX_ROW_EN[0] = 0x10
6974 00:42:53.274915 EX_ROW_EN[1] = 0x0
6975 00:42:53.275396 LP4Y_EN = 0x0
6976 00:42:53.278484 WORK_FSP = 0x1
6977 00:42:53.278888 WL = 0x5
6978 00:42:53.281401 RL = 0x5
6979 00:42:53.281737 BL = 0x2
6980 00:42:53.284986 RPST = 0x0
6981 00:42:53.285278 RD_PRE = 0x0
6982 00:42:53.288076 WR_PRE = 0x1
6983 00:42:53.288356 WR_PST = 0x1
6984 00:42:53.291176 DBI_WR = 0x0
6985 00:42:53.294680 DBI_RD = 0x0
6986 00:42:53.294852 OTF = 0x1
6987 00:42:53.297684 ===================================
6988 00:42:53.304477 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6989 00:42:53.304603 ==
6990 00:42:53.307995 Dram Type= 6, Freq= 0, CH_0, rank 0
6991 00:42:53.311121 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
6992 00:42:53.311247 ==
6993 00:42:53.314617 [Duty_Offset_Calibration]
6994 00:42:53.315018 B0:0 B1:2 CA:1
6995 00:42:53.315334
6996 00:42:53.317845 [DutyScan_Calibration_Flow] k_type=0
6997 00:42:53.329517
6998 00:42:53.330001 ==CLK 0==
6999 00:42:53.332550 Final CLK duty delay cell = 0
7000 00:42:53.336247 [0] MAX Duty = 5156%(X100), DQS PI = 22
7001 00:42:53.339809 [0] MIN Duty = 4938%(X100), DQS PI = 50
7002 00:42:53.342700 [0] AVG Duty = 5047%(X100)
7003 00:42:53.343097
7004 00:42:53.346286 CH0 CLK Duty spec in!! Max-Min= 218%
7005 00:42:53.349444 [DutyScan_Calibration_Flow] ====Done====
7006 00:42:53.349969
7007 00:42:53.352619 [DutyScan_Calibration_Flow] k_type=1
7008 00:42:53.369389
7009 00:42:53.369911 ==DQS 0 ==
7010 00:42:53.372674 Final DQS duty delay cell = 0
7011 00:42:53.375885 [0] MAX Duty = 5156%(X100), DQS PI = 34
7012 00:42:53.379399 [0] MIN Duty = 5031%(X100), DQS PI = 8
7013 00:42:53.379931 [0] AVG Duty = 5093%(X100)
7014 00:42:53.382496
7015 00:42:53.382928 ==DQS 1 ==
7016 00:42:53.386291 Final DQS duty delay cell = 0
7017 00:42:53.389538 [0] MAX Duty = 5031%(X100), DQS PI = 46
7018 00:42:53.392865 [0] MIN Duty = 4844%(X100), DQS PI = 18
7019 00:42:53.395874 [0] AVG Duty = 4937%(X100)
7020 00:42:53.396388
7021 00:42:53.398925 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7022 00:42:53.399354
7023 00:42:53.402451 CH0 DQS 1 Duty spec in!! Max-Min= 187%
7024 00:42:53.405730 [DutyScan_Calibration_Flow] ====Done====
7025 00:42:53.406160
7026 00:42:53.409149 [DutyScan_Calibration_Flow] k_type=3
7027 00:42:53.426844
7028 00:42:53.427345 ==DQM 0 ==
7029 00:42:53.429855 Final DQM duty delay cell = 0
7030 00:42:53.433281 [0] MAX Duty = 5187%(X100), DQS PI = 26
7031 00:42:53.436767 [0] MIN Duty = 4876%(X100), DQS PI = 56
7032 00:42:53.440108 [0] AVG Duty = 5031%(X100)
7033 00:42:53.440645
7034 00:42:53.441025 ==DQM 1 ==
7035 00:42:53.442998 Final DQM duty delay cell = 0
7036 00:42:53.446794 [0] MAX Duty = 5031%(X100), DQS PI = 52
7037 00:42:53.449644 [0] MIN Duty = 4782%(X100), DQS PI = 14
7038 00:42:53.452939 [0] AVG Duty = 4906%(X100)
7039 00:42:53.453447
7040 00:42:53.456546 CH0 DQM 0 Duty spec in!! Max-Min= 311%
7041 00:42:53.457082
7042 00:42:53.460106 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7043 00:42:53.462840 [DutyScan_Calibration_Flow] ====Done====
7044 00:42:53.463280
7045 00:42:53.466296 [DutyScan_Calibration_Flow] k_type=2
7046 00:42:53.483103
7047 00:42:53.483625 ==DQ 0 ==
7048 00:42:53.486172 Final DQ duty delay cell = 0
7049 00:42:53.489630 [0] MAX Duty = 5218%(X100), DQS PI = 18
7050 00:42:53.492989 [0] MIN Duty = 4938%(X100), DQS PI = 54
7051 00:42:53.493511 [0] AVG Duty = 5078%(X100)
7052 00:42:53.496210
7053 00:42:53.496726 ==DQ 1 ==
7054 00:42:53.499228 Final DQ duty delay cell = -4
7055 00:42:53.502766 [-4] MAX Duty = 5062%(X100), DQS PI = 4
7056 00:42:53.505868 [-4] MIN Duty = 4844%(X100), DQS PI = 34
7057 00:42:53.509738 [-4] AVG Duty = 4953%(X100)
7058 00:42:53.510313
7059 00:42:53.512748 CH0 DQ 0 Duty spec in!! Max-Min= 280%
7060 00:42:53.513270
7061 00:42:53.515802 CH0 DQ 1 Duty spec in!! Max-Min= 218%
7062 00:42:53.519159 [DutyScan_Calibration_Flow] ====Done====
7063 00:42:53.519596 ==
7064 00:42:53.522488 Dram Type= 6, Freq= 0, CH_1, rank 0
7065 00:42:53.525894 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7066 00:42:53.526474 ==
7067 00:42:53.529153 [Duty_Offset_Calibration]
7068 00:42:53.529588 B0:0 B1:5 CA:-5
7069 00:42:53.529929
7070 00:42:53.532676 [DutyScan_Calibration_Flow] k_type=0
7071 00:42:53.543513
7072 00:42:53.544033 ==CLK 0==
7073 00:42:53.546902 Final CLK duty delay cell = 0
7074 00:42:53.550277 [0] MAX Duty = 5156%(X100), DQS PI = 22
7075 00:42:53.553514 [0] MIN Duty = 4906%(X100), DQS PI = 50
7076 00:42:53.556586 [0] AVG Duty = 5031%(X100)
7077 00:42:53.557023
7078 00:42:53.560251 CH1 CLK Duty spec in!! Max-Min= 250%
7079 00:42:53.563393 [DutyScan_Calibration_Flow] ====Done====
7080 00:42:53.563917
7081 00:42:53.566562 [DutyScan_Calibration_Flow] k_type=1
7082 00:42:53.582527
7083 00:42:53.582960 ==DQS 0 ==
7084 00:42:53.585639 Final DQS duty delay cell = 0
7085 00:42:53.589159 [0] MAX Duty = 5156%(X100), DQS PI = 18
7086 00:42:53.592822 [0] MIN Duty = 4876%(X100), DQS PI = 42
7087 00:42:53.595605 [0] AVG Duty = 5016%(X100)
7088 00:42:53.596043
7089 00:42:53.596386 ==DQS 1 ==
7090 00:42:53.598961 Final DQS duty delay cell = -4
7091 00:42:53.602117 [-4] MAX Duty = 5000%(X100), DQS PI = 18
7092 00:42:53.605801 [-4] MIN Duty = 4844%(X100), DQS PI = 40
7093 00:42:53.609282 [-4] AVG Duty = 4922%(X100)
7094 00:42:53.609840
7095 00:42:53.612411 CH1 DQS 0 Duty spec in!! Max-Min= 280%
7096 00:42:53.612852
7097 00:42:53.615840 CH1 DQS 1 Duty spec in!! Max-Min= 156%
7098 00:42:53.618951 [DutyScan_Calibration_Flow] ====Done====
7099 00:42:53.619394
7100 00:42:53.622381 [DutyScan_Calibration_Flow] k_type=3
7101 00:42:53.638103
7102 00:42:53.638657 ==DQM 0 ==
7103 00:42:53.641582 Final DQM duty delay cell = -4
7104 00:42:53.644876 [-4] MAX Duty = 5093%(X100), DQS PI = 34
7105 00:42:53.647890 [-4] MIN Duty = 4782%(X100), DQS PI = 44
7106 00:42:53.651430 [-4] AVG Duty = 4937%(X100)
7107 00:42:53.651867
7108 00:42:53.652207 ==DQM 1 ==
7109 00:42:53.654933 Final DQM duty delay cell = -4
7110 00:42:53.658294 [-4] MAX Duty = 5031%(X100), DQS PI = 2
7111 00:42:53.661361 [-4] MIN Duty = 4876%(X100), DQS PI = 40
7112 00:42:53.664691 [-4] AVG Duty = 4953%(X100)
7113 00:42:53.665160
7114 00:42:53.667860 CH1 DQM 0 Duty spec in!! Max-Min= 311%
7115 00:42:53.668296
7116 00:42:53.671739 CH1 DQM 1 Duty spec in!! Max-Min= 155%
7117 00:42:53.674563 [DutyScan_Calibration_Flow] ====Done====
7118 00:42:53.675003
7119 00:42:53.678116 [DutyScan_Calibration_Flow] k_type=2
7120 00:42:53.695838
7121 00:42:53.696356 ==DQ 0 ==
7122 00:42:53.699021 Final DQ duty delay cell = 0
7123 00:42:53.702371 [0] MAX Duty = 5093%(X100), DQS PI = 2
7124 00:42:53.705453 [0] MIN Duty = 4938%(X100), DQS PI = 46
7125 00:42:53.705887 [0] AVG Duty = 5015%(X100)
7126 00:42:53.706274
7127 00:42:53.709129 ==DQ 1 ==
7128 00:42:53.712311 Final DQ duty delay cell = 0
7129 00:42:53.715349 [0] MAX Duty = 5062%(X100), DQS PI = 6
7130 00:42:53.718938 [0] MIN Duty = 4876%(X100), DQS PI = 26
7131 00:42:53.719530 [0] AVG Duty = 4969%(X100)
7132 00:42:53.719942
7133 00:42:53.722190 CH1 DQ 0 Duty spec in!! Max-Min= 155%
7134 00:42:53.725694
7135 00:42:53.728927 CH1 DQ 1 Duty spec in!! Max-Min= 186%
7136 00:42:53.732226 [DutyScan_Calibration_Flow] ====Done====
7137 00:42:53.735597 nWR fixed to 30
7138 00:42:53.736123 [ModeRegInit_LP4] CH0 RK0
7139 00:42:53.738757 [ModeRegInit_LP4] CH0 RK1
7140 00:42:53.742392 [ModeRegInit_LP4] CH1 RK0
7141 00:42:53.745221 [ModeRegInit_LP4] CH1 RK1
7142 00:42:53.745663 match AC timing 4
7143 00:42:53.748728 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 0
7144 00:42:53.755145 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7145 00:42:53.758679 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7146 00:42:53.762105 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7147 00:42:53.768598 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7148 00:42:53.769041 [MiockJmeterHQA]
7149 00:42:53.769384
7150 00:42:53.772400 [DramcMiockJmeter] u1RxGatingPI = 0
7151 00:42:53.775212 0 : 4257, 4029
7152 00:42:53.775661 4 : 4363, 4138
7153 00:42:53.776111 8 : 4258, 4026
7154 00:42:53.778809 12 : 4368, 4139
7155 00:42:53.779255 16 : 4257, 4029
7156 00:42:53.782115 20 : 4252, 4027
7157 00:42:53.782600 24 : 4253, 4027
7158 00:42:53.785556 28 : 4363, 4137
7159 00:42:53.786112 32 : 4364, 4137
7160 00:42:53.788479 36 : 4255, 4029
7161 00:42:53.788919 40 : 4253, 4026
7162 00:42:53.789269 44 : 4253, 4027
7163 00:42:53.791963 48 : 4252, 4027
7164 00:42:53.792407 52 : 4253, 4027
7165 00:42:53.795246 56 : 4363, 4138
7166 00:42:53.795690 60 : 4253, 4026
7167 00:42:53.798654 64 : 4252, 4026
7168 00:42:53.799098 68 : 4250, 4027
7169 00:42:53.799451 72 : 4253, 4027
7170 00:42:53.801889 76 : 4250, 4027
7171 00:42:53.802372 80 : 4360, 4137
7172 00:42:53.805316 84 : 4361, 4137
7173 00:42:53.805832 88 : 4249, 4027
7174 00:42:53.808643 92 : 4250, 4027
7175 00:42:53.809131 96 : 4250, 4027
7176 00:42:53.812025 100 : 4250, 1767
7177 00:42:53.812584 104 : 4250, 0
7178 00:42:53.812906 108 : 4255, 0
7179 00:42:53.815405 112 : 4250, 0
7180 00:42:53.815808 116 : 4250, 0
7181 00:42:53.818708 120 : 4250, 0
7182 00:42:53.819114 124 : 4250, 0
7183 00:42:53.819437 128 : 4250, 0
7184 00:42:53.821966 132 : 4360, 0
7185 00:42:53.822402 136 : 4361, 0
7186 00:42:53.822723 140 : 4361, 0
7187 00:42:53.825158 144 : 4250, 0
7188 00:42:53.825560 148 : 4250, 0
7189 00:42:53.828571 152 : 4250, 0
7190 00:42:53.829058 156 : 4250, 0
7191 00:42:53.829375 160 : 4250, 0
7192 00:42:53.832009 164 : 4250, 0
7193 00:42:53.832497 168 : 4250, 0
7194 00:42:53.835418 172 : 4250, 0
7195 00:42:53.835905 176 : 4250, 0
7196 00:42:53.836227 180 : 4253, 0
7197 00:42:53.838798 184 : 4361, 0
7198 00:42:53.839203 188 : 4361, 0
7199 00:42:53.842198 192 : 4361, 0
7200 00:42:53.842714 196 : 4250, 0
7201 00:42:53.843035 200 : 4360, 0
7202 00:42:53.845189 204 : 4250, 0
7203 00:42:53.845583 208 : 4250, 0
7204 00:42:53.845954 212 : 4250, 0
7205 00:42:53.848519 216 : 4250, 0
7206 00:42:53.849000 220 : 4250, 462
7207 00:42:53.851801 224 : 4250, 3985
7208 00:42:53.852279 228 : 4253, 4030
7209 00:42:53.854821 232 : 4250, 4027
7210 00:42:53.855217 236 : 4252, 4030
7211 00:42:53.858531 240 : 4250, 4027
7212 00:42:53.859053 244 : 4252, 4027
7213 00:42:53.861765 248 : 4360, 4137
7214 00:42:53.862312 252 : 4250, 4027
7215 00:42:53.865015 256 : 4250, 4027
7216 00:42:53.865534 260 : 4361, 4138
7217 00:42:53.866022 264 : 4250, 4027
7218 00:42:53.868472 268 : 4250, 4026
7219 00:42:53.869075 272 : 4361, 4137
7220 00:42:53.871530 276 : 4250, 4026
7221 00:42:53.871973 280 : 4250, 4027
7222 00:42:53.874800 284 : 4250, 4026
7223 00:42:53.875241 288 : 4250, 4027
7224 00:42:53.878170 292 : 4250, 4027
7225 00:42:53.878656 296 : 4250, 4027
7226 00:42:53.881398 300 : 4360, 4137
7227 00:42:53.881840 304 : 4249, 4027
7228 00:42:53.885083 308 : 4250, 4027
7229 00:42:53.885619 312 : 4361, 4138
7230 00:42:53.887964 316 : 4250, 4027
7231 00:42:53.888406 320 : 4250, 4027
7232 00:42:53.891259 324 : 4361, 4137
7233 00:42:53.891700 328 : 4250, 4027
7234 00:42:53.892047 332 : 4250, 4027
7235 00:42:53.894531 336 : 4250, 3933
7236 00:42:53.895034 340 : 4250, 1807
7237 00:42:53.895386
7238 00:42:53.898291 MIOCK jitter meter ch=0
7239 00:42:53.898738
7240 00:42:53.901594 1T = (340-100) = 240 dly cells
7241 00:42:53.907863 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 271/100 ps
7242 00:42:53.908378 ==
7243 00:42:53.911134 Dram Type= 6, Freq= 0, CH_0, rank 0
7244 00:42:53.914538 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7245 00:42:53.914975 ==
7246 00:42:53.921034 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7247 00:42:53.924278 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7248 00:42:53.927743 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7249 00:42:53.934373 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7250 00:42:53.942800 [CA 0] Center 42 (12~72) winsize 61
7251 00:42:53.946246 [CA 1] Center 41 (11~72) winsize 62
7252 00:42:53.949344 [CA 2] Center 37 (7~68) winsize 62
7253 00:42:53.952780 [CA 3] Center 37 (7~67) winsize 61
7254 00:42:53.956070 [CA 4] Center 35 (5~66) winsize 62
7255 00:42:53.959652 [CA 5] Center 35 (5~65) winsize 61
7256 00:42:53.960088
7257 00:42:53.962747 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7258 00:42:53.963320
7259 00:42:53.965867 [CATrainingPosCal] consider 1 rank data
7260 00:42:53.968928 u2DelayCellTimex100 = 271/100 ps
7261 00:42:53.972626 CA0 delay=42 (12~72),Diff = 7 PI (25 cell)
7262 00:42:53.978996 CA1 delay=41 (11~72),Diff = 6 PI (21 cell)
7263 00:42:53.982401 CA2 delay=37 (7~68),Diff = 2 PI (7 cell)
7264 00:42:53.985869 CA3 delay=37 (7~67),Diff = 2 PI (7 cell)
7265 00:42:53.988758 CA4 delay=35 (5~66),Diff = 0 PI (0 cell)
7266 00:42:53.992382 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7267 00:42:53.992895
7268 00:42:53.995544 CA PerBit enable=1, Macro0, CA PI delay=35
7269 00:42:53.995979
7270 00:42:53.998807 [CBTSetCACLKResult] CA Dly = 35
7271 00:42:54.002320 CS Dly: 11 (0~42)
7272 00:42:54.005739 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7273 00:42:54.008928 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7274 00:42:54.009441 ==
7275 00:42:54.012398 Dram Type= 6, Freq= 0, CH_0, rank 1
7276 00:42:54.018993 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7277 00:42:54.019690 ==
7278 00:42:54.021897 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7279 00:42:54.025141 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7280 00:42:54.032309 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7281 00:42:54.038419 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7282 00:42:54.045522 [CA 0] Center 42 (12~73) winsize 62
7283 00:42:54.048858 [CA 1] Center 42 (12~73) winsize 62
7284 00:42:54.052015 [CA 2] Center 38 (9~68) winsize 60
7285 00:42:54.055769 [CA 3] Center 38 (8~68) winsize 61
7286 00:42:54.058490 [CA 4] Center 36 (6~66) winsize 61
7287 00:42:54.061984 [CA 5] Center 36 (6~66) winsize 61
7288 00:42:54.062557
7289 00:42:54.065463 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7290 00:42:54.065903
7291 00:42:54.071742 [CATrainingPosCal] consider 2 rank data
7292 00:42:54.072182 u2DelayCellTimex100 = 271/100 ps
7293 00:42:54.078138 CA0 delay=42 (12~72),Diff = 7 PI (25 cell)
7294 00:42:54.081599 CA1 delay=42 (12~72),Diff = 7 PI (25 cell)
7295 00:42:54.084653 CA2 delay=38 (9~68),Diff = 3 PI (10 cell)
7296 00:42:54.087956 CA3 delay=37 (8~67),Diff = 2 PI (7 cell)
7297 00:42:54.091460 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7298 00:42:54.094712 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7299 00:42:54.095266
7300 00:42:54.097883 CA PerBit enable=1, Macro0, CA PI delay=35
7301 00:42:54.098308
7302 00:42:54.101416 [CBTSetCACLKResult] CA Dly = 35
7303 00:42:54.104710 CS Dly: 11 (0~42)
7304 00:42:54.107788 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7305 00:42:54.111294 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7306 00:42:54.111570
7307 00:42:54.114755 ----->DramcWriteLeveling(PI) begin...
7308 00:42:54.115109 ==
7309 00:42:54.117821 Dram Type= 6, Freq= 0, CH_0, rank 0
7310 00:42:54.124452 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7311 00:42:54.124808 ==
7312 00:42:54.127664 Write leveling (Byte 0): 28 => 28
7313 00:42:54.131092 Write leveling (Byte 1): 28 => 28
7314 00:42:54.131455 DramcWriteLeveling(PI) end<-----
7315 00:42:54.134565
7316 00:42:54.134990 ==
7317 00:42:54.138108 Dram Type= 6, Freq= 0, CH_0, rank 0
7318 00:42:54.141123 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7319 00:42:54.141635 ==
7320 00:42:54.144379 [Gating] SW mode calibration
7321 00:42:54.150968 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7322 00:42:54.154590 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7323 00:42:54.160817 0 12 0 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
7324 00:42:54.164048 0 12 4 | B1->B0 | 2424 3434 | 1 0 | (1 1) (0 0)
7325 00:42:54.167322 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7326 00:42:54.174000 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7327 00:42:54.177386 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7328 00:42:54.180776 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7329 00:42:54.187531 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7330 00:42:54.190680 0 12 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7331 00:42:54.193601 0 13 0 | B1->B0 | 3434 3131 | 1 0 | (1 1) (1 0)
7332 00:42:54.200607 0 13 4 | B1->B0 | 2d2d 2323 | 0 0 | (1 0) (0 0)
7333 00:42:54.203768 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7334 00:42:54.206948 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7335 00:42:54.214017 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7336 00:42:54.216986 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7337 00:42:54.220410 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7338 00:42:54.227098 0 13 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7339 00:42:54.230729 0 14 0 | B1->B0 | 2424 3e3e | 0 1 | (0 0) (0 0)
7340 00:42:54.233523 0 14 4 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
7341 00:42:54.240320 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7342 00:42:54.244052 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7343 00:42:54.247461 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7344 00:42:54.253604 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7345 00:42:54.257276 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7346 00:42:54.260033 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7347 00:42:54.266563 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7348 00:42:54.269780 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7349 00:42:54.273224 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7350 00:42:54.280018 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7351 00:42:54.283094 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7352 00:42:54.286573 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7353 00:42:54.293020 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7354 00:42:54.296152 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7355 00:42:54.299643 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7356 00:42:54.306272 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7357 00:42:54.309447 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7358 00:42:54.312895 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7359 00:42:54.319284 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7360 00:42:54.322503 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7361 00:42:54.325949 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7362 00:42:54.332539 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7363 00:42:54.335693 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7364 00:42:54.339343 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7365 00:42:54.345686 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7366 00:42:54.346322 Total UI for P1: 0, mck2ui 16
7367 00:42:54.352454 best dqsien dly found for B0: ( 1, 1, 0)
7368 00:42:54.353027 Total UI for P1: 0, mck2ui 16
7369 00:42:54.359010 best dqsien dly found for B1: ( 1, 1, 4)
7370 00:42:54.362551 best DQS0 dly(MCK, UI, PI) = (1, 1, 0)
7371 00:42:54.365668 best DQS1 dly(MCK, UI, PI) = (1, 1, 4)
7372 00:42:54.366082
7373 00:42:54.369207 best DQS0 P1 dly(MCK, UI, PI) = (1, 5, 0)
7374 00:42:54.372333 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 4)
7375 00:42:54.376415 [Gating] SW calibration Done
7376 00:42:54.376809 ==
7377 00:42:54.378841 Dram Type= 6, Freq= 0, CH_0, rank 0
7378 00:42:54.382058 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7379 00:42:54.382487 ==
7380 00:42:54.385972 RX Vref Scan: 0
7381 00:42:54.386492
7382 00:42:54.386803 RX Vref 0 -> 0, step: 1
7383 00:42:54.387087
7384 00:42:54.388828 RX Delay 0 -> 252, step: 8
7385 00:42:54.392743 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7386 00:42:54.395394 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
7387 00:42:54.402292 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
7388 00:42:54.405260 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7389 00:42:54.409092 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7390 00:42:54.412515 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7391 00:42:54.415237 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
7392 00:42:54.422334 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7393 00:42:54.425685 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
7394 00:42:54.428974 iDelay=200, Bit 9, Center 107 (56 ~ 159) 104
7395 00:42:54.431966 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7396 00:42:54.435502 iDelay=200, Bit 11, Center 115 (64 ~ 167) 104
7397 00:42:54.442390 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7398 00:42:54.445440 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7399 00:42:54.448669 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7400 00:42:54.452095 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7401 00:42:54.455043 ==
7402 00:42:54.455557 Dram Type= 6, Freq= 0, CH_0, rank 0
7403 00:42:54.461928 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7404 00:42:54.462481 ==
7405 00:42:54.462827 DQS Delay:
7406 00:42:54.464936 DQS0 = 0, DQS1 = 0
7407 00:42:54.465369 DQM Delay:
7408 00:42:54.468132 DQM0 = 130, DQM1 = 124
7409 00:42:54.468567 DQ Delay:
7410 00:42:54.471673 DQ0 =127, DQ1 =131, DQ2 =123, DQ3 =127
7411 00:42:54.475479 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =139
7412 00:42:54.478374 DQ8 =115, DQ9 =107, DQ10 =123, DQ11 =115
7413 00:42:54.481440 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
7414 00:42:54.482063
7415 00:42:54.482613
7416 00:42:54.483133 ==
7417 00:42:54.484845 Dram Type= 6, Freq= 0, CH_0, rank 0
7418 00:42:54.491916 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7419 00:42:54.492425 ==
7420 00:42:54.492767
7421 00:42:54.493079
7422 00:42:54.493378 TX Vref Scan disable
7423 00:42:54.494956 == TX Byte 0 ==
7424 00:42:54.498707 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7425 00:42:54.504978 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7426 00:42:54.505459 == TX Byte 1 ==
7427 00:42:54.508580 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7428 00:42:54.514916 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7429 00:42:54.515428 ==
7430 00:42:54.518256 Dram Type= 6, Freq= 0, CH_0, rank 0
7431 00:42:54.521270 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7432 00:42:54.521733 ==
7433 00:42:54.533789
7434 00:42:54.536834 TX Vref early break, caculate TX vref
7435 00:42:54.540460 TX Vref=16, minBit 9, minWin=22, winSum=377
7436 00:42:54.543638 TX Vref=18, minBit 8, minWin=22, winSum=383
7437 00:42:54.546676 TX Vref=20, minBit 8, minWin=23, winSum=395
7438 00:42:54.550163 TX Vref=22, minBit 9, minWin=23, winSum=403
7439 00:42:54.553631 TX Vref=24, minBit 6, minWin=25, winSum=412
7440 00:42:54.559927 TX Vref=26, minBit 8, minWin=24, winSum=414
7441 00:42:54.563217 TX Vref=28, minBit 8, minWin=25, winSum=422
7442 00:42:54.566524 TX Vref=30, minBit 0, minWin=25, winSum=416
7443 00:42:54.569900 TX Vref=32, minBit 0, minWin=25, winSum=410
7444 00:42:54.573202 TX Vref=34, minBit 1, minWin=24, winSum=398
7445 00:42:54.579804 [TxChooseVref] Worse bit 8, Min win 25, Win sum 422, Final Vref 28
7446 00:42:54.580246
7447 00:42:54.583180 Final TX Range 0 Vref 28
7448 00:42:54.583699
7449 00:42:54.584043 ==
7450 00:42:54.586595 Dram Type= 6, Freq= 0, CH_0, rank 0
7451 00:42:54.589877 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7452 00:42:54.590477 ==
7453 00:42:54.590830
7454 00:42:54.591147
7455 00:42:54.593291 TX Vref Scan disable
7456 00:42:54.599837 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
7457 00:42:54.600363 == TX Byte 0 ==
7458 00:42:54.603058 u2DelayCellOfst[0]=10 cells (3 PI)
7459 00:42:54.606396 u2DelayCellOfst[1]=18 cells (5 PI)
7460 00:42:54.609893 u2DelayCellOfst[2]=10 cells (3 PI)
7461 00:42:54.613371 u2DelayCellOfst[3]=10 cells (3 PI)
7462 00:42:54.616322 u2DelayCellOfst[4]=7 cells (2 PI)
7463 00:42:54.619535 u2DelayCellOfst[5]=0 cells (0 PI)
7464 00:42:54.623116 u2DelayCellOfst[6]=18 cells (5 PI)
7465 00:42:54.625998 u2DelayCellOfst[7]=18 cells (5 PI)
7466 00:42:54.629310 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7467 00:42:54.632717 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7468 00:42:54.636054 == TX Byte 1 ==
7469 00:42:54.636481 u2DelayCellOfst[8]=3 cells (1 PI)
7470 00:42:54.639825 u2DelayCellOfst[9]=0 cells (0 PI)
7471 00:42:54.642792 u2DelayCellOfst[10]=10 cells (3 PI)
7472 00:42:54.646282 u2DelayCellOfst[11]=7 cells (2 PI)
7473 00:42:54.650045 u2DelayCellOfst[12]=18 cells (5 PI)
7474 00:42:54.653104 u2DelayCellOfst[13]=18 cells (5 PI)
7475 00:42:54.656505 u2DelayCellOfst[14]=21 cells (6 PI)
7476 00:42:54.659600 u2DelayCellOfst[15]=18 cells (5 PI)
7477 00:42:54.662818 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
7478 00:42:54.669604 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7479 00:42:54.670130 DramC Write-DBI on
7480 00:42:54.670665 ==
7481 00:42:54.673376 Dram Type= 6, Freq= 0, CH_0, rank 0
7482 00:42:54.676118 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7483 00:42:54.679513 ==
7484 00:42:54.679944
7485 00:42:54.680282
7486 00:42:54.680595 TX Vref Scan disable
7487 00:42:54.682884 == TX Byte 0 ==
7488 00:42:54.686562 Update DQM dly =727 (2 ,6, 23) DQM OEN =(3 ,3)
7489 00:42:54.689581 == TX Byte 1 ==
7490 00:42:54.692902 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
7491 00:42:54.696398 DramC Write-DBI off
7492 00:42:54.696907
7493 00:42:54.697243 [DATLAT]
7494 00:42:54.697570 Freq=1600, CH0 RK0
7495 00:42:54.697872
7496 00:42:54.699403 DATLAT Default: 0xf
7497 00:42:54.699916 0, 0xFFFF, sum = 0
7498 00:42:54.702926 1, 0xFFFF, sum = 0
7499 00:42:54.705755 2, 0xFFFF, sum = 0
7500 00:42:54.706190 3, 0xFFFF, sum = 0
7501 00:42:54.709345 4, 0xFFFF, sum = 0
7502 00:42:54.709863 5, 0xFFFF, sum = 0
7503 00:42:54.712729 6, 0xFFFF, sum = 0
7504 00:42:54.713246 7, 0xFFFF, sum = 0
7505 00:42:54.716031 8, 0xFFFF, sum = 0
7506 00:42:54.716470 9, 0xFFFF, sum = 0
7507 00:42:54.719256 10, 0xFFFF, sum = 0
7508 00:42:54.719693 11, 0xFFFF, sum = 0
7509 00:42:54.722468 12, 0xBFF, sum = 0
7510 00:42:54.722921 13, 0x0, sum = 1
7511 00:42:54.725929 14, 0x0, sum = 2
7512 00:42:54.726412 15, 0x0, sum = 3
7513 00:42:54.729010 16, 0x0, sum = 4
7514 00:42:54.729446 best_step = 14
7515 00:42:54.729796
7516 00:42:54.730110 ==
7517 00:42:54.732529 Dram Type= 6, Freq= 0, CH_0, rank 0
7518 00:42:54.735487 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7519 00:42:54.738953 ==
7520 00:42:54.739385 RX Vref Scan: 1
7521 00:42:54.739738
7522 00:42:54.742089 Set Vref Range= 24 -> 127
7523 00:42:54.742577
7524 00:42:54.745593 RX Vref 24 -> 127, step: 1
7525 00:42:54.746113
7526 00:42:54.746525 RX Delay 11 -> 252, step: 4
7527 00:42:54.746845
7528 00:42:54.748704 Set Vref, RX VrefLevel [Byte0]: 24
7529 00:42:54.752305 [Byte1]: 24
7530 00:42:54.756281
7531 00:42:54.756799 Set Vref, RX VrefLevel [Byte0]: 25
7532 00:42:54.759555 [Byte1]: 25
7533 00:42:54.763712
7534 00:42:54.764197 Set Vref, RX VrefLevel [Byte0]: 26
7535 00:42:54.766910 [Byte1]: 26
7536 00:42:54.771204
7537 00:42:54.771635 Set Vref, RX VrefLevel [Byte0]: 27
7538 00:42:54.774650 [Byte1]: 27
7539 00:42:54.778724
7540 00:42:54.781964 Set Vref, RX VrefLevel [Byte0]: 28
7541 00:42:54.785230 [Byte1]: 28
7542 00:42:54.785666
7543 00:42:54.788658 Set Vref, RX VrefLevel [Byte0]: 29
7544 00:42:54.791810 [Byte1]: 29
7545 00:42:54.792242
7546 00:42:54.795451 Set Vref, RX VrefLevel [Byte0]: 30
7547 00:42:54.798623 [Byte1]: 30
7548 00:42:54.801891
7549 00:42:54.802446 Set Vref, RX VrefLevel [Byte0]: 31
7550 00:42:54.805268 [Byte1]: 31
7551 00:42:54.809499
7552 00:42:54.810008 Set Vref, RX VrefLevel [Byte0]: 32
7553 00:42:54.812988 [Byte1]: 32
7554 00:42:54.816970
7555 00:42:54.817405 Set Vref, RX VrefLevel [Byte0]: 33
7556 00:42:54.820462 [Byte1]: 33
7557 00:42:54.824564
7558 00:42:54.825003 Set Vref, RX VrefLevel [Byte0]: 34
7559 00:42:54.827779 [Byte1]: 34
7560 00:42:54.832450
7561 00:42:54.832984 Set Vref, RX VrefLevel [Byte0]: 35
7562 00:42:54.835829 [Byte1]: 35
7563 00:42:54.840018
7564 00:42:54.840529 Set Vref, RX VrefLevel [Byte0]: 36
7565 00:42:54.843482 [Byte1]: 36
7566 00:42:54.847778
7567 00:42:54.848302 Set Vref, RX VrefLevel [Byte0]: 37
7568 00:42:54.850927 [Byte1]: 37
7569 00:42:54.855200
7570 00:42:54.855633 Set Vref, RX VrefLevel [Byte0]: 38
7571 00:42:54.858893 [Byte1]: 38
7572 00:42:54.863122
7573 00:42:54.863647 Set Vref, RX VrefLevel [Byte0]: 39
7574 00:42:54.866018 [Byte1]: 39
7575 00:42:54.870406
7576 00:42:54.870934 Set Vref, RX VrefLevel [Byte0]: 40
7577 00:42:54.873918 [Byte1]: 40
7578 00:42:54.877875
7579 00:42:54.878349 Set Vref, RX VrefLevel [Byte0]: 41
7580 00:42:54.881083 [Byte1]: 41
7581 00:42:54.885479
7582 00:42:54.885996 Set Vref, RX VrefLevel [Byte0]: 42
7583 00:42:54.889125 [Byte1]: 42
7584 00:42:54.893383
7585 00:42:54.893898 Set Vref, RX VrefLevel [Byte0]: 43
7586 00:42:54.896456 [Byte1]: 43
7587 00:42:54.900956
7588 00:42:54.901468 Set Vref, RX VrefLevel [Byte0]: 44
7589 00:42:54.904167 [Byte1]: 44
7590 00:42:54.908339
7591 00:42:54.908771 Set Vref, RX VrefLevel [Byte0]: 45
7592 00:42:54.911821 [Byte1]: 45
7593 00:42:54.916048
7594 00:42:54.916581 Set Vref, RX VrefLevel [Byte0]: 46
7595 00:42:54.919506 [Byte1]: 46
7596 00:42:54.923612
7597 00:42:54.924173 Set Vref, RX VrefLevel [Byte0]: 47
7598 00:42:54.927237 [Byte1]: 47
7599 00:42:54.930984
7600 00:42:54.931445 Set Vref, RX VrefLevel [Byte0]: 48
7601 00:42:54.934810 [Byte1]: 48
7602 00:42:54.938619
7603 00:42:54.939055 Set Vref, RX VrefLevel [Byte0]: 49
7604 00:42:54.942298 [Byte1]: 49
7605 00:42:54.946655
7606 00:42:54.947090 Set Vref, RX VrefLevel [Byte0]: 50
7607 00:42:54.949957 [Byte1]: 50
7608 00:42:54.954182
7609 00:42:54.954753 Set Vref, RX VrefLevel [Byte0]: 51
7610 00:42:54.957386 [Byte1]: 51
7611 00:42:54.961698
7612 00:42:54.962261 Set Vref, RX VrefLevel [Byte0]: 52
7613 00:42:54.964855 [Byte1]: 52
7614 00:42:54.969390
7615 00:42:54.969950 Set Vref, RX VrefLevel [Byte0]: 53
7616 00:42:54.972690 [Byte1]: 53
7617 00:42:54.976698
7618 00:42:54.977132 Set Vref, RX VrefLevel [Byte0]: 54
7619 00:42:54.980392 [Byte1]: 54
7620 00:42:54.984588
7621 00:42:54.985180 Set Vref, RX VrefLevel [Byte0]: 55
7622 00:42:54.987626 [Byte1]: 55
7623 00:42:54.992255
7624 00:42:54.992766 Set Vref, RX VrefLevel [Byte0]: 56
7625 00:42:54.995764 [Byte1]: 56
7626 00:42:54.999793
7627 00:42:55.000324 Set Vref, RX VrefLevel [Byte0]: 57
7628 00:42:55.003434 [Byte1]: 57
7629 00:42:55.007626
7630 00:42:55.008137 Set Vref, RX VrefLevel [Byte0]: 58
7631 00:42:55.010595 [Byte1]: 58
7632 00:42:55.015183
7633 00:42:55.015698 Set Vref, RX VrefLevel [Byte0]: 59
7634 00:42:55.018340 [Byte1]: 59
7635 00:42:55.022474
7636 00:42:55.022981 Set Vref, RX VrefLevel [Byte0]: 60
7637 00:42:55.025812 [Byte1]: 60
7638 00:42:55.029997
7639 00:42:55.030495 Set Vref, RX VrefLevel [Byte0]: 61
7640 00:42:55.033436 [Byte1]: 61
7641 00:42:55.037761
7642 00:42:55.038313 Set Vref, RX VrefLevel [Byte0]: 62
7643 00:42:55.041106 [Byte1]: 62
7644 00:42:55.045473
7645 00:42:55.046002 Set Vref, RX VrefLevel [Byte0]: 63
7646 00:42:55.048840 [Byte1]: 63
7647 00:42:55.053394
7648 00:42:55.053920 Set Vref, RX VrefLevel [Byte0]: 64
7649 00:42:55.060042 [Byte1]: 64
7650 00:42:55.060908
7651 00:42:55.061275 Set Vref, RX VrefLevel [Byte0]: 65
7652 00:42:55.064162 [Byte1]: 65
7653 00:42:55.068510
7654 00:42:55.069032 Set Vref, RX VrefLevel [Byte0]: 66
7655 00:42:55.071296 [Byte1]: 66
7656 00:42:55.075799
7657 00:42:55.076432 Set Vref, RX VrefLevel [Byte0]: 67
7658 00:42:55.078892 [Byte1]: 67
7659 00:42:55.083511
7660 00:42:55.083943 Set Vref, RX VrefLevel [Byte0]: 68
7661 00:42:55.086758 [Byte1]: 68
7662 00:42:55.090848
7663 00:42:55.091277 Set Vref, RX VrefLevel [Byte0]: 69
7664 00:42:55.094918 [Byte1]: 69
7665 00:42:55.099099
7666 00:42:55.099615 Set Vref, RX VrefLevel [Byte0]: 70
7667 00:42:55.101889 [Byte1]: 70
7668 00:42:55.106292
7669 00:42:55.106725 Set Vref, RX VrefLevel [Byte0]: 71
7670 00:42:55.109668 [Byte1]: 71
7671 00:42:55.114148
7672 00:42:55.114718 Final RX Vref Byte 0 = 50 to rank0
7673 00:42:55.117019 Final RX Vref Byte 1 = 56 to rank0
7674 00:42:55.120474 Final RX Vref Byte 0 = 50 to rank1
7675 00:42:55.123947 Final RX Vref Byte 1 = 56 to rank1==
7676 00:42:55.127080 Dram Type= 6, Freq= 0, CH_0, rank 0
7677 00:42:55.133652 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7678 00:42:55.134181 ==
7679 00:42:55.134585 DQS Delay:
7680 00:42:55.137249 DQS0 = 0, DQS1 = 0
7681 00:42:55.137776 DQM Delay:
7682 00:42:55.138121 DQM0 = 126, DQM1 = 121
7683 00:42:55.140472 DQ Delay:
7684 00:42:55.143536 DQ0 =122, DQ1 =126, DQ2 =124, DQ3 =124
7685 00:42:55.147119 DQ4 =130, DQ5 =116, DQ6 =136, DQ7 =134
7686 00:42:55.150400 DQ8 =112, DQ9 =104, DQ10 =120, DQ11 =112
7687 00:42:55.153766 DQ12 =126, DQ13 =126, DQ14 =134, DQ15 =134
7688 00:42:55.154317
7689 00:42:55.154663
7690 00:42:55.154975
7691 00:42:55.156963 [DramC_TX_OE_Calibration] TA2
7692 00:42:55.160655 Original DQ_B0 (3 6) =30, OEN = 27
7693 00:42:55.163484 Original DQ_B1 (3 6) =30, OEN = 27
7694 00:42:55.166760 24, 0x0, End_B0=24 End_B1=24
7695 00:42:55.167204 25, 0x0, End_B0=25 End_B1=25
7696 00:42:55.170306 26, 0x0, End_B0=26 End_B1=26
7697 00:42:55.173338 27, 0x0, End_B0=27 End_B1=27
7698 00:42:55.176833 28, 0x0, End_B0=28 End_B1=28
7699 00:42:55.179828 29, 0x0, End_B0=29 End_B1=29
7700 00:42:55.180318 30, 0x0, End_B0=30 End_B1=30
7701 00:42:55.183490 31, 0x4141, End_B0=30 End_B1=30
7702 00:42:55.186349 Byte0 end_step=30 best_step=27
7703 00:42:55.190038 Byte1 end_step=30 best_step=27
7704 00:42:55.193465 Byte0 TX OE(2T, 0.5T) = (3, 3)
7705 00:42:55.196832 Byte1 TX OE(2T, 0.5T) = (3, 3)
7706 00:42:55.197378
7707 00:42:55.197717
7708 00:42:55.202956 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a1a, (MSB)MR19= 0x303, tDQSOscB0 = 396 ps tDQSOscB1 = 396 ps
7709 00:42:55.206484 CH0 RK0: MR19=303, MR18=1A1A
7710 00:42:55.213232 CH0_RK0: MR19=0x303, MR18=0x1A1A, DQSOSC=396, MR23=63, INC=23, DEC=15
7711 00:42:55.213752
7712 00:42:55.216581 ----->DramcWriteLeveling(PI) begin...
7713 00:42:55.217100 ==
7714 00:42:55.219553 Dram Type= 6, Freq= 0, CH_0, rank 1
7715 00:42:55.223033 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7716 00:42:55.223545 ==
7717 00:42:55.226128 Write leveling (Byte 0): 30 => 30
7718 00:42:55.229251 Write leveling (Byte 1): 25 => 25
7719 00:42:55.232680 DramcWriteLeveling(PI) end<-----
7720 00:42:55.233266
7721 00:42:55.233764 ==
7722 00:42:55.235893 Dram Type= 6, Freq= 0, CH_0, rank 1
7723 00:42:55.239180 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7724 00:42:55.242535 ==
7725 00:42:55.243165 [Gating] SW mode calibration
7726 00:42:55.249423 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7727 00:42:55.256576 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7728 00:42:55.259040 0 12 0 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
7729 00:42:55.265936 0 12 4 | B1->B0 | 2424 3434 | 1 1 | (0 0) (1 1)
7730 00:42:55.269594 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7731 00:42:55.272664 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7732 00:42:55.279118 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7733 00:42:55.282817 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7734 00:42:55.285962 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7735 00:42:55.292412 0 12 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7736 00:42:55.296053 0 13 0 | B1->B0 | 3434 3030 | 1 0 | (1 0) (1 0)
7737 00:42:55.299170 0 13 4 | B1->B0 | 2d2d 2323 | 0 0 | (0 1) (0 0)
7738 00:42:55.305959 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7739 00:42:55.309021 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7740 00:42:55.312378 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7741 00:42:55.319083 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7742 00:42:55.322206 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7743 00:42:55.325713 0 13 28 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
7744 00:42:55.332722 0 14 0 | B1->B0 | 2323 4040 | 0 0 | (0 0) (0 0)
7745 00:42:55.335284 0 14 4 | B1->B0 | 3d3d 4646 | 1 0 | (0 0) (0 0)
7746 00:42:55.338651 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7747 00:42:55.345352 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7748 00:42:55.348887 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7749 00:42:55.351958 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7750 00:42:55.359062 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7751 00:42:55.361855 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7752 00:42:55.365437 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7753 00:42:55.368476 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7754 00:42:55.375311 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7755 00:42:55.378474 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7756 00:42:55.381749 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7757 00:42:55.388412 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7758 00:42:55.391963 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7759 00:42:55.395099 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7760 00:42:55.401605 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7761 00:42:55.405096 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7762 00:42:55.408441 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7763 00:42:55.414964 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7764 00:42:55.418429 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7765 00:42:55.421782 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7766 00:42:55.428120 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7767 00:42:55.431430 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7768 00:42:55.434779 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7769 00:42:55.441490 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7770 00:42:55.444507 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7771 00:42:55.447912 Total UI for P1: 0, mck2ui 16
7772 00:42:55.451400 best dqsien dly found for B0: ( 1, 1, 0)
7773 00:42:55.455568 Total UI for P1: 0, mck2ui 16
7774 00:42:55.457927 best dqsien dly found for B1: ( 1, 1, 2)
7775 00:42:55.461852 best DQS0 dly(MCK, UI, PI) = (1, 1, 0)
7776 00:42:55.464850 best DQS1 dly(MCK, UI, PI) = (1, 1, 2)
7777 00:42:55.465243
7778 00:42:55.468051 best DQS0 P1 dly(MCK, UI, PI) = (1, 5, 0)
7779 00:42:55.471137 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 2)
7780 00:42:55.474572 [Gating] SW calibration Done
7781 00:42:55.474966 ==
7782 00:42:55.478138 Dram Type= 6, Freq= 0, CH_0, rank 1
7783 00:42:55.481414 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7784 00:42:55.481807 ==
7785 00:42:55.484689 RX Vref Scan: 0
7786 00:42:55.485081
7787 00:42:55.488112 RX Vref 0 -> 0, step: 1
7788 00:42:55.488592
7789 00:42:55.488902 RX Delay 0 -> 252, step: 8
7790 00:42:55.494792 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7791 00:42:55.497851 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
7792 00:42:55.501494 iDelay=200, Bit 2, Center 131 (72 ~ 191) 120
7793 00:42:55.504372 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7794 00:42:55.507748 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
7795 00:42:55.514163 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7796 00:42:55.517438 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
7797 00:42:55.520929 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7798 00:42:55.524287 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7799 00:42:55.527647 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7800 00:42:55.534289 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7801 00:42:55.537523 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7802 00:42:55.541216 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7803 00:42:55.544442 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7804 00:42:55.550854 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
7805 00:42:55.554156 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7806 00:42:55.554622 ==
7807 00:42:55.557414 Dram Type= 6, Freq= 0, CH_0, rank 1
7808 00:42:55.560945 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7809 00:42:55.561341 ==
7810 00:42:55.561646 DQS Delay:
7811 00:42:55.564502 DQS0 = 0, DQS1 = 0
7812 00:42:55.564895 DQM Delay:
7813 00:42:55.567373 DQM0 = 130, DQM1 = 123
7814 00:42:55.567766 DQ Delay:
7815 00:42:55.570730 DQ0 =127, DQ1 =131, DQ2 =131, DQ3 =127
7816 00:42:55.574206 DQ4 =131, DQ5 =119, DQ6 =139, DQ7 =139
7817 00:42:55.577753 DQ8 =111, DQ9 =111, DQ10 =123, DQ11 =119
7818 00:42:55.583849 DQ12 =131, DQ13 =131, DQ14 =131, DQ15 =131
7819 00:42:55.584322
7820 00:42:55.584632
7821 00:42:55.584916 ==
7822 00:42:55.587138 Dram Type= 6, Freq= 0, CH_0, rank 1
7823 00:42:55.590715 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7824 00:42:55.591172 ==
7825 00:42:55.591481
7826 00:42:55.591763
7827 00:42:55.594176 TX Vref Scan disable
7828 00:42:55.594712 == TX Byte 0 ==
7829 00:42:55.600762 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7830 00:42:55.604194 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7831 00:42:55.604686 == TX Byte 1 ==
7832 00:42:55.610611 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
7833 00:42:55.614405 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
7834 00:42:55.614902 ==
7835 00:42:55.617180 Dram Type= 6, Freq= 0, CH_0, rank 1
7836 00:42:55.620248 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7837 00:42:55.620660 ==
7838 00:42:55.634805
7839 00:42:55.638166 TX Vref early break, caculate TX vref
7840 00:42:55.641461 TX Vref=16, minBit 1, minWin=22, winSum=372
7841 00:42:55.644863 TX Vref=18, minBit 1, minWin=23, winSum=384
7842 00:42:55.648014 TX Vref=20, minBit 1, minWin=23, winSum=389
7843 00:42:55.650863 TX Vref=22, minBit 1, minWin=24, winSum=394
7844 00:42:55.654469 TX Vref=24, minBit 1, minWin=24, winSum=404
7845 00:42:55.661041 TX Vref=26, minBit 1, minWin=25, winSum=406
7846 00:42:55.664158 TX Vref=28, minBit 1, minWin=25, winSum=415
7847 00:42:55.667506 TX Vref=30, minBit 8, minWin=24, winSum=414
7848 00:42:55.670623 TX Vref=32, minBit 8, minWin=23, winSum=403
7849 00:42:55.674261 TX Vref=34, minBit 7, minWin=23, winSum=390
7850 00:42:55.680672 [TxChooseVref] Worse bit 1, Min win 25, Win sum 415, Final Vref 28
7851 00:42:55.681126
7852 00:42:55.684144 Final TX Range 0 Vref 28
7853 00:42:55.684582
7854 00:42:55.684919 ==
7855 00:42:55.687566 Dram Type= 6, Freq= 0, CH_0, rank 1
7856 00:42:55.690557 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7857 00:42:55.690998 ==
7858 00:42:55.691338
7859 00:42:55.691651
7860 00:42:55.694108 TX Vref Scan disable
7861 00:42:55.700628 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
7862 00:42:55.701136 == TX Byte 0 ==
7863 00:42:55.703927 u2DelayCellOfst[0]=10 cells (3 PI)
7864 00:42:55.706973 u2DelayCellOfst[1]=18 cells (5 PI)
7865 00:42:55.710709 u2DelayCellOfst[2]=14 cells (4 PI)
7866 00:42:55.713891 u2DelayCellOfst[3]=14 cells (4 PI)
7867 00:42:55.717194 u2DelayCellOfst[4]=7 cells (2 PI)
7868 00:42:55.720347 u2DelayCellOfst[5]=0 cells (0 PI)
7869 00:42:55.723475 u2DelayCellOfst[6]=18 cells (5 PI)
7870 00:42:55.727127 u2DelayCellOfst[7]=18 cells (5 PI)
7871 00:42:55.730818 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7872 00:42:55.733729 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7873 00:42:55.737743 == TX Byte 1 ==
7874 00:42:55.740276 u2DelayCellOfst[8]=3 cells (1 PI)
7875 00:42:55.740711 u2DelayCellOfst[9]=0 cells (0 PI)
7876 00:42:55.743626 u2DelayCellOfst[10]=10 cells (3 PI)
7877 00:42:55.747107 u2DelayCellOfst[11]=7 cells (2 PI)
7878 00:42:55.750280 u2DelayCellOfst[12]=18 cells (5 PI)
7879 00:42:55.753868 u2DelayCellOfst[13]=18 cells (5 PI)
7880 00:42:55.757192 u2DelayCellOfst[14]=21 cells (6 PI)
7881 00:42:55.760284 u2DelayCellOfst[15]=18 cells (5 PI)
7882 00:42:55.766743 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
7883 00:42:55.769888 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
7884 00:42:55.770383 DramC Write-DBI on
7885 00:42:55.770732 ==
7886 00:42:55.773914 Dram Type= 6, Freq= 0, CH_0, rank 1
7887 00:42:55.779704 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7888 00:42:55.780220 ==
7889 00:42:55.780567
7890 00:42:55.780885
7891 00:42:55.781184 TX Vref Scan disable
7892 00:42:55.784138 == TX Byte 0 ==
7893 00:42:55.787365 Update DQM dly =729 (2 ,6, 25) DQM OEN =(3 ,3)
7894 00:42:55.790798 == TX Byte 1 ==
7895 00:42:55.794101 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
7896 00:42:55.797566 DramC Write-DBI off
7897 00:42:55.798091
7898 00:42:55.798478 [DATLAT]
7899 00:42:55.798802 Freq=1600, CH0 RK1
7900 00:42:55.799108
7901 00:42:55.800431 DATLAT Default: 0xe
7902 00:42:55.804125 0, 0xFFFF, sum = 0
7903 00:42:55.804658 1, 0xFFFF, sum = 0
7904 00:42:55.807029 2, 0xFFFF, sum = 0
7905 00:42:55.807482 3, 0xFFFF, sum = 0
7906 00:42:55.810323 4, 0xFFFF, sum = 0
7907 00:42:55.810767 5, 0xFFFF, sum = 0
7908 00:42:55.813897 6, 0xFFFF, sum = 0
7909 00:42:55.814482 7, 0xFFFF, sum = 0
7910 00:42:55.817200 8, 0xFFFF, sum = 0
7911 00:42:55.817729 9, 0xFFFF, sum = 0
7912 00:42:55.820294 10, 0xFFFF, sum = 0
7913 00:42:55.820876 11, 0xFFFF, sum = 0
7914 00:42:55.823470 12, 0x8FFF, sum = 0
7915 00:42:55.823912 13, 0x0, sum = 1
7916 00:42:55.827200 14, 0x0, sum = 2
7917 00:42:55.827640 15, 0x0, sum = 3
7918 00:42:55.830715 16, 0x0, sum = 4
7919 00:42:55.831158 best_step = 14
7920 00:42:55.831495
7921 00:42:55.831809 ==
7922 00:42:55.833680 Dram Type= 6, Freq= 0, CH_0, rank 1
7923 00:42:55.837071 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7924 00:42:55.840368 ==
7925 00:42:55.840804 RX Vref Scan: 0
7926 00:42:55.841147
7927 00:42:55.843799 RX Vref 0 -> 0, step: 1
7928 00:42:55.844233
7929 00:42:55.847104 RX Delay 11 -> 252, step: 4
7930 00:42:55.850504 iDelay=195, Bit 0, Center 122 (67 ~ 178) 112
7931 00:42:55.853713 iDelay=195, Bit 1, Center 132 (79 ~ 186) 108
7932 00:42:55.857544 iDelay=195, Bit 2, Center 126 (71 ~ 182) 112
7933 00:42:55.863701 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
7934 00:42:55.866849 iDelay=195, Bit 4, Center 132 (79 ~ 186) 108
7935 00:42:55.870091 iDelay=195, Bit 5, Center 118 (63 ~ 174) 112
7936 00:42:55.873419 iDelay=195, Bit 6, Center 136 (83 ~ 190) 108
7937 00:42:55.876804 iDelay=195, Bit 7, Center 138 (83 ~ 194) 112
7938 00:42:55.883560 iDelay=195, Bit 8, Center 110 (55 ~ 166) 112
7939 00:42:55.886899 iDelay=195, Bit 9, Center 106 (51 ~ 162) 112
7940 00:42:55.890364 iDelay=195, Bit 10, Center 122 (67 ~ 178) 112
7941 00:42:55.893431 iDelay=195, Bit 11, Center 112 (59 ~ 166) 108
7942 00:42:55.896807 iDelay=195, Bit 12, Center 126 (71 ~ 182) 112
7943 00:42:55.903175 iDelay=195, Bit 13, Center 128 (75 ~ 182) 108
7944 00:42:55.906681 iDelay=195, Bit 14, Center 132 (79 ~ 186) 108
7945 00:42:55.910075 iDelay=195, Bit 15, Center 130 (75 ~ 186) 112
7946 00:42:55.910558 ==
7947 00:42:55.913159 Dram Type= 6, Freq= 0, CH_0, rank 1
7948 00:42:55.916817 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7949 00:42:55.917373 ==
7950 00:42:55.919800 DQS Delay:
7951 00:42:55.920234 DQS0 = 0, DQS1 = 0
7952 00:42:55.922926 DQM Delay:
7953 00:42:55.923360 DQM0 = 128, DQM1 = 120
7954 00:42:55.926666 DQ Delay:
7955 00:42:55.929832 DQ0 =122, DQ1 =132, DQ2 =126, DQ3 =124
7956 00:42:55.933245 DQ4 =132, DQ5 =118, DQ6 =136, DQ7 =138
7957 00:42:55.936141 DQ8 =110, DQ9 =106, DQ10 =122, DQ11 =112
7958 00:42:55.939703 DQ12 =126, DQ13 =128, DQ14 =132, DQ15 =130
7959 00:42:55.940139
7960 00:42:55.940480
7961 00:42:55.940936
7962 00:42:55.942927 [DramC_TX_OE_Calibration] TA2
7963 00:42:55.946537 Original DQ_B0 (3 6) =30, OEN = 27
7964 00:42:55.949591 Original DQ_B1 (3 6) =30, OEN = 27
7965 00:42:55.950108 24, 0x0, End_B0=24 End_B1=24
7966 00:42:55.953293 25, 0x0, End_B0=25 End_B1=25
7967 00:42:55.956430 26, 0x0, End_B0=26 End_B1=26
7968 00:42:55.959516 27, 0x0, End_B0=27 End_B1=27
7969 00:42:55.963069 28, 0x0, End_B0=28 End_B1=28
7970 00:42:55.963613 29, 0x0, End_B0=29 End_B1=29
7971 00:42:55.966286 30, 0x0, End_B0=30 End_B1=30
7972 00:42:55.969370 31, 0x4141, End_B0=30 End_B1=30
7973 00:42:55.972828 Byte0 end_step=30 best_step=27
7974 00:42:55.976233 Byte1 end_step=30 best_step=27
7975 00:42:55.979248 Byte0 TX OE(2T, 0.5T) = (3, 3)
7976 00:42:55.979708 Byte1 TX OE(2T, 0.5T) = (3, 3)
7977 00:42:55.980048
7978 00:42:55.980360
7979 00:42:55.989577 [DQSOSCAuto] RK1, (LSB)MR18= 0x2323, (MSB)MR19= 0x303, tDQSOscB0 = 392 ps tDQSOscB1 = 392 ps
7980 00:42:55.992548 CH0 RK1: MR19=303, MR18=2323
7981 00:42:55.999287 CH0_RK1: MR19=0x303, MR18=0x2323, DQSOSC=392, MR23=63, INC=24, DEC=16
7982 00:42:56.002779 [RxdqsGatingPostProcess] freq 1600
7983 00:42:56.006135 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
7984 00:42:56.009133 Pre-setting of DQS Precalculation
7985 00:42:56.016194 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7986 00:42:56.016738 ==
7987 00:42:56.019350 Dram Type= 6, Freq= 0, CH_1, rank 0
7988 00:42:56.022654 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7989 00:42:56.023090 ==
7990 00:42:56.029501 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7991 00:42:56.032498 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
7992 00:42:56.036092 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
7993 00:42:56.042342 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7994 00:42:56.050345 [CA 0] Center 41 (11~71) winsize 61
7995 00:42:56.053695 [CA 1] Center 41 (11~72) winsize 62
7996 00:42:56.057044 [CA 2] Center 37 (8~67) winsize 60
7997 00:42:56.060296 [CA 3] Center 36 (6~66) winsize 61
7998 00:42:56.063376 [CA 4] Center 34 (5~64) winsize 60
7999 00:42:56.066586 [CA 5] Center 34 (5~64) winsize 60
8000 00:42:56.067031
8001 00:42:56.069937 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8002 00:42:56.070414
8003 00:42:56.073298 [CATrainingPosCal] consider 1 rank data
8004 00:42:56.076632 u2DelayCellTimex100 = 271/100 ps
8005 00:42:56.079960 CA0 delay=41 (11~71),Diff = 7 PI (25 cell)
8006 00:42:56.086350 CA1 delay=41 (11~72),Diff = 7 PI (25 cell)
8007 00:42:56.090046 CA2 delay=37 (8~67),Diff = 3 PI (10 cell)
8008 00:42:56.093220 CA3 delay=36 (6~66),Diff = 2 PI (7 cell)
8009 00:42:56.096461 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
8010 00:42:56.100083 CA5 delay=34 (5~64),Diff = 0 PI (0 cell)
8011 00:42:56.100593
8012 00:42:56.103192 CA PerBit enable=1, Macro0, CA PI delay=34
8013 00:42:56.103704
8014 00:42:56.106448 [CBTSetCACLKResult] CA Dly = 34
8015 00:42:56.109697 CS Dly: 8 (0~39)
8016 00:42:56.112901 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8017 00:42:56.116180 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8018 00:42:56.116616 ==
8019 00:42:56.119748 Dram Type= 6, Freq= 0, CH_1, rank 1
8020 00:42:56.122826 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8021 00:42:56.126494 ==
8022 00:42:56.129518 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8023 00:42:56.132886 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8024 00:42:56.139405 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8025 00:42:56.146337 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8026 00:42:56.152821 [CA 0] Center 40 (10~70) winsize 61
8027 00:42:56.155961 [CA 1] Center 39 (9~70) winsize 62
8028 00:42:56.158936 [CA 2] Center 35 (6~65) winsize 60
8029 00:42:56.162671 [CA 3] Center 35 (6~64) winsize 59
8030 00:42:56.165956 [CA 4] Center 33 (4~63) winsize 60
8031 00:42:56.168824 [CA 5] Center 33 (3~63) winsize 61
8032 00:42:56.169259
8033 00:42:56.172436 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8034 00:42:56.172872
8035 00:42:56.175919 [CATrainingPosCal] consider 2 rank data
8036 00:42:56.179203 u2DelayCellTimex100 = 271/100 ps
8037 00:42:56.182292 CA0 delay=40 (11~70),Diff = 6 PI (21 cell)
8038 00:42:56.189429 CA1 delay=40 (11~70),Diff = 6 PI (21 cell)
8039 00:42:56.192421 CA2 delay=36 (8~65),Diff = 2 PI (7 cell)
8040 00:42:56.195489 CA3 delay=35 (6~64),Diff = 1 PI (3 cell)
8041 00:42:56.198887 CA4 delay=34 (5~63),Diff = 0 PI (0 cell)
8042 00:42:56.201883 CA5 delay=34 (5~63),Diff = 0 PI (0 cell)
8043 00:42:56.202552
8044 00:42:56.205244 CA PerBit enable=1, Macro0, CA PI delay=34
8045 00:42:56.205678
8046 00:42:56.208874 [CBTSetCACLKResult] CA Dly = 34
8047 00:42:56.212209 CS Dly: 9 (0~41)
8048 00:42:56.215263 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8049 00:42:56.218558 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8050 00:42:56.218987
8051 00:42:56.222199 ----->DramcWriteLeveling(PI) begin...
8052 00:42:56.222761 ==
8053 00:42:56.225177 Dram Type= 6, Freq= 0, CH_1, rank 0
8054 00:42:56.231500 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8055 00:42:56.232030 ==
8056 00:42:56.235150 Write leveling (Byte 0): 23 => 23
8057 00:42:56.235590 Write leveling (Byte 1): 22 => 22
8058 00:42:56.238346 DramcWriteLeveling(PI) end<-----
8059 00:42:56.238959
8060 00:42:56.239481 ==
8061 00:42:56.241826 Dram Type= 6, Freq= 0, CH_1, rank 0
8062 00:42:56.248668 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8063 00:42:56.249188 ==
8064 00:42:56.251574 [Gating] SW mode calibration
8065 00:42:56.258390 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8066 00:42:56.261866 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8067 00:42:56.268311 0 12 0 | B1->B0 | 2a2a 3434 | 1 1 | (1 1) (1 1)
8068 00:42:56.271346 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8069 00:42:56.274597 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8070 00:42:56.281589 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8071 00:42:56.284624 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8072 00:42:56.287989 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8073 00:42:56.294690 0 12 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
8074 00:42:56.298322 0 12 28 | B1->B0 | 3434 2323 | 1 0 | (1 0) (1 0)
8075 00:42:56.301892 0 13 0 | B1->B0 | 3030 2323 | 0 0 | (0 1) (0 0)
8076 00:42:56.308229 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8077 00:42:56.311917 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8078 00:42:56.314744 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8079 00:42:56.321306 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8080 00:42:56.324882 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8081 00:42:56.327911 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8082 00:42:56.331781 0 13 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8083 00:42:56.338085 0 14 0 | B1->B0 | 2a2a 4646 | 1 0 | (0 0) (0 0)
8084 00:42:56.341589 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8085 00:42:56.345335 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8086 00:42:56.351182 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8087 00:42:56.354636 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8088 00:42:56.358073 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8089 00:42:56.364452 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8090 00:42:56.367923 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8091 00:42:56.371248 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8092 00:42:56.377691 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8093 00:42:56.381002 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8094 00:42:56.384394 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8095 00:42:56.390968 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8096 00:42:56.394461 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8097 00:42:56.397852 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8098 00:42:56.404461 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8099 00:42:56.407801 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8100 00:42:56.410850 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8101 00:42:56.417313 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8102 00:42:56.420656 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8103 00:42:56.424041 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8104 00:42:56.430845 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8105 00:42:56.433938 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8106 00:42:56.437387 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8107 00:42:56.443999 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8108 00:42:56.444504 Total UI for P1: 0, mck2ui 16
8109 00:42:56.450464 best dqsien dly found for B0: ( 1, 0, 24)
8110 00:42:56.454046 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8111 00:42:56.457834 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8112 00:42:56.460637 Total UI for P1: 0, mck2ui 16
8113 00:42:56.463782 best dqsien dly found for B1: ( 1, 1, 0)
8114 00:42:56.466864 best DQS0 dly(MCK, UI, PI) = (1, 0, 24)
8115 00:42:56.470583 best DQS1 dly(MCK, UI, PI) = (1, 1, 0)
8116 00:42:56.471019
8117 00:42:56.473851 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 24)
8118 00:42:56.480453 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 0)
8119 00:42:56.480952 [Gating] SW calibration Done
8120 00:42:56.481287 ==
8121 00:42:56.483635 Dram Type= 6, Freq= 0, CH_1, rank 0
8122 00:42:56.490461 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8123 00:42:56.490892 ==
8124 00:42:56.491281 RX Vref Scan: 0
8125 00:42:56.491599
8126 00:42:56.494190 RX Vref 0 -> 0, step: 1
8127 00:42:56.494792
8128 00:42:56.497176 RX Delay 0 -> 252, step: 8
8129 00:42:56.500331 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8130 00:42:56.503894 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8131 00:42:56.506867 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8132 00:42:56.513713 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8133 00:42:56.516820 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8134 00:42:56.520161 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8135 00:42:56.523718 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
8136 00:42:56.526594 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8137 00:42:56.533457 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8138 00:42:56.536638 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8139 00:42:56.540053 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8140 00:42:56.543221 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8141 00:42:56.546593 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8142 00:42:56.553444 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8143 00:42:56.556379 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8144 00:42:56.559814 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8145 00:42:56.560243 ==
8146 00:42:56.563103 Dram Type= 6, Freq= 0, CH_1, rank 0
8147 00:42:56.566419 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8148 00:42:56.566855 ==
8149 00:42:56.569717 DQS Delay:
8150 00:42:56.570349 DQS0 = 0, DQS1 = 0
8151 00:42:56.572949 DQM Delay:
8152 00:42:56.573537 DQM0 = 131, DQM1 = 125
8153 00:42:56.576253 DQ Delay:
8154 00:42:56.579809 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =127
8155 00:42:56.583128 DQ4 =131, DQ5 =143, DQ6 =139, DQ7 =127
8156 00:42:56.586111 DQ8 =107, DQ9 =115, DQ10 =123, DQ11 =115
8157 00:42:56.589581 DQ12 =135, DQ13 =139, DQ14 =131, DQ15 =135
8158 00:42:56.589971
8159 00:42:56.590306
8160 00:42:56.590593 ==
8161 00:42:56.593167 Dram Type= 6, Freq= 0, CH_1, rank 0
8162 00:42:56.596274 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8163 00:42:56.596674 ==
8164 00:42:56.596981
8165 00:42:56.597259
8166 00:42:56.599506 TX Vref Scan disable
8167 00:42:56.603117 == TX Byte 0 ==
8168 00:42:56.606304 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8169 00:42:56.609513 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
8170 00:42:56.612897 == TX Byte 1 ==
8171 00:42:56.616260 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8172 00:42:56.619510 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8173 00:42:56.620171 ==
8174 00:42:56.622690 Dram Type= 6, Freq= 0, CH_1, rank 0
8175 00:42:56.629517 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8176 00:42:56.630025 ==
8177 00:42:56.640357
8178 00:42:56.643951 TX Vref early break, caculate TX vref
8179 00:42:56.647077 TX Vref=16, minBit 3, minWin=21, winSum=369
8180 00:42:56.650747 TX Vref=18, minBit 3, minWin=22, winSum=378
8181 00:42:56.653689 TX Vref=20, minBit 0, minWin=23, winSum=385
8182 00:42:56.656826 TX Vref=22, minBit 3, minWin=23, winSum=395
8183 00:42:56.660084 TX Vref=24, minBit 0, minWin=24, winSum=401
8184 00:42:56.666708 TX Vref=26, minBit 3, minWin=24, winSum=413
8185 00:42:56.670047 TX Vref=28, minBit 3, minWin=24, winSum=413
8186 00:42:56.673570 TX Vref=30, minBit 3, minWin=24, winSum=408
8187 00:42:56.677094 TX Vref=32, minBit 7, minWin=23, winSum=397
8188 00:42:56.680062 TX Vref=34, minBit 1, minWin=23, winSum=387
8189 00:42:56.686537 [TxChooseVref] Worse bit 3, Min win 24, Win sum 413, Final Vref 26
8190 00:42:56.686935
8191 00:42:56.689862 Final TX Range 0 Vref 26
8192 00:42:56.690294
8193 00:42:56.690608 ==
8194 00:42:56.693102 Dram Type= 6, Freq= 0, CH_1, rank 0
8195 00:42:56.696494 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8196 00:42:56.696978 ==
8197 00:42:56.697289
8198 00:42:56.697570
8199 00:42:56.700039 TX Vref Scan disable
8200 00:42:56.706539 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8201 00:42:56.707056 == TX Byte 0 ==
8202 00:42:56.709710 u2DelayCellOfst[0]=18 cells (5 PI)
8203 00:42:56.713038 u2DelayCellOfst[1]=14 cells (4 PI)
8204 00:42:56.716682 u2DelayCellOfst[2]=0 cells (0 PI)
8205 00:42:56.719894 u2DelayCellOfst[3]=7 cells (2 PI)
8206 00:42:56.722971 u2DelayCellOfst[4]=10 cells (3 PI)
8207 00:42:56.726553 u2DelayCellOfst[5]=18 cells (5 PI)
8208 00:42:56.729858 u2DelayCellOfst[6]=18 cells (5 PI)
8209 00:42:56.733271 u2DelayCellOfst[7]=10 cells (3 PI)
8210 00:42:56.736633 Update DQ dly =974 (3 ,6, 14) DQ OEN =(3 ,3)
8211 00:42:56.739654 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8212 00:42:56.743176 == TX Byte 1 ==
8213 00:42:56.743619 u2DelayCellOfst[8]=0 cells (0 PI)
8214 00:42:56.746447 u2DelayCellOfst[9]=3 cells (1 PI)
8215 00:42:56.749383 u2DelayCellOfst[10]=10 cells (3 PI)
8216 00:42:56.752849 u2DelayCellOfst[11]=3 cells (1 PI)
8217 00:42:56.756275 u2DelayCellOfst[12]=18 cells (5 PI)
8218 00:42:56.759381 u2DelayCellOfst[13]=18 cells (5 PI)
8219 00:42:56.763237 u2DelayCellOfst[14]=21 cells (6 PI)
8220 00:42:56.766386 u2DelayCellOfst[15]=18 cells (5 PI)
8221 00:42:56.769333 Update DQ dly =973 (3 ,6, 13) DQ OEN =(3 ,3)
8222 00:42:56.776197 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8223 00:42:56.776465 DramC Write-DBI on
8224 00:42:56.776646 ==
8225 00:42:56.778987 Dram Type= 6, Freq= 0, CH_1, rank 0
8226 00:42:56.785526 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8227 00:42:56.785730 ==
8228 00:42:56.785851
8229 00:42:56.785959
8230 00:42:56.786064 TX Vref Scan disable
8231 00:42:56.789566 == TX Byte 0 ==
8232 00:42:56.792532 Update DQM dly =719 (2 ,6, 15) DQM OEN =(3 ,3)
8233 00:42:56.796014 == TX Byte 1 ==
8234 00:42:56.799172 Update DQM dly =716 (2 ,6, 12) DQM OEN =(3 ,3)
8235 00:42:56.799336 DramC Write-DBI off
8236 00:42:56.802522
8237 00:42:56.802676 [DATLAT]
8238 00:42:56.802789 Freq=1600, CH1 RK0
8239 00:42:56.802897
8240 00:42:56.806150 DATLAT Default: 0xf
8241 00:42:56.806281 0, 0xFFFF, sum = 0
8242 00:42:56.809498 1, 0xFFFF, sum = 0
8243 00:42:56.809609 2, 0xFFFF, sum = 0
8244 00:42:56.812635 3, 0xFFFF, sum = 0
8245 00:42:56.815861 4, 0xFFFF, sum = 0
8246 00:42:56.815969 5, 0xFFFF, sum = 0
8247 00:42:56.819449 6, 0xFFFF, sum = 0
8248 00:42:56.819620 7, 0xFFFF, sum = 0
8249 00:42:56.822401 8, 0xFFFF, sum = 0
8250 00:42:56.822541 9, 0xFFFF, sum = 0
8251 00:42:56.825706 10, 0xFFFF, sum = 0
8252 00:42:56.825824 11, 0xFFFF, sum = 0
8253 00:42:56.829178 12, 0x8FFF, sum = 0
8254 00:42:56.829260 13, 0x0, sum = 1
8255 00:42:56.832299 14, 0x0, sum = 2
8256 00:42:56.832406 15, 0x0, sum = 3
8257 00:42:56.836061 16, 0x0, sum = 4
8258 00:42:56.836571 best_step = 14
8259 00:42:56.836911
8260 00:42:56.837225 ==
8261 00:42:56.839734 Dram Type= 6, Freq= 0, CH_1, rank 0
8262 00:42:56.842596 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8263 00:42:56.846050 ==
8264 00:42:56.846469 RX Vref Scan: 1
8265 00:42:56.846776
8266 00:42:56.849284 Set Vref Range= 24 -> 127
8267 00:42:56.849673
8268 00:42:56.849979 RX Vref 24 -> 127, step: 1
8269 00:42:56.852550
8270 00:42:56.852942 RX Delay 3 -> 252, step: 4
8271 00:42:56.853252
8272 00:42:56.855874 Set Vref, RX VrefLevel [Byte0]: 24
8273 00:42:56.859104 [Byte1]: 24
8274 00:42:56.862666
8275 00:42:56.863061 Set Vref, RX VrefLevel [Byte0]: 25
8276 00:42:56.866137 [Byte1]: 25
8277 00:42:56.870499
8278 00:42:56.870906 Set Vref, RX VrefLevel [Byte0]: 26
8279 00:42:56.873615 [Byte1]: 26
8280 00:42:56.878192
8281 00:42:56.878632 Set Vref, RX VrefLevel [Byte0]: 27
8282 00:42:56.881222 [Byte1]: 27
8283 00:42:56.885679
8284 00:42:56.886070 Set Vref, RX VrefLevel [Byte0]: 28
8285 00:42:56.889020 [Byte1]: 28
8286 00:42:56.893419
8287 00:42:56.896642 Set Vref, RX VrefLevel [Byte0]: 29
8288 00:42:56.897035 [Byte1]: 29
8289 00:42:56.901006
8290 00:42:56.901406 Set Vref, RX VrefLevel [Byte0]: 30
8291 00:42:56.904302 [Byte1]: 30
8292 00:42:56.908649
8293 00:42:56.908863 Set Vref, RX VrefLevel [Byte0]: 31
8294 00:42:56.911714 [Byte1]: 31
8295 00:42:56.916125
8296 00:42:56.916335 Set Vref, RX VrefLevel [Byte0]: 32
8297 00:42:56.919267 [Byte1]: 32
8298 00:42:56.923780
8299 00:42:56.923902 Set Vref, RX VrefLevel [Byte0]: 33
8300 00:42:56.927068 [Byte1]: 33
8301 00:42:56.931395
8302 00:42:56.931506 Set Vref, RX VrefLevel [Byte0]: 34
8303 00:42:56.934666 [Byte1]: 34
8304 00:42:56.938990
8305 00:42:56.939087 Set Vref, RX VrefLevel [Byte0]: 35
8306 00:42:56.942310 [Byte1]: 35
8307 00:42:56.946707
8308 00:42:56.946788 Set Vref, RX VrefLevel [Byte0]: 36
8309 00:42:56.949941 [Byte1]: 36
8310 00:42:56.954184
8311 00:42:56.954315 Set Vref, RX VrefLevel [Byte0]: 37
8312 00:42:56.957915 [Byte1]: 37
8313 00:42:56.961834
8314 00:42:56.961910 Set Vref, RX VrefLevel [Byte0]: 38
8315 00:42:56.965183 [Byte1]: 38
8316 00:42:56.969470
8317 00:42:56.969572 Set Vref, RX VrefLevel [Byte0]: 39
8318 00:42:56.972740 [Byte1]: 39
8319 00:42:56.977209
8320 00:42:56.977288 Set Vref, RX VrefLevel [Byte0]: 40
8321 00:42:56.980533 [Byte1]: 40
8322 00:42:56.984729
8323 00:42:56.984806 Set Vref, RX VrefLevel [Byte0]: 41
8324 00:42:56.988151 [Byte1]: 41
8325 00:42:56.992412
8326 00:42:56.992487 Set Vref, RX VrefLevel [Byte0]: 42
8327 00:42:56.995723 [Byte1]: 42
8328 00:42:57.000146
8329 00:42:57.000228 Set Vref, RX VrefLevel [Byte0]: 43
8330 00:42:57.003440 [Byte1]: 43
8331 00:42:57.008182
8332 00:42:57.008265 Set Vref, RX VrefLevel [Byte0]: 44
8333 00:42:57.011390 [Byte1]: 44
8334 00:42:57.015362
8335 00:42:57.015441 Set Vref, RX VrefLevel [Byte0]: 45
8336 00:42:57.018779 [Byte1]: 45
8337 00:42:57.023289
8338 00:42:57.023378 Set Vref, RX VrefLevel [Byte0]: 46
8339 00:42:57.026368 [Byte1]: 46
8340 00:42:57.030894
8341 00:42:57.030976 Set Vref, RX VrefLevel [Byte0]: 47
8342 00:42:57.034452 [Byte1]: 47
8343 00:42:57.038462
8344 00:42:57.038550 Set Vref, RX VrefLevel [Byte0]: 48
8345 00:42:57.041816 [Byte1]: 48
8346 00:42:57.046169
8347 00:42:57.046302 Set Vref, RX VrefLevel [Byte0]: 49
8348 00:42:57.049464 [Byte1]: 49
8349 00:42:57.054221
8350 00:42:57.054400 Set Vref, RX VrefLevel [Byte0]: 50
8351 00:42:57.057592 [Byte1]: 50
8352 00:42:57.061491
8353 00:42:57.061602 Set Vref, RX VrefLevel [Byte0]: 51
8354 00:42:57.065480 [Byte1]: 51
8355 00:42:57.069239
8356 00:42:57.069381 Set Vref, RX VrefLevel [Byte0]: 52
8357 00:42:57.072572 [Byte1]: 52
8358 00:42:57.077250
8359 00:42:57.077636 Set Vref, RX VrefLevel [Byte0]: 53
8360 00:42:57.080957 [Byte1]: 53
8361 00:42:57.084738
8362 00:42:57.085127 Set Vref, RX VrefLevel [Byte0]: 54
8363 00:42:57.088014 [Byte1]: 54
8364 00:42:57.092492
8365 00:42:57.092894 Set Vref, RX VrefLevel [Byte0]: 55
8366 00:42:57.095732 [Byte1]: 55
8367 00:42:57.100533
8368 00:42:57.101011 Set Vref, RX VrefLevel [Byte0]: 56
8369 00:42:57.103742 [Byte1]: 56
8370 00:42:57.107896
8371 00:42:57.108434 Set Vref, RX VrefLevel [Byte0]: 57
8372 00:42:57.110859 [Byte1]: 57
8373 00:42:57.115613
8374 00:42:57.116042 Set Vref, RX VrefLevel [Byte0]: 58
8375 00:42:57.118750 [Byte1]: 58
8376 00:42:57.123058
8377 00:42:57.123492 Set Vref, RX VrefLevel [Byte0]: 59
8378 00:42:57.126422 [Byte1]: 59
8379 00:42:57.130707
8380 00:42:57.131093 Set Vref, RX VrefLevel [Byte0]: 60
8381 00:42:57.133845 [Byte1]: 60
8382 00:42:57.138256
8383 00:42:57.138693 Set Vref, RX VrefLevel [Byte0]: 61
8384 00:42:57.141884 [Byte1]: 61
8385 00:42:57.146282
8386 00:42:57.146691 Set Vref, RX VrefLevel [Byte0]: 62
8387 00:42:57.149392 [Byte1]: 62
8388 00:42:57.153660
8389 00:42:57.154049 Set Vref, RX VrefLevel [Byte0]: 63
8390 00:42:57.157463 [Byte1]: 63
8391 00:42:57.161479
8392 00:42:57.161872 Set Vref, RX VrefLevel [Byte0]: 64
8393 00:42:57.164428 [Byte1]: 64
8394 00:42:57.169096
8395 00:42:57.169485 Set Vref, RX VrefLevel [Byte0]: 65
8396 00:42:57.172209 [Byte1]: 65
8397 00:42:57.176968
8398 00:42:57.177440 Set Vref, RX VrefLevel [Byte0]: 66
8399 00:42:57.179987 [Byte1]: 66
8400 00:42:57.184266
8401 00:42:57.184699 Set Vref, RX VrefLevel [Byte0]: 67
8402 00:42:57.187741 [Byte1]: 67
8403 00:42:57.192069
8404 00:42:57.192500 Set Vref, RX VrefLevel [Byte0]: 68
8405 00:42:57.195467 [Byte1]: 68
8406 00:42:57.200043
8407 00:42:57.200557 Set Vref, RX VrefLevel [Byte0]: 69
8408 00:42:57.203425 [Byte1]: 69
8409 00:42:57.207743
8410 00:42:57.208258 Set Vref, RX VrefLevel [Byte0]: 70
8411 00:42:57.210854 [Byte1]: 70
8412 00:42:57.215265
8413 00:42:57.215712 Set Vref, RX VrefLevel [Byte0]: 71
8414 00:42:57.218355 [Byte1]: 71
8415 00:42:57.222415
8416 00:42:57.222848 Set Vref, RX VrefLevel [Byte0]: 72
8417 00:42:57.225950 [Byte1]: 72
8418 00:42:57.230380
8419 00:42:57.230812 Set Vref, RX VrefLevel [Byte0]: 73
8420 00:42:57.233699 [Byte1]: 73
8421 00:42:57.237930
8422 00:42:57.238407 Final RX Vref Byte 0 = 59 to rank0
8423 00:42:57.241695 Final RX Vref Byte 1 = 54 to rank0
8424 00:42:57.244898 Final RX Vref Byte 0 = 59 to rank1
8425 00:42:57.247992 Final RX Vref Byte 1 = 54 to rank1==
8426 00:42:57.251487 Dram Type= 6, Freq= 0, CH_1, rank 0
8427 00:42:57.258024 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8428 00:42:57.258593 ==
8429 00:42:57.258943 DQS Delay:
8430 00:42:57.259258 DQS0 = 0, DQS1 = 0
8431 00:42:57.261402 DQM Delay:
8432 00:42:57.261923 DQM0 = 129, DQM1 = 122
8433 00:42:57.264212 DQ Delay:
8434 00:42:57.267800 DQ0 =132, DQ1 =124, DQ2 =116, DQ3 =126
8435 00:42:57.270719 DQ4 =130, DQ5 =140, DQ6 =138, DQ7 =126
8436 00:42:57.274545 DQ8 =104, DQ9 =114, DQ10 =124, DQ11 =110
8437 00:42:57.277722 DQ12 =130, DQ13 =134, DQ14 =132, DQ15 =132
8438 00:42:57.278282
8439 00:42:57.278637
8440 00:42:57.278955
8441 00:42:57.280941 [DramC_TX_OE_Calibration] TA2
8442 00:42:57.284004 Original DQ_B0 (3 6) =30, OEN = 27
8443 00:42:57.287458 Original DQ_B1 (3 6) =30, OEN = 27
8444 00:42:57.290649 24, 0x0, End_B0=24 End_B1=24
8445 00:42:57.291100 25, 0x0, End_B0=25 End_B1=25
8446 00:42:57.293913 26, 0x0, End_B0=26 End_B1=26
8447 00:42:57.297413 27, 0x0, End_B0=27 End_B1=27
8448 00:42:57.300737 28, 0x0, End_B0=28 End_B1=28
8449 00:42:57.304185 29, 0x0, End_B0=29 End_B1=29
8450 00:42:57.304632 30, 0x0, End_B0=30 End_B1=30
8451 00:42:57.307753 31, 0x4141, End_B0=30 End_B1=30
8452 00:42:57.311080 Byte0 end_step=30 best_step=27
8453 00:42:57.314171 Byte1 end_step=30 best_step=27
8454 00:42:57.317442 Byte0 TX OE(2T, 0.5T) = (3, 3)
8455 00:42:57.320616 Byte1 TX OE(2T, 0.5T) = (3, 3)
8456 00:42:57.321056
8457 00:42:57.321398
8458 00:42:57.327117 [DQSOSCAuto] RK0, (LSB)MR18= 0x2b2b, (MSB)MR19= 0x303, tDQSOscB0 = 388 ps tDQSOscB1 = 388 ps
8459 00:42:57.330739 CH1 RK0: MR19=303, MR18=2B2B
8460 00:42:57.337252 CH1_RK0: MR19=0x303, MR18=0x2B2B, DQSOSC=388, MR23=63, INC=24, DEC=16
8461 00:42:57.337985
8462 00:42:57.340324 ----->DramcWriteLeveling(PI) begin...
8463 00:42:57.340960 ==
8464 00:42:57.343430 Dram Type= 6, Freq= 0, CH_1, rank 1
8465 00:42:57.346979 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8466 00:42:57.347490 ==
8467 00:42:57.350283 Write leveling (Byte 0): 20 => 20
8468 00:42:57.353841 Write leveling (Byte 1): 20 => 20
8469 00:42:57.357113 DramcWriteLeveling(PI) end<-----
8470 00:42:57.357625
8471 00:42:57.357965 ==
8472 00:42:57.360969 Dram Type= 6, Freq= 0, CH_1, rank 1
8473 00:42:57.363810 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8474 00:42:57.364334 ==
8475 00:42:57.366913 [Gating] SW mode calibration
8476 00:42:57.373526 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8477 00:42:57.380156 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8478 00:42:57.383655 0 12 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
8479 00:42:57.390855 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8480 00:42:57.393640 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8481 00:42:57.396938 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8482 00:42:57.403667 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8483 00:42:57.407025 0 12 20 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
8484 00:42:57.410326 0 12 24 | B1->B0 | 3434 2a2a | 1 0 | (1 1) (0 0)
8485 00:42:57.416964 0 12 28 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8486 00:42:57.420026 0 13 0 | B1->B0 | 2626 2323 | 0 0 | (0 1) (0 0)
8487 00:42:57.423219 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8488 00:42:57.429789 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8489 00:42:57.433384 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8490 00:42:57.436451 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8491 00:42:57.443019 0 13 20 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8492 00:42:57.446760 0 13 24 | B1->B0 | 2323 3636 | 0 0 | (0 0) (0 0)
8493 00:42:57.450277 0 13 28 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
8494 00:42:57.453268 0 14 0 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
8495 00:42:57.459793 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8496 00:42:57.463218 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8497 00:42:57.466648 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8498 00:42:57.473431 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8499 00:42:57.476293 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8500 00:42:57.479938 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8501 00:42:57.486446 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8502 00:42:57.489922 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8503 00:42:57.493250 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8504 00:42:57.499608 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8505 00:42:57.503173 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8506 00:42:57.506302 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8507 00:42:57.512748 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8508 00:42:57.516085 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8509 00:42:57.519410 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8510 00:42:57.526362 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8511 00:42:57.529697 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8512 00:42:57.532739 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8513 00:42:57.539296 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8514 00:42:57.542725 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8515 00:42:57.545940 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8516 00:42:57.552303 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8517 00:42:57.555697 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8518 00:42:57.559004 Total UI for P1: 0, mck2ui 16
8519 00:42:57.562254 best dqsien dly found for B0: ( 1, 0, 22)
8520 00:42:57.565901 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8521 00:42:57.572439 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8522 00:42:57.572968 Total UI for P1: 0, mck2ui 16
8523 00:42:57.578929 best dqsien dly found for B1: ( 1, 0, 28)
8524 00:42:57.582312 best DQS0 dly(MCK, UI, PI) = (1, 0, 22)
8525 00:42:57.586020 best DQS1 dly(MCK, UI, PI) = (1, 0, 28)
8526 00:42:57.586643
8527 00:42:57.589066 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 22)
8528 00:42:57.591872 best DQS1 P1 dly(MCK, UI, PI) = (1, 4, 28)
8529 00:42:57.595411 [Gating] SW calibration Done
8530 00:42:57.595843 ==
8531 00:42:57.598854 Dram Type= 6, Freq= 0, CH_1, rank 1
8532 00:42:57.602261 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8533 00:42:57.602718 ==
8534 00:42:57.605984 RX Vref Scan: 0
8535 00:42:57.606560
8536 00:42:57.606910 RX Vref 0 -> 0, step: 1
8537 00:42:57.607226
8538 00:42:57.608629 RX Delay 0 -> 252, step: 8
8539 00:42:57.611928 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8540 00:42:57.618557 iDelay=200, Bit 1, Center 123 (64 ~ 183) 120
8541 00:42:57.622256 iDelay=200, Bit 2, Center 115 (56 ~ 175) 120
8542 00:42:57.625388 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8543 00:42:57.628673 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8544 00:42:57.632186 iDelay=200, Bit 5, Center 139 (80 ~ 199) 120
8545 00:42:57.638446 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8546 00:42:57.642099 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8547 00:42:57.646104 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8548 00:42:57.648508 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8549 00:42:57.651831 iDelay=200, Bit 10, Center 127 (64 ~ 191) 128
8550 00:42:57.658597 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8551 00:42:57.662335 iDelay=200, Bit 12, Center 135 (72 ~ 199) 128
8552 00:42:57.665796 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8553 00:42:57.668459 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8554 00:42:57.675239 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8555 00:42:57.675767 ==
8556 00:42:57.678583 Dram Type= 6, Freq= 0, CH_1, rank 1
8557 00:42:57.681951 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8558 00:42:57.682599 ==
8559 00:42:57.682949 DQS Delay:
8560 00:42:57.684925 DQS0 = 0, DQS1 = 0
8561 00:42:57.685353 DQM Delay:
8562 00:42:57.688577 DQM0 = 129, DQM1 = 125
8563 00:42:57.689007 DQ Delay:
8564 00:42:57.691650 DQ0 =131, DQ1 =123, DQ2 =115, DQ3 =131
8565 00:42:57.695452 DQ4 =131, DQ5 =139, DQ6 =139, DQ7 =127
8566 00:42:57.698571 DQ8 =107, DQ9 =115, DQ10 =127, DQ11 =115
8567 00:42:57.701922 DQ12 =135, DQ13 =139, DQ14 =131, DQ15 =131
8568 00:42:57.702472
8569 00:42:57.702816
8570 00:42:57.703123 ==
8571 00:42:57.705547 Dram Type= 6, Freq= 0, CH_1, rank 1
8572 00:42:57.711463 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8573 00:42:57.712014 ==
8574 00:42:57.712374
8575 00:42:57.712686
8576 00:42:57.714730 TX Vref Scan disable
8577 00:42:57.715169 == TX Byte 0 ==
8578 00:42:57.718278 Update DQ dly =974 (3 ,6, 14) DQ OEN =(3 ,3)
8579 00:42:57.724647 Update DQM dly =974 (3 ,6, 14) DQM OEN =(3 ,3)
8580 00:42:57.725151 == TX Byte 1 ==
8581 00:42:57.727919 Update DQ dly =974 (3 ,6, 14) DQ OEN =(3 ,3)
8582 00:42:57.734746 Update DQM dly =974 (3 ,6, 14) DQM OEN =(3 ,3)
8583 00:42:57.735189 ==
8584 00:42:57.737823 Dram Type= 6, Freq= 0, CH_1, rank 1
8585 00:42:57.741356 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8586 00:42:57.741799 ==
8587 00:42:57.754686
8588 00:42:57.757980 TX Vref early break, caculate TX vref
8589 00:42:57.761444 TX Vref=16, minBit 7, minWin=22, winSum=386
8590 00:42:57.764552 TX Vref=18, minBit 3, minWin=23, winSum=392
8591 00:42:57.767834 TX Vref=20, minBit 3, minWin=23, winSum=401
8592 00:42:57.771123 TX Vref=22, minBit 0, minWin=24, winSum=409
8593 00:42:57.774744 TX Vref=24, minBit 7, minWin=24, winSum=415
8594 00:42:57.781043 TX Vref=26, minBit 0, minWin=26, winSum=424
8595 00:42:57.784437 TX Vref=28, minBit 2, minWin=25, winSum=421
8596 00:42:57.787909 TX Vref=30, minBit 3, minWin=25, winSum=420
8597 00:42:57.791182 TX Vref=32, minBit 0, minWin=24, winSum=415
8598 00:42:57.795058 TX Vref=34, minBit 0, minWin=23, winSum=406
8599 00:42:57.797847 TX Vref=36, minBit 0, minWin=24, winSum=400
8600 00:42:57.804332 [TxChooseVref] Worse bit 0, Min win 26, Win sum 424, Final Vref 26
8601 00:42:57.804727
8602 00:42:57.807649 Final TX Range 0 Vref 26
8603 00:42:57.808063
8604 00:42:57.808372 ==
8605 00:42:57.810981 Dram Type= 6, Freq= 0, CH_1, rank 1
8606 00:42:57.814283 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8607 00:42:57.814695 ==
8608 00:42:57.815009
8609 00:42:57.817661
8610 00:42:57.818051 TX Vref Scan disable
8611 00:42:57.824416 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8612 00:42:57.824825 == TX Byte 0 ==
8613 00:42:57.827732 u2DelayCellOfst[0]=14 cells (4 PI)
8614 00:42:57.830676 u2DelayCellOfst[1]=7 cells (2 PI)
8615 00:42:57.834278 u2DelayCellOfst[2]=0 cells (0 PI)
8616 00:42:57.837787 u2DelayCellOfst[3]=7 cells (2 PI)
8617 00:42:57.840656 u2DelayCellOfst[4]=10 cells (3 PI)
8618 00:42:57.843889 u2DelayCellOfst[5]=14 cells (4 PI)
8619 00:42:57.847191 u2DelayCellOfst[6]=14 cells (4 PI)
8620 00:42:57.850753 u2DelayCellOfst[7]=7 cells (2 PI)
8621 00:42:57.854095 Update DQ dly =972 (3 ,6, 12) DQ OEN =(3 ,3)
8622 00:42:57.857607 Update DQM dly =974 (3 ,6, 14) DQM OEN =(3 ,3)
8623 00:42:57.860973 == TX Byte 1 ==
8624 00:42:57.864289 u2DelayCellOfst[8]=0 cells (0 PI)
8625 00:42:57.864799 u2DelayCellOfst[9]=3 cells (1 PI)
8626 00:42:57.867525 u2DelayCellOfst[10]=10 cells (3 PI)
8627 00:42:57.871047 u2DelayCellOfst[11]=3 cells (1 PI)
8628 00:42:57.874246 u2DelayCellOfst[12]=14 cells (4 PI)
8629 00:42:57.877625 u2DelayCellOfst[13]=18 cells (5 PI)
8630 00:42:57.880843 u2DelayCellOfst[14]=14 cells (4 PI)
8631 00:42:57.884095 u2DelayCellOfst[15]=14 cells (4 PI)
8632 00:42:57.887740 Update DQ dly =972 (3 ,6, 12) DQ OEN =(3 ,3)
8633 00:42:57.894200 Update DQM dly =974 (3 ,6, 14) DQM OEN =(3 ,3)
8634 00:42:57.894644 DramC Write-DBI on
8635 00:42:57.894957 ==
8636 00:42:57.897424 Dram Type= 6, Freq= 0, CH_1, rank 1
8637 00:42:57.903883 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8638 00:42:57.904409 ==
8639 00:42:57.904882
8640 00:42:57.905305
8641 00:42:57.905718 TX Vref Scan disable
8642 00:42:57.907352 == TX Byte 0 ==
8643 00:42:57.910816 Update DQM dly =716 (2 ,6, 12) DQM OEN =(3 ,3)
8644 00:42:57.914592 == TX Byte 1 ==
8645 00:42:57.917459 Update DQM dly =715 (2 ,6, 11) DQM OEN =(3 ,3)
8646 00:42:57.920629 DramC Write-DBI off
8647 00:42:57.921036
8648 00:42:57.921477 [DATLAT]
8649 00:42:57.921777 Freq=1600, CH1 RK1
8650 00:42:57.922069
8651 00:42:57.924313 DATLAT Default: 0xe
8652 00:42:57.927401 0, 0xFFFF, sum = 0
8653 00:42:57.928050 1, 0xFFFF, sum = 0
8654 00:42:57.930903 2, 0xFFFF, sum = 0
8655 00:42:57.931495 3, 0xFFFF, sum = 0
8656 00:42:57.933867 4, 0xFFFF, sum = 0
8657 00:42:57.934302 5, 0xFFFF, sum = 0
8658 00:42:57.937331 6, 0xFFFF, sum = 0
8659 00:42:57.937813 7, 0xFFFF, sum = 0
8660 00:42:57.940665 8, 0xFFFF, sum = 0
8661 00:42:57.941066 9, 0xFFFF, sum = 0
8662 00:42:57.943979 10, 0xFFFF, sum = 0
8663 00:42:57.944420 11, 0xFFFF, sum = 0
8664 00:42:57.947610 12, 0x8F7F, sum = 0
8665 00:42:57.948008 13, 0x0, sum = 1
8666 00:42:57.950397 14, 0x0, sum = 2
8667 00:42:57.950800 15, 0x0, sum = 3
8668 00:42:57.953913 16, 0x0, sum = 4
8669 00:42:57.954351 best_step = 14
8670 00:42:57.954668
8671 00:42:57.954952 ==
8672 00:42:57.957417 Dram Type= 6, Freq= 0, CH_1, rank 1
8673 00:42:57.964215 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8674 00:42:57.964692 ==
8675 00:42:57.965016 RX Vref Scan: 0
8676 00:42:57.965302
8677 00:42:57.967281 RX Vref 0 -> 0, step: 1
8678 00:42:57.967678
8679 00:42:57.970267 RX Delay 3 -> 252, step: 4
8680 00:42:57.974015 iDelay=195, Bit 0, Center 128 (75 ~ 182) 108
8681 00:42:57.977237 iDelay=195, Bit 1, Center 122 (67 ~ 178) 112
8682 00:42:57.980476 iDelay=195, Bit 2, Center 116 (63 ~ 170) 108
8683 00:42:57.986898 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
8684 00:42:57.990114 iDelay=195, Bit 4, Center 126 (71 ~ 182) 112
8685 00:42:57.993761 iDelay=195, Bit 5, Center 138 (83 ~ 194) 112
8686 00:42:57.996787 iDelay=195, Bit 6, Center 136 (83 ~ 190) 108
8687 00:42:58.000279 iDelay=195, Bit 7, Center 126 (71 ~ 182) 112
8688 00:42:58.006912 iDelay=195, Bit 8, Center 104 (47 ~ 162) 116
8689 00:42:58.010143 iDelay=195, Bit 9, Center 110 (55 ~ 166) 112
8690 00:42:58.013351 iDelay=195, Bit 10, Center 124 (67 ~ 182) 116
8691 00:42:58.016472 iDelay=195, Bit 11, Center 114 (59 ~ 170) 112
8692 00:42:58.020121 iDelay=195, Bit 12, Center 130 (71 ~ 190) 120
8693 00:42:58.026930 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8694 00:42:58.029914 iDelay=195, Bit 14, Center 132 (75 ~ 190) 116
8695 00:42:58.033272 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8696 00:42:58.033667 ==
8697 00:42:58.036518 Dram Type= 6, Freq= 0, CH_1, rank 1
8698 00:42:58.039650 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8699 00:42:58.043541 ==
8700 00:42:58.044019 DQS Delay:
8701 00:42:58.044331 DQS0 = 0, DQS1 = 0
8702 00:42:58.046612 DQM Delay:
8703 00:42:58.047085 DQM0 = 127, DQM1 = 122
8704 00:42:58.050114 DQ Delay:
8705 00:42:58.053006 DQ0 =128, DQ1 =122, DQ2 =116, DQ3 =124
8706 00:42:58.056424 DQ4 =126, DQ5 =138, DQ6 =136, DQ7 =126
8707 00:42:58.059644 DQ8 =104, DQ9 =110, DQ10 =124, DQ11 =114
8708 00:42:58.063154 DQ12 =130, DQ13 =132, DQ14 =132, DQ15 =132
8709 00:42:58.063628
8710 00:42:58.063937
8711 00:42:58.064214
8712 00:42:58.066461 [DramC_TX_OE_Calibration] TA2
8713 00:42:58.069610 Original DQ_B0 (3 6) =30, OEN = 27
8714 00:42:58.073287 Original DQ_B1 (3 6) =30, OEN = 27
8715 00:42:58.076630 24, 0x0, End_B0=24 End_B1=24
8716 00:42:58.077030 25, 0x0, End_B0=25 End_B1=25
8717 00:42:58.079662 26, 0x0, End_B0=26 End_B1=26
8718 00:42:58.083104 27, 0x0, End_B0=27 End_B1=27
8719 00:42:58.086287 28, 0x0, End_B0=28 End_B1=28
8720 00:42:58.086833 29, 0x0, End_B0=29 End_B1=29
8721 00:42:58.090038 30, 0x0, End_B0=30 End_B1=30
8722 00:42:58.092551 31, 0x4141, End_B0=30 End_B1=30
8723 00:42:58.096420 Byte0 end_step=30 best_step=27
8724 00:42:58.099357 Byte1 end_step=30 best_step=27
8725 00:42:58.103120 Byte0 TX OE(2T, 0.5T) = (3, 3)
8726 00:42:58.106347 Byte1 TX OE(2T, 0.5T) = (3, 3)
8727 00:42:58.106821
8728 00:42:58.107131
8729 00:42:58.112654 [DQSOSCAuto] RK1, (LSB)MR18= 0x2222, (MSB)MR19= 0x303, tDQSOscB0 = 392 ps tDQSOscB1 = 392 ps
8730 00:42:58.116216 CH1 RK1: MR19=303, MR18=2222
8731 00:42:58.122698 CH1_RK1: MR19=0x303, MR18=0x2222, DQSOSC=392, MR23=63, INC=24, DEC=16
8732 00:42:58.125843 [RxdqsGatingPostProcess] freq 1600
8733 00:42:58.129990 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
8734 00:42:58.132374 Pre-setting of DQS Precalculation
8735 00:42:58.139140 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
8736 00:42:58.145965 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
8737 00:42:58.152666 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8738 00:42:58.153187
8739 00:42:58.153528
8740 00:42:58.155816 [Calibration Summary] 3200 Mbps
8741 00:42:58.156367 CH 0, Rank 0
8742 00:42:58.158795 SW Impedance : PASS
8743 00:42:58.162342 DUTY Scan : NO K
8744 00:42:58.162843 ZQ Calibration : PASS
8745 00:42:58.165510 Jitter Meter : NO K
8746 00:42:58.168631 CBT Training : PASS
8747 00:42:58.169062 Write leveling : PASS
8748 00:42:58.172053 RX DQS gating : PASS
8749 00:42:58.175521 RX DQ/DQS(RDDQC) : PASS
8750 00:42:58.176043 TX DQ/DQS : PASS
8751 00:42:58.179134 RX DATLAT : PASS
8752 00:42:58.182170 RX DQ/DQS(Engine): PASS
8753 00:42:58.182734 TX OE : PASS
8754 00:42:58.183085 All Pass.
8755 00:42:58.185810
8756 00:42:58.186379 CH 0, Rank 1
8757 00:42:58.188953 SW Impedance : PASS
8758 00:42:58.189384 DUTY Scan : NO K
8759 00:42:58.192406 ZQ Calibration : PASS
8760 00:42:58.195695 Jitter Meter : NO K
8761 00:42:58.196217 CBT Training : PASS
8762 00:42:58.199290 Write leveling : PASS
8763 00:42:58.199808 RX DQS gating : PASS
8764 00:42:58.202251 RX DQ/DQS(RDDQC) : PASS
8765 00:42:58.205348 TX DQ/DQS : PASS
8766 00:42:58.205871 RX DATLAT : PASS
8767 00:42:58.208924 RX DQ/DQS(Engine): PASS
8768 00:42:58.212296 TX OE : PASS
8769 00:42:58.212816 All Pass.
8770 00:42:58.213156
8771 00:42:58.213470 CH 1, Rank 0
8772 00:42:58.215256 SW Impedance : PASS
8773 00:42:58.219067 DUTY Scan : NO K
8774 00:42:58.219592 ZQ Calibration : PASS
8775 00:42:58.222117 Jitter Meter : NO K
8776 00:42:58.225627 CBT Training : PASS
8777 00:42:58.226146 Write leveling : PASS
8778 00:42:58.228890 RX DQS gating : PASS
8779 00:42:58.231745 RX DQ/DQS(RDDQC) : PASS
8780 00:42:58.232203 TX DQ/DQS : PASS
8781 00:42:58.235107 RX DATLAT : PASS
8782 00:42:58.238851 RX DQ/DQS(Engine): PASS
8783 00:42:58.239366 TX OE : PASS
8784 00:42:58.241566 All Pass.
8785 00:42:58.242191
8786 00:42:58.242604 CH 1, Rank 1
8787 00:42:58.245265 SW Impedance : PASS
8788 00:42:58.245783 DUTY Scan : NO K
8789 00:42:58.248469 ZQ Calibration : PASS
8790 00:42:58.251746 Jitter Meter : NO K
8791 00:42:58.252261 CBT Training : PASS
8792 00:42:58.255222 Write leveling : PASS
8793 00:42:58.258626 RX DQS gating : PASS
8794 00:42:58.259061 RX DQ/DQS(RDDQC) : PASS
8795 00:42:58.261600 TX DQ/DQS : PASS
8796 00:42:58.262033 RX DATLAT : PASS
8797 00:42:58.265121 RX DQ/DQS(Engine): PASS
8798 00:42:58.268627 TX OE : PASS
8799 00:42:58.269142 All Pass.
8800 00:42:58.269694
8801 00:42:58.271678 DramC Write-DBI on
8802 00:42:58.272147 PER_BANK_REFRESH: Hybrid Mode
8803 00:42:58.274705 TX_TRACKING: ON
8804 00:42:58.284684 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
8805 00:42:58.291445 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
8806 00:42:58.298575 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8807 00:42:58.301404 [FAST_K] Save calibration result to emmc
8808 00:42:58.304793 sync common calibartion params.
8809 00:42:58.308066 sync cbt_mode0:0, 1:0
8810 00:42:58.308542 dram_init: ddr_geometry: 0
8811 00:42:58.311055 dram_init: ddr_geometry: 0
8812 00:42:58.314578 dram_init: ddr_geometry: 0
8813 00:42:58.318369 0:dram_rank_size:80000000
8814 00:42:58.318851 1:dram_rank_size:80000000
8815 00:42:58.324801 sync rank num:2, rank0_size:0x80000000, rank1_size:0x80000000
8816 00:42:58.328039 DFS_SHUFFLE_HW_MODE: ON
8817 00:42:58.331172 dramc_set_vcore_voltage set vcore to 725000
8818 00:42:58.331659 Read voltage for 1600, 0
8819 00:42:58.334577 Vio18 = 0
8820 00:42:58.334968 Vcore = 725000
8821 00:42:58.335282 Vdram = 0
8822 00:42:58.338263 Vddq = 0
8823 00:42:58.338743 Vmddr = 0
8824 00:42:58.340939 switch to 3200 Mbps bootup
8825 00:42:58.341332 [DramcRunTimeConfig]
8826 00:42:58.341644 PHYPLL
8827 00:42:58.344623 DPM_CONTROL_AFTERK: ON
8828 00:42:58.348029 PER_BANK_REFRESH: ON
8829 00:42:58.351152 REFRESH_OVERHEAD_REDUCTION: ON
8830 00:42:58.351594 CMD_PICG_NEW_MODE: OFF
8831 00:42:58.354667 XRTWTW_NEW_MODE: ON
8832 00:42:58.355149 XRTRTR_NEW_MODE: ON
8833 00:42:58.357742 TX_TRACKING: ON
8834 00:42:58.358261 RDSEL_TRACKING: OFF
8835 00:42:58.361358 DQS Precalculation for DVFS: ON
8836 00:42:58.364685 RX_TRACKING: OFF
8837 00:42:58.365158 HW_GATING DBG: ON
8838 00:42:58.367820 ZQCS_ENABLE_LP4: ON
8839 00:42:58.368290 RX_PICG_NEW_MODE: ON
8840 00:42:58.371250 TX_PICG_NEW_MODE: ON
8841 00:42:58.371645 ENABLE_RX_DCM_DPHY: ON
8842 00:42:58.374241 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
8843 00:42:58.377544 DUMMY_READ_FOR_TRACKING: OFF
8844 00:42:58.381394 !!! SPM_CONTROL_AFTERK: OFF
8845 00:42:58.384322 !!! SPM could not control APHY
8846 00:42:58.384801 IMPEDANCE_TRACKING: ON
8847 00:42:58.387620 TEMP_SENSOR: ON
8848 00:42:58.388014 HW_SAVE_FOR_SR: OFF
8849 00:42:58.391298 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
8850 00:42:58.394171 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
8851 00:42:58.398102 Read ODT Tracking: ON
8852 00:42:58.400724 Refresh Rate DeBounce: ON
8853 00:42:58.401197 DFS_NO_QUEUE_FLUSH: ON
8854 00:42:58.403908 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
8855 00:42:58.407729 ENABLE_DFS_RUNTIME_MRW: OFF
8856 00:42:58.410726 DDR_RESERVE_NEW_MODE: ON
8857 00:42:58.411199 MR_CBT_SWITCH_FREQ: ON
8858 00:42:58.414059 =========================
8859 00:42:58.432466 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
8860 00:42:58.435801 dram_init: ddr_geometry: 0
8861 00:42:58.453728 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
8862 00:42:58.457307 dram_init: dram init end (result: 0)
8863 00:42:58.463776 DRAM-K: Full calibration passed in 23426 msecs
8864 00:42:58.467149 MRC: failed to locate region type 0.
8865 00:42:58.467603 DRAM rank0 size:0x80000000,
8866 00:42:58.470497 DRAM rank1 size=0x80000000
8867 00:42:58.480401 Mapping address range [0x40000000:0x140000000) as cacheable | read-write | non-secure | normal
8868 00:42:58.487552 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
8869 00:42:58.493626 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
8870 00:42:58.500206 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
8871 00:42:58.503639 DRAM rank0 size:0x80000000,
8872 00:42:58.507199 DRAM rank1 size=0x80000000
8873 00:42:58.507714 CBMEM:
8874 00:42:58.510308 IMD: root @ 0xfffff000 254 entries.
8875 00:42:58.513566 IMD: root @ 0xffffec00 62 entries.
8876 00:42:58.516492 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
8877 00:42:58.520087 WARNING: RO_VPD is uninitialized or empty.
8878 00:42:58.526466 FMAP: area RW_VPD found @ 577000 (16384 bytes)
8879 00:42:58.533874 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
8880 00:42:58.545948 read SPI 0x42894 0xe01e: 6226 us, 9215 KB/s, 73.720 Mbps
8881 00:42:58.557435 BS: romstage times (exec / console): total (unknown) / 22967 ms
8882 00:42:58.557651
8883 00:42:58.557817
8884 00:42:58.566925 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
8885 00:42:58.570163 ARM64: Exception handlers installed.
8886 00:42:58.573364 ARM64: Testing exception
8887 00:42:58.576887 ARM64: Done test exception
8888 00:42:58.577058 Enumerating buses...
8889 00:42:58.580402 Show all devs... Before device enumeration.
8890 00:42:58.583602 Root Device: enabled 1
8891 00:42:58.586876 CPU_CLUSTER: 0: enabled 1
8892 00:42:58.587047 CPU: 00: enabled 1
8893 00:42:58.590041 Compare with tree...
8894 00:42:58.590361 Root Device: enabled 1
8895 00:42:58.593637 CPU_CLUSTER: 0: enabled 1
8896 00:42:58.596716 CPU: 00: enabled 1
8897 00:42:58.596983 Root Device scanning...
8898 00:42:58.600143 scan_static_bus for Root Device
8899 00:42:58.603531 CPU_CLUSTER: 0 enabled
8900 00:42:58.607126 scan_static_bus for Root Device done
8901 00:42:58.609788 scan_bus: bus Root Device finished in 8 msecs
8902 00:42:58.610003 done
8903 00:42:58.616643 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
8904 00:42:58.619839 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
8905 00:42:58.626509 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
8906 00:42:58.630246 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
8907 00:42:58.633165 Allocating resources...
8908 00:42:58.637521 Reading resources...
8909 00:42:58.640244 Root Device read_resources bus 0 link: 0
8910 00:42:58.640846 DRAM rank0 size:0x80000000,
8911 00:42:58.643633 DRAM rank1 size=0x80000000
8912 00:42:58.646606 CPU_CLUSTER: 0 read_resources bus 0 link: 0
8913 00:42:58.649867 CPU: 00 missing read_resources
8914 00:42:58.657105 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
8915 00:42:58.659898 Root Device read_resources bus 0 link: 0 done
8916 00:42:58.660186 Done reading resources.
8917 00:42:58.666868 Show resources in subtree (Root Device)...After reading.
8918 00:42:58.669813 Root Device child on link 0 CPU_CLUSTER: 0
8919 00:42:58.673457 CPU_CLUSTER: 0 child on link 0 CPU: 00
8920 00:42:58.683222 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8921 00:42:58.683510 CPU: 00
8922 00:42:58.686420 Root Device assign_resources, bus 0 link: 0
8923 00:42:58.689444 CPU_CLUSTER: 0 missing set_resources
8924 00:42:58.696660 Root Device assign_resources, bus 0 link: 0 done
8925 00:42:58.697084 Done setting resources.
8926 00:42:58.703406 Show resources in subtree (Root Device)...After assigning values.
8927 00:42:58.706644 Root Device child on link 0 CPU_CLUSTER: 0
8928 00:42:58.709856 CPU_CLUSTER: 0 child on link 0 CPU: 00
8929 00:42:58.719686 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8930 00:42:58.720212 CPU: 00
8931 00:42:58.722931 Done allocating resources.
8932 00:42:58.729400 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
8933 00:42:58.729937 Enabling resources...
8934 00:42:58.730317 done.
8935 00:42:58.736109 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
8936 00:42:58.736792 Initializing devices...
8937 00:42:58.739276 Root Device init
8938 00:42:58.739799 init hardware done!
8939 00:42:58.742851 0x00000018: ctrlr->caps
8940 00:42:58.746024 52.000 MHz: ctrlr->f_max
8941 00:42:58.746496 0.400 MHz: ctrlr->f_min
8942 00:42:58.749751 0x40ff8080: ctrlr->voltages
8943 00:42:58.752789 sclk: 390625
8944 00:42:58.753308 Bus Width = 1
8945 00:42:58.753652 sclk: 390625
8946 00:42:58.755971 Bus Width = 1
8947 00:42:58.756496 Early init status = 3
8948 00:42:58.762939 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
8949 00:42:58.765904 in-header: 03 fc 00 00 01 00 00 00
8950 00:42:58.769265 in-data: 00
8951 00:42:58.772183 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
8952 00:42:58.776601 in-header: 03 fd 00 00 00 00 00 00
8953 00:42:58.779663 in-data:
8954 00:42:58.782761 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
8955 00:42:58.786419 in-header: 03 fc 00 00 01 00 00 00
8956 00:42:58.789776 in-data: 00
8957 00:42:58.793019 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
8958 00:42:58.798247 in-header: 03 fd 00 00 00 00 00 00
8959 00:42:58.801460 in-data:
8960 00:42:58.804646 [SSUSB] Setting up USB HOST controller...
8961 00:42:58.808068 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
8962 00:42:58.811307 [SSUSB] phy power-on done.
8963 00:42:58.814771 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
8964 00:42:58.820972 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
8965 00:42:58.824513 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
8966 00:42:58.830967 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
8967 00:42:58.837279 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
8968 00:42:58.843878 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
8969 00:42:58.850570 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
8970 00:42:58.857549 read SPI 0x705bc 0x1f6a: 923 us, 8712 KB/s, 69.696 Mbps
8971 00:42:58.860846 SPM: binary array size = 0x9dc
8972 00:42:58.864174 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
8973 00:42:58.870467 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
8974 00:42:58.877415 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
8975 00:42:58.883844 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
8976 00:42:58.887400 configure_display: Starting display init
8977 00:42:58.921792 anx7625_power_on_init: Init interface.
8978 00:42:58.924644 anx7625_disable_pd_protocol: Disabled PD feature.
8979 00:42:58.927884 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
8980 00:42:58.955665 anx7625_start_dp_work: Secure OCM version=00
8981 00:42:58.958832 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
8982 00:42:58.973998 sp_tx_get_edid_block: EDID Block = 1
8983 00:42:59.076108 Extracted contents:
8984 00:42:59.079701 header: 00 ff ff ff ff ff ff 00
8985 00:42:59.082685 serial number: 26 cf 7d 05 00 00 00 00 00 1e
8986 00:42:59.085924 version: 01 04
8987 00:42:59.089348 basic params: 95 1f 11 78 0a
8988 00:42:59.092981 chroma info: 76 90 94 55 54 90 27 21 50 54
8989 00:42:59.096209 established: 00 00 00
8990 00:42:59.102943 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
8991 00:42:59.105802 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
8992 00:42:59.112404 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
8993 00:42:59.119413 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
8994 00:42:59.125925 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
8995 00:42:59.129304 extensions: 00
8996 00:42:59.129704 checksum: fb
8997 00:42:59.130015
8998 00:42:59.132358 Manufacturer: IVO Model 57d Serial Number 0
8999 00:42:59.135787 Made week 0 of 2020
9000 00:42:59.136190 EDID version: 1.4
9001 00:42:59.139023 Digital display
9002 00:42:59.142316 6 bits per primary color channel
9003 00:42:59.142975 DisplayPort interface
9004 00:42:59.145647 Maximum image size: 31 cm x 17 cm
9005 00:42:59.148753 Gamma: 220%
9006 00:42:59.149364 Check DPMS levels
9007 00:42:59.152210 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9008 00:42:59.158728 First detailed timing is preferred timing
9009 00:42:59.159230 Established timings supported:
9010 00:42:59.162105 Standard timings supported:
9011 00:42:59.165741 Detailed timings
9012 00:42:59.169130 Hex of detail: 383680a07038204018303c0035ae10000019
9013 00:42:59.175287 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9014 00:42:59.179055 0780 0798 07c8 0820 hborder 0
9015 00:42:59.181824 0438 043b 0447 0458 vborder 0
9016 00:42:59.185572 -hsync -vsync
9017 00:42:59.186044 Did detailed timing
9018 00:42:59.192307 Hex of detail: 000000000000000000000000000000000000
9019 00:42:59.195288 Manufacturer-specified data, tag 0
9020 00:42:59.198865 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9021 00:42:59.201818 ASCII string: InfoVision
9022 00:42:59.205440 Hex of detail: 000000fe00523134304e574635205248200a
9023 00:42:59.208584 ASCII string: R140NWF5 RH
9024 00:42:59.209063 Checksum
9025 00:42:59.212482 Checksum: 0xfb (valid)
9026 00:42:59.215101 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9027 00:42:59.218244 DSI data_rate: 832800000 bps
9028 00:42:59.225948 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9029 00:42:59.228758 anx7625_parse_edid: pixelclock(138800).
9030 00:42:59.232215 hactive(1920), hsync(48), hfp(24), hbp(88)
9031 00:42:59.235682 vactive(1080), vsync(12), vfp(3), vbp(17)
9032 00:42:59.238562 anx7625_dsi_config: config dsi.
9033 00:42:59.244903 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9034 00:42:59.258262 anx7625_dsi_config: success to config DSI
9035 00:42:59.261556 anx7625_dp_start: MIPI phy setup OK.
9036 00:42:59.265003 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9037 00:42:59.268659 mtk_ddp_mode_set invalid vrefresh 60
9038 00:42:59.271517 main_disp_path_setup
9039 00:42:59.272037 ovl_layer_smi_id_en
9040 00:42:59.274676 ovl_layer_smi_id_en
9041 00:42:59.275070 ccorr_config
9042 00:42:59.275377 aal_config
9043 00:42:59.278092 gamma_config
9044 00:42:59.278606 postmask_config
9045 00:42:59.281394 dither_config
9046 00:42:59.284781 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9047 00:42:59.291339 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9048 00:42:59.294711 Root Device init finished in 552 msecs
9049 00:42:59.295252 CPU_CLUSTER: 0 init
9050 00:42:59.305123 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9051 00:42:59.308022 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9052 00:42:59.311462 APU_MBOX 0x190000b0 = 0x10001
9053 00:42:59.314862 APU_MBOX 0x190001b0 = 0x10001
9054 00:42:59.318015 APU_MBOX 0x190005b0 = 0x10001
9055 00:42:59.321797 APU_MBOX 0x190006b0 = 0x10001
9056 00:42:59.325015 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9057 00:42:59.337354 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9058 00:42:59.349772 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9059 00:42:59.356716 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9060 00:42:59.368350 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9061 00:42:59.377258 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9062 00:42:59.380170 CPU_CLUSTER: 0 init finished in 81 msecs
9063 00:42:59.383733 Devices initialized
9064 00:42:59.387103 Show all devs... After init.
9065 00:42:59.387686 Root Device: enabled 1
9066 00:42:59.390421 CPU_CLUSTER: 0: enabled 1
9067 00:42:59.394017 CPU: 00: enabled 1
9068 00:42:59.396870 BS: BS_DEV_INIT run times (exec / console): 210 / 447 ms
9069 00:42:59.400037 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9070 00:42:59.403640 ELOG: NV offset 0x57f000 size 0x1000
9071 00:42:59.410301 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9072 00:42:59.417140 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9073 00:42:59.420360 ELOG: Event(17) added with size 13 at 2024-06-16 00:42:59 UTC
9074 00:42:59.423652 out: cmd=0x121: 03 db 21 01 00 00 00 00
9075 00:42:59.427052 in-header: 03 34 00 00 2c 00 00 00
9076 00:42:59.440196 in-data: 0e 6d 00 00 00 00 00 00 0a 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9077 00:42:59.446750 ELOG: Event(A1) added with size 10 at 2024-06-16 00:42:59 UTC
9078 00:42:59.453874 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
9079 00:42:59.460934 ELOG: Event(A0) added with size 9 at 2024-06-16 00:42:59 UTC
9080 00:42:59.463961 elog_add_boot_reason: Logged dev mode boot
9081 00:42:59.467075 BS: BS_POST_DEVICE entry times (exec / console): 1 / 64 ms
9082 00:42:59.470149 Finalize devices...
9083 00:42:59.470582 Devices finalized
9084 00:42:59.477126 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9085 00:42:59.480307 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
9086 00:42:59.483707 in-header: 03 07 00 00 08 00 00 00
9087 00:42:59.487004 in-data: aa e4 47 04 13 02 00 00
9088 00:42:59.490327 Chrome EC: UHEPI supported
9089 00:42:59.496955 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
9090 00:42:59.500222 in-header: 03 a9 00 00 08 00 00 00
9091 00:42:59.503502 in-data: 84 60 60 08 00 00 00 00
9092 00:42:59.506585 ELOG: Event(91) added with size 10 at 2024-06-16 00:42:59 UTC
9093 00:42:59.513474 Chrome EC: clear events_b mask to 0x0000000020004000
9094 00:42:59.520214 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
9095 00:42:59.523607 in-header: 03 fd 00 00 00 00 00 00
9096 00:42:59.524081 in-data:
9097 00:42:59.530369 BS: BS_WRITE_TABLES entry times (exec / console): 2 / 46 ms
9098 00:42:59.534126 Writing coreboot table at 0xffe64000
9099 00:42:59.537122 0. 000000000010a000-0000000000113fff: RAMSTAGE
9100 00:42:59.540619 1. 0000000040000000-00000000400fffff: RAM
9101 00:42:59.543504 2. 0000000040100000-000000004032afff: RAMSTAGE
9102 00:42:59.550163 3. 000000004032b000-00000000545fffff: RAM
9103 00:42:59.553820 4. 0000000054600000-000000005465ffff: BL31
9104 00:42:59.557376 5. 0000000054660000-00000000ffe63fff: RAM
9105 00:42:59.560806 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9106 00:42:59.566868 7. 0000000100000000-000000013fffffff: RAM
9107 00:42:59.567384 Passing 5 GPIOs to payload:
9108 00:42:59.573833 NAME | PORT | POLARITY | VALUE
9109 00:42:59.577007 EC in RW | 0x000000aa | low | undefined
9110 00:42:59.583848 EC interrupt | 0x00000005 | low | undefined
9111 00:42:59.586976 TPM interrupt | 0x000000ab | high | undefined
9112 00:42:59.590101 SD card detect | 0x00000011 | high | undefined
9113 00:42:59.597035 speaker enable | 0x00000093 | high | undefined
9114 00:42:59.600341 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9115 00:42:59.603721 in-header: 03 f8 00 00 02 00 00 00
9116 00:42:59.604243 in-data: 03 00
9117 00:42:59.606974 ADC[4]: Raw value=669327 ID=5
9118 00:42:59.610293 ADC[3]: Raw value=212549 ID=1
9119 00:42:59.610808 RAM Code: 0x51
9120 00:42:59.614086 ADC[6]: Raw value=74410 ID=0
9121 00:42:59.617102 ADC[5]: Raw value=211812 ID=1
9122 00:42:59.617539 SKU Code: 0x1
9123 00:42:59.623412 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum eed
9124 00:42:59.626889 coreboot table: 964 bytes.
9125 00:42:59.630146 IMD ROOT 0. 0xfffff000 0x00001000
9126 00:42:59.633613 IMD SMALL 1. 0xffffe000 0x00001000
9127 00:42:59.636663 RO MCACHE 2. 0xffffc000 0x00001104
9128 00:42:59.640093 CONSOLE 3. 0xfff7c000 0x00080000
9129 00:42:59.643473 FMAP 4. 0xfff7b000 0x00000452
9130 00:42:59.646657 TIME STAMP 5. 0xfff7a000 0x00000910
9131 00:42:59.650247 VBOOT WORK 6. 0xfff66000 0x00014000
9132 00:42:59.653291 RAMOOPS 7. 0xffe66000 0x00100000
9133 00:42:59.656707 COREBOOT 8. 0xffe64000 0x00002000
9134 00:42:59.657220 IMD small region:
9135 00:42:59.660421 IMD ROOT 0. 0xffffec00 0x00000400
9136 00:42:59.663302 VPD 1. 0xffffeb80 0x0000006c
9137 00:42:59.666483 MMC STATUS 2. 0xffffeb60 0x00000004
9138 00:42:59.672980 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9139 00:42:59.679695 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9140 00:42:59.718995 read SPI 0x3990ec 0x4f1b0: 34846 us, 9298 KB/s, 74.384 Mbps
9141 00:42:59.722955 Checking segment from ROM address 0x40100000
9142 00:42:59.726119 Checking segment from ROM address 0x4010001c
9143 00:42:59.732237 Loading segment from ROM address 0x40100000
9144 00:42:59.732725 code (compression=0)
9145 00:42:59.739168 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9146 00:42:59.748874 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9147 00:42:59.749440 it's not compressed!
9148 00:42:59.756020 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9149 00:42:59.759164 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9150 00:42:59.779592 Loading segment from ROM address 0x4010001c
9151 00:42:59.780154 Entry Point 0x80000000
9152 00:42:59.782831 Loaded segments
9153 00:42:59.786596 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9154 00:42:59.792683 Jumping to boot code at 0x80000000(0xffe64000)
9155 00:42:59.799398 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9156 00:42:59.805771 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9157 00:42:59.814148 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9158 00:42:59.817467 Checking segment from ROM address 0x40100000
9159 00:42:59.821069 Checking segment from ROM address 0x4010001c
9160 00:42:59.827012 Loading segment from ROM address 0x40100000
9161 00:42:59.827543 code (compression=1)
9162 00:42:59.834336 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9163 00:42:59.844246 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9164 00:42:59.844767 using LZMA
9165 00:42:59.852168 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9166 00:42:59.858748 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9167 00:42:59.862124 Loading segment from ROM address 0x4010001c
9168 00:42:59.862593 Entry Point 0x54601000
9169 00:42:59.865152 Loaded segments
9170 00:42:59.868376 NOTICE: MT8192 bl31_setup
9171 00:42:59.875506 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9172 00:42:59.879677 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9173 00:42:59.882670 WARNING: region 0:
9174 00:42:59.885882 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9175 00:42:59.886357 WARNING: region 1:
9176 00:42:59.892438 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9177 00:42:59.895804 WARNING: region 2:
9178 00:42:59.899358 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9179 00:42:59.902604 WARNING: region 3:
9180 00:42:59.906031 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9181 00:42:59.909617 WARNING: region 4:
9182 00:42:59.915631 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9183 00:42:59.916143 WARNING: region 5:
9184 00:42:59.919085 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9185 00:42:59.922322 WARNING: region 6:
9186 00:42:59.925746 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9187 00:42:59.929005 WARNING: region 7:
9188 00:42:59.932366 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9189 00:42:59.938904 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9190 00:42:59.942777 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9191 00:42:59.945832 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9192 00:42:59.952429 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9193 00:42:59.956038 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9194 00:42:59.958699 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9195 00:42:59.965753 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9196 00:42:59.968898 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9197 00:42:59.975449 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9198 00:42:59.978877 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9199 00:42:59.982056 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9200 00:42:59.989146 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9201 00:42:59.991969 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9202 00:42:59.995357 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9203 00:43:00.002444 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9204 00:43:00.005818 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9205 00:43:00.011934 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9206 00:43:00.015822 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9207 00:43:00.018609 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9208 00:43:00.025519 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9209 00:43:00.028596 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9210 00:43:00.032157 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9211 00:43:00.038626 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9212 00:43:00.042065 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9213 00:43:00.048747 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9214 00:43:00.052083 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9215 00:43:00.058527 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9216 00:43:00.062170 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9217 00:43:00.065340 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9218 00:43:00.072049 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9219 00:43:00.075381 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9220 00:43:00.078920 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9221 00:43:00.085823 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9222 00:43:00.088532 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9223 00:43:00.091759 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9224 00:43:00.095283 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9225 00:43:00.102032 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9226 00:43:00.106058 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9227 00:43:00.108771 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9228 00:43:00.112186 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9229 00:43:00.118564 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9230 00:43:00.122405 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9231 00:43:00.125131 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9232 00:43:00.128551 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9233 00:43:00.135112 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9234 00:43:00.138488 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9235 00:43:00.141747 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9236 00:43:00.148485 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9237 00:43:00.151367 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9238 00:43:00.154646 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9239 00:43:00.161788 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9240 00:43:00.165145 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9241 00:43:00.171242 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9242 00:43:00.174831 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9243 00:43:00.181747 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9244 00:43:00.185032 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9245 00:43:00.187853 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9246 00:43:00.194729 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9247 00:43:00.197842 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9248 00:43:00.204827 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9249 00:43:00.208033 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9250 00:43:00.214826 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9251 00:43:00.218025 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9252 00:43:00.224866 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9253 00:43:00.228070 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9254 00:43:00.231207 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9255 00:43:00.237833 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9256 00:43:00.241140 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9257 00:43:00.248031 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9258 00:43:00.251129 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9259 00:43:00.257923 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9260 00:43:00.261416 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9261 00:43:00.264808 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9262 00:43:00.271306 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9263 00:43:00.274452 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9264 00:43:00.281124 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9265 00:43:00.284523 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9266 00:43:00.291270 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9267 00:43:00.294573 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9268 00:43:00.301132 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9269 00:43:00.304087 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9270 00:43:00.307429 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9271 00:43:00.314473 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9272 00:43:00.317361 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9273 00:43:00.324172 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9274 00:43:00.327485 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9275 00:43:00.330892 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9276 00:43:00.337663 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9277 00:43:00.340992 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9278 00:43:00.347405 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9279 00:43:00.350888 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9280 00:43:00.357860 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9281 00:43:00.360689 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9282 00:43:00.367463 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9283 00:43:00.370878 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9284 00:43:00.374352 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9285 00:43:00.380500 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9286 00:43:00.383760 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9287 00:43:00.387528 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9288 00:43:00.390581 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9289 00:43:00.397477 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9290 00:43:00.400506 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9291 00:43:00.407631 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9292 00:43:00.410790 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9293 00:43:00.413940 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9294 00:43:00.420166 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9295 00:43:00.423882 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9296 00:43:00.430558 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9297 00:43:00.433884 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9298 00:43:00.437284 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9299 00:43:00.443943 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9300 00:43:00.447330 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9301 00:43:00.450582 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9302 00:43:00.457349 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9303 00:43:00.460584 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9304 00:43:00.467272 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9305 00:43:00.470466 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9306 00:43:00.474026 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9307 00:43:00.480740 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9308 00:43:00.483851 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9309 00:43:00.487171 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9310 00:43:00.490391 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9311 00:43:00.494044 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9312 00:43:00.500698 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9313 00:43:00.504042 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9314 00:43:00.510862 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9315 00:43:00.514464 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9316 00:43:00.517242 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9317 00:43:00.523843 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9318 00:43:00.527328 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9319 00:43:00.530520 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9320 00:43:00.537450 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9321 00:43:00.540846 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9322 00:43:00.547033 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9323 00:43:00.550810 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9324 00:43:00.553601 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9325 00:43:00.560669 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9326 00:43:00.564200 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9327 00:43:00.570591 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9328 00:43:00.574395 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9329 00:43:00.577126 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9330 00:43:00.583914 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9331 00:43:00.587022 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9332 00:43:00.593896 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9333 00:43:00.597255 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9334 00:43:00.600235 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9335 00:43:00.606962 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9336 00:43:00.610494 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9337 00:43:00.617120 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9338 00:43:00.620349 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9339 00:43:00.623576 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9340 00:43:00.630135 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9341 00:43:00.633920 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9342 00:43:00.636826 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9343 00:43:00.643898 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9344 00:43:00.647151 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9345 00:43:00.653670 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9346 00:43:00.657198 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9347 00:43:00.660420 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9348 00:43:00.667237 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9349 00:43:00.670314 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9350 00:43:00.677084 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9351 00:43:00.680169 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9352 00:43:00.683615 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9353 00:43:00.690248 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9354 00:43:00.693554 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9355 00:43:00.696732 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9356 00:43:00.703505 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9357 00:43:00.706945 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9358 00:43:00.713450 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9359 00:43:00.716932 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9360 00:43:00.719731 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9361 00:43:00.726646 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9362 00:43:00.730006 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9363 00:43:00.736575 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9364 00:43:00.740315 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9365 00:43:00.743512 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9366 00:43:00.750185 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9367 00:43:00.753184 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9368 00:43:00.760131 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9369 00:43:00.763642 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9370 00:43:00.766453 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9371 00:43:00.773502 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9372 00:43:00.776673 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9373 00:43:00.780139 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9374 00:43:00.786843 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9375 00:43:00.789863 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9376 00:43:00.797111 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9377 00:43:00.800302 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9378 00:43:00.803283 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9379 00:43:00.810102 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9380 00:43:00.813271 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9381 00:43:00.820100 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9382 00:43:00.823603 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9383 00:43:00.829942 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9384 00:43:00.833321 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9385 00:43:00.836506 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9386 00:43:00.843214 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9387 00:43:00.846296 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9388 00:43:00.853349 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9389 00:43:00.856510 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9390 00:43:00.859957 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9391 00:43:00.866643 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9392 00:43:00.869927 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9393 00:43:00.876413 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9394 00:43:00.880004 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9395 00:43:00.886434 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9396 00:43:00.889553 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9397 00:43:00.892789 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9398 00:43:00.900048 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9399 00:43:00.902990 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9400 00:43:00.909750 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9401 00:43:00.913394 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9402 00:43:00.919511 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9403 00:43:00.922937 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9404 00:43:00.926490 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9405 00:43:00.932753 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9406 00:43:00.936572 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9407 00:43:00.942892 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9408 00:43:00.946014 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9409 00:43:00.949826 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9410 00:43:00.955679 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9411 00:43:00.959058 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9412 00:43:00.965531 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9413 00:43:00.969607 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9414 00:43:00.972679 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9415 00:43:00.979257 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9416 00:43:00.982355 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9417 00:43:00.989117 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9418 00:43:00.992068 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9419 00:43:00.995442 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9420 00:43:00.999325 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9421 00:43:01.005685 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9422 00:43:01.009318 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9423 00:43:01.012986 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9424 00:43:01.019437 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9425 00:43:01.022522 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9426 00:43:01.026037 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9427 00:43:01.032458 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9428 00:43:01.036003 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9429 00:43:01.039262 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9430 00:43:01.046142 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9431 00:43:01.048890 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9432 00:43:01.052544 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9433 00:43:01.059010 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9434 00:43:01.062514 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9435 00:43:01.069119 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9436 00:43:01.072541 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9437 00:43:01.075743 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9438 00:43:01.082303 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9439 00:43:01.086283 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9440 00:43:01.089255 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9441 00:43:01.095439 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9442 00:43:01.099211 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9443 00:43:01.102559 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9444 00:43:01.109101 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9445 00:43:01.112307 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9446 00:43:01.119216 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9447 00:43:01.122335 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9448 00:43:01.125918 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9449 00:43:01.132463 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9450 00:43:01.135855 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9451 00:43:01.138960 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9452 00:43:01.145724 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9453 00:43:01.149044 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9454 00:43:01.152522 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9455 00:43:01.158806 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9456 00:43:01.162057 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9457 00:43:01.165342 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9458 00:43:01.172377 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9459 00:43:01.175438 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9460 00:43:01.179072 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9461 00:43:01.181936 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9462 00:43:01.185660 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9463 00:43:01.191936 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9464 00:43:01.195659 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9465 00:43:01.198823 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9466 00:43:01.205524 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9467 00:43:01.208525 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9468 00:43:01.211893 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9469 00:43:01.215444 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9470 00:43:01.221834 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9471 00:43:01.225591 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9472 00:43:01.228563 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9473 00:43:01.235256 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9474 00:43:01.238780 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9475 00:43:01.244987 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9476 00:43:01.248691 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9477 00:43:01.255381 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9478 00:43:01.258617 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9479 00:43:01.261905 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9480 00:43:01.269525 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9481 00:43:01.272165 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9482 00:43:01.278619 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9483 00:43:01.281956 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9484 00:43:01.285063 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9485 00:43:01.291778 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9486 00:43:01.295280 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9487 00:43:01.302008 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9488 00:43:01.305447 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9489 00:43:01.308387 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9490 00:43:01.315493 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9491 00:43:01.318795 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9492 00:43:01.325154 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9493 00:43:01.328439 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9494 00:43:01.332026 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9495 00:43:01.338646 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9496 00:43:01.342198 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9497 00:43:01.348373 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9498 00:43:01.351641 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9499 00:43:01.355225 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9500 00:43:01.361839 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9501 00:43:01.365259 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9502 00:43:01.371762 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9503 00:43:01.375361 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9504 00:43:01.378116 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9505 00:43:01.385362 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9506 00:43:01.388306 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9507 00:43:01.394861 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9508 00:43:01.398061 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9509 00:43:01.404901 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9510 00:43:01.408696 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9511 00:43:01.411491 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9512 00:43:01.418502 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9513 00:43:01.422200 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9514 00:43:01.428463 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9515 00:43:01.431697 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9516 00:43:01.435400 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9517 00:43:01.441405 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9518 00:43:01.444735 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9519 00:43:01.451576 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9520 00:43:01.455021 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9521 00:43:01.457979 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9522 00:43:01.464957 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9523 00:43:01.468373 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9524 00:43:01.474823 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9525 00:43:01.478358 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9526 00:43:01.481393 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9527 00:43:01.488201 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9528 00:43:01.491418 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9529 00:43:01.497943 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9530 00:43:01.501268 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9531 00:43:01.508191 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9532 00:43:01.511005 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9533 00:43:01.514401 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9534 00:43:01.520999 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9535 00:43:01.524341 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9536 00:43:01.531089 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9537 00:43:01.534252 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9538 00:43:01.537488 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9539 00:43:01.544201 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9540 00:43:01.547477 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9541 00:43:01.554459 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9542 00:43:01.557814 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9543 00:43:01.560996 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9544 00:43:01.567622 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9545 00:43:01.571728 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9546 00:43:01.577622 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9547 00:43:01.581094 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9548 00:43:01.587600 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9549 00:43:01.590787 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9550 00:43:01.594105 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9551 00:43:01.600816 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9552 00:43:01.604212 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9553 00:43:01.611156 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9554 00:43:01.614144 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9555 00:43:01.620924 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9556 00:43:01.624135 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9557 00:43:01.630544 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9558 00:43:01.633963 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9559 00:43:01.637334 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9560 00:43:01.643898 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9561 00:43:01.647369 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9562 00:43:01.653914 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9563 00:43:01.657205 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9564 00:43:01.663890 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9565 00:43:01.667010 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9566 00:43:01.670664 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9567 00:43:01.676944 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9568 00:43:01.680559 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9569 00:43:01.687087 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9570 00:43:01.690000 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9571 00:43:01.697207 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9572 00:43:01.700246 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9573 00:43:01.706647 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9574 00:43:01.710262 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9575 00:43:01.713719 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9576 00:43:01.720164 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9577 00:43:01.723295 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9578 00:43:01.730516 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9579 00:43:01.733421 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9580 00:43:01.740096 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9581 00:43:01.743600 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9582 00:43:01.747160 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9583 00:43:01.753611 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9584 00:43:01.757234 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9585 00:43:01.763537 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9586 00:43:01.766875 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9587 00:43:01.773627 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9588 00:43:01.776467 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9589 00:43:01.779993 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9590 00:43:01.786566 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9591 00:43:01.789997 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9592 00:43:01.796665 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9593 00:43:01.799878 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9594 00:43:01.803509 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9595 00:43:01.809984 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9596 00:43:01.813196 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9597 00:43:01.819526 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9598 00:43:01.822890 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9599 00:43:01.829938 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9600 00:43:01.832825 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9601 00:43:01.839454 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9602 00:43:01.842870 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9603 00:43:01.849715 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9604 00:43:01.852991 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9605 00:43:01.859365 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9606 00:43:01.862885 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9607 00:43:01.869448 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9608 00:43:01.873024 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9609 00:43:01.879279 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9610 00:43:01.883050 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9611 00:43:01.889400 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9612 00:43:01.892597 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9613 00:43:01.899325 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9614 00:43:01.902933 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9615 00:43:01.909543 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9616 00:43:01.912791 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9617 00:43:01.919260 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9618 00:43:01.922633 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9619 00:43:01.929617 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9620 00:43:01.932434 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9621 00:43:01.939061 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9622 00:43:01.942618 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9623 00:43:01.945796 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9624 00:43:01.949206 INFO: [APUAPC] vio 0
9625 00:43:01.956475 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9626 00:43:01.958907 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9627 00:43:01.962421 INFO: [APUAPC] D0_APC_0: 0x400510
9628 00:43:01.965701 INFO: [APUAPC] D0_APC_1: 0x0
9629 00:43:01.969268 INFO: [APUAPC] D0_APC_2: 0x1540
9630 00:43:01.972462 INFO: [APUAPC] D0_APC_3: 0x0
9631 00:43:01.975810 INFO: [APUAPC] D1_APC_0: 0xffffffff
9632 00:43:01.978950 INFO: [APUAPC] D1_APC_1: 0xffffffff
9633 00:43:01.982576 INFO: [APUAPC] D1_APC_2: 0x3fffff
9634 00:43:01.985918 INFO: [APUAPC] D1_APC_3: 0x0
9635 00:43:01.989302 INFO: [APUAPC] D2_APC_0: 0xffffffff
9636 00:43:01.992415 INFO: [APUAPC] D2_APC_1: 0xffffffff
9637 00:43:01.995672 INFO: [APUAPC] D2_APC_2: 0x3fffff
9638 00:43:01.999310 INFO: [APUAPC] D2_APC_3: 0x0
9639 00:43:02.002533 INFO: [APUAPC] D3_APC_0: 0xffffffff
9640 00:43:02.005715 INFO: [APUAPC] D3_APC_1: 0xffffffff
9641 00:43:02.009654 INFO: [APUAPC] D3_APC_2: 0x3fffff
9642 00:43:02.010174 INFO: [APUAPC] D3_APC_3: 0x0
9643 00:43:02.012347 INFO: [APUAPC] D4_APC_0: 0xffffffff
9644 00:43:02.019108 INFO: [APUAPC] D4_APC_1: 0xffffffff
9645 00:43:02.019621 INFO: [APUAPC] D4_APC_2: 0x3fffff
9646 00:43:02.022395 INFO: [APUAPC] D4_APC_3: 0x0
9647 00:43:02.026306 INFO: [APUAPC] D5_APC_0: 0xffffffff
9648 00:43:02.029178 INFO: [APUAPC] D5_APC_1: 0xffffffff
9649 00:43:02.032282 INFO: [APUAPC] D5_APC_2: 0x3fffff
9650 00:43:02.035730 INFO: [APUAPC] D5_APC_3: 0x0
9651 00:43:02.039176 INFO: [APUAPC] D6_APC_0: 0xffffffff
9652 00:43:02.042150 INFO: [APUAPC] D6_APC_1: 0xffffffff
9653 00:43:02.046305 INFO: [APUAPC] D6_APC_2: 0x3fffff
9654 00:43:02.049001 INFO: [APUAPC] D6_APC_3: 0x0
9655 00:43:02.052295 INFO: [APUAPC] D7_APC_0: 0xffffffff
9656 00:43:02.055565 INFO: [APUAPC] D7_APC_1: 0xffffffff
9657 00:43:02.059126 INFO: [APUAPC] D7_APC_2: 0x3fffff
9658 00:43:02.062417 INFO: [APUAPC] D7_APC_3: 0x0
9659 00:43:02.065555 INFO: [APUAPC] D8_APC_0: 0xffffffff
9660 00:43:02.068911 INFO: [APUAPC] D8_APC_1: 0xffffffff
9661 00:43:02.072364 INFO: [APUAPC] D8_APC_2: 0x3fffff
9662 00:43:02.075501 INFO: [APUAPC] D8_APC_3: 0x0
9663 00:43:02.078789 INFO: [APUAPC] D9_APC_0: 0xffffffff
9664 00:43:02.081977 INFO: [APUAPC] D9_APC_1: 0xffffffff
9665 00:43:02.085666 INFO: [APUAPC] D9_APC_2: 0x3fffff
9666 00:43:02.089096 INFO: [APUAPC] D9_APC_3: 0x0
9667 00:43:02.092322 INFO: [APUAPC] D10_APC_0: 0xffffffff
9668 00:43:02.095131 INFO: [APUAPC] D10_APC_1: 0xffffffff
9669 00:43:02.098860 INFO: [APUAPC] D10_APC_2: 0x3fffff
9670 00:43:02.102452 INFO: [APUAPC] D10_APC_3: 0x0
9671 00:43:02.105887 INFO: [APUAPC] D11_APC_0: 0xffffffff
9672 00:43:02.109070 INFO: [APUAPC] D11_APC_1: 0xffffffff
9673 00:43:02.112121 INFO: [APUAPC] D11_APC_2: 0x3fffff
9674 00:43:02.115472 INFO: [APUAPC] D11_APC_3: 0x0
9675 00:43:02.118804 INFO: [APUAPC] D12_APC_0: 0xffffffff
9676 00:43:02.122293 INFO: [APUAPC] D12_APC_1: 0xffffffff
9677 00:43:02.126039 INFO: [APUAPC] D12_APC_2: 0x3fffff
9678 00:43:02.128621 INFO: [APUAPC] D12_APC_3: 0x0
9679 00:43:02.132087 INFO: [APUAPC] D13_APC_0: 0xffffffff
9680 00:43:02.135430 INFO: [APUAPC] D13_APC_1: 0xffffffff
9681 00:43:02.138593 INFO: [APUAPC] D13_APC_2: 0x3fffff
9682 00:43:02.142199 INFO: [APUAPC] D13_APC_3: 0x0
9683 00:43:02.145528 INFO: [APUAPC] D14_APC_0: 0xffffffff
9684 00:43:02.148774 INFO: [APUAPC] D14_APC_1: 0xffffffff
9685 00:43:02.152224 INFO: [APUAPC] D14_APC_2: 0x3fffff
9686 00:43:02.155405 INFO: [APUAPC] D14_APC_3: 0x0
9687 00:43:02.158901 INFO: [APUAPC] D15_APC_0: 0xffffffff
9688 00:43:02.162600 INFO: [APUAPC] D15_APC_1: 0xffffffff
9689 00:43:02.165388 INFO: [APUAPC] D15_APC_2: 0x3fffff
9690 00:43:02.168738 INFO: [APUAPC] D15_APC_3: 0x0
9691 00:43:02.172158 INFO: [APUAPC] APC_CON: 0x4
9692 00:43:02.175663 INFO: [NOCDAPC] D0_APC_0: 0x0
9693 00:43:02.178520 INFO: [NOCDAPC] D0_APC_1: 0x0
9694 00:43:02.178987 INFO: [NOCDAPC] D1_APC_0: 0x0
9695 00:43:02.182317 INFO: [NOCDAPC] D1_APC_1: 0xfff
9696 00:43:02.185533 INFO: [NOCDAPC] D2_APC_0: 0x0
9697 00:43:02.188679 INFO: [NOCDAPC] D2_APC_1: 0xfff
9698 00:43:02.191875 INFO: [NOCDAPC] D3_APC_0: 0x0
9699 00:43:02.195207 INFO: [NOCDAPC] D3_APC_1: 0xfff
9700 00:43:02.198848 INFO: [NOCDAPC] D4_APC_0: 0x0
9701 00:43:02.201700 INFO: [NOCDAPC] D4_APC_1: 0xfff
9702 00:43:02.205108 INFO: [NOCDAPC] D5_APC_0: 0x0
9703 00:43:02.208389 INFO: [NOCDAPC] D5_APC_1: 0xfff
9704 00:43:02.212480 INFO: [NOCDAPC] D6_APC_0: 0x0
9705 00:43:02.213075 INFO: [NOCDAPC] D6_APC_1: 0xfff
9706 00:43:02.215125 INFO: [NOCDAPC] D7_APC_0: 0x0
9707 00:43:02.218704 INFO: [NOCDAPC] D7_APC_1: 0xfff
9708 00:43:02.221831 INFO: [NOCDAPC] D8_APC_0: 0x0
9709 00:43:02.225483 INFO: [NOCDAPC] D8_APC_1: 0xfff
9710 00:43:02.228693 INFO: [NOCDAPC] D9_APC_0: 0x0
9711 00:43:02.232202 INFO: [NOCDAPC] D9_APC_1: 0xfff
9712 00:43:02.235741 INFO: [NOCDAPC] D10_APC_0: 0x0
9713 00:43:02.238448 INFO: [NOCDAPC] D10_APC_1: 0xfff
9714 00:43:02.242019 INFO: [NOCDAPC] D11_APC_0: 0x0
9715 00:43:02.245399 INFO: [NOCDAPC] D11_APC_1: 0xfff
9716 00:43:02.248843 INFO: [NOCDAPC] D12_APC_0: 0x0
9717 00:43:02.249358 INFO: [NOCDAPC] D12_APC_1: 0xfff
9718 00:43:02.251964 INFO: [NOCDAPC] D13_APC_0: 0x0
9719 00:43:02.255099 INFO: [NOCDAPC] D13_APC_1: 0xfff
9720 00:43:02.258967 INFO: [NOCDAPC] D14_APC_0: 0x0
9721 00:43:02.261870 INFO: [NOCDAPC] D14_APC_1: 0xfff
9722 00:43:02.265674 INFO: [NOCDAPC] D15_APC_0: 0x0
9723 00:43:02.268621 INFO: [NOCDAPC] D15_APC_1: 0xfff
9724 00:43:02.271817 INFO: [NOCDAPC] APC_CON: 0x4
9725 00:43:02.275059 INFO: [APUAPC] set_apusys_apc done
9726 00:43:02.278498 INFO: [DEVAPC] devapc_init done
9727 00:43:02.281680 INFO: GICv3 without legacy support detected.
9728 00:43:02.284884 INFO: ARM GICv3 driver initialized in EL3
9729 00:43:02.288578 INFO: Maximum SPI INTID supported: 639
9730 00:43:02.295211 INFO: BL31: Initializing runtime services
9731 00:43:02.298288 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9732 00:43:02.302381 INFO: SPM: enable CPC mode
9733 00:43:02.307978 INFO: mcdi ready for mcusys-off-idle and system suspend
9734 00:43:02.311614 INFO: BL31: Preparing for EL3 exit to normal world
9735 00:43:02.315004 INFO: Entry point address = 0x80000000
9736 00:43:02.318332 INFO: SPSR = 0x8
9737 00:43:02.323582
9738 00:43:02.324183
9739 00:43:02.324549
9740 00:43:02.327015 Starting depthcharge on Spherion...
9741 00:43:02.327454
9742 00:43:02.327796 Wipe memory regions:
9743 00:43:02.328112
9744 00:43:02.330428 end: 2.2.3 depthcharge-start (duration 00:00:18) [common]
9745 00:43:02.330939 start: 2.2.4 bootloader-commands (timeout 00:04:28) [common]
9746 00:43:02.331374 Setting prompt string to ['asurada:']
9747 00:43:02.331931 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:28)
9748 00:43:02.332716 [0x00000040000000, 0x00000054600000)
9749 00:43:02.452284
9750 00:43:02.452798 [0x00000054660000, 0x00000080000000)
9751 00:43:02.713442
9752 00:43:02.714011 [0x000000821a7280, 0x000000ffe64000)
9753 00:43:03.457209
9754 00:43:03.457728 [0x00000100000000, 0x00000140000000)
9755 00:43:03.837889
9756 00:43:03.840663 Initializing XHCI USB controller at 0x11200000.
9757 00:43:04.879097
9758 00:43:04.882408 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
9759 00:43:04.882930
9760 00:43:04.883280
9761 00:43:04.884049 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9763 00:43:04.985280 asurada: tftpboot 192.168.201.1 14368387/tftp-deploy-2edglom8/kernel/image.itb 14368387/tftp-deploy-2edglom8/kernel/cmdline
9764 00:43:04.986042 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9765 00:43:04.986532 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:25)
9766 00:43:04.990970 tftpboot 192.168.201.1 14368387/tftp-deploy-2edglom8/kernel/image.itp-deploy-2edglom8/kernel/cmdline
9767 00:43:04.991418
9768 00:43:04.991758 Waiting for link
9769 00:43:05.149307
9770 00:43:05.149822 R8152: Initializing
9771 00:43:05.150168
9772 00:43:05.152899 Version 9 (ocp_data = 6010)
9773 00:43:05.153416
9774 00:43:05.156254 R8152: Done initializing
9775 00:43:05.156763
9776 00:43:05.157106 Adding net device
9777 00:43:07.097047
9778 00:43:07.097563 done.
9779 00:43:07.097903
9780 00:43:07.098245 MAC: 00:e0:4c:68:03:bd
9781 00:43:07.098568
9782 00:43:07.100591 Sending DHCP discover... done.
9783 00:43:07.101026
9784 00:43:07.103548 Waiting for reply... done.
9785 00:43:07.103992
9786 00:43:07.106793 Sending DHCP request... done.
9787 00:43:07.107229
9788 00:43:07.110303 Waiting for reply... done.
9789 00:43:07.110741
9790 00:43:07.111091 My ip is 192.168.201.16
9791 00:43:07.111401
9792 00:43:07.113461 The DHCP server ip is 192.168.201.1
9793 00:43:07.113893
9794 00:43:07.120277 TFTP server IP predefined by user: 192.168.201.1
9795 00:43:07.120727
9796 00:43:07.126700 Bootfile predefined by user: 14368387/tftp-deploy-2edglom8/kernel/image.itb
9797 00:43:07.127024
9798 00:43:07.130075 Sending tftp read request... done.
9799 00:43:07.130426
9800 00:43:07.135829 Waiting for the transfer...
9801 00:43:07.136101
9802 00:43:07.427105 00000000 ################################################################
9803 00:43:07.427226
9804 00:43:07.699640 00080000 ################################################################
9805 00:43:07.699755
9806 00:43:07.989594 00100000 ################################################################
9807 00:43:07.989712
9808 00:43:08.255319 00180000 ################################################################
9809 00:43:08.255428
9810 00:43:08.544267 00200000 ################################################################
9811 00:43:08.544376
9812 00:43:08.834120 00280000 ################################################################
9813 00:43:08.834265
9814 00:43:09.113683 00300000 ################################################################
9815 00:43:09.113800
9816 00:43:09.373433 00380000 ################################################################
9817 00:43:09.373544
9818 00:43:09.636582 00400000 ################################################################
9819 00:43:09.636695
9820 00:43:09.931022 00480000 ################################################################
9821 00:43:09.931132
9822 00:43:10.214333 00500000 ################################################################
9823 00:43:10.214444
9824 00:43:10.468138 00580000 ################################################################
9825 00:43:10.468249
9826 00:43:10.743557 00600000 ################################################################
9827 00:43:10.743665
9828 00:43:11.040197 00680000 ################################################################
9829 00:43:11.040306
9830 00:43:11.333342 00700000 ################################################################
9831 00:43:11.333456
9832 00:43:11.593679 00780000 ################################################################
9833 00:43:11.593790
9834 00:43:11.848972 00800000 ################################################################
9835 00:43:11.849079
9836 00:43:12.113953 00880000 ################################################################
9837 00:43:12.114067
9838 00:43:12.366427 00900000 ################################################################
9839 00:43:12.366540
9840 00:43:12.629616 00980000 ################################################################
9841 00:43:12.629733
9842 00:43:12.897458 00a00000 ################################################################
9843 00:43:12.897570
9844 00:43:13.162172 00a80000 ################################################################
9845 00:43:13.162287
9846 00:43:13.425027 00b00000 ################################################################
9847 00:43:13.425135
9848 00:43:13.685903 00b80000 ################################################################
9849 00:43:13.686012
9850 00:43:13.951035 00c00000 ################################################################
9851 00:43:13.951148
9852 00:43:14.202458 00c80000 ################################################################
9853 00:43:14.202568
9854 00:43:14.452854 00d00000 ################################################################
9855 00:43:14.452971
9856 00:43:14.703454 00d80000 ################################################################
9857 00:43:14.703569
9858 00:43:14.957705 00e00000 ################################################################
9859 00:43:14.957820
9860 00:43:15.234074 00e80000 ################################################################
9861 00:43:15.234187
9862 00:43:15.501962 00f00000 ################################################################
9863 00:43:15.502073
9864 00:43:15.763146 00f80000 ################################################################
9865 00:43:15.763255
9866 00:43:16.021170 01000000 ################################################################
9867 00:43:16.021300
9868 00:43:16.273069 01080000 ################################################################
9869 00:43:16.273180
9870 00:43:16.541700 01100000 ################################################################
9871 00:43:16.541813
9872 00:43:16.793497 01180000 ################################################################
9873 00:43:16.793604
9874 00:43:17.056457 01200000 ################################################################
9875 00:43:17.056572
9876 00:43:17.333955 01280000 ################################################################
9877 00:43:17.334066
9878 00:43:17.594892 01300000 ################################################################
9879 00:43:17.595008
9880 00:43:17.863063 01380000 ################################################################
9881 00:43:17.863183
9882 00:43:18.154424 01400000 ################################################################
9883 00:43:18.154545
9884 00:43:18.490263 01480000 ################################################################
9885 00:43:18.490509
9886 00:43:18.882884 01500000 ################################################################
9887 00:43:18.883329
9888 00:43:19.225972 01580000 ################################################################
9889 00:43:19.226096
9890 00:43:19.503094 01600000 ################################################################
9891 00:43:19.503248
9892 00:43:19.762359 01680000 ################################################################
9893 00:43:19.762527
9894 00:43:20.009299 01700000 ################################################################
9895 00:43:20.009413
9896 00:43:20.256270 01780000 ################################################################
9897 00:43:20.256411
9898 00:43:20.507342 01800000 ################################################################
9899 00:43:20.507484
9900 00:43:20.757308 01880000 ################################################################
9901 00:43:20.757428
9902 00:43:21.004927 01900000 ################################################################
9903 00:43:21.005070
9904 00:43:21.259466 01980000 ################################################################
9905 00:43:21.259621
9906 00:43:21.506946 01a00000 ################################################################
9907 00:43:21.507055
9908 00:43:21.753761 01a80000 ################################################################
9909 00:43:21.753900
9910 00:43:22.002373 01b00000 ################################################################
9911 00:43:22.002502
9912 00:43:22.248268 01b80000 ################################################################
9913 00:43:22.248415
9914 00:43:22.499410 01c00000 ################################################################
9915 00:43:22.499535
9916 00:43:22.750118 01c80000 ################################################################
9917 00:43:22.750307
9918 00:43:23.002251 01d00000 ################################################################
9919 00:43:23.002374
9920 00:43:23.253274 01d80000 ################################################################
9921 00:43:23.253394
9922 00:43:23.500915 01e00000 ################################################################
9923 00:43:23.501074
9924 00:43:23.751953 01e80000 ################################################################
9925 00:43:23.752093
9926 00:43:24.000331 01f00000 ################################################################
9927 00:43:24.000450
9928 00:43:24.257187 01f80000 ################################################################
9929 00:43:24.257324
9930 00:43:24.505112 02000000 ################################################################
9931 00:43:24.505263
9932 00:43:24.750551 02080000 ################################################################
9933 00:43:24.750678
9934 00:43:25.000068 02100000 ################################################################
9935 00:43:25.000202
9936 00:43:25.251429 02180000 ################################################################
9937 00:43:25.251577
9938 00:43:25.502331 02200000 ################################################################
9939 00:43:25.502446
9940 00:43:25.753135 02280000 ################################################################
9941 00:43:25.753285
9942 00:43:26.004530 02300000 ################################################################
9943 00:43:26.004650
9944 00:43:26.269999 02380000 ################################################################
9945 00:43:26.270121
9946 00:43:26.519896 02400000 ################################################################
9947 00:43:26.520030
9948 00:43:26.770609 02480000 ################################################################
9949 00:43:26.770719
9950 00:43:27.030369 02500000 ################################################################
9951 00:43:27.030489
9952 00:43:27.296949 02580000 ################################################################
9953 00:43:27.297062
9954 00:43:27.568079 02600000 ################################################################
9955 00:43:27.568199
9956 00:43:27.841369 02680000 ################################################################
9957 00:43:27.841495
9958 00:43:28.115007 02700000 ################################################################
9959 00:43:28.115133
9960 00:43:28.365655 02780000 ################################################################
9961 00:43:28.365779
9962 00:43:28.614358 02800000 ################################################################
9963 00:43:28.614473
9964 00:43:28.864651 02880000 ################################################################
9965 00:43:28.864774
9966 00:43:29.113320 02900000 ################################################################
9967 00:43:29.113440
9968 00:43:29.364132 02980000 ################################################################
9969 00:43:29.364248
9970 00:43:29.613547 02a00000 ################################################################
9971 00:43:29.613669
9972 00:43:29.863996 02a80000 ################################################################
9973 00:43:29.864115
9974 00:43:30.114561 02b00000 ################################################################
9975 00:43:30.114676
9976 00:43:30.365715 02b80000 ################################################################
9977 00:43:30.365833
9978 00:43:30.623285 02c00000 ################################################################
9979 00:43:30.623403
9980 00:43:30.880226 02c80000 ################################################################
9981 00:43:30.880342
9982 00:43:31.131151 02d00000 ################################################################
9983 00:43:31.131266
9984 00:43:31.387909 02d80000 ################################################################
9985 00:43:31.388020
9986 00:43:31.639424 02e00000 ################################################################
9987 00:43:31.639537
9988 00:43:31.887404 02e80000 ################################################################
9989 00:43:31.887530
9990 00:43:32.135279 02f00000 ################################################################
9991 00:43:32.135393
9992 00:43:32.388560 02f80000 ################################################################
9993 00:43:32.388673
9994 00:43:32.638897 03000000 ################################################################
9995 00:43:32.639025
9996 00:43:32.889572 03080000 ################################################################
9997 00:43:32.889683
9998 00:43:33.140671 03100000 ################################################################
9999 00:43:33.140807
10000 00:43:33.402429 03180000 ################################################################
10001 00:43:33.402546
10002 00:43:33.649186 03200000 ################################################################
10003 00:43:33.649314
10004 00:43:33.896017 03280000 ################################################################
10005 00:43:33.896147
10006 00:43:34.141890 03300000 ################################################################
10007 00:43:34.142032
10008 00:43:34.389845 03380000 ################################################################
10009 00:43:34.390008
10010 00:43:34.638602 03400000 ################################################################
10011 00:43:34.638739
10012 00:43:34.889029 03480000 ################################################################
10013 00:43:34.889157
10014 00:43:35.140836 03500000 ################################################################
10015 00:43:35.141007
10016 00:43:35.391485 03580000 ################################################################
10017 00:43:35.391605
10018 00:43:35.641504 03600000 ################################################################
10019 00:43:35.641631
10020 00:43:35.891187 03680000 ################################################################
10021 00:43:35.891300
10022 00:43:36.142199 03700000 ################################################################
10023 00:43:36.142334
10024 00:43:36.454115 03780000 ################################################################
10025 00:43:36.454617
10026 00:43:36.826983 03800000 ################################################################
10027 00:43:36.827109
10028 00:43:37.127506 03880000 ################################################################
10029 00:43:37.127625
10030 00:43:37.420946 03900000 ################################################################
10031 00:43:37.421058
10032 00:43:37.701560 03980000 ################################################################
10033 00:43:37.701670
10034 00:43:37.961987 03a00000 ################################################################
10035 00:43:37.962124
10036 00:43:38.214671 03a80000 ################################################################
10037 00:43:38.214780
10038 00:43:38.502134 03b00000 ################################################################
10039 00:43:38.502268
10040 00:43:38.788653 03b80000 ################################################################
10041 00:43:38.788792
10042 00:43:39.161378 03c00000 ################################################################
10043 00:43:39.161844
10044 00:43:39.549622 03c80000 ################################################################
10045 00:43:39.549753
10046 00:43:39.839041 03d00000 ################################################################
10047 00:43:39.839156
10048 00:43:40.128483 03d80000 ################################################################
10049 00:43:40.128599
10050 00:43:40.292105 03e00000 ##################################### done.
10051 00:43:40.292210
10052 00:43:40.295617 The bootfile was 65313930 bytes long.
10053 00:43:40.295690
10054 00:43:40.298886 Sending tftp read request... done.
10055 00:43:40.298970
10056 00:43:40.299034 Waiting for the transfer...
10057 00:43:40.299093
10058 00:43:40.301944 00000000 # done.
10059 00:43:40.302024
10060 00:43:40.308961 Command line loaded dynamically from TFTP file: 14368387/tftp-deploy-2edglom8/kernel/cmdline
10061 00:43:40.309555
10062 00:43:40.322001 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10063 00:43:40.322578
10064 00:43:40.325644 Loading FIT.
10065 00:43:40.326076
10066 00:43:40.328737 Image ramdisk-1 has 52138269 bytes.
10067 00:43:40.329147
10068 00:43:40.331856 Image fdt-1 has 47258 bytes.
10069 00:43:40.332255
10070 00:43:40.332557 Image kernel-1 has 13126376 bytes.
10071 00:43:40.335055
10072 00:43:40.341617 Compat preference: google,spherion-rev3-sku1 google,spherion-rev3 google,spherion-sku1 google,spherion
10073 00:43:40.342011
10074 00:43:40.361887 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 (match) google,spherion-rev2 google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10075 00:43:40.362371
10076 00:43:40.364916 Choosing best match conf-1 for compat google,spherion-rev3.
10077 00:43:40.369526
10078 00:43:40.374485 Connected to device vid:did:rid of 1ae0:0028:00
10079 00:43:40.381336
10080 00:43:40.384807 tpm_get_response: command 0x17b, return code 0x0
10081 00:43:40.385202
10082 00:43:40.387609 ec_init: CrosEC protocol v3 supported (256, 248)
10083 00:43:40.392033
10084 00:43:40.395264 tpm_cleanup: add release locality here.
10085 00:43:40.395657
10086 00:43:40.395962 Shutting down all USB controllers.
10087 00:43:40.398432
10088 00:43:40.398820 Removing current net device
10089 00:43:40.399123
10090 00:43:40.405392 Exiting depthcharge with code 4 at timestamp: 66317825
10091 00:43:40.405783
10092 00:43:40.409017 LZMA decompressing kernel-1 to 0x821a6718
10093 00:43:40.409496
10094 00:43:40.412389 LZMA decompressing kernel-1 to 0x40000000
10095 00:43:42.028022
10096 00:43:42.028535 jumping to kernel
10097 00:43:42.030669 end: 2.2.4 bootloader-commands (duration 00:00:40) [common]
10098 00:43:42.031172 start: 2.2.5 auto-login-action (timeout 00:03:48) [common]
10099 00:43:42.031556 Setting prompt string to ['Linux version [0-9]']
10100 00:43:42.031902 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10101 00:43:42.032251 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10102 00:43:42.078059
10103 00:43:42.081681 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10104 00:43:42.085264 start: 2.2.5.1 login-action (timeout 00:03:48) [common]
10105 00:43:42.085839 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10106 00:43:42.086260 Setting prompt string to []
10107 00:43:42.086669 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10108 00:43:42.087039 Using line separator: #'\n'#
10109 00:43:42.087345 No login prompt set.
10110 00:43:42.087669 Parsing kernel messages
10111 00:43:42.088041 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10112 00:43:42.088577 [login-action] Waiting for messages, (timeout 00:03:48)
10113 00:43:42.088928 Waiting using forced prompt support (timeout 00:01:54)
10114 00:43:42.104980 [ 0.000000] Linux version 6.1.92-cip22 (KernelCI@build-j232175-arm64-gcc-10-defconfig-arm64-chromebook-7lg8d) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sun Jun 16 00:28:47 UTC 2024
10115 00:43:42.107765 [ 0.000000] random: crng init done
10116 00:43:42.114653 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10117 00:43:42.118339 [ 0.000000] efi: UEFI not found.
10118 00:43:42.124617 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10119 00:43:42.134248 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10120 00:43:42.140725 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10121 00:43:42.150856 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10122 00:43:42.157325 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10123 00:43:42.163928 [ 0.000000] printk: bootconsole [mtk8250] enabled
10124 00:43:42.170190 [ 0.000000] NUMA: No NUMA configuration found
10125 00:43:42.176752 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000013fffffff]
10126 00:43:42.183485 [ 0.000000] NUMA: NODE_DATA [mem 0x13f7d5a00-0x13f7d7fff]
10127 00:43:42.183989 [ 0.000000] Zone ranges:
10128 00:43:42.190310 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10129 00:43:42.193831 [ 0.000000] DMA32 empty
10130 00:43:42.200588 [ 0.000000] Normal [mem 0x0000000100000000-0x000000013fffffff]
10131 00:43:42.203784 [ 0.000000] Movable zone start for each node
10132 00:43:42.206919 [ 0.000000] Early memory node ranges
10133 00:43:42.213777 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10134 00:43:42.220608 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10135 00:43:42.227147 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10136 00:43:42.233490 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10137 00:43:42.240043 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000013fffffff]
10138 00:43:42.246917 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000013fffffff]
10139 00:43:42.276460 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10140 00:43:42.283166 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10141 00:43:42.290023 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10142 00:43:42.293082 [ 0.000000] psci: probing for conduit method from DT.
10143 00:43:42.299383 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10144 00:43:42.302887 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10145 00:43:42.309470 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10146 00:43:42.312691 [ 0.000000] psci: SMC Calling Convention v1.2
10147 00:43:42.319544 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10148 00:43:42.322462 [ 0.000000] Detected VIPT I-cache on CPU0
10149 00:43:42.329461 [ 0.000000] CPU features: detected: GIC system register CPU interface
10150 00:43:42.335710 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10151 00:43:42.342425 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10152 00:43:42.349298 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10153 00:43:42.359218 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10154 00:43:42.365822 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10155 00:43:42.368942 [ 0.000000] alternatives: applying boot alternatives
10156 00:43:42.375594 [ 0.000000] Fallback order for Node 0: 0
10157 00:43:42.382165 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1031424
10158 00:43:42.385261 [ 0.000000] Policy zone: Normal
10159 00:43:42.398763 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10160 00:43:42.408596 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10161 00:43:42.419623 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10162 00:43:42.429169 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
10163 00:43:42.435487 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10164 00:43:42.439015 <6>[ 0.000000] software IO TLB: area num 8.
10165 00:43:42.494702 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10166 00:43:42.574891 <6>[ 0.000000] Memory: 3798728K/4191232K available (18112K kernel code, 4120K rwdata, 22644K rodata, 8512K init, 616K bss, 359736K reserved, 32768K cma-reserved)
10167 00:43:42.581688 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10168 00:43:42.588195 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10169 00:43:42.591441 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10170 00:43:42.598208 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10171 00:43:42.604486 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10172 00:43:42.607944 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10173 00:43:42.617478 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10174 00:43:42.624431 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10175 00:43:42.630796 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10176 00:43:42.637991 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10177 00:43:42.640795 <6>[ 0.000000] GICv3: 608 SPIs implemented
10178 00:43:42.644037 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10179 00:43:42.650429 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10180 00:43:42.653983 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10181 00:43:42.660630 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10182 00:43:42.674009 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10183 00:43:42.686871 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10184 00:43:42.693347 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10185 00:43:42.701274 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10186 00:43:42.714405 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10187 00:43:42.721345 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10188 00:43:42.727880 <6>[ 0.009228] Console: colour dummy device 80x25
10189 00:43:42.738118 <6>[ 0.013954] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10190 00:43:42.744595 <6>[ 0.024396] pid_max: default: 32768 minimum: 301
10191 00:43:42.747587 <6>[ 0.029267] LSM: Security Framework initializing
10192 00:43:42.754842 <6>[ 0.034180] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10193 00:43:42.764452 <6>[ 0.041787] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10194 00:43:42.770728 <6>[ 0.051066] cblist_init_generic: Setting adjustable number of callback queues.
10195 00:43:42.777771 <6>[ 0.058555] cblist_init_generic: Setting shift to 3 and lim to 1.
10196 00:43:42.787554 <6>[ 0.064933] cblist_init_generic: Setting adjustable number of callback queues.
10197 00:43:42.790919 <6>[ 0.072359] cblist_init_generic: Setting shift to 3 and lim to 1.
10198 00:43:42.797591 <6>[ 0.078796] rcu: Hierarchical SRCU implementation.
10199 00:43:42.804260 <6>[ 0.083842] rcu: Max phase no-delay instances is 1000.
10200 00:43:42.811148 <6>[ 0.090860] EFI services will not be available.
10201 00:43:42.813959 <6>[ 0.095816] smp: Bringing up secondary CPUs ...
10202 00:43:42.821706 <6>[ 0.100868] Detected VIPT I-cache on CPU1
10203 00:43:42.828840 <6>[ 0.100937] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10204 00:43:42.835262 <6>[ 0.100969] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10205 00:43:42.838386 <6>[ 0.101304] Detected VIPT I-cache on CPU2
10206 00:43:42.848253 <6>[ 0.101356] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10207 00:43:42.855073 <6>[ 0.101375] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10208 00:43:42.857950 <6>[ 0.101635] Detected VIPT I-cache on CPU3
10209 00:43:42.864973 <6>[ 0.101684] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10210 00:43:42.871352 <6>[ 0.101699] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10211 00:43:42.877647 <6>[ 0.102001] CPU features: detected: Spectre-v4
10212 00:43:42.881318 <6>[ 0.102007] CPU features: detected: Spectre-BHB
10213 00:43:42.884638 <6>[ 0.102012] Detected PIPT I-cache on CPU4
10214 00:43:42.891026 <6>[ 0.102074] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10215 00:43:42.897664 <6>[ 0.102091] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10216 00:43:42.904226 <6>[ 0.102385] Detected PIPT I-cache on CPU5
10217 00:43:42.910837 <6>[ 0.102447] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10218 00:43:42.917680 <6>[ 0.102464] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10219 00:43:42.920814 <6>[ 0.102746] Detected PIPT I-cache on CPU6
10220 00:43:42.927437 <6>[ 0.102808] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10221 00:43:42.937241 <6>[ 0.102824] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10222 00:43:42.940789 <6>[ 0.103125] Detected PIPT I-cache on CPU7
10223 00:43:42.947070 <6>[ 0.103191] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10224 00:43:42.953662 <6>[ 0.103208] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10225 00:43:42.957213 <6>[ 0.103255] smp: Brought up 1 node, 8 CPUs
10226 00:43:42.963750 <6>[ 0.244665] SMP: Total of 8 processors activated.
10227 00:43:42.967380 <6>[ 0.249586] CPU features: detected: 32-bit EL0 Support
10228 00:43:42.977067 <6>[ 0.254949] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10229 00:43:42.983927 <6>[ 0.263750] CPU features: detected: Common not Private translations
10230 00:43:42.990355 <6>[ 0.270266] CPU features: detected: CRC32 instructions
10231 00:43:42.996868 <6>[ 0.275617] CPU features: detected: RCpc load-acquire (LDAPR)
10232 00:43:42.999950 <6>[ 0.281577] CPU features: detected: LSE atomic instructions
10233 00:43:43.006523 <6>[ 0.287395] CPU features: detected: Privileged Access Never
10234 00:43:43.013684 <6>[ 0.293174] CPU features: detected: RAS Extension Support
10235 00:43:43.020118 <6>[ 0.298783] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10236 00:43:43.023153 <6>[ 0.306046] CPU: All CPU(s) started at EL2
10237 00:43:43.029749 <6>[ 0.310390] alternatives: applying system-wide alternatives
10238 00:43:43.039189 <6>[ 0.320419] devtmpfs: initialized
10239 00:43:43.053949 <6>[ 0.328677] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10240 00:43:43.060642 <6>[ 0.338639] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10241 00:43:43.066938 <6>[ 0.346866] pinctrl core: initialized pinctrl subsystem
10242 00:43:43.070815 <6>[ 0.353563] DMI not present or invalid.
10243 00:43:43.076746 <6>[ 0.357884] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10244 00:43:43.086759 <6>[ 0.364752] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
10245 00:43:43.093433 <6>[ 0.372202] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10246 00:43:43.103257 <6>[ 0.380299] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10247 00:43:43.107155 <6>[ 0.388455] audit: initializing netlink subsys (disabled)
10248 00:43:43.116498 <5>[ 0.394152] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10249 00:43:43.122924 <6>[ 0.394860] thermal_sys: Registered thermal governor 'step_wise'
10250 00:43:43.129775 <6>[ 0.402119] thermal_sys: Registered thermal governor 'power_allocator'
10251 00:43:43.132650 <6>[ 0.408373] cpuidle: using governor menu
10252 00:43:43.139484 <6>[ 0.419333] NET: Registered PF_QIPCRTR protocol family
10253 00:43:43.146426 <6>[ 0.424780] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10254 00:43:43.149524 <6>[ 0.431877] ASID allocator initialised with 32768 entries
10255 00:43:43.157171 <6>[ 0.438442] Serial: AMBA PL011 UART driver
10256 00:43:43.166107 <4>[ 0.447259] Trying to register duplicate clock ID: 134
10257 00:43:43.224182 <6>[ 0.508838] KASLR enabled
10258 00:43:43.238534 <6>[ 0.516625] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10259 00:43:43.245193 <6>[ 0.523642] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10260 00:43:43.251704 <6>[ 0.530130] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10261 00:43:43.258365 <6>[ 0.537134] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10262 00:43:43.265349 <6>[ 0.543619] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10263 00:43:43.271611 <6>[ 0.550623] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10264 00:43:43.278306 <6>[ 0.557109] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10265 00:43:43.284828 <6>[ 0.564113] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10266 00:43:43.288292 <6>[ 0.571617] ACPI: Interpreter disabled.
10267 00:43:43.296885 <6>[ 0.578037] iommu: Default domain type: Translated
10268 00:43:43.303528 <6>[ 0.583150] iommu: DMA domain TLB invalidation policy: strict mode
10269 00:43:43.306947 <5>[ 0.589812] SCSI subsystem initialized
10270 00:43:43.313464 <6>[ 0.593981] usbcore: registered new interface driver usbfs
10271 00:43:43.319823 <6>[ 0.599713] usbcore: registered new interface driver hub
10272 00:43:43.322730 <6>[ 0.605264] usbcore: registered new device driver usb
10273 00:43:43.330369 <6>[ 0.611356] pps_core: LinuxPPS API ver. 1 registered
10274 00:43:43.339631 <6>[ 0.616549] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10275 00:43:43.343137 <6>[ 0.625893] PTP clock support registered
10276 00:43:43.346492 <6>[ 0.630137] EDAC MC: Ver: 3.0.0
10277 00:43:43.354127 <6>[ 0.635284] FPGA manager framework
10278 00:43:43.360502 <6>[ 0.638971] Advanced Linux Sound Architecture Driver Initialized.
10279 00:43:43.363557 <6>[ 0.645745] vgaarb: loaded
10280 00:43:43.370499 <6>[ 0.648886] clocksource: Switched to clocksource arch_sys_counter
10281 00:43:43.373632 <5>[ 0.655323] VFS: Disk quotas dquot_6.6.0
10282 00:43:43.380344 <6>[ 0.659506] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10283 00:43:43.383693 <6>[ 0.666696] pnp: PnP ACPI: disabled
10284 00:43:43.391974 <6>[ 0.673455] NET: Registered PF_INET protocol family
10285 00:43:43.398616 <6>[ 0.678832] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
10286 00:43:43.411147 <6>[ 0.688845] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
10287 00:43:43.420791 <6>[ 0.697634] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10288 00:43:43.427377 <6>[ 0.705603] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
10289 00:43:43.434116 <6>[ 0.714005] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear)
10290 00:43:43.444584 <6>[ 0.722660] TCP: Hash tables configured (established 32768 bind 32768)
10291 00:43:43.451052 <6>[ 0.729520] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear)
10292 00:43:43.457633 <6>[ 0.736539] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear)
10293 00:43:43.464344 <6>[ 0.744062] NET: Registered PF_UNIX/PF_LOCAL protocol family
10294 00:43:43.470867 <6>[ 0.750187] RPC: Registered named UNIX socket transport module.
10295 00:43:43.474465 <6>[ 0.756343] RPC: Registered udp transport module.
10296 00:43:43.480921 <6>[ 0.761275] RPC: Registered tcp transport module.
10297 00:43:43.487491 <6>[ 0.766205] RPC: Registered tcp NFSv4.1 backchannel transport module.
10298 00:43:43.490662 <6>[ 0.772872] PCI: CLS 0 bytes, default 64
10299 00:43:43.494050 <6>[ 0.777141] Unpacking initramfs...
10300 00:43:43.519375 <6>[ 0.797474] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10301 00:43:43.529117 <6>[ 0.806117] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10302 00:43:43.532286 <6>[ 0.814975] kvm [1]: IPA Size Limit: 40 bits
10303 00:43:43.539008 <6>[ 0.819502] kvm [1]: GICv3: no GICV resource entry
10304 00:43:43.542429 <6>[ 0.824525] kvm [1]: disabling GICv2 emulation
10305 00:43:43.549063 <6>[ 0.829213] kvm [1]: GIC system register CPU interface enabled
10306 00:43:43.552095 <6>[ 0.835376] kvm [1]: vgic interrupt IRQ18
10307 00:43:43.559205 <6>[ 0.839727] kvm [1]: VHE mode initialized successfully
10308 00:43:43.565399 <5>[ 0.846154] Initialise system trusted keyrings
10309 00:43:43.571991 <6>[ 0.850939] workingset: timestamp_bits=42 max_order=20 bucket_order=0
10310 00:43:43.579534 <6>[ 0.860946] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10311 00:43:43.585828 <5>[ 0.867335] NFS: Registering the id_resolver key type
10312 00:43:43.588983 <5>[ 0.872638] Key type id_resolver registered
10313 00:43:43.595688 <5>[ 0.877054] Key type id_legacy registered
10314 00:43:43.602720 <6>[ 0.881351] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10315 00:43:43.609492 <6>[ 0.888275] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10316 00:43:43.615596 <6>[ 0.895979] 9p: Installing v9fs 9p2000 file system support
10317 00:43:43.652784 <5>[ 0.933843] Key type asymmetric registered
10318 00:43:43.655485 <5>[ 0.938176] Asymmetric key parser 'x509' registered
10319 00:43:43.665759 <6>[ 0.943349] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10320 00:43:43.669057 <6>[ 0.950985] io scheduler mq-deadline registered
10321 00:43:43.672333 <6>[ 0.955749] io scheduler kyber registered
10322 00:43:43.691173 <6>[ 0.972569] EINJ: ACPI disabled.
10323 00:43:43.724058 <4>[ 0.998359] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10324 00:43:43.733632 <4>[ 1.008997] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10325 00:43:43.748151 <6>[ 1.029633] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10326 00:43:43.756331 <6>[ 1.037584] printk: console [ttyS0] disabled
10327 00:43:43.783830 <6>[ 1.062209] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10328 00:43:43.790778 <6>[ 1.071680] printk: console [ttyS0] enabled
10329 00:43:43.794350 <6>[ 1.071680] printk: console [ttyS0] enabled
10330 00:43:43.800865 <6>[ 1.080574] printk: bootconsole [mtk8250] disabled
10331 00:43:43.804032 <6>[ 1.080574] printk: bootconsole [mtk8250] disabled
10332 00:43:43.810552 <6>[ 1.091596] SuperH (H)SCI(F) driver initialized
10333 00:43:43.813701 <6>[ 1.096858] msm_serial: driver initialized
10334 00:43:43.827604 <6>[ 1.105742] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10335 00:43:43.837474 <6>[ 1.114288] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10336 00:43:43.844012 <6>[ 1.122829] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10337 00:43:43.854110 <6>[ 1.131457] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10338 00:43:43.860604 <6>[ 1.140164] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10339 00:43:43.870735 <6>[ 1.148880] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10340 00:43:43.880447 <6>[ 1.157420] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10341 00:43:43.887243 <6>[ 1.166217] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10342 00:43:43.897172 <6>[ 1.174769] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10343 00:43:43.909136 <6>[ 1.190577] loop: module loaded
10344 00:43:43.915646 <6>[ 1.196460] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10345 00:43:43.938649 <4>[ 1.219812] mtk-pmic-keys: Failed to locate of_node [id: -1]
10346 00:43:43.945054 <6>[ 1.226605] megasas: 07.719.03.00-rc1
10347 00:43:43.954951 <6>[ 1.236284] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10348 00:43:43.966942 <6>[ 1.248261] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10349 00:43:43.983839 <6>[ 1.264926] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10350 00:43:44.040311 <6>[ 1.314727] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2
10351 00:43:45.719330 <6>[ 3.000799] Freeing initrd memory: 50912K
10352 00:43:45.731085 <6>[ 3.012507] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10353 00:43:45.741709 <6>[ 3.023479] tun: Universal TUN/TAP device driver, 1.6
10354 00:43:45.745336 <6>[ 3.029564] thunder_xcv, ver 1.0
10355 00:43:45.748781 <6>[ 3.033067] thunder_bgx, ver 1.0
10356 00:43:45.752047 <6>[ 3.036560] nicpf, ver 1.0
10357 00:43:45.762326 <6>[ 3.040584] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10358 00:43:45.765220 <6>[ 3.048061] hns3: Copyright (c) 2017 Huawei Corporation.
10359 00:43:45.772279 <6>[ 3.053651] hclge is initializing
10360 00:43:45.775339 <6>[ 3.057233] e1000: Intel(R) PRO/1000 Network Driver
10361 00:43:45.782320 <6>[ 3.062362] e1000: Copyright (c) 1999-2006 Intel Corporation.
10362 00:43:45.785646 <6>[ 3.068378] e1000e: Intel(R) PRO/1000 Network Driver
10363 00:43:45.792425 <6>[ 3.073594] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10364 00:43:45.798955 <6>[ 3.079779] igb: Intel(R) Gigabit Ethernet Network Driver
10365 00:43:45.805667 <6>[ 3.085429] igb: Copyright (c) 2007-2014 Intel Corporation.
10366 00:43:45.812130 <6>[ 3.091265] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10367 00:43:45.818374 <6>[ 3.097783] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10368 00:43:45.822071 <6>[ 3.104243] sky2: driver version 1.30
10369 00:43:45.828526 <6>[ 3.109178] usbcore: registered new device driver r8152-cfgselector
10370 00:43:45.835140 <6>[ 3.115718] usbcore: registered new interface driver r8152
10371 00:43:45.841322 <6>[ 3.121543] VFIO - User Level meta-driver version: 0.3
10372 00:43:45.848274 <6>[ 3.129784] usbcore: registered new interface driver usb-storage
10373 00:43:45.854891 <6>[ 3.136230] usbcore: registered new device driver onboard-usb-hub
10374 00:43:45.863706 <6>[ 3.145424] mt6397-rtc mt6359-rtc: registered as rtc0
10375 00:43:45.874179 <6>[ 3.150891] mt6397-rtc mt6359-rtc: setting system clock to 2024-06-16T00:43:45 UTC (1718498625)
10376 00:43:45.876927 <6>[ 3.160459] i2c_dev: i2c /dev entries driver
10377 00:43:45.890977 <4>[ 3.172581] cpu cpu0: supply cpu not found, using dummy regulator
10378 00:43:45.897641 <4>[ 3.179003] cpu cpu1: supply cpu not found, using dummy regulator
10379 00:43:45.904623 <4>[ 3.185422] cpu cpu2: supply cpu not found, using dummy regulator
10380 00:43:45.911060 <4>[ 3.191822] cpu cpu3: supply cpu not found, using dummy regulator
10381 00:43:45.917263 <4>[ 3.198227] cpu cpu4: supply cpu not found, using dummy regulator
10382 00:43:45.924206 <4>[ 3.204638] cpu cpu5: supply cpu not found, using dummy regulator
10383 00:43:45.930900 <4>[ 3.211040] cpu cpu6: supply cpu not found, using dummy regulator
10384 00:43:45.937303 <4>[ 3.217435] cpu cpu7: supply cpu not found, using dummy regulator
10385 00:43:45.956211 <6>[ 3.238063] cpu cpu0: EM: created perf domain
10386 00:43:45.959695 <6>[ 3.242991] cpu cpu4: EM: created perf domain
10387 00:43:45.966613 <6>[ 3.248566] sdhci: Secure Digital Host Controller Interface driver
10388 00:43:45.973391 <6>[ 3.254997] sdhci: Copyright(c) Pierre Ossman
10389 00:43:45.980071 <6>[ 3.259909] Synopsys Designware Multimedia Card Interface Driver
10390 00:43:45.986736 <6>[ 3.266510] sdhci-pltfm: SDHCI platform and OF driver helper
10391 00:43:45.990761 <6>[ 3.266587] mmc0: CQHCI version 5.10
10392 00:43:45.996713 <6>[ 3.276475] ledtrig-cpu: registered to indicate activity on CPUs
10393 00:43:46.003275 <6>[ 3.283549] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10394 00:43:46.010195 <6>[ 3.290547] usbcore: registered new interface driver usbhid
10395 00:43:46.013237 <6>[ 3.296367] usbhid: USB HID core driver
10396 00:43:46.020240 <6>[ 3.300568] spi_master spi0: will run message pump with realtime priority
10397 00:43:46.065923 <6>[ 3.340988] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10398 00:43:46.085247 <6>[ 3.356622] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10399 00:43:46.091722 <6>[ 3.371615] cros-ec-spi spi0.0: Chrome EC device registered
10400 00:43:46.098345 <6>[ 3.372339] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x15014
10401 00:43:46.106698 <6>[ 3.388130] mmc0: Command Queue Engine enabled
10402 00:43:46.116279 <6>[ 3.391011] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10403 00:43:46.123072 <6>[ 3.392872] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10404 00:43:46.126586 <6>[ 3.403076] NET: Registered PF_PACKET protocol family
10405 00:43:46.133255 <6>[ 3.409281] mmcblk0: mmc0:0001 DA4064 58.2 GiB
10406 00:43:46.135910 <6>[ 3.414123] 9pnet: Installing 9P2000 support
10407 00:43:46.142393 <5>[ 3.423388] Key type dns_resolver registered
10408 00:43:46.149338 <6>[ 3.428462] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10409 00:43:46.152595 <6>[ 3.428471] registered taskstats version 1
10410 00:43:46.155865 <6>[ 3.435977] mmcblk0boot0: mmc0:0001 DA4064 4.00 MiB
10411 00:43:46.162466 <5>[ 3.438771] Loading compiled-in X.509 certificates
10412 00:43:46.168946 <6>[ 3.450397] mmcblk0boot1: mmc0:0001 DA4064 4.00 MiB
10413 00:43:46.178913 <4>[ 3.455188] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10414 00:43:46.185591 <6>[ 3.456392] mmcblk0rpmb: mmc0:0001 DA4064 16.0 MiB, chardev (507:0)
10415 00:43:46.195230 <4>[ 3.466356] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10416 00:43:46.211875 <6>[ 3.493481] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10417 00:43:46.218551 <6>[ 3.500361] xhci-mtk 11200000.usb: xHCI Host Controller
10418 00:43:46.225859 <6>[ 3.505870] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10419 00:43:46.235411 <6>[ 3.513709] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10420 00:43:46.241885 <6>[ 3.523134] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10421 00:43:46.248679 <6>[ 3.529223] xhci-mtk 11200000.usb: xHCI Host Controller
10422 00:43:46.255152 <6>[ 3.534707] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10423 00:43:46.261468 <6>[ 3.542364] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10424 00:43:46.268202 <6>[ 3.549970] hub 1-0:1.0: USB hub found
10425 00:43:46.271605 <6>[ 3.553987] hub 1-0:1.0: 1 port detected
10426 00:43:46.278596 <6>[ 3.558268] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10427 00:43:46.284902 <6>[ 3.566787] hub 2-0:1.0: USB hub found
10428 00:43:46.288933 <6>[ 3.570795] hub 2-0:1.0: 1 port detected
10429 00:43:46.295634 <6>[ 3.577445] mtk-msdc 11f70000.mmc: Got CD GPIO
10430 00:43:46.308717 <6>[ 3.587367] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10431 00:43:46.318946 <6>[ 3.595749] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10432 00:43:46.325299 <6>[ 3.604091] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10433 00:43:46.335305 <6>[ 3.612437] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10434 00:43:46.341656 <6>[ 3.620775] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10435 00:43:46.351854 <6>[ 3.629113] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10436 00:43:46.358615 <6>[ 3.637451] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10437 00:43:46.368621 <6>[ 3.645790] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10438 00:43:46.374812 <6>[ 3.654127] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10439 00:43:46.384761 <6>[ 3.662465] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10440 00:43:46.391304 <6>[ 3.670803] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10441 00:43:46.401302 <6>[ 3.679150] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10442 00:43:46.407903 <6>[ 3.687489] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10443 00:43:46.417756 <6>[ 3.695826] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10444 00:43:46.424568 <6>[ 3.704164] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10445 00:43:46.430893 <6>[ 3.712857] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10446 00:43:46.437807 <6>[ 3.720008] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10447 00:43:46.445314 <6>[ 3.726740] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10448 00:43:46.454996 <6>[ 3.733518] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10449 00:43:46.461504 <6>[ 3.740443] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10450 00:43:46.468599 <6>[ 3.747283] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10451 00:43:46.478074 <6>[ 3.756416] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10452 00:43:46.488366 <6>[ 3.765535] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10453 00:43:46.497769 <6>[ 3.774829] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10454 00:43:46.507792 <6>[ 3.784296] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10455 00:43:46.514701 <6>[ 3.793762] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10456 00:43:46.524674 <6>[ 3.802881] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10457 00:43:46.534479 <6>[ 3.812347] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10458 00:43:46.544247 <6>[ 3.821465] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10459 00:43:46.554361 <6>[ 3.830761] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10460 00:43:46.563773 <6>[ 3.840921] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10461 00:43:46.574339 <6>[ 3.852567] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10462 00:43:46.690577 <6>[ 3.969159] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10463 00:43:46.844678 <6>[ 4.126601] hub 1-1:1.0: USB hub found
10464 00:43:46.847905 <6>[ 4.131142] hub 1-1:1.0: 4 ports detected
10465 00:43:46.859398 <6>[ 4.140918] hub 1-1:1.0: USB hub found
10466 00:43:46.862604 <6>[ 4.145306] hub 1-1:1.0: 4 ports detected
10467 00:43:46.970948 <6>[ 4.249516] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10468 00:43:46.997148 <6>[ 4.279067] hub 2-1:1.0: USB hub found
10469 00:43:47.000663 <6>[ 4.283560] hub 2-1:1.0: 3 ports detected
10470 00:43:47.012327 <6>[ 4.294039] hub 2-1:1.0: USB hub found
10471 00:43:47.015517 <6>[ 4.298496] hub 2-1:1.0: 3 ports detected
10472 00:43:47.182525 <6>[ 4.461199] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10473 00:43:47.315178 <6>[ 4.596767] hub 1-1.4:1.0: USB hub found
10474 00:43:47.318392 <6>[ 4.601429] hub 1-1.4:1.0: 2 ports detected
10475 00:43:47.332326 <6>[ 4.614307] hub 1-1.4:1.0: USB hub found
10476 00:43:47.335487 <6>[ 4.618943] hub 1-1.4:1.0: 2 ports detected
10477 00:43:47.402844 <6>[ 4.681407] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10478 00:43:47.511651 <6>[ 4.789832] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10479 00:43:47.567593 <6>[ 4.846518] r8152 2-1.3:1.0: load rtl8153b-2 v1 10/23/19 successfully
10480 00:43:47.608458 <6>[ 4.890583] r8152 2-1.3:1.0 eth0: v1.12.13
10481 00:43:47.634069 <6>[ 4.913021] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10482 00:43:47.826538 <6>[ 5.105192] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10483 00:43:49.215639 <6>[ 6.497724] r8152 2-1.3:1.0 eth0: carrier on
10484 00:43:51.878373 <5>[ 6.528979] Sending DHCP requests .., OK
10485 00:43:51.885069 <6>[ 9.165318] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.16
10486 00:43:51.888321 <6>[ 9.173614] IP-Config: Complete:
10487 00:43:51.901876 <6>[ 9.177111] device=eth0, hwaddr=00:e0:4c:68:03:bd, ipaddr=192.168.201.16, mask=255.255.255.0, gw=192.168.201.1
10488 00:43:51.908498 <6>[ 9.187820] host=mt8192-asurada-spherion-r0-cbg-4, domain=lava-rack, nis-domain=(none)
10489 00:43:51.914898 <6>[ 9.196436] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10490 00:43:51.921848 <6>[ 9.196445] nameserver0=192.168.201.1
10491 00:43:51.924789 <6>[ 9.208595] clk: Disabling unused clocks
10492 00:43:51.928351 <6>[ 9.214125] ALSA device list:
10493 00:43:51.934806 <6>[ 9.217404] No soundcards found.
10494 00:43:51.942329 <6>[ 9.225027] Freeing unused kernel memory: 8512K
10495 00:43:51.945671 <6>[ 9.229934] Run /init as init process
10496 00:43:51.976300 <6>[ 9.258730] NET: Registered PF_INET6 protocol family
10497 00:43:51.982984 <6>[ 9.265198] Segment Routing with IPv6
10498 00:43:51.986074 <6>[ 9.269188] In-situ OAM (IOAM) with IPv6
10499 00:43:52.026866 <30>[ 9.282785] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10500 00:43:52.033166 <30>[ 9.315903] systemd[1]: Detected architecture arm64.
10501 00:43:52.033586
10502 00:43:52.039694 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10503 00:43:52.040087
10504 00:43:52.058606 <30>[ 9.341300] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10505 00:43:52.167851 <30>[ 9.447575] systemd[1]: Queued start job for default target graphical.target.
10506 00:43:52.215525 <30>[ 9.495159] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10507 00:43:52.222300 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10508 00:43:52.241833 <30>[ 9.521496] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10509 00:43:52.251541 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10510 00:43:52.270344 <30>[ 9.549866] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10511 00:43:52.280122 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10512 00:43:52.298921 <30>[ 9.578604] systemd[1]: Created slice user.slice - User and Session Slice.
10513 00:43:52.305324 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10514 00:43:52.329327 <30>[ 9.605839] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10515 00:43:52.339150 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10516 00:43:52.357047 <30>[ 9.633320] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10517 00:43:52.363390 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10518 00:43:52.392192 <30>[ 9.661716] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10519 00:43:52.401939 <30>[ 9.681628] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10520 00:43:52.408617 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10521 00:43:52.425875 <30>[ 9.705572] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10522 00:43:52.435561 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10523 00:43:52.453370 <30>[ 9.733292] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10524 00:43:52.463662 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10525 00:43:52.478601 <30>[ 9.761614] systemd[1]: Reached target paths.target - Path Units.
10526 00:43:52.488480 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10527 00:43:52.505745 <30>[ 9.785650] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10528 00:43:52.512746 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10529 00:43:52.526303 <30>[ 9.809177] systemd[1]: Reached target slices.target - Slice Units.
10530 00:43:52.536302 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10531 00:43:52.550492 <30>[ 9.833671] systemd[1]: Reached target swap.target - Swaps.
10532 00:43:52.557197 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10533 00:43:52.577673 <30>[ 9.857589] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10534 00:43:52.587774 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10535 00:43:52.605899 <30>[ 9.885655] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10536 00:43:52.615768 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10537 00:43:52.635382 <30>[ 9.915136] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10538 00:43:52.645096 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10539 00:43:52.661964 <30>[ 9.941811] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10540 00:43:52.671995 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10541 00:43:52.690072 <30>[ 9.969794] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10542 00:43:52.696562 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10543 00:43:52.714263 <30>[ 9.993856] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10544 00:43:52.724030 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10545 00:43:52.742661 <30>[ 10.022513] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10546 00:43:52.752421 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10547 00:43:52.770282 <30>[ 10.050134] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10548 00:43:52.779971 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10549 00:43:52.829557 <30>[ 10.109423] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10550 00:43:52.836395 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10551 00:43:52.856621 <30>[ 10.136238] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10552 00:43:52.862850 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10553 00:43:52.885851 <30>[ 10.165750] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10554 00:43:52.892541 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10555 00:43:52.920421 <30>[ 10.193608] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10556 00:43:52.949877 <30>[ 10.229504] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10557 00:43:52.959467 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10558 00:43:52.982800 <30>[ 10.262681] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10559 00:43:52.989301 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10560 00:43:53.038370 <30>[ 10.317518] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10561 00:43:53.051583 Starting [0;1;39mmodpr<6>[ 10.328251] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10562 00:43:53.054690 obe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10563 00:43:53.079074 <30>[ 10.358380] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10564 00:43:53.085418 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10565 00:43:53.110843 <30>[ 10.390453] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10566 00:43:53.120679 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10567 00:43:53.162261 <30>[ 10.441637] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10568 00:43:53.168604 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10569 00:43:53.214160 <30>[ 10.493633] systemd[1]: Starting systemd-journald.service - Journal Service...
10570 00:43:53.220594 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10571 00:43:53.240636 <30>[ 10.520204] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10572 00:43:53.247494 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10573 00:43:53.273199 <30>[ 10.549186] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10574 00:43:53.279501 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10575 00:43:53.300103 <30>[ 10.580041] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10576 00:43:53.309910 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10577 00:43:53.328497 <30>[ 10.608396] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10578 00:43:53.335203 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10579 00:43:53.359563 <30>[ 10.638962] systemd[1]: Started systemd-journald.service - Journal Service.
10580 00:43:53.365778 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10581 00:43:53.389989 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10582 00:43:53.407000 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10583 00:43:53.427451 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10584 00:43:53.447160 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10585 00:43:53.468268 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10586 00:43:53.489663 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10587 00:43:53.508322 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10588 00:43:53.529082 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10589 00:43:53.551462 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10590 00:43:53.576087 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10591 00:43:53.599295 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10592 00:43:53.624246 [[0;1;31mFAILED[0m] Failed to start [0;1;39msystemd-re…ount Root and Kernel File Systems.
10593 00:43:53.642344 See 'systemctl status systemd-remount-fs.service' for details.
10594 00:43:53.663210 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10595 00:43:53.688434 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10596 00:43:53.733845 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10597 00:43:53.757910 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10598 00:43:53.776148 <46>[ 11.055615] systemd-journald[190]: Received client request to flush runtime journal.
10599 00:43:53.823039 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10600 00:43:53.851499 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10601 00:43:53.879201 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10602 00:43:53.905891 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10603 00:43:53.923315 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10604 00:43:53.947092 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10605 00:43:53.971213 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10606 00:43:53.995492 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10607 00:43:54.054360 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10608 00:43:54.085734 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10609 00:43:54.102449 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10610 00:43:54.125807 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10611 00:43:54.170180 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10612 00:43:54.194926 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10613 00:43:54.220730 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10614 00:43:54.244247 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10615 00:43:54.289327 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10616 00:43:54.459599 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
10617 00:43:54.487602 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10618 00:43:54.514446 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10619 00:43:54.551961 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10620 00:43:54.576711 [[0;32m OK [0m] Finished [0;1;39msystemd-up<5>[ 11.855850] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10621 00:43:54.579640 date-ut…cord System Boot/Shutdown in UTMP.
10622 00:43:54.608949 <5>[ 11.889017] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10623 00:43:54.615896 <5>[ 11.896049] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10624 00:43:54.626074 <6>[ 11.897357] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10625 00:43:54.632642 <3>[ 11.899986] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10626 00:43:54.638908 <3>[ 11.900038] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10627 00:43:54.649142 <3>[ 11.900045] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10628 00:43:54.655666 <6>[ 11.900099] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10629 00:43:54.665789 <6>[ 11.900139] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10630 00:43:54.672390 <6>[ 11.900151] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10631 00:43:54.682119 <4>[ 11.904511] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10632 00:43:54.692161 <6>[ 11.920177] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10633 00:43:54.695325 <6>[ 11.920679] cfg80211: failed to load regulatory.db
10634 00:43:54.705160 <6>[ 11.928672] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10635 00:43:54.711913 <3>[ 11.929086] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10636 00:43:54.718278 <3>[ 11.929111] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10637 00:43:54.728067 <3>[ 11.929115] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10638 00:43:54.734972 <3>[ 11.929122] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10639 00:43:54.744836 <3>[ 11.929126] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10640 00:43:54.751686 <3>[ 11.936305] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10641 00:43:54.761328 <3>[ 11.953916] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10642 00:43:54.767970 <4>[ 11.961970] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10643 00:43:54.777866 <3>[ 11.970917] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10644 00:43:54.784872 <6>[ 11.979235] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10645 00:43:54.794883 <3>[ 11.983955] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10646 00:43:54.801262 <6>[ 11.991535] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10647 00:43:54.807994 <3>[ 11.999685] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10648 00:43:54.818303 <6>[ 12.009806] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10649 00:43:54.825124 <3>[ 12.016313] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10650 00:43:54.831865 <6>[ 12.020629] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10651 00:43:54.838417 <6>[ 12.020642] pci_bus 0000:00: root bus resource [bus 00-ff]
10652 00:43:54.845198 <6>[ 12.020651] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10653 00:43:54.855078 <6>[ 12.020656] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10654 00:43:54.862147 <6>[ 12.020699] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10655 00:43:54.868567 <6>[ 12.020722] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10656 00:43:54.875368 <6>[ 12.020804] pci 0000:00:00.0: supports D1 D2
10657 00:43:54.881988 <6>[ 12.020808] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10658 00:43:54.888394 <6>[ 12.022719] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10659 00:43:54.894767 <6>[ 12.022876] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10660 00:43:54.901604 <6>[ 12.022909] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10661 00:43:54.911636 <6>[ 12.022931] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10662 00:43:54.917942 <6>[ 12.022951] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10663 00:43:54.921316 <6>[ 12.023072] pci 0000:01:00.0: supports D1 D2
10664 00:43:54.927658 <6>[ 12.023077] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10665 00:43:54.937722 <6>[ 12.024249] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10666 00:43:54.944435 <3>[ 12.032030] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10667 00:43:54.951280 <6>[ 12.034455] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10668 00:43:54.960898 <6>[ 12.040109] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10669 00:43:54.967726 <6>[ 12.040455] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10670 00:43:54.974176 <3>[ 12.048188] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10671 00:43:54.984041 <6>[ 12.051268] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10672 00:43:54.990765 <6>[ 12.051396] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10673 00:43:54.997308 <6>[ 12.051404] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10674 00:43:55.007249 <6>[ 12.051421] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10675 00:43:55.013883 <6>[ 12.051452] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10676 00:43:55.024015 <6>[ 12.051469] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10677 00:43:55.027023 <6>[ 12.051486] pci 0000:00:00.0: PCI bridge to [bus 01]
10678 00:43:55.037204 <6>[ 12.051495] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10679 00:43:55.044192 <6>[ 12.052767] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10680 00:43:55.047057 <6>[ 12.053784] remoteproc remoteproc0: scp is available
10681 00:43:55.053425 <6>[ 12.053873] remoteproc remoteproc0: powering up scp
10682 00:43:55.060136 <6>[ 12.053879] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10683 00:43:55.066783 <6>[ 12.053895] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10684 00:43:55.078197 <6>[ 12.057224] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10685 00:43:55.084572 <4>[ 12.057762] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10686 00:43:55.087980 <4>[ 12.057762] Fallback method does not support PEC.
10687 00:43:55.095113 <6>[ 12.060982] mc: Linux media interface: v0.10
10688 00:43:55.101426 <3>[ 12.065319] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10689 00:43:55.112272 <3>[ 12.073156] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10690 00:43:55.118895 <3>[ 12.107244] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10691 00:43:55.125514 <4>[ 12.113921] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10692 00:43:55.135663 <3>[ 12.117483] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10693 00:43:55.142035 <6>[ 12.117661] videodev: Linux video capture interface: v2.00
10694 00:43:55.145407 <6>[ 12.138396] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10695 00:43:55.155494 <4>[ 12.143374] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10696 00:43:55.162052 <6>[ 12.150090] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10697 00:43:55.168287 <6>[ 12.179773] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10698 00:43:55.175177 <6>[ 12.179806] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10699 00:43:55.181929 <6>[ 12.179816] remoteproc remoteproc0: remote processor scp is now up
10700 00:43:55.191517 <6>[ 12.330490] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10701 00:43:55.201530 <6>[ 12.337005] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10702 00:43:55.212110 <3>[ 12.376379] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10703 00:43:55.218865 <3>[ 12.377386] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10704 00:43:55.228747 <6>[ 12.379044] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10705 00:43:55.238710 <3>[ 12.379848] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10706 00:43:55.245039 <3>[ 12.403310] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10707 00:43:55.251683 <6>[ 12.464353] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10708 00:43:55.257913 <6>[ 12.470684] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10709 00:43:55.267946 <3>[ 12.502722] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10710 00:43:55.281721 <6>[ 12.519585] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10711 00:43:55.284936 <6>[ 12.526682] Bluetooth: Core ver 2.22
10712 00:43:55.291728 <6>[ 12.534136] usbcore: registered new interface driver uvcvideo
10713 00:43:55.298548 <6>[ 12.540503] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10714 00:43:55.305129 <6>[ 12.540617] NET: Registered PF_BLUETOOTH protocol family
10715 00:43:55.311438 <6>[ 12.540620] Bluetooth: HCI device and connection manager initialized
10716 00:43:55.315140 <6>[ 12.540633] Bluetooth: HCI socket layer initialized
10717 00:43:55.321716 <6>[ 12.540639] Bluetooth: L2CAP socket layer initialized
10718 00:43:55.325581 <6>[ 12.540655] Bluetooth: SCO socket layer initialized
10719 00:43:55.335740 <3>[ 12.565357] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10720 00:43:55.345902 <6>[ 12.576216] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10721 00:43:55.349506 <6>[ 12.600965] usbcore: registered new interface driver btusb
10722 00:43:55.356341 <6>[ 12.607805] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10723 00:43:55.366164 <4>[ 12.610158] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10724 00:43:55.372788 <6>[ 12.615279] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10725 00:43:55.382996 <3>[ 12.616573] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10726 00:43:55.389305 <3>[ 12.623923] Bluetooth: hci0: Failed to load firmware file (-2)
10727 00:43:55.399223 <3>[ 12.636114] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10728 00:43:55.402693 <3>[ 12.637907] Bluetooth: hci0: Failed to set up firmware (-2)
10729 00:43:55.412541 <4>[ 12.637910] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10730 00:43:55.418944 <6>[ 12.649169] mt7921e 0000:01:00.0: ASIC revision: 79610010
10731 00:43:55.428408 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
10732 00:43:55.446587 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
10733 00:43:55.496624 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
10734 00:43:55.520059 [[0;32m OK [<6>[ 12.800310] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10735 00:43:55.523485 <6>[ 12.800310]
10736 00:43:55.529966 0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
10737 00:43:55.547156 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
10738 00:43:55.593322 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
10739 00:43:55.607997 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
10740 00:43:55.626577 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10741 00:43:55.642256 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
10742 00:43:55.661068 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10743 00:43:55.676358 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
10744 00:43:55.692413 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
10745 00:43:55.710467 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
10746 00:43:55.726182 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
10747 00:43:55.745415 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
10748 00:43:55.791898 <6>[ 13.071743] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10749 00:43:55.799105 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
10750 00:43:55.828460 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
10751 00:43:55.850690 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
10752 00:43:55.871073 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
10753 00:43:55.899647 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
10754 00:43:55.949139 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
10755 00:43:55.968693 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
10756 00:43:55.986369 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
10757 00:43:56.028690 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
10758 00:43:56.048840 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
10759 00:43:56.066861 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
10760 00:43:56.088232 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
10761 00:43:56.105824 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
10762 00:43:56.159964 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
10763 00:43:56.198028 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
10764 00:43:56.236296
10765 00:43:56.239927 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
10766 00:43:56.240369
10767 00:43:56.244053 debian-bookworm-arm64 login: root (automatic login)
10768 00:43:56.244633
10769 00:43:56.257986 Linux debian-bookworm-arm64 6.1.92-cip22 #1 SMP PREEMPT Sun Jun 16 00:28:47 UTC 2024 aarch64
10770 00:43:56.258440
10771 00:43:56.264726 The programs included with the Debian GNU/Linux system are free software;
10772 00:43:56.271095 the exact distribution terms for each program are described in the
10773 00:43:56.274481 individual files in /usr/share/doc/*/copyright.
10774 00:43:56.274893
10775 00:43:56.281321 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10776 00:43:56.284675 permitted by applicable law.
10777 00:43:56.285937 Matched prompt #10: / #
10779 00:43:56.287046 Setting prompt string to ['/ #']
10780 00:43:56.287503 end: 2.2.5.1 login-action (duration 00:00:14) [common]
10782 00:43:56.288448 end: 2.2.5 auto-login-action (duration 00:00:14) [common]
10783 00:43:56.288867 start: 2.2.6 expect-shell-connection (timeout 00:03:34) [common]
10784 00:43:56.289209 Setting prompt string to ['/ #']
10785 00:43:56.289498 Forcing a shell prompt, looking for ['/ #']
10787 00:43:56.340202 / #
10788 00:43:56.340779 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10789 00:43:56.341214 Waiting using forced prompt support (timeout 00:02:30)
10790 00:43:56.346035
10791 00:43:56.346763 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10792 00:43:56.347203 start: 2.2.7 export-device-env (timeout 00:03:34) [common]
10793 00:43:56.347621 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10794 00:43:56.348019 end: 2.2 depthcharge-retry (duration 00:01:26) [common]
10795 00:43:56.348428 end: 2 depthcharge-action (duration 00:01:26) [common]
10796 00:43:56.348850 start: 3 lava-test-retry (timeout 00:05:00) [common]
10797 00:43:56.349369 start: 3.1 lava-test-shell (timeout 00:05:00) [common]
10798 00:43:56.349819 Using namespace: common
10800 00:43:56.450953 / # #
10801 00:43:56.451618 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:05:00)
10802 00:43:56.457432 #
10803 00:43:56.458263 Using /lava-14368387
10805 00:43:56.559348 / # export SHELL=/bin/sh
10806 00:43:56.565998 export SHELL=/bin/sh
10808 00:43:56.667679 / # . /lava-14368387/environment
10809 00:43:56.668503 . /lava-14368387/environment<6>[ 13.925860] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10810 00:43:56.673950
10812 00:43:56.775741 / # /lava-14368387/bin/lava-test-runner /lava-14368387/0
10813 00:43:56.776412 Test shell timeout: 10s (minimum of the action and connection timeout)
10814 00:43:56.782085 /lava-14368387/bin/lava-test-runner /lava-14368387/0
10815 00:43:56.801616 + export TESTRUN_ID=0_cros-ec
10816 00:43:56.808044 +<8>[ 14.090004] <LAVA_SIGNAL_STARTRUN 0_cros-ec 14368387_1.5.2.3.1>
10817 00:43:56.808764 Received signal: <STARTRUN> 0_cros-ec 14368387_1.5.2.3.1
10818 00:43:56.809158 Starting test lava.0_cros-ec (14368387_1.5.2.3.1)
10819 00:43:56.809566 Skipping test definition patterns.
10820 00:43:56.811940 cd /lava-14368387/0/tests/0_cros-ec
10821 00:43:56.814831 + cat uuid
10822 00:43:56.815275 + UUID=14368387_1.5.2.3.1
10823 00:43:56.815620 + set +x
10824 00:43:56.820995 + python3 -m cros.runners.lava_runner -v
10825 00:43:57.206817 test_cros_ec_accel_iio_abi (cros.tests.cros_ec_accel.TestCrosECAccel.test_cros_ec_accel_iio_abi)
10826 00:43:57.213294 Checks the cros-ec accelerometer IIO ABI. ... skipped 'No cros-ec-accel found'
10827 00:43:57.213807
10828 00:43:57.219660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_accel_iio_abi RESULT=skip>
10829 00:43:57.220423 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_accel_iio_abi RESULT=skip
10831 00:43:57.229730 test_cros_ec_accel_iio_data_is_valid (cros.tests.cros_ec_accel.TestCrosECAccel.test_cros_ec_accel_iio_data_is_valid)
10832 00:43:57.240002 Validates accelerometer data by computing the magnitude. If the ... skipped 'No accelerometer found'
10833 00:43:57.240511
10834 00:43:57.246339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_accel_iio_data_is_valid RESULT=skip>
10835 00:43:57.247141 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_accel_iio_data_is_valid RESULT=skip
10837 00:43:57.256537 test_cros_ec_gyro_iio_abi (cros.tests.cros_ec_gyro.TestCrosECGyro.test_cros_ec_gyro_iio_abi)
10838 00:43:57.262691 Checks the cros-ec gyroscope IIO ABI. ... skipped 'No cros-ec-gyro found'
10839 00:43:57.263128
10840 00:43:57.269722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_gyro_iio_abi RESULT=skip>
10841 00:43:57.270426 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_gyro_iio_abi RESULT=skip
10843 00:43:57.275713 test_cros_ec_abi (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_ec_abi)
10844 00:43:57.279411 Checks the standard ABI for the main Embedded Controller. ... ok
10845 00:43:57.282591
10846 00:43:57.285650 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_abi RESULT=pass>
10847 00:43:57.286381 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_abi RESULT=pass
10849 00:43:57.292186 test_cros_ec_chardev (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_ec_chardev)
10850 00:43:57.299075 Checks the main Embedded controller character device. ... ok
10851 00:43:57.299509
10852 00:43:57.305512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_chardev RESULT=pass>
10853 00:43:57.306195 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_chardev RESULT=pass
10855 00:43:57.312153 test_cros_ec_hello (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_ec_hello)
10856 00:43:57.318682 Checks basic comunication with the main Embedded controller. ... ok
10857 00:43:57.319135
10858 00:43:57.325471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_hello RESULT=pass>
10859 00:43:57.326159 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_hello RESULT=pass
10861 00:43:57.331783 test_cros_fp_abi (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_fp_abi)
10862 00:43:57.338457 Checks the standard ABI for the Fingerprint EC. ... skipped 'MCU cros_fp not supported'
10863 00:43:57.338946
10864 00:43:57.345427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_abi RESULT=skip>
10865 00:43:57.346071 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_abi RESULT=skip
10867 00:43:57.351802 test_cros_fp_hello (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_fp_hello)
10868 00:43:57.358722 Checks basic comunication with the fingerprint controller. ... skipped 'MCU cros_fp not found'
10869 00:43:57.359120
10870 00:43:57.364737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_hello RESULT=skip>
10871 00:43:57.365417 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_hello RESULT=skip
10873 00:43:57.371705 test_cros_fp_reboot (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_fp_reboot)
10874 00:43:57.377981 Test reboot command on Fingerprint MCU. ... skipped 'MCU cros_fp not found'
10875 00:43:57.378464
10876 00:43:57.385034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_reboot RESULT=skip>
10877 00:43:57.385712 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_reboot RESULT=skip
10879 00:43:57.391083 test_cros_pd_abi (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_pd_abi)
10880 00:43:57.397889 Checks the standard ABI for the Power Delivery EC. ... skipped 'MCU cros_pd not supported'
10881 00:43:57.401236
10882 00:43:57.404871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_pd_abi RESULT=skip>
10883 00:43:57.405551 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_pd_abi RESULT=skip
10885 00:43:57.411363 test_cros_pd_hello (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_pd_hello)
10886 00:43:57.420905 Checks basic comunication with the power delivery controller. ... skipped 'MCU cros_pd not found'
10887 00:43:57.421297
10888 00:43:57.428021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_pd_hello RESULT=skip>
10889 00:43:57.428773 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_pd_hello RESULT=skip
10891 00:43:57.434330 test_cros_tp_abi (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_tp_abi)
10892 00:43:57.440834 Checks the standard ABI for the Touchpad EC. ... skipped 'MCU cros_tp not supported'
10893 00:43:57.441339
10894 00:43:57.447511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_tp_abi RESULT=skip>
10895 00:43:57.448288 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_tp_abi RESULT=skip
10897 00:43:57.454047 test_cros_tp_hello (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_tp_hello)
10898 00:43:57.460840 Checks basic comunication with the touchpad controller. ... skipped 'MCU cros_tp not found'
10899 00:43:57.461362
10900 00:43:57.467432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_tp_hello RESULT=skip>
10901 00:43:57.468113 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_tp_hello RESULT=skip
10903 00:43:57.477134 test_cros_ec_pwm_backlight (cros.tests.cros_ec_pwm.TestCrosECPWM.test_cros_ec_pwm_backlight)
10904 00:43:57.484095 Check that the backlight is connected to a pwm of the EC and that ... skipped 'No backlight pwm found'
10905 00:43:57.484536
10906 00:43:57.490267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_pwm_backlight RESULT=skip>
10907 00:43:57.490947 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_pwm_backlight RESULT=skip
10909 00:43:57.499988 test_cros_ec_battery_abi (cros.tests.cros_ec_power.TestCrosECPower.test_cros_ec_battery_abi)
10910 00:43:57.503599 Check the cros battery ABI. ... skipped 'No BAT found'
10911 00:43:57.504020
10912 00:43:57.510132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_battery_abi RESULT=skip>
10913 00:43:57.510836 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_battery_abi RESULT=skip
10915 00:43:57.520105 test_cros_ec_usbpd_charger_abi (cros.tests.cros_ec_power.TestCrosECPower.test_cros_ec_usbpd_charger_abi)
10916 00:43:57.526464 Check the cros USBPD charger ABI. ... skipped 'No CROS_USBPD_CHARGER found'
10917 00:43:57.526861
10918 00:43:57.533106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_usbpd_charger_abi RESULT=skip>
10919 00:43:57.533872 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_usbpd_charger_abi RESULT=skip
10921 00:43:57.539729 test_cros_ec_rtc_abi (cros.tests.cros_ec_rtc.TestCrosECRTC.test_cros_ec_rtc_abi)
10922 00:43:57.549650 Check the cros RTC ABI. ... skipped 'EC_FEATURE_RTC not supported, skipping'
10923 00:43:57.550045
10924 00:43:57.552836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_rtc_abi RESULT=skip>
10925 00:43:57.553467 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_rtc_abi RESULT=skip
10927 00:43:57.563213 test_cros_ec_extcon_usbc_abi (cros.tests.cros_ec_extcon.TestCrosECextcon.test_cros_ec_extcon_usbc_abi)
10928 00:43:57.569472 Checks the cros-ec extcon ABI. ... skipped 'No extcon device found'
10929 00:43:57.569863
10930 00:43:57.576423 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_extcon_usb<8
10931 00:43:57.576904 Test case results without result (probably a sign of an incorrect parsing pattern being used): {'test_case_id': 'test_cros_ec_extcon_usb<8', 'result': 'unknown'}
10932 00:43:57.579616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_extcon_usb<8>[ 14.862867] <LAVA_SIGNAL_ENDRUN 0_cros-ec 14368387_1.5.2.3.1>
10933 00:43:57.580257 Received signal: <ENDRUN> 0_cros-ec 14368387_1.5.2.3.1
10934 00:43:57.580643 Ending use of test pattern.
10935 00:43:57.580935 Ending test lava.0_cros-ec (14368387_1.5.2.3.1), duration 0.77
10937 00:43:57.582710 c_abi RESULT=skip>
10938 00:43:57.583100
10939 00:43:57.589400 ----------------------------------------------------------------------
10940 00:43:57.589800 Ran 18 tests in 0.350s
10941 00:43:57.592669
10942 00:43:57.593057 OK (skipped=15)
10943 00:43:57.593361 + set +x
10944 00:43:57.595900 <LAVA_TEST_RUNNER EXIT>
10945 00:43:57.596613 ok: lava_test_shell seems to have completed
10946 00:43:57.597584 test_cros_ec_abi: pass
test_cros_ec_accel_iio_abi: skip
test_cros_ec_accel_iio_data_is_valid: skip
test_cros_ec_battery_abi: skip
test_cros_ec_chardev: pass
test_cros_ec_gyro_iio_abi: skip
test_cros_ec_hello: pass
test_cros_ec_pwm_backlight: skip
test_cros_ec_rtc_abi: skip
test_cros_ec_usbpd_charger_abi: skip
test_cros_fp_abi: skip
test_cros_fp_hello: skip
test_cros_fp_reboot: skip
test_cros_pd_abi: skip
test_cros_pd_hello: skip
test_cros_tp_abi: skip
test_cros_tp_hello: skip
10947 00:43:57.598134 end: 3.1 lava-test-shell (duration 00:00:01) [common]
10948 00:43:57.598666 end: 3 lava-test-retry (duration 00:00:01) [common]
10949 00:43:57.599210 start: 4 finalize (timeout 00:08:10) [common]
10950 00:43:57.599655 start: 4.1 power-off (timeout 00:00:30) [common]
10951 00:43:57.600349 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-4', '--port=1', '--command=off']
10952 00:43:57.855290 >> Command sent successfully.
10953 00:43:57.870055 Returned 0 in 0 seconds
10954 00:43:57.971467 end: 4.1 power-off (duration 00:00:00) [common]
10956 00:43:57.972961 start: 4.2 read-feedback (timeout 00:08:09) [common]
10957 00:43:57.974144 Listened to connection for namespace 'common' for up to 1s
10958 00:43:58.974487 Finalising connection for namespace 'common'
10959 00:43:58.975102 Disconnecting from shell: Finalise
10960 00:43:58.975482 / #
10961 00:43:59.076081 end: 4.2 read-feedback (duration 00:00:01) [common]
10962 00:43:59.076216 end: 4 finalize (duration 00:00:01) [common]
10963 00:43:59.076331 Cleaning after the job
10964 00:43:59.076430 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14368387/tftp-deploy-2edglom8/ramdisk
10965 00:43:59.082251 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14368387/tftp-deploy-2edglom8/kernel
10966 00:43:59.096784 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14368387/tftp-deploy-2edglom8/dtb
10967 00:43:59.097003 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14368387/tftp-deploy-2edglom8/modules
10968 00:43:59.102648 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14368387
10969 00:43:59.186760 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14368387
10970 00:43:59.186925 Job finished correctly