Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 21
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 24
1 00:40:50.646480 lava-dispatcher, installed at version: 2024.03
2 00:40:50.646680 start: 0 validate
3 00:40:50.646811 Start time: 2024-06-16 00:40:50.646801+00:00 (UTC)
4 00:40:50.646920 Using caching service: 'http://localhost/cache/?uri=%s'
5 00:40:50.647043 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 00:40:50.897255 Using caching service: 'http://localhost/cache/?uri=%s'
7 00:40:50.897566 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22-24-g0315de64ea248%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 00:41:06.153482 Using caching service: 'http://localhost/cache/?uri=%s'
9 00:41:06.154233 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22-24-g0315de64ea248%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 00:41:06.410302 Using caching service: 'http://localhost/cache/?uri=%s'
11 00:41:06.411045 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 00:41:06.906070 Using caching service: 'http://localhost/cache/?uri=%s'
13 00:41:06.906812 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22-24-g0315de64ea248%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 00:41:12.418529 validate duration: 21.77
16 00:41:12.419834 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 00:41:12.420387 start: 1.1 download-retry (timeout 00:10:00) [common]
18 00:41:12.420936 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 00:41:12.421557 Not decompressing ramdisk as can be used compressed.
20 00:41:12.422053 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 00:41:12.422426 saving as /var/lib/lava/dispatcher/tmp/14368384/tftp-deploy-28dj6z9m/ramdisk/initrd.cpio.gz
22 00:41:12.422798 total size: 5628169 (5 MB)
23 00:41:12.675038 progress 0 % (0 MB)
24 00:41:12.677031 progress 5 % (0 MB)
25 00:41:12.678775 progress 10 % (0 MB)
26 00:41:12.680326 progress 15 % (0 MB)
27 00:41:12.682062 progress 20 % (1 MB)
28 00:41:12.683484 progress 25 % (1 MB)
29 00:41:12.685061 progress 30 % (1 MB)
30 00:41:12.686616 progress 35 % (1 MB)
31 00:41:12.687976 progress 40 % (2 MB)
32 00:41:12.689493 progress 45 % (2 MB)
33 00:41:12.690861 progress 50 % (2 MB)
34 00:41:12.692526 progress 55 % (2 MB)
35 00:41:12.694237 progress 60 % (3 MB)
36 00:41:12.695714 progress 65 % (3 MB)
37 00:41:12.697327 progress 70 % (3 MB)
38 00:41:12.698665 progress 75 % (4 MB)
39 00:41:12.700207 progress 80 % (4 MB)
40 00:41:12.701603 progress 85 % (4 MB)
41 00:41:12.703125 progress 90 % (4 MB)
42 00:41:12.704663 progress 95 % (5 MB)
43 00:41:12.706012 progress 100 % (5 MB)
44 00:41:12.706216 5 MB downloaded in 0.28 s (18.94 MB/s)
45 00:41:12.706404 end: 1.1.1 http-download (duration 00:00:00) [common]
47 00:41:12.706642 end: 1.1 download-retry (duration 00:00:00) [common]
48 00:41:12.706729 start: 1.2 download-retry (timeout 00:10:00) [common]
49 00:41:12.706813 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 00:41:12.706947 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-24-g0315de64ea248/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 00:41:12.707017 saving as /var/lib/lava/dispatcher/tmp/14368384/tftp-deploy-28dj6z9m/kernel/Image
52 00:41:12.707077 total size: 54813184 (52 MB)
53 00:41:12.707139 No compression specified
54 00:41:12.708212 progress 0 % (0 MB)
55 00:41:12.721792 progress 5 % (2 MB)
56 00:41:12.735480 progress 10 % (5 MB)
57 00:41:12.749352 progress 15 % (7 MB)
58 00:41:12.763120 progress 20 % (10 MB)
59 00:41:12.776876 progress 25 % (13 MB)
60 00:41:12.790533 progress 30 % (15 MB)
61 00:41:12.804810 progress 35 % (18 MB)
62 00:41:12.818669 progress 40 % (20 MB)
63 00:41:12.832354 progress 45 % (23 MB)
64 00:41:12.846108 progress 50 % (26 MB)
65 00:41:12.860011 progress 55 % (28 MB)
66 00:41:12.873559 progress 60 % (31 MB)
67 00:41:12.887245 progress 65 % (34 MB)
68 00:41:12.901091 progress 70 % (36 MB)
69 00:41:12.914961 progress 75 % (39 MB)
70 00:41:12.928800 progress 80 % (41 MB)
71 00:41:12.942369 progress 85 % (44 MB)
72 00:41:12.956150 progress 90 % (47 MB)
73 00:41:12.969816 progress 95 % (49 MB)
74 00:41:12.983170 progress 100 % (52 MB)
75 00:41:12.983412 52 MB downloaded in 0.28 s (189.17 MB/s)
76 00:41:12.983563 end: 1.2.1 http-download (duration 00:00:00) [common]
78 00:41:12.983798 end: 1.2 download-retry (duration 00:00:00) [common]
79 00:41:12.983888 start: 1.3 download-retry (timeout 00:09:59) [common]
80 00:41:12.983973 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 00:41:12.984091 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-24-g0315de64ea248/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 00:41:12.984161 saving as /var/lib/lava/dispatcher/tmp/14368384/tftp-deploy-28dj6z9m/dtb/mt8192-asurada-spherion-r0.dtb
83 00:41:12.984224 total size: 47258 (0 MB)
84 00:41:12.984287 No compression specified
85 00:41:12.985413 progress 69 % (0 MB)
86 00:41:12.985688 progress 100 % (0 MB)
87 00:41:12.985844 0 MB downloaded in 0.00 s (27.86 MB/s)
88 00:41:12.985965 end: 1.3.1 http-download (duration 00:00:00) [common]
90 00:41:12.986192 end: 1.3 download-retry (duration 00:00:00) [common]
91 00:41:12.986280 start: 1.4 download-retry (timeout 00:09:59) [common]
92 00:41:12.986363 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 00:41:12.986473 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 00:41:12.986541 saving as /var/lib/lava/dispatcher/tmp/14368384/tftp-deploy-28dj6z9m/nfsrootfs/full.rootfs.tar
95 00:41:12.986602 total size: 120894716 (115 MB)
96 00:41:12.986664 Using unxz to decompress xz
97 00:41:12.990197 progress 0 % (0 MB)
98 00:41:13.341236 progress 5 % (5 MB)
99 00:41:13.697582 progress 10 % (11 MB)
100 00:41:14.045954 progress 15 % (17 MB)
101 00:41:14.372497 progress 20 % (23 MB)
102 00:41:14.665608 progress 25 % (28 MB)
103 00:41:15.025086 progress 30 % (34 MB)
104 00:41:15.364550 progress 35 % (40 MB)
105 00:41:15.533476 progress 40 % (46 MB)
106 00:41:15.712799 progress 45 % (51 MB)
107 00:41:16.025217 progress 50 % (57 MB)
108 00:41:16.401499 progress 55 % (63 MB)
109 00:41:16.746819 progress 60 % (69 MB)
110 00:41:17.086019 progress 65 % (74 MB)
111 00:41:17.428878 progress 70 % (80 MB)
112 00:41:17.788186 progress 75 % (86 MB)
113 00:41:18.131699 progress 80 % (92 MB)
114 00:41:18.472872 progress 85 % (98 MB)
115 00:41:18.833296 progress 90 % (103 MB)
116 00:41:19.158395 progress 95 % (109 MB)
117 00:41:19.519247 progress 100 % (115 MB)
118 00:41:19.524765 115 MB downloaded in 6.54 s (17.63 MB/s)
119 00:41:19.525018 end: 1.4.1 http-download (duration 00:00:07) [common]
121 00:41:19.525284 end: 1.4 download-retry (duration 00:00:07) [common]
122 00:41:19.525385 start: 1.5 download-retry (timeout 00:09:53) [common]
123 00:41:19.525515 start: 1.5.1 http-download (timeout 00:09:53) [common]
124 00:41:19.525693 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-24-g0315de64ea248/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 00:41:19.525767 saving as /var/lib/lava/dispatcher/tmp/14368384/tftp-deploy-28dj6z9m/modules/modules.tar
126 00:41:19.525833 total size: 8608736 (8 MB)
127 00:41:19.525901 Using unxz to decompress xz
128 00:41:19.529507 progress 0 % (0 MB)
129 00:41:19.548381 progress 5 % (0 MB)
130 00:41:19.575839 progress 10 % (0 MB)
131 00:41:19.606144 progress 15 % (1 MB)
132 00:41:19.629795 progress 20 % (1 MB)
133 00:41:19.653506 progress 25 % (2 MB)
134 00:41:19.677313 progress 30 % (2 MB)
135 00:41:19.701435 progress 35 % (2 MB)
136 00:41:19.728436 progress 40 % (3 MB)
137 00:41:19.751001 progress 45 % (3 MB)
138 00:41:19.775263 progress 50 % (4 MB)
139 00:41:19.801302 progress 55 % (4 MB)
140 00:41:19.827459 progress 60 % (4 MB)
141 00:41:19.852158 progress 65 % (5 MB)
142 00:41:19.877245 progress 70 % (5 MB)
143 00:41:19.903213 progress 75 % (6 MB)
144 00:41:19.929516 progress 80 % (6 MB)
145 00:41:19.953781 progress 85 % (7 MB)
146 00:41:19.978971 progress 90 % (7 MB)
147 00:41:20.004432 progress 95 % (7 MB)
148 00:41:20.029662 progress 100 % (8 MB)
149 00:41:20.035289 8 MB downloaded in 0.51 s (16.12 MB/s)
150 00:41:20.035544 end: 1.5.1 http-download (duration 00:00:01) [common]
152 00:41:20.035810 end: 1.5 download-retry (duration 00:00:01) [common]
153 00:41:20.035909 start: 1.6 prepare-tftp-overlay (timeout 00:09:52) [common]
154 00:41:20.036005 start: 1.6.1 extract-nfsrootfs (timeout 00:09:52) [common]
155 00:41:23.291662 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/14368384/extract-nfsrootfs-s_fvawcb
156 00:41:23.291868 end: 1.6.1 extract-nfsrootfs (duration 00:00:03) [common]
157 00:41:23.291972 start: 1.6.2 lava-overlay (timeout 00:09:49) [common]
158 00:41:23.292147 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14368384/lava-overlay-a1ioadrf
159 00:41:23.292271 makedir: /var/lib/lava/dispatcher/tmp/14368384/lava-overlay-a1ioadrf/lava-14368384/bin
160 00:41:23.292368 makedir: /var/lib/lava/dispatcher/tmp/14368384/lava-overlay-a1ioadrf/lava-14368384/tests
161 00:41:23.292462 makedir: /var/lib/lava/dispatcher/tmp/14368384/lava-overlay-a1ioadrf/lava-14368384/results
162 00:41:23.292566 Creating /var/lib/lava/dispatcher/tmp/14368384/lava-overlay-a1ioadrf/lava-14368384/bin/lava-add-keys
163 00:41:23.292702 Creating /var/lib/lava/dispatcher/tmp/14368384/lava-overlay-a1ioadrf/lava-14368384/bin/lava-add-sources
164 00:41:23.292824 Creating /var/lib/lava/dispatcher/tmp/14368384/lava-overlay-a1ioadrf/lava-14368384/bin/lava-background-process-start
165 00:41:23.292943 Creating /var/lib/lava/dispatcher/tmp/14368384/lava-overlay-a1ioadrf/lava-14368384/bin/lava-background-process-stop
166 00:41:23.293062 Creating /var/lib/lava/dispatcher/tmp/14368384/lava-overlay-a1ioadrf/lava-14368384/bin/lava-common-functions
167 00:41:23.293179 Creating /var/lib/lava/dispatcher/tmp/14368384/lava-overlay-a1ioadrf/lava-14368384/bin/lava-echo-ipv4
168 00:41:23.293297 Creating /var/lib/lava/dispatcher/tmp/14368384/lava-overlay-a1ioadrf/lava-14368384/bin/lava-install-packages
169 00:41:23.293413 Creating /var/lib/lava/dispatcher/tmp/14368384/lava-overlay-a1ioadrf/lava-14368384/bin/lava-installed-packages
170 00:41:23.293528 Creating /var/lib/lava/dispatcher/tmp/14368384/lava-overlay-a1ioadrf/lava-14368384/bin/lava-os-build
171 00:41:23.293644 Creating /var/lib/lava/dispatcher/tmp/14368384/lava-overlay-a1ioadrf/lava-14368384/bin/lava-probe-channel
172 00:41:23.293761 Creating /var/lib/lava/dispatcher/tmp/14368384/lava-overlay-a1ioadrf/lava-14368384/bin/lava-probe-ip
173 00:41:23.293878 Creating /var/lib/lava/dispatcher/tmp/14368384/lava-overlay-a1ioadrf/lava-14368384/bin/lava-target-ip
174 00:41:23.293995 Creating /var/lib/lava/dispatcher/tmp/14368384/lava-overlay-a1ioadrf/lava-14368384/bin/lava-target-mac
175 00:41:23.294109 Creating /var/lib/lava/dispatcher/tmp/14368384/lava-overlay-a1ioadrf/lava-14368384/bin/lava-target-storage
176 00:41:23.294226 Creating /var/lib/lava/dispatcher/tmp/14368384/lava-overlay-a1ioadrf/lava-14368384/bin/lava-test-case
177 00:41:23.294342 Creating /var/lib/lava/dispatcher/tmp/14368384/lava-overlay-a1ioadrf/lava-14368384/bin/lava-test-event
178 00:41:23.294457 Creating /var/lib/lava/dispatcher/tmp/14368384/lava-overlay-a1ioadrf/lava-14368384/bin/lava-test-feedback
179 00:41:23.294572 Creating /var/lib/lava/dispatcher/tmp/14368384/lava-overlay-a1ioadrf/lava-14368384/bin/lava-test-raise
180 00:41:23.294689 Creating /var/lib/lava/dispatcher/tmp/14368384/lava-overlay-a1ioadrf/lava-14368384/bin/lava-test-reference
181 00:41:23.294806 Creating /var/lib/lava/dispatcher/tmp/14368384/lava-overlay-a1ioadrf/lava-14368384/bin/lava-test-runner
182 00:41:23.294924 Creating /var/lib/lava/dispatcher/tmp/14368384/lava-overlay-a1ioadrf/lava-14368384/bin/lava-test-set
183 00:41:23.295041 Creating /var/lib/lava/dispatcher/tmp/14368384/lava-overlay-a1ioadrf/lava-14368384/bin/lava-test-shell
184 00:41:23.295159 Updating /var/lib/lava/dispatcher/tmp/14368384/lava-overlay-a1ioadrf/lava-14368384/bin/lava-add-keys (debian)
185 00:41:23.295810 Updating /var/lib/lava/dispatcher/tmp/14368384/lava-overlay-a1ioadrf/lava-14368384/bin/lava-add-sources (debian)
186 00:41:23.295948 Updating /var/lib/lava/dispatcher/tmp/14368384/lava-overlay-a1ioadrf/lava-14368384/bin/lava-install-packages (debian)
187 00:41:23.296078 Updating /var/lib/lava/dispatcher/tmp/14368384/lava-overlay-a1ioadrf/lava-14368384/bin/lava-installed-packages (debian)
188 00:41:23.296206 Updating /var/lib/lava/dispatcher/tmp/14368384/lava-overlay-a1ioadrf/lava-14368384/bin/lava-os-build (debian)
189 00:41:23.296318 Creating /var/lib/lava/dispatcher/tmp/14368384/lava-overlay-a1ioadrf/lava-14368384/environment
190 00:41:23.296408 LAVA metadata
191 00:41:23.296473 - LAVA_JOB_ID=14368384
192 00:41:23.296535 - LAVA_DISPATCHER_IP=192.168.201.1
193 00:41:23.296765 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:49) [common]
194 00:41:23.296833 skipped lava-vland-overlay
195 00:41:23.296907 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 00:41:23.296986 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:49) [common]
197 00:41:23.297051 skipped lava-multinode-overlay
198 00:41:23.297121 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 00:41:23.297197 start: 1.6.2.3 test-definition (timeout 00:09:49) [common]
200 00:41:23.297267 Loading test definitions
201 00:41:23.297359 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:49) [common]
202 00:41:23.297428 Using /lava-14368384 at stage 0
203 00:41:23.297687 uuid=14368384_1.6.2.3.1 testdef=None
204 00:41:23.297774 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 00:41:23.297858 start: 1.6.2.3.2 test-overlay (timeout 00:09:49) [common]
206 00:41:23.298310 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 00:41:23.298530 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:49) [common]
209 00:41:23.316621 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 00:41:23.316872 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:49) [common]
212 00:41:23.317388 runner path: /var/lib/lava/dispatcher/tmp/14368384/lava-overlay-a1ioadrf/lava-14368384/0/tests/0_timesync-off test_uuid 14368384_1.6.2.3.1
213 00:41:23.317544 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 00:41:23.317767 start: 1.6.2.3.5 git-repo-action (timeout 00:09:49) [common]
216 00:41:23.317839 Using /lava-14368384 at stage 0
217 00:41:23.317939 Fetching tests from https://github.com/kernelci/test-definitions.git
218 00:41:23.318071 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/14368384/lava-overlay-a1ioadrf/lava-14368384/0/tests/1_kselftest-alsa'
219 00:41:25.385322 Running '/usr/bin/git checkout kernelci.org
220 00:41:25.528799 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/14368384/lava-overlay-a1ioadrf/lava-14368384/0/tests/1_kselftest-alsa/automated/linux/kselftest/kselftest.yaml
221 00:41:25.529535 uuid=14368384_1.6.2.3.5 testdef=None
222 00:41:25.529692 end: 1.6.2.3.5 git-repo-action (duration 00:00:02) [common]
224 00:41:25.529942 start: 1.6.2.3.6 test-overlay (timeout 00:09:47) [common]
225 00:41:25.530681 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 00:41:25.530912 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:47) [common]
228 00:41:25.531906 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 00:41:25.532154 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:47) [common]
231 00:41:25.533129 runner path: /var/lib/lava/dispatcher/tmp/14368384/lava-overlay-a1ioadrf/lava-14368384/0/tests/1_kselftest-alsa test_uuid 14368384_1.6.2.3.5
232 00:41:25.533224 BOARD='mt8192-asurada-spherion-r0'
233 00:41:25.533291 BRANCH='cip'
234 00:41:25.533352 SKIPFILE='/dev/null'
235 00:41:25.533413 SKIP_INSTALL='True'
236 00:41:25.533471 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-24-g0315de64ea248/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 00:41:25.533530 TST_CASENAME=''
238 00:41:25.533587 TST_CMDFILES='alsa'
239 00:41:25.533725 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 00:41:25.533934 Creating lava-test-runner.conf files
242 00:41:25.533999 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14368384/lava-overlay-a1ioadrf/lava-14368384/0 for stage 0
243 00:41:25.534091 - 0_timesync-off
244 00:41:25.534163 - 1_kselftest-alsa
245 00:41:25.534259 end: 1.6.2.3 test-definition (duration 00:00:02) [common]
246 00:41:25.534348 start: 1.6.2.4 compress-overlay (timeout 00:09:47) [common]
247 00:41:33.018542 end: 1.6.2.4 compress-overlay (duration 00:00:07) [common]
248 00:41:33.018711 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:39) [common]
249 00:41:33.018804 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 00:41:33.018906 end: 1.6.2 lava-overlay (duration 00:00:10) [common]
251 00:41:33.019001 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:39) [common]
252 00:41:33.178088 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 00:41:33.178460 start: 1.6.4 extract-modules (timeout 00:09:39) [common]
254 00:41:33.178570 extracting modules file /var/lib/lava/dispatcher/tmp/14368384/tftp-deploy-28dj6z9m/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14368384/extract-nfsrootfs-s_fvawcb
255 00:41:33.379602 extracting modules file /var/lib/lava/dispatcher/tmp/14368384/tftp-deploy-28dj6z9m/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14368384/extract-overlay-ramdisk-b3rkzeyg/ramdisk
256 00:41:33.589179 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 00:41:33.589369 start: 1.6.5 apply-overlay-tftp (timeout 00:09:39) [common]
258 00:41:33.589469 [common] Applying overlay to NFS
259 00:41:33.589545 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14368384/compress-overlay-ai0uik61/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14368384/extract-nfsrootfs-s_fvawcb
260 00:41:34.503422 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 00:41:34.503599 start: 1.6.6 configure-preseed-file (timeout 00:09:38) [common]
262 00:41:34.503698 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 00:41:34.503793 start: 1.6.7 compress-ramdisk (timeout 00:09:38) [common]
264 00:41:34.503877 Building ramdisk /var/lib/lava/dispatcher/tmp/14368384/extract-overlay-ramdisk-b3rkzeyg/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14368384/extract-overlay-ramdisk-b3rkzeyg/ramdisk
265 00:41:34.954498 >> 130405 blocks
266 00:41:36.950448 rename /var/lib/lava/dispatcher/tmp/14368384/extract-overlay-ramdisk-b3rkzeyg/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14368384/tftp-deploy-28dj6z9m/ramdisk/ramdisk.cpio.gz
267 00:41:36.950886 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 00:41:36.951009 start: 1.6.8 prepare-kernel (timeout 00:09:35) [common]
269 00:41:36.951109 start: 1.6.8.1 prepare-fit (timeout 00:09:35) [common]
270 00:41:36.951214 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14368384/tftp-deploy-28dj6z9m/kernel/Image']
271 00:41:49.943881 Returned 0 in 12 seconds
272 00:41:50.044628 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14368384/tftp-deploy-28dj6z9m/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14368384/tftp-deploy-28dj6z9m/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14368384/tftp-deploy-28dj6z9m/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14368384/tftp-deploy-28dj6z9m/kernel/image.itb
273 00:41:50.404916 output: FIT description: Kernel Image image with one or more FDT blobs
274 00:41:50.405266 output: Created: Sun Jun 16 01:41:50 2024
275 00:41:50.405344 output: Image 0 (kernel-1)
276 00:41:50.405443 output: Description:
277 00:41:50.405539 output: Created: Sun Jun 16 01:41:50 2024
278 00:41:50.405632 output: Type: Kernel Image
279 00:41:50.405726 output: Compression: lzma compressed
280 00:41:50.405819 output: Data Size: 13126376 Bytes = 12818.73 KiB = 12.52 MiB
281 00:41:50.405893 output: Architecture: AArch64
282 00:41:50.405952 output: OS: Linux
283 00:41:50.406011 output: Load Address: 0x00000000
284 00:41:50.406068 output: Entry Point: 0x00000000
285 00:41:50.406126 output: Hash algo: crc32
286 00:41:50.406185 output: Hash value: c791a20a
287 00:41:50.406241 output: Image 1 (fdt-1)
288 00:41:50.406298 output: Description: mt8192-asurada-spherion-r0
289 00:41:50.406354 output: Created: Sun Jun 16 01:41:50 2024
290 00:41:50.406414 output: Type: Flat Device Tree
291 00:41:50.406511 output: Compression: uncompressed
292 00:41:50.406592 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
293 00:41:50.406674 output: Architecture: AArch64
294 00:41:50.406760 output: Hash algo: crc32
295 00:41:50.406838 output: Hash value: 0f8e4d2e
296 00:41:50.406896 output: Image 2 (ramdisk-1)
297 00:41:50.406951 output: Description: unavailable
298 00:41:50.407013 output: Created: Sun Jun 16 01:41:50 2024
299 00:41:50.407070 output: Type: RAMDisk Image
300 00:41:50.407125 output: Compression: Unknown Compression
301 00:41:50.407180 output: Data Size: 18740277 Bytes = 18301.05 KiB = 17.87 MiB
302 00:41:50.407236 output: Architecture: AArch64
303 00:41:50.407291 output: OS: Linux
304 00:41:50.407345 output: Load Address: unavailable
305 00:41:50.407400 output: Entry Point: unavailable
306 00:41:50.407455 output: Hash algo: crc32
307 00:41:50.407509 output: Hash value: 0e80ef84
308 00:41:50.407567 output: Default Configuration: 'conf-1'
309 00:41:50.407624 output: Configuration 0 (conf-1)
310 00:41:50.407679 output: Description: mt8192-asurada-spherion-r0
311 00:41:50.407734 output: Kernel: kernel-1
312 00:41:50.407789 output: Init Ramdisk: ramdisk-1
313 00:41:50.407843 output: FDT: fdt-1
314 00:41:50.407899 output: Loadables: kernel-1
315 00:41:50.407953 output:
316 00:41:50.408153 end: 1.6.8.1 prepare-fit (duration 00:00:13) [common]
317 00:41:50.408256 end: 1.6.8 prepare-kernel (duration 00:00:13) [common]
318 00:41:50.408362 end: 1.6 prepare-tftp-overlay (duration 00:00:30) [common]
319 00:41:50.408464 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:22) [common]
320 00:41:50.408608 No LXC device requested
321 00:41:50.408734 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 00:41:50.408836 start: 1.8 deploy-device-env (timeout 00:09:22) [common]
323 00:41:50.408917 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 00:41:50.408988 Checking files for TFTP limit of 4294967296 bytes.
325 00:41:50.409493 end: 1 tftp-deploy (duration 00:00:38) [common]
326 00:41:50.409600 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 00:41:50.409694 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 00:41:50.409825 substitutions:
329 00:41:50.409895 - {DTB}: 14368384/tftp-deploy-28dj6z9m/dtb/mt8192-asurada-spherion-r0.dtb
330 00:41:50.409965 - {INITRD}: 14368384/tftp-deploy-28dj6z9m/ramdisk/ramdisk.cpio.gz
331 00:41:50.410028 - {KERNEL}: 14368384/tftp-deploy-28dj6z9m/kernel/Image
332 00:41:50.410088 - {LAVA_MAC}: None
333 00:41:50.410147 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/14368384/extract-nfsrootfs-s_fvawcb
334 00:41:50.410206 - {NFS_SERVER_IP}: 192.168.201.1
335 00:41:50.410265 - {PRESEED_CONFIG}: None
336 00:41:50.410323 - {PRESEED_LOCAL}: None
337 00:41:50.410404 - {RAMDISK}: 14368384/tftp-deploy-28dj6z9m/ramdisk/ramdisk.cpio.gz
338 00:41:50.410490 - {ROOT_PART}: None
339 00:41:50.410571 - {ROOT}: None
340 00:41:50.410638 - {SERVER_IP}: 192.168.201.1
341 00:41:50.410695 - {TEE}: None
342 00:41:50.410751 Parsed boot commands:
343 00:41:50.410850 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 00:41:50.411064 Parsed boot commands: tftpboot 192.168.201.1 14368384/tftp-deploy-28dj6z9m/kernel/image.itb 14368384/tftp-deploy-28dj6z9m/kernel/cmdline
345 00:41:50.411162 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 00:41:50.411252 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 00:41:50.411349 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 00:41:50.411434 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 00:41:50.411510 Not connected, no need to disconnect.
350 00:41:50.411587 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 00:41:50.411672 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 00:41:50.411741 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-1'
353 00:41:50.414989 Setting prompt string to ['lava-test: # ']
354 00:41:50.415338 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 00:41:50.415465 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 00:41:50.415595 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 00:41:50.415720 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 00:41:50.415925 Calling: ['/usr/local/bin/chromebook-reboot.sh', 'mt8192-asurada-spherion-r0-cbg-1']
359 00:42:03.994022 Returned 0 in 13 seconds
360 00:42:04.094691 end: 2.2.2.1 pdu-reboot (duration 00:00:14) [common]
362 00:42:04.095031 end: 2.2.2 reset-device (duration 00:00:14) [common]
363 00:42:04.095141 start: 2.2.3 depthcharge-start (timeout 00:04:46) [common]
364 00:42:04.095262 Setting prompt string to 'Starting depthcharge on Spherion...'
365 00:42:04.095362 Changing prompt to 'Starting depthcharge on Spherion...'
366 00:42:04.095468 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
367 00:42:04.096051 [Enter `^Ec?' for help]
368 00:42:04.096165
369 00:42:04.096266
370 00:42:04.096359 F0: 102B 0000
371 00:42:04.096457
372 00:42:04.096555 F3: 1001 0000 [0200]
373 00:42:04.096651
374 00:42:04.096717 F3: 1001 0000
375 00:42:04.096774
376 00:42:04.096829 F7: 102D 0000
377 00:42:04.096884
378 00:42:04.096945 F1: 0000 0000
379 00:42:04.097004
380 00:42:04.097060 V0: 0000 0000 [0001]
381 00:42:04.097114
382 00:42:04.097172 00: 0007 8000
383 00:42:04.097237
384 00:42:04.097292 01: 0000 0000
385 00:42:04.097347
386 00:42:04.097401 BP: 0C00 0209 [0000]
387 00:42:04.097467
388 00:42:04.097551 G0: 1182 0000
389 00:42:04.097635
390 00:42:04.097706 EC: 0000 0021 [4000]
391 00:42:04.097763
392 00:42:04.097817 S7: 0000 0000 [0000]
393 00:42:04.097872
394 00:42:04.097930 CC: 0000 0000 [0001]
395 00:42:04.097990
396 00:42:04.098044 T0: 0000 0040 [010F]
397 00:42:04.098101
398 00:42:04.098154 Jump to BL
399 00:42:04.098218
400 00:42:04.098273
401 00:42:04.098327
402 00:42:04.098380 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
403 00:42:04.098448 ARM64: Exception handlers installed.
404 00:42:04.098507 ARM64: Testing exception
405 00:42:04.098580 ARM64: Done test exception
406 00:42:04.098636 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
407 00:42:04.098717 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
408 00:42:04.098804 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
409 00:42:04.098891 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
410 00:42:04.098983 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
411 00:42:04.099069 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
412 00:42:04.099155 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
413 00:42:04.099247 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
414 00:42:04.099333 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
415 00:42:04.099420 WDT: Last reset was cold boot
416 00:42:04.099508 SPI1(PAD0) initialized at 2873684 Hz
417 00:42:04.099592 SPI5(PAD0) initialized at 992727 Hz
418 00:42:04.099679 VBOOT: Loading verstage.
419 00:42:04.099767 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
420 00:42:04.099852 FMAP: Found "FLASH" version 1.1 at 0x20000.
421 00:42:04.099941 FMAP: base = 0x0 size = 0x800000 #areas = 25
422 00:42:04.100029 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
423 00:42:04.100116 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
424 00:42:04.100207 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
425 00:42:04.100294 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
426 00:42:04.100378
427 00:42:04.100466
428 00:42:04.100571 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
429 00:42:04.100645 ARM64: Exception handlers installed.
430 00:42:04.100711 ARM64: Testing exception
431 00:42:04.100796 ARM64: Done test exception
432 00:42:04.100881 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
433 00:42:04.100949 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
434 00:42:04.101009 Probing TPM: . done!
435 00:42:04.101063 TPM ready after 0 ms
436 00:42:04.101119 Connected to device vid:did:rid of 1ae0:0028:00
437 00:42:04.101178 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
438 00:42:04.101239 Initialized TPM device CR50 revision 0
439 00:42:04.101293 tlcl_send_startup: Startup return code is 0
440 00:42:04.101348 TPM: setup succeeded
441 00:42:04.101403 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
442 00:42:04.101466 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
443 00:42:04.101522 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
444 00:42:04.101576 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 00:42:04.101631 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
446 00:42:04.101694 in-header: 03 07 00 00 08 00 00 00
447 00:42:04.101752 in-data: aa e4 47 04 13 02 00 00
448 00:42:04.101807 Chrome EC: UHEPI supported
449 00:42:04.101861 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
450 00:42:04.101920 in-header: 03 a9 00 00 08 00 00 00
451 00:42:04.101981 in-data: 84 60 60 08 00 00 00 00
452 00:42:04.102036 Phase 1
453 00:42:04.102090 FMAP: area GBB found @ 3f5000 (12032 bytes)
454 00:42:04.102146 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
455 00:42:04.102209 VB2:vb2_check_recovery() Recovery was requested manually
456 00:42:04.102265 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x7
457 00:42:04.102320 Recovery requested (1009000e)
458 00:42:04.102374 TPM: Extending digest for VBOOT: boot mode into PCR 0
459 00:42:04.102435 tlcl_extend: response is 0
460 00:42:04.102495 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
461 00:42:04.102550 tlcl_extend: response is 0
462 00:42:04.102605 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
463 00:42:04.102671 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
464 00:42:04.102755 BS: bootblock times (exec / console): total (unknown) / 148 ms
465 00:42:04.102840
466 00:42:04.102926
467 00:42:04.103015 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
468 00:42:04.103101 ARM64: Exception handlers installed.
469 00:42:04.103189 ARM64: Testing exception
470 00:42:04.103275 ARM64: Done test exception
471 00:42:04.103360 pmic_efuse_setting: Set efuses in 11 msecs
472 00:42:04.103449 pmwrap_interface_init: Select PMIF_VLD_RDY
473 00:42:04.103536 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
474 00:42:04.103621 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
475 00:42:04.103902 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
476 00:42:04.103998 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
477 00:42:04.104084 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
478 00:42:04.104172 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
479 00:42:04.104260 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
480 00:42:04.104345 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
481 00:42:04.104433 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
482 00:42:04.104521 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
483 00:42:04.104626 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
484 00:42:04.104689 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
485 00:42:04.104748 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
486 00:42:04.104804 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
487 00:42:04.104859 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
488 00:42:04.104919 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
489 00:42:04.104979 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
490 00:42:04.105035 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
491 00:42:04.105090 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
492 00:42:04.105144 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
493 00:42:04.105208 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
494 00:42:04.105264 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
495 00:42:04.105319 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
496 00:42:04.105374 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
497 00:42:04.105434 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
498 00:42:04.105493 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
499 00:42:04.105548 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
500 00:42:04.105602 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
501 00:42:04.105660 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
502 00:42:04.105719 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
503 00:42:04.105774 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
504 00:42:04.105829 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
505 00:42:04.105883 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
506 00:42:04.105958 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
507 00:42:04.106044 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
508 00:42:04.106129 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
509 00:42:04.106219 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
510 00:42:04.106304 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
511 00:42:04.106389 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
512 00:42:04.106479 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
513 00:42:04.106610 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
514 00:42:04.106702 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
515 00:42:04.106788 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
516 00:42:04.106873 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
517 00:42:04.106962 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
518 00:42:04.107048 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
519 00:42:04.107132 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
520 00:42:04.107222 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
521 00:42:04.107308 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
522 00:42:04.107393 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
523 00:42:04.107486 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
524 00:42:04.107572 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x6b6d 0x5bf0 0x8100 0x4c 0xf0f 0x9248
525 00:42:04.107661 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
526 00:42:04.107749 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
527 00:42:04.107835 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
528 00:42:04.107924 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
529 00:42:04.108013 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
530 00:42:04.108098 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
531 00:42:04.108185 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 00:42:04.108272 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x2
533 00:42:04.108358 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
534 00:42:04.108448 [RTC]rtc_osc_init,62: osc32con val = 0xde70
535 00:42:04.108534 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
536 00:42:04.108655 [RTC]rtc_get_frequency_meter,154: input=15, output=772
537 00:42:04.108745 [RTC]rtc_get_frequency_meter,154: input=23, output=958
538 00:42:04.108830 [RTC]rtc_get_frequency_meter,154: input=19, output=866
539 00:42:04.108921 [RTC]rtc_get_frequency_meter,154: input=17, output=818
540 00:42:04.109009 [RTC]rtc_get_frequency_meter,154: input=16, output=797
541 00:42:04.109094 [RTC]rtc_get_frequency_meter,154: input=15, output=772
542 00:42:04.109181 [RTC]rtc_get_frequency_meter,154: input=16, output=796
543 00:42:04.109268 [RTC]rtc_eosc_cali,47: left: 15, middle: 15, right: 16
544 00:42:04.109353 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
545 00:42:04.109655 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
546 00:42:04.109817 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
547 00:42:04.109904 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
548 00:42:04.109994 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
549 00:42:04.110079 ADC[4]: Raw value=903245 ID=7
550 00:42:04.110165 ADC[3]: Raw value=213179 ID=1
551 00:42:04.110252 RAM Code: 0x71
552 00:42:04.110337 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
553 00:42:04.110490 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
554 00:42:04.110551 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
555 00:42:04.110608 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
556 00:42:04.110677 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
557 00:42:04.110740 in-header: 03 07 00 00 08 00 00 00
558 00:42:04.110795 in-data: aa e4 47 04 13 02 00 00
559 00:42:04.110850 Chrome EC: UHEPI supported
560 00:42:04.110905 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
561 00:42:04.110982 in-header: 03 a9 00 00 08 00 00 00
562 00:42:04.111037 in-data: 84 60 60 08 00 00 00 00
563 00:42:04.111092 MRC: failed to locate region type 0.
564 00:42:04.111147 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
565 00:42:04.111223 DRAM-K: Running full calibration
566 00:42:04.111279 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
567 00:42:04.111334 header.status = 0x0
568 00:42:04.111389 header.version = 0x6 (expected: 0x6)
569 00:42:04.111468 header.size = 0xd00 (expected: 0xd00)
570 00:42:04.111554 header.flags = 0x0
571 00:42:04.111639 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
572 00:42:04.111736 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
573 00:42:04.111823 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
574 00:42:04.111908 dram_init: ddr_geometry: 2
575 00:42:04.112004 [EMI] MDL number = 2
576 00:42:04.112089 [EMI] Get MDL freq = 0
577 00:42:04.112198 dram_init: ddr_type: 0
578 00:42:04.112288 is_discrete_lpddr4: 1
579 00:42:04.112374 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
580 00:42:04.112471
581 00:42:04.112565
582 00:42:04.112637 [Bian_co] ETT version 0.0.0.1
583 00:42:04.112714 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
584 00:42:04.112771
585 00:42:04.112826 dramc_set_vcore_voltage set vcore to 650000
586 00:42:04.112880 Read voltage for 800, 4
587 00:42:04.112954 Vio18 = 0
588 00:42:04.113010 Vcore = 650000
589 00:42:04.113064 Vdram = 0
590 00:42:04.113117 Vddq = 0
591 00:42:04.113183 Vmddr = 0
592 00:42:04.113268 dram_init: config_dvfs: 1
593 00:42:04.113354 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
594 00:42:04.113445 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
595 00:42:04.113533 [SwImpedanceCal] DRVP=10, DRVN=17, ODTN=9
596 00:42:04.113618 freq_region=0, Reg: DRVP=10, DRVN=17, ODTN=9
597 00:42:04.113711 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
598 00:42:04.113769 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
599 00:42:04.113823 MEM_TYPE=3, freq_sel=18
600 00:42:04.113878 sv_algorithm_assistance_LP4_1600
601 00:42:04.113952 ============ PULL DRAM RESETB DOWN ============
602 00:42:04.114011 ========== PULL DRAM RESETB DOWN end =========
603 00:42:04.114066 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
604 00:42:04.114122 ===================================
605 00:42:04.114191 LPDDR4 DRAM CONFIGURATION
606 00:42:04.114283 ===================================
607 00:42:04.114395 EX_ROW_EN[0] = 0x0
608 00:42:04.114488 EX_ROW_EN[1] = 0x0
609 00:42:04.114544 LP4Y_EN = 0x0
610 00:42:04.114599 WORK_FSP = 0x0
611 00:42:04.114655 WL = 0x2
612 00:42:04.114728 RL = 0x2
613 00:42:04.114784 BL = 0x2
614 00:42:04.114839 RPST = 0x0
615 00:42:04.114893 RD_PRE = 0x0
616 00:42:04.114969 WR_PRE = 0x1
617 00:42:04.115025 WR_PST = 0x0
618 00:42:04.115080 DBI_WR = 0x0
619 00:42:04.115134 DBI_RD = 0x0
620 00:42:04.115210 OTF = 0x1
621 00:42:04.115267 ===================================
622 00:42:04.115321 ===================================
623 00:42:04.115376 ANA top config
624 00:42:04.115447 ===================================
625 00:42:04.115507 DLL_ASYNC_EN = 0
626 00:42:04.115561 ALL_SLAVE_EN = 1
627 00:42:04.115615 NEW_RANK_MODE = 1
628 00:42:04.115685 DLL_IDLE_MODE = 1
629 00:42:04.115776 LP45_APHY_COMB_EN = 1
630 00:42:04.115831 TX_ODT_DIS = 1
631 00:42:04.115885 NEW_8X_MODE = 1
632 00:42:04.115968 ===================================
633 00:42:04.116055 ===================================
634 00:42:04.116140 data_rate = 1600
635 00:42:04.116235 CKR = 1
636 00:42:04.116320 DQ_P2S_RATIO = 8
637 00:42:04.116406 ===================================
638 00:42:04.116502 CA_P2S_RATIO = 8
639 00:42:04.116621 DQ_CA_OPEN = 0
640 00:42:04.116691 DQ_SEMI_OPEN = 0
641 00:42:04.116752 CA_SEMI_OPEN = 0
642 00:42:04.116807 CA_FULL_RATE = 0
643 00:42:04.116862 DQ_CKDIV4_EN = 1
644 00:42:04.116926 CA_CKDIV4_EN = 1
645 00:42:04.116990 CA_PREDIV_EN = 0
646 00:42:04.117044 PH8_DLY = 0
647 00:42:04.117099 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
648 00:42:04.117153 DQ_AAMCK_DIV = 4
649 00:42:04.117236 CA_AAMCK_DIV = 4
650 00:42:04.117321 CA_ADMCK_DIV = 4
651 00:42:04.117405 DQ_TRACK_CA_EN = 0
652 00:42:04.117487 CA_PICK = 800
653 00:42:04.117573 CA_MCKIO = 800
654 00:42:04.117657 MCKIO_SEMI = 0
655 00:42:04.117731 PLL_FREQ = 3068
656 00:42:04.117787 DQ_UI_PI_RATIO = 32
657 00:42:04.117841 CA_UI_PI_RATIO = 0
658 00:42:04.117895 ===================================
659 00:42:04.117972 ===================================
660 00:42:04.118029 memory_type:LPDDR4
661 00:42:04.118083 GP_NUM : 10
662 00:42:04.118137 SRAM_EN : 1
663 00:42:04.118212 MD32_EN : 0
664 00:42:04.118484 ===================================
665 00:42:04.118549 [ANA_INIT] >>>>>>>>>>>>>>
666 00:42:04.118606 <<<<<< [CONFIGURE PHASE]: ANA_TX
667 00:42:04.118673 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
668 00:42:04.118740 ===================================
669 00:42:04.118811 data_rate = 1600,PCW = 0X7600
670 00:42:04.118881 ===================================
671 00:42:04.118949 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
672 00:42:04.119010 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
673 00:42:04.119106 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 00:42:04.119177 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
675 00:42:04.119251 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
676 00:42:04.119336 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
677 00:42:04.119428 [ANA_INIT] flow start
678 00:42:04.119512 [ANA_INIT] PLL >>>>>>>>
679 00:42:04.119597 [ANA_INIT] PLL <<<<<<<<
680 00:42:04.119688 [ANA_INIT] MIDPI >>>>>>>>
681 00:42:04.119773 [ANA_INIT] MIDPI <<<<<<<<
682 00:42:04.119857 [ANA_INIT] DLL >>>>>>>>
683 00:42:04.119948 [ANA_INIT] flow end
684 00:42:04.120036 ============ LP4 DIFF to SE enter ============
685 00:42:04.120122 ============ LP4 DIFF to SE exit ============
686 00:42:04.120217 [ANA_INIT] <<<<<<<<<<<<<
687 00:42:04.120303 [Flow] Enable top DCM control >>>>>
688 00:42:04.120388 [Flow] Enable top DCM control <<<<<
689 00:42:04.120483 Enable DLL master slave shuffle
690 00:42:04.120588 ==============================================================
691 00:42:04.120663 Gating Mode config
692 00:42:04.120734 ==============================================================
693 00:42:04.120790 Config description:
694 00:42:04.120844 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
695 00:42:04.120905 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
696 00:42:04.120979 SELPH_MODE 0: By rank 1: By Phase
697 00:42:04.121036 ==============================================================
698 00:42:04.121091 GAT_TRACK_EN = 1
699 00:42:04.121146 RX_GATING_MODE = 2
700 00:42:04.121220 RX_GATING_TRACK_MODE = 2
701 00:42:04.121276 SELPH_MODE = 1
702 00:42:04.121330 PICG_EARLY_EN = 1
703 00:42:04.121384 VALID_LAT_VALUE = 1
704 00:42:04.121458 ==============================================================
705 00:42:04.121516 Enter into Gating configuration >>>>
706 00:42:04.121571 Exit from Gating configuration <<<<
707 00:42:04.121625 Enter into DVFS_PRE_config >>>>>
708 00:42:04.121696 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
709 00:42:04.121761 Exit from DVFS_PRE_config <<<<<
710 00:42:04.121816 Enter into PICG configuration >>>>
711 00:42:04.121871 Exit from PICG configuration <<<<
712 00:42:04.121938 [RX_INPUT] configuration >>>>>
713 00:42:04.121999 [RX_INPUT] configuration <<<<<
714 00:42:04.122053 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
715 00:42:04.122108 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
716 00:42:04.122168 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
717 00:42:04.122235 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
718 00:42:04.122290 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
719 00:42:04.122345 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
720 00:42:04.122399 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
721 00:42:04.122475 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
722 00:42:04.122531 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
723 00:42:04.122585 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
724 00:42:04.122641 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
725 00:42:04.122740 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
726 00:42:04.122827 ===================================
727 00:42:04.122913 LPDDR4 DRAM CONFIGURATION
728 00:42:04.122987 ===================================
729 00:42:04.123043 EX_ROW_EN[0] = 0x0
730 00:42:04.123098 EX_ROW_EN[1] = 0x0
731 00:42:04.123152 LP4Y_EN = 0x0
732 00:42:04.123228 WORK_FSP = 0x0
733 00:42:04.123285 WL = 0x2
734 00:42:04.123339 RL = 0x2
735 00:42:04.123393 BL = 0x2
736 00:42:04.123469 RPST = 0x0
737 00:42:04.123525 RD_PRE = 0x0
738 00:42:04.123580 WR_PRE = 0x1
739 00:42:04.123633 WR_PST = 0x0
740 00:42:04.123712 DBI_WR = 0x0
741 00:42:04.123797 DBI_RD = 0x0
742 00:42:04.123881 OTF = 0x1
743 00:42:04.123977 ===================================
744 00:42:04.124063 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
745 00:42:04.124149 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
746 00:42:04.124245 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
747 00:42:04.124331 ===================================
748 00:42:04.124419 LPDDR4 DRAM CONFIGURATION
749 00:42:04.124511 ===================================
750 00:42:04.124624 EX_ROW_EN[0] = 0x10
751 00:42:04.124694 EX_ROW_EN[1] = 0x0
752 00:42:04.124755 LP4Y_EN = 0x0
753 00:42:04.124810 WORK_FSP = 0x0
754 00:42:04.124864 WL = 0x2
755 00:42:04.124930 RL = 0x2
756 00:42:04.124992 BL = 0x2
757 00:42:04.125047 RPST = 0x0
758 00:42:04.125101 RD_PRE = 0x0
759 00:42:04.125155 WR_PRE = 0x1
760 00:42:04.125229 WR_PST = 0x0
761 00:42:04.125285 DBI_WR = 0x0
762 00:42:04.125339 DBI_RD = 0x0
763 00:42:04.125393 OTF = 0x1
764 00:42:04.125469 ===================================
765 00:42:04.125526 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
766 00:42:04.125581 nWR fixed to 40
767 00:42:04.125636 [ModeRegInit_LP4] CH0 RK0
768 00:42:04.125712 [ModeRegInit_LP4] CH0 RK1
769 00:42:04.125768 [ModeRegInit_LP4] CH1 RK0
770 00:42:04.125823 [ModeRegInit_LP4] CH1 RK1
771 00:42:04.125877 match AC timing 13
772 00:42:04.125948 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
773 00:42:04.126209 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
774 00:42:04.126314 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
775 00:42:04.126476 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
776 00:42:04.126534 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
777 00:42:04.126590 [EMI DOE] emi_dcm 0
778 00:42:04.126644 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
779 00:42:04.126721 ==
780 00:42:04.126780 Dram Type= 6, Freq= 0, CH_0, rank 0
781 00:42:04.126836 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 00:42:04.126891 ==
783 00:42:04.126968 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
784 00:42:04.127025 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
785 00:42:04.127081 [CA 0] Center 38 (7~69) winsize 63
786 00:42:04.127135 [CA 1] Center 38 (7~69) winsize 63
787 00:42:04.127211 [CA 2] Center 35 (5~66) winsize 62
788 00:42:04.127267 [CA 3] Center 35 (4~66) winsize 63
789 00:42:04.127322 [CA 4] Center 35 (4~66) winsize 63
790 00:42:04.127376 [CA 5] Center 33 (3~64) winsize 62
791 00:42:04.127445
792 00:42:04.127536 [CmdBusTrainingLP45] Vref(ca) range 1: 32
793 00:42:04.127591
794 00:42:04.127645 [CATrainingPosCal] consider 1 rank data
795 00:42:04.127739 u2DelayCellTimex100 = 270/100 ps
796 00:42:04.127824 CA0 delay=38 (7~69),Diff = 5 PI (36 cell)
797 00:42:04.127911 CA1 delay=38 (7~69),Diff = 5 PI (36 cell)
798 00:42:04.128006 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
799 00:42:04.128090 CA3 delay=35 (4~66),Diff = 2 PI (14 cell)
800 00:42:04.128183 CA4 delay=35 (4~66),Diff = 2 PI (14 cell)
801 00:42:04.128272 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
802 00:42:04.128356
803 00:42:04.128450 CA PerBit enable=1, Macro0, CA PI delay=33
804 00:42:04.128536
805 00:42:04.128670 [CBTSetCACLKResult] CA Dly = 33
806 00:42:04.128737 CS Dly: 6 (0~37)
807 00:42:04.128792 ==
808 00:42:04.128847 Dram Type= 6, Freq= 0, CH_0, rank 1
809 00:42:04.128901 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
810 00:42:04.128978 ==
811 00:42:04.129034 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
812 00:42:04.129089 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
813 00:42:04.129145 [CA 0] Center 38 (7~69) winsize 63
814 00:42:04.129221 [CA 1] Center 38 (7~69) winsize 63
815 00:42:04.129278 [CA 2] Center 36 (6~67) winsize 62
816 00:42:04.129333 [CA 3] Center 36 (5~67) winsize 63
817 00:42:04.129387 [CA 4] Center 35 (4~66) winsize 63
818 00:42:04.129461 [CA 5] Center 34 (4~65) winsize 62
819 00:42:04.129517
820 00:42:04.129572 [CmdBusTrainingLP45] Vref(ca) range 1: 32
821 00:42:04.129626
822 00:42:04.129695 [CATrainingPosCal] consider 2 rank data
823 00:42:04.129754 u2DelayCellTimex100 = 270/100 ps
824 00:42:04.129809 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
825 00:42:04.129863 CA1 delay=38 (7~69),Diff = 4 PI (28 cell)
826 00:42:04.129928 CA2 delay=36 (6~66),Diff = 2 PI (14 cell)
827 00:42:04.129991 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
828 00:42:04.130046 CA4 delay=35 (4~66),Diff = 1 PI (7 cell)
829 00:42:04.130099 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
830 00:42:04.130153
831 00:42:04.130227 CA PerBit enable=1, Macro0, CA PI delay=34
832 00:42:04.130282
833 00:42:04.130336 [CBTSetCACLKResult] CA Dly = 34
834 00:42:04.130391 CS Dly: 6 (0~38)
835 00:42:04.130466
836 00:42:04.130557 ----->DramcWriteLeveling(PI) begin...
837 00:42:04.130643 ==
838 00:42:04.130723 Dram Type= 6, Freq= 0, CH_0, rank 0
839 00:42:04.130779 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
840 00:42:04.130835 ==
841 00:42:04.130888 Write leveling (Byte 0): 30 => 30
842 00:42:04.130963 Write leveling (Byte 1): 29 => 29
843 00:42:04.131021 DramcWriteLeveling(PI) end<-----
844 00:42:04.131076
845 00:42:04.131129 ==
846 00:42:04.131202 Dram Type= 6, Freq= 0, CH_0, rank 0
847 00:42:04.131260 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
848 00:42:04.131314 ==
849 00:42:04.131368 [Gating] SW mode calibration
850 00:42:04.131435 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
851 00:42:04.131522 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
852 00:42:04.131607 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
853 00:42:04.131703 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
854 00:42:04.131791 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
855 00:42:04.131876 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 00:42:04.131972 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 00:42:04.132058 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 00:42:04.132143 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 00:42:04.132239 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 00:42:04.132324 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 00:42:04.132411 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 00:42:04.132505 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 00:42:04.132622 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 00:42:04.132692 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 00:42:04.132751 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 00:42:04.132805 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 00:42:04.132858 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 00:42:04.132916 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
869 00:42:04.132984 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
870 00:42:04.133039 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
871 00:42:04.133093 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
872 00:42:04.133148 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 00:42:04.133223 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 00:42:04.133279 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 00:42:04.133334 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 00:42:04.133388 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 00:42:04.133463 0 9 4 | B1->B0 | 2323 2424 | 0 1 | (0 0) (0 0)
878 00:42:04.133520 0 9 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
879 00:42:04.133574 0 9 12 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
880 00:42:04.133629 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
881 00:42:04.133895 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 00:42:04.134008 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
883 00:42:04.134065 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
884 00:42:04.134120 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
885 00:42:04.134189 0 10 4 | B1->B0 | 3434 2e2e | 1 1 | (1 1) (1 0)
886 00:42:04.134249 0 10 8 | B1->B0 | 3030 2323 | 1 0 | (1 0) (0 0)
887 00:42:04.134304 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
888 00:42:04.134358 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
889 00:42:04.134422 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 00:42:04.134487 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 00:42:04.134542 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
892 00:42:04.134596 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
893 00:42:04.134671 0 11 4 | B1->B0 | 2323 3b3b | 0 0 | (0 0) (0 0)
894 00:42:04.134737 0 11 8 | B1->B0 | 2c2c 4646 | 0 0 | (0 0) (0 0)
895 00:42:04.134793 0 11 12 | B1->B0 | 4040 4646 | 1 0 | (0 0) (0 0)
896 00:42:04.134848 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
897 00:42:04.134903 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 00:42:04.134979 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 00:42:04.135035 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
900 00:42:04.135090 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
901 00:42:04.135144 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
902 00:42:04.135220 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
903 00:42:04.135276 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
904 00:42:04.135331 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 00:42:04.135386 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 00:42:04.135470 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 00:42:04.135556 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 00:42:04.135642 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 00:42:04.135737 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 00:42:04.135823 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 00:42:04.135908 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 00:42:04.136007 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 00:42:04.136092 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 00:42:04.136185 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 00:42:04.136273 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
916 00:42:04.136358 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
917 00:42:04.136453 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
918 00:42:04.136539 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
919 00:42:04.136640 Total UI for P1: 0, mck2ui 16
920 00:42:04.136718 best dqsien dly found for B0: ( 0, 14, 4)
921 00:42:04.136774 Total UI for P1: 0, mck2ui 16
922 00:42:04.136829 best dqsien dly found for B1: ( 0, 14, 6)
923 00:42:04.136883 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
924 00:42:04.136960 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
925 00:42:04.137017
926 00:42:04.137071 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
927 00:42:04.137127 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
928 00:42:04.137199 [Gating] SW calibration Done
929 00:42:04.137257 ==
930 00:42:04.137312 Dram Type= 6, Freq= 0, CH_0, rank 0
931 00:42:04.137367 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
932 00:42:04.137434 ==
933 00:42:04.137496 RX Vref Scan: 0
934 00:42:04.137551
935 00:42:04.137606 RX Vref 0 -> 0, step: 1
936 00:42:04.137664
937 00:42:04.137732 RX Delay -130 -> 252, step: 16
938 00:42:04.137787 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
939 00:42:04.137841 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
940 00:42:04.137896 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
941 00:42:04.137971 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
942 00:42:04.138027 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
943 00:42:04.138082 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
944 00:42:04.138136 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
945 00:42:04.138212 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
946 00:42:04.138268 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
947 00:42:04.138323 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
948 00:42:04.138388 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
949 00:42:04.138467 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
950 00:42:04.138524 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
951 00:42:04.138578 iDelay=222, Bit 13, Center 85 (-18 ~ 189) 208
952 00:42:04.138632 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
953 00:42:04.138707 iDelay=222, Bit 15, Center 77 (-34 ~ 189) 224
954 00:42:04.138764 ==
955 00:42:04.138819 Dram Type= 6, Freq= 0, CH_0, rank 0
956 00:42:04.138873 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
957 00:42:04.138940 ==
958 00:42:04.139000 DQS Delay:
959 00:42:04.139055 DQS0 = 0, DQS1 = 0
960 00:42:04.139108 DQM Delay:
961 00:42:04.139168 DQM0 = 91, DQM1 = 78
962 00:42:04.139248 DQ Delay:
963 00:42:04.139332 DQ0 =93, DQ1 =93, DQ2 =85, DQ3 =85
964 00:42:04.139421 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =101
965 00:42:04.139512 DQ8 =77, DQ9 =61, DQ10 =77, DQ11 =77
966 00:42:04.139597 DQ12 =77, DQ13 =85, DQ14 =93, DQ15 =77
967 00:42:04.139689
968 00:42:04.139775
969 00:42:04.139858 ==
970 00:42:04.139952 Dram Type= 6, Freq= 0, CH_0, rank 0
971 00:42:04.140039 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
972 00:42:04.140123 ==
973 00:42:04.140217
974 00:42:04.140301
975 00:42:04.140384 TX Vref Scan disable
976 00:42:04.140480 == TX Byte 0 ==
977 00:42:04.140588 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
978 00:42:04.140664 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
979 00:42:04.140734 == TX Byte 1 ==
980 00:42:04.140790 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
981 00:42:04.140845 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
982 00:42:04.140899 ==
983 00:42:04.140976 Dram Type= 6, Freq= 0, CH_0, rank 0
984 00:42:04.141032 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
985 00:42:04.141088 ==
986 00:42:04.141143 TX Vref=22, minBit 6, minWin=27, winSum=442
987 00:42:04.141220 TX Vref=24, minBit 8, minWin=27, winSum=450
988 00:42:04.141277 TX Vref=26, minBit 8, minWin=27, winSum=448
989 00:42:04.141528 TX Vref=28, minBit 6, minWin=28, winSum=457
990 00:42:04.141621 TX Vref=30, minBit 8, minWin=28, winSum=457
991 00:42:04.141712 TX Vref=32, minBit 8, minWin=28, winSum=458
992 00:42:04.141771 [TxChooseVref] Worse bit 8, Min win 28, Win sum 458, Final Vref 32
993 00:42:04.141826
994 00:42:04.141880 Final TX Range 1 Vref 32
995 00:42:04.141956
996 00:42:04.142013 ==
997 00:42:04.142068 Dram Type= 6, Freq= 0, CH_0, rank 0
998 00:42:04.142122 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
999 00:42:04.142191 ==
1000 00:42:04.142251
1001 00:42:04.142306
1002 00:42:04.142375 TX Vref Scan disable
1003 00:42:04.142467 == TX Byte 0 ==
1004 00:42:04.142524 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1005 00:42:04.142579 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1006 00:42:04.142633 == TX Byte 1 ==
1007 00:42:04.142694 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1008 00:42:04.142751 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1009 00:42:04.142805
1010 00:42:04.142858 [DATLAT]
1011 00:42:04.142916 Freq=800, CH0 RK0
1012 00:42:04.142978
1013 00:42:04.143033 DATLAT Default: 0xa
1014 00:42:04.143087 0, 0xFFFF, sum = 0
1015 00:42:04.143143 1, 0xFFFF, sum = 0
1016 00:42:04.143212 2, 0xFFFF, sum = 0
1017 00:42:04.143298 3, 0xFFFF, sum = 0
1018 00:42:04.143387 4, 0xFFFF, sum = 0
1019 00:42:04.143478 5, 0xFFFF, sum = 0
1020 00:42:04.143563 6, 0xFFFF, sum = 0
1021 00:42:04.143648 7, 0xFFFF, sum = 0
1022 00:42:04.143739 8, 0xFFFF, sum = 0
1023 00:42:04.143824 9, 0x0, sum = 1
1024 00:42:04.143913 10, 0x0, sum = 2
1025 00:42:04.144008 11, 0x0, sum = 3
1026 00:42:04.144095 12, 0x0, sum = 4
1027 00:42:04.144183 best_step = 10
1028 00:42:04.144269
1029 00:42:04.144351 ==
1030 00:42:04.144437 Dram Type= 6, Freq= 0, CH_0, rank 0
1031 00:42:04.144523 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1032 00:42:04.144628 ==
1033 00:42:04.144689 RX Vref Scan: 1
1034 00:42:04.144748
1035 00:42:04.144802 Set Vref Range= 32 -> 127
1036 00:42:04.144856
1037 00:42:04.144913 RX Vref 32 -> 127, step: 1
1038 00:42:04.144971
1039 00:42:04.145025 RX Delay -95 -> 252, step: 8
1040 00:42:04.145078
1041 00:42:04.145131 Set Vref, RX VrefLevel [Byte0]: 32
1042 00:42:04.145191 [Byte1]: 32
1043 00:42:04.145250
1044 00:42:04.145303 Set Vref, RX VrefLevel [Byte0]: 33
1045 00:42:04.145357 [Byte1]: 33
1046 00:42:04.145413
1047 00:42:04.145476 Set Vref, RX VrefLevel [Byte0]: 34
1048 00:42:04.145559 [Byte1]: 34
1049 00:42:04.145641
1050 00:42:04.145707 Set Vref, RX VrefLevel [Byte0]: 35
1051 00:42:04.145762 [Byte1]: 35
1052 00:42:04.145816
1053 00:42:04.145869 Set Vref, RX VrefLevel [Byte0]: 36
1054 00:42:04.145927 [Byte1]: 36
1055 00:42:04.145985
1056 00:42:04.146039 Set Vref, RX VrefLevel [Byte0]: 37
1057 00:42:04.146092 [Byte1]: 37
1058 00:42:04.146146
1059 00:42:04.146207 Set Vref, RX VrefLevel [Byte0]: 38
1060 00:42:04.146262 [Byte1]: 38
1061 00:42:04.146315
1062 00:42:04.146368 Set Vref, RX VrefLevel [Byte0]: 39
1063 00:42:04.146426 [Byte1]: 39
1064 00:42:04.146484
1065 00:42:04.146538 Set Vref, RX VrefLevel [Byte0]: 40
1066 00:42:04.146591 [Byte1]: 40
1067 00:42:04.146644
1068 00:42:04.146729 Set Vref, RX VrefLevel [Byte0]: 41
1069 00:42:04.146847 [Byte1]: 41
1070 00:42:04.146903
1071 00:42:04.146989 Set Vref, RX VrefLevel [Byte0]: 42
1072 00:42:04.147072 [Byte1]: 42
1073 00:42:04.147155
1074 00:42:04.147243 Set Vref, RX VrefLevel [Byte0]: 43
1075 00:42:04.147326 [Byte1]: 43
1076 00:42:04.147409
1077 00:42:04.147495 Set Vref, RX VrefLevel [Byte0]: 44
1078 00:42:04.147578 [Byte1]: 44
1079 00:42:04.147662
1080 00:42:04.147748 Set Vref, RX VrefLevel [Byte0]: 45
1081 00:42:04.147831 [Byte1]: 45
1082 00:42:04.147915
1083 00:42:04.148001 Set Vref, RX VrefLevel [Byte0]: 46
1084 00:42:04.148084 [Byte1]: 46
1085 00:42:04.148169
1086 00:42:04.148254 Set Vref, RX VrefLevel [Byte0]: 47
1087 00:42:04.148336 [Byte1]: 47
1088 00:42:04.148421
1089 00:42:04.148506 Set Vref, RX VrefLevel [Byte0]: 48
1090 00:42:04.148605 [Byte1]: 48
1091 00:42:04.148678
1092 00:42:04.148737 Set Vref, RX VrefLevel [Byte0]: 49
1093 00:42:04.148791 [Byte1]: 49
1094 00:42:04.148845
1095 00:42:04.148898 Set Vref, RX VrefLevel [Byte0]: 50
1096 00:42:04.148959 [Byte1]: 50
1097 00:42:04.149014
1098 00:42:04.149067 Set Vref, RX VrefLevel [Byte0]: 51
1099 00:42:04.149120 [Byte1]: 51
1100 00:42:04.149178
1101 00:42:04.149237 Set Vref, RX VrefLevel [Byte0]: 52
1102 00:42:04.149290 [Byte1]: 52
1103 00:42:04.149344
1104 00:42:04.149396 Set Vref, RX VrefLevel [Byte0]: 53
1105 00:42:04.149458 [Byte1]: 53
1106 00:42:04.149511
1107 00:42:04.149564 Set Vref, RX VrefLevel [Byte0]: 54
1108 00:42:04.149617 [Byte1]: 54
1109 00:42:04.149676
1110 00:42:04.149734 Set Vref, RX VrefLevel [Byte0]: 55
1111 00:42:04.149787 [Byte1]: 55
1112 00:42:04.149841
1113 00:42:04.149894 Set Vref, RX VrefLevel [Byte0]: 56
1114 00:42:04.149956 [Byte1]: 56
1115 00:42:04.150011
1116 00:42:04.150064 Set Vref, RX VrefLevel [Byte0]: 57
1117 00:42:04.150117 [Byte1]: 57
1118 00:42:04.150174
1119 00:42:04.150232 Set Vref, RX VrefLevel [Byte0]: 58
1120 00:42:04.150285 [Byte1]: 58
1121 00:42:04.150338
1122 00:42:04.150391 Set Vref, RX VrefLevel [Byte0]: 59
1123 00:42:04.150494 [Byte1]: 59
1124 00:42:04.150552
1125 00:42:04.150605 Set Vref, RX VrefLevel [Byte0]: 60
1126 00:42:04.150661 [Byte1]: 60
1127 00:42:04.150724
1128 00:42:04.150806 Set Vref, RX VrefLevel [Byte0]: 61
1129 00:42:04.150889 [Byte1]: 61
1130 00:42:04.150976
1131 00:42:04.151059 Set Vref, RX VrefLevel [Byte0]: 62
1132 00:42:04.151141 [Byte1]: 62
1133 00:42:04.151229
1134 00:42:04.151311 Set Vref, RX VrefLevel [Byte0]: 63
1135 00:42:04.151394 [Byte1]: 63
1136 00:42:04.151481
1137 00:42:04.151564 Set Vref, RX VrefLevel [Byte0]: 64
1138 00:42:04.151646 [Byte1]: 64
1139 00:42:04.151734
1140 00:42:04.151816 Set Vref, RX VrefLevel [Byte0]: 65
1141 00:42:04.151899 [Byte1]: 65
1142 00:42:04.151962
1143 00:42:04.152017 Set Vref, RX VrefLevel [Byte0]: 66
1144 00:42:04.152070 [Byte1]: 66
1145 00:42:04.152123
1146 00:42:04.152181 Set Vref, RX VrefLevel [Byte0]: 67
1147 00:42:04.152240 [Byte1]: 67
1148 00:42:04.152293
1149 00:42:04.152346 Set Vref, RX VrefLevel [Byte0]: 68
1150 00:42:04.152399 [Byte1]: 68
1151 00:42:04.152483
1152 00:42:04.152587 Set Vref, RX VrefLevel [Byte0]: 69
1153 00:42:04.152658 [Byte1]: 69
1154 00:42:04.152719
1155 00:42:04.152772 Set Vref, RX VrefLevel [Byte0]: 70
1156 00:42:04.152826 [Byte1]: 70
1157 00:42:04.152879
1158 00:42:04.153138 Set Vref, RX VrefLevel [Byte0]: 71
1159 00:42:04.153261 [Byte1]: 71
1160 00:42:04.153332
1161 00:42:04.153386 Set Vref, RX VrefLevel [Byte0]: 72
1162 00:42:04.153449 [Byte1]: 72
1163 00:42:04.153505
1164 00:42:04.153559 Set Vref, RX VrefLevel [Byte0]: 73
1165 00:42:04.153612 [Byte1]: 73
1166 00:42:04.153670
1167 00:42:04.153729 Set Vref, RX VrefLevel [Byte0]: 74
1168 00:42:04.153783 [Byte1]: 74
1169 00:42:04.153836
1170 00:42:04.153889 Set Vref, RX VrefLevel [Byte0]: 75
1171 00:42:04.153952 [Byte1]: 75
1172 00:42:04.154008
1173 00:42:04.154061 Set Vref, RX VrefLevel [Byte0]: 76
1174 00:42:04.154114 [Byte1]: 76
1175 00:42:04.154172
1176 00:42:04.154230 Set Vref, RX VrefLevel [Byte0]: 77
1177 00:42:04.154303 [Byte1]: 77
1178 00:42:04.154359
1179 00:42:04.154417 Set Vref, RX VrefLevel [Byte0]: 78
1180 00:42:04.154503 [Byte1]: 78
1181 00:42:04.154585
1182 00:42:04.154671 Final RX Vref Byte 0 = 62 to rank0
1183 00:42:04.154757 Final RX Vref Byte 1 = 59 to rank0
1184 00:42:04.154841 Final RX Vref Byte 0 = 62 to rank1
1185 00:42:04.154927 Final RX Vref Byte 1 = 59 to rank1==
1186 00:42:04.155013 Dram Type= 6, Freq= 0, CH_0, rank 0
1187 00:42:04.155097 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1188 00:42:04.155183 ==
1189 00:42:04.155268 DQS Delay:
1190 00:42:04.155351 DQS0 = 0, DQS1 = 0
1191 00:42:04.155441 DQM Delay:
1192 00:42:04.155526 DQM0 = 93, DQM1 = 81
1193 00:42:04.155608 DQ Delay:
1194 00:42:04.155695 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1195 00:42:04.155780 DQ4 =92, DQ5 =80, DQ6 =104, DQ7 =104
1196 00:42:04.155863 DQ8 =72, DQ9 =72, DQ10 =84, DQ11 =76
1197 00:42:04.155950 DQ12 =84, DQ13 =80, DQ14 =92, DQ15 =92
1198 00:42:04.156034
1199 00:42:04.156116
1200 00:42:04.156204 [DQSOSCAuto] RK0, (LSB)MR18= 0x443f, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 392 ps
1201 00:42:04.156289 CH0 RK0: MR19=606, MR18=443F
1202 00:42:04.156373 CH0_RK0: MR19=0x606, MR18=0x443F, DQSOSC=392, MR23=63, INC=96, DEC=64
1203 00:42:04.156460
1204 00:42:04.156543 ----->DramcWriteLeveling(PI) begin...
1205 00:42:04.156644 ==
1206 00:42:04.156707 Dram Type= 6, Freq= 0, CH_0, rank 1
1207 00:42:04.156762 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1208 00:42:04.156816 ==
1209 00:42:04.156869 Write leveling (Byte 0): 32 => 32
1210 00:42:04.156928 Write leveling (Byte 1): 28 => 28
1211 00:42:04.156986 DramcWriteLeveling(PI) end<-----
1212 00:42:04.157040
1213 00:42:04.157092 ==
1214 00:42:04.157146 Dram Type= 6, Freq= 0, CH_0, rank 1
1215 00:42:04.157207 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1216 00:42:04.157263 ==
1217 00:42:04.157317 [Gating] SW mode calibration
1218 00:42:04.157371 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1219 00:42:04.157431 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1220 00:42:04.157490 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1221 00:42:04.157544 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1222 00:42:04.157598 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 00:42:04.157652 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 00:42:04.157717 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 00:42:04.157801 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 00:42:04.157884 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 00:42:04.157972 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 00:42:04.158056 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 00:42:04.158139 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 00:42:04.158227 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 00:42:04.158311 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 00:42:04.158394 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 00:42:04.158490 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 00:42:04.158576 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 00:42:04.158661 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 00:42:04.158748 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1237 00:42:04.158831 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 1)
1238 00:42:04.158916 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1239 00:42:04.159003 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1240 00:42:04.159086 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1241 00:42:04.159172 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1242 00:42:04.159258 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1243 00:42:04.159342 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1244 00:42:04.159427 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1245 00:42:04.159513 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1246 00:42:04.159597 0 9 8 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
1247 00:42:04.159682 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1248 00:42:04.159768 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1249 00:42:04.159851 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1250 00:42:04.159937 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1251 00:42:04.160023 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1252 00:42:04.160106 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1253 00:42:04.160192 0 10 4 | B1->B0 | 3333 2f2f | 1 1 | (1 0) (1 0)
1254 00:42:04.160278 0 10 8 | B1->B0 | 2d2d 2323 | 1 0 | (1 0) (0 0)
1255 00:42:04.160362 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1256 00:42:04.160449 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1257 00:42:04.160534 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1258 00:42:04.160658 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1259 00:42:04.160745 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1260 00:42:04.160829 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1261 00:42:04.160913 0 11 4 | B1->B0 | 2626 2f2f | 0 0 | (0 0) (0 0)
1262 00:42:04.160973 0 11 8 | B1->B0 | 3939 4343 | 0 0 | (0 0) (0 0)
1263 00:42:04.161028 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1264 00:42:04.161083 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1265 00:42:04.161339 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1266 00:42:04.161434 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1267 00:42:04.161552 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1268 00:42:04.161636 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1269 00:42:04.161725 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1270 00:42:04.161812 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1271 00:42:04.161869 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1272 00:42:04.161929 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1273 00:42:04.161988 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1274 00:42:04.162042 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1275 00:42:04.162096 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1276 00:42:04.162149 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1277 00:42:04.162212 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1278 00:42:04.162266 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1279 00:42:04.162319 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1280 00:42:04.162373 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1281 00:42:04.162451 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1282 00:42:04.162544 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1283 00:42:04.162599 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1284 00:42:04.162653 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1285 00:42:04.162715 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1286 00:42:04.162770 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1287 00:42:04.162823 Total UI for P1: 0, mck2ui 16
1288 00:42:04.162877 best dqsien dly found for B0: ( 0, 14, 4)
1289 00:42:04.162936 Total UI for P1: 0, mck2ui 16
1290 00:42:04.162996 best dqsien dly found for B1: ( 0, 14, 6)
1291 00:42:04.163049 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1292 00:42:04.163119 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1293 00:42:04.163194
1294 00:42:04.163251 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1295 00:42:04.163305 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1296 00:42:04.163359 [Gating] SW calibration Done
1297 00:42:04.163416 ==
1298 00:42:04.163473 Dram Type= 6, Freq= 0, CH_0, rank 1
1299 00:42:04.163526 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1300 00:42:04.163580 ==
1301 00:42:04.163633 RX Vref Scan: 0
1302 00:42:04.163694
1303 00:42:04.163778 RX Vref 0 -> 0, step: 1
1304 00:42:04.163860
1305 00:42:04.163947 RX Delay -130 -> 252, step: 16
1306 00:42:04.164033 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
1307 00:42:04.164116 iDelay=206, Bit 1, Center 93 (-18 ~ 205) 224
1308 00:42:04.164204 iDelay=206, Bit 2, Center 93 (-18 ~ 205) 224
1309 00:42:04.164288 iDelay=206, Bit 3, Center 85 (-18 ~ 189) 208
1310 00:42:04.164372 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1311 00:42:04.164460 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
1312 00:42:04.164544 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1313 00:42:04.164647 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1314 00:42:04.164710 iDelay=206, Bit 8, Center 77 (-34 ~ 189) 224
1315 00:42:04.164765 iDelay=206, Bit 9, Center 61 (-50 ~ 173) 224
1316 00:42:04.164819 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
1317 00:42:04.164873 iDelay=206, Bit 11, Center 85 (-18 ~ 189) 208
1318 00:42:04.164931 iDelay=206, Bit 12, Center 85 (-18 ~ 189) 208
1319 00:42:04.164990 iDelay=206, Bit 13, Center 85 (-18 ~ 189) 208
1320 00:42:04.165044 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
1321 00:42:04.165098 iDelay=206, Bit 15, Center 93 (-18 ~ 205) 224
1322 00:42:04.165151 ==
1323 00:42:04.165212 Dram Type= 6, Freq= 0, CH_0, rank 1
1324 00:42:04.165267 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1325 00:42:04.165321 ==
1326 00:42:04.165374 DQS Delay:
1327 00:42:04.165433 DQS0 = 0, DQS1 = 0
1328 00:42:04.165489 DQM Delay:
1329 00:42:04.165544 DQM0 = 90, DQM1 = 82
1330 00:42:04.165598 DQ Delay:
1331 00:42:04.165651 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =85
1332 00:42:04.165710 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =93
1333 00:42:04.165768 DQ8 =77, DQ9 =61, DQ10 =77, DQ11 =85
1334 00:42:04.165823 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =93
1335 00:42:04.165876
1336 00:42:04.165935
1337 00:42:04.165992 ==
1338 00:42:04.166047 Dram Type= 6, Freq= 0, CH_0, rank 1
1339 00:42:04.166099 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1340 00:42:04.166154 ==
1341 00:42:04.166213
1342 00:42:04.166270
1343 00:42:04.166323 TX Vref Scan disable
1344 00:42:04.166376 == TX Byte 0 ==
1345 00:42:04.166471 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1346 00:42:04.166545 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1347 00:42:04.166602 == TX Byte 1 ==
1348 00:42:04.166658 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1349 00:42:04.166719 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1350 00:42:04.166773 ==
1351 00:42:04.166827 Dram Type= 6, Freq= 0, CH_0, rank 1
1352 00:42:04.166880 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1353 00:42:04.166940 ==
1354 00:42:04.166999 TX Vref=22, minBit 8, minWin=27, winSum=448
1355 00:42:04.167054 TX Vref=24, minBit 8, minWin=27, winSum=449
1356 00:42:04.167107 TX Vref=26, minBit 8, minWin=27, winSum=455
1357 00:42:04.167165 TX Vref=28, minBit 8, minWin=27, winSum=456
1358 00:42:04.167221 TX Vref=30, minBit 8, minWin=27, winSum=458
1359 00:42:04.167279 TX Vref=32, minBit 8, minWin=27, winSum=456
1360 00:42:04.167332 [TxChooseVref] Worse bit 8, Min win 27, Win sum 458, Final Vref 30
1361 00:42:04.167385
1362 00:42:04.167444 Final TX Range 1 Vref 30
1363 00:42:04.167500
1364 00:42:04.167552 ==
1365 00:42:04.167604 Dram Type= 6, Freq= 0, CH_0, rank 1
1366 00:42:04.167659 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1367 00:42:04.167714 ==
1368 00:42:04.167770
1369 00:42:04.167821
1370 00:42:04.167873 TX Vref Scan disable
1371 00:42:04.167933 == TX Byte 0 ==
1372 00:42:04.168017 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1373 00:42:04.168100 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1374 00:42:04.168207 == TX Byte 1 ==
1375 00:42:04.168308 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1376 00:42:04.168390 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1377 00:42:04.168474
1378 00:42:04.168578 [DATLAT]
1379 00:42:04.168676 Freq=800, CH0 RK1
1380 00:42:04.168760
1381 00:42:04.168842 DATLAT Default: 0xa
1382 00:42:04.168925 0, 0xFFFF, sum = 0
1383 00:42:04.169011 1, 0xFFFF, sum = 0
1384 00:42:04.169095 2, 0xFFFF, sum = 0
1385 00:42:04.169180 3, 0xFFFF, sum = 0
1386 00:42:04.169266 4, 0xFFFF, sum = 0
1387 00:42:04.169349 5, 0xFFFF, sum = 0
1388 00:42:04.169434 6, 0xFFFF, sum = 0
1389 00:42:04.169519 7, 0xFFFF, sum = 0
1390 00:42:04.169603 8, 0xFFFF, sum = 0
1391 00:42:04.169689 9, 0x0, sum = 1
1392 00:42:04.169972 10, 0x0, sum = 2
1393 00:42:04.170064 11, 0x0, sum = 3
1394 00:42:04.170148 12, 0x0, sum = 4
1395 00:42:04.170235 best_step = 10
1396 00:42:04.170351
1397 00:42:04.170444 ==
1398 00:42:04.170529 Dram Type= 6, Freq= 0, CH_0, rank 1
1399 00:42:04.170611 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1400 00:42:04.170696 ==
1401 00:42:04.170779 RX Vref Scan: 0
1402 00:42:04.170861
1403 00:42:04.170944 RX Vref 0 -> 0, step: 1
1404 00:42:04.171027
1405 00:42:04.171108 RX Delay -95 -> 252, step: 8
1406 00:42:04.171195 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1407 00:42:04.171337 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1408 00:42:04.171421 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1409 00:42:04.171505 iDelay=209, Bit 3, Center 84 (-23 ~ 192) 216
1410 00:42:04.171587 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1411 00:42:04.171671 iDelay=209, Bit 5, Center 80 (-31 ~ 192) 224
1412 00:42:04.171755 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1413 00:42:04.171837 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1414 00:42:04.171922 iDelay=209, Bit 8, Center 72 (-31 ~ 176) 208
1415 00:42:04.172006 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1416 00:42:04.172088 iDelay=209, Bit 10, Center 80 (-23 ~ 184) 208
1417 00:42:04.172172 iDelay=209, Bit 11, Center 80 (-23 ~ 184) 208
1418 00:42:04.172257 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1419 00:42:04.172340 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1420 00:42:04.172430 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1421 00:42:04.172518 iDelay=209, Bit 15, Center 92 (-15 ~ 200) 216
1422 00:42:04.172640 ==
1423 00:42:04.172722 Dram Type= 6, Freq= 0, CH_0, rank 1
1424 00:42:04.172808 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1425 00:42:04.172890 ==
1426 00:42:04.172973 DQS Delay:
1427 00:42:04.173057 DQS0 = 0, DQS1 = 0
1428 00:42:04.173139 DQM Delay:
1429 00:42:04.173219 DQM0 = 90, DQM1 = 81
1430 00:42:04.173305 DQ Delay:
1431 00:42:04.173388 DQ0 =88, DQ1 =92, DQ2 =88, DQ3 =84
1432 00:42:04.173470 DQ4 =92, DQ5 =80, DQ6 =100, DQ7 =96
1433 00:42:04.173554 DQ8 =72, DQ9 =68, DQ10 =80, DQ11 =80
1434 00:42:04.173638 DQ12 =84, DQ13 =84, DQ14 =88, DQ15 =92
1435 00:42:04.173718
1436 00:42:04.173802
1437 00:42:04.173886 [DQSOSCAuto] RK1, (LSB)MR18= 0x441d, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 392 ps
1438 00:42:04.173969 CH0 RK1: MR19=606, MR18=441D
1439 00:42:04.174054 CH0_RK1: MR19=0x606, MR18=0x441D, DQSOSC=392, MR23=63, INC=96, DEC=64
1440 00:42:04.174139 [RxdqsGatingPostProcess] freq 800
1441 00:42:04.174221 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1442 00:42:04.174306 Pre-setting of DQS Precalculation
1443 00:42:04.174398 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1444 00:42:04.174481 ==
1445 00:42:04.174567 Dram Type= 6, Freq= 0, CH_1, rank 0
1446 00:42:04.174651 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1447 00:42:04.174733 ==
1448 00:42:04.174819 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1449 00:42:04.174904 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1450 00:42:04.174986 [CA 0] Center 36 (6~67) winsize 62
1451 00:42:04.175071 [CA 1] Center 37 (6~68) winsize 63
1452 00:42:04.175154 [CA 2] Center 35 (5~65) winsize 61
1453 00:42:04.175236 [CA 3] Center 34 (4~65) winsize 62
1454 00:42:04.175320 [CA 4] Center 34 (4~65) winsize 62
1455 00:42:04.175404 [CA 5] Center 34 (3~65) winsize 63
1456 00:42:04.175484
1457 00:42:04.175569 [CmdBusTrainingLP45] Vref(ca) range 1: 30
1458 00:42:04.175652
1459 00:42:04.175734 [CATrainingPosCal] consider 1 rank data
1460 00:42:04.175818 u2DelayCellTimex100 = 270/100 ps
1461 00:42:04.175902 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1462 00:42:04.175984 CA1 delay=37 (6~68),Diff = 3 PI (21 cell)
1463 00:42:04.176069 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1464 00:42:04.176152 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1465 00:42:04.176234 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1466 00:42:04.176318 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1467 00:42:04.176401
1468 00:42:04.176482 CA PerBit enable=1, Macro0, CA PI delay=34
1469 00:42:04.176590
1470 00:42:04.176664 [CBTSetCACLKResult] CA Dly = 34
1471 00:42:04.176717 CS Dly: 5 (0~36)
1472 00:42:04.176770 ==
1473 00:42:04.176829 Dram Type= 6, Freq= 0, CH_1, rank 1
1474 00:42:04.176884 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1475 00:42:04.176937 ==
1476 00:42:04.176989 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1477 00:42:04.177046 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1478 00:42:04.177099 [CA 0] Center 37 (7~68) winsize 62
1479 00:42:04.177155 [CA 1] Center 37 (6~68) winsize 63
1480 00:42:04.177207 [CA 2] Center 35 (5~66) winsize 62
1481 00:42:04.177259 [CA 3] Center 34 (4~65) winsize 62
1482 00:42:04.177316 [CA 4] Center 34 (4~65) winsize 62
1483 00:42:04.177371 [CA 5] Center 34 (4~65) winsize 62
1484 00:42:04.177424
1485 00:42:04.177476 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1486 00:42:04.177528
1487 00:42:04.177587 [CATrainingPosCal] consider 2 rank data
1488 00:42:04.177640 u2DelayCellTimex100 = 270/100 ps
1489 00:42:04.177691 CA0 delay=37 (7~67),Diff = 3 PI (21 cell)
1490 00:42:04.177743 CA1 delay=37 (6~68),Diff = 3 PI (21 cell)
1491 00:42:04.177800 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1492 00:42:04.177857 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1493 00:42:04.177908 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1494 00:42:04.177960 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1495 00:42:04.178011
1496 00:42:04.178070 CA PerBit enable=1, Macro0, CA PI delay=34
1497 00:42:04.178125
1498 00:42:04.178177 [CBTSetCACLKResult] CA Dly = 34
1499 00:42:04.178229 CS Dly: 5 (0~37)
1500 00:42:04.178281
1501 00:42:04.178340 ----->DramcWriteLeveling(PI) begin...
1502 00:42:04.178394 ==
1503 00:42:04.178446 Dram Type= 6, Freq= 0, CH_1, rank 0
1504 00:42:04.178497 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1505 00:42:04.178553 ==
1506 00:42:04.178610 Write leveling (Byte 0): 29 => 29
1507 00:42:04.178662 Write leveling (Byte 1): 30 => 30
1508 00:42:04.178714 DramcWriteLeveling(PI) end<-----
1509 00:42:04.178787
1510 00:42:04.178845 ==
1511 00:42:04.178898 Dram Type= 6, Freq= 0, CH_1, rank 0
1512 00:42:04.178950 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1513 00:42:04.179003 ==
1514 00:42:04.179060 [Gating] SW mode calibration
1515 00:42:04.179116 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1516 00:42:04.179170 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1517 00:42:04.179223 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1518 00:42:04.179473 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1519 00:42:04.179535 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 00:42:04.179595 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 00:42:04.179649 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 00:42:04.179702 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 00:42:04.179753 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 00:42:04.179813 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 00:42:04.179869 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 00:42:04.179922 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 00:42:04.179974 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 00:42:04.180026 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 00:42:04.180113 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 00:42:04.180195 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 00:42:04.180277 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 00:42:04.180365 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 00:42:04.180447 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1534 00:42:04.180529 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1535 00:42:04.180644 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1536 00:42:04.180697 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1537 00:42:04.180750 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1538 00:42:04.180807 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1539 00:42:04.180864 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1540 00:42:04.180917 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1541 00:42:04.180969 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1542 00:42:04.181020 0 9 4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
1543 00:42:04.181081 0 9 8 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
1544 00:42:04.181134 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1545 00:42:04.181185 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1546 00:42:04.181237 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1547 00:42:04.181292 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1548 00:42:04.181349 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1549 00:42:04.181401 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
1550 00:42:04.181453 0 10 4 | B1->B0 | 3030 2f2f | 0 1 | (0 1) (1 0)
1551 00:42:04.181505 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1552 00:42:04.181564 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1553 00:42:04.181620 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1554 00:42:04.181673 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1555 00:42:04.181725 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1556 00:42:04.181777 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1557 00:42:04.181837 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1558 00:42:04.181891 0 11 4 | B1->B0 | 2f2f 3636 | 1 0 | (0 0) (0 0)
1559 00:42:04.181943 0 11 8 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
1560 00:42:04.181995 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1561 00:42:04.182051 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1562 00:42:04.182108 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1563 00:42:04.182161 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1564 00:42:04.182213 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1565 00:42:04.182265 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1566 00:42:04.182327 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1567 00:42:04.182381 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1568 00:42:04.182433 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1569 00:42:04.182484 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1570 00:42:04.182541 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1571 00:42:04.182597 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1572 00:42:04.182650 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1573 00:42:04.182705 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1574 00:42:04.182798 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1575 00:42:04.182883 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1576 00:42:04.182964 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1577 00:42:04.183046 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1578 00:42:04.183128 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1579 00:42:04.183209 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1580 00:42:04.183291 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1581 00:42:04.183373 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1582 00:42:04.183456 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1583 00:42:04.183538 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1584 00:42:04.183619 Total UI for P1: 0, mck2ui 16
1585 00:42:04.183702 best dqsien dly found for B0: ( 0, 14, 4)
1586 00:42:04.183784 Total UI for P1: 0, mck2ui 16
1587 00:42:04.183867 best dqsien dly found for B1: ( 0, 14, 4)
1588 00:42:04.183948 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1589 00:42:04.184031 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1590 00:42:04.184111
1591 00:42:04.184194 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1592 00:42:04.184257 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1593 00:42:04.184338 [Gating] SW calibration Done
1594 00:42:04.184422 ==
1595 00:42:04.184509 Dram Type= 6, Freq= 0, CH_1, rank 0
1596 00:42:04.184627 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1597 00:42:04.184683 ==
1598 00:42:04.184735 RX Vref Scan: 0
1599 00:42:04.184790
1600 00:42:04.184851 RX Vref 0 -> 0, step: 1
1601 00:42:04.184903
1602 00:42:04.184955 RX Delay -130 -> 252, step: 16
1603 00:42:04.185013 iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208
1604 00:42:04.185065 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1605 00:42:04.185118 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1606 00:42:04.185175 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1607 00:42:04.185422 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1608 00:42:04.185481 iDelay=222, Bit 5, Center 101 (-2 ~ 205) 208
1609 00:42:04.185539 iDelay=222, Bit 6, Center 109 (-2 ~ 221) 224
1610 00:42:04.185593 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1611 00:42:04.185645 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1612 00:42:04.185700 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1613 00:42:04.185753 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1614 00:42:04.185805 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1615 00:42:04.185862 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1616 00:42:04.185918 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1617 00:42:04.185973 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1618 00:42:04.186025 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1619 00:42:04.186085 ==
1620 00:42:04.186138 Dram Type= 6, Freq= 0, CH_1, rank 0
1621 00:42:04.186190 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1622 00:42:04.186243 ==
1623 00:42:04.186299 DQS Delay:
1624 00:42:04.186356 DQS0 = 0, DQS1 = 0
1625 00:42:04.186410 DQM Delay:
1626 00:42:04.186462 DQM0 = 93, DQM1 = 82
1627 00:42:04.186513 DQ Delay:
1628 00:42:04.186573 DQ0 =101, DQ1 =85, DQ2 =77, DQ3 =93
1629 00:42:04.186629 DQ4 =85, DQ5 =101, DQ6 =109, DQ7 =93
1630 00:42:04.186681 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
1631 00:42:04.186733 DQ12 =93, DQ13 =93, DQ14 =85, DQ15 =85
1632 00:42:04.186806
1633 00:42:04.186868
1634 00:42:04.186971 ==
1635 00:42:04.187056 Dram Type= 6, Freq= 0, CH_1, rank 0
1636 00:42:04.187141 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1637 00:42:04.187223 ==
1638 00:42:04.187303
1639 00:42:04.187361
1640 00:42:04.187416 TX Vref Scan disable
1641 00:42:04.187469 == TX Byte 0 ==
1642 00:42:04.187520 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1643 00:42:04.187605 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1644 00:42:04.187687 == TX Byte 1 ==
1645 00:42:04.187768 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1646 00:42:04.187834 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1647 00:42:04.187916 ==
1648 00:42:04.187998 Dram Type= 6, Freq= 0, CH_1, rank 0
1649 00:42:04.188084 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1650 00:42:04.188166 ==
1651 00:42:04.188248 TX Vref=22, minBit 15, minWin=26, winSum=444
1652 00:42:04.188336 TX Vref=24, minBit 9, minWin=27, winSum=451
1653 00:42:04.188420 TX Vref=26, minBit 8, minWin=27, winSum=453
1654 00:42:04.188503 TX Vref=28, minBit 8, minWin=27, winSum=457
1655 00:42:04.188620 TX Vref=30, minBit 15, minWin=27, winSum=458
1656 00:42:04.188676 TX Vref=32, minBit 8, minWin=27, winSum=456
1657 00:42:04.188728 [TxChooseVref] Worse bit 15, Min win 27, Win sum 458, Final Vref 30
1658 00:42:04.188783
1659 00:42:04.188842 Final TX Range 1 Vref 30
1660 00:42:04.188897
1661 00:42:04.188949 ==
1662 00:42:04.189001 Dram Type= 6, Freq= 0, CH_1, rank 0
1663 00:42:04.189061 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1664 00:42:04.189118 ==
1665 00:42:04.189169
1666 00:42:04.189221
1667 00:42:04.189272 TX Vref Scan disable
1668 00:42:04.189332 == TX Byte 0 ==
1669 00:42:04.189384 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1670 00:42:04.189439 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1671 00:42:04.189491 == TX Byte 1 ==
1672 00:42:04.189547 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1673 00:42:04.189605 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1674 00:42:04.189657
1675 00:42:04.189708 [DATLAT]
1676 00:42:04.189759 Freq=800, CH1 RK0
1677 00:42:04.189818
1678 00:42:04.189873 DATLAT Default: 0xa
1679 00:42:04.189927 0, 0xFFFF, sum = 0
1680 00:42:04.189981 1, 0xFFFF, sum = 0
1681 00:42:04.190037 2, 0xFFFF, sum = 0
1682 00:42:04.190094 3, 0xFFFF, sum = 0
1683 00:42:04.190147 4, 0xFFFF, sum = 0
1684 00:42:04.190199 5, 0xFFFF, sum = 0
1685 00:42:04.190252 6, 0xFFFF, sum = 0
1686 00:42:04.190312 7, 0xFFFF, sum = 0
1687 00:42:04.190369 8, 0xFFFF, sum = 0
1688 00:42:04.190425 9, 0x0, sum = 1
1689 00:42:04.190478 10, 0x0, sum = 2
1690 00:42:04.190531 11, 0x0, sum = 3
1691 00:42:04.190591 12, 0x0, sum = 4
1692 00:42:04.190644 best_step = 10
1693 00:42:04.190695
1694 00:42:04.190746 ==
1695 00:42:04.190803 Dram Type= 6, Freq= 0, CH_1, rank 0
1696 00:42:04.190860 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1697 00:42:04.190916 ==
1698 00:42:04.190968 RX Vref Scan: 1
1699 00:42:04.191019
1700 00:42:04.191080 Set Vref Range= 32 -> 127
1701 00:42:04.191133
1702 00:42:04.191183 RX Vref 32 -> 127, step: 1
1703 00:42:04.191235
1704 00:42:04.191291 RX Delay -95 -> 252, step: 8
1705 00:42:04.191349
1706 00:42:04.191403 Set Vref, RX VrefLevel [Byte0]: 32
1707 00:42:04.191455 [Byte1]: 32
1708 00:42:04.191506
1709 00:42:04.191564 Set Vref, RX VrefLevel [Byte0]: 33
1710 00:42:04.191620 [Byte1]: 33
1711 00:42:04.191672
1712 00:42:04.191724 Set Vref, RX VrefLevel [Byte0]: 34
1713 00:42:04.191776 [Byte1]: 34
1714 00:42:04.191837
1715 00:42:04.191891 Set Vref, RX VrefLevel [Byte0]: 35
1716 00:42:04.191943 [Byte1]: 35
1717 00:42:04.191994
1718 00:42:04.192051 Set Vref, RX VrefLevel [Byte0]: 36
1719 00:42:04.192107 [Byte1]: 36
1720 00:42:04.192177
1721 00:42:04.192261 Set Vref, RX VrefLevel [Byte0]: 37
1722 00:42:04.192348 [Byte1]: 37
1723 00:42:04.192430
1724 00:42:04.192512 Set Vref, RX VrefLevel [Byte0]: 38
1725 00:42:04.192625 [Byte1]: 38
1726 00:42:04.192680
1727 00:42:04.192731 Set Vref, RX VrefLevel [Byte0]: 39
1728 00:42:04.192787 [Byte1]: 39
1729 00:42:04.192844
1730 00:42:04.192898 Set Vref, RX VrefLevel [Byte0]: 40
1731 00:42:04.192951 [Byte1]: 40
1732 00:42:04.193002
1733 00:42:04.193062 Set Vref, RX VrefLevel [Byte0]: 41
1734 00:42:04.193119 [Byte1]: 41
1735 00:42:04.193171
1736 00:42:04.193222 Set Vref, RX VrefLevel [Byte0]: 42
1737 00:42:04.193274 [Byte1]: 42
1738 00:42:04.193333
1739 00:42:04.193387 Set Vref, RX VrefLevel [Byte0]: 43
1740 00:42:04.193440 [Byte1]: 43
1741 00:42:04.193492
1742 00:42:04.193549 Set Vref, RX VrefLevel [Byte0]: 44
1743 00:42:04.193606 [Byte1]: 44
1744 00:42:04.193659
1745 00:42:04.193710 Set Vref, RX VrefLevel [Byte0]: 45
1746 00:42:04.193762 [Byte1]: 45
1747 00:42:04.193820
1748 00:42:04.193876 Set Vref, RX VrefLevel [Byte0]: 46
1749 00:42:04.193929 [Byte1]: 46
1750 00:42:04.193981
1751 00:42:04.194036 Set Vref, RX VrefLevel [Byte0]: 47
1752 00:42:04.194092 [Byte1]: 47
1753 00:42:04.194145
1754 00:42:04.194197 Set Vref, RX VrefLevel [Byte0]: 48
1755 00:42:04.194248 [Byte1]: 48
1756 00:42:04.194306
1757 00:42:04.194362 Set Vref, RX VrefLevel [Byte0]: 49
1758 00:42:04.194417 [Byte1]: 49
1759 00:42:04.194469
1760 00:42:04.194520 Set Vref, RX VrefLevel [Byte0]: 50
1761 00:42:04.194581 [Byte1]: 50
1762 00:42:04.194633
1763 00:42:04.194684 Set Vref, RX VrefLevel [Byte0]: 51
1764 00:42:04.194736 [Byte1]: 51
1765 00:42:04.194792
1766 00:42:04.194848 Set Vref, RX VrefLevel [Byte0]: 52
1767 00:42:04.195108 [Byte1]: 52
1768 00:42:04.195170
1769 00:42:04.195223 Set Vref, RX VrefLevel [Byte0]: 53
1770 00:42:04.195275 [Byte1]: 53
1771 00:42:04.195354
1772 00:42:04.195409 Set Vref, RX VrefLevel [Byte0]: 54
1773 00:42:04.195463 [Byte1]: 54
1774 00:42:04.195516
1775 00:42:04.195579 Set Vref, RX VrefLevel [Byte0]: 55
1776 00:42:04.195647 [Byte1]: 55
1777 00:42:04.195698
1778 00:42:04.195750 Set Vref, RX VrefLevel [Byte0]: 56
1779 00:42:04.195809 [Byte1]: 56
1780 00:42:04.195866
1781 00:42:04.195921 Set Vref, RX VrefLevel [Byte0]: 57
1782 00:42:04.196008 [Byte1]: 57
1783 00:42:04.196095
1784 00:42:04.196177 Set Vref, RX VrefLevel [Byte0]: 58
1785 00:42:04.196259 [Byte1]: 58
1786 00:42:04.196345
1787 00:42:04.196428 Set Vref, RX VrefLevel [Byte0]: 59
1788 00:42:04.196512 [Byte1]: 59
1789 00:42:04.196649
1790 00:42:04.196731 Set Vref, RX VrefLevel [Byte0]: 60
1791 00:42:04.196818 [Byte1]: 60
1792 00:42:04.196900
1793 00:42:04.196972 Set Vref, RX VrefLevel [Byte0]: 61
1794 00:42:04.197026 [Byte1]: 61
1795 00:42:04.197078
1796 00:42:04.197130 Set Vref, RX VrefLevel [Byte0]: 62
1797 00:42:04.197194 [Byte1]: 62
1798 00:42:04.197248
1799 00:42:04.197305 Set Vref, RX VrefLevel [Byte0]: 63
1800 00:42:04.197363 [Byte1]: 63
1801 00:42:04.197416
1802 00:42:04.197467 Set Vref, RX VrefLevel [Byte0]: 64
1803 00:42:04.197520 [Byte1]: 64
1804 00:42:04.197581
1805 00:42:04.197634 Set Vref, RX VrefLevel [Byte0]: 65
1806 00:42:04.197685 [Byte1]: 65
1807 00:42:04.197736
1808 00:42:04.197790 Set Vref, RX VrefLevel [Byte0]: 66
1809 00:42:04.197850 [Byte1]: 66
1810 00:42:04.197905
1811 00:42:04.197957 Set Vref, RX VrefLevel [Byte0]: 67
1812 00:42:04.198009 [Byte1]: 67
1813 00:42:04.198068
1814 00:42:04.198124 Set Vref, RX VrefLevel [Byte0]: 68
1815 00:42:04.198175 [Byte1]: 68
1816 00:42:04.198227
1817 00:42:04.198280 Set Vref, RX VrefLevel [Byte0]: 69
1818 00:42:04.198339 [Byte1]: 69
1819 00:42:04.198391
1820 00:42:04.198443 Set Vref, RX VrefLevel [Byte0]: 70
1821 00:42:04.198494 [Byte1]: 70
1822 00:42:04.198551
1823 00:42:04.198607 Set Vref, RX VrefLevel [Byte0]: 71
1824 00:42:04.198659 [Byte1]: 71
1825 00:42:04.198711
1826 00:42:04.198761 Set Vref, RX VrefLevel [Byte0]: 72
1827 00:42:04.198820 [Byte1]: 72
1828 00:42:04.198875
1829 00:42:04.198926 Set Vref, RX VrefLevel [Byte0]: 73
1830 00:42:04.198978 [Byte1]: 73
1831 00:42:04.199030
1832 00:42:04.199088 Set Vref, RX VrefLevel [Byte0]: 74
1833 00:42:04.199140 [Byte1]: 74
1834 00:42:04.199192
1835 00:42:04.199243 Final RX Vref Byte 0 = 53 to rank0
1836 00:42:04.199301 Final RX Vref Byte 1 = 62 to rank0
1837 00:42:04.199358 Final RX Vref Byte 0 = 53 to rank1
1838 00:42:04.199410 Final RX Vref Byte 1 = 62 to rank1==
1839 00:42:04.199463 Dram Type= 6, Freq= 0, CH_1, rank 0
1840 00:42:04.199515 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1841 00:42:04.199575 ==
1842 00:42:04.199631 DQS Delay:
1843 00:42:04.199683 DQS0 = 0, DQS1 = 0
1844 00:42:04.199735 DQM Delay:
1845 00:42:04.199790 DQM0 = 92, DQM1 = 83
1846 00:42:04.199849 DQ Delay:
1847 00:42:04.199931 DQ0 =96, DQ1 =88, DQ2 =84, DQ3 =88
1848 00:42:04.200013 DQ4 =88, DQ5 =108, DQ6 =100, DQ7 =88
1849 00:42:04.200137 DQ8 =72, DQ9 =72, DQ10 =88, DQ11 =76
1850 00:42:04.200222 DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =88
1851 00:42:04.200305
1852 00:42:04.200389
1853 00:42:04.200472 [DQSOSCAuto] RK0, (LSB)MR18= 0x304e, (MSB)MR19= 0x606, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
1854 00:42:04.200579 CH1 RK0: MR19=606, MR18=304E
1855 00:42:04.200652 CH1_RK0: MR19=0x606, MR18=0x304E, DQSOSC=390, MR23=63, INC=97, DEC=64
1856 00:42:04.200706
1857 00:42:04.200758 ----->DramcWriteLeveling(PI) begin...
1858 00:42:04.200817 ==
1859 00:42:04.200875 Dram Type= 6, Freq= 0, CH_1, rank 1
1860 00:42:04.200928 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1861 00:42:04.200980 ==
1862 00:42:04.201036 Write leveling (Byte 0): 26 => 26
1863 00:42:04.201093 Write leveling (Byte 1): 30 => 30
1864 00:42:04.201146 DramcWriteLeveling(PI) end<-----
1865 00:42:04.201197
1866 00:42:04.201248 ==
1867 00:42:04.201305 Dram Type= 6, Freq= 0, CH_1, rank 1
1868 00:42:04.201362 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1869 00:42:04.201414 ==
1870 00:42:04.201467 [Gating] SW mode calibration
1871 00:42:04.201519 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1872 00:42:04.201581 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1873 00:42:04.201634 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1874 00:42:04.201687 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1875 00:42:04.201739 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1876 00:42:04.201795 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1877 00:42:04.201853 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1878 00:42:04.201905 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 00:42:04.201958 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 00:42:04.202010 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 00:42:04.202069 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 00:42:04.202125 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 00:42:04.202177 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 00:42:04.202229 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 00:42:04.202285 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 00:42:04.202341 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 00:42:04.202394 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 00:42:04.202446 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 00:42:04.202497 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 00:42:04.202553 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1891 00:42:04.202609 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 00:42:04.202662 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1893 00:42:04.202714 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1894 00:42:04.202765 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1895 00:42:04.202826 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1896 00:42:04.203078 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1897 00:42:04.203195 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1898 00:42:04.203249 0 9 4 | B1->B0 | 2626 2323 | 1 1 | (1 1) (1 1)
1899 00:42:04.203312 0 9 8 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 1)
1900 00:42:04.203370 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1901 00:42:04.203423 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1902 00:42:04.203477 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1903 00:42:04.203533 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1904 00:42:04.203593 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1905 00:42:04.203660 0 10 0 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
1906 00:42:04.203712 0 10 4 | B1->B0 | 2d2d 3030 | 0 0 | (1 0) (0 1)
1907 00:42:04.203764 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1908 00:42:04.203824 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1909 00:42:04.203880 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1910 00:42:04.203932 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1911 00:42:04.203983 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1912 00:42:04.204040 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1913 00:42:04.204096 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1914 00:42:04.204149 0 11 4 | B1->B0 | 3333 3030 | 0 0 | (0 0) (0 0)
1915 00:42:04.204246 0 11 8 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
1916 00:42:04.204335 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1917 00:42:04.204418 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1918 00:42:04.204500 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1919 00:42:04.204603 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1920 00:42:04.204671 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1921 00:42:04.204723 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1922 00:42:04.204776 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1923 00:42:04.204837 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1924 00:42:04.204891 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1925 00:42:04.204943 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1926 00:42:04.204994 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1927 00:42:04.205051 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1928 00:42:04.205108 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1929 00:42:04.205159 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1930 00:42:04.205211 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1931 00:42:04.205263 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1932 00:42:04.205324 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1933 00:42:04.205379 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1934 00:42:04.205431 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1935 00:42:04.205483 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1936 00:42:04.205540 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1937 00:42:04.205597 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1938 00:42:04.205649 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1939 00:42:04.205701 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1940 00:42:04.205752 Total UI for P1: 0, mck2ui 16
1941 00:42:04.205812 best dqsien dly found for B0: ( 0, 14, 6)
1942 00:42:04.205869 Total UI for P1: 0, mck2ui 16
1943 00:42:04.205922 best dqsien dly found for B1: ( 0, 14, 4)
1944 00:42:04.205974 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1945 00:42:04.206026 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1946 00:42:04.206086
1947 00:42:04.206140 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1948 00:42:04.206191 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1949 00:42:04.206244 [Gating] SW calibration Done
1950 00:42:04.206300 ==
1951 00:42:04.206357 Dram Type= 6, Freq= 0, CH_1, rank 1
1952 00:42:04.206410 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1953 00:42:04.206462 ==
1954 00:42:04.206513 RX Vref Scan: 0
1955 00:42:04.206574
1956 00:42:04.206628 RX Vref 0 -> 0, step: 1
1957 00:42:04.206680
1958 00:42:04.206731 RX Delay -130 -> 252, step: 16
1959 00:42:04.206788 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
1960 00:42:04.206844 iDelay=206, Bit 1, Center 85 (-18 ~ 189) 208
1961 00:42:04.206897 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1962 00:42:04.206949 iDelay=206, Bit 3, Center 93 (-18 ~ 205) 224
1963 00:42:04.207001 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1964 00:42:04.207060 iDelay=206, Bit 5, Center 101 (-2 ~ 205) 208
1965 00:42:04.207116 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1966 00:42:04.207168 iDelay=206, Bit 7, Center 85 (-18 ~ 189) 208
1967 00:42:04.207220 iDelay=206, Bit 8, Center 77 (-34 ~ 189) 224
1968 00:42:04.207271 iDelay=206, Bit 9, Center 77 (-34 ~ 189) 224
1969 00:42:04.207331 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1970 00:42:04.207385 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1971 00:42:04.207436 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
1972 00:42:04.207488 iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224
1973 00:42:04.207544 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1974 00:42:04.207601 iDelay=206, Bit 15, Center 93 (-18 ~ 205) 224
1975 00:42:04.207654 ==
1976 00:42:04.207706 Dram Type= 6, Freq= 0, CH_1, rank 1
1977 00:42:04.207758 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1978 00:42:04.207816 ==
1979 00:42:04.207872 DQS Delay:
1980 00:42:04.207924 DQS0 = 0, DQS1 = 0
1981 00:42:04.207975 DQM Delay:
1982 00:42:04.208027 DQM0 = 90, DQM1 = 85
1983 00:42:04.208087 DQ Delay:
1984 00:42:04.208139 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1985 00:42:04.208190 DQ4 =93, DQ5 =101, DQ6 =93, DQ7 =85
1986 00:42:04.380367 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =77
1987 00:42:04.380533 DQ12 =93, DQ13 =93, DQ14 =85, DQ15 =93
1988 00:42:04.380644
1989 00:42:04.380712
1990 00:42:04.380772 ==
1991 00:42:04.380830 Dram Type= 6, Freq= 0, CH_1, rank 1
1992 00:42:04.380887 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1993 00:42:04.380950 ==
1994 00:42:04.381008
1995 00:42:04.381061
1996 00:42:04.381115 TX Vref Scan disable
1997 00:42:04.381173 == TX Byte 0 ==
1998 00:42:04.381231 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1999 00:42:04.381287 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
2000 00:42:04.381340 == TX Byte 1 ==
2001 00:42:04.381601 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2002 00:42:04.381709 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2003 00:42:04.381765 ==
2004 00:42:04.381820 Dram Type= 6, Freq= 0, CH_1, rank 1
2005 00:42:04.381873 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2006 00:42:04.381931 ==
2007 00:42:04.381989 TX Vref=22, minBit 13, minWin=27, winSum=453
2008 00:42:04.382043 TX Vref=24, minBit 13, minWin=27, winSum=455
2009 00:42:04.382095 TX Vref=26, minBit 13, minWin=27, winSum=454
2010 00:42:04.382148 TX Vref=28, minBit 8, minWin=28, winSum=459
2011 00:42:04.382208 TX Vref=30, minBit 1, minWin=28, winSum=458
2012 00:42:04.382264 TX Vref=32, minBit 8, minWin=27, winSum=457
2013 00:42:04.382317 [TxChooseVref] Worse bit 8, Min win 28, Win sum 459, Final Vref 28
2014 00:42:04.382370
2015 00:42:04.382427 Final TX Range 1 Vref 28
2016 00:42:04.382484
2017 00:42:04.382536 ==
2018 00:42:04.382589 Dram Type= 6, Freq= 0, CH_1, rank 1
2019 00:42:04.382641 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2020 00:42:04.382702 ==
2021 00:42:04.382755
2022 00:42:04.382808
2023 00:42:04.382859 TX Vref Scan disable
2024 00:42:04.382915 == TX Byte 0 ==
2025 00:42:04.382971 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
2026 00:42:04.383025 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
2027 00:42:04.383077 == TX Byte 1 ==
2028 00:42:04.383128 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2029 00:42:04.383187 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2030 00:42:04.383245
2031 00:42:04.383300 [DATLAT]
2032 00:42:04.383352 Freq=800, CH1 RK1
2033 00:42:04.383406
2034 00:42:04.383465 DATLAT Default: 0xa
2035 00:42:04.383517 0, 0xFFFF, sum = 0
2036 00:42:04.383571 1, 0xFFFF, sum = 0
2037 00:42:04.383624 2, 0xFFFF, sum = 0
2038 00:42:04.383682 3, 0xFFFF, sum = 0
2039 00:42:04.383740 4, 0xFFFF, sum = 0
2040 00:42:04.383797 5, 0xFFFF, sum = 0
2041 00:42:04.383850 6, 0xFFFF, sum = 0
2042 00:42:04.383906 7, 0xFFFF, sum = 0
2043 00:42:04.383964 8, 0xFFFF, sum = 0
2044 00:42:04.384017 9, 0x0, sum = 1
2045 00:42:04.384070 10, 0x0, sum = 2
2046 00:42:04.384122 11, 0x0, sum = 3
2047 00:42:04.384180 12, 0x0, sum = 4
2048 00:42:04.384238 best_step = 10
2049 00:42:04.384294
2050 00:42:04.384346 ==
2051 00:42:04.384398 Dram Type= 6, Freq= 0, CH_1, rank 1
2052 00:42:04.384458 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2053 00:42:04.384525 ==
2054 00:42:04.384648 RX Vref Scan: 0
2055 00:42:04.384714
2056 00:42:04.384797 RX Vref 0 -> 0, step: 1
2057 00:42:04.384879
2058 00:42:04.384950 RX Delay -79 -> 252, step: 8
2059 00:42:04.385007 iDelay=209, Bit 0, Center 96 (-7 ~ 200) 208
2060 00:42:04.385060 iDelay=209, Bit 1, Center 88 (-15 ~ 192) 208
2061 00:42:04.385113 iDelay=209, Bit 2, Center 80 (-23 ~ 184) 208
2062 00:42:04.385169 iDelay=209, Bit 3, Center 88 (-15 ~ 192) 208
2063 00:42:04.385227 iDelay=209, Bit 4, Center 96 (-7 ~ 200) 208
2064 00:42:04.385282 iDelay=209, Bit 5, Center 108 (9 ~ 208) 200
2065 00:42:04.385335 iDelay=209, Bit 6, Center 96 (-7 ~ 200) 208
2066 00:42:04.385387 iDelay=209, Bit 7, Center 88 (-15 ~ 192) 208
2067 00:42:04.385447 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
2068 00:42:04.385502 iDelay=209, Bit 9, Center 76 (-31 ~ 184) 216
2069 00:42:04.385555 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
2070 00:42:04.385607 iDelay=209, Bit 11, Center 80 (-31 ~ 192) 224
2071 00:42:04.385696 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
2072 00:42:04.385781 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
2073 00:42:04.385863 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2074 00:42:04.385948 iDelay=209, Bit 15, Center 92 (-15 ~ 200) 216
2075 00:42:04.386030 ==
2076 00:42:04.386112 Dram Type= 6, Freq= 0, CH_1, rank 1
2077 00:42:04.386189 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2078 00:42:04.386247 ==
2079 00:42:04.386303 DQS Delay:
2080 00:42:04.386357 DQS0 = 0, DQS1 = 0
2081 00:42:04.386413 DQM Delay:
2082 00:42:04.386498 DQM0 = 92, DQM1 = 83
2083 00:42:04.386581 DQ Delay:
2084 00:42:04.386664 DQ0 =96, DQ1 =88, DQ2 =80, DQ3 =88
2085 00:42:04.386729 DQ4 =96, DQ5 =108, DQ6 =96, DQ7 =88
2086 00:42:04.386813 DQ8 =68, DQ9 =76, DQ10 =84, DQ11 =80
2087 00:42:04.386896 DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =92
2088 00:42:04.386983
2089 00:42:04.387065
2090 00:42:04.387170 [DQSOSCAuto] RK1, (LSB)MR18= 0x3d12, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 394 ps
2091 00:42:04.387265 CH1 RK1: MR19=606, MR18=3D12
2092 00:42:04.387364 CH1_RK1: MR19=0x606, MR18=0x3D12, DQSOSC=394, MR23=63, INC=95, DEC=63
2093 00:42:04.387453 [RxdqsGatingPostProcess] freq 800
2094 00:42:04.387538 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2095 00:42:04.387621 Pre-setting of DQS Precalculation
2096 00:42:04.387717 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2097 00:42:04.387805 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2098 00:42:04.387890 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2099 00:42:04.387984
2100 00:42:04.388067
2101 00:42:04.388149 [Calibration Summary] 1600 Mbps
2102 00:42:04.388244 CH 0, Rank 0
2103 00:42:04.388328 SW Impedance : PASS
2104 00:42:04.388414 DUTY Scan : NO K
2105 00:42:04.388505 ZQ Calibration : PASS
2106 00:42:04.388620 Jitter Meter : NO K
2107 00:42:04.388701 CBT Training : PASS
2108 00:42:04.388788 Write leveling : PASS
2109 00:42:04.388871 RX DQS gating : PASS
2110 00:42:04.388962 RX DQ/DQS(RDDQC) : PASS
2111 00:42:04.389047 TX DQ/DQS : PASS
2112 00:42:04.389130 RX DATLAT : PASS
2113 00:42:04.389216 RX DQ/DQS(Engine): PASS
2114 00:42:04.389291 TX OE : NO K
2115 00:42:04.389347 All Pass.
2116 00:42:04.389401
2117 00:42:04.389475 CH 0, Rank 1
2118 00:42:04.389530 SW Impedance : PASS
2119 00:42:04.389583 DUTY Scan : NO K
2120 00:42:04.389636 ZQ Calibration : PASS
2121 00:42:04.389711 Jitter Meter : NO K
2122 00:42:04.389810 CBT Training : PASS
2123 00:42:04.389864 Write leveling : PASS
2124 00:42:04.389928 RX DQS gating : PASS
2125 00:42:04.389990 RX DQ/DQS(RDDQC) : PASS
2126 00:42:04.390044 TX DQ/DQS : PASS
2127 00:42:04.390097 RX DATLAT : PASS
2128 00:42:04.390150 RX DQ/DQS(Engine): PASS
2129 00:42:04.390225 TX OE : NO K
2130 00:42:04.390282 All Pass.
2131 00:42:04.390336
2132 00:42:04.390389 CH 1, Rank 0
2133 00:42:04.390464 SW Impedance : PASS
2134 00:42:04.390520 DUTY Scan : NO K
2135 00:42:04.390574 ZQ Calibration : PASS
2136 00:42:04.390627 Jitter Meter : NO K
2137 00:42:04.390699 CBT Training : PASS
2138 00:42:04.390757 Write leveling : PASS
2139 00:42:04.390813 RX DQS gating : PASS
2140 00:42:04.390866 RX DQ/DQS(RDDQC) : PASS
2141 00:42:04.390933 TX DQ/DQS : PASS
2142 00:42:04.391020 RX DATLAT : PASS
2143 00:42:04.391103 RX DQ/DQS(Engine): PASS
2144 00:42:04.391193 TX OE : NO K
2145 00:42:04.391280 All Pass.
2146 00:42:04.391363
2147 00:42:04.391454 CH 1, Rank 1
2148 00:42:04.391539 SW Impedance : PASS
2149 00:42:04.391621 DUTY Scan : NO K
2150 00:42:04.391714 ZQ Calibration : PASS
2151 00:42:04.392059 Jitter Meter : NO K
2152 00:42:04.392151 CBT Training : PASS
2153 00:42:04.392296 Write leveling : PASS
2154 00:42:04.392382 RX DQS gating : PASS
2155 00:42:04.392483 RX DQ/DQS(RDDQC) : PASS
2156 00:42:04.392594 TX DQ/DQS : PASS
2157 00:42:04.392733 RX DATLAT : PASS
2158 00:42:04.392851 RX DQ/DQS(Engine): PASS
2159 00:42:04.392973 TX OE : NO K
2160 00:42:04.393061 All Pass.
2161 00:42:04.393145
2162 00:42:04.393241 DramC Write-DBI off
2163 00:42:04.393340 PER_BANK_REFRESH: Hybrid Mode
2164 00:42:04.393430 TX_TRACKING: ON
2165 00:42:04.393518 [GetDramInforAfterCalByMRR] Vendor 6.
2166 00:42:04.393601 [GetDramInforAfterCalByMRR] Revision 606.
2167 00:42:04.393692 [GetDramInforAfterCalByMRR] Revision 2 0.
2168 00:42:04.393779 MR0 0x3b3b
2169 00:42:04.393861 MR8 0x5151
2170 00:42:04.393953 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2171 00:42:04.394037
2172 00:42:04.394119 MR0 0x3b3b
2173 00:42:04.394211 MR8 0x5151
2174 00:42:04.394296 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2175 00:42:04.394378
2176 00:42:04.394472 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2177 00:42:04.394557 [FAST_K] Save calibration result to emmc
2178 00:42:04.394671 [FAST_K] Save calibration result to emmc
2179 00:42:04.394760 dram_init: config_dvfs: 1
2180 00:42:04.394845 dramc_set_vcore_voltage set vcore to 662500
2181 00:42:04.394935 Read voltage for 1200, 2
2182 00:42:04.395020 Vio18 = 0
2183 00:42:04.395102 Vcore = 662500
2184 00:42:04.395192 Vdram = 0
2185 00:42:04.395278 Vddq = 0
2186 00:42:04.395360 Vmddr = 0
2187 00:42:04.395452 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2188 00:42:04.395538 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2189 00:42:04.395621 MEM_TYPE=3, freq_sel=15
2190 00:42:04.395715 sv_algorithm_assistance_LP4_1600
2191 00:42:04.395800 ============ PULL DRAM RESETB DOWN ============
2192 00:42:04.395884 ========== PULL DRAM RESETB DOWN end =========
2193 00:42:04.395979 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2194 00:42:04.396063 ===================================
2195 00:42:04.396146 LPDDR4 DRAM CONFIGURATION
2196 00:42:04.396240 ===================================
2197 00:42:04.396325 EX_ROW_EN[0] = 0x0
2198 00:42:04.396410 EX_ROW_EN[1] = 0x0
2199 00:42:04.396501 LP4Y_EN = 0x0
2200 00:42:04.396609 WORK_FSP = 0x0
2201 00:42:04.396676 WL = 0x4
2202 00:42:04.396746 RL = 0x4
2203 00:42:04.396830 BL = 0x2
2204 00:42:04.396913 RPST = 0x0
2205 00:42:04.397007 RD_PRE = 0x0
2206 00:42:04.397089 WR_PRE = 0x1
2207 00:42:04.397179 WR_PST = 0x0
2208 00:42:04.397267 DBI_WR = 0x0
2209 00:42:04.397349 DBI_RD = 0x0
2210 00:42:04.397440 OTF = 0x1
2211 00:42:04.397526 ===================================
2212 00:42:04.397610 ===================================
2213 00:42:04.397703 ANA top config
2214 00:42:04.397789 ===================================
2215 00:42:04.397872 DLL_ASYNC_EN = 0
2216 00:42:04.397965 ALL_SLAVE_EN = 0
2217 00:42:04.398049 NEW_RANK_MODE = 1
2218 00:42:04.398132 DLL_IDLE_MODE = 1
2219 00:42:04.398226 LP45_APHY_COMB_EN = 1
2220 00:42:04.398311 TX_ODT_DIS = 1
2221 00:42:04.398394 NEW_8X_MODE = 1
2222 00:42:04.398489 ===================================
2223 00:42:04.398573 ===================================
2224 00:42:04.398657 data_rate = 2400
2225 00:42:04.398750 CKR = 1
2226 00:42:04.398835 DQ_P2S_RATIO = 8
2227 00:42:04.398924 ===================================
2228 00:42:04.399012 CA_P2S_RATIO = 8
2229 00:42:04.399095 DQ_CA_OPEN = 0
2230 00:42:04.399185 DQ_SEMI_OPEN = 0
2231 00:42:04.399273 CA_SEMI_OPEN = 0
2232 00:42:04.399356 CA_FULL_RATE = 0
2233 00:42:04.399448 DQ_CKDIV4_EN = 0
2234 00:42:04.399533 CA_CKDIV4_EN = 0
2235 00:42:04.399615 CA_PREDIV_EN = 0
2236 00:42:04.399708 PH8_DLY = 17
2237 00:42:04.399793 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2238 00:42:04.399876 DQ_AAMCK_DIV = 4
2239 00:42:04.399970 CA_AAMCK_DIV = 4
2240 00:42:04.400053 CA_ADMCK_DIV = 4
2241 00:42:04.400136 DQ_TRACK_CA_EN = 0
2242 00:42:04.400228 CA_PICK = 1200
2243 00:42:04.400314 CA_MCKIO = 1200
2244 00:42:04.400396 MCKIO_SEMI = 0
2245 00:42:04.400491 PLL_FREQ = 2366
2246 00:42:04.400607 DQ_UI_PI_RATIO = 32
2247 00:42:04.400670 CA_UI_PI_RATIO = 0
2248 00:42:04.400737 ===================================
2249 00:42:04.400814 ===================================
2250 00:42:04.400897 memory_type:LPDDR4
2251 00:42:04.400976 GP_NUM : 10
2252 00:42:04.401032 SRAM_EN : 1
2253 00:42:04.401086 MD32_EN : 0
2254 00:42:04.401139 ===================================
2255 00:42:04.401215 [ANA_INIT] >>>>>>>>>>>>>>
2256 00:42:04.401277 <<<<<< [CONFIGURE PHASE]: ANA_TX
2257 00:42:04.401361 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2258 00:42:04.401451 ===================================
2259 00:42:04.401509 data_rate = 2400,PCW = 0X5b00
2260 00:42:04.401562 ===================================
2261 00:42:04.401616 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2262 00:42:04.401682 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2263 00:42:04.401743 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2264 00:42:04.401800 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2265 00:42:04.401854 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2266 00:42:04.401912 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2267 00:42:04.401981 [ANA_INIT] flow start
2268 00:42:04.402035 [ANA_INIT] PLL >>>>>>>>
2269 00:42:04.402088 [ANA_INIT] PLL <<<<<<<<
2270 00:42:04.402142 [ANA_INIT] MIDPI >>>>>>>>
2271 00:42:04.402217 [ANA_INIT] MIDPI <<<<<<<<
2272 00:42:04.402275 [ANA_INIT] DLL >>>>>>>>
2273 00:42:04.402329 [ANA_INIT] DLL <<<<<<<<
2274 00:42:04.402383 [ANA_INIT] flow end
2275 00:42:04.402457 ============ LP4 DIFF to SE enter ============
2276 00:42:04.402515 ============ LP4 DIFF to SE exit ============
2277 00:42:04.402569 [ANA_INIT] <<<<<<<<<<<<<
2278 00:42:04.402623 [Flow] Enable top DCM control >>>>>
2279 00:42:04.402689 [Flow] Enable top DCM control <<<<<
2280 00:42:04.402749 Enable DLL master slave shuffle
2281 00:42:04.402805 ==============================================================
2282 00:42:04.402860 Gating Mode config
2283 00:42:04.403125 ==============================================================
2284 00:42:04.403216 Config description:
2285 00:42:04.403280 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2286 00:42:04.403367 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2287 00:42:04.403464 SELPH_MODE 0: By rank 1: By Phase
2288 00:42:04.403550 ==============================================================
2289 00:42:04.403634 GAT_TRACK_EN = 1
2290 00:42:04.403729 RX_GATING_MODE = 2
2291 00:42:04.403815 RX_GATING_TRACK_MODE = 2
2292 00:42:04.403898 SELPH_MODE = 1
2293 00:42:04.403992 PICG_EARLY_EN = 1
2294 00:42:04.404076 VALID_LAT_VALUE = 1
2295 00:42:04.404162 ==============================================================
2296 00:42:04.404255 Enter into Gating configuration >>>>
2297 00:42:04.404340 Exit from Gating configuration <<<<
2298 00:42:04.404431 Enter into DVFS_PRE_config >>>>>
2299 00:42:04.404520 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2300 00:42:04.404637 Exit from DVFS_PRE_config <<<<<
2301 00:42:04.404714 Enter into PICG configuration >>>>
2302 00:42:04.404775 Exit from PICG configuration <<<<
2303 00:42:04.404858 [RX_INPUT] configuration >>>>>
2304 00:42:04.404947 [RX_INPUT] configuration <<<<<
2305 00:42:04.405007 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2306 00:42:04.405062 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2307 00:42:04.405116 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2308 00:42:04.405182 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2309 00:42:04.405244 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2310 00:42:04.405318 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2311 00:42:04.405401 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2312 00:42:04.405477 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2313 00:42:04.405533 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2314 00:42:04.405587 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2315 00:42:04.405641 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2316 00:42:04.405717 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2317 00:42:04.405774 ===================================
2318 00:42:04.405829 LPDDR4 DRAM CONFIGURATION
2319 00:42:04.405883 ===================================
2320 00:42:04.405958 EX_ROW_EN[0] = 0x0
2321 00:42:04.406014 EX_ROW_EN[1] = 0x0
2322 00:42:04.406067 LP4Y_EN = 0x0
2323 00:42:04.406121 WORK_FSP = 0x0
2324 00:42:04.406187 WL = 0x4
2325 00:42:04.406246 RL = 0x4
2326 00:42:04.406303 BL = 0x2
2327 00:42:04.406357 RPST = 0x0
2328 00:42:04.406416 RD_PRE = 0x0
2329 00:42:04.406482 WR_PRE = 0x1
2330 00:42:04.406536 WR_PST = 0x0
2331 00:42:04.406589 DBI_WR = 0x0
2332 00:42:04.406641 DBI_RD = 0x0
2333 00:42:04.406717 OTF = 0x1
2334 00:42:04.406775 ===================================
2335 00:42:04.406829 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2336 00:42:04.406884 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2337 00:42:04.406959 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2338 00:42:04.407015 ===================================
2339 00:42:04.407069 LPDDR4 DRAM CONFIGURATION
2340 00:42:04.407122 ===================================
2341 00:42:04.407190 EX_ROW_EN[0] = 0x10
2342 00:42:04.407249 EX_ROW_EN[1] = 0x0
2343 00:42:04.407330 LP4Y_EN = 0x0
2344 00:42:04.407416 WORK_FSP = 0x0
2345 00:42:04.407506 WL = 0x4
2346 00:42:04.407589 RL = 0x4
2347 00:42:04.407678 BL = 0x2
2348 00:42:04.407767 RPST = 0x0
2349 00:42:04.407849 RD_PRE = 0x0
2350 00:42:04.407940 WR_PRE = 0x1
2351 00:42:04.408026 WR_PST = 0x0
2352 00:42:04.408108 DBI_WR = 0x0
2353 00:42:04.408199 DBI_RD = 0x0
2354 00:42:04.408285 OTF = 0x1
2355 00:42:04.408369 ===================================
2356 00:42:04.408464 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2357 00:42:04.408568 ==
2358 00:42:04.408640 Dram Type= 6, Freq= 0, CH_0, rank 0
2359 00:42:04.408718 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2360 00:42:04.408780 ==
2361 00:42:04.408862 [Duty_Offset_Calibration]
2362 00:42:04.408950 B0:2 B1:0 CA:1
2363 00:42:04.409009
2364 00:42:04.409061 [DutyScan_Calibration_Flow] k_type=0
2365 00:42:04.409113
2366 00:42:04.409174 ==CLK 0==
2367 00:42:04.409236 Final CLK duty delay cell = -4
2368 00:42:04.409304 [-4] MAX Duty = 5031%(X100), DQS PI = 24
2369 00:42:04.409386 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2370 00:42:04.409465 [-4] AVG Duty = 4953%(X100)
2371 00:42:04.409520
2372 00:42:04.409572 CH0 CLK Duty spec in!! Max-Min= 156%
2373 00:42:04.409624 [DutyScan_Calibration_Flow] ====Done====
2374 00:42:04.409690
2375 00:42:04.409747 [DutyScan_Calibration_Flow] k_type=1
2376 00:42:04.409803
2377 00:42:04.409855 ==DQS 0 ==
2378 00:42:04.409909 Final DQS duty delay cell = 0
2379 00:42:04.409978 [0] MAX Duty = 5187%(X100), DQS PI = 32
2380 00:42:04.410032 [0] MIN Duty = 4938%(X100), DQS PI = 0
2381 00:42:04.410084 [0] AVG Duty = 5062%(X100)
2382 00:42:04.410136
2383 00:42:04.410209 ==DQS 1 ==
2384 00:42:04.410265 Final DQS duty delay cell = -4
2385 00:42:04.410318 [-4] MAX Duty = 5124%(X100), DQS PI = 32
2386 00:42:04.410371 [-4] MIN Duty = 4907%(X100), DQS PI = 8
2387 00:42:04.410436 [-4] AVG Duty = 5015%(X100)
2388 00:42:04.410494
2389 00:42:04.410545 CH0 DQS 0 Duty spec in!! Max-Min= 249%
2390 00:42:04.410597
2391 00:42:04.410649 CH0 DQS 1 Duty spec in!! Max-Min= 217%
2392 00:42:04.410721 [DutyScan_Calibration_Flow] ====Done====
2393 00:42:04.410776
2394 00:42:04.410828 [DutyScan_Calibration_Flow] k_type=3
2395 00:42:04.410919
2396 00:42:04.410982 ==DQM 0 ==
2397 00:42:04.411035 Final DQM duty delay cell = 0
2398 00:42:04.411087 [0] MAX Duty = 5062%(X100), DQS PI = 24
2399 00:42:04.411139 [0] MIN Duty = 4813%(X100), DQS PI = 0
2400 00:42:04.411213 [0] AVG Duty = 4937%(X100)
2401 00:42:04.411270
2402 00:42:04.411351 ==DQM 1 ==
2403 00:42:04.411441 Final DQM duty delay cell = 0
2404 00:42:04.411528 [0] MAX Duty = 5187%(X100), DQS PI = 46
2405 00:42:04.411610 [0] MIN Duty = 5000%(X100), DQS PI = 12
2406 00:42:04.411701 [0] AVG Duty = 5093%(X100)
2407 00:42:04.411785
2408 00:42:04.412073 CH0 DQM 0 Duty spec in!! Max-Min= 249%
2409 00:42:04.412169
2410 00:42:04.412259 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2411 00:42:04.412343 [DutyScan_Calibration_Flow] ====Done====
2412 00:42:04.412433
2413 00:42:04.412519 [DutyScan_Calibration_Flow] k_type=2
2414 00:42:04.412622
2415 00:42:04.412690 ==DQ 0 ==
2416 00:42:04.412749 Final DQ duty delay cell = 0
2417 00:42:04.412831 [0] MAX Duty = 5156%(X100), DQS PI = 34
2418 00:42:04.412950 [0] MIN Duty = 5000%(X100), DQS PI = 0
2419 00:42:04.413009 [0] AVG Duty = 5078%(X100)
2420 00:42:04.413062
2421 00:42:04.413114 ==DQ 1 ==
2422 00:42:04.413177 Final DQ duty delay cell = 4
2423 00:42:04.413238 [4] MAX Duty = 5093%(X100), DQS PI = 4
2424 00:42:04.413309 [4] MIN Duty = 5000%(X100), DQS PI = 16
2425 00:42:04.413391 [4] AVG Duty = 5046%(X100)
2426 00:42:04.413468
2427 00:42:04.413522 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2428 00:42:04.413575
2429 00:42:04.413626 CH0 DQ 1 Duty spec in!! Max-Min= 93%
2430 00:42:04.413696 [DutyScan_Calibration_Flow] ====Done====
2431 00:42:04.413753 ==
2432 00:42:04.413816 Dram Type= 6, Freq= 0, CH_1, rank 0
2433 00:42:04.413904 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2434 00:42:04.413998 ==
2435 00:42:04.414081 [Duty_Offset_Calibration]
2436 00:42:04.414162 B0:0 B1:-1 CA:2
2437 00:42:04.414248
2438 00:42:04.414330 [DutyScan_Calibration_Flow] k_type=0
2439 00:42:04.414415
2440 00:42:04.414495 ==CLK 0==
2441 00:42:04.414574 Final CLK duty delay cell = 0
2442 00:42:04.414629 [0] MAX Duty = 5156%(X100), DQS PI = 10
2443 00:42:04.414682 [0] MIN Duty = 4938%(X100), DQS PI = 44
2444 00:42:04.414736 [0] AVG Duty = 5047%(X100)
2445 00:42:04.414788
2446 00:42:04.414840 CH1 CLK Duty spec in!! Max-Min= 218%
2447 00:42:04.414894 [DutyScan_Calibration_Flow] ====Done====
2448 00:42:04.414970
2449 00:42:04.415024 [DutyScan_Calibration_Flow] k_type=1
2450 00:42:04.415076
2451 00:42:04.415158 ==DQS 0 ==
2452 00:42:04.415240 Final DQS duty delay cell = 0
2453 00:42:04.415324 [0] MAX Duty = 5093%(X100), DQS PI = 24
2454 00:42:04.415406 [0] MIN Duty = 4969%(X100), DQS PI = 0
2455 00:42:04.415497 [0] AVG Duty = 5031%(X100)
2456 00:42:04.415580
2457 00:42:04.415669 ==DQS 1 ==
2458 00:42:04.415753 Final DQS duty delay cell = 0
2459 00:42:04.415836 [0] MAX Duty = 5156%(X100), DQS PI = 0
2460 00:42:04.415923 [0] MIN Duty = 4844%(X100), DQS PI = 36
2461 00:42:04.416013 [0] AVG Duty = 5000%(X100)
2462 00:42:04.416094
2463 00:42:04.416183 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2464 00:42:04.416269
2465 00:42:04.416351 CH1 DQS 1 Duty spec in!! Max-Min= 312%
2466 00:42:04.416441 [DutyScan_Calibration_Flow] ====Done====
2467 00:42:04.416525
2468 00:42:04.416628 [DutyScan_Calibration_Flow] k_type=3
2469 00:42:04.416700
2470 00:42:04.416805 ==DQM 0 ==
2471 00:42:04.416902 Final DQM duty delay cell = 4
2472 00:42:04.416976 [4] MAX Duty = 5093%(X100), DQS PI = 22
2473 00:42:04.417030 [4] MIN Duty = 4938%(X100), DQS PI = 44
2474 00:42:04.417083 [4] AVG Duty = 5015%(X100)
2475 00:42:04.417135
2476 00:42:04.417207 ==DQM 1 ==
2477 00:42:04.417264 Final DQM duty delay cell = -4
2478 00:42:04.417347 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2479 00:42:04.417436 [-4] MIN Duty = 4751%(X100), DQS PI = 36
2480 00:42:04.417495 [-4] AVG Duty = 4875%(X100)
2481 00:42:04.417548
2482 00:42:04.417600 CH1 DQM 0 Duty spec in!! Max-Min= 155%
2483 00:42:04.417653
2484 00:42:04.417725 CH1 DQM 1 Duty spec in!! Max-Min= 249%
2485 00:42:04.417780 [DutyScan_Calibration_Flow] ====Done====
2486 00:42:04.417833
2487 00:42:04.417885 [DutyScan_Calibration_Flow] k_type=2
2488 00:42:04.417957
2489 00:42:04.418012 ==DQ 0 ==
2490 00:42:04.418065 Final DQ duty delay cell = 0
2491 00:42:04.418118 [0] MAX Duty = 5062%(X100), DQS PI = 20
2492 00:42:04.418184 [0] MIN Duty = 4938%(X100), DQS PI = 0
2493 00:42:04.418242 [0] AVG Duty = 5000%(X100)
2494 00:42:04.418297
2495 00:42:04.418349 ==DQ 1 ==
2496 00:42:04.418401 Final DQ duty delay cell = 0
2497 00:42:04.418474 [0] MAX Duty = 5031%(X100), DQS PI = 0
2498 00:42:04.418527 [0] MIN Duty = 4813%(X100), DQS PI = 36
2499 00:42:04.418579 [0] AVG Duty = 4922%(X100)
2500 00:42:04.418632
2501 00:42:04.418703 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2502 00:42:04.418758
2503 00:42:04.418841 CH1 DQ 1 Duty spec in!! Max-Min= 218%
2504 00:42:04.418929 [DutyScan_Calibration_Flow] ====Done====
2505 00:42:04.419015 nWR fixed to 30
2506 00:42:04.419098 [ModeRegInit_LP4] CH0 RK0
2507 00:42:04.419187 [ModeRegInit_LP4] CH0 RK1
2508 00:42:04.419273 [ModeRegInit_LP4] CH1 RK0
2509 00:42:04.419355 [ModeRegInit_LP4] CH1 RK1
2510 00:42:04.419445 match AC timing 7
2511 00:42:04.419530 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2512 00:42:04.419612 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2513 00:42:04.419704 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2514 00:42:04.419789 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2515 00:42:04.419871 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2516 00:42:04.419963 ==
2517 00:42:04.420046 Dram Type= 6, Freq= 0, CH_0, rank 0
2518 00:42:04.420128 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2519 00:42:04.420220 ==
2520 00:42:04.420305 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2521 00:42:04.420388 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2522 00:42:04.420480 [CA 0] Center 38 (8~69) winsize 62
2523 00:42:04.420589 [CA 1] Center 38 (7~69) winsize 63
2524 00:42:04.420662 [CA 2] Center 35 (5~66) winsize 62
2525 00:42:04.420730 [CA 3] Center 35 (4~66) winsize 63
2526 00:42:04.420792 [CA 4] Center 34 (4~65) winsize 62
2527 00:42:04.420873 [CA 5] Center 33 (3~63) winsize 61
2528 00:42:04.420957
2529 00:42:04.421011 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2530 00:42:04.421065
2531 00:42:04.421117 [CATrainingPosCal] consider 1 rank data
2532 00:42:04.421182 u2DelayCellTimex100 = 270/100 ps
2533 00:42:04.421241 CA0 delay=38 (8~69),Diff = 5 PI (24 cell)
2534 00:42:04.421314 CA1 delay=38 (7~69),Diff = 5 PI (24 cell)
2535 00:42:04.421396 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2536 00:42:04.421472 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2537 00:42:04.421526 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2538 00:42:04.421579 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2539 00:42:04.421631
2540 00:42:04.421702 CA PerBit enable=1, Macro0, CA PI delay=33
2541 00:42:04.421758
2542 00:42:04.421812 [CBTSetCACLKResult] CA Dly = 33
2543 00:42:04.421865 CS Dly: 6 (0~37)
2544 00:42:04.421922 ==
2545 00:42:04.421987 Dram Type= 6, Freq= 0, CH_0, rank 1
2546 00:42:04.422040 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2547 00:42:04.422093 ==
2548 00:42:04.422145 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2549 00:42:04.422218 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2550 00:42:04.422275 [CA 0] Center 39 (8~70) winsize 63
2551 00:42:04.422328 [CA 1] Center 38 (8~69) winsize 62
2552 00:42:04.422380 [CA 2] Center 35 (5~66) winsize 62
2553 00:42:04.422668 [CA 3] Center 35 (4~66) winsize 63
2554 00:42:04.422766 [CA 4] Center 34 (4~65) winsize 62
2555 00:42:04.422850 [CA 5] Center 34 (4~64) winsize 61
2556 00:42:04.422940
2557 00:42:04.423026 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2558 00:42:04.423107
2559 00:42:04.423198 [CATrainingPosCal] consider 2 rank data
2560 00:42:04.423283 u2DelayCellTimex100 = 270/100 ps
2561 00:42:04.423365 CA0 delay=38 (8~69),Diff = 5 PI (24 cell)
2562 00:42:04.423458 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2563 00:42:04.423541 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2564 00:42:04.423623 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2565 00:42:04.423714 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2566 00:42:04.423799 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
2567 00:42:04.423880
2568 00:42:04.423971 CA PerBit enable=1, Macro0, CA PI delay=33
2569 00:42:04.424054
2570 00:42:04.424135 [CBTSetCACLKResult] CA Dly = 33
2571 00:42:04.424226 CS Dly: 7 (0~39)
2572 00:42:04.424310
2573 00:42:04.424391 ----->DramcWriteLeveling(PI) begin...
2574 00:42:04.424484 ==
2575 00:42:04.424600 Dram Type= 6, Freq= 0, CH_0, rank 0
2576 00:42:04.424682 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2577 00:42:04.424742 ==
2578 00:42:04.424816 Write leveling (Byte 0): 34 => 34
2579 00:42:04.424898 Write leveling (Byte 1): 31 => 31
2580 00:42:04.424990 DramcWriteLeveling(PI) end<-----
2581 00:42:04.425072
2582 00:42:04.425153 ==
2583 00:42:04.425224 Dram Type= 6, Freq= 0, CH_0, rank 0
2584 00:42:04.425284 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2585 00:42:04.425366 ==
2586 00:42:04.425448 [Gating] SW mode calibration
2587 00:42:04.425505 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2588 00:42:04.425559 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2589 00:42:04.425611 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2590 00:42:04.425673 0 15 4 | B1->B0 | 2c2c 3434 | 0 1 | (1 1) (1 1)
2591 00:42:04.425735 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2592 00:42:04.425791 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2593 00:42:04.425844 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2594 00:42:04.425896 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2595 00:42:04.425969 0 15 24 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
2596 00:42:04.426023 0 15 28 | B1->B0 | 3434 2424 | 1 0 | (1 1) (1 0)
2597 00:42:04.426076 1 0 0 | B1->B0 | 2c2c 2323 | 0 0 | (0 1) (0 0)
2598 00:42:04.426129 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2599 00:42:04.426201 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2600 00:42:04.426256 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2601 00:42:04.426311 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2602 00:42:04.426363 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2603 00:42:04.426428 1 0 24 | B1->B0 | 2323 3535 | 0 1 | (0 0) (1 1)
2604 00:42:04.426486 1 0 28 | B1->B0 | 2828 4646 | 1 0 | (0 0) (0 0)
2605 00:42:04.426538 1 1 0 | B1->B0 | 3b3b 4646 | 0 0 | (1 1) (0 0)
2606 00:42:04.426591 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2607 00:42:04.426643 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2608 00:42:04.426716 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2609 00:42:04.426773 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2610 00:42:04.426826 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2611 00:42:04.426878 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2612 00:42:04.426950 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2613 00:42:04.427005 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2614 00:42:04.427057 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2615 00:42:04.427109 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2616 00:42:04.427172 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2617 00:42:04.427256 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2618 00:42:04.427338 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2619 00:42:04.427428 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2620 00:42:04.427514 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2621 00:42:04.427596 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2622 00:42:04.427686 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2623 00:42:04.427771 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2624 00:42:04.427854 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2625 00:42:04.427944 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2626 00:42:04.428029 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2627 00:42:04.428111 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2628 00:42:04.428204 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2629 00:42:04.428288 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2630 00:42:04.428370 Total UI for P1: 0, mck2ui 16
2631 00:42:04.428463 best dqsien dly found for B0: ( 1, 3, 28)
2632 00:42:04.428551 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2633 00:42:04.428645 Total UI for P1: 0, mck2ui 16
2634 00:42:04.428720 best dqsien dly found for B1: ( 1, 3, 30)
2635 00:42:04.428780 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2636 00:42:04.428862 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2637 00:42:04.428949
2638 00:42:04.429005 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2639 00:42:04.429058 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2640 00:42:04.429111 [Gating] SW calibration Done
2641 00:42:04.429172 ==
2642 00:42:04.429235 Dram Type= 6, Freq= 0, CH_0, rank 0
2643 00:42:04.429302 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2644 00:42:04.429384 ==
2645 00:42:04.429464 RX Vref Scan: 0
2646 00:42:04.429519
2647 00:42:04.429572 RX Vref 0 -> 0, step: 1
2648 00:42:04.429624
2649 00:42:04.429690 RX Delay -40 -> 252, step: 8
2650 00:42:04.429748 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
2651 00:42:04.429804 iDelay=200, Bit 1, Center 123 (56 ~ 191) 136
2652 00:42:04.429856 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2653 00:42:04.429908 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2654 00:42:04.429982 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2655 00:42:04.430035 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2656 00:42:04.430087 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2657 00:42:04.430342 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2658 00:42:04.430405 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2659 00:42:04.430478 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
2660 00:42:04.430532 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2661 00:42:04.430585 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2662 00:42:04.430637 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2663 00:42:04.430711 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2664 00:42:04.430767 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2665 00:42:04.430836 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2666 00:42:04.430902 ==
2667 00:42:04.430995 Dram Type= 6, Freq= 0, CH_0, rank 0
2668 00:42:04.431078 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2669 00:42:04.431163 ==
2670 00:42:04.431252 DQS Delay:
2671 00:42:04.431335 DQS0 = 0, DQS1 = 0
2672 00:42:04.431422 DQM Delay:
2673 00:42:04.431509 DQM0 = 122, DQM1 = 110
2674 00:42:04.431590 DQ Delay:
2675 00:42:04.431679 DQ0 =123, DQ1 =123, DQ2 =119, DQ3 =119
2676 00:42:04.431766 DQ4 =127, DQ5 =115, DQ6 =127, DQ7 =127
2677 00:42:04.431848 DQ8 =99, DQ9 =99, DQ10 =107, DQ11 =107
2678 00:42:04.431938 DQ12 =115, DQ13 =115, DQ14 =123, DQ15 =115
2679 00:42:04.432024
2680 00:42:04.432104
2681 00:42:04.432194 ==
2682 00:42:04.432280 Dram Type= 6, Freq= 0, CH_0, rank 0
2683 00:42:04.432363 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2684 00:42:04.432453 ==
2685 00:42:04.432536
2686 00:42:04.432601
2687 00:42:04.432654 TX Vref Scan disable
2688 00:42:04.432726 == TX Byte 0 ==
2689 00:42:04.432787 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2690 00:42:04.432871 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2691 00:42:04.432957 == TX Byte 1 ==
2692 00:42:04.433013 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2693 00:42:04.433066 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2694 00:42:04.433118 ==
2695 00:42:04.433184 Dram Type= 6, Freq= 0, CH_0, rank 0
2696 00:42:04.433242 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2697 00:42:04.433316 ==
2698 00:42:04.433398 TX Vref=22, minBit 3, minWin=24, winSum=410
2699 00:42:04.433474 TX Vref=24, minBit 4, minWin=24, winSum=414
2700 00:42:04.433528 TX Vref=26, minBit 7, minWin=24, winSum=418
2701 00:42:04.433581 TX Vref=28, minBit 5, minWin=25, winSum=423
2702 00:42:04.433634 TX Vref=30, minBit 1, minWin=25, winSum=420
2703 00:42:04.433708 TX Vref=32, minBit 1, minWin=25, winSum=418
2704 00:42:04.433766 [TxChooseVref] Worse bit 5, Min win 25, Win sum 423, Final Vref 28
2705 00:42:04.433820
2706 00:42:04.433872 Final TX Range 1 Vref 28
2707 00:42:04.433937
2708 00:42:04.433996 ==
2709 00:42:04.434049 Dram Type= 6, Freq= 0, CH_0, rank 0
2710 00:42:04.434101 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2711 00:42:04.434154 ==
2712 00:42:04.434225
2713 00:42:04.434280
2714 00:42:04.434333 TX Vref Scan disable
2715 00:42:04.434385 == TX Byte 0 ==
2716 00:42:04.434466 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2717 00:42:04.434549 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2718 00:42:04.434631 == TX Byte 1 ==
2719 00:42:04.434710 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2720 00:42:04.434768 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2721 00:42:04.434821
2722 00:42:04.434873 [DATLAT]
2723 00:42:04.434942 Freq=1200, CH0 RK0
2724 00:42:04.435026
2725 00:42:04.435107 DATLAT Default: 0xd
2726 00:42:04.435198 0, 0xFFFF, sum = 0
2727 00:42:04.435285 1, 0xFFFF, sum = 0
2728 00:42:04.435369 2, 0xFFFF, sum = 0
2729 00:42:04.435464 3, 0xFFFF, sum = 0
2730 00:42:04.435548 4, 0xFFFF, sum = 0
2731 00:42:04.435631 5, 0xFFFF, sum = 0
2732 00:42:04.435725 6, 0xFFFF, sum = 0
2733 00:42:04.435811 7, 0xFFFF, sum = 0
2734 00:42:04.435894 8, 0xFFFF, sum = 0
2735 00:42:04.435988 9, 0xFFFF, sum = 0
2736 00:42:04.436072 10, 0xFFFF, sum = 0
2737 00:42:04.436155 11, 0xFFFF, sum = 0
2738 00:42:04.436249 12, 0x0, sum = 1
2739 00:42:04.436334 13, 0x0, sum = 2
2740 00:42:04.436424 14, 0x0, sum = 3
2741 00:42:04.436511 15, 0x0, sum = 4
2742 00:42:04.436588 best_step = 13
2743 00:42:04.436641
2744 00:42:04.436716 ==
2745 00:42:04.436775 Dram Type= 6, Freq= 0, CH_0, rank 0
2746 00:42:04.436858 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2747 00:42:04.436946 ==
2748 00:42:04.437004 RX Vref Scan: 1
2749 00:42:04.437056
2750 00:42:04.437108 Set Vref Range= 32 -> 127
2751 00:42:04.437163
2752 00:42:04.437230 RX Vref 32 -> 127, step: 1
2753 00:42:04.437292
2754 00:42:04.437373 RX Delay -13 -> 252, step: 4
2755 00:42:04.437457
2756 00:42:04.437512 Set Vref, RX VrefLevel [Byte0]: 32
2757 00:42:04.437565 [Byte1]: 32
2758 00:42:04.437617
2759 00:42:04.437681 Set Vref, RX VrefLevel [Byte0]: 33
2760 00:42:04.437761 [Byte1]: 33
2761 00:42:04.437843
2762 00:42:04.437931 Set Vref, RX VrefLevel [Byte0]: 34
2763 00:42:04.437993 [Byte1]: 34
2764 00:42:04.438046
2765 00:42:04.438099 Set Vref, RX VrefLevel [Byte0]: 35
2766 00:42:04.438152 [Byte1]: 35
2767 00:42:04.438224
2768 00:42:04.438279 Set Vref, RX VrefLevel [Byte0]: 36
2769 00:42:04.438332 [Byte1]: 36
2770 00:42:04.438383
2771 00:42:04.438456 Set Vref, RX VrefLevel [Byte0]: 37
2772 00:42:04.438510 [Byte1]: 37
2773 00:42:04.438563
2774 00:42:04.438615 Set Vref, RX VrefLevel [Byte0]: 38
2775 00:42:04.438677 [Byte1]: 38
2776 00:42:04.438736
2777 00:42:04.438804 Set Vref, RX VrefLevel [Byte0]: 39
2778 00:42:04.438885 [Byte1]: 39
2779 00:42:04.438977
2780 00:42:04.439059 Set Vref, RX VrefLevel [Byte0]: 40
2781 00:42:04.439141 [Byte1]: 40
2782 00:42:04.439232
2783 00:42:04.439316 Set Vref, RX VrefLevel [Byte0]: 41
2784 00:42:04.439397 [Byte1]: 41
2785 00:42:04.439490
2786 00:42:04.439572 Set Vref, RX VrefLevel [Byte0]: 42
2787 00:42:04.439655 [Byte1]: 42
2788 00:42:04.439745
2789 00:42:04.439828 Set Vref, RX VrefLevel [Byte0]: 43
2790 00:42:04.439913 [Byte1]: 43
2791 00:42:04.440002
2792 00:42:04.440083 Set Vref, RX VrefLevel [Byte0]: 44
2793 00:42:04.440171 [Byte1]: 44
2794 00:42:04.440257
2795 00:42:04.440339 Set Vref, RX VrefLevel [Byte0]: 45
2796 00:42:04.440428 [Byte1]: 45
2797 00:42:04.440512
2798 00:42:04.440593 Set Vref, RX VrefLevel [Byte0]: 46
2799 00:42:04.440647 [Byte1]: 46
2800 00:42:04.440720
2801 00:42:04.440779 Set Vref, RX VrefLevel [Byte0]: 47
2802 00:42:04.440861 [Byte1]: 47
2803 00:42:04.440948
2804 00:42:04.441004 Set Vref, RX VrefLevel [Byte0]: 48
2805 00:42:04.441056 [Byte1]: 48
2806 00:42:04.441108
2807 00:42:04.441165 Set Vref, RX VrefLevel [Byte0]: 49
2808 00:42:04.441230 [Byte1]: 49
2809 00:42:04.441293
2810 00:42:04.441374 Set Vref, RX VrefLevel [Byte0]: 50
2811 00:42:04.441457 [Byte1]: 50
2812 00:42:04.441512
2813 00:42:04.441564 Set Vref, RX VrefLevel [Byte0]: 51
2814 00:42:04.441616 [Byte1]: 51
2815 00:42:04.441680
2816 00:42:04.441739 Set Vref, RX VrefLevel [Byte0]: 52
2817 00:42:04.441795 [Byte1]: 52
2818 00:42:04.441847
2819 00:42:04.442107 Set Vref, RX VrefLevel [Byte0]: 53
2820 00:42:04.442169 [Byte1]: 53
2821 00:42:04.442223
2822 00:42:04.442275 Set Vref, RX VrefLevel [Byte0]: 54
2823 00:42:04.442328 [Byte1]: 54
2824 00:42:04.442380
2825 00:42:04.442431 Set Vref, RX VrefLevel [Byte0]: 55
2826 00:42:04.442483 [Byte1]: 55
2827 00:42:04.442535
2828 00:42:04.442586 Set Vref, RX VrefLevel [Byte0]: 56
2829 00:42:04.442638 [Byte1]: 56
2830 00:42:04.442689
2831 00:42:04.442741 Set Vref, RX VrefLevel [Byte0]: 57
2832 00:42:04.442793 [Byte1]: 57
2833 00:42:04.442845
2834 00:42:04.442896 Set Vref, RX VrefLevel [Byte0]: 58
2835 00:42:04.442948 [Byte1]: 58
2836 00:42:04.443000
2837 00:42:04.443051 Set Vref, RX VrefLevel [Byte0]: 59
2838 00:42:04.443126 [Byte1]: 59
2839 00:42:04.443179
2840 00:42:04.443231 Set Vref, RX VrefLevel [Byte0]: 60
2841 00:42:04.443286 [Byte1]: 60
2842 00:42:04.443355
2843 00:42:04.443410 Set Vref, RX VrefLevel [Byte0]: 61
2844 00:42:04.443463 [Byte1]: 61
2845 00:42:04.443514
2846 00:42:04.443588 Set Vref, RX VrefLevel [Byte0]: 62
2847 00:42:04.443643 [Byte1]: 62
2848 00:42:04.443695
2849 00:42:04.443747 Set Vref, RX VrefLevel [Byte0]: 63
2850 00:42:04.443813 [Byte1]: 63
2851 00:42:04.443897
2852 00:42:04.443979 Set Vref, RX VrefLevel [Byte0]: 64
2853 00:42:04.444069 [Byte1]: 64
2854 00:42:04.444153
2855 00:42:04.444235 Set Vref, RX VrefLevel [Byte0]: 65
2856 00:42:04.444326 [Byte1]: 65
2857 00:42:04.444410
2858 00:42:04.444491 Set Vref, RX VrefLevel [Byte0]: 66
2859 00:42:04.444624 [Byte1]: 66
2860 00:42:04.444707
2861 00:42:04.444793 Set Vref, RX VrefLevel [Byte0]: 67
2862 00:42:04.444881 [Byte1]: 67
2863 00:42:04.444963
2864 00:42:04.445051 Set Vref, RX VrefLevel [Byte0]: 68
2865 00:42:04.445138 [Byte1]: 68
2866 00:42:04.445219
2867 00:42:04.445308 Set Vref, RX VrefLevel [Byte0]: 69
2868 00:42:04.445394 [Byte1]: 69
2869 00:42:04.445475
2870 00:42:04.445564 Set Vref, RX VrefLevel [Byte0]: 70
2871 00:42:04.445648 [Byte1]: 70
2872 00:42:04.445729
2873 00:42:04.445818 Set Vref, RX VrefLevel [Byte0]: 71
2874 00:42:04.445903 [Byte1]: 71
2875 00:42:04.445984
2876 00:42:04.446074 Final RX Vref Byte 0 = 61 to rank0
2877 00:42:04.446158 Final RX Vref Byte 1 = 49 to rank0
2878 00:42:04.446240 Final RX Vref Byte 0 = 61 to rank1
2879 00:42:04.446332 Final RX Vref Byte 1 = 49 to rank1==
2880 00:42:04.446417 Dram Type= 6, Freq= 0, CH_0, rank 0
2881 00:42:04.446499 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2882 00:42:04.446591 ==
2883 00:42:04.446674 DQS Delay:
2884 00:42:04.446755 DQS0 = 0, DQS1 = 0
2885 00:42:04.446846 DQM Delay:
2886 00:42:04.446929 DQM0 = 123, DQM1 = 109
2887 00:42:04.447011 DQ Delay:
2888 00:42:04.447102 DQ0 =122, DQ1 =122, DQ2 =120, DQ3 =120
2889 00:42:04.447185 DQ4 =126, DQ5 =116, DQ6 =130, DQ7 =128
2890 00:42:04.447267 DQ8 =100, DQ9 =94, DQ10 =110, DQ11 =106
2891 00:42:04.447358 DQ12 =116, DQ13 =110, DQ14 =122, DQ15 =118
2892 00:42:04.447442
2893 00:42:04.447523
2894 00:42:04.447616 [DQSOSCAuto] RK0, (LSB)MR18= 0xc08, (MSB)MR19= 0x404, tDQSOscB0 = 406 ps tDQSOscB1 = 405 ps
2895 00:42:04.447699 CH0 RK0: MR19=404, MR18=C08
2896 00:42:04.447783 CH0_RK0: MR19=0x404, MR18=0xC08, DQSOSC=405, MR23=63, INC=39, DEC=26
2897 00:42:04.447874
2898 00:42:04.447957 ----->DramcWriteLeveling(PI) begin...
2899 00:42:04.448047 ==
2900 00:42:04.448133 Dram Type= 6, Freq= 0, CH_0, rank 1
2901 00:42:04.448215 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2902 00:42:04.448304 ==
2903 00:42:04.448390 Write leveling (Byte 0): 35 => 35
2904 00:42:04.448472 Write leveling (Byte 1): 29 => 29
2905 00:42:04.448565 DramcWriteLeveling(PI) end<-----
2906 00:42:04.448650
2907 00:42:04.448731 ==
2908 00:42:04.448821 Dram Type= 6, Freq= 0, CH_0, rank 1
2909 00:42:04.448906 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2910 00:42:04.448988 ==
2911 00:42:04.449079 [Gating] SW mode calibration
2912 00:42:04.449164 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2913 00:42:04.449247 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2914 00:42:04.449339 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2915 00:42:04.449424 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2916 00:42:04.449507 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2917 00:42:04.449599 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2918 00:42:04.449682 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2919 00:42:04.449764 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2920 00:42:04.449856 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2921 00:42:04.449940 0 15 28 | B1->B0 | 2c2c 2c2c | 0 0 | (0 0) (0 0)
2922 00:42:04.450022 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2923 00:42:04.450114 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2924 00:42:04.450197 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2925 00:42:04.450279 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2926 00:42:04.450371 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2927 00:42:04.450455 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2928 00:42:04.450540 1 0 24 | B1->B0 | 2525 2a29 | 0 1 | (0 0) (1 1)
2929 00:42:04.450634 1 0 28 | B1->B0 | 3f3f 4545 | 0 0 | (0 0) (0 0)
2930 00:42:04.450717 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2931 00:42:04.450806 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2932 00:42:04.450892 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2933 00:42:04.450975 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2934 00:42:04.451063 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2935 00:42:04.451148 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2936 00:42:04.451230 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2937 00:42:04.451320 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2938 00:42:04.451405 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
2939 00:42:04.451488 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2940 00:42:04.451579 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2941 00:42:04.451662 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2942 00:42:04.451744 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2943 00:42:04.452041 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2944 00:42:04.452136 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2945 00:42:04.452220 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2946 00:42:04.452308 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2947 00:42:04.452368 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2948 00:42:04.452444 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2949 00:42:04.452527 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2950 00:42:04.452652 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2951 00:42:04.452708 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2952 00:42:04.452761 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2953 00:42:04.452834 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2954 00:42:04.452892 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2955 00:42:04.452974 Total UI for P1: 0, mck2ui 16
2956 00:42:04.453065 best dqsien dly found for B0: ( 1, 3, 26)
2957 00:42:04.453151 Total UI for P1: 0, mck2ui 16
2958 00:42:04.453233 best dqsien dly found for B1: ( 1, 3, 28)
2959 00:42:04.453325 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2960 00:42:04.453410 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2961 00:42:04.453490
2962 00:42:04.453582 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2963 00:42:04.453667 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2964 00:42:04.453748 [Gating] SW calibration Done
2965 00:42:04.453840 ==
2966 00:42:04.453924 Dram Type= 6, Freq= 0, CH_0, rank 1
2967 00:42:04.454006 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2968 00:42:04.454098 ==
2969 00:42:04.454181 RX Vref Scan: 0
2970 00:42:04.454262
2971 00:42:04.454352 RX Vref 0 -> 0, step: 1
2972 00:42:04.454435
2973 00:42:04.454517 RX Delay -40 -> 252, step: 8
2974 00:42:04.454608 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2975 00:42:04.454691 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2976 00:42:04.454773 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2977 00:42:04.454865 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2978 00:42:04.454949 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2979 00:42:04.455031 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2980 00:42:04.455123 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2981 00:42:04.455206 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2982 00:42:04.455291 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2983 00:42:04.455379 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2984 00:42:04.455463 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2985 00:42:04.455551 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2986 00:42:04.455637 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2987 00:42:04.455718 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2988 00:42:04.455808 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2989 00:42:04.455893 iDelay=200, Bit 15, Center 111 (48 ~ 175) 128
2990 00:42:04.455975 ==
2991 00:42:04.456064 Dram Type= 6, Freq= 0, CH_0, rank 1
2992 00:42:04.456149 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2993 00:42:04.456231 ==
2994 00:42:04.456320 DQS Delay:
2995 00:42:04.456405 DQS0 = 0, DQS1 = 0
2996 00:42:04.456486 DQM Delay:
2997 00:42:04.456612 DQM0 = 120, DQM1 = 108
2998 00:42:04.456708 DQ Delay:
2999 00:42:04.456793 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =115
3000 00:42:04.456882 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
3001 00:42:04.456965 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =107
3002 00:42:04.569045 DQ12 =115, DQ13 =115, DQ14 =119, DQ15 =111
3003 00:42:04.569186
3004 00:42:04.569253
3005 00:42:04.569334 ==
3006 00:42:04.569398 Dram Type= 6, Freq= 0, CH_0, rank 1
3007 00:42:04.569456 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3008 00:42:04.569513 ==
3009 00:42:04.569602
3010 00:42:04.569687
3011 00:42:04.569770 TX Vref Scan disable
3012 00:42:04.569847 == TX Byte 0 ==
3013 00:42:04.569905 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
3014 00:42:04.569961 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
3015 00:42:04.570015 == TX Byte 1 ==
3016 00:42:04.570089 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3017 00:42:04.570145 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3018 00:42:04.570199 ==
3019 00:42:04.570252 Dram Type= 6, Freq= 0, CH_0, rank 1
3020 00:42:04.570323 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3021 00:42:04.570408 ==
3022 00:42:04.570491 TX Vref=22, minBit 1, minWin=24, winSum=411
3023 00:42:04.570585 TX Vref=24, minBit 1, minWin=24, winSum=415
3024 00:42:04.570669 TX Vref=26, minBit 1, minWin=24, winSum=418
3025 00:42:04.570752 TX Vref=28, minBit 2, minWin=25, winSum=428
3026 00:42:04.570845 TX Vref=30, minBit 5, minWin=25, winSum=427
3027 00:42:04.570930 TX Vref=32, minBit 4, minWin=25, winSum=422
3028 00:42:04.571013 [TxChooseVref] Worse bit 2, Min win 25, Win sum 428, Final Vref 28
3029 00:42:04.571106
3030 00:42:04.571189 Final TX Range 1 Vref 28
3031 00:42:04.571270
3032 00:42:04.571362 ==
3033 00:42:04.571446 Dram Type= 6, Freq= 0, CH_0, rank 1
3034 00:42:04.571529 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3035 00:42:04.571621 ==
3036 00:42:04.571703
3037 00:42:04.571787
3038 00:42:04.571854 TX Vref Scan disable
3039 00:42:04.571911 == TX Byte 0 ==
3040 00:42:04.571964 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
3041 00:42:04.572017 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
3042 00:42:04.572091 == TX Byte 1 ==
3043 00:42:04.572146 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3044 00:42:04.572198 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3045 00:42:04.572250
3046 00:42:04.572319 [DATLAT]
3047 00:42:04.572377 Freq=1200, CH0 RK1
3048 00:42:04.572458
3049 00:42:04.572549 DATLAT Default: 0xd
3050 00:42:04.572638 0, 0xFFFF, sum = 0
3051 00:42:04.572723 1, 0xFFFF, sum = 0
3052 00:42:04.572814 2, 0xFFFF, sum = 0
3053 00:42:04.572902 3, 0xFFFF, sum = 0
3054 00:42:04.572986 4, 0xFFFF, sum = 0
3055 00:42:04.573080 5, 0xFFFF, sum = 0
3056 00:42:04.573164 6, 0xFFFF, sum = 0
3057 00:42:04.573247 7, 0xFFFF, sum = 0
3058 00:42:04.573341 8, 0xFFFF, sum = 0
3059 00:42:04.573427 9, 0xFFFF, sum = 0
3060 00:42:04.573510 10, 0xFFFF, sum = 0
3061 00:42:04.573605 11, 0xFFFF, sum = 0
3062 00:42:04.573689 12, 0x0, sum = 1
3063 00:42:04.573773 13, 0x0, sum = 2
3064 00:42:04.573867 14, 0x0, sum = 3
3065 00:42:04.573952 15, 0x0, sum = 4
3066 00:42:04.574039 best_step = 13
3067 00:42:04.574126
3068 00:42:04.574207 ==
3069 00:42:04.574293 Dram Type= 6, Freq= 0, CH_0, rank 1
3070 00:42:04.574381 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3071 00:42:04.574464 ==
3072 00:42:04.574553 RX Vref Scan: 0
3073 00:42:04.574638
3074 00:42:04.574719 RX Vref 0 -> 0, step: 1
3075 00:42:04.574809
3076 00:42:04.574896 RX Delay -21 -> 252, step: 4
3077 00:42:04.574980 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3078 00:42:04.575071 iDelay=195, Bit 1, Center 122 (55 ~ 190) 136
3079 00:42:04.575158 iDelay=195, Bit 2, Center 116 (51 ~ 182) 132
3080 00:42:04.575451 iDelay=195, Bit 3, Center 112 (47 ~ 178) 132
3081 00:42:04.575550 iDelay=195, Bit 4, Center 120 (55 ~ 186) 132
3082 00:42:04.575639 iDelay=195, Bit 5, Center 114 (51 ~ 178) 128
3083 00:42:04.575724 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3084 00:42:04.575816 iDelay=195, Bit 7, Center 124 (55 ~ 194) 140
3085 00:42:04.575989 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3086 00:42:04.576114 iDelay=195, Bit 9, Center 94 (31 ~ 158) 128
3087 00:42:04.576228 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3088 00:42:04.576322 iDelay=195, Bit 11, Center 104 (43 ~ 166) 124
3089 00:42:04.576411 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
3090 00:42:04.576497 iDelay=195, Bit 13, Center 110 (47 ~ 174) 128
3091 00:42:04.576611 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3092 00:42:04.576695 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
3093 00:42:04.576778 ==
3094 00:42:04.576872 Dram Type= 6, Freq= 0, CH_0, rank 1
3095 00:42:04.576957 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3096 00:42:04.577047 ==
3097 00:42:04.577134 DQS Delay:
3098 00:42:04.577217 DQS0 = 0, DQS1 = 0
3099 00:42:04.577307 DQM Delay:
3100 00:42:04.577395 DQM0 = 119, DQM1 = 107
3101 00:42:04.577477 DQ Delay:
3102 00:42:04.577568 DQ0 =118, DQ1 =122, DQ2 =116, DQ3 =112
3103 00:42:04.577654 DQ4 =120, DQ5 =114, DQ6 =126, DQ7 =124
3104 00:42:04.577737 DQ8 =98, DQ9 =94, DQ10 =110, DQ11 =104
3105 00:42:04.577847 DQ12 =112, DQ13 =110, DQ14 =118, DQ15 =114
3106 00:42:04.577946
3107 00:42:04.578032
3108 00:42:04.578123 [DQSOSCAuto] RK1, (LSB)MR18= 0x14fa, (MSB)MR19= 0x403, tDQSOscB0 = 412 ps tDQSOscB1 = 402 ps
3109 00:42:04.578207 CH0 RK1: MR19=403, MR18=14FA
3110 00:42:04.578299 CH0_RK1: MR19=0x403, MR18=0x14FA, DQSOSC=402, MR23=63, INC=40, DEC=27
3111 00:42:04.578387 [RxdqsGatingPostProcess] freq 1200
3112 00:42:04.578472 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3113 00:42:04.578563 best DQS0 dly(2T, 0.5T) = (0, 11)
3114 00:42:04.578650 best DQS1 dly(2T, 0.5T) = (0, 11)
3115 00:42:04.578733 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3116 00:42:04.578825 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3117 00:42:04.578911 best DQS0 dly(2T, 0.5T) = (0, 11)
3118 00:42:04.578995 best DQS1 dly(2T, 0.5T) = (0, 11)
3119 00:42:04.579087 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3120 00:42:04.579171 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3121 00:42:04.579254 Pre-setting of DQS Precalculation
3122 00:42:04.579348 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3123 00:42:04.579434 ==
3124 00:42:04.579517 Dram Type= 6, Freq= 0, CH_1, rank 0
3125 00:42:04.579611 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3126 00:42:04.579694 ==
3127 00:42:04.579779 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3128 00:42:04.579872 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
3129 00:42:04.579958 [CA 0] Center 37 (7~68) winsize 62
3130 00:42:04.580047 [CA 1] Center 37 (7~68) winsize 62
3131 00:42:04.580135 [CA 2] Center 35 (5~65) winsize 61
3132 00:42:04.580218 [CA 3] Center 34 (4~65) winsize 62
3133 00:42:04.580308 [CA 4] Center 34 (3~65) winsize 63
3134 00:42:04.580395 [CA 5] Center 33 (3~64) winsize 62
3135 00:42:04.580478
3136 00:42:04.580595 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3137 00:42:04.580693
3138 00:42:04.580776 [CATrainingPosCal] consider 1 rank data
3139 00:42:04.580849 u2DelayCellTimex100 = 270/100 ps
3140 00:42:04.580912 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3141 00:42:04.580995 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3142 00:42:04.581090 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3143 00:42:04.581175 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3144 00:42:04.581258 CA4 delay=34 (3~65),Diff = 1 PI (4 cell)
3145 00:42:04.581352 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3146 00:42:04.581437
3147 00:42:04.581520 CA PerBit enable=1, Macro0, CA PI delay=33
3148 00:42:04.581613
3149 00:42:04.581696 [CBTSetCACLKResult] CA Dly = 33
3150 00:42:04.581779 CS Dly: 5 (0~36)
3151 00:42:04.581853 ==
3152 00:42:04.581911 Dram Type= 6, Freq= 0, CH_1, rank 1
3153 00:42:04.581965 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3154 00:42:04.582020 ==
3155 00:42:04.582094 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3156 00:42:04.582151 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3157 00:42:04.582205 [CA 0] Center 38 (8~68) winsize 61
3158 00:42:04.582259 [CA 1] Center 38 (7~69) winsize 63
3159 00:42:04.582333 [CA 2] Center 35 (5~66) winsize 62
3160 00:42:04.582393 [CA 3] Center 35 (5~65) winsize 61
3161 00:42:04.582476 [CA 4] Center 35 (5~65) winsize 61
3162 00:42:04.582569 [CA 5] Center 34 (4~64) winsize 61
3163 00:42:04.582655
3164 00:42:04.582738 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3165 00:42:04.582830
3166 00:42:04.582916 [CATrainingPosCal] consider 2 rank data
3167 00:42:04.583000 u2DelayCellTimex100 = 270/100 ps
3168 00:42:04.583094 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3169 00:42:04.583179 CA1 delay=37 (7~68),Diff = 3 PI (14 cell)
3170 00:42:04.583262 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3171 00:42:04.583356 CA3 delay=35 (5~65),Diff = 1 PI (4 cell)
3172 00:42:04.583441 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
3173 00:42:04.583524 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3174 00:42:04.583618
3175 00:42:04.583702 CA PerBit enable=1, Macro0, CA PI delay=34
3176 00:42:04.583787
3177 00:42:04.583878 [CBTSetCACLKResult] CA Dly = 34
3178 00:42:04.583962 CS Dly: 6 (0~39)
3179 00:42:04.584051
3180 00:42:04.584139 ----->DramcWriteLeveling(PI) begin...
3181 00:42:04.584223 ==
3182 00:42:04.584314 Dram Type= 6, Freq= 0, CH_1, rank 0
3183 00:42:04.584402 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3184 00:42:04.584486 ==
3185 00:42:04.584614 Write leveling (Byte 0): 24 => 24
3186 00:42:04.584700 Write leveling (Byte 1): 29 => 29
3187 00:42:04.584787 DramcWriteLeveling(PI) end<-----
3188 00:42:04.584877
3189 00:42:04.584961 ==
3190 00:42:04.585051 Dram Type= 6, Freq= 0, CH_1, rank 0
3191 00:42:04.585139 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3192 00:42:04.585222 ==
3193 00:42:04.585312 [Gating] SW mode calibration
3194 00:42:04.585401 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3195 00:42:04.585486 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3196 00:42:04.585580 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3197 00:42:04.585666 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3198 00:42:04.585749 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3199 00:42:04.586052 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3200 00:42:04.586146 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3201 00:42:04.586231 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3202 00:42:04.586325 0 15 24 | B1->B0 | 2c2c 2525 | 0 0 | (1 0) (1 0)
3203 00:42:04.586412 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3204 00:42:04.586496 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3205 00:42:04.586591 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3206 00:42:04.586675 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3207 00:42:04.586794 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3208 00:42:04.586886 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3209 00:42:04.586970 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3210 00:42:04.587061 1 0 24 | B1->B0 | 3c3c 4545 | 0 0 | (0 0) (0 0)
3211 00:42:04.587148 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3212 00:42:04.587231 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3213 00:42:04.587324 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3214 00:42:04.587410 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3215 00:42:04.587494 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3216 00:42:04.587620 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3217 00:42:04.587704 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3218 00:42:04.587794 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3219 00:42:04.587884 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3220 00:42:04.587968 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3221 00:42:04.588060 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3222 00:42:04.588147 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3223 00:42:04.588230 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3224 00:42:04.588321 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3225 00:42:04.588408 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3226 00:42:04.588492 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3227 00:42:04.588634 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3228 00:42:04.588719 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3229 00:42:04.588810 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3230 00:42:04.588898 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3231 00:42:04.588982 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3232 00:42:04.589074 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3233 00:42:04.589159 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3234 00:42:04.589242 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3235 00:42:04.589336 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3236 00:42:04.589421 Total UI for P1: 0, mck2ui 16
3237 00:42:04.589505 best dqsien dly found for B0: ( 1, 3, 24)
3238 00:42:04.589599 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3239 00:42:04.589682 Total UI for P1: 0, mck2ui 16
3240 00:42:04.589766 best dqsien dly found for B1: ( 1, 3, 26)
3241 00:42:04.589881 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3242 00:42:04.589980 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3243 00:42:04.590071
3244 00:42:04.590157 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3245 00:42:04.590241 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3246 00:42:04.590334 [Gating] SW calibration Done
3247 00:42:04.590418 ==
3248 00:42:04.590502 Dram Type= 6, Freq= 0, CH_1, rank 0
3249 00:42:04.590595 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3250 00:42:04.590679 ==
3251 00:42:04.590762 RX Vref Scan: 0
3252 00:42:04.590854
3253 00:42:04.590939 RX Vref 0 -> 0, step: 1
3254 00:42:04.591021
3255 00:42:04.591113 RX Delay -40 -> 252, step: 8
3256 00:42:04.591197 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3257 00:42:04.591281 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3258 00:42:04.591374 iDelay=200, Bit 2, Center 111 (48 ~ 175) 128
3259 00:42:04.591459 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3260 00:42:04.591550 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3261 00:42:04.591637 iDelay=200, Bit 5, Center 127 (64 ~ 191) 128
3262 00:42:04.591720 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3263 00:42:04.591811 iDelay=200, Bit 7, Center 119 (56 ~ 183) 128
3264 00:42:04.591899 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3265 00:42:04.591982 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3266 00:42:04.592075 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3267 00:42:04.592160 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3268 00:42:04.592243 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3269 00:42:04.592336 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3270 00:42:04.592422 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3271 00:42:04.592505 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3272 00:42:04.592637 ==
3273 00:42:04.592721 Dram Type= 6, Freq= 0, CH_1, rank 0
3274 00:42:04.592812 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3275 00:42:04.592899 ==
3276 00:42:04.592982 DQS Delay:
3277 00:42:04.593073 DQS0 = 0, DQS1 = 0
3278 00:42:04.593158 DQM Delay:
3279 00:42:04.593240 DQM0 = 120, DQM1 = 112
3280 00:42:04.593333 DQ Delay:
3281 00:42:04.593418 DQ0 =123, DQ1 =115, DQ2 =111, DQ3 =119
3282 00:42:04.593501 DQ4 =115, DQ5 =127, DQ6 =131, DQ7 =119
3283 00:42:04.593594 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3284 00:42:04.593678 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3285 00:42:04.593760
3286 00:42:04.593852
3287 00:42:04.593968 ==
3288 00:42:04.594058 Dram Type= 6, Freq= 0, CH_1, rank 0
3289 00:42:04.594145 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3290 00:42:04.594228 ==
3291 00:42:04.594318
3292 00:42:04.594404
3293 00:42:04.594487 TX Vref Scan disable
3294 00:42:04.594579 == TX Byte 0 ==
3295 00:42:04.594664 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3296 00:42:04.594749 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3297 00:42:04.594841 == TX Byte 1 ==
3298 00:42:04.594926 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3299 00:42:04.595010 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3300 00:42:04.595103 ==
3301 00:42:04.595187 Dram Type= 6, Freq= 0, CH_1, rank 0
3302 00:42:04.595270 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3303 00:42:04.595364 ==
3304 00:42:04.595449 TX Vref=22, minBit 1, minWin=24, winSum=406
3305 00:42:04.595535 TX Vref=24, minBit 11, minWin=24, winSum=410
3306 00:42:04.595838 TX Vref=26, minBit 3, minWin=25, winSum=416
3307 00:42:04.595930 TX Vref=28, minBit 10, minWin=25, winSum=422
3308 00:42:04.596016 TX Vref=30, minBit 8, minWin=25, winSum=423
3309 00:42:04.596111 TX Vref=32, minBit 1, minWin=26, winSum=424
3310 00:42:04.596196 [TxChooseVref] Worse bit 1, Min win 26, Win sum 424, Final Vref 32
3311 00:42:04.596280
3312 00:42:04.596374 Final TX Range 1 Vref 32
3313 00:42:04.596459
3314 00:42:04.596552 ==
3315 00:42:04.596673 Dram Type= 6, Freq= 0, CH_1, rank 0
3316 00:42:04.596756 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3317 00:42:04.596849 ==
3318 00:42:04.596934
3319 00:42:04.597016
3320 00:42:04.597108 TX Vref Scan disable
3321 00:42:04.597192 == TX Byte 0 ==
3322 00:42:04.597275 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3323 00:42:04.597370 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3324 00:42:04.597455 == TX Byte 1 ==
3325 00:42:04.597544 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3326 00:42:04.597632 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3327 00:42:04.597715
3328 00:42:04.597803 [DATLAT]
3329 00:42:04.597890 Freq=1200, CH1 RK0
3330 00:42:04.597974
3331 00:42:04.598063 DATLAT Default: 0xd
3332 00:42:04.598149 0, 0xFFFF, sum = 0
3333 00:42:04.598235 1, 0xFFFF, sum = 0
3334 00:42:04.598329 2, 0xFFFF, sum = 0
3335 00:42:04.598417 3, 0xFFFF, sum = 0
3336 00:42:04.598501 4, 0xFFFF, sum = 0
3337 00:42:04.598596 5, 0xFFFF, sum = 0
3338 00:42:04.598681 6, 0xFFFF, sum = 0
3339 00:42:04.598766 7, 0xFFFF, sum = 0
3340 00:42:04.598860 8, 0xFFFF, sum = 0
3341 00:42:04.598947 9, 0xFFFF, sum = 0
3342 00:42:04.599031 10, 0xFFFF, sum = 0
3343 00:42:04.599127 11, 0xFFFF, sum = 0
3344 00:42:04.599212 12, 0x0, sum = 1
3345 00:42:04.599303 13, 0x0, sum = 2
3346 00:42:04.599393 14, 0x0, sum = 3
3347 00:42:04.599478 15, 0x0, sum = 4
3348 00:42:04.599572 best_step = 13
3349 00:42:04.599656
3350 00:42:04.599738 ==
3351 00:42:04.599831 Dram Type= 6, Freq= 0, CH_1, rank 0
3352 00:42:04.599917 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3353 00:42:04.600001 ==
3354 00:42:04.600093 RX Vref Scan: 1
3355 00:42:04.600176
3356 00:42:04.600259 Set Vref Range= 32 -> 127
3357 00:42:04.600351
3358 00:42:04.600435 RX Vref 32 -> 127, step: 1
3359 00:42:04.600518
3360 00:42:04.600649 RX Delay -13 -> 252, step: 4
3361 00:42:04.600732
3362 00:42:04.600822 Set Vref, RX VrefLevel [Byte0]: 32
3363 00:42:04.600907 [Byte1]: 32
3364 00:42:04.600988
3365 00:42:04.601078 Set Vref, RX VrefLevel [Byte0]: 33
3366 00:42:04.601162 [Byte1]: 33
3367 00:42:04.601242
3368 00:42:04.601333 Set Vref, RX VrefLevel [Byte0]: 34
3369 00:42:04.601418 [Byte1]: 34
3370 00:42:04.601499
3371 00:42:04.601590 Set Vref, RX VrefLevel [Byte0]: 35
3372 00:42:04.601673 [Byte1]: 35
3373 00:42:04.601753
3374 00:42:04.601844 Set Vref, RX VrefLevel [Byte0]: 36
3375 00:42:04.601929 [Byte1]: 36
3376 00:42:04.602009
3377 00:42:04.602100 Set Vref, RX VrefLevel [Byte0]: 37
3378 00:42:04.602183 [Byte1]: 37
3379 00:42:04.602264
3380 00:42:04.602354 Set Vref, RX VrefLevel [Byte0]: 38
3381 00:42:04.602438 [Byte1]: 38
3382 00:42:04.602519
3383 00:42:04.602610 Set Vref, RX VrefLevel [Byte0]: 39
3384 00:42:04.602692 [Byte1]: 39
3385 00:42:04.602772
3386 00:42:04.602864 Set Vref, RX VrefLevel [Byte0]: 40
3387 00:42:04.602948 [Byte1]: 40
3388 00:42:04.603028
3389 00:42:04.603120 Set Vref, RX VrefLevel [Byte0]: 41
3390 00:42:04.603202 [Byte1]: 41
3391 00:42:04.603285
3392 00:42:04.603374 Set Vref, RX VrefLevel [Byte0]: 42
3393 00:42:04.603457 [Byte1]: 42
3394 00:42:04.603544
3395 00:42:04.603629 Set Vref, RX VrefLevel [Byte0]: 43
3396 00:42:04.603711 [Byte1]: 43
3397 00:42:04.603799
3398 00:42:04.603922 Set Vref, RX VrefLevel [Byte0]: 44
3399 00:42:04.604003 [Byte1]: 44
3400 00:42:04.604093
3401 00:42:04.604176 Set Vref, RX VrefLevel [Byte0]: 45
3402 00:42:04.604258 [Byte1]: 45
3403 00:42:04.604349
3404 00:42:04.604432 Set Vref, RX VrefLevel [Byte0]: 46
3405 00:42:04.604514 [Byte1]: 46
3406 00:42:04.604641
3407 00:42:04.604723 Set Vref, RX VrefLevel [Byte0]: 47
3408 00:42:04.604813 [Byte1]: 47
3409 00:42:04.604898
3410 00:42:04.604979 Set Vref, RX VrefLevel [Byte0]: 48
3411 00:42:04.605069 [Byte1]: 48
3412 00:42:04.605153
3413 00:42:04.605237 Set Vref, RX VrefLevel [Byte0]: 49
3414 00:42:04.605330 [Byte1]: 49
3415 00:42:04.605414
3416 00:42:04.605495 Set Vref, RX VrefLevel [Byte0]: 50
3417 00:42:04.605578 [Byte1]: 50
3418 00:42:04.605660
3419 00:42:04.605741 Set Vref, RX VrefLevel [Byte0]: 51
3420 00:42:04.605824 [Byte1]: 51
3421 00:42:04.605904
3422 00:42:04.605988 Set Vref, RX VrefLevel [Byte0]: 52
3423 00:42:04.606070 [Byte1]: 52
3424 00:42:04.606152
3425 00:42:04.606233 Set Vref, RX VrefLevel [Byte0]: 53
3426 00:42:04.606316 [Byte1]: 53
3427 00:42:04.606396
3428 00:42:04.606477 Set Vref, RX VrefLevel [Byte0]: 54
3429 00:42:04.606564 [Byte1]: 54
3430 00:42:04.606645
3431 00:42:04.606737 Set Vref, RX VrefLevel [Byte0]: 55
3432 00:42:04.606819 [Byte1]: 55
3433 00:42:04.606902
3434 00:42:04.606983 Set Vref, RX VrefLevel [Byte0]: 56
3435 00:42:04.607072 [Byte1]: 56
3436 00:42:04.607156
3437 00:42:04.607239 Set Vref, RX VrefLevel [Byte0]: 57
3438 00:42:04.607321 [Byte1]: 57
3439 00:42:04.607402
3440 00:42:04.607494 Set Vref, RX VrefLevel [Byte0]: 58
3441 00:42:04.607578 [Byte1]: 58
3442 00:42:04.607660
3443 00:42:04.607739 Set Vref, RX VrefLevel [Byte0]: 59
3444 00:42:04.607821 [Byte1]: 59
3445 00:42:04.607904
3446 00:42:04.607996 Set Vref, RX VrefLevel [Byte0]: 60
3447 00:42:04.608080 [Byte1]: 60
3448 00:42:04.608163
3449 00:42:04.608253 Set Vref, RX VrefLevel [Byte0]: 61
3450 00:42:04.608335 [Byte1]: 61
3451 00:42:04.608417
3452 00:42:04.608506 Set Vref, RX VrefLevel [Byte0]: 62
3453 00:42:04.608638 [Byte1]: 62
3454 00:42:04.608729
3455 00:42:04.608811 Set Vref, RX VrefLevel [Byte0]: 63
3456 00:42:04.608893 [Byte1]: 63
3457 00:42:04.608984
3458 00:42:04.609067 Set Vref, RX VrefLevel [Byte0]: 64
3459 00:42:04.609149 [Byte1]: 64
3460 00:42:04.609240
3461 00:42:04.609322 Set Vref, RX VrefLevel [Byte0]: 65
3462 00:42:04.609404 [Byte1]: 65
3463 00:42:04.609495
3464 00:42:04.609577 Set Vref, RX VrefLevel [Byte0]: 66
3465 00:42:04.609661 [Byte1]: 66
3466 00:42:04.609749
3467 00:42:04.609830 Set Vref, RX VrefLevel [Byte0]: 67
3468 00:42:04.609915 [Byte1]: 67
3469 00:42:04.610002
3470 00:42:04.610085 Set Vref, RX VrefLevel [Byte0]: 68
3471 00:42:04.610173 [Byte1]: 68
3472 00:42:04.610258
3473 00:42:04.610340 Final RX Vref Byte 0 = 52 to rank0
3474 00:42:04.610429 Final RX Vref Byte 1 = 53 to rank0
3475 00:42:04.610726 Final RX Vref Byte 0 = 52 to rank1
3476 00:42:04.610820 Final RX Vref Byte 1 = 53 to rank1==
3477 00:42:04.610905 Dram Type= 6, Freq= 0, CH_1, rank 0
3478 00:42:04.610998 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3479 00:42:04.611082 ==
3480 00:42:04.611169 DQS Delay:
3481 00:42:04.611257 DQS0 = 0, DQS1 = 0
3482 00:42:04.611339 DQM Delay:
3483 00:42:04.611427 DQM0 = 118, DQM1 = 112
3484 00:42:04.611513 DQ Delay:
3485 00:42:04.611595 DQ0 =120, DQ1 =112, DQ2 =112, DQ3 =118
3486 00:42:04.611684 DQ4 =118, DQ5 =126, DQ6 =128, DQ7 =116
3487 00:42:04.611770 DQ8 =102, DQ9 =100, DQ10 =114, DQ11 =106
3488 00:42:04.611853 DQ12 =122, DQ13 =118, DQ14 =122, DQ15 =118
3489 00:42:04.611941
3490 00:42:04.612026
3491 00:42:04.612109 [DQSOSCAuto] RK0, (LSB)MR18= 0x71b, (MSB)MR19= 0x404, tDQSOscB0 = 399 ps tDQSOscB1 = 407 ps
3492 00:42:04.612201 CH1 RK0: MR19=404, MR18=71B
3493 00:42:04.612285 CH1_RK0: MR19=0x404, MR18=0x71B, DQSOSC=399, MR23=63, INC=41, DEC=27
3494 00:42:04.612367
3495 00:42:04.612456 ----->DramcWriteLeveling(PI) begin...
3496 00:42:04.612542 ==
3497 00:42:04.612636 Dram Type= 6, Freq= 0, CH_1, rank 1
3498 00:42:04.612710 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3499 00:42:04.612766 ==
3500 00:42:04.612818 Write leveling (Byte 0): 24 => 24
3501 00:42:04.612870 Write leveling (Byte 1): 28 => 28
3502 00:42:04.612935 DramcWriteLeveling(PI) end<-----
3503 00:42:04.612993
3504 00:42:04.613068 ==
3505 00:42:04.613151 Dram Type= 6, Freq= 0, CH_1, rank 1
3506 00:42:04.613225 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3507 00:42:04.613280 ==
3508 00:42:04.613332 [Gating] SW mode calibration
3509 00:42:04.613384 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3510 00:42:04.613467 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3511 00:42:04.613541 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3512 00:42:04.613595 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3513 00:42:04.613648 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3514 00:42:04.613721 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3515 00:42:04.613775 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3516 00:42:04.613828 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3517 00:42:04.613880 0 15 24 | B1->B0 | 2727 3434 | 0 1 | (0 0) (1 0)
3518 00:42:04.613953 0 15 28 | B1->B0 | 2323 2828 | 0 1 | (0 0) (0 0)
3519 00:42:04.614008 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3520 00:42:04.614063 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3521 00:42:04.614115 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3522 00:42:04.614179 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3523 00:42:04.614239 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3524 00:42:04.614292 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3525 00:42:04.614344 1 0 24 | B1->B0 | 4040 3030 | 0 1 | (0 0) (0 0)
3526 00:42:04.614397 1 0 28 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
3527 00:42:04.614470 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3528 00:42:04.614525 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3529 00:42:04.614578 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3530 00:42:04.614631 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3531 00:42:04.614710 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3532 00:42:04.614793 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3533 00:42:04.614875 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3534 00:42:04.614968 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3535 00:42:04.615052 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3536 00:42:04.615134 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3537 00:42:04.615227 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3538 00:42:04.615310 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3539 00:42:04.615392 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3540 00:42:04.615485 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3541 00:42:04.615569 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3542 00:42:04.615651 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3543 00:42:04.615744 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3544 00:42:04.615827 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3545 00:42:04.615910 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3546 00:42:04.616001 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3547 00:42:04.616085 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3548 00:42:04.616172 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3549 00:42:04.616259 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3550 00:42:04.616341 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3551 00:42:04.616428 Total UI for P1: 0, mck2ui 16
3552 00:42:04.616516 best dqsien dly found for B0: ( 1, 3, 22)
3553 00:42:04.616589 Total UI for P1: 0, mck2ui 16
3554 00:42:04.616643 best dqsien dly found for B1: ( 1, 3, 22)
3555 00:42:04.616716 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3556 00:42:04.616770 best DQS1 dly(MCK, UI, PI) = (1, 3, 22)
3557 00:42:04.616822
3558 00:42:04.616874 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3559 00:42:04.616942 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 22)
3560 00:42:04.617000 [Gating] SW calibration Done
3561 00:42:04.617080 ==
3562 00:42:04.617165 Dram Type= 6, Freq= 0, CH_1, rank 1
3563 00:42:04.617231 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3564 00:42:04.617285 ==
3565 00:42:04.617337 RX Vref Scan: 0
3566 00:42:04.617389
3567 00:42:04.617462 RX Vref 0 -> 0, step: 1
3568 00:42:04.617517
3569 00:42:04.617570 RX Delay -40 -> 252, step: 8
3570 00:42:04.617622 iDelay=200, Bit 0, Center 123 (64 ~ 183) 120
3571 00:42:04.617687 iDelay=200, Bit 1, Center 111 (48 ~ 175) 128
3572 00:42:04.617746 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3573 00:42:04.617798 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3574 00:42:04.617850 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
3575 00:42:04.617902 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3576 00:42:04.617975 iDelay=200, Bit 6, Center 123 (56 ~ 191) 136
3577 00:42:04.618030 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3578 00:42:04.618083 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3579 00:42:04.618340 iDelay=200, Bit 9, Center 103 (40 ~ 167) 128
3580 00:42:04.618439 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3581 00:42:04.618528 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3582 00:42:04.618611 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3583 00:42:04.618703 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3584 00:42:04.618787 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3585 00:42:04.618869 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3586 00:42:04.618960 ==
3587 00:42:04.619045 Dram Type= 6, Freq= 0, CH_1, rank 1
3588 00:42:04.619128 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3589 00:42:04.619221 ==
3590 00:42:04.619303 DQS Delay:
3591 00:42:04.619385 DQS0 = 0, DQS1 = 0
3592 00:42:04.619476 DQM Delay:
3593 00:42:04.619560 DQM0 = 119, DQM1 = 112
3594 00:42:04.619642 DQ Delay:
3595 00:42:04.619733 DQ0 =123, DQ1 =111, DQ2 =107, DQ3 =119
3596 00:42:04.619816 DQ4 =123, DQ5 =131, DQ6 =123, DQ7 =115
3597 00:42:04.619898 DQ8 =99, DQ9 =103, DQ10 =115, DQ11 =107
3598 00:42:04.619992 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3599 00:42:04.620075
3600 00:42:04.620156
3601 00:42:04.620246 ==
3602 00:42:04.620329 Dram Type= 6, Freq= 0, CH_1, rank 1
3603 00:42:04.620412 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3604 00:42:04.620503 ==
3605 00:42:04.620581
3606 00:42:04.620636
3607 00:42:04.620708 TX Vref Scan disable
3608 00:42:04.620763 == TX Byte 0 ==
3609 00:42:04.620816 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3610 00:42:04.620869 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3611 00:42:04.620936 == TX Byte 1 ==
3612 00:42:04.620998 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3613 00:42:04.621081 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3614 00:42:04.621169 ==
3615 00:42:04.621231 Dram Type= 6, Freq= 0, CH_1, rank 1
3616 00:42:04.621283 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3617 00:42:04.621336 ==
3618 00:42:04.621388 TX Vref=22, minBit 1, minWin=25, winSum=414
3619 00:42:04.621461 TX Vref=24, minBit 1, minWin=25, winSum=423
3620 00:42:04.621519 TX Vref=26, minBit 1, minWin=25, winSum=423
3621 00:42:04.621572 TX Vref=28, minBit 10, minWin=25, winSum=426
3622 00:42:04.621625 TX Vref=30, minBit 10, minWin=25, winSum=427
3623 00:42:04.621700 TX Vref=32, minBit 0, minWin=26, winSum=424
3624 00:42:04.621754 [TxChooseVref] Worse bit 0, Min win 26, Win sum 424, Final Vref 32
3625 00:42:04.621807
3626 00:42:04.621859 Final TX Range 1 Vref 32
3627 00:42:04.621925
3628 00:42:04.621983 ==
3629 00:42:04.622038 Dram Type= 6, Freq= 0, CH_1, rank 1
3630 00:42:04.622091 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3631 00:42:04.622143 ==
3632 00:42:04.622220
3633 00:42:04.622302
3634 00:42:04.622382 TX Vref Scan disable
3635 00:42:04.622475 == TX Byte 0 ==
3636 00:42:04.622559 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3637 00:42:04.622643 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3638 00:42:04.622735 == TX Byte 1 ==
3639 00:42:04.622818 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3640 00:42:04.622900 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3641 00:42:04.622993
3642 00:42:04.623076 [DATLAT]
3643 00:42:04.623159 Freq=1200, CH1 RK1
3644 00:42:04.623250
3645 00:42:04.623331 DATLAT Default: 0xd
3646 00:42:04.623417 0, 0xFFFF, sum = 0
3647 00:42:04.623482 1, 0xFFFF, sum = 0
3648 00:42:04.623539 2, 0xFFFF, sum = 0
3649 00:42:04.623592 3, 0xFFFF, sum = 0
3650 00:42:04.623645 4, 0xFFFF, sum = 0
3651 00:42:04.623719 5, 0xFFFF, sum = 0
3652 00:42:04.623774 6, 0xFFFF, sum = 0
3653 00:42:04.623826 7, 0xFFFF, sum = 0
3654 00:42:04.623879 8, 0xFFFF, sum = 0
3655 00:42:04.623954 9, 0xFFFF, sum = 0
3656 00:42:04.624012 10, 0xFFFF, sum = 0
3657 00:42:04.624066 11, 0xFFFF, sum = 0
3658 00:42:04.624119 12, 0x0, sum = 1
3659 00:42:04.624185 13, 0x0, sum = 2
3660 00:42:04.624245 14, 0x0, sum = 3
3661 00:42:04.624298 15, 0x0, sum = 4
3662 00:42:04.624351 best_step = 13
3663 00:42:04.624403
3664 00:42:04.624492 ==
3665 00:42:04.624611 Dram Type= 6, Freq= 0, CH_1, rank 1
3666 00:42:04.624678 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3667 00:42:04.624740 ==
3668 00:42:04.624792 RX Vref Scan: 0
3669 00:42:04.624843
3670 00:42:04.624895 RX Vref 0 -> 0, step: 1
3671 00:42:04.624968
3672 00:42:04.625028 RX Delay -13 -> 252, step: 4
3673 00:42:04.625110 iDelay=191, Bit 0, Center 122 (63 ~ 182) 120
3674 00:42:04.625198 iDelay=191, Bit 1, Center 114 (55 ~ 174) 120
3675 00:42:04.625255 iDelay=191, Bit 2, Center 108 (51 ~ 166) 116
3676 00:42:04.625308 iDelay=191, Bit 3, Center 118 (59 ~ 178) 120
3677 00:42:04.625360 iDelay=191, Bit 4, Center 122 (63 ~ 182) 120
3678 00:42:04.625421 iDelay=191, Bit 5, Center 128 (67 ~ 190) 124
3679 00:42:04.625483 iDelay=191, Bit 6, Center 126 (67 ~ 186) 120
3680 00:42:04.625539 iDelay=191, Bit 7, Center 116 (55 ~ 178) 124
3681 00:42:04.625591 iDelay=191, Bit 8, Center 100 (39 ~ 162) 124
3682 00:42:04.625643 iDelay=191, Bit 9, Center 102 (39 ~ 166) 128
3683 00:42:04.625717 iDelay=191, Bit 10, Center 114 (51 ~ 178) 128
3684 00:42:04.625771 iDelay=191, Bit 11, Center 106 (43 ~ 170) 128
3685 00:42:04.625823 iDelay=191, Bit 12, Center 122 (59 ~ 186) 128
3686 00:42:04.625875 iDelay=191, Bit 13, Center 118 (55 ~ 182) 128
3687 00:42:04.625944 iDelay=191, Bit 14, Center 122 (59 ~ 186) 128
3688 00:42:04.626030 iDelay=191, Bit 15, Center 124 (59 ~ 190) 132
3689 00:42:04.626111 ==
3690 00:42:04.626203 Dram Type= 6, Freq= 0, CH_1, rank 1
3691 00:42:04.626287 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3692 00:42:04.626369 ==
3693 00:42:04.626460 DQS Delay:
3694 00:42:04.626544 DQS0 = 0, DQS1 = 0
3695 00:42:04.626625 DQM Delay:
3696 00:42:04.626717 DQM0 = 119, DQM1 = 113
3697 00:42:04.626799 DQ Delay:
3698 00:42:04.626881 DQ0 =122, DQ1 =114, DQ2 =108, DQ3 =118
3699 00:42:04.626973 DQ4 =122, DQ5 =128, DQ6 =126, DQ7 =116
3700 00:42:04.627057 DQ8 =100, DQ9 =102, DQ10 =114, DQ11 =106
3701 00:42:04.627139 DQ12 =122, DQ13 =118, DQ14 =122, DQ15 =124
3702 00:42:04.627230
3703 00:42:04.627311
3704 00:42:04.627394 [DQSOSCAuto] RK1, (LSB)MR18= 0xaef, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 406 ps
3705 00:42:04.627487 CH1 RK1: MR19=403, MR18=AEF
3706 00:42:04.627572 CH1_RK1: MR19=0x403, MR18=0xAEF, DQSOSC=406, MR23=63, INC=39, DEC=26
3707 00:42:04.627656 [RxdqsGatingPostProcess] freq 1200
3708 00:42:04.627748 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3709 00:42:04.627830 best DQS0 dly(2T, 0.5T) = (0, 11)
3710 00:42:04.627915 best DQS1 dly(2T, 0.5T) = (0, 11)
3711 00:42:04.628003 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3712 00:42:04.628086 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3713 00:42:04.628175 best DQS0 dly(2T, 0.5T) = (0, 11)
3714 00:42:04.628260 best DQS1 dly(2T, 0.5T) = (0, 11)
3715 00:42:04.628342 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3716 00:42:04.628430 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3717 00:42:04.628516 Pre-setting of DQS Precalculation
3718 00:42:04.628798 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3719 00:42:04.628862 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3720 00:42:04.628930 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3721 00:42:04.628992
3722 00:42:04.629066
3723 00:42:04.629148 [Calibration Summary] 2400 Mbps
3724 00:42:04.629224 CH 0, Rank 0
3725 00:42:04.629278 SW Impedance : PASS
3726 00:42:04.629331 DUTY Scan : NO K
3727 00:42:04.629383 ZQ Calibration : PASS
3728 00:42:04.629459 Jitter Meter : NO K
3729 00:42:04.629544 CBT Training : PASS
3730 00:42:04.629625 Write leveling : PASS
3731 00:42:04.629717 RX DQS gating : PASS
3732 00:42:04.629800 RX DQ/DQS(RDDQC) : PASS
3733 00:42:04.629881 TX DQ/DQS : PASS
3734 00:42:04.629974 RX DATLAT : PASS
3735 00:42:04.630058 RX DQ/DQS(Engine): PASS
3736 00:42:04.630140 TX OE : NO K
3737 00:42:04.630232 All Pass.
3738 00:42:04.630314
3739 00:42:04.630395 CH 0, Rank 1
3740 00:42:04.630488 SW Impedance : PASS
3741 00:42:04.630571 DUTY Scan : NO K
3742 00:42:04.630653 ZQ Calibration : PASS
3743 00:42:04.630746 Jitter Meter : NO K
3744 00:42:04.630828 CBT Training : PASS
3745 00:42:04.630911 Write leveling : PASS
3746 00:42:04.631000 RX DQS gating : PASS
3747 00:42:04.631084 RX DQ/DQS(RDDQC) : PASS
3748 00:42:04.631171 TX DQ/DQS : PASS
3749 00:42:04.631258 RX DATLAT : PASS
3750 00:42:04.631339 RX DQ/DQS(Engine): PASS
3751 00:42:04.631428 TX OE : NO K
3752 00:42:04.631514 All Pass.
3753 00:42:04.631595
3754 00:42:04.631683 CH 1, Rank 0
3755 00:42:04.631768 SW Impedance : PASS
3756 00:42:04.631850 DUTY Scan : NO K
3757 00:42:04.631939 ZQ Calibration : PASS
3758 00:42:04.632025 Jitter Meter : NO K
3759 00:42:04.632107 CBT Training : PASS
3760 00:42:04.632197 Write leveling : PASS
3761 00:42:04.632280 RX DQS gating : PASS
3762 00:42:04.632361 RX DQ/DQS(RDDQC) : PASS
3763 00:42:04.632452 TX DQ/DQS : PASS
3764 00:42:04.632538 RX DATLAT : PASS
3765 00:42:04.632627 RX DQ/DQS(Engine): PASS
3766 00:42:04.632720 TX OE : NO K
3767 00:42:04.632803 All Pass.
3768 00:42:04.632884
3769 00:42:04.632974 CH 1, Rank 1
3770 00:42:04.633058 SW Impedance : PASS
3771 00:42:04.633140 DUTY Scan : NO K
3772 00:42:04.633232 ZQ Calibration : PASS
3773 00:42:04.633317 Jitter Meter : NO K
3774 00:42:04.633403 CBT Training : PASS
3775 00:42:04.633495 Write leveling : PASS
3776 00:42:04.633579 RX DQS gating : PASS
3777 00:42:04.633663 RX DQ/DQS(RDDQC) : PASS
3778 00:42:04.633752 TX DQ/DQS : PASS
3779 00:42:04.633834 RX DATLAT : PASS
3780 00:42:04.633921 RX DQ/DQS(Engine): PASS
3781 00:42:04.634009 TX OE : NO K
3782 00:42:04.634092 All Pass.
3783 00:42:04.634181
3784 00:42:04.634266 DramC Write-DBI off
3785 00:42:04.634348 PER_BANK_REFRESH: Hybrid Mode
3786 00:42:04.634437 TX_TRACKING: ON
3787 00:42:04.634525 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3788 00:42:04.634609 [FAST_K] Save calibration result to emmc
3789 00:42:04.634700 dramc_set_vcore_voltage set vcore to 650000
3790 00:42:04.634784 Read voltage for 600, 5
3791 00:42:04.634865 Vio18 = 0
3792 00:42:04.634956 Vcore = 650000
3793 00:42:04.635039 Vdram = 0
3794 00:42:04.635121 Vddq = 0
3795 00:42:04.635212 Vmddr = 0
3796 00:42:04.635295 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3797 00:42:04.635378 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3798 00:42:04.635469 MEM_TYPE=3, freq_sel=19
3799 00:42:04.635554 sv_algorithm_assistance_LP4_1600
3800 00:42:04.635636 ============ PULL DRAM RESETB DOWN ============
3801 00:42:04.635728 ========== PULL DRAM RESETB DOWN end =========
3802 00:42:04.635812 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3803 00:42:04.635893 ===================================
3804 00:42:04.635987 LPDDR4 DRAM CONFIGURATION
3805 00:42:04.636072 ===================================
3806 00:42:04.636154 EX_ROW_EN[0] = 0x0
3807 00:42:04.636245 EX_ROW_EN[1] = 0x0
3808 00:42:04.636327 LP4Y_EN = 0x0
3809 00:42:04.636409 WORK_FSP = 0x0
3810 00:42:04.636501 WL = 0x2
3811 00:42:04.636603 RL = 0x2
3812 00:42:04.636683 BL = 0x2
3813 00:42:04.636742 RPST = 0x0
3814 00:42:04.636794 RD_PRE = 0x0
3815 00:42:04.636846 WR_PRE = 0x1
3816 00:42:04.636897 WR_PST = 0x0
3817 00:42:04.636969 DBI_WR = 0x0
3818 00:42:04.637028 DBI_RD = 0x0
3819 00:42:04.637109 OTF = 0x1
3820 00:42:04.637196 ===================================
3821 00:42:04.637254 ===================================
3822 00:42:04.637307 ANA top config
3823 00:42:04.637359 ===================================
3824 00:42:04.637417 DLL_ASYNC_EN = 0
3825 00:42:04.637506 ALL_SLAVE_EN = 1
3826 00:42:04.637564 NEW_RANK_MODE = 1
3827 00:42:04.637618 DLL_IDLE_MODE = 1
3828 00:42:04.637683 LP45_APHY_COMB_EN = 1
3829 00:42:04.637741 TX_ODT_DIS = 1
3830 00:42:04.637794 NEW_8X_MODE = 1
3831 00:42:04.637847 ===================================
3832 00:42:04.637899 ===================================
3833 00:42:04.637972 data_rate = 1200
3834 00:42:04.638027 CKR = 1
3835 00:42:04.638080 DQ_P2S_RATIO = 8
3836 00:42:04.638132 ===================================
3837 00:42:04.638206 CA_P2S_RATIO = 8
3838 00:42:04.638259 DQ_CA_OPEN = 0
3839 00:42:04.638312 DQ_SEMI_OPEN = 0
3840 00:42:04.638364 CA_SEMI_OPEN = 0
3841 00:42:04.638424 CA_FULL_RATE = 0
3842 00:42:04.638487 DQ_CKDIV4_EN = 1
3843 00:42:04.638542 CA_CKDIV4_EN = 1
3844 00:42:04.638595 CA_PREDIV_EN = 0
3845 00:42:04.638648 PH8_DLY = 0
3846 00:42:04.638720 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3847 00:42:04.638774 DQ_AAMCK_DIV = 4
3848 00:42:04.638827 CA_AAMCK_DIV = 4
3849 00:42:04.638878 CA_ADMCK_DIV = 4
3850 00:42:04.638952 DQ_TRACK_CA_EN = 0
3851 00:42:04.639037 CA_PICK = 600
3852 00:42:04.639119 CA_MCKIO = 600
3853 00:42:04.639211 MCKIO_SEMI = 0
3854 00:42:04.639294 PLL_FREQ = 2288
3855 00:42:04.639376 DQ_UI_PI_RATIO = 32
3856 00:42:04.639468 CA_UI_PI_RATIO = 0
3857 00:42:04.639552 ===================================
3858 00:42:04.639634 ===================================
3859 00:42:04.639726 memory_type:LPDDR4
3860 00:42:04.639809 GP_NUM : 10
3861 00:42:04.639891 SRAM_EN : 1
3862 00:42:04.639983 MD32_EN : 0
3863 00:42:04.640067 ===================================
3864 00:42:04.640149 [ANA_INIT] >>>>>>>>>>>>>>
3865 00:42:04.640449 <<<<<< [CONFIGURE PHASE]: ANA_TX
3866 00:42:04.640542 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3867 00:42:04.640650 ===================================
3868 00:42:04.640726 data_rate = 1200,PCW = 0X5800
3869 00:42:04.640780 ===================================
3870 00:42:04.640833 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3871 00:42:04.640887 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3872 00:42:04.640961 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3873 00:42:04.641021 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3874 00:42:04.641104 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3875 00:42:04.641192 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3876 00:42:04.641252 [ANA_INIT] flow start
3877 00:42:04.641304 [ANA_INIT] PLL >>>>>>>>
3878 00:42:04.641356 [ANA_INIT] PLL <<<<<<<<
3879 00:42:04.641412 [ANA_INIT] MIDPI >>>>>>>>
3880 00:42:04.641501 [ANA_INIT] MIDPI <<<<<<<<
3881 00:42:04.641559 [ANA_INIT] DLL >>>>>>>>
3882 00:42:04.641612 [ANA_INIT] flow end
3883 00:42:04.641675 ============ LP4 DIFF to SE enter ============
3884 00:42:04.641737 ============ LP4 DIFF to SE exit ============
3885 00:42:04.641790 [ANA_INIT] <<<<<<<<<<<<<
3886 00:42:04.641856 [Flow] Enable top DCM control >>>>>
3887 00:42:04.644461 [Flow] Enable top DCM control <<<<<
3888 00:42:04.647701 Enable DLL master slave shuffle
3889 00:42:04.654603 ==============================================================
3890 00:42:04.654731 Gating Mode config
3891 00:42:04.661215 ==============================================================
3892 00:42:04.664307 Config description:
3893 00:42:04.674593 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3894 00:42:04.681295 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3895 00:42:04.684350 SELPH_MODE 0: By rank 1: By Phase
3896 00:42:04.691251 ==============================================================
3897 00:42:04.694316 GAT_TRACK_EN = 1
3898 00:42:04.694429 RX_GATING_MODE = 2
3899 00:42:04.697469 RX_GATING_TRACK_MODE = 2
3900 00:42:04.701078 SELPH_MODE = 1
3901 00:42:04.704224 PICG_EARLY_EN = 1
3902 00:42:04.707677 VALID_LAT_VALUE = 1
3903 00:42:04.714483 ==============================================================
3904 00:42:04.717789 Enter into Gating configuration >>>>
3905 00:42:04.720852 Exit from Gating configuration <<<<
3906 00:42:04.723981 Enter into DVFS_PRE_config >>>>>
3907 00:42:04.734412 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3908 00:42:04.737655 Exit from DVFS_PRE_config <<<<<
3909 00:42:04.741053 Enter into PICG configuration >>>>
3910 00:42:04.744248 Exit from PICG configuration <<<<
3911 00:42:04.747632 [RX_INPUT] configuration >>>>>
3912 00:42:04.750854 [RX_INPUT] configuration <<<<<
3913 00:42:04.754122 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3914 00:42:04.760796 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3915 00:42:04.767573 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3916 00:42:04.770658 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3917 00:42:04.777369 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3918 00:42:04.783788 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3919 00:42:04.787318 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3920 00:42:04.790742 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3921 00:42:04.797210 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3922 00:42:04.800703 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3923 00:42:04.804008 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3924 00:42:04.810541 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3925 00:42:04.814143 ===================================
3926 00:42:04.814226 LPDDR4 DRAM CONFIGURATION
3927 00:42:04.817218 ===================================
3928 00:42:04.820960 EX_ROW_EN[0] = 0x0
3929 00:42:04.824038 EX_ROW_EN[1] = 0x0
3930 00:42:04.824142 LP4Y_EN = 0x0
3931 00:42:04.827459 WORK_FSP = 0x0
3932 00:42:04.827560 WL = 0x2
3933 00:42:04.830618 RL = 0x2
3934 00:42:04.830693 BL = 0x2
3935 00:42:04.833763 RPST = 0x0
3936 00:42:04.833863 RD_PRE = 0x0
3937 00:42:04.837446 WR_PRE = 0x1
3938 00:42:04.837545 WR_PST = 0x0
3939 00:42:04.840598 DBI_WR = 0x0
3940 00:42:04.840688 DBI_RD = 0x0
3941 00:42:04.843969 OTF = 0x1
3942 00:42:04.847223 ===================================
3943 00:42:04.850474 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3944 00:42:04.853873 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3945 00:42:04.857801 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3946 00:42:04.860569 ===================================
3947 00:42:04.864156 LPDDR4 DRAM CONFIGURATION
3948 00:42:04.867264 ===================================
3949 00:42:04.870639 EX_ROW_EN[0] = 0x10
3950 00:42:04.870749 EX_ROW_EN[1] = 0x0
3951 00:42:04.873707 LP4Y_EN = 0x0
3952 00:42:04.873787 WORK_FSP = 0x0
3953 00:42:04.877323 WL = 0x2
3954 00:42:04.877401 RL = 0x2
3955 00:42:04.880484 BL = 0x2
3956 00:42:04.883785 RPST = 0x0
3957 00:42:04.883889 RD_PRE = 0x0
3958 00:42:04.886982 WR_PRE = 0x1
3959 00:42:04.887056 WR_PST = 0x0
3960 00:42:04.890443 DBI_WR = 0x0
3961 00:42:04.890555 DBI_RD = 0x0
3962 00:42:04.893692 OTF = 0x1
3963 00:42:04.896922 ===================================
3964 00:42:04.900219 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3965 00:42:04.905690 nWR fixed to 30
3966 00:42:04.909205 [ModeRegInit_LP4] CH0 RK0
3967 00:42:04.909309 [ModeRegInit_LP4] CH0 RK1
3968 00:42:04.912449 [ModeRegInit_LP4] CH1 RK0
3969 00:42:04.916055 [ModeRegInit_LP4] CH1 RK1
3970 00:42:04.916157 match AC timing 17
3971 00:42:04.922537 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3972 00:42:04.926131 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3973 00:42:04.929365 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3974 00:42:04.935983 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3975 00:42:04.939130 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3976 00:42:04.939207 ==
3977 00:42:04.942836 Dram Type= 6, Freq= 0, CH_0, rank 0
3978 00:42:04.945724 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3979 00:42:04.945812 ==
3980 00:42:04.952554 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3981 00:42:04.959160 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3982 00:42:04.962160 [CA 0] Center 36 (6~67) winsize 62
3983 00:42:04.965554 [CA 1] Center 36 (6~67) winsize 62
3984 00:42:04.968769 [CA 2] Center 34 (4~65) winsize 62
3985 00:42:04.972010 [CA 3] Center 34 (3~65) winsize 63
3986 00:42:04.975615 [CA 4] Center 34 (3~65) winsize 63
3987 00:42:04.979225 [CA 5] Center 33 (2~64) winsize 63
3988 00:42:04.979300
3989 00:42:04.982230 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3990 00:42:04.982302
3991 00:42:04.985541 [CATrainingPosCal] consider 1 rank data
3992 00:42:04.988870 u2DelayCellTimex100 = 270/100 ps
3993 00:42:04.992003 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3994 00:42:04.995320 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3995 00:42:04.998428 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3996 00:42:05.001866 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3997 00:42:05.005236 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
3998 00:42:05.011663 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
3999 00:42:05.011770
4000 00:42:05.015335 CA PerBit enable=1, Macro0, CA PI delay=33
4001 00:42:05.015432
4002 00:42:05.018604 [CBTSetCACLKResult] CA Dly = 33
4003 00:42:05.018707 CS Dly: 5 (0~36)
4004 00:42:05.018798 ==
4005 00:42:05.021745 Dram Type= 6, Freq= 0, CH_0, rank 1
4006 00:42:05.025073 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4007 00:42:05.028394 ==
4008 00:42:05.031758 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4009 00:42:05.038502 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4010 00:42:05.041988 [CA 0] Center 36 (6~67) winsize 62
4011 00:42:05.045217 [CA 1] Center 36 (6~67) winsize 62
4012 00:42:05.048476 [CA 2] Center 34 (4~65) winsize 62
4013 00:42:05.051808 [CA 3] Center 34 (4~65) winsize 62
4014 00:42:05.055126 [CA 4] Center 33 (3~64) winsize 62
4015 00:42:05.058310 [CA 5] Center 33 (3~64) winsize 62
4016 00:42:05.058412
4017 00:42:05.062062 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4018 00:42:05.062161
4019 00:42:05.065023 [CATrainingPosCal] consider 2 rank data
4020 00:42:05.068217 u2DelayCellTimex100 = 270/100 ps
4021 00:42:05.072007 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
4022 00:42:05.075366 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
4023 00:42:05.078539 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4024 00:42:05.081675 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4025 00:42:05.088653 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4026 00:42:05.091801 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4027 00:42:05.091882
4028 00:42:05.095203 CA PerBit enable=1, Macro0, CA PI delay=33
4029 00:42:05.095304
4030 00:42:05.098523 [CBTSetCACLKResult] CA Dly = 33
4031 00:42:05.098623 CS Dly: 5 (0~37)
4032 00:42:05.098723
4033 00:42:05.101613 ----->DramcWriteLeveling(PI) begin...
4034 00:42:05.101703 ==
4035 00:42:05.105185 Dram Type= 6, Freq= 0, CH_0, rank 0
4036 00:42:05.111865 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4037 00:42:05.111986 ==
4038 00:42:05.115236 Write leveling (Byte 0): 31 => 31
4039 00:42:05.115336 Write leveling (Byte 1): 31 => 31
4040 00:42:05.118652 DramcWriteLeveling(PI) end<-----
4041 00:42:05.118736
4042 00:42:05.121956 ==
4043 00:42:05.122031 Dram Type= 6, Freq= 0, CH_0, rank 0
4044 00:42:05.128383 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4045 00:42:05.128499 ==
4046 00:42:05.131577 [Gating] SW mode calibration
4047 00:42:05.138149 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4048 00:42:05.141637 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4049 00:42:05.148663 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4050 00:42:05.151607 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4051 00:42:05.154987 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4052 00:42:05.161575 0 9 12 | B1->B0 | 3434 2a2a | 0 0 | (0 0) (1 0)
4053 00:42:05.164959 0 9 16 | B1->B0 | 2c2c 2323 | 0 0 | (0 0) (0 0)
4054 00:42:05.168291 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4055 00:42:05.171525 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4056 00:42:05.178585 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4057 00:42:05.181650 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4058 00:42:05.184806 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4059 00:42:05.191764 0 10 8 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
4060 00:42:05.195233 0 10 12 | B1->B0 | 2929 3e3d | 0 1 | (0 0) (0 0)
4061 00:42:05.198517 0 10 16 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
4062 00:42:05.205063 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4063 00:42:05.208268 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4064 00:42:05.211519 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4065 00:42:05.218260 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4066 00:42:05.221964 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4067 00:42:05.224828 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4068 00:42:05.231623 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4069 00:42:05.235185 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4070 00:42:05.238415 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4071 00:42:05.245231 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4072 00:42:05.248293 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4073 00:42:05.251720 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4074 00:42:05.258665 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4075 00:42:05.261537 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4076 00:42:05.264964 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4077 00:42:05.271469 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4078 00:42:05.274826 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4079 00:42:05.278139 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4080 00:42:05.284833 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4081 00:42:05.288169 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4082 00:42:05.291306 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4083 00:42:05.295131 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4084 00:42:05.301472 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4085 00:42:05.304862 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4086 00:42:05.308176 Total UI for P1: 0, mck2ui 16
4087 00:42:05.311438 best dqsien dly found for B0: ( 0, 13, 12)
4088 00:42:05.314798 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4089 00:42:05.318291 Total UI for P1: 0, mck2ui 16
4090 00:42:05.321491 best dqsien dly found for B1: ( 0, 13, 14)
4091 00:42:05.324632 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4092 00:42:05.331145 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4093 00:42:05.331258
4094 00:42:05.334502 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4095 00:42:05.337696 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4096 00:42:05.341225 [Gating] SW calibration Done
4097 00:42:05.341311 ==
4098 00:42:05.344465 Dram Type= 6, Freq= 0, CH_0, rank 0
4099 00:42:05.347731 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4100 00:42:05.347842 ==
4101 00:42:05.351464 RX Vref Scan: 0
4102 00:42:05.351577
4103 00:42:05.351671 RX Vref 0 -> 0, step: 1
4104 00:42:05.351760
4105 00:42:05.354907 RX Delay -230 -> 252, step: 16
4106 00:42:05.357904 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4107 00:42:05.364386 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4108 00:42:05.367800 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4109 00:42:05.371171 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4110 00:42:05.374457 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4111 00:42:05.378314 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4112 00:42:05.384816 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4113 00:42:05.388301 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4114 00:42:05.391440 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4115 00:42:05.394594 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4116 00:42:05.398279 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4117 00:42:05.404799 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4118 00:42:05.408127 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4119 00:42:05.411358 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4120 00:42:05.414703 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4121 00:42:05.421051 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4122 00:42:05.421142 ==
4123 00:42:05.424735 Dram Type= 6, Freq= 0, CH_0, rank 0
4124 00:42:05.427992 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4125 00:42:05.428078 ==
4126 00:42:05.428146 DQS Delay:
4127 00:42:05.431216 DQS0 = 0, DQS1 = 0
4128 00:42:05.431301 DQM Delay:
4129 00:42:05.434454 DQM0 = 51, DQM1 = 36
4130 00:42:05.434540 DQ Delay:
4131 00:42:05.437831 DQ0 =49, DQ1 =57, DQ2 =41, DQ3 =49
4132 00:42:05.441279 DQ4 =57, DQ5 =41, DQ6 =57, DQ7 =57
4133 00:42:05.444453 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =25
4134 00:42:05.448196 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =41
4135 00:42:05.448286
4136 00:42:05.448352
4137 00:42:05.448413 ==
4138 00:42:05.451139 Dram Type= 6, Freq= 0, CH_0, rank 0
4139 00:42:05.454719 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4140 00:42:05.454806 ==
4141 00:42:05.457854
4142 00:42:05.457938
4143 00:42:05.458005 TX Vref Scan disable
4144 00:42:05.461155 == TX Byte 0 ==
4145 00:42:05.464476 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4146 00:42:05.468096 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4147 00:42:05.471152 == TX Byte 1 ==
4148 00:42:05.474675 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4149 00:42:05.478200 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4150 00:42:05.481053 ==
4151 00:42:05.481137 Dram Type= 6, Freq= 0, CH_0, rank 0
4152 00:42:05.487719 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4153 00:42:05.487835 ==
4154 00:42:05.487929
4155 00:42:05.488017
4156 00:42:05.490760 TX Vref Scan disable
4157 00:42:05.490874 == TX Byte 0 ==
4158 00:42:05.497386 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4159 00:42:05.501054 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4160 00:42:05.501133 == TX Byte 1 ==
4161 00:42:05.507594 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4162 00:42:05.510867 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4163 00:42:05.510946
4164 00:42:05.511010 [DATLAT]
4165 00:42:05.514073 Freq=600, CH0 RK0
4166 00:42:05.514174
4167 00:42:05.514265 DATLAT Default: 0x9
4168 00:42:05.517595 0, 0xFFFF, sum = 0
4169 00:42:05.517682 1, 0xFFFF, sum = 0
4170 00:42:05.520880 2, 0xFFFF, sum = 0
4171 00:42:05.520967 3, 0xFFFF, sum = 0
4172 00:42:05.524102 4, 0xFFFF, sum = 0
4173 00:42:05.524189 5, 0xFFFF, sum = 0
4174 00:42:05.527796 6, 0xFFFF, sum = 0
4175 00:42:05.531041 7, 0xFFFF, sum = 0
4176 00:42:05.531128 8, 0x0, sum = 1
4177 00:42:05.531197 9, 0x0, sum = 2
4178 00:42:05.534272 10, 0x0, sum = 3
4179 00:42:05.534385 11, 0x0, sum = 4
4180 00:42:05.537562 best_step = 9
4181 00:42:05.537647
4182 00:42:05.537723 ==
4183 00:42:05.540736 Dram Type= 6, Freq= 0, CH_0, rank 0
4184 00:42:05.544510 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4185 00:42:05.544648 ==
4186 00:42:05.547554 RX Vref Scan: 1
4187 00:42:05.547639
4188 00:42:05.547705 RX Vref 0 -> 0, step: 1
4189 00:42:05.547766
4190 00:42:05.550763 RX Delay -179 -> 252, step: 8
4191 00:42:05.550848
4192 00:42:05.553948 Set Vref, RX VrefLevel [Byte0]: 61
4193 00:42:05.557336 [Byte1]: 49
4194 00:42:05.561413
4195 00:42:05.561498 Final RX Vref Byte 0 = 61 to rank0
4196 00:42:05.564474 Final RX Vref Byte 1 = 49 to rank0
4197 00:42:05.567838 Final RX Vref Byte 0 = 61 to rank1
4198 00:42:05.571151 Final RX Vref Byte 1 = 49 to rank1==
4199 00:42:05.574727 Dram Type= 6, Freq= 0, CH_0, rank 0
4200 00:42:05.581289 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4201 00:42:05.581384 ==
4202 00:42:05.581453 DQS Delay:
4203 00:42:05.581515 DQS0 = 0, DQS1 = 0
4204 00:42:05.584515 DQM Delay:
4205 00:42:05.584644 DQM0 = 49, DQM1 = 37
4206 00:42:05.588051 DQ Delay:
4207 00:42:05.591491 DQ0 =48, DQ1 =48, DQ2 =48, DQ3 =44
4208 00:42:05.594726 DQ4 =52, DQ5 =40, DQ6 =60, DQ7 =56
4209 00:42:05.594816 DQ8 =32, DQ9 =20, DQ10 =36, DQ11 =32
4210 00:42:05.601289 DQ12 =44, DQ13 =40, DQ14 =48, DQ15 =44
4211 00:42:05.601377
4212 00:42:05.601444
4213 00:42:05.607719 [DQSOSCAuto] RK0, (LSB)MR18= 0x665f, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 390 ps
4214 00:42:05.610996 CH0 RK0: MR19=808, MR18=665F
4215 00:42:05.617663 CH0_RK0: MR19=0x808, MR18=0x665F, DQSOSC=390, MR23=63, INC=172, DEC=114
4216 00:42:05.617761
4217 00:42:05.621196 ----->DramcWriteLeveling(PI) begin...
4218 00:42:05.621286 ==
4219 00:42:05.624328 Dram Type= 6, Freq= 0, CH_0, rank 1
4220 00:42:05.628064 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4221 00:42:05.628154 ==
4222 00:42:05.631108 Write leveling (Byte 0): 33 => 33
4223 00:42:05.634339 Write leveling (Byte 1): 33 => 33
4224 00:42:05.637746 DramcWriteLeveling(PI) end<-----
4225 00:42:05.637835
4226 00:42:05.637902 ==
4227 00:42:05.641180 Dram Type= 6, Freq= 0, CH_0, rank 1
4228 00:42:05.644595 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4229 00:42:05.644683 ==
4230 00:42:05.647901 [Gating] SW mode calibration
4231 00:42:05.654338 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4232 00:42:05.661104 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4233 00:42:05.664495 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4234 00:42:05.667581 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4235 00:42:05.674344 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4236 00:42:05.677516 0 9 12 | B1->B0 | 3333 2e2e | 1 1 | (1 0) (1 1)
4237 00:42:05.681197 0 9 16 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
4238 00:42:05.687479 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4239 00:42:05.691107 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4240 00:42:05.694137 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4241 00:42:05.701221 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4242 00:42:05.704457 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4243 00:42:05.707693 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4244 00:42:05.714271 0 10 12 | B1->B0 | 2f2f 3636 | 1 0 | (0 0) (0 0)
4245 00:42:05.717755 0 10 16 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
4246 00:42:05.720828 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4247 00:42:05.727752 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4248 00:42:05.731056 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4249 00:42:05.734106 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4250 00:42:05.740888 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4251 00:42:05.744157 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4252 00:42:05.747459 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4253 00:42:05.754022 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4254 00:42:05.757814 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4255 00:42:05.760815 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4256 00:42:05.764103 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4257 00:42:05.771082 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4258 00:42:05.774361 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4259 00:42:05.777466 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4260 00:42:05.783999 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4261 00:42:05.787863 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4262 00:42:05.790695 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4263 00:42:05.797849 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4264 00:42:05.800693 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4265 00:42:05.804320 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4266 00:42:05.810728 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4267 00:42:05.814344 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4268 00:42:05.817609 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4269 00:42:05.824044 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4270 00:42:05.824136 Total UI for P1: 0, mck2ui 16
4271 00:42:05.830844 best dqsien dly found for B0: ( 0, 13, 12)
4272 00:42:05.834179 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4273 00:42:05.837466 Total UI for P1: 0, mck2ui 16
4274 00:42:05.840749 best dqsien dly found for B1: ( 0, 13, 14)
4275 00:42:05.844003 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4276 00:42:05.847390 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4277 00:42:05.847477
4278 00:42:05.850557 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4279 00:42:05.854356 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4280 00:42:05.857673 [Gating] SW calibration Done
4281 00:42:05.857759 ==
4282 00:42:05.860573 Dram Type= 6, Freq= 0, CH_0, rank 1
4283 00:42:05.864177 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4284 00:42:05.867489 ==
4285 00:42:05.867575 RX Vref Scan: 0
4286 00:42:05.867642
4287 00:42:05.870835 RX Vref 0 -> 0, step: 1
4288 00:42:05.870919
4289 00:42:05.874231 RX Delay -230 -> 252, step: 16
4290 00:42:05.877561 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4291 00:42:05.880762 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4292 00:42:05.884056 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4293 00:42:05.887442 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4294 00:42:05.893911 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4295 00:42:05.897408 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4296 00:42:05.900690 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4297 00:42:05.903761 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4298 00:42:05.910693 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4299 00:42:05.914052 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4300 00:42:05.917367 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4301 00:42:05.920332 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4302 00:42:05.926872 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4303 00:42:05.930447 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4304 00:42:05.933803 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4305 00:42:05.937148 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4306 00:42:05.937304 ==
4307 00:42:05.940073 Dram Type= 6, Freq= 0, CH_0, rank 1
4308 00:42:05.946916 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4309 00:42:05.947004 ==
4310 00:42:05.947073 DQS Delay:
4311 00:42:05.950262 DQS0 = 0, DQS1 = 0
4312 00:42:05.950342 DQM Delay:
4313 00:42:05.950408 DQM0 = 48, DQM1 = 42
4314 00:42:05.953767 DQ Delay:
4315 00:42:05.957084 DQ0 =41, DQ1 =57, DQ2 =41, DQ3 =41
4316 00:42:05.960279 DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =57
4317 00:42:05.963820 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =41
4318 00:42:05.966714 DQ12 =41, DQ13 =49, DQ14 =49, DQ15 =49
4319 00:42:05.966799
4320 00:42:05.966866
4321 00:42:05.966928 ==
4322 00:42:05.970219 Dram Type= 6, Freq= 0, CH_0, rank 1
4323 00:42:05.973521 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4324 00:42:05.973607 ==
4325 00:42:05.973673
4326 00:42:05.973734
4327 00:42:05.976881 TX Vref Scan disable
4328 00:42:05.976966 == TX Byte 0 ==
4329 00:42:05.983398 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4330 00:42:05.986847 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4331 00:42:05.990262 == TX Byte 1 ==
4332 00:42:05.993530 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4333 00:42:05.996753 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4334 00:42:05.996838 ==
4335 00:42:06.000389 Dram Type= 6, Freq= 0, CH_0, rank 1
4336 00:42:06.003493 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4337 00:42:06.003579 ==
4338 00:42:06.006655
4339 00:42:06.006739
4340 00:42:06.006805 TX Vref Scan disable
4341 00:42:06.010317 == TX Byte 0 ==
4342 00:42:06.013709 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4343 00:42:06.020175 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4344 00:42:06.020261 == TX Byte 1 ==
4345 00:42:06.023397 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4346 00:42:06.030162 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4347 00:42:06.030249
4348 00:42:06.030316 [DATLAT]
4349 00:42:06.030376 Freq=600, CH0 RK1
4350 00:42:06.030436
4351 00:42:06.033777 DATLAT Default: 0x9
4352 00:42:06.033861 0, 0xFFFF, sum = 0
4353 00:42:06.036679 1, 0xFFFF, sum = 0
4354 00:42:06.036765 2, 0xFFFF, sum = 0
4355 00:42:06.040285 3, 0xFFFF, sum = 0
4356 00:42:06.043593 4, 0xFFFF, sum = 0
4357 00:42:06.043679 5, 0xFFFF, sum = 0
4358 00:42:06.046775 6, 0xFFFF, sum = 0
4359 00:42:06.046861 7, 0xFFFF, sum = 0
4360 00:42:06.049987 8, 0x0, sum = 1
4361 00:42:06.050072 9, 0x0, sum = 2
4362 00:42:06.050138 10, 0x0, sum = 3
4363 00:42:06.053675 11, 0x0, sum = 4
4364 00:42:06.053760 best_step = 9
4365 00:42:06.053824
4366 00:42:06.053884 ==
4367 00:42:06.056841 Dram Type= 6, Freq= 0, CH_0, rank 1
4368 00:42:06.063540 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4369 00:42:06.063624 ==
4370 00:42:06.063689 RX Vref Scan: 0
4371 00:42:06.063750
4372 00:42:06.066743 RX Vref 0 -> 0, step: 1
4373 00:42:06.066826
4374 00:42:06.069980 RX Delay -163 -> 252, step: 8
4375 00:42:06.073560 iDelay=205, Bit 0, Center 48 (-99 ~ 196) 296
4376 00:42:06.080104 iDelay=205, Bit 1, Center 48 (-99 ~ 196) 296
4377 00:42:06.083502 iDelay=205, Bit 2, Center 48 (-99 ~ 196) 296
4378 00:42:06.086979 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4379 00:42:06.090021 iDelay=205, Bit 4, Center 48 (-99 ~ 196) 296
4380 00:42:06.093735 iDelay=205, Bit 5, Center 40 (-107 ~ 188) 296
4381 00:42:06.100277 iDelay=205, Bit 6, Center 56 (-91 ~ 204) 296
4382 00:42:06.103096 iDelay=205, Bit 7, Center 56 (-91 ~ 204) 296
4383 00:42:06.106806 iDelay=205, Bit 8, Center 36 (-107 ~ 180) 288
4384 00:42:06.110069 iDelay=205, Bit 9, Center 28 (-115 ~ 172) 288
4385 00:42:06.113102 iDelay=205, Bit 10, Center 40 (-107 ~ 188) 296
4386 00:42:06.119815 iDelay=205, Bit 11, Center 32 (-115 ~ 180) 296
4387 00:42:06.123207 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4388 00:42:06.126659 iDelay=205, Bit 13, Center 44 (-99 ~ 188) 288
4389 00:42:06.130056 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4390 00:42:06.133476 iDelay=205, Bit 15, Center 48 (-91 ~ 188) 280
4391 00:42:06.136429 ==
4392 00:42:06.139796 Dram Type= 6, Freq= 0, CH_0, rank 1
4393 00:42:06.143481 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4394 00:42:06.143564 ==
4395 00:42:06.143629 DQS Delay:
4396 00:42:06.146698 DQS0 = 0, DQS1 = 0
4397 00:42:06.146780 DQM Delay:
4398 00:42:06.149999 DQM0 = 48, DQM1 = 41
4399 00:42:06.150080 DQ Delay:
4400 00:42:06.153350 DQ0 =48, DQ1 =48, DQ2 =48, DQ3 =44
4401 00:42:06.156357 DQ4 =48, DQ5 =40, DQ6 =56, DQ7 =56
4402 00:42:06.160181 DQ8 =36, DQ9 =28, DQ10 =40, DQ11 =32
4403 00:42:06.163525 DQ12 =48, DQ13 =44, DQ14 =52, DQ15 =48
4404 00:42:06.163608
4405 00:42:06.163672
4406 00:42:06.170128 [DQSOSCAuto] RK1, (LSB)MR18= 0x6532, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 390 ps
4407 00:42:06.173349 CH0 RK1: MR19=808, MR18=6532
4408 00:42:06.180098 CH0_RK1: MR19=0x808, MR18=0x6532, DQSOSC=390, MR23=63, INC=172, DEC=114
4409 00:42:06.183467 [RxdqsGatingPostProcess] freq 600
4410 00:42:06.186722 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4411 00:42:06.190000 Pre-setting of DQS Precalculation
4412 00:42:06.196531 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4413 00:42:06.196659 ==
4414 00:42:06.200022 Dram Type= 6, Freq= 0, CH_1, rank 0
4415 00:42:06.203234 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4416 00:42:06.203317 ==
4417 00:42:06.210026 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4418 00:42:06.216661 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4419 00:42:06.219971 [CA 0] Center 35 (5~66) winsize 62
4420 00:42:06.223285 [CA 1] Center 35 (5~66) winsize 62
4421 00:42:06.226710 [CA 2] Center 34 (3~65) winsize 63
4422 00:42:06.230207 [CA 3] Center 33 (3~64) winsize 62
4423 00:42:06.233517 [CA 4] Center 33 (3~64) winsize 62
4424 00:42:06.233602 [CA 5] Center 33 (3~64) winsize 62
4425 00:42:06.236781
4426 00:42:06.240420 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4427 00:42:06.240506
4428 00:42:06.243563 [CATrainingPosCal] consider 1 rank data
4429 00:42:06.246917 u2DelayCellTimex100 = 270/100 ps
4430 00:42:06.249989 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4431 00:42:06.253358 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4432 00:42:06.256863 CA2 delay=34 (3~65),Diff = 1 PI (9 cell)
4433 00:42:06.260449 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4434 00:42:06.263721 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4435 00:42:06.266975 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4436 00:42:06.267060
4437 00:42:06.270117 CA PerBit enable=1, Macro0, CA PI delay=33
4438 00:42:06.270201
4439 00:42:06.273288 [CBTSetCACLKResult] CA Dly = 33
4440 00:42:06.276966 CS Dly: 4 (0~35)
4441 00:42:06.277051 ==
4442 00:42:06.279860 Dram Type= 6, Freq= 0, CH_1, rank 1
4443 00:42:06.283563 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4444 00:42:06.283649 ==
4445 00:42:06.289920 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4446 00:42:06.296866 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4447 00:42:06.299944 [CA 0] Center 35 (5~66) winsize 62
4448 00:42:06.303478 [CA 1] Center 35 (5~66) winsize 62
4449 00:42:06.306677 [CA 2] Center 34 (4~65) winsize 62
4450 00:42:06.309994 [CA 3] Center 34 (4~65) winsize 62
4451 00:42:06.313519 [CA 4] Center 34 (4~65) winsize 62
4452 00:42:06.316834 [CA 5] Center 34 (4~64) winsize 61
4453 00:42:06.316919
4454 00:42:06.320160 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4455 00:42:06.320245
4456 00:42:06.323290 [CATrainingPosCal] consider 2 rank data
4457 00:42:06.326536 u2DelayCellTimex100 = 270/100 ps
4458 00:42:06.329857 CA0 delay=35 (5~66),Diff = 1 PI (9 cell)
4459 00:42:06.333189 CA1 delay=35 (5~66),Diff = 1 PI (9 cell)
4460 00:42:06.336688 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4461 00:42:06.340039 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
4462 00:42:06.343049 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
4463 00:42:06.346254 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4464 00:42:06.346339
4465 00:42:06.350009 CA PerBit enable=1, Macro0, CA PI delay=34
4466 00:42:06.350111
4467 00:42:06.353442 [CBTSetCACLKResult] CA Dly = 34
4468 00:42:06.356671 CS Dly: 4 (0~36)
4469 00:42:06.356755
4470 00:42:06.359959 ----->DramcWriteLeveling(PI) begin...
4471 00:42:06.360043 ==
4472 00:42:06.363481 Dram Type= 6, Freq= 0, CH_1, rank 0
4473 00:42:06.366745 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4474 00:42:06.366831 ==
4475 00:42:06.370005 Write leveling (Byte 0): 31 => 31
4476 00:42:06.373111 Write leveling (Byte 1): 29 => 29
4477 00:42:06.376484 DramcWriteLeveling(PI) end<-----
4478 00:42:06.376605
4479 00:42:06.376673 ==
4480 00:42:06.379912 Dram Type= 6, Freq= 0, CH_1, rank 0
4481 00:42:06.383196 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4482 00:42:06.383280 ==
4483 00:42:06.386517 [Gating] SW mode calibration
4484 00:42:06.393075 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4485 00:42:06.399573 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4486 00:42:06.402908 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4487 00:42:06.409569 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4488 00:42:06.412780 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
4489 00:42:06.416107 0 9 12 | B1->B0 | 2b2b 2c2c | 0 0 | (0 0) (0 0)
4490 00:42:06.422746 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4491 00:42:06.425825 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4492 00:42:06.429462 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4493 00:42:06.435992 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4494 00:42:06.439436 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4495 00:42:06.442615 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4496 00:42:06.449003 0 10 8 | B1->B0 | 2323 2525 | 0 1 | (0 0) (0 0)
4497 00:42:06.452436 0 10 12 | B1->B0 | 3939 4242 | 1 0 | (0 0) (0 0)
4498 00:42:06.455981 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4499 00:42:06.462598 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4500 00:42:06.465966 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4501 00:42:06.469357 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4502 00:42:06.472554 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4503 00:42:06.479449 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4504 00:42:06.482283 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4505 00:42:06.485878 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4506 00:42:06.492402 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4507 00:42:06.495763 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4508 00:42:06.498907 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4509 00:42:06.505856 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4510 00:42:06.509069 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4511 00:42:06.512328 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4512 00:42:06.519190 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4513 00:42:06.522627 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4514 00:42:06.525920 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4515 00:42:06.532465 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4516 00:42:06.535610 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4517 00:42:06.539251 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4518 00:42:06.545377 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4519 00:42:06.549186 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4520 00:42:06.552016 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4521 00:42:06.558689 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4522 00:42:06.562059 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4523 00:42:06.565406 Total UI for P1: 0, mck2ui 16
4524 00:42:06.569006 best dqsien dly found for B0: ( 0, 13, 10)
4525 00:42:06.572062 Total UI for P1: 0, mck2ui 16
4526 00:42:06.575299 best dqsien dly found for B1: ( 0, 13, 12)
4527 00:42:06.578625 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4528 00:42:06.581987 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4529 00:42:06.582063
4530 00:42:06.585516 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4531 00:42:06.588872 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4532 00:42:06.592157 [Gating] SW calibration Done
4533 00:42:06.592262 ==
4534 00:42:06.595346 Dram Type= 6, Freq= 0, CH_1, rank 0
4535 00:42:06.599028 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4536 00:42:06.599114 ==
4537 00:42:06.602383 RX Vref Scan: 0
4538 00:42:06.602467
4539 00:42:06.605653 RX Vref 0 -> 0, step: 1
4540 00:42:06.605737
4541 00:42:06.609173 RX Delay -230 -> 252, step: 16
4542 00:42:06.612527 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4543 00:42:06.615376 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4544 00:42:06.618845 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4545 00:42:06.622081 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4546 00:42:06.629030 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4547 00:42:06.632159 iDelay=218, Bit 5, Center 57 (-86 ~ 201) 288
4548 00:42:06.635580 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4549 00:42:06.639077 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4550 00:42:06.642214 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4551 00:42:06.649064 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4552 00:42:06.652109 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4553 00:42:06.655298 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4554 00:42:06.658789 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4555 00:42:06.665573 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4556 00:42:06.668693 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4557 00:42:06.672290 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4558 00:42:06.672377 ==
4559 00:42:06.675381 Dram Type= 6, Freq= 0, CH_1, rank 0
4560 00:42:06.678591 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4561 00:42:06.682219 ==
4562 00:42:06.682305 DQS Delay:
4563 00:42:06.682373 DQS0 = 0, DQS1 = 0
4564 00:42:06.685347 DQM Delay:
4565 00:42:06.685433 DQM0 = 51, DQM1 = 38
4566 00:42:06.688504 DQ Delay:
4567 00:42:06.688611 DQ0 =57, DQ1 =49, DQ2 =33, DQ3 =49
4568 00:42:06.691872 DQ4 =49, DQ5 =57, DQ6 =65, DQ7 =49
4569 00:42:06.695150 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =41
4570 00:42:06.698664 DQ12 =49, DQ13 =41, DQ14 =41, DQ15 =41
4571 00:42:06.698750
4572 00:42:06.701873
4573 00:42:06.701958 ==
4574 00:42:06.705380 Dram Type= 6, Freq= 0, CH_1, rank 0
4575 00:42:06.709118 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4576 00:42:06.709204 ==
4577 00:42:06.709271
4578 00:42:06.709332
4579 00:42:06.712009 TX Vref Scan disable
4580 00:42:06.712094 == TX Byte 0 ==
4581 00:42:06.718443 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4582 00:42:06.721687 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4583 00:42:06.721773 == TX Byte 1 ==
4584 00:42:06.728747 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4585 00:42:06.731773 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4586 00:42:06.731861 ==
4587 00:42:06.735095 Dram Type= 6, Freq= 0, CH_1, rank 0
4588 00:42:06.738487 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4589 00:42:06.738571 ==
4590 00:42:06.738638
4591 00:42:06.738712
4592 00:42:06.741790 TX Vref Scan disable
4593 00:42:06.744911 == TX Byte 0 ==
4594 00:42:06.748149 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4595 00:42:06.751861 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4596 00:42:06.754887 == TX Byte 1 ==
4597 00:42:06.758196 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4598 00:42:06.761922 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4599 00:42:06.761997
4600 00:42:06.765286 [DATLAT]
4601 00:42:06.765386 Freq=600, CH1 RK0
4602 00:42:06.765451
4603 00:42:06.768187 DATLAT Default: 0x9
4604 00:42:06.768256 0, 0xFFFF, sum = 0
4605 00:42:06.771960 1, 0xFFFF, sum = 0
4606 00:42:06.772042 2, 0xFFFF, sum = 0
4607 00:42:06.775335 3, 0xFFFF, sum = 0
4608 00:42:06.775408 4, 0xFFFF, sum = 0
4609 00:42:06.778290 5, 0xFFFF, sum = 0
4610 00:42:06.778367 6, 0xFFFF, sum = 0
4611 00:42:06.781531 7, 0xFFFF, sum = 0
4612 00:42:06.781609 8, 0x0, sum = 1
4613 00:42:06.784749 9, 0x0, sum = 2
4614 00:42:06.784829 10, 0x0, sum = 3
4615 00:42:06.788372 11, 0x0, sum = 4
4616 00:42:06.788445 best_step = 9
4617 00:42:06.788505
4618 00:42:06.788581 ==
4619 00:42:06.791778 Dram Type= 6, Freq= 0, CH_1, rank 0
4620 00:42:06.795165 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4621 00:42:06.798353 ==
4622 00:42:06.798432 RX Vref Scan: 1
4623 00:42:06.798496
4624 00:42:06.801687 RX Vref 0 -> 0, step: 1
4625 00:42:06.801759
4626 00:42:06.804972 RX Delay -179 -> 252, step: 8
4627 00:42:06.805048
4628 00:42:06.808621 Set Vref, RX VrefLevel [Byte0]: 52
4629 00:42:06.811604 [Byte1]: 53
4630 00:42:06.811677
4631 00:42:06.814879 Final RX Vref Byte 0 = 52 to rank0
4632 00:42:06.818074 Final RX Vref Byte 1 = 53 to rank0
4633 00:42:06.821332 Final RX Vref Byte 0 = 52 to rank1
4634 00:42:06.825018 Final RX Vref Byte 1 = 53 to rank1==
4635 00:42:06.828160 Dram Type= 6, Freq= 0, CH_1, rank 0
4636 00:42:06.831495 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4637 00:42:06.831578 ==
4638 00:42:06.834652 DQS Delay:
4639 00:42:06.834741 DQS0 = 0, DQS1 = 0
4640 00:42:06.834828 DQM Delay:
4641 00:42:06.838475 DQM0 = 48, DQM1 = 40
4642 00:42:06.838564 DQ Delay:
4643 00:42:06.841438 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4644 00:42:06.845001 DQ4 =44, DQ5 =60, DQ6 =60, DQ7 =44
4645 00:42:06.848346 DQ8 =28, DQ9 =28, DQ10 =44, DQ11 =32
4646 00:42:06.851466 DQ12 =52, DQ13 =48, DQ14 =44, DQ15 =48
4647 00:42:06.851556
4648 00:42:06.851642
4649 00:42:06.861608 [DQSOSCAuto] RK0, (LSB)MR18= 0x5279, (MSB)MR19= 0x808, tDQSOscB0 = 387 ps tDQSOscB1 = 394 ps
4650 00:42:06.861708 CH1 RK0: MR19=808, MR18=5279
4651 00:42:06.868333 CH1_RK0: MR19=0x808, MR18=0x5279, DQSOSC=387, MR23=63, INC=175, DEC=116
4652 00:42:06.868427
4653 00:42:06.871422 ----->DramcWriteLeveling(PI) begin...
4654 00:42:06.871511 ==
4655 00:42:06.874762 Dram Type= 6, Freq= 0, CH_1, rank 1
4656 00:42:06.881661 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4657 00:42:06.881753 ==
4658 00:42:06.884805 Write leveling (Byte 0): 30 => 30
4659 00:42:06.888178 Write leveling (Byte 1): 30 => 30
4660 00:42:06.888267 DramcWriteLeveling(PI) end<-----
4661 00:42:06.888354
4662 00:42:06.891355 ==
4663 00:42:06.894758 Dram Type= 6, Freq= 0, CH_1, rank 1
4664 00:42:06.898314 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4665 00:42:06.898392 ==
4666 00:42:06.901721 [Gating] SW mode calibration
4667 00:42:06.908512 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4668 00:42:06.911528 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4669 00:42:06.918483 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4670 00:42:06.921785 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4671 00:42:06.924938 0 9 8 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
4672 00:42:06.931731 0 9 12 | B1->B0 | 2b2b 3232 | 0 0 | (0 0) (0 1)
4673 00:42:06.935027 0 9 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4674 00:42:06.938225 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4675 00:42:06.944707 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4676 00:42:06.948155 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4677 00:42:06.951623 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4678 00:42:06.957920 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4679 00:42:06.961495 0 10 8 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
4680 00:42:06.964745 0 10 12 | B1->B0 | 4040 3131 | 0 1 | (0 0) (0 0)
4681 00:42:06.971583 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4682 00:42:06.974789 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4683 00:42:06.977759 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4684 00:42:06.984543 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4685 00:42:06.987703 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4686 00:42:06.991316 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4687 00:42:06.997580 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4688 00:42:07.001346 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4689 00:42:07.004584 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4690 00:42:07.007578 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4691 00:42:07.014216 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4692 00:42:07.017540 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4693 00:42:07.020784 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4694 00:42:07.027675 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4695 00:42:07.030954 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4696 00:42:07.034213 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4697 00:42:07.040969 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4698 00:42:07.044150 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4699 00:42:07.047645 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4700 00:42:07.054478 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4701 00:42:07.057439 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4702 00:42:07.060882 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4703 00:42:07.067719 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4704 00:42:07.071022 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4705 00:42:07.074183 Total UI for P1: 0, mck2ui 16
4706 00:42:07.077651 best dqsien dly found for B1: ( 0, 13, 10)
4707 00:42:07.080986 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4708 00:42:07.084000 Total UI for P1: 0, mck2ui 16
4709 00:42:07.087529 best dqsien dly found for B0: ( 0, 13, 12)
4710 00:42:07.090802 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4711 00:42:07.094261 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4712 00:42:07.094348
4713 00:42:07.101071 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4714 00:42:07.103876 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4715 00:42:07.103962 [Gating] SW calibration Done
4716 00:42:07.107410 ==
4717 00:42:07.110833 Dram Type= 6, Freq= 0, CH_1, rank 1
4718 00:42:07.114234 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4719 00:42:07.114322 ==
4720 00:42:07.114389 RX Vref Scan: 0
4721 00:42:07.114452
4722 00:42:07.117315 RX Vref 0 -> 0, step: 1
4723 00:42:07.117439
4724 00:42:07.120832 RX Delay -230 -> 252, step: 16
4725 00:42:07.124073 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4726 00:42:07.127465 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4727 00:42:07.134079 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4728 00:42:07.137204 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4729 00:42:07.140750 iDelay=218, Bit 4, Center 57 (-86 ~ 201) 288
4730 00:42:07.143963 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4731 00:42:07.147559 iDelay=218, Bit 6, Center 57 (-86 ~ 201) 288
4732 00:42:07.154066 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4733 00:42:07.157437 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4734 00:42:07.160584 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4735 00:42:07.164435 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4736 00:42:07.167497 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4737 00:42:07.174129 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4738 00:42:07.177507 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4739 00:42:07.180663 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4740 00:42:07.184091 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4741 00:42:07.187421 ==
4742 00:42:07.190584 Dram Type= 6, Freq= 0, CH_1, rank 1
4743 00:42:07.193931 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4744 00:42:07.194018 ==
4745 00:42:07.194086 DQS Delay:
4746 00:42:07.197009 DQS0 = 0, DQS1 = 0
4747 00:42:07.197094 DQM Delay:
4748 00:42:07.200395 DQM0 = 52, DQM1 = 46
4749 00:42:07.200506 DQ Delay:
4750 00:42:07.204139 DQ0 =57, DQ1 =49, DQ2 =33, DQ3 =49
4751 00:42:07.207403 DQ4 =57, DQ5 =65, DQ6 =57, DQ7 =49
4752 00:42:07.210512 DQ8 =25, DQ9 =33, DQ10 =49, DQ11 =41
4753 00:42:07.213816 DQ12 =57, DQ13 =49, DQ14 =57, DQ15 =57
4754 00:42:07.213901
4755 00:42:07.213968
4756 00:42:07.214029 ==
4757 00:42:07.217423 Dram Type= 6, Freq= 0, CH_1, rank 1
4758 00:42:07.220311 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4759 00:42:07.220417 ==
4760 00:42:07.220512
4761 00:42:07.220595
4762 00:42:07.224032 TX Vref Scan disable
4763 00:42:07.226987 == TX Byte 0 ==
4764 00:42:07.230484 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4765 00:42:07.233879 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4766 00:42:07.237337 == TX Byte 1 ==
4767 00:42:07.240509 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4768 00:42:07.243849 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4769 00:42:07.243935 ==
4770 00:42:07.247386 Dram Type= 6, Freq= 0, CH_1, rank 1
4771 00:42:07.250369 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4772 00:42:07.253790 ==
4773 00:42:07.253876
4774 00:42:07.253944
4775 00:42:07.254005 TX Vref Scan disable
4776 00:42:07.257628 == TX Byte 0 ==
4777 00:42:07.260927 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4778 00:42:07.267761 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4779 00:42:07.267851 == TX Byte 1 ==
4780 00:42:07.270958 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4781 00:42:07.274318 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4782 00:42:07.277572
4783 00:42:07.277658 [DATLAT]
4784 00:42:07.277725 Freq=600, CH1 RK1
4785 00:42:07.277791
4786 00:42:07.281344 DATLAT Default: 0x9
4787 00:42:07.281430 0, 0xFFFF, sum = 0
4788 00:42:07.284492 1, 0xFFFF, sum = 0
4789 00:42:07.284620 2, 0xFFFF, sum = 0
4790 00:42:07.287895 3, 0xFFFF, sum = 0
4791 00:42:07.287981 4, 0xFFFF, sum = 0
4792 00:42:07.291457 5, 0xFFFF, sum = 0
4793 00:42:07.291544 6, 0xFFFF, sum = 0
4794 00:42:07.294368 7, 0xFFFF, sum = 0
4795 00:42:07.294455 8, 0x0, sum = 1
4796 00:42:07.298047 9, 0x0, sum = 2
4797 00:42:07.298134 10, 0x0, sum = 3
4798 00:42:07.301131 11, 0x0, sum = 4
4799 00:42:07.301218 best_step = 9
4800 00:42:07.301286
4801 00:42:07.301347 ==
4802 00:42:07.304523 Dram Type= 6, Freq= 0, CH_1, rank 1
4803 00:42:07.307937 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4804 00:42:07.311177 ==
4805 00:42:07.311263 RX Vref Scan: 0
4806 00:42:07.311329
4807 00:42:07.314805 RX Vref 0 -> 0, step: 1
4808 00:42:07.314890
4809 00:42:07.317863 RX Delay -179 -> 252, step: 8
4810 00:42:07.321124 iDelay=205, Bit 0, Center 56 (-83 ~ 196) 280
4811 00:42:07.324468 iDelay=205, Bit 1, Center 40 (-99 ~ 180) 280
4812 00:42:07.331173 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4813 00:42:07.334667 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4814 00:42:07.338135 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4815 00:42:07.340970 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4816 00:42:07.344684 iDelay=205, Bit 6, Center 56 (-83 ~ 196) 280
4817 00:42:07.351472 iDelay=205, Bit 7, Center 48 (-91 ~ 188) 280
4818 00:42:07.354203 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4819 00:42:07.357482 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4820 00:42:07.360981 iDelay=205, Bit 10, Center 40 (-107 ~ 188) 296
4821 00:42:07.367816 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4822 00:42:07.371155 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4823 00:42:07.374155 iDelay=205, Bit 13, Center 48 (-99 ~ 196) 296
4824 00:42:07.377326 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4825 00:42:07.383956 iDelay=205, Bit 15, Center 56 (-91 ~ 204) 296
4826 00:42:07.384043 ==
4827 00:42:07.387568 Dram Type= 6, Freq= 0, CH_1, rank 1
4828 00:42:07.390768 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4829 00:42:07.390854 ==
4830 00:42:07.390921 DQS Delay:
4831 00:42:07.394263 DQS0 = 0, DQS1 = 0
4832 00:42:07.394350 DQM Delay:
4833 00:42:07.397384 DQM0 = 48, DQM1 = 43
4834 00:42:07.397469 DQ Delay:
4835 00:42:07.400494 DQ0 =56, DQ1 =40, DQ2 =36, DQ3 =44
4836 00:42:07.404013 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4837 00:42:07.407290 DQ8 =32, DQ9 =32, DQ10 =40, DQ11 =40
4838 00:42:07.410639 DQ12 =48, DQ13 =48, DQ14 =48, DQ15 =56
4839 00:42:07.410725
4840 00:42:07.410791
4841 00:42:07.417430 [DQSOSCAuto] RK1, (LSB)MR18= 0x632a, (MSB)MR19= 0x808, tDQSOscB0 = 401 ps tDQSOscB1 = 391 ps
4842 00:42:07.420400 CH1 RK1: MR19=808, MR18=632A
4843 00:42:07.427045 CH1_RK1: MR19=0x808, MR18=0x632A, DQSOSC=391, MR23=63, INC=171, DEC=114
4844 00:42:07.430444 [RxdqsGatingPostProcess] freq 600
4845 00:42:07.437081 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4846 00:42:07.440515 Pre-setting of DQS Precalculation
4847 00:42:07.443857 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4848 00:42:07.450746 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4849 00:42:07.456944 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4850 00:42:07.457031
4851 00:42:07.457098
4852 00:42:07.460902 [Calibration Summary] 1200 Mbps
4853 00:42:07.463733 CH 0, Rank 0
4854 00:42:07.463819 SW Impedance : PASS
4855 00:42:07.467351 DUTY Scan : NO K
4856 00:42:07.470474 ZQ Calibration : PASS
4857 00:42:07.470561 Jitter Meter : NO K
4858 00:42:07.473969 CBT Training : PASS
4859 00:42:07.474057 Write leveling : PASS
4860 00:42:07.477022 RX DQS gating : PASS
4861 00:42:07.480473 RX DQ/DQS(RDDQC) : PASS
4862 00:42:07.480568 TX DQ/DQS : PASS
4863 00:42:07.483634 RX DATLAT : PASS
4864 00:42:07.486883 RX DQ/DQS(Engine): PASS
4865 00:42:07.486968 TX OE : NO K
4866 00:42:07.490183 All Pass.
4867 00:42:07.490269
4868 00:42:07.490336 CH 0, Rank 1
4869 00:42:07.493943 SW Impedance : PASS
4870 00:42:07.494029 DUTY Scan : NO K
4871 00:42:07.497273 ZQ Calibration : PASS
4872 00:42:07.500501 Jitter Meter : NO K
4873 00:42:07.500611 CBT Training : PASS
4874 00:42:07.503914 Write leveling : PASS
4875 00:42:07.507223 RX DQS gating : PASS
4876 00:42:07.507309 RX DQ/DQS(RDDQC) : PASS
4877 00:42:07.510384 TX DQ/DQS : PASS
4878 00:42:07.514071 RX DATLAT : PASS
4879 00:42:07.514159 RX DQ/DQS(Engine): PASS
4880 00:42:07.517252 TX OE : NO K
4881 00:42:07.517342 All Pass.
4882 00:42:07.517410
4883 00:42:07.520495 CH 1, Rank 0
4884 00:42:07.520601 SW Impedance : PASS
4885 00:42:07.523720 DUTY Scan : NO K
4886 00:42:07.523820 ZQ Calibration : PASS
4887 00:42:07.526904 Jitter Meter : NO K
4888 00:42:07.530360 CBT Training : PASS
4889 00:42:07.530445 Write leveling : PASS
4890 00:42:07.533753 RX DQS gating : PASS
4891 00:42:07.536975 RX DQ/DQS(RDDQC) : PASS
4892 00:42:07.537060 TX DQ/DQS : PASS
4893 00:42:07.540345 RX DATLAT : PASS
4894 00:42:07.543409 RX DQ/DQS(Engine): PASS
4895 00:42:07.543495 TX OE : NO K
4896 00:42:07.546905 All Pass.
4897 00:42:07.546990
4898 00:42:07.547057 CH 1, Rank 1
4899 00:42:07.550552 SW Impedance : PASS
4900 00:42:07.550638 DUTY Scan : NO K
4901 00:42:07.553409 ZQ Calibration : PASS
4902 00:42:07.556760 Jitter Meter : NO K
4903 00:42:07.556845 CBT Training : PASS
4904 00:42:07.560138 Write leveling : PASS
4905 00:42:07.563466 RX DQS gating : PASS
4906 00:42:07.563593 RX DQ/DQS(RDDQC) : PASS
4907 00:42:07.567139 TX DQ/DQS : PASS
4908 00:42:07.570251 RX DATLAT : PASS
4909 00:42:07.570336 RX DQ/DQS(Engine): PASS
4910 00:42:07.573250 TX OE : NO K
4911 00:42:07.573336 All Pass.
4912 00:42:07.573402
4913 00:42:07.576683 DramC Write-DBI off
4914 00:42:07.579844 PER_BANK_REFRESH: Hybrid Mode
4915 00:42:07.579929 TX_TRACKING: ON
4916 00:42:07.590134 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4917 00:42:07.593534 [FAST_K] Save calibration result to emmc
4918 00:42:07.596899 dramc_set_vcore_voltage set vcore to 662500
4919 00:42:07.596986 Read voltage for 933, 3
4920 00:42:07.600149 Vio18 = 0
4921 00:42:07.600235 Vcore = 662500
4922 00:42:07.600302 Vdram = 0
4923 00:42:07.603124 Vddq = 0
4924 00:42:07.603210 Vmddr = 0
4925 00:42:07.609728 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4926 00:42:07.613228 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4927 00:42:07.616686 MEM_TYPE=3, freq_sel=17
4928 00:42:07.619841 sv_algorithm_assistance_LP4_1600
4929 00:42:07.623447 ============ PULL DRAM RESETB DOWN ============
4930 00:42:07.626626 ========== PULL DRAM RESETB DOWN end =========
4931 00:42:07.633075 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4932 00:42:07.636537 ===================================
4933 00:42:07.636660 LPDDR4 DRAM CONFIGURATION
4934 00:42:07.639909 ===================================
4935 00:42:07.643162 EX_ROW_EN[0] = 0x0
4936 00:42:07.643247 EX_ROW_EN[1] = 0x0
4937 00:42:07.646581 LP4Y_EN = 0x0
4938 00:42:07.650016 WORK_FSP = 0x0
4939 00:42:07.650117 WL = 0x3
4940 00:42:07.653072 RL = 0x3
4941 00:42:07.653157 BL = 0x2
4942 00:42:07.656430 RPST = 0x0
4943 00:42:07.656531 RD_PRE = 0x0
4944 00:42:07.659705 WR_PRE = 0x1
4945 00:42:07.659816 WR_PST = 0x0
4946 00:42:07.663030 DBI_WR = 0x0
4947 00:42:07.663116 DBI_RD = 0x0
4948 00:42:07.666609 OTF = 0x1
4949 00:42:07.669907 ===================================
4950 00:42:07.673259 ===================================
4951 00:42:07.673345 ANA top config
4952 00:42:07.676788 ===================================
4953 00:42:07.679880 DLL_ASYNC_EN = 0
4954 00:42:07.683158 ALL_SLAVE_EN = 1
4955 00:42:07.683268 NEW_RANK_MODE = 1
4956 00:42:07.686707 DLL_IDLE_MODE = 1
4957 00:42:07.689809 LP45_APHY_COMB_EN = 1
4958 00:42:07.693420 TX_ODT_DIS = 1
4959 00:42:07.693508 NEW_8X_MODE = 1
4960 00:42:07.696414 ===================================
4961 00:42:07.699766 ===================================
4962 00:42:07.703080 data_rate = 1866
4963 00:42:07.706479 CKR = 1
4964 00:42:07.709835 DQ_P2S_RATIO = 8
4965 00:42:07.713226 ===================================
4966 00:42:07.716335 CA_P2S_RATIO = 8
4967 00:42:07.720101 DQ_CA_OPEN = 0
4968 00:42:07.720188 DQ_SEMI_OPEN = 0
4969 00:42:07.722937 CA_SEMI_OPEN = 0
4970 00:42:07.726414 CA_FULL_RATE = 0
4971 00:42:07.729851 DQ_CKDIV4_EN = 1
4972 00:42:07.733476 CA_CKDIV4_EN = 1
4973 00:42:07.736568 CA_PREDIV_EN = 0
4974 00:42:07.736668 PH8_DLY = 0
4975 00:42:07.739788 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4976 00:42:07.743092 DQ_AAMCK_DIV = 4
4977 00:42:07.746624 CA_AAMCK_DIV = 4
4978 00:42:07.749785 CA_ADMCK_DIV = 4
4979 00:42:07.752991 DQ_TRACK_CA_EN = 0
4980 00:42:07.753077 CA_PICK = 933
4981 00:42:07.756647 CA_MCKIO = 933
4982 00:42:07.759616 MCKIO_SEMI = 0
4983 00:42:07.763267 PLL_FREQ = 3732
4984 00:42:07.766655 DQ_UI_PI_RATIO = 32
4985 00:42:07.770061 CA_UI_PI_RATIO = 0
4986 00:42:07.773147 ===================================
4987 00:42:07.776752 ===================================
4988 00:42:07.776839 memory_type:LPDDR4
4989 00:42:07.779633 GP_NUM : 10
4990 00:42:07.782905 SRAM_EN : 1
4991 00:42:07.782990 MD32_EN : 0
4992 00:42:07.786466 ===================================
4993 00:42:07.789814 [ANA_INIT] >>>>>>>>>>>>>>
4994 00:42:07.792812 <<<<<< [CONFIGURE PHASE]: ANA_TX
4995 00:42:07.796585 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4996 00:42:07.799761 ===================================
4997 00:42:07.802991 data_rate = 1866,PCW = 0X8f00
4998 00:42:07.806324 ===================================
4999 00:42:07.809549 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5000 00:42:07.812758 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5001 00:42:07.819401 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5002 00:42:07.823092 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5003 00:42:07.826338 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5004 00:42:07.829368 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5005 00:42:07.833101 [ANA_INIT] flow start
5006 00:42:07.836495 [ANA_INIT] PLL >>>>>>>>
5007 00:42:07.836607 [ANA_INIT] PLL <<<<<<<<
5008 00:42:07.839826 [ANA_INIT] MIDPI >>>>>>>>
5009 00:42:07.843282 [ANA_INIT] MIDPI <<<<<<<<
5010 00:42:07.846192 [ANA_INIT] DLL >>>>>>>>
5011 00:42:07.846277 [ANA_INIT] flow end
5012 00:42:07.849577 ============ LP4 DIFF to SE enter ============
5013 00:42:07.856330 ============ LP4 DIFF to SE exit ============
5014 00:42:07.856455 [ANA_INIT] <<<<<<<<<<<<<
5015 00:42:07.859562 [Flow] Enable top DCM control >>>>>
5016 00:42:07.862971 [Flow] Enable top DCM control <<<<<
5017 00:42:07.866360 Enable DLL master slave shuffle
5018 00:42:07.872922 ==============================================================
5019 00:42:07.873013 Gating Mode config
5020 00:42:07.879698 ==============================================================
5021 00:42:07.882892 Config description:
5022 00:42:07.889642 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5023 00:42:07.896395 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5024 00:42:07.902946 SELPH_MODE 0: By rank 1: By Phase
5025 00:42:07.909794 ==============================================================
5026 00:42:07.909889 GAT_TRACK_EN = 1
5027 00:42:07.912895 RX_GATING_MODE = 2
5028 00:42:07.916452 RX_GATING_TRACK_MODE = 2
5029 00:42:07.919706 SELPH_MODE = 1
5030 00:42:07.922951 PICG_EARLY_EN = 1
5031 00:42:07.926192 VALID_LAT_VALUE = 1
5032 00:42:07.932866 ==============================================================
5033 00:42:07.936246 Enter into Gating configuration >>>>
5034 00:42:07.939424 Exit from Gating configuration <<<<
5035 00:42:07.943080 Enter into DVFS_PRE_config >>>>>
5036 00:42:07.952953 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5037 00:42:07.956262 Exit from DVFS_PRE_config <<<<<
5038 00:42:07.959544 Enter into PICG configuration >>>>
5039 00:42:07.962659 Exit from PICG configuration <<<<
5040 00:42:07.966123 [RX_INPUT] configuration >>>>>
5041 00:42:07.966208 [RX_INPUT] configuration <<<<<
5042 00:42:07.972372 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5043 00:42:07.979280 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5044 00:42:07.986049 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5045 00:42:07.989031 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5046 00:42:07.995698 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5047 00:42:08.002095 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5048 00:42:08.005262 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5049 00:42:08.011899 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5050 00:42:08.015198 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5051 00:42:08.018637 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5052 00:42:08.021896 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5053 00:42:08.028477 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5054 00:42:08.032108 ===================================
5055 00:42:08.032224 LPDDR4 DRAM CONFIGURATION
5056 00:42:08.035481 ===================================
5057 00:42:08.038747 EX_ROW_EN[0] = 0x0
5058 00:42:08.041811 EX_ROW_EN[1] = 0x0
5059 00:42:08.041924 LP4Y_EN = 0x0
5060 00:42:08.045207 WORK_FSP = 0x0
5061 00:42:08.045292 WL = 0x3
5062 00:42:08.048502 RL = 0x3
5063 00:42:08.048638 BL = 0x2
5064 00:42:08.051779 RPST = 0x0
5065 00:42:08.051864 RD_PRE = 0x0
5066 00:42:08.055431 WR_PRE = 0x1
5067 00:42:08.055516 WR_PST = 0x0
5068 00:42:08.058818 DBI_WR = 0x0
5069 00:42:08.058903 DBI_RD = 0x0
5070 00:42:08.061739 OTF = 0x1
5071 00:42:08.064939 ===================================
5072 00:42:08.068407 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5073 00:42:08.071515 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5074 00:42:08.078051 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5075 00:42:08.081846 ===================================
5076 00:42:08.081931 LPDDR4 DRAM CONFIGURATION
5077 00:42:08.084790 ===================================
5078 00:42:08.088420 EX_ROW_EN[0] = 0x10
5079 00:42:08.091386 EX_ROW_EN[1] = 0x0
5080 00:42:08.091470 LP4Y_EN = 0x0
5081 00:42:08.095114 WORK_FSP = 0x0
5082 00:42:08.095198 WL = 0x3
5083 00:42:08.098525 RL = 0x3
5084 00:42:08.098609 BL = 0x2
5085 00:42:08.101564 RPST = 0x0
5086 00:42:08.101649 RD_PRE = 0x0
5087 00:42:08.104679 WR_PRE = 0x1
5088 00:42:08.104763 WR_PST = 0x0
5089 00:42:08.108041 DBI_WR = 0x0
5090 00:42:08.108126 DBI_RD = 0x0
5091 00:42:08.111666 OTF = 0x1
5092 00:42:08.114747 ===================================
5093 00:42:08.121309 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5094 00:42:08.124563 nWR fixed to 30
5095 00:42:08.124649 [ModeRegInit_LP4] CH0 RK0
5096 00:42:08.128196 [ModeRegInit_LP4] CH0 RK1
5097 00:42:08.131624 [ModeRegInit_LP4] CH1 RK0
5098 00:42:08.134476 [ModeRegInit_LP4] CH1 RK1
5099 00:42:08.134583 match AC timing 9
5100 00:42:08.137890 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5101 00:42:08.144603 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5102 00:42:08.147688 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5103 00:42:08.154663 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5104 00:42:08.158071 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5105 00:42:08.158155 ==
5106 00:42:08.161407 Dram Type= 6, Freq= 0, CH_0, rank 0
5107 00:42:08.164727 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5108 00:42:08.164812 ==
5109 00:42:08.170950 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5110 00:42:08.177868 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5111 00:42:08.181233 [CA 0] Center 37 (7~68) winsize 62
5112 00:42:08.184687 [CA 1] Center 38 (7~69) winsize 63
5113 00:42:08.187705 [CA 2] Center 35 (5~65) winsize 61
5114 00:42:08.190785 [CA 3] Center 35 (5~65) winsize 61
5115 00:42:08.194192 [CA 4] Center 34 (4~65) winsize 62
5116 00:42:08.197607 [CA 5] Center 33 (3~64) winsize 62
5117 00:42:08.197693
5118 00:42:08.200890 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5119 00:42:08.200974
5120 00:42:08.204312 [CATrainingPosCal] consider 1 rank data
5121 00:42:08.207866 u2DelayCellTimex100 = 270/100 ps
5122 00:42:08.210798 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5123 00:42:08.214141 CA1 delay=38 (7~69),Diff = 5 PI (31 cell)
5124 00:42:08.217749 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5125 00:42:08.220829 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5126 00:42:08.224430 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5127 00:42:08.227489 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5128 00:42:08.227589
5129 00:42:08.234025 CA PerBit enable=1, Macro0, CA PI delay=33
5130 00:42:08.234110
5131 00:42:08.234176 [CBTSetCACLKResult] CA Dly = 33
5132 00:42:08.237653 CS Dly: 7 (0~38)
5133 00:42:08.237737 ==
5134 00:42:08.241080 Dram Type= 6, Freq= 0, CH_0, rank 1
5135 00:42:08.244158 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5136 00:42:08.244243 ==
5137 00:42:08.250611 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5138 00:42:08.257666 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5139 00:42:08.261158 [CA 0] Center 38 (8~69) winsize 62
5140 00:42:08.264389 [CA 1] Center 38 (8~69) winsize 62
5141 00:42:08.267794 [CA 2] Center 36 (6~66) winsize 61
5142 00:42:08.270911 [CA 3] Center 35 (5~66) winsize 62
5143 00:42:08.273920 [CA 4] Center 35 (5~65) winsize 61
5144 00:42:08.277678 [CA 5] Center 34 (4~64) winsize 61
5145 00:42:08.277762
5146 00:42:08.280920 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5147 00:42:08.281005
5148 00:42:08.284230 [CATrainingPosCal] consider 2 rank data
5149 00:42:08.287414 u2DelayCellTimex100 = 270/100 ps
5150 00:42:08.290790 CA0 delay=38 (8~68),Diff = 4 PI (24 cell)
5151 00:42:08.293993 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5152 00:42:08.297470 CA2 delay=35 (6~65),Diff = 1 PI (6 cell)
5153 00:42:08.301021 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5154 00:42:08.304202 CA4 delay=35 (5~65),Diff = 1 PI (6 cell)
5155 00:42:08.307576 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5156 00:42:08.307660
5157 00:42:08.314013 CA PerBit enable=1, Macro0, CA PI delay=34
5158 00:42:08.314099
5159 00:42:08.314164 [CBTSetCACLKResult] CA Dly = 34
5160 00:42:08.317483 CS Dly: 8 (0~40)
5161 00:42:08.317567
5162 00:42:08.320534 ----->DramcWriteLeveling(PI) begin...
5163 00:42:08.320654 ==
5164 00:42:08.323901 Dram Type= 6, Freq= 0, CH_0, rank 0
5165 00:42:08.327480 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5166 00:42:08.327566 ==
5167 00:42:08.330539 Write leveling (Byte 0): 32 => 32
5168 00:42:08.334174 Write leveling (Byte 1): 31 => 31
5169 00:42:08.337496 DramcWriteLeveling(PI) end<-----
5170 00:42:08.337580
5171 00:42:08.337646 ==
5172 00:42:08.340778 Dram Type= 6, Freq= 0, CH_0, rank 0
5173 00:42:08.346965 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5174 00:42:08.347050 ==
5175 00:42:08.347116 [Gating] SW mode calibration
5176 00:42:08.357311 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5177 00:42:08.360291 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5178 00:42:08.363693 0 14 0 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
5179 00:42:08.370440 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5180 00:42:08.373694 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5181 00:42:08.376868 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5182 00:42:08.383693 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5183 00:42:08.387004 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5184 00:42:08.390215 0 14 24 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 1)
5185 00:42:08.397165 0 14 28 | B1->B0 | 3131 2323 | 0 0 | (1 0) (1 0)
5186 00:42:08.400217 0 15 0 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
5187 00:42:08.403838 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5188 00:42:08.410473 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5189 00:42:08.413922 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5190 00:42:08.417262 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5191 00:42:08.423853 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5192 00:42:08.427216 0 15 24 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
5193 00:42:08.430413 0 15 28 | B1->B0 | 2e2e 4646 | 0 0 | (0 0) (0 0)
5194 00:42:08.437151 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5195 00:42:08.440250 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5196 00:42:08.443658 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5197 00:42:08.450258 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5198 00:42:08.453647 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5199 00:42:08.456939 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5200 00:42:08.460495 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5201 00:42:08.467029 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5202 00:42:08.470412 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5203 00:42:08.473516 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5204 00:42:08.480323 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5205 00:42:08.483506 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5206 00:42:08.486624 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5207 00:42:08.493429 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5208 00:42:08.496966 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5209 00:42:08.500318 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5210 00:42:08.506608 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5211 00:42:08.510317 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5212 00:42:08.513611 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5213 00:42:08.520075 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5214 00:42:08.523451 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5215 00:42:08.526495 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5216 00:42:08.533002 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5217 00:42:08.536476 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5218 00:42:08.539933 Total UI for P1: 0, mck2ui 16
5219 00:42:08.543288 best dqsien dly found for B0: ( 1, 2, 24)
5220 00:42:08.546387 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5221 00:42:08.550129 Total UI for P1: 0, mck2ui 16
5222 00:42:08.553058 best dqsien dly found for B1: ( 1, 2, 28)
5223 00:42:08.556495 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5224 00:42:08.559668 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5225 00:42:08.559752
5226 00:42:08.566474 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5227 00:42:08.569954 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5228 00:42:08.570037 [Gating] SW calibration Done
5229 00:42:08.573265 ==
5230 00:42:08.576624 Dram Type= 6, Freq= 0, CH_0, rank 0
5231 00:42:08.579845 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5232 00:42:08.580030 ==
5233 00:42:08.580105 RX Vref Scan: 0
5234 00:42:08.580167
5235 00:42:08.583183 RX Vref 0 -> 0, step: 1
5236 00:42:08.583333
5237 00:42:08.586448 RX Delay -80 -> 252, step: 8
5238 00:42:08.589995 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5239 00:42:08.593315 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5240 00:42:08.596594 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5241 00:42:08.603409 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5242 00:42:08.606587 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5243 00:42:08.609631 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5244 00:42:08.613214 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5245 00:42:08.616449 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5246 00:42:08.619802 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5247 00:42:08.626432 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5248 00:42:08.629922 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5249 00:42:08.633078 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5250 00:42:08.636747 iDelay=208, Bit 12, Center 95 (8 ~ 183) 176
5251 00:42:08.639885 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5252 00:42:08.643058 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5253 00:42:08.649696 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5254 00:42:08.649780 ==
5255 00:42:08.653089 Dram Type= 6, Freq= 0, CH_0, rank 0
5256 00:42:08.656453 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5257 00:42:08.656539 ==
5258 00:42:08.656612 DQS Delay:
5259 00:42:08.659720 DQS0 = 0, DQS1 = 0
5260 00:42:08.659804 DQM Delay:
5261 00:42:08.663219 DQM0 = 105, DQM1 = 90
5262 00:42:08.663309 DQ Delay:
5263 00:42:08.666563 DQ0 =107, DQ1 =107, DQ2 =99, DQ3 =99
5264 00:42:08.669384 DQ4 =107, DQ5 =95, DQ6 =115, DQ7 =115
5265 00:42:08.672924 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =87
5266 00:42:08.675987 DQ12 =95, DQ13 =91, DQ14 =99, DQ15 =99
5267 00:42:08.676071
5268 00:42:08.676138
5269 00:42:08.676199 ==
5270 00:42:08.679504 Dram Type= 6, Freq= 0, CH_0, rank 0
5271 00:42:08.682896 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5272 00:42:08.686075 ==
5273 00:42:08.686160
5274 00:42:08.686225
5275 00:42:08.686286 TX Vref Scan disable
5276 00:42:08.689634 == TX Byte 0 ==
5277 00:42:08.692853 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5278 00:42:08.696200 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5279 00:42:08.699246 == TX Byte 1 ==
5280 00:42:08.702924 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5281 00:42:08.706260 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5282 00:42:08.709264 ==
5283 00:42:08.712898 Dram Type= 6, Freq= 0, CH_0, rank 0
5284 00:42:08.716206 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5285 00:42:08.716292 ==
5286 00:42:08.716358
5287 00:42:08.716418
5288 00:42:08.719463 TX Vref Scan disable
5289 00:42:08.719548 == TX Byte 0 ==
5290 00:42:08.725884 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5291 00:42:08.729259 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5292 00:42:08.729345 == TX Byte 1 ==
5293 00:42:08.736213 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5294 00:42:08.739469 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5295 00:42:08.739555
5296 00:42:08.739622 [DATLAT]
5297 00:42:08.742938 Freq=933, CH0 RK0
5298 00:42:08.743024
5299 00:42:08.743090 DATLAT Default: 0xd
5300 00:42:08.746063 0, 0xFFFF, sum = 0
5301 00:42:08.746149 1, 0xFFFF, sum = 0
5302 00:42:08.749464 2, 0xFFFF, sum = 0
5303 00:42:08.749573 3, 0xFFFF, sum = 0
5304 00:42:08.752524 4, 0xFFFF, sum = 0
5305 00:42:08.752645 5, 0xFFFF, sum = 0
5306 00:42:08.755898 6, 0xFFFF, sum = 0
5307 00:42:08.755983 7, 0xFFFF, sum = 0
5308 00:42:08.759418 8, 0xFFFF, sum = 0
5309 00:42:08.759503 9, 0xFFFF, sum = 0
5310 00:42:08.762713 10, 0x0, sum = 1
5311 00:42:08.762799 11, 0x0, sum = 2
5312 00:42:08.765776 12, 0x0, sum = 3
5313 00:42:08.765861 13, 0x0, sum = 4
5314 00:42:08.769513 best_step = 11
5315 00:42:08.769674
5316 00:42:08.769743 ==
5317 00:42:08.772970 Dram Type= 6, Freq= 0, CH_0, rank 0
5318 00:42:08.775757 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5319 00:42:08.775841 ==
5320 00:42:08.779352 RX Vref Scan: 1
5321 00:42:08.779440
5322 00:42:08.779521 RX Vref 0 -> 0, step: 1
5323 00:42:08.779598
5324 00:42:08.782529 RX Delay -53 -> 252, step: 4
5325 00:42:08.782608
5326 00:42:08.785870 Set Vref, RX VrefLevel [Byte0]: 61
5327 00:42:08.789399 [Byte1]: 49
5328 00:42:08.793047
5329 00:42:08.793124 Final RX Vref Byte 0 = 61 to rank0
5330 00:42:08.796571 Final RX Vref Byte 1 = 49 to rank0
5331 00:42:08.799865 Final RX Vref Byte 0 = 61 to rank1
5332 00:42:08.803044 Final RX Vref Byte 1 = 49 to rank1==
5333 00:42:08.806447 Dram Type= 6, Freq= 0, CH_0, rank 0
5334 00:42:08.813069 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5335 00:42:08.813153 ==
5336 00:42:08.813235 DQS Delay:
5337 00:42:08.813320 DQS0 = 0, DQS1 = 0
5338 00:42:08.816414 DQM Delay:
5339 00:42:08.816522 DQM0 = 108, DQM1 = 91
5340 00:42:08.819521 DQ Delay:
5341 00:42:08.822757 DQ0 =106, DQ1 =108, DQ2 =106, DQ3 =106
5342 00:42:08.826557 DQ4 =110, DQ5 =100, DQ6 =116, DQ7 =114
5343 00:42:08.829701 DQ8 =88, DQ9 =78, DQ10 =92, DQ11 =90
5344 00:42:08.833258 DQ12 =94, DQ13 =92, DQ14 =100, DQ15 =98
5345 00:42:08.833345
5346 00:42:08.833428
5347 00:42:08.839712 [DQSOSCAuto] RK0, (LSB)MR18= 0x2723, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 409 ps
5348 00:42:08.843071 CH0 RK0: MR19=505, MR18=2723
5349 00:42:08.849723 CH0_RK0: MR19=0x505, MR18=0x2723, DQSOSC=409, MR23=63, INC=64, DEC=43
5350 00:42:08.849812
5351 00:42:08.852982 ----->DramcWriteLeveling(PI) begin...
5352 00:42:08.853068 ==
5353 00:42:08.856424 Dram Type= 6, Freq= 0, CH_0, rank 1
5354 00:42:08.860043 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5355 00:42:08.860124 ==
5356 00:42:08.862913 Write leveling (Byte 0): 30 => 30
5357 00:42:08.866230 Write leveling (Byte 1): 29 => 29
5358 00:42:08.869776 DramcWriteLeveling(PI) end<-----
5359 00:42:08.869857
5360 00:42:08.869939 ==
5361 00:42:08.873078 Dram Type= 6, Freq= 0, CH_0, rank 1
5362 00:42:08.876243 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5363 00:42:08.880051 ==
5364 00:42:08.880159 [Gating] SW mode calibration
5365 00:42:08.886656 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5366 00:42:08.893057 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5367 00:42:08.896470 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5368 00:42:08.903155 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5369 00:42:08.906367 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5370 00:42:08.909903 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5371 00:42:08.916365 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5372 00:42:08.919810 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5373 00:42:08.922856 0 14 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5374 00:42:08.929536 0 14 28 | B1->B0 | 2929 2424 | 0 0 | (1 0) (1 0)
5375 00:42:08.932778 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5376 00:42:08.935999 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5377 00:42:08.943030 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5378 00:42:08.946084 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5379 00:42:08.949227 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5380 00:42:08.956352 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5381 00:42:08.959637 0 15 24 | B1->B0 | 2323 2a29 | 0 1 | (0 0) (0 0)
5382 00:42:08.962875 0 15 28 | B1->B0 | 3d3d 3d3d | 0 0 | (1 1) (0 0)
5383 00:42:08.966217 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5384 00:42:08.972755 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5385 00:42:08.976388 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5386 00:42:08.979560 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5387 00:42:08.985982 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5388 00:42:08.989426 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5389 00:42:08.992387 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5390 00:42:08.999194 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5391 00:42:09.002610 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5392 00:42:09.005963 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5393 00:42:09.012748 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5394 00:42:09.016093 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5395 00:42:09.019423 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5396 00:42:09.026150 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5397 00:42:09.029273 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5398 00:42:09.032436 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5399 00:42:09.039051 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5400 00:42:09.042539 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5401 00:42:09.045890 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5402 00:42:09.052388 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5403 00:42:09.055835 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5404 00:42:09.059432 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5405 00:42:09.065845 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5406 00:42:09.069238 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5407 00:42:09.072402 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5408 00:42:09.075825 Total UI for P1: 0, mck2ui 16
5409 00:42:09.079087 best dqsien dly found for B0: ( 1, 2, 26)
5410 00:42:09.082292 Total UI for P1: 0, mck2ui 16
5411 00:42:09.085659 best dqsien dly found for B1: ( 1, 2, 26)
5412 00:42:09.088926 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5413 00:42:09.092667 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5414 00:42:09.092753
5415 00:42:09.095628 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5416 00:42:09.102365 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5417 00:42:09.102470 [Gating] SW calibration Done
5418 00:42:09.102536 ==
5419 00:42:09.105967 Dram Type= 6, Freq= 0, CH_0, rank 1
5420 00:42:09.112305 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5421 00:42:09.112404 ==
5422 00:42:09.112471 RX Vref Scan: 0
5423 00:42:09.112533
5424 00:42:09.115410 RX Vref 0 -> 0, step: 1
5425 00:42:09.115510
5426 00:42:09.118846 RX Delay -80 -> 252, step: 8
5427 00:42:09.122406 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5428 00:42:09.125388 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5429 00:42:09.129092 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5430 00:42:09.135466 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5431 00:42:09.138725 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5432 00:42:09.142170 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5433 00:42:09.145408 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5434 00:42:09.148857 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5435 00:42:09.152065 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5436 00:42:09.158765 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5437 00:42:09.162190 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5438 00:42:09.165197 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5439 00:42:09.168739 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5440 00:42:09.172176 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5441 00:42:09.175593 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5442 00:42:09.182083 iDelay=208, Bit 15, Center 95 (8 ~ 183) 176
5443 00:42:09.182173 ==
5444 00:42:09.185460 Dram Type= 6, Freq= 0, CH_0, rank 1
5445 00:42:09.188564 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5446 00:42:09.188652 ==
5447 00:42:09.188735 DQS Delay:
5448 00:42:09.192390 DQS0 = 0, DQS1 = 0
5449 00:42:09.192468 DQM Delay:
5450 00:42:09.195419 DQM0 = 104, DQM1 = 90
5451 00:42:09.195538 DQ Delay:
5452 00:42:09.198700 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5453 00:42:09.202246 DQ4 =107, DQ5 =95, DQ6 =115, DQ7 =111
5454 00:42:09.205561 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =87
5455 00:42:09.208483 DQ12 =95, DQ13 =91, DQ14 =99, DQ15 =95
5456 00:42:09.208596
5457 00:42:09.208665
5458 00:42:09.208727 ==
5459 00:42:09.211789 Dram Type= 6, Freq= 0, CH_0, rank 1
5460 00:42:09.215247 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5461 00:42:09.218429 ==
5462 00:42:09.218517
5463 00:42:09.218585
5464 00:42:09.218649 TX Vref Scan disable
5465 00:42:09.221650 == TX Byte 0 ==
5466 00:42:09.225195 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5467 00:42:09.228327 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5468 00:42:09.231813 == TX Byte 1 ==
5469 00:42:09.235165 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5470 00:42:09.238430 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5471 00:42:09.238537 ==
5472 00:42:09.241669 Dram Type= 6, Freq= 0, CH_0, rank 1
5473 00:42:09.248499 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5474 00:42:09.248642 ==
5475 00:42:09.248719
5476 00:42:09.248781
5477 00:42:09.248839 TX Vref Scan disable
5478 00:42:09.252870 == TX Byte 0 ==
5479 00:42:09.256109 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5480 00:42:09.259519 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5481 00:42:09.262952 == TX Byte 1 ==
5482 00:42:09.265903 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5483 00:42:09.272971 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5484 00:42:09.273127
5485 00:42:09.273199 [DATLAT]
5486 00:42:09.273262 Freq=933, CH0 RK1
5487 00:42:09.273322
5488 00:42:09.275872 DATLAT Default: 0xb
5489 00:42:09.276090 0, 0xFFFF, sum = 0
5490 00:42:09.279132 1, 0xFFFF, sum = 0
5491 00:42:09.279281 2, 0xFFFF, sum = 0
5492 00:42:09.282806 3, 0xFFFF, sum = 0
5493 00:42:09.282916 4, 0xFFFF, sum = 0
5494 00:42:09.285896 5, 0xFFFF, sum = 0
5495 00:42:09.289476 6, 0xFFFF, sum = 0
5496 00:42:09.289600 7, 0xFFFF, sum = 0
5497 00:42:09.292666 8, 0xFFFF, sum = 0
5498 00:42:09.292843 9, 0xFFFF, sum = 0
5499 00:42:09.296180 10, 0x0, sum = 1
5500 00:42:09.296332 11, 0x0, sum = 2
5501 00:42:09.296435 12, 0x0, sum = 3
5502 00:42:09.299443 13, 0x0, sum = 4
5503 00:42:09.299610 best_step = 11
5504 00:42:09.299756
5505 00:42:09.299883 ==
5506 00:42:09.302811 Dram Type= 6, Freq= 0, CH_0, rank 1
5507 00:42:09.309593 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5508 00:42:09.309779 ==
5509 00:42:09.309916 RX Vref Scan: 0
5510 00:42:09.310013
5511 00:42:09.312976 RX Vref 0 -> 0, step: 1
5512 00:42:09.313103
5513 00:42:09.316253 RX Delay -53 -> 252, step: 4
5514 00:42:09.319539 iDelay=199, Bit 0, Center 104 (19 ~ 190) 172
5515 00:42:09.326498 iDelay=199, Bit 1, Center 106 (19 ~ 194) 176
5516 00:42:09.329511 iDelay=199, Bit 2, Center 102 (15 ~ 190) 176
5517 00:42:09.332980 iDelay=199, Bit 3, Center 98 (15 ~ 182) 168
5518 00:42:09.336261 iDelay=199, Bit 4, Center 104 (19 ~ 190) 172
5519 00:42:09.339707 iDelay=199, Bit 5, Center 96 (11 ~ 182) 172
5520 00:42:09.342804 iDelay=199, Bit 6, Center 110 (23 ~ 198) 176
5521 00:42:09.349712 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5522 00:42:09.353097 iDelay=199, Bit 8, Center 86 (3 ~ 170) 168
5523 00:42:09.356169 iDelay=199, Bit 9, Center 80 (-5 ~ 166) 172
5524 00:42:09.359411 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5525 00:42:09.362802 iDelay=199, Bit 11, Center 90 (7 ~ 174) 168
5526 00:42:09.366238 iDelay=199, Bit 12, Center 96 (11 ~ 182) 172
5527 00:42:09.373085 iDelay=199, Bit 13, Center 96 (15 ~ 178) 164
5528 00:42:09.376083 iDelay=199, Bit 14, Center 104 (19 ~ 190) 172
5529 00:42:09.379509 iDelay=199, Bit 15, Center 100 (19 ~ 182) 164
5530 00:42:09.379597 ==
5531 00:42:09.382883 Dram Type= 6, Freq= 0, CH_0, rank 1
5532 00:42:09.385967 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5533 00:42:09.389860 ==
5534 00:42:09.389946 DQS Delay:
5535 00:42:09.390014 DQS0 = 0, DQS1 = 0
5536 00:42:09.393142 DQM Delay:
5537 00:42:09.393234 DQM0 = 104, DQM1 = 93
5538 00:42:09.393302 DQ Delay:
5539 00:42:09.396366 DQ0 =104, DQ1 =106, DQ2 =102, DQ3 =98
5540 00:42:09.399395 DQ4 =104, DQ5 =96, DQ6 =110, DQ7 =112
5541 00:42:09.402878 DQ8 =86, DQ9 =80, DQ10 =94, DQ11 =90
5542 00:42:09.409380 DQ12 =96, DQ13 =96, DQ14 =104, DQ15 =100
5543 00:42:09.409487
5544 00:42:09.409557
5545 00:42:09.416401 [DQSOSCAuto] RK1, (LSB)MR18= 0x2e0f, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 407 ps
5546 00:42:09.419382 CH0 RK1: MR19=505, MR18=2E0F
5547 00:42:09.426112 CH0_RK1: MR19=0x505, MR18=0x2E0F, DQSOSC=407, MR23=63, INC=65, DEC=43
5548 00:42:09.429377 [RxdqsGatingPostProcess] freq 933
5549 00:42:09.432724 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5550 00:42:09.436198 best DQS0 dly(2T, 0.5T) = (0, 10)
5551 00:42:09.439615 best DQS1 dly(2T, 0.5T) = (0, 10)
5552 00:42:09.442932 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5553 00:42:09.446562 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5554 00:42:09.449639 best DQS0 dly(2T, 0.5T) = (0, 10)
5555 00:42:09.452985 best DQS1 dly(2T, 0.5T) = (0, 10)
5556 00:42:09.456440 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5557 00:42:09.459461 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5558 00:42:09.463255 Pre-setting of DQS Precalculation
5559 00:42:09.466095 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5560 00:42:09.466181 ==
5561 00:42:09.469490 Dram Type= 6, Freq= 0, CH_1, rank 0
5562 00:42:09.475952 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5563 00:42:09.476049 ==
5564 00:42:09.479355 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5565 00:42:09.486163 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5566 00:42:09.489596 [CA 0] Center 37 (7~67) winsize 61
5567 00:42:09.492479 [CA 1] Center 37 (7~68) winsize 62
5568 00:42:09.495819 [CA 2] Center 35 (5~66) winsize 62
5569 00:42:09.499469 [CA 3] Center 34 (4~65) winsize 62
5570 00:42:09.502636 [CA 4] Center 34 (4~65) winsize 62
5571 00:42:09.505837 [CA 5] Center 34 (4~64) winsize 61
5572 00:42:09.505915
5573 00:42:09.509413 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5574 00:42:09.509490
5575 00:42:09.512731 [CATrainingPosCal] consider 1 rank data
5576 00:42:09.515980 u2DelayCellTimex100 = 270/100 ps
5577 00:42:09.519036 CA0 delay=37 (7~67),Diff = 3 PI (18 cell)
5578 00:42:09.522444 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5579 00:42:09.525967 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5580 00:42:09.532574 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5581 00:42:09.535998 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5582 00:42:09.539413 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5583 00:42:09.539489
5584 00:42:09.542831 CA PerBit enable=1, Macro0, CA PI delay=34
5585 00:42:09.542904
5586 00:42:09.545770 [CBTSetCACLKResult] CA Dly = 34
5587 00:42:09.545852 CS Dly: 5 (0~36)
5588 00:42:09.545935 ==
5589 00:42:09.549335 Dram Type= 6, Freq= 0, CH_1, rank 1
5590 00:42:09.555922 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5591 00:42:09.556004 ==
5592 00:42:09.559057 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5593 00:42:09.565783 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5594 00:42:09.569136 [CA 0] Center 37 (7~68) winsize 62
5595 00:42:09.572536 [CA 1] Center 37 (7~68) winsize 62
5596 00:42:09.575942 [CA 2] Center 36 (6~66) winsize 61
5597 00:42:09.579382 [CA 3] Center 35 (5~65) winsize 61
5598 00:42:09.582408 [CA 4] Center 35 (5~65) winsize 61
5599 00:42:09.585987 [CA 5] Center 35 (5~65) winsize 61
5600 00:42:09.586071
5601 00:42:09.588900 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5602 00:42:09.588986
5603 00:42:09.592390 [CATrainingPosCal] consider 2 rank data
5604 00:42:09.595692 u2DelayCellTimex100 = 270/100 ps
5605 00:42:09.598899 CA0 delay=37 (7~67),Diff = 3 PI (18 cell)
5606 00:42:09.602538 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5607 00:42:09.608882 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5608 00:42:09.612470 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5609 00:42:09.615608 CA4 delay=35 (5~65),Diff = 1 PI (6 cell)
5610 00:42:09.619170 CA5 delay=34 (5~64),Diff = 0 PI (0 cell)
5611 00:42:09.619255
5612 00:42:09.622499 CA PerBit enable=1, Macro0, CA PI delay=34
5613 00:42:09.622584
5614 00:42:09.625410 [CBTSetCACLKResult] CA Dly = 34
5615 00:42:09.625495 CS Dly: 6 (0~38)
5616 00:42:09.625563
5617 00:42:09.628993 ----->DramcWriteLeveling(PI) begin...
5618 00:42:09.632344 ==
5619 00:42:09.635638 Dram Type= 6, Freq= 0, CH_1, rank 0
5620 00:42:09.638998 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5621 00:42:09.639083 ==
5622 00:42:09.642248 Write leveling (Byte 0): 25 => 25
5623 00:42:09.645731 Write leveling (Byte 1): 30 => 30
5624 00:42:09.648746 DramcWriteLeveling(PI) end<-----
5625 00:42:09.648842
5626 00:42:09.648918 ==
5627 00:42:09.652146 Dram Type= 6, Freq= 0, CH_1, rank 0
5628 00:42:09.655461 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5629 00:42:09.655561 ==
5630 00:42:09.658526 [Gating] SW mode calibration
5631 00:42:09.665529 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5632 00:42:09.672212 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5633 00:42:09.675524 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5634 00:42:09.678916 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5635 00:42:09.681952 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5636 00:42:09.688722 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5637 00:42:09.692200 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5638 00:42:09.695628 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5639 00:42:09.702038 0 14 24 | B1->B0 | 3030 3030 | 1 1 | (1 1) (1 0)
5640 00:42:09.705528 0 14 28 | B1->B0 | 2424 2525 | 0 0 | (1 0) (0 0)
5641 00:42:09.709099 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5642 00:42:09.715265 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5643 00:42:09.718779 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5644 00:42:09.722042 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5645 00:42:09.728661 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5646 00:42:09.731838 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5647 00:42:09.735420 0 15 24 | B1->B0 | 2727 2c2c | 0 0 | (0 0) (1 1)
5648 00:42:09.741817 0 15 28 | B1->B0 | 4141 3f3f | 0 0 | (0 0) (0 0)
5649 00:42:09.745224 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5650 00:42:09.748666 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5651 00:42:09.755414 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5652 00:42:09.758367 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5653 00:42:09.762057 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5654 00:42:09.768440 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5655 00:42:09.771889 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5656 00:42:09.775358 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5657 00:42:09.781925 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5658 00:42:09.785364 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5659 00:42:09.788720 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5660 00:42:09.792091 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5661 00:42:09.798442 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5662 00:42:09.801998 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5663 00:42:09.805568 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5664 00:42:09.811970 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5665 00:42:09.815068 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5666 00:42:09.818595 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5667 00:42:09.825206 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5668 00:42:09.828537 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5669 00:42:09.831822 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5670 00:42:09.838555 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5671 00:42:09.841733 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5672 00:42:09.844910 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5673 00:42:09.848520 Total UI for P1: 0, mck2ui 16
5674 00:42:09.851879 best dqsien dly found for B0: ( 1, 2, 22)
5675 00:42:09.855269 Total UI for P1: 0, mck2ui 16
5676 00:42:09.858680 best dqsien dly found for B1: ( 1, 2, 22)
5677 00:42:09.861680 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5678 00:42:09.864859 best DQS1 dly(MCK, UI, PI) = (1, 2, 22)
5679 00:42:09.864944
5680 00:42:09.871692 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5681 00:42:09.875102 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 22)
5682 00:42:09.875186 [Gating] SW calibration Done
5683 00:42:09.878524 ==
5684 00:42:09.881890 Dram Type= 6, Freq= 0, CH_1, rank 0
5685 00:42:09.884951 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5686 00:42:09.885064 ==
5687 00:42:09.885163 RX Vref Scan: 0
5688 00:42:09.885252
5689 00:42:09.888211 RX Vref 0 -> 0, step: 1
5690 00:42:09.888295
5691 00:42:09.891690 RX Delay -80 -> 252, step: 8
5692 00:42:09.894648 iDelay=208, Bit 0, Center 107 (24 ~ 191) 168
5693 00:42:09.898134 iDelay=208, Bit 1, Center 99 (16 ~ 183) 168
5694 00:42:09.901608 iDelay=208, Bit 2, Center 99 (16 ~ 183) 168
5695 00:42:09.908440 iDelay=208, Bit 3, Center 103 (16 ~ 191) 176
5696 00:42:09.911427 iDelay=208, Bit 4, Center 103 (16 ~ 191) 176
5697 00:42:09.915148 iDelay=208, Bit 5, Center 111 (24 ~ 199) 176
5698 00:42:09.917897 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5699 00:42:09.921479 iDelay=208, Bit 7, Center 103 (16 ~ 191) 176
5700 00:42:09.927886 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5701 00:42:09.931990 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5702 00:42:09.934607 iDelay=208, Bit 10, Center 103 (16 ~ 191) 176
5703 00:42:09.938330 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5704 00:42:09.941441 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5705 00:42:09.947891 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5706 00:42:09.950931 iDelay=208, Bit 14, Center 107 (16 ~ 199) 184
5707 00:42:09.954443 iDelay=208, Bit 15, Center 103 (16 ~ 191) 176
5708 00:42:09.954528 ==
5709 00:42:09.958083 Dram Type= 6, Freq= 0, CH_1, rank 0
5710 00:42:09.960960 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5711 00:42:09.961045 ==
5712 00:42:09.964439 DQS Delay:
5713 00:42:09.964524 DQS0 = 0, DQS1 = 0
5714 00:42:09.967646 DQM Delay:
5715 00:42:09.967730 DQM0 = 105, DQM1 = 98
5716 00:42:09.967796 DQ Delay:
5717 00:42:09.970985 DQ0 =107, DQ1 =99, DQ2 =99, DQ3 =103
5718 00:42:09.977897 DQ4 =103, DQ5 =111, DQ6 =115, DQ7 =103
5719 00:42:09.981338 DQ8 =87, DQ9 =87, DQ10 =103, DQ11 =91
5720 00:42:09.984052 DQ12 =107, DQ13 =103, DQ14 =107, DQ15 =103
5721 00:42:09.984137
5722 00:42:09.984203
5723 00:42:09.984264 ==
5724 00:42:09.987413 Dram Type= 6, Freq= 0, CH_1, rank 0
5725 00:42:09.990861 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5726 00:42:09.990946 ==
5727 00:42:09.991012
5728 00:42:09.991076
5729 00:42:09.994464 TX Vref Scan disable
5730 00:42:09.997489 == TX Byte 0 ==
5731 00:42:10.000911 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5732 00:42:10.004398 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5733 00:42:10.007399 == TX Byte 1 ==
5734 00:42:10.010810 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5735 00:42:10.014204 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5736 00:42:10.014289 ==
5737 00:42:10.017470 Dram Type= 6, Freq= 0, CH_1, rank 0
5738 00:42:10.020833 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5739 00:42:10.023790 ==
5740 00:42:10.023874
5741 00:42:10.023940
5742 00:42:10.024001 TX Vref Scan disable
5743 00:42:10.027742 == TX Byte 0 ==
5744 00:42:10.030725 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5745 00:42:10.034229 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5746 00:42:10.037776 == TX Byte 1 ==
5747 00:42:10.040843 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5748 00:42:10.044323 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5749 00:42:10.047511
5750 00:42:10.047595 [DATLAT]
5751 00:42:10.047661 Freq=933, CH1 RK0
5752 00:42:10.047723
5753 00:42:10.050968 DATLAT Default: 0xd
5754 00:42:10.051052 0, 0xFFFF, sum = 0
5755 00:42:10.054340 1, 0xFFFF, sum = 0
5756 00:42:10.054425 2, 0xFFFF, sum = 0
5757 00:42:10.057727 3, 0xFFFF, sum = 0
5758 00:42:10.057813 4, 0xFFFF, sum = 0
5759 00:42:10.061013 5, 0xFFFF, sum = 0
5760 00:42:10.061099 6, 0xFFFF, sum = 0
5761 00:42:10.064079 7, 0xFFFF, sum = 0
5762 00:42:10.067565 8, 0xFFFF, sum = 0
5763 00:42:10.067650 9, 0xFFFF, sum = 0
5764 00:42:10.071011 10, 0x0, sum = 1
5765 00:42:10.071096 11, 0x0, sum = 2
5766 00:42:10.071164 12, 0x0, sum = 3
5767 00:42:10.074349 13, 0x0, sum = 4
5768 00:42:10.074435 best_step = 11
5769 00:42:10.074501
5770 00:42:10.074561 ==
5771 00:42:10.077499 Dram Type= 6, Freq= 0, CH_1, rank 0
5772 00:42:10.084462 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5773 00:42:10.084559 ==
5774 00:42:10.084659 RX Vref Scan: 1
5775 00:42:10.084755
5776 00:42:10.087665 RX Vref 0 -> 0, step: 1
5777 00:42:10.087749
5778 00:42:10.090891 RX Delay -45 -> 252, step: 4
5779 00:42:10.090977
5780 00:42:10.094384 Set Vref, RX VrefLevel [Byte0]: 52
5781 00:42:10.097815 [Byte1]: 53
5782 00:42:10.097906
5783 00:42:10.100779 Final RX Vref Byte 0 = 52 to rank0
5784 00:42:10.104204 Final RX Vref Byte 1 = 53 to rank0
5785 00:42:10.107669 Final RX Vref Byte 0 = 52 to rank1
5786 00:42:10.110785 Final RX Vref Byte 1 = 53 to rank1==
5787 00:42:10.114224 Dram Type= 6, Freq= 0, CH_1, rank 0
5788 00:42:10.117733 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5789 00:42:10.117818 ==
5790 00:42:10.120709 DQS Delay:
5791 00:42:10.120793 DQS0 = 0, DQS1 = 0
5792 00:42:10.124201 DQM Delay:
5793 00:42:10.124284 DQM0 = 107, DQM1 = 101
5794 00:42:10.124350 DQ Delay:
5795 00:42:10.127431 DQ0 =110, DQ1 =102, DQ2 =100, DQ3 =106
5796 00:42:10.130731 DQ4 =108, DQ5 =116, DQ6 =116, DQ7 =104
5797 00:42:10.137621 DQ8 =92, DQ9 =90, DQ10 =104, DQ11 =94
5798 00:42:10.140941 DQ12 =110, DQ13 =104, DQ14 =108, DQ15 =106
5799 00:42:10.141025
5800 00:42:10.141089
5801 00:42:10.147498 [DQSOSCAuto] RK0, (LSB)MR18= 0x1c35, (MSB)MR19= 0x505, tDQSOscB0 = 405 ps tDQSOscB1 = 412 ps
5802 00:42:10.150858 CH1 RK0: MR19=505, MR18=1C35
5803 00:42:10.157615 CH1_RK0: MR19=0x505, MR18=0x1C35, DQSOSC=405, MR23=63, INC=66, DEC=44
5804 00:42:10.157700
5805 00:42:10.160799 ----->DramcWriteLeveling(PI) begin...
5806 00:42:10.160884 ==
5807 00:42:10.164088 Dram Type= 6, Freq= 0, CH_1, rank 1
5808 00:42:10.167691 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5809 00:42:10.167775 ==
5810 00:42:10.170944 Write leveling (Byte 0): 27 => 27
5811 00:42:10.174272 Write leveling (Byte 1): 25 => 25
5812 00:42:10.177416 DramcWriteLeveling(PI) end<-----
5813 00:42:10.177500
5814 00:42:10.177565 ==
5815 00:42:10.180570 Dram Type= 6, Freq= 0, CH_1, rank 1
5816 00:42:10.184100 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5817 00:42:10.184184 ==
5818 00:42:10.187642 [Gating] SW mode calibration
5819 00:42:10.194124 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5820 00:42:10.200952 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5821 00:42:10.204431 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5822 00:42:10.207711 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5823 00:42:10.214040 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5824 00:42:10.217398 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5825 00:42:10.220883 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5826 00:42:10.227365 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5827 00:42:10.230717 0 14 24 | B1->B0 | 3232 3434 | 0 1 | (0 1) (1 0)
5828 00:42:10.234355 0 14 28 | B1->B0 | 2525 2f2f | 0 1 | (1 0) (1 0)
5829 00:42:10.240510 0 15 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5830 00:42:10.244020 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5831 00:42:10.247493 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5832 00:42:10.254176 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5833 00:42:10.257685 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5834 00:42:10.260515 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5835 00:42:10.267404 0 15 24 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)
5836 00:42:10.270752 0 15 28 | B1->B0 | 3c3c 3636 | 0 0 | (0 0) (0 0)
5837 00:42:10.274053 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5838 00:42:10.280807 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5839 00:42:10.283827 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5840 00:42:10.287226 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5841 00:42:10.293924 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5842 00:42:10.297156 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5843 00:42:10.300476 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5844 00:42:10.307409 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5845 00:42:10.310477 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5846 00:42:10.313894 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5847 00:42:10.320570 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5848 00:42:10.323963 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5849 00:42:10.327360 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5850 00:42:10.334055 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5851 00:42:10.338004 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5852 00:42:10.341149 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5853 00:42:10.344227 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5854 00:42:10.351103 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5855 00:42:10.354316 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5856 00:42:10.357681 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5857 00:42:10.363985 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5858 00:42:10.367458 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5859 00:42:10.370950 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5860 00:42:10.374342 Total UI for P1: 0, mck2ui 16
5861 00:42:10.377480 best dqsien dly found for B1: ( 1, 2, 22)
5862 00:42:10.384140 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5863 00:42:10.387526 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5864 00:42:10.391005 Total UI for P1: 0, mck2ui 16
5865 00:42:10.394111 best dqsien dly found for B0: ( 1, 2, 26)
5866 00:42:10.397515 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5867 00:42:10.400848 best DQS1 dly(MCK, UI, PI) = (1, 2, 22)
5868 00:42:10.401287
5869 00:42:10.404192 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5870 00:42:10.407524 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 22)
5871 00:42:10.411212 [Gating] SW calibration Done
5872 00:42:10.411741 ==
5873 00:42:10.413837 Dram Type= 6, Freq= 0, CH_1, rank 1
5874 00:42:10.417200 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5875 00:42:10.420771 ==
5876 00:42:10.421202 RX Vref Scan: 0
5877 00:42:10.421538
5878 00:42:10.423805 RX Vref 0 -> 0, step: 1
5879 00:42:10.424231
5880 00:42:10.427457 RX Delay -80 -> 252, step: 8
5881 00:42:10.430325 iDelay=200, Bit 0, Center 111 (32 ~ 191) 160
5882 00:42:10.433858 iDelay=200, Bit 1, Center 99 (16 ~ 183) 168
5883 00:42:10.437476 iDelay=200, Bit 2, Center 95 (16 ~ 175) 160
5884 00:42:10.440997 iDelay=200, Bit 3, Center 103 (16 ~ 191) 176
5885 00:42:10.447306 iDelay=200, Bit 4, Center 103 (16 ~ 191) 176
5886 00:42:10.450336 iDelay=200, Bit 5, Center 115 (32 ~ 199) 168
5887 00:42:10.453851 iDelay=200, Bit 6, Center 115 (32 ~ 199) 168
5888 00:42:10.457140 iDelay=200, Bit 7, Center 103 (16 ~ 191) 176
5889 00:42:10.460263 iDelay=200, Bit 8, Center 83 (-8 ~ 175) 184
5890 00:42:10.463597 iDelay=200, Bit 9, Center 91 (8 ~ 175) 168
5891 00:42:10.470319 iDelay=200, Bit 10, Center 103 (16 ~ 191) 176
5892 00:42:10.473755 iDelay=200, Bit 11, Center 95 (8 ~ 183) 176
5893 00:42:10.476952 iDelay=200, Bit 12, Center 107 (16 ~ 199) 184
5894 00:42:10.479984 iDelay=200, Bit 13, Center 107 (16 ~ 199) 184
5895 00:42:10.486841 iDelay=200, Bit 14, Center 107 (16 ~ 199) 184
5896 00:42:10.490104 iDelay=200, Bit 15, Center 107 (16 ~ 199) 184
5897 00:42:10.490533 ==
5898 00:42:10.493326 Dram Type= 6, Freq= 0, CH_1, rank 1
5899 00:42:10.496937 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5900 00:42:10.497432 ==
5901 00:42:10.497777 DQS Delay:
5902 00:42:10.500014 DQS0 = 0, DQS1 = 0
5903 00:42:10.500439 DQM Delay:
5904 00:42:10.503456 DQM0 = 105, DQM1 = 100
5905 00:42:10.503881 DQ Delay:
5906 00:42:10.507198 DQ0 =111, DQ1 =99, DQ2 =95, DQ3 =103
5907 00:42:10.510678 DQ4 =103, DQ5 =115, DQ6 =115, DQ7 =103
5908 00:42:10.514001 DQ8 =83, DQ9 =91, DQ10 =103, DQ11 =95
5909 00:42:10.516899 DQ12 =107, DQ13 =107, DQ14 =107, DQ15 =107
5910 00:42:10.517326
5911 00:42:10.517716
5912 00:42:10.520338 ==
5913 00:42:10.523688 Dram Type= 6, Freq= 0, CH_1, rank 1
5914 00:42:10.527276 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5915 00:42:10.527810 ==
5916 00:42:10.528151
5917 00:42:10.528456
5918 00:42:10.530060 TX Vref Scan disable
5919 00:42:10.530484 == TX Byte 0 ==
5920 00:42:10.533713 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5921 00:42:10.540717 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5922 00:42:10.541244 == TX Byte 1 ==
5923 00:42:10.543562 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5924 00:42:10.550402 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5925 00:42:10.550935 ==
5926 00:42:10.553923 Dram Type= 6, Freq= 0, CH_1, rank 1
5927 00:42:10.556828 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5928 00:42:10.557258 ==
5929 00:42:10.557594
5930 00:42:10.557903
5931 00:42:10.560523 TX Vref Scan disable
5932 00:42:10.563313 == TX Byte 0 ==
5933 00:42:10.566690 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5934 00:42:10.569965 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5935 00:42:10.573444 == TX Byte 1 ==
5936 00:42:10.576864 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5937 00:42:10.580442 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5938 00:42:10.580996
5939 00:42:10.583167 [DATLAT]
5940 00:42:10.583588 Freq=933, CH1 RK1
5941 00:42:10.583922
5942 00:42:10.586730 DATLAT Default: 0xb
5943 00:42:10.587265 0, 0xFFFF, sum = 0
5944 00:42:10.590278 1, 0xFFFF, sum = 0
5945 00:42:10.590811 2, 0xFFFF, sum = 0
5946 00:42:10.593223 3, 0xFFFF, sum = 0
5947 00:42:10.593755 4, 0xFFFF, sum = 0
5948 00:42:10.596756 5, 0xFFFF, sum = 0
5949 00:42:10.597298 6, 0xFFFF, sum = 0
5950 00:42:10.599805 7, 0xFFFF, sum = 0
5951 00:42:10.600234 8, 0xFFFF, sum = 0
5952 00:42:10.602979 9, 0xFFFF, sum = 0
5953 00:42:10.603408 10, 0x0, sum = 1
5954 00:42:10.606712 11, 0x0, sum = 2
5955 00:42:10.607286 12, 0x0, sum = 3
5956 00:42:10.610218 13, 0x0, sum = 4
5957 00:42:10.610755 best_step = 11
5958 00:42:10.611096
5959 00:42:10.611410 ==
5960 00:42:10.613072 Dram Type= 6, Freq= 0, CH_1, rank 1
5961 00:42:10.616381 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5962 00:42:10.619875 ==
5963 00:42:10.620401 RX Vref Scan: 0
5964 00:42:10.620802
5965 00:42:10.623193 RX Vref 0 -> 0, step: 1
5966 00:42:10.623618
5967 00:42:10.626732 RX Delay -53 -> 252, step: 4
5968 00:42:10.630044 iDelay=199, Bit 0, Center 112 (39 ~ 186) 148
5969 00:42:10.633148 iDelay=199, Bit 1, Center 104 (31 ~ 178) 148
5970 00:42:10.636511 iDelay=199, Bit 2, Center 98 (23 ~ 174) 152
5971 00:42:10.643371 iDelay=199, Bit 3, Center 106 (27 ~ 186) 160
5972 00:42:10.646788 iDelay=199, Bit 4, Center 108 (31 ~ 186) 156
5973 00:42:10.649860 iDelay=199, Bit 5, Center 118 (39 ~ 198) 160
5974 00:42:10.653164 iDelay=199, Bit 6, Center 114 (35 ~ 194) 160
5975 00:42:10.656537 iDelay=199, Bit 7, Center 104 (27 ~ 182) 156
5976 00:42:10.663071 iDelay=199, Bit 8, Center 88 (7 ~ 170) 164
5977 00:42:10.666573 iDelay=199, Bit 9, Center 88 (7 ~ 170) 164
5978 00:42:10.669626 iDelay=199, Bit 10, Center 100 (19 ~ 182) 164
5979 00:42:10.672848 iDelay=199, Bit 11, Center 94 (11 ~ 178) 168
5980 00:42:10.676708 iDelay=199, Bit 12, Center 108 (27 ~ 190) 164
5981 00:42:10.683388 iDelay=199, Bit 13, Center 104 (23 ~ 186) 164
5982 00:42:10.686764 iDelay=199, Bit 14, Center 106 (19 ~ 194) 176
5983 00:42:10.689580 iDelay=199, Bit 15, Center 110 (27 ~ 194) 168
5984 00:42:10.690010 ==
5985 00:42:10.692939 Dram Type= 6, Freq= 0, CH_1, rank 1
5986 00:42:10.696238 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5987 00:42:10.696815 ==
5988 00:42:10.699410 DQS Delay:
5989 00:42:10.699855 DQS0 = 0, DQS1 = 0
5990 00:42:10.702973 DQM Delay:
5991 00:42:10.703424 DQM0 = 108, DQM1 = 99
5992 00:42:10.703815 DQ Delay:
5993 00:42:10.706381 DQ0 =112, DQ1 =104, DQ2 =98, DQ3 =106
5994 00:42:10.712937 DQ4 =108, DQ5 =118, DQ6 =114, DQ7 =104
5995 00:42:10.716305 DQ8 =88, DQ9 =88, DQ10 =100, DQ11 =94
5996 00:42:10.719655 DQ12 =108, DQ13 =104, DQ14 =106, DQ15 =110
5997 00:42:10.720084
5998 00:42:10.720419
5999 00:42:10.726338 [DQSOSCAuto] RK1, (LSB)MR18= 0x2200, (MSB)MR19= 0x505, tDQSOscB0 = 422 ps tDQSOscB1 = 411 ps
6000 00:42:10.729519 CH1 RK1: MR19=505, MR18=2200
6001 00:42:10.736461 CH1_RK1: MR19=0x505, MR18=0x2200, DQSOSC=411, MR23=63, INC=64, DEC=42
6002 00:42:10.739847 [RxdqsGatingPostProcess] freq 933
6003 00:42:10.743155 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6004 00:42:10.746684 best DQS0 dly(2T, 0.5T) = (0, 10)
6005 00:42:10.749567 best DQS1 dly(2T, 0.5T) = (0, 10)
6006 00:42:10.753035 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6007 00:42:10.756514 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6008 00:42:10.759892 best DQS0 dly(2T, 0.5T) = (0, 10)
6009 00:42:10.763151 best DQS1 dly(2T, 0.5T) = (0, 10)
6010 00:42:10.766587 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6011 00:42:10.769277 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6012 00:42:10.772769 Pre-setting of DQS Precalculation
6013 00:42:10.776376 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6014 00:42:10.786306 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6015 00:42:10.792733 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6016 00:42:10.793269
6017 00:42:10.793607
6018 00:42:10.796118 [Calibration Summary] 1866 Mbps
6019 00:42:10.796688 CH 0, Rank 0
6020 00:42:10.799135 SW Impedance : PASS
6021 00:42:10.799696 DUTY Scan : NO K
6022 00:42:10.802410 ZQ Calibration : PASS
6023 00:42:10.806115 Jitter Meter : NO K
6024 00:42:10.806651 CBT Training : PASS
6025 00:42:10.809380 Write leveling : PASS
6026 00:42:10.812414 RX DQS gating : PASS
6027 00:42:10.812967 RX DQ/DQS(RDDQC) : PASS
6028 00:42:10.816053 TX DQ/DQS : PASS
6029 00:42:10.819493 RX DATLAT : PASS
6030 00:42:10.819924 RX DQ/DQS(Engine): PASS
6031 00:42:10.822342 TX OE : NO K
6032 00:42:10.822773 All Pass.
6033 00:42:10.823113
6034 00:42:10.825938 CH 0, Rank 1
6035 00:42:10.826504 SW Impedance : PASS
6036 00:42:10.829178 DUTY Scan : NO K
6037 00:42:10.829604 ZQ Calibration : PASS
6038 00:42:10.832621 Jitter Meter : NO K
6039 00:42:10.836192 CBT Training : PASS
6040 00:42:10.836775 Write leveling : PASS
6041 00:42:10.839538 RX DQS gating : PASS
6042 00:42:10.842399 RX DQ/DQS(RDDQC) : PASS
6043 00:42:10.842825 TX DQ/DQS : PASS
6044 00:42:10.846112 RX DATLAT : PASS
6045 00:42:10.849527 RX DQ/DQS(Engine): PASS
6046 00:42:10.850061 TX OE : NO K
6047 00:42:10.852613 All Pass.
6048 00:42:10.853153
6049 00:42:10.853492 CH 1, Rank 0
6050 00:42:10.855787 SW Impedance : PASS
6051 00:42:10.856319 DUTY Scan : NO K
6052 00:42:10.859335 ZQ Calibration : PASS
6053 00:42:10.862744 Jitter Meter : NO K
6054 00:42:10.863277 CBT Training : PASS
6055 00:42:10.866050 Write leveling : PASS
6056 00:42:10.869431 RX DQS gating : PASS
6057 00:42:10.869964 RX DQ/DQS(RDDQC) : PASS
6058 00:42:10.872455 TX DQ/DQS : PASS
6059 00:42:10.872954 RX DATLAT : PASS
6060 00:42:10.876123 RX DQ/DQS(Engine): PASS
6061 00:42:10.879531 TX OE : NO K
6062 00:42:10.880072 All Pass.
6063 00:42:10.880413
6064 00:42:10.880788 CH 1, Rank 1
6065 00:42:10.882210 SW Impedance : PASS
6066 00:42:10.886163 DUTY Scan : NO K
6067 00:42:10.886703 ZQ Calibration : PASS
6068 00:42:10.889197 Jitter Meter : NO K
6069 00:42:10.892611 CBT Training : PASS
6070 00:42:10.893262 Write leveling : PASS
6071 00:42:10.896030 RX DQS gating : PASS
6072 00:42:10.899377 RX DQ/DQS(RDDQC) : PASS
6073 00:42:10.899962 TX DQ/DQS : PASS
6074 00:42:10.902624 RX DATLAT : PASS
6075 00:42:10.905886 RX DQ/DQS(Engine): PASS
6076 00:42:10.906339 TX OE : NO K
6077 00:42:10.906689 All Pass.
6078 00:42:10.909493
6079 00:42:10.910023 DramC Write-DBI off
6080 00:42:10.912460 PER_BANK_REFRESH: Hybrid Mode
6081 00:42:10.913082 TX_TRACKING: ON
6082 00:42:10.922277 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6083 00:42:10.925823 [FAST_K] Save calibration result to emmc
6084 00:42:10.929446 dramc_set_vcore_voltage set vcore to 650000
6085 00:42:10.932254 Read voltage for 400, 6
6086 00:42:10.932773 Vio18 = 0
6087 00:42:10.935849 Vcore = 650000
6088 00:42:10.936388 Vdram = 0
6089 00:42:10.936831 Vddq = 0
6090 00:42:10.937255 Vmddr = 0
6091 00:42:10.942598 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6092 00:42:10.949206 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6093 00:42:10.949738 MEM_TYPE=3, freq_sel=20
6094 00:42:10.952739 sv_algorithm_assistance_LP4_800
6095 00:42:10.956230 ============ PULL DRAM RESETB DOWN ============
6096 00:42:10.962458 ========== PULL DRAM RESETB DOWN end =========
6097 00:42:10.972732 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6098 00:42:10.973178 ===================================
6099 00:42:10.973522 LPDDR4 DRAM CONFIGURATION
6100 00:42:10.975582 ===================================
6101 00:42:10.976015 EX_ROW_EN[0] = 0x0
6102 00:42:10.978895 EX_ROW_EN[1] = 0x0
6103 00:42:10.979327 LP4Y_EN = 0x0
6104 00:42:10.982316 WORK_FSP = 0x0
6105 00:42:10.982749 WL = 0x2
6106 00:42:10.985739 RL = 0x2
6107 00:42:10.986177 BL = 0x2
6108 00:42:10.988518 RPST = 0x0
6109 00:42:10.992474 RD_PRE = 0x0
6110 00:42:10.992947 WR_PRE = 0x1
6111 00:42:10.995201 WR_PST = 0x0
6112 00:42:10.995632 DBI_WR = 0x0
6113 00:42:10.998827 DBI_RD = 0x0
6114 00:42:10.999361 OTF = 0x1
6115 00:42:11.001898 ===================================
6116 00:42:11.005368 ===================================
6117 00:42:11.008973 ANA top config
6118 00:42:11.009504 ===================================
6119 00:42:11.012000 DLL_ASYNC_EN = 0
6120 00:42:11.015613 ALL_SLAVE_EN = 1
6121 00:42:11.018500 NEW_RANK_MODE = 1
6122 00:42:11.021845 DLL_IDLE_MODE = 1
6123 00:42:11.022279 LP45_APHY_COMB_EN = 1
6124 00:42:11.025226 TX_ODT_DIS = 1
6125 00:42:11.029011 NEW_8X_MODE = 1
6126 00:42:11.032247 ===================================
6127 00:42:11.035634 ===================================
6128 00:42:11.038717 data_rate = 800
6129 00:42:11.042097 CKR = 1
6130 00:42:11.044999 DQ_P2S_RATIO = 4
6131 00:42:11.048626 ===================================
6132 00:42:11.049154 CA_P2S_RATIO = 4
6133 00:42:11.051806 DQ_CA_OPEN = 0
6134 00:42:11.055270 DQ_SEMI_OPEN = 1
6135 00:42:11.058398 CA_SEMI_OPEN = 1
6136 00:42:11.061561 CA_FULL_RATE = 0
6137 00:42:11.065279 DQ_CKDIV4_EN = 0
6138 00:42:11.065854 CA_CKDIV4_EN = 1
6139 00:42:11.068733 CA_PREDIV_EN = 0
6140 00:42:11.071869 PH8_DLY = 0
6141 00:42:11.074982 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6142 00:42:11.078293 DQ_AAMCK_DIV = 0
6143 00:42:11.081882 CA_AAMCK_DIV = 0
6144 00:42:11.082409 CA_ADMCK_DIV = 4
6145 00:42:11.085097 DQ_TRACK_CA_EN = 0
6146 00:42:11.088414 CA_PICK = 800
6147 00:42:11.092062 CA_MCKIO = 400
6148 00:42:11.095234 MCKIO_SEMI = 400
6149 00:42:11.098467 PLL_FREQ = 3016
6150 00:42:11.101398 DQ_UI_PI_RATIO = 32
6151 00:42:11.102072 CA_UI_PI_RATIO = 32
6152 00:42:11.104732 ===================================
6153 00:42:11.108300 ===================================
6154 00:42:11.111617 memory_type:LPDDR4
6155 00:42:11.115291 GP_NUM : 10
6156 00:42:11.115865 SRAM_EN : 1
6157 00:42:11.118022 MD32_EN : 0
6158 00:42:11.121600 ===================================
6159 00:42:11.124718 [ANA_INIT] >>>>>>>>>>>>>>
6160 00:42:11.128367 <<<<<< [CONFIGURE PHASE]: ANA_TX
6161 00:42:11.131511 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6162 00:42:11.134818 ===================================
6163 00:42:11.135364 data_rate = 800,PCW = 0X7400
6164 00:42:11.138209 ===================================
6165 00:42:11.141097 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6166 00:42:11.147793 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6167 00:42:11.161152 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6168 00:42:11.164484 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6169 00:42:11.167471 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6170 00:42:11.170864 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6171 00:42:11.174202 [ANA_INIT] flow start
6172 00:42:11.174656 [ANA_INIT] PLL >>>>>>>>
6173 00:42:11.177437 [ANA_INIT] PLL <<<<<<<<
6174 00:42:11.180806 [ANA_INIT] MIDPI >>>>>>>>
6175 00:42:11.181240 [ANA_INIT] MIDPI <<<<<<<<
6176 00:42:11.184141 [ANA_INIT] DLL >>>>>>>>
6177 00:42:11.187597 [ANA_INIT] flow end
6178 00:42:11.191163 ============ LP4 DIFF to SE enter ============
6179 00:42:11.194850 ============ LP4 DIFF to SE exit ============
6180 00:42:11.197813 [ANA_INIT] <<<<<<<<<<<<<
6181 00:42:11.201128 [Flow] Enable top DCM control >>>>>
6182 00:42:11.204402 [Flow] Enable top DCM control <<<<<
6183 00:42:11.208220 Enable DLL master slave shuffle
6184 00:42:11.210907 ==============================================================
6185 00:42:11.214633 Gating Mode config
6186 00:42:11.221012 ==============================================================
6187 00:42:11.221449 Config description:
6188 00:42:11.230969 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6189 00:42:11.237702 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6190 00:42:11.240994 SELPH_MODE 0: By rank 1: By Phase
6191 00:42:11.247913 ==============================================================
6192 00:42:11.251212 GAT_TRACK_EN = 0
6193 00:42:11.254643 RX_GATING_MODE = 2
6194 00:42:11.257754 RX_GATING_TRACK_MODE = 2
6195 00:42:11.260985 SELPH_MODE = 1
6196 00:42:11.264013 PICG_EARLY_EN = 1
6197 00:42:11.267655 VALID_LAT_VALUE = 1
6198 00:42:11.271251 ==============================================================
6199 00:42:11.274626 Enter into Gating configuration >>>>
6200 00:42:11.277357 Exit from Gating configuration <<<<
6201 00:42:11.280649 Enter into DVFS_PRE_config >>>>>
6202 00:42:11.291371 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6203 00:42:11.294249 Exit from DVFS_PRE_config <<<<<
6204 00:42:11.297451 Enter into PICG configuration >>>>
6205 00:42:11.301142 Exit from PICG configuration <<<<
6206 00:42:11.304391 [RX_INPUT] configuration >>>>>
6207 00:42:11.308130 [RX_INPUT] configuration <<<<<
6208 00:42:11.314289 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6209 00:42:11.317512 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6210 00:42:11.324153 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6211 00:42:11.331115 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6212 00:42:11.337710 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6213 00:42:11.344351 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6214 00:42:11.347695 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6215 00:42:11.350794 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6216 00:42:11.354539 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6217 00:42:11.361073 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6218 00:42:11.364629 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6219 00:42:11.367689 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6220 00:42:11.370877 ===================================
6221 00:42:11.374177 LPDDR4 DRAM CONFIGURATION
6222 00:42:11.377230 ===================================
6223 00:42:11.377710 EX_ROW_EN[0] = 0x0
6224 00:42:11.380779 EX_ROW_EN[1] = 0x0
6225 00:42:11.381348 LP4Y_EN = 0x0
6226 00:42:11.384154 WORK_FSP = 0x0
6227 00:42:11.384852 WL = 0x2
6228 00:42:11.387300 RL = 0x2
6229 00:42:11.391150 BL = 0x2
6230 00:42:11.391734 RPST = 0x0
6231 00:42:11.394367 RD_PRE = 0x0
6232 00:42:11.394937 WR_PRE = 0x1
6233 00:42:11.397759 WR_PST = 0x0
6234 00:42:11.398342 DBI_WR = 0x0
6235 00:42:11.400706 DBI_RD = 0x0
6236 00:42:11.401268 OTF = 0x1
6237 00:42:11.403905 ===================================
6238 00:42:11.407255 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6239 00:42:11.414071 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6240 00:42:11.417500 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6241 00:42:11.420805 ===================================
6242 00:42:11.424058 LPDDR4 DRAM CONFIGURATION
6243 00:42:11.427440 ===================================
6244 00:42:11.428012 EX_ROW_EN[0] = 0x10
6245 00:42:11.430920 EX_ROW_EN[1] = 0x0
6246 00:42:11.431492 LP4Y_EN = 0x0
6247 00:42:11.433906 WORK_FSP = 0x0
6248 00:42:11.434476 WL = 0x2
6249 00:42:11.437256 RL = 0x2
6250 00:42:11.437821 BL = 0x2
6251 00:42:11.440789 RPST = 0x0
6252 00:42:11.441355 RD_PRE = 0x0
6253 00:42:11.443869 WR_PRE = 0x1
6254 00:42:11.447196 WR_PST = 0x0
6255 00:42:11.447766 DBI_WR = 0x0
6256 00:42:11.450611 DBI_RD = 0x0
6257 00:42:11.451182 OTF = 0x1
6258 00:42:11.453723 ===================================
6259 00:42:11.460818 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6260 00:42:11.464312 nWR fixed to 30
6261 00:42:11.467517 [ModeRegInit_LP4] CH0 RK0
6262 00:42:11.468089 [ModeRegInit_LP4] CH0 RK1
6263 00:42:11.470966 [ModeRegInit_LP4] CH1 RK0
6264 00:42:11.473943 [ModeRegInit_LP4] CH1 RK1
6265 00:42:11.474409 match AC timing 19
6266 00:42:11.480652 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6267 00:42:11.483732 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6268 00:42:11.487169 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6269 00:42:11.494201 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6270 00:42:11.497372 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6271 00:42:11.497843 ==
6272 00:42:11.501110 Dram Type= 6, Freq= 0, CH_0, rank 0
6273 00:42:11.503814 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6274 00:42:11.504286 ==
6275 00:42:11.510770 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6276 00:42:11.517139 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6277 00:42:11.520684 [CA 0] Center 36 (8~64) winsize 57
6278 00:42:11.523992 [CA 1] Center 36 (8~64) winsize 57
6279 00:42:11.527355 [CA 2] Center 36 (8~64) winsize 57
6280 00:42:11.527928 [CA 3] Center 36 (8~64) winsize 57
6281 00:42:11.530559 [CA 4] Center 36 (8~64) winsize 57
6282 00:42:11.533691 [CA 5] Center 36 (8~64) winsize 57
6283 00:42:11.534256
6284 00:42:11.537544 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6285 00:42:11.540648
6286 00:42:11.544148 [CATrainingPosCal] consider 1 rank data
6287 00:42:11.544776 u2DelayCellTimex100 = 270/100 ps
6288 00:42:11.550731 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6289 00:42:11.554081 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6290 00:42:11.557485 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6291 00:42:11.560931 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6292 00:42:11.563916 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6293 00:42:11.567723 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6294 00:42:11.568299
6295 00:42:11.570654 CA PerBit enable=1, Macro0, CA PI delay=36
6296 00:42:11.571226
6297 00:42:11.573940 [CBTSetCACLKResult] CA Dly = 36
6298 00:42:11.577341 CS Dly: 1 (0~32)
6299 00:42:11.577914 ==
6300 00:42:11.580492 Dram Type= 6, Freq= 0, CH_0, rank 1
6301 00:42:11.583905 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6302 00:42:11.584475 ==
6303 00:42:11.590184 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6304 00:42:11.593662 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6305 00:42:11.597057 [CA 0] Center 36 (8~64) winsize 57
6306 00:42:11.600452 [CA 1] Center 36 (8~64) winsize 57
6307 00:42:11.603657 [CA 2] Center 36 (8~64) winsize 57
6308 00:42:11.606978 [CA 3] Center 36 (8~64) winsize 57
6309 00:42:11.610646 [CA 4] Center 36 (8~64) winsize 57
6310 00:42:11.613756 [CA 5] Center 36 (8~64) winsize 57
6311 00:42:11.614235
6312 00:42:11.616765 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6313 00:42:11.617246
6314 00:42:11.620457 [CATrainingPosCal] consider 2 rank data
6315 00:42:11.623634 u2DelayCellTimex100 = 270/100 ps
6316 00:42:11.627143 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6317 00:42:11.630629 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6318 00:42:11.633655 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6319 00:42:11.640419 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6320 00:42:11.643906 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6321 00:42:11.646923 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6322 00:42:11.647507
6323 00:42:11.649888 CA PerBit enable=1, Macro0, CA PI delay=36
6324 00:42:11.650368
6325 00:42:11.653533 [CBTSetCACLKResult] CA Dly = 36
6326 00:42:11.654116 CS Dly: 1 (0~32)
6327 00:42:11.654497
6328 00:42:11.656972 ----->DramcWriteLeveling(PI) begin...
6329 00:42:11.657561 ==
6330 00:42:11.660342 Dram Type= 6, Freq= 0, CH_0, rank 0
6331 00:42:11.666914 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6332 00:42:11.667496 ==
6333 00:42:11.670280 Write leveling (Byte 0): 40 => 8
6334 00:42:11.673487 Write leveling (Byte 1): 32 => 0
6335 00:42:11.673986 DramcWriteLeveling(PI) end<-----
6336 00:42:11.674363
6337 00:42:11.676686 ==
6338 00:42:11.679910 Dram Type= 6, Freq= 0, CH_0, rank 0
6339 00:42:11.683461 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6340 00:42:11.684046 ==
6341 00:42:11.686636 [Gating] SW mode calibration
6342 00:42:11.693308 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6343 00:42:11.696331 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6344 00:42:11.703065 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6345 00:42:11.706355 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6346 00:42:11.709597 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6347 00:42:11.716523 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6348 00:42:11.719835 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6349 00:42:11.723380 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6350 00:42:11.729555 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6351 00:42:11.733137 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6352 00:42:11.736057 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6353 00:42:11.739680 Total UI for P1: 0, mck2ui 16
6354 00:42:11.742867 best dqsien dly found for B0: ( 0, 14, 24)
6355 00:42:11.746243 Total UI for P1: 0, mck2ui 16
6356 00:42:11.749614 best dqsien dly found for B1: ( 0, 14, 24)
6357 00:42:11.753055 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6358 00:42:11.755850 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6359 00:42:11.759537
6360 00:42:11.762627 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6361 00:42:11.765929 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6362 00:42:11.769375 [Gating] SW calibration Done
6363 00:42:11.769818 ==
6364 00:42:11.772379 Dram Type= 6, Freq= 0, CH_0, rank 0
6365 00:42:11.775787 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6366 00:42:11.776202 ==
6367 00:42:11.776523 RX Vref Scan: 0
6368 00:42:11.778803
6369 00:42:11.779237 RX Vref 0 -> 0, step: 1
6370 00:42:11.779564
6371 00:42:11.782194 RX Delay -410 -> 252, step: 16
6372 00:42:11.785916 iDelay=230, Bit 0, Center -11 (-234 ~ 213) 448
6373 00:42:11.792365 iDelay=230, Bit 1, Center -3 (-234 ~ 229) 464
6374 00:42:11.795672 iDelay=230, Bit 2, Center -11 (-234 ~ 213) 448
6375 00:42:11.799160 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6376 00:42:11.802478 iDelay=230, Bit 4, Center -3 (-234 ~ 229) 464
6377 00:42:11.809093 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6378 00:42:11.812454 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6379 00:42:11.815837 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6380 00:42:11.818714 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6381 00:42:11.822198 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6382 00:42:11.829348 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6383 00:42:11.832190 iDelay=230, Bit 11, Center -43 (-282 ~ 197) 480
6384 00:42:11.835654 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6385 00:42:11.842808 iDelay=230, Bit 13, Center -27 (-266 ~ 213) 480
6386 00:42:11.845620 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6387 00:42:11.849203 iDelay=230, Bit 15, Center -27 (-266 ~ 213) 480
6388 00:42:11.849761 ==
6389 00:42:11.852723 Dram Type= 6, Freq= 0, CH_0, rank 0
6390 00:42:11.855995 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6391 00:42:11.856588 ==
6392 00:42:11.859231 DQS Delay:
6393 00:42:11.859784 DQS0 = 27, DQS1 = 43
6394 00:42:11.862529 DQM Delay:
6395 00:42:11.863087 DQM0 = 17, DQM1 = 11
6396 00:42:11.865265 DQ Delay:
6397 00:42:11.865720 DQ0 =16, DQ1 =24, DQ2 =16, DQ3 =8
6398 00:42:11.868945 DQ4 =24, DQ5 =0, DQ6 =24, DQ7 =24
6399 00:42:11.872350 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6400 00:42:11.875772 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6401 00:42:11.876334
6402 00:42:11.876738
6403 00:42:11.878735 ==
6404 00:42:11.879193 Dram Type= 6, Freq= 0, CH_0, rank 0
6405 00:42:11.885741 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6406 00:42:11.886300 ==
6407 00:42:11.886663
6408 00:42:11.886991
6409 00:42:11.888872 TX Vref Scan disable
6410 00:42:11.889328 == TX Byte 0 ==
6411 00:42:11.892628 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6412 00:42:11.898804 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6413 00:42:11.899365 == TX Byte 1 ==
6414 00:42:11.902051 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6415 00:42:11.908667 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6416 00:42:11.909128 ==
6417 00:42:11.912232 Dram Type= 6, Freq= 0, CH_0, rank 0
6418 00:42:11.915344 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6419 00:42:11.915904 ==
6420 00:42:11.916266
6421 00:42:11.916639
6422 00:42:11.918738 TX Vref Scan disable
6423 00:42:11.919248 == TX Byte 0 ==
6424 00:42:11.922107 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6425 00:42:11.928716 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6426 00:42:11.929336 == TX Byte 1 ==
6427 00:42:11.932303 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6428 00:42:11.938896 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6429 00:42:11.939493
6430 00:42:11.939856 [DATLAT]
6431 00:42:11.940193 Freq=400, CH0 RK0
6432 00:42:11.940515
6433 00:42:11.941793 DATLAT Default: 0xf
6434 00:42:11.945507 0, 0xFFFF, sum = 0
6435 00:42:11.946076 1, 0xFFFF, sum = 0
6436 00:42:11.948862 2, 0xFFFF, sum = 0
6437 00:42:11.949433 3, 0xFFFF, sum = 0
6438 00:42:11.952049 4, 0xFFFF, sum = 0
6439 00:42:11.952657 5, 0xFFFF, sum = 0
6440 00:42:11.955480 6, 0xFFFF, sum = 0
6441 00:42:11.956052 7, 0xFFFF, sum = 0
6442 00:42:11.958952 8, 0xFFFF, sum = 0
6443 00:42:11.959524 9, 0xFFFF, sum = 0
6444 00:42:11.962017 10, 0xFFFF, sum = 0
6445 00:42:11.962589 11, 0xFFFF, sum = 0
6446 00:42:11.965266 12, 0xFFFF, sum = 0
6447 00:42:11.965984 13, 0x0, sum = 1
6448 00:42:11.969186 14, 0x0, sum = 2
6449 00:42:11.969821 15, 0x0, sum = 3
6450 00:42:11.972252 16, 0x0, sum = 4
6451 00:42:11.972901 best_step = 14
6452 00:42:11.973274
6453 00:42:11.973612 ==
6454 00:42:11.975262 Dram Type= 6, Freq= 0, CH_0, rank 0
6455 00:42:11.978466 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6456 00:42:11.981796 ==
6457 00:42:11.982454 RX Vref Scan: 1
6458 00:42:11.982847
6459 00:42:11.985465 RX Vref 0 -> 0, step: 1
6460 00:42:11.986036
6461 00:42:11.988624 RX Delay -327 -> 252, step: 8
6462 00:42:11.989097
6463 00:42:11.991926 Set Vref, RX VrefLevel [Byte0]: 61
6464 00:42:11.995341 [Byte1]: 49
6465 00:42:11.995814
6466 00:42:11.998629 Final RX Vref Byte 0 = 61 to rank0
6467 00:42:12.001841 Final RX Vref Byte 1 = 49 to rank0
6468 00:42:12.005111 Final RX Vref Byte 0 = 61 to rank1
6469 00:42:12.008790 Final RX Vref Byte 1 = 49 to rank1==
6470 00:42:12.011977 Dram Type= 6, Freq= 0, CH_0, rank 0
6471 00:42:12.015252 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6472 00:42:12.015830 ==
6473 00:42:12.018418 DQS Delay:
6474 00:42:12.018950 DQS0 = 28, DQS1 = 48
6475 00:42:12.021493 DQM Delay:
6476 00:42:12.021963 DQM0 = 11, DQM1 = 15
6477 00:42:12.022337 DQ Delay:
6478 00:42:12.025158 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =8
6479 00:42:12.028379 DQ4 =12, DQ5 =0, DQ6 =24, DQ7 =20
6480 00:42:12.032093 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =12
6481 00:42:12.035159 DQ12 =20, DQ13 =16, DQ14 =28, DQ15 =24
6482 00:42:12.035717
6483 00:42:12.036087
6484 00:42:12.045490 [DQSOSCAuto] RK0, (LSB)MR18= 0xb8ae, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 386 ps
6485 00:42:12.046071 CH0 RK0: MR19=C0C, MR18=B8AE
6486 00:42:12.052178 CH0_RK0: MR19=0xC0C, MR18=0xB8AE, DQSOSC=386, MR23=63, INC=396, DEC=264
6487 00:42:12.052824 ==
6488 00:42:12.055258 Dram Type= 6, Freq= 0, CH_0, rank 1
6489 00:42:12.062055 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6490 00:42:12.062627 ==
6491 00:42:12.065092 [Gating] SW mode calibration
6492 00:42:12.072070 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6493 00:42:12.075389 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6494 00:42:12.081685 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6495 00:42:12.085313 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6496 00:42:12.088794 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6497 00:42:12.095357 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6498 00:42:12.098732 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6499 00:42:12.102123 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6500 00:42:12.104938 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6501 00:42:12.111909 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6502 00:42:12.115317 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6503 00:42:12.118436 Total UI for P1: 0, mck2ui 16
6504 00:42:12.121578 best dqsien dly found for B0: ( 0, 14, 24)
6505 00:42:12.125082 Total UI for P1: 0, mck2ui 16
6506 00:42:12.128371 best dqsien dly found for B1: ( 0, 14, 24)
6507 00:42:12.131676 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6508 00:42:12.135163 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6509 00:42:12.135765
6510 00:42:12.138381 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6511 00:42:12.145117 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6512 00:42:12.145687 [Gating] SW calibration Done
6513 00:42:12.146065 ==
6514 00:42:12.148472 Dram Type= 6, Freq= 0, CH_0, rank 1
6515 00:42:12.154934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6516 00:42:12.155505 ==
6517 00:42:12.155880 RX Vref Scan: 0
6518 00:42:12.156224
6519 00:42:12.158140 RX Vref 0 -> 0, step: 1
6520 00:42:12.158704
6521 00:42:12.162020 RX Delay -410 -> 252, step: 16
6522 00:42:12.164796 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6523 00:42:12.168364 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6524 00:42:12.174866 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6525 00:42:12.178392 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6526 00:42:12.181546 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6527 00:42:12.185161 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6528 00:42:12.191816 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6529 00:42:12.194948 iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480
6530 00:42:12.198333 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6531 00:42:12.201228 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6532 00:42:12.207938 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6533 00:42:12.211380 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6534 00:42:12.214800 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6535 00:42:12.218268 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6536 00:42:12.224729 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6537 00:42:12.228031 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6538 00:42:12.228613 ==
6539 00:42:12.231489 Dram Type= 6, Freq= 0, CH_0, rank 1
6540 00:42:12.234643 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6541 00:42:12.235166 ==
6542 00:42:12.238486 DQS Delay:
6543 00:42:12.238925 DQS0 = 27, DQS1 = 43
6544 00:42:12.239356 DQM Delay:
6545 00:42:12.241264 DQM0 = 9, DQM1 = 16
6546 00:42:12.241699 DQ Delay:
6547 00:42:12.244825 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6548 00:42:12.248094 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6549 00:42:12.251304 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =16
6550 00:42:12.254791 DQ12 =16, DQ13 =24, DQ14 =24, DQ15 =24
6551 00:42:12.255333
6552 00:42:12.255772
6553 00:42:12.256175 ==
6554 00:42:12.258275 Dram Type= 6, Freq= 0, CH_0, rank 1
6555 00:42:12.261431 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6556 00:42:12.261971 ==
6557 00:42:12.264860
6558 00:42:12.265400
6559 00:42:12.265834 TX Vref Scan disable
6560 00:42:12.268032 == TX Byte 0 ==
6561 00:42:12.271412 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6562 00:42:12.274810 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6563 00:42:12.278277 == TX Byte 1 ==
6564 00:42:12.281391 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6565 00:42:12.284921 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6566 00:42:12.285462 ==
6567 00:42:12.288369 Dram Type= 6, Freq= 0, CH_0, rank 1
6568 00:42:12.291743 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6569 00:42:12.292288 ==
6570 00:42:12.294808
6571 00:42:12.295240
6572 00:42:12.295683 TX Vref Scan disable
6573 00:42:12.298103 == TX Byte 0 ==
6574 00:42:12.301621 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6575 00:42:12.304626 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6576 00:42:12.307832 == TX Byte 1 ==
6577 00:42:12.311100 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6578 00:42:12.314780 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6579 00:42:12.315322
6580 00:42:12.315760 [DATLAT]
6581 00:42:12.317762 Freq=400, CH0 RK1
6582 00:42:12.318196
6583 00:42:12.318623 DATLAT Default: 0xe
6584 00:42:12.321273 0, 0xFFFF, sum = 0
6585 00:42:12.324737 1, 0xFFFF, sum = 0
6586 00:42:12.325184 2, 0xFFFF, sum = 0
6587 00:42:12.328051 3, 0xFFFF, sum = 0
6588 00:42:12.328628 4, 0xFFFF, sum = 0
6589 00:42:12.331354 5, 0xFFFF, sum = 0
6590 00:42:12.331900 6, 0xFFFF, sum = 0
6591 00:42:12.334567 7, 0xFFFF, sum = 0
6592 00:42:12.335121 8, 0xFFFF, sum = 0
6593 00:42:12.338188 9, 0xFFFF, sum = 0
6594 00:42:12.338737 10, 0xFFFF, sum = 0
6595 00:42:12.341086 11, 0xFFFF, sum = 0
6596 00:42:12.341529 12, 0xFFFF, sum = 0
6597 00:42:12.344627 13, 0x0, sum = 1
6598 00:42:12.345185 14, 0x0, sum = 2
6599 00:42:12.348155 15, 0x0, sum = 3
6600 00:42:12.348726 16, 0x0, sum = 4
6601 00:42:12.351460 best_step = 14
6602 00:42:12.352026
6603 00:42:12.352470 ==
6604 00:42:12.354953 Dram Type= 6, Freq= 0, CH_0, rank 1
6605 00:42:12.358068 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6606 00:42:12.358616 ==
6607 00:42:12.359061 RX Vref Scan: 0
6608 00:42:12.361311
6609 00:42:12.361745 RX Vref 0 -> 0, step: 1
6610 00:42:12.362175
6611 00:42:12.364531 RX Delay -327 -> 252, step: 8
6612 00:42:12.371981 iDelay=217, Bit 0, Center -20 (-247 ~ 208) 456
6613 00:42:12.375299 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6614 00:42:12.378982 iDelay=217, Bit 2, Center -24 (-247 ~ 200) 448
6615 00:42:12.382119 iDelay=217, Bit 3, Center -20 (-239 ~ 200) 440
6616 00:42:12.388718 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6617 00:42:12.392204 iDelay=217, Bit 5, Center -28 (-255 ~ 200) 456
6618 00:42:12.395671 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6619 00:42:12.398343 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6620 00:42:12.405223 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6621 00:42:12.408588 iDelay=217, Bit 9, Center -40 (-263 ~ 184) 448
6622 00:42:12.412532 iDelay=217, Bit 10, Center -28 (-255 ~ 200) 456
6623 00:42:12.415220 iDelay=217, Bit 11, Center -36 (-263 ~ 192) 456
6624 00:42:12.421940 iDelay=217, Bit 12, Center -24 (-247 ~ 200) 448
6625 00:42:12.424825 iDelay=217, Bit 13, Center -20 (-239 ~ 200) 440
6626 00:42:12.428600 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6627 00:42:12.435279 iDelay=217, Bit 15, Center -20 (-239 ~ 200) 440
6628 00:42:12.435865 ==
6629 00:42:12.438653 Dram Type= 6, Freq= 0, CH_0, rank 1
6630 00:42:12.441966 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6631 00:42:12.442541 ==
6632 00:42:12.442923 DQS Delay:
6633 00:42:12.445000 DQS0 = 28, DQS1 = 40
6634 00:42:12.445479 DQM Delay:
6635 00:42:12.448339 DQM0 = 10, DQM1 = 12
6636 00:42:12.448850 DQ Delay:
6637 00:42:12.451913 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =8
6638 00:42:12.454970 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6639 00:42:12.458325 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =4
6640 00:42:12.461919 DQ12 =16, DQ13 =20, DQ14 =24, DQ15 =20
6641 00:42:12.462496
6642 00:42:12.462868
6643 00:42:12.468458 [DQSOSCAuto] RK1, (LSB)MR18= 0xc87a, (MSB)MR19= 0xc0c, tDQSOscB0 = 394 ps tDQSOscB1 = 385 ps
6644 00:42:12.471966 CH0 RK1: MR19=C0C, MR18=C87A
6645 00:42:12.478170 CH0_RK1: MR19=0xC0C, MR18=0xC87A, DQSOSC=385, MR23=63, INC=398, DEC=265
6646 00:42:12.481630 [RxdqsGatingPostProcess] freq 400
6647 00:42:12.485135 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6648 00:42:12.488621 best DQS0 dly(2T, 0.5T) = (0, 10)
6649 00:42:12.491636 best DQS1 dly(2T, 0.5T) = (0, 10)
6650 00:42:12.495257 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6651 00:42:12.498301 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6652 00:42:12.501957 best DQS0 dly(2T, 0.5T) = (0, 10)
6653 00:42:12.504792 best DQS1 dly(2T, 0.5T) = (0, 10)
6654 00:42:12.508283 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6655 00:42:12.511919 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6656 00:42:12.515087 Pre-setting of DQS Precalculation
6657 00:42:12.518253 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6658 00:42:12.518726 ==
6659 00:42:12.521422 Dram Type= 6, Freq= 0, CH_1, rank 0
6660 00:42:12.528337 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6661 00:42:12.528841 ==
6662 00:42:12.532018 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6663 00:42:12.538198 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6664 00:42:12.541449 [CA 0] Center 36 (8~64) winsize 57
6665 00:42:12.544943 [CA 1] Center 36 (8~64) winsize 57
6666 00:42:12.548435 [CA 2] Center 36 (8~64) winsize 57
6667 00:42:12.552112 [CA 3] Center 36 (8~64) winsize 57
6668 00:42:12.555117 [CA 4] Center 36 (8~64) winsize 57
6669 00:42:12.558473 [CA 5] Center 36 (8~64) winsize 57
6670 00:42:12.559050
6671 00:42:12.561577 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6672 00:42:12.562048
6673 00:42:12.564636 [CATrainingPosCal] consider 1 rank data
6674 00:42:12.568085 u2DelayCellTimex100 = 270/100 ps
6675 00:42:12.571281 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6676 00:42:12.574834 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6677 00:42:12.578084 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6678 00:42:12.581731 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6679 00:42:12.585024 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6680 00:42:12.591425 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6681 00:42:12.591981
6682 00:42:12.594898 CA PerBit enable=1, Macro0, CA PI delay=36
6683 00:42:12.595491
6684 00:42:12.597924 [CBTSetCACLKResult] CA Dly = 36
6685 00:42:12.598396 CS Dly: 1 (0~32)
6686 00:42:12.598763 ==
6687 00:42:12.601346 Dram Type= 6, Freq= 0, CH_1, rank 1
6688 00:42:12.604933 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6689 00:42:12.608100 ==
6690 00:42:12.611406 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6691 00:42:12.618104 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6692 00:42:12.621282 [CA 0] Center 36 (8~64) winsize 57
6693 00:42:12.624795 [CA 1] Center 36 (8~64) winsize 57
6694 00:42:12.627658 [CA 2] Center 36 (8~64) winsize 57
6695 00:42:12.631310 [CA 3] Center 36 (8~64) winsize 57
6696 00:42:12.634404 [CA 4] Center 36 (8~64) winsize 57
6697 00:42:12.637984 [CA 5] Center 36 (8~64) winsize 57
6698 00:42:12.638558
6699 00:42:12.641365 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6700 00:42:12.641829
6701 00:42:12.644515 [CATrainingPosCal] consider 2 rank data
6702 00:42:12.647738 u2DelayCellTimex100 = 270/100 ps
6703 00:42:12.651045 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6704 00:42:12.654570 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6705 00:42:12.657787 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6706 00:42:12.661408 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6707 00:42:12.664783 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6708 00:42:12.668074 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6709 00:42:12.668707
6710 00:42:12.670953 CA PerBit enable=1, Macro0, CA PI delay=36
6711 00:42:12.671423
6712 00:42:12.674297 [CBTSetCACLKResult] CA Dly = 36
6713 00:42:12.677882 CS Dly: 1 (0~32)
6714 00:42:12.678350
6715 00:42:12.681328 ----->DramcWriteLeveling(PI) begin...
6716 00:42:12.681961 ==
6717 00:42:12.684598 Dram Type= 6, Freq= 0, CH_1, rank 0
6718 00:42:12.687896 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6719 00:42:12.688475 ==
6720 00:42:12.691484 Write leveling (Byte 0): 40 => 8
6721 00:42:12.694547 Write leveling (Byte 1): 32 => 0
6722 00:42:12.697697 DramcWriteLeveling(PI) end<-----
6723 00:42:12.698178
6724 00:42:12.698613 ==
6725 00:42:12.701007 Dram Type= 6, Freq= 0, CH_1, rank 0
6726 00:42:12.704312 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6727 00:42:12.704837 ==
6728 00:42:12.707731 [Gating] SW mode calibration
6729 00:42:12.714144 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6730 00:42:12.721009 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6731 00:42:12.724518 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6732 00:42:12.727708 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6733 00:42:12.734867 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6734 00:42:12.738154 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6735 00:42:12.740918 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6736 00:42:12.747961 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6737 00:42:12.751369 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6738 00:42:12.754795 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6739 00:42:12.761181 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6740 00:42:12.764733 Total UI for P1: 0, mck2ui 16
6741 00:42:12.768093 best dqsien dly found for B0: ( 0, 14, 24)
6742 00:42:12.768715 Total UI for P1: 0, mck2ui 16
6743 00:42:12.774434 best dqsien dly found for B1: ( 0, 14, 24)
6744 00:42:12.777479 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6745 00:42:12.781176 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6746 00:42:12.781786
6747 00:42:12.784708 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6748 00:42:12.787599 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6749 00:42:12.790820 [Gating] SW calibration Done
6750 00:42:12.791293 ==
6751 00:42:12.794443 Dram Type= 6, Freq= 0, CH_1, rank 0
6752 00:42:12.797988 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6753 00:42:12.798570 ==
6754 00:42:12.801171 RX Vref Scan: 0
6755 00:42:12.801750
6756 00:42:12.802125 RX Vref 0 -> 0, step: 1
6757 00:42:12.802510
6758 00:42:12.804393 RX Delay -410 -> 252, step: 16
6759 00:42:12.811187 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6760 00:42:12.814589 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6761 00:42:12.817959 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6762 00:42:12.821015 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6763 00:42:12.827426 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6764 00:42:12.830963 iDelay=230, Bit 5, Center -19 (-250 ~ 213) 464
6765 00:42:12.834576 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6766 00:42:12.837814 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6767 00:42:12.844705 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6768 00:42:12.847910 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6769 00:42:12.850589 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6770 00:42:12.854641 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6771 00:42:12.860997 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6772 00:42:12.864251 iDelay=230, Bit 13, Center -11 (-250 ~ 229) 480
6773 00:42:12.868006 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6774 00:42:12.870687 iDelay=230, Bit 15, Center -19 (-266 ~ 229) 496
6775 00:42:12.874263 ==
6776 00:42:12.874741 Dram Type= 6, Freq= 0, CH_1, rank 0
6777 00:42:12.881125 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6778 00:42:12.881764 ==
6779 00:42:12.882150 DQS Delay:
6780 00:42:12.884318 DQS0 = 27, DQS1 = 35
6781 00:42:12.884954 DQM Delay:
6782 00:42:12.887069 DQM0 = 8, DQM1 = 11
6783 00:42:12.887543 DQ Delay:
6784 00:42:12.891058 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6785 00:42:12.893889 DQ4 =8, DQ5 =8, DQ6 =16, DQ7 =8
6786 00:42:12.894500 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =8
6787 00:42:12.897445 DQ12 =24, DQ13 =24, DQ14 =8, DQ15 =16
6788 00:42:12.898070
6789 00:42:12.901076
6790 00:42:12.901676 ==
6791 00:42:12.903940 Dram Type= 6, Freq= 0, CH_1, rank 0
6792 00:42:12.907600 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6793 00:42:12.908199 ==
6794 00:42:12.908625
6795 00:42:12.908992
6796 00:42:12.910744 TX Vref Scan disable
6797 00:42:12.911225 == TX Byte 0 ==
6798 00:42:12.913814 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6799 00:42:12.920611 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6800 00:42:12.921109 == TX Byte 1 ==
6801 00:42:12.923938 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6802 00:42:12.930885 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6803 00:42:12.931406 ==
6804 00:42:12.934056 Dram Type= 6, Freq= 0, CH_1, rank 0
6805 00:42:12.937083 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6806 00:42:12.937560 ==
6807 00:42:12.937932
6808 00:42:12.938321
6809 00:42:12.940673 TX Vref Scan disable
6810 00:42:12.941145 == TX Byte 0 ==
6811 00:42:12.944312 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6812 00:42:12.950461 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6813 00:42:12.951008 == TX Byte 1 ==
6814 00:42:12.953970 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6815 00:42:12.960787 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6816 00:42:12.961360
6817 00:42:12.961934 [DATLAT]
6818 00:42:12.964222 Freq=400, CH1 RK0
6819 00:42:12.965008
6820 00:42:12.965623 DATLAT Default: 0xf
6821 00:42:12.967283 0, 0xFFFF, sum = 0
6822 00:42:12.967761 1, 0xFFFF, sum = 0
6823 00:42:12.970451 2, 0xFFFF, sum = 0
6824 00:42:12.970931 3, 0xFFFF, sum = 0
6825 00:42:12.973883 4, 0xFFFF, sum = 0
6826 00:42:12.974397 5, 0xFFFF, sum = 0
6827 00:42:12.976757 6, 0xFFFF, sum = 0
6828 00:42:12.977235 7, 0xFFFF, sum = 0
6829 00:42:12.980581 8, 0xFFFF, sum = 0
6830 00:42:12.981272 9, 0xFFFF, sum = 0
6831 00:42:12.983833 10, 0xFFFF, sum = 0
6832 00:42:12.984313 11, 0xFFFF, sum = 0
6833 00:42:12.987179 12, 0xFFFF, sum = 0
6834 00:42:12.987763 13, 0x0, sum = 1
6835 00:42:12.990412 14, 0x0, sum = 2
6836 00:42:12.990927 15, 0x0, sum = 3
6837 00:42:12.993778 16, 0x0, sum = 4
6838 00:42:12.994261 best_step = 14
6839 00:42:12.994710
6840 00:42:12.995150 ==
6841 00:42:12.997306 Dram Type= 6, Freq= 0, CH_1, rank 0
6842 00:42:13.003931 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6843 00:42:13.004407 ==
6844 00:42:13.005019 RX Vref Scan: 1
6845 00:42:13.005388
6846 00:42:13.007222 RX Vref 0 -> 0, step: 1
6847 00:42:13.007777
6848 00:42:13.010490 RX Delay -311 -> 252, step: 8
6849 00:42:13.010966
6850 00:42:13.013777 Set Vref, RX VrefLevel [Byte0]: 52
6851 00:42:13.017235 [Byte1]: 53
6852 00:42:13.017820
6853 00:42:13.020484 Final RX Vref Byte 0 = 52 to rank0
6854 00:42:13.023795 Final RX Vref Byte 1 = 53 to rank0
6855 00:42:13.026789 Final RX Vref Byte 0 = 52 to rank1
6856 00:42:13.030560 Final RX Vref Byte 1 = 53 to rank1==
6857 00:42:13.033689 Dram Type= 6, Freq= 0, CH_1, rank 0
6858 00:42:13.037028 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6859 00:42:13.040606 ==
6860 00:42:13.041165 DQS Delay:
6861 00:42:13.041653 DQS0 = 32, DQS1 = 40
6862 00:42:13.043760 DQM Delay:
6863 00:42:13.044195 DQM0 = 11, DQM1 = 14
6864 00:42:13.046796 DQ Delay:
6865 00:42:13.047230 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =8
6866 00:42:13.050348 DQ4 =8, DQ5 =20, DQ6 =24, DQ7 =8
6867 00:42:13.053957 DQ8 =4, DQ9 =0, DQ10 =20, DQ11 =8
6868 00:42:13.056639 DQ12 =24, DQ13 =20, DQ14 =16, DQ15 =20
6869 00:42:13.057074
6870 00:42:13.057416
6871 00:42:13.067352 [DQSOSCAuto] RK0, (LSB)MR18= 0x9ad4, (MSB)MR19= 0xc0c, tDQSOscB0 = 383 ps tDQSOscB1 = 390 ps
6872 00:42:13.070076 CH1 RK0: MR19=C0C, MR18=9AD4
6873 00:42:13.073922 CH1_RK0: MR19=0xC0C, MR18=0x9AD4, DQSOSC=383, MR23=63, INC=402, DEC=268
6874 00:42:13.076915 ==
6875 00:42:13.079913 Dram Type= 6, Freq= 0, CH_1, rank 1
6876 00:42:13.083597 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6877 00:42:13.084144 ==
6878 00:42:13.087058 [Gating] SW mode calibration
6879 00:42:13.093714 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6880 00:42:13.097061 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6881 00:42:13.103146 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6882 00:42:13.106718 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6883 00:42:13.109871 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6884 00:42:13.116529 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6885 00:42:13.120071 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6886 00:42:13.123015 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6887 00:42:13.129901 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6888 00:42:13.133407 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6889 00:42:13.136324 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6890 00:42:13.139831 Total UI for P1: 0, mck2ui 16
6891 00:42:13.143088 best dqsien dly found for B0: ( 0, 14, 24)
6892 00:42:13.146561 Total UI for P1: 0, mck2ui 16
6893 00:42:13.149822 best dqsien dly found for B1: ( 0, 14, 24)
6894 00:42:13.153221 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6895 00:42:13.156670 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6896 00:42:13.157172
6897 00:42:13.163048 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6898 00:42:13.166425 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6899 00:42:13.167113 [Gating] SW calibration Done
6900 00:42:13.169881 ==
6901 00:42:13.172817 Dram Type= 6, Freq= 0, CH_1, rank 1
6902 00:42:13.176141 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6903 00:42:13.176729 ==
6904 00:42:13.177079 RX Vref Scan: 0
6905 00:42:13.177396
6906 00:42:13.179438 RX Vref 0 -> 0, step: 1
6907 00:42:13.179869
6908 00:42:13.182836 RX Delay -410 -> 252, step: 16
6909 00:42:13.186329 iDelay=230, Bit 0, Center -11 (-234 ~ 213) 448
6910 00:42:13.189885 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6911 00:42:13.196438 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6912 00:42:13.199615 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6913 00:42:13.203187 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6914 00:42:13.206754 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6915 00:42:13.212689 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6916 00:42:13.216228 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6917 00:42:13.219655 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6918 00:42:13.222880 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6919 00:42:13.229823 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6920 00:42:13.232835 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6921 00:42:13.236256 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6922 00:42:13.239777 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6923 00:42:13.246143 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6924 00:42:13.249699 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6925 00:42:13.250178 ==
6926 00:42:13.253087 Dram Type= 6, Freq= 0, CH_1, rank 1
6927 00:42:13.256152 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6928 00:42:13.256943 ==
6929 00:42:13.259668 DQS Delay:
6930 00:42:13.260139 DQS0 = 35, DQS1 = 43
6931 00:42:13.263185 DQM Delay:
6932 00:42:13.263926 DQM0 = 18, DQM1 = 19
6933 00:42:13.264427 DQ Delay:
6934 00:42:13.266262 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6935 00:42:13.269716 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16
6936 00:42:13.272681 DQ8 =0, DQ9 =8, DQ10 =24, DQ11 =16
6937 00:42:13.276162 DQ12 =32, DQ13 =24, DQ14 =16, DQ15 =32
6938 00:42:13.276767
6939 00:42:13.277118
6940 00:42:13.277432 ==
6941 00:42:13.279578 Dram Type= 6, Freq= 0, CH_1, rank 1
6942 00:42:13.286043 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6943 00:42:13.286480 ==
6944 00:42:13.286817
6945 00:42:13.287127
6946 00:42:13.287424 TX Vref Scan disable
6947 00:42:13.289485 == TX Byte 0 ==
6948 00:42:13.292988 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6949 00:42:13.296391 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6950 00:42:13.299307 == TX Byte 1 ==
6951 00:42:13.302988 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6952 00:42:13.306097 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6953 00:42:13.306607 ==
6954 00:42:13.309349 Dram Type= 6, Freq= 0, CH_1, rank 1
6955 00:42:13.316129 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6956 00:42:13.316692 ==
6957 00:42:13.317040
6958 00:42:13.317355
6959 00:42:13.317654 TX Vref Scan disable
6960 00:42:13.319488 == TX Byte 0 ==
6961 00:42:13.322953 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6962 00:42:13.326244 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6963 00:42:13.329544 == TX Byte 1 ==
6964 00:42:13.332882 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6965 00:42:13.336223 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6966 00:42:13.336795
6967 00:42:13.339459 [DATLAT]
6968 00:42:13.339980 Freq=400, CH1 RK1
6969 00:42:13.340317
6970 00:42:13.342712 DATLAT Default: 0xe
6971 00:42:13.343135 0, 0xFFFF, sum = 0
6972 00:42:13.346377 1, 0xFFFF, sum = 0
6973 00:42:13.346808 2, 0xFFFF, sum = 0
6974 00:42:13.349572 3, 0xFFFF, sum = 0
6975 00:42:13.350003 4, 0xFFFF, sum = 0
6976 00:42:13.352575 5, 0xFFFF, sum = 0
6977 00:42:13.353013 6, 0xFFFF, sum = 0
6978 00:42:13.356212 7, 0xFFFF, sum = 0
6979 00:42:13.356784 8, 0xFFFF, sum = 0
6980 00:42:13.359519 9, 0xFFFF, sum = 0
6981 00:42:13.362923 10, 0xFFFF, sum = 0
6982 00:42:13.363439 11, 0xFFFF, sum = 0
6983 00:42:13.366479 12, 0xFFFF, sum = 0
6984 00:42:13.367072 13, 0x0, sum = 1
6985 00:42:13.369150 14, 0x0, sum = 2
6986 00:42:13.369623 15, 0x0, sum = 3
6987 00:42:13.369996 16, 0x0, sum = 4
6988 00:42:13.372675 best_step = 14
6989 00:42:13.373222
6990 00:42:13.373598 ==
6991 00:42:13.375999 Dram Type= 6, Freq= 0, CH_1, rank 1
6992 00:42:13.379528 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6993 00:42:13.380133 ==
6994 00:42:13.382977 RX Vref Scan: 0
6995 00:42:13.383442
6996 00:42:13.383805 RX Vref 0 -> 0, step: 1
6997 00:42:13.386235
6998 00:42:13.386701 RX Delay -327 -> 252, step: 8
6999 00:42:13.394539 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
7000 00:42:13.397860 iDelay=217, Bit 1, Center -24 (-247 ~ 200) 448
7001 00:42:13.400833 iDelay=217, Bit 2, Center -32 (-255 ~ 192) 448
7002 00:42:13.404764 iDelay=217, Bit 3, Center -20 (-247 ~ 208) 456
7003 00:42:13.411174 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
7004 00:42:13.414227 iDelay=217, Bit 5, Center -8 (-231 ~ 216) 448
7005 00:42:13.417762 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
7006 00:42:13.421223 iDelay=217, Bit 7, Center -20 (-239 ~ 200) 440
7007 00:42:13.427514 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
7008 00:42:13.431094 iDelay=217, Bit 9, Center -36 (-263 ~ 192) 456
7009 00:42:13.434258 iDelay=217, Bit 10, Center -24 (-247 ~ 200) 448
7010 00:42:13.437636 iDelay=217, Bit 11, Center -32 (-263 ~ 200) 464
7011 00:42:13.444231 iDelay=217, Bit 12, Center -20 (-247 ~ 208) 456
7012 00:42:13.447659 iDelay=217, Bit 13, Center -20 (-247 ~ 208) 456
7013 00:42:13.450810 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
7014 00:42:13.457711 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
7015 00:42:13.458189 ==
7016 00:42:13.461210 Dram Type= 6, Freq= 0, CH_1, rank 1
7017 00:42:13.464136 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7018 00:42:13.464721 ==
7019 00:42:13.465107 DQS Delay:
7020 00:42:13.467880 DQS0 = 32, DQS1 = 36
7021 00:42:13.468453 DQM Delay:
7022 00:42:13.470977 DQM0 = 14, DQM1 = 11
7023 00:42:13.471448 DQ Delay:
7024 00:42:13.474217 DQ0 =20, DQ1 =8, DQ2 =0, DQ3 =12
7025 00:42:13.478003 DQ4 =16, DQ5 =24, DQ6 =20, DQ7 =12
7026 00:42:13.480884 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
7027 00:42:13.484299 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =24
7028 00:42:13.484804
7029 00:42:13.485175
7030 00:42:13.491091 [DQSOSCAuto] RK1, (LSB)MR18= 0xb660, (MSB)MR19= 0xc0c, tDQSOscB0 = 397 ps tDQSOscB1 = 387 ps
7031 00:42:13.494207 CH1 RK1: MR19=C0C, MR18=B660
7032 00:42:13.500846 CH1_RK1: MR19=0xC0C, MR18=0xB660, DQSOSC=387, MR23=63, INC=394, DEC=262
7033 00:42:13.504295 [RxdqsGatingPostProcess] freq 400
7034 00:42:13.507602 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7035 00:42:13.510911 best DQS0 dly(2T, 0.5T) = (0, 10)
7036 00:42:13.514396 best DQS1 dly(2T, 0.5T) = (0, 10)
7037 00:42:13.517401 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7038 00:42:13.520829 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7039 00:42:13.524181 best DQS0 dly(2T, 0.5T) = (0, 10)
7040 00:42:13.527722 best DQS1 dly(2T, 0.5T) = (0, 10)
7041 00:42:13.530892 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7042 00:42:13.534293 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7043 00:42:13.537970 Pre-setting of DQS Precalculation
7044 00:42:13.540732 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7045 00:42:13.550582 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7046 00:42:13.557864 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7047 00:42:13.558430
7048 00:42:13.558825
7049 00:42:13.560584 [Calibration Summary] 800 Mbps
7050 00:42:13.561068 CH 0, Rank 0
7051 00:42:13.564493 SW Impedance : PASS
7052 00:42:13.565275 DUTY Scan : NO K
7053 00:42:13.567300 ZQ Calibration : PASS
7054 00:42:13.570841 Jitter Meter : NO K
7055 00:42:13.571313 CBT Training : PASS
7056 00:42:13.573791 Write leveling : PASS
7057 00:42:13.577200 RX DQS gating : PASS
7058 00:42:13.577672 RX DQ/DQS(RDDQC) : PASS
7059 00:42:13.580539 TX DQ/DQS : PASS
7060 00:42:13.584086 RX DATLAT : PASS
7061 00:42:13.584700 RX DQ/DQS(Engine): PASS
7062 00:42:13.587445 TX OE : NO K
7063 00:42:13.587919 All Pass.
7064 00:42:13.588292
7065 00:42:13.590798 CH 0, Rank 1
7066 00:42:13.591272 SW Impedance : PASS
7067 00:42:13.594247 DUTY Scan : NO K
7068 00:42:13.594718 ZQ Calibration : PASS
7069 00:42:13.597544 Jitter Meter : NO K
7070 00:42:13.600888 CBT Training : PASS
7071 00:42:13.601357 Write leveling : NO K
7072 00:42:13.603803 RX DQS gating : PASS
7073 00:42:13.607298 RX DQ/DQS(RDDQC) : PASS
7074 00:42:13.607770 TX DQ/DQS : PASS
7075 00:42:13.610589 RX DATLAT : PASS
7076 00:42:13.613957 RX DQ/DQS(Engine): PASS
7077 00:42:13.614443 TX OE : NO K
7078 00:42:13.617167 All Pass.
7079 00:42:13.617634
7080 00:42:13.618002 CH 1, Rank 0
7081 00:42:13.620522 SW Impedance : PASS
7082 00:42:13.621022 DUTY Scan : NO K
7083 00:42:13.623934 ZQ Calibration : PASS
7084 00:42:13.627423 Jitter Meter : NO K
7085 00:42:13.627889 CBT Training : PASS
7086 00:42:13.630848 Write leveling : PASS
7087 00:42:13.634291 RX DQS gating : PASS
7088 00:42:13.634714 RX DQ/DQS(RDDQC) : PASS
7089 00:42:13.637137 TX DQ/DQS : PASS
7090 00:42:13.640804 RX DATLAT : PASS
7091 00:42:13.641229 RX DQ/DQS(Engine): PASS
7092 00:42:13.643809 TX OE : NO K
7093 00:42:13.644234 All Pass.
7094 00:42:13.644592
7095 00:42:13.647312 CH 1, Rank 1
7096 00:42:13.647734 SW Impedance : PASS
7097 00:42:13.650828 DUTY Scan : NO K
7098 00:42:13.651361 ZQ Calibration : PASS
7099 00:42:13.653995 Jitter Meter : NO K
7100 00:42:13.657706 CBT Training : PASS
7101 00:42:13.658239 Write leveling : NO K
7102 00:42:13.660405 RX DQS gating : PASS
7103 00:42:13.663791 RX DQ/DQS(RDDQC) : PASS
7104 00:42:13.664212 TX DQ/DQS : PASS
7105 00:42:13.667609 RX DATLAT : PASS
7106 00:42:13.670458 RX DQ/DQS(Engine): PASS
7107 00:42:13.670945 TX OE : NO K
7108 00:42:13.674424 All Pass.
7109 00:42:13.674851
7110 00:42:13.675185 DramC Write-DBI off
7111 00:42:13.677159 PER_BANK_REFRESH: Hybrid Mode
7112 00:42:13.677591 TX_TRACKING: ON
7113 00:42:13.687324 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7114 00:42:13.690840 [FAST_K] Save calibration result to emmc
7115 00:42:13.694259 dramc_set_vcore_voltage set vcore to 725000
7116 00:42:13.696994 Read voltage for 1600, 0
7117 00:42:13.697418 Vio18 = 0
7118 00:42:13.700291 Vcore = 725000
7119 00:42:13.700731 Vdram = 0
7120 00:42:13.701064 Vddq = 0
7121 00:42:13.703937 Vmddr = 0
7122 00:42:13.707355 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7123 00:42:13.713901 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7124 00:42:13.714382 MEM_TYPE=3, freq_sel=13
7125 00:42:13.716979 sv_algorithm_assistance_LP4_3733
7126 00:42:13.720672 ============ PULL DRAM RESETB DOWN ============
7127 00:42:13.727292 ========== PULL DRAM RESETB DOWN end =========
7128 00:42:13.730516 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7129 00:42:13.733691 ===================================
7130 00:42:13.736876 LPDDR4 DRAM CONFIGURATION
7131 00:42:13.740283 ===================================
7132 00:42:13.740803 EX_ROW_EN[0] = 0x0
7133 00:42:13.743868 EX_ROW_EN[1] = 0x0
7134 00:42:13.747263 LP4Y_EN = 0x0
7135 00:42:13.747850 WORK_FSP = 0x1
7136 00:42:13.750254 WL = 0x5
7137 00:42:13.750720 RL = 0x5
7138 00:42:13.753609 BL = 0x2
7139 00:42:13.754077 RPST = 0x0
7140 00:42:13.757073 RD_PRE = 0x0
7141 00:42:13.757544 WR_PRE = 0x1
7142 00:42:13.760660 WR_PST = 0x1
7143 00:42:13.761245 DBI_WR = 0x0
7144 00:42:13.763749 DBI_RD = 0x0
7145 00:42:13.764217 OTF = 0x1
7146 00:42:13.767323 ===================================
7147 00:42:13.770679 ===================================
7148 00:42:13.773801 ANA top config
7149 00:42:13.776667 ===================================
7150 00:42:13.777162 DLL_ASYNC_EN = 0
7151 00:42:13.780466 ALL_SLAVE_EN = 0
7152 00:42:13.783571 NEW_RANK_MODE = 1
7153 00:42:13.786905 DLL_IDLE_MODE = 1
7154 00:42:13.787373 LP45_APHY_COMB_EN = 1
7155 00:42:13.790365 TX_ODT_DIS = 0
7156 00:42:13.793432 NEW_8X_MODE = 1
7157 00:42:13.797052 ===================================
7158 00:42:13.800387 ===================================
7159 00:42:13.803850 data_rate = 3200
7160 00:42:13.807093 CKR = 1
7161 00:42:13.810462 DQ_P2S_RATIO = 8
7162 00:42:13.811148 ===================================
7163 00:42:13.813788 CA_P2S_RATIO = 8
7164 00:42:13.817055 DQ_CA_OPEN = 0
7165 00:42:13.819976 DQ_SEMI_OPEN = 0
7166 00:42:13.823470 CA_SEMI_OPEN = 0
7167 00:42:13.826989 CA_FULL_RATE = 0
7168 00:42:13.827470 DQ_CKDIV4_EN = 0
7169 00:42:13.830345 CA_CKDIV4_EN = 0
7170 00:42:13.833831 CA_PREDIV_EN = 0
7171 00:42:13.837346 PH8_DLY = 12
7172 00:42:13.840267 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7173 00:42:13.843646 DQ_AAMCK_DIV = 4
7174 00:42:13.844121 CA_AAMCK_DIV = 4
7175 00:42:13.847199 CA_ADMCK_DIV = 4
7176 00:42:13.849885 DQ_TRACK_CA_EN = 0
7177 00:42:13.853536 CA_PICK = 1600
7178 00:42:13.856535 CA_MCKIO = 1600
7179 00:42:13.860259 MCKIO_SEMI = 0
7180 00:42:13.863539 PLL_FREQ = 3068
7181 00:42:13.867232 DQ_UI_PI_RATIO = 32
7182 00:42:13.867828 CA_UI_PI_RATIO = 0
7183 00:42:13.870234 ===================================
7184 00:42:13.873208 ===================================
7185 00:42:13.876827 memory_type:LPDDR4
7186 00:42:13.880035 GP_NUM : 10
7187 00:42:13.880523 SRAM_EN : 1
7188 00:42:13.883472 MD32_EN : 0
7189 00:42:13.886861 ===================================
7190 00:42:13.890158 [ANA_INIT] >>>>>>>>>>>>>>
7191 00:42:13.893397 <<<<<< [CONFIGURE PHASE]: ANA_TX
7192 00:42:13.896838 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7193 00:42:13.899835 ===================================
7194 00:42:13.900331 data_rate = 3200,PCW = 0X7600
7195 00:42:13.903595 ===================================
7196 00:42:13.906636 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7197 00:42:13.913353 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7198 00:42:13.919686 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7199 00:42:13.923168 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7200 00:42:13.926534 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7201 00:42:13.929821 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7202 00:42:13.933115 [ANA_INIT] flow start
7203 00:42:13.933605 [ANA_INIT] PLL >>>>>>>>
7204 00:42:13.936616 [ANA_INIT] PLL <<<<<<<<
7205 00:42:13.939996 [ANA_INIT] MIDPI >>>>>>>>
7206 00:42:13.943392 [ANA_INIT] MIDPI <<<<<<<<
7207 00:42:13.943868 [ANA_INIT] DLL >>>>>>>>
7208 00:42:13.946256 [ANA_INIT] DLL <<<<<<<<
7209 00:42:13.949924 [ANA_INIT] flow end
7210 00:42:13.952945 ============ LP4 DIFF to SE enter ============
7211 00:42:13.956483 ============ LP4 DIFF to SE exit ============
7212 00:42:13.959647 [ANA_INIT] <<<<<<<<<<<<<
7213 00:42:13.962945 [Flow] Enable top DCM control >>>>>
7214 00:42:13.966425 [Flow] Enable top DCM control <<<<<
7215 00:42:13.969700 Enable DLL master slave shuffle
7216 00:42:13.973008 ==============================================================
7217 00:42:13.976440 Gating Mode config
7218 00:42:13.979767 ==============================================================
7219 00:42:13.983075 Config description:
7220 00:42:13.992822 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7221 00:42:13.999693 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7222 00:42:14.002918 SELPH_MODE 0: By rank 1: By Phase
7223 00:42:14.009745 ==============================================================
7224 00:42:14.012752 GAT_TRACK_EN = 1
7225 00:42:14.016341 RX_GATING_MODE = 2
7226 00:42:14.019853 RX_GATING_TRACK_MODE = 2
7227 00:42:14.022773 SELPH_MODE = 1
7228 00:42:14.023269 PICG_EARLY_EN = 1
7229 00:42:14.026367 VALID_LAT_VALUE = 1
7230 00:42:14.033144 ==============================================================
7231 00:42:14.036398 Enter into Gating configuration >>>>
7232 00:42:14.039710 Exit from Gating configuration <<<<
7233 00:42:14.043066 Enter into DVFS_PRE_config >>>>>
7234 00:42:14.053045 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7235 00:42:14.056413 Exit from DVFS_PRE_config <<<<<
7236 00:42:14.059858 Enter into PICG configuration >>>>
7237 00:42:14.063178 Exit from PICG configuration <<<<
7238 00:42:14.066159 [RX_INPUT] configuration >>>>>
7239 00:42:14.069611 [RX_INPUT] configuration <<<<<
7240 00:42:14.073304 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7241 00:42:14.080068 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7242 00:42:14.086357 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7243 00:42:14.093188 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7244 00:42:14.099642 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7245 00:42:14.102991 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7246 00:42:14.109452 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7247 00:42:14.112905 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7248 00:42:14.116132 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7249 00:42:14.119711 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7250 00:42:14.122741 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7251 00:42:14.129693 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7252 00:42:14.133092 ===================================
7253 00:42:14.136200 LPDDR4 DRAM CONFIGURATION
7254 00:42:14.139482 ===================================
7255 00:42:14.139954 EX_ROW_EN[0] = 0x0
7256 00:42:14.142647 EX_ROW_EN[1] = 0x0
7257 00:42:14.143113 LP4Y_EN = 0x0
7258 00:42:14.146471 WORK_FSP = 0x1
7259 00:42:14.147045 WL = 0x5
7260 00:42:14.149570 RL = 0x5
7261 00:42:14.150040 BL = 0x2
7262 00:42:14.153037 RPST = 0x0
7263 00:42:14.153503 RD_PRE = 0x0
7264 00:42:14.156574 WR_PRE = 0x1
7265 00:42:14.157204 WR_PST = 0x1
7266 00:42:14.159833 DBI_WR = 0x0
7267 00:42:14.160301 DBI_RD = 0x0
7268 00:42:14.162762 OTF = 0x1
7269 00:42:14.166364 ===================================
7270 00:42:14.169340 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7271 00:42:14.173102 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7272 00:42:14.179423 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7273 00:42:14.183153 ===================================
7274 00:42:14.183745 LPDDR4 DRAM CONFIGURATION
7275 00:42:14.186312 ===================================
7276 00:42:14.189871 EX_ROW_EN[0] = 0x10
7277 00:42:14.192996 EX_ROW_EN[1] = 0x0
7278 00:42:14.193470 LP4Y_EN = 0x0
7279 00:42:14.196263 WORK_FSP = 0x1
7280 00:42:14.196870 WL = 0x5
7281 00:42:14.199234 RL = 0x5
7282 00:42:14.199703 BL = 0x2
7283 00:42:14.203015 RPST = 0x0
7284 00:42:14.203639 RD_PRE = 0x0
7285 00:42:14.206180 WR_PRE = 0x1
7286 00:42:14.206650 WR_PST = 0x1
7287 00:42:14.209339 DBI_WR = 0x0
7288 00:42:14.209991 DBI_RD = 0x0
7289 00:42:14.212969 OTF = 0x1
7290 00:42:14.216333 ===================================
7291 00:42:14.222819 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7292 00:42:14.223345 ==
7293 00:42:14.226264 Dram Type= 6, Freq= 0, CH_0, rank 0
7294 00:42:14.229404 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7295 00:42:14.229880 ==
7296 00:42:14.232735 [Duty_Offset_Calibration]
7297 00:42:14.233204 B0:2 B1:0 CA:1
7298 00:42:14.233571
7299 00:42:14.235984 [DutyScan_Calibration_Flow] k_type=0
7300 00:42:14.246850
7301 00:42:14.247410 ==CLK 0==
7302 00:42:14.250326 Final CLK duty delay cell = 0
7303 00:42:14.253042 [0] MAX Duty = 5187%(X100), DQS PI = 20
7304 00:42:14.256601 [0] MIN Duty = 5031%(X100), DQS PI = 0
7305 00:42:14.257076 [0] AVG Duty = 5109%(X100)
7306 00:42:14.260200
7307 00:42:14.263536 CH0 CLK Duty spec in!! Max-Min= 156%
7308 00:42:14.266705 [DutyScan_Calibration_Flow] ====Done====
7309 00:42:14.267175
7310 00:42:14.269492 [DutyScan_Calibration_Flow] k_type=1
7311 00:42:14.285822
7312 00:42:14.286354 ==DQS 0 ==
7313 00:42:14.289047 Final DQS duty delay cell = 0
7314 00:42:14.292405 [0] MAX Duty = 5249%(X100), DQS PI = 32
7315 00:42:14.295293 [0] MIN Duty = 4938%(X100), DQS PI = 0
7316 00:42:14.298934 [0] AVG Duty = 5093%(X100)
7317 00:42:14.299591
7318 00:42:14.300161 ==DQS 1 ==
7319 00:42:14.302163 Final DQS duty delay cell = -4
7320 00:42:14.305190 [-4] MAX Duty = 5094%(X100), DQS PI = 28
7321 00:42:14.308672 [-4] MIN Duty = 4844%(X100), DQS PI = 4
7322 00:42:14.312176 [-4] AVG Duty = 4969%(X100)
7323 00:42:14.312739
7324 00:42:14.315609 CH0 DQS 0 Duty spec in!! Max-Min= 311%
7325 00:42:14.316033
7326 00:42:14.318855 CH0 DQS 1 Duty spec in!! Max-Min= 250%
7327 00:42:14.322188 [DutyScan_Calibration_Flow] ====Done====
7328 00:42:14.322613
7329 00:42:14.325575 [DutyScan_Calibration_Flow] k_type=3
7330 00:42:14.343384
7331 00:42:14.343953 ==DQM 0 ==
7332 00:42:14.346297 Final DQM duty delay cell = 0
7333 00:42:14.349763 [0] MAX Duty = 5062%(X100), DQS PI = 26
7334 00:42:14.353017 [0] MIN Duty = 4813%(X100), DQS PI = 2
7335 00:42:14.356468 [0] AVG Duty = 4937%(X100)
7336 00:42:14.357100
7337 00:42:14.357444 ==DQM 1 ==
7338 00:42:14.359794 Final DQM duty delay cell = 0
7339 00:42:14.362992 [0] MAX Duty = 5249%(X100), DQS PI = 44
7340 00:42:14.366596 [0] MIN Duty = 5000%(X100), DQS PI = 18
7341 00:42:14.370037 [0] AVG Duty = 5124%(X100)
7342 00:42:14.370580
7343 00:42:14.373130 CH0 DQM 0 Duty spec in!! Max-Min= 249%
7344 00:42:14.373592
7345 00:42:14.376090 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7346 00:42:14.379535 [DutyScan_Calibration_Flow] ====Done====
7347 00:42:14.379976
7348 00:42:14.382849 [DutyScan_Calibration_Flow] k_type=2
7349 00:42:14.400686
7350 00:42:14.401271 ==DQ 0 ==
7351 00:42:14.404163 Final DQ duty delay cell = 0
7352 00:42:14.407384 [0] MAX Duty = 5124%(X100), DQS PI = 34
7353 00:42:14.410536 [0] MIN Duty = 5000%(X100), DQS PI = 0
7354 00:42:14.411015 [0] AVG Duty = 5062%(X100)
7355 00:42:14.411392
7356 00:42:14.413762 ==DQ 1 ==
7357 00:42:14.417180 Final DQ duty delay cell = 0
7358 00:42:14.420316 [0] MAX Duty = 4969%(X100), DQS PI = 44
7359 00:42:14.423467 [0] MIN Duty = 4875%(X100), DQS PI = 10
7360 00:42:14.423943 [0] AVG Duty = 4922%(X100)
7361 00:42:14.424331
7362 00:42:14.427009 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7363 00:42:14.429924
7364 00:42:14.430387 CH0 DQ 1 Duty spec in!! Max-Min= 94%
7365 00:42:14.436521 [DutyScan_Calibration_Flow] ====Done====
7366 00:42:14.437050 ==
7367 00:42:14.440192 Dram Type= 6, Freq= 0, CH_1, rank 0
7368 00:42:14.443761 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7369 00:42:14.444231 ==
7370 00:42:14.446719 [Duty_Offset_Calibration]
7371 00:42:14.447184 B0:0 B1:-1 CA:2
7372 00:42:14.447549
7373 00:42:14.450350 [DutyScan_Calibration_Flow] k_type=0
7374 00:42:14.460498
7375 00:42:14.461082 ==CLK 0==
7376 00:42:14.463709 Final CLK duty delay cell = 0
7377 00:42:14.466890 [0] MAX Duty = 5156%(X100), DQS PI = 10
7378 00:42:14.470078 [0] MIN Duty = 4906%(X100), DQS PI = 46
7379 00:42:14.473559 [0] AVG Duty = 5031%(X100)
7380 00:42:14.474096
7381 00:42:14.476913 CH1 CLK Duty spec in!! Max-Min= 250%
7382 00:42:14.480373 [DutyScan_Calibration_Flow] ====Done====
7383 00:42:14.480832
7384 00:42:14.483468 [DutyScan_Calibration_Flow] k_type=1
7385 00:42:14.500085
7386 00:42:14.500650 ==DQS 0 ==
7387 00:42:14.503479 Final DQS duty delay cell = 0
7388 00:42:14.507355 [0] MAX Duty = 5093%(X100), DQS PI = 24
7389 00:42:14.510469 [0] MIN Duty = 5000%(X100), DQS PI = 0
7390 00:42:14.510955 [0] AVG Duty = 5046%(X100)
7391 00:42:14.513455
7392 00:42:14.513919 ==DQS 1 ==
7393 00:42:14.516914 Final DQS duty delay cell = 0
7394 00:42:14.520334 [0] MAX Duty = 5187%(X100), DQS PI = 0
7395 00:42:14.523372 [0] MIN Duty = 4844%(X100), DQS PI = 32
7396 00:42:14.523837 [0] AVG Duty = 5015%(X100)
7397 00:42:14.527018
7398 00:42:14.529966 CH1 DQS 0 Duty spec in!! Max-Min= 93%
7399 00:42:14.530460
7400 00:42:14.533328 CH1 DQS 1 Duty spec in!! Max-Min= 343%
7401 00:42:14.536791 [DutyScan_Calibration_Flow] ====Done====
7402 00:42:14.537256
7403 00:42:14.539985 [DutyScan_Calibration_Flow] k_type=3
7404 00:42:14.557566
7405 00:42:14.558217 ==DQM 0 ==
7406 00:42:14.561170 Final DQM duty delay cell = 4
7407 00:42:14.564488 [4] MAX Duty = 5125%(X100), DQS PI = 22
7408 00:42:14.567489 [4] MIN Duty = 4969%(X100), DQS PI = 32
7409 00:42:14.568071 [4] AVG Duty = 5047%(X100)
7410 00:42:14.570862
7411 00:42:14.571561 ==DQM 1 ==
7412 00:42:14.574226 Final DQM duty delay cell = 0
7413 00:42:14.577649 [0] MAX Duty = 5281%(X100), DQS PI = 58
7414 00:42:14.580987 [0] MIN Duty = 4876%(X100), DQS PI = 34
7415 00:42:14.584347 [0] AVG Duty = 5078%(X100)
7416 00:42:14.584840
7417 00:42:14.587645 CH1 DQM 0 Duty spec in!! Max-Min= 156%
7418 00:42:14.588131
7419 00:42:14.591385 CH1 DQM 1 Duty spec in!! Max-Min= 405%
7420 00:42:14.594328 [DutyScan_Calibration_Flow] ====Done====
7421 00:42:14.594791
7422 00:42:14.597592 [DutyScan_Calibration_Flow] k_type=2
7423 00:42:14.614991
7424 00:42:14.615561 ==DQ 0 ==
7425 00:42:14.618206 Final DQ duty delay cell = 0
7426 00:42:14.621513 [0] MAX Duty = 5062%(X100), DQS PI = 18
7427 00:42:14.624453 [0] MIN Duty = 4969%(X100), DQS PI = 2
7428 00:42:14.624989 [0] AVG Duty = 5015%(X100)
7429 00:42:14.625389
7430 00:42:14.627805 ==DQ 1 ==
7431 00:42:14.631224 Final DQ duty delay cell = 0
7432 00:42:14.634822 [0] MAX Duty = 5062%(X100), DQS PI = 2
7433 00:42:14.638028 [0] MIN Duty = 4813%(X100), DQS PI = 34
7434 00:42:14.638523 [0] AVG Duty = 4937%(X100)
7435 00:42:14.638890
7436 00:42:14.641357 CH1 DQ 0 Duty spec in!! Max-Min= 93%
7437 00:42:14.641825
7438 00:42:14.644836 CH1 DQ 1 Duty spec in!! Max-Min= 249%
7439 00:42:14.651241 [DutyScan_Calibration_Flow] ====Done====
7440 00:42:14.654870 nWR fixed to 30
7441 00:42:14.655341 [ModeRegInit_LP4] CH0 RK0
7442 00:42:14.657889 [ModeRegInit_LP4] CH0 RK1
7443 00:42:14.661113 [ModeRegInit_LP4] CH1 RK0
7444 00:42:14.661688 [ModeRegInit_LP4] CH1 RK1
7445 00:42:14.664288 match AC timing 5
7446 00:42:14.667571 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7447 00:42:14.671131 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7448 00:42:14.677983 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7449 00:42:14.681145 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7450 00:42:14.687669 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7451 00:42:14.688234 [MiockJmeterHQA]
7452 00:42:14.688646
7453 00:42:14.690854 [DramcMiockJmeter] u1RxGatingPI = 0
7454 00:42:14.694140 0 : 4253, 4027
7455 00:42:14.694727 4 : 4371, 4142
7456 00:42:14.695116 8 : 4252, 4027
7457 00:42:14.698019 12 : 4253, 4026
7458 00:42:14.698688 16 : 4252, 4027
7459 00:42:14.700756 20 : 4253, 4026
7460 00:42:14.701344 24 : 4255, 4030
7461 00:42:14.704454 28 : 4252, 4027
7462 00:42:14.705104 32 : 4252, 4027
7463 00:42:14.705484 36 : 4366, 4140
7464 00:42:14.707796 40 : 4253, 4026
7465 00:42:14.708475 44 : 4255, 4029
7466 00:42:14.711296 48 : 4255, 4030
7467 00:42:14.711867 52 : 4363, 4138
7468 00:42:14.714021 56 : 4252, 4027
7469 00:42:14.714629 60 : 4363, 4139
7470 00:42:14.717388 64 : 4253, 4029
7471 00:42:14.717973 68 : 4250, 4026
7472 00:42:14.718365 72 : 4252, 4029
7473 00:42:14.720925 76 : 4252, 4030
7474 00:42:14.721501 80 : 4361, 4137
7475 00:42:14.724191 84 : 4250, 4027
7476 00:42:14.724864 88 : 4360, 3386
7477 00:42:14.727570 92 : 4250, 0
7478 00:42:14.728069 96 : 4250, 0
7479 00:42:14.728443 100 : 4249, 0
7480 00:42:14.731233 104 : 4250, 0
7481 00:42:14.731705 108 : 4253, 0
7482 00:42:14.734274 112 : 4250, 0
7483 00:42:14.734744 116 : 4252, 0
7484 00:42:14.735117 120 : 4361, 0
7485 00:42:14.737672 124 : 4250, 0
7486 00:42:14.738189 128 : 4250, 0
7487 00:42:14.738565 132 : 4250, 0
7488 00:42:14.740881 136 : 4361, 0
7489 00:42:14.741464 140 : 4250, 0
7490 00:42:14.744428 144 : 4250, 0
7491 00:42:14.745040 148 : 4250, 0
7492 00:42:14.745446 152 : 4364, 0
7493 00:42:14.747752 156 : 4249, 0
7494 00:42:14.748316 160 : 4250, 0
7495 00:42:14.751224 164 : 4250, 0
7496 00:42:14.751819 168 : 4252, 0
7497 00:42:14.752205 172 : 4250, 0
7498 00:42:14.754466 176 : 4250, 0
7499 00:42:14.755030 180 : 4252, 0
7500 00:42:14.755417 184 : 4250, 0
7501 00:42:14.757919 188 : 4361, 0
7502 00:42:14.758482 192 : 4250, 0
7503 00:42:14.761055 196 : 4250, 0
7504 00:42:14.761636 200 : 4253, 338
7505 00:42:14.764393 204 : 4252, 3710
7506 00:42:14.765024 208 : 4361, 4138
7507 00:42:14.765417 212 : 4250, 4027
7508 00:42:14.767719 216 : 4250, 4026
7509 00:42:14.768296 220 : 4250, 4027
7510 00:42:14.771166 224 : 4252, 4030
7511 00:42:14.771721 228 : 4250, 4027
7512 00:42:14.774146 232 : 4250, 4026
7513 00:42:14.774621 236 : 4250, 4027
7514 00:42:14.777637 240 : 4252, 4030
7515 00:42:14.778148 244 : 4250, 4027
7516 00:42:14.780871 248 : 4360, 4137
7517 00:42:14.781387 252 : 4361, 4137
7518 00:42:14.784284 256 : 4250, 4027
7519 00:42:14.784798 260 : 4363, 4140
7520 00:42:14.787611 264 : 4249, 4027
7521 00:42:14.788088 268 : 4250, 4026
7522 00:42:14.788462 272 : 4250, 4027
7523 00:42:14.791090 276 : 4252, 4030
7524 00:42:14.791669 280 : 4250, 4027
7525 00:42:14.794002 284 : 4250, 4026
7526 00:42:14.794501 288 : 4252, 4027
7527 00:42:14.797522 292 : 4252, 4030
7528 00:42:14.798106 296 : 4250, 4027
7529 00:42:14.800953 300 : 4360, 4138
7530 00:42:14.801579 304 : 4361, 4137
7531 00:42:14.804678 308 : 4250, 4027
7532 00:42:14.805257 312 : 4363, 3433
7533 00:42:14.807744 316 : 4250, 1037
7534 00:42:14.808218
7535 00:42:14.808617 MIOCK jitter meter ch=0
7536 00:42:14.808968
7537 00:42:14.811052 1T = (316-92) = 224 dly cells
7538 00:42:14.817889 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7539 00:42:14.818463 ==
7540 00:42:14.820658 Dram Type= 6, Freq= 0, CH_0, rank 0
7541 00:42:14.824106 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7542 00:42:14.824632 ==
7543 00:42:14.831047 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7544 00:42:14.834321 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7545 00:42:14.837445 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7546 00:42:14.844218 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7547 00:42:14.853621 [CA 0] Center 42 (12~73) winsize 62
7548 00:42:14.857475 [CA 1] Center 43 (13~73) winsize 61
7549 00:42:14.860501 [CA 2] Center 37 (7~67) winsize 61
7550 00:42:14.863807 [CA 3] Center 37 (7~67) winsize 61
7551 00:42:14.866862 [CA 4] Center 36 (6~66) winsize 61
7552 00:42:14.870268 [CA 5] Center 35 (5~65) winsize 61
7553 00:42:14.870841
7554 00:42:14.873940 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7555 00:42:14.874520
7556 00:42:14.876724 [CATrainingPosCal] consider 1 rank data
7557 00:42:14.879996 u2DelayCellTimex100 = 290/100 ps
7558 00:42:14.883600 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7559 00:42:14.889949 CA1 delay=43 (13~73),Diff = 8 PI (26 cell)
7560 00:42:14.893625 CA2 delay=37 (7~67),Diff = 2 PI (6 cell)
7561 00:42:14.896627 CA3 delay=37 (7~67),Diff = 2 PI (6 cell)
7562 00:42:14.900097 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7563 00:42:14.903422 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7564 00:42:14.903893
7565 00:42:14.906827 CA PerBit enable=1, Macro0, CA PI delay=35
7566 00:42:14.907297
7567 00:42:14.909739 [CBTSetCACLKResult] CA Dly = 35
7568 00:42:14.913232 CS Dly: 10 (0~41)
7569 00:42:14.916739 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7570 00:42:14.920025 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7571 00:42:14.920707 ==
7572 00:42:14.923397 Dram Type= 6, Freq= 0, CH_0, rank 1
7573 00:42:14.926603 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7574 00:42:14.929680 ==
7575 00:42:14.933088 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7576 00:42:14.936441 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7577 00:42:14.942760 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7578 00:42:14.946465 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7579 00:42:14.957156 [CA 0] Center 43 (13~73) winsize 61
7580 00:42:14.959891 [CA 1] Center 43 (13~73) winsize 61
7581 00:42:14.963485 [CA 2] Center 37 (8~67) winsize 60
7582 00:42:14.966902 [CA 3] Center 38 (9~68) winsize 60
7583 00:42:14.970235 [CA 4] Center 37 (7~67) winsize 61
7584 00:42:14.973338 [CA 5] Center 36 (7~66) winsize 60
7585 00:42:14.973881
7586 00:42:14.976864 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7587 00:42:14.977334
7588 00:42:14.980084 [CATrainingPosCal] consider 2 rank data
7589 00:42:14.983613 u2DelayCellTimex100 = 290/100 ps
7590 00:42:14.986799 CA0 delay=43 (13~73),Diff = 7 PI (23 cell)
7591 00:42:14.993760 CA1 delay=43 (13~73),Diff = 7 PI (23 cell)
7592 00:42:14.996852 CA2 delay=37 (8~67),Diff = 1 PI (3 cell)
7593 00:42:14.999968 CA3 delay=38 (9~67),Diff = 2 PI (6 cell)
7594 00:42:15.003330 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7595 00:42:15.006832 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
7596 00:42:15.007359
7597 00:42:15.010057 CA PerBit enable=1, Macro0, CA PI delay=36
7598 00:42:15.010581
7599 00:42:15.013237 [CBTSetCACLKResult] CA Dly = 36
7600 00:42:15.016834 CS Dly: 11 (0~43)
7601 00:42:15.019721 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7602 00:42:15.023126 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7603 00:42:15.023720
7604 00:42:15.026614 ----->DramcWriteLeveling(PI) begin...
7605 00:42:15.027092 ==
7606 00:42:15.030004 Dram Type= 6, Freq= 0, CH_0, rank 0
7607 00:42:15.033114 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7608 00:42:15.036596 ==
7609 00:42:15.037082 Write leveling (Byte 0): 35 => 35
7610 00:42:15.039968 Write leveling (Byte 1): 29 => 29
7611 00:42:15.043767 DramcWriteLeveling(PI) end<-----
7612 00:42:15.044325
7613 00:42:15.044758 ==
7614 00:42:15.047195 Dram Type= 6, Freq= 0, CH_0, rank 0
7615 00:42:15.053629 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7616 00:42:15.054169 ==
7617 00:42:15.054539 [Gating] SW mode calibration
7618 00:42:15.063513 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7619 00:42:15.067075 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7620 00:42:15.070178 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7621 00:42:15.076656 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7622 00:42:15.079968 1 4 8 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (1 1)
7623 00:42:15.083562 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7624 00:42:15.089922 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7625 00:42:15.093329 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7626 00:42:15.096932 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7627 00:42:15.103367 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7628 00:42:15.106815 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7629 00:42:15.110200 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7630 00:42:15.116854 1 5 8 | B1->B0 | 3434 2e2e | 1 1 | (1 1) (1 0)
7631 00:42:15.120084 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7632 00:42:15.123450 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7633 00:42:15.130050 1 5 20 | B1->B0 | 2e2e 2323 | 0 0 | (1 0) (0 0)
7634 00:42:15.133472 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
7635 00:42:15.136979 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7636 00:42:15.143452 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7637 00:42:15.146755 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7638 00:42:15.150270 1 6 8 | B1->B0 | 2323 3b3b | 0 0 | (0 0) (0 0)
7639 00:42:15.156715 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7640 00:42:15.160311 1 6 16 | B1->B0 | 2828 4646 | 0 0 | (0 0) (0 0)
7641 00:42:15.163474 1 6 20 | B1->B0 | 3e3e 4646 | 1 0 | (1 1) (0 0)
7642 00:42:15.170301 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7643 00:42:15.173429 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7644 00:42:15.176624 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7645 00:42:15.179705 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7646 00:42:15.186743 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7647 00:42:15.189856 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7648 00:42:15.193468 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7649 00:42:15.200179 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7650 00:42:15.203364 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7651 00:42:15.206803 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7652 00:42:15.213361 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7653 00:42:15.216686 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7654 00:42:15.219699 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7655 00:42:15.226641 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7656 00:42:15.230076 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7657 00:42:15.233083 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7658 00:42:15.239830 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7659 00:42:15.242850 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7660 00:42:15.246509 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7661 00:42:15.253321 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7662 00:42:15.256298 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7663 00:42:15.259564 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7664 00:42:15.266749 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7665 00:42:15.267319 Total UI for P1: 0, mck2ui 16
7666 00:42:15.273046 best dqsien dly found for B0: ( 1, 9, 10)
7667 00:42:15.276699 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7668 00:42:15.279340 Total UI for P1: 0, mck2ui 16
7669 00:42:15.283062 best dqsien dly found for B1: ( 1, 9, 18)
7670 00:42:15.286073 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7671 00:42:15.289646 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7672 00:42:15.290115
7673 00:42:15.293061 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7674 00:42:15.296045 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7675 00:42:15.299611 [Gating] SW calibration Done
7676 00:42:15.300193 ==
7677 00:42:15.302836 Dram Type= 6, Freq= 0, CH_0, rank 0
7678 00:42:15.306195 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7679 00:42:15.306690 ==
7680 00:42:15.310127 RX Vref Scan: 0
7681 00:42:15.310691
7682 00:42:15.313296 RX Vref 0 -> 0, step: 1
7683 00:42:15.313863
7684 00:42:15.314237 RX Delay 0 -> 252, step: 8
7685 00:42:15.319511 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
7686 00:42:15.323173 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7687 00:42:15.326246 iDelay=200, Bit 2, Center 135 (88 ~ 183) 96
7688 00:42:15.329473 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7689 00:42:15.333135 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7690 00:42:15.339496 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7691 00:42:15.342788 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7692 00:42:15.346133 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7693 00:42:15.349260 iDelay=200, Bit 8, Center 123 (72 ~ 175) 104
7694 00:42:15.352749 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7695 00:42:15.356132 iDelay=200, Bit 10, Center 127 (80 ~ 175) 96
7696 00:42:15.362979 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
7697 00:42:15.366203 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7698 00:42:15.369876 iDelay=200, Bit 13, Center 131 (88 ~ 175) 88
7699 00:42:15.372837 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7700 00:42:15.379333 iDelay=200, Bit 15, Center 135 (88 ~ 183) 96
7701 00:42:15.379909 ==
7702 00:42:15.382770 Dram Type= 6, Freq= 0, CH_0, rank 0
7703 00:42:15.385697 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7704 00:42:15.386129 ==
7705 00:42:15.386497 DQS Delay:
7706 00:42:15.389030 DQS0 = 0, DQS1 = 0
7707 00:42:15.389458 DQM Delay:
7708 00:42:15.392455 DQM0 = 137, DQM1 = 128
7709 00:42:15.393009 DQ Delay:
7710 00:42:15.395916 DQ0 =139, DQ1 =139, DQ2 =135, DQ3 =131
7711 00:42:15.399076 DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =147
7712 00:42:15.402545 DQ8 =123, DQ9 =115, DQ10 =127, DQ11 =127
7713 00:42:15.406070 DQ12 =131, DQ13 =131, DQ14 =139, DQ15 =135
7714 00:42:15.406611
7715 00:42:15.406951
7716 00:42:15.409476 ==
7717 00:42:15.410011 Dram Type= 6, Freq= 0, CH_0, rank 0
7718 00:42:15.416309 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7719 00:42:15.416949 ==
7720 00:42:15.417299
7721 00:42:15.417615
7722 00:42:15.419291 TX Vref Scan disable
7723 00:42:15.419773 == TX Byte 0 ==
7724 00:42:15.422354 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7725 00:42:15.429276 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7726 00:42:15.429704 == TX Byte 1 ==
7727 00:42:15.432364 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7728 00:42:15.439099 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7729 00:42:15.439833 ==
7730 00:42:15.442222 Dram Type= 6, Freq= 0, CH_0, rank 0
7731 00:42:15.445538 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7732 00:42:15.446137 ==
7733 00:42:15.459723
7734 00:42:15.462905 TX Vref early break, caculate TX vref
7735 00:42:15.466019 TX Vref=16, minBit 12, minWin=22, winSum=377
7736 00:42:15.469692 TX Vref=18, minBit 12, minWin=22, winSum=386
7737 00:42:15.472615 TX Vref=20, minBit 2, minWin=24, winSum=398
7738 00:42:15.475889 TX Vref=22, minBit 7, minWin=24, winSum=405
7739 00:42:15.479258 TX Vref=24, minBit 1, minWin=25, winSum=418
7740 00:42:15.486198 TX Vref=26, minBit 12, minWin=25, winSum=426
7741 00:42:15.488877 TX Vref=28, minBit 0, minWin=26, winSum=432
7742 00:42:15.492695 TX Vref=30, minBit 7, minWin=25, winSum=426
7743 00:42:15.495757 TX Vref=32, minBit 2, minWin=25, winSum=416
7744 00:42:15.499532 TX Vref=34, minBit 7, minWin=24, winSum=404
7745 00:42:15.505885 [TxChooseVref] Worse bit 0, Min win 26, Win sum 432, Final Vref 28
7746 00:42:15.506369
7747 00:42:15.509190 Final TX Range 0 Vref 28
7748 00:42:15.509768
7749 00:42:15.510145 ==
7750 00:42:15.512717 Dram Type= 6, Freq= 0, CH_0, rank 0
7751 00:42:15.516083 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7752 00:42:15.516689 ==
7753 00:42:15.517173
7754 00:42:15.517705
7755 00:42:15.519314 TX Vref Scan disable
7756 00:42:15.525848 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7757 00:42:15.526382 == TX Byte 0 ==
7758 00:42:15.529309 u2DelayCellOfst[0]=13 cells (4 PI)
7759 00:42:15.532611 u2DelayCellOfst[1]=16 cells (5 PI)
7760 00:42:15.535791 u2DelayCellOfst[2]=10 cells (3 PI)
7761 00:42:15.539268 u2DelayCellOfst[3]=10 cells (3 PI)
7762 00:42:15.542112 u2DelayCellOfst[4]=6 cells (2 PI)
7763 00:42:15.546015 u2DelayCellOfst[5]=0 cells (0 PI)
7764 00:42:15.548781 u2DelayCellOfst[6]=16 cells (5 PI)
7765 00:42:15.552265 u2DelayCellOfst[7]=13 cells (4 PI)
7766 00:42:15.555816 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7767 00:42:15.559352 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7768 00:42:15.562253 == TX Byte 1 ==
7769 00:42:15.562821 u2DelayCellOfst[8]=0 cells (0 PI)
7770 00:42:15.565388 u2DelayCellOfst[9]=0 cells (0 PI)
7771 00:42:15.568993 u2DelayCellOfst[10]=6 cells (2 PI)
7772 00:42:15.572282 u2DelayCellOfst[11]=3 cells (1 PI)
7773 00:42:15.575522 u2DelayCellOfst[12]=13 cells (4 PI)
7774 00:42:15.578881 u2DelayCellOfst[13]=10 cells (3 PI)
7775 00:42:15.582286 u2DelayCellOfst[14]=13 cells (4 PI)
7776 00:42:15.585205 u2DelayCellOfst[15]=10 cells (3 PI)
7777 00:42:15.588802 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7778 00:42:15.595321 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7779 00:42:15.595887 DramC Write-DBI on
7780 00:42:15.596256 ==
7781 00:42:15.598520 Dram Type= 6, Freq= 0, CH_0, rank 0
7782 00:42:15.602101 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7783 00:42:15.604995 ==
7784 00:42:15.605736
7785 00:42:15.606212
7786 00:42:15.606568 TX Vref Scan disable
7787 00:42:15.609035 == TX Byte 0 ==
7788 00:42:15.612335 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
7789 00:42:15.615316 == TX Byte 1 ==
7790 00:42:15.618769 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
7791 00:42:15.622324 DramC Write-DBI off
7792 00:42:15.622791
7793 00:42:15.623157 [DATLAT]
7794 00:42:15.623495 Freq=1600, CH0 RK0
7795 00:42:15.623934
7796 00:42:15.625623 DATLAT Default: 0xf
7797 00:42:15.626097 0, 0xFFFF, sum = 0
7798 00:42:15.629022 1, 0xFFFF, sum = 0
7799 00:42:15.629498 2, 0xFFFF, sum = 0
7800 00:42:15.632183 3, 0xFFFF, sum = 0
7801 00:42:15.635520 4, 0xFFFF, sum = 0
7802 00:42:15.635994 5, 0xFFFF, sum = 0
7803 00:42:15.639120 6, 0xFFFF, sum = 0
7804 00:42:15.639794 7, 0xFFFF, sum = 0
7805 00:42:15.642324 8, 0xFFFF, sum = 0
7806 00:42:15.642798 9, 0xFFFF, sum = 0
7807 00:42:15.645796 10, 0xFFFF, sum = 0
7808 00:42:15.646270 11, 0xFFFF, sum = 0
7809 00:42:15.648711 12, 0xFFFF, sum = 0
7810 00:42:15.649188 13, 0xFFFF, sum = 0
7811 00:42:15.652000 14, 0x0, sum = 1
7812 00:42:15.652475 15, 0x0, sum = 2
7813 00:42:15.655346 16, 0x0, sum = 3
7814 00:42:15.655822 17, 0x0, sum = 4
7815 00:42:15.658673 best_step = 15
7816 00:42:15.659140
7817 00:42:15.659507 ==
7818 00:42:15.662089 Dram Type= 6, Freq= 0, CH_0, rank 0
7819 00:42:15.665476 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7820 00:42:15.665903 ==
7821 00:42:15.666235 RX Vref Scan: 1
7822 00:42:15.666545
7823 00:42:15.668863 Set Vref Range= 24 -> 127
7824 00:42:15.669285
7825 00:42:15.672323 RX Vref 24 -> 127, step: 1
7826 00:42:15.672899
7827 00:42:15.675663 RX Delay 19 -> 252, step: 4
7828 00:42:15.676213
7829 00:42:15.678671 Set Vref, RX VrefLevel [Byte0]: 24
7830 00:42:15.682170 [Byte1]: 24
7831 00:42:15.682709
7832 00:42:15.685235 Set Vref, RX VrefLevel [Byte0]: 25
7833 00:42:15.688698 [Byte1]: 25
7834 00:42:15.689146
7835 00:42:15.692046 Set Vref, RX VrefLevel [Byte0]: 26
7836 00:42:15.695476 [Byte1]: 26
7837 00:42:15.699428
7838 00:42:15.699945 Set Vref, RX VrefLevel [Byte0]: 27
7839 00:42:15.702380 [Byte1]: 27
7840 00:42:15.707044
7841 00:42:15.707607 Set Vref, RX VrefLevel [Byte0]: 28
7842 00:42:15.710050 [Byte1]: 28
7843 00:42:15.714251
7844 00:42:15.714694 Set Vref, RX VrefLevel [Byte0]: 29
7845 00:42:15.717883 [Byte1]: 29
7846 00:42:15.721889
7847 00:42:15.722410 Set Vref, RX VrefLevel [Byte0]: 30
7848 00:42:15.725221 [Byte1]: 30
7849 00:42:15.729194
7850 00:42:15.729639 Set Vref, RX VrefLevel [Byte0]: 31
7851 00:42:15.732490 [Byte1]: 31
7852 00:42:15.736998
7853 00:42:15.737443 Set Vref, RX VrefLevel [Byte0]: 32
7854 00:42:15.740024 [Byte1]: 32
7855 00:42:15.744679
7856 00:42:15.745168 Set Vref, RX VrefLevel [Byte0]: 33
7857 00:42:15.747925 [Byte1]: 33
7858 00:42:15.752069
7859 00:42:15.752494 Set Vref, RX VrefLevel [Byte0]: 34
7860 00:42:15.755169 [Byte1]: 34
7861 00:42:15.759299
7862 00:42:15.759885 Set Vref, RX VrefLevel [Byte0]: 35
7863 00:42:15.762844 [Byte1]: 35
7864 00:42:15.767140
7865 00:42:15.767565 Set Vref, RX VrefLevel [Byte0]: 36
7866 00:42:15.770474 [Byte1]: 36
7867 00:42:15.775217
7868 00:42:15.775741 Set Vref, RX VrefLevel [Byte0]: 37
7869 00:42:15.778236 [Byte1]: 37
7870 00:42:15.782498
7871 00:42:15.782921 Set Vref, RX VrefLevel [Byte0]: 38
7872 00:42:15.785471 [Byte1]: 38
7873 00:42:15.789791
7874 00:42:15.790222 Set Vref, RX VrefLevel [Byte0]: 39
7875 00:42:15.793242 [Byte1]: 39
7876 00:42:15.797570
7877 00:42:15.798042 Set Vref, RX VrefLevel [Byte0]: 40
7878 00:42:15.800968 [Byte1]: 40
7879 00:42:15.805038
7880 00:42:15.805464 Set Vref, RX VrefLevel [Byte0]: 41
7881 00:42:15.808497 [Byte1]: 41
7882 00:42:15.812810
7883 00:42:15.813239 Set Vref, RX VrefLevel [Byte0]: 42
7884 00:42:15.815760 [Byte1]: 42
7885 00:42:15.820335
7886 00:42:15.820821 Set Vref, RX VrefLevel [Byte0]: 43
7887 00:42:15.823454 [Byte1]: 43
7888 00:42:15.827737
7889 00:42:15.828251 Set Vref, RX VrefLevel [Byte0]: 44
7890 00:42:15.831253 [Byte1]: 44
7891 00:42:15.835268
7892 00:42:15.835696 Set Vref, RX VrefLevel [Byte0]: 45
7893 00:42:15.838621 [Byte1]: 45
7894 00:42:15.842620
7895 00:42:15.843074 Set Vref, RX VrefLevel [Byte0]: 46
7896 00:42:15.846326 [Byte1]: 46
7897 00:42:15.850469
7898 00:42:15.850912 Set Vref, RX VrefLevel [Byte0]: 47
7899 00:42:15.853988 [Byte1]: 47
7900 00:42:15.858250
7901 00:42:15.858686 Set Vref, RX VrefLevel [Byte0]: 48
7902 00:42:15.861431 [Byte1]: 48
7903 00:42:15.865626
7904 00:42:15.866058 Set Vref, RX VrefLevel [Byte0]: 49
7905 00:42:15.869038 [Byte1]: 49
7906 00:42:15.873147
7907 00:42:15.873571 Set Vref, RX VrefLevel [Byte0]: 50
7908 00:42:15.876763 [Byte1]: 50
7909 00:42:15.880752
7910 00:42:15.881368 Set Vref, RX VrefLevel [Byte0]: 51
7911 00:42:15.883983 [Byte1]: 51
7912 00:42:15.888162
7913 00:42:15.888756 Set Vref, RX VrefLevel [Byte0]: 52
7914 00:42:15.891412 [Byte1]: 52
7915 00:42:15.895948
7916 00:42:15.899248 Set Vref, RX VrefLevel [Byte0]: 53
7917 00:42:15.899799 [Byte1]: 53
7918 00:42:15.903670
7919 00:42:15.904136 Set Vref, RX VrefLevel [Byte0]: 54
7920 00:42:15.906654 [Byte1]: 54
7921 00:42:15.910983
7922 00:42:15.911406 Set Vref, RX VrefLevel [Byte0]: 55
7923 00:42:15.914378 [Byte1]: 55
7924 00:42:15.918845
7925 00:42:15.919283 Set Vref, RX VrefLevel [Byte0]: 56
7926 00:42:15.922178 [Byte1]: 56
7927 00:42:15.926444
7928 00:42:15.926870 Set Vref, RX VrefLevel [Byte0]: 57
7929 00:42:15.929274 [Byte1]: 57
7930 00:42:15.933609
7931 00:42:15.934037 Set Vref, RX VrefLevel [Byte0]: 58
7932 00:42:15.936981 [Byte1]: 58
7933 00:42:15.941407
7934 00:42:15.941900 Set Vref, RX VrefLevel [Byte0]: 59
7935 00:42:15.944972 [Byte1]: 59
7936 00:42:15.949131
7937 00:42:15.949557 Set Vref, RX VrefLevel [Byte0]: 60
7938 00:42:15.952513 [Byte1]: 60
7939 00:42:15.956480
7940 00:42:15.957020 Set Vref, RX VrefLevel [Byte0]: 61
7941 00:42:15.960008 [Byte1]: 61
7942 00:42:15.964234
7943 00:42:15.964837 Set Vref, RX VrefLevel [Byte0]: 62
7944 00:42:15.967296 [Byte1]: 62
7945 00:42:15.971605
7946 00:42:15.972213 Set Vref, RX VrefLevel [Byte0]: 63
7947 00:42:15.975195 [Byte1]: 63
7948 00:42:15.979115
7949 00:42:15.979538 Set Vref, RX VrefLevel [Byte0]: 64
7950 00:42:15.982517 [Byte1]: 64
7951 00:42:15.986868
7952 00:42:15.987335 Set Vref, RX VrefLevel [Byte0]: 65
7953 00:42:15.990306 [Byte1]: 65
7954 00:42:15.994595
7955 00:42:15.995087 Set Vref, RX VrefLevel [Byte0]: 66
7956 00:42:15.997782 [Byte1]: 66
7957 00:42:16.001919
7958 00:42:16.002414 Set Vref, RX VrefLevel [Byte0]: 67
7959 00:42:16.005319 [Byte1]: 67
7960 00:42:16.009519
7961 00:42:16.010088 Set Vref, RX VrefLevel [Byte0]: 68
7962 00:42:16.013002 [Byte1]: 68
7963 00:42:16.017204
7964 00:42:16.017796 Set Vref, RX VrefLevel [Byte0]: 69
7965 00:42:16.020129 [Byte1]: 69
7966 00:42:16.024614
7967 00:42:16.025042 Set Vref, RX VrefLevel [Byte0]: 70
7968 00:42:16.027678 [Byte1]: 70
7969 00:42:16.032119
7970 00:42:16.032565 Set Vref, RX VrefLevel [Byte0]: 71
7971 00:42:16.035526 [Byte1]: 71
7972 00:42:16.039884
7973 00:42:16.040312 Set Vref, RX VrefLevel [Byte0]: 72
7974 00:42:16.043053 [Byte1]: 72
7975 00:42:16.047612
7976 00:42:16.048121 Set Vref, RX VrefLevel [Byte0]: 73
7977 00:42:16.051068 [Byte1]: 73
7978 00:42:16.055149
7979 00:42:16.055689 Set Vref, RX VrefLevel [Byte0]: 74
7980 00:42:16.058679 [Byte1]: 74
7981 00:42:16.062882
7982 00:42:16.063316 Set Vref, RX VrefLevel [Byte0]: 75
7983 00:42:16.066103 [Byte1]: 75
7984 00:42:16.070100
7985 00:42:16.070529 Set Vref, RX VrefLevel [Byte0]: 76
7986 00:42:16.073488 [Byte1]: 76
7987 00:42:16.077930
7988 00:42:16.078419 Set Vref, RX VrefLevel [Byte0]: 77
7989 00:42:16.081168 [Byte1]: 77
7990 00:42:16.085178
7991 00:42:16.085604 Set Vref, RX VrefLevel [Byte0]: 78
7992 00:42:16.088650 [Byte1]: 78
7993 00:42:16.092752
7994 00:42:16.093178 Set Vref, RX VrefLevel [Byte0]: 79
7995 00:42:16.096341 [Byte1]: 79
7996 00:42:16.100654
7997 00:42:16.101080 Final RX Vref Byte 0 = 65 to rank0
7998 00:42:16.103893 Final RX Vref Byte 1 = 62 to rank0
7999 00:42:16.107339 Final RX Vref Byte 0 = 65 to rank1
8000 00:42:16.110532 Final RX Vref Byte 1 = 62 to rank1==
8001 00:42:16.113796 Dram Type= 6, Freq= 0, CH_0, rank 0
8002 00:42:16.120632 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8003 00:42:16.121158 ==
8004 00:42:16.121503 DQS Delay:
8005 00:42:16.121816 DQS0 = 0, DQS1 = 0
8006 00:42:16.123827 DQM Delay:
8007 00:42:16.124248 DQM0 = 135, DQM1 = 126
8008 00:42:16.127132 DQ Delay:
8009 00:42:16.130476 DQ0 =134, DQ1 =134, DQ2 =132, DQ3 =132
8010 00:42:16.133904 DQ4 =138, DQ5 =124, DQ6 =144, DQ7 =142
8011 00:42:16.137097 DQ8 =116, DQ9 =114, DQ10 =128, DQ11 =122
8012 00:42:16.140737 DQ12 =130, DQ13 =130, DQ14 =138, DQ15 =132
8013 00:42:16.141324
8014 00:42:16.141698
8015 00:42:16.142041
8016 00:42:16.144106 [DramC_TX_OE_Calibration] TA2
8017 00:42:16.147278 Original DQ_B0 (3 6) =30, OEN = 27
8018 00:42:16.150497 Original DQ_B1 (3 6) =30, OEN = 27
8019 00:42:16.154242 24, 0x0, End_B0=24 End_B1=24
8020 00:42:16.154822 25, 0x0, End_B0=25 End_B1=25
8021 00:42:16.157258 26, 0x0, End_B0=26 End_B1=26
8022 00:42:16.160451 27, 0x0, End_B0=27 End_B1=27
8023 00:42:16.164007 28, 0x0, End_B0=28 End_B1=28
8024 00:42:16.164665 29, 0x0, End_B0=29 End_B1=29
8025 00:42:16.167342 30, 0x0, End_B0=30 End_B1=30
8026 00:42:16.170668 31, 0x4141, End_B0=30 End_B1=30
8027 00:42:16.173709 Byte0 end_step=30 best_step=27
8028 00:42:16.176956 Byte1 end_step=30 best_step=27
8029 00:42:16.180646 Byte0 TX OE(2T, 0.5T) = (3, 3)
8030 00:42:16.181248 Byte1 TX OE(2T, 0.5T) = (3, 3)
8031 00:42:16.181653
8032 00:42:16.183970
8033 00:42:16.190859 [DQSOSCAuto] RK0, (LSB)MR18= 0x2220, (MSB)MR19= 0x303, tDQSOscB0 = 393 ps tDQSOscB1 = 392 ps
8034 00:42:16.193554 CH0 RK0: MR19=303, MR18=2220
8035 00:42:16.200575 CH0_RK0: MR19=0x303, MR18=0x2220, DQSOSC=392, MR23=63, INC=24, DEC=16
8036 00:42:16.201158
8037 00:42:16.203792 ----->DramcWriteLeveling(PI) begin...
8038 00:42:16.204375 ==
8039 00:42:16.207007 Dram Type= 6, Freq= 0, CH_0, rank 1
8040 00:42:16.210518 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8041 00:42:16.211102 ==
8042 00:42:16.214112 Write leveling (Byte 0): 36 => 36
8043 00:42:16.217174 Write leveling (Byte 1): 28 => 28
8044 00:42:16.220634 DramcWriteLeveling(PI) end<-----
8045 00:42:16.221140
8046 00:42:16.221635 ==
8047 00:42:16.223474 Dram Type= 6, Freq= 0, CH_0, rank 1
8048 00:42:16.226898 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8049 00:42:16.227375 ==
8050 00:42:16.230405 [Gating] SW mode calibration
8051 00:42:16.237024 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8052 00:42:16.243794 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8053 00:42:16.247237 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8054 00:42:16.250497 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8055 00:42:16.257242 1 4 8 | B1->B0 | 2323 2424 | 0 1 | (0 0) (0 0)
8056 00:42:16.260426 1 4 12 | B1->B0 | 2424 2e2e | 0 0 | (0 0) (0 0)
8057 00:42:16.264227 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8058 00:42:16.270480 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8059 00:42:16.273970 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8060 00:42:16.277033 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8061 00:42:16.283969 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8062 00:42:16.287195 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8063 00:42:16.290151 1 5 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
8064 00:42:16.293841 1 5 12 | B1->B0 | 3434 2727 | 1 0 | (1 0) (1 0)
8065 00:42:16.300692 1 5 16 | B1->B0 | 2525 2323 | 1 0 | (1 0) (1 0)
8066 00:42:16.303566 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8067 00:42:16.307125 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8068 00:42:16.313650 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8069 00:42:16.317158 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8070 00:42:16.320473 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8071 00:42:16.327200 1 6 8 | B1->B0 | 2323 3030 | 0 1 | (0 0) (0 0)
8072 00:42:16.330463 1 6 12 | B1->B0 | 3131 4646 | 1 0 | (0 0) (0 0)
8073 00:42:16.333937 1 6 16 | B1->B0 | 4343 4646 | 1 0 | (0 0) (0 0)
8074 00:42:16.340717 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8075 00:42:16.343719 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8076 00:42:16.347541 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8077 00:42:16.353894 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8078 00:42:16.357343 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8079 00:42:16.360278 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8080 00:42:16.367134 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8081 00:42:16.370184 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8082 00:42:16.373588 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8083 00:42:16.380276 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8084 00:42:16.383722 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8085 00:42:16.387071 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8086 00:42:16.393356 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8087 00:42:16.397003 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8088 00:42:16.400348 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8089 00:42:16.403345 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8090 00:42:16.410092 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8091 00:42:16.413541 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8092 00:42:16.416871 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8093 00:42:16.423148 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8094 00:42:16.426288 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8095 00:42:16.429671 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8096 00:42:16.436424 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8097 00:42:16.439864 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8098 00:42:16.443509 Total UI for P1: 0, mck2ui 16
8099 00:42:16.446580 best dqsien dly found for B0: ( 1, 9, 12)
8100 00:42:16.450085 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8101 00:42:16.453126 Total UI for P1: 0, mck2ui 16
8102 00:42:16.457115 best dqsien dly found for B1: ( 1, 9, 14)
8103 00:42:16.460060 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8104 00:42:16.463516 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8105 00:42:16.464088
8106 00:42:16.470225 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8107 00:42:16.473407 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8108 00:42:16.476727 [Gating] SW calibration Done
8109 00:42:16.477294 ==
8110 00:42:16.480082 Dram Type= 6, Freq= 0, CH_0, rank 1
8111 00:42:16.483220 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8112 00:42:16.483694 ==
8113 00:42:16.484063 RX Vref Scan: 0
8114 00:42:16.484409
8115 00:42:16.486733 RX Vref 0 -> 0, step: 1
8116 00:42:16.487199
8117 00:42:16.489917 RX Delay 0 -> 252, step: 8
8118 00:42:16.493403 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8119 00:42:16.496929 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8120 00:42:16.503384 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8121 00:42:16.506511 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
8122 00:42:16.510110 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8123 00:42:16.513371 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8124 00:42:16.517051 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8125 00:42:16.519843 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8126 00:42:16.526470 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8127 00:42:16.529704 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
8128 00:42:16.533090 iDelay=200, Bit 10, Center 127 (80 ~ 175) 96
8129 00:42:16.536581 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8130 00:42:16.540147 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
8131 00:42:16.546540 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
8132 00:42:16.549909 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8133 00:42:16.553225 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8134 00:42:16.553795 ==
8135 00:42:16.556771 Dram Type= 6, Freq= 0, CH_0, rank 1
8136 00:42:16.559564 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8137 00:42:16.563077 ==
8138 00:42:16.563650 DQS Delay:
8139 00:42:16.564024 DQS0 = 0, DQS1 = 0
8140 00:42:16.566501 DQM Delay:
8141 00:42:16.567076 DQM0 = 135, DQM1 = 126
8142 00:42:16.570023 DQ Delay:
8143 00:42:16.573439 DQ0 =135, DQ1 =135, DQ2 =135, DQ3 =131
8144 00:42:16.576431 DQ4 =135, DQ5 =127, DQ6 =143, DQ7 =143
8145 00:42:16.580093 DQ8 =115, DQ9 =115, DQ10 =127, DQ11 =123
8146 00:42:16.583331 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
8147 00:42:16.583797
8148 00:42:16.584159
8149 00:42:16.584497 ==
8150 00:42:16.586518 Dram Type= 6, Freq= 0, CH_0, rank 1
8151 00:42:16.589777 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8152 00:42:16.590372 ==
8153 00:42:16.590747
8154 00:42:16.591179
8155 00:42:16.593082 TX Vref Scan disable
8156 00:42:16.596368 == TX Byte 0 ==
8157 00:42:16.599926 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8158 00:42:16.603178 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8159 00:42:16.606288 == TX Byte 1 ==
8160 00:42:16.609529 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8161 00:42:16.613103 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8162 00:42:16.613588 ==
8163 00:42:16.616145 Dram Type= 6, Freq= 0, CH_0, rank 1
8164 00:42:16.623199 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8165 00:42:16.623855 ==
8166 00:42:16.636504
8167 00:42:16.639894 TX Vref early break, caculate TX vref
8168 00:42:16.643108 TX Vref=16, minBit 0, minWin=23, winSum=385
8169 00:42:16.646756 TX Vref=18, minBit 0, minWin=24, winSum=396
8170 00:42:16.649634 TX Vref=20, minBit 3, minWin=24, winSum=406
8171 00:42:16.652904 TX Vref=22, minBit 8, minWin=24, winSum=413
8172 00:42:16.656422 TX Vref=24, minBit 2, minWin=25, winSum=420
8173 00:42:16.663170 TX Vref=26, minBit 0, minWin=26, winSum=427
8174 00:42:16.666437 TX Vref=28, minBit 0, minWin=25, winSum=427
8175 00:42:16.669797 TX Vref=30, minBit 0, minWin=25, winSum=422
8176 00:42:16.673185 TX Vref=32, minBit 1, minWin=25, winSum=419
8177 00:42:16.676510 TX Vref=34, minBit 0, minWin=25, winSum=409
8178 00:42:16.679891 TX Vref=36, minBit 2, minWin=24, winSum=401
8179 00:42:16.686913 [TxChooseVref] Worse bit 0, Min win 26, Win sum 427, Final Vref 26
8180 00:42:16.687499
8181 00:42:16.690229 Final TX Range 0 Vref 26
8182 00:42:16.690816
8183 00:42:16.691196 ==
8184 00:42:16.693474 Dram Type= 6, Freq= 0, CH_0, rank 1
8185 00:42:16.696442 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8186 00:42:16.697077 ==
8187 00:42:16.697487
8188 00:42:16.697841
8189 00:42:16.699709 TX Vref Scan disable
8190 00:42:16.706248 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8191 00:42:16.706787 == TX Byte 0 ==
8192 00:42:16.709859 u2DelayCellOfst[0]=13 cells (4 PI)
8193 00:42:16.712916 u2DelayCellOfst[1]=16 cells (5 PI)
8194 00:42:16.716290 u2DelayCellOfst[2]=10 cells (3 PI)
8195 00:42:16.719862 u2DelayCellOfst[3]=10 cells (3 PI)
8196 00:42:16.723124 u2DelayCellOfst[4]=6 cells (2 PI)
8197 00:42:16.726350 u2DelayCellOfst[5]=0 cells (0 PI)
8198 00:42:16.729743 u2DelayCellOfst[6]=16 cells (5 PI)
8199 00:42:16.732982 u2DelayCellOfst[7]=16 cells (5 PI)
8200 00:42:16.736172 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8201 00:42:16.739839 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8202 00:42:16.743321 == TX Byte 1 ==
8203 00:42:16.746680 u2DelayCellOfst[8]=0 cells (0 PI)
8204 00:42:16.747248 u2DelayCellOfst[9]=3 cells (1 PI)
8205 00:42:16.749331 u2DelayCellOfst[10]=6 cells (2 PI)
8206 00:42:16.753443 u2DelayCellOfst[11]=3 cells (1 PI)
8207 00:42:16.755931 u2DelayCellOfst[12]=10 cells (3 PI)
8208 00:42:16.759680 u2DelayCellOfst[13]=10 cells (3 PI)
8209 00:42:16.762945 u2DelayCellOfst[14]=13 cells (4 PI)
8210 00:42:16.766040 u2DelayCellOfst[15]=10 cells (3 PI)
8211 00:42:16.769880 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8212 00:42:16.776270 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8213 00:42:16.776878 DramC Write-DBI on
8214 00:42:16.777257 ==
8215 00:42:16.779410 Dram Type= 6, Freq= 0, CH_0, rank 1
8216 00:42:16.786407 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8217 00:42:16.786985 ==
8218 00:42:16.787361
8219 00:42:16.787707
8220 00:42:16.788038 TX Vref Scan disable
8221 00:42:16.789999 == TX Byte 0 ==
8222 00:42:16.793561 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
8223 00:42:16.796266 == TX Byte 1 ==
8224 00:42:16.799816 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8225 00:42:16.803382 DramC Write-DBI off
8226 00:42:16.803953
8227 00:42:16.804331 [DATLAT]
8228 00:42:16.804758 Freq=1600, CH0 RK1
8229 00:42:16.805114
8230 00:42:16.806851 DATLAT Default: 0xf
8231 00:42:16.807325 0, 0xFFFF, sum = 0
8232 00:42:16.809684 1, 0xFFFF, sum = 0
8233 00:42:16.813114 2, 0xFFFF, sum = 0
8234 00:42:16.813598 3, 0xFFFF, sum = 0
8235 00:42:16.816580 4, 0xFFFF, sum = 0
8236 00:42:16.817279 5, 0xFFFF, sum = 0
8237 00:42:16.820216 6, 0xFFFF, sum = 0
8238 00:42:16.820831 7, 0xFFFF, sum = 0
8239 00:42:16.823580 8, 0xFFFF, sum = 0
8240 00:42:16.824157 9, 0xFFFF, sum = 0
8241 00:42:16.826304 10, 0xFFFF, sum = 0
8242 00:42:16.826786 11, 0xFFFF, sum = 0
8243 00:42:16.829768 12, 0xFFFF, sum = 0
8244 00:42:16.830276 13, 0xFFFF, sum = 0
8245 00:42:16.833177 14, 0x0, sum = 1
8246 00:42:16.833660 15, 0x0, sum = 2
8247 00:42:16.836346 16, 0x0, sum = 3
8248 00:42:16.836869 17, 0x0, sum = 4
8249 00:42:16.839893 best_step = 15
8250 00:42:16.840369
8251 00:42:16.840799 ==
8252 00:42:16.843115 Dram Type= 6, Freq= 0, CH_0, rank 1
8253 00:42:16.846389 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8254 00:42:16.846872 ==
8255 00:42:16.849773 RX Vref Scan: 0
8256 00:42:16.850247
8257 00:42:16.850622 RX Vref 0 -> 0, step: 1
8258 00:42:16.850970
8259 00:42:16.853171 RX Delay 19 -> 252, step: 4
8260 00:42:16.856373 iDelay=191, Bit 0, Center 130 (79 ~ 182) 104
8261 00:42:16.862834 iDelay=191, Bit 1, Center 134 (83 ~ 186) 104
8262 00:42:16.866235 iDelay=191, Bit 2, Center 130 (79 ~ 182) 104
8263 00:42:16.869484 iDelay=191, Bit 3, Center 130 (83 ~ 178) 96
8264 00:42:16.873061 iDelay=191, Bit 4, Center 134 (83 ~ 186) 104
8265 00:42:16.876214 iDelay=191, Bit 5, Center 124 (75 ~ 174) 100
8266 00:42:16.882486 iDelay=191, Bit 6, Center 138 (87 ~ 190) 104
8267 00:42:16.886213 iDelay=191, Bit 7, Center 138 (87 ~ 190) 104
8268 00:42:16.889466 iDelay=191, Bit 8, Center 118 (71 ~ 166) 96
8269 00:42:16.892972 iDelay=191, Bit 9, Center 112 (63 ~ 162) 100
8270 00:42:16.896382 iDelay=191, Bit 10, Center 128 (83 ~ 174) 92
8271 00:42:16.902621 iDelay=191, Bit 11, Center 122 (75 ~ 170) 96
8272 00:42:16.906222 iDelay=191, Bit 12, Center 130 (79 ~ 182) 104
8273 00:42:16.909288 iDelay=191, Bit 13, Center 130 (83 ~ 178) 96
8274 00:42:16.912900 iDelay=191, Bit 14, Center 134 (83 ~ 186) 104
8275 00:42:16.915916 iDelay=191, Bit 15, Center 132 (83 ~ 182) 100
8276 00:42:16.916479 ==
8277 00:42:16.919459 Dram Type= 6, Freq= 0, CH_0, rank 1
8278 00:42:16.926010 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8279 00:42:16.926604 ==
8280 00:42:16.926989 DQS Delay:
8281 00:42:16.929464 DQS0 = 0, DQS1 = 0
8282 00:42:16.929943 DQM Delay:
8283 00:42:16.932658 DQM0 = 132, DQM1 = 125
8284 00:42:16.933134 DQ Delay:
8285 00:42:16.936050 DQ0 =130, DQ1 =134, DQ2 =130, DQ3 =130
8286 00:42:16.939460 DQ4 =134, DQ5 =124, DQ6 =138, DQ7 =138
8287 00:42:16.942486 DQ8 =118, DQ9 =112, DQ10 =128, DQ11 =122
8288 00:42:16.946314 DQ12 =130, DQ13 =130, DQ14 =134, DQ15 =132
8289 00:42:16.946881
8290 00:42:16.947259
8291 00:42:16.947606
8292 00:42:16.949053 [DramC_TX_OE_Calibration] TA2
8293 00:42:16.952702 Original DQ_B0 (3 6) =30, OEN = 27
8294 00:42:16.956108 Original DQ_B1 (3 6) =30, OEN = 27
8295 00:42:16.959675 24, 0x0, End_B0=24 End_B1=24
8296 00:42:16.962534 25, 0x0, End_B0=25 End_B1=25
8297 00:42:16.963114 26, 0x0, End_B0=26 End_B1=26
8298 00:42:16.965784 27, 0x0, End_B0=27 End_B1=27
8299 00:42:16.969217 28, 0x0, End_B0=28 End_B1=28
8300 00:42:16.972657 29, 0x0, End_B0=29 End_B1=29
8301 00:42:16.973225 30, 0x0, End_B0=30 End_B1=30
8302 00:42:16.976088 31, 0x4141, End_B0=30 End_B1=30
8303 00:42:16.979362 Byte0 end_step=30 best_step=27
8304 00:42:16.982377 Byte1 end_step=30 best_step=27
8305 00:42:16.986093 Byte0 TX OE(2T, 0.5T) = (3, 3)
8306 00:42:16.989086 Byte1 TX OE(2T, 0.5T) = (3, 3)
8307 00:42:16.989646
8308 00:42:16.990020
8309 00:42:16.995537 [DQSOSCAuto] RK1, (LSB)MR18= 0x2412, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 391 ps
8310 00:42:16.998908 CH0 RK1: MR19=303, MR18=2412
8311 00:42:17.005636 CH0_RK1: MR19=0x303, MR18=0x2412, DQSOSC=391, MR23=63, INC=24, DEC=16
8312 00:42:17.008869 [RxdqsGatingPostProcess] freq 1600
8313 00:42:17.012260 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8314 00:42:17.015860 best DQS0 dly(2T, 0.5T) = (1, 1)
8315 00:42:17.018816 best DQS1 dly(2T, 0.5T) = (1, 1)
8316 00:42:17.022237 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8317 00:42:17.025532 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8318 00:42:17.029161 best DQS0 dly(2T, 0.5T) = (1, 1)
8319 00:42:17.032371 best DQS1 dly(2T, 0.5T) = (1, 1)
8320 00:42:17.035537 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8321 00:42:17.039288 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8322 00:42:17.042368 Pre-setting of DQS Precalculation
8323 00:42:17.045613 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8324 00:42:17.046119 ==
8325 00:42:17.048842 Dram Type= 6, Freq= 0, CH_1, rank 0
8326 00:42:17.052173 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8327 00:42:17.055865 ==
8328 00:42:17.058994 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8329 00:42:17.062455 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8330 00:42:17.069372 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8331 00:42:17.072699 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8332 00:42:17.082667 [CA 0] Center 40 (11~70) winsize 60
8333 00:42:17.086303 [CA 1] Center 41 (12~71) winsize 60
8334 00:42:17.089599 [CA 2] Center 37 (8~67) winsize 60
8335 00:42:17.092723 [CA 3] Center 36 (7~66) winsize 60
8336 00:42:17.096076 [CA 4] Center 37 (7~67) winsize 61
8337 00:42:17.099400 [CA 5] Center 36 (6~66) winsize 61
8338 00:42:17.099973
8339 00:42:17.102624 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8340 00:42:17.103198
8341 00:42:17.106317 [CATrainingPosCal] consider 1 rank data
8342 00:42:17.109189 u2DelayCellTimex100 = 290/100 ps
8343 00:42:17.112361 CA0 delay=40 (11~70),Diff = 4 PI (13 cell)
8344 00:42:17.119211 CA1 delay=41 (12~71),Diff = 5 PI (16 cell)
8345 00:42:17.122620 CA2 delay=37 (8~67),Diff = 1 PI (3 cell)
8346 00:42:17.125583 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8347 00:42:17.129060 CA4 delay=37 (7~67),Diff = 1 PI (3 cell)
8348 00:42:17.132372 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
8349 00:42:17.132890
8350 00:42:17.135626 CA PerBit enable=1, Macro0, CA PI delay=36
8351 00:42:17.136093
8352 00:42:17.138766 [CBTSetCACLKResult] CA Dly = 36
8353 00:42:17.142443 CS Dly: 8 (0~39)
8354 00:42:17.145662 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8355 00:42:17.149077 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8356 00:42:17.149653 ==
8357 00:42:17.152431 Dram Type= 6, Freq= 0, CH_1, rank 1
8358 00:42:17.155771 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8359 00:42:17.156343 ==
8360 00:42:17.162223 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8361 00:42:17.165722 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8362 00:42:17.172334 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8363 00:42:17.175350 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8364 00:42:17.185533 [CA 0] Center 43 (13~73) winsize 61
8365 00:42:17.188831 [CA 1] Center 43 (13~73) winsize 61
8366 00:42:17.192344 [CA 2] Center 38 (9~68) winsize 60
8367 00:42:17.195807 [CA 3] Center 38 (9~67) winsize 59
8368 00:42:17.199183 [CA 4] Center 38 (9~67) winsize 59
8369 00:42:17.202416 [CA 5] Center 37 (8~67) winsize 60
8370 00:42:17.202747
8371 00:42:17.205909 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8372 00:42:17.206337
8373 00:42:17.208939 [CATrainingPosCal] consider 2 rank data
8374 00:42:17.212172 u2DelayCellTimex100 = 290/100 ps
8375 00:42:17.215484 CA0 delay=41 (13~70),Diff = 4 PI (13 cell)
8376 00:42:17.222180 CA1 delay=42 (13~71),Diff = 5 PI (16 cell)
8377 00:42:17.225528 CA2 delay=38 (9~67),Diff = 1 PI (3 cell)
8378 00:42:17.229021 CA3 delay=37 (9~66),Diff = 0 PI (0 cell)
8379 00:42:17.231897 CA4 delay=38 (9~67),Diff = 1 PI (3 cell)
8380 00:42:17.235649 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8381 00:42:17.236193
8382 00:42:17.238670 CA PerBit enable=1, Macro0, CA PI delay=37
8383 00:42:17.239132
8384 00:42:17.241965 [CBTSetCACLKResult] CA Dly = 37
8385 00:42:17.245178 CS Dly: 9 (0~42)
8386 00:42:17.248408 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8387 00:42:17.252095 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8388 00:42:17.252699
8389 00:42:17.255607 ----->DramcWriteLeveling(PI) begin...
8390 00:42:17.256176 ==
8391 00:42:17.258601 Dram Type= 6, Freq= 0, CH_1, rank 0
8392 00:42:17.262163 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8393 00:42:17.265522 ==
8394 00:42:17.266080 Write leveling (Byte 0): 26 => 26
8395 00:42:17.268825 Write leveling (Byte 1): 27 => 27
8396 00:42:17.272400 DramcWriteLeveling(PI) end<-----
8397 00:42:17.272998
8398 00:42:17.273354 ==
8399 00:42:17.275306 Dram Type= 6, Freq= 0, CH_1, rank 0
8400 00:42:17.281895 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8401 00:42:17.282442 ==
8402 00:42:17.282802 [Gating] SW mode calibration
8403 00:42:17.292260 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8404 00:42:17.295821 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8405 00:42:17.299185 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8406 00:42:17.305452 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8407 00:42:17.308983 1 4 8 | B1->B0 | 2c2c 3131 | 1 1 | (1 1) (1 1)
8408 00:42:17.312256 1 4 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8409 00:42:17.318913 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8410 00:42:17.322044 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8411 00:42:17.325607 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8412 00:42:17.331897 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8413 00:42:17.335214 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8414 00:42:17.338531 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8415 00:42:17.345473 1 5 8 | B1->B0 | 2f2f 2929 | 0 0 | (0 1) (1 0)
8416 00:42:17.348543 1 5 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8417 00:42:17.351903 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8418 00:42:17.358626 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8419 00:42:17.362322 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8420 00:42:17.365141 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8421 00:42:17.371737 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8422 00:42:17.375768 1 6 4 | B1->B0 | 2525 2626 | 1 0 | (1 1) (0 0)
8423 00:42:17.378728 1 6 8 | B1->B0 | 3d3d 4343 | 0 0 | (0 0) (0 0)
8424 00:42:17.385273 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8425 00:42:17.389021 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8426 00:42:17.392034 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8427 00:42:17.398623 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8428 00:42:17.401995 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8429 00:42:17.405489 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8430 00:42:17.411742 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8431 00:42:17.415083 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8432 00:42:17.418275 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8433 00:42:17.424903 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8434 00:42:17.428118 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8435 00:42:17.431440 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8436 00:42:17.434648 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8437 00:42:17.441317 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8438 00:42:17.444522 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8439 00:42:17.448345 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8440 00:42:17.454841 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8441 00:42:17.458199 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8442 00:42:17.461386 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8443 00:42:17.468214 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8444 00:42:17.471611 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8445 00:42:17.475003 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8446 00:42:17.481606 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8447 00:42:17.484936 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8448 00:42:17.488262 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8449 00:42:17.491611 Total UI for P1: 0, mck2ui 16
8450 00:42:17.495071 best dqsien dly found for B0: ( 1, 9, 8)
8451 00:42:17.501538 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8452 00:42:17.502097 Total UI for P1: 0, mck2ui 16
8453 00:42:17.508407 best dqsien dly found for B1: ( 1, 9, 10)
8454 00:42:17.511892 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8455 00:42:17.515112 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8456 00:42:17.515581
8457 00:42:17.518257 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8458 00:42:17.521340 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8459 00:42:17.524668 [Gating] SW calibration Done
8460 00:42:17.525258 ==
8461 00:42:17.528344 Dram Type= 6, Freq= 0, CH_1, rank 0
8462 00:42:17.531359 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8463 00:42:17.531932 ==
8464 00:42:17.534795 RX Vref Scan: 0
8465 00:42:17.535420
8466 00:42:17.535836 RX Vref 0 -> 0, step: 1
8467 00:42:17.536184
8468 00:42:17.538046 RX Delay 0 -> 252, step: 8
8469 00:42:17.541195 iDelay=200, Bit 0, Center 139 (96 ~ 183) 88
8470 00:42:17.544753 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8471 00:42:17.551630 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8472 00:42:17.554811 iDelay=200, Bit 3, Center 139 (88 ~ 191) 104
8473 00:42:17.558310 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8474 00:42:17.562108 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8475 00:42:17.564644 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8476 00:42:17.571572 iDelay=200, Bit 7, Center 135 (88 ~ 183) 96
8477 00:42:17.574764 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8478 00:42:17.578329 iDelay=200, Bit 9, Center 119 (72 ~ 167) 96
8479 00:42:17.581372 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8480 00:42:17.584700 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8481 00:42:17.591604 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8482 00:42:17.595154 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8483 00:42:17.597997 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8484 00:42:17.601389 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8485 00:42:17.601863 ==
8486 00:42:17.604997 Dram Type= 6, Freq= 0, CH_1, rank 0
8487 00:42:17.611542 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8488 00:42:17.612117 ==
8489 00:42:17.612490 DQS Delay:
8490 00:42:17.614914 DQS0 = 0, DQS1 = 0
8491 00:42:17.615476 DQM Delay:
8492 00:42:17.615852 DQM0 = 137, DQM1 = 130
8493 00:42:17.617708 DQ Delay:
8494 00:42:17.621304 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =139
8495 00:42:17.624931 DQ4 =135, DQ5 =147, DQ6 =147, DQ7 =135
8496 00:42:17.627906 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
8497 00:42:17.631494 DQ12 =139, DQ13 =135, DQ14 =139, DQ15 =139
8498 00:42:17.631968
8499 00:42:17.632337
8500 00:42:17.632721 ==
8501 00:42:17.634367 Dram Type= 6, Freq= 0, CH_1, rank 0
8502 00:42:17.637842 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8503 00:42:17.638315 ==
8504 00:42:17.641348
8505 00:42:17.641816
8506 00:42:17.642185 TX Vref Scan disable
8507 00:42:17.644497 == TX Byte 0 ==
8508 00:42:17.647770 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8509 00:42:17.651207 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8510 00:42:17.654635 == TX Byte 1 ==
8511 00:42:17.657741 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8512 00:42:17.661252 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8513 00:42:17.661728 ==
8514 00:42:17.664358 Dram Type= 6, Freq= 0, CH_1, rank 0
8515 00:42:17.670913 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8516 00:42:17.671471 ==
8517 00:42:17.682868
8518 00:42:17.686121 TX Vref early break, caculate TX vref
8519 00:42:17.689521 TX Vref=16, minBit 10, minWin=22, winSum=374
8520 00:42:17.693164 TX Vref=18, minBit 10, minWin=22, winSum=385
8521 00:42:17.696111 TX Vref=20, minBit 0, minWin=24, winSum=393
8522 00:42:17.699500 TX Vref=22, minBit 10, minWin=23, winSum=402
8523 00:42:17.702695 TX Vref=24, minBit 10, minWin=24, winSum=415
8524 00:42:17.709667 TX Vref=26, minBit 10, minWin=24, winSum=421
8525 00:42:17.712843 TX Vref=28, minBit 0, minWin=26, winSum=427
8526 00:42:17.716381 TX Vref=30, minBit 13, minWin=24, winSum=415
8527 00:42:17.719432 TX Vref=32, minBit 12, minWin=24, winSum=408
8528 00:42:17.723078 TX Vref=34, minBit 5, minWin=24, winSum=401
8529 00:42:17.729520 [TxChooseVref] Worse bit 0, Min win 26, Win sum 427, Final Vref 28
8530 00:42:17.730079
8531 00:42:17.732456 Final TX Range 0 Vref 28
8532 00:42:17.733052
8533 00:42:17.733427 ==
8534 00:42:17.736097 Dram Type= 6, Freq= 0, CH_1, rank 0
8535 00:42:17.739460 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8536 00:42:17.739930 ==
8537 00:42:17.740299
8538 00:42:17.740679
8539 00:42:17.742695 TX Vref Scan disable
8540 00:42:17.749273 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8541 00:42:17.749853 == TX Byte 0 ==
8542 00:42:17.752983 u2DelayCellOfst[0]=13 cells (4 PI)
8543 00:42:17.755882 u2DelayCellOfst[1]=6 cells (2 PI)
8544 00:42:17.759626 u2DelayCellOfst[2]=0 cells (0 PI)
8545 00:42:17.762713 u2DelayCellOfst[3]=3 cells (1 PI)
8546 00:42:17.766299 u2DelayCellOfst[4]=6 cells (2 PI)
8547 00:42:17.769437 u2DelayCellOfst[5]=16 cells (5 PI)
8548 00:42:17.772859 u2DelayCellOfst[6]=16 cells (5 PI)
8549 00:42:17.776114 u2DelayCellOfst[7]=3 cells (1 PI)
8550 00:42:17.779575 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8551 00:42:17.783070 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8552 00:42:17.783633 == TX Byte 1 ==
8553 00:42:17.786015 u2DelayCellOfst[8]=0 cells (0 PI)
8554 00:42:17.789263 u2DelayCellOfst[9]=3 cells (1 PI)
8555 00:42:17.793311 u2DelayCellOfst[10]=10 cells (3 PI)
8556 00:42:17.796202 u2DelayCellOfst[11]=3 cells (1 PI)
8557 00:42:17.799764 u2DelayCellOfst[12]=16 cells (5 PI)
8558 00:42:17.803139 u2DelayCellOfst[13]=16 cells (5 PI)
8559 00:42:17.806216 u2DelayCellOfst[14]=20 cells (6 PI)
8560 00:42:17.809360 u2DelayCellOfst[15]=16 cells (5 PI)
8561 00:42:17.813205 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8562 00:42:17.819861 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8563 00:42:17.820432 DramC Write-DBI on
8564 00:42:17.820840 ==
8565 00:42:17.822947 Dram Type= 6, Freq= 0, CH_1, rank 0
8566 00:42:17.826286 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8567 00:42:17.826869 ==
8568 00:42:17.829491
8569 00:42:17.830060
8570 00:42:17.830429 TX Vref Scan disable
8571 00:42:17.832941 == TX Byte 0 ==
8572 00:42:17.836162 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8573 00:42:17.839041 == TX Byte 1 ==
8574 00:42:17.843048 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8575 00:42:17.843620 DramC Write-DBI off
8576 00:42:17.846062
8577 00:42:17.846627 [DATLAT]
8578 00:42:17.846997 Freq=1600, CH1 RK0
8579 00:42:17.847340
8580 00:42:17.849184 DATLAT Default: 0xf
8581 00:42:17.849648 0, 0xFFFF, sum = 0
8582 00:42:17.852508 1, 0xFFFF, sum = 0
8583 00:42:17.853018 2, 0xFFFF, sum = 0
8584 00:42:17.855762 3, 0xFFFF, sum = 0
8585 00:42:17.856234 4, 0xFFFF, sum = 0
8586 00:42:17.859260 5, 0xFFFF, sum = 0
8587 00:42:17.862488 6, 0xFFFF, sum = 0
8588 00:42:17.863159 7, 0xFFFF, sum = 0
8589 00:42:17.866094 8, 0xFFFF, sum = 0
8590 00:42:17.866666 9, 0xFFFF, sum = 0
8591 00:42:17.869080 10, 0xFFFF, sum = 0
8592 00:42:17.869556 11, 0xFFFF, sum = 0
8593 00:42:17.872540 12, 0xFFFF, sum = 0
8594 00:42:17.873156 13, 0xFFFF, sum = 0
8595 00:42:17.875715 14, 0x0, sum = 1
8596 00:42:17.876251 15, 0x0, sum = 2
8597 00:42:17.879580 16, 0x0, sum = 3
8598 00:42:17.880170 17, 0x0, sum = 4
8599 00:42:17.882634 best_step = 15
8600 00:42:17.883101
8601 00:42:17.883464 ==
8602 00:42:17.885709 Dram Type= 6, Freq= 0, CH_1, rank 0
8603 00:42:17.889365 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8604 00:42:17.889945 ==
8605 00:42:17.890317 RX Vref Scan: 1
8606 00:42:17.890659
8607 00:42:17.892718 Set Vref Range= 24 -> 127
8608 00:42:17.893275
8609 00:42:17.895988 RX Vref 24 -> 127, step: 1
8610 00:42:17.896610
8611 00:42:17.899268 RX Delay 19 -> 252, step: 4
8612 00:42:17.899838
8613 00:42:17.902440 Set Vref, RX VrefLevel [Byte0]: 24
8614 00:42:17.905594 [Byte1]: 24
8615 00:42:17.906160
8616 00:42:17.908886 Set Vref, RX VrefLevel [Byte0]: 25
8617 00:42:17.912471 [Byte1]: 25
8618 00:42:17.913080
8619 00:42:17.915916 Set Vref, RX VrefLevel [Byte0]: 26
8620 00:42:17.919312 [Byte1]: 26
8621 00:42:17.922920
8622 00:42:17.923482 Set Vref, RX VrefLevel [Byte0]: 27
8623 00:42:17.926301 [Byte1]: 27
8624 00:42:17.930465
8625 00:42:17.930943 Set Vref, RX VrefLevel [Byte0]: 28
8626 00:42:17.933587 [Byte1]: 28
8627 00:42:17.937757
8628 00:42:17.938225 Set Vref, RX VrefLevel [Byte0]: 29
8629 00:42:17.941156 [Byte1]: 29
8630 00:42:17.945534
8631 00:42:17.946119 Set Vref, RX VrefLevel [Byte0]: 30
8632 00:42:17.948664 [Byte1]: 30
8633 00:42:17.953255
8634 00:42:17.953823 Set Vref, RX VrefLevel [Byte0]: 31
8635 00:42:17.956659 [Byte1]: 31
8636 00:42:17.960494
8637 00:42:17.961114 Set Vref, RX VrefLevel [Byte0]: 32
8638 00:42:17.963925 [Byte1]: 32
8639 00:42:17.968086
8640 00:42:17.968687 Set Vref, RX VrefLevel [Byte0]: 33
8641 00:42:17.971377 [Byte1]: 33
8642 00:42:17.975686
8643 00:42:17.976158 Set Vref, RX VrefLevel [Byte0]: 34
8644 00:42:17.979048 [Byte1]: 34
8645 00:42:17.983196
8646 00:42:17.983663 Set Vref, RX VrefLevel [Byte0]: 35
8647 00:42:17.986354 [Byte1]: 35
8648 00:42:17.991231
8649 00:42:17.991799 Set Vref, RX VrefLevel [Byte0]: 36
8650 00:42:17.994289 [Byte1]: 36
8651 00:42:17.998829
8652 00:42:17.999401 Set Vref, RX VrefLevel [Byte0]: 37
8653 00:42:18.001508 [Byte1]: 37
8654 00:42:18.006225
8655 00:42:18.006788 Set Vref, RX VrefLevel [Byte0]: 38
8656 00:42:18.009355 [Byte1]: 38
8657 00:42:18.013478
8658 00:42:18.014041 Set Vref, RX VrefLevel [Byte0]: 39
8659 00:42:18.016985 [Byte1]: 39
8660 00:42:18.021477
8661 00:42:18.022048 Set Vref, RX VrefLevel [Byte0]: 40
8662 00:42:18.024350 [Byte1]: 40
8663 00:42:18.028903
8664 00:42:18.029469 Set Vref, RX VrefLevel [Byte0]: 41
8665 00:42:18.031945 [Byte1]: 41
8666 00:42:18.036610
8667 00:42:18.037185 Set Vref, RX VrefLevel [Byte0]: 42
8668 00:42:18.039771 [Byte1]: 42
8669 00:42:18.043875
8670 00:42:18.044445 Set Vref, RX VrefLevel [Byte0]: 43
8671 00:42:18.047274 [Byte1]: 43
8672 00:42:18.051332
8673 00:42:18.051898 Set Vref, RX VrefLevel [Byte0]: 44
8674 00:42:18.055030 [Byte1]: 44
8675 00:42:18.059206
8676 00:42:18.059773 Set Vref, RX VrefLevel [Byte0]: 45
8677 00:42:18.062435 [Byte1]: 45
8678 00:42:18.066676
8679 00:42:18.067238 Set Vref, RX VrefLevel [Byte0]: 46
8680 00:42:18.069988 [Byte1]: 46
8681 00:42:18.074396
8682 00:42:18.074965 Set Vref, RX VrefLevel [Byte0]: 47
8683 00:42:18.077336 [Byte1]: 47
8684 00:42:18.081749
8685 00:42:18.082236 Set Vref, RX VrefLevel [Byte0]: 48
8686 00:42:18.084992 [Byte1]: 48
8687 00:42:18.089609
8688 00:42:18.090190 Set Vref, RX VrefLevel [Byte0]: 49
8689 00:42:18.092679 [Byte1]: 49
8690 00:42:18.096721
8691 00:42:18.097275 Set Vref, RX VrefLevel [Byte0]: 50
8692 00:42:18.100182 [Byte1]: 50
8693 00:42:18.104263
8694 00:42:18.104878 Set Vref, RX VrefLevel [Byte0]: 51
8695 00:42:18.107981 [Byte1]: 51
8696 00:42:18.111957
8697 00:42:18.112525 Set Vref, RX VrefLevel [Byte0]: 52
8698 00:42:18.115363 [Byte1]: 52
8699 00:42:18.119795
8700 00:42:18.120367 Set Vref, RX VrefLevel [Byte0]: 53
8701 00:42:18.123266 [Byte1]: 53
8702 00:42:18.127195
8703 00:42:18.127763 Set Vref, RX VrefLevel [Byte0]: 54
8704 00:42:18.130231 [Byte1]: 54
8705 00:42:18.134911
8706 00:42:18.135480 Set Vref, RX VrefLevel [Byte0]: 55
8707 00:42:18.138036 [Byte1]: 55
8708 00:42:18.142628
8709 00:42:18.143198 Set Vref, RX VrefLevel [Byte0]: 56
8710 00:42:18.146035 [Byte1]: 56
8711 00:42:18.149942
8712 00:42:18.150522 Set Vref, RX VrefLevel [Byte0]: 57
8713 00:42:18.153242 [Byte1]: 57
8714 00:42:18.157376
8715 00:42:18.157943 Set Vref, RX VrefLevel [Byte0]: 58
8716 00:42:18.161120 [Byte1]: 58
8717 00:42:18.165036
8718 00:42:18.165601 Set Vref, RX VrefLevel [Byte0]: 59
8719 00:42:18.168507 [Byte1]: 59
8720 00:42:18.172729
8721 00:42:18.173287 Set Vref, RX VrefLevel [Byte0]: 60
8722 00:42:18.176091 [Byte1]: 60
8723 00:42:18.180452
8724 00:42:18.181069 Set Vref, RX VrefLevel [Byte0]: 61
8725 00:42:18.183803 [Byte1]: 61
8726 00:42:18.187896
8727 00:42:18.188361 Set Vref, RX VrefLevel [Byte0]: 62
8728 00:42:18.191592 [Byte1]: 62
8729 00:42:18.195235
8730 00:42:18.195839 Set Vref, RX VrefLevel [Byte0]: 63
8731 00:42:18.199029 [Byte1]: 63
8732 00:42:18.203344
8733 00:42:18.203978 Set Vref, RX VrefLevel [Byte0]: 64
8734 00:42:18.206439 [Byte1]: 64
8735 00:42:18.210838
8736 00:42:18.211408 Set Vref, RX VrefLevel [Byte0]: 65
8737 00:42:18.214242 [Byte1]: 65
8738 00:42:18.218110
8739 00:42:18.218678 Set Vref, RX VrefLevel [Byte0]: 66
8740 00:42:18.221447 [Byte1]: 66
8741 00:42:18.225909
8742 00:42:18.226477 Set Vref, RX VrefLevel [Byte0]: 67
8743 00:42:18.228936 [Byte1]: 67
8744 00:42:18.233165
8745 00:42:18.233761 Set Vref, RX VrefLevel [Byte0]: 68
8746 00:42:18.236739 [Byte1]: 68
8747 00:42:18.240476
8748 00:42:18.240997 Set Vref, RX VrefLevel [Byte0]: 69
8749 00:42:18.247408 [Byte1]: 69
8750 00:42:18.247983
8751 00:42:18.250412 Set Vref, RX VrefLevel [Byte0]: 70
8752 00:42:18.253769 [Byte1]: 70
8753 00:42:18.254341
8754 00:42:18.257071 Set Vref, RX VrefLevel [Byte0]: 71
8755 00:42:18.260620 [Byte1]: 71
8756 00:42:18.261199
8757 00:42:18.263826 Set Vref, RX VrefLevel [Byte0]: 72
8758 00:42:18.267361 [Byte1]: 72
8759 00:42:18.271255
8760 00:42:18.271823 Set Vref, RX VrefLevel [Byte0]: 73
8761 00:42:18.274443 [Byte1]: 73
8762 00:42:18.278755
8763 00:42:18.279324 Set Vref, RX VrefLevel [Byte0]: 74
8764 00:42:18.282124 [Byte1]: 74
8765 00:42:18.286357
8766 00:42:18.286824 Final RX Vref Byte 0 = 59 to rank0
8767 00:42:18.289695 Final RX Vref Byte 1 = 63 to rank0
8768 00:42:18.292870 Final RX Vref Byte 0 = 59 to rank1
8769 00:42:18.296650 Final RX Vref Byte 1 = 63 to rank1==
8770 00:42:18.299417 Dram Type= 6, Freq= 0, CH_1, rank 0
8771 00:42:18.305865 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8772 00:42:18.306336 ==
8773 00:42:18.306705 DQS Delay:
8774 00:42:18.307043 DQS0 = 0, DQS1 = 0
8775 00:42:18.309739 DQM Delay:
8776 00:42:18.310275 DQM0 = 134, DQM1 = 129
8777 00:42:18.313367 DQ Delay:
8778 00:42:18.316532 DQ0 =138, DQ1 =128, DQ2 =122, DQ3 =132
8779 00:42:18.319952 DQ4 =130, DQ5 =144, DQ6 =146, DQ7 =132
8780 00:42:18.322929 DQ8 =116, DQ9 =120, DQ10 =132, DQ11 =122
8781 00:42:18.326141 DQ12 =140, DQ13 =134, DQ14 =136, DQ15 =134
8782 00:42:18.326611
8783 00:42:18.326975
8784 00:42:18.327313
8785 00:42:18.329453 [DramC_TX_OE_Calibration] TA2
8786 00:42:18.333198 Original DQ_B0 (3 6) =30, OEN = 27
8787 00:42:18.336691 Original DQ_B1 (3 6) =30, OEN = 27
8788 00:42:18.339441 24, 0x0, End_B0=24 End_B1=24
8789 00:42:18.340014 25, 0x0, End_B0=25 End_B1=25
8790 00:42:18.342549 26, 0x0, End_B0=26 End_B1=26
8791 00:42:18.346279 27, 0x0, End_B0=27 End_B1=27
8792 00:42:18.349539 28, 0x0, End_B0=28 End_B1=28
8793 00:42:18.350018 29, 0x0, End_B0=29 End_B1=29
8794 00:42:18.352919 30, 0x0, End_B0=30 End_B1=30
8795 00:42:18.356135 31, 0x4141, End_B0=30 End_B1=30
8796 00:42:18.359625 Byte0 end_step=30 best_step=27
8797 00:42:18.363082 Byte1 end_step=30 best_step=27
8798 00:42:18.365968 Byte0 TX OE(2T, 0.5T) = (3, 3)
8799 00:42:18.366438 Byte1 TX OE(2T, 0.5T) = (3, 3)
8800 00:42:18.369656
8801 00:42:18.370223
8802 00:42:18.376080 [DQSOSCAuto] RK0, (LSB)MR18= 0x1927, (MSB)MR19= 0x303, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
8803 00:42:18.379615 CH1 RK0: MR19=303, MR18=1927
8804 00:42:18.385930 CH1_RK0: MR19=0x303, MR18=0x1927, DQSOSC=390, MR23=63, INC=24, DEC=16
8805 00:42:18.386433
8806 00:42:18.389429 ----->DramcWriteLeveling(PI) begin...
8807 00:42:18.389903 ==
8808 00:42:18.392667 Dram Type= 6, Freq= 0, CH_1, rank 1
8809 00:42:18.396227 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8810 00:42:18.396896 ==
8811 00:42:18.399074 Write leveling (Byte 0): 24 => 24
8812 00:42:18.402499 Write leveling (Byte 1): 28 => 28
8813 00:42:18.405758 DramcWriteLeveling(PI) end<-----
8814 00:42:18.406226
8815 00:42:18.406590 ==
8816 00:42:18.408961 Dram Type= 6, Freq= 0, CH_1, rank 1
8817 00:42:18.412593 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8818 00:42:18.413160 ==
8819 00:42:18.415834 [Gating] SW mode calibration
8820 00:42:18.422750 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8821 00:42:18.429180 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8822 00:42:18.432589 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8823 00:42:18.435842 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8824 00:42:18.442272 1 4 8 | B1->B0 | 3131 2323 | 1 0 | (1 1) (0 0)
8825 00:42:18.445409 1 4 12 | B1->B0 | 3434 2828 | 1 1 | (1 1) (1 1)
8826 00:42:18.449085 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8827 00:42:18.455924 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8828 00:42:18.458842 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8829 00:42:18.462204 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8830 00:42:18.468902 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8831 00:42:18.472069 1 5 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 0)
8832 00:42:18.475470 1 5 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 0)
8833 00:42:18.482195 1 5 12 | B1->B0 | 2323 3030 | 0 0 | (0 0) (1 0)
8834 00:42:18.485499 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8835 00:42:18.489165 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8836 00:42:18.495360 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8837 00:42:18.499019 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8838 00:42:18.502140 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8839 00:42:18.508682 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8840 00:42:18.512451 1 6 8 | B1->B0 | 4646 2323 | 0 0 | (0 0) (0 0)
8841 00:42:18.515581 1 6 12 | B1->B0 | 4646 3c3c | 0 0 | (0 0) (0 0)
8842 00:42:18.522341 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8843 00:42:18.525721 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8844 00:42:18.529406 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8845 00:42:18.532313 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8846 00:42:18.539112 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8847 00:42:18.541860 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8848 00:42:18.545243 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8849 00:42:18.552128 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8850 00:42:18.555430 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8851 00:42:18.558965 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8852 00:42:18.565731 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8853 00:42:18.568751 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8854 00:42:18.572302 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8855 00:42:18.578745 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8856 00:42:18.582180 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8857 00:42:18.585323 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8858 00:42:18.592018 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8859 00:42:18.595361 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8860 00:42:18.598669 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8861 00:42:18.605412 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8862 00:42:18.608689 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8863 00:42:18.611998 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8864 00:42:18.619049 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8865 00:42:18.622294 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8866 00:42:18.625589 Total UI for P1: 0, mck2ui 16
8867 00:42:18.628998 best dqsien dly found for B1: ( 1, 9, 6)
8868 00:42:18.632106 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8869 00:42:18.635709 Total UI for P1: 0, mck2ui 16
8870 00:42:18.638578 best dqsien dly found for B0: ( 1, 9, 8)
8871 00:42:18.641744 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8872 00:42:18.645218 best DQS1 dly(MCK, UI, PI) = (1, 9, 6)
8873 00:42:18.645699
8874 00:42:18.648308 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8875 00:42:18.655473 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 6)
8876 00:42:18.656058 [Gating] SW calibration Done
8877 00:42:18.656437 ==
8878 00:42:18.658925 Dram Type= 6, Freq= 0, CH_1, rank 1
8879 00:42:18.665496 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8880 00:42:18.666082 ==
8881 00:42:18.666462 RX Vref Scan: 0
8882 00:42:18.666811
8883 00:42:18.668682 RX Vref 0 -> 0, step: 1
8884 00:42:18.669163
8885 00:42:18.671609 RX Delay 0 -> 252, step: 8
8886 00:42:18.675298 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8887 00:42:18.678617 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8888 00:42:18.681494 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8889 00:42:18.685035 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8890 00:42:18.691672 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8891 00:42:18.695062 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8892 00:42:18.698052 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8893 00:42:18.701538 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8894 00:42:18.704796 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8895 00:42:18.711107 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8896 00:42:18.715157 iDelay=200, Bit 10, Center 135 (80 ~ 191) 112
8897 00:42:18.718033 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8898 00:42:18.721642 iDelay=200, Bit 12, Center 143 (88 ~ 199) 112
8899 00:42:18.728518 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8900 00:42:18.731611 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8901 00:42:18.734827 iDelay=200, Bit 15, Center 143 (88 ~ 199) 112
8902 00:42:18.735303 ==
8903 00:42:18.738295 Dram Type= 6, Freq= 0, CH_1, rank 1
8904 00:42:18.741200 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8905 00:42:18.741897 ==
8906 00:42:18.744625 DQS Delay:
8907 00:42:18.745100 DQS0 = 0, DQS1 = 0
8908 00:42:18.745476 DQM Delay:
8909 00:42:18.748046 DQM0 = 136, DQM1 = 132
8910 00:42:18.748522 DQ Delay:
8911 00:42:18.751578 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8912 00:42:18.755208 DQ4 =139, DQ5 =147, DQ6 =143, DQ7 =135
8913 00:42:18.761411 DQ8 =115, DQ9 =119, DQ10 =135, DQ11 =127
8914 00:42:18.764798 DQ12 =143, DQ13 =139, DQ14 =139, DQ15 =143
8915 00:42:18.765287
8916 00:42:18.765660
8917 00:42:18.766006 ==
8918 00:42:18.767961 Dram Type= 6, Freq= 0, CH_1, rank 1
8919 00:42:18.771860 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8920 00:42:18.772449 ==
8921 00:42:18.772902
8922 00:42:18.773259
8923 00:42:18.774448 TX Vref Scan disable
8924 00:42:18.778160 == TX Byte 0 ==
8925 00:42:18.781415 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8926 00:42:18.784801 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8927 00:42:18.788039 == TX Byte 1 ==
8928 00:42:18.791571 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8929 00:42:18.795060 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8930 00:42:18.795645 ==
8931 00:42:18.798262 Dram Type= 6, Freq= 0, CH_1, rank 1
8932 00:42:18.801394 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8933 00:42:18.801874 ==
8934 00:42:18.815901
8935 00:42:18.819087 TX Vref early break, caculate TX vref
8936 00:42:18.821940 TX Vref=16, minBit 9, minWin=21, winSum=380
8937 00:42:18.825286 TX Vref=18, minBit 9, minWin=23, winSum=391
8938 00:42:18.829185 TX Vref=20, minBit 9, minWin=23, winSum=395
8939 00:42:18.831984 TX Vref=22, minBit 8, minWin=24, winSum=407
8940 00:42:18.835547 TX Vref=24, minBit 9, minWin=23, winSum=415
8941 00:42:18.842143 TX Vref=26, minBit 10, minWin=25, winSum=423
8942 00:42:18.845491 TX Vref=28, minBit 12, minWin=25, winSum=424
8943 00:42:18.848765 TX Vref=30, minBit 9, minWin=24, winSum=410
8944 00:42:18.852277 TX Vref=32, minBit 10, minWin=24, winSum=410
8945 00:42:18.855845 TX Vref=34, minBit 0, minWin=24, winSum=398
8946 00:42:18.862000 [TxChooseVref] Worse bit 12, Min win 25, Win sum 424, Final Vref 28
8947 00:42:18.862582
8948 00:42:18.865572 Final TX Range 0 Vref 28
8949 00:42:18.866158
8950 00:42:18.866539 ==
8951 00:42:18.869017 Dram Type= 6, Freq= 0, CH_1, rank 1
8952 00:42:18.871824 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8953 00:42:18.872405 ==
8954 00:42:18.872846
8955 00:42:18.873201
8956 00:42:18.875365 TX Vref Scan disable
8957 00:42:18.882018 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8958 00:42:18.882594 == TX Byte 0 ==
8959 00:42:18.885472 u2DelayCellOfst[0]=13 cells (4 PI)
8960 00:42:18.888501 u2DelayCellOfst[1]=10 cells (3 PI)
8961 00:42:18.892336 u2DelayCellOfst[2]=0 cells (0 PI)
8962 00:42:18.895424 u2DelayCellOfst[3]=3 cells (1 PI)
8963 00:42:18.898563 u2DelayCellOfst[4]=6 cells (2 PI)
8964 00:42:18.902136 u2DelayCellOfst[5]=16 cells (5 PI)
8965 00:42:18.905263 u2DelayCellOfst[6]=16 cells (5 PI)
8966 00:42:18.905741 u2DelayCellOfst[7]=3 cells (1 PI)
8967 00:42:18.911887 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8968 00:42:18.915481 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8969 00:42:18.916068 == TX Byte 1 ==
8970 00:42:18.918674 u2DelayCellOfst[8]=0 cells (0 PI)
8971 00:42:18.921774 u2DelayCellOfst[9]=3 cells (1 PI)
8972 00:42:18.925077 u2DelayCellOfst[10]=10 cells (3 PI)
8973 00:42:18.928637 u2DelayCellOfst[11]=3 cells (1 PI)
8974 00:42:18.931686 u2DelayCellOfst[12]=13 cells (4 PI)
8975 00:42:18.935135 u2DelayCellOfst[13]=16 cells (5 PI)
8976 00:42:18.938243 u2DelayCellOfst[14]=20 cells (6 PI)
8977 00:42:18.941613 u2DelayCellOfst[15]=16 cells (5 PI)
8978 00:42:18.944769 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8979 00:42:18.951853 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8980 00:42:18.952442 DramC Write-DBI on
8981 00:42:18.952931 ==
8982 00:42:18.955098 Dram Type= 6, Freq= 0, CH_1, rank 1
8983 00:42:18.958637 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8984 00:42:18.961952 ==
8985 00:42:18.962536
8986 00:42:18.962913
8987 00:42:18.963262 TX Vref Scan disable
8988 00:42:18.964729 == TX Byte 0 ==
8989 00:42:18.968180 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8990 00:42:18.971753 == TX Byte 1 ==
8991 00:42:18.974860 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8992 00:42:18.978309 DramC Write-DBI off
8993 00:42:18.978891
8994 00:42:18.979270 [DATLAT]
8995 00:42:18.979618 Freq=1600, CH1 RK1
8996 00:42:18.979958
8997 00:42:18.981724 DATLAT Default: 0xf
8998 00:42:18.982306 0, 0xFFFF, sum = 0
8999 00:42:18.984970 1, 0xFFFF, sum = 0
9000 00:42:18.988347 2, 0xFFFF, sum = 0
9001 00:42:18.988881 3, 0xFFFF, sum = 0
9002 00:42:18.991549 4, 0xFFFF, sum = 0
9003 00:42:18.992163 5, 0xFFFF, sum = 0
9004 00:42:18.994592 6, 0xFFFF, sum = 0
9005 00:42:18.995089 7, 0xFFFF, sum = 0
9006 00:42:18.998351 8, 0xFFFF, sum = 0
9007 00:42:18.998936 9, 0xFFFF, sum = 0
9008 00:42:19.001417 10, 0xFFFF, sum = 0
9009 00:42:19.002005 11, 0xFFFF, sum = 0
9010 00:42:19.004737 12, 0xFFFF, sum = 0
9011 00:42:19.005221 13, 0xFFFF, sum = 0
9012 00:42:19.008444 14, 0x0, sum = 1
9013 00:42:19.009072 15, 0x0, sum = 2
9014 00:42:19.011437 16, 0x0, sum = 3
9015 00:42:19.011919 17, 0x0, sum = 4
9016 00:42:19.014973 best_step = 15
9017 00:42:19.015546
9018 00:42:19.015923 ==
9019 00:42:19.018733 Dram Type= 6, Freq= 0, CH_1, rank 1
9020 00:42:19.021656 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9021 00:42:19.022140 ==
9022 00:42:19.022518 RX Vref Scan: 0
9023 00:42:19.025252
9024 00:42:19.025825 RX Vref 0 -> 0, step: 1
9025 00:42:19.026206
9026 00:42:19.028475 RX Delay 19 -> 252, step: 4
9027 00:42:19.031453 iDelay=195, Bit 0, Center 136 (91 ~ 182) 92
9028 00:42:19.038361 iDelay=195, Bit 1, Center 130 (83 ~ 178) 96
9029 00:42:19.041339 iDelay=195, Bit 2, Center 120 (71 ~ 170) 100
9030 00:42:19.044737 iDelay=195, Bit 3, Center 132 (83 ~ 182) 100
9031 00:42:19.048683 iDelay=195, Bit 4, Center 134 (87 ~ 182) 96
9032 00:42:19.051973 iDelay=195, Bit 5, Center 144 (99 ~ 190) 92
9033 00:42:19.055012 iDelay=195, Bit 6, Center 142 (95 ~ 190) 96
9034 00:42:19.061504 iDelay=195, Bit 7, Center 130 (83 ~ 178) 96
9035 00:42:19.065319 iDelay=195, Bit 8, Center 112 (63 ~ 162) 100
9036 00:42:19.068605 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
9037 00:42:19.071568 iDelay=195, Bit 10, Center 130 (79 ~ 182) 104
9038 00:42:19.075078 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
9039 00:42:19.081572 iDelay=195, Bit 12, Center 138 (87 ~ 190) 104
9040 00:42:19.084948 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
9041 00:42:19.088206 iDelay=195, Bit 14, Center 138 (91 ~ 186) 96
9042 00:42:19.091835 iDelay=195, Bit 15, Center 140 (87 ~ 194) 108
9043 00:42:19.092423 ==
9044 00:42:19.095210 Dram Type= 6, Freq= 0, CH_1, rank 1
9045 00:42:19.101870 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9046 00:42:19.102462 ==
9047 00:42:19.102845 DQS Delay:
9048 00:42:19.103196 DQS0 = 0, DQS1 = 0
9049 00:42:19.104860 DQM Delay:
9050 00:42:19.105335 DQM0 = 133, DQM1 = 129
9051 00:42:19.108354 DQ Delay:
9052 00:42:19.111503 DQ0 =136, DQ1 =130, DQ2 =120, DQ3 =132
9053 00:42:19.114766 DQ4 =134, DQ5 =144, DQ6 =142, DQ7 =130
9054 00:42:19.118021 DQ8 =112, DQ9 =118, DQ10 =130, DQ11 =124
9055 00:42:19.121230 DQ12 =138, DQ13 =138, DQ14 =138, DQ15 =140
9056 00:42:19.121705
9057 00:42:19.122077
9058 00:42:19.122420
9059 00:42:19.124847 [DramC_TX_OE_Calibration] TA2
9060 00:42:19.128011 Original DQ_B0 (3 6) =30, OEN = 27
9061 00:42:19.131196 Original DQ_B1 (3 6) =30, OEN = 27
9062 00:42:19.134704 24, 0x0, End_B0=24 End_B1=24
9063 00:42:19.135278 25, 0x0, End_B0=25 End_B1=25
9064 00:42:19.138217 26, 0x0, End_B0=26 End_B1=26
9065 00:42:19.141296 27, 0x0, End_B0=27 End_B1=27
9066 00:42:19.144678 28, 0x0, End_B0=28 End_B1=28
9067 00:42:19.145158 29, 0x0, End_B0=29 End_B1=29
9068 00:42:19.147883 30, 0x0, End_B0=30 End_B1=30
9069 00:42:19.151381 31, 0x4141, End_B0=30 End_B1=30
9070 00:42:19.154829 Byte0 end_step=30 best_step=27
9071 00:42:19.158300 Byte1 end_step=30 best_step=27
9072 00:42:19.161438 Byte0 TX OE(2T, 0.5T) = (3, 3)
9073 00:42:19.161911 Byte1 TX OE(2T, 0.5T) = (3, 3)
9074 00:42:19.162283
9075 00:42:19.164951
9076 00:42:19.171659 [DQSOSCAuto] RK1, (LSB)MR18= 0x1c06, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 395 ps
9077 00:42:19.174771 CH1 RK1: MR19=303, MR18=1C06
9078 00:42:19.181462 CH1_RK1: MR19=0x303, MR18=0x1C06, DQSOSC=395, MR23=63, INC=23, DEC=15
9079 00:42:19.184496 [RxdqsGatingPostProcess] freq 1600
9080 00:42:19.187831 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9081 00:42:19.191669 best DQS0 dly(2T, 0.5T) = (1, 1)
9082 00:42:19.194763 best DQS1 dly(2T, 0.5T) = (1, 1)
9083 00:42:19.198515 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9084 00:42:19.201208 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9085 00:42:19.204943 best DQS0 dly(2T, 0.5T) = (1, 1)
9086 00:42:19.207997 best DQS1 dly(2T, 0.5T) = (1, 1)
9087 00:42:19.211503 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9088 00:42:19.215285 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9089 00:42:19.215866 Pre-setting of DQS Precalculation
9090 00:42:19.221271 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9091 00:42:19.228070 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9092 00:42:19.234359 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9093 00:42:19.234917
9094 00:42:19.235290
9095 00:42:19.237757 [Calibration Summary] 3200 Mbps
9096 00:42:19.241459 CH 0, Rank 0
9097 00:42:19.241939 SW Impedance : PASS
9098 00:42:19.244785 DUTY Scan : NO K
9099 00:42:19.247753 ZQ Calibration : PASS
9100 00:42:19.248224 Jitter Meter : NO K
9101 00:42:19.251388 CBT Training : PASS
9102 00:42:19.251862 Write leveling : PASS
9103 00:42:19.254415 RX DQS gating : PASS
9104 00:42:19.258354 RX DQ/DQS(RDDQC) : PASS
9105 00:42:19.258927 TX DQ/DQS : PASS
9106 00:42:19.261699 RX DATLAT : PASS
9107 00:42:19.264343 RX DQ/DQS(Engine): PASS
9108 00:42:19.264866 TX OE : PASS
9109 00:42:19.267780 All Pass.
9110 00:42:19.268349
9111 00:42:19.268791 CH 0, Rank 1
9112 00:42:19.271446 SW Impedance : PASS
9113 00:42:19.272013 DUTY Scan : NO K
9114 00:42:19.274531 ZQ Calibration : PASS
9115 00:42:19.277737 Jitter Meter : NO K
9116 00:42:19.278304 CBT Training : PASS
9117 00:42:19.281038 Write leveling : PASS
9118 00:42:19.284724 RX DQS gating : PASS
9119 00:42:19.285291 RX DQ/DQS(RDDQC) : PASS
9120 00:42:19.287898 TX DQ/DQS : PASS
9121 00:42:19.291128 RX DATLAT : PASS
9122 00:42:19.291599 RX DQ/DQS(Engine): PASS
9123 00:42:19.294640 TX OE : PASS
9124 00:42:19.295111 All Pass.
9125 00:42:19.295482
9126 00:42:19.298191 CH 1, Rank 0
9127 00:42:19.298762 SW Impedance : PASS
9128 00:42:19.300970 DUTY Scan : NO K
9129 00:42:19.304431 ZQ Calibration : PASS
9130 00:42:19.305113 Jitter Meter : NO K
9131 00:42:19.307754 CBT Training : PASS
9132 00:42:19.308324 Write leveling : PASS
9133 00:42:19.311368 RX DQS gating : PASS
9134 00:42:19.314453 RX DQ/DQS(RDDQC) : PASS
9135 00:42:19.315024 TX DQ/DQS : PASS
9136 00:42:19.317774 RX DATLAT : PASS
9137 00:42:19.320983 RX DQ/DQS(Engine): PASS
9138 00:42:19.321547 TX OE : PASS
9139 00:42:19.324419 All Pass.
9140 00:42:19.325031
9141 00:42:19.325405 CH 1, Rank 1
9142 00:42:19.327766 SW Impedance : PASS
9143 00:42:19.328339 DUTY Scan : NO K
9144 00:42:19.331106 ZQ Calibration : PASS
9145 00:42:19.334212 Jitter Meter : NO K
9146 00:42:19.334702 CBT Training : PASS
9147 00:42:19.337529 Write leveling : PASS
9148 00:42:19.341034 RX DQS gating : PASS
9149 00:42:19.341603 RX DQ/DQS(RDDQC) : PASS
9150 00:42:19.344155 TX DQ/DQS : PASS
9151 00:42:19.347755 RX DATLAT : PASS
9152 00:42:19.348222 RX DQ/DQS(Engine): PASS
9153 00:42:19.351070 TX OE : PASS
9154 00:42:19.351641 All Pass.
9155 00:42:19.352014
9156 00:42:19.354183 DramC Write-DBI on
9157 00:42:19.357237 PER_BANK_REFRESH: Hybrid Mode
9158 00:42:19.357708 TX_TRACKING: ON
9159 00:42:19.367256 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9160 00:42:19.374238 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9161 00:42:19.381121 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9162 00:42:19.384494 [FAST_K] Save calibration result to emmc
9163 00:42:19.387338 sync common calibartion params.
9164 00:42:19.390925 sync cbt_mode0:1, 1:1
9165 00:42:19.394172 dram_init: ddr_geometry: 2
9166 00:42:19.394874 dram_init: ddr_geometry: 2
9167 00:42:19.397332 dram_init: ddr_geometry: 2
9168 00:42:19.400732 0:dram_rank_size:100000000
9169 00:42:19.401310 1:dram_rank_size:100000000
9170 00:42:19.407314 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9171 00:42:19.410904 DFS_SHUFFLE_HW_MODE: ON
9172 00:42:19.414198 dramc_set_vcore_voltage set vcore to 725000
9173 00:42:19.417173 Read voltage for 1600, 0
9174 00:42:19.417746 Vio18 = 0
9175 00:42:19.418158 Vcore = 725000
9176 00:42:19.420771 Vdram = 0
9177 00:42:19.421335 Vddq = 0
9178 00:42:19.421704 Vmddr = 0
9179 00:42:19.424208 switch to 3200 Mbps bootup
9180 00:42:19.424816 [DramcRunTimeConfig]
9181 00:42:19.427121 PHYPLL
9182 00:42:19.427686 DPM_CONTROL_AFTERK: ON
9183 00:42:19.430570 PER_BANK_REFRESH: ON
9184 00:42:19.433943 REFRESH_OVERHEAD_REDUCTION: ON
9185 00:42:19.434512 CMD_PICG_NEW_MODE: OFF
9186 00:42:19.437324 XRTWTW_NEW_MODE: ON
9187 00:42:19.437792 XRTRTR_NEW_MODE: ON
9188 00:42:19.440646 TX_TRACKING: ON
9189 00:42:19.441213 RDSEL_TRACKING: OFF
9190 00:42:19.443524 DQS Precalculation for DVFS: ON
9191 00:42:19.446967 RX_TRACKING: OFF
9192 00:42:19.447436 HW_GATING DBG: ON
9193 00:42:19.450268 ZQCS_ENABLE_LP4: ON
9194 00:42:19.450769 RX_PICG_NEW_MODE: ON
9195 00:42:19.453967 TX_PICG_NEW_MODE: ON
9196 00:42:19.454593 ENABLE_RX_DCM_DPHY: ON
9197 00:42:19.457160 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9198 00:42:19.460481 DUMMY_READ_FOR_TRACKING: OFF
9199 00:42:19.463841 !!! SPM_CONTROL_AFTERK: OFF
9200 00:42:19.467331 !!! SPM could not control APHY
9201 00:42:19.467923 IMPEDANCE_TRACKING: ON
9202 00:42:19.470345 TEMP_SENSOR: ON
9203 00:42:19.470909 HW_SAVE_FOR_SR: OFF
9204 00:42:19.473815 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9205 00:42:19.477214 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9206 00:42:19.480652 Read ODT Tracking: ON
9207 00:42:19.484018 Refresh Rate DeBounce: ON
9208 00:42:19.484619 DFS_NO_QUEUE_FLUSH: ON
9209 00:42:19.487413 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9210 00:42:19.490895 ENABLE_DFS_RUNTIME_MRW: OFF
9211 00:42:19.494221 DDR_RESERVE_NEW_MODE: ON
9212 00:42:19.494791 MR_CBT_SWITCH_FREQ: ON
9213 00:42:19.497192 =========================
9214 00:42:19.515578 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9215 00:42:19.518923 dram_init: ddr_geometry: 2
9216 00:42:19.537408 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9217 00:42:19.540356 dram_init: dram init end (result: 0)
9218 00:42:19.547398 DRAM-K: Full calibration passed in 24499 msecs
9219 00:42:19.550743 MRC: failed to locate region type 0.
9220 00:42:19.551169 DRAM rank0 size:0x100000000,
9221 00:42:19.553993 DRAM rank1 size=0x100000000
9222 00:42:19.564089 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9223 00:42:19.570372 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9224 00:42:19.577278 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9225 00:42:19.584156 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9226 00:42:19.587073 DRAM rank0 size:0x100000000,
9227 00:42:19.590603 DRAM rank1 size=0x100000000
9228 00:42:19.591177 CBMEM:
9229 00:42:19.594044 IMD: root @ 0xfffff000 254 entries.
9230 00:42:19.596774 IMD: root @ 0xffffec00 62 entries.
9231 00:42:19.600481 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9232 00:42:19.603814 WARNING: RO_VPD is uninitialized or empty.
9233 00:42:19.610636 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9234 00:42:19.617839 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9235 00:42:19.630402 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9236 00:42:19.641367 BS: romstage times (exec / console): total (unknown) / 24009 ms
9237 00:42:19.641925
9238 00:42:19.642293
9239 00:42:19.651783 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9240 00:42:19.655092 ARM64: Exception handlers installed.
9241 00:42:19.658458 ARM64: Testing exception
9242 00:42:19.661682 ARM64: Done test exception
9243 00:42:19.662252 Enumerating buses...
9244 00:42:19.664655 Show all devs... Before device enumeration.
9245 00:42:19.668579 Root Device: enabled 1
9246 00:42:19.671627 CPU_CLUSTER: 0: enabled 1
9247 00:42:19.672198 CPU: 00: enabled 1
9248 00:42:19.674969 Compare with tree...
9249 00:42:19.675538 Root Device: enabled 1
9250 00:42:19.678348 CPU_CLUSTER: 0: enabled 1
9251 00:42:19.681549 CPU: 00: enabled 1
9252 00:42:19.682120 Root Device scanning...
9253 00:42:19.685122 scan_static_bus for Root Device
9254 00:42:19.687951 CPU_CLUSTER: 0 enabled
9255 00:42:19.691684 scan_static_bus for Root Device done
9256 00:42:19.695121 scan_bus: bus Root Device finished in 8 msecs
9257 00:42:19.695766 done
9258 00:42:19.701349 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9259 00:42:19.705065 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9260 00:42:19.711496 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9261 00:42:19.715203 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9262 00:42:19.718399 Allocating resources...
9263 00:42:19.718964 Reading resources...
9264 00:42:19.724879 Root Device read_resources bus 0 link: 0
9265 00:42:19.725453 DRAM rank0 size:0x100000000,
9266 00:42:19.728097 DRAM rank1 size=0x100000000
9267 00:42:19.731789 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9268 00:42:19.734752 CPU: 00 missing read_resources
9269 00:42:19.737964 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9270 00:42:19.744835 Root Device read_resources bus 0 link: 0 done
9271 00:42:19.745306 Done reading resources.
9272 00:42:19.751478 Show resources in subtree (Root Device)...After reading.
9273 00:42:19.754709 Root Device child on link 0 CPU_CLUSTER: 0
9274 00:42:19.758142 CPU_CLUSTER: 0 child on link 0 CPU: 00
9275 00:42:19.768232 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9276 00:42:19.769007 CPU: 00
9277 00:42:19.771524 Root Device assign_resources, bus 0 link: 0
9278 00:42:19.775000 CPU_CLUSTER: 0 missing set_resources
9279 00:42:19.777700 Root Device assign_resources, bus 0 link: 0 done
9280 00:42:19.781379 Done setting resources.
9281 00:42:19.788263 Show resources in subtree (Root Device)...After assigning values.
9282 00:42:19.791409 Root Device child on link 0 CPU_CLUSTER: 0
9283 00:42:19.794871 CPU_CLUSTER: 0 child on link 0 CPU: 00
9284 00:42:19.805181 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9285 00:42:19.805766 CPU: 00
9286 00:42:19.807759 Done allocating resources.
9287 00:42:19.811438 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9288 00:42:19.814700 Enabling resources...
9289 00:42:19.815173 done.
9290 00:42:19.821289 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9291 00:42:19.821869 Initializing devices...
9292 00:42:19.824822 Root Device init
9293 00:42:19.825403 init hardware done!
9294 00:42:19.828294 0x00000018: ctrlr->caps
9295 00:42:19.831428 52.000 MHz: ctrlr->f_max
9296 00:42:19.832014 0.400 MHz: ctrlr->f_min
9297 00:42:19.834515 0x40ff8080: ctrlr->voltages
9298 00:42:19.834996 sclk: 390625
9299 00:42:19.837791 Bus Width = 1
9300 00:42:19.838260 sclk: 390625
9301 00:42:19.838630 Bus Width = 1
9302 00:42:19.841122 Early init status = 3
9303 00:42:19.848040 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9304 00:42:19.851600 in-header: 03 fc 00 00 01 00 00 00
9305 00:42:19.854291 in-data: 00
9306 00:42:19.857830 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9307 00:42:19.863047 in-header: 03 fd 00 00 00 00 00 00
9308 00:42:19.865924 in-data:
9309 00:42:19.869319 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9310 00:42:19.873330 in-header: 03 fc 00 00 01 00 00 00
9311 00:42:19.876921 in-data: 00
9312 00:42:19.880088 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9313 00:42:19.885907 in-header: 03 fd 00 00 00 00 00 00
9314 00:42:19.889050 in-data:
9315 00:42:19.893120 [SSUSB] Setting up USB HOST controller...
9316 00:42:19.896261 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9317 00:42:19.899015 [SSUSB] phy power-on done.
9318 00:42:19.902562 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9319 00:42:19.909464 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9320 00:42:19.912528 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9321 00:42:19.918892 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9322 00:42:19.925707 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9323 00:42:19.932397 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9324 00:42:19.938768 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9325 00:42:19.945534 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9326 00:42:19.948700 SPM: binary array size = 0x9dc
9327 00:42:19.952383 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9328 00:42:19.959002 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9329 00:42:19.965422 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9330 00:42:19.972235 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9331 00:42:19.975255 configure_display: Starting display init
9332 00:42:20.009683 anx7625_power_on_init: Init interface.
9333 00:42:20.012641 anx7625_disable_pd_protocol: Disabled PD feature.
9334 00:42:20.015927 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9335 00:42:20.044106 anx7625_start_dp_work: Secure OCM version=00
9336 00:42:20.046916 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9337 00:42:20.061498 sp_tx_get_edid_block: EDID Block = 1
9338 00:42:20.164692 Extracted contents:
9339 00:42:20.167910 header: 00 ff ff ff ff ff ff 00
9340 00:42:20.171406 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9341 00:42:20.174541 version: 01 04
9342 00:42:20.177436 basic params: 95 1f 11 78 0a
9343 00:42:20.181096 chroma info: 76 90 94 55 54 90 27 21 50 54
9344 00:42:20.184134 established: 00 00 00
9345 00:42:20.190716 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9346 00:42:20.194194 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9347 00:42:20.201078 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9348 00:42:20.207805 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9349 00:42:20.214539 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9350 00:42:20.217436 extensions: 00
9351 00:42:20.218004 checksum: fb
9352 00:42:20.218376
9353 00:42:20.220655 Manufacturer: IVO Model 57d Serial Number 0
9354 00:42:20.224145 Made week 0 of 2020
9355 00:42:20.224751 EDID version: 1.4
9356 00:42:20.227559 Digital display
9357 00:42:20.230725 6 bits per primary color channel
9358 00:42:20.231205 DisplayPort interface
9359 00:42:20.233917 Maximum image size: 31 cm x 17 cm
9360 00:42:20.237327 Gamma: 220%
9361 00:42:20.237808 Check DPMS levels
9362 00:42:20.240165 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9363 00:42:20.243852 First detailed timing is preferred timing
9364 00:42:20.247211 Established timings supported:
9365 00:42:20.250797 Standard timings supported:
9366 00:42:20.250970 Detailed timings
9367 00:42:20.256870 Hex of detail: 383680a07038204018303c0035ae10000019
9368 00:42:20.260433 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9369 00:42:20.267052 0780 0798 07c8 0820 hborder 0
9370 00:42:20.270473 0438 043b 0447 0458 vborder 0
9371 00:42:20.270689 -hsync -vsync
9372 00:42:20.273788 Did detailed timing
9373 00:42:20.277189 Hex of detail: 000000000000000000000000000000000000
9374 00:42:20.280382 Manufacturer-specified data, tag 0
9375 00:42:20.286940 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9376 00:42:20.287169 ASCII string: InfoVision
9377 00:42:20.293742 Hex of detail: 000000fe00523134304e574635205248200a
9378 00:42:20.294012 ASCII string: R140NWF5 RH
9379 00:42:20.297263 Checksum
9380 00:42:20.297558 Checksum: 0xfb (valid)
9381 00:42:20.304229 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9382 00:42:20.306988 DSI data_rate: 832800000 bps
9383 00:42:20.310511 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9384 00:42:20.314132 anx7625_parse_edid: pixelclock(138800).
9385 00:42:20.320545 hactive(1920), hsync(48), hfp(24), hbp(88)
9386 00:42:20.323876 vactive(1080), vsync(12), vfp(3), vbp(17)
9387 00:42:20.327427 anx7625_dsi_config: config dsi.
9388 00:42:20.333562 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9389 00:42:20.346229 anx7625_dsi_config: success to config DSI
9390 00:42:20.349711 anx7625_dp_start: MIPI phy setup OK.
9391 00:42:20.353144 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9392 00:42:20.356303 mtk_ddp_mode_set invalid vrefresh 60
9393 00:42:20.359774 main_disp_path_setup
9394 00:42:20.360328 ovl_layer_smi_id_en
9395 00:42:20.363085 ovl_layer_smi_id_en
9396 00:42:20.363638 ccorr_config
9397 00:42:20.363999 aal_config
9398 00:42:20.366279 gamma_config
9399 00:42:20.366742 postmask_config
9400 00:42:20.369939 dither_config
9401 00:42:20.372935 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9402 00:42:20.380005 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9403 00:42:20.383144 Root Device init finished in 555 msecs
9404 00:42:20.383704 CPU_CLUSTER: 0 init
9405 00:42:20.392971 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9406 00:42:20.396495 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9407 00:42:20.399498 APU_MBOX 0x190000b0 = 0x10001
9408 00:42:20.403029 APU_MBOX 0x190001b0 = 0x10001
9409 00:42:20.406138 APU_MBOX 0x190005b0 = 0x10001
9410 00:42:20.409765 APU_MBOX 0x190006b0 = 0x10001
9411 00:42:20.412607 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9412 00:42:20.425491 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9413 00:42:20.437740 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9414 00:42:20.444542 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9415 00:42:20.455921 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9416 00:42:20.465096 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9417 00:42:20.468525 CPU_CLUSTER: 0 init finished in 81 msecs
9418 00:42:20.471684 Devices initialized
9419 00:42:20.475337 Show all devs... After init.
9420 00:42:20.475910 Root Device: enabled 1
9421 00:42:20.478618 CPU_CLUSTER: 0: enabled 1
9422 00:42:20.481916 CPU: 00: enabled 1
9423 00:42:20.485211 BS: BS_DEV_INIT run times (exec / console): 214 / 447 ms
9424 00:42:20.488199 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9425 00:42:20.491728 ELOG: NV offset 0x57f000 size 0x1000
9426 00:42:20.498843 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9427 00:42:20.505151 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9428 00:42:20.508050 ELOG: Event(17) added with size 13 at 2024-06-16 00:40:55 UTC
9429 00:42:20.511731 out: cmd=0x121: 03 db 21 01 00 00 00 00
9430 00:42:20.515723 in-header: 03 5a 00 00 2c 00 00 00
9431 00:42:20.529017 in-data: e5 70 00 00 00 00 00 00 0a 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9432 00:42:20.535247 ELOG: Event(A1) added with size 10 at 2024-06-16 00:40:55 UTC
9433 00:42:20.542279 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
9434 00:42:20.548571 ELOG: Event(A0) added with size 9 at 2024-06-16 00:40:55 UTC
9435 00:42:20.552101 elog_add_boot_reason: Logged dev mode boot
9436 00:42:20.555504 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9437 00:42:20.558820 Finalize devices...
9438 00:42:20.559319 Devices finalized
9439 00:42:20.565013 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9440 00:42:20.568270 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
9441 00:42:20.571739 in-header: 03 07 00 00 08 00 00 00
9442 00:42:20.575248 in-data: aa e4 47 04 13 02 00 00
9443 00:42:20.578476 Chrome EC: UHEPI supported
9444 00:42:20.585182 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
9445 00:42:20.588638 in-header: 03 a9 00 00 08 00 00 00
9446 00:42:20.591620 in-data: 84 60 60 08 00 00 00 00
9447 00:42:20.595346 ELOG: Event(91) added with size 10 at 2024-06-16 00:40:55 UTC
9448 00:42:20.601938 Chrome EC: clear events_b mask to 0x0000000020004000
9449 00:42:20.608413 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
9450 00:42:20.611737 in-header: 03 fd 00 00 00 00 00 00
9451 00:42:20.612176 in-data:
9452 00:42:20.618741 BS: BS_WRITE_TABLES entry times (exec / console): 2 / 46 ms
9453 00:42:20.621898 Writing coreboot table at 0xffe64000
9454 00:42:20.625201 0. 000000000010a000-0000000000113fff: RAMSTAGE
9455 00:42:20.628602 1. 0000000040000000-00000000400fffff: RAM
9456 00:42:20.632182 2. 0000000040100000-000000004032afff: RAMSTAGE
9457 00:42:20.638244 3. 000000004032b000-00000000545fffff: RAM
9458 00:42:20.641560 4. 0000000054600000-000000005465ffff: BL31
9459 00:42:20.644999 5. 0000000054660000-00000000ffe63fff: RAM
9460 00:42:20.648754 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9461 00:42:20.655776 7. 0000000100000000-000000023fffffff: RAM
9462 00:42:20.656361 Passing 5 GPIOs to payload:
9463 00:42:20.662077 NAME | PORT | POLARITY | VALUE
9464 00:42:20.665052 EC in RW | 0x000000aa | low | undefined
9465 00:42:20.668385 EC interrupt | 0x00000005 | low | undefined
9466 00:42:20.675498 TPM interrupt | 0x000000ab | high | undefined
9467 00:42:20.678426 SD card detect | 0x00000011 | high | undefined
9468 00:42:20.685044 speaker enable | 0x00000093 | high | undefined
9469 00:42:20.688191 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9470 00:42:20.692015 in-header: 03 f9 00 00 02 00 00 00
9471 00:42:20.692632 in-data: 02 00
9472 00:42:20.695502 ADC[4]: Raw value=900295 ID=7
9473 00:42:20.698357 ADC[3]: Raw value=213179 ID=1
9474 00:42:20.698938 RAM Code: 0x71
9475 00:42:20.701611 ADC[6]: Raw value=74502 ID=0
9476 00:42:20.705238 ADC[5]: Raw value=212072 ID=1
9477 00:42:20.705822 SKU Code: 0x1
9478 00:42:20.711697 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 34dc
9479 00:42:20.714911 coreboot table: 964 bytes.
9480 00:42:20.718024 IMD ROOT 0. 0xfffff000 0x00001000
9481 00:42:20.721395 IMD SMALL 1. 0xffffe000 0x00001000
9482 00:42:20.725105 RO MCACHE 2. 0xffffc000 0x00001104
9483 00:42:20.728420 CONSOLE 3. 0xfff7c000 0x00080000
9484 00:42:20.731510 FMAP 4. 0xfff7b000 0x00000452
9485 00:42:20.734755 TIME STAMP 5. 0xfff7a000 0x00000910
9486 00:42:20.738128 VBOOT WORK 6. 0xfff66000 0x00014000
9487 00:42:20.741568 RAMOOPS 7. 0xffe66000 0x00100000
9488 00:42:20.744988 COREBOOT 8. 0xffe64000 0x00002000
9489 00:42:20.745461 IMD small region:
9490 00:42:20.748286 IMD ROOT 0. 0xffffec00 0x00000400
9491 00:42:20.751302 VPD 1. 0xffffeb80 0x0000006c
9492 00:42:20.754957 MMC STATUS 2. 0xffffeb60 0x00000004
9493 00:42:20.761462 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9494 00:42:20.767623 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9495 00:42:20.806971 read SPI 0x3990ec 0x4f1b0: 34845 us, 9298 KB/s, 74.384 Mbps
9496 00:42:20.810230 Checking segment from ROM address 0x40100000
9497 00:42:20.813967 Checking segment from ROM address 0x4010001c
9498 00:42:20.820349 Loading segment from ROM address 0x40100000
9499 00:42:20.820886 code (compression=0)
9500 00:42:20.830182 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9501 00:42:20.836628 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9502 00:42:20.837299 it's not compressed!
9503 00:42:20.843468 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9504 00:42:20.850245 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9505 00:42:20.867723 Loading segment from ROM address 0x4010001c
9506 00:42:20.868189 Entry Point 0x80000000
9507 00:42:20.870995 Loaded segments
9508 00:42:20.874252 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9509 00:42:20.880676 Jumping to boot code at 0x80000000(0xffe64000)
9510 00:42:20.887155 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9511 00:42:20.893816 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9512 00:42:20.901993 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9513 00:42:20.905120 Checking segment from ROM address 0x40100000
9514 00:42:20.908797 Checking segment from ROM address 0x4010001c
9515 00:42:20.915127 Loading segment from ROM address 0x40100000
9516 00:42:20.915557 code (compression=1)
9517 00:42:20.922013 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9518 00:42:20.931867 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9519 00:42:20.932424 using LZMA
9520 00:42:20.940484 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9521 00:42:20.946921 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9522 00:42:20.950186 Loading segment from ROM address 0x4010001c
9523 00:42:20.950659 Entry Point 0x54601000
9524 00:42:20.953652 Loaded segments
9525 00:42:20.957292 NOTICE: MT8192 bl31_setup
9526 00:42:20.964160 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9527 00:42:20.967549 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9528 00:42:20.970837 WARNING: region 0:
9529 00:42:20.973900 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9530 00:42:20.974440 WARNING: region 1:
9531 00:42:20.980320 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9532 00:42:20.984217 WARNING: region 2:
9533 00:42:20.987540 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9534 00:42:20.990320 WARNING: region 3:
9535 00:42:20.993765 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9536 00:42:20.997422 WARNING: region 4:
9537 00:42:21.004231 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9538 00:42:21.004852 WARNING: region 5:
9539 00:42:21.007124 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9540 00:42:21.010218 WARNING: region 6:
9541 00:42:21.013765 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9542 00:42:21.017357 WARNING: region 7:
9543 00:42:21.020321 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9544 00:42:21.026856 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9545 00:42:21.030261 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9546 00:42:21.033789 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9547 00:42:21.040719 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9548 00:42:21.043834 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9549 00:42:21.047014 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9550 00:42:21.053644 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9551 00:42:21.057346 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9552 00:42:21.063851 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9553 00:42:21.066826 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9554 00:42:21.070224 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9555 00:42:21.076650 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9556 00:42:21.080484 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9557 00:42:21.084023 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9558 00:42:21.090466 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9559 00:42:21.093446 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9560 00:42:21.100475 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9561 00:42:21.103614 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9562 00:42:21.107251 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9563 00:42:21.113231 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9564 00:42:21.116776 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9565 00:42:21.120173 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9566 00:42:21.126737 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9567 00:42:21.130111 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9568 00:42:21.137214 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9569 00:42:21.140680 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9570 00:42:21.146933 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9571 00:42:21.150392 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9572 00:42:21.153478 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9573 00:42:21.160587 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9574 00:42:21.163698 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9575 00:42:21.166816 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9576 00:42:21.173635 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9577 00:42:21.176818 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9578 00:42:21.180305 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9579 00:42:21.183635 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9580 00:42:21.190038 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9581 00:42:21.193319 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9582 00:42:21.196724 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9583 00:42:21.200105 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9584 00:42:21.207003 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9585 00:42:21.209804 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9586 00:42:21.213383 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9587 00:42:21.216717 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9588 00:42:21.223272 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9589 00:42:21.226696 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9590 00:42:21.230136 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9591 00:42:21.233416 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9592 00:42:21.239713 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9593 00:42:21.243191 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9594 00:42:21.250256 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9595 00:42:21.253296 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9596 00:42:21.260072 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9597 00:42:21.263642 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9598 00:42:21.266848 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9599 00:42:21.273284 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9600 00:42:21.276691 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9601 00:42:21.283637 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9602 00:42:21.286751 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9603 00:42:21.293513 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9604 00:42:21.297152 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9605 00:42:21.300501 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9606 00:42:21.307046 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9607 00:42:21.310464 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9608 00:42:21.316864 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9609 00:42:21.320237 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9610 00:42:21.326385 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9611 00:42:21.329875 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9612 00:42:21.336667 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9613 00:42:21.340005 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9614 00:42:21.343238 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9615 00:42:21.349612 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9616 00:42:21.353066 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9617 00:42:21.359544 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9618 00:42:21.362958 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9619 00:42:21.369567 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9620 00:42:21.373018 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9621 00:42:21.376669 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9622 00:42:21.383188 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9623 00:42:21.386489 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9624 00:42:21.392678 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9625 00:42:21.396220 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9626 00:42:21.402742 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9627 00:42:21.406148 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9628 00:42:21.410003 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9629 00:42:21.416060 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9630 00:42:21.419427 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9631 00:42:21.426201 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9632 00:42:21.429506 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9633 00:42:21.436352 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9634 00:42:21.439213 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9635 00:42:21.445899 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9636 00:42:21.449388 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9637 00:42:21.452675 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9638 00:42:21.459483 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9639 00:42:21.462873 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9640 00:42:21.469236 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9641 00:42:21.472572 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9642 00:42:21.475994 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9643 00:42:21.479439 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9644 00:42:21.485963 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9645 00:42:21.489545 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9646 00:42:21.492763 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9647 00:42:21.499427 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9648 00:42:21.502750 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9649 00:42:21.509272 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9650 00:42:21.512708 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9651 00:42:21.516065 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9652 00:42:21.522462 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9653 00:42:21.525956 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9654 00:42:21.532305 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9655 00:42:21.535696 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9656 00:42:21.539168 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9657 00:42:21.545508 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9658 00:42:21.549193 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9659 00:42:21.552523 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9660 00:42:21.558840 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9661 00:42:21.562345 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9662 00:42:21.565572 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9663 00:42:21.572324 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9664 00:42:21.575577 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9665 00:42:21.578668 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9666 00:42:21.582276 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9667 00:42:21.589025 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9668 00:42:21.592269 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9669 00:42:21.595570 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9670 00:42:21.602059 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9671 00:42:21.605334 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9672 00:42:21.612241 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9673 00:42:21.615206 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9674 00:42:21.618656 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9675 00:42:21.625413 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9676 00:42:21.628470 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9677 00:42:21.635867 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9678 00:42:21.638792 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9679 00:42:21.642122 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9680 00:42:21.649226 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9681 00:42:21.652452 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9682 00:42:21.659062 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9683 00:42:21.661947 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9684 00:42:21.665447 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9685 00:42:21.671957 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9686 00:42:21.675076 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9687 00:42:21.682036 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9688 00:42:21.685005 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9689 00:42:21.688326 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9690 00:42:21.695195 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9691 00:42:21.698632 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9692 00:42:21.701934 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9693 00:42:21.708560 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9694 00:42:21.711834 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9695 00:42:21.719157 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9696 00:42:21.722004 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9697 00:42:21.725633 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9698 00:42:21.732044 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9699 00:42:21.735420 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9700 00:42:21.738523 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9701 00:42:21.745531 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9702 00:42:21.748437 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9703 00:42:21.755561 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9704 00:42:21.758519 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9705 00:42:21.762198 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9706 00:42:21.769194 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9707 00:42:21.772719 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9708 00:42:21.779269 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9709 00:42:21.782405 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9710 00:42:21.785879 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9711 00:42:21.792614 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9712 00:42:21.796261 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9713 00:42:21.799345 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9714 00:42:21.806240 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9715 00:42:21.809225 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9716 00:42:21.815726 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9717 00:42:21.819120 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9718 00:42:21.822590 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9719 00:42:21.829387 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9720 00:42:21.832675 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9721 00:42:21.838672 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9722 00:42:21.842610 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9723 00:42:21.845539 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9724 00:42:21.852152 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9725 00:42:21.855385 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9726 00:42:21.861946 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9727 00:42:21.865329 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9728 00:42:21.868254 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9729 00:42:21.875513 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9730 00:42:21.878519 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9731 00:42:21.885318 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9732 00:42:21.888516 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9733 00:42:21.891786 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9734 00:42:21.898560 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9735 00:42:21.901638 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9736 00:42:21.908609 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9737 00:42:21.912134 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9738 00:42:21.915383 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9739 00:42:21.921561 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9740 00:42:21.924983 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9741 00:42:21.931631 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9742 00:42:21.934889 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9743 00:42:21.941484 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9744 00:42:21.944770 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9745 00:42:21.947943 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9746 00:42:21.954820 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9747 00:42:21.957782 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9748 00:42:21.964679 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9749 00:42:21.967969 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9750 00:42:21.974603 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9751 00:42:21.978032 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9752 00:42:21.981490 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9753 00:42:21.987686 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9754 00:42:21.990852 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9755 00:42:21.997880 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9756 00:42:22.000824 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9757 00:42:22.007568 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9758 00:42:22.010834 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9759 00:42:22.014383 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9760 00:42:22.020603 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9761 00:42:22.024371 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9762 00:42:22.030826 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9763 00:42:22.034278 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9764 00:42:22.040808 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9765 00:42:22.044164 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9766 00:42:22.047059 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9767 00:42:22.054014 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9768 00:42:22.057237 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9769 00:42:22.063751 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9770 00:42:22.067515 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9771 00:42:22.070925 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9772 00:42:22.077554 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9773 00:42:22.081240 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9774 00:42:22.083911 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9775 00:42:22.087328 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9776 00:42:22.093804 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9777 00:42:22.097320 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9778 00:42:22.100425 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9779 00:42:22.107142 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9780 00:42:22.110510 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9781 00:42:22.113698 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9782 00:42:22.120693 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9783 00:42:22.124079 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9784 00:42:22.127065 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9785 00:42:22.134018 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9786 00:42:22.137377 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9787 00:42:22.140466 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9788 00:42:22.146806 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9789 00:42:22.150358 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9790 00:42:22.157472 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9791 00:42:22.160532 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9792 00:42:22.164278 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9793 00:42:22.170555 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9794 00:42:22.173998 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9795 00:42:22.177290 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9796 00:42:22.183930 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9797 00:42:22.187145 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9798 00:42:22.190751 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9799 00:42:22.197295 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9800 00:42:22.200603 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9801 00:42:22.207119 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9802 00:42:22.210190 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9803 00:42:22.213922 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9804 00:42:22.220653 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9805 00:42:22.223718 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9806 00:42:22.227317 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9807 00:42:22.234286 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9808 00:42:22.237150 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9809 00:42:22.240618 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9810 00:42:22.247165 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9811 00:42:22.250713 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9812 00:42:22.253548 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9813 00:42:22.260250 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9814 00:42:22.263627 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9815 00:42:22.267090 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9816 00:42:22.270455 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9817 00:42:22.273837 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9818 00:42:22.280490 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9819 00:42:22.283471 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9820 00:42:22.286845 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9821 00:42:22.293796 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9822 00:42:22.296950 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9823 00:42:22.300226 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9824 00:42:22.303384 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9825 00:42:22.310225 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9826 00:42:22.313441 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9827 00:42:22.320177 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9828 00:42:22.323589 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9829 00:42:22.327121 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9830 00:42:22.333831 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9831 00:42:22.337276 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9832 00:42:22.343759 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9833 00:42:22.347059 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9834 00:42:22.350179 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9835 00:42:22.357324 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9836 00:42:22.360009 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9837 00:42:22.366946 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9838 00:42:22.370345 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9839 00:42:22.373694 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9840 00:42:22.380235 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9841 00:42:22.383571 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9842 00:42:22.390043 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9843 00:42:22.393550 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9844 00:42:22.397080 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9845 00:42:22.403647 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9846 00:42:22.406985 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9847 00:42:22.413585 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9848 00:42:22.416772 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9849 00:42:22.420224 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9850 00:42:22.426677 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9851 00:42:22.430395 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9852 00:42:22.436844 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9853 00:42:22.440223 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9854 00:42:22.443820 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9855 00:42:22.450334 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9856 00:42:22.453115 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9857 00:42:22.460074 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9858 00:42:22.463570 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9859 00:42:22.466705 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9860 00:42:22.473662 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9861 00:42:22.476877 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9862 00:42:22.483719 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9863 00:42:22.486826 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9864 00:42:22.493181 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9865 00:42:22.496599 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9866 00:42:22.500090 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9867 00:42:22.506996 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9868 00:42:22.510307 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9869 00:42:22.516370 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9870 00:42:22.519711 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9871 00:42:22.523544 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9872 00:42:22.530060 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9873 00:42:22.533499 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9874 00:42:22.539640 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9875 00:42:22.543577 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9876 00:42:22.546234 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9877 00:42:22.553195 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9878 00:42:22.556343 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9879 00:42:22.563194 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9880 00:42:22.566593 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9881 00:42:22.570106 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9882 00:42:22.576588 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9883 00:42:22.580282 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9884 00:42:22.586566 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9885 00:42:22.589939 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9886 00:42:22.593430 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9887 00:42:22.599674 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9888 00:42:22.603206 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9889 00:42:22.609856 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9890 00:42:22.613364 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9891 00:42:22.616126 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9892 00:42:22.622694 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9893 00:42:22.626170 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9894 00:42:22.632882 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9895 00:42:22.636090 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9896 00:42:22.642726 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9897 00:42:22.646099 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9898 00:42:22.649596 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9899 00:42:22.656283 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9900 00:42:22.659184 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9901 00:42:22.666184 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9902 00:42:22.669549 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9903 00:42:22.676367 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9904 00:42:22.679778 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9905 00:42:22.682869 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9906 00:42:22.689555 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9907 00:42:22.692989 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9908 00:42:22.700122 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9909 00:42:22.703031 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9910 00:42:22.706063 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9911 00:42:22.712916 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9912 00:42:22.716642 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9913 00:42:22.722721 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9914 00:42:22.726440 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9915 00:42:22.732806 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9916 00:42:22.736085 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9917 00:42:22.739855 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9918 00:42:22.746010 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9919 00:42:22.749262 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9920 00:42:22.756226 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9921 00:42:22.759456 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9922 00:42:22.766486 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9923 00:42:22.769749 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9924 00:42:22.772781 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9925 00:42:22.779553 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9926 00:42:22.783120 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9927 00:42:22.789460 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9928 00:42:22.792836 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9929 00:42:22.800023 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9930 00:42:22.802958 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9931 00:42:22.806376 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9932 00:42:22.813414 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9933 00:42:22.815890 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9934 00:42:22.822785 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9935 00:42:22.826296 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9936 00:42:22.833104 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9937 00:42:22.836446 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9938 00:42:22.839710 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9939 00:42:22.846008 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9940 00:42:22.849710 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9941 00:42:22.856716 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9942 00:42:22.859607 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9943 00:42:22.866581 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9944 00:42:22.869336 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9945 00:42:22.872824 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9946 00:42:22.879507 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9947 00:42:22.882966 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9948 00:42:22.889763 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9949 00:42:22.892721 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9950 00:42:22.899560 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9951 00:42:22.902955 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9952 00:42:22.909365 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9953 00:42:22.912883 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9954 00:42:22.916381 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9955 00:42:22.922721 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9956 00:42:22.926080 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9957 00:42:22.932783 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9958 00:42:22.936418 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9959 00:42:22.942758 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9960 00:42:22.946179 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9961 00:42:22.952850 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9962 00:42:22.956597 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9963 00:42:22.962671 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9964 00:42:22.966238 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9965 00:42:22.972789 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9966 00:42:22.976178 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9967 00:42:22.982545 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9968 00:42:22.985918 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9969 00:42:22.992767 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9970 00:42:22.995938 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9971 00:42:23.002392 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9972 00:42:23.005761 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9973 00:42:23.012402 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9974 00:42:23.015822 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9975 00:42:23.022217 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9976 00:42:23.025575 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9977 00:42:23.032392 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9978 00:42:23.035894 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9979 00:42:23.039500 INFO: [APUAPC] vio 0
9980 00:42:23.042294 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9981 00:42:23.049363 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9982 00:42:23.052688 INFO: [APUAPC] D0_APC_0: 0x400510
9983 00:42:23.053370 INFO: [APUAPC] D0_APC_1: 0x0
9984 00:42:23.055732 INFO: [APUAPC] D0_APC_2: 0x1540
9985 00:42:23.059081 INFO: [APUAPC] D0_APC_3: 0x0
9986 00:42:23.062121 INFO: [APUAPC] D1_APC_0: 0xffffffff
9987 00:42:23.065478 INFO: [APUAPC] D1_APC_1: 0xffffffff
9988 00:42:23.068891 INFO: [APUAPC] D1_APC_2: 0x3fffff
9989 00:42:23.072465 INFO: [APUAPC] D1_APC_3: 0x0
9990 00:42:23.076090 INFO: [APUAPC] D2_APC_0: 0xffffffff
9991 00:42:23.079062 INFO: [APUAPC] D2_APC_1: 0xffffffff
9992 00:42:23.082725 INFO: [APUAPC] D2_APC_2: 0x3fffff
9993 00:42:23.085784 INFO: [APUAPC] D2_APC_3: 0x0
9994 00:42:23.089100 INFO: [APUAPC] D3_APC_0: 0xffffffff
9995 00:42:23.092775 INFO: [APUAPC] D3_APC_1: 0xffffffff
9996 00:42:23.095886 INFO: [APUAPC] D3_APC_2: 0x3fffff
9997 00:42:23.099448 INFO: [APUAPC] D3_APC_3: 0x0
9998 00:42:23.102484 INFO: [APUAPC] D4_APC_0: 0xffffffff
9999 00:42:23.105876 INFO: [APUAPC] D4_APC_1: 0xffffffff
10000 00:42:23.109507 INFO: [APUAPC] D4_APC_2: 0x3fffff
10001 00:42:23.112751 INFO: [APUAPC] D4_APC_3: 0x0
10002 00:42:23.115764 INFO: [APUAPC] D5_APC_0: 0xffffffff
10003 00:42:23.118952 INFO: [APUAPC] D5_APC_1: 0xffffffff
10004 00:42:23.122262 INFO: [APUAPC] D5_APC_2: 0x3fffff
10005 00:42:23.125968 INFO: [APUAPC] D5_APC_3: 0x0
10006 00:42:23.129238 INFO: [APUAPC] D6_APC_0: 0xffffffff
10007 00:42:23.132721 INFO: [APUAPC] D6_APC_1: 0xffffffff
10008 00:42:23.136049 INFO: [APUAPC] D6_APC_2: 0x3fffff
10009 00:42:23.138767 INFO: [APUAPC] D6_APC_3: 0x0
10010 00:42:23.142202 INFO: [APUAPC] D7_APC_0: 0xffffffff
10011 00:42:23.145787 INFO: [APUAPC] D7_APC_1: 0xffffffff
10012 00:42:23.149284 INFO: [APUAPC] D7_APC_2: 0x3fffff
10013 00:42:23.149903 INFO: [APUAPC] D7_APC_3: 0x0
10014 00:42:23.156190 INFO: [APUAPC] D8_APC_0: 0xffffffff
10015 00:42:23.159278 INFO: [APUAPC] D8_APC_1: 0xffffffff
10016 00:42:23.162084 INFO: [APUAPC] D8_APC_2: 0x3fffff
10017 00:42:23.162676 INFO: [APUAPC] D8_APC_3: 0x0
10018 00:42:23.165812 INFO: [APUAPC] D9_APC_0: 0xffffffff
10019 00:42:23.168855 INFO: [APUAPC] D9_APC_1: 0xffffffff
10020 00:42:23.172632 INFO: [APUAPC] D9_APC_2: 0x3fffff
10021 00:42:23.176019 INFO: [APUAPC] D9_APC_3: 0x0
10022 00:42:23.179179 INFO: [APUAPC] D10_APC_0: 0xffffffff
10023 00:42:23.182073 INFO: [APUAPC] D10_APC_1: 0xffffffff
10024 00:42:23.185531 INFO: [APUAPC] D10_APC_2: 0x3fffff
10025 00:42:23.189316 INFO: [APUAPC] D10_APC_3: 0x0
10026 00:42:23.192647 INFO: [APUAPC] D11_APC_0: 0xffffffff
10027 00:42:23.195849 INFO: [APUAPC] D11_APC_1: 0xffffffff
10028 00:42:23.199019 INFO: [APUAPC] D11_APC_2: 0x3fffff
10029 00:42:23.202241 INFO: [APUAPC] D11_APC_3: 0x0
10030 00:42:23.205718 INFO: [APUAPC] D12_APC_0: 0xffffffff
10031 00:42:23.209179 INFO: [APUAPC] D12_APC_1: 0xffffffff
10032 00:42:23.212587 INFO: [APUAPC] D12_APC_2: 0x3fffff
10033 00:42:23.215582 INFO: [APUAPC] D12_APC_3: 0x0
10034 00:42:23.218983 INFO: [APUAPC] D13_APC_0: 0xffffffff
10035 00:42:23.221923 INFO: [APUAPC] D13_APC_1: 0xffffffff
10036 00:42:23.225385 INFO: [APUAPC] D13_APC_2: 0x3fffff
10037 00:42:23.229186 INFO: [APUAPC] D13_APC_3: 0x0
10038 00:42:23.232171 INFO: [APUAPC] D14_APC_0: 0xffffffff
10039 00:42:23.235242 INFO: [APUAPC] D14_APC_1: 0xffffffff
10040 00:42:23.242368 INFO: [APUAPC] D14_APC_2: 0x3fffff
10041 00:42:23.242950 INFO: [APUAPC] D14_APC_3: 0x0
10042 00:42:23.245761 INFO: [APUAPC] D15_APC_0: 0xffffffff
10043 00:42:23.249407 INFO: [APUAPC] D15_APC_1: 0xffffffff
10044 00:42:23.252187 INFO: [APUAPC] D15_APC_2: 0x3fffff
10045 00:42:23.255576 INFO: [APUAPC] D15_APC_3: 0x0
10046 00:42:23.259048 INFO: [APUAPC] APC_CON: 0x4
10047 00:42:23.262313 INFO: [NOCDAPC] D0_APC_0: 0x0
10048 00:42:23.265341 INFO: [NOCDAPC] D0_APC_1: 0x0
10049 00:42:23.268722 INFO: [NOCDAPC] D1_APC_0: 0x0
10050 00:42:23.271955 INFO: [NOCDAPC] D1_APC_1: 0xfff
10051 00:42:23.275460 INFO: [NOCDAPC] D2_APC_0: 0x0
10052 00:42:23.278863 INFO: [NOCDAPC] D2_APC_1: 0xfff
10053 00:42:23.279447 INFO: [NOCDAPC] D3_APC_0: 0x0
10054 00:42:23.282384 INFO: [NOCDAPC] D3_APC_1: 0xfff
10055 00:42:23.285745 INFO: [NOCDAPC] D4_APC_0: 0x0
10056 00:42:23.288962 INFO: [NOCDAPC] D4_APC_1: 0xfff
10057 00:42:23.292378 INFO: [NOCDAPC] D5_APC_0: 0x0
10058 00:42:23.295632 INFO: [NOCDAPC] D5_APC_1: 0xfff
10059 00:42:23.299002 INFO: [NOCDAPC] D6_APC_0: 0x0
10060 00:42:23.302345 INFO: [NOCDAPC] D6_APC_1: 0xfff
10061 00:42:23.305746 INFO: [NOCDAPC] D7_APC_0: 0x0
10062 00:42:23.309214 INFO: [NOCDAPC] D7_APC_1: 0xfff
10063 00:42:23.312256 INFO: [NOCDAPC] D8_APC_0: 0x0
10064 00:42:23.312878 INFO: [NOCDAPC] D8_APC_1: 0xfff
10065 00:42:23.315830 INFO: [NOCDAPC] D9_APC_0: 0x0
10066 00:42:23.318953 INFO: [NOCDAPC] D9_APC_1: 0xfff
10067 00:42:23.322160 INFO: [NOCDAPC] D10_APC_0: 0x0
10068 00:42:23.325377 INFO: [NOCDAPC] D10_APC_1: 0xfff
10069 00:42:23.328849 INFO: [NOCDAPC] D11_APC_0: 0x0
10070 00:42:23.332197 INFO: [NOCDAPC] D11_APC_1: 0xfff
10071 00:42:23.335436 INFO: [NOCDAPC] D12_APC_0: 0x0
10072 00:42:23.338908 INFO: [NOCDAPC] D12_APC_1: 0xfff
10073 00:42:23.341877 INFO: [NOCDAPC] D13_APC_0: 0x0
10074 00:42:23.345407 INFO: [NOCDAPC] D13_APC_1: 0xfff
10075 00:42:23.348976 INFO: [NOCDAPC] D14_APC_0: 0x0
10076 00:42:23.352020 INFO: [NOCDAPC] D14_APC_1: 0xfff
10077 00:42:23.355436 INFO: [NOCDAPC] D15_APC_0: 0x0
10078 00:42:23.356014 INFO: [NOCDAPC] D15_APC_1: 0xfff
10079 00:42:23.358959 INFO: [NOCDAPC] APC_CON: 0x4
10080 00:42:23.361726 INFO: [APUAPC] set_apusys_apc done
10081 00:42:23.365250 INFO: [DEVAPC] devapc_init done
10082 00:42:23.372046 INFO: GICv3 without legacy support detected.
10083 00:42:23.375333 INFO: ARM GICv3 driver initialized in EL3
10084 00:42:23.378562 INFO: Maximum SPI INTID supported: 639
10085 00:42:23.382308 INFO: BL31: Initializing runtime services
10086 00:42:23.388829 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10087 00:42:23.391717 INFO: SPM: enable CPC mode
10088 00:42:23.395057 INFO: mcdi ready for mcusys-off-idle and system suspend
10089 00:42:23.401933 INFO: BL31: Preparing for EL3 exit to normal world
10090 00:42:23.405370 INFO: Entry point address = 0x80000000
10091 00:42:23.405954 INFO: SPSR = 0x8
10092 00:42:23.412152
10093 00:42:23.412758
10094 00:42:23.413141
10095 00:42:23.415454 end: 2.2.3 depthcharge-start (duration 00:00:19) [common]
10096 00:42:23.416192 start: 2.2.4 bootloader-commands (timeout 00:04:27) [common]
10097 00:42:23.416727 Setting prompt string to ['asurada:']
10098 00:42:23.417191 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:27)
10099 00:42:23.417933 Starting depthcharge on Spherion...
10100 00:42:23.418327
10101 00:42:23.418672 Wipe memory regions:
10102 00:42:23.419005
10103 00:42:23.419399 [0x00000040000000, 0x00000054600000)
10104 00:42:23.541163
10105 00:42:23.541760 [0x00000054660000, 0x00000080000000)
10106 00:42:23.801449
10107 00:42:23.802022 [0x000000821a7280, 0x000000ffe64000)
10108 00:42:24.546071
10109 00:42:24.546657 [0x00000100000000, 0x00000240000000)
10110 00:42:26.435952
10111 00:42:26.439530 Initializing XHCI USB controller at 0x11200000.
10112 00:42:27.477661
10113 00:42:27.481298 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10114 00:42:27.481781
10115 00:42:27.482155
10116 00:42:27.482962 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10118 00:42:27.584469 asurada: tftpboot 192.168.201.1 14368384/tftp-deploy-28dj6z9m/kernel/image.itb 14368384/tftp-deploy-28dj6z9m/kernel/cmdline
10119 00:42:27.585219 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10120 00:42:27.585674 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:23)
10121 00:42:27.590290 tftpboot 192.168.201.1 14368384/tftp-deploy-28dj6z9m/kernel/image.itp-deploy-28dj6z9m/kernel/cmdline
10122 00:42:27.590774
10123 00:42:27.591148 Waiting for link
10124 00:42:27.748201
10125 00:42:27.748887 R8152: Initializing
10126 00:42:27.749272
10127 00:42:27.751444 Version 9 (ocp_data = 6010)
10128 00:42:27.751919
10129 00:42:27.754453 R8152: Done initializing
10130 00:42:27.754928
10131 00:42:27.755304 Adding net device
10132 00:42:29.699068
10133 00:42:29.699794 done.
10134 00:42:29.700184
10135 00:42:29.700529 MAC: 00:e0:4c:72:2d:d6
10136 00:42:29.700947
10137 00:42:29.702423 Sending DHCP discover... done.
10138 00:42:29.702897
10139 00:42:29.705910 Waiting for reply... done.
10140 00:42:29.706385
10141 00:42:29.709193 Sending DHCP request... done.
10142 00:42:29.709670
10143 00:42:29.717748 Waiting for reply... done.
10144 00:42:29.718330
10145 00:42:29.718704 My ip is 192.168.201.21
10146 00:42:29.719054
10147 00:42:29.721050 The DHCP server ip is 192.168.201.1
10148 00:42:29.721519
10149 00:42:29.727829 TFTP server IP predefined by user: 192.168.201.1
10150 00:42:29.728411
10151 00:42:29.734533 Bootfile predefined by user: 14368384/tftp-deploy-28dj6z9m/kernel/image.itb
10152 00:42:29.735077
10153 00:42:29.737552 Sending tftp read request... done.
10154 00:42:29.738019
10155 00:42:29.742305 Waiting for the transfer...
10156 00:42:29.742777
10157 00:42:30.019232 00000000 ################################################################
10158 00:42:30.019375
10159 00:42:30.279510 00080000 ################################################################
10160 00:42:30.279640
10161 00:42:30.570676 00100000 ################################################################
10162 00:42:30.570806
10163 00:42:30.852082 00180000 ################################################################
10164 00:42:30.852217
10165 00:42:31.131420 00200000 ################################################################
10166 00:42:31.131567
10167 00:42:31.425688 00280000 ################################################################
10168 00:42:31.425813
10169 00:42:31.715796 00300000 ################################################################
10170 00:42:31.715925
10171 00:42:32.001493 00380000 ################################################################
10172 00:42:32.001629
10173 00:42:32.283174 00400000 ################################################################
10174 00:42:32.283319
10175 00:42:32.578093 00480000 ################################################################
10176 00:42:32.578230
10177 00:42:32.874736 00500000 ################################################################
10178 00:42:32.874860
10179 00:42:33.171795 00580000 ################################################################
10180 00:42:33.171947
10181 00:42:33.439865 00600000 ################################################################
10182 00:42:33.440005
10183 00:42:33.706851 00680000 ################################################################
10184 00:42:33.707027
10185 00:42:33.978017 00700000 ################################################################
10186 00:42:33.978163
10187 00:42:34.251310 00780000 ################################################################
10188 00:42:34.251461
10189 00:42:34.520755 00800000 ################################################################
10190 00:42:34.520895
10191 00:42:34.781629 00880000 ################################################################
10192 00:42:34.781761
10193 00:42:35.053737 00900000 ################################################################
10194 00:42:35.053869
10195 00:42:35.325207 00980000 ################################################################
10196 00:42:35.325338
10197 00:42:35.578293 00a00000 ################################################################
10198 00:42:35.578423
10199 00:42:35.831840 00a80000 ################################################################
10200 00:42:35.831974
10201 00:42:36.102833 00b00000 ################################################################
10202 00:42:36.102992
10203 00:42:36.359997 00b80000 ################################################################
10204 00:42:36.360157
10205 00:42:36.619357 00c00000 ################################################################
10206 00:42:36.619516
10207 00:42:36.871151 00c80000 ################################################################
10208 00:42:36.871308
10209 00:42:37.132207 00d00000 ################################################################
10210 00:42:37.132367
10211 00:42:37.393978 00d80000 ################################################################
10212 00:42:37.394119
10213 00:42:37.652022 00e00000 ################################################################
10214 00:42:37.652159
10215 00:42:37.905382 00e80000 ################################################################
10216 00:42:37.905514
10217 00:42:38.156110 00f00000 ################################################################
10218 00:42:38.156281
10219 00:42:38.399425 00f80000 ################################################################
10220 00:42:38.399599
10221 00:42:38.644158 01000000 ################################################################
10222 00:42:38.644321
10223 00:42:38.891336 01080000 ################################################################
10224 00:42:38.891491
10225 00:42:39.137610 01100000 ################################################################
10226 00:42:39.137744
10227 00:42:39.383869 01180000 ################################################################
10228 00:42:39.384019
10229 00:42:39.631598 01200000 ################################################################
10230 00:42:39.631736
10231 00:42:39.878341 01280000 ################################################################
10232 00:42:39.878498
10233 00:42:40.129851 01300000 ################################################################
10234 00:42:40.129989
10235 00:42:40.399180 01380000 ################################################################
10236 00:42:40.399316
10237 00:42:40.665006 01400000 ################################################################
10238 00:42:40.665138
10239 00:42:40.926145 01480000 ################################################################
10240 00:42:40.926277
10241 00:42:41.191395 01500000 ################################################################
10242 00:42:41.191544
10243 00:42:41.442874 01580000 ################################################################
10244 00:42:41.443078
10245 00:42:41.691585 01600000 ################################################################
10246 00:42:41.691755
10247 00:42:41.937609 01680000 ################################################################
10248 00:42:41.937778
10249 00:42:42.182600 01700000 ################################################################
10250 00:42:42.182785
10251 00:42:42.434176 01780000 ################################################################
10252 00:42:42.434343
10253 00:42:42.707654 01800000 ################################################################
10254 00:42:42.707797
10255 00:42:42.962515 01880000 ################################################################
10256 00:42:42.962654
10257 00:42:43.217842 01900000 ################################################################
10258 00:42:43.217988
10259 00:42:43.477597 01980000 ################################################################
10260 00:42:43.477771
10261 00:42:43.742152 01a00000 ################################################################
10262 00:42:43.742297
10263 00:42:44.004765 01a80000 ################################################################
10264 00:42:44.004898
10265 00:42:44.274201 01b00000 ################################################################
10266 00:42:44.274347
10267 00:42:44.529892 01b80000 ################################################################
10268 00:42:44.530130
10269 00:42:44.787269 01c00000 ################################################################
10270 00:42:44.787419
10271 00:42:45.057812 01c80000 ################################################################
10272 00:42:45.057960
10273 00:42:45.333128 01d00000 ################################################################
10274 00:42:45.333271
10275 00:42:45.596843 01d80000 ################################################################
10276 00:42:45.597003
10277 00:42:45.821980 01e00000 ######################################################## done.
10278 00:42:45.822122
10279 00:42:45.825457 The bootfile was 31915946 bytes long.
10280 00:42:45.825545
10281 00:42:45.828821 Sending tftp read request... done.
10282 00:42:45.828901
10283 00:42:45.828965 Waiting for the transfer...
10284 00:42:45.829035
10285 00:42:45.832152 00000000 # done.
10286 00:42:45.832243
10287 00:42:45.839102 Command line loaded dynamically from TFTP file: 14368384/tftp-deploy-28dj6z9m/kernel/cmdline
10288 00:42:45.839188
10289 00:42:45.862004 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14368384/extract-nfsrootfs-s_fvawcb,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10290 00:42:45.862096
10291 00:42:45.862163 Loading FIT.
10292 00:42:45.862224
10293 00:42:45.865435 Image ramdisk-1 has 18740277 bytes.
10294 00:42:45.865520
10295 00:42:45.868387 Image fdt-1 has 47258 bytes.
10296 00:42:45.868472
10297 00:42:45.871753 Image kernel-1 has 13126376 bytes.
10298 00:42:45.871838
10299 00:42:45.881594 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10300 00:42:45.881683
10301 00:42:45.898418 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10302 00:42:45.898509
10303 00:42:45.904689 Choosing best match conf-1 for compat google,spherion-rev2.
10304 00:42:45.904775
10305 00:42:45.912476 Connected to device vid:did:rid of 1ae0:0028:00
10306 00:42:45.919748
10307 00:42:45.923250 tpm_get_response: command 0x17b, return code 0x0
10308 00:42:45.923335
10309 00:42:45.929577 ec_init: CrosEC protocol v3 supported (256, 248)
10310 00:42:45.929661
10311 00:42:45.933059 tpm_cleanup: add release locality here.
10312 00:42:45.933143
10313 00:42:45.936426 Shutting down all USB controllers.
10314 00:42:45.936511
10315 00:42:45.939584 Removing current net device
10316 00:42:45.939667
10317 00:42:45.942850 Exiting depthcharge with code 4 at timestamp: 51856065
10318 00:42:45.942934
10319 00:42:45.946369 LZMA decompressing kernel-1 to 0x821a6718
10320 00:42:45.946452
10321 00:42:45.949673 LZMA decompressing kernel-1 to 0x40000000
10322 00:42:47.568033
10323 00:42:47.568230 jumping to kernel
10324 00:42:47.568831 end: 2.2.4 bootloader-commands (duration 00:00:24) [common]
10325 00:42:47.568975 start: 2.2.5 auto-login-action (timeout 00:04:03) [common]
10326 00:42:47.569088 Setting prompt string to ['Linux version [0-9]']
10327 00:42:47.569187 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10328 00:42:47.569285 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10329 00:42:47.650498
10330 00:42:47.653946 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10331 00:42:47.657919 start: 2.2.5.1 login-action (timeout 00:04:03) [common]
10332 00:42:47.658475 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10333 00:42:47.658869 Setting prompt string to []
10334 00:42:47.659280 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10335 00:42:47.659714 Using line separator: #'\n'#
10336 00:42:47.660058 No login prompt set.
10337 00:42:47.660410 Parsing kernel messages
10338 00:42:47.660838 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10339 00:42:47.661359 [login-action] Waiting for messages, (timeout 00:04:03)
10340 00:42:47.661706 Waiting using forced prompt support (timeout 00:02:01)
10341 00:42:47.676985 [ 0.000000] Linux version 6.1.92-cip22 (KernelCI@build-j232175-arm64-gcc-10-defconfig-arm64-chromebook-7lg8d) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sun Jun 16 00:28:47 UTC 2024
10342 00:42:47.680061 [ 0.000000] random: crng init done
10343 00:42:47.686677 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10344 00:42:47.690218 [ 0.000000] efi: UEFI not found.
10345 00:42:47.697097 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10346 00:42:47.703376 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10347 00:42:47.713541 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10348 00:42:47.723358 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10349 00:42:47.730374 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10350 00:42:47.736589 [ 0.000000] printk: bootconsole [mtk8250] enabled
10351 00:42:47.743469 [ 0.000000] NUMA: No NUMA configuration found
10352 00:42:47.749866 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10353 00:42:47.753092 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10354 00:42:47.756429 [ 0.000000] Zone ranges:
10355 00:42:47.762919 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10356 00:42:47.766238 [ 0.000000] DMA32 empty
10357 00:42:47.772805 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10358 00:42:47.775915 [ 0.000000] Movable zone start for each node
10359 00:42:47.779278 [ 0.000000] Early memory node ranges
10360 00:42:47.785796 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10361 00:42:47.792238 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10362 00:42:47.798802 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10363 00:42:47.805428 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10364 00:42:47.812091 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10365 00:42:47.818820 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10366 00:42:47.875183 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10367 00:42:47.882035 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10368 00:42:47.888193 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10369 00:42:47.891456 [ 0.000000] psci: probing for conduit method from DT.
10370 00:42:47.898371 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10371 00:42:47.901549 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10372 00:42:47.908335 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10373 00:42:47.911706 [ 0.000000] psci: SMC Calling Convention v1.2
10374 00:42:47.918054 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10375 00:42:47.921450 [ 0.000000] Detected VIPT I-cache on CPU0
10376 00:42:47.927949 [ 0.000000] CPU features: detected: GIC system register CPU interface
10377 00:42:47.934581 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10378 00:42:47.941286 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10379 00:42:47.947447 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10380 00:42:47.957581 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10381 00:42:47.964226 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10382 00:42:47.967472 [ 0.000000] alternatives: applying boot alternatives
10383 00:42:47.974328 [ 0.000000] Fallback order for Node 0: 0
10384 00:42:47.980974 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10385 00:42:47.983911 [ 0.000000] Policy zone: Normal
10386 00:42:48.006986 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14368384/extract-nfsrootfs-s_fvawcb,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10387 00:42:48.017194 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10388 00:42:48.028480 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10389 00:42:48.038457 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10390 00:42:48.044987 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10391 00:42:48.048283 <6>[ 0.000000] software IO TLB: area num 8.
10392 00:42:48.105247 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10393 00:42:48.254847 <6>[ 0.000000] Memory: 7945760K/8385536K available (18112K kernel code, 4120K rwdata, 22644K rodata, 8512K init, 616K bss, 407008K reserved, 32768K cma-reserved)
10394 00:42:48.261373 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10395 00:42:48.268174 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10396 00:42:48.271545 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10397 00:42:48.277875 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10398 00:42:48.284768 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10399 00:42:48.287787 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10400 00:42:48.297975 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10401 00:42:48.304210 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10402 00:42:48.311215 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10403 00:42:48.317271 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10404 00:42:48.320776 <6>[ 0.000000] GICv3: 608 SPIs implemented
10405 00:42:48.324220 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10406 00:42:48.330576 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10407 00:42:48.334042 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10408 00:42:48.340485 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10409 00:42:48.353603 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10410 00:42:48.366967 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10411 00:42:48.373242 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10412 00:42:48.381416 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10413 00:42:48.394747 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10414 00:42:48.401332 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10415 00:42:48.407953 <6>[ 0.009184] Console: colour dummy device 80x25
10416 00:42:48.417878 <6>[ 0.013931] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10417 00:42:48.424236 <6>[ 0.024373] pid_max: default: 32768 minimum: 301
10418 00:42:48.427702 <6>[ 0.029273] LSM: Security Framework initializing
10419 00:42:48.434064 <6>[ 0.034213] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10420 00:42:48.444042 <6>[ 0.042075] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10421 00:42:48.454338 <6>[ 0.051540] cblist_init_generic: Setting adjustable number of callback queues.
10422 00:42:48.460505 <6>[ 0.058985] cblist_init_generic: Setting shift to 3 and lim to 1.
10423 00:42:48.467147 <6>[ 0.065325] cblist_init_generic: Setting adjustable number of callback queues.
10424 00:42:48.473923 <6>[ 0.072751] cblist_init_generic: Setting shift to 3 and lim to 1.
10425 00:42:48.477386 <6>[ 0.079151] rcu: Hierarchical SRCU implementation.
10426 00:42:48.483582 <6>[ 0.084165] rcu: Max phase no-delay instances is 1000.
10427 00:42:48.490748 <6>[ 0.091199] EFI services will not be available.
10428 00:42:48.493390 <6>[ 0.096155] smp: Bringing up secondary CPUs ...
10429 00:42:48.502781 <6>[ 0.101205] Detected VIPT I-cache on CPU1
10430 00:42:48.509313 <6>[ 0.101279] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10431 00:42:48.515689 <6>[ 0.101311] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10432 00:42:48.518749 <6>[ 0.101641] Detected VIPT I-cache on CPU2
10433 00:42:48.528942 <6>[ 0.101692] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10434 00:42:48.535570 <6>[ 0.101709] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10435 00:42:48.538542 <6>[ 0.101967] Detected VIPT I-cache on CPU3
10436 00:42:48.545121 <6>[ 0.102014] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10437 00:42:48.551849 <6>[ 0.102029] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10438 00:42:48.558270 <6>[ 0.102333] CPU features: detected: Spectre-v4
10439 00:42:48.561418 <6>[ 0.102338] CPU features: detected: Spectre-BHB
10440 00:42:48.564890 <6>[ 0.102344] Detected PIPT I-cache on CPU4
10441 00:42:48.571454 <6>[ 0.102402] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10442 00:42:48.578125 <6>[ 0.102418] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10443 00:42:48.584871 <6>[ 0.102710] Detected PIPT I-cache on CPU5
10444 00:42:48.591033 <6>[ 0.102772] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10445 00:42:48.598337 <6>[ 0.102789] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10446 00:42:48.601313 <6>[ 0.103070] Detected PIPT I-cache on CPU6
10447 00:42:48.610945 <6>[ 0.103136] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10448 00:42:48.617736 <6>[ 0.103151] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10449 00:42:48.621030 <6>[ 0.103449] Detected PIPT I-cache on CPU7
10450 00:42:48.627772 <6>[ 0.103514] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10451 00:42:48.634118 <6>[ 0.103530] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10452 00:42:48.637407 <6>[ 0.103577] smp: Brought up 1 node, 8 CPUs
10453 00:42:48.644261 <6>[ 0.244944] SMP: Total of 8 processors activated.
10454 00:42:48.647439 <6>[ 0.249865] CPU features: detected: 32-bit EL0 Support
10455 00:42:48.657599 <6>[ 0.255228] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10456 00:42:48.663957 <6>[ 0.264029] CPU features: detected: Common not Private translations
10457 00:42:48.670728 <6>[ 0.270504] CPU features: detected: CRC32 instructions
10458 00:42:48.677216 <6>[ 0.275856] CPU features: detected: RCpc load-acquire (LDAPR)
10459 00:42:48.680496 <6>[ 0.281816] CPU features: detected: LSE atomic instructions
10460 00:42:48.686983 <6>[ 0.287597] CPU features: detected: Privileged Access Never
10461 00:42:48.693496 <6>[ 0.293377] CPU features: detected: RAS Extension Support
10462 00:42:48.700480 <6>[ 0.298986] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10463 00:42:48.703529 <6>[ 0.306250] CPU: All CPU(s) started at EL2
10464 00:42:48.710541 <6>[ 0.310584] alternatives: applying system-wide alternatives
10465 00:42:48.719966 <6>[ 0.321434] devtmpfs: initialized
10466 00:42:48.735653 <6>[ 0.330266] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10467 00:42:48.742469 <6>[ 0.340225] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10468 00:42:48.748542 <6>[ 0.348238] pinctrl core: initialized pinctrl subsystem
10469 00:42:48.752253 <6>[ 0.354918] DMI not present or invalid.
10470 00:42:48.758832 <6>[ 0.359328] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10471 00:42:48.768307 <6>[ 0.366088] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10472 00:42:48.775018 <6>[ 0.373675] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10473 00:42:48.784975 <6>[ 0.381896] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10474 00:42:48.788200 <6>[ 0.390138] audit: initializing netlink subsys (disabled)
10475 00:42:48.798466 <5>[ 0.395832] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10476 00:42:48.804905 <6>[ 0.396556] thermal_sys: Registered thermal governor 'step_wise'
10477 00:42:48.811396 <6>[ 0.403800] thermal_sys: Registered thermal governor 'power_allocator'
10478 00:42:48.814903 <6>[ 0.410057] cpuidle: using governor menu
10479 00:42:48.821306 <6>[ 0.421016] NET: Registered PF_QIPCRTR protocol family
10480 00:42:48.827737 <6>[ 0.426501] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10481 00:42:48.834545 <6>[ 0.433603] ASID allocator initialised with 32768 entries
10482 00:42:48.837676 <6>[ 0.440195] Serial: AMBA PL011 UART driver
10483 00:42:48.847552 <4>[ 0.449022] Trying to register duplicate clock ID: 134
10484 00:42:48.906392 <6>[ 0.510494] KASLR enabled
10485 00:42:48.920260 <6>[ 0.518189] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10486 00:42:48.926920 <6>[ 0.525205] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10487 00:42:48.933590 <6>[ 0.531696] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10488 00:42:48.940035 <6>[ 0.538702] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10489 00:42:48.947114 <6>[ 0.545190] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10490 00:42:48.953406 <6>[ 0.552194] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10491 00:42:48.960108 <6>[ 0.558680] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10492 00:42:48.966247 <6>[ 0.565686] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10493 00:42:48.969396 <6>[ 0.573212] ACPI: Interpreter disabled.
10494 00:42:48.978600 <6>[ 0.579651] iommu: Default domain type: Translated
10495 00:42:48.984781 <6>[ 0.584763] iommu: DMA domain TLB invalidation policy: strict mode
10496 00:42:48.988321 <5>[ 0.591421] SCSI subsystem initialized
10497 00:42:48.994800 <6>[ 0.595590] usbcore: registered new interface driver usbfs
10498 00:42:49.001715 <6>[ 0.601324] usbcore: registered new interface driver hub
10499 00:42:49.004842 <6>[ 0.606875] usbcore: registered new device driver usb
10500 00:42:49.011515 <6>[ 0.612979] pps_core: LinuxPPS API ver. 1 registered
10501 00:42:49.021760 <6>[ 0.618172] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10502 00:42:49.024986 <6>[ 0.627518] PTP clock support registered
10503 00:42:49.028263 <6>[ 0.631760] EDAC MC: Ver: 3.0.0
10504 00:42:49.035548 <6>[ 0.636923] FPGA manager framework
10505 00:42:49.042225 <6>[ 0.640611] Advanced Linux Sound Architecture Driver Initialized.
10506 00:42:49.045698 <6>[ 0.647380] vgaarb: loaded
10507 00:42:49.048858 <6>[ 0.650480] clocksource: Switched to clocksource arch_sys_counter
10508 00:42:49.055652 <5>[ 0.656917] VFS: Disk quotas dquot_6.6.0
10509 00:42:49.062383 <6>[ 0.661105] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10510 00:42:49.065698 <6>[ 0.668294] pnp: PnP ACPI: disabled
10511 00:42:49.073658 <6>[ 0.675014] NET: Registered PF_INET protocol family
10512 00:42:49.083777 <6>[ 0.680605] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10513 00:42:49.095112 <6>[ 0.692922] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10514 00:42:49.104824 <6>[ 0.701733] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10515 00:42:49.111592 <6>[ 0.709700] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10516 00:42:49.118113 <6>[ 0.718401] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10517 00:42:49.130352 <6>[ 0.728161] TCP: Hash tables configured (established 65536 bind 65536)
10518 00:42:49.136962 <6>[ 0.735024] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10519 00:42:49.143430 <6>[ 0.742224] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10520 00:42:49.150429 <6>[ 0.749930] NET: Registered PF_UNIX/PF_LOCAL protocol family
10521 00:42:49.157042 <6>[ 0.756085] RPC: Registered named UNIX socket transport module.
10522 00:42:49.160043 <6>[ 0.762236] RPC: Registered udp transport module.
10523 00:42:49.166796 <6>[ 0.767168] RPC: Registered tcp transport module.
10524 00:42:49.173516 <6>[ 0.772101] RPC: Registered tcp NFSv4.1 backchannel transport module.
10525 00:42:49.176892 <6>[ 0.778767] PCI: CLS 0 bytes, default 64
10526 00:42:49.180192 <6>[ 0.783173] Unpacking initramfs...
10527 00:42:49.190188 <6>[ 0.786878] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10528 00:42:49.196525 <6>[ 0.795511] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10529 00:42:49.203444 <6>[ 0.804316] kvm [1]: IPA Size Limit: 40 bits
10530 00:42:49.206656 <6>[ 0.808847] kvm [1]: GICv3: no GICV resource entry
10531 00:42:49.213415 <6>[ 0.813870] kvm [1]: disabling GICv2 emulation
10532 00:42:49.219592 <6>[ 0.818557] kvm [1]: GIC system register CPU interface enabled
10533 00:42:49.223210 <6>[ 0.824711] kvm [1]: vgic interrupt IRQ18
10534 00:42:49.229944 <6>[ 0.830538] kvm [1]: VHE mode initialized successfully
10535 00:42:49.236284 <5>[ 0.836903] Initialise system trusted keyrings
10536 00:42:49.242833 <6>[ 0.841718] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10537 00:42:49.250655 <6>[ 0.851660] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10538 00:42:49.257234 <5>[ 0.858053] NFS: Registering the id_resolver key type
10539 00:42:49.260163 <5>[ 0.863356] Key type id_resolver registered
10540 00:42:49.267037 <5>[ 0.867773] Key type id_legacy registered
10541 00:42:49.273570 <6>[ 0.872054] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10542 00:42:49.280195 <6>[ 0.878979] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10543 00:42:49.286754 <6>[ 0.886684] 9p: Installing v9fs 9p2000 file system support
10544 00:42:49.323149 <5>[ 0.924495] Key type asymmetric registered
10545 00:42:49.326396 <5>[ 0.928823] Asymmetric key parser 'x509' registered
10546 00:42:49.336424 <6>[ 0.933979] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10547 00:42:49.339732 <6>[ 0.941594] io scheduler mq-deadline registered
10548 00:42:49.343342 <6>[ 0.946355] io scheduler kyber registered
10549 00:42:49.362315 <6>[ 0.963394] EINJ: ACPI disabled.
10550 00:42:49.394591 <4>[ 0.989477] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10551 00:42:49.404457 <4>[ 1.000110] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10552 00:42:49.419854 <6>[ 1.020968] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10553 00:42:49.427810 <6>[ 1.028945] printk: console [ttyS0] disabled
10554 00:42:49.455472 <6>[ 1.053571] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10555 00:42:49.462436 <6>[ 1.063042] printk: console [ttyS0] enabled
10556 00:42:49.465598 <6>[ 1.063042] printk: console [ttyS0] enabled
10557 00:42:49.472557 <6>[ 1.071935] printk: bootconsole [mtk8250] disabled
10558 00:42:49.475872 <6>[ 1.071935] printk: bootconsole [mtk8250] disabled
10559 00:42:49.482258 <6>[ 1.083007] SuperH (H)SCI(F) driver initialized
10560 00:42:49.486110 <6>[ 1.088289] msm_serial: driver initialized
10561 00:42:49.499033 <6>[ 1.097206] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10562 00:42:49.509193 <6>[ 1.105751] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10563 00:42:49.515930 <6>[ 1.114293] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10564 00:42:49.525500 <6>[ 1.122919] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10565 00:42:49.535236 <6>[ 1.131625] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10566 00:42:49.542161 <6>[ 1.140344] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10567 00:42:49.552245 <6>[ 1.148886] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10568 00:42:49.558761 <6>[ 1.157681] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10569 00:42:49.568414 <6>[ 1.166222] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10570 00:42:49.580736 <6>[ 1.181939] loop: module loaded
10571 00:42:49.587127 <6>[ 1.187905] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10572 00:42:49.609829 <4>[ 1.211279] mtk-pmic-keys: Failed to locate of_node [id: -1]
10573 00:42:49.616732 <6>[ 1.218055] megasas: 07.719.03.00-rc1
10574 00:42:49.626742 <6>[ 1.227862] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10575 00:42:49.633614 <6>[ 1.233872] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10576 00:42:49.649221 <6>[ 1.250612] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10577 00:42:49.706136 <6>[ 1.300476] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10578 00:42:49.972629 <6>[ 1.573471] Freeing initrd memory: 18296K
10579 00:42:49.984678 <6>[ 1.585254] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10580 00:42:49.995740 <6>[ 1.596198] tun: Universal TUN/TAP device driver, 1.6
10581 00:42:49.998730 <6>[ 1.602257] thunder_xcv, ver 1.0
10582 00:42:50.002047 <6>[ 1.605761] thunder_bgx, ver 1.0
10583 00:42:50.005785 <6>[ 1.609263] nicpf, ver 1.0
10584 00:42:50.016037 <6>[ 1.613288] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10585 00:42:50.018933 <6>[ 1.620763] hns3: Copyright (c) 2017 Huawei Corporation.
10586 00:42:50.022609 <6>[ 1.626356] hclge is initializing
10587 00:42:50.028857 <6>[ 1.629931] e1000: Intel(R) PRO/1000 Network Driver
10588 00:42:50.035880 <6>[ 1.635060] e1000: Copyright (c) 1999-2006 Intel Corporation.
10589 00:42:50.039318 <6>[ 1.641075] e1000e: Intel(R) PRO/1000 Network Driver
10590 00:42:50.045793 <6>[ 1.646290] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10591 00:42:50.052596 <6>[ 1.652476] igb: Intel(R) Gigabit Ethernet Network Driver
10592 00:42:50.058798 <6>[ 1.658126] igb: Copyright (c) 2007-2014 Intel Corporation.
10593 00:42:50.066152 <6>[ 1.663964] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10594 00:42:50.072246 <6>[ 1.670482] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10595 00:42:50.075400 <6>[ 1.676945] sky2: driver version 1.30
10596 00:42:50.082513 <6>[ 1.681871] usbcore: registered new device driver r8152-cfgselector
10597 00:42:50.088694 <6>[ 1.688427] usbcore: registered new interface driver r8152
10598 00:42:50.091974 <6>[ 1.694242] VFIO - User Level meta-driver version: 0.3
10599 00:42:50.101556 <6>[ 1.702459] usbcore: registered new interface driver usb-storage
10600 00:42:50.109003 <6>[ 1.708909] usbcore: registered new device driver onboard-usb-hub
10601 00:42:50.117461 <6>[ 1.718110] mt6397-rtc mt6359-rtc: registered as rtc0
10602 00:42:50.127167 <6>[ 1.723578] mt6397-rtc mt6359-rtc: setting system clock to 2024-06-16T00:41:24 UTC (1718498484)
10603 00:42:50.130703 <6>[ 1.733142] i2c_dev: i2c /dev entries driver
10604 00:42:50.144621 <4>[ 1.745187] cpu cpu0: supply cpu not found, using dummy regulator
10605 00:42:50.151354 <4>[ 1.751615] cpu cpu1: supply cpu not found, using dummy regulator
10606 00:42:50.157597 <4>[ 1.758034] cpu cpu2: supply cpu not found, using dummy regulator
10607 00:42:50.164637 <4>[ 1.764435] cpu cpu3: supply cpu not found, using dummy regulator
10608 00:42:50.170751 <4>[ 1.770830] cpu cpu4: supply cpu not found, using dummy regulator
10609 00:42:50.178020 <4>[ 1.777228] cpu cpu5: supply cpu not found, using dummy regulator
10610 00:42:50.184408 <4>[ 1.783628] cpu cpu6: supply cpu not found, using dummy regulator
10611 00:42:50.190889 <4>[ 1.790027] cpu cpu7: supply cpu not found, using dummy regulator
10612 00:42:50.211043 <6>[ 1.811669] cpu cpu0: EM: created perf domain
10613 00:42:50.214385 <6>[ 1.816601] cpu cpu4: EM: created perf domain
10614 00:42:50.221493 <6>[ 1.822209] sdhci: Secure Digital Host Controller Interface driver
10615 00:42:50.228194 <6>[ 1.828642] sdhci: Copyright(c) Pierre Ossman
10616 00:42:50.234817 <6>[ 1.833599] Synopsys Designware Multimedia Card Interface Driver
10617 00:42:50.241380 <6>[ 1.840236] sdhci-pltfm: SDHCI platform and OF driver helper
10618 00:42:50.244667 <6>[ 1.840384] mmc0: CQHCI version 5.10
10619 00:42:50.251213 <6>[ 1.850281] ledtrig-cpu: registered to indicate activity on CPUs
10620 00:42:50.257668 <6>[ 1.857190] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10621 00:42:50.264951 <6>[ 1.864242] usbcore: registered new interface driver usbhid
10622 00:42:50.268295 <6>[ 1.870063] usbhid: USB HID core driver
10623 00:42:50.274471 <6>[ 1.874233] spi_master spi0: will run message pump with realtime priority
10624 00:42:50.321499 <6>[ 1.915511] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10625 00:42:50.337619 <6>[ 1.931280] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10626 00:42:50.343844 <6>[ 1.935579] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x17414
10627 00:42:50.351591 <6>[ 1.952183] cros-ec-spi spi0.0: Chrome EC device registered
10628 00:42:50.358488 <6>[ 1.958215] mmc0: Command Queue Engine enabled
10629 00:42:50.364924 <6>[ 1.962961] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10630 00:42:50.368521 <6>[ 1.970758] mmcblk0: mmc0:0001 DA4128 116 GiB
10631 00:42:50.378280 <6>[ 1.979376] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10632 00:42:50.385772 <6>[ 1.986788] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10633 00:42:50.392877 <6>[ 1.992836] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10634 00:42:50.402624 <6>[ 1.998147] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10635 00:42:50.409662 <6>[ 1.998762] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10636 00:42:50.412885 <6>[ 2.008945] NET: Registered PF_PACKET protocol family
10637 00:42:50.419560 <6>[ 2.019433] 9pnet: Installing 9P2000 support
10638 00:42:50.422789 <5>[ 2.024002] Key type dns_resolver registered
10639 00:42:50.426051 <6>[ 2.028962] registered taskstats version 1
10640 00:42:50.432481 <5>[ 2.033368] Loading compiled-in X.509 certificates
10641 00:42:50.463202 <4>[ 2.057116] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10642 00:42:50.472893 <4>[ 2.067913] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10643 00:42:50.487429 <6>[ 2.088072] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10644 00:42:50.494017 <6>[ 2.095120] xhci-mtk 11200000.usb: xHCI Host Controller
10645 00:42:50.500796 <6>[ 2.100623] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10646 00:42:50.511110 <6>[ 2.108482] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10647 00:42:50.517841 <6>[ 2.117919] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10648 00:42:50.524415 <6>[ 2.124037] xhci-mtk 11200000.usb: xHCI Host Controller
10649 00:42:50.530759 <6>[ 2.129534] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10650 00:42:50.538135 <6>[ 2.137332] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10651 00:42:50.544642 <6>[ 2.145198] hub 1-0:1.0: USB hub found
10652 00:42:50.547930 <6>[ 2.149255] hub 1-0:1.0: 1 port detected
10653 00:42:50.554940 <6>[ 2.153586] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10654 00:42:50.561214 <6>[ 2.162351] hub 2-0:1.0: USB hub found
10655 00:42:50.564957 <6>[ 2.166390] hub 2-0:1.0: 1 port detected
10656 00:42:50.573152 <6>[ 2.173501] mtk-msdc 11f70000.mmc: Got CD GPIO
10657 00:42:50.586887 <6>[ 2.184273] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10658 00:42:50.596760 <6>[ 2.192649] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10659 00:42:50.603387 <6>[ 2.200996] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10660 00:42:50.613332 <6>[ 2.209337] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10661 00:42:50.620128 <6>[ 2.217676] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10662 00:42:50.630059 <6>[ 2.226017] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10663 00:42:50.636773 <6>[ 2.234355] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10664 00:42:50.643813 <6>[ 2.242692] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10665 00:42:50.653639 <6>[ 2.251030] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10666 00:42:50.660422 <6>[ 2.259367] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10667 00:42:50.670452 <6>[ 2.267704] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10668 00:42:50.677469 <6>[ 2.276047] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10669 00:42:50.686638 <6>[ 2.284385] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10670 00:42:50.696697 <6>[ 2.292723] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10671 00:42:50.703829 <6>[ 2.301061] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10672 00:42:50.709998 <6>[ 2.309663] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10673 00:42:50.716699 <6>[ 2.316812] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10674 00:42:50.723071 <6>[ 2.323621] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10675 00:42:50.729804 <6>[ 2.330392] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10676 00:42:50.739857 <6>[ 2.337313] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10677 00:42:50.746612 <6>[ 2.344193] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10678 00:42:50.756252 <6>[ 2.353326] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10679 00:42:50.765968 <6>[ 2.362445] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10680 00:42:50.776115 <6>[ 2.371739] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10681 00:42:50.785974 <6>[ 2.381205] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10682 00:42:50.792802 <6>[ 2.390673] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10683 00:42:50.802612 <6>[ 2.399791] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10684 00:42:50.812753 <6>[ 2.409257] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10685 00:42:50.822149 <6>[ 2.418377] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10686 00:42:50.832355 <6>[ 2.427675] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10687 00:42:50.842719 <6>[ 2.437835] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10688 00:42:50.852141 <6>[ 2.449837] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10689 00:42:50.859598 <6>[ 2.460675] Trying to probe devices needed for running init ...
10690 00:42:50.870745 <3>[ 2.467937] mt8192-audio 11210000.syscon:mt8192-afe-pcm: could not get audiosys reset:-517
10691 00:42:50.977187 <6>[ 2.574804] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10692 00:42:51.131551 <6>[ 2.732527] hub 1-1:1.0: USB hub found
10693 00:42:51.134790 <6>[ 2.737078] hub 1-1:1.0: 4 ports detected
10694 00:42:51.145041 <6>[ 2.746125] hub 1-1:1.0: USB hub found
10695 00:42:51.148650 <6>[ 2.750428] hub 1-1:1.0: 4 ports detected
10696 00:42:51.257312 <6>[ 2.854990] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10697 00:42:51.284030 <6>[ 2.884808] hub 2-1:1.0: USB hub found
10698 00:42:51.287236 <6>[ 2.889333] hub 2-1:1.0: 3 ports detected
10699 00:42:51.299636 <6>[ 2.900283] hub 2-1:1.0: USB hub found
10700 00:42:51.302595 <6>[ 2.904832] hub 2-1:1.0: 3 ports detected
10701 00:42:51.473293 <6>[ 3.070807] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10702 00:42:51.606129 <6>[ 3.206613] hub 1-1.4:1.0: USB hub found
10703 00:42:51.609234 <6>[ 3.211276] hub 1-1.4:1.0: 2 ports detected
10704 00:42:51.623972 <6>[ 3.224850] hub 1-1.4:1.0: USB hub found
10705 00:42:51.627086 <6>[ 3.229529] hub 1-1.4:1.0: 2 ports detected
10706 00:42:51.685310 <6>[ 3.283015] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10707 00:42:51.793889 <6>[ 3.391432] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10708 00:42:51.829530 <4>[ 3.426855] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10709 00:42:51.839286 <4>[ 3.435966] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10710 00:42:51.883589 <6>[ 3.484358] r8152 2-1.3:1.0 eth0: v1.12.13
10711 00:42:51.924814 <6>[ 3.522603] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10712 00:42:52.120888 <6>[ 3.718657] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10713 00:42:53.475849 <6>[ 5.077557] r8152 2-1.3:1.0 eth0: carrier on
10714 00:42:56.133267 <5>[ 5.102598] Sending DHCP requests .., OK
10715 00:42:56.140286 <6>[ 7.739103] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.21
10716 00:42:56.143314 <6>[ 7.747405] IP-Config: Complete:
10717 00:42:56.156474 <6>[ 7.750901] device=eth0, hwaddr=00:e0:4c:72:2d:d6, ipaddr=192.168.201.21, mask=255.255.255.0, gw=192.168.201.1
10718 00:42:56.163044 <6>[ 7.761619] host=mt8192-asurada-spherion-r0-cbg-1, domain=lava-rack, nis-domain=(none)
10719 00:42:56.169774 <6>[ 7.770238] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10720 00:42:56.176756 <6>[ 7.770247] nameserver0=192.168.201.1
10721 00:42:56.179671 <6>[ 7.782391] clk: Disabling unused clocks
10722 00:42:56.183144 <6>[ 7.787952] ALSA device list:
10723 00:42:56.189316 <6>[ 7.791227] No soundcards found.
10724 00:42:56.197606 <6>[ 7.798791] Freeing unused kernel memory: 8512K
10725 00:42:56.200755 <6>[ 7.803707] Run /init as init process
10726 00:42:56.210268 Loading, please wait...
10727 00:42:56.239377 Starting systemd-udevd version 252.22-1~deb12u1
10728 00:42:56.481539 <6>[ 8.080034] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10729 00:42:56.488464 <6>[ 8.089150] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10730 00:42:56.503577 <6>[ 8.101853] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10731 00:42:56.507310 <6>[ 8.108305] remoteproc remoteproc0: scp is available
10732 00:42:56.517112 <6>[ 8.109935] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10733 00:42:56.520436 <6>[ 8.115914] remoteproc remoteproc0: powering up scp
10734 00:42:56.530516 <6>[ 8.117061] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10735 00:42:56.536945 <6>[ 8.117093] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10736 00:42:56.546830 <6>[ 8.117102] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10737 00:42:56.557278 <4>[ 8.123199] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10738 00:42:56.563857 <6>[ 8.128082] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10739 00:42:56.570009 <6>[ 8.128108] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10740 00:42:56.576463 <6>[ 8.136319] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10741 00:42:56.586601 <6>[ 8.139981] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10742 00:42:56.593559 <3>[ 8.153942] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10743 00:42:56.599882 <6>[ 8.162106] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10744 00:42:56.609526 <3>[ 8.170669] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10745 00:42:56.616644 <4>[ 8.172445] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10746 00:42:56.623255 <4>[ 8.176398] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10747 00:42:56.633331 <6>[ 8.180046] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10748 00:42:56.639742 <6>[ 8.180056] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10749 00:42:56.645988 <6>[ 8.180059] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10750 00:42:56.656275 <6>[ 8.180061] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10751 00:42:56.665765 <3>[ 8.184407] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10752 00:42:56.672936 <4>[ 8.186054] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10753 00:42:56.679442 <4>[ 8.186054] Fallback method does not support PEC.
10754 00:42:56.682902 <6>[ 8.228371] mc: Linux media interface: v0.10
10755 00:42:56.689168 <6>[ 8.239949] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10756 00:42:56.699110 <3>[ 8.242758] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10757 00:42:56.705598 <3>[ 8.242773] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10758 00:42:56.715661 <3>[ 8.242777] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10759 00:42:56.722495 <3>[ 8.242889] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10760 00:42:56.728855 <3>[ 8.242899] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10761 00:42:56.738883 <3>[ 8.250856] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10762 00:42:56.745497 <6>[ 8.254374] pci_bus 0000:00: root bus resource [bus 00-ff]
10763 00:42:56.752466 <3>[ 8.263534] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10764 00:42:56.758789 <6>[ 8.269497] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10765 00:42:56.765042 <6>[ 8.271499] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10766 00:42:56.774972 <6>[ 8.271508] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10767 00:42:56.781825 <6>[ 8.271565] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10768 00:42:56.791819 <6>[ 8.285178] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10769 00:42:56.798533 <3>[ 8.285659] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10770 00:42:56.807984 <3>[ 8.285665] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10771 00:42:56.815177 <3>[ 8.285716] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10772 00:42:56.824876 <3>[ 8.285719] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10773 00:42:56.831292 <3>[ 8.285722] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10774 00:42:56.841497 <3>[ 8.285727] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10775 00:42:56.847912 <3>[ 8.285729] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10776 00:42:56.854781 <3>[ 8.285765] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10777 00:42:56.865202 <6>[ 8.289680] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10778 00:42:56.871373 <6>[ 8.290617] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10779 00:42:56.881220 <6>[ 8.292418] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10780 00:42:56.887582 <6>[ 8.296530] remoteproc remoteproc0: remote processor scp is now up
10781 00:42:56.891520 <6>[ 8.304666] pci 0000:00:00.0: supports D1 D2
10782 00:42:56.901256 <6>[ 8.307155] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10783 00:42:56.910809 <6>[ 8.307522] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10784 00:42:56.920602 <6>[ 8.318404] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10785 00:42:56.927236 <6>[ 8.320758] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10786 00:42:56.930618 <6>[ 8.337504] videodev: Linux video capture interface: v2.00
10787 00:42:56.941065 <6>[ 8.346388] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10788 00:42:56.944617 <6>[ 8.366870] Bluetooth: Core ver 2.22
10789 00:42:56.950356 <6>[ 8.373309] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10790 00:42:56.957077 <6>[ 8.383133] NET: Registered PF_BLUETOOTH protocol family
10791 00:42:56.963609 <6>[ 8.389319] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10792 00:42:56.970055 <6>[ 8.397846] Bluetooth: HCI device and connection manager initialized
10793 00:42:56.977460 <6>[ 8.405901] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10794 00:42:56.984044 <6>[ 8.407253] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10795 00:42:56.997231 <6>[ 8.409011] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10796 00:42:57.003917 <6>[ 8.409308] usbcore: registered new interface driver uvcvideo
10797 00:42:57.006901 <6>[ 8.413989] Bluetooth: HCI socket layer initialized
10798 00:42:57.013821 <6>[ 8.422053] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10799 00:42:57.020267 <6>[ 8.430129] Bluetooth: L2CAP socket layer initialized
10800 00:42:57.023808 <6>[ 8.438311] pci 0000:01:00.0: supports D1 D2
10801 00:42:57.030317 <6>[ 8.446287] Bluetooth: SCO socket layer initialized
10802 00:42:57.036631 <6>[ 8.454350] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10803 00:42:57.043687 <6>[ 8.455111] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10804 00:42:57.049856 <6>[ 8.466635] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10805 00:42:57.056517 <6>[ 8.539044] usbcore: registered new interface driver btusb
10806 00:42:57.066647 <4>[ 8.540112] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10807 00:42:57.073005 <3>[ 8.540120] Bluetooth: hci0: Failed to load firmware file (-2)
10808 00:42:57.079379 <3>[ 8.540122] Bluetooth: hci0: Failed to set up firmware (-2)
10809 00:42:57.089733 <4>[ 8.540125] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10810 00:42:57.096140 <6>[ 8.546621] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10811 00:42:57.105918 <6>[ 8.703592] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10812 00:42:57.112498 <6>[ 8.711590] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10813 00:42:57.119374 <6>[ 8.719595] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10814 00:42:57.129107 <6>[ 8.727597] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10815 00:42:57.132414 <6>[ 8.735597] pci 0000:00:00.0: PCI bridge to [bus 01]
10816 00:42:57.142747 <6>[ 8.740813] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10817 00:42:57.148832 <6>[ 8.748956] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10818 00:42:57.155705 <6>[ 8.755801] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10819 00:42:57.162389 <6>[ 8.762228] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10820 00:42:57.177611 <5>[ 8.776013] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10821 00:42:57.200298 <5>[ 8.798823] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10822 00:42:57.207157 <5>[ 8.806232] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10823 00:42:57.217447 <4>[ 8.814741] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10824 00:42:57.220438 <6>[ 8.823630] cfg80211: failed to load regulatory.db
10825 00:42:57.269941 <6>[ 8.868197] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10826 00:42:57.276333 <6>[ 8.875706] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10827 00:42:57.300777 <6>[ 8.902412] mt7921e 0000:01:00.0: ASIC revision: 79610010
10828 00:42:57.403927 <6>[ 9.002421] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10829 00:42:57.407177 <6>[ 9.002421]
10830 00:42:57.421973 Begin: Loading essential drivers ... done.
10831 00:42:57.425216 Begin: Running /scripts/init-premount ... done.
10832 00:42:57.431900 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10833 00:42:57.441963 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10834 00:42:57.445026 Device /sys/class/net/eth0 found
10835 00:42:57.445543 done.
10836 00:42:57.464924 Begin: Waiting up to 180 secs for any network device to become available ... done.
10837 00:42:57.521242 IP-Config: eth0 hardware address 00:e0:4c:72:2d:d6 mtu 1500 DHCP
10838 00:42:57.527818 IP-Config: eth0 complete (dhcp from 192.168.201.1):
10839 00:42:57.534537 address: 192.168.201.21 broadcast: 192.168.201.255 netmask: 255.255.255.0
10840 00:42:57.541141 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10841 00:42:57.547617 host : mt8192-asurada-spherion-r0-cbg-1
10842 00:42:57.554633 domain : lava-rack
10843 00:42:57.557503 rootserver: 192.168.201.1 rootpath:
10844 00:42:57.557993 filename :
10845 00:42:57.671210 <6>[ 9.269958] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10846 00:42:57.728367 done.
10847 00:42:57.736797 Begin: Running /scripts/nfs-bottom ... done.
10848 00:42:57.758618 Begin: Running /scripts/init-bottom ... done.
10849 00:42:59.085032 <6>[ 10.686800] NET: Registered PF_INET6 protocol family
10850 00:42:59.091955 <6>[ 10.693966] Segment Routing with IPv6
10851 00:42:59.095235 <6>[ 10.697929] In-situ OAM (IOAM) with IPv6
10852 00:42:59.261843 <30>[ 10.837157] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10853 00:42:59.268360 <30>[ 10.870329] systemd[1]: Detected architecture arm64.
10854 00:42:59.276652
10855 00:42:59.280294 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10856 00:42:59.280904
10857 00:42:59.301963 <30>[ 10.904028] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10858 00:43:00.379980 <30>[ 11.978702] systemd[1]: Queued start job for default target graphical.target.
10859 00:43:00.425644 <30>[ 12.024133] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10860 00:43:00.432222 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10861 00:43:00.453888 <30>[ 12.052560] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10862 00:43:00.464205 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10863 00:43:00.481850 <30>[ 12.080516] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10864 00:43:00.491980 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10865 00:43:00.509761 <30>[ 12.108107] systemd[1]: Created slice user.slice - User and Session Slice.
10866 00:43:00.515884 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10867 00:43:00.540156 <30>[ 12.135564] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10868 00:43:00.549875 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10869 00:43:00.567564 <30>[ 12.162929] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10870 00:43:00.574149 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10871 00:43:00.602753 <30>[ 12.191358] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10872 00:43:00.612446 <30>[ 12.211250] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10873 00:43:00.619355 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10874 00:43:00.636812 <30>[ 12.235108] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10875 00:43:00.646228 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10876 00:43:00.660428 <30>[ 12.258810] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10877 00:43:00.669872 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10878 00:43:00.684876 <30>[ 12.286827] systemd[1]: Reached target paths.target - Path Units.
10879 00:43:00.691977 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10880 00:43:00.712329 <30>[ 12.310754] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10881 00:43:00.718757 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10882 00:43:00.732588 <30>[ 12.334776] systemd[1]: Reached target slices.target - Slice Units.
10883 00:43:00.742653 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10884 00:43:00.756872 <30>[ 12.358761] systemd[1]: Reached target swap.target - Swaps.
10885 00:43:00.763441 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10886 00:43:00.779953 <30>[ 12.378788] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10887 00:43:00.789840 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10888 00:43:00.809004 <30>[ 12.407634] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10889 00:43:00.818915 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10890 00:43:00.838753 <30>[ 12.437726] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10891 00:43:00.849009 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10892 00:43:00.865542 <30>[ 12.464000] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10893 00:43:00.875069 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10894 00:43:00.892671 <30>[ 12.491320] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10895 00:43:00.899173 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10896 00:43:00.917885 <30>[ 12.516189] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10897 00:43:00.927520 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10898 00:43:00.946754 <30>[ 12.545433] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10899 00:43:00.956330 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10900 00:43:00.972745 <30>[ 12.571152] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10901 00:43:00.982176 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10902 00:43:01.032145 <30>[ 12.630896] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10903 00:43:01.038833 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10904 00:43:01.060085 <30>[ 12.658634] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10905 00:43:01.066443 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10906 00:43:01.089602 <30>[ 12.688516] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10907 00:43:01.096181 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10908 00:43:01.122921 <30>[ 12.715271] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10909 00:43:01.136913 <30>[ 12.735766] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10910 00:43:01.146974 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10911 00:43:01.169478 <30>[ 12.768029] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10912 00:43:01.176089 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10913 00:43:01.201456 <30>[ 12.800252] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10914 00:43:01.208089 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10915 00:43:01.234181 <30>[ 12.832590] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10916 00:43:01.240472 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10917 00:43:01.250373 <6>[ 12.846721] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10918 00:43:01.251082
10919 00:43:01.264656 <30>[ 12.863217] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10920 00:43:01.274376 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10921 00:43:01.298212 <30>[ 12.896834] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10922 00:43:01.304506 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10923 00:43:01.329773 <30>[ 12.928519] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10924 00:43:01.339480 Starting [0;1;39mmodprobe@loop.ser…e<6>[ 12.940662] fuse: init (API version 7.37)
10925 00:43:01.342918 [0m - Load Kernel Module loop...
10926 00:43:01.368964 <30>[ 12.968108] systemd[1]: Starting systemd-journald.service - Journal Service...
10927 00:43:01.375353 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10928 00:43:01.420850 <30>[ 13.020092] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10929 00:43:01.428009 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10930 00:43:01.457493 <30>[ 13.052771] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10931 00:43:01.463910 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10932 00:43:01.505012 <30>[ 13.103848] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10933 00:43:01.514488 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10934 00:43:01.539755 <30>[ 13.138163] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10935 00:43:01.545914 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10936 00:43:01.573743 <30>[ 13.172648] systemd[1]: Started systemd-journald.service - Journal Service.
10937 00:43:01.580090 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10938 00:43:01.604796 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10939 00:43:01.624692 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10940 00:43:01.645534 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10941 00:43:01.666081 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10942 00:43:01.687129 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10943 00:43:01.706517 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10944 00:43:01.725868 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10945 00:43:01.745053 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10946 00:43:01.765073 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
10947 00:43:01.791227 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10948 00:43:01.814116 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10949 00:43:01.837599 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10950 00:43:01.858000 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
10951 00:43:01.876931 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10952 00:43:01.928514 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
10953 00:43:01.953799 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10954 00:43:01.978289 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10955 00:43:02.002044 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10956 00:43:02.030109 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10957 00:43:02.057605 Starting [0;1;39msyste<46>[ 13.656188] systemd-journald[311]: Received client request to flush runtime journal.
10958 00:43:02.061177 md-sysusers.…rvice[0m - Create System Users...
10959 00:43:02.098925 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10960 00:43:02.116502 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
10961 00:43:02.136570 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10962 00:43:02.157193 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10963 00:43:02.177771 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10964 00:43:02.826279 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10965 00:43:02.872326 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10966 00:43:03.458709 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10967 00:43:03.497307 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10968 00:43:03.516139 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10969 00:43:03.532058 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10970 00:43:03.584036 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10971 00:43:03.609344 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10972 00:43:03.823867 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10973 00:43:03.869794 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
10974 00:43:03.953462 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10975 00:43:04.255511 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10976 00:43:04.273268 <6>[ 15.876359] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10977 00:43:04.298424 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
10978 00:43:04.352182 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
10979 00:43:04.461716 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10980 00:43:04.485997 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10981 00:43:04.505201 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
10982 00:43:04.526538 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
10983 00:43:04.608544 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10984 00:43:04.632315 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10985 00:43:04.660099 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
10986 00:43:04.676303 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
10987 00:43:04.696000 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10988 00:43:04.711880 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10989 00:43:04.728180 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
10990 00:43:04.753398 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
10991 00:43:04.775334 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
10992 00:43:04.792185 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
10993 00:43:04.811150 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
10994 00:43:04.831258 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
10995 00:43:04.847302 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
10996 00:43:04.866238 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
10997 00:43:04.884454 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
10998 00:43:04.904751 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
10999 00:43:04.925324 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
11000 00:43:04.962271 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11001 00:43:05.002305 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
11002 00:43:05.082126 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11003 00:43:05.108341 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11004 00:43:05.139176 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11005 00:43:05.185391 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11006 00:43:05.229871 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11007 00:43:05.256829 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11008 00:43:05.280940 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11009 00:43:05.324587 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11010 00:43:05.367482 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11011 00:43:05.386971 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11012 00:43:05.448742 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
11013 00:43:05.473930 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11014 00:43:05.492010 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11015 00:43:05.537433 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11016 00:43:05.589143 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11017 00:43:05.698733
11018 00:43:05.701584 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11019 00:43:05.702055
11020 00:43:05.705078 debian-bookworm-arm64 login: root (automatic login)
11021 00:43:05.705546
11022 00:43:06.023099 Linux debian-bookworm-arm64 6.1.92-cip22 #1 SMP PREEMPT Sun Jun 16 00:28:47 UTC 2024 aarch64
11023 00:43:06.023249
11024 00:43:06.029607 The programs included with the Debian GNU/Linux system are free software;
11025 00:43:06.036590 the exact distribution terms for each program are described in the
11026 00:43:06.039592 individual files in /usr/share/doc/*/copyright.
11027 00:43:06.039739
11028 00:43:06.046099 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11029 00:43:06.049615 permitted by applicable law.
11030 00:43:07.050144 Matched prompt #10: / #
11032 00:43:07.051296 Setting prompt string to ['/ #']
11033 00:43:07.051723 end: 2.2.5.1 login-action (duration 00:00:19) [common]
11035 00:43:07.052708 end: 2.2.5 auto-login-action (duration 00:00:19) [common]
11036 00:43:07.053155 start: 2.2.6 expect-shell-connection (timeout 00:03:43) [common]
11037 00:43:07.053505 Setting prompt string to ['/ #']
11038 00:43:07.053808 Forcing a shell prompt, looking for ['/ #']
11040 00:43:07.104576 / #
11041 00:43:07.104914 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11042 00:43:07.105121 Waiting using forced prompt support (timeout 00:02:30)
11043 00:43:07.110383
11044 00:43:07.110999 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11045 00:43:07.111295 start: 2.2.7 export-device-env (timeout 00:03:43) [common]
11047 00:43:07.212331 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14368384/extract-nfsrootfs-s_fvawcb'
11048 00:43:07.218958 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14368384/extract-nfsrootfs-s_fvawcb'
11050 00:43:07.320772 / # export NFS_SERVER_IP='192.168.201.1'
11051 00:43:07.327135 export NFS_SERVER_IP='192.168.201.1'
11052 00:43:07.328067 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11053 00:43:07.328640 end: 2.2 depthcharge-retry (duration 00:01:17) [common]
11054 00:43:07.329166 end: 2 depthcharge-action (duration 00:01:17) [common]
11055 00:43:07.329749 start: 3 lava-test-retry (timeout 00:08:05) [common]
11056 00:43:07.330246 start: 3.1 lava-test-shell (timeout 00:08:05) [common]
11057 00:43:07.330664 Using namespace: common
11059 00:43:07.431984 / # #
11060 00:43:07.432705 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11061 00:43:07.438553 #
11062 00:43:07.439431 Using /lava-14368384
11064 00:43:07.540680 / # export SHELL=/bin/bash
11065 00:43:07.546961 export SHELL=/bin/bash
11067 00:43:07.648636 / # . /lava-14368384/environment
11068 00:43:07.655121 . /lava-14368384/environment
11070 00:43:07.762417 / # /lava-14368384/bin/lava-test-runner /lava-14368384/0
11071 00:43:07.763110 Test shell timeout: 10s (minimum of the action and connection timeout)
11072 00:43:07.768762 /lava-14368384/bin/lava-test-runner /lava-14368384/0
11073 00:43:08.011069 + export TESTRUN_ID=0_timesync-off
11074 00:43:08.014146 + TESTRUN_ID=0_timesync-off
11075 00:43:08.017481 + cd /lava-14368384/0/tests/0_timesync-off
11076 00:43:08.020919 ++ cat uuid
11077 00:43:08.023967 + UUID=14368384_1.6.2.3.1
11078 00:43:08.024391 + set +x
11079 00:43:08.030539 <LAVA_SIGNAL_STARTRUN 0_timesync-off 14368384_1.6.2.3.1>
11080 00:43:08.031252 Received signal: <STARTRUN> 0_timesync-off 14368384_1.6.2.3.1
11081 00:43:08.031655 Starting test lava.0_timesync-off (14368384_1.6.2.3.1)
11082 00:43:08.032071 Skipping test definition patterns.
11083 00:43:08.034001 + systemctl stop systemd-timesyncd
11084 00:43:08.095804 + set +x
11085 00:43:08.099004 <LAVA_SIGNAL_ENDRUN 0_timesync-off 14368384_1.6.2.3.1>
11086 00:43:08.099741 Received signal: <ENDRUN> 0_timesync-off 14368384_1.6.2.3.1
11087 00:43:08.100171 Ending use of test pattern.
11088 00:43:08.100494 Ending test lava.0_timesync-off (14368384_1.6.2.3.1), duration 0.07
11090 00:43:08.170051 + export TESTRUN_ID=1_kselftest-alsa
11091 00:43:08.173205 + TESTRUN_ID=1_kselftest-alsa
11092 00:43:08.179626 + cd /lava-14368384/0/tests/1_kselftest-alsa
11093 00:43:08.180056 ++ cat uuid
11094 00:43:08.184293 + UUID=14368384_1.6.2.3.5
11095 00:43:08.184759 + set +x
11096 00:43:08.191385 <LAVA_SIGNAL_STARTRUN 1_kselftest-alsa 14368384_1.6.2.3.5>
11097 00:43:08.192057 Received signal: <STARTRUN> 1_kselftest-alsa 14368384_1.6.2.3.5
11098 00:43:08.192405 Starting test lava.1_kselftest-alsa (14368384_1.6.2.3.5)
11099 00:43:08.192830 Skipping test definition patterns.
11100 00:43:08.194300 + cd ./automated/linux/kselftest/
11101 00:43:08.221030 + ./kselftest.sh -c alsa -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-24-g0315de64ea248/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11102 00:43:08.260273 INFO: install_deps skipped
11103 00:43:08.765042 --2024-06-16 00:41:43-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-24-g0315de64ea248/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11104 00:43:08.779176 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11105 00:43:08.904388 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11106 00:43:09.029343 HTTP request sent, awaiting response... 200 OK
11107 00:43:09.032541 Length: 1647580 (1.6M) [application/octet-stream]
11108 00:43:09.036329 Saving to: 'kselftest_armhf.tar.gz'
11109 00:43:09.036988
11110 00:43:09.037364
11111 00:43:09.278722 kselftest_armhf.tar 0%[ ] 0 --.-KB/s
11112 00:43:09.528671 kselftest_armhf.tar 2%[ ] 46.39K 186KB/s
11113 00:43:09.825522 kselftest_armhf.tar 13%[=> ] 218.91K 439KB/s
11114 00:43:09.952406 kselftest_armhf.tar 50%[=========> ] 812.82K 1021KB/s
11115 00:43:09.959075 kselftest_armhf.tar 100%[===================>] 1.57M 1.70MB/s in 0.9s
11116 00:43:09.959501
11117 00:43:10.102573 2024-06-16 00:41:44 (1.70 MB/s) - 'kselftest_armhf.tar.gz' saved [1647580/1647580]
11118 00:43:10.102717
11119 00:43:13.692832 skiplist:
11120 00:43:13.696202 ========================================
11121 00:43:13.699334 ========================================
11122 00:43:13.737954 alsa:mixer-test
11123 00:43:13.756935 ============== Tests to run ===============
11124 00:43:13.757048 alsa:mixer-test
11125 00:43:13.760310 ===========End Tests to run ===============
11126 00:43:13.763219 shardfile-alsa pass
11127 00:43:13.858440 <12>[ 25.462794] kselftest: Running tests in alsa
11128 00:43:13.868137 TAP version 13
11129 00:43:13.880145 1..1
11130 00:43:13.892496 # selftests: alsa: mixer-test
11131 00:43:14.373788 # TAP version 13
11132 00:43:14.373952 # 1..0
11133 00:43:14.379993 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:0 error:0
11134 00:43:14.383285 ok 1 selftests: alsa: mixer-test
11135 00:43:15.780891 alsa_mixer-test pass
11136 00:43:15.856638 + ../../utils/send-to-lava.sh ./output/result.txt
11137 00:43:15.913217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-alsa RESULT=pass>
11138 00:43:15.913517 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-alsa RESULT=pass
11140 00:43:15.949151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test RESULT=pass>
11141 00:43:15.949255 + set +x
11142 00:43:15.949495 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test RESULT=pass
11144 00:43:15.955928 <LAVA_SIGNAL_ENDRUN 1_kselftest-alsa 14368384_1.6.2.3.5>
11145 00:43:15.956182 Received signal: <ENDRUN> 1_kselftest-alsa 14368384_1.6.2.3.5
11146 00:43:15.956258 Ending use of test pattern.
11147 00:43:15.956322 Ending test lava.1_kselftest-alsa (14368384_1.6.2.3.5), duration 7.76
11149 00:43:15.959251 <LAVA_TEST_RUNNER EXIT>
11150 00:43:15.959506 ok: lava_test_shell seems to have completed
11151 00:43:15.959610 alsa_mixer-test: pass
shardfile-alsa: pass
11152 00:43:15.959703 end: 3.1 lava-test-shell (duration 00:00:09) [common]
11153 00:43:15.959787 end: 3 lava-test-retry (duration 00:00:09) [common]
11154 00:43:15.959874 start: 4 finalize (timeout 00:07:56) [common]
11155 00:43:15.959967 start: 4.1 power-off (timeout 00:00:30) [common]
11156 00:43:15.960121 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-1', '--port=1', '--command=off']
11157 00:43:16.159915 >> Command sent successfully.
11158 00:43:16.162221 Returned 0 in 0 seconds
11159 00:43:16.262579 end: 4.1 power-off (duration 00:00:00) [common]
11161 00:43:16.262869 start: 4.2 read-feedback (timeout 00:07:56) [common]
11162 00:43:16.263115 Listened to connection for namespace 'common' for up to 1s
11163 00:43:17.264107 Finalising connection for namespace 'common'
11164 00:43:17.264294 Disconnecting from shell: Finalise
11165 00:43:17.264371 / #
11166 00:43:17.364707 end: 4.2 read-feedback (duration 00:00:01) [common]
11167 00:43:17.364864 end: 4 finalize (duration 00:00:01) [common]
11168 00:43:17.364984 Cleaning after the job
11169 00:43:17.365098 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14368384/tftp-deploy-28dj6z9m/ramdisk
11170 00:43:17.367230 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14368384/tftp-deploy-28dj6z9m/kernel
11171 00:43:17.377826 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14368384/tftp-deploy-28dj6z9m/dtb
11172 00:43:17.378006 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14368384/tftp-deploy-28dj6z9m/nfsrootfs
11173 00:43:17.439107 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14368384/tftp-deploy-28dj6z9m/modules
11174 00:43:17.444609 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14368384
11175 00:43:17.952109 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14368384
11176 00:43:17.952294 Job finished correctly