Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 31
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 25
1 00:42:56.023745 lava-dispatcher, installed at version: 2024.03
2 00:42:56.023946 start: 0 validate
3 00:42:56.024075 Start time: 2024-06-16 00:42:56.024068+00:00 (UTC)
4 00:42:56.024190 Using caching service: 'http://localhost/cache/?uri=%s'
5 00:42:56.024317 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 00:42:56.294689 Using caching service: 'http://localhost/cache/?uri=%s'
7 00:42:56.295359 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22-24-g0315de64ea248%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 00:42:56.549847 Using caching service: 'http://localhost/cache/?uri=%s'
9 00:42:56.550624 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22-24-g0315de64ea248%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 00:42:56.804420 Using caching service: 'http://localhost/cache/?uri=%s'
11 00:42:56.805042 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 00:42:57.060433 Using caching service: 'http://localhost/cache/?uri=%s'
13 00:42:57.061170 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22-24-g0315de64ea248%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 00:42:57.321782 validate duration: 1.30
16 00:42:57.323041 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 00:42:57.323568 start: 1.1 download-retry (timeout 00:10:00) [common]
18 00:42:57.324198 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 00:42:57.324798 Not decompressing ramdisk as can be used compressed.
20 00:42:57.325234 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 00:42:57.325572 saving as /var/lib/lava/dispatcher/tmp/14368400/tftp-deploy-4dnvlh_0/ramdisk/initrd.cpio.gz
22 00:42:57.325906 total size: 5628169 (5 MB)
23 00:42:57.330766 progress 0 % (0 MB)
24 00:42:57.338800 progress 5 % (0 MB)
25 00:42:57.346361 progress 10 % (0 MB)
26 00:42:57.350681 progress 15 % (0 MB)
27 00:42:57.354650 progress 20 % (1 MB)
28 00:42:57.357679 progress 25 % (1 MB)
29 00:42:57.360704 progress 30 % (1 MB)
30 00:42:57.363520 progress 35 % (1 MB)
31 00:42:57.365682 progress 40 % (2 MB)
32 00:42:57.368089 progress 45 % (2 MB)
33 00:42:57.370090 progress 50 % (2 MB)
34 00:42:57.372207 progress 55 % (2 MB)
35 00:42:57.374249 progress 60 % (3 MB)
36 00:42:57.375926 progress 65 % (3 MB)
37 00:42:57.377803 progress 70 % (3 MB)
38 00:42:57.379428 progress 75 % (4 MB)
39 00:42:57.381123 progress 80 % (4 MB)
40 00:42:57.382643 progress 85 % (4 MB)
41 00:42:57.384291 progress 90 % (4 MB)
42 00:42:57.385848 progress 95 % (5 MB)
43 00:42:57.387255 progress 100 % (5 MB)
44 00:42:57.387465 5 MB downloaded in 0.06 s (87.16 MB/s)
45 00:42:57.387617 end: 1.1.1 http-download (duration 00:00:00) [common]
47 00:42:57.387864 end: 1.1 download-retry (duration 00:00:00) [common]
48 00:42:57.387950 start: 1.2 download-retry (timeout 00:10:00) [common]
49 00:42:57.388035 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 00:42:57.388172 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-24-g0315de64ea248/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 00:42:57.388251 saving as /var/lib/lava/dispatcher/tmp/14368400/tftp-deploy-4dnvlh_0/kernel/Image
52 00:42:57.388326 total size: 54813184 (52 MB)
53 00:42:57.388388 No compression specified
54 00:42:57.389523 progress 0 % (0 MB)
55 00:42:57.403363 progress 5 % (2 MB)
56 00:42:57.417288 progress 10 % (5 MB)
57 00:42:57.431001 progress 15 % (7 MB)
58 00:42:57.444949 progress 20 % (10 MB)
59 00:42:57.458782 progress 25 % (13 MB)
60 00:42:57.472506 progress 30 % (15 MB)
61 00:42:57.486351 progress 35 % (18 MB)
62 00:42:57.500185 progress 40 % (20 MB)
63 00:42:57.513946 progress 45 % (23 MB)
64 00:42:57.527867 progress 50 % (26 MB)
65 00:42:57.541677 progress 55 % (28 MB)
66 00:42:57.555410 progress 60 % (31 MB)
67 00:42:57.569297 progress 65 % (34 MB)
68 00:42:57.582969 progress 70 % (36 MB)
69 00:42:57.596734 progress 75 % (39 MB)
70 00:42:57.610660 progress 80 % (41 MB)
71 00:42:57.624347 progress 85 % (44 MB)
72 00:42:57.638057 progress 90 % (47 MB)
73 00:42:57.651774 progress 95 % (49 MB)
74 00:42:57.665191 progress 100 % (52 MB)
75 00:42:57.665416 52 MB downloaded in 0.28 s (188.66 MB/s)
76 00:42:57.665567 end: 1.2.1 http-download (duration 00:00:00) [common]
78 00:42:57.665799 end: 1.2 download-retry (duration 00:00:00) [common]
79 00:42:57.665885 start: 1.3 download-retry (timeout 00:10:00) [common]
80 00:42:57.665969 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 00:42:57.666104 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-24-g0315de64ea248/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 00:42:57.666204 saving as /var/lib/lava/dispatcher/tmp/14368400/tftp-deploy-4dnvlh_0/dtb/mt8192-asurada-spherion-r0.dtb
83 00:42:57.666294 total size: 47258 (0 MB)
84 00:42:57.666355 No compression specified
85 00:42:57.667485 progress 69 % (0 MB)
86 00:42:57.667752 progress 100 % (0 MB)
87 00:42:57.667906 0 MB downloaded in 0.00 s (28.00 MB/s)
88 00:42:57.668027 end: 1.3.1 http-download (duration 00:00:00) [common]
90 00:42:57.668258 end: 1.3 download-retry (duration 00:00:00) [common]
91 00:42:57.668345 start: 1.4 download-retry (timeout 00:10:00) [common]
92 00:42:57.668427 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 00:42:57.668537 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 00:42:57.668604 saving as /var/lib/lava/dispatcher/tmp/14368400/tftp-deploy-4dnvlh_0/nfsrootfs/full.rootfs.tar
95 00:42:57.668678 total size: 120894716 (115 MB)
96 00:42:57.668740 Using unxz to decompress xz
97 00:42:57.672511 progress 0 % (0 MB)
98 00:42:58.013204 progress 5 % (5 MB)
99 00:42:58.363037 progress 10 % (11 MB)
100 00:42:58.713877 progress 15 % (17 MB)
101 00:42:59.051375 progress 20 % (23 MB)
102 00:42:59.348421 progress 25 % (28 MB)
103 00:42:59.708033 progress 30 % (34 MB)
104 00:43:00.047628 progress 35 % (40 MB)
105 00:43:00.213659 progress 40 % (46 MB)
106 00:43:00.393386 progress 45 % (51 MB)
107 00:43:00.705267 progress 50 % (57 MB)
108 00:43:01.081019 progress 55 % (63 MB)
109 00:43:01.425285 progress 60 % (69 MB)
110 00:43:01.773545 progress 65 % (74 MB)
111 00:43:02.119394 progress 70 % (80 MB)
112 00:43:02.478473 progress 75 % (86 MB)
113 00:43:02.820170 progress 80 % (92 MB)
114 00:43:03.165173 progress 85 % (98 MB)
115 00:43:03.520789 progress 90 % (103 MB)
116 00:43:03.847061 progress 95 % (109 MB)
117 00:43:04.209467 progress 100 % (115 MB)
118 00:43:04.214937 115 MB downloaded in 6.55 s (17.61 MB/s)
119 00:43:04.215191 end: 1.4.1 http-download (duration 00:00:07) [common]
121 00:43:04.215457 end: 1.4 download-retry (duration 00:00:07) [common]
122 00:43:04.215551 start: 1.5 download-retry (timeout 00:09:53) [common]
123 00:43:04.215640 start: 1.5.1 http-download (timeout 00:09:53) [common]
124 00:43:04.215789 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-24-g0315de64ea248/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 00:43:04.215863 saving as /var/lib/lava/dispatcher/tmp/14368400/tftp-deploy-4dnvlh_0/modules/modules.tar
126 00:43:04.215924 total size: 8608736 (8 MB)
127 00:43:04.215988 Using unxz to decompress xz
128 00:43:04.219892 progress 0 % (0 MB)
129 00:43:04.239034 progress 5 % (0 MB)
130 00:43:04.266591 progress 10 % (0 MB)
131 00:43:04.296715 progress 15 % (1 MB)
132 00:43:04.320787 progress 20 % (1 MB)
133 00:43:04.344508 progress 25 % (2 MB)
134 00:43:04.368585 progress 30 % (2 MB)
135 00:43:04.393383 progress 35 % (2 MB)
136 00:43:04.420427 progress 40 % (3 MB)
137 00:43:04.443285 progress 45 % (3 MB)
138 00:43:04.467432 progress 50 % (4 MB)
139 00:43:04.493583 progress 55 % (4 MB)
140 00:43:04.518990 progress 60 % (4 MB)
141 00:43:04.543727 progress 65 % (5 MB)
142 00:43:04.568588 progress 70 % (5 MB)
143 00:43:04.594631 progress 75 % (6 MB)
144 00:43:04.621137 progress 80 % (6 MB)
145 00:43:04.647667 progress 85 % (7 MB)
146 00:43:04.673114 progress 90 % (7 MB)
147 00:43:04.699224 progress 95 % (7 MB)
148 00:43:04.726226 progress 100 % (8 MB)
149 00:43:04.732109 8 MB downloaded in 0.52 s (15.91 MB/s)
150 00:43:04.732361 end: 1.5.1 http-download (duration 00:00:01) [common]
152 00:43:04.732623 end: 1.5 download-retry (duration 00:00:01) [common]
153 00:43:04.732716 start: 1.6 prepare-tftp-overlay (timeout 00:09:53) [common]
154 00:43:04.732811 start: 1.6.1 extract-nfsrootfs (timeout 00:09:53) [common]
155 00:43:08.187023 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/14368400/extract-nfsrootfs-x3fw3_sq
156 00:43:08.187224 end: 1.6.1 extract-nfsrootfs (duration 00:00:03) [common]
157 00:43:08.187326 start: 1.6.2 lava-overlay (timeout 00:09:49) [common]
158 00:43:08.187494 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14368400/lava-overlay-aqw1f_8v
159 00:43:08.187623 makedir: /var/lib/lava/dispatcher/tmp/14368400/lava-overlay-aqw1f_8v/lava-14368400/bin
160 00:43:08.187759 makedir: /var/lib/lava/dispatcher/tmp/14368400/lava-overlay-aqw1f_8v/lava-14368400/tests
161 00:43:08.187857 makedir: /var/lib/lava/dispatcher/tmp/14368400/lava-overlay-aqw1f_8v/lava-14368400/results
162 00:43:08.187958 Creating /var/lib/lava/dispatcher/tmp/14368400/lava-overlay-aqw1f_8v/lava-14368400/bin/lava-add-keys
163 00:43:08.188102 Creating /var/lib/lava/dispatcher/tmp/14368400/lava-overlay-aqw1f_8v/lava-14368400/bin/lava-add-sources
164 00:43:08.188230 Creating /var/lib/lava/dispatcher/tmp/14368400/lava-overlay-aqw1f_8v/lava-14368400/bin/lava-background-process-start
165 00:43:08.188357 Creating /var/lib/lava/dispatcher/tmp/14368400/lava-overlay-aqw1f_8v/lava-14368400/bin/lava-background-process-stop
166 00:43:08.188482 Creating /var/lib/lava/dispatcher/tmp/14368400/lava-overlay-aqw1f_8v/lava-14368400/bin/lava-common-functions
167 00:43:08.188605 Creating /var/lib/lava/dispatcher/tmp/14368400/lava-overlay-aqw1f_8v/lava-14368400/bin/lava-echo-ipv4
168 00:43:08.188728 Creating /var/lib/lava/dispatcher/tmp/14368400/lava-overlay-aqw1f_8v/lava-14368400/bin/lava-install-packages
169 00:43:08.188851 Creating /var/lib/lava/dispatcher/tmp/14368400/lava-overlay-aqw1f_8v/lava-14368400/bin/lava-installed-packages
170 00:43:08.188972 Creating /var/lib/lava/dispatcher/tmp/14368400/lava-overlay-aqw1f_8v/lava-14368400/bin/lava-os-build
171 00:43:08.189094 Creating /var/lib/lava/dispatcher/tmp/14368400/lava-overlay-aqw1f_8v/lava-14368400/bin/lava-probe-channel
172 00:43:08.189216 Creating /var/lib/lava/dispatcher/tmp/14368400/lava-overlay-aqw1f_8v/lava-14368400/bin/lava-probe-ip
173 00:43:08.189346 Creating /var/lib/lava/dispatcher/tmp/14368400/lava-overlay-aqw1f_8v/lava-14368400/bin/lava-target-ip
174 00:43:08.189469 Creating /var/lib/lava/dispatcher/tmp/14368400/lava-overlay-aqw1f_8v/lava-14368400/bin/lava-target-mac
175 00:43:08.189590 Creating /var/lib/lava/dispatcher/tmp/14368400/lava-overlay-aqw1f_8v/lava-14368400/bin/lava-target-storage
176 00:43:08.189762 Creating /var/lib/lava/dispatcher/tmp/14368400/lava-overlay-aqw1f_8v/lava-14368400/bin/lava-test-case
177 00:43:08.189929 Creating /var/lib/lava/dispatcher/tmp/14368400/lava-overlay-aqw1f_8v/lava-14368400/bin/lava-test-event
178 00:43:08.190056 Creating /var/lib/lava/dispatcher/tmp/14368400/lava-overlay-aqw1f_8v/lava-14368400/bin/lava-test-feedback
179 00:43:08.190350 Creating /var/lib/lava/dispatcher/tmp/14368400/lava-overlay-aqw1f_8v/lava-14368400/bin/lava-test-raise
180 00:43:08.190480 Creating /var/lib/lava/dispatcher/tmp/14368400/lava-overlay-aqw1f_8v/lava-14368400/bin/lava-test-reference
181 00:43:08.190607 Creating /var/lib/lava/dispatcher/tmp/14368400/lava-overlay-aqw1f_8v/lava-14368400/bin/lava-test-runner
182 00:43:08.190731 Creating /var/lib/lava/dispatcher/tmp/14368400/lava-overlay-aqw1f_8v/lava-14368400/bin/lava-test-set
183 00:43:08.190856 Creating /var/lib/lava/dispatcher/tmp/14368400/lava-overlay-aqw1f_8v/lava-14368400/bin/lava-test-shell
184 00:43:08.190981 Updating /var/lib/lava/dispatcher/tmp/14368400/lava-overlay-aqw1f_8v/lava-14368400/bin/lava-add-keys (debian)
185 00:43:08.191141 Updating /var/lib/lava/dispatcher/tmp/14368400/lava-overlay-aqw1f_8v/lava-14368400/bin/lava-add-sources (debian)
186 00:43:08.191279 Updating /var/lib/lava/dispatcher/tmp/14368400/lava-overlay-aqw1f_8v/lava-14368400/bin/lava-install-packages (debian)
187 00:43:08.191415 Updating /var/lib/lava/dispatcher/tmp/14368400/lava-overlay-aqw1f_8v/lava-14368400/bin/lava-installed-packages (debian)
188 00:43:08.191551 Updating /var/lib/lava/dispatcher/tmp/14368400/lava-overlay-aqw1f_8v/lava-14368400/bin/lava-os-build (debian)
189 00:43:08.191669 Creating /var/lib/lava/dispatcher/tmp/14368400/lava-overlay-aqw1f_8v/lava-14368400/environment
190 00:43:08.191765 LAVA metadata
191 00:43:08.191831 - LAVA_JOB_ID=14368400
192 00:43:08.191892 - LAVA_DISPATCHER_IP=192.168.201.1
193 00:43:08.191993 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:49) [common]
194 00:43:08.192058 skipped lava-vland-overlay
195 00:43:08.192130 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 00:43:08.192208 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:49) [common]
197 00:43:08.192268 skipped lava-multinode-overlay
198 00:43:08.192338 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 00:43:08.192428 start: 1.6.2.3 test-definition (timeout 00:09:49) [common]
200 00:43:08.192500 Loading test definitions
201 00:43:08.192588 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:49) [common]
202 00:43:08.192661 Using /lava-14368400 at stage 0
203 00:43:08.192933 uuid=14368400_1.6.2.3.1 testdef=None
204 00:43:08.193021 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 00:43:08.193103 start: 1.6.2.3.2 test-overlay (timeout 00:09:49) [common]
206 00:43:08.193551 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 00:43:08.193772 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:49) [common]
209 00:43:08.194325 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 00:43:08.194552 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:49) [common]
212 00:43:08.195082 runner path: /var/lib/lava/dispatcher/tmp/14368400/lava-overlay-aqw1f_8v/lava-14368400/0/tests/0_timesync-off test_uuid 14368400_1.6.2.3.1
213 00:43:08.195239 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 00:43:08.195464 start: 1.6.2.3.5 git-repo-action (timeout 00:09:49) [common]
216 00:43:08.195536 Using /lava-14368400 at stage 0
217 00:43:08.195632 Fetching tests from https://github.com/kernelci/test-definitions.git
218 00:43:08.195718 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/14368400/lava-overlay-aqw1f_8v/lava-14368400/0/tests/1_kselftest-arm64'
219 00:43:10.672779 Running '/usr/bin/git checkout kernelci.org
220 00:43:10.819918 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/14368400/lava-overlay-aqw1f_8v/lava-14368400/0/tests/1_kselftest-arm64/automated/linux/kselftest/kselftest.yaml
221 00:43:10.820659 uuid=14368400_1.6.2.3.5 testdef=None
222 00:43:10.820819 end: 1.6.2.3.5 git-repo-action (duration 00:00:03) [common]
224 00:43:10.821069 start: 1.6.2.3.6 test-overlay (timeout 00:09:47) [common]
225 00:43:10.821842 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 00:43:10.822079 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:47) [common]
228 00:43:10.823209 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 00:43:10.823452 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:46) [common]
231 00:43:10.824374 runner path: /var/lib/lava/dispatcher/tmp/14368400/lava-overlay-aqw1f_8v/lava-14368400/0/tests/1_kselftest-arm64 test_uuid 14368400_1.6.2.3.5
232 00:43:10.824467 BOARD='mt8192-asurada-spherion-r0'
233 00:43:10.824531 BRANCH='cip'
234 00:43:10.824590 SKIPFILE='/dev/null'
235 00:43:10.824649 SKIP_INSTALL='True'
236 00:43:10.824705 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-24-g0315de64ea248/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 00:43:10.824770 TST_CASENAME=''
238 00:43:10.824868 TST_CMDFILES='arm64'
239 00:43:10.825089 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 00:43:10.825301 Creating lava-test-runner.conf files
242 00:43:10.825367 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14368400/lava-overlay-aqw1f_8v/lava-14368400/0 for stage 0
243 00:43:10.825462 - 0_timesync-off
244 00:43:10.825531 - 1_kselftest-arm64
245 00:43:10.825626 end: 1.6.2.3 test-definition (duration 00:00:03) [common]
246 00:43:10.825716 start: 1.6.2.4 compress-overlay (timeout 00:09:46) [common]
247 00:43:18.352957 end: 1.6.2.4 compress-overlay (duration 00:00:08) [common]
248 00:43:18.353104 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:39) [common]
249 00:43:18.353193 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 00:43:18.353292 end: 1.6.2 lava-overlay (duration 00:00:10) [common]
251 00:43:18.353381 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:39) [common]
252 00:43:18.519824 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 00:43:18.520242 start: 1.6.4 extract-modules (timeout 00:09:39) [common]
254 00:43:18.520391 extracting modules file /var/lib/lava/dispatcher/tmp/14368400/tftp-deploy-4dnvlh_0/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14368400/extract-nfsrootfs-x3fw3_sq
255 00:43:18.746343 extracting modules file /var/lib/lava/dispatcher/tmp/14368400/tftp-deploy-4dnvlh_0/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14368400/extract-overlay-ramdisk-vccpr4je/ramdisk
256 00:43:18.967709 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 00:43:18.967875 start: 1.6.5 apply-overlay-tftp (timeout 00:09:38) [common]
258 00:43:18.967972 [common] Applying overlay to NFS
259 00:43:18.968044 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14368400/compress-overlay-9ge27i1p/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14368400/extract-nfsrootfs-x3fw3_sq
260 00:43:19.940582 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 00:43:19.940802 start: 1.6.6 configure-preseed-file (timeout 00:09:37) [common]
262 00:43:19.940931 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 00:43:19.941060 start: 1.6.7 compress-ramdisk (timeout 00:09:37) [common]
264 00:43:19.941171 Building ramdisk /var/lib/lava/dispatcher/tmp/14368400/extract-overlay-ramdisk-vccpr4je/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14368400/extract-overlay-ramdisk-vccpr4je/ramdisk
265 00:43:20.287175 >> 130405 blocks
266 00:43:22.352554 rename /var/lib/lava/dispatcher/tmp/14368400/extract-overlay-ramdisk-vccpr4je/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14368400/tftp-deploy-4dnvlh_0/ramdisk/ramdisk.cpio.gz
267 00:43:22.353047 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 00:43:22.353216 start: 1.6.8 prepare-kernel (timeout 00:09:35) [common]
269 00:43:22.353354 start: 1.6.8.1 prepare-fit (timeout 00:09:35) [common]
270 00:43:22.353507 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14368400/tftp-deploy-4dnvlh_0/kernel/Image']
271 00:43:35.850170 Returned 0 in 13 seconds
272 00:43:35.951231 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14368400/tftp-deploy-4dnvlh_0/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14368400/tftp-deploy-4dnvlh_0/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14368400/tftp-deploy-4dnvlh_0/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14368400/tftp-deploy-4dnvlh_0/kernel/image.itb
273 00:43:36.302661 output: FIT description: Kernel Image image with one or more FDT blobs
274 00:43:36.303122 output: Created: Sun Jun 16 01:43:36 2024
275 00:43:36.303203 output: Image 0 (kernel-1)
276 00:43:36.303265 output: Description:
277 00:43:36.303330 output: Created: Sun Jun 16 01:43:36 2024
278 00:43:36.303393 output: Type: Kernel Image
279 00:43:36.303453 output: Compression: lzma compressed
280 00:43:36.303512 output: Data Size: 13126376 Bytes = 12818.73 KiB = 12.52 MiB
281 00:43:36.303569 output: Architecture: AArch64
282 00:43:36.303625 output: OS: Linux
283 00:43:36.303681 output: Load Address: 0x00000000
284 00:43:36.303734 output: Entry Point: 0x00000000
285 00:43:36.303788 output: Hash algo: crc32
286 00:43:36.303842 output: Hash value: c791a20a
287 00:43:36.303893 output: Image 1 (fdt-1)
288 00:43:36.303946 output: Description: mt8192-asurada-spherion-r0
289 00:43:36.304001 output: Created: Sun Jun 16 01:43:36 2024
290 00:43:36.304055 output: Type: Flat Device Tree
291 00:43:36.304108 output: Compression: uncompressed
292 00:43:36.304160 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
293 00:43:36.304212 output: Architecture: AArch64
294 00:43:36.304264 output: Hash algo: crc32
295 00:43:36.304316 output: Hash value: 0f8e4d2e
296 00:43:36.304367 output: Image 2 (ramdisk-1)
297 00:43:36.304418 output: Description: unavailable
298 00:43:36.304469 output: Created: Sun Jun 16 01:43:36 2024
299 00:43:36.304521 output: Type: RAMDisk Image
300 00:43:36.304573 output: Compression: Unknown Compression
301 00:43:36.304624 output: Data Size: 18742656 Bytes = 18303.38 KiB = 17.87 MiB
302 00:43:36.304676 output: Architecture: AArch64
303 00:43:36.304728 output: OS: Linux
304 00:43:36.304778 output: Load Address: unavailable
305 00:43:36.304830 output: Entry Point: unavailable
306 00:43:36.304881 output: Hash algo: crc32
307 00:43:36.304932 output: Hash value: c7b02c88
308 00:43:36.304983 output: Default Configuration: 'conf-1'
309 00:43:36.305034 output: Configuration 0 (conf-1)
310 00:43:36.305085 output: Description: mt8192-asurada-spherion-r0
311 00:43:36.305136 output: Kernel: kernel-1
312 00:43:36.305187 output: Init Ramdisk: ramdisk-1
313 00:43:36.305239 output: FDT: fdt-1
314 00:43:36.305290 output: Loadables: kernel-1
315 00:43:36.305340 output:
316 00:43:36.305535 end: 1.6.8.1 prepare-fit (duration 00:00:14) [common]
317 00:43:36.305631 end: 1.6.8 prepare-kernel (duration 00:00:14) [common]
318 00:43:36.305739 end: 1.6 prepare-tftp-overlay (duration 00:00:32) [common]
319 00:43:36.305833 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:21) [common]
320 00:43:36.305913 No LXC device requested
321 00:43:36.305990 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 00:43:36.306079 start: 1.8 deploy-device-env (timeout 00:09:21) [common]
323 00:43:36.306158 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 00:43:36.306271 Checking files for TFTP limit of 4294967296 bytes.
325 00:43:36.306757 end: 1 tftp-deploy (duration 00:00:39) [common]
326 00:43:36.306860 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 00:43:36.306965 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 00:43:36.307086 substitutions:
329 00:43:36.307157 - {DTB}: 14368400/tftp-deploy-4dnvlh_0/dtb/mt8192-asurada-spherion-r0.dtb
330 00:43:36.307221 - {INITRD}: 14368400/tftp-deploy-4dnvlh_0/ramdisk/ramdisk.cpio.gz
331 00:43:36.307280 - {KERNEL}: 14368400/tftp-deploy-4dnvlh_0/kernel/Image
332 00:43:36.307338 - {LAVA_MAC}: None
333 00:43:36.307395 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/14368400/extract-nfsrootfs-x3fw3_sq
334 00:43:36.307450 - {NFS_SERVER_IP}: 192.168.201.1
335 00:43:36.307504 - {PRESEED_CONFIG}: None
336 00:43:36.307558 - {PRESEED_LOCAL}: None
337 00:43:36.307611 - {RAMDISK}: 14368400/tftp-deploy-4dnvlh_0/ramdisk/ramdisk.cpio.gz
338 00:43:36.307665 - {ROOT_PART}: None
339 00:43:36.307717 - {ROOT}: None
340 00:43:36.307771 - {SERVER_IP}: 192.168.201.1
341 00:43:36.307823 - {TEE}: None
342 00:43:36.307876 Parsed boot commands:
343 00:43:36.307930 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 00:43:36.308105 Parsed boot commands: tftpboot 192.168.201.1 14368400/tftp-deploy-4dnvlh_0/kernel/image.itb 14368400/tftp-deploy-4dnvlh_0/kernel/cmdline
345 00:43:36.308192 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 00:43:36.308278 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 00:43:36.308369 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 00:43:36.308453 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 00:43:36.308525 Not connected, no need to disconnect.
350 00:43:36.308598 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 00:43:36.308679 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 00:43:36.308745 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-9'
353 00:43:36.312291 Setting prompt string to ['lava-test: # ']
354 00:43:36.312668 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 00:43:36.312773 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 00:43:36.312886 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 00:43:36.312981 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 00:43:36.313155 Calling: ['/usr/local/bin/chromebook-reboot.sh', 'mt8192-asurada-spherion-r0-cbg-9']
359 00:43:50.415722 Returned 0 in 14 seconds
360 00:43:50.516457 end: 2.2.2.1 pdu-reboot (duration 00:00:14) [common]
362 00:43:50.516798 end: 2.2.2 reset-device (duration 00:00:14) [common]
363 00:43:50.516902 start: 2.2.3 depthcharge-start (timeout 00:04:46) [common]
364 00:43:50.517001 Setting prompt string to 'Starting depthcharge on Spherion...'
365 00:43:50.517075 Changing prompt to 'Starting depthcharge on Spherion...'
366 00:43:50.517146 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
367 00:43:50.517565 [Enter `^Ec?' for help]
368 00:43:50.517646
369 00:43:50.517716
370 00:43:50.517790 F0: 102B 0000
371 00:43:50.517855
372 00:43:50.517915 F3: 1001 0000 [0200]
373 00:43:50.517975
374 00:43:50.518043 F3: 1001 0000
375 00:43:50.518101
376 00:43:50.518156 F7: 102D 0000
377 00:43:50.518272
378 00:43:50.518332 F1: 0000 0000
379 00:43:50.518386
380 00:43:50.518440 V0: 0000 0000 [0001]
381 00:43:50.518495
382 00:43:50.518548 00: 0007 8000
383 00:43:50.518613
384 00:43:50.518668 01: 0000 0000
385 00:43:50.518723
386 00:43:50.518819 BP: 0C00 0209 [0000]
387 00:43:50.518919
388 00:43:50.519004 G0: 1182 0000
389 00:43:50.519096
390 00:43:50.519190 EC: 0000 0021 [4000]
391 00:43:50.519269
392 00:43:50.519352 S7: 0000 0000 [0000]
393 00:43:50.519413
394 00:43:50.519472 CC: 0000 0000 [0001]
395 00:43:50.519537
396 00:43:50.519596 T0: 0000 0040 [010F]
397 00:43:50.519654
398 00:43:50.519711 Jump to BL
399 00:43:50.519775
400 00:43:50.519833
401 00:43:50.519891
402 00:43:50.519948 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
403 00:43:50.520017 ARM64: Exception handlers installed.
404 00:43:50.520080 ARM64: Testing exception
405 00:43:50.520138 ARM64: Done test exception
406 00:43:50.520195 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
407 00:43:50.520261 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
408 00:43:50.520321 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
409 00:43:50.520379 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
410 00:43:50.520438 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
411 00:43:50.520503 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
412 00:43:50.520562 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
413 00:43:50.520620 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
414 00:43:50.520678 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
415 00:43:50.520741 WDT: Last reset was cold boot
416 00:43:50.520801 SPI1(PAD0) initialized at 2873684 Hz
417 00:43:50.520858 SPI5(PAD0) initialized at 992727 Hz
418 00:43:50.520916 VBOOT: Loading verstage.
419 00:43:50.520973 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
420 00:43:50.521039 FMAP: Found "FLASH" version 1.1 at 0x20000.
421 00:43:50.521098 FMAP: base = 0x0 size = 0x800000 #areas = 25
422 00:43:50.521156 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
423 00:43:50.521214 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
424 00:43:50.521280 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
425 00:43:50.521338 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
426 00:43:50.521396
427 00:43:50.521453
428 00:43:50.521517 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
429 00:43:50.521577 ARM64: Exception handlers installed.
430 00:43:50.521634 ARM64: Testing exception
431 00:43:50.521691 ARM64: Done test exception
432 00:43:50.521755 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
433 00:43:50.521815 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
434 00:43:50.521873 Probing TPM: . done!
435 00:43:50.521930 TPM ready after 0 ms
436 00:43:50.521995 Connected to device vid:did:rid of 1ae0:0028:00
437 00:43:50.522053 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
438 00:43:50.522112 Initialized TPM device CR50 revision 0
439 00:43:50.522184 tlcl_send_startup: Startup return code is 0
440 00:43:50.522255 TPM: setup succeeded
441 00:43:50.522313 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
442 00:43:50.522372 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
443 00:43:50.522429 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
444 00:43:50.522487 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 00:43:50.522545 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
446 00:43:50.522611 in-header: 03 07 00 00 08 00 00 00
447 00:43:50.522670 in-data: aa e4 47 04 13 02 00 00
448 00:43:50.522728 Chrome EC: UHEPI supported
449 00:43:50.522793 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
450 00:43:50.522866 in-header: 03 a9 00 00 08 00 00 00
451 00:43:50.522928 in-data: 84 60 60 08 00 00 00 00
452 00:43:50.522986 Phase 1
453 00:43:50.523043 FMAP: area GBB found @ 3f5000 (12032 bytes)
454 00:43:50.523110 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
455 00:43:50.523169 VB2:vb2_check_recovery() Recovery was requested manually
456 00:43:50.523234 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x7
457 00:43:50.523293 Recovery requested (1009000e)
458 00:43:50.523351 TPM: Extending digest for VBOOT: boot mode into PCR 0
459 00:43:50.523409 tlcl_extend: response is 0
460 00:43:50.523474 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
461 00:43:50.523533 tlcl_extend: response is 0
462 00:43:50.523590 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
463 00:43:50.523649 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
464 00:43:50.523707 BS: bootblock times (exec / console): total (unknown) / 148 ms
465 00:43:50.523764
466 00:43:50.523829
467 00:43:50.523887 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
468 00:43:50.523945 ARM64: Exception handlers installed.
469 00:43:50.524010 ARM64: Testing exception
470 00:43:50.524069 ARM64: Done test exception
471 00:43:50.524125 pmic_efuse_setting: Set efuses in 11 msecs
472 00:43:50.524188 pmwrap_interface_init: Select PMIF_VLD_RDY
473 00:43:50.524247 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
474 00:43:50.524305 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
475 00:43:50.524580 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
476 00:43:50.524745 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
477 00:43:50.524896 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
478 00:43:50.525056 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
479 00:43:50.525215 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
480 00:43:50.525367 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
481 00:43:50.525528 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
482 00:43:50.525678 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
483 00:43:50.525827 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
484 00:43:50.525913 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
485 00:43:50.525978 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
486 00:43:50.526042 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
487 00:43:50.526106 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
488 00:43:50.526184 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
489 00:43:50.526250 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
490 00:43:50.526324 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
491 00:43:50.526387 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
492 00:43:50.526448 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
493 00:43:50.526511 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
494 00:43:50.526573 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
495 00:43:50.526636 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
496 00:43:50.526698 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
497 00:43:50.526760 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
498 00:43:50.526822 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
499 00:43:50.526895 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
500 00:43:50.526959 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
501 00:43:50.527022 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
502 00:43:50.527085 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
503 00:43:50.527147 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
504 00:43:50.527209 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
505 00:43:50.527270 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
506 00:43:50.527333 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
507 00:43:50.527395 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
508 00:43:50.527457 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
509 00:43:50.527519 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
510 00:43:50.527582 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
511 00:43:50.527644 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
512 00:43:50.527706 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
513 00:43:50.527769 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
514 00:43:50.527840 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
515 00:43:50.527904 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
516 00:43:50.527965 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
517 00:43:50.528027 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
518 00:43:50.528089 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
519 00:43:50.528151 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
520 00:43:50.528213 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
521 00:43:50.528274 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
522 00:43:50.528336 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
523 00:43:50.528406 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
524 00:43:50.528470 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x6b6d 0x5bf0 0x8100 0x4c 0xf0f 0x9248
525 00:43:50.528533 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
526 00:43:50.528604 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
527 00:43:50.528667 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
528 00:43:50.528730 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
529 00:43:50.528793 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
530 00:43:50.528855 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
531 00:43:50.528926 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 00:43:50.528989 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6c, sec=0x29
533 00:43:50.529052 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
534 00:43:50.529122 [RTC]rtc_osc_init,62: osc32con val = 0xde6c
535 00:43:50.529185 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
536 00:43:50.529247 [RTC]rtc_get_frequency_meter,154: input=15, output=836
537 00:43:50.529310 [RTC]rtc_get_frequency_meter,154: input=7, output=709
538 00:43:50.529372 [RTC]rtc_get_frequency_meter,154: input=11, output=772
539 00:43:50.529443 [RTC]rtc_get_frequency_meter,154: input=13, output=804
540 00:43:50.529505 [RTC]rtc_get_frequency_meter,154: input=12, output=788
541 00:43:50.529567 [RTC]rtc_get_frequency_meter,154: input=12, output=788
542 00:43:50.529636 [RTC]rtc_get_frequency_meter,154: input=13, output=802
543 00:43:50.529699 [RTC]rtc_eosc_cali,47: left: 12, middle: 12, right: 13
544 00:43:50.529761 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6c
545 00:43:50.530022 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
546 00:43:50.530199 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
547 00:43:50.530355 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
548 00:43:50.530515 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
549 00:43:50.530656 ADC[4]: Raw value=904509 ID=7
550 00:43:50.530725 ADC[3]: Raw value=213652 ID=1
551 00:43:50.530789 RAM Code: 0x71
552 00:43:50.530853 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
553 00:43:50.530925 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
554 00:43:50.530990 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
555 00:43:50.531054 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
556 00:43:50.531126 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
557 00:43:50.531189 in-header: 03 07 00 00 08 00 00 00
558 00:43:50.531252 in-data: aa e4 47 04 13 02 00 00
559 00:43:50.531313 Chrome EC: UHEPI supported
560 00:43:50.531382 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
561 00:43:50.531447 in-header: 03 a9 00 00 08 00 00 00
562 00:43:50.531509 in-data: 84 60 60 08 00 00 00 00
563 00:43:50.531578 MRC: failed to locate region type 0.
564 00:43:50.531641 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
565 00:43:50.531704 DRAM-K: Running full calibration
566 00:43:50.531766 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
567 00:43:50.531837 header.status = 0x0
568 00:43:50.531898 header.version = 0x6 (expected: 0x6)
569 00:43:50.531960 header.size = 0xd00 (expected: 0xd00)
570 00:43:50.532021 header.flags = 0x0
571 00:43:50.532083 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
572 00:43:50.532152 read SPI 0x72590 0x1c583: 12497 us, 9290 KB/s, 74.320 Mbps
573 00:43:50.532215 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
574 00:43:50.532283 dram_init: ddr_geometry: 2
575 00:43:50.532347 [EMI] MDL number = 2
576 00:43:50.532408 [EMI] Get MDL freq = 0
577 00:43:50.532470 dram_init: ddr_type: 0
578 00:43:50.532532 is_discrete_lpddr4: 1
579 00:43:50.532594 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
580 00:43:50.532664
581 00:43:50.532725
582 00:43:50.532793 [Bian_co] ETT version 0.0.0.1
583 00:43:50.532856 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
584 00:43:50.532918
585 00:43:50.532980 dramc_set_vcore_voltage set vcore to 650000
586 00:43:50.533042 Read voltage for 800, 4
587 00:43:50.533103 Vio18 = 0
588 00:43:50.533172 Vcore = 650000
589 00:43:50.533234 Vdram = 0
590 00:43:50.533296 Vddq = 0
591 00:43:50.533365 Vmddr = 0
592 00:43:50.533426 dram_init: config_dvfs: 1
593 00:43:50.533488 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
594 00:43:50.533558 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
595 00:43:50.533620 [SwImpedanceCal] DRVP=8, DRVN=15, ODTN=9
596 00:43:50.533682 freq_region=0, Reg: DRVP=8, DRVN=15, ODTN=9
597 00:43:50.533750 [SwImpedanceCal] DRVP=14, DRVN=24, ODTN=9
598 00:43:50.533814 freq_region=1, Reg: DRVP=14, DRVN=24, ODTN=9
599 00:43:50.533876 MEM_TYPE=3, freq_sel=18
600 00:43:50.533937 sv_algorithm_assistance_LP4_1600
601 00:43:50.534005 ============ PULL DRAM RESETB DOWN ============
602 00:43:50.534068 ========== PULL DRAM RESETB DOWN end =========
603 00:43:50.534130 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
604 00:43:50.534203 ===================================
605 00:43:50.534275 LPDDR4 DRAM CONFIGURATION
606 00:43:50.534338 ===================================
607 00:43:50.534399 EX_ROW_EN[0] = 0x0
608 00:43:50.534461 EX_ROW_EN[1] = 0x0
609 00:43:50.534531 LP4Y_EN = 0x0
610 00:43:50.534593 WORK_FSP = 0x0
611 00:43:50.534655 WL = 0x2
612 00:43:50.534716 RL = 0x2
613 00:43:50.534786 BL = 0x2
614 00:43:50.534848 RPST = 0x0
615 00:43:50.534908 RD_PRE = 0x0
616 00:43:50.534975 WR_PRE = 0x1
617 00:43:50.535039 WR_PST = 0x0
618 00:43:50.535099 DBI_WR = 0x0
619 00:43:50.535161 DBI_RD = 0x0
620 00:43:50.535228 OTF = 0x1
621 00:43:50.535292 ===================================
622 00:43:50.535354 ===================================
623 00:43:50.535417 ANA top config
624 00:43:50.535485 ===================================
625 00:43:50.535548 DLL_ASYNC_EN = 0
626 00:43:50.535610 ALL_SLAVE_EN = 1
627 00:43:50.535674 NEW_RANK_MODE = 1
628 00:43:50.535746 DLL_IDLE_MODE = 1
629 00:43:50.535809 LP45_APHY_COMB_EN = 1
630 00:43:50.535870 TX_ODT_DIS = 1
631 00:43:50.535932 NEW_8X_MODE = 1
632 00:43:50.536002 ===================================
633 00:43:50.536064 ===================================
634 00:43:50.536126 data_rate = 1600
635 00:43:50.536187 CKR = 1
636 00:43:50.536257 DQ_P2S_RATIO = 8
637 00:43:50.536318 ===================================
638 00:43:50.536380 CA_P2S_RATIO = 8
639 00:43:50.536448 DQ_CA_OPEN = 0
640 00:43:50.536511 DQ_SEMI_OPEN = 0
641 00:43:50.536572 CA_SEMI_OPEN = 0
642 00:43:50.536633 CA_FULL_RATE = 0
643 00:43:50.536700 DQ_CKDIV4_EN = 1
644 00:43:50.536763 CA_CKDIV4_EN = 1
645 00:43:50.536824 CA_PREDIV_EN = 0
646 00:43:50.536886 PH8_DLY = 0
647 00:43:50.536954 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
648 00:43:50.537018 DQ_AAMCK_DIV = 4
649 00:43:50.537079 CA_AAMCK_DIV = 4
650 00:43:50.537140 CA_ADMCK_DIV = 4
651 00:43:50.537210 DQ_TRACK_CA_EN = 0
652 00:43:50.537272 CA_PICK = 800
653 00:43:50.537334 CA_MCKIO = 800
654 00:43:50.537396 MCKIO_SEMI = 0
655 00:43:50.537465 PLL_FREQ = 3068
656 00:43:50.537527 DQ_UI_PI_RATIO = 32
657 00:43:50.537589 CA_UI_PI_RATIO = 0
658 00:43:50.537650 ===================================
659 00:43:50.537720 ===================================
660 00:43:50.537783 memory_type:LPDDR4
661 00:43:50.537845 GP_NUM : 10
662 00:43:50.537907 SRAM_EN : 1
663 00:43:50.537977 MD32_EN : 0
664 00:43:50.538245 ===================================
665 00:43:50.538322 [ANA_INIT] >>>>>>>>>>>>>>
666 00:43:50.538387 <<<<<< [CONFIGURE PHASE]: ANA_TX
667 00:43:50.538461 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
668 00:43:50.538525 ===================================
669 00:43:50.538588 data_rate = 1600,PCW = 0X7600
670 00:43:50.538650 ===================================
671 00:43:50.538720 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
672 00:43:50.538784 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
673 00:43:50.538847 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 00:43:50.538916 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
675 00:43:50.538980 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
676 00:43:50.539043 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
677 00:43:50.539105 [ANA_INIT] flow start
678 00:43:50.539173 [ANA_INIT] PLL >>>>>>>>
679 00:43:50.539236 [ANA_INIT] PLL <<<<<<<<
680 00:43:50.539297 [ANA_INIT] MIDPI >>>>>>>>
681 00:43:50.539358 [ANA_INIT] MIDPI <<<<<<<<
682 00:43:50.539418 [ANA_INIT] DLL >>>>>>>>
683 00:43:50.539479 [ANA_INIT] flow end
684 00:43:50.539540 ============ LP4 DIFF to SE enter ============
685 00:43:50.539611 ============ LP4 DIFF to SE exit ============
686 00:43:50.539686 [ANA_INIT] <<<<<<<<<<<<<
687 00:43:50.539750 [Flow] Enable top DCM control >>>>>
688 00:43:50.539812 [Flow] Enable top DCM control <<<<<
689 00:43:50.539874 Enable DLL master slave shuffle
690 00:43:50.539936 ==============================================================
691 00:43:50.539998 Gating Mode config
692 00:43:50.540060 ==============================================================
693 00:43:50.540125 Config description:
694 00:43:50.540196 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
695 00:43:50.540261 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
696 00:43:50.540324 SELPH_MODE 0: By rank 1: By Phase
697 00:43:50.540386 ==============================================================
698 00:43:50.540457 GAT_TRACK_EN = 1
699 00:43:50.540522 RX_GATING_MODE = 2
700 00:43:50.540584 RX_GATING_TRACK_MODE = 2
701 00:43:50.540645 SELPH_MODE = 1
702 00:43:50.540716 PICG_EARLY_EN = 1
703 00:43:50.540778 VALID_LAT_VALUE = 1
704 00:43:50.540840 ==============================================================
705 00:43:50.540903 Enter into Gating configuration >>>>
706 00:43:50.540973 Exit from Gating configuration <<<<
707 00:43:50.541035 Enter into DVFS_PRE_config >>>>>
708 00:43:50.541097 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
709 00:43:50.541168 Exit from DVFS_PRE_config <<<<<
710 00:43:50.541233 Enter into PICG configuration >>>>
711 00:43:50.541296 Exit from PICG configuration <<<<
712 00:43:50.541357 [RX_INPUT] configuration >>>>>
713 00:43:50.541425 [RX_INPUT] configuration <<<<<
714 00:43:50.541489 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
715 00:43:50.541552 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
716 00:43:50.541613 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
717 00:43:50.541682 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
718 00:43:50.541746 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
719 00:43:50.541807 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
720 00:43:50.541869 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
721 00:43:50.541938 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
722 00:43:50.542001 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
723 00:43:50.542063 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
724 00:43:50.542125 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
725 00:43:50.542214 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
726 00:43:50.542279 ===================================
727 00:43:50.542341 LPDDR4 DRAM CONFIGURATION
728 00:43:50.542403 ===================================
729 00:43:50.542474 EX_ROW_EN[0] = 0x0
730 00:43:50.542536 EX_ROW_EN[1] = 0x0
731 00:43:50.542597 LP4Y_EN = 0x0
732 00:43:50.542666 WORK_FSP = 0x0
733 00:43:50.542729 WL = 0x2
734 00:43:50.542790 RL = 0x2
735 00:43:50.542866 BL = 0x2
736 00:43:50.542938 RPST = 0x0
737 00:43:50.543000 RD_PRE = 0x0
738 00:43:50.543062 WR_PRE = 0x1
739 00:43:50.543124 WR_PST = 0x0
740 00:43:50.543194 DBI_WR = 0x0
741 00:43:50.543256 DBI_RD = 0x0
742 00:43:50.543317 OTF = 0x1
743 00:43:50.543378 ===================================
744 00:43:50.543449 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
745 00:43:50.543512 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
746 00:43:50.543574 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
747 00:43:50.543642 ===================================
748 00:43:50.543707 LPDDR4 DRAM CONFIGURATION
749 00:43:50.543769 ===================================
750 00:43:50.543831 EX_ROW_EN[0] = 0x10
751 00:43:50.543899 EX_ROW_EN[1] = 0x0
752 00:43:50.543962 LP4Y_EN = 0x0
753 00:43:50.544024 WORK_FSP = 0x0
754 00:43:50.544085 WL = 0x2
755 00:43:50.544154 RL = 0x2
756 00:43:50.544217 BL = 0x2
757 00:43:50.544278 RPST = 0x0
758 00:43:50.544340 RD_PRE = 0x0
759 00:43:50.544408 WR_PRE = 0x1
760 00:43:50.544471 WR_PST = 0x0
761 00:43:50.544532 DBI_WR = 0x0
762 00:43:50.544593 DBI_RD = 0x0
763 00:43:50.544661 OTF = 0x1
764 00:43:50.544724 ===================================
765 00:43:50.544786 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
766 00:43:50.544848 nWR fixed to 40
767 00:43:50.544926 [ModeRegInit_LP4] CH0 RK0
768 00:43:50.544988 [ModeRegInit_LP4] CH0 RK1
769 00:43:50.545049 [ModeRegInit_LP4] CH1 RK0
770 00:43:50.545116 [ModeRegInit_LP4] CH1 RK1
771 00:43:50.545180 match AC timing 13
772 00:43:50.545242 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
773 00:43:50.545506 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
774 00:43:50.545670 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
775 00:43:50.545822 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
776 00:43:50.545984 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
777 00:43:50.546144 [EMI DOE] emi_dcm 0
778 00:43:50.546304 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
779 00:43:50.546466 ==
780 00:43:50.546633 Dram Type= 6, Freq= 0, CH_0, rank 0
781 00:43:50.546785 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 00:43:50.546901 ==
783 00:43:50.546968 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
784 00:43:50.547032 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
785 00:43:50.547105 [CA 0] Center 37 (6~68) winsize 63
786 00:43:50.547170 [CA 1] Center 36 (6~67) winsize 62
787 00:43:50.547232 [CA 2] Center 34 (4~65) winsize 62
788 00:43:50.547295 [CA 3] Center 34 (4~65) winsize 62
789 00:43:50.547365 [CA 4] Center 33 (3~64) winsize 62
790 00:43:50.547427 [CA 5] Center 33 (3~64) winsize 62
791 00:43:50.547489
792 00:43:50.547550 [CmdBusTrainingLP45] Vref(ca) range 1: 32
793 00:43:50.547621
794 00:43:50.547682 [CATrainingPosCal] consider 1 rank data
795 00:43:50.547757 u2DelayCellTimex100 = 270/100 ps
796 00:43:50.547832 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
797 00:43:50.547897 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
798 00:43:50.547960 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
799 00:43:50.548022 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
800 00:43:50.548091 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
801 00:43:50.548154 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
802 00:43:50.548216
803 00:43:50.548277 CA PerBit enable=1, Macro0, CA PI delay=33
804 00:43:50.548348
805 00:43:50.548410 [CBTSetCACLKResult] CA Dly = 33
806 00:43:50.548472 CS Dly: 6 (0~37)
807 00:43:50.548534 ==
808 00:43:50.548604 Dram Type= 6, Freq= 0, CH_0, rank 1
809 00:43:50.548668 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
810 00:43:50.548730 ==
811 00:43:50.548793 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
812 00:43:50.548862 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
813 00:43:50.548926 [CA 0] Center 37 (6~68) winsize 63
814 00:43:50.548988 [CA 1] Center 37 (7~68) winsize 62
815 00:43:50.549055 [CA 2] Center 34 (4~65) winsize 62
816 00:43:50.549118 [CA 3] Center 34 (4~65) winsize 62
817 00:43:50.549181 [CA 4] Center 33 (3~64) winsize 62
818 00:43:50.549243 [CA 5] Center 33 (2~64) winsize 63
819 00:43:50.549323
820 00:43:50.549380 [CmdBusTrainingLP45] Vref(ca) range 1: 34
821 00:43:50.549436
822 00:43:50.549492 [CATrainingPosCal] consider 2 rank data
823 00:43:50.549554 u2DelayCellTimex100 = 270/100 ps
824 00:43:50.549612 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
825 00:43:50.549669 CA1 delay=37 (7~67),Diff = 4 PI (28 cell)
826 00:43:50.549725 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
827 00:43:50.549781 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
828 00:43:50.549845 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
829 00:43:50.549901 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
830 00:43:50.549957
831 00:43:50.550012 CA PerBit enable=1, Macro0, CA PI delay=33
832 00:43:50.550076
833 00:43:50.550131 [CBTSetCACLKResult] CA Dly = 33
834 00:43:50.550199 CS Dly: 6 (0~38)
835 00:43:50.550256
836 00:43:50.550320 ----->DramcWriteLeveling(PI) begin...
837 00:43:50.550378 ==
838 00:43:50.550435 Dram Type= 6, Freq= 0, CH_0, rank 0
839 00:43:50.550491 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
840 00:43:50.550554 ==
841 00:43:50.550611 Write leveling (Byte 0): 30 => 30
842 00:43:50.550667 Write leveling (Byte 1): 29 => 29
843 00:43:50.550723 DramcWriteLeveling(PI) end<-----
844 00:43:50.550785
845 00:43:50.550845 ==
846 00:43:50.550902 Dram Type= 6, Freq= 0, CH_0, rank 0
847 00:43:50.550958 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
848 00:43:50.551022 ==
849 00:43:50.551080 [Gating] SW mode calibration
850 00:43:50.551140 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
851 00:43:50.551236 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
852 00:43:50.551324 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
853 00:43:50.551415 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
854 00:43:50.551479 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
855 00:43:50.551547 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
856 00:43:50.551604 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 00:43:50.551661 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 00:43:50.551717 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 00:43:50.551773 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 00:43:50.551829 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 00:43:50.551885 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 00:43:50.551942 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 00:43:50.551997 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 00:43:50.552053 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 00:43:50.552108 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 00:43:50.552164 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 00:43:50.552220 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 00:43:50.552285 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 00:43:50.552342 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
870 00:43:50.552398 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
871 00:43:50.552461 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
872 00:43:50.552518 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 00:43:50.552575 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 00:43:50.552631 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 00:43:50.552687 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 00:43:50.552743 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 00:43:50.552799 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 00:43:50.552856 0 9 8 | B1->B0 | 2322 2e2e | 1 1 | (0 0) (1 1)
879 00:43:50.552919 0 9 12 | B1->B0 | 2f2f 3434 | 1 1 | (0 0) (1 1)
880 00:43:50.552976 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
881 00:43:50.553229 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 00:43:50.553302 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
883 00:43:50.553361 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
884 00:43:50.553418 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
885 00:43:50.553475 0 10 4 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
886 00:43:50.553539 0 10 8 | B1->B0 | 3434 2d2d | 0 0 | (0 0) (1 0)
887 00:43:50.553596 0 10 12 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
888 00:43:50.553654 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
889 00:43:50.553710 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 00:43:50.553773 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 00:43:50.553830 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
892 00:43:50.553887 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
893 00:43:50.553943 0 11 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
894 00:43:50.554005 0 11 8 | B1->B0 | 2323 3b3b | 0 0 | (0 0) (0 0)
895 00:43:50.554062 0 11 12 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
896 00:43:50.554119 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
897 00:43:50.554188 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 00:43:50.554254 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 00:43:50.554313 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
900 00:43:50.554380 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
901 00:43:50.554434 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
902 00:43:50.554488 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
903 00:43:50.554549 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
904 00:43:50.554603 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 00:43:50.554672 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 00:43:50.554736 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 00:43:50.554792 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 00:43:50.554845 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 00:43:50.554899 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 00:43:50.554953 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 00:43:50.555014 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 00:43:50.555072 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 00:43:50.555126 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 00:43:50.555180 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 00:43:50.555239 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
916 00:43:50.555293 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
917 00:43:50.555346 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
918 00:43:50.555400 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
919 00:43:50.555453 Total UI for P1: 0, mck2ui 16
920 00:43:50.555515 best dqsien dly found for B0: ( 0, 14, 4)
921 00:43:50.555569 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
922 00:43:50.555623 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
923 00:43:50.555676 Total UI for P1: 0, mck2ui 16
924 00:43:50.555736 best dqsien dly found for B1: ( 0, 14, 10)
925 00:43:50.555791 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
926 00:43:50.555844 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
927 00:43:50.555898
928 00:43:50.555951 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
929 00:43:50.556012 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
930 00:43:50.556065 [Gating] SW calibration Done
931 00:43:50.556119 ==
932 00:43:50.556172 Dram Type= 6, Freq= 0, CH_0, rank 0
933 00:43:50.556232 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 00:43:50.556287 ==
935 00:43:50.556340 RX Vref Scan: 0
936 00:43:50.556393
937 00:43:50.556446 RX Vref 0 -> 0, step: 1
938 00:43:50.556505
939 00:43:50.556558 RX Delay -130 -> 252, step: 16
940 00:43:50.556612 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
941 00:43:50.556665 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
942 00:43:50.556725 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
943 00:43:50.556779 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
944 00:43:50.556833 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
945 00:43:50.556921 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
946 00:43:50.556981 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
947 00:43:50.557034 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
948 00:43:50.557088 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
949 00:43:50.557141 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
950 00:43:50.557199 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
951 00:43:50.557254 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
952 00:43:50.557307 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
953 00:43:50.557360 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
954 00:43:50.557413 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
955 00:43:50.557474 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
956 00:43:50.557528 ==
957 00:43:50.557581 Dram Type= 6, Freq= 0, CH_0, rank 0
958 00:43:50.557634 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
959 00:43:50.557694 ==
960 00:43:50.557748 DQS Delay:
961 00:43:50.557801 DQS0 = 0, DQS1 = 0
962 00:43:50.557854 DQM Delay:
963 00:43:50.557907 DQM0 = 86, DQM1 = 74
964 00:43:50.557967 DQ Delay:
965 00:43:50.558021 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
966 00:43:50.558075 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =101
967 00:43:50.558129 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =69
968 00:43:50.558220 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =85
969 00:43:50.558289
970 00:43:50.558342
971 00:43:50.558395 ==
972 00:43:50.558448 Dram Type= 6, Freq= 0, CH_0, rank 0
973 00:43:50.558509 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
974 00:43:50.558563 ==
975 00:43:50.558616
976 00:43:50.558669
977 00:43:50.558729 TX Vref Scan disable
978 00:43:50.558782 == TX Byte 0 ==
979 00:43:50.558836 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
980 00:43:50.558890 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
981 00:43:50.558950 == TX Byte 1 ==
982 00:43:50.559004 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
983 00:43:50.559057 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
984 00:43:50.559111 ==
985 00:43:50.559169 Dram Type= 6, Freq= 0, CH_0, rank 0
986 00:43:50.559224 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
987 00:43:50.559278 ==
988 00:43:50.559535 TX Vref=22, minBit 13, minWin=26, winSum=439
989 00:43:50.559677 TX Vref=24, minBit 4, minWin=27, winSum=440
990 00:43:50.559808 TX Vref=26, minBit 5, minWin=27, winSum=446
991 00:43:50.559945 TX Vref=28, minBit 8, minWin=27, winSum=445
992 00:43:50.560075 TX Vref=30, minBit 8, minWin=27, winSum=445
993 00:43:50.560214 TX Vref=32, minBit 4, minWin=27, winSum=444
994 00:43:50.560344 [TxChooseVref] Worse bit 5, Min win 27, Win sum 446, Final Vref 26
995 00:43:50.560472
996 00:43:50.560599 Final TX Range 1 Vref 26
997 00:43:50.560781
998 00:43:50.560854 ==
999 00:43:50.560958 Dram Type= 6, Freq= 0, CH_0, rank 0
1000 00:43:50.561015 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1001 00:43:50.561070 ==
1002 00:43:50.561123
1003 00:43:50.561177
1004 00:43:50.561240 TX Vref Scan disable
1005 00:43:50.561293 == TX Byte 0 ==
1006 00:43:50.561347 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1007 00:43:50.561401 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1008 00:43:50.561461 == TX Byte 1 ==
1009 00:43:50.561517 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1010 00:43:50.561571 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1011 00:43:50.561626
1012 00:43:50.561680 [DATLAT]
1013 00:43:50.561741 Freq=800, CH0 RK0
1014 00:43:50.561796
1015 00:43:50.561849 DATLAT Default: 0xa
1016 00:43:50.561902 0, 0xFFFF, sum = 0
1017 00:43:50.561964 1, 0xFFFF, sum = 0
1018 00:43:50.562019 2, 0xFFFF, sum = 0
1019 00:43:50.562074 3, 0xFFFF, sum = 0
1020 00:43:50.562128 4, 0xFFFF, sum = 0
1021 00:43:50.562226 5, 0xFFFF, sum = 0
1022 00:43:50.562282 6, 0xFFFF, sum = 0
1023 00:43:50.562336 7, 0xFFFF, sum = 0
1024 00:43:50.562391 8, 0xFFFF, sum = 0
1025 00:43:50.562454 9, 0x0, sum = 1
1026 00:43:50.562521 10, 0x0, sum = 2
1027 00:43:50.562577 11, 0x0, sum = 3
1028 00:43:50.562632 12, 0x0, sum = 4
1029 00:43:50.562691 best_step = 10
1030 00:43:50.562746
1031 00:43:50.562799 ==
1032 00:43:50.562852 Dram Type= 6, Freq= 0, CH_0, rank 0
1033 00:43:50.562905 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1034 00:43:50.562966 ==
1035 00:43:50.563019 RX Vref Scan: 1
1036 00:43:50.563073
1037 00:43:50.563125 Set Vref Range= 32 -> 127
1038 00:43:50.563184
1039 00:43:50.563238 RX Vref 32 -> 127, step: 1
1040 00:43:50.563291
1041 00:43:50.563343 RX Delay -111 -> 252, step: 8
1042 00:43:50.563396
1043 00:43:50.563455 Set Vref, RX VrefLevel [Byte0]: 32
1044 00:43:50.563509 [Byte1]: 32
1045 00:43:50.563562
1046 00:43:50.563614 Set Vref, RX VrefLevel [Byte0]: 33
1047 00:43:50.563672 [Byte1]: 33
1048 00:43:50.563727
1049 00:43:50.563780 Set Vref, RX VrefLevel [Byte0]: 34
1050 00:43:50.563833 [Byte1]: 34
1051 00:43:50.563885
1052 00:43:50.563945 Set Vref, RX VrefLevel [Byte0]: 35
1053 00:43:50.563998 [Byte1]: 35
1054 00:43:50.564051
1055 00:43:50.564103 Set Vref, RX VrefLevel [Byte0]: 36
1056 00:43:50.564156 [Byte1]: 36
1057 00:43:50.564215
1058 00:43:50.564268 Set Vref, RX VrefLevel [Byte0]: 37
1059 00:43:50.564321 [Byte1]: 37
1060 00:43:50.564373
1061 00:43:50.564432 Set Vref, RX VrefLevel [Byte0]: 38
1062 00:43:50.564486 [Byte1]: 38
1063 00:43:50.564538
1064 00:43:50.564591 Set Vref, RX VrefLevel [Byte0]: 39
1065 00:43:50.564644 [Byte1]: 39
1066 00:43:50.564703
1067 00:43:50.564755 Set Vref, RX VrefLevel [Byte0]: 40
1068 00:43:50.564808 [Byte1]: 40
1069 00:43:50.564860
1070 00:43:50.564919 Set Vref, RX VrefLevel [Byte0]: 41
1071 00:43:50.564972 [Byte1]: 41
1072 00:43:50.565025
1073 00:43:50.565077 Set Vref, RX VrefLevel [Byte0]: 42
1074 00:43:50.565130 [Byte1]: 42
1075 00:43:50.565189
1076 00:43:50.565242 Set Vref, RX VrefLevel [Byte0]: 43
1077 00:43:50.565294 [Byte1]: 43
1078 00:43:50.565347
1079 00:43:50.565405 Set Vref, RX VrefLevel [Byte0]: 44
1080 00:43:50.565459 [Byte1]: 44
1081 00:43:50.565512
1082 00:43:50.565564 Set Vref, RX VrefLevel [Byte0]: 45
1083 00:43:50.565617 [Byte1]: 45
1084 00:43:50.565676
1085 00:43:50.565728 Set Vref, RX VrefLevel [Byte0]: 46
1086 00:43:50.565781 [Byte1]: 46
1087 00:43:50.565833
1088 00:43:50.565890 Set Vref, RX VrefLevel [Byte0]: 47
1089 00:43:50.565945 [Byte1]: 47
1090 00:43:50.565997
1091 00:43:50.566050 Set Vref, RX VrefLevel [Byte0]: 48
1092 00:43:50.566102 [Byte1]: 48
1093 00:43:50.566167
1094 00:43:50.566257 Set Vref, RX VrefLevel [Byte0]: 49
1095 00:43:50.566310 [Byte1]: 49
1096 00:43:50.566362
1097 00:43:50.566414 Set Vref, RX VrefLevel [Byte0]: 50
1098 00:43:50.566474 [Byte1]: 50
1099 00:43:50.566527
1100 00:43:50.566580 Set Vref, RX VrefLevel [Byte0]: 51
1101 00:43:50.566638 [Byte1]: 51
1102 00:43:50.566692
1103 00:43:50.566745 Set Vref, RX VrefLevel [Byte0]: 52
1104 00:43:50.566797 [Byte1]: 52
1105 00:43:50.566849
1106 00:43:50.566919 Set Vref, RX VrefLevel [Byte0]: 53
1107 00:43:50.566996 [Byte1]: 53
1108 00:43:50.567075
1109 00:43:50.567137 Set Vref, RX VrefLevel [Byte0]: 54
1110 00:43:50.567192 [Byte1]: 54
1111 00:43:50.567245
1112 00:43:50.567297 Set Vref, RX VrefLevel [Byte0]: 55
1113 00:43:50.567350 [Byte1]: 55
1114 00:43:50.567410
1115 00:43:50.567463 Set Vref, RX VrefLevel [Byte0]: 56
1116 00:43:50.567516 [Byte1]: 56
1117 00:43:50.567569
1118 00:43:50.567629 Set Vref, RX VrefLevel [Byte0]: 57
1119 00:43:50.567683 [Byte1]: 57
1120 00:43:50.567735
1121 00:43:50.567787 Set Vref, RX VrefLevel [Byte0]: 58
1122 00:43:50.567840 [Byte1]: 58
1123 00:43:50.567892
1124 00:43:50.567950 Set Vref, RX VrefLevel [Byte0]: 59
1125 00:43:50.568005 [Byte1]: 59
1126 00:43:50.568058
1127 00:43:50.568110 Set Vref, RX VrefLevel [Byte0]: 60
1128 00:43:50.568164 [Byte1]: 60
1129 00:43:50.568216
1130 00:43:50.568269 Set Vref, RX VrefLevel [Byte0]: 61
1131 00:43:50.568321 [Byte1]: 61
1132 00:43:50.568374
1133 00:43:50.568426 Set Vref, RX VrefLevel [Byte0]: 62
1134 00:43:50.568485 [Byte1]: 62
1135 00:43:50.568539
1136 00:43:50.568592 Set Vref, RX VrefLevel [Byte0]: 63
1137 00:43:50.568644 [Byte1]: 63
1138 00:43:50.568696
1139 00:43:50.568756 Set Vref, RX VrefLevel [Byte0]: 64
1140 00:43:50.568809 [Byte1]: 64
1141 00:43:50.568861
1142 00:43:50.568914 Set Vref, RX VrefLevel [Byte0]: 65
1143 00:43:50.568973 [Byte1]: 65
1144 00:43:50.569026
1145 00:43:50.569079 Set Vref, RX VrefLevel [Byte0]: 66
1146 00:43:50.569132 [Byte1]: 66
1147 00:43:50.569185
1148 00:43:50.569244 Set Vref, RX VrefLevel [Byte0]: 67
1149 00:43:50.569297 [Byte1]: 67
1150 00:43:50.569349
1151 00:43:50.569402 Set Vref, RX VrefLevel [Byte0]: 68
1152 00:43:50.569455 [Byte1]: 68
1153 00:43:50.569514
1154 00:43:50.569566 Set Vref, RX VrefLevel [Byte0]: 69
1155 00:43:50.569619 [Byte1]: 69
1156 00:43:50.569671
1157 00:43:50.569931 Set Vref, RX VrefLevel [Byte0]: 70
1158 00:43:50.570069 [Byte1]: 70
1159 00:43:50.570243
1160 00:43:50.570371 Set Vref, RX VrefLevel [Byte0]: 71
1161 00:43:50.570507 [Byte1]: 71
1162 00:43:50.570574
1163 00:43:50.570630 Set Vref, RX VrefLevel [Byte0]: 72
1164 00:43:50.570683 [Byte1]: 72
1165 00:43:50.570745
1166 00:43:50.570798 Set Vref, RX VrefLevel [Byte0]: 73
1167 00:43:50.570851 [Byte1]: 73
1168 00:43:50.570904
1169 00:43:50.570963 Set Vref, RX VrefLevel [Byte0]: 74
1170 00:43:50.571017 [Byte1]: 74
1171 00:43:50.571070
1172 00:43:50.571122 Set Vref, RX VrefLevel [Byte0]: 75
1173 00:43:50.571175 [Byte1]: 75
1174 00:43:50.571235
1175 00:43:50.571288 Set Vref, RX VrefLevel [Byte0]: 76
1176 00:43:50.571341 [Byte1]: 76
1177 00:43:50.571393
1178 00:43:50.571452 Set Vref, RX VrefLevel [Byte0]: 77
1179 00:43:50.571506 [Byte1]: 77
1180 00:43:50.571559
1181 00:43:50.571612 Set Vref, RX VrefLevel [Byte0]: 78
1182 00:43:50.571665 [Byte1]: 78
1183 00:43:50.571724
1184 00:43:50.571777 Set Vref, RX VrefLevel [Byte0]: 79
1185 00:43:50.571829 [Byte1]: 79
1186 00:43:50.571882
1187 00:43:50.571940 Set Vref, RX VrefLevel [Byte0]: 80
1188 00:43:50.571994 [Byte1]: 80
1189 00:43:50.572046
1190 00:43:50.572098 Final RX Vref Byte 0 = 67 to rank0
1191 00:43:50.572151 Final RX Vref Byte 1 = 55 to rank0
1192 00:43:50.572211 Final RX Vref Byte 0 = 67 to rank1
1193 00:43:50.572264 Final RX Vref Byte 1 = 55 to rank1==
1194 00:43:50.572317 Dram Type= 6, Freq= 0, CH_0, rank 0
1195 00:43:50.572370 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1196 00:43:50.572429 ==
1197 00:43:50.572483 DQS Delay:
1198 00:43:50.572536 DQS0 = 0, DQS1 = 0
1199 00:43:50.572589 DQM Delay:
1200 00:43:50.572641 DQM0 = 88, DQM1 = 76
1201 00:43:50.572701 DQ Delay:
1202 00:43:50.572754 DQ0 =84, DQ1 =92, DQ2 =84, DQ3 =84
1203 00:43:50.572807 DQ4 =88, DQ5 =76, DQ6 =100, DQ7 =96
1204 00:43:50.572859 DQ8 =68, DQ9 =64, DQ10 =76, DQ11 =68
1205 00:43:50.572918 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =84
1206 00:43:50.572972
1207 00:43:50.573025
1208 00:43:50.573077 [DQSOSCAuto] RK0, (LSB)MR18= 0x4627, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 392 ps
1209 00:43:50.573131 CH0 RK0: MR19=606, MR18=4627
1210 00:43:50.573191 CH0_RK0: MR19=0x606, MR18=0x4627, DQSOSC=392, MR23=63, INC=96, DEC=64
1211 00:43:50.573244
1212 00:43:50.573296 ----->DramcWriteLeveling(PI) begin...
1213 00:43:50.573350 ==
1214 00:43:50.573408 Dram Type= 6, Freq= 0, CH_0, rank 1
1215 00:43:50.573463 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1216 00:43:50.573516 ==
1217 00:43:50.573568 Write leveling (Byte 0): 32 => 32
1218 00:43:50.573620 Write leveling (Byte 1): 32 => 32
1219 00:43:50.573680 DramcWriteLeveling(PI) end<-----
1220 00:43:50.573733
1221 00:43:50.573785 ==
1222 00:43:50.573838 Dram Type= 6, Freq= 0, CH_0, rank 1
1223 00:43:50.573896 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1224 00:43:50.573951 ==
1225 00:43:50.574004 [Gating] SW mode calibration
1226 00:43:50.574057 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1227 00:43:50.574113 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1228 00:43:50.574208 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1229 00:43:50.574278 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1230 00:43:50.574331 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1231 00:43:50.574384 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 00:43:50.574444 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 00:43:50.574498 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 00:43:50.574551 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 00:43:50.574604 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 00:43:50.574663 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1237 00:43:50.574718 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1238 00:43:50.574771 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1239 00:43:50.574823 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1240 00:43:50.574882 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1241 00:43:50.574936 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1242 00:43:50.574989 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1243 00:43:50.575042 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1244 00:43:50.575095 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1245 00:43:50.575155 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1246 00:43:50.575209 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1247 00:43:50.575262 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1248 00:43:50.575315 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1249 00:43:50.575373 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1250 00:43:50.575428 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1251 00:43:50.575481 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1252 00:43:50.575535 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1253 00:43:50.575587 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1254 00:43:50.575648 0 9 8 | B1->B0 | 2727 2c2c | 0 0 | (0 0) (0 0)
1255 00:43:50.575701 0 9 12 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
1256 00:43:50.575754 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1257 00:43:50.575806 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1258 00:43:50.575864 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1259 00:43:50.575919 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1260 00:43:50.575972 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1261 00:43:50.576024 0 10 4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
1262 00:43:50.576077 0 10 8 | B1->B0 | 2f2f 2a2a | 0 0 | (1 0) (1 1)
1263 00:43:50.576137 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1264 00:43:50.576191 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1265 00:43:50.576243 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1266 00:43:50.576296 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1267 00:43:50.576348 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1268 00:43:50.576614 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1269 00:43:50.576752 0 11 4 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
1270 00:43:50.576889 0 11 8 | B1->B0 | 2d2d 3e3e | 0 0 | (0 0) (0 0)
1271 00:43:50.577016 0 11 12 | B1->B0 | 4242 4646 | 0 0 | (1 1) (0 0)
1272 00:43:50.577149 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1273 00:43:50.577208 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1274 00:43:50.577263 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1275 00:43:50.577316 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1276 00:43:50.577377 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1277 00:43:50.577431 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1278 00:43:50.577484 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1279 00:43:50.577536 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1280 00:43:50.577594 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1281 00:43:50.577648 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1282 00:43:50.577700 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1283 00:43:50.577753 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1284 00:43:50.577806 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1285 00:43:50.577865 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1286 00:43:50.577919 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1287 00:43:50.577972 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1288 00:43:50.578024 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1289 00:43:50.578083 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1290 00:43:50.578137 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1291 00:43:50.578225 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1292 00:43:50.578292 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1293 00:43:50.578351 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1294 00:43:50.578406 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1295 00:43:50.578459 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1296 00:43:50.578511 Total UI for P1: 0, mck2ui 16
1297 00:43:50.578565 best dqsien dly found for B0: ( 0, 14, 8)
1298 00:43:50.578626 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1299 00:43:50.578679 Total UI for P1: 0, mck2ui 16
1300 00:43:50.578732 best dqsien dly found for B1: ( 0, 14, 10)
1301 00:43:50.578785 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1302 00:43:50.578845 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
1303 00:43:50.578898
1304 00:43:50.578951 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1305 00:43:50.579003 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
1306 00:43:50.579056 [Gating] SW calibration Done
1307 00:43:50.579116 ==
1308 00:43:50.579170 Dram Type= 6, Freq= 0, CH_0, rank 1
1309 00:43:50.579222 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1310 00:43:50.579276 ==
1311 00:43:50.579335 RX Vref Scan: 0
1312 00:43:50.579388
1313 00:43:50.579440 RX Vref 0 -> 0, step: 1
1314 00:43:50.579492
1315 00:43:50.579545 RX Delay -130 -> 252, step: 16
1316 00:43:50.579598 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1317 00:43:50.579650 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1318 00:43:50.579703 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1319 00:43:50.579755 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1320 00:43:50.579808 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1321 00:43:50.579870 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1322 00:43:50.579923 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1323 00:43:50.579976 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1324 00:43:50.580029 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1325 00:43:50.580081 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1326 00:43:50.580133 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1327 00:43:50.580186 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1328 00:43:50.580238 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1329 00:43:50.580291 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1330 00:43:50.580350 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1331 00:43:50.580404 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1332 00:43:50.580456 ==
1333 00:43:50.580510 Dram Type= 6, Freq= 0, CH_0, rank 1
1334 00:43:50.580562 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1335 00:43:50.580622 ==
1336 00:43:50.580675 DQS Delay:
1337 00:43:50.580727 DQS0 = 0, DQS1 = 0
1338 00:43:50.580780 DQM Delay:
1339 00:43:50.580838 DQM0 = 84, DQM1 = 77
1340 00:43:50.580893 DQ Delay:
1341 00:43:50.580948 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =77
1342 00:43:50.581001 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
1343 00:43:50.581053 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1344 00:43:50.581113 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =77
1345 00:43:50.581167
1346 00:43:50.581219
1347 00:43:50.581271 ==
1348 00:43:50.581330 Dram Type= 6, Freq= 0, CH_0, rank 1
1349 00:43:50.581385 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1350 00:43:50.581438 ==
1351 00:43:50.581490
1352 00:43:50.581542
1353 00:43:50.581601 TX Vref Scan disable
1354 00:43:50.581655 == TX Byte 0 ==
1355 00:43:50.581708 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1356 00:43:50.581762 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1357 00:43:50.581814 == TX Byte 1 ==
1358 00:43:50.581874 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1359 00:43:50.581927 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1360 00:43:50.581980 ==
1361 00:43:50.582033 Dram Type= 6, Freq= 0, CH_0, rank 1
1362 00:43:50.582091 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1363 00:43:50.582145 ==
1364 00:43:50.582242 TX Vref=22, minBit 3, minWin=27, winSum=444
1365 00:43:50.582296 TX Vref=24, minBit 3, minWin=27, winSum=448
1366 00:43:50.582355 TX Vref=26, minBit 9, minWin=27, winSum=448
1367 00:43:50.582409 TX Vref=28, minBit 11, minWin=27, winSum=449
1368 00:43:50.582462 TX Vref=30, minBit 12, minWin=27, winSum=447
1369 00:43:50.582515 TX Vref=32, minBit 8, minWin=27, winSum=446
1370 00:43:50.582568 [TxChooseVref] Worse bit 11, Min win 27, Win sum 449, Final Vref 28
1371 00:43:50.582628
1372 00:43:50.582680 Final TX Range 1 Vref 28
1373 00:43:50.582732
1374 00:43:50.582784 ==
1375 00:43:50.582843 Dram Type= 6, Freq= 0, CH_0, rank 1
1376 00:43:50.582896 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1377 00:43:50.582949 ==
1378 00:43:50.583011
1379 00:43:50.583069
1380 00:43:50.583122 TX Vref Scan disable
1381 00:43:50.583175 == TX Byte 0 ==
1382 00:43:50.583227 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1383 00:43:50.583280 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1384 00:43:50.583339 == TX Byte 1 ==
1385 00:43:50.583587 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1386 00:43:50.583647 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1387 00:43:50.583708
1388 00:43:50.583760 [DATLAT]
1389 00:43:50.583812 Freq=800, CH0 RK1
1390 00:43:50.583865
1391 00:43:50.583924 DATLAT Default: 0xa
1392 00:43:50.583977 0, 0xFFFF, sum = 0
1393 00:43:50.584030 1, 0xFFFF, sum = 0
1394 00:43:50.584088 2, 0xFFFF, sum = 0
1395 00:43:50.584143 3, 0xFFFF, sum = 0
1396 00:43:50.584195 4, 0xFFFF, sum = 0
1397 00:43:50.584247 5, 0xFFFF, sum = 0
1398 00:43:50.584300 6, 0xFFFF, sum = 0
1399 00:43:50.584352 7, 0xFFFF, sum = 0
1400 00:43:50.584404 8, 0xFFFF, sum = 0
1401 00:43:50.584457 9, 0x0, sum = 1
1402 00:43:50.584509 10, 0x0, sum = 2
1403 00:43:50.584569 11, 0x0, sum = 3
1404 00:43:50.584623 12, 0x0, sum = 4
1405 00:43:50.584676 best_step = 10
1406 00:43:50.584728
1407 00:43:50.584780 ==
1408 00:43:50.584837 Dram Type= 6, Freq= 0, CH_0, rank 1
1409 00:43:50.584892 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1410 00:43:50.584945 ==
1411 00:43:50.584996 RX Vref Scan: 0
1412 00:43:50.585048
1413 00:43:50.585143 RX Vref 0 -> 0, step: 1
1414 00:43:50.585195
1415 00:43:50.585246 RX Delay -95 -> 252, step: 8
1416 00:43:50.585298 iDelay=217, Bit 0, Center 84 (-31 ~ 200) 232
1417 00:43:50.585356 iDelay=217, Bit 1, Center 92 (-23 ~ 208) 232
1418 00:43:50.585409 iDelay=217, Bit 2, Center 80 (-31 ~ 192) 224
1419 00:43:50.585461 iDelay=217, Bit 3, Center 80 (-31 ~ 192) 224
1420 00:43:50.585519 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
1421 00:43:50.585572 iDelay=217, Bit 5, Center 76 (-39 ~ 192) 232
1422 00:43:50.585624 iDelay=217, Bit 6, Center 96 (-15 ~ 208) 224
1423 00:43:50.585677 iDelay=217, Bit 7, Center 96 (-23 ~ 216) 240
1424 00:43:50.585728 iDelay=217, Bit 8, Center 68 (-47 ~ 184) 232
1425 00:43:50.585787 iDelay=217, Bit 9, Center 64 (-47 ~ 176) 224
1426 00:43:50.585839 iDelay=217, Bit 10, Center 76 (-39 ~ 192) 232
1427 00:43:50.585891 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
1428 00:43:50.585942 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
1429 00:43:50.585994 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
1430 00:43:50.586046 iDelay=217, Bit 14, Center 88 (-23 ~ 200) 224
1431 00:43:50.586104 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
1432 00:43:50.586157 ==
1433 00:43:50.586253 Dram Type= 6, Freq= 0, CH_0, rank 1
1434 00:43:50.586305 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1435 00:43:50.586365 ==
1436 00:43:50.586418 DQS Delay:
1437 00:43:50.586470 DQS0 = 0, DQS1 = 0
1438 00:43:50.586527 DQM Delay:
1439 00:43:50.586580 DQM0 = 86, DQM1 = 77
1440 00:43:50.586632 DQ Delay:
1441 00:43:50.586684 DQ0 =84, DQ1 =92, DQ2 =80, DQ3 =80
1442 00:43:50.586736 DQ4 =84, DQ5 =76, DQ6 =96, DQ7 =96
1443 00:43:50.586796 DQ8 =68, DQ9 =64, DQ10 =76, DQ11 =68
1444 00:43:50.586850 DQ12 =84, DQ13 =84, DQ14 =88, DQ15 =84
1445 00:43:50.586901
1446 00:43:50.586953
1447 00:43:50.587032 [DQSOSCAuto] RK1, (LSB)MR18= 0x4109, (MSB)MR19= 0x606, tDQSOscB0 = 407 ps tDQSOscB1 = 393 ps
1448 00:43:50.587087 CH0 RK1: MR19=606, MR18=4109
1449 00:43:50.587140 CH0_RK1: MR19=0x606, MR18=0x4109, DQSOSC=393, MR23=63, INC=95, DEC=63
1450 00:43:50.587192 [RxdqsGatingPostProcess] freq 800
1451 00:43:50.587251 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1452 00:43:50.587304 Pre-setting of DQS Precalculation
1453 00:43:50.587356 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1454 00:43:50.587409 ==
1455 00:43:50.587461 Dram Type= 6, Freq= 0, CH_1, rank 0
1456 00:43:50.587520 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1457 00:43:50.587574 ==
1458 00:43:50.587626 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1459 00:43:50.587678 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1460 00:43:50.587755 [CA 0] Center 36 (6~67) winsize 62
1461 00:43:50.587822 [CA 1] Center 36 (6~67) winsize 62
1462 00:43:50.587874 [CA 2] Center 34 (4~65) winsize 62
1463 00:43:50.587925 [CA 3] Center 34 (4~65) winsize 62
1464 00:43:50.587999 [CA 4] Center 34 (4~65) winsize 62
1465 00:43:50.588066 [CA 5] Center 34 (3~65) winsize 63
1466 00:43:50.588117
1467 00:43:50.588168 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1468 00:43:50.588220
1469 00:43:50.588278 [CATrainingPosCal] consider 1 rank data
1470 00:43:50.588330 u2DelayCellTimex100 = 270/100 ps
1471 00:43:50.588382 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1472 00:43:50.588433 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1473 00:43:50.588491 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1474 00:43:50.588544 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1475 00:43:50.588596 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1476 00:43:50.588648 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1477 00:43:50.588699
1478 00:43:50.588759 CA PerBit enable=1, Macro0, CA PI delay=34
1479 00:43:50.588811
1480 00:43:50.588862 [CBTSetCACLKResult] CA Dly = 34
1481 00:43:50.588914 CS Dly: 5 (0~36)
1482 00:43:50.588973 ==
1483 00:43:50.589032 Dram Type= 6, Freq= 0, CH_1, rank 1
1484 00:43:50.589085 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1485 00:43:50.589138 ==
1486 00:43:50.589190 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1487 00:43:50.589250 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1488 00:43:50.589302 [CA 0] Center 36 (6~67) winsize 62
1489 00:43:50.589355 [CA 1] Center 37 (6~68) winsize 63
1490 00:43:50.589407 [CA 2] Center 34 (4~65) winsize 62
1491 00:43:50.589464 [CA 3] Center 34 (4~65) winsize 62
1492 00:43:50.589518 [CA 4] Center 34 (4~65) winsize 62
1493 00:43:50.589570 [CA 5] Center 34 (4~64) winsize 61
1494 00:43:50.589622
1495 00:43:50.589673 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1496 00:43:50.589732
1497 00:43:50.589784 [CATrainingPosCal] consider 2 rank data
1498 00:43:50.589836 u2DelayCellTimex100 = 270/100 ps
1499 00:43:50.589889 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1500 00:43:50.589941 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1501 00:43:50.590000 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1502 00:43:50.590052 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1503 00:43:50.590105 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1504 00:43:50.590156 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1505 00:43:50.590263
1506 00:43:50.590316 CA PerBit enable=1, Macro0, CA PI delay=34
1507 00:43:50.590368
1508 00:43:50.590419 [CBTSetCACLKResult] CA Dly = 34
1509 00:43:50.590471 CS Dly: 5 (0~37)
1510 00:43:50.590523
1511 00:43:50.590575 ----->DramcWriteLeveling(PI) begin...
1512 00:43:50.590628 ==
1513 00:43:50.590680 Dram Type= 6, Freq= 0, CH_1, rank 0
1514 00:43:50.590733 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1515 00:43:50.590785 ==
1516 00:43:50.590837 Write leveling (Byte 0): 27 => 27
1517 00:43:50.590896 Write leveling (Byte 1): 27 => 27
1518 00:43:50.591152 DramcWriteLeveling(PI) end<-----
1519 00:43:50.591283
1520 00:43:50.591408 ==
1521 00:43:50.591534 Dram Type= 6, Freq= 0, CH_1, rank 0
1522 00:43:50.591671 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1523 00:43:50.591808 ==
1524 00:43:50.591943 [Gating] SW mode calibration
1525 00:43:50.592073 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1526 00:43:50.592201 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1527 00:43:50.592283 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1528 00:43:50.592339 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1529 00:43:50.592393 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 00:43:50.592452 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 00:43:50.592507 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 00:43:50.592559 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 00:43:50.592611 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 00:43:50.592663 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1535 00:43:50.592716 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1536 00:43:50.592768 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1537 00:43:50.592827 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1538 00:43:50.592880 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1539 00:43:50.592933 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1540 00:43:50.592996 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1541 00:43:50.593066 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1542 00:43:50.593156 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1543 00:43:50.593221 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1544 00:43:50.593274 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1545 00:43:50.593327 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1546 00:43:50.593380 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1547 00:43:50.593433 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1548 00:43:50.593490 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1549 00:43:50.593545 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1550 00:43:50.593597 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1551 00:43:50.593649 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1552 00:43:50.593709 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1553 00:43:50.593762 0 9 8 | B1->B0 | 2c2b 3434 | 1 1 | (0 0) (1 1)
1554 00:43:50.593815 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1555 00:43:50.593867 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1556 00:43:50.593919 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1557 00:43:50.593972 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1558 00:43:50.594032 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1559 00:43:50.594085 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1560 00:43:50.594137 0 10 4 | B1->B0 | 3434 3030 | 1 1 | (0 1) (0 0)
1561 00:43:50.594212 0 10 8 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
1562 00:43:50.594267 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1563 00:43:50.594320 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1564 00:43:50.594371 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1565 00:43:50.594423 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1566 00:43:50.594476 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1567 00:43:50.594534 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1568 00:43:50.594587 0 11 4 | B1->B0 | 2424 2525 | 0 0 | (0 0) (0 0)
1569 00:43:50.594640 0 11 8 | B1->B0 | 3636 4343 | 0 0 | (0 0) (0 0)
1570 00:43:50.594692 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1571 00:43:50.594751 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1572 00:43:50.594803 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1573 00:43:50.594855 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1574 00:43:50.594913 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1575 00:43:50.594966 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1576 00:43:50.595040 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1577 00:43:50.595093 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1578 00:43:50.595146 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1579 00:43:50.595199 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1580 00:43:50.595258 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1581 00:43:50.595311 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1582 00:43:50.595363 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1583 00:43:50.595415 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1584 00:43:50.595474 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1585 00:43:50.595527 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1586 00:43:50.595579 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1587 00:43:50.595637 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1588 00:43:50.595691 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1589 00:43:50.595743 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1590 00:43:50.595796 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1591 00:43:50.595848 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1592 00:43:50.595900 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1593 00:43:50.595958 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1594 00:43:50.596012 Total UI for P1: 0, mck2ui 16
1595 00:43:50.596065 best dqsien dly found for B0: ( 0, 14, 4)
1596 00:43:50.596118 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1597 00:43:50.596177 Total UI for P1: 0, mck2ui 16
1598 00:43:50.596230 best dqsien dly found for B1: ( 0, 14, 8)
1599 00:43:50.596282 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1600 00:43:50.596335 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1601 00:43:50.596386
1602 00:43:50.596438 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1603 00:43:50.596497 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1604 00:43:50.596746 [Gating] SW calibration Done
1605 00:43:50.596807 ==
1606 00:43:50.596860 Dram Type= 6, Freq= 0, CH_1, rank 0
1607 00:43:50.596913 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1608 00:43:50.596974 ==
1609 00:43:50.597027 RX Vref Scan: 0
1610 00:43:50.597079
1611 00:43:50.597137 RX Vref 0 -> 0, step: 1
1612 00:43:50.597190
1613 00:43:50.597242 RX Delay -130 -> 252, step: 16
1614 00:43:50.597294 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1615 00:43:50.597346 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1616 00:43:50.597398 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1617 00:43:50.597450 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1618 00:43:50.597509 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1619 00:43:50.597562 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1620 00:43:50.597614 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1621 00:43:50.597665 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1622 00:43:50.597725 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1623 00:43:50.597778 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1624 00:43:50.597829 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1625 00:43:50.597888 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1626 00:43:50.597941 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1627 00:43:50.597992 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1628 00:43:50.598045 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1629 00:43:50.598097 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1630 00:43:50.598148 ==
1631 00:43:50.598243 Dram Type= 6, Freq= 0, CH_1, rank 0
1632 00:43:50.598310 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1633 00:43:50.598362 ==
1634 00:43:50.598421 DQS Delay:
1635 00:43:50.598474 DQS0 = 0, DQS1 = 0
1636 00:43:50.598526 DQM Delay:
1637 00:43:50.598578 DQM0 = 88, DQM1 = 79
1638 00:43:50.598636 DQ Delay:
1639 00:43:50.598688 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =85
1640 00:43:50.598741 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1641 00:43:50.598793 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
1642 00:43:50.598852 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1643 00:43:50.598904
1644 00:43:50.598956
1645 00:43:50.599035 ==
1646 00:43:50.599156 Dram Type= 6, Freq= 0, CH_1, rank 0
1647 00:43:50.599252 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1648 00:43:50.599314 ==
1649 00:43:50.599369
1650 00:43:50.599422
1651 00:43:50.599474 TX Vref Scan disable
1652 00:43:50.599526 == TX Byte 0 ==
1653 00:43:50.599586 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1654 00:43:50.599639 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1655 00:43:50.599692 == TX Byte 1 ==
1656 00:43:50.599745 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1657 00:43:50.599803 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1658 00:43:50.599857 ==
1659 00:43:50.599909 Dram Type= 6, Freq= 0, CH_1, rank 0
1660 00:43:50.599962 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1661 00:43:50.600014 ==
1662 00:43:50.600072 TX Vref=22, minBit 8, minWin=27, winSum=443
1663 00:43:50.600126 TX Vref=24, minBit 9, minWin=27, winSum=446
1664 00:43:50.600179 TX Vref=26, minBit 9, minWin=27, winSum=449
1665 00:43:50.600231 TX Vref=28, minBit 8, minWin=27, winSum=448
1666 00:43:50.600283 TX Vref=30, minBit 0, minWin=27, winSum=449
1667 00:43:50.600343 TX Vref=32, minBit 8, minWin=27, winSum=450
1668 00:43:50.600396 [TxChooseVref] Worse bit 8, Min win 27, Win sum 450, Final Vref 32
1669 00:43:50.600449
1670 00:43:50.600501 Final TX Range 1 Vref 32
1671 00:43:50.600559
1672 00:43:50.600612 ==
1673 00:43:50.600665 Dram Type= 6, Freq= 0, CH_1, rank 0
1674 00:43:50.600717 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1675 00:43:50.600770 ==
1676 00:43:50.600822
1677 00:43:50.600874
1678 00:43:50.600925 TX Vref Scan disable
1679 00:43:50.600977 == TX Byte 0 ==
1680 00:43:50.601029 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1681 00:43:50.601082 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1682 00:43:50.601134 == TX Byte 1 ==
1683 00:43:50.601186 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1684 00:43:50.601238 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1685 00:43:50.601290
1686 00:43:50.601351 [DATLAT]
1687 00:43:50.601404 Freq=800, CH1 RK0
1688 00:43:50.601456
1689 00:43:50.601508 DATLAT Default: 0xa
1690 00:43:50.601560 0, 0xFFFF, sum = 0
1691 00:43:50.601615 1, 0xFFFF, sum = 0
1692 00:43:50.601668 2, 0xFFFF, sum = 0
1693 00:43:50.601721 3, 0xFFFF, sum = 0
1694 00:43:50.601774 4, 0xFFFF, sum = 0
1695 00:43:50.601827 5, 0xFFFF, sum = 0
1696 00:43:50.601888 6, 0xFFFF, sum = 0
1697 00:43:50.601941 7, 0xFFFF, sum = 0
1698 00:43:50.601994 8, 0xFFFF, sum = 0
1699 00:43:50.602047 9, 0x0, sum = 1
1700 00:43:50.602108 10, 0x0, sum = 2
1701 00:43:50.602168 11, 0x0, sum = 3
1702 00:43:50.602260 12, 0x0, sum = 4
1703 00:43:50.602313 best_step = 10
1704 00:43:50.602372
1705 00:43:50.602425 ==
1706 00:43:50.602478 Dram Type= 6, Freq= 0, CH_1, rank 0
1707 00:43:50.602530 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1708 00:43:50.602583 ==
1709 00:43:50.602643 RX Vref Scan: 1
1710 00:43:50.602696
1711 00:43:50.602748 Set Vref Range= 32 -> 127
1712 00:43:50.602800
1713 00:43:50.602852 RX Vref 32 -> 127, step: 1
1714 00:43:50.602904
1715 00:43:50.602956 RX Delay -95 -> 252, step: 8
1716 00:43:50.603008
1717 00:43:50.603067 Set Vref, RX VrefLevel [Byte0]: 32
1718 00:43:50.603121 [Byte1]: 32
1719 00:43:50.603173
1720 00:43:50.603225 Set Vref, RX VrefLevel [Byte0]: 33
1721 00:43:50.603284 [Byte1]: 33
1722 00:43:50.603337
1723 00:43:50.603389 Set Vref, RX VrefLevel [Byte0]: 34
1724 00:43:50.603440 [Byte1]: 34
1725 00:43:50.603499
1726 00:43:50.603551 Set Vref, RX VrefLevel [Byte0]: 35
1727 00:43:50.603603 [Byte1]: 35
1728 00:43:50.603655
1729 00:43:50.603706 Set Vref, RX VrefLevel [Byte0]: 36
1730 00:43:50.603758 [Byte1]: 36
1731 00:43:50.603817
1732 00:43:50.603869 Set Vref, RX VrefLevel [Byte0]: 37
1733 00:43:50.603922 [Byte1]: 37
1734 00:43:50.603981
1735 00:43:50.604034 Set Vref, RX VrefLevel [Byte0]: 38
1736 00:43:50.604086 [Byte1]: 38
1737 00:43:50.604139
1738 00:43:50.604196 Set Vref, RX VrefLevel [Byte0]: 39
1739 00:43:50.604249 [Byte1]: 39
1740 00:43:50.604301
1741 00:43:50.604353 Set Vref, RX VrefLevel [Byte0]: 40
1742 00:43:50.604405 [Byte1]: 40
1743 00:43:50.604463
1744 00:43:50.604516 Set Vref, RX VrefLevel [Byte0]: 41
1745 00:43:50.604568 [Byte1]: 41
1746 00:43:50.604620
1747 00:43:50.604677 Set Vref, RX VrefLevel [Byte0]: 42
1748 00:43:50.604730 [Byte1]: 42
1749 00:43:50.604783
1750 00:43:50.604835 Set Vref, RX VrefLevel [Byte0]: 43
1751 00:43:50.604886 [Byte1]: 43
1752 00:43:50.604945
1753 00:43:50.604997 Set Vref, RX VrefLevel [Byte0]: 44
1754 00:43:50.605049 [Byte1]: 44
1755 00:43:50.605101
1756 00:43:50.605153 Set Vref, RX VrefLevel [Byte0]: 45
1757 00:43:50.605213 [Byte1]: 45
1758 00:43:50.605265
1759 00:43:50.605317 Set Vref, RX VrefLevel [Byte0]: 46
1760 00:43:50.605369 [Byte1]: 46
1761 00:43:50.605427
1762 00:43:50.605681 Set Vref, RX VrefLevel [Byte0]: 47
1763 00:43:50.605809 [Byte1]: 47
1764 00:43:50.605945
1765 00:43:50.606068 Set Vref, RX VrefLevel [Byte0]: 48
1766 00:43:50.606252 [Byte1]: 48
1767 00:43:50.606377
1768 00:43:50.606513 Set Vref, RX VrefLevel [Byte0]: 49
1769 00:43:50.606639 [Byte1]: 49
1770 00:43:50.606774
1771 00:43:50.606904 Set Vref, RX VrefLevel [Byte0]: 50
1772 00:43:50.606963 [Byte1]: 50
1773 00:43:50.607016
1774 00:43:50.607071 Set Vref, RX VrefLevel [Byte0]: 51
1775 00:43:50.607123 [Byte1]: 51
1776 00:43:50.607183
1777 00:43:50.607234 Set Vref, RX VrefLevel [Byte0]: 52
1778 00:43:50.607287 [Byte1]: 52
1779 00:43:50.607338
1780 00:43:50.607397 Set Vref, RX VrefLevel [Byte0]: 53
1781 00:43:50.607449 [Byte1]: 53
1782 00:43:50.607500
1783 00:43:50.607551 Set Vref, RX VrefLevel [Byte0]: 54
1784 00:43:50.607602 [Byte1]: 54
1785 00:43:50.607661
1786 00:43:50.607713 Set Vref, RX VrefLevel [Byte0]: 55
1787 00:43:50.607764 [Byte1]: 55
1788 00:43:50.607816
1789 00:43:50.607873 Set Vref, RX VrefLevel [Byte0]: 56
1790 00:43:50.607926 [Byte1]: 56
1791 00:43:50.607978
1792 00:43:50.608029 Set Vref, RX VrefLevel [Byte0]: 57
1793 00:43:50.608081 [Byte1]: 57
1794 00:43:50.608140
1795 00:43:50.608192 Set Vref, RX VrefLevel [Byte0]: 58
1796 00:43:50.608243 [Byte1]: 58
1797 00:43:50.608294
1798 00:43:50.608345 Set Vref, RX VrefLevel [Byte0]: 59
1799 00:43:50.608404 [Byte1]: 59
1800 00:43:50.608456
1801 00:43:50.608508 Set Vref, RX VrefLevel [Byte0]: 60
1802 00:43:50.608560 [Byte1]: 60
1803 00:43:50.608618
1804 00:43:50.608670 Set Vref, RX VrefLevel [Byte0]: 61
1805 00:43:50.608722 [Byte1]: 61
1806 00:43:50.608774
1807 00:43:50.608826 Set Vref, RX VrefLevel [Byte0]: 62
1808 00:43:50.608884 [Byte1]: 62
1809 00:43:50.608936
1810 00:43:50.608987 Set Vref, RX VrefLevel [Byte0]: 63
1811 00:43:50.609039 [Byte1]: 63
1812 00:43:50.609090
1813 00:43:50.609149 Set Vref, RX VrefLevel [Byte0]: 64
1814 00:43:50.609201 [Byte1]: 64
1815 00:43:50.609252
1816 00:43:50.609304 Set Vref, RX VrefLevel [Byte0]: 65
1817 00:43:50.609361 [Byte1]: 65
1818 00:43:50.609414
1819 00:43:50.609465 Set Vref, RX VrefLevel [Byte0]: 66
1820 00:43:50.609516 [Byte1]: 66
1821 00:43:50.609568
1822 00:43:50.609626 Set Vref, RX VrefLevel [Byte0]: 67
1823 00:43:50.609679 [Byte1]: 67
1824 00:43:50.609731
1825 00:43:50.609782 Set Vref, RX VrefLevel [Byte0]: 68
1826 00:43:50.609839 [Byte1]: 68
1827 00:43:50.609893
1828 00:43:50.609945 Set Vref, RX VrefLevel [Byte0]: 69
1829 00:43:50.609997 [Byte1]: 69
1830 00:43:50.610048
1831 00:43:50.610107 Set Vref, RX VrefLevel [Byte0]: 70
1832 00:43:50.610159 [Byte1]: 70
1833 00:43:50.610259
1834 00:43:50.610311 Set Vref, RX VrefLevel [Byte0]: 71
1835 00:43:50.610370 [Byte1]: 71
1836 00:43:50.610423
1837 00:43:50.610475 Set Vref, RX VrefLevel [Byte0]: 72
1838 00:43:50.610526 [Byte1]: 72
1839 00:43:50.610584
1840 00:43:50.610637 Set Vref, RX VrefLevel [Byte0]: 73
1841 00:43:50.610690 [Byte1]: 73
1842 00:43:50.610741
1843 00:43:50.610793 Set Vref, RX VrefLevel [Byte0]: 74
1844 00:43:50.610851 [Byte1]: 74
1845 00:43:50.610904
1846 00:43:50.610955 Set Vref, RX VrefLevel [Byte0]: 75
1847 00:43:50.611007 [Byte1]: 75
1848 00:43:50.611058
1849 00:43:50.611117 Set Vref, RX VrefLevel [Byte0]: 76
1850 00:43:50.611169 [Byte1]: 76
1851 00:43:50.611221
1852 00:43:50.611272 Set Vref, RX VrefLevel [Byte0]: 77
1853 00:43:50.611330 [Byte1]: 77
1854 00:43:50.611383
1855 00:43:50.611434 Final RX Vref Byte 0 = 63 to rank0
1856 00:43:50.611487 Final RX Vref Byte 1 = 64 to rank0
1857 00:43:50.611538 Final RX Vref Byte 0 = 63 to rank1
1858 00:43:50.611598 Final RX Vref Byte 1 = 64 to rank1==
1859 00:43:50.611651 Dram Type= 6, Freq= 0, CH_1, rank 0
1860 00:43:50.611703 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1861 00:43:50.611755 ==
1862 00:43:50.611812 DQS Delay:
1863 00:43:50.611865 DQS0 = 0, DQS1 = 0
1864 00:43:50.611918 DQM Delay:
1865 00:43:50.611969 DQM0 = 86, DQM1 = 79
1866 00:43:50.612022 DQ Delay:
1867 00:43:50.612081 DQ0 =92, DQ1 =84, DQ2 =76, DQ3 =84
1868 00:43:50.612133 DQ4 =80, DQ5 =100, DQ6 =96, DQ7 =80
1869 00:43:50.612185 DQ8 =68, DQ9 =68, DQ10 =84, DQ11 =68
1870 00:43:50.612237 DQ12 =84, DQ13 =84, DQ14 =88, DQ15 =88
1871 00:43:50.612288
1872 00:43:50.612346
1873 00:43:50.612398 [DQSOSCAuto] RK0, (LSB)MR18= 0x331e, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 396 ps
1874 00:43:50.612450 CH1 RK0: MR19=606, MR18=331E
1875 00:43:50.612503 CH1_RK0: MR19=0x606, MR18=0x331E, DQSOSC=396, MR23=63, INC=94, DEC=62
1876 00:43:50.612561
1877 00:43:50.612614 ----->DramcWriteLeveling(PI) begin...
1878 00:43:50.612666 ==
1879 00:43:50.612718 Dram Type= 6, Freq= 0, CH_1, rank 1
1880 00:43:50.612776 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1881 00:43:50.612829 ==
1882 00:43:50.612880 Write leveling (Byte 0): 26 => 26
1883 00:43:50.612933 Write leveling (Byte 1): 31 => 31
1884 00:43:50.612985 DramcWriteLeveling(PI) end<-----
1885 00:43:50.613036
1886 00:43:50.613088 ==
1887 00:43:50.613146 Dram Type= 6, Freq= 0, CH_1, rank 1
1888 00:43:50.613199 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1889 00:43:50.613252 ==
1890 00:43:50.613304 [Gating] SW mode calibration
1891 00:43:50.613356 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1892 00:43:50.613408 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1893 00:43:50.613461 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1894 00:43:50.613513 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1895 00:43:50.613565 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1896 00:43:50.613617 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1897 00:43:50.613669 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1898 00:43:50.613730 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1899 00:43:50.613782 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1900 00:43:50.613834 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1901 00:43:50.613886 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1902 00:43:50.613938 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1903 00:43:50.613990 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1904 00:43:50.614246 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1905 00:43:50.614307 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1906 00:43:50.614361 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1907 00:43:50.614414 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1908 00:43:50.614473 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1909 00:43:50.614528 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1910 00:43:50.614580 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1911 00:43:50.614632 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 1)
1912 00:43:50.614685 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1913 00:43:50.614737 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1914 00:43:50.614789 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1915 00:43:50.614848 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1916 00:43:50.614901 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1917 00:43:50.614954 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1918 00:43:50.615011 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1919 00:43:50.615065 0 9 8 | B1->B0 | 3131 2626 | 0 1 | (0 0) (0 0)
1920 00:43:50.615118 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1921 00:43:50.615170 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1922 00:43:50.615229 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1923 00:43:50.615281 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1924 00:43:50.615333 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1925 00:43:50.615384 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1926 00:43:50.615437 0 10 4 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
1927 00:43:50.615488 0 10 8 | B1->B0 | 2727 2e2e | 0 1 | (0 0) (1 0)
1928 00:43:50.615548 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1929 00:43:50.615600 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1930 00:43:50.615652 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1931 00:43:50.615704 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1932 00:43:50.615764 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1933 00:43:50.615817 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1934 00:43:50.615869 0 11 4 | B1->B0 | 2d2d 2727 | 0 1 | (0 0) (0 0)
1935 00:43:50.615921 0 11 8 | B1->B0 | 3c3c 3838 | 0 0 | (0 0) (0 0)
1936 00:43:50.615973 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1937 00:43:50.616026 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1938 00:43:50.616086 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1939 00:43:50.616138 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1940 00:43:50.616190 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1941 00:43:50.616249 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1942 00:43:50.616301 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1943 00:43:50.616353 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1944 00:43:50.616405 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1945 00:43:50.616457 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1946 00:43:50.616510 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1947 00:43:50.616567 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1948 00:43:50.616620 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1949 00:43:50.616672 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1950 00:43:50.616725 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1951 00:43:50.616783 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1952 00:43:50.616836 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1953 00:43:50.616888 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1954 00:43:50.616945 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1955 00:43:50.616999 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1956 00:43:50.617051 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1957 00:43:50.617103 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1958 00:43:50.617155 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1959 00:43:50.617207 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1960 00:43:50.617258 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1961 00:43:50.617310 Total UI for P1: 0, mck2ui 16
1962 00:43:50.617363 best dqsien dly found for B0: ( 0, 14, 6)
1963 00:43:50.617423 Total UI for P1: 0, mck2ui 16
1964 00:43:50.617476 best dqsien dly found for B1: ( 0, 14, 6)
1965 00:43:50.617528 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1966 00:43:50.617587 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1967 00:43:50.617640
1968 00:43:50.617691 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1969 00:43:50.617743 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1970 00:43:50.617795 [Gating] SW calibration Done
1971 00:43:50.617847 ==
1972 00:43:50.617899 Dram Type= 6, Freq= 0, CH_1, rank 1
1973 00:43:50.617951 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1974 00:43:50.618003 ==
1975 00:43:50.618063 RX Vref Scan: 0
1976 00:43:50.618115
1977 00:43:50.618175 RX Vref 0 -> 0, step: 1
1978 00:43:50.618260
1979 00:43:50.618312 RX Delay -130 -> 252, step: 16
1980 00:43:50.618364 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1981 00:43:50.618416 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1982 00:43:50.618469 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1983 00:43:50.618521 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1984 00:43:50.618573 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1985 00:43:50.618625 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1986 00:43:50.618677 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1987 00:43:50.769894 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1988 00:43:50.770592 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1989 00:43:50.771099 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1990 00:43:50.771588 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1991 00:43:50.772064 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1992 00:43:50.772527 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1993 00:43:50.772983 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1994 00:43:50.773862 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1995 00:43:50.774374 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1996 00:43:50.774708 ==
1997 00:43:50.775103 Dram Type= 6, Freq= 0, CH_1, rank 1
1998 00:43:50.775438 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1999 00:43:50.775756 ==
2000 00:43:50.776189 DQS Delay:
2001 00:43:50.776660 DQS0 = 0, DQS1 = 0
2002 00:43:50.777156 DQM Delay:
2003 00:43:50.777606 DQM0 = 87, DQM1 = 78
2004 00:43:50.778068 DQ Delay:
2005 00:43:50.778454 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =85
2006 00:43:50.778796 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
2007 00:43:50.779106 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
2008 00:43:50.779511 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
2009 00:43:50.779996
2010 00:43:50.780456
2011 00:43:50.780906 ==
2012 00:43:50.781333 Dram Type= 6, Freq= 0, CH_1, rank 1
2013 00:43:50.781646 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2014 00:43:50.782093 ==
2015 00:43:50.782464
2016 00:43:50.782744
2017 00:43:50.783042 TX Vref Scan disable
2018 00:43:50.783333 == TX Byte 0 ==
2019 00:43:50.783631 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2020 00:43:50.783914 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2021 00:43:50.784221 == TX Byte 1 ==
2022 00:43:50.784504 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
2023 00:43:50.784944 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
2024 00:43:50.785382 ==
2025 00:43:50.785872 Dram Type= 6, Freq= 0, CH_1, rank 1
2026 00:43:50.786380 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2027 00:43:50.786685 ==
2028 00:43:50.787067 TX Vref=22, minBit 9, minWin=26, winSum=444
2029 00:43:50.787426 TX Vref=24, minBit 8, minWin=27, winSum=446
2030 00:43:50.787723 TX Vref=26, minBit 9, minWin=26, winSum=448
2031 00:43:50.788162 TX Vref=28, minBit 8, minWin=27, winSum=450
2032 00:43:50.788407 TX Vref=30, minBit 8, minWin=27, winSum=451
2033 00:43:50.788460 TX Vref=32, minBit 8, minWin=27, winSum=451
2034 00:43:50.788513 [TxChooseVref] Worse bit 8, Min win 27, Win sum 451, Final Vref 30
2035 00:43:50.788572
2036 00:43:50.788626 Final TX Range 1 Vref 30
2037 00:43:50.788679
2038 00:43:50.788735 ==
2039 00:43:50.788819 Dram Type= 6, Freq= 0, CH_1, rank 1
2040 00:43:50.788901 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2041 00:43:50.788983 ==
2042 00:43:50.789066
2043 00:43:50.789148
2044 00:43:50.789228 TX Vref Scan disable
2045 00:43:50.789299 == TX Byte 0 ==
2046 00:43:50.789353 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2047 00:43:50.789407 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2048 00:43:50.789464 == TX Byte 1 ==
2049 00:43:50.789518 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
2050 00:43:50.789571 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
2051 00:43:50.789623
2052 00:43:50.789675 [DATLAT]
2053 00:43:50.789727 Freq=800, CH1 RK1
2054 00:43:50.789806
2055 00:43:50.789887 DATLAT Default: 0xa
2056 00:43:50.789968 0, 0xFFFF, sum = 0
2057 00:43:50.790051 1, 0xFFFF, sum = 0
2058 00:43:50.790135 2, 0xFFFF, sum = 0
2059 00:43:50.790209 3, 0xFFFF, sum = 0
2060 00:43:50.790302 4, 0xFFFF, sum = 0
2061 00:43:50.790360 5, 0xFFFF, sum = 0
2062 00:43:50.790413 6, 0xFFFF, sum = 0
2063 00:43:50.790467 7, 0xFFFF, sum = 0
2064 00:43:50.790559 8, 0xFFFF, sum = 0
2065 00:43:50.790614 9, 0x0, sum = 1
2066 00:43:50.790669 10, 0x0, sum = 2
2067 00:43:50.790722 11, 0x0, sum = 3
2068 00:43:50.790775 12, 0x0, sum = 4
2069 00:43:50.790837 best_step = 10
2070 00:43:50.790892
2071 00:43:50.790944 ==
2072 00:43:50.790996 Dram Type= 6, Freq= 0, CH_1, rank 1
2073 00:43:50.791055 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2074 00:43:50.791109 ==
2075 00:43:50.791161 RX Vref Scan: 0
2076 00:43:50.791218
2077 00:43:50.791272 RX Vref 0 -> 0, step: 1
2078 00:43:50.791325
2079 00:43:50.791377 RX Delay -95 -> 252, step: 8
2080 00:43:50.791429 iDelay=217, Bit 0, Center 92 (-23 ~ 208) 232
2081 00:43:50.791483 iDelay=217, Bit 1, Center 80 (-31 ~ 192) 224
2082 00:43:50.791540 iDelay=217, Bit 2, Center 76 (-39 ~ 192) 232
2083 00:43:50.791595 iDelay=217, Bit 3, Center 84 (-31 ~ 200) 232
2084 00:43:50.791647 iDelay=217, Bit 4, Center 88 (-23 ~ 200) 224
2085 00:43:50.791706 iDelay=217, Bit 5, Center 96 (-15 ~ 208) 224
2086 00:43:50.791789 iDelay=217, Bit 6, Center 100 (-15 ~ 216) 232
2087 00:43:50.791871 iDelay=217, Bit 7, Center 84 (-31 ~ 200) 232
2088 00:43:50.791953 iDelay=217, Bit 8, Center 68 (-47 ~ 184) 232
2089 00:43:50.792035 iDelay=217, Bit 9, Center 68 (-47 ~ 184) 232
2090 00:43:50.792123 iDelay=217, Bit 10, Center 84 (-31 ~ 200) 232
2091 00:43:50.792206 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
2092 00:43:50.792292 iDelay=217, Bit 12, Center 88 (-23 ~ 200) 224
2093 00:43:50.792375 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
2094 00:43:50.792457 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
2095 00:43:50.792538 iDelay=217, Bit 15, Center 88 (-31 ~ 208) 240
2096 00:43:50.792619 ==
2097 00:43:50.792705 Dram Type= 6, Freq= 0, CH_1, rank 1
2098 00:43:50.792788 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2099 00:43:50.792873 ==
2100 00:43:50.792955 DQS Delay:
2101 00:43:50.793036 DQS0 = 0, DQS1 = 0
2102 00:43:50.793117 DQM Delay:
2103 00:43:50.793198 DQM0 = 87, DQM1 = 79
2104 00:43:50.793284 DQ Delay:
2105 00:43:50.793341 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
2106 00:43:50.793394 DQ4 =88, DQ5 =96, DQ6 =100, DQ7 =84
2107 00:43:50.793451 DQ8 =68, DQ9 =68, DQ10 =84, DQ11 =68
2108 00:43:50.793506 DQ12 =88, DQ13 =84, DQ14 =84, DQ15 =88
2109 00:43:50.793559
2110 00:43:50.793611
2111 00:43:50.793663 [DQSOSCAuto] RK1, (LSB)MR18= 0x1810, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 403 ps
2112 00:43:50.793718 CH1 RK1: MR19=606, MR18=1810
2113 00:43:50.793772 CH1_RK1: MR19=0x606, MR18=0x1810, DQSOSC=403, MR23=63, INC=90, DEC=60
2114 00:43:50.793824 [RxdqsGatingPostProcess] freq 800
2115 00:43:50.793880 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2116 00:43:50.793965 Pre-setting of DQS Precalculation
2117 00:43:50.794048 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2118 00:43:50.794135 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2119 00:43:50.794243 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2120 00:43:50.794298
2121 00:43:50.794350
2122 00:43:50.794402 [Calibration Summary] 1600 Mbps
2123 00:43:50.794463 CH 0, Rank 0
2124 00:43:50.794516 SW Impedance : PASS
2125 00:43:50.794569 DUTY Scan : NO K
2126 00:43:50.794623 ZQ Calibration : PASS
2127 00:43:50.794681 Jitter Meter : NO K
2128 00:43:50.794734 CBT Training : PASS
2129 00:43:50.794786 Write leveling : PASS
2130 00:43:50.794845 RX DQS gating : PASS
2131 00:43:50.794898 RX DQ/DQS(RDDQC) : PASS
2132 00:43:50.794950 TX DQ/DQS : PASS
2133 00:43:50.795003 RX DATLAT : PASS
2134 00:43:50.795085 RX DQ/DQS(Engine): PASS
2135 00:43:50.795168 TX OE : NO K
2136 00:43:50.795249 All Pass.
2137 00:43:50.795330
2138 00:43:50.795390 CH 0, Rank 1
2139 00:43:50.795444 SW Impedance : PASS
2140 00:43:50.795698 DUTY Scan : NO K
2141 00:43:50.795785 ZQ Calibration : PASS
2142 00:43:50.795871 Jitter Meter : NO K
2143 00:43:50.795954 CBT Training : PASS
2144 00:43:50.796039 Write leveling : PASS
2145 00:43:50.796144 RX DQS gating : PASS
2146 00:43:50.796241 RX DQ/DQS(RDDQC) : PASS
2147 00:43:50.796324 TX DQ/DQS : PASS
2148 00:43:50.796415 RX DATLAT : PASS
2149 00:43:50.796497 RX DQ/DQS(Engine): PASS
2150 00:43:50.796578 TX OE : NO K
2151 00:43:50.796666 All Pass.
2152 00:43:50.796767
2153 00:43:50.796851 CH 1, Rank 0
2154 00:43:50.796936 SW Impedance : PASS
2155 00:43:50.797018 DUTY Scan : NO K
2156 00:43:50.797103 ZQ Calibration : PASS
2157 00:43:50.797185 Jitter Meter : NO K
2158 00:43:50.797269 CBT Training : PASS
2159 00:43:50.797326 Write leveling : PASS
2160 00:43:50.797379 RX DQS gating : PASS
2161 00:43:50.797432 RX DQ/DQS(RDDQC) : PASS
2162 00:43:50.797485 TX DQ/DQS : PASS
2163 00:43:50.797538 RX DATLAT : PASS
2164 00:43:50.797591 RX DQ/DQS(Engine): PASS
2165 00:43:50.797650 TX OE : NO K
2166 00:43:50.797733 All Pass.
2167 00:43:50.797819
2168 00:43:50.797902 CH 1, Rank 1
2169 00:43:50.797984 SW Impedance : PASS
2170 00:43:50.798069 DUTY Scan : NO K
2171 00:43:50.798152 ZQ Calibration : PASS
2172 00:43:50.798270 Jitter Meter : NO K
2173 00:43:50.798325 CBT Training : PASS
2174 00:43:50.798379 Write leveling : PASS
2175 00:43:50.798431 RX DQS gating : PASS
2176 00:43:50.798484 RX DQ/DQS(RDDQC) : PASS
2177 00:43:50.798544 TX DQ/DQS : PASS
2178 00:43:50.798598 RX DATLAT : PASS
2179 00:43:50.798651 RX DQ/DQS(Engine): PASS
2180 00:43:50.798703 TX OE : NO K
2181 00:43:50.798760 All Pass.
2182 00:43:50.798815
2183 00:43:50.798867 DramC Write-DBI off
2184 00:43:50.798920 PER_BANK_REFRESH: Hybrid Mode
2185 00:43:50.798973 TX_TRACKING: ON
2186 00:43:50.799026 [GetDramInforAfterCalByMRR] Vendor 6.
2187 00:43:50.799079 [GetDramInforAfterCalByMRR] Revision 606.
2188 00:43:50.799144 [GetDramInforAfterCalByMRR] Revision 2 0.
2189 00:43:50.799199 MR0 0x3b3b
2190 00:43:50.799252 MR8 0x5151
2191 00:43:50.799325 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2192 00:43:50.799406
2193 00:43:50.799490 MR0 0x3b3b
2194 00:43:50.799572 MR8 0x5151
2195 00:43:50.799654 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2196 00:43:50.799735
2197 00:43:50.799818 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2198 00:43:50.799905 [FAST_K] Save calibration result to emmc
2199 00:43:50.799998 [FAST_K] Save calibration result to emmc
2200 00:43:50.800084 dram_init: config_dvfs: 1
2201 00:43:50.800166 dramc_set_vcore_voltage set vcore to 662500
2202 00:43:50.800252 Read voltage for 1200, 2
2203 00:43:50.800336 Vio18 = 0
2204 00:43:50.800417 Vcore = 662500
2205 00:43:50.800499 Vdram = 0
2206 00:43:50.800580 Vddq = 0
2207 00:43:50.800665 Vmddr = 0
2208 00:43:50.800747 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2209 00:43:50.800834 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2210 00:43:50.800917 MEM_TYPE=3, freq_sel=15
2211 00:43:50.801001 sv_algorithm_assistance_LP4_1600
2212 00:43:50.801084 ============ PULL DRAM RESETB DOWN ============
2213 00:43:50.801167 ========== PULL DRAM RESETB DOWN end =========
2214 00:43:50.801250 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2215 00:43:50.801332 ===================================
2216 00:43:50.801414 LPDDR4 DRAM CONFIGURATION
2217 00:43:50.801494 ===================================
2218 00:43:50.801549 EX_ROW_EN[0] = 0x0
2219 00:43:50.801604 EX_ROW_EN[1] = 0x0
2220 00:43:50.801675 LP4Y_EN = 0x0
2221 00:43:50.801757 WORK_FSP = 0x0
2222 00:43:50.801841 WL = 0x4
2223 00:43:50.801923 RL = 0x4
2224 00:43:50.802004 BL = 0x2
2225 00:43:50.802085 RPST = 0x0
2226 00:43:50.802177 RD_PRE = 0x0
2227 00:43:50.802273 WR_PRE = 0x1
2228 00:43:50.802327 WR_PST = 0x0
2229 00:43:50.802384 DBI_WR = 0x0
2230 00:43:50.802439 DBI_RD = 0x0
2231 00:43:50.802492 OTF = 0x1
2232 00:43:50.802545 ===================================
2233 00:43:50.802603 ===================================
2234 00:43:50.802658 ANA top config
2235 00:43:50.802711 ===================================
2236 00:43:50.802765 DLL_ASYNC_EN = 0
2237 00:43:50.802818 ALL_SLAVE_EN = 0
2238 00:43:50.802870 NEW_RANK_MODE = 1
2239 00:43:50.802928 DLL_IDLE_MODE = 1
2240 00:43:50.802983 LP45_APHY_COMB_EN = 1
2241 00:43:50.803036 TX_ODT_DIS = 1
2242 00:43:50.803093 NEW_8X_MODE = 1
2243 00:43:50.803149 ===================================
2244 00:43:50.803202 ===================================
2245 00:43:50.803255 data_rate = 2400
2246 00:43:50.803308 CKR = 1
2247 00:43:50.803361 DQ_P2S_RATIO = 8
2248 00:43:50.803414 ===================================
2249 00:43:50.803478 CA_P2S_RATIO = 8
2250 00:43:50.803532 DQ_CA_OPEN = 0
2251 00:43:50.803585 DQ_SEMI_OPEN = 0
2252 00:43:50.803654 CA_SEMI_OPEN = 0
2253 00:43:50.803737 CA_FULL_RATE = 0
2254 00:43:50.803821 DQ_CKDIV4_EN = 0
2255 00:43:50.803904 CA_CKDIV4_EN = 0
2256 00:43:50.803985 CA_PREDIV_EN = 0
2257 00:43:50.804067 PH8_DLY = 17
2258 00:43:50.804151 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2259 00:43:50.804234 DQ_AAMCK_DIV = 4
2260 00:43:50.804318 CA_AAMCK_DIV = 4
2261 00:43:50.804401 CA_ADMCK_DIV = 4
2262 00:43:50.804483 DQ_TRACK_CA_EN = 0
2263 00:43:50.804565 CA_PICK = 1200
2264 00:43:50.804652 CA_MCKIO = 1200
2265 00:43:50.804735 MCKIO_SEMI = 0
2266 00:43:50.804820 PLL_FREQ = 2366
2267 00:43:50.804913 DQ_UI_PI_RATIO = 32
2268 00:43:50.804995 CA_UI_PI_RATIO = 0
2269 00:43:50.805078 ===================================
2270 00:43:50.805163 ===================================
2271 00:43:50.805246 memory_type:LPDDR4
2272 00:43:50.805328 GP_NUM : 10
2273 00:43:50.805385 SRAM_EN : 1
2274 00:43:50.805439 MD32_EN : 0
2275 00:43:50.805491 ===================================
2276 00:43:50.805545 [ANA_INIT] >>>>>>>>>>>>>>
2277 00:43:50.805598 <<<<<< [CONFIGURE PHASE]: ANA_TX
2278 00:43:50.805651 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2279 00:43:50.805703 ===================================
2280 00:43:50.805767 data_rate = 2400,PCW = 0X5b00
2281 00:43:50.805850 ===================================
2282 00:43:50.805936 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2283 00:43:50.806020 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2284 00:43:50.806298 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2285 00:43:50.806362 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2286 00:43:50.806422 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2287 00:43:50.806476 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2288 00:43:50.806529 [ANA_INIT] flow start
2289 00:43:50.806586 [ANA_INIT] PLL >>>>>>>>
2290 00:43:50.806641 [ANA_INIT] PLL <<<<<<<<
2291 00:43:50.806694 [ANA_INIT] MIDPI >>>>>>>>
2292 00:43:50.806746 [ANA_INIT] MIDPI <<<<<<<<
2293 00:43:50.806810 [ANA_INIT] DLL >>>>>>>>
2294 00:43:50.806863 [ANA_INIT] DLL <<<<<<<<
2295 00:43:50.806916 [ANA_INIT] flow end
2296 00:43:50.806970 ============ LP4 DIFF to SE enter ============
2297 00:43:50.807031 ============ LP4 DIFF to SE exit ============
2298 00:43:50.807085 [ANA_INIT] <<<<<<<<<<<<<
2299 00:43:50.807139 [Flow] Enable top DCM control >>>>>
2300 00:43:50.807192 [Flow] Enable top DCM control <<<<<
2301 00:43:50.807276 Enable DLL master slave shuffle
2302 00:43:50.807359 ==============================================================
2303 00:43:50.807442 Gating Mode config
2304 00:43:50.807524 ==============================================================
2305 00:43:50.807606 Config description:
2306 00:43:50.807690 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2307 00:43:50.807774 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2308 00:43:50.807878 SELPH_MODE 0: By rank 1: By Phase
2309 00:43:50.807965 ==============================================================
2310 00:43:50.808052 GAT_TRACK_EN = 1
2311 00:43:50.808135 RX_GATING_MODE = 2
2312 00:43:50.808220 RX_GATING_TRACK_MODE = 2
2313 00:43:50.808303 SELPH_MODE = 1
2314 00:43:50.808385 PICG_EARLY_EN = 1
2315 00:43:50.808470 VALID_LAT_VALUE = 1
2316 00:43:50.808553 ==============================================================
2317 00:43:50.808635 Enter into Gating configuration >>>>
2318 00:43:50.808717 Exit from Gating configuration <<<<
2319 00:43:50.808802 Enter into DVFS_PRE_config >>>>>
2320 00:43:50.808886 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2321 00:43:50.808976 Exit from DVFS_PRE_config <<<<<
2322 00:43:50.809058 Enter into PICG configuration >>>>
2323 00:43:50.809140 Exit from PICG configuration <<<<
2324 00:43:50.809222 [RX_INPUT] configuration >>>>>
2325 00:43:50.809300 [RX_INPUT] configuration <<<<<
2326 00:43:50.809355 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2327 00:43:50.809409 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2328 00:43:50.809469 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2329 00:43:50.809524 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2330 00:43:50.809578 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2331 00:43:50.809634 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2332 00:43:50.809717 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2333 00:43:50.809800 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2334 00:43:50.809882 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2335 00:43:50.809964 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2336 00:43:50.810053 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2337 00:43:50.810136 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2338 00:43:50.810252 ===================================
2339 00:43:50.810308 LPDDR4 DRAM CONFIGURATION
2340 00:43:50.810361 ===================================
2341 00:43:50.810415 EX_ROW_EN[0] = 0x0
2342 00:43:50.810476 EX_ROW_EN[1] = 0x0
2343 00:43:50.810529 LP4Y_EN = 0x0
2344 00:43:50.810583 WORK_FSP = 0x0
2345 00:43:50.810635 WL = 0x4
2346 00:43:50.810688 RL = 0x4
2347 00:43:50.810740 BL = 0x2
2348 00:43:50.810793 RPST = 0x0
2349 00:43:50.810846 RD_PRE = 0x0
2350 00:43:50.810898 WR_PRE = 0x1
2351 00:43:50.810958 WR_PST = 0x0
2352 00:43:50.811011 DBI_WR = 0x0
2353 00:43:50.811064 DBI_RD = 0x0
2354 00:43:50.811124 OTF = 0x1
2355 00:43:50.811179 ===================================
2356 00:43:50.811233 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2357 00:43:50.811287 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2358 00:43:50.811346 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2359 00:43:50.811399 ===================================
2360 00:43:50.811452 LPDDR4 DRAM CONFIGURATION
2361 00:43:50.811504 ===================================
2362 00:43:50.811556 EX_ROW_EN[0] = 0x10
2363 00:43:50.811609 EX_ROW_EN[1] = 0x0
2364 00:43:50.811661 LP4Y_EN = 0x0
2365 00:43:50.811714 WORK_FSP = 0x0
2366 00:43:50.811773 WL = 0x4
2367 00:43:50.811826 RL = 0x4
2368 00:43:50.811878 BL = 0x2
2369 00:43:50.811938 RPST = 0x0
2370 00:43:50.812020 RD_PRE = 0x0
2371 00:43:50.812101 WR_PRE = 0x1
2372 00:43:50.812181 WR_PST = 0x0
2373 00:43:50.812262 DBI_WR = 0x0
2374 00:43:50.812345 DBI_RD = 0x0
2375 00:43:50.812430 OTF = 0x1
2376 00:43:50.812511 ===================================
2377 00:43:50.812598 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2378 00:43:50.812680 ==
2379 00:43:50.812762 Dram Type= 6, Freq= 0, CH_0, rank 0
2380 00:43:50.812843 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2381 00:43:50.812924 ==
2382 00:43:50.813009 [Duty_Offset_Calibration]
2383 00:43:50.813091 B0:1 B1:-1 CA:0
2384 00:43:50.813177
2385 00:43:50.813259 [DutyScan_Calibration_Flow] k_type=0
2386 00:43:50.813340
2387 00:43:50.813420 ==CLK 0==
2388 00:43:50.813489 Final CLK duty delay cell = 0
2389 00:43:50.813543 [0] MAX Duty = 5094%(X100), DQS PI = 16
2390 00:43:50.813596 [0] MIN Duty = 4875%(X100), DQS PI = 8
2391 00:43:50.813654 [0] AVG Duty = 4984%(X100)
2392 00:43:50.813708
2393 00:43:50.813760 CH0 CLK Duty spec in!! Max-Min= 219%
2394 00:43:50.813813 [DutyScan_Calibration_Flow] ====Done====
2395 00:43:50.813865
2396 00:43:50.813917 [DutyScan_Calibration_Flow] k_type=1
2397 00:43:50.813970
2398 00:43:50.814052 ==DQS 0 ==
2399 00:43:50.814134 Final DQS duty delay cell = -4
2400 00:43:50.814246 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2401 00:43:50.814495 [-4] MIN Duty = 4875%(X100), DQS PI = 54
2402 00:43:50.814555 [-4] AVG Duty = 4968%(X100)
2403 00:43:50.814609
2404 00:43:50.814669 ==DQS 1 ==
2405 00:43:50.814724 Final DQS duty delay cell = 0
2406 00:43:50.814778 [0] MAX Duty = 5124%(X100), DQS PI = 6
2407 00:43:50.814831 [0] MIN Duty = 5000%(X100), DQS PI = 20
2408 00:43:50.814890 [0] AVG Duty = 5062%(X100)
2409 00:43:50.814943
2410 00:43:50.814995 CH0 DQS 0 Duty spec in!! Max-Min= 187%
2411 00:43:50.815048
2412 00:43:50.815100 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2413 00:43:50.815152 [DutyScan_Calibration_Flow] ====Done====
2414 00:43:50.815218
2415 00:43:50.815272 [DutyScan_Calibration_Flow] k_type=3
2416 00:43:50.815325
2417 00:43:50.815382 ==DQM 0 ==
2418 00:43:50.815436 Final DQM duty delay cell = 0
2419 00:43:50.815489 [0] MAX Duty = 5062%(X100), DQS PI = 18
2420 00:43:50.815542 [0] MIN Duty = 4844%(X100), DQS PI = 8
2421 00:43:50.815595 [0] AVG Duty = 4953%(X100)
2422 00:43:50.815679
2423 00:43:50.815758 ==DQM 1 ==
2424 00:43:50.815840 Final DQM duty delay cell = 4
2425 00:43:50.815926 [4] MAX Duty = 5187%(X100), DQS PI = 56
2426 00:43:50.816008 [4] MIN Duty = 4969%(X100), DQS PI = 24
2427 00:43:50.816094 [4] AVG Duty = 5078%(X100)
2428 00:43:50.816175
2429 00:43:50.816257 CH0 DQM 0 Duty spec in!! Max-Min= 218%
2430 00:43:50.816338
2431 00:43:50.816425 CH0 DQM 1 Duty spec in!! Max-Min= 218%
2432 00:43:50.816508 [DutyScan_Calibration_Flow] ====Done====
2433 00:43:50.816592
2434 00:43:50.816673 [DutyScan_Calibration_Flow] k_type=2
2435 00:43:50.816754
2436 00:43:50.816835 ==DQ 0 ==
2437 00:43:50.816920 Final DQ duty delay cell = -4
2438 00:43:50.817003 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2439 00:43:50.817088 [-4] MIN Duty = 4875%(X100), DQS PI = 52
2440 00:43:50.817170 [-4] AVG Duty = 4953%(X100)
2441 00:43:50.817251
2442 00:43:50.817331 ==DQ 1 ==
2443 00:43:50.817391 Final DQ duty delay cell = 0
2444 00:43:50.817445 [0] MAX Duty = 5125%(X100), DQS PI = 50
2445 00:43:50.817498 [0] MIN Duty = 4969%(X100), DQS PI = 40
2446 00:43:50.817561 [0] AVG Duty = 5047%(X100)
2447 00:43:50.817617
2448 00:43:50.817669 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2449 00:43:50.817746
2450 00:43:50.817829 CH0 DQ 1 Duty spec in!! Max-Min= 156%
2451 00:43:50.817915 [DutyScan_Calibration_Flow] ====Done====
2452 00:43:50.817996 ==
2453 00:43:50.818081 Dram Type= 6, Freq= 0, CH_1, rank 0
2454 00:43:50.818169 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2455 00:43:50.818259 ==
2456 00:43:50.818313 [Duty_Offset_Calibration]
2457 00:43:50.818366 B0:-1 B1:1 CA:1
2458 00:43:50.818424
2459 00:43:50.818477 [DutyScan_Calibration_Flow] k_type=0
2460 00:43:50.818530
2461 00:43:50.818594 ==CLK 0==
2462 00:43:50.818648 Final CLK duty delay cell = 0
2463 00:43:50.818701 [0] MAX Duty = 5156%(X100), DQS PI = 4
2464 00:43:50.818754 [0] MIN Duty = 5000%(X100), DQS PI = 28
2465 00:43:50.818812 [0] AVG Duty = 5078%(X100)
2466 00:43:50.818866
2467 00:43:50.818918 CH1 CLK Duty spec in!! Max-Min= 156%
2468 00:43:50.818971 [DutyScan_Calibration_Flow] ====Done====
2469 00:43:50.819023
2470 00:43:50.819075 [DutyScan_Calibration_Flow] k_type=1
2471 00:43:50.819135
2472 00:43:50.819188 ==DQS 0 ==
2473 00:43:50.819241 Final DQS duty delay cell = 0
2474 00:43:50.819301 [0] MAX Duty = 5125%(X100), DQS PI = 18
2475 00:43:50.819355 [0] MIN Duty = 4875%(X100), DQS PI = 38
2476 00:43:50.819407 [0] AVG Duty = 5000%(X100)
2477 00:43:50.819460
2478 00:43:50.819518 ==DQS 1 ==
2479 00:43:50.819601 Final DQS duty delay cell = 0
2480 00:43:50.819713 [0] MAX Duty = 5094%(X100), DQS PI = 44
2481 00:43:50.819795 [0] MIN Duty = 4969%(X100), DQS PI = 26
2482 00:43:50.819882 [0] AVG Duty = 5031%(X100)
2483 00:43:50.819967
2484 00:43:50.820052 CH1 DQS 0 Duty spec in!! Max-Min= 250%
2485 00:43:50.820133
2486 00:43:50.820214 CH1 DQS 1 Duty spec in!! Max-Min= 125%
2487 00:43:50.820300 [DutyScan_Calibration_Flow] ====Done====
2488 00:43:50.820381
2489 00:43:50.820462 [DutyScan_Calibration_Flow] k_type=3
2490 00:43:50.820544
2491 00:43:50.820628 ==DQM 0 ==
2492 00:43:50.820710 Final DQM duty delay cell = -4
2493 00:43:50.820796 [-4] MAX Duty = 5031%(X100), DQS PI = 2
2494 00:43:50.820878 [-4] MIN Duty = 4844%(X100), DQS PI = 38
2495 00:43:50.820959 [-4] AVG Duty = 4937%(X100)
2496 00:43:50.821046
2497 00:43:50.821128 ==DQM 1 ==
2498 00:43:50.821209 Final DQM duty delay cell = 0
2499 00:43:50.821292 [0] MAX Duty = 5187%(X100), DQS PI = 36
2500 00:43:50.821348 [0] MIN Duty = 4969%(X100), DQS PI = 0
2501 00:43:50.821401 [0] AVG Duty = 5078%(X100)
2502 00:43:50.821453
2503 00:43:50.821513 CH1 DQM 0 Duty spec in!! Max-Min= 187%
2504 00:43:50.821566
2505 00:43:50.821618 CH1 DQM 1 Duty spec in!! Max-Min= 218%
2506 00:43:50.821670 [DutyScan_Calibration_Flow] ====Done====
2507 00:43:50.821728
2508 00:43:50.821810 [DutyScan_Calibration_Flow] k_type=2
2509 00:43:50.821891
2510 00:43:50.821974 ==DQ 0 ==
2511 00:43:50.822056 Final DQ duty delay cell = 0
2512 00:43:50.822139 [0] MAX Duty = 5156%(X100), DQS PI = 60
2513 00:43:50.822256 [0] MIN Duty = 4907%(X100), DQS PI = 36
2514 00:43:50.822324 [0] AVG Duty = 5031%(X100)
2515 00:43:50.822378
2516 00:43:50.822431 ==DQ 1 ==
2517 00:43:50.822483 Final DQ duty delay cell = 0
2518 00:43:50.822540 [0] MAX Duty = 5124%(X100), DQS PI = 42
2519 00:43:50.822595 [0] MIN Duty = 4969%(X100), DQS PI = 0
2520 00:43:50.822648 [0] AVG Duty = 5046%(X100)
2521 00:43:50.822699
2522 00:43:50.822757 CH1 DQ 0 Duty spec in!! Max-Min= 249%
2523 00:43:50.822810
2524 00:43:50.822862 CH1 DQ 1 Duty spec in!! Max-Min= 155%
2525 00:43:50.822915 [DutyScan_Calibration_Flow] ====Done====
2526 00:43:50.822974 nWR fixed to 30
2527 00:43:50.823029 [ModeRegInit_LP4] CH0 RK0
2528 00:43:50.823082 [ModeRegInit_LP4] CH0 RK1
2529 00:43:50.823134 [ModeRegInit_LP4] CH1 RK0
2530 00:43:50.823185 [ModeRegInit_LP4] CH1 RK1
2531 00:43:50.823238 match AC timing 7
2532 00:43:50.823301 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2533 00:43:50.823356 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2534 00:43:50.823409 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2535 00:43:50.823474 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2536 00:43:50.823558 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2537 00:43:50.823639 ==
2538 00:43:50.823725 Dram Type= 6, Freq= 0, CH_0, rank 0
2539 00:43:50.823807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2540 00:43:50.823889 ==
2541 00:43:50.823971 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2542 00:43:50.824060 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2543 00:43:50.824142 [CA 0] Center 39 (9~70) winsize 62
2544 00:43:50.824228 [CA 1] Center 39 (9~69) winsize 61
2545 00:43:50.824309 [CA 2] Center 35 (5~66) winsize 62
2546 00:43:50.824391 [CA 3] Center 35 (4~66) winsize 63
2547 00:43:50.824475 [CA 4] Center 33 (4~63) winsize 60
2548 00:43:50.824556 [CA 5] Center 33 (3~63) winsize 61
2549 00:43:50.824637
2550 00:43:50.824720 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2551 00:43:50.824802
2552 00:43:50.824883 [CATrainingPosCal] consider 1 rank data
2553 00:43:50.824964 u2DelayCellTimex100 = 270/100 ps
2554 00:43:50.825246 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2555 00:43:50.825308 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2556 00:43:50.825363 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2557 00:43:50.825422 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2558 00:43:50.825476 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
2559 00:43:50.825529 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2560 00:43:50.825581
2561 00:43:50.825634 CA PerBit enable=1, Macro0, CA PI delay=33
2562 00:43:50.825686
2563 00:43:50.825746 [CBTSetCACLKResult] CA Dly = 33
2564 00:43:50.825828 CS Dly: 8 (0~39)
2565 00:43:50.825912 ==
2566 00:43:50.825995 Dram Type= 6, Freq= 0, CH_0, rank 1
2567 00:43:50.826077 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2568 00:43:50.826188 ==
2569 00:43:50.826261 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2570 00:43:50.826315 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2571 00:43:50.826370 [CA 0] Center 39 (9~70) winsize 62
2572 00:43:50.826423 [CA 1] Center 39 (9~70) winsize 62
2573 00:43:50.826475 [CA 2] Center 35 (4~66) winsize 63
2574 00:43:50.826535 [CA 3] Center 34 (4~65) winsize 62
2575 00:43:50.826589 [CA 4] Center 33 (3~63) winsize 61
2576 00:43:50.826641 [CA 5] Center 33 (3~63) winsize 61
2577 00:43:50.826700
2578 00:43:50.826753 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2579 00:43:50.826806
2580 00:43:50.826858 [CATrainingPosCal] consider 2 rank data
2581 00:43:50.826914 u2DelayCellTimex100 = 270/100 ps
2582 00:43:50.826968 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2583 00:43:50.827020 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2584 00:43:50.827073 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2585 00:43:50.827125 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
2586 00:43:50.827177 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
2587 00:43:50.827229 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2588 00:43:50.827293
2589 00:43:50.827347 CA PerBit enable=1, Macro0, CA PI delay=33
2590 00:43:50.827399
2591 00:43:50.827458 [CBTSetCACLKResult] CA Dly = 33
2592 00:43:50.827541 CS Dly: 8 (0~40)
2593 00:43:50.827622
2594 00:43:50.827707 ----->DramcWriteLeveling(PI) begin...
2595 00:43:50.827789 ==
2596 00:43:50.827871 Dram Type= 6, Freq= 0, CH_0, rank 0
2597 00:43:50.827954 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2598 00:43:50.828038 ==
2599 00:43:50.828120 Write leveling (Byte 0): 31 => 31
2600 00:43:50.828205 Write leveling (Byte 1): 29 => 29
2601 00:43:50.828287 DramcWriteLeveling(PI) end<-----
2602 00:43:50.828367
2603 00:43:50.828448 ==
2604 00:43:50.828535 Dram Type= 6, Freq= 0, CH_0, rank 0
2605 00:43:50.828617 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2606 00:43:50.828702 ==
2607 00:43:50.828784 [Gating] SW mode calibration
2608 00:43:50.828866 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2609 00:43:50.828949 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2610 00:43:50.829031 0 15 0 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (1 1)
2611 00:43:50.829119 0 15 4 | B1->B0 | 2525 3434 | 1 1 | (1 1) (1 1)
2612 00:43:50.829201 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2613 00:43:50.829281 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2614 00:43:50.829336 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2615 00:43:50.829389 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2616 00:43:50.829441 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2617 00:43:50.829493 0 15 28 | B1->B0 | 3434 2d2d | 1 0 | (1 1) (1 0)
2618 00:43:50.829546 1 0 0 | B1->B0 | 3131 2323 | 1 0 | (1 0) (0 0)
2619 00:43:50.829598 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2620 00:43:50.829650 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2621 00:43:50.829720 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2622 00:43:50.829803 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2623 00:43:50.829884 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2624 00:43:50.829966 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2625 00:43:50.830048 1 0 28 | B1->B0 | 2323 3d3c | 0 1 | (0 0) (0 0)
2626 00:43:50.830134 1 1 0 | B1->B0 | 2424 4545 | 0 0 | (0 0) (0 0)
2627 00:43:50.830237 1 1 4 | B1->B0 | 4040 4646 | 1 0 | (0 0) (0 0)
2628 00:43:50.830291 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2629 00:43:50.830343 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2630 00:43:50.830401 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2631 00:43:50.830455 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2632 00:43:50.830508 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2633 00:43:50.830561 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
2634 00:43:50.830613 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2635 00:43:50.830672 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2636 00:43:50.830725 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2637 00:43:50.830778 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2638 00:43:50.830838 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2639 00:43:50.830893 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2640 00:43:50.830946 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2641 00:43:50.830998 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2642 00:43:50.831057 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2643 00:43:50.831111 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2644 00:43:50.831164 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2645 00:43:50.831239 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2646 00:43:50.831321 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2647 00:43:50.831403 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2648 00:43:50.831488 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2649 00:43:50.831570 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2650 00:43:50.831651 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2651 00:43:50.831732 Total UI for P1: 0, mck2ui 16
2652 00:43:50.831815 best dqsien dly found for B0: ( 1, 3, 28)
2653 00:43:50.831903 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2654 00:43:50.831985 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2655 00:43:50.832069 Total UI for P1: 0, mck2ui 16
2656 00:43:50.832348 best dqsien dly found for B1: ( 1, 4, 2)
2657 00:43:50.832434 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2658 00:43:50.832516 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2659 00:43:50.832601
2660 00:43:50.832683 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2661 00:43:50.832769 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2662 00:43:50.832851 [Gating] SW calibration Done
2663 00:43:50.832932 ==
2664 00:43:50.833014 Dram Type= 6, Freq= 0, CH_0, rank 0
2665 00:43:50.833095 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2666 00:43:50.833183 ==
2667 00:43:50.833265 RX Vref Scan: 0
2668 00:43:50.833344
2669 00:43:50.833398 RX Vref 0 -> 0, step: 1
2670 00:43:50.833450
2671 00:43:50.833507 RX Delay -40 -> 252, step: 8
2672 00:43:50.833561 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2673 00:43:50.833614 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2674 00:43:50.833667 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2675 00:43:50.833725 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2676 00:43:50.833808 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2677 00:43:50.833889 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2678 00:43:50.833971 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2679 00:43:50.834055 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2680 00:43:50.834137 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2681 00:43:50.834253 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2682 00:43:50.834308 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2683 00:43:50.834361 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2684 00:43:50.834414 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2685 00:43:50.834467 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2686 00:43:50.834525 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2687 00:43:50.834577 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2688 00:43:50.834629 ==
2689 00:43:50.834681 Dram Type= 6, Freq= 0, CH_0, rank 0
2690 00:43:50.834740 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2691 00:43:50.834794 ==
2692 00:43:50.834847 DQS Delay:
2693 00:43:50.834899 DQS0 = 0, DQS1 = 0
2694 00:43:50.834951 DQM Delay:
2695 00:43:50.835003 DQM0 = 118, DQM1 = 107
2696 00:43:50.835062 DQ Delay:
2697 00:43:50.835116 DQ0 =119, DQ1 =119, DQ2 =115, DQ3 =115
2698 00:43:50.835168 DQ4 =119, DQ5 =111, DQ6 =127, DQ7 =123
2699 00:43:50.835226 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =103
2700 00:43:50.835280 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2701 00:43:50.835332
2702 00:43:50.835384
2703 00:43:50.835436 ==
2704 00:43:50.835488 Dram Type= 6, Freq= 0, CH_0, rank 0
2705 00:43:50.835540 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2706 00:43:50.835625 ==
2707 00:43:50.835706
2708 00:43:50.835790
2709 00:43:50.835871 TX Vref Scan disable
2710 00:43:50.835952 == TX Byte 0 ==
2711 00:43:50.836033 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2712 00:43:50.836119 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2713 00:43:50.836200 == TX Byte 1 ==
2714 00:43:50.836286 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2715 00:43:50.836368 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2716 00:43:50.836452 ==
2717 00:43:50.836534 Dram Type= 6, Freq= 0, CH_0, rank 0
2718 00:43:50.836615 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2719 00:43:50.836696 ==
2720 00:43:50.836781 TX Vref=22, minBit 3, minWin=25, winSum=414
2721 00:43:50.836864 TX Vref=24, minBit 3, minWin=25, winSum=421
2722 00:43:50.836950 TX Vref=26, minBit 0, minWin=26, winSum=424
2723 00:43:50.837033 TX Vref=28, minBit 4, minWin=26, winSum=431
2724 00:43:50.837115 TX Vref=30, minBit 4, minWin=26, winSum=429
2725 00:43:50.837196 TX Vref=32, minBit 5, minWin=26, winSum=430
2726 00:43:50.837268 [TxChooseVref] Worse bit 4, Min win 26, Win sum 431, Final Vref 28
2727 00:43:50.837322
2728 00:43:50.837375 Final TX Range 1 Vref 28
2729 00:43:50.837432
2730 00:43:50.837485 ==
2731 00:43:50.837537 Dram Type= 6, Freq= 0, CH_0, rank 0
2732 00:43:50.837590 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2733 00:43:50.837642 ==
2734 00:43:50.837694
2735 00:43:50.837761
2736 00:43:50.837842 TX Vref Scan disable
2737 00:43:50.837926 == TX Byte 0 ==
2738 00:43:50.838008 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2739 00:43:50.838090 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2740 00:43:50.838183 == TX Byte 1 ==
2741 00:43:50.838280 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2742 00:43:50.838334 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2743 00:43:50.838387
2744 00:43:50.838447 [DATLAT]
2745 00:43:50.838500 Freq=1200, CH0 RK0
2746 00:43:50.838552
2747 00:43:50.838604 DATLAT Default: 0xd
2748 00:43:50.838662 0, 0xFFFF, sum = 0
2749 00:43:50.838718 1, 0xFFFF, sum = 0
2750 00:43:50.838771 2, 0xFFFF, sum = 0
2751 00:43:50.838824 3, 0xFFFF, sum = 0
2752 00:43:50.838877 4, 0xFFFF, sum = 0
2753 00:43:50.838930 5, 0xFFFF, sum = 0
2754 00:43:50.838986 6, 0xFFFF, sum = 0
2755 00:43:50.839041 7, 0xFFFF, sum = 0
2756 00:43:50.839095 8, 0xFFFF, sum = 0
2757 00:43:50.839148 9, 0xFFFF, sum = 0
2758 00:43:50.839206 10, 0xFFFF, sum = 0
2759 00:43:50.839260 11, 0xFFFF, sum = 0
2760 00:43:50.839313 12, 0x0, sum = 1
2761 00:43:50.839366 13, 0x0, sum = 2
2762 00:43:50.839418 14, 0x0, sum = 3
2763 00:43:50.839472 15, 0x0, sum = 4
2764 00:43:50.839525 best_step = 13
2765 00:43:50.839577
2766 00:43:50.839638 ==
2767 00:43:50.839691 Dram Type= 6, Freq= 0, CH_0, rank 0
2768 00:43:50.839744 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2769 00:43:50.839804 ==
2770 00:43:50.839857 RX Vref Scan: 1
2771 00:43:50.839909
2772 00:43:50.839961 Set Vref Range= 32 -> 127
2773 00:43:50.840016
2774 00:43:50.840068 RX Vref 32 -> 127, step: 1
2775 00:43:50.840119
2776 00:43:50.840171 RX Delay -21 -> 252, step: 4
2777 00:43:50.840227
2778 00:43:50.840280 Set Vref, RX VrefLevel [Byte0]: 32
2779 00:43:50.840332 [Byte1]: 32
2780 00:43:50.840386
2781 00:43:50.840443 Set Vref, RX VrefLevel [Byte0]: 33
2782 00:43:50.840495 [Byte1]: 33
2783 00:43:50.840547
2784 00:43:50.840599 Set Vref, RX VrefLevel [Byte0]: 34
2785 00:43:50.840651 [Byte1]: 34
2786 00:43:50.840703
2787 00:43:50.840754 Set Vref, RX VrefLevel [Byte0]: 35
2788 00:43:50.840806 [Byte1]: 35
2789 00:43:50.840866
2790 00:43:50.840918 Set Vref, RX VrefLevel [Byte0]: 36
2791 00:43:50.840971 [Byte1]: 36
2792 00:43:50.841026
2793 00:43:50.841080 Set Vref, RX VrefLevel [Byte0]: 37
2794 00:43:50.841132 [Byte1]: 37
2795 00:43:50.841185
2796 00:43:50.841236 Set Vref, RX VrefLevel [Byte0]: 38
2797 00:43:50.841288 [Byte1]: 38
2798 00:43:50.841340
2799 00:43:50.841399 Set Vref, RX VrefLevel [Byte0]: 39
2800 00:43:50.841452 [Byte1]: 39
2801 00:43:50.841503
2802 00:43:50.841561 Set Vref, RX VrefLevel [Byte0]: 40
2803 00:43:50.841614 [Byte1]: 40
2804 00:43:50.841667
2805 00:43:50.841718 Set Vref, RX VrefLevel [Byte0]: 41
2806 00:43:50.841776 [Byte1]: 41
2807 00:43:50.841829
2808 00:43:50.841881 Set Vref, RX VrefLevel [Byte0]: 42
2809 00:43:50.841934 [Byte1]: 42
2810 00:43:50.841986
2811 00:43:50.842039 Set Vref, RX VrefLevel [Byte0]: 43
2812 00:43:50.842321 [Byte1]: 43
2813 00:43:50.842383
2814 00:43:50.842437 Set Vref, RX VrefLevel [Byte0]: 44
2815 00:43:50.842491 [Byte1]: 44
2816 00:43:50.842543
2817 00:43:50.842603 Set Vref, RX VrefLevel [Byte0]: 45
2818 00:43:50.842657 [Byte1]: 45
2819 00:43:50.842709
2820 00:43:50.842766 Set Vref, RX VrefLevel [Byte0]: 46
2821 00:43:50.842820 [Byte1]: 46
2822 00:43:50.842872
2823 00:43:50.842924 Set Vref, RX VrefLevel [Byte0]: 47
2824 00:43:50.842981 [Byte1]: 47
2825 00:43:50.843034
2826 00:43:50.843087 Set Vref, RX VrefLevel [Byte0]: 48
2827 00:43:50.843139 [Byte1]: 48
2828 00:43:50.843191
2829 00:43:50.843242 Set Vref, RX VrefLevel [Byte0]: 49
2830 00:43:50.843302 [Byte1]: 49
2831 00:43:50.843355
2832 00:43:50.843407 Set Vref, RX VrefLevel [Byte0]: 50
2833 00:43:50.843465 [Byte1]: 50
2834 00:43:50.843519
2835 00:43:50.843571 Set Vref, RX VrefLevel [Byte0]: 51
2836 00:43:50.843623 [Byte1]: 51
2837 00:43:50.843675
2838 00:43:50.843726 Set Vref, RX VrefLevel [Byte0]: 52
2839 00:43:50.843782 [Byte1]: 52
2840 00:43:50.843837
2841 00:43:50.843889 Set Vref, RX VrefLevel [Byte0]: 53
2842 00:43:50.843941 [Byte1]: 53
2843 00:43:50.844000
2844 00:43:50.844053 Set Vref, RX VrefLevel [Byte0]: 54
2845 00:43:50.844105 [Byte1]: 54
2846 00:43:50.844158
2847 00:43:50.844209 Set Vref, RX VrefLevel [Byte0]: 55
2848 00:43:50.844262 [Byte1]: 55
2849 00:43:50.844314
2850 00:43:50.844366 Set Vref, RX VrefLevel [Byte0]: 56
2851 00:43:50.844427 [Byte1]: 56
2852 00:43:50.844480
2853 00:43:50.844532 Set Vref, RX VrefLevel [Byte0]: 57
2854 00:43:50.844589 [Byte1]: 57
2855 00:43:50.844643
2856 00:43:50.844695 Set Vref, RX VrefLevel [Byte0]: 58
2857 00:43:50.844747 [Byte1]: 58
2858 00:43:50.844799
2859 00:43:50.844851 Set Vref, RX VrefLevel [Byte0]: 59
2860 00:43:50.844903 [Byte1]: 59
2861 00:43:50.844955
2862 00:43:50.845011 Set Vref, RX VrefLevel [Byte0]: 60
2863 00:43:50.845066 [Byte1]: 60
2864 00:43:50.845118
2865 00:43:50.845170 Set Vref, RX VrefLevel [Byte0]: 61
2866 00:43:50.845230 [Byte1]: 61
2867 00:43:50.845283
2868 00:43:50.845335 Set Vref, RX VrefLevel [Byte0]: 62
2869 00:43:50.845387 [Byte1]: 62
2870 00:43:50.845439
2871 00:43:50.845491 Set Vref, RX VrefLevel [Byte0]: 63
2872 00:43:50.845547 [Byte1]: 63
2873 00:43:50.845601
2874 00:43:50.845654 Set Vref, RX VrefLevel [Byte0]: 64
2875 00:43:50.845706 [Byte1]: 64
2876 00:43:50.845765
2877 00:43:50.845817 Set Vref, RX VrefLevel [Byte0]: 65
2878 00:43:50.845869 [Byte1]: 65
2879 00:43:50.845928
2880 00:43:50.845981 Set Vref, RX VrefLevel [Byte0]: 66
2881 00:43:50.846033 [Byte1]: 66
2882 00:43:50.846085
2883 00:43:50.846137 Set Vref, RX VrefLevel [Byte0]: 67
2884 00:43:50.846255 [Byte1]: 67
2885 00:43:50.846310
2886 00:43:50.846363 Set Vref, RX VrefLevel [Byte0]: 68
2887 00:43:50.846416 [Byte1]: 68
2888 00:43:50.846474
2889 00:43:50.846526 Set Vref, RX VrefLevel [Byte0]: 69
2890 00:43:50.846579 [Byte1]: 69
2891 00:43:50.846632
2892 00:43:50.846690 Set Vref, RX VrefLevel [Byte0]: 70
2893 00:43:50.846744 [Byte1]: 70
2894 00:43:50.846797
2895 00:43:50.846849 Set Vref, RX VrefLevel [Byte0]: 71
2896 00:43:50.846901 [Byte1]: 71
2897 00:43:50.846956
2898 00:43:50.847011 Set Vref, RX VrefLevel [Byte0]: 72
2899 00:43:50.847063 [Byte1]: 72
2900 00:43:50.847115
2901 00:43:50.847174 Set Vref, RX VrefLevel [Byte0]: 73
2902 00:43:50.847226 [Byte1]: 73
2903 00:43:50.847278
2904 00:43:50.847331 Set Vref, RX VrefLevel [Byte0]: 74
2905 00:43:50.847387 [Byte1]: 74
2906 00:43:50.847441
2907 00:43:50.847493 Set Vref, RX VrefLevel [Byte0]: 75
2908 00:43:50.847545 [Byte1]: 75
2909 00:43:50.847597
2910 00:43:50.847656 Set Vref, RX VrefLevel [Byte0]: 76
2911 00:43:50.847709 [Byte1]: 76
2912 00:43:50.847761
2913 00:43:50.847813 Final RX Vref Byte 0 = 60 to rank0
2914 00:43:50.847865 Final RX Vref Byte 1 = 55 to rank0
2915 00:43:50.847917 Final RX Vref Byte 0 = 60 to rank1
2916 00:43:50.847978 Final RX Vref Byte 1 = 55 to rank1==
2917 00:43:50.848035 Dram Type= 6, Freq= 0, CH_0, rank 0
2918 00:43:50.848088 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2919 00:43:50.848147 ==
2920 00:43:50.848201 DQS Delay:
2921 00:43:50.848254 DQS0 = 0, DQS1 = 0
2922 00:43:50.848306 DQM Delay:
2923 00:43:50.848362 DQM0 = 119, DQM1 = 107
2924 00:43:50.848416 DQ Delay:
2925 00:43:50.848469 DQ0 =116, DQ1 =120, DQ2 =116, DQ3 =116
2926 00:43:50.848521 DQ4 =120, DQ5 =114, DQ6 =126, DQ7 =126
2927 00:43:50.848574 DQ8 =98, DQ9 =94, DQ10 =110, DQ11 =102
2928 00:43:50.848626 DQ12 =112, DQ13 =110, DQ14 =120, DQ15 =116
2929 00:43:50.848678
2930 00:43:50.848730
2931 00:43:50.848782 [DQSOSCAuto] RK0, (LSB)MR18= 0x14ff, (MSB)MR19= 0x403, tDQSOscB0 = 410 ps tDQSOscB1 = 402 ps
2932 00:43:50.848835 CH0 RK0: MR19=403, MR18=14FF
2933 00:43:50.848887 CH0_RK0: MR19=0x403, MR18=0x14FF, DQSOSC=402, MR23=63, INC=40, DEC=27
2934 00:43:50.848941
2935 00:43:50.848994 ----->DramcWriteLeveling(PI) begin...
2936 00:43:50.849047 ==
2937 00:43:50.849100 Dram Type= 6, Freq= 0, CH_0, rank 1
2938 00:43:50.849152 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2939 00:43:50.849205 ==
2940 00:43:50.849257 Write leveling (Byte 0): 33 => 33
2941 00:43:50.849309 Write leveling (Byte 1): 30 => 30
2942 00:43:50.849361 DramcWriteLeveling(PI) end<-----
2943 00:43:50.849413
2944 00:43:50.849464 ==
2945 00:43:50.849516 Dram Type= 6, Freq= 0, CH_0, rank 1
2946 00:43:50.849568 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2947 00:43:50.849620 ==
2948 00:43:50.849672 [Gating] SW mode calibration
2949 00:43:50.849724 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2950 00:43:50.849793 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2951 00:43:50.849849 0 15 0 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
2952 00:43:50.849902 0 15 4 | B1->B0 | 3030 3434 | 1 1 | (0 0) (1 1)
2953 00:43:50.849954 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2954 00:43:50.850006 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2955 00:43:50.850058 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2956 00:43:50.850111 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2957 00:43:50.850169 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2958 00:43:50.850448 0 15 28 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
2959 00:43:50.850506 1 0 0 | B1->B0 | 2e2e 2323 | 1 0 | (1 0) (0 0)
2960 00:43:50.850559 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2961 00:43:50.850612 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2962 00:43:50.850664 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2963 00:43:50.850717 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2964 00:43:50.850769 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2965 00:43:50.850820 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2966 00:43:50.850873 1 0 28 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
2967 00:43:50.850925 1 1 0 | B1->B0 | 3636 4646 | 0 0 | (0 0) (0 0)
2968 00:43:50.850977 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2969 00:43:50.851029 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2970 00:43:50.851083 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2971 00:43:50.851136 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2972 00:43:50.851188 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2973 00:43:50.851240 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2974 00:43:50.851292 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2975 00:43:50.851344 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2976 00:43:50.851396 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2977 00:43:50.851450 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2978 00:43:50.851502 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2979 00:43:50.851554 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2980 00:43:50.851606 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2981 00:43:50.851658 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2982 00:43:50.851710 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2983 00:43:50.851762 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2984 00:43:50.851814 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2985 00:43:50.851866 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2986 00:43:50.851921 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2987 00:43:50.851973 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2988 00:43:50.852025 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2989 00:43:50.852077 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2990 00:43:50.852129 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2991 00:43:50.852181 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2992 00:43:50.852233 Total UI for P1: 0, mck2ui 16
2993 00:43:50.852285 best dqsien dly found for B0: ( 1, 3, 26)
2994 00:43:50.852338 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2995 00:43:50.852390 Total UI for P1: 0, mck2ui 16
2996 00:43:50.852442 best dqsien dly found for B1: ( 1, 4, 0)
2997 00:43:50.852494 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2998 00:43:50.852546 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2999 00:43:50.852598
3000 00:43:50.852649 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3001 00:43:50.852701 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
3002 00:43:50.852753 [Gating] SW calibration Done
3003 00:43:50.852805 ==
3004 00:43:50.852857 Dram Type= 6, Freq= 0, CH_0, rank 1
3005 00:43:50.981006 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3006 00:43:50.981179 ==
3007 00:43:50.981279 RX Vref Scan: 0
3008 00:43:50.981374
3009 00:43:50.981452 RX Vref 0 -> 0, step: 1
3010 00:43:50.981513
3011 00:43:50.981572 RX Delay -40 -> 252, step: 8
3012 00:43:50.981631 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
3013 00:43:50.981697 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
3014 00:43:50.981756 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
3015 00:43:50.981813 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3016 00:43:50.981872 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3017 00:43:50.981943 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
3018 00:43:50.982031 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3019 00:43:50.982119 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
3020 00:43:50.982224 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3021 00:43:50.982285 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3022 00:43:50.982343 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3023 00:43:50.982400 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3024 00:43:50.982457 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
3025 00:43:50.982514 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
3026 00:43:50.982571 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3027 00:43:50.982643 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
3028 00:43:50.982738 ==
3029 00:43:50.982798 Dram Type= 6, Freq= 0, CH_0, rank 1
3030 00:43:50.982856 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3031 00:43:50.982914 ==
3032 00:43:50.982970 DQS Delay:
3033 00:43:50.983027 DQS0 = 0, DQS1 = 0
3034 00:43:50.983084 DQM Delay:
3035 00:43:50.983140 DQM0 = 116, DQM1 = 108
3036 00:43:50.983196 DQ Delay:
3037 00:43:50.983252 DQ0 =111, DQ1 =119, DQ2 =111, DQ3 =115
3038 00:43:50.983309 DQ4 =119, DQ5 =111, DQ6 =123, DQ7 =123
3039 00:43:50.983365 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =103
3040 00:43:50.983421 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =115
3041 00:43:50.983476
3042 00:43:50.983534
3043 00:43:50.983594 ==
3044 00:43:50.983651 Dram Type= 6, Freq= 0, CH_0, rank 1
3045 00:43:50.983711 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3046 00:43:50.983772 ==
3047 00:43:50.983828
3048 00:43:50.983884
3049 00:43:50.983939 TX Vref Scan disable
3050 00:43:50.983996 == TX Byte 0 ==
3051 00:43:50.984051 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
3052 00:43:50.984113 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
3053 00:43:50.984171 == TX Byte 1 ==
3054 00:43:50.984228 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3055 00:43:50.984284 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3056 00:43:50.984356 ==
3057 00:43:50.984417 Dram Type= 6, Freq= 0, CH_0, rank 1
3058 00:43:50.984477 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3059 00:43:50.984572 ==
3060 00:43:50.984667 TX Vref=22, minBit 1, minWin=25, winSum=417
3061 00:43:50.984766 TX Vref=24, minBit 8, minWin=25, winSum=425
3062 00:43:50.984861 TX Vref=26, minBit 2, minWin=26, winSum=428
3063 00:43:50.984955 TX Vref=28, minBit 1, minWin=26, winSum=430
3064 00:43:50.985054 TX Vref=30, minBit 10, minWin=26, winSum=431
3065 00:43:50.985363 TX Vref=32, minBit 1, minWin=26, winSum=430
3066 00:43:50.985435 [TxChooseVref] Worse bit 10, Min win 26, Win sum 431, Final Vref 30
3067 00:43:50.985498
3068 00:43:50.985567 Final TX Range 1 Vref 30
3069 00:43:50.985629
3070 00:43:50.985692 ==
3071 00:43:50.985789 Dram Type= 6, Freq= 0, CH_0, rank 1
3072 00:43:50.985884 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3073 00:43:50.985978 ==
3074 00:43:50.986071
3075 00:43:50.986171
3076 00:43:50.986237 TX Vref Scan disable
3077 00:43:50.986298 == TX Byte 0 ==
3078 00:43:50.986359 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
3079 00:43:50.986426 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
3080 00:43:50.986489 == TX Byte 1 ==
3081 00:43:50.986549 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3082 00:43:50.986610 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3083 00:43:50.986671
3084 00:43:50.986737 [DATLAT]
3085 00:43:50.986797 Freq=1200, CH0 RK1
3086 00:43:50.986858
3087 00:43:50.986926 DATLAT Default: 0xd
3088 00:43:50.986988 0, 0xFFFF, sum = 0
3089 00:43:50.987050 1, 0xFFFF, sum = 0
3090 00:43:50.987120 2, 0xFFFF, sum = 0
3091 00:43:50.987183 3, 0xFFFF, sum = 0
3092 00:43:50.987244 4, 0xFFFF, sum = 0
3093 00:43:50.987311 5, 0xFFFF, sum = 0
3094 00:43:50.987375 6, 0xFFFF, sum = 0
3095 00:43:50.987437 7, 0xFFFF, sum = 0
3096 00:43:50.987499 8, 0xFFFF, sum = 0
3097 00:43:50.987570 9, 0xFFFF, sum = 0
3098 00:43:50.987686 10, 0xFFFF, sum = 0
3099 00:43:50.987785 11, 0xFFFF, sum = 0
3100 00:43:50.987882 12, 0x0, sum = 1
3101 00:43:50.987983 13, 0x0, sum = 2
3102 00:43:50.988084 14, 0x0, sum = 3
3103 00:43:50.988180 15, 0x0, sum = 4
3104 00:43:50.988276 best_step = 13
3105 00:43:50.988374
3106 00:43:50.988468 ==
3107 00:43:50.988566 Dram Type= 6, Freq= 0, CH_0, rank 1
3108 00:43:50.988661 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3109 00:43:50.988756 ==
3110 00:43:50.988849 RX Vref Scan: 0
3111 00:43:50.988942
3112 00:43:50.989036 RX Vref 0 -> 0, step: 1
3113 00:43:50.989129
3114 00:43:50.989223 RX Delay -21 -> 252, step: 4
3115 00:43:50.989308 iDelay=199, Bit 0, Center 114 (47 ~ 182) 136
3116 00:43:50.989371 iDelay=199, Bit 1, Center 118 (47 ~ 190) 144
3117 00:43:50.989441 iDelay=199, Bit 2, Center 110 (43 ~ 178) 136
3118 00:43:50.989503 iDelay=199, Bit 3, Center 114 (43 ~ 186) 144
3119 00:43:50.989565 iDelay=199, Bit 4, Center 116 (47 ~ 186) 140
3120 00:43:50.989626 iDelay=199, Bit 5, Center 110 (43 ~ 178) 136
3121 00:43:50.989686 iDelay=199, Bit 6, Center 126 (55 ~ 198) 144
3122 00:43:50.989754 iDelay=199, Bit 7, Center 124 (55 ~ 194) 140
3123 00:43:50.989851 iDelay=199, Bit 8, Center 98 (31 ~ 166) 136
3124 00:43:50.989945 iDelay=199, Bit 9, Center 94 (27 ~ 162) 136
3125 00:43:50.990039 iDelay=199, Bit 10, Center 110 (43 ~ 178) 136
3126 00:43:50.990134 iDelay=199, Bit 11, Center 100 (35 ~ 166) 132
3127 00:43:50.990214 iDelay=199, Bit 12, Center 114 (47 ~ 182) 136
3128 00:43:50.990276 iDelay=199, Bit 13, Center 114 (51 ~ 178) 128
3129 00:43:50.990337 iDelay=199, Bit 14, Center 120 (55 ~ 186) 132
3130 00:43:50.990403 iDelay=199, Bit 15, Center 116 (51 ~ 182) 132
3131 00:43:50.990466 ==
3132 00:43:50.990527 Dram Type= 6, Freq= 0, CH_0, rank 1
3133 00:43:50.990588 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3134 00:43:50.990650 ==
3135 00:43:50.990710 DQS Delay:
3136 00:43:50.990777 DQS0 = 0, DQS1 = 0
3137 00:43:50.990839 DQM Delay:
3138 00:43:50.990899 DQM0 = 116, DQM1 = 108
3139 00:43:50.990960 DQ Delay:
3140 00:43:50.991021 DQ0 =114, DQ1 =118, DQ2 =110, DQ3 =114
3141 00:43:50.991082 DQ4 =116, DQ5 =110, DQ6 =126, DQ7 =124
3142 00:43:50.991149 DQ8 =98, DQ9 =94, DQ10 =110, DQ11 =100
3143 00:43:50.991211 DQ12 =114, DQ13 =114, DQ14 =120, DQ15 =116
3144 00:43:50.991272
3145 00:43:50.991338
3146 00:43:50.991400 [DQSOSCAuto] RK1, (LSB)MR18= 0xee9, (MSB)MR19= 0x403, tDQSOscB0 = 419 ps tDQSOscB1 = 404 ps
3147 00:43:50.991462 CH0 RK1: MR19=403, MR18=EE9
3148 00:43:50.991531 CH0_RK1: MR19=0x403, MR18=0xEE9, DQSOSC=404, MR23=63, INC=40, DEC=26
3149 00:43:50.991594 [RxdqsGatingPostProcess] freq 1200
3150 00:43:50.991655 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3151 00:43:50.991716 best DQS0 dly(2T, 0.5T) = (0, 11)
3152 00:43:50.991811 best DQS1 dly(2T, 0.5T) = (0, 12)
3153 00:43:50.991905 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3154 00:43:50.992003 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3155 00:43:50.992098 best DQS0 dly(2T, 0.5T) = (0, 11)
3156 00:43:50.992192 best DQS1 dly(2T, 0.5T) = (0, 12)
3157 00:43:50.992291 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3158 00:43:50.992385 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3159 00:43:50.992482 Pre-setting of DQS Precalculation
3160 00:43:50.992578 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3161 00:43:50.992672 ==
3162 00:43:50.992771 Dram Type= 6, Freq= 0, CH_1, rank 0
3163 00:43:50.992866 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3164 00:43:50.992963 ==
3165 00:43:50.993059 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3166 00:43:50.993155 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3167 00:43:50.993241 [CA 0] Center 37 (7~67) winsize 61
3168 00:43:50.993304 [CA 1] Center 37 (7~68) winsize 62
3169 00:43:50.993365 [CA 2] Center 34 (4~64) winsize 61
3170 00:43:50.993426 [CA 3] Center 33 (3~64) winsize 62
3171 00:43:50.993519 [CA 4] Center 34 (4~64) winsize 61
3172 00:43:50.993614 [CA 5] Center 33 (3~64) winsize 62
3173 00:43:50.993708
3174 00:43:50.993802 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3175 00:43:50.993895
3176 00:43:50.993989 [CATrainingPosCal] consider 1 rank data
3177 00:43:50.994088 u2DelayCellTimex100 = 270/100 ps
3178 00:43:50.994191 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3179 00:43:50.994287 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3180 00:43:50.994381 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3181 00:43:50.994475 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3182 00:43:50.994569 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3183 00:43:50.994664 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3184 00:43:50.994757
3185 00:43:50.994850 CA PerBit enable=1, Macro0, CA PI delay=33
3186 00:43:50.994944
3187 00:43:50.995038 [CBTSetCACLKResult] CA Dly = 33
3188 00:43:50.995131 CS Dly: 6 (0~37)
3189 00:43:50.995224 ==
3190 00:43:50.995319 Dram Type= 6, Freq= 0, CH_1, rank 1
3191 00:43:50.995413 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3192 00:43:50.995507 ==
3193 00:43:50.995626 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3194 00:43:50.995726 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3195 00:43:50.995821 [CA 0] Center 37 (7~67) winsize 61
3196 00:43:50.995916 [CA 1] Center 37 (7~68) winsize 62
3197 00:43:50.996010 [CA 2] Center 34 (3~65) winsize 63
3198 00:43:50.996096 [CA 3] Center 33 (3~64) winsize 62
3199 00:43:50.996160 [CA 4] Center 34 (4~64) winsize 61
3200 00:43:50.996431 [CA 5] Center 33 (3~64) winsize 62
3201 00:43:50.996501
3202 00:43:50.996563 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3203 00:43:50.996657
3204 00:43:50.996752 [CATrainingPosCal] consider 2 rank data
3205 00:43:50.996851 u2DelayCellTimex100 = 270/100 ps
3206 00:43:50.996946 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3207 00:43:50.997044 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3208 00:43:50.997140 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3209 00:43:50.997234 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3210 00:43:50.997329 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3211 00:43:50.997408 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3212 00:43:50.997471
3213 00:43:50.997536 CA PerBit enable=1, Macro0, CA PI delay=33
3214 00:43:50.997600
3215 00:43:50.997660 [CBTSetCACLKResult] CA Dly = 33
3216 00:43:50.997721 CS Dly: 7 (0~40)
3217 00:43:50.997789
3218 00:43:50.997884 ----->DramcWriteLeveling(PI) begin...
3219 00:43:50.997980 ==
3220 00:43:50.998074 Dram Type= 6, Freq= 0, CH_1, rank 0
3221 00:43:50.998185 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3222 00:43:50.998252 ==
3223 00:43:50.998322 Write leveling (Byte 0): 25 => 25
3224 00:43:50.998384 Write leveling (Byte 1): 30 => 30
3225 00:43:50.998446 DramcWriteLeveling(PI) end<-----
3226 00:43:50.998508
3227 00:43:50.998576 ==
3228 00:43:50.998638 Dram Type= 6, Freq= 0, CH_1, rank 0
3229 00:43:50.998699 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3230 00:43:50.998766 ==
3231 00:43:50.998828 [Gating] SW mode calibration
3232 00:43:50.998889 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3233 00:43:50.998951 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3234 00:43:50.999018 0 15 0 | B1->B0 | 2c2c 3434 | 1 1 | (1 1) (1 1)
3235 00:43:50.999081 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3236 00:43:50.999143 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3237 00:43:50.999204 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3238 00:43:50.999265 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3239 00:43:50.999329 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3240 00:43:50.999393 0 15 24 | B1->B0 | 3434 2c2c | 1 0 | (1 0) (0 1)
3241 00:43:50.999454 0 15 28 | B1->B0 | 2b2b 2323 | 1 0 | (1 0) (1 0)
3242 00:43:50.999520 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3243 00:43:50.999583 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3244 00:43:50.999644 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3245 00:43:50.999705 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3246 00:43:50.999788 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3247 00:43:50.999883 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3248 00:43:50.999978 1 0 24 | B1->B0 | 2323 3e3e | 0 0 | (0 0) (0 0)
3249 00:43:51.000076 1 0 28 | B1->B0 | 4242 4646 | 1 0 | (0 0) (0 0)
3250 00:43:51.000172 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3251 00:43:51.000271 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3252 00:43:51.000378 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3253 00:43:51.000476 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3254 00:43:51.000573 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3255 00:43:51.000668 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3256 00:43:51.000766 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3257 00:43:51.000862 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3258 00:43:51.000957 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3259 00:43:51.001055 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3260 00:43:51.001151 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3261 00:43:51.001245 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3262 00:43:51.001331 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3263 00:43:51.001394 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3264 00:43:51.001456 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3265 00:43:51.001523 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3266 00:43:51.001585 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3267 00:43:51.001646 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3268 00:43:51.001713 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3269 00:43:51.001809 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3270 00:43:51.001904 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3271 00:43:51.001998 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3272 00:43:51.002097 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3273 00:43:51.002192 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3274 00:43:51.002262 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3275 00:43:51.002324 Total UI for P1: 0, mck2ui 16
3276 00:43:51.002386 best dqsien dly found for B0: ( 1, 3, 26)
3277 00:43:51.002448 Total UI for P1: 0, mck2ui 16
3278 00:43:51.002517 best dqsien dly found for B1: ( 1, 3, 26)
3279 00:43:51.002578 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3280 00:43:51.002640 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3281 00:43:51.002706
3282 00:43:51.002769 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3283 00:43:51.002830 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3284 00:43:51.002891 [Gating] SW calibration Done
3285 00:43:51.002957 ==
3286 00:43:51.003020 Dram Type= 6, Freq= 0, CH_1, rank 0
3287 00:43:51.003081 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3288 00:43:51.003143 ==
3289 00:43:51.003210 RX Vref Scan: 0
3290 00:43:51.003273
3291 00:43:51.003333 RX Vref 0 -> 0, step: 1
3292 00:43:51.003394
3293 00:43:51.003475 RX Delay -40 -> 252, step: 8
3294 00:43:51.003570 iDelay=208, Bit 0, Center 119 (48 ~ 191) 144
3295 00:43:51.003665 iDelay=208, Bit 1, Center 115 (48 ~ 183) 136
3296 00:43:51.003763 iDelay=208, Bit 2, Center 111 (40 ~ 183) 144
3297 00:43:51.003858 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3298 00:43:51.003956 iDelay=208, Bit 4, Center 115 (48 ~ 183) 136
3299 00:43:51.004052 iDelay=208, Bit 5, Center 131 (56 ~ 207) 152
3300 00:43:51.004146 iDelay=208, Bit 6, Center 127 (56 ~ 199) 144
3301 00:43:51.004245 iDelay=208, Bit 7, Center 115 (48 ~ 183) 136
3302 00:43:51.004340 iDelay=208, Bit 8, Center 99 (32 ~ 167) 136
3303 00:43:51.004438 iDelay=208, Bit 9, Center 103 (32 ~ 175) 144
3304 00:43:51.004734 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3305 00:43:51.004835 iDelay=208, Bit 11, Center 99 (32 ~ 167) 136
3306 00:43:51.004935 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3307 00:43:51.005031 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3308 00:43:51.005126 iDelay=208, Bit 14, Center 119 (48 ~ 191) 144
3309 00:43:51.005225 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3310 00:43:51.005319 ==
3311 00:43:51.005414 Dram Type= 6, Freq= 0, CH_1, rank 0
3312 00:43:51.005509 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3313 00:43:51.005603 ==
3314 00:43:51.005698 DQS Delay:
3315 00:43:51.005815 DQS0 = 0, DQS1 = 0
3316 00:43:51.005913 DQM Delay:
3317 00:43:51.006008 DQM0 = 118, DQM1 = 111
3318 00:43:51.006102 DQ Delay:
3319 00:43:51.006199 DQ0 =119, DQ1 =115, DQ2 =111, DQ3 =115
3320 00:43:51.006270 DQ4 =115, DQ5 =131, DQ6 =127, DQ7 =115
3321 00:43:51.006332 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =99
3322 00:43:51.006393 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3323 00:43:51.006455
3324 00:43:51.006515
3325 00:43:51.006584 ==
3326 00:43:51.006647 Dram Type= 6, Freq= 0, CH_1, rank 0
3327 00:43:51.006709 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3328 00:43:51.006778 ==
3329 00:43:51.006840
3330 00:43:51.006900
3331 00:43:51.006962 TX Vref Scan disable
3332 00:43:51.007022 == TX Byte 0 ==
3333 00:43:51.007089 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3334 00:43:51.007153 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3335 00:43:51.007214 == TX Byte 1 ==
3336 00:43:51.007283 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3337 00:43:51.007345 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3338 00:43:51.007407 ==
3339 00:43:51.007468 Dram Type= 6, Freq= 0, CH_1, rank 0
3340 00:43:51.007529 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3341 00:43:51.007599 ==
3342 00:43:51.007662 TX Vref=22, minBit 5, minWin=25, winSum=410
3343 00:43:51.007724 TX Vref=24, minBit 1, minWin=25, winSum=413
3344 00:43:51.007792 TX Vref=26, minBit 9, minWin=25, winSum=421
3345 00:43:51.007854 TX Vref=28, minBit 10, minWin=25, winSum=424
3346 00:43:51.007916 TX Vref=30, minBit 1, minWin=26, winSum=427
3347 00:43:51.008008 TX Vref=32, minBit 9, minWin=25, winSum=420
3348 00:43:51.008104 [TxChooseVref] Worse bit 1, Min win 26, Win sum 427, Final Vref 30
3349 00:43:51.008197
3350 00:43:51.008295 Final TX Range 1 Vref 30
3351 00:43:51.008390
3352 00:43:51.008488 ==
3353 00:43:51.008582 Dram Type= 6, Freq= 0, CH_1, rank 0
3354 00:43:51.008679 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3355 00:43:51.008775 ==
3356 00:43:51.008869
3357 00:43:51.008961
3358 00:43:51.009059 TX Vref Scan disable
3359 00:43:51.009153 == TX Byte 0 ==
3360 00:43:51.009227 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3361 00:43:51.009289 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3362 00:43:51.009359 == TX Byte 1 ==
3363 00:43:51.009417 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3364 00:43:51.009475 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3365 00:43:51.009530
3366 00:43:51.009585 [DATLAT]
3367 00:43:51.009638 Freq=1200, CH1 RK0
3368 00:43:51.009693
3369 00:43:51.009754 DATLAT Default: 0xd
3370 00:43:51.009839 0, 0xFFFF, sum = 0
3371 00:43:51.009929 1, 0xFFFF, sum = 0
3372 00:43:51.010017 2, 0xFFFF, sum = 0
3373 00:43:51.010104 3, 0xFFFF, sum = 0
3374 00:43:51.010197 4, 0xFFFF, sum = 0
3375 00:43:51.010256 5, 0xFFFF, sum = 0
3376 00:43:51.010312 6, 0xFFFF, sum = 0
3377 00:43:51.010368 7, 0xFFFF, sum = 0
3378 00:43:51.010424 8, 0xFFFF, sum = 0
3379 00:43:51.010479 9, 0xFFFF, sum = 0
3380 00:43:51.010535 10, 0xFFFF, sum = 0
3381 00:43:51.010591 11, 0xFFFF, sum = 0
3382 00:43:51.010652 12, 0x0, sum = 1
3383 00:43:51.010709 13, 0x0, sum = 2
3384 00:43:51.010765 14, 0x0, sum = 3
3385 00:43:51.010825 15, 0x0, sum = 4
3386 00:43:51.010882 best_step = 13
3387 00:43:51.010937
3388 00:43:51.010991 ==
3389 00:43:51.011053 Dram Type= 6, Freq= 0, CH_1, rank 0
3390 00:43:51.011109 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3391 00:43:51.011164 ==
3392 00:43:51.011219 RX Vref Scan: 1
3393 00:43:51.011278
3394 00:43:51.011334 Set Vref Range= 32 -> 127
3395 00:43:51.011389
3396 00:43:51.011443 RX Vref 32 -> 127, step: 1
3397 00:43:51.011498
3398 00:43:51.011551 RX Delay -13 -> 252, step: 4
3399 00:43:51.011623
3400 00:43:51.011708 Set Vref, RX VrefLevel [Byte0]: 32
3401 00:43:51.011798 [Byte1]: 32
3402 00:43:51.011882
3403 00:43:51.011970 Set Vref, RX VrefLevel [Byte0]: 33
3404 00:43:51.012057 [Byte1]: 33
3405 00:43:51.012143
3406 00:43:51.012228 Set Vref, RX VrefLevel [Byte0]: 34
3407 00:43:51.012313 [Byte1]: 34
3408 00:43:51.012398
3409 00:43:51.012482 Set Vref, RX VrefLevel [Byte0]: 35
3410 00:43:51.012574 [Byte1]: 35
3411 00:43:51.012674
3412 00:43:51.012759 Set Vref, RX VrefLevel [Byte0]: 36
3413 00:43:51.012845 [Byte1]: 36
3414 00:43:51.012929
3415 00:43:51.013013 Set Vref, RX VrefLevel [Byte0]: 37
3416 00:43:51.013103 [Byte1]: 37
3417 00:43:51.013188
3418 00:43:51.013273 Set Vref, RX VrefLevel [Byte0]: 38
3419 00:43:51.013337 [Byte1]: 38
3420 00:43:51.013393
3421 00:43:51.013448 Set Vref, RX VrefLevel [Byte0]: 39
3422 00:43:51.013504 [Byte1]: 39
3423 00:43:51.013566
3424 00:43:51.013621 Set Vref, RX VrefLevel [Byte0]: 40
3425 00:43:51.013675 [Byte1]: 40
3426 00:43:51.013730
3427 00:43:51.013791 Set Vref, RX VrefLevel [Byte0]: 41
3428 00:43:51.013877 [Byte1]: 41
3429 00:43:51.013962
3430 00:43:51.014047 Set Vref, RX VrefLevel [Byte0]: 42
3431 00:43:51.014136 [Byte1]: 42
3432 00:43:51.014211
3433 00:43:51.014269 Set Vref, RX VrefLevel [Byte0]: 43
3434 00:43:51.014341 [Byte1]: 43
3435 00:43:51.014393
3436 00:43:51.014445 Set Vref, RX VrefLevel [Byte0]: 44
3437 00:43:51.014498 [Byte1]: 44
3438 00:43:51.014551
3439 00:43:51.014608 Set Vref, RX VrefLevel [Byte0]: 45
3440 00:43:51.014661 [Byte1]: 45
3441 00:43:51.014713
3442 00:43:51.014772 Set Vref, RX VrefLevel [Byte0]: 46
3443 00:43:51.014826 [Byte1]: 46
3444 00:43:51.014878
3445 00:43:51.014930 Set Vref, RX VrefLevel [Byte0]: 47
3446 00:43:51.014983 [Byte1]: 47
3447 00:43:51.015036
3448 00:43:51.015093 Set Vref, RX VrefLevel [Byte0]: 48
3449 00:43:51.015146 [Byte1]: 48
3450 00:43:51.015199
3451 00:43:51.015255 Set Vref, RX VrefLevel [Byte0]: 49
3452 00:43:51.015308 [Byte1]: 49
3453 00:43:51.015361
3454 00:43:51.015413 Set Vref, RX VrefLevel [Byte0]: 50
3455 00:43:51.015465 [Byte1]: 50
3456 00:43:51.015526
3457 00:43:51.015608 Set Vref, RX VrefLevel [Byte0]: 51
3458 00:43:51.015689 [Byte1]: 51
3459 00:43:51.015773
3460 00:43:51.015855 Set Vref, RX VrefLevel [Byte0]: 52
3461 00:43:51.015937 [Byte1]: 52
3462 00:43:51.016017
3463 00:43:51.016102 Set Vref, RX VrefLevel [Byte0]: 53
3464 00:43:51.016184 [Byte1]: 53
3465 00:43:51.016267
3466 00:43:51.016349 Set Vref, RX VrefLevel [Byte0]: 54
3467 00:43:51.016625 [Byte1]: 54
3468 00:43:51.016712
3469 00:43:51.016797 Set Vref, RX VrefLevel [Byte0]: 55
3470 00:43:51.016880 [Byte1]: 55
3471 00:43:51.016961
3472 00:43:51.017042 Set Vref, RX VrefLevel [Byte0]: 56
3473 00:43:51.017128 [Byte1]: 56
3474 00:43:51.017209
3475 00:43:51.017290 Set Vref, RX VrefLevel [Byte0]: 57
3476 00:43:51.017372 [Byte1]: 57
3477 00:43:51.017453
3478 00:43:51.017534 Set Vref, RX VrefLevel [Byte0]: 58
3479 00:43:51.017623 [Byte1]: 58
3480 00:43:51.017679
3481 00:43:51.017732 Set Vref, RX VrefLevel [Byte0]: 59
3482 00:43:51.017786 [Byte1]: 59
3483 00:43:51.017839
3484 00:43:51.017891 Set Vref, RX VrefLevel [Byte0]: 60
3485 00:43:51.017947 [Byte1]: 60
3486 00:43:51.018037
3487 00:43:51.018119 Set Vref, RX VrefLevel [Byte0]: 61
3488 00:43:51.018238 [Byte1]: 61
3489 00:43:51.018318
3490 00:43:51.018372 Set Vref, RX VrefLevel [Byte0]: 62
3491 00:43:51.018425 [Byte1]: 62
3492 00:43:51.018478
3493 00:43:51.018530 Set Vref, RX VrefLevel [Byte0]: 63
3494 00:43:51.018582 [Byte1]: 63
3495 00:43:51.018634
3496 00:43:51.018686 Set Vref, RX VrefLevel [Byte0]: 64
3497 00:43:51.018762 [Byte1]: 64
3498 00:43:51.018817
3499 00:43:51.018870 Set Vref, RX VrefLevel [Byte0]: 65
3500 00:43:51.018922 [Byte1]: 65
3501 00:43:51.018975
3502 00:43:51.019027 Set Vref, RX VrefLevel [Byte0]: 66
3503 00:43:51.019084 [Byte1]: 66
3504 00:43:51.019153
3505 00:43:51.019205 Set Vref, RX VrefLevel [Byte0]: 67
3506 00:43:51.019259 [Byte1]: 67
3507 00:43:51.019312
3508 00:43:51.019364 Set Vref, RX VrefLevel [Byte0]: 68
3509 00:43:51.019417 [Byte1]: 68
3510 00:43:51.019469
3511 00:43:51.019521 Set Vref, RX VrefLevel [Byte0]: 69
3512 00:43:51.019573 [Byte1]: 69
3513 00:43:51.019626
3514 00:43:51.019681 Final RX Vref Byte 0 = 49 to rank0
3515 00:43:51.019773 Final RX Vref Byte 1 = 51 to rank0
3516 00:43:51.019829 Final RX Vref Byte 0 = 49 to rank1
3517 00:43:51.019882 Final RX Vref Byte 1 = 51 to rank1==
3518 00:43:51.019934 Dram Type= 6, Freq= 0, CH_1, rank 0
3519 00:43:51.019987 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3520 00:43:51.020040 ==
3521 00:43:51.020092 DQS Delay:
3522 00:43:51.020144 DQS0 = 0, DQS1 = 0
3523 00:43:51.020203 DQM Delay:
3524 00:43:51.020257 DQM0 = 117, DQM1 = 110
3525 00:43:51.020309 DQ Delay:
3526 00:43:51.020361 DQ0 =118, DQ1 =112, DQ2 =108, DQ3 =112
3527 00:43:51.020428 DQ4 =116, DQ5 =128, DQ6 =128, DQ7 =114
3528 00:43:51.020510 DQ8 =98, DQ9 =100, DQ10 =114, DQ11 =98
3529 00:43:51.020592 DQ12 =118, DQ13 =118, DQ14 =120, DQ15 =120
3530 00:43:51.020673
3531 00:43:51.020757
3532 00:43:51.020841 [DQSOSCAuto] RK0, (LSB)MR18= 0x1f5, (MSB)MR19= 0x403, tDQSOscB0 = 414 ps tDQSOscB1 = 409 ps
3533 00:43:51.020927 CH1 RK0: MR19=403, MR18=1F5
3534 00:43:51.021011 CH1_RK0: MR19=0x403, MR18=0x1F5, DQSOSC=409, MR23=63, INC=39, DEC=26
3535 00:43:51.021092
3536 00:43:51.021177 ----->DramcWriteLeveling(PI) begin...
3537 00:43:51.021260 ==
3538 00:43:51.021342 Dram Type= 6, Freq= 0, CH_1, rank 1
3539 00:43:51.021420 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3540 00:43:51.021475 ==
3541 00:43:51.021528 Write leveling (Byte 0): 24 => 24
3542 00:43:51.021581 Write leveling (Byte 1): 28 => 28
3543 00:43:51.021633 DramcWriteLeveling(PI) end<-----
3544 00:43:51.021686
3545 00:43:51.021742 ==
3546 00:43:51.021796 Dram Type= 6, Freq= 0, CH_1, rank 1
3547 00:43:51.021849 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3548 00:43:51.021907 ==
3549 00:43:51.021990 [Gating] SW mode calibration
3550 00:43:51.022073 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3551 00:43:51.022159 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3552 00:43:51.022257 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3553 00:43:51.022310 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3554 00:43:51.022364 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3555 00:43:51.022417 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3556 00:43:51.022478 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3557 00:43:51.022532 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3558 00:43:51.022584 0 15 24 | B1->B0 | 3333 3434 | 1 1 | (1 0) (1 1)
3559 00:43:51.022639 0 15 28 | B1->B0 | 2424 2828 | 0 0 | (1 0) (0 0)
3560 00:43:51.022695 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3561 00:43:51.022748 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3562 00:43:51.022800 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3563 00:43:51.022852 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3564 00:43:51.022913 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3565 00:43:51.022966 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3566 00:43:51.023019 1 0 24 | B1->B0 | 2c2c 2323 | 0 1 | (0 0) (0 0)
3567 00:43:51.023071 1 0 28 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
3568 00:43:51.023124 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3569 00:43:51.023177 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3570 00:43:51.023238 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3571 00:43:51.023291 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3572 00:43:51.023344 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3573 00:43:51.023403 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3574 00:43:51.023456 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3575 00:43:51.023508 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3576 00:43:51.023561 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3577 00:43:51.023617 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3578 00:43:51.023672 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3579 00:43:51.023724 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3580 00:43:51.023777 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3581 00:43:51.023829 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3582 00:43:51.023910 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3583 00:43:51.023992 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3584 00:43:51.024074 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3585 00:43:51.024156 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3586 00:43:51.024445 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3587 00:43:51.024531 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3588 00:43:51.024617 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3589 00:43:51.024701 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3590 00:43:51.024783 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3591 00:43:51.024868 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3592 00:43:51.024951 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3593 00:43:51.025032 Total UI for P1: 0, mck2ui 16
3594 00:43:51.025115 best dqsien dly found for B0: ( 1, 3, 28)
3595 00:43:51.025201 Total UI for P1: 0, mck2ui 16
3596 00:43:51.025284 best dqsien dly found for B1: ( 1, 3, 26)
3597 00:43:51.025369 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3598 00:43:51.025452 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3599 00:43:51.025532
3600 00:43:51.025617 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3601 00:43:51.025699 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3602 00:43:51.025781 [Gating] SW calibration Done
3603 00:43:51.025866 ==
3604 00:43:51.025948 Dram Type= 6, Freq= 0, CH_1, rank 1
3605 00:43:51.026030 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3606 00:43:51.026112 ==
3607 00:43:51.026225 RX Vref Scan: 0
3608 00:43:51.026280
3609 00:43:51.026333 RX Vref 0 -> 0, step: 1
3610 00:43:51.026392
3611 00:43:51.026445 RX Delay -40 -> 252, step: 8
3612 00:43:51.026498 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3613 00:43:51.026551 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3614 00:43:51.026610 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3615 00:43:51.026662 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3616 00:43:51.026715 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3617 00:43:51.026767 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3618 00:43:51.026819 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3619 00:43:51.026871 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3620 00:43:51.026929 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3621 00:43:51.026983 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3622 00:43:51.027035 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3623 00:43:51.027095 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
3624 00:43:51.027148 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3625 00:43:51.027201 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3626 00:43:51.027254 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3627 00:43:51.027310 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3628 00:43:51.027363 ==
3629 00:43:51.027415 Dram Type= 6, Freq= 0, CH_1, rank 1
3630 00:43:51.027467 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3631 00:43:51.027520 ==
3632 00:43:51.027572 DQS Delay:
3633 00:43:51.027624 DQS0 = 0, DQS1 = 0
3634 00:43:51.027676 DQM Delay:
3635 00:43:51.027757 DQM0 = 117, DQM1 = 110
3636 00:43:51.027839 DQ Delay:
3637 00:43:51.027920 DQ0 =123, DQ1 =111, DQ2 =107, DQ3 =111
3638 00:43:51.028002 DQ4 =115, DQ5 =127, DQ6 =127, DQ7 =115
3639 00:43:51.028084 DQ8 =99, DQ9 =95, DQ10 =111, DQ11 =99
3640 00:43:51.028166 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3641 00:43:51.028248
3642 00:43:51.028335
3643 00:43:51.028429 ==
3644 00:43:51.028515 Dram Type= 6, Freq= 0, CH_1, rank 1
3645 00:43:51.028597 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3646 00:43:51.028679 ==
3647 00:43:51.028765
3648 00:43:51.028852
3649 00:43:51.028933 TX Vref Scan disable
3650 00:43:51.029014 == TX Byte 0 ==
3651 00:43:51.029096 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3652 00:43:51.029186 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3653 00:43:51.029253 == TX Byte 1 ==
3654 00:43:51.029306 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3655 00:43:51.029359 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3656 00:43:51.029413 ==
3657 00:43:51.029466 Dram Type= 6, Freq= 0, CH_1, rank 1
3658 00:43:51.029518 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3659 00:43:51.029570 ==
3660 00:43:51.029623 TX Vref=22, minBit 0, minWin=26, winSum=424
3661 00:43:51.029682 TX Vref=24, minBit 8, minWin=25, winSum=424
3662 00:43:51.029736 TX Vref=26, minBit 1, minWin=26, winSum=431
3663 00:43:51.029789 TX Vref=28, minBit 9, minWin=26, winSum=433
3664 00:43:51.029842 TX Vref=30, minBit 10, minWin=26, winSum=432
3665 00:43:51.029894 TX Vref=32, minBit 10, minWin=26, winSum=431
3666 00:43:51.029947 [TxChooseVref] Worse bit 9, Min win 26, Win sum 433, Final Vref 28
3667 00:43:51.029999
3668 00:43:51.030051 Final TX Range 1 Vref 28
3669 00:43:51.030104
3670 00:43:51.030155 ==
3671 00:43:51.030249 Dram Type= 6, Freq= 0, CH_1, rank 1
3672 00:43:51.030302 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3673 00:43:51.030355 ==
3674 00:43:51.030408
3675 00:43:51.030459
3676 00:43:51.030512 TX Vref Scan disable
3677 00:43:51.030564 == TX Byte 0 ==
3678 00:43:51.030617 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3679 00:43:51.030669 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3680 00:43:51.030722 == TX Byte 1 ==
3681 00:43:51.030774 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3682 00:43:51.030828 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3683 00:43:51.030893
3684 00:43:51.030949 [DATLAT]
3685 00:43:51.031002 Freq=1200, CH1 RK1
3686 00:43:51.031055
3687 00:43:51.031107 DATLAT Default: 0xd
3688 00:43:51.031159 0, 0xFFFF, sum = 0
3689 00:43:51.031213 1, 0xFFFF, sum = 0
3690 00:43:51.031267 2, 0xFFFF, sum = 0
3691 00:43:51.031320 3, 0xFFFF, sum = 0
3692 00:43:51.031372 4, 0xFFFF, sum = 0
3693 00:43:51.031426 5, 0xFFFF, sum = 0
3694 00:43:51.031479 6, 0xFFFF, sum = 0
3695 00:43:51.031532 7, 0xFFFF, sum = 0
3696 00:43:51.031586 8, 0xFFFF, sum = 0
3697 00:43:51.031638 9, 0xFFFF, sum = 0
3698 00:43:51.031692 10, 0xFFFF, sum = 0
3699 00:43:51.031745 11, 0xFFFF, sum = 0
3700 00:43:51.031798 12, 0x0, sum = 1
3701 00:43:51.031851 13, 0x0, sum = 2
3702 00:43:51.031905 14, 0x0, sum = 3
3703 00:43:51.031957 15, 0x0, sum = 4
3704 00:43:51.032010 best_step = 13
3705 00:43:51.032062
3706 00:43:51.032115 ==
3707 00:43:51.032167 Dram Type= 6, Freq= 0, CH_1, rank 1
3708 00:43:51.032251 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3709 00:43:51.032329 ==
3710 00:43:51.032386 RX Vref Scan: 0
3711 00:43:51.032440
3712 00:43:51.032492 RX Vref 0 -> 0, step: 1
3713 00:43:51.032573
3714 00:43:51.032657 RX Delay -21 -> 252, step: 4
3715 00:43:51.032760 iDelay=199, Bit 0, Center 120 (55 ~ 186) 132
3716 00:43:51.032883 iDelay=199, Bit 1, Center 112 (47 ~ 178) 132
3717 00:43:51.032972 iDelay=199, Bit 2, Center 108 (47 ~ 170) 124
3718 00:43:51.033065 iDelay=199, Bit 3, Center 114 (51 ~ 178) 128
3719 00:43:51.033150 iDelay=199, Bit 4, Center 116 (51 ~ 182) 132
3720 00:43:51.033241 iDelay=199, Bit 5, Center 128 (63 ~ 194) 132
3721 00:43:51.033299 iDelay=199, Bit 6, Center 130 (63 ~ 198) 136
3722 00:43:51.033352 iDelay=199, Bit 7, Center 116 (51 ~ 182) 132
3723 00:43:51.033404 iDelay=199, Bit 8, Center 98 (35 ~ 162) 128
3724 00:43:51.033651 iDelay=199, Bit 9, Center 100 (35 ~ 166) 132
3725 00:43:51.033711 iDelay=199, Bit 10, Center 112 (47 ~ 178) 132
3726 00:43:51.033766 iDelay=199, Bit 11, Center 100 (35 ~ 166) 132
3727 00:43:51.033819 iDelay=199, Bit 12, Center 120 (55 ~ 186) 132
3728 00:43:51.033871 iDelay=199, Bit 13, Center 120 (55 ~ 186) 132
3729 00:43:51.033923 iDelay=199, Bit 14, Center 116 (51 ~ 182) 132
3730 00:43:51.033975 iDelay=199, Bit 15, Center 120 (55 ~ 186) 132
3731 00:43:51.034027 ==
3732 00:43:51.034079 Dram Type= 6, Freq= 0, CH_1, rank 1
3733 00:43:51.034131 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3734 00:43:51.034252 ==
3735 00:43:51.034309 DQS Delay:
3736 00:43:51.034362 DQS0 = 0, DQS1 = 0
3737 00:43:51.034414 DQM Delay:
3738 00:43:51.034466 DQM0 = 118, DQM1 = 110
3739 00:43:51.034518 DQ Delay:
3740 00:43:51.034570 DQ0 =120, DQ1 =112, DQ2 =108, DQ3 =114
3741 00:43:51.034623 DQ4 =116, DQ5 =128, DQ6 =130, DQ7 =116
3742 00:43:51.034675 DQ8 =98, DQ9 =100, DQ10 =112, DQ11 =100
3743 00:43:51.034727 DQ12 =120, DQ13 =120, DQ14 =116, DQ15 =120
3744 00:43:51.034779
3745 00:43:51.034831
3746 00:43:51.034883 [DQSOSCAuto] RK1, (LSB)MR18= 0xf5f1, (MSB)MR19= 0x303, tDQSOscB0 = 416 ps tDQSOscB1 = 414 ps
3747 00:43:51.034937 CH1 RK1: MR19=303, MR18=F5F1
3748 00:43:51.034989 CH1_RK1: MR19=0x303, MR18=0xF5F1, DQSOSC=414, MR23=63, INC=38, DEC=25
3749 00:43:51.035064 [RxdqsGatingPostProcess] freq 1200
3750 00:43:51.035121 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3751 00:43:51.035197 best DQS0 dly(2T, 0.5T) = (0, 11)
3752 00:43:51.035254 best DQS1 dly(2T, 0.5T) = (0, 11)
3753 00:43:51.035307 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3754 00:43:51.035360 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3755 00:43:51.035412 best DQS0 dly(2T, 0.5T) = (0, 11)
3756 00:43:51.035465 best DQS1 dly(2T, 0.5T) = (0, 11)
3757 00:43:51.035518 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3758 00:43:51.035570 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3759 00:43:51.035625 Pre-setting of DQS Precalculation
3760 00:43:51.035699 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3761 00:43:51.035760 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3762 00:43:51.035853 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3763 00:43:51.035937
3764 00:43:51.036018
3765 00:43:51.036099 [Calibration Summary] 2400 Mbps
3766 00:43:51.036180 CH 0, Rank 0
3767 00:43:51.036261 SW Impedance : PASS
3768 00:43:51.036343 DUTY Scan : NO K
3769 00:43:51.036433 ZQ Calibration : PASS
3770 00:43:51.036519 Jitter Meter : NO K
3771 00:43:51.036612 CBT Training : PASS
3772 00:43:51.036694 Write leveling : PASS
3773 00:43:51.036776 RX DQS gating : PASS
3774 00:43:51.036857 RX DQ/DQS(RDDQC) : PASS
3775 00:43:51.036938 TX DQ/DQS : PASS
3776 00:43:51.037032 RX DATLAT : PASS
3777 00:43:51.037115 RX DQ/DQS(Engine): PASS
3778 00:43:51.037196 TX OE : NO K
3779 00:43:51.037278 All Pass.
3780 00:43:51.037360
3781 00:43:51.037434 CH 0, Rank 1
3782 00:43:51.037488 SW Impedance : PASS
3783 00:43:51.037541 DUTY Scan : NO K
3784 00:43:51.037594 ZQ Calibration : PASS
3785 00:43:51.037647 Jitter Meter : NO K
3786 00:43:51.037699 CBT Training : PASS
3787 00:43:51.037751 Write leveling : PASS
3788 00:43:51.037803 RX DQS gating : PASS
3789 00:43:51.037877 RX DQ/DQS(RDDQC) : PASS
3790 00:43:51.037961 TX DQ/DQS : PASS
3791 00:43:51.038043 RX DATLAT : PASS
3792 00:43:51.038125 RX DQ/DQS(Engine): PASS
3793 00:43:51.038242 TX OE : NO K
3794 00:43:51.038297 All Pass.
3795 00:43:51.038349
3796 00:43:51.038402 CH 1, Rank 0
3797 00:43:51.038455 SW Impedance : PASS
3798 00:43:51.038508 DUTY Scan : NO K
3799 00:43:51.038560 ZQ Calibration : PASS
3800 00:43:51.038613 Jitter Meter : NO K
3801 00:43:51.038665 CBT Training : PASS
3802 00:43:51.038717 Write leveling : PASS
3803 00:43:51.038770 RX DQS gating : PASS
3804 00:43:51.038822 RX DQ/DQS(RDDQC) : PASS
3805 00:43:51.038875 TX DQ/DQS : PASS
3806 00:43:51.038954 RX DATLAT : PASS
3807 00:43:51.039010 RX DQ/DQS(Engine): PASS
3808 00:43:51.039063 TX OE : NO K
3809 00:43:51.039116 All Pass.
3810 00:43:51.039168
3811 00:43:51.039221 CH 1, Rank 1
3812 00:43:51.039273 SW Impedance : PASS
3813 00:43:51.039325 DUTY Scan : NO K
3814 00:43:51.039378 ZQ Calibration : PASS
3815 00:43:51.039430 Jitter Meter : NO K
3816 00:43:51.039482 CBT Training : PASS
3817 00:43:51.039534 Write leveling : PASS
3818 00:43:51.039612 RX DQS gating : PASS
3819 00:43:51.039666 RX DQ/DQS(RDDQC) : PASS
3820 00:43:51.039719 TX DQ/DQS : PASS
3821 00:43:51.039772 RX DATLAT : PASS
3822 00:43:51.039824 RX DQ/DQS(Engine): PASS
3823 00:43:51.039876 TX OE : NO K
3824 00:43:51.039929 All Pass.
3825 00:43:51.040006
3826 00:43:51.040061 DramC Write-DBI off
3827 00:43:51.040114 PER_BANK_REFRESH: Hybrid Mode
3828 00:43:51.040167 TX_TRACKING: ON
3829 00:43:51.040220 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3830 00:43:51.040274 [FAST_K] Save calibration result to emmc
3831 00:43:51.040327 dramc_set_vcore_voltage set vcore to 650000
3832 00:43:51.040380 Read voltage for 600, 5
3833 00:43:51.040432 Vio18 = 0
3834 00:43:51.040485 Vcore = 650000
3835 00:43:51.040537 Vdram = 0
3836 00:43:51.040589 Vddq = 0
3837 00:43:51.040641 Vmddr = 0
3838 00:43:51.040693 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3839 00:43:51.040746 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3840 00:43:51.040798 MEM_TYPE=3, freq_sel=19
3841 00:43:51.040850 sv_algorithm_assistance_LP4_1600
3842 00:43:51.040903 ============ PULL DRAM RESETB DOWN ============
3843 00:43:51.040956 ========== PULL DRAM RESETB DOWN end =========
3844 00:43:51.041008 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3845 00:43:51.041067 ===================================
3846 00:43:51.041159 LPDDR4 DRAM CONFIGURATION
3847 00:43:51.041242 ===================================
3848 00:43:51.041325 EX_ROW_EN[0] = 0x0
3849 00:43:51.041406 EX_ROW_EN[1] = 0x0
3850 00:43:51.041498 LP4Y_EN = 0x0
3851 00:43:51.041556 WORK_FSP = 0x0
3852 00:43:51.041614 WL = 0x2
3853 00:43:51.041684 RL = 0x2
3854 00:43:51.041741 BL = 0x2
3855 00:43:51.041833 RPST = 0x0
3856 00:43:51.041915 RD_PRE = 0x0
3857 00:43:51.042008 WR_PRE = 0x1
3858 00:43:51.042091 WR_PST = 0x0
3859 00:43:51.042176 DBI_WR = 0x0
3860 00:43:51.042266 DBI_RD = 0x0
3861 00:43:51.042335 OTF = 0x1
3862 00:43:51.042402 ===================================
3863 00:43:51.042455 ===================================
3864 00:43:51.042507 ANA top config
3865 00:43:51.042559 ===================================
3866 00:43:51.042612 DLL_ASYNC_EN = 0
3867 00:43:51.042863 ALL_SLAVE_EN = 1
3868 00:43:51.042924 NEW_RANK_MODE = 1
3869 00:43:51.042978 DLL_IDLE_MODE = 1
3870 00:43:51.043031 LP45_APHY_COMB_EN = 1
3871 00:43:51.043087 TX_ODT_DIS = 1
3872 00:43:51.043161 NEW_8X_MODE = 1
3873 00:43:51.043216 ===================================
3874 00:43:51.043269 ===================================
3875 00:43:51.043323 data_rate = 1200
3876 00:43:51.043376 CKR = 1
3877 00:43:51.043429 DQ_P2S_RATIO = 8
3878 00:43:51.043481 ===================================
3879 00:43:51.043534 CA_P2S_RATIO = 8
3880 00:43:51.043614 DQ_CA_OPEN = 0
3881 00:43:51.043669 DQ_SEMI_OPEN = 0
3882 00:43:51.043722 CA_SEMI_OPEN = 0
3883 00:43:51.043775 CA_FULL_RATE = 0
3884 00:43:51.043827 DQ_CKDIV4_EN = 1
3885 00:43:51.043879 CA_CKDIV4_EN = 1
3886 00:43:51.043932 CA_PREDIV_EN = 0
3887 00:43:51.043983 PH8_DLY = 0
3888 00:43:51.044036 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3889 00:43:51.044089 DQ_AAMCK_DIV = 4
3890 00:43:51.044141 CA_AAMCK_DIV = 4
3891 00:43:51.044220 CA_ADMCK_DIV = 4
3892 00:43:51.044275 DQ_TRACK_CA_EN = 0
3893 00:43:51.044328 CA_PICK = 600
3894 00:43:51.044634 CA_MCKIO = 600
3895 00:43:51.048096 MCKIO_SEMI = 0
3896 00:43:51.051399 PLL_FREQ = 2288
3897 00:43:51.054673 DQ_UI_PI_RATIO = 32
3898 00:43:51.058074 CA_UI_PI_RATIO = 0
3899 00:43:51.058217 ===================================
3900 00:43:51.061266 ===================================
3901 00:43:51.064586 memory_type:LPDDR4
3902 00:43:51.067815 GP_NUM : 10
3903 00:43:51.067887 SRAM_EN : 1
3904 00:43:51.071436 MD32_EN : 0
3905 00:43:51.075104 ===================================
3906 00:43:51.078143 [ANA_INIT] >>>>>>>>>>>>>>
3907 00:43:51.080780 <<<<<< [CONFIGURE PHASE]: ANA_TX
3908 00:43:51.084497 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3909 00:43:51.087792 ===================================
3910 00:43:51.091182 data_rate = 1200,PCW = 0X5800
3911 00:43:51.094209 ===================================
3912 00:43:51.097883 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3913 00:43:51.101108 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3914 00:43:51.107227 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3915 00:43:51.111229 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3916 00:43:51.114246 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3917 00:43:51.117513 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3918 00:43:51.120650 [ANA_INIT] flow start
3919 00:43:51.124048 [ANA_INIT] PLL >>>>>>>>
3920 00:43:51.124219 [ANA_INIT] PLL <<<<<<<<
3921 00:43:51.127421 [ANA_INIT] MIDPI >>>>>>>>
3922 00:43:51.130963 [ANA_INIT] MIDPI <<<<<<<<
3923 00:43:51.131203 [ANA_INIT] DLL >>>>>>>>
3924 00:43:51.133738 [ANA_INIT] flow end
3925 00:43:51.137401 ============ LP4 DIFF to SE enter ============
3926 00:43:51.144600 ============ LP4 DIFF to SE exit ============
3927 00:43:51.145017 [ANA_INIT] <<<<<<<<<<<<<
3928 00:43:51.147860 [Flow] Enable top DCM control >>>>>
3929 00:43:51.150923 [Flow] Enable top DCM control <<<<<
3930 00:43:51.154318 Enable DLL master slave shuffle
3931 00:43:51.161007 ==============================================================
3932 00:43:51.161528 Gating Mode config
3933 00:43:51.167529 ==============================================================
3934 00:43:51.171085 Config description:
3935 00:43:51.180281 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3936 00:43:51.187141 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3937 00:43:51.191079 SELPH_MODE 0: By rank 1: By Phase
3938 00:43:51.197370 ==============================================================
3939 00:43:51.200644 GAT_TRACK_EN = 1
3940 00:43:51.201193 RX_GATING_MODE = 2
3941 00:43:51.204153 RX_GATING_TRACK_MODE = 2
3942 00:43:51.207060 SELPH_MODE = 1
3943 00:43:51.210639 PICG_EARLY_EN = 1
3944 00:43:51.213834 VALID_LAT_VALUE = 1
3945 00:43:51.220073 ==============================================================
3946 00:43:51.223263 Enter into Gating configuration >>>>
3947 00:43:51.226707 Exit from Gating configuration <<<<
3948 00:43:51.230094 Enter into DVFS_PRE_config >>>>>
3949 00:43:51.240212 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3950 00:43:51.243446 Exit from DVFS_PRE_config <<<<<
3951 00:43:51.246753 Enter into PICG configuration >>>>
3952 00:43:51.249748 Exit from PICG configuration <<<<
3953 00:43:51.253438 [RX_INPUT] configuration >>>>>
3954 00:43:51.256664 [RX_INPUT] configuration <<<<<
3955 00:43:51.259603 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3956 00:43:51.266134 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3957 00:43:51.272763 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3958 00:43:51.279370 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3959 00:43:51.285724 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3960 00:43:51.289049 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3961 00:43:51.295522 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3962 00:43:51.299133 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3963 00:43:51.302191 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3964 00:43:51.305760 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3965 00:43:51.312528 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3966 00:43:51.315675 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3967 00:43:51.318807 ===================================
3968 00:43:51.321861 LPDDR4 DRAM CONFIGURATION
3969 00:43:51.325300 ===================================
3970 00:43:51.325749 EX_ROW_EN[0] = 0x0
3971 00:43:51.328605 EX_ROW_EN[1] = 0x0
3972 00:43:51.329014 LP4Y_EN = 0x0
3973 00:43:51.332422 WORK_FSP = 0x0
3974 00:43:51.332819 WL = 0x2
3975 00:43:51.335474 RL = 0x2
3976 00:43:51.335891 BL = 0x2
3977 00:43:51.338770 RPST = 0x0
3978 00:43:51.342213 RD_PRE = 0x0
3979 00:43:51.342620 WR_PRE = 0x1
3980 00:43:51.345196 WR_PST = 0x0
3981 00:43:51.345562 DBI_WR = 0x0
3982 00:43:51.348582 DBI_RD = 0x0
3983 00:43:51.348952 OTF = 0x1
3984 00:43:51.351436 ===================================
3985 00:43:51.354929 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3986 00:43:51.361510 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3987 00:43:51.364728 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3988 00:43:51.368395 ===================================
3989 00:43:51.371456 LPDDR4 DRAM CONFIGURATION
3990 00:43:51.374582 ===================================
3991 00:43:51.374998 EX_ROW_EN[0] = 0x10
3992 00:43:51.378046 EX_ROW_EN[1] = 0x0
3993 00:43:51.378486 LP4Y_EN = 0x0
3994 00:43:51.381256 WORK_FSP = 0x0
3995 00:43:51.381637 WL = 0x2
3996 00:43:51.385237 RL = 0x2
3997 00:43:51.385588 BL = 0x2
3998 00:43:51.388218 RPST = 0x0
3999 00:43:51.391440 RD_PRE = 0x0
4000 00:43:51.391852 WR_PRE = 0x1
4001 00:43:51.394868 WR_PST = 0x0
4002 00:43:51.395161 DBI_WR = 0x0
4003 00:43:51.397891 DBI_RD = 0x0
4004 00:43:51.398215 OTF = 0x1
4005 00:43:51.401353 ===================================
4006 00:43:51.408186 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
4007 00:43:51.412107 nWR fixed to 30
4008 00:43:51.415371 [ModeRegInit_LP4] CH0 RK0
4009 00:43:51.415777 [ModeRegInit_LP4] CH0 RK1
4010 00:43:51.418641 [ModeRegInit_LP4] CH1 RK0
4011 00:43:51.421806 [ModeRegInit_LP4] CH1 RK1
4012 00:43:51.422450 match AC timing 17
4013 00:43:51.428911 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
4014 00:43:51.431821 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
4015 00:43:51.435097 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
4016 00:43:51.441244 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
4017 00:43:51.444727 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
4018 00:43:51.445138 ==
4019 00:43:51.447889 Dram Type= 6, Freq= 0, CH_0, rank 0
4020 00:43:51.451511 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4021 00:43:51.451931 ==
4022 00:43:51.457694 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4023 00:43:51.464448 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4024 00:43:51.467660 [CA 0] Center 36 (6~66) winsize 61
4025 00:43:51.470924 [CA 1] Center 36 (6~66) winsize 61
4026 00:43:51.474263 [CA 2] Center 34 (4~65) winsize 62
4027 00:43:51.477569 [CA 3] Center 34 (3~65) winsize 63
4028 00:43:51.480897 [CA 4] Center 33 (3~64) winsize 62
4029 00:43:51.484643 [CA 5] Center 33 (3~64) winsize 62
4030 00:43:51.485207
4031 00:43:51.487497 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4032 00:43:51.487908
4033 00:43:51.491488 [CATrainingPosCal] consider 1 rank data
4034 00:43:51.494417 u2DelayCellTimex100 = 270/100 ps
4035 00:43:51.497652 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4036 00:43:51.500897 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4037 00:43:51.504364 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4038 00:43:51.510828 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4039 00:43:51.514467 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4040 00:43:51.517727 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4041 00:43:51.518378
4042 00:43:51.520973 CA PerBit enable=1, Macro0, CA PI delay=33
4043 00:43:51.521513
4044 00:43:51.523817 [CBTSetCACLKResult] CA Dly = 33
4045 00:43:51.524344 CS Dly: 6 (0~37)
4046 00:43:51.524812 ==
4047 00:43:51.527525 Dram Type= 6, Freq= 0, CH_0, rank 1
4048 00:43:51.534312 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4049 00:43:51.534861 ==
4050 00:43:51.536980 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4051 00:43:51.543645 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4052 00:43:51.547253 [CA 0] Center 36 (6~66) winsize 61
4053 00:43:51.550568 [CA 1] Center 36 (6~66) winsize 61
4054 00:43:51.553744 [CA 2] Center 33 (3~64) winsize 62
4055 00:43:51.557039 [CA 3] Center 34 (4~64) winsize 61
4056 00:43:51.560752 [CA 4] Center 33 (2~64) winsize 63
4057 00:43:51.563930 [CA 5] Center 33 (2~64) winsize 63
4058 00:43:51.564344
4059 00:43:51.566911 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4060 00:43:51.567325
4061 00:43:51.570623 [CATrainingPosCal] consider 2 rank data
4062 00:43:51.573491 u2DelayCellTimex100 = 270/100 ps
4063 00:43:51.577076 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4064 00:43:51.583429 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4065 00:43:51.586625 CA2 delay=34 (4~64),Diff = 1 PI (9 cell)
4066 00:43:51.589905 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4067 00:43:51.593331 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4068 00:43:51.596815 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4069 00:43:51.597230
4070 00:43:51.599823 CA PerBit enable=1, Macro0, CA PI delay=33
4071 00:43:51.600284
4072 00:43:51.603441 [CBTSetCACLKResult] CA Dly = 33
4073 00:43:51.606758 CS Dly: 5 (0~36)
4074 00:43:51.607170
4075 00:43:51.609867 ----->DramcWriteLeveling(PI) begin...
4076 00:43:51.610350 ==
4077 00:43:51.612772 Dram Type= 6, Freq= 0, CH_0, rank 0
4078 00:43:51.616201 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4079 00:43:51.616617 ==
4080 00:43:51.619701 Write leveling (Byte 0): 34 => 34
4081 00:43:51.623046 Write leveling (Byte 1): 30 => 30
4082 00:43:51.626138 DramcWriteLeveling(PI) end<-----
4083 00:43:51.626581
4084 00:43:51.626906 ==
4085 00:43:51.629663 Dram Type= 6, Freq= 0, CH_0, rank 0
4086 00:43:51.633295 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4087 00:43:51.633714 ==
4088 00:43:51.636295 [Gating] SW mode calibration
4089 00:43:51.642800 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4090 00:43:51.649263 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4091 00:43:51.652315 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4092 00:43:51.656021 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4093 00:43:51.662536 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4094 00:43:51.665451 0 9 12 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 1)
4095 00:43:51.668944 0 9 16 | B1->B0 | 3030 2929 | 0 0 | (1 1) (0 0)
4096 00:43:51.675665 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4097 00:43:51.678841 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4098 00:43:51.685860 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4099 00:43:51.688962 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4100 00:43:51.692008 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4101 00:43:51.699006 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4102 00:43:51.701783 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4103 00:43:51.705083 0 10 16 | B1->B0 | 3535 3d3d | 0 0 | (0 0) (0 0)
4104 00:43:51.708640 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4105 00:43:51.715110 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4106 00:43:51.718722 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4107 00:43:51.724789 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4108 00:43:51.728217 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4109 00:43:51.731318 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4110 00:43:51.737848 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4111 00:43:51.740990 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4112 00:43:51.744731 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4113 00:43:51.751587 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4114 00:43:51.754840 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4115 00:43:51.757788 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4116 00:43:51.764590 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4117 00:43:51.767725 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4118 00:43:51.771246 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4119 00:43:51.777311 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4120 00:43:51.780634 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4121 00:43:51.784099 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4122 00:43:51.790700 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4123 00:43:51.793742 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4124 00:43:51.797080 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4125 00:43:51.803876 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4126 00:43:51.807142 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4127 00:43:51.810500 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4128 00:43:51.813566 Total UI for P1: 0, mck2ui 16
4129 00:43:51.816639 best dqsien dly found for B0: ( 0, 13, 12)
4130 00:43:51.823227 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4131 00:43:51.823650 Total UI for P1: 0, mck2ui 16
4132 00:43:51.830022 best dqsien dly found for B1: ( 0, 13, 14)
4133 00:43:51.833461 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4134 00:43:51.836653 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4135 00:43:51.836948
4136 00:43:51.839704 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4137 00:43:51.843028 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4138 00:43:51.846422 [Gating] SW calibration Done
4139 00:43:51.846603 ==
4140 00:43:51.849680 Dram Type= 6, Freq= 0, CH_0, rank 0
4141 00:43:51.853075 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4142 00:43:51.853227 ==
4143 00:43:51.856244 RX Vref Scan: 0
4144 00:43:51.856373
4145 00:43:51.856473 RX Vref 0 -> 0, step: 1
4146 00:43:51.856569
4147 00:43:51.859407 RX Delay -230 -> 252, step: 16
4148 00:43:51.866050 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4149 00:43:51.869905 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4150 00:43:51.873194 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4151 00:43:51.876174 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4152 00:43:51.882987 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4153 00:43:51.886307 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4154 00:43:51.889456 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4155 00:43:51.892866 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4156 00:43:51.896341 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4157 00:43:51.902838 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4158 00:43:51.906200 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4159 00:43:51.909145 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4160 00:43:51.912571 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4161 00:43:51.919169 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4162 00:43:51.922586 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4163 00:43:51.925983 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4164 00:43:51.926430 ==
4165 00:43:51.928838 Dram Type= 6, Freq= 0, CH_0, rank 0
4166 00:43:51.935681 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4167 00:43:51.936095 ==
4168 00:43:51.936431 DQS Delay:
4169 00:43:51.936818 DQS0 = 0, DQS1 = 0
4170 00:43:51.939214 DQM Delay:
4171 00:43:51.939625 DQM0 = 42, DQM1 = 29
4172 00:43:51.942680 DQ Delay:
4173 00:43:51.945496 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =33
4174 00:43:51.948503 DQ4 =41, DQ5 =33, DQ6 =57, DQ7 =49
4175 00:43:51.952163 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4176 00:43:51.955015 DQ12 =33, DQ13 =33, DQ14 =41, DQ15 =33
4177 00:43:51.955410
4178 00:43:51.955716
4179 00:43:51.956039 ==
4180 00:43:51.958444 Dram Type= 6, Freq= 0, CH_0, rank 0
4181 00:43:51.962207 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4182 00:43:51.962628 ==
4183 00:43:51.962977
4184 00:43:51.963281
4185 00:43:51.965119 TX Vref Scan disable
4186 00:43:51.965509 == TX Byte 0 ==
4187 00:43:51.971874 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4188 00:43:51.975096 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4189 00:43:51.978340 == TX Byte 1 ==
4190 00:43:51.981841 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4191 00:43:51.985102 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4192 00:43:51.985469 ==
4193 00:43:51.988214 Dram Type= 6, Freq= 0, CH_0, rank 0
4194 00:43:51.991381 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4195 00:43:51.994646 ==
4196 00:43:51.995055
4197 00:43:51.995378
4198 00:43:51.995679 TX Vref Scan disable
4199 00:43:51.998645 == TX Byte 0 ==
4200 00:43:52.002235 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4201 00:43:52.008516 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4202 00:43:52.008884 == TX Byte 1 ==
4203 00:43:52.012214 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4204 00:43:52.018772 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4205 00:43:52.019187
4206 00:43:52.019540 [DATLAT]
4207 00:43:52.019847 Freq=600, CH0 RK0
4208 00:43:52.020139
4209 00:43:52.021793 DATLAT Default: 0x9
4210 00:43:52.022129 0, 0xFFFF, sum = 0
4211 00:43:52.025018 1, 0xFFFF, sum = 0
4212 00:43:52.028040 2, 0xFFFF, sum = 0
4213 00:43:52.028445 3, 0xFFFF, sum = 0
4214 00:43:52.031508 4, 0xFFFF, sum = 0
4215 00:43:52.031947 5, 0xFFFF, sum = 0
4216 00:43:52.035446 6, 0xFFFF, sum = 0
4217 00:43:52.035864 7, 0xFFFF, sum = 0
4218 00:43:52.038086 8, 0x0, sum = 1
4219 00:43:52.038533 9, 0x0, sum = 2
4220 00:43:52.038867 10, 0x0, sum = 3
4221 00:43:52.041301 11, 0x0, sum = 4
4222 00:43:52.041740 best_step = 9
4223 00:43:52.042067
4224 00:43:52.044971 ==
4225 00:43:52.045548 Dram Type= 6, Freq= 0, CH_0, rank 0
4226 00:43:52.051719 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4227 00:43:52.052135 ==
4228 00:43:52.052459 RX Vref Scan: 1
4229 00:43:52.052764
4230 00:43:52.054715 RX Vref 0 -> 0, step: 1
4231 00:43:52.055135
4232 00:43:52.058479 RX Delay -195 -> 252, step: 8
4233 00:43:52.058891
4234 00:43:52.061837 Set Vref, RX VrefLevel [Byte0]: 60
4235 00:43:52.064889 [Byte1]: 55
4236 00:43:52.065302
4237 00:43:52.068114 Final RX Vref Byte 0 = 60 to rank0
4238 00:43:52.071511 Final RX Vref Byte 1 = 55 to rank0
4239 00:43:52.075037 Final RX Vref Byte 0 = 60 to rank1
4240 00:43:52.078284 Final RX Vref Byte 1 = 55 to rank1==
4241 00:43:52.081266 Dram Type= 6, Freq= 0, CH_0, rank 0
4242 00:43:52.084655 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4243 00:43:52.087532 ==
4244 00:43:52.087996 DQS Delay:
4245 00:43:52.088340 DQS0 = 0, DQS1 = 0
4246 00:43:52.091437 DQM Delay:
4247 00:43:52.091907 DQM0 = 43, DQM1 = 33
4248 00:43:52.094455 DQ Delay:
4249 00:43:52.094869 DQ0 =44, DQ1 =44, DQ2 =40, DQ3 =40
4250 00:43:52.097813 DQ4 =44, DQ5 =36, DQ6 =52, DQ7 =48
4251 00:43:52.101105 DQ8 =20, DQ9 =24, DQ10 =36, DQ11 =24
4252 00:43:52.104270 DQ12 =36, DQ13 =40, DQ14 =44, DQ15 =40
4253 00:43:52.107287
4254 00:43:52.107748
4255 00:43:52.114057 [DQSOSCAuto] RK0, (LSB)MR18= 0x683f, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 390 ps
4256 00:43:52.117765 CH0 RK0: MR19=808, MR18=683F
4257 00:43:52.123991 CH0_RK0: MR19=0x808, MR18=0x683F, DQSOSC=390, MR23=63, INC=172, DEC=114
4258 00:43:52.124409
4259 00:43:52.127090 ----->DramcWriteLeveling(PI) begin...
4260 00:43:52.127510 ==
4261 00:43:52.130686 Dram Type= 6, Freq= 0, CH_0, rank 1
4262 00:43:52.133698 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4263 00:43:52.134117 ==
4264 00:43:52.136954 Write leveling (Byte 0): 35 => 35
4265 00:43:52.140246 Write leveling (Byte 1): 31 => 31
4266 00:43:52.144113 DramcWriteLeveling(PI) end<-----
4267 00:43:52.144524
4268 00:43:52.144846 ==
4269 00:43:52.147025 Dram Type= 6, Freq= 0, CH_0, rank 1
4270 00:43:52.150099 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4271 00:43:52.150553 ==
4272 00:43:52.153854 [Gating] SW mode calibration
4273 00:43:52.160241 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4274 00:43:52.166953 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4275 00:43:52.170207 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4276 00:43:52.176597 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4277 00:43:52.179945 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4278 00:43:52.183087 0 9 12 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
4279 00:43:52.189795 0 9 16 | B1->B0 | 2e2e 2727 | 0 0 | (0 0) (0 0)
4280 00:43:52.192979 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4281 00:43:52.196895 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4282 00:43:52.202653 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4283 00:43:52.206046 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4284 00:43:52.209184 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4285 00:43:52.215937 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4286 00:43:52.219495 0 10 12 | B1->B0 | 2525 2828 | 0 1 | (0 0) (0 0)
4287 00:43:52.222340 0 10 16 | B1->B0 | 3a3a 4040 | 0 0 | (0 0) (0 0)
4288 00:43:52.229027 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4289 00:43:52.232629 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4290 00:43:52.235832 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4291 00:43:52.242519 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4292 00:43:52.245807 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4293 00:43:52.249100 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4294 00:43:52.255281 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4295 00:43:52.258594 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4296 00:43:52.262019 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4297 00:43:52.268891 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4298 00:43:52.271878 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4299 00:43:52.275707 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4300 00:43:52.282131 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4301 00:43:52.285379 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4302 00:43:52.288839 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4303 00:43:52.294995 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4304 00:43:52.298365 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4305 00:43:52.301464 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4306 00:43:52.308647 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4307 00:43:52.311395 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4308 00:43:52.314745 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4309 00:43:52.321515 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4310 00:43:52.325057 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4311 00:43:52.327826 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4312 00:43:52.331242 Total UI for P1: 0, mck2ui 16
4313 00:43:52.334598 best dqsien dly found for B1: ( 0, 13, 12)
4314 00:43:52.341153 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4315 00:43:52.341535 Total UI for P1: 0, mck2ui 16
4316 00:43:52.347960 best dqsien dly found for B0: ( 0, 13, 14)
4317 00:43:52.351066 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4318 00:43:52.354503 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4319 00:43:52.354919
4320 00:43:52.357908 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4321 00:43:52.361123 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4322 00:43:52.364071 [Gating] SW calibration Done
4323 00:43:52.364436 ==
4324 00:43:52.367923 Dram Type= 6, Freq= 0, CH_0, rank 1
4325 00:43:52.370757 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4326 00:43:52.371171 ==
4327 00:43:52.374359 RX Vref Scan: 0
4328 00:43:52.374759
4329 00:43:52.377604 RX Vref 0 -> 0, step: 1
4330 00:43:52.377971
4331 00:43:52.378316 RX Delay -230 -> 252, step: 16
4332 00:43:52.384360 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4333 00:43:52.387456 iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336
4334 00:43:52.390521 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4335 00:43:52.393807 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4336 00:43:52.400599 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4337 00:43:52.403886 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4338 00:43:52.407212 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4339 00:43:52.410245 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4340 00:43:52.417292 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4341 00:43:52.420456 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4342 00:43:52.423687 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4343 00:43:52.426813 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4344 00:43:52.433240 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4345 00:43:52.436873 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4346 00:43:52.440254 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4347 00:43:52.443091 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4348 00:43:52.443564 ==
4349 00:43:52.446643 Dram Type= 6, Freq= 0, CH_0, rank 1
4350 00:43:52.453172 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4351 00:43:52.453586 ==
4352 00:43:52.454010 DQS Delay:
4353 00:43:52.456287 DQS0 = 0, DQS1 = 0
4354 00:43:52.456654 DQM Delay:
4355 00:43:52.456962 DQM0 = 42, DQM1 = 36
4356 00:43:52.459736 DQ Delay:
4357 00:43:52.463004 DQ0 =41, DQ1 =49, DQ2 =41, DQ3 =33
4358 00:43:52.466257 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4359 00:43:52.469830 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4360 00:43:52.472866 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =41
4361 00:43:52.473282
4362 00:43:52.473603
4363 00:43:52.473904 ==
4364 00:43:52.476207 Dram Type= 6, Freq= 0, CH_0, rank 1
4365 00:43:52.479797 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4366 00:43:52.480215 ==
4367 00:43:52.480540
4368 00:43:52.480951
4369 00:43:52.482853 TX Vref Scan disable
4370 00:43:52.486217 == TX Byte 0 ==
4371 00:43:52.489321 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4372 00:43:52.492917 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4373 00:43:52.496139 == TX Byte 1 ==
4374 00:43:52.499329 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4375 00:43:52.502344 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4376 00:43:52.502572 ==
4377 00:43:52.505591 Dram Type= 6, Freq= 0, CH_0, rank 1
4378 00:43:52.512256 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4379 00:43:52.512481 ==
4380 00:43:52.512658
4381 00:43:52.512820
4382 00:43:52.512974 TX Vref Scan disable
4383 00:43:52.516855 == TX Byte 0 ==
4384 00:43:52.520159 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4385 00:43:52.526669 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4386 00:43:52.526922 == TX Byte 1 ==
4387 00:43:52.529688 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4388 00:43:52.536592 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4389 00:43:52.536866
4390 00:43:52.537079 [DATLAT]
4391 00:43:52.537281 Freq=600, CH0 RK1
4392 00:43:52.537476
4393 00:43:52.539501 DATLAT Default: 0x9
4394 00:43:52.539811 0, 0xFFFF, sum = 0
4395 00:43:52.543350 1, 0xFFFF, sum = 0
4396 00:43:52.546097 2, 0xFFFF, sum = 0
4397 00:43:52.546521 3, 0xFFFF, sum = 0
4398 00:43:52.549609 4, 0xFFFF, sum = 0
4399 00:43:52.550082 5, 0xFFFF, sum = 0
4400 00:43:52.552969 6, 0xFFFF, sum = 0
4401 00:43:52.553399 7, 0xFFFF, sum = 0
4402 00:43:52.556341 8, 0x0, sum = 1
4403 00:43:52.556759 9, 0x0, sum = 2
4404 00:43:52.559424 10, 0x0, sum = 3
4405 00:43:52.559851 11, 0x0, sum = 4
4406 00:43:52.560220 best_step = 9
4407 00:43:52.560538
4408 00:43:52.563262 ==
4409 00:43:52.563854 Dram Type= 6, Freq= 0, CH_0, rank 1
4410 00:43:52.569415 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4411 00:43:52.569835 ==
4412 00:43:52.570507 RX Vref Scan: 0
4413 00:43:52.571043
4414 00:43:52.572918 RX Vref 0 -> 0, step: 1
4415 00:43:52.573330
4416 00:43:52.575630 RX Delay -179 -> 252, step: 8
4417 00:43:52.582649 iDelay=205, Bit 0, Center 36 (-115 ~ 188) 304
4418 00:43:52.585752 iDelay=205, Bit 1, Center 40 (-115 ~ 196) 312
4419 00:43:52.589393 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4420 00:43:52.592467 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4421 00:43:52.595699 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4422 00:43:52.602546 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4423 00:43:52.605890 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4424 00:43:52.609531 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4425 00:43:52.612792 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4426 00:43:52.619023 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4427 00:43:52.622263 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4428 00:43:52.625632 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4429 00:43:52.628587 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4430 00:43:52.635676 iDelay=205, Bit 13, Center 44 (-107 ~ 196) 304
4431 00:43:52.638616 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4432 00:43:52.641810 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4433 00:43:52.642274 ==
4434 00:43:52.645354 Dram Type= 6, Freq= 0, CH_0, rank 1
4435 00:43:52.648368 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4436 00:43:52.651733 ==
4437 00:43:52.652319 DQS Delay:
4438 00:43:52.652847 DQS0 = 0, DQS1 = 0
4439 00:43:52.655197 DQM Delay:
4440 00:43:52.655707 DQM0 = 40, DQM1 = 35
4441 00:43:52.658725 DQ Delay:
4442 00:43:52.659296 DQ0 =36, DQ1 =40, DQ2 =36, DQ3 =40
4443 00:43:52.661681 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =48
4444 00:43:52.665196 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =28
4445 00:43:52.668366 DQ12 =40, DQ13 =44, DQ14 =44, DQ15 =44
4446 00:43:52.671615
4447 00:43:52.672027
4448 00:43:52.678349 [DQSOSCAuto] RK1, (LSB)MR18= 0x6014, (MSB)MR19= 0x808, tDQSOscB0 = 406 ps tDQSOscB1 = 391 ps
4449 00:43:52.681115 CH0 RK1: MR19=808, MR18=6014
4450 00:43:52.688179 CH0_RK1: MR19=0x808, MR18=0x6014, DQSOSC=391, MR23=63, INC=171, DEC=114
4451 00:43:52.691736 [RxdqsGatingPostProcess] freq 600
4452 00:43:52.694485 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4453 00:43:52.697668 Pre-setting of DQS Precalculation
4454 00:43:52.704520 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4455 00:43:52.705036 ==
4456 00:43:52.708051 Dram Type= 6, Freq= 0, CH_1, rank 0
4457 00:43:52.711514 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4458 00:43:52.711934 ==
4459 00:43:52.717579 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4460 00:43:52.720879 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4461 00:43:52.725840 [CA 0] Center 35 (5~66) winsize 62
4462 00:43:52.728730 [CA 1] Center 35 (5~66) winsize 62
4463 00:43:52.732327 [CA 2] Center 34 (4~65) winsize 62
4464 00:43:52.735566 [CA 3] Center 33 (3~64) winsize 62
4465 00:43:52.739007 [CA 4] Center 34 (4~64) winsize 61
4466 00:43:52.742225 [CA 5] Center 33 (3~64) winsize 62
4467 00:43:52.742695
4468 00:43:52.745156 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4469 00:43:52.745570
4470 00:43:52.748781 [CATrainingPosCal] consider 1 rank data
4471 00:43:52.751972 u2DelayCellTimex100 = 270/100 ps
4472 00:43:52.755185 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4473 00:43:52.761660 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4474 00:43:52.764833 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4475 00:43:52.768608 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4476 00:43:52.771817 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4477 00:43:52.774901 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4478 00:43:52.775312
4479 00:43:52.777990 CA PerBit enable=1, Macro0, CA PI delay=33
4480 00:43:52.778430
4481 00:43:52.781777 [CBTSetCACLKResult] CA Dly = 33
4482 00:43:52.784957 CS Dly: 5 (0~36)
4483 00:43:52.785368 ==
4484 00:43:52.788039 Dram Type= 6, Freq= 0, CH_1, rank 1
4485 00:43:52.791385 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4486 00:43:52.791772 ==
4487 00:43:52.797834 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4488 00:43:52.804051 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4489 00:43:52.807570 [CA 0] Center 35 (5~66) winsize 62
4490 00:43:52.810848 [CA 1] Center 36 (6~66) winsize 61
4491 00:43:52.814292 [CA 2] Center 34 (4~65) winsize 62
4492 00:43:52.817692 [CA 3] Center 33 (3~64) winsize 62
4493 00:43:52.820827 [CA 4] Center 34 (3~65) winsize 63
4494 00:43:52.823813 [CA 5] Center 33 (3~64) winsize 62
4495 00:43:52.824331
4496 00:43:52.827568 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4497 00:43:52.828017
4498 00:43:52.830469 [CATrainingPosCal] consider 2 rank data
4499 00:43:52.833652 u2DelayCellTimex100 = 270/100 ps
4500 00:43:52.837029 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4501 00:43:52.840243 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4502 00:43:52.844106 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4503 00:43:52.847033 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4504 00:43:52.850117 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4505 00:43:52.854218 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4506 00:43:52.854656
4507 00:43:52.860480 CA PerBit enable=1, Macro0, CA PI delay=33
4508 00:43:52.860898
4509 00:43:52.863828 [CBTSetCACLKResult] CA Dly = 33
4510 00:43:52.864247 CS Dly: 5 (0~36)
4511 00:43:52.864581
4512 00:43:52.866865 ----->DramcWriteLeveling(PI) begin...
4513 00:43:52.867354 ==
4514 00:43:52.869999 Dram Type= 6, Freq= 0, CH_1, rank 0
4515 00:43:52.873823 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4516 00:43:52.874289 ==
4517 00:43:52.877333 Write leveling (Byte 0): 30 => 30
4518 00:43:52.880312 Write leveling (Byte 1): 32 => 32
4519 00:43:52.883266 DramcWriteLeveling(PI) end<-----
4520 00:43:52.883604
4521 00:43:52.883926 ==
4522 00:43:52.886950 Dram Type= 6, Freq= 0, CH_1, rank 0
4523 00:43:52.893095 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4524 00:43:52.893322 ==
4525 00:43:52.893502 [Gating] SW mode calibration
4526 00:43:52.903195 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4527 00:43:52.906598 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4528 00:43:52.910004 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4529 00:43:52.916275 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4530 00:43:52.919756 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4531 00:43:52.922836 0 9 12 | B1->B0 | 3232 2e2e | 1 1 | (1 0) (1 0)
4532 00:43:52.929514 0 9 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4533 00:43:52.932813 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4534 00:43:52.936315 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4535 00:43:52.942886 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4536 00:43:52.946277 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4537 00:43:52.949231 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4538 00:43:52.956073 0 10 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4539 00:43:52.959384 0 10 12 | B1->B0 | 2f2f 3535 | 1 0 | (0 0) (1 1)
4540 00:43:52.962457 0 10 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4541 00:43:52.969106 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4542 00:43:52.972863 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4543 00:43:52.976218 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4544 00:43:52.982370 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4545 00:43:52.985765 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4546 00:43:52.992683 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4547 00:43:52.995577 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4548 00:43:52.998817 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4549 00:43:53.005264 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4550 00:43:53.008796 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4551 00:43:53.011886 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4552 00:43:53.018705 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4553 00:43:53.022020 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4554 00:43:53.025097 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4555 00:43:53.031536 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4556 00:43:53.035299 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4557 00:43:53.038669 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4558 00:43:53.044888 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4559 00:43:53.048314 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4560 00:43:53.051584 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4561 00:43:53.054737 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4562 00:43:53.061025 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4563 00:43:53.064737 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4564 00:43:53.071559 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4565 00:43:53.072086 Total UI for P1: 0, mck2ui 16
4566 00:43:53.074515 best dqsien dly found for B0: ( 0, 13, 10)
4567 00:43:53.077774 Total UI for P1: 0, mck2ui 16
4568 00:43:53.081435 best dqsien dly found for B1: ( 0, 13, 12)
4569 00:43:53.087886 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4570 00:43:53.091193 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4571 00:43:53.091652
4572 00:43:53.094675 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4573 00:43:53.097790 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4574 00:43:53.101311 [Gating] SW calibration Done
4575 00:43:53.101728 ==
4576 00:43:53.104631 Dram Type= 6, Freq= 0, CH_1, rank 0
4577 00:43:53.108031 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4578 00:43:53.108606 ==
4579 00:43:53.111284 RX Vref Scan: 0
4580 00:43:53.111748
4581 00:43:53.112363 RX Vref 0 -> 0, step: 1
4582 00:43:53.112754
4583 00:43:53.114488 RX Delay -230 -> 252, step: 16
4584 00:43:53.117800 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4585 00:43:53.124242 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4586 00:43:53.127459 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4587 00:43:53.130645 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4588 00:43:53.133877 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4589 00:43:53.140718 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4590 00:43:53.143577 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4591 00:43:53.147066 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4592 00:43:53.150277 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4593 00:43:53.156728 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4594 00:43:53.160315 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4595 00:43:53.163770 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4596 00:43:53.166804 iDelay=218, Bit 12, Center 41 (-134 ~ 217) 352
4597 00:43:53.173582 iDelay=218, Bit 13, Center 41 (-134 ~ 217) 352
4598 00:43:53.176804 iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352
4599 00:43:53.180152 iDelay=218, Bit 15, Center 41 (-134 ~ 217) 352
4600 00:43:53.180419 ==
4601 00:43:53.183672 Dram Type= 6, Freq= 0, CH_1, rank 0
4602 00:43:53.186422 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4603 00:43:53.186627 ==
4604 00:43:53.189883 DQS Delay:
4605 00:43:53.190067 DQS0 = 0, DQS1 = 0
4606 00:43:53.193257 DQM Delay:
4607 00:43:53.193440 DQM0 = 42, DQM1 = 33
4608 00:43:53.193633 DQ Delay:
4609 00:43:53.196396 DQ0 =49, DQ1 =41, DQ2 =33, DQ3 =41
4610 00:43:53.199728 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =33
4611 00:43:53.203063 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4612 00:43:53.206482 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4613 00:43:53.206685
4614 00:43:53.206873
4615 00:43:53.209894 ==
4616 00:43:53.213277 Dram Type= 6, Freq= 0, CH_1, rank 0
4617 00:43:53.216584 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4618 00:43:53.216880 ==
4619 00:43:53.217081
4620 00:43:53.217240
4621 00:43:53.219529 TX Vref Scan disable
4622 00:43:53.219734 == TX Byte 0 ==
4623 00:43:53.226714 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4624 00:43:53.229470 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4625 00:43:53.229699 == TX Byte 1 ==
4626 00:43:53.236157 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4627 00:43:53.239235 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4628 00:43:53.239430 ==
4629 00:43:53.242600 Dram Type= 6, Freq= 0, CH_1, rank 0
4630 00:43:53.245953 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4631 00:43:53.246132 ==
4632 00:43:53.246289
4633 00:43:53.246425
4634 00:43:53.249130 TX Vref Scan disable
4635 00:43:53.252687 == TX Byte 0 ==
4636 00:43:53.255968 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4637 00:43:53.259193 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4638 00:43:53.262763 == TX Byte 1 ==
4639 00:43:53.265903 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4640 00:43:53.268975 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4641 00:43:53.272838
4642 00:43:53.273091 [DATLAT]
4643 00:43:53.273289 Freq=600, CH1 RK0
4644 00:43:53.273475
4645 00:43:53.276387 DATLAT Default: 0x9
4646 00:43:53.276644 0, 0xFFFF, sum = 0
4647 00:43:53.279101 1, 0xFFFF, sum = 0
4648 00:43:53.279358 2, 0xFFFF, sum = 0
4649 00:43:53.282338 3, 0xFFFF, sum = 0
4650 00:43:53.285806 4, 0xFFFF, sum = 0
4651 00:43:53.286135 5, 0xFFFF, sum = 0
4652 00:43:53.289035 6, 0xFFFF, sum = 0
4653 00:43:53.289403 7, 0xFFFF, sum = 0
4654 00:43:53.292404 8, 0x0, sum = 1
4655 00:43:53.292855 9, 0x0, sum = 2
4656 00:43:53.293194 10, 0x0, sum = 3
4657 00:43:53.295471 11, 0x0, sum = 4
4658 00:43:53.295915 best_step = 9
4659 00:43:53.296351
4660 00:43:53.296665 ==
4661 00:43:53.298830 Dram Type= 6, Freq= 0, CH_1, rank 0
4662 00:43:53.305509 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4663 00:43:53.305956 ==
4664 00:43:53.306451 RX Vref Scan: 1
4665 00:43:53.306776
4666 00:43:53.308943 RX Vref 0 -> 0, step: 1
4667 00:43:53.309353
4668 00:43:53.312149 RX Delay -195 -> 252, step: 8
4669 00:43:53.312560
4670 00:43:53.315564 Set Vref, RX VrefLevel [Byte0]: 49
4671 00:43:53.318967 [Byte1]: 51
4672 00:43:53.319378
4673 00:43:53.322663 Final RX Vref Byte 0 = 49 to rank0
4674 00:43:53.325790 Final RX Vref Byte 1 = 51 to rank0
4675 00:43:53.328929 Final RX Vref Byte 0 = 49 to rank1
4676 00:43:53.332372 Final RX Vref Byte 1 = 51 to rank1==
4677 00:43:53.335540 Dram Type= 6, Freq= 0, CH_1, rank 0
4678 00:43:53.338742 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4679 00:43:53.339157 ==
4680 00:43:53.342241 DQS Delay:
4681 00:43:53.342659 DQS0 = 0, DQS1 = 0
4682 00:43:53.345512 DQM Delay:
4683 00:43:53.345925 DQM0 = 44, DQM1 = 33
4684 00:43:53.346400 DQ Delay:
4685 00:43:53.348625 DQ0 =52, DQ1 =40, DQ2 =36, DQ3 =40
4686 00:43:53.352297 DQ4 =40, DQ5 =56, DQ6 =52, DQ7 =40
4687 00:43:53.355329 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =24
4688 00:43:53.358736 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4689 00:43:53.359183
4690 00:43:53.359510
4691 00:43:53.368874 [DQSOSCAuto] RK0, (LSB)MR18= 0x4c30, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 395 ps
4692 00:43:53.371622 CH1 RK0: MR19=808, MR18=4C30
4693 00:43:53.378342 CH1_RK0: MR19=0x808, MR18=0x4C30, DQSOSC=395, MR23=63, INC=168, DEC=112
4694 00:43:53.378853
4695 00:43:53.381378 ----->DramcWriteLeveling(PI) begin...
4696 00:43:53.381924 ==
4697 00:43:53.384569 Dram Type= 6, Freq= 0, CH_1, rank 1
4698 00:43:53.388483 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4699 00:43:53.388903 ==
4700 00:43:53.391847 Write leveling (Byte 0): 30 => 30
4701 00:43:53.394855 Write leveling (Byte 1): 30 => 30
4702 00:43:53.398277 DramcWriteLeveling(PI) end<-----
4703 00:43:53.398697
4704 00:43:53.399113 ==
4705 00:43:53.401062 Dram Type= 6, Freq= 0, CH_1, rank 1
4706 00:43:53.404372 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4707 00:43:53.404880 ==
4708 00:43:53.408272 [Gating] SW mode calibration
4709 00:43:53.414837 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4710 00:43:53.420579 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4711 00:43:53.424023 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4712 00:43:53.430487 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4713 00:43:53.433924 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4714 00:43:53.437032 0 9 12 | B1->B0 | 3030 3434 | 0 0 | (0 0) (0 1)
4715 00:43:53.443829 0 9 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4716 00:43:53.446651 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4717 00:43:53.450284 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4718 00:43:53.456580 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4719 00:43:53.459928 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4720 00:43:53.463149 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4721 00:43:53.469849 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4722 00:43:53.473681 0 10 12 | B1->B0 | 3131 2f2f | 0 0 | (0 0) (0 0)
4723 00:43:53.476455 0 10 16 | B1->B0 | 4444 4444 | 1 0 | (0 0) (0 0)
4724 00:43:53.483042 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4725 00:43:53.486801 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4726 00:43:53.490178 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4727 00:43:53.496708 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4728 00:43:53.499803 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4729 00:43:53.503098 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4730 00:43:53.509957 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4731 00:43:53.513199 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4732 00:43:53.516240 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4733 00:43:53.522973 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4734 00:43:53.526615 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4735 00:43:53.529541 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4736 00:43:53.536060 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4737 00:43:53.539311 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4738 00:43:53.542744 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4739 00:43:53.549202 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4740 00:43:53.552882 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4741 00:43:53.555736 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4742 00:43:53.562311 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4743 00:43:53.565557 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4744 00:43:53.569179 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4745 00:43:53.575729 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4746 00:43:53.579425 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4747 00:43:53.582376 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4748 00:43:53.585987 Total UI for P1: 0, mck2ui 16
4749 00:43:53.589396 best dqsien dly found for B0: ( 0, 13, 12)
4750 00:43:53.592449 Total UI for P1: 0, mck2ui 16
4751 00:43:53.595845 best dqsien dly found for B1: ( 0, 13, 12)
4752 00:43:53.598998 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4753 00:43:53.602134 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4754 00:43:53.602616
4755 00:43:53.608818 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4756 00:43:53.611830 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4757 00:43:53.612378 [Gating] SW calibration Done
4758 00:43:53.615070 ==
4759 00:43:53.618619 Dram Type= 6, Freq= 0, CH_1, rank 1
4760 00:43:53.621932 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4761 00:43:53.622381 ==
4762 00:43:53.622710 RX Vref Scan: 0
4763 00:43:53.623018
4764 00:43:53.625192 RX Vref 0 -> 0, step: 1
4765 00:43:53.625605
4766 00:43:53.628970 RX Delay -230 -> 252, step: 16
4767 00:43:53.632027 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4768 00:43:53.635328 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4769 00:43:53.641562 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4770 00:43:53.645087 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4771 00:43:53.648894 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4772 00:43:53.652267 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4773 00:43:53.658116 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4774 00:43:53.661817 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4775 00:43:53.664907 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4776 00:43:53.668082 iDelay=218, Bit 9, Center 33 (-134 ~ 201) 336
4777 00:43:53.674731 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4778 00:43:53.677957 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4779 00:43:53.681382 iDelay=218, Bit 12, Center 41 (-134 ~ 217) 352
4780 00:43:53.684772 iDelay=218, Bit 13, Center 41 (-134 ~ 217) 352
4781 00:43:53.691201 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4782 00:43:53.694548 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4783 00:43:53.695096 ==
4784 00:43:53.697722 Dram Type= 6, Freq= 0, CH_1, rank 1
4785 00:43:53.700834 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4786 00:43:53.701353 ==
4787 00:43:53.704357 DQS Delay:
4788 00:43:53.704770 DQS0 = 0, DQS1 = 0
4789 00:43:53.705096 DQM Delay:
4790 00:43:53.707816 DQM0 = 38, DQM1 = 34
4791 00:43:53.708232 DQ Delay:
4792 00:43:53.711159 DQ0 =41, DQ1 =33, DQ2 =25, DQ3 =41
4793 00:43:53.714149 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4794 00:43:53.717600 DQ8 =17, DQ9 =33, DQ10 =33, DQ11 =25
4795 00:43:53.721426 DQ12 =41, DQ13 =41, DQ14 =33, DQ15 =49
4796 00:43:53.721840
4797 00:43:53.722204
4798 00:43:53.722526 ==
4799 00:43:53.724178 Dram Type= 6, Freq= 0, CH_1, rank 1
4800 00:43:53.730549 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4801 00:43:53.730967 ==
4802 00:43:53.731363
4803 00:43:53.731683
4804 00:43:53.731988 TX Vref Scan disable
4805 00:43:53.734555 == TX Byte 0 ==
4806 00:43:53.737832 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4807 00:43:53.744179 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4808 00:43:53.744654 == TX Byte 1 ==
4809 00:43:53.747598 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4810 00:43:53.753900 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4811 00:43:53.754453 ==
4812 00:43:53.757366 Dram Type= 6, Freq= 0, CH_1, rank 1
4813 00:43:53.760963 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4814 00:43:53.761582 ==
4815 00:43:53.761921
4816 00:43:53.762272
4817 00:43:53.764094 TX Vref Scan disable
4818 00:43:53.767710 == TX Byte 0 ==
4819 00:43:53.770819 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4820 00:43:53.773905 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4821 00:43:53.777388 == TX Byte 1 ==
4822 00:43:53.780482 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4823 00:43:53.783964 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4824 00:43:53.784404
4825 00:43:53.784813 [DATLAT]
4826 00:43:53.787009 Freq=600, CH1 RK1
4827 00:43:53.787449
4828 00:43:53.790389 DATLAT Default: 0x9
4829 00:43:53.790805 0, 0xFFFF, sum = 0
4830 00:43:53.793589 1, 0xFFFF, sum = 0
4831 00:43:53.794031 2, 0xFFFF, sum = 0
4832 00:43:53.796827 3, 0xFFFF, sum = 0
4833 00:43:53.797398 4, 0xFFFF, sum = 0
4834 00:43:53.800124 5, 0xFFFF, sum = 0
4835 00:43:53.800545 6, 0xFFFF, sum = 0
4836 00:43:53.803721 7, 0xFFFF, sum = 0
4837 00:43:53.804174 8, 0x0, sum = 1
4838 00:43:53.806902 9, 0x0, sum = 2
4839 00:43:53.807352 10, 0x0, sum = 3
4840 00:43:53.810052 11, 0x0, sum = 4
4841 00:43:53.810567 best_step = 9
4842 00:43:53.810901
4843 00:43:53.811207 ==
4844 00:43:53.813569 Dram Type= 6, Freq= 0, CH_1, rank 1
4845 00:43:53.816693 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4846 00:43:53.817111 ==
4847 00:43:53.820105 RX Vref Scan: 0
4848 00:43:53.820615
4849 00:43:53.823525 RX Vref 0 -> 0, step: 1
4850 00:43:53.823938
4851 00:43:53.826747 RX Delay -195 -> 252, step: 8
4852 00:43:53.829575 iDelay=213, Bit 0, Center 48 (-99 ~ 196) 296
4853 00:43:53.833609 iDelay=213, Bit 1, Center 36 (-115 ~ 188) 304
4854 00:43:53.839508 iDelay=213, Bit 2, Center 28 (-123 ~ 180) 304
4855 00:43:53.843084 iDelay=213, Bit 3, Center 40 (-107 ~ 188) 296
4856 00:43:53.846132 iDelay=213, Bit 4, Center 40 (-115 ~ 196) 312
4857 00:43:53.849644 iDelay=213, Bit 5, Center 52 (-99 ~ 204) 304
4858 00:43:53.856507 iDelay=213, Bit 6, Center 56 (-99 ~ 212) 312
4859 00:43:53.859388 iDelay=213, Bit 7, Center 40 (-115 ~ 196) 312
4860 00:43:53.862843 iDelay=213, Bit 8, Center 20 (-139 ~ 180) 320
4861 00:43:53.866116 iDelay=213, Bit 9, Center 20 (-139 ~ 180) 320
4862 00:43:53.869183 iDelay=213, Bit 10, Center 32 (-123 ~ 188) 312
4863 00:43:53.876177 iDelay=213, Bit 11, Center 24 (-131 ~ 180) 312
4864 00:43:53.879352 iDelay=213, Bit 12, Center 44 (-115 ~ 204) 320
4865 00:43:53.882815 iDelay=213, Bit 13, Center 40 (-115 ~ 196) 312
4866 00:43:53.886080 iDelay=213, Bit 14, Center 40 (-115 ~ 196) 312
4867 00:43:53.892812 iDelay=213, Bit 15, Center 44 (-107 ~ 196) 304
4868 00:43:53.893305 ==
4869 00:43:53.895740 Dram Type= 6, Freq= 0, CH_1, rank 1
4870 00:43:53.898904 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4871 00:43:53.899343 ==
4872 00:43:53.899677 DQS Delay:
4873 00:43:53.902408 DQS0 = 0, DQS1 = 0
4874 00:43:53.902826 DQM Delay:
4875 00:43:53.905738 DQM0 = 42, DQM1 = 33
4876 00:43:53.906157 DQ Delay:
4877 00:43:53.908638 DQ0 =48, DQ1 =36, DQ2 =28, DQ3 =40
4878 00:43:53.912533 DQ4 =40, DQ5 =52, DQ6 =56, DQ7 =40
4879 00:43:53.915626 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =24
4880 00:43:53.919338 DQ12 =44, DQ13 =40, DQ14 =40, DQ15 =44
4881 00:43:53.919757
4882 00:43:53.920085
4883 00:43:53.929222 [DQSOSCAuto] RK1, (LSB)MR18= 0x2a1f, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 401 ps
4884 00:43:53.929679 CH1 RK1: MR19=808, MR18=2A1F
4885 00:43:53.935375 CH1_RK1: MR19=0x808, MR18=0x2A1F, DQSOSC=401, MR23=63, INC=163, DEC=108
4886 00:43:53.938806 [RxdqsGatingPostProcess] freq 600
4887 00:43:53.945173 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4888 00:43:53.948647 Pre-setting of DQS Precalculation
4889 00:43:53.951918 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4890 00:43:53.958285 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4891 00:43:53.968617 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4892 00:43:53.969042
4893 00:43:53.969283
4894 00:43:53.971554 [Calibration Summary] 1200 Mbps
4895 00:43:53.971847 CH 0, Rank 0
4896 00:43:53.975170 SW Impedance : PASS
4897 00:43:53.975465 DUTY Scan : NO K
4898 00:43:53.978181 ZQ Calibration : PASS
4899 00:43:53.981323 Jitter Meter : NO K
4900 00:43:53.981620 CBT Training : PASS
4901 00:43:53.985148 Write leveling : PASS
4902 00:43:53.988462 RX DQS gating : PASS
4903 00:43:53.988901 RX DQ/DQS(RDDQC) : PASS
4904 00:43:53.991253 TX DQ/DQS : PASS
4905 00:43:53.991595 RX DATLAT : PASS
4906 00:43:53.994744 RX DQ/DQS(Engine): PASS
4907 00:43:53.997623 TX OE : NO K
4908 00:43:53.998018 All Pass.
4909 00:43:53.998403
4910 00:43:54.001338 CH 0, Rank 1
4911 00:43:54.001644 SW Impedance : PASS
4912 00:43:54.004691 DUTY Scan : NO K
4913 00:43:54.005000 ZQ Calibration : PASS
4914 00:43:54.007875 Jitter Meter : NO K
4915 00:43:54.011018 CBT Training : PASS
4916 00:43:54.011356 Write leveling : PASS
4917 00:43:54.014433 RX DQS gating : PASS
4918 00:43:54.017858 RX DQ/DQS(RDDQC) : PASS
4919 00:43:54.018153 TX DQ/DQS : PASS
4920 00:43:54.020924 RX DATLAT : PASS
4921 00:43:54.024399 RX DQ/DQS(Engine): PASS
4922 00:43:54.024694 TX OE : NO K
4923 00:43:54.027963 All Pass.
4924 00:43:54.028258
4925 00:43:54.028492 CH 1, Rank 0
4926 00:43:54.030729 SW Impedance : PASS
4927 00:43:54.031127 DUTY Scan : NO K
4928 00:43:54.033876 ZQ Calibration : PASS
4929 00:43:54.037696 Jitter Meter : NO K
4930 00:43:54.038005 CBT Training : PASS
4931 00:43:54.040762 Write leveling : PASS
4932 00:43:54.043826 RX DQS gating : PASS
4933 00:43:54.044186 RX DQ/DQS(RDDQC) : PASS
4934 00:43:54.047312 TX DQ/DQS : PASS
4935 00:43:54.050800 RX DATLAT : PASS
4936 00:43:54.051134 RX DQ/DQS(Engine): PASS
4937 00:43:54.054039 TX OE : NO K
4938 00:43:54.054380 All Pass.
4939 00:43:54.054689
4940 00:43:54.057417 CH 1, Rank 1
4941 00:43:54.057739 SW Impedance : PASS
4942 00:43:54.060703 DUTY Scan : NO K
4943 00:43:54.063962 ZQ Calibration : PASS
4944 00:43:54.064265 Jitter Meter : NO K
4945 00:43:54.067116 CBT Training : PASS
4946 00:43:54.070512 Write leveling : PASS
4947 00:43:54.070817 RX DQS gating : PASS
4948 00:43:54.073918 RX DQ/DQS(RDDQC) : PASS
4949 00:43:54.074258 TX DQ/DQS : PASS
4950 00:43:54.077360 RX DATLAT : PASS
4951 00:43:54.080452 RX DQ/DQS(Engine): PASS
4952 00:43:54.080757 TX OE : NO K
4953 00:43:54.083489 All Pass.
4954 00:43:54.083792
4955 00:43:54.084103 DramC Write-DBI off
4956 00:43:54.086904 PER_BANK_REFRESH: Hybrid Mode
4957 00:43:54.090529 TX_TRACKING: ON
4958 00:43:54.096625 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4959 00:43:54.100175 [FAST_K] Save calibration result to emmc
4960 00:43:54.106752 dramc_set_vcore_voltage set vcore to 662500
4961 00:43:54.107058 Read voltage for 933, 3
4962 00:43:54.109523 Vio18 = 0
4963 00:43:54.109829 Vcore = 662500
4964 00:43:54.110213 Vdram = 0
4965 00:43:54.110508 Vddq = 0
4966 00:43:54.112839 Vmddr = 0
4967 00:43:54.116726 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4968 00:43:54.123181 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4969 00:43:54.126222 MEM_TYPE=3, freq_sel=17
4970 00:43:54.126526 sv_algorithm_assistance_LP4_1600
4971 00:43:54.132902 ============ PULL DRAM RESETB DOWN ============
4972 00:43:54.136321 ========== PULL DRAM RESETB DOWN end =========
4973 00:43:54.139444 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4974 00:43:54.142561 ===================================
4975 00:43:54.146194 LPDDR4 DRAM CONFIGURATION
4976 00:43:54.149399 ===================================
4977 00:43:54.152705 EX_ROW_EN[0] = 0x0
4978 00:43:54.152998 EX_ROW_EN[1] = 0x0
4979 00:43:54.156102 LP4Y_EN = 0x0
4980 00:43:54.156394 WORK_FSP = 0x0
4981 00:43:54.159262 WL = 0x3
4982 00:43:54.159554 RL = 0x3
4983 00:43:54.162253 BL = 0x2
4984 00:43:54.162557 RPST = 0x0
4985 00:43:54.165936 RD_PRE = 0x0
4986 00:43:54.168880 WR_PRE = 0x1
4987 00:43:54.169311 WR_PST = 0x0
4988 00:43:54.172690 DBI_WR = 0x0
4989 00:43:54.172983 DBI_RD = 0x0
4990 00:43:54.175716 OTF = 0x1
4991 00:43:54.178864 ===================================
4992 00:43:54.182202 ===================================
4993 00:43:54.182522 ANA top config
4994 00:43:54.185346 ===================================
4995 00:43:54.188912 DLL_ASYNC_EN = 0
4996 00:43:54.191797 ALL_SLAVE_EN = 1
4997 00:43:54.192100 NEW_RANK_MODE = 1
4998 00:43:54.195569 DLL_IDLE_MODE = 1
4999 00:43:54.198370 LP45_APHY_COMB_EN = 1
5000 00:43:54.201595 TX_ODT_DIS = 1
5001 00:43:54.205391 NEW_8X_MODE = 1
5002 00:43:54.208534 ===================================
5003 00:43:54.211851 ===================================
5004 00:43:54.212157 data_rate = 1866
5005 00:43:54.214935 CKR = 1
5006 00:43:54.218397 DQ_P2S_RATIO = 8
5007 00:43:54.221698 ===================================
5008 00:43:54.225694 CA_P2S_RATIO = 8
5009 00:43:54.228877 DQ_CA_OPEN = 0
5010 00:43:54.231563 DQ_SEMI_OPEN = 0
5011 00:43:54.231877 CA_SEMI_OPEN = 0
5012 00:43:54.234698 CA_FULL_RATE = 0
5013 00:43:54.238403 DQ_CKDIV4_EN = 1
5014 00:43:54.241890 CA_CKDIV4_EN = 1
5015 00:43:54.244633 CA_PREDIV_EN = 0
5016 00:43:54.248141 PH8_DLY = 0
5017 00:43:54.248637 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
5018 00:43:54.251602 DQ_AAMCK_DIV = 4
5019 00:43:54.254692 CA_AAMCK_DIV = 4
5020 00:43:54.257839 CA_ADMCK_DIV = 4
5021 00:43:54.261549 DQ_TRACK_CA_EN = 0
5022 00:43:54.264401 CA_PICK = 933
5023 00:43:54.267701 CA_MCKIO = 933
5024 00:43:54.268015 MCKIO_SEMI = 0
5025 00:43:54.271339 PLL_FREQ = 3732
5026 00:43:54.274486 DQ_UI_PI_RATIO = 32
5027 00:43:54.277967 CA_UI_PI_RATIO = 0
5028 00:43:54.281473 ===================================
5029 00:43:54.284655 ===================================
5030 00:43:54.287717 memory_type:LPDDR4
5031 00:43:54.288123 GP_NUM : 10
5032 00:43:54.291088 SRAM_EN : 1
5033 00:43:54.294102 MD32_EN : 0
5034 00:43:54.297710 ===================================
5035 00:43:54.298016 [ANA_INIT] >>>>>>>>>>>>>>
5036 00:43:54.301007 <<<<<< [CONFIGURE PHASE]: ANA_TX
5037 00:43:54.304020 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5038 00:43:54.307473 ===================================
5039 00:43:54.310688 data_rate = 1866,PCW = 0X8f00
5040 00:43:54.313909 ===================================
5041 00:43:54.317273 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5042 00:43:54.323935 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5043 00:43:54.330572 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5044 00:43:54.333317 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5045 00:43:54.336858 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5046 00:43:54.340609 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5047 00:43:54.343740 [ANA_INIT] flow start
5048 00:43:54.344055 [ANA_INIT] PLL >>>>>>>>
5049 00:43:54.346924 [ANA_INIT] PLL <<<<<<<<
5050 00:43:54.350238 [ANA_INIT] MIDPI >>>>>>>>
5051 00:43:54.350544 [ANA_INIT] MIDPI <<<<<<<<
5052 00:43:54.353292 [ANA_INIT] DLL >>>>>>>>
5053 00:43:54.356709 [ANA_INIT] flow end
5054 00:43:54.359750 ============ LP4 DIFF to SE enter ============
5055 00:43:54.363333 ============ LP4 DIFF to SE exit ============
5056 00:43:54.366472 [ANA_INIT] <<<<<<<<<<<<<
5057 00:43:54.369762 [Flow] Enable top DCM control >>>>>
5058 00:43:54.373282 [Flow] Enable top DCM control <<<<<
5059 00:43:54.376631 Enable DLL master slave shuffle
5060 00:43:54.383189 ==============================================================
5061 00:43:54.383593 Gating Mode config
5062 00:43:54.389846 ==============================================================
5063 00:43:54.390444 Config description:
5064 00:43:54.400247 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5065 00:43:54.406121 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5066 00:43:54.412796 SELPH_MODE 0: By rank 1: By Phase
5067 00:43:54.415986 ==============================================================
5068 00:43:54.419505 GAT_TRACK_EN = 1
5069 00:43:54.422692 RX_GATING_MODE = 2
5070 00:43:54.426124 RX_GATING_TRACK_MODE = 2
5071 00:43:54.429658 SELPH_MODE = 1
5072 00:43:54.432833 PICG_EARLY_EN = 1
5073 00:43:54.435863 VALID_LAT_VALUE = 1
5074 00:43:54.442415 ==============================================================
5075 00:43:54.446189 Enter into Gating configuration >>>>
5076 00:43:54.449097 Exit from Gating configuration <<<<
5077 00:43:54.452482 Enter into DVFS_PRE_config >>>>>
5078 00:43:54.462106 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5079 00:43:54.465274 Exit from DVFS_PRE_config <<<<<
5080 00:43:54.468668 Enter into PICG configuration >>>>
5081 00:43:54.471954 Exit from PICG configuration <<<<
5082 00:43:54.475328 [RX_INPUT] configuration >>>>>
5083 00:43:54.475758 [RX_INPUT] configuration <<<<<
5084 00:43:54.482123 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5085 00:43:54.488712 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5086 00:43:54.491713 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5087 00:43:54.498214 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5088 00:43:54.504777 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5089 00:43:54.511786 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5090 00:43:54.514891 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5091 00:43:54.518276 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5092 00:43:54.524622 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5093 00:43:54.528430 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5094 00:43:54.531337 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5095 00:43:54.538269 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5096 00:43:54.541280 ===================================
5097 00:43:54.541695 LPDDR4 DRAM CONFIGURATION
5098 00:43:54.544611 ===================================
5099 00:43:54.547895 EX_ROW_EN[0] = 0x0
5100 00:43:54.551426 EX_ROW_EN[1] = 0x0
5101 00:43:54.551904 LP4Y_EN = 0x0
5102 00:43:54.554715 WORK_FSP = 0x0
5103 00:43:54.555147 WL = 0x3
5104 00:43:54.558097 RL = 0x3
5105 00:43:54.558569 BL = 0x2
5106 00:43:54.560908 RPST = 0x0
5107 00:43:54.561339 RD_PRE = 0x0
5108 00:43:54.564434 WR_PRE = 0x1
5109 00:43:54.564994 WR_PST = 0x0
5110 00:43:54.567864 DBI_WR = 0x0
5111 00:43:54.568422 DBI_RD = 0x0
5112 00:43:54.570907 OTF = 0x1
5113 00:43:54.574285 ===================================
5114 00:43:54.577712 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5115 00:43:54.580886 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5116 00:43:54.587518 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5117 00:43:54.590695 ===================================
5118 00:43:54.591109 LPDDR4 DRAM CONFIGURATION
5119 00:43:54.593964 ===================================
5120 00:43:54.597074 EX_ROW_EN[0] = 0x10
5121 00:43:54.601024 EX_ROW_EN[1] = 0x0
5122 00:43:54.601108 LP4Y_EN = 0x0
5123 00:43:54.603480 WORK_FSP = 0x0
5124 00:43:54.603564 WL = 0x3
5125 00:43:54.607134 RL = 0x3
5126 00:43:54.607218 BL = 0x2
5127 00:43:54.610525 RPST = 0x0
5128 00:43:54.610609 RD_PRE = 0x0
5129 00:43:54.613550 WR_PRE = 0x1
5130 00:43:54.613635 WR_PST = 0x0
5131 00:43:54.617071 DBI_WR = 0x0
5132 00:43:54.617155 DBI_RD = 0x0
5133 00:43:54.619862 OTF = 0x1
5134 00:43:54.623622 ===================================
5135 00:43:54.629766 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5136 00:43:54.633133 nWR fixed to 30
5137 00:43:54.636592 [ModeRegInit_LP4] CH0 RK0
5138 00:43:54.636715 [ModeRegInit_LP4] CH0 RK1
5139 00:43:54.639717 [ModeRegInit_LP4] CH1 RK0
5140 00:43:54.643062 [ModeRegInit_LP4] CH1 RK1
5141 00:43:54.643150 match AC timing 9
5142 00:43:54.650109 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5143 00:43:54.652787 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5144 00:43:54.656222 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5145 00:43:54.662625 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5146 00:43:54.665991 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5147 00:43:54.666103 ==
5148 00:43:54.669466 Dram Type= 6, Freq= 0, CH_0, rank 0
5149 00:43:54.672596 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5150 00:43:54.672684 ==
5151 00:43:54.679134 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5152 00:43:54.685744 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5153 00:43:54.689036 [CA 0] Center 37 (7~68) winsize 62
5154 00:43:54.692543 [CA 1] Center 37 (7~68) winsize 62
5155 00:43:54.695643 [CA 2] Center 34 (4~65) winsize 62
5156 00:43:54.698905 [CA 3] Center 34 (4~65) winsize 62
5157 00:43:54.702361 [CA 4] Center 33 (3~64) winsize 62
5158 00:43:54.705798 [CA 5] Center 33 (3~64) winsize 62
5159 00:43:54.705884
5160 00:43:54.708928 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5161 00:43:54.709015
5162 00:43:54.712147 [CATrainingPosCal] consider 1 rank data
5163 00:43:54.715655 u2DelayCellTimex100 = 270/100 ps
5164 00:43:54.718895 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5165 00:43:54.722135 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5166 00:43:54.725256 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5167 00:43:54.728505 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5168 00:43:54.735658 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5169 00:43:54.738718 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5170 00:43:54.738804
5171 00:43:54.741865 CA PerBit enable=1, Macro0, CA PI delay=33
5172 00:43:54.741949
5173 00:43:54.745374 [CBTSetCACLKResult] CA Dly = 33
5174 00:43:54.745490 CS Dly: 7 (0~38)
5175 00:43:54.745571 ==
5176 00:43:54.748506 Dram Type= 6, Freq= 0, CH_0, rank 1
5177 00:43:54.755120 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5178 00:43:54.755205 ==
5179 00:43:54.758671 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5180 00:43:54.764892 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5181 00:43:54.768306 [CA 0] Center 37 (7~68) winsize 62
5182 00:43:54.771894 [CA 1] Center 37 (7~68) winsize 62
5183 00:43:54.775205 [CA 2] Center 34 (4~65) winsize 62
5184 00:43:54.778268 [CA 3] Center 34 (4~65) winsize 62
5185 00:43:54.781665 [CA 4] Center 33 (3~64) winsize 62
5186 00:43:54.784887 [CA 5] Center 33 (3~63) winsize 61
5187 00:43:54.784972
5188 00:43:54.787959 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5189 00:43:54.788043
5190 00:43:54.791552 [CATrainingPosCal] consider 2 rank data
5191 00:43:54.794702 u2DelayCellTimex100 = 270/100 ps
5192 00:43:54.798035 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5193 00:43:54.801011 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5194 00:43:54.807631 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5195 00:43:54.811142 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5196 00:43:54.814575 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5197 00:43:54.817709 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5198 00:43:54.817789
5199 00:43:54.821473 CA PerBit enable=1, Macro0, CA PI delay=33
5200 00:43:54.821553
5201 00:43:54.824353 [CBTSetCACLKResult] CA Dly = 33
5202 00:43:54.824433 CS Dly: 7 (0~39)
5203 00:43:54.824497
5204 00:43:54.831037 ----->DramcWriteLeveling(PI) begin...
5205 00:43:54.831118 ==
5206 00:43:54.834366 Dram Type= 6, Freq= 0, CH_0, rank 0
5207 00:43:54.837877 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5208 00:43:54.837958 ==
5209 00:43:54.840955 Write leveling (Byte 0): 31 => 31
5210 00:43:54.844124 Write leveling (Byte 1): 31 => 31
5211 00:43:54.847588 DramcWriteLeveling(PI) end<-----
5212 00:43:54.847668
5213 00:43:54.847731 ==
5214 00:43:54.850958 Dram Type= 6, Freq= 0, CH_0, rank 0
5215 00:43:54.854287 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5216 00:43:54.854368 ==
5217 00:43:54.857565 [Gating] SW mode calibration
5218 00:43:54.864040 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5219 00:43:54.870738 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5220 00:43:54.873931 0 14 0 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
5221 00:43:54.877523 0 14 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5222 00:43:54.883753 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5223 00:43:54.887258 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5224 00:43:54.890477 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5225 00:43:54.897364 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5226 00:43:54.900559 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5227 00:43:54.903758 0 14 28 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (1 0)
5228 00:43:54.910614 0 15 0 | B1->B0 | 3131 2525 | 1 0 | (0 1) (0 0)
5229 00:43:54.913536 0 15 4 | B1->B0 | 2424 2323 | 0 0 | (1 1) (0 0)
5230 00:43:54.917131 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5231 00:43:54.923737 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5232 00:43:54.926978 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5233 00:43:54.930068 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5234 00:43:54.936715 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5235 00:43:54.940452 0 15 28 | B1->B0 | 2323 3535 | 0 0 | (0 0) (1 1)
5236 00:43:54.943443 1 0 0 | B1->B0 | 3131 4444 | 0 0 | (0 0) (0 0)
5237 00:43:54.950091 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5238 00:43:54.953296 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5239 00:43:54.956537 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5240 00:43:54.963403 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5241 00:43:54.966479 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5242 00:43:54.969711 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5243 00:43:54.976340 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5244 00:43:54.979550 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5245 00:43:54.982961 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5246 00:43:54.989486 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5247 00:43:54.992958 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5248 00:43:54.996438 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5249 00:43:54.999739 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5250 00:43:55.006512 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5251 00:43:55.009650 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5252 00:43:55.016021 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5253 00:43:55.019348 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5254 00:43:55.022357 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5255 00:43:55.029249 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5256 00:43:55.032208 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5257 00:43:55.035604 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5258 00:43:55.042180 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5259 00:43:55.045777 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5260 00:43:55.048681 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5261 00:43:55.052014 Total UI for P1: 0, mck2ui 16
5262 00:43:55.055745 best dqsien dly found for B0: ( 1, 2, 30)
5263 00:43:55.062192 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5264 00:43:55.062292 Total UI for P1: 0, mck2ui 16
5265 00:43:55.065388 best dqsien dly found for B1: ( 1, 3, 0)
5266 00:43:55.072021 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5267 00:43:55.075187 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5268 00:43:55.075272
5269 00:43:55.078509 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5270 00:43:55.082041 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5271 00:43:55.085298 [Gating] SW calibration Done
5272 00:43:55.085382 ==
5273 00:43:55.088124 Dram Type= 6, Freq= 0, CH_0, rank 0
5274 00:43:55.091445 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5275 00:43:55.091532 ==
5276 00:43:55.094646 RX Vref Scan: 0
5277 00:43:55.094731
5278 00:43:55.094816 RX Vref 0 -> 0, step: 1
5279 00:43:55.094897
5280 00:43:55.098079 RX Delay -80 -> 252, step: 8
5281 00:43:55.101724 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5282 00:43:55.108188 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5283 00:43:55.111828 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5284 00:43:55.114794 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5285 00:43:55.118282 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5286 00:43:55.121129 iDelay=208, Bit 5, Center 83 (-16 ~ 183) 200
5287 00:43:55.124668 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5288 00:43:55.131110 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5289 00:43:55.134580 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5290 00:43:55.137682 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5291 00:43:55.140906 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5292 00:43:55.144127 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5293 00:43:55.150849 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5294 00:43:55.154101 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5295 00:43:55.157292 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5296 00:43:55.160807 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5297 00:43:55.160893 ==
5298 00:43:55.163734 Dram Type= 6, Freq= 0, CH_0, rank 0
5299 00:43:55.170454 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5300 00:43:55.170543 ==
5301 00:43:55.170630 DQS Delay:
5302 00:43:55.173583 DQS0 = 0, DQS1 = 0
5303 00:43:55.173668 DQM Delay:
5304 00:43:55.173753 DQM0 = 96, DQM1 = 86
5305 00:43:55.176880 DQ Delay:
5306 00:43:55.180203 DQ0 =95, DQ1 =99, DQ2 =91, DQ3 =91
5307 00:43:55.183445 DQ4 =99, DQ5 =83, DQ6 =107, DQ7 =107
5308 00:43:55.187383 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =79
5309 00:43:55.190467 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
5310 00:43:55.190552
5311 00:43:55.190638
5312 00:43:55.190718 ==
5313 00:43:55.193423 Dram Type= 6, Freq= 0, CH_0, rank 0
5314 00:43:55.196949 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5315 00:43:55.197035 ==
5316 00:43:55.197121
5317 00:43:55.197201
5318 00:43:55.200206 TX Vref Scan disable
5319 00:43:55.203255 == TX Byte 0 ==
5320 00:43:55.206898 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5321 00:43:55.210149 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5322 00:43:55.213323 == TX Byte 1 ==
5323 00:43:55.216846 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5324 00:43:55.219694 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5325 00:43:55.219778 ==
5326 00:43:55.223375 Dram Type= 6, Freq= 0, CH_0, rank 0
5327 00:43:55.226390 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5328 00:43:55.229573 ==
5329 00:43:55.229657
5330 00:43:55.229742
5331 00:43:55.229822 TX Vref Scan disable
5332 00:43:55.233449 == TX Byte 0 ==
5333 00:43:55.236620 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5334 00:43:55.243251 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5335 00:43:55.243334 == TX Byte 1 ==
5336 00:43:55.246938 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5337 00:43:55.253149 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5338 00:43:55.253233
5339 00:43:55.253297 [DATLAT]
5340 00:43:55.253357 Freq=933, CH0 RK0
5341 00:43:55.253416
5342 00:43:55.256501 DATLAT Default: 0xd
5343 00:43:55.256581 0, 0xFFFF, sum = 0
5344 00:43:55.260000 1, 0xFFFF, sum = 0
5345 00:43:55.263208 2, 0xFFFF, sum = 0
5346 00:43:55.263289 3, 0xFFFF, sum = 0
5347 00:43:55.266550 4, 0xFFFF, sum = 0
5348 00:43:55.266633 5, 0xFFFF, sum = 0
5349 00:43:55.270083 6, 0xFFFF, sum = 0
5350 00:43:55.270189 7, 0xFFFF, sum = 0
5351 00:43:55.273343 8, 0xFFFF, sum = 0
5352 00:43:55.273427 9, 0xFFFF, sum = 0
5353 00:43:55.276407 10, 0x0, sum = 1
5354 00:43:55.276494 11, 0x0, sum = 2
5355 00:43:55.279900 12, 0x0, sum = 3
5356 00:43:55.280073 13, 0x0, sum = 4
5357 00:43:55.280162 best_step = 11
5358 00:43:55.283270
5359 00:43:55.283435 ==
5360 00:43:55.286300 Dram Type= 6, Freq= 0, CH_0, rank 0
5361 00:43:55.289424 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5362 00:43:55.289508 ==
5363 00:43:55.289573 RX Vref Scan: 1
5364 00:43:55.289633
5365 00:43:55.292901 RX Vref 0 -> 0, step: 1
5366 00:43:55.292982
5367 00:43:55.296205 RX Delay -61 -> 252, step: 4
5368 00:43:55.296292
5369 00:43:55.299507 Set Vref, RX VrefLevel [Byte0]: 60
5370 00:43:55.302471 [Byte1]: 55
5371 00:43:55.306119
5372 00:43:55.306228 Final RX Vref Byte 0 = 60 to rank0
5373 00:43:55.309493 Final RX Vref Byte 1 = 55 to rank0
5374 00:43:55.312518 Final RX Vref Byte 0 = 60 to rank1
5375 00:43:55.315894 Final RX Vref Byte 1 = 55 to rank1==
5376 00:43:55.319187 Dram Type= 6, Freq= 0, CH_0, rank 0
5377 00:43:55.326111 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5378 00:43:55.326235 ==
5379 00:43:55.326317 DQS Delay:
5380 00:43:55.329265 DQS0 = 0, DQS1 = 0
5381 00:43:55.329423 DQM Delay:
5382 00:43:55.329528 DQM0 = 97, DQM1 = 85
5383 00:43:55.332354 DQ Delay:
5384 00:43:55.335620 DQ0 =96, DQ1 =98, DQ2 =94, DQ3 =92
5385 00:43:55.339358 DQ4 =98, DQ5 =88, DQ6 =104, DQ7 =106
5386 00:43:55.342283 DQ8 =78, DQ9 =74, DQ10 =86, DQ11 =80
5387 00:43:55.345702 DQ12 =90, DQ13 =90, DQ14 =94, DQ15 =92
5388 00:43:55.345853
5389 00:43:55.345970
5390 00:43:55.352168 [DQSOSCAuto] RK0, (LSB)MR18= 0x2b12, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 408 ps
5391 00:43:55.355854 CH0 RK0: MR19=505, MR18=2B12
5392 00:43:55.362712 CH0_RK0: MR19=0x505, MR18=0x2B12, DQSOSC=408, MR23=63, INC=65, DEC=43
5393 00:43:55.362953
5394 00:43:55.365571 ----->DramcWriteLeveling(PI) begin...
5395 00:43:55.365871 ==
5396 00:43:55.369085 Dram Type= 6, Freq= 0, CH_0, rank 1
5397 00:43:55.372404 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5398 00:43:55.372793 ==
5399 00:43:55.375759 Write leveling (Byte 0): 35 => 35
5400 00:43:55.379486 Write leveling (Byte 1): 29 => 29
5401 00:43:55.382198 DramcWriteLeveling(PI) end<-----
5402 00:43:55.382584
5403 00:43:55.382895 ==
5404 00:43:55.385672 Dram Type= 6, Freq= 0, CH_0, rank 1
5405 00:43:55.389084 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5406 00:43:55.392307 ==
5407 00:43:55.392703 [Gating] SW mode calibration
5408 00:43:55.402196 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5409 00:43:55.405362 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5410 00:43:55.408650 0 14 0 | B1->B0 | 2c2c 3434 | 1 1 | (0 0) (1 1)
5411 00:43:55.415113 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5412 00:43:55.418382 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5413 00:43:55.421793 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5414 00:43:55.428162 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5415 00:43:55.431969 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5416 00:43:55.434915 0 14 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5417 00:43:55.441752 0 14 28 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (0 0)
5418 00:43:55.444989 0 15 0 | B1->B0 | 2b2b 2525 | 1 1 | (0 0) (0 0)
5419 00:43:55.448368 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5420 00:43:55.454732 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5421 00:43:55.458286 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5422 00:43:55.461346 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5423 00:43:55.467860 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5424 00:43:55.471258 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5425 00:43:55.474767 0 15 28 | B1->B0 | 2727 3535 | 0 0 | (0 0) (1 1)
5426 00:43:55.481649 1 0 0 | B1->B0 | 3939 3f3f | 0 0 | (0 0) (0 0)
5427 00:43:55.484887 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5428 00:43:55.487803 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5429 00:43:55.494828 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5430 00:43:55.497763 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5431 00:43:55.501032 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5432 00:43:55.507622 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5433 00:43:55.510782 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5434 00:43:55.514622 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5435 00:43:55.520709 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5436 00:43:55.523953 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5437 00:43:55.527081 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5438 00:43:55.533861 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5439 00:43:55.537089 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5440 00:43:55.540395 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5441 00:43:55.547106 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5442 00:43:55.550319 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5443 00:43:55.553373 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5444 00:43:55.560098 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5445 00:43:55.563332 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5446 00:43:55.566342 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5447 00:43:55.572973 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5448 00:43:55.576439 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5449 00:43:55.579712 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5450 00:43:55.586152 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5451 00:43:55.589413 Total UI for P1: 0, mck2ui 16
5452 00:43:55.592987 best dqsien dly found for B0: ( 1, 2, 28)
5453 00:43:55.596142 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5454 00:43:55.599303 Total UI for P1: 0, mck2ui 16
5455 00:43:55.602457 best dqsien dly found for B1: ( 1, 2, 30)
5456 00:43:55.605718 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5457 00:43:55.609069 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5458 00:43:55.609253
5459 00:43:55.612562 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5460 00:43:55.619568 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5461 00:43:55.619907 [Gating] SW calibration Done
5462 00:43:55.620214 ==
5463 00:43:55.622595 Dram Type= 6, Freq= 0, CH_0, rank 1
5464 00:43:55.629062 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5465 00:43:55.629302 ==
5466 00:43:55.629487 RX Vref Scan: 0
5467 00:43:55.629661
5468 00:43:55.632431 RX Vref 0 -> 0, step: 1
5469 00:43:55.632668
5470 00:43:55.635778 RX Delay -80 -> 252, step: 8
5471 00:43:55.638842 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5472 00:43:55.642841 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5473 00:43:55.645990 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5474 00:43:55.649291 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5475 00:43:55.655928 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5476 00:43:55.658937 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5477 00:43:55.662579 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5478 00:43:55.665597 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5479 00:43:55.669358 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5480 00:43:55.675594 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5481 00:43:55.679212 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5482 00:43:55.682069 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5483 00:43:55.685540 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5484 00:43:55.689513 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5485 00:43:55.692091 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5486 00:43:55.698587 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5487 00:43:55.699134 ==
5488 00:43:55.701772 Dram Type= 6, Freq= 0, CH_0, rank 1
5489 00:43:55.705092 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5490 00:43:55.705513 ==
5491 00:43:55.705841 DQS Delay:
5492 00:43:55.708256 DQS0 = 0, DQS1 = 0
5493 00:43:55.708674 DQM Delay:
5494 00:43:55.711538 DQM0 = 96, DQM1 = 90
5495 00:43:55.711952 DQ Delay:
5496 00:43:55.715231 DQ0 =95, DQ1 =99, DQ2 =87, DQ3 =91
5497 00:43:55.718494 DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =107
5498 00:43:55.721911 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =87
5499 00:43:55.724923 DQ12 =95, DQ13 =95, DQ14 =99, DQ15 =95
5500 00:43:55.725349
5501 00:43:55.725676
5502 00:43:55.725977 ==
5503 00:43:55.728690 Dram Type= 6, Freq= 0, CH_0, rank 1
5504 00:43:55.731876 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5505 00:43:55.734918 ==
5506 00:43:55.735537
5507 00:43:55.736072
5508 00:43:55.736569 TX Vref Scan disable
5509 00:43:55.738074 == TX Byte 0 ==
5510 00:43:55.741732 Update DQ dly =719 (2 ,6, 15) DQ OEN =(2 ,3)
5511 00:43:55.744745 Update DQM dly =719 (2 ,6, 15) DQM OEN =(2 ,3)
5512 00:43:55.748273 == TX Byte 1 ==
5513 00:43:55.751228 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5514 00:43:55.755105 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5515 00:43:55.758004 ==
5516 00:43:55.761679 Dram Type= 6, Freq= 0, CH_0, rank 1
5517 00:43:55.764615 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5518 00:43:55.765044 ==
5519 00:43:55.765414
5520 00:43:55.765916
5521 00:43:55.768210 TX Vref Scan disable
5522 00:43:55.768626 == TX Byte 0 ==
5523 00:43:55.774599 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5524 00:43:55.778140 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5525 00:43:55.778756 == TX Byte 1 ==
5526 00:43:55.784455 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5527 00:43:55.787514 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5528 00:43:55.787623
5529 00:43:55.787716 [DATLAT]
5530 00:43:55.791113 Freq=933, CH0 RK1
5531 00:43:55.791223
5532 00:43:55.791317 DATLAT Default: 0xb
5533 00:43:55.794525 0, 0xFFFF, sum = 0
5534 00:43:55.794609 1, 0xFFFF, sum = 0
5535 00:43:55.797507 2, 0xFFFF, sum = 0
5536 00:43:55.797580 3, 0xFFFF, sum = 0
5537 00:43:55.800949 4, 0xFFFF, sum = 0
5538 00:43:55.804417 5, 0xFFFF, sum = 0
5539 00:43:55.804518 6, 0xFFFF, sum = 0
5540 00:43:55.807794 7, 0xFFFF, sum = 0
5541 00:43:55.807897 8, 0xFFFF, sum = 0
5542 00:43:55.810581 9, 0xFFFF, sum = 0
5543 00:43:55.810689 10, 0x0, sum = 1
5544 00:43:55.813899 11, 0x0, sum = 2
5545 00:43:55.813979 12, 0x0, sum = 3
5546 00:43:55.817119 13, 0x0, sum = 4
5547 00:43:55.817224 best_step = 11
5548 00:43:55.817303
5549 00:43:55.817360 ==
5550 00:43:55.820745 Dram Type= 6, Freq= 0, CH_0, rank 1
5551 00:43:55.823681 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5552 00:43:55.823761 ==
5553 00:43:55.827186 RX Vref Scan: 0
5554 00:43:55.827291
5555 00:43:55.830481 RX Vref 0 -> 0, step: 1
5556 00:43:55.830561
5557 00:43:55.830624 RX Delay -61 -> 252, step: 4
5558 00:43:55.838265 iDelay=203, Bit 0, Center 92 (-1 ~ 186) 188
5559 00:43:55.841489 iDelay=203, Bit 1, Center 96 (-1 ~ 194) 196
5560 00:43:55.844713 iDelay=203, Bit 2, Center 88 (-5 ~ 182) 188
5561 00:43:55.848137 iDelay=203, Bit 3, Center 92 (-5 ~ 190) 196
5562 00:43:55.851547 iDelay=203, Bit 4, Center 96 (3 ~ 190) 188
5563 00:43:55.857983 iDelay=203, Bit 5, Center 86 (-9 ~ 182) 192
5564 00:43:55.861191 iDelay=203, Bit 6, Center 104 (7 ~ 202) 196
5565 00:43:55.864315 iDelay=203, Bit 7, Center 104 (11 ~ 198) 188
5566 00:43:55.867718 iDelay=203, Bit 8, Center 80 (-13 ~ 174) 188
5567 00:43:55.871400 iDelay=203, Bit 9, Center 78 (-13 ~ 170) 184
5568 00:43:55.874523 iDelay=203, Bit 10, Center 90 (-5 ~ 186) 192
5569 00:43:55.881071 iDelay=203, Bit 11, Center 80 (-13 ~ 174) 188
5570 00:43:55.884366 iDelay=203, Bit 12, Center 90 (-5 ~ 186) 192
5571 00:43:55.887406 iDelay=203, Bit 13, Center 94 (3 ~ 186) 184
5572 00:43:55.890990 iDelay=203, Bit 14, Center 96 (3 ~ 190) 188
5573 00:43:55.894537 iDelay=203, Bit 15, Center 92 (-1 ~ 186) 188
5574 00:43:55.897921 ==
5575 00:43:55.900745 Dram Type= 6, Freq= 0, CH_0, rank 1
5576 00:43:55.904025 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5577 00:43:55.904106 ==
5578 00:43:55.904169 DQS Delay:
5579 00:43:55.907412 DQS0 = 0, DQS1 = 0
5580 00:43:55.907500 DQM Delay:
5581 00:43:55.910826 DQM0 = 94, DQM1 = 87
5582 00:43:55.910935 DQ Delay:
5583 00:43:55.914527 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =92
5584 00:43:55.917492 DQ4 =96, DQ5 =86, DQ6 =104, DQ7 =104
5585 00:43:55.920366 DQ8 =80, DQ9 =78, DQ10 =90, DQ11 =80
5586 00:43:55.923970 DQ12 =90, DQ13 =94, DQ14 =96, DQ15 =92
5587 00:43:55.924050
5588 00:43:55.924113
5589 00:43:55.930576 [DQSOSCAuto] RK1, (LSB)MR18= 0x26f7, (MSB)MR19= 0x504, tDQSOscB0 = 425 ps tDQSOscB1 = 409 ps
5590 00:43:55.933541 CH0 RK1: MR19=504, MR18=26F7
5591 00:43:55.940282 CH0_RK1: MR19=0x504, MR18=0x26F7, DQSOSC=409, MR23=63, INC=64, DEC=43
5592 00:43:55.943613 [RxdqsGatingPostProcess] freq 933
5593 00:43:55.950303 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5594 00:43:55.953831 best DQS0 dly(2T, 0.5T) = (0, 10)
5595 00:43:55.957041 best DQS1 dly(2T, 0.5T) = (0, 11)
5596 00:43:55.960200 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5597 00:43:55.963462 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5598 00:43:55.963610 best DQS0 dly(2T, 0.5T) = (0, 10)
5599 00:43:55.967020 best DQS1 dly(2T, 0.5T) = (0, 10)
5600 00:43:55.970298 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5601 00:43:55.973337 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5602 00:43:55.977011 Pre-setting of DQS Precalculation
5603 00:43:55.983304 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5604 00:43:55.983398 ==
5605 00:43:55.986575 Dram Type= 6, Freq= 0, CH_1, rank 0
5606 00:43:55.989819 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5607 00:43:55.989964 ==
5608 00:43:55.996224 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5609 00:43:56.002887 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5610 00:43:56.006298 [CA 0] Center 36 (6~67) winsize 62
5611 00:43:56.009389 [CA 1] Center 36 (6~67) winsize 62
5612 00:43:56.012880 [CA 2] Center 34 (4~65) winsize 62
5613 00:43:56.016412 [CA 3] Center 33 (3~64) winsize 62
5614 00:43:56.019395 [CA 4] Center 34 (4~64) winsize 61
5615 00:43:56.022861 [CA 5] Center 33 (3~64) winsize 62
5616 00:43:56.023100
5617 00:43:56.026153 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5618 00:43:56.026483
5619 00:43:56.029795 [CATrainingPosCal] consider 1 rank data
5620 00:43:56.032839 u2DelayCellTimex100 = 270/100 ps
5621 00:43:56.036365 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5622 00:43:56.039465 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5623 00:43:56.042874 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5624 00:43:56.046064 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5625 00:43:56.049351 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5626 00:43:56.052567 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5627 00:43:56.055958
5628 00:43:56.059011 CA PerBit enable=1, Macro0, CA PI delay=33
5629 00:43:56.059427
5630 00:43:56.062765 [CBTSetCACLKResult] CA Dly = 33
5631 00:43:56.063176 CS Dly: 6 (0~37)
5632 00:43:56.063520 ==
5633 00:43:56.066046 Dram Type= 6, Freq= 0, CH_1, rank 1
5634 00:43:56.069177 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5635 00:43:56.069594 ==
5636 00:43:56.076149 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5637 00:43:56.082052 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5638 00:43:56.085722 [CA 0] Center 36 (6~67) winsize 62
5639 00:43:56.088869 [CA 1] Center 36 (6~67) winsize 62
5640 00:43:56.092154 [CA 2] Center 34 (3~65) winsize 63
5641 00:43:56.095423 [CA 3] Center 33 (3~64) winsize 62
5642 00:43:56.098730 [CA 4] Center 34 (3~65) winsize 63
5643 00:43:56.101886 [CA 5] Center 33 (3~64) winsize 62
5644 00:43:56.102428
5645 00:43:56.105425 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5646 00:43:56.105855
5647 00:43:56.108309 [CATrainingPosCal] consider 2 rank data
5648 00:43:56.111915 u2DelayCellTimex100 = 270/100 ps
5649 00:43:56.115009 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5650 00:43:56.118617 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5651 00:43:56.121605 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5652 00:43:56.128318 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5653 00:43:56.131779 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5654 00:43:56.134759 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5655 00:43:56.135175
5656 00:43:56.138089 CA PerBit enable=1, Macro0, CA PI delay=33
5657 00:43:56.138543
5658 00:43:56.141720 [CBTSetCACLKResult] CA Dly = 33
5659 00:43:56.142136 CS Dly: 7 (0~39)
5660 00:43:56.142523
5661 00:43:56.144780 ----->DramcWriteLeveling(PI) begin...
5662 00:43:56.147985 ==
5663 00:43:56.151452 Dram Type= 6, Freq= 0, CH_1, rank 0
5664 00:43:56.155034 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5665 00:43:56.155455 ==
5666 00:43:56.158285 Write leveling (Byte 0): 26 => 26
5667 00:43:56.161472 Write leveling (Byte 1): 27 => 27
5668 00:43:56.164502 DramcWriteLeveling(PI) end<-----
5669 00:43:56.164914
5670 00:43:56.165240 ==
5671 00:43:56.167809 Dram Type= 6, Freq= 0, CH_1, rank 0
5672 00:43:56.170940 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5673 00:43:56.171376 ==
5674 00:43:56.174446 [Gating] SW mode calibration
5675 00:43:56.181119 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5676 00:43:56.187422 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5677 00:43:56.190785 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5678 00:43:56.194140 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5679 00:43:56.201118 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5680 00:43:56.204215 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5681 00:43:56.207626 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5682 00:43:56.214033 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5683 00:43:56.217617 0 14 24 | B1->B0 | 3434 3232 | 1 1 | (1 0) (1 0)
5684 00:43:56.220432 0 14 28 | B1->B0 | 2e2e 2727 | 0 0 | (0 1) (1 1)
5685 00:43:56.226920 0 15 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5686 00:43:56.230716 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5687 00:43:56.233693 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5688 00:43:56.240002 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5689 00:43:56.243392 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5690 00:43:56.246951 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5691 00:43:56.253313 0 15 24 | B1->B0 | 2323 2626 | 0 1 | (0 0) (0 0)
5692 00:43:56.256521 0 15 28 | B1->B0 | 3939 4444 | 0 0 | (0 0) (0 0)
5693 00:43:56.260124 1 0 0 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
5694 00:43:56.266467 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5695 00:43:56.269515 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5696 00:43:56.273237 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5697 00:43:56.279686 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5698 00:43:56.282854 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5699 00:43:56.286264 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5700 00:43:56.292436 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5701 00:43:56.296236 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5702 00:43:56.299436 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5703 00:43:56.305793 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5704 00:43:56.308989 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5705 00:43:56.312829 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5706 00:43:56.319175 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5707 00:43:56.322670 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5708 00:43:56.325787 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5709 00:43:56.332517 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5710 00:43:56.335475 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5711 00:43:56.338680 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5712 00:43:56.345176 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5713 00:43:56.348562 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5714 00:43:56.352086 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5715 00:43:56.358873 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5716 00:43:56.362212 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5717 00:43:56.365259 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5718 00:43:56.368696 Total UI for P1: 0, mck2ui 16
5719 00:43:56.371685 best dqsien dly found for B0: ( 1, 2, 28)
5720 00:43:56.378521 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5721 00:43:56.378940 Total UI for P1: 0, mck2ui 16
5722 00:43:56.385360 best dqsien dly found for B1: ( 1, 2, 30)
5723 00:43:56.388260 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5724 00:43:56.391544 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5725 00:43:56.391958
5726 00:43:56.395079 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5727 00:43:56.398489 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5728 00:43:56.401583 [Gating] SW calibration Done
5729 00:43:56.402034 ==
5730 00:43:56.404730 Dram Type= 6, Freq= 0, CH_1, rank 0
5731 00:43:56.408392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5732 00:43:56.408811 ==
5733 00:43:56.411914 RX Vref Scan: 0
5734 00:43:56.412327
5735 00:43:56.412655 RX Vref 0 -> 0, step: 1
5736 00:43:56.412960
5737 00:43:56.415095 RX Delay -80 -> 252, step: 8
5738 00:43:56.421489 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5739 00:43:56.424851 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5740 00:43:56.427839 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5741 00:43:56.431029 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5742 00:43:56.434715 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5743 00:43:56.438469 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5744 00:43:56.444315 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5745 00:43:56.447550 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5746 00:43:56.451193 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5747 00:43:56.454420 iDelay=208, Bit 9, Center 83 (-16 ~ 183) 200
5748 00:43:56.457771 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5749 00:43:56.463932 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5750 00:43:56.467264 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5751 00:43:56.470986 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5752 00:43:56.473911 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5753 00:43:56.477537 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5754 00:43:56.477617 ==
5755 00:43:56.480581 Dram Type= 6, Freq= 0, CH_1, rank 0
5756 00:43:56.487185 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5757 00:43:56.487267 ==
5758 00:43:56.487331 DQS Delay:
5759 00:43:56.487390 DQS0 = 0, DQS1 = 0
5760 00:43:56.490321 DQM Delay:
5761 00:43:56.490400 DQM0 = 100, DQM1 = 91
5762 00:43:56.493707 DQ Delay:
5763 00:43:56.496955 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =95
5764 00:43:56.500429 DQ4 =95, DQ5 =111, DQ6 =111, DQ7 =95
5765 00:43:56.503522 DQ8 =79, DQ9 =83, DQ10 =91, DQ11 =79
5766 00:43:56.507329 DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =99
5767 00:43:56.507430
5768 00:43:56.507520
5769 00:43:56.507606 ==
5770 00:43:56.510306 Dram Type= 6, Freq= 0, CH_1, rank 0
5771 00:43:56.513890 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5772 00:43:56.513986 ==
5773 00:43:56.514074
5774 00:43:56.514168
5775 00:43:56.516871 TX Vref Scan disable
5776 00:43:56.516964 == TX Byte 0 ==
5777 00:43:56.523679 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5778 00:43:56.526551 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5779 00:43:56.530201 == TX Byte 1 ==
5780 00:43:56.533041 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5781 00:43:56.536633 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5782 00:43:56.536713 ==
5783 00:43:56.539760 Dram Type= 6, Freq= 0, CH_1, rank 0
5784 00:43:56.543378 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5785 00:43:56.546527 ==
5786 00:43:56.546608
5787 00:43:56.546670
5788 00:43:56.546729 TX Vref Scan disable
5789 00:43:56.550275 == TX Byte 0 ==
5790 00:43:56.553332 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5791 00:43:56.559864 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5792 00:43:56.559946 == TX Byte 1 ==
5793 00:43:56.563567 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5794 00:43:56.569526 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5795 00:43:56.569608
5796 00:43:56.569676 [DATLAT]
5797 00:43:56.569746 Freq=933, CH1 RK0
5798 00:43:56.569805
5799 00:43:56.573148 DATLAT Default: 0xd
5800 00:43:56.573229 0, 0xFFFF, sum = 0
5801 00:43:56.576311 1, 0xFFFF, sum = 0
5802 00:43:56.579756 2, 0xFFFF, sum = 0
5803 00:43:56.579850 3, 0xFFFF, sum = 0
5804 00:43:56.582950 4, 0xFFFF, sum = 0
5805 00:43:56.583043 5, 0xFFFF, sum = 0
5806 00:43:56.586874 6, 0xFFFF, sum = 0
5807 00:43:56.586975 7, 0xFFFF, sum = 0
5808 00:43:56.589607 8, 0xFFFF, sum = 0
5809 00:43:56.589718 9, 0xFFFF, sum = 0
5810 00:43:56.592931 10, 0x0, sum = 1
5811 00:43:56.593042 11, 0x0, sum = 2
5812 00:43:56.596723 12, 0x0, sum = 3
5813 00:43:56.596845 13, 0x0, sum = 4
5814 00:43:56.596940 best_step = 11
5815 00:43:56.599453
5816 00:43:56.599585 ==
5817 00:43:56.603176 Dram Type= 6, Freq= 0, CH_1, rank 0
5818 00:43:56.606498 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5819 00:43:56.606649 ==
5820 00:43:56.606821 RX Vref Scan: 1
5821 00:43:56.606936
5822 00:43:56.609609 RX Vref 0 -> 0, step: 1
5823 00:43:56.609781
5824 00:43:56.612656 RX Delay -61 -> 252, step: 4
5825 00:43:56.612829
5826 00:43:56.616106 Set Vref, RX VrefLevel [Byte0]: 49
5827 00:43:56.619410 [Byte1]: 51
5828 00:43:56.619723
5829 00:43:56.623163 Final RX Vref Byte 0 = 49 to rank0
5830 00:43:56.625961 Final RX Vref Byte 1 = 51 to rank0
5831 00:43:56.629468 Final RX Vref Byte 0 = 49 to rank1
5832 00:43:56.633037 Final RX Vref Byte 1 = 51 to rank1==
5833 00:43:56.636312 Dram Type= 6, Freq= 0, CH_1, rank 0
5834 00:43:56.642521 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5835 00:43:56.642971 ==
5836 00:43:56.643325 DQS Delay:
5837 00:43:56.643775 DQS0 = 0, DQS1 = 0
5838 00:43:56.646056 DQM Delay:
5839 00:43:56.646546 DQM0 = 100, DQM1 = 93
5840 00:43:56.649285 DQ Delay:
5841 00:43:56.652892 DQ0 =106, DQ1 =94, DQ2 =92, DQ3 =98
5842 00:43:56.656030 DQ4 =98, DQ5 =110, DQ6 =108, DQ7 =98
5843 00:43:56.659334 DQ8 =80, DQ9 =84, DQ10 =94, DQ11 =82
5844 00:43:56.662964 DQ12 =102, DQ13 =98, DQ14 =102, DQ15 =102
5845 00:43:56.663379
5846 00:43:56.663703
5847 00:43:56.669364 [DQSOSCAuto] RK0, (LSB)MR18= 0x1b0b, (MSB)MR19= 0x505, tDQSOscB0 = 418 ps tDQSOscB1 = 413 ps
5848 00:43:56.672289 CH1 RK0: MR19=505, MR18=1B0B
5849 00:43:56.679240 CH1_RK0: MR19=0x505, MR18=0x1B0B, DQSOSC=413, MR23=63, INC=63, DEC=42
5850 00:43:56.679661
5851 00:43:56.682049 ----->DramcWriteLeveling(PI) begin...
5852 00:43:56.682531 ==
5853 00:43:56.685310 Dram Type= 6, Freq= 0, CH_1, rank 1
5854 00:43:56.688670 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5855 00:43:56.689092 ==
5856 00:43:56.692170 Write leveling (Byte 0): 26 => 26
5857 00:43:56.695328 Write leveling (Byte 1): 29 => 29
5858 00:43:56.698570 DramcWriteLeveling(PI) end<-----
5859 00:43:56.698984
5860 00:43:56.699312 ==
5861 00:43:56.701991 Dram Type= 6, Freq= 0, CH_1, rank 1
5862 00:43:56.708642 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5863 00:43:56.709064 ==
5864 00:43:56.709394 [Gating] SW mode calibration
5865 00:43:56.718367 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5866 00:43:56.721735 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5867 00:43:56.728182 0 14 0 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
5868 00:43:56.731761 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5869 00:43:56.734798 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5870 00:43:56.741456 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5871 00:43:56.745007 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5872 00:43:56.747912 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5873 00:43:56.754760 0 14 24 | B1->B0 | 3232 3434 | 1 0 | (1 1) (0 0)
5874 00:43:56.758016 0 14 28 | B1->B0 | 2c2c 3030 | 0 0 | (1 0) (1 0)
5875 00:43:56.761207 0 15 0 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5876 00:43:56.767995 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5877 00:43:56.771103 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5878 00:43:56.774437 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5879 00:43:56.780863 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5880 00:43:56.784494 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5881 00:43:56.787251 0 15 24 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
5882 00:43:56.794338 0 15 28 | B1->B0 | 3b3b 3535 | 0 1 | (0 0) (0 0)
5883 00:43:56.797358 1 0 0 | B1->B0 | 4646 4141 | 0 1 | (0 0) (0 0)
5884 00:43:56.800164 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5885 00:43:56.807216 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5886 00:43:56.810377 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5887 00:43:56.813522 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5888 00:43:56.820262 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5889 00:43:56.823569 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5890 00:43:56.826424 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5891 00:43:56.833145 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5892 00:43:56.836406 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5893 00:43:56.839757 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5894 00:43:56.846516 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5895 00:43:56.849849 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5896 00:43:56.852777 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5897 00:43:56.859670 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5898 00:43:56.862860 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5899 00:43:56.866043 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5900 00:43:56.873073 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5901 00:43:56.876031 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5902 00:43:56.879721 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5903 00:43:56.886300 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5904 00:43:56.889378 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5905 00:43:56.892640 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5906 00:43:56.899221 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5907 00:43:56.899303 Total UI for P1: 0, mck2ui 16
5908 00:43:56.906148 best dqsien dly found for B0: ( 1, 2, 26)
5909 00:43:56.906256 Total UI for P1: 0, mck2ui 16
5910 00:43:56.912245 best dqsien dly found for B1: ( 1, 2, 26)
5911 00:43:56.915825 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5912 00:43:56.918985 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5913 00:43:56.919067
5914 00:43:56.922281 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5915 00:43:56.925375 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5916 00:43:56.928764 [Gating] SW calibration Done
5917 00:43:56.928845 ==
5918 00:43:56.931976 Dram Type= 6, Freq= 0, CH_1, rank 1
5919 00:43:56.935441 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5920 00:43:56.935523 ==
5921 00:43:56.938945 RX Vref Scan: 0
5922 00:43:56.939026
5923 00:43:56.939089 RX Vref 0 -> 0, step: 1
5924 00:43:56.939149
5925 00:43:56.941857 RX Delay -80 -> 252, step: 8
5926 00:43:56.948425 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5927 00:43:56.951799 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5928 00:43:56.955267 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5929 00:43:56.958566 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5930 00:43:56.961501 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5931 00:43:56.964732 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5932 00:43:56.971733 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5933 00:43:56.975403 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5934 00:43:56.978372 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5935 00:43:56.981868 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5936 00:43:56.984611 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5937 00:43:56.991192 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5938 00:43:56.994600 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5939 00:43:56.998295 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5940 00:43:57.001502 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5941 00:43:57.005096 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5942 00:43:57.005205 ==
5943 00:43:57.007778 Dram Type= 6, Freq= 0, CH_1, rank 1
5944 00:43:57.014535 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5945 00:43:57.014623 ==
5946 00:43:57.014688 DQS Delay:
5947 00:43:57.017702 DQS0 = 0, DQS1 = 0
5948 00:43:57.017782 DQM Delay:
5949 00:43:57.017846 DQM0 = 99, DQM1 = 89
5950 00:43:57.020823 DQ Delay:
5951 00:43:57.024538 DQ0 =103, DQ1 =95, DQ2 =87, DQ3 =95
5952 00:43:57.027431 DQ4 =95, DQ5 =111, DQ6 =111, DQ7 =95
5953 00:43:57.031140 DQ8 =75, DQ9 =79, DQ10 =91, DQ11 =79
5954 00:43:57.034401 DQ12 =99, DQ13 =99, DQ14 =95, DQ15 =99
5955 00:43:57.034492
5956 00:43:57.034569
5957 00:43:57.034641 ==
5958 00:43:57.037824 Dram Type= 6, Freq= 0, CH_1, rank 1
5959 00:43:57.040989 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5960 00:43:57.041083 ==
5961 00:43:57.041162
5962 00:43:57.041239
5963 00:43:57.044098 TX Vref Scan disable
5964 00:43:57.047731 == TX Byte 0 ==
5965 00:43:57.050735 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5966 00:43:57.054301 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5967 00:43:57.057244 == TX Byte 1 ==
5968 00:43:57.061146 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5969 00:43:57.064152 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5970 00:43:57.064342 ==
5971 00:43:57.067240 Dram Type= 6, Freq= 0, CH_1, rank 1
5972 00:43:57.070712 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5973 00:43:57.074137 ==
5974 00:43:57.074448
5975 00:43:57.074680
5976 00:43:57.074898 TX Vref Scan disable
5977 00:43:57.078035 == TX Byte 0 ==
5978 00:43:57.080919 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5979 00:43:57.087754 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5980 00:43:57.088320 == TX Byte 1 ==
5981 00:43:57.090799 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5982 00:43:57.097345 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5983 00:43:57.097765
5984 00:43:57.098092 [DATLAT]
5985 00:43:57.098431 Freq=933, CH1 RK1
5986 00:43:57.098726
5987 00:43:57.100863 DATLAT Default: 0xb
5988 00:43:57.104072 0, 0xFFFF, sum = 0
5989 00:43:57.104499 1, 0xFFFF, sum = 0
5990 00:43:57.107181 2, 0xFFFF, sum = 0
5991 00:43:57.107763 3, 0xFFFF, sum = 0
5992 00:43:57.110582 4, 0xFFFF, sum = 0
5993 00:43:57.111007 5, 0xFFFF, sum = 0
5994 00:43:57.113907 6, 0xFFFF, sum = 0
5995 00:43:57.114409 7, 0xFFFF, sum = 0
5996 00:43:57.116924 8, 0xFFFF, sum = 0
5997 00:43:57.117348 9, 0xFFFF, sum = 0
5998 00:43:57.120174 10, 0x0, sum = 1
5999 00:43:57.120597 11, 0x0, sum = 2
6000 00:43:57.123793 12, 0x0, sum = 3
6001 00:43:57.124436 13, 0x0, sum = 4
6002 00:43:57.127318 best_step = 11
6003 00:43:57.127833
6004 00:43:57.128340 ==
6005 00:43:57.130149 Dram Type= 6, Freq= 0, CH_1, rank 1
6006 00:43:57.133450 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
6007 00:43:57.133867 ==
6008 00:43:57.134233 RX Vref Scan: 0
6009 00:43:57.137009
6010 00:43:57.137634 RX Vref 0 -> 0, step: 1
6011 00:43:57.138233
6012 00:43:57.140103 RX Delay -69 -> 252, step: 4
6013 00:43:57.146648 iDelay=207, Bit 0, Center 106 (19 ~ 194) 176
6014 00:43:57.150258 iDelay=207, Bit 1, Center 94 (7 ~ 182) 176
6015 00:43:57.153530 iDelay=207, Bit 2, Center 90 (3 ~ 178) 176
6016 00:43:57.156901 iDelay=207, Bit 3, Center 98 (15 ~ 182) 168
6017 00:43:57.160319 iDelay=207, Bit 4, Center 100 (11 ~ 190) 180
6018 00:43:57.166594 iDelay=207, Bit 5, Center 110 (23 ~ 198) 176
6019 00:43:57.169794 iDelay=207, Bit 6, Center 114 (23 ~ 206) 184
6020 00:43:57.173092 iDelay=207, Bit 7, Center 96 (3 ~ 190) 188
6021 00:43:57.176695 iDelay=207, Bit 8, Center 80 (-9 ~ 170) 180
6022 00:43:57.179769 iDelay=207, Bit 9, Center 82 (-9 ~ 174) 184
6023 00:43:57.186283 iDelay=207, Bit 10, Center 90 (-1 ~ 182) 184
6024 00:43:57.189458 iDelay=207, Bit 11, Center 82 (-9 ~ 174) 184
6025 00:43:57.192514 iDelay=207, Bit 12, Center 102 (11 ~ 194) 184
6026 00:43:57.196212 iDelay=207, Bit 13, Center 100 (7 ~ 194) 188
6027 00:43:57.199299 iDelay=207, Bit 14, Center 98 (7 ~ 190) 184
6028 00:43:57.206232 iDelay=207, Bit 15, Center 102 (11 ~ 194) 184
6029 00:43:57.206776 ==
6030 00:43:57.209496 Dram Type= 6, Freq= 0, CH_1, rank 1
6031 00:43:57.212687 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
6032 00:43:57.213205 ==
6033 00:43:57.213537 DQS Delay:
6034 00:43:57.215905 DQS0 = 0, DQS1 = 0
6035 00:43:57.216421 DQM Delay:
6036 00:43:57.218962 DQM0 = 101, DQM1 = 92
6037 00:43:57.219371 DQ Delay:
6038 00:43:57.222566 DQ0 =106, DQ1 =94, DQ2 =90, DQ3 =98
6039 00:43:57.225439 DQ4 =100, DQ5 =110, DQ6 =114, DQ7 =96
6040 00:43:57.228854 DQ8 =80, DQ9 =82, DQ10 =90, DQ11 =82
6041 00:43:57.232338 DQ12 =102, DQ13 =100, DQ14 =98, DQ15 =102
6042 00:43:57.232752
6043 00:43:57.233077
6044 00:43:57.242249 [DQSOSCAuto] RK1, (LSB)MR18= 0xa03, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 418 ps
6045 00:43:57.242671 CH1 RK1: MR19=505, MR18=A03
6046 00:43:57.248593 CH1_RK1: MR19=0x505, MR18=0xA03, DQSOSC=418, MR23=63, INC=62, DEC=41
6047 00:43:57.252037 [RxdqsGatingPostProcess] freq 933
6048 00:43:57.258887 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6049 00:43:57.261935 best DQS0 dly(2T, 0.5T) = (0, 10)
6050 00:43:57.265212 best DQS1 dly(2T, 0.5T) = (0, 10)
6051 00:43:57.268561 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6052 00:43:57.271815 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6053 00:43:57.274958 best DQS0 dly(2T, 0.5T) = (0, 10)
6054 00:43:57.278441 best DQS1 dly(2T, 0.5T) = (0, 10)
6055 00:43:57.281808 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6056 00:43:57.284900 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6057 00:43:57.285327 Pre-setting of DQS Precalculation
6058 00:43:57.291755 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6059 00:43:57.298063 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6060 00:43:57.304677 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6061 00:43:57.305233
6062 00:43:57.305567
6063 00:43:57.308120 [Calibration Summary] 1866 Mbps
6064 00:43:57.311512 CH 0, Rank 0
6065 00:43:57.312081 SW Impedance : PASS
6066 00:43:57.314476 DUTY Scan : NO K
6067 00:43:57.317804 ZQ Calibration : PASS
6068 00:43:57.318377 Jitter Meter : NO K
6069 00:43:57.321006 CBT Training : PASS
6070 00:43:57.324603 Write leveling : PASS
6071 00:43:57.325032 RX DQS gating : PASS
6072 00:43:57.327653 RX DQ/DQS(RDDQC) : PASS
6073 00:43:57.330977 TX DQ/DQS : PASS
6074 00:43:57.331390 RX DATLAT : PASS
6075 00:43:57.334434 RX DQ/DQS(Engine): PASS
6076 00:43:57.337404 TX OE : NO K
6077 00:43:57.337961 All Pass.
6078 00:43:57.338409
6079 00:43:57.338744 CH 0, Rank 1
6080 00:43:57.340712 SW Impedance : PASS
6081 00:43:57.343871 DUTY Scan : NO K
6082 00:43:57.344404 ZQ Calibration : PASS
6083 00:43:57.347313 Jitter Meter : NO K
6084 00:43:57.351083 CBT Training : PASS
6085 00:43:57.351512 Write leveling : PASS
6086 00:43:57.353973 RX DQS gating : PASS
6087 00:43:57.357407 RX DQ/DQS(RDDQC) : PASS
6088 00:43:57.357970 TX DQ/DQS : PASS
6089 00:43:57.360553 RX DATLAT : PASS
6090 00:43:57.360971 RX DQ/DQS(Engine): PASS
6091 00:43:57.364172 TX OE : NO K
6092 00:43:57.364583 All Pass.
6093 00:43:57.364903
6094 00:43:57.367686 CH 1, Rank 0
6095 00:43:57.368127 SW Impedance : PASS
6096 00:43:57.370420 DUTY Scan : NO K
6097 00:43:57.373632 ZQ Calibration : PASS
6098 00:43:57.374063 Jitter Meter : NO K
6099 00:43:57.377048 CBT Training : PASS
6100 00:43:57.380178 Write leveling : PASS
6101 00:43:57.380722 RX DQS gating : PASS
6102 00:43:57.384347 RX DQ/DQS(RDDQC) : PASS
6103 00:43:57.387098 TX DQ/DQS : PASS
6104 00:43:57.387512 RX DATLAT : PASS
6105 00:43:57.390542 RX DQ/DQS(Engine): PASS
6106 00:43:57.393227 TX OE : NO K
6107 00:43:57.393642 All Pass.
6108 00:43:57.393967
6109 00:43:57.394311 CH 1, Rank 1
6110 00:43:57.396782 SW Impedance : PASS
6111 00:43:57.400082 DUTY Scan : NO K
6112 00:43:57.400604 ZQ Calibration : PASS
6113 00:43:57.403535 Jitter Meter : NO K
6114 00:43:57.406844 CBT Training : PASS
6115 00:43:57.407257 Write leveling : PASS
6116 00:43:57.410442 RX DQS gating : PASS
6117 00:43:57.413322 RX DQ/DQS(RDDQC) : PASS
6118 00:43:57.413732 TX DQ/DQS : PASS
6119 00:43:57.416891 RX DATLAT : PASS
6120 00:43:57.419800 RX DQ/DQS(Engine): PASS
6121 00:43:57.420212 TX OE : NO K
6122 00:43:57.423069 All Pass.
6123 00:43:57.423480
6124 00:43:57.423807 DramC Write-DBI off
6125 00:43:57.426644 PER_BANK_REFRESH: Hybrid Mode
6126 00:43:57.427057 TX_TRACKING: ON
6127 00:43:57.436240 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6128 00:43:57.439388 [FAST_K] Save calibration result to emmc
6129 00:43:57.442590 dramc_set_vcore_voltage set vcore to 650000
6130 00:43:57.446012 Read voltage for 400, 6
6131 00:43:57.446476 Vio18 = 0
6132 00:43:57.449196 Vcore = 650000
6133 00:43:57.449625 Vdram = 0
6134 00:43:57.449947 Vddq = 0
6135 00:43:57.452807 Vmddr = 0
6136 00:43:57.456079 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6137 00:43:57.462295 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6138 00:43:57.462742 MEM_TYPE=3, freq_sel=20
6139 00:43:57.465809 sv_algorithm_assistance_LP4_800
6140 00:43:57.472454 ============ PULL DRAM RESETB DOWN ============
6141 00:43:57.475863 ========== PULL DRAM RESETB DOWN end =========
6142 00:43:57.478755 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6143 00:43:57.481990 ===================================
6144 00:43:57.485605 LPDDR4 DRAM CONFIGURATION
6145 00:43:57.488448 ===================================
6146 00:43:57.491950 EX_ROW_EN[0] = 0x0
6147 00:43:57.492251 EX_ROW_EN[1] = 0x0
6148 00:43:57.495081 LP4Y_EN = 0x0
6149 00:43:57.495319 WORK_FSP = 0x0
6150 00:43:57.498551 WL = 0x2
6151 00:43:57.498853 RL = 0x2
6152 00:43:57.501770 BL = 0x2
6153 00:43:57.501992 RPST = 0x0
6154 00:43:57.505105 RD_PRE = 0x0
6155 00:43:57.505364 WR_PRE = 0x1
6156 00:43:57.508188 WR_PST = 0x0
6157 00:43:57.508414 DBI_WR = 0x0
6158 00:43:57.511540 DBI_RD = 0x0
6159 00:43:57.511778 OTF = 0x1
6160 00:43:57.514957 ===================================
6161 00:43:57.518061 ===================================
6162 00:43:57.521240 ANA top config
6163 00:43:57.524774 ===================================
6164 00:43:57.528003 DLL_ASYNC_EN = 0
6165 00:43:57.528227 ALL_SLAVE_EN = 1
6166 00:43:57.531327 NEW_RANK_MODE = 1
6167 00:43:57.534841 DLL_IDLE_MODE = 1
6168 00:43:57.538093 LP45_APHY_COMB_EN = 1
6169 00:43:57.541381 TX_ODT_DIS = 1
6170 00:43:57.541606 NEW_8X_MODE = 1
6171 00:43:57.544665 ===================================
6172 00:43:57.548030 ===================================
6173 00:43:57.551052 data_rate = 800
6174 00:43:57.554690 CKR = 1
6175 00:43:57.557845 DQ_P2S_RATIO = 4
6176 00:43:57.560796 ===================================
6177 00:43:57.564185 CA_P2S_RATIO = 4
6178 00:43:57.567547 DQ_CA_OPEN = 0
6179 00:43:57.567772 DQ_SEMI_OPEN = 1
6180 00:43:57.570889 CA_SEMI_OPEN = 1
6181 00:43:57.574211 CA_FULL_RATE = 0
6182 00:43:57.577178 DQ_CKDIV4_EN = 0
6183 00:43:57.580929 CA_CKDIV4_EN = 1
6184 00:43:57.584042 CA_PREDIV_EN = 0
6185 00:43:57.584264 PH8_DLY = 0
6186 00:43:57.587896 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6187 00:43:57.590905 DQ_AAMCK_DIV = 0
6188 00:43:57.593775 CA_AAMCK_DIV = 0
6189 00:43:57.597324 CA_ADMCK_DIV = 4
6190 00:43:57.601090 DQ_TRACK_CA_EN = 0
6191 00:43:57.604148 CA_PICK = 800
6192 00:43:57.604644 CA_MCKIO = 400
6193 00:43:57.607267 MCKIO_SEMI = 400
6194 00:43:57.610745 PLL_FREQ = 3016
6195 00:43:57.613972 DQ_UI_PI_RATIO = 32
6196 00:43:57.617213 CA_UI_PI_RATIO = 32
6197 00:43:57.620556 ===================================
6198 00:43:57.624033 ===================================
6199 00:43:57.627258 memory_type:LPDDR4
6200 00:43:57.627687 GP_NUM : 10
6201 00:43:57.630802 SRAM_EN : 1
6202 00:43:57.631216 MD32_EN : 0
6203 00:43:57.634083 ===================================
6204 00:43:57.637224 [ANA_INIT] >>>>>>>>>>>>>>
6205 00:43:57.640851 <<<<<< [CONFIGURE PHASE]: ANA_TX
6206 00:43:57.643789 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6207 00:43:57.647471 ===================================
6208 00:43:57.650225 data_rate = 800,PCW = 0X7400
6209 00:43:57.653626 ===================================
6210 00:43:57.657063 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6211 00:43:57.663905 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6212 00:43:57.673431 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6213 00:43:57.680588 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6214 00:43:57.683876 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6215 00:43:57.686921 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6216 00:43:57.687341 [ANA_INIT] flow start
6217 00:43:57.690081 [ANA_INIT] PLL >>>>>>>>
6218 00:43:57.693263 [ANA_INIT] PLL <<<<<<<<
6219 00:43:57.693677 [ANA_INIT] MIDPI >>>>>>>>
6220 00:43:57.696742 [ANA_INIT] MIDPI <<<<<<<<
6221 00:43:57.700208 [ANA_INIT] DLL >>>>>>>>
6222 00:43:57.700729 [ANA_INIT] flow end
6223 00:43:57.706132 ============ LP4 DIFF to SE enter ============
6224 00:43:57.709392 ============ LP4 DIFF to SE exit ============
6225 00:43:57.712852 [ANA_INIT] <<<<<<<<<<<<<
6226 00:43:57.716312 [Flow] Enable top DCM control >>>>>
6227 00:43:57.719559 [Flow] Enable top DCM control <<<<<
6228 00:43:57.719975 Enable DLL master slave shuffle
6229 00:43:57.725975 ==============================================================
6230 00:43:57.729150 Gating Mode config
6231 00:43:57.732332 ==============================================================
6232 00:43:57.735933 Config description:
6233 00:43:57.745850 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6234 00:43:57.752401 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6235 00:43:57.755744 SELPH_MODE 0: By rank 1: By Phase
6236 00:43:57.762073 ==============================================================
6237 00:43:57.765091 GAT_TRACK_EN = 0
6238 00:43:57.768609 RX_GATING_MODE = 2
6239 00:43:57.772078 RX_GATING_TRACK_MODE = 2
6240 00:43:57.775475 SELPH_MODE = 1
6241 00:43:57.778620 PICG_EARLY_EN = 1
6242 00:43:57.779030 VALID_LAT_VALUE = 1
6243 00:43:57.785416 ==============================================================
6244 00:43:57.788601 Enter into Gating configuration >>>>
6245 00:43:57.792120 Exit from Gating configuration <<<<
6246 00:43:57.795344 Enter into DVFS_PRE_config >>>>>
6247 00:43:57.805495 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6248 00:43:57.808533 Exit from DVFS_PRE_config <<<<<
6249 00:43:57.812015 Enter into PICG configuration >>>>
6250 00:43:57.815328 Exit from PICG configuration <<<<
6251 00:43:57.818308 [RX_INPUT] configuration >>>>>
6252 00:43:57.821787 [RX_INPUT] configuration <<<<<
6253 00:43:57.828337 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6254 00:43:57.831419 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6255 00:43:57.838545 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6256 00:43:57.844813 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6257 00:43:57.851597 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6258 00:43:57.857691 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6259 00:43:57.861380 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6260 00:43:57.864570 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6261 00:43:57.868174 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6262 00:43:57.874438 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6263 00:43:57.877836 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6264 00:43:57.881276 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6265 00:43:57.884290 ===================================
6266 00:43:57.887653 LPDDR4 DRAM CONFIGURATION
6267 00:43:57.891133 ===================================
6268 00:43:57.891569 EX_ROW_EN[0] = 0x0
6269 00:43:57.894415 EX_ROW_EN[1] = 0x0
6270 00:43:57.897681 LP4Y_EN = 0x0
6271 00:43:57.898311 WORK_FSP = 0x0
6272 00:43:57.901160 WL = 0x2
6273 00:43:57.901648 RL = 0x2
6274 00:43:57.904622 BL = 0x2
6275 00:43:57.905139 RPST = 0x0
6276 00:43:57.907803 RD_PRE = 0x0
6277 00:43:57.908297 WR_PRE = 0x1
6278 00:43:57.910854 WR_PST = 0x0
6279 00:43:57.911318 DBI_WR = 0x0
6280 00:43:57.914138 DBI_RD = 0x0
6281 00:43:57.914590 OTF = 0x1
6282 00:43:57.917393 ===================================
6283 00:43:57.924168 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6284 00:43:57.927482 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6285 00:43:57.930774 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6286 00:43:57.933744 ===================================
6287 00:43:57.936918 LPDDR4 DRAM CONFIGURATION
6288 00:43:57.940202 ===================================
6289 00:43:57.943727 EX_ROW_EN[0] = 0x10
6290 00:43:57.944143 EX_ROW_EN[1] = 0x0
6291 00:43:57.947003 LP4Y_EN = 0x0
6292 00:43:57.947413 WORK_FSP = 0x0
6293 00:43:57.950227 WL = 0x2
6294 00:43:57.950653 RL = 0x2
6295 00:43:57.953880 BL = 0x2
6296 00:43:57.954408 RPST = 0x0
6297 00:43:57.956789 RD_PRE = 0x0
6298 00:43:57.957212 WR_PRE = 0x1
6299 00:43:57.960279 WR_PST = 0x0
6300 00:43:57.960694 DBI_WR = 0x0
6301 00:43:57.963402 DBI_RD = 0x0
6302 00:43:57.963814 OTF = 0x1
6303 00:43:57.966656 ===================================
6304 00:43:57.973331 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6305 00:43:57.978058 nWR fixed to 30
6306 00:43:57.981634 [ModeRegInit_LP4] CH0 RK0
6307 00:43:57.982050 [ModeRegInit_LP4] CH0 RK1
6308 00:43:57.985023 [ModeRegInit_LP4] CH1 RK0
6309 00:43:57.988120 [ModeRegInit_LP4] CH1 RK1
6310 00:43:57.988572 match AC timing 19
6311 00:43:57.994638 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6312 00:43:57.997954 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6313 00:43:58.001451 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6314 00:43:58.007617 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6315 00:43:58.011157 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6316 00:43:58.011575 ==
6317 00:43:58.014612 Dram Type= 6, Freq= 0, CH_0, rank 0
6318 00:43:58.017481 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6319 00:43:58.017901 ==
6320 00:43:58.024077 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6321 00:43:58.031039 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6322 00:43:58.034674 [CA 0] Center 36 (8~64) winsize 57
6323 00:43:58.037609 [CA 1] Center 36 (8~64) winsize 57
6324 00:43:58.041093 [CA 2] Center 36 (8~64) winsize 57
6325 00:43:58.044045 [CA 3] Center 36 (8~64) winsize 57
6326 00:43:58.047585 [CA 4] Center 36 (8~64) winsize 57
6327 00:43:58.050591 [CA 5] Center 36 (8~64) winsize 57
6328 00:43:58.051004
6329 00:43:58.054087 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6330 00:43:58.054550
6331 00:43:58.057503 [CATrainingPosCal] consider 1 rank data
6332 00:43:58.060423 u2DelayCellTimex100 = 270/100 ps
6333 00:43:58.064202 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6334 00:43:58.067586 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6335 00:43:58.070828 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6336 00:43:58.074014 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6337 00:43:58.077055 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6338 00:43:58.080541 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6339 00:43:58.080959
6340 00:43:58.087331 CA PerBit enable=1, Macro0, CA PI delay=36
6341 00:43:58.087746
6342 00:43:58.088070 [CBTSetCACLKResult] CA Dly = 36
6343 00:43:58.090451 CS Dly: 1 (0~32)
6344 00:43:58.090863 ==
6345 00:43:58.093680 Dram Type= 6, Freq= 0, CH_0, rank 1
6346 00:43:58.096597 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6347 00:43:58.097013 ==
6348 00:43:58.103064 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6349 00:43:58.109882 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6350 00:43:58.113489 [CA 0] Center 36 (8~64) winsize 57
6351 00:43:58.116673 [CA 1] Center 36 (8~64) winsize 57
6352 00:43:58.119980 [CA 2] Center 36 (8~64) winsize 57
6353 00:43:58.123005 [CA 3] Center 36 (8~64) winsize 57
6354 00:43:58.126279 [CA 4] Center 36 (8~64) winsize 57
6355 00:43:58.126694 [CA 5] Center 36 (8~64) winsize 57
6356 00:43:58.129499
6357 00:43:58.132646 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6358 00:43:58.133058
6359 00:43:58.136281 [CATrainingPosCal] consider 2 rank data
6360 00:43:58.139391 u2DelayCellTimex100 = 270/100 ps
6361 00:43:58.142973 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6362 00:43:58.146294 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6363 00:43:58.149421 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6364 00:43:58.152756 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6365 00:43:58.155993 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6366 00:43:58.159402 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6367 00:43:58.159846
6368 00:43:58.162721 CA PerBit enable=1, Macro0, CA PI delay=36
6369 00:43:58.165865
6370 00:43:58.166206 [CBTSetCACLKResult] CA Dly = 36
6371 00:43:58.168791 CS Dly: 1 (0~32)
6372 00:43:58.169012
6373 00:43:58.172403 ----->DramcWriteLeveling(PI) begin...
6374 00:43:58.172629 ==
6375 00:43:58.175598 Dram Type= 6, Freq= 0, CH_0, rank 0
6376 00:43:58.178944 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6377 00:43:58.179166 ==
6378 00:43:58.181961 Write leveling (Byte 0): 40 => 8
6379 00:43:58.185640 Write leveling (Byte 1): 32 => 0
6380 00:43:58.188681 DramcWriteLeveling(PI) end<-----
6381 00:43:58.188976
6382 00:43:58.189238 ==
6383 00:43:58.191660 Dram Type= 6, Freq= 0, CH_0, rank 0
6384 00:43:58.195373 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6385 00:43:58.198892 ==
6386 00:43:58.199150 [Gating] SW mode calibration
6387 00:43:58.205011 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6388 00:43:58.212064 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6389 00:43:58.215355 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6390 00:43:58.221513 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6391 00:43:58.225148 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6392 00:43:58.228426 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6393 00:43:58.234679 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6394 00:43:58.237780 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6395 00:43:58.241083 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6396 00:43:58.247815 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6397 00:43:58.250917 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6398 00:43:58.254481 Total UI for P1: 0, mck2ui 16
6399 00:43:58.257706 best dqsien dly found for B0: ( 0, 14, 24)
6400 00:43:58.261101 Total UI for P1: 0, mck2ui 16
6401 00:43:58.264199 best dqsien dly found for B1: ( 0, 14, 24)
6402 00:43:58.267730 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6403 00:43:58.270819 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6404 00:43:58.270951
6405 00:43:58.273970 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6406 00:43:58.280466 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6407 00:43:58.280552 [Gating] SW calibration Done
6408 00:43:58.280620 ==
6409 00:43:58.284062 Dram Type= 6, Freq= 0, CH_0, rank 0
6410 00:43:58.290731 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6411 00:43:58.290907 ==
6412 00:43:58.291016 RX Vref Scan: 0
6413 00:43:58.291098
6414 00:43:58.293806 RX Vref 0 -> 0, step: 1
6415 00:43:58.293906
6416 00:43:58.296778 RX Delay -410 -> 252, step: 16
6417 00:43:58.300425 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6418 00:43:58.303559 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6419 00:43:58.310374 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6420 00:43:58.313868 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6421 00:43:58.316924 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6422 00:43:58.320651 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6423 00:43:58.327184 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6424 00:43:58.330450 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6425 00:43:58.333760 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6426 00:43:58.337040 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6427 00:43:58.343519 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6428 00:43:58.347337 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6429 00:43:58.350130 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6430 00:43:58.356784 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6431 00:43:58.359994 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6432 00:43:58.363243 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6433 00:43:58.363659 ==
6434 00:43:58.366718 Dram Type= 6, Freq= 0, CH_0, rank 0
6435 00:43:58.369912 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6436 00:43:58.372912 ==
6437 00:43:58.373341 DQS Delay:
6438 00:43:58.373671 DQS0 = 43, DQS1 = 59
6439 00:43:58.376327 DQM Delay:
6440 00:43:58.376741 DQM0 = 9, DQM1 = 11
6441 00:43:58.379989 DQ Delay:
6442 00:43:58.380402 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =0
6443 00:43:58.383152 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6444 00:43:58.386538 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6445 00:43:58.389809 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6446 00:43:58.390259
6447 00:43:58.390595
6448 00:43:58.393054 ==
6449 00:43:58.393468 Dram Type= 6, Freq= 0, CH_0, rank 0
6450 00:43:58.400215 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6451 00:43:58.400718 ==
6452 00:43:58.401048
6453 00:43:58.401353
6454 00:43:58.403349 TX Vref Scan disable
6455 00:43:58.403764 == TX Byte 0 ==
6456 00:43:58.406711 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6457 00:43:58.412828 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6458 00:43:58.413425 == TX Byte 1 ==
6459 00:43:58.415818 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6460 00:43:58.422103 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6461 00:43:58.422224 ==
6462 00:43:58.425293 Dram Type= 6, Freq= 0, CH_0, rank 0
6463 00:43:58.429036 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6464 00:43:58.429145 ==
6465 00:43:58.429247
6466 00:43:58.429355
6467 00:43:58.432021 TX Vref Scan disable
6468 00:43:58.432132 == TX Byte 0 ==
6469 00:43:58.438918 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6470 00:43:58.442010 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6471 00:43:58.442137 == TX Byte 1 ==
6472 00:43:58.445526 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6473 00:43:58.452363 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6474 00:43:58.452526
6475 00:43:58.452671 [DATLAT]
6476 00:43:58.455376 Freq=400, CH0 RK0
6477 00:43:58.455547
6478 00:43:58.455699 DATLAT Default: 0xf
6479 00:43:58.459110 0, 0xFFFF, sum = 0
6480 00:43:58.459235 1, 0xFFFF, sum = 0
6481 00:43:58.461998 2, 0xFFFF, sum = 0
6482 00:43:58.462190 3, 0xFFFF, sum = 0
6483 00:43:58.465452 4, 0xFFFF, sum = 0
6484 00:43:58.465626 5, 0xFFFF, sum = 0
6485 00:43:58.468519 6, 0xFFFF, sum = 0
6486 00:43:58.468694 7, 0xFFFF, sum = 0
6487 00:43:58.471893 8, 0xFFFF, sum = 0
6488 00:43:58.472096 9, 0xFFFF, sum = 0
6489 00:43:58.475755 10, 0xFFFF, sum = 0
6490 00:43:58.475998 11, 0xFFFF, sum = 0
6491 00:43:58.478733 12, 0xFFFF, sum = 0
6492 00:43:58.482135 13, 0x0, sum = 1
6493 00:43:58.482481 14, 0x0, sum = 2
6494 00:43:58.482796 15, 0x0, sum = 3
6495 00:43:58.485220 16, 0x0, sum = 4
6496 00:43:58.485609 best_step = 14
6497 00:43:58.485910
6498 00:43:58.486228 ==
6499 00:43:58.488692 Dram Type= 6, Freq= 0, CH_0, rank 0
6500 00:43:58.495486 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6501 00:43:58.495906 ==
6502 00:43:58.496234 RX Vref Scan: 1
6503 00:43:58.496542
6504 00:43:58.498546 RX Vref 0 -> 0, step: 1
6505 00:43:58.498961
6506 00:43:58.501742 RX Delay -359 -> 252, step: 8
6507 00:43:58.502183
6508 00:43:58.505153 Set Vref, RX VrefLevel [Byte0]: 60
6509 00:43:58.508489 [Byte1]: 55
6510 00:43:58.512094
6511 00:43:58.512508 Final RX Vref Byte 0 = 60 to rank0
6512 00:43:58.515339 Final RX Vref Byte 1 = 55 to rank0
6513 00:43:58.519445 Final RX Vref Byte 0 = 60 to rank1
6514 00:43:58.522137 Final RX Vref Byte 1 = 55 to rank1==
6515 00:43:58.525780 Dram Type= 6, Freq= 0, CH_0, rank 0
6516 00:43:58.531988 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6517 00:43:58.532492 ==
6518 00:43:58.532828 DQS Delay:
6519 00:43:58.535138 DQS0 = 48, DQS1 = 60
6520 00:43:58.535558 DQM Delay:
6521 00:43:58.535887 DQM0 = 11, DQM1 = 11
6522 00:43:58.538551 DQ Delay:
6523 00:43:58.541603 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8
6524 00:43:58.544935 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6525 00:43:58.545504 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6526 00:43:58.551466 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6527 00:43:58.551885
6528 00:43:58.552215
6529 00:43:58.558103 [DQSOSCAuto] RK0, (LSB)MR18= 0xba7d, (MSB)MR19= 0xc0c, tDQSOscB0 = 394 ps tDQSOscB1 = 386 ps
6530 00:43:58.561788 CH0 RK0: MR19=C0C, MR18=BA7D
6531 00:43:58.567954 CH0_RK0: MR19=0xC0C, MR18=0xBA7D, DQSOSC=386, MR23=63, INC=396, DEC=264
6532 00:43:58.568500 ==
6533 00:43:58.571284 Dram Type= 6, Freq= 0, CH_0, rank 1
6534 00:43:58.574342 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6535 00:43:58.574807 ==
6536 00:43:58.578310 [Gating] SW mode calibration
6537 00:43:58.584593 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6538 00:43:58.591081 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6539 00:43:58.594194 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6540 00:43:58.597570 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6541 00:43:58.604088 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6542 00:43:58.607376 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6543 00:43:58.610790 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6544 00:43:58.617286 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6545 00:43:58.620708 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6546 00:43:58.623863 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6547 00:43:58.630866 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6548 00:43:58.633863 Total UI for P1: 0, mck2ui 16
6549 00:43:58.636870 best dqsien dly found for B0: ( 0, 14, 24)
6550 00:43:58.640505 Total UI for P1: 0, mck2ui 16
6551 00:43:58.643741 best dqsien dly found for B1: ( 0, 14, 24)
6552 00:43:58.646918 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6553 00:43:58.650218 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6554 00:43:58.650861
6555 00:43:58.653789 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6556 00:43:58.657005 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6557 00:43:58.660078 [Gating] SW calibration Done
6558 00:43:58.660535 ==
6559 00:43:58.663590 Dram Type= 6, Freq= 0, CH_0, rank 1
6560 00:43:58.667182 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6561 00:43:58.667601 ==
6562 00:43:58.670139 RX Vref Scan: 0
6563 00:43:58.670589
6564 00:43:58.673630 RX Vref 0 -> 0, step: 1
6565 00:43:58.674044
6566 00:43:58.676589 RX Delay -410 -> 252, step: 16
6567 00:43:58.679975 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6568 00:43:58.683536 iDelay=230, Bit 1, Center -27 (-282 ~ 229) 512
6569 00:43:58.686810 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6570 00:43:58.693468 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6571 00:43:58.696623 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6572 00:43:58.699647 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6573 00:43:58.703491 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6574 00:43:58.709465 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6575 00:43:58.713008 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6576 00:43:58.715875 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6577 00:43:58.719580 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6578 00:43:58.725955 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6579 00:43:58.729426 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6580 00:43:58.732443 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6581 00:43:58.739295 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6582 00:43:58.742220 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6583 00:43:58.742647 ==
6584 00:43:58.745804 Dram Type= 6, Freq= 0, CH_0, rank 1
6585 00:43:58.748991 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6586 00:43:58.749411 ==
6587 00:43:58.751911 DQS Delay:
6588 00:43:58.752321 DQS0 = 43, DQS1 = 51
6589 00:43:58.755662 DQM Delay:
6590 00:43:58.756072 DQM0 = 10, DQM1 = 9
6591 00:43:58.756391 DQ Delay:
6592 00:43:58.758884 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6593 00:43:58.761921 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6594 00:43:58.765247 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6595 00:43:58.768558 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6596 00:43:58.769004
6597 00:43:58.769515
6598 00:43:58.769930 ==
6599 00:43:58.772039 Dram Type= 6, Freq= 0, CH_0, rank 1
6600 00:43:58.775462 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6601 00:43:58.778385 ==
6602 00:43:58.778808
6603 00:43:58.779266
6604 00:43:58.779756 TX Vref Scan disable
6605 00:43:58.782219 == TX Byte 0 ==
6606 00:43:58.785417 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6607 00:43:58.788696 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6608 00:43:58.791510 == TX Byte 1 ==
6609 00:43:58.794969 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6610 00:43:58.798316 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6611 00:43:58.798787 ==
6612 00:43:58.801855 Dram Type= 6, Freq= 0, CH_0, rank 1
6613 00:43:58.808376 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6614 00:43:58.808955 ==
6615 00:43:58.809449
6616 00:43:58.809963
6617 00:43:58.810442 TX Vref Scan disable
6618 00:43:58.811482 == TX Byte 0 ==
6619 00:43:58.814586 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6620 00:43:58.818474 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6621 00:43:58.821325 == TX Byte 1 ==
6622 00:43:58.824710 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6623 00:43:58.827883 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6624 00:43:58.828337
6625 00:43:58.831213 [DATLAT]
6626 00:43:58.831759 Freq=400, CH0 RK1
6627 00:43:58.832190
6628 00:43:58.834376 DATLAT Default: 0xe
6629 00:43:58.834804 0, 0xFFFF, sum = 0
6630 00:43:58.837888 1, 0xFFFF, sum = 0
6631 00:43:58.838354 2, 0xFFFF, sum = 0
6632 00:43:58.841159 3, 0xFFFF, sum = 0
6633 00:43:58.841733 4, 0xFFFF, sum = 0
6634 00:43:58.844544 5, 0xFFFF, sum = 0
6635 00:43:58.844976 6, 0xFFFF, sum = 0
6636 00:43:58.847640 7, 0xFFFF, sum = 0
6637 00:43:58.851101 8, 0xFFFF, sum = 0
6638 00:43:58.851726 9, 0xFFFF, sum = 0
6639 00:43:58.854231 10, 0xFFFF, sum = 0
6640 00:43:58.854674 11, 0xFFFF, sum = 0
6641 00:43:58.857343 12, 0xFFFF, sum = 0
6642 00:43:58.857758 13, 0x0, sum = 1
6643 00:43:58.861298 14, 0x0, sum = 2
6644 00:43:58.861731 15, 0x0, sum = 3
6645 00:43:58.864331 16, 0x0, sum = 4
6646 00:43:58.864797 best_step = 14
6647 00:43:58.865261
6648 00:43:58.865707 ==
6649 00:43:58.867700 Dram Type= 6, Freq= 0, CH_0, rank 1
6650 00:43:58.870715 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6651 00:43:58.871270 ==
6652 00:43:58.874497 RX Vref Scan: 0
6653 00:43:58.874913
6654 00:43:58.877174 RX Vref 0 -> 0, step: 1
6655 00:43:58.877583
6656 00:43:58.877904 RX Delay -343 -> 252, step: 8
6657 00:43:58.886449 iDelay=217, Bit 0, Center -40 (-279 ~ 200) 480
6658 00:43:58.889766 iDelay=217, Bit 1, Center -36 (-279 ~ 208) 488
6659 00:43:58.892925 iDelay=217, Bit 2, Center -44 (-287 ~ 200) 488
6660 00:43:58.896070 iDelay=217, Bit 3, Center -40 (-287 ~ 208) 496
6661 00:43:58.902758 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6662 00:43:58.905990 iDelay=217, Bit 5, Center -44 (-287 ~ 200) 488
6663 00:43:58.909239 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6664 00:43:58.916359 iDelay=217, Bit 7, Center -28 (-271 ~ 216) 488
6665 00:43:58.919502 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
6666 00:43:58.922588 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6667 00:43:58.926039 iDelay=217, Bit 10, Center -40 (-287 ~ 208) 496
6668 00:43:58.932613 iDelay=217, Bit 11, Center -56 (-303 ~ 192) 496
6669 00:43:58.935670 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6670 00:43:58.939189 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6671 00:43:58.942733 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6672 00:43:58.949132 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6673 00:43:58.949685 ==
6674 00:43:58.952159 Dram Type= 6, Freq= 0, CH_0, rank 1
6675 00:43:58.955590 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6676 00:43:58.956017 ==
6677 00:43:58.956447 DQS Delay:
6678 00:43:58.958950 DQS0 = 44, DQS1 = 60
6679 00:43:58.959371 DQM Delay:
6680 00:43:58.962092 DQM0 = 7, DQM1 = 14
6681 00:43:58.962661 DQ Delay:
6682 00:43:58.965748 DQ0 =4, DQ1 =8, DQ2 =0, DQ3 =4
6683 00:43:58.968675 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6684 00:43:58.972180 DQ8 =4, DQ9 =0, DQ10 =20, DQ11 =4
6685 00:43:58.975347 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =20
6686 00:43:58.975896
6687 00:43:58.976433
6688 00:43:58.981846 [DQSOSCAuto] RK1, (LSB)MR18= 0xb946, (MSB)MR19= 0xc0c, tDQSOscB0 = 401 ps tDQSOscB1 = 386 ps
6689 00:43:58.985346 CH0 RK1: MR19=C0C, MR18=B946
6690 00:43:58.992121 CH0_RK1: MR19=0xC0C, MR18=0xB946, DQSOSC=386, MR23=63, INC=396, DEC=264
6691 00:43:58.994941 [RxdqsGatingPostProcess] freq 400
6692 00:43:59.001832 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6693 00:43:59.004825 best DQS0 dly(2T, 0.5T) = (0, 10)
6694 00:43:59.008248 best DQS1 dly(2T, 0.5T) = (0, 10)
6695 00:43:59.011721 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6696 00:43:59.014789 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6697 00:43:59.015209 best DQS0 dly(2T, 0.5T) = (0, 10)
6698 00:43:59.018046 best DQS1 dly(2T, 0.5T) = (0, 10)
6699 00:43:59.021327 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6700 00:43:59.024629 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6701 00:43:59.027909 Pre-setting of DQS Precalculation
6702 00:43:59.034716 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6703 00:43:59.034945 ==
6704 00:43:59.037724 Dram Type= 6, Freq= 0, CH_1, rank 0
6705 00:43:59.041187 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6706 00:43:59.041371 ==
6707 00:43:59.047612 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6708 00:43:59.054510 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6709 00:43:59.057134 [CA 0] Center 36 (8~64) winsize 57
6710 00:43:59.060612 [CA 1] Center 36 (8~64) winsize 57
6711 00:43:59.060719 [CA 2] Center 36 (8~64) winsize 57
6712 00:43:59.063743 [CA 3] Center 36 (8~64) winsize 57
6713 00:43:59.067285 [CA 4] Center 36 (8~64) winsize 57
6714 00:43:59.070343 [CA 5] Center 36 (8~64) winsize 57
6715 00:43:59.070430
6716 00:43:59.073942 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6717 00:43:59.077100
6718 00:43:59.080384 [CATrainingPosCal] consider 1 rank data
6719 00:43:59.080502 u2DelayCellTimex100 = 270/100 ps
6720 00:43:59.086783 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6721 00:43:59.090625 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6722 00:43:59.093822 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6723 00:43:59.096902 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6724 00:43:59.100053 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6725 00:43:59.103385 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6726 00:43:59.103514
6727 00:43:59.106466 CA PerBit enable=1, Macro0, CA PI delay=36
6728 00:43:59.106556
6729 00:43:59.109811 [CBTSetCACLKResult] CA Dly = 36
6730 00:43:59.113603 CS Dly: 1 (0~32)
6731 00:43:59.113699 ==
6732 00:43:59.116946 Dram Type= 6, Freq= 0, CH_1, rank 1
6733 00:43:59.120147 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6734 00:43:59.120261 ==
6735 00:43:59.126813 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6736 00:43:59.129995 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6737 00:43:59.133561 [CA 0] Center 36 (8~64) winsize 57
6738 00:43:59.136692 [CA 1] Center 36 (8~64) winsize 57
6739 00:43:59.140090 [CA 2] Center 36 (8~64) winsize 57
6740 00:43:59.143179 [CA 3] Center 36 (8~64) winsize 57
6741 00:43:59.147116 [CA 4] Center 36 (8~64) winsize 57
6742 00:43:59.149891 [CA 5] Center 36 (8~64) winsize 57
6743 00:43:59.150146
6744 00:43:59.153113 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6745 00:43:59.153374
6746 00:43:59.157063 [CATrainingPosCal] consider 2 rank data
6747 00:43:59.160181 u2DelayCellTimex100 = 270/100 ps
6748 00:43:59.163487 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6749 00:43:59.166611 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6750 00:43:59.173271 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6751 00:43:59.176440 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6752 00:43:59.180034 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6753 00:43:59.183221 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6754 00:43:59.183645
6755 00:43:59.186398 CA PerBit enable=1, Macro0, CA PI delay=36
6756 00:43:59.186817
6757 00:43:59.189773 [CBTSetCACLKResult] CA Dly = 36
6758 00:43:59.190282 CS Dly: 1 (0~32)
6759 00:43:59.192973
6760 00:43:59.196655 ----->DramcWriteLeveling(PI) begin...
6761 00:43:59.197079 ==
6762 00:43:59.199887 Dram Type= 6, Freq= 0, CH_1, rank 0
6763 00:43:59.203037 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6764 00:43:59.203456 ==
6765 00:43:59.206377 Write leveling (Byte 0): 40 => 8
6766 00:43:59.210084 Write leveling (Byte 1): 40 => 8
6767 00:43:59.213081 DramcWriteLeveling(PI) end<-----
6768 00:43:59.213546
6769 00:43:59.213879 ==
6770 00:43:59.216667 Dram Type= 6, Freq= 0, CH_1, rank 0
6771 00:43:59.219591 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6772 00:43:59.220011 ==
6773 00:43:59.223253 [Gating] SW mode calibration
6774 00:43:59.229419 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6775 00:43:59.235754 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6776 00:43:59.239412 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6777 00:43:59.242408 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6778 00:43:59.249498 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6779 00:43:59.252246 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6780 00:43:59.256053 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6781 00:43:59.262254 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6782 00:43:59.265568 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6783 00:43:59.269211 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6784 00:43:59.275895 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6785 00:43:59.276316 Total UI for P1: 0, mck2ui 16
6786 00:43:59.282575 best dqsien dly found for B0: ( 0, 14, 24)
6787 00:43:59.282992 Total UI for P1: 0, mck2ui 16
6788 00:43:59.288997 best dqsien dly found for B1: ( 0, 14, 24)
6789 00:43:59.291966 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6790 00:43:59.295262 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6791 00:43:59.295678
6792 00:43:59.298769 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6793 00:43:59.301968 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6794 00:43:59.305156 [Gating] SW calibration Done
6795 00:43:59.305572 ==
6796 00:43:59.308410 Dram Type= 6, Freq= 0, CH_1, rank 0
6797 00:43:59.311644 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6798 00:43:59.312065 ==
6799 00:43:59.315354 RX Vref Scan: 0
6800 00:43:59.315933
6801 00:43:59.316293 RX Vref 0 -> 0, step: 1
6802 00:43:59.316649
6803 00:43:59.318615 RX Delay -410 -> 252, step: 16
6804 00:43:59.324865 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6805 00:43:59.328246 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6806 00:43:59.331628 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6807 00:43:59.334914 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6808 00:43:59.341731 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6809 00:43:59.344887 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6810 00:43:59.348351 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6811 00:43:59.360884 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6812 00:43:59.361781 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6813 00:43:59.362157 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6814 00:43:59.364611 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6815 00:43:59.367996 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6816 00:43:59.374737 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6817 00:43:59.377986 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6818 00:43:59.381309 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6819 00:43:59.387893 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6820 00:43:59.388413 ==
6821 00:43:59.391430 Dram Type= 6, Freq= 0, CH_1, rank 0
6822 00:43:59.394454 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6823 00:43:59.394874 ==
6824 00:43:59.395202 DQS Delay:
6825 00:43:59.397782 DQS0 = 43, DQS1 = 51
6826 00:43:59.398353 DQM Delay:
6827 00:43:59.401147 DQM0 = 12, DQM1 = 14
6828 00:43:59.401559 DQ Delay:
6829 00:43:59.404406 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6830 00:43:59.407653 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6831 00:43:59.410840 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =0
6832 00:43:59.413973 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6833 00:43:59.414414
6834 00:43:59.414741
6835 00:43:59.415093 ==
6836 00:43:59.417380 Dram Type= 6, Freq= 0, CH_1, rank 0
6837 00:43:59.420552 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6838 00:43:59.420971 ==
6839 00:43:59.421300
6840 00:43:59.421604
6841 00:43:59.423883 TX Vref Scan disable
6842 00:43:59.427481 == TX Byte 0 ==
6843 00:43:59.430454 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6844 00:43:59.434032 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6845 00:43:59.437118 == TX Byte 1 ==
6846 00:43:59.440464 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6847 00:43:59.443742 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6848 00:43:59.444154 ==
6849 00:43:59.446844 Dram Type= 6, Freq= 0, CH_1, rank 0
6850 00:43:59.450509 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6851 00:43:59.450927 ==
6852 00:43:59.453382
6853 00:43:59.453849
6854 00:43:59.454219 TX Vref Scan disable
6855 00:43:59.456813 == TX Byte 0 ==
6856 00:43:59.460544 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6857 00:43:59.463331 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6858 00:43:59.466961 == TX Byte 1 ==
6859 00:43:59.470398 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6860 00:43:59.473086 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6861 00:43:59.473500
6862 00:43:59.473839 [DATLAT]
6863 00:43:59.476760 Freq=400, CH1 RK0
6864 00:43:59.477282
6865 00:43:59.480196 DATLAT Default: 0xf
6866 00:43:59.480712 0, 0xFFFF, sum = 0
6867 00:43:59.483327 1, 0xFFFF, sum = 0
6868 00:43:59.483745 2, 0xFFFF, sum = 0
6869 00:43:59.486615 3, 0xFFFF, sum = 0
6870 00:43:59.487037 4, 0xFFFF, sum = 0
6871 00:43:59.489707 5, 0xFFFF, sum = 0
6872 00:43:59.490125 6, 0xFFFF, sum = 0
6873 00:43:59.493335 7, 0xFFFF, sum = 0
6874 00:43:59.493754 8, 0xFFFF, sum = 0
6875 00:43:59.496564 9, 0xFFFF, sum = 0
6876 00:43:59.497055 10, 0xFFFF, sum = 0
6877 00:43:59.499710 11, 0xFFFF, sum = 0
6878 00:43:59.500187 12, 0xFFFF, sum = 0
6879 00:43:59.503350 13, 0x0, sum = 1
6880 00:43:59.503769 14, 0x0, sum = 2
6881 00:43:59.506590 15, 0x0, sum = 3
6882 00:43:59.507053 16, 0x0, sum = 4
6883 00:43:59.509788 best_step = 14
6884 00:43:59.510221
6885 00:43:59.510554 ==
6886 00:43:59.512906 Dram Type= 6, Freq= 0, CH_1, rank 0
6887 00:43:59.516452 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6888 00:43:59.516867 ==
6889 00:43:59.519903 RX Vref Scan: 1
6890 00:43:59.520492
6891 00:43:59.520835 RX Vref 0 -> 0, step: 1
6892 00:43:59.521147
6893 00:43:59.522867 RX Delay -343 -> 252, step: 8
6894 00:43:59.523281
6895 00:43:59.526000 Set Vref, RX VrefLevel [Byte0]: 49
6896 00:43:59.529163 [Byte1]: 51
6897 00:43:59.534272
6898 00:43:59.534804 Final RX Vref Byte 0 = 49 to rank0
6899 00:43:59.537718 Final RX Vref Byte 1 = 51 to rank0
6900 00:43:59.540935 Final RX Vref Byte 0 = 49 to rank1
6901 00:43:59.544245 Final RX Vref Byte 1 = 51 to rank1==
6902 00:43:59.547219 Dram Type= 6, Freq= 0, CH_1, rank 0
6903 00:43:59.554453 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6904 00:43:59.555139 ==
6905 00:43:59.555484 DQS Delay:
6906 00:43:59.557169 DQS0 = 44, DQS1 = 56
6907 00:43:59.557581 DQM Delay:
6908 00:43:59.557906 DQM0 = 7, DQM1 = 11
6909 00:43:59.560815 DQ Delay:
6910 00:43:59.564278 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
6911 00:43:59.564794 DQ4 =4, DQ5 =16, DQ6 =16, DQ7 =4
6912 00:43:59.567013 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6913 00:43:59.570738 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =20
6914 00:43:59.573450
6915 00:43:59.573879
6916 00:43:59.580224 [DQSOSCAuto] RK0, (LSB)MR18= 0x996f, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 390 ps
6917 00:43:59.584322 CH1 RK0: MR19=C0C, MR18=996F
6918 00:43:59.590507 CH1_RK0: MR19=0xC0C, MR18=0x996F, DQSOSC=390, MR23=63, INC=388, DEC=258
6919 00:43:59.591030 ==
6920 00:43:59.593706 Dram Type= 6, Freq= 0, CH_1, rank 1
6921 00:43:59.596653 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6922 00:43:59.597129 ==
6923 00:43:59.600382 [Gating] SW mode calibration
6924 00:43:59.606844 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6925 00:43:59.613255 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6926 00:43:59.616816 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6927 00:43:59.620006 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6928 00:43:59.626491 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6929 00:43:59.629694 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6930 00:43:59.633510 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6931 00:43:59.639809 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6932 00:43:59.642848 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6933 00:43:59.646723 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6934 00:43:59.653037 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6935 00:43:59.653590 Total UI for P1: 0, mck2ui 16
6936 00:43:59.659673 best dqsien dly found for B0: ( 0, 14, 24)
6937 00:43:59.660131 Total UI for P1: 0, mck2ui 16
6938 00:43:59.666299 best dqsien dly found for B1: ( 0, 14, 24)
6939 00:43:59.669705 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6940 00:43:59.673127 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6941 00:43:59.673704
6942 00:43:59.676485 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6943 00:43:59.679438 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6944 00:43:59.682855 [Gating] SW calibration Done
6945 00:43:59.683411 ==
6946 00:43:59.685955 Dram Type= 6, Freq= 0, CH_1, rank 1
6947 00:43:59.689230 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6948 00:43:59.689781 ==
6949 00:43:59.692581 RX Vref Scan: 0
6950 00:43:59.693136
6951 00:43:59.693496 RX Vref 0 -> 0, step: 1
6952 00:43:59.696148
6953 00:43:59.696673 RX Delay -410 -> 252, step: 16
6954 00:43:59.702622 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6955 00:43:59.706057 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6956 00:43:59.709132 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6957 00:43:59.712295 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6958 00:43:59.718952 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6959 00:43:59.722577 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6960 00:43:59.725583 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6961 00:43:59.729019 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6962 00:43:59.735450 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6963 00:43:59.738705 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6964 00:43:59.741917 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6965 00:43:59.748721 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6966 00:43:59.751937 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6967 00:43:59.755298 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6968 00:43:59.758706 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6969 00:43:59.765113 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6970 00:43:59.765582 ==
6971 00:43:59.768087 Dram Type= 6, Freq= 0, CH_1, rank 1
6972 00:43:59.771567 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6973 00:43:59.772030 ==
6974 00:43:59.772389 DQS Delay:
6975 00:43:59.775024 DQS0 = 51, DQS1 = 51
6976 00:43:59.775477 DQM Delay:
6977 00:43:59.778576 DQM0 = 19, DQM1 = 13
6978 00:43:59.779099 DQ Delay:
6979 00:43:59.781595 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6980 00:43:59.785013 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6981 00:43:59.788002 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6982 00:43:59.791387 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6983 00:43:59.791805
6984 00:43:59.792135
6985 00:43:59.792437 ==
6986 00:43:59.794683 Dram Type= 6, Freq= 0, CH_1, rank 1
6987 00:43:59.798057 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6988 00:43:59.801145 ==
6989 00:43:59.801560
6990 00:43:59.801880
6991 00:43:59.802209 TX Vref Scan disable
6992 00:43:59.804388 == TX Byte 0 ==
6993 00:43:59.807742 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6994 00:43:59.811058 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6995 00:43:59.814098 == TX Byte 1 ==
6996 00:43:59.817891 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6997 00:43:59.820952 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6998 00:43:59.821586 ==
6999 00:43:59.824125 Dram Type= 6, Freq= 0, CH_1, rank 1
7000 00:43:59.831002 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7001 00:43:59.831417 ==
7002 00:43:59.831743
7003 00:43:59.832046
7004 00:43:59.832338 TX Vref Scan disable
7005 00:43:59.833911 == TX Byte 0 ==
7006 00:43:59.837657 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
7007 00:43:59.840745 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
7008 00:43:59.844015 == TX Byte 1 ==
7009 00:43:59.847496 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
7010 00:43:59.850543 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
7011 00:43:59.850958
7012 00:43:59.853797 [DATLAT]
7013 00:43:59.854239 Freq=400, CH1 RK1
7014 00:43:59.854579
7015 00:43:59.857161 DATLAT Default: 0xe
7016 00:43:59.857761 0, 0xFFFF, sum = 0
7017 00:43:59.860163 1, 0xFFFF, sum = 0
7018 00:43:59.860581 2, 0xFFFF, sum = 0
7019 00:43:59.863731 3, 0xFFFF, sum = 0
7020 00:43:59.864148 4, 0xFFFF, sum = 0
7021 00:43:59.867260 5, 0xFFFF, sum = 0
7022 00:43:59.867959 6, 0xFFFF, sum = 0
7023 00:43:59.869980 7, 0xFFFF, sum = 0
7024 00:43:59.870450 8, 0xFFFF, sum = 0
7025 00:43:59.873439 9, 0xFFFF, sum = 0
7026 00:43:59.877113 10, 0xFFFF, sum = 0
7027 00:43:59.877719 11, 0xFFFF, sum = 0
7028 00:43:59.879950 12, 0xFFFF, sum = 0
7029 00:43:59.880378 13, 0x0, sum = 1
7030 00:43:59.883191 14, 0x0, sum = 2
7031 00:43:59.883635 15, 0x0, sum = 3
7032 00:43:59.883976 16, 0x0, sum = 4
7033 00:43:59.886932 best_step = 14
7034 00:43:59.887353
7035 00:43:59.887680 ==
7036 00:43:59.889830 Dram Type= 6, Freq= 0, CH_1, rank 1
7037 00:43:59.893101 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7038 00:43:59.893526 ==
7039 00:43:59.896599 RX Vref Scan: 0
7040 00:43:59.897190
7041 00:43:59.899752 RX Vref 0 -> 0, step: 1
7042 00:43:59.900170
7043 00:43:59.900499 RX Delay -343 -> 252, step: 8
7044 00:43:59.908468 iDelay=225, Bit 0, Center -28 (-271 ~ 216) 488
7045 00:43:59.912252 iDelay=225, Bit 1, Center -44 (-287 ~ 200) 488
7046 00:43:59.915433 iDelay=225, Bit 2, Center -48 (-287 ~ 192) 480
7047 00:43:59.921805 iDelay=225, Bit 3, Center -40 (-279 ~ 200) 480
7048 00:43:59.924966 iDelay=225, Bit 4, Center -36 (-279 ~ 208) 488
7049 00:43:59.928535 iDelay=225, Bit 5, Center -28 (-271 ~ 216) 488
7050 00:43:59.931525 iDelay=225, Bit 6, Center -24 (-271 ~ 224) 496
7051 00:43:59.938235 iDelay=225, Bit 7, Center -40 (-287 ~ 208) 496
7052 00:43:59.941544 iDelay=225, Bit 8, Center -56 (-303 ~ 192) 496
7053 00:43:59.944861 iDelay=225, Bit 9, Center -56 (-303 ~ 192) 496
7054 00:43:59.948170 iDelay=225, Bit 10, Center -44 (-287 ~ 200) 488
7055 00:43:59.954958 iDelay=225, Bit 11, Center -52 (-295 ~ 192) 488
7056 00:43:59.958039 iDelay=225, Bit 12, Center -36 (-287 ~ 216) 504
7057 00:43:59.961443 iDelay=225, Bit 13, Center -40 (-287 ~ 208) 496
7058 00:43:59.964753 iDelay=225, Bit 14, Center -40 (-287 ~ 208) 496
7059 00:43:59.971898 iDelay=225, Bit 15, Center -40 (-287 ~ 208) 496
7060 00:43:59.972363 ==
7061 00:43:59.975108 Dram Type= 6, Freq= 0, CH_1, rank 1
7062 00:43:59.977826 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7063 00:43:59.978281 ==
7064 00:43:59.978655 DQS Delay:
7065 00:43:59.981558 DQS0 = 48, DQS1 = 56
7066 00:43:59.981991 DQM Delay:
7067 00:43:59.984984 DQM0 = 12, DQM1 = 10
7068 00:43:59.985397 DQ Delay:
7069 00:43:59.987977 DQ0 =20, DQ1 =4, DQ2 =0, DQ3 =8
7070 00:43:59.991082 DQ4 =12, DQ5 =20, DQ6 =24, DQ7 =8
7071 00:43:59.994814 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
7072 00:43:59.998058 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =16
7073 00:43:59.998537
7074 00:43:59.998867
7075 00:44:00.004455 [DQSOSCAuto] RK1, (LSB)MR18= 0x6c5b, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 396 ps
7076 00:44:00.007893 CH1 RK1: MR19=C0C, MR18=6C5B
7077 00:44:00.014416 CH1_RK1: MR19=0xC0C, MR18=0x6C5B, DQSOSC=396, MR23=63, INC=376, DEC=251
7078 00:44:00.017531 [RxdqsGatingPostProcess] freq 400
7079 00:44:00.024049 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7080 00:44:00.027592 best DQS0 dly(2T, 0.5T) = (0, 10)
7081 00:44:00.030837 best DQS1 dly(2T, 0.5T) = (0, 10)
7082 00:44:00.033853 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7083 00:44:00.037489 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7084 00:44:00.037971 best DQS0 dly(2T, 0.5T) = (0, 10)
7085 00:44:00.040708 best DQS1 dly(2T, 0.5T) = (0, 10)
7086 00:44:00.044131 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7087 00:44:00.047239 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7088 00:44:00.050537 Pre-setting of DQS Precalculation
7089 00:44:00.057196 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7090 00:44:00.063626 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7091 00:44:00.070786 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7092 00:44:00.071202
7093 00:44:00.071526
7094 00:44:00.073380 [Calibration Summary] 800 Mbps
7095 00:44:00.073817 CH 0, Rank 0
7096 00:44:00.076897 SW Impedance : PASS
7097 00:44:00.080413 DUTY Scan : NO K
7098 00:44:00.080953 ZQ Calibration : PASS
7099 00:44:00.083349 Jitter Meter : NO K
7100 00:44:00.086866 CBT Training : PASS
7101 00:44:00.087285 Write leveling : PASS
7102 00:44:00.090557 RX DQS gating : PASS
7103 00:44:00.093302 RX DQ/DQS(RDDQC) : PASS
7104 00:44:00.093721 TX DQ/DQS : PASS
7105 00:44:00.096673 RX DATLAT : PASS
7106 00:44:00.099890 RX DQ/DQS(Engine): PASS
7107 00:44:00.100307 TX OE : NO K
7108 00:44:00.103349 All Pass.
7109 00:44:00.103764
7110 00:44:00.104091 CH 0, Rank 1
7111 00:44:00.106476 SW Impedance : PASS
7112 00:44:00.106893 DUTY Scan : NO K
7113 00:44:00.109894 ZQ Calibration : PASS
7114 00:44:00.113014 Jitter Meter : NO K
7115 00:44:00.113430 CBT Training : PASS
7116 00:44:00.116363 Write leveling : NO K
7117 00:44:00.119537 RX DQS gating : PASS
7118 00:44:00.119963 RX DQ/DQS(RDDQC) : PASS
7119 00:44:00.122941 TX DQ/DQS : PASS
7120 00:44:00.126278 RX DATLAT : PASS
7121 00:44:00.126692 RX DQ/DQS(Engine): PASS
7122 00:44:00.129773 TX OE : NO K
7123 00:44:00.130213 All Pass.
7124 00:44:00.130545
7125 00:44:00.133184 CH 1, Rank 0
7126 00:44:00.133596 SW Impedance : PASS
7127 00:44:00.136451 DUTY Scan : NO K
7128 00:44:00.139391 ZQ Calibration : PASS
7129 00:44:00.139807 Jitter Meter : NO K
7130 00:44:00.143105 CBT Training : PASS
7131 00:44:00.145816 Write leveling : PASS
7132 00:44:00.146268 RX DQS gating : PASS
7133 00:44:00.149499 RX DQ/DQS(RDDQC) : PASS
7134 00:44:00.149913 TX DQ/DQS : PASS
7135 00:44:00.152759 RX DATLAT : PASS
7136 00:44:00.156186 RX DQ/DQS(Engine): PASS
7137 00:44:00.156600 TX OE : NO K
7138 00:44:00.159324 All Pass.
7139 00:44:00.159752
7140 00:44:00.160077 CH 1, Rank 1
7141 00:44:00.162914 SW Impedance : PASS
7142 00:44:00.163521 DUTY Scan : NO K
7143 00:44:00.166196 ZQ Calibration : PASS
7144 00:44:00.169414 Jitter Meter : NO K
7145 00:44:00.169834 CBT Training : PASS
7146 00:44:00.172401 Write leveling : NO K
7147 00:44:00.176250 RX DQS gating : PASS
7148 00:44:00.176669 RX DQ/DQS(RDDQC) : PASS
7149 00:44:00.178903 TX DQ/DQS : PASS
7150 00:44:00.182096 RX DATLAT : PASS
7151 00:44:00.182664 RX DQ/DQS(Engine): PASS
7152 00:44:00.185576 TX OE : NO K
7153 00:44:00.185997 All Pass.
7154 00:44:00.186535
7155 00:44:00.189117 DramC Write-DBI off
7156 00:44:00.192118 PER_BANK_REFRESH: Hybrid Mode
7157 00:44:00.192539 TX_TRACKING: ON
7158 00:44:00.201894 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7159 00:44:00.205183 [FAST_K] Save calibration result to emmc
7160 00:44:00.208428 dramc_set_vcore_voltage set vcore to 725000
7161 00:44:00.211920 Read voltage for 1600, 0
7162 00:44:00.212339 Vio18 = 0
7163 00:44:00.212670 Vcore = 725000
7164 00:44:00.215364 Vdram = 0
7165 00:44:00.215797 Vddq = 0
7166 00:44:00.216141 Vmddr = 0
7167 00:44:00.221784 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7168 00:44:00.224984 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7169 00:44:00.228648 MEM_TYPE=3, freq_sel=13
7170 00:44:00.231940 sv_algorithm_assistance_LP4_3733
7171 00:44:00.235038 ============ PULL DRAM RESETB DOWN ============
7172 00:44:00.241813 ========== PULL DRAM RESETB DOWN end =========
7173 00:44:00.245024 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7174 00:44:00.248187 ===================================
7175 00:44:00.251699 LPDDR4 DRAM CONFIGURATION
7176 00:44:00.254977 ===================================
7177 00:44:00.255591 EX_ROW_EN[0] = 0x0
7178 00:44:00.257942 EX_ROW_EN[1] = 0x0
7179 00:44:00.258489 LP4Y_EN = 0x0
7180 00:44:00.261389 WORK_FSP = 0x1
7181 00:44:00.261900 WL = 0x5
7182 00:44:00.265005 RL = 0x5
7183 00:44:00.268169 BL = 0x2
7184 00:44:00.268581 RPST = 0x0
7185 00:44:00.271394 RD_PRE = 0x0
7186 00:44:00.271850 WR_PRE = 0x1
7187 00:44:00.274568 WR_PST = 0x1
7188 00:44:00.274982 DBI_WR = 0x0
7189 00:44:00.277784 DBI_RD = 0x0
7190 00:44:00.278223 OTF = 0x1
7191 00:44:00.281655 ===================================
7192 00:44:00.284699 ===================================
7193 00:44:00.287905 ANA top config
7194 00:44:00.291401 ===================================
7195 00:44:00.291922 DLL_ASYNC_EN = 0
7196 00:44:00.294524 ALL_SLAVE_EN = 0
7197 00:44:00.298016 NEW_RANK_MODE = 1
7198 00:44:00.300817 DLL_IDLE_MODE = 1
7199 00:44:00.301247 LP45_APHY_COMB_EN = 1
7200 00:44:00.304687 TX_ODT_DIS = 0
7201 00:44:00.307730 NEW_8X_MODE = 1
7202 00:44:00.311266 ===================================
7203 00:44:00.314631 ===================================
7204 00:44:00.317541 data_rate = 3200
7205 00:44:00.321233 CKR = 1
7206 00:44:00.324673 DQ_P2S_RATIO = 8
7207 00:44:00.327535 ===================================
7208 00:44:00.327951 CA_P2S_RATIO = 8
7209 00:44:00.331147 DQ_CA_OPEN = 0
7210 00:44:00.334594 DQ_SEMI_OPEN = 0
7211 00:44:00.337646 CA_SEMI_OPEN = 0
7212 00:44:00.340874 CA_FULL_RATE = 0
7213 00:44:00.343800 DQ_CKDIV4_EN = 0
7214 00:44:00.344215 CA_CKDIV4_EN = 0
7215 00:44:00.347715 CA_PREDIV_EN = 0
7216 00:44:00.350766 PH8_DLY = 12
7217 00:44:00.354215 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7218 00:44:00.357249 DQ_AAMCK_DIV = 4
7219 00:44:00.360558 CA_AAMCK_DIV = 4
7220 00:44:00.360975 CA_ADMCK_DIV = 4
7221 00:44:00.363644 DQ_TRACK_CA_EN = 0
7222 00:44:00.367438 CA_PICK = 1600
7223 00:44:00.370706 CA_MCKIO = 1600
7224 00:44:00.373795 MCKIO_SEMI = 0
7225 00:44:00.377536 PLL_FREQ = 3068
7226 00:44:00.380392 DQ_UI_PI_RATIO = 32
7227 00:44:00.383925 CA_UI_PI_RATIO = 0
7228 00:44:00.386989 ===================================
7229 00:44:00.390333 ===================================
7230 00:44:00.390756 memory_type:LPDDR4
7231 00:44:00.393637 GP_NUM : 10
7232 00:44:00.394052 SRAM_EN : 1
7233 00:44:00.397063 MD32_EN : 0
7234 00:44:00.400191 ===================================
7235 00:44:00.404134 [ANA_INIT] >>>>>>>>>>>>>>
7236 00:44:00.406883 <<<<<< [CONFIGURE PHASE]: ANA_TX
7237 00:44:00.410488 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7238 00:44:00.413805 ===================================
7239 00:44:00.417495 data_rate = 3200,PCW = 0X7600
7240 00:44:00.420557 ===================================
7241 00:44:00.424050 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7242 00:44:00.427071 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7243 00:44:00.433876 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7244 00:44:00.437181 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7245 00:44:00.440313 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7246 00:44:00.443299 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7247 00:44:00.446863 [ANA_INIT] flow start
7248 00:44:00.449758 [ANA_INIT] PLL >>>>>>>>
7249 00:44:00.450357 [ANA_INIT] PLL <<<<<<<<
7250 00:44:00.452976 [ANA_INIT] MIDPI >>>>>>>>
7251 00:44:00.456587 [ANA_INIT] MIDPI <<<<<<<<
7252 00:44:00.457047 [ANA_INIT] DLL >>>>>>>>
7253 00:44:00.460093 [ANA_INIT] DLL <<<<<<<<
7254 00:44:00.463449 [ANA_INIT] flow end
7255 00:44:00.466812 ============ LP4 DIFF to SE enter ============
7256 00:44:00.469564 ============ LP4 DIFF to SE exit ============
7257 00:44:00.473372 [ANA_INIT] <<<<<<<<<<<<<
7258 00:44:00.476310 [Flow] Enable top DCM control >>>>>
7259 00:44:00.479762 [Flow] Enable top DCM control <<<<<
7260 00:44:00.483193 Enable DLL master slave shuffle
7261 00:44:00.489573 ==============================================================
7262 00:44:00.490038 Gating Mode config
7263 00:44:00.496005 ==============================================================
7264 00:44:00.496567 Config description:
7265 00:44:00.505808 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7266 00:44:00.513089 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7267 00:44:00.518806 SELPH_MODE 0: By rank 1: By Phase
7268 00:44:00.522269 ==============================================================
7269 00:44:00.525791 GAT_TRACK_EN = 1
7270 00:44:00.529352 RX_GATING_MODE = 2
7271 00:44:00.532198 RX_GATING_TRACK_MODE = 2
7272 00:44:00.535642 SELPH_MODE = 1
7273 00:44:00.538639 PICG_EARLY_EN = 1
7274 00:44:00.542599 VALID_LAT_VALUE = 1
7275 00:44:00.549143 ==============================================================
7276 00:44:00.552262 Enter into Gating configuration >>>>
7277 00:44:00.555238 Exit from Gating configuration <<<<
7278 00:44:00.558619 Enter into DVFS_PRE_config >>>>>
7279 00:44:00.568405 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7280 00:44:00.571678 Exit from DVFS_PRE_config <<<<<
7281 00:44:00.575190 Enter into PICG configuration >>>>
7282 00:44:00.578880 Exit from PICG configuration <<<<
7283 00:44:00.582020 [RX_INPUT] configuration >>>>>
7284 00:44:00.582639 [RX_INPUT] configuration <<<<<
7285 00:44:00.588563 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7286 00:44:00.594880 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7287 00:44:00.598560 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7288 00:44:00.605521 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7289 00:44:00.612081 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7290 00:44:00.618337 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7291 00:44:00.621879 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7292 00:44:00.624985 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7293 00:44:00.631572 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7294 00:44:00.635105 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7295 00:44:00.638463 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7296 00:44:00.644492 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7297 00:44:00.648095 ===================================
7298 00:44:00.648664 LPDDR4 DRAM CONFIGURATION
7299 00:44:00.651342 ===================================
7300 00:44:00.654993 EX_ROW_EN[0] = 0x0
7301 00:44:00.655691 EX_ROW_EN[1] = 0x0
7302 00:44:00.657922 LP4Y_EN = 0x0
7303 00:44:00.661583 WORK_FSP = 0x1
7304 00:44:00.662098 WL = 0x5
7305 00:44:00.664844 RL = 0x5
7306 00:44:00.665317 BL = 0x2
7307 00:44:00.667557 RPST = 0x0
7308 00:44:00.668058 RD_PRE = 0x0
7309 00:44:00.670925 WR_PRE = 0x1
7310 00:44:00.671396 WR_PST = 0x1
7311 00:44:00.674283 DBI_WR = 0x0
7312 00:44:00.674755 DBI_RD = 0x0
7313 00:44:00.677866 OTF = 0x1
7314 00:44:00.680992 ===================================
7315 00:44:00.684362 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7316 00:44:00.687643 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7317 00:44:00.694018 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7318 00:44:00.697407 ===================================
7319 00:44:00.697898 LPDDR4 DRAM CONFIGURATION
7320 00:44:00.700726 ===================================
7321 00:44:00.703822 EX_ROW_EN[0] = 0x10
7322 00:44:00.707511 EX_ROW_EN[1] = 0x0
7323 00:44:00.707968 LP4Y_EN = 0x0
7324 00:44:00.711037 WORK_FSP = 0x1
7325 00:44:00.711593 WL = 0x5
7326 00:44:00.714089 RL = 0x5
7327 00:44:00.714599 BL = 0x2
7328 00:44:00.717372 RPST = 0x0
7329 00:44:00.717921 RD_PRE = 0x0
7330 00:44:00.720813 WR_PRE = 0x1
7331 00:44:00.721361 WR_PST = 0x1
7332 00:44:00.724409 DBI_WR = 0x0
7333 00:44:00.724962 DBI_RD = 0x0
7334 00:44:00.727091 OTF = 0x1
7335 00:44:00.730185 ===================================
7336 00:44:00.737101 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7337 00:44:00.737658 ==
7338 00:44:00.740196 Dram Type= 6, Freq= 0, CH_0, rank 0
7339 00:44:00.743532 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7340 00:44:00.744161 ==
7341 00:44:00.747080 [Duty_Offset_Calibration]
7342 00:44:00.747550 B0:1 B1:-1 CA:0
7343 00:44:00.748031
7344 00:44:00.750310 [DutyScan_Calibration_Flow] k_type=0
7345 00:44:00.761229
7346 00:44:00.761933 ==CLK 0==
7347 00:44:00.764359 Final CLK duty delay cell = 0
7348 00:44:00.767612 [0] MAX Duty = 5124%(X100), DQS PI = 22
7349 00:44:00.771227 [0] MIN Duty = 4907%(X100), DQS PI = 4
7350 00:44:00.771809 [0] AVG Duty = 5015%(X100)
7351 00:44:00.773881
7352 00:44:00.777844 CH0 CLK Duty spec in!! Max-Min= 217%
7353 00:44:00.780865 [DutyScan_Calibration_Flow] ====Done====
7354 00:44:00.781319
7355 00:44:00.783789 [DutyScan_Calibration_Flow] k_type=1
7356 00:44:00.800024
7357 00:44:00.800591 ==DQS 0 ==
7358 00:44:00.803089 Final DQS duty delay cell = -4
7359 00:44:00.806628 [-4] MAX Duty = 4969%(X100), DQS PI = 18
7360 00:44:00.809859 [-4] MIN Duty = 4844%(X100), DQS PI = 48
7361 00:44:00.813386 [-4] AVG Duty = 4906%(X100)
7362 00:44:00.813945
7363 00:44:00.814350 ==DQS 1 ==
7364 00:44:00.816671 Final DQS duty delay cell = 0
7365 00:44:00.819961 [0] MAX Duty = 5156%(X100), DQS PI = 2
7366 00:44:00.823324 [0] MIN Duty = 5000%(X100), DQS PI = 20
7367 00:44:00.826897 [0] AVG Duty = 5078%(X100)
7368 00:44:00.827416
7369 00:44:00.829527 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7370 00:44:00.829983
7371 00:44:00.833210 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7372 00:44:00.835945 [DutyScan_Calibration_Flow] ====Done====
7373 00:44:00.836301
7374 00:44:00.839293 [DutyScan_Calibration_Flow] k_type=3
7375 00:44:00.857387
7376 00:44:00.857793 ==DQM 0 ==
7377 00:44:00.860826 Final DQM duty delay cell = 0
7378 00:44:00.864077 [0] MAX Duty = 5124%(X100), DQS PI = 20
7379 00:44:00.867144 [0] MIN Duty = 4906%(X100), DQS PI = 12
7380 00:44:00.870750 [0] AVG Duty = 5015%(X100)
7381 00:44:00.871298
7382 00:44:00.871656 ==DQM 1 ==
7383 00:44:00.874010 Final DQM duty delay cell = 0
7384 00:44:00.877098 [0] MAX Duty = 5000%(X100), DQS PI = 6
7385 00:44:00.880472 [0] MIN Duty = 4782%(X100), DQS PI = 20
7386 00:44:00.883829 [0] AVG Duty = 4891%(X100)
7387 00:44:00.884282
7388 00:44:00.886849 CH0 DQM 0 Duty spec in!! Max-Min= 218%
7389 00:44:00.887303
7390 00:44:00.890558 CH0 DQM 1 Duty spec in!! Max-Min= 218%
7391 00:44:00.894055 [DutyScan_Calibration_Flow] ====Done====
7392 00:44:00.894657
7393 00:44:00.896709 [DutyScan_Calibration_Flow] k_type=2
7394 00:44:00.914085
7395 00:44:00.914688 ==DQ 0 ==
7396 00:44:00.917591 Final DQ duty delay cell = -4
7397 00:44:00.920297 [-4] MAX Duty = 5000%(X100), DQS PI = 22
7398 00:44:00.924136 [-4] MIN Duty = 4876%(X100), DQS PI = 52
7399 00:44:00.926796 [-4] AVG Duty = 4938%(X100)
7400 00:44:00.927250
7401 00:44:00.927664 ==DQ 1 ==
7402 00:44:00.930115 Final DQ duty delay cell = 0
7403 00:44:00.933611 [0] MAX Duty = 5125%(X100), DQS PI = 48
7404 00:44:00.936724 [0] MIN Duty = 5000%(X100), DQS PI = 36
7405 00:44:00.939949 [0] AVG Duty = 5062%(X100)
7406 00:44:00.940468
7407 00:44:00.943147 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7408 00:44:00.943601
7409 00:44:00.946620 CH0 DQ 1 Duty spec in!! Max-Min= 125%
7410 00:44:00.950046 [DutyScan_Calibration_Flow] ====Done====
7411 00:44:00.950546 ==
7412 00:44:00.953241 Dram Type= 6, Freq= 0, CH_1, rank 0
7413 00:44:00.956526 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7414 00:44:00.956989 ==
7415 00:44:00.959711 [Duty_Offset_Calibration]
7416 00:44:00.963236 B0:-1 B1:1 CA:2
7417 00:44:00.963685
7418 00:44:00.966024 [DutyScan_Calibration_Flow] k_type=0
7419 00:44:00.974716
7420 00:44:00.975122 ==CLK 0==
7421 00:44:00.977639 Final CLK duty delay cell = 0
7422 00:44:00.981074 [0] MAX Duty = 5187%(X100), DQS PI = 22
7423 00:44:00.984518 [0] MIN Duty = 4969%(X100), DQS PI = 62
7424 00:44:00.987486 [0] AVG Duty = 5078%(X100)
7425 00:44:00.987913
7426 00:44:00.991012 CH1 CLK Duty spec in!! Max-Min= 218%
7427 00:44:00.994225 [DutyScan_Calibration_Flow] ====Done====
7428 00:44:00.994640
7429 00:44:00.997758 [DutyScan_Calibration_Flow] k_type=1
7430 00:44:01.014007
7431 00:44:01.014504 ==DQS 0 ==
7432 00:44:01.017364 Final DQS duty delay cell = 0
7433 00:44:01.020425 [0] MAX Duty = 5124%(X100), DQS PI = 18
7434 00:44:01.024061 [0] MIN Duty = 4907%(X100), DQS PI = 10
7435 00:44:01.027203 [0] AVG Duty = 5015%(X100)
7436 00:44:01.027651
7437 00:44:01.027985 ==DQS 1 ==
7438 00:44:01.030765 Final DQS duty delay cell = 0
7439 00:44:01.033855 [0] MAX Duty = 5093%(X100), DQS PI = 30
7440 00:44:01.037286 [0] MIN Duty = 4969%(X100), DQS PI = 54
7441 00:44:01.040321 [0] AVG Duty = 5031%(X100)
7442 00:44:01.040743
7443 00:44:01.043974 CH1 DQS 0 Duty spec in!! Max-Min= 217%
7444 00:44:01.044385
7445 00:44:01.047608 CH1 DQS 1 Duty spec in!! Max-Min= 124%
7446 00:44:01.050607 [DutyScan_Calibration_Flow] ====Done====
7447 00:44:01.051019
7448 00:44:01.053886 [DutyScan_Calibration_Flow] k_type=3
7449 00:44:01.071090
7450 00:44:01.071502 ==DQM 0 ==
7451 00:44:01.074390 Final DQM duty delay cell = 0
7452 00:44:01.077558 [0] MAX Duty = 5218%(X100), DQS PI = 36
7453 00:44:01.080996 [0] MIN Duty = 5031%(X100), DQS PI = 6
7454 00:44:01.084411 [0] AVG Duty = 5124%(X100)
7455 00:44:01.084821
7456 00:44:01.085142 ==DQM 1 ==
7457 00:44:01.087304 Final DQM duty delay cell = 0
7458 00:44:01.090631 [0] MAX Duty = 5156%(X100), DQS PI = 6
7459 00:44:01.094111 [0] MIN Duty = 4938%(X100), DQS PI = 34
7460 00:44:01.097435 [0] AVG Duty = 5047%(X100)
7461 00:44:01.097843
7462 00:44:01.100589 CH1 DQM 0 Duty spec in!! Max-Min= 187%
7463 00:44:01.101000
7464 00:44:01.104388 CH1 DQM 1 Duty spec in!! Max-Min= 218%
7465 00:44:01.107225 [DutyScan_Calibration_Flow] ====Done====
7466 00:44:01.107638
7467 00:44:01.110441 [DutyScan_Calibration_Flow] k_type=2
7468 00:44:01.127546
7469 00:44:01.127844 ==DQ 0 ==
7470 00:44:01.130703 Final DQ duty delay cell = 0
7471 00:44:01.133995 [0] MAX Duty = 5156%(X100), DQS PI = 30
7472 00:44:01.137520 [0] MIN Duty = 4906%(X100), DQS PI = 8
7473 00:44:01.137699 [0] AVG Duty = 5031%(X100)
7474 00:44:01.140555
7475 00:44:01.140703 ==DQ 1 ==
7476 00:44:01.144214 Final DQ duty delay cell = 0
7477 00:44:01.147433 [0] MAX Duty = 5156%(X100), DQS PI = 10
7478 00:44:01.150299 [0] MIN Duty = 4938%(X100), DQS PI = 58
7479 00:44:01.153775 [0] AVG Duty = 5047%(X100)
7480 00:44:01.153887
7481 00:44:01.156873 CH1 DQ 0 Duty spec in!! Max-Min= 250%
7482 00:44:01.156973
7483 00:44:01.160257 CH1 DQ 1 Duty spec in!! Max-Min= 218%
7484 00:44:01.163601 [DutyScan_Calibration_Flow] ====Done====
7485 00:44:01.167064 nWR fixed to 30
7486 00:44:01.170091 [ModeRegInit_LP4] CH0 RK0
7487 00:44:01.170248 [ModeRegInit_LP4] CH0 RK1
7488 00:44:01.173574 [ModeRegInit_LP4] CH1 RK0
7489 00:44:01.176894 [ModeRegInit_LP4] CH1 RK1
7490 00:44:01.176978 match AC timing 5
7491 00:44:01.183662 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7492 00:44:01.186626 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7493 00:44:01.190154 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7494 00:44:01.196650 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7495 00:44:01.200145 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7496 00:44:01.200230 [MiockJmeterHQA]
7497 00:44:01.200295
7498 00:44:01.203037 [DramcMiockJmeter] u1RxGatingPI = 0
7499 00:44:01.206575 0 : 4367, 4140
7500 00:44:01.206658 4 : 4368, 4140
7501 00:44:01.210146 8 : 4252, 4027
7502 00:44:01.210267 12 : 4252, 4027
7503 00:44:01.213094 16 : 4252, 4027
7504 00:44:01.213177 20 : 4252, 4027
7505 00:44:01.213243 24 : 4254, 4029
7506 00:44:01.216490 28 : 4253, 4026
7507 00:44:01.216574 32 : 4252, 4027
7508 00:44:01.220059 36 : 4366, 4139
7509 00:44:01.220143 40 : 4255, 4029
7510 00:44:01.223246 44 : 4254, 4029
7511 00:44:01.223329 48 : 4252, 4027
7512 00:44:01.226217 52 : 4363, 4138
7513 00:44:01.226310 56 : 4253, 4026
7514 00:44:01.226375 60 : 4360, 4138
7515 00:44:01.229435 64 : 4252, 4030
7516 00:44:01.229519 68 : 4250, 4027
7517 00:44:01.232712 72 : 4250, 4027
7518 00:44:01.232857 76 : 4252, 4029
7519 00:44:01.236154 80 : 4250, 4026
7520 00:44:01.236238 84 : 4249, 4027
7521 00:44:01.239283 88 : 4363, 4140
7522 00:44:01.239398 92 : 4250, 1042
7523 00:44:01.239493 96 : 4252, 0
7524 00:44:01.242690 100 : 4363, 0
7525 00:44:01.242775 104 : 4363, 0
7526 00:44:01.246133 108 : 4250, 0
7527 00:44:01.246252 112 : 4252, 0
7528 00:44:01.246319 116 : 4361, 0
7529 00:44:01.249276 120 : 4360, 0
7530 00:44:01.249360 124 : 4250, 0
7531 00:44:01.252857 128 : 4250, 0
7532 00:44:01.252940 132 : 4250, 0
7533 00:44:01.253006 136 : 4252, 0
7534 00:44:01.255783 140 : 4360, 0
7535 00:44:01.255878 144 : 4250, 0
7536 00:44:01.259125 148 : 4250, 0
7537 00:44:01.259207 152 : 4249, 0
7538 00:44:01.259286 156 : 4360, 0
7539 00:44:01.262386 160 : 4360, 0
7540 00:44:01.262510 164 : 4249, 0
7541 00:44:01.262618 168 : 4361, 0
7542 00:44:01.265654 172 : 4250, 0
7543 00:44:01.265758 176 : 4250, 0
7544 00:44:01.268626 180 : 4250, 0
7545 00:44:01.268737 184 : 4250, 0
7546 00:44:01.268924 188 : 4253, 0
7547 00:44:01.272158 192 : 4360, 0
7548 00:44:01.272264 196 : 4250, 0
7549 00:44:01.275866 200 : 4250, 0
7550 00:44:01.275955 204 : 4249, 0
7551 00:44:01.276021 208 : 4361, 0
7552 00:44:01.278785 212 : 4360, 0
7553 00:44:01.278870 216 : 4250, 0
7554 00:44:01.282038 220 : 4250, 0
7555 00:44:01.282146 224 : 4363, 142
7556 00:44:01.285373 228 : 4250, 2850
7557 00:44:01.285454 232 : 4250, 4027
7558 00:44:01.285517 236 : 4249, 4027
7559 00:44:01.288502 240 : 4250, 4026
7560 00:44:01.288585 244 : 4250, 4027
7561 00:44:01.292015 248 : 4249, 4027
7562 00:44:01.292111 252 : 4252, 4029
7563 00:44:01.295438 256 : 4250, 4026
7564 00:44:01.295533 260 : 4361, 4137
7565 00:44:01.298816 264 : 4360, 4138
7566 00:44:01.298912 268 : 4250, 4027
7567 00:44:01.301740 272 : 4363, 4140
7568 00:44:01.301866 276 : 4250, 4026
7569 00:44:01.305050 280 : 4250, 4027
7570 00:44:01.305203 284 : 4249, 4027
7571 00:44:01.308855 288 : 4252, 4029
7572 00:44:01.308967 292 : 4250, 4026
7573 00:44:01.309056 296 : 4250, 4027
7574 00:44:01.312379 300 : 4249, 4027
7575 00:44:01.312503 304 : 4252, 4029
7576 00:44:01.314997 308 : 4250, 4027
7577 00:44:01.315134 312 : 4361, 4137
7578 00:44:01.318081 316 : 4363, 4140
7579 00:44:01.318268 320 : 4250, 4027
7580 00:44:01.321630 324 : 4363, 4140
7581 00:44:01.321784 328 : 4250, 4026
7582 00:44:01.324689 332 : 4250, 4027
7583 00:44:01.324848 336 : 4249, 3871
7584 00:44:01.328305 340 : 4252, 1960
7585 00:44:01.328577
7586 00:44:01.328755 MIOCK jitter meter ch=0
7587 00:44:01.328940
7588 00:44:01.331854 1T = (340-92) = 248 dly cells
7589 00:44:01.338358 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 262/100 ps
7590 00:44:01.338574 ==
7591 00:44:01.341660 Dram Type= 6, Freq= 0, CH_0, rank 0
7592 00:44:01.344772 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7593 00:44:01.344942 ==
7594 00:44:01.351073 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7595 00:44:01.354700 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7596 00:44:01.361725 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7597 00:44:01.364476 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7598 00:44:01.374580 [CA 0] Center 43 (13~74) winsize 62
7599 00:44:01.377903 [CA 1] Center 43 (13~73) winsize 61
7600 00:44:01.381031 [CA 2] Center 38 (9~68) winsize 60
7601 00:44:01.384706 [CA 3] Center 38 (9~68) winsize 60
7602 00:44:01.387718 [CA 4] Center 37 (8~66) winsize 59
7603 00:44:01.391616 [CA 5] Center 36 (7~66) winsize 60
7604 00:44:01.391856
7605 00:44:01.394429 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7606 00:44:01.394679
7607 00:44:01.401223 [CATrainingPosCal] consider 1 rank data
7608 00:44:01.401512 u2DelayCellTimex100 = 262/100 ps
7609 00:44:01.407705 CA0 delay=43 (13~74),Diff = 7 PI (26 cell)
7610 00:44:01.411234 CA1 delay=43 (13~73),Diff = 7 PI (26 cell)
7611 00:44:01.414049 CA2 delay=38 (9~68),Diff = 2 PI (7 cell)
7612 00:44:01.417453 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7613 00:44:01.420679 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
7614 00:44:01.424118 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7615 00:44:01.424355
7616 00:44:01.427368 CA PerBit enable=1, Macro0, CA PI delay=36
7617 00:44:01.427605
7618 00:44:01.430898 [CBTSetCACLKResult] CA Dly = 36
7619 00:44:01.433960 CS Dly: 11 (0~42)
7620 00:44:01.437569 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7621 00:44:01.440642 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7622 00:44:01.441059 ==
7623 00:44:01.443969 Dram Type= 6, Freq= 0, CH_0, rank 1
7624 00:44:01.450699 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7625 00:44:01.451113 ==
7626 00:44:01.454202 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7627 00:44:01.460396 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7628 00:44:01.463780 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7629 00:44:01.470305 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7630 00:44:01.478256 [CA 0] Center 42 (12~73) winsize 62
7631 00:44:01.481816 [CA 1] Center 43 (13~73) winsize 61
7632 00:44:01.484917 [CA 2] Center 37 (8~67) winsize 60
7633 00:44:01.488332 [CA 3] Center 37 (7~67) winsize 61
7634 00:44:01.491338 [CA 4] Center 36 (6~66) winsize 61
7635 00:44:01.494702 [CA 5] Center 35 (5~65) winsize 61
7636 00:44:01.495221
7637 00:44:01.497905 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7638 00:44:01.498389
7639 00:44:01.501860 [CATrainingPosCal] consider 2 rank data
7640 00:44:01.504759 u2DelayCellTimex100 = 262/100 ps
7641 00:44:01.508299 CA0 delay=43 (13~73),Diff = 7 PI (26 cell)
7642 00:44:01.514608 CA1 delay=43 (13~73),Diff = 7 PI (26 cell)
7643 00:44:01.518418 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
7644 00:44:01.521456 CA3 delay=38 (9~67),Diff = 2 PI (7 cell)
7645 00:44:01.524722 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
7646 00:44:01.527873 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
7647 00:44:01.528300
7648 00:44:01.531445 CA PerBit enable=1, Macro0, CA PI delay=36
7649 00:44:01.531860
7650 00:44:01.534908 [CBTSetCACLKResult] CA Dly = 36
7651 00:44:01.537760 CS Dly: 12 (0~44)
7652 00:44:01.541209 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7653 00:44:01.544516 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7654 00:44:01.544931
7655 00:44:01.547453 ----->DramcWriteLeveling(PI) begin...
7656 00:44:01.547873 ==
7657 00:44:01.551005 Dram Type= 6, Freq= 0, CH_0, rank 0
7658 00:44:01.557938 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7659 00:44:01.558487 ==
7660 00:44:01.560798 Write leveling (Byte 0): 36 => 36
7661 00:44:01.564554 Write leveling (Byte 1): 27 => 27
7662 00:44:01.565015 DramcWriteLeveling(PI) end<-----
7663 00:44:01.565540
7664 00:44:01.567684 ==
7665 00:44:01.570689 Dram Type= 6, Freq= 0, CH_0, rank 0
7666 00:44:01.574053 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7667 00:44:01.574521 ==
7668 00:44:01.577050 [Gating] SW mode calibration
7669 00:44:01.583946 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7670 00:44:01.587403 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7671 00:44:01.594106 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7672 00:44:01.597443 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7673 00:44:01.600507 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7674 00:44:01.607046 1 4 12 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
7675 00:44:01.610338 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7676 00:44:01.613901 1 4 20 | B1->B0 | 2323 3434 | 1 1 | (1 1) (1 1)
7677 00:44:01.620423 1 4 24 | B1->B0 | 3030 3434 | 1 1 | (0 0) (1 1)
7678 00:44:01.623466 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7679 00:44:01.627082 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7680 00:44:01.633559 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7681 00:44:01.636846 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7682 00:44:01.639887 1 5 12 | B1->B0 | 3434 2a2a | 1 0 | (1 1) (0 0)
7683 00:44:01.646350 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7684 00:44:01.649813 1 5 20 | B1->B0 | 3434 2323 | 0 0 | (0 1) (0 0)
7685 00:44:01.653073 1 5 24 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
7686 00:44:01.659681 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7687 00:44:01.663007 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7688 00:44:01.666544 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7689 00:44:01.672760 1 6 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7690 00:44:01.676377 1 6 12 | B1->B0 | 2323 3636 | 0 1 | (0 0) (0 0)
7691 00:44:01.680090 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7692 00:44:01.686248 1 6 20 | B1->B0 | 2626 4646 | 0 0 | (0 0) (0 0)
7693 00:44:01.689234 1 6 24 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
7694 00:44:01.692700 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7695 00:44:01.699150 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7696 00:44:01.702443 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7697 00:44:01.706011 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7698 00:44:01.712925 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7699 00:44:01.715631 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7700 00:44:01.719032 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7701 00:44:01.725650 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7702 00:44:01.728721 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7703 00:44:01.732604 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7704 00:44:01.738786 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7705 00:44:01.742048 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7706 00:44:01.745400 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7707 00:44:01.751950 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7708 00:44:01.755315 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7709 00:44:01.758676 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7710 00:44:01.765168 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7711 00:44:01.768392 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7712 00:44:01.771689 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7713 00:44:01.778280 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7714 00:44:01.781577 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7715 00:44:01.785057 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7716 00:44:01.788608 Total UI for P1: 0, mck2ui 16
7717 00:44:01.791460 best dqsien dly found for B0: ( 1, 9, 12)
7718 00:44:01.798539 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7719 00:44:01.801352 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7720 00:44:01.804608 Total UI for P1: 0, mck2ui 16
7721 00:44:01.807935 best dqsien dly found for B1: ( 1, 9, 20)
7722 00:44:01.811018 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
7723 00:44:01.814393 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7724 00:44:01.814886
7725 00:44:01.817709 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
7726 00:44:01.824800 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7727 00:44:01.825470 [Gating] SW calibration Done
7728 00:44:01.827751 ==
7729 00:44:01.828202 Dram Type= 6, Freq= 0, CH_0, rank 0
7730 00:44:01.834672 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7731 00:44:01.835151 ==
7732 00:44:01.835509 RX Vref Scan: 0
7733 00:44:01.835822
7734 00:44:01.837620 RX Vref 0 -> 0, step: 1
7735 00:44:01.838030
7736 00:44:01.840896 RX Delay 0 -> 252, step: 8
7737 00:44:01.844313 iDelay=200, Bit 0, Center 135 (88 ~ 183) 96
7738 00:44:01.847363 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7739 00:44:01.851102 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
7740 00:44:01.857535 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7741 00:44:01.860407 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7742 00:44:01.864065 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7743 00:44:01.867709 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
7744 00:44:01.871011 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7745 00:44:01.877219 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7746 00:44:01.880366 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7747 00:44:01.883507 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
7748 00:44:01.887359 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7749 00:44:01.893394 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7750 00:44:01.896655 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7751 00:44:01.900142 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7752 00:44:01.903653 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7753 00:44:01.904066 ==
7754 00:44:01.906720 Dram Type= 6, Freq= 0, CH_0, rank 0
7755 00:44:01.913152 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7756 00:44:01.913570 ==
7757 00:44:01.913892 DQS Delay:
7758 00:44:01.914235 DQS0 = 0, DQS1 = 0
7759 00:44:01.916592 DQM Delay:
7760 00:44:01.917010 DQM0 = 136, DQM1 = 126
7761 00:44:01.919513 DQ Delay:
7762 00:44:01.923351 DQ0 =135, DQ1 =139, DQ2 =131, DQ3 =131
7763 00:44:01.926442 DQ4 =139, DQ5 =123, DQ6 =143, DQ7 =147
7764 00:44:01.929843 DQ8 =119, DQ9 =111, DQ10 =127, DQ11 =119
7765 00:44:01.932861 DQ12 =131, DQ13 =135, DQ14 =139, DQ15 =131
7766 00:44:01.933286
7767 00:44:01.933609
7768 00:44:01.933907 ==
7769 00:44:01.936319 Dram Type= 6, Freq= 0, CH_0, rank 0
7770 00:44:01.942874 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7771 00:44:01.943296 ==
7772 00:44:01.943625
7773 00:44:01.943924
7774 00:44:01.944212 TX Vref Scan disable
7775 00:44:01.946041 == TX Byte 0 ==
7776 00:44:01.949375 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7777 00:44:01.955904 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7778 00:44:01.956350 == TX Byte 1 ==
7779 00:44:01.959127 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7780 00:44:01.965670 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7781 00:44:01.966144 ==
7782 00:44:01.969174 Dram Type= 6, Freq= 0, CH_0, rank 0
7783 00:44:01.972573 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7784 00:44:01.972986 ==
7785 00:44:01.985596
7786 00:44:01.989186 TX Vref early break, caculate TX vref
7787 00:44:01.992251 TX Vref=16, minBit 14, minWin=22, winSum=373
7788 00:44:01.995542 TX Vref=18, minBit 4, minWin=22, winSum=379
7789 00:44:01.998712 TX Vref=20, minBit 1, minWin=24, winSum=388
7790 00:44:02.001951 TX Vref=22, minBit 4, minWin=23, winSum=400
7791 00:44:02.008816 TX Vref=24, minBit 3, minWin=24, winSum=406
7792 00:44:02.012203 TX Vref=26, minBit 0, minWin=25, winSum=418
7793 00:44:02.015550 TX Vref=28, minBit 4, minWin=25, winSum=419
7794 00:44:02.018500 TX Vref=30, minBit 7, minWin=24, winSum=410
7795 00:44:02.021719 TX Vref=32, minBit 5, minWin=23, winSum=398
7796 00:44:02.025623 TX Vref=34, minBit 4, minWin=22, winSum=386
7797 00:44:02.031649 [TxChooseVref] Worse bit 4, Min win 25, Win sum 419, Final Vref 28
7798 00:44:02.032199
7799 00:44:02.035178 Final TX Range 0 Vref 28
7800 00:44:02.035597
7801 00:44:02.035958 ==
7802 00:44:02.038692 Dram Type= 6, Freq= 0, CH_0, rank 0
7803 00:44:02.041445 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7804 00:44:02.041898 ==
7805 00:44:02.042253
7806 00:44:02.044777
7807 00:44:02.045180 TX Vref Scan disable
7808 00:44:02.051763 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
7809 00:44:02.052339 == TX Byte 0 ==
7810 00:44:02.054666 u2DelayCellOfst[0]=14 cells (4 PI)
7811 00:44:02.058207 u2DelayCellOfst[1]=18 cells (5 PI)
7812 00:44:02.061281 u2DelayCellOfst[2]=14 cells (4 PI)
7813 00:44:02.064227 u2DelayCellOfst[3]=14 cells (4 PI)
7814 00:44:02.067853 u2DelayCellOfst[4]=11 cells (3 PI)
7815 00:44:02.071185 u2DelayCellOfst[5]=0 cells (0 PI)
7816 00:44:02.074769 u2DelayCellOfst[6]=18 cells (5 PI)
7817 00:44:02.078086 u2DelayCellOfst[7]=22 cells (6 PI)
7818 00:44:02.081151 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7819 00:44:02.084236 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7820 00:44:02.087461 == TX Byte 1 ==
7821 00:44:02.090553 u2DelayCellOfst[8]=0 cells (0 PI)
7822 00:44:02.094471 u2DelayCellOfst[9]=0 cells (0 PI)
7823 00:44:02.097823 u2DelayCellOfst[10]=3 cells (1 PI)
7824 00:44:02.100480 u2DelayCellOfst[11]=0 cells (0 PI)
7825 00:44:02.103853 u2DelayCellOfst[12]=7 cells (2 PI)
7826 00:44:02.106847 u2DelayCellOfst[13]=11 cells (3 PI)
7827 00:44:02.110436 u2DelayCellOfst[14]=11 cells (3 PI)
7828 00:44:02.113514 u2DelayCellOfst[15]=7 cells (2 PI)
7829 00:44:02.117167 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7830 00:44:02.120613 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7831 00:44:02.123653 DramC Write-DBI on
7832 00:44:02.124106 ==
7833 00:44:02.127187 Dram Type= 6, Freq= 0, CH_0, rank 0
7834 00:44:02.130025 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7835 00:44:02.130519 ==
7836 00:44:02.130878
7837 00:44:02.131207
7838 00:44:02.133609 TX Vref Scan disable
7839 00:44:02.137127 == TX Byte 0 ==
7840 00:44:02.140249 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
7841 00:44:02.140705 == TX Byte 1 ==
7842 00:44:02.146535 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
7843 00:44:02.147095 DramC Write-DBI off
7844 00:44:02.147454
7845 00:44:02.147782 [DATLAT]
7846 00:44:02.150342 Freq=1600, CH0 RK0
7847 00:44:02.150907
7848 00:44:02.153131 DATLAT Default: 0xf
7849 00:44:02.153581 0, 0xFFFF, sum = 0
7850 00:44:02.156622 1, 0xFFFF, sum = 0
7851 00:44:02.157181 2, 0xFFFF, sum = 0
7852 00:44:02.160134 3, 0xFFFF, sum = 0
7853 00:44:02.160608 4, 0xFFFF, sum = 0
7854 00:44:02.163545 5, 0xFFFF, sum = 0
7855 00:44:02.164039 6, 0xFFFF, sum = 0
7856 00:44:02.166610 7, 0xFFFF, sum = 0
7857 00:44:02.167100 8, 0xFFFF, sum = 0
7858 00:44:02.169406 9, 0xFFFF, sum = 0
7859 00:44:02.169867 10, 0xFFFF, sum = 0
7860 00:44:02.173111 11, 0xFFFF, sum = 0
7861 00:44:02.173708 12, 0xFFFF, sum = 0
7862 00:44:02.176541 13, 0xFFFF, sum = 0
7863 00:44:02.177103 14, 0x0, sum = 1
7864 00:44:02.179570 15, 0x0, sum = 2
7865 00:44:02.180032 16, 0x0, sum = 3
7866 00:44:02.183301 17, 0x0, sum = 4
7867 00:44:02.183863 best_step = 15
7868 00:44:02.184224
7869 00:44:02.184553 ==
7870 00:44:02.186420 Dram Type= 6, Freq= 0, CH_0, rank 0
7871 00:44:02.193040 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7872 00:44:02.193609 ==
7873 00:44:02.193994 RX Vref Scan: 1
7874 00:44:02.194388
7875 00:44:02.196404 Set Vref Range= 24 -> 127
7876 00:44:02.196856
7877 00:44:02.199888 RX Vref 24 -> 127, step: 1
7878 00:44:02.200444
7879 00:44:02.202775 RX Delay 11 -> 252, step: 4
7880 00:44:02.203229
7881 00:44:02.206348 Set Vref, RX VrefLevel [Byte0]: 24
7882 00:44:02.208896 [Byte1]: 24
7883 00:44:02.209349
7884 00:44:02.212882 Set Vref, RX VrefLevel [Byte0]: 25
7885 00:44:02.215782 [Byte1]: 25
7886 00:44:02.216233
7887 00:44:02.219309 Set Vref, RX VrefLevel [Byte0]: 26
7888 00:44:02.222410 [Byte1]: 26
7889 00:44:02.225681
7890 00:44:02.226279 Set Vref, RX VrefLevel [Byte0]: 27
7891 00:44:02.228914 [Byte1]: 27
7892 00:44:02.233312
7893 00:44:02.233934 Set Vref, RX VrefLevel [Byte0]: 28
7894 00:44:02.236215 [Byte1]: 28
7895 00:44:02.240672
7896 00:44:02.241249 Set Vref, RX VrefLevel [Byte0]: 29
7897 00:44:02.244172 [Byte1]: 29
7898 00:44:02.248537
7899 00:44:02.248989 Set Vref, RX VrefLevel [Byte0]: 30
7900 00:44:02.251998 [Byte1]: 30
7901 00:44:02.256197
7902 00:44:02.256606 Set Vref, RX VrefLevel [Byte0]: 31
7903 00:44:02.259661 [Byte1]: 31
7904 00:44:02.263732
7905 00:44:02.264173 Set Vref, RX VrefLevel [Byte0]: 32
7906 00:44:02.267095 [Byte1]: 32
7907 00:44:02.271365
7908 00:44:02.271964 Set Vref, RX VrefLevel [Byte0]: 33
7909 00:44:02.274753 [Byte1]: 33
7910 00:44:02.278894
7911 00:44:02.279433 Set Vref, RX VrefLevel [Byte0]: 34
7912 00:44:02.281967 [Byte1]: 34
7913 00:44:02.286645
7914 00:44:02.287054 Set Vref, RX VrefLevel [Byte0]: 35
7915 00:44:02.289899 [Byte1]: 35
7916 00:44:02.294191
7917 00:44:02.294719 Set Vref, RX VrefLevel [Byte0]: 36
7918 00:44:02.297504 [Byte1]: 36
7919 00:44:02.301975
7920 00:44:02.302574 Set Vref, RX VrefLevel [Byte0]: 37
7921 00:44:02.308280 [Byte1]: 37
7922 00:44:02.308794
7923 00:44:02.311789 Set Vref, RX VrefLevel [Byte0]: 38
7924 00:44:02.314633 [Byte1]: 38
7925 00:44:02.315052
7926 00:44:02.318460 Set Vref, RX VrefLevel [Byte0]: 39
7927 00:44:02.321600 [Byte1]: 39
7928 00:44:02.324765
7929 00:44:02.325321 Set Vref, RX VrefLevel [Byte0]: 40
7930 00:44:02.328045 [Byte1]: 40
7931 00:44:02.332190
7932 00:44:02.332609 Set Vref, RX VrefLevel [Byte0]: 41
7933 00:44:02.335653 [Byte1]: 41
7934 00:44:02.339888
7935 00:44:02.340396 Set Vref, RX VrefLevel [Byte0]: 42
7936 00:44:02.343066 [Byte1]: 42
7937 00:44:02.347325
7938 00:44:02.347748 Set Vref, RX VrefLevel [Byte0]: 43
7939 00:44:02.350840 [Byte1]: 43
7940 00:44:02.355112
7941 00:44:02.355617 Set Vref, RX VrefLevel [Byte0]: 44
7942 00:44:02.358605 [Byte1]: 44
7943 00:44:02.362907
7944 00:44:02.363315 Set Vref, RX VrefLevel [Byte0]: 45
7945 00:44:02.366097 [Byte1]: 45
7946 00:44:02.370085
7947 00:44:02.370540 Set Vref, RX VrefLevel [Byte0]: 46
7948 00:44:02.373661 [Byte1]: 46
7949 00:44:02.378261
7950 00:44:02.378845 Set Vref, RX VrefLevel [Byte0]: 47
7951 00:44:02.381051 [Byte1]: 47
7952 00:44:02.385811
7953 00:44:02.386345 Set Vref, RX VrefLevel [Byte0]: 48
7954 00:44:02.389583 [Byte1]: 48
7955 00:44:02.393683
7956 00:44:02.394216 Set Vref, RX VrefLevel [Byte0]: 49
7957 00:44:02.396891 [Byte1]: 49
7958 00:44:02.400802
7959 00:44:02.401313 Set Vref, RX VrefLevel [Byte0]: 50
7960 00:44:02.406857 [Byte1]: 50
7961 00:44:02.407266
7962 00:44:02.410534 Set Vref, RX VrefLevel [Byte0]: 51
7963 00:44:02.414315 [Byte1]: 51
7964 00:44:02.414825
7965 00:44:02.416991 Set Vref, RX VrefLevel [Byte0]: 52
7966 00:44:02.420317 [Byte1]: 52
7967 00:44:02.423302
7968 00:44:02.423707 Set Vref, RX VrefLevel [Byte0]: 53
7969 00:44:02.427302 [Byte1]: 53
7970 00:44:02.431143
7971 00:44:02.431697 Set Vref, RX VrefLevel [Byte0]: 54
7972 00:44:02.434461 [Byte1]: 54
7973 00:44:02.438560
7974 00:44:02.439072 Set Vref, RX VrefLevel [Byte0]: 55
7975 00:44:02.441854 [Byte1]: 55
7976 00:44:02.446573
7977 00:44:02.447019 Set Vref, RX VrefLevel [Byte0]: 56
7978 00:44:02.450043 [Byte1]: 56
7979 00:44:02.453959
7980 00:44:02.454408 Set Vref, RX VrefLevel [Byte0]: 57
7981 00:44:02.457270 [Byte1]: 57
7982 00:44:02.461699
7983 00:44:02.462276 Set Vref, RX VrefLevel [Byte0]: 58
7984 00:44:02.464915 [Byte1]: 58
7985 00:44:02.469015
7986 00:44:02.469450 Set Vref, RX VrefLevel [Byte0]: 59
7987 00:44:02.472452 [Byte1]: 59
7988 00:44:02.476795
7989 00:44:02.477458 Set Vref, RX VrefLevel [Byte0]: 60
7990 00:44:02.480070 [Byte1]: 60
7991 00:44:02.484335
7992 00:44:02.484904 Set Vref, RX VrefLevel [Byte0]: 61
7993 00:44:02.487612 [Byte1]: 61
7994 00:44:02.491910
7995 00:44:02.492466 Set Vref, RX VrefLevel [Byte0]: 62
7996 00:44:02.495756 [Byte1]: 62
7997 00:44:02.499526
7998 00:44:02.499943 Set Vref, RX VrefLevel [Byte0]: 63
7999 00:44:02.506446 [Byte1]: 63
8000 00:44:02.506974
8001 00:44:02.509289 Set Vref, RX VrefLevel [Byte0]: 64
8002 00:44:02.513033 [Byte1]: 64
8003 00:44:02.513546
8004 00:44:02.516181 Set Vref, RX VrefLevel [Byte0]: 65
8005 00:44:02.519262 [Byte1]: 65
8006 00:44:02.522315
8007 00:44:02.522897 Set Vref, RX VrefLevel [Byte0]: 66
8008 00:44:02.525735 [Byte1]: 66
8009 00:44:02.530019
8010 00:44:02.530486 Set Vref, RX VrefLevel [Byte0]: 67
8011 00:44:02.533579 [Byte1]: 67
8012 00:44:02.537825
8013 00:44:02.538275 Set Vref, RX VrefLevel [Byte0]: 68
8014 00:44:02.541378 [Byte1]: 68
8015 00:44:02.545479
8016 00:44:02.545890 Set Vref, RX VrefLevel [Byte0]: 69
8017 00:44:02.548501 [Byte1]: 69
8018 00:44:02.552932
8019 00:44:02.553440 Set Vref, RX VrefLevel [Byte0]: 70
8020 00:44:02.556237 [Byte1]: 70
8021 00:44:02.560424
8022 00:44:02.560854 Set Vref, RX VrefLevel [Byte0]: 71
8023 00:44:02.564246 [Byte1]: 71
8024 00:44:02.568099
8025 00:44:02.568508 Set Vref, RX VrefLevel [Byte0]: 72
8026 00:44:02.571476 [Byte1]: 72
8027 00:44:02.576101
8028 00:44:02.576511 Set Vref, RX VrefLevel [Byte0]: 73
8029 00:44:02.579418 [Byte1]: 73
8030 00:44:02.583336
8031 00:44:02.583742 Set Vref, RX VrefLevel [Byte0]: 74
8032 00:44:02.586637 [Byte1]: 74
8033 00:44:02.590742
8034 00:44:02.591256 Set Vref, RX VrefLevel [Byte0]: 75
8035 00:44:02.594147 [Byte1]: 75
8036 00:44:02.598485
8037 00:44:02.598894 Set Vref, RX VrefLevel [Byte0]: 76
8038 00:44:02.604826 [Byte1]: 76
8039 00:44:02.605325
8040 00:44:02.608455 Set Vref, RX VrefLevel [Byte0]: 77
8041 00:44:02.611321 [Byte1]: 77
8042 00:44:02.611733
8043 00:44:02.614961 Set Vref, RX VrefLevel [Byte0]: 78
8044 00:44:02.618047 [Byte1]: 78
8045 00:44:02.621603
8046 00:44:02.622110 Set Vref, RX VrefLevel [Byte0]: 79
8047 00:44:02.625566 [Byte1]: 79
8048 00:44:02.629111
8049 00:44:02.629666 Final RX Vref Byte 0 = 66 to rank0
8050 00:44:02.632319 Final RX Vref Byte 1 = 58 to rank0
8051 00:44:02.636004 Final RX Vref Byte 0 = 66 to rank1
8052 00:44:02.639321 Final RX Vref Byte 1 = 58 to rank1==
8053 00:44:02.642353 Dram Type= 6, Freq= 0, CH_0, rank 0
8054 00:44:02.649200 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8055 00:44:02.649754 ==
8056 00:44:02.650233 DQS Delay:
8057 00:44:02.652268 DQS0 = 0, DQS1 = 0
8058 00:44:02.652817 DQM Delay:
8059 00:44:02.653178 DQM0 = 133, DQM1 = 123
8060 00:44:02.655561 DQ Delay:
8061 00:44:02.658857 DQ0 =130, DQ1 =136, DQ2 =132, DQ3 =132
8062 00:44:02.661995 DQ4 =134, DQ5 =122, DQ6 =140, DQ7 =142
8063 00:44:02.665161 DQ8 =114, DQ9 =112, DQ10 =124, DQ11 =116
8064 00:44:02.668625 DQ12 =128, DQ13 =126, DQ14 =134, DQ15 =130
8065 00:44:02.669079
8066 00:44:02.669432
8067 00:44:02.669775
8068 00:44:02.671969 [DramC_TX_OE_Calibration] TA2
8069 00:44:02.675118 Original DQ_B0 (3 6) =30, OEN = 27
8070 00:44:02.678386 Original DQ_B1 (3 6) =30, OEN = 27
8071 00:44:02.681821 24, 0x0, End_B0=24 End_B1=24
8072 00:44:02.684908 25, 0x0, End_B0=25 End_B1=25
8073 00:44:02.685366 26, 0x0, End_B0=26 End_B1=26
8074 00:44:02.688733 27, 0x0, End_B0=27 End_B1=27
8075 00:44:02.692016 28, 0x0, End_B0=28 End_B1=28
8076 00:44:02.694877 29, 0x0, End_B0=29 End_B1=29
8077 00:44:02.695337 30, 0x0, End_B0=30 End_B1=30
8078 00:44:02.698519 31, 0x4141, End_B0=30 End_B1=30
8079 00:44:02.702128 Byte0 end_step=30 best_step=27
8080 00:44:02.704862 Byte1 end_step=30 best_step=27
8081 00:44:02.708156 Byte0 TX OE(2T, 0.5T) = (3, 3)
8082 00:44:02.711371 Byte1 TX OE(2T, 0.5T) = (3, 3)
8083 00:44:02.711826
8084 00:44:02.712184
8085 00:44:02.718101 [DQSOSCAuto] RK0, (LSB)MR18= 0x2011, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 393 ps
8086 00:44:02.721695 CH0 RK0: MR19=303, MR18=2011
8087 00:44:02.727733 CH0_RK0: MR19=0x303, MR18=0x2011, DQSOSC=393, MR23=63, INC=23, DEC=15
8088 00:44:02.728322
8089 00:44:02.731152 ----->DramcWriteLeveling(PI) begin...
8090 00:44:02.731702 ==
8091 00:44:02.734284 Dram Type= 6, Freq= 0, CH_0, rank 1
8092 00:44:02.737799 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8093 00:44:02.738295 ==
8094 00:44:02.741523 Write leveling (Byte 0): 36 => 36
8095 00:44:02.744629 Write leveling (Byte 1): 27 => 27
8096 00:44:02.747994 DramcWriteLeveling(PI) end<-----
8097 00:44:02.748404
8098 00:44:02.748725 ==
8099 00:44:02.750873 Dram Type= 6, Freq= 0, CH_0, rank 1
8100 00:44:02.754194 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8101 00:44:02.757784 ==
8102 00:44:02.758229 [Gating] SW mode calibration
8103 00:44:02.767678 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8104 00:44:02.771126 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8105 00:44:02.774244 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8106 00:44:02.780759 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8107 00:44:02.784095 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8108 00:44:02.787491 1 4 12 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8109 00:44:02.794109 1 4 16 | B1->B0 | 2323 3333 | 0 1 | (0 0) (0 0)
8110 00:44:02.797550 1 4 20 | B1->B0 | 2b2b 3434 | 0 1 | (0 0) (1 1)
8111 00:44:02.800689 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8112 00:44:02.807228 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8113 00:44:02.810541 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8114 00:44:02.814098 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8115 00:44:02.820418 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8116 00:44:02.823876 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8117 00:44:02.827300 1 5 16 | B1->B0 | 3434 2424 | 1 0 | (1 0) (0 1)
8118 00:44:02.834222 1 5 20 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
8119 00:44:02.837277 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8120 00:44:02.840613 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8121 00:44:02.847370 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8122 00:44:02.849958 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8123 00:44:02.853476 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8124 00:44:02.860047 1 6 12 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
8125 00:44:02.863844 1 6 16 | B1->B0 | 2c2c 4545 | 1 0 | (0 0) (0 0)
8126 00:44:02.866517 1 6 20 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
8127 00:44:02.873171 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8128 00:44:02.876397 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8129 00:44:02.879967 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8130 00:44:02.886122 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8131 00:44:02.890210 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8132 00:44:02.893182 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8133 00:44:02.899745 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8134 00:44:02.902941 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8135 00:44:02.906781 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8136 00:44:02.913184 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8137 00:44:02.916774 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8138 00:44:02.919817 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8139 00:44:02.926455 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8140 00:44:02.929706 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8141 00:44:02.932786 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8142 00:44:02.939829 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8143 00:44:02.943114 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8144 00:44:02.946654 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8145 00:44:02.953064 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8146 00:44:02.956489 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8147 00:44:02.959292 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8148 00:44:02.966156 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8149 00:44:02.969284 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8150 00:44:02.972502 Total UI for P1: 0, mck2ui 16
8151 00:44:02.975664 best dqsien dly found for B0: ( 1, 9, 12)
8152 00:44:02.978988 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8153 00:44:02.985986 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8154 00:44:02.986502 Total UI for P1: 0, mck2ui 16
8155 00:44:02.992720 best dqsien dly found for B1: ( 1, 9, 18)
8156 00:44:02.995908 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8157 00:44:02.998854 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8158 00:44:02.999311
8159 00:44:03.002271 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8160 00:44:03.005338 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8161 00:44:03.008806 [Gating] SW calibration Done
8162 00:44:03.009217 ==
8163 00:44:03.011932 Dram Type= 6, Freq= 0, CH_0, rank 1
8164 00:44:03.015243 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8165 00:44:03.015656 ==
8166 00:44:03.018489 RX Vref Scan: 0
8167 00:44:03.018894
8168 00:44:03.019214 RX Vref 0 -> 0, step: 1
8169 00:44:03.019515
8170 00:44:03.021783 RX Delay 0 -> 252, step: 8
8171 00:44:03.025078 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8172 00:44:03.031921 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8173 00:44:03.034988 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8174 00:44:03.038265 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8175 00:44:03.041795 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8176 00:44:03.044808 iDelay=200, Bit 5, Center 123 (64 ~ 183) 120
8177 00:44:03.051624 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8178 00:44:03.054791 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8179 00:44:03.058553 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8180 00:44:03.061401 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8181 00:44:03.068097 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8182 00:44:03.071051 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8183 00:44:03.074428 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8184 00:44:03.077835 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8185 00:44:03.080950 iDelay=200, Bit 14, Center 143 (88 ~ 199) 112
8186 00:44:03.088009 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8187 00:44:03.088563 ==
8188 00:44:03.091407 Dram Type= 6, Freq= 0, CH_0, rank 1
8189 00:44:03.094209 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8190 00:44:03.094672 ==
8191 00:44:03.095028 DQS Delay:
8192 00:44:03.097832 DQS0 = 0, DQS1 = 0
8193 00:44:03.098429 DQM Delay:
8194 00:44:03.100821 DQM0 = 133, DQM1 = 129
8195 00:44:03.101517 DQ Delay:
8196 00:44:03.103809 DQ0 =135, DQ1 =135, DQ2 =127, DQ3 =127
8197 00:44:03.107263 DQ4 =135, DQ5 =123, DQ6 =139, DQ7 =143
8198 00:44:03.110901 DQ8 =119, DQ9 =115, DQ10 =131, DQ11 =123
8199 00:44:03.117486 DQ12 =135, DQ13 =135, DQ14 =143, DQ15 =135
8200 00:44:03.118033
8201 00:44:03.118438
8202 00:44:03.118769 ==
8203 00:44:03.120748 Dram Type= 6, Freq= 0, CH_0, rank 1
8204 00:44:03.123541 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8205 00:44:03.123952 ==
8206 00:44:03.124274
8207 00:44:03.124571
8208 00:44:03.127467 TX Vref Scan disable
8209 00:44:03.127895 == TX Byte 0 ==
8210 00:44:03.133946 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8211 00:44:03.136949 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8212 00:44:03.137364 == TX Byte 1 ==
8213 00:44:03.143794 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8214 00:44:03.146669 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8215 00:44:03.147081 ==
8216 00:44:03.149935 Dram Type= 6, Freq= 0, CH_0, rank 1
8217 00:44:03.153430 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8218 00:44:03.153926 ==
8219 00:44:03.168211
8220 00:44:03.171584 TX Vref early break, caculate TX vref
8221 00:44:03.174893 TX Vref=16, minBit 0, minWin=22, winSum=375
8222 00:44:03.178239 TX Vref=18, minBit 0, minWin=23, winSum=386
8223 00:44:03.181661 TX Vref=20, minBit 5, minWin=23, winSum=393
8224 00:44:03.184931 TX Vref=22, minBit 1, minWin=24, winSum=398
8225 00:44:03.188280 TX Vref=24, minBit 3, minWin=24, winSum=406
8226 00:44:03.194951 TX Vref=26, minBit 2, minWin=24, winSum=411
8227 00:44:03.197998 TX Vref=28, minBit 0, minWin=24, winSum=412
8228 00:44:03.201311 TX Vref=30, minBit 1, minWin=24, winSum=403
8229 00:44:03.204494 TX Vref=32, minBit 0, minWin=24, winSum=396
8230 00:44:03.208153 TX Vref=34, minBit 0, minWin=22, winSum=387
8231 00:44:03.214938 [TxChooseVref] Worse bit 0, Min win 24, Win sum 412, Final Vref 28
8232 00:44:03.215358
8233 00:44:03.218219 Final TX Range 0 Vref 28
8234 00:44:03.218737
8235 00:44:03.219064 ==
8236 00:44:03.221178 Dram Type= 6, Freq= 0, CH_0, rank 1
8237 00:44:03.224871 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8238 00:44:03.225390 ==
8239 00:44:03.225723
8240 00:44:03.226023
8241 00:44:03.227874 TX Vref Scan disable
8242 00:44:03.234134 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8243 00:44:03.234610 == TX Byte 0 ==
8244 00:44:03.237719 u2DelayCellOfst[0]=11 cells (3 PI)
8245 00:44:03.241192 u2DelayCellOfst[1]=14 cells (4 PI)
8246 00:44:03.244154 u2DelayCellOfst[2]=11 cells (3 PI)
8247 00:44:03.247490 u2DelayCellOfst[3]=11 cells (3 PI)
8248 00:44:03.250731 u2DelayCellOfst[4]=7 cells (2 PI)
8249 00:44:03.254216 u2DelayCellOfst[5]=0 cells (0 PI)
8250 00:44:03.257538 u2DelayCellOfst[6]=14 cells (4 PI)
8251 00:44:03.260695 u2DelayCellOfst[7]=18 cells (5 PI)
8252 00:44:03.264324 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8253 00:44:03.267364 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8254 00:44:03.270734 == TX Byte 1 ==
8255 00:44:03.274236 u2DelayCellOfst[8]=0 cells (0 PI)
8256 00:44:03.277132 u2DelayCellOfst[9]=0 cells (0 PI)
8257 00:44:03.277547 u2DelayCellOfst[10]=7 cells (2 PI)
8258 00:44:03.280626 u2DelayCellOfst[11]=0 cells (0 PI)
8259 00:44:03.284153 u2DelayCellOfst[12]=11 cells (3 PI)
8260 00:44:03.287145 u2DelayCellOfst[13]=11 cells (3 PI)
8261 00:44:03.290398 u2DelayCellOfst[14]=14 cells (4 PI)
8262 00:44:03.294203 u2DelayCellOfst[15]=11 cells (3 PI)
8263 00:44:03.300008 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8264 00:44:03.303106 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8265 00:44:03.303187 DramC Write-DBI on
8266 00:44:03.306848 ==
8267 00:44:03.306929 Dram Type= 6, Freq= 0, CH_0, rank 1
8268 00:44:03.312985 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8269 00:44:03.313066 ==
8270 00:44:03.313128
8271 00:44:03.313187
8272 00:44:03.316361 TX Vref Scan disable
8273 00:44:03.316441 == TX Byte 0 ==
8274 00:44:03.322852 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
8275 00:44:03.322960 == TX Byte 1 ==
8276 00:44:03.326500 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8277 00:44:03.329421 DramC Write-DBI off
8278 00:44:03.329521
8279 00:44:03.329611 [DATLAT]
8280 00:44:03.332825 Freq=1600, CH0 RK1
8281 00:44:03.332905
8282 00:44:03.332968 DATLAT Default: 0xf
8283 00:44:03.336003 0, 0xFFFF, sum = 0
8284 00:44:03.336085 1, 0xFFFF, sum = 0
8285 00:44:03.339413 2, 0xFFFF, sum = 0
8286 00:44:03.339494 3, 0xFFFF, sum = 0
8287 00:44:03.342882 4, 0xFFFF, sum = 0
8288 00:44:03.342964 5, 0xFFFF, sum = 0
8289 00:44:03.346035 6, 0xFFFF, sum = 0
8290 00:44:03.349155 7, 0xFFFF, sum = 0
8291 00:44:03.349264 8, 0xFFFF, sum = 0
8292 00:44:03.352637 9, 0xFFFF, sum = 0
8293 00:44:03.352718 10, 0xFFFF, sum = 0
8294 00:44:03.356040 11, 0xFFFF, sum = 0
8295 00:44:03.356121 12, 0xFFFF, sum = 0
8296 00:44:03.359071 13, 0xFFFF, sum = 0
8297 00:44:03.359168 14, 0x0, sum = 1
8298 00:44:03.362723 15, 0x0, sum = 2
8299 00:44:03.362805 16, 0x0, sum = 3
8300 00:44:03.366310 17, 0x0, sum = 4
8301 00:44:03.366391 best_step = 15
8302 00:44:03.366454
8303 00:44:03.366512 ==
8304 00:44:03.369209 Dram Type= 6, Freq= 0, CH_0, rank 1
8305 00:44:03.372494 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8306 00:44:03.376029 ==
8307 00:44:03.376116 RX Vref Scan: 0
8308 00:44:03.376194
8309 00:44:03.379009 RX Vref 0 -> 0, step: 1
8310 00:44:03.379121
8311 00:44:03.379219 RX Delay 11 -> 252, step: 4
8312 00:44:03.386438 iDelay=195, Bit 0, Center 128 (79 ~ 178) 100
8313 00:44:03.389847 iDelay=195, Bit 1, Center 134 (79 ~ 190) 112
8314 00:44:03.392946 iDelay=195, Bit 2, Center 124 (71 ~ 178) 108
8315 00:44:03.396436 iDelay=195, Bit 3, Center 128 (75 ~ 182) 108
8316 00:44:03.403099 iDelay=195, Bit 4, Center 130 (79 ~ 182) 104
8317 00:44:03.406150 iDelay=195, Bit 5, Center 120 (67 ~ 174) 108
8318 00:44:03.409671 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
8319 00:44:03.412828 iDelay=195, Bit 7, Center 140 (87 ~ 194) 108
8320 00:44:03.416322 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
8321 00:44:03.422510 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8322 00:44:03.426071 iDelay=195, Bit 10, Center 126 (71 ~ 182) 112
8323 00:44:03.429483 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8324 00:44:03.432724 iDelay=195, Bit 12, Center 130 (79 ~ 182) 104
8325 00:44:03.439777 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8326 00:44:03.442688 iDelay=195, Bit 14, Center 136 (83 ~ 190) 108
8327 00:44:03.446220 iDelay=195, Bit 15, Center 134 (83 ~ 186) 104
8328 00:44:03.446635 ==
8329 00:44:03.449483 Dram Type= 6, Freq= 0, CH_0, rank 1
8330 00:44:03.452785 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8331 00:44:03.453239 ==
8332 00:44:03.455602 DQS Delay:
8333 00:44:03.456012 DQS0 = 0, DQS1 = 0
8334 00:44:03.458923 DQM Delay:
8335 00:44:03.459334 DQM0 = 130, DQM1 = 125
8336 00:44:03.459657 DQ Delay:
8337 00:44:03.466063 DQ0 =128, DQ1 =134, DQ2 =124, DQ3 =128
8338 00:44:03.469253 DQ4 =130, DQ5 =120, DQ6 =138, DQ7 =140
8339 00:44:03.472199 DQ8 =116, DQ9 =112, DQ10 =126, DQ11 =120
8340 00:44:03.475783 DQ12 =130, DQ13 =132, DQ14 =136, DQ15 =134
8341 00:44:03.476194
8342 00:44:03.476513
8343 00:44:03.476865
8344 00:44:03.478902 [DramC_TX_OE_Calibration] TA2
8345 00:44:03.482496 Original DQ_B0 (3 6) =30, OEN = 27
8346 00:44:03.485347 Original DQ_B1 (3 6) =30, OEN = 27
8347 00:44:03.485762 24, 0x0, End_B0=24 End_B1=24
8348 00:44:03.488764 25, 0x0, End_B0=25 End_B1=25
8349 00:44:03.491971 26, 0x0, End_B0=26 End_B1=26
8350 00:44:03.495782 27, 0x0, End_B0=27 End_B1=27
8351 00:44:03.499076 28, 0x0, End_B0=28 End_B1=28
8352 00:44:03.499558 29, 0x0, End_B0=29 End_B1=29
8353 00:44:03.502055 30, 0x0, End_B0=30 End_B1=30
8354 00:44:03.505301 31, 0x4141, End_B0=30 End_B1=30
8355 00:44:03.508434 Byte0 end_step=30 best_step=27
8356 00:44:03.511621 Byte1 end_step=30 best_step=27
8357 00:44:03.515085 Byte0 TX OE(2T, 0.5T) = (3, 3)
8358 00:44:03.515514 Byte1 TX OE(2T, 0.5T) = (3, 3)
8359 00:44:03.515842
8360 00:44:03.518449
8361 00:44:03.524848 [DQSOSCAuto] RK1, (LSB)MR18= 0x2004, (MSB)MR19= 0x303, tDQSOscB0 = 408 ps tDQSOscB1 = 393 ps
8362 00:44:03.528183 CH0 RK1: MR19=303, MR18=2004
8363 00:44:03.535055 CH0_RK1: MR19=0x303, MR18=0x2004, DQSOSC=393, MR23=63, INC=23, DEC=15
8364 00:44:03.538065 [RxdqsGatingPostProcess] freq 1600
8365 00:44:03.541215 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8366 00:44:03.544589 best DQS0 dly(2T, 0.5T) = (1, 1)
8367 00:44:03.547981 best DQS1 dly(2T, 0.5T) = (1, 1)
8368 00:44:03.551412 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8369 00:44:03.555047 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8370 00:44:03.558154 best DQS0 dly(2T, 0.5T) = (1, 1)
8371 00:44:03.561262 best DQS1 dly(2T, 0.5T) = (1, 1)
8372 00:44:03.564633 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8373 00:44:03.567874 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8374 00:44:03.571281 Pre-setting of DQS Precalculation
8375 00:44:03.574340 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8376 00:44:03.574776 ==
8377 00:44:03.577958 Dram Type= 6, Freq= 0, CH_1, rank 0
8378 00:44:03.580898 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8379 00:44:03.581450 ==
8380 00:44:03.587915 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8381 00:44:03.591097 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8382 00:44:03.597491 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8383 00:44:03.600685 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8384 00:44:03.610935 [CA 0] Center 42 (12~72) winsize 61
8385 00:44:03.614485 [CA 1] Center 42 (13~72) winsize 60
8386 00:44:03.617808 [CA 2] Center 38 (9~67) winsize 59
8387 00:44:03.620816 [CA 3] Center 37 (8~66) winsize 59
8388 00:44:03.623953 [CA 4] Center 38 (9~67) winsize 59
8389 00:44:03.627397 [CA 5] Center 37 (8~67) winsize 60
8390 00:44:03.627896
8391 00:44:03.630554 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8392 00:44:03.630959
8393 00:44:03.637273 [CATrainingPosCal] consider 1 rank data
8394 00:44:03.637681 u2DelayCellTimex100 = 262/100 ps
8395 00:44:03.644128 CA0 delay=42 (12~72),Diff = 5 PI (18 cell)
8396 00:44:03.647249 CA1 delay=42 (13~72),Diff = 5 PI (18 cell)
8397 00:44:03.650502 CA2 delay=38 (9~67),Diff = 1 PI (3 cell)
8398 00:44:03.653989 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8399 00:44:03.656982 CA4 delay=38 (9~67),Diff = 1 PI (3 cell)
8400 00:44:03.660464 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8401 00:44:03.660875
8402 00:44:03.663541 CA PerBit enable=1, Macro0, CA PI delay=37
8403 00:44:03.663952
8404 00:44:03.666792 [CBTSetCACLKResult] CA Dly = 37
8405 00:44:03.670017 CS Dly: 9 (0~40)
8406 00:44:03.673625 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8407 00:44:03.676662 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8408 00:44:03.677069 ==
8409 00:44:03.680244 Dram Type= 6, Freq= 0, CH_1, rank 1
8410 00:44:03.686604 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8411 00:44:03.687036 ==
8412 00:44:03.689624 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8413 00:44:03.696860 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8414 00:44:03.699757 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8415 00:44:03.706259 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8416 00:44:03.714377 [CA 0] Center 42 (12~72) winsize 61
8417 00:44:03.717499 [CA 1] Center 42 (13~72) winsize 60
8418 00:44:03.721046 [CA 2] Center 37 (8~67) winsize 60
8419 00:44:03.724030 [CA 3] Center 37 (8~66) winsize 59
8420 00:44:03.727107 [CA 4] Center 37 (8~67) winsize 60
8421 00:44:03.730467 [CA 5] Center 37 (7~67) winsize 61
8422 00:44:03.730885
8423 00:44:03.734102 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8424 00:44:03.734571
8425 00:44:03.737726 [CATrainingPosCal] consider 2 rank data
8426 00:44:03.740539 u2DelayCellTimex100 = 262/100 ps
8427 00:44:03.747362 CA0 delay=42 (12~72),Diff = 5 PI (18 cell)
8428 00:44:03.750619 CA1 delay=42 (13~72),Diff = 5 PI (18 cell)
8429 00:44:03.754155 CA2 delay=38 (9~67),Diff = 1 PI (3 cell)
8430 00:44:03.757077 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8431 00:44:03.760650 CA4 delay=38 (9~67),Diff = 1 PI (3 cell)
8432 00:44:03.764161 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8433 00:44:03.764619
8434 00:44:03.766990 CA PerBit enable=1, Macro0, CA PI delay=37
8435 00:44:03.767402
8436 00:44:03.770517 [CBTSetCACLKResult] CA Dly = 37
8437 00:44:03.773292 CS Dly: 10 (0~43)
8438 00:44:03.776883 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8439 00:44:03.780091 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8440 00:44:03.780655
8441 00:44:03.783336 ----->DramcWriteLeveling(PI) begin...
8442 00:44:03.783769 ==
8443 00:44:03.786724 Dram Type= 6, Freq= 0, CH_1, rank 0
8444 00:44:03.793164 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8445 00:44:03.793705 ==
8446 00:44:03.796679 Write leveling (Byte 0): 23 => 23
8447 00:44:03.799669 Write leveling (Byte 1): 26 => 26
8448 00:44:03.800091 DramcWriteLeveling(PI) end<-----
8449 00:44:03.803372
8450 00:44:03.803879 ==
8451 00:44:03.806248 Dram Type= 6, Freq= 0, CH_1, rank 0
8452 00:44:03.809759 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8453 00:44:03.810209 ==
8454 00:44:03.812918 [Gating] SW mode calibration
8455 00:44:03.819685 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8456 00:44:03.826046 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8457 00:44:03.829463 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8458 00:44:03.832991 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8459 00:44:03.839052 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8460 00:44:03.842610 1 4 12 | B1->B0 | 2d2d 3434 | 0 1 | (0 0) (1 1)
8461 00:44:03.846264 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8462 00:44:03.852601 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8463 00:44:03.855936 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8464 00:44:03.858925 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8465 00:44:03.865604 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8466 00:44:03.868728 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8467 00:44:03.872423 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8468 00:44:03.878627 1 5 12 | B1->B0 | 3131 2626 | 1 0 | (1 0) (1 0)
8469 00:44:03.881809 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8470 00:44:03.885128 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8471 00:44:03.891867 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8472 00:44:03.895144 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8473 00:44:03.898502 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8474 00:44:03.905278 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8475 00:44:03.908274 1 6 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8476 00:44:03.911313 1 6 12 | B1->B0 | 3d3d 4444 | 0 0 | (0 0) (0 0)
8477 00:44:03.918258 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8478 00:44:03.921639 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8479 00:44:03.924652 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8480 00:44:03.931253 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8481 00:44:03.934353 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8482 00:44:03.937764 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8483 00:44:03.944544 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8484 00:44:03.947842 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8485 00:44:03.951167 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8486 00:44:03.957440 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8487 00:44:03.960575 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8488 00:44:03.964345 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8489 00:44:03.970896 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8490 00:44:03.974371 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8491 00:44:03.977536 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8492 00:44:03.983866 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8493 00:44:03.987491 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8494 00:44:03.990518 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8495 00:44:03.997081 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8496 00:44:04.000361 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8497 00:44:04.003605 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8498 00:44:04.010653 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8499 00:44:04.013687 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8500 00:44:04.016878 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8501 00:44:04.023358 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8502 00:44:04.023777 Total UI for P1: 0, mck2ui 16
8503 00:44:04.030356 best dqsien dly found for B0: ( 1, 9, 10)
8504 00:44:04.030773 Total UI for P1: 0, mck2ui 16
8505 00:44:04.036710 best dqsien dly found for B1: ( 1, 9, 12)
8506 00:44:04.039855 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8507 00:44:04.043112 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8508 00:44:04.043526
8509 00:44:04.046517 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8510 00:44:04.049960 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8511 00:44:04.053082 [Gating] SW calibration Done
8512 00:44:04.053517 ==
8513 00:44:04.056373 Dram Type= 6, Freq= 0, CH_1, rank 0
8514 00:44:04.059960 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8515 00:44:04.060376 ==
8516 00:44:04.062693 RX Vref Scan: 0
8517 00:44:04.063110
8518 00:44:04.063438 RX Vref 0 -> 0, step: 1
8519 00:44:04.066237
8520 00:44:04.066652 RX Delay 0 -> 252, step: 8
8521 00:44:04.073203 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8522 00:44:04.076488 iDelay=208, Bit 1, Center 131 (80 ~ 183) 104
8523 00:44:04.079655 iDelay=208, Bit 2, Center 127 (72 ~ 183) 112
8524 00:44:04.083143 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8525 00:44:04.086330 iDelay=208, Bit 4, Center 135 (80 ~ 191) 112
8526 00:44:04.092838 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8527 00:44:04.096147 iDelay=208, Bit 6, Center 143 (88 ~ 199) 112
8528 00:44:04.099483 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8529 00:44:04.102828 iDelay=208, Bit 8, Center 115 (56 ~ 175) 120
8530 00:44:04.105878 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8531 00:44:04.112555 iDelay=208, Bit 10, Center 127 (72 ~ 183) 112
8532 00:44:04.115751 iDelay=208, Bit 11, Center 123 (72 ~ 175) 104
8533 00:44:04.118904 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8534 00:44:04.122065 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8535 00:44:04.125973 iDelay=208, Bit 14, Center 135 (80 ~ 191) 112
8536 00:44:04.132499 iDelay=208, Bit 15, Center 139 (88 ~ 191) 104
8537 00:44:04.132930 ==
8538 00:44:04.135361 Dram Type= 6, Freq= 0, CH_1, rank 0
8539 00:44:04.138790 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8540 00:44:04.139206 ==
8541 00:44:04.139671 DQS Delay:
8542 00:44:04.142065 DQS0 = 0, DQS1 = 0
8543 00:44:04.142509 DQM Delay:
8544 00:44:04.145408 DQM0 = 137, DQM1 = 128
8545 00:44:04.145840 DQ Delay:
8546 00:44:04.148724 DQ0 =139, DQ1 =131, DQ2 =127, DQ3 =135
8547 00:44:04.152158 DQ4 =135, DQ5 =151, DQ6 =143, DQ7 =135
8548 00:44:04.155091 DQ8 =115, DQ9 =115, DQ10 =127, DQ11 =123
8549 00:44:04.161707 DQ12 =135, DQ13 =139, DQ14 =135, DQ15 =139
8550 00:44:04.162235
8551 00:44:04.162574
8552 00:44:04.162892 ==
8553 00:44:04.164912 Dram Type= 6, Freq= 0, CH_1, rank 0
8554 00:44:04.168237 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8555 00:44:04.168653 ==
8556 00:44:04.169013
8557 00:44:04.169328
8558 00:44:04.171755 TX Vref Scan disable
8559 00:44:04.171835 == TX Byte 0 ==
8560 00:44:04.178076 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8561 00:44:04.181179 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8562 00:44:04.181259 == TX Byte 1 ==
8563 00:44:04.187664 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8564 00:44:04.190872 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8565 00:44:04.190952 ==
8566 00:44:04.194569 Dram Type= 6, Freq= 0, CH_1, rank 0
8567 00:44:04.197587 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8568 00:44:04.197667 ==
8569 00:44:04.212221
8570 00:44:04.215549 TX Vref early break, caculate TX vref
8571 00:44:04.218329 TX Vref=16, minBit 0, minWin=21, winSum=372
8572 00:44:04.221603 TX Vref=18, minBit 0, minWin=22, winSum=385
8573 00:44:04.224729 TX Vref=20, minBit 0, minWin=23, winSum=391
8574 00:44:04.227900 TX Vref=22, minBit 0, minWin=23, winSum=401
8575 00:44:04.231429 TX Vref=24, minBit 5, minWin=23, winSum=409
8576 00:44:04.237931 TX Vref=26, minBit 0, minWin=24, winSum=417
8577 00:44:04.241250 TX Vref=28, minBit 0, minWin=24, winSum=419
8578 00:44:04.244421 TX Vref=30, minBit 0, minWin=24, winSum=412
8579 00:44:04.247990 TX Vref=32, minBit 0, minWin=23, winSum=400
8580 00:44:04.251751 TX Vref=34, minBit 0, minWin=23, winSum=395
8581 00:44:04.257923 [TxChooseVref] Worse bit 0, Min win 24, Win sum 419, Final Vref 28
8582 00:44:04.258006
8583 00:44:04.261202 Final TX Range 0 Vref 28
8584 00:44:04.261283
8585 00:44:04.261347 ==
8586 00:44:04.264691 Dram Type= 6, Freq= 0, CH_1, rank 0
8587 00:44:04.267877 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8588 00:44:04.267958 ==
8589 00:44:04.268023
8590 00:44:04.268082
8591 00:44:04.271242 TX Vref Scan disable
8592 00:44:04.277754 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8593 00:44:04.277867 == TX Byte 0 ==
8594 00:44:04.281517 u2DelayCellOfst[0]=18 cells (5 PI)
8595 00:44:04.284497 u2DelayCellOfst[1]=11 cells (3 PI)
8596 00:44:04.287769 u2DelayCellOfst[2]=0 cells (0 PI)
8597 00:44:04.290872 u2DelayCellOfst[3]=3 cells (1 PI)
8598 00:44:04.294131 u2DelayCellOfst[4]=7 cells (2 PI)
8599 00:44:04.297497 u2DelayCellOfst[5]=18 cells (5 PI)
8600 00:44:04.300982 u2DelayCellOfst[6]=18 cells (5 PI)
8601 00:44:04.304235 u2DelayCellOfst[7]=3 cells (1 PI)
8602 00:44:04.307149 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8603 00:44:04.310611 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8604 00:44:04.313832 == TX Byte 1 ==
8605 00:44:04.317327 u2DelayCellOfst[8]=0 cells (0 PI)
8606 00:44:04.317407 u2DelayCellOfst[9]=3 cells (1 PI)
8607 00:44:04.320418 u2DelayCellOfst[10]=11 cells (3 PI)
8608 00:44:04.323824 u2DelayCellOfst[11]=3 cells (1 PI)
8609 00:44:04.327011 u2DelayCellOfst[12]=14 cells (4 PI)
8610 00:44:04.330521 u2DelayCellOfst[13]=18 cells (5 PI)
8611 00:44:04.333941 u2DelayCellOfst[14]=18 cells (5 PI)
8612 00:44:04.337403 u2DelayCellOfst[15]=18 cells (5 PI)
8613 00:44:04.343640 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8614 00:44:04.346866 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8615 00:44:04.346946 DramC Write-DBI on
8616 00:44:04.347010 ==
8617 00:44:04.350156 Dram Type= 6, Freq= 0, CH_1, rank 0
8618 00:44:04.357245 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8619 00:44:04.357326 ==
8620 00:44:04.357390
8621 00:44:04.357448
8622 00:44:04.357505 TX Vref Scan disable
8623 00:44:04.361013 == TX Byte 0 ==
8624 00:44:04.364032 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
8625 00:44:04.367757 == TX Byte 1 ==
8626 00:44:04.371020 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8627 00:44:04.374043 DramC Write-DBI off
8628 00:44:04.374150
8629 00:44:04.374264 [DATLAT]
8630 00:44:04.374324 Freq=1600, CH1 RK0
8631 00:44:04.374382
8632 00:44:04.377434 DATLAT Default: 0xf
8633 00:44:04.377514 0, 0xFFFF, sum = 0
8634 00:44:04.380808 1, 0xFFFF, sum = 0
8635 00:44:04.384016 2, 0xFFFF, sum = 0
8636 00:44:04.384098 3, 0xFFFF, sum = 0
8637 00:44:04.387122 4, 0xFFFF, sum = 0
8638 00:44:04.387209 5, 0xFFFF, sum = 0
8639 00:44:04.390414 6, 0xFFFF, sum = 0
8640 00:44:04.390509 7, 0xFFFF, sum = 0
8641 00:44:04.393662 8, 0xFFFF, sum = 0
8642 00:44:04.393743 9, 0xFFFF, sum = 0
8643 00:44:04.397201 10, 0xFFFF, sum = 0
8644 00:44:04.397288 11, 0xFFFF, sum = 0
8645 00:44:04.400287 12, 0xFFFF, sum = 0
8646 00:44:04.400369 13, 0xFFFF, sum = 0
8647 00:44:04.403988 14, 0x0, sum = 1
8648 00:44:04.404070 15, 0x0, sum = 2
8649 00:44:04.407199 16, 0x0, sum = 3
8650 00:44:04.407281 17, 0x0, sum = 4
8651 00:44:04.410215 best_step = 15
8652 00:44:04.410296
8653 00:44:04.410359 ==
8654 00:44:04.413501 Dram Type= 6, Freq= 0, CH_1, rank 0
8655 00:44:04.417229 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8656 00:44:04.417310 ==
8657 00:44:04.420170 RX Vref Scan: 1
8658 00:44:04.420251
8659 00:44:04.420313 Set Vref Range= 24 -> 127
8660 00:44:04.420391
8661 00:44:04.423762 RX Vref 24 -> 127, step: 1
8662 00:44:04.423843
8663 00:44:04.426850 RX Delay 11 -> 252, step: 4
8664 00:44:04.426930
8665 00:44:04.430132 Set Vref, RX VrefLevel [Byte0]: 24
8666 00:44:04.433604 [Byte1]: 24
8667 00:44:04.433770
8668 00:44:04.436739 Set Vref, RX VrefLevel [Byte0]: 25
8669 00:44:04.440279 [Byte1]: 25
8670 00:44:04.443759
8671 00:44:04.443933 Set Vref, RX VrefLevel [Byte0]: 26
8672 00:44:04.447003 [Byte1]: 26
8673 00:44:04.451685
8674 00:44:04.451887 Set Vref, RX VrefLevel [Byte0]: 27
8675 00:44:04.454523 [Byte1]: 27
8676 00:44:04.458965
8677 00:44:04.459097 Set Vref, RX VrefLevel [Byte0]: 28
8678 00:44:04.462099 [Byte1]: 28
8679 00:44:04.466738
8680 00:44:04.466908 Set Vref, RX VrefLevel [Byte0]: 29
8681 00:44:04.469881 [Byte1]: 29
8682 00:44:04.474107
8683 00:44:04.474347 Set Vref, RX VrefLevel [Byte0]: 30
8684 00:44:04.477787 [Byte1]: 30
8685 00:44:04.481870
8686 00:44:04.482190 Set Vref, RX VrefLevel [Byte0]: 31
8687 00:44:04.485496 [Byte1]: 31
8688 00:44:04.489404
8689 00:44:04.489812 Set Vref, RX VrefLevel [Byte0]: 32
8690 00:44:04.492760 [Byte1]: 32
8691 00:44:04.497421
8692 00:44:04.497835 Set Vref, RX VrefLevel [Byte0]: 33
8693 00:44:04.500823 [Byte1]: 33
8694 00:44:04.505015
8695 00:44:04.505425 Set Vref, RX VrefLevel [Byte0]: 34
8696 00:44:04.508013 [Byte1]: 34
8697 00:44:04.512563
8698 00:44:04.513122 Set Vref, RX VrefLevel [Byte0]: 35
8699 00:44:04.515705 [Byte1]: 35
8700 00:44:04.520483
8701 00:44:04.520892 Set Vref, RX VrefLevel [Byte0]: 36
8702 00:44:04.523494 [Byte1]: 36
8703 00:44:04.527866
8704 00:44:04.528280 Set Vref, RX VrefLevel [Byte0]: 37
8705 00:44:04.530861 [Byte1]: 37
8706 00:44:04.535527
8707 00:44:04.536003 Set Vref, RX VrefLevel [Byte0]: 38
8708 00:44:04.538535 [Byte1]: 38
8709 00:44:04.543028
8710 00:44:04.543437 Set Vref, RX VrefLevel [Byte0]: 39
8711 00:44:04.546434 [Byte1]: 39
8712 00:44:04.550534
8713 00:44:04.550944 Set Vref, RX VrefLevel [Byte0]: 40
8714 00:44:04.554029 [Byte1]: 40
8715 00:44:04.558260
8716 00:44:04.558677 Set Vref, RX VrefLevel [Byte0]: 41
8717 00:44:04.561566 [Byte1]: 41
8718 00:44:04.565731
8719 00:44:04.566148 Set Vref, RX VrefLevel [Byte0]: 42
8720 00:44:04.568894 [Byte1]: 42
8721 00:44:04.573325
8722 00:44:04.573736 Set Vref, RX VrefLevel [Byte0]: 43
8723 00:44:04.576621 [Byte1]: 43
8724 00:44:04.580758
8725 00:44:04.581380 Set Vref, RX VrefLevel [Byte0]: 44
8726 00:44:04.584197 [Byte1]: 44
8727 00:44:04.588361
8728 00:44:04.588772 Set Vref, RX VrefLevel [Byte0]: 45
8729 00:44:04.592140 [Byte1]: 45
8730 00:44:04.596366
8731 00:44:04.596777 Set Vref, RX VrefLevel [Byte0]: 46
8732 00:44:04.599289 [Byte1]: 46
8733 00:44:04.604157
8734 00:44:04.604574 Set Vref, RX VrefLevel [Byte0]: 47
8735 00:44:04.607257 [Byte1]: 47
8736 00:44:04.611282
8737 00:44:04.611361 Set Vref, RX VrefLevel [Byte0]: 48
8738 00:44:04.614466 [Byte1]: 48
8739 00:44:04.618679
8740 00:44:04.618759 Set Vref, RX VrefLevel [Byte0]: 49
8741 00:44:04.622027 [Byte1]: 49
8742 00:44:04.626445
8743 00:44:04.626525 Set Vref, RX VrefLevel [Byte0]: 50
8744 00:44:04.629533 [Byte1]: 50
8745 00:44:04.634256
8746 00:44:04.634336 Set Vref, RX VrefLevel [Byte0]: 51
8747 00:44:04.637103 [Byte1]: 51
8748 00:44:04.641670
8749 00:44:04.641749 Set Vref, RX VrefLevel [Byte0]: 52
8750 00:44:04.644650 [Byte1]: 52
8751 00:44:04.649712
8752 00:44:04.649875 Set Vref, RX VrefLevel [Byte0]: 53
8753 00:44:04.652387 [Byte1]: 53
8754 00:44:04.657029
8755 00:44:04.657203 Set Vref, RX VrefLevel [Byte0]: 54
8756 00:44:04.660140 [Byte1]: 54
8757 00:44:04.664472
8758 00:44:04.664573 Set Vref, RX VrefLevel [Byte0]: 55
8759 00:44:04.667738 [Byte1]: 55
8760 00:44:04.672218
8761 00:44:04.672631 Set Vref, RX VrefLevel [Byte0]: 56
8762 00:44:04.675538 [Byte1]: 56
8763 00:44:04.679771
8764 00:44:04.680185 Set Vref, RX VrefLevel [Byte0]: 57
8765 00:44:04.683299 [Byte1]: 57
8766 00:44:04.687363
8767 00:44:04.687812 Set Vref, RX VrefLevel [Byte0]: 58
8768 00:44:04.690760 [Byte1]: 58
8769 00:44:04.695210
8770 00:44:04.695635 Set Vref, RX VrefLevel [Byte0]: 59
8771 00:44:04.698671 [Byte1]: 59
8772 00:44:04.702921
8773 00:44:04.703333 Set Vref, RX VrefLevel [Byte0]: 60
8774 00:44:04.706086 [Byte1]: 60
8775 00:44:04.710467
8776 00:44:04.710548 Set Vref, RX VrefLevel [Byte0]: 61
8777 00:44:04.713765 [Byte1]: 61
8778 00:44:04.718035
8779 00:44:04.718116 Set Vref, RX VrefLevel [Byte0]: 62
8780 00:44:04.720768 [Byte1]: 62
8781 00:44:04.725197
8782 00:44:04.725277 Set Vref, RX VrefLevel [Byte0]: 63
8783 00:44:04.728346 [Byte1]: 63
8784 00:44:04.732788
8785 00:44:04.732868 Set Vref, RX VrefLevel [Byte0]: 64
8786 00:44:04.736266 [Byte1]: 64
8787 00:44:04.740995
8788 00:44:04.741076 Set Vref, RX VrefLevel [Byte0]: 65
8789 00:44:04.743717 [Byte1]: 65
8790 00:44:04.748197
8791 00:44:04.748277 Set Vref, RX VrefLevel [Byte0]: 66
8792 00:44:04.751582 [Byte1]: 66
8793 00:44:04.755526
8794 00:44:04.755605 Set Vref, RX VrefLevel [Byte0]: 67
8795 00:44:04.758854 [Byte1]: 67
8796 00:44:04.763291
8797 00:44:04.763370 Set Vref, RX VrefLevel [Byte0]: 68
8798 00:44:04.766538 [Byte1]: 68
8799 00:44:04.770949
8800 00:44:04.771030 Set Vref, RX VrefLevel [Byte0]: 69
8801 00:44:04.774391 [Byte1]: 69
8802 00:44:04.778762
8803 00:44:04.778842 Set Vref, RX VrefLevel [Byte0]: 70
8804 00:44:04.781595 [Byte1]: 70
8805 00:44:04.785928
8806 00:44:04.786009 Set Vref, RX VrefLevel [Byte0]: 71
8807 00:44:04.789476 [Byte1]: 71
8808 00:44:04.793800
8809 00:44:04.793880 Set Vref, RX VrefLevel [Byte0]: 72
8810 00:44:04.797124 [Byte1]: 72
8811 00:44:04.801214
8812 00:44:04.801294 Set Vref, RX VrefLevel [Byte0]: 73
8813 00:44:04.804896 [Byte1]: 73
8814 00:44:04.808882
8815 00:44:04.808970 Final RX Vref Byte 0 = 55 to rank0
8816 00:44:04.812461 Final RX Vref Byte 1 = 58 to rank0
8817 00:44:04.815678 Final RX Vref Byte 0 = 55 to rank1
8818 00:44:04.818874 Final RX Vref Byte 1 = 58 to rank1==
8819 00:44:04.822430 Dram Type= 6, Freq= 0, CH_1, rank 0
8820 00:44:04.828549 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8821 00:44:04.828631 ==
8822 00:44:04.828695 DQS Delay:
8823 00:44:04.831989 DQS0 = 0, DQS1 = 0
8824 00:44:04.832070 DQM Delay:
8825 00:44:04.835354 DQM0 = 133, DQM1 = 127
8826 00:44:04.835434 DQ Delay:
8827 00:44:04.838474 DQ0 =140, DQ1 =128, DQ2 =122, DQ3 =130
8828 00:44:04.841684 DQ4 =132, DQ5 =146, DQ6 =144, DQ7 =128
8829 00:44:04.845208 DQ8 =114, DQ9 =116, DQ10 =130, DQ11 =116
8830 00:44:04.848784 DQ12 =136, DQ13 =136, DQ14 =136, DQ15 =138
8831 00:44:04.848865
8832 00:44:04.848929
8833 00:44:04.848987
8834 00:44:04.851614 [DramC_TX_OE_Calibration] TA2
8835 00:44:04.855026 Original DQ_B0 (3 6) =30, OEN = 27
8836 00:44:04.858500 Original DQ_B1 (3 6) =30, OEN = 27
8837 00:44:04.861673 24, 0x0, End_B0=24 End_B1=24
8838 00:44:04.864590 25, 0x0, End_B0=25 End_B1=25
8839 00:44:04.864672 26, 0x0, End_B0=26 End_B1=26
8840 00:44:04.868134 27, 0x0, End_B0=27 End_B1=27
8841 00:44:04.871523 28, 0x0, End_B0=28 End_B1=28
8842 00:44:04.874741 29, 0x0, End_B0=29 End_B1=29
8843 00:44:04.874823 30, 0x0, End_B0=30 End_B1=30
8844 00:44:04.877911 31, 0x4141, End_B0=30 End_B1=30
8845 00:44:04.881282 Byte0 end_step=30 best_step=27
8846 00:44:04.884631 Byte1 end_step=30 best_step=27
8847 00:44:04.887985 Byte0 TX OE(2T, 0.5T) = (3, 3)
8848 00:44:04.891270 Byte1 TX OE(2T, 0.5T) = (3, 3)
8849 00:44:04.891351
8850 00:44:04.891431
8851 00:44:04.897773 [DQSOSCAuto] RK0, (LSB)MR18= 0x190e, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 397 ps
8852 00:44:04.901291 CH1 RK0: MR19=303, MR18=190E
8853 00:44:04.907638 CH1_RK0: MR19=0x303, MR18=0x190E, DQSOSC=397, MR23=63, INC=23, DEC=15
8854 00:44:04.907725
8855 00:44:04.911190 ----->DramcWriteLeveling(PI) begin...
8856 00:44:04.911272 ==
8857 00:44:04.914195 Dram Type= 6, Freq= 0, CH_1, rank 1
8858 00:44:04.918109 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8859 00:44:04.918228 ==
8860 00:44:04.921156 Write leveling (Byte 0): 24 => 24
8861 00:44:04.924381 Write leveling (Byte 1): 28 => 28
8862 00:44:04.927584 DramcWriteLeveling(PI) end<-----
8863 00:44:04.927664
8864 00:44:04.927727 ==
8865 00:44:04.931006 Dram Type= 6, Freq= 0, CH_1, rank 1
8866 00:44:04.937252 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8867 00:44:04.937333 ==
8868 00:44:04.937396 [Gating] SW mode calibration
8869 00:44:04.947473 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8870 00:44:04.950547 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8871 00:44:04.953817 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8872 00:44:04.960839 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8873 00:44:04.964609 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8874 00:44:04.967577 1 4 12 | B1->B0 | 3434 2323 | 1 1 | (1 1) (1 1)
8875 00:44:04.973836 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8876 00:44:04.977494 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8877 00:44:04.980864 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8878 00:44:04.986978 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8879 00:44:04.990258 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8880 00:44:04.993871 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8881 00:44:05.000537 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8882 00:44:05.003844 1 5 12 | B1->B0 | 2525 3434 | 0 1 | (0 0) (1 0)
8883 00:44:05.007025 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
8884 00:44:05.013538 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8885 00:44:05.017048 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8886 00:44:05.020636 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8887 00:44:05.027002 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8888 00:44:05.030540 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8889 00:44:05.033786 1 6 8 | B1->B0 | 2b2b 2323 | 1 0 | (0 0) (0 0)
8890 00:44:05.040600 1 6 12 | B1->B0 | 4646 2929 | 0 1 | (0 0) (0 0)
8891 00:44:05.043508 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8892 00:44:05.046635 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8893 00:44:05.053214 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8894 00:44:05.056304 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8895 00:44:05.059861 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8896 00:44:05.066824 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8897 00:44:05.069567 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8898 00:44:05.073236 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8899 00:44:05.079450 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8900 00:44:05.083568 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8901 00:44:05.086210 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8902 00:44:05.092751 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8903 00:44:05.096187 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8904 00:44:05.099348 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8905 00:44:05.105762 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8906 00:44:05.109002 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8907 00:44:05.113080 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8908 00:44:05.119308 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8909 00:44:05.122611 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8910 00:44:05.125802 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8911 00:44:05.132362 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8912 00:44:05.135416 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8913 00:44:05.138650 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8914 00:44:05.145636 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8915 00:44:05.148784 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8916 00:44:05.151922 Total UI for P1: 0, mck2ui 16
8917 00:44:05.155585 best dqsien dly found for B0: ( 1, 9, 12)
8918 00:44:05.158608 Total UI for P1: 0, mck2ui 16
8919 00:44:05.162277 best dqsien dly found for B1: ( 1, 9, 10)
8920 00:44:05.165370 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8921 00:44:05.168621 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8922 00:44:05.169048
8923 00:44:05.172468 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8924 00:44:05.178353 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8925 00:44:05.178772 [Gating] SW calibration Done
8926 00:44:05.179100 ==
8927 00:44:05.182271 Dram Type= 6, Freq= 0, CH_1, rank 1
8928 00:44:05.188463 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8929 00:44:05.188884 ==
8930 00:44:05.189215 RX Vref Scan: 0
8931 00:44:05.189520
8932 00:44:05.191608 RX Vref 0 -> 0, step: 1
8933 00:44:05.192022
8934 00:44:05.194826 RX Delay 0 -> 252, step: 8
8935 00:44:05.198003 iDelay=208, Bit 0, Center 139 (80 ~ 199) 120
8936 00:44:05.201525 iDelay=208, Bit 1, Center 131 (72 ~ 191) 120
8937 00:44:05.204940 iDelay=208, Bit 2, Center 123 (64 ~ 183) 120
8938 00:44:05.211490 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8939 00:44:05.214481 iDelay=208, Bit 4, Center 135 (80 ~ 191) 112
8940 00:44:05.217964 iDelay=208, Bit 5, Center 147 (88 ~ 207) 120
8941 00:44:05.221232 iDelay=208, Bit 6, Center 147 (88 ~ 207) 120
8942 00:44:05.224457 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8943 00:44:05.230774 iDelay=208, Bit 8, Center 115 (56 ~ 175) 120
8944 00:44:05.234287 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8945 00:44:05.237710 iDelay=208, Bit 10, Center 131 (72 ~ 191) 120
8946 00:44:05.241111 iDelay=208, Bit 11, Center 119 (64 ~ 175) 112
8947 00:44:05.247517 iDelay=208, Bit 12, Center 139 (80 ~ 199) 120
8948 00:44:05.250915 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8949 00:44:05.254080 iDelay=208, Bit 14, Center 135 (80 ~ 191) 112
8950 00:44:05.257464 iDelay=208, Bit 15, Center 139 (80 ~ 199) 120
8951 00:44:05.257882 ==
8952 00:44:05.260916 Dram Type= 6, Freq= 0, CH_1, rank 1
8953 00:44:05.267423 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8954 00:44:05.267867 ==
8955 00:44:05.268198 DQS Delay:
8956 00:44:05.268506 DQS0 = 0, DQS1 = 0
8957 00:44:05.270571 DQM Delay:
8958 00:44:05.271006 DQM0 = 136, DQM1 = 129
8959 00:44:05.273938 DQ Delay:
8960 00:44:05.277387 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8961 00:44:05.280396 DQ4 =135, DQ5 =147, DQ6 =147, DQ7 =135
8962 00:44:05.283951 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =119
8963 00:44:05.287011 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =139
8964 00:44:05.287435
8965 00:44:05.287764
8966 00:44:05.288067 ==
8967 00:44:05.290288 Dram Type= 6, Freq= 0, CH_1, rank 1
8968 00:44:05.293636 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8969 00:44:05.296896 ==
8970 00:44:05.297315
8971 00:44:05.297738
8972 00:44:05.298054 TX Vref Scan disable
8973 00:44:05.300400 == TX Byte 0 ==
8974 00:44:05.303673 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8975 00:44:05.306860 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8976 00:44:05.309954 == TX Byte 1 ==
8977 00:44:05.313482 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8978 00:44:05.316825 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8979 00:44:05.320067 ==
8980 00:44:05.323338 Dram Type= 6, Freq= 0, CH_1, rank 1
8981 00:44:05.326738 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8982 00:44:05.327159 ==
8983 00:44:05.339136
8984 00:44:05.342274 TX Vref early break, caculate TX vref
8985 00:44:05.345636 TX Vref=16, minBit 0, minWin=23, winSum=380
8986 00:44:05.349255 TX Vref=18, minBit 0, minWin=23, winSum=392
8987 00:44:05.352740 TX Vref=20, minBit 0, minWin=24, winSum=403
8988 00:44:05.355601 TX Vref=22, minBit 1, minWin=24, winSum=409
8989 00:44:05.359124 TX Vref=24, minBit 0, minWin=25, winSum=414
8990 00:44:05.365616 TX Vref=26, minBit 5, minWin=25, winSum=423
8991 00:44:05.369026 TX Vref=28, minBit 0, minWin=25, winSum=423
8992 00:44:05.372336 TX Vref=30, minBit 0, minWin=24, winSum=416
8993 00:44:05.375824 TX Vref=32, minBit 1, minWin=24, winSum=405
8994 00:44:05.378792 TX Vref=34, minBit 0, minWin=23, winSum=395
8995 00:44:05.385076 [TxChooseVref] Worse bit 5, Min win 25, Win sum 423, Final Vref 26
8996 00:44:05.385563
8997 00:44:05.388697 Final TX Range 0 Vref 26
8998 00:44:05.389117
8999 00:44:05.389447 ==
9000 00:44:05.391962 Dram Type= 6, Freq= 0, CH_1, rank 1
9001 00:44:05.395626 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9002 00:44:05.396048 ==
9003 00:44:05.396419
9004 00:44:05.396744
9005 00:44:05.398775 TX Vref Scan disable
9006 00:44:05.405193 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
9007 00:44:05.405611 == TX Byte 0 ==
9008 00:44:05.408464 u2DelayCellOfst[0]=18 cells (5 PI)
9009 00:44:05.411482 u2DelayCellOfst[1]=14 cells (4 PI)
9010 00:44:05.414969 u2DelayCellOfst[2]=0 cells (0 PI)
9011 00:44:05.418813 u2DelayCellOfst[3]=7 cells (2 PI)
9012 00:44:05.421583 u2DelayCellOfst[4]=7 cells (2 PI)
9013 00:44:05.425044 u2DelayCellOfst[5]=18 cells (5 PI)
9014 00:44:05.428085 u2DelayCellOfst[6]=18 cells (5 PI)
9015 00:44:05.431432 u2DelayCellOfst[7]=3 cells (1 PI)
9016 00:44:05.435047 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
9017 00:44:05.438217 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
9018 00:44:05.441694 == TX Byte 1 ==
9019 00:44:05.444719 u2DelayCellOfst[8]=0 cells (0 PI)
9020 00:44:05.445136 u2DelayCellOfst[9]=7 cells (2 PI)
9021 00:44:05.447912 u2DelayCellOfst[10]=14 cells (4 PI)
9022 00:44:05.451516 u2DelayCellOfst[11]=7 cells (2 PI)
9023 00:44:05.454854 u2DelayCellOfst[12]=14 cells (4 PI)
9024 00:44:05.457868 u2DelayCellOfst[13]=18 cells (5 PI)
9025 00:44:05.461215 u2DelayCellOfst[14]=18 cells (5 PI)
9026 00:44:05.464589 u2DelayCellOfst[15]=18 cells (5 PI)
9027 00:44:05.467905 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
9028 00:44:05.474456 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
9029 00:44:05.474876 DramC Write-DBI on
9030 00:44:05.475204 ==
9031 00:44:05.477749 Dram Type= 6, Freq= 0, CH_1, rank 1
9032 00:44:05.484526 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9033 00:44:05.485099 ==
9034 00:44:05.485489
9035 00:44:05.485799
9036 00:44:05.486093 TX Vref Scan disable
9037 00:44:05.488284 == TX Byte 0 ==
9038 00:44:05.491704 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
9039 00:44:05.494732 == TX Byte 1 ==
9040 00:44:05.498247 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
9041 00:44:05.501423 DramC Write-DBI off
9042 00:44:05.501925
9043 00:44:05.502401 [DATLAT]
9044 00:44:05.502882 Freq=1600, CH1 RK1
9045 00:44:05.503265
9046 00:44:05.504794 DATLAT Default: 0xf
9047 00:44:05.507919 0, 0xFFFF, sum = 0
9048 00:44:05.508340 1, 0xFFFF, sum = 0
9049 00:44:05.511831 2, 0xFFFF, sum = 0
9050 00:44:05.512356 3, 0xFFFF, sum = 0
9051 00:44:05.514825 4, 0xFFFF, sum = 0
9052 00:44:05.515245 5, 0xFFFF, sum = 0
9053 00:44:05.518839 6, 0xFFFF, sum = 0
9054 00:44:05.519364 7, 0xFFFF, sum = 0
9055 00:44:05.521604 8, 0xFFFF, sum = 0
9056 00:44:05.522123 9, 0xFFFF, sum = 0
9057 00:44:05.524718 10, 0xFFFF, sum = 0
9058 00:44:05.525282 11, 0xFFFF, sum = 0
9059 00:44:05.528389 12, 0xFFFF, sum = 0
9060 00:44:05.528958 13, 0xFFFF, sum = 0
9061 00:44:05.531078 14, 0x0, sum = 1
9062 00:44:05.531554 15, 0x0, sum = 2
9063 00:44:05.534433 16, 0x0, sum = 3
9064 00:44:05.534902 17, 0x0, sum = 4
9065 00:44:05.537909 best_step = 15
9066 00:44:05.538453
9067 00:44:05.539016 ==
9068 00:44:05.541552 Dram Type= 6, Freq= 0, CH_1, rank 1
9069 00:44:05.544724 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9070 00:44:05.545288 ==
9071 00:44:05.548163 RX Vref Scan: 0
9072 00:44:05.548678
9073 00:44:05.549053 RX Vref 0 -> 0, step: 1
9074 00:44:05.549390
9075 00:44:05.551080 RX Delay 11 -> 252, step: 4
9076 00:44:05.557868 iDelay=199, Bit 0, Center 140 (87 ~ 194) 108
9077 00:44:05.561219 iDelay=199, Bit 1, Center 128 (75 ~ 182) 108
9078 00:44:05.564397 iDelay=199, Bit 2, Center 122 (67 ~ 178) 112
9079 00:44:05.567656 iDelay=199, Bit 3, Center 130 (79 ~ 182) 104
9080 00:44:05.571018 iDelay=199, Bit 4, Center 134 (79 ~ 190) 112
9081 00:44:05.577516 iDelay=199, Bit 5, Center 146 (95 ~ 198) 104
9082 00:44:05.580869 iDelay=199, Bit 6, Center 144 (91 ~ 198) 108
9083 00:44:05.584448 iDelay=199, Bit 7, Center 130 (79 ~ 182) 104
9084 00:44:05.587721 iDelay=199, Bit 8, Center 114 (59 ~ 170) 112
9085 00:44:05.591147 iDelay=199, Bit 9, Center 114 (59 ~ 170) 112
9086 00:44:05.597495 iDelay=199, Bit 10, Center 126 (71 ~ 182) 112
9087 00:44:05.600624 iDelay=199, Bit 11, Center 118 (67 ~ 170) 104
9088 00:44:05.603774 iDelay=199, Bit 12, Center 136 (83 ~ 190) 108
9089 00:44:05.606939 iDelay=199, Bit 13, Center 136 (83 ~ 190) 108
9090 00:44:05.610512 iDelay=199, Bit 14, Center 134 (79 ~ 190) 112
9091 00:44:05.617213 iDelay=199, Bit 15, Center 138 (83 ~ 194) 112
9092 00:44:05.617628 ==
9093 00:44:05.620739 Dram Type= 6, Freq= 0, CH_1, rank 1
9094 00:44:05.623614 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9095 00:44:05.624093 ==
9096 00:44:05.624387 DQS Delay:
9097 00:44:05.626875 DQS0 = 0, DQS1 = 0
9098 00:44:05.627178 DQM Delay:
9099 00:44:05.630330 DQM0 = 134, DQM1 = 127
9100 00:44:05.630552 DQ Delay:
9101 00:44:05.633207 DQ0 =140, DQ1 =128, DQ2 =122, DQ3 =130
9102 00:44:05.636701 DQ4 =134, DQ5 =146, DQ6 =144, DQ7 =130
9103 00:44:05.639996 DQ8 =114, DQ9 =114, DQ10 =126, DQ11 =118
9104 00:44:05.646326 DQ12 =136, DQ13 =136, DQ14 =134, DQ15 =138
9105 00:44:05.646507
9106 00:44:05.646676
9107 00:44:05.646882
9108 00:44:05.649595 [DramC_TX_OE_Calibration] TA2
9109 00:44:05.649773 Original DQ_B0 (3 6) =30, OEN = 27
9110 00:44:05.653224 Original DQ_B1 (3 6) =30, OEN = 27
9111 00:44:05.656005 24, 0x0, End_B0=24 End_B1=24
9112 00:44:05.659648 25, 0x0, End_B0=25 End_B1=25
9113 00:44:05.663041 26, 0x0, End_B0=26 End_B1=26
9114 00:44:05.666079 27, 0x0, End_B0=27 End_B1=27
9115 00:44:05.666182 28, 0x0, End_B0=28 End_B1=28
9116 00:44:05.669454 29, 0x0, End_B0=29 End_B1=29
9117 00:44:05.672603 30, 0x0, End_B0=30 End_B1=30
9118 00:44:05.676013 31, 0x4141, End_B0=30 End_B1=30
9119 00:44:05.679508 Byte0 end_step=30 best_step=27
9120 00:44:05.679589 Byte1 end_step=30 best_step=27
9121 00:44:05.682786 Byte0 TX OE(2T, 0.5T) = (3, 3)
9122 00:44:05.686159 Byte1 TX OE(2T, 0.5T) = (3, 3)
9123 00:44:05.686262
9124 00:44:05.686326
9125 00:44:05.696124 [DQSOSCAuto] RK1, (LSB)MR18= 0xb07, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 404 ps
9126 00:44:05.696206 CH1 RK1: MR19=303, MR18=B07
9127 00:44:05.702465 CH1_RK1: MR19=0x303, MR18=0xB07, DQSOSC=404, MR23=63, INC=22, DEC=15
9128 00:44:05.705941 [RxdqsGatingPostProcess] freq 1600
9129 00:44:05.712181 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9130 00:44:05.715654 best DQS0 dly(2T, 0.5T) = (1, 1)
9131 00:44:05.718876 best DQS1 dly(2T, 0.5T) = (1, 1)
9132 00:44:05.722380 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9133 00:44:05.725634 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9134 00:44:05.725714 best DQS0 dly(2T, 0.5T) = (1, 1)
9135 00:44:05.729143 best DQS1 dly(2T, 0.5T) = (1, 1)
9136 00:44:05.732219 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9137 00:44:05.735435 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9138 00:44:05.738868 Pre-setting of DQS Precalculation
9139 00:44:05.745749 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9140 00:44:05.752157 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9141 00:44:05.758409 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9142 00:44:05.758491
9143 00:44:05.758555
9144 00:44:05.761869 [Calibration Summary] 3200 Mbps
9145 00:44:05.761950 CH 0, Rank 0
9146 00:44:05.765112 SW Impedance : PASS
9147 00:44:05.768840 DUTY Scan : NO K
9148 00:44:05.768921 ZQ Calibration : PASS
9149 00:44:05.772010 Jitter Meter : NO K
9150 00:44:05.775371 CBT Training : PASS
9151 00:44:05.775453 Write leveling : PASS
9152 00:44:05.778589 RX DQS gating : PASS
9153 00:44:05.781873 RX DQ/DQS(RDDQC) : PASS
9154 00:44:05.781993 TX DQ/DQS : PASS
9155 00:44:05.785094 RX DATLAT : PASS
9156 00:44:05.788485 RX DQ/DQS(Engine): PASS
9157 00:44:05.788567 TX OE : PASS
9158 00:44:05.792014 All Pass.
9159 00:44:05.792096
9160 00:44:05.792160 CH 0, Rank 1
9161 00:44:05.794948 SW Impedance : PASS
9162 00:44:05.795029 DUTY Scan : NO K
9163 00:44:05.798406 ZQ Calibration : PASS
9164 00:44:05.801846 Jitter Meter : NO K
9165 00:44:05.801928 CBT Training : PASS
9166 00:44:05.804775 Write leveling : PASS
9167 00:44:05.808258 RX DQS gating : PASS
9168 00:44:05.808339 RX DQ/DQS(RDDQC) : PASS
9169 00:44:05.812037 TX DQ/DQS : PASS
9170 00:44:05.812119 RX DATLAT : PASS
9171 00:44:05.814856 RX DQ/DQS(Engine): PASS
9172 00:44:05.818364 TX OE : PASS
9173 00:44:05.818446 All Pass.
9174 00:44:05.818510
9175 00:44:05.821240 CH 1, Rank 0
9176 00:44:05.821321 SW Impedance : PASS
9177 00:44:05.824568 DUTY Scan : NO K
9178 00:44:05.824650 ZQ Calibration : PASS
9179 00:44:05.828345 Jitter Meter : NO K
9180 00:44:05.831174 CBT Training : PASS
9181 00:44:05.831255 Write leveling : PASS
9182 00:44:05.834873 RX DQS gating : PASS
9183 00:44:05.837727 RX DQ/DQS(RDDQC) : PASS
9184 00:44:05.837809 TX DQ/DQS : PASS
9185 00:44:05.841152 RX DATLAT : PASS
9186 00:44:05.844458 RX DQ/DQS(Engine): PASS
9187 00:44:05.844539 TX OE : PASS
9188 00:44:05.847898 All Pass.
9189 00:44:05.847979
9190 00:44:05.848042 CH 1, Rank 1
9191 00:44:05.851156 SW Impedance : PASS
9192 00:44:05.851237 DUTY Scan : NO K
9193 00:44:05.854092 ZQ Calibration : PASS
9194 00:44:05.857664 Jitter Meter : NO K
9195 00:44:05.857746 CBT Training : PASS
9196 00:44:05.860714 Write leveling : PASS
9197 00:44:05.864260 RX DQS gating : PASS
9198 00:44:05.864341 RX DQ/DQS(RDDQC) : PASS
9199 00:44:05.867460 TX DQ/DQS : PASS
9200 00:44:05.870758 RX DATLAT : PASS
9201 00:44:05.870839 RX DQ/DQS(Engine): PASS
9202 00:44:05.874021 TX OE : PASS
9203 00:44:05.874103 All Pass.
9204 00:44:05.874191
9205 00:44:05.877229 DramC Write-DBI on
9206 00:44:05.880761 PER_BANK_REFRESH: Hybrid Mode
9207 00:44:05.880842 TX_TRACKING: ON
9208 00:44:05.890744 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9209 00:44:05.897176 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9210 00:44:05.903994 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9211 00:44:05.907332 [FAST_K] Save calibration result to emmc
9212 00:44:05.910344 sync common calibartion params.
9213 00:44:05.913555 sync cbt_mode0:1, 1:1
9214 00:44:05.916964 dram_init: ddr_geometry: 2
9215 00:44:05.917070 dram_init: ddr_geometry: 2
9216 00:44:05.920434 dram_init: ddr_geometry: 2
9217 00:44:05.923745 0:dram_rank_size:100000000
9218 00:44:05.926737 1:dram_rank_size:100000000
9219 00:44:05.929994 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9220 00:44:05.933417 DFS_SHUFFLE_HW_MODE: ON
9221 00:44:05.936953 dramc_set_vcore_voltage set vcore to 725000
9222 00:44:05.940153 Read voltage for 1600, 0
9223 00:44:05.940225 Vio18 = 0
9224 00:44:05.940285 Vcore = 725000
9225 00:44:05.943727 Vdram = 0
9226 00:44:05.943830 Vddq = 0
9227 00:44:05.943918 Vmddr = 0
9228 00:44:05.946887 switch to 3200 Mbps bootup
9229 00:44:05.949854 [DramcRunTimeConfig]
9230 00:44:05.949958 PHYPLL
9231 00:44:05.950047 DPM_CONTROL_AFTERK: ON
9232 00:44:05.953240 PER_BANK_REFRESH: ON
9233 00:44:05.956597 REFRESH_OVERHEAD_REDUCTION: ON
9234 00:44:05.956704 CMD_PICG_NEW_MODE: OFF
9235 00:44:05.959938 XRTWTW_NEW_MODE: ON
9236 00:44:05.963137 XRTRTR_NEW_MODE: ON
9237 00:44:05.963236 TX_TRACKING: ON
9238 00:44:05.966516 RDSEL_TRACKING: OFF
9239 00:44:05.966596 DQS Precalculation for DVFS: ON
9240 00:44:05.969833 RX_TRACKING: OFF
9241 00:44:05.969938 HW_GATING DBG: ON
9242 00:44:05.972972 ZQCS_ENABLE_LP4: ON
9243 00:44:05.976534 RX_PICG_NEW_MODE: ON
9244 00:44:05.976627 TX_PICG_NEW_MODE: ON
9245 00:44:05.980083 ENABLE_RX_DCM_DPHY: ON
9246 00:44:05.982939 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9247 00:44:05.983072 DUMMY_READ_FOR_TRACKING: OFF
9248 00:44:05.986124 !!! SPM_CONTROL_AFTERK: OFF
9249 00:44:05.989688 !!! SPM could not control APHY
9250 00:44:05.992986 IMPEDANCE_TRACKING: ON
9251 00:44:05.993107 TEMP_SENSOR: ON
9252 00:44:05.996274 HW_SAVE_FOR_SR: OFF
9253 00:44:05.999426 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9254 00:44:06.002888 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9255 00:44:06.002969 Read ODT Tracking: ON
9256 00:44:06.005932 Refresh Rate DeBounce: ON
9257 00:44:06.009328 DFS_NO_QUEUE_FLUSH: ON
9258 00:44:06.012647 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9259 00:44:06.012728 ENABLE_DFS_RUNTIME_MRW: OFF
9260 00:44:06.016072 DDR_RESERVE_NEW_MODE: ON
9261 00:44:06.019271 MR_CBT_SWITCH_FREQ: ON
9262 00:44:06.019352 =========================
9263 00:44:06.039305 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9264 00:44:06.042318 dram_init: ddr_geometry: 2
9265 00:44:06.061384 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9266 00:44:06.064372 dram_init: dram init end (result: 0)
9267 00:44:06.070863 DRAM-K: Full calibration passed in 24643 msecs
9268 00:44:06.074114 MRC: failed to locate region type 0.
9269 00:44:06.074583 DRAM rank0 size:0x100000000,
9270 00:44:06.077520 DRAM rank1 size=0x100000000
9271 00:44:06.087881 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9272 00:44:06.094001 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9273 00:44:06.100733 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9274 00:44:06.107909 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9275 00:44:06.110638 DRAM rank0 size:0x100000000,
9276 00:44:06.113843 DRAM rank1 size=0x100000000
9277 00:44:06.114305 CBMEM:
9278 00:44:06.117514 IMD: root @ 0xfffff000 254 entries.
9279 00:44:06.120314 IMD: root @ 0xffffec00 62 entries.
9280 00:44:06.124037 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9281 00:44:06.130603 WARNING: RO_VPD is uninitialized or empty.
9282 00:44:06.134131 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9283 00:44:06.141122 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9284 00:44:06.154124 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9285 00:44:06.165543 BS: romstage times (exec / console): total (unknown) / 24133 ms
9286 00:44:06.165965
9287 00:44:06.166394
9288 00:44:06.175113 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9289 00:44:06.178253 ARM64: Exception handlers installed.
9290 00:44:06.181839 ARM64: Testing exception
9291 00:44:06.184960 ARM64: Done test exception
9292 00:44:06.185377 Enumerating buses...
9293 00:44:06.188466 Show all devs... Before device enumeration.
9294 00:44:06.191466 Root Device: enabled 1
9295 00:44:06.194888 CPU_CLUSTER: 0: enabled 1
9296 00:44:06.195306 CPU: 00: enabled 1
9297 00:44:06.198351 Compare with tree...
9298 00:44:06.198771 Root Device: enabled 1
9299 00:44:06.201620 CPU_CLUSTER: 0: enabled 1
9300 00:44:06.205265 CPU: 00: enabled 1
9301 00:44:06.205684 Root Device scanning...
9302 00:44:06.208472 scan_static_bus for Root Device
9303 00:44:06.211504 CPU_CLUSTER: 0 enabled
9304 00:44:06.214892 scan_static_bus for Root Device done
9305 00:44:06.217904 scan_bus: bus Root Device finished in 8 msecs
9306 00:44:06.218363 done
9307 00:44:06.224492 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9308 00:44:06.227800 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9309 00:44:06.234535 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9310 00:44:06.238140 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9311 00:44:06.241095 Allocating resources...
9312 00:44:06.244475 Reading resources...
9313 00:44:06.247846 Root Device read_resources bus 0 link: 0
9314 00:44:06.250862 DRAM rank0 size:0x100000000,
9315 00:44:06.251280 DRAM rank1 size=0x100000000
9316 00:44:06.257615 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9317 00:44:06.258030 CPU: 00 missing read_resources
9318 00:44:06.264492 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9319 00:44:06.267833 Root Device read_resources bus 0 link: 0 done
9320 00:44:06.271111 Done reading resources.
9321 00:44:06.274140 Show resources in subtree (Root Device)...After reading.
9322 00:44:06.277320 Root Device child on link 0 CPU_CLUSTER: 0
9323 00:44:06.280795 CPU_CLUSTER: 0 child on link 0 CPU: 00
9324 00:44:06.290242 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9325 00:44:06.290674 CPU: 00
9326 00:44:06.297095 Root Device assign_resources, bus 0 link: 0
9327 00:44:06.300840 CPU_CLUSTER: 0 missing set_resources
9328 00:44:06.303411 Root Device assign_resources, bus 0 link: 0 done
9329 00:44:06.306884 Done setting resources.
9330 00:44:06.310069 Show resources in subtree (Root Device)...After assigning values.
9331 00:44:06.313709 Root Device child on link 0 CPU_CLUSTER: 0
9332 00:44:06.320045 CPU_CLUSTER: 0 child on link 0 CPU: 00
9333 00:44:06.326627 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9334 00:44:06.329833 CPU: 00
9335 00:44:06.330304 Done allocating resources.
9336 00:44:06.336248 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9337 00:44:06.336688 Enabling resources...
9338 00:44:06.339805 done.
9339 00:44:06.342850 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9340 00:44:06.346343 Initializing devices...
9341 00:44:06.346759 Root Device init
9342 00:44:06.349268 init hardware done!
9343 00:44:06.352708 0x00000018: ctrlr->caps
9344 00:44:06.353158 52.000 MHz: ctrlr->f_max
9345 00:44:06.355982 0.400 MHz: ctrlr->f_min
9346 00:44:06.359538 0x40ff8080: ctrlr->voltages
9347 00:44:06.359961 sclk: 390625
9348 00:44:06.360288 Bus Width = 1
9349 00:44:06.362728 sclk: 390625
9350 00:44:06.363141 Bus Width = 1
9351 00:44:06.365943 Early init status = 3
9352 00:44:06.369102 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9353 00:44:06.373648 in-header: 03 fc 00 00 01 00 00 00
9354 00:44:06.376606 in-data: 00
9355 00:44:06.380399 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9356 00:44:06.385906 in-header: 03 fd 00 00 00 00 00 00
9357 00:44:06.389589 in-data:
9358 00:44:06.392075 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9359 00:44:06.400097 in-header: 03 fc 00 00 01 00 00 00
9360 00:44:06.400595 in-data: 00
9361 00:44:06.403014 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9362 00:44:06.409082 in-header: 03 fd 00 00 00 00 00 00
9363 00:44:06.411973 in-data:
9364 00:44:06.415415 [SSUSB] Setting up USB HOST controller...
9365 00:44:06.418446 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9366 00:44:06.421762 [SSUSB] phy power-on done.
9367 00:44:06.424943 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9368 00:44:06.431680 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9369 00:44:06.434751 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9370 00:44:06.441645 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9371 00:44:06.448105 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9372 00:44:06.454885 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9373 00:44:06.461479 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9374 00:44:06.468006 read SPI 0x705bc 0x1f6a: 923 us, 8712 KB/s, 69.696 Mbps
9375 00:44:06.471120 SPM: binary array size = 0x9dc
9376 00:44:06.474873 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9377 00:44:06.481046 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9378 00:44:06.487502 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9379 00:44:06.494514 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9380 00:44:06.497585 configure_display: Starting display init
9381 00:44:06.531655 anx7625_power_on_init: Init interface.
9382 00:44:06.534917 anx7625_disable_pd_protocol: Disabled PD feature.
9383 00:44:06.538103 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9384 00:44:06.566651 anx7625_start_dp_work: Secure OCM version=00
9385 00:44:06.569701 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9386 00:44:06.584574 sp_tx_get_edid_block: EDID Block = 1
9387 00:44:06.687206 Extracted contents:
9388 00:44:06.690409 header: 00 ff ff ff ff ff ff 00
9389 00:44:06.693663 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9390 00:44:06.696941 version: 01 04
9391 00:44:06.700265 basic params: 95 1f 11 78 0a
9392 00:44:06.703835 chroma info: 76 90 94 55 54 90 27 21 50 54
9393 00:44:06.706916 established: 00 00 00
9394 00:44:06.713638 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9395 00:44:06.716890 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9396 00:44:06.723763 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9397 00:44:06.730234 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9398 00:44:06.736734 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9399 00:44:06.740133 extensions: 00
9400 00:44:06.740554 checksum: fb
9401 00:44:06.740886
9402 00:44:06.743244 Manufacturer: IVO Model 57d Serial Number 0
9403 00:44:06.747031 Made week 0 of 2020
9404 00:44:06.747453 EDID version: 1.4
9405 00:44:06.749779 Digital display
9406 00:44:06.753146 6 bits per primary color channel
9407 00:44:06.753569 DisplayPort interface
9408 00:44:06.756327 Maximum image size: 31 cm x 17 cm
9409 00:44:06.759868 Gamma: 220%
9410 00:44:06.760285 Check DPMS levels
9411 00:44:06.763023 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9412 00:44:06.769887 First detailed timing is preferred timing
9413 00:44:06.770350 Established timings supported:
9414 00:44:06.772943 Standard timings supported:
9415 00:44:06.776292 Detailed timings
9416 00:44:06.779837 Hex of detail: 383680a07038204018303c0035ae10000019
9417 00:44:06.786252 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9418 00:44:06.789484 0780 0798 07c8 0820 hborder 0
9419 00:44:06.792891 0438 043b 0447 0458 vborder 0
9420 00:44:06.796238 -hsync -vsync
9421 00:44:06.796655 Did detailed timing
9422 00:44:06.802793 Hex of detail: 000000000000000000000000000000000000
9423 00:44:06.805718 Manufacturer-specified data, tag 0
9424 00:44:06.809069 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9425 00:44:06.812529 ASCII string: InfoVision
9426 00:44:06.815893 Hex of detail: 000000fe00523134304e574635205248200a
9427 00:44:06.819272 ASCII string: R140NWF5 RH
9428 00:44:06.819693 Checksum
9429 00:44:06.822496 Checksum: 0xfb (valid)
9430 00:44:06.825991 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9431 00:44:06.828807 DSI data_rate: 832800000 bps
9432 00:44:06.835673 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9433 00:44:06.838862 anx7625_parse_edid: pixelclock(138800).
9434 00:44:06.842269 hactive(1920), hsync(48), hfp(24), hbp(88)
9435 00:44:06.845551 vactive(1080), vsync(12), vfp(3), vbp(17)
9436 00:44:06.848852 anx7625_dsi_config: config dsi.
9437 00:44:06.855083 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9438 00:44:06.869139 anx7625_dsi_config: success to config DSI
9439 00:44:06.872525 anx7625_dp_start: MIPI phy setup OK.
9440 00:44:06.875755 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9441 00:44:06.879188 mtk_ddp_mode_set invalid vrefresh 60
9442 00:44:06.882366 main_disp_path_setup
9443 00:44:06.882923 ovl_layer_smi_id_en
9444 00:44:06.885587 ovl_layer_smi_id_en
9445 00:44:06.886246 ccorr_config
9446 00:44:06.886601 aal_config
9447 00:44:06.888785 gamma_config
9448 00:44:06.889200 postmask_config
9449 00:44:06.891902 dither_config
9450 00:44:06.895863 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9451 00:44:06.902135 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9452 00:44:06.905239 Root Device init finished in 554 msecs
9453 00:44:06.908698 CPU_CLUSTER: 0 init
9454 00:44:06.915258 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9455 00:44:06.921818 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9456 00:44:06.922390 APU_MBOX 0x190000b0 = 0x10001
9457 00:44:06.925146 APU_MBOX 0x190001b0 = 0x10001
9458 00:44:06.928701 APU_MBOX 0x190005b0 = 0x10001
9459 00:44:06.931905 APU_MBOX 0x190006b0 = 0x10001
9460 00:44:06.938267 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9461 00:44:06.948176 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9462 00:44:06.960574 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9463 00:44:06.966910 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9464 00:44:06.978816 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9465 00:44:06.988185 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9466 00:44:06.991195 CPU_CLUSTER: 0 init finished in 81 msecs
9467 00:44:06.994702 Devices initialized
9468 00:44:06.997799 Show all devs... After init.
9469 00:44:06.998326 Root Device: enabled 1
9470 00:44:07.001252 CPU_CLUSTER: 0: enabled 1
9471 00:44:07.004358 CPU: 00: enabled 1
9472 00:44:07.007606 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9473 00:44:07.011045 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9474 00:44:07.014148 ELOG: NV offset 0x57f000 size 0x1000
9475 00:44:07.021142 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9476 00:44:07.027483 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9477 00:44:07.030919 ELOG: Event(17) added with size 13 at 2024-06-16 00:44:06 UTC
9478 00:44:07.037284 out: cmd=0x121: 03 db 21 01 00 00 00 00
9479 00:44:07.040718 in-header: 03 21 00 00 2c 00 00 00
9480 00:44:07.054317 in-data: 1b 73 00 00 00 00 00 00 0a 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9481 00:44:07.057311 ELOG: Event(A1) added with size 10 at 2024-06-16 00:44:06 UTC
9482 00:44:07.064001 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
9483 00:44:07.070314 ELOG: Event(A0) added with size 9 at 2024-06-16 00:44:06 UTC
9484 00:44:07.073736 elog_add_boot_reason: Logged dev mode boot
9485 00:44:07.080695 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9486 00:44:07.081113 Finalize devices...
9487 00:44:07.083848 Devices finalized
9488 00:44:07.087188 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9489 00:44:07.090467 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
9490 00:44:07.093763 in-header: 03 07 00 00 08 00 00 00
9491 00:44:07.097049 in-data: aa e4 47 04 13 02 00 00
9492 00:44:07.100536 Chrome EC: UHEPI supported
9493 00:44:07.106980 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
9494 00:44:07.110138 in-header: 03 a9 00 00 08 00 00 00
9495 00:44:07.114037 in-data: 84 60 60 08 00 00 00 00
9496 00:44:07.120138 ELOG: Event(91) added with size 10 at 2024-06-16 00:44:06 UTC
9497 00:44:07.123302 Chrome EC: clear events_b mask to 0x0000000020004000
9498 00:44:07.129837 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
9499 00:44:07.133966 in-header: 03 fd 00 00 00 00 00 00
9500 00:44:07.137681 in-data:
9501 00:44:07.140737 BS: BS_WRITE_TABLES entry times (exec / console): 3 / 46 ms
9502 00:44:07.143921 Writing coreboot table at 0xffe64000
9503 00:44:07.150759 0. 000000000010a000-0000000000113fff: RAMSTAGE
9504 00:44:07.153969 1. 0000000040000000-00000000400fffff: RAM
9505 00:44:07.157329 2. 0000000040100000-000000004032afff: RAMSTAGE
9506 00:44:07.160944 3. 000000004032b000-00000000545fffff: RAM
9507 00:44:07.163810 4. 0000000054600000-000000005465ffff: BL31
9508 00:44:07.167507 5. 0000000054660000-00000000ffe63fff: RAM
9509 00:44:07.173906 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9510 00:44:07.177390 7. 0000000100000000-000000023fffffff: RAM
9511 00:44:07.180412 Passing 5 GPIOs to payload:
9512 00:44:07.183822 NAME | PORT | POLARITY | VALUE
9513 00:44:07.190270 EC in RW | 0x000000aa | low | undefined
9514 00:44:07.193858 EC interrupt | 0x00000005 | low | undefined
9515 00:44:07.200322 TPM interrupt | 0x000000ab | high | undefined
9516 00:44:07.203575 SD card detect | 0x00000011 | high | undefined
9517 00:44:07.206839 speaker enable | 0x00000093 | high | undefined
9518 00:44:07.213261 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9519 00:44:07.216906 in-header: 03 f9 00 00 02 00 00 00
9520 00:44:07.217326 in-data: 02 00
9521 00:44:07.219863 ADC[4]: Raw value=902291 ID=7
9522 00:44:07.223386 ADC[3]: Raw value=213282 ID=1
9523 00:44:07.223804 RAM Code: 0x71
9524 00:44:07.226879 ADC[6]: Raw value=75036 ID=0
9525 00:44:07.230010 ADC[5]: Raw value=212543 ID=1
9526 00:44:07.230449 SKU Code: 0x1
9527 00:44:07.236818 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 8ba8
9528 00:44:07.239674 coreboot table: 964 bytes.
9529 00:44:07.242908 IMD ROOT 0. 0xfffff000 0x00001000
9530 00:44:07.246536 IMD SMALL 1. 0xffffe000 0x00001000
9531 00:44:07.249406 RO MCACHE 2. 0xffffc000 0x00001104
9532 00:44:07.252832 CONSOLE 3. 0xfff7c000 0x00080000
9533 00:44:07.256181 FMAP 4. 0xfff7b000 0x00000452
9534 00:44:07.259435 TIME STAMP 5. 0xfff7a000 0x00000910
9535 00:44:07.262622 VBOOT WORK 6. 0xfff66000 0x00014000
9536 00:44:07.265861 RAMOOPS 7. 0xffe66000 0x00100000
9537 00:44:07.269368 COREBOOT 8. 0xffe64000 0x00002000
9538 00:44:07.269785 IMD small region:
9539 00:44:07.272735 IMD ROOT 0. 0xffffec00 0x00000400
9540 00:44:07.275864 VPD 1. 0xffffeb80 0x0000006c
9541 00:44:07.279479 MMC STATUS 2. 0xffffeb60 0x00000004
9542 00:44:07.286218 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9543 00:44:07.292636 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9544 00:44:07.331241 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9545 00:44:07.334941 Checking segment from ROM address 0x40100000
9546 00:44:07.341232 Checking segment from ROM address 0x4010001c
9547 00:44:07.344550 Loading segment from ROM address 0x40100000
9548 00:44:07.345032 code (compression=0)
9549 00:44:07.354556 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9550 00:44:07.361150 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9551 00:44:07.361556 it's not compressed!
9552 00:44:07.367714 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9553 00:44:07.374431 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9554 00:44:07.391871 Loading segment from ROM address 0x4010001c
9555 00:44:07.392297 Entry Point 0x80000000
9556 00:44:07.395153 Loaded segments
9557 00:44:07.398543 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9558 00:44:07.405033 Jumping to boot code at 0x80000000(0xffe64000)
9559 00:44:07.411674 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9560 00:44:07.418295 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9561 00:44:07.426623 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9562 00:44:07.429790 Checking segment from ROM address 0x40100000
9563 00:44:07.433184 Checking segment from ROM address 0x4010001c
9564 00:44:07.439681 Loading segment from ROM address 0x40100000
9565 00:44:07.440346 code (compression=1)
9566 00:44:07.446355 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9567 00:44:07.455983 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9568 00:44:07.456428 using LZMA
9569 00:44:07.464611 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9570 00:44:07.471643 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9571 00:44:07.474403 Loading segment from ROM address 0x4010001c
9572 00:44:07.477801 Entry Point 0x54601000
9573 00:44:07.478384 Loaded segments
9574 00:44:07.480971 NOTICE: MT8192 bl31_setup
9575 00:44:07.488289 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9576 00:44:07.491686 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9577 00:44:07.494674 WARNING: region 0:
9578 00:44:07.498553 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9579 00:44:07.499201 WARNING: region 1:
9580 00:44:07.505093 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9581 00:44:07.508115 WARNING: region 2:
9582 00:44:07.511208 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9583 00:44:07.514271 WARNING: region 3:
9584 00:44:07.520940 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9585 00:44:07.521485 WARNING: region 4:
9586 00:44:07.527689 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9587 00:44:07.528111 WARNING: region 5:
9588 00:44:07.531128 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9589 00:44:07.534337 WARNING: region 6:
9590 00:44:07.537466 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9591 00:44:07.540854 WARNING: region 7:
9592 00:44:07.544240 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9593 00:44:07.550525 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9594 00:44:07.554083 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9595 00:44:07.560404 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9596 00:44:07.563822 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9597 00:44:07.567139 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9598 00:44:07.573497 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9599 00:44:07.577126 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9600 00:44:07.583179 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9601 00:44:07.586494 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9602 00:44:07.589824 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9603 00:44:07.596423 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9604 00:44:07.599878 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9605 00:44:07.606316 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9606 00:44:07.609719 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9607 00:44:07.613244 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9608 00:44:07.619675 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9609 00:44:07.622925 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9610 00:44:07.626588 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9611 00:44:07.632986 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9612 00:44:07.636138 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9613 00:44:07.642847 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9614 00:44:07.646352 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9615 00:44:07.649579 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9616 00:44:07.656300 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9617 00:44:07.659586 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9618 00:44:07.666234 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9619 00:44:07.669628 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9620 00:44:07.672909 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9621 00:44:07.679783 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9622 00:44:07.682635 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9623 00:44:07.689123 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9624 00:44:07.692776 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9625 00:44:07.695832 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9626 00:44:07.699566 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9627 00:44:07.706237 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9628 00:44:07.709452 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9629 00:44:07.712768 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9630 00:44:07.719224 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9631 00:44:07.722535 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9632 00:44:07.725714 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9633 00:44:07.729340 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9634 00:44:07.735655 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9635 00:44:07.738914 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9636 00:44:07.742127 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9637 00:44:07.745412 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9638 00:44:07.752028 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9639 00:44:07.755790 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9640 00:44:07.759123 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9641 00:44:07.765438 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9642 00:44:07.768396 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9643 00:44:07.775168 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9644 00:44:07.779077 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9645 00:44:07.782108 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9646 00:44:07.788249 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9647 00:44:07.791414 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9648 00:44:07.798053 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9649 00:44:07.801680 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9650 00:44:07.808533 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9651 00:44:07.811566 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9652 00:44:07.814602 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9653 00:44:07.821689 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9654 00:44:07.824627 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9655 00:44:07.831043 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9656 00:44:07.834352 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9657 00:44:07.841309 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9658 00:44:07.844548 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9659 00:44:07.850859 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9660 00:44:07.854130 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9661 00:44:07.860758 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9662 00:44:07.864087 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9663 00:44:07.867241 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9664 00:44:07.874124 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9665 00:44:07.877628 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9666 00:44:07.884389 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9667 00:44:07.887098 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9668 00:44:07.894028 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9669 00:44:07.897126 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9670 00:44:07.904109 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9671 00:44:07.907388 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9672 00:44:07.910446 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9673 00:44:07.916814 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9674 00:44:07.920784 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9675 00:44:07.927109 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9676 00:44:07.930440 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9677 00:44:07.937294 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9678 00:44:07.940268 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9679 00:44:07.943364 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9680 00:44:07.949989 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9681 00:44:07.953646 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9682 00:44:07.960346 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9683 00:44:07.963418 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9684 00:44:07.969825 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9685 00:44:07.973087 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9686 00:44:07.979794 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9687 00:44:07.983430 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9688 00:44:07.989850 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9689 00:44:07.993265 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9690 00:44:07.996710 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9691 00:44:07.999688 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9692 00:44:08.006210 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9693 00:44:08.009486 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9694 00:44:08.013409 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9695 00:44:08.019536 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9696 00:44:08.022788 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9697 00:44:08.029503 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9698 00:44:08.032657 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9699 00:44:08.036049 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9700 00:44:08.042566 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9701 00:44:08.046070 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9702 00:44:08.052357 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9703 00:44:08.055945 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9704 00:44:08.059425 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9705 00:44:08.065946 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9706 00:44:08.069097 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9707 00:44:08.075727 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9708 00:44:08.078786 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9709 00:44:08.083168 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9710 00:44:08.086228 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9711 00:44:08.092459 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9712 00:44:08.095726 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9713 00:44:08.099136 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9714 00:44:08.105776 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9715 00:44:08.109080 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9716 00:44:08.112411 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9717 00:44:08.118690 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9718 00:44:08.121924 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9719 00:44:08.125541 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9720 00:44:08.131747 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9721 00:44:08.135166 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9722 00:44:08.141863 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9723 00:44:08.145394 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9724 00:44:08.148569 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9725 00:44:08.155023 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9726 00:44:08.158405 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9727 00:44:08.161665 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9728 00:44:08.168297 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9729 00:44:08.172105 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9730 00:44:08.178268 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9731 00:44:08.182037 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9732 00:44:08.185268 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9733 00:44:08.191714 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9734 00:44:08.194854 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9735 00:44:08.201412 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9736 00:44:08.204680 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9737 00:44:08.208291 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9738 00:44:08.214620 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9739 00:44:08.217804 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9740 00:44:08.224776 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9741 00:44:08.227700 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9742 00:44:08.231044 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9743 00:44:08.237817 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9744 00:44:08.241300 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9745 00:44:08.248260 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9746 00:44:08.251186 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9747 00:44:08.254525 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9748 00:44:08.261068 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9749 00:44:08.264155 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9750 00:44:08.270911 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9751 00:44:08.274694 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9752 00:44:08.278099 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9753 00:44:08.284154 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9754 00:44:08.287295 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9755 00:44:08.293953 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9756 00:44:08.297238 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9757 00:44:08.300641 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9758 00:44:08.307158 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9759 00:44:08.310773 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9760 00:44:08.317372 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9761 00:44:08.320488 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9762 00:44:08.323888 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9763 00:44:08.330447 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9764 00:44:08.333824 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9765 00:44:08.337220 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9766 00:44:08.343789 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9767 00:44:08.346878 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9768 00:44:08.353547 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9769 00:44:08.357036 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9770 00:44:08.363649 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9771 00:44:08.367275 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9772 00:44:08.370069 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9773 00:44:08.376772 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9774 00:44:08.380001 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9775 00:44:08.383614 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9776 00:44:08.389695 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9777 00:44:08.393109 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9778 00:44:08.399649 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9779 00:44:08.403001 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9780 00:44:08.409695 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9781 00:44:08.412900 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9782 00:44:08.416405 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9783 00:44:08.422895 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9784 00:44:08.426107 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9785 00:44:08.432577 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9786 00:44:08.435822 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9787 00:44:08.442544 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9788 00:44:08.445845 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9789 00:44:08.449261 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9790 00:44:08.455704 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9791 00:44:08.459345 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9792 00:44:08.465920 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9793 00:44:08.469132 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9794 00:44:08.472376 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9795 00:44:08.479130 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9796 00:44:08.482108 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9797 00:44:08.488928 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9798 00:44:08.492169 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9799 00:44:08.499031 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9800 00:44:08.502468 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9801 00:44:08.505407 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9802 00:44:08.512120 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9803 00:44:08.515275 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9804 00:44:08.522091 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9805 00:44:08.525501 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9806 00:44:08.531816 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9807 00:44:08.535255 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9808 00:44:08.538795 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9809 00:44:08.545163 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9810 00:44:08.548683 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9811 00:44:08.555366 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9812 00:44:08.558471 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9813 00:44:08.561918 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9814 00:44:08.568608 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9815 00:44:08.571800 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9816 00:44:08.578237 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9817 00:44:08.582062 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9818 00:44:08.588438 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9819 00:44:08.591602 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9820 00:44:08.595017 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9821 00:44:08.601347 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9822 00:44:08.604830 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9823 00:44:08.608114 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9824 00:44:08.611569 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9825 00:44:08.617974 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9826 00:44:08.621482 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9827 00:44:08.625029 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9828 00:44:08.631119 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9829 00:44:08.634659 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9830 00:44:08.641154 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9831 00:44:08.644379 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9832 00:44:08.647653 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9833 00:44:08.654638 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9834 00:44:08.657905 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9835 00:44:08.660782 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9836 00:44:08.667712 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9837 00:44:08.671375 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9838 00:44:08.674496 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9839 00:44:08.680904 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9840 00:44:08.684117 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9841 00:44:08.687668 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9842 00:44:08.694255 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9843 00:44:08.697245 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9844 00:44:08.703924 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9845 00:44:08.707493 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9846 00:44:08.710949 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9847 00:44:08.717171 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9848 00:44:08.720988 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9849 00:44:08.727133 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9850 00:44:08.730552 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9851 00:44:08.733772 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9852 00:44:08.740496 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9853 00:44:08.743454 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9854 00:44:08.746715 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9855 00:44:08.753887 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9856 00:44:08.756967 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9857 00:44:08.759985 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9858 00:44:08.766556 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9859 00:44:08.769930 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9860 00:44:08.776754 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9861 00:44:08.779873 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9862 00:44:08.783575 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9863 00:44:08.786552 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9864 00:44:08.793176 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9865 00:44:08.796306 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9866 00:44:08.799515 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9867 00:44:08.802730 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9868 00:44:08.809647 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9869 00:44:08.812841 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9870 00:44:08.816396 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9871 00:44:08.819350 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9872 00:44:08.826248 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9873 00:44:08.829492 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9874 00:44:08.832589 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9875 00:44:08.839591 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9876 00:44:08.842533 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9877 00:44:08.849586 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9878 00:44:08.852250 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9879 00:44:08.855891 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9880 00:44:08.862356 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9881 00:44:08.865480 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9882 00:44:08.872297 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9883 00:44:08.875339 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9884 00:44:08.878737 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9885 00:44:08.885404 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9886 00:44:08.888416 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9887 00:44:08.894958 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9888 00:44:08.898845 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9889 00:44:08.905167 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9890 00:44:08.908306 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9891 00:44:08.911633 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9892 00:44:08.918651 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9893 00:44:08.921894 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9894 00:44:08.928962 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9895 00:44:08.931708 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9896 00:44:08.938089 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9897 00:44:08.941449 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9898 00:44:08.945117 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9899 00:44:08.951654 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9900 00:44:08.955133 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9901 00:44:08.961342 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9902 00:44:08.964574 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9903 00:44:08.968012 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9904 00:44:08.974543 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9905 00:44:08.977712 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9906 00:44:08.984202 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9907 00:44:08.987817 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9908 00:44:08.990847 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9909 00:44:08.997783 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9910 00:44:09.000977 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9911 00:44:09.007640 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9912 00:44:09.010858 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9913 00:44:09.017699 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9914 00:44:09.020494 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9915 00:44:09.023947 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9916 00:44:09.030592 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9917 00:44:09.033863 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9918 00:44:09.040361 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9919 00:44:09.043854 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9920 00:44:09.050414 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9921 00:44:09.053800 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9922 00:44:09.057074 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9923 00:44:09.063644 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9924 00:44:09.066958 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9925 00:44:09.073440 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9926 00:44:09.076906 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9927 00:44:09.080108 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9928 00:44:09.086668 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9929 00:44:09.090078 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9930 00:44:09.096662 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9931 00:44:09.100062 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9932 00:44:09.103791 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9933 00:44:09.110085 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9934 00:44:09.113682 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9935 00:44:09.120084 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9936 00:44:09.123185 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9937 00:44:09.130041 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9938 00:44:09.133240 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9939 00:44:09.136531 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9940 00:44:09.143060 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9941 00:44:09.146600 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9942 00:44:09.153098 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9943 00:44:09.156268 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9944 00:44:09.159579 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9945 00:44:09.166501 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9946 00:44:09.169744 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9947 00:44:09.176481 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9948 00:44:09.179578 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9949 00:44:09.186211 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9950 00:44:09.189501 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9951 00:44:09.192845 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9952 00:44:09.199493 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9953 00:44:09.202866 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9954 00:44:09.209513 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9955 00:44:09.212573 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9956 00:44:09.219226 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9957 00:44:09.222816 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9958 00:44:09.225980 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9959 00:44:09.232411 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9960 00:44:09.235666 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9961 00:44:09.242093 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9962 00:44:09.245339 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9963 00:44:09.252792 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9964 00:44:09.255542 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9965 00:44:09.261831 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9966 00:44:09.265181 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9967 00:44:09.271860 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9968 00:44:09.275200 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9969 00:44:09.278330 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9970 00:44:09.285103 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9971 00:44:09.288753 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9972 00:44:09.295182 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9973 00:44:09.298494 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9974 00:44:09.305318 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9975 00:44:09.308242 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9976 00:44:09.311747 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9977 00:44:09.318685 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9978 00:44:09.321910 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9979 00:44:09.328938 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9980 00:44:09.331543 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9981 00:44:09.338159 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9982 00:44:09.341940 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9983 00:44:09.348256 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9984 00:44:09.351422 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9985 00:44:09.354600 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9986 00:44:09.361474 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9987 00:44:09.366336 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9988 00:44:09.371431 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9989 00:44:09.374500 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9990 00:44:09.381405 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9991 00:44:09.384429 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9992 00:44:09.387994 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9993 00:44:09.394352 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9994 00:44:09.397888 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9995 00:44:09.404387 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9996 00:44:09.407612 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9997 00:44:09.414625 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9998 00:44:09.417847 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9999 00:44:09.421212 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
10000 00:44:09.427698 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
10001 00:44:09.430722 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
10002 00:44:09.437353 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
10003 00:44:09.440655 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
10004 00:44:09.447199 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
10005 00:44:09.450750 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
10006 00:44:09.457336 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
10007 00:44:09.460525 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
10008 00:44:09.467222 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
10009 00:44:09.470413 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
10010 00:44:09.476720 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
10011 00:44:09.480100 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
10012 00:44:09.486803 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
10013 00:44:09.489953 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
10014 00:44:09.496683 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
10015 00:44:09.500374 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
10016 00:44:09.506897 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
10017 00:44:09.509789 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
10018 00:44:09.516492 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
10019 00:44:09.519781 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
10020 00:44:09.526307 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
10021 00:44:09.529623 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
10022 00:44:09.536243 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
10023 00:44:09.539830 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
10024 00:44:09.546051 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
10025 00:44:09.549297 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
10026 00:44:09.555996 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
10027 00:44:09.559266 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
10028 00:44:09.562538 INFO: [APUAPC] vio 0
10029 00:44:09.566144 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
10030 00:44:09.572576 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
10031 00:44:09.575941 INFO: [APUAPC] D0_APC_0: 0x400510
10032 00:44:09.579642 INFO: [APUAPC] D0_APC_1: 0x0
10033 00:44:09.582866 INFO: [APUAPC] D0_APC_2: 0x1540
10034 00:44:09.583400 INFO: [APUAPC] D0_APC_3: 0x0
10035 00:44:09.585978 INFO: [APUAPC] D1_APC_0: 0xffffffff
10036 00:44:09.589126 INFO: [APUAPC] D1_APC_1: 0xffffffff
10037 00:44:09.592404 INFO: [APUAPC] D1_APC_2: 0x3fffff
10038 00:44:09.595680 INFO: [APUAPC] D1_APC_3: 0x0
10039 00:44:09.598924 INFO: [APUAPC] D2_APC_0: 0xffffffff
10040 00:44:09.602397 INFO: [APUAPC] D2_APC_1: 0xffffffff
10041 00:44:09.605754 INFO: [APUAPC] D2_APC_2: 0x3fffff
10042 00:44:09.609039 INFO: [APUAPC] D2_APC_3: 0x0
10043 00:44:09.612501 INFO: [APUAPC] D3_APC_0: 0xffffffff
10044 00:44:09.615804 INFO: [APUAPC] D3_APC_1: 0xffffffff
10045 00:44:09.619064 INFO: [APUAPC] D3_APC_2: 0x3fffff
10046 00:44:09.622133 INFO: [APUAPC] D3_APC_3: 0x0
10047 00:44:09.625504 INFO: [APUAPC] D4_APC_0: 0xffffffff
10048 00:44:09.628947 INFO: [APUAPC] D4_APC_1: 0xffffffff
10049 00:44:09.632225 INFO: [APUAPC] D4_APC_2: 0x3fffff
10050 00:44:09.635518 INFO: [APUAPC] D4_APC_3: 0x0
10051 00:44:09.638937 INFO: [APUAPC] D5_APC_0: 0xffffffff
10052 00:44:09.642515 INFO: [APUAPC] D5_APC_1: 0xffffffff
10053 00:44:09.645658 INFO: [APUAPC] D5_APC_2: 0x3fffff
10054 00:44:09.648583 INFO: [APUAPC] D5_APC_3: 0x0
10055 00:44:09.652039 INFO: [APUAPC] D6_APC_0: 0xffffffff
10056 00:44:09.655356 INFO: [APUAPC] D6_APC_1: 0xffffffff
10057 00:44:09.658988 INFO: [APUAPC] D6_APC_2: 0x3fffff
10058 00:44:09.662050 INFO: [APUAPC] D6_APC_3: 0x0
10059 00:44:09.665183 INFO: [APUAPC] D7_APC_0: 0xffffffff
10060 00:44:09.668473 INFO: [APUAPC] D7_APC_1: 0xffffffff
10061 00:44:09.672079 INFO: [APUAPC] D7_APC_2: 0x3fffff
10062 00:44:09.675198 INFO: [APUAPC] D7_APC_3: 0x0
10063 00:44:09.678695 INFO: [APUAPC] D8_APC_0: 0xffffffff
10064 00:44:09.682000 INFO: [APUAPC] D8_APC_1: 0xffffffff
10065 00:44:09.685317 INFO: [APUAPC] D8_APC_2: 0x3fffff
10066 00:44:09.688653 INFO: [APUAPC] D8_APC_3: 0x0
10067 00:44:09.691997 INFO: [APUAPC] D9_APC_0: 0xffffffff
10068 00:44:09.695414 INFO: [APUAPC] D9_APC_1: 0xffffffff
10069 00:44:09.698379 INFO: [APUAPC] D9_APC_2: 0x3fffff
10070 00:44:09.701940 INFO: [APUAPC] D9_APC_3: 0x0
10071 00:44:09.705585 INFO: [APUAPC] D10_APC_0: 0xffffffff
10072 00:44:09.708563 INFO: [APUAPC] D10_APC_1: 0xffffffff
10073 00:44:09.711623 INFO: [APUAPC] D10_APC_2: 0x3fffff
10074 00:44:09.714948 INFO: [APUAPC] D10_APC_3: 0x0
10075 00:44:09.718246 INFO: [APUAPC] D11_APC_0: 0xffffffff
10076 00:44:09.721367 INFO: [APUAPC] D11_APC_1: 0xffffffff
10077 00:44:09.724932 INFO: [APUAPC] D11_APC_2: 0x3fffff
10078 00:44:09.728364 INFO: [APUAPC] D11_APC_3: 0x0
10079 00:44:09.731376 INFO: [APUAPC] D12_APC_0: 0xffffffff
10080 00:44:09.734756 INFO: [APUAPC] D12_APC_1: 0xffffffff
10081 00:44:09.738026 INFO: [APUAPC] D12_APC_2: 0x3fffff
10082 00:44:09.741501 INFO: [APUAPC] D12_APC_3: 0x0
10083 00:44:09.745029 INFO: [APUAPC] D13_APC_0: 0xffffffff
10084 00:44:09.748214 INFO: [APUAPC] D13_APC_1: 0xffffffff
10085 00:44:09.751204 INFO: [APUAPC] D13_APC_2: 0x3fffff
10086 00:44:09.754692 INFO: [APUAPC] D13_APC_3: 0x0
10087 00:44:09.757906 INFO: [APUAPC] D14_APC_0: 0xffffffff
10088 00:44:09.761273 INFO: [APUAPC] D14_APC_1: 0xffffffff
10089 00:44:09.764467 INFO: [APUAPC] D14_APC_2: 0x3fffff
10090 00:44:09.767837 INFO: [APUAPC] D14_APC_3: 0x0
10091 00:44:09.771059 INFO: [APUAPC] D15_APC_0: 0xffffffff
10092 00:44:09.774428 INFO: [APUAPC] D15_APC_1: 0xffffffff
10093 00:44:09.777744 INFO: [APUAPC] D15_APC_2: 0x3fffff
10094 00:44:09.781176 INFO: [APUAPC] D15_APC_3: 0x0
10095 00:44:09.784459 INFO: [APUAPC] APC_CON: 0x4
10096 00:44:09.787888 INFO: [NOCDAPC] D0_APC_0: 0x0
10097 00:44:09.790992 INFO: [NOCDAPC] D0_APC_1: 0x0
10098 00:44:09.794328 INFO: [NOCDAPC] D1_APC_0: 0x0
10099 00:44:09.794744 INFO: [NOCDAPC] D1_APC_1: 0xfff
10100 00:44:09.797772 INFO: [NOCDAPC] D2_APC_0: 0x0
10101 00:44:09.800936 INFO: [NOCDAPC] D2_APC_1: 0xfff
10102 00:44:09.804062 INFO: [NOCDAPC] D3_APC_0: 0x0
10103 00:44:09.807652 INFO: [NOCDAPC] D3_APC_1: 0xfff
10104 00:44:09.811249 INFO: [NOCDAPC] D4_APC_0: 0x0
10105 00:44:09.814249 INFO: [NOCDAPC] D4_APC_1: 0xfff
10106 00:44:09.817977 INFO: [NOCDAPC] D5_APC_0: 0x0
10107 00:44:09.820940 INFO: [NOCDAPC] D5_APC_1: 0xfff
10108 00:44:09.824243 INFO: [NOCDAPC] D6_APC_0: 0x0
10109 00:44:09.828117 INFO: [NOCDAPC] D6_APC_1: 0xfff
10110 00:44:09.828642 INFO: [NOCDAPC] D7_APC_0: 0x0
10111 00:44:09.830947 INFO: [NOCDAPC] D7_APC_1: 0xfff
10112 00:44:09.834027 INFO: [NOCDAPC] D8_APC_0: 0x0
10113 00:44:09.837244 INFO: [NOCDAPC] D8_APC_1: 0xfff
10114 00:44:09.840545 INFO: [NOCDAPC] D9_APC_0: 0x0
10115 00:44:09.844057 INFO: [NOCDAPC] D9_APC_1: 0xfff
10116 00:44:09.847752 INFO: [NOCDAPC] D10_APC_0: 0x0
10117 00:44:09.850887 INFO: [NOCDAPC] D10_APC_1: 0xfff
10118 00:44:09.853691 INFO: [NOCDAPC] D11_APC_0: 0x0
10119 00:44:09.857349 INFO: [NOCDAPC] D11_APC_1: 0xfff
10120 00:44:09.860796 INFO: [NOCDAPC] D12_APC_0: 0x0
10121 00:44:09.863723 INFO: [NOCDAPC] D12_APC_1: 0xfff
10122 00:44:09.867370 INFO: [NOCDAPC] D13_APC_0: 0x0
10123 00:44:09.870635 INFO: [NOCDAPC] D13_APC_1: 0xfff
10124 00:44:09.871068 INFO: [NOCDAPC] D14_APC_0: 0x0
10125 00:44:09.873868 INFO: [NOCDAPC] D14_APC_1: 0xfff
10126 00:44:09.877097 INFO: [NOCDAPC] D15_APC_0: 0x0
10127 00:44:09.880150 INFO: [NOCDAPC] D15_APC_1: 0xfff
10128 00:44:09.884266 INFO: [NOCDAPC] APC_CON: 0x4
10129 00:44:09.887111 INFO: [APUAPC] set_apusys_apc done
10130 00:44:09.890478 INFO: [DEVAPC] devapc_init done
10131 00:44:09.893507 INFO: GICv3 without legacy support detected.
10132 00:44:09.900031 INFO: ARM GICv3 driver initialized in EL3
10133 00:44:09.903311 INFO: Maximum SPI INTID supported: 639
10134 00:44:09.906865 INFO: BL31: Initializing runtime services
10135 00:44:09.913247 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10136 00:44:09.916392 INFO: SPM: enable CPC mode
10137 00:44:09.919796 INFO: mcdi ready for mcusys-off-idle and system suspend
10138 00:44:09.926899 INFO: BL31: Preparing for EL3 exit to normal world
10139 00:44:09.929710 INFO: Entry point address = 0x80000000
10140 00:44:09.930133 INFO: SPSR = 0x8
10141 00:44:09.936422
10142 00:44:09.936892
10143 00:44:09.937271
10144 00:44:09.940043 Starting depthcharge on Spherion...
10145 00:44:09.940471
10146 00:44:09.940801 Wipe memory regions:
10147 00:44:09.941232
10148 00:44:09.943765 end: 2.2.3 depthcharge-start (duration 00:00:19) [common]
10149 00:44:09.944572 start: 2.2.4 bootloader-commands (timeout 00:04:26) [common]
10150 00:44:09.945112 Setting prompt string to ['asurada:']
10151 00:44:09.945783 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:26)
10152 00:44:09.946729 [0x00000040000000, 0x00000054600000)
10153 00:44:10.065153
10154 00:44:10.065694 [0x00000054660000, 0x00000080000000)
10155 00:44:10.325779
10156 00:44:10.329002 [0x000000821a7280, 0x000000ffe64000)
10157 00:44:11.070291
10158 00:44:11.070845 [0x00000100000000, 0x00000240000000)
10159 00:44:12.959835
10160 00:44:12.963470 Initializing XHCI USB controller at 0x11200000.
10161 00:44:14.001069
10162 00:44:14.004196 [firmware-asurada-13885.B-collabora] Dec 14 2021 15:21:43
10163 00:44:14.004283
10164 00:44:14.004347
10165 00:44:14.004628 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10167 00:44:14.105022 asurada: tftpboot 192.168.201.1 14368400/tftp-deploy-4dnvlh_0/kernel/image.itb 14368400/tftp-deploy-4dnvlh_0/kernel/cmdline
10168 00:44:14.105200 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10169 00:44:14.105283 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:22)
10170 00:44:14.109430 tftpboot 192.168.201.1 14368400/tftp-deploy-4dnvlh_0/kernel/image.itp-deploy-4dnvlh_0/kernel/cmdline
10171 00:44:14.109516
10172 00:44:14.109580 Waiting for link
10173 00:44:14.267742
10174 00:44:14.267952 R8152: Initializing
10175 00:44:14.268073
10176 00:44:14.271071 Version 6 (ocp_data = 5c30)
10177 00:44:14.271243
10178 00:44:14.274046 R8152: Done initializing
10179 00:44:14.274260
10180 00:44:14.274384 Adding net device
10181 00:44:16.133548
10182 00:44:16.134104 done.
10183 00:44:16.134564
10184 00:44:16.134933 MAC: 00:e0:4c:68:02:81
10185 00:44:16.135276
10186 00:44:16.136670 Sending DHCP discover... done.
10187 00:44:16.137132
10188 00:44:16.139867 Waiting for reply... done.
10189 00:44:16.140453
10190 00:44:16.143170 Sending DHCP request... done.
10191 00:44:16.143631
10192 00:44:16.146216 Waiting for reply... done.
10193 00:44:16.146695
10194 00:44:16.147237 My ip is 192.168.201.14
10195 00:44:16.147599
10196 00:44:16.149854 The DHCP server ip is 192.168.201.1
10197 00:44:16.150368
10198 00:44:16.156788 TFTP server IP predefined by user: 192.168.201.1
10199 00:44:16.157345
10200 00:44:16.162752 Bootfile predefined by user: 14368400/tftp-deploy-4dnvlh_0/kernel/image.itb
10201 00:44:16.163216
10202 00:44:16.163580 Sending tftp read request... done.
10203 00:44:16.165817
10204 00:44:16.172798 Waiting for the transfer...
10205 00:44:16.173362
10206 00:44:16.886631 00000000 ################################################################
10207 00:44:16.887162
10208 00:44:17.572260 00080000 ################################################################
10209 00:44:17.572865
10210 00:44:18.271712 00100000 ################################################################
10211 00:44:18.272224
10212 00:44:18.987702 00180000 ################################################################
10213 00:44:18.988279
10214 00:44:19.692610 00200000 ################################################################
10215 00:44:19.693134
10216 00:44:20.386304 00280000 ################################################################
10217 00:44:20.386821
10218 00:44:21.090276 00300000 ################################################################
10219 00:44:21.090799
10220 00:44:21.800815 00380000 ################################################################
10221 00:44:21.801398
10222 00:44:22.517329 00400000 ################################################################
10223 00:44:22.517889
10224 00:44:23.245622 00480000 ################################################################
10225 00:44:23.246242
10226 00:44:23.932539 00500000 ################################################################
10227 00:44:23.933094
10228 00:44:24.627733 00580000 ################################################################
10229 00:44:24.628256
10230 00:44:25.326648 00600000 ################################################################
10231 00:44:25.327174
10232 00:44:26.031045 00680000 ################################################################
10233 00:44:26.031588
10234 00:44:26.744707 00700000 ################################################################
10235 00:44:26.745280
10236 00:44:27.453657 00780000 ################################################################
10237 00:44:27.454212
10238 00:44:28.088350 00800000 ################################################################
10239 00:44:28.088584
10240 00:44:28.801813 00880000 ################################################################
10241 00:44:28.802462
10242 00:44:29.530154 00900000 ################################################################
10243 00:44:29.530947
10244 00:44:30.238845 00980000 ################################################################
10245 00:44:30.239439
10246 00:44:30.952494 00a00000 ################################################################
10247 00:44:30.952999
10248 00:44:31.668303 00a80000 ################################################################
10249 00:44:31.668853
10250 00:44:32.364739 00b00000 ################################################################
10251 00:44:32.365260
10252 00:44:33.088590 00b80000 ################################################################
10253 00:44:33.089173
10254 00:44:33.814645 00c00000 ################################################################
10255 00:44:33.815372
10256 00:44:34.537155 00c80000 ################################################################
10257 00:44:34.537696
10258 00:44:35.242260 00d00000 ################################################################
10259 00:44:35.242772
10260 00:44:35.934060 00d80000 ################################################################
10261 00:44:35.934630
10262 00:44:36.653680 00e00000 ################################################################
10263 00:44:36.654230
10264 00:44:37.354725 00e80000 ################################################################
10265 00:44:37.355241
10266 00:44:38.079176 00f00000 ################################################################
10267 00:44:38.079782
10268 00:44:38.799146 00f80000 ################################################################
10269 00:44:38.799771
10270 00:44:39.511334 01000000 ################################################################
10271 00:44:39.511871
10272 00:44:40.219526 01080000 ################################################################
10273 00:44:40.220137
10274 00:44:40.922724 01100000 ################################################################
10275 00:44:40.923240
10276 00:44:41.608484 01180000 ################################################################
10277 00:44:41.608996
10278 00:44:42.279910 01200000 ################################################################
10279 00:44:42.280421
10280 00:44:42.975413 01280000 ################################################################
10281 00:44:42.975925
10282 00:44:43.665566 01300000 ################################################################
10283 00:44:43.665716
10284 00:44:44.307954 01380000 ################################################################
10285 00:44:44.308464
10286 00:44:45.006059 01400000 ################################################################
10287 00:44:45.006589
10288 00:44:45.708152 01480000 ################################################################
10289 00:44:45.708660
10290 00:44:46.429173 01500000 ################################################################
10291 00:44:46.429677
10292 00:44:47.138676 01580000 ################################################################
10293 00:44:47.139236
10294 00:44:47.844846 01600000 ################################################################
10295 00:44:47.845358
10296 00:44:48.540244 01680000 ################################################################
10297 00:44:48.540891
10298 00:44:49.242766 01700000 ################################################################
10299 00:44:49.243372
10300 00:44:49.964277 01780000 ################################################################
10301 00:44:49.964804
10302 00:44:50.668150 01800000 ################################################################
10303 00:44:50.668664
10304 00:44:51.378957 01880000 ################################################################
10305 00:44:51.379478
10306 00:44:52.087751 01900000 ################################################################
10307 00:44:52.088270
10308 00:44:52.807166 01980000 ################################################################
10309 00:44:52.807696
10310 00:44:53.523948 01a00000 ################################################################
10311 00:44:53.524522
10312 00:44:54.257417 01a80000 ################################################################
10313 00:44:54.258074
10314 00:44:54.967229 01b00000 ################################################################
10315 00:44:54.967760
10316 00:44:55.693379 01b80000 ################################################################
10317 00:44:55.693895
10318 00:44:56.307335 01c00000 ################################################################
10319 00:44:56.307508
10320 00:44:57.002133 01c80000 ################################################################
10321 00:44:57.002669
10322 00:44:57.661771 01d00000 ################################################################
10323 00:44:57.661940
10324 00:44:58.229297 01d80000 ################################################################
10325 00:44:58.229452
10326 00:44:58.720194 01e00000 ######################################################### done.
10327 00:44:58.720347
10328 00:44:58.723240 The bootfile was 31918322 bytes long.
10329 00:44:58.723324
10330 00:44:58.726486 Sending tftp read request... done.
10331 00:44:58.726583
10332 00:44:58.729559 Waiting for the transfer...
10333 00:44:58.729650
10334 00:44:58.733075 00000000 # done.
10335 00:44:58.733204
10336 00:44:58.739423 Command line loaded dynamically from TFTP file: 14368400/tftp-deploy-4dnvlh_0/kernel/cmdline
10337 00:44:58.739531
10338 00:44:58.762410 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14368400/extract-nfsrootfs-x3fw3_sq,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10339 00:44:58.762559
10340 00:44:58.762630 Loading FIT.
10341 00:44:58.762691
10342 00:44:58.766102 Image ramdisk-1 has 18742656 bytes.
10343 00:44:58.766224
10344 00:44:58.769347 Image fdt-1 has 47258 bytes.
10345 00:44:58.769456
10346 00:44:58.772654 Image kernel-1 has 13126376 bytes.
10347 00:44:58.772740
10348 00:44:58.782306 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10349 00:44:58.782406
10350 00:44:58.799029 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10351 00:44:58.799146
10352 00:44:58.802185 Choosing best match conf-1 for compat google,spherion-rev2.
10353 00:44:58.805497
10354 00:44:58.809201 Connected to device vid:did:rid of 1ae0:0028:00
10355 00:44:58.819242
10356 00:44:58.822538 tpm_get_response: command 0x17b, return code 0x0
10357 00:44:58.822629
10358 00:44:58.825751 ec_init: CrosEC protocol v3 supported (256, 248)
10359 00:44:58.829922
10360 00:44:58.833511 tpm_cleanup: add release locality here.
10361 00:44:58.833597
10362 00:44:58.833661 Shutting down all USB controllers.
10363 00:44:58.836645
10364 00:44:58.836726 Removing current net device
10365 00:44:58.836791
10366 00:44:58.843350 Exiting depthcharge with code 4 at timestamp: 78368556
10367 00:44:58.843436
10368 00:44:58.846583 LZMA decompressing kernel-1 to 0x821a6718
10369 00:44:58.846666
10370 00:44:58.849664 LZMA decompressing kernel-1 to 0x40000000
10371 00:45:00.467724
10372 00:45:00.467876 jumping to kernel
10373 00:45:00.468367 end: 2.2.4 bootloader-commands (duration 00:00:51) [common]
10374 00:45:00.468495 start: 2.2.5 auto-login-action (timeout 00:03:36) [common]
10375 00:45:00.468574 Setting prompt string to ['Linux version [0-9]']
10376 00:45:00.468644 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10377 00:45:00.468722 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10378 00:45:00.551447
10379 00:45:00.554361 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10380 00:45:00.557819 start: 2.2.5.1 login-action (timeout 00:03:36) [common]
10381 00:45:00.557918 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10382 00:45:00.557992 Setting prompt string to []
10383 00:45:00.558096 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10384 00:45:00.558231 Using line separator: #'\n'#
10385 00:45:00.558293 No login prompt set.
10386 00:45:00.558354 Parsing kernel messages
10387 00:45:00.558409 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10388 00:45:00.558517 [login-action] Waiting for messages, (timeout 00:03:36)
10389 00:45:00.558584 Waiting using forced prompt support (timeout 00:01:48)
10390 00:45:00.577486 [ 0.000000] Linux version 6.1.92-cip22 (KernelCI@build-j232175-arm64-gcc-10-defconfig-arm64-chromebook-7lg8d) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sun Jun 16 00:28:47 UTC 2024
10391 00:45:00.580495 [ 0.000000] random: crng init done
10392 00:45:00.587406 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10393 00:45:00.590467 [ 0.000000] efi: UEFI not found.
10394 00:45:00.597164 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10395 00:45:00.607007 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10396 00:45:00.613570 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10397 00:45:00.623772 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10398 00:45:00.630107 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10399 00:45:00.636798 [ 0.000000] printk: bootconsole [mtk8250] enabled
10400 00:45:00.643412 [ 0.000000] NUMA: No NUMA configuration found
10401 00:45:00.649845 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10402 00:45:00.656479 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10403 00:45:00.656664 [ 0.000000] Zone ranges:
10404 00:45:00.662811 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10405 00:45:00.666190 [ 0.000000] DMA32 empty
10406 00:45:00.673051 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10407 00:45:00.676015 [ 0.000000] Movable zone start for each node
10408 00:45:00.679266 [ 0.000000] Early memory node ranges
10409 00:45:00.686407 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10410 00:45:00.692658 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10411 00:45:00.698978 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10412 00:45:00.705587 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10413 00:45:00.712423 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10414 00:45:00.718698 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10415 00:45:00.775204 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10416 00:45:00.781557 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10417 00:45:00.788346 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10418 00:45:00.791420 [ 0.000000] psci: probing for conduit method from DT.
10419 00:45:00.798121 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10420 00:45:00.801089 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10421 00:45:00.808046 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10422 00:45:00.811033 [ 0.000000] psci: SMC Calling Convention v1.2
10423 00:45:00.817839 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10424 00:45:00.821112 [ 0.000000] Detected VIPT I-cache on CPU0
10425 00:45:00.827428 [ 0.000000] CPU features: detected: GIC system register CPU interface
10426 00:45:00.834434 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10427 00:45:00.840616 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10428 00:45:00.847326 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10429 00:45:00.857167 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10430 00:45:00.863899 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10431 00:45:00.866966 [ 0.000000] alternatives: applying boot alternatives
10432 00:45:00.874312 [ 0.000000] Fallback order for Node 0: 0
10433 00:45:00.880620 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10434 00:45:00.884114 [ 0.000000] Policy zone: Normal
10435 00:45:00.907074 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14368400/extract-nfsrootfs-x3fw3_sq,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10436 00:45:00.916836 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10437 00:45:00.927859 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10438 00:45:00.937822 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10439 00:45:00.944238 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10440 00:45:00.947672 <6>[ 0.000000] software IO TLB: area num 8.
10441 00:45:01.004813 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10442 00:45:01.153685 <6>[ 0.000000] Memory: 7945756K/8385536K available (18112K kernel code, 4120K rwdata, 22644K rodata, 8512K init, 616K bss, 407012K reserved, 32768K cma-reserved)
10443 00:45:01.160394 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10444 00:45:01.166497 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10445 00:45:01.170118 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10446 00:45:01.176683 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10447 00:45:01.183297 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10448 00:45:01.186424 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10449 00:45:01.196518 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10450 00:45:01.203275 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10451 00:45:01.209695 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10452 00:45:01.215980 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10453 00:45:01.219258 <6>[ 0.000000] GICv3: 608 SPIs implemented
10454 00:45:01.222638 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10455 00:45:01.229004 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10456 00:45:01.232571 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10457 00:45:01.240024 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10458 00:45:01.252457 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10459 00:45:01.265339 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10460 00:45:01.271736 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10461 00:45:01.280208 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10462 00:45:01.293205 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10463 00:45:01.299898 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10464 00:45:01.306568 <6>[ 0.009233] Console: colour dummy device 80x25
10465 00:45:01.316586 <6>[ 0.013960] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10466 00:45:01.323308 <6>[ 0.024451] pid_max: default: 32768 minimum: 301
10467 00:45:01.326292 <6>[ 0.029354] LSM: Security Framework initializing
10468 00:45:01.332804 <6>[ 0.034291] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10469 00:45:01.342632 <6>[ 0.042153] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10470 00:45:01.352520 <6>[ 0.051571] cblist_init_generic: Setting adjustable number of callback queues.
10471 00:45:01.359171 <6>[ 0.059061] cblist_init_generic: Setting shift to 3 and lim to 1.
10472 00:45:01.365845 <6>[ 0.065400] cblist_init_generic: Setting adjustable number of callback queues.
10473 00:45:01.372501 <6>[ 0.072826] cblist_init_generic: Setting shift to 3 and lim to 1.
10474 00:45:01.375580 <6>[ 0.079225] rcu: Hierarchical SRCU implementation.
10475 00:45:01.382219 <6>[ 0.084241] rcu: Max phase no-delay instances is 1000.
10476 00:45:01.389042 <6>[ 0.091312] EFI services will not be available.
10477 00:45:01.392326 <6>[ 0.096271] smp: Bringing up secondary CPUs ...
10478 00:45:01.401031 <6>[ 0.101319] Detected VIPT I-cache on CPU1
10479 00:45:01.407967 <6>[ 0.101390] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10480 00:45:01.414071 <6>[ 0.101420] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10481 00:45:01.417516 <6>[ 0.101762] Detected VIPT I-cache on CPU2
10482 00:45:01.427212 <6>[ 0.101816] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10483 00:45:01.433796 <6>[ 0.101836] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10484 00:45:01.437195 <6>[ 0.102094] Detected VIPT I-cache on CPU3
10485 00:45:01.443972 <6>[ 0.102140] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10486 00:45:01.450182 <6>[ 0.102154] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10487 00:45:01.453506 <6>[ 0.102459] CPU features: detected: Spectre-v4
10488 00:45:01.460206 <6>[ 0.102465] CPU features: detected: Spectre-BHB
10489 00:45:01.463362 <6>[ 0.102470] Detected PIPT I-cache on CPU4
10490 00:45:01.470340 <6>[ 0.102527] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10491 00:45:01.476487 <6>[ 0.102544] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10492 00:45:01.483215 <6>[ 0.102839] Detected PIPT I-cache on CPU5
10493 00:45:01.489919 <6>[ 0.102902] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10494 00:45:01.496334 <6>[ 0.102918] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10495 00:45:01.499850 <6>[ 0.103200] Detected PIPT I-cache on CPU6
10496 00:45:01.506479 <6>[ 0.103264] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10497 00:45:01.516161 <6>[ 0.103280] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10498 00:45:01.519549 <6>[ 0.103577] Detected PIPT I-cache on CPU7
10499 00:45:01.526221 <6>[ 0.103642] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10500 00:45:01.532546 <6>[ 0.103657] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10501 00:45:01.535913 <6>[ 0.103704] smp: Brought up 1 node, 8 CPUs
10502 00:45:01.542614 <6>[ 0.245052] SMP: Total of 8 processors activated.
10503 00:45:01.545852 <6>[ 0.249973] CPU features: detected: 32-bit EL0 Support
10504 00:45:01.555927 <6>[ 0.255337] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10505 00:45:01.562426 <6>[ 0.264137] CPU features: detected: Common not Private translations
10506 00:45:01.568800 <6>[ 0.270613] CPU features: detected: CRC32 instructions
10507 00:45:01.575729 <6>[ 0.275965] CPU features: detected: RCpc load-acquire (LDAPR)
10508 00:45:01.578857 <6>[ 0.281925] CPU features: detected: LSE atomic instructions
10509 00:45:01.585461 <6>[ 0.287707] CPU features: detected: Privileged Access Never
10510 00:45:01.592382 <6>[ 0.293486] CPU features: detected: RAS Extension Support
10511 00:45:01.598821 <6>[ 0.299095] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10512 00:45:01.601879 <6>[ 0.306312] CPU: All CPU(s) started at EL2
10513 00:45:01.608494 <6>[ 0.310629] alternatives: applying system-wide alternatives
10514 00:45:01.618567 <6>[ 0.321505] devtmpfs: initialized
10515 00:45:01.634438 <6>[ 0.330451] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10516 00:45:01.641108 <6>[ 0.340415] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10517 00:45:01.647166 <6>[ 0.348428] pinctrl core: initialized pinctrl subsystem
10518 00:45:01.650899 <6>[ 0.355116] DMI not present or invalid.
10519 00:45:01.657402 <6>[ 0.359528] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10520 00:45:01.667111 <6>[ 0.366359] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10521 00:45:01.673576 <6>[ 0.373953] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10522 00:45:01.683839 <6>[ 0.382171] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10523 00:45:01.687040 <6>[ 0.390412] audit: initializing netlink subsys (disabled)
10524 00:45:01.696634 <5>[ 0.396102] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10525 00:45:01.703472 <6>[ 0.396822] thermal_sys: Registered thermal governor 'step_wise'
10526 00:45:01.710058 <6>[ 0.404072] thermal_sys: Registered thermal governor 'power_allocator'
10527 00:45:01.713789 <6>[ 0.410326] cpuidle: using governor menu
10528 00:45:01.720099 <6>[ 0.421284] NET: Registered PF_QIPCRTR protocol family
10529 00:45:01.726507 <6>[ 0.426772] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10530 00:45:01.732951 <6>[ 0.433878] ASID allocator initialised with 32768 entries
10531 00:45:01.736354 <6>[ 0.440467] Serial: AMBA PL011 UART driver
10532 00:45:01.746342 <4>[ 0.449320] Trying to register duplicate clock ID: 134
10533 00:45:01.806405 <6>[ 0.512531] KASLR enabled
10534 00:45:01.820951 <6>[ 0.520204] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10535 00:45:01.827457 <6>[ 0.527214] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10536 00:45:01.833940 <6>[ 0.533702] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10537 00:45:01.840300 <6>[ 0.540707] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10538 00:45:01.847308 <6>[ 0.547192] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10539 00:45:01.853855 <6>[ 0.554199] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10540 00:45:01.860224 <6>[ 0.560685] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10541 00:45:01.866945 <6>[ 0.567690] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10542 00:45:01.869915 <6>[ 0.575166] ACPI: Interpreter disabled.
10543 00:45:01.878998 <6>[ 0.581597] iommu: Default domain type: Translated
10544 00:45:01.885179 <6>[ 0.586747] iommu: DMA domain TLB invalidation policy: strict mode
10545 00:45:01.888577 <5>[ 0.593406] SCSI subsystem initialized
10546 00:45:01.895461 <6>[ 0.597651] usbcore: registered new interface driver usbfs
10547 00:45:01.901590 <6>[ 0.603382] usbcore: registered new interface driver hub
10548 00:45:01.904845 <6>[ 0.608935] usbcore: registered new device driver usb
10549 00:45:01.912402 <6>[ 0.615050] pps_core: LinuxPPS API ver. 1 registered
10550 00:45:01.922585 <6>[ 0.620244] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10551 00:45:01.925698 <6>[ 0.629588] PTP clock support registered
10552 00:45:01.928582 <6>[ 0.633825] EDAC MC: Ver: 3.0.0
10553 00:45:01.936283 <6>[ 0.639010] FPGA manager framework
10554 00:45:01.943374 <6>[ 0.642688] Advanced Linux Sound Architecture Driver Initialized.
10555 00:45:01.945996 <6>[ 0.649471] vgaarb: loaded
10556 00:45:01.952453 <6>[ 0.652619] clocksource: Switched to clocksource arch_sys_counter
10557 00:45:01.955903 <5>[ 0.659062] VFS: Disk quotas dquot_6.6.0
10558 00:45:01.962422 <6>[ 0.663250] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10559 00:45:01.965861 <6>[ 0.670445] pnp: PnP ACPI: disabled
10560 00:45:01.974383 <6>[ 0.677178] NET: Registered PF_INET protocol family
10561 00:45:01.984249 <6>[ 0.682772] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10562 00:45:01.995486 <6>[ 0.695112] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10563 00:45:02.005396 <6>[ 0.703928] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10564 00:45:02.012156 <6>[ 0.711898] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10565 00:45:02.021911 <6>[ 0.720599] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10566 00:45:02.028615 <6>[ 0.730352] TCP: Hash tables configured (established 65536 bind 65536)
10567 00:45:02.035755 <6>[ 0.737221] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10568 00:45:02.045187 <6>[ 0.744422] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10569 00:45:02.051586 <6>[ 0.752130] NET: Registered PF_UNIX/PF_LOCAL protocol family
10570 00:45:02.058020 <6>[ 0.758278] RPC: Registered named UNIX socket transport module.
10571 00:45:02.061746 <6>[ 0.764431] RPC: Registered udp transport module.
10572 00:45:02.068170 <6>[ 0.769365] RPC: Registered tcp transport module.
10573 00:45:02.074907 <6>[ 0.774297] RPC: Registered tcp NFSv4.1 backchannel transport module.
10574 00:45:02.077834 <6>[ 0.780962] PCI: CLS 0 bytes, default 64
10575 00:45:02.081434 <6>[ 0.785336] Unpacking initramfs...
10576 00:45:02.090815 <6>[ 0.789055] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10577 00:45:02.097568 <6>[ 0.797681] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10578 00:45:02.104265 <6>[ 0.806484] kvm [1]: IPA Size Limit: 40 bits
10579 00:45:02.107310 <6>[ 0.811011] kvm [1]: GICv3: no GICV resource entry
10580 00:45:02.113709 <6>[ 0.816033] kvm [1]: disabling GICv2 emulation
10581 00:45:02.120228 <6>[ 0.820718] kvm [1]: GIC system register CPU interface enabled
10582 00:45:02.123991 <6>[ 0.826880] kvm [1]: vgic interrupt IRQ18
10583 00:45:02.130410 <6>[ 0.832685] kvm [1]: VHE mode initialized successfully
10584 00:45:02.136784 <5>[ 0.839074] Initialise system trusted keyrings
10585 00:45:02.143404 <6>[ 0.843894] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10586 00:45:02.150902 <6>[ 0.853880] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10587 00:45:02.157730 <5>[ 0.860256] NFS: Registering the id_resolver key type
10588 00:45:02.160950 <5>[ 0.865556] Key type id_resolver registered
10589 00:45:02.167917 <5>[ 0.869972] Key type id_legacy registered
10590 00:45:02.173981 <6>[ 0.874259] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10591 00:45:02.180794 <6>[ 0.881179] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10592 00:45:02.187128 <6>[ 0.888893] 9p: Installing v9fs 9p2000 file system support
10593 00:45:02.223308 <5>[ 0.926236] Key type asymmetric registered
10594 00:45:02.226683 <5>[ 0.930567] Asymmetric key parser 'x509' registered
10595 00:45:02.236428 <6>[ 0.935702] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10596 00:45:02.239873 <6>[ 0.943314] io scheduler mq-deadline registered
10597 00:45:02.243120 <6>[ 0.948073] io scheduler kyber registered
10598 00:45:02.262056 <6>[ 0.965075] EINJ: ACPI disabled.
10599 00:45:02.295667 <4>[ 0.991766] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10600 00:45:02.305403 <4>[ 1.002364] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10601 00:45:02.320255 <6>[ 1.023366] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10602 00:45:02.328248 <6>[ 1.031315] printk: console [ttyS0] disabled
10603 00:45:02.356262 <6>[ 1.055936] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10604 00:45:02.362957 <6>[ 1.065412] printk: console [ttyS0] enabled
10605 00:45:02.366168 <6>[ 1.065412] printk: console [ttyS0] enabled
10606 00:45:02.372816 <6>[ 1.074306] printk: bootconsole [mtk8250] disabled
10607 00:45:02.376041 <6>[ 1.074306] printk: bootconsole [mtk8250] disabled
10608 00:45:02.382727 <6>[ 1.085347] SuperH (H)SCI(F) driver initialized
10609 00:45:02.386022 <6>[ 1.090604] msm_serial: driver initialized
10610 00:45:02.400056 <6>[ 1.099488] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10611 00:45:02.410100 <6>[ 1.108033] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10612 00:45:02.416535 <6>[ 1.116576] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10613 00:45:02.426276 <6>[ 1.125202] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10614 00:45:02.436531 <6>[ 1.133908] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10615 00:45:02.442678 <6>[ 1.142626] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10616 00:45:02.452492 <6>[ 1.151166] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10617 00:45:02.459149 <6>[ 1.159965] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10618 00:45:02.469124 <6>[ 1.168506] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10619 00:45:02.481205 <6>[ 1.184013] loop: module loaded
10620 00:45:02.487665 <6>[ 1.190033] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10621 00:45:02.510102 <4>[ 1.213203] mtk-pmic-keys: Failed to locate of_node [id: -1]
10622 00:45:02.517023 <6>[ 1.219965] megasas: 07.719.03.00-rc1
10623 00:45:02.526804 <6>[ 1.229544] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10624 00:45:02.537216 <6>[ 1.239984] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10625 00:45:02.552759 <6>[ 1.255797] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10626 00:45:02.612462 <6>[ 1.308601] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10627 00:45:02.872252 <6>[ 1.575014] Freeing initrd memory: 18300K
10628 00:45:02.883483 <6>[ 1.586685] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10629 00:45:02.894494 <6>[ 1.597504] tun: Universal TUN/TAP device driver, 1.6
10630 00:45:02.897848 <6>[ 1.603555] thunder_xcv, ver 1.0
10631 00:45:02.901229 <6>[ 1.607061] thunder_bgx, ver 1.0
10632 00:45:02.904445 <6>[ 1.610557] nicpf, ver 1.0
10633 00:45:02.915037 <6>[ 1.614562] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10634 00:45:02.918326 <6>[ 1.622038] hns3: Copyright (c) 2017 Huawei Corporation.
10635 00:45:02.924714 <6>[ 1.627630] hclge is initializing
10636 00:45:02.928148 <6>[ 1.631206] e1000: Intel(R) PRO/1000 Network Driver
10637 00:45:02.934778 <6>[ 1.636337] e1000: Copyright (c) 1999-2006 Intel Corporation.
10638 00:45:02.938281 <6>[ 1.642351] e1000e: Intel(R) PRO/1000 Network Driver
10639 00:45:02.944771 <6>[ 1.647566] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10640 00:45:02.951571 <6>[ 1.653751] igb: Intel(R) Gigabit Ethernet Network Driver
10641 00:45:02.958644 <6>[ 1.659401] igb: Copyright (c) 2007-2014 Intel Corporation.
10642 00:45:02.964670 <6>[ 1.665240] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10643 00:45:02.971386 <6>[ 1.671758] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10644 00:45:02.974702 <6>[ 1.678215] sky2: driver version 1.30
10645 00:45:02.981140 <6>[ 1.683147] usbcore: registered new device driver r8152-cfgselector
10646 00:45:02.987631 <6>[ 1.689683] usbcore: registered new interface driver r8152
10647 00:45:02.994319 <6>[ 1.695497] VFIO - User Level meta-driver version: 0.3
10648 00:45:03.000781 <6>[ 1.703701] usbcore: registered new interface driver usb-storage
10649 00:45:03.007521 <6>[ 1.710144] usbcore: registered new device driver onboard-usb-hub
10650 00:45:03.016380 <6>[ 1.719292] mt6397-rtc mt6359-rtc: registered as rtc0
10651 00:45:03.026284 <6>[ 1.724760] mt6397-rtc mt6359-rtc: setting system clock to 2024-06-16T00:45:02 UTC (1718498702)
10652 00:45:03.029458 <6>[ 1.734321] i2c_dev: i2c /dev entries driver
10653 00:45:03.043146 <4>[ 1.746279] cpu cpu0: supply cpu not found, using dummy regulator
10654 00:45:03.050012 <4>[ 1.752704] cpu cpu1: supply cpu not found, using dummy regulator
10655 00:45:03.056566 <4>[ 1.759110] cpu cpu2: supply cpu not found, using dummy regulator
10656 00:45:03.063133 <4>[ 1.765515] cpu cpu3: supply cpu not found, using dummy regulator
10657 00:45:03.069786 <4>[ 1.771928] cpu cpu4: supply cpu not found, using dummy regulator
10658 00:45:03.076384 <4>[ 1.778328] cpu cpu5: supply cpu not found, using dummy regulator
10659 00:45:03.083154 <4>[ 1.784728] cpu cpu6: supply cpu not found, using dummy regulator
10660 00:45:03.089503 <4>[ 1.791127] cpu cpu7: supply cpu not found, using dummy regulator
10661 00:45:03.108983 <6>[ 1.811776] cpu cpu0: EM: created perf domain
10662 00:45:03.112495 <6>[ 1.816730] cpu cpu4: EM: created perf domain
10663 00:45:03.119131 <6>[ 1.822285] sdhci: Secure Digital Host Controller Interface driver
10664 00:45:03.125830 <6>[ 1.828719] sdhci: Copyright(c) Pierre Ossman
10665 00:45:03.132488 <6>[ 1.833677] Synopsys Designware Multimedia Card Interface Driver
10666 00:45:03.139272 <6>[ 1.840309] sdhci-pltfm: SDHCI platform and OF driver helper
10667 00:45:03.142632 <6>[ 1.840346] mmc0: CQHCI version 5.10
10668 00:45:03.149475 <6>[ 1.850736] ledtrig-cpu: registered to indicate activity on CPUs
10669 00:45:03.155787 <6>[ 1.857518] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10670 00:45:03.162597 <6>[ 1.864574] usbcore: registered new interface driver usbhid
10671 00:45:03.165803 <6>[ 1.870396] usbhid: USB HID core driver
10672 00:45:03.172458 <6>[ 1.874584] spi_master spi0: will run message pump with realtime priority
10673 00:45:03.216895 <6>[ 1.913137] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10674 00:45:03.236130 <6>[ 1.929089] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10675 00:45:03.239501 <6>[ 1.941355] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x17414
10676 00:45:03.248050 <6>[ 1.950697] cros-ec-spi spi0.0: Chrome EC device registered
10677 00:45:03.254636 <6>[ 1.956703] mmc0: Command Queue Engine enabled
10678 00:45:03.260983 <6>[ 1.961424] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10679 00:45:03.264647 <6>[ 1.968884] mmcblk0: mmc0:0001 DA4128 116 GiB
10680 00:45:03.274144 <6>[ 1.977278] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10681 00:45:03.281607 <6>[ 1.984581] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10682 00:45:03.288051 <6>[ 1.990464] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10683 00:45:03.298287 <6>[ 1.995620] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10684 00:45:03.304792 <6>[ 1.996303] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10685 00:45:03.307854 <6>[ 2.006623] NET: Registered PF_PACKET protocol family
10686 00:45:03.314765 <6>[ 2.016907] 9pnet: Installing 9P2000 support
10687 00:45:03.317894 <5>[ 2.021481] Key type dns_resolver registered
10688 00:45:03.324869 <6>[ 2.026477] registered taskstats version 1
10689 00:45:03.328165 <5>[ 2.030860] Loading compiled-in X.509 certificates
10690 00:45:03.356855 <4>[ 2.053031] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10691 00:45:03.366440 <4>[ 2.063765] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10692 00:45:03.380927 <6>[ 2.083898] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10693 00:45:03.388271 <6>[ 2.090947] xhci-mtk 11200000.usb: xHCI Host Controller
10694 00:45:03.394552 <6>[ 2.096473] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10695 00:45:03.404546 <6>[ 2.104331] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10696 00:45:03.411444 <6>[ 2.113765] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10697 00:45:03.418137 <6>[ 2.119935] xhci-mtk 11200000.usb: xHCI Host Controller
10698 00:45:03.424592 <6>[ 2.125425] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10699 00:45:03.431270 <6>[ 2.133080] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10700 00:45:03.438517 <6>[ 2.140965] hub 1-0:1.0: USB hub found
10701 00:45:03.441248 <6>[ 2.144988] hub 1-0:1.0: 1 port detected
10702 00:45:03.451441 <6>[ 2.149287] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10703 00:45:03.454570 <6>[ 2.158021] hub 2-0:1.0: USB hub found
10704 00:45:03.457859 <6>[ 2.162045] hub 2-0:1.0: 1 port detected
10705 00:45:03.465831 <6>[ 2.168964] mtk-msdc 11f70000.mmc: Got CD GPIO
10706 00:45:03.480001 <6>[ 2.179436] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10707 00:45:03.489811 <6>[ 2.187830] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10708 00:45:03.496328 <6>[ 2.196171] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10709 00:45:03.506190 <6>[ 2.204513] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10710 00:45:03.512955 <6>[ 2.212852] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10711 00:45:03.522903 <6>[ 2.221191] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10712 00:45:03.529461 <6>[ 2.229530] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10713 00:45:03.539928 <6>[ 2.237868] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10714 00:45:03.546083 <6>[ 2.246207] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10715 00:45:03.555791 <6>[ 2.254544] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10716 00:45:03.562348 <6>[ 2.262882] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10717 00:45:03.572402 <6>[ 2.271225] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10718 00:45:03.579449 <6>[ 2.279563] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10719 00:45:03.588996 <6>[ 2.287901] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10720 00:45:03.595425 <6>[ 2.296238] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10721 00:45:03.602064 <6>[ 2.305081] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10722 00:45:03.609225 <6>[ 2.312271] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10723 00:45:03.615869 <6>[ 2.319051] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10724 00:45:03.626033 <6>[ 2.325867] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10725 00:45:03.632570 <6>[ 2.332803] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10726 00:45:03.639261 <6>[ 2.339680] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10727 00:45:03.649073 <6>[ 2.348819] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10728 00:45:03.658989 <6>[ 2.357937] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10729 00:45:03.668893 <6>[ 2.367233] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10730 00:45:03.678828 <6>[ 2.376700] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10731 00:45:03.688872 <6>[ 2.386168] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10732 00:45:03.695508 <6>[ 2.395287] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10733 00:45:03.705157 <6>[ 2.404753] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10734 00:45:03.715235 <6>[ 2.413875] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10735 00:45:03.725015 <6>[ 2.423175] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10736 00:45:03.734716 <6>[ 2.433335] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10737 00:45:03.745212 <6>[ 2.445019] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10738 00:45:03.753129 <6>[ 2.456060] Trying to probe devices needed for running init ...
10739 00:45:03.763545 <3>[ 2.463347] mt8192-audio 11210000.syscon:mt8192-afe-pcm: could not get audiosys reset:-517
10740 00:45:03.873690 <6>[ 2.572897] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10741 00:45:04.027585 <6>[ 2.730729] hub 1-1:1.0: USB hub found
10742 00:45:04.031509 <6>[ 2.735249] hub 1-1:1.0: 4 ports detected
10743 00:45:04.042913 <6>[ 2.745957] hub 1-1:1.0: USB hub found
10744 00:45:04.046063 <6>[ 2.750296] hub 1-1:1.0: 4 ports detected
10745 00:45:04.153465 <6>[ 2.853122] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10746 00:45:04.180127 <6>[ 2.882970] hub 2-1:1.0: USB hub found
10747 00:45:04.183113 <6>[ 2.887478] hub 2-1:1.0: 3 ports detected
10748 00:45:04.195760 <6>[ 2.898696] hub 2-1:1.0: USB hub found
10749 00:45:04.198833 <6>[ 2.903204] hub 2-1:1.0: 3 ports detected
10750 00:45:04.365119 <6>[ 3.064935] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10751 00:45:04.497161 <6>[ 3.200229] hub 1-1.4:1.0: USB hub found
10752 00:45:04.500668 <6>[ 3.204833] hub 1-1.4:1.0: 2 ports detected
10753 00:45:04.514997 <6>[ 3.218033] hub 1-1.4:1.0: USB hub found
10754 00:45:04.517984 <6>[ 3.222626] hub 1-1.4:1.0: 2 ports detected
10755 00:45:04.577394 <6>[ 3.277148] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10756 00:45:04.685681 <6>[ 3.385575] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10757 00:45:04.722292 <4>[ 3.421957] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10758 00:45:04.731898 <4>[ 3.431077] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10759 00:45:04.766929 <6>[ 3.470464] r8152 2-1.3:1.0 eth0: v1.12.13
10760 00:45:04.817047 <6>[ 3.516685] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10761 00:45:05.013090 <6>[ 3.712953] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10762 00:45:06.431498 <6>[ 5.135022] r8152 2-1.3:1.0 eth0: carrier on
10763 00:45:09.121297 <5>[ 5.160729] Sending DHCP requests .., OK
10764 00:45:09.127830 <6>[ 7.829073] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.14
10765 00:45:09.131264 <6>[ 7.837368] IP-Config: Complete:
10766 00:45:09.144576 <6>[ 7.840862] device=eth0, hwaddr=00:e0:4c:68:02:81, ipaddr=192.168.201.14, mask=255.255.255.0, gw=192.168.201.1
10767 00:45:09.150643 <6>[ 7.851568] host=mt8192-asurada-spherion-r0-cbg-9, domain=lava-rack, nis-domain=(none)
10768 00:45:09.160614 <6>[ 7.860185] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10769 00:45:09.163959 <6>[ 7.860194] nameserver0=192.168.201.1
10770 00:45:09.167084 <6>[ 7.872337] clk: Disabling unused clocks
10771 00:45:09.170747 <6>[ 7.877853] ALSA device list:
10772 00:45:09.177278 <6>[ 7.881131] No soundcards found.
10773 00:45:09.185297 <6>[ 7.888870] Freeing unused kernel memory: 8512K
10774 00:45:09.188866 <6>[ 7.893820] Run /init as init process
10775 00:45:09.198819 Loading, please wait...
10776 00:45:09.225195 Starting systemd-udevd version 252.22-1~deb12u1
10777 00:45:09.503032 <6>[ 8.203446] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10778 00:45:09.518071 <6>[ 8.218399] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10779 00:45:09.524437 <6>[ 8.221049] remoteproc remoteproc0: scp is available
10780 00:45:09.531221 <6>[ 8.232484] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10781 00:45:09.537781 <6>[ 8.232572] remoteproc remoteproc0: powering up scp
10782 00:45:09.544501 <6>[ 8.240541] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10783 00:45:09.554049 <4>[ 8.241916] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10784 00:45:09.564276 <6>[ 8.246725] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10785 00:45:09.570610 <3>[ 8.248544] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10786 00:45:09.577264 <3>[ 8.248553] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10787 00:45:09.587146 <3>[ 8.248557] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10788 00:45:09.594106 <3>[ 8.248650] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10789 00:45:09.603863 <3>[ 8.248655] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10790 00:45:09.610315 <3>[ 8.248658] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10791 00:45:09.620363 <3>[ 8.248663] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10792 00:45:09.627054 <3>[ 8.248666] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10793 00:45:09.636573 <3>[ 8.248695] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10794 00:45:09.643214 <3>[ 8.248716] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10795 00:45:09.649902 <3>[ 8.248719] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10796 00:45:09.660215 <3>[ 8.248721] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10797 00:45:09.666165 <3>[ 8.248742] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10798 00:45:09.676351 <3>[ 8.248745] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10799 00:45:09.682865 <3>[ 8.248748] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10800 00:45:09.692626 <3>[ 8.248751] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10801 00:45:09.700122 <3>[ 8.248753] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10802 00:45:09.706561 <3>[ 8.248767] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10803 00:45:09.716879 <6>[ 8.254147] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10804 00:45:09.723448 <6>[ 8.262128] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10805 00:45:09.733464 <6>[ 8.262192] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10806 00:45:09.739972 <6>[ 8.262206] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10807 00:45:09.746527 <6>[ 8.262682] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10808 00:45:09.753056 <6>[ 8.271097] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10809 00:45:09.760047 <6>[ 8.306139] mc: Linux media interface: v0.10
10810 00:45:09.766299 <6>[ 8.313568] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10811 00:45:09.773111 <4>[ 8.317547] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10812 00:45:09.782751 <4>[ 8.323495] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10813 00:45:09.789632 <6>[ 8.327811] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10814 00:45:09.796108 <6>[ 8.344282] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10815 00:45:09.806092 <6>[ 8.353083] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10816 00:45:09.812531 <6>[ 8.382231] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10817 00:45:09.822538 <6>[ 8.384572] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10818 00:45:09.825824 <6>[ 8.392595] pci_bus 0000:00: root bus resource [bus 00-ff]
10819 00:45:09.835610 <4>[ 8.394979] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10820 00:45:09.838952 <4>[ 8.394979] Fallback method does not support PEC.
10821 00:45:09.848731 <6>[ 8.404361] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10822 00:45:09.855392 <6>[ 8.404368] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10823 00:45:09.862215 <6>[ 8.408739] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10824 00:45:09.871992 <6>[ 8.408744] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10825 00:45:09.881778 <6>[ 8.410218] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10826 00:45:09.891776 <3>[ 8.410526] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10827 00:45:09.898241 <6>[ 8.411943] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10828 00:45:09.904982 <6>[ 8.416821] remoteproc remoteproc0: remote processor scp is now up
10829 00:45:09.911618 <6>[ 8.424919] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10830 00:45:09.921772 <3>[ 8.433706] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10831 00:45:09.928402 <6>[ 8.441143] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10832 00:45:09.931490 <6>[ 8.441214] pci 0000:00:00.0: supports D1 D2
10833 00:45:09.941414 <6>[ 8.453700] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10834 00:45:09.948071 <6>[ 8.455490] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10835 00:45:09.957893 <6>[ 8.456459] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10836 00:45:09.967638 <6>[ 8.458681] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10837 00:45:09.974229 <6>[ 8.459084] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10838 00:45:09.981090 <6>[ 8.476236] videodev: Linux video capture interface: v2.00
10839 00:45:09.987349 <6>[ 8.483334] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10840 00:45:09.991000 <6>[ 8.514202] Bluetooth: Core ver 2.22
10841 00:45:09.997418 <6>[ 8.520793] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10842 00:45:10.004341 <6>[ 8.529832] NET: Registered PF_BLUETOOTH protocol family
10843 00:45:10.010699 <6>[ 8.529834] Bluetooth: HCI device and connection manager initialized
10844 00:45:10.017029 <6>[ 8.529853] Bluetooth: HCI socket layer initialized
10845 00:45:10.020649 <6>[ 8.529859] Bluetooth: L2CAP socket layer initialized
10846 00:45:10.027313 <6>[ 8.529867] Bluetooth: SCO socket layer initialized
10847 00:45:10.033627 <6>[ 8.564996] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10848 00:45:10.040466 <6>[ 8.565904] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10849 00:45:10.046921 <6>[ 8.572452] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10850 00:45:10.053500 <6>[ 8.572819] usbcore: registered new interface driver btusb
10851 00:45:10.063750 <4>[ 8.573732] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10852 00:45:10.069876 <3>[ 8.573744] Bluetooth: hci0: Failed to load firmware file (-2)
10853 00:45:10.076587 <3>[ 8.573748] Bluetooth: hci0: Failed to set up firmware (-2)
10854 00:45:10.086979 <4>[ 8.573753] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10855 00:45:10.099452 <6>[ 8.583642] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10856 00:45:10.106243 <6>[ 8.590508] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10857 00:45:10.112874 <6>[ 8.599432] usbcore: registered new interface driver uvcvideo
10858 00:45:10.116360 <6>[ 8.607647] pci 0000:01:00.0: supports D1 D2
10859 00:45:10.122943 <6>[ 8.825356] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10860 00:45:10.140408 <6>[ 8.840807] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10861 00:45:10.146713 <6>[ 8.847706] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10862 00:45:10.153634 <6>[ 8.855789] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10863 00:45:10.163072 <6>[ 8.863786] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10864 00:45:10.169877 <6>[ 8.871788] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10865 00:45:10.179707 <6>[ 8.879788] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10866 00:45:10.182913 <6>[ 8.887807] pci 0000:00:00.0: PCI bridge to [bus 01]
10867 00:45:10.192761 <6>[ 8.893025] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10868 00:45:10.199597 <6>[ 8.901149] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10869 00:45:10.206094 <6>[ 8.908008] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10870 00:45:10.212493 <6>[ 8.914773] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10871 00:45:10.234618 <5>[ 8.935332] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10872 00:45:10.255493 <5>[ 8.956277] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10873 00:45:10.261998 <5>[ 8.963867] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10874 00:45:10.271869 <4>[ 8.972381] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10875 00:45:10.278482 <6>[ 8.981283] cfg80211: failed to load regulatory.db
10876 00:45:10.331035 <6>[ 9.031527] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10877 00:45:10.337519 <6>[ 9.039066] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10878 00:45:10.361980 <6>[ 9.065939] mt7921e 0000:01:00.0: ASIC revision: 79610010
10879 00:45:10.465198 <6>[ 9.165663] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10880 00:45:10.468580 <6>[ 9.165663]
10881 00:45:10.482035 Begin: Loading essential drivers ... done.
10882 00:45:10.485209 Begin: Running /scripts/init-premount ... done.
10883 00:45:10.491990 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10884 00:45:10.501716 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10885 00:45:10.505223 Device /sys/class/net/eth0 found
10886 00:45:10.505342 done.
10887 00:45:10.525260 Begin: Waiting up to 180 secs for any network device to become available ... done.
10888 00:45:10.585364 IP-Config: eth0 hardware address 00:e0:4c:68:02:81 mtu 1500 DHCP
10889 00:45:10.677310 IP-Config: eth0 complete (dhcp from 192.168.201.1):
10890 00:45:10.684025 address: 192.168.201.14 broadcast: 192.168.201.255 netmask: 255.255.255.0
10891 00:45:10.690324 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10892 00:45:10.697020 host : mt8192-asurada-spherion-r0-cbg-9
10893 00:45:10.703931 domain : lava-rack
10894 00:45:10.706783 rootserver: 192.168.201.1 rootpath:
10895 00:45:10.709917 filename :
10896 00:45:10.732107 <6>[ 9.432458] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10897 00:45:10.816971 done.
10898 00:45:10.824914 Begin: Running /scripts/nfs-bottom ... done.
10899 00:45:10.841678 Begin: Running /scripts/init-bottom ... done.
10900 00:45:12.210782 <6>[ 10.914776] NET: Registered PF_INET6 protocol family
10901 00:45:12.217899 <6>[ 10.921837] Segment Routing with IPv6
10902 00:45:12.220949 <6>[ 10.925824] In-situ OAM (IOAM) with IPv6
10903 00:45:12.394361 <30>[ 11.072112] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10904 00:45:12.401118 <30>[ 11.105242] systemd[1]: Detected architecture arm64.
10905 00:45:12.410100
10906 00:45:12.413156 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10907 00:45:12.413239
10908 00:45:12.442679 <30>[ 11.146586] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10909 00:45:13.542132 <30>[ 12.242830] systemd[1]: Queued start job for default target graphical.target.
10910 00:45:13.584983 <30>[ 12.285870] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10911 00:45:13.591668 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10912 00:45:13.614190 <30>[ 12.314756] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10913 00:45:13.623869 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10914 00:45:13.641933 <30>[ 12.342687] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10915 00:45:13.651613 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10916 00:45:13.669504 <30>[ 12.370514] systemd[1]: Created slice user.slice - User and Session Slice.
10917 00:45:13.676034 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10918 00:45:13.700131 <30>[ 12.397694] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10919 00:45:13.710037 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10920 00:45:13.727631 <30>[ 12.425160] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10921 00:45:13.734507 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10922 00:45:13.762617 <30>[ 12.453472] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10923 00:45:13.772590 <30>[ 12.473374] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10924 00:45:13.779123 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10925 00:45:13.795998 <30>[ 12.496932] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10926 00:45:13.802740 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10927 00:45:13.820400 <30>[ 12.520962] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10928 00:45:13.830270 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10929 00:45:13.844873 <30>[ 12.549022] systemd[1]: Reached target paths.target - Path Units.
10930 00:45:13.854907 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10931 00:45:13.872780 <30>[ 12.573350] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10932 00:45:13.878909 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10933 00:45:13.892730 <30>[ 12.596922] systemd[1]: Reached target slices.target - Slice Units.
10934 00:45:13.902726 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10935 00:45:13.917197 <30>[ 12.621386] systemd[1]: Reached target swap.target - Swaps.
10936 00:45:13.923890 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10937 00:45:13.945066 <30>[ 12.645384] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10938 00:45:13.954416 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10939 00:45:13.972139 <30>[ 12.673416] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10940 00:45:13.982461 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10941 00:45:14.003222 <30>[ 12.703731] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10942 00:45:14.012293 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10943 00:45:14.029761 <30>[ 12.730397] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10944 00:45:14.039497 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10945 00:45:14.056742 <30>[ 12.757593] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10946 00:45:14.063242 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10947 00:45:14.082100 <30>[ 12.782596] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10948 00:45:14.091393 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10949 00:45:14.111002 <30>[ 12.812020] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10950 00:45:14.120883 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10951 00:45:14.136723 <30>[ 12.837391] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10952 00:45:14.146577 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10953 00:45:14.196933 <30>[ 12.897374] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10954 00:45:14.202892 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10955 00:45:14.215053 <30>[ 12.916026] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10956 00:45:14.221632 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10957 00:45:14.243442 <30>[ 12.944264] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10958 00:45:14.250066 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10959 00:45:14.275206 <30>[ 12.969466] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10960 00:45:14.291000 <30>[ 12.991617] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10961 00:45:14.300491 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10962 00:45:14.321853 <30>[ 13.022631] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10963 00:45:14.331333 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10964 00:45:14.353533 <30>[ 13.054613] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10965 00:45:14.363363 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10966 00:45:14.385878 <30>[ 13.086720] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10967 00:45:14.392276 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10968 00:45:14.402301 <6>[ 13.100341] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10969 00:45:14.402388
10970 00:45:14.425746 <30>[ 13.126596] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10971 00:45:14.435454 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10972 00:45:14.458218 <30>[ 13.158890] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10973 00:45:14.464949 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10974 00:45:14.489857 <30>[ 13.190683] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10975 00:45:14.499648 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kern<6>[ 13.204219] fuse: init (API version 7.37)
10976 00:45:14.502710 el Module loop...
10977 00:45:14.529294 <30>[ 13.230219] systemd[1]: Starting systemd-journald.service - Journal Service...
10978 00:45:14.535741 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10979 00:45:14.569630 <30>[ 13.270373] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10980 00:45:14.575823 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10981 00:45:14.607623 <30>[ 13.305130] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10982 00:45:14.613861 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10983 00:45:14.635792 <30>[ 13.336903] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10984 00:45:14.646000 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10985 00:45:14.670929 <30>[ 13.371491] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10986 00:45:14.687524 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices..<3>[ 13.386604] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10987 00:45:14.687623 .
10988 00:45:14.711184 <30>[ 13.411514] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
10989 00:45:14.717674 <3>[ 13.418129] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10990 00:45:14.727472 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10991 00:45:14.744562 <30>[ 13.445714] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
10992 00:45:14.751259 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10993 00:45:14.763091 <3>[ 13.464451] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10994 00:45:14.773230 <30>[ 13.473686] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
10995 00:45:14.780183 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10996 00:45:14.792790 <3>[ 13.493879] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10997 00:45:14.802831 <30>[ 13.503901] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
10998 00:45:14.812868 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10999 00:45:14.833549 <30>[ 13.534110] systemd[1]: modprobe@configfs.service: Deactivated successfully.
11000 00:45:14.839869 <30>[ 13.542175] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
11001 00:45:14.849784 <3>[ 13.550798] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11002 00:45:14.859811 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
11003 00:45:14.879177 <3>[ 13.580129] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11004 00:45:14.889683 <30>[ 13.590549] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
11005 00:45:14.896030 <30>[ 13.598536] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
11006 00:45:14.905859 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
11007 00:45:14.923461 <3>[ 13.624518] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11008 00:45:14.934325 <30>[ 13.635191] systemd[1]: modprobe@drm.service: Deactivated successfully.
11009 00:45:14.941163 <30>[ 13.642958] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
11010 00:45:14.954340 [[0;32m OK [0m] Finished [0;1;39mmodprobe@d<3>[ 13.653716] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11011 00:45:14.957695 rm.service[0m - Load Kernel Module drm.
11012 00:45:14.978415 <30>[ 13.679131] systemd[1]: modprobe@efi_pstore.service: Deactivated successfully.
11013 00:45:14.988559 <30>[ 13.687591] systemd[1]: Finished modprobe@efi_pstore.service - Load Kernel Module efi_pstore.
11014 00:45:15.001778 [[0;32m OK [0m] Finished [0;1;39mmodprobe@e<3>[ 13.700149] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11015 00:45:15.005058 fi_psto…m - Load Kernel Module efi_pstore.
11016 00:45:15.026108 <30>[ 13.726908] systemd[1]: modprobe@fuse.service: Deactivated successfully.
11017 00:45:15.032618 <30>[ 13.734522] systemd[1]: Finished modprobe@fuse.service - Load Kernel Module fuse.
11018 00:45:15.045801 [[0;32m OK [0m] Finished [0<3>[ 13.744867] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11019 00:45:15.049190 ;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
11020 00:45:15.073246 <30>[ 13.774050] systemd[1]: modprobe@loop.service: Deactivated successfully.
11021 00:45:15.079954 <30>[ 13.782038] systemd[1]: Finished modprobe@loop.service - Load Kernel Module loop.
11022 00:45:15.093340 [[0;32m OK [0m] Finished [0;1;39mmodprobe@l<3>[ 13.793655] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11023 00:45:15.096812 oop.service[0m - Load Kernel Module loop.
11024 00:45:15.113679 <3>[ 13.814768] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11025 00:45:15.130677 <4>[ 13.823570] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
11026 00:45:15.137202 <30>[ 13.824518] systemd[1]: Finished systemd-modules-load.service - Load Kernel Modules.
11027 00:45:15.144349 <3>[ 13.839203] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
11028 00:45:15.154501 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
11029 00:45:15.177089 <30>[ 13.874467] systemd[1]: Finished systemd-network-generator.service - Generate network units from Kernel command line.
11030 00:45:15.183827 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
11031 00:45:15.200285 <30>[ 13.901464] systemd[1]: Started systemd-journald.service - Journal Service.
11032 00:45:15.207027 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
11033 00:45:15.228504 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
11034 00:45:15.245333 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
11035 00:45:15.266751 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
11036 00:45:15.309098 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
11037 00:45:15.333762 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
11038 00:45:15.357773 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
11039 00:45:15.382542 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
11040 00:45:15.410925 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
11041 00:45:15.427520 <46>[ 14.128109] systemd-journald[310]: Received client request to flush runtime journal.
11042 00:45:15.457373 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
11043 00:45:15.575278 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
11044 00:45:15.592487 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
11045 00:45:15.609190 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
11046 00:45:15.629526 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
11047 00:45:16.817510 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
11048 00:45:16.836941 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
11049 00:45:16.876958 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
11050 00:45:16.983790 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
11051 00:45:17.000309 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
11052 00:45:17.019538 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
11053 00:45:17.072655 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
11054 00:45:17.095777 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
11055 00:45:17.413626 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
11056 00:45:17.470142 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
11057 00:45:17.560603 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
11058 00:45:17.758131 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
11059 00:45:17.844799 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
11060 00:45:17.857187 <6>[ 16.561666] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11061 00:45:17.884375 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
11062 00:45:17.971181 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
11063 00:45:17.987729 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
11064 00:45:18.032225 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
11065 00:45:18.064802 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11066 00:45:18.109178 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11067 00:45:18.132890 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
11068 00:45:18.152253 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
11069 00:45:18.172655 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
11070 00:45:18.196194 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11071 00:45:18.230355 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11072 00:45:18.249000 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
11073 00:45:18.268072 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
11074 00:45:18.287857 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
11075 00:45:18.308014 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
11076 00:45:18.331489 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
11077 00:45:18.350845 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
11078 00:45:18.371836 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
11079 00:45:18.390980 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
11080 00:45:18.411156 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
11081 00:45:18.427608 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
11082 00:45:18.446846 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
11083 00:45:18.463510 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
11084 00:45:18.479639 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
11085 00:45:18.513317 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11086 00:45:18.548201 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
11087 00:45:18.656768 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11088 00:45:18.682354 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11089 00:45:18.764664 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11090 00:45:18.828739 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11091 00:45:18.868993 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11092 00:45:18.888172 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11093 00:45:18.908940 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11094 00:45:18.957881 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11095 00:45:19.093777 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
11096 00:45:19.114919 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11097 00:45:19.137053 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11098 00:45:19.203655 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11099 00:45:19.249016 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11100 00:45:19.337809
11101 00:45:19.341438 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11102 00:45:19.341524
11103 00:45:19.344422 debian-bookworm-arm64 login: root (automatic login)
11104 00:45:19.344500
11105 00:45:19.674275 Linux debian-bookworm-arm64 6.1.92-cip22 #1 SMP PREEMPT Sun Jun 16 00:28:47 UTC 2024 aarch64
11106 00:45:19.674419
11107 00:45:19.680864 The programs included with the Debian GNU/Linux system are free software;
11108 00:45:19.687431 the exact distribution terms for each program are described in the
11109 00:45:19.690699 individual files in /usr/share/doc/*/copyright.
11110 00:45:19.690792
11111 00:45:19.697280 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11112 00:45:19.700665 permitted by applicable law.
11113 00:45:20.889968 Matched prompt #10: / #
11115 00:45:20.890297 Setting prompt string to ['/ #']
11116 00:45:20.890393 end: 2.2.5.1 login-action (duration 00:00:20) [common]
11118 00:45:20.890590 end: 2.2.5 auto-login-action (duration 00:00:20) [common]
11119 00:45:20.890677 start: 2.2.6 expect-shell-connection (timeout 00:03:15) [common]
11120 00:45:20.890747 Setting prompt string to ['/ #']
11121 00:45:20.890808 Forcing a shell prompt, looking for ['/ #']
11123 00:45:20.941022 / #
11124 00:45:20.941124 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11125 00:45:20.941214 Waiting using forced prompt support (timeout 00:02:30)
11126 00:45:20.945805
11127 00:45:20.946095 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11128 00:45:20.946262 start: 2.2.7 export-device-env (timeout 00:03:15) [common]
11130 00:45:21.046674 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14368400/extract-nfsrootfs-x3fw3_sq'
11131 00:45:21.052057 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14368400/extract-nfsrootfs-x3fw3_sq'
11133 00:45:21.152638 / # export NFS_SERVER_IP='192.168.201.1'
11134 00:45:21.157928 export NFS_SERVER_IP='192.168.201.1'
11135 00:45:21.158212 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11136 00:45:21.158316 end: 2.2 depthcharge-retry (duration 00:01:45) [common]
11137 00:45:21.158407 end: 2 depthcharge-action (duration 00:01:45) [common]
11138 00:45:21.158497 start: 3 lava-test-retry (timeout 00:07:36) [common]
11139 00:45:21.158580 start: 3.1 lava-test-shell (timeout 00:07:36) [common]
11140 00:45:21.158656 Using namespace: common
11142 00:45:21.259037 / # #
11143 00:45:21.259223 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11144 00:45:21.264357 #
11145 00:45:21.264637 Using /lava-14368400
11147 00:45:21.364984 / # export SHELL=/bin/bash
11148 00:45:21.369809 export SHELL=/bin/bash
11150 00:45:21.470368 / # . /lava-14368400/environment
11151 00:45:21.475390 . /lava-14368400/environment
11153 00:45:21.582259 / # /lava-14368400/bin/lava-test-runner /lava-14368400/0
11154 00:45:21.582448 Test shell timeout: 10s (minimum of the action and connection timeout)
11155 00:45:21.587386 /lava-14368400/bin/lava-test-runner /lava-14368400/0
11156 00:45:21.877840 + export TESTRUN_ID=0_timesync-off
11157 00:45:21.881171 + TESTRUN_ID=0_timesync-off
11158 00:45:21.884872 + cd /lava-14368400/0/tests/0_timesync-off
11159 00:45:21.887661 ++ cat uuid
11160 00:45:21.894716 + UUID=14368400_1.6.2.3.1
11161 00:45:21.894846 + set +x
11162 00:45:21.901328 <LAVA_SIGNAL_STARTRUN 0_timesync-off 14368400_1.6.2.3.1>
11163 00:45:21.901625 Received signal: <STARTRUN> 0_timesync-off 14368400_1.6.2.3.1
11164 00:45:21.901710 Starting test lava.0_timesync-off (14368400_1.6.2.3.1)
11165 00:45:21.901824 Skipping test definition patterns.
11166 00:45:21.904306 + systemctl stop systemd-timesyncd
11167 00:45:21.991021 + set +x
11168 00:45:21.994061 <LAVA_SIGNAL_ENDRUN 0_timesync-off 14368400_1.6.2.3.1>
11169 00:45:21.994378 Received signal: <ENDRUN> 0_timesync-off 14368400_1.6.2.3.1
11170 00:45:21.994469 Ending use of test pattern.
11171 00:45:21.994532 Ending test lava.0_timesync-off (14368400_1.6.2.3.1), duration 0.09
11173 00:45:22.080236 + export TESTRUN_ID=1_kselftest-arm64
11174 00:45:22.080388 + TESTRUN_ID=1_kselftest-arm64
11175 00:45:22.086898 + cd /lava-14368400/0/tests/1_kselftest-arm64
11176 00:45:22.087019 ++ cat uuid
11177 00:45:22.094562 + UUID=14368400_1.6.2.3.5
11178 00:45:22.094765 + set +x
11179 00:45:22.101566 <LAVA_SIGNAL_STARTRUN 1_kselftest-arm64 14368400_1.6.2.3.5>
11180 00:45:22.101869 Received signal: <STARTRUN> 1_kselftest-arm64 14368400_1.6.2.3.5
11181 00:45:22.101948 Starting test lava.1_kselftest-arm64 (14368400_1.6.2.3.5)
11182 00:45:22.102076 Skipping test definition patterns.
11183 00:45:22.104874 + cd ./automated/linux/kselftest/
11184 00:45:22.130560 + ./kselftest.sh -c arm64 -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-24-g0315de64ea248/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11185 00:45:22.185218 INFO: install_deps skipped
11186 00:45:22.700092 --2024-06-16 00:45:22-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-24-g0315de64ea248/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11187 00:45:22.715078 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11188 00:45:22.839994 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11189 00:45:22.965207 HTTP request sent, awaiting response... 200 OK
11190 00:45:22.968344 Length: 1647580 (1.6M) [application/octet-stream]
11191 00:45:22.971823 Saving to: 'kselftest_armhf.tar.gz'
11192 00:45:22.971943
11193 00:45:22.972010
11194 00:45:23.214915 kselftest_armhf.tar 0%[ ] 0 --.-KB/s
11195 00:45:23.465224 kselftest_armhf.tar 2%[ ] 47.81K 192KB/s
11196 00:45:23.760574 kselftest_armhf.tar 13%[=> ] 217.50K 436KB/s
11197 00:45:23.890033 kselftest_armhf.tar 50%[=========> ] 814.23K 1.00MB/s
11198 00:45:23.896220 kselftest_armhf.tar 100%[===================>] 1.57M 1.70MB/s in 0.9s
11199 00:45:23.896383
11200 00:45:24.041458 2024-06-16 00:45:23 (1.70 MB/s) - 'kselftest_armhf.tar.gz' saved [1647580/1647580]
11201 00:45:24.041617
11202 00:45:29.245344 skiplist:
11203 00:45:29.248564 ========================================
11204 00:45:29.252062 ========================================
11205 00:45:29.305504 arm64:tags_test
11206 00:45:29.308306 arm64:run_tags_test.sh
11207 00:45:29.308407 arm64:fake_sigreturn_bad_magic
11208 00:45:29.311469 arm64:fake_sigreturn_bad_size
11209 00:45:29.315010 arm64:fake_sigreturn_bad_size_for_magic0
11210 00:45:29.318259 arm64:fake_sigreturn_duplicated_fpsimd
11211 00:45:29.321416 arm64:fake_sigreturn_misaligned_sp
11212 00:45:29.325203 arm64:fake_sigreturn_missing_fpsimd
11213 00:45:29.328209 arm64:fake_sigreturn_sme_change_vl
11214 00:45:29.331622 arm64:fake_sigreturn_sve_change_vl
11215 00:45:29.334728 arm64:mangle_pstate_invalid_compat_toggle
11216 00:45:29.338013 arm64:mangle_pstate_invalid_daif_bits
11217 00:45:29.341446 arm64:mangle_pstate_invalid_mode_el1h
11218 00:45:29.344497 arm64:mangle_pstate_invalid_mode_el1t
11219 00:45:29.347811 arm64:mangle_pstate_invalid_mode_el2h
11220 00:45:29.351467 arm64:mangle_pstate_invalid_mode_el2t
11221 00:45:29.357838 arm64:mangle_pstate_invalid_mode_el3h
11222 00:45:29.361067 arm64:mangle_pstate_invalid_mode_el3t
11223 00:45:29.361173 arm64:sme_trap_no_sm
11224 00:45:29.364558 arm64:sme_trap_non_streaming
11225 00:45:29.364651 arm64:sme_trap_za
11226 00:45:29.367695 arm64:sme_vl
11227 00:45:29.367787 arm64:ssve_regs
11228 00:45:29.371005 arm64:sve_regs
11229 00:45:29.371095 arm64:sve_vl
11230 00:45:29.371159 arm64:za_no_regs
11231 00:45:29.374072 arm64:za_regs
11232 00:45:29.374156 arm64:pac
11233 00:45:29.377460 arm64:fp-stress
11234 00:45:29.377554 arm64:sve-ptrace
11235 00:45:29.381080 arm64:sve-probe-vls
11236 00:45:29.381180 arm64:vec-syscfg
11237 00:45:29.384183 arm64:za-fork
11238 00:45:29.384271 arm64:za-ptrace
11239 00:45:29.387326 arm64:check_buffer_fill
11240 00:45:29.387417 arm64:check_child_memory
11241 00:45:29.390724 arm64:check_gcr_el1_cswitch
11242 00:45:29.395063 arm64:check_ksm_options
11243 00:45:29.395162 arm64:check_mmap_options
11244 00:45:29.397462 arm64:check_prctl
11245 00:45:29.400797 arm64:check_tags_inclusion
11246 00:45:29.400888 arm64:check_user_mem
11247 00:45:29.404192 arm64:btitest
11248 00:45:29.404278 arm64:nobtitest
11249 00:45:29.404344 arm64:hwcap
11250 00:45:29.407257 arm64:ptrace
11251 00:45:29.407348 arm64:syscall-abi
11252 00:45:29.410744 arm64:tpidr2
11253 00:45:29.413739 ============== Tests to run ===============
11254 00:45:29.413831 arm64:tags_test
11255 00:45:29.417115 arm64:run_tags_test.sh
11256 00:45:29.420835 arm64:fake_sigreturn_bad_magic
11257 00:45:29.423872 arm64:fake_sigreturn_bad_size
11258 00:45:29.426944 arm64:fake_sigreturn_bad_size_for_magic0
11259 00:45:29.430313 arm64:fake_sigreturn_duplicated_fpsimd
11260 00:45:29.433520 arm64:fake_sigreturn_misaligned_sp
11261 00:45:29.437146 arm64:fake_sigreturn_missing_fpsimd
11262 00:45:29.440386 arm64:fake_sigreturn_sme_change_vl
11263 00:45:29.443737 arm64:fake_sigreturn_sve_change_vl
11264 00:45:29.446700 arm64:mangle_pstate_invalid_compat_toggle
11265 00:45:29.450656 arm64:mangle_pstate_invalid_daif_bits
11266 00:45:29.453807 arm64:mangle_pstate_invalid_mode_el1h
11267 00:45:29.456721 arm64:mangle_pstate_invalid_mode_el1t
11268 00:45:29.460042 arm64:mangle_pstate_invalid_mode_el2h
11269 00:45:29.463517 arm64:mangle_pstate_invalid_mode_el2t
11270 00:45:29.466762 arm64:mangle_pstate_invalid_mode_el3h
11271 00:45:29.469836 arm64:mangle_pstate_invalid_mode_el3t
11272 00:45:29.469936 arm64:sme_trap_no_sm
11273 00:45:29.473079 arm64:sme_trap_non_streaming
11274 00:45:29.476706 arm64:sme_trap_za
11275 00:45:29.476882 arm64:sme_vl
11276 00:45:29.480197 arm64:ssve_regs
11277 00:45:29.480300 arm64:sve_regs
11278 00:45:29.480365 arm64:sve_vl
11279 00:45:29.483053 arm64:za_no_regs
11280 00:45:29.483144 arm64:za_regs
11281 00:45:29.483210 arm64:pac
11282 00:45:29.486381 arm64:fp-stress
11283 00:45:29.486473 arm64:sve-ptrace
11284 00:45:29.490088 arm64:sve-probe-vls
11285 00:45:29.490221 arm64:vec-syscfg
11286 00:45:29.492975 arm64:za-fork
11287 00:45:29.493061 arm64:za-ptrace
11288 00:45:29.496344 arm64:check_buffer_fill
11289 00:45:29.499890 arm64:check_child_memory
11290 00:45:29.499987 arm64:check_gcr_el1_cswitch
11291 00:45:29.502718 arm64:check_ksm_options
11292 00:45:29.506062 arm64:check_mmap_options
11293 00:45:29.506180 arm64:check_prctl
11294 00:45:29.509398 arm64:check_tags_inclusion
11295 00:45:29.512968 arm64:check_user_mem
11296 00:45:29.513070 arm64:btitest
11297 00:45:29.513137 arm64:nobtitest
11298 00:45:29.516188 arm64:hwcap
11299 00:45:29.516277 arm64:ptrace
11300 00:45:29.519531 arm64:syscall-abi
11301 00:45:29.519621 arm64:tpidr2
11302 00:45:29.522793 ===========End Tests to run ===============
11303 00:45:29.525963 shardfile-arm64 pass
11304 00:45:29.757508 <12>[ 28.463370] kselftest: Running tests in arm64
11305 00:45:29.767686 TAP version 13
11306 00:45:29.783526 1..48
11307 00:45:29.803359 # selftests: arm64: tags_test
11308 00:45:30.273640 ok 1 selftests: arm64: tags_test
11309 00:45:30.288569 # selftests: arm64: run_tags_test.sh
11310 00:45:30.340737 # --------------------
11311 00:45:30.344293 # running tags test
11312 00:45:30.344383 # --------------------
11313 00:45:30.347649 # [PASS]
11314 00:45:30.350464 ok 2 selftests: arm64: run_tags_test.sh
11315 00:45:30.362362 # selftests: arm64: fake_sigreturn_bad_magic
11316 00:45:30.434082 # Registered handlers for all signals.
11317 00:45:30.434312 # Detected MINSTKSIGSZ:4720
11318 00:45:30.437318 # Testcase initialized.
11319 00:45:30.441202 # uc context validated.
11320 00:45:30.444185 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11321 00:45:30.447197 # Handled SIG_COPYCTX
11322 00:45:30.447307 # Available space:3568
11323 00:45:30.454015 # Using badly built context - ERR: BAD MAGIC !
11324 00:45:30.460728 # SIG_OK -- SP:0xFFFFDB4B1000 si_addr@:0xffffdb4b1000 si_code:2 token@:0xffffdb4afda0 offset:-4704
11325 00:45:30.463688 # ==>> completed. PASS(1)
11326 00:45:30.470783 # # FAKE_SIGRETURN_BAD_MAGIC :: Trigger a sigreturn with a sigframe with a bad magic
11327 00:45:30.477058 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFDB4AFDA0
11328 00:45:30.483750 ok 3 selftests: arm64: fake_sigreturn_bad_magic
11329 00:45:30.486737 # selftests: arm64: fake_sigreturn_bad_size
11330 00:45:30.517615 # Registered handlers for all signals.
11331 00:45:30.517801 # Detected MINSTKSIGSZ:4720
11332 00:45:30.520640 # Testcase initialized.
11333 00:45:30.524293 # uc context validated.
11334 00:45:30.527222 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11335 00:45:30.530581 # Handled SIG_COPYCTX
11336 00:45:30.530706 # Available space:3568
11337 00:45:30.534041 # uc context validated.
11338 00:45:30.540840 # Using badly built context - ERR: Bad size for esr_context
11339 00:45:30.547002 # SIG_OK -- SP:0xFFFFF29F5C00 si_addr@:0xfffff29f5c00 si_code:2 token@:0xfffff29f49a0 offset:-4704
11340 00:45:30.550565 # ==>> completed. PASS(1)
11341 00:45:30.557266 # # FAKE_SIGRETURN_BAD_SIZE :: Triggers a sigreturn with a overrun __reserved area
11342 00:45:30.563778 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFF29F49A0
11343 00:45:30.567014 ok 4 selftests: arm64: fake_sigreturn_bad_size
11344 00:45:30.573991 # selftests: arm64: fake_sigreturn_bad_size_for_magic0
11345 00:45:30.593581 # Registered handlers for all signals.
11346 00:45:30.593770 # Detected MINSTKSIGSZ:4720
11347 00:45:30.596895 # Testcase initialized.
11348 00:45:30.600489 # uc context validated.
11349 00:45:30.603801 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11350 00:45:30.607033 # Handled SIG_COPYCTX
11351 00:45:30.607158 # Available space:3568
11352 00:45:30.613341 # Using badly built context - ERR: Bad size for terminator
11353 00:45:30.623409 # SIG_OK -- SP:0xFFFFE85C6840 si_addr@:0xffffe85c6840 si_code:2 token@:0xffffe85c55e0 offset:-4704
11354 00:45:30.623586 # ==>> completed. PASS(1)
11355 00:45:30.632999 # # FAKE_SIGRETURN_BAD_SIZE_FOR_TERMINATOR :: Trigger a sigreturn using non-zero size terminator
11356 00:45:30.639808 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFE85C55E0
11357 00:45:30.643196 ok 5 selftests: arm64: fake_sigreturn_bad_size_for_magic0
11358 00:45:30.649568 # selftests: arm64: fake_sigreturn_duplicated_fpsimd
11359 00:45:30.673574 # Registered handlers for all signals.
11360 00:45:30.673727 # Detected MINSTKSIGSZ:4720
11361 00:45:30.676983 # Testcase initialized.
11362 00:45:30.680192 # uc context validated.
11363 00:45:30.683579 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11364 00:45:30.686862 # Handled SIG_COPYCTX
11365 00:45:30.686994 # Available space:3568
11366 00:45:30.693626 # Using badly built context - ERR: Multiple FPSIMD_MAGIC
11367 00:45:30.703235 # SIG_OK -- SP:0xFFFFF596B390 si_addr@:0xfffff596b390 si_code:2 token@:0xfffff596a130 offset:-4704
11368 00:45:30.703437 # ==>> completed. PASS(1)
11369 00:45:30.713088 # # FAKE_SIGRETURN_DUPLICATED_FPSIMD :: Triggers a sigreturn including two fpsimd_context
11370 00:45:30.719786 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFF596A130
11371 00:45:30.723336 ok 6 selftests: arm64: fake_sigreturn_duplicated_fpsimd
11372 00:45:30.726320 # selftests: arm64: fake_sigreturn_misaligned_sp
11373 00:45:30.774156 # Registered handlers for all signals.
11374 00:45:30.774411 # Detected MINSTKSIGSZ:4720
11375 00:45:30.777366 # Testcase initialized.
11376 00:45:30.780796 # uc context validated.
11377 00:45:30.784270 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11378 00:45:30.787439 # Handled SIG_COPYCTX
11379 00:45:30.794119 # SIG_OK -- SP:0xFFFFEB959623 si_addr@:0xffffeb959623 si_code:2 token@:0xffffeb959623 offset:0
11380 00:45:30.797328 # ==>> completed. PASS(1)
11381 00:45:30.804104 # # FAKE_SIGRETURN_MISALIGNED_SP :: Triggers a sigreturn with a misaligned sigframe
11382 00:45:30.810547 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFEB959623
11383 00:45:30.817182 ok 7 selftests: arm64: fake_sigreturn_misaligned_sp
11384 00:45:30.820212 # selftests: arm64: fake_sigreturn_missing_fpsimd
11385 00:45:30.866354 # Registered handlers for all signals.
11386 00:45:30.866556 # Detected MINSTKSIGSZ:4720
11387 00:45:30.869625 # Testcase initialized.
11388 00:45:30.873057 # uc context validated.
11389 00:45:30.876348 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11390 00:45:30.879619 # Handled SIG_COPYCTX
11391 00:45:30.882915 # Mangling template header. Spare space:4096
11392 00:45:30.886051 # Using badly built context - ERR: Missing FPSIMD
11393 00:45:30.895838 # SIG_OK -- SP:0xFFFFF3422D80 si_addr@:0xfffff3422d80 si_code:2 token@:0xfffff3421b20 offset:-4704
11394 00:45:30.899279 # ==>> completed. PASS(1)
11395 00:45:30.905884 # # FAKE_SIGRETURN_MISSING_FPSIMD :: Triggers a sigreturn with a missing fpsimd_context
11396 00:45:30.913043 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFF3421B20
11397 00:45:30.915597 ok 8 selftests: arm64: fake_sigreturn_missing_fpsimd
11398 00:45:30.922232 # selftests: arm64: fake_sigreturn_sme_change_vl
11399 00:45:30.950203 # Registered handlers for all signals.
11400 00:45:30.950357 # Detected MINSTKSIGSZ:4720
11401 00:45:30.953736 # ==>> completed. SKIP.
11402 00:45:30.960113 # # FAKE_SIGRETURN_SSVE_CHANGE :: Attempt to change Streaming SVE VL
11403 00:45:30.963279 ok 9 selftests: arm64: fake_sigreturn_sme_change_vl # SKIP
11404 00:45:30.972040 # selftests: arm64: fake_sigreturn_sve_change_vl
11405 00:45:31.040541 # Registered handlers for all signals.
11406 00:45:31.040694 # Detected MINSTKSIGSZ:4720
11407 00:45:31.043594 # ==>> completed. SKIP.
11408 00:45:31.050216 # # FAKE_SIGRETURN_SVE_CHANGE :: Attempt to change SVE VL
11409 00:45:31.053402 ok 10 selftests: arm64: fake_sigreturn_sve_change_vl # SKIP
11410 00:45:31.061095 # selftests: arm64: mangle_pstate_invalid_compat_toggle
11411 00:45:31.117834 # Registered handlers for all signals.
11412 00:45:31.117986 # Detected MINSTKSIGSZ:4720
11413 00:45:31.121120 # Testcase initialized.
11414 00:45:31.124335 # uc context validated.
11415 00:45:31.124421 # Handled SIG_TRIG
11416 00:45:31.134203 # SIG_OK -- SP:0xFFFFD99BFAD0 si_addr@:0xffffd99bfad0 si_code:2 token@:(nil) offset:-281474332621520
11417 00:45:31.137484 # ==>> completed. PASS(1)
11418 00:45:31.144214 # # MANGLE_PSTATE_INVALID_STATE_TOGGLE :: Mangling uc_mcontext with INVALID STATE_TOGGLE
11419 00:45:31.150554 ok 11 selftests: arm64: mangle_pstate_invalid_compat_toggle
11420 00:45:31.153932 # selftests: arm64: mangle_pstate_invalid_daif_bits
11421 00:45:31.208480 # Registered handlers for all signals.
11422 00:45:31.208633 # Detected MINSTKSIGSZ:4720
11423 00:45:31.211624 # Testcase initialized.
11424 00:45:31.215225 # uc context validated.
11425 00:45:31.215343 # Handled SIG_TRIG
11426 00:45:31.224965 # SIG_OK -- SP:0xFFFFD02FFB20 si_addr@:0xffffd02ffb20 si_code:2 token@:(nil) offset:-281474174548768
11427 00:45:31.228628 # ==>> completed. PASS(1)
11428 00:45:31.234851 # # MANGLE_PSTATE_INVALID_DAIF_BITS :: Mangling uc_mcontext with INVALID DAIF_BITS
11429 00:45:31.238115 ok 12 selftests: arm64: mangle_pstate_invalid_daif_bits
11430 00:45:31.244797 # selftests: arm64: mangle_pstate_invalid_mode_el1h
11431 00:45:31.307615 # Registered handlers for all signals.
11432 00:45:31.307768 # Detected MINSTKSIGSZ:4720
11433 00:45:31.310460 # Testcase initialized.
11434 00:45:31.314010 # uc context validated.
11435 00:45:31.314104 # Handled SIG_TRIG
11436 00:45:31.323774 # SIG_OK -- SP:0xFFFFC74194F0 si_addr@:0xffffc74194f0 si_code:2 token@:(nil) offset:-281474024707312
11437 00:45:31.327255 # ==>> completed. PASS(1)
11438 00:45:31.333792 # # MANGLE_PSTATE_INVALID_MODE_EL1h :: Mangling uc_mcontext INVALID MODE EL1h
11439 00:45:31.336844 ok 13 selftests: arm64: mangle_pstate_invalid_mode_el1h
11440 00:45:31.343392 # selftests: arm64: mangle_pstate_invalid_mode_el1t
11441 00:45:31.385750 # Registered handlers for all signals.
11442 00:45:31.385904 # Detected MINSTKSIGSZ:4720
11443 00:45:31.388806 # Testcase initialized.
11444 00:45:31.392575 # uc context validated.
11445 00:45:31.392677 # Handled SIG_TRIG
11446 00:45:31.402004 # SIG_OK -- SP:0xFFFFCDBEB270 si_addr@:0xffffcdbeb270 si_code:2 token@:(nil) offset:-281474133570160
11447 00:45:31.405413 # ==>> completed. PASS(1)
11448 00:45:31.412176 # # MANGLE_PSTATE_INVALID_MODE_EL1t :: Mangling uc_mcontext INVALID MODE EL1t
11449 00:45:31.415347 ok 14 selftests: arm64: mangle_pstate_invalid_mode_el1t
11450 00:45:31.421988 # selftests: arm64: mangle_pstate_invalid_mode_el2h
11451 00:45:31.475300 # Registered handlers for all signals.
11452 00:45:31.475452 # Detected MINSTKSIGSZ:4720
11453 00:45:31.478810 # Testcase initialized.
11454 00:45:31.482030 # uc context validated.
11455 00:45:31.482178 # Handled SIG_TRIG
11456 00:45:31.491722 # SIG_OK -- SP:0xFFFFE34981E0 si_addr@:0xffffe34981e0 si_code:2 token@:(nil) offset:-281474494988768
11457 00:45:31.495166 # ==>> completed. PASS(1)
11458 00:45:31.501735 # # MANGLE_PSTATE_INVALID_MODE_EL2h :: Mangling uc_mcontext INVALID MODE EL2h
11459 00:45:31.504894 ok 15 selftests: arm64: mangle_pstate_invalid_mode_el2h
11460 00:45:31.511604 # selftests: arm64: mangle_pstate_invalid_mode_el2t
11461 00:45:31.563260 # Registered handlers for all signals.
11462 00:45:31.563415 # Detected MINSTKSIGSZ:4720
11463 00:45:31.566721 # Testcase initialized.
11464 00:45:31.569592 # uc context validated.
11465 00:45:31.569695 # Handled SIG_TRIG
11466 00:45:31.579950 # SIG_OK -- SP:0xFFFFFB31B3D0 si_addr@:0xfffffb31b3d0 si_code:2 token@:(nil) offset:-281474896081872
11467 00:45:31.582955 # ==>> completed. PASS(1)
11468 00:45:31.589621 # # MANGLE_PSTATE_INVALID_MODE_EL2t :: Mangling uc_mcontext INVALID MODE EL2t
11469 00:45:31.593183 ok 16 selftests: arm64: mangle_pstate_invalid_mode_el2t
11470 00:45:31.599100 # selftests: arm64: mangle_pstate_invalid_mode_el3h
11471 00:45:31.645070 # Registered handlers for all signals.
11472 00:45:31.645258 # Detected MINSTKSIGSZ:4720
11473 00:45:31.648261 # Testcase initialized.
11474 00:45:31.651705 # uc context validated.
11475 00:45:31.651819 # Handled SIG_TRIG
11476 00:45:31.661412 # SIG_OK -- SP:0xFFFFF6F003E0 si_addr@:0xfffff6f003e0 si_code:2 token@:(nil) offset:-281474824668128
11477 00:45:31.664461 # ==>> completed. PASS(1)
11478 00:45:31.671382 # # MANGLE_PSTATE_INVALID_MODE_EL3h :: Mangling uc_mcontext INVALID MODE EL3h
11479 00:45:31.674525 ok 17 selftests: arm64: mangle_pstate_invalid_mode_el3h
11480 00:45:31.681045 # selftests: arm64: mangle_pstate_invalid_mode_el3t
11481 00:45:31.723230 # Registered handlers for all signals.
11482 00:45:31.723437 # Detected MINSTKSIGSZ:4720
11483 00:45:31.726683 # Testcase initialized.
11484 00:45:31.729978 # uc context validated.
11485 00:45:31.730095 # Handled SIG_TRIG
11486 00:45:31.740001 # SIG_OK -- SP:0xFFFFC88C5860 si_addr@:0xffffc88c5860 si_code:2 token@:(nil) offset:-281474046384224
11487 00:45:31.743320 # ==>> completed. PASS(1)
11488 00:45:31.749910 # # MANGLE_PSTATE_INVALID_MODE_EL3t :: Mangling uc_mcontext INVALID MODE EL3t
11489 00:45:31.753040 ok 18 selftests: arm64: mangle_pstate_invalid_mode_el3t
11490 00:45:31.756186 # selftests: arm64: sme_trap_no_sm
11491 00:45:31.798393 # Registered handlers for all signals.
11492 00:45:31.798578 # Detected MINSTKSIGSZ:4720
11493 00:45:31.801657 # ==>> completed. SKIP.
11494 00:45:31.811434 # # SME trap without SM :: Check that we get a SIGILL if we use streaming mode without enabling it
11495 00:45:31.814813 ok 19 selftests: arm64: sme_trap_no_sm # SKIP
11496 00:45:31.817881 # selftests: arm64: sme_trap_non_streaming
11497 00:45:31.888471 # Registered handlers for all signals.
11498 00:45:31.888624 # Detected MINSTKSIGSZ:4720
11499 00:45:31.892098 # ==>> completed. SKIP.
11500 00:45:31.902098 # # SME SM trap unsupported instruction :: Check that we get a SIGILL if we use an unsupported instruction in streaming mode
11501 00:45:31.908414 ok 20 selftests: arm64: sme_trap_non_streaming # SKIP
11502 00:45:31.911350 # selftests: arm64: sme_trap_za
11503 00:45:31.971171 # Registered handlers for all signals.
11504 00:45:31.971323 # Detected MINSTKSIGSZ:4720
11505 00:45:31.974330 # Testcase initialized.
11506 00:45:31.984326 # SIG_OK -- SP:0xFFFFF41BAB50 si_addr@:0xaaaae2a32510 si_code:1 token@:(nil) offset:-187650923504912
11507 00:45:31.984474 # ==>> completed. PASS(1)
11508 00:45:31.994296 # # SME ZA trap :: Check that we get a SIGILL if we access ZA without enabling
11509 00:45:31.997451 ok 21 selftests: arm64: sme_trap_za
11510 00:45:31.997567 # selftests: arm64: sme_vl
11511 00:45:32.051987 # Registered handlers for all signals.
11512 00:45:32.052166 # Detected MINSTKSIGSZ:4720
11513 00:45:32.055572 # ==>> completed. SKIP.
11514 00:45:32.062387 # # SME VL :: Check that we get the right SME VL reported
11515 00:45:32.065348 ok 22 selftests: arm64: sme_vl # SKIP
11516 00:45:32.069987 # selftests: arm64: ssve_regs
11517 00:45:32.145228 # Registered handlers for all signals.
11518 00:45:32.145414 # Detected MINSTKSIGSZ:4720
11519 00:45:32.148224 # ==>> completed. SKIP.
11520 00:45:32.154842 # # Streaming SVE registers :: Check that we get the right Streaming SVE registers reported
11521 00:45:32.161423 ok 23 selftests: arm64: ssve_regs # SKIP
11522 00:45:32.165183 # selftests: arm64: sve_regs
11523 00:45:32.238156 # Registered handlers for all signals.
11524 00:45:32.238350 # Detected MINSTKSIGSZ:4720
11525 00:45:32.241694 # ==>> completed. SKIP.
11526 00:45:32.248030 # # SVE registers :: Check that we get the right SVE registers reported
11527 00:45:32.251246 ok 24 selftests: arm64: sve_regs # SKIP
11528 00:45:32.256854 # selftests: arm64: sve_vl
11529 00:45:32.319311 # Registered handlers for all signals.
11530 00:45:32.319463 # Detected MINSTKSIGSZ:4720
11531 00:45:32.322199 # ==>> completed. SKIP.
11532 00:45:32.328923 # # SVE VL :: Check that we get the right SVE VL reported
11533 00:45:32.332100 ok 25 selftests: arm64: sve_vl # SKIP
11534 00:45:32.336184 # selftests: arm64: za_no_regs
11535 00:45:32.396518 # Registered handlers for all signals.
11536 00:45:32.396669 # Detected MINSTKSIGSZ:4720
11537 00:45:32.399845 # ==>> completed. SKIP.
11538 00:45:32.406299 # # ZA registers - ZA disabled :: Check ZA context with ZA disabled
11539 00:45:32.409825 ok 26 selftests: arm64: za_no_regs # SKIP
11540 00:45:32.415598 # selftests: arm64: za_regs
11541 00:45:32.497392 # Registered handlers for all signals.
11542 00:45:32.497542 # Detected MINSTKSIGSZ:4720
11543 00:45:32.500682 # ==>> completed. SKIP.
11544 00:45:32.507197 # # ZA register :: Check that we get the right ZA registers reported
11545 00:45:32.510722 ok 27 selftests: arm64: za_regs # SKIP
11546 00:45:32.516480 # selftests: arm64: pac
11547 00:45:32.593956 # TAP version 13
11548 00:45:32.594137 # 1..7
11549 00:45:32.596975 # # Starting 7 tests from 1 test cases.
11550 00:45:32.600568 # # RUN global.corrupt_pac ...
11551 00:45:32.604046 # # SKIP PAUTH not enabled
11552 00:45:32.606818 # # OK global.corrupt_pac
11553 00:45:32.610419 # ok 1 # SKIP PAUTH not enabled
11554 00:45:32.617208 # # RUN global.pac_instructions_not_nop ...
11555 00:45:32.620445 # # SKIP PAUTH not enabled
11556 00:45:32.623428 # # OK global.pac_instructions_not_nop
11557 00:45:32.626561 # ok 2 # SKIP PAUTH not enabled
11558 00:45:32.633288 # # RUN global.pac_instructions_not_nop_generic ...
11559 00:45:32.636686 # # SKIP Generic PAUTH not enabled
11560 00:45:32.639805 # # OK global.pac_instructions_not_nop_generic
11561 00:45:32.646330 # ok 3 # SKIP Generic PAUTH not enabled
11562 00:45:32.650350 # # RUN global.single_thread_different_keys ...
11563 00:45:32.653243 # # SKIP PAUTH not enabled
11564 00:45:32.659704 # # OK global.single_thread_different_keys
11565 00:45:32.659798 # ok 4 # SKIP PAUTH not enabled
11566 00:45:32.666528 # # RUN global.exec_changed_keys ...
11567 00:45:32.669616 # # SKIP PAUTH not enabled
11568 00:45:32.672825 # # OK global.exec_changed_keys
11569 00:45:32.676231 # ok 5 # SKIP PAUTH not enabled
11570 00:45:32.679599 # # RUN global.context_switch_keep_keys ...
11571 00:45:32.683220 # # SKIP PAUTH not enabled
11572 00:45:32.689878 # # OK global.context_switch_keep_keys
11573 00:45:32.693004 # ok 6 # SKIP PAUTH not enabled
11574 00:45:32.695960 # # RUN global.context_switch_keep_keys_generic ...
11575 00:45:32.699085 # # SKIP Generic PAUTH not enabled
11576 00:45:32.705862 # # OK global.context_switch_keep_keys_generic
11577 00:45:32.709315 # ok 7 # SKIP Generic PAUTH not enabled
11578 00:45:32.712505 # # PASSED: 7 / 7 tests passed.
11579 00:45:32.715828 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:7 error:0
11580 00:45:32.719050 ok 28 selftests: arm64: pac
11581 00:45:32.722299 # selftests: arm64: fp-stress
11582 00:45:39.258794 <6>[ 37.968709] vpu: disabling
11583 00:45:39.261923 <6>[ 37.971759] vproc2: disabling
11584 00:45:39.265076 <6>[ 37.975034] vproc1: disabling
11585 00:45:39.268615 <6>[ 37.978305] vaud18: disabling
11586 00:45:39.274923 <6>[ 37.981737] vsram_others: disabling
11587 00:45:39.278119 <6>[ 37.985630] va09: disabling
11588 00:45:39.281931 <6>[ 37.988745] vsram_md: disabling
11589 00:45:39.284587 <6>[ 37.992243] Vgpu: disabling
11590 00:45:42.682920 # TAP version 13
11591 00:45:42.683475 # 1..16
11592 00:45:42.686238 # # 8 CPUs, 0 SVE VLs, 0 SME VLs
11593 00:45:42.689763 # # Will run for 10s
11594 00:45:42.692635 # # Started FPSIMD-0-0
11595 00:45:42.693145 # # Started FPSIMD-0-1
11596 00:45:42.696239 # # Started FPSIMD-1-0
11597 00:45:42.696739 # # Started FPSIMD-1-1
11598 00:45:42.699259 # # Started FPSIMD-2-0
11599 00:45:42.702318 # # Started FPSIMD-2-1
11600 00:45:42.702772 # # Started FPSIMD-3-0
11601 00:45:42.706011 # # Started FPSIMD-3-1
11602 00:45:42.709075 # # Started FPSIMD-4-0
11603 00:45:42.709527 # # Started FPSIMD-4-1
11604 00:45:42.712459 # # Started FPSIMD-5-0
11605 00:45:42.716002 # # Started FPSIMD-5-1
11606 00:45:42.716512 # # Started FPSIMD-6-0
11607 00:45:42.718961 # # Started FPSIMD-6-1
11608 00:45:42.719371 # # Started FPSIMD-7-0
11609 00:45:42.722468 # # Started FPSIMD-7-1
11610 00:45:42.725764 # # FPSIMD-2-0: Vector length: 128 bits
11611 00:45:42.729147 # # FPSIMD-2-0: PID: 1174
11612 00:45:42.732708 # # FPSIMD-0-1: Vector length: 128 bits
11613 00:45:42.735453 # # FPSIMD-0-1: PID: 1171
11614 00:45:42.739090 # # FPSIMD-0-0: Vector length: 128 bits
11615 00:45:42.739498 # # FPSIMD-0-0: PID: 1170
11616 00:45:42.745602 # # FPSIMD-1-0: Vector length: 128 bits
11617 00:45:42.746126 # # FPSIMD-1-0: PID: 1172
11618 00:45:42.749046 # # FPSIMD-1-1: Vector length: 128 bits
11619 00:45:42.751884 # # FPSIMD-1-1: PID: 1173
11620 00:45:42.755209 # # FPSIMD-7-1: Vector length: 128 bits
11621 00:45:42.758713 # # FPSIMD-7-1: PID: 1185
11622 00:45:42.762235 # # FPSIMD-5-1: Vector length: 128 bits
11623 00:45:42.765504 # # FPSIMD-5-1: PID: 1181
11624 00:45:42.768844 # # FPSIMD-2-1: Vector length: 128 bits
11625 00:45:42.769261 # # FPSIMD-2-1: PID: 1175
11626 00:45:42.771925 # # FPSIMD-4-0: Vector length: 128 bits
11627 00:45:42.775174 # # FPSIMD-4-0: PID: 1178
11628 00:45:42.778495 # # FPSIMD-5-0: Vector length: 128 bits
11629 00:45:42.781685 # # FPSIMD-5-0: PID: 1180
11630 00:45:42.785069 # # FPSIMD-6-0: Vector length: 128 bits
11631 00:45:42.788832 # # FPSIMD-6-0: PID: 1182
11632 00:45:42.791822 # # FPSIMD-6-1: Vector length: 128 bits
11633 00:45:42.794778 # # FPSIMD-6-1: PID: 1183
11634 00:45:42.798279 # # FPSIMD-3-1: Vector length: 128 bits
11635 00:45:42.798699 # # FPSIMD-3-1: PID: 1177
11636 00:45:42.801669 # # FPSIMD-4-1: Vector length: 128 bits
11637 00:45:42.804918 # # FPSIMD-4-1: PID: 1179
11638 00:45:42.808225 # # FPSIMD-7-0: Vector length: 128 bits
11639 00:45:42.811517 # # FPSIMD-7-0: PID: 1184
11640 00:45:42.814806 # # FPSIMD-3-0: Vector length: 128 bits
11641 00:45:42.817839 # # FPSIMD-3-0: PID: 1176
11642 00:45:42.818302 # # Finishing up...
11643 00:45:42.824808 # # FPSIMD-4-1: Terminated by signal 15, no error, iterations=810683, signals=10
11644 00:45:42.834945 # # FPSIMD-3-0: Terminated by signal 15, no error, iterations=1085060, signals=10
11645 00:45:42.840916 # # FPSIMD-5-0: Terminated by signal 15, no error, iterations=1109198, signals=10
11646 00:45:42.847530 # # FPSIMD-2-0: Terminated by signal 15, no error, iterations=1751564, signals=10
11647 00:45:42.854283 # # FPSIMD-5-1: Terminated by signal 15, no error, iterations=1449063, signals=10
11648 00:45:42.861187 # # FPSIMD-0-1: Terminated by signal 15, no error, iterations=1272193, signals=10
11649 00:45:42.870542 # # FPSIMD-7-0: Terminated by signal 15, no error, iterations=1910799, signals=10
11650 00:45:42.871045 # ok 1 FPSIMD-0-0
11651 00:45:42.874156 # ok 2 FPSIMD-0-1
11652 00:45:42.874654 # ok 3 FPSIMD-1-0
11653 00:45:42.877806 # ok 4 FPSIMD-1-1
11654 00:45:42.878262 # ok 5 FPSIMD-2-0
11655 00:45:42.880813 # ok 6 FPSIMD-2-1
11656 00:45:42.881228 # ok 7 FPSIMD-3-0
11657 00:45:42.881558 # ok 8 FPSIMD-3-1
11658 00:45:42.884260 # ok 9 FPSIMD-4-0
11659 00:45:42.887762 # ok 10 FPSIMD-4-1
11660 00:45:42.888181 # ok 11 FPSIMD-5-0
11661 00:45:42.891371 # ok 12 FPSIMD-5-1
11662 00:45:42.891895 # ok 13 FPSIMD-6-0
11663 00:45:42.894385 # ok 14 FPSIMD-6-1
11664 00:45:42.894947 # ok 15 FPSIMD-7-0
11665 00:45:42.897385 # ok 16 FPSIMD-7-1
11666 00:45:42.904244 # # FPSIMD-4-0: Terminated by signal 15, no error, iterations=1149494, signals=9
11667 00:45:42.910443 # # FPSIMD-1-1: Terminated by signal 15, no error, iterations=860675, signals=10
11668 00:45:42.916887 # # FPSIMD-2-1: Terminated by signal 15, no error, iterations=907142, signals=10
11669 00:45:42.923739 # # FPSIMD-0-0: Terminated by signal 15, no error, iterations=1093707, signals=10
11670 00:45:42.930337 # # FPSIMD-3-1: Terminated by signal 15, no error, iterations=861249, signals=9
11671 00:45:42.940021 # # FPSIMD-7-1: Terminated by signal 15, no error, iterations=1092819, signals=10
11672 00:45:42.946602 # # FPSIMD-1-0: Terminated by signal 15, no error, iterations=1092363, signals=10
11673 00:45:42.953155 # # FPSIMD-6-1: Terminated by signal 15, no error, iterations=890590, signals=10
11674 00:45:42.959912 # # FPSIMD-6-0: Terminated by signal 15, no error, iterations=1943256, signals=9
11675 00:45:42.966404 # # Totals: pass:16 fail:0 xfail:0 xpass:0 skip:0 error:0
11676 00:45:42.969704 ok 29 selftests: arm64: fp-stress
11677 00:45:42.970218 # selftests: arm64: sve-ptrace
11678 00:45:42.973258 # TAP version 13
11679 00:45:42.973714 # 1..4104
11680 00:45:42.976364 # ok 2 # SKIP SVE not available
11681 00:45:42.979877 # # Planned tests != run tests (4104 != 1)
11682 00:45:42.986616 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11683 00:45:42.989618 ok 30 selftests: arm64: sve-ptrace # SKIP
11684 00:45:42.993193 # selftests: arm64: sve-probe-vls
11685 00:45:42.993612 # TAP version 13
11686 00:45:42.996024 # 1..2
11687 00:45:42.996443 # ok 2 # SKIP SVE not available
11688 00:45:42.999446 # # Planned tests != run tests (2 != 1)
11689 00:45:43.006017 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11690 00:45:43.009333 ok 31 selftests: arm64: sve-probe-vls # SKIP
11691 00:45:43.013031 # selftests: arm64: vec-syscfg
11692 00:45:43.016380 # TAP version 13
11693 00:45:43.016803 # 1..20
11694 00:45:43.019505 # ok 1 # SKIP SVE not supported
11695 00:45:43.019926 # ok 2 # SKIP SVE not supported
11696 00:45:43.022602 # ok 3 # SKIP SVE not supported
11697 00:45:43.025702 # ok 4 # SKIP SVE not supported
11698 00:45:43.029389 # ok 5 # SKIP SVE not supported
11699 00:45:43.032787 # ok 6 # SKIP SVE not supported
11700 00:45:43.035678 # ok 7 # SKIP SVE not supported
11701 00:45:43.039047 # ok 8 # SKIP SVE not supported
11702 00:45:43.042460 # ok 9 # SKIP SVE not supported
11703 00:45:43.042882 # ok 10 # SKIP SVE not supported
11704 00:45:43.045950 # ok 11 # SKIP SME not supported
11705 00:45:43.049034 # ok 12 # SKIP SME not supported
11706 00:45:43.052106 # ok 13 # SKIP SME not supported
11707 00:45:43.055463 # ok 14 # SKIP SME not supported
11708 00:45:43.058659 # ok 15 # SKIP SME not supported
11709 00:45:43.062037 # ok 16 # SKIP SME not supported
11710 00:45:43.065837 # ok 17 # SKIP SME not supported
11711 00:45:43.068521 # ok 18 # SKIP SME not supported
11712 00:45:43.072078 # ok 19 # SKIP SME not supported
11713 00:45:43.072619 # ok 20 # SKIP SME not supported
11714 00:45:43.078423 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:20 error:0
11715 00:45:43.082031 ok 32 selftests: arm64: vec-syscfg
11716 00:45:43.085257 # selftests: arm64: za-fork
11717 00:45:43.085698 # TAP version 13
11718 00:45:43.086205 # 1..1
11719 00:45:43.088378 # # PID: 1262
11720 00:45:43.092093 # # SME support not present
11721 00:45:43.092524 # ok 0 skipped
11722 00:45:43.094917 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11723 00:45:43.098238 ok 33 selftests: arm64: za-fork
11724 00:45:43.101556 # selftests: arm64: za-ptrace
11725 00:45:43.162827 # TAP version 13
11726 00:45:43.163306 # 1..1
11727 00:45:43.166006 # ok 2 # SKIP SME not available
11728 00:45:43.172776 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11729 00:45:43.175974 ok 34 selftests: arm64: za-ptrace # SKIP
11730 00:45:43.189934 # selftests: arm64: check_buffer_fill
11731 00:45:43.264635 # # SKIP: MTE features unavailable
11732 00:45:43.273022 ok 35 selftests: arm64: check_buffer_fill # SKIP
11733 00:45:43.292020 # selftests: arm64: check_child_memory
11734 00:45:43.353871 # # SKIP: MTE features unavailable
11735 00:45:43.360799 ok 36 selftests: arm64: check_child_memory # SKIP
11736 00:45:43.378694 # selftests: arm64: check_gcr_el1_cswitch
11737 00:45:43.444638 # # SKIP: MTE features unavailable
11738 00:45:43.452778 ok 37 selftests: arm64: check_gcr_el1_cswitch # SKIP
11739 00:45:43.474012 # selftests: arm64: check_ksm_options
11740 00:45:43.536369 # # SKIP: MTE features unavailable
11741 00:45:43.543634 ok 38 selftests: arm64: check_ksm_options # SKIP
11742 00:45:43.561650 # selftests: arm64: check_mmap_options
11743 00:45:43.610424 # # SKIP: MTE features unavailable
11744 00:45:43.617268 ok 39 selftests: arm64: check_mmap_options # SKIP
11745 00:45:43.635247 # selftests: arm64: check_prctl
11746 00:45:43.715732 # TAP version 13
11747 00:45:43.716305 # 1..5
11748 00:45:43.719365 # ok 1 check_basic_read
11749 00:45:43.719843 # ok 2 NONE
11750 00:45:43.722409 # ok 3 # SKIP SYNC
11751 00:45:43.722889 # ok 4 # SKIP ASYNC
11752 00:45:43.726002 # ok 5 # SKIP SYNC+ASYNC
11753 00:45:43.729158 # # Totals: pass:2 fail:0 xfail:0 xpass:0 skip:3 error:0
11754 00:45:43.731920 ok 40 selftests: arm64: check_prctl
11755 00:45:43.746670 # selftests: arm64: check_tags_inclusion
11756 00:45:43.819323 # # SKIP: MTE features unavailable
11757 00:45:43.826297 ok 41 selftests: arm64: check_tags_inclusion # SKIP
11758 00:45:43.841529 # selftests: arm64: check_user_mem
11759 00:45:43.911868 # # SKIP: MTE features unavailable
11760 00:45:43.921749 ok 42 selftests: arm64: check_user_mem # SKIP
11761 00:45:43.937319 # selftests: arm64: btitest
11762 00:45:44.025693 # TAP version 13
11763 00:45:44.026346 # 1..18
11764 00:45:44.029025 # # HWCAP_PACA not present
11765 00:45:44.032152 # # HWCAP2_BTI not present
11766 00:45:44.035321 # # Test binary built for BTI
11767 00:45:44.038674 # ok 1 nohint_func/call_using_br_x0 # SKIP
11768 00:45:44.042030 # ok 1 nohint_func/call_using_br_x16 # SKIP
11769 00:45:44.045489 # ok 1 nohint_func/call_using_blr # SKIP
11770 00:45:44.049060 # ok 1 bti_none_func/call_using_br_x0 # SKIP
11771 00:45:44.051844 # ok 1 bti_none_func/call_using_br_x16 # SKIP
11772 00:45:44.058455 # ok 1 bti_none_func/call_using_blr # SKIP
11773 00:45:44.062040 # ok 1 bti_c_func/call_using_br_x0 # SKIP
11774 00:45:44.065262 # ok 1 bti_c_func/call_using_br_x16 # SKIP
11775 00:45:44.068427 # ok 1 bti_c_func/call_using_blr # SKIP
11776 00:45:44.071916 # ok 1 bti_j_func/call_using_br_x0 # SKIP
11777 00:45:44.075203 # ok 1 bti_j_func/call_using_br_x16 # SKIP
11778 00:45:44.078389 # ok 1 bti_j_func/call_using_blr # SKIP
11779 00:45:44.081443 # ok 1 bti_jc_func/call_using_br_x0 # SKIP
11780 00:45:44.088686 # ok 1 bti_jc_func/call_using_br_x16 # SKIP
11781 00:45:44.091815 # ok 1 bti_jc_func/call_using_blr # SKIP
11782 00:45:44.095048 # ok 1 paciasp_func/call_using_br_x0 # SKIP
11783 00:45:44.098544 # ok 1 paciasp_func/call_using_br_x16 # SKIP
11784 00:45:44.101544 # ok 1 paciasp_func/call_using_blr # SKIP
11785 00:45:44.108524 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:18 error:0
11786 00:45:44.111685 # # WARNING - EXPECTED TEST COUNT WRONG
11787 00:45:44.114964 ok 43 selftests: arm64: btitest
11788 00:45:44.118485 # selftests: arm64: nobtitest
11789 00:45:44.118903 # TAP version 13
11790 00:45:44.119234 # 1..18
11791 00:45:44.121710 # # HWCAP_PACA not present
11792 00:45:44.124758 # # HWCAP2_BTI not present
11793 00:45:44.127773 # # Test binary not built for BTI
11794 00:45:44.131047 # ok 1 nohint_func/call_using_br_x0 # SKIP
11795 00:45:44.134406 # ok 1 nohint_func/call_using_br_x16 # SKIP
11796 00:45:44.137572 # ok 1 nohint_func/call_using_blr # SKIP
11797 00:45:44.140850 # ok 1 bti_none_func/call_using_br_x0 # SKIP
11798 00:45:44.147432 # ok 1 bti_none_func/call_using_br_x16 # SKIP
11799 00:45:44.150614 # ok 1 bti_none_func/call_using_blr # SKIP
11800 00:45:44.154329 # ok 1 bti_c_func/call_using_br_x0 # SKIP
11801 00:45:44.157370 # ok 1 bti_c_func/call_using_br_x16 # SKIP
11802 00:45:44.160757 # ok 1 bti_c_func/call_using_blr # SKIP
11803 00:45:44.164171 # ok 1 bti_j_func/call_using_br_x0 # SKIP
11804 00:45:44.170745 # ok 1 bti_j_func/call_using_br_x16 # SKIP
11805 00:45:44.173778 # ok 1 bti_j_func/call_using_blr # SKIP
11806 00:45:44.177661 # ok 1 bti_jc_func/call_using_br_x0 # SKIP
11807 00:45:44.181123 # ok 1 bti_jc_func/call_using_br_x16 # SKIP
11808 00:45:44.183907 # ok 1 bti_jc_func/call_using_blr # SKIP
11809 00:45:44.187189 # ok 1 paciasp_func/call_using_br_x0 # SKIP
11810 00:45:44.190664 # ok 1 paciasp_func/call_using_br_x16 # SKIP
11811 00:45:44.197515 # ok 1 paciasp_func/call_using_blr # SKIP
11812 00:45:44.200894 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:18 error:0
11813 00:45:44.203665 # # WARNING - EXPECTED TEST COUNT WRONG
11814 00:45:44.206821 ok 44 selftests: arm64: nobtitest
11815 00:45:44.210338 # selftests: arm64: hwcap
11816 00:45:44.210799 # TAP version 13
11817 00:45:44.214082 # 1..28
11818 00:45:44.214720 # ok 1 cpuinfo_match_RNG
11819 00:45:44.216895 # # SIGILL reported for RNG
11820 00:45:44.220595 # ok 2 # SKIP sigill_RNG
11821 00:45:44.221061 # ok 3 cpuinfo_match_SME
11822 00:45:44.223236 # ok 4 sigill_SME
11823 00:45:44.226600 # ok 5 cpuinfo_match_SVE
11824 00:45:44.227064 # ok 6 sigill_SVE
11825 00:45:44.230053 # ok 7 cpuinfo_match_SVE 2
11826 00:45:44.233187 # # SIGILL reported for SVE 2
11827 00:45:44.233605 # ok 8 # SKIP sigill_SVE 2
11828 00:45:44.236761 # ok 9 cpuinfo_match_SVE AES
11829 00:45:44.239924 # # SIGILL reported for SVE AES
11830 00:45:44.243462 # ok 10 # SKIP sigill_SVE AES
11831 00:45:44.246692 # ok 11 cpuinfo_match_SVE2 PMULL
11832 00:45:44.250071 # # SIGILL reported for SVE2 PMULL
11833 00:45:44.253394 # ok 12 # SKIP sigill_SVE2 PMULL
11834 00:45:44.256466 # ok 13 cpuinfo_match_SVE2 BITPERM
11835 00:45:44.259847 # # SIGILL reported for SVE2 BITPERM
11836 00:45:44.260263 # ok 14 # SKIP sigill_SVE2 BITPERM
11837 00:45:44.263198 # ok 15 cpuinfo_match_SVE2 SHA3
11838 00:45:44.266501 # # SIGILL reported for SVE2 SHA3
11839 00:45:44.269790 # ok 16 # SKIP sigill_SVE2 SHA3
11840 00:45:44.272896 # ok 17 cpuinfo_match_SVE2 SM4
11841 00:45:44.276046 # # SIGILL reported for SVE2 SM4
11842 00:45:44.279879 # ok 18 # SKIP sigill_SVE2 SM4
11843 00:45:44.282679 # ok 19 cpuinfo_match_SVE2 I8MM
11844 00:45:44.283100 # # SIGILL reported for SVE2 I8MM
11845 00:45:44.286050 # ok 20 # SKIP sigill_SVE2 I8MM
11846 00:45:44.289439 # ok 21 cpuinfo_match_SVE2 F32MM
11847 00:45:44.292822 # # SIGILL reported for SVE2 F32MM
11848 00:45:44.295818 # ok 22 # SKIP sigill_SVE2 F32MM
11849 00:45:44.299177 # ok 23 cpuinfo_match_SVE2 F64MM
11850 00:45:44.302893 # # SIGILL reported for SVE2 F64MM
11851 00:45:44.306259 # ok 24 # SKIP sigill_SVE2 F64MM
11852 00:45:44.309280 # ok 25 cpuinfo_match_SVE2 BF16
11853 00:45:44.312904 # # SIGILL reported for SVE2 BF16
11854 00:45:44.313426 # ok 26 # SKIP sigill_SVE2 BF16
11855 00:45:44.315498 # ok 27 cpuinfo_match_SVE2 EBF16
11856 00:45:44.319071 # ok 28 # SKIP sigill_SVE2 EBF16
11857 00:45:44.326007 # # Totals: pass:16 fail:0 xfail:0 xpass:0 skip:12 error:0
11858 00:45:44.329061 ok 45 selftests: arm64: hwcap
11859 00:45:44.329481 # selftests: arm64: ptrace
11860 00:45:44.332139 # TAP version 13
11861 00:45:44.332560 # 1..7
11862 00:45:44.335828 # # Parent is 1505, child is 1506
11863 00:45:44.339354 # ok 1 read_tpidr_one
11864 00:45:44.339773 # ok 2 write_tpidr_one
11865 00:45:44.341969 # ok 3 verify_tpidr_one
11866 00:45:44.342433 # ok 4 count_tpidrs
11867 00:45:44.345415 # ok 5 tpidr2_write
11868 00:45:44.348865 # ok 6 tpidr2_read
11869 00:45:44.349279 # ok 7 write_tpidr_only
11870 00:45:44.355436 # # Totals: pass:7 fail:0 xfail:0 xpass:0 skip:0 error:0
11871 00:45:44.358729 ok 46 selftests: arm64: ptrace
11872 00:45:44.359148 # selftests: arm64: syscall-abi
11873 00:45:44.396012 # TAP version 13
11874 00:45:44.396524 # 1..2
11875 00:45:44.399207 # ok 1 getpid() FPSIMD
11876 00:45:44.402689 # ok 2 sched_yield() FPSIMD
11877 00:45:44.405780 # # Totals: pass:2 fail:0 xfail:0 xpass:0 skip:0 error:0
11878 00:45:44.409085 ok 47 selftests: arm64: syscall-abi
11879 00:45:44.418952 # selftests: arm64: tpidr2
11880 00:45:44.494845 # TAP version 13
11881 00:45:44.495147 # 1..5
11882 00:45:44.498101 # # PID: 1542
11883 00:45:44.498355 # # SME support not present
11884 00:45:44.501602 # ok 0 skipped, TPIDR2 not supported
11885 00:45:44.504519 # ok 1 skipped, TPIDR2 not supported
11886 00:45:44.507872 # ok 2 skipped, TPIDR2 not supported
11887 00:45:44.511026 # ok 3 skipped, TPIDR2 not supported
11888 00:45:44.514602 # ok 4 skipped, TPIDR2 not supported
11889 00:45:44.520969 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:5 error:0
11890 00:45:44.524257 ok 48 selftests: arm64: tpidr2
11891 00:45:46.119086 arm64_tags_test pass
11892 00:45:46.122582 arm64_run_tags_test_sh pass
11893 00:45:46.125844 arm64_fake_sigreturn_bad_magic pass
11894 00:45:46.128804 arm64_fake_sigreturn_bad_size pass
11895 00:45:46.131886 arm64_fake_sigreturn_bad_size_for_magic0 pass
11896 00:45:46.135566 arm64_fake_sigreturn_duplicated_fpsimd pass
11897 00:45:46.138819 arm64_fake_sigreturn_misaligned_sp pass
11898 00:45:46.141989 arm64_fake_sigreturn_missing_fpsimd pass
11899 00:45:46.145497 arm64_fake_sigreturn_sme_change_vl skip
11900 00:45:46.152086 arm64_fake_sigreturn_sve_change_vl skip
11901 00:45:46.155198 arm64_mangle_pstate_invalid_compat_toggle pass
11902 00:45:46.158414 arm64_mangle_pstate_invalid_daif_bits pass
11903 00:45:46.161691 arm64_mangle_pstate_invalid_mode_el1h pass
11904 00:45:46.165074 arm64_mangle_pstate_invalid_mode_el1t pass
11905 00:45:46.168311 arm64_mangle_pstate_invalid_mode_el2h pass
11906 00:45:46.174854 arm64_mangle_pstate_invalid_mode_el2t pass
11907 00:45:46.178532 arm64_mangle_pstate_invalid_mode_el3h pass
11908 00:45:46.181584 arm64_mangle_pstate_invalid_mode_el3t pass
11909 00:45:46.185409 arm64_sme_trap_no_sm skip
11910 00:45:46.188471 arm64_sme_trap_non_streaming skip
11911 00:45:46.189000 arm64_sme_trap_za pass
11912 00:45:46.191411 arm64_sme_vl skip
11913 00:45:46.191872 arm64_ssve_regs skip
11914 00:45:46.194996 arm64_sve_regs skip
11915 00:45:46.195612 arm64_sve_vl skip
11916 00:45:46.197996 arm64_za_no_regs skip
11917 00:45:46.198483 arm64_za_regs skip
11918 00:45:46.201526 arm64_pac_PAUTH_not_enabled skip
11919 00:45:46.204632 arm64_pac_PAUTH_not_enabled_dup2 skip
11920 00:45:46.207850 arm64_pac_Generic_PAUTH_not_enabled skip
11921 00:45:46.214484 arm64_pac_PAUTH_not_enabled_dup3 skip
11922 00:45:46.217629 arm64_pac_PAUTH_not_enabled_dup4 skip
11923 00:45:46.221232 arm64_pac_PAUTH_not_enabled_dup5 skip
11924 00:45:46.224706 arm64_pac_Generic_PAUTH_not_enabled_dup2 skip
11925 00:45:46.225244 arm64_pac pass
11926 00:45:46.227731 arm64_fp-stress_FPSIMD-0-0 pass
11927 00:45:46.231303 arm64_fp-stress_FPSIMD-0-1 pass
11928 00:45:46.234854 arm64_fp-stress_FPSIMD-1-0 pass
11929 00:45:46.237783 arm64_fp-stress_FPSIMD-1-1 pass
11930 00:45:46.241525 arm64_fp-stress_FPSIMD-2-0 pass
11931 00:45:46.242100 arm64_fp-stress_FPSIMD-2-1 pass
11932 00:45:46.243956 arm64_fp-stress_FPSIMD-3-0 pass
11933 00:45:46.247295 arm64_fp-stress_FPSIMD-3-1 pass
11934 00:45:46.250869 arm64_fp-stress_FPSIMD-4-0 pass
11935 00:45:46.254283 arm64_fp-stress_FPSIMD-4-1 pass
11936 00:45:46.257505 arm64_fp-stress_FPSIMD-5-0 pass
11937 00:45:46.260367 arm64_fp-stress_FPSIMD-5-1 pass
11938 00:45:46.264256 arm64_fp-stress_FPSIMD-6-0 pass
11939 00:45:46.264809 arm64_fp-stress_FPSIMD-6-1 pass
11940 00:45:46.267315 arm64_fp-stress_FPSIMD-7-0 pass
11941 00:45:46.270735 arm64_fp-stress_FPSIMD-7-1 pass
11942 00:45:46.274394 arm64_fp-stress pass
11943 00:45:46.277040 arm64_sve-ptrace_SVE_not_available skip
11944 00:45:46.277554 arm64_sve-ptrace skip
11945 00:45:46.283818 arm64_sve-probe-vls_SVE_not_available skip
11946 00:45:46.284386 arm64_sve-probe-vls skip
11947 00:45:46.287349 arm64_vec-syscfg_SVE_not_supported skip
11948 00:45:46.293624 arm64_vec-syscfg_SVE_not_supported_dup2 skip
11949 00:45:46.296905 arm64_vec-syscfg_SVE_not_supported_dup3 skip
11950 00:45:46.300411 arm64_vec-syscfg_SVE_not_supported_dup4 skip
11951 00:45:46.303439 arm64_vec-syscfg_SVE_not_supported_dup5 skip
11952 00:45:46.307477 arm64_vec-syscfg_SVE_not_supported_dup6 skip
11953 00:45:46.313910 arm64_vec-syscfg_SVE_not_supported_dup7 skip
11954 00:45:46.317177 arm64_vec-syscfg_SVE_not_supported_dup8 skip
11955 00:45:46.320080 arm64_vec-syscfg_SVE_not_supported_dup9 skip
11956 00:45:46.323253 arm64_vec-syscfg_SVE_not_supported_dup10 skip
11957 00:45:46.326273 arm64_vec-syscfg_SME_not_supported skip
11958 00:45:46.333014 arm64_vec-syscfg_SME_not_supported_dup2 skip
11959 00:45:46.336879 arm64_vec-syscfg_SME_not_supported_dup3 skip
11960 00:45:46.340321 arm64_vec-syscfg_SME_not_supported_dup4 skip
11961 00:45:46.343126 arm64_vec-syscfg_SME_not_supported_dup5 skip
11962 00:45:46.346584 arm64_vec-syscfg_SME_not_supported_dup6 skip
11963 00:45:46.353327 arm64_vec-syscfg_SME_not_supported_dup7 skip
11964 00:45:46.356026 arm64_vec-syscfg_SME_not_supported_dup8 skip
11965 00:45:46.359460 arm64_vec-syscfg_SME_not_supported_dup9 skip
11966 00:45:46.363305 arm64_vec-syscfg_SME_not_supported_dup10 skip
11967 00:45:46.366288 arm64_vec-syscfg pass
11968 00:45:46.369458 arm64_za-fork_skipped pass
11969 00:45:46.369920 arm64_za-fork pass
11970 00:45:46.373005 arm64_za-ptrace_SME_not_available skip
11971 00:45:46.376030 arm64_za-ptrace skip
11972 00:45:46.379394 arm64_check_buffer_fill skip
11973 00:45:46.379856 arm64_check_child_memory skip
11974 00:45:46.382980 arm64_check_gcr_el1_cswitch skip
11975 00:45:46.386078 arm64_check_ksm_options skip
11976 00:45:46.389273 arm64_check_mmap_options skip
11977 00:45:46.392740 arm64_check_prctl_check_basic_read pass
11978 00:45:46.395618 arm64_check_prctl_NONE pass
11979 00:45:46.396085 arm64_check_prctl_SYNC skip
11980 00:45:46.399325 arm64_check_prctl_ASYNC skip
11981 00:45:46.402355 arm64_check_prctl_SYNC_ASYNC skip
11982 00:45:46.406027 arm64_check_prctl pass
11983 00:45:46.409249 arm64_check_tags_inclusion skip
11984 00:45:46.409826 arm64_check_user_mem skip
11985 00:45:46.415994 arm64_btitest_nohint_func_call_using_br_x0 skip
11986 00:45:46.419439 arm64_btitest_nohint_func_call_using_br_x16 skip
11987 00:45:46.422064 arm64_btitest_nohint_func_call_using_blr skip
11988 00:45:46.429091 arm64_btitest_bti_none_func_call_using_br_x0 skip
11989 00:45:46.432114 arm64_btitest_bti_none_func_call_using_br_x16 skip
11990 00:45:46.435682 arm64_btitest_bti_none_func_call_using_blr skip
11991 00:45:46.438900 arm64_btitest_bti_c_func_call_using_br_x0 skip
11992 00:45:46.445076 arm64_btitest_bti_c_func_call_using_br_x16 skip
11993 00:45:46.448640 arm64_btitest_bti_c_func_call_using_blr skip
11994 00:45:46.452334 arm64_btitest_bti_j_func_call_using_br_x0 skip
11995 00:45:46.458632 arm64_btitest_bti_j_func_call_using_br_x16 skip
11996 00:45:46.461778 arm64_btitest_bti_j_func_call_using_blr skip
11997 00:45:46.465049 arm64_btitest_bti_jc_func_call_using_br_x0 skip
11998 00:45:46.468365 arm64_btitest_bti_jc_func_call_using_br_x16 skip
11999 00:45:46.474732 arm64_btitest_bti_jc_func_call_using_blr skip
12000 00:45:46.478111 arm64_btitest_paciasp_func_call_using_br_x0 skip
12001 00:45:46.481404 arm64_btitest_paciasp_func_call_using_br_x16 skip
12002 00:45:46.487962 arm64_btitest_paciasp_func_call_using_blr skip
12003 00:45:46.488429 arm64_btitest pass
12004 00:45:46.491308 arm64_nobtitest_nohint_func_call_using_br_x0 skip
12005 00:45:46.497727 arm64_nobtitest_nohint_func_call_using_br_x16 skip
12006 00:45:46.502094 arm64_nobtitest_nohint_func_call_using_blr skip
12007 00:45:46.504503 arm64_nobtitest_bti_none_func_call_using_br_x0 skip
12008 00:45:46.511217 arm64_nobtitest_bti_none_func_call_using_br_x16 skip
12009 00:45:46.514855 arm64_nobtitest_bti_none_func_call_using_blr skip
12010 00:45:46.521509 arm64_nobtitest_bti_c_func_call_using_br_x0 skip
12011 00:45:46.524135 arm64_nobtitest_bti_c_func_call_using_br_x16 skip
12012 00:45:46.527391 arm64_nobtitest_bti_c_func_call_using_blr skip
12013 00:45:46.530951 arm64_nobtitest_bti_j_func_call_using_br_x0 skip
12014 00:45:46.537367 arm64_nobtitest_bti_j_func_call_using_br_x16 skip
12015 00:45:46.540861 arm64_nobtitest_bti_j_func_call_using_blr skip
12016 00:45:46.544371 arm64_nobtitest_bti_jc_func_call_using_br_x0 skip
12017 00:45:46.550762 arm64_nobtitest_bti_jc_func_call_using_br_x16 skip
12018 00:45:46.554210 arm64_nobtitest_bti_jc_func_call_using_blr skip
12019 00:45:46.557216 arm64_nobtitest_paciasp_func_call_using_br_x0 skip
12020 00:45:46.564085 arm64_nobtitest_paciasp_func_call_using_br_x16 skip
12021 00:45:46.567595 arm64_nobtitest_paciasp_func_call_using_blr skip
12022 00:45:46.570542 arm64_nobtitest pass
12023 00:45:46.573702 arm64_hwcap_cpuinfo_match_RNG pass
12024 00:45:46.574255 arm64_hwcap_sigill_RNG skip
12025 00:45:46.576937 arm64_hwcap_cpuinfo_match_SME pass
12026 00:45:46.580393 arm64_hwcap_sigill_SME pass
12027 00:45:46.583559 arm64_hwcap_cpuinfo_match_SVE pass
12028 00:45:46.587273 arm64_hwcap_sigill_SVE pass
12029 00:45:46.590261 arm64_hwcap_cpuinfo_match_SVE_2 pass
12030 00:45:46.593605 arm64_hwcap_sigill_SVE_2 skip
12031 00:45:46.596760 arm64_hwcap_cpuinfo_match_SVE_AES pass
12032 00:45:46.600459 arm64_hwcap_sigill_SVE_AES skip
12033 00:45:46.603810 arm64_hwcap_cpuinfo_match_SVE2_PMULL pass
12034 00:45:46.606724 arm64_hwcap_sigill_SVE2_PMULL skip
12035 00:45:46.610622 arm64_hwcap_cpuinfo_match_SVE2_BITPERM pass
12036 00:45:46.613744 arm64_hwcap_sigill_SVE2_BITPERM skip
12037 00:45:46.617004 arm64_hwcap_cpuinfo_match_SVE2_SHA3 pass
12038 00:45:46.619788 arm64_hwcap_sigill_SVE2_SHA3 skip
12039 00:45:46.623282 arm64_hwcap_cpuinfo_match_SVE2_SM4 pass
12040 00:45:46.626737 arm64_hwcap_sigill_SVE2_SM4 skip
12041 00:45:46.630031 arm64_hwcap_cpuinfo_match_SVE2_I8MM pass
12042 00:45:46.633302 arm64_hwcap_sigill_SVE2_I8MM skip
12043 00:45:46.636468 arm64_hwcap_cpuinfo_match_SVE2_F32MM pass
12044 00:45:46.640021 arm64_hwcap_sigill_SVE2_F32MM skip
12045 00:45:46.642996 arm64_hwcap_cpuinfo_match_SVE2_F64MM pass
12046 00:45:46.646510 arm64_hwcap_sigill_SVE2_F64MM skip
12047 00:45:46.649549 arm64_hwcap_cpuinfo_match_SVE2_BF16 pass
12048 00:45:46.652781 arm64_hwcap_sigill_SVE2_BF16 skip
12049 00:45:46.656259 arm64_hwcap_cpuinfo_match_SVE2_EBF16 pass
12050 00:45:46.659744 arm64_hwcap_sigill_SVE2_EBF16 skip
12051 00:45:46.662911 arm64_hwcap pass
12052 00:45:46.666100 arm64_ptrace_read_tpidr_one pass
12053 00:45:46.666577 arm64_ptrace_write_tpidr_one pass
12054 00:45:46.669423 arm64_ptrace_verify_tpidr_one pass
12055 00:45:46.672726 arm64_ptrace_count_tpidrs pass
12056 00:45:46.676103 arm64_ptrace_tpidr2_write pass
12057 00:45:46.679326 arm64_ptrace_tpidr2_read pass
12058 00:45:46.682527 arm64_ptrace_write_tpidr_only pass
12059 00:45:46.682946 arm64_ptrace pass
12060 00:45:46.686009 arm64_syscall-abi_getpid_FPSIMD pass
12061 00:45:46.689328 arm64_syscall-abi_sched_yield_FPSIMD pass
12062 00:45:46.692404 arm64_syscall-abi pass
12063 00:45:46.695761 arm64_tpidr2_skipped_TPIDR2_not_supported pass
12064 00:45:46.702565 arm64_tpidr2_skipped_TPIDR2_not_supported_dup2 pass
12065 00:45:46.705525 arm64_tpidr2_skipped_TPIDR2_not_supported_dup3 pass
12066 00:45:46.712608 arm64_tpidr2_skipped_TPIDR2_not_supported_dup4 pass
12067 00:45:46.715653 arm64_tpidr2_skipped_TPIDR2_not_supported_dup5 pass
12068 00:45:46.716079 arm64_tpidr2 pass
12069 00:45:46.721988 + ../../utils/send-to-lava.sh ./output/result.txt
12070 00:45:46.725611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-arm64 RESULT=pass>
12071 00:45:46.726395 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-arm64 RESULT=pass
12073 00:45:46.732301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tags_test RESULT=pass>
12074 00:45:46.732976 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tags_test RESULT=pass
12076 00:45:46.738556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_run_tags_test_sh RESULT=pass>
12077 00:45:46.739229 Received signal: <TESTCASE> TEST_CASE_ID=arm64_run_tags_test_sh RESULT=pass
12079 00:45:46.770274 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_magic RESULT=pass>
12080 00:45:46.771027 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_magic RESULT=pass
12082 00:45:46.836480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_size RESULT=pass>
12083 00:45:46.837204 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_size RESULT=pass
12085 00:45:46.905519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_size_for_magic0 RESULT=pass>
12086 00:45:46.906254 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_size_for_magic0 RESULT=pass
12088 00:45:46.973355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_duplicated_fpsimd RESULT=pass>
12089 00:45:46.974069 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_duplicated_fpsimd RESULT=pass
12091 00:45:47.042473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_misaligned_sp RESULT=pass>
12092 00:45:47.043239 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_misaligned_sp RESULT=pass
12094 00:45:47.114504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_missing_fpsimd RESULT=pass>
12095 00:45:47.115311 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_missing_fpsimd RESULT=pass
12097 00:45:47.183360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_sme_change_vl RESULT=skip>
12098 00:45:47.184114 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_sme_change_vl RESULT=skip
12100 00:45:47.251821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_sve_change_vl RESULT=skip>
12101 00:45:47.252656 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_sve_change_vl RESULT=skip
12103 00:45:47.322919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_compat_toggle RESULT=pass>
12104 00:45:47.323772 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_compat_toggle RESULT=pass
12106 00:45:47.394664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_daif_bits RESULT=pass>
12107 00:45:47.395508 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_daif_bits RESULT=pass
12109 00:45:47.464799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1h RESULT=pass>
12110 00:45:47.465587 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1h RESULT=pass
12112 00:45:47.528050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1t RESULT=pass>
12113 00:45:47.528810 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1t RESULT=pass
12115 00:45:47.594961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2h RESULT=pass>
12116 00:45:47.595784 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2h RESULT=pass
12118 00:45:47.666451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2t RESULT=pass>
12119 00:45:47.667249 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2t RESULT=pass
12121 00:45:47.734313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3h RESULT=pass>
12122 00:45:47.735023 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3h RESULT=pass
12124 00:45:47.800363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3t RESULT=pass>
12125 00:45:47.801120 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3t RESULT=pass
12127 00:45:47.866728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_no_sm RESULT=skip>
12128 00:45:47.867546 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_no_sm RESULT=skip
12130 00:45:47.938072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_non_streaming RESULT=skip>
12131 00:45:47.938808 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_non_streaming RESULT=skip
12133 00:45:48.004092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_za RESULT=pass>
12134 00:45:48.004792 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_za RESULT=pass
12136 00:45:48.071296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_vl RESULT=skip>
12137 00:45:48.072188 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_vl RESULT=skip
12139 00:45:48.131913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ssve_regs RESULT=skip>
12140 00:45:48.132206 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ssve_regs RESULT=skip
12142 00:45:48.192308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve_regs RESULT=skip>
12143 00:45:48.192602 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve_regs RESULT=skip
12145 00:45:48.257830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve_vl RESULT=skip>
12146 00:45:48.258585 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve_vl RESULT=skip
12148 00:45:48.323956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za_no_regs RESULT=skip>
12149 00:45:48.324653 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za_no_regs RESULT=skip
12151 00:45:48.395360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za_regs RESULT=skip>
12152 00:45:48.396120 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za_regs RESULT=skip
12154 00:45:48.461284 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip
12156 00:45:48.464020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip>
12157 00:45:48.538386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup2 RESULT=skip>
12158 00:45:48.539215 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup2 RESULT=skip
12160 00:45:48.613010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_Generic_PAUTH_not_enabled RESULT=skip>
12161 00:45:48.613879 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_Generic_PAUTH_not_enabled RESULT=skip
12163 00:45:48.677848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup3 RESULT=skip>
12164 00:45:48.678630 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup3 RESULT=skip
12166 00:45:48.744193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup4 RESULT=skip>
12167 00:45:48.744883 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup4 RESULT=skip
12169 00:45:48.817572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup5 RESULT=skip>
12170 00:45:48.818389 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup5 RESULT=skip
12172 00:45:48.883163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_Generic_PAUTH_not_enabled_dup2 RESULT=skip>
12173 00:45:48.884035 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_Generic_PAUTH_not_enabled_dup2 RESULT=skip
12175 00:45:48.950404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac RESULT=pass>
12176 00:45:48.951223 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac RESULT=pass
12178 00:45:49.016973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-0 RESULT=pass>
12179 00:45:49.017866 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-0 RESULT=pass
12181 00:45:49.083428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-1 RESULT=pass>
12182 00:45:49.084146 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-1 RESULT=pass
12184 00:45:49.152178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-0 RESULT=pass>
12185 00:45:49.152935 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-0 RESULT=pass
12187 00:45:49.218677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-1 RESULT=pass>
12188 00:45:49.219459 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-1 RESULT=pass
12190 00:45:49.288289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-0 RESULT=pass>
12191 00:45:49.289105 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-0 RESULT=pass
12193 00:45:49.358712 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-1 RESULT=pass
12195 00:45:49.361444 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-1 RESULT=pass>
12196 00:45:49.428976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-0 RESULT=pass>
12197 00:45:49.429678 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-0 RESULT=pass
12199 00:45:49.497389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-1 RESULT=pass>
12200 00:45:49.498085 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-1 RESULT=pass
12202 00:45:49.566515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-0 RESULT=pass>
12203 00:45:49.567201 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-0 RESULT=pass
12205 00:45:49.632476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-1 RESULT=pass>
12206 00:45:49.632889 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-1 RESULT=pass
12208 00:45:49.694954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-0 RESULT=pass>
12209 00:45:49.695712 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-0 RESULT=pass
12211 00:45:49.759705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-1 RESULT=pass>
12212 00:45:49.760043 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-1 RESULT=pass
12214 00:45:49.824807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-0 RESULT=pass>
12215 00:45:49.825460 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-0 RESULT=pass
12217 00:45:49.882886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-1 RESULT=pass>
12218 00:45:49.883521 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-1 RESULT=pass
12220 00:45:49.945984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-0 RESULT=pass>
12221 00:45:49.946351 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-0 RESULT=pass
12223 00:45:50.011383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-1 RESULT=pass>
12224 00:45:50.012098 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-1 RESULT=pass
12226 00:45:50.084222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress RESULT=pass>
12227 00:45:50.084923 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress RESULT=pass
12229 00:45:50.151923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_not_available RESULT=skip>
12230 00:45:50.152656 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_not_available RESULT=skip
12232 00:45:50.216774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace RESULT=skip>
12233 00:45:50.217620 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace RESULT=skip
12235 00:45:50.296513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls_SVE_not_available RESULT=skip>
12236 00:45:50.297275 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls_SVE_not_available RESULT=skip
12238 00:45:50.356160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls RESULT=skip>
12239 00:45:50.356954 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls RESULT=skip
12241 00:45:50.429436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip>
12242 00:45:50.430134 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip
12244 00:45:50.499818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup2 RESULT=skip>
12245 00:45:50.500526 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup2 RESULT=skip
12247 00:45:50.569692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup3 RESULT=skip>
12248 00:45:50.570651 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup3 RESULT=skip
12250 00:45:50.640822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup4 RESULT=skip>
12251 00:45:50.641536 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup4 RESULT=skip
12253 00:45:50.709014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup5 RESULT=skip>
12254 00:45:50.709707 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup5 RESULT=skip
12256 00:45:50.777846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup6 RESULT=skip>
12257 00:45:50.778599 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup6 RESULT=skip
12259 00:45:50.845362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup7 RESULT=skip>
12260 00:45:50.846126 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup7 RESULT=skip
12262 00:45:50.920421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup8 RESULT=skip>
12263 00:45:50.921256 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup8 RESULT=skip
12265 00:45:50.988654 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup9 RESULT=skip>
12266 00:45:50.989375 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup9 RESULT=skip
12268 00:45:51.056446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup10 RESULT=skip>
12269 00:45:51.057336 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup10 RESULT=skip
12271 00:45:51.123660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip>
12272 00:45:51.124582 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip
12274 00:45:51.194266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup2 RESULT=skip>
12275 00:45:51.194995 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup2 RESULT=skip
12277 00:45:51.265745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup3 RESULT=skip>
12278 00:45:51.266550 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup3 RESULT=skip
12280 00:45:51.331689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup4 RESULT=skip>
12281 00:45:51.332381 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup4 RESULT=skip
12283 00:45:51.402235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup5 RESULT=skip>
12284 00:45:51.403023 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup5 RESULT=skip
12286 00:45:51.467137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup6 RESULT=skip>
12287 00:45:51.467975 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup6 RESULT=skip
12289 00:45:51.538594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup7 RESULT=skip>
12290 00:45:51.539401 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup7 RESULT=skip
12292 00:45:51.605157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup8 RESULT=skip>
12293 00:45:51.605927 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup8 RESULT=skip
12295 00:45:51.668478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup9 RESULT=skip>
12296 00:45:51.669189 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup9 RESULT=skip
12298 00:45:51.733726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup10 RESULT=skip>
12299 00:45:51.734610 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup10 RESULT=skip
12301 00:45:51.793224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg RESULT=pass>
12302 00:45:51.794022 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg RESULT=pass
12304 00:45:51.856990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-fork_skipped RESULT=pass>
12305 00:45:51.857756 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-fork_skipped RESULT=pass
12307 00:45:51.923823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-fork RESULT=pass>
12308 00:45:51.924583 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-fork RESULT=pass
12310 00:45:51.993201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_SME_not_available RESULT=skip>
12311 00:45:51.993958 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_SME_not_available RESULT=skip
12313 00:45:52.056801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace RESULT=skip>
12314 00:45:52.057557 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace RESULT=skip
12316 00:45:52.126084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill RESULT=skip>
12317 00:45:52.126878 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill RESULT=skip
12319 00:45:52.194973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory RESULT=skip>
12320 00:45:52.195689 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory RESULT=skip
12322 00:45:52.254880 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_gcr_el1_cswitch RESULT=skip
12324 00:45:52.257791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_gcr_el1_cswitch RESULT=skip>
12325 00:45:52.321949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_ksm_options RESULT=skip>
12326 00:45:52.322697 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_ksm_options RESULT=skip
12328 00:45:52.387433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options RESULT=skip>
12329 00:45:52.388144 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options RESULT=skip
12331 00:45:52.466813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_check_basic_read RESULT=pass>
12332 00:45:52.467652 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_check_basic_read RESULT=pass
12334 00:45:52.529120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_NONE RESULT=pass>
12335 00:45:52.529801 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_NONE RESULT=pass
12337 00:45:52.598873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_SYNC RESULT=skip>
12338 00:45:52.599633 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_SYNC RESULT=skip
12340 00:45:52.665508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_ASYNC RESULT=skip>
12341 00:45:52.666289 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_ASYNC RESULT=skip
12343 00:45:52.732244 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_SYNC_ASYNC RESULT=skip
12345 00:45:52.735396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_SYNC_ASYNC RESULT=skip>
12346 00:45:52.800016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl RESULT=pass>
12347 00:45:52.800796 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl RESULT=pass
12349 00:45:52.869747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_tags_inclusion RESULT=skip>
12350 00:45:52.870482 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_tags_inclusion RESULT=skip
12352 00:45:52.940237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem RESULT=skip>
12353 00:45:52.941045 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem RESULT=skip
12355 00:45:53.013442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x0 RESULT=skip>
12356 00:45:53.014142 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x0 RESULT=skip
12358 00:45:53.086133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x16 RESULT=skip>
12359 00:45:53.087013 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x16 RESULT=skip
12361 00:45:53.153955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_blr RESULT=skip>
12362 00:45:53.154913 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_blr RESULT=skip
12364 00:45:53.220317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x0 RESULT=skip>
12365 00:45:53.221045 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x0 RESULT=skip
12367 00:45:53.292505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x16 RESULT=skip>
12368 00:45:53.293277 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x16 RESULT=skip
12370 00:45:53.362215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_blr RESULT=skip>
12371 00:45:53.362966 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_blr RESULT=skip
12373 00:45:53.430268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x0 RESULT=skip>
12374 00:45:53.431014 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x0 RESULT=skip
12376 00:45:53.500877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x16 RESULT=skip>
12377 00:45:53.501698 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x16 RESULT=skip
12379 00:45:53.572696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_blr RESULT=skip>
12380 00:45:53.573480 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_blr RESULT=skip
12382 00:45:53.642550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x0 RESULT=skip>
12383 00:45:53.643304 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x0 RESULT=skip
12385 00:45:53.708171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x16 RESULT=skip>
12386 00:45:53.708468 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x16 RESULT=skip
12388 00:45:53.756126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_blr RESULT=skip>
12389 00:45:53.756388 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_blr RESULT=skip
12391 00:45:53.812240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x0 RESULT=skip>
12392 00:45:53.812516 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x0 RESULT=skip
12394 00:45:53.867162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x16 RESULT=skip>
12395 00:45:53.867433 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x16 RESULT=skip
12397 00:45:53.921032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_blr RESULT=skip>
12398 00:45:53.921301 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_blr RESULT=skip
12400 00:45:53.977965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x0 RESULT=skip>
12401 00:45:53.978237 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x0 RESULT=skip
12403 00:45:54.028950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x16 RESULT=skip>
12404 00:45:54.029264 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x16 RESULT=skip
12406 00:45:54.084767 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_blr RESULT=skip>
12407 00:45:54.085078 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_blr RESULT=skip
12409 00:45:54.138661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest RESULT=pass>
12410 00:45:54.138961 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest RESULT=pass
12412 00:45:54.196807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x0 RESULT=skip>
12413 00:45:54.197112 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x0 RESULT=skip
12415 00:45:54.249553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x16 RESULT=skip>
12416 00:45:54.249830 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x16 RESULT=skip
12418 00:45:54.308216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_blr RESULT=skip>
12419 00:45:54.308503 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_blr RESULT=skip
12421 00:45:54.367168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x0 RESULT=skip>
12422 00:45:54.367457 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x0 RESULT=skip
12424 00:45:54.426079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x16 RESULT=skip>
12425 00:45:54.426355 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x16 RESULT=skip
12427 00:45:54.484951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_blr RESULT=skip>
12428 00:45:54.485229 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_blr RESULT=skip
12430 00:45:54.542407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x0 RESULT=skip>
12431 00:45:54.542697 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x0 RESULT=skip
12433 00:45:54.598014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x16 RESULT=skip>
12434 00:45:54.598293 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x16 RESULT=skip
12436 00:45:54.652391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_blr RESULT=skip>
12437 00:45:54.652690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_blr RESULT=skip
12439 00:45:54.709765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x0 RESULT=skip>
12440 00:45:54.710073 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x0 RESULT=skip
12442 00:45:54.765723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x16 RESULT=skip>
12443 00:45:54.766005 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x16 RESULT=skip
12445 00:45:54.825948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_blr RESULT=skip>
12446 00:45:54.826215 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_blr RESULT=skip
12448 00:45:54.880572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x0 RESULT=skip>
12449 00:45:54.880874 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x0 RESULT=skip
12451 00:45:54.936490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x16 RESULT=skip>
12452 00:45:54.936786 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x16 RESULT=skip
12454 00:45:54.994499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_blr RESULT=skip>
12455 00:45:54.994844 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_blr RESULT=skip
12457 00:45:55.051756 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x0 RESULT=skip>
12458 00:45:55.052071 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x0 RESULT=skip
12460 00:45:55.103729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x16 RESULT=skip>
12461 00:45:55.104060 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x16 RESULT=skip
12463 00:45:55.155446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_blr RESULT=skip>
12464 00:45:55.155752 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_blr RESULT=skip
12466 00:45:55.203919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest RESULT=pass>
12467 00:45:55.204191 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest RESULT=pass
12469 00:45:55.266832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_RNG RESULT=pass>
12470 00:45:55.267124 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_RNG RESULT=pass
12472 00:45:55.322092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_RNG RESULT=skip>
12473 00:45:55.322421 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_RNG RESULT=skip
12475 00:45:55.383127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SME RESULT=pass>
12476 00:45:55.383409 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SME RESULT=pass
12478 00:45:55.436515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SME RESULT=pass>
12479 00:45:55.436796 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SME RESULT=pass
12481 00:45:55.496540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE RESULT=pass>
12482 00:45:55.496829 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE RESULT=pass
12484 00:45:55.549903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE RESULT=pass>
12485 00:45:55.550181 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE RESULT=pass
12487 00:45:55.607971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_2 RESULT=pass>
12488 00:45:55.608250 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_2 RESULT=pass
12490 00:45:55.664858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE_2 RESULT=skip>
12491 00:45:55.665145 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE_2 RESULT=skip
12493 00:45:55.725329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_AES RESULT=pass>
12494 00:45:55.725613 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_AES RESULT=pass
12496 00:45:55.784481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE_AES RESULT=skip>
12497 00:45:55.784771 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE_AES RESULT=skip
12499 00:45:55.846487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_PMULL RESULT=pass>
12500 00:45:55.846771 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_PMULL RESULT=pass
12502 00:45:55.902670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_PMULL RESULT=skip>
12503 00:45:55.902947 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_PMULL RESULT=skip
12505 00:45:55.959049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BITPERM RESULT=pass>
12506 00:45:55.959313 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BITPERM RESULT=pass
12508 00:45:56.017869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BITPERM RESULT=skip>
12509 00:45:56.018147 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BITPERM RESULT=skip
12511 00:45:56.074831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SHA3 RESULT=pass>
12512 00:45:56.075107 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SHA3 RESULT=pass
12514 00:45:56.126447 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SHA3 RESULT=skip
12516 00:45:56.129634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SHA3 RESULT=skip>
12517 00:45:56.183124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SM4 RESULT=pass>
12518 00:45:56.183402 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SM4 RESULT=pass
12520 00:45:56.232530 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SM4 RESULT=skip
12522 00:45:56.235898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SM4 RESULT=skip>
12523 00:45:56.294316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_I8MM RESULT=pass>
12524 00:45:56.294594 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_I8MM RESULT=pass
12526 00:45:56.348949 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_I8MM RESULT=skip
12528 00:45:56.351587 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_I8MM RESULT=skip>
12529 00:45:56.405044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F32MM RESULT=pass>
12530 00:45:56.405315 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F32MM RESULT=pass
12532 00:45:56.462901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F32MM RESULT=skip>
12533 00:45:56.463166 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F32MM RESULT=skip
12535 00:45:56.517285 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F64MM RESULT=pass>
12536 00:45:56.517563 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F64MM RESULT=pass
12538 00:45:56.572891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F64MM RESULT=skip>
12539 00:45:56.573172 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F64MM RESULT=skip
12541 00:45:56.629541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BF16 RESULT=pass>
12542 00:45:56.629853 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BF16 RESULT=pass
12544 00:45:56.687245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BF16 RESULT=skip>
12545 00:45:56.687538 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BF16 RESULT=skip
12547 00:45:56.747626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_EBF16 RESULT=pass>
12548 00:45:56.747902 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_EBF16 RESULT=pass
12550 00:45:56.803960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_EBF16 RESULT=skip>
12551 00:45:56.804243 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_EBF16 RESULT=skip
12553 00:45:56.861710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap RESULT=pass>
12554 00:45:56.861999 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap RESULT=pass
12556 00:45:56.917403 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_read_tpidr_one RESULT=pass
12558 00:45:56.920089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_read_tpidr_one RESULT=pass>
12559 00:45:56.981060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_write_tpidr_one RESULT=pass>
12560 00:45:56.981338 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_write_tpidr_one RESULT=pass
12562 00:45:57.042112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_verify_tpidr_one RESULT=pass>
12563 00:45:57.042456 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_verify_tpidr_one RESULT=pass
12565 00:45:57.098557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_count_tpidrs RESULT=pass>
12566 00:45:57.098838 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_count_tpidrs RESULT=pass
12568 00:45:57.159269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_tpidr2_write RESULT=pass>
12569 00:45:57.159534 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_tpidr2_write RESULT=pass
12571 00:45:57.217803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_tpidr2_read RESULT=pass>
12572 00:45:57.218079 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_tpidr2_read RESULT=pass
12574 00:45:57.278908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_write_tpidr_only RESULT=pass>
12575 00:45:57.279187 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_write_tpidr_only RESULT=pass
12577 00:45:57.335532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace RESULT=pass>
12578 00:45:57.335796 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace RESULT=pass
12580 00:45:57.392881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_FPSIMD RESULT=pass>
12581 00:45:57.393163 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_FPSIMD RESULT=pass
12583 00:45:57.451843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_FPSIMD RESULT=pass>
12584 00:45:57.452110 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_FPSIMD RESULT=pass
12586 00:45:57.505442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi RESULT=pass>
12587 00:45:57.505715 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi RESULT=pass
12589 00:45:57.564230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12590 00:45:57.564494 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12592 00:45:57.619548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup2 RESULT=pass>
12593 00:45:57.619828 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup2 RESULT=pass
12595 00:45:57.675271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup3 RESULT=pass>
12596 00:45:57.675547 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup3 RESULT=pass
12598 00:45:57.732538 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup4 RESULT=pass>
12599 00:45:57.732815 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup4 RESULT=pass
12601 00:45:57.789454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup5 RESULT=pass>
12602 00:45:57.789736 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup5 RESULT=pass
12604 00:45:57.843770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2 RESULT=pass>
12605 00:45:57.843879 + set +x
12606 00:45:57.844116 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2 RESULT=pass
12608 00:45:57.850737 <LAVA_SIGNAL_ENDRUN 1_kselftest-arm64 14368400_1.6.2.3.5>
12609 00:45:57.850986 Received signal: <ENDRUN> 1_kselftest-arm64 14368400_1.6.2.3.5
12610 00:45:57.851060 Ending use of test pattern.
12611 00:45:57.851120 Ending test lava.1_kselftest-arm64 (14368400_1.6.2.3.5), duration 35.75
12613 00:45:57.853814 <LAVA_TEST_RUNNER EXIT>
12614 00:45:57.854063 ok: lava_test_shell seems to have completed
12615 00:45:57.855180 arm64_btitest: pass
arm64_btitest_bti_c_func_call_using_blr: skip
arm64_btitest_bti_c_func_call_using_br_x0: skip
arm64_btitest_bti_c_func_call_using_br_x16: skip
arm64_btitest_bti_j_func_call_using_blr: skip
arm64_btitest_bti_j_func_call_using_br_x0: skip
arm64_btitest_bti_j_func_call_using_br_x16: skip
arm64_btitest_bti_jc_func_call_using_blr: skip
arm64_btitest_bti_jc_func_call_using_br_x0: skip
arm64_btitest_bti_jc_func_call_using_br_x16: skip
arm64_btitest_bti_none_func_call_using_blr: skip
arm64_btitest_bti_none_func_call_using_br_x0: skip
arm64_btitest_bti_none_func_call_using_br_x16: skip
arm64_btitest_nohint_func_call_using_blr: skip
arm64_btitest_nohint_func_call_using_br_x0: skip
arm64_btitest_nohint_func_call_using_br_x16: skip
arm64_btitest_paciasp_func_call_using_blr: skip
arm64_btitest_paciasp_func_call_using_br_x0: skip
arm64_btitest_paciasp_func_call_using_br_x16: skip
arm64_check_buffer_fill: skip
arm64_check_child_memory: skip
arm64_check_gcr_el1_cswitch: skip
arm64_check_ksm_options: skip
arm64_check_mmap_options: skip
arm64_check_prctl: pass
arm64_check_prctl_ASYNC: skip
arm64_check_prctl_NONE: pass
arm64_check_prctl_SYNC: skip
arm64_check_prctl_SYNC_ASYNC: skip
arm64_check_prctl_check_basic_read: pass
arm64_check_tags_inclusion: skip
arm64_check_user_mem: skip
arm64_fake_sigreturn_bad_magic: pass
arm64_fake_sigreturn_bad_size: pass
arm64_fake_sigreturn_bad_size_for_magic0: pass
arm64_fake_sigreturn_duplicated_fpsimd: pass
arm64_fake_sigreturn_misaligned_sp: pass
arm64_fake_sigreturn_missing_fpsimd: pass
arm64_fake_sigreturn_sme_change_vl: skip
arm64_fake_sigreturn_sve_change_vl: skip
arm64_fp-stress: pass
arm64_fp-stress_FPSIMD-0-0: pass
arm64_fp-stress_FPSIMD-0-1: pass
arm64_fp-stress_FPSIMD-1-0: pass
arm64_fp-stress_FPSIMD-1-1: pass
arm64_fp-stress_FPSIMD-2-0: pass
arm64_fp-stress_FPSIMD-2-1: pass
arm64_fp-stress_FPSIMD-3-0: pass
arm64_fp-stress_FPSIMD-3-1: pass
arm64_fp-stress_FPSIMD-4-0: pass
arm64_fp-stress_FPSIMD-4-1: pass
arm64_fp-stress_FPSIMD-5-0: pass
arm64_fp-stress_FPSIMD-5-1: pass
arm64_fp-stress_FPSIMD-6-0: pass
arm64_fp-stress_FPSIMD-6-1: pass
arm64_fp-stress_FPSIMD-7-0: pass
arm64_fp-stress_FPSIMD-7-1: pass
arm64_hwcap: pass
arm64_hwcap_cpuinfo_match_RNG: pass
arm64_hwcap_cpuinfo_match_SME: pass
arm64_hwcap_cpuinfo_match_SVE: pass
arm64_hwcap_cpuinfo_match_SVE2_BF16: pass
arm64_hwcap_cpuinfo_match_SVE2_BITPERM: pass
arm64_hwcap_cpuinfo_match_SVE2_EBF16: pass
arm64_hwcap_cpuinfo_match_SVE2_F32MM: pass
arm64_hwcap_cpuinfo_match_SVE2_F64MM: pass
arm64_hwcap_cpuinfo_match_SVE2_I8MM: pass
arm64_hwcap_cpuinfo_match_SVE2_PMULL: pass
arm64_hwcap_cpuinfo_match_SVE2_SHA3: pass
arm64_hwcap_cpuinfo_match_SVE2_SM4: pass
arm64_hwcap_cpuinfo_match_SVE_2: pass
arm64_hwcap_cpuinfo_match_SVE_AES: pass
arm64_hwcap_sigill_RNG: skip
arm64_hwcap_sigill_SME: pass
arm64_hwcap_sigill_SVE: pass
arm64_hwcap_sigill_SVE2_BF16: skip
arm64_hwcap_sigill_SVE2_BITPERM: skip
arm64_hwcap_sigill_SVE2_EBF16: skip
arm64_hwcap_sigill_SVE2_F32MM: skip
arm64_hwcap_sigill_SVE2_F64MM: skip
arm64_hwcap_sigill_SVE2_I8MM: skip
arm64_hwcap_sigill_SVE2_PMULL: skip
arm64_hwcap_sigill_SVE2_SHA3: skip
arm64_hwcap_sigill_SVE2_SM4: skip
arm64_hwcap_sigill_SVE_2: skip
arm64_hwcap_sigill_SVE_AES: skip
arm64_mangle_pstate_invalid_compat_toggle: pass
arm64_mangle_pstate_invalid_daif_bits: pass
arm64_mangle_pstate_invalid_mode_el1h: pass
arm64_mangle_pstate_invalid_mode_el1t: pass
arm64_mangle_pstate_invalid_mode_el2h: pass
arm64_mangle_pstate_invalid_mode_el2t: pass
arm64_mangle_pstate_invalid_mode_el3h: pass
arm64_mangle_pstate_invalid_mode_el3t: pass
arm64_nobtitest: pass
arm64_nobtitest_bti_c_func_call_using_blr: skip
arm64_nobtitest_bti_c_func_call_using_br_x0: skip
arm64_nobtitest_bti_c_func_call_using_br_x16: skip
arm64_nobtitest_bti_j_func_call_using_blr: skip
arm64_nobtitest_bti_j_func_call_using_br_x0: skip
arm64_nobtitest_bti_j_func_call_using_br_x16: skip
arm64_nobtitest_bti_jc_func_call_using_blr: skip
arm64_nobtitest_bti_jc_func_call_using_br_x0: skip
arm64_nobtitest_bti_jc_func_call_using_br_x16: skip
arm64_nobtitest_bti_none_func_call_using_blr: skip
arm64_nobtitest_bti_none_func_call_using_br_x0: skip
arm64_nobtitest_bti_none_func_call_using_br_x16: skip
arm64_nobtitest_nohint_func_call_using_blr: skip
arm64_nobtitest_nohint_func_call_using_br_x0: skip
arm64_nobtitest_nohint_func_call_using_br_x16: skip
arm64_nobtitest_paciasp_func_call_using_blr: skip
arm64_nobtitest_paciasp_func_call_using_br_x0: skip
arm64_nobtitest_paciasp_func_call_using_br_x16: skip
arm64_pac: pass
arm64_pac_Generic_PAUTH_not_enabled: skip
arm64_pac_Generic_PAUTH_not_enabled_dup2: skip
arm64_pac_PAUTH_not_enabled: skip
arm64_pac_PAUTH_not_enabled_dup2: skip
arm64_pac_PAUTH_not_enabled_dup3: skip
arm64_pac_PAUTH_not_enabled_dup4: skip
arm64_pac_PAUTH_not_enabled_dup5: skip
arm64_ptrace: pass
arm64_ptrace_count_tpidrs: pass
arm64_ptrace_read_tpidr_one: pass
arm64_ptrace_tpidr2_read: pass
arm64_ptrace_tpidr2_write: pass
arm64_ptrace_verify_tpidr_one: pass
arm64_ptrace_write_tpidr_one: pass
arm64_ptrace_write_tpidr_only: pass
arm64_run_tags_test_sh: pass
arm64_sme_trap_no_sm: skip
arm64_sme_trap_non_streaming: skip
arm64_sme_trap_za: pass
arm64_sme_vl: skip
arm64_ssve_regs: skip
arm64_sve-probe-vls: skip
arm64_sve-probe-vls_SVE_not_available: skip
arm64_sve-ptrace: skip
arm64_sve-ptrace_SVE_not_available: skip
arm64_sve_regs: skip
arm64_sve_vl: skip
arm64_syscall-abi: pass
arm64_syscall-abi_getpid_FPSIMD: pass
arm64_syscall-abi_sched_yield_FPSIMD: pass
arm64_tags_test: pass
arm64_tpidr2: pass
arm64_tpidr2_skipped_TPIDR2_not_supported: pass
arm64_tpidr2_skipped_TPIDR2_not_supported_dup2: pass
arm64_tpidr2_skipped_TPIDR2_not_supported_dup3: pass
arm64_tpidr2_skipped_TPIDR2_not_supported_dup4: pass
arm64_tpidr2_skipped_TPIDR2_not_supported_dup5: pass
arm64_vec-syscfg: pass
arm64_vec-syscfg_SME_not_supported: skip
arm64_vec-syscfg_SME_not_supported_dup10: skip
arm64_vec-syscfg_SME_not_supported_dup2: skip
arm64_vec-syscfg_SME_not_supported_dup3: skip
arm64_vec-syscfg_SME_not_supported_dup4: skip
arm64_vec-syscfg_SME_not_supported_dup5: skip
arm64_vec-syscfg_SME_not_supported_dup6: skip
arm64_vec-syscfg_SME_not_supported_dup7: skip
arm64_vec-syscfg_SME_not_supported_dup8: skip
arm64_vec-syscfg_SME_not_supported_dup9: skip
arm64_vec-syscfg_SVE_not_supported: skip
arm64_vec-syscfg_SVE_not_supported_dup10: skip
arm64_vec-syscfg_SVE_not_supported_dup2: skip
arm64_vec-syscfg_SVE_not_supported_dup3: skip
arm64_vec-syscfg_SVE_not_supported_dup4: skip
arm64_vec-syscfg_SVE_not_supported_dup5: skip
arm64_vec-syscfg_SVE_not_supported_dup6: skip
arm64_vec-syscfg_SVE_not_supported_dup7: skip
arm64_vec-syscfg_SVE_not_supported_dup8: skip
arm64_vec-syscfg_SVE_not_supported_dup9: skip
arm64_za-fork: pass
arm64_za-fork_skipped: pass
arm64_za-ptrace: skip
arm64_za-ptrace_SME_not_available: skip
arm64_za_no_regs: skip
arm64_za_regs: skip
shardfile-arm64: pass
12616 00:45:57.855334 end: 3.1 lava-test-shell (duration 00:00:37) [common]
12617 00:45:57.855420 end: 3 lava-test-retry (duration 00:00:37) [common]
12618 00:45:57.855504 start: 4 finalize (timeout 00:06:59) [common]
12619 00:45:57.855590 start: 4.1 power-off (timeout 00:00:30) [common]
12620 00:45:57.855767 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-9', '--port=1', '--command=off']
12621 00:45:58.053989 >> Command sent successfully.
12622 00:45:58.056281 Returned 0 in 0 seconds
12623 00:45:58.156677 end: 4.1 power-off (duration 00:00:00) [common]
12625 00:45:58.156997 start: 4.2 read-feedback (timeout 00:06:59) [common]
12626 00:45:58.157248 Listened to connection for namespace 'common' for up to 1s
12627 00:45:59.158192 Finalising connection for namespace 'common'
12628 00:45:59.158378 Disconnecting from shell: Finalise
12629 00:45:59.158452 / #
12630 00:45:59.258772 end: 4.2 read-feedback (duration 00:00:01) [common]
12631 00:45:59.258940 end: 4 finalize (duration 00:00:01) [common]
12632 00:45:59.259051 Cleaning after the job
12633 00:45:59.259149 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14368400/tftp-deploy-4dnvlh_0/ramdisk
12634 00:45:59.261282 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14368400/tftp-deploy-4dnvlh_0/kernel
12635 00:45:59.271834 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14368400/tftp-deploy-4dnvlh_0/dtb
12636 00:45:59.272005 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14368400/tftp-deploy-4dnvlh_0/nfsrootfs
12637 00:45:59.336912 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14368400/tftp-deploy-4dnvlh_0/modules
12638 00:45:59.342709 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14368400
12639 00:45:59.918640 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14368400
12640 00:45:59.918825 Job finished correctly