Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 21
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 24
1 00:43:50.464317 lava-dispatcher, installed at version: 2024.03
2 00:43:50.464513 start: 0 validate
3 00:43:50.464699 Start time: 2024-06-16 00:43:50.464691+00:00 (UTC)
4 00:43:50.464818 Using caching service: 'http://localhost/cache/?uri=%s'
5 00:43:50.464944 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 00:43:50.718558 Using caching service: 'http://localhost/cache/?uri=%s'
7 00:43:50.719310 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22-24-g0315de64ea248%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 00:43:50.972926 Using caching service: 'http://localhost/cache/?uri=%s'
9 00:43:50.973666 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22-24-g0315de64ea248%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 00:43:51.226751 Using caching service: 'http://localhost/cache/?uri=%s'
11 00:43:51.227545 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 00:43:51.480422 Using caching service: 'http://localhost/cache/?uri=%s'
13 00:43:51.481248 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22-24-g0315de64ea248%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 00:43:51.742496 validate duration: 1.28
16 00:43:51.743831 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 00:43:51.744395 start: 1.1 download-retry (timeout 00:10:00) [common]
18 00:43:51.744912 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 00:43:51.745539 Not decompressing ramdisk as can be used compressed.
20 00:43:51.746030 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 00:43:51.746401 saving as /var/lib/lava/dispatcher/tmp/14368392/tftp-deploy-ut6dle8v/ramdisk/initrd.cpio.gz
22 00:43:51.746777 total size: 5628169 (5 MB)
23 00:43:51.751984 progress 0 % (0 MB)
24 00:43:51.761106 progress 5 % (0 MB)
25 00:43:51.769059 progress 10 % (0 MB)
26 00:43:51.773838 progress 15 % (0 MB)
27 00:43:51.778034 progress 20 % (1 MB)
28 00:43:51.781225 progress 25 % (1 MB)
29 00:43:51.784306 progress 30 % (1 MB)
30 00:43:51.787244 progress 35 % (1 MB)
31 00:43:51.789557 progress 40 % (2 MB)
32 00:43:51.792088 progress 45 % (2 MB)
33 00:43:51.794052 progress 50 % (2 MB)
34 00:43:51.796228 progress 55 % (2 MB)
35 00:43:51.798250 progress 60 % (3 MB)
36 00:43:51.799973 progress 65 % (3 MB)
37 00:43:51.801919 progress 70 % (3 MB)
38 00:43:51.803471 progress 75 % (4 MB)
39 00:43:51.805212 progress 80 % (4 MB)
40 00:43:51.806766 progress 85 % (4 MB)
41 00:43:51.808372 progress 90 % (4 MB)
42 00:43:51.809957 progress 95 % (5 MB)
43 00:43:51.811392 progress 100 % (5 MB)
44 00:43:51.811607 5 MB downloaded in 0.06 s (82.77 MB/s)
45 00:43:51.811766 end: 1.1.1 http-download (duration 00:00:00) [common]
47 00:43:51.812032 end: 1.1 download-retry (duration 00:00:00) [common]
48 00:43:51.812120 start: 1.2 download-retry (timeout 00:10:00) [common]
49 00:43:51.812205 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 00:43:51.812338 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-24-g0315de64ea248/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 00:43:51.812413 saving as /var/lib/lava/dispatcher/tmp/14368392/tftp-deploy-ut6dle8v/kernel/Image
52 00:43:51.812474 total size: 54813184 (52 MB)
53 00:43:51.812536 No compression specified
54 00:43:51.813665 progress 0 % (0 MB)
55 00:43:51.827205 progress 5 % (2 MB)
56 00:43:51.840875 progress 10 % (5 MB)
57 00:43:51.854214 progress 15 % (7 MB)
58 00:43:51.867871 progress 20 % (10 MB)
59 00:43:51.881600 progress 25 % (13 MB)
60 00:43:51.895093 progress 30 % (15 MB)
61 00:43:51.908600 progress 35 % (18 MB)
62 00:43:51.922200 progress 40 % (20 MB)
63 00:43:51.935612 progress 45 % (23 MB)
64 00:43:51.949144 progress 50 % (26 MB)
65 00:43:51.962855 progress 55 % (28 MB)
66 00:43:51.976276 progress 60 % (31 MB)
67 00:43:51.989917 progress 65 % (34 MB)
68 00:43:52.003537 progress 70 % (36 MB)
69 00:43:52.017158 progress 75 % (39 MB)
70 00:43:52.030716 progress 80 % (41 MB)
71 00:43:52.044129 progress 85 % (44 MB)
72 00:43:52.057685 progress 90 % (47 MB)
73 00:43:52.071149 progress 95 % (49 MB)
74 00:43:52.084375 progress 100 % (52 MB)
75 00:43:52.084633 52 MB downloaded in 0.27 s (192.07 MB/s)
76 00:43:52.084786 end: 1.2.1 http-download (duration 00:00:00) [common]
78 00:43:52.085021 end: 1.2 download-retry (duration 00:00:00) [common]
79 00:43:52.085110 start: 1.3 download-retry (timeout 00:10:00) [common]
80 00:43:52.085197 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 00:43:52.085329 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-24-g0315de64ea248/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 00:43:52.085399 saving as /var/lib/lava/dispatcher/tmp/14368392/tftp-deploy-ut6dle8v/dtb/mt8192-asurada-spherion-r0.dtb
83 00:43:52.085478 total size: 47258 (0 MB)
84 00:43:52.085545 No compression specified
85 00:43:52.086662 progress 69 % (0 MB)
86 00:43:52.086930 progress 100 % (0 MB)
87 00:43:52.087083 0 MB downloaded in 0.00 s (28.11 MB/s)
88 00:43:52.087207 end: 1.3.1 http-download (duration 00:00:00) [common]
90 00:43:52.087435 end: 1.3 download-retry (duration 00:00:00) [common]
91 00:43:52.087520 start: 1.4 download-retry (timeout 00:10:00) [common]
92 00:43:52.087603 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 00:43:52.087714 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 00:43:52.087783 saving as /var/lib/lava/dispatcher/tmp/14368392/tftp-deploy-ut6dle8v/nfsrootfs/full.rootfs.tar
95 00:43:52.087844 total size: 120894716 (115 MB)
96 00:43:52.087906 Using unxz to decompress xz
97 00:43:52.091441 progress 0 % (0 MB)
98 00:43:52.440405 progress 5 % (5 MB)
99 00:43:52.810089 progress 10 % (11 MB)
100 00:43:53.163567 progress 15 % (17 MB)
101 00:43:53.493916 progress 20 % (23 MB)
102 00:43:53.787429 progress 25 % (28 MB)
103 00:43:54.153888 progress 30 % (34 MB)
104 00:43:54.499593 progress 35 % (40 MB)
105 00:43:54.663946 progress 40 % (46 MB)
106 00:43:54.843078 progress 45 % (51 MB)
107 00:43:55.159677 progress 50 % (57 MB)
108 00:43:55.540748 progress 55 % (63 MB)
109 00:43:55.885552 progress 60 % (69 MB)
110 00:43:56.223441 progress 65 % (74 MB)
111 00:43:56.566043 progress 70 % (80 MB)
112 00:43:56.922967 progress 75 % (86 MB)
113 00:43:57.260636 progress 80 % (92 MB)
114 00:43:57.597278 progress 85 % (98 MB)
115 00:43:57.956334 progress 90 % (103 MB)
116 00:43:58.283319 progress 95 % (109 MB)
117 00:43:58.639504 progress 100 % (115 MB)
118 00:43:58.644953 115 MB downloaded in 6.56 s (17.58 MB/s)
119 00:43:58.645193 end: 1.4.1 http-download (duration 00:00:07) [common]
121 00:43:58.645469 end: 1.4 download-retry (duration 00:00:07) [common]
122 00:43:58.645565 start: 1.5 download-retry (timeout 00:09:53) [common]
123 00:43:58.645659 start: 1.5.1 http-download (timeout 00:09:53) [common]
124 00:43:58.645813 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-24-g0315de64ea248/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 00:43:58.645893 saving as /var/lib/lava/dispatcher/tmp/14368392/tftp-deploy-ut6dle8v/modules/modules.tar
126 00:43:58.645957 total size: 8608736 (8 MB)
127 00:43:58.646025 Using unxz to decompress xz
128 00:43:58.649666 progress 0 % (0 MB)
129 00:43:58.668491 progress 5 % (0 MB)
130 00:43:58.695713 progress 10 % (0 MB)
131 00:43:58.725555 progress 15 % (1 MB)
132 00:43:58.749117 progress 20 % (1 MB)
133 00:43:58.772777 progress 25 % (2 MB)
134 00:43:58.796425 progress 30 % (2 MB)
135 00:43:58.820913 progress 35 % (2 MB)
136 00:43:58.847658 progress 40 % (3 MB)
137 00:43:58.870529 progress 45 % (3 MB)
138 00:43:58.895036 progress 50 % (4 MB)
139 00:43:58.921784 progress 55 % (4 MB)
140 00:43:58.946591 progress 60 % (4 MB)
141 00:43:58.971148 progress 65 % (5 MB)
142 00:43:58.996331 progress 70 % (5 MB)
143 00:43:59.022507 progress 75 % (6 MB)
144 00:43:59.048838 progress 80 % (6 MB)
145 00:43:59.073393 progress 85 % (7 MB)
146 00:43:59.098828 progress 90 % (7 MB)
147 00:43:59.124775 progress 95 % (7 MB)
148 00:43:59.150232 progress 100 % (8 MB)
149 00:43:59.156011 8 MB downloaded in 0.51 s (16.10 MB/s)
150 00:43:59.156300 end: 1.5.1 http-download (duration 00:00:01) [common]
152 00:43:59.156738 end: 1.5 download-retry (duration 00:00:01) [common]
153 00:43:59.156866 start: 1.6 prepare-tftp-overlay (timeout 00:09:53) [common]
154 00:43:59.156991 start: 1.6.1 extract-nfsrootfs (timeout 00:09:53) [common]
155 00:44:02.686175 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/14368392/extract-nfsrootfs-_yqx9ly3
156 00:44:02.686381 end: 1.6.1 extract-nfsrootfs (duration 00:00:04) [common]
157 00:44:02.686483 start: 1.6.2 lava-overlay (timeout 00:09:49) [common]
158 00:44:02.686651 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14368392/lava-overlay-9ff4ufwo
159 00:44:02.686777 makedir: /var/lib/lava/dispatcher/tmp/14368392/lava-overlay-9ff4ufwo/lava-14368392/bin
160 00:44:02.686877 makedir: /var/lib/lava/dispatcher/tmp/14368392/lava-overlay-9ff4ufwo/lava-14368392/tests
161 00:44:02.686972 makedir: /var/lib/lava/dispatcher/tmp/14368392/lava-overlay-9ff4ufwo/lava-14368392/results
162 00:44:02.687073 Creating /var/lib/lava/dispatcher/tmp/14368392/lava-overlay-9ff4ufwo/lava-14368392/bin/lava-add-keys
163 00:44:02.687213 Creating /var/lib/lava/dispatcher/tmp/14368392/lava-overlay-9ff4ufwo/lava-14368392/bin/lava-add-sources
164 00:44:02.687337 Creating /var/lib/lava/dispatcher/tmp/14368392/lava-overlay-9ff4ufwo/lava-14368392/bin/lava-background-process-start
165 00:44:02.687461 Creating /var/lib/lava/dispatcher/tmp/14368392/lava-overlay-9ff4ufwo/lava-14368392/bin/lava-background-process-stop
166 00:44:02.687583 Creating /var/lib/lava/dispatcher/tmp/14368392/lava-overlay-9ff4ufwo/lava-14368392/bin/lava-common-functions
167 00:44:02.687703 Creating /var/lib/lava/dispatcher/tmp/14368392/lava-overlay-9ff4ufwo/lava-14368392/bin/lava-echo-ipv4
168 00:44:02.687824 Creating /var/lib/lava/dispatcher/tmp/14368392/lava-overlay-9ff4ufwo/lava-14368392/bin/lava-install-packages
169 00:44:02.687944 Creating /var/lib/lava/dispatcher/tmp/14368392/lava-overlay-9ff4ufwo/lava-14368392/bin/lava-installed-packages
170 00:44:02.688062 Creating /var/lib/lava/dispatcher/tmp/14368392/lava-overlay-9ff4ufwo/lava-14368392/bin/lava-os-build
171 00:44:02.688183 Creating /var/lib/lava/dispatcher/tmp/14368392/lava-overlay-9ff4ufwo/lava-14368392/bin/lava-probe-channel
172 00:44:02.688302 Creating /var/lib/lava/dispatcher/tmp/14368392/lava-overlay-9ff4ufwo/lava-14368392/bin/lava-probe-ip
173 00:44:02.688420 Creating /var/lib/lava/dispatcher/tmp/14368392/lava-overlay-9ff4ufwo/lava-14368392/bin/lava-target-ip
174 00:44:02.688541 Creating /var/lib/lava/dispatcher/tmp/14368392/lava-overlay-9ff4ufwo/lava-14368392/bin/lava-target-mac
175 00:44:02.688704 Creating /var/lib/lava/dispatcher/tmp/14368392/lava-overlay-9ff4ufwo/lava-14368392/bin/lava-target-storage
176 00:44:02.688828 Creating /var/lib/lava/dispatcher/tmp/14368392/lava-overlay-9ff4ufwo/lava-14368392/bin/lava-test-case
177 00:44:02.688950 Creating /var/lib/lava/dispatcher/tmp/14368392/lava-overlay-9ff4ufwo/lava-14368392/bin/lava-test-event
178 00:44:02.689073 Creating /var/lib/lava/dispatcher/tmp/14368392/lava-overlay-9ff4ufwo/lava-14368392/bin/lava-test-feedback
179 00:44:02.689194 Creating /var/lib/lava/dispatcher/tmp/14368392/lava-overlay-9ff4ufwo/lava-14368392/bin/lava-test-raise
180 00:44:02.689312 Creating /var/lib/lava/dispatcher/tmp/14368392/lava-overlay-9ff4ufwo/lava-14368392/bin/lava-test-reference
181 00:44:02.689434 Creating /var/lib/lava/dispatcher/tmp/14368392/lava-overlay-9ff4ufwo/lava-14368392/bin/lava-test-runner
182 00:44:02.689555 Creating /var/lib/lava/dispatcher/tmp/14368392/lava-overlay-9ff4ufwo/lava-14368392/bin/lava-test-set
183 00:44:02.689675 Creating /var/lib/lava/dispatcher/tmp/14368392/lava-overlay-9ff4ufwo/lava-14368392/bin/lava-test-shell
184 00:44:02.689795 Updating /var/lib/lava/dispatcher/tmp/14368392/lava-overlay-9ff4ufwo/lava-14368392/bin/lava-add-keys (debian)
185 00:44:02.689943 Updating /var/lib/lava/dispatcher/tmp/14368392/lava-overlay-9ff4ufwo/lava-14368392/bin/lava-add-sources (debian)
186 00:44:02.690086 Updating /var/lib/lava/dispatcher/tmp/14368392/lava-overlay-9ff4ufwo/lava-14368392/bin/lava-install-packages (debian)
187 00:44:02.690219 Updating /var/lib/lava/dispatcher/tmp/14368392/lava-overlay-9ff4ufwo/lava-14368392/bin/lava-installed-packages (debian)
188 00:44:02.690360 Updating /var/lib/lava/dispatcher/tmp/14368392/lava-overlay-9ff4ufwo/lava-14368392/bin/lava-os-build (debian)
189 00:44:02.690482 Creating /var/lib/lava/dispatcher/tmp/14368392/lava-overlay-9ff4ufwo/lava-14368392/environment
190 00:44:02.690580 LAVA metadata
191 00:44:02.690646 - LAVA_JOB_ID=14368392
192 00:44:02.690708 - LAVA_DISPATCHER_IP=192.168.201.1
193 00:44:02.690808 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:49) [common]
194 00:44:02.690874 skipped lava-vland-overlay
195 00:44:02.690948 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 00:44:02.691027 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:49) [common]
197 00:44:02.691087 skipped lava-multinode-overlay
198 00:44:02.691158 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 00:44:02.691235 start: 1.6.2.3 test-definition (timeout 00:09:49) [common]
200 00:44:02.691307 Loading test definitions
201 00:44:02.691396 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:49) [common]
202 00:44:02.691465 Using /lava-14368392 at stage 0
203 00:44:02.691730 uuid=14368392_1.6.2.3.1 testdef=None
204 00:44:02.691818 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 00:44:02.691902 start: 1.6.2.3.2 test-overlay (timeout 00:09:49) [common]
206 00:44:02.692349 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 00:44:02.692609 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:49) [common]
209 00:44:02.693165 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 00:44:02.693399 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:49) [common]
212 00:44:02.693931 runner path: /var/lib/lava/dispatcher/tmp/14368392/lava-overlay-9ff4ufwo/lava-14368392/0/tests/0_timesync-off test_uuid 14368392_1.6.2.3.1
213 00:44:02.694085 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 00:44:02.694312 start: 1.6.2.3.5 git-repo-action (timeout 00:09:49) [common]
216 00:44:02.694384 Using /lava-14368392 at stage 0
217 00:44:02.694479 Fetching tests from https://github.com/kernelci/test-definitions.git
218 00:44:02.694565 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/14368392/lava-overlay-9ff4ufwo/lava-14368392/0/tests/1_kselftest-rtc'
219 00:44:04.410148 Running '/usr/bin/git checkout kernelci.org
220 00:44:04.555278 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/14368392/lava-overlay-9ff4ufwo/lava-14368392/0/tests/1_kselftest-rtc/automated/linux/kselftest/kselftest.yaml
221 00:44:04.555985 uuid=14368392_1.6.2.3.5 testdef=None
222 00:44:04.556145 end: 1.6.2.3.5 git-repo-action (duration 00:00:02) [common]
224 00:44:04.556400 start: 1.6.2.3.6 test-overlay (timeout 00:09:47) [common]
225 00:44:04.557193 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 00:44:04.557426 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:47) [common]
228 00:44:04.558413 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 00:44:04.558678 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:47) [common]
231 00:44:04.559613 runner path: /var/lib/lava/dispatcher/tmp/14368392/lava-overlay-9ff4ufwo/lava-14368392/0/tests/1_kselftest-rtc test_uuid 14368392_1.6.2.3.5
232 00:44:04.559705 BOARD='mt8192-asurada-spherion-r0'
233 00:44:04.559770 BRANCH='cip'
234 00:44:04.559834 SKIPFILE='/dev/null'
235 00:44:04.559894 SKIP_INSTALL='True'
236 00:44:04.559951 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-24-g0315de64ea248/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 00:44:04.560008 TST_CASENAME=''
238 00:44:04.560069 TST_CMDFILES='rtc'
239 00:44:04.560207 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 00:44:04.560415 Creating lava-test-runner.conf files
242 00:44:04.560483 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14368392/lava-overlay-9ff4ufwo/lava-14368392/0 for stage 0
243 00:44:04.560615 - 0_timesync-off
244 00:44:04.560685 - 1_kselftest-rtc
245 00:44:04.560782 end: 1.6.2.3 test-definition (duration 00:00:02) [common]
246 00:44:04.560871 start: 1.6.2.4 compress-overlay (timeout 00:09:47) [common]
247 00:44:12.101478 end: 1.6.2.4 compress-overlay (duration 00:00:08) [common]
248 00:44:12.101642 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:40) [common]
249 00:44:12.101770 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 00:44:12.101868 end: 1.6.2 lava-overlay (duration 00:00:09) [common]
251 00:44:12.101960 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:40) [common]
252 00:44:12.262817 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 00:44:12.263179 start: 1.6.4 extract-modules (timeout 00:09:39) [common]
254 00:44:12.263293 extracting modules file /var/lib/lava/dispatcher/tmp/14368392/tftp-deploy-ut6dle8v/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14368392/extract-nfsrootfs-_yqx9ly3
255 00:44:12.463793 extracting modules file /var/lib/lava/dispatcher/tmp/14368392/tftp-deploy-ut6dle8v/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14368392/extract-overlay-ramdisk-nbbvk2pq/ramdisk
256 00:44:12.683792 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 00:44:12.683965 start: 1.6.5 apply-overlay-tftp (timeout 00:09:39) [common]
258 00:44:12.684073 [common] Applying overlay to NFS
259 00:44:12.684146 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14368392/compress-overlay-tj1n_hsu/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14368392/extract-nfsrootfs-_yqx9ly3
260 00:44:13.584805 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 00:44:13.584977 start: 1.6.6 configure-preseed-file (timeout 00:09:38) [common]
262 00:44:13.585077 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 00:44:13.585166 start: 1.6.7 compress-ramdisk (timeout 00:09:38) [common]
264 00:44:13.585246 Building ramdisk /var/lib/lava/dispatcher/tmp/14368392/extract-overlay-ramdisk-nbbvk2pq/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14368392/extract-overlay-ramdisk-nbbvk2pq/ramdisk
265 00:44:13.914715 >> 130405 blocks
266 00:44:15.983316 rename /var/lib/lava/dispatcher/tmp/14368392/extract-overlay-ramdisk-nbbvk2pq/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14368392/tftp-deploy-ut6dle8v/ramdisk/ramdisk.cpio.gz
267 00:44:15.983741 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 00:44:15.983871 start: 1.6.8 prepare-kernel (timeout 00:09:36) [common]
269 00:44:15.983974 start: 1.6.8.1 prepare-fit (timeout 00:09:36) [common]
270 00:44:15.984081 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14368392/tftp-deploy-ut6dle8v/kernel/Image']
271 00:44:29.065164 Returned 0 in 13 seconds
272 00:44:29.166235 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14368392/tftp-deploy-ut6dle8v/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14368392/tftp-deploy-ut6dle8v/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14368392/tftp-deploy-ut6dle8v/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14368392/tftp-deploy-ut6dle8v/kernel/image.itb
273 00:44:29.568020 output: FIT description: Kernel Image image with one or more FDT blobs
274 00:44:29.568376 output: Created: Sun Jun 16 01:44:29 2024
275 00:44:29.568489 output: Image 0 (kernel-1)
276 00:44:29.568591 output: Description:
277 00:44:29.568693 output: Created: Sun Jun 16 01:44:29 2024
278 00:44:29.568793 output: Type: Kernel Image
279 00:44:29.568892 output: Compression: lzma compressed
280 00:44:29.568988 output: Data Size: 13126376 Bytes = 12818.73 KiB = 12.52 MiB
281 00:44:29.569083 output: Architecture: AArch64
282 00:44:29.569183 output: OS: Linux
283 00:44:29.569272 output: Load Address: 0x00000000
284 00:44:29.569359 output: Entry Point: 0x00000000
285 00:44:29.569445 output: Hash algo: crc32
286 00:44:29.569532 output: Hash value: c791a20a
287 00:44:29.569616 output: Image 1 (fdt-1)
288 00:44:29.569700 output: Description: mt8192-asurada-spherion-r0
289 00:44:29.569786 output: Created: Sun Jun 16 01:44:29 2024
290 00:44:29.569868 output: Type: Flat Device Tree
291 00:44:29.569948 output: Compression: uncompressed
292 00:44:29.570030 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
293 00:44:29.570111 output: Architecture: AArch64
294 00:44:29.570192 output: Hash algo: crc32
295 00:44:29.570273 output: Hash value: 0f8e4d2e
296 00:44:29.570354 output: Image 2 (ramdisk-1)
297 00:44:29.570434 output: Description: unavailable
298 00:44:29.570515 output: Created: Sun Jun 16 01:44:29 2024
299 00:44:29.570596 output: Type: RAMDisk Image
300 00:44:29.570677 output: Compression: Unknown Compression
301 00:44:29.570758 output: Data Size: 18739632 Bytes = 18300.42 KiB = 17.87 MiB
302 00:44:29.570839 output: Architecture: AArch64
303 00:44:29.570920 output: OS: Linux
304 00:44:29.571001 output: Load Address: unavailable
305 00:44:29.571081 output: Entry Point: unavailable
306 00:44:29.571162 output: Hash algo: crc32
307 00:44:29.571243 output: Hash value: 25c4305c
308 00:44:29.571323 output: Default Configuration: 'conf-1'
309 00:44:29.571404 output: Configuration 0 (conf-1)
310 00:44:29.571484 output: Description: mt8192-asurada-spherion-r0
311 00:44:29.571565 output: Kernel: kernel-1
312 00:44:29.571646 output: Init Ramdisk: ramdisk-1
313 00:44:29.571726 output: FDT: fdt-1
314 00:44:29.571807 output: Loadables: kernel-1
315 00:44:29.571887 output:
316 00:44:29.572110 end: 1.6.8.1 prepare-fit (duration 00:00:14) [common]
317 00:44:29.572237 end: 1.6.8 prepare-kernel (duration 00:00:14) [common]
318 00:44:29.572376 end: 1.6 prepare-tftp-overlay (duration 00:00:30) [common]
319 00:44:29.572496 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:22) [common]
320 00:44:29.572637 No LXC device requested
321 00:44:29.572745 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 00:44:29.572863 start: 1.8 deploy-device-env (timeout 00:09:22) [common]
323 00:44:29.572969 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 00:44:29.573063 Checking files for TFTP limit of 4294967296 bytes.
325 00:44:29.573692 end: 1 tftp-deploy (duration 00:00:38) [common]
326 00:44:29.573823 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 00:44:29.573943 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 00:44:29.574106 substitutions:
329 00:44:29.574199 - {DTB}: 14368392/tftp-deploy-ut6dle8v/dtb/mt8192-asurada-spherion-r0.dtb
330 00:44:29.574291 - {INITRD}: 14368392/tftp-deploy-ut6dle8v/ramdisk/ramdisk.cpio.gz
331 00:44:29.574378 - {KERNEL}: 14368392/tftp-deploy-ut6dle8v/kernel/Image
332 00:44:29.574463 - {LAVA_MAC}: None
333 00:44:29.574547 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/14368392/extract-nfsrootfs-_yqx9ly3
334 00:44:29.574631 - {NFS_SERVER_IP}: 192.168.201.1
335 00:44:29.574713 - {PRESEED_CONFIG}: None
336 00:44:29.574796 - {PRESEED_LOCAL}: None
337 00:44:29.574878 - {RAMDISK}: 14368392/tftp-deploy-ut6dle8v/ramdisk/ramdisk.cpio.gz
338 00:44:29.574961 - {ROOT_PART}: None
339 00:44:29.575043 - {ROOT}: None
340 00:44:29.575125 - {SERVER_IP}: 192.168.201.1
341 00:44:29.575208 - {TEE}: None
342 00:44:29.575290 Parsed boot commands:
343 00:44:29.575371 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 00:44:29.575586 Parsed boot commands: tftpboot 192.168.201.1 14368392/tftp-deploy-ut6dle8v/kernel/image.itb 14368392/tftp-deploy-ut6dle8v/kernel/cmdline
345 00:44:29.575699 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 00:44:29.575813 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 00:44:29.575933 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 00:44:29.576047 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 00:44:29.576146 Not connected, no need to disconnect.
350 00:44:29.576248 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 00:44:29.576357 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 00:44:29.576450 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-1'
353 00:44:29.579662 Setting prompt string to ['lava-test: # ']
354 00:44:29.580010 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 00:44:29.580145 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 00:44:29.580318 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 00:44:29.580437 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 00:44:29.580653 Calling: ['/usr/local/bin/chromebook-reboot.sh', 'mt8192-asurada-spherion-r0-cbg-1']
359 00:44:43.201684 Returned 0 in 13 seconds
360 00:44:43.302746 end: 2.2.2.1 pdu-reboot (duration 00:00:14) [common]
362 00:44:43.304431 end: 2.2.2 reset-device (duration 00:00:14) [common]
363 00:44:43.305058 start: 2.2.3 depthcharge-start (timeout 00:04:46) [common]
364 00:44:43.305535 Setting prompt string to 'Starting depthcharge on Spherion...'
365 00:44:43.305924 Changing prompt to 'Starting depthcharge on Spherion...'
366 00:44:43.306316 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
367 00:44:43.308449 [Enter `^Ec?' for help]
368 00:44:43.308967
369 00:44:43.309339
370 00:44:43.309704 F0: 102B 0000
371 00:44:43.310059
372 00:44:43.310524 F3: 1001 0000 [0200]
373 00:44:43.310876
374 00:44:43.311228 F3: 1001 0000
375 00:44:43.311551
376 00:44:43.311868 F7: 102D 0000
377 00:44:43.312181
378 00:44:43.312492 F1: 0000 0000
379 00:44:43.312995
380 00:44:43.313323 V0: 0000 0000 [0001]
381 00:44:43.313744
382 00:44:43.314067 00: 0007 8000
383 00:44:43.314392
384 00:44:43.314705 01: 0000 0000
385 00:44:43.315024
386 00:44:43.315331 BP: 0C00 0209 [0000]
387 00:44:43.315643
388 00:44:43.315948 G0: 1182 0000
389 00:44:43.316256
390 00:44:43.316618 EC: 0000 0021 [4000]
391 00:44:43.316938
392 00:44:43.317363 S7: 0000 0000 [0000]
393 00:44:43.317682
394 00:44:43.317989 CC: 0000 0000 [0001]
395 00:44:43.318295
396 00:44:43.318599 T0: 0000 0040 [010F]
397 00:44:43.318909
398 00:44:43.319213 Jump to BL
399 00:44:43.319524
400 00:44:43.319831
401 00:44:43.320137
402 00:44:43.320571 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
403 00:44:43.320934 ARM64: Exception handlers installed.
404 00:44:43.321259 ARM64: Testing exception
405 00:44:43.321567 ARM64: Done test exception
406 00:44:43.321873 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
407 00:44:43.322185 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
408 00:44:43.322497 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
409 00:44:43.322805 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
410 00:44:43.323115 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
411 00:44:43.323426 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
412 00:44:43.323844 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
413 00:44:43.324167 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
414 00:44:43.324477 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
415 00:44:43.324828 WDT: Last reset was cold boot
416 00:44:43.325153 SPI1(PAD0) initialized at 2873684 Hz
417 00:44:43.325463 SPI5(PAD0) initialized at 992727 Hz
418 00:44:43.325767 VBOOT: Loading verstage.
419 00:44:43.326131 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
420 00:44:43.326447 FMAP: Found "FLASH" version 1.1 at 0x20000.
421 00:44:43.326762 FMAP: base = 0x0 size = 0x800000 #areas = 25
422 00:44:43.327152 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
423 00:44:43.327481 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
424 00:44:43.327812 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
425 00:44:43.328299 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
426 00:44:43.328809
427 00:44:43.329135
428 00:44:43.329448 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
429 00:44:43.329762 ARM64: Exception handlers installed.
430 00:44:43.330074 ARM64: Testing exception
431 00:44:43.330450 ARM64: Done test exception
432 00:44:43.330793 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
433 00:44:43.331107 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
434 00:44:43.331417 Probing TPM: . done!
435 00:44:43.331727 TPM ready after 0 ms
436 00:44:43.332034 Connected to device vid:did:rid of 1ae0:0028:00
437 00:44:43.332352 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
438 00:44:43.332658 Initialized TPM device CR50 revision 0
439 00:44:43.332942 tlcl_send_startup: Startup return code is 0
440 00:44:43.333224 TPM: setup succeeded
441 00:44:43.333518 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
442 00:44:43.333725 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
443 00:44:43.333925 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
444 00:44:43.334128 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 00:44:43.334329 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
446 00:44:43.334530 in-header: 03 07 00 00 08 00 00 00
447 00:44:43.334727 in-data: aa e4 47 04 13 02 00 00
448 00:44:43.334926 Chrome EC: UHEPI supported
449 00:44:43.335123 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
450 00:44:43.335324 in-header: 03 a9 00 00 08 00 00 00
451 00:44:43.335524 in-data: 84 60 60 08 00 00 00 00
452 00:44:43.335720 Phase 1
453 00:44:43.335922 FMAP: area GBB found @ 3f5000 (12032 bytes)
454 00:44:43.336124 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
455 00:44:43.336326 VB2:vb2_check_recovery() Recovery was requested manually
456 00:44:43.336526 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x7
457 00:44:43.336794 Recovery requested (1009000e)
458 00:44:43.337012 TPM: Extending digest for VBOOT: boot mode into PCR 0
459 00:44:43.337214 tlcl_extend: response is 0
460 00:44:43.337414 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
461 00:44:43.337615 tlcl_extend: response is 0
462 00:44:43.337813 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
463 00:44:43.338014 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
464 00:44:43.338215 BS: bootblock times (exec / console): total (unknown) / 148 ms
465 00:44:43.338389
466 00:44:43.338540
467 00:44:43.338689 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
468 00:44:43.338842 ARM64: Exception handlers installed.
469 00:44:43.338991 ARM64: Testing exception
470 00:44:43.339140 ARM64: Done test exception
471 00:44:43.339288 pmic_efuse_setting: Set efuses in 11 msecs
472 00:44:43.339437 pmwrap_interface_init: Select PMIF_VLD_RDY
473 00:44:43.339587 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
474 00:44:43.339738 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
475 00:44:43.340146 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
476 00:44:43.340322 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
477 00:44:43.340477 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
478 00:44:43.340657 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
479 00:44:43.340809 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
480 00:44:43.340959 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
481 00:44:43.341111 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
482 00:44:43.341262 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
483 00:44:43.341413 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
484 00:44:43.341565 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
485 00:44:43.341717 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
486 00:44:43.341866 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
487 00:44:43.342016 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
488 00:44:43.342163 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
489 00:44:43.342311 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
490 00:44:43.342461 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
491 00:44:43.342611 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
492 00:44:43.342761 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
493 00:44:43.342910 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
494 00:44:43.343059 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
495 00:44:43.343210 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
496 00:44:43.343346 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
497 00:44:43.343509 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
498 00:44:43.343632 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
499 00:44:43.343754 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
500 00:44:43.343876 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
501 00:44:43.343996 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
502 00:44:43.344117 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
503 00:44:43.344239 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
504 00:44:43.344360 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
505 00:44:43.344481 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
506 00:44:43.344624 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
507 00:44:43.344748 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
508 00:44:43.344871 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
509 00:44:43.344992 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
510 00:44:43.345114 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
511 00:44:43.345236 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
512 00:44:43.345357 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
513 00:44:43.345478 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
514 00:44:43.345599 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
515 00:44:43.345720 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
516 00:44:43.345840 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
517 00:44:43.345961 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
518 00:44:43.346080 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
519 00:44:43.346200 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
520 00:44:43.346319 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
521 00:44:43.346440 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
522 00:44:43.346560 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
523 00:44:43.346679 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
524 00:44:43.346799 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x6b6d 0x5bf0 0x8100 0x4c 0xf0f 0x9248
525 00:44:43.347005 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
526 00:44:43.347136 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
527 00:44:43.347259 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
528 00:44:43.347382 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
529 00:44:43.347504 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
530 00:44:43.347625 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
531 00:44:43.347746 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 00:44:43.347867 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x2
533 00:44:43.347989 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
534 00:44:43.348111 [RTC]rtc_osc_init,62: osc32con val = 0xde70
535 00:44:43.348232 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
536 00:44:43.348352 [RTC]rtc_get_frequency_meter,154: input=15, output=773
537 00:44:43.348453 [RTC]rtc_get_frequency_meter,154: input=23, output=959
538 00:44:43.348560 [RTC]rtc_get_frequency_meter,154: input=19, output=865
539 00:44:43.348661 [RTC]rtc_get_frequency_meter,154: input=17, output=817
540 00:44:43.348762 [RTC]rtc_get_frequency_meter,154: input=16, output=797
541 00:44:43.348863 [RTC]rtc_get_frequency_meter,154: input=15, output=773
542 00:44:43.348964 [RTC]rtc_get_frequency_meter,154: input=16, output=796
543 00:44:43.349083 [RTC]rtc_eosc_cali,47: left: 15, middle: 15, right: 16
544 00:44:43.349187 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
545 00:44:43.349504 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
546 00:44:43.349618 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
547 00:44:43.349721 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
548 00:44:43.349822 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
549 00:44:43.349923 ADC[4]: Raw value=902507 ID=7
550 00:44:43.350024 ADC[3]: Raw value=213179 ID=1
551 00:44:43.350139 RAM Code: 0x71
552 00:44:43.350257 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
553 00:44:43.350360 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
554 00:44:43.350462 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
555 00:44:43.350564 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
556 00:44:43.350665 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
557 00:44:43.350767 in-header: 03 07 00 00 08 00 00 00
558 00:44:43.350868 in-data: aa e4 47 04 13 02 00 00
559 00:44:43.350969 Chrome EC: UHEPI supported
560 00:44:43.351070 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
561 00:44:43.351172 in-header: 03 a9 00 00 08 00 00 00
562 00:44:43.351272 in-data: 84 60 60 08 00 00 00 00
563 00:44:43.351372 MRC: failed to locate region type 0.
564 00:44:43.351473 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
565 00:44:43.351575 DRAM-K: Running full calibration
566 00:44:43.351675 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
567 00:44:43.351777 header.status = 0x0
568 00:44:43.351878 header.version = 0x6 (expected: 0x6)
569 00:44:43.351978 header.size = 0xd00 (expected: 0xd00)
570 00:44:43.352078 header.flags = 0x0
571 00:44:43.352179 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
572 00:44:43.352280 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
573 00:44:43.352381 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
574 00:44:43.352482 dram_init: ddr_geometry: 2
575 00:44:43.352597 [EMI] MDL number = 2
576 00:44:43.352700 [EMI] Get MDL freq = 0
577 00:44:43.352799 dram_init: ddr_type: 0
578 00:44:43.352898 is_discrete_lpddr4: 1
579 00:44:43.352998 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
580 00:44:43.353099
581 00:44:43.353198
582 00:44:43.353306 [Bian_co] ETT version 0.0.0.1
583 00:44:43.353392 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
584 00:44:43.353479
585 00:44:43.353592 dramc_set_vcore_voltage set vcore to 650000
586 00:44:43.353684 Read voltage for 800, 4
587 00:44:43.353771 Vio18 = 0
588 00:44:43.353858 Vcore = 650000
589 00:44:43.353943 Vdram = 0
590 00:44:43.354029 Vddq = 0
591 00:44:43.354115 Vmddr = 0
592 00:44:43.354201 dram_init: config_dvfs: 1
593 00:44:43.354287 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
594 00:44:43.354375 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
595 00:44:43.354462 [SwImpedanceCal] DRVP=10, DRVN=17, ODTN=9
596 00:44:43.354547 freq_region=0, Reg: DRVP=10, DRVN=17, ODTN=9
597 00:44:43.354637 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
598 00:44:43.354724 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
599 00:44:43.354811 MEM_TYPE=3, freq_sel=18
600 00:44:43.354897 sv_algorithm_assistance_LP4_1600
601 00:44:43.354983 ============ PULL DRAM RESETB DOWN ============
602 00:44:43.355073 ========== PULL DRAM RESETB DOWN end =========
603 00:44:43.355160 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
604 00:44:43.355246 ===================================
605 00:44:43.355333 LPDDR4 DRAM CONFIGURATION
606 00:44:43.355419 ===================================
607 00:44:43.355506 EX_ROW_EN[0] = 0x0
608 00:44:43.355591 EX_ROW_EN[1] = 0x0
609 00:44:43.355677 LP4Y_EN = 0x0
610 00:44:43.355762 WORK_FSP = 0x0
611 00:44:43.355848 WL = 0x2
612 00:44:43.355933 RL = 0x2
613 00:44:43.356018 BL = 0x2
614 00:44:43.356104 RPST = 0x0
615 00:44:43.356190 RD_PRE = 0x0
616 00:44:43.356275 WR_PRE = 0x1
617 00:44:43.356366 WR_PST = 0x0
618 00:44:43.356452 DBI_WR = 0x0
619 00:44:43.356537 DBI_RD = 0x0
620 00:44:43.356638 OTF = 0x1
621 00:44:43.356725 ===================================
622 00:44:43.356813 ===================================
623 00:44:43.356930 ANA top config
624 00:44:43.357019 ===================================
625 00:44:43.357107 DLL_ASYNC_EN = 0
626 00:44:43.357193 ALL_SLAVE_EN = 1
627 00:44:43.357279 NEW_RANK_MODE = 1
628 00:44:43.357370 DLL_IDLE_MODE = 1
629 00:44:43.357456 LP45_APHY_COMB_EN = 1
630 00:44:43.357543 TX_ODT_DIS = 1
631 00:44:43.357631 NEW_8X_MODE = 1
632 00:44:43.357719 ===================================
633 00:44:43.357805 ===================================
634 00:44:43.357892 data_rate = 1600
635 00:44:43.357979 CKR = 1
636 00:44:43.358065 DQ_P2S_RATIO = 8
637 00:44:43.358152 ===================================
638 00:44:43.358239 CA_P2S_RATIO = 8
639 00:44:43.358330 DQ_CA_OPEN = 0
640 00:44:43.358405 DQ_SEMI_OPEN = 0
641 00:44:43.358482 CA_SEMI_OPEN = 0
642 00:44:43.358557 CA_FULL_RATE = 0
643 00:44:43.358632 DQ_CKDIV4_EN = 1
644 00:44:43.358707 CA_CKDIV4_EN = 1
645 00:44:43.358783 CA_PREDIV_EN = 0
646 00:44:43.358863 PH8_DLY = 0
647 00:44:43.358939 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
648 00:44:43.359014 DQ_AAMCK_DIV = 4
649 00:44:43.359089 CA_AAMCK_DIV = 4
650 00:44:43.359164 CA_ADMCK_DIV = 4
651 00:44:43.359240 DQ_TRACK_CA_EN = 0
652 00:44:43.359315 CA_PICK = 800
653 00:44:43.359390 CA_MCKIO = 800
654 00:44:43.359465 MCKIO_SEMI = 0
655 00:44:43.359541 PLL_FREQ = 3068
656 00:44:43.359617 DQ_UI_PI_RATIO = 32
657 00:44:43.359693 CA_UI_PI_RATIO = 0
658 00:44:43.359768 ===================================
659 00:44:43.359844 ===================================
660 00:44:43.359920 memory_type:LPDDR4
661 00:44:43.359996 GP_NUM : 10
662 00:44:43.360099 SRAM_EN : 1
663 00:44:43.360177 MD32_EN : 0
664 00:44:43.360484 ===================================
665 00:44:43.360583 [ANA_INIT] >>>>>>>>>>>>>>
666 00:44:43.360664 <<<<<< [CONFIGURE PHASE]: ANA_TX
667 00:44:43.360745 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
668 00:44:43.360822 ===================================
669 00:44:43.360900 data_rate = 1600,PCW = 0X7600
670 00:44:43.360976 ===================================
671 00:44:43.361053 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
672 00:44:43.361129 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
673 00:44:43.361206 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 00:44:43.361283 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
675 00:44:43.361359 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
676 00:44:43.361435 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
677 00:44:43.361511 [ANA_INIT] flow start
678 00:44:43.361587 [ANA_INIT] PLL >>>>>>>>
679 00:44:43.361662 [ANA_INIT] PLL <<<<<<<<
680 00:44:43.361737 [ANA_INIT] MIDPI >>>>>>>>
681 00:44:43.361811 [ANA_INIT] MIDPI <<<<<<<<
682 00:44:43.361887 [ANA_INIT] DLL >>>>>>>>
683 00:44:43.361961 [ANA_INIT] flow end
684 00:44:43.362036 ============ LP4 DIFF to SE enter ============
685 00:44:43.362113 ============ LP4 DIFF to SE exit ============
686 00:44:43.362189 [ANA_INIT] <<<<<<<<<<<<<
687 00:44:43.362264 [Flow] Enable top DCM control >>>>>
688 00:44:43.362340 [Flow] Enable top DCM control <<<<<
689 00:44:43.362415 Enable DLL master slave shuffle
690 00:44:43.362490 ==============================================================
691 00:44:43.362566 Gating Mode config
692 00:44:43.362642 ==============================================================
693 00:44:43.362718 Config description:
694 00:44:43.362792 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
695 00:44:43.362870 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
696 00:44:43.362946 SELPH_MODE 0: By rank 1: By Phase
697 00:44:43.363023 ==============================================================
698 00:44:43.363099 GAT_TRACK_EN = 1
699 00:44:43.363175 RX_GATING_MODE = 2
700 00:44:43.363250 RX_GATING_TRACK_MODE = 2
701 00:44:43.363333 SELPH_MODE = 1
702 00:44:43.363400 PICG_EARLY_EN = 1
703 00:44:43.363467 VALID_LAT_VALUE = 1
704 00:44:43.363545 ==============================================================
705 00:44:43.363623 Enter into Gating configuration >>>>
706 00:44:43.363697 Exit from Gating configuration <<<<
707 00:44:43.363766 Enter into DVFS_PRE_config >>>>>
708 00:44:43.363834 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
709 00:44:43.363907 Exit from DVFS_PRE_config <<<<<
710 00:44:43.363975 Enter into PICG configuration >>>>
711 00:44:43.364043 Exit from PICG configuration <<<<
712 00:44:43.364111 [RX_INPUT] configuration >>>>>
713 00:44:43.364177 [RX_INPUT] configuration <<<<<
714 00:44:43.364245 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
715 00:44:43.364312 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
716 00:44:43.364379 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
717 00:44:43.364447 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
718 00:44:43.364515 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
719 00:44:43.364607 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
720 00:44:43.364677 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
721 00:44:43.364746 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
722 00:44:43.364814 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
723 00:44:43.364882 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
724 00:44:43.364950 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
725 00:44:43.365017 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
726 00:44:43.365085 ===================================
727 00:44:43.365152 LPDDR4 DRAM CONFIGURATION
728 00:44:43.365220 ===================================
729 00:44:43.365287 EX_ROW_EN[0] = 0x0
730 00:44:43.365355 EX_ROW_EN[1] = 0x0
731 00:44:43.365422 LP4Y_EN = 0x0
732 00:44:43.365489 WORK_FSP = 0x0
733 00:44:43.365556 WL = 0x2
734 00:44:43.365623 RL = 0x2
735 00:44:43.365689 BL = 0x2
736 00:44:43.365756 RPST = 0x0
737 00:44:43.365823 RD_PRE = 0x0
738 00:44:43.365890 WR_PRE = 0x1
739 00:44:43.365956 WR_PST = 0x0
740 00:44:43.366023 DBI_WR = 0x0
741 00:44:43.366090 DBI_RD = 0x0
742 00:44:43.366157 OTF = 0x1
743 00:44:43.366224 ===================================
744 00:44:43.366292 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
745 00:44:43.366359 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
746 00:44:43.366443 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
747 00:44:43.366516 ===================================
748 00:44:43.366584 LPDDR4 DRAM CONFIGURATION
749 00:44:43.366651 ===================================
750 00:44:43.366718 EX_ROW_EN[0] = 0x10
751 00:44:43.366786 EX_ROW_EN[1] = 0x0
752 00:44:43.366854 LP4Y_EN = 0x0
753 00:44:43.366921 WORK_FSP = 0x0
754 00:44:43.366987 WL = 0x2
755 00:44:43.367054 RL = 0x2
756 00:44:43.367121 BL = 0x2
757 00:44:43.367188 RPST = 0x0
758 00:44:43.367254 RD_PRE = 0x0
759 00:44:43.367321 WR_PRE = 0x1
760 00:44:43.367388 WR_PST = 0x0
761 00:44:43.367454 DBI_WR = 0x0
762 00:44:43.367520 DBI_RD = 0x0
763 00:44:43.367586 OTF = 0x1
764 00:44:43.367654 ===================================
765 00:44:43.367722 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
766 00:44:43.367789 nWR fixed to 40
767 00:44:43.367857 [ModeRegInit_LP4] CH0 RK0
768 00:44:43.367924 [ModeRegInit_LP4] CH0 RK1
769 00:44:43.367991 [ModeRegInit_LP4] CH1 RK0
770 00:44:43.368058 [ModeRegInit_LP4] CH1 RK1
771 00:44:43.368125 match AC timing 13
772 00:44:43.368191 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
773 00:44:43.368469 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
774 00:44:43.368540 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
775 00:44:43.368613 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
776 00:44:43.368675 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
777 00:44:43.368737 [EMI DOE] emi_dcm 0
778 00:44:43.368798 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
779 00:44:43.368859 ==
780 00:44:43.368920 Dram Type= 6, Freq= 0, CH_0, rank 0
781 00:44:43.368981 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 00:44:43.369042 ==
783 00:44:43.369104 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
784 00:44:43.369165 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
785 00:44:43.369226 [CA 0] Center 38 (7~69) winsize 63
786 00:44:43.369287 [CA 1] Center 38 (7~69) winsize 63
787 00:44:43.369347 [CA 2] Center 35 (5~66) winsize 62
788 00:44:43.369407 [CA 3] Center 35 (5~66) winsize 62
789 00:44:43.369468 [CA 4] Center 35 (4~66) winsize 63
790 00:44:43.369528 [CA 5] Center 33 (3~64) winsize 62
791 00:44:43.369588
792 00:44:43.369649 [CmdBusTrainingLP45] Vref(ca) range 1: 32
793 00:44:43.369709
794 00:44:43.369769 [CATrainingPosCal] consider 1 rank data
795 00:44:43.369858 u2DelayCellTimex100 = 270/100 ps
796 00:44:43.369955 CA0 delay=38 (7~69),Diff = 5 PI (36 cell)
797 00:44:43.370051 CA1 delay=38 (7~69),Diff = 5 PI (36 cell)
798 00:44:43.370147 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
799 00:44:43.370217 CA3 delay=35 (5~66),Diff = 2 PI (14 cell)
800 00:44:43.370279 CA4 delay=35 (4~66),Diff = 2 PI (14 cell)
801 00:44:43.370340 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
802 00:44:43.370402
803 00:44:43.370463 CA PerBit enable=1, Macro0, CA PI delay=33
804 00:44:43.370525
805 00:44:43.370587 [CBTSetCACLKResult] CA Dly = 33
806 00:44:43.370648 CS Dly: 6 (0~37)
807 00:44:43.370707 ==
808 00:44:43.370769 Dram Type= 6, Freq= 0, CH_0, rank 1
809 00:44:43.370830 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
810 00:44:43.370892 ==
811 00:44:43.370953 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
812 00:44:43.371015 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
813 00:44:43.371076 [CA 0] Center 38 (7~69) winsize 63
814 00:44:43.371136 [CA 1] Center 38 (7~69) winsize 63
815 00:44:43.371197 [CA 2] Center 36 (6~67) winsize 62
816 00:44:43.371257 [CA 3] Center 35 (5~66) winsize 62
817 00:44:43.371318 [CA 4] Center 35 (4~66) winsize 63
818 00:44:43.371378 [CA 5] Center 34 (4~65) winsize 62
819 00:44:43.371438
820 00:44:43.371499 [CmdBusTrainingLP45] Vref(ca) range 1: 34
821 00:44:43.371565
822 00:44:43.371626 [CATrainingPosCal] consider 2 rank data
823 00:44:43.371687 u2DelayCellTimex100 = 270/100 ps
824 00:44:43.371747 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
825 00:44:43.371808 CA1 delay=38 (7~69),Diff = 4 PI (28 cell)
826 00:44:43.371868 CA2 delay=36 (6~66),Diff = 2 PI (14 cell)
827 00:44:43.371929 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
828 00:44:43.371989 CA4 delay=35 (4~66),Diff = 1 PI (7 cell)
829 00:44:43.372049 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
830 00:44:43.372110
831 00:44:43.372171 CA PerBit enable=1, Macro0, CA PI delay=34
832 00:44:43.372231
833 00:44:43.372291 [CBTSetCACLKResult] CA Dly = 34
834 00:44:43.372352 CS Dly: 6 (0~38)
835 00:44:43.372412
836 00:44:43.372473 ----->DramcWriteLeveling(PI) begin...
837 00:44:43.372535 ==
838 00:44:43.372607 Dram Type= 6, Freq= 0, CH_0, rank 0
839 00:44:43.372669 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
840 00:44:43.372731 ==
841 00:44:43.372792 Write leveling (Byte 0): 31 => 31
842 00:44:43.372854 Write leveling (Byte 1): 30 => 30
843 00:44:43.372914 DramcWriteLeveling(PI) end<-----
844 00:44:43.372975
845 00:44:43.373035 ==
846 00:44:43.373096 Dram Type= 6, Freq= 0, CH_0, rank 0
847 00:44:43.373157 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
848 00:44:43.373218 ==
849 00:44:43.373287 [Gating] SW mode calibration
850 00:44:43.373365 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
851 00:44:43.373423 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
852 00:44:43.373479 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
853 00:44:43.373535 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
854 00:44:43.373591 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
855 00:44:43.373648 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 00:44:43.373704 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 00:44:43.373759 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 00:44:43.373815 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 00:44:43.373871 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 00:44:43.373926 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 00:44:43.373982 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 00:44:43.374037 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 00:44:43.374093 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 00:44:43.374148 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 00:44:43.374204 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 00:44:43.374259 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 00:44:43.374314 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 00:44:43.374370 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
869 00:44:43.374425 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
870 00:44:43.374480 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
871 00:44:43.374535 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
872 00:44:43.374590 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 00:44:43.374645 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 00:44:43.374700 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 00:44:43.374755 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 00:44:43.374810 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 00:44:43.374866 0 9 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
878 00:44:43.374921 0 9 8 | B1->B0 | 2323 3434 | 1 1 | (1 1) (1 1)
879 00:44:43.374976 0 9 12 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
880 00:44:43.375031 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
881 00:44:43.375280 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 00:44:43.375342 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
883 00:44:43.375399 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
884 00:44:43.375455 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
885 00:44:43.375511 0 10 4 | B1->B0 | 3434 2f2f | 1 1 | (1 0) (1 0)
886 00:44:43.375567 0 10 8 | B1->B0 | 3131 2323 | 1 0 | (0 0) (0 0)
887 00:44:43.375623 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
888 00:44:43.375678 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
889 00:44:43.375734 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 00:44:43.375790 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 00:44:43.375846 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
892 00:44:43.375901 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
893 00:44:43.375956 0 11 4 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
894 00:44:43.376012 0 11 8 | B1->B0 | 2c2c 4646 | 0 0 | (0 0) (0 0)
895 00:44:43.376067 0 11 12 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
896 00:44:43.376122 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
897 00:44:43.376178 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 00:44:43.376233 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 00:44:43.376289 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
900 00:44:43.376345 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
901 00:44:43.376400 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
902 00:44:43.376456 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
903 00:44:43.376511 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
904 00:44:43.376574 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 00:44:43.376653 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 00:44:43.376711 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 00:44:43.376768 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 00:44:43.376824 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 00:44:43.376879 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 00:44:43.376935 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 00:44:43.376991 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 00:44:43.377051 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 00:44:43.377107 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 00:44:43.377162 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 00:44:43.377217 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
916 00:44:43.377273 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
917 00:44:43.377328 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
918 00:44:43.377384 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
919 00:44:43.377439 Total UI for P1: 0, mck2ui 16
920 00:44:43.377495 best dqsien dly found for B0: ( 0, 14, 4)
921 00:44:43.377550 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
922 00:44:43.377606 Total UI for P1: 0, mck2ui 16
923 00:44:43.377661 best dqsien dly found for B1: ( 0, 14, 6)
924 00:44:43.377717 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
925 00:44:43.377773 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
926 00:44:43.377827
927 00:44:43.377883 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
928 00:44:43.377939 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
929 00:44:43.377994 [Gating] SW calibration Done
930 00:44:43.378049 ==
931 00:44:43.378105 Dram Type= 6, Freq= 0, CH_0, rank 0
932 00:44:43.378161 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
933 00:44:43.378216 ==
934 00:44:43.378284 RX Vref Scan: 0
935 00:44:43.378337
936 00:44:43.378391 RX Vref 0 -> 0, step: 1
937 00:44:43.378445
938 00:44:43.378498 RX Delay -130 -> 252, step: 16
939 00:44:43.378552 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
940 00:44:43.378606 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
941 00:44:43.378661 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
942 00:44:43.378715 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
943 00:44:43.378769 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
944 00:44:43.378823 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
945 00:44:43.378877 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
946 00:44:43.378931 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
947 00:44:43.378984 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
948 00:44:43.379038 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
949 00:44:43.379092 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
950 00:44:43.379146 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
951 00:44:43.379200 iDelay=222, Bit 12, Center 85 (-18 ~ 189) 208
952 00:44:43.379254 iDelay=222, Bit 13, Center 85 (-18 ~ 189) 208
953 00:44:43.379307 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
954 00:44:43.379361 iDelay=222, Bit 15, Center 85 (-18 ~ 189) 208
955 00:44:43.379416 ==
956 00:44:43.379469 Dram Type= 6, Freq= 0, CH_0, rank 0
957 00:44:43.379524 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
958 00:44:43.379578 ==
959 00:44:43.379633 DQS Delay:
960 00:44:43.379686 DQS0 = 0, DQS1 = 0
961 00:44:43.379740 DQM Delay:
962 00:44:43.379794 DQM0 = 91, DQM1 = 80
963 00:44:43.379848 DQ Delay:
964 00:44:43.379902 DQ0 =93, DQ1 =93, DQ2 =85, DQ3 =85
965 00:44:43.379960 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =101
966 00:44:43.380028 DQ8 =77, DQ9 =61, DQ10 =77, DQ11 =77
967 00:44:43.380083 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =85
968 00:44:43.380138
969 00:44:43.380191
970 00:44:43.380245 ==
971 00:44:43.380300 Dram Type= 6, Freq= 0, CH_0, rank 0
972 00:44:43.380354 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
973 00:44:43.380409 ==
974 00:44:43.380463
975 00:44:43.380517
976 00:44:43.380574 TX Vref Scan disable
977 00:44:43.380628 == TX Byte 0 ==
978 00:44:43.380683 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
979 00:44:43.380738 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
980 00:44:43.380794 == TX Byte 1 ==
981 00:44:43.380847 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
982 00:44:43.380902 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
983 00:44:43.380956 ==
984 00:44:43.381010 Dram Type= 6, Freq= 0, CH_0, rank 0
985 00:44:43.381065 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
986 00:44:43.381119 ==
987 00:44:43.381174 TX Vref=22, minBit 11, minWin=26, winSum=442
988 00:44:43.381230 TX Vref=24, minBit 6, minWin=27, winSum=445
989 00:44:43.381475 TX Vref=26, minBit 9, minWin=27, winSum=448
990 00:44:43.381537 TX Vref=28, minBit 8, minWin=27, winSum=455
991 00:44:43.381594 TX Vref=30, minBit 5, minWin=28, winSum=460
992 00:44:43.381649 TX Vref=32, minBit 4, minWin=28, winSum=456
993 00:44:43.381705 [TxChooseVref] Worse bit 5, Min win 28, Win sum 460, Final Vref 30
994 00:44:43.381761
995 00:44:43.381816 Final TX Range 1 Vref 30
996 00:44:43.381870
997 00:44:43.381925 ==
998 00:44:43.381979 Dram Type= 6, Freq= 0, CH_0, rank 0
999 00:44:43.382034 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1000 00:44:43.382088 ==
1001 00:44:43.382142
1002 00:44:43.382194
1003 00:44:43.382248 TX Vref Scan disable
1004 00:44:43.382302 == TX Byte 0 ==
1005 00:44:43.382357 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1006 00:44:43.382412 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1007 00:44:43.382466 == TX Byte 1 ==
1008 00:44:43.382520 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1009 00:44:43.382575 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1010 00:44:43.382629
1011 00:44:43.382684 [DATLAT]
1012 00:44:43.382740 Freq=800, CH0 RK0
1013 00:44:43.382794
1014 00:44:43.382848 DATLAT Default: 0xa
1015 00:44:43.382902 0, 0xFFFF, sum = 0
1016 00:44:43.382957 1, 0xFFFF, sum = 0
1017 00:44:43.383013 2, 0xFFFF, sum = 0
1018 00:44:43.383068 3, 0xFFFF, sum = 0
1019 00:44:43.383123 4, 0xFFFF, sum = 0
1020 00:44:43.383178 5, 0xFFFF, sum = 0
1021 00:44:43.383233 6, 0xFFFF, sum = 0
1022 00:44:43.383308 7, 0xFFFF, sum = 0
1023 00:44:43.383366 8, 0xFFFF, sum = 0
1024 00:44:43.383422 9, 0x0, sum = 1
1025 00:44:43.383484 10, 0x0, sum = 2
1026 00:44:43.383542 11, 0x0, sum = 3
1027 00:44:43.383598 12, 0x0, sum = 4
1028 00:44:43.383653 best_step = 10
1029 00:44:43.383707
1030 00:44:43.383760 ==
1031 00:44:43.383813 Dram Type= 6, Freq= 0, CH_0, rank 0
1032 00:44:43.383867 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1033 00:44:43.383920 ==
1034 00:44:43.383973 RX Vref Scan: 1
1035 00:44:43.384027
1036 00:44:43.384080 Set Vref Range= 32 -> 127
1037 00:44:43.384134
1038 00:44:43.384187 RX Vref 32 -> 127, step: 1
1039 00:44:43.384240
1040 00:44:43.384293 RX Delay -95 -> 252, step: 8
1041 00:44:43.384347
1042 00:44:43.384400 Set Vref, RX VrefLevel [Byte0]: 32
1043 00:44:43.384452 [Byte1]: 32
1044 00:44:43.384506
1045 00:44:43.384564 Set Vref, RX VrefLevel [Byte0]: 33
1046 00:44:43.384618 [Byte1]: 33
1047 00:44:43.384671
1048 00:44:43.384724 Set Vref, RX VrefLevel [Byte0]: 34
1049 00:44:43.384777 [Byte1]: 34
1050 00:44:43.384831
1051 00:44:43.384883 Set Vref, RX VrefLevel [Byte0]: 35
1052 00:44:43.384936 [Byte1]: 35
1053 00:44:43.384989
1054 00:44:43.385042 Set Vref, RX VrefLevel [Byte0]: 36
1055 00:44:43.385096 [Byte1]: 36
1056 00:44:43.385148
1057 00:44:43.385201 Set Vref, RX VrefLevel [Byte0]: 37
1058 00:44:43.385255 [Byte1]: 37
1059 00:44:43.385308
1060 00:44:43.385360 Set Vref, RX VrefLevel [Byte0]: 38
1061 00:44:43.385413 [Byte1]: 38
1062 00:44:43.385466
1063 00:44:43.385519 Set Vref, RX VrefLevel [Byte0]: 39
1064 00:44:43.385572 [Byte1]: 39
1065 00:44:43.385625
1066 00:44:43.385678 Set Vref, RX VrefLevel [Byte0]: 40
1067 00:44:43.385731 [Byte1]: 40
1068 00:44:43.385784
1069 00:44:43.385836 Set Vref, RX VrefLevel [Byte0]: 41
1070 00:44:43.385890 [Byte1]: 41
1071 00:44:43.385943
1072 00:44:43.385996 Set Vref, RX VrefLevel [Byte0]: 42
1073 00:44:43.386049 [Byte1]: 42
1074 00:44:43.386102
1075 00:44:43.386155 Set Vref, RX VrefLevel [Byte0]: 43
1076 00:44:43.386208 [Byte1]: 43
1077 00:44:43.386264
1078 00:44:43.386317 Set Vref, RX VrefLevel [Byte0]: 44
1079 00:44:43.386370 [Byte1]: 44
1080 00:44:43.386424
1081 00:44:43.386477 Set Vref, RX VrefLevel [Byte0]: 45
1082 00:44:43.386553 [Byte1]: 45
1083 00:44:43.386608
1084 00:44:43.386662 Set Vref, RX VrefLevel [Byte0]: 46
1085 00:44:43.386715 [Byte1]: 46
1086 00:44:43.386768
1087 00:44:43.386821 Set Vref, RX VrefLevel [Byte0]: 47
1088 00:44:43.386874 [Byte1]: 47
1089 00:44:43.386927
1090 00:44:43.386980 Set Vref, RX VrefLevel [Byte0]: 48
1091 00:44:43.387033 [Byte1]: 48
1092 00:44:43.387086
1093 00:44:43.387138 Set Vref, RX VrefLevel [Byte0]: 49
1094 00:44:43.387192 [Byte1]: 49
1095 00:44:43.387246
1096 00:44:43.387298 Set Vref, RX VrefLevel [Byte0]: 50
1097 00:44:43.387351 [Byte1]: 50
1098 00:44:43.387404
1099 00:44:43.387456 Set Vref, RX VrefLevel [Byte0]: 51
1100 00:44:43.387509 [Byte1]: 51
1101 00:44:43.387561
1102 00:44:43.387614 Set Vref, RX VrefLevel [Byte0]: 52
1103 00:44:43.387666 [Byte1]: 52
1104 00:44:43.387719
1105 00:44:43.387772 Set Vref, RX VrefLevel [Byte0]: 53
1106 00:44:43.387825 [Byte1]: 53
1107 00:44:43.387878
1108 00:44:43.387931 Set Vref, RX VrefLevel [Byte0]: 54
1109 00:44:43.387984 [Byte1]: 54
1110 00:44:43.388037
1111 00:44:43.388089 Set Vref, RX VrefLevel [Byte0]: 55
1112 00:44:43.388143 [Byte1]: 55
1113 00:44:43.388196
1114 00:44:43.388249 Set Vref, RX VrefLevel [Byte0]: 56
1115 00:44:43.388302 [Byte1]: 56
1116 00:44:43.388354
1117 00:44:43.388407 Set Vref, RX VrefLevel [Byte0]: 57
1118 00:44:43.388460 [Byte1]: 57
1119 00:44:43.388512
1120 00:44:43.388592 Set Vref, RX VrefLevel [Byte0]: 58
1121 00:44:43.388660 [Byte1]: 58
1122 00:44:43.388713
1123 00:44:43.388766 Set Vref, RX VrefLevel [Byte0]: 59
1124 00:44:43.388818 [Byte1]: 59
1125 00:44:43.388872
1126 00:44:43.388924 Set Vref, RX VrefLevel [Byte0]: 60
1127 00:44:43.388977 [Byte1]: 60
1128 00:44:43.389030
1129 00:44:43.389083 Set Vref, RX VrefLevel [Byte0]: 61
1130 00:44:43.389136 [Byte1]: 61
1131 00:44:43.389189
1132 00:44:43.389241 Set Vref, RX VrefLevel [Byte0]: 62
1133 00:44:43.389294 [Byte1]: 62
1134 00:44:43.389347
1135 00:44:43.389400 Set Vref, RX VrefLevel [Byte0]: 63
1136 00:44:43.389453 [Byte1]: 63
1137 00:44:43.389506
1138 00:44:43.389559 Set Vref, RX VrefLevel [Byte0]: 64
1139 00:44:43.389612 [Byte1]: 64
1140 00:44:43.389665
1141 00:44:43.389717 Set Vref, RX VrefLevel [Byte0]: 65
1142 00:44:43.389770 [Byte1]: 65
1143 00:44:43.389822
1144 00:44:43.389875 Set Vref, RX VrefLevel [Byte0]: 66
1145 00:44:43.389941 [Byte1]: 66
1146 00:44:43.389999
1147 00:44:43.390052 Set Vref, RX VrefLevel [Byte0]: 67
1148 00:44:43.390106 [Byte1]: 67
1149 00:44:43.390159
1150 00:44:43.390212 Set Vref, RX VrefLevel [Byte0]: 68
1151 00:44:43.390264 [Byte1]: 68
1152 00:44:43.390318
1153 00:44:43.390370 Set Vref, RX VrefLevel [Byte0]: 69
1154 00:44:43.390423 [Byte1]: 69
1155 00:44:43.390476
1156 00:44:43.390529 Set Vref, RX VrefLevel [Byte0]: 70
1157 00:44:43.390776 [Byte1]: 70
1158 00:44:43.390838
1159 00:44:43.390893 Set Vref, RX VrefLevel [Byte0]: 71
1160 00:44:43.390947 [Byte1]: 71
1161 00:44:43.391001
1162 00:44:43.391054 Set Vref, RX VrefLevel [Byte0]: 72
1163 00:44:43.391108 [Byte1]: 72
1164 00:44:43.391162
1165 00:44:43.391215 Set Vref, RX VrefLevel [Byte0]: 73
1166 00:44:43.391269 [Byte1]: 73
1167 00:44:43.391322
1168 00:44:43.391375 Set Vref, RX VrefLevel [Byte0]: 74
1169 00:44:43.391428 [Byte1]: 74
1170 00:44:43.391481
1171 00:44:43.391534 Set Vref, RX VrefLevel [Byte0]: 75
1172 00:44:43.391588 [Byte1]: 75
1173 00:44:43.391642
1174 00:44:43.391695 Set Vref, RX VrefLevel [Byte0]: 76
1175 00:44:43.391748 [Byte1]: 76
1176 00:44:43.391801
1177 00:44:43.391854 Set Vref, RX VrefLevel [Byte0]: 77
1178 00:44:43.391907 [Byte1]: 77
1179 00:44:43.391960
1180 00:44:43.392013 Set Vref, RX VrefLevel [Byte0]: 78
1181 00:44:43.392067 [Byte1]: 78
1182 00:44:43.392120
1183 00:44:43.392173 Set Vref, RX VrefLevel [Byte0]: 79
1184 00:44:43.392227 [Byte1]: 79
1185 00:44:43.392280
1186 00:44:43.392332 Final RX Vref Byte 0 = 62 to rank0
1187 00:44:43.392386 Final RX Vref Byte 1 = 61 to rank0
1188 00:44:43.392439 Final RX Vref Byte 0 = 62 to rank1
1189 00:44:43.392493 Final RX Vref Byte 1 = 61 to rank1==
1190 00:44:43.392553 Dram Type= 6, Freq= 0, CH_0, rank 0
1191 00:44:43.392644 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1192 00:44:43.392698 ==
1193 00:44:43.392752 DQS Delay:
1194 00:44:43.392805 DQS0 = 0, DQS1 = 0
1195 00:44:43.392859 DQM Delay:
1196 00:44:43.392912 DQM0 = 93, DQM1 = 82
1197 00:44:43.392972 DQ Delay:
1198 00:44:43.393035 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1199 00:44:43.393089 DQ4 =92, DQ5 =80, DQ6 =104, DQ7 =104
1200 00:44:43.393143 DQ8 =72, DQ9 =72, DQ10 =84, DQ11 =80
1201 00:44:43.393196 DQ12 =84, DQ13 =80, DQ14 =92, DQ15 =92
1202 00:44:43.393249
1203 00:44:43.393302
1204 00:44:43.393355 [DQSOSCAuto] RK0, (LSB)MR18= 0x3b36, (MSB)MR19= 0x606, tDQSOscB0 = 396 ps tDQSOscB1 = 394 ps
1205 00:44:43.393410 CH0 RK0: MR19=606, MR18=3B36
1206 00:44:43.393465 CH0_RK0: MR19=0x606, MR18=0x3B36, DQSOSC=394, MR23=63, INC=95, DEC=63
1207 00:44:43.393519
1208 00:44:43.393571 ----->DramcWriteLeveling(PI) begin...
1209 00:44:43.393625 ==
1210 00:44:43.393679 Dram Type= 6, Freq= 0, CH_0, rank 1
1211 00:44:43.393731 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1212 00:44:43.393785 ==
1213 00:44:43.393839 Write leveling (Byte 0): 33 => 33
1214 00:44:43.393893 Write leveling (Byte 1): 29 => 29
1215 00:44:43.393946 DramcWriteLeveling(PI) end<-----
1216 00:44:43.393999
1217 00:44:43.394051 ==
1218 00:44:43.394105 Dram Type= 6, Freq= 0, CH_0, rank 1
1219 00:44:43.394158 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1220 00:44:43.394212 ==
1221 00:44:43.394265 [Gating] SW mode calibration
1222 00:44:43.394319 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1223 00:44:43.394375 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1224 00:44:43.394430 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1225 00:44:43.394483 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1226 00:44:43.394537 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1227 00:44:43.394590 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 00:44:43.394644 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 00:44:43.394697 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 00:44:43.394751 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 00:44:43.394804 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 00:44:43.394857 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 00:44:43.394910 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 00:44:43.394964 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 00:44:43.395017 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 00:44:43.395070 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1237 00:44:43.395124 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1238 00:44:43.395177 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1239 00:44:43.395230 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1240 00:44:43.395283 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1241 00:44:43.395336 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1242 00:44:43.395389 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1243 00:44:43.395442 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1244 00:44:43.395496 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1245 00:44:43.395549 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1246 00:44:43.395602 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1247 00:44:43.395655 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1248 00:44:43.395708 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1249 00:44:43.395761 0 9 4 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
1250 00:44:43.395814 0 9 8 | B1->B0 | 2f2f 3333 | 1 1 | (0 0) (1 1)
1251 00:44:43.395867 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1252 00:44:43.395920 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1253 00:44:43.395973 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1254 00:44:43.396026 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1255 00:44:43.396080 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1256 00:44:43.396132 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1257 00:44:43.396185 0 10 4 | B1->B0 | 3131 2f2f | 1 1 | (1 0) (1 0)
1258 00:44:43.396239 0 10 8 | B1->B0 | 2b2b 2323 | 1 0 | (0 0) (0 0)
1259 00:44:43.396292 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1260 00:44:43.396364 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1261 00:44:43.396419 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1262 00:44:43.396473 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1263 00:44:43.396526 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1264 00:44:43.396610 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1265 00:44:43.396678 0 11 4 | B1->B0 | 2929 3535 | 0 1 | (0 0) (0 0)
1266 00:44:43.396731 0 11 8 | B1->B0 | 3d3d 4545 | 0 0 | (0 0) (0 0)
1267 00:44:43.396976 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1268 00:44:43.397035 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1269 00:44:43.397090 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1270 00:44:43.397144 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1271 00:44:43.397197 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1272 00:44:43.397250 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1273 00:44:43.397304 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1274 00:44:43.397358 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1275 00:44:43.397412 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1276 00:44:43.397465 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1277 00:44:43.397519 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1278 00:44:43.397572 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1279 00:44:43.397625 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1280 00:44:43.397678 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1281 00:44:43.397732 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1282 00:44:43.397785 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1283 00:44:43.397838 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1284 00:44:43.397892 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1285 00:44:43.397945 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1286 00:44:43.397999 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1287 00:44:43.398053 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1288 00:44:43.398106 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1289 00:44:43.398160 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1290 00:44:43.398213 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1291 00:44:43.398267 Total UI for P1: 0, mck2ui 16
1292 00:44:43.398320 best dqsien dly found for B0: ( 0, 14, 4)
1293 00:44:43.398374 Total UI for P1: 0, mck2ui 16
1294 00:44:43.398428 best dqsien dly found for B1: ( 0, 14, 4)
1295 00:44:43.398481 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1296 00:44:43.398534 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1297 00:44:43.398587
1298 00:44:43.398640 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1299 00:44:43.398693 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1300 00:44:43.398746 [Gating] SW calibration Done
1301 00:44:43.398799 ==
1302 00:44:43.398852 Dram Type= 6, Freq= 0, CH_0, rank 1
1303 00:44:43.398906 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1304 00:44:43.398959 ==
1305 00:44:43.399013 RX Vref Scan: 0
1306 00:44:43.399066
1307 00:44:43.399118 RX Vref 0 -> 0, step: 1
1308 00:44:43.399172
1309 00:44:43.399225 RX Delay -130 -> 252, step: 16
1310 00:44:43.399278 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1311 00:44:43.399332 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1312 00:44:43.399385 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
1313 00:44:43.399438 iDelay=222, Bit 3, Center 77 (-34 ~ 189) 224
1314 00:44:43.399492 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1315 00:44:43.399545 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
1316 00:44:43.399614 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1317 00:44:43.399671 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1318 00:44:43.399724 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1319 00:44:43.399777 iDelay=222, Bit 9, Center 69 (-34 ~ 173) 208
1320 00:44:43.399831 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1321 00:44:43.399884 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1322 00:44:43.399937 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
1323 00:44:43.399990 iDelay=222, Bit 13, Center 77 (-34 ~ 189) 224
1324 00:44:43.400043 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1325 00:44:43.400097 iDelay=222, Bit 15, Center 77 (-34 ~ 189) 224
1326 00:44:43.400150 ==
1327 00:44:43.400203 Dram Type= 6, Freq= 0, CH_0, rank 1
1328 00:44:43.400256 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1329 00:44:43.400310 ==
1330 00:44:43.400363 DQS Delay:
1331 00:44:43.400416 DQS0 = 0, DQS1 = 0
1332 00:44:43.400469 DQM Delay:
1333 00:44:43.400526 DQM0 = 90, DQM1 = 78
1334 00:44:43.400628 DQ Delay:
1335 00:44:43.400683 DQ0 =85, DQ1 =93, DQ2 =93, DQ3 =77
1336 00:44:43.400737 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =101
1337 00:44:43.400791 DQ8 =77, DQ9 =69, DQ10 =77, DQ11 =77
1338 00:44:43.400844 DQ12 =77, DQ13 =77, DQ14 =93, DQ15 =77
1339 00:44:43.400898
1340 00:44:43.400950
1341 00:44:43.401003 ==
1342 00:44:43.401056 Dram Type= 6, Freq= 0, CH_0, rank 1
1343 00:44:43.401109 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1344 00:44:43.401163 ==
1345 00:44:43.401216
1346 00:44:43.401268
1347 00:44:43.401321 TX Vref Scan disable
1348 00:44:43.401374 == TX Byte 0 ==
1349 00:44:43.401427 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1350 00:44:43.401481 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1351 00:44:43.401535 == TX Byte 1 ==
1352 00:44:43.401588 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1353 00:44:43.401642 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1354 00:44:43.401696 ==
1355 00:44:43.401749 Dram Type= 6, Freq= 0, CH_0, rank 1
1356 00:44:43.401802 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1357 00:44:43.401856 ==
1358 00:44:43.401909 TX Vref=22, minBit 3, minWin=27, winSum=443
1359 00:44:43.401963 TX Vref=24, minBit 8, minWin=27, winSum=449
1360 00:44:43.402017 TX Vref=26, minBit 8, minWin=27, winSum=453
1361 00:44:43.402069 TX Vref=28, minBit 8, minWin=27, winSum=455
1362 00:44:43.402121 TX Vref=30, minBit 10, minWin=27, winSum=457
1363 00:44:43.402173 TX Vref=32, minBit 8, minWin=28, winSum=458
1364 00:44:43.402225 [TxChooseVref] Worse bit 8, Min win 28, Win sum 458, Final Vref 32
1365 00:44:43.402278
1366 00:44:43.402330 Final TX Range 1 Vref 32
1367 00:44:43.402382
1368 00:44:43.402433 ==
1369 00:44:43.402484 Dram Type= 6, Freq= 0, CH_0, rank 1
1370 00:44:43.402535 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1371 00:44:43.402587 ==
1372 00:44:43.402638
1373 00:44:43.402713
1374 00:44:43.402778 TX Vref Scan disable
1375 00:44:43.402829 == TX Byte 0 ==
1376 00:44:43.402880 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1377 00:44:43.402932 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1378 00:44:43.402984 == TX Byte 1 ==
1379 00:44:43.403050 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1380 00:44:43.403105 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1381 00:44:43.403157
1382 00:44:43.403208 [DATLAT]
1383 00:44:43.403260 Freq=800, CH0 RK1
1384 00:44:43.403312
1385 00:44:43.403364 DATLAT Default: 0xa
1386 00:44:43.403416 0, 0xFFFF, sum = 0
1387 00:44:43.403469 1, 0xFFFF, sum = 0
1388 00:44:43.403522 2, 0xFFFF, sum = 0
1389 00:44:43.403766 3, 0xFFFF, sum = 0
1390 00:44:43.403826 4, 0xFFFF, sum = 0
1391 00:44:43.403880 5, 0xFFFF, sum = 0
1392 00:44:43.403933 6, 0xFFFF, sum = 0
1393 00:44:43.403985 7, 0xFFFF, sum = 0
1394 00:44:43.404038 8, 0xFFFF, sum = 0
1395 00:44:43.404091 9, 0x0, sum = 1
1396 00:44:43.404143 10, 0x0, sum = 2
1397 00:44:43.404196 11, 0x0, sum = 3
1398 00:44:43.404249 12, 0x0, sum = 4
1399 00:44:43.404301 best_step = 10
1400 00:44:43.404352
1401 00:44:43.404403 ==
1402 00:44:43.404455 Dram Type= 6, Freq= 0, CH_0, rank 1
1403 00:44:43.404507 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1404 00:44:43.404565 ==
1405 00:44:43.404652 RX Vref Scan: 0
1406 00:44:43.404704
1407 00:44:43.404755 RX Vref 0 -> 0, step: 1
1408 00:44:43.404806
1409 00:44:43.404858 RX Delay -79 -> 252, step: 8
1410 00:44:43.404910 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1411 00:44:43.404962 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1412 00:44:43.405014 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1413 00:44:43.405066 iDelay=209, Bit 3, Center 84 (-23 ~ 192) 216
1414 00:44:43.405118 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1415 00:44:43.405170 iDelay=209, Bit 5, Center 80 (-31 ~ 192) 224
1416 00:44:43.405221 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1417 00:44:43.405273 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1418 00:44:43.405324 iDelay=209, Bit 8, Center 72 (-31 ~ 176) 208
1419 00:44:43.405376 iDelay=209, Bit 9, Center 72 (-31 ~ 176) 208
1420 00:44:43.405427 iDelay=209, Bit 10, Center 80 (-23 ~ 184) 208
1421 00:44:43.405478 iDelay=209, Bit 11, Center 80 (-23 ~ 184) 208
1422 00:44:43.405529 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1423 00:44:43.405581 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1424 00:44:43.405632 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1425 00:44:43.405684 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1426 00:44:43.405735 ==
1427 00:44:43.405787 Dram Type= 6, Freq= 0, CH_0, rank 1
1428 00:44:43.405838 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1429 00:44:43.405890 ==
1430 00:44:43.405941 DQS Delay:
1431 00:44:43.405992 DQS0 = 0, DQS1 = 0
1432 00:44:43.406043 DQM Delay:
1433 00:44:43.406094 DQM0 = 90, DQM1 = 81
1434 00:44:43.406146 DQ Delay:
1435 00:44:43.406219 DQ0 =88, DQ1 =92, DQ2 =88, DQ3 =84
1436 00:44:43.406274 DQ4 =92, DQ5 =80, DQ6 =100, DQ7 =100
1437 00:44:43.406326 DQ8 =72, DQ9 =72, DQ10 =80, DQ11 =80
1438 00:44:43.406378 DQ12 =84, DQ13 =84, DQ14 =92, DQ15 =88
1439 00:44:43.406429
1440 00:44:43.406481
1441 00:44:43.406532 [DQSOSCAuto] RK1, (LSB)MR18= 0x4922, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 391 ps
1442 00:44:43.406585 CH0 RK1: MR19=606, MR18=4922
1443 00:44:43.406638 CH0_RK1: MR19=0x606, MR18=0x4922, DQSOSC=391, MR23=63, INC=96, DEC=64
1444 00:44:43.406691 [RxdqsGatingPostProcess] freq 800
1445 00:44:43.406743 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1446 00:44:43.406794 Pre-setting of DQS Precalculation
1447 00:44:43.406846 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1448 00:44:43.406897 ==
1449 00:44:43.406949 Dram Type= 6, Freq= 0, CH_1, rank 0
1450 00:44:43.407001 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1451 00:44:43.407052 ==
1452 00:44:43.407104 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1453 00:44:43.407156 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1454 00:44:43.407209 [CA 0] Center 36 (6~67) winsize 62
1455 00:44:43.407260 [CA 1] Center 37 (6~68) winsize 63
1456 00:44:43.407311 [CA 2] Center 35 (5~65) winsize 61
1457 00:44:43.407363 [CA 3] Center 34 (4~65) winsize 62
1458 00:44:43.407414 [CA 4] Center 34 (4~65) winsize 62
1459 00:44:43.407466 [CA 5] Center 33 (3~64) winsize 62
1460 00:44:43.407517
1461 00:44:43.407569 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1462 00:44:43.407620
1463 00:44:43.407671 [CATrainingPosCal] consider 1 rank data
1464 00:44:43.407723 u2DelayCellTimex100 = 270/100 ps
1465 00:44:43.407775 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1466 00:44:43.407827 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1467 00:44:43.407879 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
1468 00:44:43.407931 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1469 00:44:43.407981 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1470 00:44:43.408033 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1471 00:44:43.408084
1472 00:44:43.408135 CA PerBit enable=1, Macro0, CA PI delay=33
1473 00:44:43.408187
1474 00:44:43.408237 [CBTSetCACLKResult] CA Dly = 33
1475 00:44:43.408289 CS Dly: 4 (0~35)
1476 00:44:43.408341 ==
1477 00:44:43.408392 Dram Type= 6, Freq= 0, CH_1, rank 1
1478 00:44:43.408444 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1479 00:44:43.408496 ==
1480 00:44:43.408556 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1481 00:44:43.408643 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1482 00:44:43.408696 [CA 0] Center 37 (6~68) winsize 63
1483 00:44:43.408748 [CA 1] Center 37 (6~68) winsize 63
1484 00:44:43.408800 [CA 2] Center 35 (5~66) winsize 62
1485 00:44:43.408852 [CA 3] Center 34 (4~65) winsize 62
1486 00:44:43.408903 [CA 4] Center 34 (4~65) winsize 62
1487 00:44:43.408954 [CA 5] Center 34 (4~65) winsize 62
1488 00:44:43.409005
1489 00:44:43.409056 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1490 00:44:43.409108
1491 00:44:43.409158 [CATrainingPosCal] consider 2 rank data
1492 00:44:43.409210 u2DelayCellTimex100 = 270/100 ps
1493 00:44:43.409261 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1494 00:44:43.409313 CA1 delay=37 (6~68),Diff = 3 PI (21 cell)
1495 00:44:43.409365 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1496 00:44:43.409416 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1497 00:44:43.409467 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1498 00:44:43.409518 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1499 00:44:43.409573
1500 00:44:43.409638 CA PerBit enable=1, Macro0, CA PI delay=34
1501 00:44:43.409691
1502 00:44:43.409743 [CBTSetCACLKResult] CA Dly = 34
1503 00:44:43.409795 CS Dly: 5 (0~38)
1504 00:44:43.409847
1505 00:44:43.409898 ----->DramcWriteLeveling(PI) begin...
1506 00:44:43.409951 ==
1507 00:44:43.410002 Dram Type= 6, Freq= 0, CH_1, rank 0
1508 00:44:43.410053 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1509 00:44:43.410105 ==
1510 00:44:43.410156 Write leveling (Byte 0): 26 => 26
1511 00:44:43.410208 Write leveling (Byte 1): 29 => 29
1512 00:44:43.410260 DramcWriteLeveling(PI) end<-----
1513 00:44:43.410311
1514 00:44:43.410363 ==
1515 00:44:43.410414 Dram Type= 6, Freq= 0, CH_1, rank 0
1516 00:44:43.410465 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1517 00:44:43.410517 ==
1518 00:44:43.410568 [Gating] SW mode calibration
1519 00:44:43.410817 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1520 00:44:43.410880 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1521 00:44:43.410933 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1522 00:44:43.410987 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1523 00:44:43.411040 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 00:44:43.411092 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 00:44:43.411145 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 00:44:43.411196 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 00:44:43.411248 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 00:44:43.411299 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 00:44:43.411351 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 00:44:43.411403 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 00:44:43.411455 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 00:44:43.411506 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 00:44:43.411557 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 00:44:43.411609 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1535 00:44:43.411661 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1536 00:44:43.411712 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1537 00:44:43.411763 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1538 00:44:43.411815 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1539 00:44:43.411866 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1540 00:44:43.411918 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1541 00:44:43.411969 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1542 00:44:43.412021 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1543 00:44:43.412072 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1544 00:44:43.412124 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1545 00:44:43.412175 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1546 00:44:43.412227 0 9 4 | B1->B0 | 2323 2424 | 1 0 | (1 1) (0 0)
1547 00:44:43.412279 0 9 8 | B1->B0 | 3232 3434 | 1 0 | (1 1) (0 0)
1548 00:44:43.412330 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1549 00:44:43.412382 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1550 00:44:43.412434 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1551 00:44:43.412485 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1552 00:44:43.412537 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1553 00:44:43.412660 0 10 0 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 1)
1554 00:44:43.412742 0 10 4 | B1->B0 | 2f2f 2f2f | 0 0 | (0 0) (0 0)
1555 00:44:43.412825 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1556 00:44:43.412907 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1557 00:44:43.412980 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1558 00:44:43.413034 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1559 00:44:43.413090 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1560 00:44:43.413156 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1561 00:44:43.413209 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1562 00:44:43.413261 0 11 4 | B1->B0 | 2f2f 3232 | 0 0 | (0 0) (0 0)
1563 00:44:43.413313 0 11 8 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
1564 00:44:43.413364 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1565 00:44:43.413416 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1566 00:44:43.413468 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1567 00:44:43.413520 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1568 00:44:43.413571 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1569 00:44:43.413623 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1570 00:44:43.413675 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1571 00:44:43.413726 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1572 00:44:43.413778 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1573 00:44:43.413829 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1574 00:44:43.413881 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1575 00:44:43.413933 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1576 00:44:43.413984 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1577 00:44:43.414036 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1578 00:44:43.414087 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1579 00:44:43.414138 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1580 00:44:43.414190 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1581 00:44:43.414242 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1582 00:44:43.414293 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1583 00:44:43.414345 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1584 00:44:43.414397 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1585 00:44:43.414449 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1586 00:44:43.414500 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1587 00:44:43.414552 Total UI for P1: 0, mck2ui 16
1588 00:44:43.414604 best dqsien dly found for B0: ( 0, 14, 0)
1589 00:44:43.414656 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1590 00:44:43.414708 Total UI for P1: 0, mck2ui 16
1591 00:44:43.414760 best dqsien dly found for B1: ( 0, 14, 2)
1592 00:44:43.414812 best DQS0 dly(MCK, UI, PI) = (0, 14, 0)
1593 00:44:43.414863 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1594 00:44:43.414915
1595 00:44:43.414966 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 0)
1596 00:44:43.415018 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1597 00:44:43.415070 [Gating] SW calibration Done
1598 00:44:43.415121 ==
1599 00:44:43.415173 Dram Type= 6, Freq= 0, CH_1, rank 0
1600 00:44:43.415225 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1601 00:44:43.415276 ==
1602 00:44:43.415328 RX Vref Scan: 0
1603 00:44:43.415379
1604 00:44:43.415430 RX Vref 0 -> 0, step: 1
1605 00:44:43.415482
1606 00:44:43.415533 RX Delay -130 -> 252, step: 16
1607 00:44:43.415585 iDelay=206, Bit 0, Center 101 (-2 ~ 205) 208
1608 00:44:43.415637 iDelay=206, Bit 1, Center 85 (-18 ~ 189) 208
1609 00:44:43.415880 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1610 00:44:43.415938 iDelay=206, Bit 3, Center 93 (-18 ~ 205) 224
1611 00:44:43.415990 iDelay=206, Bit 4, Center 85 (-18 ~ 189) 208
1612 00:44:43.416042 iDelay=206, Bit 5, Center 101 (-2 ~ 205) 208
1613 00:44:43.416094 iDelay=206, Bit 6, Center 101 (-2 ~ 205) 208
1614 00:44:43.416146 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1615 00:44:43.416198 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1616 00:44:43.416250 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1617 00:44:43.416301 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1618 00:44:43.416353 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1619 00:44:43.416417 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
1620 00:44:43.416502 iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224
1621 00:44:43.416616 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1622 00:44:43.416670 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1623 00:44:43.416723 ==
1624 00:44:43.416776 Dram Type= 6, Freq= 0, CH_1, rank 0
1625 00:44:43.416827 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1626 00:44:43.416880 ==
1627 00:44:43.416933 DQS Delay:
1628 00:44:43.416984 DQS0 = 0, DQS1 = 0
1629 00:44:43.417036 DQM Delay:
1630 00:44:43.417087 DQM0 = 92, DQM1 = 82
1631 00:44:43.417139 DQ Delay:
1632 00:44:43.417190 DQ0 =101, DQ1 =85, DQ2 =77, DQ3 =93
1633 00:44:43.417242 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =93
1634 00:44:43.417294 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
1635 00:44:43.417346 DQ12 =93, DQ13 =93, DQ14 =85, DQ15 =85
1636 00:44:43.417397
1637 00:44:43.417448
1638 00:44:43.417499 ==
1639 00:44:43.417550 Dram Type= 6, Freq= 0, CH_1, rank 0
1640 00:44:43.417602 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1641 00:44:43.417654 ==
1642 00:44:43.417705
1643 00:44:43.417755
1644 00:44:43.417806 TX Vref Scan disable
1645 00:44:43.417858 == TX Byte 0 ==
1646 00:44:43.417909 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1647 00:44:43.417961 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1648 00:44:43.418013 == TX Byte 1 ==
1649 00:44:43.418064 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1650 00:44:43.418117 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1651 00:44:43.418168 ==
1652 00:44:43.418219 Dram Type= 6, Freq= 0, CH_1, rank 0
1653 00:44:43.418271 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1654 00:44:43.418323 ==
1655 00:44:43.418374 TX Vref=22, minBit 8, minWin=27, winSum=448
1656 00:44:43.418427 TX Vref=24, minBit 8, minWin=27, winSum=449
1657 00:44:43.418479 TX Vref=26, minBit 10, minWin=27, winSum=452
1658 00:44:43.418531 TX Vref=28, minBit 10, minWin=27, winSum=455
1659 00:44:43.418583 TX Vref=30, minBit 8, minWin=27, winSum=457
1660 00:44:43.418635 TX Vref=32, minBit 8, minWin=27, winSum=455
1661 00:44:43.418687 [TxChooseVref] Worse bit 8, Min win 27, Win sum 457, Final Vref 30
1662 00:44:43.418739
1663 00:44:43.418790 Final TX Range 1 Vref 30
1664 00:44:43.418842
1665 00:44:43.418893 ==
1666 00:44:43.418945 Dram Type= 6, Freq= 0, CH_1, rank 0
1667 00:44:43.418997 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1668 00:44:43.419048 ==
1669 00:44:43.419101
1670 00:44:43.419152
1671 00:44:43.419203 TX Vref Scan disable
1672 00:44:43.419254 == TX Byte 0 ==
1673 00:44:43.419305 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1674 00:44:43.419357 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1675 00:44:43.419430 == TX Byte 1 ==
1676 00:44:43.419484 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1677 00:44:43.419537 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1678 00:44:43.419588
1679 00:44:43.419639 [DATLAT]
1680 00:44:43.419690 Freq=800, CH1 RK0
1681 00:44:43.419742
1682 00:44:43.419793 DATLAT Default: 0xa
1683 00:44:43.419845 0, 0xFFFF, sum = 0
1684 00:44:43.419898 1, 0xFFFF, sum = 0
1685 00:44:43.419950 2, 0xFFFF, sum = 0
1686 00:44:43.420002 3, 0xFFFF, sum = 0
1687 00:44:43.420054 4, 0xFFFF, sum = 0
1688 00:44:43.420106 5, 0xFFFF, sum = 0
1689 00:44:43.420158 6, 0xFFFF, sum = 0
1690 00:44:43.420210 7, 0xFFFF, sum = 0
1691 00:44:43.420263 8, 0xFFFF, sum = 0
1692 00:44:43.420314 9, 0x0, sum = 1
1693 00:44:43.420366 10, 0x0, sum = 2
1694 00:44:43.420419 11, 0x0, sum = 3
1695 00:44:43.420471 12, 0x0, sum = 4
1696 00:44:43.420523 best_step = 10
1697 00:44:43.420587
1698 00:44:43.420639 ==
1699 00:44:43.420691 Dram Type= 6, Freq= 0, CH_1, rank 0
1700 00:44:43.420742 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1701 00:44:43.420794 ==
1702 00:44:43.420845 RX Vref Scan: 1
1703 00:44:43.420896
1704 00:44:43.420947 Set Vref Range= 32 -> 127
1705 00:44:43.420999
1706 00:44:43.421049 RX Vref 32 -> 127, step: 1
1707 00:44:43.421100
1708 00:44:43.421151 RX Delay -95 -> 252, step: 8
1709 00:44:43.421202
1710 00:44:43.421253 Set Vref, RX VrefLevel [Byte0]: 32
1711 00:44:43.421305 [Byte1]: 32
1712 00:44:43.421356
1713 00:44:43.421407 Set Vref, RX VrefLevel [Byte0]: 33
1714 00:44:43.421459 [Byte1]: 33
1715 00:44:43.421511
1716 00:44:43.421562 Set Vref, RX VrefLevel [Byte0]: 34
1717 00:44:43.421614 [Byte1]: 34
1718 00:44:43.421665
1719 00:44:43.421716 Set Vref, RX VrefLevel [Byte0]: 35
1720 00:44:43.421768 [Byte1]: 35
1721 00:44:43.421819
1722 00:44:43.421870 Set Vref, RX VrefLevel [Byte0]: 36
1723 00:44:43.421921 [Byte1]: 36
1724 00:44:43.421973
1725 00:44:43.422024 Set Vref, RX VrefLevel [Byte0]: 37
1726 00:44:43.422076 [Byte1]: 37
1727 00:44:43.422127
1728 00:44:43.422177 Set Vref, RX VrefLevel [Byte0]: 38
1729 00:44:43.422229 [Byte1]: 38
1730 00:44:43.422280
1731 00:44:43.422331 Set Vref, RX VrefLevel [Byte0]: 39
1732 00:44:43.422383 [Byte1]: 39
1733 00:44:43.422434
1734 00:44:43.422485 Set Vref, RX VrefLevel [Byte0]: 40
1735 00:44:43.422536 [Byte1]: 40
1736 00:44:43.422587
1737 00:44:43.422638 Set Vref, RX VrefLevel [Byte0]: 41
1738 00:44:43.422689 [Byte1]: 41
1739 00:44:43.422740
1740 00:44:43.422791 Set Vref, RX VrefLevel [Byte0]: 42
1741 00:44:43.422843 [Byte1]: 42
1742 00:44:43.422894
1743 00:44:43.422944 Set Vref, RX VrefLevel [Byte0]: 43
1744 00:44:43.423016 [Byte1]: 43
1745 00:44:43.423069
1746 00:44:43.423121 Set Vref, RX VrefLevel [Byte0]: 44
1747 00:44:43.423173 [Byte1]: 44
1748 00:44:43.423224
1749 00:44:43.423275 Set Vref, RX VrefLevel [Byte0]: 45
1750 00:44:43.423327 [Byte1]: 45
1751 00:44:43.423378
1752 00:44:43.423428 Set Vref, RX VrefLevel [Byte0]: 46
1753 00:44:43.423480 [Byte1]: 46
1754 00:44:43.423531
1755 00:44:43.423582 Set Vref, RX VrefLevel [Byte0]: 47
1756 00:44:43.423635 [Byte1]: 47
1757 00:44:43.423687
1758 00:44:43.423738 Set Vref, RX VrefLevel [Byte0]: 48
1759 00:44:43.423789 [Byte1]: 48
1760 00:44:43.423840
1761 00:44:43.423890 Set Vref, RX VrefLevel [Byte0]: 49
1762 00:44:43.423942 [Byte1]: 49
1763 00:44:43.423993
1764 00:44:43.424043 Set Vref, RX VrefLevel [Byte0]: 50
1765 00:44:43.424291 [Byte1]: 50
1766 00:44:43.424350
1767 00:44:43.424403 Set Vref, RX VrefLevel [Byte0]: 51
1768 00:44:43.424455 [Byte1]: 51
1769 00:44:43.424507
1770 00:44:43.424567 Set Vref, RX VrefLevel [Byte0]: 52
1771 00:44:43.424619 [Byte1]: 52
1772 00:44:43.424670
1773 00:44:43.424721 Set Vref, RX VrefLevel [Byte0]: 53
1774 00:44:43.424773 [Byte1]: 53
1775 00:44:43.424825
1776 00:44:43.424876 Set Vref, RX VrefLevel [Byte0]: 54
1777 00:44:43.424928 [Byte1]: 54
1778 00:44:43.424979
1779 00:44:43.425030 Set Vref, RX VrefLevel [Byte0]: 55
1780 00:44:43.425082 [Byte1]: 55
1781 00:44:43.425133
1782 00:44:43.425184 Set Vref, RX VrefLevel [Byte0]: 56
1783 00:44:43.425236 [Byte1]: 56
1784 00:44:43.425287
1785 00:44:43.425338 Set Vref, RX VrefLevel [Byte0]: 57
1786 00:44:43.425389 [Byte1]: 57
1787 00:44:43.425441
1788 00:44:43.425491 Set Vref, RX VrefLevel [Byte0]: 58
1789 00:44:43.425542 [Byte1]: 58
1790 00:44:43.425593
1791 00:44:43.425643 Set Vref, RX VrefLevel [Byte0]: 59
1792 00:44:43.425694 [Byte1]: 59
1793 00:44:43.425745
1794 00:44:43.425796 Set Vref, RX VrefLevel [Byte0]: 60
1795 00:44:43.425848 [Byte1]: 60
1796 00:44:43.425899
1797 00:44:43.425950 Set Vref, RX VrefLevel [Byte0]: 61
1798 00:44:43.426002 [Byte1]: 61
1799 00:44:43.426075
1800 00:44:43.426128 Set Vref, RX VrefLevel [Byte0]: 62
1801 00:44:43.426180 [Byte1]: 62
1802 00:44:43.426232
1803 00:44:43.426283 Set Vref, RX VrefLevel [Byte0]: 63
1804 00:44:43.426335 [Byte1]: 63
1805 00:44:43.426386
1806 00:44:43.426437 Set Vref, RX VrefLevel [Byte0]: 64
1807 00:44:43.426488 [Byte1]: 64
1808 00:44:43.426540
1809 00:44:43.426591 Set Vref, RX VrefLevel [Byte0]: 65
1810 00:44:43.426643 [Byte1]: 65
1811 00:44:43.426693
1812 00:44:43.426744 Set Vref, RX VrefLevel [Byte0]: 66
1813 00:44:43.426796 [Byte1]: 66
1814 00:44:43.426848
1815 00:44:43.426899 Set Vref, RX VrefLevel [Byte0]: 67
1816 00:44:43.426950 [Byte1]: 67
1817 00:44:43.427001
1818 00:44:43.427052 Set Vref, RX VrefLevel [Byte0]: 68
1819 00:44:43.427104 [Byte1]: 68
1820 00:44:43.427155
1821 00:44:43.427206 Set Vref, RX VrefLevel [Byte0]: 69
1822 00:44:43.427257 [Byte1]: 69
1823 00:44:43.427308
1824 00:44:43.427359 Set Vref, RX VrefLevel [Byte0]: 70
1825 00:44:43.427410 [Byte1]: 70
1826 00:44:43.427461
1827 00:44:43.427512 Set Vref, RX VrefLevel [Byte0]: 71
1828 00:44:43.427563 [Byte1]: 71
1829 00:44:43.427614
1830 00:44:43.427665 Set Vref, RX VrefLevel [Byte0]: 72
1831 00:44:43.427716 [Byte1]: 72
1832 00:44:43.427767
1833 00:44:43.427817 Set Vref, RX VrefLevel [Byte0]: 73
1834 00:44:43.427869 [Byte1]: 73
1835 00:44:43.427920
1836 00:44:43.427970 Set Vref, RX VrefLevel [Byte0]: 74
1837 00:44:43.428022 [Byte1]: 74
1838 00:44:43.428073
1839 00:44:43.428124 Set Vref, RX VrefLevel [Byte0]: 75
1840 00:44:43.428177 [Byte1]: 75
1841 00:44:43.428228
1842 00:44:43.428279 Final RX Vref Byte 0 = 51 to rank0
1843 00:44:43.428330 Final RX Vref Byte 1 = 62 to rank0
1844 00:44:43.428399 Final RX Vref Byte 0 = 51 to rank1
1845 00:44:43.428452 Final RX Vref Byte 1 = 62 to rank1==
1846 00:44:43.428504 Dram Type= 6, Freq= 0, CH_1, rank 0
1847 00:44:43.428560 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1848 00:44:43.428614 ==
1849 00:44:43.428665 DQS Delay:
1850 00:44:43.428717 DQS0 = 0, DQS1 = 0
1851 00:44:43.428769 DQM Delay:
1852 00:44:43.428820 DQM0 = 92, DQM1 = 83
1853 00:44:43.428871 DQ Delay:
1854 00:44:43.428923 DQ0 =96, DQ1 =84, DQ2 =84, DQ3 =88
1855 00:44:43.428974 DQ4 =92, DQ5 =108, DQ6 =100, DQ7 =88
1856 00:44:43.429026 DQ8 =72, DQ9 =72, DQ10 =88, DQ11 =76
1857 00:44:43.429078 DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =88
1858 00:44:43.429129
1859 00:44:43.429179
1860 00:44:43.429231 [DQSOSCAuto] RK0, (LSB)MR18= 0x3250, (MSB)MR19= 0x606, tDQSOscB0 = 389 ps tDQSOscB1 = 397 ps
1861 00:44:43.429283 CH1 RK0: MR19=606, MR18=3250
1862 00:44:43.429335 CH1_RK0: MR19=0x606, MR18=0x3250, DQSOSC=389, MR23=63, INC=97, DEC=65
1863 00:44:43.429386
1864 00:44:43.429437 ----->DramcWriteLeveling(PI) begin...
1865 00:44:43.429490 ==
1866 00:44:43.429559 Dram Type= 6, Freq= 0, CH_1, rank 1
1867 00:44:43.429614 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1868 00:44:43.429667 ==
1869 00:44:43.429719 Write leveling (Byte 0): 28 => 28
1870 00:44:43.429771 Write leveling (Byte 1): 29 => 29
1871 00:44:43.429822 DramcWriteLeveling(PI) end<-----
1872 00:44:43.429874
1873 00:44:43.429925 ==
1874 00:44:43.429976 Dram Type= 6, Freq= 0, CH_1, rank 1
1875 00:44:43.430028 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1876 00:44:43.430080 ==
1877 00:44:43.430132 [Gating] SW mode calibration
1878 00:44:43.430184 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1879 00:44:43.430236 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1880 00:44:43.430289 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1881 00:44:43.430342 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1882 00:44:43.430417 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 00:44:43.430493 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 00:44:43.430548 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 00:44:43.430601 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 00:44:43.430653 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 00:44:43.430706 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 00:44:43.430758 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 00:44:43.430810 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 00:44:43.430861 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 00:44:43.430912 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 00:44:43.430964 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1893 00:44:43.431016 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1894 00:44:43.431067 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1895 00:44:43.431119 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1896 00:44:43.431171 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1897 00:44:43.431223 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1898 00:44:43.431274 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1899 00:44:43.431518 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1900 00:44:43.431579 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1901 00:44:43.431633 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1902 00:44:43.431684 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1903 00:44:43.431736 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1904 00:44:43.431789 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1905 00:44:43.431841 0 9 4 | B1->B0 | 2424 2323 | 1 0 | (1 1) (0 0)
1906 00:44:43.431893 0 9 8 | B1->B0 | 3434 3030 | 0 0 | (0 0) (0 0)
1907 00:44:43.431945 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1908 00:44:43.431997 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1909 00:44:43.432049 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1910 00:44:43.432100 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1911 00:44:43.432152 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1912 00:44:43.432203 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1913 00:44:43.432256 0 10 4 | B1->B0 | 2e2e 3232 | 0 1 | (1 0) (1 0)
1914 00:44:43.432308 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1915 00:44:43.432361 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1916 00:44:43.432412 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1917 00:44:43.432464 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1918 00:44:43.432515 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1919 00:44:43.432574 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1920 00:44:43.432628 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1921 00:44:43.432680 0 11 4 | B1->B0 | 3030 2828 | 0 0 | (0 0) (0 0)
1922 00:44:43.432731 0 11 8 | B1->B0 | 4545 4141 | 0 0 | (0 0) (0 0)
1923 00:44:43.432788 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1924 00:44:43.432858 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1925 00:44:43.432911 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1926 00:44:43.432963 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1927 00:44:43.433015 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1928 00:44:43.433067 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1929 00:44:43.433119 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1930 00:44:43.433170 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1931 00:44:43.433221 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1932 00:44:43.433273 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1933 00:44:43.433324 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1934 00:44:43.433376 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1935 00:44:43.433427 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1936 00:44:43.433479 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1937 00:44:43.433530 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1938 00:44:43.433582 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1939 00:44:43.433633 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1940 00:44:43.433684 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1941 00:44:43.433736 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1942 00:44:43.433787 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1943 00:44:43.433839 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1944 00:44:43.433891 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1945 00:44:43.433942 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1946 00:44:43.433995 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1947 00:44:43.434047 Total UI for P1: 0, mck2ui 16
1948 00:44:43.434100 best dqsien dly found for B0: ( 0, 14, 4)
1949 00:44:43.434152 Total UI for P1: 0, mck2ui 16
1950 00:44:43.434203 best dqsien dly found for B1: ( 0, 14, 4)
1951 00:44:43.434255 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1952 00:44:43.434306 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1953 00:44:43.434357
1954 00:44:43.434409 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1955 00:44:43.434461 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1956 00:44:43.434512 [Gating] SW calibration Done
1957 00:44:43.434563 ==
1958 00:44:43.434615 Dram Type= 6, Freq= 0, CH_1, rank 1
1959 00:44:43.434666 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1960 00:44:43.434718 ==
1961 00:44:43.434769 RX Vref Scan: 0
1962 00:44:43.434820
1963 00:44:43.434871 RX Vref 0 -> 0, step: 1
1964 00:44:43.434922
1965 00:44:43.434973 RX Delay -130 -> 252, step: 16
1966 00:44:43.435025 iDelay=206, Bit 0, Center 101 (-2 ~ 205) 208
1967 00:44:43.435078 iDelay=206, Bit 1, Center 85 (-18 ~ 189) 208
1968 00:44:43.435129 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1969 00:44:43.435180 iDelay=206, Bit 3, Center 85 (-18 ~ 189) 208
1970 00:44:43.435232 iDelay=206, Bit 4, Center 85 (-18 ~ 189) 208
1971 00:44:43.435283 iDelay=206, Bit 5, Center 101 (-2 ~ 205) 208
1972 00:44:43.435334 iDelay=206, Bit 6, Center 101 (-2 ~ 205) 208
1973 00:44:43.435386 iDelay=206, Bit 7, Center 85 (-18 ~ 189) 208
1974 00:44:43.435437 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1975 00:44:43.435489 iDelay=206, Bit 9, Center 77 (-34 ~ 189) 224
1976 00:44:43.435540 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1977 00:44:43.435591 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1978 00:44:43.435643 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
1979 00:44:43.435694 iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224
1980 00:44:43.435746 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1981 00:44:43.435797 iDelay=206, Bit 15, Center 93 (-18 ~ 205) 224
1982 00:44:43.435848 ==
1983 00:44:43.435900 Dram Type= 6, Freq= 0, CH_1, rank 1
1984 00:44:43.701179 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1985 00:44:43.701705 ==
1986 00:44:43.702062 DQS Delay:
1987 00:44:43.702381 DQS0 = 0, DQS1 = 0
1988 00:44:43.702441 DQM Delay:
1989 00:44:43.702497 DQM0 = 90, DQM1 = 84
1990 00:44:43.702552 DQ Delay:
1991 00:44:43.702605 DQ0 =101, DQ1 =85, DQ2 =77, DQ3 =85
1992 00:44:43.702659 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1993 00:44:43.702711 DQ8 =69, DQ9 =77, DQ10 =85, DQ11 =77
1994 00:44:43.702765 DQ12 =93, DQ13 =93, DQ14 =85, DQ15 =93
1995 00:44:43.702817
1996 00:44:43.702869
1997 00:44:43.702920 ==
1998 00:44:43.702971 Dram Type= 6, Freq= 0, CH_1, rank 1
1999 00:44:43.703024 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2000 00:44:43.703281 ==
2001 00:44:43.703392
2002 00:44:43.703445
2003 00:44:43.703497 TX Vref Scan disable
2004 00:44:43.703551 == TX Byte 0 ==
2005 00:44:43.703603 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2006 00:44:43.703656 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2007 00:44:43.703708 == TX Byte 1 ==
2008 00:44:43.703759 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2009 00:44:43.703824 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2010 00:44:43.703876 ==
2011 00:44:43.703927 Dram Type= 6, Freq= 0, CH_1, rank 1
2012 00:44:43.703978 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2013 00:44:43.704029 ==
2014 00:44:43.704080 TX Vref=22, minBit 8, minWin=27, winSum=450
2015 00:44:43.704132 TX Vref=24, minBit 8, minWin=27, winSum=453
2016 00:44:43.704183 TX Vref=26, minBit 13, minWin=27, winSum=455
2017 00:44:43.704235 TX Vref=28, minBit 13, minWin=27, winSum=458
2018 00:44:43.704286 TX Vref=30, minBit 8, minWin=28, winSum=460
2019 00:44:43.704338 TX Vref=32, minBit 8, minWin=28, winSum=459
2020 00:44:43.704389 [TxChooseVref] Worse bit 8, Min win 28, Win sum 460, Final Vref 30
2021 00:44:43.704441
2022 00:44:43.704492 Final TX Range 1 Vref 30
2023 00:44:43.704542
2024 00:44:43.704655 ==
2025 00:44:43.704706 Dram Type= 6, Freq= 0, CH_1, rank 1
2026 00:44:43.704758 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2027 00:44:43.704810 ==
2028 00:44:43.704860
2029 00:44:43.704910
2030 00:44:43.704961 TX Vref Scan disable
2031 00:44:43.705011 == TX Byte 0 ==
2032 00:44:43.705061 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2033 00:44:43.705112 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2034 00:44:43.705163 == TX Byte 1 ==
2035 00:44:43.705214 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2036 00:44:43.705265 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2037 00:44:43.705315
2038 00:44:43.705407 [DATLAT]
2039 00:44:43.705461 Freq=800, CH1 RK1
2040 00:44:43.705512
2041 00:44:43.705563 DATLAT Default: 0xa
2042 00:44:43.705614 0, 0xFFFF, sum = 0
2043 00:44:43.705666 1, 0xFFFF, sum = 0
2044 00:44:43.705718 2, 0xFFFF, sum = 0
2045 00:44:43.705769 3, 0xFFFF, sum = 0
2046 00:44:43.705821 4, 0xFFFF, sum = 0
2047 00:44:43.705872 5, 0xFFFF, sum = 0
2048 00:44:43.705923 6, 0xFFFF, sum = 0
2049 00:44:43.705974 7, 0xFFFF, sum = 0
2050 00:44:43.706026 8, 0xFFFF, sum = 0
2051 00:44:43.706077 9, 0x0, sum = 1
2052 00:44:43.706128 10, 0x0, sum = 2
2053 00:44:43.706179 11, 0x0, sum = 3
2054 00:44:43.706230 12, 0x0, sum = 4
2055 00:44:43.706282 best_step = 10
2056 00:44:43.706332
2057 00:44:43.706383 ==
2058 00:44:43.706433 Dram Type= 6, Freq= 0, CH_1, rank 1
2059 00:44:43.706484 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2060 00:44:43.706535 ==
2061 00:44:43.706586 RX Vref Scan: 0
2062 00:44:43.706637
2063 00:44:43.706687 RX Vref 0 -> 0, step: 1
2064 00:44:43.706738
2065 00:44:43.706788 RX Delay -95 -> 252, step: 8
2066 00:44:43.706838 iDelay=209, Bit 0, Center 92 (-7 ~ 192) 200
2067 00:44:43.706889 iDelay=209, Bit 1, Center 84 (-15 ~ 184) 200
2068 00:44:43.706941 iDelay=209, Bit 2, Center 80 (-23 ~ 184) 208
2069 00:44:43.706992 iDelay=209, Bit 3, Center 88 (-15 ~ 192) 208
2070 00:44:43.707042 iDelay=209, Bit 4, Center 92 (-7 ~ 192) 200
2071 00:44:43.707093 iDelay=209, Bit 5, Center 108 (9 ~ 208) 200
2072 00:44:43.707144 iDelay=209, Bit 6, Center 100 (1 ~ 200) 200
2073 00:44:43.707194 iDelay=209, Bit 7, Center 88 (-15 ~ 192) 208
2074 00:44:43.707245 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
2075 00:44:43.707296 iDelay=209, Bit 9, Center 76 (-31 ~ 184) 216
2076 00:44:43.707346 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
2077 00:44:43.707397 iDelay=209, Bit 11, Center 80 (-31 ~ 192) 224
2078 00:44:43.707447 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
2079 00:44:43.707498 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
2080 00:44:43.707549 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2081 00:44:43.707599 iDelay=209, Bit 15, Center 92 (-15 ~ 200) 216
2082 00:44:43.707649 ==
2083 00:44:43.707700 Dram Type= 6, Freq= 0, CH_1, rank 1
2084 00:44:43.707751 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2085 00:44:43.707804 ==
2086 00:44:43.707855 DQS Delay:
2087 00:44:43.707929 DQS0 = 0, DQS1 = 0
2088 00:44:43.707995 DQM Delay:
2089 00:44:43.708046 DQM0 = 91, DQM1 = 83
2090 00:44:43.708098 DQ Delay:
2091 00:44:43.708149 DQ0 =92, DQ1 =84, DQ2 =80, DQ3 =88
2092 00:44:43.708201 DQ4 =92, DQ5 =108, DQ6 =100, DQ7 =88
2093 00:44:43.708252 DQ8 =68, DQ9 =76, DQ10 =84, DQ11 =80
2094 00:44:43.708304 DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =92
2095 00:44:43.708356
2096 00:44:43.708423
2097 00:44:43.708516 [DQSOSCAuto] RK1, (LSB)MR18= 0x3a0f, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 395 ps
2098 00:44:43.708638 CH1 RK1: MR19=606, MR18=3A0F
2099 00:44:43.708693 CH1_RK1: MR19=0x606, MR18=0x3A0F, DQSOSC=395, MR23=63, INC=94, DEC=63
2100 00:44:43.708747 [RxdqsGatingPostProcess] freq 800
2101 00:44:43.708800 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2102 00:44:43.708852 Pre-setting of DQS Precalculation
2103 00:44:43.708906 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2104 00:44:43.708959 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2105 00:44:43.709012 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2106 00:44:43.709065
2107 00:44:43.709117
2108 00:44:43.709169 [Calibration Summary] 1600 Mbps
2109 00:44:43.709223 CH 0, Rank 0
2110 00:44:43.709275 SW Impedance : PASS
2111 00:44:43.709328 DUTY Scan : NO K
2112 00:44:43.709381 ZQ Calibration : PASS
2113 00:44:43.709434 Jitter Meter : NO K
2114 00:44:43.709486 CBT Training : PASS
2115 00:44:43.709539 Write leveling : PASS
2116 00:44:43.709592 RX DQS gating : PASS
2117 00:44:43.709644 RX DQ/DQS(RDDQC) : PASS
2118 00:44:43.709696 TX DQ/DQS : PASS
2119 00:44:43.709748 RX DATLAT : PASS
2120 00:44:43.709801 RX DQ/DQS(Engine): PASS
2121 00:44:43.709852 TX OE : NO K
2122 00:44:43.709905 All Pass.
2123 00:44:43.709956
2124 00:44:43.710008 CH 0, Rank 1
2125 00:44:43.710060 SW Impedance : PASS
2126 00:44:43.710112 DUTY Scan : NO K
2127 00:44:43.710164 ZQ Calibration : PASS
2128 00:44:43.710217 Jitter Meter : NO K
2129 00:44:43.710269 CBT Training : PASS
2130 00:44:43.710321 Write leveling : PASS
2131 00:44:43.710374 RX DQS gating : PASS
2132 00:44:43.710426 RX DQ/DQS(RDDQC) : PASS
2133 00:44:43.710479 TX DQ/DQS : PASS
2134 00:44:43.710532 RX DATLAT : PASS
2135 00:44:43.710584 RX DQ/DQS(Engine): PASS
2136 00:44:43.710636 TX OE : NO K
2137 00:44:43.710689 All Pass.
2138 00:44:43.710741
2139 00:44:43.710793 CH 1, Rank 0
2140 00:44:43.710844 SW Impedance : PASS
2141 00:44:43.710897 DUTY Scan : NO K
2142 00:44:43.710949 ZQ Calibration : PASS
2143 00:44:43.711001 Jitter Meter : NO K
2144 00:44:43.711053 CBT Training : PASS
2145 00:44:43.711105 Write leveling : PASS
2146 00:44:43.711157 RX DQS gating : PASS
2147 00:44:43.711406 RX DQ/DQS(RDDQC) : PASS
2148 00:44:43.711518 TX DQ/DQS : PASS
2149 00:44:43.711586 RX DATLAT : PASS
2150 00:44:43.711638 RX DQ/DQS(Engine): PASS
2151 00:44:43.711691 TX OE : NO K
2152 00:44:43.711743 All Pass.
2153 00:44:43.711817
2154 00:44:43.711881 CH 1, Rank 1
2155 00:44:43.711936 SW Impedance : PASS
2156 00:44:43.711989 DUTY Scan : NO K
2157 00:44:43.712042 ZQ Calibration : PASS
2158 00:44:43.712095 Jitter Meter : NO K
2159 00:44:43.712148 CBT Training : PASS
2160 00:44:43.712200 Write leveling : PASS
2161 00:44:43.712252 RX DQS gating : PASS
2162 00:44:43.712304 RX DQ/DQS(RDDQC) : PASS
2163 00:44:43.712357 TX DQ/DQS : PASS
2164 00:44:43.712410 RX DATLAT : PASS
2165 00:44:43.712463 RX DQ/DQS(Engine): PASS
2166 00:44:43.712515 TX OE : NO K
2167 00:44:43.712592 All Pass.
2168 00:44:43.712659
2169 00:44:43.712711 DramC Write-DBI off
2170 00:44:43.712764 PER_BANK_REFRESH: Hybrid Mode
2171 00:44:43.712816 TX_TRACKING: ON
2172 00:44:43.712869 [GetDramInforAfterCalByMRR] Vendor 6.
2173 00:44:43.712921 [GetDramInforAfterCalByMRR] Revision 606.
2174 00:44:43.712974 [GetDramInforAfterCalByMRR] Revision 2 0.
2175 00:44:43.713026 MR0 0x3b3b
2176 00:44:43.713079 MR8 0x5151
2177 00:44:43.713131 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2178 00:44:43.713183
2179 00:44:43.713235 MR0 0x3b3b
2180 00:44:43.713287 MR8 0x5151
2181 00:44:43.713339 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2182 00:44:43.713408
2183 00:44:43.713470 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2184 00:44:43.713539 [FAST_K] Save calibration result to emmc
2185 00:44:43.713592 [FAST_K] Save calibration result to emmc
2186 00:44:43.713644 dram_init: config_dvfs: 1
2187 00:44:43.713697 dramc_set_vcore_voltage set vcore to 662500
2188 00:44:43.713749 Read voltage for 1200, 2
2189 00:44:43.713801 Vio18 = 0
2190 00:44:43.713853 Vcore = 662500
2191 00:44:43.713905 Vdram = 0
2192 00:44:43.713957 Vddq = 0
2193 00:44:43.714010 Vmddr = 0
2194 00:44:43.714062 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2195 00:44:43.714115 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2196 00:44:43.714168 MEM_TYPE=3, freq_sel=15
2197 00:44:43.714221 sv_algorithm_assistance_LP4_1600
2198 00:44:43.714273 ============ PULL DRAM RESETB DOWN ============
2199 00:44:43.714326 ========== PULL DRAM RESETB DOWN end =========
2200 00:44:43.714380 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2201 00:44:43.714433 ===================================
2202 00:44:43.714485 LPDDR4 DRAM CONFIGURATION
2203 00:44:43.714538 ===================================
2204 00:44:43.714590 EX_ROW_EN[0] = 0x0
2205 00:44:43.714643 EX_ROW_EN[1] = 0x0
2206 00:44:43.714695 LP4Y_EN = 0x0
2207 00:44:43.714747 WORK_FSP = 0x0
2208 00:44:43.714799 WL = 0x4
2209 00:44:43.714852 RL = 0x4
2210 00:44:43.714904 BL = 0x2
2211 00:44:43.714956 RPST = 0x0
2212 00:44:43.715008 RD_PRE = 0x0
2213 00:44:43.715060 WR_PRE = 0x1
2214 00:44:43.715112 WR_PST = 0x0
2215 00:44:43.715163 DBI_WR = 0x0
2216 00:44:43.715224 DBI_RD = 0x0
2217 00:44:43.715284 OTF = 0x1
2218 00:44:43.715337 ===================================
2219 00:44:43.715390 ===================================
2220 00:44:43.715450 ANA top config
2221 00:44:43.715503 ===================================
2222 00:44:43.715556 DLL_ASYNC_EN = 0
2223 00:44:43.715608 ALL_SLAVE_EN = 0
2224 00:44:43.715660 NEW_RANK_MODE = 1
2225 00:44:43.715713 DLL_IDLE_MODE = 1
2226 00:44:43.715766 LP45_APHY_COMB_EN = 1
2227 00:44:43.715818 TX_ODT_DIS = 1
2228 00:44:43.715870 NEW_8X_MODE = 1
2229 00:44:43.715923 ===================================
2230 00:44:43.715975 ===================================
2231 00:44:43.716028 data_rate = 2400
2232 00:44:43.716080 CKR = 1
2233 00:44:43.716133 DQ_P2S_RATIO = 8
2234 00:44:43.716185 ===================================
2235 00:44:43.716238 CA_P2S_RATIO = 8
2236 00:44:43.716290 DQ_CA_OPEN = 0
2237 00:44:43.716342 DQ_SEMI_OPEN = 0
2238 00:44:43.716394 CA_SEMI_OPEN = 0
2239 00:44:43.716446 CA_FULL_RATE = 0
2240 00:44:43.716498 DQ_CKDIV4_EN = 0
2241 00:44:43.716558 CA_CKDIV4_EN = 0
2242 00:44:43.716661 CA_PREDIV_EN = 0
2243 00:44:43.716713 PH8_DLY = 17
2244 00:44:43.716779 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2245 00:44:43.716832 DQ_AAMCK_DIV = 4
2246 00:44:43.716885 CA_AAMCK_DIV = 4
2247 00:44:43.716937 CA_ADMCK_DIV = 4
2248 00:44:43.716989 DQ_TRACK_CA_EN = 0
2249 00:44:43.717042 CA_PICK = 1200
2250 00:44:43.717094 CA_MCKIO = 1200
2251 00:44:43.717146 MCKIO_SEMI = 0
2252 00:44:43.717198 PLL_FREQ = 2366
2253 00:44:43.717251 DQ_UI_PI_RATIO = 32
2254 00:44:43.717303 CA_UI_PI_RATIO = 0
2255 00:44:43.717356 ===================================
2256 00:44:43.717408 ===================================
2257 00:44:43.717477 memory_type:LPDDR4
2258 00:44:43.717543 GP_NUM : 10
2259 00:44:43.717595 SRAM_EN : 1
2260 00:44:43.717648 MD32_EN : 0
2261 00:44:43.717700 ===================================
2262 00:44:43.717752 [ANA_INIT] >>>>>>>>>>>>>>
2263 00:44:43.717805 <<<<<< [CONFIGURE PHASE]: ANA_TX
2264 00:44:43.717858 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2265 00:44:43.717910 ===================================
2266 00:44:43.717962 data_rate = 2400,PCW = 0X5b00
2267 00:44:43.718015 ===================================
2268 00:44:43.718067 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2269 00:44:43.718120 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2270 00:44:43.718173 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2271 00:44:43.718226 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2272 00:44:43.718278 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2273 00:44:43.718330 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2274 00:44:43.718383 [ANA_INIT] flow start
2275 00:44:43.718436 [ANA_INIT] PLL >>>>>>>>
2276 00:44:43.718488 [ANA_INIT] PLL <<<<<<<<
2277 00:44:43.718541 [ANA_INIT] MIDPI >>>>>>>>
2278 00:44:43.718592 [ANA_INIT] MIDPI <<<<<<<<
2279 00:44:43.718646 [ANA_INIT] DLL >>>>>>>>
2280 00:44:43.718715 [ANA_INIT] DLL <<<<<<<<
2281 00:44:43.718784 [ANA_INIT] flow end
2282 00:44:43.718850 ============ LP4 DIFF to SE enter ============
2283 00:44:43.718904 ============ LP4 DIFF to SE exit ============
2284 00:44:43.719162 [ANA_INIT] <<<<<<<<<<<<<
2285 00:44:43.719223 [Flow] Enable top DCM control >>>>>
2286 00:44:43.719278 [Flow] Enable top DCM control <<<<<
2287 00:44:43.719332 Enable DLL master slave shuffle
2288 00:44:43.719385 ==============================================================
2289 00:44:43.719439 Gating Mode config
2290 00:44:43.719493 ==============================================================
2291 00:44:43.719547 Config description:
2292 00:44:43.719600 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2293 00:44:43.719655 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2294 00:44:43.719709 SELPH_MODE 0: By rank 1: By Phase
2295 00:44:43.719764 ==============================================================
2296 00:44:43.719817 GAT_TRACK_EN = 1
2297 00:44:43.719870 RX_GATING_MODE = 2
2298 00:44:43.719923 RX_GATING_TRACK_MODE = 2
2299 00:44:43.719976 SELPH_MODE = 1
2300 00:44:43.720029 PICG_EARLY_EN = 1
2301 00:44:43.720082 VALID_LAT_VALUE = 1
2302 00:44:43.720135 ==============================================================
2303 00:44:43.720189 Enter into Gating configuration >>>>
2304 00:44:43.720242 Exit from Gating configuration <<<<
2305 00:44:43.720295 Enter into DVFS_PRE_config >>>>>
2306 00:44:43.720348 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2307 00:44:43.720402 Exit from DVFS_PRE_config <<<<<
2308 00:44:43.720455 Enter into PICG configuration >>>>
2309 00:44:43.720507 Exit from PICG configuration <<<<
2310 00:44:43.720569 [RX_INPUT] configuration >>>>>
2311 00:44:43.720624 [RX_INPUT] configuration <<<<<
2312 00:44:43.720677 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2313 00:44:43.720730 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2314 00:44:43.720784 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2315 00:44:43.720838 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2316 00:44:43.720892 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2317 00:44:43.720945 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2318 00:44:43.720997 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2319 00:44:43.721051 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2320 00:44:43.721117 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2321 00:44:43.721169 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2322 00:44:43.721221 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2323 00:44:43.721273 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2324 00:44:43.721326 ===================================
2325 00:44:43.721379 LPDDR4 DRAM CONFIGURATION
2326 00:44:43.721432 ===================================
2327 00:44:43.721484 EX_ROW_EN[0] = 0x0
2328 00:44:43.721536 EX_ROW_EN[1] = 0x0
2329 00:44:43.721588 LP4Y_EN = 0x0
2330 00:44:43.721640 WORK_FSP = 0x0
2331 00:44:43.721692 WL = 0x4
2332 00:44:43.721744 RL = 0x4
2333 00:44:43.721796 BL = 0x2
2334 00:44:43.721848 RPST = 0x0
2335 00:44:43.721901 RD_PRE = 0x0
2336 00:44:43.721952 WR_PRE = 0x1
2337 00:44:43.722004 WR_PST = 0x0
2338 00:44:43.722056 DBI_WR = 0x0
2339 00:44:43.722107 DBI_RD = 0x0
2340 00:44:43.722160 OTF = 0x1
2341 00:44:43.722212 ===================================
2342 00:44:43.722264 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2343 00:44:43.722317 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2344 00:44:43.722369 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2345 00:44:43.722422 ===================================
2346 00:44:43.722474 LPDDR4 DRAM CONFIGURATION
2347 00:44:43.722526 ===================================
2348 00:44:43.722598 EX_ROW_EN[0] = 0x10
2349 00:44:43.722678 EX_ROW_EN[1] = 0x0
2350 00:44:43.722757 LP4Y_EN = 0x0
2351 00:44:43.722829 WORK_FSP = 0x0
2352 00:44:43.722881 WL = 0x4
2353 00:44:43.722933 RL = 0x4
2354 00:44:43.722985 BL = 0x2
2355 00:44:43.723037 RPST = 0x0
2356 00:44:43.723089 RD_PRE = 0x0
2357 00:44:43.723141 WR_PRE = 0x1
2358 00:44:43.723193 WR_PST = 0x0
2359 00:44:43.723245 DBI_WR = 0x0
2360 00:44:43.723297 DBI_RD = 0x0
2361 00:44:43.723348 OTF = 0x1
2362 00:44:43.723399 ===================================
2363 00:44:43.723450 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2364 00:44:43.723501 ==
2365 00:44:43.723552 Dram Type= 6, Freq= 0, CH_0, rank 0
2366 00:44:43.723603 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2367 00:44:43.723654 ==
2368 00:44:43.723705 [Duty_Offset_Calibration]
2369 00:44:43.723756 B0:2 B1:0 CA:1
2370 00:44:43.723806
2371 00:44:43.723856 [DutyScan_Calibration_Flow] k_type=0
2372 00:44:43.723906
2373 00:44:43.723956 ==CLK 0==
2374 00:44:43.724007 Final CLK duty delay cell = -4
2375 00:44:43.724058 [-4] MAX Duty = 5031%(X100), DQS PI = 24
2376 00:44:43.724109 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2377 00:44:43.724159 [-4] AVG Duty = 4953%(X100)
2378 00:44:43.724210
2379 00:44:43.724260 CH0 CLK Duty spec in!! Max-Min= 156%
2380 00:44:43.724311 [DutyScan_Calibration_Flow] ====Done====
2381 00:44:43.724361
2382 00:44:43.724411 [DutyScan_Calibration_Flow] k_type=1
2383 00:44:43.724461
2384 00:44:43.724511 ==DQS 0 ==
2385 00:44:43.724584 Final DQS duty delay cell = 0
2386 00:44:43.724650 [0] MAX Duty = 5187%(X100), DQS PI = 30
2387 00:44:43.724700 [0] MIN Duty = 4938%(X100), DQS PI = 0
2388 00:44:43.724767 [0] AVG Duty = 5062%(X100)
2389 00:44:43.724818
2390 00:44:43.724897 ==DQS 1 ==
2391 00:44:43.724977 Final DQS duty delay cell = -4
2392 00:44:43.725070 [-4] MAX Duty = 5124%(X100), DQS PI = 32
2393 00:44:43.725123 [-4] MIN Duty = 4907%(X100), DQS PI = 8
2394 00:44:43.725175 [-4] AVG Duty = 5015%(X100)
2395 00:44:43.725225
2396 00:44:43.725276 CH0 DQS 0 Duty spec in!! Max-Min= 249%
2397 00:44:43.725327
2398 00:44:43.725377 CH0 DQS 1 Duty spec in!! Max-Min= 217%
2399 00:44:43.725428 [DutyScan_Calibration_Flow] ====Done====
2400 00:44:43.725478
2401 00:44:43.725528 [DutyScan_Calibration_Flow] k_type=3
2402 00:44:43.725579
2403 00:44:43.725630 ==DQM 0 ==
2404 00:44:43.725681 Final DQM duty delay cell = 0
2405 00:44:43.725732 [0] MAX Duty = 5062%(X100), DQS PI = 24
2406 00:44:43.725976 [0] MIN Duty = 4813%(X100), DQS PI = 0
2407 00:44:43.726087 [0] AVG Duty = 4937%(X100)
2408 00:44:43.726140
2409 00:44:43.726192 ==DQM 1 ==
2410 00:44:43.726243 Final DQM duty delay cell = 0
2411 00:44:43.726296 [0] MAX Duty = 5187%(X100), DQS PI = 48
2412 00:44:43.726347 [0] MIN Duty = 5000%(X100), DQS PI = 12
2413 00:44:43.726399 [0] AVG Duty = 5093%(X100)
2414 00:44:43.726451
2415 00:44:43.726515 CH0 DQM 0 Duty spec in!! Max-Min= 249%
2416 00:44:43.726566
2417 00:44:43.726616 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2418 00:44:43.726666 [DutyScan_Calibration_Flow] ====Done====
2419 00:44:43.726734
2420 00:44:43.726785 [DutyScan_Calibration_Flow] k_type=2
2421 00:44:43.726849
2422 00:44:43.726899 ==DQ 0 ==
2423 00:44:43.726950 Final DQ duty delay cell = -4
2424 00:44:43.727001 [-4] MAX Duty = 5031%(X100), DQS PI = 34
2425 00:44:43.727052 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2426 00:44:43.727102 [-4] AVG Duty = 4953%(X100)
2427 00:44:43.727153
2428 00:44:43.727203 ==DQ 1 ==
2429 00:44:43.727253 Final DQ duty delay cell = 4
2430 00:44:43.727304 [4] MAX Duty = 5093%(X100), DQS PI = 4
2431 00:44:43.727355 [4] MIN Duty = 5031%(X100), DQS PI = 0
2432 00:44:43.727405 [4] AVG Duty = 5062%(X100)
2433 00:44:43.727455
2434 00:44:43.727506 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2435 00:44:43.727556
2436 00:44:43.727607 CH0 DQ 1 Duty spec in!! Max-Min= 62%
2437 00:44:43.727657 [DutyScan_Calibration_Flow] ====Done====
2438 00:44:43.727708 ==
2439 00:44:43.727758 Dram Type= 6, Freq= 0, CH_1, rank 0
2440 00:44:43.727809 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2441 00:44:43.727861 ==
2442 00:44:43.727912 [Duty_Offset_Calibration]
2443 00:44:43.727962 B0:0 B1:-1 CA:2
2444 00:44:43.728012
2445 00:44:43.728063 [DutyScan_Calibration_Flow] k_type=0
2446 00:44:43.728114
2447 00:44:43.728164 ==CLK 0==
2448 00:44:43.728215 Final CLK duty delay cell = 0
2449 00:44:43.728266 [0] MAX Duty = 5156%(X100), DQS PI = 16
2450 00:44:43.728316 [0] MIN Duty = 4938%(X100), DQS PI = 44
2451 00:44:43.728366 [0] AVG Duty = 5047%(X100)
2452 00:44:43.728416
2453 00:44:43.728466 CH1 CLK Duty spec in!! Max-Min= 218%
2454 00:44:43.728533 [DutyScan_Calibration_Flow] ====Done====
2455 00:44:43.728622
2456 00:44:43.728674 [DutyScan_Calibration_Flow] k_type=1
2457 00:44:43.728741
2458 00:44:43.728793 ==DQS 0 ==
2459 00:44:43.728845 Final DQS duty delay cell = 0
2460 00:44:43.728909 [0] MAX Duty = 5093%(X100), DQS PI = 24
2461 00:44:43.728960 [0] MIN Duty = 4969%(X100), DQS PI = 0
2462 00:44:43.729010 [0] AVG Duty = 5031%(X100)
2463 00:44:43.729061
2464 00:44:43.729111 ==DQS 1 ==
2465 00:44:43.729162 Final DQS duty delay cell = 0
2466 00:44:43.729213 [0] MAX Duty = 5156%(X100), DQS PI = 0
2467 00:44:43.729264 [0] MIN Duty = 4844%(X100), DQS PI = 34
2468 00:44:43.729315 [0] AVG Duty = 5000%(X100)
2469 00:44:43.729365
2470 00:44:43.729416 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2471 00:44:43.729466
2472 00:44:43.729516 CH1 DQS 1 Duty spec in!! Max-Min= 312%
2473 00:44:43.729566 [DutyScan_Calibration_Flow] ====Done====
2474 00:44:43.729617
2475 00:44:43.729667 [DutyScan_Calibration_Flow] k_type=3
2476 00:44:43.729718
2477 00:44:43.729768 ==DQM 0 ==
2478 00:44:43.729818 Final DQM duty delay cell = 4
2479 00:44:43.729870 [4] MAX Duty = 5093%(X100), DQS PI = 20
2480 00:44:43.729920 [4] MIN Duty = 4907%(X100), DQS PI = 44
2481 00:44:43.729971 [4] AVG Duty = 5000%(X100)
2482 00:44:43.730021
2483 00:44:43.730071 ==DQM 1 ==
2484 00:44:43.730122 Final DQM duty delay cell = -4
2485 00:44:43.730174 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2486 00:44:43.730225 [-4] MIN Duty = 4751%(X100), DQS PI = 36
2487 00:44:43.730276 [-4] AVG Duty = 4875%(X100)
2488 00:44:43.730327
2489 00:44:43.730378 CH1 DQM 0 Duty spec in!! Max-Min= 186%
2490 00:44:43.730428
2491 00:44:43.730478 CH1 DQM 1 Duty spec in!! Max-Min= 249%
2492 00:44:43.730529 [DutyScan_Calibration_Flow] ====Done====
2493 00:44:43.730580
2494 00:44:43.730629 [DutyScan_Calibration_Flow] k_type=2
2495 00:44:43.730680
2496 00:44:43.730730 ==DQ 0 ==
2497 00:44:43.730781 Final DQ duty delay cell = 0
2498 00:44:43.730833 [0] MAX Duty = 5031%(X100), DQS PI = 16
2499 00:44:43.730918 [0] MIN Duty = 4938%(X100), DQS PI = 0
2500 00:44:43.730969 [0] AVG Duty = 4984%(X100)
2501 00:44:43.731019
2502 00:44:43.731069 ==DQ 1 ==
2503 00:44:43.731120 Final DQ duty delay cell = 0
2504 00:44:43.731171 [0] MAX Duty = 5031%(X100), DQS PI = 2
2505 00:44:43.731222 [0] MIN Duty = 4813%(X100), DQS PI = 36
2506 00:44:43.731272 [0] AVG Duty = 4922%(X100)
2507 00:44:43.731323
2508 00:44:43.731373 CH1 DQ 0 Duty spec in!! Max-Min= 93%
2509 00:44:43.731424
2510 00:44:43.731474 CH1 DQ 1 Duty spec in!! Max-Min= 218%
2511 00:44:43.731524 [DutyScan_Calibration_Flow] ====Done====
2512 00:44:43.731575 nWR fixed to 30
2513 00:44:43.731626 [ModeRegInit_LP4] CH0 RK0
2514 00:44:43.731677 [ModeRegInit_LP4] CH0 RK1
2515 00:44:43.731727 [ModeRegInit_LP4] CH1 RK0
2516 00:44:43.731827 [ModeRegInit_LP4] CH1 RK1
2517 00:44:43.731880 match AC timing 7
2518 00:44:43.731931 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2519 00:44:43.731983 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2520 00:44:43.732033 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2521 00:44:43.732085 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2522 00:44:43.732136 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2523 00:44:43.732188 ==
2524 00:44:43.732239 Dram Type= 6, Freq= 0, CH_0, rank 0
2525 00:44:43.732289 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2526 00:44:43.732341 ==
2527 00:44:43.732391 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2528 00:44:43.732442 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2529 00:44:43.732494 [CA 0] Center 38 (8~69) winsize 62
2530 00:44:43.732618 [CA 1] Center 38 (7~69) winsize 63
2531 00:44:43.732672 [CA 2] Center 35 (5~66) winsize 62
2532 00:44:43.732723 [CA 3] Center 35 (5~66) winsize 62
2533 00:44:43.732774 [CA 4] Center 34 (4~65) winsize 62
2534 00:44:43.732824 [CA 5] Center 33 (3~63) winsize 61
2535 00:44:43.732892
2536 00:44:43.732987 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2537 00:44:43.733038
2538 00:44:43.733088 [CATrainingPosCal] consider 1 rank data
2539 00:44:43.733139 u2DelayCellTimex100 = 270/100 ps
2540 00:44:43.733190 CA0 delay=38 (8~69),Diff = 5 PI (24 cell)
2541 00:44:43.733240 CA1 delay=38 (7~69),Diff = 5 PI (24 cell)
2542 00:44:43.733291 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2543 00:44:43.733342 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2544 00:44:43.733393 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2545 00:44:43.733443 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2546 00:44:43.733493
2547 00:44:43.733543 CA PerBit enable=1, Macro0, CA PI delay=33
2548 00:44:43.733593
2549 00:44:43.733643 [CBTSetCACLKResult] CA Dly = 33
2550 00:44:43.733694 CS Dly: 6 (0~37)
2551 00:44:43.733744 ==
2552 00:44:43.733795 Dram Type= 6, Freq= 0, CH_0, rank 1
2553 00:44:43.733845 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2554 00:44:43.733896 ==
2555 00:44:43.734143 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2556 00:44:43.734200 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2557 00:44:43.734253 [CA 0] Center 39 (8~70) winsize 63
2558 00:44:43.734304 [CA 1] Center 38 (8~69) winsize 62
2559 00:44:43.734355 [CA 2] Center 35 (5~66) winsize 62
2560 00:44:43.734421 [CA 3] Center 35 (5~66) winsize 62
2561 00:44:43.734485 [CA 4] Center 34 (4~65) winsize 62
2562 00:44:43.734535 [CA 5] Center 34 (4~64) winsize 61
2563 00:44:43.734586
2564 00:44:43.734636 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2565 00:44:43.734687
2566 00:44:43.734737 [CATrainingPosCal] consider 2 rank data
2567 00:44:43.734788 u2DelayCellTimex100 = 270/100 ps
2568 00:44:43.734839 CA0 delay=38 (8~69),Diff = 5 PI (24 cell)
2569 00:44:43.734920 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2570 00:44:43.734971 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2571 00:44:43.735022 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2572 00:44:43.735073 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2573 00:44:43.735124 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
2574 00:44:43.735174
2575 00:44:43.735225 CA PerBit enable=1, Macro0, CA PI delay=33
2576 00:44:43.735282
2577 00:44:43.735343 [CBTSetCACLKResult] CA Dly = 33
2578 00:44:43.735394 CS Dly: 7 (0~39)
2579 00:44:43.735445
2580 00:44:43.735495 ----->DramcWriteLeveling(PI) begin...
2581 00:44:43.735547 ==
2582 00:44:43.735597 Dram Type= 6, Freq= 0, CH_0, rank 0
2583 00:44:43.735648 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2584 00:44:43.735699 ==
2585 00:44:43.735750 Write leveling (Byte 0): 34 => 34
2586 00:44:43.735800 Write leveling (Byte 1): 31 => 31
2587 00:44:43.735850 DramcWriteLeveling(PI) end<-----
2588 00:44:43.735900
2589 00:44:43.735949 ==
2590 00:44:43.736000 Dram Type= 6, Freq= 0, CH_0, rank 0
2591 00:44:43.736050 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2592 00:44:43.736101 ==
2593 00:44:43.736151 [Gating] SW mode calibration
2594 00:44:43.736203 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2595 00:44:43.736254 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2596 00:44:43.736305 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2597 00:44:43.736356 0 15 4 | B1->B0 | 2e2e 3434 | 0 1 | (0 0) (1 1)
2598 00:44:43.736406 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2599 00:44:43.736457 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2600 00:44:43.736507 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2601 00:44:43.736568 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2602 00:44:43.736658 0 15 24 | B1->B0 | 3434 2e2e | 1 1 | (1 1) (1 0)
2603 00:44:43.736708 0 15 28 | B1->B0 | 3434 2727 | 1 0 | (1 1) (0 1)
2604 00:44:43.736759 1 0 0 | B1->B0 | 2a2a 2323 | 1 0 | (1 0) (0 0)
2605 00:44:43.736810 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2606 00:44:43.736879 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2607 00:44:43.736972 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2608 00:44:43.737067 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2609 00:44:43.737131 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2610 00:44:43.737182 1 0 24 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
2611 00:44:43.737231 1 0 28 | B1->B0 | 2727 4646 | 0 0 | (0 0) (0 0)
2612 00:44:43.737282 1 1 0 | B1->B0 | 3131 4646 | 1 0 | (0 0) (0 0)
2613 00:44:43.737332 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2614 00:44:43.737383 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2615 00:44:43.737433 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2616 00:44:43.737484 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2617 00:44:43.737534 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2618 00:44:43.737584 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2619 00:44:43.737634 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2620 00:44:43.737685 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2621 00:44:43.737735 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2622 00:44:43.737785 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2623 00:44:43.737836 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2624 00:44:43.737886 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2625 00:44:43.737937 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2626 00:44:43.737988 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2627 00:44:43.738067 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2628 00:44:43.738118 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2629 00:44:43.738168 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2630 00:44:43.738218 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2631 00:44:43.738269 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2632 00:44:43.738319 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2633 00:44:43.738369 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2634 00:44:43.738468 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2635 00:44:43.738522 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2636 00:44:43.738573 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2637 00:44:43.738625 Total UI for P1: 0, mck2ui 16
2638 00:44:43.738676 best dqsien dly found for B0: ( 1, 3, 26)
2639 00:44:43.738728 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2640 00:44:43.738820 Total UI for P1: 0, mck2ui 16
2641 00:44:43.738918 best dqsien dly found for B1: ( 1, 4, 0)
2642 00:44:43.738983 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2643 00:44:43.739035 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2644 00:44:43.739086
2645 00:44:43.739136 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2646 00:44:43.739187 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2647 00:44:43.739238 [Gating] SW calibration Done
2648 00:44:43.739288 ==
2649 00:44:43.739358 Dram Type= 6, Freq= 0, CH_0, rank 0
2650 00:44:43.739410 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2651 00:44:43.739462 ==
2652 00:44:43.739514 RX Vref Scan: 0
2653 00:44:43.739565
2654 00:44:43.739616 RX Vref 0 -> 0, step: 1
2655 00:44:43.739668
2656 00:44:43.739720 RX Delay -40 -> 252, step: 8
2657 00:44:43.739771 iDelay=208, Bit 0, Center 119 (48 ~ 191) 144
2658 00:44:43.739823 iDelay=208, Bit 1, Center 119 (48 ~ 191) 144
2659 00:44:43.739874 iDelay=208, Bit 2, Center 119 (48 ~ 191) 144
2660 00:44:43.740118 iDelay=208, Bit 3, Center 119 (48 ~ 191) 144
2661 00:44:43.740178 iDelay=208, Bit 4, Center 127 (56 ~ 199) 144
2662 00:44:43.740230 iDelay=208, Bit 5, Center 115 (48 ~ 183) 136
2663 00:44:43.740282 iDelay=208, Bit 6, Center 131 (56 ~ 207) 152
2664 00:44:43.740334 iDelay=208, Bit 7, Center 127 (56 ~ 199) 144
2665 00:44:43.740386 iDelay=208, Bit 8, Center 99 (32 ~ 167) 136
2666 00:44:43.740437 iDelay=208, Bit 9, Center 99 (32 ~ 167) 136
2667 00:44:43.740490 iDelay=208, Bit 10, Center 107 (40 ~ 175) 136
2668 00:44:43.740541 iDelay=208, Bit 11, Center 107 (40 ~ 175) 136
2669 00:44:43.740605 iDelay=208, Bit 12, Center 115 (48 ~ 183) 136
2670 00:44:43.740658 iDelay=208, Bit 13, Center 115 (48 ~ 183) 136
2671 00:44:43.740709 iDelay=208, Bit 14, Center 123 (56 ~ 191) 136
2672 00:44:43.740761 iDelay=208, Bit 15, Center 115 (48 ~ 183) 136
2673 00:44:43.740812 ==
2674 00:44:43.740865 Dram Type= 6, Freq= 0, CH_0, rank 0
2675 00:44:43.740950 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2676 00:44:43.741020 ==
2677 00:44:43.741073 DQS Delay:
2678 00:44:43.741125 DQS0 = 0, DQS1 = 0
2679 00:44:43.741177 DQM Delay:
2680 00:44:43.741229 DQM0 = 122, DQM1 = 110
2681 00:44:43.741280 DQ Delay:
2682 00:44:43.741332 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =119
2683 00:44:43.741384 DQ4 =127, DQ5 =115, DQ6 =131, DQ7 =127
2684 00:44:43.741436 DQ8 =99, DQ9 =99, DQ10 =107, DQ11 =107
2685 00:44:43.741488 DQ12 =115, DQ13 =115, DQ14 =123, DQ15 =115
2686 00:44:43.741539
2687 00:44:43.741590
2688 00:44:43.741641 ==
2689 00:44:43.741692 Dram Type= 6, Freq= 0, CH_0, rank 0
2690 00:44:43.741743 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2691 00:44:43.741796 ==
2692 00:44:43.741846
2693 00:44:43.741897
2694 00:44:43.741948 TX Vref Scan disable
2695 00:44:43.741999 == TX Byte 0 ==
2696 00:44:43.742069 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2697 00:44:43.742124 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2698 00:44:43.742177 == TX Byte 1 ==
2699 00:44:43.742229 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2700 00:44:43.742281 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2701 00:44:43.742332 ==
2702 00:44:43.742384 Dram Type= 6, Freq= 0, CH_0, rank 0
2703 00:44:43.742435 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2704 00:44:43.742488 ==
2705 00:44:43.742539 TX Vref=22, minBit 6, minWin=23, winSum=404
2706 00:44:43.742591 TX Vref=24, minBit 0, minWin=24, winSum=411
2707 00:44:43.742644 TX Vref=26, minBit 4, minWin=24, winSum=412
2708 00:44:43.742695 TX Vref=28, minBit 2, minWin=25, winSum=420
2709 00:44:43.742746 TX Vref=30, minBit 7, minWin=24, winSum=422
2710 00:44:43.742798 TX Vref=32, minBit 1, minWin=25, winSum=418
2711 00:44:43.742849 [TxChooseVref] Worse bit 2, Min win 25, Win sum 420, Final Vref 28
2712 00:44:43.742901
2713 00:44:43.742952 Final TX Range 1 Vref 28
2714 00:44:43.743003
2715 00:44:43.743054 ==
2716 00:44:43.743106 Dram Type= 6, Freq= 0, CH_0, rank 0
2717 00:44:43.743157 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2718 00:44:43.743209 ==
2719 00:44:43.743260
2720 00:44:43.743311
2721 00:44:43.743363 TX Vref Scan disable
2722 00:44:43.743414 == TX Byte 0 ==
2723 00:44:43.743465 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2724 00:44:43.743517 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2725 00:44:43.743569 == TX Byte 1 ==
2726 00:44:43.743620 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2727 00:44:43.743671 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2728 00:44:43.743722
2729 00:44:43.743773 [DATLAT]
2730 00:44:43.743824 Freq=1200, CH0 RK0
2731 00:44:43.743876
2732 00:44:43.743927 DATLAT Default: 0xd
2733 00:44:43.743978 0, 0xFFFF, sum = 0
2734 00:44:43.744031 1, 0xFFFF, sum = 0
2735 00:44:43.744083 2, 0xFFFF, sum = 0
2736 00:44:43.744135 3, 0xFFFF, sum = 0
2737 00:44:43.744188 4, 0xFFFF, sum = 0
2738 00:44:43.744239 5, 0xFFFF, sum = 0
2739 00:44:43.744291 6, 0xFFFF, sum = 0
2740 00:44:43.744344 7, 0xFFFF, sum = 0
2741 00:44:43.744396 8, 0xFFFF, sum = 0
2742 00:44:43.744448 9, 0xFFFF, sum = 0
2743 00:44:43.744500 10, 0xFFFF, sum = 0
2744 00:44:43.744559 11, 0xFFFF, sum = 0
2745 00:44:43.744613 12, 0x0, sum = 1
2746 00:44:43.744665 13, 0x0, sum = 2
2747 00:44:43.744718 14, 0x0, sum = 3
2748 00:44:43.744770 15, 0x0, sum = 4
2749 00:44:43.744822 best_step = 13
2750 00:44:43.744873
2751 00:44:43.744924 ==
2752 00:44:43.744975 Dram Type= 6, Freq= 0, CH_0, rank 0
2753 00:44:43.745026 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2754 00:44:43.745078 ==
2755 00:44:43.745129 RX Vref Scan: 1
2756 00:44:43.745181
2757 00:44:43.745246 Set Vref Range= 32 -> 127
2758 00:44:43.745330
2759 00:44:43.745416 RX Vref 32 -> 127, step: 1
2760 00:44:43.745476
2761 00:44:43.745528 RX Delay -13 -> 252, step: 4
2762 00:44:43.745580
2763 00:44:43.745631 Set Vref, RX VrefLevel [Byte0]: 32
2764 00:44:43.745684 [Byte1]: 32
2765 00:44:43.745735
2766 00:44:43.745787 Set Vref, RX VrefLevel [Byte0]: 33
2767 00:44:43.745840 [Byte1]: 33
2768 00:44:43.745891
2769 00:44:43.745942 Set Vref, RX VrefLevel [Byte0]: 34
2770 00:44:43.745993 [Byte1]: 34
2771 00:44:43.746045
2772 00:44:43.746096 Set Vref, RX VrefLevel [Byte0]: 35
2773 00:44:43.746147 [Byte1]: 35
2774 00:44:43.746199
2775 00:44:43.746250 Set Vref, RX VrefLevel [Byte0]: 36
2776 00:44:43.746302 [Byte1]: 36
2777 00:44:43.746353
2778 00:44:43.746404 Set Vref, RX VrefLevel [Byte0]: 37
2779 00:44:43.746455 [Byte1]: 37
2780 00:44:43.746506
2781 00:44:43.746557 Set Vref, RX VrefLevel [Byte0]: 38
2782 00:44:43.746609 [Byte1]: 38
2783 00:44:43.746660
2784 00:44:43.746711 Set Vref, RX VrefLevel [Byte0]: 39
2785 00:44:43.746762 [Byte1]: 39
2786 00:44:43.746813
2787 00:44:43.746864 Set Vref, RX VrefLevel [Byte0]: 40
2788 00:44:43.746915 [Byte1]: 40
2789 00:44:43.746966
2790 00:44:43.747017 Set Vref, RX VrefLevel [Byte0]: 41
2791 00:44:43.747068 [Byte1]: 41
2792 00:44:43.747119
2793 00:44:43.747169 Set Vref, RX VrefLevel [Byte0]: 42
2794 00:44:43.747221 [Byte1]: 42
2795 00:44:43.747272
2796 00:44:43.747323 Set Vref, RX VrefLevel [Byte0]: 43
2797 00:44:43.747374 [Byte1]: 43
2798 00:44:43.747425
2799 00:44:43.747476 Set Vref, RX VrefLevel [Byte0]: 44
2800 00:44:43.747527 [Byte1]: 44
2801 00:44:43.747578
2802 00:44:43.747629 Set Vref, RX VrefLevel [Byte0]: 45
2803 00:44:43.747680 [Byte1]: 45
2804 00:44:43.747731
2805 00:44:43.747782 Set Vref, RX VrefLevel [Byte0]: 46
2806 00:44:43.747833 [Byte1]: 46
2807 00:44:43.747884
2808 00:44:43.747935 Set Vref, RX VrefLevel [Byte0]: 47
2809 00:44:43.747987 [Byte1]: 47
2810 00:44:43.748038
2811 00:44:43.748089 Set Vref, RX VrefLevel [Byte0]: 48
2812 00:44:43.748140 [Byte1]: 48
2813 00:44:43.748192
2814 00:44:43.748243 Set Vref, RX VrefLevel [Byte0]: 49
2815 00:44:43.748294 [Byte1]: 49
2816 00:44:43.748346
2817 00:44:43.748397 Set Vref, RX VrefLevel [Byte0]: 50
2818 00:44:43.748679 [Byte1]: 50
2819 00:44:43.748743
2820 00:44:43.748796 Set Vref, RX VrefLevel [Byte0]: 51
2821 00:44:43.748848 [Byte1]: 51
2822 00:44:43.748900
2823 00:44:43.748952 Set Vref, RX VrefLevel [Byte0]: 52
2824 00:44:43.749003 [Byte1]: 52
2825 00:44:43.749055
2826 00:44:43.749105 Set Vref, RX VrefLevel [Byte0]: 53
2827 00:44:43.749157 [Byte1]: 53
2828 00:44:43.749209
2829 00:44:43.749260 Set Vref, RX VrefLevel [Byte0]: 54
2830 00:44:43.749312 [Byte1]: 54
2831 00:44:43.749363
2832 00:44:43.749414 Set Vref, RX VrefLevel [Byte0]: 55
2833 00:44:43.749466 [Byte1]: 55
2834 00:44:43.749517
2835 00:44:43.749568 Set Vref, RX VrefLevel [Byte0]: 56
2836 00:44:43.749619 [Byte1]: 56
2837 00:44:43.749671
2838 00:44:43.749722 Set Vref, RX VrefLevel [Byte0]: 57
2839 00:44:43.749773 [Byte1]: 57
2840 00:44:43.749824
2841 00:44:43.749875 Set Vref, RX VrefLevel [Byte0]: 58
2842 00:44:43.749926 [Byte1]: 58
2843 00:44:43.749978
2844 00:44:43.750029 Set Vref, RX VrefLevel [Byte0]: 59
2845 00:44:43.750080 [Byte1]: 59
2846 00:44:43.750131
2847 00:44:43.750182 Set Vref, RX VrefLevel [Byte0]: 60
2848 00:44:43.750233 [Byte1]: 60
2849 00:44:43.750285
2850 00:44:43.750336 Set Vref, RX VrefLevel [Byte0]: 61
2851 00:44:43.750388 [Byte1]: 61
2852 00:44:43.750439
2853 00:44:43.750491 Set Vref, RX VrefLevel [Byte0]: 62
2854 00:44:43.750542 [Byte1]: 62
2855 00:44:43.750594
2856 00:44:43.750644 Set Vref, RX VrefLevel [Byte0]: 63
2857 00:44:43.750696 [Byte1]: 63
2858 00:44:43.750747
2859 00:44:43.750797 Set Vref, RX VrefLevel [Byte0]: 64
2860 00:44:43.750848 [Byte1]: 64
2861 00:44:43.750899
2862 00:44:43.750950 Set Vref, RX VrefLevel [Byte0]: 65
2863 00:44:43.751001 [Byte1]: 65
2864 00:44:43.751052
2865 00:44:43.751103 Set Vref, RX VrefLevel [Byte0]: 66
2866 00:44:43.751154 [Byte1]: 66
2867 00:44:43.751205
2868 00:44:43.751257 Set Vref, RX VrefLevel [Byte0]: 67
2869 00:44:43.751308 [Byte1]: 67
2870 00:44:43.751359
2871 00:44:43.751410 Set Vref, RX VrefLevel [Byte0]: 68
2872 00:44:43.751462 [Byte1]: 68
2873 00:44:43.751513
2874 00:44:43.751564 Set Vref, RX VrefLevel [Byte0]: 69
2875 00:44:43.751615 [Byte1]: 69
2876 00:44:43.751667
2877 00:44:43.751717 Final RX Vref Byte 0 = 59 to rank0
2878 00:44:43.751769 Final RX Vref Byte 1 = 50 to rank0
2879 00:44:43.751821 Final RX Vref Byte 0 = 59 to rank1
2880 00:44:43.751872 Final RX Vref Byte 1 = 50 to rank1==
2881 00:44:43.751924 Dram Type= 6, Freq= 0, CH_0, rank 0
2882 00:44:43.751975 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2883 00:44:43.752028 ==
2884 00:44:43.752100 DQS Delay:
2885 00:44:43.752154 DQS0 = 0, DQS1 = 0
2886 00:44:43.752206 DQM Delay:
2887 00:44:43.752257 DQM0 = 122, DQM1 = 109
2888 00:44:43.752309 DQ Delay:
2889 00:44:43.752360 DQ0 =122, DQ1 =122, DQ2 =118, DQ3 =120
2890 00:44:43.752412 DQ4 =126, DQ5 =116, DQ6 =130, DQ7 =128
2891 00:44:43.752464 DQ8 =102, DQ9 =94, DQ10 =110, DQ11 =104
2892 00:44:43.752515 DQ12 =116, DQ13 =110, DQ14 =122, DQ15 =116
2893 00:44:43.752576
2894 00:44:43.752628
2895 00:44:43.752680 [DQSOSCAuto] RK0, (LSB)MR18= 0x100c, (MSB)MR19= 0x404, tDQSOscB0 = 405 ps tDQSOscB1 = 403 ps
2896 00:44:43.752733 CH0 RK0: MR19=404, MR18=100C
2897 00:44:43.752784 CH0_RK0: MR19=0x404, MR18=0x100C, DQSOSC=403, MR23=63, INC=40, DEC=26
2898 00:44:43.752836
2899 00:44:43.752887 ----->DramcWriteLeveling(PI) begin...
2900 00:44:43.752939 ==
2901 00:44:43.752991 Dram Type= 6, Freq= 0, CH_0, rank 1
2902 00:44:43.753042 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2903 00:44:43.753094 ==
2904 00:44:43.753146 Write leveling (Byte 0): 33 => 33
2905 00:44:43.753198 Write leveling (Byte 1): 30 => 30
2906 00:44:43.753249 DramcWriteLeveling(PI) end<-----
2907 00:44:43.753301
2908 00:44:43.753352 ==
2909 00:44:43.753403 Dram Type= 6, Freq= 0, CH_0, rank 1
2910 00:44:43.753454 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2911 00:44:43.753505 ==
2912 00:44:43.753556 [Gating] SW mode calibration
2913 00:44:43.753607 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2914 00:44:43.753660 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2915 00:44:43.753712 0 15 0 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
2916 00:44:43.753764 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2917 00:44:43.753816 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2918 00:44:43.753867 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2919 00:44:43.753919 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2920 00:44:43.753970 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2921 00:44:43.754022 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2922 00:44:43.754074 0 15 28 | B1->B0 | 3232 2b2b | 0 1 | (0 0) (1 0)
2923 00:44:43.754125 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2924 00:44:43.754177 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2925 00:44:43.754228 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2926 00:44:43.754280 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2927 00:44:43.754331 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2928 00:44:43.754382 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2929 00:44:43.754434 1 0 24 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
2930 00:44:43.754486 1 0 28 | B1->B0 | 3b3b 4444 | 0 0 | (0 0) (0 0)
2931 00:44:43.754537 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2932 00:44:43.754589 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2933 00:44:43.754640 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2934 00:44:43.754692 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2935 00:44:43.754743 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2936 00:44:43.754794 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2937 00:44:43.754846 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2938 00:44:43.754898 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2939 00:44:43.754949 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
2940 00:44:43.755000 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2941 00:44:43.755052 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2942 00:44:43.755307 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2943 00:44:43.755370 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2944 00:44:43.755424 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2945 00:44:43.755477 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2946 00:44:43.755528 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2947 00:44:43.755581 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2948 00:44:43.755633 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2949 00:44:43.755684 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2950 00:44:43.755737 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2951 00:44:43.755788 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2952 00:44:43.755840 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2953 00:44:43.755891 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2954 00:44:43.755943 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2955 00:44:43.755994 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
2956 00:44:43.756046 Total UI for P1: 0, mck2ui 16
2957 00:44:43.756098 best dqsien dly found for B1: ( 1, 3, 30)
2958 00:44:43.756149 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2959 00:44:43.756201 Total UI for P1: 0, mck2ui 16
2960 00:44:43.756253 best dqsien dly found for B0: ( 1, 3, 28)
2961 00:44:43.756304 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2962 00:44:43.756355 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2963 00:44:43.756405
2964 00:44:43.756457 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2965 00:44:43.756508 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2966 00:44:43.756585 [Gating] SW calibration Done
2967 00:44:43.756668 ==
2968 00:44:43.756739 Dram Type= 6, Freq= 0, CH_0, rank 1
2969 00:44:43.756793 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2970 00:44:43.756846 ==
2971 00:44:43.756898 RX Vref Scan: 0
2972 00:44:43.756949
2973 00:44:43.757001 RX Vref 0 -> 0, step: 1
2974 00:44:43.757053
2975 00:44:43.757104 RX Delay -40 -> 252, step: 8
2976 00:44:43.757155 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2977 00:44:43.757208 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2978 00:44:43.757260 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2979 00:44:43.757312 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2980 00:44:43.757363 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2981 00:44:43.757415 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2982 00:44:43.757466 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2983 00:44:43.757518 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2984 00:44:43.757569 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2985 00:44:43.757621 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2986 00:44:43.757672 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2987 00:44:43.757724 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2988 00:44:43.757775 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2989 00:44:43.757827 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2990 00:44:43.757878 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2991 00:44:43.757930 iDelay=200, Bit 15, Center 111 (48 ~ 175) 128
2992 00:44:43.757981 ==
2993 00:44:43.758033 Dram Type= 6, Freq= 0, CH_0, rank 1
2994 00:44:43.758085 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2995 00:44:43.758137 ==
2996 00:44:43.758189 DQS Delay:
2997 00:44:43.758240 DQS0 = 0, DQS1 = 0
2998 00:44:43.758292 DQM Delay:
2999 00:44:43.758351 DQM0 = 120, DQM1 = 108
3000 00:44:43.758412 DQ Delay:
3001 00:44:43.758464 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =115
3002 00:44:43.758516 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
3003 00:44:43.758568 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =107
3004 00:44:43.895479 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =111
3005 00:44:43.896002
3006 00:44:43.896357
3007 00:44:43.896717 ==
3008 00:44:43.897041 Dram Type= 6, Freq= 0, CH_0, rank 1
3009 00:44:43.897354 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3010 00:44:43.897667 ==
3011 00:44:43.897975
3012 00:44:43.898271
3013 00:44:43.898569 TX Vref Scan disable
3014 00:44:43.898867 == TX Byte 0 ==
3015 00:44:43.899162 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
3016 00:44:43.899458 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
3017 00:44:43.899753 == TX Byte 1 ==
3018 00:44:43.900048 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3019 00:44:43.900346 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3020 00:44:43.900680 ==
3021 00:44:43.900984 Dram Type= 6, Freq= 0, CH_0, rank 1
3022 00:44:43.901283 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3023 00:44:43.901582 ==
3024 00:44:43.901876 TX Vref=22, minBit 0, minWin=25, winSum=414
3025 00:44:43.902172 TX Vref=24, minBit 0, minWin=25, winSum=421
3026 00:44:43.902471 TX Vref=26, minBit 0, minWin=25, winSum=422
3027 00:44:43.902768 TX Vref=28, minBit 7, minWin=25, winSum=426
3028 00:44:43.903065 TX Vref=30, minBit 3, minWin=25, winSum=429
3029 00:44:43.903357 TX Vref=32, minBit 1, minWin=25, winSum=423
3030 00:44:43.903653 [TxChooseVref] Worse bit 3, Min win 25, Win sum 429, Final Vref 30
3031 00:44:43.903954
3032 00:44:43.904245 Final TX Range 1 Vref 30
3033 00:44:43.904537
3034 00:44:43.904871 ==
3035 00:44:43.905164 Dram Type= 6, Freq= 0, CH_0, rank 1
3036 00:44:43.905459 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3037 00:44:43.905754 ==
3038 00:44:43.906045
3039 00:44:43.906335
3040 00:44:43.906625 TX Vref Scan disable
3041 00:44:43.906914 == TX Byte 0 ==
3042 00:44:43.907205 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
3043 00:44:43.907500 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
3044 00:44:43.907795 == TX Byte 1 ==
3045 00:44:43.908087 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3046 00:44:43.908379 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3047 00:44:43.908717
3048 00:44:43.909010 [DATLAT]
3049 00:44:43.909299 Freq=1200, CH0 RK1
3050 00:44:43.909590
3051 00:44:43.909879 DATLAT Default: 0xd
3052 00:44:43.910170 0, 0xFFFF, sum = 0
3053 00:44:43.910471 1, 0xFFFF, sum = 0
3054 00:44:43.910772 2, 0xFFFF, sum = 0
3055 00:44:43.911073 3, 0xFFFF, sum = 0
3056 00:44:43.911373 4, 0xFFFF, sum = 0
3057 00:44:43.911670 5, 0xFFFF, sum = 0
3058 00:44:43.911961 6, 0xFFFF, sum = 0
3059 00:44:43.912353 7, 0xFFFF, sum = 0
3060 00:44:43.912696 8, 0xFFFF, sum = 0
3061 00:44:43.913000 9, 0xFFFF, sum = 0
3062 00:44:43.913295 10, 0xFFFF, sum = 0
3063 00:44:43.913594 11, 0xFFFF, sum = 0
3064 00:44:43.913980 12, 0x0, sum = 1
3065 00:44:43.914289 13, 0x0, sum = 2
3066 00:44:43.914587 14, 0x0, sum = 3
3067 00:44:43.914888 15, 0x0, sum = 4
3068 00:44:43.915182 best_step = 13
3069 00:44:43.915471
3070 00:44:43.915765 ==
3071 00:44:43.916058 Dram Type= 6, Freq= 0, CH_0, rank 1
3072 00:44:43.916350 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3073 00:44:43.916668 ==
3074 00:44:43.916966 RX Vref Scan: 0
3075 00:44:43.917262
3076 00:44:43.917554 RX Vref 0 -> 0, step: 1
3077 00:44:43.917847
3078 00:44:43.918135 RX Delay -21 -> 252, step: 4
3079 00:44:43.918429 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3080 00:44:43.919141 iDelay=195, Bit 1, Center 122 (55 ~ 190) 136
3081 00:44:43.919476 iDelay=195, Bit 2, Center 116 (51 ~ 182) 132
3082 00:44:43.919779 iDelay=195, Bit 3, Center 112 (47 ~ 178) 132
3083 00:44:43.920077 iDelay=195, Bit 4, Center 118 (51 ~ 186) 136
3084 00:44:43.920375 iDelay=195, Bit 5, Center 114 (51 ~ 178) 128
3085 00:44:43.920697 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3086 00:44:43.920995 iDelay=195, Bit 7, Center 124 (55 ~ 194) 140
3087 00:44:43.921289 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3088 00:44:43.921583 iDelay=195, Bit 9, Center 96 (31 ~ 162) 132
3089 00:44:43.921872 iDelay=195, Bit 10, Center 108 (47 ~ 170) 124
3090 00:44:43.922164 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3091 00:44:43.922455 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
3092 00:44:43.922745 iDelay=195, Bit 13, Center 112 (51 ~ 174) 124
3093 00:44:43.923036 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3094 00:44:43.923317 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
3095 00:44:43.923522 ==
3096 00:44:43.923728 Dram Type= 6, Freq= 0, CH_0, rank 1
3097 00:44:43.923936 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3098 00:44:43.924142 ==
3099 00:44:43.924350 DQS Delay:
3100 00:44:43.924565 DQS0 = 0, DQS1 = 0
3101 00:44:43.924774 DQM Delay:
3102 00:44:43.924978 DQM0 = 118, DQM1 = 108
3103 00:44:43.925182 DQ Delay:
3104 00:44:43.925388 DQ0 =118, DQ1 =122, DQ2 =116, DQ3 =112
3105 00:44:43.925594 DQ4 =118, DQ5 =114, DQ6 =126, DQ7 =124
3106 00:44:43.925801 DQ8 =98, DQ9 =96, DQ10 =108, DQ11 =106
3107 00:44:43.926004 DQ12 =114, DQ13 =112, DQ14 =118, DQ15 =114
3108 00:44:43.926209
3109 00:44:43.926414
3110 00:44:43.926619 [DQSOSCAuto] RK1, (LSB)MR18= 0xff6, (MSB)MR19= 0x403, tDQSOscB0 = 414 ps tDQSOscB1 = 404 ps
3111 00:44:43.926828 CH0 RK1: MR19=403, MR18=FF6
3112 00:44:43.927035 CH0_RK1: MR19=0x403, MR18=0xFF6, DQSOSC=404, MR23=63, INC=40, DEC=26
3113 00:44:43.927247 [RxdqsGatingPostProcess] freq 1200
3114 00:44:43.927462 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3115 00:44:43.927676 best DQS0 dly(2T, 0.5T) = (0, 11)
3116 00:44:43.927890 best DQS1 dly(2T, 0.5T) = (0, 12)
3117 00:44:43.928102 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3118 00:44:43.928307 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3119 00:44:43.928463 best DQS0 dly(2T, 0.5T) = (0, 11)
3120 00:44:43.928631 best DQS1 dly(2T, 0.5T) = (0, 11)
3121 00:44:43.928790 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3122 00:44:43.928946 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3123 00:44:43.929101 Pre-setting of DQS Precalculation
3124 00:44:43.929258 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3125 00:44:43.929416 ==
3126 00:44:43.929574 Dram Type= 6, Freq= 0, CH_1, rank 0
3127 00:44:43.929733 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3128 00:44:43.929891 ==
3129 00:44:43.930050 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3130 00:44:43.930208 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3131 00:44:43.930366 [CA 0] Center 37 (7~68) winsize 62
3132 00:44:43.930523 [CA 1] Center 37 (7~68) winsize 62
3133 00:44:43.930681 [CA 2] Center 35 (5~65) winsize 61
3134 00:44:43.930837 [CA 3] Center 34 (4~65) winsize 62
3135 00:44:43.930994 [CA 4] Center 34 (4~64) winsize 61
3136 00:44:43.931150 [CA 5] Center 33 (3~64) winsize 62
3137 00:44:43.931307
3138 00:44:43.931463 [CmdBusTrainingLP45] Vref(ca) range 1: 31
3139 00:44:43.931622
3140 00:44:43.931776 [CATrainingPosCal] consider 1 rank data
3141 00:44:43.931933 u2DelayCellTimex100 = 270/100 ps
3142 00:44:43.932090 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3143 00:44:43.932247 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3144 00:44:43.932404 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3145 00:44:43.932576 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3146 00:44:43.932736 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3147 00:44:43.932893 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3148 00:44:43.933049
3149 00:44:43.933204 CA PerBit enable=1, Macro0, CA PI delay=33
3150 00:44:43.933348
3151 00:44:43.933470 [CBTSetCACLKResult] CA Dly = 33
3152 00:44:43.933595 CS Dly: 5 (0~36)
3153 00:44:43.933718 ==
3154 00:44:43.933842 Dram Type= 6, Freq= 0, CH_1, rank 1
3155 00:44:43.933967 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3156 00:44:43.934092 ==
3157 00:44:43.934215 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3158 00:44:43.934340 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3159 00:44:43.934465 [CA 0] Center 38 (8~69) winsize 62
3160 00:44:43.934589 [CA 1] Center 38 (7~69) winsize 63
3161 00:44:43.934713 [CA 2] Center 35 (5~66) winsize 62
3162 00:44:43.934835 [CA 3] Center 35 (5~65) winsize 61
3163 00:44:43.934959 [CA 4] Center 34 (4~64) winsize 61
3164 00:44:43.935084 [CA 5] Center 34 (4~64) winsize 61
3165 00:44:43.935208
3166 00:44:43.935331 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3167 00:44:43.935456
3168 00:44:43.935578 [CATrainingPosCal] consider 2 rank data
3169 00:44:43.935703 u2DelayCellTimex100 = 270/100 ps
3170 00:44:43.935827 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3171 00:44:43.935952 CA1 delay=37 (7~68),Diff = 3 PI (14 cell)
3172 00:44:43.936075 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3173 00:44:43.936199 CA3 delay=35 (5~65),Diff = 1 PI (4 cell)
3174 00:44:43.936323 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
3175 00:44:43.936447 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3176 00:44:43.936577
3177 00:44:43.936703 CA PerBit enable=1, Macro0, CA PI delay=34
3178 00:44:43.936828
3179 00:44:43.936951 [CBTSetCACLKResult] CA Dly = 34
3180 00:44:43.937075 CS Dly: 6 (0~39)
3181 00:44:43.937198
3182 00:44:43.937321 ----->DramcWriteLeveling(PI) begin...
3183 00:44:43.937446 ==
3184 00:44:43.937571 Dram Type= 6, Freq= 0, CH_1, rank 0
3185 00:44:43.937695 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3186 00:44:43.937820 ==
3187 00:44:43.937944 Write leveling (Byte 0): 25 => 25
3188 00:44:43.938068 Write leveling (Byte 1): 27 => 27
3189 00:44:43.938192 DramcWriteLeveling(PI) end<-----
3190 00:44:43.938316
3191 00:44:43.938416 ==
3192 00:44:43.938518 Dram Type= 6, Freq= 0, CH_1, rank 0
3193 00:44:43.938622 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3194 00:44:43.938726 ==
3195 00:44:43.938830 [Gating] SW mode calibration
3196 00:44:43.938934 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3197 00:44:43.939039 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3198 00:44:43.939143 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3199 00:44:43.939478 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3200 00:44:43.939595 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3201 00:44:43.939701 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3202 00:44:43.939805 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3203 00:44:43.939908 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3204 00:44:43.940012 0 15 24 | B1->B0 | 2a2a 2525 | 1 0 | (1 0) (1 0)
3205 00:44:43.940116 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3206 00:44:43.940220 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3207 00:44:43.940323 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3208 00:44:43.940426 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3209 00:44:43.940529 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3210 00:44:43.940642 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3211 00:44:43.940745 1 0 20 | B1->B0 | 2525 2c2c | 0 0 | (0 0) (0 0)
3212 00:44:43.940847 1 0 24 | B1->B0 | 3737 4343 | 0 0 | (0 0) (0 0)
3213 00:44:43.940950 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3214 00:44:43.941054 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3215 00:44:43.941156 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3216 00:44:43.941259 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3217 00:44:43.941361 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3218 00:44:43.941464 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3219 00:44:43.941567 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3220 00:44:43.941670 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3221 00:44:43.941773 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3222 00:44:43.941878 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3223 00:44:43.941981 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3224 00:44:43.942084 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3225 00:44:43.942188 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3226 00:44:43.942291 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3227 00:44:43.942394 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3228 00:44:43.942497 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3229 00:44:43.942600 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3230 00:44:43.942703 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3231 00:44:43.942806 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3232 00:44:43.942909 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3233 00:44:43.943013 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3234 00:44:43.943116 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3235 00:44:43.943231 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3236 00:44:43.943319 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3237 00:44:43.943407 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3238 00:44:43.943495 Total UI for P1: 0, mck2ui 16
3239 00:44:43.943584 best dqsien dly found for B0: ( 1, 3, 22)
3240 00:44:43.943673 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3241 00:44:43.943761 Total UI for P1: 0, mck2ui 16
3242 00:44:43.943849 best dqsien dly found for B1: ( 1, 3, 24)
3243 00:44:43.943937 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3244 00:44:43.944025 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3245 00:44:43.944113
3246 00:44:43.944200 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3247 00:44:43.944291 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3248 00:44:43.944378 [Gating] SW calibration Done
3249 00:44:43.944465 ==
3250 00:44:43.944587 Dram Type= 6, Freq= 0, CH_1, rank 0
3251 00:44:43.944679 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3252 00:44:43.944769 ==
3253 00:44:43.944857 RX Vref Scan: 0
3254 00:44:43.944945
3255 00:44:43.945032 RX Vref 0 -> 0, step: 1
3256 00:44:43.945121
3257 00:44:43.945207 RX Delay -40 -> 252, step: 8
3258 00:44:43.945295 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3259 00:44:43.945383 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3260 00:44:43.945471 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3261 00:44:43.945558 iDelay=200, Bit 3, Center 123 (56 ~ 191) 136
3262 00:44:43.945646 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3263 00:44:43.945735 iDelay=200, Bit 5, Center 127 (64 ~ 191) 128
3264 00:44:43.945824 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3265 00:44:43.945914 iDelay=200, Bit 7, Center 119 (56 ~ 183) 128
3266 00:44:43.946001 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3267 00:44:43.946088 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3268 00:44:43.946175 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3269 00:44:43.946263 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3270 00:44:43.946351 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3271 00:44:43.946439 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
3272 00:44:43.946527 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3273 00:44:43.946614 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3274 00:44:43.946701 ==
3275 00:44:43.946789 Dram Type= 6, Freq= 0, CH_1, rank 0
3276 00:44:43.946877 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3277 00:44:43.946966 ==
3278 00:44:43.947054 DQS Delay:
3279 00:44:43.947141 DQS0 = 0, DQS1 = 0
3280 00:44:43.947229 DQM Delay:
3281 00:44:43.947317 DQM0 = 120, DQM1 = 113
3282 00:44:43.947403 DQ Delay:
3283 00:44:43.947492 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =123
3284 00:44:43.947581 DQ4 =115, DQ5 =127, DQ6 =131, DQ7 =119
3285 00:44:43.947669 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3286 00:44:43.947757 DQ12 =123, DQ13 =123, DQ14 =119, DQ15 =119
3287 00:44:43.947844
3288 00:44:43.947931
3289 00:44:43.948017 ==
3290 00:44:43.948105 Dram Type= 6, Freq= 0, CH_1, rank 0
3291 00:44:43.948192 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3292 00:44:43.948286 ==
3293 00:44:43.948362
3294 00:44:43.948439
3295 00:44:43.948515 TX Vref Scan disable
3296 00:44:43.948598 == TX Byte 0 ==
3297 00:44:43.948675 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3298 00:44:43.948752 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3299 00:44:43.948829 == TX Byte 1 ==
3300 00:44:43.948905 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3301 00:44:43.948982 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3302 00:44:43.949058 ==
3303 00:44:43.949135 Dram Type= 6, Freq= 0, CH_1, rank 0
3304 00:44:43.949211 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3305 00:44:43.949289 ==
3306 00:44:43.949574 TX Vref=22, minBit 10, minWin=24, winSum=405
3307 00:44:43.949662 TX Vref=24, minBit 10, minWin=24, winSum=409
3308 00:44:43.949742 TX Vref=26, minBit 3, minWin=25, winSum=414
3309 00:44:43.949820 TX Vref=28, minBit 8, minWin=25, winSum=417
3310 00:44:43.949898 TX Vref=30, minBit 9, minWin=25, winSum=421
3311 00:44:43.949975 TX Vref=32, minBit 9, minWin=25, winSum=419
3312 00:44:43.950053 [TxChooseVref] Worse bit 9, Min win 25, Win sum 421, Final Vref 30
3313 00:44:43.950131
3314 00:44:43.950208 Final TX Range 1 Vref 30
3315 00:44:43.950285
3316 00:44:43.950362 ==
3317 00:44:43.950440 Dram Type= 6, Freq= 0, CH_1, rank 0
3318 00:44:43.950517 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3319 00:44:43.950594 ==
3320 00:44:43.950671
3321 00:44:43.950747
3322 00:44:43.950823 TX Vref Scan disable
3323 00:44:43.950900 == TX Byte 0 ==
3324 00:44:43.950976 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3325 00:44:43.951055 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3326 00:44:43.951132 == TX Byte 1 ==
3327 00:44:43.951209 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3328 00:44:43.951286 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3329 00:44:43.951364
3330 00:44:43.951441 [DATLAT]
3331 00:44:43.951517 Freq=1200, CH1 RK0
3332 00:44:43.951594
3333 00:44:43.951669 DATLAT Default: 0xd
3334 00:44:43.951747 0, 0xFFFF, sum = 0
3335 00:44:43.951826 1, 0xFFFF, sum = 0
3336 00:44:43.951904 2, 0xFFFF, sum = 0
3337 00:44:43.951982 3, 0xFFFF, sum = 0
3338 00:44:43.952061 4, 0xFFFF, sum = 0
3339 00:44:43.952138 5, 0xFFFF, sum = 0
3340 00:44:43.952216 6, 0xFFFF, sum = 0
3341 00:44:43.952293 7, 0xFFFF, sum = 0
3342 00:44:43.952371 8, 0xFFFF, sum = 0
3343 00:44:43.952449 9, 0xFFFF, sum = 0
3344 00:44:43.952527 10, 0xFFFF, sum = 0
3345 00:44:43.952620 11, 0xFFFF, sum = 0
3346 00:44:43.952699 12, 0x0, sum = 1
3347 00:44:43.952777 13, 0x0, sum = 2
3348 00:44:43.952855 14, 0x0, sum = 3
3349 00:44:43.952934 15, 0x0, sum = 4
3350 00:44:43.953012 best_step = 13
3351 00:44:43.953088
3352 00:44:43.953164 ==
3353 00:44:43.953251 Dram Type= 6, Freq= 0, CH_1, rank 0
3354 00:44:43.953321 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3355 00:44:43.953390 ==
3356 00:44:43.953458 RX Vref Scan: 1
3357 00:44:43.953525
3358 00:44:43.953592 Set Vref Range= 32 -> 127
3359 00:44:43.953661
3360 00:44:43.953728 RX Vref 32 -> 127, step: 1
3361 00:44:43.953795
3362 00:44:43.953862 RX Delay -13 -> 252, step: 4
3363 00:44:43.953927
3364 00:44:43.953993 Set Vref, RX VrefLevel [Byte0]: 32
3365 00:44:43.954060 [Byte1]: 32
3366 00:44:43.954126
3367 00:44:43.954191 Set Vref, RX VrefLevel [Byte0]: 33
3368 00:44:43.954257 [Byte1]: 33
3369 00:44:43.954322
3370 00:44:43.954388 Set Vref, RX VrefLevel [Byte0]: 34
3371 00:44:43.954454 [Byte1]: 34
3372 00:44:43.954519
3373 00:44:43.954584 Set Vref, RX VrefLevel [Byte0]: 35
3374 00:44:43.954650 [Byte1]: 35
3375 00:44:43.954717
3376 00:44:43.954782 Set Vref, RX VrefLevel [Byte0]: 36
3377 00:44:43.954848 [Byte1]: 36
3378 00:44:43.954913
3379 00:44:43.954979 Set Vref, RX VrefLevel [Byte0]: 37
3380 00:44:43.955045 [Byte1]: 37
3381 00:44:43.955110
3382 00:44:43.955175 Set Vref, RX VrefLevel [Byte0]: 38
3383 00:44:43.955241 [Byte1]: 38
3384 00:44:43.955306
3385 00:44:43.955373 Set Vref, RX VrefLevel [Byte0]: 39
3386 00:44:43.955439 [Byte1]: 39
3387 00:44:43.955504
3388 00:44:43.955570 Set Vref, RX VrefLevel [Byte0]: 40
3389 00:44:43.955635 [Byte1]: 40
3390 00:44:43.955701
3391 00:44:43.955766 Set Vref, RX VrefLevel [Byte0]: 41
3392 00:44:43.955831 [Byte1]: 41
3393 00:44:43.955897
3394 00:44:43.955962 Set Vref, RX VrefLevel [Byte0]: 42
3395 00:44:43.956027 [Byte1]: 42
3396 00:44:43.956093
3397 00:44:43.956159 Set Vref, RX VrefLevel [Byte0]: 43
3398 00:44:43.956226 [Byte1]: 43
3399 00:44:43.956291
3400 00:44:43.956356 Set Vref, RX VrefLevel [Byte0]: 44
3401 00:44:43.956422 [Byte1]: 44
3402 00:44:43.956488
3403 00:44:43.956557 Set Vref, RX VrefLevel [Byte0]: 45
3404 00:44:43.956626 [Byte1]: 45
3405 00:44:43.956693
3406 00:44:43.956758 Set Vref, RX VrefLevel [Byte0]: 46
3407 00:44:43.956824 [Byte1]: 46
3408 00:44:43.956889
3409 00:44:43.956954 Set Vref, RX VrefLevel [Byte0]: 47
3410 00:44:43.957020 [Byte1]: 47
3411 00:44:43.957086
3412 00:44:43.957151 Set Vref, RX VrefLevel [Byte0]: 48
3413 00:44:43.957217 [Byte1]: 48
3414 00:44:43.957283
3415 00:44:43.957348 Set Vref, RX VrefLevel [Byte0]: 49
3416 00:44:43.957414 [Byte1]: 49
3417 00:44:43.957479
3418 00:44:43.957544 Set Vref, RX VrefLevel [Byte0]: 50
3419 00:44:43.957609 [Byte1]: 50
3420 00:44:43.957675
3421 00:44:43.957740 Set Vref, RX VrefLevel [Byte0]: 51
3422 00:44:43.957806 [Byte1]: 51
3423 00:44:43.957872
3424 00:44:43.957937 Set Vref, RX VrefLevel [Byte0]: 52
3425 00:44:43.958004 [Byte1]: 52
3426 00:44:43.958069
3427 00:44:43.958135 Set Vref, RX VrefLevel [Byte0]: 53
3428 00:44:43.958201 [Byte1]: 53
3429 00:44:43.958278
3430 00:44:43.958337 Set Vref, RX VrefLevel [Byte0]: 54
3431 00:44:43.958396 [Byte1]: 54
3432 00:44:43.958455
3433 00:44:43.958514 Set Vref, RX VrefLevel [Byte0]: 55
3434 00:44:43.958572 [Byte1]: 55
3435 00:44:43.958632
3436 00:44:43.958691 Set Vref, RX VrefLevel [Byte0]: 56
3437 00:44:43.958750 [Byte1]: 56
3438 00:44:43.958809
3439 00:44:43.958868 Set Vref, RX VrefLevel [Byte0]: 57
3440 00:44:43.958927 [Byte1]: 57
3441 00:44:43.958986
3442 00:44:43.959045 Set Vref, RX VrefLevel [Byte0]: 58
3443 00:44:43.959103 [Byte1]: 58
3444 00:44:43.959163
3445 00:44:43.959222 Set Vref, RX VrefLevel [Byte0]: 59
3446 00:44:43.959282 [Byte1]: 59
3447 00:44:43.959342
3448 00:44:43.959401 Set Vref, RX VrefLevel [Byte0]: 60
3449 00:44:43.959460 [Byte1]: 60
3450 00:44:43.959518
3451 00:44:43.959577 Set Vref, RX VrefLevel [Byte0]: 61
3452 00:44:43.959635 [Byte1]: 61
3453 00:44:43.959694
3454 00:44:43.959753 Set Vref, RX VrefLevel [Byte0]: 62
3455 00:44:43.959813 [Byte1]: 62
3456 00:44:43.959872
3457 00:44:43.959931 Set Vref, RX VrefLevel [Byte0]: 63
3458 00:44:43.959991 [Byte1]: 63
3459 00:44:43.960049
3460 00:44:43.960108 Set Vref, RX VrefLevel [Byte0]: 64
3461 00:44:43.960167 [Byte1]: 64
3462 00:44:43.960225
3463 00:44:43.960283 Set Vref, RX VrefLevel [Byte0]: 65
3464 00:44:43.960343 [Byte1]: 65
3465 00:44:43.960402
3466 00:44:43.960461 Set Vref, RX VrefLevel [Byte0]: 66
3467 00:44:43.960520 [Byte1]: 66
3468 00:44:43.960584
3469 00:44:43.960643 Set Vref, RX VrefLevel [Byte0]: 67
3470 00:44:43.960702 [Byte1]: 67
3471 00:44:43.960761
3472 00:44:43.960820 Final RX Vref Byte 0 = 51 to rank0
3473 00:44:43.961080 Final RX Vref Byte 1 = 59 to rank0
3474 00:44:43.961150 Final RX Vref Byte 0 = 51 to rank1
3475 00:44:43.961211 Final RX Vref Byte 1 = 59 to rank1==
3476 00:44:43.961272 Dram Type= 6, Freq= 0, CH_1, rank 0
3477 00:44:43.961332 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3478 00:44:43.961392 ==
3479 00:44:43.961452 DQS Delay:
3480 00:44:43.961512 DQS0 = 0, DQS1 = 0
3481 00:44:43.961572 DQM Delay:
3482 00:44:43.961631 DQM0 = 118, DQM1 = 113
3483 00:44:43.961691 DQ Delay:
3484 00:44:43.961751 DQ0 =120, DQ1 =112, DQ2 =112, DQ3 =116
3485 00:44:43.961810 DQ4 =118, DQ5 =128, DQ6 =128, DQ7 =116
3486 00:44:43.961870 DQ8 =102, DQ9 =100, DQ10 =118, DQ11 =106
3487 00:44:43.961931 DQ12 =122, DQ13 =118, DQ14 =120, DQ15 =122
3488 00:44:43.961991
3489 00:44:43.962049
3490 00:44:43.962108 [DQSOSCAuto] RK0, (LSB)MR18= 0x115, (MSB)MR19= 0x404, tDQSOscB0 = 401 ps tDQSOscB1 = 409 ps
3491 00:44:43.962169 CH1 RK0: MR19=404, MR18=115
3492 00:44:43.962229 CH1_RK0: MR19=0x404, MR18=0x115, DQSOSC=401, MR23=63, INC=40, DEC=27
3493 00:44:43.962289
3494 00:44:43.962347 ----->DramcWriteLeveling(PI) begin...
3495 00:44:43.962408 ==
3496 00:44:43.962467 Dram Type= 6, Freq= 0, CH_1, rank 1
3497 00:44:43.962527 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3498 00:44:43.962586 ==
3499 00:44:43.962645 Write leveling (Byte 0): 26 => 26
3500 00:44:43.962705 Write leveling (Byte 1): 27 => 27
3501 00:44:43.962764 DramcWriteLeveling(PI) end<-----
3502 00:44:43.962823
3503 00:44:43.962882 ==
3504 00:44:43.962942 Dram Type= 6, Freq= 0, CH_1, rank 1
3505 00:44:43.963001 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3506 00:44:43.963061 ==
3507 00:44:43.963120 [Gating] SW mode calibration
3508 00:44:43.963180 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3509 00:44:43.963252 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3510 00:44:43.963307 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3511 00:44:43.963361 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3512 00:44:43.963415 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3513 00:44:43.963469 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3514 00:44:43.963523 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3515 00:44:43.963577 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3516 00:44:43.963631 0 15 24 | B1->B0 | 2b2b 3434 | 0 1 | (0 0) (1 0)
3517 00:44:43.963684 0 15 28 | B1->B0 | 2323 2828 | 0 0 | (0 0) (1 0)
3518 00:44:43.963738 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3519 00:44:43.963792 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3520 00:44:43.963846 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3521 00:44:43.963899 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3522 00:44:43.963953 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3523 00:44:43.964006 1 0 20 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
3524 00:44:43.964060 1 0 24 | B1->B0 | 4040 3030 | 0 0 | (0 0) (0 0)
3525 00:44:43.964114 1 0 28 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
3526 00:44:43.964168 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3527 00:44:43.964222 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3528 00:44:43.964276 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3529 00:44:43.964330 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3530 00:44:43.964385 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3531 00:44:43.964438 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3532 00:44:43.964492 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3533 00:44:43.964550 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3534 00:44:43.964606 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3535 00:44:43.964661 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3536 00:44:43.964715 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3537 00:44:43.964769 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3538 00:44:43.964822 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3539 00:44:43.964877 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3540 00:44:43.964934 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3541 00:44:43.964989 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3542 00:44:43.965042 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3543 00:44:43.965096 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3544 00:44:43.965150 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3545 00:44:43.965204 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3546 00:44:43.965257 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3547 00:44:43.965311 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3548 00:44:43.965365 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3549 00:44:43.965418 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3550 00:44:43.965472 Total UI for P1: 0, mck2ui 16
3551 00:44:43.965527 best dqsien dly found for B1: ( 1, 3, 24)
3552 00:44:43.965581 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3553 00:44:43.965635 Total UI for P1: 0, mck2ui 16
3554 00:44:43.965690 best dqsien dly found for B0: ( 1, 3, 24)
3555 00:44:43.965744 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3556 00:44:43.965798 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3557 00:44:43.965852
3558 00:44:43.965906 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3559 00:44:43.965960 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3560 00:44:43.966015 [Gating] SW calibration Done
3561 00:44:43.966068 ==
3562 00:44:43.966122 Dram Type= 6, Freq= 0, CH_1, rank 1
3563 00:44:43.966176 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3564 00:44:43.966230 ==
3565 00:44:43.966284 RX Vref Scan: 0
3566 00:44:43.966338
3567 00:44:43.966391 RX Vref 0 -> 0, step: 1
3568 00:44:43.966445
3569 00:44:43.966498 RX Delay -40 -> 252, step: 8
3570 00:44:43.966552 iDelay=200, Bit 0, Center 123 (64 ~ 183) 120
3571 00:44:43.966606 iDelay=200, Bit 1, Center 111 (48 ~ 175) 128
3572 00:44:43.966660 iDelay=200, Bit 2, Center 111 (48 ~ 175) 128
3573 00:44:43.966714 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3574 00:44:43.966768 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
3575 00:44:43.966822 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3576 00:44:43.966876 iDelay=200, Bit 6, Center 127 (64 ~ 191) 128
3577 00:44:43.967120 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3578 00:44:43.967181 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3579 00:44:43.967236 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3580 00:44:43.967291 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3581 00:44:43.967345 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3582 00:44:43.967399 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3583 00:44:43.967453 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3584 00:44:43.967507 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3585 00:44:43.967561 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3586 00:44:43.967615 ==
3587 00:44:43.967669 Dram Type= 6, Freq= 0, CH_1, rank 1
3588 00:44:43.967723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3589 00:44:43.967778 ==
3590 00:44:43.967832 DQS Delay:
3591 00:44:43.967886 DQS0 = 0, DQS1 = 0
3592 00:44:43.967940 DQM Delay:
3593 00:44:43.967994 DQM0 = 120, DQM1 = 112
3594 00:44:43.968048 DQ Delay:
3595 00:44:43.968101 DQ0 =123, DQ1 =111, DQ2 =111, DQ3 =119
3596 00:44:43.968156 DQ4 =123, DQ5 =131, DQ6 =127, DQ7 =115
3597 00:44:43.968210 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3598 00:44:43.968265 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =119
3599 00:44:43.968330
3600 00:44:43.968380
3601 00:44:43.968431 ==
3602 00:44:43.968483 Dram Type= 6, Freq= 0, CH_1, rank 1
3603 00:44:43.968534 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3604 00:44:43.968616 ==
3605 00:44:43.968682
3606 00:44:43.968732
3607 00:44:43.968784 TX Vref Scan disable
3608 00:44:43.968835 == TX Byte 0 ==
3609 00:44:43.968886 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3610 00:44:43.968938 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3611 00:44:43.968990 == TX Byte 1 ==
3612 00:44:43.969041 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3613 00:44:43.969093 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3614 00:44:43.969145 ==
3615 00:44:43.969197 Dram Type= 6, Freq= 0, CH_1, rank 1
3616 00:44:43.969248 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3617 00:44:43.969300 ==
3618 00:44:43.969351 TX Vref=22, minBit 1, minWin=25, winSum=416
3619 00:44:43.969404 TX Vref=24, minBit 8, minWin=25, winSum=418
3620 00:44:43.969456 TX Vref=26, minBit 9, minWin=25, winSum=424
3621 00:44:43.969507 TX Vref=28, minBit 4, minWin=26, winSum=428
3622 00:44:43.969559 TX Vref=30, minBit 8, minWin=26, winSum=430
3623 00:44:43.969611 TX Vref=32, minBit 7, minWin=26, winSum=426
3624 00:44:43.969663 [TxChooseVref] Worse bit 8, Min win 26, Win sum 430, Final Vref 30
3625 00:44:43.969715
3626 00:44:43.969766 Final TX Range 1 Vref 30
3627 00:44:43.969818
3628 00:44:43.969868 ==
3629 00:44:43.969919 Dram Type= 6, Freq= 0, CH_1, rank 1
3630 00:44:43.969971 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3631 00:44:43.970022 ==
3632 00:44:43.970074
3633 00:44:43.970124
3634 00:44:43.970175 TX Vref Scan disable
3635 00:44:43.970226 == TX Byte 0 ==
3636 00:44:43.970277 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3637 00:44:43.970329 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3638 00:44:43.970380 == TX Byte 1 ==
3639 00:44:43.970432 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3640 00:44:43.970485 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3641 00:44:43.970536
3642 00:44:43.970586 [DATLAT]
3643 00:44:43.970637 Freq=1200, CH1 RK1
3644 00:44:43.970689
3645 00:44:43.970740 DATLAT Default: 0xd
3646 00:44:43.970792 0, 0xFFFF, sum = 0
3647 00:44:43.970845 1, 0xFFFF, sum = 0
3648 00:44:43.970897 2, 0xFFFF, sum = 0
3649 00:44:43.970949 3, 0xFFFF, sum = 0
3650 00:44:43.971001 4, 0xFFFF, sum = 0
3651 00:44:43.971053 5, 0xFFFF, sum = 0
3652 00:44:43.971105 6, 0xFFFF, sum = 0
3653 00:44:43.971157 7, 0xFFFF, sum = 0
3654 00:44:43.971210 8, 0xFFFF, sum = 0
3655 00:44:43.971262 9, 0xFFFF, sum = 0
3656 00:44:43.971314 10, 0xFFFF, sum = 0
3657 00:44:43.971366 11, 0xFFFF, sum = 0
3658 00:44:43.971418 12, 0x0, sum = 1
3659 00:44:43.971471 13, 0x0, sum = 2
3660 00:44:43.971523 14, 0x0, sum = 3
3661 00:44:43.971575 15, 0x0, sum = 4
3662 00:44:43.971627 best_step = 13
3663 00:44:43.971678
3664 00:44:43.971730 ==
3665 00:44:43.971781 Dram Type= 6, Freq= 0, CH_1, rank 1
3666 00:44:43.971832 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3667 00:44:43.971884 ==
3668 00:44:43.971936 RX Vref Scan: 0
3669 00:44:43.971987
3670 00:44:43.972038 RX Vref 0 -> 0, step: 1
3671 00:44:43.972090
3672 00:44:43.972141 RX Delay -13 -> 252, step: 4
3673 00:44:43.972192 iDelay=195, Bit 0, Center 122 (63 ~ 182) 120
3674 00:44:43.972244 iDelay=195, Bit 1, Center 114 (55 ~ 174) 120
3675 00:44:43.972296 iDelay=195, Bit 2, Center 108 (51 ~ 166) 116
3676 00:44:43.972348 iDelay=195, Bit 3, Center 118 (59 ~ 178) 120
3677 00:44:43.972399 iDelay=195, Bit 4, Center 122 (63 ~ 182) 120
3678 00:44:43.972450 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3679 00:44:43.972502 iDelay=195, Bit 6, Center 126 (67 ~ 186) 120
3680 00:44:43.972556 iDelay=195, Bit 7, Center 116 (55 ~ 178) 124
3681 00:44:43.972642 iDelay=195, Bit 8, Center 100 (39 ~ 162) 124
3682 00:44:43.972694 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3683 00:44:43.972745 iDelay=195, Bit 10, Center 114 (51 ~ 178) 128
3684 00:44:43.972797 iDelay=195, Bit 11, Center 108 (43 ~ 174) 132
3685 00:44:43.972849 iDelay=195, Bit 12, Center 122 (59 ~ 186) 128
3686 00:44:43.972900 iDelay=195, Bit 13, Center 120 (59 ~ 182) 124
3687 00:44:43.972952 iDelay=195, Bit 14, Center 120 (59 ~ 182) 124
3688 00:44:43.973003 iDelay=195, Bit 15, Center 124 (59 ~ 190) 132
3689 00:44:43.973054 ==
3690 00:44:43.973106 Dram Type= 6, Freq= 0, CH_1, rank 1
3691 00:44:43.973157 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3692 00:44:43.973209 ==
3693 00:44:43.973260 DQS Delay:
3694 00:44:43.973311 DQS0 = 0, DQS1 = 0
3695 00:44:43.973362 DQM Delay:
3696 00:44:43.973413 DQM0 = 119, DQM1 = 113
3697 00:44:43.973465 DQ Delay:
3698 00:44:43.973516 DQ0 =122, DQ1 =114, DQ2 =108, DQ3 =118
3699 00:44:43.973567 DQ4 =122, DQ5 =130, DQ6 =126, DQ7 =116
3700 00:44:43.973619 DQ8 =100, DQ9 =102, DQ10 =114, DQ11 =108
3701 00:44:43.973671 DQ12 =122, DQ13 =120, DQ14 =120, DQ15 =124
3702 00:44:43.973722
3703 00:44:43.973773
3704 00:44:43.973824 [DQSOSCAuto] RK1, (LSB)MR18= 0xaef, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 406 ps
3705 00:44:43.973877 CH1 RK1: MR19=403, MR18=AEF
3706 00:44:43.973929 CH1_RK1: MR19=0x403, MR18=0xAEF, DQSOSC=406, MR23=63, INC=39, DEC=26
3707 00:44:43.973981 [RxdqsGatingPostProcess] freq 1200
3708 00:44:43.974033 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3709 00:44:43.974084 best DQS0 dly(2T, 0.5T) = (0, 11)
3710 00:44:43.974136 best DQS1 dly(2T, 0.5T) = (0, 11)
3711 00:44:43.974187 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3712 00:44:43.974238 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3713 00:44:43.974289 best DQS0 dly(2T, 0.5T) = (0, 11)
3714 00:44:43.974341 best DQS1 dly(2T, 0.5T) = (0, 11)
3715 00:44:43.974392 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3716 00:44:43.974637 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3717 00:44:43.974694 Pre-setting of DQS Precalculation
3718 00:44:43.974747 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3719 00:44:43.974800 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3720 00:44:43.974854 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3721 00:44:43.974907
3722 00:44:43.974958
3723 00:44:43.975009 [Calibration Summary] 2400 Mbps
3724 00:44:43.975061 CH 0, Rank 0
3725 00:44:43.975112 SW Impedance : PASS
3726 00:44:43.975164 DUTY Scan : NO K
3727 00:44:43.975216 ZQ Calibration : PASS
3728 00:44:43.975268 Jitter Meter : NO K
3729 00:44:43.975320 CBT Training : PASS
3730 00:44:43.975372 Write leveling : PASS
3731 00:44:43.975423 RX DQS gating : PASS
3732 00:44:43.975475 RX DQ/DQS(RDDQC) : PASS
3733 00:44:43.975526 TX DQ/DQS : PASS
3734 00:44:43.975578 RX DATLAT : PASS
3735 00:44:43.975629 RX DQ/DQS(Engine): PASS
3736 00:44:43.975681 TX OE : NO K
3737 00:44:43.975733 All Pass.
3738 00:44:43.975784
3739 00:44:43.975836 CH 0, Rank 1
3740 00:44:43.975887 SW Impedance : PASS
3741 00:44:43.975939 DUTY Scan : NO K
3742 00:44:43.975990 ZQ Calibration : PASS
3743 00:44:43.976041 Jitter Meter : NO K
3744 00:44:43.976092 CBT Training : PASS
3745 00:44:43.976144 Write leveling : PASS
3746 00:44:43.976221 RX DQS gating : PASS
3747 00:44:43.976276 RX DQ/DQS(RDDQC) : PASS
3748 00:44:43.976328 TX DQ/DQS : PASS
3749 00:44:43.976380 RX DATLAT : PASS
3750 00:44:43.976459 RX DQ/DQS(Engine): PASS
3751 00:44:43.976574 TX OE : NO K
3752 00:44:43.976646 All Pass.
3753 00:44:43.976699
3754 00:44:43.976751 CH 1, Rank 0
3755 00:44:43.976804 SW Impedance : PASS
3756 00:44:43.976856 DUTY Scan : NO K
3757 00:44:43.976908 ZQ Calibration : PASS
3758 00:44:43.976959 Jitter Meter : NO K
3759 00:44:43.977019 CBT Training : PASS
3760 00:44:43.977073 Write leveling : PASS
3761 00:44:43.977138 RX DQS gating : PASS
3762 00:44:43.977191 RX DQ/DQS(RDDQC) : PASS
3763 00:44:43.977244 TX DQ/DQS : PASS
3764 00:44:43.977296 RX DATLAT : PASS
3765 00:44:43.977348 RX DQ/DQS(Engine): PASS
3766 00:44:43.977400 TX OE : NO K
3767 00:44:43.977451 All Pass.
3768 00:44:43.977502
3769 00:44:43.977554 CH 1, Rank 1
3770 00:44:43.977605 SW Impedance : PASS
3771 00:44:43.977657 DUTY Scan : NO K
3772 00:44:43.977708 ZQ Calibration : PASS
3773 00:44:43.977760 Jitter Meter : NO K
3774 00:44:43.977812 CBT Training : PASS
3775 00:44:43.977863 Write leveling : PASS
3776 00:44:43.977914 RX DQS gating : PASS
3777 00:44:43.977965 RX DQ/DQS(RDDQC) : PASS
3778 00:44:43.978017 TX DQ/DQS : PASS
3779 00:44:43.978068 RX DATLAT : PASS
3780 00:44:43.978119 RX DQ/DQS(Engine): PASS
3781 00:44:43.978172 TX OE : NO K
3782 00:44:43.978223 All Pass.
3783 00:44:43.978275
3784 00:44:43.978326 DramC Write-DBI off
3785 00:44:43.978380 PER_BANK_REFRESH: Hybrid Mode
3786 00:44:43.978433 TX_TRACKING: ON
3787 00:44:43.978486 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3788 00:44:43.978539 [FAST_K] Save calibration result to emmc
3789 00:44:43.978595 dramc_set_vcore_voltage set vcore to 650000
3790 00:44:43.978649 Read voltage for 600, 5
3791 00:44:43.978701 Vio18 = 0
3792 00:44:43.978752 Vcore = 650000
3793 00:44:43.978803 Vdram = 0
3794 00:44:43.978854 Vddq = 0
3795 00:44:43.978910 Vmddr = 0
3796 00:44:43.978965 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3797 00:44:43.979018 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3798 00:44:43.979070 MEM_TYPE=3, freq_sel=19
3799 00:44:43.979127 sv_algorithm_assistance_LP4_1600
3800 00:44:43.979179 ============ PULL DRAM RESETB DOWN ============
3801 00:44:43.979232 ========== PULL DRAM RESETB DOWN end =========
3802 00:44:43.979284 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3803 00:44:43.979335 ===================================
3804 00:44:43.979388 LPDDR4 DRAM CONFIGURATION
3805 00:44:43.979440 ===================================
3806 00:44:43.979492 EX_ROW_EN[0] = 0x0
3807 00:44:43.979544 EX_ROW_EN[1] = 0x0
3808 00:44:43.979610 LP4Y_EN = 0x0
3809 00:44:43.979663 WORK_FSP = 0x0
3810 00:44:43.979718 WL = 0x2
3811 00:44:43.979777 RL = 0x2
3812 00:44:43.979841 BL = 0x2
3813 00:44:43.979893 RPST = 0x0
3814 00:44:43.979945 RD_PRE = 0x0
3815 00:44:43.979997 WR_PRE = 0x1
3816 00:44:43.980049 WR_PST = 0x0
3817 00:44:43.980100 DBI_WR = 0x0
3818 00:44:43.980151 DBI_RD = 0x0
3819 00:44:43.980202 OTF = 0x1
3820 00:44:43.980263 ===================================
3821 00:44:43.980324 ===================================
3822 00:44:43.980379 ANA top config
3823 00:44:43.980430 ===================================
3824 00:44:43.980482 DLL_ASYNC_EN = 0
3825 00:44:43.980534 ALL_SLAVE_EN = 1
3826 00:44:43.980621 NEW_RANK_MODE = 1
3827 00:44:43.980674 DLL_IDLE_MODE = 1
3828 00:44:43.980725 LP45_APHY_COMB_EN = 1
3829 00:44:43.980777 TX_ODT_DIS = 1
3830 00:44:43.980829 NEW_8X_MODE = 1
3831 00:44:43.980881 ===================================
3832 00:44:43.980932 ===================================
3833 00:44:43.980985 data_rate = 1200
3834 00:44:43.981037 CKR = 1
3835 00:44:43.981088 DQ_P2S_RATIO = 8
3836 00:44:43.981139 ===================================
3837 00:44:43.981191 CA_P2S_RATIO = 8
3838 00:44:43.981243 DQ_CA_OPEN = 0
3839 00:44:43.981294 DQ_SEMI_OPEN = 0
3840 00:44:43.981345 CA_SEMI_OPEN = 0
3841 00:44:43.981396 CA_FULL_RATE = 0
3842 00:44:43.981448 DQ_CKDIV4_EN = 1
3843 00:44:43.981499 CA_CKDIV4_EN = 1
3844 00:44:43.981550 CA_PREDIV_EN = 0
3845 00:44:43.981603 PH8_DLY = 0
3846 00:44:43.981655 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3847 00:44:43.981706 DQ_AAMCK_DIV = 4
3848 00:44:43.981757 CA_AAMCK_DIV = 4
3849 00:44:43.981809 CA_ADMCK_DIV = 4
3850 00:44:43.981860 DQ_TRACK_CA_EN = 0
3851 00:44:43.981911 CA_PICK = 600
3852 00:44:43.981963 CA_MCKIO = 600
3853 00:44:43.982014 MCKIO_SEMI = 0
3854 00:44:43.982066 PLL_FREQ = 2288
3855 00:44:43.982117 DQ_UI_PI_RATIO = 32
3856 00:44:43.982170 CA_UI_PI_RATIO = 0
3857 00:44:43.982221 ===================================
3858 00:44:43.982274 ===================================
3859 00:44:43.982326 memory_type:LPDDR4
3860 00:44:43.982377 GP_NUM : 10
3861 00:44:43.982428 SRAM_EN : 1
3862 00:44:43.982480 MD32_EN : 0
3863 00:44:43.982722 ===================================
3864 00:44:43.982783 [ANA_INIT] >>>>>>>>>>>>>>
3865 00:44:43.982837 <<<<<< [CONFIGURE PHASE]: ANA_TX
3866 00:44:43.982889 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3867 00:44:43.982942 ===================================
3868 00:44:43.982993 data_rate = 1200,PCW = 0X5800
3869 00:44:43.983045 ===================================
3870 00:44:43.983097 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3871 00:44:43.983148 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3872 00:44:43.983200 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3873 00:44:43.983252 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3874 00:44:43.983305 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3875 00:44:43.983356 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3876 00:44:43.983408 [ANA_INIT] flow start
3877 00:44:43.983459 [ANA_INIT] PLL >>>>>>>>
3878 00:44:43.983510 [ANA_INIT] PLL <<<<<<<<
3879 00:44:43.983562 [ANA_INIT] MIDPI >>>>>>>>
3880 00:44:43.983613 [ANA_INIT] MIDPI <<<<<<<<
3881 00:44:43.983664 [ANA_INIT] DLL >>>>>>>>
3882 00:44:43.983715 [ANA_INIT] flow end
3883 00:44:43.983766 ============ LP4 DIFF to SE enter ============
3884 00:44:43.983819 ============ LP4 DIFF to SE exit ============
3885 00:44:43.983872 [ANA_INIT] <<<<<<<<<<<<<
3886 00:44:43.983923 [Flow] Enable top DCM control >>>>>
3887 00:44:43.983975 [Flow] Enable top DCM control <<<<<
3888 00:44:43.984026 Enable DLL master slave shuffle
3889 00:44:43.984077 ==============================================================
3890 00:44:43.984129 Gating Mode config
3891 00:44:43.984180 ==============================================================
3892 00:44:43.984232 Config description:
3893 00:44:43.984283 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3894 00:44:43.984336 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3895 00:44:43.984388 SELPH_MODE 0: By rank 1: By Phase
3896 00:44:43.984440 ==============================================================
3897 00:44:43.984492 GAT_TRACK_EN = 1
3898 00:44:43.984544 RX_GATING_MODE = 2
3899 00:44:43.984636 RX_GATING_TRACK_MODE = 2
3900 00:44:43.984707 SELPH_MODE = 1
3901 00:44:43.984761 PICG_EARLY_EN = 1
3902 00:44:43.984824 VALID_LAT_VALUE = 1
3903 00:44:43.984889 ==============================================================
3904 00:44:43.984943 Enter into Gating configuration >>>>
3905 00:44:43.985000 Exit from Gating configuration <<<<
3906 00:44:43.985052 Enter into DVFS_PRE_config >>>>>
3907 00:44:43.985104 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3908 00:44:43.985160 Exit from DVFS_PRE_config <<<<<
3909 00:44:43.985223 Enter into PICG configuration >>>>
3910 00:44:43.985285 Exit from PICG configuration <<<<
3911 00:44:43.985353 [RX_INPUT] configuration >>>>>
3912 00:44:43.985419 [RX_INPUT] configuration <<<<<
3913 00:44:43.985489 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3914 00:44:43.991806 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3915 00:44:43.998601 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3916 00:44:44.001513 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3917 00:44:44.008024 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3918 00:44:44.014928 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3919 00:44:44.018057 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3920 00:44:44.024972 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3921 00:44:44.028017 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3922 00:44:44.031806 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3923 00:44:44.035056 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3924 00:44:44.041433 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3925 00:44:44.044882 ===================================
3926 00:44:44.045240 LPDDR4 DRAM CONFIGURATION
3927 00:44:44.048464 ===================================
3928 00:44:44.051709 EX_ROW_EN[0] = 0x0
3929 00:44:44.055041 EX_ROW_EN[1] = 0x0
3930 00:44:44.055775 LP4Y_EN = 0x0
3931 00:44:44.058134 WORK_FSP = 0x0
3932 00:44:44.058588 WL = 0x2
3933 00:44:44.061737 RL = 0x2
3934 00:44:44.062294 BL = 0x2
3935 00:44:44.064635 RPST = 0x0
3936 00:44:44.065091 RD_PRE = 0x0
3937 00:44:44.068143 WR_PRE = 0x1
3938 00:44:44.068709 WR_PST = 0x0
3939 00:44:44.071651 DBI_WR = 0x0
3940 00:44:44.072101 DBI_RD = 0x0
3941 00:44:44.075098 OTF = 0x1
3942 00:44:44.078116 ===================================
3943 00:44:44.081504 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3944 00:44:44.084995 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3945 00:44:44.091597 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3946 00:44:44.095087 ===================================
3947 00:44:44.095650 LPDDR4 DRAM CONFIGURATION
3948 00:44:44.098337 ===================================
3949 00:44:44.101523 EX_ROW_EN[0] = 0x10
3950 00:44:44.104985 EX_ROW_EN[1] = 0x0
3951 00:44:44.105440 LP4Y_EN = 0x0
3952 00:44:44.107862 WORK_FSP = 0x0
3953 00:44:44.108314 WL = 0x2
3954 00:44:44.111369 RL = 0x2
3955 00:44:44.111826 BL = 0x2
3956 00:44:44.114866 RPST = 0x0
3957 00:44:44.115326 RD_PRE = 0x0
3958 00:44:44.117945 WR_PRE = 0x1
3959 00:44:44.118416 WR_PST = 0x0
3960 00:44:44.121395 DBI_WR = 0x0
3961 00:44:44.121857 DBI_RD = 0x0
3962 00:44:44.124845 OTF = 0x1
3963 00:44:44.127775 ===================================
3964 00:44:44.134710 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3965 00:44:44.137717 nWR fixed to 30
3966 00:44:44.138179 [ModeRegInit_LP4] CH0 RK0
3967 00:44:44.141203 [ModeRegInit_LP4] CH0 RK1
3968 00:44:44.144626 [ModeRegInit_LP4] CH1 RK0
3969 00:44:44.147903 [ModeRegInit_LP4] CH1 RK1
3970 00:44:44.148309 match AC timing 17
3971 00:44:44.151173 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3972 00:44:44.157772 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3973 00:44:44.161276 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3974 00:44:44.164271 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3975 00:44:44.170765 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3976 00:44:44.170997 ==
3977 00:44:44.174291 Dram Type= 6, Freq= 0, CH_0, rank 0
3978 00:44:44.177263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3979 00:44:44.177496 ==
3980 00:44:44.184517 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3981 00:44:44.191038 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3982 00:44:44.194806 [CA 0] Center 36 (6~67) winsize 62
3983 00:44:44.197607 [CA 1] Center 36 (6~67) winsize 62
3984 00:44:44.201121 [CA 2] Center 34 (4~65) winsize 62
3985 00:44:44.204814 [CA 3] Center 34 (4~65) winsize 62
3986 00:44:44.207820 [CA 4] Center 33 (3~64) winsize 62
3987 00:44:44.211161 [CA 5] Center 33 (2~64) winsize 63
3988 00:44:44.211733
3989 00:44:44.214353 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3990 00:44:44.214827
3991 00:44:44.217442 [CATrainingPosCal] consider 1 rank data
3992 00:44:44.221212 u2DelayCellTimex100 = 270/100 ps
3993 00:44:44.224620 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3994 00:44:44.227919 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3995 00:44:44.231340 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3996 00:44:44.234237 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3997 00:44:44.237573 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3998 00:44:44.241142 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
3999 00:44:44.241711
4000 00:44:44.244529 CA PerBit enable=1, Macro0, CA PI delay=33
4001 00:44:44.247986
4002 00:44:44.248594 [CBTSetCACLKResult] CA Dly = 33
4003 00:44:44.251518 CS Dly: 4 (0~35)
4004 00:44:44.252086 ==
4005 00:44:44.254453 Dram Type= 6, Freq= 0, CH_0, rank 1
4006 00:44:44.257966 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4007 00:44:44.258542 ==
4008 00:44:44.264331 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4009 00:44:44.270762 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4010 00:44:44.274197 [CA 0] Center 36 (6~67) winsize 62
4011 00:44:44.277738 [CA 1] Center 36 (6~67) winsize 62
4012 00:44:44.280983 [CA 2] Center 35 (5~66) winsize 62
4013 00:44:44.284354 [CA 3] Center 34 (4~65) winsize 62
4014 00:44:44.287821 [CA 4] Center 34 (3~65) winsize 63
4015 00:44:44.290730 [CA 5] Center 34 (3~65) winsize 63
4016 00:44:44.291227
4017 00:44:44.294485 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4018 00:44:44.294956
4019 00:44:44.297365 [CATrainingPosCal] consider 2 rank data
4020 00:44:44.301122 u2DelayCellTimex100 = 270/100 ps
4021 00:44:44.304467 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
4022 00:44:44.307766 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
4023 00:44:44.311522 CA2 delay=35 (5~65),Diff = 2 PI (19 cell)
4024 00:44:44.314136 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4025 00:44:44.317777 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4026 00:44:44.321325 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4027 00:44:44.321915
4028 00:44:44.327863 CA PerBit enable=1, Macro0, CA PI delay=33
4029 00:44:44.328444
4030 00:44:44.328901 [CBTSetCACLKResult] CA Dly = 33
4031 00:44:44.331208 CS Dly: 5 (0~37)
4032 00:44:44.331781
4033 00:44:44.334182 ----->DramcWriteLeveling(PI) begin...
4034 00:44:44.334770 ==
4035 00:44:44.337533 Dram Type= 6, Freq= 0, CH_0, rank 0
4036 00:44:44.340957 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4037 00:44:44.341536 ==
4038 00:44:44.344385 Write leveling (Byte 0): 33 => 33
4039 00:44:44.347972 Write leveling (Byte 1): 29 => 29
4040 00:44:44.350794 DramcWriteLeveling(PI) end<-----
4041 00:44:44.351371
4042 00:44:44.351747 ==
4043 00:44:44.354247 Dram Type= 6, Freq= 0, CH_0, rank 0
4044 00:44:44.357529 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4045 00:44:44.360876 ==
4046 00:44:44.361350 [Gating] SW mode calibration
4047 00:44:44.367621 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4048 00:44:44.373969 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4049 00:44:44.377386 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4050 00:44:44.383854 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4051 00:44:44.387491 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4052 00:44:44.390744 0 9 12 | B1->B0 | 3333 2f2f | 1 0 | (1 1) (1 1)
4053 00:44:44.397223 0 9 16 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
4054 00:44:44.400875 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4055 00:44:44.403739 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4056 00:44:44.410981 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4057 00:44:44.413986 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4058 00:44:44.417613 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4059 00:44:44.423982 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4060 00:44:44.427222 0 10 12 | B1->B0 | 2828 4040 | 0 0 | (0 0) (0 0)
4061 00:44:44.430884 0 10 16 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
4062 00:44:44.434029 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4063 00:44:44.441048 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4064 00:44:44.443959 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4065 00:44:44.447542 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4066 00:44:44.454006 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4067 00:44:44.457472 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4068 00:44:44.460246 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4069 00:44:44.467108 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4070 00:44:44.470124 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4071 00:44:44.473448 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4072 00:44:44.480423 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4073 00:44:44.484286 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4074 00:44:44.487096 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4075 00:44:44.494013 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4076 00:44:44.497210 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4077 00:44:44.500463 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4078 00:44:44.507357 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4079 00:44:44.510305 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4080 00:44:44.513597 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4081 00:44:44.520973 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4082 00:44:44.523754 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4083 00:44:44.527358 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4084 00:44:44.534168 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4085 00:44:44.537212 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4086 00:44:44.540718 Total UI for P1: 0, mck2ui 16
4087 00:44:44.543911 best dqsien dly found for B0: ( 0, 13, 12)
4088 00:44:44.547069 Total UI for P1: 0, mck2ui 16
4089 00:44:44.550543 best dqsien dly found for B1: ( 0, 13, 14)
4090 00:44:44.554018 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4091 00:44:44.557059 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4092 00:44:44.557627
4093 00:44:44.560404 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4094 00:44:44.563824 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4095 00:44:44.567041 [Gating] SW calibration Done
4096 00:44:44.567503 ==
4097 00:44:44.570489 Dram Type= 6, Freq= 0, CH_0, rank 0
4098 00:44:44.573610 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4099 00:44:44.574095 ==
4100 00:44:44.576778 RX Vref Scan: 0
4101 00:44:44.577239
4102 00:44:44.580583 RX Vref 0 -> 0, step: 1
4103 00:44:44.581155
4104 00:44:44.581544 RX Delay -230 -> 252, step: 16
4105 00:44:44.587305 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4106 00:44:44.590292 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4107 00:44:44.593630 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4108 00:44:44.596931 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4109 00:44:44.603651 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4110 00:44:44.607176 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4111 00:44:44.610460 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4112 00:44:44.613333 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4113 00:44:44.616843 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4114 00:44:44.623876 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4115 00:44:44.627096 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4116 00:44:44.630502 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4117 00:44:44.633859 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4118 00:44:44.640016 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4119 00:44:44.643853 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4120 00:44:44.646660 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4121 00:44:44.647229 ==
4122 00:44:44.650228 Dram Type= 6, Freq= 0, CH_0, rank 0
4123 00:44:44.653280 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4124 00:44:44.657012 ==
4125 00:44:44.657577 DQS Delay:
4126 00:44:44.657948 DQS0 = 0, DQS1 = 0
4127 00:44:44.660242 DQM Delay:
4128 00:44:44.660737 DQM0 = 50, DQM1 = 40
4129 00:44:44.663498 DQ Delay:
4130 00:44:44.664063 DQ0 =49, DQ1 =57, DQ2 =41, DQ3 =41
4131 00:44:44.666748 DQ4 =57, DQ5 =41, DQ6 =57, DQ7 =57
4132 00:44:44.669921 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =33
4133 00:44:44.673602 DQ12 =41, DQ13 =41, DQ14 =57, DQ15 =41
4134 00:44:44.674174
4135 00:44:44.676845
4136 00:44:44.677305 ==
4137 00:44:44.680142 Dram Type= 6, Freq= 0, CH_0, rank 0
4138 00:44:44.683765 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4139 00:44:44.684335 ==
4140 00:44:44.684748
4141 00:44:44.685093
4142 00:44:44.687280 TX Vref Scan disable
4143 00:44:44.687844 == TX Byte 0 ==
4144 00:44:44.693481 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4145 00:44:44.696747 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4146 00:44:44.697212 == TX Byte 1 ==
4147 00:44:44.703892 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4148 00:44:44.706699 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4149 00:44:44.707168 ==
4150 00:44:44.709738 Dram Type= 6, Freq= 0, CH_0, rank 0
4151 00:44:44.713111 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4152 00:44:44.713580 ==
4153 00:44:44.714097
4154 00:44:44.714561
4155 00:44:44.716406 TX Vref Scan disable
4156 00:44:44.720094 == TX Byte 0 ==
4157 00:44:44.723402 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4158 00:44:44.726680 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4159 00:44:44.729833 == TX Byte 1 ==
4160 00:44:44.733487 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4161 00:44:44.737187 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4162 00:44:44.737754
4163 00:44:44.739955 [DATLAT]
4164 00:44:44.740518 Freq=600, CH0 RK0
4165 00:44:44.740936
4166 00:44:44.743438 DATLAT Default: 0x9
4167 00:44:44.744003 0, 0xFFFF, sum = 0
4168 00:44:44.746513 1, 0xFFFF, sum = 0
4169 00:44:44.746983 2, 0xFFFF, sum = 0
4170 00:44:44.750253 3, 0xFFFF, sum = 0
4171 00:44:44.750827 4, 0xFFFF, sum = 0
4172 00:44:44.753323 5, 0xFFFF, sum = 0
4173 00:44:44.753794 6, 0xFFFF, sum = 0
4174 00:44:44.757124 7, 0xFFFF, sum = 0
4175 00:44:44.757697 8, 0x0, sum = 1
4176 00:44:44.759756 9, 0x0, sum = 2
4177 00:44:44.760227 10, 0x0, sum = 3
4178 00:44:44.763545 11, 0x0, sum = 4
4179 00:44:44.764114 best_step = 9
4180 00:44:44.764483
4181 00:44:44.764888 ==
4182 00:44:44.766752 Dram Type= 6, Freq= 0, CH_0, rank 0
4183 00:44:44.769826 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4184 00:44:44.773253 ==
4185 00:44:44.773716 RX Vref Scan: 1
4186 00:44:44.774081
4187 00:44:44.777061 RX Vref 0 -> 0, step: 1
4188 00:44:44.777631
4189 00:44:44.780415 RX Delay -163 -> 252, step: 8
4190 00:44:44.781033
4191 00:44:44.783487 Set Vref, RX VrefLevel [Byte0]: 59
4192 00:44:44.786682 [Byte1]: 50
4193 00:44:44.787251
4194 00:44:44.790262 Final RX Vref Byte 0 = 59 to rank0
4195 00:44:44.793392 Final RX Vref Byte 1 = 50 to rank0
4196 00:44:44.796735 Final RX Vref Byte 0 = 59 to rank1
4197 00:44:44.800054 Final RX Vref Byte 1 = 50 to rank1==
4198 00:44:44.803193 Dram Type= 6, Freq= 0, CH_0, rank 0
4199 00:44:44.806616 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4200 00:44:44.807085 ==
4201 00:44:44.807456 DQS Delay:
4202 00:44:44.809663 DQS0 = 0, DQS1 = 0
4203 00:44:44.810127 DQM Delay:
4204 00:44:44.813045 DQM0 = 48, DQM1 = 39
4205 00:44:44.813677 DQ Delay:
4206 00:44:44.817115 DQ0 =44, DQ1 =48, DQ2 =44, DQ3 =44
4207 00:44:44.819754 DQ4 =48, DQ5 =40, DQ6 =60, DQ7 =56
4208 00:44:44.823062 DQ8 =36, DQ9 =28, DQ10 =36, DQ11 =32
4209 00:44:44.826678 DQ12 =44, DQ13 =40, DQ14 =52, DQ15 =48
4210 00:44:44.827265
4211 00:44:44.827635
4212 00:44:44.836671 [DQSOSCAuto] RK0, (LSB)MR18= 0x5e58, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 392 ps
4213 00:44:44.837246 CH0 RK0: MR19=808, MR18=5E58
4214 00:44:44.843577 CH0_RK0: MR19=0x808, MR18=0x5E58, DQSOSC=392, MR23=63, INC=170, DEC=113
4215 00:44:44.844142
4216 00:44:44.846313 ----->DramcWriteLeveling(PI) begin...
4217 00:44:44.846784 ==
4218 00:44:44.850243 Dram Type= 6, Freq= 0, CH_0, rank 1
4219 00:44:44.856895 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4220 00:44:44.857472 ==
4221 00:44:44.859527 Write leveling (Byte 0): 34 => 34
4222 00:44:44.863208 Write leveling (Byte 1): 30 => 30
4223 00:44:44.863788 DramcWriteLeveling(PI) end<-----
4224 00:44:44.864168
4225 00:44:44.866704 ==
4226 00:44:44.869950 Dram Type= 6, Freq= 0, CH_0, rank 1
4227 00:44:44.873450 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4228 00:44:44.874019 ==
4229 00:44:44.876418 [Gating] SW mode calibration
4230 00:44:44.883327 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4231 00:44:44.886702 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4232 00:44:44.893395 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4233 00:44:44.896468 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4234 00:44:44.900250 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4235 00:44:44.906379 0 9 12 | B1->B0 | 3333 3333 | 0 0 | (0 1) (0 1)
4236 00:44:44.909777 0 9 16 | B1->B0 | 2525 2424 | 0 0 | (0 0) (0 0)
4237 00:44:44.913247 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4238 00:44:44.919908 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4239 00:44:44.923038 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4240 00:44:44.926461 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4241 00:44:44.933217 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4242 00:44:44.936287 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4243 00:44:44.939961 0 10 12 | B1->B0 | 3232 3232 | 1 0 | (0 0) (0 0)
4244 00:44:44.943454 0 10 16 | B1->B0 | 4040 4545 | 1 0 | (0 0) (0 0)
4245 00:44:44.949915 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4246 00:44:44.953349 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4247 00:44:44.956868 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4248 00:44:44.963351 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4249 00:44:44.966829 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4250 00:44:44.969532 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4251 00:44:44.976312 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4252 00:44:44.979990 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4253 00:44:44.983525 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4254 00:44:44.989556 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4255 00:44:44.993094 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4256 00:44:44.996500 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4257 00:44:45.002709 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4258 00:44:45.006402 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4259 00:44:45.009591 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4260 00:44:45.016217 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4261 00:44:45.019496 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4262 00:44:45.022690 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4263 00:44:45.029449 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4264 00:44:45.032815 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4265 00:44:45.035875 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4266 00:44:45.042579 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4267 00:44:45.046164 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4268 00:44:45.049409 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4269 00:44:45.052708 Total UI for P1: 0, mck2ui 16
4270 00:44:45.056236 best dqsien dly found for B0: ( 0, 13, 14)
4271 00:44:45.059495 Total UI for P1: 0, mck2ui 16
4272 00:44:45.062600 best dqsien dly found for B1: ( 0, 13, 12)
4273 00:44:45.066063 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4274 00:44:45.069058 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4275 00:44:45.069581
4276 00:44:45.072336 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4277 00:44:45.079140 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4278 00:44:45.079613 [Gating] SW calibration Done
4279 00:44:45.079983 ==
4280 00:44:45.082600 Dram Type= 6, Freq= 0, CH_0, rank 1
4281 00:44:45.089850 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4282 00:44:45.090421 ==
4283 00:44:45.090796 RX Vref Scan: 0
4284 00:44:45.091147
4285 00:44:45.092364 RX Vref 0 -> 0, step: 1
4286 00:44:45.092882
4287 00:44:45.095904 RX Delay -230 -> 252, step: 16
4288 00:44:45.099360 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4289 00:44:45.102630 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4290 00:44:45.109374 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4291 00:44:45.112422 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4292 00:44:45.115922 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4293 00:44:45.119323 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4294 00:44:45.122833 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4295 00:44:45.129427 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4296 00:44:45.132491 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4297 00:44:45.135877 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4298 00:44:45.139487 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4299 00:44:45.145738 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4300 00:44:45.149461 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4301 00:44:45.152992 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4302 00:44:45.156064 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4303 00:44:45.159675 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4304 00:44:45.162370 ==
4305 00:44:45.165866 Dram Type= 6, Freq= 0, CH_0, rank 1
4306 00:44:45.168978 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4307 00:44:45.169454 ==
4308 00:44:45.169825 DQS Delay:
4309 00:44:45.172648 DQS0 = 0, DQS1 = 0
4310 00:44:45.173241 DQM Delay:
4311 00:44:45.175971 DQM0 = 48, DQM1 = 40
4312 00:44:45.176440 DQ Delay:
4313 00:44:45.179395 DQ0 =41, DQ1 =57, DQ2 =41, DQ3 =41
4314 00:44:45.182471 DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =57
4315 00:44:45.185949 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =41
4316 00:44:45.189363 DQ12 =41, DQ13 =49, DQ14 =49, DQ15 =49
4317 00:44:45.189937
4318 00:44:45.190308
4319 00:44:45.190648 ==
4320 00:44:45.192275 Dram Type= 6, Freq= 0, CH_0, rank 1
4321 00:44:45.196092 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4322 00:44:45.196910 ==
4323 00:44:45.197299
4324 00:44:45.197647
4325 00:44:45.199605 TX Vref Scan disable
4326 00:44:45.202587 == TX Byte 0 ==
4327 00:44:45.205922 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4328 00:44:45.209025 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4329 00:44:45.212777 == TX Byte 1 ==
4330 00:44:45.216066 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4331 00:44:45.219163 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4332 00:44:45.219735 ==
4333 00:44:45.222548 Dram Type= 6, Freq= 0, CH_0, rank 1
4334 00:44:45.225942 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4335 00:44:45.229476 ==
4336 00:44:45.230045
4337 00:44:45.230525
4338 00:44:45.230971 TX Vref Scan disable
4339 00:44:45.233212 == TX Byte 0 ==
4340 00:44:45.236771 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4341 00:44:45.243471 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4342 00:44:45.244063 == TX Byte 1 ==
4343 00:44:45.246575 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4344 00:44:45.253181 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4345 00:44:45.253748
4346 00:44:45.254226 [DATLAT]
4347 00:44:45.254675 Freq=600, CH0 RK1
4348 00:44:45.255137
4349 00:44:45.256124 DATLAT Default: 0x9
4350 00:44:45.256631 0, 0xFFFF, sum = 0
4351 00:44:45.259694 1, 0xFFFF, sum = 0
4352 00:44:45.260272 2, 0xFFFF, sum = 0
4353 00:44:45.263089 3, 0xFFFF, sum = 0
4354 00:44:45.266403 4, 0xFFFF, sum = 0
4355 00:44:45.266923 5, 0xFFFF, sum = 0
4356 00:44:45.269762 6, 0xFFFF, sum = 0
4357 00:44:45.270250 7, 0xFFFF, sum = 0
4358 00:44:45.272960 8, 0x0, sum = 1
4359 00:44:45.273432 9, 0x0, sum = 2
4360 00:44:45.273813 10, 0x0, sum = 3
4361 00:44:45.276358 11, 0x0, sum = 4
4362 00:44:45.276849 best_step = 9
4363 00:44:45.277208
4364 00:44:45.277543 ==
4365 00:44:45.279843 Dram Type= 6, Freq= 0, CH_0, rank 1
4366 00:44:45.286482 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4367 00:44:45.286944 ==
4368 00:44:45.287302 RX Vref Scan: 0
4369 00:44:45.287636
4370 00:44:45.289468 RX Vref 0 -> 0, step: 1
4371 00:44:45.289921
4372 00:44:45.292898 RX Delay -179 -> 252, step: 8
4373 00:44:45.296293 iDelay=205, Bit 0, Center 48 (-99 ~ 196) 296
4374 00:44:45.303007 iDelay=205, Bit 1, Center 48 (-99 ~ 196) 296
4375 00:44:45.306095 iDelay=205, Bit 2, Center 44 (-99 ~ 188) 288
4376 00:44:45.309758 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4377 00:44:45.312955 iDelay=205, Bit 4, Center 48 (-99 ~ 196) 296
4378 00:44:45.316271 iDelay=205, Bit 5, Center 40 (-107 ~ 188) 296
4379 00:44:45.322813 iDelay=205, Bit 6, Center 56 (-91 ~ 204) 296
4380 00:44:45.326347 iDelay=205, Bit 7, Center 56 (-91 ~ 204) 296
4381 00:44:45.329764 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4382 00:44:45.332995 iDelay=205, Bit 9, Center 28 (-115 ~ 172) 288
4383 00:44:45.336393 iDelay=205, Bit 10, Center 40 (-107 ~ 188) 296
4384 00:44:45.342841 iDelay=205, Bit 11, Center 32 (-115 ~ 180) 296
4385 00:44:45.346083 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4386 00:44:45.350261 iDelay=205, Bit 13, Center 44 (-99 ~ 188) 288
4387 00:44:45.353169 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4388 00:44:45.356302 iDelay=205, Bit 15, Center 44 (-99 ~ 188) 288
4389 00:44:45.359297 ==
4390 00:44:45.362971 Dram Type= 6, Freq= 0, CH_0, rank 1
4391 00:44:45.366275 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4392 00:44:45.366735 ==
4393 00:44:45.367095 DQS Delay:
4394 00:44:45.369233 DQS0 = 0, DQS1 = 0
4395 00:44:45.369690 DQM Delay:
4396 00:44:45.372793 DQM0 = 48, DQM1 = 39
4397 00:44:45.373290 DQ Delay:
4398 00:44:45.376031 DQ0 =48, DQ1 =48, DQ2 =44, DQ3 =44
4399 00:44:45.379552 DQ4 =48, DQ5 =40, DQ6 =56, DQ7 =56
4400 00:44:45.383130 DQ8 =32, DQ9 =28, DQ10 =40, DQ11 =32
4401 00:44:45.386357 DQ12 =48, DQ13 =44, DQ14 =48, DQ15 =44
4402 00:44:45.386909
4403 00:44:45.387273
4404 00:44:45.392931 [DQSOSCAuto] RK1, (LSB)MR18= 0x6532, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 390 ps
4405 00:44:45.396326 CH0 RK1: MR19=808, MR18=6532
4406 00:44:45.402984 CH0_RK1: MR19=0x808, MR18=0x6532, DQSOSC=390, MR23=63, INC=172, DEC=114
4407 00:44:45.406332 [RxdqsGatingPostProcess] freq 600
4408 00:44:45.412950 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4409 00:44:45.413505 Pre-setting of DQS Precalculation
4410 00:44:45.419726 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4411 00:44:45.420288 ==
4412 00:44:45.423090 Dram Type= 6, Freq= 0, CH_1, rank 0
4413 00:44:45.426529 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4414 00:44:45.427087 ==
4415 00:44:45.433110 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4416 00:44:45.439943 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=31, u1VrefScanEnd=31
4417 00:44:45.443210 [CA 0] Center 35 (5~66) winsize 62
4418 00:44:45.446434 [CA 1] Center 35 (5~66) winsize 62
4419 00:44:45.449470 [CA 2] Center 34 (4~65) winsize 62
4420 00:44:45.453102 [CA 3] Center 34 (3~65) winsize 63
4421 00:44:45.456331 [CA 4] Center 34 (3~65) winsize 63
4422 00:44:45.459617 [CA 5] Center 34 (3~65) winsize 63
4423 00:44:45.460203
4424 00:44:45.462768 [CmdBusTrainingLP45] Vref(ca) range 1: 31
4425 00:44:45.463336
4426 00:44:45.466366 [CATrainingPosCal] consider 1 rank data
4427 00:44:45.469706 u2DelayCellTimex100 = 270/100 ps
4428 00:44:45.472606 CA0 delay=35 (5~66),Diff = 1 PI (9 cell)
4429 00:44:45.476101 CA1 delay=35 (5~66),Diff = 1 PI (9 cell)
4430 00:44:45.479736 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4431 00:44:45.483053 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
4432 00:44:45.486092 CA4 delay=34 (3~65),Diff = 0 PI (0 cell)
4433 00:44:45.489630 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4434 00:44:45.490211
4435 00:44:45.492661 CA PerBit enable=1, Macro0, CA PI delay=34
4436 00:44:45.496029
4437 00:44:45.496660 [CBTSetCACLKResult] CA Dly = 34
4438 00:44:45.499151 CS Dly: 5 (0~36)
4439 00:44:45.499628 ==
4440 00:44:45.502926 Dram Type= 6, Freq= 0, CH_1, rank 1
4441 00:44:45.506026 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4442 00:44:45.506508 ==
4443 00:44:45.512794 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4444 00:44:45.519274 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4445 00:44:45.522730 [CA 0] Center 35 (5~66) winsize 62
4446 00:44:45.526030 [CA 1] Center 35 (5~66) winsize 62
4447 00:44:45.529291 [CA 2] Center 34 (4~65) winsize 62
4448 00:44:45.532817 [CA 3] Center 34 (4~65) winsize 62
4449 00:44:45.535684 [CA 4] Center 34 (4~65) winsize 62
4450 00:44:45.539060 [CA 5] Center 34 (4~64) winsize 61
4451 00:44:45.539523
4452 00:44:45.542391 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4453 00:44:45.542854
4454 00:44:45.546085 [CATrainingPosCal] consider 2 rank data
4455 00:44:45.549133 u2DelayCellTimex100 = 270/100 ps
4456 00:44:45.552349 CA0 delay=35 (5~66),Diff = 1 PI (9 cell)
4457 00:44:45.556102 CA1 delay=35 (5~66),Diff = 1 PI (9 cell)
4458 00:44:45.559501 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4459 00:44:45.562613 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4460 00:44:45.565815 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4461 00:44:45.569231 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4462 00:44:45.569694
4463 00:44:45.575578 CA PerBit enable=1, Macro0, CA PI delay=34
4464 00:44:45.576044
4465 00:44:45.576413 [CBTSetCACLKResult] CA Dly = 34
4466 00:44:45.578933 CS Dly: 5 (0~37)
4467 00:44:45.579394
4468 00:44:45.582122 ----->DramcWriteLeveling(PI) begin...
4469 00:44:45.582595 ==
4470 00:44:45.585821 Dram Type= 6, Freq= 0, CH_1, rank 0
4471 00:44:45.589126 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4472 00:44:45.589719 ==
4473 00:44:45.592470 Write leveling (Byte 0): 30 => 30
4474 00:44:45.596209 Write leveling (Byte 1): 31 => 31
4475 00:44:45.598980 DramcWriteLeveling(PI) end<-----
4476 00:44:45.599449
4477 00:44:45.599818 ==
4478 00:44:45.602407 Dram Type= 6, Freq= 0, CH_1, rank 0
4479 00:44:45.605817 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4480 00:44:45.608794 ==
4481 00:44:45.609255 [Gating] SW mode calibration
4482 00:44:45.615920 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4483 00:44:45.622197 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4484 00:44:45.625515 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4485 00:44:45.632706 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4486 00:44:45.635831 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4487 00:44:45.638799 0 9 12 | B1->B0 | 2525 2525 | 1 0 | (1 0) (0 0)
4488 00:44:45.645722 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4489 00:44:45.649048 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4490 00:44:45.652599 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4491 00:44:45.659053 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4492 00:44:45.662285 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4493 00:44:45.665603 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4494 00:44:45.668756 0 10 8 | B1->B0 | 2929 2525 | 0 0 | (0 0) (0 0)
4495 00:44:45.675782 0 10 12 | B1->B0 | 4040 4242 | 0 0 | (0 0) (0 0)
4496 00:44:45.678840 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4497 00:44:45.682134 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4498 00:44:45.688808 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4499 00:44:45.692324 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4500 00:44:45.695326 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4501 00:44:45.702262 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4502 00:44:45.705238 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4503 00:44:45.708994 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4504 00:44:45.715426 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4505 00:44:45.718546 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4506 00:44:45.721993 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4507 00:44:45.728814 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4508 00:44:45.732105 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4509 00:44:45.735203 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4510 00:44:45.741844 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4511 00:44:45.745262 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4512 00:44:45.748534 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4513 00:44:45.755777 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4514 00:44:45.758516 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4515 00:44:45.761942 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4516 00:44:45.768865 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4517 00:44:45.771970 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4518 00:44:45.775315 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4519 00:44:45.781818 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4520 00:44:45.782324 Total UI for P1: 0, mck2ui 16
4521 00:44:45.785332 best dqsien dly found for B0: ( 0, 13, 8)
4522 00:44:45.788772 Total UI for P1: 0, mck2ui 16
4523 00:44:45.792369 best dqsien dly found for B1: ( 0, 13, 10)
4524 00:44:45.795369 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4525 00:44:45.801810 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4526 00:44:45.802285
4527 00:44:45.805222 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4528 00:44:45.808680 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4529 00:44:45.811841 [Gating] SW calibration Done
4530 00:44:45.812255 ==
4531 00:44:45.815156 Dram Type= 6, Freq= 0, CH_1, rank 0
4532 00:44:45.818898 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4533 00:44:45.819337 ==
4534 00:44:45.819709 RX Vref Scan: 0
4535 00:44:45.821767
4536 00:44:45.822235 RX Vref 0 -> 0, step: 1
4537 00:44:45.822610
4538 00:44:45.825337 RX Delay -230 -> 252, step: 16
4539 00:44:45.828722 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4540 00:44:45.835502 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4541 00:44:45.838729 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4542 00:44:45.841895 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4543 00:44:45.845471 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4544 00:44:45.848479 iDelay=218, Bit 5, Center 57 (-86 ~ 201) 288
4545 00:44:45.855659 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4546 00:44:45.858822 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4547 00:44:45.861939 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4548 00:44:45.865117 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4549 00:44:45.871867 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4550 00:44:45.875386 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4551 00:44:45.878435 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4552 00:44:45.882059 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4553 00:44:45.885257 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4554 00:44:45.891880 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4555 00:44:45.892348 ==
4556 00:44:45.894713 Dram Type= 6, Freq= 0, CH_1, rank 0
4557 00:44:45.898115 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4558 00:44:45.898580 ==
4559 00:44:45.901756 DQS Delay:
4560 00:44:45.902237 DQS0 = 0, DQS1 = 0
4561 00:44:45.902604 DQM Delay:
4562 00:44:45.904924 DQM0 = 50, DQM1 = 41
4563 00:44:45.905385 DQ Delay:
4564 00:44:45.908233 DQ0 =49, DQ1 =49, DQ2 =41, DQ3 =49
4565 00:44:45.912088 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49
4566 00:44:45.915205 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =41
4567 00:44:45.918175 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =41
4568 00:44:45.918644
4569 00:44:45.919009
4570 00:44:45.919344 ==
4571 00:44:45.921551 Dram Type= 6, Freq= 0, CH_1, rank 0
4572 00:44:45.924928 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4573 00:44:45.928409 ==
4574 00:44:45.929035
4575 00:44:45.929406
4576 00:44:45.929750 TX Vref Scan disable
4577 00:44:45.931616 == TX Byte 0 ==
4578 00:44:45.934464 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4579 00:44:45.941441 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4580 00:44:45.942010 == TX Byte 1 ==
4581 00:44:45.944646 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4582 00:44:45.951585 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4583 00:44:45.952159 ==
4584 00:44:45.954957 Dram Type= 6, Freq= 0, CH_1, rank 0
4585 00:44:45.957985 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4586 00:44:45.958570 ==
4587 00:44:45.958948
4588 00:44:45.959297
4589 00:44:45.961286 TX Vref Scan disable
4590 00:44:45.964810 == TX Byte 0 ==
4591 00:44:45.967977 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4592 00:44:45.971327 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4593 00:44:45.974419 == TX Byte 1 ==
4594 00:44:45.977695 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4595 00:44:45.981194 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4596 00:44:45.981756
4597 00:44:45.982128 [DATLAT]
4598 00:44:45.984462 Freq=600, CH1 RK0
4599 00:44:45.985051
4600 00:44:45.985427 DATLAT Default: 0x9
4601 00:44:45.988001 0, 0xFFFF, sum = 0
4602 00:44:45.991386 1, 0xFFFF, sum = 0
4603 00:44:45.991994 2, 0xFFFF, sum = 0
4604 00:44:45.994219 3, 0xFFFF, sum = 0
4605 00:44:45.994692 4, 0xFFFF, sum = 0
4606 00:44:45.997654 5, 0xFFFF, sum = 0
4607 00:44:45.998229 6, 0xFFFF, sum = 0
4608 00:44:46.001154 7, 0xFFFF, sum = 0
4609 00:44:46.001727 8, 0x0, sum = 1
4610 00:44:46.004419 9, 0x0, sum = 2
4611 00:44:46.004931 10, 0x0, sum = 3
4612 00:44:46.005310 11, 0x0, sum = 4
4613 00:44:46.008047 best_step = 9
4614 00:44:46.008819
4615 00:44:46.009225 ==
4616 00:44:46.010999 Dram Type= 6, Freq= 0, CH_1, rank 0
4617 00:44:46.014117 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4618 00:44:46.014583 ==
4619 00:44:46.017813 RX Vref Scan: 1
4620 00:44:46.018304
4621 00:44:46.018676 RX Vref 0 -> 0, step: 1
4622 00:44:46.019018
4623 00:44:46.021110 RX Delay -163 -> 252, step: 8
4624 00:44:46.021574
4625 00:44:46.024396 Set Vref, RX VrefLevel [Byte0]: 51
4626 00:44:46.027554 [Byte1]: 59
4627 00:44:46.032095
4628 00:44:46.032742 Final RX Vref Byte 0 = 51 to rank0
4629 00:44:46.035094 Final RX Vref Byte 1 = 59 to rank0
4630 00:44:46.038574 Final RX Vref Byte 0 = 51 to rank1
4631 00:44:46.041727 Final RX Vref Byte 1 = 59 to rank1==
4632 00:44:46.045566 Dram Type= 6, Freq= 0, CH_1, rank 0
4633 00:44:46.052121 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4634 00:44:46.052744 ==
4635 00:44:46.053135 DQS Delay:
4636 00:44:46.053489 DQS0 = 0, DQS1 = 0
4637 00:44:46.055585 DQM Delay:
4638 00:44:46.056160 DQM0 = 47, DQM1 = 40
4639 00:44:46.058480 DQ Delay:
4640 00:44:46.061752 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4641 00:44:46.062330 DQ4 =48, DQ5 =56, DQ6 =56, DQ7 =44
4642 00:44:46.064999 DQ8 =28, DQ9 =28, DQ10 =44, DQ11 =32
4643 00:44:46.068823 DQ12 =52, DQ13 =48, DQ14 =44, DQ15 =48
4644 00:44:46.071854
4645 00:44:46.072323
4646 00:44:46.078368 [DQSOSCAuto] RK0, (LSB)MR18= 0x5077, (MSB)MR19= 0x808, tDQSOscB0 = 387 ps tDQSOscB1 = 394 ps
4647 00:44:46.081979 CH1 RK0: MR19=808, MR18=5077
4648 00:44:46.088340 CH1_RK0: MR19=0x808, MR18=0x5077, DQSOSC=387, MR23=63, INC=175, DEC=116
4649 00:44:46.088942
4650 00:44:46.091778 ----->DramcWriteLeveling(PI) begin...
4651 00:44:46.092517 ==
4652 00:44:46.095065 Dram Type= 6, Freq= 0, CH_1, rank 1
4653 00:44:46.098223 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4654 00:44:46.098806 ==
4655 00:44:46.101674 Write leveling (Byte 0): 28 => 28
4656 00:44:46.104761 Write leveling (Byte 1): 29 => 29
4657 00:44:46.108144 DramcWriteLeveling(PI) end<-----
4658 00:44:46.108964
4659 00:44:46.109370 ==
4660 00:44:46.111507 Dram Type= 6, Freq= 0, CH_1, rank 1
4661 00:44:46.115282 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4662 00:44:46.115869 ==
4663 00:44:46.118418 [Gating] SW mode calibration
4664 00:44:46.125205 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4665 00:44:46.131561 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4666 00:44:46.134809 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4667 00:44:46.138136 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4668 00:44:46.144950 0 9 8 | B1->B0 | 3333 3434 | 1 1 | (1 0) (1 0)
4669 00:44:46.148535 0 9 12 | B1->B0 | 2828 3131 | 0 1 | (1 0) (0 0)
4670 00:44:46.152181 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4671 00:44:46.158257 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4672 00:44:46.161311 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4673 00:44:46.165095 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4674 00:44:46.171577 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4675 00:44:46.174880 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4676 00:44:46.178127 0 10 8 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
4677 00:44:46.185311 0 10 12 | B1->B0 | 3b3b 2d2d | 1 1 | (0 0) (0 0)
4678 00:44:46.188616 0 10 16 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
4679 00:44:46.191995 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4680 00:44:46.197820 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4681 00:44:46.201452 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4682 00:44:46.204871 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4683 00:44:46.211577 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4684 00:44:46.214683 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4685 00:44:46.218007 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4686 00:44:46.221616 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4687 00:44:46.228225 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4688 00:44:46.231544 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4689 00:44:46.235375 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4690 00:44:46.241707 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4691 00:44:46.244809 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4692 00:44:46.248260 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4693 00:44:46.254711 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4694 00:44:46.258379 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4695 00:44:46.262007 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4696 00:44:46.268924 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4697 00:44:46.271821 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4698 00:44:46.275053 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4699 00:44:46.282084 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4700 00:44:46.285142 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4701 00:44:46.288534 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4702 00:44:46.292075 Total UI for P1: 0, mck2ui 16
4703 00:44:46.295074 best dqsien dly found for B0: ( 0, 13, 10)
4704 00:44:46.298155 Total UI for P1: 0, mck2ui 16
4705 00:44:46.301709 best dqsien dly found for B1: ( 0, 13, 10)
4706 00:44:46.304833 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4707 00:44:46.308405 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4708 00:44:46.309018
4709 00:44:46.314924 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4710 00:44:46.317831 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4711 00:44:46.318368 [Gating] SW calibration Done
4712 00:44:46.321308 ==
4713 00:44:46.324802 Dram Type= 6, Freq= 0, CH_1, rank 1
4714 00:44:46.328605 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4715 00:44:46.329181 ==
4716 00:44:46.329557 RX Vref Scan: 0
4717 00:44:46.329907
4718 00:44:46.331014 RX Vref 0 -> 0, step: 1
4719 00:44:46.331483
4720 00:44:46.334832 RX Delay -230 -> 252, step: 16
4721 00:44:46.337931 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4722 00:44:46.341145 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4723 00:44:46.348111 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4724 00:44:46.351072 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4725 00:44:46.354580 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4726 00:44:46.357867 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4727 00:44:46.361501 iDelay=218, Bit 6, Center 57 (-86 ~ 201) 288
4728 00:44:46.367782 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4729 00:44:46.371061 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4730 00:44:46.374635 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4731 00:44:46.377828 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4732 00:44:46.384524 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4733 00:44:46.388048 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4734 00:44:46.390840 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4735 00:44:46.394262 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4736 00:44:46.400854 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4737 00:44:46.401446 ==
4738 00:44:46.404080 Dram Type= 6, Freq= 0, CH_1, rank 1
4739 00:44:46.407486 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4740 00:44:46.408056 ==
4741 00:44:46.408430 DQS Delay:
4742 00:44:46.411161 DQS0 = 0, DQS1 = 0
4743 00:44:46.411726 DQM Delay:
4744 00:44:46.414491 DQM0 = 51, DQM1 = 45
4745 00:44:46.415069 DQ Delay:
4746 00:44:46.417237 DQ0 =57, DQ1 =49, DQ2 =33, DQ3 =49
4747 00:44:46.421048 DQ4 =49, DQ5 =65, DQ6 =57, DQ7 =49
4748 00:44:46.424300 DQ8 =25, DQ9 =33, DQ10 =41, DQ11 =41
4749 00:44:46.427446 DQ12 =57, DQ13 =57, DQ14 =49, DQ15 =57
4750 00:44:46.428012
4751 00:44:46.428381
4752 00:44:46.428806 ==
4753 00:44:46.430521 Dram Type= 6, Freq= 0, CH_1, rank 1
4754 00:44:46.433933 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4755 00:44:46.437425 ==
4756 00:44:46.437995
4757 00:44:46.438367
4758 00:44:46.438713 TX Vref Scan disable
4759 00:44:46.440157 == TX Byte 0 ==
4760 00:44:46.444060 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4761 00:44:46.447187 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4762 00:44:46.450482 == TX Byte 1 ==
4763 00:44:46.453948 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4764 00:44:46.456768 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4765 00:44:46.460468 ==
4766 00:44:46.463724 Dram Type= 6, Freq= 0, CH_1, rank 1
4767 00:44:46.467029 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4768 00:44:46.467501 ==
4769 00:44:46.467870
4770 00:44:46.468209
4771 00:44:46.470149 TX Vref Scan disable
4772 00:44:46.470610 == TX Byte 0 ==
4773 00:44:46.476926 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4774 00:44:46.480592 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4775 00:44:46.481159 == TX Byte 1 ==
4776 00:44:46.486969 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4777 00:44:46.490461 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4778 00:44:46.491029
4779 00:44:46.491397 [DATLAT]
4780 00:44:46.493216 Freq=600, CH1 RK1
4781 00:44:46.493681
4782 00:44:46.494043 DATLAT Default: 0x9
4783 00:44:46.496910 0, 0xFFFF, sum = 0
4784 00:44:46.497485 1, 0xFFFF, sum = 0
4785 00:44:46.500377 2, 0xFFFF, sum = 0
4786 00:44:46.500999 3, 0xFFFF, sum = 0
4787 00:44:46.503200 4, 0xFFFF, sum = 0
4788 00:44:46.503669 5, 0xFFFF, sum = 0
4789 00:44:46.506826 6, 0xFFFF, sum = 0
4790 00:44:46.510228 7, 0xFFFF, sum = 0
4791 00:44:46.510700 8, 0x0, sum = 1
4792 00:44:46.511076 9, 0x0, sum = 2
4793 00:44:46.513178 10, 0x0, sum = 3
4794 00:44:46.513650 11, 0x0, sum = 4
4795 00:44:46.516771 best_step = 9
4796 00:44:46.517233
4797 00:44:46.517598 ==
4798 00:44:46.519936 Dram Type= 6, Freq= 0, CH_1, rank 1
4799 00:44:46.523452 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4800 00:44:46.524021 ==
4801 00:44:46.526642 RX Vref Scan: 0
4802 00:44:46.527103
4803 00:44:46.527467 RX Vref 0 -> 0, step: 1
4804 00:44:46.527811
4805 00:44:46.529545 RX Delay -179 -> 252, step: 8
4806 00:44:46.537073 iDelay=205, Bit 0, Center 56 (-83 ~ 196) 280
4807 00:44:46.540670 iDelay=205, Bit 1, Center 40 (-99 ~ 180) 280
4808 00:44:46.544024 iDelay=205, Bit 2, Center 40 (-99 ~ 180) 280
4809 00:44:46.547103 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4810 00:44:46.550076 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4811 00:44:46.557088 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4812 00:44:46.560185 iDelay=205, Bit 6, Center 56 (-83 ~ 196) 280
4813 00:44:46.563474 iDelay=205, Bit 7, Center 48 (-91 ~ 188) 280
4814 00:44:46.566941 iDelay=205, Bit 8, Center 24 (-123 ~ 172) 296
4815 00:44:46.573534 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4816 00:44:46.576816 iDelay=205, Bit 10, Center 44 (-99 ~ 188) 288
4817 00:44:46.580222 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4818 00:44:46.583348 iDelay=205, Bit 12, Center 52 (-99 ~ 204) 304
4819 00:44:46.586972 iDelay=205, Bit 13, Center 48 (-99 ~ 196) 296
4820 00:44:46.593760 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4821 00:44:46.596925 iDelay=205, Bit 15, Center 52 (-99 ~ 204) 304
4822 00:44:46.597392 ==
4823 00:44:46.599988 Dram Type= 6, Freq= 0, CH_1, rank 1
4824 00:44:46.603568 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4825 00:44:46.604140 ==
4826 00:44:46.606786 DQS Delay:
4827 00:44:46.607250 DQS0 = 0, DQS1 = 0
4828 00:44:46.607618 DQM Delay:
4829 00:44:46.609864 DQM0 = 49, DQM1 = 42
4830 00:44:46.610328 DQ Delay:
4831 00:44:46.613538 DQ0 =56, DQ1 =40, DQ2 =40, DQ3 =44
4832 00:44:46.616528 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4833 00:44:46.619891 DQ8 =24, DQ9 =32, DQ10 =44, DQ11 =40
4834 00:44:46.623606 DQ12 =52, DQ13 =48, DQ14 =48, DQ15 =52
4835 00:44:46.624173
4836 00:44:46.624542
4837 00:44:46.633299 [DQSOSCAuto] RK1, (LSB)MR18= 0x5a21, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 392 ps
4838 00:44:46.633868 CH1 RK1: MR19=808, MR18=5A21
4839 00:44:46.640098 CH1_RK1: MR19=0x808, MR18=0x5A21, DQSOSC=392, MR23=63, INC=170, DEC=113
4840 00:44:46.643849 [RxdqsGatingPostProcess] freq 600
4841 00:44:46.649957 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4842 00:44:46.653433 Pre-setting of DQS Precalculation
4843 00:44:46.657278 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4844 00:44:46.663441 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4845 00:44:46.673464 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4846 00:44:46.674017
4847 00:44:46.674385
4848 00:44:46.676769 [Calibration Summary] 1200 Mbps
4849 00:44:46.677235 CH 0, Rank 0
4850 00:44:46.679821 SW Impedance : PASS
4851 00:44:46.680287 DUTY Scan : NO K
4852 00:44:46.683496 ZQ Calibration : PASS
4853 00:44:46.683959 Jitter Meter : NO K
4854 00:44:46.686638 CBT Training : PASS
4855 00:44:46.689805 Write leveling : PASS
4856 00:44:46.690291 RX DQS gating : PASS
4857 00:44:46.693469 RX DQ/DQS(RDDQC) : PASS
4858 00:44:46.696834 TX DQ/DQS : PASS
4859 00:44:46.697302 RX DATLAT : PASS
4860 00:44:46.700034 RX DQ/DQS(Engine): PASS
4861 00:44:46.703576 TX OE : NO K
4862 00:44:46.704370 All Pass.
4863 00:44:46.704824
4864 00:44:46.705183 CH 0, Rank 1
4865 00:44:46.706775 SW Impedance : PASS
4866 00:44:46.709793 DUTY Scan : NO K
4867 00:44:46.710258 ZQ Calibration : PASS
4868 00:44:46.713249 Jitter Meter : NO K
4869 00:44:46.716632 CBT Training : PASS
4870 00:44:46.717104 Write leveling : PASS
4871 00:44:46.719995 RX DQS gating : PASS
4872 00:44:46.723775 RX DQ/DQS(RDDQC) : PASS
4873 00:44:46.724340 TX DQ/DQS : PASS
4874 00:44:46.726839 RX DATLAT : PASS
4875 00:44:46.727405 RX DQ/DQS(Engine): PASS
4876 00:44:46.730037 TX OE : NO K
4877 00:44:46.730610 All Pass.
4878 00:44:46.730977
4879 00:44:46.733223 CH 1, Rank 0
4880 00:44:46.733687 SW Impedance : PASS
4881 00:44:46.736847 DUTY Scan : NO K
4882 00:44:46.740258 ZQ Calibration : PASS
4883 00:44:46.740896 Jitter Meter : NO K
4884 00:44:46.743350 CBT Training : PASS
4885 00:44:46.746587 Write leveling : PASS
4886 00:44:46.747050 RX DQS gating : PASS
4887 00:44:46.750017 RX DQ/DQS(RDDQC) : PASS
4888 00:44:46.753532 TX DQ/DQS : PASS
4889 00:44:46.754104 RX DATLAT : PASS
4890 00:44:46.757058 RX DQ/DQS(Engine): PASS
4891 00:44:46.760698 TX OE : NO K
4892 00:44:46.761255 All Pass.
4893 00:44:46.761621
4894 00:44:46.761970 CH 1, Rank 1
4895 00:44:46.764043 SW Impedance : PASS
4896 00:44:46.766839 DUTY Scan : NO K
4897 00:44:46.767306 ZQ Calibration : PASS
4898 00:44:46.769898 Jitter Meter : NO K
4899 00:44:46.770382 CBT Training : PASS
4900 00:44:46.773350 Write leveling : PASS
4901 00:44:46.776778 RX DQS gating : PASS
4902 00:44:46.777240 RX DQ/DQS(RDDQC) : PASS
4903 00:44:46.779746 TX DQ/DQS : PASS
4904 00:44:46.783471 RX DATLAT : PASS
4905 00:44:46.784040 RX DQ/DQS(Engine): PASS
4906 00:44:46.786863 TX OE : NO K
4907 00:44:46.787330 All Pass.
4908 00:44:46.787700
4909 00:44:46.789863 DramC Write-DBI off
4910 00:44:46.793261 PER_BANK_REFRESH: Hybrid Mode
4911 00:44:46.793824 TX_TRACKING: ON
4912 00:44:46.803548 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4913 00:44:46.806845 [FAST_K] Save calibration result to emmc
4914 00:44:46.809742 dramc_set_vcore_voltage set vcore to 662500
4915 00:44:46.813228 Read voltage for 933, 3
4916 00:44:46.813720 Vio18 = 0
4917 00:44:46.814257 Vcore = 662500
4918 00:44:46.816656 Vdram = 0
4919 00:44:46.817117 Vddq = 0
4920 00:44:46.817483 Vmddr = 0
4921 00:44:46.823308 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4922 00:44:46.826521 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4923 00:44:46.830068 MEM_TYPE=3, freq_sel=17
4924 00:44:46.833496 sv_algorithm_assistance_LP4_1600
4925 00:44:46.836678 ============ PULL DRAM RESETB DOWN ============
4926 00:44:46.840357 ========== PULL DRAM RESETB DOWN end =========
4927 00:44:46.846469 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4928 00:44:46.849915 ===================================
4929 00:44:46.852994 LPDDR4 DRAM CONFIGURATION
4930 00:44:46.853461 ===================================
4931 00:44:46.856199 EX_ROW_EN[0] = 0x0
4932 00:44:46.860050 EX_ROW_EN[1] = 0x0
4933 00:44:46.860674 LP4Y_EN = 0x0
4934 00:44:46.863478 WORK_FSP = 0x0
4935 00:44:46.864042 WL = 0x3
4936 00:44:46.866574 RL = 0x3
4937 00:44:46.867044 BL = 0x2
4938 00:44:46.869867 RPST = 0x0
4939 00:44:46.870331 RD_PRE = 0x0
4940 00:44:46.873350 WR_PRE = 0x1
4941 00:44:46.873827 WR_PST = 0x0
4942 00:44:46.876339 DBI_WR = 0x0
4943 00:44:46.876830 DBI_RD = 0x0
4944 00:44:46.879719 OTF = 0x1
4945 00:44:46.883050 ===================================
4946 00:44:46.886167 ===================================
4947 00:44:46.886633 ANA top config
4948 00:44:46.889895 ===================================
4949 00:44:46.893447 DLL_ASYNC_EN = 0
4950 00:44:46.896521 ALL_SLAVE_EN = 1
4951 00:44:46.899955 NEW_RANK_MODE = 1
4952 00:44:46.900525 DLL_IDLE_MODE = 1
4953 00:44:46.903673 LP45_APHY_COMB_EN = 1
4954 00:44:46.906292 TX_ODT_DIS = 1
4955 00:44:46.909860 NEW_8X_MODE = 1
4956 00:44:46.913374 ===================================
4957 00:44:46.916779 ===================================
4958 00:44:46.917337 data_rate = 1866
4959 00:44:46.920069 CKR = 1
4960 00:44:46.923793 DQ_P2S_RATIO = 8
4961 00:44:46.926648 ===================================
4962 00:44:46.930000 CA_P2S_RATIO = 8
4963 00:44:46.933211 DQ_CA_OPEN = 0
4964 00:44:46.936805 DQ_SEMI_OPEN = 0
4965 00:44:46.937371 CA_SEMI_OPEN = 0
4966 00:44:46.940278 CA_FULL_RATE = 0
4967 00:44:46.943755 DQ_CKDIV4_EN = 1
4968 00:44:46.947070 CA_CKDIV4_EN = 1
4969 00:44:46.949952 CA_PREDIV_EN = 0
4970 00:44:46.953109 PH8_DLY = 0
4971 00:44:46.953571 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4972 00:44:46.956413 DQ_AAMCK_DIV = 4
4973 00:44:46.960016 CA_AAMCK_DIV = 4
4974 00:44:46.963494 CA_ADMCK_DIV = 4
4975 00:44:46.966619 DQ_TRACK_CA_EN = 0
4976 00:44:46.969754 CA_PICK = 933
4977 00:44:46.973010 CA_MCKIO = 933
4978 00:44:46.973580 MCKIO_SEMI = 0
4979 00:44:46.976304 PLL_FREQ = 3732
4980 00:44:46.979789 DQ_UI_PI_RATIO = 32
4981 00:44:46.983317 CA_UI_PI_RATIO = 0
4982 00:44:46.986493 ===================================
4983 00:44:46.989631 ===================================
4984 00:44:46.992849 memory_type:LPDDR4
4985 00:44:46.993412 GP_NUM : 10
4986 00:44:46.996429 SRAM_EN : 1
4987 00:44:46.996955 MD32_EN : 0
4988 00:44:46.999448 ===================================
4989 00:44:47.002979 [ANA_INIT] >>>>>>>>>>>>>>
4990 00:44:47.005994 <<<<<< [CONFIGURE PHASE]: ANA_TX
4991 00:44:47.009490 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4992 00:44:47.013319 ===================================
4993 00:44:47.016157 data_rate = 1866,PCW = 0X8f00
4994 00:44:47.019731 ===================================
4995 00:44:47.023206 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4996 00:44:47.029369 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4997 00:44:47.032533 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4998 00:44:47.039576 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4999 00:44:47.043022 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5000 00:44:47.046357 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5001 00:44:47.046927 [ANA_INIT] flow start
5002 00:44:47.049672 [ANA_INIT] PLL >>>>>>>>
5003 00:44:47.053346 [ANA_INIT] PLL <<<<<<<<
5004 00:44:47.053912 [ANA_INIT] MIDPI >>>>>>>>
5005 00:44:47.056090 [ANA_INIT] MIDPI <<<<<<<<
5006 00:44:47.059532 [ANA_INIT] DLL >>>>>>>>
5007 00:44:47.060120 [ANA_INIT] flow end
5008 00:44:47.065936 ============ LP4 DIFF to SE enter ============
5009 00:44:47.069442 ============ LP4 DIFF to SE exit ============
5010 00:44:47.072719 [ANA_INIT] <<<<<<<<<<<<<
5011 00:44:47.076018 [Flow] Enable top DCM control >>>>>
5012 00:44:47.079353 [Flow] Enable top DCM control <<<<<
5013 00:44:47.079817 Enable DLL master slave shuffle
5014 00:44:47.086512 ==============================================================
5015 00:44:47.089382 Gating Mode config
5016 00:44:47.092886 ==============================================================
5017 00:44:47.095940 Config description:
5018 00:44:47.106111 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5019 00:44:47.112685 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5020 00:44:47.115779 SELPH_MODE 0: By rank 1: By Phase
5021 00:44:47.122529 ==============================================================
5022 00:44:47.125672 GAT_TRACK_EN = 1
5023 00:44:47.129011 RX_GATING_MODE = 2
5024 00:44:47.131974 RX_GATING_TRACK_MODE = 2
5025 00:44:47.132056 SELPH_MODE = 1
5026 00:44:47.135253 PICG_EARLY_EN = 1
5027 00:44:47.138818 VALID_LAT_VALUE = 1
5028 00:44:47.145407 ==============================================================
5029 00:44:47.148684 Enter into Gating configuration >>>>
5030 00:44:47.152058 Exit from Gating configuration <<<<
5031 00:44:47.155583 Enter into DVFS_PRE_config >>>>>
5032 00:44:47.165596 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5033 00:44:47.168551 Exit from DVFS_PRE_config <<<<<
5034 00:44:47.172182 Enter into PICG configuration >>>>
5035 00:44:47.175571 Exit from PICG configuration <<<<
5036 00:44:47.179197 [RX_INPUT] configuration >>>>>
5037 00:44:47.182374 [RX_INPUT] configuration <<<<<
5038 00:44:47.185734 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5039 00:44:47.192621 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5040 00:44:47.198887 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5041 00:44:47.205398 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5042 00:44:47.208934 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5043 00:44:47.215652 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5044 00:44:47.218751 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5045 00:44:47.225569 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5046 00:44:47.229153 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5047 00:44:47.232643 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5048 00:44:47.235972 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5049 00:44:47.242394 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5050 00:44:47.245955 ===================================
5051 00:44:47.246524 LPDDR4 DRAM CONFIGURATION
5052 00:44:47.249384 ===================================
5053 00:44:47.252330 EX_ROW_EN[0] = 0x0
5054 00:44:47.255504 EX_ROW_EN[1] = 0x0
5055 00:44:47.256064 LP4Y_EN = 0x0
5056 00:44:47.259316 WORK_FSP = 0x0
5057 00:44:47.259881 WL = 0x3
5058 00:44:47.262626 RL = 0x3
5059 00:44:47.263189 BL = 0x2
5060 00:44:47.265773 RPST = 0x0
5061 00:44:47.266234 RD_PRE = 0x0
5062 00:44:47.268644 WR_PRE = 0x1
5063 00:44:47.269108 WR_PST = 0x0
5064 00:44:47.272277 DBI_WR = 0x0
5065 00:44:47.272772 DBI_RD = 0x0
5066 00:44:47.275676 OTF = 0x1
5067 00:44:47.278750 ===================================
5068 00:44:47.282551 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5069 00:44:47.285827 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5070 00:44:47.292594 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5071 00:44:47.295626 ===================================
5072 00:44:47.296194 LPDDR4 DRAM CONFIGURATION
5073 00:44:47.299039 ===================================
5074 00:44:47.302427 EX_ROW_EN[0] = 0x10
5075 00:44:47.305252 EX_ROW_EN[1] = 0x0
5076 00:44:47.305715 LP4Y_EN = 0x0
5077 00:44:47.308579 WORK_FSP = 0x0
5078 00:44:47.309048 WL = 0x3
5079 00:44:47.312106 RL = 0x3
5080 00:44:47.312703 BL = 0x2
5081 00:44:47.315131 RPST = 0x0
5082 00:44:47.315596 RD_PRE = 0x0
5083 00:44:47.318563 WR_PRE = 0x1
5084 00:44:47.319024 WR_PST = 0x0
5085 00:44:47.321756 DBI_WR = 0x0
5086 00:44:47.322240 DBI_RD = 0x0
5087 00:44:47.325251 OTF = 0x1
5088 00:44:47.328895 ===================================
5089 00:44:47.335071 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5090 00:44:47.338957 nWR fixed to 30
5091 00:44:47.339486 [ModeRegInit_LP4] CH0 RK0
5092 00:44:47.342233 [ModeRegInit_LP4] CH0 RK1
5093 00:44:47.345363 [ModeRegInit_LP4] CH1 RK0
5094 00:44:47.348664 [ModeRegInit_LP4] CH1 RK1
5095 00:44:47.349186 match AC timing 9
5096 00:44:47.352103 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5097 00:44:47.358830 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5098 00:44:47.362262 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5099 00:44:47.368742 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5100 00:44:47.372317 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5101 00:44:47.372912 ==
5102 00:44:47.375420 Dram Type= 6, Freq= 0, CH_0, rank 0
5103 00:44:47.378582 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5104 00:44:47.379048 ==
5105 00:44:47.385462 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5106 00:44:47.392087 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5107 00:44:47.395554 [CA 0] Center 37 (7~68) winsize 62
5108 00:44:47.398269 [CA 1] Center 38 (8~69) winsize 62
5109 00:44:47.401971 [CA 2] Center 35 (5~66) winsize 62
5110 00:44:47.405262 [CA 3] Center 35 (5~65) winsize 61
5111 00:44:47.408652 [CA 4] Center 34 (4~65) winsize 62
5112 00:44:47.409113 [CA 5] Center 33 (3~64) winsize 62
5113 00:44:47.411826
5114 00:44:47.414948 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5115 00:44:47.415524
5116 00:44:47.418382 [CATrainingPosCal] consider 1 rank data
5117 00:44:47.421775 u2DelayCellTimex100 = 270/100 ps
5118 00:44:47.424843 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5119 00:44:47.428480 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5120 00:44:47.431804 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5121 00:44:47.434735 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5122 00:44:47.438267 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5123 00:44:47.441809 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5124 00:44:47.442386
5125 00:44:47.448805 CA PerBit enable=1, Macro0, CA PI delay=33
5126 00:44:47.449369
5127 00:44:47.449741 [CBTSetCACLKResult] CA Dly = 33
5128 00:44:47.451751 CS Dly: 7 (0~38)
5129 00:44:47.452334 ==
5130 00:44:47.454994 Dram Type= 6, Freq= 0, CH_0, rank 1
5131 00:44:47.458184 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5132 00:44:47.458655 ==
5133 00:44:47.464849 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5134 00:44:47.471361 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5135 00:44:47.474707 [CA 0] Center 38 (8~69) winsize 62
5136 00:44:47.478055 [CA 1] Center 38 (8~69) winsize 62
5137 00:44:47.481279 [CA 2] Center 36 (6~66) winsize 61
5138 00:44:47.484950 [CA 3] Center 35 (5~66) winsize 62
5139 00:44:47.488509 [CA 4] Center 34 (4~65) winsize 62
5140 00:44:47.491747 [CA 5] Center 34 (4~65) winsize 62
5141 00:44:47.492310
5142 00:44:47.494732 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5143 00:44:47.495301
5144 00:44:47.497811 [CATrainingPosCal] consider 2 rank data
5145 00:44:47.501208 u2DelayCellTimex100 = 270/100 ps
5146 00:44:47.504956 CA0 delay=38 (8~68),Diff = 4 PI (24 cell)
5147 00:44:47.507749 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5148 00:44:47.511176 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5149 00:44:47.514689 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5150 00:44:47.517597 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5151 00:44:47.521207 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5152 00:44:47.521646
5153 00:44:47.527696 CA PerBit enable=1, Macro0, CA PI delay=34
5154 00:44:47.528119
5155 00:44:47.531072 [CBTSetCACLKResult] CA Dly = 34
5156 00:44:47.531495 CS Dly: 7 (0~39)
5157 00:44:47.531827
5158 00:44:47.534488 ----->DramcWriteLeveling(PI) begin...
5159 00:44:47.534914 ==
5160 00:44:47.537998 Dram Type= 6, Freq= 0, CH_0, rank 0
5161 00:44:47.541283 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5162 00:44:47.544370 ==
5163 00:44:47.544840 Write leveling (Byte 0): 30 => 30
5164 00:44:47.547574 Write leveling (Byte 1): 28 => 28
5165 00:44:47.550890 DramcWriteLeveling(PI) end<-----
5166 00:44:47.551309
5167 00:44:47.551639 ==
5168 00:44:47.554531 Dram Type= 6, Freq= 0, CH_0, rank 0
5169 00:44:47.560892 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5170 00:44:47.561195 ==
5171 00:44:47.561435 [Gating] SW mode calibration
5172 00:44:47.570949 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5173 00:44:47.574433 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5174 00:44:47.577679 0 14 0 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
5175 00:44:47.583906 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5176 00:44:47.587215 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5177 00:44:47.590983 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5178 00:44:47.597792 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5179 00:44:47.601050 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5180 00:44:47.604443 0 14 24 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
5181 00:44:47.610784 0 14 28 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
5182 00:44:47.614329 0 15 0 | B1->B0 | 2626 2323 | 0 0 | (1 0) (1 0)
5183 00:44:47.617676 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5184 00:44:47.624268 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5185 00:44:47.627704 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5186 00:44:47.630677 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5187 00:44:47.637565 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5188 00:44:47.640741 0 15 24 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
5189 00:44:47.643935 0 15 28 | B1->B0 | 2e2d 4646 | 1 0 | (0 0) (0 0)
5190 00:44:47.651003 1 0 0 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
5191 00:44:47.654065 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5192 00:44:47.657539 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5193 00:44:47.664163 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5194 00:44:47.667598 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5195 00:44:47.670659 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5196 00:44:47.674167 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5197 00:44:47.680648 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5198 00:44:47.684400 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5199 00:44:47.687513 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5200 00:44:47.694844 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5201 00:44:47.697778 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5202 00:44:47.701203 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5203 00:44:47.707972 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5204 00:44:47.710632 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5205 00:44:47.714286 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5206 00:44:47.721205 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5207 00:44:47.724530 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5208 00:44:47.727909 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5209 00:44:47.734031 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5210 00:44:47.737247 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5211 00:44:47.741182 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5212 00:44:47.747583 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5213 00:44:47.751157 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
5214 00:44:47.754507 Total UI for P1: 0, mck2ui 16
5215 00:44:47.757352 best dqsien dly found for B0: ( 1, 2, 26)
5216 00:44:47.761007 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5217 00:44:47.764099 Total UI for P1: 0, mck2ui 16
5218 00:44:47.767281 best dqsien dly found for B1: ( 1, 2, 30)
5219 00:44:47.770449 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5220 00:44:47.773868 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5221 00:44:47.774334
5222 00:44:47.780701 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5223 00:44:47.784102 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5224 00:44:47.784714 [Gating] SW calibration Done
5225 00:44:47.787641 ==
5226 00:44:47.788206 Dram Type= 6, Freq= 0, CH_0, rank 0
5227 00:44:47.793922 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5228 00:44:47.794495 ==
5229 00:44:47.794866 RX Vref Scan: 0
5230 00:44:47.795211
5231 00:44:47.797436 RX Vref 0 -> 0, step: 1
5232 00:44:47.797900
5233 00:44:47.800710 RX Delay -80 -> 252, step: 8
5234 00:44:47.803718 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5235 00:44:47.807433 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5236 00:44:47.810310 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5237 00:44:47.817220 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5238 00:44:47.820442 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5239 00:44:47.823897 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5240 00:44:47.827384 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5241 00:44:47.830097 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5242 00:44:47.833476 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5243 00:44:47.840233 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5244 00:44:47.843864 iDelay=208, Bit 10, Center 87 (0 ~ 175) 176
5245 00:44:47.847296 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5246 00:44:47.850250 iDelay=208, Bit 12, Center 91 (0 ~ 183) 184
5247 00:44:47.853441 iDelay=208, Bit 13, Center 87 (0 ~ 175) 176
5248 00:44:47.860329 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5249 00:44:47.864028 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5250 00:44:47.864633 ==
5251 00:44:47.866584 Dram Type= 6, Freq= 0, CH_0, rank 0
5252 00:44:47.870198 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5253 00:44:47.870773 ==
5254 00:44:47.871147 DQS Delay:
5255 00:44:47.873493 DQS0 = 0, DQS1 = 0
5256 00:44:47.873957 DQM Delay:
5257 00:44:47.876807 DQM0 = 105, DQM1 = 89
5258 00:44:47.877289 DQ Delay:
5259 00:44:47.880446 DQ0 =107, DQ1 =107, DQ2 =99, DQ3 =99
5260 00:44:47.883592 DQ4 =107, DQ5 =95, DQ6 =115, DQ7 =115
5261 00:44:47.886787 DQ8 =83, DQ9 =79, DQ10 =87, DQ11 =87
5262 00:44:47.889877 DQ12 =91, DQ13 =87, DQ14 =103, DQ15 =99
5263 00:44:47.890342
5264 00:44:47.890708
5265 00:44:47.891051 ==
5266 00:44:47.893367 Dram Type= 6, Freq= 0, CH_0, rank 0
5267 00:44:47.899909 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5268 00:44:47.900482 ==
5269 00:44:47.900881
5270 00:44:47.901225
5271 00:44:47.901549 TX Vref Scan disable
5272 00:44:47.903682 == TX Byte 0 ==
5273 00:44:47.907169 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5274 00:44:47.910315 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5275 00:44:47.913680 == TX Byte 1 ==
5276 00:44:47.917231 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5277 00:44:47.920350 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5278 00:44:47.923784 ==
5279 00:44:47.927266 Dram Type= 6, Freq= 0, CH_0, rank 0
5280 00:44:47.930616 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5281 00:44:47.931185 ==
5282 00:44:47.931555
5283 00:44:47.931893
5284 00:44:47.933405 TX Vref Scan disable
5285 00:44:47.933869 == TX Byte 0 ==
5286 00:44:47.940178 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5287 00:44:47.943730 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5288 00:44:47.944299 == TX Byte 1 ==
5289 00:44:47.950112 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5290 00:44:47.953418 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5291 00:44:47.953986
5292 00:44:47.954353 [DATLAT]
5293 00:44:47.957114 Freq=933, CH0 RK0
5294 00:44:47.957702
5295 00:44:47.958072 DATLAT Default: 0xd
5296 00:44:47.960013 0, 0xFFFF, sum = 0
5297 00:44:47.960602 1, 0xFFFF, sum = 0
5298 00:44:47.963402 2, 0xFFFF, sum = 0
5299 00:44:47.963976 3, 0xFFFF, sum = 0
5300 00:44:47.966813 4, 0xFFFF, sum = 0
5301 00:44:47.967392 5, 0xFFFF, sum = 0
5302 00:44:47.969994 6, 0xFFFF, sum = 0
5303 00:44:47.970570 7, 0xFFFF, sum = 0
5304 00:44:47.973297 8, 0xFFFF, sum = 0
5305 00:44:47.976464 9, 0xFFFF, sum = 0
5306 00:44:47.976967 10, 0x0, sum = 1
5307 00:44:47.979970 11, 0x0, sum = 2
5308 00:44:47.980595 12, 0x0, sum = 3
5309 00:44:47.980987 13, 0x0, sum = 4
5310 00:44:47.983587 best_step = 11
5311 00:44:47.984160
5312 00:44:47.984534 ==
5313 00:44:47.986353 Dram Type= 6, Freq= 0, CH_0, rank 0
5314 00:44:47.990161 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5315 00:44:47.990742 ==
5316 00:44:47.992993 RX Vref Scan: 1
5317 00:44:47.993454
5318 00:44:47.993819 RX Vref 0 -> 0, step: 1
5319 00:44:47.996529
5320 00:44:47.997107 RX Delay -53 -> 252, step: 4
5321 00:44:47.997549
5322 00:44:48.000004 Set Vref, RX VrefLevel [Byte0]: 59
5323 00:44:48.003125 [Byte1]: 50
5324 00:44:48.007554
5325 00:44:48.008019 Final RX Vref Byte 0 = 59 to rank0
5326 00:44:48.010924 Final RX Vref Byte 1 = 50 to rank0
5327 00:44:48.014152 Final RX Vref Byte 0 = 59 to rank1
5328 00:44:48.017889 Final RX Vref Byte 1 = 50 to rank1==
5329 00:44:48.021227 Dram Type= 6, Freq= 0, CH_0, rank 0
5330 00:44:48.027653 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5331 00:44:48.028223 ==
5332 00:44:48.028633 DQS Delay:
5333 00:44:48.028993 DQS0 = 0, DQS1 = 0
5334 00:44:48.030989 DQM Delay:
5335 00:44:48.031553 DQM0 = 107, DQM1 = 92
5336 00:44:48.033998 DQ Delay:
5337 00:44:48.037460 DQ0 =108, DQ1 =106, DQ2 =102, DQ3 =106
5338 00:44:48.040984 DQ4 =108, DQ5 =98, DQ6 =116, DQ7 =114
5339 00:44:48.043868 DQ8 =84, DQ9 =78, DQ10 =92, DQ11 =90
5340 00:44:48.047425 DQ12 =96, DQ13 =94, DQ14 =104, DQ15 =98
5341 00:44:48.047993
5342 00:44:48.048362
5343 00:44:48.054294 [DQSOSCAuto] RK0, (LSB)MR18= 0x2420, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 410 ps
5344 00:44:48.057182 CH0 RK0: MR19=505, MR18=2420
5345 00:44:48.064380 CH0_RK0: MR19=0x505, MR18=0x2420, DQSOSC=410, MR23=63, INC=64, DEC=42
5346 00:44:48.064991
5347 00:44:48.067304 ----->DramcWriteLeveling(PI) begin...
5348 00:44:48.067878 ==
5349 00:44:48.070392 Dram Type= 6, Freq= 0, CH_0, rank 1
5350 00:44:48.073784 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5351 00:44:48.074360 ==
5352 00:44:48.077217 Write leveling (Byte 0): 34 => 34
5353 00:44:48.080757 Write leveling (Byte 1): 29 => 29
5354 00:44:48.083962 DramcWriteLeveling(PI) end<-----
5355 00:44:48.084538
5356 00:44:48.084965 ==
5357 00:44:48.087062 Dram Type= 6, Freq= 0, CH_0, rank 1
5358 00:44:48.090254 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5359 00:44:48.093909 ==
5360 00:44:48.094487 [Gating] SW mode calibration
5361 00:44:48.103539 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5362 00:44:48.107041 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5363 00:44:48.110356 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5364 00:44:48.117078 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5365 00:44:48.120338 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5366 00:44:48.123997 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5367 00:44:48.130259 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5368 00:44:48.134125 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5369 00:44:48.137172 0 14 24 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
5370 00:44:48.143751 0 14 28 | B1->B0 | 2d2d 2525 | 0 0 | (1 0) (0 1)
5371 00:44:48.147362 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
5372 00:44:48.150660 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5373 00:44:48.157105 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5374 00:44:48.160468 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5375 00:44:48.163554 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5376 00:44:48.170202 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5377 00:44:48.173610 0 15 24 | B1->B0 | 2727 2d2d | 0 1 | (0 0) (0 0)
5378 00:44:48.176968 0 15 28 | B1->B0 | 3b3b 4343 | 1 0 | (0 0) (0 0)
5379 00:44:48.180104 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5380 00:44:48.186779 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5381 00:44:48.190267 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5382 00:44:48.193542 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5383 00:44:48.200306 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5384 00:44:48.203503 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5385 00:44:48.206625 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5386 00:44:48.213259 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5387 00:44:48.216806 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5388 00:44:48.220345 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5389 00:44:48.226801 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5390 00:44:48.230857 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5391 00:44:48.233666 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5392 00:44:48.240473 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5393 00:44:48.244063 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5394 00:44:48.247556 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5395 00:44:48.253513 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5396 00:44:48.257111 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5397 00:44:48.260624 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5398 00:44:48.263976 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5399 00:44:48.270371 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5400 00:44:48.273629 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5401 00:44:48.277139 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5402 00:44:48.283954 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5403 00:44:48.287066 Total UI for P1: 0, mck2ui 16
5404 00:44:48.290469 best dqsien dly found for B0: ( 1, 2, 26)
5405 00:44:48.293863 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5406 00:44:48.297304 Total UI for P1: 0, mck2ui 16
5407 00:44:48.300291 best dqsien dly found for B1: ( 1, 2, 26)
5408 00:44:48.303854 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5409 00:44:48.307041 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5410 00:44:48.307599
5411 00:44:48.309989 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5412 00:44:48.313483 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5413 00:44:48.316699 [Gating] SW calibration Done
5414 00:44:48.317164 ==
5415 00:44:48.319977 Dram Type= 6, Freq= 0, CH_0, rank 1
5416 00:44:48.326699 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5417 00:44:48.327238 ==
5418 00:44:48.327611 RX Vref Scan: 0
5419 00:44:48.327959
5420 00:44:48.329802 RX Vref 0 -> 0, step: 1
5421 00:44:48.330273
5422 00:44:48.333238 RX Delay -80 -> 252, step: 8
5423 00:44:48.336824 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5424 00:44:48.339997 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5425 00:44:48.343536 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5426 00:44:48.346919 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5427 00:44:48.353638 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5428 00:44:48.356611 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5429 00:44:48.359976 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5430 00:44:48.363332 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5431 00:44:48.366665 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5432 00:44:48.369678 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5433 00:44:48.376199 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5434 00:44:48.379680 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5435 00:44:48.382940 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5436 00:44:48.386233 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5437 00:44:48.389589 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5438 00:44:48.396381 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5439 00:44:48.397013 ==
5440 00:44:48.399979 Dram Type= 6, Freq= 0, CH_0, rank 1
5441 00:44:48.402675 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5442 00:44:48.403254 ==
5443 00:44:48.403630 DQS Delay:
5444 00:44:48.406108 DQS0 = 0, DQS1 = 0
5445 00:44:48.406682 DQM Delay:
5446 00:44:48.409292 DQM0 = 104, DQM1 = 90
5447 00:44:48.409769 DQ Delay:
5448 00:44:48.412971 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5449 00:44:48.416215 DQ4 =107, DQ5 =95, DQ6 =115, DQ7 =111
5450 00:44:48.419757 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =87
5451 00:44:48.422664 DQ12 =95, DQ13 =91, DQ14 =99, DQ15 =99
5452 00:44:48.423164
5453 00:44:48.423528
5454 00:44:48.423944 ==
5455 00:44:48.426349 Dram Type= 6, Freq= 0, CH_0, rank 1
5456 00:44:48.429334 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5457 00:44:48.432796 ==
5458 00:44:48.433358
5459 00:44:48.433728
5460 00:44:48.434066 TX Vref Scan disable
5461 00:44:48.436186 == TX Byte 0 ==
5462 00:44:48.439021 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5463 00:44:48.442723 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5464 00:44:48.445716 == TX Byte 1 ==
5465 00:44:48.449483 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5466 00:44:48.452414 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5467 00:44:48.455905 ==
5468 00:44:48.459352 Dram Type= 6, Freq= 0, CH_0, rank 1
5469 00:44:48.462549 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5470 00:44:48.463124 ==
5471 00:44:48.463498
5472 00:44:48.463841
5473 00:44:48.465746 TX Vref Scan disable
5474 00:44:48.466312 == TX Byte 0 ==
5475 00:44:48.472583 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5476 00:44:48.475560 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5477 00:44:48.476135 == TX Byte 1 ==
5478 00:44:48.482359 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5479 00:44:48.485130 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5480 00:44:48.485597
5481 00:44:48.485965 [DATLAT]
5482 00:44:48.488644 Freq=933, CH0 RK1
5483 00:44:48.489217
5484 00:44:48.489588 DATLAT Default: 0xb
5485 00:44:48.492119 0, 0xFFFF, sum = 0
5486 00:44:48.492863 1, 0xFFFF, sum = 0
5487 00:44:48.495278 2, 0xFFFF, sum = 0
5488 00:44:48.495850 3, 0xFFFF, sum = 0
5489 00:44:48.498957 4, 0xFFFF, sum = 0
5490 00:44:48.499529 5, 0xFFFF, sum = 0
5491 00:44:48.501675 6, 0xFFFF, sum = 0
5492 00:44:48.505210 7, 0xFFFF, sum = 0
5493 00:44:48.505782 8, 0xFFFF, sum = 0
5494 00:44:48.508795 9, 0xFFFF, sum = 0
5495 00:44:48.509368 10, 0x0, sum = 1
5496 00:44:48.511994 11, 0x0, sum = 2
5497 00:44:48.512605 12, 0x0, sum = 3
5498 00:44:48.513008 13, 0x0, sum = 4
5499 00:44:48.515229 best_step = 11
5500 00:44:48.515698
5501 00:44:48.516069 ==
5502 00:44:48.518834 Dram Type= 6, Freq= 0, CH_0, rank 1
5503 00:44:48.522013 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5504 00:44:48.522562 ==
5505 00:44:48.525647 RX Vref Scan: 0
5506 00:44:48.526227
5507 00:44:48.526684 RX Vref 0 -> 0, step: 1
5508 00:44:48.528624
5509 00:44:48.529194 RX Delay -53 -> 252, step: 4
5510 00:44:48.536181 iDelay=199, Bit 0, Center 102 (15 ~ 190) 176
5511 00:44:48.539345 iDelay=199, Bit 1, Center 106 (19 ~ 194) 176
5512 00:44:48.542634 iDelay=199, Bit 2, Center 100 (15 ~ 186) 172
5513 00:44:48.546133 iDelay=199, Bit 3, Center 100 (19 ~ 182) 164
5514 00:44:48.549666 iDelay=199, Bit 4, Center 104 (19 ~ 190) 172
5515 00:44:48.555961 iDelay=199, Bit 5, Center 96 (11 ~ 182) 172
5516 00:44:48.559469 iDelay=199, Bit 6, Center 114 (31 ~ 198) 168
5517 00:44:48.562704 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5518 00:44:48.566136 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5519 00:44:48.569426 iDelay=199, Bit 9, Center 80 (-1 ~ 162) 164
5520 00:44:48.575962 iDelay=199, Bit 10, Center 92 (7 ~ 178) 172
5521 00:44:48.579505 iDelay=199, Bit 11, Center 90 (7 ~ 174) 168
5522 00:44:48.582712 iDelay=199, Bit 12, Center 96 (11 ~ 182) 172
5523 00:44:48.586103 iDelay=199, Bit 13, Center 94 (11 ~ 178) 168
5524 00:44:48.589212 iDelay=199, Bit 14, Center 100 (15 ~ 186) 172
5525 00:44:48.592545 iDelay=199, Bit 15, Center 98 (15 ~ 182) 168
5526 00:44:48.595655 ==
5527 00:44:48.599337 Dram Type= 6, Freq= 0, CH_0, rank 1
5528 00:44:48.602474 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5529 00:44:48.603040 ==
5530 00:44:48.603415 DQS Delay:
5531 00:44:48.605618 DQS0 = 0, DQS1 = 0
5532 00:44:48.606087 DQM Delay:
5533 00:44:48.609327 DQM0 = 104, DQM1 = 91
5534 00:44:48.609893 DQ Delay:
5535 00:44:48.612741 DQ0 =102, DQ1 =106, DQ2 =100, DQ3 =100
5536 00:44:48.615927 DQ4 =104, DQ5 =96, DQ6 =114, DQ7 =112
5537 00:44:48.619129 DQ8 =84, DQ9 =80, DQ10 =92, DQ11 =90
5538 00:44:48.622303 DQ12 =96, DQ13 =94, DQ14 =100, DQ15 =98
5539 00:44:48.622922
5540 00:44:48.623323
5541 00:44:48.632291 [DQSOSCAuto] RK1, (LSB)MR18= 0x2f10, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 407 ps
5542 00:44:48.632895 CH0 RK1: MR19=505, MR18=2F10
5543 00:44:48.638890 CH0_RK1: MR19=0x505, MR18=0x2F10, DQSOSC=407, MR23=63, INC=65, DEC=43
5544 00:44:48.642496 [RxdqsGatingPostProcess] freq 933
5545 00:44:48.649087 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5546 00:44:48.652662 best DQS0 dly(2T, 0.5T) = (0, 10)
5547 00:44:48.656031 best DQS1 dly(2T, 0.5T) = (0, 10)
5548 00:44:48.659149 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5549 00:44:48.662561 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5550 00:44:48.663126 best DQS0 dly(2T, 0.5T) = (0, 10)
5551 00:44:48.665671 best DQS1 dly(2T, 0.5T) = (0, 10)
5552 00:44:48.668893 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5553 00:44:48.672290 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5554 00:44:48.675871 Pre-setting of DQS Precalculation
5555 00:44:48.682490 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5556 00:44:48.683060 ==
5557 00:44:48.685363 Dram Type= 6, Freq= 0, CH_1, rank 0
5558 00:44:48.688936 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5559 00:44:48.689504 ==
5560 00:44:48.695771 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5561 00:44:48.701924 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=31, u1VrefScanEnd=31
5562 00:44:48.705281 [CA 0] Center 37 (7~68) winsize 62
5563 00:44:48.709253 [CA 1] Center 37 (7~68) winsize 62
5564 00:44:48.712189 [CA 2] Center 36 (6~66) winsize 61
5565 00:44:48.715337 [CA 3] Center 34 (4~65) winsize 62
5566 00:44:48.718786 [CA 4] Center 35 (5~65) winsize 61
5567 00:44:48.719252 [CA 5] Center 34 (4~64) winsize 61
5568 00:44:48.719621
5569 00:44:48.725144 [CmdBusTrainingLP45] Vref(ca) range 1: 31
5570 00:44:48.725608
5571 00:44:48.728788 [CATrainingPosCal] consider 1 rank data
5572 00:44:48.732377 u2DelayCellTimex100 = 270/100 ps
5573 00:44:48.735636 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5574 00:44:48.739091 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5575 00:44:48.741693 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5576 00:44:48.745335 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5577 00:44:48.748788 CA4 delay=35 (5~65),Diff = 1 PI (6 cell)
5578 00:44:48.752061 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5579 00:44:48.752665
5580 00:44:48.755512 CA PerBit enable=1, Macro0, CA PI delay=34
5581 00:44:48.756141
5582 00:44:48.758796 [CBTSetCACLKResult] CA Dly = 34
5583 00:44:48.762183 CS Dly: 6 (0~37)
5584 00:44:48.762646 ==
5585 00:44:48.765159 Dram Type= 6, Freq= 0, CH_1, rank 1
5586 00:44:48.768373 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5587 00:44:48.768883 ==
5588 00:44:48.775134 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5589 00:44:48.781730 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5590 00:44:48.785168 [CA 0] Center 37 (7~68) winsize 62
5591 00:44:48.789054 [CA 1] Center 38 (8~69) winsize 62
5592 00:44:48.792025 [CA 2] Center 36 (6~66) winsize 61
5593 00:44:48.795256 [CA 3] Center 35 (5~65) winsize 61
5594 00:44:48.798886 [CA 4] Center 35 (6~65) winsize 60
5595 00:44:48.802296 [CA 5] Center 34 (5~64) winsize 60
5596 00:44:48.802868
5597 00:44:48.805098 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5598 00:44:48.805664
5599 00:44:48.808460 [CATrainingPosCal] consider 2 rank data
5600 00:44:48.812106 u2DelayCellTimex100 = 270/100 ps
5601 00:44:48.815087 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5602 00:44:48.818781 CA1 delay=38 (8~68),Diff = 4 PI (24 cell)
5603 00:44:48.821491 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5604 00:44:48.824925 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5605 00:44:48.828611 CA4 delay=35 (6~65),Diff = 1 PI (6 cell)
5606 00:44:48.832140 CA5 delay=34 (5~64),Diff = 0 PI (0 cell)
5607 00:44:48.832752
5608 00:44:48.838574 CA PerBit enable=1, Macro0, CA PI delay=34
5609 00:44:48.839152
5610 00:44:48.839524 [CBTSetCACLKResult] CA Dly = 34
5611 00:44:48.841745 CS Dly: 7 (0~40)
5612 00:44:48.842311
5613 00:44:48.845204 ----->DramcWriteLeveling(PI) begin...
5614 00:44:48.845779 ==
5615 00:44:48.848414 Dram Type= 6, Freq= 0, CH_1, rank 0
5616 00:44:48.851889 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5617 00:44:48.852458 ==
5618 00:44:48.855174 Write leveling (Byte 0): 24 => 24
5619 00:44:48.858480 Write leveling (Byte 1): 27 => 27
5620 00:44:48.861801 DramcWriteLeveling(PI) end<-----
5621 00:44:48.862367
5622 00:44:48.862735 ==
5623 00:44:48.865152 Dram Type= 6, Freq= 0, CH_1, rank 0
5624 00:44:48.868272 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5625 00:44:48.868794 ==
5626 00:44:48.871731 [Gating] SW mode calibration
5627 00:44:48.878318 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5628 00:44:48.885008 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5629 00:44:48.888737 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5630 00:44:48.895060 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5631 00:44:48.898339 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5632 00:44:48.901477 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5633 00:44:48.907869 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5634 00:44:48.911454 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5635 00:44:48.914830 0 14 24 | B1->B0 | 3232 3131 | 0 1 | (0 0) (0 1)
5636 00:44:48.921270 0 14 28 | B1->B0 | 2626 2626 | 0 0 | (0 0) (0 0)
5637 00:44:48.924429 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5638 00:44:48.927999 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5639 00:44:48.934577 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5640 00:44:48.937949 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5641 00:44:48.941462 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5642 00:44:48.947694 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5643 00:44:48.951070 0 15 24 | B1->B0 | 2828 2c2c | 0 0 | (0 0) (0 0)
5644 00:44:48.954851 0 15 28 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
5645 00:44:48.961380 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5646 00:44:48.964463 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5647 00:44:48.967979 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5648 00:44:48.974232 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5649 00:44:48.977507 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5650 00:44:48.980728 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5651 00:44:48.987580 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5652 00:44:48.990960 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5653 00:44:48.994396 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5654 00:44:49.000605 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5655 00:44:49.004253 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5656 00:44:49.007474 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5657 00:44:49.010860 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5658 00:44:49.017711 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5659 00:44:49.020765 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5660 00:44:49.023727 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5661 00:44:49.030600 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5662 00:44:49.033928 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5663 00:44:49.037471 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5664 00:44:49.043904 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5665 00:44:49.047384 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5666 00:44:49.050868 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5667 00:44:49.057262 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5668 00:44:49.060702 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5669 00:44:49.063732 Total UI for P1: 0, mck2ui 16
5670 00:44:49.067074 best dqsien dly found for B0: ( 1, 2, 24)
5671 00:44:49.070419 Total UI for P1: 0, mck2ui 16
5672 00:44:49.073469 best dqsien dly found for B1: ( 1, 2, 26)
5673 00:44:49.076919 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5674 00:44:49.080258 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5675 00:44:49.080762
5676 00:44:49.083519 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5677 00:44:49.086769 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5678 00:44:49.089975 [Gating] SW calibration Done
5679 00:44:49.090489 ==
5680 00:44:49.093859 Dram Type= 6, Freq= 0, CH_1, rank 0
5681 00:44:49.099906 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5682 00:44:49.100453 ==
5683 00:44:49.100891 RX Vref Scan: 0
5684 00:44:49.101266
5685 00:44:49.103478 RX Vref 0 -> 0, step: 1
5686 00:44:49.104051
5687 00:44:49.106932 RX Delay -80 -> 252, step: 8
5688 00:44:49.110275 iDelay=208, Bit 0, Center 107 (24 ~ 191) 168
5689 00:44:49.113549 iDelay=208, Bit 1, Center 95 (8 ~ 183) 176
5690 00:44:49.117137 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5691 00:44:49.119883 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5692 00:44:49.126849 iDelay=208, Bit 4, Center 103 (16 ~ 191) 176
5693 00:44:49.130292 iDelay=208, Bit 5, Center 111 (24 ~ 199) 176
5694 00:44:49.133428 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5695 00:44:49.136740 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5696 00:44:49.140076 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5697 00:44:49.143436 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5698 00:44:49.150087 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5699 00:44:49.153489 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5700 00:44:49.157031 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5701 00:44:49.160017 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5702 00:44:49.163255 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5703 00:44:49.166725 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5704 00:44:49.170155 ==
5705 00:44:49.170728 Dram Type= 6, Freq= 0, CH_1, rank 0
5706 00:44:49.176331 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5707 00:44:49.176935 ==
5708 00:44:49.177313 DQS Delay:
5709 00:44:49.179702 DQS0 = 0, DQS1 = 0
5710 00:44:49.180233 DQM Delay:
5711 00:44:49.182948 DQM0 = 102, DQM1 = 94
5712 00:44:49.183416 DQ Delay:
5713 00:44:49.186680 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =99
5714 00:44:49.190009 DQ4 =103, DQ5 =111, DQ6 =115, DQ7 =99
5715 00:44:49.192916 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =91
5716 00:44:49.196488 DQ12 =103, DQ13 =103, DQ14 =99, DQ15 =99
5717 00:44:49.196999
5718 00:44:49.197367
5719 00:44:49.197710 ==
5720 00:44:49.199929 Dram Type= 6, Freq= 0, CH_1, rank 0
5721 00:44:49.204851 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5722 00:44:49.205300 ==
5723 00:44:49.205670
5724 00:44:49.206354
5725 00:44:49.206717 TX Vref Scan disable
5726 00:44:49.209646 == TX Byte 0 ==
5727 00:44:49.213158 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5728 00:44:49.216130 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5729 00:44:49.219678 == TX Byte 1 ==
5730 00:44:49.222777 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5731 00:44:49.226619 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5732 00:44:49.227049 ==
5733 00:44:49.229314 Dram Type= 6, Freq= 0, CH_1, rank 0
5734 00:44:49.236272 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5735 00:44:49.236728 ==
5736 00:44:49.237074
5737 00:44:49.237393
5738 00:44:49.237697 TX Vref Scan disable
5739 00:44:49.240211 == TX Byte 0 ==
5740 00:44:49.243546 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5741 00:44:49.250111 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5742 00:44:49.250540 == TX Byte 1 ==
5743 00:44:49.253577 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5744 00:44:49.260435 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5745 00:44:49.261049
5746 00:44:49.261398 [DATLAT]
5747 00:44:49.261719 Freq=933, CH1 RK0
5748 00:44:49.262026
5749 00:44:49.263897 DATLAT Default: 0xd
5750 00:44:49.264434 0, 0xFFFF, sum = 0
5751 00:44:49.266821 1, 0xFFFF, sum = 0
5752 00:44:49.267252 2, 0xFFFF, sum = 0
5753 00:44:49.270207 3, 0xFFFF, sum = 0
5754 00:44:49.270642 4, 0xFFFF, sum = 0
5755 00:44:49.274007 5, 0xFFFF, sum = 0
5756 00:44:49.277440 6, 0xFFFF, sum = 0
5757 00:44:49.277983 7, 0xFFFF, sum = 0
5758 00:44:49.280144 8, 0xFFFF, sum = 0
5759 00:44:49.280637 9, 0xFFFF, sum = 0
5760 00:44:49.283886 10, 0x0, sum = 1
5761 00:44:49.284427 11, 0x0, sum = 2
5762 00:44:49.284834 12, 0x0, sum = 3
5763 00:44:49.287213 13, 0x0, sum = 4
5764 00:44:49.287759 best_step = 11
5765 00:44:49.288103
5766 00:44:49.290422 ==
5767 00:44:49.290850 Dram Type= 6, Freq= 0, CH_1, rank 0
5768 00:44:49.297307 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5769 00:44:49.297848 ==
5770 00:44:49.298193 RX Vref Scan: 1
5771 00:44:49.298509
5772 00:44:49.300398 RX Vref 0 -> 0, step: 1
5773 00:44:49.300982
5774 00:44:49.303426 RX Delay -53 -> 252, step: 4
5775 00:44:49.303854
5776 00:44:49.307265 Set Vref, RX VrefLevel [Byte0]: 51
5777 00:44:49.310102 [Byte1]: 59
5778 00:44:49.310533
5779 00:44:49.313604 Final RX Vref Byte 0 = 51 to rank0
5780 00:44:49.317040 Final RX Vref Byte 1 = 59 to rank0
5781 00:44:49.320036 Final RX Vref Byte 0 = 51 to rank1
5782 00:44:49.323664 Final RX Vref Byte 1 = 59 to rank1==
5783 00:44:49.326954 Dram Type= 6, Freq= 0, CH_1, rank 0
5784 00:44:49.330284 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5785 00:44:49.330715 ==
5786 00:44:49.333578 DQS Delay:
5787 00:44:49.334006 DQS0 = 0, DQS1 = 0
5788 00:44:49.336922 DQM Delay:
5789 00:44:49.337348 DQM0 = 104, DQM1 = 97
5790 00:44:49.337688 DQ Delay:
5791 00:44:49.340306 DQ0 =108, DQ1 =98, DQ2 =94, DQ3 =104
5792 00:44:49.343723 DQ4 =104, DQ5 =112, DQ6 =114, DQ7 =102
5793 00:44:49.346908 DQ8 =88, DQ9 =86, DQ10 =100, DQ11 =92
5794 00:44:49.353901 DQ12 =106, DQ13 =102, DQ14 =106, DQ15 =102
5795 00:44:49.354424
5796 00:44:49.354767
5797 00:44:49.360445 [DQSOSCAuto] RK0, (LSB)MR18= 0x2038, (MSB)MR19= 0x505, tDQSOscB0 = 404 ps tDQSOscB1 = 411 ps
5798 00:44:49.363716 CH1 RK0: MR19=505, MR18=2038
5799 00:44:49.370391 CH1_RK0: MR19=0x505, MR18=0x2038, DQSOSC=404, MR23=63, INC=66, DEC=44
5800 00:44:49.371043
5801 00:44:49.373384 ----->DramcWriteLeveling(PI) begin...
5802 00:44:49.373824 ==
5803 00:44:49.376862 Dram Type= 6, Freq= 0, CH_1, rank 1
5804 00:44:49.380226 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5805 00:44:49.380784 ==
5806 00:44:49.383622 Write leveling (Byte 0): 27 => 27
5807 00:44:49.387294 Write leveling (Byte 1): 28 => 28
5808 00:44:49.390089 DramcWriteLeveling(PI) end<-----
5809 00:44:49.390516
5810 00:44:49.390850 ==
5811 00:44:49.393750 Dram Type= 6, Freq= 0, CH_1, rank 1
5812 00:44:49.397208 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5813 00:44:49.397734 ==
5814 00:44:49.400427 [Gating] SW mode calibration
5815 00:44:49.406954 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5816 00:44:49.413514 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5817 00:44:49.416468 0 14 0 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
5818 00:44:49.423235 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5819 00:44:49.426754 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5820 00:44:49.429966 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5821 00:44:49.433287 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5822 00:44:49.439984 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5823 00:44:49.443239 0 14 24 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 0)
5824 00:44:49.446815 0 14 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5825 00:44:49.453595 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5826 00:44:49.456709 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5827 00:44:49.459999 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5828 00:44:49.466917 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5829 00:44:49.469877 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5830 00:44:49.473058 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5831 00:44:49.479674 0 15 24 | B1->B0 | 2d2d 2525 | 0 0 | (0 0) (0 0)
5832 00:44:49.483210 0 15 28 | B1->B0 | 3d3d 3636 | 0 0 | (1 1) (0 0)
5833 00:44:49.486914 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5834 00:44:49.493267 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5835 00:44:49.496140 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5836 00:44:49.499844 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5837 00:44:49.506388 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5838 00:44:49.509710 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5839 00:44:49.513177 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5840 00:44:49.519497 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5841 00:44:49.522717 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5842 00:44:49.526117 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5843 00:44:49.532898 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5844 00:44:49.536491 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5845 00:44:49.540045 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5846 00:44:49.546153 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5847 00:44:49.549778 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5848 00:44:49.552761 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5849 00:44:49.556508 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5850 00:44:49.562937 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5851 00:44:49.566446 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5852 00:44:49.572499 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5853 00:44:49.575957 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5854 00:44:49.579340 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5855 00:44:49.582702 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5856 00:44:49.589163 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5857 00:44:49.592976 Total UI for P1: 0, mck2ui 16
5858 00:44:49.595735 best dqsien dly found for B1: ( 1, 2, 24)
5859 00:44:49.599502 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5860 00:44:49.603007 Total UI for P1: 0, mck2ui 16
5861 00:44:49.605775 best dqsien dly found for B0: ( 1, 2, 28)
5862 00:44:49.609287 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5863 00:44:49.612822 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5864 00:44:49.613451
5865 00:44:49.615665 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5866 00:44:49.619366 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5867 00:44:49.622258 [Gating] SW calibration Done
5868 00:44:49.622739 ==
5869 00:44:49.625918 Dram Type= 6, Freq= 0, CH_1, rank 1
5870 00:44:49.632524 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5871 00:44:49.633059 ==
5872 00:44:49.633539 RX Vref Scan: 0
5873 00:44:49.634121
5874 00:44:49.635462 RX Vref 0 -> 0, step: 1
5875 00:44:49.635943
5876 00:44:49.638911 RX Delay -80 -> 252, step: 8
5877 00:44:49.642196 iDelay=200, Bit 0, Center 107 (24 ~ 191) 168
5878 00:44:49.645664 iDelay=200, Bit 1, Center 95 (8 ~ 183) 176
5879 00:44:49.649136 iDelay=200, Bit 2, Center 91 (8 ~ 175) 168
5880 00:44:49.652244 iDelay=200, Bit 3, Center 99 (8 ~ 191) 184
5881 00:44:49.659478 iDelay=200, Bit 4, Center 103 (16 ~ 191) 176
5882 00:44:49.662624 iDelay=200, Bit 5, Center 111 (24 ~ 199) 176
5883 00:44:49.665818 iDelay=200, Bit 6, Center 111 (24 ~ 199) 176
5884 00:44:49.668841 iDelay=200, Bit 7, Center 99 (8 ~ 191) 184
5885 00:44:49.672333 iDelay=200, Bit 8, Center 83 (-8 ~ 175) 184
5886 00:44:49.675863 iDelay=200, Bit 9, Center 83 (-8 ~ 175) 184
5887 00:44:49.682196 iDelay=200, Bit 10, Center 95 (0 ~ 191) 192
5888 00:44:49.685396 iDelay=200, Bit 11, Center 91 (0 ~ 183) 184
5889 00:44:49.689096 iDelay=200, Bit 12, Center 103 (8 ~ 199) 192
5890 00:44:49.692326 iDelay=200, Bit 13, Center 103 (8 ~ 199) 192
5891 00:44:49.696039 iDelay=200, Bit 14, Center 99 (8 ~ 191) 184
5892 00:44:49.698950 iDelay=200, Bit 15, Center 103 (8 ~ 199) 192
5893 00:44:49.702198 ==
5894 00:44:49.705741 Dram Type= 6, Freq= 0, CH_1, rank 1
5895 00:44:49.709318 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5896 00:44:49.709852 ==
5897 00:44:49.710220 DQS Delay:
5898 00:44:49.712118 DQS0 = 0, DQS1 = 0
5899 00:44:49.712609 DQM Delay:
5900 00:44:49.715601 DQM0 = 102, DQM1 = 95
5901 00:44:49.716142 DQ Delay:
5902 00:44:49.719090 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =99
5903 00:44:49.722307 DQ4 =103, DQ5 =111, DQ6 =111, DQ7 =99
5904 00:44:49.725893 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =91
5905 00:44:49.729064 DQ12 =103, DQ13 =103, DQ14 =99, DQ15 =103
5906 00:44:49.729622
5907 00:44:49.729993
5908 00:44:49.730331 ==
5909 00:44:49.732004 Dram Type= 6, Freq= 0, CH_1, rank 1
5910 00:44:49.735677 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5911 00:44:49.736147 ==
5912 00:44:49.738604
5913 00:44:49.739065
5914 00:44:49.739432 TX Vref Scan disable
5915 00:44:49.742090 == TX Byte 0 ==
5916 00:44:49.745598 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5917 00:44:49.749060 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5918 00:44:49.752298 == TX Byte 1 ==
5919 00:44:49.755307 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5920 00:44:49.758933 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5921 00:44:49.759400 ==
5922 00:44:49.762556 Dram Type= 6, Freq= 0, CH_1, rank 1
5923 00:44:49.769124 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5924 00:44:49.769703 ==
5925 00:44:49.770079
5926 00:44:49.770422
5927 00:44:49.770751 TX Vref Scan disable
5928 00:44:49.773111 == TX Byte 0 ==
5929 00:44:49.776540 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5930 00:44:49.782895 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5931 00:44:49.783367 == TX Byte 1 ==
5932 00:44:49.786299 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5933 00:44:49.792809 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5934 00:44:49.793371
5935 00:44:49.793746 [DATLAT]
5936 00:44:49.794091 Freq=933, CH1 RK1
5937 00:44:49.794419
5938 00:44:49.796392 DATLAT Default: 0xb
5939 00:44:49.797007 0, 0xFFFF, sum = 0
5940 00:44:49.799914 1, 0xFFFF, sum = 0
5941 00:44:49.800488 2, 0xFFFF, sum = 0
5942 00:44:49.802561 3, 0xFFFF, sum = 0
5943 00:44:49.805983 4, 0xFFFF, sum = 0
5944 00:44:49.806453 5, 0xFFFF, sum = 0
5945 00:44:49.809618 6, 0xFFFF, sum = 0
5946 00:44:49.810191 7, 0xFFFF, sum = 0
5947 00:44:49.812790 8, 0xFFFF, sum = 0
5948 00:44:49.813263 9, 0xFFFF, sum = 0
5949 00:44:49.816181 10, 0x0, sum = 1
5950 00:44:49.816691 11, 0x0, sum = 2
5951 00:44:49.817077 12, 0x0, sum = 3
5952 00:44:49.819386 13, 0x0, sum = 4
5953 00:44:49.819856 best_step = 11
5954 00:44:49.820226
5955 00:44:49.822666 ==
5956 00:44:49.823129 Dram Type= 6, Freq= 0, CH_1, rank 1
5957 00:44:49.829748 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5958 00:44:49.830219 ==
5959 00:44:49.830691 RX Vref Scan: 0
5960 00:44:49.831049
5961 00:44:49.832631 RX Vref 0 -> 0, step: 1
5962 00:44:49.833098
5963 00:44:49.836339 RX Delay -53 -> 252, step: 4
5964 00:44:49.839586 iDelay=199, Bit 0, Center 108 (31 ~ 186) 156
5965 00:44:49.846222 iDelay=199, Bit 1, Center 98 (19 ~ 178) 160
5966 00:44:49.849900 iDelay=199, Bit 2, Center 94 (15 ~ 174) 160
5967 00:44:49.852792 iDelay=199, Bit 3, Center 102 (19 ~ 186) 168
5968 00:44:49.856446 iDelay=199, Bit 4, Center 104 (23 ~ 186) 164
5969 00:44:49.859559 iDelay=199, Bit 5, Center 116 (35 ~ 198) 164
5970 00:44:49.863225 iDelay=199, Bit 6, Center 114 (35 ~ 194) 160
5971 00:44:49.869672 iDelay=199, Bit 7, Center 102 (23 ~ 182) 160
5972 00:44:49.872963 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5973 00:44:49.876136 iDelay=199, Bit 9, Center 88 (3 ~ 174) 172
5974 00:44:49.879511 iDelay=199, Bit 10, Center 98 (11 ~ 186) 176
5975 00:44:49.882939 iDelay=199, Bit 11, Center 92 (7 ~ 178) 172
5976 00:44:49.889284 iDelay=199, Bit 12, Center 106 (19 ~ 194) 176
5977 00:44:49.892727 iDelay=199, Bit 13, Center 104 (19 ~ 190) 172
5978 00:44:49.896371 iDelay=199, Bit 14, Center 104 (19 ~ 190) 172
5979 00:44:49.899334 iDelay=199, Bit 15, Center 106 (19 ~ 194) 176
5980 00:44:49.899806 ==
5981 00:44:49.903005 Dram Type= 6, Freq= 0, CH_1, rank 1
5982 00:44:49.909788 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5983 00:44:49.910369 ==
5984 00:44:49.910748 DQS Delay:
5985 00:44:49.911096 DQS0 = 0, DQS1 = 0
5986 00:44:49.912727 DQM Delay:
5987 00:44:49.913198 DQM0 = 104, DQM1 = 97
5988 00:44:49.916107 DQ Delay:
5989 00:44:49.919559 DQ0 =108, DQ1 =98, DQ2 =94, DQ3 =102
5990 00:44:49.922735 DQ4 =104, DQ5 =116, DQ6 =114, DQ7 =102
5991 00:44:49.925720 DQ8 =84, DQ9 =88, DQ10 =98, DQ11 =92
5992 00:44:49.929156 DQ12 =106, DQ13 =104, DQ14 =104, DQ15 =106
5993 00:44:49.929630
5994 00:44:49.930003
5995 00:44:49.935904 [DQSOSCAuto] RK1, (LSB)MR18= 0x22ff, (MSB)MR19= 0x504, tDQSOscB0 = 422 ps tDQSOscB1 = 411 ps
5996 00:44:49.939214 CH1 RK1: MR19=504, MR18=22FF
5997 00:44:49.945879 CH1_RK1: MR19=0x504, MR18=0x22FF, DQSOSC=411, MR23=63, INC=64, DEC=42
5998 00:44:49.949095 [RxdqsGatingPostProcess] freq 933
5999 00:44:49.955753 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6000 00:44:49.956371 best DQS0 dly(2T, 0.5T) = (0, 10)
6001 00:44:49.958960 best DQS1 dly(2T, 0.5T) = (0, 10)
6002 00:44:49.962309 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6003 00:44:49.965454 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6004 00:44:49.969053 best DQS0 dly(2T, 0.5T) = (0, 10)
6005 00:44:49.972455 best DQS1 dly(2T, 0.5T) = (0, 10)
6006 00:44:49.975399 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6007 00:44:49.979048 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6008 00:44:49.982602 Pre-setting of DQS Precalculation
6009 00:44:49.989308 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6010 00:44:49.995567 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6011 00:44:50.002232 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6012 00:44:50.002775
6013 00:44:50.003140
6014 00:44:50.005461 [Calibration Summary] 1866 Mbps
6015 00:44:50.005927 CH 0, Rank 0
6016 00:44:50.008960 SW Impedance : PASS
6017 00:44:50.011985 DUTY Scan : NO K
6018 00:44:50.012592 ZQ Calibration : PASS
6019 00:44:50.015460 Jitter Meter : NO K
6020 00:44:50.018600 CBT Training : PASS
6021 00:44:50.019065 Write leveling : PASS
6022 00:44:50.021916 RX DQS gating : PASS
6023 00:44:50.025365 RX DQ/DQS(RDDQC) : PASS
6024 00:44:50.025828 TX DQ/DQS : PASS
6025 00:44:50.028845 RX DATLAT : PASS
6026 00:44:50.029407 RX DQ/DQS(Engine): PASS
6027 00:44:50.031746 TX OE : NO K
6028 00:44:50.032339 All Pass.
6029 00:44:50.032775
6030 00:44:50.035185 CH 0, Rank 1
6031 00:44:50.035647 SW Impedance : PASS
6032 00:44:50.038794 DUTY Scan : NO K
6033 00:44:50.041995 ZQ Calibration : PASS
6034 00:44:50.042466 Jitter Meter : NO K
6035 00:44:50.045221 CBT Training : PASS
6036 00:44:50.048325 Write leveling : PASS
6037 00:44:50.048838 RX DQS gating : PASS
6038 00:44:50.051693 RX DQ/DQS(RDDQC) : PASS
6039 00:44:50.055442 TX DQ/DQS : PASS
6040 00:44:50.056010 RX DATLAT : PASS
6041 00:44:50.058424 RX DQ/DQS(Engine): PASS
6042 00:44:50.062258 TX OE : NO K
6043 00:44:50.062826 All Pass.
6044 00:44:50.063197
6045 00:44:50.063540 CH 1, Rank 0
6046 00:44:50.065268 SW Impedance : PASS
6047 00:44:50.068421 DUTY Scan : NO K
6048 00:44:50.069043 ZQ Calibration : PASS
6049 00:44:50.071738 Jitter Meter : NO K
6050 00:44:50.075075 CBT Training : PASS
6051 00:44:50.075679 Write leveling : PASS
6052 00:44:50.078391 RX DQS gating : PASS
6053 00:44:50.078853 RX DQ/DQS(RDDQC) : PASS
6054 00:44:50.081439 TX DQ/DQS : PASS
6055 00:44:50.084919 RX DATLAT : PASS
6056 00:44:50.085383 RX DQ/DQS(Engine): PASS
6057 00:44:50.088723 TX OE : NO K
6058 00:44:50.089295 All Pass.
6059 00:44:50.089668
6060 00:44:50.091968 CH 1, Rank 1
6061 00:44:50.092532 SW Impedance : PASS
6062 00:44:50.095004 DUTY Scan : NO K
6063 00:44:50.098230 ZQ Calibration : PASS
6064 00:44:50.098694 Jitter Meter : NO K
6065 00:44:50.101728 CBT Training : PASS
6066 00:44:50.104639 Write leveling : PASS
6067 00:44:50.105104 RX DQS gating : PASS
6068 00:44:50.108420 RX DQ/DQS(RDDQC) : PASS
6069 00:44:50.111881 TX DQ/DQS : PASS
6070 00:44:50.112453 RX DATLAT : PASS
6071 00:44:50.114880 RX DQ/DQS(Engine): PASS
6072 00:44:50.118373 TX OE : NO K
6073 00:44:50.118841 All Pass.
6074 00:44:50.119206
6075 00:44:50.119546 DramC Write-DBI off
6076 00:44:50.121709 PER_BANK_REFRESH: Hybrid Mode
6077 00:44:50.124665 TX_TRACKING: ON
6078 00:44:50.131143 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6079 00:44:50.134918 [FAST_K] Save calibration result to emmc
6080 00:44:50.141103 dramc_set_vcore_voltage set vcore to 650000
6081 00:44:50.141658 Read voltage for 400, 6
6082 00:44:50.145008 Vio18 = 0
6083 00:44:50.145523 Vcore = 650000
6084 00:44:50.145901 Vdram = 0
6085 00:44:50.148446 Vddq = 0
6086 00:44:50.149145 Vmddr = 0
6087 00:44:50.151840 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6088 00:44:50.158005 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6089 00:44:50.161230 MEM_TYPE=3, freq_sel=20
6090 00:44:50.164799 sv_algorithm_assistance_LP4_800
6091 00:44:50.168066 ============ PULL DRAM RESETB DOWN ============
6092 00:44:50.171362 ========== PULL DRAM RESETB DOWN end =========
6093 00:44:50.174372 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6094 00:44:50.177938 ===================================
6095 00:44:50.181116 LPDDR4 DRAM CONFIGURATION
6096 00:44:50.184482 ===================================
6097 00:44:50.187919 EX_ROW_EN[0] = 0x0
6098 00:44:50.188386 EX_ROW_EN[1] = 0x0
6099 00:44:50.191391 LP4Y_EN = 0x0
6100 00:44:50.191961 WORK_FSP = 0x0
6101 00:44:50.194387 WL = 0x2
6102 00:44:50.195044 RL = 0x2
6103 00:44:50.198022 BL = 0x2
6104 00:44:50.198489 RPST = 0x0
6105 00:44:50.201559 RD_PRE = 0x0
6106 00:44:50.202153 WR_PRE = 0x1
6107 00:44:50.204438 WR_PST = 0x0
6108 00:44:50.204940 DBI_WR = 0x0
6109 00:44:50.207665 DBI_RD = 0x0
6110 00:44:50.208121 OTF = 0x1
6111 00:44:50.211237 ===================================
6112 00:44:50.214621 ===================================
6113 00:44:50.217921 ANA top config
6114 00:44:50.221539 ===================================
6115 00:44:50.224689 DLL_ASYNC_EN = 0
6116 00:44:50.225160 ALL_SLAVE_EN = 1
6117 00:44:50.227648 NEW_RANK_MODE = 1
6118 00:44:50.230997 DLL_IDLE_MODE = 1
6119 00:44:50.234641 LP45_APHY_COMB_EN = 1
6120 00:44:50.238308 TX_ODT_DIS = 1
6121 00:44:50.238879 NEW_8X_MODE = 1
6122 00:44:50.241380 ===================================
6123 00:44:50.245010 ===================================
6124 00:44:50.247986 data_rate = 800
6125 00:44:50.251109 CKR = 1
6126 00:44:50.254424 DQ_P2S_RATIO = 4
6127 00:44:50.257728 ===================================
6128 00:44:50.261111 CA_P2S_RATIO = 4
6129 00:44:50.261608 DQ_CA_OPEN = 0
6130 00:44:50.264674 DQ_SEMI_OPEN = 1
6131 00:44:50.268216 CA_SEMI_OPEN = 1
6132 00:44:50.271363 CA_FULL_RATE = 0
6133 00:44:50.274650 DQ_CKDIV4_EN = 0
6134 00:44:50.277912 CA_CKDIV4_EN = 1
6135 00:44:50.278377 CA_PREDIV_EN = 0
6136 00:44:50.281315 PH8_DLY = 0
6137 00:44:50.284328 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6138 00:44:50.288112 DQ_AAMCK_DIV = 0
6139 00:44:50.290979 CA_AAMCK_DIV = 0
6140 00:44:50.294556 CA_ADMCK_DIV = 4
6141 00:44:50.295132 DQ_TRACK_CA_EN = 0
6142 00:44:50.297683 CA_PICK = 800
6143 00:44:50.300943 CA_MCKIO = 400
6144 00:44:50.304814 MCKIO_SEMI = 400
6145 00:44:50.307567 PLL_FREQ = 3016
6146 00:44:50.311278 DQ_UI_PI_RATIO = 32
6147 00:44:50.314385 CA_UI_PI_RATIO = 32
6148 00:44:50.317453 ===================================
6149 00:44:50.321243 ===================================
6150 00:44:50.321825 memory_type:LPDDR4
6151 00:44:50.324390 GP_NUM : 10
6152 00:44:50.327927 SRAM_EN : 1
6153 00:44:50.328476 MD32_EN : 0
6154 00:44:50.331192 ===================================
6155 00:44:50.334844 [ANA_INIT] >>>>>>>>>>>>>>
6156 00:44:50.337709 <<<<<< [CONFIGURE PHASE]: ANA_TX
6157 00:44:50.340993 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6158 00:44:50.344906 ===================================
6159 00:44:50.347653 data_rate = 800,PCW = 0X7400
6160 00:44:50.350884 ===================================
6161 00:44:50.354480 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6162 00:44:50.357526 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6163 00:44:50.371167 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6164 00:44:50.374432 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6165 00:44:50.377702 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6166 00:44:50.381200 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6167 00:44:50.384420 [ANA_INIT] flow start
6168 00:44:50.385109 [ANA_INIT] PLL >>>>>>>>
6169 00:44:50.387812 [ANA_INIT] PLL <<<<<<<<
6170 00:44:50.390773 [ANA_INIT] MIDPI >>>>>>>>
6171 00:44:50.394218 [ANA_INIT] MIDPI <<<<<<<<
6172 00:44:50.394767 [ANA_INIT] DLL >>>>>>>>
6173 00:44:50.397533 [ANA_INIT] flow end
6174 00:44:50.400510 ============ LP4 DIFF to SE enter ============
6175 00:44:50.404290 ============ LP4 DIFF to SE exit ============
6176 00:44:50.407438 [ANA_INIT] <<<<<<<<<<<<<
6177 00:44:50.410839 [Flow] Enable top DCM control >>>>>
6178 00:44:50.413922 [Flow] Enable top DCM control <<<<<
6179 00:44:50.417144 Enable DLL master slave shuffle
6180 00:44:50.424015 ==============================================================
6181 00:44:50.424608 Gating Mode config
6182 00:44:50.430498 ==============================================================
6183 00:44:50.430972 Config description:
6184 00:44:50.441000 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6185 00:44:50.447429 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6186 00:44:50.454029 SELPH_MODE 0: By rank 1: By Phase
6187 00:44:50.457506 ==============================================================
6188 00:44:50.460941 GAT_TRACK_EN = 0
6189 00:44:50.463613 RX_GATING_MODE = 2
6190 00:44:50.466936 RX_GATING_TRACK_MODE = 2
6191 00:44:50.470698 SELPH_MODE = 1
6192 00:44:50.473773 PICG_EARLY_EN = 1
6193 00:44:50.477485 VALID_LAT_VALUE = 1
6194 00:44:50.480195 ==============================================================
6195 00:44:50.483714 Enter into Gating configuration >>>>
6196 00:44:50.487436 Exit from Gating configuration <<<<
6197 00:44:50.490682 Enter into DVFS_PRE_config >>>>>
6198 00:44:50.504043 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6199 00:44:50.507186 Exit from DVFS_PRE_config <<<<<
6200 00:44:50.510505 Enter into PICG configuration >>>>
6201 00:44:50.510969 Exit from PICG configuration <<<<
6202 00:44:50.513794 [RX_INPUT] configuration >>>>>
6203 00:44:50.516996 [RX_INPUT] configuration <<<<<
6204 00:44:50.523660 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6205 00:44:50.526866 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6206 00:44:50.533782 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6207 00:44:50.540782 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6208 00:44:50.547166 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6209 00:44:50.553959 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6210 00:44:50.557208 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6211 00:44:50.560021 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6212 00:44:50.563689 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6213 00:44:50.570222 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6214 00:44:50.573628 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6215 00:44:50.577187 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6216 00:44:50.579940 ===================================
6217 00:44:50.583565 LPDDR4 DRAM CONFIGURATION
6218 00:44:50.586730 ===================================
6219 00:44:50.590217 EX_ROW_EN[0] = 0x0
6220 00:44:50.590679 EX_ROW_EN[1] = 0x0
6221 00:44:50.593137 LP4Y_EN = 0x0
6222 00:44:50.593601 WORK_FSP = 0x0
6223 00:44:50.596906 WL = 0x2
6224 00:44:50.597469 RL = 0x2
6225 00:44:50.599730 BL = 0x2
6226 00:44:50.600213 RPST = 0x0
6227 00:44:50.603118 RD_PRE = 0x0
6228 00:44:50.603582 WR_PRE = 0x1
6229 00:44:50.606362 WR_PST = 0x0
6230 00:44:50.606828 DBI_WR = 0x0
6231 00:44:50.609971 DBI_RD = 0x0
6232 00:44:50.610556 OTF = 0x1
6233 00:44:50.613403 ===================================
6234 00:44:50.620076 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6235 00:44:50.623067 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6236 00:44:50.626179 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6237 00:44:50.629546 ===================================
6238 00:44:50.633013 LPDDR4 DRAM CONFIGURATION
6239 00:44:50.636271 ===================================
6240 00:44:50.639893 EX_ROW_EN[0] = 0x10
6241 00:44:50.640448 EX_ROW_EN[1] = 0x0
6242 00:44:50.643254 LP4Y_EN = 0x0
6243 00:44:50.643774 WORK_FSP = 0x0
6244 00:44:50.646185 WL = 0x2
6245 00:44:50.646647 RL = 0x2
6246 00:44:50.649693 BL = 0x2
6247 00:44:50.650160 RPST = 0x0
6248 00:44:50.653253 RD_PRE = 0x0
6249 00:44:50.653716 WR_PRE = 0x1
6250 00:44:50.656583 WR_PST = 0x0
6251 00:44:50.657145 DBI_WR = 0x0
6252 00:44:50.659879 DBI_RD = 0x0
6253 00:44:50.660341 OTF = 0x1
6254 00:44:50.663515 ===================================
6255 00:44:50.669711 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6256 00:44:50.674459 nWR fixed to 30
6257 00:44:50.677697 [ModeRegInit_LP4] CH0 RK0
6258 00:44:50.678180 [ModeRegInit_LP4] CH0 RK1
6259 00:44:50.680781 [ModeRegInit_LP4] CH1 RK0
6260 00:44:50.684773 [ModeRegInit_LP4] CH1 RK1
6261 00:44:50.685357 match AC timing 19
6262 00:44:50.691183 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6263 00:44:50.694588 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6264 00:44:50.697988 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6265 00:44:50.704498 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6266 00:44:50.707295 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6267 00:44:50.707774 ==
6268 00:44:50.710988 Dram Type= 6, Freq= 0, CH_0, rank 0
6269 00:44:50.714745 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6270 00:44:50.715332 ==
6271 00:44:50.721343 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6272 00:44:50.727766 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6273 00:44:50.731175 [CA 0] Center 36 (8~64) winsize 57
6274 00:44:50.734552 [CA 1] Center 36 (8~64) winsize 57
6275 00:44:50.735031 [CA 2] Center 36 (8~64) winsize 57
6276 00:44:50.737525 [CA 3] Center 36 (8~64) winsize 57
6277 00:44:50.740931 [CA 4] Center 36 (8~64) winsize 57
6278 00:44:50.744038 [CA 5] Center 36 (8~64) winsize 57
6279 00:44:50.744513
6280 00:44:50.747617 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6281 00:44:50.748201
6282 00:44:50.754500 [CATrainingPosCal] consider 1 rank data
6283 00:44:50.755084 u2DelayCellTimex100 = 270/100 ps
6284 00:44:50.760938 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6285 00:44:50.764398 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6286 00:44:50.767774 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6287 00:44:50.771259 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6288 00:44:50.774338 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6289 00:44:50.777820 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6290 00:44:50.778287
6291 00:44:50.781183 CA PerBit enable=1, Macro0, CA PI delay=36
6292 00:44:50.781647
6293 00:44:50.784144 [CBTSetCACLKResult] CA Dly = 36
6294 00:44:50.784624 CS Dly: 1 (0~32)
6295 00:44:50.787657 ==
6296 00:44:50.791466 Dram Type= 6, Freq= 0, CH_0, rank 1
6297 00:44:50.794215 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6298 00:44:50.794685 ==
6299 00:44:50.797926 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6300 00:44:50.804845 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6301 00:44:50.808299 [CA 0] Center 36 (8~64) winsize 57
6302 00:44:50.811501 [CA 1] Center 36 (8~64) winsize 57
6303 00:44:50.814407 [CA 2] Center 36 (8~64) winsize 57
6304 00:44:50.817908 [CA 3] Center 36 (8~64) winsize 57
6305 00:44:50.821165 [CA 4] Center 36 (8~64) winsize 57
6306 00:44:50.824581 [CA 5] Center 36 (8~64) winsize 57
6307 00:44:50.825049
6308 00:44:50.827942 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6309 00:44:50.828406
6310 00:44:50.831349 [CATrainingPosCal] consider 2 rank data
6311 00:44:50.834873 u2DelayCellTimex100 = 270/100 ps
6312 00:44:50.837867 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6313 00:44:50.841339 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6314 00:44:50.844676 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6315 00:44:50.848021 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6316 00:44:50.850707 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6317 00:44:50.857996 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6318 00:44:50.858574
6319 00:44:50.861211 CA PerBit enable=1, Macro0, CA PI delay=36
6320 00:44:50.861681
6321 00:44:50.864153 [CBTSetCACLKResult] CA Dly = 36
6322 00:44:50.864664 CS Dly: 1 (0~32)
6323 00:44:50.865045
6324 00:44:50.867436 ----->DramcWriteLeveling(PI) begin...
6325 00:44:50.867910 ==
6326 00:44:50.870914 Dram Type= 6, Freq= 0, CH_0, rank 0
6327 00:44:50.874211 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6328 00:44:50.877508 ==
6329 00:44:50.878018 Write leveling (Byte 0): 40 => 8
6330 00:44:50.880624 Write leveling (Byte 1): 32 => 0
6331 00:44:50.883962 DramcWriteLeveling(PI) end<-----
6332 00:44:50.884432
6333 00:44:50.884856 ==
6334 00:44:50.887432 Dram Type= 6, Freq= 0, CH_0, rank 0
6335 00:44:50.894091 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6336 00:44:50.894662 ==
6337 00:44:50.895040 [Gating] SW mode calibration
6338 00:44:50.903848 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6339 00:44:50.907640 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6340 00:44:50.913961 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6341 00:44:50.917466 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6342 00:44:50.920894 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6343 00:44:50.924253 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6344 00:44:50.930453 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6345 00:44:50.934251 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6346 00:44:50.937340 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6347 00:44:50.944020 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6348 00:44:50.947805 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6349 00:44:50.950616 Total UI for P1: 0, mck2ui 16
6350 00:44:50.954464 best dqsien dly found for B0: ( 0, 14, 24)
6351 00:44:50.957477 Total UI for P1: 0, mck2ui 16
6352 00:44:50.960807 best dqsien dly found for B1: ( 0, 14, 24)
6353 00:44:50.964419 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6354 00:44:50.967579 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6355 00:44:50.968143
6356 00:44:50.970873 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6357 00:44:50.974113 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6358 00:44:50.977503 [Gating] SW calibration Done
6359 00:44:50.977984 ==
6360 00:44:50.980713 Dram Type= 6, Freq= 0, CH_0, rank 0
6361 00:44:50.987218 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6362 00:44:50.987677 ==
6363 00:44:50.988094 RX Vref Scan: 0
6364 00:44:50.988430
6365 00:44:50.990691 RX Vref 0 -> 0, step: 1
6366 00:44:50.991146
6367 00:44:50.993796 RX Delay -410 -> 252, step: 16
6368 00:44:50.997356 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6369 00:44:51.000682 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6370 00:44:51.004495 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6371 00:44:51.010976 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6372 00:44:51.014229 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6373 00:44:51.017741 iDelay=230, Bit 5, Center -19 (-250 ~ 213) 464
6374 00:44:51.021084 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6375 00:44:51.027164 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6376 00:44:51.030770 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6377 00:44:51.034231 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6378 00:44:51.037633 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6379 00:44:51.043772 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6380 00:44:51.047375 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6381 00:44:51.050694 iDelay=230, Bit 13, Center -27 (-266 ~ 213) 480
6382 00:44:51.053979 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6383 00:44:51.060583 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6384 00:44:51.061174 ==
6385 00:44:51.063961 Dram Type= 6, Freq= 0, CH_0, rank 0
6386 00:44:51.067899 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6387 00:44:51.068462 ==
6388 00:44:51.068855 DQS Delay:
6389 00:44:51.070946 DQS0 = 19, DQS1 = 43
6390 00:44:51.071503 DQM Delay:
6391 00:44:51.074089 DQM0 = 5, DQM1 = 14
6392 00:44:51.074708 DQ Delay:
6393 00:44:51.077211 DQ0 =0, DQ1 =8, DQ2 =0, DQ3 =0
6394 00:44:51.080861 DQ4 =8, DQ5 =0, DQ6 =8, DQ7 =16
6395 00:44:51.083905 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6396 00:44:51.087416 DQ12 =24, DQ13 =16, DQ14 =24, DQ15 =24
6397 00:44:51.087949
6398 00:44:51.088305
6399 00:44:51.088697 ==
6400 00:44:51.091000 Dram Type= 6, Freq= 0, CH_0, rank 0
6401 00:44:51.094281 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6402 00:44:51.094780 ==
6403 00:44:51.095143
6404 00:44:51.095472
6405 00:44:51.097230 TX Vref Scan disable
6406 00:44:51.097682 == TX Byte 0 ==
6407 00:44:51.104214 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6408 00:44:51.107633 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6409 00:44:51.108190 == TX Byte 1 ==
6410 00:44:51.114051 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6411 00:44:51.117455 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6412 00:44:51.118016 ==
6413 00:44:51.120724 Dram Type= 6, Freq= 0, CH_0, rank 0
6414 00:44:51.124393 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6415 00:44:51.124993 ==
6416 00:44:51.125358
6417 00:44:51.125690
6418 00:44:51.127378 TX Vref Scan disable
6419 00:44:51.131061 == TX Byte 0 ==
6420 00:44:51.134018 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6421 00:44:51.137479 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6422 00:44:51.138034 == TX Byte 1 ==
6423 00:44:51.143966 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6424 00:44:51.147593 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6425 00:44:51.148152
6426 00:44:51.148729 [DATLAT]
6427 00:44:51.150777 Freq=400, CH0 RK0
6428 00:44:51.151231
6429 00:44:51.151585 DATLAT Default: 0xf
6430 00:44:51.154218 0, 0xFFFF, sum = 0
6431 00:44:51.154789 1, 0xFFFF, sum = 0
6432 00:44:51.157696 2, 0xFFFF, sum = 0
6433 00:44:51.160235 3, 0xFFFF, sum = 0
6434 00:44:51.160738 4, 0xFFFF, sum = 0
6435 00:44:51.164016 5, 0xFFFF, sum = 0
6436 00:44:51.164609 6, 0xFFFF, sum = 0
6437 00:44:51.167283 7, 0xFFFF, sum = 0
6438 00:44:51.167745 8, 0xFFFF, sum = 0
6439 00:44:51.170278 9, 0xFFFF, sum = 0
6440 00:44:51.170735 10, 0xFFFF, sum = 0
6441 00:44:51.173787 11, 0xFFFF, sum = 0
6442 00:44:51.174246 12, 0xFFFF, sum = 0
6443 00:44:51.177221 13, 0x0, sum = 1
6444 00:44:51.177687 14, 0x0, sum = 2
6445 00:44:51.180534 15, 0x0, sum = 3
6446 00:44:51.181059 16, 0x0, sum = 4
6447 00:44:51.183790 best_step = 14
6448 00:44:51.184238
6449 00:44:51.184629 ==
6450 00:44:51.187101 Dram Type= 6, Freq= 0, CH_0, rank 0
6451 00:44:51.190896 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6452 00:44:51.191454 ==
6453 00:44:51.191818 RX Vref Scan: 1
6454 00:44:51.192151
6455 00:44:51.194218 RX Vref 0 -> 0, step: 1
6456 00:44:51.194778
6457 00:44:51.197448 RX Delay -327 -> 252, step: 8
6458 00:44:51.198002
6459 00:44:51.200648 Set Vref, RX VrefLevel [Byte0]: 59
6460 00:44:51.204003 [Byte1]: 50
6461 00:44:51.207786
6462 00:44:51.208397 Final RX Vref Byte 0 = 59 to rank0
6463 00:44:51.211255 Final RX Vref Byte 1 = 50 to rank0
6464 00:44:51.214781 Final RX Vref Byte 0 = 59 to rank1
6465 00:44:51.217727 Final RX Vref Byte 1 = 50 to rank1==
6466 00:44:51.221146 Dram Type= 6, Freq= 0, CH_0, rank 0
6467 00:44:51.227407 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6468 00:44:51.228054 ==
6469 00:44:51.228678 DQS Delay:
6470 00:44:51.230921 DQS0 = 28, DQS1 = 48
6471 00:44:51.231473 DQM Delay:
6472 00:44:51.231833 DQM0 = 12, DQM1 = 15
6473 00:44:51.234453 DQ Delay:
6474 00:44:51.237805 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8
6475 00:44:51.241004 DQ4 =12, DQ5 =0, DQ6 =24, DQ7 =20
6476 00:44:51.241559 DQ8 =8, DQ9 =0, DQ10 =12, DQ11 =12
6477 00:44:51.244247 DQ12 =20, DQ13 =20, DQ14 =28, DQ15 =24
6478 00:44:51.247655
6479 00:44:51.248111
6480 00:44:51.254053 [DQSOSCAuto] RK0, (LSB)MR18= 0xb6ae, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 387 ps
6481 00:44:51.257487 CH0 RK0: MR19=C0C, MR18=B6AE
6482 00:44:51.264023 CH0_RK0: MR19=0xC0C, MR18=0xB6AE, DQSOSC=387, MR23=63, INC=394, DEC=262
6483 00:44:51.264606 ==
6484 00:44:51.267549 Dram Type= 6, Freq= 0, CH_0, rank 1
6485 00:44:51.271033 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6486 00:44:51.271526 ==
6487 00:44:51.274456 [Gating] SW mode calibration
6488 00:44:51.280514 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6489 00:44:51.287101 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6490 00:44:51.290404 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6491 00:44:51.293840 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6492 00:44:51.300275 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6493 00:44:51.303711 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6494 00:44:51.307179 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6495 00:44:51.313655 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6496 00:44:51.317205 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6497 00:44:51.320624 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6498 00:44:51.326895 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6499 00:44:51.327361 Total UI for P1: 0, mck2ui 16
6500 00:44:51.330247 best dqsien dly found for B0: ( 0, 14, 24)
6501 00:44:51.333891 Total UI for P1: 0, mck2ui 16
6502 00:44:51.336740 best dqsien dly found for B1: ( 0, 14, 24)
6503 00:44:51.343636 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6504 00:44:51.347010 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6505 00:44:51.347432
6506 00:44:51.350602 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6507 00:44:51.353538 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6508 00:44:51.357042 [Gating] SW calibration Done
6509 00:44:51.357463 ==
6510 00:44:51.360813 Dram Type= 6, Freq= 0, CH_0, rank 1
6511 00:44:51.363737 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6512 00:44:51.364263 ==
6513 00:44:51.367141 RX Vref Scan: 0
6514 00:44:51.367560
6515 00:44:51.367894 RX Vref 0 -> 0, step: 1
6516 00:44:51.368205
6517 00:44:51.370241 RX Delay -410 -> 252, step: 16
6518 00:44:51.373558 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6519 00:44:51.380031 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6520 00:44:51.383583 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6521 00:44:51.387167 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6522 00:44:51.390010 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6523 00:44:51.396663 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6524 00:44:51.400304 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6525 00:44:51.403763 iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480
6526 00:44:51.407059 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6527 00:44:51.413132 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6528 00:44:51.417007 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6529 00:44:51.420023 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6530 00:44:51.423667 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6531 00:44:51.429744 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6532 00:44:51.433208 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6533 00:44:51.436494 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6534 00:44:51.436982 ==
6535 00:44:51.440047 Dram Type= 6, Freq= 0, CH_0, rank 1
6536 00:44:51.446409 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6537 00:44:51.446842 ==
6538 00:44:51.447252 DQS Delay:
6539 00:44:51.450081 DQS0 = 27, DQS1 = 35
6540 00:44:51.450670 DQM Delay:
6541 00:44:51.451046 DQM0 = 10, DQM1 = 9
6542 00:44:51.453200 DQ Delay:
6543 00:44:51.456230 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6544 00:44:51.456713 DQ4 =8, DQ5 =0, DQ6 =24, DQ7 =16
6545 00:44:51.459942 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =8
6546 00:44:51.463446 DQ12 =8, DQ13 =16, DQ14 =16, DQ15 =16
6547 00:44:51.463970
6548 00:44:51.464309
6549 00:44:51.466945 ==
6550 00:44:51.469853 Dram Type= 6, Freq= 0, CH_0, rank 1
6551 00:44:51.473170 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6552 00:44:51.473603 ==
6553 00:44:51.473946
6554 00:44:51.474340
6555 00:44:51.476330 TX Vref Scan disable
6556 00:44:51.476789 == TX Byte 0 ==
6557 00:44:51.479832 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6558 00:44:51.486522 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6559 00:44:51.486952 == TX Byte 1 ==
6560 00:44:51.489478 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6561 00:44:51.496588 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6562 00:44:51.497021 ==
6563 00:44:51.499330 Dram Type= 6, Freq= 0, CH_0, rank 1
6564 00:44:51.502877 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6565 00:44:51.503309 ==
6566 00:44:51.503652
6567 00:44:51.503963
6568 00:44:51.506345 TX Vref Scan disable
6569 00:44:51.506774 == TX Byte 0 ==
6570 00:44:51.509994 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6571 00:44:51.516319 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6572 00:44:51.516787 == TX Byte 1 ==
6573 00:44:51.519840 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6574 00:44:51.526434 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6575 00:44:51.526870
6576 00:44:51.527211 [DATLAT]
6577 00:44:51.527528 Freq=400, CH0 RK1
6578 00:44:51.527836
6579 00:44:51.529475 DATLAT Default: 0xe
6580 00:44:51.529906 0, 0xFFFF, sum = 0
6581 00:44:51.532811 1, 0xFFFF, sum = 0
6582 00:44:51.533249 2, 0xFFFF, sum = 0
6583 00:44:51.536317 3, 0xFFFF, sum = 0
6584 00:44:51.539880 4, 0xFFFF, sum = 0
6585 00:44:51.540408 5, 0xFFFF, sum = 0
6586 00:44:51.543240 6, 0xFFFF, sum = 0
6587 00:44:51.543773 7, 0xFFFF, sum = 0
6588 00:44:51.546493 8, 0xFFFF, sum = 0
6589 00:44:51.547024 9, 0xFFFF, sum = 0
6590 00:44:51.549610 10, 0xFFFF, sum = 0
6591 00:44:51.550045 11, 0xFFFF, sum = 0
6592 00:44:51.552777 12, 0xFFFF, sum = 0
6593 00:44:51.553212 13, 0x0, sum = 1
6594 00:44:51.556437 14, 0x0, sum = 2
6595 00:44:51.556914 15, 0x0, sum = 3
6596 00:44:51.560127 16, 0x0, sum = 4
6597 00:44:51.560690 best_step = 14
6598 00:44:51.561038
6599 00:44:51.561357 ==
6600 00:44:51.563055 Dram Type= 6, Freq= 0, CH_0, rank 1
6601 00:44:51.566511 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6602 00:44:51.566942 ==
6603 00:44:51.569489 RX Vref Scan: 0
6604 00:44:51.570005
6605 00:44:51.572988 RX Vref 0 -> 0, step: 1
6606 00:44:51.573486
6607 00:44:51.573831 RX Delay -311 -> 252, step: 8
6608 00:44:51.581574 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6609 00:44:51.584868 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6610 00:44:51.588270 iDelay=217, Bit 2, Center -24 (-247 ~ 200) 448
6611 00:44:51.591592 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6612 00:44:51.598379 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6613 00:44:51.601739 iDelay=217, Bit 5, Center -28 (-255 ~ 200) 456
6614 00:44:51.604928 iDelay=217, Bit 6, Center -12 (-239 ~ 216) 456
6615 00:44:51.608188 iDelay=217, Bit 7, Center -12 (-239 ~ 216) 456
6616 00:44:51.615019 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6617 00:44:51.618222 iDelay=217, Bit 9, Center -40 (-263 ~ 184) 448
6618 00:44:51.621661 iDelay=217, Bit 10, Center -24 (-247 ~ 200) 448
6619 00:44:51.624642 iDelay=217, Bit 11, Center -36 (-263 ~ 192) 456
6620 00:44:51.631485 iDelay=217, Bit 12, Center -24 (-247 ~ 200) 448
6621 00:44:51.635021 iDelay=217, Bit 13, Center -24 (-247 ~ 200) 448
6622 00:44:51.637906 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
6623 00:44:51.644981 iDelay=217, Bit 15, Center -20 (-239 ~ 200) 440
6624 00:44:51.645503 ==
6625 00:44:51.648341 Dram Type= 6, Freq= 0, CH_0, rank 1
6626 00:44:51.651473 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6627 00:44:51.651994 ==
6628 00:44:51.652338 DQS Delay:
6629 00:44:51.654953 DQS0 = 28, DQS1 = 40
6630 00:44:51.655450 DQM Delay:
6631 00:44:51.658188 DQM0 = 9, DQM1 = 12
6632 00:44:51.658710 DQ Delay:
6633 00:44:51.661438 DQ0 =12, DQ1 =12, DQ2 =4, DQ3 =4
6634 00:44:51.664884 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =16
6635 00:44:51.668052 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =4
6636 00:44:51.671430 DQ12 =16, DQ13 =16, DQ14 =20, DQ15 =20
6637 00:44:51.671946
6638 00:44:51.672282
6639 00:44:51.678188 [DQSOSCAuto] RK1, (LSB)MR18= 0xc576, (MSB)MR19= 0xc0c, tDQSOscB0 = 394 ps tDQSOscB1 = 385 ps
6640 00:44:51.681343 CH0 RK1: MR19=C0C, MR18=C576
6641 00:44:51.687921 CH0_RK1: MR19=0xC0C, MR18=0xC576, DQSOSC=385, MR23=63, INC=398, DEC=265
6642 00:44:51.691458 [RxdqsGatingPostProcess] freq 400
6643 00:44:51.697885 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6644 00:44:51.698382 best DQS0 dly(2T, 0.5T) = (0, 10)
6645 00:44:51.701123 best DQS1 dly(2T, 0.5T) = (0, 10)
6646 00:44:51.704661 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6647 00:44:51.707721 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6648 00:44:51.710937 best DQS0 dly(2T, 0.5T) = (0, 10)
6649 00:44:51.714497 best DQS1 dly(2T, 0.5T) = (0, 10)
6650 00:44:51.717890 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6651 00:44:51.721039 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6652 00:44:51.724613 Pre-setting of DQS Precalculation
6653 00:44:51.730822 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6654 00:44:51.731314 ==
6655 00:44:51.734267 Dram Type= 6, Freq= 0, CH_1, rank 0
6656 00:44:51.737893 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6657 00:44:51.738495 ==
6658 00:44:51.741381 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6659 00:44:51.748341 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=31, u1VrefScanEnd=31
6660 00:44:51.751409 [CA 0] Center 36 (8~64) winsize 57
6661 00:44:51.754550 [CA 1] Center 36 (8~64) winsize 57
6662 00:44:51.757932 [CA 2] Center 36 (8~64) winsize 57
6663 00:44:51.761578 [CA 3] Center 36 (8~64) winsize 57
6664 00:44:51.764377 [CA 4] Center 36 (8~64) winsize 57
6665 00:44:51.767943 [CA 5] Center 36 (8~64) winsize 57
6666 00:44:51.768481
6667 00:44:51.771204 [CmdBusTrainingLP45] Vref(ca) range 1: 31
6668 00:44:51.771741
6669 00:44:51.774667 [CATrainingPosCal] consider 1 rank data
6670 00:44:51.778007 u2DelayCellTimex100 = 270/100 ps
6671 00:44:51.780834 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6672 00:44:51.784351 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6673 00:44:51.787580 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6674 00:44:51.791245 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6675 00:44:51.794302 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6676 00:44:51.801359 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6677 00:44:51.801878
6678 00:44:51.804731 CA PerBit enable=1, Macro0, CA PI delay=36
6679 00:44:51.805224
6680 00:44:51.807709 [CBTSetCACLKResult] CA Dly = 36
6681 00:44:51.808237 CS Dly: 1 (0~32)
6682 00:44:51.808624 ==
6683 00:44:51.810985 Dram Type= 6, Freq= 0, CH_1, rank 1
6684 00:44:51.814217 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6685 00:44:51.817573 ==
6686 00:44:51.821051 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6687 00:44:51.827743 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6688 00:44:51.830953 [CA 0] Center 36 (8~64) winsize 57
6689 00:44:51.834389 [CA 1] Center 36 (8~64) winsize 57
6690 00:44:51.837611 [CA 2] Center 36 (8~64) winsize 57
6691 00:44:51.841079 [CA 3] Center 36 (8~64) winsize 57
6692 00:44:51.844218 [CA 4] Center 36 (8~64) winsize 57
6693 00:44:51.847967 [CA 5] Center 36 (8~64) winsize 57
6694 00:44:51.848502
6695 00:44:51.851193 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6696 00:44:51.851725
6697 00:44:51.854559 [CATrainingPosCal] consider 2 rank data
6698 00:44:51.857800 u2DelayCellTimex100 = 270/100 ps
6699 00:44:51.861240 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6700 00:44:51.864388 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6701 00:44:51.867900 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6702 00:44:51.870906 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6703 00:44:51.874421 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6704 00:44:51.877856 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6705 00:44:51.878399
6706 00:44:51.880756 CA PerBit enable=1, Macro0, CA PI delay=36
6707 00:44:51.881188
6708 00:44:51.884177 [CBTSetCACLKResult] CA Dly = 36
6709 00:44:51.887494 CS Dly: 1 (0~32)
6710 00:44:51.887990
6711 00:44:51.890904 ----->DramcWriteLeveling(PI) begin...
6712 00:44:51.891405 ==
6713 00:44:51.894569 Dram Type= 6, Freq= 0, CH_1, rank 0
6714 00:44:51.897955 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6715 00:44:51.898496 ==
6716 00:44:51.901319 Write leveling (Byte 0): 40 => 8
6717 00:44:51.904664 Write leveling (Byte 1): 32 => 0
6718 00:44:51.907514 DramcWriteLeveling(PI) end<-----
6719 00:44:51.907948
6720 00:44:51.908289 ==
6721 00:44:51.910958 Dram Type= 6, Freq= 0, CH_1, rank 0
6722 00:44:51.914395 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6723 00:44:51.914944 ==
6724 00:44:51.917676 [Gating] SW mode calibration
6725 00:44:51.924335 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6726 00:44:51.931058 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6727 00:44:51.934520 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6728 00:44:51.937493 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6729 00:44:51.944257 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6730 00:44:51.947627 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6731 00:44:51.950922 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6732 00:44:51.957630 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6733 00:44:51.960517 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6734 00:44:51.964529 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6735 00:44:51.970854 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6736 00:44:51.971378 Total UI for P1: 0, mck2ui 16
6737 00:44:51.977886 best dqsien dly found for B0: ( 0, 14, 24)
6738 00:44:51.978421 Total UI for P1: 0, mck2ui 16
6739 00:44:51.984188 best dqsien dly found for B1: ( 0, 14, 24)
6740 00:44:51.987490 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6741 00:44:51.990650 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6742 00:44:51.991079
6743 00:44:51.994154 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6744 00:44:51.997655 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6745 00:44:52.000958 [Gating] SW calibration Done
6746 00:44:52.001493 ==
6747 00:44:52.004214 Dram Type= 6, Freq= 0, CH_1, rank 0
6748 00:44:52.007341 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6749 00:44:52.007773 ==
6750 00:44:52.010637 RX Vref Scan: 0
6751 00:44:52.011062
6752 00:44:52.011401 RX Vref 0 -> 0, step: 1
6753 00:44:52.011719
6754 00:44:52.014460 RX Delay -410 -> 252, step: 16
6755 00:44:52.020922 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6756 00:44:52.024365 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6757 00:44:52.027550 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6758 00:44:52.030590 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6759 00:44:52.037832 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6760 00:44:52.040325 iDelay=230, Bit 5, Center -11 (-250 ~ 229) 480
6761 00:44:52.044099 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6762 00:44:52.047247 iDelay=230, Bit 7, Center -27 (-266 ~ 213) 480
6763 00:44:52.054085 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6764 00:44:52.057090 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6765 00:44:52.061022 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6766 00:44:52.063901 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6767 00:44:52.070385 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6768 00:44:52.073916 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6769 00:44:52.076811 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6770 00:44:52.083770 iDelay=230, Bit 15, Center -19 (-266 ~ 229) 496
6771 00:44:52.084303 ==
6772 00:44:52.086675 Dram Type= 6, Freq= 0, CH_1, rank 0
6773 00:44:52.090446 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6774 00:44:52.091013 ==
6775 00:44:52.091573 DQS Delay:
6776 00:44:52.093454 DQS0 = 27, DQS1 = 43
6777 00:44:52.093884 DQM Delay:
6778 00:44:52.096709 DQM0 = 8, DQM1 = 17
6779 00:44:52.097100 DQ Delay:
6780 00:44:52.100695 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6781 00:44:52.103224 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =0
6782 00:44:52.106924 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6783 00:44:52.110072 DQ12 =32, DQ13 =24, DQ14 =16, DQ15 =24
6784 00:44:52.110499
6785 00:44:52.110836
6786 00:44:52.111148 ==
6787 00:44:52.113427 Dram Type= 6, Freq= 0, CH_1, rank 0
6788 00:44:52.116740 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6789 00:44:52.117173 ==
6790 00:44:52.117615
6791 00:44:52.118170
6792 00:44:52.120261 TX Vref Scan disable
6793 00:44:52.120846 == TX Byte 0 ==
6794 00:44:52.126495 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6795 00:44:52.129997 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6796 00:44:52.130427 == TX Byte 1 ==
6797 00:44:52.136650 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6798 00:44:52.140035 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6799 00:44:52.140458 ==
6800 00:44:52.143769 Dram Type= 6, Freq= 0, CH_1, rank 0
6801 00:44:52.146683 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6802 00:44:52.147133 ==
6803 00:44:52.147467
6804 00:44:52.147771
6805 00:44:52.149927 TX Vref Scan disable
6806 00:44:52.150361 == TX Byte 0 ==
6807 00:44:52.156659 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6808 00:44:52.159840 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6809 00:44:52.160259 == TX Byte 1 ==
6810 00:44:52.166488 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6811 00:44:52.170060 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6812 00:44:52.170590
6813 00:44:52.170930 [DATLAT]
6814 00:44:52.173408 Freq=400, CH1 RK0
6815 00:44:52.173971
6816 00:44:52.174361 DATLAT Default: 0xf
6817 00:44:52.176696 0, 0xFFFF, sum = 0
6818 00:44:52.177142 1, 0xFFFF, sum = 0
6819 00:44:52.180265 2, 0xFFFF, sum = 0
6820 00:44:52.180804 3, 0xFFFF, sum = 0
6821 00:44:52.183323 4, 0xFFFF, sum = 0
6822 00:44:52.183749 5, 0xFFFF, sum = 0
6823 00:44:52.187022 6, 0xFFFF, sum = 0
6824 00:44:52.189714 7, 0xFFFF, sum = 0
6825 00:44:52.190142 8, 0xFFFF, sum = 0
6826 00:44:52.193918 9, 0xFFFF, sum = 0
6827 00:44:52.194451 10, 0xFFFF, sum = 0
6828 00:44:52.196912 11, 0xFFFF, sum = 0
6829 00:44:52.197448 12, 0xFFFF, sum = 0
6830 00:44:52.200316 13, 0x0, sum = 1
6831 00:44:52.200875 14, 0x0, sum = 2
6832 00:44:52.203729 15, 0x0, sum = 3
6833 00:44:52.204279 16, 0x0, sum = 4
6834 00:44:52.204653 best_step = 14
6835 00:44:52.206605
6836 00:44:52.207126 ==
6837 00:44:52.209848 Dram Type= 6, Freq= 0, CH_1, rank 0
6838 00:44:52.213375 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6839 00:44:52.213907 ==
6840 00:44:52.214245 RX Vref Scan: 1
6841 00:44:52.214557
6842 00:44:52.216934 RX Vref 0 -> 0, step: 1
6843 00:44:52.217459
6844 00:44:52.219923 RX Delay -327 -> 252, step: 8
6845 00:44:52.220474
6846 00:44:52.223053 Set Vref, RX VrefLevel [Byte0]: 51
6847 00:44:52.226713 [Byte1]: 59
6848 00:44:52.230047
6849 00:44:52.230467 Final RX Vref Byte 0 = 51 to rank0
6850 00:44:52.233438 Final RX Vref Byte 1 = 59 to rank0
6851 00:44:52.237062 Final RX Vref Byte 0 = 51 to rank1
6852 00:44:52.240268 Final RX Vref Byte 1 = 59 to rank1==
6853 00:44:52.243697 Dram Type= 6, Freq= 0, CH_1, rank 0
6854 00:44:52.250188 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6855 00:44:52.250696 ==
6856 00:44:52.251036 DQS Delay:
6857 00:44:52.253518 DQS0 = 32, DQS1 = 40
6858 00:44:52.253938 DQM Delay:
6859 00:44:52.254273 DQM0 = 10, DQM1 = 13
6860 00:44:52.257200 DQ Delay:
6861 00:44:52.260398 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =8
6862 00:44:52.260994 DQ4 =8, DQ5 =24, DQ6 =20, DQ7 =8
6863 00:44:52.263416 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6864 00:44:52.266919 DQ12 =24, DQ13 =20, DQ14 =16, DQ15 =16
6865 00:44:52.267439
6866 00:44:52.267775
6867 00:44:52.277082 [DQSOSCAuto] RK0, (LSB)MR18= 0x9bd6, (MSB)MR19= 0xc0c, tDQSOscB0 = 383 ps tDQSOscB1 = 390 ps
6868 00:44:52.280329 CH1 RK0: MR19=C0C, MR18=9BD6
6869 00:44:52.286934 CH1_RK0: MR19=0xC0C, MR18=0x9BD6, DQSOSC=383, MR23=63, INC=402, DEC=268
6870 00:44:52.287404 ==
6871 00:44:52.289908 Dram Type= 6, Freq= 0, CH_1, rank 1
6872 00:44:52.293252 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6873 00:44:52.293720 ==
6874 00:44:52.296693 [Gating] SW mode calibration
6875 00:44:52.303576 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6876 00:44:52.306647 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6877 00:44:52.313391 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6878 00:44:52.316740 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6879 00:44:52.320500 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6880 00:44:52.326437 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6881 00:44:52.329895 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6882 00:44:52.333412 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6883 00:44:52.339906 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6884 00:44:52.343193 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6885 00:44:52.346475 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6886 00:44:52.349761 Total UI for P1: 0, mck2ui 16
6887 00:44:52.353110 best dqsien dly found for B0: ( 0, 14, 24)
6888 00:44:52.356374 Total UI for P1: 0, mck2ui 16
6889 00:44:52.360108 best dqsien dly found for B1: ( 0, 14, 24)
6890 00:44:52.362923 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6891 00:44:52.366315 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6892 00:44:52.369589
6893 00:44:52.372993 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6894 00:44:52.376125 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6895 00:44:52.379596 [Gating] SW calibration Done
6896 00:44:52.380100 ==
6897 00:44:52.382706 Dram Type= 6, Freq= 0, CH_1, rank 1
6898 00:44:52.386304 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6899 00:44:52.386776 ==
6900 00:44:52.387147 RX Vref Scan: 0
6901 00:44:52.387491
6902 00:44:52.389438 RX Vref 0 -> 0, step: 1
6903 00:44:52.389952
6904 00:44:52.392870 RX Delay -410 -> 252, step: 16
6905 00:44:52.396345 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6906 00:44:52.403163 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6907 00:44:52.406579 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6908 00:44:52.409893 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6909 00:44:52.413217 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6910 00:44:52.419547 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6911 00:44:52.423066 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6912 00:44:52.426203 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6913 00:44:52.429690 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6914 00:44:52.432899 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6915 00:44:52.440029 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6916 00:44:52.443095 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6917 00:44:52.446366 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6918 00:44:52.452991 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6919 00:44:52.456156 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6920 00:44:52.460096 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6921 00:44:52.460714 ==
6922 00:44:52.463210 Dram Type= 6, Freq= 0, CH_1, rank 1
6923 00:44:52.466595 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6924 00:44:52.467175 ==
6925 00:44:52.469335 DQS Delay:
6926 00:44:52.469801 DQS0 = 35, DQS1 = 43
6927 00:44:52.472757 DQM Delay:
6928 00:44:52.473225 DQM0 = 18, DQM1 = 18
6929 00:44:52.476510 DQ Delay:
6930 00:44:52.477165 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6931 00:44:52.479525 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6932 00:44:52.482694 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6933 00:44:52.486247 DQ12 =32, DQ13 =24, DQ14 =16, DQ15 =32
6934 00:44:52.486855
6935 00:44:52.487235
6936 00:44:52.489415 ==
6937 00:44:52.492652 Dram Type= 6, Freq= 0, CH_1, rank 1
6938 00:44:52.495920 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6939 00:44:52.496388 ==
6940 00:44:52.496900
6941 00:44:52.497258
6942 00:44:52.499163 TX Vref Scan disable
6943 00:44:52.499677 == TX Byte 0 ==
6944 00:44:52.502820 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6945 00:44:52.509189 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6946 00:44:52.509658 == TX Byte 1 ==
6947 00:44:52.512730 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6948 00:44:52.516157 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6949 00:44:52.519809 ==
6950 00:44:52.522945 Dram Type= 6, Freq= 0, CH_1, rank 1
6951 00:44:52.526154 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6952 00:44:52.526690 ==
6953 00:44:52.527032
6954 00:44:52.527343
6955 00:44:52.529222 TX Vref Scan disable
6956 00:44:52.529645 == TX Byte 0 ==
6957 00:44:52.532723 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6958 00:44:52.536098 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6959 00:44:52.539318 == TX Byte 1 ==
6960 00:44:52.542899 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6961 00:44:52.546332 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6962 00:44:52.549370
6963 00:44:52.549817 [DATLAT]
6964 00:44:52.550284 Freq=400, CH1 RK1
6965 00:44:52.550741
6966 00:44:52.552811 DATLAT Default: 0xe
6967 00:44:52.553297 0, 0xFFFF, sum = 0
6968 00:44:52.556290 1, 0xFFFF, sum = 0
6969 00:44:52.556914 2, 0xFFFF, sum = 0
6970 00:44:52.559831 3, 0xFFFF, sum = 0
6971 00:44:52.560403 4, 0xFFFF, sum = 0
6972 00:44:52.562516 5, 0xFFFF, sum = 0
6973 00:44:52.566177 6, 0xFFFF, sum = 0
6974 00:44:52.566659 7, 0xFFFF, sum = 0
6975 00:44:52.569435 8, 0xFFFF, sum = 0
6976 00:44:52.569883 9, 0xFFFF, sum = 0
6977 00:44:52.572362 10, 0xFFFF, sum = 0
6978 00:44:52.572899 11, 0xFFFF, sum = 0
6979 00:44:52.576214 12, 0xFFFF, sum = 0
6980 00:44:52.576793 13, 0x0, sum = 1
6981 00:44:52.579463 14, 0x0, sum = 2
6982 00:44:52.580004 15, 0x0, sum = 3
6983 00:44:52.582668 16, 0x0, sum = 4
6984 00:44:52.583114 best_step = 14
6985 00:44:52.583559
6986 00:44:52.583977 ==
6987 00:44:52.585481 Dram Type= 6, Freq= 0, CH_1, rank 1
6988 00:44:52.589149 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6989 00:44:52.589693 ==
6990 00:44:52.592148 RX Vref Scan: 0
6991 00:44:52.592603
6992 00:44:52.595563 RX Vref 0 -> 0, step: 1
6993 00:44:52.596002
6994 00:44:52.596438 RX Delay -327 -> 252, step: 8
6995 00:44:52.604482 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
6996 00:44:52.608186 iDelay=217, Bit 1, Center -24 (-247 ~ 200) 448
6997 00:44:52.611339 iDelay=217, Bit 2, Center -32 (-255 ~ 192) 448
6998 00:44:52.614611 iDelay=217, Bit 3, Center -16 (-239 ~ 208) 448
6999 00:44:52.621468 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
7000 00:44:52.624682 iDelay=217, Bit 5, Center -12 (-239 ~ 216) 456
7001 00:44:52.628333 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
7002 00:44:52.630874 iDelay=217, Bit 7, Center -24 (-247 ~ 200) 448
7003 00:44:52.637803 iDelay=217, Bit 8, Center -40 (-271 ~ 192) 464
7004 00:44:52.641190 iDelay=217, Bit 9, Center -36 (-263 ~ 192) 456
7005 00:44:52.644355 iDelay=217, Bit 10, Center -24 (-255 ~ 208) 464
7006 00:44:52.648278 iDelay=217, Bit 11, Center -32 (-263 ~ 200) 464
7007 00:44:52.654500 iDelay=217, Bit 12, Center -16 (-247 ~ 216) 464
7008 00:44:52.657786 iDelay=217, Bit 13, Center -20 (-247 ~ 208) 456
7009 00:44:52.661195 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
7010 00:44:52.668193 iDelay=217, Bit 15, Center -16 (-247 ~ 216) 464
7011 00:44:52.668807 ==
7012 00:44:52.671170 Dram Type= 6, Freq= 0, CH_1, rank 1
7013 00:44:52.674513 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7014 00:44:52.675084 ==
7015 00:44:52.675459 DQS Delay:
7016 00:44:52.677724 DQS0 = 32, DQS1 = 40
7017 00:44:52.678202 DQM Delay:
7018 00:44:52.681413 DQM0 = 13, DQM1 = 14
7019 00:44:52.681981 DQ Delay:
7020 00:44:52.684206 DQ0 =20, DQ1 =8, DQ2 =0, DQ3 =16
7021 00:44:52.687393 DQ4 =16, DQ5 =20, DQ6 =20, DQ7 =8
7022 00:44:52.690829 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
7023 00:44:52.694082 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =24
7024 00:44:52.694547
7025 00:44:52.694910
7026 00:44:52.701131 [DQSOSCAuto] RK1, (LSB)MR18= 0xaf58, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 388 ps
7027 00:44:52.704843 CH1 RK1: MR19=C0C, MR18=AF58
7028 00:44:52.711169 CH1_RK1: MR19=0xC0C, MR18=0xAF58, DQSOSC=388, MR23=63, INC=392, DEC=261
7029 00:44:52.714429 [RxdqsGatingPostProcess] freq 400
7030 00:44:52.720984 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7031 00:44:52.721515 best DQS0 dly(2T, 0.5T) = (0, 10)
7032 00:44:52.724036 best DQS1 dly(2T, 0.5T) = (0, 10)
7033 00:44:52.727465 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7034 00:44:52.730776 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7035 00:44:52.734214 best DQS0 dly(2T, 0.5T) = (0, 10)
7036 00:44:52.737387 best DQS1 dly(2T, 0.5T) = (0, 10)
7037 00:44:52.740934 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7038 00:44:52.744318 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7039 00:44:52.747722 Pre-setting of DQS Precalculation
7040 00:44:52.754449 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7041 00:44:52.760819 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7042 00:44:52.767657 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7043 00:44:52.768227
7044 00:44:52.768646
7045 00:44:52.770959 [Calibration Summary] 800 Mbps
7046 00:44:52.771539 CH 0, Rank 0
7047 00:44:52.774092 SW Impedance : PASS
7048 00:44:52.777123 DUTY Scan : NO K
7049 00:44:52.777593 ZQ Calibration : PASS
7050 00:44:52.780741 Jitter Meter : NO K
7051 00:44:52.781207 CBT Training : PASS
7052 00:44:52.783744 Write leveling : PASS
7053 00:44:52.787197 RX DQS gating : PASS
7054 00:44:52.787665 RX DQ/DQS(RDDQC) : PASS
7055 00:44:52.790962 TX DQ/DQS : PASS
7056 00:44:52.793778 RX DATLAT : PASS
7057 00:44:52.794249 RX DQ/DQS(Engine): PASS
7058 00:44:52.797394 TX OE : NO K
7059 00:44:52.797962 All Pass.
7060 00:44:52.798336
7061 00:44:52.800625 CH 0, Rank 1
7062 00:44:52.801191 SW Impedance : PASS
7063 00:44:52.803838 DUTY Scan : NO K
7064 00:44:52.807492 ZQ Calibration : PASS
7065 00:44:52.808056 Jitter Meter : NO K
7066 00:44:52.811024 CBT Training : PASS
7067 00:44:52.813554 Write leveling : NO K
7068 00:44:52.814024 RX DQS gating : PASS
7069 00:44:52.817148 RX DQ/DQS(RDDQC) : PASS
7070 00:44:52.820279 TX DQ/DQS : PASS
7071 00:44:52.820788 RX DATLAT : PASS
7072 00:44:52.823771 RX DQ/DQS(Engine): PASS
7073 00:44:52.824233 TX OE : NO K
7074 00:44:52.826873 All Pass.
7075 00:44:52.827336
7076 00:44:52.827670 CH 1, Rank 0
7077 00:44:52.830272 SW Impedance : PASS
7078 00:44:52.830740 DUTY Scan : NO K
7079 00:44:52.833507 ZQ Calibration : PASS
7080 00:44:52.837044 Jitter Meter : NO K
7081 00:44:52.837613 CBT Training : PASS
7082 00:44:52.840225 Write leveling : PASS
7083 00:44:52.844013 RX DQS gating : PASS
7084 00:44:52.844604 RX DQ/DQS(RDDQC) : PASS
7085 00:44:52.846894 TX DQ/DQS : PASS
7086 00:44:52.850237 RX DATLAT : PASS
7087 00:44:52.850822 RX DQ/DQS(Engine): PASS
7088 00:44:52.853708 TX OE : NO K
7089 00:44:52.854193 All Pass.
7090 00:44:52.854532
7091 00:44:52.857043 CH 1, Rank 1
7092 00:44:52.857463 SW Impedance : PASS
7093 00:44:52.860069 DUTY Scan : NO K
7094 00:44:52.863652 ZQ Calibration : PASS
7095 00:44:52.864186 Jitter Meter : NO K
7096 00:44:52.867066 CBT Training : PASS
7097 00:44:52.870395 Write leveling : NO K
7098 00:44:52.870821 RX DQS gating : PASS
7099 00:44:52.873769 RX DQ/DQS(RDDQC) : PASS
7100 00:44:52.876519 TX DQ/DQS : PASS
7101 00:44:52.876994 RX DATLAT : PASS
7102 00:44:52.880309 RX DQ/DQS(Engine): PASS
7103 00:44:52.880770 TX OE : NO K
7104 00:44:52.883057 All Pass.
7105 00:44:52.883476
7106 00:44:52.883810 DramC Write-DBI off
7107 00:44:52.886768 PER_BANK_REFRESH: Hybrid Mode
7108 00:44:52.890151 TX_TRACKING: ON
7109 00:44:52.896865 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7110 00:44:52.900342 [FAST_K] Save calibration result to emmc
7111 00:44:52.906438 dramc_set_vcore_voltage set vcore to 725000
7112 00:44:52.906961 Read voltage for 1600, 0
7113 00:44:52.910013 Vio18 = 0
7114 00:44:52.910551 Vcore = 725000
7115 00:44:52.910900 Vdram = 0
7116 00:44:52.911220 Vddq = 0
7117 00:44:52.913079 Vmddr = 0
7118 00:44:52.916632 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7119 00:44:52.923181 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7120 00:44:52.927060 MEM_TYPE=3, freq_sel=13
7121 00:44:52.927489 sv_algorithm_assistance_LP4_3733
7122 00:44:52.932904 ============ PULL DRAM RESETB DOWN ============
7123 00:44:52.936590 ========== PULL DRAM RESETB DOWN end =========
7124 00:44:52.939739 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7125 00:44:52.943006 ===================================
7126 00:44:52.946358 LPDDR4 DRAM CONFIGURATION
7127 00:44:52.949925 ===================================
7128 00:44:52.952907 EX_ROW_EN[0] = 0x0
7129 00:44:52.953331 EX_ROW_EN[1] = 0x0
7130 00:44:52.956167 LP4Y_EN = 0x0
7131 00:44:52.956618 WORK_FSP = 0x1
7132 00:44:52.959875 WL = 0x5
7133 00:44:52.960398 RL = 0x5
7134 00:44:52.963383 BL = 0x2
7135 00:44:52.963907 RPST = 0x0
7136 00:44:52.966619 RD_PRE = 0x0
7137 00:44:52.967143 WR_PRE = 0x1
7138 00:44:52.970230 WR_PST = 0x1
7139 00:44:52.970756 DBI_WR = 0x0
7140 00:44:52.973090 DBI_RD = 0x0
7141 00:44:52.973615 OTF = 0x1
7142 00:44:52.976593 ===================================
7143 00:44:52.979845 ===================================
7144 00:44:52.983181 ANA top config
7145 00:44:52.986069 ===================================
7146 00:44:52.989597 DLL_ASYNC_EN = 0
7147 00:44:52.990024 ALL_SLAVE_EN = 0
7148 00:44:52.993192 NEW_RANK_MODE = 1
7149 00:44:52.996514 DLL_IDLE_MODE = 1
7150 00:44:52.999606 LP45_APHY_COMB_EN = 1
7151 00:44:53.003055 TX_ODT_DIS = 0
7152 00:44:53.003583 NEW_8X_MODE = 1
7153 00:44:53.006468 ===================================
7154 00:44:53.009722 ===================================
7155 00:44:53.012691 data_rate = 3200
7156 00:44:53.016294 CKR = 1
7157 00:44:53.019709 DQ_P2S_RATIO = 8
7158 00:44:53.023112 ===================================
7159 00:44:53.026251 CA_P2S_RATIO = 8
7160 00:44:53.026680 DQ_CA_OPEN = 0
7161 00:44:53.029639 DQ_SEMI_OPEN = 0
7162 00:44:53.032737 CA_SEMI_OPEN = 0
7163 00:44:53.035957 CA_FULL_RATE = 0
7164 00:44:53.039834 DQ_CKDIV4_EN = 0
7165 00:44:53.042553 CA_CKDIV4_EN = 0
7166 00:44:53.042986 CA_PREDIV_EN = 0
7167 00:44:53.045842 PH8_DLY = 12
7168 00:44:53.049575 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7169 00:44:53.052804 DQ_AAMCK_DIV = 4
7170 00:44:53.056132 CA_AAMCK_DIV = 4
7171 00:44:53.059633 CA_ADMCK_DIV = 4
7172 00:44:53.060160 DQ_TRACK_CA_EN = 0
7173 00:44:53.062533 CA_PICK = 1600
7174 00:44:53.065986 CA_MCKIO = 1600
7175 00:44:53.069316 MCKIO_SEMI = 0
7176 00:44:53.073153 PLL_FREQ = 3068
7177 00:44:53.076110 DQ_UI_PI_RATIO = 32
7178 00:44:53.079236 CA_UI_PI_RATIO = 0
7179 00:44:53.083112 ===================================
7180 00:44:53.085712 ===================================
7181 00:44:53.086144 memory_type:LPDDR4
7182 00:44:53.089433 GP_NUM : 10
7183 00:44:53.093193 SRAM_EN : 1
7184 00:44:53.093718 MD32_EN : 0
7185 00:44:53.096588 ===================================
7186 00:44:53.099568 [ANA_INIT] >>>>>>>>>>>>>>
7187 00:44:53.103106 <<<<<< [CONFIGURE PHASE]: ANA_TX
7188 00:44:53.106463 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7189 00:44:53.109763 ===================================
7190 00:44:53.113238 data_rate = 3200,PCW = 0X7600
7191 00:44:53.116046 ===================================
7192 00:44:53.119847 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7193 00:44:53.122925 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7194 00:44:53.129511 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7195 00:44:53.132923 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7196 00:44:53.135966 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7197 00:44:53.139437 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7198 00:44:53.143011 [ANA_INIT] flow start
7199 00:44:53.146163 [ANA_INIT] PLL >>>>>>>>
7200 00:44:53.146732 [ANA_INIT] PLL <<<<<<<<
7201 00:44:53.149129 [ANA_INIT] MIDPI >>>>>>>>
7202 00:44:53.152799 [ANA_INIT] MIDPI <<<<<<<<
7203 00:44:53.153365 [ANA_INIT] DLL >>>>>>>>
7204 00:44:53.156318 [ANA_INIT] DLL <<<<<<<<
7205 00:44:53.159610 [ANA_INIT] flow end
7206 00:44:53.162775 ============ LP4 DIFF to SE enter ============
7207 00:44:53.166078 ============ LP4 DIFF to SE exit ============
7208 00:44:53.169256 [ANA_INIT] <<<<<<<<<<<<<
7209 00:44:53.173004 [Flow] Enable top DCM control >>>>>
7210 00:44:53.176349 [Flow] Enable top DCM control <<<<<
7211 00:44:53.179833 Enable DLL master slave shuffle
7212 00:44:53.182832 ==============================================================
7213 00:44:53.186350 Gating Mode config
7214 00:44:53.192756 ==============================================================
7215 00:44:53.193320 Config description:
7216 00:44:53.203253 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7217 00:44:53.209485 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7218 00:44:53.212719 SELPH_MODE 0: By rank 1: By Phase
7219 00:44:53.219482 ==============================================================
7220 00:44:53.222883 GAT_TRACK_EN = 1
7221 00:44:53.225901 RX_GATING_MODE = 2
7222 00:44:53.229374 RX_GATING_TRACK_MODE = 2
7223 00:44:53.232364 SELPH_MODE = 1
7224 00:44:53.235717 PICG_EARLY_EN = 1
7225 00:44:53.239034 VALID_LAT_VALUE = 1
7226 00:44:53.242625 ==============================================================
7227 00:44:53.245907 Enter into Gating configuration >>>>
7228 00:44:53.249293 Exit from Gating configuration <<<<
7229 00:44:53.252642 Enter into DVFS_PRE_config >>>>>
7230 00:44:53.265929 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7231 00:44:53.266500 Exit from DVFS_PRE_config <<<<<
7232 00:44:53.268925 Enter into PICG configuration >>>>
7233 00:44:53.272391 Exit from PICG configuration <<<<
7234 00:44:53.275693 [RX_INPUT] configuration >>>>>
7235 00:44:53.278788 [RX_INPUT] configuration <<<<<
7236 00:44:53.285966 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7237 00:44:53.288939 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7238 00:44:53.295629 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7239 00:44:53.302462 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7240 00:44:53.309198 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7241 00:44:53.316119 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7242 00:44:53.318821 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7243 00:44:53.322352 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7244 00:44:53.325850 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7245 00:44:53.332294 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7246 00:44:53.335623 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7247 00:44:53.338725 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7248 00:44:53.342096 ===================================
7249 00:44:53.345293 LPDDR4 DRAM CONFIGURATION
7250 00:44:53.348987 ===================================
7251 00:44:53.349558 EX_ROW_EN[0] = 0x0
7252 00:44:53.352196 EX_ROW_EN[1] = 0x0
7253 00:44:53.355431 LP4Y_EN = 0x0
7254 00:44:53.355899 WORK_FSP = 0x1
7255 00:44:53.358632 WL = 0x5
7256 00:44:53.359099 RL = 0x5
7257 00:44:53.362179 BL = 0x2
7258 00:44:53.362742 RPST = 0x0
7259 00:44:53.365681 RD_PRE = 0x0
7260 00:44:53.366246 WR_PRE = 0x1
7261 00:44:53.368791 WR_PST = 0x1
7262 00:44:53.369350 DBI_WR = 0x0
7263 00:44:53.372493 DBI_RD = 0x0
7264 00:44:53.373096 OTF = 0x1
7265 00:44:53.375650 ===================================
7266 00:44:53.378791 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7267 00:44:53.385256 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7268 00:44:53.388657 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7269 00:44:53.392011 ===================================
7270 00:44:53.395298 LPDDR4 DRAM CONFIGURATION
7271 00:44:53.398817 ===================================
7272 00:44:53.399288 EX_ROW_EN[0] = 0x10
7273 00:44:53.402331 EX_ROW_EN[1] = 0x0
7274 00:44:53.402797 LP4Y_EN = 0x0
7275 00:44:53.405588 WORK_FSP = 0x1
7276 00:44:53.406056 WL = 0x5
7277 00:44:53.408753 RL = 0x5
7278 00:44:53.412159 BL = 0x2
7279 00:44:53.412639 RPST = 0x0
7280 00:44:53.415074 RD_PRE = 0x0
7281 00:44:53.415546 WR_PRE = 0x1
7282 00:44:53.418579 WR_PST = 0x1
7283 00:44:53.419031 DBI_WR = 0x0
7284 00:44:53.421689 DBI_RD = 0x0
7285 00:44:53.422113 OTF = 0x1
7286 00:44:53.425046 ===================================
7287 00:44:53.432050 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7288 00:44:53.432678 ==
7289 00:44:53.435254 Dram Type= 6, Freq= 0, CH_0, rank 0
7290 00:44:53.438689 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7291 00:44:53.439214 ==
7292 00:44:53.441693 [Duty_Offset_Calibration]
7293 00:44:53.445097 B0:2 B1:0 CA:1
7294 00:44:53.445520
7295 00:44:53.448373 [DutyScan_Calibration_Flow] k_type=0
7296 00:44:53.456290
7297 00:44:53.456850 ==CLK 0==
7298 00:44:53.459364 Final CLK duty delay cell = -4
7299 00:44:53.462838 [-4] MAX Duty = 5031%(X100), DQS PI = 30
7300 00:44:53.465708 [-4] MIN Duty = 4813%(X100), DQS PI = 0
7301 00:44:53.469277 [-4] AVG Duty = 4922%(X100)
7302 00:44:53.469700
7303 00:44:53.472831 CH0 CLK Duty spec in!! Max-Min= 218%
7304 00:44:53.476291 [DutyScan_Calibration_Flow] ====Done====
7305 00:44:53.476863
7306 00:44:53.479311 [DutyScan_Calibration_Flow] k_type=1
7307 00:44:53.495381
7308 00:44:53.495914 ==DQS 0 ==
7309 00:44:53.498815 Final DQS duty delay cell = 0
7310 00:44:53.502254 [0] MAX Duty = 5249%(X100), DQS PI = 32
7311 00:44:53.505371 [0] MIN Duty = 4938%(X100), DQS PI = 62
7312 00:44:53.508761 [0] AVG Duty = 5093%(X100)
7313 00:44:53.509320
7314 00:44:53.509689 ==DQS 1 ==
7315 00:44:53.512304 Final DQS duty delay cell = -4
7316 00:44:53.515488 [-4] MAX Duty = 5125%(X100), DQS PI = 44
7317 00:44:53.519158 [-4] MIN Duty = 4844%(X100), DQS PI = 6
7318 00:44:53.522441 [-4] AVG Duty = 4984%(X100)
7319 00:44:53.523005
7320 00:44:53.525811 CH0 DQS 0 Duty spec in!! Max-Min= 311%
7321 00:44:53.526280
7322 00:44:53.528932 CH0 DQS 1 Duty spec in!! Max-Min= 281%
7323 00:44:53.531977 [DutyScan_Calibration_Flow] ====Done====
7324 00:44:53.532451
7325 00:44:53.535586 [DutyScan_Calibration_Flow] k_type=3
7326 00:44:53.553190
7327 00:44:53.553756 ==DQM 0 ==
7328 00:44:53.556783 Final DQM duty delay cell = 0
7329 00:44:53.559467 [0] MAX Duty = 5062%(X100), DQS PI = 24
7330 00:44:53.563095 [0] MIN Duty = 4813%(X100), DQS PI = 50
7331 00:44:53.563663 [0] AVG Duty = 4937%(X100)
7332 00:44:53.566312
7333 00:44:53.566871 ==DQM 1 ==
7334 00:44:53.569364 Final DQM duty delay cell = 0
7335 00:44:53.573206 [0] MAX Duty = 5249%(X100), DQS PI = 30
7336 00:44:53.576480 [0] MIN Duty = 5000%(X100), DQS PI = 20
7337 00:44:53.579731 [0] AVG Duty = 5124%(X100)
7338 00:44:53.580200
7339 00:44:53.582715 CH0 DQM 0 Duty spec in!! Max-Min= 249%
7340 00:44:53.583184
7341 00:44:53.586553 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7342 00:44:53.589599 [DutyScan_Calibration_Flow] ====Done====
7343 00:44:53.590070
7344 00:44:53.593016 [DutyScan_Calibration_Flow] k_type=2
7345 00:44:53.610089
7346 00:44:53.610620 ==DQ 0 ==
7347 00:44:53.613352 Final DQ duty delay cell = 0
7348 00:44:53.616822 [0] MAX Duty = 5124%(X100), DQS PI = 36
7349 00:44:53.620198 [0] MIN Duty = 5000%(X100), DQS PI = 0
7350 00:44:53.620770 [0] AVG Duty = 5062%(X100)
7351 00:44:53.621148
7352 00:44:53.623827 ==DQ 1 ==
7353 00:44:53.626984 Final DQ duty delay cell = 0
7354 00:44:53.630329 [0] MAX Duty = 4969%(X100), DQS PI = 44
7355 00:44:53.633368 [0] MIN Duty = 4875%(X100), DQS PI = 10
7356 00:44:53.633846 [0] AVG Duty = 4922%(X100)
7357 00:44:53.634228
7358 00:44:53.636627 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7359 00:44:53.639975
7360 00:44:53.640393 CH0 DQ 1 Duty spec in!! Max-Min= 94%
7361 00:44:53.646542 [DutyScan_Calibration_Flow] ====Done====
7362 00:44:53.646949 ==
7363 00:44:53.649988 Dram Type= 6, Freq= 0, CH_1, rank 0
7364 00:44:53.653406 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7365 00:44:53.653818 ==
7366 00:44:53.656714 [Duty_Offset_Calibration]
7367 00:44:53.657123 B0:0 B1:-1 CA:2
7368 00:44:53.657441
7369 00:44:53.659944 [DutyScan_Calibration_Flow] k_type=0
7370 00:44:53.670195
7371 00:44:53.670714 ==CLK 0==
7372 00:44:53.674014 Final CLK duty delay cell = 0
7373 00:44:53.677522 [0] MAX Duty = 5156%(X100), DQS PI = 40
7374 00:44:53.680523 [0] MIN Duty = 4906%(X100), DQS PI = 12
7375 00:44:53.680977 [0] AVG Duty = 5031%(X100)
7376 00:44:53.683573
7377 00:44:53.687041 CH1 CLK Duty spec in!! Max-Min= 250%
7378 00:44:53.690315 [DutyScan_Calibration_Flow] ====Done====
7379 00:44:53.690727
7380 00:44:53.693669 [DutyScan_Calibration_Flow] k_type=1
7381 00:44:53.709997
7382 00:44:53.710540 ==DQS 0 ==
7383 00:44:53.713161 Final DQS duty delay cell = 0
7384 00:44:53.716764 [0] MAX Duty = 5062%(X100), DQS PI = 8
7385 00:44:53.719860 [0] MIN Duty = 5000%(X100), DQS PI = 0
7386 00:44:53.720478 [0] AVG Duty = 5031%(X100)
7387 00:44:53.723117
7388 00:44:53.723577 ==DQS 1 ==
7389 00:44:53.726520 Final DQS duty delay cell = 0
7390 00:44:53.730206 [0] MAX Duty = 5187%(X100), DQS PI = 26
7391 00:44:53.733421 [0] MIN Duty = 4844%(X100), DQS PI = 0
7392 00:44:53.733880 [0] AVG Duty = 5015%(X100)
7393 00:44:53.736417
7394 00:44:53.739850 CH1 DQS 0 Duty spec in!! Max-Min= 62%
7395 00:44:53.740266
7396 00:44:53.743020 CH1 DQS 1 Duty spec in!! Max-Min= 343%
7397 00:44:53.746170 [DutyScan_Calibration_Flow] ====Done====
7398 00:44:53.746585
7399 00:44:53.749868 [DutyScan_Calibration_Flow] k_type=3
7400 00:44:53.767317
7401 00:44:53.767845 ==DQM 0 ==
7402 00:44:53.770765 Final DQM duty delay cell = 4
7403 00:44:53.774244 [4] MAX Duty = 5125%(X100), DQS PI = 24
7404 00:44:53.777579 [4] MIN Duty = 4938%(X100), DQS PI = 0
7405 00:44:53.778038 [4] AVG Duty = 5031%(X100)
7406 00:44:53.780702
7407 00:44:53.781152 ==DQM 1 ==
7408 00:44:53.784191 Final DQM duty delay cell = 0
7409 00:44:53.787474 [0] MAX Duty = 5281%(X100), DQS PI = 26
7410 00:44:53.790914 [0] MIN Duty = 4907%(X100), DQS PI = 2
7411 00:44:53.791443 [0] AVG Duty = 5094%(X100)
7412 00:44:53.794242
7413 00:44:53.797405 CH1 DQM 0 Duty spec in!! Max-Min= 187%
7414 00:44:53.797867
7415 00:44:53.800600 CH1 DQM 1 Duty spec in!! Max-Min= 374%
7416 00:44:53.804031 [DutyScan_Calibration_Flow] ====Done====
7417 00:44:53.804443
7418 00:44:53.807562 [DutyScan_Calibration_Flow] k_type=2
7419 00:44:53.824047
7420 00:44:53.824282 ==DQ 0 ==
7421 00:44:53.827448 Final DQ duty delay cell = 0
7422 00:44:53.830581 [0] MAX Duty = 5093%(X100), DQS PI = 24
7423 00:44:53.833985 [0] MIN Duty = 4938%(X100), DQS PI = 0
7424 00:44:53.834141 [0] AVG Duty = 5015%(X100)
7425 00:44:53.834263
7426 00:44:53.837227 ==DQ 1 ==
7427 00:44:53.840738 Final DQ duty delay cell = 0
7428 00:44:53.843640 [0] MAX Duty = 5094%(X100), DQS PI = 34
7429 00:44:53.847412 [0] MIN Duty = 4813%(X100), DQS PI = 0
7430 00:44:53.847519 [0] AVG Duty = 4953%(X100)
7431 00:44:53.847601
7432 00:44:53.850680 CH1 DQ 0 Duty spec in!! Max-Min= 155%
7433 00:44:53.850787
7434 00:44:53.853833 CH1 DQ 1 Duty spec in!! Max-Min= 281%
7435 00:44:53.860409 [DutyScan_Calibration_Flow] ====Done====
7436 00:44:53.863654 nWR fixed to 30
7437 00:44:53.863742 [ModeRegInit_LP4] CH0 RK0
7438 00:44:53.866973 [ModeRegInit_LP4] CH0 RK1
7439 00:44:53.870135 [ModeRegInit_LP4] CH1 RK0
7440 00:44:53.870225 [ModeRegInit_LP4] CH1 RK1
7441 00:44:53.873866 match AC timing 5
7442 00:44:53.877264 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7443 00:44:53.883796 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7444 00:44:53.887222 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7445 00:44:53.893379 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7446 00:44:53.896754 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7447 00:44:53.897179 [MiockJmeterHQA]
7448 00:44:53.897518
7449 00:44:53.900006 [DramcMiockJmeter] u1RxGatingPI = 0
7450 00:44:53.903509 0 : 4366, 4138
7451 00:44:53.903937 4 : 4253, 4027
7452 00:44:53.906803 8 : 4252, 4027
7453 00:44:53.907231 12 : 4366, 4140
7454 00:44:53.907570 16 : 4253, 4026
7455 00:44:53.910049 20 : 4252, 4027
7456 00:44:53.910549 24 : 4252, 4027
7457 00:44:53.913466 28 : 4363, 4137
7458 00:44:53.913897 32 : 4252, 4026
7459 00:44:53.916866 36 : 4363, 4137
7460 00:44:53.917293 40 : 4252, 4027
7461 00:44:53.917631 44 : 4252, 4027
7462 00:44:53.920472 48 : 4253, 4026
7463 00:44:53.921053 52 : 4255, 4029
7464 00:44:53.923618 56 : 4363, 4137
7465 00:44:53.924046 60 : 4253, 4027
7466 00:44:53.926902 64 : 4363, 4137
7467 00:44:53.927330 68 : 4250, 4027
7468 00:44:53.930480 72 : 4252, 4027
7469 00:44:53.930909 76 : 4250, 4026
7470 00:44:53.931253 80 : 4361, 4137
7471 00:44:53.933717 84 : 4250, 4027
7472 00:44:53.934149 88 : 4361, 3636
7473 00:44:53.937083 92 : 4253, 0
7474 00:44:53.937510 96 : 4361, 0
7475 00:44:53.937852 100 : 4253, 0
7476 00:44:53.940110 104 : 4360, 0
7477 00:44:53.940539 108 : 4253, 0
7478 00:44:53.943518 112 : 4255, 0
7479 00:44:53.944053 116 : 4250, 0
7480 00:44:53.944451 120 : 4252, 0
7481 00:44:53.946655 124 : 4252, 0
7482 00:44:53.947082 128 : 4250, 0
7483 00:44:53.950384 132 : 4252, 0
7484 00:44:53.950814 136 : 4361, 0
7485 00:44:53.951158 140 : 4361, 0
7486 00:44:53.953630 144 : 4250, 0
7487 00:44:53.954059 148 : 4252, 0
7488 00:44:53.954401 152 : 4361, 0
7489 00:44:53.956899 156 : 4360, 0
7490 00:44:53.957328 160 : 4249, 0
7491 00:44:53.960156 164 : 4250, 0
7492 00:44:53.960609 168 : 4250, 0
7493 00:44:53.960959 172 : 4250, 0
7494 00:44:53.963747 176 : 4250, 0
7495 00:44:53.964171 180 : 4250, 0
7496 00:44:53.967398 184 : 4250, 0
7497 00:44:53.967928 188 : 4250, 0
7498 00:44:53.968268 192 : 4361, 0
7499 00:44:53.970071 196 : 4361, 0
7500 00:44:53.970502 200 : 4252, 7
7501 00:44:53.973610 204 : 4361, 2767
7502 00:44:53.974035 208 : 4363, 4137
7503 00:44:53.976848 212 : 4250, 4027
7504 00:44:53.977273 216 : 4250, 4027
7505 00:44:53.977614 220 : 4360, 4138
7506 00:44:53.980445 224 : 4361, 4137
7507 00:44:53.980896 228 : 4250, 4026
7508 00:44:53.983268 232 : 4361, 4137
7509 00:44:53.983689 236 : 4361, 4137
7510 00:44:53.986829 240 : 4250, 4027
7511 00:44:53.987253 244 : 4250, 4027
7512 00:44:53.989922 248 : 4250, 4026
7513 00:44:53.990346 252 : 4250, 4027
7514 00:44:53.993343 256 : 4250, 4027
7515 00:44:53.993768 260 : 4250, 4027
7516 00:44:53.996974 264 : 4250, 4027
7517 00:44:53.997504 268 : 4250, 4027
7518 00:44:54.000463 272 : 4360, 4137
7519 00:44:54.001103 276 : 4361, 4137
7520 00:44:54.001450 280 : 4250, 4027
7521 00:44:54.003563 284 : 4361, 4138
7522 00:44:54.003988 288 : 4250, 4027
7523 00:44:54.006719 292 : 4250, 4027
7524 00:44:54.007144 296 : 4250, 4027
7525 00:44:54.010095 300 : 4250, 4027
7526 00:44:54.010522 304 : 4250, 4027
7527 00:44:54.013496 308 : 4250, 4026
7528 00:44:54.013921 312 : 4250, 3960
7529 00:44:54.016467 316 : 4250, 1781
7530 00:44:54.016915
7531 00:44:54.017245 MIOCK jitter meter ch=0
7532 00:44:54.017553
7533 00:44:54.019820 1T = (316-92) = 224 dly cells
7534 00:44:54.026936 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7535 00:44:54.027479 ==
7536 00:44:54.029820 Dram Type= 6, Freq= 0, CH_0, rank 0
7537 00:44:54.033190 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7538 00:44:54.033616 ==
7539 00:44:54.039473 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7540 00:44:54.043273 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7541 00:44:54.050018 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7542 00:44:54.053282 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7543 00:44:54.063039 [CA 0] Center 43 (13~73) winsize 61
7544 00:44:54.066183 [CA 1] Center 43 (13~73) winsize 61
7545 00:44:54.069715 [CA 2] Center 38 (8~68) winsize 61
7546 00:44:54.073039 [CA 3] Center 37 (8~67) winsize 60
7547 00:44:54.076324 [CA 4] Center 36 (6~66) winsize 61
7548 00:44:54.079482 [CA 5] Center 35 (5~65) winsize 61
7549 00:44:54.079954
7550 00:44:54.083118 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7551 00:44:54.083599
7552 00:44:54.086426 [CATrainingPosCal] consider 1 rank data
7553 00:44:54.089500 u2DelayCellTimex100 = 290/100 ps
7554 00:44:54.093319 CA0 delay=43 (13~73),Diff = 8 PI (26 cell)
7555 00:44:54.100064 CA1 delay=43 (13~73),Diff = 8 PI (26 cell)
7556 00:44:54.103194 CA2 delay=38 (8~68),Diff = 3 PI (10 cell)
7557 00:44:54.106333 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7558 00:44:54.109688 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7559 00:44:54.113055 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7560 00:44:54.113625
7561 00:44:54.116242 CA PerBit enable=1, Macro0, CA PI delay=35
7562 00:44:54.116900
7563 00:44:54.119591 [CBTSetCACLKResult] CA Dly = 35
7564 00:44:54.122988 CS Dly: 10 (0~41)
7565 00:44:54.125944 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7566 00:44:54.129399 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7567 00:44:54.129871 ==
7568 00:44:54.132761 Dram Type= 6, Freq= 0, CH_0, rank 1
7569 00:44:54.136376 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7570 00:44:54.139443 ==
7571 00:44:54.142682 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7572 00:44:54.145970 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7573 00:44:54.152394 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7574 00:44:54.159533 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7575 00:44:54.166497 [CA 0] Center 43 (13~74) winsize 62
7576 00:44:54.169709 [CA 1] Center 43 (13~73) winsize 61
7577 00:44:54.172880 [CA 2] Center 38 (9~68) winsize 60
7578 00:44:54.176682 [CA 3] Center 38 (9~68) winsize 60
7579 00:44:54.179955 [CA 4] Center 36 (7~66) winsize 60
7580 00:44:54.183109 [CA 5] Center 36 (6~66) winsize 61
7581 00:44:54.183669
7582 00:44:54.186937 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7583 00:44:54.187513
7584 00:44:54.189869 [CATrainingPosCal] consider 2 rank data
7585 00:44:54.192984 u2DelayCellTimex100 = 290/100 ps
7586 00:44:54.196623 CA0 delay=43 (13~73),Diff = 8 PI (26 cell)
7587 00:44:54.202807 CA1 delay=43 (13~73),Diff = 8 PI (26 cell)
7588 00:44:54.206390 CA2 delay=38 (9~68),Diff = 3 PI (10 cell)
7589 00:44:54.209831 CA3 delay=38 (9~67),Diff = 3 PI (10 cell)
7590 00:44:54.213301 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
7591 00:44:54.216164 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7592 00:44:54.216754
7593 00:44:54.220026 CA PerBit enable=1, Macro0, CA PI delay=35
7594 00:44:54.220629
7595 00:44:54.222907 [CBTSetCACLKResult] CA Dly = 35
7596 00:44:54.226312 CS Dly: 11 (0~44)
7597 00:44:54.229700 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7598 00:44:54.233064 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7599 00:44:54.233533
7600 00:44:54.236272 ----->DramcWriteLeveling(PI) begin...
7601 00:44:54.236868 ==
7602 00:44:54.239829 Dram Type= 6, Freq= 0, CH_0, rank 0
7603 00:44:54.245831 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7604 00:44:54.246503 ==
7605 00:44:54.249379 Write leveling (Byte 0): 36 => 36
7606 00:44:54.249844 Write leveling (Byte 1): 33 => 33
7607 00:44:54.252774 DramcWriteLeveling(PI) end<-----
7608 00:44:54.253236
7609 00:44:54.253641 ==
7610 00:44:54.255882 Dram Type= 6, Freq= 0, CH_0, rank 0
7611 00:44:54.262544 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7612 00:44:54.263011 ==
7613 00:44:54.265876 [Gating] SW mode calibration
7614 00:44:54.272817 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7615 00:44:54.276342 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7616 00:44:54.283101 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7617 00:44:54.286371 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7618 00:44:54.289473 1 4 8 | B1->B0 | 2323 2827 | 0 1 | (0 0) (0 0)
7619 00:44:54.296292 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7620 00:44:54.298987 1 4 16 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)
7621 00:44:54.302794 1 4 20 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
7622 00:44:54.309298 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7623 00:44:54.312820 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7624 00:44:54.316421 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7625 00:44:54.319571 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7626 00:44:54.326009 1 5 8 | B1->B0 | 3434 2a2a | 1 0 | (1 1) (0 0)
7627 00:44:54.329378 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7628 00:44:54.332784 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7629 00:44:54.339516 1 5 20 | B1->B0 | 2727 2323 | 1 0 | (1 0) (0 0)
7630 00:44:54.342777 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7631 00:44:54.345675 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7632 00:44:54.352810 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7633 00:44:54.356120 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7634 00:44:54.359468 1 6 8 | B1->B0 | 2323 4040 | 0 0 | (0 0) (0 0)
7635 00:44:54.366061 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7636 00:44:54.369122 1 6 16 | B1->B0 | 2727 4646 | 0 0 | (1 1) (0 0)
7637 00:44:54.372656 1 6 20 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
7638 00:44:54.379293 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7639 00:44:54.382388 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7640 00:44:54.385750 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7641 00:44:54.392462 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7642 00:44:54.395763 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7643 00:44:54.399428 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7644 00:44:54.406069 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7645 00:44:54.408935 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7646 00:44:54.412589 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7647 00:44:54.419018 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7648 00:44:54.422500 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7649 00:44:54.425691 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7650 00:44:54.432193 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7651 00:44:54.435909 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7652 00:44:54.438639 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7653 00:44:54.445784 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7654 00:44:54.448592 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7655 00:44:54.451901 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7656 00:44:54.458401 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7657 00:44:54.461854 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7658 00:44:54.465386 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7659 00:44:54.468341 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7660 00:44:54.471580 Total UI for P1: 0, mck2ui 16
7661 00:44:54.475027 best dqsien dly found for B0: ( 1, 9, 8)
7662 00:44:54.481935 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7663 00:44:54.485198 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7664 00:44:54.488656 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7665 00:44:54.495110 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7666 00:44:54.498914 Total UI for P1: 0, mck2ui 16
7667 00:44:54.501836 best dqsien dly found for B1: ( 1, 9, 20)
7668 00:44:54.505516 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
7669 00:44:54.508761 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7670 00:44:54.509277
7671 00:44:54.512096 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
7672 00:44:54.515237 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7673 00:44:54.518629 [Gating] SW calibration Done
7674 00:44:54.519195 ==
7675 00:44:54.522018 Dram Type= 6, Freq= 0, CH_0, rank 0
7676 00:44:54.525472 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7677 00:44:54.526042 ==
7678 00:44:54.528242 RX Vref Scan: 0
7679 00:44:54.528744
7680 00:44:54.529132 RX Vref 0 -> 0, step: 1
7681 00:44:54.529475
7682 00:44:54.532209 RX Delay 0 -> 252, step: 8
7683 00:44:54.535209 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
7684 00:44:54.541871 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7685 00:44:54.544966 iDelay=200, Bit 2, Center 135 (88 ~ 183) 96
7686 00:44:54.548453 iDelay=200, Bit 3, Center 135 (88 ~ 183) 96
7687 00:44:54.551882 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7688 00:44:54.555161 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
7689 00:44:54.562114 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7690 00:44:54.564828 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7691 00:44:54.568260 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7692 00:44:54.572012 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7693 00:44:54.575425 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
7694 00:44:54.581808 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
7695 00:44:54.585100 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7696 00:44:54.588377 iDelay=200, Bit 13, Center 127 (80 ~ 175) 96
7697 00:44:54.591777 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7698 00:44:54.595348 iDelay=200, Bit 15, Center 135 (88 ~ 183) 96
7699 00:44:54.595927 ==
7700 00:44:54.598279 Dram Type= 6, Freq= 0, CH_0, rank 0
7701 00:44:54.605401 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7702 00:44:54.605942 ==
7703 00:44:54.606382 DQS Delay:
7704 00:44:54.608215 DQS0 = 0, DQS1 = 0
7705 00:44:54.608684 DQM Delay:
7706 00:44:54.609113 DQM0 = 138, DQM1 = 126
7707 00:44:54.611761 DQ Delay:
7708 00:44:54.615010 DQ0 =139, DQ1 =139, DQ2 =135, DQ3 =135
7709 00:44:54.618672 DQ4 =139, DQ5 =127, DQ6 =147, DQ7 =147
7710 00:44:54.621885 DQ8 =119, DQ9 =115, DQ10 =123, DQ11 =123
7711 00:44:54.625269 DQ12 =131, DQ13 =127, DQ14 =139, DQ15 =135
7712 00:44:54.625816
7713 00:44:54.626257
7714 00:44:54.626663 ==
7715 00:44:54.628350 Dram Type= 6, Freq= 0, CH_0, rank 0
7716 00:44:54.631910 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7717 00:44:54.635492 ==
7718 00:44:54.635920
7719 00:44:54.636352
7720 00:44:54.636796 TX Vref Scan disable
7721 00:44:54.637929 == TX Byte 0 ==
7722 00:44:54.641735 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7723 00:44:54.645077 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7724 00:44:54.648187 == TX Byte 1 ==
7725 00:44:54.651986 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7726 00:44:54.655023 Update DQM dly =988 (3 ,6, 28) DQM OEN =(3 ,3)
7727 00:44:54.658154 ==
7728 00:44:54.658588 Dram Type= 6, Freq= 0, CH_0, rank 0
7729 00:44:54.664689 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7730 00:44:54.665124 ==
7731 00:44:54.677059
7732 00:44:54.680005 TX Vref early break, caculate TX vref
7733 00:44:54.683549 TX Vref=16, minBit 0, minWin=23, winSum=380
7734 00:44:54.686930 TX Vref=18, minBit 7, minWin=23, winSum=390
7735 00:44:54.690416 TX Vref=20, minBit 1, minWin=24, winSum=399
7736 00:44:54.693694 TX Vref=22, minBit 7, minWin=24, winSum=405
7737 00:44:54.697186 TX Vref=24, minBit 6, minWin=25, winSum=414
7738 00:44:54.703691 TX Vref=26, minBit 6, minWin=25, winSum=423
7739 00:44:54.707062 TX Vref=28, minBit 0, minWin=26, winSum=426
7740 00:44:54.710355 TX Vref=30, minBit 0, minWin=25, winSum=421
7741 00:44:54.713366 TX Vref=32, minBit 0, minWin=25, winSum=412
7742 00:44:54.717013 TX Vref=34, minBit 2, minWin=24, winSum=403
7743 00:44:54.723248 [TxChooseVref] Worse bit 0, Min win 26, Win sum 426, Final Vref 28
7744 00:44:54.723815
7745 00:44:54.727111 Final TX Range 0 Vref 28
7746 00:44:54.727691
7747 00:44:54.728170 ==
7748 00:44:54.730116 Dram Type= 6, Freq= 0, CH_0, rank 0
7749 00:44:54.733753 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7750 00:44:54.734454 ==
7751 00:44:54.734944
7752 00:44:54.735393
7753 00:44:54.736636 TX Vref Scan disable
7754 00:44:54.743150 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7755 00:44:54.743717 == TX Byte 0 ==
7756 00:44:54.746523 u2DelayCellOfst[0]=13 cells (4 PI)
7757 00:44:54.749838 u2DelayCellOfst[1]=13 cells (4 PI)
7758 00:44:54.753466 u2DelayCellOfst[2]=10 cells (3 PI)
7759 00:44:54.756844 u2DelayCellOfst[3]=10 cells (3 PI)
7760 00:44:54.759948 u2DelayCellOfst[4]=6 cells (2 PI)
7761 00:44:54.763424 u2DelayCellOfst[5]=0 cells (0 PI)
7762 00:44:54.766929 u2DelayCellOfst[6]=16 cells (5 PI)
7763 00:44:54.769830 u2DelayCellOfst[7]=13 cells (4 PI)
7764 00:44:54.773674 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7765 00:44:54.776711 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7766 00:44:54.777300 == TX Byte 1 ==
7767 00:44:54.780037 u2DelayCellOfst[8]=0 cells (0 PI)
7768 00:44:54.783194 u2DelayCellOfst[9]=0 cells (0 PI)
7769 00:44:54.786713 u2DelayCellOfst[10]=10 cells (3 PI)
7770 00:44:54.790049 u2DelayCellOfst[11]=3 cells (1 PI)
7771 00:44:54.792952 u2DelayCellOfst[12]=13 cells (4 PI)
7772 00:44:54.796572 u2DelayCellOfst[13]=13 cells (4 PI)
7773 00:44:54.800152 u2DelayCellOfst[14]=13 cells (4 PI)
7774 00:44:54.803287 u2DelayCellOfst[15]=10 cells (3 PI)
7775 00:44:54.806669 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
7776 00:44:54.813090 Update DQM dly =988 (3 ,6, 28) DQM OEN =(3 ,3)
7777 00:44:54.813656 DramC Write-DBI on
7778 00:44:54.814136 ==
7779 00:44:54.816430 Dram Type= 6, Freq= 0, CH_0, rank 0
7780 00:44:54.819577 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7781 00:44:54.823037 ==
7782 00:44:54.823511
7783 00:44:54.823978
7784 00:44:54.824421 TX Vref Scan disable
7785 00:44:54.826230 == TX Byte 0 ==
7786 00:44:54.829687 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
7787 00:44:54.832938 == TX Byte 1 ==
7788 00:44:54.836687 Update DQM dly =729 (2 ,6, 25) DQM OEN =(3 ,3)
7789 00:44:54.837263 DramC Write-DBI off
7790 00:44:54.840204
7791 00:44:54.840815 [DATLAT]
7792 00:44:54.841298 Freq=1600, CH0 RK0
7793 00:44:54.841746
7794 00:44:54.842975 DATLAT Default: 0xf
7795 00:44:54.843448 0, 0xFFFF, sum = 0
7796 00:44:54.846208 1, 0xFFFF, sum = 0
7797 00:44:54.846693 2, 0xFFFF, sum = 0
7798 00:44:54.849904 3, 0xFFFF, sum = 0
7799 00:44:54.850493 4, 0xFFFF, sum = 0
7800 00:44:54.853113 5, 0xFFFF, sum = 0
7801 00:44:54.856927 6, 0xFFFF, sum = 0
7802 00:44:54.857510 7, 0xFFFF, sum = 0
7803 00:44:54.859913 8, 0xFFFF, sum = 0
7804 00:44:54.860498 9, 0xFFFF, sum = 0
7805 00:44:54.863409 10, 0xFFFF, sum = 0
7806 00:44:54.863999 11, 0xFFFF, sum = 0
7807 00:44:54.866873 12, 0xFFFF, sum = 0
7808 00:44:54.867455 13, 0xFFFF, sum = 0
7809 00:44:54.869574 14, 0x0, sum = 1
7810 00:44:54.870059 15, 0x0, sum = 2
7811 00:44:54.873216 16, 0x0, sum = 3
7812 00:44:54.873824 17, 0x0, sum = 4
7813 00:44:54.876955 best_step = 15
7814 00:44:54.877532
7815 00:44:54.878012 ==
7816 00:44:54.879677 Dram Type= 6, Freq= 0, CH_0, rank 0
7817 00:44:54.883074 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7818 00:44:54.883553 ==
7819 00:44:54.884023 RX Vref Scan: 1
7820 00:44:54.884461
7821 00:44:54.886529 Set Vref Range= 24 -> 127
7822 00:44:54.887004
7823 00:44:54.889975 RX Vref 24 -> 127, step: 1
7824 00:44:54.890450
7825 00:44:54.892986 RX Delay 19 -> 252, step: 4
7826 00:44:54.893462
7827 00:44:54.896579 Set Vref, RX VrefLevel [Byte0]: 24
7828 00:44:54.899754 [Byte1]: 24
7829 00:44:54.900331
7830 00:44:54.903165 Set Vref, RX VrefLevel [Byte0]: 25
7831 00:44:54.906764 [Byte1]: 25
7832 00:44:54.907342
7833 00:44:54.910112 Set Vref, RX VrefLevel [Byte0]: 26
7834 00:44:54.913463 [Byte1]: 26
7835 00:44:54.916673
7836 00:44:54.917149 Set Vref, RX VrefLevel [Byte0]: 27
7837 00:44:54.920398 [Byte1]: 27
7838 00:44:54.924469
7839 00:44:54.925093 Set Vref, RX VrefLevel [Byte0]: 28
7840 00:44:54.927532 [Byte1]: 28
7841 00:44:54.931704
7842 00:44:54.932179 Set Vref, RX VrefLevel [Byte0]: 29
7843 00:44:54.935138 [Byte1]: 29
7844 00:44:54.939362
7845 00:44:54.939944 Set Vref, RX VrefLevel [Byte0]: 30
7846 00:44:54.942871 [Byte1]: 30
7847 00:44:54.947037
7848 00:44:54.947512 Set Vref, RX VrefLevel [Byte0]: 31
7849 00:44:54.950580 [Byte1]: 31
7850 00:44:54.954962
7851 00:44:54.955541 Set Vref, RX VrefLevel [Byte0]: 32
7852 00:44:54.957949 [Byte1]: 32
7853 00:44:54.962454
7854 00:44:54.963038 Set Vref, RX VrefLevel [Byte0]: 33
7855 00:44:54.965886 [Byte1]: 33
7856 00:44:54.969807
7857 00:44:54.970383 Set Vref, RX VrefLevel [Byte0]: 34
7858 00:44:54.973218 [Byte1]: 34
7859 00:44:54.977311
7860 00:44:54.977892 Set Vref, RX VrefLevel [Byte0]: 35
7861 00:44:54.980844 [Byte1]: 35
7862 00:44:54.985204
7863 00:44:54.985783 Set Vref, RX VrefLevel [Byte0]: 36
7864 00:44:54.987926 [Byte1]: 36
7865 00:44:54.992512
7866 00:44:54.993125 Set Vref, RX VrefLevel [Byte0]: 37
7867 00:44:54.996045 [Byte1]: 37
7868 00:44:54.999924
7869 00:44:55.000597 Set Vref, RX VrefLevel [Byte0]: 38
7870 00:44:55.003542 [Byte1]: 38
7871 00:44:55.007946
7872 00:44:55.008544 Set Vref, RX VrefLevel [Byte0]: 39
7873 00:44:55.011215 [Byte1]: 39
7874 00:44:55.015562
7875 00:44:55.016192 Set Vref, RX VrefLevel [Byte0]: 40
7876 00:44:55.018468 [Byte1]: 40
7877 00:44:55.022735
7878 00:44:55.023310 Set Vref, RX VrefLevel [Byte0]: 41
7879 00:44:55.026110 [Byte1]: 41
7880 00:44:55.030210
7881 00:44:55.030814 Set Vref, RX VrefLevel [Byte0]: 42
7882 00:44:55.033826 [Byte1]: 42
7883 00:44:55.037707
7884 00:44:55.038183 Set Vref, RX VrefLevel [Byte0]: 43
7885 00:44:55.041270 [Byte1]: 43
7886 00:44:55.045578
7887 00:44:55.046048 Set Vref, RX VrefLevel [Byte0]: 44
7888 00:44:55.048632 [Byte1]: 44
7889 00:44:55.053141
7890 00:44:55.053609 Set Vref, RX VrefLevel [Byte0]: 45
7891 00:44:55.056334 [Byte1]: 45
7892 00:44:55.061005
7893 00:44:55.061580 Set Vref, RX VrefLevel [Byte0]: 46
7894 00:44:55.063684 [Byte1]: 46
7895 00:44:55.068421
7896 00:44:55.069043 Set Vref, RX VrefLevel [Byte0]: 47
7897 00:44:55.071959 [Byte1]: 47
7898 00:44:55.075954
7899 00:44:55.076529 Set Vref, RX VrefLevel [Byte0]: 48
7900 00:44:55.079337 [Byte1]: 48
7901 00:44:55.083562
7902 00:44:55.084134 Set Vref, RX VrefLevel [Byte0]: 49
7903 00:44:55.087089 [Byte1]: 49
7904 00:44:55.091061
7905 00:44:55.091639 Set Vref, RX VrefLevel [Byte0]: 50
7906 00:44:55.094288 [Byte1]: 50
7907 00:44:55.098378
7908 00:44:55.098974 Set Vref, RX VrefLevel [Byte0]: 51
7909 00:44:55.101591 [Byte1]: 51
7910 00:44:55.106150
7911 00:44:55.106725 Set Vref, RX VrefLevel [Byte0]: 52
7912 00:44:55.109409 [Byte1]: 52
7913 00:44:55.113967
7914 00:44:55.114525 Set Vref, RX VrefLevel [Byte0]: 53
7915 00:44:55.116704 [Byte1]: 53
7916 00:44:55.121477
7917 00:44:55.122039 Set Vref, RX VrefLevel [Byte0]: 54
7918 00:44:55.124842 [Byte1]: 54
7919 00:44:55.129219
7920 00:44:55.129788 Set Vref, RX VrefLevel [Byte0]: 55
7921 00:44:55.131822 [Byte1]: 55
7922 00:44:55.136163
7923 00:44:55.136686 Set Vref, RX VrefLevel [Byte0]: 56
7924 00:44:55.139941 [Byte1]: 56
7925 00:44:55.143761
7926 00:44:55.144322 Set Vref, RX VrefLevel [Byte0]: 57
7927 00:44:55.147020 [Byte1]: 57
7928 00:44:55.151198
7929 00:44:55.151658 Set Vref, RX VrefLevel [Byte0]: 58
7930 00:44:55.154674 [Byte1]: 58
7931 00:44:55.158874
7932 00:44:55.159335 Set Vref, RX VrefLevel [Byte0]: 59
7933 00:44:55.162586 [Byte1]: 59
7934 00:44:55.166835
7935 00:44:55.167397 Set Vref, RX VrefLevel [Byte0]: 60
7936 00:44:55.170201 [Byte1]: 60
7937 00:44:55.174162
7938 00:44:55.174726 Set Vref, RX VrefLevel [Byte0]: 61
7939 00:44:55.177339 [Byte1]: 61
7940 00:44:55.181979
7941 00:44:55.182539 Set Vref, RX VrefLevel [Byte0]: 62
7942 00:44:55.185264 [Byte1]: 62
7943 00:44:55.189408
7944 00:44:55.189915 Set Vref, RX VrefLevel [Byte0]: 63
7945 00:44:55.192856 [Byte1]: 63
7946 00:44:55.197214
7947 00:44:55.197773 Set Vref, RX VrefLevel [Byte0]: 64
7948 00:44:55.200183 [Byte1]: 64
7949 00:44:55.204844
7950 00:44:55.205551 Set Vref, RX VrefLevel [Byte0]: 65
7951 00:44:55.207980 [Byte1]: 65
7952 00:44:55.212442
7953 00:44:55.213031 Set Vref, RX VrefLevel [Byte0]: 66
7954 00:44:55.215545 [Byte1]: 66
7955 00:44:55.219626
7956 00:44:55.220203 Set Vref, RX VrefLevel [Byte0]: 67
7957 00:44:55.222892 [Byte1]: 67
7958 00:44:55.227382
7959 00:44:55.227941 Set Vref, RX VrefLevel [Byte0]: 68
7960 00:44:55.230763 [Byte1]: 68
7961 00:44:55.234888
7962 00:44:55.235462 Set Vref, RX VrefLevel [Byte0]: 69
7963 00:44:55.238232 [Byte1]: 69
7964 00:44:55.242194
7965 00:44:55.242764 Set Vref, RX VrefLevel [Byte0]: 70
7966 00:44:55.245804 [Byte1]: 70
7967 00:44:55.249758
7968 00:44:55.250231 Set Vref, RX VrefLevel [Byte0]: 71
7969 00:44:55.253067 [Byte1]: 71
7970 00:44:55.257810
7971 00:44:55.258376 Set Vref, RX VrefLevel [Byte0]: 72
7972 00:44:55.260907 [Byte1]: 72
7973 00:44:55.265087
7974 00:44:55.265557 Set Vref, RX VrefLevel [Byte0]: 73
7975 00:44:55.268124 [Byte1]: 73
7976 00:44:55.272780
7977 00:44:55.273353 Set Vref, RX VrefLevel [Byte0]: 74
7978 00:44:55.275976 [Byte1]: 74
7979 00:44:55.280402
7980 00:44:55.281027 Set Vref, RX VrefLevel [Byte0]: 75
7981 00:44:55.283485 [Byte1]: 75
7982 00:44:55.287790
7983 00:44:55.288369 Set Vref, RX VrefLevel [Byte0]: 76
7984 00:44:55.291139 [Byte1]: 76
7985 00:44:55.295149
7986 00:44:55.295617 Set Vref, RX VrefLevel [Byte0]: 77
7987 00:44:55.298594 [Byte1]: 77
7988 00:44:55.303355
7989 00:44:55.303938 Final RX Vref Byte 0 = 61 to rank0
7990 00:44:55.306031 Final RX Vref Byte 1 = 61 to rank0
7991 00:44:55.309825 Final RX Vref Byte 0 = 61 to rank1
7992 00:44:55.312839 Final RX Vref Byte 1 = 61 to rank1==
7993 00:44:55.316601 Dram Type= 6, Freq= 0, CH_0, rank 0
7994 00:44:55.323150 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7995 00:44:55.323719 ==
7996 00:44:55.324090 DQS Delay:
7997 00:44:55.324434 DQS0 = 0, DQS1 = 0
7998 00:44:55.326335 DQM Delay:
7999 00:44:55.326898 DQM0 = 135, DQM1 = 123
8000 00:44:55.329834 DQ Delay:
8001 00:44:55.333278 DQ0 =136, DQ1 =136, DQ2 =132, DQ3 =134
8002 00:44:55.336345 DQ4 =138, DQ5 =124, DQ6 =144, DQ7 =142
8003 00:44:55.339383 DQ8 =114, DQ9 =110, DQ10 =126, DQ11 =118
8004 00:44:55.342708 DQ12 =126, DQ13 =128, DQ14 =136, DQ15 =132
8005 00:44:55.343178
8006 00:44:55.343547
8007 00:44:55.343889
8008 00:44:55.346079 [DramC_TX_OE_Calibration] TA2
8009 00:44:55.349418 Original DQ_B0 (3 6) =30, OEN = 27
8010 00:44:55.353066 Original DQ_B1 (3 6) =30, OEN = 27
8011 00:44:55.356412 24, 0x0, End_B0=24 End_B1=24
8012 00:44:55.357052 25, 0x0, End_B0=25 End_B1=25
8013 00:44:55.359659 26, 0x0, End_B0=26 End_B1=26
8014 00:44:55.362927 27, 0x0, End_B0=27 End_B1=27
8015 00:44:55.366665 28, 0x0, End_B0=28 End_B1=28
8016 00:44:55.367254 29, 0x0, End_B0=29 End_B1=29
8017 00:44:55.369464 30, 0x0, End_B0=30 End_B1=30
8018 00:44:55.372536 31, 0x4141, End_B0=30 End_B1=30
8019 00:44:55.376278 Byte0 end_step=30 best_step=27
8020 00:44:55.379412 Byte1 end_step=30 best_step=27
8021 00:44:55.382483 Byte0 TX OE(2T, 0.5T) = (3, 3)
8022 00:44:55.382952 Byte1 TX OE(2T, 0.5T) = (3, 3)
8023 00:44:55.386048
8024 00:44:55.386556
8025 00:44:55.392753 [DQSOSCAuto] RK0, (LSB)MR18= 0x1d1b, (MSB)MR19= 0x303, tDQSOscB0 = 396 ps tDQSOscB1 = 395 ps
8026 00:44:55.395904 CH0 RK0: MR19=303, MR18=1D1B
8027 00:44:55.402549 CH0_RK0: MR19=0x303, MR18=0x1D1B, DQSOSC=395, MR23=63, INC=23, DEC=15
8028 00:44:55.403125
8029 00:44:55.405750 ----->DramcWriteLeveling(PI) begin...
8030 00:44:55.406226 ==
8031 00:44:55.409239 Dram Type= 6, Freq= 0, CH_0, rank 1
8032 00:44:55.412977 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8033 00:44:55.413558 ==
8034 00:44:55.416233 Write leveling (Byte 0): 37 => 37
8035 00:44:55.419709 Write leveling (Byte 1): 29 => 29
8036 00:44:55.422970 DramcWriteLeveling(PI) end<-----
8037 00:44:55.423550
8038 00:44:55.423925 ==
8039 00:44:55.426278 Dram Type= 6, Freq= 0, CH_0, rank 1
8040 00:44:55.429241 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8041 00:44:55.429882 ==
8042 00:44:55.432652 [Gating] SW mode calibration
8043 00:44:55.439530 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8044 00:44:55.445848 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8045 00:44:55.449303 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8046 00:44:55.452615 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8047 00:44:55.459535 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8048 00:44:55.462779 1 4 12 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
8049 00:44:55.466151 1 4 16 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
8050 00:44:55.472517 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8051 00:44:55.475785 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8052 00:44:55.478942 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8053 00:44:55.485610 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8054 00:44:55.488926 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8055 00:44:55.492126 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
8056 00:44:55.498803 1 5 12 | B1->B0 | 3434 2727 | 0 0 | (0 1) (0 1)
8057 00:44:55.502147 1 5 16 | B1->B0 | 2828 2323 | 0 0 | (1 0) (0 0)
8058 00:44:55.505466 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8059 00:44:55.512366 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8060 00:44:55.515048 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8061 00:44:55.518876 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8062 00:44:55.525791 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8063 00:44:55.528624 1 6 8 | B1->B0 | 2323 3332 | 0 1 | (0 0) (0 0)
8064 00:44:55.532037 1 6 12 | B1->B0 | 3232 4646 | 1 0 | (0 0) (0 0)
8065 00:44:55.539220 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8066 00:44:55.542119 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8067 00:44:55.545487 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8068 00:44:55.551785 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8069 00:44:55.555087 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8070 00:44:55.558289 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8071 00:44:55.565428 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8072 00:44:55.568713 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8073 00:44:55.572067 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8074 00:44:55.578217 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8075 00:44:55.581778 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8076 00:44:55.584878 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8077 00:44:55.588454 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8078 00:44:55.595158 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8079 00:44:55.598558 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8080 00:44:55.601922 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8081 00:44:55.608636 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8082 00:44:55.611872 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8083 00:44:55.615145 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8084 00:44:55.621737 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8085 00:44:55.625179 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8086 00:44:55.628598 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8087 00:44:55.635076 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8088 00:44:55.638530 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8089 00:44:55.641631 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8090 00:44:55.645147 Total UI for P1: 0, mck2ui 16
8091 00:44:55.648713 best dqsien dly found for B0: ( 1, 9, 12)
8092 00:44:55.654969 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8093 00:44:55.655539 Total UI for P1: 0, mck2ui 16
8094 00:44:55.661694 best dqsien dly found for B1: ( 1, 9, 16)
8095 00:44:55.665123 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8096 00:44:55.668420 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8097 00:44:55.669034
8098 00:44:55.671851 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8099 00:44:55.675299 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8100 00:44:55.678207 [Gating] SW calibration Done
8101 00:44:55.678771 ==
8102 00:44:55.681390 Dram Type= 6, Freq= 0, CH_0, rank 1
8103 00:44:55.684910 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8104 00:44:55.685482 ==
8105 00:44:55.688226 RX Vref Scan: 0
8106 00:44:55.688827
8107 00:44:55.689203 RX Vref 0 -> 0, step: 1
8108 00:44:55.689546
8109 00:44:55.691527 RX Delay 0 -> 252, step: 8
8110 00:44:55.694896 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8111 00:44:55.701678 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8112 00:44:55.704977 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8113 00:44:55.708266 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
8114 00:44:55.711468 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8115 00:44:55.714823 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8116 00:44:55.721431 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8117 00:44:55.724776 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8118 00:44:55.728199 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8119 00:44:55.731239 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8120 00:44:55.734954 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
8121 00:44:55.741203 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8122 00:44:55.744983 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8123 00:44:55.748012 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
8124 00:44:55.751113 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8125 00:44:55.754366 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8126 00:44:55.757976 ==
8127 00:44:55.761174 Dram Type= 6, Freq= 0, CH_0, rank 1
8128 00:44:55.764520 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8129 00:44:55.765130 ==
8130 00:44:55.765498 DQS Delay:
8131 00:44:55.768001 DQS0 = 0, DQS1 = 0
8132 00:44:55.768590 DQM Delay:
8133 00:44:55.771506 DQM0 = 136, DQM1 = 125
8134 00:44:55.772075 DQ Delay:
8135 00:44:55.774875 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =131
8136 00:44:55.777874 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143
8137 00:44:55.781157 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =123
8138 00:44:55.784532 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =135
8139 00:44:55.785136
8140 00:44:55.785507
8141 00:44:55.785842 ==
8142 00:44:55.787692 Dram Type= 6, Freq= 0, CH_0, rank 1
8143 00:44:55.794160 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8144 00:44:55.794626 ==
8145 00:44:55.794992
8146 00:44:55.795330
8147 00:44:55.795660 TX Vref Scan disable
8148 00:44:55.797901 == TX Byte 0 ==
8149 00:44:55.801250 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8150 00:44:55.807809 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8151 00:44:55.808382 == TX Byte 1 ==
8152 00:44:55.811333 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8153 00:44:55.817592 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8154 00:44:55.818058 ==
8155 00:44:55.821355 Dram Type= 6, Freq= 0, CH_0, rank 1
8156 00:44:55.824471 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8157 00:44:55.824968 ==
8158 00:44:55.839437
8159 00:44:55.842828 TX Vref early break, caculate TX vref
8160 00:44:55.846040 TX Vref=16, minBit 8, minWin=23, winSum=390
8161 00:44:55.849124 TX Vref=18, minBit 8, minWin=23, winSum=393
8162 00:44:55.852210 TX Vref=20, minBit 1, minWin=24, winSum=407
8163 00:44:55.855903 TX Vref=22, minBit 8, minWin=24, winSum=411
8164 00:44:55.859309 TX Vref=24, minBit 4, minWin=25, winSum=421
8165 00:44:55.865810 TX Vref=26, minBit 2, minWin=25, winSum=429
8166 00:44:55.869176 TX Vref=28, minBit 1, minWin=25, winSum=428
8167 00:44:55.872373 TX Vref=30, minBit 0, minWin=26, winSum=425
8168 00:44:55.875889 TX Vref=32, minBit 0, minWin=25, winSum=418
8169 00:44:55.879044 TX Vref=34, minBit 0, minWin=25, winSum=410
8170 00:44:55.882550 TX Vref=36, minBit 0, minWin=24, winSum=403
8171 00:44:55.888836 [TxChooseVref] Worse bit 0, Min win 26, Win sum 425, Final Vref 30
8172 00:44:55.889316
8173 00:44:55.892343 Final TX Range 0 Vref 30
8174 00:44:55.892867
8175 00:44:55.893248 ==
8176 00:44:55.895766 Dram Type= 6, Freq= 0, CH_0, rank 1
8177 00:44:55.898966 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8178 00:44:55.899440 ==
8179 00:44:55.899815
8180 00:44:55.900160
8181 00:44:55.902201 TX Vref Scan disable
8182 00:44:55.908988 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8183 00:44:55.909461 == TX Byte 0 ==
8184 00:44:55.912361 u2DelayCellOfst[0]=10 cells (3 PI)
8185 00:44:55.915305 u2DelayCellOfst[1]=16 cells (5 PI)
8186 00:44:55.918535 u2DelayCellOfst[2]=13 cells (4 PI)
8187 00:44:55.921676 u2DelayCellOfst[3]=10 cells (3 PI)
8188 00:44:55.925189 u2DelayCellOfst[4]=6 cells (2 PI)
8189 00:44:55.928292 u2DelayCellOfst[5]=0 cells (0 PI)
8190 00:44:55.931773 u2DelayCellOfst[6]=16 cells (5 PI)
8191 00:44:55.935270 u2DelayCellOfst[7]=16 cells (5 PI)
8192 00:44:55.938489 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8193 00:44:55.941827 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8194 00:44:55.944889 == TX Byte 1 ==
8195 00:44:55.948424 u2DelayCellOfst[8]=0 cells (0 PI)
8196 00:44:55.948545 u2DelayCellOfst[9]=0 cells (0 PI)
8197 00:44:55.951706 u2DelayCellOfst[10]=3 cells (1 PI)
8198 00:44:55.954874 u2DelayCellOfst[11]=0 cells (0 PI)
8199 00:44:55.958438 u2DelayCellOfst[12]=10 cells (3 PI)
8200 00:44:55.961674 u2DelayCellOfst[13]=10 cells (3 PI)
8201 00:44:55.965063 u2DelayCellOfst[14]=10 cells (3 PI)
8202 00:44:55.968104 u2DelayCellOfst[15]=6 cells (2 PI)
8203 00:44:55.972011 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8204 00:44:55.978270 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8205 00:44:55.978356 DramC Write-DBI on
8206 00:44:55.978422 ==
8207 00:44:55.981597 Dram Type= 6, Freq= 0, CH_0, rank 1
8208 00:44:55.988152 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8209 00:44:55.988241 ==
8210 00:44:55.988306
8211 00:44:55.988367
8212 00:44:55.988431 TX Vref Scan disable
8213 00:44:55.992026 == TX Byte 0 ==
8214 00:44:55.995289 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
8215 00:44:55.998447 == TX Byte 1 ==
8216 00:44:56.001734 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8217 00:44:56.005015 DramC Write-DBI off
8218 00:44:56.005099
8219 00:44:56.005165 [DATLAT]
8220 00:44:56.005224 Freq=1600, CH0 RK1
8221 00:44:56.005290
8222 00:44:56.008382 DATLAT Default: 0xf
8223 00:44:56.008464 0, 0xFFFF, sum = 0
8224 00:44:56.011600 1, 0xFFFF, sum = 0
8225 00:44:56.015178 2, 0xFFFF, sum = 0
8226 00:44:56.015263 3, 0xFFFF, sum = 0
8227 00:44:56.018512 4, 0xFFFF, sum = 0
8228 00:44:56.018596 5, 0xFFFF, sum = 0
8229 00:44:56.021837 6, 0xFFFF, sum = 0
8230 00:44:56.021922 7, 0xFFFF, sum = 0
8231 00:44:56.025119 8, 0xFFFF, sum = 0
8232 00:44:56.025204 9, 0xFFFF, sum = 0
8233 00:44:56.028376 10, 0xFFFF, sum = 0
8234 00:44:56.028460 11, 0xFFFF, sum = 0
8235 00:44:56.031773 12, 0xFFFF, sum = 0
8236 00:44:56.031858 13, 0xFFFF, sum = 0
8237 00:44:56.035184 14, 0x0, sum = 1
8238 00:44:56.035350 15, 0x0, sum = 2
8239 00:44:56.038478 16, 0x0, sum = 3
8240 00:44:56.038613 17, 0x0, sum = 4
8241 00:44:56.041663 best_step = 15
8242 00:44:56.041825
8243 00:44:56.041901 ==
8244 00:44:56.045084 Dram Type= 6, Freq= 0, CH_0, rank 1
8245 00:44:56.048272 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8246 00:44:56.048399 ==
8247 00:44:56.052052 RX Vref Scan: 0
8248 00:44:56.052214
8249 00:44:56.052287 RX Vref 0 -> 0, step: 1
8250 00:44:56.052353
8251 00:44:56.055186 RX Delay 11 -> 252, step: 4
8252 00:44:56.058381 iDelay=191, Bit 0, Center 132 (83 ~ 182) 100
8253 00:44:56.065199 iDelay=191, Bit 1, Center 136 (87 ~ 186) 100
8254 00:44:56.068979 iDelay=191, Bit 2, Center 128 (79 ~ 178) 100
8255 00:44:56.071628 iDelay=191, Bit 3, Center 130 (83 ~ 178) 96
8256 00:44:56.075449 iDelay=191, Bit 4, Center 134 (83 ~ 186) 104
8257 00:44:56.078580 iDelay=191, Bit 5, Center 124 (75 ~ 174) 100
8258 00:44:56.085041 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8259 00:44:56.088099 iDelay=191, Bit 7, Center 138 (87 ~ 190) 104
8260 00:44:56.091512 iDelay=191, Bit 8, Center 116 (67 ~ 166) 100
8261 00:44:56.095045 iDelay=191, Bit 9, Center 112 (59 ~ 166) 108
8262 00:44:56.098468 iDelay=191, Bit 10, Center 124 (75 ~ 174) 100
8263 00:44:56.104912 iDelay=191, Bit 11, Center 120 (71 ~ 170) 100
8264 00:44:56.108212 iDelay=191, Bit 12, Center 128 (75 ~ 182) 108
8265 00:44:56.112048 iDelay=191, Bit 13, Center 128 (79 ~ 178) 100
8266 00:44:56.114967 iDelay=191, Bit 14, Center 132 (79 ~ 186) 108
8267 00:44:56.118080 iDelay=191, Bit 15, Center 130 (79 ~ 182) 104
8268 00:44:56.121780 ==
8269 00:44:56.124947 Dram Type= 6, Freq= 0, CH_0, rank 1
8270 00:44:56.128535 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8271 00:44:56.129024 ==
8272 00:44:56.129313 DQS Delay:
8273 00:44:56.131935 DQS0 = 0, DQS1 = 0
8274 00:44:56.132497 DQM Delay:
8275 00:44:56.135224 DQM0 = 132, DQM1 = 123
8276 00:44:56.135689 DQ Delay:
8277 00:44:56.138188 DQ0 =132, DQ1 =136, DQ2 =128, DQ3 =130
8278 00:44:56.141554 DQ4 =134, DQ5 =124, DQ6 =140, DQ7 =138
8279 00:44:56.144753 DQ8 =116, DQ9 =112, DQ10 =124, DQ11 =120
8280 00:44:56.148464 DQ12 =128, DQ13 =128, DQ14 =132, DQ15 =130
8281 00:44:56.149055
8282 00:44:56.149427
8283 00:44:56.149766
8284 00:44:56.151837 [DramC_TX_OE_Calibration] TA2
8285 00:44:56.154840 Original DQ_B0 (3 6) =30, OEN = 27
8286 00:44:56.158423 Original DQ_B1 (3 6) =30, OEN = 27
8287 00:44:56.161833 24, 0x0, End_B0=24 End_B1=24
8288 00:44:56.165124 25, 0x0, End_B0=25 End_B1=25
8289 00:44:56.165695 26, 0x0, End_B0=26 End_B1=26
8290 00:44:56.168626 27, 0x0, End_B0=27 End_B1=27
8291 00:44:56.171955 28, 0x0, End_B0=28 End_B1=28
8292 00:44:56.175236 29, 0x0, End_B0=29 End_B1=29
8293 00:44:56.178304 30, 0x0, End_B0=30 End_B1=30
8294 00:44:56.178875 31, 0x4141, End_B0=30 End_B1=30
8295 00:44:56.181545 Byte0 end_step=30 best_step=27
8296 00:44:56.184971 Byte1 end_step=30 best_step=27
8297 00:44:56.188383 Byte0 TX OE(2T, 0.5T) = (3, 3)
8298 00:44:56.191677 Byte1 TX OE(2T, 0.5T) = (3, 3)
8299 00:44:56.192237
8300 00:44:56.192654
8301 00:44:56.198086 [DQSOSCAuto] RK1, (LSB)MR18= 0x200c, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 393 ps
8302 00:44:56.201305 CH0 RK1: MR19=303, MR18=200C
8303 00:44:56.207821 CH0_RK1: MR19=0x303, MR18=0x200C, DQSOSC=393, MR23=63, INC=23, DEC=15
8304 00:44:56.211271 [RxdqsGatingPostProcess] freq 1600
8305 00:44:56.217897 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8306 00:44:56.218045 best DQS0 dly(2T, 0.5T) = (1, 1)
8307 00:44:56.220839 best DQS1 dly(2T, 0.5T) = (1, 1)
8308 00:44:56.224248 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8309 00:44:56.227853 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8310 00:44:56.231194 best DQS0 dly(2T, 0.5T) = (1, 1)
8311 00:44:56.234724 best DQS1 dly(2T, 0.5T) = (1, 1)
8312 00:44:56.238068 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8313 00:44:56.241280 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8314 00:44:56.244505 Pre-setting of DQS Precalculation
8315 00:44:56.247873 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8316 00:44:56.248035 ==
8317 00:44:56.251452 Dram Type= 6, Freq= 0, CH_1, rank 0
8318 00:44:56.258398 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8319 00:44:56.258576 ==
8320 00:44:56.261709 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8321 00:44:56.264952 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8322 00:44:56.271435 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8323 00:44:56.278082 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8324 00:44:56.285314 [CA 0] Center 41 (11~71) winsize 61
8325 00:44:56.288452 [CA 1] Center 42 (12~72) winsize 61
8326 00:44:56.291757 [CA 2] Center 38 (9~67) winsize 59
8327 00:44:56.295510 [CA 3] Center 36 (7~66) winsize 60
8328 00:44:56.298578 [CA 4] Center 37 (7~68) winsize 62
8329 00:44:56.302348 [CA 5] Center 36 (7~66) winsize 60
8330 00:44:56.302745
8331 00:44:56.305336 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8332 00:44:56.305736
8333 00:44:56.309141 [CATrainingPosCal] consider 1 rank data
8334 00:44:56.312066 u2DelayCellTimex100 = 290/100 ps
8335 00:44:56.315099 CA0 delay=41 (11~71),Diff = 5 PI (16 cell)
8336 00:44:56.321858 CA1 delay=42 (12~72),Diff = 6 PI (20 cell)
8337 00:44:56.325461 CA2 delay=38 (9~67),Diff = 2 PI (6 cell)
8338 00:44:56.328256 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8339 00:44:56.332122 CA4 delay=37 (7~68),Diff = 1 PI (3 cell)
8340 00:44:56.335135 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8341 00:44:56.335602
8342 00:44:56.338504 CA PerBit enable=1, Macro0, CA PI delay=36
8343 00:44:56.339075
8344 00:44:56.341968 [CBTSetCACLKResult] CA Dly = 36
8345 00:44:56.345124 CS Dly: 9 (0~40)
8346 00:44:56.348402 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8347 00:44:56.351907 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8348 00:44:56.352475 ==
8349 00:44:56.354998 Dram Type= 6, Freq= 0, CH_1, rank 1
8350 00:44:56.358494 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8351 00:44:56.359063 ==
8352 00:44:56.365400 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8353 00:44:56.368432 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8354 00:44:56.374981 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8355 00:44:56.378633 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8356 00:44:56.388791 [CA 0] Center 42 (13~72) winsize 60
8357 00:44:56.392065 [CA 1] Center 42 (12~72) winsize 61
8358 00:44:56.395386 [CA 2] Center 38 (9~68) winsize 60
8359 00:44:56.398827 [CA 3] Center 37 (8~67) winsize 60
8360 00:44:56.401742 [CA 4] Center 38 (9~68) winsize 60
8361 00:44:56.404903 [CA 5] Center 37 (8~67) winsize 60
8362 00:44:56.405358
8363 00:44:56.408489 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8364 00:44:56.408972
8365 00:44:56.411632 [CATrainingPosCal] consider 2 rank data
8366 00:44:56.414989 u2DelayCellTimex100 = 290/100 ps
8367 00:44:56.418261 CA0 delay=42 (13~71),Diff = 5 PI (16 cell)
8368 00:44:56.425224 CA1 delay=42 (12~72),Diff = 5 PI (16 cell)
8369 00:44:56.428457 CA2 delay=38 (9~67),Diff = 1 PI (3 cell)
8370 00:44:56.431576 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8371 00:44:56.435192 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8372 00:44:56.438742 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8373 00:44:56.439299
8374 00:44:56.441883 CA PerBit enable=1, Macro0, CA PI delay=37
8375 00:44:56.442340
8376 00:44:56.445350 [CBTSetCACLKResult] CA Dly = 37
8377 00:44:56.448053 CS Dly: 10 (0~42)
8378 00:44:56.451734 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8379 00:44:56.454969 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8380 00:44:56.455430
8381 00:44:56.458089 ----->DramcWriteLeveling(PI) begin...
8382 00:44:56.458550 ==
8383 00:44:56.461486 Dram Type= 6, Freq= 0, CH_1, rank 0
8384 00:44:56.464527 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8385 00:44:56.468127 ==
8386 00:44:56.468618 Write leveling (Byte 0): 23 => 23
8387 00:44:56.471326 Write leveling (Byte 1): 28 => 28
8388 00:44:56.474622 DramcWriteLeveling(PI) end<-----
8389 00:44:56.475075
8390 00:44:56.475433 ==
8391 00:44:56.478561 Dram Type= 6, Freq= 0, CH_1, rank 0
8392 00:44:56.485356 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8393 00:44:56.485920 ==
8394 00:44:56.486283 [Gating] SW mode calibration
8395 00:44:56.494981 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8396 00:44:56.498446 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8397 00:44:56.505360 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8398 00:44:56.507961 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8399 00:44:56.511844 1 4 8 | B1->B0 | 2e2e 3131 | 1 1 | (1 1) (1 1)
8400 00:44:56.514959 1 4 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8401 00:44:56.521407 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8402 00:44:56.524785 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8403 00:44:56.528118 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8404 00:44:56.534480 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8405 00:44:56.538385 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8406 00:44:56.541620 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8407 00:44:56.548051 1 5 8 | B1->B0 | 2828 2525 | 0 0 | (0 1) (0 1)
8408 00:44:56.551137 1 5 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8409 00:44:56.555186 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8410 00:44:56.561305 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8411 00:44:56.564663 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8412 00:44:56.568108 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8413 00:44:56.574584 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8414 00:44:56.578382 1 6 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
8415 00:44:56.581495 1 6 8 | B1->B0 | 3d3d 4444 | 0 0 | (0 0) (0 0)
8416 00:44:56.588328 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8417 00:44:56.591648 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8418 00:44:56.595013 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8419 00:44:56.601293 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8420 00:44:56.604497 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8421 00:44:56.608464 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8422 00:44:56.614748 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8423 00:44:56.618461 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8424 00:44:56.621622 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8425 00:44:56.624921 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8426 00:44:56.631621 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8427 00:44:56.635066 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8428 00:44:56.637996 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8429 00:44:56.644714 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8430 00:44:56.648305 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8431 00:44:56.651507 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8432 00:44:56.657917 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8433 00:44:56.661230 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8434 00:44:56.664538 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8435 00:44:56.671315 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8436 00:44:56.674866 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8437 00:44:56.678142 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8438 00:44:56.684351 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8439 00:44:56.688146 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8440 00:44:56.691163 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8441 00:44:56.695000 Total UI for P1: 0, mck2ui 16
8442 00:44:56.697498 best dqsien dly found for B0: ( 1, 9, 8)
8443 00:44:56.700845 Total UI for P1: 0, mck2ui 16
8444 00:44:56.704614 best dqsien dly found for B1: ( 1, 9, 8)
8445 00:44:56.707607 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8446 00:44:56.711468 best DQS1 dly(MCK, UI, PI) = (1, 9, 8)
8447 00:44:56.712031
8448 00:44:56.714439 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8449 00:44:56.720912 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 8)
8450 00:44:56.721479 [Gating] SW calibration Done
8451 00:44:56.721854 ==
8452 00:44:56.724655 Dram Type= 6, Freq= 0, CH_1, rank 0
8453 00:44:56.731389 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8454 00:44:56.731962 ==
8455 00:44:56.732334 RX Vref Scan: 0
8456 00:44:56.732720
8457 00:44:56.734375 RX Vref 0 -> 0, step: 1
8458 00:44:56.734845
8459 00:44:56.737974 RX Delay 0 -> 252, step: 8
8460 00:44:56.741078 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8461 00:44:56.744447 iDelay=200, Bit 1, Center 135 (88 ~ 183) 96
8462 00:44:56.747482 iDelay=200, Bit 2, Center 127 (80 ~ 175) 96
8463 00:44:56.751002 iDelay=200, Bit 3, Center 139 (88 ~ 191) 104
8464 00:44:56.757624 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8465 00:44:56.760658 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8466 00:44:56.764298 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8467 00:44:56.767700 iDelay=200, Bit 7, Center 135 (88 ~ 183) 96
8468 00:44:56.770974 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8469 00:44:56.777697 iDelay=200, Bit 9, Center 119 (72 ~ 167) 96
8470 00:44:56.780902 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8471 00:44:56.784242 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8472 00:44:56.787898 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8473 00:44:56.790912 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8474 00:44:56.797771 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8475 00:44:56.801049 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8476 00:44:56.801513 ==
8477 00:44:56.804792 Dram Type= 6, Freq= 0, CH_1, rank 0
8478 00:44:56.807723 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8479 00:44:56.808289 ==
8480 00:44:56.810931 DQS Delay:
8481 00:44:56.811499 DQS0 = 0, DQS1 = 0
8482 00:44:56.811870 DQM Delay:
8483 00:44:56.814430 DQM0 = 138, DQM1 = 129
8484 00:44:56.814989 DQ Delay:
8485 00:44:56.817888 DQ0 =143, DQ1 =135, DQ2 =127, DQ3 =139
8486 00:44:56.820657 DQ4 =135, DQ5 =147, DQ6 =147, DQ7 =135
8487 00:44:56.824594 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
8488 00:44:56.830911 DQ12 =139, DQ13 =135, DQ14 =135, DQ15 =135
8489 00:44:56.831477
8490 00:44:56.831844
8491 00:44:56.832182 ==
8492 00:44:56.834327 Dram Type= 6, Freq= 0, CH_1, rank 0
8493 00:44:56.837513 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8494 00:44:56.838189 ==
8495 00:44:56.838576
8496 00:44:56.838918
8497 00:44:56.840472 TX Vref Scan disable
8498 00:44:56.840965 == TX Byte 0 ==
8499 00:44:56.847480 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8500 00:44:56.851015 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8501 00:44:56.851599 == TX Byte 1 ==
8502 00:44:56.857142 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8503 00:44:56.860509 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8504 00:44:56.861018 ==
8505 00:44:56.864371 Dram Type= 6, Freq= 0, CH_1, rank 0
8506 00:44:56.867159 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8507 00:44:56.867732 ==
8508 00:44:56.881303
8509 00:44:56.884809 TX Vref early break, caculate TX vref
8510 00:44:56.887722 TX Vref=16, minBit 10, minWin=21, winSum=365
8511 00:44:56.890762 TX Vref=18, minBit 10, minWin=22, winSum=377
8512 00:44:56.894454 TX Vref=20, minBit 10, minWin=22, winSum=385
8513 00:44:56.897563 TX Vref=22, minBit 15, minWin=23, winSum=396
8514 00:44:56.904450 TX Vref=24, minBit 10, minWin=23, winSum=402
8515 00:44:56.907661 TX Vref=26, minBit 10, minWin=24, winSum=413
8516 00:44:56.911296 TX Vref=28, minBit 10, minWin=25, winSum=418
8517 00:44:56.914201 TX Vref=30, minBit 13, minWin=24, winSum=412
8518 00:44:56.917747 TX Vref=32, minBit 9, minWin=24, winSum=402
8519 00:44:56.921267 TX Vref=34, minBit 11, minWin=23, winSum=395
8520 00:44:56.927612 [TxChooseVref] Worse bit 10, Min win 25, Win sum 418, Final Vref 28
8521 00:44:56.928178
8522 00:44:56.930823 Final TX Range 0 Vref 28
8523 00:44:56.931394
8524 00:44:56.931760 ==
8525 00:44:56.934023 Dram Type= 6, Freq= 0, CH_1, rank 0
8526 00:44:56.937534 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8527 00:44:56.938001 ==
8528 00:44:56.941210
8529 00:44:56.941781
8530 00:44:56.942148 TX Vref Scan disable
8531 00:44:56.947483 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8532 00:44:56.947948 == TX Byte 0 ==
8533 00:44:56.950413 u2DelayCellOfst[0]=16 cells (5 PI)
8534 00:44:56.953939 u2DelayCellOfst[1]=10 cells (3 PI)
8535 00:44:56.957267 u2DelayCellOfst[2]=0 cells (0 PI)
8536 00:44:56.960850 u2DelayCellOfst[3]=6 cells (2 PI)
8537 00:44:56.964410 u2DelayCellOfst[4]=6 cells (2 PI)
8538 00:44:56.967670 u2DelayCellOfst[5]=16 cells (5 PI)
8539 00:44:56.970937 u2DelayCellOfst[6]=16 cells (5 PI)
8540 00:44:56.974162 u2DelayCellOfst[7]=3 cells (1 PI)
8541 00:44:56.977173 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8542 00:44:56.980710 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8543 00:44:56.983998 == TX Byte 1 ==
8544 00:44:56.987211 u2DelayCellOfst[8]=0 cells (0 PI)
8545 00:44:56.990849 u2DelayCellOfst[9]=3 cells (1 PI)
8546 00:44:56.991333 u2DelayCellOfst[10]=10 cells (3 PI)
8547 00:44:56.993916 u2DelayCellOfst[11]=3 cells (1 PI)
8548 00:44:56.997176 u2DelayCellOfst[12]=16 cells (5 PI)
8549 00:44:57.000757 u2DelayCellOfst[13]=20 cells (6 PI)
8550 00:44:57.003844 u2DelayCellOfst[14]=20 cells (6 PI)
8551 00:44:57.007241 u2DelayCellOfst[15]=16 cells (5 PI)
8552 00:44:57.014306 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8553 00:44:57.017297 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8554 00:44:57.017868 DramC Write-DBI on
8555 00:44:57.018240 ==
8556 00:44:57.020833 Dram Type= 6, Freq= 0, CH_1, rank 0
8557 00:44:57.027182 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8558 00:44:57.027753 ==
8559 00:44:57.028121
8560 00:44:57.028462
8561 00:44:57.028916 TX Vref Scan disable
8562 00:44:57.031305 == TX Byte 0 ==
8563 00:44:57.034339 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
8564 00:44:57.038255 == TX Byte 1 ==
8565 00:44:57.041452 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8566 00:44:57.044753 DramC Write-DBI off
8567 00:44:57.045307
8568 00:44:57.045678 [DATLAT]
8569 00:44:57.046095 Freq=1600, CH1 RK0
8570 00:44:57.046434
8571 00:44:57.048026 DATLAT Default: 0xf
8572 00:44:57.048651 0, 0xFFFF, sum = 0
8573 00:44:57.051169 1, 0xFFFF, sum = 0
8574 00:44:57.054186 2, 0xFFFF, sum = 0
8575 00:44:57.054658 3, 0xFFFF, sum = 0
8576 00:44:57.058106 4, 0xFFFF, sum = 0
8577 00:44:57.058694 5, 0xFFFF, sum = 0
8578 00:44:57.060978 6, 0xFFFF, sum = 0
8579 00:44:57.061446 7, 0xFFFF, sum = 0
8580 00:44:57.064355 8, 0xFFFF, sum = 0
8581 00:44:57.064855 9, 0xFFFF, sum = 0
8582 00:44:57.067783 10, 0xFFFF, sum = 0
8583 00:44:57.068356 11, 0xFFFF, sum = 0
8584 00:44:57.071640 12, 0xFFFF, sum = 0
8585 00:44:57.072213 13, 0xFFFF, sum = 0
8586 00:44:57.074710 14, 0x0, sum = 1
8587 00:44:57.075289 15, 0x0, sum = 2
8588 00:44:57.077740 16, 0x0, sum = 3
8589 00:44:57.078314 17, 0x0, sum = 4
8590 00:44:57.081217 best_step = 15
8591 00:44:57.081780
8592 00:44:57.082148 ==
8593 00:44:57.084460 Dram Type= 6, Freq= 0, CH_1, rank 0
8594 00:44:57.087777 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8595 00:44:57.088346 ==
8596 00:44:57.088783 RX Vref Scan: 1
8597 00:44:57.090896
8598 00:44:57.091354 Set Vref Range= 24 -> 127
8599 00:44:57.091719
8600 00:44:57.094392 RX Vref 24 -> 127, step: 1
8601 00:44:57.094855
8602 00:44:57.098459 RX Delay 19 -> 252, step: 4
8603 00:44:57.099027
8604 00:44:57.100754 Set Vref, RX VrefLevel [Byte0]: 24
8605 00:44:57.104150 [Byte1]: 24
8606 00:44:57.104666
8607 00:44:57.107824 Set Vref, RX VrefLevel [Byte0]: 25
8608 00:44:57.110997 [Byte1]: 25
8609 00:44:57.111562
8610 00:44:57.114261 Set Vref, RX VrefLevel [Byte0]: 26
8611 00:44:57.117540 [Byte1]: 26
8612 00:44:57.121633
8613 00:44:57.122190 Set Vref, RX VrefLevel [Byte0]: 27
8614 00:44:57.124845 [Byte1]: 27
8615 00:44:57.129098
8616 00:44:57.129654 Set Vref, RX VrefLevel [Byte0]: 28
8617 00:44:57.132645 [Byte1]: 28
8618 00:44:57.136668
8619 00:44:57.137223 Set Vref, RX VrefLevel [Byte0]: 29
8620 00:44:57.139785 [Byte1]: 29
8621 00:44:57.144371
8622 00:44:57.144974 Set Vref, RX VrefLevel [Byte0]: 30
8623 00:44:57.147403 [Byte1]: 30
8624 00:44:57.152135
8625 00:44:57.152729 Set Vref, RX VrefLevel [Byte0]: 31
8626 00:44:57.155347 [Byte1]: 31
8627 00:44:57.159075
8628 00:44:57.159548 Set Vref, RX VrefLevel [Byte0]: 32
8629 00:44:57.162884 [Byte1]: 32
8630 00:44:57.166865
8631 00:44:57.167451 Set Vref, RX VrefLevel [Byte0]: 33
8632 00:44:57.170346 [Byte1]: 33
8633 00:44:57.174294
8634 00:44:57.174758 Set Vref, RX VrefLevel [Byte0]: 34
8635 00:44:57.177699 [Byte1]: 34
8636 00:44:57.182081
8637 00:44:57.182644 Set Vref, RX VrefLevel [Byte0]: 35
8638 00:44:57.185703 [Byte1]: 35
8639 00:44:57.190007
8640 00:44:57.190581 Set Vref, RX VrefLevel [Byte0]: 36
8641 00:44:57.192918 [Byte1]: 36
8642 00:44:57.197629
8643 00:44:57.198190 Set Vref, RX VrefLevel [Byte0]: 37
8644 00:44:57.200659 [Byte1]: 37
8645 00:44:57.204926
8646 00:44:57.205488 Set Vref, RX VrefLevel [Byte0]: 38
8647 00:44:57.208411 [Byte1]: 38
8648 00:44:57.212432
8649 00:44:57.213045 Set Vref, RX VrefLevel [Byte0]: 39
8650 00:44:57.216003 [Byte1]: 39
8651 00:44:57.219851
8652 00:44:57.220409 Set Vref, RX VrefLevel [Byte0]: 40
8653 00:44:57.223258 [Byte1]: 40
8654 00:44:57.227712
8655 00:44:57.228272 Set Vref, RX VrefLevel [Byte0]: 41
8656 00:44:57.230795 [Byte1]: 41
8657 00:44:57.235044
8658 00:44:57.235573 Set Vref, RX VrefLevel [Byte0]: 42
8659 00:44:57.238382 [Byte1]: 42
8660 00:44:57.242735
8661 00:44:57.243311 Set Vref, RX VrefLevel [Byte0]: 43
8662 00:44:57.246169 [Byte1]: 43
8663 00:44:57.250337
8664 00:44:57.250901 Set Vref, RX VrefLevel [Byte0]: 44
8665 00:44:57.253711 [Byte1]: 44
8666 00:44:57.258129
8667 00:44:57.258858 Set Vref, RX VrefLevel [Byte0]: 45
8668 00:44:57.260841 [Byte1]: 45
8669 00:44:57.265081
8670 00:44:57.265549 Set Vref, RX VrefLevel [Byte0]: 46
8671 00:44:57.268890 [Byte1]: 46
8672 00:44:57.272669
8673 00:44:57.273138 Set Vref, RX VrefLevel [Byte0]: 47
8674 00:44:57.276359 [Byte1]: 47
8675 00:44:57.280718
8676 00:44:57.281185 Set Vref, RX VrefLevel [Byte0]: 48
8677 00:44:57.283810 [Byte1]: 48
8678 00:44:57.287954
8679 00:44:57.288515 Set Vref, RX VrefLevel [Byte0]: 49
8680 00:44:57.291460 [Byte1]: 49
8681 00:44:57.295527
8682 00:44:57.296096 Set Vref, RX VrefLevel [Byte0]: 50
8683 00:44:57.298901 [Byte1]: 50
8684 00:44:57.303346
8685 00:44:57.303910 Set Vref, RX VrefLevel [Byte0]: 51
8686 00:44:57.306713 [Byte1]: 51
8687 00:44:57.310779
8688 00:44:57.311345 Set Vref, RX VrefLevel [Byte0]: 52
8689 00:44:57.314445 [Byte1]: 52
8690 00:44:57.318341
8691 00:44:57.318906 Set Vref, RX VrefLevel [Byte0]: 53
8692 00:44:57.321475 [Byte1]: 53
8693 00:44:57.325979
8694 00:44:57.326548 Set Vref, RX VrefLevel [Byte0]: 54
8695 00:44:57.329450 [Byte1]: 54
8696 00:44:57.333670
8697 00:44:57.334238 Set Vref, RX VrefLevel [Byte0]: 55
8698 00:44:57.336912 [Byte1]: 55
8699 00:44:57.341112
8700 00:44:57.341573 Set Vref, RX VrefLevel [Byte0]: 56
8701 00:44:57.344336 [Byte1]: 56
8702 00:44:57.348762
8703 00:44:57.349339 Set Vref, RX VrefLevel [Byte0]: 57
8704 00:44:57.352341 [Byte1]: 57
8705 00:44:57.356494
8706 00:44:57.357101 Set Vref, RX VrefLevel [Byte0]: 58
8707 00:44:57.362765 [Byte1]: 58
8708 00:44:57.363483
8709 00:44:57.366267 Set Vref, RX VrefLevel [Byte0]: 59
8710 00:44:57.369290 [Byte1]: 59
8711 00:44:57.369758
8712 00:44:57.372644 Set Vref, RX VrefLevel [Byte0]: 60
8713 00:44:57.376026 [Byte1]: 60
8714 00:44:57.376672
8715 00:44:57.379293 Set Vref, RX VrefLevel [Byte0]: 61
8716 00:44:57.382466 [Byte1]: 61
8717 00:44:57.386288
8718 00:44:57.386754 Set Vref, RX VrefLevel [Byte0]: 62
8719 00:44:57.389624 [Byte1]: 62
8720 00:44:57.394145
8721 00:44:57.394748 Set Vref, RX VrefLevel [Byte0]: 63
8722 00:44:57.397280 [Byte1]: 63
8723 00:44:57.401648
8724 00:44:57.402216 Set Vref, RX VrefLevel [Byte0]: 64
8725 00:44:57.405002 [Byte1]: 64
8726 00:44:57.409622
8727 00:44:57.410271 Set Vref, RX VrefLevel [Byte0]: 65
8728 00:44:57.412699 [Byte1]: 65
8729 00:44:57.416694
8730 00:44:57.417269 Set Vref, RX VrefLevel [Byte0]: 66
8731 00:44:57.420468 [Byte1]: 66
8732 00:44:57.424708
8733 00:44:57.425273 Set Vref, RX VrefLevel [Byte0]: 67
8734 00:44:57.428110 [Byte1]: 67
8735 00:44:57.431853
8736 00:44:57.432420 Set Vref, RX VrefLevel [Byte0]: 68
8737 00:44:57.434984 [Byte1]: 68
8738 00:44:57.439569
8739 00:44:57.440054 Set Vref, RX VrefLevel [Byte0]: 69
8740 00:44:57.443109 [Byte1]: 69
8741 00:44:57.447115
8742 00:44:57.447687 Set Vref, RX VrefLevel [Byte0]: 70
8743 00:44:57.450251 [Byte1]: 70
8744 00:44:57.455032
8745 00:44:57.455592 Set Vref, RX VrefLevel [Byte0]: 71
8746 00:44:57.457965 [Byte1]: 71
8747 00:44:57.462649
8748 00:44:57.463212 Set Vref, RX VrefLevel [Byte0]: 72
8749 00:44:57.465317 [Byte1]: 72
8750 00:44:57.470133
8751 00:44:57.470693 Set Vref, RX VrefLevel [Byte0]: 73
8752 00:44:57.473280 [Byte1]: 73
8753 00:44:57.477359
8754 00:44:57.477928 Final RX Vref Byte 0 = 53 to rank0
8755 00:44:57.481002 Final RX Vref Byte 1 = 65 to rank0
8756 00:44:57.484095 Final RX Vref Byte 0 = 53 to rank1
8757 00:44:57.487421 Final RX Vref Byte 1 = 65 to rank1==
8758 00:44:57.490597 Dram Type= 6, Freq= 0, CH_1, rank 0
8759 00:44:57.497439 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8760 00:44:57.498016 ==
8761 00:44:57.498392 DQS Delay:
8762 00:44:57.498736 DQS0 = 0, DQS1 = 0
8763 00:44:57.500655 DQM Delay:
8764 00:44:57.501219 DQM0 = 133, DQM1 = 129
8765 00:44:57.504236 DQ Delay:
8766 00:44:57.507070 DQ0 =136, DQ1 =130, DQ2 =122, DQ3 =132
8767 00:44:57.510999 DQ4 =132, DQ5 =144, DQ6 =144, DQ7 =130
8768 00:44:57.514273 DQ8 =116, DQ9 =118, DQ10 =132, DQ11 =120
8769 00:44:57.517284 DQ12 =140, DQ13 =134, DQ14 =136, DQ15 =136
8770 00:44:57.517851
8771 00:44:57.518218
8772 00:44:57.518559
8773 00:44:57.521036 [DramC_TX_OE_Calibration] TA2
8774 00:44:57.523911 Original DQ_B0 (3 6) =30, OEN = 27
8775 00:44:57.527423 Original DQ_B1 (3 6) =30, OEN = 27
8776 00:44:57.530413 24, 0x0, End_B0=24 End_B1=24
8777 00:44:57.530903 25, 0x0, End_B0=25 End_B1=25
8778 00:44:57.534067 26, 0x0, End_B0=26 End_B1=26
8779 00:44:57.537026 27, 0x0, End_B0=27 End_B1=27
8780 00:44:57.540531 28, 0x0, End_B0=28 End_B1=28
8781 00:44:57.541030 29, 0x0, End_B0=29 End_B1=29
8782 00:44:57.544010 30, 0x0, End_B0=30 End_B1=30
8783 00:44:57.547128 31, 0x4141, End_B0=30 End_B1=30
8784 00:44:57.550985 Byte0 end_step=30 best_step=27
8785 00:44:57.554029 Byte1 end_step=30 best_step=27
8786 00:44:57.557261 Byte0 TX OE(2T, 0.5T) = (3, 3)
8787 00:44:57.557814 Byte1 TX OE(2T, 0.5T) = (3, 3)
8788 00:44:57.558192
8789 00:44:57.560681
8790 00:44:57.567627 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a28, (MSB)MR19= 0x303, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
8791 00:44:57.570936 CH1 RK0: MR19=303, MR18=1A28
8792 00:44:57.577493 CH1_RK0: MR19=0x303, MR18=0x1A28, DQSOSC=389, MR23=63, INC=24, DEC=16
8793 00:44:57.578066
8794 00:44:57.580611 ----->DramcWriteLeveling(PI) begin...
8795 00:44:57.581093 ==
8796 00:44:57.583880 Dram Type= 6, Freq= 0, CH_1, rank 1
8797 00:44:57.587167 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8798 00:44:57.587830 ==
8799 00:44:57.590792 Write leveling (Byte 0): 25 => 25
8800 00:44:57.594110 Write leveling (Byte 1): 28 => 28
8801 00:44:57.597166 DramcWriteLeveling(PI) end<-----
8802 00:44:57.597661
8803 00:44:57.598346 ==
8804 00:44:57.600442 Dram Type= 6, Freq= 0, CH_1, rank 1
8805 00:44:57.603947 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8806 00:44:57.604421 ==
8807 00:44:57.607255 [Gating] SW mode calibration
8808 00:44:57.613857 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8809 00:44:57.620458 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8810 00:44:57.624062 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8811 00:44:57.627278 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8812 00:44:57.633914 1 4 8 | B1->B0 | 3232 2323 | 1 0 | (1 1) (0 0)
8813 00:44:57.637085 1 4 12 | B1->B0 | 3434 2525 | 1 1 | (1 1) (0 0)
8814 00:44:57.640230 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8815 00:44:57.647382 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8816 00:44:57.650464 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8817 00:44:57.653723 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8818 00:44:57.660322 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8819 00:44:57.663699 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8820 00:44:57.667615 1 5 8 | B1->B0 | 2727 3434 | 0 1 | (1 0) (1 0)
8821 00:44:57.673498 1 5 12 | B1->B0 | 2323 3030 | 0 1 | (1 0) (1 0)
8822 00:44:57.677247 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8823 00:44:57.680650 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8824 00:44:57.683898 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8825 00:44:57.690587 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8826 00:44:57.693645 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8827 00:44:57.697066 1 6 4 | B1->B0 | 2424 2323 | 0 0 | (1 1) (0 0)
8828 00:44:57.703832 1 6 8 | B1->B0 | 4545 2727 | 0 0 | (0 0) (0 0)
8829 00:44:57.707014 1 6 12 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
8830 00:44:57.710013 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8831 00:44:57.716946 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8832 00:44:57.720235 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8833 00:44:57.723695 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8834 00:44:57.730206 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8835 00:44:57.733414 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8836 00:44:57.736706 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8837 00:44:57.743617 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8838 00:44:57.747060 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8839 00:44:57.750379 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8840 00:44:57.757153 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8841 00:44:57.759958 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8842 00:44:57.763147 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8843 00:44:57.770279 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8844 00:44:57.773081 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8845 00:44:57.776535 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8846 00:44:57.783438 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8847 00:44:57.786715 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8848 00:44:57.789975 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8849 00:44:57.796646 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8850 00:44:57.800151 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8851 00:44:57.803353 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8852 00:44:57.809790 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8853 00:44:57.813160 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8854 00:44:57.816975 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8855 00:44:57.819873 Total UI for P1: 0, mck2ui 16
8856 00:44:57.823244 best dqsien dly found for B0: ( 1, 9, 8)
8857 00:44:57.826917 Total UI for P1: 0, mck2ui 16
8858 00:44:57.830038 best dqsien dly found for B1: ( 1, 9, 8)
8859 00:44:57.833543 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8860 00:44:57.836587 best DQS1 dly(MCK, UI, PI) = (1, 9, 8)
8861 00:44:57.837159
8862 00:44:57.840275 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8863 00:44:57.843697 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 8)
8864 00:44:57.846623 [Gating] SW calibration Done
8865 00:44:57.847189 ==
8866 00:44:57.849959 Dram Type= 6, Freq= 0, CH_1, rank 1
8867 00:44:57.856843 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8868 00:44:57.857414 ==
8869 00:44:57.857793 RX Vref Scan: 0
8870 00:44:57.858141
8871 00:44:57.860005 RX Vref 0 -> 0, step: 1
8872 00:44:57.860619
8873 00:44:57.863076 RX Delay 0 -> 252, step: 8
8874 00:44:57.866818 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8875 00:44:57.869647 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8876 00:44:57.873165 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8877 00:44:57.876471 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8878 00:44:57.882861 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8879 00:44:57.886343 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8880 00:44:57.889604 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
8881 00:44:57.893000 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8882 00:44:57.896342 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8883 00:44:57.903101 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8884 00:44:57.906517 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8885 00:44:57.909868 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8886 00:44:57.913413 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8887 00:44:57.916419 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8888 00:44:57.922803 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8889 00:44:57.926595 iDelay=200, Bit 15, Center 143 (88 ~ 199) 112
8890 00:44:57.927164 ==
8891 00:44:57.929892 Dram Type= 6, Freq= 0, CH_1, rank 1
8892 00:44:57.933058 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8893 00:44:57.933627 ==
8894 00:44:57.936459 DQS Delay:
8895 00:44:57.937086 DQS0 = 0, DQS1 = 0
8896 00:44:57.937464 DQM Delay:
8897 00:44:57.939610 DQM0 = 136, DQM1 = 132
8898 00:44:57.940078 DQ Delay:
8899 00:44:57.943132 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8900 00:44:57.946342 DQ4 =135, DQ5 =147, DQ6 =139, DQ7 =135
8901 00:44:57.949634 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =127
8902 00:44:57.956119 DQ12 =139, DQ13 =143, DQ14 =139, DQ15 =143
8903 00:44:57.956717
8904 00:44:57.957094
8905 00:44:57.957438 ==
8906 00:44:57.959861 Dram Type= 6, Freq= 0, CH_1, rank 1
8907 00:44:57.962736 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8908 00:44:57.963407 ==
8909 00:44:57.963799
8910 00:44:57.964142
8911 00:44:57.966132 TX Vref Scan disable
8912 00:44:57.966599 == TX Byte 0 ==
8913 00:44:57.972771 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8914 00:44:57.976297 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8915 00:44:57.976910 == TX Byte 1 ==
8916 00:44:57.982940 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8917 00:44:57.986109 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8918 00:44:57.986574 ==
8919 00:44:57.989003 Dram Type= 6, Freq= 0, CH_1, rank 1
8920 00:44:57.992487 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8921 00:44:57.993004 ==
8922 00:44:58.007565
8923 00:44:58.011207 TX Vref early break, caculate TX vref
8924 00:44:58.014566 TX Vref=16, minBit 9, minWin=22, winSum=384
8925 00:44:58.017187 TX Vref=18, minBit 9, minWin=23, winSum=393
8926 00:44:58.020712 TX Vref=20, minBit 10, minWin=23, winSum=401
8927 00:44:58.023818 TX Vref=22, minBit 9, minWin=24, winSum=407
8928 00:44:58.027433 TX Vref=24, minBit 9, minWin=24, winSum=415
8929 00:44:58.034103 TX Vref=26, minBit 9, minWin=25, winSum=424
8930 00:44:58.037077 TX Vref=28, minBit 9, minWin=25, winSum=422
8931 00:44:58.040848 TX Vref=30, minBit 10, minWin=24, winSum=414
8932 00:44:58.043937 TX Vref=32, minBit 10, minWin=24, winSum=408
8933 00:44:58.047584 TX Vref=34, minBit 0, minWin=24, winSum=402
8934 00:44:58.054189 TX Vref=36, minBit 11, minWin=23, winSum=391
8935 00:44:58.057522 [TxChooseVref] Worse bit 9, Min win 25, Win sum 424, Final Vref 26
8936 00:44:58.058102
8937 00:44:58.060312 Final TX Range 0 Vref 26
8938 00:44:58.060809
8939 00:44:58.061184 ==
8940 00:44:58.063638 Dram Type= 6, Freq= 0, CH_1, rank 1
8941 00:44:58.067375 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8942 00:44:58.070536 ==
8943 00:44:58.071015
8944 00:44:58.071488
8945 00:44:58.071933 TX Vref Scan disable
8946 00:44:58.077100 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8947 00:44:58.077667 == TX Byte 0 ==
8948 00:44:58.080888 u2DelayCellOfst[0]=16 cells (5 PI)
8949 00:44:58.083967 u2DelayCellOfst[1]=10 cells (3 PI)
8950 00:44:58.087256 u2DelayCellOfst[2]=0 cells (0 PI)
8951 00:44:58.090657 u2DelayCellOfst[3]=6 cells (2 PI)
8952 00:44:58.094629 u2DelayCellOfst[4]=10 cells (3 PI)
8953 00:44:58.097317 u2DelayCellOfst[5]=20 cells (6 PI)
8954 00:44:58.100396 u2DelayCellOfst[6]=20 cells (6 PI)
8955 00:44:58.103602 u2DelayCellOfst[7]=6 cells (2 PI)
8956 00:44:58.107592 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8957 00:44:58.110391 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8958 00:44:58.113797 == TX Byte 1 ==
8959 00:44:58.117302 u2DelayCellOfst[8]=0 cells (0 PI)
8960 00:44:58.120811 u2DelayCellOfst[9]=6 cells (2 PI)
8961 00:44:58.121393 u2DelayCellOfst[10]=10 cells (3 PI)
8962 00:44:58.123702 u2DelayCellOfst[11]=3 cells (1 PI)
8963 00:44:58.127259 u2DelayCellOfst[12]=16 cells (5 PI)
8964 00:44:58.130744 u2DelayCellOfst[13]=20 cells (6 PI)
8965 00:44:58.133826 u2DelayCellOfst[14]=16 cells (5 PI)
8966 00:44:58.137436 u2DelayCellOfst[15]=20 cells (6 PI)
8967 00:44:58.143775 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8968 00:44:58.147216 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8969 00:44:58.147804 DramC Write-DBI on
8970 00:44:58.148376 ==
8971 00:44:58.150221 Dram Type= 6, Freq= 0, CH_1, rank 1
8972 00:44:58.157151 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8973 00:44:58.157733 ==
8974 00:44:58.158217
8975 00:44:58.158665
8976 00:44:58.159099 TX Vref Scan disable
8977 00:44:58.161217 == TX Byte 0 ==
8978 00:44:58.164223 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8979 00:44:58.167762 == TX Byte 1 ==
8980 00:44:58.171419 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8981 00:44:58.174286 DramC Write-DBI off
8982 00:44:58.174759
8983 00:44:58.175299 [DATLAT]
8984 00:44:58.175745 Freq=1600, CH1 RK1
8985 00:44:58.176182
8986 00:44:58.177792 DATLAT Default: 0xf
8987 00:44:58.178266 0, 0xFFFF, sum = 0
8988 00:44:58.181002 1, 0xFFFF, sum = 0
8989 00:44:58.184054 2, 0xFFFF, sum = 0
8990 00:44:58.184533 3, 0xFFFF, sum = 0
8991 00:44:58.187759 4, 0xFFFF, sum = 0
8992 00:44:58.188332 5, 0xFFFF, sum = 0
8993 00:44:58.190676 6, 0xFFFF, sum = 0
8994 00:44:58.191157 7, 0xFFFF, sum = 0
8995 00:44:58.194067 8, 0xFFFF, sum = 0
8996 00:44:58.194550 9, 0xFFFF, sum = 0
8997 00:44:58.197760 10, 0xFFFF, sum = 0
8998 00:44:58.198380 11, 0xFFFF, sum = 0
8999 00:44:58.200825 12, 0xFFFF, sum = 0
9000 00:44:58.201306 13, 0xFFFF, sum = 0
9001 00:44:58.204470 14, 0x0, sum = 1
9002 00:44:58.205159 15, 0x0, sum = 2
9003 00:44:58.207443 16, 0x0, sum = 3
9004 00:44:58.207911 17, 0x0, sum = 4
9005 00:44:58.211135 best_step = 15
9006 00:44:58.211693
9007 00:44:58.212060 ==
9008 00:44:58.214487 Dram Type= 6, Freq= 0, CH_1, rank 1
9009 00:44:58.217318 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9010 00:44:58.217786 ==
9011 00:44:58.218155 RX Vref Scan: 0
9012 00:44:58.221114
9013 00:44:58.221576 RX Vref 0 -> 0, step: 1
9014 00:44:58.221943
9015 00:44:58.224408 RX Delay 19 -> 252, step: 4
9016 00:44:58.227588 iDelay=195, Bit 0, Center 138 (95 ~ 182) 88
9017 00:44:58.234631 iDelay=195, Bit 1, Center 130 (83 ~ 178) 96
9018 00:44:58.237481 iDelay=195, Bit 2, Center 120 (71 ~ 170) 100
9019 00:44:58.241129 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
9020 00:44:58.244346 iDelay=195, Bit 4, Center 134 (87 ~ 182) 96
9021 00:44:58.247895 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
9022 00:44:58.251133 iDelay=195, Bit 6, Center 142 (95 ~ 190) 96
9023 00:44:58.257493 iDelay=195, Bit 7, Center 130 (83 ~ 178) 96
9024 00:44:58.261377 iDelay=195, Bit 8, Center 114 (67 ~ 162) 96
9025 00:44:58.264601 iDelay=195, Bit 9, Center 120 (71 ~ 170) 100
9026 00:44:58.267730 iDelay=195, Bit 10, Center 130 (79 ~ 182) 104
9027 00:44:58.270735 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
9028 00:44:58.277919 iDelay=195, Bit 12, Center 140 (91 ~ 190) 100
9029 00:44:58.281221 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
9030 00:44:58.284655 iDelay=195, Bit 14, Center 138 (91 ~ 186) 96
9031 00:44:58.287915 iDelay=195, Bit 15, Center 138 (87 ~ 190) 104
9032 00:44:58.288483 ==
9033 00:44:58.290810 Dram Type= 6, Freq= 0, CH_1, rank 1
9034 00:44:58.294025 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9035 00:44:58.297764 ==
9036 00:44:58.298329 DQS Delay:
9037 00:44:58.298870 DQS0 = 0, DQS1 = 0
9038 00:44:58.301155 DQM Delay:
9039 00:44:58.301625 DQM0 = 133, DQM1 = 130
9040 00:44:58.304100 DQ Delay:
9041 00:44:58.307544 DQ0 =138, DQ1 =130, DQ2 =120, DQ3 =130
9042 00:44:58.310629 DQ4 =134, DQ5 =146, DQ6 =142, DQ7 =130
9043 00:44:58.313942 DQ8 =114, DQ9 =120, DQ10 =130, DQ11 =124
9044 00:44:58.317468 DQ12 =140, DQ13 =138, DQ14 =138, DQ15 =138
9045 00:44:58.318034
9046 00:44:58.318405
9047 00:44:58.318743
9048 00:44:58.321006 [DramC_TX_OE_Calibration] TA2
9049 00:44:58.324254 Original DQ_B0 (3 6) =30, OEN = 27
9050 00:44:58.327389 Original DQ_B1 (3 6) =30, OEN = 27
9051 00:44:58.330669 24, 0x0, End_B0=24 End_B1=24
9052 00:44:58.331285 25, 0x0, End_B0=25 End_B1=25
9053 00:44:58.334019 26, 0x0, End_B0=26 End_B1=26
9054 00:44:58.337001 27, 0x0, End_B0=27 End_B1=27
9055 00:44:58.341101 28, 0x0, End_B0=28 End_B1=28
9056 00:44:58.341677 29, 0x0, End_B0=29 End_B1=29
9057 00:44:58.343827 30, 0x0, End_B0=30 End_B1=30
9058 00:44:58.347095 31, 0x4141, End_B0=30 End_B1=30
9059 00:44:58.351044 Byte0 end_step=30 best_step=27
9060 00:44:58.354085 Byte1 end_step=30 best_step=27
9061 00:44:58.357297 Byte0 TX OE(2T, 0.5T) = (3, 3)
9062 00:44:58.357864 Byte1 TX OE(2T, 0.5T) = (3, 3)
9063 00:44:58.358236
9064 00:44:58.360642
9065 00:44:58.367434 [DQSOSCAuto] RK1, (LSB)MR18= 0x1e08, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 394 ps
9066 00:44:58.370550 CH1 RK1: MR19=303, MR18=1E08
9067 00:44:58.377439 CH1_RK1: MR19=0x303, MR18=0x1E08, DQSOSC=394, MR23=63, INC=23, DEC=15
9068 00:44:58.380801 [RxdqsGatingPostProcess] freq 1600
9069 00:44:58.384388 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9070 00:44:58.387163 best DQS0 dly(2T, 0.5T) = (1, 1)
9071 00:44:58.390351 best DQS1 dly(2T, 0.5T) = (1, 1)
9072 00:44:58.393881 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9073 00:44:58.397166 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9074 00:44:58.400177 best DQS0 dly(2T, 0.5T) = (1, 1)
9075 00:44:58.403590 best DQS1 dly(2T, 0.5T) = (1, 1)
9076 00:44:58.407531 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9077 00:44:58.410411 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9078 00:44:58.413542 Pre-setting of DQS Precalculation
9079 00:44:58.416996 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9080 00:44:58.423704 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9081 00:44:58.430461 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9082 00:44:58.431042
9083 00:44:58.433596
9084 00:44:58.434071 [Calibration Summary] 3200 Mbps
9085 00:44:58.436631 CH 0, Rank 0
9086 00:44:58.437110 SW Impedance : PASS
9087 00:44:58.440005 DUTY Scan : NO K
9088 00:44:58.443366 ZQ Calibration : PASS
9089 00:44:58.443840 Jitter Meter : NO K
9090 00:44:58.446934 CBT Training : PASS
9091 00:44:58.450019 Write leveling : PASS
9092 00:44:58.450598 RX DQS gating : PASS
9093 00:44:58.453405 RX DQ/DQS(RDDQC) : PASS
9094 00:44:58.456843 TX DQ/DQS : PASS
9095 00:44:58.457427 RX DATLAT : PASS
9096 00:44:58.460150 RX DQ/DQS(Engine): PASS
9097 00:44:58.463270 TX OE : PASS
9098 00:44:58.463851 All Pass.
9099 00:44:58.464332
9100 00:44:58.464853 CH 0, Rank 1
9101 00:44:58.466069 SW Impedance : PASS
9102 00:44:58.469613 DUTY Scan : NO K
9103 00:44:58.470078 ZQ Calibration : PASS
9104 00:44:58.473302 Jitter Meter : NO K
9105 00:44:58.476705 CBT Training : PASS
9106 00:44:58.477277 Write leveling : PASS
9107 00:44:58.479484 RX DQS gating : PASS
9108 00:44:58.479948 RX DQ/DQS(RDDQC) : PASS
9109 00:44:58.483059 TX DQ/DQS : PASS
9110 00:44:58.486375 RX DATLAT : PASS
9111 00:44:58.486936 RX DQ/DQS(Engine): PASS
9112 00:44:58.489711 TX OE : PASS
9113 00:44:58.490285 All Pass.
9114 00:44:58.490658
9115 00:44:58.492733 CH 1, Rank 0
9116 00:44:58.493199 SW Impedance : PASS
9117 00:44:58.496655 DUTY Scan : NO K
9118 00:44:58.500224 ZQ Calibration : PASS
9119 00:44:58.500882 Jitter Meter : NO K
9120 00:44:58.503613 CBT Training : PASS
9121 00:44:58.506258 Write leveling : PASS
9122 00:44:58.506729 RX DQS gating : PASS
9123 00:44:58.509642 RX DQ/DQS(RDDQC) : PASS
9124 00:44:58.513430 TX DQ/DQS : PASS
9125 00:44:58.513995 RX DATLAT : PASS
9126 00:44:58.516097 RX DQ/DQS(Engine): PASS
9127 00:44:58.519402 TX OE : PASS
9128 00:44:58.520013 All Pass.
9129 00:44:58.520398
9130 00:44:58.520796 CH 1, Rank 1
9131 00:44:58.522910 SW Impedance : PASS
9132 00:44:58.526173 DUTY Scan : NO K
9133 00:44:58.526638 ZQ Calibration : PASS
9134 00:44:58.529875 Jitter Meter : NO K
9135 00:44:58.532878 CBT Training : PASS
9136 00:44:58.533456 Write leveling : PASS
9137 00:44:58.536001 RX DQS gating : PASS
9138 00:44:58.536467 RX DQ/DQS(RDDQC) : PASS
9139 00:44:58.539870 TX DQ/DQS : PASS
9140 00:44:58.542846 RX DATLAT : PASS
9141 00:44:58.543310 RX DQ/DQS(Engine): PASS
9142 00:44:58.545911 TX OE : PASS
9143 00:44:58.546375 All Pass.
9144 00:44:58.546740
9145 00:44:58.549178 DramC Write-DBI on
9146 00:44:58.552746 PER_BANK_REFRESH: Hybrid Mode
9147 00:44:58.553211 TX_TRACKING: ON
9148 00:44:58.562717 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9149 00:44:58.569354 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9150 00:44:58.576212 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9151 00:44:58.582929 [FAST_K] Save calibration result to emmc
9152 00:44:58.583519 sync common calibartion params.
9153 00:44:58.585713 sync cbt_mode0:1, 1:1
9154 00:44:58.589358 dram_init: ddr_geometry: 2
9155 00:44:58.589954 dram_init: ddr_geometry: 2
9156 00:44:58.592698 dram_init: ddr_geometry: 2
9157 00:44:58.595829 0:dram_rank_size:100000000
9158 00:44:58.599103 1:dram_rank_size:100000000
9159 00:44:58.602472 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9160 00:44:58.605669 DFS_SHUFFLE_HW_MODE: ON
9161 00:44:58.609279 dramc_set_vcore_voltage set vcore to 725000
9162 00:44:58.612359 Read voltage for 1600, 0
9163 00:44:58.613007 Vio18 = 0
9164 00:44:58.613466 Vcore = 725000
9165 00:44:58.615803 Vdram = 0
9166 00:44:58.616360 Vddq = 0
9167 00:44:58.616853 Vmddr = 0
9168 00:44:58.619051 switch to 3200 Mbps bootup
9169 00:44:58.622411 [DramcRunTimeConfig]
9170 00:44:58.622874 PHYPLL
9171 00:44:58.623245 DPM_CONTROL_AFTERK: ON
9172 00:44:58.625540 PER_BANK_REFRESH: ON
9173 00:44:58.629382 REFRESH_OVERHEAD_REDUCTION: ON
9174 00:44:58.629875 CMD_PICG_NEW_MODE: OFF
9175 00:44:58.632146 XRTWTW_NEW_MODE: ON
9176 00:44:58.635439 XRTRTR_NEW_MODE: ON
9177 00:44:58.635934 TX_TRACKING: ON
9178 00:44:58.638987 RDSEL_TRACKING: OFF
9179 00:44:58.639456 DQS Precalculation for DVFS: ON
9180 00:44:58.642273 RX_TRACKING: OFF
9181 00:44:58.642759 HW_GATING DBG: ON
9182 00:44:58.645721 ZQCS_ENABLE_LP4: ON
9183 00:44:58.646413 RX_PICG_NEW_MODE: ON
9184 00:44:58.649127 TX_PICG_NEW_MODE: ON
9185 00:44:58.652285 ENABLE_RX_DCM_DPHY: ON
9186 00:44:58.655681 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9187 00:44:58.656191 DUMMY_READ_FOR_TRACKING: OFF
9188 00:44:58.658579 !!! SPM_CONTROL_AFTERK: OFF
9189 00:44:58.661952 !!! SPM could not control APHY
9190 00:44:58.665588 IMPEDANCE_TRACKING: ON
9191 00:44:58.666026 TEMP_SENSOR: ON
9192 00:44:58.669330 HW_SAVE_FOR_SR: OFF
9193 00:44:58.669759 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9194 00:44:58.675620 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9195 00:44:58.676158 Read ODT Tracking: ON
9196 00:44:58.679172 Refresh Rate DeBounce: ON
9197 00:44:58.682579 DFS_NO_QUEUE_FLUSH: ON
9198 00:44:58.683115 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9199 00:44:58.685920 ENABLE_DFS_RUNTIME_MRW: OFF
9200 00:44:58.688979 DDR_RESERVE_NEW_MODE: ON
9201 00:44:58.692181 MR_CBT_SWITCH_FREQ: ON
9202 00:44:58.692633 =========================
9203 00:44:58.711815 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9204 00:44:58.715176 dram_init: ddr_geometry: 2
9205 00:44:58.733436 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9206 00:44:58.736698 dram_init: dram init end (result: 0)
9207 00:44:58.743602 DRAM-K: Full calibration passed in 24467 msecs
9208 00:44:58.746687 MRC: failed to locate region type 0.
9209 00:44:58.747189 DRAM rank0 size:0x100000000,
9210 00:44:58.749743 DRAM rank1 size=0x100000000
9211 00:44:58.760141 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9212 00:44:58.766706 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9213 00:44:58.773439 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9214 00:44:58.780097 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9215 00:44:58.783051 DRAM rank0 size:0x100000000,
9216 00:44:58.786388 DRAM rank1 size=0x100000000
9217 00:44:58.786969 CBMEM:
9218 00:44:58.789552 IMD: root @ 0xfffff000 254 entries.
9219 00:44:58.793376 IMD: root @ 0xffffec00 62 entries.
9220 00:44:58.796792 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9221 00:44:58.799986 WARNING: RO_VPD is uninitialized or empty.
9222 00:44:58.806271 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9223 00:44:58.813175 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9224 00:44:58.826089 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9225 00:44:58.837912 BS: romstage times (exec / console): total (unknown) / 23985 ms
9226 00:44:58.838494
9227 00:44:58.838868
9228 00:44:58.847650 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9229 00:44:58.850932 ARM64: Exception handlers installed.
9230 00:44:58.854071 ARM64: Testing exception
9231 00:44:58.857413 ARM64: Done test exception
9232 00:44:58.858000 Enumerating buses...
9233 00:44:58.861061 Show all devs... Before device enumeration.
9234 00:44:58.863865 Root Device: enabled 1
9235 00:44:58.867414 CPU_CLUSTER: 0: enabled 1
9236 00:44:58.867937 CPU: 00: enabled 1
9237 00:44:58.870842 Compare with tree...
9238 00:44:58.871403 Root Device: enabled 1
9239 00:44:58.874229 CPU_CLUSTER: 0: enabled 1
9240 00:44:58.877137 CPU: 00: enabled 1
9241 00:44:58.877608 Root Device scanning...
9242 00:44:58.880517 scan_static_bus for Root Device
9243 00:44:58.884001 CPU_CLUSTER: 0 enabled
9244 00:44:58.887667 scan_static_bus for Root Device done
9245 00:44:58.890768 scan_bus: bus Root Device finished in 8 msecs
9246 00:44:58.891329 done
9247 00:44:58.897120 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9248 00:44:58.900534 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9249 00:44:58.907455 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9250 00:44:58.910169 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9251 00:44:58.913730 Allocating resources...
9252 00:44:58.917337 Reading resources...
9253 00:44:58.920807 Root Device read_resources bus 0 link: 0
9254 00:44:58.921377 DRAM rank0 size:0x100000000,
9255 00:44:58.923948 DRAM rank1 size=0x100000000
9256 00:44:58.927148 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9257 00:44:58.930695 CPU: 00 missing read_resources
9258 00:44:58.933853 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9259 00:44:58.940456 Root Device read_resources bus 0 link: 0 done
9260 00:44:58.941055 Done reading resources.
9261 00:44:58.946851 Show resources in subtree (Root Device)...After reading.
9262 00:44:58.950039 Root Device child on link 0 CPU_CLUSTER: 0
9263 00:44:58.953700 CPU_CLUSTER: 0 child on link 0 CPU: 00
9264 00:44:58.963517 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9265 00:44:58.964087 CPU: 00
9266 00:44:58.966893 Root Device assign_resources, bus 0 link: 0
9267 00:44:58.970302 CPU_CLUSTER: 0 missing set_resources
9268 00:44:58.977029 Root Device assign_resources, bus 0 link: 0 done
9269 00:44:58.977593 Done setting resources.
9270 00:44:58.983798 Show resources in subtree (Root Device)...After assigning values.
9271 00:44:58.986935 Root Device child on link 0 CPU_CLUSTER: 0
9272 00:44:58.990144 CPU_CLUSTER: 0 child on link 0 CPU: 00
9273 00:44:59.000432 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9274 00:44:59.001056 CPU: 00
9275 00:44:59.003937 Done allocating resources.
9276 00:44:59.007281 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9277 00:44:59.010967 Enabling resources...
9278 00:44:59.011526 done.
9279 00:44:59.016690 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9280 00:44:59.017166 Initializing devices...
9281 00:44:59.020261 Root Device init
9282 00:44:59.020869 init hardware done!
9283 00:44:59.023872 0x00000018: ctrlr->caps
9284 00:44:59.027051 52.000 MHz: ctrlr->f_max
9285 00:44:59.027643 0.400 MHz: ctrlr->f_min
9286 00:44:59.030372 0x40ff8080: ctrlr->voltages
9287 00:44:59.030959 sclk: 390625
9288 00:44:59.034100 Bus Width = 1
9289 00:44:59.034676 sclk: 390625
9290 00:44:59.035160 Bus Width = 1
9291 00:44:59.037221 Early init status = 3
9292 00:44:59.043769 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9293 00:44:59.046905 in-header: 03 fc 00 00 01 00 00 00
9294 00:44:59.047388 in-data: 00
9295 00:44:59.053381 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9296 00:44:59.057586 in-header: 03 fd 00 00 00 00 00 00
9297 00:44:59.061282 in-data:
9298 00:44:59.063850 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9299 00:44:59.068196 in-header: 03 fc 00 00 01 00 00 00
9300 00:44:59.071626 in-data: 00
9301 00:44:59.074863 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9302 00:44:59.080603 in-header: 03 fd 00 00 00 00 00 00
9303 00:44:59.084153 in-data:
9304 00:44:59.087611 [SSUSB] Setting up USB HOST controller...
9305 00:44:59.090633 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9306 00:44:59.093759 [SSUSB] phy power-on done.
9307 00:44:59.097357 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9308 00:44:59.104299 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9309 00:44:59.107063 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9310 00:44:59.114343 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9311 00:44:59.121012 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9312 00:44:59.127882 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9313 00:44:59.134396 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9314 00:44:59.140856 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9315 00:44:59.141422 SPM: binary array size = 0x9dc
9316 00:44:59.147250 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9317 00:44:59.153613 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9318 00:44:59.160493 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9319 00:44:59.164188 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9320 00:44:59.166802 configure_display: Starting display init
9321 00:44:59.204174 anx7625_power_on_init: Init interface.
9322 00:44:59.207219 anx7625_disable_pd_protocol: Disabled PD feature.
9323 00:44:59.210413 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9324 00:44:59.238747 anx7625_start_dp_work: Secure OCM version=00
9325 00:44:59.241329 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9326 00:44:59.256645 sp_tx_get_edid_block: EDID Block = 1
9327 00:44:59.359328 Extracted contents:
9328 00:44:59.362579 header: 00 ff ff ff ff ff ff 00
9329 00:44:59.365834 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9330 00:44:59.369173 version: 01 04
9331 00:44:59.372251 basic params: 95 1f 11 78 0a
9332 00:44:59.375657 chroma info: 76 90 94 55 54 90 27 21 50 54
9333 00:44:59.378823 established: 00 00 00
9334 00:44:59.385843 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9335 00:44:59.389040 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9336 00:44:59.395208 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9337 00:44:59.402273 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9338 00:44:59.409149 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9339 00:44:59.412221 extensions: 00
9340 00:44:59.412827 checksum: fb
9341 00:44:59.413208
9342 00:44:59.415501 Manufacturer: IVO Model 57d Serial Number 0
9343 00:44:59.418962 Made week 0 of 2020
9344 00:44:59.419532 EDID version: 1.4
9345 00:44:59.421831 Digital display
9346 00:44:59.425460 6 bits per primary color channel
9347 00:44:59.426038 DisplayPort interface
9348 00:44:59.428785 Maximum image size: 31 cm x 17 cm
9349 00:44:59.432141 Gamma: 220%
9350 00:44:59.432764 Check DPMS levels
9351 00:44:59.435568 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9352 00:44:59.439073 First detailed timing is preferred timing
9353 00:44:59.441719 Established timings supported:
9354 00:44:59.445189 Standard timings supported:
9355 00:44:59.445656 Detailed timings
9356 00:44:59.451589 Hex of detail: 383680a07038204018303c0035ae10000019
9357 00:44:59.455506 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9358 00:44:59.462301 0780 0798 07c8 0820 hborder 0
9359 00:44:59.465244 0438 043b 0447 0458 vborder 0
9360 00:44:59.468720 -hsync -vsync
9361 00:44:59.469188 Did detailed timing
9362 00:44:59.472084 Hex of detail: 000000000000000000000000000000000000
9363 00:44:59.475230 Manufacturer-specified data, tag 0
9364 00:44:59.481819 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9365 00:44:59.482280 ASCII string: InfoVision
9366 00:44:59.488517 Hex of detail: 000000fe00523134304e574635205248200a
9367 00:44:59.491870 ASCII string: R140NWF5 RH
9368 00:44:59.492331 Checksum
9369 00:44:59.492726 Checksum: 0xfb (valid)
9370 00:44:59.498251 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9371 00:44:59.501764 DSI data_rate: 832800000 bps
9372 00:44:59.505172 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9373 00:44:59.512112 anx7625_parse_edid: pixelclock(138800).
9374 00:44:59.515062 hactive(1920), hsync(48), hfp(24), hbp(88)
9375 00:44:59.518578 vactive(1080), vsync(12), vfp(3), vbp(17)
9376 00:44:59.521837 anx7625_dsi_config: config dsi.
9377 00:44:59.528169 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9378 00:44:59.541228 anx7625_dsi_config: success to config DSI
9379 00:44:59.544216 anx7625_dp_start: MIPI phy setup OK.
9380 00:44:59.548034 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9381 00:44:59.551396 mtk_ddp_mode_set invalid vrefresh 60
9382 00:44:59.554548 main_disp_path_setup
9383 00:44:59.555110 ovl_layer_smi_id_en
9384 00:44:59.557923 ovl_layer_smi_id_en
9385 00:44:59.558486 ccorr_config
9386 00:44:59.558851 aal_config
9387 00:44:59.561170 gamma_config
9388 00:44:59.561625 postmask_config
9389 00:44:59.564668 dither_config
9390 00:44:59.567881 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9391 00:44:59.574756 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9392 00:44:59.577983 Root Device init finished in 554 msecs
9393 00:44:59.578536 CPU_CLUSTER: 0 init
9394 00:44:59.587964 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9395 00:44:59.590919 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9396 00:44:59.594609 APU_MBOX 0x190000b0 = 0x10001
9397 00:44:59.597550 APU_MBOX 0x190001b0 = 0x10001
9398 00:44:59.601055 APU_MBOX 0x190005b0 = 0x10001
9399 00:44:59.603844 APU_MBOX 0x190006b0 = 0x10001
9400 00:44:59.607601 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9401 00:44:59.620028 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9402 00:44:59.632406 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9403 00:44:59.638925 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9404 00:44:59.651173 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9405 00:44:59.660166 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9406 00:44:59.663097 CPU_CLUSTER: 0 init finished in 81 msecs
9407 00:44:59.666285 Devices initialized
9408 00:44:59.669762 Show all devs... After init.
9409 00:44:59.670233 Root Device: enabled 1
9410 00:44:59.673203 CPU_CLUSTER: 0: enabled 1
9411 00:44:59.676363 CPU: 00: enabled 1
9412 00:44:59.679387 BS: BS_DEV_INIT run times (exec / console): 212 / 447 ms
9413 00:44:59.682732 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9414 00:44:59.686180 ELOG: NV offset 0x57f000 size 0x1000
9415 00:44:59.692511 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9416 00:44:59.699356 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9417 00:44:59.702648 ELOG: Event(17) added with size 13 at 2024-06-16 00:43:34 UTC
9418 00:44:59.706190 out: cmd=0x121: 03 db 21 01 00 00 00 00
9419 00:44:59.710688 in-header: 03 4f 00 00 2c 00 00 00
9420 00:44:59.724249 in-data: f0 70 00 00 00 00 00 00 0a 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9421 00:44:59.730912 ELOG: Event(A1) added with size 10 at 2024-06-16 00:43:34 UTC
9422 00:44:59.737991 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
9423 00:44:59.741277 ELOG: Event(A0) added with size 9 at 2024-06-16 00:43:34 UTC
9424 00:44:59.747967 elog_add_boot_reason: Logged dev mode boot
9425 00:44:59.751248 BS: BS_POST_DEVICE entry times (exec / console): 3 / 64 ms
9426 00:44:59.754277 Finalize devices...
9427 00:44:59.754749 Devices finalized
9428 00:44:59.761464 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9429 00:44:59.764527 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
9430 00:44:59.767998 in-header: 03 07 00 00 08 00 00 00
9431 00:44:59.771043 in-data: aa e4 47 04 13 02 00 00
9432 00:44:59.771629 Chrome EC: UHEPI supported
9433 00:44:59.777578 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
9434 00:44:59.781625 in-header: 03 a9 00 00 08 00 00 00
9435 00:44:59.784986 in-data: 84 60 60 08 00 00 00 00
9436 00:44:59.791482 ELOG: Event(91) added with size 10 at 2024-06-16 00:43:34 UTC
9437 00:44:59.795132 Chrome EC: clear events_b mask to 0x0000000020004000
9438 00:44:59.801448 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
9439 00:44:59.805752 in-header: 03 fd 00 00 00 00 00 00
9440 00:44:59.809109 in-data:
9441 00:44:59.812400 BS: BS_WRITE_TABLES entry times (exec / console): 2 / 46 ms
9442 00:44:59.815504 Writing coreboot table at 0xffe64000
9443 00:44:59.821990 0. 000000000010a000-0000000000113fff: RAMSTAGE
9444 00:44:59.825408 1. 0000000040000000-00000000400fffff: RAM
9445 00:44:59.828635 2. 0000000040100000-000000004032afff: RAMSTAGE
9446 00:44:59.832190 3. 000000004032b000-00000000545fffff: RAM
9447 00:44:59.835448 4. 0000000054600000-000000005465ffff: BL31
9448 00:44:59.838879 5. 0000000054660000-00000000ffe63fff: RAM
9449 00:44:59.845272 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9450 00:44:59.849122 7. 0000000100000000-000000023fffffff: RAM
9451 00:44:59.852138 Passing 5 GPIOs to payload:
9452 00:44:59.855435 NAME | PORT | POLARITY | VALUE
9453 00:44:59.862649 EC in RW | 0x000000aa | low | undefined
9454 00:44:59.865445 EC interrupt | 0x00000005 | low | undefined
9455 00:44:59.868796 TPM interrupt | 0x000000ab | high | undefined
9456 00:44:59.875857 SD card detect | 0x00000011 | high | undefined
9457 00:44:59.878708 speaker enable | 0x00000093 | high | undefined
9458 00:44:59.882337 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9459 00:44:59.885697 in-header: 03 f9 00 00 02 00 00 00
9460 00:44:59.889000 in-data: 02 00
9461 00:44:59.892294 ADC[4]: Raw value=901032 ID=7
9462 00:44:59.892943 ADC[3]: Raw value=212810 ID=1
9463 00:44:59.895543 RAM Code: 0x71
9464 00:44:59.898532 ADC[6]: Raw value=74502 ID=0
9465 00:44:59.898997 ADC[5]: Raw value=212072 ID=1
9466 00:44:59.902576 SKU Code: 0x1
9467 00:44:59.905385 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum afca
9468 00:44:59.908658 coreboot table: 964 bytes.
9469 00:44:59.912279 IMD ROOT 0. 0xfffff000 0x00001000
9470 00:44:59.915594 IMD SMALL 1. 0xffffe000 0x00001000
9471 00:44:59.918621 RO MCACHE 2. 0xffffc000 0x00001104
9472 00:44:59.922157 CONSOLE 3. 0xfff7c000 0x00080000
9473 00:44:59.925834 FMAP 4. 0xfff7b000 0x00000452
9474 00:44:59.928506 TIME STAMP 5. 0xfff7a000 0x00000910
9475 00:44:59.932126 VBOOT WORK 6. 0xfff66000 0x00014000
9476 00:44:59.935365 RAMOOPS 7. 0xffe66000 0x00100000
9477 00:44:59.938251 COREBOOT 8. 0xffe64000 0x00002000
9478 00:44:59.941652 IMD small region:
9479 00:44:59.945012 IMD ROOT 0. 0xffffec00 0x00000400
9480 00:44:59.948627 VPD 1. 0xffffeb80 0x0000006c
9481 00:44:59.951937 MMC STATUS 2. 0xffffeb60 0x00000004
9482 00:44:59.955189 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9483 00:44:59.961733 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9484 00:45:00.002970 read SPI 0x3990ec 0x4f1b0: 34846 us, 9298 KB/s, 74.384 Mbps
9485 00:45:00.006041 Checking segment from ROM address 0x40100000
9486 00:45:00.009477 Checking segment from ROM address 0x4010001c
9487 00:45:00.016016 Loading segment from ROM address 0x40100000
9488 00:45:00.016607 code (compression=0)
9489 00:45:00.022820 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9490 00:45:00.032726 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9491 00:45:00.033310 it's not compressed!
9492 00:45:00.039552 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9493 00:45:00.042631 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9494 00:45:00.063381 Loading segment from ROM address 0x4010001c
9495 00:45:00.063949 Entry Point 0x80000000
9496 00:45:00.066338 Loaded segments
9497 00:45:00.069492 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9498 00:45:00.075943 Jumping to boot code at 0x80000000(0xffe64000)
9499 00:45:00.083130 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9500 00:45:00.089304 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9501 00:45:00.097492 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9502 00:45:00.101240 Checking segment from ROM address 0x40100000
9503 00:45:00.104502 Checking segment from ROM address 0x4010001c
9504 00:45:00.110644 Loading segment from ROM address 0x40100000
9505 00:45:00.111116 code (compression=1)
9506 00:45:00.117443 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9507 00:45:00.127453 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9508 00:45:00.128020 using LZMA
9509 00:45:00.135668 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9510 00:45:00.142255 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9511 00:45:00.145542 Loading segment from ROM address 0x4010001c
9512 00:45:00.146014 Entry Point 0x54601000
9513 00:45:00.149243 Loaded segments
9514 00:45:00.152212 NOTICE: MT8192 bl31_setup
9515 00:45:00.159367 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9516 00:45:00.163165 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9517 00:45:00.166098 WARNING: region 0:
9518 00:45:00.169489 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9519 00:45:00.170057 WARNING: region 1:
9520 00:45:00.176067 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9521 00:45:00.179628 WARNING: region 2:
9522 00:45:00.182798 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9523 00:45:00.185947 WARNING: region 3:
9524 00:45:00.189364 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9525 00:45:00.192996 WARNING: region 4:
9526 00:45:00.199330 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9527 00:45:00.199902 WARNING: region 5:
9528 00:45:00.202545 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9529 00:45:00.206140 WARNING: region 6:
9530 00:45:00.209699 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9531 00:45:00.212678 WARNING: region 7:
9532 00:45:00.216638 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9533 00:45:00.223056 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9534 00:45:00.226370 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9535 00:45:00.229828 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9536 00:45:00.236073 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9537 00:45:00.239514 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9538 00:45:00.242980 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9539 00:45:00.249766 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9540 00:45:00.253197 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9541 00:45:00.256215 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9542 00:45:00.262740 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9543 00:45:00.266025 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9544 00:45:00.272693 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9545 00:45:00.276273 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9546 00:45:00.279752 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9547 00:45:00.285998 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9548 00:45:00.289271 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9549 00:45:00.295938 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9550 00:45:00.299364 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9551 00:45:00.302404 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9552 00:45:00.309562 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9553 00:45:00.312731 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9554 00:45:00.315930 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9555 00:45:00.322809 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9556 00:45:00.325977 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9557 00:45:00.332921 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9558 00:45:00.335893 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9559 00:45:00.339543 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9560 00:45:00.345608 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9561 00:45:00.349433 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9562 00:45:00.355636 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9563 00:45:00.359308 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9564 00:45:00.362264 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9565 00:45:00.368905 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9566 00:45:00.372428 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9567 00:45:00.375668 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9568 00:45:00.379037 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9569 00:45:00.385282 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9570 00:45:00.389085 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9571 00:45:00.392306 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9572 00:45:00.395848 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9573 00:45:00.402488 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9574 00:45:00.405745 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9575 00:45:00.409171 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9576 00:45:00.412473 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9577 00:45:00.418995 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9578 00:45:00.422162 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9579 00:45:00.425837 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9580 00:45:00.429194 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9581 00:45:00.435617 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9582 00:45:00.438831 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9583 00:45:00.445847 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9584 00:45:00.449142 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9585 00:45:00.455323 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9586 00:45:00.458668 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9587 00:45:00.462374 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9588 00:45:00.468806 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9589 00:45:00.471933 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9590 00:45:00.478229 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9591 00:45:00.482053 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9592 00:45:00.488492 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9593 00:45:00.491840 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9594 00:45:00.498225 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9595 00:45:00.501558 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9596 00:45:00.505488 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9597 00:45:00.511497 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9598 00:45:00.515017 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9599 00:45:00.521932 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9600 00:45:00.525296 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9601 00:45:00.532109 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9602 00:45:00.535341 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9603 00:45:00.538681 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9604 00:45:00.545559 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9605 00:45:00.548849 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9606 00:45:00.555497 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9607 00:45:00.558587 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9608 00:45:00.565257 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9609 00:45:00.568508 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9610 00:45:00.571874 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9611 00:45:00.578536 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9612 00:45:00.581711 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9613 00:45:00.588689 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9614 00:45:00.592166 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9615 00:45:00.598277 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9616 00:45:00.601915 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9617 00:45:00.608214 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9618 00:45:00.611741 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9619 00:45:00.615110 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9620 00:45:00.621558 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9621 00:45:00.625054 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9622 00:45:00.631345 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9623 00:45:00.635113 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9624 00:45:00.641453 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9625 00:45:00.645133 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9626 00:45:00.651690 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9627 00:45:00.654989 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9628 00:45:00.658620 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9629 00:45:00.664754 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9630 00:45:00.668012 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9631 00:45:00.670838 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9632 00:45:00.674595 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9633 00:45:00.681417 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9634 00:45:00.684632 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9635 00:45:00.688133 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9636 00:45:00.694598 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9637 00:45:00.698241 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9638 00:45:00.704703 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9639 00:45:00.708055 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9640 00:45:00.711504 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9641 00:45:00.717848 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9642 00:45:00.721028 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9643 00:45:00.728325 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9644 00:45:00.731150 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9645 00:45:00.734304 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9646 00:45:00.741411 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9647 00:45:00.744898 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9648 00:45:00.751550 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9649 00:45:00.754465 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9650 00:45:00.758076 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9651 00:45:00.764574 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9652 00:45:00.768274 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9653 00:45:00.771223 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9654 00:45:00.774328 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9655 00:45:00.777597 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9656 00:45:00.784656 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9657 00:45:00.787612 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9658 00:45:00.794461 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9659 00:45:00.797803 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9660 00:45:00.801038 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9661 00:45:00.807815 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9662 00:45:00.811278 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9663 00:45:00.814177 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9664 00:45:00.821019 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9665 00:45:00.824209 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9666 00:45:00.830714 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9667 00:45:00.834283 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9668 00:45:00.837386 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9669 00:45:00.844203 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9670 00:45:00.847297 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9671 00:45:00.854199 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9672 00:45:00.857495 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9673 00:45:00.861186 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9674 00:45:00.867681 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9675 00:45:00.871075 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9676 00:45:00.877211 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9677 00:45:00.880485 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9678 00:45:00.884156 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9679 00:45:00.891035 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9680 00:45:00.894142 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9681 00:45:00.897313 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9682 00:45:00.904279 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9683 00:45:00.907710 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9684 00:45:00.913814 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9685 00:45:00.917429 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9686 00:45:00.920769 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9687 00:45:00.927489 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9688 00:45:00.930674 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9689 00:45:00.937063 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9690 00:45:00.940656 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9691 00:45:00.944072 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9692 00:45:00.950734 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9693 00:45:00.954157 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9694 00:45:00.960935 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9695 00:45:00.964416 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9696 00:45:00.967264 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9697 00:45:00.974085 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9698 00:45:00.977619 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9699 00:45:00.980761 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9700 00:45:00.987317 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9701 00:45:00.990665 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9702 00:45:00.997383 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9703 00:45:01.000737 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9704 00:45:01.004316 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9705 00:45:01.010342 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9706 00:45:01.013895 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9707 00:45:01.020827 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9708 00:45:01.023841 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9709 00:45:01.027555 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9710 00:45:01.033999 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9711 00:45:01.036948 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9712 00:45:01.040805 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9713 00:45:01.047026 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9714 00:45:01.050760 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9715 00:45:01.057198 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9716 00:45:01.060930 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9717 00:45:01.064362 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9718 00:45:01.070884 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9719 00:45:01.074255 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9720 00:45:01.080521 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9721 00:45:01.083874 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9722 00:45:01.087455 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9723 00:45:01.094061 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9724 00:45:01.097032 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9725 00:45:01.104223 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9726 00:45:01.107327 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9727 00:45:01.110290 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9728 00:45:01.117209 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9729 00:45:01.120663 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9730 00:45:01.127501 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9731 00:45:01.130896 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9732 00:45:01.137374 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9733 00:45:01.140814 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9734 00:45:01.143860 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9735 00:45:01.151071 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9736 00:45:01.154189 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9737 00:45:01.160835 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9738 00:45:01.164249 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9739 00:45:01.167238 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9740 00:45:01.174196 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9741 00:45:01.176986 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9742 00:45:01.183530 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9743 00:45:01.187352 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9744 00:45:01.190743 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9745 00:45:01.196823 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9746 00:45:01.200232 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9747 00:45:01.207113 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9748 00:45:01.210657 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9749 00:45:01.217450 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9750 00:45:01.220318 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9751 00:45:01.223832 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9752 00:45:01.230406 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9753 00:45:01.234003 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9754 00:45:01.240643 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9755 00:45:01.243969 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9756 00:45:01.246830 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9757 00:45:01.254142 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9758 00:45:01.256780 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9759 00:45:01.263983 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9760 00:45:01.266741 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9761 00:45:01.270699 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9762 00:45:01.277278 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9763 00:45:01.280162 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9764 00:45:01.283841 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9765 00:45:01.287138 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9766 00:45:01.294073 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9767 00:45:01.296900 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9768 00:45:01.300146 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9769 00:45:01.306679 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9770 00:45:01.309900 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9771 00:45:01.313505 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9772 00:45:01.320256 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9773 00:45:01.323715 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9774 00:45:01.330355 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9775 00:45:01.333639 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9776 00:45:01.336756 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9777 00:45:01.343398 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9778 00:45:01.346477 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9779 00:45:01.349712 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9780 00:45:01.357262 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9781 00:45:01.360143 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9782 00:45:01.363489 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9783 00:45:01.370172 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9784 00:45:01.373345 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9785 00:45:01.380047 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9786 00:45:01.383156 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9787 00:45:01.386788 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9788 00:45:01.393784 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9789 00:45:01.396875 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9790 00:45:01.399723 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9791 00:45:01.406426 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9792 00:45:01.409852 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9793 00:45:01.413239 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9794 00:45:01.419856 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9795 00:45:01.423520 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9796 00:45:01.426589 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9797 00:45:01.433423 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9798 00:45:01.436383 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9799 00:45:01.443144 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9800 00:45:01.446679 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9801 00:45:01.449867 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9802 00:45:01.453614 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9803 00:45:01.459591 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9804 00:45:01.463166 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9805 00:45:01.466508 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9806 00:45:01.469589 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9807 00:45:01.476656 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9808 00:45:01.479591 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9809 00:45:01.483114 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9810 00:45:01.486581 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9811 00:45:01.492886 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9812 00:45:01.496287 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9813 00:45:01.499897 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9814 00:45:01.506263 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9815 00:45:01.509730 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9816 00:45:01.512465 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9817 00:45:01.519825 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9818 00:45:01.522668 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9819 00:45:01.529335 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9820 00:45:01.532840 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9821 00:45:01.536254 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9822 00:45:01.543052 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9823 00:45:01.546058 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9824 00:45:01.553135 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9825 00:45:01.556252 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9826 00:45:01.559391 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9827 00:45:01.565905 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9828 00:45:01.569267 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9829 00:45:01.576019 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9830 00:45:01.579286 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9831 00:45:01.582297 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9832 00:45:01.589137 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9833 00:45:01.592858 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9834 00:45:01.599597 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9835 00:45:01.602623 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9836 00:45:01.609527 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9837 00:45:01.612301 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9838 00:45:01.616255 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9839 00:45:01.622326 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9840 00:45:01.625713 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9841 00:45:01.631961 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9842 00:45:01.636032 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9843 00:45:01.638846 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9844 00:45:01.645682 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9845 00:45:01.648949 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9846 00:45:01.652182 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9847 00:45:01.658968 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9848 00:45:01.662403 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9849 00:45:01.668967 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9850 00:45:01.672247 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9851 00:45:01.679336 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9852 00:45:01.682207 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9853 00:45:01.685929 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9854 00:45:01.692247 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9855 00:45:01.696047 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9856 00:45:01.702301 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9857 00:45:01.705634 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9858 00:45:01.709114 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9859 00:45:01.715889 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9860 00:45:01.719092 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9861 00:45:01.725874 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9862 00:45:01.729215 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9863 00:45:01.732261 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9864 00:45:01.739051 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9865 00:45:01.742433 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9866 00:45:01.749065 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9867 00:45:01.752388 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9868 00:45:01.758879 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9869 00:45:01.761766 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9870 00:45:01.765031 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9871 00:45:01.772092 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9872 00:45:01.775237 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9873 00:45:01.782070 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9874 00:45:01.785577 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9875 00:45:01.788912 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9876 00:45:01.795403 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9877 00:45:01.798317 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9878 00:45:01.804963 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9879 00:45:01.808446 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9880 00:45:01.811825 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9881 00:45:01.819030 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9882 00:45:01.821615 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9883 00:45:01.828543 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9884 00:45:01.831568 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9885 00:45:01.838409 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9886 00:45:01.841862 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9887 00:45:01.845158 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9888 00:45:01.851845 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9889 00:45:01.855020 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9890 00:45:01.862095 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9891 00:45:01.865415 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9892 00:45:01.868763 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9893 00:45:01.875363 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9894 00:45:01.878274 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9895 00:45:01.885092 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9896 00:45:01.888535 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9897 00:45:01.895236 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9898 00:45:01.898772 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9899 00:45:01.905050 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9900 00:45:01.908370 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9901 00:45:01.911720 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9902 00:45:01.918816 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9903 00:45:01.921651 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9904 00:45:01.928766 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9905 00:45:01.932141 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9906 00:45:01.935312 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9907 00:45:01.942091 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9908 00:45:01.945388 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9909 00:45:01.952034 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9910 00:45:01.955351 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9911 00:45:01.961528 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9912 00:45:01.965445 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9913 00:45:01.968796 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9914 00:45:01.975462 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9915 00:45:01.978361 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9916 00:45:01.985081 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9917 00:45:01.988608 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9918 00:45:01.992150 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9919 00:45:01.998483 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9920 00:45:02.001786 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9921 00:45:02.008514 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9922 00:45:02.011285 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9923 00:45:02.018362 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9924 00:45:02.021595 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9925 00:45:02.028542 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9926 00:45:02.031684 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9927 00:45:02.034800 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9928 00:45:02.041183 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9929 00:45:02.044761 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9930 00:45:02.051032 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9931 00:45:02.054609 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9932 00:45:02.061146 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9933 00:45:02.064941 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9934 00:45:02.068019 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9935 00:45:02.074705 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9936 00:45:02.077881 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9937 00:45:02.084385 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9938 00:45:02.087896 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9939 00:45:02.094622 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9940 00:45:02.097768 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9941 00:45:02.104440 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9942 00:45:02.107868 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9943 00:45:02.114782 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9944 00:45:02.117993 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9945 00:45:02.124487 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9946 00:45:02.127629 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9947 00:45:02.131285 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9948 00:45:02.138275 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9949 00:45:02.141005 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9950 00:45:02.147854 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9951 00:45:02.151587 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9952 00:45:02.157700 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9953 00:45:02.161152 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9954 00:45:02.167945 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9955 00:45:02.171136 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9956 00:45:02.177763 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9957 00:45:02.180931 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9958 00:45:02.187779 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9959 00:45:02.190616 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9960 00:45:02.197459 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9961 00:45:02.201224 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9962 00:45:02.207881 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9963 00:45:02.211277 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9964 00:45:02.217414 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9965 00:45:02.221132 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9966 00:45:02.227887 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9967 00:45:02.231422 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9968 00:45:02.234094 INFO: [APUAPC] vio 0
9969 00:45:02.237842 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9970 00:45:02.244315 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9971 00:45:02.247219 INFO: [APUAPC] D0_APC_0: 0x400510
9972 00:45:02.247681 INFO: [APUAPC] D0_APC_1: 0x0
9973 00:45:02.250852 INFO: [APUAPC] D0_APC_2: 0x1540
9974 00:45:02.254529 INFO: [APUAPC] D0_APC_3: 0x0
9975 00:45:02.257530 INFO: [APUAPC] D1_APC_0: 0xffffffff
9976 00:45:02.260935 INFO: [APUAPC] D1_APC_1: 0xffffffff
9977 00:45:02.264925 INFO: [APUAPC] D1_APC_2: 0x3fffff
9978 00:45:02.267568 INFO: [APUAPC] D1_APC_3: 0x0
9979 00:45:02.271605 INFO: [APUAPC] D2_APC_0: 0xffffffff
9980 00:45:02.274238 INFO: [APUAPC] D2_APC_1: 0xffffffff
9981 00:45:02.277814 INFO: [APUAPC] D2_APC_2: 0x3fffff
9982 00:45:02.281004 INFO: [APUAPC] D2_APC_3: 0x0
9983 00:45:02.284265 INFO: [APUAPC] D3_APC_0: 0xffffffff
9984 00:45:02.287444 INFO: [APUAPC] D3_APC_1: 0xffffffff
9985 00:45:02.290935 INFO: [APUAPC] D3_APC_2: 0x3fffff
9986 00:45:02.294384 INFO: [APUAPC] D3_APC_3: 0x0
9987 00:45:02.297682 INFO: [APUAPC] D4_APC_0: 0xffffffff
9988 00:45:02.301000 INFO: [APUAPC] D4_APC_1: 0xffffffff
9989 00:45:02.304151 INFO: [APUAPC] D4_APC_2: 0x3fffff
9990 00:45:02.307034 INFO: [APUAPC] D4_APC_3: 0x0
9991 00:45:02.310414 INFO: [APUAPC] D5_APC_0: 0xffffffff
9992 00:45:02.313909 INFO: [APUAPC] D5_APC_1: 0xffffffff
9993 00:45:02.316952 INFO: [APUAPC] D5_APC_2: 0x3fffff
9994 00:45:02.320392 INFO: [APUAPC] D5_APC_3: 0x0
9995 00:45:02.324145 INFO: [APUAPC] D6_APC_0: 0xffffffff
9996 00:45:02.327080 INFO: [APUAPC] D6_APC_1: 0xffffffff
9997 00:45:02.330448 INFO: [APUAPC] D6_APC_2: 0x3fffff
9998 00:45:02.333697 INFO: [APUAPC] D6_APC_3: 0x0
9999 00:45:02.337290 INFO: [APUAPC] D7_APC_0: 0xffffffff
10000 00:45:02.340339 INFO: [APUAPC] D7_APC_1: 0xffffffff
10001 00:45:02.343968 INFO: [APUAPC] D7_APC_2: 0x3fffff
10002 00:45:02.347054 INFO: [APUAPC] D7_APC_3: 0x0
10003 00:45:02.350540 INFO: [APUAPC] D8_APC_0: 0xffffffff
10004 00:45:02.353689 INFO: [APUAPC] D8_APC_1: 0xffffffff
10005 00:45:02.357030 INFO: [APUAPC] D8_APC_2: 0x3fffff
10006 00:45:02.360025 INFO: [APUAPC] D8_APC_3: 0x0
10007 00:45:02.363415 INFO: [APUAPC] D9_APC_0: 0xffffffff
10008 00:45:02.367100 INFO: [APUAPC] D9_APC_1: 0xffffffff
10009 00:45:02.370053 INFO: [APUAPC] D9_APC_2: 0x3fffff
10010 00:45:02.373696 INFO: [APUAPC] D9_APC_3: 0x0
10011 00:45:02.376770 INFO: [APUAPC] D10_APC_0: 0xffffffff
10012 00:45:02.380409 INFO: [APUAPC] D10_APC_1: 0xffffffff
10013 00:45:02.383687 INFO: [APUAPC] D10_APC_2: 0x3fffff
10014 00:45:02.386868 INFO: [APUAPC] D10_APC_3: 0x0
10015 00:45:02.390459 INFO: [APUAPC] D11_APC_0: 0xffffffff
10016 00:45:02.393816 INFO: [APUAPC] D11_APC_1: 0xffffffff
10017 00:45:02.397196 INFO: [APUAPC] D11_APC_2: 0x3fffff
10018 00:45:02.400286 INFO: [APUAPC] D11_APC_3: 0x0
10019 00:45:02.403449 INFO: [APUAPC] D12_APC_0: 0xffffffff
10020 00:45:02.406665 INFO: [APUAPC] D12_APC_1: 0xffffffff
10021 00:45:02.410577 INFO: [APUAPC] D12_APC_2: 0x3fffff
10022 00:45:02.413217 INFO: [APUAPC] D12_APC_3: 0x0
10023 00:45:02.416926 INFO: [APUAPC] D13_APC_0: 0xffffffff
10024 00:45:02.420058 INFO: [APUAPC] D13_APC_1: 0xffffffff
10025 00:45:02.423314 INFO: [APUAPC] D13_APC_2: 0x3fffff
10026 00:45:02.426796 INFO: [APUAPC] D13_APC_3: 0x0
10027 00:45:02.430047 INFO: [APUAPC] D14_APC_0: 0xffffffff
10028 00:45:02.433402 INFO: [APUAPC] D14_APC_1: 0xffffffff
10029 00:45:02.437006 INFO: [APUAPC] D14_APC_2: 0x3fffff
10030 00:45:02.439983 INFO: [APUAPC] D14_APC_3: 0x0
10031 00:45:02.443449 INFO: [APUAPC] D15_APC_0: 0xffffffff
10032 00:45:02.446696 INFO: [APUAPC] D15_APC_1: 0xffffffff
10033 00:45:02.449794 INFO: [APUAPC] D15_APC_2: 0x3fffff
10034 00:45:02.453488 INFO: [APUAPC] D15_APC_3: 0x0
10035 00:45:02.454071 INFO: [APUAPC] APC_CON: 0x4
10036 00:45:02.456950 INFO: [NOCDAPC] D0_APC_0: 0x0
10037 00:45:02.459741 INFO: [NOCDAPC] D0_APC_1: 0x0
10038 00:45:02.463499 INFO: [NOCDAPC] D1_APC_0: 0x0
10039 00:45:02.466526 INFO: [NOCDAPC] D1_APC_1: 0xfff
10040 00:45:02.469901 INFO: [NOCDAPC] D2_APC_0: 0x0
10041 00:45:02.473615 INFO: [NOCDAPC] D2_APC_1: 0xfff
10042 00:45:02.476844 INFO: [NOCDAPC] D3_APC_0: 0x0
10043 00:45:02.480715 INFO: [NOCDAPC] D3_APC_1: 0xfff
10044 00:45:02.483737 INFO: [NOCDAPC] D4_APC_0: 0x0
10045 00:45:02.484311 INFO: [NOCDAPC] D4_APC_1: 0xfff
10046 00:45:02.486911 INFO: [NOCDAPC] D5_APC_0: 0x0
10047 00:45:02.489939 INFO: [NOCDAPC] D5_APC_1: 0xfff
10048 00:45:02.494037 INFO: [NOCDAPC] D6_APC_0: 0x0
10049 00:45:02.496928 INFO: [NOCDAPC] D6_APC_1: 0xfff
10050 00:45:02.500259 INFO: [NOCDAPC] D7_APC_0: 0x0
10051 00:45:02.503582 INFO: [NOCDAPC] D7_APC_1: 0xfff
10052 00:45:02.507007 INFO: [NOCDAPC] D8_APC_0: 0x0
10053 00:45:02.510202 INFO: [NOCDAPC] D8_APC_1: 0xfff
10054 00:45:02.513121 INFO: [NOCDAPC] D9_APC_0: 0x0
10055 00:45:02.516816 INFO: [NOCDAPC] D9_APC_1: 0xfff
10056 00:45:02.517284 INFO: [NOCDAPC] D10_APC_0: 0x0
10057 00:45:02.519849 INFO: [NOCDAPC] D10_APC_1: 0xfff
10058 00:45:02.524185 INFO: [NOCDAPC] D11_APC_0: 0x0
10059 00:45:02.526801 INFO: [NOCDAPC] D11_APC_1: 0xfff
10060 00:45:02.530500 INFO: [NOCDAPC] D12_APC_0: 0x0
10061 00:45:02.533233 INFO: [NOCDAPC] D12_APC_1: 0xfff
10062 00:45:02.536835 INFO: [NOCDAPC] D13_APC_0: 0x0
10063 00:45:02.540464 INFO: [NOCDAPC] D13_APC_1: 0xfff
10064 00:45:02.543456 INFO: [NOCDAPC] D14_APC_0: 0x0
10065 00:45:02.546679 INFO: [NOCDAPC] D14_APC_1: 0xfff
10066 00:45:02.549802 INFO: [NOCDAPC] D15_APC_0: 0x0
10067 00:45:02.553514 INFO: [NOCDAPC] D15_APC_1: 0xfff
10068 00:45:02.556809 INFO: [NOCDAPC] APC_CON: 0x4
10069 00:45:02.560066 INFO: [APUAPC] set_apusys_apc done
10070 00:45:02.563128 INFO: [DEVAPC] devapc_init done
10071 00:45:02.566520 INFO: GICv3 without legacy support detected.
10072 00:45:02.570003 INFO: ARM GICv3 driver initialized in EL3
10073 00:45:02.573080 INFO: Maximum SPI INTID supported: 639
10074 00:45:02.577170 INFO: BL31: Initializing runtime services
10075 00:45:02.583689 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10076 00:45:02.586979 INFO: SPM: enable CPC mode
10077 00:45:02.589935 INFO: mcdi ready for mcusys-off-idle and system suspend
10078 00:45:02.596440 INFO: BL31: Preparing for EL3 exit to normal world
10079 00:45:02.600050 INFO: Entry point address = 0x80000000
10080 00:45:02.603090 INFO: SPSR = 0x8
10081 00:45:02.607846
10082 00:45:02.608419
10083 00:45:02.608840
10084 00:45:02.610389 Starting depthcharge on Spherion...
10085 00:45:02.610859
10086 00:45:02.611232 Wipe memory regions:
10087 00:45:02.611579
10088 00:45:02.613931 end: 2.2.3 depthcharge-start (duration 00:00:19) [common]
10089 00:45:02.614498 start: 2.2.4 bootloader-commands (timeout 00:04:27) [common]
10090 00:45:02.614970 Setting prompt string to ['asurada:']
10091 00:45:02.615413 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:27)
10092 00:45:02.616137 [0x00000040000000, 0x00000054600000)
10093 00:45:02.736393
10094 00:45:02.737004 [0x00000054660000, 0x00000080000000)
10095 00:45:02.996811
10096 00:45:02.997381 [0x000000821a7280, 0x000000ffe64000)
10097 00:45:03.741633
10098 00:45:03.742210 [0x00000100000000, 0x00000240000000)
10099 00:45:05.632144
10100 00:45:05.635064 Initializing XHCI USB controller at 0x11200000.
10101 00:45:06.674888
10102 00:45:06.677919 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10103 00:45:06.678488
10104 00:45:06.678863
10105 00:45:06.679702 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10107 00:45:06.780913 asurada: tftpboot 192.168.201.1 14368392/tftp-deploy-ut6dle8v/kernel/image.itb 14368392/tftp-deploy-ut6dle8v/kernel/cmdline
10108 00:45:06.781573 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10109 00:45:06.782130 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:23)
10110 00:45:06.786776 tftpboot 192.168.201.1 14368392/tftp-deploy-ut6dle8v/kernel/image.itp-deploy-ut6dle8v/kernel/cmdline
10111 00:45:06.787253
10112 00:45:06.787621 Waiting for link
10113 00:45:06.944865
10114 00:45:06.945435 R8152: Initializing
10115 00:45:06.945811
10116 00:45:06.948074 Version 9 (ocp_data = 6010)
10117 00:45:06.948684
10118 00:45:06.951015 R8152: Done initializing
10119 00:45:06.951585
10120 00:45:06.951953 Adding net device
10121 00:45:08.822687
10122 00:45:08.823307 done.
10123 00:45:08.824090
10124 00:45:08.824901 MAC: 00:e0:4c:72:2d:d6
10125 00:45:08.825548
10126 00:45:08.826428 Sending DHCP discover... done.
10127 00:45:08.826822
10128 00:45:08.829078 Waiting for reply... done.
10129 00:45:08.829587
10130 00:45:08.832624 Sending DHCP request... done.
10131 00:45:08.833090
10132 00:45:08.833460 Waiting for reply... done.
10133 00:45:08.833803
10134 00:45:08.836041 My ip is 192.168.201.21
10135 00:45:08.836667
10136 00:45:08.839212 The DHCP server ip is 192.168.201.1
10137 00:45:08.839800
10138 00:45:08.842455 TFTP server IP predefined by user: 192.168.201.1
10139 00:45:08.842924
10140 00:45:08.849060 Bootfile predefined by user: 14368392/tftp-deploy-ut6dle8v/kernel/image.itb
10141 00:45:08.849550
10142 00:45:08.852415 Sending tftp read request... done.
10143 00:45:08.853004
10144 00:45:08.858916 Waiting for the transfer...
10145 00:45:08.859480
10146 00:45:09.126964 00000000 ################################################################
10147 00:45:09.127086
10148 00:45:09.404815 00080000 ################################################################
10149 00:45:09.404974
10150 00:45:09.682025 00100000 ################################################################
10151 00:45:09.682153
10152 00:45:09.960109 00180000 ################################################################
10153 00:45:09.960234
10154 00:45:10.220153 00200000 ################################################################
10155 00:45:10.220290
10156 00:45:10.505439 00280000 ################################################################
10157 00:45:10.505587
10158 00:45:10.789270 00300000 ################################################################
10159 00:45:10.789398
10160 00:45:11.064724 00380000 ################################################################
10161 00:45:11.064860
10162 00:45:11.323514 00400000 ################################################################
10163 00:45:11.323659
10164 00:45:11.599162 00480000 ################################################################
10165 00:45:11.599297
10166 00:45:11.894998 00500000 ################################################################
10167 00:45:11.895132
10168 00:45:12.179352 00580000 ################################################################
10169 00:45:12.179484
10170 00:45:12.447374 00600000 ################################################################
10171 00:45:12.447510
10172 00:45:12.697992 00680000 ################################################################
10173 00:45:12.698109
10174 00:45:12.956220 00700000 ################################################################
10175 00:45:12.956373
10176 00:45:13.213676 00780000 ################################################################
10177 00:45:13.213795
10178 00:45:13.494066 00800000 ################################################################
10179 00:45:13.494215
10180 00:45:13.791956 00880000 ################################################################
10181 00:45:13.792088
10182 00:45:14.075066 00900000 ################################################################
10183 00:45:14.075191
10184 00:45:14.370724 00980000 ################################################################
10185 00:45:14.370863
10186 00:45:14.648405 00a00000 ################################################################
10187 00:45:14.648539
10188 00:45:14.942534 00a80000 ################################################################
10189 00:45:14.942664
10190 00:45:15.223716 00b00000 ################################################################
10191 00:45:15.223837
10192 00:45:15.500948 00b80000 ################################################################
10193 00:45:15.501086
10194 00:45:15.749819 00c00000 ################################################################
10195 00:45:15.749982
10196 00:45:16.037756 00c80000 ################################################################
10197 00:45:16.037934
10198 00:45:16.335068 00d00000 ################################################################
10199 00:45:16.335224
10200 00:45:16.622255 00d80000 ################################################################
10201 00:45:16.622417
10202 00:45:16.911905 00e00000 ################################################################
10203 00:45:16.912059
10204 00:45:17.208783 00e80000 ################################################################
10205 00:45:17.208934
10206 00:45:17.504079 00f00000 ################################################################
10207 00:45:17.504264
10208 00:45:17.753359 00f80000 ################################################################
10209 00:45:17.753515
10210 00:45:18.002352 01000000 ################################################################
10211 00:45:18.002477
10212 00:45:18.294238 01080000 ################################################################
10213 00:45:18.294361
10214 00:45:18.582614 01100000 ################################################################
10215 00:45:18.582753
10216 00:45:18.831356 01180000 ################################################################
10217 00:45:18.831478
10218 00:45:19.081010 01200000 ################################################################
10219 00:45:19.081130
10220 00:45:19.330252 01280000 ################################################################
10221 00:45:19.330372
10222 00:45:19.604398 01300000 ################################################################
10223 00:45:19.604528
10224 00:45:19.883558 01380000 ################################################################
10225 00:45:19.883690
10226 00:45:20.172943 01400000 ################################################################
10227 00:45:20.173063
10228 00:45:20.470207 01480000 ################################################################
10229 00:45:20.470333
10230 00:45:20.734069 01500000 ################################################################
10231 00:45:20.734204
10232 00:45:20.983064 01580000 ################################################################
10233 00:45:20.983186
10234 00:45:21.237912 01600000 ################################################################
10235 00:45:21.238029
10236 00:45:21.513104 01680000 ################################################################
10237 00:45:21.513249
10238 00:45:21.792230 01700000 ################################################################
10239 00:45:21.792365
10240 00:45:22.048842 01780000 ################################################################
10241 00:45:22.048966
10242 00:45:22.327662 01800000 ################################################################
10243 00:45:22.327786
10244 00:45:22.620224 01880000 ################################################################
10245 00:45:22.620348
10246 00:45:22.905499 01900000 ################################################################
10247 00:45:22.905640
10248 00:45:23.195001 01980000 ################################################################
10249 00:45:23.195126
10250 00:45:23.486357 01a00000 ################################################################
10251 00:45:23.486481
10252 00:45:23.766784 01a80000 ################################################################
10253 00:45:23.766909
10254 00:45:24.023949 01b00000 ################################################################
10255 00:45:24.024081
10256 00:45:24.304056 01b80000 ################################################################
10257 00:45:24.304181
10258 00:45:24.592984 01c00000 ################################################################
10259 00:45:24.593110
10260 00:45:24.872594 01c80000 ################################################################
10261 00:45:24.872721
10262 00:45:25.159819 01d00000 ################################################################
10263 00:45:25.159956
10264 00:45:25.457810 01d80000 ################################################################
10265 00:45:25.457940
10266 00:45:25.718393 01e00000 ######################################################## done.
10267 00:45:25.718526
10268 00:45:25.721737 The bootfile was 31915298 bytes long.
10269 00:45:25.721828
10270 00:45:25.724637 Sending tftp read request... done.
10271 00:45:25.724733
10272 00:45:25.724841 Waiting for the transfer...
10273 00:45:25.724951
10274 00:45:25.727958 00000000 # done.
10275 00:45:25.728060
10276 00:45:25.734925 Command line loaded dynamically from TFTP file: 14368392/tftp-deploy-ut6dle8v/kernel/cmdline
10277 00:45:25.735113
10278 00:45:25.757917 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14368392/extract-nfsrootfs-_yqx9ly3,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10279 00:45:25.758218
10280 00:45:25.758385 Loading FIT.
10281 00:45:25.758535
10282 00:45:25.761124 Image ramdisk-1 has 18739632 bytes.
10283 00:45:25.761423
10284 00:45:25.764755 Image fdt-1 has 47258 bytes.
10285 00:45:25.764989
10286 00:45:25.767772 Image kernel-1 has 13126376 bytes.
10287 00:45:25.768269
10288 00:45:25.778127 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10289 00:45:25.778709
10290 00:45:25.794151 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10291 00:45:25.794761
10292 00:45:25.800759 Choosing best match conf-1 for compat google,spherion-rev2.
10293 00:45:25.804258
10294 00:45:25.809050 Connected to device vid:did:rid of 1ae0:0028:00
10295 00:45:25.817375
10296 00:45:25.820694 tpm_get_response: command 0x17b, return code 0x0
10297 00:45:25.821263
10298 00:45:25.823642 ec_init: CrosEC protocol v3 supported (256, 248)
10299 00:45:25.829221
10300 00:45:25.832247 tpm_cleanup: add release locality here.
10301 00:45:25.832754
10302 00:45:25.833135 Shutting down all USB controllers.
10303 00:45:25.836343
10304 00:45:25.836958 Removing current net device
10305 00:45:25.837340
10306 00:45:25.842600 Exiting depthcharge with code 4 at timestamp: 52541317
10307 00:45:25.843076
10308 00:45:25.845993 LZMA decompressing kernel-1 to 0x821a6718
10309 00:45:25.846564
10310 00:45:25.848835 LZMA decompressing kernel-1 to 0x40000000
10311 00:45:27.466145
10312 00:45:27.466866 jumping to kernel
10313 00:45:27.469427 end: 2.2.4 bootloader-commands (duration 00:00:25) [common]
10314 00:45:27.469952 start: 2.2.5 auto-login-action (timeout 00:04:02) [common]
10315 00:45:27.470372 Setting prompt string to ['Linux version [0-9]']
10316 00:45:27.470746 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10317 00:45:27.471120 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10318 00:45:27.549122
10319 00:45:27.552514 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10320 00:45:27.556743 start: 2.2.5.1 login-action (timeout 00:04:02) [common]
10321 00:45:27.557361 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10322 00:45:27.557793 Setting prompt string to []
10323 00:45:27.558312 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10324 00:45:27.558756 Using line separator: #'\n'#
10325 00:45:27.559132 No login prompt set.
10326 00:45:27.559498 Parsing kernel messages
10327 00:45:27.559823 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10328 00:45:27.560798 [login-action] Waiting for messages, (timeout 00:04:02)
10329 00:45:27.561222 Waiting using forced prompt support (timeout 00:02:01)
10330 00:45:27.576040 [ 0.000000] Linux version 6.1.92-cip22 (KernelCI@build-j232175-arm64-gcc-10-defconfig-arm64-chromebook-7lg8d) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sun Jun 16 00:28:47 UTC 2024
10331 00:45:27.579159 [ 0.000000] random: crng init done
10332 00:45:27.585466 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10333 00:45:27.588842 [ 0.000000] efi: UEFI not found.
10334 00:45:27.595107 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10335 00:45:27.605147 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10336 00:45:27.611697 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10337 00:45:27.621412 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10338 00:45:27.628399 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10339 00:45:27.634896 [ 0.000000] printk: bootconsole [mtk8250] enabled
10340 00:45:27.641785 [ 0.000000] NUMA: No NUMA configuration found
10341 00:45:27.648044 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10342 00:45:27.651489 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10343 00:45:27.654903 [ 0.000000] Zone ranges:
10344 00:45:27.661677 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10345 00:45:27.664728 [ 0.000000] DMA32 empty
10346 00:45:27.671462 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10347 00:45:27.674553 [ 0.000000] Movable zone start for each node
10348 00:45:27.678502 [ 0.000000] Early memory node ranges
10349 00:45:27.685052 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10350 00:45:27.691053 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10351 00:45:27.698197 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10352 00:45:27.704443 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10353 00:45:27.710861 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10354 00:45:27.717755 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10355 00:45:27.773997 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10356 00:45:27.780381 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10357 00:45:27.787093 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10358 00:45:27.790325 [ 0.000000] psci: probing for conduit method from DT.
10359 00:45:27.797410 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10360 00:45:27.800492 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10361 00:45:27.806908 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10362 00:45:27.810401 [ 0.000000] psci: SMC Calling Convention v1.2
10363 00:45:27.816977 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10364 00:45:27.820236 [ 0.000000] Detected VIPT I-cache on CPU0
10365 00:45:27.827215 [ 0.000000] CPU features: detected: GIC system register CPU interface
10366 00:45:27.833464 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10367 00:45:27.840227 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10368 00:45:27.846749 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10369 00:45:27.853395 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10370 00:45:27.862943 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10371 00:45:27.866665 [ 0.000000] alternatives: applying boot alternatives
10372 00:45:27.873043 [ 0.000000] Fallback order for Node 0: 0
10373 00:45:27.879525 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10374 00:45:27.883039 [ 0.000000] Policy zone: Normal
10375 00:45:27.906192 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14368392/extract-nfsrootfs-_yqx9ly3,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10376 00:45:27.916020 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10377 00:45:27.926788 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10378 00:45:27.936894 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10379 00:45:27.943471 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10380 00:45:27.946854 <6>[ 0.000000] software IO TLB: area num 8.
10381 00:45:28.004253 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10382 00:45:28.153852 <6>[ 0.000000] Memory: 7945760K/8385536K available (18112K kernel code, 4120K rwdata, 22644K rodata, 8512K init, 616K bss, 407008K reserved, 32768K cma-reserved)
10383 00:45:28.160734 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10384 00:45:28.167282 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10385 00:45:28.170692 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10386 00:45:28.177157 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10387 00:45:28.183962 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10388 00:45:28.186759 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10389 00:45:28.196719 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10390 00:45:28.203805 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10391 00:45:28.209853 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10392 00:45:28.216948 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10393 00:45:28.220156 <6>[ 0.000000] GICv3: 608 SPIs implemented
10394 00:45:28.223326 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10395 00:45:28.229794 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10396 00:45:28.233397 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10397 00:45:28.239411 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10398 00:45:28.253231 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10399 00:45:28.262793 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10400 00:45:28.272650 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10401 00:45:28.280077 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10402 00:45:28.292975 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10403 00:45:28.299988 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10404 00:45:28.306779 <6>[ 0.009180] Console: colour dummy device 80x25
10405 00:45:28.316513 <6>[ 0.013918] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10406 00:45:28.323309 <6>[ 0.024360] pid_max: default: 32768 minimum: 301
10407 00:45:28.326612 <6>[ 0.029232] LSM: Security Framework initializing
10408 00:45:28.333121 <6>[ 0.034201] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10409 00:45:28.342771 <6>[ 0.042015] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10410 00:45:28.352784 <6>[ 0.051487] cblist_init_generic: Setting adjustable number of callback queues.
10411 00:45:28.356114 <6>[ 0.058931] cblist_init_generic: Setting shift to 3 and lim to 1.
10412 00:45:28.365851 <6>[ 0.065270] cblist_init_generic: Setting adjustable number of callback queues.
10413 00:45:28.372740 <6>[ 0.072696] cblist_init_generic: Setting shift to 3 and lim to 1.
10414 00:45:28.376214 <6>[ 0.079101] rcu: Hierarchical SRCU implementation.
10415 00:45:28.382687 <6>[ 0.084147] rcu: Max phase no-delay instances is 1000.
10416 00:45:28.388823 <6>[ 0.091182] EFI services will not be available.
10417 00:45:28.392275 <6>[ 0.096134] smp: Bringing up secondary CPUs ...
10418 00:45:28.400872 <6>[ 0.101185] Detected VIPT I-cache on CPU1
10419 00:45:28.407561 <6>[ 0.101259] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10420 00:45:28.414115 <6>[ 0.101290] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10421 00:45:28.416947 <6>[ 0.101627] Detected VIPT I-cache on CPU2
10422 00:45:28.427153 <6>[ 0.101680] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10423 00:45:28.433522 <6>[ 0.101699] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10424 00:45:28.437110 <6>[ 0.101958] Detected VIPT I-cache on CPU3
10425 00:45:28.443942 <6>[ 0.102006] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10426 00:45:28.449961 <6>[ 0.102020] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10427 00:45:28.457213 <6>[ 0.102327] CPU features: detected: Spectre-v4
10428 00:45:28.460179 <6>[ 0.102333] CPU features: detected: Spectre-BHB
10429 00:45:28.463736 <6>[ 0.102338] Detected PIPT I-cache on CPU4
10430 00:45:28.470235 <6>[ 0.102396] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10431 00:45:28.476936 <6>[ 0.102412] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10432 00:45:28.483956 <6>[ 0.102705] Detected PIPT I-cache on CPU5
10433 00:45:28.489950 <6>[ 0.102768] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10434 00:45:28.496782 <6>[ 0.102784] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10435 00:45:28.500173 <6>[ 0.103064] Detected PIPT I-cache on CPU6
10436 00:45:28.506936 <6>[ 0.103131] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10437 00:45:28.513266 <6>[ 0.103147] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10438 00:45:28.519942 <6>[ 0.103445] Detected PIPT I-cache on CPU7
10439 00:45:28.526531 <6>[ 0.103510] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10440 00:45:28.533132 <6>[ 0.103526] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10441 00:45:28.536376 <6>[ 0.103573] smp: Brought up 1 node, 8 CPUs
10442 00:45:28.543150 <6>[ 0.245016] SMP: Total of 8 processors activated.
10443 00:45:28.545823 <6>[ 0.249938] CPU features: detected: 32-bit EL0 Support
10444 00:45:28.556497 <6>[ 0.255334] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10445 00:45:28.562920 <6>[ 0.264190] CPU features: detected: Common not Private translations
10446 00:45:28.569268 <6>[ 0.270665] CPU features: detected: CRC32 instructions
10447 00:45:28.576032 <6>[ 0.276017] CPU features: detected: RCpc load-acquire (LDAPR)
10448 00:45:28.579579 <6>[ 0.282014] CPU features: detected: LSE atomic instructions
10449 00:45:28.585763 <6>[ 0.287796] CPU features: detected: Privileged Access Never
10450 00:45:28.592476 <6>[ 0.293611] CPU features: detected: RAS Extension Support
10451 00:45:28.599226 <6>[ 0.299254] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10452 00:45:28.602459 <6>[ 0.306473] CPU: All CPU(s) started at EL2
10453 00:45:28.609059 <6>[ 0.310790] alternatives: applying system-wide alternatives
10454 00:45:28.619047 <6>[ 0.321644] devtmpfs: initialized
10455 00:45:28.634318 <6>[ 0.330493] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10456 00:45:28.641048 <6>[ 0.340455] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10457 00:45:28.647679 <6>[ 0.348462] pinctrl core: initialized pinctrl subsystem
10458 00:45:28.651000 <6>[ 0.355157] DMI not present or invalid.
10459 00:45:28.657688 <6>[ 0.359566] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10460 00:45:28.667512 <6>[ 0.366352] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10461 00:45:28.673719 <6>[ 0.373939] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10462 00:45:28.684142 <6>[ 0.382160] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10463 00:45:28.687010 <6>[ 0.390403] audit: initializing netlink subsys (disabled)
10464 00:45:28.696931 <5>[ 0.396094] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10465 00:45:28.703445 <6>[ 0.396824] thermal_sys: Registered thermal governor 'step_wise'
10466 00:45:28.710259 <6>[ 0.404059] thermal_sys: Registered thermal governor 'power_allocator'
10467 00:45:28.713498 <6>[ 0.410314] cpuidle: using governor menu
10468 00:45:28.720064 <6>[ 0.421275] NET: Registered PF_QIPCRTR protocol family
10469 00:45:28.726739 <6>[ 0.426758] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10470 00:45:28.733142 <6>[ 0.433860] ASID allocator initialised with 32768 entries
10471 00:45:28.736305 <6>[ 0.440442] Serial: AMBA PL011 UART driver
10472 00:45:28.746667 <4>[ 0.449271] Trying to register duplicate clock ID: 134
10473 00:45:28.805148 <6>[ 0.510814] KASLR enabled
10474 00:45:28.819623 <6>[ 0.518515] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10475 00:45:28.825863 <6>[ 0.525531] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10476 00:45:28.832383 <6>[ 0.532023] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10477 00:45:28.839533 <6>[ 0.539028] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10478 00:45:28.845501 <6>[ 0.545514] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10479 00:45:28.851925 <6>[ 0.552516] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10480 00:45:28.859116 <6>[ 0.558999] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10481 00:45:28.865156 <6>[ 0.566004] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10482 00:45:28.868604 <6>[ 0.573512] ACPI: Interpreter disabled.
10483 00:45:28.877072 <6>[ 0.579944] iommu: Default domain type: Translated
10484 00:45:28.883908 <6>[ 0.585054] iommu: DMA domain TLB invalidation policy: strict mode
10485 00:45:28.887070 <5>[ 0.591713] SCSI subsystem initialized
10486 00:45:28.893710 <6>[ 0.595876] usbcore: registered new interface driver usbfs
10487 00:45:28.900362 <6>[ 0.601609] usbcore: registered new interface driver hub
10488 00:45:28.903820 <6>[ 0.607164] usbcore: registered new device driver usb
10489 00:45:28.910807 <6>[ 0.613265] pps_core: LinuxPPS API ver. 1 registered
10490 00:45:28.920654 <6>[ 0.618461] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10491 00:45:28.924033 <6>[ 0.627808] PTP clock support registered
10492 00:45:28.927034 <6>[ 0.632050] EDAC MC: Ver: 3.0.0
10493 00:45:28.934676 <6>[ 0.637209] FPGA manager framework
10494 00:45:28.941641 <6>[ 0.640894] Advanced Linux Sound Architecture Driver Initialized.
10495 00:45:28.944512 <6>[ 0.647672] vgaarb: loaded
10496 00:45:28.947980 <6>[ 0.650827] clocksource: Switched to clocksource arch_sys_counter
10497 00:45:28.954887 <5>[ 0.657266] VFS: Disk quotas dquot_6.6.0
10498 00:45:28.961124 <6>[ 0.661452] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10499 00:45:28.964608 <6>[ 0.668642] pnp: PnP ACPI: disabled
10500 00:45:28.972980 <6>[ 0.675391] NET: Registered PF_INET protocol family
10501 00:45:28.982561 <6>[ 0.680983] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10502 00:45:28.993577 <6>[ 0.693301] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10503 00:45:29.003471 <6>[ 0.702114] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10504 00:45:29.010955 <6>[ 0.710087] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10505 00:45:29.016986 <6>[ 0.718788] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10506 00:45:29.029248 <6>[ 0.728542] TCP: Hash tables configured (established 65536 bind 65536)
10507 00:45:29.036044 <6>[ 0.735405] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10508 00:45:29.042534 <6>[ 0.742603] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10509 00:45:29.049124 <6>[ 0.750307] NET: Registered PF_UNIX/PF_LOCAL protocol family
10510 00:45:29.055683 <6>[ 0.756464] RPC: Registered named UNIX socket transport module.
10511 00:45:29.058966 <6>[ 0.762619] RPC: Registered udp transport module.
10512 00:45:29.065239 <6>[ 0.767553] RPC: Registered tcp transport module.
10513 00:45:29.072166 <6>[ 0.772485] RPC: Registered tcp NFSv4.1 backchannel transport module.
10514 00:45:29.075683 <6>[ 0.779150] PCI: CLS 0 bytes, default 64
10515 00:45:29.078840 <6>[ 0.783491] Unpacking initramfs...
10516 00:45:29.103370 <6>[ 0.802925] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10517 00:45:29.113289 <6>[ 0.811576] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10518 00:45:29.116845 <6>[ 0.820422] kvm [1]: IPA Size Limit: 40 bits
10519 00:45:29.123560 <6>[ 0.824956] kvm [1]: GICv3: no GICV resource entry
10520 00:45:29.126865 <6>[ 0.829978] kvm [1]: disabling GICv2 emulation
10521 00:45:29.133173 <6>[ 0.834669] kvm [1]: GIC system register CPU interface enabled
10522 00:45:29.136413 <6>[ 0.840826] kvm [1]: vgic interrupt IRQ18
10523 00:45:29.143504 <6>[ 0.845178] kvm [1]: VHE mode initialized successfully
10524 00:45:29.149770 <5>[ 0.851626] Initialise system trusted keyrings
10525 00:45:29.156674 <6>[ 0.856462] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10526 00:45:29.163341 <6>[ 0.866405] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10527 00:45:29.170096 <5>[ 0.872790] NFS: Registering the id_resolver key type
10528 00:45:29.173442 <5>[ 0.878092] Key type id_resolver registered
10529 00:45:29.180265 <5>[ 0.882507] Key type id_legacy registered
10530 00:45:29.187073 <6>[ 0.886783] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10531 00:45:29.193518 <6>[ 0.893706] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10532 00:45:29.199541 <6>[ 0.901419] 9p: Installing v9fs 9p2000 file system support
10533 00:45:29.235766 <5>[ 0.938549] Key type asymmetric registered
10534 00:45:29.239398 <5>[ 0.942878] Asymmetric key parser 'x509' registered
10535 00:45:29.249451 <6>[ 0.948023] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10536 00:45:29.252083 <6>[ 0.955642] io scheduler mq-deadline registered
10537 00:45:29.255982 <6>[ 0.960434] io scheduler kyber registered
10538 00:45:29.274313 <6>[ 0.977340] EINJ: ACPI disabled.
10539 00:45:29.307086 <4>[ 1.003019] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10540 00:45:29.316995 <4>[ 1.013639] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10541 00:45:29.332613 <6>[ 1.035106] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10542 00:45:29.340915 <6>[ 1.043302] printk: console [ttyS0] disabled
10543 00:45:29.368840 <6>[ 1.067934] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10544 00:45:29.375274 <6>[ 1.077413] printk: console [ttyS0] enabled
10545 00:45:29.378367 <6>[ 1.077413] printk: console [ttyS0] enabled
10546 00:45:29.384975 <6>[ 1.086307] printk: bootconsole [mtk8250] disabled
10547 00:45:29.388354 <6>[ 1.086307] printk: bootconsole [mtk8250] disabled
10548 00:45:29.395512 <6>[ 1.097534] SuperH (H)SCI(F) driver initialized
10549 00:45:29.398253 <6>[ 1.102819] msm_serial: driver initialized
10550 00:45:29.412459 <6>[ 1.111753] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10551 00:45:29.422625 <6>[ 1.120298] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10552 00:45:29.429041 <6>[ 1.128841] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10553 00:45:29.439581 <6>[ 1.137468] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10554 00:45:29.445275 <6>[ 1.146174] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10555 00:45:29.455887 <6>[ 1.154895] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10556 00:45:29.465240 <6>[ 1.163437] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10557 00:45:29.472007 <6>[ 1.172242] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10558 00:45:29.481942 <6>[ 1.180787] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10559 00:45:29.493450 <6>[ 1.196369] loop: module loaded
10560 00:45:29.500150 <6>[ 1.202343] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10561 00:45:29.523356 <4>[ 1.225716] mtk-pmic-keys: Failed to locate of_node [id: -1]
10562 00:45:29.530192 <6>[ 1.232621] megasas: 07.719.03.00-rc1
10563 00:45:29.540094 <6>[ 1.242277] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10564 00:45:29.547667 <6>[ 1.250213] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10565 00:45:29.564660 <6>[ 1.266986] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10566 00:45:29.621184 <6>[ 1.317150] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10567 00:45:29.870581 <6>[ 1.573507] Freeing initrd memory: 18296K
10568 00:45:29.882749 <6>[ 1.585288] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10569 00:45:29.893650 <6>[ 1.596167] tun: Universal TUN/TAP device driver, 1.6
10570 00:45:29.896928 <6>[ 1.602218] thunder_xcv, ver 1.0
10571 00:45:29.900109 <6>[ 1.605722] thunder_bgx, ver 1.0
10572 00:45:29.903546 <6>[ 1.609223] nicpf, ver 1.0
10573 00:45:29.913939 <6>[ 1.613225] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10574 00:45:29.917002 <6>[ 1.620701] hns3: Copyright (c) 2017 Huawei Corporation.
10575 00:45:29.920432 <6>[ 1.626289] hclge is initializing
10576 00:45:29.927213 <6>[ 1.629870] e1000: Intel(R) PRO/1000 Network Driver
10577 00:45:29.933742 <6>[ 1.634999] e1000: Copyright (c) 1999-2006 Intel Corporation.
10578 00:45:29.936959 <6>[ 1.641015] e1000e: Intel(R) PRO/1000 Network Driver
10579 00:45:29.944114 <6>[ 1.646231] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10580 00:45:29.950694 <6>[ 1.652417] igb: Intel(R) Gigabit Ethernet Network Driver
10581 00:45:29.957465 <6>[ 1.658066] igb: Copyright (c) 2007-2014 Intel Corporation.
10582 00:45:29.964174 <6>[ 1.663903] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10583 00:45:29.970582 <6>[ 1.670421] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10584 00:45:29.973464 <6>[ 1.676884] sky2: driver version 1.30
10585 00:45:29.980059 <6>[ 1.681809] usbcore: registered new device driver r8152-cfgselector
10586 00:45:29.986988 <6>[ 1.688347] usbcore: registered new interface driver r8152
10587 00:45:29.990203 <6>[ 1.694158] VFIO - User Level meta-driver version: 0.3
10588 00:45:29.999652 <6>[ 1.702360] usbcore: registered new interface driver usb-storage
10589 00:45:30.006275 <6>[ 1.708807] usbcore: registered new device driver onboard-usb-hub
10590 00:45:30.015192 <6>[ 1.717914] mt6397-rtc mt6359-rtc: registered as rtc0
10591 00:45:30.025413 <6>[ 1.723380] mt6397-rtc mt6359-rtc: setting system clock to 2024-06-16T00:44:04 UTC (1718498644)
10592 00:45:30.028391 <6>[ 1.732938] i2c_dev: i2c /dev entries driver
10593 00:45:30.042069 <4>[ 1.744926] cpu cpu0: supply cpu not found, using dummy regulator
10594 00:45:30.048747 <4>[ 1.751353] cpu cpu1: supply cpu not found, using dummy regulator
10595 00:45:30.055292 <4>[ 1.757760] cpu cpu2: supply cpu not found, using dummy regulator
10596 00:45:30.062281 <4>[ 1.764162] cpu cpu3: supply cpu not found, using dummy regulator
10597 00:45:30.068785 <4>[ 1.770561] cpu cpu4: supply cpu not found, using dummy regulator
10598 00:45:30.075595 <4>[ 1.776974] cpu cpu5: supply cpu not found, using dummy regulator
10599 00:45:30.082257 <4>[ 1.783368] cpu cpu6: supply cpu not found, using dummy regulator
10600 00:45:30.089079 <4>[ 1.789764] cpu cpu7: supply cpu not found, using dummy regulator
10601 00:45:30.107875 <6>[ 1.810395] cpu cpu0: EM: created perf domain
10602 00:45:30.111187 <6>[ 1.815366] cpu cpu4: EM: created perf domain
10603 00:45:30.118397 <6>[ 1.820941] sdhci: Secure Digital Host Controller Interface driver
10604 00:45:30.124934 <6>[ 1.827373] sdhci: Copyright(c) Pierre Ossman
10605 00:45:30.131549 <6>[ 1.832316] Synopsys Designware Multimedia Card Interface Driver
10606 00:45:30.137948 <6>[ 1.838966] sdhci-pltfm: SDHCI platform and OF driver helper
10607 00:45:30.141467 <6>[ 1.839040] mmc0: CQHCI version 5.10
10608 00:45:30.148257 <6>[ 1.848992] ledtrig-cpu: registered to indicate activity on CPUs
10609 00:45:30.154594 <6>[ 1.856075] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10610 00:45:30.161320 <6>[ 1.863125] usbcore: registered new interface driver usbhid
10611 00:45:30.164492 <6>[ 1.868947] usbhid: USB HID core driver
10612 00:45:30.171226 <6>[ 1.873151] spi_master spi0: will run message pump with realtime priority
10613 00:45:30.217229 <6>[ 1.913745] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10614 00:45:30.232979 <6>[ 1.928755] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10615 00:45:30.239252 <6>[ 1.940319] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x16c14
10616 00:45:30.247794 <6>[ 1.950353] cros-ec-spi spi0.0: Chrome EC device registered
10617 00:45:30.254679 <6>[ 1.956338] mmc0: Command Queue Engine enabled
10618 00:45:30.260929 <6>[ 1.961066] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10619 00:45:30.264322 <6>[ 1.968611] mmcblk0: mmc0:0001 DA4128 116 GiB
10620 00:45:30.274539 <6>[ 1.977641] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10621 00:45:30.282494 <6>[ 1.985288] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10622 00:45:30.292487 <6>[ 1.988824] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10623 00:45:30.295727 <6>[ 1.991189] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10624 00:45:30.302926 <6>[ 2.001116] NET: Registered PF_PACKET protocol family
10625 00:45:30.308926 <6>[ 2.005669] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10626 00:45:30.312732 <6>[ 2.010414] 9pnet: Installing 9P2000 support
10627 00:45:30.319151 <5>[ 2.021424] Key type dns_resolver registered
10628 00:45:30.322855 <6>[ 2.026447] registered taskstats version 1
10629 00:45:30.329407 <5>[ 2.030832] Loading compiled-in X.509 certificates
10630 00:45:30.357677 <4>[ 2.054200] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10631 00:45:30.367760 <4>[ 2.064969] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10632 00:45:30.382864 <6>[ 2.085819] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10633 00:45:30.389769 <6>[ 2.092654] xhci-mtk 11200000.usb: xHCI Host Controller
10634 00:45:30.395975 <6>[ 2.098151] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10635 00:45:30.406177 <6>[ 2.106002] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10636 00:45:30.412813 <6>[ 2.115425] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10637 00:45:30.419452 <6>[ 2.121495] xhci-mtk 11200000.usb: xHCI Host Controller
10638 00:45:30.426126 <6>[ 2.126971] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10639 00:45:30.433109 <6>[ 2.134616] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10640 00:45:30.439398 <6>[ 2.142214] hub 1-0:1.0: USB hub found
10641 00:45:30.443107 <6>[ 2.146224] hub 1-0:1.0: 1 port detected
10642 00:45:30.449741 <6>[ 2.150487] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10643 00:45:30.456264 <6>[ 2.159053] hub 2-0:1.0: USB hub found
10644 00:45:30.459293 <6>[ 2.163056] hub 2-0:1.0: 1 port detected
10645 00:45:30.466810 <6>[ 2.169907] mtk-msdc 11f70000.mmc: Got CD GPIO
10646 00:45:30.478186 <6>[ 2.178042] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10647 00:45:30.487917 <6>[ 2.186421] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10648 00:45:30.494592 <6>[ 2.194760] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10649 00:45:30.501613 <6>[ 2.203107] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10650 00:45:30.511411 <6>[ 2.211444] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10651 00:45:30.517992 <6>[ 2.219782] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10652 00:45:30.528402 <6>[ 2.228123] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10653 00:45:30.534968 <6>[ 2.236462] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10654 00:45:30.544938 <6>[ 2.244800] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10655 00:45:30.551393 <6>[ 2.253138] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10656 00:45:30.561205 <6>[ 2.261476] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10657 00:45:30.571484 <6>[ 2.269814] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10658 00:45:30.578143 <6>[ 2.278157] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10659 00:45:30.585074 <6>[ 2.286495] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10660 00:45:30.594874 <6>[ 2.294833] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10661 00:45:30.601548 <6>[ 2.303513] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10662 00:45:30.608323 <6>[ 2.310396] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10663 00:45:30.615154 <6>[ 2.317198] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10664 00:45:30.622000 <6>[ 2.323961] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10665 00:45:30.628004 <6>[ 2.330892] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10666 00:45:30.638036 <6>[ 2.337766] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10667 00:45:30.648396 <6>[ 2.346902] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10668 00:45:30.657895 <6>[ 2.356024] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10669 00:45:30.667756 <6>[ 2.365317] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10670 00:45:30.674616 <6>[ 2.374785] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10671 00:45:30.684432 <6>[ 2.384252] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10672 00:45:30.694337 <6>[ 2.393372] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10673 00:45:30.704349 <6>[ 2.402840] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10674 00:45:30.714111 <6>[ 2.411959] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10675 00:45:30.724128 <6>[ 2.421253] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10676 00:45:30.734331 <6>[ 2.431413] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10677 00:45:30.744234 <6>[ 2.443145] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10678 00:45:30.750782 <6>[ 2.454277] Trying to probe devices needed for running init ...
10679 00:45:30.761044 <3>[ 2.461198] mt8192-audio 11210000.syscon:mt8192-afe-pcm: could not get audiosys reset:-517
10680 00:45:30.867577 <6>[ 2.567110] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10681 00:45:31.022042 <6>[ 2.725016] hub 1-1:1.0: USB hub found
10682 00:45:31.025675 <6>[ 2.729492] hub 1-1:1.0: 4 ports detected
10683 00:45:31.036952 <6>[ 2.739813] hub 1-1:1.0: USB hub found
10684 00:45:31.040370 <6>[ 2.744113] hub 1-1:1.0: 4 ports detected
10685 00:45:31.147440 <6>[ 2.847463] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10686 00:45:31.173738 <6>[ 2.877214] hub 2-1:1.0: USB hub found
10687 00:45:31.177085 <6>[ 2.881730] hub 2-1:1.0: 3 ports detected
10688 00:45:31.188466 <6>[ 2.891951] hub 2-1:1.0: USB hub found
10689 00:45:31.191972 <6>[ 2.896390] hub 2-1:1.0: 3 ports detected
10690 00:45:31.359406 <6>[ 3.059162] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10691 00:45:31.492672 <6>[ 3.195103] hub 1-1.4:1.0: USB hub found
10692 00:45:31.495562 <6>[ 3.199766] hub 1-1.4:1.0: 2 ports detected
10693 00:45:31.507410 <6>[ 3.210626] hub 1-1.4:1.0: USB hub found
10694 00:45:31.510900 <6>[ 3.215200] hub 1-1.4:1.0: 2 ports detected
10695 00:45:31.571562 <6>[ 3.271279] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10696 00:45:31.679979 <6>[ 3.379845] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10697 00:45:31.716259 <4>[ 3.415602] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10698 00:45:31.725895 <4>[ 3.424705] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10699 00:45:31.770107 <6>[ 3.472847] r8152 2-1.3:1.0 eth0: v1.12.13
10700 00:45:31.811237 <6>[ 3.510911] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10701 00:45:32.002763 <6>[ 3.703157] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10702 00:45:33.403402 <6>[ 5.107070] r8152 2-1.3:1.0 eth0: carrier on
10703 00:45:36.074933 <5>[ 5.130909] Sending DHCP requests .., OK
10704 00:45:36.081703 <6>[ 7.783232] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.21
10705 00:45:36.084838 <6>[ 7.791526] IP-Config: Complete:
10706 00:45:36.098008 <6>[ 7.795020] device=eth0, hwaddr=00:e0:4c:72:2d:d6, ipaddr=192.168.201.21, mask=255.255.255.0, gw=192.168.201.1
10707 00:45:36.104999 <6>[ 7.805731] host=mt8192-asurada-spherion-r0-cbg-1, domain=lava-rack, nis-domain=(none)
10708 00:45:36.111229 <6>[ 7.814349] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10709 00:45:36.118110 <6>[ 7.814360] nameserver0=192.168.201.1
10710 00:45:36.120983 <6>[ 7.826517] clk: Disabling unused clocks
10711 00:45:36.125393 <6>[ 7.832318] ALSA device list:
10712 00:45:36.131410 <6>[ 7.835562] No soundcards found.
10713 00:45:36.139196 <6>[ 7.843043] Freeing unused kernel memory: 8512K
10714 00:45:36.142547 <6>[ 7.847961] Run /init as init process
10715 00:45:36.151221 Loading, please wait...
10716 00:45:36.180785 Starting systemd-udevd version 252.22-1~deb12u1
10717 00:45:36.422894 <6>[ 8.123501] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10718 00:45:36.447522 <6>[ 8.148423] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10719 00:45:36.454806 <6>[ 8.149440] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10720 00:45:36.465044 <6>[ 8.165946] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10721 00:45:36.475353 <6>[ 8.174998] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10722 00:45:36.483801 <6>[ 8.187986] remoteproc remoteproc0: scp is available
10723 00:45:36.490477 <6>[ 8.193533] remoteproc remoteproc0: powering up scp
10724 00:45:36.497049 <6>[ 8.196150] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10725 00:45:36.506818 <3>[ 8.196696] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10726 00:45:36.513641 <3>[ 8.196720] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10727 00:45:36.520248 <3>[ 8.196729] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10728 00:45:36.530053 <6>[ 8.198692] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10729 00:45:36.536905 <6>[ 8.206689] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10730 00:45:36.546422 <3>[ 8.214287] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10731 00:45:36.553037 <3>[ 8.214312] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10732 00:45:36.563364 <3>[ 8.214335] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10733 00:45:36.569738 <3>[ 8.214357] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10734 00:45:36.580015 <3>[ 8.214372] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10735 00:45:36.583043 <6>[ 8.214770] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10736 00:45:36.592944 <3>[ 8.221536] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10737 00:45:36.599649 <4>[ 8.222931] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10738 00:45:36.609596 <3>[ 8.230690] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10739 00:45:36.616153 <3>[ 8.230710] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10740 00:45:36.626290 <3>[ 8.230718] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10741 00:45:36.633153 <3>[ 8.230793] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10742 00:45:36.642992 <3>[ 8.230802] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10743 00:45:36.649383 <3>[ 8.230809] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10744 00:45:36.659422 <3>[ 8.230820] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10745 00:45:36.665803 <3>[ 8.230846] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10746 00:45:36.672559 <3>[ 8.230900] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10747 00:45:36.682335 <6>[ 8.268578] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10748 00:45:36.689318 <4>[ 8.268845] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10749 00:45:36.692499 <6>[ 8.269059] Bluetooth: Core ver 2.22
10750 00:45:36.699273 <6>[ 8.270482] NET: Registered PF_BLUETOOTH protocol family
10751 00:45:36.705928 <6>[ 8.270484] Bluetooth: HCI device and connection manager initialized
10752 00:45:36.709114 <6>[ 8.270684] Bluetooth: HCI socket layer initialized
10753 00:45:36.715629 <6>[ 8.270692] Bluetooth: L2CAP socket layer initialized
10754 00:45:36.722301 <6>[ 8.270699] Bluetooth: SCO socket layer initialized
10755 00:45:36.728935 <6>[ 8.271936] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10756 00:45:36.735928 <4>[ 8.275112] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10757 00:45:36.742429 <6>[ 8.283656] mc: Linux media interface: v0.10
10758 00:45:36.748894 <6>[ 8.287608] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10759 00:45:36.755345 <6>[ 8.291475] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10760 00:45:36.765588 <4>[ 8.293960] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10761 00:45:36.768895 <4>[ 8.293960] Fallback method does not support PEC.
10762 00:45:36.778752 <6>[ 8.301427] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10763 00:45:36.785721 <6>[ 8.315042] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10764 00:45:36.792024 <6>[ 8.318561] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10765 00:45:36.798568 <6>[ 8.326718] pci_bus 0000:00: root bus resource [bus 00-ff]
10766 00:45:36.808690 <6>[ 8.334711] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10767 00:45:36.818446 <6>[ 8.430169] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10768 00:45:36.824991 <6>[ 8.438114] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10769 00:45:36.831579 <6>[ 8.438172] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10770 00:45:36.838506 <6>[ 8.438182] remoteproc remoteproc0: remote processor scp is now up
10771 00:45:36.845000 <6>[ 8.445364] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10772 00:45:36.854901 <6>[ 8.451183] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10773 00:45:36.865172 <6>[ 8.458227] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10774 00:45:36.875220 <6>[ 8.466467] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10775 00:45:36.881851 <6>[ 8.479513] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10776 00:45:36.888200 <6>[ 8.487327] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10777 00:45:36.898072 <6>[ 8.494157] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10778 00:45:36.901854 <6>[ 8.494254] pci 0000:00:00.0: supports D1 D2
10779 00:45:36.908159 <6>[ 8.495231] videodev: Linux video capture interface: v2.00
10780 00:45:36.914630 <6>[ 8.505070] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10781 00:45:36.921240 <6>[ 8.507768] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10782 00:45:36.931259 <6>[ 8.509108] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10783 00:45:36.937890 <6>[ 8.549842] usbcore: registered new interface driver btusb
10784 00:45:36.948298 <4>[ 8.550260] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10785 00:45:36.954692 <3>[ 8.550269] Bluetooth: hci0: Failed to load firmware file (-2)
10786 00:45:36.958165 <3>[ 8.550272] Bluetooth: hci0: Failed to set up firmware (-2)
10787 00:45:36.967781 <4>[ 8.550275] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10788 00:45:36.974767 <6>[ 8.555619] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10789 00:45:36.981231 <6>[ 8.556440] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10790 00:45:36.994837 <6>[ 8.557746] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10791 00:45:37.001025 <6>[ 8.557893] usbcore: registered new interface driver uvcvideo
10792 00:45:37.007807 <6>[ 8.591253] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10793 00:45:37.014206 <6>[ 8.598922] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10794 00:45:37.024348 <6>[ 8.724216] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10795 00:45:37.030847 <6>[ 8.731700] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10796 00:45:37.034129 <6>[ 8.739288] pci 0000:01:00.0: supports D1 D2
10797 00:45:37.040515 <6>[ 8.743807] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10798 00:45:37.062364 <6>[ 8.763066] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10799 00:45:37.068974 <6>[ 8.769967] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10800 00:45:37.075658 <6>[ 8.778052] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10801 00:45:37.085420 <6>[ 8.786050] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10802 00:45:37.091939 <6>[ 8.794050] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10803 00:45:37.102381 <6>[ 8.802051] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10804 00:45:37.105795 <6>[ 8.810053] pci 0000:00:00.0: PCI bridge to [bus 01]
10805 00:45:37.115549 <6>[ 8.815270] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10806 00:45:37.121896 <6>[ 8.823398] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10807 00:45:37.128528 <6>[ 8.830229] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10808 00:45:37.135032 <6>[ 8.836914] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10809 00:45:37.157770 <5>[ 8.858656] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10810 00:45:37.180218 <5>[ 8.881208] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10811 00:45:37.186860 <5>[ 8.889360] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10812 00:45:37.197002 <4>[ 8.897873] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10813 00:45:37.203643 <6>[ 8.906801] cfg80211: failed to load regulatory.db
10814 00:45:37.257724 <6>[ 8.958727] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10815 00:45:37.264497 <6>[ 8.966285] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10816 00:45:37.289139 <6>[ 8.993275] mt7921e 0000:01:00.0: ASIC revision: 79610010
10817 00:45:37.394992 <6>[ 9.095854] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10818 00:45:37.398166 <6>[ 9.095854]
10819 00:45:37.407917 Begin: Loading essential drivers ... done.
10820 00:45:37.411413 Begin: Running /scripts/init-premount ... done.
10821 00:45:37.418028 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10822 00:45:37.427763 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10823 00:45:37.431234 Device /sys/class/net/eth0 found
10824 00:45:37.431320 done.
10825 00:45:37.438191 Begin: Waiting up to 180 secs for any network device to become available ... done.
10826 00:45:37.486996 IP-Config: eth0 hardware address 00:e0:4c:72:2d:d6 mtu 1500 DHCP
10827 00:45:37.496284 IP-Config: eth0 complete (dhcp from 192.168.201.1):
10828 00:45:37.502921 address: 192.168.201.21 broadcast: 192.168.201.255 netmask: 255.255.255.0
10829 00:45:37.509502 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10830 00:45:37.516126 host : mt8192-asurada-spherion-r0-cbg-1
10831 00:45:37.522617 domain : lava-rack
10832 00:45:37.525774 rootserver: 192.168.201.1 rootpath:
10833 00:45:37.529203 filename :
10834 00:45:37.625325 done.
10835 00:45:37.631557 Begin: Running /scripts/nfs-bottom ... done.
10836 00:45:37.648156 Begin: Running /scripts/init-bottom ... done.
10837 00:45:37.663647 <6>[ 9.364276] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10838 00:45:38.982593 <6>[ 10.686933] NET: Registered PF_INET6 protocol family
10839 00:45:38.989971 <6>[ 10.694658] Segment Routing with IPv6
10840 00:45:38.993472 <6>[ 10.698660] In-situ OAM (IOAM) with IPv6
10841 00:45:39.163768 <30>[ 10.841735] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10842 00:45:39.170442 <30>[ 10.874915] systemd[1]: Detected architecture arm64.
10843 00:45:39.178345
10844 00:45:39.181634 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10845 00:45:39.181720
10846 00:45:39.208028 <30>[ 10.912163] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10847 00:45:40.250298 <30>[ 11.951506] systemd[1]: Queued start job for default target graphical.target.
10848 00:45:40.287489 <30>[ 11.988448] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10849 00:45:40.294031 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10850 00:45:40.315939 <30>[ 12.017182] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10851 00:45:40.325730 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10852 00:45:40.343602 <30>[ 12.045049] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10853 00:45:40.354091 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10854 00:45:40.372301 <30>[ 12.073507] systemd[1]: Created slice user.slice - User and Session Slice.
10855 00:45:40.378639 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10856 00:45:40.402043 <30>[ 12.100044] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10857 00:45:40.411792 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10858 00:45:40.433234 <30>[ 12.131072] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10859 00:45:40.439979 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10860 00:45:40.468512 <30>[ 12.159788] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10861 00:45:40.478541 <30>[ 12.179727] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10862 00:45:40.485293 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10863 00:45:40.502547 <30>[ 12.203565] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10864 00:45:40.511994 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10865 00:45:40.529871 <30>[ 12.231295] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10866 00:45:40.540020 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10867 00:45:40.555127 <30>[ 12.259717] systemd[1]: Reached target paths.target - Path Units.
10868 00:45:40.565204 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10869 00:45:40.582427 <30>[ 12.283604] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10870 00:45:40.588928 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10871 00:45:40.603035 <30>[ 12.307153] systemd[1]: Reached target slices.target - Slice Units.
10872 00:45:40.613025 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10873 00:45:40.626878 <30>[ 12.331217] systemd[1]: Reached target swap.target - Swaps.
10874 00:45:40.633279 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10875 00:45:40.653940 <30>[ 12.355241] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10876 00:45:40.664218 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10877 00:45:40.683010 <30>[ 12.384189] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10878 00:45:40.693179 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10879 00:45:40.712390 <30>[ 12.413655] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10880 00:45:40.722429 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10881 00:45:40.739270 <30>[ 12.440497] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10882 00:45:40.748854 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10883 00:45:40.766861 <30>[ 12.467885] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10884 00:45:40.773447 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10885 00:45:40.791359 <30>[ 12.492652] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10886 00:45:40.801326 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10887 00:45:40.820515 <30>[ 12.521938] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10888 00:45:40.830423 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10889 00:45:40.847109 <30>[ 12.548400] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10890 00:45:40.856901 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10891 00:45:40.897978 <30>[ 12.599184] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10892 00:45:40.904486 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10893 00:45:40.926993 <30>[ 12.628129] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10894 00:45:40.933414 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10895 00:45:40.959194 <30>[ 12.660630] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10896 00:45:40.965883 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10897 00:45:40.993364 <30>[ 12.687914] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10898 00:45:41.042621 <30>[ 12.743902] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10899 00:45:41.052367 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10900 00:45:41.076531 <30>[ 12.777700] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10901 00:45:41.083393 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10902 00:45:41.107933 <30>[ 12.809212] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10903 00:45:41.114702 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10904 00:45:41.140193 <30>[ 12.841517] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10905 00:45:41.150277 Startin<6>[ 12.850898] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10906 00:45:41.156805 g [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10907 00:45:41.206850 <30>[ 12.907952] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10908 00:45:41.216457 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10909 00:45:41.240361 <30>[ 12.941894] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10910 00:45:41.247066 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10911 00:45:41.272193 <30>[ 12.973352] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10912 00:45:41.278821 Startin<6>[ 12.982216] fuse: init (API version 7.37)
10913 00:45:41.285143 g [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10914 00:45:41.346967 <30>[ 13.048187] systemd[1]: Starting systemd-journald.service - Journal Service...
10915 00:45:41.353640 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10916 00:45:41.414584 <30>[ 13.116001] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10917 00:45:41.421530 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10918 00:45:41.452107 <30>[ 13.150319] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10919 00:45:41.458664 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10920 00:45:41.484110 <30>[ 13.185466] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10921 00:45:41.493985 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10922 00:45:41.516570 <30>[ 13.218140] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10923 00:45:41.523681 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10924 00:45:41.548458 <30>[ 13.249914] systemd[1]: Started systemd-journald.service - Journal Service.
10925 00:45:41.555082 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10926 00:45:41.578195 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10927 00:45:41.594596 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10928 00:45:41.614330 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10929 00:45:41.634916 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10930 00:45:41.657519 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10931 00:45:41.688507 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10932 00:45:41.707637 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10933 00:45:41.727181 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10934 00:45:41.752840 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
10935 00:45:41.776860 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10936 00:45:41.799795 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10937 00:45:41.819571 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10938 00:45:41.839298 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
10939 00:45:41.864657 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10940 00:45:41.930641 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
10941 00:45:41.953161 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10942 00:45:41.976911 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10943 00:45:42.002524 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10944 00:45:42.028545 <46>[ 13.729947] systemd-journald[312]: Received client request to flush runtime journal.
10945 00:45:42.043362 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10946 00:45:42.074590 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10947 00:45:42.362519 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10948 00:45:42.382819 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
10949 00:45:42.402214 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10950 00:45:42.419455 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10951 00:45:42.809519 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10952 00:45:43.173257 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10953 00:45:43.214527 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10954 00:45:43.466291 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10955 00:45:43.584225 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10956 00:45:43.602987 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10957 00:45:43.622184 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10958 00:45:43.666018 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10959 00:45:43.687396 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10960 00:45:43.932114 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10961 00:45:43.989144 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
10962 00:45:44.031317 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10963 00:45:44.227857 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10964 00:45:44.323567 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10965 00:45:44.348030 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10966 00:45:44.355260 <6>[ 16.059279] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10967 00:45:44.405788 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
10968 00:45:44.463090 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
10969 00:45:44.514105 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
10970 00:45:44.556083 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
10971 00:45:44.602824 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
10972 00:45:44.622675 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
10973 00:45:44.643062 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10974 00:45:44.665416 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
10975 00:45:44.685209 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
10976 00:45:44.718161 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10977 00:45:44.735142 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
10978 00:45:44.758156 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10979 00:45:44.774298 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10980 00:45:44.789670 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
10981 00:45:44.840059 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
10982 00:45:44.864997 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
10983 00:45:44.881999 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
10984 00:45:44.901854 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
10985 00:45:44.921302 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
10986 00:45:44.937770 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
10987 00:45:44.955956 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
10988 00:45:44.974203 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
10989 00:45:44.980692 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
10990 00:45:45.031285 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
10991 00:45:45.065402 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
10992 00:45:45.142900 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
10993 00:45:45.169669 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
10994 00:45:45.218541 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
10995 00:45:45.283094 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
10996 00:45:45.308533 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
10997 00:45:45.333874 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
10998 00:45:45.354070 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
10999 00:45:45.399479 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11000 00:45:45.515851 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
11001 00:45:45.529063 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11002 00:45:45.545097 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11003 00:45:45.597039 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11004 00:45:45.653561 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11005 00:45:45.740272
11006 00:45:45.743655 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11007 00:45:45.743748
11008 00:45:45.746795 debian-bookworm-arm64 login: root (automatic login)
11009 00:45:45.746882
11010 00:45:46.036410 Linux debian-bookworm-arm64 6.1.92-cip22 #1 SMP PREEMPT Sun Jun 16 00:28:47 UTC 2024 aarch64
11011 00:45:46.036571
11012 00:45:46.043131 The programs included with the Debian GNU/Linux system are free software;
11013 00:45:46.049320 the exact distribution terms for each program are described in the
11014 00:45:46.053050 individual files in /usr/share/doc/*/copyright.
11015 00:45:46.053135
11016 00:45:46.059279 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11017 00:45:46.062747 permitted by applicable law.
11018 00:45:47.119055 Matched prompt #10: / #
11020 00:45:47.119448 Setting prompt string to ['/ #']
11021 00:45:47.119576 end: 2.2.5.1 login-action (duration 00:00:20) [common]
11023 00:45:47.119879 end: 2.2.5 auto-login-action (duration 00:00:20) [common]
11024 00:45:47.119998 start: 2.2.6 expect-shell-connection (timeout 00:03:42) [common]
11025 00:45:47.120099 Setting prompt string to ['/ #']
11026 00:45:47.120190 Forcing a shell prompt, looking for ['/ #']
11028 00:45:47.170470 / #
11029 00:45:47.170571 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11030 00:45:47.170648 Waiting using forced prompt support (timeout 00:02:30)
11031 00:45:47.175820
11032 00:45:47.176089 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11033 00:45:47.176186 start: 2.2.7 export-device-env (timeout 00:03:42) [common]
11035 00:45:47.276534 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14368392/extract-nfsrootfs-_yqx9ly3'
11036 00:45:47.281581 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14368392/extract-nfsrootfs-_yqx9ly3'
11038 00:45:47.382102 / # export NFS_SERVER_IP='192.168.201.1'
11039 00:45:47.387354 export NFS_SERVER_IP='192.168.201.1'
11040 00:45:47.387638 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11041 00:45:47.387740 end: 2.2 depthcharge-retry (duration 00:01:18) [common]
11042 00:45:47.387831 end: 2 depthcharge-action (duration 00:01:18) [common]
11043 00:45:47.387925 start: 3 lava-test-retry (timeout 00:08:04) [common]
11044 00:45:47.388018 start: 3.1 lava-test-shell (timeout 00:08:04) [common]
11045 00:45:47.388093 Using namespace: common
11047 00:45:47.488438 / # #
11048 00:45:47.488571 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11049 00:45:47.493734 #
11050 00:45:47.493996 Using /lava-14368392
11052 00:45:47.594330 / # export SHELL=/bin/bash
11053 00:45:47.599750 export SHELL=/bin/bash
11055 00:45:47.700265 / # . /lava-14368392/environment
11056 00:45:47.706017 . /lava-14368392/environment
11058 00:45:47.811898 / # /lava-14368392/bin/lava-test-runner /lava-14368392/0
11059 00:45:47.812008 Test shell timeout: 10s (minimum of the action and connection timeout)
11060 00:45:47.817241 /lava-14368392/bin/lava-test-runner /lava-14368392/0
11061 00:45:48.046128 + export TESTRUN_ID=0_timesync-off
11062 00:45:48.049381 + TESTRUN_ID=0_timesync-off
11063 00:45:48.052480 + cd /lava-14368392/0/tests/0_timesync-off
11064 00:45:48.056054 ++ cat uuid
11065 00:45:48.059293 + UUID=14368392_1.6.2.3.1
11066 00:45:48.059376 + set +x
11067 00:45:48.066346 <LAVA_SIGNAL_STARTRUN 0_timesync-off 14368392_1.6.2.3.1>
11068 00:45:48.066610 Received signal: <STARTRUN> 0_timesync-off 14368392_1.6.2.3.1
11069 00:45:48.066686 Starting test lava.0_timesync-off (14368392_1.6.2.3.1)
11070 00:45:48.066778 Skipping test definition patterns.
11071 00:45:48.069341 + systemctl stop systemd-timesyncd
11072 00:45:48.126531 + set +x
11073 00:45:48.129858 <LAVA_SIGNAL_ENDRUN 0_timesync-off 14368392_1.6.2.3.1>
11074 00:45:48.130115 Received signal: <ENDRUN> 0_timesync-off 14368392_1.6.2.3.1
11075 00:45:48.130199 Ending use of test pattern.
11076 00:45:48.130274 Ending test lava.0_timesync-off (14368392_1.6.2.3.1), duration 0.06
11078 00:45:48.190664 + export TESTRUN_ID=1_kselftest-rtc
11079 00:45:48.193812 + TESTRUN_ID=1_kselftest-rtc
11080 00:45:48.197025 + cd /lava-14368392/0/tests/1_kselftest-rtc
11081 00:45:48.200462 ++ cat uuid
11082 00:45:48.204082 + UUID=14368392_1.6.2.3.5
11083 00:45:48.204160 + set +x
11084 00:45:48.210558 <LAVA_SIGNAL_STARTRUN 1_kselftest-rtc 14368392_1.6.2.3.5>
11085 00:45:48.210801 Received signal: <STARTRUN> 1_kselftest-rtc 14368392_1.6.2.3.5
11086 00:45:48.210867 Starting test lava.1_kselftest-rtc (14368392_1.6.2.3.5)
11087 00:45:48.210944 Skipping test definition patterns.
11088 00:45:48.213605 + cd ./automated/linux/kselftest/
11089 00:45:48.240313 + ./kselftest.sh -c rtc -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-24-g0315de64ea248/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11090 00:45:48.268956 INFO: install_deps skipped
11091 00:45:48.770660 --2024-06-16 00:44:23-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-24-g0315de64ea248/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11092 00:45:48.776976 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11093 00:45:48.895023 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11094 00:45:49.019561 HTTP request sent, awaiting response... 200 OK
11095 00:45:49.022511 Length: 1647580 (1.6M) [application/octet-stream]
11096 00:45:49.025751 Saving to: 'kselftest_armhf.tar.gz'
11097 00:45:49.025920
11098 00:45:49.026100
11099 00:45:49.268632 kselftest_armhf.tar 0%[ ] 0 --.-KB/s
11100 00:45:49.517058 kselftest_armhf.tar 2%[ ] 47.81K 188KB/s
11101 00:45:49.812674 kselftest_armhf.tar 13%[=> ] 214.67K 421KB/s
11102 00:45:49.944627 kselftest_armhf.tar 51%[=========> ] 828.37K 1021KB/s
11103 00:45:49.951298 kselftest_armhf.tar 100%[===================>] 1.57M 1.66MB/s in 0.9s
11104 00:45:49.951393
11105 00:45:50.102624 2024-06-16 00:44:24 (1.66 MB/s) - 'kselftest_armhf.tar.gz' saved [1647580/1647580]
11106 00:45:50.102767
11107 00:45:54.129005 skiplist:
11108 00:45:54.132102 ========================================
11109 00:45:54.135580 ========================================
11110 00:45:54.182882 rtc:rtctest
11111 00:45:54.203759 ============== Tests to run ===============
11112 00:45:54.203849 rtc:rtctest
11113 00:45:54.207296 ===========End Tests to run ===============
11114 00:45:54.210545 shardfile-rtc pass
11115 00:45:54.308399 <12>[ 26.014702] kselftest: Running tests in rtc
11116 00:45:54.318088 TAP version 13
11117 00:45:54.332337 1..1
11118 00:45:54.363307 # selftests: rtc: rtctest
11119 00:45:54.831865 # TAP version 13
11120 00:45:54.832019 # 1..8
11121 00:45:54.834780 # # Starting 8 tests from 2 test cases.
11122 00:45:54.838463 # # RUN rtc.date_read ...
11123 00:45:54.844734 # # rtctest.c:49:date_read:Current RTC date/time is 16/06/2024 00:44:28.
11124 00:45:54.848306 # # OK rtc.date_read
11125 00:45:54.851248 # ok 1 rtc.date_read
11126 00:45:54.854769 # # RUN rtc.date_read_loop ...
11127 00:45:54.864412 # # rtctest.c:88:date_read_loop:Continuously reading RTC time for 30s (with 11ms breaks after every read).
11128 00:46:05.979835 <6>[ 37.690599] vpu: disabling
11129 00:46:05.982926 <6>[ 37.693778] vproc2: disabling
11130 00:46:05.986343 <6>[ 37.697409] vproc1: disabling
11131 00:46:05.990127 <6>[ 37.700870] vaud18: disabling
11132 00:46:05.996890 <6>[ 37.704413] vsram_others: disabling
11133 00:46:06.000104 <6>[ 37.708392] va09: disabling
11134 00:46:06.003563 <6>[ 37.711570] vsram_md: disabling
11135 00:46:06.006637 <6>[ 37.715528] Vgpu: disabling
11136 00:46:24.491673 # # rtctest.c:115:date_read_loop:Performed 2590 RTC time reads.
11137 00:46:24.494544 # # OK rtc.date_read_loop
11138 00:46:24.497943 # ok 2 rtc.date_read_loop
11139 00:46:24.501328 # # RUN rtc.uie_read ...
11140 00:46:27.471257 # # OK rtc.uie_read
11141 00:46:27.474494 # ok 3 rtc.uie_read
11142 00:46:27.477812 # # RUN rtc.uie_select ...
11143 00:46:30.471179 # # OK rtc.uie_select
11144 00:46:30.474372 # ok 4 rtc.uie_select
11145 00:46:30.477851 # # RUN rtc.alarm_alm_set ...
11146 00:46:30.484572 # # rtctest.c:202:alarm_alm_set:Alarm time now set to 00:45:08.
11147 00:46:30.487825 # # rtctest.c:207:alarm_alm_set:Expected -1 (-1) != rc (-1)
11148 00:46:30.494427 # # alarm_alm_set: Test terminated by assertion
11149 00:46:30.497509 # # FAIL rtc.alarm_alm_set
11150 00:46:30.497588 # not ok 5 rtc.alarm_alm_set
11151 00:46:30.504502 # # RUN rtc.alarm_wkalm_set ...
11152 00:46:30.511027 # # rtctest.c:258:alarm_wkalm_set:Alarm time now set to 16/06/2024 00:45:08.
11153 00:46:33.473803 # # OK rtc.alarm_wkalm_set
11154 00:46:33.473954 # ok 6 rtc.alarm_wkalm_set
11155 00:46:33.480716 # # RUN rtc.alarm_alm_set_minute ...
11156 00:46:33.483776 # # rtctest.c:304:alarm_alm_set_minute:Alarm time now set to 00:46:00.
11157 00:46:33.490400 # # rtctest.c:309:alarm_alm_set_minute:Expected -1 (-1) != rc (-1)
11158 00:46:33.497184 # # alarm_alm_set_minute: Test terminated by assertion
11159 00:46:33.500344 # # FAIL rtc.alarm_alm_set_minute
11160 00:46:33.503772 # not ok 7 rtc.alarm_alm_set_minute
11161 00:46:33.507278 # # RUN rtc.alarm_wkalm_set_minute ...
11162 00:46:33.513822 # # rtctest.c:360:alarm_wkalm_set_minute:Alarm time now set to 16/06/2024 00:46:00.
11163 00:47:25.467915 # # OK rtc.alarm_wkalm_set_minute
11164 00:47:25.470985 # ok 8 rtc.alarm_wkalm_set_minute
11165 00:47:25.474284 # # FAILED: 6 / 8 tests passed.
11166 00:47:25.477973 # # Totals: pass:6 fail:2 xfail:0 xpass:0 skip:0 error:0
11167 00:47:25.481267 not ok 1 selftests: rtc: rtctest # exit=1
11168 00:47:27.003110 rtc_rtctest_rtc_date_read pass
11169 00:47:27.006468 rtc_rtctest_rtc_date_read_loop pass
11170 00:47:27.009347 rtc_rtctest_rtc_uie_read pass
11171 00:47:27.012229 rtc_rtctest_rtc_uie_select pass
11172 00:47:27.015654 rtc_rtctest_rtc_alarm_alm_set fail
11173 00:47:27.018584 rtc_rtctest_rtc_alarm_wkalm_set pass
11174 00:47:27.021840 rtc_rtctest_rtc_alarm_alm_set_minute fail
11175 00:47:27.025183 rtc_rtctest_rtc_alarm_wkalm_set_minute pass
11176 00:47:27.028522 rtc_rtctest fail
11177 00:47:27.079596 + ../../utils/send-to-lava.sh ./output/result.txt
11178 00:47:27.141985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-rtc RESULT=pass>
11179 00:47:27.142260 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-rtc RESULT=pass
11181 00:47:27.179499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_date_read RESULT=pass>
11182 00:47:27.179767 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_date_read RESULT=pass
11184 00:47:27.220925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_date_read_loop RESULT=pass>
11185 00:47:27.221180 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_date_read_loop RESULT=pass
11187 00:47:27.260018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_uie_read RESULT=pass>
11188 00:47:27.260283 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_uie_read RESULT=pass
11190 00:47:27.300988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_uie_select RESULT=pass>
11191 00:47:27.301260 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_uie_select RESULT=pass
11193 00:47:27.344497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set RESULT=fail>
11194 00:47:27.344758 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set RESULT=fail
11196 00:47:27.374298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set RESULT=pass>
11197 00:47:27.374602 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set RESULT=pass
11199 00:47:27.403693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set_minute RESULT=fail>
11200 00:47:27.403949 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set_minute RESULT=fail
11202 00:47:27.439874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set_minute RESULT=pass>
11203 00:47:27.440125 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set_minute RESULT=pass
11205 00:47:27.471391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest RESULT=fail>
11206 00:47:27.471478 + set +x
11207 00:47:27.471743 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest RESULT=fail
11209 00:47:27.477843 <LAVA_SIGNAL_ENDRUN 1_kselftest-rtc 14368392_1.6.2.3.5>
11210 00:47:27.478098 Received signal: <ENDRUN> 1_kselftest-rtc 14368392_1.6.2.3.5
11211 00:47:27.478175 Ending use of test pattern.
11212 00:47:27.478239 Ending test lava.1_kselftest-rtc (14368392_1.6.2.3.5), duration 99.27
11214 00:47:27.478459 ok: lava_test_shell seems to have completed
11215 00:47:27.478591 rtc_rtctest: fail
rtc_rtctest_rtc_alarm_alm_set: fail
rtc_rtctest_rtc_alarm_alm_set_minute: fail
rtc_rtctest_rtc_alarm_wkalm_set: pass
rtc_rtctest_rtc_alarm_wkalm_set_minute: pass
rtc_rtctest_rtc_date_read: pass
rtc_rtctest_rtc_date_read_loop: pass
rtc_rtctest_rtc_uie_read: pass
rtc_rtctest_rtc_uie_select: pass
shardfile-rtc: pass
11216 00:47:27.478682 end: 3.1 lava-test-shell (duration 00:01:40) [common]
11217 00:47:27.478764 end: 3 lava-test-retry (duration 00:01:40) [common]
11218 00:47:27.478855 start: 4 finalize (timeout 00:06:24) [common]
11219 00:47:27.478945 start: 4.1 power-off (timeout 00:00:30) [common]
11220 00:47:27.479096 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-1', '--port=1', '--command=off']
11221 00:47:27.687225 >> Command sent successfully.
11222 00:47:27.697809 Returned 0 in 0 seconds
11223 00:47:27.799127 end: 4.1 power-off (duration 00:00:00) [common]
11225 00:47:27.800648 start: 4.2 read-feedback (timeout 00:06:24) [common]
11227 00:47:27.802840 Listened to connection for namespace 'common' for up to 1s
11228 00:47:28.802684 Finalising connection for namespace 'common'
11229 00:47:28.803375 Disconnecting from shell: Finalise
11230 00:47:28.803798 / #
11231 00:47:28.904855 end: 4.2 read-feedback (duration 00:00:01) [common]
11232 00:47:28.905701 end: 4 finalize (duration 00:00:01) [common]
11233 00:47:28.906336 Cleaning after the job
11234 00:47:28.906850 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14368392/tftp-deploy-ut6dle8v/ramdisk
11235 00:47:28.917572 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14368392/tftp-deploy-ut6dle8v/kernel
11236 00:47:28.950920 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14368392/tftp-deploy-ut6dle8v/dtb
11237 00:47:28.951244 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14368392/tftp-deploy-ut6dle8v/nfsrootfs
11238 00:47:29.017702 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14368392/tftp-deploy-ut6dle8v/modules
11239 00:47:29.023180 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14368392
11240 00:47:29.533212 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14368392
11241 00:47:29.533399 Job finished correctly