Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 35
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 25
1 00:43:24.103451 lava-dispatcher, installed at version: 2024.03
2 00:43:24.103662 start: 0 validate
3 00:43:24.103775 Start time: 2024-06-16 00:43:24.103767+00:00 (UTC)
4 00:43:24.103895 Using caching service: 'http://localhost/cache/?uri=%s'
5 00:43:24.104034 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 00:43:24.359297 Using caching service: 'http://localhost/cache/?uri=%s'
7 00:43:24.359994 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22-24-g0315de64ea248%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 00:43:24.613163 Using caching service: 'http://localhost/cache/?uri=%s'
9 00:43:24.613918 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22-24-g0315de64ea248%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 00:43:24.867334 Using caching service: 'http://localhost/cache/?uri=%s'
11 00:43:24.867926 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 00:43:25.128013 Using caching service: 'http://localhost/cache/?uri=%s'
13 00:43:25.128696 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22-24-g0315de64ea248%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 00:43:25.387659 validate duration: 1.28
16 00:43:25.389028 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 00:43:25.389569 start: 1.1 download-retry (timeout 00:10:00) [common]
18 00:43:25.390051 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 00:43:25.390776 Not decompressing ramdisk as can be used compressed.
20 00:43:25.391262 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 00:43:25.391590 saving as /var/lib/lava/dispatcher/tmp/14368401/tftp-deploy-ngfchemh/ramdisk/initrd.cpio.gz
22 00:43:25.391915 total size: 5628169 (5 MB)
23 00:43:25.396529 progress 0 % (0 MB)
24 00:43:25.404666 progress 5 % (0 MB)
25 00:43:25.411791 progress 10 % (0 MB)
26 00:43:25.416436 progress 15 % (0 MB)
27 00:43:25.420496 progress 20 % (1 MB)
28 00:43:25.423520 progress 25 % (1 MB)
29 00:43:25.426606 progress 30 % (1 MB)
30 00:43:25.429383 progress 35 % (1 MB)
31 00:43:25.431589 progress 40 % (2 MB)
32 00:43:25.433952 progress 45 % (2 MB)
33 00:43:25.435960 progress 50 % (2 MB)
34 00:43:25.438119 progress 55 % (2 MB)
35 00:43:25.440178 progress 60 % (3 MB)
36 00:43:25.441842 progress 65 % (3 MB)
37 00:43:25.443712 progress 70 % (3 MB)
38 00:43:25.445350 progress 75 % (4 MB)
39 00:43:25.447014 progress 80 % (4 MB)
40 00:43:25.448496 progress 85 % (4 MB)
41 00:43:25.450171 progress 90 % (4 MB)
42 00:43:25.451685 progress 95 % (5 MB)
43 00:43:25.453065 progress 100 % (5 MB)
44 00:43:25.453272 5 MB downloaded in 0.06 s (87.48 MB/s)
45 00:43:25.453419 end: 1.1.1 http-download (duration 00:00:00) [common]
47 00:43:25.453645 end: 1.1 download-retry (duration 00:00:00) [common]
48 00:43:25.453726 start: 1.2 download-retry (timeout 00:10:00) [common]
49 00:43:25.453804 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 00:43:25.453936 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-24-g0315de64ea248/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 00:43:25.453998 saving as /var/lib/lava/dispatcher/tmp/14368401/tftp-deploy-ngfchemh/kernel/Image
52 00:43:25.454052 total size: 54813184 (52 MB)
53 00:43:25.454108 No compression specified
54 00:43:25.455129 progress 0 % (0 MB)
55 00:43:25.468773 progress 5 % (2 MB)
56 00:43:25.482420 progress 10 % (5 MB)
57 00:43:25.496094 progress 15 % (7 MB)
58 00:43:25.509770 progress 20 % (10 MB)
59 00:43:25.523504 progress 25 % (13 MB)
60 00:43:25.537034 progress 30 % (15 MB)
61 00:43:25.550632 progress 35 % (18 MB)
62 00:43:25.564393 progress 40 % (20 MB)
63 00:43:25.577958 progress 45 % (23 MB)
64 00:43:25.591688 progress 50 % (26 MB)
65 00:43:25.605290 progress 55 % (28 MB)
66 00:43:25.618731 progress 60 % (31 MB)
67 00:43:25.632359 progress 65 % (34 MB)
68 00:43:25.645816 progress 70 % (36 MB)
69 00:43:25.660973 progress 75 % (39 MB)
70 00:43:25.674897 progress 80 % (41 MB)
71 00:43:25.688277 progress 85 % (44 MB)
72 00:43:25.702421 progress 90 % (47 MB)
73 00:43:25.716026 progress 95 % (49 MB)
74 00:43:25.729644 progress 100 % (52 MB)
75 00:43:25.729857 52 MB downloaded in 0.28 s (189.54 MB/s)
76 00:43:25.730001 end: 1.2.1 http-download (duration 00:00:00) [common]
78 00:43:25.730206 end: 1.2 download-retry (duration 00:00:00) [common]
79 00:43:25.730286 start: 1.3 download-retry (timeout 00:10:00) [common]
80 00:43:25.730362 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 00:43:25.730486 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-24-g0315de64ea248/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 00:43:25.730547 saving as /var/lib/lava/dispatcher/tmp/14368401/tftp-deploy-ngfchemh/dtb/mt8192-asurada-spherion-r0.dtb
83 00:43:25.730599 total size: 47258 (0 MB)
84 00:43:25.730652 No compression specified
85 00:43:25.731849 progress 69 % (0 MB)
86 00:43:25.732113 progress 100 % (0 MB)
87 00:43:25.732257 0 MB downloaded in 0.00 s (27.21 MB/s)
88 00:43:25.732366 end: 1.3.1 http-download (duration 00:00:00) [common]
90 00:43:25.732562 end: 1.3 download-retry (duration 00:00:00) [common]
91 00:43:25.732636 start: 1.4 download-retry (timeout 00:10:00) [common]
92 00:43:25.732749 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 00:43:25.732850 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 00:43:25.732908 saving as /var/lib/lava/dispatcher/tmp/14368401/tftp-deploy-ngfchemh/nfsrootfs/full.rootfs.tar
95 00:43:25.732960 total size: 120894716 (115 MB)
96 00:43:25.733013 Using unxz to decompress xz
97 00:43:25.734164 progress 0 % (0 MB)
98 00:43:26.062937 progress 5 % (5 MB)
99 00:43:26.391857 progress 10 % (11 MB)
100 00:43:26.725881 progress 15 % (17 MB)
101 00:43:27.050420 progress 20 % (23 MB)
102 00:43:27.350952 progress 25 % (28 MB)
103 00:43:27.685206 progress 30 % (34 MB)
104 00:43:27.998740 progress 35 % (40 MB)
105 00:43:28.170270 progress 40 % (46 MB)
106 00:43:28.350363 progress 45 % (51 MB)
107 00:43:28.643382 progress 50 % (57 MB)
108 00:43:28.994600 progress 55 % (63 MB)
109 00:43:29.325862 progress 60 % (69 MB)
110 00:43:29.659544 progress 65 % (74 MB)
111 00:43:29.990988 progress 70 % (80 MB)
112 00:43:30.340040 progress 75 % (86 MB)
113 00:43:30.670101 progress 80 % (92 MB)
114 00:43:31.000088 progress 85 % (98 MB)
115 00:43:31.327500 progress 90 % (103 MB)
116 00:43:31.651895 progress 95 % (109 MB)
117 00:43:32.005969 progress 100 % (115 MB)
118 00:43:32.011264 115 MB downloaded in 6.28 s (18.36 MB/s)
119 00:43:32.011431 end: 1.4.1 http-download (duration 00:00:06) [common]
121 00:43:32.011662 end: 1.4 download-retry (duration 00:00:06) [common]
122 00:43:32.011752 start: 1.5 download-retry (timeout 00:09:53) [common]
123 00:43:32.011840 start: 1.5.1 http-download (timeout 00:09:53) [common]
124 00:43:32.011979 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-24-g0315de64ea248/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 00:43:32.012043 saving as /var/lib/lava/dispatcher/tmp/14368401/tftp-deploy-ngfchemh/modules/modules.tar
126 00:43:32.012129 total size: 8608736 (8 MB)
127 00:43:32.012216 Using unxz to decompress xz
128 00:43:32.013896 progress 0 % (0 MB)
129 00:43:32.031983 progress 5 % (0 MB)
130 00:43:32.057049 progress 10 % (0 MB)
131 00:43:32.084176 progress 15 % (1 MB)
132 00:43:32.106945 progress 20 % (1 MB)
133 00:43:32.129497 progress 25 % (2 MB)
134 00:43:32.151876 progress 30 % (2 MB)
135 00:43:32.174885 progress 35 % (2 MB)
136 00:43:32.200204 progress 40 % (3 MB)
137 00:43:32.221888 progress 45 % (3 MB)
138 00:43:32.244652 progress 50 % (4 MB)
139 00:43:32.268159 progress 55 % (4 MB)
140 00:43:32.291342 progress 60 % (4 MB)
141 00:43:32.314331 progress 65 % (5 MB)
142 00:43:32.337861 progress 70 % (5 MB)
143 00:43:32.362357 progress 75 % (6 MB)
144 00:43:32.387119 progress 80 % (6 MB)
145 00:43:32.410276 progress 85 % (7 MB)
146 00:43:32.434252 progress 90 % (7 MB)
147 00:43:32.458078 progress 95 % (7 MB)
148 00:43:32.482273 progress 100 % (8 MB)
149 00:43:32.487632 8 MB downloaded in 0.48 s (17.27 MB/s)
150 00:43:32.487780 end: 1.5.1 http-download (duration 00:00:00) [common]
152 00:43:32.487989 end: 1.5 download-retry (duration 00:00:00) [common]
153 00:43:32.488067 start: 1.6 prepare-tftp-overlay (timeout 00:09:53) [common]
154 00:43:32.488143 start: 1.6.1 extract-nfsrootfs (timeout 00:09:53) [common]
155 00:43:35.927538 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/14368401/extract-nfsrootfs-dn_hmfv5
156 00:43:35.927714 end: 1.6.1 extract-nfsrootfs (duration 00:00:03) [common]
157 00:43:35.927803 start: 1.6.2 lava-overlay (timeout 00:09:49) [common]
158 00:43:35.927962 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14368401/lava-overlay-yw2221_y
159 00:43:35.928077 makedir: /var/lib/lava/dispatcher/tmp/14368401/lava-overlay-yw2221_y/lava-14368401/bin
160 00:43:35.928167 makedir: /var/lib/lava/dispatcher/tmp/14368401/lava-overlay-yw2221_y/lava-14368401/tests
161 00:43:35.928253 makedir: /var/lib/lava/dispatcher/tmp/14368401/lava-overlay-yw2221_y/lava-14368401/results
162 00:43:35.928335 Creating /var/lib/lava/dispatcher/tmp/14368401/lava-overlay-yw2221_y/lava-14368401/bin/lava-add-keys
163 00:43:35.928460 Creating /var/lib/lava/dispatcher/tmp/14368401/lava-overlay-yw2221_y/lava-14368401/bin/lava-add-sources
164 00:43:35.928577 Creating /var/lib/lava/dispatcher/tmp/14368401/lava-overlay-yw2221_y/lava-14368401/bin/lava-background-process-start
165 00:43:35.928740 Creating /var/lib/lava/dispatcher/tmp/14368401/lava-overlay-yw2221_y/lava-14368401/bin/lava-background-process-stop
166 00:43:35.928872 Creating /var/lib/lava/dispatcher/tmp/14368401/lava-overlay-yw2221_y/lava-14368401/bin/lava-common-functions
167 00:43:35.928988 Creating /var/lib/lava/dispatcher/tmp/14368401/lava-overlay-yw2221_y/lava-14368401/bin/lava-echo-ipv4
168 00:43:35.929101 Creating /var/lib/lava/dispatcher/tmp/14368401/lava-overlay-yw2221_y/lava-14368401/bin/lava-install-packages
169 00:43:35.929212 Creating /var/lib/lava/dispatcher/tmp/14368401/lava-overlay-yw2221_y/lava-14368401/bin/lava-installed-packages
170 00:43:35.929323 Creating /var/lib/lava/dispatcher/tmp/14368401/lava-overlay-yw2221_y/lava-14368401/bin/lava-os-build
171 00:43:35.929433 Creating /var/lib/lava/dispatcher/tmp/14368401/lava-overlay-yw2221_y/lava-14368401/bin/lava-probe-channel
172 00:43:35.929544 Creating /var/lib/lava/dispatcher/tmp/14368401/lava-overlay-yw2221_y/lava-14368401/bin/lava-probe-ip
173 00:43:35.929655 Creating /var/lib/lava/dispatcher/tmp/14368401/lava-overlay-yw2221_y/lava-14368401/bin/lava-target-ip
174 00:43:35.929765 Creating /var/lib/lava/dispatcher/tmp/14368401/lava-overlay-yw2221_y/lava-14368401/bin/lava-target-mac
175 00:43:35.929876 Creating /var/lib/lava/dispatcher/tmp/14368401/lava-overlay-yw2221_y/lava-14368401/bin/lava-target-storage
176 00:43:35.929989 Creating /var/lib/lava/dispatcher/tmp/14368401/lava-overlay-yw2221_y/lava-14368401/bin/lava-test-case
177 00:43:35.930100 Creating /var/lib/lava/dispatcher/tmp/14368401/lava-overlay-yw2221_y/lava-14368401/bin/lava-test-event
178 00:43:35.930209 Creating /var/lib/lava/dispatcher/tmp/14368401/lava-overlay-yw2221_y/lava-14368401/bin/lava-test-feedback
179 00:43:35.930319 Creating /var/lib/lava/dispatcher/tmp/14368401/lava-overlay-yw2221_y/lava-14368401/bin/lava-test-raise
180 00:43:35.930432 Creating /var/lib/lava/dispatcher/tmp/14368401/lava-overlay-yw2221_y/lava-14368401/bin/lava-test-reference
181 00:43:35.930543 Creating /var/lib/lava/dispatcher/tmp/14368401/lava-overlay-yw2221_y/lava-14368401/bin/lava-test-runner
182 00:43:35.930653 Creating /var/lib/lava/dispatcher/tmp/14368401/lava-overlay-yw2221_y/lava-14368401/bin/lava-test-set
183 00:43:35.930763 Creating /var/lib/lava/dispatcher/tmp/14368401/lava-overlay-yw2221_y/lava-14368401/bin/lava-test-shell
184 00:43:35.930874 Updating /var/lib/lava/dispatcher/tmp/14368401/lava-overlay-yw2221_y/lava-14368401/bin/lava-add-keys (debian)
185 00:43:35.931011 Updating /var/lib/lava/dispatcher/tmp/14368401/lava-overlay-yw2221_y/lava-14368401/bin/lava-add-sources (debian)
186 00:43:35.931134 Updating /var/lib/lava/dispatcher/tmp/14368401/lava-overlay-yw2221_y/lava-14368401/bin/lava-install-packages (debian)
187 00:43:35.931256 Updating /var/lib/lava/dispatcher/tmp/14368401/lava-overlay-yw2221_y/lava-14368401/bin/lava-installed-packages (debian)
188 00:43:35.931378 Updating /var/lib/lava/dispatcher/tmp/14368401/lava-overlay-yw2221_y/lava-14368401/bin/lava-os-build (debian)
189 00:43:35.931485 Creating /var/lib/lava/dispatcher/tmp/14368401/lava-overlay-yw2221_y/lava-14368401/environment
190 00:43:35.931569 LAVA metadata
191 00:43:35.931633 - LAVA_JOB_ID=14368401
192 00:43:35.931688 - LAVA_DISPATCHER_IP=192.168.201.1
193 00:43:35.931780 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:49) [common]
194 00:43:35.931835 skipped lava-vland-overlay
195 00:43:35.931902 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 00:43:35.931972 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:49) [common]
197 00:43:35.932024 skipped lava-multinode-overlay
198 00:43:35.932087 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 00:43:35.932155 start: 1.6.2.3 test-definition (timeout 00:09:49) [common]
200 00:43:35.932215 Loading test definitions
201 00:43:35.932301 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:49) [common]
202 00:43:35.932357 Using /lava-14368401 at stage 0
203 00:43:35.932621 uuid=14368401_1.6.2.3.1 testdef=None
204 00:43:35.932704 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 00:43:35.932778 start: 1.6.2.3.2 test-overlay (timeout 00:09:49) [common]
206 00:43:35.933172 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 00:43:35.933367 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:49) [common]
209 00:43:35.933868 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 00:43:35.934073 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:49) [common]
212 00:43:35.934561 runner path: /var/lib/lava/dispatcher/tmp/14368401/lava-overlay-yw2221_y/lava-14368401/0/tests/0_timesync-off test_uuid 14368401_1.6.2.3.1
213 00:43:35.934703 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 00:43:35.934902 start: 1.6.2.3.5 git-repo-action (timeout 00:09:49) [common]
216 00:43:35.934967 Using /lava-14368401 at stage 0
217 00:43:35.935053 Fetching tests from https://github.com/kernelci/test-definitions.git
218 00:43:35.935125 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/14368401/lava-overlay-yw2221_y/lava-14368401/0/tests/1_kselftest-tpm2'
219 00:43:38.099619 Running '/usr/bin/git checkout kernelci.org
220 00:43:38.180166 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/14368401/lava-overlay-yw2221_y/lava-14368401/0/tests/1_kselftest-tpm2/automated/linux/kselftest/kselftest.yaml
221 00:43:38.180518 uuid=14368401_1.6.2.3.5 testdef=None
222 00:43:38.180616 end: 1.6.2.3.5 git-repo-action (duration 00:00:02) [common]
224 00:43:38.180849 start: 1.6.2.3.6 test-overlay (timeout 00:09:47) [common]
225 00:43:38.181469 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 00:43:38.181668 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:47) [common]
228 00:43:38.182510 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 00:43:38.182720 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:47) [common]
231 00:43:38.183633 runner path: /var/lib/lava/dispatcher/tmp/14368401/lava-overlay-yw2221_y/lava-14368401/0/tests/1_kselftest-tpm2 test_uuid 14368401_1.6.2.3.5
232 00:43:38.183736 BOARD='mt8192-asurada-spherion-r0'
233 00:43:38.183795 BRANCH='cip'
234 00:43:38.183849 SKIPFILE='/dev/null'
235 00:43:38.183914 SKIP_INSTALL='True'
236 00:43:38.183963 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-24-g0315de64ea248/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 00:43:38.184013 TST_CASENAME=''
238 00:43:38.184061 TST_CMDFILES='tpm2'
239 00:43:38.184190 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 00:43:38.184368 Creating lava-test-runner.conf files
242 00:43:38.184421 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14368401/lava-overlay-yw2221_y/lava-14368401/0 for stage 0
243 00:43:38.184502 - 0_timesync-off
244 00:43:38.184560 - 1_kselftest-tpm2
245 00:43:38.184651 end: 1.6.2.3 test-definition (duration 00:00:02) [common]
246 00:43:38.184778 start: 1.6.2.4 compress-overlay (timeout 00:09:47) [common]
247 00:43:45.293681 end: 1.6.2.4 compress-overlay (duration 00:00:07) [common]
248 00:43:45.293815 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:40) [common]
249 00:43:45.293898 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 00:43:45.293980 end: 1.6.2 lava-overlay (duration 00:00:09) [common]
251 00:43:45.294059 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:40) [common]
252 00:43:45.449481 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 00:43:45.449628 start: 1.6.4 extract-modules (timeout 00:09:40) [common]
254 00:43:45.449707 extracting modules file /var/lib/lava/dispatcher/tmp/14368401/tftp-deploy-ngfchemh/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14368401/extract-nfsrootfs-dn_hmfv5
255 00:43:45.661938 extracting modules file /var/lib/lava/dispatcher/tmp/14368401/tftp-deploy-ngfchemh/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14368401/extract-overlay-ramdisk-4vupcklp/ramdisk
256 00:43:45.880480 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 00:43:45.880629 start: 1.6.5 apply-overlay-tftp (timeout 00:09:40) [common]
258 00:43:45.880726 [common] Applying overlay to NFS
259 00:43:45.880788 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14368401/compress-overlay-p7xlj0mc/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14368401/extract-nfsrootfs-dn_hmfv5
260 00:43:46.710382 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 00:43:46.710521 start: 1.6.6 configure-preseed-file (timeout 00:09:39) [common]
262 00:43:46.710604 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 00:43:46.710682 start: 1.6.7 compress-ramdisk (timeout 00:09:39) [common]
264 00:43:46.710749 Building ramdisk /var/lib/lava/dispatcher/tmp/14368401/extract-overlay-ramdisk-4vupcklp/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14368401/extract-overlay-ramdisk-4vupcklp/ramdisk
265 00:43:47.032857 >> 130405 blocks
266 00:43:49.108958 rename /var/lib/lava/dispatcher/tmp/14368401/extract-overlay-ramdisk-4vupcklp/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14368401/tftp-deploy-ngfchemh/ramdisk/ramdisk.cpio.gz
267 00:43:49.109121 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 00:43:49.109207 start: 1.6.8 prepare-kernel (timeout 00:09:36) [common]
269 00:43:49.109285 start: 1.6.8.1 prepare-fit (timeout 00:09:36) [common]
270 00:43:49.109361 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14368401/tftp-deploy-ngfchemh/kernel/Image']
271 00:44:02.422282 Returned 0 in 13 seconds
272 00:44:02.522788 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14368401/tftp-deploy-ngfchemh/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14368401/tftp-deploy-ngfchemh/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14368401/tftp-deploy-ngfchemh/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14368401/tftp-deploy-ngfchemh/kernel/image.itb
273 00:44:02.929181 output: FIT description: Kernel Image image with one or more FDT blobs
274 00:44:02.929322 output: Created: Sun Jun 16 01:44:02 2024
275 00:44:02.929386 output: Image 0 (kernel-1)
276 00:44:02.929445 output: Description:
277 00:44:02.929498 output: Created: Sun Jun 16 01:44:02 2024
278 00:44:02.929550 output: Type: Kernel Image
279 00:44:02.929602 output: Compression: lzma compressed
280 00:44:02.929657 output: Data Size: 13126376 Bytes = 12818.73 KiB = 12.52 MiB
281 00:44:02.929710 output: Architecture: AArch64
282 00:44:02.929759 output: OS: Linux
283 00:44:02.929812 output: Load Address: 0x00000000
284 00:44:02.929864 output: Entry Point: 0x00000000
285 00:44:02.929916 output: Hash algo: crc32
286 00:44:02.929972 output: Hash value: c791a20a
287 00:44:02.930024 output: Image 1 (fdt-1)
288 00:44:02.930077 output: Description: mt8192-asurada-spherion-r0
289 00:44:02.930129 output: Created: Sun Jun 16 01:44:02 2024
290 00:44:02.930179 output: Type: Flat Device Tree
291 00:44:02.930233 output: Compression: uncompressed
292 00:44:02.930286 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
293 00:44:02.930338 output: Architecture: AArch64
294 00:44:02.930389 output: Hash algo: crc32
295 00:44:02.930438 output: Hash value: 0f8e4d2e
296 00:44:02.930486 output: Image 2 (ramdisk-1)
297 00:44:02.930533 output: Description: unavailable
298 00:44:02.930579 output: Created: Sun Jun 16 01:44:02 2024
299 00:44:02.930627 output: Type: RAMDisk Image
300 00:44:02.930674 output: Compression: uncompressed
301 00:44:02.930721 output: Data Size: 18734341 Bytes = 18295.25 KiB = 17.87 MiB
302 00:44:02.930768 output: Architecture: AArch64
303 00:44:02.930815 output: OS: Linux
304 00:44:02.930861 output: Load Address: unavailable
305 00:44:02.930908 output: Entry Point: unavailable
306 00:44:02.930954 output: Hash algo: crc32
307 00:44:02.931000 output: Hash value: 646545db
308 00:44:02.931046 output: Default Configuration: 'conf-1'
309 00:44:02.931093 output: Configuration 0 (conf-1)
310 00:44:02.931139 output: Description: mt8192-asurada-spherion-r0
311 00:44:02.931186 output: Kernel: kernel-1
312 00:44:02.931233 output: Init Ramdisk: ramdisk-1
313 00:44:02.931279 output: FDT: fdt-1
314 00:44:02.931325 output: Loadables: kernel-1
315 00:44:02.931371 output:
316 00:44:02.931506 end: 1.6.8.1 prepare-fit (duration 00:00:14) [common]
317 00:44:02.931593 end: 1.6.8 prepare-kernel (duration 00:00:14) [common]
318 00:44:02.931686 end: 1.6 prepare-tftp-overlay (duration 00:00:30) [common]
319 00:44:02.931769 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:22) [common]
320 00:44:02.931836 No LXC device requested
321 00:44:02.931903 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 00:44:02.931977 start: 1.8 deploy-device-env (timeout 00:09:22) [common]
323 00:44:02.932044 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 00:44:02.932105 Checking files for TFTP limit of 4294967296 bytes.
325 00:44:02.932542 end: 1 tftp-deploy (duration 00:00:38) [common]
326 00:44:02.932638 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 00:44:02.932757 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 00:44:02.932863 substitutions:
329 00:44:02.932922 - {DTB}: 14368401/tftp-deploy-ngfchemh/dtb/mt8192-asurada-spherion-r0.dtb
330 00:44:02.932977 - {INITRD}: 14368401/tftp-deploy-ngfchemh/ramdisk/ramdisk.cpio.gz
331 00:44:02.933029 - {KERNEL}: 14368401/tftp-deploy-ngfchemh/kernel/Image
332 00:44:02.933078 - {LAVA_MAC}: None
333 00:44:02.933127 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/14368401/extract-nfsrootfs-dn_hmfv5
334 00:44:02.933176 - {NFS_SERVER_IP}: 192.168.201.1
335 00:44:02.933223 - {PRESEED_CONFIG}: None
336 00:44:02.933287 - {PRESEED_LOCAL}: None
337 00:44:02.933348 - {RAMDISK}: 14368401/tftp-deploy-ngfchemh/ramdisk/ramdisk.cpio.gz
338 00:44:02.933424 - {ROOT_PART}: None
339 00:44:02.933476 - {ROOT}: None
340 00:44:02.933523 - {SERVER_IP}: 192.168.201.1
341 00:44:02.933570 - {TEE}: None
342 00:44:02.933618 Parsed boot commands:
343 00:44:02.933664 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 00:44:02.933811 Parsed boot commands: tftpboot 192.168.201.1 14368401/tftp-deploy-ngfchemh/kernel/image.itb 14368401/tftp-deploy-ngfchemh/kernel/cmdline
345 00:44:02.933892 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 00:44:02.933965 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 00:44:02.934043 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 00:44:02.934119 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 00:44:02.934180 Not connected, no need to disconnect.
350 00:44:02.934244 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 00:44:02.934314 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 00:44:02.934373 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-8'
353 00:44:02.937612 Setting prompt string to ['lava-test: # ']
354 00:44:02.937926 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 00:44:02.938027 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 00:44:02.938116 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 00:44:02.938199 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 00:44:02.938391 Calling: ['/usr/local/bin/chromebook-reboot.sh', 'mt8192-asurada-spherion-r0-cbg-8']
359 00:44:16.741251 Returned 0 in 13 seconds
360 00:44:16.842322 end: 2.2.2.1 pdu-reboot (duration 00:00:14) [common]
362 00:44:16.843748 end: 2.2.2 reset-device (duration 00:00:14) [common]
363 00:44:16.844369 start: 2.2.3 depthcharge-start (timeout 00:04:46) [common]
364 00:44:16.844954 Setting prompt string to 'Starting depthcharge on Spherion...'
365 00:44:16.845370 Changing prompt to 'Starting depthcharge on Spherion...'
366 00:44:16.845851 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
367 00:44:16.846953 [Enter `^Ec?' for help]
368 00:44:16.847032
369 00:44:16.847108
370 00:44:16.847183 F0: 102B 0000
371 00:44:16.847254
372 00:44:16.847324 F3: 1001 0000 [0200]
373 00:44:16.847396
374 00:44:16.847467 F3: 1001 0000
375 00:44:16.847553
376 00:44:16.847637 F7: 102D 0000
377 00:44:16.847723
378 00:44:16.847809 F1: 0000 0000
379 00:44:16.847894
380 00:44:16.847979 V0: 0000 0000 [0001]
381 00:44:16.848065
382 00:44:16.848151 00: 0007 8000
383 00:44:16.848238
384 00:44:16.848321 01: 0000 0000
385 00:44:16.848406
386 00:44:16.848488 BP: 0C00 0209 [0000]
387 00:44:16.848571
388 00:44:16.848659 G0: 1182 0000
389 00:44:16.848743
390 00:44:16.848825 EC: 0000 0021 [4000]
391 00:44:16.848907
392 00:44:16.848989 S7: 0000 0000 [0000]
393 00:44:16.849071
394 00:44:16.849154 CC: 0000 0000 [0001]
395 00:44:16.849236
396 00:44:16.849317 T0: 0000 0040 [010F]
397 00:44:16.849400
398 00:44:16.849481 Jump to BL
399 00:44:16.849563
400 00:44:16.849645
401 00:44:16.849727
402 00:44:16.849810 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
403 00:44:16.849897 ARM64: Exception handlers installed.
404 00:44:16.849981 ARM64: Testing exception
405 00:44:16.850063 ARM64: Done test exception
406 00:44:16.850146 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
407 00:44:16.850229 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
408 00:44:16.850315 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
409 00:44:16.850398 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
410 00:44:16.850482 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
411 00:44:16.850565 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
412 00:44:16.850648 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
413 00:44:16.850731 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
414 00:44:16.850814 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
415 00:44:16.850898 WDT: Last reset was cold boot
416 00:44:16.850981 SPI1(PAD0) initialized at 2873684 Hz
417 00:44:16.851064 SPI5(PAD0) initialized at 992727 Hz
418 00:44:16.851147 VBOOT: Loading verstage.
419 00:44:16.851229 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
420 00:44:16.851312 FMAP: Found "FLASH" version 1.1 at 0x20000.
421 00:44:16.851396 FMAP: base = 0x0 size = 0x800000 #areas = 25
422 00:44:16.851479 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
423 00:44:16.851588 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
424 00:44:16.851686 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
425 00:44:16.851771 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
426 00:44:16.851854
427 00:44:16.851936
428 00:44:16.852019 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
429 00:44:16.852104 ARM64: Exception handlers installed.
430 00:44:16.852187 ARM64: Testing exception
431 00:44:16.852269 ARM64: Done test exception
432 00:44:16.852351 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
433 00:44:16.852435 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
434 00:44:16.852517 Probing TPM: . done!
435 00:44:16.852599 TPM ready after 0 ms
436 00:44:16.852721 Connected to device vid:did:rid of 1ae0:0028:00
437 00:44:16.852805 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
438 00:44:16.852889 Initialized TPM device CR50 revision 0
439 00:44:16.852972 tlcl_send_startup: Startup return code is 0
440 00:44:16.853056 TPM: setup succeeded
441 00:44:16.853139 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
442 00:44:16.853222 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
443 00:44:16.853306 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
444 00:44:16.853389 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 00:44:16.853472 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
446 00:44:16.853555 in-header: 03 07 00 00 08 00 00 00
447 00:44:16.853637 in-data: aa e4 47 04 13 02 00 00
448 00:44:16.853720 Chrome EC: UHEPI supported
449 00:44:16.853802 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
450 00:44:16.853886 in-header: 03 a9 00 00 08 00 00 00
451 00:44:16.853969 in-data: 84 60 60 08 00 00 00 00
452 00:44:16.854051 Phase 1
453 00:44:16.854134 FMAP: area GBB found @ 3f5000 (12032 bytes)
454 00:44:16.854217 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
455 00:44:16.854301 VB2:vb2_check_recovery() Recovery was requested manually
456 00:44:16.854383 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x7
457 00:44:16.854467 Recovery requested (1009000e)
458 00:44:16.854549 TPM: Extending digest for VBOOT: boot mode into PCR 0
459 00:44:16.854632 tlcl_extend: response is 0
460 00:44:16.854715 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
461 00:44:16.854798 tlcl_extend: response is 0
462 00:44:16.854880 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
463 00:44:16.854964 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
464 00:44:16.855047 BS: bootblock times (exec / console): total (unknown) / 148 ms
465 00:44:16.855130
466 00:44:16.855212
467 00:44:16.855294 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
468 00:44:16.855378 ARM64: Exception handlers installed.
469 00:44:16.855460 ARM64: Testing exception
470 00:44:16.855542 ARM64: Done test exception
471 00:44:16.855625 pmic_efuse_setting: Set efuses in 11 msecs
472 00:44:16.855707 pmwrap_interface_init: Select PMIF_VLD_RDY
473 00:44:16.855790 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
474 00:44:16.855872 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
475 00:44:16.856146 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
476 00:44:16.856261 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
477 00:44:16.856370 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
478 00:44:16.856476 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
479 00:44:16.856582 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
480 00:44:16.856727 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
481 00:44:16.856835 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
482 00:44:16.856941 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
483 00:44:16.857049 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
484 00:44:16.857154 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
485 00:44:16.857261 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
486 00:44:16.857367 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
487 00:44:16.857454 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
488 00:44:16.857531 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
489 00:44:16.857608 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
490 00:44:16.857724 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
491 00:44:16.857808 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
492 00:44:16.857891 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
493 00:44:16.857974 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
494 00:44:16.858057 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
495 00:44:16.858141 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
496 00:44:16.858223 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
497 00:44:16.858306 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
498 00:44:16.858388 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
499 00:44:16.858472 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
500 00:44:16.858555 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
501 00:44:16.858638 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
502 00:44:16.858721 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
503 00:44:16.858803 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
504 00:44:16.858886 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
505 00:44:16.858969 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
506 00:44:16.859051 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
507 00:44:16.859134 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
508 00:44:16.859216 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
509 00:44:16.859299 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
510 00:44:16.859382 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
511 00:44:16.859467 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
512 00:44:16.859550 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
513 00:44:16.859633 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
514 00:44:16.859716 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
515 00:44:16.859799 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
516 00:44:16.859881 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
517 00:44:16.859967 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
518 00:44:16.860045 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
519 00:44:16.860121 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
520 00:44:16.860196 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
521 00:44:16.860273 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
522 00:44:16.860348 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
523 00:44:16.860423 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
524 00:44:16.860499 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x6b6d 0x5bf0 0x8100 0x4c 0xf0f 0x9248
525 00:44:16.860577 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
526 00:44:16.860674 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
527 00:44:16.860781 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
528 00:44:16.860860 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
529 00:44:16.860939 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
530 00:44:16.861016 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
531 00:44:16.861094 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 00:44:16.861172 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x5
533 00:44:16.861250 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
534 00:44:16.861328 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
535 00:44:16.861405 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
536 00:44:16.861482 [RTC]rtc_get_frequency_meter,154: input=15, output=794
537 00:44:16.861560 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
538 00:44:16.861637 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
539 00:44:16.861714 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
540 00:44:16.861791 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
541 00:44:16.861868 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
542 00:44:16.861945 ADC[4]: Raw value=895191 ID=7
543 00:44:16.862021 ADC[3]: Raw value=212700 ID=1
544 00:44:16.862097 RAM Code: 0x71
545 00:44:16.862174 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
546 00:44:16.862252 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
547 00:44:16.862523 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
548 00:44:16.862610 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
549 00:44:16.862688 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
550 00:44:16.862766 in-header: 03 07 00 00 08 00 00 00
551 00:44:16.862843 in-data: aa e4 47 04 13 02 00 00
552 00:44:16.862919 Chrome EC: UHEPI supported
553 00:44:16.862997 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
554 00:44:16.863075 in-header: 03 a9 00 00 08 00 00 00
555 00:44:16.863151 in-data: 84 60 60 08 00 00 00 00
556 00:44:16.863228 MRC: failed to locate region type 0.
557 00:44:16.863306 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
558 00:44:16.863383 DRAM-K: Running full calibration
559 00:44:16.863460 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
560 00:44:16.863536 header.status = 0x0
561 00:44:16.863613 header.version = 0x6 (expected: 0x6)
562 00:44:16.863689 header.size = 0xd00 (expected: 0xd00)
563 00:44:16.863765 header.flags = 0x0
564 00:44:16.863842 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
565 00:44:16.863920 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
566 00:44:16.863998 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
567 00:44:16.864074 dram_init: ddr_geometry: 2
568 00:44:16.864150 [EMI] MDL number = 2
569 00:44:16.864226 [EMI] Get MDL freq = 0
570 00:44:16.864302 dram_init: ddr_type: 0
571 00:44:16.864378 is_discrete_lpddr4: 1
572 00:44:16.864454 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
573 00:44:16.864530
574 00:44:16.864605
575 00:44:16.864678 [Bian_co] ETT version 0.0.0.1
576 00:44:16.864729 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
577 00:44:16.864778
578 00:44:16.864826 dramc_set_vcore_voltage set vcore to 650000
579 00:44:16.864874 Read voltage for 800, 4
580 00:44:16.864923 Vio18 = 0
581 00:44:16.864971 Vcore = 650000
582 00:44:16.865020 Vdram = 0
583 00:44:16.865069 Vddq = 0
584 00:44:16.865117 Vmddr = 0
585 00:44:16.865165 dram_init: config_dvfs: 1
586 00:44:16.865215 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
587 00:44:16.865264 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
588 00:44:16.865313 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=9
589 00:44:16.865361 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=9
590 00:44:16.865410 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
591 00:44:16.865460 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
592 00:44:16.865508 MEM_TYPE=3, freq_sel=18
593 00:44:16.865556 sv_algorithm_assistance_LP4_1600
594 00:44:16.865604 ============ PULL DRAM RESETB DOWN ============
595 00:44:16.865655 ========== PULL DRAM RESETB DOWN end =========
596 00:44:16.865703 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
597 00:44:16.865752 ===================================
598 00:44:16.865800 LPDDR4 DRAM CONFIGURATION
599 00:44:16.865848 ===================================
600 00:44:16.865896 EX_ROW_EN[0] = 0x0
601 00:44:16.865944 EX_ROW_EN[1] = 0x0
602 00:44:16.865992 LP4Y_EN = 0x0
603 00:44:16.866040 WORK_FSP = 0x0
604 00:44:16.866087 WL = 0x2
605 00:44:16.866135 RL = 0x2
606 00:44:16.866182 BL = 0x2
607 00:44:16.866229 RPST = 0x0
608 00:44:16.866276 RD_PRE = 0x0
609 00:44:16.866324 WR_PRE = 0x1
610 00:44:16.866372 WR_PST = 0x0
611 00:44:16.866420 DBI_WR = 0x0
612 00:44:16.866468 DBI_RD = 0x0
613 00:44:16.866515 OTF = 0x1
614 00:44:16.866563 ===================================
615 00:44:16.866612 ===================================
616 00:44:16.866660 ANA top config
617 00:44:16.866707 ===================================
618 00:44:16.866755 DLL_ASYNC_EN = 0
619 00:44:16.866802 ALL_SLAVE_EN = 1
620 00:44:16.866850 NEW_RANK_MODE = 1
621 00:44:16.866899 DLL_IDLE_MODE = 1
622 00:44:16.866947 LP45_APHY_COMB_EN = 1
623 00:44:16.866994 TX_ODT_DIS = 1
624 00:44:16.867042 NEW_8X_MODE = 1
625 00:44:16.867091 ===================================
626 00:44:16.867139 ===================================
627 00:44:16.867186 data_rate = 1600
628 00:44:16.867234 CKR = 1
629 00:44:16.867282 DQ_P2S_RATIO = 8
630 00:44:16.867330 ===================================
631 00:44:16.867378 CA_P2S_RATIO = 8
632 00:44:16.867425 DQ_CA_OPEN = 0
633 00:44:16.867473 DQ_SEMI_OPEN = 0
634 00:44:16.867521 CA_SEMI_OPEN = 0
635 00:44:16.867577 CA_FULL_RATE = 0
636 00:44:16.867637 DQ_CKDIV4_EN = 1
637 00:44:16.867726 CA_CKDIV4_EN = 1
638 00:44:16.867807 CA_PREDIV_EN = 0
639 00:44:16.867884 PH8_DLY = 0
640 00:44:16.867961 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
641 00:44:16.868037 DQ_AAMCK_DIV = 4
642 00:44:16.868113 CA_AAMCK_DIV = 4
643 00:44:16.868190 CA_ADMCK_DIV = 4
644 00:44:16.868267 DQ_TRACK_CA_EN = 0
645 00:44:16.868343 CA_PICK = 800
646 00:44:16.868420 CA_MCKIO = 800
647 00:44:16.868497 MCKIO_SEMI = 0
648 00:44:16.868573 PLL_FREQ = 3068
649 00:44:16.868655 DQ_UI_PI_RATIO = 32
650 00:44:16.868708 CA_UI_PI_RATIO = 0
651 00:44:16.868756 ===================================
652 00:44:16.868805 ===================================
653 00:44:16.868855 memory_type:LPDDR4
654 00:44:16.868903 GP_NUM : 10
655 00:44:16.868951 SRAM_EN : 1
656 00:44:16.868999 MD32_EN : 0
657 00:44:16.869047 ===================================
658 00:44:16.869094 [ANA_INIT] >>>>>>>>>>>>>>
659 00:44:16.869142 <<<<<< [CONFIGURE PHASE]: ANA_TX
660 00:44:16.869193 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
661 00:44:16.869241 ===================================
662 00:44:16.869290 data_rate = 1600,PCW = 0X7600
663 00:44:16.869338 ===================================
664 00:44:16.869386 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
665 00:44:16.869434 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
666 00:44:16.869482 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
667 00:44:16.869740 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
668 00:44:16.869857 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
669 00:44:16.869967 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
670 00:44:16.870075 [ANA_INIT] flow start
671 00:44:16.870184 [ANA_INIT] PLL >>>>>>>>
672 00:44:16.870292 [ANA_INIT] PLL <<<<<<<<
673 00:44:16.870400 [ANA_INIT] MIDPI >>>>>>>>
674 00:44:16.870508 [ANA_INIT] MIDPI <<<<<<<<
675 00:44:16.870617 [ANA_INIT] DLL >>>>>>>>
676 00:44:16.870726 [ANA_INIT] flow end
677 00:44:16.870833 ============ LP4 DIFF to SE enter ============
678 00:44:16.870942 ============ LP4 DIFF to SE exit ============
679 00:44:16.871025 [ANA_INIT] <<<<<<<<<<<<<
680 00:44:16.871103 [Flow] Enable top DCM control >>>>>
681 00:44:16.871181 [Flow] Enable top DCM control <<<<<
682 00:44:16.871257 Enable DLL master slave shuffle
683 00:44:16.871335 ==============================================================
684 00:44:16.871412 Gating Mode config
685 00:44:16.871490 ==============================================================
686 00:44:16.871567 Config description:
687 00:44:16.871646 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
688 00:44:16.871717 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
689 00:44:16.871786 SELPH_MODE 0: By rank 1: By Phase
690 00:44:16.871853 ==============================================================
691 00:44:16.871920 GAT_TRACK_EN = 1
692 00:44:16.871986 RX_GATING_MODE = 2
693 00:44:16.872052 RX_GATING_TRACK_MODE = 2
694 00:44:16.872136 SELPH_MODE = 1
695 00:44:16.872221 PICG_EARLY_EN = 1
696 00:44:16.872305 VALID_LAT_VALUE = 1
697 00:44:16.872389 ==============================================================
698 00:44:16.872474 Enter into Gating configuration >>>>
699 00:44:16.872559 Exit from Gating configuration <<<<
700 00:44:16.872649 Enter into DVFS_PRE_config >>>>>
701 00:44:16.872736 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
702 00:44:16.872825 Exit from DVFS_PRE_config <<<<<
703 00:44:16.872910 Enter into PICG configuration >>>>
704 00:44:16.872995 Exit from PICG configuration <<<<
705 00:44:16.873079 [RX_INPUT] configuration >>>>>
706 00:44:16.873164 [RX_INPUT] configuration <<<<<
707 00:44:16.873248 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
708 00:44:16.873332 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
709 00:44:16.873418 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
710 00:44:16.873503 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
711 00:44:16.873588 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
712 00:44:16.873673 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
713 00:44:16.873758 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
714 00:44:16.873843 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
715 00:44:16.873928 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
716 00:44:16.874013 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
717 00:44:16.874098 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
718 00:44:16.874182 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
719 00:44:16.874266 ===================================
720 00:44:16.874351 LPDDR4 DRAM CONFIGURATION
721 00:44:16.874435 ===================================
722 00:44:16.874519 EX_ROW_EN[0] = 0x0
723 00:44:16.874604 EX_ROW_EN[1] = 0x0
724 00:44:16.874688 LP4Y_EN = 0x0
725 00:44:16.874772 WORK_FSP = 0x0
726 00:44:16.874855 WL = 0x2
727 00:44:16.874939 RL = 0x2
728 00:44:16.875023 BL = 0x2
729 00:44:16.875107 RPST = 0x0
730 00:44:16.875191 RD_PRE = 0x0
731 00:44:16.875275 WR_PRE = 0x1
732 00:44:16.875359 WR_PST = 0x0
733 00:44:16.875443 DBI_WR = 0x0
734 00:44:16.875527 DBI_RD = 0x0
735 00:44:16.875610 OTF = 0x1
736 00:44:16.875707 ===================================
737 00:44:16.875790 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
738 00:44:16.875873 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
739 00:44:16.875965 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
740 00:44:16.876048 ===================================
741 00:44:16.876132 LPDDR4 DRAM CONFIGURATION
742 00:44:16.876214 ===================================
743 00:44:16.876297 EX_ROW_EN[0] = 0x10
744 00:44:16.876379 EX_ROW_EN[1] = 0x0
745 00:44:16.876462 LP4Y_EN = 0x0
746 00:44:16.876543 WORK_FSP = 0x0
747 00:44:16.876625 WL = 0x2
748 00:44:16.876748 RL = 0x2
749 00:44:16.876830 BL = 0x2
750 00:44:16.876913 RPST = 0x0
751 00:44:16.876996 RD_PRE = 0x0
752 00:44:16.877078 WR_PRE = 0x1
753 00:44:16.877161 WR_PST = 0x0
754 00:44:16.877243 DBI_WR = 0x0
755 00:44:16.877325 DBI_RD = 0x0
756 00:44:16.877407 OTF = 0x1
757 00:44:16.877490 ===================================
758 00:44:16.877574 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
759 00:44:16.877657 nWR fixed to 40
760 00:44:16.877741 [ModeRegInit_LP4] CH0 RK0
761 00:44:16.877823 [ModeRegInit_LP4] CH0 RK1
762 00:44:16.877905 [ModeRegInit_LP4] CH1 RK0
763 00:44:16.877987 [ModeRegInit_LP4] CH1 RK1
764 00:44:16.878069 match AC timing 13
765 00:44:16.878152 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
766 00:44:16.878235 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
767 00:44:16.878318 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
768 00:44:16.878401 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
769 00:44:16.878484 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
770 00:44:16.878566 [EMI DOE] emi_dcm 0
771 00:44:16.878648 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
772 00:44:16.878731 ==
773 00:44:16.878814 Dram Type= 6, Freq= 0, CH_0, rank 0
774 00:44:16.878896 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
775 00:44:16.878979 ==
776 00:44:16.879255 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
777 00:44:16.879338 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
778 00:44:16.879422 [CA 0] Center 38 (7~69) winsize 63
779 00:44:16.879506 [CA 1] Center 37 (7~68) winsize 62
780 00:44:16.879589 [CA 2] Center 35 (5~66) winsize 62
781 00:44:16.879672 [CA 3] Center 35 (5~66) winsize 62
782 00:44:16.879754 [CA 4] Center 34 (4~65) winsize 62
783 00:44:16.879837 [CA 5] Center 34 (4~65) winsize 62
784 00:44:16.879919
785 00:44:16.880002 [CmdBusTrainingLP45] Vref(ca) range 1: 34
786 00:44:16.880085
787 00:44:16.880167 [CATrainingPosCal] consider 1 rank data
788 00:44:16.880250 u2DelayCellTimex100 = 270/100 ps
789 00:44:16.880332 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
790 00:44:16.880415 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
791 00:44:16.880497 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
792 00:44:16.880580 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
793 00:44:16.880668 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
794 00:44:16.880752 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
795 00:44:16.880834
796 00:44:16.880916 CA PerBit enable=1, Macro0, CA PI delay=34
797 00:44:16.880999
798 00:44:16.881081 [CBTSetCACLKResult] CA Dly = 34
799 00:44:16.881163 CS Dly: 6 (0~37)
800 00:44:16.881246 ==
801 00:44:16.881328 Dram Type= 6, Freq= 0, CH_0, rank 1
802 00:44:16.881411 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
803 00:44:16.881494 ==
804 00:44:16.881576 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
805 00:44:16.881662 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
806 00:44:16.881744 [CA 0] Center 38 (7~69) winsize 63
807 00:44:16.881828 [CA 1] Center 38 (7~69) winsize 63
808 00:44:16.881910 [CA 2] Center 35 (5~66) winsize 62
809 00:44:16.882004 [CA 3] Center 35 (5~66) winsize 62
810 00:44:16.882087 [CA 4] Center 34 (4~65) winsize 62
811 00:44:16.882170 [CA 5] Center 34 (4~65) winsize 62
812 00:44:16.882252
813 00:44:16.882334 [CmdBusTrainingLP45] Vref(ca) range 1: 32
814 00:44:16.882417
815 00:44:16.882499 [CATrainingPosCal] consider 2 rank data
816 00:44:16.882581 u2DelayCellTimex100 = 270/100 ps
817 00:44:16.882664 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
818 00:44:16.882747 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
819 00:44:16.882829 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
820 00:44:16.882911 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
821 00:44:16.882994 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
822 00:44:16.883076 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
823 00:44:16.883158
824 00:44:16.883241 CA PerBit enable=1, Macro0, CA PI delay=34
825 00:44:16.883323
826 00:44:16.883405 [CBTSetCACLKResult] CA Dly = 34
827 00:44:16.883487 CS Dly: 6 (0~38)
828 00:44:16.883569
829 00:44:16.883651 ----->DramcWriteLeveling(PI) begin...
830 00:44:16.883735 ==
831 00:44:16.883817 Dram Type= 6, Freq= 0, CH_0, rank 0
832 00:44:16.883900 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
833 00:44:16.883982 ==
834 00:44:16.884064 Write leveling (Byte 0): 33 => 33
835 00:44:16.884148 Write leveling (Byte 1): 28 => 28
836 00:44:16.884231 DramcWriteLeveling(PI) end<-----
837 00:44:16.884314
838 00:44:16.884396 ==
839 00:44:16.884479 Dram Type= 6, Freq= 0, CH_0, rank 0
840 00:44:16.884561 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
841 00:44:16.884650 ==
842 00:44:16.884771 [Gating] SW mode calibration
843 00:44:16.884854 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
844 00:44:16.884937 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
845 00:44:16.885020 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
846 00:44:16.885103 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
847 00:44:16.885185 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
848 00:44:16.885268 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
849 00:44:16.885351 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
850 00:44:16.885433 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
851 00:44:16.885516 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
852 00:44:16.885598 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
853 00:44:16.885681 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
854 00:44:16.885763 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
855 00:44:16.885845 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 00:44:16.885928 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 00:44:16.886010 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 00:44:16.886092 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 00:44:16.886174 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 00:44:16.886257 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 00:44:16.886339 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 00:44:16.886421 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 00:44:16.886504 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
864 00:44:16.886587 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
865 00:44:16.886669 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 00:44:16.886752 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 00:44:16.886834 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 00:44:16.886917 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 00:44:16.887000 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 00:44:16.887083 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
871 00:44:16.887165 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
872 00:44:16.887248 0 9 12 | B1->B0 | 2626 3333 | 0 1 | (0 0) (0 0)
873 00:44:16.887330 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
874 00:44:16.887413 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
875 00:44:16.887495 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
876 00:44:16.887578 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
877 00:44:16.887661 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
878 00:44:16.887744 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
879 00:44:16.887826 0 10 8 | B1->B0 | 3434 3232 | 1 0 | (1 0) (0 1)
880 00:44:16.887909 0 10 12 | B1->B0 | 3030 2626 | 0 0 | (0 1) (0 0)
881 00:44:16.887992 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
882 00:44:16.888278 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
883 00:44:16.888396 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
884 00:44:16.888507 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
885 00:44:16.888614 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
886 00:44:16.888755 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
887 00:44:16.888863 0 11 8 | B1->B0 | 2424 2d2d | 0 0 | (0 0) (1 1)
888 00:44:16.888970 0 11 12 | B1->B0 | 3232 3f3f | 0 0 | (1 1) (0 0)
889 00:44:16.889076 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
890 00:44:16.889182 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
891 00:44:16.889290 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
892 00:44:16.889404 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
893 00:44:16.889503 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
894 00:44:16.889581 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
895 00:44:16.889657 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
896 00:44:16.889733 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
897 00:44:16.889809 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
898 00:44:16.889884 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
899 00:44:16.889991 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
900 00:44:16.890122 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
901 00:44:16.890207 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
902 00:44:16.890284 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
903 00:44:16.890360 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
904 00:44:16.890436 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 00:44:16.890512 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 00:44:16.890587 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 00:44:16.890663 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 00:44:16.890739 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 00:44:16.890815 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 00:44:16.890890 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 00:44:16.890966 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
912 00:44:16.891041 Total UI for P1: 0, mck2ui 16
913 00:44:16.891117 best dqsien dly found for B0: ( 0, 14, 6)
914 00:44:16.891193 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
915 00:44:16.891268 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
916 00:44:16.891343 Total UI for P1: 0, mck2ui 16
917 00:44:16.891419 best dqsien dly found for B1: ( 0, 14, 12)
918 00:44:16.891494 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
919 00:44:16.891570 best DQS1 dly(MCK, UI, PI) = (0, 14, 12)
920 00:44:16.891645
921 00:44:16.891721 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
922 00:44:16.891796 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 12)
923 00:44:16.891871 [Gating] SW calibration Done
924 00:44:16.891963 ==
925 00:44:16.892084 Dram Type= 6, Freq= 0, CH_0, rank 0
926 00:44:16.892176 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
927 00:44:16.892265 ==
928 00:44:16.892357 RX Vref Scan: 0
929 00:44:16.892444
930 00:44:16.892519 RX Vref 0 -> 0, step: 1
931 00:44:16.892593
932 00:44:16.892698 RX Delay -130 -> 252, step: 16
933 00:44:16.892750 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
934 00:44:16.892798 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
935 00:44:16.892846 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
936 00:44:16.892893 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
937 00:44:16.892941 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
938 00:44:16.892987 iDelay=222, Bit 5, Center 61 (-66 ~ 189) 256
939 00:44:16.893035 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
940 00:44:16.893082 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
941 00:44:16.893130 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
942 00:44:16.893177 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
943 00:44:16.893224 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
944 00:44:16.893272 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
945 00:44:16.893319 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
946 00:44:16.893366 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
947 00:44:16.893414 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
948 00:44:16.893538 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
949 00:44:16.893616 ==
950 00:44:16.893679 Dram Type= 6, Freq= 0, CH_0, rank 0
951 00:44:16.893726 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
952 00:44:16.893774 ==
953 00:44:16.893821 DQS Delay:
954 00:44:16.893868 DQS0 = 0, DQS1 = 0
955 00:44:16.893916 DQM Delay:
956 00:44:16.893962 DQM0 = 81, DQM1 = 70
957 00:44:16.894009 DQ Delay:
958 00:44:16.894055 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =77
959 00:44:16.894102 DQ4 =85, DQ5 =61, DQ6 =85, DQ7 =93
960 00:44:16.894150 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =61
961 00:44:16.894197 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
962 00:44:16.894244
963 00:44:16.894291
964 00:44:16.894354 ==
965 00:44:16.894402 Dram Type= 6, Freq= 0, CH_0, rank 0
966 00:44:16.894479 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
967 00:44:16.894527 ==
968 00:44:16.894587
969 00:44:16.894662
970 00:44:16.894737 TX Vref Scan disable
971 00:44:16.894784 == TX Byte 0 ==
972 00:44:16.894831 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
973 00:44:16.894879 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
974 00:44:16.894926 == TX Byte 1 ==
975 00:44:16.894974 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
976 00:44:16.895022 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
977 00:44:16.895068 ==
978 00:44:16.895114 Dram Type= 6, Freq= 0, CH_0, rank 0
979 00:44:16.895161 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
980 00:44:16.895209 ==
981 00:44:16.895256 TX Vref=22, minBit 11, minWin=26, winSum=439
982 00:44:16.895303 TX Vref=24, minBit 1, minWin=27, winSum=444
983 00:44:16.895350 TX Vref=26, minBit 4, minWin=27, winSum=443
984 00:44:16.895398 TX Vref=28, minBit 4, minWin=27, winSum=445
985 00:44:16.895445 TX Vref=30, minBit 11, minWin=27, winSum=446
986 00:44:16.895492 TX Vref=32, minBit 4, minWin=27, winSum=444
987 00:44:16.895538 [TxChooseVref] Worse bit 11, Min win 27, Win sum 446, Final Vref 30
988 00:44:16.895585
989 00:44:16.895632 Final TX Range 1 Vref 30
990 00:44:16.895680
991 00:44:16.895740 ==
992 00:44:16.895802 Dram Type= 6, Freq= 0, CH_0, rank 0
993 00:44:16.896057 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
994 00:44:16.896141 ==
995 00:44:16.896216
996 00:44:16.896291
997 00:44:16.896374 TX Vref Scan disable
998 00:44:16.896426 == TX Byte 0 ==
999 00:44:16.896490 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1000 00:44:16.896539 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1001 00:44:16.896587 == TX Byte 1 ==
1002 00:44:16.896636 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1003 00:44:16.896716 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1004 00:44:16.896764
1005 00:44:16.896812 [DATLAT]
1006 00:44:16.896859 Freq=800, CH0 RK0
1007 00:44:16.896907
1008 00:44:16.896955 DATLAT Default: 0xa
1009 00:44:16.897003 0, 0xFFFF, sum = 0
1010 00:44:16.897052 1, 0xFFFF, sum = 0
1011 00:44:16.897101 2, 0xFFFF, sum = 0
1012 00:44:16.897150 3, 0xFFFF, sum = 0
1013 00:44:16.897198 4, 0xFFFF, sum = 0
1014 00:44:16.897246 5, 0xFFFF, sum = 0
1015 00:44:16.897294 6, 0xFFFF, sum = 0
1016 00:44:16.897341 7, 0xFFFF, sum = 0
1017 00:44:16.897390 8, 0xFFFF, sum = 0
1018 00:44:16.897438 9, 0x0, sum = 1
1019 00:44:16.897486 10, 0x0, sum = 2
1020 00:44:16.897534 11, 0x0, sum = 3
1021 00:44:16.897582 12, 0x0, sum = 4
1022 00:44:16.897632 best_step = 10
1023 00:44:16.897680
1024 00:44:16.897727 ==
1025 00:44:16.897774 Dram Type= 6, Freq= 0, CH_0, rank 0
1026 00:44:16.897821 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1027 00:44:16.897868 ==
1028 00:44:16.897915 RX Vref Scan: 1
1029 00:44:16.897962
1030 00:44:16.898008 Set Vref Range= 32 -> 127
1031 00:44:16.898094
1032 00:44:16.898140 RX Vref 32 -> 127, step: 1
1033 00:44:16.898188
1034 00:44:16.898235 RX Delay -111 -> 252, step: 8
1035 00:44:16.898282
1036 00:44:16.898346 Set Vref, RX VrefLevel [Byte0]: 32
1037 00:44:16.898397 [Byte1]: 32
1038 00:44:16.898445
1039 00:44:16.898492 Set Vref, RX VrefLevel [Byte0]: 33
1040 00:44:16.898539 [Byte1]: 33
1041 00:44:16.898585
1042 00:44:16.898632 Set Vref, RX VrefLevel [Byte0]: 34
1043 00:44:16.898679 [Byte1]: 34
1044 00:44:16.898726
1045 00:44:16.898774 Set Vref, RX VrefLevel [Byte0]: 35
1046 00:44:16.898820 [Byte1]: 35
1047 00:44:16.898868
1048 00:44:16.898914 Set Vref, RX VrefLevel [Byte0]: 36
1049 00:44:16.898961 [Byte1]: 36
1050 00:44:16.899007
1051 00:44:16.899053 Set Vref, RX VrefLevel [Byte0]: 37
1052 00:44:16.899100 [Byte1]: 37
1053 00:44:16.899147
1054 00:44:16.899193 Set Vref, RX VrefLevel [Byte0]: 38
1055 00:44:16.899251 [Byte1]: 38
1056 00:44:16.899304
1057 00:44:16.899351 Set Vref, RX VrefLevel [Byte0]: 39
1058 00:44:16.899398 [Byte1]: 39
1059 00:44:16.899445
1060 00:44:16.899491 Set Vref, RX VrefLevel [Byte0]: 40
1061 00:44:16.899538 [Byte1]: 40
1062 00:44:16.899584
1063 00:44:16.899631 Set Vref, RX VrefLevel [Byte0]: 41
1064 00:44:16.899678 [Byte1]: 41
1065 00:44:16.899726
1066 00:44:16.899772 Set Vref, RX VrefLevel [Byte0]: 42
1067 00:44:16.899819 [Byte1]: 42
1068 00:44:16.899866
1069 00:44:16.899913 Set Vref, RX VrefLevel [Byte0]: 43
1070 00:44:16.899960 [Byte1]: 43
1071 00:44:16.900022
1072 00:44:16.900112 Set Vref, RX VrefLevel [Byte0]: 44
1073 00:44:16.900160 [Byte1]: 44
1074 00:44:16.900207
1075 00:44:16.900254 Set Vref, RX VrefLevel [Byte0]: 45
1076 00:44:16.900301 [Byte1]: 45
1077 00:44:16.900348
1078 00:44:16.900418 Set Vref, RX VrefLevel [Byte0]: 46
1079 00:44:16.900498 [Byte1]: 46
1080 00:44:16.900579
1081 00:44:16.900658 Set Vref, RX VrefLevel [Byte0]: 47
1082 00:44:16.900737 [Byte1]: 47
1083 00:44:16.900785
1084 00:44:16.900832 Set Vref, RX VrefLevel [Byte0]: 48
1085 00:44:16.900879 [Byte1]: 48
1086 00:44:16.900926
1087 00:44:16.900974 Set Vref, RX VrefLevel [Byte0]: 49
1088 00:44:16.901023 [Byte1]: 49
1089 00:44:16.901070
1090 00:44:16.901117 Set Vref, RX VrefLevel [Byte0]: 50
1091 00:44:16.901165 [Byte1]: 50
1092 00:44:16.901211
1093 00:44:16.901258 Set Vref, RX VrefLevel [Byte0]: 51
1094 00:44:16.901305 [Byte1]: 51
1095 00:44:16.901352
1096 00:44:16.901399 Set Vref, RX VrefLevel [Byte0]: 52
1097 00:44:16.901446 [Byte1]: 52
1098 00:44:16.901492
1099 00:44:16.901539 Set Vref, RX VrefLevel [Byte0]: 53
1100 00:44:16.901586 [Byte1]: 53
1101 00:44:16.901634
1102 00:44:16.901681 Set Vref, RX VrefLevel [Byte0]: 54
1103 00:44:16.901728 [Byte1]: 54
1104 00:44:16.901775
1105 00:44:16.901822 Set Vref, RX VrefLevel [Byte0]: 55
1106 00:44:16.901869 [Byte1]: 55
1107 00:44:16.901916
1108 00:44:16.901963 Set Vref, RX VrefLevel [Byte0]: 56
1109 00:44:16.902009 [Byte1]: 56
1110 00:44:16.902056
1111 00:44:16.902136 Set Vref, RX VrefLevel [Byte0]: 57
1112 00:44:16.902183 [Byte1]: 57
1113 00:44:16.902230
1114 00:44:16.902277 Set Vref, RX VrefLevel [Byte0]: 58
1115 00:44:16.902324 [Byte1]: 58
1116 00:44:16.902371
1117 00:44:16.902419 Set Vref, RX VrefLevel [Byte0]: 59
1118 00:44:16.902465 [Byte1]: 59
1119 00:44:16.902512
1120 00:44:16.902558 Set Vref, RX VrefLevel [Byte0]: 60
1121 00:44:16.902605 [Byte1]: 60
1122 00:44:16.902652
1123 00:44:16.902699 Set Vref, RX VrefLevel [Byte0]: 61
1124 00:44:16.902746 [Byte1]: 61
1125 00:44:16.902793
1126 00:44:16.902839 Set Vref, RX VrefLevel [Byte0]: 62
1127 00:44:16.902886 [Byte1]: 62
1128 00:44:16.902932
1129 00:44:16.902978 Set Vref, RX VrefLevel [Byte0]: 63
1130 00:44:16.903025 [Byte1]: 63
1131 00:44:16.903072
1132 00:44:16.903118 Set Vref, RX VrefLevel [Byte0]: 64
1133 00:44:16.903165 [Byte1]: 64
1134 00:44:16.903212
1135 00:44:16.903258 Set Vref, RX VrefLevel [Byte0]: 65
1136 00:44:16.903306 [Byte1]: 65
1137 00:44:16.903353
1138 00:44:16.903399 Set Vref, RX VrefLevel [Byte0]: 66
1139 00:44:16.903446 [Byte1]: 66
1140 00:44:16.903493
1141 00:44:16.903540 Set Vref, RX VrefLevel [Byte0]: 67
1142 00:44:16.903587 [Byte1]: 67
1143 00:44:16.903634
1144 00:44:16.903680 Set Vref, RX VrefLevel [Byte0]: 68
1145 00:44:16.903726 [Byte1]: 68
1146 00:44:16.903773
1147 00:44:16.903818 Set Vref, RX VrefLevel [Byte0]: 69
1148 00:44:16.903865 [Byte1]: 69
1149 00:44:16.903912
1150 00:44:16.903958 Set Vref, RX VrefLevel [Byte0]: 70
1151 00:44:16.904004 [Byte1]: 70
1152 00:44:16.904050
1153 00:44:16.904097 Set Vref, RX VrefLevel [Byte0]: 71
1154 00:44:16.904144 [Byte1]: 71
1155 00:44:16.904190
1156 00:44:16.904236 Set Vref, RX VrefLevel [Byte0]: 72
1157 00:44:16.904283 [Byte1]: 72
1158 00:44:16.904330
1159 00:44:16.904377 Set Vref, RX VrefLevel [Byte0]: 73
1160 00:44:16.904423 [Byte1]: 73
1161 00:44:16.904470
1162 00:44:16.904517 Set Vref, RX VrefLevel [Byte0]: 74
1163 00:44:16.904563 [Byte1]: 74
1164 00:44:16.904610
1165 00:44:16.904852 Set Vref, RX VrefLevel [Byte0]: 75
1166 00:44:16.904962 [Byte1]: 75
1167 00:44:16.905068
1168 00:44:16.905173 Set Vref, RX VrefLevel [Byte0]: 76
1169 00:44:16.905279 [Byte1]: 76
1170 00:44:16.905421
1171 00:44:16.905529 Set Vref, RX VrefLevel [Byte0]: 77
1172 00:44:16.905635 [Byte1]: 77
1173 00:44:16.905740
1174 00:44:16.905847 Set Vref, RX VrefLevel [Byte0]: 78
1175 00:44:16.905952 [Byte1]: 78
1176 00:44:16.906057
1177 00:44:16.906113 Set Vref, RX VrefLevel [Byte0]: 79
1178 00:44:16.906191 [Byte1]: 79
1179 00:44:16.906239
1180 00:44:16.906286 Set Vref, RX VrefLevel [Byte0]: 80
1181 00:44:16.906333 [Byte1]: 80
1182 00:44:16.906380
1183 00:44:16.906443 Final RX Vref Byte 0 = 59 to rank0
1184 00:44:16.906503 Final RX Vref Byte 1 = 55 to rank0
1185 00:44:16.906552 Final RX Vref Byte 0 = 59 to rank1
1186 00:44:16.906599 Final RX Vref Byte 1 = 55 to rank1==
1187 00:44:16.906646 Dram Type= 6, Freq= 0, CH_0, rank 0
1188 00:44:16.906693 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1189 00:44:16.906740 ==
1190 00:44:16.906787 DQS Delay:
1191 00:44:16.906834 DQS0 = 0, DQS1 = 0
1192 00:44:16.906880 DQM Delay:
1193 00:44:16.906926 DQM0 = 82, DQM1 = 67
1194 00:44:16.906972 DQ Delay:
1195 00:44:16.907019 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1196 00:44:16.907083 DQ4 =84, DQ5 =68, DQ6 =88, DQ7 =92
1197 00:44:16.907144 DQ8 =60, DQ9 =56, DQ10 =68, DQ11 =60
1198 00:44:16.907221 DQ12 =72, DQ13 =68, DQ14 =80, DQ15 =76
1199 00:44:16.907268
1200 00:44:16.907314
1201 00:44:16.907360 [DQSOSCAuto] RK0, (LSB)MR18= 0x2c2b, (MSB)MR19= 0x606, tDQSOscB0 = 398 ps tDQSOscB1 = 398 ps
1202 00:44:16.907421 CH0 RK0: MR19=606, MR18=2C2B
1203 00:44:16.907482 CH0_RK0: MR19=0x606, MR18=0x2C2B, DQSOSC=398, MR23=63, INC=93, DEC=62
1204 00:44:16.907530
1205 00:44:16.907576 ----->DramcWriteLeveling(PI) begin...
1206 00:44:16.907624 ==
1207 00:44:16.907672 Dram Type= 6, Freq= 0, CH_0, rank 1
1208 00:44:16.907719 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1209 00:44:16.907766 ==
1210 00:44:16.907813 Write leveling (Byte 0): 30 => 30
1211 00:44:16.907859 Write leveling (Byte 1): 30 => 30
1212 00:44:16.907905 DramcWriteLeveling(PI) end<-----
1213 00:44:16.907952
1214 00:44:16.907999 ==
1215 00:44:16.908046 Dram Type= 6, Freq= 0, CH_0, rank 1
1216 00:44:16.908093 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1217 00:44:16.908140 ==
1218 00:44:16.908200 [Gating] SW mode calibration
1219 00:44:16.908262 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1220 00:44:16.908310 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1221 00:44:16.908358 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1222 00:44:16.908406 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1223 00:44:16.908453 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1224 00:44:16.908500 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 00:44:16.908562 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 00:44:16.908610 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 00:44:16.908695 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 00:44:16.908747 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 00:44:16.908794 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 00:44:16.908841 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 00:44:16.908889 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 00:44:16.908936 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 00:44:16.908984 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 00:44:16.909031 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 00:44:16.909078 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 00:44:16.909125 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1237 00:44:16.909172 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1238 00:44:16.909219 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1239 00:44:16.909266 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1240 00:44:16.909314 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1241 00:44:16.909362 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1242 00:44:16.909409 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1243 00:44:16.909456 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1244 00:44:16.909503 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1245 00:44:16.909551 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1246 00:44:16.909597 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1247 00:44:16.909644 0 9 8 | B1->B0 | 2323 2c2c | 0 0 | (1 1) (0 0)
1248 00:44:16.909691 0 9 12 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
1249 00:44:16.909738 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1250 00:44:16.909785 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1251 00:44:16.909832 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1252 00:44:16.909879 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1253 00:44:16.909926 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1254 00:44:16.909973 0 10 4 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
1255 00:44:16.910021 0 10 8 | B1->B0 | 2f2f 2323 | 0 0 | (0 1) (0 0)
1256 00:44:16.910068 0 10 12 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
1257 00:44:16.910115 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1258 00:44:16.910162 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1259 00:44:16.910209 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1260 00:44:16.910256 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1261 00:44:16.910302 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1262 00:44:16.910349 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1263 00:44:16.910442 0 11 8 | B1->B0 | 2a2a 3c3c | 1 0 | (0 0) (0 0)
1264 00:44:16.910502 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1265 00:44:16.910549 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1266 00:44:16.910596 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1267 00:44:16.910643 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1268 00:44:16.910690 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1269 00:44:16.910944 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1270 00:44:16.911055 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1271 00:44:16.911191 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1272 00:44:16.911297 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1273 00:44:16.911402 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1274 00:44:16.911512 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1275 00:44:16.911618 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1276 00:44:16.911682 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1277 00:44:16.911731 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1278 00:44:16.911794 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1279 00:44:16.911855 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1280 00:44:16.911903 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1281 00:44:16.911950 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1282 00:44:16.911996 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1283 00:44:16.912058 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1284 00:44:16.912119 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1285 00:44:16.912166 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1286 00:44:16.912213 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1287 00:44:16.912260 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1288 00:44:16.912307 Total UI for P1: 0, mck2ui 16
1289 00:44:16.912374 best dqsien dly found for B0: ( 0, 14, 6)
1290 00:44:16.912423 Total UI for P1: 0, mck2ui 16
1291 00:44:16.912471 best dqsien dly found for B1: ( 0, 14, 6)
1292 00:44:16.912518 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1293 00:44:16.912565 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1294 00:44:16.912612
1295 00:44:16.912695 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1296 00:44:16.912744 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1297 00:44:16.912792 [Gating] SW calibration Done
1298 00:44:16.912839 ==
1299 00:44:16.912886 Dram Type= 6, Freq= 0, CH_0, rank 1
1300 00:44:16.912933 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1301 00:44:16.912980 ==
1302 00:44:16.913027 RX Vref Scan: 0
1303 00:44:16.913074
1304 00:44:16.913121 RX Vref 0 -> 0, step: 1
1305 00:44:16.913169
1306 00:44:16.913215 RX Delay -130 -> 252, step: 16
1307 00:44:16.913262 iDelay=206, Bit 0, Center 77 (-50 ~ 205) 256
1308 00:44:16.913310 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1309 00:44:16.913357 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1310 00:44:16.913404 iDelay=206, Bit 3, Center 69 (-50 ~ 189) 240
1311 00:44:16.913451 iDelay=206, Bit 4, Center 77 (-50 ~ 205) 256
1312 00:44:16.913498 iDelay=206, Bit 5, Center 61 (-66 ~ 189) 256
1313 00:44:16.913574 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1314 00:44:16.913622 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
1315 00:44:16.913669 iDelay=206, Bit 8, Center 61 (-66 ~ 189) 256
1316 00:44:16.913716 iDelay=206, Bit 9, Center 53 (-66 ~ 173) 240
1317 00:44:16.913763 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1318 00:44:16.913828 iDelay=206, Bit 11, Center 61 (-66 ~ 189) 256
1319 00:44:16.913889 iDelay=206, Bit 12, Center 77 (-50 ~ 205) 256
1320 00:44:16.913936 iDelay=206, Bit 13, Center 77 (-50 ~ 205) 256
1321 00:44:16.913983 iDelay=206, Bit 14, Center 77 (-50 ~ 205) 256
1322 00:44:16.914029 iDelay=206, Bit 15, Center 77 (-50 ~ 205) 256
1323 00:44:16.914076 ==
1324 00:44:16.914123 Dram Type= 6, Freq= 0, CH_0, rank 1
1325 00:44:16.914170 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1326 00:44:16.914217 ==
1327 00:44:16.914264 DQS Delay:
1328 00:44:16.914313 DQS0 = 0, DQS1 = 0
1329 00:44:16.914385 DQM Delay:
1330 00:44:16.914460 DQM0 = 76, DQM1 = 69
1331 00:44:16.914508 DQ Delay:
1332 00:44:16.914555 DQ0 =77, DQ1 =85, DQ2 =69, DQ3 =69
1333 00:44:16.914603 DQ4 =77, DQ5 =61, DQ6 =85, DQ7 =85
1334 00:44:16.914650 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
1335 00:44:16.914696 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1336 00:44:16.914743
1337 00:44:16.914789
1338 00:44:16.914836 ==
1339 00:44:16.914899 Dram Type= 6, Freq= 0, CH_0, rank 1
1340 00:44:16.914962 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1341 00:44:16.915014 ==
1342 00:44:16.915074
1343 00:44:16.915122
1344 00:44:16.915169 TX Vref Scan disable
1345 00:44:16.915216 == TX Byte 0 ==
1346 00:44:16.915263 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1347 00:44:16.915310 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1348 00:44:16.915357 == TX Byte 1 ==
1349 00:44:16.915404 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1350 00:44:16.915451 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1351 00:44:16.915497 ==
1352 00:44:16.915544 Dram Type= 6, Freq= 0, CH_0, rank 1
1353 00:44:16.915591 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1354 00:44:16.915639 ==
1355 00:44:16.915685 TX Vref=22, minBit 0, minWin=27, winSum=432
1356 00:44:16.915733 TX Vref=24, minBit 1, minWin=27, winSum=438
1357 00:44:16.915779 TX Vref=26, minBit 1, minWin=27, winSum=438
1358 00:44:16.915827 TX Vref=28, minBit 1, minWin=27, winSum=443
1359 00:44:16.915875 TX Vref=30, minBit 1, minWin=27, winSum=447
1360 00:44:16.915922 TX Vref=32, minBit 11, minWin=26, winSum=440
1361 00:44:16.915969 [TxChooseVref] Worse bit 1, Min win 27, Win sum 447, Final Vref 30
1362 00:44:16.916017
1363 00:44:16.916064 Final TX Range 1 Vref 30
1364 00:44:16.916110
1365 00:44:16.916156 ==
1366 00:44:16.916202 Dram Type= 6, Freq= 0, CH_0, rank 1
1367 00:44:16.916249 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1368 00:44:16.916296 ==
1369 00:44:16.916342
1370 00:44:16.916388
1371 00:44:16.916433 TX Vref Scan disable
1372 00:44:16.916479 == TX Byte 0 ==
1373 00:44:16.916525 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1374 00:44:16.916572 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1375 00:44:16.916618 == TX Byte 1 ==
1376 00:44:16.916701 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1377 00:44:16.916749 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1378 00:44:16.916796
1379 00:44:16.916843 [DATLAT]
1380 00:44:16.916889 Freq=800, CH0 RK1
1381 00:44:16.916936
1382 00:44:16.916982 DATLAT Default: 0xa
1383 00:44:16.917029 0, 0xFFFF, sum = 0
1384 00:44:16.917077 1, 0xFFFF, sum = 0
1385 00:44:16.917125 2, 0xFFFF, sum = 0
1386 00:44:16.917172 3, 0xFFFF, sum = 0
1387 00:44:16.917220 4, 0xFFFF, sum = 0
1388 00:44:16.917268 5, 0xFFFF, sum = 0
1389 00:44:16.917315 6, 0xFFFF, sum = 0
1390 00:44:16.917362 7, 0xFFFF, sum = 0
1391 00:44:16.917410 8, 0xFFFF, sum = 0
1392 00:44:16.917456 9, 0x0, sum = 1
1393 00:44:16.917503 10, 0x0, sum = 2
1394 00:44:16.917550 11, 0x0, sum = 3
1395 00:44:16.917597 12, 0x0, sum = 4
1396 00:44:16.917645 best_step = 10
1397 00:44:16.917691
1398 00:44:16.917736 ==
1399 00:44:16.917782 Dram Type= 6, Freq= 0, CH_0, rank 1
1400 00:44:16.918020 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1401 00:44:16.918133 ==
1402 00:44:16.918240 RX Vref Scan: 0
1403 00:44:16.918345
1404 00:44:16.918466 RX Vref 0 -> 0, step: 1
1405 00:44:16.918586
1406 00:44:16.918668 RX Delay -111 -> 252, step: 8
1407 00:44:16.918718 iDelay=209, Bit 0, Center 76 (-39 ~ 192) 232
1408 00:44:16.918765 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
1409 00:44:16.918813 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1410 00:44:16.918860 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
1411 00:44:16.918906 iDelay=209, Bit 4, Center 80 (-39 ~ 200) 240
1412 00:44:16.918953 iDelay=209, Bit 5, Center 64 (-55 ~ 184) 240
1413 00:44:16.918998 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
1414 00:44:16.919044 iDelay=209, Bit 7, Center 92 (-23 ~ 208) 232
1415 00:44:16.919108 iDelay=209, Bit 8, Center 60 (-55 ~ 176) 232
1416 00:44:16.919155 iDelay=209, Bit 9, Center 56 (-55 ~ 168) 224
1417 00:44:16.919215 iDelay=209, Bit 10, Center 72 (-47 ~ 192) 240
1418 00:44:16.919262 iDelay=209, Bit 11, Center 60 (-55 ~ 176) 232
1419 00:44:16.919308 iDelay=209, Bit 12, Center 80 (-39 ~ 200) 240
1420 00:44:16.919371 iDelay=209, Bit 13, Center 76 (-39 ~ 192) 232
1421 00:44:16.919418 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
1422 00:44:16.919479 iDelay=209, Bit 15, Center 76 (-39 ~ 192) 232
1423 00:44:16.919526 ==
1424 00:44:16.919589 Dram Type= 6, Freq= 0, CH_0, rank 1
1425 00:44:16.919650 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1426 00:44:16.919697 ==
1427 00:44:16.919743 DQS Delay:
1428 00:44:16.919789 DQS0 = 0, DQS1 = 0
1429 00:44:16.919836 DQM Delay:
1430 00:44:16.919881 DQM0 = 79, DQM1 = 70
1431 00:44:16.919927 DQ Delay:
1432 00:44:16.919974 DQ0 =76, DQ1 =84, DQ2 =76, DQ3 =72
1433 00:44:16.920020 DQ4 =80, DQ5 =64, DQ6 =88, DQ7 =92
1434 00:44:16.920066 DQ8 =60, DQ9 =56, DQ10 =72, DQ11 =60
1435 00:44:16.920112 DQ12 =80, DQ13 =76, DQ14 =80, DQ15 =76
1436 00:44:16.920159
1437 00:44:16.920226
1438 00:44:16.920287 [DQSOSCAuto] RK1, (LSB)MR18= 0x502c, (MSB)MR19= 0x606, tDQSOscB0 = 398 ps tDQSOscB1 = 389 ps
1439 00:44:16.920335 CH0 RK1: MR19=606, MR18=502C
1440 00:44:16.920390 CH0_RK1: MR19=0x606, MR18=0x502C, DQSOSC=389, MR23=63, INC=97, DEC=65
1441 00:44:16.920438 [RxdqsGatingPostProcess] freq 800
1442 00:44:16.920485 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1443 00:44:16.920534 Pre-setting of DQS Precalculation
1444 00:44:16.920582 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1445 00:44:16.920629 ==
1446 00:44:16.920715 Dram Type= 6, Freq= 0, CH_1, rank 0
1447 00:44:16.920763 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1448 00:44:16.920810 ==
1449 00:44:16.920856 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1450 00:44:16.920903 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1451 00:44:16.920950 [CA 0] Center 36 (6~66) winsize 61
1452 00:44:16.920997 [CA 1] Center 36 (6~67) winsize 62
1453 00:44:16.921043 [CA 2] Center 34 (4~64) winsize 61
1454 00:44:16.921090 [CA 3] Center 34 (4~64) winsize 61
1455 00:44:16.921137 [CA 4] Center 34 (4~65) winsize 62
1456 00:44:16.921183 [CA 5] Center 34 (4~64) winsize 61
1457 00:44:16.921230
1458 00:44:16.921276 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1459 00:44:16.921323
1460 00:44:16.921369 [CATrainingPosCal] consider 1 rank data
1461 00:44:16.921415 u2DelayCellTimex100 = 270/100 ps
1462 00:44:16.921462 CA0 delay=36 (6~66),Diff = 2 PI (14 cell)
1463 00:44:16.921508 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1464 00:44:16.921555 CA2 delay=34 (4~64),Diff = 0 PI (0 cell)
1465 00:44:16.921603 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1466 00:44:16.921649 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1467 00:44:16.921696 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1468 00:44:16.921742
1469 00:44:16.921818 CA PerBit enable=1, Macro0, CA PI delay=34
1470 00:44:16.921864
1471 00:44:16.921910 [CBTSetCACLKResult] CA Dly = 34
1472 00:44:16.921957 CS Dly: 5 (0~36)
1473 00:44:16.922003 ==
1474 00:44:16.922050 Dram Type= 6, Freq= 0, CH_1, rank 1
1475 00:44:16.922097 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1476 00:44:16.922143 ==
1477 00:44:16.922189 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1478 00:44:16.922236 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1479 00:44:16.922302 [CA 0] Center 36 (6~67) winsize 62
1480 00:44:16.922400 [CA 1] Center 36 (6~67) winsize 62
1481 00:44:16.922462 [CA 2] Center 35 (5~65) winsize 61
1482 00:44:16.922545 [CA 3] Center 34 (4~64) winsize 61
1483 00:44:16.922595 [CA 4] Center 34 (4~65) winsize 62
1484 00:44:16.922642 [CA 5] Center 33 (3~64) winsize 62
1485 00:44:16.922689
1486 00:44:16.922735 [CmdBusTrainingLP45] Vref(ca) range 1: 30
1487 00:44:16.922782
1488 00:44:16.922828 [CATrainingPosCal] consider 2 rank data
1489 00:44:16.922875 u2DelayCellTimex100 = 270/100 ps
1490 00:44:16.922922 CA0 delay=36 (6~66),Diff = 2 PI (14 cell)
1491 00:44:16.922969 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1492 00:44:16.923015 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
1493 00:44:16.923062 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1494 00:44:16.923108 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1495 00:44:16.923154 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1496 00:44:16.923200
1497 00:44:16.923246 CA PerBit enable=1, Macro0, CA PI delay=34
1498 00:44:16.923293
1499 00:44:16.923339 [CBTSetCACLKResult] CA Dly = 34
1500 00:44:16.923386 CS Dly: 6 (0~38)
1501 00:44:16.923432
1502 00:44:16.923478 ----->DramcWriteLeveling(PI) begin...
1503 00:44:16.923527 ==
1504 00:44:16.923574 Dram Type= 6, Freq= 0, CH_1, rank 0
1505 00:44:16.923620 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1506 00:44:16.923666 ==
1507 00:44:16.923712 Write leveling (Byte 0): 31 => 31
1508 00:44:16.923759 Write leveling (Byte 1): 32 => 32
1509 00:44:16.923806 DramcWriteLeveling(PI) end<-----
1510 00:44:16.923852
1511 00:44:16.923898 ==
1512 00:44:16.923944 Dram Type= 6, Freq= 0, CH_1, rank 0
1513 00:44:16.924006 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1514 00:44:16.924068 ==
1515 00:44:16.924114 [Gating] SW mode calibration
1516 00:44:16.924161 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1517 00:44:16.924208 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1518 00:44:16.924256 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1519 00:44:16.924303 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1520 00:44:16.924349 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1521 00:44:16.924397 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 00:44:16.924636 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 00:44:16.924782 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 00:44:16.924889 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 00:44:16.924994 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 00:44:16.925100 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 00:44:16.925206 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 00:44:16.925283 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 00:44:16.925333 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 00:44:16.925381 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 00:44:16.925427 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 00:44:16.925473 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 00:44:16.925520 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 00:44:16.925567 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1535 00:44:16.925614 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1536 00:44:16.925661 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1537 00:44:16.925707 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1538 00:44:16.925753 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1539 00:44:16.925801 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1540 00:44:16.925846 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1541 00:44:16.925893 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1542 00:44:16.925939 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1543 00:44:16.925986 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1544 00:44:16.926033 0 9 8 | B1->B0 | 2525 2727 | 0 1 | (1 1) (1 1)
1545 00:44:16.926080 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1546 00:44:16.926127 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1547 00:44:16.926173 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1548 00:44:16.926220 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1549 00:44:16.926267 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1550 00:44:16.926313 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1551 00:44:16.926360 0 10 4 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 0)
1552 00:44:16.926407 0 10 8 | B1->B0 | 2f2f 2c2c | 1 0 | (1 0) (1 0)
1553 00:44:16.926453 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1554 00:44:16.926500 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1555 00:44:16.926547 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1556 00:44:16.926594 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1557 00:44:16.926641 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1558 00:44:16.926687 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1559 00:44:16.926734 0 11 4 | B1->B0 | 2626 2323 | 0 0 | (1 1) (0 0)
1560 00:44:16.926780 0 11 8 | B1->B0 | 3636 3636 | 0 0 | (0 0) (0 0)
1561 00:44:16.926826 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1562 00:44:16.926873 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1563 00:44:16.926920 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1564 00:44:16.926966 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1565 00:44:16.927012 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1566 00:44:16.927058 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1567 00:44:16.927104 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1568 00:44:16.927151 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1569 00:44:16.927197 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1570 00:44:16.927244 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1571 00:44:16.927291 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1572 00:44:16.927338 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1573 00:44:16.927384 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1574 00:44:16.927431 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1575 00:44:16.927477 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1576 00:44:16.927523 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1577 00:44:16.927569 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1578 00:44:16.927615 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1579 00:44:16.927662 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1580 00:44:16.927708 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1581 00:44:16.927754 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1582 00:44:16.927800 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1583 00:44:16.927847 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1584 00:44:16.927893 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1585 00:44:16.927939 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1586 00:44:16.927985 Total UI for P1: 0, mck2ui 16
1587 00:44:16.928032 best dqsien dly found for B0: ( 0, 14, 8)
1588 00:44:16.928080 Total UI for P1: 0, mck2ui 16
1589 00:44:16.928127 best dqsien dly found for B1: ( 0, 14, 8)
1590 00:44:16.928174 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1591 00:44:16.928221 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1592 00:44:16.928267
1593 00:44:16.928314 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1594 00:44:16.928360 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1595 00:44:16.928407 [Gating] SW calibration Done
1596 00:44:16.928453 ==
1597 00:44:16.928499 Dram Type= 6, Freq= 0, CH_1, rank 0
1598 00:44:16.928546 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1599 00:44:16.928594 ==
1600 00:44:16.928640 RX Vref Scan: 0
1601 00:44:16.928729
1602 00:44:16.928776 RX Vref 0 -> 0, step: 1
1603 00:44:16.928822
1604 00:44:16.928869 RX Delay -130 -> 252, step: 16
1605 00:44:16.928915 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1606 00:44:16.928962 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1607 00:44:16.929008 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1608 00:44:16.929054 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1609 00:44:16.929100 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1610 00:44:16.929146 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1611 00:44:16.929386 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1612 00:44:16.929497 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1613 00:44:16.929604 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1614 00:44:16.929710 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1615 00:44:16.929815 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1616 00:44:16.929921 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1617 00:44:16.930001 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1618 00:44:16.930051 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1619 00:44:16.930099 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1620 00:44:16.930146 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1621 00:44:16.930193 ==
1622 00:44:16.930240 Dram Type= 6, Freq= 0, CH_1, rank 0
1623 00:44:16.930287 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1624 00:44:16.930334 ==
1625 00:44:16.930382 DQS Delay:
1626 00:44:16.930428 DQS0 = 0, DQS1 = 0
1627 00:44:16.930476 DQM Delay:
1628 00:44:16.930523 DQM0 = 82, DQM1 = 70
1629 00:44:16.930569 DQ Delay:
1630 00:44:16.930615 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1631 00:44:16.930661 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =77
1632 00:44:16.930706 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =61
1633 00:44:16.930753 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1634 00:44:16.930799
1635 00:44:16.930846
1636 00:44:16.930892 ==
1637 00:44:16.930939 Dram Type= 6, Freq= 0, CH_1, rank 0
1638 00:44:16.930986 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1639 00:44:16.931032 ==
1640 00:44:16.931079
1641 00:44:16.931125
1642 00:44:16.931170 TX Vref Scan disable
1643 00:44:16.931217 == TX Byte 0 ==
1644 00:44:16.931263 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1645 00:44:16.931310 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1646 00:44:16.931356 == TX Byte 1 ==
1647 00:44:16.931403 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1648 00:44:16.931449 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1649 00:44:16.931495 ==
1650 00:44:16.931541 Dram Type= 6, Freq= 0, CH_1, rank 0
1651 00:44:16.931588 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1652 00:44:16.931634 ==
1653 00:44:16.931680 TX Vref=22, minBit 1, minWin=26, winSum=437
1654 00:44:16.931727 TX Vref=24, minBit 0, minWin=27, winSum=442
1655 00:44:16.931774 TX Vref=26, minBit 8, minWin=27, winSum=446
1656 00:44:16.931820 TX Vref=28, minBit 9, minWin=27, winSum=447
1657 00:44:16.931867 TX Vref=30, minBit 4, minWin=27, winSum=448
1658 00:44:16.931913 TX Vref=32, minBit 15, minWin=27, winSum=449
1659 00:44:16.931960 [TxChooseVref] Worse bit 15, Min win 27, Win sum 449, Final Vref 32
1660 00:44:16.932007
1661 00:44:16.932053 Final TX Range 1 Vref 32
1662 00:44:16.932099
1663 00:44:16.932144 ==
1664 00:44:16.932190 Dram Type= 6, Freq= 0, CH_1, rank 0
1665 00:44:16.932236 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1666 00:44:16.932284 ==
1667 00:44:16.932329
1668 00:44:16.932375
1669 00:44:16.932421 TX Vref Scan disable
1670 00:44:16.932467 == TX Byte 0 ==
1671 00:44:16.932514 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1672 00:44:16.932560 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1673 00:44:16.932607 == TX Byte 1 ==
1674 00:44:16.932732 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1675 00:44:16.932786 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1676 00:44:16.932833
1677 00:44:16.932880 [DATLAT]
1678 00:44:16.932926 Freq=800, CH1 RK0
1679 00:44:16.932973
1680 00:44:16.933020 DATLAT Default: 0xa
1681 00:44:16.933066 0, 0xFFFF, sum = 0
1682 00:44:16.933114 1, 0xFFFF, sum = 0
1683 00:44:16.933162 2, 0xFFFF, sum = 0
1684 00:44:16.933210 3, 0xFFFF, sum = 0
1685 00:44:16.933257 4, 0xFFFF, sum = 0
1686 00:44:16.933304 5, 0xFFFF, sum = 0
1687 00:44:16.933351 6, 0xFFFF, sum = 0
1688 00:44:16.933398 7, 0xFFFF, sum = 0
1689 00:44:16.933446 8, 0xFFFF, sum = 0
1690 00:44:16.933493 9, 0x0, sum = 1
1691 00:44:16.933541 10, 0x0, sum = 2
1692 00:44:16.933589 11, 0x0, sum = 3
1693 00:44:16.933636 12, 0x0, sum = 4
1694 00:44:16.933684 best_step = 10
1695 00:44:16.933730
1696 00:44:16.933776 ==
1697 00:44:16.933823 Dram Type= 6, Freq= 0, CH_1, rank 0
1698 00:44:16.933870 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1699 00:44:16.933917 ==
1700 00:44:16.933963 RX Vref Scan: 1
1701 00:44:16.934011
1702 00:44:16.934057 Set Vref Range= 32 -> 127
1703 00:44:16.934104
1704 00:44:16.934151 RX Vref 32 -> 127, step: 1
1705 00:44:16.934197
1706 00:44:16.934243 RX Delay -111 -> 252, step: 8
1707 00:44:16.934290
1708 00:44:16.934336 Set Vref, RX VrefLevel [Byte0]: 32
1709 00:44:16.934383 [Byte1]: 32
1710 00:44:16.934430
1711 00:44:16.934477 Set Vref, RX VrefLevel [Byte0]: 33
1712 00:44:16.934524 [Byte1]: 33
1713 00:44:16.934571
1714 00:44:16.934618 Set Vref, RX VrefLevel [Byte0]: 34
1715 00:44:16.934665 [Byte1]: 34
1716 00:44:16.934711
1717 00:44:16.934758 Set Vref, RX VrefLevel [Byte0]: 35
1718 00:44:16.934805 [Byte1]: 35
1719 00:44:16.934852
1720 00:44:16.934898 Set Vref, RX VrefLevel [Byte0]: 36
1721 00:44:16.934945 [Byte1]: 36
1722 00:44:16.934992
1723 00:44:16.935037 Set Vref, RX VrefLevel [Byte0]: 37
1724 00:44:16.935084 [Byte1]: 37
1725 00:44:16.935131
1726 00:44:16.935177 Set Vref, RX VrefLevel [Byte0]: 38
1727 00:44:16.935224 [Byte1]: 38
1728 00:44:16.935270
1729 00:44:16.935316 Set Vref, RX VrefLevel [Byte0]: 39
1730 00:44:16.935362 [Byte1]: 39
1731 00:44:16.935410
1732 00:44:16.935456 Set Vref, RX VrefLevel [Byte0]: 40
1733 00:44:16.935503 [Byte1]: 40
1734 00:44:16.935549
1735 00:44:16.935595 Set Vref, RX VrefLevel [Byte0]: 41
1736 00:44:16.935641 [Byte1]: 41
1737 00:44:16.935687
1738 00:44:16.935733 Set Vref, RX VrefLevel [Byte0]: 42
1739 00:44:16.935779 [Byte1]: 42
1740 00:44:16.935825
1741 00:44:16.935870 Set Vref, RX VrefLevel [Byte0]: 43
1742 00:44:16.935917 [Byte1]: 43
1743 00:44:16.935963
1744 00:44:16.936009 Set Vref, RX VrefLevel [Byte0]: 44
1745 00:44:16.936056 [Byte1]: 44
1746 00:44:16.936102
1747 00:44:16.936148 Set Vref, RX VrefLevel [Byte0]: 45
1748 00:44:16.936195 [Byte1]: 45
1749 00:44:16.936241
1750 00:44:16.936287 Set Vref, RX VrefLevel [Byte0]: 46
1751 00:44:16.936333 [Byte1]: 46
1752 00:44:16.936379
1753 00:44:16.936425 Set Vref, RX VrefLevel [Byte0]: 47
1754 00:44:16.936471 [Byte1]: 47
1755 00:44:16.936518
1756 00:44:16.936564 Set Vref, RX VrefLevel [Byte0]: 48
1757 00:44:16.936611 [Byte1]: 48
1758 00:44:16.936667
1759 00:44:16.936752 Set Vref, RX VrefLevel [Byte0]: 49
1760 00:44:16.936799 [Byte1]: 49
1761 00:44:16.936846
1762 00:44:16.936892 Set Vref, RX VrefLevel [Byte0]: 50
1763 00:44:16.936938 [Byte1]: 50
1764 00:44:16.936985
1765 00:44:16.937031 Set Vref, RX VrefLevel [Byte0]: 51
1766 00:44:16.937078 [Byte1]: 51
1767 00:44:16.937124
1768 00:44:16.937170 Set Vref, RX VrefLevel [Byte0]: 52
1769 00:44:16.937216 [Byte1]: 52
1770 00:44:16.937263
1771 00:44:16.937309 Set Vref, RX VrefLevel [Byte0]: 53
1772 00:44:16.937544 [Byte1]: 53
1773 00:44:16.937599
1774 00:44:16.937647 Set Vref, RX VrefLevel [Byte0]: 54
1775 00:44:16.937694 [Byte1]: 54
1776 00:44:16.937741
1777 00:44:16.937787 Set Vref, RX VrefLevel [Byte0]: 55
1778 00:44:16.937834 [Byte1]: 55
1779 00:44:16.937880
1780 00:44:16.937926 Set Vref, RX VrefLevel [Byte0]: 56
1781 00:44:16.937973 [Byte1]: 56
1782 00:44:16.938020
1783 00:44:16.938067 Set Vref, RX VrefLevel [Byte0]: 57
1784 00:44:16.938114 [Byte1]: 57
1785 00:44:16.938161
1786 00:44:16.938207 Set Vref, RX VrefLevel [Byte0]: 58
1787 00:44:16.938255 [Byte1]: 58
1788 00:44:16.938302
1789 00:44:16.938348 Set Vref, RX VrefLevel [Byte0]: 59
1790 00:44:16.938394 [Byte1]: 59
1791 00:44:16.938440
1792 00:44:16.938487 Set Vref, RX VrefLevel [Byte0]: 60
1793 00:44:16.938533 [Byte1]: 60
1794 00:44:16.938580
1795 00:44:16.938627 Set Vref, RX VrefLevel [Byte0]: 61
1796 00:44:16.938673 [Byte1]: 61
1797 00:44:16.938720
1798 00:44:16.938766 Set Vref, RX VrefLevel [Byte0]: 62
1799 00:44:16.938814 [Byte1]: 62
1800 00:44:16.938860
1801 00:44:16.938907 Set Vref, RX VrefLevel [Byte0]: 63
1802 00:44:16.938953 [Byte1]: 63
1803 00:44:16.939000
1804 00:44:16.939046 Set Vref, RX VrefLevel [Byte0]: 64
1805 00:44:16.939093 [Byte1]: 64
1806 00:44:16.939140
1807 00:44:16.939186 Set Vref, RX VrefLevel [Byte0]: 65
1808 00:44:16.939233 [Byte1]: 65
1809 00:44:16.939279
1810 00:44:16.939325 Set Vref, RX VrefLevel [Byte0]: 66
1811 00:44:16.939371 [Byte1]: 66
1812 00:44:16.939417
1813 00:44:16.939463 Set Vref, RX VrefLevel [Byte0]: 67
1814 00:44:16.939509 [Byte1]: 67
1815 00:44:16.939556
1816 00:44:16.939602 Set Vref, RX VrefLevel [Byte0]: 68
1817 00:44:16.939648 [Byte1]: 68
1818 00:44:16.939694
1819 00:44:16.939740 Set Vref, RX VrefLevel [Byte0]: 69
1820 00:44:16.939786 [Byte1]: 69
1821 00:44:16.939832
1822 00:44:16.939878 Set Vref, RX VrefLevel [Byte0]: 70
1823 00:44:16.939925 [Byte1]: 70
1824 00:44:16.939971
1825 00:44:16.940017 Set Vref, RX VrefLevel [Byte0]: 71
1826 00:44:16.940063 [Byte1]: 71
1827 00:44:16.940109
1828 00:44:16.940155 Set Vref, RX VrefLevel [Byte0]: 72
1829 00:44:16.940202 [Byte1]: 72
1830 00:44:16.940248
1831 00:44:16.940294 Set Vref, RX VrefLevel [Byte0]: 73
1832 00:44:16.940340 [Byte1]: 73
1833 00:44:16.940385
1834 00:44:16.940431 Set Vref, RX VrefLevel [Byte0]: 74
1835 00:44:16.940477 [Byte1]: 74
1836 00:44:16.940524
1837 00:44:16.940570 Final RX Vref Byte 0 = 63 to rank0
1838 00:44:16.940617 Final RX Vref Byte 1 = 56 to rank0
1839 00:44:16.940677 Final RX Vref Byte 0 = 63 to rank1
1840 00:44:16.940762 Final RX Vref Byte 1 = 56 to rank1==
1841 00:44:16.940810 Dram Type= 6, Freq= 0, CH_1, rank 0
1842 00:44:16.940857 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1843 00:44:16.940905 ==
1844 00:44:16.940951 DQS Delay:
1845 00:44:16.940998 DQS0 = 0, DQS1 = 0
1846 00:44:16.941045 DQM Delay:
1847 00:44:16.941091 DQM0 = 80, DQM1 = 71
1848 00:44:16.941137 DQ Delay:
1849 00:44:16.941184 DQ0 =88, DQ1 =72, DQ2 =68, DQ3 =76
1850 00:44:16.941230 DQ4 =76, DQ5 =92, DQ6 =92, DQ7 =76
1851 00:44:16.941276 DQ8 =56, DQ9 =64, DQ10 =72, DQ11 =68
1852 00:44:16.941323 DQ12 =80, DQ13 =76, DQ14 =76, DQ15 =76
1853 00:44:16.941368
1854 00:44:16.941414
1855 00:44:16.941460 [DQSOSCAuto] RK0, (LSB)MR18= 0x1721, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 404 ps
1856 00:44:16.941508 CH1 RK0: MR19=606, MR18=1721
1857 00:44:16.941555 CH1_RK0: MR19=0x606, MR18=0x1721, DQSOSC=401, MR23=63, INC=91, DEC=61
1858 00:44:16.941603
1859 00:44:16.941649 ----->DramcWriteLeveling(PI) begin...
1860 00:44:16.941696 ==
1861 00:44:16.941743 Dram Type= 6, Freq= 0, CH_1, rank 1
1862 00:44:16.941789 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1863 00:44:16.941836 ==
1864 00:44:16.941883 Write leveling (Byte 0): 25 => 25
1865 00:44:16.941930 Write leveling (Byte 1): 26 => 26
1866 00:44:16.941976 DramcWriteLeveling(PI) end<-----
1867 00:44:16.942023
1868 00:44:16.942069 ==
1869 00:44:16.942114 Dram Type= 6, Freq= 0, CH_1, rank 1
1870 00:44:16.942161 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1871 00:44:16.942208 ==
1872 00:44:16.942254 [Gating] SW mode calibration
1873 00:44:16.942300 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1874 00:44:16.942348 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1875 00:44:16.942395 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1876 00:44:16.942442 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1877 00:44:16.942489 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1878 00:44:16.942535 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 00:44:16.942582 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 00:44:16.942629 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 00:44:16.942676 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 00:44:16.942723 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 00:44:16.942769 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 00:44:16.942815 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 00:44:16.942862 0 7 8 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
1886 00:44:16.942908 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 00:44:16.942955 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 00:44:16.943002 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 00:44:16.943047 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 00:44:16.943093 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 00:44:16.943139 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 00:44:16.943186 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1893 00:44:16.943232 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1894 00:44:16.943278 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1895 00:44:16.943324 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1896 00:44:16.943370 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1897 00:44:16.943417 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1898 00:44:16.943463 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1899 00:44:16.943509 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1900 00:44:16.943760 0 9 4 | B1->B0 | 2323 2c2b | 1 1 | (1 1) (0 0)
1901 00:44:16.943873 0 9 8 | B1->B0 | 2e2e 3434 | 1 1 | (0 0) (1 1)
1902 00:44:16.943981 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1903 00:44:16.944107 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1904 00:44:16.944217 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1905 00:44:16.944323 0 9 24 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
1906 00:44:16.944428 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1907 00:44:16.944557 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1908 00:44:16.944733 0 10 4 | B1->B0 | 3232 2a2a | 1 0 | (1 1) (0 0)
1909 00:44:16.944851 0 10 8 | B1->B0 | 2c2c 2323 | 0 0 | (1 0) (1 0)
1910 00:44:16.944989 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1911 00:44:16.945095 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1912 00:44:16.945149 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1913 00:44:16.945200 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1914 00:44:16.945248 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1915 00:44:16.945295 0 11 0 | B1->B0 | 2323 2828 | 0 0 | (0 0) (1 1)
1916 00:44:16.945342 0 11 4 | B1->B0 | 3030 3c3c | 0 1 | (0 0) (0 0)
1917 00:44:16.945388 0 11 8 | B1->B0 | 3e3e 4646 | 1 0 | (0 0) (0 0)
1918 00:44:16.945434 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1919 00:44:16.945481 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1920 00:44:16.945527 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1921 00:44:16.945574 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1922 00:44:16.945620 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1923 00:44:16.945666 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1924 00:44:16.945713 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1925 00:44:16.945759 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1926 00:44:16.945806 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1927 00:44:16.945853 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1928 00:44:16.945900 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1929 00:44:16.945946 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1930 00:44:16.945993 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1931 00:44:16.946039 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1932 00:44:16.946085 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1933 00:44:16.946132 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1934 00:44:16.946178 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1935 00:44:16.946224 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1936 00:44:16.946271 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1937 00:44:16.946318 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1938 00:44:16.946365 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1939 00:44:16.946411 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1940 00:44:16.946458 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1941 00:44:16.946504 Total UI for P1: 0, mck2ui 16
1942 00:44:16.946551 best dqsien dly found for B0: ( 0, 14, 2)
1943 00:44:16.946598 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1944 00:44:16.946644 Total UI for P1: 0, mck2ui 16
1945 00:44:16.946691 best dqsien dly found for B1: ( 0, 14, 4)
1946 00:44:16.946737 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1947 00:44:16.946785 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1948 00:44:16.946832
1949 00:44:16.946878 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1950 00:44:16.946924 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1951 00:44:16.946970 [Gating] SW calibration Done
1952 00:44:16.947016 ==
1953 00:44:16.947062 Dram Type= 6, Freq= 0, CH_1, rank 1
1954 00:44:16.947108 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1955 00:44:16.947156 ==
1956 00:44:16.947202 RX Vref Scan: 0
1957 00:44:16.947249
1958 00:44:16.947295 RX Vref 0 -> 0, step: 1
1959 00:44:16.947341
1960 00:44:16.947387 RX Delay -130 -> 252, step: 16
1961 00:44:16.947434 iDelay=206, Bit 0, Center 77 (-50 ~ 205) 256
1962 00:44:16.947481 iDelay=206, Bit 1, Center 69 (-50 ~ 189) 240
1963 00:44:16.947527 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1964 00:44:16.947573 iDelay=206, Bit 3, Center 69 (-50 ~ 189) 240
1965 00:44:16.947619 iDelay=206, Bit 4, Center 69 (-50 ~ 189) 240
1966 00:44:16.947666 iDelay=206, Bit 5, Center 85 (-34 ~ 205) 240
1967 00:44:16.947712 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1968 00:44:16.947758 iDelay=206, Bit 7, Center 77 (-50 ~ 205) 256
1969 00:44:16.947805 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1970 00:44:16.947851 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1971 00:44:16.947898 iDelay=206, Bit 10, Center 77 (-50 ~ 205) 256
1972 00:44:16.947944 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1973 00:44:16.947991 iDelay=206, Bit 12, Center 77 (-50 ~ 205) 256
1974 00:44:16.948037 iDelay=206, Bit 13, Center 77 (-50 ~ 205) 256
1975 00:44:16.948083 iDelay=206, Bit 14, Center 77 (-50 ~ 205) 256
1976 00:44:16.948130 iDelay=206, Bit 15, Center 77 (-50 ~ 205) 256
1977 00:44:16.948176 ==
1978 00:44:16.948222 Dram Type= 6, Freq= 0, CH_1, rank 1
1979 00:44:16.948269 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1980 00:44:16.948316 ==
1981 00:44:16.948362 DQS Delay:
1982 00:44:16.948408 DQS0 = 0, DQS1 = 0
1983 00:44:16.948454 DQM Delay:
1984 00:44:16.948500 DQM0 = 75, DQM1 = 74
1985 00:44:16.948546 DQ Delay:
1986 00:44:16.948592 DQ0 =77, DQ1 =69, DQ2 =69, DQ3 =69
1987 00:44:17.186628 DQ4 =69, DQ5 =85, DQ6 =85, DQ7 =77
1988 00:44:17.186735 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1989 00:44:17.186794 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1990 00:44:17.186847
1991 00:44:17.186899
1992 00:44:17.186949 ==
1993 00:44:17.186998 Dram Type= 6, Freq= 0, CH_1, rank 1
1994 00:44:17.187046 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1995 00:44:17.187096 ==
1996 00:44:17.187143
1997 00:44:17.187190
1998 00:44:17.187237 TX Vref Scan disable
1999 00:44:17.187284 == TX Byte 0 ==
2000 00:44:17.187332 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
2001 00:44:17.187379 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
2002 00:44:17.187427 == TX Byte 1 ==
2003 00:44:17.187474 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
2004 00:44:17.187522 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
2005 00:44:17.187568 ==
2006 00:44:17.187615 Dram Type= 6, Freq= 0, CH_1, rank 1
2007 00:44:17.187863 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2008 00:44:17.187974 ==
2009 00:44:17.188083 TX Vref=22, minBit 1, minWin=28, winSum=454
2010 00:44:17.188192 TX Vref=24, minBit 1, minWin=28, winSum=457
2011 00:44:17.188302 TX Vref=26, minBit 5, minWin=28, winSum=461
2012 00:44:17.188409 TX Vref=28, minBit 5, minWin=28, winSum=462
2013 00:44:17.188528 TX Vref=30, minBit 1, minWin=28, winSum=463
2014 00:44:17.188622 TX Vref=32, minBit 5, minWin=28, winSum=462
2015 00:44:17.188694 [TxChooseVref] Worse bit 1, Min win 28, Win sum 463, Final Vref 30
2016 00:44:17.188746
2017 00:44:17.188809 Final TX Range 1 Vref 30
2018 00:44:17.188856
2019 00:44:17.188903 ==
2020 00:44:17.188951 Dram Type= 6, Freq= 0, CH_1, rank 1
2021 00:44:17.188998 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2022 00:44:17.189044 ==
2023 00:44:17.189090
2024 00:44:17.189136
2025 00:44:17.189183 TX Vref Scan disable
2026 00:44:17.189230 == TX Byte 0 ==
2027 00:44:17.189277 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
2028 00:44:17.189324 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
2029 00:44:17.189370 == TX Byte 1 ==
2030 00:44:17.189416 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
2031 00:44:17.189463 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
2032 00:44:17.189510
2033 00:44:17.189556 [DATLAT]
2034 00:44:17.189616 Freq=800, CH1 RK1
2035 00:44:17.189677
2036 00:44:17.189723 DATLAT Default: 0xa
2037 00:44:17.189770 0, 0xFFFF, sum = 0
2038 00:44:17.189831 1, 0xFFFF, sum = 0
2039 00:44:17.189894 2, 0xFFFF, sum = 0
2040 00:44:17.189941 3, 0xFFFF, sum = 0
2041 00:44:17.189988 4, 0xFFFF, sum = 0
2042 00:44:17.190035 5, 0xFFFF, sum = 0
2043 00:44:17.190082 6, 0xFFFF, sum = 0
2044 00:44:17.190130 7, 0xFFFF, sum = 0
2045 00:44:17.190200 8, 0xFFFF, sum = 0
2046 00:44:17.190250 9, 0x0, sum = 1
2047 00:44:17.190310 10, 0x0, sum = 2
2048 00:44:17.190407 11, 0x0, sum = 3
2049 00:44:17.190456 12, 0x0, sum = 4
2050 00:44:17.190503 best_step = 10
2051 00:44:17.190549
2052 00:44:17.190596 ==
2053 00:44:17.190666 Dram Type= 6, Freq= 0, CH_1, rank 1
2054 00:44:17.190785 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2055 00:44:17.190870 ==
2056 00:44:17.190917 RX Vref Scan: 0
2057 00:44:17.190964
2058 00:44:17.191031 RX Vref 0 -> 0, step: 1
2059 00:44:17.191079
2060 00:44:17.191126 RX Delay -95 -> 252, step: 8
2061 00:44:17.191175 iDelay=209, Bit 0, Center 80 (-39 ~ 200) 240
2062 00:44:17.191222 iDelay=209, Bit 1, Center 72 (-47 ~ 192) 240
2063 00:44:17.191269 iDelay=209, Bit 2, Center 68 (-55 ~ 192) 248
2064 00:44:17.191316 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
2065 00:44:17.191362 iDelay=209, Bit 4, Center 72 (-47 ~ 192) 240
2066 00:44:17.191409 iDelay=209, Bit 5, Center 88 (-31 ~ 208) 240
2067 00:44:17.191456 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
2068 00:44:17.191503 iDelay=209, Bit 7, Center 76 (-47 ~ 200) 248
2069 00:44:17.191549 iDelay=209, Bit 8, Center 64 (-55 ~ 184) 240
2070 00:44:17.191595 iDelay=209, Bit 9, Center 64 (-55 ~ 184) 240
2071 00:44:17.191642 iDelay=209, Bit 10, Center 76 (-47 ~ 200) 248
2072 00:44:17.191689 iDelay=209, Bit 11, Center 64 (-55 ~ 184) 240
2073 00:44:17.191736 iDelay=209, Bit 12, Center 80 (-39 ~ 200) 240
2074 00:44:17.191783 iDelay=209, Bit 13, Center 80 (-39 ~ 200) 240
2075 00:44:17.191850 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
2076 00:44:17.191899 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
2077 00:44:17.191945 ==
2078 00:44:17.191992 Dram Type= 6, Freq= 0, CH_1, rank 1
2079 00:44:17.192058 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2080 00:44:17.192107 ==
2081 00:44:17.192155 DQS Delay:
2082 00:44:17.192203 DQS0 = 0, DQS1 = 0
2083 00:44:17.192250 DQM Delay:
2084 00:44:17.192297 DQM0 = 77, DQM1 = 73
2085 00:44:17.192344 DQ Delay:
2086 00:44:17.192391 DQ0 =80, DQ1 =72, DQ2 =68, DQ3 =72
2087 00:44:17.192437 DQ4 =72, DQ5 =88, DQ6 =92, DQ7 =76
2088 00:44:17.192484 DQ8 =64, DQ9 =64, DQ10 =76, DQ11 =64
2089 00:44:17.192548 DQ12 =80, DQ13 =80, DQ14 =80, DQ15 =80
2090 00:44:17.192612
2091 00:44:17.192699
2092 00:44:17.192753 [DQSOSCAuto] RK1, (LSB)MR18= 0x243a, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 400 ps
2093 00:44:17.192803 CH1 RK1: MR19=606, MR18=243A
2094 00:44:17.192869 CH1_RK1: MR19=0x606, MR18=0x243A, DQSOSC=395, MR23=63, INC=94, DEC=63
2095 00:44:17.193000 [RxdqsGatingPostProcess] freq 800
2096 00:44:17.193050 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2097 00:44:17.193098 Pre-setting of DQS Precalculation
2098 00:44:17.193171 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2099 00:44:17.193304 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2100 00:44:17.193357 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2101 00:44:17.193406
2102 00:44:17.193453
2103 00:44:17.193500 [Calibration Summary] 1600 Mbps
2104 00:44:17.193547 CH 0, Rank 0
2105 00:44:17.193595 SW Impedance : PASS
2106 00:44:17.193643 DUTY Scan : NO K
2107 00:44:17.193690 ZQ Calibration : PASS
2108 00:44:17.193738 Jitter Meter : NO K
2109 00:44:17.193785 CBT Training : PASS
2110 00:44:17.193832 Write leveling : PASS
2111 00:44:17.193879 RX DQS gating : PASS
2112 00:44:17.193926 RX DQ/DQS(RDDQC) : PASS
2113 00:44:17.193973 TX DQ/DQS : PASS
2114 00:44:17.194020 RX DATLAT : PASS
2115 00:44:17.194067 RX DQ/DQS(Engine): PASS
2116 00:44:17.194115 TX OE : NO K
2117 00:44:17.194163 All Pass.
2118 00:44:17.194227
2119 00:44:17.194275 CH 0, Rank 1
2120 00:44:17.194322 SW Impedance : PASS
2121 00:44:17.194380 DUTY Scan : NO K
2122 00:44:17.194432 ZQ Calibration : PASS
2123 00:44:17.194497 Jitter Meter : NO K
2124 00:44:17.194546 CBT Training : PASS
2125 00:44:17.194594 Write leveling : PASS
2126 00:44:17.194641 RX DQS gating : PASS
2127 00:44:17.194688 RX DQ/DQS(RDDQC) : PASS
2128 00:44:17.194735 TX DQ/DQS : PASS
2129 00:44:17.194783 RX DATLAT : PASS
2130 00:44:17.194831 RX DQ/DQS(Engine): PASS
2131 00:44:17.194878 TX OE : NO K
2132 00:44:17.194925 All Pass.
2133 00:44:17.194972
2134 00:44:17.195019 CH 1, Rank 0
2135 00:44:17.195066 SW Impedance : PASS
2136 00:44:17.195113 DUTY Scan : NO K
2137 00:44:17.195162 ZQ Calibration : PASS
2138 00:44:17.195236 Jitter Meter : NO K
2139 00:44:17.195286 CBT Training : PASS
2140 00:44:17.195334 Write leveling : PASS
2141 00:44:17.195381 RX DQS gating : PASS
2142 00:44:17.195445 RX DQ/DQS(RDDQC) : PASS
2143 00:44:17.195522 TX DQ/DQS : PASS
2144 00:44:17.195608 RX DATLAT : PASS
2145 00:44:17.195687 RX DQ/DQS(Engine): PASS
2146 00:44:17.195762 TX OE : NO K
2147 00:44:17.195837 All Pass.
2148 00:44:17.195911
2149 00:44:17.195986 CH 1, Rank 1
2150 00:44:17.196060 SW Impedance : PASS
2151 00:44:17.196136 DUTY Scan : NO K
2152 00:44:17.196210 ZQ Calibration : PASS
2153 00:44:17.196291 Jitter Meter : NO K
2154 00:44:17.196382 CBT Training : PASS
2155 00:44:17.196480 Write leveling : PASS
2156 00:44:17.196556 RX DQS gating : PASS
2157 00:44:17.196823 RX DQ/DQS(RDDQC) : PASS
2158 00:44:17.196976 TX DQ/DQS : PASS
2159 00:44:17.197086 RX DATLAT : PASS
2160 00:44:17.197206 RX DQ/DQS(Engine): PASS
2161 00:44:17.197340 TX OE : NO K
2162 00:44:17.197445 All Pass.
2163 00:44:17.197530
2164 00:44:17.197580 DramC Write-DBI off
2165 00:44:17.197629 PER_BANK_REFRESH: Hybrid Mode
2166 00:44:17.197677 TX_TRACKING: ON
2167 00:44:17.197724 [GetDramInforAfterCalByMRR] Vendor 6.
2168 00:44:17.197772 [GetDramInforAfterCalByMRR] Revision 606.
2169 00:44:17.197819 [GetDramInforAfterCalByMRR] Revision 2 0.
2170 00:44:17.197866 MR0 0x3b3b
2171 00:44:17.197913 MR8 0x5151
2172 00:44:17.197960 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2173 00:44:17.198032
2174 00:44:17.198155 MR0 0x3b3b
2175 00:44:17.198238 MR8 0x5151
2176 00:44:17.198296 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2177 00:44:17.198354
2178 00:44:17.198421 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2179 00:44:17.198474 [FAST_K] Save calibration result to emmc
2180 00:44:17.198524 [FAST_K] Save calibration result to emmc
2181 00:44:17.198573 dram_init: config_dvfs: 1
2182 00:44:17.198621 dramc_set_vcore_voltage set vcore to 662500
2183 00:44:17.198690 Read voltage for 1200, 2
2184 00:44:17.198754 Vio18 = 0
2185 00:44:17.198806 Vcore = 662500
2186 00:44:17.198855 Vdram = 0
2187 00:44:17.198903 Vddq = 0
2188 00:44:17.198951 Vmddr = 0
2189 00:44:17.198998 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2190 00:44:17.199047 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2191 00:44:17.199096 MEM_TYPE=3, freq_sel=15
2192 00:44:17.199144 sv_algorithm_assistance_LP4_1600
2193 00:44:17.199193 ============ PULL DRAM RESETB DOWN ============
2194 00:44:17.199273 ========== PULL DRAM RESETB DOWN end =========
2195 00:44:17.199322 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2196 00:44:17.199369 ===================================
2197 00:44:17.199416 LPDDR4 DRAM CONFIGURATION
2198 00:44:17.199477 ===================================
2199 00:44:17.199552 EX_ROW_EN[0] = 0x0
2200 00:44:17.199630 EX_ROW_EN[1] = 0x0
2201 00:44:17.199706 LP4Y_EN = 0x0
2202 00:44:17.199783 WORK_FSP = 0x0
2203 00:44:17.199859 WL = 0x4
2204 00:44:17.199950 RL = 0x4
2205 00:44:17.200024 BL = 0x2
2206 00:44:17.200099 RPST = 0x0
2207 00:44:17.200174 RD_PRE = 0x0
2208 00:44:17.200259 WR_PRE = 0x1
2209 00:44:17.200311 WR_PST = 0x0
2210 00:44:17.200358 DBI_WR = 0x0
2211 00:44:17.200405 DBI_RD = 0x0
2212 00:44:17.200452 OTF = 0x1
2213 00:44:17.200501 ===================================
2214 00:44:17.200548 ===================================
2215 00:44:17.200596 ANA top config
2216 00:44:17.200648 ===================================
2217 00:44:17.200729 DLL_ASYNC_EN = 0
2218 00:44:17.200776 ALL_SLAVE_EN = 0
2219 00:44:17.200823 NEW_RANK_MODE = 1
2220 00:44:17.200870 DLL_IDLE_MODE = 1
2221 00:44:17.200917 LP45_APHY_COMB_EN = 1
2222 00:44:17.200964 TX_ODT_DIS = 1
2223 00:44:17.201011 NEW_8X_MODE = 1
2224 00:44:17.201059 ===================================
2225 00:44:17.201107 ===================================
2226 00:44:17.201154 data_rate = 2400
2227 00:44:17.201201 CKR = 1
2228 00:44:17.201249 DQ_P2S_RATIO = 8
2229 00:44:17.201296 ===================================
2230 00:44:17.201343 CA_P2S_RATIO = 8
2231 00:44:17.201389 DQ_CA_OPEN = 0
2232 00:44:17.201436 DQ_SEMI_OPEN = 0
2233 00:44:17.201483 CA_SEMI_OPEN = 0
2234 00:44:17.201529 CA_FULL_RATE = 0
2235 00:44:17.201576 DQ_CKDIV4_EN = 0
2236 00:44:17.201623 CA_CKDIV4_EN = 0
2237 00:44:17.201670 CA_PREDIV_EN = 0
2238 00:44:17.201717 PH8_DLY = 17
2239 00:44:17.201764 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2240 00:44:17.201811 DQ_AAMCK_DIV = 4
2241 00:44:17.201857 CA_AAMCK_DIV = 4
2242 00:44:17.201904 CA_ADMCK_DIV = 4
2243 00:44:17.201951 DQ_TRACK_CA_EN = 0
2244 00:44:17.201998 CA_PICK = 1200
2245 00:44:17.202045 CA_MCKIO = 1200
2246 00:44:17.202092 MCKIO_SEMI = 0
2247 00:44:17.202139 PLL_FREQ = 2366
2248 00:44:17.202186 DQ_UI_PI_RATIO = 32
2249 00:44:17.202243 CA_UI_PI_RATIO = 0
2250 00:44:17.202293 ===================================
2251 00:44:17.202340 ===================================
2252 00:44:17.202387 memory_type:LPDDR4
2253 00:44:17.202435 GP_NUM : 10
2254 00:44:17.202481 SRAM_EN : 1
2255 00:44:17.202528 MD32_EN : 0
2256 00:44:17.202575 ===================================
2257 00:44:17.202622 [ANA_INIT] >>>>>>>>>>>>>>
2258 00:44:17.202669 <<<<<< [CONFIGURE PHASE]: ANA_TX
2259 00:44:17.202718 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2260 00:44:17.202765 ===================================
2261 00:44:17.202812 data_rate = 2400,PCW = 0X5b00
2262 00:44:17.202859 ===================================
2263 00:44:17.202907 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2264 00:44:17.202954 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2265 00:44:17.203002 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2266 00:44:17.203050 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2267 00:44:17.203097 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2268 00:44:17.203144 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2269 00:44:17.203191 [ANA_INIT] flow start
2270 00:44:17.203237 [ANA_INIT] PLL >>>>>>>>
2271 00:44:17.203284 [ANA_INIT] PLL <<<<<<<<
2272 00:44:17.203331 [ANA_INIT] MIDPI >>>>>>>>
2273 00:44:17.203378 [ANA_INIT] MIDPI <<<<<<<<
2274 00:44:17.203424 [ANA_INIT] DLL >>>>>>>>
2275 00:44:17.203471 [ANA_INIT] DLL <<<<<<<<
2276 00:44:17.203518 [ANA_INIT] flow end
2277 00:44:17.203566 ============ LP4 DIFF to SE enter ============
2278 00:44:17.203614 ============ LP4 DIFF to SE exit ============
2279 00:44:17.203661 [ANA_INIT] <<<<<<<<<<<<<
2280 00:44:17.203708 [Flow] Enable top DCM control >>>>>
2281 00:44:17.203755 [Flow] Enable top DCM control <<<<<
2282 00:44:17.203802 Enable DLL master slave shuffle
2283 00:44:17.203850 ==============================================================
2284 00:44:17.203898 Gating Mode config
2285 00:44:17.203945 ==============================================================
2286 00:44:17.203993 Config description:
2287 00:44:17.204232 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2288 00:44:17.204315 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2289 00:44:17.204407 SELPH_MODE 0: By rank 1: By Phase
2290 00:44:17.204485 ==============================================================
2291 00:44:17.204563 GAT_TRACK_EN = 1
2292 00:44:17.204658 RX_GATING_MODE = 2
2293 00:44:17.204724 RX_GATING_TRACK_MODE = 2
2294 00:44:17.204771 SELPH_MODE = 1
2295 00:44:17.204819 PICG_EARLY_EN = 1
2296 00:44:17.204866 VALID_LAT_VALUE = 1
2297 00:44:17.204914 ==============================================================
2298 00:44:17.204962 Enter into Gating configuration >>>>
2299 00:44:17.205009 Exit from Gating configuration <<<<
2300 00:44:17.205056 Enter into DVFS_PRE_config >>>>>
2301 00:44:17.205104 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2302 00:44:17.205153 Exit from DVFS_PRE_config <<<<<
2303 00:44:17.205200 Enter into PICG configuration >>>>
2304 00:44:17.205247 Exit from PICG configuration <<<<
2305 00:44:17.205295 [RX_INPUT] configuration >>>>>
2306 00:44:17.205342 [RX_INPUT] configuration <<<<<
2307 00:44:17.205390 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2308 00:44:17.205437 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2309 00:44:17.205485 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2310 00:44:17.205533 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2311 00:44:17.205580 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2312 00:44:17.205628 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2313 00:44:17.205675 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2314 00:44:17.205723 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2315 00:44:17.205770 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2316 00:44:17.205817 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2317 00:44:17.205864 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2318 00:44:17.205912 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2319 00:44:17.205960 ===================================
2320 00:44:17.206008 LPDDR4 DRAM CONFIGURATION
2321 00:44:17.206054 ===================================
2322 00:44:17.206101 EX_ROW_EN[0] = 0x0
2323 00:44:17.206148 EX_ROW_EN[1] = 0x0
2324 00:44:17.206195 LP4Y_EN = 0x0
2325 00:44:17.206241 WORK_FSP = 0x0
2326 00:44:17.206288 WL = 0x4
2327 00:44:17.206335 RL = 0x4
2328 00:44:17.206382 BL = 0x2
2329 00:44:17.206428 RPST = 0x0
2330 00:44:17.206475 RD_PRE = 0x0
2331 00:44:17.206522 WR_PRE = 0x1
2332 00:44:17.206569 WR_PST = 0x0
2333 00:44:17.206633 DBI_WR = 0x0
2334 00:44:17.206695 DBI_RD = 0x0
2335 00:44:17.206742 OTF = 0x1
2336 00:44:17.206789 ===================================
2337 00:44:17.206836 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2338 00:44:17.206883 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2339 00:44:17.206931 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2340 00:44:17.206978 ===================================
2341 00:44:17.207025 LPDDR4 DRAM CONFIGURATION
2342 00:44:17.207071 ===================================
2343 00:44:17.207119 EX_ROW_EN[0] = 0x10
2344 00:44:17.207165 EX_ROW_EN[1] = 0x0
2345 00:44:17.207211 LP4Y_EN = 0x0
2346 00:44:17.207258 WORK_FSP = 0x0
2347 00:44:17.207305 WL = 0x4
2348 00:44:17.207352 RL = 0x4
2349 00:44:17.207399 BL = 0x2
2350 00:44:17.207446 RPST = 0x0
2351 00:44:17.207493 RD_PRE = 0x0
2352 00:44:17.207539 WR_PRE = 0x1
2353 00:44:17.207586 WR_PST = 0x0
2354 00:44:17.207633 DBI_WR = 0x0
2355 00:44:17.207680 DBI_RD = 0x0
2356 00:44:17.207727 OTF = 0x1
2357 00:44:17.207773 ===================================
2358 00:44:17.207820 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2359 00:44:17.207867 ==
2360 00:44:17.207915 Dram Type= 6, Freq= 0, CH_0, rank 0
2361 00:44:17.207963 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2362 00:44:17.208010 ==
2363 00:44:17.208056 [Duty_Offset_Calibration]
2364 00:44:17.208103 B0:2 B1:0 CA:3
2365 00:44:17.208149
2366 00:44:17.208195 [DutyScan_Calibration_Flow] k_type=0
2367 00:44:17.208241
2368 00:44:17.208286 ==CLK 0==
2369 00:44:17.208332 Final CLK duty delay cell = 0
2370 00:44:17.208379 [0] MAX Duty = 5062%(X100), DQS PI = 12
2371 00:44:17.208427 [0] MIN Duty = 4906%(X100), DQS PI = 54
2372 00:44:17.208489 [0] AVG Duty = 4984%(X100)
2373 00:44:17.208536
2374 00:44:17.208584 CH0 CLK Duty spec in!! Max-Min= 156%
2375 00:44:17.208632 [DutyScan_Calibration_Flow] ====Done====
2376 00:44:17.208704
2377 00:44:17.208751 [DutyScan_Calibration_Flow] k_type=1
2378 00:44:17.208798
2379 00:44:17.208843 ==DQS 0 ==
2380 00:44:17.208890 Final DQS duty delay cell = 0
2381 00:44:17.208937 [0] MAX Duty = 5062%(X100), DQS PI = 16
2382 00:44:17.208984 [0] MIN Duty = 4907%(X100), DQS PI = 2
2383 00:44:17.209031 [0] AVG Duty = 4984%(X100)
2384 00:44:17.209086
2385 00:44:17.209138 ==DQS 1 ==
2386 00:44:17.209185 Final DQS duty delay cell = -4
2387 00:44:17.209232 [-4] MAX Duty = 4969%(X100), DQS PI = 6
2388 00:44:17.209279 [-4] MIN Duty = 4876%(X100), DQS PI = 14
2389 00:44:17.209326 [-4] AVG Duty = 4922%(X100)
2390 00:44:17.209373
2391 00:44:17.209420 CH0 DQS 0 Duty spec in!! Max-Min= 155%
2392 00:44:17.209466
2393 00:44:17.209512 CH0 DQS 1 Duty spec in!! Max-Min= 93%
2394 00:44:17.209559 [DutyScan_Calibration_Flow] ====Done====
2395 00:44:17.209606
2396 00:44:17.209652 [DutyScan_Calibration_Flow] k_type=3
2397 00:44:17.209698
2398 00:44:17.209744 ==DQM 0 ==
2399 00:44:17.209790 Final DQM duty delay cell = 0
2400 00:44:17.209836 [0] MAX Duty = 5124%(X100), DQS PI = 28
2401 00:44:17.209883 [0] MIN Duty = 4876%(X100), DQS PI = 48
2402 00:44:17.209929 [0] AVG Duty = 5000%(X100)
2403 00:44:17.209976
2404 00:44:17.210024 ==DQM 1 ==
2405 00:44:17.210070 Final DQM duty delay cell = 4
2406 00:44:17.210118 [4] MAX Duty = 5124%(X100), DQS PI = 52
2407 00:44:17.210164 [4] MIN Duty = 5000%(X100), DQS PI = 12
2408 00:44:17.210210 [4] AVG Duty = 5062%(X100)
2409 00:44:17.210256
2410 00:44:17.210303 CH0 DQM 0 Duty spec in!! Max-Min= 248%
2411 00:44:17.210350
2412 00:44:17.210397 CH0 DQM 1 Duty spec in!! Max-Min= 124%
2413 00:44:17.210634 [DutyScan_Calibration_Flow] ====Done====
2414 00:44:17.210692
2415 00:44:17.210740 [DutyScan_Calibration_Flow] k_type=2
2416 00:44:17.210787
2417 00:44:17.210834 ==DQ 0 ==
2418 00:44:17.210880 Final DQ duty delay cell = -4
2419 00:44:17.210928 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2420 00:44:17.210975 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2421 00:44:17.211022 [-4] AVG Duty = 4969%(X100)
2422 00:44:17.211068
2423 00:44:17.211114 ==DQ 1 ==
2424 00:44:17.211160 Final DQ duty delay cell = -4
2425 00:44:17.211208 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2426 00:44:17.211254 [-4] MIN Duty = 4876%(X100), DQS PI = 20
2427 00:44:17.211300 [-4] AVG Duty = 4938%(X100)
2428 00:44:17.211346
2429 00:44:17.211393 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2430 00:44:17.211439
2431 00:44:17.211486 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2432 00:44:17.211533 [DutyScan_Calibration_Flow] ====Done====
2433 00:44:17.211580 ==
2434 00:44:17.211626 Dram Type= 6, Freq= 0, CH_1, rank 0
2435 00:44:17.211673 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2436 00:44:17.211719 ==
2437 00:44:17.211765 [Duty_Offset_Calibration]
2438 00:44:17.211811 B0:1 B1:-2 CA:0
2439 00:44:17.211857
2440 00:44:17.211904 [DutyScan_Calibration_Flow] k_type=0
2441 00:44:17.211950
2442 00:44:17.211995 ==CLK 0==
2443 00:44:17.212042 Final CLK duty delay cell = 0
2444 00:44:17.212089 [0] MAX Duty = 5031%(X100), DQS PI = 16
2445 00:44:17.212136 [0] MIN Duty = 4875%(X100), DQS PI = 58
2446 00:44:17.212183 [0] AVG Duty = 4953%(X100)
2447 00:44:17.212230
2448 00:44:17.212276 CH1 CLK Duty spec in!! Max-Min= 156%
2449 00:44:17.212323 [DutyScan_Calibration_Flow] ====Done====
2450 00:44:17.212370
2451 00:44:17.212416 [DutyScan_Calibration_Flow] k_type=1
2452 00:44:17.212463
2453 00:44:17.212508 ==DQS 0 ==
2454 00:44:17.212554 Final DQS duty delay cell = -4
2455 00:44:17.212601 [-4] MAX Duty = 5000%(X100), DQS PI = 24
2456 00:44:17.212656 [-4] MIN Duty = 4876%(X100), DQS PI = 50
2457 00:44:17.212739 [-4] AVG Duty = 4938%(X100)
2458 00:44:17.212784
2459 00:44:17.212830 ==DQS 1 ==
2460 00:44:17.212876 Final DQS duty delay cell = 0
2461 00:44:17.212924 [0] MAX Duty = 5062%(X100), DQS PI = 0
2462 00:44:17.212970 [0] MIN Duty = 4875%(X100), DQS PI = 26
2463 00:44:17.213017 [0] AVG Duty = 4968%(X100)
2464 00:44:17.213064
2465 00:44:17.213110 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2466 00:44:17.213157
2467 00:44:17.213204 CH1 DQS 1 Duty spec in!! Max-Min= 187%
2468 00:44:17.213250 [DutyScan_Calibration_Flow] ====Done====
2469 00:44:17.213296
2470 00:44:17.213342 [DutyScan_Calibration_Flow] k_type=3
2471 00:44:17.213389
2472 00:44:17.213436 ==DQM 0 ==
2473 00:44:17.213483 Final DQM duty delay cell = 0
2474 00:44:17.213529 [0] MAX Duty = 5000%(X100), DQS PI = 22
2475 00:44:17.213576 [0] MIN Duty = 4876%(X100), DQS PI = 4
2476 00:44:17.213622 [0] AVG Duty = 4938%(X100)
2477 00:44:17.213668
2478 00:44:17.213713 ==DQM 1 ==
2479 00:44:17.213759 Final DQM duty delay cell = 0
2480 00:44:17.213806 [0] MAX Duty = 5031%(X100), DQS PI = 36
2481 00:44:17.213853 [0] MIN Duty = 4907%(X100), DQS PI = 2
2482 00:44:17.213900 [0] AVG Duty = 4969%(X100)
2483 00:44:17.213946
2484 00:44:17.213992 CH1 DQM 0 Duty spec in!! Max-Min= 124%
2485 00:44:17.214038
2486 00:44:17.214084 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2487 00:44:17.214131 [DutyScan_Calibration_Flow] ====Done====
2488 00:44:17.214178
2489 00:44:17.214224 [DutyScan_Calibration_Flow] k_type=2
2490 00:44:17.214270
2491 00:44:17.214317 ==DQ 0 ==
2492 00:44:17.214364 Final DQ duty delay cell = 0
2493 00:44:17.214410 [0] MAX Duty = 5062%(X100), DQS PI = 12
2494 00:44:17.214456 [0] MIN Duty = 4938%(X100), DQS PI = 54
2495 00:44:17.214503 [0] AVG Duty = 5000%(X100)
2496 00:44:17.214548
2497 00:44:17.214594 ==DQ 1 ==
2498 00:44:17.214639 Final DQ duty delay cell = 0
2499 00:44:17.214685 [0] MAX Duty = 5125%(X100), DQS PI = 36
2500 00:44:17.214731 [0] MIN Duty = 4969%(X100), DQS PI = 26
2501 00:44:17.214778 [0] AVG Duty = 5047%(X100)
2502 00:44:17.214824
2503 00:44:17.214870 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2504 00:44:17.214916
2505 00:44:17.214962 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2506 00:44:17.215008 [DutyScan_Calibration_Flow] ====Done====
2507 00:44:17.215055 nWR fixed to 30
2508 00:44:17.215101 [ModeRegInit_LP4] CH0 RK0
2509 00:44:17.215147 [ModeRegInit_LP4] CH0 RK1
2510 00:44:17.215193 [ModeRegInit_LP4] CH1 RK0
2511 00:44:17.215239 [ModeRegInit_LP4] CH1 RK1
2512 00:44:17.215285 match AC timing 7
2513 00:44:17.215331 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2514 00:44:17.215378 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2515 00:44:17.215425 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2516 00:44:17.215484 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2517 00:44:17.215536 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2518 00:44:17.215583 ==
2519 00:44:17.215629 Dram Type= 6, Freq= 0, CH_0, rank 0
2520 00:44:17.215675 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2521 00:44:17.215722 ==
2522 00:44:17.215768 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2523 00:44:17.215816 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2524 00:44:17.215863 [CA 0] Center 40 (10~71) winsize 62
2525 00:44:17.215910 [CA 1] Center 39 (9~70) winsize 62
2526 00:44:17.215957 [CA 2] Center 36 (6~66) winsize 61
2527 00:44:17.216003 [CA 3] Center 35 (5~66) winsize 62
2528 00:44:17.216049 [CA 4] Center 34 (4~65) winsize 62
2529 00:44:17.216096 [CA 5] Center 33 (3~63) winsize 61
2530 00:44:17.216144
2531 00:44:17.216190 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2532 00:44:17.216237
2533 00:44:17.216283 [CATrainingPosCal] consider 1 rank data
2534 00:44:17.216330 u2DelayCellTimex100 = 270/100 ps
2535 00:44:17.216377 CA0 delay=40 (10~71),Diff = 7 PI (33 cell)
2536 00:44:17.216440 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2537 00:44:17.216488 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2538 00:44:17.216535 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2539 00:44:17.216583 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2540 00:44:17.216632 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2541 00:44:17.216707
2542 00:44:17.216754 CA PerBit enable=1, Macro0, CA PI delay=33
2543 00:44:17.216802
2544 00:44:17.216848 [CBTSetCACLKResult] CA Dly = 33
2545 00:44:17.216894 CS Dly: 7 (0~38)
2546 00:44:17.216971 ==
2547 00:44:17.217017 Dram Type= 6, Freq= 0, CH_0, rank 1
2548 00:44:17.217063 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2549 00:44:17.217110 ==
2550 00:44:17.217157 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2551 00:44:17.217204 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2552 00:44:17.217251 [CA 0] Center 40 (10~70) winsize 61
2553 00:44:17.217297 [CA 1] Center 39 (9~70) winsize 62
2554 00:44:17.217343 [CA 2] Center 35 (5~66) winsize 62
2555 00:44:17.217390 [CA 3] Center 35 (5~66) winsize 62
2556 00:44:17.217435 [CA 4] Center 34 (4~65) winsize 62
2557 00:44:17.217840 [CA 5] Center 33 (3~63) winsize 61
2558 00:44:17.217957
2559 00:44:17.218048 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2560 00:44:17.218126
2561 00:44:17.218202 [CATrainingPosCal] consider 2 rank data
2562 00:44:17.218277 u2DelayCellTimex100 = 270/100 ps
2563 00:44:17.218353 CA0 delay=40 (10~70),Diff = 7 PI (33 cell)
2564 00:44:17.218429 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2565 00:44:17.218504 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2566 00:44:17.218579 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2567 00:44:17.218654 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2568 00:44:17.218728 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2569 00:44:17.218803
2570 00:44:17.218878 CA PerBit enable=1, Macro0, CA PI delay=33
2571 00:44:17.218953
2572 00:44:17.219027 [CBTSetCACLKResult] CA Dly = 33
2573 00:44:17.219101 CS Dly: 8 (0~40)
2574 00:44:17.219175
2575 00:44:17.219249 ----->DramcWriteLeveling(PI) begin...
2576 00:44:17.219324 ==
2577 00:44:17.219400 Dram Type= 6, Freq= 0, CH_0, rank 0
2578 00:44:17.219475 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2579 00:44:17.219550 ==
2580 00:44:17.219624 Write leveling (Byte 0): 33 => 33
2581 00:44:17.219740 Write leveling (Byte 1): 30 => 30
2582 00:44:17.219789 DramcWriteLeveling(PI) end<-----
2583 00:44:17.219854
2584 00:44:17.219916 ==
2585 00:44:17.219994 Dram Type= 6, Freq= 0, CH_0, rank 0
2586 00:44:17.220042 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2587 00:44:17.220089 ==
2588 00:44:17.220135 [Gating] SW mode calibration
2589 00:44:17.220198 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2590 00:44:17.220275 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2591 00:44:17.220336 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2592 00:44:17.220383 0 15 4 | B1->B0 | 2626 3434 | 1 0 | (1 1) (0 0)
2593 00:44:17.220429 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2594 00:44:17.220476 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2595 00:44:17.220523 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2596 00:44:17.220569 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2597 00:44:17.220615 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2598 00:44:17.220700 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2599 00:44:17.220750 1 0 0 | B1->B0 | 3232 2a2a | 0 0 | (0 0) (0 0)
2600 00:44:17.220797 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2601 00:44:17.220844 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2602 00:44:17.220891 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2603 00:44:17.220937 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2604 00:44:17.220984 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2605 00:44:17.221030 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2606 00:44:17.221076 1 0 28 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
2607 00:44:17.221123 1 1 0 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (1 1)
2608 00:44:17.221170 1 1 4 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
2609 00:44:17.221217 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2610 00:44:17.221264 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2611 00:44:17.221310 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2612 00:44:17.221356 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2613 00:44:17.221403 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2614 00:44:17.221450 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2615 00:44:17.221496 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2616 00:44:17.221541 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2617 00:44:17.221588 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2618 00:44:17.221634 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2619 00:44:17.221681 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2620 00:44:17.221727 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2621 00:44:17.221774 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2622 00:44:17.221821 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2623 00:44:17.221868 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2624 00:44:17.222022 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2625 00:44:17.222120 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2626 00:44:17.222190 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2627 00:44:17.222240 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2628 00:44:17.222287 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2629 00:44:17.222333 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2630 00:44:17.222379 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2631 00:44:17.222427 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2632 00:44:17.222474 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2633 00:44:17.222521 Total UI for P1: 0, mck2ui 16
2634 00:44:17.222568 best dqsien dly found for B0: ( 1, 4, 0)
2635 00:44:17.222614 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2636 00:44:17.222661 Total UI for P1: 0, mck2ui 16
2637 00:44:17.222708 best dqsien dly found for B1: ( 1, 4, 2)
2638 00:44:17.222755 best DQS0 dly(MCK, UI, PI) = (1, 4, 0)
2639 00:44:17.222801 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2640 00:44:17.222847
2641 00:44:17.222895 best DQS0 P1 dly(MCK, UI, PI) = (1, 8, 0)
2642 00:44:17.222943 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2643 00:44:17.222990 [Gating] SW calibration Done
2644 00:44:17.223036 ==
2645 00:44:17.223082 Dram Type= 6, Freq= 0, CH_0, rank 0
2646 00:44:17.223129 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2647 00:44:17.223176 ==
2648 00:44:17.223222 RX Vref Scan: 0
2649 00:44:17.223268
2650 00:44:17.223314 RX Vref 0 -> 0, step: 1
2651 00:44:17.223360
2652 00:44:17.223407 RX Delay -40 -> 252, step: 8
2653 00:44:17.223453 iDelay=200, Bit 0, Center 111 (32 ~ 191) 160
2654 00:44:17.223500 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
2655 00:44:17.223546 iDelay=200, Bit 2, Center 107 (32 ~ 183) 152
2656 00:44:17.223593 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2657 00:44:17.223639 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2658 00:44:17.223685 iDelay=200, Bit 5, Center 99 (24 ~ 175) 152
2659 00:44:17.223730 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
2660 00:44:17.223777 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2661 00:44:17.224011 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
2662 00:44:17.224064 iDelay=200, Bit 9, Center 87 (8 ~ 167) 160
2663 00:44:17.224112 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2664 00:44:17.224159 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2665 00:44:17.224206 iDelay=200, Bit 12, Center 103 (32 ~ 175) 144
2666 00:44:17.224251 iDelay=200, Bit 13, Center 107 (32 ~ 183) 152
2667 00:44:17.224298 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
2668 00:44:17.224344 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2669 00:44:17.224390 ==
2670 00:44:17.224437 Dram Type= 6, Freq= 0, CH_0, rank 0
2671 00:44:17.224483 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2672 00:44:17.224530 ==
2673 00:44:17.224576 DQS Delay:
2674 00:44:17.224633 DQS0 = 0, DQS1 = 0
2675 00:44:17.224724 DQM Delay:
2676 00:44:17.224778 DQM0 = 111, DQM1 = 101
2677 00:44:17.224835 DQ Delay:
2678 00:44:17.224883 DQ0 =111, DQ1 =111, DQ2 =107, DQ3 =107
2679 00:44:17.224931 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =123
2680 00:44:17.224985 DQ8 =91, DQ9 =87, DQ10 =103, DQ11 =95
2681 00:44:17.225036 DQ12 =103, DQ13 =107, DQ14 =115, DQ15 =111
2682 00:44:17.225083
2683 00:44:17.225134
2684 00:44:17.225183 ==
2685 00:44:17.225229 Dram Type= 6, Freq= 0, CH_0, rank 0
2686 00:44:17.225276 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2687 00:44:17.225323 ==
2688 00:44:17.225384
2689 00:44:17.225432
2690 00:44:17.225478 TX Vref Scan disable
2691 00:44:17.225527 == TX Byte 0 ==
2692 00:44:17.225577 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2693 00:44:17.225624 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2694 00:44:17.225671 == TX Byte 1 ==
2695 00:44:17.225717 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2696 00:44:17.225769 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2697 00:44:17.225821 ==
2698 00:44:17.225868 Dram Type= 6, Freq= 0, CH_0, rank 0
2699 00:44:17.225915 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2700 00:44:17.225972 ==
2701 00:44:17.226048 TX Vref=22, minBit 1, minWin=25, winSum=415
2702 00:44:17.226124 TX Vref=24, minBit 1, minWin=26, winSum=424
2703 00:44:17.226205 TX Vref=26, minBit 3, minWin=26, winSum=426
2704 00:44:17.226281 TX Vref=28, minBit 2, minWin=26, winSum=431
2705 00:44:17.226357 TX Vref=30, minBit 8, minWin=26, winSum=434
2706 00:44:17.226436 TX Vref=32, minBit 1, minWin=26, winSum=428
2707 00:44:17.226512 [TxChooseVref] Worse bit 8, Min win 26, Win sum 434, Final Vref 30
2708 00:44:17.226591
2709 00:44:17.226668 Final TX Range 1 Vref 30
2710 00:44:17.226742
2711 00:44:17.226816 ==
2712 00:44:17.226891 Dram Type= 6, Freq= 0, CH_0, rank 0
2713 00:44:17.226967 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2714 00:44:17.227041 ==
2715 00:44:17.227115
2716 00:44:17.227188
2717 00:44:17.227262 TX Vref Scan disable
2718 00:44:17.227337 == TX Byte 0 ==
2719 00:44:17.227411 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2720 00:44:17.227487 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2721 00:44:17.227561 == TX Byte 1 ==
2722 00:44:17.227636 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2723 00:44:17.227711 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2724 00:44:17.227785
2725 00:44:17.227859 [DATLAT]
2726 00:44:17.227933 Freq=1200, CH0 RK0
2727 00:44:17.228007
2728 00:44:17.228081 DATLAT Default: 0xd
2729 00:44:17.228156 0, 0xFFFF, sum = 0
2730 00:44:17.228233 1, 0xFFFF, sum = 0
2731 00:44:17.228309 2, 0xFFFF, sum = 0
2732 00:44:17.228385 3, 0xFFFF, sum = 0
2733 00:44:17.228461 4, 0xFFFF, sum = 0
2734 00:44:17.228536 5, 0xFFFF, sum = 0
2735 00:44:17.228612 6, 0xFFFF, sum = 0
2736 00:44:17.228702 7, 0xFFFF, sum = 0
2737 00:44:17.228764 8, 0xFFFF, sum = 0
2738 00:44:17.228812 9, 0xFFFF, sum = 0
2739 00:44:17.228860 10, 0xFFFF, sum = 0
2740 00:44:17.228908 11, 0xFFFF, sum = 0
2741 00:44:17.228954 12, 0x0, sum = 1
2742 00:44:17.229001 13, 0x0, sum = 2
2743 00:44:17.229048 14, 0x0, sum = 3
2744 00:44:17.229096 15, 0x0, sum = 4
2745 00:44:17.229143 best_step = 13
2746 00:44:17.229189
2747 00:44:17.229235 ==
2748 00:44:17.229281 Dram Type= 6, Freq= 0, CH_0, rank 0
2749 00:44:17.229327 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2750 00:44:17.229373 ==
2751 00:44:17.229419 RX Vref Scan: 1
2752 00:44:17.229466
2753 00:44:17.229512 Set Vref Range= 32 -> 127
2754 00:44:17.229559
2755 00:44:17.229605 RX Vref 32 -> 127, step: 1
2756 00:44:17.229651
2757 00:44:17.229698 RX Delay -37 -> 252, step: 4
2758 00:44:17.229744
2759 00:44:17.229791 Set Vref, RX VrefLevel [Byte0]: 32
2760 00:44:17.229838 [Byte1]: 32
2761 00:44:17.229884
2762 00:44:17.229929 Set Vref, RX VrefLevel [Byte0]: 33
2763 00:44:17.229976 [Byte1]: 33
2764 00:44:17.230022
2765 00:44:17.230068 Set Vref, RX VrefLevel [Byte0]: 34
2766 00:44:17.230114 [Byte1]: 34
2767 00:44:17.230161
2768 00:44:17.230208 Set Vref, RX VrefLevel [Byte0]: 35
2769 00:44:17.230255 [Byte1]: 35
2770 00:44:17.230302
2771 00:44:17.230347 Set Vref, RX VrefLevel [Byte0]: 36
2772 00:44:17.230393 [Byte1]: 36
2773 00:44:17.230439
2774 00:44:17.230484 Set Vref, RX VrefLevel [Byte0]: 37
2775 00:44:17.230531 [Byte1]: 37
2776 00:44:17.230578
2777 00:44:17.230624 Set Vref, RX VrefLevel [Byte0]: 38
2778 00:44:17.230669 [Byte1]: 38
2779 00:44:17.230715
2780 00:44:17.230761 Set Vref, RX VrefLevel [Byte0]: 39
2781 00:44:17.230808 [Byte1]: 39
2782 00:44:17.230854
2783 00:44:17.230900 Set Vref, RX VrefLevel [Byte0]: 40
2784 00:44:17.230947 [Byte1]: 40
2785 00:44:17.230993
2786 00:44:17.231039 Set Vref, RX VrefLevel [Byte0]: 41
2787 00:44:17.231085 [Byte1]: 41
2788 00:44:17.231131
2789 00:44:17.231177 Set Vref, RX VrefLevel [Byte0]: 42
2790 00:44:17.231223 [Byte1]: 42
2791 00:44:17.231269
2792 00:44:17.231315 Set Vref, RX VrefLevel [Byte0]: 43
2793 00:44:17.231361 [Byte1]: 43
2794 00:44:17.231406
2795 00:44:17.231452 Set Vref, RX VrefLevel [Byte0]: 44
2796 00:44:17.231498 [Byte1]: 44
2797 00:44:17.231544
2798 00:44:17.231591 Set Vref, RX VrefLevel [Byte0]: 45
2799 00:44:17.231637 [Byte1]: 45
2800 00:44:17.231683
2801 00:44:17.231730 Set Vref, RX VrefLevel [Byte0]: 46
2802 00:44:17.231776 [Byte1]: 46
2803 00:44:17.231822
2804 00:44:17.231868 Set Vref, RX VrefLevel [Byte0]: 47
2805 00:44:17.231914 [Byte1]: 47
2806 00:44:17.231960
2807 00:44:17.232006 Set Vref, RX VrefLevel [Byte0]: 48
2808 00:44:17.232052 [Byte1]: 48
2809 00:44:17.232098
2810 00:44:17.232144 Set Vref, RX VrefLevel [Byte0]: 49
2811 00:44:17.232192 [Byte1]: 49
2812 00:44:17.232238
2813 00:44:17.232284 Set Vref, RX VrefLevel [Byte0]: 50
2814 00:44:17.232330 [Byte1]: 50
2815 00:44:17.232376
2816 00:44:17.232423 Set Vref, RX VrefLevel [Byte0]: 51
2817 00:44:17.232469 [Byte1]: 51
2818 00:44:17.232516
2819 00:44:17.232562 Set Vref, RX VrefLevel [Byte0]: 52
2820 00:44:17.232607 [Byte1]: 52
2821 00:44:17.232661
2822 00:44:17.232745 Set Vref, RX VrefLevel [Byte0]: 53
2823 00:44:17.232981 [Byte1]: 53
2824 00:44:17.233034
2825 00:44:17.233081 Set Vref, RX VrefLevel [Byte0]: 54
2826 00:44:17.233129 [Byte1]: 54
2827 00:44:17.233176
2828 00:44:17.233222 Set Vref, RX VrefLevel [Byte0]: 55
2829 00:44:17.233269 [Byte1]: 55
2830 00:44:17.233315
2831 00:44:17.233361 Set Vref, RX VrefLevel [Byte0]: 56
2832 00:44:17.233408 [Byte1]: 56
2833 00:44:17.233454
2834 00:44:17.233499 Set Vref, RX VrefLevel [Byte0]: 57
2835 00:44:17.233546 [Byte1]: 57
2836 00:44:17.233592
2837 00:44:17.233638 Set Vref, RX VrefLevel [Byte0]: 58
2838 00:44:17.233684 [Byte1]: 58
2839 00:44:17.233730
2840 00:44:17.233777 Set Vref, RX VrefLevel [Byte0]: 59
2841 00:44:17.233822 [Byte1]: 59
2842 00:44:17.233868
2843 00:44:17.233914 Set Vref, RX VrefLevel [Byte0]: 60
2844 00:44:17.233960 [Byte1]: 60
2845 00:44:17.234006
2846 00:44:17.234051 Set Vref, RX VrefLevel [Byte0]: 61
2847 00:44:17.234098 [Byte1]: 61
2848 00:44:17.234144
2849 00:44:17.234190 Set Vref, RX VrefLevel [Byte0]: 62
2850 00:44:17.234273 [Byte1]: 62
2851 00:44:17.234320
2852 00:44:17.234367 Set Vref, RX VrefLevel [Byte0]: 63
2853 00:44:17.234414 [Byte1]: 63
2854 00:44:17.234461
2855 00:44:17.234506 Set Vref, RX VrefLevel [Byte0]: 64
2856 00:44:17.234552 [Byte1]: 64
2857 00:44:17.234598
2858 00:44:17.234644 Set Vref, RX VrefLevel [Byte0]: 65
2859 00:44:17.234691 [Byte1]: 65
2860 00:44:17.234737
2861 00:44:17.234783 Set Vref, RX VrefLevel [Byte0]: 66
2862 00:44:17.234829 [Byte1]: 66
2863 00:44:17.234875
2864 00:44:17.234921 Set Vref, RX VrefLevel [Byte0]: 67
2865 00:44:17.234968 [Byte1]: 67
2866 00:44:17.235014
2867 00:44:17.235060 Set Vref, RX VrefLevel [Byte0]: 68
2868 00:44:17.235107 [Byte1]: 68
2869 00:44:17.235153
2870 00:44:17.235199 Set Vref, RX VrefLevel [Byte0]: 69
2871 00:44:17.235254 [Byte1]: 69
2872 00:44:17.235310
2873 00:44:17.235364 Set Vref, RX VrefLevel [Byte0]: 70
2874 00:44:17.235413 [Byte1]: 70
2875 00:44:17.235466
2876 00:44:17.235546 Set Vref, RX VrefLevel [Byte0]: 71
2877 00:44:17.235624 [Byte1]: 71
2878 00:44:17.235699
2879 00:44:17.235773 Set Vref, RX VrefLevel [Byte0]: 72
2880 00:44:17.235848 [Byte1]: 72
2881 00:44:17.235925
2882 00:44:17.236004 Set Vref, RX VrefLevel [Byte0]: 73
2883 00:44:17.236084 [Byte1]: 73
2884 00:44:17.236162
2885 00:44:17.236284 Set Vref, RX VrefLevel [Byte0]: 74
2886 00:44:17.236363 [Byte1]: 74
2887 00:44:17.236442
2888 00:44:17.236520 Set Vref, RX VrefLevel [Byte0]: 75
2889 00:44:17.236597 [Byte1]: 75
2890 00:44:17.236709
2891 00:44:17.236784 Final RX Vref Byte 0 = 61 to rank0
2892 00:44:17.236859 Final RX Vref Byte 1 = 48 to rank0
2893 00:44:17.236934 Final RX Vref Byte 0 = 61 to rank1
2894 00:44:17.237009 Final RX Vref Byte 1 = 48 to rank1==
2895 00:44:17.237085 Dram Type= 6, Freq= 0, CH_0, rank 0
2896 00:44:17.237160 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2897 00:44:17.237234 ==
2898 00:44:17.237308 DQS Delay:
2899 00:44:17.237382 DQS0 = 0, DQS1 = 0
2900 00:44:17.237456 DQM Delay:
2901 00:44:17.237530 DQM0 = 111, DQM1 = 98
2902 00:44:17.237603 DQ Delay:
2903 00:44:17.237677 DQ0 =108, DQ1 =112, DQ2 =112, DQ3 =108
2904 00:44:17.237752 DQ4 =112, DQ5 =104, DQ6 =118, DQ7 =120
2905 00:44:17.237826 DQ8 =90, DQ9 =82, DQ10 =100, DQ11 =90
2906 00:44:17.237900 DQ12 =104, DQ13 =104, DQ14 =112, DQ15 =106
2907 00:44:17.237974
2908 00:44:17.238047
2909 00:44:17.238122 [DQSOSCAuto] RK0, (LSB)MR18= 0xfdfc, (MSB)MR19= 0x303, tDQSOscB0 = 411 ps tDQSOscB1 = 411 ps
2910 00:44:17.238197 CH0 RK0: MR19=303, MR18=FDFC
2911 00:44:17.238272 CH0_RK0: MR19=0x303, MR18=0xFDFC, DQSOSC=411, MR23=63, INC=38, DEC=25
2912 00:44:17.238346
2913 00:44:17.238421 ----->DramcWriteLeveling(PI) begin...
2914 00:44:17.238496 ==
2915 00:44:17.238570 Dram Type= 6, Freq= 0, CH_0, rank 1
2916 00:44:17.238645 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2917 00:44:17.238719 ==
2918 00:44:17.238793 Write leveling (Byte 0): 31 => 31
2919 00:44:17.238867 Write leveling (Byte 1): 31 => 31
2920 00:44:17.238941 DramcWriteLeveling(PI) end<-----
2921 00:44:17.239015
2922 00:44:17.239088 ==
2923 00:44:17.239162 Dram Type= 6, Freq= 0, CH_0, rank 1
2924 00:44:17.239237 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2925 00:44:17.239311 ==
2926 00:44:17.239385 [Gating] SW mode calibration
2927 00:44:17.239460 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2928 00:44:17.239537 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2929 00:44:17.239612 0 15 0 | B1->B0 | 2727 3434 | 1 1 | (1 1) (1 1)
2930 00:44:17.239687 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2931 00:44:17.239761 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2932 00:44:17.239836 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2933 00:44:17.239910 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2934 00:44:17.239986 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2935 00:44:17.240062 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
2936 00:44:17.240137 0 15 28 | B1->B0 | 3434 2929 | 1 1 | (1 1) (0 0)
2937 00:44:17.240217 1 0 0 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
2938 00:44:17.240294 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2939 00:44:17.240369 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2940 00:44:17.240444 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2941 00:44:17.240519 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2942 00:44:17.240594 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2943 00:44:17.240692 1 0 24 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (1 1)
2944 00:44:17.240781 1 0 28 | B1->B0 | 2727 4040 | 0 0 | (0 0) (0 0)
2945 00:44:17.240856 1 1 0 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
2946 00:44:17.240931 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2947 00:44:17.241016 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2948 00:44:17.241166 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2949 00:44:17.241261 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2950 00:44:17.241315 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2951 00:44:17.241363 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2952 00:44:17.241410 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2953 00:44:17.241648 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2954 00:44:17.241703 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2955 00:44:17.241841 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2956 00:44:17.241890 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2957 00:44:17.241938 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2958 00:44:17.241985 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2959 00:44:17.242031 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2960 00:44:17.242078 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2961 00:44:17.242127 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2962 00:44:17.242175 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2963 00:44:17.242262 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2964 00:44:17.242340 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2965 00:44:17.242416 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2966 00:44:17.242491 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2967 00:44:17.242568 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2968 00:44:17.242704 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2969 00:44:17.242814 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2970 00:44:17.242902 Total UI for P1: 0, mck2ui 16
2971 00:44:17.242979 best dqsien dly found for B0: ( 1, 3, 26)
2972 00:44:17.243055 Total UI for P1: 0, mck2ui 16
2973 00:44:17.243130 best dqsien dly found for B1: ( 1, 3, 30)
2974 00:44:17.243205 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2975 00:44:17.243279 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2976 00:44:17.243353
2977 00:44:17.243427 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2978 00:44:17.243502 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2979 00:44:17.243577 [Gating] SW calibration Done
2980 00:44:17.243651 ==
2981 00:44:17.243725 Dram Type= 6, Freq= 0, CH_0, rank 1
2982 00:44:17.243800 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2983 00:44:17.243875 ==
2984 00:44:17.243950 RX Vref Scan: 0
2985 00:44:17.244026
2986 00:44:17.244102 RX Vref 0 -> 0, step: 1
2987 00:44:17.244176
2988 00:44:17.244250 RX Delay -40 -> 252, step: 8
2989 00:44:17.244324 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2990 00:44:17.244399 iDelay=200, Bit 1, Center 111 (32 ~ 191) 160
2991 00:44:17.244474 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2992 00:44:17.244549 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2993 00:44:17.244624 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2994 00:44:17.244721 iDelay=200, Bit 5, Center 95 (24 ~ 167) 144
2995 00:44:17.244769 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
2996 00:44:17.244816 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2997 00:44:17.244876 iDelay=200, Bit 8, Center 87 (16 ~ 159) 144
2998 00:44:17.244926 iDelay=200, Bit 9, Center 83 (8 ~ 159) 152
2999 00:44:17.244972 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
3000 00:44:17.245039 iDelay=200, Bit 11, Center 91 (16 ~ 167) 152
3001 00:44:17.245088 iDelay=200, Bit 12, Center 107 (32 ~ 183) 152
3002 00:44:17.245143 iDelay=200, Bit 13, Center 107 (32 ~ 183) 152
3003 00:44:17.245197 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3004 00:44:17.245248 iDelay=200, Bit 15, Center 107 (32 ~ 183) 152
3005 00:44:17.387472 ==
3006 00:44:17.387892 Dram Type= 6, Freq= 0, CH_0, rank 1
3007 00:44:17.388187 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3008 00:44:17.388459 ==
3009 00:44:17.388793 DQS Delay:
3010 00:44:17.389190 DQS0 = 0, DQS1 = 0
3011 00:44:17.389694 DQM Delay:
3012 00:44:17.390173 DQM0 = 111, DQM1 = 99
3013 00:44:17.390453 DQ Delay:
3014 00:44:17.390706 DQ0 =111, DQ1 =111, DQ2 =111, DQ3 =107
3015 00:44:17.390957 DQ4 =115, DQ5 =95, DQ6 =119, DQ7 =123
3016 00:44:17.391203 DQ8 =87, DQ9 =83, DQ10 =103, DQ11 =91
3017 00:44:17.391451 DQ12 =107, DQ13 =107, DQ14 =111, DQ15 =107
3018 00:44:17.391693
3019 00:44:17.391943
3020 00:44:17.392187 ==
3021 00:44:17.392431 Dram Type= 6, Freq= 0, CH_0, rank 1
3022 00:44:17.392712 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3023 00:44:17.392971 ==
3024 00:44:17.393216
3025 00:44:17.393456
3026 00:44:17.393695 TX Vref Scan disable
3027 00:44:17.393937 == TX Byte 0 ==
3028 00:44:17.394181 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
3029 00:44:17.394423 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
3030 00:44:17.394665 == TX Byte 1 ==
3031 00:44:17.394902 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3032 00:44:17.395143 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3033 00:44:17.395385 ==
3034 00:44:17.395627 Dram Type= 6, Freq= 0, CH_0, rank 1
3035 00:44:17.395869 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3036 00:44:17.396111 ==
3037 00:44:17.396351 TX Vref=22, minBit 0, minWin=26, winSum=425
3038 00:44:17.396595 TX Vref=24, minBit 5, minWin=26, winSum=430
3039 00:44:17.396891 TX Vref=26, minBit 1, minWin=26, winSum=435
3040 00:44:17.397138 TX Vref=28, minBit 5, minWin=26, winSum=440
3041 00:44:17.397380 TX Vref=30, minBit 8, minWin=26, winSum=439
3042 00:44:17.397620 TX Vref=32, minBit 13, minWin=26, winSum=440
3043 00:44:17.397863 [TxChooseVref] Worse bit 5, Min win 26, Win sum 440, Final Vref 28
3044 00:44:17.398107
3045 00:44:17.398342 Final TX Range 1 Vref 28
3046 00:44:17.398581
3047 00:44:17.398818 ==
3048 00:44:17.399059 Dram Type= 6, Freq= 0, CH_0, rank 1
3049 00:44:17.399298 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3050 00:44:17.399537 ==
3051 00:44:17.399773
3052 00:44:17.400009
3053 00:44:17.400248 TX Vref Scan disable
3054 00:44:17.400489 == TX Byte 0 ==
3055 00:44:17.400764 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
3056 00:44:17.401017 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
3057 00:44:17.401258 == TX Byte 1 ==
3058 00:44:17.401496 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3059 00:44:17.401741 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3060 00:44:17.401979
3061 00:44:17.402216 [DATLAT]
3062 00:44:17.402457 Freq=1200, CH0 RK1
3063 00:44:17.402698
3064 00:44:17.402940 DATLAT Default: 0xd
3065 00:44:17.403239 0, 0xFFFF, sum = 0
3066 00:44:17.403492 1, 0xFFFF, sum = 0
3067 00:44:17.403738 2, 0xFFFF, sum = 0
3068 00:44:17.403986 3, 0xFFFF, sum = 0
3069 00:44:17.404230 4, 0xFFFF, sum = 0
3070 00:44:17.404472 5, 0xFFFF, sum = 0
3071 00:44:17.404747 6, 0xFFFF, sum = 0
3072 00:44:17.405000 7, 0xFFFF, sum = 0
3073 00:44:17.405243 8, 0xFFFF, sum = 0
3074 00:44:17.405485 9, 0xFFFF, sum = 0
3075 00:44:17.405730 10, 0xFFFF, sum = 0
3076 00:44:17.405977 11, 0xFFFF, sum = 0
3077 00:44:17.406220 12, 0x0, sum = 1
3078 00:44:17.406463 13, 0x0, sum = 2
3079 00:44:17.406706 14, 0x0, sum = 3
3080 00:44:17.406951 15, 0x0, sum = 4
3081 00:44:17.407195 best_step = 13
3082 00:44:17.407432
3083 00:44:17.407668 ==
3084 00:44:17.407907 Dram Type= 6, Freq= 0, CH_0, rank 1
3085 00:44:17.408496 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3086 00:44:17.408825 ==
3087 00:44:17.409079 RX Vref Scan: 0
3088 00:44:17.409324
3089 00:44:17.409677 RX Vref 0 -> 0, step: 1
3090 00:44:17.409935
3091 00:44:17.410177 RX Delay -37 -> 252, step: 4
3092 00:44:17.410422 iDelay=195, Bit 0, Center 108 (39 ~ 178) 140
3093 00:44:17.410665 iDelay=195, Bit 1, Center 110 (39 ~ 182) 144
3094 00:44:17.410880 iDelay=195, Bit 2, Center 108 (39 ~ 178) 140
3095 00:44:17.411055 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3096 00:44:17.411227 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3097 00:44:17.411400 iDelay=195, Bit 5, Center 100 (35 ~ 166) 132
3098 00:44:17.411569 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3099 00:44:17.411741 iDelay=195, Bit 7, Center 116 (43 ~ 190) 148
3100 00:44:17.411913 iDelay=195, Bit 8, Center 90 (19 ~ 162) 144
3101 00:44:17.412087 iDelay=195, Bit 9, Center 82 (11 ~ 154) 144
3102 00:44:17.412259 iDelay=195, Bit 10, Center 102 (31 ~ 174) 144
3103 00:44:17.412434 iDelay=195, Bit 11, Center 90 (23 ~ 158) 136
3104 00:44:17.412608 iDelay=195, Bit 12, Center 108 (39 ~ 178) 140
3105 00:44:17.412814 iDelay=195, Bit 13, Center 106 (35 ~ 178) 144
3106 00:44:17.412990 iDelay=195, Bit 14, Center 112 (47 ~ 178) 132
3107 00:44:17.413174 iDelay=195, Bit 15, Center 108 (39 ~ 178) 140
3108 00:44:17.413348 ==
3109 00:44:17.413519 Dram Type= 6, Freq= 0, CH_0, rank 1
3110 00:44:17.413692 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3111 00:44:17.413865 ==
3112 00:44:17.414035 DQS Delay:
3113 00:44:17.414206 DQS0 = 0, DQS1 = 0
3114 00:44:17.414379 DQM Delay:
3115 00:44:17.414552 DQM0 = 110, DQM1 = 99
3116 00:44:17.414724 DQ Delay:
3117 00:44:17.414899 DQ0 =108, DQ1 =110, DQ2 =108, DQ3 =108
3118 00:44:17.415071 DQ4 =112, DQ5 =100, DQ6 =120, DQ7 =116
3119 00:44:17.415243 DQ8 =90, DQ9 =82, DQ10 =102, DQ11 =90
3120 00:44:17.415415 DQ12 =108, DQ13 =106, DQ14 =112, DQ15 =108
3121 00:44:17.415586
3122 00:44:17.415747
3123 00:44:17.415875 [DQSOSCAuto] RK1, (LSB)MR18= 0x15fd, (MSB)MR19= 0x403, tDQSOscB0 = 411 ps tDQSOscB1 = 401 ps
3124 00:44:17.416015 CH0 RK1: MR19=403, MR18=15FD
3125 00:44:17.416147 CH0_RK1: MR19=0x403, MR18=0x15FD, DQSOSC=401, MR23=63, INC=40, DEC=27
3126 00:44:17.416276 [RxdqsGatingPostProcess] freq 1200
3127 00:44:17.416405 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3128 00:44:17.416536 best DQS0 dly(2T, 0.5T) = (0, 12)
3129 00:44:17.416686 best DQS1 dly(2T, 0.5T) = (0, 12)
3130 00:44:17.416822 best DQS0 P1 dly(2T, 0.5T) = (1, 0)
3131 00:44:17.416952 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3132 00:44:17.417081 best DQS0 dly(2T, 0.5T) = (0, 11)
3133 00:44:17.417210 best DQS1 dly(2T, 0.5T) = (0, 11)
3134 00:44:17.417341 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3135 00:44:17.417471 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3136 00:44:17.417602 Pre-setting of DQS Precalculation
3137 00:44:17.417734 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3138 00:44:17.417866 ==
3139 00:44:17.417997 Dram Type= 6, Freq= 0, CH_1, rank 0
3140 00:44:17.418126 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3141 00:44:17.418256 ==
3142 00:44:17.418384 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3143 00:44:17.418517 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3144 00:44:17.418651 [CA 0] Center 37 (8~67) winsize 60
3145 00:44:17.418783 [CA 1] Center 37 (7~68) winsize 62
3146 00:44:17.418935 [CA 2] Center 34 (4~64) winsize 61
3147 00:44:17.419068 [CA 3] Center 34 (4~64) winsize 61
3148 00:44:17.419199 [CA 4] Center 34 (4~64) winsize 61
3149 00:44:17.419328 [CA 5] Center 33 (3~63) winsize 61
3150 00:44:17.419456
3151 00:44:17.419587 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3152 00:44:17.419718
3153 00:44:17.419849 [CATrainingPosCal] consider 1 rank data
3154 00:44:17.419981 u2DelayCellTimex100 = 270/100 ps
3155 00:44:17.420112 CA0 delay=37 (8~67),Diff = 4 PI (19 cell)
3156 00:44:17.420243 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3157 00:44:17.420374 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3158 00:44:17.420505 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3159 00:44:17.420636 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3160 00:44:17.420767 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3161 00:44:17.420870
3162 00:44:17.420973 CA PerBit enable=1, Macro0, CA PI delay=33
3163 00:44:17.421081
3164 00:44:17.421185 [CBTSetCACLKResult] CA Dly = 33
3165 00:44:17.421290 CS Dly: 6 (0~37)
3166 00:44:17.421394 ==
3167 00:44:17.421500 Dram Type= 6, Freq= 0, CH_1, rank 1
3168 00:44:17.421608 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3169 00:44:17.421715 ==
3170 00:44:17.421817 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3171 00:44:17.421923 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
3172 00:44:17.422027 [CA 0] Center 37 (7~67) winsize 61
3173 00:44:17.422133 [CA 1] Center 37 (7~68) winsize 62
3174 00:44:17.422237 [CA 2] Center 34 (4~65) winsize 62
3175 00:44:17.422341 [CA 3] Center 33 (3~64) winsize 62
3176 00:44:17.422445 [CA 4] Center 34 (4~65) winsize 62
3177 00:44:17.422549 [CA 5] Center 32 (2~63) winsize 62
3178 00:44:17.422652
3179 00:44:17.422755 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3180 00:44:17.422858
3181 00:44:17.422960 [CATrainingPosCal] consider 2 rank data
3182 00:44:17.423065 u2DelayCellTimex100 = 270/100 ps
3183 00:44:17.423169 CA0 delay=37 (8~67),Diff = 4 PI (19 cell)
3184 00:44:17.423273 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3185 00:44:17.423377 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3186 00:44:17.423481 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3187 00:44:17.423586 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3188 00:44:17.423691 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3189 00:44:17.423794
3190 00:44:17.423896 CA PerBit enable=1, Macro0, CA PI delay=33
3191 00:44:17.424000
3192 00:44:17.424103 [CBTSetCACLKResult] CA Dly = 33
3193 00:44:17.424207 CS Dly: 7 (0~40)
3194 00:44:17.424309
3195 00:44:17.424411 ----->DramcWriteLeveling(PI) begin...
3196 00:44:17.424517 ==
3197 00:44:17.424622 Dram Type= 6, Freq= 0, CH_1, rank 0
3198 00:44:17.424736 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3199 00:44:17.424841 ==
3200 00:44:17.424946 Write leveling (Byte 0): 25 => 25
3201 00:44:17.425052 Write leveling (Byte 1): 29 => 29
3202 00:44:17.425156 DramcWriteLeveling(PI) end<-----
3203 00:44:17.425260
3204 00:44:17.425364 ==
3205 00:44:17.425469 Dram Type= 6, Freq= 0, CH_1, rank 0
3206 00:44:17.425574 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3207 00:44:17.425678 ==
3208 00:44:17.425782 [Gating] SW mode calibration
3209 00:44:17.426093 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3210 00:44:17.426195 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3211 00:44:17.426287 0 15 0 | B1->B0 | 3333 3232 | 0 0 | (0 0) (0 0)
3212 00:44:17.426377 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3213 00:44:17.426467 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3214 00:44:17.426555 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3215 00:44:17.426644 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3216 00:44:17.426733 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3217 00:44:17.426820 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
3218 00:44:17.426908 0 15 28 | B1->B0 | 2828 2b2b | 0 0 | (0 1) (1 0)
3219 00:44:17.426997 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
3220 00:44:17.427085 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3221 00:44:17.427174 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3222 00:44:17.427262 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3223 00:44:17.427383 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3224 00:44:17.427474 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3225 00:44:17.427563 1 0 24 | B1->B0 | 2827 2323 | 1 0 | (0 0) (0 0)
3226 00:44:17.427652 1 0 28 | B1->B0 | 3939 3635 | 1 1 | (1 1) (0 0)
3227 00:44:17.427740 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3228 00:44:17.427828 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3229 00:44:17.427917 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3230 00:44:17.428005 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3231 00:44:17.428094 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3232 00:44:17.428182 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3233 00:44:17.428270 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3234 00:44:17.428357 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3235 00:44:17.428445 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3236 00:44:17.428533 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3237 00:44:17.428622 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3238 00:44:17.428725 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3239 00:44:17.428815 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3240 00:44:17.428903 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3241 00:44:17.428990 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3242 00:44:17.429077 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3243 00:44:17.429165 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3244 00:44:17.429253 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3245 00:44:17.429341 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3246 00:44:17.429429 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3247 00:44:17.429516 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3248 00:44:17.429606 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3249 00:44:17.429694 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3250 00:44:17.429781 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3251 00:44:17.429869 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3252 00:44:17.429956 Total UI for P1: 0, mck2ui 16
3253 00:44:17.430044 best dqsien dly found for B0: ( 1, 3, 28)
3254 00:44:17.430133 Total UI for P1: 0, mck2ui 16
3255 00:44:17.430221 best dqsien dly found for B1: ( 1, 3, 26)
3256 00:44:17.430308 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3257 00:44:17.430397 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3258 00:44:17.430484
3259 00:44:17.430571 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3260 00:44:17.430659 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3261 00:44:17.430749 [Gating] SW calibration Done
3262 00:44:17.430823 ==
3263 00:44:17.430898 Dram Type= 6, Freq= 0, CH_1, rank 0
3264 00:44:17.430973 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3265 00:44:17.431048 ==
3266 00:44:17.431122 RX Vref Scan: 0
3267 00:44:17.431197
3268 00:44:17.431271 RX Vref 0 -> 0, step: 1
3269 00:44:17.431345
3270 00:44:17.431420 RX Delay -40 -> 252, step: 8
3271 00:44:17.431496 iDelay=200, Bit 0, Center 119 (40 ~ 199) 160
3272 00:44:17.431572 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3273 00:44:17.431648 iDelay=200, Bit 2, Center 99 (24 ~ 175) 152
3274 00:44:17.431724 iDelay=200, Bit 3, Center 111 (32 ~ 191) 160
3275 00:44:17.431798 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3276 00:44:17.431873 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3277 00:44:17.431948 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3278 00:44:17.432023 iDelay=200, Bit 7, Center 111 (32 ~ 191) 160
3279 00:44:17.432099 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3280 00:44:17.432174 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3281 00:44:17.432248 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
3282 00:44:17.432323 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3283 00:44:17.432398 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
3284 00:44:17.432473 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
3285 00:44:17.432549 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3286 00:44:17.432623 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3287 00:44:17.432704 ==
3288 00:44:17.432780 Dram Type= 6, Freq= 0, CH_1, rank 0
3289 00:44:17.432855 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3290 00:44:17.432929 ==
3291 00:44:17.433004 DQS Delay:
3292 00:44:17.433078 DQS0 = 0, DQS1 = 0
3293 00:44:17.433154 DQM Delay:
3294 00:44:17.433229 DQM0 = 113, DQM1 = 105
3295 00:44:17.433303 DQ Delay:
3296 00:44:17.433378 DQ0 =119, DQ1 =107, DQ2 =99, DQ3 =111
3297 00:44:17.433453 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =111
3298 00:44:17.433526 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
3299 00:44:17.433601 DQ12 =111, DQ13 =111, DQ14 =111, DQ15 =111
3300 00:44:17.433675
3301 00:44:17.433748
3302 00:44:17.433822 ==
3303 00:44:17.433897 Dram Type= 6, Freq= 0, CH_1, rank 0
3304 00:44:17.433973 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3305 00:44:17.434049 ==
3306 00:44:17.434123
3307 00:44:17.434197
3308 00:44:17.434271 TX Vref Scan disable
3309 00:44:17.434346 == TX Byte 0 ==
3310 00:44:17.434421 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3311 00:44:17.434496 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3312 00:44:17.434570 == TX Byte 1 ==
3313 00:44:17.434645 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3314 00:44:17.434927 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3315 00:44:17.435011 ==
3316 00:44:17.435088 Dram Type= 6, Freq= 0, CH_1, rank 0
3317 00:44:17.435164 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3318 00:44:17.435240 ==
3319 00:44:17.435316 TX Vref=22, minBit 11, minWin=24, winSum=411
3320 00:44:17.435392 TX Vref=24, minBit 8, minWin=24, winSum=415
3321 00:44:17.435469 TX Vref=26, minBit 11, minWin=24, winSum=416
3322 00:44:17.435545 TX Vref=28, minBit 9, minWin=25, winSum=424
3323 00:44:17.435622 TX Vref=30, minBit 9, minWin=25, winSum=420
3324 00:44:17.435705 TX Vref=32, minBit 8, minWin=25, winSum=424
3325 00:44:17.435771 [TxChooseVref] Worse bit 9, Min win 25, Win sum 424, Final Vref 28
3326 00:44:17.435838
3327 00:44:17.435904 Final TX Range 1 Vref 28
3328 00:44:17.435970
3329 00:44:17.436034 ==
3330 00:44:17.436099 Dram Type= 6, Freq= 0, CH_1, rank 0
3331 00:44:17.436165 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3332 00:44:17.436232 ==
3333 00:44:17.436296
3334 00:44:17.436361
3335 00:44:17.436426 TX Vref Scan disable
3336 00:44:17.436491 == TX Byte 0 ==
3337 00:44:17.436556 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3338 00:44:17.436622 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3339 00:44:17.436694 == TX Byte 1 ==
3340 00:44:17.436759 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3341 00:44:17.436825 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3342 00:44:17.436891
3343 00:44:17.436956 [DATLAT]
3344 00:44:17.437022 Freq=1200, CH1 RK0
3345 00:44:17.437087
3346 00:44:17.437155 DATLAT Default: 0xd
3347 00:44:17.437237 0, 0xFFFF, sum = 0
3348 00:44:17.437306 1, 0xFFFF, sum = 0
3349 00:44:17.437372 2, 0xFFFF, sum = 0
3350 00:44:17.437438 3, 0xFFFF, sum = 0
3351 00:44:17.437504 4, 0xFFFF, sum = 0
3352 00:44:17.437570 5, 0xFFFF, sum = 0
3353 00:44:17.437637 6, 0xFFFF, sum = 0
3354 00:44:17.437703 7, 0xFFFF, sum = 0
3355 00:44:17.437771 8, 0xFFFF, sum = 0
3356 00:44:17.437838 9, 0xFFFF, sum = 0
3357 00:44:17.437904 10, 0xFFFF, sum = 0
3358 00:44:17.437970 11, 0xFFFF, sum = 0
3359 00:44:17.438037 12, 0x0, sum = 1
3360 00:44:17.438104 13, 0x0, sum = 2
3361 00:44:17.438170 14, 0x0, sum = 3
3362 00:44:17.438236 15, 0x0, sum = 4
3363 00:44:17.438302 best_step = 13
3364 00:44:17.438367
3365 00:44:17.438430 ==
3366 00:44:17.438494 Dram Type= 6, Freq= 0, CH_1, rank 0
3367 00:44:17.438559 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3368 00:44:17.438624 ==
3369 00:44:17.438690 RX Vref Scan: 1
3370 00:44:17.438755
3371 00:44:17.438820 Set Vref Range= 32 -> 127
3372 00:44:17.438885
3373 00:44:17.438949 RX Vref 32 -> 127, step: 1
3374 00:44:17.439014
3375 00:44:17.439078 RX Delay -21 -> 252, step: 4
3376 00:44:17.439142
3377 00:44:17.439205 Set Vref, RX VrefLevel [Byte0]: 32
3378 00:44:17.439271 [Byte1]: 32
3379 00:44:17.439335
3380 00:44:17.439400 Set Vref, RX VrefLevel [Byte0]: 33
3381 00:44:17.439465 [Byte1]: 33
3382 00:44:17.439529
3383 00:44:17.439593 Set Vref, RX VrefLevel [Byte0]: 34
3384 00:44:17.439659 [Byte1]: 34
3385 00:44:17.439724
3386 00:44:17.439788 Set Vref, RX VrefLevel [Byte0]: 35
3387 00:44:17.439852 [Byte1]: 35
3388 00:44:17.439916
3389 00:44:17.439980 Set Vref, RX VrefLevel [Byte0]: 36
3390 00:44:17.440045 [Byte1]: 36
3391 00:44:17.440110
3392 00:44:17.440175 Set Vref, RX VrefLevel [Byte0]: 37
3393 00:44:17.440240 [Byte1]: 37
3394 00:44:17.440304
3395 00:44:17.440369 Set Vref, RX VrefLevel [Byte0]: 38
3396 00:44:17.440434 [Byte1]: 38
3397 00:44:17.440501
3398 00:44:17.440568 Set Vref, RX VrefLevel [Byte0]: 39
3399 00:44:17.440634 [Byte1]: 39
3400 00:44:17.440721
3401 00:44:17.440779 Set Vref, RX VrefLevel [Byte0]: 40
3402 00:44:17.440837 [Byte1]: 40
3403 00:44:17.440894
3404 00:44:17.440951 Set Vref, RX VrefLevel [Byte0]: 41
3405 00:44:17.441011 [Byte1]: 41
3406 00:44:17.441069
3407 00:44:17.441125 Set Vref, RX VrefLevel [Byte0]: 42
3408 00:44:17.441183 [Byte1]: 42
3409 00:44:17.441240
3410 00:44:17.441297 Set Vref, RX VrefLevel [Byte0]: 43
3411 00:44:17.441355 [Byte1]: 43
3412 00:44:17.441413
3413 00:44:17.441469 Set Vref, RX VrefLevel [Byte0]: 44
3414 00:44:17.441527 [Byte1]: 44
3415 00:44:17.441585
3416 00:44:17.441642 Set Vref, RX VrefLevel [Byte0]: 45
3417 00:44:17.441700 [Byte1]: 45
3418 00:44:17.441757
3419 00:44:17.441814 Set Vref, RX VrefLevel [Byte0]: 46
3420 00:44:17.441872 [Byte1]: 46
3421 00:44:17.441930
3422 00:44:17.441987 Set Vref, RX VrefLevel [Byte0]: 47
3423 00:44:17.442044 [Byte1]: 47
3424 00:44:17.442101
3425 00:44:17.442158 Set Vref, RX VrefLevel [Byte0]: 48
3426 00:44:17.442216 [Byte1]: 48
3427 00:44:17.442273
3428 00:44:17.442330 Set Vref, RX VrefLevel [Byte0]: 49
3429 00:44:17.442387 [Byte1]: 49
3430 00:44:17.442444
3431 00:44:17.442501 Set Vref, RX VrefLevel [Byte0]: 50
3432 00:44:17.442559 [Byte1]: 50
3433 00:44:17.442615
3434 00:44:17.442671 Set Vref, RX VrefLevel [Byte0]: 51
3435 00:44:17.442728 [Byte1]: 51
3436 00:44:17.442786
3437 00:44:17.442843 Set Vref, RX VrefLevel [Byte0]: 52
3438 00:44:17.442901 [Byte1]: 52
3439 00:44:17.442959
3440 00:44:17.443017 Set Vref, RX VrefLevel [Byte0]: 53
3441 00:44:17.443074 [Byte1]: 53
3442 00:44:17.443131
3443 00:44:17.443188 Set Vref, RX VrefLevel [Byte0]: 54
3444 00:44:17.443246 [Byte1]: 54
3445 00:44:17.443303
3446 00:44:17.443360 Set Vref, RX VrefLevel [Byte0]: 55
3447 00:44:17.443420 [Byte1]: 55
3448 00:44:17.443478
3449 00:44:17.443535 Set Vref, RX VrefLevel [Byte0]: 56
3450 00:44:17.443592 [Byte1]: 56
3451 00:44:17.443649
3452 00:44:17.443706 Set Vref, RX VrefLevel [Byte0]: 57
3453 00:44:17.443764 [Byte1]: 57
3454 00:44:17.443822
3455 00:44:17.443879 Set Vref, RX VrefLevel [Byte0]: 58
3456 00:44:17.443936 [Byte1]: 58
3457 00:44:17.443994
3458 00:44:17.444051 Set Vref, RX VrefLevel [Byte0]: 59
3459 00:44:17.444109 [Byte1]: 59
3460 00:44:17.444165
3461 00:44:17.444222 Set Vref, RX VrefLevel [Byte0]: 60
3462 00:44:17.444280 [Byte1]: 60
3463 00:44:17.444338
3464 00:44:17.444395 Set Vref, RX VrefLevel [Byte0]: 61
3465 00:44:17.444453 [Byte1]: 61
3466 00:44:17.444510
3467 00:44:17.444568 Set Vref, RX VrefLevel [Byte0]: 62
3468 00:44:17.444625 [Byte1]: 62
3469 00:44:17.444693
3470 00:44:17.444750 Set Vref, RX VrefLevel [Byte0]: 63
3471 00:44:17.444808 [Byte1]: 63
3472 00:44:17.444866
3473 00:44:17.444923 Set Vref, RX VrefLevel [Byte0]: 64
3474 00:44:17.444982 [Byte1]: 64
3475 00:44:17.445039
3476 00:44:17.445096 Set Vref, RX VrefLevel [Byte0]: 65
3477 00:44:17.445154 [Byte1]: 65
3478 00:44:17.445212
3479 00:44:17.445270 Set Vref, RX VrefLevel [Byte0]: 66
3480 00:44:17.445527 [Byte1]: 66
3481 00:44:17.445595
3482 00:44:17.445654 Set Vref, RX VrefLevel [Byte0]: 67
3483 00:44:17.445723 [Byte1]: 67
3484 00:44:17.445775
3485 00:44:17.445827 Set Vref, RX VrefLevel [Byte0]: 68
3486 00:44:17.445879 [Byte1]: 68
3487 00:44:17.445932
3488 00:44:17.445985 Final RX Vref Byte 0 = 57 to rank0
3489 00:44:17.446039 Final RX Vref Byte 1 = 53 to rank0
3490 00:44:17.446092 Final RX Vref Byte 0 = 57 to rank1
3491 00:44:17.446144 Final RX Vref Byte 1 = 53 to rank1==
3492 00:44:17.446197 Dram Type= 6, Freq= 0, CH_1, rank 0
3493 00:44:17.446249 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3494 00:44:17.446302 ==
3495 00:44:17.446354 DQS Delay:
3496 00:44:17.446406 DQS0 = 0, DQS1 = 0
3497 00:44:17.446457 DQM Delay:
3498 00:44:17.446509 DQM0 = 114, DQM1 = 106
3499 00:44:17.446562 DQ Delay:
3500 00:44:17.446613 DQ0 =116, DQ1 =108, DQ2 =104, DQ3 =112
3501 00:44:17.446665 DQ4 =112, DQ5 =124, DQ6 =126, DQ7 =112
3502 00:44:17.446717 DQ8 =94, DQ9 =98, DQ10 =104, DQ11 =102
3503 00:44:17.446769 DQ12 =116, DQ13 =112, DQ14 =116, DQ15 =112
3504 00:44:17.446820
3505 00:44:17.446872
3506 00:44:17.446923 [DQSOSCAuto] RK0, (LSB)MR18= 0xf3fa, (MSB)MR19= 0x303, tDQSOscB0 = 412 ps tDQSOscB1 = 415 ps
3507 00:44:17.446976 CH1 RK0: MR19=303, MR18=F3FA
3508 00:44:17.447029 CH1_RK0: MR19=0x303, MR18=0xF3FA, DQSOSC=412, MR23=63, INC=38, DEC=25
3509 00:44:17.447081
3510 00:44:17.447132 ----->DramcWriteLeveling(PI) begin...
3511 00:44:17.447185 ==
3512 00:44:17.447237 Dram Type= 6, Freq= 0, CH_1, rank 1
3513 00:44:17.447289 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3514 00:44:17.447341 ==
3515 00:44:17.447392 Write leveling (Byte 0): 25 => 25
3516 00:44:17.447444 Write leveling (Byte 1): 26 => 26
3517 00:44:17.447496 DramcWriteLeveling(PI) end<-----
3518 00:44:17.447548
3519 00:44:17.447599 ==
3520 00:44:17.447650 Dram Type= 6, Freq= 0, CH_1, rank 1
3521 00:44:17.447702 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3522 00:44:17.447754 ==
3523 00:44:17.447806 [Gating] SW mode calibration
3524 00:44:17.447859 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3525 00:44:17.447912 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3526 00:44:17.447965 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3527 00:44:17.448017 0 15 4 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
3528 00:44:17.448069 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3529 00:44:17.448121 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3530 00:44:17.448173 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3531 00:44:17.448225 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3532 00:44:17.448278 0 15 24 | B1->B0 | 3333 2525 | 1 0 | (1 0) (0 0)
3533 00:44:17.448330 0 15 28 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
3534 00:44:17.448382 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3535 00:44:17.448434 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3536 00:44:17.448486 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3537 00:44:17.448539 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3538 00:44:17.448590 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3539 00:44:17.448647 1 0 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
3540 00:44:17.448701 1 0 24 | B1->B0 | 2d2d 4646 | 0 0 | (0 0) (0 0)
3541 00:44:17.448753 1 0 28 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
3542 00:44:17.448805 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3543 00:44:17.448857 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3544 00:44:17.448909 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3545 00:44:17.448961 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3546 00:44:17.449013 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3547 00:44:17.449065 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3548 00:44:17.449117 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3549 00:44:17.449169 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3550 00:44:17.449221 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3551 00:44:17.449274 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3552 00:44:17.449327 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3553 00:44:17.449378 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3554 00:44:17.449431 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3555 00:44:17.449483 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3556 00:44:17.449535 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3557 00:44:17.449587 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3558 00:44:17.449640 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3559 00:44:17.449692 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3560 00:44:17.449745 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3561 00:44:17.449797 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3562 00:44:17.449849 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3563 00:44:17.449902 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3564 00:44:17.449953 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3565 00:44:17.450006 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3566 00:44:17.450058 Total UI for P1: 0, mck2ui 16
3567 00:44:17.450112 best dqsien dly found for B0: ( 1, 3, 22)
3568 00:44:17.450164 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3569 00:44:17.450217 Total UI for P1: 0, mck2ui 16
3570 00:44:17.450269 best dqsien dly found for B1: ( 1, 3, 26)
3571 00:44:17.450321 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3572 00:44:17.450373 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3573 00:44:17.450424
3574 00:44:17.450475 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3575 00:44:17.450527 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3576 00:44:17.450578 [Gating] SW calibration Done
3577 00:44:17.450630 ==
3578 00:44:17.450693 Dram Type= 6, Freq= 0, CH_1, rank 1
3579 00:44:17.450742 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3580 00:44:17.450790 ==
3581 00:44:17.450837 RX Vref Scan: 0
3582 00:44:17.450884
3583 00:44:17.450931 RX Vref 0 -> 0, step: 1
3584 00:44:17.450977
3585 00:44:17.451024 RX Delay -40 -> 252, step: 8
3586 00:44:17.451071 iDelay=200, Bit 0, Center 111 (32 ~ 191) 160
3587 00:44:17.451119 iDelay=200, Bit 1, Center 107 (40 ~ 175) 136
3588 00:44:17.451353 iDelay=200, Bit 2, Center 99 (24 ~ 175) 152
3589 00:44:17.451407 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
3590 00:44:17.451457 iDelay=200, Bit 4, Center 107 (32 ~ 183) 152
3591 00:44:17.451505 iDelay=200, Bit 5, Center 119 (40 ~ 199) 160
3592 00:44:17.451552 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
3593 00:44:17.451600 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3594 00:44:17.451648 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3595 00:44:17.451695 iDelay=200, Bit 9, Center 99 (24 ~ 175) 152
3596 00:44:17.451743 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
3597 00:44:17.451791 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3598 00:44:17.451838 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
3599 00:44:17.451886 iDelay=200, Bit 13, Center 115 (40 ~ 191) 152
3600 00:44:17.451934 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3601 00:44:17.451982 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3602 00:44:17.452029 ==
3603 00:44:17.452076 Dram Type= 6, Freq= 0, CH_1, rank 1
3604 00:44:17.452124 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3605 00:44:17.452171 ==
3606 00:44:17.452218 DQS Delay:
3607 00:44:17.452266 DQS0 = 0, DQS1 = 0
3608 00:44:17.452314 DQM Delay:
3609 00:44:17.452361 DQM0 = 110, DQM1 = 106
3610 00:44:17.452409 DQ Delay:
3611 00:44:17.452457 DQ0 =111, DQ1 =107, DQ2 =99, DQ3 =107
3612 00:44:17.452504 DQ4 =107, DQ5 =119, DQ6 =119, DQ7 =111
3613 00:44:17.452551 DQ8 =95, DQ9 =99, DQ10 =107, DQ11 =103
3614 00:44:17.452599 DQ12 =111, DQ13 =115, DQ14 =111, DQ15 =111
3615 00:44:17.452650
3616 00:44:17.452698
3617 00:44:17.452745 ==
3618 00:44:17.452792 Dram Type= 6, Freq= 0, CH_1, rank 1
3619 00:44:17.452840 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3620 00:44:17.452888 ==
3621 00:44:17.452936
3622 00:44:17.452982
3623 00:44:17.453029 TX Vref Scan disable
3624 00:44:17.453077 == TX Byte 0 ==
3625 00:44:17.453124 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3626 00:44:17.453172 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3627 00:44:17.453220 == TX Byte 1 ==
3628 00:44:17.453267 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3629 00:44:17.453314 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3630 00:44:17.453362 ==
3631 00:44:17.453408 Dram Type= 6, Freq= 0, CH_1, rank 1
3632 00:44:17.453456 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3633 00:44:17.453503 ==
3634 00:44:17.453550 TX Vref=22, minBit 9, minWin=25, winSum=420
3635 00:44:17.453599 TX Vref=24, minBit 9, minWin=25, winSum=422
3636 00:44:17.453647 TX Vref=26, minBit 9, minWin=26, winSum=435
3637 00:44:17.453695 TX Vref=28, minBit 9, minWin=26, winSum=432
3638 00:44:17.453743 TX Vref=30, minBit 8, minWin=26, winSum=431
3639 00:44:17.453790 TX Vref=32, minBit 8, minWin=26, winSum=430
3640 00:44:17.453838 [TxChooseVref] Worse bit 9, Min win 26, Win sum 435, Final Vref 26
3641 00:44:17.453887
3642 00:44:17.453934 Final TX Range 1 Vref 26
3643 00:44:17.453982
3644 00:44:17.454032 ==
3645 00:44:17.454079 Dram Type= 6, Freq= 0, CH_1, rank 1
3646 00:44:17.454126 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3647 00:44:17.454173 ==
3648 00:44:17.454221
3649 00:44:17.454268
3650 00:44:17.454315 TX Vref Scan disable
3651 00:44:17.454362 == TX Byte 0 ==
3652 00:44:17.454409 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3653 00:44:17.454457 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3654 00:44:17.454504 == TX Byte 1 ==
3655 00:44:17.454551 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3656 00:44:17.454599 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3657 00:44:17.454646
3658 00:44:17.454694 [DATLAT]
3659 00:44:17.454741 Freq=1200, CH1 RK1
3660 00:44:17.454788
3661 00:44:17.454835 DATLAT Default: 0xd
3662 00:44:17.454881 0, 0xFFFF, sum = 0
3663 00:44:17.454930 1, 0xFFFF, sum = 0
3664 00:44:17.454978 2, 0xFFFF, sum = 0
3665 00:44:17.455026 3, 0xFFFF, sum = 0
3666 00:44:17.455074 4, 0xFFFF, sum = 0
3667 00:44:17.455122 5, 0xFFFF, sum = 0
3668 00:44:17.455170 6, 0xFFFF, sum = 0
3669 00:44:17.455218 7, 0xFFFF, sum = 0
3670 00:44:17.455265 8, 0xFFFF, sum = 0
3671 00:44:17.455313 9, 0xFFFF, sum = 0
3672 00:44:17.455361 10, 0xFFFF, sum = 0
3673 00:44:17.455409 11, 0xFFFF, sum = 0
3674 00:44:17.455457 12, 0x0, sum = 1
3675 00:44:17.455505 13, 0x0, sum = 2
3676 00:44:17.455553 14, 0x0, sum = 3
3677 00:44:17.455630 15, 0x0, sum = 4
3678 00:44:17.455699 best_step = 13
3679 00:44:17.455761
3680 00:44:17.455808 ==
3681 00:44:17.455855 Dram Type= 6, Freq= 0, CH_1, rank 1
3682 00:44:17.455902 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3683 00:44:17.455952 ==
3684 00:44:17.456007 RX Vref Scan: 0
3685 00:44:17.456060
3686 00:44:17.456110 RX Vref 0 -> 0, step: 1
3687 00:44:17.456164
3688 00:44:17.456219 RX Delay -21 -> 252, step: 4
3689 00:44:17.456273 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3690 00:44:17.456325 iDelay=195, Bit 1, Center 108 (43 ~ 174) 132
3691 00:44:17.456373 iDelay=195, Bit 2, Center 100 (31 ~ 170) 140
3692 00:44:17.456421 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3693 00:44:17.456467 iDelay=195, Bit 4, Center 108 (39 ~ 178) 140
3694 00:44:17.456514 iDelay=195, Bit 5, Center 118 (43 ~ 194) 152
3695 00:44:17.456560 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3696 00:44:17.456613 iDelay=195, Bit 7, Center 110 (43 ~ 178) 136
3697 00:44:17.456674 iDelay=195, Bit 8, Center 96 (31 ~ 162) 132
3698 00:44:17.456763 iDelay=195, Bit 9, Center 100 (35 ~ 166) 132
3699 00:44:17.456810 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
3700 00:44:17.456858 iDelay=195, Bit 11, Center 104 (39 ~ 170) 132
3701 00:44:17.456914 iDelay=195, Bit 12, Center 118 (55 ~ 182) 128
3702 00:44:17.456967 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3703 00:44:17.457015 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3704 00:44:17.457068 iDelay=195, Bit 15, Center 120 (55 ~ 186) 132
3705 00:44:17.457122 ==
3706 00:44:17.457169 Dram Type= 6, Freq= 0, CH_1, rank 1
3707 00:44:17.457223 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3708 00:44:17.457271 ==
3709 00:44:17.457318 DQS Delay:
3710 00:44:17.457371 DQS0 = 0, DQS1 = 0
3711 00:44:17.457418 DQM Delay:
3712 00:44:17.457465 DQM0 = 111, DQM1 = 110
3713 00:44:17.457511 DQ Delay:
3714 00:44:17.457567 DQ0 =114, DQ1 =108, DQ2 =100, DQ3 =108
3715 00:44:17.457621 DQ4 =108, DQ5 =118, DQ6 =122, DQ7 =110
3716 00:44:17.457673 DQ8 =96, DQ9 =100, DQ10 =110, DQ11 =104
3717 00:44:17.457722 DQ12 =118, DQ13 =118, DQ14 =118, DQ15 =120
3718 00:44:17.457775
3719 00:44:17.457823
3720 00:44:17.457869 [DQSOSCAuto] RK1, (LSB)MR18= 0xfd0c, (MSB)MR19= 0x304, tDQSOscB0 = 405 ps tDQSOscB1 = 411 ps
3721 00:44:17.457917 CH1 RK1: MR19=304, MR18=FD0C
3722 00:44:17.457963 CH1_RK1: MR19=0x304, MR18=0xFD0C, DQSOSC=405, MR23=63, INC=39, DEC=26
3723 00:44:17.458010 [RxdqsGatingPostProcess] freq 1200
3724 00:44:17.458057 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3725 00:44:17.458105 best DQS0 dly(2T, 0.5T) = (0, 11)
3726 00:44:17.458340 best DQS1 dly(2T, 0.5T) = (0, 11)
3727 00:44:17.458395 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3728 00:44:17.458443 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3729 00:44:17.458490 best DQS0 dly(2T, 0.5T) = (0, 11)
3730 00:44:17.458537 best DQS1 dly(2T, 0.5T) = (0, 11)
3731 00:44:17.458583 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3732 00:44:17.458629 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3733 00:44:17.458677 Pre-setting of DQS Precalculation
3734 00:44:17.458723 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3735 00:44:17.458771 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3736 00:44:17.458819 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3737 00:44:17.458866
3738 00:44:17.458911
3739 00:44:17.458957 [Calibration Summary] 2400 Mbps
3740 00:44:17.459003 CH 0, Rank 0
3741 00:44:17.459050 SW Impedance : PASS
3742 00:44:17.459097 DUTY Scan : NO K
3743 00:44:17.459144 ZQ Calibration : PASS
3744 00:44:17.459190 Jitter Meter : NO K
3745 00:44:17.459236 CBT Training : PASS
3746 00:44:17.459282 Write leveling : PASS
3747 00:44:17.459329 RX DQS gating : PASS
3748 00:44:17.459375 RX DQ/DQS(RDDQC) : PASS
3749 00:44:17.459421 TX DQ/DQS : PASS
3750 00:44:17.459467 RX DATLAT : PASS
3751 00:44:17.459513 RX DQ/DQS(Engine): PASS
3752 00:44:17.459559 TX OE : NO K
3753 00:44:17.459605 All Pass.
3754 00:44:17.459651
3755 00:44:17.459696 CH 0, Rank 1
3756 00:44:17.459742 SW Impedance : PASS
3757 00:44:17.459788 DUTY Scan : NO K
3758 00:44:17.459834 ZQ Calibration : PASS
3759 00:44:17.459881 Jitter Meter : NO K
3760 00:44:17.459926 CBT Training : PASS
3761 00:44:17.459972 Write leveling : PASS
3762 00:44:17.460018 RX DQS gating : PASS
3763 00:44:17.460064 RX DQ/DQS(RDDQC) : PASS
3764 00:44:17.460111 TX DQ/DQS : PASS
3765 00:44:17.460158 RX DATLAT : PASS
3766 00:44:17.460204 RX DQ/DQS(Engine): PASS
3767 00:44:17.460251 TX OE : NO K
3768 00:44:17.460298 All Pass.
3769 00:44:17.460344
3770 00:44:17.460389 CH 1, Rank 0
3771 00:44:17.460435 SW Impedance : PASS
3772 00:44:17.460481 DUTY Scan : NO K
3773 00:44:17.460527 ZQ Calibration : PASS
3774 00:44:17.460573 Jitter Meter : NO K
3775 00:44:17.460620 CBT Training : PASS
3776 00:44:17.460673 Write leveling : PASS
3777 00:44:17.460758 RX DQS gating : PASS
3778 00:44:17.460804 RX DQ/DQS(RDDQC) : PASS
3779 00:44:17.460850 TX DQ/DQS : PASS
3780 00:44:17.460896 RX DATLAT : PASS
3781 00:44:17.460945 RX DQ/DQS(Engine): PASS
3782 00:44:17.460991 TX OE : NO K
3783 00:44:17.461037 All Pass.
3784 00:44:17.461083
3785 00:44:17.461129 CH 1, Rank 1
3786 00:44:17.461174 SW Impedance : PASS
3787 00:44:17.461221 DUTY Scan : NO K
3788 00:44:17.461267 ZQ Calibration : PASS
3789 00:44:17.461313 Jitter Meter : NO K
3790 00:44:17.461360 CBT Training : PASS
3791 00:44:17.461406 Write leveling : PASS
3792 00:44:17.461452 RX DQS gating : PASS
3793 00:44:17.461497 RX DQ/DQS(RDDQC) : PASS
3794 00:44:17.461543 TX DQ/DQS : PASS
3795 00:44:17.461589 RX DATLAT : PASS
3796 00:44:17.461636 RX DQ/DQS(Engine): PASS
3797 00:44:17.461682 TX OE : NO K
3798 00:44:17.461728 All Pass.
3799 00:44:17.461774
3800 00:44:17.461819 DramC Write-DBI off
3801 00:44:17.461865 PER_BANK_REFRESH: Hybrid Mode
3802 00:44:17.461912 TX_TRACKING: ON
3803 00:44:17.461959 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3804 00:44:17.462006 [FAST_K] Save calibration result to emmc
3805 00:44:17.462053 dramc_set_vcore_voltage set vcore to 650000
3806 00:44:17.462099 Read voltage for 600, 5
3807 00:44:17.462146 Vio18 = 0
3808 00:44:17.462192 Vcore = 650000
3809 00:44:17.462238 Vdram = 0
3810 00:44:17.462284 Vddq = 0
3811 00:44:17.462329 Vmddr = 0
3812 00:44:17.462376 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3813 00:44:17.462422 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3814 00:44:17.462468 MEM_TYPE=3, freq_sel=19
3815 00:44:17.462514 sv_algorithm_assistance_LP4_1600
3816 00:44:17.462560 ============ PULL DRAM RESETB DOWN ============
3817 00:44:17.462607 ========== PULL DRAM RESETB DOWN end =========
3818 00:44:17.462653 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3819 00:44:17.462700 ===================================
3820 00:44:17.462746 LPDDR4 DRAM CONFIGURATION
3821 00:44:17.462792 ===================================
3822 00:44:17.462838 EX_ROW_EN[0] = 0x0
3823 00:44:17.462884 EX_ROW_EN[1] = 0x0
3824 00:44:17.462930 LP4Y_EN = 0x0
3825 00:44:17.462976 WORK_FSP = 0x0
3826 00:44:17.463022 WL = 0x2
3827 00:44:17.463068 RL = 0x2
3828 00:44:17.463114 BL = 0x2
3829 00:44:17.463160 RPST = 0x0
3830 00:44:17.463206 RD_PRE = 0x0
3831 00:44:17.463252 WR_PRE = 0x1
3832 00:44:17.463298 WR_PST = 0x0
3833 00:44:17.463344 DBI_WR = 0x0
3834 00:44:17.463389 DBI_RD = 0x0
3835 00:44:17.463434 OTF = 0x1
3836 00:44:17.463480 ===================================
3837 00:44:17.463527 ===================================
3838 00:44:17.463574 ANA top config
3839 00:44:17.463619 ===================================
3840 00:44:17.463666 DLL_ASYNC_EN = 0
3841 00:44:17.463713 ALL_SLAVE_EN = 1
3842 00:44:17.463759 NEW_RANK_MODE = 1
3843 00:44:17.463806 DLL_IDLE_MODE = 1
3844 00:44:17.463851 LP45_APHY_COMB_EN = 1
3845 00:44:17.463897 TX_ODT_DIS = 1
3846 00:44:17.463943 NEW_8X_MODE = 1
3847 00:44:17.463989 ===================================
3848 00:44:17.464037 ===================================
3849 00:44:17.464083 data_rate = 1200
3850 00:44:17.464129 CKR = 1
3851 00:44:17.464175 DQ_P2S_RATIO = 8
3852 00:44:17.464221 ===================================
3853 00:44:17.464267 CA_P2S_RATIO = 8
3854 00:44:17.464313 DQ_CA_OPEN = 0
3855 00:44:17.464358 DQ_SEMI_OPEN = 0
3856 00:44:17.464404 CA_SEMI_OPEN = 0
3857 00:44:17.464450 CA_FULL_RATE = 0
3858 00:44:17.464495 DQ_CKDIV4_EN = 1
3859 00:44:17.464542 CA_CKDIV4_EN = 1
3860 00:44:17.464587 CA_PREDIV_EN = 0
3861 00:44:17.464634 PH8_DLY = 0
3862 00:44:17.464727 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3863 00:44:17.464774 DQ_AAMCK_DIV = 4
3864 00:44:17.464819 CA_AAMCK_DIV = 4
3865 00:44:17.464865 CA_ADMCK_DIV = 4
3866 00:44:17.464911 DQ_TRACK_CA_EN = 0
3867 00:44:17.464958 CA_PICK = 600
3868 00:44:17.465004 CA_MCKIO = 600
3869 00:44:17.465050 MCKIO_SEMI = 0
3870 00:44:17.465096 PLL_FREQ = 2288
3871 00:44:17.465143 DQ_UI_PI_RATIO = 32
3872 00:44:17.465372 CA_UI_PI_RATIO = 0
3873 00:44:17.465426 ===================================
3874 00:44:17.465474 ===================================
3875 00:44:17.465522 memory_type:LPDDR4
3876 00:44:17.465568 GP_NUM : 10
3877 00:44:17.465615 SRAM_EN : 1
3878 00:44:17.465661 MD32_EN : 0
3879 00:44:17.465707 ===================================
3880 00:44:17.465754 [ANA_INIT] >>>>>>>>>>>>>>
3881 00:44:17.465800 <<<<<< [CONFIGURE PHASE]: ANA_TX
3882 00:44:17.465846 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3883 00:44:17.465892 ===================================
3884 00:44:17.465939 data_rate = 1200,PCW = 0X5800
3885 00:44:17.465986 ===================================
3886 00:44:17.466032 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3887 00:44:17.466080 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3888 00:44:17.466127 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3889 00:44:17.466175 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3890 00:44:17.466221 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3891 00:44:17.466267 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3892 00:44:17.466313 [ANA_INIT] flow start
3893 00:44:17.466359 [ANA_INIT] PLL >>>>>>>>
3894 00:44:17.466406 [ANA_INIT] PLL <<<<<<<<
3895 00:44:17.466453 [ANA_INIT] MIDPI >>>>>>>>
3896 00:44:17.466500 [ANA_INIT] MIDPI <<<<<<<<
3897 00:44:17.466546 [ANA_INIT] DLL >>>>>>>>
3898 00:44:17.466592 [ANA_INIT] flow end
3899 00:44:17.466638 ============ LP4 DIFF to SE enter ============
3900 00:44:17.466686 ============ LP4 DIFF to SE exit ============
3901 00:44:17.466748 [ANA_INIT] <<<<<<<<<<<<<
3902 00:44:17.466800 [Flow] Enable top DCM control >>>>>
3903 00:44:17.466849 [Flow] Enable top DCM control <<<<<
3904 00:44:17.466896 Enable DLL master slave shuffle
3905 00:44:17.466953 ==============================================================
3906 00:44:17.467003 Gating Mode config
3907 00:44:17.467050 ==============================================================
3908 00:44:17.467097 Config description:
3909 00:44:17.467144 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3910 00:44:17.467192 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3911 00:44:17.467240 SELPH_MODE 0: By rank 1: By Phase
3912 00:44:17.467287 ==============================================================
3913 00:44:17.467334 GAT_TRACK_EN = 1
3914 00:44:17.467381 RX_GATING_MODE = 2
3915 00:44:17.467427 RX_GATING_TRACK_MODE = 2
3916 00:44:17.467473 SELPH_MODE = 1
3917 00:44:17.467519 PICG_EARLY_EN = 1
3918 00:44:17.467566 VALID_LAT_VALUE = 1
3919 00:44:17.467612 ==============================================================
3920 00:44:17.467659 Enter into Gating configuration >>>>
3921 00:44:17.468526 Exit from Gating configuration <<<<
3922 00:44:17.471586 Enter into DVFS_PRE_config >>>>>
3923 00:44:17.481887 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3924 00:44:17.485251 Exit from DVFS_PRE_config <<<<<
3925 00:44:17.488549 Enter into PICG configuration >>>>
3926 00:44:17.491747 Exit from PICG configuration <<<<
3927 00:44:17.495330 [RX_INPUT] configuration >>>>>
3928 00:44:17.495470 [RX_INPUT] configuration <<<<<
3929 00:44:17.501499 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3930 00:44:17.508287 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3931 00:44:17.511489 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3932 00:44:17.518481 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3933 00:44:17.525118 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3934 00:44:17.531803 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3935 00:44:17.534878 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3936 00:44:17.538206 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3937 00:44:17.545033 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3938 00:44:17.548563 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3939 00:44:17.551980 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3940 00:44:17.558520 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3941 00:44:17.561716 ===================================
3942 00:44:17.562073 LPDDR4 DRAM CONFIGURATION
3943 00:44:17.564873 ===================================
3944 00:44:17.568390 EX_ROW_EN[0] = 0x0
3945 00:44:17.568917 EX_ROW_EN[1] = 0x0
3946 00:44:17.571799 LP4Y_EN = 0x0
3947 00:44:17.572299 WORK_FSP = 0x0
3948 00:44:17.575288 WL = 0x2
3949 00:44:17.578373 RL = 0x2
3950 00:44:17.578795 BL = 0x2
3951 00:44:17.581634 RPST = 0x0
3952 00:44:17.582146 RD_PRE = 0x0
3953 00:44:17.584595 WR_PRE = 0x1
3954 00:44:17.585048 WR_PST = 0x0
3955 00:44:17.588325 DBI_WR = 0x0
3956 00:44:17.588863 DBI_RD = 0x0
3957 00:44:17.591516 OTF = 0x1
3958 00:44:17.594658 ===================================
3959 00:44:17.597829 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3960 00:44:17.601433 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3961 00:44:17.604483 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3962 00:44:17.608296 ===================================
3963 00:44:17.611472 LPDDR4 DRAM CONFIGURATION
3964 00:44:17.614872 ===================================
3965 00:44:17.617810 EX_ROW_EN[0] = 0x10
3966 00:44:17.618191 EX_ROW_EN[1] = 0x0
3967 00:44:17.621011 LP4Y_EN = 0x0
3968 00:44:17.621390 WORK_FSP = 0x0
3969 00:44:17.624307 WL = 0x2
3970 00:44:17.624718 RL = 0x2
3971 00:44:17.627780 BL = 0x2
3972 00:44:17.628167 RPST = 0x0
3973 00:44:17.631056 RD_PRE = 0x0
3974 00:44:17.634658 WR_PRE = 0x1
3975 00:44:17.635122 WR_PST = 0x0
3976 00:44:17.637992 DBI_WR = 0x0
3977 00:44:17.638460 DBI_RD = 0x0
3978 00:44:17.641375 OTF = 0x1
3979 00:44:17.644506 ===================================
3980 00:44:17.648769 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3981 00:44:17.653576 nWR fixed to 30
3982 00:44:17.656442 [ModeRegInit_LP4] CH0 RK0
3983 00:44:17.656868 [ModeRegInit_LP4] CH0 RK1
3984 00:44:17.660069 [ModeRegInit_LP4] CH1 RK0
3985 00:44:17.663206 [ModeRegInit_LP4] CH1 RK1
3986 00:44:17.663593 match AC timing 17
3987 00:44:17.669821 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3988 00:44:17.672894 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3989 00:44:17.676396 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3990 00:44:17.683277 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3991 00:44:17.686825 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3992 00:44:17.687291 ==
3993 00:44:17.689716 Dram Type= 6, Freq= 0, CH_0, rank 0
3994 00:44:17.692966 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3995 00:44:17.693353 ==
3996 00:44:17.700118 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3997 00:44:17.706208 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3998 00:44:17.709323 [CA 0] Center 37 (7~67) winsize 61
3999 00:44:17.713163 [CA 1] Center 36 (6~67) winsize 62
4000 00:44:17.716207 [CA 2] Center 35 (5~65) winsize 61
4001 00:44:17.719990 [CA 3] Center 35 (5~65) winsize 61
4002 00:44:17.723338 [CA 4] Center 34 (4~65) winsize 62
4003 00:44:17.725891 [CA 5] Center 34 (4~65) winsize 62
4004 00:44:17.726318
4005 00:44:17.729570 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4006 00:44:17.730073
4007 00:44:17.733279 [CATrainingPosCal] consider 1 rank data
4008 00:44:17.736679 u2DelayCellTimex100 = 270/100 ps
4009 00:44:17.739856 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
4010 00:44:17.742530 CA1 delay=36 (6~67),Diff = 2 PI (19 cell)
4011 00:44:17.746468 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
4012 00:44:17.749609 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
4013 00:44:17.753229 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4014 00:44:17.759444 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4015 00:44:17.759948
4016 00:44:17.762401 CA PerBit enable=1, Macro0, CA PI delay=34
4017 00:44:17.762824
4018 00:44:17.765707 [CBTSetCACLKResult] CA Dly = 34
4019 00:44:17.766133 CS Dly: 5 (0~36)
4020 00:44:17.766465 ==
4021 00:44:17.769440 Dram Type= 6, Freq= 0, CH_0, rank 1
4022 00:44:17.772440 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4023 00:44:17.775903 ==
4024 00:44:17.779358 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4025 00:44:17.786127 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4026 00:44:17.789022 [CA 0] Center 37 (7~67) winsize 61
4027 00:44:17.792485 [CA 1] Center 36 (6~67) winsize 62
4028 00:44:17.795945 [CA 2] Center 35 (5~65) winsize 61
4029 00:44:17.799195 [CA 3] Center 35 (5~65) winsize 61
4030 00:44:17.802154 [CA 4] Center 34 (4~65) winsize 62
4031 00:44:17.805691 [CA 5] Center 33 (3~64) winsize 62
4032 00:44:17.806130
4033 00:44:17.809058 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4034 00:44:17.809501
4035 00:44:17.812258 [CATrainingPosCal] consider 2 rank data
4036 00:44:17.816096 u2DelayCellTimex100 = 270/100 ps
4037 00:44:17.819625 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
4038 00:44:17.822156 CA1 delay=36 (6~67),Diff = 2 PI (19 cell)
4039 00:44:17.825936 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
4040 00:44:17.832585 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
4041 00:44:17.836032 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4042 00:44:17.839518 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4043 00:44:17.840040
4044 00:44:17.842802 CA PerBit enable=1, Macro0, CA PI delay=34
4045 00:44:17.843244
4046 00:44:17.845704 [CBTSetCACLKResult] CA Dly = 34
4047 00:44:17.846226 CS Dly: 6 (0~38)
4048 00:44:17.846668
4049 00:44:17.849366 ----->DramcWriteLeveling(PI) begin...
4050 00:44:17.849894 ==
4051 00:44:17.852362 Dram Type= 6, Freq= 0, CH_0, rank 0
4052 00:44:17.858642 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4053 00:44:17.859150 ==
4054 00:44:17.862116 Write leveling (Byte 0): 35 => 35
4055 00:44:17.865553 Write leveling (Byte 1): 32 => 32
4056 00:44:17.865997 DramcWriteLeveling(PI) end<-----
4057 00:44:17.869087
4058 00:44:17.869648 ==
4059 00:44:17.872221 Dram Type= 6, Freq= 0, CH_0, rank 0
4060 00:44:17.875545 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4061 00:44:17.876081 ==
4062 00:44:17.878946 [Gating] SW mode calibration
4063 00:44:17.885347 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4064 00:44:17.888379 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4065 00:44:17.895500 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4066 00:44:17.898488 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4067 00:44:17.901753 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4068 00:44:17.908884 0 9 12 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)
4069 00:44:17.911833 0 9 16 | B1->B0 | 3333 2a2a | 0 1 | (0 0) (1 0)
4070 00:44:17.915182 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4071 00:44:17.922178 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4072 00:44:17.925539 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4073 00:44:17.929036 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4074 00:44:17.935199 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4075 00:44:17.938727 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4076 00:44:17.941994 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4077 00:44:17.949019 0 10 16 | B1->B0 | 3131 4141 | 1 0 | (0 0) (1 1)
4078 00:44:17.951845 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4079 00:44:17.954829 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4080 00:44:17.961780 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4081 00:44:17.965026 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4082 00:44:17.968883 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4083 00:44:17.975174 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4084 00:44:17.978423 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4085 00:44:17.981992 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4086 00:44:17.985481 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4087 00:44:17.991848 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4088 00:44:17.995279 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4089 00:44:17.998560 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4090 00:44:18.004857 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4091 00:44:18.008511 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4092 00:44:18.011691 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4093 00:44:18.018207 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4094 00:44:18.022027 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4095 00:44:18.025214 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4096 00:44:18.031519 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4097 00:44:18.035308 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4098 00:44:18.038354 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4099 00:44:18.044462 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4100 00:44:18.047898 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4101 00:44:18.051768 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4102 00:44:18.054430 Total UI for P1: 0, mck2ui 16
4103 00:44:18.057732 best dqsien dly found for B0: ( 0, 13, 12)
4104 00:44:18.064765 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4105 00:44:18.065214 Total UI for P1: 0, mck2ui 16
4106 00:44:18.071444 best dqsien dly found for B1: ( 0, 13, 18)
4107 00:44:18.074313 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4108 00:44:18.077777 best DQS1 dly(MCK, UI, PI) = (0, 13, 18)
4109 00:44:18.078218
4110 00:44:18.081477 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4111 00:44:18.084871 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 18)
4112 00:44:18.088162 [Gating] SW calibration Done
4113 00:44:18.088723 ==
4114 00:44:18.091665 Dram Type= 6, Freq= 0, CH_0, rank 0
4115 00:44:18.094228 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4116 00:44:18.094761 ==
4117 00:44:18.097586 RX Vref Scan: 0
4118 00:44:18.098012
4119 00:44:18.098343 RX Vref 0 -> 0, step: 1
4120 00:44:18.101330
4121 00:44:18.101801 RX Delay -230 -> 252, step: 16
4122 00:44:18.107974 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4123 00:44:18.110844 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4124 00:44:18.114354 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4125 00:44:18.117573 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4126 00:44:18.124587 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4127 00:44:18.128051 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4128 00:44:18.130996 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4129 00:44:18.134639 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4130 00:44:18.137534 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4131 00:44:18.144370 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4132 00:44:18.147650 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4133 00:44:18.150761 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4134 00:44:18.154151 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4135 00:44:18.161189 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4136 00:44:18.164154 iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352
4137 00:44:18.167744 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4138 00:44:18.168256 ==
4139 00:44:18.171489 Dram Type= 6, Freq= 0, CH_0, rank 0
4140 00:44:18.174218 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4141 00:44:18.174657 ==
4142 00:44:18.178037 DQS Delay:
4143 00:44:18.178552 DQS0 = 0, DQS1 = 0
4144 00:44:18.182203 DQM Delay:
4145 00:44:18.182745 DQM0 = 37, DQM1 = 29
4146 00:44:18.183190 DQ Delay:
4147 00:44:18.184229 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
4148 00:44:18.187744 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4149 00:44:18.190868 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4150 00:44:18.194006 DQ12 =33, DQ13 =33, DQ14 =41, DQ15 =33
4151 00:44:18.194649
4152 00:44:18.195153
4153 00:44:18.197319 ==
4154 00:44:18.201098 Dram Type= 6, Freq= 0, CH_0, rank 0
4155 00:44:18.204484 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4156 00:44:18.205072 ==
4157 00:44:18.205514
4158 00:44:18.205918
4159 00:44:18.207132 TX Vref Scan disable
4160 00:44:18.207573 == TX Byte 0 ==
4161 00:44:18.213966 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4162 00:44:18.217412 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4163 00:44:18.217939 == TX Byte 1 ==
4164 00:44:18.223675 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4165 00:44:18.226964 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4166 00:44:18.227485 ==
4167 00:44:18.230067 Dram Type= 6, Freq= 0, CH_0, rank 0
4168 00:44:18.233678 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4169 00:44:18.234203 ==
4170 00:44:18.234646
4171 00:44:18.235057
4172 00:44:18.237244 TX Vref Scan disable
4173 00:44:18.240759 == TX Byte 0 ==
4174 00:44:18.244154 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4175 00:44:18.247524 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4176 00:44:18.250326 == TX Byte 1 ==
4177 00:44:18.253686 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4178 00:44:18.257014 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4179 00:44:18.260773
4180 00:44:18.261289 [DATLAT]
4181 00:44:18.261730 Freq=600, CH0 RK0
4182 00:44:18.262146
4183 00:44:18.263775 DATLAT Default: 0x9
4184 00:44:18.264201 0, 0xFFFF, sum = 0
4185 00:44:18.266814 1, 0xFFFF, sum = 0
4186 00:44:18.267329 2, 0xFFFF, sum = 0
4187 00:44:18.269935 3, 0xFFFF, sum = 0
4188 00:44:18.270370 4, 0xFFFF, sum = 0
4189 00:44:18.273361 5, 0xFFFF, sum = 0
4190 00:44:18.276851 6, 0xFFFF, sum = 0
4191 00:44:18.277370 7, 0xFFFF, sum = 0
4192 00:44:18.277711 8, 0x0, sum = 1
4193 00:44:18.279991 9, 0x0, sum = 2
4194 00:44:18.280383 10, 0x0, sum = 3
4195 00:44:18.283264 11, 0x0, sum = 4
4196 00:44:18.283654 best_step = 9
4197 00:44:18.283958
4198 00:44:18.284233 ==
4199 00:44:18.286541 Dram Type= 6, Freq= 0, CH_0, rank 0
4200 00:44:18.293131 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4201 00:44:18.293605 ==
4202 00:44:18.293960 RX Vref Scan: 1
4203 00:44:18.294270
4204 00:44:18.296566 RX Vref 0 -> 0, step: 1
4205 00:44:18.297006
4206 00:44:18.299992 RX Delay -195 -> 252, step: 8
4207 00:44:18.300431
4208 00:44:18.303179 Set Vref, RX VrefLevel [Byte0]: 61
4209 00:44:18.306500 [Byte1]: 48
4210 00:44:18.306990
4211 00:44:18.309976 Final RX Vref Byte 0 = 61 to rank0
4212 00:44:18.313137 Final RX Vref Byte 1 = 48 to rank0
4213 00:44:18.316844 Final RX Vref Byte 0 = 61 to rank1
4214 00:44:18.320351 Final RX Vref Byte 1 = 48 to rank1==
4215 00:44:18.323800 Dram Type= 6, Freq= 0, CH_0, rank 0
4216 00:44:18.326578 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4217 00:44:18.327106 ==
4218 00:44:18.329600 DQS Delay:
4219 00:44:18.330040 DQS0 = 0, DQS1 = 0
4220 00:44:18.333313 DQM Delay:
4221 00:44:18.333836 DQM0 = 35, DQM1 = 29
4222 00:44:18.334279 DQ Delay:
4223 00:44:18.336542 DQ0 =36, DQ1 =36, DQ2 =36, DQ3 =28
4224 00:44:18.340111 DQ4 =32, DQ5 =24, DQ6 =40, DQ7 =48
4225 00:44:18.343333 DQ8 =20, DQ9 =16, DQ10 =28, DQ11 =20
4226 00:44:18.346849 DQ12 =36, DQ13 =36, DQ14 =40, DQ15 =36
4227 00:44:18.347369
4228 00:44:18.347811
4229 00:44:18.356358 [DQSOSCAuto] RK0, (LSB)MR18= 0x4341, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 397 ps
4230 00:44:18.360053 CH0 RK0: MR19=808, MR18=4341
4231 00:44:18.363147 CH0_RK0: MR19=0x808, MR18=0x4341, DQSOSC=397, MR23=63, INC=166, DEC=110
4232 00:44:18.366260
4233 00:44:18.369473 ----->DramcWriteLeveling(PI) begin...
4234 00:44:18.369918 ==
4235 00:44:18.372919 Dram Type= 6, Freq= 0, CH_0, rank 1
4236 00:44:18.376544 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4237 00:44:18.377118 ==
4238 00:44:18.379706 Write leveling (Byte 0): 31 => 31
4239 00:44:18.382880 Write leveling (Byte 1): 31 => 31
4240 00:44:18.386072 DramcWriteLeveling(PI) end<-----
4241 00:44:18.386594
4242 00:44:18.387034 ==
4243 00:44:18.389295 Dram Type= 6, Freq= 0, CH_0, rank 1
4244 00:44:18.392423 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4245 00:44:18.392845 ==
4246 00:44:18.395831 [Gating] SW mode calibration
4247 00:44:18.402265 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4248 00:44:18.409223 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4249 00:44:18.412444 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4250 00:44:18.415801 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4251 00:44:18.423128 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4252 00:44:18.426260 0 9 12 | B1->B0 | 3434 2f2f | 0 1 | (0 0) (1 1)
4253 00:44:18.429289 0 9 16 | B1->B0 | 3030 2323 | 0 0 | (0 1) (0 0)
4254 00:44:18.435989 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4255 00:44:18.439495 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4256 00:44:18.442948 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4257 00:44:18.446116 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4258 00:44:18.452516 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4259 00:44:18.455879 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4260 00:44:18.459421 0 10 12 | B1->B0 | 2b2b 3131 | 0 0 | (0 0) (0 0)
4261 00:44:18.465772 0 10 16 | B1->B0 | 3838 4646 | 1 0 | (0 0) (0 0)
4262 00:44:18.469165 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4263 00:44:18.472593 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4264 00:44:18.478984 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4265 00:44:18.482418 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4266 00:44:18.485903 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4267 00:44:18.492692 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4268 00:44:18.496190 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4269 00:44:18.499397 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4270 00:44:18.505830 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4271 00:44:18.509215 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4272 00:44:18.512367 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4273 00:44:18.518997 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4274 00:44:18.522536 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4275 00:44:18.525944 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4276 00:44:18.531832 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4277 00:44:18.535715 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4278 00:44:18.538773 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4279 00:44:18.545617 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4280 00:44:18.548694 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4281 00:44:18.552299 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4282 00:44:18.558525 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4283 00:44:18.562142 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4284 00:44:18.565150 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4285 00:44:18.572068 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4286 00:44:18.575063 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4287 00:44:18.578236 Total UI for P1: 0, mck2ui 16
4288 00:44:18.581831 best dqsien dly found for B0: ( 0, 13, 14)
4289 00:44:18.585201 Total UI for P1: 0, mck2ui 16
4290 00:44:18.589027 best dqsien dly found for B1: ( 0, 13, 18)
4291 00:44:18.592399 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4292 00:44:18.595703 best DQS1 dly(MCK, UI, PI) = (0, 13, 18)
4293 00:44:18.596171
4294 00:44:18.598829 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4295 00:44:18.602106 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 18)
4296 00:44:18.605260 [Gating] SW calibration Done
4297 00:44:18.605651 ==
4298 00:44:18.608901 Dram Type= 6, Freq= 0, CH_0, rank 1
4299 00:44:18.612085 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4300 00:44:18.612562 ==
4301 00:44:18.615654 RX Vref Scan: 0
4302 00:44:18.616118
4303 00:44:18.618864 RX Vref 0 -> 0, step: 1
4304 00:44:18.619332
4305 00:44:18.621580 RX Delay -230 -> 252, step: 16
4306 00:44:18.624825 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4307 00:44:18.628419 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4308 00:44:18.631805 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4309 00:44:18.635002 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4310 00:44:18.641861 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4311 00:44:18.645347 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4312 00:44:18.648570 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4313 00:44:18.652118 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4314 00:44:18.658328 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4315 00:44:18.662309 iDelay=218, Bit 9, Center 9 (-150 ~ 169) 320
4316 00:44:18.664778 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4317 00:44:18.668467 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4318 00:44:18.674976 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4319 00:44:18.678096 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4320 00:44:18.681470 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4321 00:44:18.684989 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4322 00:44:18.685584 ==
4323 00:44:18.688337 Dram Type= 6, Freq= 0, CH_0, rank 1
4324 00:44:18.695177 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4325 00:44:18.695685 ==
4326 00:44:18.696021 DQS Delay:
4327 00:44:18.697942 DQS0 = 0, DQS1 = 0
4328 00:44:18.698454 DQM Delay:
4329 00:44:18.698803 DQM0 = 36, DQM1 = 29
4330 00:44:18.701393 DQ Delay:
4331 00:44:18.704734 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
4332 00:44:18.708206 DQ4 =33, DQ5 =25, DQ6 =49, DQ7 =49
4333 00:44:18.711629 DQ8 =25, DQ9 =9, DQ10 =33, DQ11 =25
4334 00:44:18.714919 DQ12 =33, DQ13 =33, DQ14 =41, DQ15 =33
4335 00:44:18.715388
4336 00:44:18.715714
4337 00:44:18.716022 ==
4338 00:44:18.718238 Dram Type= 6, Freq= 0, CH_0, rank 1
4339 00:44:18.720931 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4340 00:44:18.721375 ==
4341 00:44:18.721726
4342 00:44:18.722007
4343 00:44:18.724494 TX Vref Scan disable
4344 00:44:18.724999 == TX Byte 0 ==
4345 00:44:18.731037 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4346 00:44:18.734444 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4347 00:44:18.734951 == TX Byte 1 ==
4348 00:44:18.741000 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4349 00:44:18.744365 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4350 00:44:18.744915 ==
4351 00:44:18.747877 Dram Type= 6, Freq= 0, CH_0, rank 1
4352 00:44:18.751304 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4353 00:44:18.751815 ==
4354 00:44:18.754542
4355 00:44:18.755045
4356 00:44:18.755377 TX Vref Scan disable
4357 00:44:18.757725 == TX Byte 0 ==
4358 00:44:18.761484 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4359 00:44:18.767704 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4360 00:44:18.768187 == TX Byte 1 ==
4361 00:44:18.770722 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4362 00:44:18.777587 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4363 00:44:18.777981
4364 00:44:18.778300 [DATLAT]
4365 00:44:18.778584 Freq=600, CH0 RK1
4366 00:44:18.778855
4367 00:44:18.780995 DATLAT Default: 0x9
4368 00:44:18.781385 0, 0xFFFF, sum = 0
4369 00:44:18.784333 1, 0xFFFF, sum = 0
4370 00:44:18.787200 2, 0xFFFF, sum = 0
4371 00:44:18.787597 3, 0xFFFF, sum = 0
4372 00:44:18.790464 4, 0xFFFF, sum = 0
4373 00:44:18.790860 5, 0xFFFF, sum = 0
4374 00:44:18.793910 6, 0xFFFF, sum = 0
4375 00:44:18.794308 7, 0xFFFF, sum = 0
4376 00:44:18.797517 8, 0x0, sum = 1
4377 00:44:18.798142 9, 0x0, sum = 2
4378 00:44:18.798706 10, 0x0, sum = 3
4379 00:44:18.800762 11, 0x0, sum = 4
4380 00:44:18.801156 best_step = 9
4381 00:44:18.801458
4382 00:44:18.801734 ==
4383 00:44:18.804005 Dram Type= 6, Freq= 0, CH_0, rank 1
4384 00:44:18.810972 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4385 00:44:18.811361 ==
4386 00:44:18.811660 RX Vref Scan: 0
4387 00:44:18.811939
4388 00:44:18.814024 RX Vref 0 -> 0, step: 1
4389 00:44:18.814462
4390 00:44:18.817502 RX Delay -195 -> 252, step: 8
4391 00:44:18.820530 iDelay=205, Bit 0, Center 32 (-123 ~ 188) 312
4392 00:44:18.827493 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4393 00:44:18.830899 iDelay=205, Bit 2, Center 32 (-123 ~ 188) 312
4394 00:44:18.834029 iDelay=205, Bit 3, Center 28 (-131 ~ 188) 320
4395 00:44:18.836994 iDelay=205, Bit 4, Center 32 (-123 ~ 188) 312
4396 00:44:18.844088 iDelay=205, Bit 5, Center 20 (-139 ~ 180) 320
4397 00:44:18.847372 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4398 00:44:18.851075 iDelay=205, Bit 7, Center 44 (-115 ~ 204) 320
4399 00:44:18.853631 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4400 00:44:18.857151 iDelay=205, Bit 9, Center 12 (-139 ~ 164) 304
4401 00:44:18.864036 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4402 00:44:18.867609 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4403 00:44:18.870717 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4404 00:44:18.873526 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4405 00:44:18.880543 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4406 00:44:18.884105 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4407 00:44:18.884610 ==
4408 00:44:18.887556 Dram Type= 6, Freq= 0, CH_0, rank 1
4409 00:44:18.890994 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4410 00:44:18.891503 ==
4411 00:44:18.893818 DQS Delay:
4412 00:44:18.894321 DQS0 = 0, DQS1 = 0
4413 00:44:18.894657 DQM Delay:
4414 00:44:18.897171 DQM0 = 33, DQM1 = 28
4415 00:44:18.897676 DQ Delay:
4416 00:44:18.900466 DQ0 =32, DQ1 =36, DQ2 =32, DQ3 =28
4417 00:44:18.904061 DQ4 =32, DQ5 =20, DQ6 =44, DQ7 =44
4418 00:44:18.907123 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =20
4419 00:44:18.910660 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4420 00:44:18.911122
4421 00:44:18.911421
4422 00:44:18.920291 [DQSOSCAuto] RK1, (LSB)MR18= 0x6d3b, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 389 ps
4423 00:44:18.923695 CH0 RK1: MR19=808, MR18=6D3B
4424 00:44:18.926913 CH0_RK1: MR19=0x808, MR18=0x6D3B, DQSOSC=389, MR23=63, INC=173, DEC=115
4425 00:44:18.930647 [RxdqsGatingPostProcess] freq 600
4426 00:44:18.936810 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4427 00:44:18.940436 Pre-setting of DQS Precalculation
4428 00:44:18.944045 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4429 00:44:18.944547 ==
4430 00:44:18.946810 Dram Type= 6, Freq= 0, CH_1, rank 0
4431 00:44:18.953492 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4432 00:44:18.954042 ==
4433 00:44:18.956744 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4434 00:44:18.963523 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4435 00:44:18.966569 [CA 0] Center 35 (5~66) winsize 62
4436 00:44:18.970096 [CA 1] Center 36 (6~66) winsize 61
4437 00:44:18.973332 [CA 2] Center 34 (4~65) winsize 62
4438 00:44:18.976950 [CA 3] Center 34 (3~65) winsize 63
4439 00:44:18.980169 [CA 4] Center 34 (4~65) winsize 62
4440 00:44:18.983444 [CA 5] Center 33 (3~64) winsize 62
4441 00:44:18.983874
4442 00:44:18.986684 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4443 00:44:18.987073
4444 00:44:18.990356 [CATrainingPosCal] consider 1 rank data
4445 00:44:18.993866 u2DelayCellTimex100 = 270/100 ps
4446 00:44:18.997197 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4447 00:44:18.999755 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4448 00:44:19.006608 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4449 00:44:19.010279 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4450 00:44:19.013379 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4451 00:44:19.017044 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4452 00:44:19.017508
4453 00:44:19.020117 CA PerBit enable=1, Macro0, CA PI delay=33
4454 00:44:19.020502
4455 00:44:19.023300 [CBTSetCACLKResult] CA Dly = 33
4456 00:44:19.023784 CS Dly: 4 (0~35)
4457 00:44:19.026409 ==
4458 00:44:19.026918 Dram Type= 6, Freq= 0, CH_1, rank 1
4459 00:44:19.033251 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4460 00:44:19.033639 ==
4461 00:44:19.036750 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4462 00:44:19.043338 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4463 00:44:19.046863 [CA 0] Center 36 (6~66) winsize 61
4464 00:44:19.050490 [CA 1] Center 35 (5~66) winsize 62
4465 00:44:19.053633 [CA 2] Center 34 (4~65) winsize 62
4466 00:44:19.057119 [CA 3] Center 34 (3~65) winsize 63
4467 00:44:19.060308 [CA 4] Center 34 (4~65) winsize 62
4468 00:44:19.063434 [CA 5] Center 33 (3~64) winsize 62
4469 00:44:19.063827
4470 00:44:19.066880 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4471 00:44:19.067272
4472 00:44:19.070606 [CATrainingPosCal] consider 2 rank data
4473 00:44:19.073635 u2DelayCellTimex100 = 270/100 ps
4474 00:44:19.076801 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4475 00:44:19.080440 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4476 00:44:19.086882 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4477 00:44:19.090322 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4478 00:44:19.093409 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4479 00:44:19.096873 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4480 00:44:19.097339
4481 00:44:19.100094 CA PerBit enable=1, Macro0, CA PI delay=33
4482 00:44:19.100575
4483 00:44:19.103130 [CBTSetCACLKResult] CA Dly = 33
4484 00:44:19.103534 CS Dly: 4 (0~36)
4485 00:44:19.103834
4486 00:44:19.106642 ----->DramcWriteLeveling(PI) begin...
4487 00:44:19.109908 ==
4488 00:44:19.113246 Dram Type= 6, Freq= 0, CH_1, rank 0
4489 00:44:19.116492 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4490 00:44:19.116913 ==
4491 00:44:19.119666 Write leveling (Byte 0): 31 => 31
4492 00:44:19.123253 Write leveling (Byte 1): 31 => 31
4493 00:44:19.126936 DramcWriteLeveling(PI) end<-----
4494 00:44:19.127417
4495 00:44:19.127815 ==
4496 00:44:19.129664 Dram Type= 6, Freq= 0, CH_1, rank 0
4497 00:44:19.133027 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4498 00:44:19.133427 ==
4499 00:44:19.136391 [Gating] SW mode calibration
4500 00:44:19.143553 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4501 00:44:19.150041 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4502 00:44:19.152993 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4503 00:44:19.156914 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4504 00:44:19.162890 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4505 00:44:19.166220 0 9 12 | B1->B0 | 3131 3232 | 0 0 | (0 0) (0 1)
4506 00:44:19.169754 0 9 16 | B1->B0 | 2727 2626 | 0 0 | (0 0) (0 0)
4507 00:44:19.173316 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4508 00:44:19.179399 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4509 00:44:19.183009 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4510 00:44:19.186480 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4511 00:44:19.192983 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4512 00:44:19.196337 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4513 00:44:19.199598 0 10 12 | B1->B0 | 3131 2f2f | 0 0 | (0 0) (0 0)
4514 00:44:19.206155 0 10 16 | B1->B0 | 3f3f 4141 | 0 0 | (0 0) (0 0)
4515 00:44:19.209536 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4516 00:44:19.212886 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4517 00:44:19.219461 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4518 00:44:19.223051 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4519 00:44:19.226381 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4520 00:44:19.232433 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4521 00:44:19.236261 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4522 00:44:19.239247 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4523 00:44:19.245807 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4524 00:44:19.249170 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4525 00:44:19.252475 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4526 00:44:19.259398 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4527 00:44:19.262557 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4528 00:44:19.266122 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4529 00:44:19.272716 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4530 00:44:19.276130 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4531 00:44:19.279589 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4532 00:44:19.285810 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4533 00:44:19.289112 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4534 00:44:19.292570 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4535 00:44:19.299422 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4536 00:44:19.302125 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4537 00:44:19.305597 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4538 00:44:19.312805 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4539 00:44:19.313314 Total UI for P1: 0, mck2ui 16
4540 00:44:19.315819 best dqsien dly found for B0: ( 0, 13, 12)
4541 00:44:19.322649 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4542 00:44:19.325235 Total UI for P1: 0, mck2ui 16
4543 00:44:19.328954 best dqsien dly found for B1: ( 0, 13, 14)
4544 00:44:19.332287 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4545 00:44:19.335458 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4546 00:44:19.335959
4547 00:44:19.338958 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4548 00:44:19.342171 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4549 00:44:19.345541 [Gating] SW calibration Done
4550 00:44:19.346046 ==
4551 00:44:19.348570 Dram Type= 6, Freq= 0, CH_1, rank 0
4552 00:44:19.351846 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4553 00:44:19.355521 ==
4554 00:44:19.356031 RX Vref Scan: 0
4555 00:44:19.356430
4556 00:44:19.358665 RX Vref 0 -> 0, step: 1
4557 00:44:19.359090
4558 00:44:19.361927 RX Delay -230 -> 252, step: 16
4559 00:44:19.364905 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4560 00:44:19.368744 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4561 00:44:19.371779 iDelay=218, Bit 2, Center 25 (-150 ~ 201) 352
4562 00:44:19.375044 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4563 00:44:19.381654 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4564 00:44:19.384752 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4565 00:44:19.388074 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4566 00:44:19.391496 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4567 00:44:19.398208 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4568 00:44:19.401882 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4569 00:44:19.404706 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4570 00:44:19.408038 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4571 00:44:19.414789 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4572 00:44:19.418299 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4573 00:44:19.421058 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4574 00:44:19.424413 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4575 00:44:19.424865 ==
4576 00:44:19.427852 Dram Type= 6, Freq= 0, CH_1, rank 0
4577 00:44:19.434908 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4578 00:44:19.435299 ==
4579 00:44:19.435606 DQS Delay:
4580 00:44:19.437823 DQS0 = 0, DQS1 = 0
4581 00:44:19.438101 DQM Delay:
4582 00:44:19.438320 DQM0 = 38, DQM1 = 28
4583 00:44:19.441142 DQ Delay:
4584 00:44:19.444519 DQ0 =49, DQ1 =33, DQ2 =25, DQ3 =33
4585 00:44:19.447665 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4586 00:44:19.450756 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4587 00:44:19.454552 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4588 00:44:19.454718
4589 00:44:19.454848
4590 00:44:19.454967 ==
4591 00:44:19.457614 Dram Type= 6, Freq= 0, CH_1, rank 0
4592 00:44:19.460655 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4593 00:44:19.460836 ==
4594 00:44:19.460968
4595 00:44:19.461090
4596 00:44:19.464044 TX Vref Scan disable
4597 00:44:19.467989 == TX Byte 0 ==
4598 00:44:19.470800 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4599 00:44:19.474264 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4600 00:44:19.477645 == TX Byte 1 ==
4601 00:44:19.480527 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4602 00:44:19.484144 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4603 00:44:19.484534 ==
4604 00:44:19.487475 Dram Type= 6, Freq= 0, CH_1, rank 0
4605 00:44:19.491258 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4606 00:44:19.491655 ==
4607 00:44:19.494211
4608 00:44:19.494598
4609 00:44:19.494944 TX Vref Scan disable
4610 00:44:19.497821 == TX Byte 0 ==
4611 00:44:19.501057 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4612 00:44:19.507746 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4613 00:44:19.507960 == TX Byte 1 ==
4614 00:44:19.511171 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4615 00:44:19.514814 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4616 00:44:19.517711
4617 00:44:19.517853 [DATLAT]
4618 00:44:19.517964 Freq=600, CH1 RK0
4619 00:44:19.518067
4620 00:44:19.520859 DATLAT Default: 0x9
4621 00:44:19.521090 0, 0xFFFF, sum = 0
4622 00:44:19.524201 1, 0xFFFF, sum = 0
4623 00:44:19.524350 2, 0xFFFF, sum = 0
4624 00:44:19.527634 3, 0xFFFF, sum = 0
4625 00:44:19.531008 4, 0xFFFF, sum = 0
4626 00:44:19.531117 5, 0xFFFF, sum = 0
4627 00:44:19.534341 6, 0xFFFF, sum = 0
4628 00:44:19.534436 7, 0xFFFF, sum = 0
4629 00:44:19.534512 8, 0x0, sum = 1
4630 00:44:19.537996 9, 0x0, sum = 2
4631 00:44:19.538154 10, 0x0, sum = 3
4632 00:44:19.540737 11, 0x0, sum = 4
4633 00:44:19.540853 best_step = 9
4634 00:44:19.540928
4635 00:44:19.540997 ==
4636 00:44:19.544038 Dram Type= 6, Freq= 0, CH_1, rank 0
4637 00:44:19.550861 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4638 00:44:19.551018 ==
4639 00:44:19.551098 RX Vref Scan: 1
4640 00:44:19.551170
4641 00:44:19.554027 RX Vref 0 -> 0, step: 1
4642 00:44:19.554182
4643 00:44:19.557910 RX Delay -195 -> 252, step: 8
4644 00:44:19.558068
4645 00:44:19.561205 Set Vref, RX VrefLevel [Byte0]: 57
4646 00:44:19.564157 [Byte1]: 53
4647 00:44:19.564324
4648 00:44:19.567435 Final RX Vref Byte 0 = 57 to rank0
4649 00:44:19.570822 Final RX Vref Byte 1 = 53 to rank0
4650 00:44:19.574315 Final RX Vref Byte 0 = 57 to rank1
4651 00:44:19.577648 Final RX Vref Byte 1 = 53 to rank1==
4652 00:44:19.580555 Dram Type= 6, Freq= 0, CH_1, rank 0
4653 00:44:19.584271 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4654 00:44:19.584682 ==
4655 00:44:19.587795 DQS Delay:
4656 00:44:19.588256 DQS0 = 0, DQS1 = 0
4657 00:44:19.590985 DQM Delay:
4658 00:44:19.591377 DQM0 = 39, DQM1 = 28
4659 00:44:19.591683 DQ Delay:
4660 00:44:19.594190 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =36
4661 00:44:19.597466 DQ4 =36, DQ5 =52, DQ6 =48, DQ7 =36
4662 00:44:19.600536 DQ8 =12, DQ9 =16, DQ10 =32, DQ11 =20
4663 00:44:19.603921 DQ12 =40, DQ13 =36, DQ14 =36, DQ15 =36
4664 00:44:19.604315
4665 00:44:19.604619
4666 00:44:19.614086 [DQSOSCAuto] RK0, (LSB)MR18= 0x2c38, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 401 ps
4667 00:44:19.617092 CH1 RK0: MR19=808, MR18=2C38
4668 00:44:19.624053 CH1_RK0: MR19=0x808, MR18=0x2C38, DQSOSC=399, MR23=63, INC=164, DEC=109
4669 00:44:19.624438
4670 00:44:19.627395 ----->DramcWriteLeveling(PI) begin...
4671 00:44:19.627789 ==
4672 00:44:19.630693 Dram Type= 6, Freq= 0, CH_1, rank 1
4673 00:44:19.633721 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4674 00:44:19.634145 ==
4675 00:44:19.637008 Write leveling (Byte 0): 29 => 29
4676 00:44:19.640394 Write leveling (Byte 1): 29 => 29
4677 00:44:19.643497 DramcWriteLeveling(PI) end<-----
4678 00:44:19.643966
4679 00:44:19.644270 ==
4680 00:44:19.646878 Dram Type= 6, Freq= 0, CH_1, rank 1
4681 00:44:19.650634 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4682 00:44:19.651022 ==
4683 00:44:19.653812 [Gating] SW mode calibration
4684 00:44:19.660149 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4685 00:44:19.667026 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4686 00:44:19.670136 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4687 00:44:19.673780 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4688 00:44:19.680349 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4689 00:44:19.683932 0 9 12 | B1->B0 | 3030 2e2e | 0 0 | (0 0) (0 0)
4690 00:44:19.687066 0 9 16 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
4691 00:44:19.693913 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4692 00:44:19.697113 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4693 00:44:19.700592 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4694 00:44:19.707174 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4695 00:44:19.710361 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4696 00:44:19.713724 0 10 8 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
4697 00:44:19.720049 0 10 12 | B1->B0 | 3434 4444 | 0 0 | (0 0) (0 0)
4698 00:44:19.723295 0 10 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4699 00:44:19.726983 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4700 00:44:19.730348 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4701 00:44:19.736583 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4702 00:44:19.740308 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4703 00:44:19.743449 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4704 00:44:19.750014 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4705 00:44:19.753525 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4706 00:44:19.756706 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4707 00:44:19.763662 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4708 00:44:19.766716 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4709 00:44:19.770146 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4710 00:44:19.776714 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4711 00:44:19.779796 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4712 00:44:19.782826 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4713 00:44:19.789650 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4714 00:44:19.792920 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4715 00:44:19.796193 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4716 00:44:19.802605 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4717 00:44:19.806087 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4718 00:44:19.809480 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4719 00:44:19.815769 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4720 00:44:19.819249 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4721 00:44:19.822738 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4722 00:44:19.826160 Total UI for P1: 0, mck2ui 16
4723 00:44:19.829342 best dqsien dly found for B0: ( 0, 13, 8)
4724 00:44:19.835742 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4725 00:44:19.839065 Total UI for P1: 0, mck2ui 16
4726 00:44:19.842454 best dqsien dly found for B1: ( 0, 13, 10)
4727 00:44:19.845636 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4728 00:44:19.849114 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4729 00:44:19.849498
4730 00:44:19.852634 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4731 00:44:19.856094 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4732 00:44:19.859329 [Gating] SW calibration Done
4733 00:44:19.859715 ==
4734 00:44:19.862620 Dram Type= 6, Freq= 0, CH_1, rank 1
4735 00:44:19.865606 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4736 00:44:19.866123 ==
4737 00:44:19.869120 RX Vref Scan: 0
4738 00:44:19.869587
4739 00:44:19.872230 RX Vref 0 -> 0, step: 1
4740 00:44:19.872886
4741 00:44:19.873226 RX Delay -230 -> 252, step: 16
4742 00:44:19.878648 iDelay=218, Bit 0, Center 41 (-134 ~ 217) 352
4743 00:44:19.881992 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4744 00:44:19.885395 iDelay=218, Bit 2, Center 17 (-150 ~ 185) 336
4745 00:44:19.889317 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4746 00:44:19.895298 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4747 00:44:19.898521 iDelay=218, Bit 5, Center 41 (-134 ~ 217) 352
4748 00:44:19.901949 iDelay=218, Bit 6, Center 41 (-134 ~ 217) 352
4749 00:44:19.905382 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4750 00:44:19.908537 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4751 00:44:19.915017 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4752 00:44:19.918436 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4753 00:44:19.921813 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4754 00:44:19.925349 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4755 00:44:19.931601 iDelay=218, Bit 13, Center 41 (-134 ~ 217) 352
4756 00:44:19.935020 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4757 00:44:19.938419 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4758 00:44:19.938812 ==
4759 00:44:19.941857 Dram Type= 6, Freq= 0, CH_1, rank 1
4760 00:44:19.948131 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4761 00:44:19.948541 ==
4762 00:44:19.948937 DQS Delay:
4763 00:44:19.949224 DQS0 = 0, DQS1 = 0
4764 00:44:19.951908 DQM Delay:
4765 00:44:19.952341 DQM0 = 34, DQM1 = 29
4766 00:44:19.955168 DQ Delay:
4767 00:44:19.958401 DQ0 =41, DQ1 =33, DQ2 =17, DQ3 =33
4768 00:44:19.958837 DQ4 =33, DQ5 =41, DQ6 =41, DQ7 =33
4769 00:44:19.961906 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4770 00:44:19.968325 DQ12 =33, DQ13 =41, DQ14 =33, DQ15 =33
4771 00:44:19.968756
4772 00:44:19.969153
4773 00:44:19.969435 ==
4774 00:44:19.971657 Dram Type= 6, Freq= 0, CH_1, rank 1
4775 00:44:19.974815 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4776 00:44:19.975244 ==
4777 00:44:19.975542
4778 00:44:19.975812
4779 00:44:19.977985 TX Vref Scan disable
4780 00:44:19.978368 == TX Byte 0 ==
4781 00:44:19.985421 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4782 00:44:19.988241 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4783 00:44:19.988776 == TX Byte 1 ==
4784 00:44:19.994875 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4785 00:44:19.998190 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4786 00:44:19.998631 ==
4787 00:44:20.001200 Dram Type= 6, Freq= 0, CH_1, rank 1
4788 00:44:20.004482 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4789 00:44:20.005086 ==
4790 00:44:20.005485
4791 00:44:20.005952
4792 00:44:20.007731 TX Vref Scan disable
4793 00:44:20.011393 == TX Byte 0 ==
4794 00:44:20.014819 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4795 00:44:20.021038 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4796 00:44:20.021423 == TX Byte 1 ==
4797 00:44:20.024696 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4798 00:44:20.030877 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4799 00:44:20.031273
4800 00:44:20.031573 [DATLAT]
4801 00:44:20.031851 Freq=600, CH1 RK1
4802 00:44:20.032117
4803 00:44:20.034488 DATLAT Default: 0x9
4804 00:44:20.034927 0, 0xFFFF, sum = 0
4805 00:44:20.038099 1, 0xFFFF, sum = 0
4806 00:44:20.041299 2, 0xFFFF, sum = 0
4807 00:44:20.041765 3, 0xFFFF, sum = 0
4808 00:44:20.044696 4, 0xFFFF, sum = 0
4809 00:44:20.045169 5, 0xFFFF, sum = 0
4810 00:44:20.048066 6, 0xFFFF, sum = 0
4811 00:44:20.048581 7, 0xFFFF, sum = 0
4812 00:44:20.051523 8, 0x0, sum = 1
4813 00:44:20.052033 9, 0x0, sum = 2
4814 00:44:20.052373 10, 0x0, sum = 3
4815 00:44:20.054705 11, 0x0, sum = 4
4816 00:44:20.055219 best_step = 9
4817 00:44:20.055553
4818 00:44:20.055853 ==
4819 00:44:20.057912 Dram Type= 6, Freq= 0, CH_1, rank 1
4820 00:44:20.064673 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4821 00:44:20.065184 ==
4822 00:44:20.065519 RX Vref Scan: 0
4823 00:44:20.065826
4824 00:44:20.067942 RX Vref 0 -> 0, step: 1
4825 00:44:20.068410
4826 00:44:20.071065 RX Delay -195 -> 252, step: 8
4827 00:44:20.074277 iDelay=205, Bit 0, Center 36 (-123 ~ 196) 320
4828 00:44:20.080918 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4829 00:44:20.084416 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4830 00:44:20.088120 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4831 00:44:20.091306 iDelay=205, Bit 4, Center 32 (-123 ~ 188) 312
4832 00:44:20.097966 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4833 00:44:20.101165 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4834 00:44:20.104627 iDelay=205, Bit 7, Center 36 (-123 ~ 196) 320
4835 00:44:20.107688 iDelay=205, Bit 8, Center 16 (-147 ~ 180) 328
4836 00:44:20.110912 iDelay=205, Bit 9, Center 16 (-147 ~ 180) 328
4837 00:44:20.117370 iDelay=205, Bit 10, Center 32 (-131 ~ 196) 328
4838 00:44:20.121104 iDelay=205, Bit 11, Center 24 (-139 ~ 188) 328
4839 00:44:20.124074 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4840 00:44:20.128022 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4841 00:44:20.134348 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4842 00:44:20.137455 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4843 00:44:20.137881 ==
4844 00:44:20.140717 Dram Type= 6, Freq= 0, CH_1, rank 1
4845 00:44:20.144432 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4846 00:44:20.144908 ==
4847 00:44:20.146974 DQS Delay:
4848 00:44:20.147404 DQS0 = 0, DQS1 = 0
4849 00:44:20.147868 DQM Delay:
4850 00:44:20.150463 DQM0 = 36, DQM1 = 29
4851 00:44:20.150846 DQ Delay:
4852 00:44:20.153994 DQ0 =36, DQ1 =32, DQ2 =24, DQ3 =32
4853 00:44:20.157428 DQ4 =32, DQ5 =48, DQ6 =48, DQ7 =36
4854 00:44:20.160422 DQ8 =16, DQ9 =16, DQ10 =32, DQ11 =24
4855 00:44:20.163709 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4856 00:44:20.164106
4857 00:44:20.164434
4858 00:44:20.173788 [DQSOSCAuto] RK1, (LSB)MR18= 0x3b5a, (MSB)MR19= 0x808, tDQSOscB0 = 392 ps tDQSOscB1 = 398 ps
4859 00:44:20.176767 CH1 RK1: MR19=808, MR18=3B5A
4860 00:44:20.183886 CH1_RK1: MR19=0x808, MR18=0x3B5A, DQSOSC=392, MR23=63, INC=170, DEC=113
4861 00:44:20.184282 [RxdqsGatingPostProcess] freq 600
4862 00:44:20.190051 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4863 00:44:20.193495 Pre-setting of DQS Precalculation
4864 00:44:20.197068 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4865 00:44:20.206493 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4866 00:44:20.213435 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4867 00:44:20.213843
4868 00:44:20.214239
4869 00:44:20.216988 [Calibration Summary] 1200 Mbps
4870 00:44:20.217389 CH 0, Rank 0
4871 00:44:20.219871 SW Impedance : PASS
4872 00:44:20.220271 DUTY Scan : NO K
4873 00:44:20.223349 ZQ Calibration : PASS
4874 00:44:20.226788 Jitter Meter : NO K
4875 00:44:20.227190 CBT Training : PASS
4876 00:44:20.230321 Write leveling : PASS
4877 00:44:20.233175 RX DQS gating : PASS
4878 00:44:20.233577 RX DQ/DQS(RDDQC) : PASS
4879 00:44:20.236495 TX DQ/DQS : PASS
4880 00:44:20.239812 RX DATLAT : PASS
4881 00:44:20.240218 RX DQ/DQS(Engine): PASS
4882 00:44:20.242921 TX OE : NO K
4883 00:44:20.243324 All Pass.
4884 00:44:20.243719
4885 00:44:20.246745 CH 0, Rank 1
4886 00:44:20.247145 SW Impedance : PASS
4887 00:44:20.249710 DUTY Scan : NO K
4888 00:44:20.253596 ZQ Calibration : PASS
4889 00:44:20.254000 Jitter Meter : NO K
4890 00:44:20.256240 CBT Training : PASS
4891 00:44:20.256673 Write leveling : PASS
4892 00:44:20.259825 RX DQS gating : PASS
4893 00:44:20.263372 RX DQ/DQS(RDDQC) : PASS
4894 00:44:20.263771 TX DQ/DQS : PASS
4895 00:44:20.266270 RX DATLAT : PASS
4896 00:44:20.269694 RX DQ/DQS(Engine): PASS
4897 00:44:20.270095 TX OE : NO K
4898 00:44:20.273422 All Pass.
4899 00:44:20.273821
4900 00:44:20.274219 CH 1, Rank 0
4901 00:44:20.276467 SW Impedance : PASS
4902 00:44:20.276916 DUTY Scan : NO K
4903 00:44:20.279847 ZQ Calibration : PASS
4904 00:44:20.283364 Jitter Meter : NO K
4905 00:44:20.283764 CBT Training : PASS
4906 00:44:20.286301 Write leveling : PASS
4907 00:44:20.289727 RX DQS gating : PASS
4908 00:44:20.290127 RX DQ/DQS(RDDQC) : PASS
4909 00:44:20.293133 TX DQ/DQS : PASS
4910 00:44:20.296459 RX DATLAT : PASS
4911 00:44:20.296913 RX DQ/DQS(Engine): PASS
4912 00:44:20.299903 TX OE : NO K
4913 00:44:20.300304 All Pass.
4914 00:44:20.300742
4915 00:44:20.301122 CH 1, Rank 1
4916 00:44:20.303029 SW Impedance : PASS
4917 00:44:20.306624 DUTY Scan : NO K
4918 00:44:20.307230 ZQ Calibration : PASS
4919 00:44:20.309600 Jitter Meter : NO K
4920 00:44:20.313493 CBT Training : PASS
4921 00:44:20.313890 Write leveling : PASS
4922 00:44:20.316523 RX DQS gating : PASS
4923 00:44:20.319721 RX DQ/DQS(RDDQC) : PASS
4924 00:44:20.320142 TX DQ/DQS : PASS
4925 00:44:20.323496 RX DATLAT : PASS
4926 00:44:20.326174 RX DQ/DQS(Engine): PASS
4927 00:44:20.326618 TX OE : NO K
4928 00:44:20.329619 All Pass.
4929 00:44:20.330014
4930 00:44:20.330332 DramC Write-DBI off
4931 00:44:20.333098 PER_BANK_REFRESH: Hybrid Mode
4932 00:44:20.333428 TX_TRACKING: ON
4933 00:44:20.342953 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4934 00:44:20.346227 [FAST_K] Save calibration result to emmc
4935 00:44:20.349539 dramc_set_vcore_voltage set vcore to 662500
4936 00:44:20.352890 Read voltage for 933, 3
4937 00:44:20.353294 Vio18 = 0
4938 00:44:20.356419 Vcore = 662500
4939 00:44:20.356798 Vdram = 0
4940 00:44:20.357087 Vddq = 0
4941 00:44:20.359317 Vmddr = 0
4942 00:44:20.362716 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4943 00:44:20.369240 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4944 00:44:20.369631 MEM_TYPE=3, freq_sel=17
4945 00:44:20.372977 sv_algorithm_assistance_LP4_1600
4946 00:44:20.376207 ============ PULL DRAM RESETB DOWN ============
4947 00:44:20.382448 ========== PULL DRAM RESETB DOWN end =========
4948 00:44:20.386160 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4949 00:44:20.389340 ===================================
4950 00:44:20.392531 LPDDR4 DRAM CONFIGURATION
4951 00:44:20.396008 ===================================
4952 00:44:20.396393 EX_ROW_EN[0] = 0x0
4953 00:44:20.399478 EX_ROW_EN[1] = 0x0
4954 00:44:20.402315 LP4Y_EN = 0x0
4955 00:44:20.402699 WORK_FSP = 0x0
4956 00:44:20.405630 WL = 0x3
4957 00:44:20.406011 RL = 0x3
4958 00:44:20.409145 BL = 0x2
4959 00:44:20.409532 RPST = 0x0
4960 00:44:20.412854 RD_PRE = 0x0
4961 00:44:20.413262 WR_PRE = 0x1
4962 00:44:20.415927 WR_PST = 0x0
4963 00:44:20.416345 DBI_WR = 0x0
4964 00:44:20.419339 DBI_RD = 0x0
4965 00:44:20.419726 OTF = 0x1
4966 00:44:20.422531 ===================================
4967 00:44:20.425762 ===================================
4968 00:44:20.428962 ANA top config
4969 00:44:20.432495 ===================================
4970 00:44:20.432921 DLL_ASYNC_EN = 0
4971 00:44:20.435884 ALL_SLAVE_EN = 1
4972 00:44:20.438901 NEW_RANK_MODE = 1
4973 00:44:20.442293 DLL_IDLE_MODE = 1
4974 00:44:20.445791 LP45_APHY_COMB_EN = 1
4975 00:44:20.446175 TX_ODT_DIS = 1
4976 00:44:20.449020 NEW_8X_MODE = 1
4977 00:44:20.452342 ===================================
4978 00:44:20.455741 ===================================
4979 00:44:20.459005 data_rate = 1866
4980 00:44:20.462240 CKR = 1
4981 00:44:20.465773 DQ_P2S_RATIO = 8
4982 00:44:20.469278 ===================================
4983 00:44:20.469663 CA_P2S_RATIO = 8
4984 00:44:20.472509 DQ_CA_OPEN = 0
4985 00:44:20.475395 DQ_SEMI_OPEN = 0
4986 00:44:20.478731 CA_SEMI_OPEN = 0
4987 00:44:20.482175 CA_FULL_RATE = 0
4988 00:44:20.485992 DQ_CKDIV4_EN = 1
4989 00:44:20.486383 CA_CKDIV4_EN = 1
4990 00:44:20.489032 CA_PREDIV_EN = 0
4991 00:44:20.492513 PH8_DLY = 0
4992 00:44:20.495712 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4993 00:44:20.498997 DQ_AAMCK_DIV = 4
4994 00:44:20.502383 CA_AAMCK_DIV = 4
4995 00:44:20.502776 CA_ADMCK_DIV = 4
4996 00:44:20.505522 DQ_TRACK_CA_EN = 0
4997 00:44:20.508745 CA_PICK = 933
4998 00:44:20.512057 CA_MCKIO = 933
4999 00:44:20.515604 MCKIO_SEMI = 0
5000 00:44:20.519117 PLL_FREQ = 3732
5001 00:44:20.522368 DQ_UI_PI_RATIO = 32
5002 00:44:20.522759 CA_UI_PI_RATIO = 0
5003 00:44:20.525447 ===================================
5004 00:44:20.528868 ===================================
5005 00:44:20.532512 memory_type:LPDDR4
5006 00:44:20.535481 GP_NUM : 10
5007 00:44:20.535875 SRAM_EN : 1
5008 00:44:20.538860 MD32_EN : 0
5009 00:44:20.542150 ===================================
5010 00:44:20.545550 [ANA_INIT] >>>>>>>>>>>>>>
5011 00:44:20.548953 <<<<<< [CONFIGURE PHASE]: ANA_TX
5012 00:44:20.551819 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5013 00:44:20.555521 ===================================
5014 00:44:20.555909 data_rate = 1866,PCW = 0X8f00
5015 00:44:20.558306 ===================================
5016 00:44:20.561836 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5017 00:44:20.568558 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5018 00:44:20.575467 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5019 00:44:20.578908 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5020 00:44:20.581707 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5021 00:44:20.585151 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5022 00:44:20.588642 [ANA_INIT] flow start
5023 00:44:20.589057 [ANA_INIT] PLL >>>>>>>>
5024 00:44:20.592221 [ANA_INIT] PLL <<<<<<<<
5025 00:44:20.595004 [ANA_INIT] MIDPI >>>>>>>>
5026 00:44:20.598356 [ANA_INIT] MIDPI <<<<<<<<
5027 00:44:20.598746 [ANA_INIT] DLL >>>>>>>>
5028 00:44:20.601757 [ANA_INIT] flow end
5029 00:44:20.604980 ============ LP4 DIFF to SE enter ============
5030 00:44:20.608527 ============ LP4 DIFF to SE exit ============
5031 00:44:20.611814 [ANA_INIT] <<<<<<<<<<<<<
5032 00:44:20.615058 [Flow] Enable top DCM control >>>>>
5033 00:44:20.618429 [Flow] Enable top DCM control <<<<<
5034 00:44:20.621885 Enable DLL master slave shuffle
5035 00:44:20.628355 ==============================================================
5036 00:44:20.628908 Gating Mode config
5037 00:44:20.635236 ==============================================================
5038 00:44:20.635630 Config description:
5039 00:44:20.644919 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5040 00:44:20.651882 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5041 00:44:20.657992 SELPH_MODE 0: By rank 1: By Phase
5042 00:44:20.661425 ==============================================================
5043 00:44:20.664960 GAT_TRACK_EN = 1
5044 00:44:20.668424 RX_GATING_MODE = 2
5045 00:44:20.671599 RX_GATING_TRACK_MODE = 2
5046 00:44:20.674764 SELPH_MODE = 1
5047 00:44:20.678163 PICG_EARLY_EN = 1
5048 00:44:20.681349 VALID_LAT_VALUE = 1
5049 00:44:20.684803 ==============================================================
5050 00:44:20.688266 Enter into Gating configuration >>>>
5051 00:44:20.691613 Exit from Gating configuration <<<<
5052 00:44:20.694451 Enter into DVFS_PRE_config >>>>>
5053 00:44:20.708009 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5054 00:44:20.711504 Exit from DVFS_PRE_config <<<<<
5055 00:44:20.714370 Enter into PICG configuration >>>>
5056 00:44:20.717637 Exit from PICG configuration <<<<
5057 00:44:20.718028 [RX_INPUT] configuration >>>>>
5058 00:44:20.721130 [RX_INPUT] configuration <<<<<
5059 00:44:20.727655 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5060 00:44:20.731295 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5061 00:44:20.737844 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5062 00:44:20.744336 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5063 00:44:20.751224 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5064 00:44:20.757664 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5065 00:44:20.760886 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5066 00:44:20.764935 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5067 00:44:20.771115 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5068 00:44:20.774316 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5069 00:44:20.777723 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5070 00:44:20.780935 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5071 00:44:20.784107 ===================================
5072 00:44:20.787570 LPDDR4 DRAM CONFIGURATION
5073 00:44:20.790518 ===================================
5074 00:44:20.794095 EX_ROW_EN[0] = 0x0
5075 00:44:20.794646 EX_ROW_EN[1] = 0x0
5076 00:44:20.797562 LP4Y_EN = 0x0
5077 00:44:20.798099 WORK_FSP = 0x0
5078 00:44:20.800999 WL = 0x3
5079 00:44:20.801454 RL = 0x3
5080 00:44:20.803905 BL = 0x2
5081 00:44:20.804379 RPST = 0x0
5082 00:44:20.807473 RD_PRE = 0x0
5083 00:44:20.807929 WR_PRE = 0x1
5084 00:44:20.810916 WR_PST = 0x0
5085 00:44:20.811559 DBI_WR = 0x0
5086 00:44:20.813869 DBI_RD = 0x0
5087 00:44:20.817260 OTF = 0x1
5088 00:44:20.820841 ===================================
5089 00:44:20.824116 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5090 00:44:20.827502 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5091 00:44:20.830901 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5092 00:44:20.834365 ===================================
5093 00:44:20.837735 LPDDR4 DRAM CONFIGURATION
5094 00:44:20.840681 ===================================
5095 00:44:20.844100 EX_ROW_EN[0] = 0x10
5096 00:44:20.844629 EX_ROW_EN[1] = 0x0
5097 00:44:20.847489 LP4Y_EN = 0x0
5098 00:44:20.847936 WORK_FSP = 0x0
5099 00:44:20.850679 WL = 0x3
5100 00:44:20.851205 RL = 0x3
5101 00:44:20.854430 BL = 0x2
5102 00:44:20.854955 RPST = 0x0
5103 00:44:20.857536 RD_PRE = 0x0
5104 00:44:20.858023 WR_PRE = 0x1
5105 00:44:20.860482 WR_PST = 0x0
5106 00:44:20.861053 DBI_WR = 0x0
5107 00:44:20.863779 DBI_RD = 0x0
5108 00:44:20.864387 OTF = 0x1
5109 00:44:20.867507 ===================================
5110 00:44:20.873680 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5111 00:44:20.878926 nWR fixed to 30
5112 00:44:20.882110 [ModeRegInit_LP4] CH0 RK0
5113 00:44:20.882528 [ModeRegInit_LP4] CH0 RK1
5114 00:44:20.885226 [ModeRegInit_LP4] CH1 RK0
5115 00:44:20.888708 [ModeRegInit_LP4] CH1 RK1
5116 00:44:20.889096 match AC timing 9
5117 00:44:20.895622 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5118 00:44:20.898414 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5119 00:44:20.901959 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5120 00:44:20.908641 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5121 00:44:20.912164 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5122 00:44:20.912564 ==
5123 00:44:20.915486 Dram Type= 6, Freq= 0, CH_0, rank 0
5124 00:44:20.918393 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5125 00:44:20.918809 ==
5126 00:44:20.925328 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5127 00:44:20.931452 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5128 00:44:20.934992 [CA 0] Center 38 (8~69) winsize 62
5129 00:44:20.938440 [CA 1] Center 38 (7~69) winsize 63
5130 00:44:20.941883 [CA 2] Center 35 (5~66) winsize 62
5131 00:44:20.944756 [CA 3] Center 35 (5~66) winsize 62
5132 00:44:20.948113 [CA 4] Center 34 (4~65) winsize 62
5133 00:44:20.951665 [CA 5] Center 34 (4~64) winsize 61
5134 00:44:20.952066
5135 00:44:20.954978 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5136 00:44:20.955377
5137 00:44:20.957882 [CATrainingPosCal] consider 1 rank data
5138 00:44:20.961276 u2DelayCellTimex100 = 270/100 ps
5139 00:44:20.964497 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5140 00:44:20.968262 CA1 delay=38 (7~69),Diff = 4 PI (24 cell)
5141 00:44:20.971302 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5142 00:44:20.974993 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
5143 00:44:20.977663 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5144 00:44:20.984713 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5145 00:44:20.985122
5146 00:44:20.987886 CA PerBit enable=1, Macro0, CA PI delay=34
5147 00:44:20.988291
5148 00:44:20.990917 [CBTSetCACLKResult] CA Dly = 34
5149 00:44:20.991319 CS Dly: 7 (0~38)
5150 00:44:20.991721 ==
5151 00:44:20.994304 Dram Type= 6, Freq= 0, CH_0, rank 1
5152 00:44:21.000700 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5153 00:44:21.001112 ==
5154 00:44:21.004117 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5155 00:44:21.011047 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5156 00:44:21.014275 [CA 0] Center 38 (8~69) winsize 62
5157 00:44:21.017707 [CA 1] Center 38 (7~69) winsize 63
5158 00:44:21.020903 [CA 2] Center 35 (5~66) winsize 62
5159 00:44:21.024016 [CA 3] Center 35 (5~66) winsize 62
5160 00:44:21.027356 [CA 4] Center 34 (4~65) winsize 62
5161 00:44:21.030835 [CA 5] Center 33 (3~64) winsize 62
5162 00:44:21.031345
5163 00:44:21.034101 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5164 00:44:21.034492
5165 00:44:21.037662 [CATrainingPosCal] consider 2 rank data
5166 00:44:21.041045 u2DelayCellTimex100 = 270/100 ps
5167 00:44:21.044329 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5168 00:44:21.047817 CA1 delay=38 (7~69),Diff = 4 PI (24 cell)
5169 00:44:21.050637 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5170 00:44:21.057363 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
5171 00:44:21.060977 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5172 00:44:21.064201 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5173 00:44:21.064590
5174 00:44:21.067699 CA PerBit enable=1, Macro0, CA PI delay=34
5175 00:44:21.068091
5176 00:44:21.070676 [CBTSetCACLKResult] CA Dly = 34
5177 00:44:21.071063 CS Dly: 7 (0~39)
5178 00:44:21.071368
5179 00:44:21.074053 ----->DramcWriteLeveling(PI) begin...
5180 00:44:21.074487 ==
5181 00:44:21.077082 Dram Type= 6, Freq= 0, CH_0, rank 0
5182 00:44:21.083859 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5183 00:44:21.084285 ==
5184 00:44:21.087485 Write leveling (Byte 0): 31 => 31
5185 00:44:21.090631 Write leveling (Byte 1): 29 => 29
5186 00:44:21.091017 DramcWriteLeveling(PI) end<-----
5187 00:44:21.093953
5188 00:44:21.094336 ==
5189 00:44:21.097143 Dram Type= 6, Freq= 0, CH_0, rank 0
5190 00:44:21.100395 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5191 00:44:21.100843 ==
5192 00:44:21.103782 [Gating] SW mode calibration
5193 00:44:21.110684 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5194 00:44:21.113917 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5195 00:44:21.120590 0 14 0 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (0 0)
5196 00:44:21.123848 0 14 4 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
5197 00:44:21.127045 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5198 00:44:21.133470 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5199 00:44:21.137610 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5200 00:44:21.140286 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5201 00:44:21.146892 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5202 00:44:21.150712 0 14 28 | B1->B0 | 3434 3434 | 1 0 | (1 1) (1 0)
5203 00:44:21.154139 0 15 0 | B1->B0 | 3434 2d2d | 0 0 | (0 1) (1 0)
5204 00:44:21.160372 0 15 4 | B1->B0 | 2727 2323 | 0 0 | (1 1) (0 0)
5205 00:44:21.163783 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5206 00:44:21.166711 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5207 00:44:21.173677 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5208 00:44:21.177124 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5209 00:44:21.179982 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5210 00:44:21.187219 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5211 00:44:21.190464 1 0 0 | B1->B0 | 2b2b 3e3e | 0 0 | (0 0) (0 0)
5212 00:44:21.193616 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5213 00:44:21.200284 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5214 00:44:21.203351 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5215 00:44:21.206665 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5216 00:44:21.213691 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5217 00:44:21.217062 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5218 00:44:21.219966 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5219 00:44:21.226490 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5220 00:44:21.229978 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5221 00:44:21.233453 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5222 00:44:21.240179 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5223 00:44:21.243441 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5224 00:44:21.246532 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5225 00:44:21.249775 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5226 00:44:21.256134 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5227 00:44:21.259965 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5228 00:44:21.263032 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5229 00:44:21.269909 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5230 00:44:21.273335 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5231 00:44:21.276187 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5232 00:44:21.283101 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5233 00:44:21.286348 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5234 00:44:21.289761 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5235 00:44:21.296035 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5236 00:44:21.299363 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5237 00:44:21.303092 Total UI for P1: 0, mck2ui 16
5238 00:44:21.306320 best dqsien dly found for B0: ( 1, 2, 30)
5239 00:44:21.309571 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5240 00:44:21.313315 Total UI for P1: 0, mck2ui 16
5241 00:44:21.315868 best dqsien dly found for B1: ( 1, 3, 4)
5242 00:44:21.319509 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5243 00:44:21.322929 best DQS1 dly(MCK, UI, PI) = (1, 3, 4)
5244 00:44:21.323318
5245 00:44:21.329128 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5246 00:44:21.332589 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 4)
5247 00:44:21.336003 [Gating] SW calibration Done
5248 00:44:21.336391 ==
5249 00:44:21.339439 Dram Type= 6, Freq= 0, CH_0, rank 0
5250 00:44:21.342792 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5251 00:44:21.343184 ==
5252 00:44:21.343486 RX Vref Scan: 0
5253 00:44:21.343770
5254 00:44:21.345667 RX Vref 0 -> 0, step: 1
5255 00:44:21.346053
5256 00:44:21.349069 RX Delay -80 -> 252, step: 8
5257 00:44:21.352347 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5258 00:44:21.355683 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5259 00:44:21.359084 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5260 00:44:21.365902 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5261 00:44:21.369359 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5262 00:44:21.372487 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5263 00:44:21.376074 iDelay=208, Bit 6, Center 99 (0 ~ 199) 200
5264 00:44:21.378937 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5265 00:44:21.385897 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5266 00:44:21.389254 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5267 00:44:21.392615 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5268 00:44:21.395587 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5269 00:44:21.398977 iDelay=208, Bit 12, Center 87 (-16 ~ 191) 208
5270 00:44:21.405870 iDelay=208, Bit 13, Center 87 (-16 ~ 191) 208
5271 00:44:21.409157 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5272 00:44:21.412369 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5273 00:44:21.412791 ==
5274 00:44:21.415581 Dram Type= 6, Freq= 0, CH_0, rank 0
5275 00:44:21.418884 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5276 00:44:21.419272 ==
5277 00:44:21.422183 DQS Delay:
5278 00:44:21.422586 DQS0 = 0, DQS1 = 0
5279 00:44:21.425429 DQM Delay:
5280 00:44:21.425809 DQM0 = 94, DQM1 = 83
5281 00:44:21.426106 DQ Delay:
5282 00:44:21.428783 DQ0 =91, DQ1 =95, DQ2 =91, DQ3 =91
5283 00:44:21.432022 DQ4 =95, DQ5 =79, DQ6 =99, DQ7 =111
5284 00:44:21.435300 DQ8 =75, DQ9 =71, DQ10 =83, DQ11 =79
5285 00:44:21.438756 DQ12 =87, DQ13 =87, DQ14 =91, DQ15 =91
5286 00:44:21.439143
5287 00:44:21.439448
5288 00:44:21.441928 ==
5289 00:44:21.442316 Dram Type= 6, Freq= 0, CH_0, rank 0
5290 00:44:21.448998 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5291 00:44:21.449399 ==
5292 00:44:21.449704
5293 00:44:21.449984
5294 00:44:21.451956 TX Vref Scan disable
5295 00:44:21.452347 == TX Byte 0 ==
5296 00:44:21.455315 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5297 00:44:21.461981 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5298 00:44:21.462477 == TX Byte 1 ==
5299 00:44:21.465450 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5300 00:44:21.472122 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5301 00:44:21.472556 ==
5302 00:44:21.475324 Dram Type= 6, Freq= 0, CH_0, rank 0
5303 00:44:21.478986 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5304 00:44:21.479378 ==
5305 00:44:21.479682
5306 00:44:21.479960
5307 00:44:21.481766 TX Vref Scan disable
5308 00:44:21.484957 == TX Byte 0 ==
5309 00:44:21.488578 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5310 00:44:21.492238 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5311 00:44:21.495968 == TX Byte 1 ==
5312 00:44:21.498683 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5313 00:44:21.502081 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5314 00:44:21.502472
5315 00:44:21.502779 [DATLAT]
5316 00:44:21.504929 Freq=933, CH0 RK0
5317 00:44:21.505319
5318 00:44:21.508477 DATLAT Default: 0xd
5319 00:44:21.508915 0, 0xFFFF, sum = 0
5320 00:44:21.511884 1, 0xFFFF, sum = 0
5321 00:44:21.512476 2, 0xFFFF, sum = 0
5322 00:44:21.515184 3, 0xFFFF, sum = 0
5323 00:44:21.515583 4, 0xFFFF, sum = 0
5324 00:44:21.518323 5, 0xFFFF, sum = 0
5325 00:44:21.518719 6, 0xFFFF, sum = 0
5326 00:44:21.521823 7, 0xFFFF, sum = 0
5327 00:44:21.522219 8, 0xFFFF, sum = 0
5328 00:44:21.525275 9, 0xFFFF, sum = 0
5329 00:44:21.525673 10, 0x0, sum = 1
5330 00:44:21.528619 11, 0x0, sum = 2
5331 00:44:21.529060 12, 0x0, sum = 3
5332 00:44:21.531429 13, 0x0, sum = 4
5333 00:44:21.531825 best_step = 11
5334 00:44:21.532124
5335 00:44:21.532402 ==
5336 00:44:21.534863 Dram Type= 6, Freq= 0, CH_0, rank 0
5337 00:44:21.538177 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5338 00:44:21.542057 ==
5339 00:44:21.542446 RX Vref Scan: 1
5340 00:44:21.542749
5341 00:44:21.544846 RX Vref 0 -> 0, step: 1
5342 00:44:21.545229
5343 00:44:21.545534 RX Delay -69 -> 252, step: 4
5344 00:44:21.548322
5345 00:44:21.548685 Set Vref, RX VrefLevel [Byte0]: 61
5346 00:44:21.551479 [Byte1]: 48
5347 00:44:21.556466
5348 00:44:21.556999 Final RX Vref Byte 0 = 61 to rank0
5349 00:44:21.559774 Final RX Vref Byte 1 = 48 to rank0
5350 00:44:21.563147 Final RX Vref Byte 0 = 61 to rank1
5351 00:44:21.566508 Final RX Vref Byte 1 = 48 to rank1==
5352 00:44:21.569794 Dram Type= 6, Freq= 0, CH_0, rank 0
5353 00:44:21.576703 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5354 00:44:21.577107 ==
5355 00:44:21.577500 DQS Delay:
5356 00:44:21.577937 DQS0 = 0, DQS1 = 0
5357 00:44:21.579636 DQM Delay:
5358 00:44:21.580029 DQM0 = 96, DQM1 = 83
5359 00:44:21.583171 DQ Delay:
5360 00:44:21.586157 DQ0 =94, DQ1 =94, DQ2 =94, DQ3 =94
5361 00:44:21.589972 DQ4 =96, DQ5 =84, DQ6 =104, DQ7 =108
5362 00:44:21.592908 DQ8 =76, DQ9 =68, DQ10 =82, DQ11 =78
5363 00:44:21.596395 DQ12 =86, DQ13 =88, DQ14 =96, DQ15 =92
5364 00:44:21.596906
5365 00:44:21.597335
5366 00:44:21.603009 [DQSOSCAuto] RK0, (LSB)MR18= 0x1818, (MSB)MR19= 0x505, tDQSOscB0 = 414 ps tDQSOscB1 = 414 ps
5367 00:44:21.606640 CH0 RK0: MR19=505, MR18=1818
5368 00:44:21.613052 CH0_RK0: MR19=0x505, MR18=0x1818, DQSOSC=414, MR23=63, INC=63, DEC=42
5369 00:44:21.613267
5370 00:44:21.615876 ----->DramcWriteLeveling(PI) begin...
5371 00:44:21.616105 ==
5372 00:44:21.619182 Dram Type= 6, Freq= 0, CH_0, rank 1
5373 00:44:21.622718 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5374 00:44:21.622885 ==
5375 00:44:21.625960 Write leveling (Byte 0): 29 => 29
5376 00:44:21.629598 Write leveling (Byte 1): 29 => 29
5377 00:44:21.632870 DramcWriteLeveling(PI) end<-----
5378 00:44:21.633120
5379 00:44:21.633302 ==
5380 00:44:21.635713 Dram Type= 6, Freq= 0, CH_0, rank 1
5381 00:44:21.639632 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5382 00:44:21.639800 ==
5383 00:44:21.642445 [Gating] SW mode calibration
5384 00:44:21.649404 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5385 00:44:21.656243 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5386 00:44:21.659499 0 14 0 | B1->B0 | 2929 3434 | 0 1 | (0 0) (1 1)
5387 00:44:21.666457 0 14 4 | B1->B0 | 3333 3434 | 1 1 | (0 0) (1 1)
5388 00:44:21.669322 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5389 00:44:21.672946 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5390 00:44:21.676749 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5391 00:44:21.683295 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5392 00:44:21.686390 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5393 00:44:21.689679 0 14 28 | B1->B0 | 3333 2d2d | 1 0 | (1 1) (1 0)
5394 00:44:21.696519 0 15 0 | B1->B0 | 2f2f 2323 | 0 0 | (0 1) (0 0)
5395 00:44:21.699914 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5396 00:44:21.703508 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5397 00:44:21.709441 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5398 00:44:21.712871 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5399 00:44:21.716158 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5400 00:44:21.723033 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5401 00:44:21.726375 0 15 28 | B1->B0 | 2424 3a3a | 0 0 | (0 0) (0 0)
5402 00:44:21.729265 1 0 0 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
5403 00:44:21.736258 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5404 00:44:21.739600 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5405 00:44:21.743241 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5406 00:44:21.749388 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5407 00:44:21.752460 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5408 00:44:21.756277 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5409 00:44:21.762745 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5410 00:44:21.765929 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5411 00:44:21.769265 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5412 00:44:21.775785 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5413 00:44:21.779338 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5414 00:44:21.783012 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5415 00:44:21.789313 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5416 00:44:21.792717 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5417 00:44:21.795672 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5418 00:44:21.802333 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5419 00:44:21.805537 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5420 00:44:21.808955 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5421 00:44:21.815668 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5422 00:44:21.819082 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5423 00:44:21.822399 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5424 00:44:21.825814 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5425 00:44:21.832227 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5426 00:44:21.835759 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5427 00:44:21.838899 Total UI for P1: 0, mck2ui 16
5428 00:44:21.842402 best dqsien dly found for B0: ( 1, 2, 26)
5429 00:44:21.845323 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5430 00:44:21.848679 Total UI for P1: 0, mck2ui 16
5431 00:44:21.852152 best dqsien dly found for B1: ( 1, 3, 0)
5432 00:44:21.855422 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5433 00:44:21.859124 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5434 00:44:21.859514
5435 00:44:21.865220 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5436 00:44:21.868673 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5437 00:44:21.872120 [Gating] SW calibration Done
5438 00:44:21.872504 ==
5439 00:44:21.875458 Dram Type= 6, Freq= 0, CH_0, rank 1
5440 00:44:21.878787 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5441 00:44:21.879182 ==
5442 00:44:21.879485 RX Vref Scan: 0
5443 00:44:21.879824
5444 00:44:21.882133 RX Vref 0 -> 0, step: 1
5445 00:44:21.882523
5446 00:44:21.885319 RX Delay -80 -> 252, step: 8
5447 00:44:21.888986 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5448 00:44:21.891998 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5449 00:44:21.895035 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5450 00:44:21.902189 iDelay=208, Bit 3, Center 87 (-16 ~ 191) 208
5451 00:44:21.905236 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5452 00:44:21.908620 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5453 00:44:21.911967 iDelay=208, Bit 6, Center 99 (0 ~ 199) 200
5454 00:44:21.915059 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5455 00:44:21.921696 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5456 00:44:21.924493 iDelay=208, Bit 9, Center 67 (-32 ~ 167) 200
5457 00:44:21.927930 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5458 00:44:21.931432 iDelay=208, Bit 11, Center 75 (-16 ~ 167) 184
5459 00:44:21.934863 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5460 00:44:21.941527 iDelay=208, Bit 13, Center 87 (-16 ~ 191) 208
5461 00:44:21.944676 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5462 00:44:21.948041 iDelay=208, Bit 15, Center 87 (-8 ~ 183) 192
5463 00:44:21.948117 ==
5464 00:44:21.951448 Dram Type= 6, Freq= 0, CH_0, rank 1
5465 00:44:21.954870 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5466 00:44:21.954947 ==
5467 00:44:21.958361 DQS Delay:
5468 00:44:21.958437 DQS0 = 0, DQS1 = 0
5469 00:44:21.961210 DQM Delay:
5470 00:44:21.961285 DQM0 = 91, DQM1 = 82
5471 00:44:21.961344 DQ Delay:
5472 00:44:21.964549 DQ0 =91, DQ1 =91, DQ2 =87, DQ3 =87
5473 00:44:21.968263 DQ4 =91, DQ5 =79, DQ6 =99, DQ7 =107
5474 00:44:21.971533 DQ8 =75, DQ9 =67, DQ10 =87, DQ11 =75
5475 00:44:21.974439 DQ12 =91, DQ13 =87, DQ14 =91, DQ15 =87
5476 00:44:21.974514
5477 00:44:21.974574
5478 00:44:21.978068 ==
5479 00:44:21.978144 Dram Type= 6, Freq= 0, CH_0, rank 1
5480 00:44:21.984586 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5481 00:44:21.984669 ==
5482 00:44:21.984729
5483 00:44:21.984784
5484 00:44:21.987983 TX Vref Scan disable
5485 00:44:21.988058 == TX Byte 0 ==
5486 00:44:21.991834 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5487 00:44:21.998230 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5488 00:44:21.998379 == TX Byte 1 ==
5489 00:44:22.001236 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5490 00:44:22.008205 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5491 00:44:22.008370 ==
5492 00:44:22.010915 Dram Type= 6, Freq= 0, CH_0, rank 1
5493 00:44:22.014254 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5494 00:44:22.014402 ==
5495 00:44:22.014541
5496 00:44:22.014652
5497 00:44:22.017561 TX Vref Scan disable
5498 00:44:22.020668 == TX Byte 0 ==
5499 00:44:22.024331 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5500 00:44:22.027466 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5501 00:44:22.030700 == TX Byte 1 ==
5502 00:44:22.033964 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5503 00:44:22.037477 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5504 00:44:22.037569
5505 00:44:22.041144 [DATLAT]
5506 00:44:22.041239 Freq=933, CH0 RK1
5507 00:44:22.041313
5508 00:44:22.044350 DATLAT Default: 0xb
5509 00:44:22.044444 0, 0xFFFF, sum = 0
5510 00:44:22.047613 1, 0xFFFF, sum = 0
5511 00:44:22.047718 2, 0xFFFF, sum = 0
5512 00:44:22.050616 3, 0xFFFF, sum = 0
5513 00:44:22.050740 4, 0xFFFF, sum = 0
5514 00:44:22.054030 5, 0xFFFF, sum = 0
5515 00:44:22.054145 6, 0xFFFF, sum = 0
5516 00:44:22.057382 7, 0xFFFF, sum = 0
5517 00:44:22.057509 8, 0xFFFF, sum = 0
5518 00:44:22.060636 9, 0xFFFF, sum = 0
5519 00:44:22.060806 10, 0x0, sum = 1
5520 00:44:22.064283 11, 0x0, sum = 2
5521 00:44:22.064424 12, 0x0, sum = 3
5522 00:44:22.067565 13, 0x0, sum = 4
5523 00:44:22.067727 best_step = 11
5524 00:44:22.067851
5525 00:44:22.067966 ==
5526 00:44:22.070597 Dram Type= 6, Freq= 0, CH_0, rank 1
5527 00:44:22.077180 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5528 00:44:22.077403 ==
5529 00:44:22.077576 RX Vref Scan: 0
5530 00:44:22.077738
5531 00:44:22.080459 RX Vref 0 -> 0, step: 1
5532 00:44:22.080792
5533 00:44:22.083792 RX Delay -77 -> 252, step: 4
5534 00:44:22.087194 iDelay=199, Bit 0, Center 90 (-5 ~ 186) 192
5535 00:44:22.090618 iDelay=199, Bit 1, Center 92 (-1 ~ 186) 188
5536 00:44:22.097427 iDelay=199, Bit 2, Center 88 (-5 ~ 182) 188
5537 00:44:22.100791 iDelay=199, Bit 3, Center 88 (-9 ~ 186) 196
5538 00:44:22.104054 iDelay=199, Bit 4, Center 92 (-1 ~ 186) 188
5539 00:44:22.107213 iDelay=199, Bit 5, Center 80 (-13 ~ 174) 188
5540 00:44:22.110638 iDelay=199, Bit 6, Center 106 (15 ~ 198) 184
5541 00:44:22.117068 iDelay=199, Bit 7, Center 102 (11 ~ 194) 184
5542 00:44:22.120563 iDelay=199, Bit 8, Center 76 (-13 ~ 166) 180
5543 00:44:22.123479 iDelay=199, Bit 9, Center 66 (-21 ~ 154) 176
5544 00:44:22.126970 iDelay=199, Bit 10, Center 86 (-5 ~ 178) 184
5545 00:44:22.130178 iDelay=199, Bit 11, Center 76 (-13 ~ 166) 180
5546 00:44:22.136977 iDelay=199, Bit 12, Center 90 (-1 ~ 182) 184
5547 00:44:22.140390 iDelay=199, Bit 13, Center 90 (-1 ~ 182) 184
5548 00:44:22.143871 iDelay=199, Bit 14, Center 94 (3 ~ 186) 184
5549 00:44:22.147425 iDelay=199, Bit 15, Center 92 (3 ~ 182) 180
5550 00:44:22.147897 ==
5551 00:44:22.150126 Dram Type= 6, Freq= 0, CH_0, rank 1
5552 00:44:22.153440 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5553 00:44:22.153853 ==
5554 00:44:22.156807 DQS Delay:
5555 00:44:22.157205 DQS0 = 0, DQS1 = 0
5556 00:44:22.160288 DQM Delay:
5557 00:44:22.160721 DQM0 = 92, DQM1 = 83
5558 00:44:22.161038 DQ Delay:
5559 00:44:22.163634 DQ0 =90, DQ1 =92, DQ2 =88, DQ3 =88
5560 00:44:22.166976 DQ4 =92, DQ5 =80, DQ6 =106, DQ7 =102
5561 00:44:22.170102 DQ8 =76, DQ9 =66, DQ10 =86, DQ11 =76
5562 00:44:22.173626 DQ12 =90, DQ13 =90, DQ14 =94, DQ15 =92
5563 00:44:22.174016
5564 00:44:22.177175
5565 00:44:22.183711 [DQSOSCAuto] RK1, (LSB)MR18= 0x3214, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 406 ps
5566 00:44:22.186578 CH0 RK1: MR19=505, MR18=3214
5567 00:44:22.193323 CH0_RK1: MR19=0x505, MR18=0x3214, DQSOSC=406, MR23=63, INC=65, DEC=43
5568 00:44:22.193747 [RxdqsGatingPostProcess] freq 933
5569 00:44:22.199977 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5570 00:44:22.203574 best DQS0 dly(2T, 0.5T) = (0, 10)
5571 00:44:22.206713 best DQS1 dly(2T, 0.5T) = (0, 11)
5572 00:44:22.210199 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5573 00:44:22.213183 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5574 00:44:22.216427 best DQS0 dly(2T, 0.5T) = (0, 10)
5575 00:44:22.220095 best DQS1 dly(2T, 0.5T) = (0, 11)
5576 00:44:22.223667 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5577 00:44:22.226442 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5578 00:44:22.229752 Pre-setting of DQS Precalculation
5579 00:44:22.233177 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5580 00:44:22.233574 ==
5581 00:44:22.236460 Dram Type= 6, Freq= 0, CH_1, rank 0
5582 00:44:22.239997 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5583 00:44:22.243472 ==
5584 00:44:22.246893 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5585 00:44:22.253064 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5586 00:44:22.256498 [CA 0] Center 37 (7~67) winsize 61
5587 00:44:22.259895 [CA 1] Center 37 (7~68) winsize 62
5588 00:44:22.263463 [CA 2] Center 35 (5~65) winsize 61
5589 00:44:22.266273 [CA 3] Center 34 (4~65) winsize 62
5590 00:44:22.269798 [CA 4] Center 35 (5~65) winsize 61
5591 00:44:22.273224 [CA 5] Center 34 (4~64) winsize 61
5592 00:44:22.273956
5593 00:44:22.276092 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5594 00:44:22.276530
5595 00:44:22.279604 [CATrainingPosCal] consider 1 rank data
5596 00:44:22.283078 u2DelayCellTimex100 = 270/100 ps
5597 00:44:22.286604 CA0 delay=37 (7~67),Diff = 3 PI (18 cell)
5598 00:44:22.289419 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5599 00:44:22.292901 CA2 delay=35 (5~65),Diff = 1 PI (6 cell)
5600 00:44:22.296492 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5601 00:44:22.303051 CA4 delay=35 (5~65),Diff = 1 PI (6 cell)
5602 00:44:22.306319 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5603 00:44:22.306705
5604 00:44:22.309471 CA PerBit enable=1, Macro0, CA PI delay=34
5605 00:44:22.310297
5606 00:44:22.312593 [CBTSetCACLKResult] CA Dly = 34
5607 00:44:22.313007 CS Dly: 6 (0~37)
5608 00:44:22.313308 ==
5609 00:44:22.316070 Dram Type= 6, Freq= 0, CH_1, rank 1
5610 00:44:22.322975 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5611 00:44:22.323388 ==
5612 00:44:22.326340 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5613 00:44:22.333251 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5614 00:44:22.336338 [CA 0] Center 38 (8~68) winsize 61
5615 00:44:22.339541 [CA 1] Center 37 (7~68) winsize 62
5616 00:44:22.342394 [CA 2] Center 35 (5~65) winsize 61
5617 00:44:22.345773 [CA 3] Center 34 (4~64) winsize 61
5618 00:44:22.349201 [CA 4] Center 35 (5~65) winsize 61
5619 00:44:22.352519 [CA 5] Center 33 (3~64) winsize 62
5620 00:44:22.353013
5621 00:44:22.355751 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5622 00:44:22.356136
5623 00:44:22.359429 [CATrainingPosCal] consider 2 rank data
5624 00:44:22.362388 u2DelayCellTimex100 = 270/100 ps
5625 00:44:22.365768 CA0 delay=37 (8~67),Diff = 3 PI (18 cell)
5626 00:44:22.369286 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5627 00:44:22.376076 CA2 delay=35 (5~65),Diff = 1 PI (6 cell)
5628 00:44:22.379284 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
5629 00:44:22.382440 CA4 delay=35 (5~65),Diff = 1 PI (6 cell)
5630 00:44:22.385998 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5631 00:44:22.386398
5632 00:44:22.389367 CA PerBit enable=1, Macro0, CA PI delay=34
5633 00:44:22.389830
5634 00:44:22.392272 [CBTSetCACLKResult] CA Dly = 34
5635 00:44:22.392706 CS Dly: 7 (0~39)
5636 00:44:22.393147
5637 00:44:22.395847 ----->DramcWriteLeveling(PI) begin...
5638 00:44:22.399248 ==
5639 00:44:22.399666 Dram Type= 6, Freq= 0, CH_1, rank 0
5640 00:44:22.405814 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5641 00:44:22.406219 ==
5642 00:44:22.409207 Write leveling (Byte 0): 28 => 28
5643 00:44:22.412383 Write leveling (Byte 1): 29 => 29
5644 00:44:22.415938 DramcWriteLeveling(PI) end<-----
5645 00:44:22.416407
5646 00:44:22.416879 ==
5647 00:44:22.419274 Dram Type= 6, Freq= 0, CH_1, rank 0
5648 00:44:22.422254 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5649 00:44:22.422654 ==
5650 00:44:22.425495 [Gating] SW mode calibration
5651 00:44:22.432180 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5652 00:44:22.435564 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5653 00:44:22.442598 0 14 0 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
5654 00:44:22.445834 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5655 00:44:22.449237 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5656 00:44:22.455579 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5657 00:44:22.458843 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5658 00:44:22.462142 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5659 00:44:22.468778 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5660 00:44:22.472028 0 14 28 | B1->B0 | 2f2f 2e2e | 1 1 | (1 0) (1 0)
5661 00:44:22.475471 0 15 0 | B1->B0 | 2626 2626 | 0 0 | (0 0) (0 0)
5662 00:44:22.482126 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5663 00:44:22.485608 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5664 00:44:22.488952 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5665 00:44:22.495622 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5666 00:44:22.498355 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5667 00:44:22.502084 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5668 00:44:22.508509 0 15 28 | B1->B0 | 3535 3535 | 0 0 | (1 1) (1 1)
5669 00:44:22.511636 1 0 0 | B1->B0 | 4646 4343 | 0 0 | (0 0) (0 0)
5670 00:44:22.515134 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5671 00:44:22.522349 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5672 00:44:22.525101 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5673 00:44:22.528699 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5674 00:44:22.534820 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5675 00:44:22.538167 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5676 00:44:22.541679 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5677 00:44:22.548186 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5678 00:44:22.551705 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5679 00:44:22.555140 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5680 00:44:22.561456 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5681 00:44:22.564803 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5682 00:44:22.568445 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5683 00:44:22.575157 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5684 00:44:22.578061 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5685 00:44:22.581489 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5686 00:44:22.588013 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5687 00:44:22.591603 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5688 00:44:22.594807 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5689 00:44:22.601557 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5690 00:44:22.604786 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5691 00:44:22.607998 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5692 00:44:22.614655 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5693 00:44:22.618066 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5694 00:44:22.621350 Total UI for P1: 0, mck2ui 16
5695 00:44:22.624385 best dqsien dly found for B0: ( 1, 2, 28)
5696 00:44:22.627796 Total UI for P1: 0, mck2ui 16
5697 00:44:22.631426 best dqsien dly found for B1: ( 1, 2, 28)
5698 00:44:22.634434 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5699 00:44:22.637535 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5700 00:44:22.637960
5701 00:44:22.641031 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5702 00:44:22.644763 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5703 00:44:22.647764 [Gating] SW calibration Done
5704 00:44:22.648192 ==
5705 00:44:22.651082 Dram Type= 6, Freq= 0, CH_1, rank 0
5706 00:44:22.654675 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5707 00:44:22.655366 ==
5708 00:44:22.657484 RX Vref Scan: 0
5709 00:44:22.657914
5710 00:44:22.660779 RX Vref 0 -> 0, step: 1
5711 00:44:22.661207
5712 00:44:22.661540 RX Delay -80 -> 252, step: 8
5713 00:44:22.667742 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5714 00:44:22.670939 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5715 00:44:22.674670 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5716 00:44:22.677365 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5717 00:44:22.680763 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5718 00:44:22.687633 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5719 00:44:22.690904 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5720 00:44:22.693985 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5721 00:44:22.697150 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5722 00:44:22.701065 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5723 00:44:22.704046 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5724 00:44:22.710797 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5725 00:44:22.713987 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5726 00:44:22.717385 iDelay=208, Bit 13, Center 95 (-8 ~ 199) 208
5727 00:44:22.720752 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5728 00:44:22.723753 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5729 00:44:22.727208 ==
5730 00:44:22.730866 Dram Type= 6, Freq= 0, CH_1, rank 0
5731 00:44:22.734134 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5732 00:44:22.734643 ==
5733 00:44:22.734978 DQS Delay:
5734 00:44:22.736818 DQS0 = 0, DQS1 = 0
5735 00:44:22.737252 DQM Delay:
5736 00:44:22.740566 DQM0 = 94, DQM1 = 87
5737 00:44:22.741126 DQ Delay:
5738 00:44:22.744011 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =91
5739 00:44:22.747724 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =91
5740 00:44:22.750321 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =83
5741 00:44:22.753675 DQ12 =91, DQ13 =95, DQ14 =91, DQ15 =91
5742 00:44:22.754102
5743 00:44:22.754430
5744 00:44:22.754736 ==
5745 00:44:22.757217 Dram Type= 6, Freq= 0, CH_1, rank 0
5746 00:44:22.760472 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5747 00:44:22.760950 ==
5748 00:44:22.761286
5749 00:44:22.761631
5750 00:44:22.763595 TX Vref Scan disable
5751 00:44:22.766978 == TX Byte 0 ==
5752 00:44:22.770354 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5753 00:44:22.773466 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5754 00:44:22.777287 == TX Byte 1 ==
5755 00:44:22.780442 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5756 00:44:22.784007 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5757 00:44:22.784532 ==
5758 00:44:22.786905 Dram Type= 6, Freq= 0, CH_1, rank 0
5759 00:44:22.793439 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5760 00:44:22.793940 ==
5761 00:44:22.794275
5762 00:44:22.794579
5763 00:44:22.794872 TX Vref Scan disable
5764 00:44:22.797362 == TX Byte 0 ==
5765 00:44:22.800445 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5766 00:44:22.807165 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5767 00:44:22.807591 == TX Byte 1 ==
5768 00:44:22.810703 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5769 00:44:22.814023 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5770 00:44:22.817126
5771 00:44:22.817567 [DATLAT]
5772 00:44:22.817905 Freq=933, CH1 RK0
5773 00:44:22.818220
5774 00:44:22.820556 DATLAT Default: 0xd
5775 00:44:22.821016 0, 0xFFFF, sum = 0
5776 00:44:22.824084 1, 0xFFFF, sum = 0
5777 00:44:22.824522 2, 0xFFFF, sum = 0
5778 00:44:22.827014 3, 0xFFFF, sum = 0
5779 00:44:22.827444 4, 0xFFFF, sum = 0
5780 00:44:22.830490 5, 0xFFFF, sum = 0
5781 00:44:22.833961 6, 0xFFFF, sum = 0
5782 00:44:22.834555 7, 0xFFFF, sum = 0
5783 00:44:22.837233 8, 0xFFFF, sum = 0
5784 00:44:22.837671 9, 0xFFFF, sum = 0
5785 00:44:22.840517 10, 0x0, sum = 1
5786 00:44:22.841083 11, 0x0, sum = 2
5787 00:44:22.843734 12, 0x0, sum = 3
5788 00:44:22.844172 13, 0x0, sum = 4
5789 00:44:22.844516 best_step = 11
5790 00:44:22.844898
5791 00:44:22.846789 ==
5792 00:44:22.850616 Dram Type= 6, Freq= 0, CH_1, rank 0
5793 00:44:22.853815 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5794 00:44:22.854288 ==
5795 00:44:22.854777 RX Vref Scan: 1
5796 00:44:22.855145
5797 00:44:22.856955 RX Vref 0 -> 0, step: 1
5798 00:44:22.857380
5799 00:44:22.860736 RX Delay -61 -> 252, step: 4
5800 00:44:22.861246
5801 00:44:22.863852 Set Vref, RX VrefLevel [Byte0]: 57
5802 00:44:22.867154 [Byte1]: 53
5803 00:44:22.867580
5804 00:44:22.870297 Final RX Vref Byte 0 = 57 to rank0
5805 00:44:22.873520 Final RX Vref Byte 1 = 53 to rank0
5806 00:44:22.876601 Final RX Vref Byte 0 = 57 to rank1
5807 00:44:22.880187 Final RX Vref Byte 1 = 53 to rank1==
5808 00:44:22.883581 Dram Type= 6, Freq= 0, CH_1, rank 0
5809 00:44:22.886563 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5810 00:44:22.889961 ==
5811 00:44:22.890432 DQS Delay:
5812 00:44:22.890734 DQS0 = 0, DQS1 = 0
5813 00:44:22.893359 DQM Delay:
5814 00:44:22.893741 DQM0 = 96, DQM1 = 88
5815 00:44:22.896800 DQ Delay:
5816 00:44:22.900359 DQ0 =102, DQ1 =92, DQ2 =84, DQ3 =94
5817 00:44:22.903670 DQ4 =94, DQ5 =106, DQ6 =108, DQ7 =94
5818 00:44:22.904062 DQ8 =78, DQ9 =80, DQ10 =88, DQ11 =82
5819 00:44:22.910103 DQ12 =100, DQ13 =94, DQ14 =94, DQ15 =94
5820 00:44:22.910488
5821 00:44:22.910787
5822 00:44:22.917032 [DQSOSCAuto] RK0, (LSB)MR18= 0x30b, (MSB)MR19= 0x505, tDQSOscB0 = 418 ps tDQSOscB1 = 421 ps
5823 00:44:22.919963 CH1 RK0: MR19=505, MR18=30B
5824 00:44:22.926628 CH1_RK0: MR19=0x505, MR18=0x30B, DQSOSC=418, MR23=63, INC=62, DEC=41
5825 00:44:22.927152
5826 00:44:22.929907 ----->DramcWriteLeveling(PI) begin...
5827 00:44:22.930420 ==
5828 00:44:22.933231 Dram Type= 6, Freq= 0, CH_1, rank 1
5829 00:44:22.936719 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5830 00:44:22.937229 ==
5831 00:44:22.939671 Write leveling (Byte 0): 25 => 25
5832 00:44:22.942987 Write leveling (Byte 1): 28 => 28
5833 00:44:22.946536 DramcWriteLeveling(PI) end<-----
5834 00:44:22.947045
5835 00:44:22.947382 ==
5836 00:44:22.949550 Dram Type= 6, Freq= 0, CH_1, rank 1
5837 00:44:22.953280 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5838 00:44:22.953792 ==
5839 00:44:22.956158 [Gating] SW mode calibration
5840 00:44:22.963090 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5841 00:44:22.969495 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5842 00:44:22.972812 0 14 0 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
5843 00:44:22.979388 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5844 00:44:22.982813 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5845 00:44:22.986052 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5846 00:44:22.992512 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5847 00:44:22.995801 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5848 00:44:22.999180 0 14 24 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 1)
5849 00:44:23.005440 0 14 28 | B1->B0 | 2828 2323 | 0 0 | (0 0) (1 0)
5850 00:44:23.009021 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5851 00:44:23.012221 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5852 00:44:23.018797 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5853 00:44:23.021895 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5854 00:44:23.025317 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5855 00:44:23.031916 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5856 00:44:23.035326 0 15 24 | B1->B0 | 2626 3535 | 0 0 | (0 0) (1 1)
5857 00:44:23.038690 0 15 28 | B1->B0 | 3d3d 4646 | 0 0 | (1 1) (0 0)
5858 00:44:23.045638 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5859 00:44:23.049270 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5860 00:44:23.052356 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5861 00:44:23.055051 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5862 00:44:23.061735 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5863 00:44:23.065142 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5864 00:44:23.068720 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5865 00:44:23.075470 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5866 00:44:23.078101 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5867 00:44:23.081357 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5868 00:44:23.088226 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5869 00:44:23.091736 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5870 00:44:23.095207 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5871 00:44:23.101522 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5872 00:44:23.104765 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5873 00:44:23.108178 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5874 00:44:23.115105 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5875 00:44:23.117968 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5876 00:44:23.121215 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5877 00:44:23.127810 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5878 00:44:23.131519 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5879 00:44:23.134419 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5880 00:44:23.141234 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5881 00:44:23.144596 Total UI for P1: 0, mck2ui 16
5882 00:44:23.147935 best dqsien dly found for B0: ( 1, 2, 22)
5883 00:44:23.151208 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5884 00:44:23.154731 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5885 00:44:23.157647 Total UI for P1: 0, mck2ui 16
5886 00:44:23.161169 best dqsien dly found for B1: ( 1, 2, 26)
5887 00:44:23.164381 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5888 00:44:23.167844 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5889 00:44:23.168256
5890 00:44:23.174303 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5891 00:44:23.177782 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5892 00:44:23.181065 [Gating] SW calibration Done
5893 00:44:23.181524 ==
5894 00:44:23.184070 Dram Type= 6, Freq= 0, CH_1, rank 1
5895 00:44:23.187552 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5896 00:44:23.187942 ==
5897 00:44:23.188242 RX Vref Scan: 0
5898 00:44:23.188523
5899 00:44:23.190891 RX Vref 0 -> 0, step: 1
5900 00:44:23.191274
5901 00:44:23.194265 RX Delay -80 -> 252, step: 8
5902 00:44:23.197814 iDelay=208, Bit 0, Center 95 (-8 ~ 199) 208
5903 00:44:23.201151 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5904 00:44:23.208049 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5905 00:44:23.210998 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5906 00:44:23.213966 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5907 00:44:23.217333 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5908 00:44:23.220956 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5909 00:44:23.223868 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5910 00:44:23.231017 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5911 00:44:23.234248 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5912 00:44:23.237391 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5913 00:44:23.240291 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5914 00:44:23.243888 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5915 00:44:23.250346 iDelay=208, Bit 13, Center 95 (-8 ~ 199) 208
5916 00:44:23.253435 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5917 00:44:23.256882 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5918 00:44:23.257269 ==
5919 00:44:23.260329 Dram Type= 6, Freq= 0, CH_1, rank 1
5920 00:44:23.263942 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5921 00:44:23.264330 ==
5922 00:44:23.267270 DQS Delay:
5923 00:44:23.267652 DQS0 = 0, DQS1 = 0
5924 00:44:23.270532 DQM Delay:
5925 00:44:23.270917 DQM0 = 93, DQM1 = 88
5926 00:44:23.271216 DQ Delay:
5927 00:44:23.273434 DQ0 =95, DQ1 =91, DQ2 =83, DQ3 =91
5928 00:44:23.276999 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =91
5929 00:44:23.280458 DQ8 =75, DQ9 =75, DQ10 =91, DQ11 =83
5930 00:44:23.283858 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5931 00:44:23.284245
5932 00:44:23.284542
5933 00:44:23.287326 ==
5934 00:44:23.287710 Dram Type= 6, Freq= 0, CH_1, rank 1
5935 00:44:23.293435 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5936 00:44:23.293824 ==
5937 00:44:23.294124
5938 00:44:23.294397
5939 00:44:23.296922 TX Vref Scan disable
5940 00:44:23.297306 == TX Byte 0 ==
5941 00:44:23.300337 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5942 00:44:23.306721 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5943 00:44:23.307177 == TX Byte 1 ==
5944 00:44:23.313158 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5945 00:44:23.316339 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5946 00:44:23.316780 ==
5947 00:44:23.319287 Dram Type= 6, Freq= 0, CH_1, rank 1
5948 00:44:23.323434 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5949 00:44:23.323928 ==
5950 00:44:23.324242
5951 00:44:23.324516
5952 00:44:23.326386 TX Vref Scan disable
5953 00:44:23.329763 == TX Byte 0 ==
5954 00:44:23.333220 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5955 00:44:23.336843 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5956 00:44:23.340118 == TX Byte 1 ==
5957 00:44:23.343038 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5958 00:44:23.346422 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5959 00:44:23.346807
5960 00:44:23.349869 [DATLAT]
5961 00:44:23.350400 Freq=933, CH1 RK1
5962 00:44:23.350775
5963 00:44:23.352791 DATLAT Default: 0xb
5964 00:44:23.353176 0, 0xFFFF, sum = 0
5965 00:44:23.356056 1, 0xFFFF, sum = 0
5966 00:44:23.356447 2, 0xFFFF, sum = 0
5967 00:44:23.359890 3, 0xFFFF, sum = 0
5968 00:44:23.360281 4, 0xFFFF, sum = 0
5969 00:44:23.363061 5, 0xFFFF, sum = 0
5970 00:44:23.363488 6, 0xFFFF, sum = 0
5971 00:44:23.366246 7, 0xFFFF, sum = 0
5972 00:44:23.366690 8, 0xFFFF, sum = 0
5973 00:44:23.369574 9, 0xFFFF, sum = 0
5974 00:44:23.369962 10, 0x0, sum = 1
5975 00:44:23.373497 11, 0x0, sum = 2
5976 00:44:23.373893 12, 0x0, sum = 3
5977 00:44:23.377039 13, 0x0, sum = 4
5978 00:44:23.377510 best_step = 11
5979 00:44:23.377810
5980 00:44:23.378084 ==
5981 00:44:23.379596 Dram Type= 6, Freq= 0, CH_1, rank 1
5982 00:44:23.382884 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5983 00:44:23.386460 ==
5984 00:44:23.386844 RX Vref Scan: 0
5985 00:44:23.387142
5986 00:44:23.389811 RX Vref 0 -> 0, step: 1
5987 00:44:23.390195
5988 00:44:23.392531 RX Delay -69 -> 252, step: 4
5989 00:44:23.396195 iDelay=203, Bit 0, Center 96 (-1 ~ 194) 196
5990 00:44:23.399372 iDelay=203, Bit 1, Center 86 (-9 ~ 182) 192
5991 00:44:23.406388 iDelay=203, Bit 2, Center 82 (-13 ~ 178) 192
5992 00:44:23.409039 iDelay=203, Bit 3, Center 88 (-9 ~ 186) 196
5993 00:44:23.412772 iDelay=203, Bit 4, Center 88 (-9 ~ 186) 196
5994 00:44:23.415871 iDelay=203, Bit 5, Center 102 (3 ~ 202) 200
5995 00:44:23.419243 iDelay=203, Bit 6, Center 104 (7 ~ 202) 196
5996 00:44:23.422513 iDelay=203, Bit 7, Center 88 (-9 ~ 186) 196
5997 00:44:23.429562 iDelay=203, Bit 8, Center 80 (-9 ~ 170) 180
5998 00:44:23.432282 iDelay=203, Bit 9, Center 82 (-9 ~ 174) 184
5999 00:44:23.435616 iDelay=203, Bit 10, Center 92 (-1 ~ 186) 188
6000 00:44:23.439149 iDelay=203, Bit 11, Center 84 (-9 ~ 178) 188
6001 00:44:23.442559 iDelay=203, Bit 12, Center 98 (7 ~ 190) 184
6002 00:44:23.448713 iDelay=203, Bit 13, Center 96 (3 ~ 190) 188
6003 00:44:23.452210 iDelay=203, Bit 14, Center 96 (3 ~ 190) 188
6004 00:44:23.455645 iDelay=203, Bit 15, Center 96 (3 ~ 190) 188
6005 00:44:23.456046 ==
6006 00:44:23.459408 Dram Type= 6, Freq= 0, CH_1, rank 1
6007 00:44:23.462036 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
6008 00:44:23.462461 ==
6009 00:44:23.465420 DQS Delay:
6010 00:44:23.465821 DQS0 = 0, DQS1 = 0
6011 00:44:23.466213 DQM Delay:
6012 00:44:23.468677 DQM0 = 91, DQM1 = 90
6013 00:44:23.469073 DQ Delay:
6014 00:44:23.471817 DQ0 =96, DQ1 =86, DQ2 =82, DQ3 =88
6015 00:44:23.475344 DQ4 =88, DQ5 =102, DQ6 =104, DQ7 =88
6016 00:44:23.478670 DQ8 =80, DQ9 =82, DQ10 =92, DQ11 =84
6017 00:44:23.482035 DQ12 =98, DQ13 =96, DQ14 =96, DQ15 =96
6018 00:44:23.482417
6019 00:44:23.482733
6020 00:44:23.491883 [DQSOSCAuto] RK1, (LSB)MR18= 0x1529, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 415 ps
6021 00:44:23.495587 CH1 RK1: MR19=505, MR18=1529
6022 00:44:23.498714 CH1_RK1: MR19=0x505, MR18=0x1529, DQSOSC=408, MR23=63, INC=65, DEC=43
6023 00:44:23.501669 [RxdqsGatingPostProcess] freq 933
6024 00:44:23.508456 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6025 00:44:23.512026 best DQS0 dly(2T, 0.5T) = (0, 10)
6026 00:44:23.515319 best DQS1 dly(2T, 0.5T) = (0, 10)
6027 00:44:23.518099 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6028 00:44:23.521967 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6029 00:44:23.525419 best DQS0 dly(2T, 0.5T) = (0, 10)
6030 00:44:23.528606 best DQS1 dly(2T, 0.5T) = (0, 10)
6031 00:44:23.531727 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6032 00:44:23.535041 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6033 00:44:23.538593 Pre-setting of DQS Precalculation
6034 00:44:23.542048 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6035 00:44:23.548198 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6036 00:44:23.555040 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6037 00:44:23.555430
6038 00:44:23.558455
6039 00:44:23.558839 [Calibration Summary] 1866 Mbps
6040 00:44:23.561905 CH 0, Rank 0
6041 00:44:23.562287 SW Impedance : PASS
6042 00:44:23.564819 DUTY Scan : NO K
6043 00:44:23.568364 ZQ Calibration : PASS
6044 00:44:23.568777 Jitter Meter : NO K
6045 00:44:23.571319 CBT Training : PASS
6046 00:44:23.575149 Write leveling : PASS
6047 00:44:23.575535 RX DQS gating : PASS
6048 00:44:23.578223 RX DQ/DQS(RDDQC) : PASS
6049 00:44:23.581237 TX DQ/DQS : PASS
6050 00:44:23.581712 RX DATLAT : PASS
6051 00:44:23.584562 RX DQ/DQS(Engine): PASS
6052 00:44:23.588103 TX OE : NO K
6053 00:44:23.588492 All Pass.
6054 00:44:23.588842
6055 00:44:23.589125 CH 0, Rank 1
6056 00:44:23.591523 SW Impedance : PASS
6057 00:44:23.594880 DUTY Scan : NO K
6058 00:44:23.595262 ZQ Calibration : PASS
6059 00:44:23.597905 Jitter Meter : NO K
6060 00:44:23.598292 CBT Training : PASS
6061 00:44:23.601233 Write leveling : PASS
6062 00:44:23.604929 RX DQS gating : PASS
6063 00:44:23.605318 RX DQ/DQS(RDDQC) : PASS
6064 00:44:23.607831 TX DQ/DQS : PASS
6065 00:44:23.611459 RX DATLAT : PASS
6066 00:44:23.611968 RX DQ/DQS(Engine): PASS
6067 00:44:23.614716 TX OE : NO K
6068 00:44:23.615103 All Pass.
6069 00:44:23.615443
6070 00:44:23.617766 CH 1, Rank 0
6071 00:44:23.618151 SW Impedance : PASS
6072 00:44:23.621104 DUTY Scan : NO K
6073 00:44:23.624533 ZQ Calibration : PASS
6074 00:44:23.624975 Jitter Meter : NO K
6075 00:44:23.627953 CBT Training : PASS
6076 00:44:23.631423 Write leveling : PASS
6077 00:44:23.631811 RX DQS gating : PASS
6078 00:44:23.634294 RX DQ/DQS(RDDQC) : PASS
6079 00:44:23.637870 TX DQ/DQS : PASS
6080 00:44:23.638259 RX DATLAT : PASS
6081 00:44:23.640982 RX DQ/DQS(Engine): PASS
6082 00:44:23.644488 TX OE : NO K
6083 00:44:23.644940 All Pass.
6084 00:44:23.645284
6085 00:44:23.645583 CH 1, Rank 1
6086 00:44:23.647472 SW Impedance : PASS
6087 00:44:23.650740 DUTY Scan : NO K
6088 00:44:23.651212 ZQ Calibration : PASS
6089 00:44:23.654355 Jitter Meter : NO K
6090 00:44:23.657393 CBT Training : PASS
6091 00:44:23.657780 Write leveling : PASS
6092 00:44:23.660769 RX DQS gating : PASS
6093 00:44:23.661187 RX DQ/DQS(RDDQC) : PASS
6094 00:44:23.664539 TX DQ/DQS : PASS
6095 00:44:23.667378 RX DATLAT : PASS
6096 00:44:23.667764 RX DQ/DQS(Engine): PASS
6097 00:44:23.670737 TX OE : NO K
6098 00:44:23.671125 All Pass.
6099 00:44:23.671483
6100 00:44:23.674490 DramC Write-DBI off
6101 00:44:23.678139 PER_BANK_REFRESH: Hybrid Mode
6102 00:44:23.678709 TX_TRACKING: ON
6103 00:44:23.687544 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6104 00:44:23.691070 [FAST_K] Save calibration result to emmc
6105 00:44:23.694174 dramc_set_vcore_voltage set vcore to 650000
6106 00:44:23.697568 Read voltage for 400, 6
6107 00:44:23.698084 Vio18 = 0
6108 00:44:23.698395 Vcore = 650000
6109 00:44:23.700716 Vdram = 0
6110 00:44:23.701117 Vddq = 0
6111 00:44:23.701495 Vmddr = 0
6112 00:44:23.707260 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6113 00:44:23.710811 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6114 00:44:23.714258 MEM_TYPE=3, freq_sel=20
6115 00:44:23.717262 sv_algorithm_assistance_LP4_800
6116 00:44:23.720521 ============ PULL DRAM RESETB DOWN ============
6117 00:44:23.726961 ========== PULL DRAM RESETB DOWN end =========
6118 00:44:23.730628 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6119 00:44:23.733836 ===================================
6120 00:44:23.737295 LPDDR4 DRAM CONFIGURATION
6121 00:44:23.740268 ===================================
6122 00:44:23.740801 EX_ROW_EN[0] = 0x0
6123 00:44:23.744067 EX_ROW_EN[1] = 0x0
6124 00:44:23.744454 LP4Y_EN = 0x0
6125 00:44:23.747395 WORK_FSP = 0x0
6126 00:44:23.747813 WL = 0x2
6127 00:44:23.750144 RL = 0x2
6128 00:44:23.750571 BL = 0x2
6129 00:44:23.753808 RPST = 0x0
6130 00:44:23.754224 RD_PRE = 0x0
6131 00:44:23.756784 WR_PRE = 0x1
6132 00:44:23.757173 WR_PST = 0x0
6133 00:44:23.760566 DBI_WR = 0x0
6134 00:44:23.763330 DBI_RD = 0x0
6135 00:44:23.763715 OTF = 0x1
6136 00:44:23.767138 ===================================
6137 00:44:23.770145 ===================================
6138 00:44:23.770535 ANA top config
6139 00:44:23.773417 ===================================
6140 00:44:23.777125 DLL_ASYNC_EN = 0
6141 00:44:23.779995 ALL_SLAVE_EN = 1
6142 00:44:23.783721 NEW_RANK_MODE = 1
6143 00:44:23.786809 DLL_IDLE_MODE = 1
6144 00:44:23.787299 LP45_APHY_COMB_EN = 1
6145 00:44:23.790294 TX_ODT_DIS = 1
6146 00:44:23.793537 NEW_8X_MODE = 1
6147 00:44:23.796956 ===================================
6148 00:44:23.799768 ===================================
6149 00:44:23.803218 data_rate = 800
6150 00:44:23.806690 CKR = 1
6151 00:44:23.807182 DQ_P2S_RATIO = 4
6152 00:44:23.810184 ===================================
6153 00:44:23.813627 CA_P2S_RATIO = 4
6154 00:44:23.816790 DQ_CA_OPEN = 0
6155 00:44:23.819885 DQ_SEMI_OPEN = 1
6156 00:44:23.823251 CA_SEMI_OPEN = 1
6157 00:44:23.826636 CA_FULL_RATE = 0
6158 00:44:23.827027 DQ_CKDIV4_EN = 0
6159 00:44:23.829817 CA_CKDIV4_EN = 1
6160 00:44:23.833175 CA_PREDIV_EN = 0
6161 00:44:23.836734 PH8_DLY = 0
6162 00:44:23.839830 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6163 00:44:23.842998 DQ_AAMCK_DIV = 0
6164 00:44:23.843388 CA_AAMCK_DIV = 0
6165 00:44:23.846844 CA_ADMCK_DIV = 4
6166 00:44:23.849893 DQ_TRACK_CA_EN = 0
6167 00:44:23.853037 CA_PICK = 800
6168 00:44:23.856875 CA_MCKIO = 400
6169 00:44:23.859725 MCKIO_SEMI = 400
6170 00:44:23.862898 PLL_FREQ = 3016
6171 00:44:23.866446 DQ_UI_PI_RATIO = 32
6172 00:44:23.867039 CA_UI_PI_RATIO = 32
6173 00:44:23.869370 ===================================
6174 00:44:23.872620 ===================================
6175 00:44:23.876395 memory_type:LPDDR4
6176 00:44:23.879592 GP_NUM : 10
6177 00:44:23.880181 SRAM_EN : 1
6178 00:44:23.882804 MD32_EN : 0
6179 00:44:23.886059 ===================================
6180 00:44:23.889252 [ANA_INIT] >>>>>>>>>>>>>>
6181 00:44:23.892541 <<<<<< [CONFIGURE PHASE]: ANA_TX
6182 00:44:23.896041 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6183 00:44:23.899402 ===================================
6184 00:44:23.899894 data_rate = 800,PCW = 0X7400
6185 00:44:23.902574 ===================================
6186 00:44:23.905776 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6187 00:44:23.912414 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6188 00:44:23.922741 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6189 00:44:23.929006 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6190 00:44:23.932487 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6191 00:44:23.935838 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6192 00:44:23.939377 [ANA_INIT] flow start
6193 00:44:23.939762 [ANA_INIT] PLL >>>>>>>>
6194 00:44:23.942384 [ANA_INIT] PLL <<<<<<<<
6195 00:44:23.946129 [ANA_INIT] MIDPI >>>>>>>>
6196 00:44:23.946514 [ANA_INIT] MIDPI <<<<<<<<
6197 00:44:23.949057 [ANA_INIT] DLL >>>>>>>>
6198 00:44:23.952322 [ANA_INIT] flow end
6199 00:44:23.955753 ============ LP4 DIFF to SE enter ============
6200 00:44:23.959482 ============ LP4 DIFF to SE exit ============
6201 00:44:23.962797 [ANA_INIT] <<<<<<<<<<<<<
6202 00:44:23.966080 [Flow] Enable top DCM control >>>>>
6203 00:44:23.969485 [Flow] Enable top DCM control <<<<<
6204 00:44:23.972331 Enable DLL master slave shuffle
6205 00:44:23.975556 ==============================================================
6206 00:44:23.979056 Gating Mode config
6207 00:44:23.985917 ==============================================================
6208 00:44:23.986320 Config description:
6209 00:44:23.995887 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6210 00:44:24.002769 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6211 00:44:24.005610 SELPH_MODE 0: By rank 1: By Phase
6212 00:44:24.012307 ==============================================================
6213 00:44:24.015349 GAT_TRACK_EN = 0
6214 00:44:24.018940 RX_GATING_MODE = 2
6215 00:44:24.022230 RX_GATING_TRACK_MODE = 2
6216 00:44:24.025680 SELPH_MODE = 1
6217 00:44:24.028470 PICG_EARLY_EN = 1
6218 00:44:24.031919 VALID_LAT_VALUE = 1
6219 00:44:24.035459 ==============================================================
6220 00:44:24.038964 Enter into Gating configuration >>>>
6221 00:44:24.042280 Exit from Gating configuration <<<<
6222 00:44:24.045605 Enter into DVFS_PRE_config >>>>>
6223 00:44:24.058650 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6224 00:44:24.059125 Exit from DVFS_PRE_config <<<<<
6225 00:44:24.062267 Enter into PICG configuration >>>>
6226 00:44:24.065327 Exit from PICG configuration <<<<
6227 00:44:24.068209 [RX_INPUT] configuration >>>>>
6228 00:44:24.071655 [RX_INPUT] configuration <<<<<
6229 00:44:24.078819 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6230 00:44:24.082074 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6231 00:44:24.088352 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6232 00:44:24.095017 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6233 00:44:24.101593 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6234 00:44:24.107954 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6235 00:44:24.111275 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6236 00:44:24.114554 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6237 00:44:24.117817 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6238 00:44:24.124969 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6239 00:44:24.128440 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6240 00:44:24.131348 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6241 00:44:24.134820 ===================================
6242 00:44:24.137993 LPDDR4 DRAM CONFIGURATION
6243 00:44:24.141570 ===================================
6244 00:44:24.141975 EX_ROW_EN[0] = 0x0
6245 00:44:24.145117 EX_ROW_EN[1] = 0x0
6246 00:44:24.148411 LP4Y_EN = 0x0
6247 00:44:24.148843 WORK_FSP = 0x0
6248 00:44:24.151442 WL = 0x2
6249 00:44:24.151846 RL = 0x2
6250 00:44:24.154815 BL = 0x2
6251 00:44:24.155220 RPST = 0x0
6252 00:44:24.157976 RD_PRE = 0x0
6253 00:44:24.158380 WR_PRE = 0x1
6254 00:44:24.161245 WR_PST = 0x0
6255 00:44:24.161647 DBI_WR = 0x0
6256 00:44:24.164621 DBI_RD = 0x0
6257 00:44:24.165063 OTF = 0x1
6258 00:44:24.167810 ===================================
6259 00:44:24.171301 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6260 00:44:24.178445 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6261 00:44:24.181790 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6262 00:44:24.184515 ===================================
6263 00:44:24.188232 LPDDR4 DRAM CONFIGURATION
6264 00:44:24.191519 ===================================
6265 00:44:24.192057 EX_ROW_EN[0] = 0x10
6266 00:44:24.195504 EX_ROW_EN[1] = 0x0
6267 00:44:24.196033 LP4Y_EN = 0x0
6268 00:44:24.198267 WORK_FSP = 0x0
6269 00:44:24.201086 WL = 0x2
6270 00:44:24.201664 RL = 0x2
6271 00:44:24.204449 BL = 0x2
6272 00:44:24.205066 RPST = 0x0
6273 00:44:24.208098 RD_PRE = 0x0
6274 00:44:24.208622 WR_PRE = 0x1
6275 00:44:24.211438 WR_PST = 0x0
6276 00:44:24.211865 DBI_WR = 0x0
6277 00:44:24.214904 DBI_RD = 0x0
6278 00:44:24.215422 OTF = 0x1
6279 00:44:24.218081 ===================================
6280 00:44:24.224543 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6281 00:44:24.228450 nWR fixed to 30
6282 00:44:24.231866 [ModeRegInit_LP4] CH0 RK0
6283 00:44:24.232295 [ModeRegInit_LP4] CH0 RK1
6284 00:44:24.235454 [ModeRegInit_LP4] CH1 RK0
6285 00:44:24.238631 [ModeRegInit_LP4] CH1 RK1
6286 00:44:24.239063 match AC timing 19
6287 00:44:24.244990 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6288 00:44:24.248677 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6289 00:44:24.251705 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6290 00:44:24.258653 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6291 00:44:24.261830 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6292 00:44:24.261932 ==
6293 00:44:24.265095 Dram Type= 6, Freq= 0, CH_0, rank 0
6294 00:44:24.268166 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6295 00:44:24.268244 ==
6296 00:44:24.274632 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6297 00:44:24.281881 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6298 00:44:24.284978 [CA 0] Center 36 (8~64) winsize 57
6299 00:44:24.288277 [CA 1] Center 36 (8~64) winsize 57
6300 00:44:24.291181 [CA 2] Center 36 (8~64) winsize 57
6301 00:44:24.291288 [CA 3] Center 36 (8~64) winsize 57
6302 00:44:24.294733 [CA 4] Center 36 (8~64) winsize 57
6303 00:44:24.298059 [CA 5] Center 36 (8~64) winsize 57
6304 00:44:24.298153
6305 00:44:24.301319 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6306 00:44:24.304948
6307 00:44:24.307970 [CATrainingPosCal] consider 1 rank data
6308 00:44:24.308087 u2DelayCellTimex100 = 270/100 ps
6309 00:44:24.314747 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6310 00:44:24.318186 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6311 00:44:24.321604 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6312 00:44:24.324904 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6313 00:44:24.328437 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6314 00:44:24.331703 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6315 00:44:24.332169
6316 00:44:24.334814 CA PerBit enable=1, Macro0, CA PI delay=36
6317 00:44:24.335242
6318 00:44:24.338737 [CBTSetCACLKResult] CA Dly = 36
6319 00:44:24.341657 CS Dly: 1 (0~32)
6320 00:44:24.342093 ==
6321 00:44:24.344686 Dram Type= 6, Freq= 0, CH_0, rank 1
6322 00:44:24.348290 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6323 00:44:24.348847 ==
6324 00:44:24.355371 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6325 00:44:24.357998 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6326 00:44:24.361397 [CA 0] Center 36 (8~64) winsize 57
6327 00:44:24.364810 [CA 1] Center 36 (8~64) winsize 57
6328 00:44:24.368271 [CA 2] Center 36 (8~64) winsize 57
6329 00:44:24.371328 [CA 3] Center 36 (8~64) winsize 57
6330 00:44:24.374455 [CA 4] Center 36 (8~64) winsize 57
6331 00:44:24.377737 [CA 5] Center 36 (8~64) winsize 57
6332 00:44:24.378167
6333 00:44:24.381252 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6334 00:44:24.381679
6335 00:44:24.384706 [CATrainingPosCal] consider 2 rank data
6336 00:44:24.388091 u2DelayCellTimex100 = 270/100 ps
6337 00:44:24.391438 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6338 00:44:24.394286 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6339 00:44:24.401005 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6340 00:44:24.404266 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6341 00:44:24.407933 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6342 00:44:24.411097 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6343 00:44:24.411665
6344 00:44:24.414306 CA PerBit enable=1, Macro0, CA PI delay=36
6345 00:44:24.414796
6346 00:44:24.417909 [CBTSetCACLKResult] CA Dly = 36
6347 00:44:24.418414 CS Dly: 1 (0~32)
6348 00:44:24.418855
6349 00:44:24.424305 ----->DramcWriteLeveling(PI) begin...
6350 00:44:24.424905 ==
6351 00:44:24.427351 Dram Type= 6, Freq= 0, CH_0, rank 0
6352 00:44:24.430807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6353 00:44:24.431287 ==
6354 00:44:24.433953 Write leveling (Byte 0): 40 => 8
6355 00:44:24.437379 Write leveling (Byte 1): 40 => 8
6356 00:44:24.440721 DramcWriteLeveling(PI) end<-----
6357 00:44:24.441158
6358 00:44:24.441490 ==
6359 00:44:24.443988 Dram Type= 6, Freq= 0, CH_0, rank 0
6360 00:44:24.447201 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6361 00:44:24.447586 ==
6362 00:44:24.451103 [Gating] SW mode calibration
6363 00:44:24.457335 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6364 00:44:24.463782 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6365 00:44:24.467134 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6366 00:44:24.470052 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6367 00:44:24.476867 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6368 00:44:24.480269 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6369 00:44:24.483091 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6370 00:44:24.489780 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6371 00:44:24.493508 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6372 00:44:24.496916 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6373 00:44:24.503501 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6374 00:44:24.503896 Total UI for P1: 0, mck2ui 16
6375 00:44:24.510035 best dqsien dly found for B0: ( 0, 14, 24)
6376 00:44:24.510452 Total UI for P1: 0, mck2ui 16
6377 00:44:24.513272 best dqsien dly found for B1: ( 0, 14, 24)
6378 00:44:24.519880 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6379 00:44:24.523164 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6380 00:44:24.523689
6381 00:44:24.526544 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6382 00:44:24.529973 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6383 00:44:24.533425 [Gating] SW calibration Done
6384 00:44:24.533849 ==
6385 00:44:24.536263 Dram Type= 6, Freq= 0, CH_0, rank 0
6386 00:44:24.540023 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6387 00:44:24.540526 ==
6388 00:44:24.543133 RX Vref Scan: 0
6389 00:44:24.543512
6390 00:44:24.543802 RX Vref 0 -> 0, step: 1
6391 00:44:24.544073
6392 00:44:24.546565 RX Delay -410 -> 252, step: 16
6393 00:44:24.553123 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6394 00:44:24.556323 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6395 00:44:24.559446 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6396 00:44:24.563461 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6397 00:44:24.569433 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6398 00:44:24.572904 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6399 00:44:24.576211 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6400 00:44:24.579631 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6401 00:44:24.586485 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6402 00:44:24.589989 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6403 00:44:24.592923 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6404 00:44:24.596185 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6405 00:44:24.602799 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6406 00:44:24.606306 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6407 00:44:24.609260 iDelay=230, Bit 14, Center -35 (-298 ~ 229) 528
6408 00:44:24.613136 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6409 00:44:24.613623 ==
6410 00:44:24.616416 Dram Type= 6, Freq= 0, CH_0, rank 0
6411 00:44:24.622609 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6412 00:44:24.622993 ==
6413 00:44:24.623289 DQS Delay:
6414 00:44:24.625957 DQS0 = 59, DQS1 = 59
6415 00:44:24.626345 DQM Delay:
6416 00:44:24.629260 DQM0 = 18, DQM1 = 10
6417 00:44:24.629647 DQ Delay:
6418 00:44:24.632765 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6419 00:44:24.636236 DQ4 =16, DQ5 =0, DQ6 =32, DQ7 =32
6420 00:44:24.639279 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6421 00:44:24.642725 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6422 00:44:24.643114
6423 00:44:24.643414
6424 00:44:24.643696 ==
6425 00:44:24.646177 Dram Type= 6, Freq= 0, CH_0, rank 0
6426 00:44:24.649600 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6427 00:44:24.649995 ==
6428 00:44:24.650300
6429 00:44:24.650576
6430 00:44:24.652594 TX Vref Scan disable
6431 00:44:24.653022 == TX Byte 0 ==
6432 00:44:24.659334 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6433 00:44:24.662679 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6434 00:44:24.663080 == TX Byte 1 ==
6435 00:44:24.669178 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6436 00:44:24.672534 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6437 00:44:24.672985 ==
6438 00:44:24.676190 Dram Type= 6, Freq= 0, CH_0, rank 0
6439 00:44:24.679195 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6440 00:44:24.679620 ==
6441 00:44:24.680085
6442 00:44:24.680443
6443 00:44:24.682482 TX Vref Scan disable
6444 00:44:24.682975 == TX Byte 0 ==
6445 00:44:24.689483 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6446 00:44:24.692919 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6447 00:44:24.693486 == TX Byte 1 ==
6448 00:44:24.699233 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6449 00:44:24.702523 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6450 00:44:24.702926
6451 00:44:24.703226 [DATLAT]
6452 00:44:24.705856 Freq=400, CH0 RK0
6453 00:44:24.706237
6454 00:44:24.706531 DATLAT Default: 0xf
6455 00:44:24.709138 0, 0xFFFF, sum = 0
6456 00:44:24.709529 1, 0xFFFF, sum = 0
6457 00:44:24.712513 2, 0xFFFF, sum = 0
6458 00:44:24.713065 3, 0xFFFF, sum = 0
6459 00:44:24.715963 4, 0xFFFF, sum = 0
6460 00:44:24.716509 5, 0xFFFF, sum = 0
6461 00:44:24.719448 6, 0xFFFF, sum = 0
6462 00:44:24.719953 7, 0xFFFF, sum = 0
6463 00:44:24.722135 8, 0xFFFF, sum = 0
6464 00:44:24.722702 9, 0xFFFF, sum = 0
6465 00:44:24.725826 10, 0xFFFF, sum = 0
6466 00:44:24.726211 11, 0xFFFF, sum = 0
6467 00:44:24.729116 12, 0xFFFF, sum = 0
6468 00:44:24.729505 13, 0x0, sum = 1
6469 00:44:24.732581 14, 0x0, sum = 2
6470 00:44:24.733032 15, 0x0, sum = 3
6471 00:44:24.735623 16, 0x0, sum = 4
6472 00:44:24.736199 best_step = 14
6473 00:44:24.736740
6474 00:44:24.737211 ==
6475 00:44:24.738829 Dram Type= 6, Freq= 0, CH_0, rank 0
6476 00:44:24.745599 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6477 00:44:24.745987 ==
6478 00:44:24.746288 RX Vref Scan: 1
6479 00:44:24.746568
6480 00:44:24.749223 RX Vref 0 -> 0, step: 1
6481 00:44:24.749718
6482 00:44:24.752585 RX Delay -359 -> 252, step: 8
6483 00:44:24.753034
6484 00:44:24.755534 Set Vref, RX VrefLevel [Byte0]: 61
6485 00:44:24.758986 [Byte1]: 48
6486 00:44:24.762200
6487 00:44:24.762613 Final RX Vref Byte 0 = 61 to rank0
6488 00:44:24.765475 Final RX Vref Byte 1 = 48 to rank0
6489 00:44:24.768814 Final RX Vref Byte 0 = 61 to rank1
6490 00:44:24.772422 Final RX Vref Byte 1 = 48 to rank1==
6491 00:44:24.775644 Dram Type= 6, Freq= 0, CH_0, rank 0
6492 00:44:24.782141 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6493 00:44:24.782552 ==
6494 00:44:24.782877 DQS Delay:
6495 00:44:24.785493 DQS0 = 60, DQS1 = 68
6496 00:44:24.785882 DQM Delay:
6497 00:44:24.786191 DQM0 = 15, DQM1 = 13
6498 00:44:24.788748 DQ Delay:
6499 00:44:24.792801 DQ0 =16, DQ1 =16, DQ2 =12, DQ3 =12
6500 00:44:24.795711 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6501 00:44:24.796127 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6502 00:44:24.799049 DQ12 =20, DQ13 =16, DQ14 =24, DQ15 =20
6503 00:44:24.802269
6504 00:44:24.802655
6505 00:44:24.808449 [DQSOSCAuto] RK0, (LSB)MR18= 0x8886, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 392 ps
6506 00:44:24.812282 CH0 RK0: MR19=C0C, MR18=8886
6507 00:44:24.818675 CH0_RK0: MR19=0xC0C, MR18=0x8886, DQSOSC=392, MR23=63, INC=384, DEC=256
6508 00:44:24.819067 ==
6509 00:44:24.822104 Dram Type= 6, Freq= 0, CH_0, rank 1
6510 00:44:24.825554 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6511 00:44:24.825947 ==
6512 00:44:24.828415 [Gating] SW mode calibration
6513 00:44:24.835845 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6514 00:44:24.842142 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6515 00:44:24.845378 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6516 00:44:24.848415 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6517 00:44:24.855537 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6518 00:44:24.858342 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6519 00:44:24.861617 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6520 00:44:24.868425 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6521 00:44:24.871920 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6522 00:44:24.874850 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6523 00:44:24.881421 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6524 00:44:24.881828 Total UI for P1: 0, mck2ui 16
6525 00:44:24.888110 best dqsien dly found for B0: ( 0, 14, 24)
6526 00:44:24.888625 Total UI for P1: 0, mck2ui 16
6527 00:44:24.892238 best dqsien dly found for B1: ( 0, 14, 24)
6528 00:44:24.898240 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6529 00:44:24.901662 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6530 00:44:24.902053
6531 00:44:24.904748 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6532 00:44:24.908402 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6533 00:44:24.911520 [Gating] SW calibration Done
6534 00:44:24.911903 ==
6535 00:44:24.914771 Dram Type= 6, Freq= 0, CH_0, rank 1
6536 00:44:24.918014 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6537 00:44:24.918422 ==
6538 00:44:24.921232 RX Vref Scan: 0
6539 00:44:24.921625
6540 00:44:24.921922 RX Vref 0 -> 0, step: 1
6541 00:44:24.922219
6542 00:44:24.924516 RX Delay -410 -> 252, step: 16
6543 00:44:24.931512 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6544 00:44:24.934425 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6545 00:44:24.938178 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6546 00:44:24.941349 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6547 00:44:24.948382 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6548 00:44:24.951362 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6549 00:44:24.954756 iDelay=230, Bit 6, Center -35 (-298 ~ 229) 528
6550 00:44:24.957730 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6551 00:44:24.964574 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6552 00:44:24.967740 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6553 00:44:24.971231 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6554 00:44:24.974701 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6555 00:44:24.980902 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6556 00:44:24.984444 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6557 00:44:24.988015 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6558 00:44:24.990748 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6559 00:44:24.994604 ==
6560 00:44:24.997975 Dram Type= 6, Freq= 0, CH_0, rank 1
6561 00:44:25.001355 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6562 00:44:25.001967 ==
6563 00:44:25.002307 DQS Delay:
6564 00:44:25.004248 DQS0 = 59, DQS1 = 59
6565 00:44:25.004704 DQM Delay:
6566 00:44:25.008105 DQM0 = 17, DQM1 = 10
6567 00:44:25.008619 DQ Delay:
6568 00:44:25.011417 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6569 00:44:25.014274 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =32
6570 00:44:25.017727 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6571 00:44:25.020749 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6572 00:44:25.021222
6573 00:44:25.021732
6574 00:44:25.022070 ==
6575 00:44:25.024291 Dram Type= 6, Freq= 0, CH_0, rank 1
6576 00:44:25.027686 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6577 00:44:25.028244 ==
6578 00:44:25.028846
6579 00:44:25.029358
6580 00:44:25.030713 TX Vref Scan disable
6581 00:44:25.031157 == TX Byte 0 ==
6582 00:44:25.037498 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6583 00:44:25.040490 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6584 00:44:25.040989 == TX Byte 1 ==
6585 00:44:25.047388 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6586 00:44:25.050823 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6587 00:44:25.051250 ==
6588 00:44:25.053960 Dram Type= 6, Freq= 0, CH_0, rank 1
6589 00:44:25.057188 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6590 00:44:25.057575 ==
6591 00:44:25.057877
6592 00:44:25.058153
6593 00:44:25.060594 TX Vref Scan disable
6594 00:44:25.061022 == TX Byte 0 ==
6595 00:44:25.067639 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6596 00:44:25.070566 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6597 00:44:25.070986 == TX Byte 1 ==
6598 00:44:25.077476 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6599 00:44:25.080368 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6600 00:44:25.080781
6601 00:44:25.081085 [DATLAT]
6602 00:44:25.084077 Freq=400, CH0 RK1
6603 00:44:25.084464
6604 00:44:25.084807 DATLAT Default: 0xe
6605 00:44:25.087299 0, 0xFFFF, sum = 0
6606 00:44:25.087689 1, 0xFFFF, sum = 0
6607 00:44:25.090742 2, 0xFFFF, sum = 0
6608 00:44:25.091134 3, 0xFFFF, sum = 0
6609 00:44:25.093617 4, 0xFFFF, sum = 0
6610 00:44:25.094002 5, 0xFFFF, sum = 0
6611 00:44:25.097055 6, 0xFFFF, sum = 0
6612 00:44:25.097444 7, 0xFFFF, sum = 0
6613 00:44:25.100469 8, 0xFFFF, sum = 0
6614 00:44:25.100902 9, 0xFFFF, sum = 0
6615 00:44:25.103666 10, 0xFFFF, sum = 0
6616 00:44:25.106927 11, 0xFFFF, sum = 0
6617 00:44:25.107443 12, 0xFFFF, sum = 0
6618 00:44:25.110164 13, 0x0, sum = 1
6619 00:44:25.110555 14, 0x0, sum = 2
6620 00:44:25.113445 15, 0x0, sum = 3
6621 00:44:25.113870 16, 0x0, sum = 4
6622 00:44:25.114349 best_step = 14
6623 00:44:25.114650
6624 00:44:25.116631 ==
6625 00:44:25.120165 Dram Type= 6, Freq= 0, CH_0, rank 1
6626 00:44:25.123588 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6627 00:44:25.123977 ==
6628 00:44:25.124276 RX Vref Scan: 0
6629 00:44:25.124554
6630 00:44:25.126740 RX Vref 0 -> 0, step: 1
6631 00:44:25.127127
6632 00:44:25.130358 RX Delay -359 -> 252, step: 8
6633 00:44:25.137316 iDelay=217, Bit 0, Center -52 (-303 ~ 200) 504
6634 00:44:25.140556 iDelay=217, Bit 1, Center -44 (-295 ~ 208) 504
6635 00:44:25.144067 iDelay=217, Bit 2, Center -52 (-303 ~ 200) 504
6636 00:44:25.147397 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6637 00:44:25.153743 iDelay=217, Bit 4, Center -52 (-303 ~ 200) 504
6638 00:44:25.157190 iDelay=217, Bit 5, Center -60 (-311 ~ 192) 504
6639 00:44:25.160434 iDelay=217, Bit 6, Center -40 (-295 ~ 216) 512
6640 00:44:25.163813 iDelay=217, Bit 7, Center -36 (-287 ~ 216) 504
6641 00:44:25.170314 iDelay=217, Bit 8, Center -64 (-311 ~ 184) 496
6642 00:44:25.173842 iDelay=217, Bit 9, Center -72 (-319 ~ 176) 496
6643 00:44:25.177317 iDelay=217, Bit 10, Center -52 (-303 ~ 200) 504
6644 00:44:25.183542 iDelay=217, Bit 11, Center -64 (-311 ~ 184) 496
6645 00:44:25.186506 iDelay=217, Bit 12, Center -52 (-303 ~ 200) 504
6646 00:44:25.190017 iDelay=217, Bit 13, Center -44 (-295 ~ 208) 504
6647 00:44:25.193395 iDelay=217, Bit 14, Center -44 (-295 ~ 208) 504
6648 00:44:25.199960 iDelay=217, Bit 15, Center -48 (-295 ~ 200) 496
6649 00:44:25.200039 ==
6650 00:44:25.203140 Dram Type= 6, Freq= 0, CH_0, rank 1
6651 00:44:25.206859 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6652 00:44:25.206938 ==
6653 00:44:25.207015 DQS Delay:
6654 00:44:25.209635 DQS0 = 60, DQS1 = 72
6655 00:44:25.209713 DQM Delay:
6656 00:44:25.212975 DQM0 = 11, DQM1 = 17
6657 00:44:25.213053 DQ Delay:
6658 00:44:25.216392 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6659 00:44:25.220095 DQ4 =8, DQ5 =0, DQ6 =20, DQ7 =24
6660 00:44:25.223122 DQ8 =8, DQ9 =0, DQ10 =20, DQ11 =8
6661 00:44:25.226379 DQ12 =20, DQ13 =28, DQ14 =28, DQ15 =24
6662 00:44:25.226483
6663 00:44:25.226541
6664 00:44:25.233497 [DQSOSCAuto] RK1, (LSB)MR18= 0xca80, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 384 ps
6665 00:44:25.236550 CH0 RK1: MR19=C0C, MR18=CA80
6666 00:44:25.243000 CH0_RK1: MR19=0xC0C, MR18=0xCA80, DQSOSC=384, MR23=63, INC=400, DEC=267
6667 00:44:25.246543 [RxdqsGatingPostProcess] freq 400
6668 00:44:25.253378 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6669 00:44:25.253472 best DQS0 dly(2T, 0.5T) = (0, 10)
6670 00:44:25.256528 best DQS1 dly(2T, 0.5T) = (0, 10)
6671 00:44:25.259474 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6672 00:44:25.262751 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6673 00:44:25.266565 best DQS0 dly(2T, 0.5T) = (0, 10)
6674 00:44:25.269947 best DQS1 dly(2T, 0.5T) = (0, 10)
6675 00:44:25.272826 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6676 00:44:25.276266 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6677 00:44:25.279522 Pre-setting of DQS Precalculation
6678 00:44:25.286033 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6679 00:44:25.286109 ==
6680 00:44:25.289473 Dram Type= 6, Freq= 0, CH_1, rank 0
6681 00:44:25.293037 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6682 00:44:25.293113 ==
6683 00:44:25.299680 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6684 00:44:25.303063 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6685 00:44:25.305923 [CA 0] Center 36 (8~64) winsize 57
6686 00:44:25.309430 [CA 1] Center 36 (8~64) winsize 57
6687 00:44:25.313019 [CA 2] Center 36 (8~64) winsize 57
6688 00:44:25.316015 [CA 3] Center 36 (8~64) winsize 57
6689 00:44:25.319383 [CA 4] Center 36 (8~64) winsize 57
6690 00:44:25.322960 [CA 5] Center 36 (8~64) winsize 57
6691 00:44:25.323036
6692 00:44:25.325898 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6693 00:44:25.325974
6694 00:44:25.329224 [CATrainingPosCal] consider 1 rank data
6695 00:44:25.332373 u2DelayCellTimex100 = 270/100 ps
6696 00:44:25.335976 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6697 00:44:25.339351 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6698 00:44:25.342361 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6699 00:44:25.349008 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6700 00:44:25.352803 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6701 00:44:25.355953 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6702 00:44:25.356029
6703 00:44:25.359146 CA PerBit enable=1, Macro0, CA PI delay=36
6704 00:44:25.359223
6705 00:44:25.362345 [CBTSetCACLKResult] CA Dly = 36
6706 00:44:25.362445 CS Dly: 1 (0~32)
6707 00:44:25.362548 ==
6708 00:44:25.365694 Dram Type= 6, Freq= 0, CH_1, rank 1
6709 00:44:25.372527 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6710 00:44:25.372627 ==
6711 00:44:25.375408 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6712 00:44:25.382232 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6713 00:44:25.385806 [CA 0] Center 36 (8~64) winsize 57
6714 00:44:25.388983 [CA 1] Center 36 (8~64) winsize 57
6715 00:44:25.392595 [CA 2] Center 36 (8~64) winsize 57
6716 00:44:25.395649 [CA 3] Center 36 (8~64) winsize 57
6717 00:44:25.399159 [CA 4] Center 36 (8~64) winsize 57
6718 00:44:25.402404 [CA 5] Center 36 (8~64) winsize 57
6719 00:44:25.402479
6720 00:44:25.406189 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6721 00:44:25.406265
6722 00:44:25.409129 [CATrainingPosCal] consider 2 rank data
6723 00:44:25.412565 u2DelayCellTimex100 = 270/100 ps
6724 00:44:25.415447 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6725 00:44:25.418963 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6726 00:44:25.422262 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6727 00:44:25.426158 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6728 00:44:25.428825 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6729 00:44:25.432404 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6730 00:44:25.432507
6731 00:44:25.438942 CA PerBit enable=1, Macro0, CA PI delay=36
6732 00:44:25.439017
6733 00:44:25.442289 [CBTSetCACLKResult] CA Dly = 36
6734 00:44:25.442366 CS Dly: 1 (0~32)
6735 00:44:25.442434
6736 00:44:25.445420 ----->DramcWriteLeveling(PI) begin...
6737 00:44:25.445497 ==
6738 00:44:25.448835 Dram Type= 6, Freq= 0, CH_1, rank 0
6739 00:44:25.452352 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6740 00:44:25.452485 ==
6741 00:44:25.455456 Write leveling (Byte 0): 40 => 8
6742 00:44:25.458453 Write leveling (Byte 1): 40 => 8
6743 00:44:25.461903 DramcWriteLeveling(PI) end<-----
6744 00:44:25.461978
6745 00:44:25.462037 ==
6746 00:44:25.465028 Dram Type= 6, Freq= 0, CH_1, rank 0
6747 00:44:25.471998 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6748 00:44:25.472074 ==
6749 00:44:25.472134 [Gating] SW mode calibration
6750 00:44:25.481519 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6751 00:44:25.485108 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6752 00:44:25.488561 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6753 00:44:25.495178 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6754 00:44:25.498300 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6755 00:44:25.501768 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6756 00:44:25.508535 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6757 00:44:25.511373 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6758 00:44:25.514713 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6759 00:44:25.521502 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6760 00:44:25.524810 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6761 00:44:25.527769 Total UI for P1: 0, mck2ui 16
6762 00:44:25.531152 best dqsien dly found for B0: ( 0, 14, 24)
6763 00:44:25.534563 Total UI for P1: 0, mck2ui 16
6764 00:44:25.537691 best dqsien dly found for B1: ( 0, 14, 24)
6765 00:44:25.541463 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6766 00:44:25.544685 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6767 00:44:25.544762
6768 00:44:25.547657 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6769 00:44:25.554498 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6770 00:44:25.554584 [Gating] SW calibration Done
6771 00:44:25.554646 ==
6772 00:44:25.557610 Dram Type= 6, Freq= 0, CH_1, rank 0
6773 00:44:25.564473 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6774 00:44:25.564566 ==
6775 00:44:25.564627 RX Vref Scan: 0
6776 00:44:25.564705
6777 00:44:25.567536 RX Vref 0 -> 0, step: 1
6778 00:44:25.567613
6779 00:44:25.571153 RX Delay -410 -> 252, step: 16
6780 00:44:25.574247 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6781 00:44:25.577420 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6782 00:44:25.583887 iDelay=230, Bit 2, Center -51 (-314 ~ 213) 528
6783 00:44:25.587571 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6784 00:44:25.590591 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6785 00:44:25.594053 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6786 00:44:25.600936 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6787 00:44:25.604026 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6788 00:44:25.607157 iDelay=230, Bit 8, Center -67 (-330 ~ 197) 528
6789 00:44:25.610535 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6790 00:44:25.617457 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6791 00:44:25.620359 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6792 00:44:25.623725 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6793 00:44:25.630228 iDelay=230, Bit 13, Center -35 (-298 ~ 229) 528
6794 00:44:25.634118 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6795 00:44:25.636927 iDelay=230, Bit 15, Center -35 (-298 ~ 229) 528
6796 00:44:25.637003 ==
6797 00:44:25.640419 Dram Type= 6, Freq= 0, CH_1, rank 0
6798 00:44:25.643805 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6799 00:44:25.643882 ==
6800 00:44:25.646688 DQS Delay:
6801 00:44:25.646764 DQS0 = 51, DQS1 = 67
6802 00:44:25.650024 DQM Delay:
6803 00:44:25.650099 DQM0 = 12, DQM1 = 19
6804 00:44:25.653248 DQ Delay:
6805 00:44:25.653324 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6806 00:44:25.657257 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6807 00:44:25.660085 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6808 00:44:25.663425 DQ12 =24, DQ13 =32, DQ14 =24, DQ15 =32
6809 00:44:25.663501
6810 00:44:25.663560
6811 00:44:25.666952 ==
6812 00:44:25.667027 Dram Type= 6, Freq= 0, CH_1, rank 0
6813 00:44:25.673504 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6814 00:44:25.673580 ==
6815 00:44:25.673639
6816 00:44:25.673693
6817 00:44:25.676631 TX Vref Scan disable
6818 00:44:25.676731 == TX Byte 0 ==
6819 00:44:25.679908 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6820 00:44:25.686628 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6821 00:44:25.686704 == TX Byte 1 ==
6822 00:44:25.689996 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6823 00:44:25.696633 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6824 00:44:25.696729 ==
6825 00:44:25.699972 Dram Type= 6, Freq= 0, CH_1, rank 0
6826 00:44:25.703451 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6827 00:44:25.703528 ==
6828 00:44:25.703588
6829 00:44:25.703642
6830 00:44:25.706357 TX Vref Scan disable
6831 00:44:25.706434 == TX Byte 0 ==
6832 00:44:25.709610 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6833 00:44:25.715899 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6834 00:44:25.715975 == TX Byte 1 ==
6835 00:44:25.719201 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6836 00:44:25.725964 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6837 00:44:25.726040
6838 00:44:25.726098 [DATLAT]
6839 00:44:25.726154 Freq=400, CH1 RK0
6840 00:44:25.729451
6841 00:44:25.729527 DATLAT Default: 0xf
6842 00:44:25.732837 0, 0xFFFF, sum = 0
6843 00:44:25.732916 1, 0xFFFF, sum = 0
6844 00:44:25.736295 2, 0xFFFF, sum = 0
6845 00:44:25.736371 3, 0xFFFF, sum = 0
6846 00:44:25.739121 4, 0xFFFF, sum = 0
6847 00:44:25.739198 5, 0xFFFF, sum = 0
6848 00:44:25.742500 6, 0xFFFF, sum = 0
6849 00:44:25.742577 7, 0xFFFF, sum = 0
6850 00:44:25.745975 8, 0xFFFF, sum = 0
6851 00:44:25.746052 9, 0xFFFF, sum = 0
6852 00:44:25.749419 10, 0xFFFF, sum = 0
6853 00:44:25.749495 11, 0xFFFF, sum = 0
6854 00:44:25.752355 12, 0xFFFF, sum = 0
6855 00:44:25.752432 13, 0x0, sum = 1
6856 00:44:25.755792 14, 0x0, sum = 2
6857 00:44:25.755869 15, 0x0, sum = 3
6858 00:44:25.759057 16, 0x0, sum = 4
6859 00:44:25.759134 best_step = 14
6860 00:44:25.759193
6861 00:44:25.759247 ==
6862 00:44:25.762669 Dram Type= 6, Freq= 0, CH_1, rank 0
6863 00:44:25.768897 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6864 00:44:25.768973 ==
6865 00:44:25.769032 RX Vref Scan: 1
6866 00:44:25.769087
6867 00:44:25.772279 RX Vref 0 -> 0, step: 1
6868 00:44:25.772374
6869 00:44:25.775963 RX Delay -375 -> 252, step: 8
6870 00:44:25.776039
6871 00:44:25.778977 Set Vref, RX VrefLevel [Byte0]: 57
6872 00:44:25.782434 [Byte1]: 53
6873 00:44:25.782510
6874 00:44:25.785550 Final RX Vref Byte 0 = 57 to rank0
6875 00:44:25.789182 Final RX Vref Byte 1 = 53 to rank0
6876 00:44:25.792338 Final RX Vref Byte 0 = 57 to rank1
6877 00:44:25.795733 Final RX Vref Byte 1 = 53 to rank1==
6878 00:44:25.799058 Dram Type= 6, Freq= 0, CH_1, rank 0
6879 00:44:25.802204 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6880 00:44:25.805637 ==
6881 00:44:25.805712 DQS Delay:
6882 00:44:25.805771 DQS0 = 56, DQS1 = 64
6883 00:44:25.809126 DQM Delay:
6884 00:44:25.809201 DQM0 = 12, DQM1 = 10
6885 00:44:25.812514 DQ Delay:
6886 00:44:25.812589 DQ0 =20, DQ1 =8, DQ2 =0, DQ3 =8
6887 00:44:25.815807 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6888 00:44:25.819083 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6889 00:44:25.822124 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =16
6890 00:44:25.822203
6891 00:44:25.822262
6892 00:44:25.832349 [DQSOSCAuto] RK0, (LSB)MR18= 0x6072, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 397 ps
6893 00:44:25.835184 CH1 RK0: MR19=C0C, MR18=6072
6894 00:44:25.842124 CH1_RK0: MR19=0xC0C, MR18=0x6072, DQSOSC=395, MR23=63, INC=378, DEC=252
6895 00:44:25.842201 ==
6896 00:44:25.845658 Dram Type= 6, Freq= 0, CH_1, rank 1
6897 00:44:25.848476 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6898 00:44:25.848553 ==
6899 00:44:25.851901 [Gating] SW mode calibration
6900 00:44:25.858748 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6901 00:44:25.862160 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6902 00:44:25.868363 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6903 00:44:25.871860 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6904 00:44:25.875668 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6905 00:44:25.881991 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6906 00:44:25.885125 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6907 00:44:25.888352 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6908 00:44:25.895226 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6909 00:44:25.898770 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6910 00:44:25.901399 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6911 00:44:25.904565 Total UI for P1: 0, mck2ui 16
6912 00:44:25.908244 best dqsien dly found for B0: ( 0, 14, 24)
6913 00:44:25.911291 Total UI for P1: 0, mck2ui 16
6914 00:44:25.915021 best dqsien dly found for B1: ( 0, 14, 24)
6915 00:44:25.917894 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6916 00:44:25.924901 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6917 00:44:25.925088
6918 00:44:25.928141 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6919 00:44:25.931193 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6920 00:44:25.934787 [Gating] SW calibration Done
6921 00:44:25.935066 ==
6922 00:44:25.938558 Dram Type= 6, Freq= 0, CH_1, rank 1
6923 00:44:25.941450 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6924 00:44:25.941811 ==
6925 00:44:25.942095 RX Vref Scan: 0
6926 00:44:25.944990
6927 00:44:25.945377 RX Vref 0 -> 0, step: 1
6928 00:44:25.945681
6929 00:44:25.948442 RX Delay -410 -> 252, step: 16
6930 00:44:25.951332 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6931 00:44:25.958338 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6932 00:44:25.961246 iDelay=230, Bit 2, Center -59 (-314 ~ 197) 512
6933 00:44:25.964840 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6934 00:44:25.968269 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6935 00:44:25.974592 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6936 00:44:25.977978 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6937 00:44:25.981333 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6938 00:44:25.984281 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6939 00:44:25.991213 iDelay=230, Bit 9, Center -51 (-314 ~ 213) 528
6940 00:44:25.994271 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6941 00:44:25.997678 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6942 00:44:26.004403 iDelay=230, Bit 12, Center -35 (-298 ~ 229) 528
6943 00:44:26.007664 iDelay=230, Bit 13, Center -35 (-298 ~ 229) 528
6944 00:44:26.010723 iDelay=230, Bit 14, Center -35 (-298 ~ 229) 528
6945 00:44:26.014242 iDelay=230, Bit 15, Center -35 (-298 ~ 229) 528
6946 00:44:26.014451 ==
6947 00:44:26.017373 Dram Type= 6, Freq= 0, CH_1, rank 1
6948 00:44:26.024068 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6949 00:44:26.024281 ==
6950 00:44:26.024446 DQS Delay:
6951 00:44:26.027281 DQS0 = 59, DQS1 = 59
6952 00:44:26.027490 DQM Delay:
6953 00:44:26.030873 DQM0 = 19, DQM1 = 16
6954 00:44:26.031081 DQ Delay:
6955 00:44:26.033791 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6956 00:44:26.037223 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6957 00:44:26.040806 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6958 00:44:26.043793 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6959 00:44:26.044004
6960 00:44:26.044167
6961 00:44:26.044318 ==
6962 00:44:26.047100 Dram Type= 6, Freq= 0, CH_1, rank 1
6963 00:44:26.050420 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6964 00:44:26.050629 ==
6965 00:44:26.050792
6966 00:44:26.050941
6967 00:44:26.053860 TX Vref Scan disable
6968 00:44:26.054069 == TX Byte 0 ==
6969 00:44:26.060210 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6970 00:44:26.063620 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6971 00:44:26.063831 == TX Byte 1 ==
6972 00:44:26.070346 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6973 00:44:26.073755 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6974 00:44:26.073965 ==
6975 00:44:26.076693 Dram Type= 6, Freq= 0, CH_1, rank 1
6976 00:44:26.080097 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6977 00:44:26.080308 ==
6978 00:44:26.080472
6979 00:44:26.080621
6980 00:44:26.083476 TX Vref Scan disable
6981 00:44:26.083687 == TX Byte 0 ==
6982 00:44:26.090406 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6983 00:44:26.093206 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6984 00:44:26.093416 == TX Byte 1 ==
6985 00:44:26.099947 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6986 00:44:26.103108 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6987 00:44:26.103319
6988 00:44:26.103483 [DATLAT]
6989 00:44:26.106529 Freq=400, CH1 RK1
6990 00:44:26.106738
6991 00:44:26.106901 DATLAT Default: 0xe
6992 00:44:26.109596 0, 0xFFFF, sum = 0
6993 00:44:26.109808 1, 0xFFFF, sum = 0
6994 00:44:26.112934 2, 0xFFFF, sum = 0
6995 00:44:26.113147 3, 0xFFFF, sum = 0
6996 00:44:26.116315 4, 0xFFFF, sum = 0
6997 00:44:26.119691 5, 0xFFFF, sum = 0
6998 00:44:26.119903 6, 0xFFFF, sum = 0
6999 00:44:26.123023 7, 0xFFFF, sum = 0
7000 00:44:26.123238 8, 0xFFFF, sum = 0
7001 00:44:26.126276 9, 0xFFFF, sum = 0
7002 00:44:26.126489 10, 0xFFFF, sum = 0
7003 00:44:26.129217 11, 0xFFFF, sum = 0
7004 00:44:26.129294 12, 0xFFFF, sum = 0
7005 00:44:26.133038 13, 0x0, sum = 1
7006 00:44:26.133116 14, 0x0, sum = 2
7007 00:44:26.136326 15, 0x0, sum = 3
7008 00:44:26.136403 16, 0x0, sum = 4
7009 00:44:26.136463 best_step = 14
7010 00:44:26.139529
7011 00:44:26.139605 ==
7012 00:44:26.142873 Dram Type= 6, Freq= 0, CH_1, rank 1
7013 00:44:26.145939 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7014 00:44:26.146015 ==
7015 00:44:26.146075 RX Vref Scan: 0
7016 00:44:26.146131
7017 00:44:26.149304 RX Vref 0 -> 0, step: 1
7018 00:44:26.149380
7019 00:44:26.152866 RX Delay -359 -> 252, step: 8
7020 00:44:26.160110 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
7021 00:44:26.163251 iDelay=217, Bit 1, Center -52 (-303 ~ 200) 504
7022 00:44:26.166536 iDelay=217, Bit 2, Center -60 (-311 ~ 192) 504
7023 00:44:26.170121 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
7024 00:44:26.176407 iDelay=217, Bit 4, Center -48 (-303 ~ 208) 512
7025 00:44:26.179943 iDelay=217, Bit 5, Center -36 (-287 ~ 216) 504
7026 00:44:26.183364 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
7027 00:44:26.186229 iDelay=217, Bit 7, Center -52 (-303 ~ 200) 504
7028 00:44:26.193226 iDelay=217, Bit 8, Center -68 (-327 ~ 192) 520
7029 00:44:26.196086 iDelay=217, Bit 9, Center -64 (-319 ~ 192) 512
7030 00:44:26.199546 iDelay=217, Bit 10, Center -48 (-303 ~ 208) 512
7031 00:44:26.206404 iDelay=217, Bit 11, Center -60 (-311 ~ 192) 504
7032 00:44:26.209985 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
7033 00:44:26.213108 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
7034 00:44:26.216515 iDelay=217, Bit 14, Center -48 (-303 ~ 208) 512
7035 00:44:26.223205 iDelay=217, Bit 15, Center -48 (-303 ~ 208) 512
7036 00:44:26.223282 ==
7037 00:44:26.226084 Dram Type= 6, Freq= 0, CH_1, rank 1
7038 00:44:26.229963 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7039 00:44:26.230040 ==
7040 00:44:26.230098 DQS Delay:
7041 00:44:26.232723 DQS0 = 60, DQS1 = 68
7042 00:44:26.232799 DQM Delay:
7043 00:44:26.236137 DQM0 = 12, DQM1 = 14
7044 00:44:26.236212 DQ Delay:
7045 00:44:26.239567 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
7046 00:44:26.243385 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =8
7047 00:44:26.246808 DQ8 =0, DQ9 =4, DQ10 =20, DQ11 =8
7048 00:44:26.249987 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20
7049 00:44:26.250477
7050 00:44:26.250787
7051 00:44:26.256417 [DQSOSCAuto] RK1, (LSB)MR18= 0x7dad, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 394 ps
7052 00:44:26.260038 CH1 RK1: MR19=C0C, MR18=7DAD
7053 00:44:26.266527 CH1_RK1: MR19=0xC0C, MR18=0x7DAD, DQSOSC=388, MR23=63, INC=392, DEC=261
7054 00:44:26.269737 [RxdqsGatingPostProcess] freq 400
7055 00:44:26.276600 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7056 00:44:26.277140 best DQS0 dly(2T, 0.5T) = (0, 10)
7057 00:44:26.280001 best DQS1 dly(2T, 0.5T) = (0, 10)
7058 00:44:26.283573 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7059 00:44:26.286309 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7060 00:44:26.290202 best DQS0 dly(2T, 0.5T) = (0, 10)
7061 00:44:26.292983 best DQS1 dly(2T, 0.5T) = (0, 10)
7062 00:44:26.296837 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7063 00:44:26.299881 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7064 00:44:26.303243 Pre-setting of DQS Precalculation
7065 00:44:26.309668 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7066 00:44:26.316414 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7067 00:44:26.323168 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7068 00:44:26.323602
7069 00:44:26.323936
7070 00:44:26.326207 [Calibration Summary] 800 Mbps
7071 00:44:26.326640 CH 0, Rank 0
7072 00:44:26.329695 SW Impedance : PASS
7073 00:44:26.330127 DUTY Scan : NO K
7074 00:44:26.332988 ZQ Calibration : PASS
7075 00:44:26.336379 Jitter Meter : NO K
7076 00:44:26.336852 CBT Training : PASS
7077 00:44:26.339669 Write leveling : PASS
7078 00:44:26.342954 RX DQS gating : PASS
7079 00:44:26.343389 RX DQ/DQS(RDDQC) : PASS
7080 00:44:26.346419 TX DQ/DQS : PASS
7081 00:44:26.349373 RX DATLAT : PASS
7082 00:44:26.349807 RX DQ/DQS(Engine): PASS
7083 00:44:26.352794 TX OE : NO K
7084 00:44:26.353187 All Pass.
7085 00:44:26.353493
7086 00:44:26.355939 CH 0, Rank 1
7087 00:44:26.356328 SW Impedance : PASS
7088 00:44:26.359576 DUTY Scan : NO K
7089 00:44:26.362862 ZQ Calibration : PASS
7090 00:44:26.363251 Jitter Meter : NO K
7091 00:44:26.366078 CBT Training : PASS
7092 00:44:26.369294 Write leveling : NO K
7093 00:44:26.369712 RX DQS gating : PASS
7094 00:44:26.372685 RX DQ/DQS(RDDQC) : PASS
7095 00:44:26.376138 TX DQ/DQS : PASS
7096 00:44:26.376528 RX DATLAT : PASS
7097 00:44:26.379529 RX DQ/DQS(Engine): PASS
7098 00:44:26.379918 TX OE : NO K
7099 00:44:26.382791 All Pass.
7100 00:44:26.383179
7101 00:44:26.383481 CH 1, Rank 0
7102 00:44:26.385427 SW Impedance : PASS
7103 00:44:26.388924 DUTY Scan : NO K
7104 00:44:26.389000 ZQ Calibration : PASS
7105 00:44:26.392318 Jitter Meter : NO K
7106 00:44:26.392393 CBT Training : PASS
7107 00:44:26.395441 Write leveling : PASS
7108 00:44:26.398739 RX DQS gating : PASS
7109 00:44:26.398814 RX DQ/DQS(RDDQC) : PASS
7110 00:44:26.402240 TX DQ/DQS : PASS
7111 00:44:26.405616 RX DATLAT : PASS
7112 00:44:26.405692 RX DQ/DQS(Engine): PASS
7113 00:44:26.408514 TX OE : NO K
7114 00:44:26.408589 All Pass.
7115 00:44:26.408668
7116 00:44:26.411885 CH 1, Rank 1
7117 00:44:26.411960 SW Impedance : PASS
7118 00:44:26.415321 DUTY Scan : NO K
7119 00:44:26.418772 ZQ Calibration : PASS
7120 00:44:26.418847 Jitter Meter : NO K
7121 00:44:26.422076 CBT Training : PASS
7122 00:44:26.425346 Write leveling : NO K
7123 00:44:26.425421 RX DQS gating : PASS
7124 00:44:26.428567 RX DQ/DQS(RDDQC) : PASS
7125 00:44:26.432199 TX DQ/DQS : PASS
7126 00:44:26.432275 RX DATLAT : PASS
7127 00:44:26.435120 RX DQ/DQS(Engine): PASS
7128 00:44:26.435197 TX OE : NO K
7129 00:44:26.438464 All Pass.
7130 00:44:26.438539
7131 00:44:26.438597 DramC Write-DBI off
7132 00:44:26.441880 PER_BANK_REFRESH: Hybrid Mode
7133 00:44:26.445570 TX_TRACKING: ON
7134 00:44:26.451939 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7135 00:44:26.455372 [FAST_K] Save calibration result to emmc
7136 00:44:26.462133 dramc_set_vcore_voltage set vcore to 725000
7137 00:44:26.462210 Read voltage for 1600, 0
7138 00:44:26.462269 Vio18 = 0
7139 00:44:26.465449 Vcore = 725000
7140 00:44:26.465524 Vdram = 0
7141 00:44:26.465583 Vddq = 0
7142 00:44:26.468574 Vmddr = 0
7143 00:44:26.471691 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7144 00:44:26.478447 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7145 00:44:26.481985 MEM_TYPE=3, freq_sel=13
7146 00:44:26.482085 sv_algorithm_assistance_LP4_3733
7147 00:44:26.488322 ============ PULL DRAM RESETB DOWN ============
7148 00:44:26.491817 ========== PULL DRAM RESETB DOWN end =========
7149 00:44:26.495164 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7150 00:44:26.498331 ===================================
7151 00:44:26.501420 LPDDR4 DRAM CONFIGURATION
7152 00:44:26.505007 ===================================
7153 00:44:26.508323 EX_ROW_EN[0] = 0x0
7154 00:44:26.508398 EX_ROW_EN[1] = 0x0
7155 00:44:26.511820 LP4Y_EN = 0x0
7156 00:44:26.511895 WORK_FSP = 0x1
7157 00:44:26.515228 WL = 0x5
7158 00:44:26.515303 RL = 0x5
7159 00:44:26.518075 BL = 0x2
7160 00:44:26.518151 RPST = 0x0
7161 00:44:26.521502 RD_PRE = 0x0
7162 00:44:26.521577 WR_PRE = 0x1
7163 00:44:26.524883 WR_PST = 0x1
7164 00:44:26.524958 DBI_WR = 0x0
7165 00:44:26.528188 DBI_RD = 0x0
7166 00:44:26.531453 OTF = 0x1
7167 00:44:26.531528 ===================================
7168 00:44:26.534847 ===================================
7169 00:44:26.538197 ANA top config
7170 00:44:26.541580 ===================================
7171 00:44:26.545014 DLL_ASYNC_EN = 0
7172 00:44:26.545115 ALL_SLAVE_EN = 0
7173 00:44:26.548198 NEW_RANK_MODE = 1
7174 00:44:26.551418 DLL_IDLE_MODE = 1
7175 00:44:26.554838 LP45_APHY_COMB_EN = 1
7176 00:44:26.558319 TX_ODT_DIS = 0
7177 00:44:26.558396 NEW_8X_MODE = 1
7178 00:44:26.561520 ===================================
7179 00:44:26.564631 ===================================
7180 00:44:26.568443 data_rate = 3200
7181 00:44:26.571757 CKR = 1
7182 00:44:26.574907 DQ_P2S_RATIO = 8
7183 00:44:26.577924 ===================================
7184 00:44:26.581481 CA_P2S_RATIO = 8
7185 00:44:26.584610 DQ_CA_OPEN = 0
7186 00:44:26.584695 DQ_SEMI_OPEN = 0
7187 00:44:26.587823 CA_SEMI_OPEN = 0
7188 00:44:26.591401 CA_FULL_RATE = 0
7189 00:44:26.594814 DQ_CKDIV4_EN = 0
7190 00:44:26.598165 CA_CKDIV4_EN = 0
7191 00:44:26.598260 CA_PREDIV_EN = 0
7192 00:44:26.601049 PH8_DLY = 12
7193 00:44:26.604455 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7194 00:44:26.607851 DQ_AAMCK_DIV = 4
7195 00:44:26.610937 CA_AAMCK_DIV = 4
7196 00:44:26.614586 CA_ADMCK_DIV = 4
7197 00:44:26.618107 DQ_TRACK_CA_EN = 0
7198 00:44:26.618210 CA_PICK = 1600
7199 00:44:26.621023 CA_MCKIO = 1600
7200 00:44:26.624446 MCKIO_SEMI = 0
7201 00:44:26.627997 PLL_FREQ = 3068
7202 00:44:26.631375 DQ_UI_PI_RATIO = 32
7203 00:44:26.634595 CA_UI_PI_RATIO = 0
7204 00:44:26.638218 ===================================
7205 00:44:26.641461 ===================================
7206 00:44:26.641693 memory_type:LPDDR4
7207 00:44:26.644834 GP_NUM : 10
7208 00:44:26.647737 SRAM_EN : 1
7209 00:44:26.648005 MD32_EN : 0
7210 00:44:26.650863 ===================================
7211 00:44:26.654587 [ANA_INIT] >>>>>>>>>>>>>>
7212 00:44:26.657789 <<<<<< [CONFIGURE PHASE]: ANA_TX
7213 00:44:26.660990 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7214 00:44:26.664535 ===================================
7215 00:44:26.667957 data_rate = 3200,PCW = 0X7600
7216 00:44:26.671395 ===================================
7217 00:44:26.674285 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7218 00:44:26.677747 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7219 00:44:26.684520 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7220 00:44:26.687964 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7221 00:44:26.694196 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7222 00:44:26.697709 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7223 00:44:26.698153 [ANA_INIT] flow start
7224 00:44:26.701286 [ANA_INIT] PLL >>>>>>>>
7225 00:44:26.704494 [ANA_INIT] PLL <<<<<<<<
7226 00:44:26.704947 [ANA_INIT] MIDPI >>>>>>>>
7227 00:44:26.708056 [ANA_INIT] MIDPI <<<<<<<<
7228 00:44:26.711394 [ANA_INIT] DLL >>>>>>>>
7229 00:44:26.711913 [ANA_INIT] DLL <<<<<<<<
7230 00:44:26.714516 [ANA_INIT] flow end
7231 00:44:26.717715 ============ LP4 DIFF to SE enter ============
7232 00:44:26.720607 ============ LP4 DIFF to SE exit ============
7233 00:44:26.724350 [ANA_INIT] <<<<<<<<<<<<<
7234 00:44:26.727684 [Flow] Enable top DCM control >>>>>
7235 00:44:26.731313 [Flow] Enable top DCM control <<<<<
7236 00:44:26.734368 Enable DLL master slave shuffle
7237 00:44:26.740595 ==============================================================
7238 00:44:26.741192 Gating Mode config
7239 00:44:26.747471 ==============================================================
7240 00:44:26.748040 Config description:
7241 00:44:26.757489 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7242 00:44:26.764041 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7243 00:44:26.770365 SELPH_MODE 0: By rank 1: By Phase
7244 00:44:26.777308 ==============================================================
7245 00:44:26.777852 GAT_TRACK_EN = 1
7246 00:44:26.780573 RX_GATING_MODE = 2
7247 00:44:26.783418 RX_GATING_TRACK_MODE = 2
7248 00:44:26.786789 SELPH_MODE = 1
7249 00:44:26.790374 PICG_EARLY_EN = 1
7250 00:44:26.793837 VALID_LAT_VALUE = 1
7251 00:44:26.800535 ==============================================================
7252 00:44:26.803630 Enter into Gating configuration >>>>
7253 00:44:26.807069 Exit from Gating configuration <<<<
7254 00:44:26.810254 Enter into DVFS_PRE_config >>>>>
7255 00:44:26.819916 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7256 00:44:26.823542 Exit from DVFS_PRE_config <<<<<
7257 00:44:26.826868 Enter into PICG configuration >>>>
7258 00:44:26.829990 Exit from PICG configuration <<<<
7259 00:44:26.833540 [RX_INPUT] configuration >>>>>
7260 00:44:26.834204 [RX_INPUT] configuration <<<<<
7261 00:44:26.839451 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7262 00:44:26.846349 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7263 00:44:26.852883 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7264 00:44:26.856142 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7265 00:44:26.862996 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7266 00:44:26.869946 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7267 00:44:26.872841 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7268 00:44:26.879562 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7269 00:44:26.882620 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7270 00:44:26.886065 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7271 00:44:26.889630 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7272 00:44:26.895811 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7273 00:44:26.899553 ===================================
7274 00:44:26.900118 LPDDR4 DRAM CONFIGURATION
7275 00:44:26.902772 ===================================
7276 00:44:26.905890 EX_ROW_EN[0] = 0x0
7277 00:44:26.909295 EX_ROW_EN[1] = 0x0
7278 00:44:26.909755 LP4Y_EN = 0x0
7279 00:44:26.912077 WORK_FSP = 0x1
7280 00:44:26.912587 WL = 0x5
7281 00:44:26.915476 RL = 0x5
7282 00:44:26.915875 BL = 0x2
7283 00:44:26.919237 RPST = 0x0
7284 00:44:26.919626 RD_PRE = 0x0
7285 00:44:26.922241 WR_PRE = 0x1
7286 00:44:26.922786 WR_PST = 0x1
7287 00:44:26.925576 DBI_WR = 0x0
7288 00:44:26.925922 DBI_RD = 0x0
7289 00:44:26.929064 OTF = 0x1
7290 00:44:26.932415 ===================================
7291 00:44:26.935744 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7292 00:44:26.938796 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7293 00:44:26.945406 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7294 00:44:26.949065 ===================================
7295 00:44:26.949455 LPDDR4 DRAM CONFIGURATION
7296 00:44:26.951928 ===================================
7297 00:44:26.955380 EX_ROW_EN[0] = 0x10
7298 00:44:26.958660 EX_ROW_EN[1] = 0x0
7299 00:44:26.959052 LP4Y_EN = 0x0
7300 00:44:26.961989 WORK_FSP = 0x1
7301 00:44:26.962373 WL = 0x5
7302 00:44:26.965378 RL = 0x5
7303 00:44:26.965808 BL = 0x2
7304 00:44:26.968743 RPST = 0x0
7305 00:44:26.969103 RD_PRE = 0x0
7306 00:44:26.971785 WR_PRE = 0x1
7307 00:44:26.972293 WR_PST = 0x1
7308 00:44:26.975264 DBI_WR = 0x0
7309 00:44:26.975772 DBI_RD = 0x0
7310 00:44:26.978928 OTF = 0x1
7311 00:44:26.981746 ===================================
7312 00:44:26.988492 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7313 00:44:26.988964 ==
7314 00:44:26.991829 Dram Type= 6, Freq= 0, CH_0, rank 0
7315 00:44:26.995141 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7316 00:44:26.995649 ==
7317 00:44:26.998669 [Duty_Offset_Calibration]
7318 00:44:26.999186 B0:2 B1:0 CA:3
7319 00:44:26.999650
7320 00:44:27.001568 [DutyScan_Calibration_Flow] k_type=0
7321 00:44:27.012286
7322 00:44:27.012797 ==CLK 0==
7323 00:44:27.015580 Final CLK duty delay cell = 0
7324 00:44:27.019058 [0] MAX Duty = 5031%(X100), DQS PI = 12
7325 00:44:27.022555 [0] MIN Duty = 4907%(X100), DQS PI = 6
7326 00:44:27.023070 [0] AVG Duty = 4969%(X100)
7327 00:44:27.026053
7328 00:44:27.029269 CH0 CLK Duty spec in!! Max-Min= 124%
7329 00:44:27.032394 [DutyScan_Calibration_Flow] ====Done====
7330 00:44:27.032909
7331 00:44:27.035280 [DutyScan_Calibration_Flow] k_type=1
7332 00:44:27.052385
7333 00:44:27.052824 ==DQS 0 ==
7334 00:44:27.055715 Final DQS duty delay cell = 0
7335 00:44:27.058857 [0] MAX Duty = 5094%(X100), DQS PI = 30
7336 00:44:27.062211 [0] MIN Duty = 4875%(X100), DQS PI = 48
7337 00:44:27.065635 [0] AVG Duty = 4984%(X100)
7338 00:44:27.066020
7339 00:44:27.066312 ==DQS 1 ==
7340 00:44:27.069161 Final DQS duty delay cell = 0
7341 00:44:27.072023 [0] MAX Duty = 5156%(X100), DQS PI = 32
7342 00:44:27.075702 [0] MIN Duty = 5062%(X100), DQS PI = 0
7343 00:44:27.078812 [0] AVG Duty = 5109%(X100)
7344 00:44:27.079290
7345 00:44:27.081877 CH0 DQS 0 Duty spec in!! Max-Min= 219%
7346 00:44:27.082395
7347 00:44:27.085291 CH0 DQS 1 Duty spec in!! Max-Min= 94%
7348 00:44:27.088770 [DutyScan_Calibration_Flow] ====Done====
7349 00:44:27.089227
7350 00:44:27.091740 [DutyScan_Calibration_Flow] k_type=3
7351 00:44:27.110100
7352 00:44:27.110624 ==DQM 0 ==
7353 00:44:27.113453 Final DQM duty delay cell = 0
7354 00:44:27.116636 [0] MAX Duty = 5156%(X100), DQS PI = 30
7355 00:44:27.120270 [0] MIN Duty = 4875%(X100), DQS PI = 0
7356 00:44:27.123170 [0] AVG Duty = 5015%(X100)
7357 00:44:27.123639
7358 00:44:27.123948 ==DQM 1 ==
7359 00:44:27.126637 Final DQM duty delay cell = 4
7360 00:44:27.130209 [4] MAX Duty = 5156%(X100), DQS PI = 54
7361 00:44:27.133109 [4] MIN Duty = 5000%(X100), DQS PI = 14
7362 00:44:27.136512 [4] AVG Duty = 5078%(X100)
7363 00:44:27.136928
7364 00:44:27.139799 CH0 DQM 0 Duty spec in!! Max-Min= 281%
7365 00:44:27.140179
7366 00:44:27.143091 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7367 00:44:27.146666 [DutyScan_Calibration_Flow] ====Done====
7368 00:44:27.147043
7369 00:44:27.149656 [DutyScan_Calibration_Flow] k_type=2
7370 00:44:27.167016
7371 00:44:27.167392 ==DQ 0 ==
7372 00:44:27.169967 Final DQ duty delay cell = -4
7373 00:44:27.173135 [-4] MAX Duty = 5000%(X100), DQS PI = 18
7374 00:44:27.176422 [-4] MIN Duty = 4876%(X100), DQS PI = 0
7375 00:44:27.179800 [-4] AVG Duty = 4938%(X100)
7376 00:44:27.180245
7377 00:44:27.180569 ==DQ 1 ==
7378 00:44:27.182968 Final DQ duty delay cell = 0
7379 00:44:27.186326 [0] MAX Duty = 5156%(X100), DQS PI = 60
7380 00:44:27.189544 [0] MIN Duty = 5000%(X100), DQS PI = 16
7381 00:44:27.193397 [0] AVG Duty = 5078%(X100)
7382 00:44:27.193772
7383 00:44:27.196402 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7384 00:44:27.196913
7385 00:44:27.199544 CH0 DQ 1 Duty spec in!! Max-Min= 156%
7386 00:44:27.203029 [DutyScan_Calibration_Flow] ====Done====
7387 00:44:27.203429 ==
7388 00:44:27.206503 Dram Type= 6, Freq= 0, CH_1, rank 0
7389 00:44:27.209909 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7390 00:44:27.210291 ==
7391 00:44:27.213190 [Duty_Offset_Calibration]
7392 00:44:27.213617 B0:1 B1:-2 CA:1
7393 00:44:27.214088
7394 00:44:27.216284 [DutyScan_Calibration_Flow] k_type=0
7395 00:44:27.227334
7396 00:44:27.227808 ==CLK 0==
7397 00:44:27.230420 Final CLK duty delay cell = 0
7398 00:44:27.233786 [0] MAX Duty = 5062%(X100), DQS PI = 20
7399 00:44:27.237179 [0] MIN Duty = 4844%(X100), DQS PI = 4
7400 00:44:27.237602 [0] AVG Duty = 4953%(X100)
7401 00:44:27.240543
7402 00:44:27.243889 CH1 CLK Duty spec in!! Max-Min= 218%
7403 00:44:27.246808 [DutyScan_Calibration_Flow] ====Done====
7404 00:44:27.247285
7405 00:44:27.250376 [DutyScan_Calibration_Flow] k_type=1
7406 00:44:27.265979
7407 00:44:27.266375 ==DQS 0 ==
7408 00:44:27.269691 Final DQS duty delay cell = -4
7409 00:44:27.272745 [-4] MAX Duty = 4969%(X100), DQS PI = 26
7410 00:44:27.275805 [-4] MIN Duty = 4844%(X100), DQS PI = 0
7411 00:44:27.279540 [-4] AVG Duty = 4906%(X100)
7412 00:44:27.280194
7413 00:44:27.280748 ==DQS 1 ==
7414 00:44:27.282551 Final DQS duty delay cell = 0
7415 00:44:27.285987 [0] MAX Duty = 5093%(X100), DQS PI = 62
7416 00:44:27.289588 [0] MIN Duty = 4844%(X100), DQS PI = 26
7417 00:44:27.292976 [0] AVG Duty = 4968%(X100)
7418 00:44:27.293357
7419 00:44:27.296313 CH1 DQS 0 Duty spec in!! Max-Min= 125%
7420 00:44:27.296815
7421 00:44:27.299051 CH1 DQS 1 Duty spec in!! Max-Min= 249%
7422 00:44:27.302844 [DutyScan_Calibration_Flow] ====Done====
7423 00:44:27.303250
7424 00:44:27.306022 [DutyScan_Calibration_Flow] k_type=3
7425 00:44:27.323209
7426 00:44:27.323638 ==DQM 0 ==
7427 00:44:27.326711 Final DQM duty delay cell = 0
7428 00:44:27.330034 [0] MAX Duty = 5031%(X100), DQS PI = 26
7429 00:44:27.333152 [0] MIN Duty = 4813%(X100), DQS PI = 54
7430 00:44:27.336471 [0] AVG Duty = 4922%(X100)
7431 00:44:27.337218
7432 00:44:27.337622 ==DQM 1 ==
7433 00:44:27.339667 Final DQM duty delay cell = 0
7434 00:44:27.342934 [0] MAX Duty = 5062%(X100), DQS PI = 34
7435 00:44:27.346508 [0] MIN Duty = 4875%(X100), DQS PI = 24
7436 00:44:27.349895 [0] AVG Duty = 4968%(X100)
7437 00:44:27.350386
7438 00:44:27.353449 CH1 DQM 0 Duty spec in!! Max-Min= 218%
7439 00:44:27.353911
7440 00:44:27.356289 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7441 00:44:27.359790 [DutyScan_Calibration_Flow] ====Done====
7442 00:44:27.360496
7443 00:44:27.362778 [DutyScan_Calibration_Flow] k_type=2
7444 00:44:27.380077
7445 00:44:27.380509 ==DQ 0 ==
7446 00:44:27.383403 Final DQ duty delay cell = 0
7447 00:44:27.386661 [0] MAX Duty = 5093%(X100), DQS PI = 22
7448 00:44:27.390303 [0] MIN Duty = 4938%(X100), DQS PI = 0
7449 00:44:27.390813 [0] AVG Duty = 5015%(X100)
7450 00:44:27.393409
7451 00:44:27.393792 ==DQ 1 ==
7452 00:44:27.396848 Final DQ duty delay cell = 0
7453 00:44:27.400046 [0] MAX Duty = 5125%(X100), DQS PI = 34
7454 00:44:27.403584 [0] MIN Duty = 4969%(X100), DQS PI = 24
7455 00:44:27.403971 [0] AVG Duty = 5047%(X100)
7456 00:44:27.406924
7457 00:44:27.410184 CH1 DQ 0 Duty spec in!! Max-Min= 155%
7458 00:44:27.410567
7459 00:44:27.413564 CH1 DQ 1 Duty spec in!! Max-Min= 156%
7460 00:44:27.416518 [DutyScan_Calibration_Flow] ====Done====
7461 00:44:27.419719 nWR fixed to 30
7462 00:44:27.420102 [ModeRegInit_LP4] CH0 RK0
7463 00:44:27.423371 [ModeRegInit_LP4] CH0 RK1
7464 00:44:27.426545 [ModeRegInit_LP4] CH1 RK0
7465 00:44:27.430143 [ModeRegInit_LP4] CH1 RK1
7466 00:44:27.430525 match AC timing 5
7467 00:44:27.436427 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7468 00:44:27.439780 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7469 00:44:27.443029 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7470 00:44:27.449722 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7471 00:44:27.453080 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7472 00:44:27.453466 [MiockJmeterHQA]
7473 00:44:27.453766
7474 00:44:27.456443 [DramcMiockJmeter] u1RxGatingPI = 0
7475 00:44:27.459447 0 : 4363, 4138
7476 00:44:27.459835 4 : 4252, 4027
7477 00:44:27.462986 8 : 4363, 4137
7478 00:44:27.463376 12 : 4363, 4137
7479 00:44:27.463682 16 : 4252, 4027
7480 00:44:27.466409 20 : 4252, 4027
7481 00:44:27.466797 24 : 4253, 4027
7482 00:44:27.469802 28 : 4253, 4026
7483 00:44:27.470190 32 : 4252, 4027
7484 00:44:27.473337 36 : 4252, 4027
7485 00:44:27.473730 40 : 4363, 4137
7486 00:44:27.474035 44 : 4252, 4027
7487 00:44:27.476666 48 : 4253, 4026
7488 00:44:27.477064 52 : 4252, 4027
7489 00:44:27.479758 56 : 4253, 4027
7490 00:44:27.480148 60 : 4252, 4027
7491 00:44:27.482848 64 : 4361, 4138
7492 00:44:27.483240 68 : 4361, 4137
7493 00:44:27.486085 72 : 4250, 4027
7494 00:44:27.486475 76 : 4249, 4027
7495 00:44:27.486794 80 : 4250, 4027
7496 00:44:27.489321 84 : 4250, 4027
7497 00:44:27.489714 88 : 4250, 4026
7498 00:44:27.492769 92 : 4360, 4138
7499 00:44:27.493200 96 : 4249, 4027
7500 00:44:27.496570 100 : 4250, 4027
7501 00:44:27.497077 104 : 4360, 3612
7502 00:44:27.499281 108 : 4250, 2
7503 00:44:27.499669 112 : 4253, 0
7504 00:44:27.499980 116 : 4253, 0
7505 00:44:27.503064 120 : 4250, 0
7506 00:44:27.503522 124 : 4361, 0
7507 00:44:27.503831 128 : 4250, 0
7508 00:44:27.506393 132 : 4360, 0
7509 00:44:27.506783 136 : 4250, 0
7510 00:44:27.509760 140 : 4361, 0
7511 00:44:27.510151 144 : 4250, 0
7512 00:44:27.510452 148 : 4250, 0
7513 00:44:27.512759 152 : 4250, 0
7514 00:44:27.513234 156 : 4252, 0
7515 00:44:27.516298 160 : 4250, 0
7516 00:44:27.516723 164 : 4250, 0
7517 00:44:27.517040 168 : 4253, 0
7518 00:44:27.519628 172 : 4360, 0
7519 00:44:27.520017 176 : 4361, 0
7520 00:44:27.522602 180 : 4250, 0
7521 00:44:27.522995 184 : 4360, 0
7522 00:44:27.523299 188 : 4360, 0
7523 00:44:27.526072 192 : 4250, 0
7524 00:44:27.526461 196 : 4249, 0
7525 00:44:27.526768 200 : 4249, 0
7526 00:44:27.529593 204 : 4250, 0
7527 00:44:27.530045 208 : 4250, 0
7528 00:44:27.532551 212 : 4250, 0
7529 00:44:27.532980 216 : 4250, 0
7530 00:44:27.533286 220 : 4250, 0
7531 00:44:27.536199 224 : 4360, 0
7532 00:44:27.536813 228 : 4361, 0
7533 00:44:27.539442 232 : 4360, 0
7534 00:44:27.539830 236 : 4249, 960
7535 00:44:27.542834 240 : 4250, 4027
7536 00:44:27.543222 244 : 4361, 4137
7537 00:44:27.543527 248 : 4250, 4026
7538 00:44:27.546312 252 : 4249, 4027
7539 00:44:27.546704 256 : 4360, 4138
7540 00:44:27.549466 260 : 4250, 4026
7541 00:44:27.549859 264 : 4250, 4027
7542 00:44:27.552764 268 : 4249, 4027
7543 00:44:27.553156 272 : 4252, 4029
7544 00:44:27.555820 276 : 4250, 4026
7545 00:44:27.556212 280 : 4250, 4027
7546 00:44:27.559448 284 : 4360, 4138
7547 00:44:27.559837 288 : 4250, 4027
7548 00:44:27.562341 292 : 4250, 4027
7549 00:44:27.562733 296 : 4361, 4137
7550 00:44:27.565757 300 : 4250, 4027
7551 00:44:27.566149 304 : 4250, 4027
7552 00:44:27.569321 308 : 4363, 4140
7553 00:44:27.569708 312 : 4250, 4027
7554 00:44:27.570011 316 : 4250, 4027
7555 00:44:27.572533 320 : 4252, 4027
7556 00:44:27.572964 324 : 4252, 4029
7557 00:44:27.576043 328 : 4250, 4027
7558 00:44:27.576432 332 : 4250, 4027
7559 00:44:27.579572 336 : 4363, 4138
7560 00:44:27.580016 340 : 4250, 4027
7561 00:44:27.582481 344 : 4250, 4027
7562 00:44:27.582874 348 : 4360, 4138
7563 00:44:27.585847 352 : 4250, 4023
7564 00:44:27.586239 356 : 4249, 2587
7565 00:44:27.589459 360 : 4363, 2
7566 00:44:27.589850
7567 00:44:27.590149 MIOCK jitter meter ch=0
7568 00:44:27.590424
7569 00:44:27.592702 1T = (360-108) = 252 dly cells
7570 00:44:27.599344 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 258/100 ps
7571 00:44:27.599735 ==
7572 00:44:27.602620 Dram Type= 6, Freq= 0, CH_0, rank 0
7573 00:44:27.605805 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7574 00:44:27.606193 ==
7575 00:44:27.612509 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7576 00:44:27.615718 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7577 00:44:27.619014 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7578 00:44:27.625855 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7579 00:44:27.635038 [CA 0] Center 44 (14~75) winsize 62
7580 00:44:27.638399 [CA 1] Center 43 (13~74) winsize 62
7581 00:44:27.641638 [CA 2] Center 39 (10~69) winsize 60
7582 00:44:27.645091 [CA 3] Center 39 (10~68) winsize 59
7583 00:44:27.648556 [CA 4] Center 37 (8~67) winsize 60
7584 00:44:27.652000 [CA 5] Center 37 (7~67) winsize 61
7585 00:44:27.652568
7586 00:44:27.654973 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7587 00:44:27.655468
7588 00:44:27.661246 [CATrainingPosCal] consider 1 rank data
7589 00:44:27.661629 u2DelayCellTimex100 = 258/100 ps
7590 00:44:27.667936 CA0 delay=44 (14~75),Diff = 7 PI (26 cell)
7591 00:44:27.671424 CA1 delay=43 (13~74),Diff = 6 PI (22 cell)
7592 00:44:27.674811 CA2 delay=39 (10~69),Diff = 2 PI (7 cell)
7593 00:44:27.678093 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7594 00:44:27.681217 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7595 00:44:27.684686 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7596 00:44:27.685181
7597 00:44:27.688201 CA PerBit enable=1, Macro0, CA PI delay=37
7598 00:44:27.688589
7599 00:44:27.691017 [CBTSetCACLKResult] CA Dly = 37
7600 00:44:27.694396 CS Dly: 11 (0~42)
7601 00:44:27.697677 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7602 00:44:27.701203 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7603 00:44:27.701624 ==
7604 00:44:27.704628 Dram Type= 6, Freq= 0, CH_0, rank 1
7605 00:44:27.711340 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7606 00:44:27.711783 ==
7607 00:44:27.714711 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7608 00:44:27.720525 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7609 00:44:27.723816 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7610 00:44:27.730674 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7611 00:44:27.738596 [CA 0] Center 44 (14~75) winsize 62
7612 00:44:27.742018 [CA 1] Center 43 (13~74) winsize 62
7613 00:44:27.744910 [CA 2] Center 39 (10~69) winsize 60
7614 00:44:27.748183 [CA 3] Center 39 (10~69) winsize 60
7615 00:44:27.752134 [CA 4] Center 37 (8~67) winsize 60
7616 00:44:27.755017 [CA 5] Center 37 (7~67) winsize 61
7617 00:44:27.755083
7618 00:44:27.759113 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7619 00:44:27.759570
7620 00:44:27.762502 [CATrainingPosCal] consider 2 rank data
7621 00:44:27.765641 u2DelayCellTimex100 = 258/100 ps
7622 00:44:27.768927 CA0 delay=44 (14~75),Diff = 7 PI (26 cell)
7623 00:44:27.775353 CA1 delay=43 (13~74),Diff = 6 PI (22 cell)
7624 00:44:27.778771 CA2 delay=39 (10~69),Diff = 2 PI (7 cell)
7625 00:44:27.782345 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7626 00:44:27.785194 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7627 00:44:27.789088 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7628 00:44:27.789521
7629 00:44:27.792464 CA PerBit enable=1, Macro0, CA PI delay=37
7630 00:44:27.792887
7631 00:44:27.795347 [CBTSetCACLKResult] CA Dly = 37
7632 00:44:27.798661 CS Dly: 11 (0~43)
7633 00:44:27.801939 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7634 00:44:27.805127 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7635 00:44:27.805523
7636 00:44:27.808935 ----->DramcWriteLeveling(PI) begin...
7637 00:44:27.809373 ==
7638 00:44:27.811934 Dram Type= 6, Freq= 0, CH_0, rank 0
7639 00:44:27.818756 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7640 00:44:27.819193 ==
7641 00:44:27.821883 Write leveling (Byte 0): 35 => 35
7642 00:44:27.822384 Write leveling (Byte 1): 30 => 30
7643 00:44:27.825068 DramcWriteLeveling(PI) end<-----
7644 00:44:27.825611
7645 00:44:27.828503 ==
7646 00:44:27.829061 Dram Type= 6, Freq= 0, CH_0, rank 0
7647 00:44:27.834865 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7648 00:44:27.835343 ==
7649 00:44:27.838523 [Gating] SW mode calibration
7650 00:44:27.844953 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7651 00:44:27.848282 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7652 00:44:27.855193 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7653 00:44:27.858349 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7654 00:44:27.861854 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7655 00:44:27.868241 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7656 00:44:27.871645 1 4 16 | B1->B0 | 2323 2929 | 0 1 | (0 0) (1 1)
7657 00:44:27.875097 1 4 20 | B1->B0 | 2323 3434 | 1 0 | (0 0) (0 0)
7658 00:44:27.881282 1 4 24 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
7659 00:44:27.884600 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7660 00:44:27.887994 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7661 00:44:27.895000 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7662 00:44:27.897788 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7663 00:44:27.901130 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7664 00:44:27.907846 1 5 16 | B1->B0 | 3434 2d2d | 1 0 | (1 1) (0 0)
7665 00:44:27.910981 1 5 20 | B1->B0 | 3030 2323 | 0 0 | (0 0) (0 0)
7666 00:44:27.914571 1 5 24 | B1->B0 | 2929 2323 | 1 0 | (0 0) (0 0)
7667 00:44:27.921127 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7668 00:44:27.924488 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7669 00:44:27.927893 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7670 00:44:27.934404 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7671 00:44:27.937829 1 6 12 | B1->B0 | 2323 2525 | 0 0 | (0 0) (1 1)
7672 00:44:27.941265 1 6 16 | B1->B0 | 2323 4242 | 0 0 | (0 0) (0 0)
7673 00:44:27.947606 1 6 20 | B1->B0 | 2525 4646 | 0 0 | (0 0) (0 0)
7674 00:44:27.951042 1 6 24 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
7675 00:44:27.954557 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7676 00:44:27.960815 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7677 00:44:27.964755 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7678 00:44:27.967460 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7679 00:44:27.974162 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7680 00:44:27.977419 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7681 00:44:27.980949 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7682 00:44:27.984197 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7683 00:44:27.990624 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7684 00:44:27.994328 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7685 00:44:27.997612 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7686 00:44:28.003781 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7687 00:44:28.007379 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7688 00:44:28.010788 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7689 00:44:28.017263 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7690 00:44:28.020821 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7691 00:44:28.023913 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7692 00:44:28.030490 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7693 00:44:28.034004 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7694 00:44:28.036698 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7695 00:44:28.043438 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7696 00:44:28.047237 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7697 00:44:28.050351 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7698 00:44:28.053438 Total UI for P1: 0, mck2ui 16
7699 00:44:28.057363 best dqsien dly found for B0: ( 1, 9, 14)
7700 00:44:28.063384 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7701 00:44:28.066657 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7702 00:44:28.070524 Total UI for P1: 0, mck2ui 16
7703 00:44:28.073380 best dqsien dly found for B1: ( 1, 9, 22)
7704 00:44:28.076963 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
7705 00:44:28.080473 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7706 00:44:28.080943
7707 00:44:28.083856 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
7708 00:44:28.086826 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7709 00:44:28.090399 [Gating] SW calibration Done
7710 00:44:28.090782 ==
7711 00:44:28.093669 Dram Type= 6, Freq= 0, CH_0, rank 0
7712 00:44:28.100492 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7713 00:44:28.100977 ==
7714 00:44:28.101367 RX Vref Scan: 0
7715 00:44:28.101765
7716 00:44:28.103634 RX Vref 0 -> 0, step: 1
7717 00:44:28.104177
7718 00:44:28.107221 RX Delay 0 -> 252, step: 8
7719 00:44:28.110076 iDelay=192, Bit 0, Center 127 (72 ~ 183) 112
7720 00:44:28.113653 iDelay=192, Bit 1, Center 131 (80 ~ 183) 104
7721 00:44:28.116919 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7722 00:44:28.120313 iDelay=192, Bit 3, Center 123 (72 ~ 175) 104
7723 00:44:28.126659 iDelay=192, Bit 4, Center 127 (72 ~ 183) 112
7724 00:44:28.129922 iDelay=192, Bit 5, Center 111 (56 ~ 167) 112
7725 00:44:28.133626 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
7726 00:44:28.136677 iDelay=192, Bit 7, Center 139 (88 ~ 191) 104
7727 00:44:28.140155 iDelay=192, Bit 8, Center 115 (56 ~ 175) 120
7728 00:44:28.146458 iDelay=192, Bit 9, Center 111 (56 ~ 167) 112
7729 00:44:28.149712 iDelay=192, Bit 10, Center 123 (64 ~ 183) 120
7730 00:44:28.153028 iDelay=192, Bit 11, Center 119 (64 ~ 175) 112
7731 00:44:28.156632 iDelay=192, Bit 12, Center 127 (72 ~ 183) 112
7732 00:44:28.159879 iDelay=192, Bit 13, Center 131 (72 ~ 191) 120
7733 00:44:28.166293 iDelay=192, Bit 14, Center 135 (80 ~ 191) 112
7734 00:44:28.169831 iDelay=192, Bit 15, Center 131 (72 ~ 191) 120
7735 00:44:28.170197 ==
7736 00:44:28.173126 Dram Type= 6, Freq= 0, CH_0, rank 0
7737 00:44:28.176565 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7738 00:44:28.176877 ==
7739 00:44:28.179746 DQS Delay:
7740 00:44:28.180033 DQS0 = 0, DQS1 = 0
7741 00:44:28.180327 DQM Delay:
7742 00:44:28.183273 DQM0 = 128, DQM1 = 124
7743 00:44:28.183559 DQ Delay:
7744 00:44:28.186095 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =123
7745 00:44:28.189394 DQ4 =127, DQ5 =111, DQ6 =139, DQ7 =139
7746 00:44:28.196017 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =119
7747 00:44:28.199640 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =131
7748 00:44:28.200011
7749 00:44:28.200311
7750 00:44:28.200581 ==
7751 00:44:28.202838 Dram Type= 6, Freq= 0, CH_0, rank 0
7752 00:44:28.206087 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7753 00:44:28.206377 ==
7754 00:44:28.206664
7755 00:44:28.206931
7756 00:44:28.209321 TX Vref Scan disable
7757 00:44:28.209608 == TX Byte 0 ==
7758 00:44:28.216232 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7759 00:44:28.219691 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7760 00:44:28.219992 == TX Byte 1 ==
7761 00:44:28.226408 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
7762 00:44:28.229647 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7763 00:44:28.230022 ==
7764 00:44:28.232434 Dram Type= 6, Freq= 0, CH_0, rank 0
7765 00:44:28.235922 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7766 00:44:28.236293 ==
7767 00:44:28.249858
7768 00:44:28.253019 TX Vref early break, caculate TX vref
7769 00:44:28.256404 TX Vref=16, minBit 4, minWin=21, winSum=362
7770 00:44:28.259673 TX Vref=18, minBit 0, minWin=23, winSum=376
7771 00:44:28.262823 TX Vref=20, minBit 13, minWin=23, winSum=388
7772 00:44:28.266162 TX Vref=22, minBit 0, minWin=24, winSum=396
7773 00:44:28.269642 TX Vref=24, minBit 1, minWin=24, winSum=404
7774 00:44:28.276163 TX Vref=26, minBit 2, minWin=25, winSum=414
7775 00:44:28.279562 TX Vref=28, minBit 2, minWin=25, winSum=418
7776 00:44:28.283111 TX Vref=30, minBit 7, minWin=24, winSum=405
7777 00:44:28.285859 TX Vref=32, minBit 7, minWin=24, winSum=396
7778 00:44:28.292578 [TxChooseVref] Worse bit 2, Min win 25, Win sum 418, Final Vref 28
7779 00:44:28.293144
7780 00:44:28.296322 Final TX Range 0 Vref 28
7781 00:44:28.296913
7782 00:44:28.297355 ==
7783 00:44:28.298783 Dram Type= 6, Freq= 0, CH_0, rank 0
7784 00:44:28.302784 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7785 00:44:28.303249 ==
7786 00:44:28.303688
7787 00:44:28.304100
7788 00:44:28.305673 TX Vref Scan disable
7789 00:44:28.312939 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
7790 00:44:28.313481 == TX Byte 0 ==
7791 00:44:28.315582 u2DelayCellOfst[0]=11 cells (3 PI)
7792 00:44:28.318781 u2DelayCellOfst[1]=18 cells (5 PI)
7793 00:44:28.322374 u2DelayCellOfst[2]=11 cells (3 PI)
7794 00:44:28.325593 u2DelayCellOfst[3]=11 cells (3 PI)
7795 00:44:28.329305 u2DelayCellOfst[4]=11 cells (3 PI)
7796 00:44:28.332001 u2DelayCellOfst[5]=0 cells (0 PI)
7797 00:44:28.335688 u2DelayCellOfst[6]=22 cells (6 PI)
7798 00:44:28.338951 u2DelayCellOfst[7]=18 cells (5 PI)
7799 00:44:28.342030 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7800 00:44:28.345530 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7801 00:44:28.348917 == TX Byte 1 ==
7802 00:44:28.349372 u2DelayCellOfst[8]=0 cells (0 PI)
7803 00:44:28.352298 u2DelayCellOfst[9]=0 cells (0 PI)
7804 00:44:28.355154 u2DelayCellOfst[10]=3 cells (1 PI)
7805 00:44:28.358677 u2DelayCellOfst[11]=0 cells (0 PI)
7806 00:44:28.361869 u2DelayCellOfst[12]=11 cells (3 PI)
7807 00:44:28.365314 u2DelayCellOfst[13]=7 cells (2 PI)
7808 00:44:28.369004 u2DelayCellOfst[14]=15 cells (4 PI)
7809 00:44:28.372058 u2DelayCellOfst[15]=7 cells (2 PI)
7810 00:44:28.375341 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7811 00:44:28.381822 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7812 00:44:28.382253 DramC Write-DBI on
7813 00:44:28.382583 ==
7814 00:44:28.385295 Dram Type= 6, Freq= 0, CH_0, rank 0
7815 00:44:28.388453 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7816 00:44:28.392210 ==
7817 00:44:28.392824
7818 00:44:28.393200
7819 00:44:28.393529 TX Vref Scan disable
7820 00:44:28.395342 == TX Byte 0 ==
7821 00:44:28.398684 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
7822 00:44:28.401677 == TX Byte 1 ==
7823 00:44:28.404970 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
7824 00:44:28.407672 DramC Write-DBI off
7825 00:44:28.407748
7826 00:44:28.407807 [DATLAT]
7827 00:44:28.407862 Freq=1600, CH0 RK0
7828 00:44:28.407915
7829 00:44:28.411181 DATLAT Default: 0xf
7830 00:44:28.411258 0, 0xFFFF, sum = 0
7831 00:44:28.414677 1, 0xFFFF, sum = 0
7832 00:44:28.417663 2, 0xFFFF, sum = 0
7833 00:44:28.417740 3, 0xFFFF, sum = 0
7834 00:44:28.420981 4, 0xFFFF, sum = 0
7835 00:44:28.421059 5, 0xFFFF, sum = 0
7836 00:44:28.424380 6, 0xFFFF, sum = 0
7837 00:44:28.424458 7, 0xFFFF, sum = 0
7838 00:44:28.427668 8, 0xFFFF, sum = 0
7839 00:44:28.427745 9, 0xFFFF, sum = 0
7840 00:44:28.430950 10, 0xFFFF, sum = 0
7841 00:44:28.431028 11, 0xFFFF, sum = 0
7842 00:44:28.434313 12, 0xFFFF, sum = 0
7843 00:44:28.434390 13, 0xEFFF, sum = 0
7844 00:44:28.437671 14, 0x0, sum = 1
7845 00:44:28.437754 15, 0x0, sum = 2
7846 00:44:28.441018 16, 0x0, sum = 3
7847 00:44:28.441102 17, 0x0, sum = 4
7848 00:44:28.444497 best_step = 15
7849 00:44:28.444584
7850 00:44:28.444661 ==
7851 00:44:28.447578 Dram Type= 6, Freq= 0, CH_0, rank 0
7852 00:44:28.450916 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7853 00:44:28.451025 ==
7854 00:44:28.454242 RX Vref Scan: 1
7855 00:44:28.454348
7856 00:44:28.454436 Set Vref Range= 24 -> 127
7857 00:44:28.454512
7858 00:44:28.457548 RX Vref 24 -> 127, step: 1
7859 00:44:28.457660
7860 00:44:28.460893 RX Delay 11 -> 252, step: 4
7861 00:44:28.460986
7862 00:44:28.464078 Set Vref, RX VrefLevel [Byte0]: 24
7863 00:44:28.467654 [Byte1]: 24
7864 00:44:28.467786
7865 00:44:28.470917 Set Vref, RX VrefLevel [Byte0]: 25
7866 00:44:28.474461 [Byte1]: 25
7867 00:44:28.477583
7868 00:44:28.477745 Set Vref, RX VrefLevel [Byte0]: 26
7869 00:44:28.481121 [Byte1]: 26
7870 00:44:28.485414
7871 00:44:28.485790 Set Vref, RX VrefLevel [Byte0]: 27
7872 00:44:28.489038 [Byte1]: 27
7873 00:44:28.493118
7874 00:44:28.493538 Set Vref, RX VrefLevel [Byte0]: 28
7875 00:44:28.496551 [Byte1]: 28
7876 00:44:28.500740
7877 00:44:28.501138 Set Vref, RX VrefLevel [Byte0]: 29
7878 00:44:28.504075 [Byte1]: 29
7879 00:44:28.508409
7880 00:44:28.508970 Set Vref, RX VrefLevel [Byte0]: 30
7881 00:44:28.511550 [Byte1]: 30
7882 00:44:28.516071
7883 00:44:28.516673 Set Vref, RX VrefLevel [Byte0]: 31
7884 00:44:28.519595 [Byte1]: 31
7885 00:44:28.523496
7886 00:44:28.523885 Set Vref, RX VrefLevel [Byte0]: 32
7887 00:44:28.527279 [Byte1]: 32
7888 00:44:28.531457
7889 00:44:28.531907 Set Vref, RX VrefLevel [Byte0]: 33
7890 00:44:28.534696 [Byte1]: 33
7891 00:44:28.538933
7892 00:44:28.539365 Set Vref, RX VrefLevel [Byte0]: 34
7893 00:44:28.542317 [Byte1]: 34
7894 00:44:28.546423
7895 00:44:28.546857 Set Vref, RX VrefLevel [Byte0]: 35
7896 00:44:28.549432 [Byte1]: 35
7897 00:44:28.554062
7898 00:44:28.554450 Set Vref, RX VrefLevel [Byte0]: 36
7899 00:44:28.557068 [Byte1]: 36
7900 00:44:28.561515
7901 00:44:28.561946 Set Vref, RX VrefLevel [Byte0]: 37
7902 00:44:28.564743 [Byte1]: 37
7903 00:44:28.569270
7904 00:44:28.569701 Set Vref, RX VrefLevel [Byte0]: 38
7905 00:44:28.572524 [Byte1]: 38
7906 00:44:28.576707
7907 00:44:28.577219 Set Vref, RX VrefLevel [Byte0]: 39
7908 00:44:28.580254 [Byte1]: 39
7909 00:44:28.584740
7910 00:44:28.585166 Set Vref, RX VrefLevel [Byte0]: 40
7911 00:44:28.587770 [Byte1]: 40
7912 00:44:28.592621
7913 00:44:28.593254 Set Vref, RX VrefLevel [Byte0]: 41
7914 00:44:28.595651 [Byte1]: 41
7915 00:44:28.599815
7916 00:44:28.600236 Set Vref, RX VrefLevel [Byte0]: 42
7917 00:44:28.603176 [Byte1]: 42
7918 00:44:28.607342
7919 00:44:28.607726 Set Vref, RX VrefLevel [Byte0]: 43
7920 00:44:28.610891 [Byte1]: 43
7921 00:44:28.614982
7922 00:44:28.615362 Set Vref, RX VrefLevel [Byte0]: 44
7923 00:44:28.618190 [Byte1]: 44
7924 00:44:28.622589
7925 00:44:28.623065 Set Vref, RX VrefLevel [Byte0]: 45
7926 00:44:28.626132 [Byte1]: 45
7927 00:44:28.630173
7928 00:44:28.630555 Set Vref, RX VrefLevel [Byte0]: 46
7929 00:44:28.633725 [Byte1]: 46
7930 00:44:28.637704
7931 00:44:28.638134 Set Vref, RX VrefLevel [Byte0]: 47
7932 00:44:28.640944 [Byte1]: 47
7933 00:44:28.645289
7934 00:44:28.645733 Set Vref, RX VrefLevel [Byte0]: 48
7935 00:44:28.648755 [Byte1]: 48
7936 00:44:28.653340
7937 00:44:28.653767 Set Vref, RX VrefLevel [Byte0]: 49
7938 00:44:28.656553 [Byte1]: 49
7939 00:44:28.660841
7940 00:44:28.661266 Set Vref, RX VrefLevel [Byte0]: 50
7941 00:44:28.663776 [Byte1]: 50
7942 00:44:28.668119
7943 00:44:28.668563 Set Vref, RX VrefLevel [Byte0]: 51
7944 00:44:28.671541 [Byte1]: 51
7945 00:44:28.675612
7946 00:44:28.676116 Set Vref, RX VrefLevel [Byte0]: 52
7947 00:44:28.678954 [Byte1]: 52
7948 00:44:28.683529
7949 00:44:28.684019 Set Vref, RX VrefLevel [Byte0]: 53
7950 00:44:28.686411 [Byte1]: 53
7951 00:44:28.691233
7952 00:44:28.691793 Set Vref, RX VrefLevel [Byte0]: 54
7953 00:44:28.694259 [Byte1]: 54
7954 00:44:28.698963
7955 00:44:28.699590 Set Vref, RX VrefLevel [Byte0]: 55
7956 00:44:28.701914 [Byte1]: 55
7957 00:44:28.706374
7958 00:44:28.706835 Set Vref, RX VrefLevel [Byte0]: 56
7959 00:44:28.709876 [Byte1]: 56
7960 00:44:28.713827
7961 00:44:28.714230 Set Vref, RX VrefLevel [Byte0]: 57
7962 00:44:28.717240 [Byte1]: 57
7963 00:44:28.721744
7964 00:44:28.722198 Set Vref, RX VrefLevel [Byte0]: 58
7965 00:44:28.724611 [Byte1]: 58
7966 00:44:28.728893
7967 00:44:28.729244 Set Vref, RX VrefLevel [Byte0]: 59
7968 00:44:28.732241 [Byte1]: 59
7969 00:44:28.736977
7970 00:44:28.737286 Set Vref, RX VrefLevel [Byte0]: 60
7971 00:44:28.740240 [Byte1]: 60
7972 00:44:28.744284
7973 00:44:28.744816 Set Vref, RX VrefLevel [Byte0]: 61
7974 00:44:28.747657 [Byte1]: 61
7975 00:44:28.751974
7976 00:44:28.752509 Set Vref, RX VrefLevel [Byte0]: 62
7977 00:44:28.755096 [Byte1]: 62
7978 00:44:28.759774
7979 00:44:28.760202 Set Vref, RX VrefLevel [Byte0]: 63
7980 00:44:28.763237 [Byte1]: 63
7981 00:44:28.767166
7982 00:44:28.767730 Set Vref, RX VrefLevel [Byte0]: 64
7983 00:44:28.770599 [Byte1]: 64
7984 00:44:28.774505
7985 00:44:28.774964 Set Vref, RX VrefLevel [Byte0]: 65
7986 00:44:28.777777 [Byte1]: 65
7987 00:44:28.782586
7988 00:44:28.782981 Set Vref, RX VrefLevel [Byte0]: 66
7989 00:44:28.785344 [Byte1]: 66
7990 00:44:28.790046
7991 00:44:28.790488 Set Vref, RX VrefLevel [Byte0]: 67
7992 00:44:28.793343 [Byte1]: 67
7993 00:44:28.797583
7994 00:44:28.797966 Set Vref, RX VrefLevel [Byte0]: 68
7995 00:44:28.800951 [Byte1]: 68
7996 00:44:28.805239
7997 00:44:28.805656 Set Vref, RX VrefLevel [Byte0]: 69
7998 00:44:28.808479 [Byte1]: 69
7999 00:44:28.812601
8000 00:44:28.813042 Set Vref, RX VrefLevel [Byte0]: 70
8001 00:44:28.816042 [Byte1]: 70
8002 00:44:28.820739
8003 00:44:28.821130 Set Vref, RX VrefLevel [Byte0]: 71
8004 00:44:28.823479 [Byte1]: 71
8005 00:44:28.828138
8006 00:44:28.828764 Set Vref, RX VrefLevel [Byte0]: 72
8007 00:44:28.831623 [Byte1]: 72
8008 00:44:28.836009
8009 00:44:28.836391 Set Vref, RX VrefLevel [Byte0]: 73
8010 00:44:28.838815 [Byte1]: 73
8011 00:44:28.843099
8012 00:44:28.843514 Set Vref, RX VrefLevel [Byte0]: 74
8013 00:44:28.846637 [Byte1]: 74
8014 00:44:28.851161
8015 00:44:28.851603 Set Vref, RX VrefLevel [Byte0]: 75
8016 00:44:28.854120 [Byte1]: 75
8017 00:44:28.858392
8018 00:44:28.858779 Set Vref, RX VrefLevel [Byte0]: 76
8019 00:44:28.861838 [Byte1]: 76
8020 00:44:28.865893
8021 00:44:28.866431 Set Vref, RX VrefLevel [Byte0]: 77
8022 00:44:28.869291 [Byte1]: 77
8023 00:44:28.873795
8024 00:44:28.874182 Final RX Vref Byte 0 = 65 to rank0
8025 00:44:28.877278 Final RX Vref Byte 1 = 60 to rank0
8026 00:44:28.880589 Final RX Vref Byte 0 = 65 to rank1
8027 00:44:28.883886 Final RX Vref Byte 1 = 60 to rank1==
8028 00:44:28.886817 Dram Type= 6, Freq= 0, CH_0, rank 0
8029 00:44:28.893540 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8030 00:44:28.894067 ==
8031 00:44:28.894534 DQS Delay:
8032 00:44:28.896662 DQS0 = 0, DQS1 = 0
8033 00:44:28.896994 DQM Delay:
8034 00:44:28.897269 DQM0 = 126, DQM1 = 119
8035 00:44:28.899965 DQ Delay:
8036 00:44:28.903281 DQ0 =126, DQ1 =128, DQ2 =126, DQ3 =122
8037 00:44:28.906762 DQ4 =126, DQ5 =114, DQ6 =134, DQ7 =138
8038 00:44:28.910265 DQ8 =112, DQ9 =106, DQ10 =120, DQ11 =114
8039 00:44:28.913530 DQ12 =124, DQ13 =124, DQ14 =130, DQ15 =126
8040 00:44:28.913922
8041 00:44:28.914228
8042 00:44:28.914508
8043 00:44:28.916684 [DramC_TX_OE_Calibration] TA2
8044 00:44:28.920240 Original DQ_B0 (3 6) =30, OEN = 27
8045 00:44:28.923396 Original DQ_B1 (3 6) =30, OEN = 27
8046 00:44:28.927103 24, 0x0, End_B0=24 End_B1=24
8047 00:44:28.927501 25, 0x0, End_B0=25 End_B1=25
8048 00:44:28.930332 26, 0x0, End_B0=26 End_B1=26
8049 00:44:28.933061 27, 0x0, End_B0=27 End_B1=27
8050 00:44:28.936420 28, 0x0, End_B0=28 End_B1=28
8051 00:44:28.939741 29, 0x0, End_B0=29 End_B1=29
8052 00:44:28.940139 30, 0x0, End_B0=30 End_B1=30
8053 00:44:28.943236 31, 0x4141, End_B0=30 End_B1=30
8054 00:44:28.946824 Byte0 end_step=30 best_step=27
8055 00:44:28.950102 Byte1 end_step=30 best_step=27
8056 00:44:28.953198 Byte0 TX OE(2T, 0.5T) = (3, 3)
8057 00:44:28.956795 Byte1 TX OE(2T, 0.5T) = (3, 3)
8058 00:44:28.957220
8059 00:44:28.957533
8060 00:44:28.963342 [DQSOSCAuto] RK0, (LSB)MR18= 0x1514, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 399 ps
8061 00:44:28.966865 CH0 RK0: MR19=303, MR18=1514
8062 00:44:28.973015 CH0_RK0: MR19=0x303, MR18=0x1514, DQSOSC=399, MR23=63, INC=23, DEC=15
8063 00:44:28.973406
8064 00:44:28.976387 ----->DramcWriteLeveling(PI) begin...
8065 00:44:28.976926 ==
8066 00:44:28.979785 Dram Type= 6, Freq= 0, CH_0, rank 1
8067 00:44:28.983466 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8068 00:44:28.983864 ==
8069 00:44:28.986212 Write leveling (Byte 0): 34 => 34
8070 00:44:28.989648 Write leveling (Byte 1): 30 => 30
8071 00:44:28.992982 DramcWriteLeveling(PI) end<-----
8072 00:44:28.993367
8073 00:44:28.993665 ==
8074 00:44:28.996395 Dram Type= 6, Freq= 0, CH_0, rank 1
8075 00:44:28.999974 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8076 00:44:29.000463 ==
8077 00:44:29.003254 [Gating] SW mode calibration
8078 00:44:29.009533 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8079 00:44:29.016382 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8080 00:44:29.019571 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8081 00:44:29.022847 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8082 00:44:29.029656 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8083 00:44:29.032867 1 4 12 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
8084 00:44:29.036211 1 4 16 | B1->B0 | 2b2b 3434 | 0 1 | (1 1) (1 1)
8085 00:44:29.042876 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8086 00:44:29.046446 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8087 00:44:29.049926 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8088 00:44:29.056260 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8089 00:44:29.059579 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8090 00:44:29.062561 1 5 8 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)
8091 00:44:29.069296 1 5 12 | B1->B0 | 3434 2b2b | 1 0 | (1 1) (1 0)
8092 00:44:29.073091 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
8093 00:44:29.076282 1 5 20 | B1->B0 | 2727 2323 | 0 0 | (1 0) (0 0)
8094 00:44:29.083114 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8095 00:44:29.086414 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8096 00:44:29.089496 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8097 00:44:29.095848 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8098 00:44:29.099369 1 6 8 | B1->B0 | 2323 2828 | 0 0 | (0 0) (1 1)
8099 00:44:29.102914 1 6 12 | B1->B0 | 2323 3d3d | 0 0 | (0 0) (0 0)
8100 00:44:29.109901 1 6 16 | B1->B0 | 2f2f 4646 | 0 0 | (0 0) (0 0)
8101 00:44:29.112804 1 6 20 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
8102 00:44:29.116093 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8103 00:44:29.122308 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8104 00:44:29.126055 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8105 00:44:29.129386 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8106 00:44:29.135667 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8107 00:44:29.139317 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8108 00:44:29.142330 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8109 00:44:29.149299 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8110 00:44:29.152512 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8111 00:44:29.155824 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8112 00:44:29.162703 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8113 00:44:29.166070 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8114 00:44:29.169525 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8115 00:44:29.175834 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8116 00:44:29.178701 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8117 00:44:29.182543 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8118 00:44:29.188687 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8119 00:44:29.191987 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8120 00:44:29.195448 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8121 00:44:29.202261 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8122 00:44:29.205525 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8123 00:44:29.208908 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8124 00:44:29.212219 Total UI for P1: 0, mck2ui 16
8125 00:44:29.215457 best dqsien dly found for B0: ( 1, 9, 8)
8126 00:44:29.218936 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8127 00:44:29.225386 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8128 00:44:29.228518 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8129 00:44:29.231866 Total UI for P1: 0, mck2ui 16
8130 00:44:29.235114 best dqsien dly found for B1: ( 1, 9, 18)
8131 00:44:29.238495 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8132 00:44:29.242106 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8133 00:44:29.242539
8134 00:44:29.245377 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8135 00:44:29.248388 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8136 00:44:29.251966 [Gating] SW calibration Done
8137 00:44:29.252398 ==
8138 00:44:29.255583 Dram Type= 6, Freq= 0, CH_0, rank 1
8139 00:44:29.262141 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8140 00:44:29.262643 ==
8141 00:44:29.262980 RX Vref Scan: 0
8142 00:44:29.263288
8143 00:44:29.265619 RX Vref 0 -> 0, step: 1
8144 00:44:29.266049
8145 00:44:29.268522 RX Delay 0 -> 252, step: 8
8146 00:44:29.272078 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
8147 00:44:29.275515 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8148 00:44:29.278579 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8149 00:44:29.281854 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
8150 00:44:29.288448 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8151 00:44:29.291720 iDelay=200, Bit 5, Center 111 (56 ~ 167) 112
8152 00:44:29.295007 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8153 00:44:29.298275 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8154 00:44:29.301690 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8155 00:44:29.308393 iDelay=200, Bit 9, Center 107 (48 ~ 167) 120
8156 00:44:29.311764 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8157 00:44:29.315153 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8158 00:44:29.318485 iDelay=200, Bit 12, Center 127 (64 ~ 191) 128
8159 00:44:29.321265 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
8160 00:44:29.328340 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8161 00:44:29.331404 iDelay=200, Bit 15, Center 127 (64 ~ 191) 128
8162 00:44:29.331841 ==
8163 00:44:29.335049 Dram Type= 6, Freq= 0, CH_0, rank 1
8164 00:44:29.338341 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8165 00:44:29.338776 ==
8166 00:44:29.342033 DQS Delay:
8167 00:44:29.342544 DQS0 = 0, DQS1 = 0
8168 00:44:29.342885 DQM Delay:
8169 00:44:29.344618 DQM0 = 127, DQM1 = 121
8170 00:44:29.345108 DQ Delay:
8171 00:44:29.347982 DQ0 =127, DQ1 =127, DQ2 =123, DQ3 =123
8172 00:44:29.351312 DQ4 =127, DQ5 =111, DQ6 =139, DQ7 =139
8173 00:44:29.358589 DQ8 =115, DQ9 =107, DQ10 =123, DQ11 =115
8174 00:44:29.361971 DQ12 =127, DQ13 =127, DQ14 =131, DQ15 =127
8175 00:44:29.362404
8176 00:44:29.362738
8177 00:44:29.363053 ==
8178 00:44:29.364934 Dram Type= 6, Freq= 0, CH_0, rank 1
8179 00:44:29.367819 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8180 00:44:29.368214 ==
8181 00:44:29.368520
8182 00:44:29.368869
8183 00:44:29.371468 TX Vref Scan disable
8184 00:44:29.374580 == TX Byte 0 ==
8185 00:44:29.378270 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8186 00:44:29.381221 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8187 00:44:29.384551 == TX Byte 1 ==
8188 00:44:29.387996 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
8189 00:44:29.391254 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8190 00:44:29.391648 ==
8191 00:44:29.394518 Dram Type= 6, Freq= 0, CH_0, rank 1
8192 00:44:29.397827 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8193 00:44:29.398259 ==
8194 00:44:29.413391
8195 00:44:29.416777 TX Vref early break, caculate TX vref
8196 00:44:29.420064 TX Vref=16, minBit 0, minWin=22, winSum=374
8197 00:44:29.423408 TX Vref=18, minBit 1, minWin=22, winSum=379
8198 00:44:29.426944 TX Vref=20, minBit 0, minWin=23, winSum=392
8199 00:44:29.430461 TX Vref=22, minBit 2, minWin=23, winSum=398
8200 00:44:29.433090 TX Vref=24, minBit 1, minWin=24, winSum=405
8201 00:44:29.439632 TX Vref=26, minBit 1, minWin=25, winSum=412
8202 00:44:29.442924 TX Vref=28, minBit 1, minWin=25, winSum=417
8203 00:44:29.446509 TX Vref=30, minBit 8, minWin=24, winSum=415
8204 00:44:29.449848 TX Vref=32, minBit 13, minWin=24, winSum=406
8205 00:44:29.453428 TX Vref=34, minBit 0, minWin=24, winSum=396
8206 00:44:29.456392 TX Vref=36, minBit 13, minWin=23, winSum=391
8207 00:44:29.462839 [TxChooseVref] Worse bit 1, Min win 25, Win sum 417, Final Vref 28
8208 00:44:29.463229
8209 00:44:29.466342 Final TX Range 0 Vref 28
8210 00:44:29.466727
8211 00:44:29.467028 ==
8212 00:44:29.469654 Dram Type= 6, Freq= 0, CH_0, rank 1
8213 00:44:29.472744 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8214 00:44:29.473149 ==
8215 00:44:29.473462
8216 00:44:29.476373
8217 00:44:29.476799 TX Vref Scan disable
8218 00:44:29.483234 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8219 00:44:29.483625 == TX Byte 0 ==
8220 00:44:29.487149 u2DelayCellOfst[0]=11 cells (3 PI)
8221 00:44:29.490236 u2DelayCellOfst[1]=15 cells (4 PI)
8222 00:44:29.493086 u2DelayCellOfst[2]=11 cells (3 PI)
8223 00:44:29.496302 u2DelayCellOfst[3]=11 cells (3 PI)
8224 00:44:29.499790 u2DelayCellOfst[4]=7 cells (2 PI)
8225 00:44:29.503165 u2DelayCellOfst[5]=0 cells (0 PI)
8226 00:44:29.506439 u2DelayCellOfst[6]=18 cells (5 PI)
8227 00:44:29.509852 u2DelayCellOfst[7]=18 cells (5 PI)
8228 00:44:29.512696 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
8229 00:44:29.516255 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8230 00:44:29.519371 == TX Byte 1 ==
8231 00:44:29.522930 u2DelayCellOfst[8]=0 cells (0 PI)
8232 00:44:29.526421 u2DelayCellOfst[9]=0 cells (0 PI)
8233 00:44:29.526812 u2DelayCellOfst[10]=3 cells (1 PI)
8234 00:44:29.529650 u2DelayCellOfst[11]=3 cells (1 PI)
8235 00:44:29.532954 u2DelayCellOfst[12]=11 cells (3 PI)
8236 00:44:29.536513 u2DelayCellOfst[13]=7 cells (2 PI)
8237 00:44:29.539704 u2DelayCellOfst[14]=15 cells (4 PI)
8238 00:44:29.542935 u2DelayCellOfst[15]=11 cells (3 PI)
8239 00:44:29.549704 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8240 00:44:29.552872 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8241 00:44:29.553268 DramC Write-DBI on
8242 00:44:29.553574 ==
8243 00:44:29.556002 Dram Type= 6, Freq= 0, CH_0, rank 1
8244 00:44:29.562768 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8245 00:44:29.563161 ==
8246 00:44:29.563463
8247 00:44:29.563741
8248 00:44:29.564006 TX Vref Scan disable
8249 00:44:29.566633 == TX Byte 0 ==
8250 00:44:29.570066 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
8251 00:44:29.573585 == TX Byte 1 ==
8252 00:44:29.576722 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
8253 00:44:29.579926 DramC Write-DBI off
8254 00:44:29.580313
8255 00:44:29.580618 [DATLAT]
8256 00:44:29.580944 Freq=1600, CH0 RK1
8257 00:44:29.581221
8258 00:44:29.583081 DATLAT Default: 0xf
8259 00:44:29.583469 0, 0xFFFF, sum = 0
8260 00:44:29.586507 1, 0xFFFF, sum = 0
8261 00:44:29.589707 2, 0xFFFF, sum = 0
8262 00:44:29.590100 3, 0xFFFF, sum = 0
8263 00:44:29.593156 4, 0xFFFF, sum = 0
8264 00:44:29.593550 5, 0xFFFF, sum = 0
8265 00:44:29.596825 6, 0xFFFF, sum = 0
8266 00:44:29.597221 7, 0xFFFF, sum = 0
8267 00:44:29.600073 8, 0xFFFF, sum = 0
8268 00:44:29.600463 9, 0xFFFF, sum = 0
8269 00:44:29.603282 10, 0xFFFF, sum = 0
8270 00:44:29.603738 11, 0xFFFF, sum = 0
8271 00:44:29.606508 12, 0xFFFF, sum = 0
8272 00:44:29.606902 13, 0xCFFF, sum = 0
8273 00:44:29.609848 14, 0x0, sum = 1
8274 00:44:29.610413 15, 0x0, sum = 2
8275 00:44:29.613015 16, 0x0, sum = 3
8276 00:44:29.613422 17, 0x0, sum = 4
8277 00:44:29.616160 best_step = 15
8278 00:44:29.616637
8279 00:44:29.616993 ==
8280 00:44:29.619551 Dram Type= 6, Freq= 0, CH_0, rank 1
8281 00:44:29.622792 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8282 00:44:29.623206 ==
8283 00:44:29.626457 RX Vref Scan: 0
8284 00:44:29.626843
8285 00:44:29.627219 RX Vref 0 -> 0, step: 1
8286 00:44:29.627513
8287 00:44:29.629496 RX Delay 3 -> 252, step: 4
8288 00:44:29.633232 iDelay=191, Bit 0, Center 124 (71 ~ 178) 108
8289 00:44:29.639837 iDelay=191, Bit 1, Center 124 (71 ~ 178) 108
8290 00:44:29.642586 iDelay=191, Bit 2, Center 122 (71 ~ 174) 104
8291 00:44:29.646227 iDelay=191, Bit 3, Center 122 (67 ~ 178) 112
8292 00:44:29.649631 iDelay=191, Bit 4, Center 124 (71 ~ 178) 108
8293 00:44:29.653075 iDelay=191, Bit 5, Center 112 (59 ~ 166) 108
8294 00:44:29.659423 iDelay=191, Bit 6, Center 134 (79 ~ 190) 112
8295 00:44:29.662867 iDelay=191, Bit 7, Center 134 (79 ~ 190) 112
8296 00:44:29.666291 iDelay=191, Bit 8, Center 112 (55 ~ 170) 116
8297 00:44:29.669676 iDelay=191, Bit 9, Center 104 (47 ~ 162) 116
8298 00:44:29.673048 iDelay=191, Bit 10, Center 120 (63 ~ 178) 116
8299 00:44:29.679272 iDelay=191, Bit 11, Center 112 (55 ~ 170) 116
8300 00:44:29.682689 iDelay=191, Bit 12, Center 124 (67 ~ 182) 116
8301 00:44:29.686195 iDelay=191, Bit 13, Center 122 (67 ~ 178) 112
8302 00:44:29.689210 iDelay=191, Bit 14, Center 128 (71 ~ 186) 116
8303 00:44:29.695823 iDelay=191, Bit 15, Center 124 (67 ~ 182) 116
8304 00:44:29.696184 ==
8305 00:44:29.699291 Dram Type= 6, Freq= 0, CH_0, rank 1
8306 00:44:29.702212 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8307 00:44:29.702537 ==
8308 00:44:29.702751 DQS Delay:
8309 00:44:29.706161 DQS0 = 0, DQS1 = 0
8310 00:44:29.706438 DQM Delay:
8311 00:44:29.709067 DQM0 = 124, DQM1 = 118
8312 00:44:29.709375 DQ Delay:
8313 00:44:29.712112 DQ0 =124, DQ1 =124, DQ2 =122, DQ3 =122
8314 00:44:29.715815 DQ4 =124, DQ5 =112, DQ6 =134, DQ7 =134
8315 00:44:29.718973 DQ8 =112, DQ9 =104, DQ10 =120, DQ11 =112
8316 00:44:29.722153 DQ12 =124, DQ13 =122, DQ14 =128, DQ15 =124
8317 00:44:29.722432
8318 00:44:29.725581
8319 00:44:29.725941
8320 00:44:29.726223 [DramC_TX_OE_Calibration] TA2
8321 00:44:29.729010 Original DQ_B0 (3 6) =30, OEN = 27
8322 00:44:29.732482 Original DQ_B1 (3 6) =30, OEN = 27
8323 00:44:29.735884 24, 0x0, End_B0=24 End_B1=24
8324 00:44:29.738762 25, 0x0, End_B0=25 End_B1=25
8325 00:44:29.742296 26, 0x0, End_B0=26 End_B1=26
8326 00:44:29.742738 27, 0x0, End_B0=27 End_B1=27
8327 00:44:29.745847 28, 0x0, End_B0=28 End_B1=28
8328 00:44:29.748710 29, 0x0, End_B0=29 End_B1=29
8329 00:44:29.751910 30, 0x0, End_B0=30 End_B1=30
8330 00:44:29.755485 31, 0x5151, End_B0=30 End_B1=30
8331 00:44:29.756009 Byte0 end_step=30 best_step=27
8332 00:44:29.758928 Byte1 end_step=30 best_step=27
8333 00:44:29.762374 Byte0 TX OE(2T, 0.5T) = (3, 3)
8334 00:44:29.765632 Byte1 TX OE(2T, 0.5T) = (3, 3)
8335 00:44:29.766062
8336 00:44:29.766395
8337 00:44:29.772059 [DQSOSCAuto] RK1, (LSB)MR18= 0x2613, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 390 ps
8338 00:44:29.775331 CH0 RK1: MR19=303, MR18=2613
8339 00:44:29.781729 CH0_RK1: MR19=0x303, MR18=0x2613, DQSOSC=390, MR23=63, INC=24, DEC=16
8340 00:44:29.785079 [RxdqsGatingPostProcess] freq 1600
8341 00:44:29.791936 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8342 00:44:29.795596 best DQS0 dly(2T, 0.5T) = (1, 1)
8343 00:44:29.796028 best DQS1 dly(2T, 0.5T) = (1, 1)
8344 00:44:29.798730 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8345 00:44:29.802298 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8346 00:44:29.804960 best DQS0 dly(2T, 0.5T) = (1, 1)
8347 00:44:29.808620 best DQS1 dly(2T, 0.5T) = (1, 1)
8348 00:44:29.811814 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8349 00:44:29.815395 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8350 00:44:29.818823 Pre-setting of DQS Precalculation
8351 00:44:29.824876 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8352 00:44:29.825320 ==
8353 00:44:29.828240 Dram Type= 6, Freq= 0, CH_1, rank 0
8354 00:44:29.831928 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8355 00:44:29.832370 ==
8356 00:44:29.834862 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8357 00:44:29.841651 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8358 00:44:29.845127 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8359 00:44:29.851704 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8360 00:44:29.860351 [CA 0] Center 41 (12~70) winsize 59
8361 00:44:29.862981 [CA 1] Center 42 (12~72) winsize 61
8362 00:44:29.866616 [CA 2] Center 37 (8~66) winsize 59
8363 00:44:29.869922 [CA 3] Center 37 (8~66) winsize 59
8364 00:44:29.873415 [CA 4] Center 37 (8~67) winsize 60
8365 00:44:29.876710 [CA 5] Center 36 (7~65) winsize 59
8366 00:44:29.877139
8367 00:44:29.879826 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8368 00:44:29.880121
8369 00:44:29.882848 [CATrainingPosCal] consider 1 rank data
8370 00:44:29.886519 u2DelayCellTimex100 = 258/100 ps
8371 00:44:29.889801 CA0 delay=41 (12~70),Diff = 5 PI (18 cell)
8372 00:44:29.896311 CA1 delay=42 (12~72),Diff = 6 PI (22 cell)
8373 00:44:29.899620 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8374 00:44:29.902866 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8375 00:44:29.906082 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8376 00:44:29.909804 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
8377 00:44:29.910235
8378 00:44:29.912741 CA PerBit enable=1, Macro0, CA PI delay=36
8379 00:44:29.913149
8380 00:44:29.916113 [CBTSetCACLKResult] CA Dly = 36
8381 00:44:29.919431 CS Dly: 9 (0~40)
8382 00:44:29.923151 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8383 00:44:29.926554 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8384 00:44:29.926984 ==
8385 00:44:29.929906 Dram Type= 6, Freq= 0, CH_1, rank 1
8386 00:44:29.932698 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8387 00:44:29.933142 ==
8388 00:44:29.939565 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8389 00:44:29.942892 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8390 00:44:29.949337 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8391 00:44:29.952555 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8392 00:44:29.962850 [CA 0] Center 42 (13~72) winsize 60
8393 00:44:29.966371 [CA 1] Center 42 (13~72) winsize 60
8394 00:44:29.969976 [CA 2] Center 38 (9~67) winsize 59
8395 00:44:29.972537 [CA 3] Center 36 (7~66) winsize 60
8396 00:44:29.976108 [CA 4] Center 38 (8~68) winsize 61
8397 00:44:29.979388 [CA 5] Center 36 (7~66) winsize 60
8398 00:44:29.979792
8399 00:44:29.982736 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8400 00:44:29.983229
8401 00:44:29.989575 [CATrainingPosCal] consider 2 rank data
8402 00:44:29.990002 u2DelayCellTimex100 = 258/100 ps
8403 00:44:29.996007 CA0 delay=41 (13~70),Diff = 5 PI (18 cell)
8404 00:44:29.999178 CA1 delay=42 (13~72),Diff = 6 PI (22 cell)
8405 00:44:30.002691 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8406 00:44:30.005688 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8407 00:44:30.009264 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8408 00:44:30.012526 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
8409 00:44:30.013067
8410 00:44:30.016138 CA PerBit enable=1, Macro0, CA PI delay=36
8411 00:44:30.016722
8412 00:44:30.019257 [CBTSetCACLKResult] CA Dly = 36
8413 00:44:30.022929 CS Dly: 10 (0~43)
8414 00:44:30.025959 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8415 00:44:30.029218 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8416 00:44:30.029648
8417 00:44:30.032367 ----->DramcWriteLeveling(PI) begin...
8418 00:44:30.032882 ==
8419 00:44:30.035783 Dram Type= 6, Freq= 0, CH_1, rank 0
8420 00:44:30.042149 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8421 00:44:30.042685 ==
8422 00:44:30.045610 Write leveling (Byte 0): 24 => 24
8423 00:44:30.046044 Write leveling (Byte 1): 30 => 30
8424 00:44:30.048918 DramcWriteLeveling(PI) end<-----
8425 00:44:30.049765
8426 00:44:30.052420 ==
8427 00:44:30.053006 Dram Type= 6, Freq= 0, CH_1, rank 0
8428 00:44:30.059074 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8429 00:44:30.059542 ==
8430 00:44:30.062533 [Gating] SW mode calibration
8431 00:44:30.068918 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8432 00:44:30.072145 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8433 00:44:30.079149 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8434 00:44:30.082261 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8435 00:44:30.085833 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8436 00:44:30.092180 1 4 12 | B1->B0 | 2828 2424 | 1 0 | (1 1) (0 0)
8437 00:44:30.095491 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8438 00:44:30.098940 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8439 00:44:30.105492 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8440 00:44:30.108805 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8441 00:44:30.111982 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8442 00:44:30.118617 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8443 00:44:30.121680 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8444 00:44:30.125092 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (0 0) (1 1)
8445 00:44:30.131918 1 5 16 | B1->B0 | 2424 2323 | 0 0 | (1 0) (1 0)
8446 00:44:30.135037 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8447 00:44:30.138517 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8448 00:44:30.145469 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8449 00:44:30.148521 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8450 00:44:30.151616 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8451 00:44:30.158527 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8452 00:44:30.162487 1 6 12 | B1->B0 | 2626 2424 | 0 0 | (0 0) (0 0)
8453 00:44:30.165187 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8454 00:44:30.168774 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8455 00:44:30.175045 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8456 00:44:30.178913 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8457 00:44:30.181752 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8458 00:44:30.188447 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8459 00:44:30.191912 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8460 00:44:30.195584 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8461 00:44:30.201727 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8462 00:44:30.205212 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8463 00:44:30.208736 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8464 00:44:30.215565 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8465 00:44:30.218386 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8466 00:44:30.221659 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8467 00:44:30.228104 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8468 00:44:30.231526 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8469 00:44:30.234925 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8470 00:44:30.241558 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8471 00:44:30.244933 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8472 00:44:30.248417 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8473 00:44:30.254914 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8474 00:44:30.258429 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8475 00:44:30.261339 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8476 00:44:30.268091 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8477 00:44:30.271904 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8478 00:44:30.274827 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8479 00:44:30.278353 Total UI for P1: 0, mck2ui 16
8480 00:44:30.281294 best dqsien dly found for B0: ( 1, 9, 14)
8481 00:44:30.284602 Total UI for P1: 0, mck2ui 16
8482 00:44:30.288344 best dqsien dly found for B1: ( 1, 9, 16)
8483 00:44:30.291763 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8484 00:44:30.294405 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8485 00:44:30.294865
8486 00:44:30.301396 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8487 00:44:30.304512 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8488 00:44:30.305055 [Gating] SW calibration Done
8489 00:44:30.308291 ==
8490 00:44:30.311654 Dram Type= 6, Freq= 0, CH_1, rank 0
8491 00:44:30.314949 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8492 00:44:30.315457 ==
8493 00:44:30.315801 RX Vref Scan: 0
8494 00:44:30.316113
8495 00:44:30.318361 RX Vref 0 -> 0, step: 1
8496 00:44:30.318867
8497 00:44:30.321285 RX Delay 0 -> 252, step: 8
8498 00:44:30.324329 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8499 00:44:30.327977 iDelay=200, Bit 1, Center 127 (64 ~ 191) 128
8500 00:44:30.331488 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8501 00:44:30.338394 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8502 00:44:30.341269 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8503 00:44:30.344734 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8504 00:44:30.348157 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8505 00:44:30.351522 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8506 00:44:30.357594 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8507 00:44:30.361137 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8508 00:44:30.364824 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
8509 00:44:30.367654 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8510 00:44:30.370802 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8511 00:44:30.377379 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8512 00:44:30.380490 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8513 00:44:30.384116 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8514 00:44:30.384748 ==
8515 00:44:30.387486 Dram Type= 6, Freq= 0, CH_1, rank 0
8516 00:44:30.390502 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8517 00:44:30.394093 ==
8518 00:44:30.394603 DQS Delay:
8519 00:44:30.394949 DQS0 = 0, DQS1 = 0
8520 00:44:30.397378 DQM Delay:
8521 00:44:30.397876 DQM0 = 132, DQM1 = 126
8522 00:44:30.400529 DQ Delay:
8523 00:44:30.404234 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8524 00:44:30.407004 DQ4 =127, DQ5 =143, DQ6 =143, DQ7 =131
8525 00:44:30.410288 DQ8 =111, DQ9 =115, DQ10 =123, DQ11 =119
8526 00:44:30.413959 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8527 00:44:30.414388
8528 00:44:30.414722
8529 00:44:30.415034 ==
8530 00:44:30.417305 Dram Type= 6, Freq= 0, CH_1, rank 0
8531 00:44:30.420763 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8532 00:44:30.421197 ==
8533 00:44:30.421535
8534 00:44:30.423965
8535 00:44:30.424392 TX Vref Scan disable
8536 00:44:30.427325 == TX Byte 0 ==
8537 00:44:30.430842 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8538 00:44:30.434050 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8539 00:44:30.437018 == TX Byte 1 ==
8540 00:44:30.440584 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
8541 00:44:30.443901 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8542 00:44:30.444324 ==
8543 00:44:30.447794 Dram Type= 6, Freq= 0, CH_1, rank 0
8544 00:44:30.453815 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8545 00:44:30.454250 ==
8546 00:44:30.466008
8547 00:44:30.468962 TX Vref early break, caculate TX vref
8548 00:44:30.472408 TX Vref=16, minBit 8, minWin=20, winSum=356
8549 00:44:30.475238 TX Vref=18, minBit 8, minWin=21, winSum=366
8550 00:44:30.478647 TX Vref=20, minBit 9, minWin=22, winSum=378
8551 00:44:30.482028 TX Vref=22, minBit 8, minWin=23, winSum=391
8552 00:44:30.485448 TX Vref=24, minBit 8, minWin=24, winSum=399
8553 00:44:30.492225 TX Vref=26, minBit 8, minWin=24, winSum=409
8554 00:44:30.495625 TX Vref=28, minBit 12, minWin=24, winSum=412
8555 00:44:30.498681 TX Vref=30, minBit 1, minWin=24, winSum=403
8556 00:44:30.502040 TX Vref=32, minBit 0, minWin=23, winSum=393
8557 00:44:30.505235 TX Vref=34, minBit 9, minWin=22, winSum=387
8558 00:44:30.512204 [TxChooseVref] Worse bit 12, Min win 24, Win sum 412, Final Vref 28
8559 00:44:30.512756
8560 00:44:30.515326 Final TX Range 0 Vref 28
8561 00:44:30.515803
8562 00:44:30.516183 ==
8563 00:44:30.518504 Dram Type= 6, Freq= 0, CH_1, rank 0
8564 00:44:30.522020 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8565 00:44:30.522490 ==
8566 00:44:30.522858
8567 00:44:30.523139
8568 00:44:30.525216 TX Vref Scan disable
8569 00:44:30.532288 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8570 00:44:30.532830 == TX Byte 0 ==
8571 00:44:30.535263 u2DelayCellOfst[0]=22 cells (6 PI)
8572 00:44:30.538676 u2DelayCellOfst[1]=15 cells (4 PI)
8573 00:44:30.541754 u2DelayCellOfst[2]=0 cells (0 PI)
8574 00:44:30.545297 u2DelayCellOfst[3]=7 cells (2 PI)
8575 00:44:30.548547 u2DelayCellOfst[4]=11 cells (3 PI)
8576 00:44:30.552144 u2DelayCellOfst[5]=26 cells (7 PI)
8577 00:44:30.555484 u2DelayCellOfst[6]=22 cells (6 PI)
8578 00:44:30.558394 u2DelayCellOfst[7]=7 cells (2 PI)
8579 00:44:30.561768 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8580 00:44:30.565313 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8581 00:44:30.565699 == TX Byte 1 ==
8582 00:44:30.568665 u2DelayCellOfst[8]=0 cells (0 PI)
8583 00:44:30.572181 u2DelayCellOfst[9]=7 cells (2 PI)
8584 00:44:30.575488 u2DelayCellOfst[10]=11 cells (3 PI)
8585 00:44:30.578365 u2DelayCellOfst[11]=7 cells (2 PI)
8586 00:44:30.581722 u2DelayCellOfst[12]=15 cells (4 PI)
8587 00:44:30.585164 u2DelayCellOfst[13]=18 cells (5 PI)
8588 00:44:30.588469 u2DelayCellOfst[14]=18 cells (5 PI)
8589 00:44:30.591715 u2DelayCellOfst[15]=18 cells (5 PI)
8590 00:44:30.595199 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8591 00:44:30.601630 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8592 00:44:30.602043 DramC Write-DBI on
8593 00:44:30.602347 ==
8594 00:44:30.605528 Dram Type= 6, Freq= 0, CH_1, rank 0
8595 00:44:30.608545 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8596 00:44:30.608973 ==
8597 00:44:30.611862
8598 00:44:30.612242
8599 00:44:30.612542 TX Vref Scan disable
8600 00:44:30.615242 == TX Byte 0 ==
8601 00:44:30.618733 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8602 00:44:30.621507 == TX Byte 1 ==
8603 00:44:30.624917 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8604 00:44:30.628391 DramC Write-DBI off
8605 00:44:30.628933
8606 00:44:30.629269 [DATLAT]
8607 00:44:30.629578 Freq=1600, CH1 RK0
8608 00:44:30.629878
8609 00:44:30.632088 DATLAT Default: 0xf
8610 00:44:30.632591 0, 0xFFFF, sum = 0
8611 00:44:30.635258 1, 0xFFFF, sum = 0
8612 00:44:30.638446 2, 0xFFFF, sum = 0
8613 00:44:30.638962 3, 0xFFFF, sum = 0
8614 00:44:30.641687 4, 0xFFFF, sum = 0
8615 00:44:30.642238 5, 0xFFFF, sum = 0
8616 00:44:30.644759 6, 0xFFFF, sum = 0
8617 00:44:30.645192 7, 0xFFFF, sum = 0
8618 00:44:30.648469 8, 0xFFFF, sum = 0
8619 00:44:30.649032 9, 0xFFFF, sum = 0
8620 00:44:30.651732 10, 0xFFFF, sum = 0
8621 00:44:30.652386 11, 0xFFFF, sum = 0
8622 00:44:30.654807 12, 0xFFFF, sum = 0
8623 00:44:30.655242 13, 0x8FFF, sum = 0
8624 00:44:30.658201 14, 0x0, sum = 1
8625 00:44:30.658637 15, 0x0, sum = 2
8626 00:44:30.662494 16, 0x0, sum = 3
8627 00:44:30.663007 17, 0x0, sum = 4
8628 00:44:30.665401 best_step = 15
8629 00:44:30.665900
8630 00:44:30.666231 ==
8631 00:44:30.668218 Dram Type= 6, Freq= 0, CH_1, rank 0
8632 00:44:30.671612 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8633 00:44:30.672124 ==
8634 00:44:30.675004 RX Vref Scan: 1
8635 00:44:30.675428
8636 00:44:30.675765 Set Vref Range= 24 -> 127
8637 00:44:30.676076
8638 00:44:30.678574 RX Vref 24 -> 127, step: 1
8639 00:44:30.679247
8640 00:44:30.681527 RX Delay 11 -> 252, step: 4
8641 00:44:30.682007
8642 00:44:30.684899 Set Vref, RX VrefLevel [Byte0]: 24
8643 00:44:30.687976 [Byte1]: 24
8644 00:44:30.688508
8645 00:44:30.691175 Set Vref, RX VrefLevel [Byte0]: 25
8646 00:44:30.694429 [Byte1]: 25
8647 00:44:30.697785
8648 00:44:30.698264 Set Vref, RX VrefLevel [Byte0]: 26
8649 00:44:30.701241 [Byte1]: 26
8650 00:44:30.705690
8651 00:44:30.706116 Set Vref, RX VrefLevel [Byte0]: 27
8652 00:44:30.708841 [Byte1]: 27
8653 00:44:30.713302
8654 00:44:30.713773 Set Vref, RX VrefLevel [Byte0]: 28
8655 00:44:30.716705 [Byte1]: 28
8656 00:44:30.720609
8657 00:44:30.721092 Set Vref, RX VrefLevel [Byte0]: 29
8658 00:44:30.723962 [Byte1]: 29
8659 00:44:30.728135
8660 00:44:30.728533 Set Vref, RX VrefLevel [Byte0]: 30
8661 00:44:30.731336 [Byte1]: 30
8662 00:44:30.735903
8663 00:44:30.736477 Set Vref, RX VrefLevel [Byte0]: 31
8664 00:44:30.739280 [Byte1]: 31
8665 00:44:30.743816
8666 00:44:30.744251 Set Vref, RX VrefLevel [Byte0]: 32
8667 00:44:30.747052 [Byte1]: 32
8668 00:44:30.750943
8669 00:44:30.751323 Set Vref, RX VrefLevel [Byte0]: 33
8670 00:44:30.754272 [Byte1]: 33
8671 00:44:30.758770
8672 00:44:30.759176 Set Vref, RX VrefLevel [Byte0]: 34
8673 00:44:30.761905 [Byte1]: 34
8674 00:44:30.766369
8675 00:44:30.766725 Set Vref, RX VrefLevel [Byte0]: 35
8676 00:44:30.769545 [Byte1]: 35
8677 00:44:30.774085
8678 00:44:30.774468 Set Vref, RX VrefLevel [Byte0]: 36
8679 00:44:30.777634 [Byte1]: 36
8680 00:44:30.782005
8681 00:44:30.782390 Set Vref, RX VrefLevel [Byte0]: 37
8682 00:44:30.784792 [Byte1]: 37
8683 00:44:30.788956
8684 00:44:30.789504 Set Vref, RX VrefLevel [Byte0]: 38
8685 00:44:30.792262 [Byte1]: 38
8686 00:44:30.797056
8687 00:44:30.797447 Set Vref, RX VrefLevel [Byte0]: 39
8688 00:44:30.800331 [Byte1]: 39
8689 00:44:30.804229
8690 00:44:30.804617 Set Vref, RX VrefLevel [Byte0]: 40
8691 00:44:30.807661 [Byte1]: 40
8692 00:44:30.811718
8693 00:44:30.812135 Set Vref, RX VrefLevel [Byte0]: 41
8694 00:44:30.815420 [Byte1]: 41
8695 00:44:30.819819
8696 00:44:30.820280 Set Vref, RX VrefLevel [Byte0]: 42
8697 00:44:30.823027 [Byte1]: 42
8698 00:44:30.827359
8699 00:44:30.827822 Set Vref, RX VrefLevel [Byte0]: 43
8700 00:44:30.830613 [Byte1]: 43
8701 00:44:30.834653
8702 00:44:30.835041 Set Vref, RX VrefLevel [Byte0]: 44
8703 00:44:30.837887 [Byte1]: 44
8704 00:44:30.842330
8705 00:44:30.842774 Set Vref, RX VrefLevel [Byte0]: 45
8706 00:44:30.845740 [Byte1]: 45
8707 00:44:30.850319
8708 00:44:30.850729 Set Vref, RX VrefLevel [Byte0]: 46
8709 00:44:30.853776 [Byte1]: 46
8710 00:44:30.858217
8711 00:44:30.858702 Set Vref, RX VrefLevel [Byte0]: 47
8712 00:44:30.860962 [Byte1]: 47
8713 00:44:30.865646
8714 00:44:30.866051 Set Vref, RX VrefLevel [Byte0]: 48
8715 00:44:30.868360 [Byte1]: 48
8716 00:44:30.872995
8717 00:44:30.873386 Set Vref, RX VrefLevel [Byte0]: 49
8718 00:44:30.876390 [Byte1]: 49
8719 00:44:30.880798
8720 00:44:30.881180 Set Vref, RX VrefLevel [Byte0]: 50
8721 00:44:30.884168 [Byte1]: 50
8722 00:44:30.888065
8723 00:44:30.888446 Set Vref, RX VrefLevel [Byte0]: 51
8724 00:44:30.891573 [Byte1]: 51
8725 00:44:30.895999
8726 00:44:30.896333 Set Vref, RX VrefLevel [Byte0]: 52
8727 00:44:30.899412 [Byte1]: 52
8728 00:44:30.903468
8729 00:44:30.903853 Set Vref, RX VrefLevel [Byte0]: 53
8730 00:44:30.906650 [Byte1]: 53
8731 00:44:30.910805
8732 00:44:30.911187 Set Vref, RX VrefLevel [Byte0]: 54
8733 00:44:30.914594 [Byte1]: 54
8734 00:44:30.918780
8735 00:44:30.919168 Set Vref, RX VrefLevel [Byte0]: 55
8736 00:44:30.921848 [Byte1]: 55
8737 00:44:30.926040
8738 00:44:30.926435 Set Vref, RX VrefLevel [Byte0]: 56
8739 00:44:30.929634 [Byte1]: 56
8740 00:44:30.934346
8741 00:44:30.934829 Set Vref, RX VrefLevel [Byte0]: 57
8742 00:44:30.937050 [Byte1]: 57
8743 00:44:30.941639
8744 00:44:30.942071 Set Vref, RX VrefLevel [Byte0]: 58
8745 00:44:30.944835 [Byte1]: 58
8746 00:44:30.948855
8747 00:44:30.949247 Set Vref, RX VrefLevel [Byte0]: 59
8748 00:44:30.952512 [Byte1]: 59
8749 00:44:30.956625
8750 00:44:30.957062 Set Vref, RX VrefLevel [Byte0]: 60
8751 00:44:30.959972 [Byte1]: 60
8752 00:44:30.964410
8753 00:44:30.964982 Set Vref, RX VrefLevel [Byte0]: 61
8754 00:44:30.967460 [Byte1]: 61
8755 00:44:30.972103
8756 00:44:30.972535 Set Vref, RX VrefLevel [Byte0]: 62
8757 00:44:30.974961 [Byte1]: 62
8758 00:44:30.979439
8759 00:44:30.979834 Set Vref, RX VrefLevel [Byte0]: 63
8760 00:44:30.983234 [Byte1]: 63
8761 00:44:30.986922
8762 00:44:30.987367 Set Vref, RX VrefLevel [Byte0]: 64
8763 00:44:30.990708 [Byte1]: 64
8764 00:44:30.995049
8765 00:44:30.995476 Set Vref, RX VrefLevel [Byte0]: 65
8766 00:44:30.997888 [Byte1]: 65
8767 00:44:31.002848
8768 00:44:31.003370 Set Vref, RX VrefLevel [Byte0]: 66
8769 00:44:31.005461 [Byte1]: 66
8770 00:44:31.009984
8771 00:44:31.010531 Set Vref, RX VrefLevel [Byte0]: 67
8772 00:44:31.013230 [Byte1]: 67
8773 00:44:31.017773
8774 00:44:31.018276 Set Vref, RX VrefLevel [Byte0]: 68
8775 00:44:31.021100 [Byte1]: 68
8776 00:44:31.025099
8777 00:44:31.025620 Set Vref, RX VrefLevel [Byte0]: 69
8778 00:44:31.028390 [Byte1]: 69
8779 00:44:31.033227
8780 00:44:31.033739 Set Vref, RX VrefLevel [Byte0]: 70
8781 00:44:31.036044 [Byte1]: 70
8782 00:44:31.040690
8783 00:44:31.041122 Set Vref, RX VrefLevel [Byte0]: 71
8784 00:44:31.044242 [Byte1]: 71
8785 00:44:31.048043
8786 00:44:31.048551 Set Vref, RX VrefLevel [Byte0]: 72
8787 00:44:31.051484 [Byte1]: 72
8788 00:44:31.055637
8789 00:44:31.056063 Final RX Vref Byte 0 = 56 to rank0
8790 00:44:31.059416 Final RX Vref Byte 1 = 56 to rank0
8791 00:44:31.062222 Final RX Vref Byte 0 = 56 to rank1
8792 00:44:31.065345 Final RX Vref Byte 1 = 56 to rank1==
8793 00:44:31.069022 Dram Type= 6, Freq= 0, CH_1, rank 0
8794 00:44:31.075696 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8795 00:44:31.076204 ==
8796 00:44:31.076540 DQS Delay:
8797 00:44:31.079080 DQS0 = 0, DQS1 = 0
8798 00:44:31.079567 DQM Delay:
8799 00:44:31.079914 DQM0 = 131, DQM1 = 122
8800 00:44:31.081680 DQ Delay:
8801 00:44:31.085246 DQ0 =138, DQ1 =126, DQ2 =120, DQ3 =130
8802 00:44:31.088614 DQ4 =126, DQ5 =142, DQ6 =142, DQ7 =128
8803 00:44:31.091762 DQ8 =108, DQ9 =112, DQ10 =122, DQ11 =116
8804 00:44:31.094899 DQ12 =132, DQ13 =130, DQ14 =130, DQ15 =132
8805 00:44:31.095325
8806 00:44:31.095656
8807 00:44:31.095959
8808 00:44:31.098438 [DramC_TX_OE_Calibration] TA2
8809 00:44:31.102036 Original DQ_B0 (3 6) =30, OEN = 27
8810 00:44:31.105946 Original DQ_B1 (3 6) =30, OEN = 27
8811 00:44:31.108333 24, 0x0, End_B0=24 End_B1=24
8812 00:44:31.111766 25, 0x0, End_B0=25 End_B1=25
8813 00:44:31.112199 26, 0x0, End_B0=26 End_B1=26
8814 00:44:31.115035 27, 0x0, End_B0=27 End_B1=27
8815 00:44:31.118418 28, 0x0, End_B0=28 End_B1=28
8816 00:44:31.121492 29, 0x0, End_B0=29 End_B1=29
8817 00:44:31.121881 30, 0x0, End_B0=30 End_B1=30
8818 00:44:31.125061 31, 0x4141, End_B0=30 End_B1=30
8819 00:44:31.127979 Byte0 end_step=30 best_step=27
8820 00:44:31.131367 Byte1 end_step=30 best_step=27
8821 00:44:31.134902 Byte0 TX OE(2T, 0.5T) = (3, 3)
8822 00:44:31.137702 Byte1 TX OE(2T, 0.5T) = (3, 3)
8823 00:44:31.138116
8824 00:44:31.138420
8825 00:44:31.144753 [DQSOSCAuto] RK0, (LSB)MR18= 0xa0e, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 404 ps
8826 00:44:31.148011 CH1 RK0: MR19=303, MR18=A0E
8827 00:44:31.154637 CH1_RK0: MR19=0x303, MR18=0xA0E, DQSOSC=402, MR23=63, INC=22, DEC=15
8828 00:44:31.155167
8829 00:44:31.158089 ----->DramcWriteLeveling(PI) begin...
8830 00:44:31.158624 ==
8831 00:44:31.161323 Dram Type= 6, Freq= 0, CH_1, rank 1
8832 00:44:31.164968 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8833 00:44:31.165485 ==
8834 00:44:31.167750 Write leveling (Byte 0): 24 => 24
8835 00:44:31.171083 Write leveling (Byte 1): 27 => 27
8836 00:44:31.174311 DramcWriteLeveling(PI) end<-----
8837 00:44:31.174821
8838 00:44:31.175172 ==
8839 00:44:31.177805 Dram Type= 6, Freq= 0, CH_1, rank 1
8840 00:44:31.180976 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8841 00:44:31.181668 ==
8842 00:44:31.184224 [Gating] SW mode calibration
8843 00:44:31.190973 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8844 00:44:31.197441 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8845 00:44:31.200750 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8846 00:44:31.207271 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8847 00:44:31.210801 1 4 8 | B1->B0 | 2524 3434 | 1 1 | (0 0) (1 1)
8848 00:44:31.214185 1 4 12 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
8849 00:44:31.220325 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8850 00:44:31.223857 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8851 00:44:31.227366 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8852 00:44:31.233539 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8853 00:44:31.237568 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8854 00:44:31.240583 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8855 00:44:31.246749 1 5 8 | B1->B0 | 3333 2323 | 0 0 | (0 1) (1 0)
8856 00:44:31.250207 1 5 12 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
8857 00:44:31.253951 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8858 00:44:31.260585 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8859 00:44:31.263579 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8860 00:44:31.267224 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8861 00:44:31.273748 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8862 00:44:31.277250 1 6 4 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
8863 00:44:31.280938 1 6 8 | B1->B0 | 2c2c 4646 | 0 0 | (0 0) (0 0)
8864 00:44:31.286931 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8865 00:44:31.290366 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8866 00:44:31.293797 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8867 00:44:31.296830 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8868 00:44:31.303420 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8869 00:44:31.306968 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8870 00:44:31.310497 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8871 00:44:31.317272 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8872 00:44:31.320560 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8873 00:44:31.323711 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8874 00:44:31.330152 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8875 00:44:31.333261 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8876 00:44:31.337118 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8877 00:44:31.343682 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8878 00:44:31.347115 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8879 00:44:31.350042 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8880 00:44:31.356736 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8881 00:44:31.360330 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8882 00:44:31.363506 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8883 00:44:31.369880 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8884 00:44:31.373184 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8885 00:44:31.376453 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8886 00:44:31.383017 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8887 00:44:31.386442 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8888 00:44:31.389582 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8889 00:44:31.396480 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8890 00:44:31.396960 Total UI for P1: 0, mck2ui 16
8891 00:44:31.403069 best dqsien dly found for B0: ( 1, 9, 8)
8892 00:44:31.403593 Total UI for P1: 0, mck2ui 16
8893 00:44:31.409901 best dqsien dly found for B1: ( 1, 9, 10)
8894 00:44:31.412712 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8895 00:44:31.416215 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8896 00:44:31.416615
8897 00:44:31.419518 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8898 00:44:31.422942 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8899 00:44:31.427018 [Gating] SW calibration Done
8900 00:44:31.427494 ==
8901 00:44:31.430011 Dram Type= 6, Freq= 0, CH_1, rank 1
8902 00:44:31.433067 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8903 00:44:31.433578 ==
8904 00:44:31.436356 RX Vref Scan: 0
8905 00:44:31.436873
8906 00:44:31.437282 RX Vref 0 -> 0, step: 1
8907 00:44:31.437664
8908 00:44:31.439555 RX Delay 0 -> 252, step: 8
8909 00:44:31.442974 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8910 00:44:31.449601 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8911 00:44:31.453203 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8912 00:44:31.456208 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8913 00:44:31.459633 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8914 00:44:31.463384 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8915 00:44:31.469361 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8916 00:44:31.472705 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8917 00:44:31.475956 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8918 00:44:31.479334 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8919 00:44:31.482706 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8920 00:44:31.489271 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8921 00:44:31.492530 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8922 00:44:31.495843 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8923 00:44:31.499222 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8924 00:44:31.502818 iDelay=200, Bit 15, Center 139 (80 ~ 199) 120
8925 00:44:31.505682 ==
8926 00:44:31.508934 Dram Type= 6, Freq= 0, CH_1, rank 1
8927 00:44:31.512265 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8928 00:44:31.512693 ==
8929 00:44:31.513017 DQS Delay:
8930 00:44:31.515990 DQS0 = 0, DQS1 = 0
8931 00:44:31.516387 DQM Delay:
8932 00:44:31.519192 DQM0 = 133, DQM1 = 128
8933 00:44:31.519594 DQ Delay:
8934 00:44:31.522554 DQ0 =135, DQ1 =131, DQ2 =119, DQ3 =131
8935 00:44:31.525964 DQ4 =131, DQ5 =143, DQ6 =143, DQ7 =131
8936 00:44:31.528898 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =123
8937 00:44:31.532337 DQ12 =131, DQ13 =139, DQ14 =131, DQ15 =139
8938 00:44:31.532835
8939 00:44:31.533296
8940 00:44:31.533711 ==
8941 00:44:31.535623 Dram Type= 6, Freq= 0, CH_1, rank 1
8942 00:44:31.542616 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8943 00:44:31.543069 ==
8944 00:44:31.543601
8945 00:44:31.543977
8946 00:44:31.544338 TX Vref Scan disable
8947 00:44:31.545986 == TX Byte 0 ==
8948 00:44:31.549465 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8949 00:44:31.555783 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8950 00:44:31.556235 == TX Byte 1 ==
8951 00:44:31.559268 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8952 00:44:31.565993 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8953 00:44:31.566441 ==
8954 00:44:31.568894 Dram Type= 6, Freq= 0, CH_1, rank 1
8955 00:44:31.572440 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8956 00:44:31.572914 ==
8957 00:44:31.584880
8958 00:44:31.588134 TX Vref early break, caculate TX vref
8959 00:44:31.591396 TX Vref=16, minBit 0, minWin=22, winSum=390
8960 00:44:31.594387 TX Vref=18, minBit 0, minWin=22, winSum=392
8961 00:44:31.598174 TX Vref=20, minBit 1, minWin=23, winSum=404
8962 00:44:31.601520 TX Vref=22, minBit 0, minWin=24, winSum=416
8963 00:44:31.604907 TX Vref=24, minBit 0, minWin=24, winSum=418
8964 00:44:31.611284 TX Vref=26, minBit 0, minWin=25, winSum=426
8965 00:44:31.614587 TX Vref=28, minBit 0, minWin=25, winSum=428
8966 00:44:31.617820 TX Vref=30, minBit 1, minWin=24, winSum=420
8967 00:44:31.621205 TX Vref=32, minBit 1, minWin=24, winSum=412
8968 00:44:31.624502 TX Vref=34, minBit 1, minWin=24, winSum=405
8969 00:44:31.631293 [TxChooseVref] Worse bit 0, Min win 25, Win sum 428, Final Vref 28
8970 00:44:31.631687
8971 00:44:31.634600 Final TX Range 0 Vref 28
8972 00:44:31.634993
8973 00:44:31.635301 ==
8974 00:44:31.637752 Dram Type= 6, Freq= 0, CH_1, rank 1
8975 00:44:31.640833 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8976 00:44:31.641373 ==
8977 00:44:31.641808
8978 00:44:31.642101
8979 00:44:31.644389 TX Vref Scan disable
8980 00:44:31.650890 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8981 00:44:31.651283 == TX Byte 0 ==
8982 00:44:31.654191 u2DelayCellOfst[0]=18 cells (5 PI)
8983 00:44:31.657702 u2DelayCellOfst[1]=15 cells (4 PI)
8984 00:44:31.661010 u2DelayCellOfst[2]=0 cells (0 PI)
8985 00:44:31.663916 u2DelayCellOfst[3]=7 cells (2 PI)
8986 00:44:31.667446 u2DelayCellOfst[4]=11 cells (3 PI)
8987 00:44:31.670992 u2DelayCellOfst[5]=22 cells (6 PI)
8988 00:44:31.674354 u2DelayCellOfst[6]=22 cells (6 PI)
8989 00:44:31.677381 u2DelayCellOfst[7]=7 cells (2 PI)
8990 00:44:31.680799 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8991 00:44:31.684028 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8992 00:44:31.687339 == TX Byte 1 ==
8993 00:44:31.687730 u2DelayCellOfst[8]=0 cells (0 PI)
8994 00:44:31.690583 u2DelayCellOfst[9]=7 cells (2 PI)
8995 00:44:31.694089 u2DelayCellOfst[10]=15 cells (4 PI)
8996 00:44:31.697023 u2DelayCellOfst[11]=7 cells (2 PI)
8997 00:44:31.700242 u2DelayCellOfst[12]=15 cells (4 PI)
8998 00:44:31.703551 u2DelayCellOfst[13]=18 cells (5 PI)
8999 00:44:31.706744 u2DelayCellOfst[14]=18 cells (5 PI)
9000 00:44:31.710194 u2DelayCellOfst[15]=18 cells (5 PI)
9001 00:44:31.713805 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
9002 00:44:31.720079 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
9003 00:44:31.720217 DramC Write-DBI on
9004 00:44:31.720310 ==
9005 00:44:31.723503 Dram Type= 6, Freq= 0, CH_1, rank 1
9006 00:44:31.730499 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9007 00:44:31.730662 ==
9008 00:44:31.730762
9009 00:44:31.730848
9010 00:44:31.730931 TX Vref Scan disable
9011 00:44:31.734069 == TX Byte 0 ==
9012 00:44:31.737315 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
9013 00:44:31.740309 == TX Byte 1 ==
9014 00:44:31.744029 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
9015 00:44:31.746885 DramC Write-DBI off
9016 00:44:31.747045
9017 00:44:31.747172 [DATLAT]
9018 00:44:31.747289 Freq=1600, CH1 RK1
9019 00:44:31.747403
9020 00:44:31.750332 DATLAT Default: 0xf
9021 00:44:31.750520 0, 0xFFFF, sum = 0
9022 00:44:31.753843 1, 0xFFFF, sum = 0
9023 00:44:31.756893 2, 0xFFFF, sum = 0
9024 00:44:31.757119 3, 0xFFFF, sum = 0
9025 00:44:31.760443 4, 0xFFFF, sum = 0
9026 00:44:31.760745 5, 0xFFFF, sum = 0
9027 00:44:31.763650 6, 0xFFFF, sum = 0
9028 00:44:31.764012 7, 0xFFFF, sum = 0
9029 00:44:31.767187 8, 0xFFFF, sum = 0
9030 00:44:31.767552 9, 0xFFFF, sum = 0
9031 00:44:31.770301 10, 0xFFFF, sum = 0
9032 00:44:31.770832 11, 0xFFFF, sum = 0
9033 00:44:31.773474 12, 0xFFFF, sum = 0
9034 00:44:31.773869 13, 0x8FFF, sum = 0
9035 00:44:31.777169 14, 0x0, sum = 1
9036 00:44:31.777563 15, 0x0, sum = 2
9037 00:44:31.780086 16, 0x0, sum = 3
9038 00:44:31.780486 17, 0x0, sum = 4
9039 00:44:31.783622 best_step = 15
9040 00:44:31.784027
9041 00:44:31.784354 ==
9042 00:44:31.786851 Dram Type= 6, Freq= 0, CH_1, rank 1
9043 00:44:31.790662 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9044 00:44:31.791055 ==
9045 00:44:31.793485 RX Vref Scan: 0
9046 00:44:31.793875
9047 00:44:31.794180 RX Vref 0 -> 0, step: 1
9048 00:44:31.794466
9049 00:44:31.796803 RX Delay 11 -> 252, step: 4
9050 00:44:31.803710 iDelay=195, Bit 0, Center 134 (83 ~ 186) 104
9051 00:44:31.806849 iDelay=195, Bit 1, Center 128 (79 ~ 178) 100
9052 00:44:31.810196 iDelay=195, Bit 2, Center 118 (67 ~ 170) 104
9053 00:44:31.813796 iDelay=195, Bit 3, Center 126 (75 ~ 178) 104
9054 00:44:31.816554 iDelay=195, Bit 4, Center 126 (71 ~ 182) 112
9055 00:44:31.820070 iDelay=195, Bit 5, Center 142 (91 ~ 194) 104
9056 00:44:31.826938 iDelay=195, Bit 6, Center 140 (87 ~ 194) 108
9057 00:44:31.829884 iDelay=195, Bit 7, Center 124 (71 ~ 178) 108
9058 00:44:31.834007 iDelay=195, Bit 8, Center 112 (55 ~ 170) 116
9059 00:44:31.836665 iDelay=195, Bit 9, Center 114 (63 ~ 166) 104
9060 00:44:31.843515 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
9061 00:44:31.846882 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
9062 00:44:31.850088 iDelay=195, Bit 12, Center 134 (79 ~ 190) 112
9063 00:44:31.853469 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
9064 00:44:31.856698 iDelay=195, Bit 14, Center 132 (79 ~ 186) 108
9065 00:44:31.863041 iDelay=195, Bit 15, Center 134 (79 ~ 190) 112
9066 00:44:31.863448 ==
9067 00:44:31.866453 Dram Type= 6, Freq= 0, CH_1, rank 1
9068 00:44:31.870175 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9069 00:44:31.870602 ==
9070 00:44:31.871085 DQS Delay:
9071 00:44:31.873076 DQS0 = 0, DQS1 = 0
9072 00:44:31.873473 DQM Delay:
9073 00:44:31.876708 DQM0 = 129, DQM1 = 125
9074 00:44:31.877114 DQ Delay:
9075 00:44:31.879763 DQ0 =134, DQ1 =128, DQ2 =118, DQ3 =126
9076 00:44:31.882954 DQ4 =126, DQ5 =142, DQ6 =140, DQ7 =124
9077 00:44:31.886573 DQ8 =112, DQ9 =114, DQ10 =128, DQ11 =120
9078 00:44:31.889909 DQ12 =134, DQ13 =132, DQ14 =132, DQ15 =134
9079 00:44:31.890302
9080 00:44:31.890612
9081 00:44:31.893094
9082 00:44:31.893570 [DramC_TX_OE_Calibration] TA2
9083 00:44:31.896562 Original DQ_B0 (3 6) =30, OEN = 27
9084 00:44:31.899481 Original DQ_B1 (3 6) =30, OEN = 27
9085 00:44:31.902971 24, 0x0, End_B0=24 End_B1=24
9086 00:44:31.906373 25, 0x0, End_B0=25 End_B1=25
9087 00:44:31.909660 26, 0x0, End_B0=26 End_B1=26
9088 00:44:31.910057 27, 0x0, End_B0=27 End_B1=27
9089 00:44:31.912953 28, 0x0, End_B0=28 End_B1=28
9090 00:44:31.916539 29, 0x0, End_B0=29 End_B1=29
9091 00:44:31.919543 30, 0x0, End_B0=30 End_B1=30
9092 00:44:31.920071 31, 0x4141, End_B0=30 End_B1=30
9093 00:44:31.922986 Byte0 end_step=30 best_step=27
9094 00:44:31.926569 Byte1 end_step=30 best_step=27
9095 00:44:31.930040 Byte0 TX OE(2T, 0.5T) = (3, 3)
9096 00:44:31.932877 Byte1 TX OE(2T, 0.5T) = (3, 3)
9097 00:44:31.933266
9098 00:44:31.933611
9099 00:44:31.939752 [DQSOSCAuto] RK1, (LSB)MR18= 0x111c, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 401 ps
9100 00:44:31.943282 CH1 RK1: MR19=303, MR18=111C
9101 00:44:31.949642 CH1_RK1: MR19=0x303, MR18=0x111C, DQSOSC=395, MR23=63, INC=23, DEC=15
9102 00:44:31.953017 [RxdqsGatingPostProcess] freq 1600
9103 00:44:31.959547 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9104 00:44:31.962520 best DQS0 dly(2T, 0.5T) = (1, 1)
9105 00:44:31.962909 best DQS1 dly(2T, 0.5T) = (1, 1)
9106 00:44:31.965894 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9107 00:44:31.969387 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9108 00:44:31.972766 best DQS0 dly(2T, 0.5T) = (1, 1)
9109 00:44:31.975977 best DQS1 dly(2T, 0.5T) = (1, 1)
9110 00:44:31.979123 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9111 00:44:31.982570 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9112 00:44:31.985830 Pre-setting of DQS Precalculation
9113 00:44:31.992273 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9114 00:44:31.998850 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9115 00:44:32.005667 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9116 00:44:32.006064
9117 00:44:32.006372
9118 00:44:32.008906 [Calibration Summary] 3200 Mbps
9119 00:44:32.009295 CH 0, Rank 0
9120 00:44:32.012373 SW Impedance : PASS
9121 00:44:32.015532 DUTY Scan : NO K
9122 00:44:32.015920 ZQ Calibration : PASS
9123 00:44:32.019066 Jitter Meter : NO K
9124 00:44:32.019645 CBT Training : PASS
9125 00:44:32.022352 Write leveling : PASS
9126 00:44:32.025504 RX DQS gating : PASS
9127 00:44:32.025967 RX DQ/DQS(RDDQC) : PASS
9128 00:44:32.029048 TX DQ/DQS : PASS
9129 00:44:32.032091 RX DATLAT : PASS
9130 00:44:32.032494 RX DQ/DQS(Engine): PASS
9131 00:44:32.036112 TX OE : PASS
9132 00:44:32.036624 All Pass.
9133 00:44:32.037109
9134 00:44:32.038839 CH 0, Rank 1
9135 00:44:32.039340 SW Impedance : PASS
9136 00:44:32.042504 DUTY Scan : NO K
9137 00:44:32.045682 ZQ Calibration : PASS
9138 00:44:32.046291 Jitter Meter : NO K
9139 00:44:32.048352 CBT Training : PASS
9140 00:44:32.051963 Write leveling : PASS
9141 00:44:32.052347 RX DQS gating : PASS
9142 00:44:32.055388 RX DQ/DQS(RDDQC) : PASS
9143 00:44:32.058808 TX DQ/DQS : PASS
9144 00:44:32.059196 RX DATLAT : PASS
9145 00:44:32.062172 RX DQ/DQS(Engine): PASS
9146 00:44:32.065418 TX OE : PASS
9147 00:44:32.065807 All Pass.
9148 00:44:32.066137
9149 00:44:32.066416 CH 1, Rank 0
9150 00:44:32.068927 SW Impedance : PASS
9151 00:44:32.071871 DUTY Scan : NO K
9152 00:44:32.072257 ZQ Calibration : PASS
9153 00:44:32.075217 Jitter Meter : NO K
9154 00:44:32.078597 CBT Training : PASS
9155 00:44:32.078983 Write leveling : PASS
9156 00:44:32.081829 RX DQS gating : PASS
9157 00:44:32.082378 RX DQ/DQS(RDDQC) : PASS
9158 00:44:32.085153 TX DQ/DQS : PASS
9159 00:44:32.088212 RX DATLAT : PASS
9160 00:44:32.088603 RX DQ/DQS(Engine): PASS
9161 00:44:32.091529 TX OE : PASS
9162 00:44:32.091976 All Pass.
9163 00:44:32.092281
9164 00:44:32.094817 CH 1, Rank 1
9165 00:44:32.095382 SW Impedance : PASS
9166 00:44:32.098329 DUTY Scan : NO K
9167 00:44:32.101596 ZQ Calibration : PASS
9168 00:44:32.101986 Jitter Meter : NO K
9169 00:44:32.105010 CBT Training : PASS
9170 00:44:32.108426 Write leveling : PASS
9171 00:44:32.108866 RX DQS gating : PASS
9172 00:44:32.111881 RX DQ/DQS(RDDQC) : PASS
9173 00:44:32.114935 TX DQ/DQS : PASS
9174 00:44:32.115384 RX DATLAT : PASS
9175 00:44:32.118240 RX DQ/DQS(Engine): PASS
9176 00:44:32.121686 TX OE : PASS
9177 00:44:32.122078 All Pass.
9178 00:44:32.122398
9179 00:44:32.122816 DramC Write-DBI on
9180 00:44:32.125006 PER_BANK_REFRESH: Hybrid Mode
9181 00:44:32.128309 TX_TRACKING: ON
9182 00:44:32.134446 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9183 00:44:32.144491 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9184 00:44:32.151063 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9185 00:44:32.154583 [FAST_K] Save calibration result to emmc
9186 00:44:32.158067 sync common calibartion params.
9187 00:44:32.160973 sync cbt_mode0:1, 1:1
9188 00:44:32.161592 dram_init: ddr_geometry: 2
9189 00:44:32.164761 dram_init: ddr_geometry: 2
9190 00:44:32.168364 dram_init: ddr_geometry: 2
9191 00:44:32.168784 0:dram_rank_size:100000000
9192 00:44:32.171264 1:dram_rank_size:100000000
9193 00:44:32.177948 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9194 00:44:32.181440 DFS_SHUFFLE_HW_MODE: ON
9195 00:44:32.184198 dramc_set_vcore_voltage set vcore to 725000
9196 00:44:32.184585 Read voltage for 1600, 0
9197 00:44:32.187578 Vio18 = 0
9198 00:44:32.187965 Vcore = 725000
9199 00:44:32.188265 Vdram = 0
9200 00:44:32.191056 Vddq = 0
9201 00:44:32.191441 Vmddr = 0
9202 00:44:32.194324 switch to 3200 Mbps bootup
9203 00:44:32.194711 [DramcRunTimeConfig]
9204 00:44:32.195011 PHYPLL
9205 00:44:32.197892 DPM_CONTROL_AFTERK: ON
9206 00:44:32.200737 PER_BANK_REFRESH: ON
9207 00:44:32.201128 REFRESH_OVERHEAD_REDUCTION: ON
9208 00:44:32.204246 CMD_PICG_NEW_MODE: OFF
9209 00:44:32.207514 XRTWTW_NEW_MODE: ON
9210 00:44:32.207899 XRTRTR_NEW_MODE: ON
9211 00:44:32.210722 TX_TRACKING: ON
9212 00:44:32.211139 RDSEL_TRACKING: OFF
9213 00:44:32.214303 DQS Precalculation for DVFS: ON
9214 00:44:32.214691 RX_TRACKING: OFF
9215 00:44:32.217767 HW_GATING DBG: ON
9216 00:44:32.220601 ZQCS_ENABLE_LP4: ON
9217 00:44:32.221023 RX_PICG_NEW_MODE: ON
9218 00:44:32.224059 TX_PICG_NEW_MODE: ON
9219 00:44:32.224447 ENABLE_RX_DCM_DPHY: ON
9220 00:44:32.227413 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9221 00:44:32.230763 DUMMY_READ_FOR_TRACKING: OFF
9222 00:44:32.234132 !!! SPM_CONTROL_AFTERK: OFF
9223 00:44:32.237369 !!! SPM could not control APHY
9224 00:44:32.237922 IMPEDANCE_TRACKING: ON
9225 00:44:32.240420 TEMP_SENSOR: ON
9226 00:44:32.240901 HW_SAVE_FOR_SR: OFF
9227 00:44:32.243741 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9228 00:44:32.247086 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9229 00:44:32.250412 Read ODT Tracking: ON
9230 00:44:32.253881 Refresh Rate DeBounce: ON
9231 00:44:32.254271 DFS_NO_QUEUE_FLUSH: ON
9232 00:44:32.256813 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9233 00:44:32.260228 ENABLE_DFS_RUNTIME_MRW: OFF
9234 00:44:32.263673 DDR_RESERVE_NEW_MODE: ON
9235 00:44:32.264067 MR_CBT_SWITCH_FREQ: ON
9236 00:44:32.267168 =========================
9237 00:44:32.285531 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9238 00:44:32.289073 dram_init: ddr_geometry: 2
9239 00:44:32.307371 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9240 00:44:32.310298 dram_init: dram init end (result: 0)
9241 00:44:32.316980 DRAM-K: Full calibration passed in 24596 msecs
9242 00:44:32.320349 MRC: failed to locate region type 0.
9243 00:44:32.320770 DRAM rank0 size:0x100000000,
9244 00:44:32.323927 DRAM rank1 size=0x100000000
9245 00:44:32.333544 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9246 00:44:32.340181 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9247 00:44:32.346667 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9248 00:44:32.353214 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9249 00:44:32.356536 DRAM rank0 size:0x100000000,
9250 00:44:32.360212 DRAM rank1 size=0x100000000
9251 00:44:32.360610 CBMEM:
9252 00:44:32.363349 IMD: root @ 0xfffff000 254 entries.
9253 00:44:32.366748 IMD: root @ 0xffffec00 62 entries.
9254 00:44:32.370179 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9255 00:44:32.376531 WARNING: RO_VPD is uninitialized or empty.
9256 00:44:32.379995 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9257 00:44:32.387408 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9258 00:44:32.400240 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9259 00:44:32.412265 BS: romstage times (exec / console): total (unknown) / 24057 ms
9260 00:44:32.412699
9261 00:44:32.413018
9262 00:44:32.422084 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9263 00:44:32.424706 ARM64: Exception handlers installed.
9264 00:44:32.427765 ARM64: Testing exception
9265 00:44:32.431195 ARM64: Done test exception
9266 00:44:32.431588 Enumerating buses...
9267 00:44:32.434524 Show all devs... Before device enumeration.
9268 00:44:32.437881 Root Device: enabled 1
9269 00:44:32.441391 CPU_CLUSTER: 0: enabled 1
9270 00:44:32.441782 CPU: 00: enabled 1
9271 00:44:32.444603 Compare with tree...
9272 00:44:32.445020 Root Device: enabled 1
9273 00:44:32.448031 CPU_CLUSTER: 0: enabled 1
9274 00:44:32.450882 CPU: 00: enabled 1
9275 00:44:32.451272 Root Device scanning...
9276 00:44:32.454742 scan_static_bus for Root Device
9277 00:44:32.457953 CPU_CLUSTER: 0 enabled
9278 00:44:32.461228 scan_static_bus for Root Device done
9279 00:44:32.464208 scan_bus: bus Root Device finished in 8 msecs
9280 00:44:32.464600 done
9281 00:44:32.470809 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9282 00:44:32.474362 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9283 00:44:32.480880 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9284 00:44:32.484298 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9285 00:44:32.487311 Allocating resources...
9286 00:44:32.490773 Reading resources...
9287 00:44:32.494385 Root Device read_resources bus 0 link: 0
9288 00:44:32.494462 DRAM rank0 size:0x100000000,
9289 00:44:32.497819 DRAM rank1 size=0x100000000
9290 00:44:32.500568 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9291 00:44:32.503964 CPU: 00 missing read_resources
9292 00:44:32.507549 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9293 00:44:32.513890 Root Device read_resources bus 0 link: 0 done
9294 00:44:32.513966 Done reading resources.
9295 00:44:32.520773 Show resources in subtree (Root Device)...After reading.
9296 00:44:32.524026 Root Device child on link 0 CPU_CLUSTER: 0
9297 00:44:32.527254 CPU_CLUSTER: 0 child on link 0 CPU: 00
9298 00:44:32.537558 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9299 00:44:32.537635 CPU: 00
9300 00:44:32.540580 Root Device assign_resources, bus 0 link: 0
9301 00:44:32.543803 CPU_CLUSTER: 0 missing set_resources
9302 00:44:32.547351 Root Device assign_resources, bus 0 link: 0 done
9303 00:44:32.550408 Done setting resources.
9304 00:44:32.557018 Show resources in subtree (Root Device)...After assigning values.
9305 00:44:32.560238 Root Device child on link 0 CPU_CLUSTER: 0
9306 00:44:32.563992 CPU_CLUSTER: 0 child on link 0 CPU: 00
9307 00:44:32.573680 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9308 00:44:32.573770 CPU: 00
9309 00:44:32.576877 Done allocating resources.
9310 00:44:32.580124 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9311 00:44:32.583555 Enabling resources...
9312 00:44:32.583676 done.
9313 00:44:32.590387 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9314 00:44:32.590516 Initializing devices...
9315 00:44:32.593785 Root Device init
9316 00:44:32.593920 init hardware done!
9317 00:44:32.597130 0x00000018: ctrlr->caps
9318 00:44:32.600535 52.000 MHz: ctrlr->f_max
9319 00:44:32.600702 0.400 MHz: ctrlr->f_min
9320 00:44:32.603436 0x40ff8080: ctrlr->voltages
9321 00:44:32.603604 sclk: 390625
9322 00:44:32.606947 Bus Width = 1
9323 00:44:32.607109 sclk: 390625
9324 00:44:32.610303 Bus Width = 1
9325 00:44:32.610487 Early init status = 3
9326 00:44:32.616928 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9327 00:44:32.619937 in-header: 03 fc 00 00 01 00 00 00
9328 00:44:32.623374 in-data: 00
9329 00:44:32.626730 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9330 00:44:32.631923 in-header: 03 fd 00 00 00 00 00 00
9331 00:44:32.635529 in-data:
9332 00:44:32.638836 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9333 00:44:32.643025 in-header: 03 fc 00 00 01 00 00 00
9334 00:44:32.646429 in-data: 00
9335 00:44:32.649404 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9336 00:44:32.655611 in-header: 03 fd 00 00 00 00 00 00
9337 00:44:32.658416 in-data:
9338 00:44:32.661780 [SSUSB] Setting up USB HOST controller...
9339 00:44:32.665029 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9340 00:44:32.668145 [SSUSB] phy power-on done.
9341 00:44:32.671465 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9342 00:44:32.678509 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9343 00:44:32.681782 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9344 00:44:32.688455 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9345 00:44:32.694910 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9346 00:44:32.701496 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9347 00:44:32.708457 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9348 00:44:32.714717 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9349 00:44:32.718388 SPM: binary array size = 0x9dc
9350 00:44:32.721573 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9351 00:44:32.728547 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9352 00:44:32.734505 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9353 00:44:32.741388 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9354 00:44:32.744634 configure_display: Starting display init
9355 00:44:32.779069 anx7625_power_on_init: Init interface.
9356 00:44:32.781820 anx7625_disable_pd_protocol: Disabled PD feature.
9357 00:44:32.784958 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9358 00:44:32.813230 anx7625_start_dp_work: Secure OCM version=00
9359 00:44:32.816292 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9360 00:44:32.831181 sp_tx_get_edid_block: EDID Block = 1
9361 00:44:32.933635 Extracted contents:
9362 00:44:32.936966 header: 00 ff ff ff ff ff ff 00
9363 00:44:32.940624 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9364 00:44:32.943810 version: 01 04
9365 00:44:32.946882 basic params: 95 1f 11 78 0a
9366 00:44:32.950569 chroma info: 76 90 94 55 54 90 27 21 50 54
9367 00:44:32.953341 established: 00 00 00
9368 00:44:32.960044 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9369 00:44:32.963712 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9370 00:44:32.970221 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9371 00:44:32.976640 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9372 00:44:32.983340 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9373 00:44:32.986734 extensions: 00
9374 00:44:32.987181 checksum: fb
9375 00:44:32.987535
9376 00:44:32.989890 Manufacturer: IVO Model 57d Serial Number 0
9377 00:44:32.993592 Made week 0 of 2020
9378 00:44:32.994094 EDID version: 1.4
9379 00:44:32.996808 Digital display
9380 00:44:33.000110 6 bits per primary color channel
9381 00:44:33.000621 DisplayPort interface
9382 00:44:33.003516 Maximum image size: 31 cm x 17 cm
9383 00:44:33.006568 Gamma: 220%
9384 00:44:33.006993 Check DPMS levels
9385 00:44:33.009568 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9386 00:44:33.016092 First detailed timing is preferred timing
9387 00:44:33.016584 Established timings supported:
9388 00:44:33.019908 Standard timings supported:
9389 00:44:33.023008 Detailed timings
9390 00:44:33.026487 Hex of detail: 383680a07038204018303c0035ae10000019
9391 00:44:33.029452 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9392 00:44:33.036456 0780 0798 07c8 0820 hborder 0
9393 00:44:33.039709 0438 043b 0447 0458 vborder 0
9394 00:44:33.042633 -hsync -vsync
9395 00:44:33.043062 Did detailed timing
9396 00:44:33.049562 Hex of detail: 000000000000000000000000000000000000
9397 00:44:33.053336 Manufacturer-specified data, tag 0
9398 00:44:33.055901 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9399 00:44:33.059455 ASCII string: InfoVision
9400 00:44:33.062611 Hex of detail: 000000fe00523134304e574635205248200a
9401 00:44:33.065891 ASCII string: R140NWF5 RH
9402 00:44:33.066316 Checksum
9403 00:44:33.069319 Checksum: 0xfb (valid)
9404 00:44:33.072365 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9405 00:44:33.076228 DSI data_rate: 832800000 bps
9406 00:44:33.082684 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9407 00:44:33.085845 anx7625_parse_edid: pixelclock(138800).
9408 00:44:33.088807 hactive(1920), hsync(48), hfp(24), hbp(88)
9409 00:44:33.092521 vactive(1080), vsync(12), vfp(3), vbp(17)
9410 00:44:33.095470 anx7625_dsi_config: config dsi.
9411 00:44:33.102595 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9412 00:44:33.115719 anx7625_dsi_config: success to config DSI
9413 00:44:33.119213 anx7625_dp_start: MIPI phy setup OK.
9414 00:44:33.122596 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9415 00:44:33.125780 mtk_ddp_mode_set invalid vrefresh 60
9416 00:44:33.128985 main_disp_path_setup
9417 00:44:33.129416 ovl_layer_smi_id_en
9418 00:44:33.132241 ovl_layer_smi_id_en
9419 00:44:33.132715 ccorr_config
9420 00:44:33.133056 aal_config
9421 00:44:33.135504 gamma_config
9422 00:44:33.135928 postmask_config
9423 00:44:33.138535 dither_config
9424 00:44:33.142140 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9425 00:44:33.148607 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9426 00:44:33.151849 Root Device init finished in 555 msecs
9427 00:44:33.155165 CPU_CLUSTER: 0 init
9428 00:44:33.162270 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9429 00:44:33.165472 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9430 00:44:33.168338 APU_MBOX 0x190000b0 = 0x10001
9431 00:44:33.172080 APU_MBOX 0x190001b0 = 0x10001
9432 00:44:33.175576 APU_MBOX 0x190005b0 = 0x10001
9433 00:44:33.178631 APU_MBOX 0x190006b0 = 0x10001
9434 00:44:33.184841 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9435 00:44:33.194780 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9436 00:44:33.207006 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9437 00:44:33.213634 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9438 00:44:33.225552 read SPI 0x61c74 0xe8ef: 6411 us, 9301 KB/s, 74.408 Mbps
9439 00:44:33.234547 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9440 00:44:33.237330 CPU_CLUSTER: 0 init finished in 81 msecs
9441 00:44:33.240994 Devices initialized
9442 00:44:33.244520 Show all devs... After init.
9443 00:44:33.245123 Root Device: enabled 1
9444 00:44:33.247572 CPU_CLUSTER: 0: enabled 1
9445 00:44:33.251317 CPU: 00: enabled 1
9446 00:44:33.254222 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9447 00:44:33.257322 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9448 00:44:33.260886 ELOG: NV offset 0x57f000 size 0x1000
9449 00:44:33.267897 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9450 00:44:33.274122 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9451 00:44:33.277504 ELOG: Event(17) added with size 13 at 2024-06-16 00:44:33 UTC
9452 00:44:33.280929 out: cmd=0x121: 03 db 21 01 00 00 00 00
9453 00:44:33.284983 in-header: 03 5b 00 00 2c 00 00 00
9454 00:44:33.297886 in-data: e2 72 00 00 00 00 00 00 0a 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9455 00:44:33.304917 ELOG: Event(A1) added with size 10 at 2024-06-16 00:44:33 UTC
9456 00:44:33.311074 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
9457 00:44:33.317599 ELOG: Event(A0) added with size 9 at 2024-06-16 00:44:33 UTC
9458 00:44:33.321099 elog_add_boot_reason: Logged dev mode boot
9459 00:44:33.324678 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9460 00:44:33.328008 Finalize devices...
9461 00:44:33.328525 Devices finalized
9462 00:44:33.334538 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9463 00:44:33.337777 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
9464 00:44:33.341001 in-header: 03 07 00 00 08 00 00 00
9465 00:44:33.344008 in-data: aa e4 47 04 13 02 00 00
9466 00:44:33.347289 Chrome EC: UHEPI supported
9467 00:44:33.354334 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
9468 00:44:33.357575 in-header: 03 a9 00 00 08 00 00 00
9469 00:44:33.361126 in-data: 84 60 60 08 00 00 00 00
9470 00:44:33.364014 ELOG: Event(91) added with size 10 at 2024-06-16 00:44:33 UTC
9471 00:44:33.370622 Chrome EC: clear events_b mask to 0x0000000020004000
9472 00:44:33.378140 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
9473 00:44:33.381035 in-header: 03 fd 00 00 00 00 00 00
9474 00:44:33.381473 in-data:
9475 00:44:33.387589 BS: BS_WRITE_TABLES entry times (exec / console): 2 / 46 ms
9476 00:44:33.391040 Writing coreboot table at 0xffe64000
9477 00:44:33.394031 0. 000000000010a000-0000000000113fff: RAMSTAGE
9478 00:44:33.397432 1. 0000000040000000-00000000400fffff: RAM
9479 00:44:33.400835 2. 0000000040100000-000000004032afff: RAMSTAGE
9480 00:44:33.407255 3. 000000004032b000-00000000545fffff: RAM
9481 00:44:33.410447 4. 0000000054600000-000000005465ffff: BL31
9482 00:44:33.414024 5. 0000000054660000-00000000ffe63fff: RAM
9483 00:44:33.420428 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9484 00:44:33.424006 7. 0000000100000000-000000023fffffff: RAM
9485 00:44:33.424472 Passing 5 GPIOs to payload:
9486 00:44:33.430242 NAME | PORT | POLARITY | VALUE
9487 00:44:33.433792 EC in RW | 0x000000aa | low | undefined
9488 00:44:33.440623 EC interrupt | 0x00000005 | low | undefined
9489 00:44:33.443727 TPM interrupt | 0x000000ab | high | undefined
9490 00:44:33.447163 SD card detect | 0x00000011 | high | undefined
9491 00:44:33.453878 speaker enable | 0x00000093 | high | undefined
9492 00:44:33.457214 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9493 00:44:33.460578 in-header: 03 f9 00 00 02 00 00 00
9494 00:44:33.461056 in-data: 02 00
9495 00:44:33.463535 ADC[4]: Raw value=894821 ID=7
9496 00:44:33.467047 ADC[3]: Raw value=212700 ID=1
9497 00:44:33.467488 RAM Code: 0x71
9498 00:44:33.470812 ADC[6]: Raw value=74722 ID=0
9499 00:44:33.473954 ADC[5]: Raw value=211960 ID=1
9500 00:44:33.474385 SKU Code: 0x1
9501 00:44:33.480382 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 19b9
9502 00:44:33.483797 coreboot table: 964 bytes.
9503 00:44:33.486798 IMD ROOT 0. 0xfffff000 0x00001000
9504 00:44:33.490368 IMD SMALL 1. 0xffffe000 0x00001000
9505 00:44:33.493379 RO MCACHE 2. 0xffffc000 0x00001104
9506 00:44:33.497629 CONSOLE 3. 0xfff7c000 0x00080000
9507 00:44:33.500344 FMAP 4. 0xfff7b000 0x00000452
9508 00:44:33.503756 TIME STAMP 5. 0xfff7a000 0x00000910
9509 00:44:33.506932 VBOOT WORK 6. 0xfff66000 0x00014000
9510 00:44:33.510607 RAMOOPS 7. 0xffe66000 0x00100000
9511 00:44:33.513364 COREBOOT 8. 0xffe64000 0x00002000
9512 00:44:33.513753 IMD small region:
9513 00:44:33.516578 IMD ROOT 0. 0xffffec00 0x00000400
9514 00:44:33.520316 VPD 1. 0xffffeb80 0x0000006c
9515 00:44:33.523411 MMC STATUS 2. 0xffffeb60 0x00000004
9516 00:44:33.529802 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9517 00:44:33.536717 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9518 00:44:33.576872 read SPI 0x3990ec 0x4f1b0: 34847 us, 9298 KB/s, 74.384 Mbps
9519 00:44:33.579686 Checking segment from ROM address 0x40100000
9520 00:44:33.583190 Checking segment from ROM address 0x4010001c
9521 00:44:33.589839 Loading segment from ROM address 0x40100000
9522 00:44:33.590329 code (compression=0)
9523 00:44:33.599911 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9524 00:44:33.606311 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9525 00:44:33.606820 it's not compressed!
9526 00:44:33.612947 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9527 00:44:33.619507 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9528 00:44:33.636768 Loading segment from ROM address 0x4010001c
9529 00:44:33.637287 Entry Point 0x80000000
9530 00:44:33.640093 Loaded segments
9531 00:44:33.643154 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9532 00:44:33.649997 Jumping to boot code at 0x80000000(0xffe64000)
9533 00:44:33.656140 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9534 00:44:33.662458 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9535 00:44:33.670410 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9536 00:44:33.673831 Checking segment from ROM address 0x40100000
9537 00:44:33.676994 Checking segment from ROM address 0x4010001c
9538 00:44:33.684113 Loading segment from ROM address 0x40100000
9539 00:44:33.684190 code (compression=1)
9540 00:44:33.690650 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9541 00:44:33.700367 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9542 00:44:33.700462 using LZMA
9543 00:44:33.709171 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9544 00:44:33.715616 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9545 00:44:33.719351 Loading segment from ROM address 0x4010001c
9546 00:44:33.719557 Entry Point 0x54601000
9547 00:44:33.722660 Loaded segments
9548 00:44:33.725984 NOTICE: MT8192 bl31_setup
9549 00:44:33.732926 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9550 00:44:33.736464 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9551 00:44:33.739945 WARNING: region 0:
9552 00:44:33.742740 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9553 00:44:33.743037 WARNING: region 1:
9554 00:44:33.749708 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9555 00:44:33.753154 WARNING: region 2:
9556 00:44:33.755995 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9557 00:44:33.759467 WARNING: region 3:
9558 00:44:33.762954 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9559 00:44:33.766390 WARNING: region 4:
9560 00:44:33.772698 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9561 00:44:33.773129 WARNING: region 5:
9562 00:44:33.776190 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9563 00:44:33.779678 WARNING: region 6:
9564 00:44:33.782587 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9565 00:44:33.786184 WARNING: region 7:
9566 00:44:33.789198 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9567 00:44:33.795832 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9568 00:44:33.799338 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9569 00:44:33.802677 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9570 00:44:33.809868 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9571 00:44:33.812783 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9572 00:44:33.819505 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9573 00:44:33.822829 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9574 00:44:33.825737 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9575 00:44:33.832726 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9576 00:44:33.835939 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9577 00:44:33.839370 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9578 00:44:33.846045 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9579 00:44:33.849842 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9580 00:44:33.855665 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9581 00:44:33.858997 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9582 00:44:33.862279 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9583 00:44:33.869107 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9584 00:44:33.872379 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9585 00:44:33.878824 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9586 00:44:33.882597 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9587 00:44:33.885674 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9588 00:44:33.892310 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9589 00:44:33.895827 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9590 00:44:33.898433 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9591 00:44:33.905362 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9592 00:44:33.908884 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9593 00:44:33.915419 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9594 00:44:33.918236 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9595 00:44:33.925383 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9596 00:44:33.928233 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9597 00:44:33.931718 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9598 00:44:33.938713 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9599 00:44:33.941793 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9600 00:44:33.944943 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9601 00:44:33.948233 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9602 00:44:33.955205 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9603 00:44:33.958300 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9604 00:44:33.961672 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9605 00:44:33.964899 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9606 00:44:33.971362 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9607 00:44:33.974723 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9608 00:44:33.978964 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9609 00:44:33.981108 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9610 00:44:33.988165 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9611 00:44:33.991619 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9612 00:44:33.994516 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9613 00:44:34.001322 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9614 00:44:34.004616 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9615 00:44:34.007823 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9616 00:44:34.014193 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9617 00:44:34.017620 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9618 00:44:34.024341 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9619 00:44:34.027536 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9620 00:44:34.030598 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9621 00:44:34.037330 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9622 00:44:34.040708 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9623 00:44:34.047353 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9624 00:44:34.050726 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9625 00:44:34.057087 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9626 00:44:34.060466 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9627 00:44:34.066836 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9628 00:44:34.070240 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9629 00:44:34.073872 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9630 00:44:34.080314 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9631 00:44:34.084375 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9632 00:44:34.090438 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9633 00:44:34.093561 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9634 00:44:34.100072 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9635 00:44:34.103406 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9636 00:44:34.110138 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9637 00:44:34.113683 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9638 00:44:34.117059 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9639 00:44:34.123407 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9640 00:44:34.126874 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9641 00:44:34.133021 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9642 00:44:34.136577 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9643 00:44:34.143398 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9644 00:44:34.146211 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9645 00:44:34.152759 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9646 00:44:34.156474 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9647 00:44:34.163021 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9648 00:44:34.166473 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9649 00:44:34.169493 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9650 00:44:34.176003 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9651 00:44:34.179489 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9652 00:44:34.185828 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9653 00:44:34.189327 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9654 00:44:34.196186 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9655 00:44:34.199176 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9656 00:44:34.202673 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9657 00:44:34.209243 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9658 00:44:34.212393 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9659 00:44:34.218958 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9660 00:44:34.222344 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9661 00:44:34.228874 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9662 00:44:34.231700 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9663 00:44:34.235213 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9664 00:44:34.241908 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9665 00:44:34.245381 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9666 00:44:34.248396 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9667 00:44:34.251842 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9668 00:44:34.258316 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9669 00:44:34.261861 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9670 00:44:34.268200 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9671 00:44:34.271733 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9672 00:44:34.275257 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9673 00:44:34.281412 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9674 00:44:34.284823 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9675 00:44:34.291168 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9676 00:44:34.294748 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9677 00:44:34.301073 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9678 00:44:34.304628 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9679 00:44:34.307936 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9680 00:44:34.314851 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9681 00:44:34.317613 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9682 00:44:34.324168 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9683 00:44:34.327844 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9684 00:44:34.330774 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9685 00:44:34.337567 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9686 00:44:34.340874 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9687 00:44:34.344819 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9688 00:44:34.347708 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9689 00:44:34.351064 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9690 00:44:34.357793 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9691 00:44:34.360844 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9692 00:44:34.367328 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9693 00:44:34.370730 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9694 00:44:34.373908 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9695 00:44:34.380847 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9696 00:44:34.383708 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9697 00:44:34.390569 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9698 00:44:34.393688 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9699 00:44:34.397096 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9700 00:44:34.403482 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9701 00:44:34.406832 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9702 00:44:34.413872 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9703 00:44:34.416806 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9704 00:44:34.420359 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9705 00:44:34.426558 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9706 00:44:34.430212 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9707 00:44:34.436566 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9708 00:44:34.440164 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9709 00:44:34.443596 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9710 00:44:34.449727 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9711 00:44:34.453037 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9712 00:44:34.459818 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9713 00:44:34.463127 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9714 00:44:34.466674 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9715 00:44:34.473000 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9716 00:44:34.476181 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9717 00:44:34.482942 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9718 00:44:34.485847 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9719 00:44:34.489391 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9720 00:44:34.495940 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9721 00:44:34.499455 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9722 00:44:34.505707 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9723 00:44:34.508927 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9724 00:44:34.512312 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9725 00:44:34.518861 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9726 00:44:34.522403 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9727 00:44:34.528957 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9728 00:44:34.532264 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9729 00:44:34.535694 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9730 00:44:34.542373 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9731 00:44:34.545544 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9732 00:44:34.552341 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9733 00:44:34.555103 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9734 00:44:34.558710 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9735 00:44:34.565504 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9736 00:44:34.568402 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9737 00:44:34.575005 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9738 00:44:34.578284 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9739 00:44:34.581609 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9740 00:44:34.588466 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9741 00:44:34.591392 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9742 00:44:34.597932 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9743 00:44:34.601394 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9744 00:44:34.604921 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9745 00:44:34.611502 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9746 00:44:34.615114 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9747 00:44:34.621221 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9748 00:44:34.624641 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9749 00:44:34.627891 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9750 00:44:34.634843 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9751 00:44:34.638181 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9752 00:44:34.641565 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9753 00:44:34.648051 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9754 00:44:34.651152 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9755 00:44:34.657879 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9756 00:44:34.661329 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9757 00:44:34.667765 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9758 00:44:34.671258 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9759 00:44:34.674754 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9760 00:44:34.681039 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9761 00:44:34.684530 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9762 00:44:34.691300 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9763 00:44:34.694654 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9764 00:44:34.700913 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9765 00:44:34.704242 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9766 00:44:34.707307 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9767 00:44:34.714469 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9768 00:44:34.717164 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9769 00:44:34.724335 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9770 00:44:34.727237 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9771 00:44:34.734130 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9772 00:44:34.737604 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9773 00:44:34.740502 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9774 00:44:34.747450 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9775 00:44:34.751027 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9776 00:44:34.757296 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9777 00:44:34.760358 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9778 00:44:34.763648 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9779 00:44:34.770219 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9780 00:44:34.773800 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9781 00:44:34.780313 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9782 00:44:34.783850 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9783 00:44:34.790512 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9784 00:44:34.793761 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9785 00:44:34.796824 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9786 00:44:34.803365 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9787 00:44:34.806826 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9788 00:44:34.813230 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9789 00:44:34.817021 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9790 00:44:34.820160 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9791 00:44:34.826593 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9792 00:44:34.830396 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9793 00:44:34.836651 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9794 00:44:34.840017 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9795 00:44:34.846572 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9796 00:44:34.849871 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9797 00:44:34.852979 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9798 00:44:34.856458 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9799 00:44:34.859814 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9800 00:44:34.866850 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9801 00:44:34.869853 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9802 00:44:34.873346 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9803 00:44:34.880099 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9804 00:44:34.882925 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9805 00:44:34.886175 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9806 00:44:34.893083 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9807 00:44:34.896154 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9808 00:44:34.902811 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9809 00:44:34.906065 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9810 00:44:34.909654 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9811 00:44:34.916404 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9812 00:44:34.919345 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9813 00:44:34.926104 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9814 00:44:34.929195 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9815 00:44:34.932882 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9816 00:44:34.939291 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9817 00:44:34.942639 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9818 00:44:34.946078 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9819 00:44:34.952545 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9820 00:44:34.956262 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9821 00:44:34.959151 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9822 00:44:34.966066 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9823 00:44:34.969096 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9824 00:44:34.975567 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9825 00:44:34.979158 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9826 00:44:34.982333 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9827 00:44:34.989239 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9828 00:44:34.992162 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9829 00:44:34.998695 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9830 00:44:35.002084 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9831 00:44:35.005392 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9832 00:44:35.011984 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9833 00:44:35.015493 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9834 00:44:35.018357 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9835 00:44:35.025021 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9836 00:44:35.028428 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9837 00:44:35.031753 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9838 00:44:35.035227 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9839 00:44:35.041535 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9840 00:44:35.045311 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9841 00:44:35.048275 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9842 00:44:35.051708 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9843 00:44:35.055048 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9844 00:44:35.061617 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9845 00:44:35.065164 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9846 00:44:35.068117 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9847 00:44:35.075232 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9848 00:44:35.078337 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9849 00:44:35.081808 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9850 00:44:35.088402 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9851 00:44:35.091635 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9852 00:44:35.097814 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9853 00:44:35.101485 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9854 00:44:35.104871 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9855 00:44:35.111509 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9856 00:44:35.114456 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9857 00:44:35.121387 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9858 00:44:35.124798 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9859 00:44:35.131482 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9860 00:44:35.134510 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9861 00:44:35.137571 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9862 00:44:35.144283 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9863 00:44:35.147881 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9864 00:44:35.154499 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9865 00:44:35.157656 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9866 00:44:35.160744 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9867 00:44:35.167230 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9868 00:44:35.170413 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9869 00:44:35.177656 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9870 00:44:35.180834 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9871 00:44:35.187327 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9872 00:44:35.190660 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9873 00:44:35.194088 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9874 00:44:35.200592 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9875 00:44:35.203505 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9876 00:44:35.210535 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9877 00:44:35.213887 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9878 00:44:35.217211 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9879 00:44:35.223876 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9880 00:44:35.226889 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9881 00:44:35.233938 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9882 00:44:35.236737 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9883 00:44:35.240207 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9884 00:44:35.246583 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9885 00:44:35.249985 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9886 00:44:35.256795 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9887 00:44:35.260417 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9888 00:44:35.263296 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9889 00:44:35.269798 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9890 00:44:35.273509 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9891 00:44:35.279887 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9892 00:44:35.283208 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9893 00:44:35.289678 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9894 00:44:35.293362 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9895 00:44:35.296169 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9896 00:44:35.302876 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9897 00:44:35.306486 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9898 00:44:35.312937 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9899 00:44:35.316388 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9900 00:44:35.320009 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9901 00:44:35.326358 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9902 00:44:35.329794 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9903 00:44:35.336475 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9904 00:44:35.339760 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9905 00:44:35.343132 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9906 00:44:35.349551 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9907 00:44:35.353097 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9908 00:44:35.359374 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9909 00:44:35.362926 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9910 00:44:35.369523 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9911 00:44:35.372351 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9912 00:44:35.375821 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9913 00:44:35.382559 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9914 00:44:35.386018 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9915 00:44:35.392558 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9916 00:44:35.395765 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9917 00:44:35.402201 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9918 00:44:35.405662 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9919 00:44:35.408999 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9920 00:44:35.415288 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9921 00:44:35.418607 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9922 00:44:35.425652 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9923 00:44:35.428341 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9924 00:44:35.434980 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9925 00:44:35.438444 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9926 00:44:35.441862 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9927 00:44:35.448934 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9928 00:44:35.452086 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9929 00:44:35.458622 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9930 00:44:35.462037 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9931 00:44:35.468305 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9932 00:44:35.471946 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9933 00:44:35.474844 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9934 00:44:35.481800 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9935 00:44:35.484673 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9936 00:44:35.491540 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9937 00:44:35.495108 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9938 00:44:35.501550 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9939 00:44:35.504591 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9940 00:44:35.511351 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9941 00:44:35.514645 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9942 00:44:35.517773 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9943 00:44:35.524731 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9944 00:44:35.527734 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9945 00:44:35.534745 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9946 00:44:35.537506 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9947 00:44:35.544597 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9948 00:44:35.547499 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9949 00:44:35.554460 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9950 00:44:35.557408 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9951 00:44:35.560832 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9952 00:44:35.567137 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9953 00:44:35.570556 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9954 00:44:35.577505 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9955 00:44:35.580848 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9956 00:44:35.587330 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9957 00:44:35.590684 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9958 00:44:35.597116 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9959 00:44:35.600562 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9960 00:44:35.603979 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9961 00:44:35.610618 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9962 00:44:35.613952 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9963 00:44:35.620119 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9964 00:44:35.623429 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9965 00:44:35.629986 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9966 00:44:35.633120 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9967 00:44:35.640302 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9968 00:44:35.643076 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9969 00:44:35.646538 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9970 00:44:35.652963 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9971 00:44:35.656434 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9972 00:44:35.663113 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9973 00:44:35.666577 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9974 00:44:35.672767 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9975 00:44:35.676280 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9976 00:44:35.682678 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9977 00:44:35.686259 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9978 00:44:35.692564 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9979 00:44:35.696293 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9980 00:44:35.699267 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9981 00:44:35.706020 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9982 00:44:35.709486 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9983 00:44:35.715684 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9984 00:44:35.719144 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9985 00:44:35.725739 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9986 00:44:35.729556 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9987 00:44:35.735990 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9988 00:44:35.739038 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9989 00:44:35.745398 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9990 00:44:35.749046 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9991 00:44:35.755810 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9992 00:44:35.758971 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9993 00:44:35.765728 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9994 00:44:35.769256 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9995 00:44:35.776152 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9996 00:44:35.782460 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9997 00:44:35.785456 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9998 00:44:35.788854 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9999 00:44:35.795974 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
10000 00:44:35.802400 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
10001 00:44:35.805322 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
10002 00:44:35.805797 INFO: [APUAPC] vio 0
10003 00:44:35.812260 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
10004 00:44:35.815693 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
10005 00:44:35.819053 INFO: [APUAPC] D0_APC_0: 0x400510
10006 00:44:35.822508 INFO: [APUAPC] D0_APC_1: 0x0
10007 00:44:35.825540 INFO: [APUAPC] D0_APC_2: 0x1540
10008 00:44:35.828810 INFO: [APUAPC] D0_APC_3: 0x0
10009 00:44:35.832122 INFO: [APUAPC] D1_APC_0: 0xffffffff
10010 00:44:35.835704 INFO: [APUAPC] D1_APC_1: 0xffffffff
10011 00:44:35.838739 INFO: [APUAPC] D1_APC_2: 0x3fffff
10012 00:44:35.842421 INFO: [APUAPC] D1_APC_3: 0x0
10013 00:44:35.845874 INFO: [APUAPC] D2_APC_0: 0xffffffff
10014 00:44:35.848872 INFO: [APUAPC] D2_APC_1: 0xffffffff
10015 00:44:35.852224 INFO: [APUAPC] D2_APC_2: 0x3fffff
10016 00:44:35.855587 INFO: [APUAPC] D2_APC_3: 0x0
10017 00:44:35.858698 INFO: [APUAPC] D3_APC_0: 0xffffffff
10018 00:44:35.862036 INFO: [APUAPC] D3_APC_1: 0xffffffff
10019 00:44:35.865597 INFO: [APUAPC] D3_APC_2: 0x3fffff
10020 00:44:35.868676 INFO: [APUAPC] D3_APC_3: 0x0
10021 00:44:35.872215 INFO: [APUAPC] D4_APC_0: 0xffffffff
10022 00:44:35.875031 INFO: [APUAPC] D4_APC_1: 0xffffffff
10023 00:44:35.878486 INFO: [APUAPC] D4_APC_2: 0x3fffff
10024 00:44:35.881896 INFO: [APUAPC] D4_APC_3: 0x0
10025 00:44:35.885446 INFO: [APUAPC] D5_APC_0: 0xffffffff
10026 00:44:35.888323 INFO: [APUAPC] D5_APC_1: 0xffffffff
10027 00:44:35.891881 INFO: [APUAPC] D5_APC_2: 0x3fffff
10028 00:44:35.891962 INFO: [APUAPC] D5_APC_3: 0x0
10029 00:44:35.895326 INFO: [APUAPC] D6_APC_0: 0xffffffff
10030 00:44:35.901709 INFO: [APUAPC] D6_APC_1: 0xffffffff
10031 00:44:35.905340 INFO: [APUAPC] D6_APC_2: 0x3fffff
10032 00:44:35.905435 INFO: [APUAPC] D6_APC_3: 0x0
10033 00:44:35.908172 INFO: [APUAPC] D7_APC_0: 0xffffffff
10034 00:44:35.911464 INFO: [APUAPC] D7_APC_1: 0xffffffff
10035 00:44:35.914876 INFO: [APUAPC] D7_APC_2: 0x3fffff
10036 00:44:35.918270 INFO: [APUAPC] D7_APC_3: 0x0
10037 00:44:35.921734 INFO: [APUAPC] D8_APC_0: 0xffffffff
10038 00:44:35.924974 INFO: [APUAPC] D8_APC_1: 0xffffffff
10039 00:44:35.928458 INFO: [APUAPC] D8_APC_2: 0x3fffff
10040 00:44:35.931467 INFO: [APUAPC] D8_APC_3: 0x0
10041 00:44:35.934924 INFO: [APUAPC] D9_APC_0: 0xffffffff
10042 00:44:35.938306 INFO: [APUAPC] D9_APC_1: 0xffffffff
10043 00:44:35.941561 INFO: [APUAPC] D9_APC_2: 0x3fffff
10044 00:44:35.944612 INFO: [APUAPC] D9_APC_3: 0x0
10045 00:44:35.947780 INFO: [APUAPC] D10_APC_0: 0xffffffff
10046 00:44:35.951084 INFO: [APUAPC] D10_APC_1: 0xffffffff
10047 00:44:35.954934 INFO: [APUAPC] D10_APC_2: 0x3fffff
10048 00:44:35.958353 INFO: [APUAPC] D10_APC_3: 0x0
10049 00:44:35.961267 INFO: [APUAPC] D11_APC_0: 0xffffffff
10050 00:44:35.964391 INFO: [APUAPC] D11_APC_1: 0xffffffff
10051 00:44:35.968035 INFO: [APUAPC] D11_APC_2: 0x3fffff
10052 00:44:35.971385 INFO: [APUAPC] D11_APC_3: 0x0
10053 00:44:35.974539 INFO: [APUAPC] D12_APC_0: 0xffffffff
10054 00:44:35.977510 INFO: [APUAPC] D12_APC_1: 0xffffffff
10055 00:44:35.981174 INFO: [APUAPC] D12_APC_2: 0x3fffff
10056 00:44:35.984597 INFO: [APUAPC] D12_APC_3: 0x0
10057 00:44:35.987862 INFO: [APUAPC] D13_APC_0: 0xffffffff
10058 00:44:35.990823 INFO: [APUAPC] D13_APC_1: 0xffffffff
10059 00:44:35.994213 INFO: [APUAPC] D13_APC_2: 0x3fffff
10060 00:44:35.997883 INFO: [APUAPC] D13_APC_3: 0x0
10061 00:44:36.000803 INFO: [APUAPC] D14_APC_0: 0xffffffff
10062 00:44:36.004280 INFO: [APUAPC] D14_APC_1: 0xffffffff
10063 00:44:36.007447 INFO: [APUAPC] D14_APC_2: 0x3fffff
10064 00:44:36.010927 INFO: [APUAPC] D14_APC_3: 0x0
10065 00:44:36.014356 INFO: [APUAPC] D15_APC_0: 0xffffffff
10066 00:44:36.017852 INFO: [APUAPC] D15_APC_1: 0xffffffff
10067 00:44:36.021258 INFO: [APUAPC] D15_APC_2: 0x3fffff
10068 00:44:36.024304 INFO: [APUAPC] D15_APC_3: 0x0
10069 00:44:36.027836 INFO: [APUAPC] APC_CON: 0x4
10070 00:44:36.031342 INFO: [NOCDAPC] D0_APC_0: 0x0
10071 00:44:36.034247 INFO: [NOCDAPC] D0_APC_1: 0x0
10072 00:44:36.037950 INFO: [NOCDAPC] D1_APC_0: 0x0
10073 00:44:36.041410 INFO: [NOCDAPC] D1_APC_1: 0xfff
10074 00:44:36.044772 INFO: [NOCDAPC] D2_APC_0: 0x0
10075 00:44:36.047848 INFO: [NOCDAPC] D2_APC_1: 0xfff
10076 00:44:36.051093 INFO: [NOCDAPC] D3_APC_0: 0x0
10077 00:44:36.051481 INFO: [NOCDAPC] D3_APC_1: 0xfff
10078 00:44:36.054120 INFO: [NOCDAPC] D4_APC_0: 0x0
10079 00:44:36.057897 INFO: [NOCDAPC] D4_APC_1: 0xfff
10080 00:44:36.061078 INFO: [NOCDAPC] D5_APC_0: 0x0
10081 00:44:36.064142 INFO: [NOCDAPC] D5_APC_1: 0xfff
10082 00:44:36.067918 INFO: [NOCDAPC] D6_APC_0: 0x0
10083 00:44:36.070928 INFO: [NOCDAPC] D6_APC_1: 0xfff
10084 00:44:36.074409 INFO: [NOCDAPC] D7_APC_0: 0x0
10085 00:44:36.077431 INFO: [NOCDAPC] D7_APC_1: 0xfff
10086 00:44:36.081165 INFO: [NOCDAPC] D8_APC_0: 0x0
10087 00:44:36.084439 INFO: [NOCDAPC] D8_APC_1: 0xfff
10088 00:44:36.085079 INFO: [NOCDAPC] D9_APC_0: 0x0
10089 00:44:36.087241 INFO: [NOCDAPC] D9_APC_1: 0xfff
10090 00:44:36.091081 INFO: [NOCDAPC] D10_APC_0: 0x0
10091 00:44:36.094230 INFO: [NOCDAPC] D10_APC_1: 0xfff
10092 00:44:36.097361 INFO: [NOCDAPC] D11_APC_0: 0x0
10093 00:44:36.101149 INFO: [NOCDAPC] D11_APC_1: 0xfff
10094 00:44:36.104214 INFO: [NOCDAPC] D12_APC_0: 0x0
10095 00:44:36.107210 INFO: [NOCDAPC] D12_APC_1: 0xfff
10096 00:44:36.110705 INFO: [NOCDAPC] D13_APC_0: 0x0
10097 00:44:36.113614 INFO: [NOCDAPC] D13_APC_1: 0xfff
10098 00:44:36.117109 INFO: [NOCDAPC] D14_APC_0: 0x0
10099 00:44:36.120424 INFO: [NOCDAPC] D14_APC_1: 0xfff
10100 00:44:36.123895 INFO: [NOCDAPC] D15_APC_0: 0x0
10101 00:44:36.127009 INFO: [NOCDAPC] D15_APC_1: 0xfff
10102 00:44:36.127477 INFO: [NOCDAPC] APC_CON: 0x4
10103 00:44:36.130320 INFO: [APUAPC] set_apusys_apc done
10104 00:44:36.133785 INFO: [DEVAPC] devapc_init done
10105 00:44:36.140097 INFO: GICv3 without legacy support detected.
10106 00:44:36.143436 INFO: ARM GICv3 driver initialized in EL3
10107 00:44:36.146852 INFO: Maximum SPI INTID supported: 639
10108 00:44:36.149854 INFO: BL31: Initializing runtime services
10109 00:44:36.156885 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10110 00:44:36.160204 INFO: SPM: enable CPC mode
10111 00:44:36.163191 INFO: mcdi ready for mcusys-off-idle and system suspend
10112 00:44:36.170410 INFO: BL31: Preparing for EL3 exit to normal world
10113 00:44:36.173506 INFO: Entry point address = 0x80000000
10114 00:44:36.173608 INFO: SPSR = 0x8
10115 00:44:36.180467
10116 00:44:36.180582
10117 00:44:36.180684
10118 00:44:36.184123 Starting depthcharge on Spherion...
10119 00:44:36.184244
10120 00:44:36.184348 Wipe memory regions:
10121 00:44:36.184448
10122 00:44:36.185215 end: 2.2.3 depthcharge-start (duration 00:00:19) [common]
10123 00:44:36.185334 start: 2.2.4 bootloader-commands (timeout 00:04:27) [common]
10124 00:44:36.185429 Setting prompt string to ['asurada:']
10125 00:44:36.185517 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:27)
10126 00:44:36.187590 [0x00000040000000, 0x00000054600000)
10127 00:44:36.309263
10128 00:44:36.309390 [0x00000054660000, 0x00000080000000)
10129 00:44:36.569860
10130 00:44:36.569971 [0x000000821a7280, 0x000000ffe64000)
10131 00:44:37.315351
10132 00:44:37.315807 [0x00000100000000, 0x00000240000000)
10133 00:44:39.205287
10134 00:44:39.208277 Initializing XHCI USB controller at 0x11200000.
10135 00:44:40.246849
10136 00:44:40.249764 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10137 00:44:40.250155
10138 00:44:40.250454
10139 00:44:40.251173 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10141 00:44:40.352383 asurada: tftpboot 192.168.201.1 14368401/tftp-deploy-ngfchemh/kernel/image.itb 14368401/tftp-deploy-ngfchemh/kernel/cmdline
10142 00:44:40.353098 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10143 00:44:40.353585 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:23)
10144 00:44:40.357803 tftpboot 192.168.201.1 14368401/tftp-deploy-ngfchemh/kernel/image.itp-deploy-ngfchemh/kernel/cmdline
10145 00:44:40.358313
10146 00:44:40.358644 Waiting for link
10147 00:44:40.516403
10148 00:44:40.516976 R8152: Initializing
10149 00:44:40.517316
10150 00:44:40.519339 Version 6 (ocp_data = 5c30)
10151 00:44:40.519760
10152 00:44:40.522358 R8152: Done initializing
10153 00:44:40.522780
10154 00:44:40.523108 Adding net device
10155 00:44:42.426734
10156 00:44:42.427263 done.
10157 00:44:42.427602
10158 00:44:42.427910 MAC: 00:24:32:30:78:ff
10159 00:44:42.428209
10160 00:44:42.429282 Sending DHCP discover... done.
10161 00:44:42.429706
10162 00:44:42.433275 Waiting for reply... done.
10163 00:44:42.433774
10164 00:44:42.438129 Sending DHCP request... done.
10165 00:44:42.438555
10166 00:44:42.464528 Waiting for reply... done.
10167 00:44:42.465140
10168 00:44:42.465481 My ip is 192.168.201.21
10169 00:44:42.465791
10170 00:44:42.467451 The DHCP server ip is 192.168.201.1
10171 00:44:42.467962
10172 00:44:42.474299 TFTP server IP predefined by user: 192.168.201.1
10173 00:44:42.474729
10174 00:44:42.481055 Bootfile predefined by user: 14368401/tftp-deploy-ngfchemh/kernel/image.itb
10175 00:44:42.481562
10176 00:44:42.481896 Sending tftp read request... done.
10177 00:44:42.483627
10178 00:44:42.491081 Waiting for the transfer...
10179 00:44:42.491587
10180 00:44:43.181131 00000000 ################################################################
10181 00:44:43.181595
10182 00:44:43.861886 00080000 ################################################################
10183 00:44:43.862341
10184 00:44:44.533738 00100000 ################################################################
10185 00:44:44.534203
10186 00:44:45.223216 00180000 ################################################################
10187 00:44:45.223711
10188 00:44:45.912956 00200000 ################################################################
10189 00:44:45.913415
10190 00:44:46.579227 00280000 ################################################################
10191 00:44:46.579686
10192 00:44:47.264968 00300000 ################################################################
10193 00:44:47.265472
10194 00:44:47.921148 00380000 ################################################################
10195 00:44:47.921614
10196 00:44:48.583719 00400000 ################################################################
10197 00:44:48.584180
10198 00:44:49.243548 00480000 ################################################################
10199 00:44:49.243685
10200 00:44:49.839146 00500000 ################################################################
10201 00:44:49.839731
10202 00:44:50.505946 00580000 ################################################################
10203 00:44:50.506409
10204 00:44:51.185757 00600000 ################################################################
10205 00:44:51.186236
10206 00:44:51.871319 00680000 ################################################################
10207 00:44:51.871771
10208 00:44:52.558640 00700000 ################################################################
10209 00:44:52.559112
10210 00:44:53.259097 00780000 ################################################################
10211 00:44:53.259560
10212 00:44:53.953338 00800000 ################################################################
10213 00:44:53.953872
10214 00:44:54.642968 00880000 ################################################################
10215 00:44:54.643525
10216 00:44:55.336572 00900000 ################################################################
10217 00:44:55.337166
10218 00:44:56.022220 00980000 ################################################################
10219 00:44:56.022698
10220 00:44:56.716744 00a00000 ################################################################
10221 00:44:56.717286
10222 00:44:57.407000 00a80000 ################################################################
10223 00:44:57.407470
10224 00:44:58.080551 00b00000 ################################################################
10225 00:44:58.081270
10226 00:44:58.776350 00b80000 ################################################################
10227 00:44:58.777042
10228 00:44:59.472047 00c00000 ################################################################
10229 00:44:59.472567
10230 00:45:00.149792 00c80000 ################################################################
10231 00:45:00.150261
10232 00:45:00.806308 00d00000 ################################################################
10233 00:45:00.806770
10234 00:45:01.480430 00d80000 ################################################################
10235 00:45:01.480968
10236 00:45:02.129304 00e00000 ################################################################
10237 00:45:02.129865
10238 00:45:02.805933 00e80000 ################################################################
10239 00:45:02.806438
10240 00:45:03.493639 00f00000 ################################################################
10241 00:45:03.494146
10242 00:45:04.155863 00f80000 ################################################################
10243 00:45:04.155991
10244 00:45:04.776313 01000000 ################################################################
10245 00:45:04.776852
10246 00:45:05.472102 01080000 ################################################################
10247 00:45:05.472604
10248 00:45:06.062199 01100000 ################################################################
10249 00:45:06.062329
10250 00:45:06.609319 01180000 ################################################################
10251 00:45:06.609447
10252 00:45:07.133545 01200000 ################################################################
10253 00:45:07.133675
10254 00:45:07.674713 01280000 ################################################################
10255 00:45:07.674843
10256 00:45:08.238920 01300000 ################################################################
10257 00:45:08.239033
10258 00:45:08.787065 01380000 ################################################################
10259 00:45:08.787220
10260 00:45:09.324799 01400000 ################################################################
10261 00:45:09.324962
10262 00:45:09.882189 01480000 ################################################################
10263 00:45:09.882315
10264 00:45:10.455186 01500000 ################################################################
10265 00:45:10.455335
10266 00:45:11.001614 01580000 ################################################################
10267 00:45:11.001735
10268 00:45:11.568316 01600000 ################################################################
10269 00:45:11.568444
10270 00:45:12.122377 01680000 ################################################################
10271 00:45:12.122507
10272 00:45:12.692216 01700000 ################################################################
10273 00:45:12.692340
10274 00:45:13.266778 01780000 ################################################################
10275 00:45:13.266906
10276 00:45:13.843352 01800000 ################################################################
10277 00:45:13.843490
10278 00:45:14.414865 01880000 ################################################################
10279 00:45:14.415018
10280 00:45:14.964134 01900000 ################################################################
10281 00:45:14.964299
10282 00:45:15.591435 01980000 ################################################################
10283 00:45:15.591552
10284 00:45:16.128321 01a00000 ################################################################
10285 00:45:16.128451
10286 00:45:16.658283 01a80000 ################################################################
10287 00:45:16.658428
10288 00:45:17.211912 01b00000 ################################################################
10289 00:45:17.212026
10290 00:45:17.765321 01b80000 ################################################################
10291 00:45:17.765447
10292 00:45:18.332760 01c00000 ################################################################
10293 00:45:18.332882
10294 00:45:18.908325 01c80000 ################################################################
10295 00:45:18.908457
10296 00:45:19.455247 01d00000 ################################################################
10297 00:45:19.455373
10298 00:45:20.015559 01d80000 ################################################################
10299 00:45:20.015682
10300 00:45:20.494712 01e00000 ######################################################## done.
10301 00:45:20.494833
10302 00:45:20.498058 The bootfile was 31910002 bytes long.
10303 00:45:20.498135
10304 00:45:20.501436 Sending tftp read request... done.
10305 00:45:20.501513
10306 00:45:20.504335 Waiting for the transfer...
10307 00:45:20.504412
10308 00:45:20.507700 00000000 # done.
10309 00:45:20.507778
10310 00:45:20.514823 Command line loaded dynamically from TFTP file: 14368401/tftp-deploy-ngfchemh/kernel/cmdline
10311 00:45:20.514900
10312 00:45:20.537895 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14368401/extract-nfsrootfs-dn_hmfv5,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10313 00:45:20.537984
10314 00:45:20.538043 Loading FIT.
10315 00:45:20.538098
10316 00:45:20.541139 Image ramdisk-1 has 18734341 bytes.
10317 00:45:20.541216
10318 00:45:20.544165 Image fdt-1 has 47258 bytes.
10319 00:45:20.544240
10320 00:45:20.547374 Image kernel-1 has 13126376 bytes.
10321 00:45:20.547450
10322 00:45:20.554037 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10323 00:45:20.554115
10324 00:45:20.574125 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10325 00:45:20.574203
10326 00:45:20.577589 Choosing best match conf-1 for compat google,spherion-rev2.
10327 00:45:20.582915
10328 00:45:20.587278 Connected to device vid:did:rid of 1ae0:0028:00
10329 00:45:20.594408
10330 00:45:20.597681 tpm_get_response: command 0x17b, return code 0x0
10331 00:45:20.597758
10332 00:45:20.600998 ec_init: CrosEC protocol v3 supported (256, 248)
10333 00:45:20.606194
10334 00:45:20.609686 tpm_cleanup: add release locality here.
10335 00:45:20.609763
10336 00:45:20.609822 Shutting down all USB controllers.
10337 00:45:20.612940
10338 00:45:20.613015 Removing current net device
10339 00:45:20.613074
10340 00:45:20.619456 Exiting depthcharge with code 4 at timestamp: 73818876
10341 00:45:20.619533
10342 00:45:20.623079 LZMA decompressing kernel-1 to 0x821a6718
10343 00:45:20.623155
10344 00:45:20.626217 LZMA decompressing kernel-1 to 0x40000000
10345 00:45:22.242690
10346 00:45:22.242819 jumping to kernel
10347 00:45:22.243259 end: 2.2.4 bootloader-commands (duration 00:00:46) [common]
10348 00:45:22.243348 start: 2.2.5 auto-login-action (timeout 00:03:41) [common]
10349 00:45:22.243415 Setting prompt string to ['Linux version [0-9]']
10350 00:45:22.243476 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10351 00:45:22.243538 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10352 00:45:22.324873
10353 00:45:22.327777 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10354 00:45:22.331268 start: 2.2.5.1 login-action (timeout 00:03:41) [common]
10355 00:45:22.331360 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10356 00:45:22.331425 Setting prompt string to []
10357 00:45:22.331498 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10358 00:45:22.331561 Using line separator: #'\n'#
10359 00:45:22.331614 No login prompt set.
10360 00:45:22.331670 Parsing kernel messages
10361 00:45:22.331720 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10362 00:45:22.331815 [login-action] Waiting for messages, (timeout 00:03:41)
10363 00:45:22.331896 Waiting using forced prompt support (timeout 00:01:50)
10364 00:45:22.350632 [ 0.000000] Linux version 6.1.92-cip22 (KernelCI@build-j232175-arm64-gcc-10-defconfig-arm64-chromebook-7lg8d) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sun Jun 16 00:28:47 UTC 2024
10365 00:45:22.354043 [ 0.000000] random: crng init done
10366 00:45:22.360961 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10367 00:45:22.364219 [ 0.000000] efi: UEFI not found.
10368 00:45:22.370379 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10369 00:45:22.380377 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10370 00:45:22.390322 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10371 00:45:22.396913 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10372 00:45:22.403759 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10373 00:45:22.410720 [ 0.000000] printk: bootconsole [mtk8250] enabled
10374 00:45:22.417255 [ 0.000000] NUMA: No NUMA configuration found
10375 00:45:22.423418 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10376 00:45:22.430249 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10377 00:45:22.430326 [ 0.000000] Zone ranges:
10378 00:45:22.437119 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10379 00:45:22.440484 [ 0.000000] DMA32 empty
10380 00:45:22.447062 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10381 00:45:22.450316 [ 0.000000] Movable zone start for each node
10382 00:45:22.453354 [ 0.000000] Early memory node ranges
10383 00:45:22.460000 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10384 00:45:22.466713 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10385 00:45:22.473250 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10386 00:45:22.480107 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10387 00:45:22.486316 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10388 00:45:22.493072 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10389 00:45:22.549080 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10390 00:45:22.555915 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10391 00:45:22.562274 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10392 00:45:22.565669 [ 0.000000] psci: probing for conduit method from DT.
10393 00:45:22.572721 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10394 00:45:22.575710 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10395 00:45:22.582417 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10396 00:45:22.585768 [ 0.000000] psci: SMC Calling Convention v1.2
10397 00:45:22.592266 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10398 00:45:22.596050 [ 0.000000] Detected VIPT I-cache on CPU0
10399 00:45:22.602554 [ 0.000000] CPU features: detected: GIC system register CPU interface
10400 00:45:22.609133 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10401 00:45:22.615861 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10402 00:45:22.622653 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10403 00:45:22.628948 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10404 00:45:22.639013 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10405 00:45:22.641927 [ 0.000000] alternatives: applying boot alternatives
10406 00:45:22.648852 [ 0.000000] Fallback order for Node 0: 0
10407 00:45:22.655140 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10408 00:45:22.658570 [ 0.000000] Policy zone: Normal
10409 00:45:22.682026 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14368401/extract-nfsrootfs-dn_hmfv5,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10410 00:45:22.691778 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10411 00:45:22.701742 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10412 00:45:22.711572 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10413 00:45:22.718156 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10414 00:45:22.721422 <6>[ 0.000000] software IO TLB: area num 8.
10415 00:45:22.777524 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10416 00:45:22.927157 <6>[ 0.000000] Memory: 7945760K/8385536K available (18112K kernel code, 4120K rwdata, 22644K rodata, 8512K init, 616K bss, 407008K reserved, 32768K cma-reserved)
10417 00:45:22.933675 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10418 00:45:22.940295 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10419 00:45:22.943657 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10420 00:45:22.950426 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10421 00:45:22.956638 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10422 00:45:22.959910 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10423 00:45:22.969949 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10424 00:45:22.976607 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10425 00:45:22.983221 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10426 00:45:22.990072 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10427 00:45:22.993508 <6>[ 0.000000] GICv3: 608 SPIs implemented
10428 00:45:22.996497 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10429 00:45:23.002892 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10430 00:45:23.006522 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10431 00:45:23.012894 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10432 00:45:23.026166 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10433 00:45:23.039265 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10434 00:45:23.046195 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10435 00:45:23.054046 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10436 00:45:23.066929 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10437 00:45:23.073718 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10438 00:45:23.080288 <6>[ 0.009180] Console: colour dummy device 80x25
10439 00:45:23.090222 <6>[ 0.013908] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10440 00:45:23.096606 <6>[ 0.024349] pid_max: default: 32768 minimum: 301
10441 00:45:23.099823 <6>[ 0.029221] LSM: Security Framework initializing
10442 00:45:23.106965 <6>[ 0.034159] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10443 00:45:23.117511 <6>[ 0.041974] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10444 00:45:23.126856 <6>[ 0.051402] cblist_init_generic: Setting adjustable number of callback queues.
10445 00:45:23.129952 <6>[ 0.058891] cblist_init_generic: Setting shift to 3 and lim to 1.
10446 00:45:23.139616 <6>[ 0.065230] cblist_init_generic: Setting adjustable number of callback queues.
10447 00:45:23.146401 <6>[ 0.072657] cblist_init_generic: Setting shift to 3 and lim to 1.
10448 00:45:23.150094 <6>[ 0.079047] rcu: Hierarchical SRCU implementation.
10449 00:45:23.156636 <6>[ 0.084062] rcu: Max phase no-delay instances is 1000.
10450 00:45:23.162807 <6>[ 0.091130] EFI services will not be available.
10451 00:45:23.166212 <6>[ 0.096060] smp: Bringing up secondary CPUs ...
10452 00:45:23.174706 <6>[ 0.101105] Detected VIPT I-cache on CPU1
10453 00:45:23.181411 <6>[ 0.101177] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10454 00:45:23.187633 <6>[ 0.101207] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10455 00:45:23.191083 <6>[ 0.101548] Detected VIPT I-cache on CPU2
10456 00:45:23.200651 <6>[ 0.101602] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10457 00:45:23.207382 <6>[ 0.101619] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10458 00:45:23.210683 <6>[ 0.101880] Detected VIPT I-cache on CPU3
10459 00:45:23.217310 <6>[ 0.101927] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10460 00:45:23.224361 <6>[ 0.101941] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10461 00:45:23.227557 <6>[ 0.102242] CPU features: detected: Spectre-v4
10462 00:45:23.234172 <6>[ 0.102247] CPU features: detected: Spectre-BHB
10463 00:45:23.237299 <6>[ 0.102252] Detected PIPT I-cache on CPU4
10464 00:45:23.244237 <6>[ 0.102310] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10465 00:45:23.250715 <6>[ 0.102327] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10466 00:45:23.257391 <6>[ 0.102619] Detected PIPT I-cache on CPU5
10467 00:45:23.263891 <6>[ 0.102683] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10468 00:45:23.270559 <6>[ 0.102699] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10469 00:45:23.273887 <6>[ 0.102980] Detected PIPT I-cache on CPU6
10470 00:45:23.280157 <6>[ 0.103045] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10471 00:45:23.286811 <6>[ 0.103061] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10472 00:45:23.293356 <6>[ 0.103358] Detected PIPT I-cache on CPU7
10473 00:45:23.300141 <6>[ 0.103423] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10474 00:45:23.306682 <6>[ 0.103439] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10475 00:45:23.309968 <6>[ 0.103486] smp: Brought up 1 node, 8 CPUs
10476 00:45:23.316387 <6>[ 0.245036] SMP: Total of 8 processors activated.
10477 00:45:23.319829 <6>[ 0.249957] CPU features: detected: 32-bit EL0 Support
10478 00:45:23.329637 <6>[ 0.255353] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10479 00:45:23.336700 <6>[ 0.264153] CPU features: detected: Common not Private translations
10480 00:45:23.343153 <6>[ 0.270669] CPU features: detected: CRC32 instructions
10481 00:45:23.349513 <6>[ 0.276054] CPU features: detected: RCpc load-acquire (LDAPR)
10482 00:45:23.352993 <6>[ 0.282014] CPU features: detected: LSE atomic instructions
10483 00:45:23.359331 <6>[ 0.287795] CPU features: detected: Privileged Access Never
10484 00:45:23.366019 <6>[ 0.293611] CPU features: detected: RAS Extension Support
10485 00:45:23.372763 <6>[ 0.299219] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10486 00:45:23.376002 <6>[ 0.306441] CPU: All CPU(s) started at EL2
10487 00:45:23.382843 <6>[ 0.310758] alternatives: applying system-wide alternatives
10488 00:45:23.392380 <6>[ 0.321600] devtmpfs: initialized
10489 00:45:23.408095 <6>[ 0.330422] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10490 00:45:23.414434 <6>[ 0.340384] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10491 00:45:23.421590 <6>[ 0.348409] pinctrl core: initialized pinctrl subsystem
10492 00:45:23.424421 <6>[ 0.355092] DMI not present or invalid.
10493 00:45:23.431512 <6>[ 0.359504] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10494 00:45:23.440809 <6>[ 0.366363] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10495 00:45:23.447490 <6>[ 0.373950] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10496 00:45:23.457553 <6>[ 0.382173] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10497 00:45:23.460689 <6>[ 0.390417] audit: initializing netlink subsys (disabled)
10498 00:45:23.470582 <5>[ 0.396112] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10499 00:45:23.477333 <6>[ 0.396836] thermal_sys: Registered thermal governor 'step_wise'
10500 00:45:23.483782 <6>[ 0.404079] thermal_sys: Registered thermal governor 'power_allocator'
10501 00:45:23.486986 <6>[ 0.410333] cpuidle: using governor menu
10502 00:45:23.493581 <6>[ 0.421293] NET: Registered PF_QIPCRTR protocol family
10503 00:45:23.500263 <6>[ 0.426780] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10504 00:45:23.506878 <6>[ 0.433882] ASID allocator initialised with 32768 entries
10505 00:45:23.510460 <6>[ 0.440465] Serial: AMBA PL011 UART driver
10506 00:45:23.520472 <4>[ 0.449360] Trying to register duplicate clock ID: 134
10507 00:45:23.579099 <6>[ 0.511179] KASLR enabled
10508 00:45:23.593515 <6>[ 0.518907] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10509 00:45:23.599982 <6>[ 0.525922] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10510 00:45:23.606255 <6>[ 0.532409] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10511 00:45:23.612924 <6>[ 0.539412] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10512 00:45:23.619951 <6>[ 0.545900] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10513 00:45:23.626505 <6>[ 0.552901] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10514 00:45:23.632628 <6>[ 0.559388] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10515 00:45:23.639350 <6>[ 0.566393] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10516 00:45:23.642624 <6>[ 0.573907] ACPI: Interpreter disabled.
10517 00:45:23.651481 <6>[ 0.580343] iommu: Default domain type: Translated
10518 00:45:23.658032 <6>[ 0.585454] iommu: DMA domain TLB invalidation policy: strict mode
10519 00:45:23.661191 <5>[ 0.592118] SCSI subsystem initialized
10520 00:45:23.667777 <6>[ 0.596284] usbcore: registered new interface driver usbfs
10521 00:45:23.674404 <6>[ 0.602016] usbcore: registered new interface driver hub
10522 00:45:23.677726 <6>[ 0.607566] usbcore: registered new device driver usb
10523 00:45:23.685043 <6>[ 0.613670] pps_core: LinuxPPS API ver. 1 registered
10524 00:45:23.694835 <6>[ 0.618864] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10525 00:45:23.698233 <6>[ 0.628211] PTP clock support registered
10526 00:45:23.701449 <6>[ 0.632455] EDAC MC: Ver: 3.0.0
10527 00:45:23.708751 <6>[ 0.637605] FPGA manager framework
10528 00:45:23.715405 <6>[ 0.641291] Advanced Linux Sound Architecture Driver Initialized.
10529 00:45:23.718818 <6>[ 0.648064] vgaarb: loaded
10530 00:45:23.724913 <6>[ 0.651216] clocksource: Switched to clocksource arch_sys_counter
10531 00:45:23.728401 <5>[ 0.657658] VFS: Disk quotas dquot_6.6.0
10532 00:45:23.735521 <6>[ 0.661844] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10533 00:45:23.738344 <6>[ 0.669035] pnp: PnP ACPI: disabled
10534 00:45:23.747111 <6>[ 0.675832] NET: Registered PF_INET protocol family
10535 00:45:23.757123 <6>[ 0.681435] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10536 00:45:23.768337 <6>[ 0.693778] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10537 00:45:23.777778 <6>[ 0.702595] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10538 00:45:23.785065 <6>[ 0.710565] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10539 00:45:23.791669 <6>[ 0.719267] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10540 00:45:23.803119 <6>[ 0.729016] TCP: Hash tables configured (established 65536 bind 65536)
10541 00:45:23.809714 <6>[ 0.735887] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10542 00:45:23.816425 <6>[ 0.743085] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10543 00:45:23.823191 <6>[ 0.750793] NET: Registered PF_UNIX/PF_LOCAL protocol family
10544 00:45:23.829933 <6>[ 0.756870] RPC: Registered named UNIX socket transport module.
10545 00:45:23.833076 <6>[ 0.763018] RPC: Registered udp transport module.
10546 00:45:23.839923 <6>[ 0.767950] RPC: Registered tcp transport module.
10547 00:45:23.846679 <6>[ 0.772883] RPC: Registered tcp NFSv4.1 backchannel transport module.
10548 00:45:23.849891 <6>[ 0.779545] PCI: CLS 0 bytes, default 64
10549 00:45:23.852964 <6>[ 0.783874] Unpacking initramfs...
10550 00:45:23.869987 <6>[ 0.795745] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10551 00:45:23.880207 <6>[ 0.804399] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10552 00:45:23.883593 <6>[ 0.813270] kvm [1]: IPA Size Limit: 40 bits
10553 00:45:23.889684 <6>[ 0.817797] kvm [1]: GICv3: no GICV resource entry
10554 00:45:23.893221 <6>[ 0.822817] kvm [1]: disabling GICv2 emulation
10555 00:45:23.899749 <6>[ 0.827505] kvm [1]: GIC system register CPU interface enabled
10556 00:45:23.902972 <6>[ 0.833677] kvm [1]: vgic interrupt IRQ18
10557 00:45:23.909766 <6>[ 0.838028] kvm [1]: VHE mode initialized successfully
10558 00:45:23.916390 <5>[ 0.844449] Initialise system trusted keyrings
10559 00:45:23.922759 <6>[ 0.849238] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10560 00:45:23.930619 <6>[ 0.859245] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10561 00:45:23.937013 <5>[ 0.865674] NFS: Registering the id_resolver key type
10562 00:45:23.940304 <5>[ 0.870988] Key type id_resolver registered
10563 00:45:23.946717 <5>[ 0.875403] Key type id_legacy registered
10564 00:45:23.953623 <6>[ 0.879680] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10565 00:45:23.960210 <6>[ 0.886602] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10566 00:45:23.966809 <6>[ 0.894312] 9p: Installing v9fs 9p2000 file system support
10567 00:45:24.003320 <5>[ 0.932211] Key type asymmetric registered
10568 00:45:24.006407 <5>[ 0.936542] Asymmetric key parser 'x509' registered
10569 00:45:24.016840 <6>[ 0.941701] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10570 00:45:24.019532 <6>[ 0.949316] io scheduler mq-deadline registered
10571 00:45:24.022896 <6>[ 0.954077] io scheduler kyber registered
10572 00:45:24.042395 <6>[ 0.971178] EINJ: ACPI disabled.
10573 00:45:24.075251 <4>[ 0.997458] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10574 00:45:24.085208 <4>[ 1.008090] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10575 00:45:24.100047 <6>[ 1.028835] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10576 00:45:24.107692 <6>[ 1.036739] printk: console [ttyS0] disabled
10577 00:45:24.135805 <6>[ 1.061371] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10578 00:45:24.142478 <6>[ 1.070846] printk: console [ttyS0] enabled
10579 00:45:24.145595 <6>[ 1.070846] printk: console [ttyS0] enabled
10580 00:45:24.152309 <6>[ 1.079741] printk: bootconsole [mtk8250] disabled
10581 00:45:24.155763 <6>[ 1.079741] printk: bootconsole [mtk8250] disabled
10582 00:45:24.162241 <6>[ 1.090760] SuperH (H)SCI(F) driver initialized
10583 00:45:24.165261 <6>[ 1.096031] msm_serial: driver initialized
10584 00:45:24.179336 <6>[ 1.104946] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10585 00:45:24.189448 <6>[ 1.113493] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10586 00:45:24.195621 <6>[ 1.122036] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10587 00:45:24.205538 <6>[ 1.130665] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10588 00:45:24.215505 <6>[ 1.139372] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10589 00:45:24.222528 <6>[ 1.148086] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10590 00:45:24.232303 <6>[ 1.156627] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10591 00:45:24.238780 <6>[ 1.165437] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10592 00:45:24.248823 <6>[ 1.173979] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10593 00:45:24.260437 <6>[ 1.189554] loop: module loaded
10594 00:45:24.267215 <6>[ 1.195513] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10595 00:45:24.289252 <4>[ 1.218587] mtk-pmic-keys: Failed to locate of_node [id: -1]
10596 00:45:24.296588 <6>[ 1.225366] megasas: 07.719.03.00-rc1
10597 00:45:24.305735 <6>[ 1.235030] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10598 00:45:24.313633 <6>[ 1.242577] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10599 00:45:24.330159 <6>[ 1.259045] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10600 00:45:24.385482 <6>[ 1.307911] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10601 00:45:24.642641 <6>[ 1.571838] Freeing initrd memory: 18292K
10602 00:45:24.654125 <6>[ 1.583385] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10603 00:45:24.664938 <6>[ 1.594220] tun: Universal TUN/TAP device driver, 1.6
10604 00:45:24.668993 <6>[ 1.600286] thunder_xcv, ver 1.0
10605 00:45:24.671726 <6>[ 1.603790] thunder_bgx, ver 1.0
10606 00:45:24.675006 <6>[ 1.607285] nicpf, ver 1.0
10607 00:45:24.685240 <6>[ 1.611294] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10608 00:45:24.689125 <6>[ 1.618769] hns3: Copyright (c) 2017 Huawei Corporation.
10609 00:45:24.691947 <6>[ 1.624357] hclge is initializing
10610 00:45:24.698617 <6>[ 1.627937] e1000: Intel(R) PRO/1000 Network Driver
10611 00:45:24.705452 <6>[ 1.633067] e1000: Copyright (c) 1999-2006 Intel Corporation.
10612 00:45:24.708614 <6>[ 1.639079] e1000e: Intel(R) PRO/1000 Network Driver
10613 00:45:24.715210 <6>[ 1.644295] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10614 00:45:24.721898 <6>[ 1.650483] igb: Intel(R) Gigabit Ethernet Network Driver
10615 00:45:24.728362 <6>[ 1.656133] igb: Copyright (c) 2007-2014 Intel Corporation.
10616 00:45:24.735392 <6>[ 1.661968] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10617 00:45:24.741974 <6>[ 1.668487] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10618 00:45:24.744998 <6>[ 1.674944] sky2: driver version 1.30
10619 00:45:24.751528 <6>[ 1.679881] usbcore: registered new device driver r8152-cfgselector
10620 00:45:24.758641 <6>[ 1.686416] usbcore: registered new interface driver r8152
10621 00:45:24.764829 <6>[ 1.692235] VFIO - User Level meta-driver version: 0.3
10622 00:45:24.771631 <6>[ 1.700475] usbcore: registered new interface driver usb-storage
10623 00:45:24.778196 <6>[ 1.706916] usbcore: registered new device driver onboard-usb-hub
10624 00:45:24.787376 <6>[ 1.716059] mt6397-rtc mt6359-rtc: registered as rtc0
10625 00:45:24.797196 <6>[ 1.721524] mt6397-rtc mt6359-rtc: setting system clock to 2024-06-16T00:45:24 UTC (1718498724)
10626 00:45:24.800596 <6>[ 1.731086] i2c_dev: i2c /dev entries driver
10627 00:45:24.814067 <4>[ 1.743099] cpu cpu0: supply cpu not found, using dummy regulator
10628 00:45:24.820943 <4>[ 1.749540] cpu cpu1: supply cpu not found, using dummy regulator
10629 00:45:24.827401 <4>[ 1.755945] cpu cpu2: supply cpu not found, using dummy regulator
10630 00:45:24.834055 <4>[ 1.762347] cpu cpu3: supply cpu not found, using dummy regulator
10631 00:45:24.840658 <4>[ 1.768746] cpu cpu4: supply cpu not found, using dummy regulator
10632 00:45:24.847245 <4>[ 1.775141] cpu cpu5: supply cpu not found, using dummy regulator
10633 00:45:24.853949 <4>[ 1.781557] cpu cpu6: supply cpu not found, using dummy regulator
10634 00:45:24.860231 <4>[ 1.787958] cpu cpu7: supply cpu not found, using dummy regulator
10635 00:45:24.880252 <6>[ 1.809605] cpu cpu0: EM: created perf domain
10636 00:45:24.883511 <6>[ 1.814559] cpu cpu4: EM: created perf domain
10637 00:45:24.890974 <6>[ 1.820127] sdhci: Secure Digital Host Controller Interface driver
10638 00:45:24.897603 <6>[ 1.826560] sdhci: Copyright(c) Pierre Ossman
10639 00:45:24.904345 <6>[ 1.831515] Synopsys Designware Multimedia Card Interface Driver
10640 00:45:24.910885 <6>[ 1.838143] sdhci-pltfm: SDHCI platform and OF driver helper
10641 00:45:24.914512 <6>[ 1.838185] mmc0: CQHCI version 5.10
10642 00:45:24.920641 <6>[ 1.848071] ledtrig-cpu: registered to indicate activity on CPUs
10643 00:45:24.927824 <6>[ 1.855020] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10644 00:45:24.934342 <6>[ 1.862071] usbcore: registered new interface driver usbhid
10645 00:45:24.937714 <6>[ 1.867892] usbhid: USB HID core driver
10646 00:45:24.943884 <6>[ 1.872058] spi_master spi0: will run message pump with realtime priority
10647 00:45:24.988301 <6>[ 1.910895] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10648 00:45:25.008006 <6>[ 1.926745] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10649 00:45:25.010870 <6>[ 1.937059] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x16014
10650 00:45:25.019778 <6>[ 1.948201] cros-ec-spi spi0.0: Chrome EC device registered
10651 00:45:25.026048 <6>[ 1.954229] mmc0: Command Queue Engine enabled
10652 00:45:25.032635 <6>[ 1.958990] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10653 00:45:25.035898 <6>[ 1.966701] mmcblk0: mmc0:0001 DA4128 116 GiB
10654 00:45:25.049256 <6>[ 1.978393] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10655 00:45:25.059105 <6>[ 1.983599] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10656 00:45:25.065773 <6>[ 1.985837] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10657 00:45:25.069522 <6>[ 1.994945] NET: Registered PF_PACKET protocol family
10658 00:45:25.075640 <6>[ 1.999599] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10659 00:45:25.079223 <6>[ 2.004215] 9pnet: Installing 9P2000 support
10660 00:45:25.086198 <6>[ 2.009998] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10661 00:45:25.089030 <5>[ 2.013914] Key type dns_resolver registered
10662 00:45:25.096338 <6>[ 2.025367] registered taskstats version 1
10663 00:45:25.099580 <5>[ 2.029745] Loading compiled-in X.509 certificates
10664 00:45:25.131386 <4>[ 2.053636] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10665 00:45:25.141181 <4>[ 2.064536] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10666 00:45:25.155742 <6>[ 2.085068] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10667 00:45:25.162835 <6>[ 2.092184] xhci-mtk 11200000.usb: xHCI Host Controller
10668 00:45:25.169662 <6>[ 2.097711] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10669 00:45:25.180073 <6>[ 2.105593] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10670 00:45:25.186601 <6>[ 2.115168] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10671 00:45:25.193034 <6>[ 2.121275] xhci-mtk 11200000.usb: xHCI Host Controller
10672 00:45:25.200043 <6>[ 2.126766] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10673 00:45:25.206392 <6>[ 2.134424] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10674 00:45:25.213399 <6>[ 2.142269] hub 1-0:1.0: USB hub found
10675 00:45:25.216527 <6>[ 2.146318] hub 1-0:1.0: 1 port detected
10676 00:45:25.223397 <6>[ 2.150624] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10677 00:45:25.230093 <6>[ 2.159400] hub 2-0:1.0: USB hub found
10678 00:45:25.233617 <6>[ 2.163428] hub 2-0:1.0: 1 port detected
10679 00:45:25.241380 <6>[ 2.170241] mtk-msdc 11f70000.mmc: Got CD GPIO
10680 00:45:25.257718 <6>[ 2.183081] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10681 00:45:25.267616 <6>[ 2.191566] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10682 00:45:25.274219 <6>[ 2.199909] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10683 00:45:25.283891 <6>[ 2.208268] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10684 00:45:25.290564 <6>[ 2.216608] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10685 00:45:25.300891 <6>[ 2.224965] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10686 00:45:25.307215 <6>[ 2.233303] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10687 00:45:25.316905 <6>[ 2.241652] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10688 00:45:25.323751 <6>[ 2.249991] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10689 00:45:25.333798 <6>[ 2.258340] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10690 00:45:25.340239 <6>[ 2.266678] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10691 00:45:25.350602 <6>[ 2.275027] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10692 00:45:25.356890 <6>[ 2.283366] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10693 00:45:25.366941 <6>[ 2.291714] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10694 00:45:25.373908 <6>[ 2.300054] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10695 00:45:25.380310 <6>[ 2.308747] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10696 00:45:25.386904 <6>[ 2.315920] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10697 00:45:25.393699 <6>[ 2.322712] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10698 00:45:25.403739 <6>[ 2.329532] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10699 00:45:25.410124 <6>[ 2.336457] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10700 00:45:25.416845 <6>[ 2.343313] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10701 00:45:25.426994 <6>[ 2.352443] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10702 00:45:25.437097 <6>[ 2.361564] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10703 00:45:25.446590 <6>[ 2.370865] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10704 00:45:25.456878 <6>[ 2.380332] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10705 00:45:25.466212 <6>[ 2.389800] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10706 00:45:25.472782 <6>[ 2.398919] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10707 00:45:25.482976 <6>[ 2.408387] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10708 00:45:25.492809 <6>[ 2.417506] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10709 00:45:25.502992 <6>[ 2.426800] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10710 00:45:25.512903 <6>[ 2.436994] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10711 00:45:25.522408 <6>[ 2.448409] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10712 00:45:25.529724 <6>[ 2.459008] Trying to probe devices needed for running init ...
10713 00:45:25.540448 <3>[ 2.466300] mt8192-audio 11210000.syscon:mt8192-afe-pcm: could not get audiosys reset:-517
10714 00:45:25.649948 <6>[ 2.575554] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10715 00:45:25.808705 <6>[ 2.737374] hub 1-1:1.0: USB hub found
10716 00:45:25.811190 <6>[ 2.741892] hub 1-1:1.0: 4 ports detected
10717 00:45:25.823680 <6>[ 2.752667] hub 1-1:1.0: USB hub found
10718 00:45:25.826893 <6>[ 2.757109] hub 1-1:1.0: 4 ports detected
10719 00:45:25.934024 <6>[ 2.859822] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10720 00:45:25.960520 <6>[ 2.889543] hub 2-1:1.0: USB hub found
10721 00:45:25.963887 <6>[ 2.894040] hub 2-1:1.0: 3 ports detected
10722 00:45:25.974941 <6>[ 2.903982] hub 2-1:1.0: USB hub found
10723 00:45:25.977788 <6>[ 2.908370] hub 2-1:1.0: 3 ports detected
10724 00:45:26.150017 <6>[ 3.075534] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10725 00:45:26.282309 <6>[ 3.211387] hub 1-1.4:1.0: USB hub found
10726 00:45:26.285224 <6>[ 3.215986] hub 1-1.4:1.0: 2 ports detected
10727 00:45:26.298008 <6>[ 3.227252] hub 1-1.4:1.0: USB hub found
10728 00:45:26.301350 <6>[ 3.231818] hub 1-1.4:1.0: 2 ports detected
10729 00:45:26.361383 <6>[ 3.287517] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10730 00:45:26.470053 <6>[ 3.396174] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10731 00:45:26.506815 <4>[ 3.432579] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10732 00:45:26.516195 <4>[ 3.441673] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10733 00:45:26.551807 <6>[ 3.480992] r8152 2-1.3:1.0 eth0: v1.12.13
10734 00:45:26.597182 <6>[ 3.523331] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10735 00:45:26.789458 <6>[ 3.715343] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10736 00:45:28.143134 <6>[ 5.072571] r8152 2-1.3:1.0 eth0: carrier on
10737 00:45:30.317509 <5>[ 5.099310] Sending DHCP requests .., OK
10738 00:45:30.324388 <6>[ 7.251657] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.21
10739 00:45:30.327572 <6>[ 7.259946] IP-Config: Complete:
10740 00:45:30.340601 <6>[ 7.263443] device=eth0, hwaddr=00:24:32:30:78:ff, ipaddr=192.168.201.21, mask=255.255.255.0, gw=192.168.201.1
10741 00:45:30.347317 <6>[ 7.274150] host=mt8192-asurada-spherion-r0-cbg-8, domain=lava-rack, nis-domain=(none)
10742 00:45:30.354093 <6>[ 7.282765] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10743 00:45:30.360812 <6>[ 7.282774] nameserver0=192.168.201.1
10744 00:45:30.363953 <6>[ 7.294933] clk: Disabling unused clocks
10745 00:45:30.367277 <6>[ 7.300396] ALSA device list:
10746 00:45:30.373672 <6>[ 7.303694] No soundcards found.
10747 00:45:30.381635 <6>[ 7.311446] Freeing unused kernel memory: 8512K
10748 00:45:30.384927 <6>[ 7.316486] Run /init as init process
10749 00:45:30.395062 Loading, please wait...
10750 00:45:30.429752 Starting systemd-udevd version 252.22-1~deb12u1
10751 00:45:30.643591 <6>[ 7.570249] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10752 00:45:30.653750 <6>[ 7.579781] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10753 00:45:30.660163 <6>[ 7.584942] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10754 00:45:30.670053 <6>[ 7.591654] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10755 00:45:30.676925 <6>[ 7.595450] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10756 00:45:30.686750 <4>[ 7.595770] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10757 00:45:30.696582 <6>[ 7.609051] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10758 00:45:30.703100 <6>[ 7.613909] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10759 00:45:30.709853 <6>[ 7.614277] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10760 00:45:30.716478 <6>[ 7.617896] remoteproc remoteproc0: scp is available
10761 00:45:30.719830 <6>[ 7.618021] remoteproc remoteproc0: powering up scp
10762 00:45:30.730023 <6>[ 7.618030] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10763 00:45:30.736182 <6>[ 7.618059] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10764 00:45:30.739370 <6>[ 7.639651] mc: Linux media interface: v0.10
10765 00:45:30.745977 <3>[ 7.640391] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10766 00:45:30.756016 <3>[ 7.640408] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10767 00:45:30.762772 <3>[ 7.640415] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10768 00:45:30.772629 <6>[ 7.645386] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10769 00:45:30.779934 <3>[ 7.645674] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10770 00:45:30.789804 <3>[ 7.645688] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10771 00:45:30.796477 <3>[ 7.645696] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10772 00:45:30.802950 <3>[ 7.645707] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10773 00:45:30.812881 <3>[ 7.645715] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10774 00:45:30.819883 <3>[ 7.646982] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10775 00:45:30.830067 <3>[ 7.647045] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10776 00:45:30.836577 <3>[ 7.647054] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10777 00:45:30.846825 <3>[ 7.647064] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10778 00:45:30.853502 <3>[ 7.647148] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10779 00:45:30.859752 <3>[ 7.647156] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10780 00:45:30.869811 <3>[ 7.647162] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10781 00:45:30.876379 <3>[ 7.647171] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10782 00:45:30.886353 <3>[ 7.647178] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10783 00:45:30.893210 <3>[ 7.647249] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10784 00:45:30.902989 <6>[ 7.650265] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10785 00:45:30.909417 <4>[ 7.678042] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10786 00:45:30.916149 <4>[ 7.678042] Fallback method does not support PEC.
10787 00:45:30.922542 <4>[ 7.679126] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10788 00:45:30.929170 <4>[ 7.679308] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10789 00:45:30.936025 <6>[ 7.684867] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10790 00:45:30.942543 <6>[ 7.698523] videodev: Linux video capture interface: v2.00
10791 00:45:30.952286 <6>[ 7.699399] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10792 00:45:30.959131 <3>[ 7.715270] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10793 00:45:30.969177 <6>[ 7.723142] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10794 00:45:30.975799 <6>[ 7.740678] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10795 00:45:30.982355 <6>[ 7.743298] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10796 00:45:30.989130 <6>[ 7.743300] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10797 00:45:30.995550 <6>[ 7.743307] remoteproc remoteproc0: remote processor scp is now up
10798 00:45:31.005335 <6>[ 7.747233] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10799 00:45:31.015119 <6>[ 7.749009] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10800 00:45:31.018996 <6>[ 7.755510] pci_bus 0000:00: root bus resource [bus 00-ff]
10801 00:45:31.028484 <6>[ 7.766332] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10802 00:45:31.035039 <6>[ 7.771855] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10803 00:45:31.045231 <3>[ 7.780301] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10804 00:45:31.051761 <6>[ 7.784591] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10805 00:45:31.061370 <6>[ 7.787997] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10806 00:45:31.071313 <6>[ 7.788088] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10807 00:45:31.081582 <6>[ 7.788545] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10808 00:45:31.084855 <6>[ 7.821106] Bluetooth: Core ver 2.22
10809 00:45:31.091457 <6>[ 7.828491] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10810 00:45:31.097672 <6>[ 7.836227] NET: Registered PF_BLUETOOTH protocol family
10811 00:45:31.104677 <6>[ 7.849755] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10812 00:45:31.111114 <6>[ 7.849842] pci 0000:00:00.0: supports D1 D2
10813 00:45:31.117362 <6>[ 7.850718] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10814 00:45:31.127384 <6>[ 7.851842] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10815 00:45:31.134006 <6>[ 7.851980] usbcore: registered new interface driver uvcvideo
10816 00:45:31.140634 <6>[ 7.857099] Bluetooth: HCI device and connection manager initialized
10817 00:45:31.147504 <6>[ 7.864367] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10818 00:45:31.157327 <6>[ 7.865579] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10819 00:45:31.160808 <6>[ 7.872292] Bluetooth: HCI socket layer initialized
10820 00:45:31.167107 <6>[ 7.872786] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10821 00:45:31.173730 <6>[ 7.878114] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10822 00:45:31.180405 <6>[ 7.885837] Bluetooth: L2CAP socket layer initialized
10823 00:45:31.187087 <6>[ 7.894631] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10824 00:45:31.193263 <6>[ 7.902432] Bluetooth: SCO socket layer initialized
10825 00:45:31.200186 <6>[ 7.909296] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10826 00:45:31.206777 <6>[ 7.970192] usbcore: registered new interface driver btusb
10827 00:45:31.216654 <4>[ 7.970943] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10828 00:45:31.223206 <3>[ 7.970959] Bluetooth: hci0: Failed to load firmware file (-2)
10829 00:45:31.226603 <3>[ 7.970966] Bluetooth: hci0: Failed to set up firmware (-2)
10830 00:45:31.239814 <4>[ 7.970972] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10831 00:45:31.246723 <6>[ 7.978529] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10832 00:45:31.249639 <6>[ 8.180965] pci 0000:01:00.0: supports D1 D2
10833 00:45:31.256420 <6>[ 8.185485] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10834 00:45:31.277086 <6>[ 8.203244] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10835 00:45:31.283277 <6>[ 8.210134] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10836 00:45:31.290277 <6>[ 8.218215] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10837 00:45:31.300120 <6>[ 8.226212] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10838 00:45:31.306720 <6>[ 8.234212] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10839 00:45:31.316402 <6>[ 8.242213] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10840 00:45:31.319591 <6>[ 8.250212] pci 0000:00:00.0: PCI bridge to [bus 01]
10841 00:45:31.329617 <6>[ 8.255427] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10842 00:45:31.336450 <6>[ 8.263528] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10843 00:45:31.342856 <6>[ 8.270327] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10844 00:45:31.349440 <6>[ 8.277114] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10845 00:45:31.364615 <5>[ 8.290895] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10846 00:45:31.387848 <5>[ 8.314337] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10847 00:45:31.394401 <5>[ 8.321789] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10848 00:45:31.404638 <4>[ 8.330274] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10849 00:45:31.411155 <6>[ 8.339165] cfg80211: failed to load regulatory.db
10850 00:45:31.456670 <6>[ 8.383152] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10851 00:45:31.463300 <6>[ 8.390667] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10852 00:45:31.487746 <6>[ 8.417332] mt7921e 0000:01:00.0: ASIC revision: 79610010
10853 00:45:31.588883 <6>[ 8.515359] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10854 00:45:31.592258 <6>[ 8.515359]
10855 00:45:31.618661 Begin: Loading essential drivers ... done.
10856 00:45:31.621998 Begin: Running /scripts/init-premount ... done.
10857 00:45:31.628636 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10858 00:45:31.638137 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10859 00:45:31.641909 Device /sys/class/net/eth0 found
10860 00:45:31.641997 done.
10861 00:45:31.669533 Begin: Waiting up to 180 secs for any network device to become available ... done.
10862 00:45:31.721707 IP-Config: eth0 hardware address 00:24:32:30:78:ff mtu 1500 DHCP
10863 00:45:31.728412 IP-Config: eth0 complete (dhcp from 192.168.201.1):
10864 00:45:31.735166 address: 192.168.201.21 broadcast: 192.168.201.255 netmask: 255.255.255.0
10865 00:45:31.741284 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10866 00:45:31.748381 host : mt8192-asurada-spherion-r0-cbg-8
10867 00:45:31.754880 domain : lava-rack
10868 00:45:31.758057 rootserver: 192.168.201.1 rootpath:
10869 00:45:31.761522 filename :
10870 00:45:31.766128 done.
10871 00:45:31.774042 Begin: Running /scripts/nfs-bottom ... done.
10872 00:45:31.786874 Begin: Running /scripts/init-bottom ... done.
10873 00:45:31.857298 <6>[ 8.783647] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10874 00:45:33.165693 <6>[ 10.095790] NET: Registered PF_INET6 protocol family
10875 00:45:33.173350 <6>[ 10.103336] Segment Routing with IPv6
10876 00:45:33.176346 <6>[ 10.107324] In-situ OAM (IOAM) with IPv6
10877 00:45:33.356621 <30>[ 10.260167] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10878 00:45:33.363412 <30>[ 10.293303] systemd[1]: Detected architecture arm64.
10879 00:45:33.372934
10880 00:45:33.376146 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10881 00:45:33.376234
10882 00:45:33.403381 <30>[ 10.333591] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10883 00:45:34.521635 <30>[ 11.448593] systemd[1]: Queued start job for default target graphical.target.
10884 00:45:34.561906 <30>[ 11.488724] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10885 00:45:34.568788 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10886 00:45:34.590598 <30>[ 11.517273] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10887 00:45:34.600230 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10888 00:45:34.618269 <30>[ 11.545213] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10889 00:45:34.628326 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10890 00:45:34.646169 <30>[ 11.572880] systemd[1]: Created slice user.slice - User and Session Slice.
10891 00:45:34.652631 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10892 00:45:34.676462 <30>[ 11.599968] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10893 00:45:34.683053 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10894 00:45:34.704200 <30>[ 11.627741] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10895 00:45:34.710746 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10896 00:45:34.739376 <30>[ 11.656149] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10897 00:45:34.749013 <30>[ 11.676074] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10898 00:45:34.755479 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10899 00:45:34.772905 <30>[ 11.699819] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10900 00:45:34.782936 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10901 00:45:34.801557 <30>[ 11.727918] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10902 00:45:34.811217 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10903 00:45:34.825653 <30>[ 11.756001] systemd[1]: Reached target paths.target - Path Units.
10904 00:45:34.835794 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10905 00:45:34.853081 <30>[ 11.779986] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10906 00:45:34.859790 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10907 00:45:34.873740 <30>[ 11.803487] systemd[1]: Reached target slices.target - Slice Units.
10908 00:45:34.883075 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10909 00:45:34.897792 <30>[ 11.827995] systemd[1]: Reached target swap.target - Swaps.
10910 00:45:34.904619 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10911 00:45:34.925064 <30>[ 11.852014] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10912 00:45:34.935176 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10913 00:45:34.952836 <30>[ 11.879976] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10914 00:45:34.962895 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10915 00:45:34.983219 <30>[ 11.910300] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10916 00:45:34.993030 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10917 00:45:35.010143 <30>[ 11.936988] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10918 00:45:35.020121 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10919 00:45:35.037753 <30>[ 11.964889] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10920 00:45:35.044849 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10921 00:45:35.066400 <30>[ 11.993285] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10922 00:45:35.076035 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10923 00:45:35.096988 <30>[ 12.023585] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10924 00:45:35.106286 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10925 00:45:35.125810 <30>[ 12.052746] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10926 00:45:35.135622 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10927 00:45:35.184984 <30>[ 12.112032] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10928 00:45:35.191555 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10929 00:45:35.217724 <30>[ 12.144420] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10930 00:45:35.223780 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10931 00:45:35.248912 <30>[ 12.175870] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10932 00:45:35.255716 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10933 00:45:35.284085 <30>[ 12.204073] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10934 00:45:35.329332 <30>[ 12.256012] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10935 00:45:35.338589 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10936 00:45:35.362751 <30>[ 12.289570] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10937 00:45:35.369709 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10938 00:45:35.416768 <30>[ 12.343912] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10939 00:45:35.423357 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10940 00:45:35.451146 <30>[ 12.377840] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10941 00:45:35.457604 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10942 00:45:35.468084 <6>[ 12.395169] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10943 00:45:35.482899 <30>[ 12.409880] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10944 00:45:35.492744 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10945 00:45:35.513067 <30>[ 12.440092] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10946 00:45:35.519752 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10947 00:45:35.545329 <30>[ 12.472360] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10948 00:45:35.551834 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10949 00:45:35.569685 <6>[ 12.500214] fuse: init (API version 7.37)
10950 00:45:35.582097 <30>[ 12.508923] systemd[1]: Starting systemd-journald.service - Journal Service...
10951 00:45:35.588767 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10952 00:45:35.649444 <30>[ 12.576715] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10953 00:45:35.656267 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10954 00:45:35.683773 <30>[ 12.607159] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10955 00:45:35.690301 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10956 00:45:35.715410 <30>[ 12.642331] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10957 00:45:35.725259 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10958 00:45:35.742492 <3>[ 12.669276] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10959 00:45:35.774130 <30>[ 12.700087] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10960 00:45:35.784194 <3>[ 12.705527] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10961 00:45:35.790249 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10962 00:45:35.812978 <30>[ 12.740105] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
10963 00:45:35.819808 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10964 00:45:35.833637 <3>[ 12.760694] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10965 00:45:35.843524 <30>[ 12.770296] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
10966 00:45:35.850400 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10967 00:45:35.863656 <3>[ 12.790474] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10968 00:45:35.873275 <30>[ 12.800052] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
10969 00:45:35.880429 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10970 00:45:35.893917 <3>[ 12.820749] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10971 00:45:35.903399 <30>[ 12.830224] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
10972 00:45:35.910620 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10973 00:45:35.930121 <30>[ 12.856789] systemd[1]: modprobe@configfs.service: Deactivated successfully.
10974 00:45:35.936211 <3>[ 12.864471] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10975 00:45:35.945982 <30>[ 12.864874] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
10976 00:45:35.955763 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10977 00:45:35.970751 <30>[ 12.900143] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
10978 00:45:35.980869 <3>[ 12.906976] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10979 00:45:35.990363 <30>[ 12.907792] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
10980 00:45:35.997178 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10981 00:45:36.010667 <3>[ 12.937570] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10982 00:45:36.021333 <30>[ 12.948173] systemd[1]: modprobe@drm.service: Deactivated successfully.
10983 00:45:36.027381 <30>[ 12.955660] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
10984 00:45:36.044897 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Mod<3>[ 12.969870] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10985 00:45:36.045020 ule drm.
10986 00:45:36.065988 <30>[ 12.992374] systemd[1]: modprobe@efi_pstore.service: Deactivated successfully.
10987 00:45:36.072399 <30>[ 13.000601] systemd[1]: Finished modprobe@efi_pstore.service - Load Kernel Module efi_pstore.
10988 00:45:36.082414 <3>[ 13.000933] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10989 00:45:36.092272 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10990 00:45:36.113942 <30>[ 13.040704] systemd[1]: modprobe@fuse.service: Deactivated successfully.
10991 00:45:36.120509 <3>[ 13.042275] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10992 00:45:36.130074 <30>[ 13.048204] systemd[1]: Finished modprobe@fuse.service - Load Kernel Module fuse.
10993 00:45:36.136836 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
10994 00:45:36.153332 <3>[ 13.080319] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10995 00:45:36.163293 <30>[ 13.090296] systemd[1]: modprobe@loop.service: Deactivated successfully.
10996 00:45:36.170023 <30>[ 13.097940] systemd[1]: Finished modprobe@loop.service - Load Kernel Module loop.
10997 00:45:36.180290 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10998 00:45:36.201759 <30>[ 13.128381] systemd[1]: Finished systemd-modules-load.service - Load Kernel Modules.
10999 00:45:36.208953 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
11000 00:45:36.229462 <30>[ 13.155974] systemd[1]: Started systemd-journald.service - Journal Service.
11001 00:45:36.242355 <4>[ 13.159431] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
11002 00:45:36.252216 <3>[ 13.178944] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
11003 00:45:36.259050 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
11004 00:45:36.279165 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
11005 00:45:36.301755 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
11006 00:45:36.325625 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
11007 00:45:36.351635 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
11008 00:45:36.389080 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
11009 00:45:36.413976 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
11010 00:45:36.438219 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
11011 00:45:36.462488 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
11012 00:45:36.490625 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
11013 00:45:36.511563 <46>[ 13.438634] systemd-journald[309]: Received client request to flush runtime journal.
11014 00:45:36.518121 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
11015 00:45:36.550507 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
11016 00:45:36.569331 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
11017 00:45:36.589756 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
11018 00:45:36.610179 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
11019 00:45:37.616656 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
11020 00:45:37.665508 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
11021 00:45:37.914739 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
11022 00:45:38.030225 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
11023 00:45:38.049049 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
11024 00:45:38.068603 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
11025 00:45:38.112978 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
11026 00:45:38.140449 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
11027 00:45:38.414994 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
11028 00:45:38.469967 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
11029 00:45:38.540626 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
11030 00:45:38.602594 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
11031 00:45:38.762593 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
11032 00:45:38.779167 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
11033 00:45:38.880919 <6>[ 15.811622] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11034 00:45:38.941198 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
11035 00:45:38.962187 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
11036 00:45:39.010896 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
11037 00:45:39.067432 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11038 00:45:39.085727 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
11039 00:45:39.141933 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11040 00:45:39.162258 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11041 00:45:39.184873 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
11042 00:45:39.209892 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
11043 00:45:39.252673 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11044 00:45:39.268572 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
11045 00:45:39.288303 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
11046 00:45:39.304000 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
11047 00:45:39.319669 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
11048 00:45:39.342641 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
11049 00:45:39.361381 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
11050 00:45:39.377649 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
11051 00:45:39.395859 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
11052 00:45:39.415083 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
11053 00:45:39.431501 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
11054 00:45:39.448912 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
11055 00:45:39.466074 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
11056 00:45:39.482008 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
11057 00:45:39.517707 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11058 00:45:39.610271 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
11059 00:45:39.657280 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11060 00:45:39.680843 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11061 00:45:39.733576 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11062 00:45:39.783664 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11063 00:45:39.822006 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11064 00:45:39.841373 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11065 00:45:39.847694 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11066 00:45:39.907040 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11067 00:45:40.122006 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
11068 00:45:40.141777 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11069 00:45:40.159140 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11070 00:45:40.208964 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11071 00:45:40.273520 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11072 00:45:40.349030
11073 00:45:40.352285 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11074 00:45:40.352359
11075 00:45:40.355244 debian-bookworm-arm64 login: root (automatic login)
11076 00:45:40.355322
11077 00:45:40.680122 Linux debian-bookworm-arm64 6.1.92-cip22 #1 SMP PREEMPT Sun Jun 16 00:28:47 UTC 2024 aarch64
11078 00:45:40.680252
11079 00:45:40.686879 The programs included with the Debian GNU/Linux system are free software;
11080 00:45:40.693455 the exact distribution terms for each program are described in the
11081 00:45:40.696824 individual files in /usr/share/doc/*/copyright.
11082 00:45:40.696903
11083 00:45:40.703356 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11084 00:45:40.706330 permitted by applicable law.
11085 00:45:41.778207 Matched prompt #10: / #
11087 00:45:41.778461 Setting prompt string to ['/ #']
11088 00:45:41.778553 end: 2.2.5.1 login-action (duration 00:00:19) [common]
11090 00:45:41.778730 end: 2.2.5 auto-login-action (duration 00:00:20) [common]
11091 00:45:41.778812 start: 2.2.6 expect-shell-connection (timeout 00:03:21) [common]
11092 00:45:41.778878 Setting prompt string to ['/ #']
11093 00:45:41.778937 Forcing a shell prompt, looking for ['/ #']
11095 00:45:41.829190 / #
11096 00:45:41.829391 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11097 00:45:41.829468 Waiting using forced prompt support (timeout 00:02:30)
11098 00:45:41.834405
11099 00:45:41.834676 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11100 00:45:41.834779 start: 2.2.7 export-device-env (timeout 00:03:21) [common]
11102 00:45:41.935157 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14368401/extract-nfsrootfs-dn_hmfv5'
11103 00:45:41.940632 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14368401/extract-nfsrootfs-dn_hmfv5'
11105 00:45:42.041260 / # export NFS_SERVER_IP='192.168.201.1'
11106 00:45:42.046215 export NFS_SERVER_IP='192.168.201.1'
11107 00:45:42.046535 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11108 00:45:42.046664 end: 2.2 depthcharge-retry (duration 00:01:39) [common]
11109 00:45:42.046763 end: 2 depthcharge-action (duration 00:01:39) [common]
11110 00:45:42.046894 start: 3 lava-test-retry (timeout 00:07:43) [common]
11111 00:45:42.047025 start: 3.1 lava-test-shell (timeout 00:07:43) [common]
11112 00:45:42.047128 Using namespace: common
11114 00:45:42.147602 / # #
11115 00:45:42.148178 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11116 00:45:42.153552 #
11117 00:45:42.154229 Using /lava-14368401
11119 00:45:42.255091 / # export SHELL=/bin/bash
11120 00:45:42.261238 export SHELL=/bin/bash
11122 00:45:42.362888 / # . /lava-14368401/environment
11123 00:45:42.368097 . /lava-14368401/environment
11125 00:45:42.475599 / # /lava-14368401/bin/lava-test-runner /lava-14368401/0
11126 00:45:42.475805 Test shell timeout: 10s (minimum of the action and connection timeout)
11127 00:45:42.481131 /lava-14368401/bin/lava-test-runner /lava-14368401/0
11128 00:45:42.774053 + export TESTRUN_ID=0_timesync-off
11129 00:45:42.777354 + TESTRUN_ID=0_timesync-off
11130 00:45:42.780230 + cd /lava-14368401/0/tests/0_timesync-off
11131 00:45:42.783647 ++ cat uuid
11132 00:45:42.792438 + UUID=14368401_1.6.2.3.1
11133 00:45:42.792890 + set +x
11134 00:45:42.799228 <LAVA_SIGNAL_STARTRUN 0_timesync-off 14368401_1.6.2.3.1>
11135 00:45:42.800036 Received signal: <STARTRUN> 0_timesync-off 14368401_1.6.2.3.1
11136 00:45:42.800423 Starting test lava.0_timesync-off (14368401_1.6.2.3.1)
11137 00:45:42.800863 Skipping test definition patterns.
11138 00:45:42.802471 + systemctl stop systemd-timesyncd
11139 00:45:42.885907 + set +x
11140 00:45:42.889121 <LAVA_SIGNAL_ENDRUN 0_timesync-off 14368401_1.6.2.3.1>
11141 00:45:42.889757 Received signal: <ENDRUN> 0_timesync-off 14368401_1.6.2.3.1
11142 00:45:42.890133 Ending use of test pattern.
11143 00:45:42.890422 Ending test lava.0_timesync-off (14368401_1.6.2.3.1), duration 0.09
11145 00:45:42.988567 + export TESTRUN_ID=1_kselftest-tpm2
11146 00:45:42.991896 + TESTRUN_ID=1_kselftest-tpm2
11147 00:45:42.998214 + cd /lava-14368401/0/tests/1_kselftest-tpm2
11148 00:45:42.998608 ++ cat uuid
11149 00:45:43.006654 + UUID=14368401_1.6.2.3.5
11150 00:45:43.007047 + set +x
11151 00:45:43.013537 <LAVA_SIGNAL_STARTRUN 1_kselftest-tpm2 14368401_1.6.2.3.5>
11152 00:45:43.014245 Received signal: <STARTRUN> 1_kselftest-tpm2 14368401_1.6.2.3.5
11153 00:45:43.014572 Starting test lava.1_kselftest-tpm2 (14368401_1.6.2.3.5)
11154 00:45:43.014930 Skipping test definition patterns.
11155 00:45:43.016752 + cd ./automated/linux/kselftest/
11156 00:45:43.043098 + ./kselftest.sh -c tpm2 -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-24-g0315de64ea248/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11157 00:45:43.101934 INFO: install_deps skipped
11158 00:45:43.622937 --2024-06-16 00:45:43-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-24-g0315de64ea248/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11159 00:45:43.629139 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11160 00:45:43.752172 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11161 00:45:43.877957 HTTP request sent, awaiting response... 200 OK
11162 00:45:43.881474 Length: 1647580 (1.6M) [application/octet-stream]
11163 00:45:43.884884 Saving to: 'kselftest_armhf.tar.gz'
11164 00:45:43.885388
11165 00:45:43.885731
11166 00:45:44.128818 kselftest_armhf.tar 0%[ ] 0 --.-KB/s
11167 00:45:44.379806 kselftest_armhf.tar 2%[ ] 47.81K 187KB/s
11168 00:45:44.630481 kselftest_armhf.tar 13%[=> ] 217.50K 425KB/s
11169 00:45:44.806271 kselftest_armhf.tar 55%[==========> ] 898.59K 1.14MB/s
11170 00:45:44.812470 kselftest_armhf.tar 100%[===================>] 1.57M 1.66MB/s in 0.9s
11171 00:45:44.812925
11172 00:45:44.957339 2024-06-16 00:45:44 (1.66 MB/s) - 'kselftest_armhf.tar.gz' saved [1647580/1647580]
11173 00:45:44.957469
11174 00:45:50.412888 skiplist:
11175 00:45:50.416206 ========================================
11176 00:45:50.419404 ========================================
11177 00:45:50.479635 tpm2:test_smoke.sh
11178 00:45:50.482965 tpm2:test_space.sh
11179 00:45:50.504430 ============== Tests to run ===============
11180 00:45:50.507530 tpm2:test_smoke.sh
11181 00:45:50.507977 tpm2:test_space.sh
11182 00:45:50.514194 ===========End Tests to run ===============
11183 00:45:50.517542 shardfile-tpm2 pass
11184 00:45:50.653348 <12>[ 27.584846] kselftest: Running tests in tpm2
11185 00:45:50.664834 TAP version 13
11186 00:45:50.681450 1..2
11187 00:45:50.722278 # selftests: tpm2: test_smoke.sh
11188 00:45:52.649146 # test_read_partial_overwrite (tpm2_tests.SmokeTest.test_read_partial_overwrite) ... ERROR
11189 00:45:52.655715 # test_read_partial_resp (tpm2_tests.SmokeTest.test_read_partial_resp) ... ERROR
11190 00:45:52.662004 # Exception ignored in: <function Client.__del__ at 0xffff9ce7ccc0>
11191 00:45:52.665292 # Traceback (most recent call last):
11192 00:45:52.675332 # File "/lava-14368401/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11193 00:45:52.675901 # if self.tpm:
11194 00:45:52.678590 # ^^^^^^^^
11195 00:45:52.682038 # AttributeError: 'Client' object has no attribute 'tpm'
11196 00:45:52.688740 # test_seal_with_auth (tpm2_tests.SmokeTest.test_seal_with_auth) ... ERROR
11197 00:45:52.695680 # Exception ignored in: <function Client.__del__ at 0xffff9ce7ccc0>
11198 00:45:52.698728 # Traceback (most recent call last):
11199 00:45:52.708492 # File "/lava-14368401/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11200 00:45:52.708992 # if self.tpm:
11201 00:45:52.711789 # ^^^^^^^^
11202 00:45:52.715054 # AttributeError: 'Client' object has no attribute 'tpm'
11203 00:45:52.725197 # test_seal_with_policy (tpm2_tests.SmokeTest.test_seal_with_policy) ... ERROR
11204 00:45:52.728766 # Exception ignored in: <function Client.__del__ at 0xffff9ce7ccc0>
11205 00:45:52.732118 # Traceback (most recent call last):
11206 00:45:52.741952 # File "/lava-14368401/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11207 00:45:52.745360 # if self.tpm:
11208 00:45:52.745887 # ^^^^^^^^
11209 00:45:52.751791 # AttributeError: 'Client' object has no attribute 'tpm'
11210 00:45:52.758264 # test_seal_with_too_long_auth (tpm2_tests.SmokeTest.test_seal_with_too_long_auth) ... ERROR
11211 00:45:52.764839 # Exception ignored in: <function Client.__del__ at 0xffff9ce7ccc0>
11212 00:45:52.768172 # Traceback (most recent call last):
11213 00:45:52.778243 # File "/lava-14368401/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11214 00:45:52.781436 # if self.tpm:
11215 00:45:52.781861 # ^^^^^^^^
11216 00:45:52.788113 # AttributeError: 'Client' object has no attribute 'tpm'
11217 00:45:52.791702 # test_send_two_cmds (tpm2_tests.SmokeTest.test_send_two_cmds) ... ERROR
11218 00:45:52.798127 # Exception ignored in: <function Client.__del__ at 0xffff9ce7ccc0>
11219 00:45:52.801132 # Traceback (most recent call last):
11220 00:45:52.811221 # File "/lava-14368401/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11221 00:45:52.814634 # if self.tpm:
11222 00:45:52.815062 # ^^^^^^^^
11223 00:45:52.821086 # AttributeError: 'Client' object has no attribute 'tpm'
11224 00:45:52.828047 # test_too_short_cmd (tpm2_tests.SmokeTest.test_too_short_cmd) ... ERROR
11225 00:45:52.834304 # Exception ignored in: <function Client.__del__ at 0xffff9ce7ccc0>
11226 00:45:52.837516 # Traceback (most recent call last):
11227 00:45:52.847625 # File "/lava-14368401/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11228 00:45:52.848126 # if self.tpm:
11229 00:45:52.851039 # ^^^^^^^^
11230 00:45:52.854627 # AttributeError: 'Client' object has no attribute 'tpm'
11231 00:45:52.864369 # test_unseal_with_wrong_auth (tpm2_tests.SmokeTest.test_unseal_with_wrong_auth) ... ERROR
11232 00:45:52.867401 # Exception ignored in: <function Client.__del__ at 0xffff9ce7ccc0>
11233 00:45:52.870721 # Traceback (most recent call last):
11234 00:45:52.880839 # File "/lava-14368401/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11235 00:45:52.883875 # if self.tpm:
11236 00:45:52.884296 # ^^^^^^^^
11237 00:45:52.890615 # AttributeError: 'Client' object has no attribute 'tpm'
11238 00:45:52.897483 # test_unseal_with_wrong_policy (tpm2_tests.SmokeTest.test_unseal_with_wrong_policy) ... ERROR
11239 00:45:52.904294 # Exception ignored in: <function Client.__del__ at 0xffff9ce7ccc0>
11240 00:45:52.907575 # Traceback (most recent call last):
11241 00:45:52.917096 # File "/lava-14368401/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11242 00:45:52.920958 # if self.tpm:
11243 00:45:52.921387 # ^^^^^^^^
11244 00:45:52.927121 # AttributeError: 'Client' object has no attribute 'tpm'
11245 00:45:52.927541 #
11246 00:45:52.933965 # ======================================================================
11247 00:45:52.940875 # ERROR: test_read_partial_overwrite (tpm2_tests.SmokeTest.test_read_partial_overwrite)
11248 00:45:52.947057 # ----------------------------------------------------------------------
11249 00:45:52.950886 # Traceback (most recent call last):
11250 00:45:52.961109 # File "/lava-14368401/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 16, in setUp
11251 00:45:52.964037 # self.root_key = self.client.create_root_key()
11252 00:45:52.971144 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11253 00:45:52.980449 # File "/lava-14368401/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11254 00:45:52.983737 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11255 00:45:52.990697 # ^^^^^^^^^^^^^^^^^^
11256 00:45:53.000363 # File "/lava-14368401/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11257 00:45:53.005349 # raise ProtocolError(cc, rc)
11258 00:45:53.008820 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11259 00:45:53.009243 #
11260 00:45:53.017223 # ======================================================================
11261 00:45:53.024180 # ERROR: test_read_partial_resp (tpm2_tests.SmokeTest.test_read_partial_resp)
11262 00:45:53.030765 # ----------------------------------------------------------------------
11263 00:45:53.034313 # Traceback (most recent call last):
11264 00:45:53.043947 # File "/lava-14368401/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11265 00:45:53.047313 # self.client = tpm2.Client()
11266 00:45:53.047816 # ^^^^^^^^^^^^^
11267 00:45:53.057421 # File "/lava-14368401/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11268 00:45:53.063761 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11269 00:45:53.066657 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11270 00:45:53.073662 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11271 00:45:53.074090 #
11272 00:45:53.080300 # ======================================================================
11273 00:45:53.087032 # ERROR: test_seal_with_auth (tpm2_tests.SmokeTest.test_seal_with_auth)
11274 00:45:53.093509 # ----------------------------------------------------------------------
11275 00:45:53.096740 # Traceback (most recent call last):
11276 00:45:53.106495 # File "/lava-14368401/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11277 00:45:53.109897 # self.client = tpm2.Client()
11278 00:45:53.113187 # ^^^^^^^^^^^^^
11279 00:45:53.123053 # File "/lava-14368401/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11280 00:45:53.126447 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11281 00:45:53.133237 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11282 00:45:53.136751 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11283 00:45:53.137183 #
11284 00:45:53.143194 # ======================================================================
11285 00:45:53.149470 # ERROR: test_seal_with_policy (tpm2_tests.SmokeTest.test_seal_with_policy)
11286 00:45:53.156620 # ----------------------------------------------------------------------
11287 00:45:53.160044 # Traceback (most recent call last):
11288 00:45:53.169912 # File "/lava-14368401/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11289 00:45:53.172789 # self.client = tpm2.Client()
11290 00:45:53.176036 # ^^^^^^^^^^^^^
11291 00:45:53.186596 # File "/lava-14368401/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11292 00:45:53.189867 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11293 00:45:53.196466 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11294 00:45:53.200089 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11295 00:45:53.203069 #
11296 00:45:53.209434 # ======================================================================
11297 00:45:53.216447 # ERROR: test_seal_with_too_long_auth (tpm2_tests.SmokeTest.test_seal_with_too_long_auth)
11298 00:45:53.223026 # ----------------------------------------------------------------------
11299 00:45:53.226075 # Traceback (most recent call last):
11300 00:45:53.236192 # File "/lava-14368401/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11301 00:45:53.239954 # self.client = tpm2.Client()
11302 00:45:53.242547 # ^^^^^^^^^^^^^
11303 00:45:53.253262 # File "/lava-14368401/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11304 00:45:53.256023 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11305 00:45:53.263077 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11306 00:45:53.266314 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11307 00:45:53.266819 #
11308 00:45:53.272927 # ======================================================================
11309 00:45:53.279806 # ERROR: test_send_two_cmds (tpm2_tests.SmokeTest.test_send_two_cmds)
11310 00:45:53.286476 # ----------------------------------------------------------------------
11311 00:45:53.289426 # Traceback (most recent call last):
11312 00:45:53.299072 # File "/lava-14368401/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11313 00:45:53.302594 # self.client = tpm2.Client()
11314 00:45:53.305424 # ^^^^^^^^^^^^^
11315 00:45:53.315869 # File "/lava-14368401/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11316 00:45:53.319072 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11317 00:45:53.325841 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11318 00:45:53.329091 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11319 00:45:53.332193 #
11320 00:45:53.338813 # ======================================================================
11321 00:45:53.342282 # ERROR: test_too_short_cmd (tpm2_tests.SmokeTest.test_too_short_cmd)
11322 00:45:53.348845 # ----------------------------------------------------------------------
11323 00:45:53.352513 # Traceback (most recent call last):
11324 00:45:53.362122 # File "/lava-14368401/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11325 00:45:53.365649 # self.client = tpm2.Client()
11326 00:45:53.369051 # ^^^^^^^^^^^^^
11327 00:45:53.379178 # File "/lava-14368401/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11328 00:45:53.385047 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11329 00:45:53.388788 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11330 00:45:53.396640 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11331 00:45:53.397197 #
11332 00:45:53.400359 # ======================================================================
11333 00:45:53.410310 # ERROR: test_unseal_with_wrong_auth (tpm2_tests.SmokeTest.test_unseal_with_wrong_auth)
11334 00:45:53.414280 # ----------------------------------------------------------------------
11335 00:45:53.417187 # Traceback (most recent call last):
11336 00:45:53.428117 # File "/lava-14368401/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11337 00:45:53.431648 # self.client = tpm2.Client()
11338 00:45:53.436258 # ^^^^^^^^^^^^^
11339 00:45:53.444543 # File "/lava-14368401/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11340 00:45:53.447953 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11341 00:45:53.454904 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11342 00:45:53.457931 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11343 00:45:53.458437 #
11344 00:45:53.465639 # ======================================================================
11345 00:45:53.475790 # ERROR: test_unseal_with_wrong_policy (tpm2_tests.SmokeTest.test_unseal_with_wrong_policy)
11346 00:45:53.479087 # ----------------------------------------------------------------------
11347 00:45:53.482189 # Traceback (most recent call last):
11348 00:45:53.492534 # File "/lava-14368401/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11349 00:45:53.495925 # self.client = tpm2.Client()
11350 00:45:53.499239 # ^^^^^^^^^^^^^
11351 00:45:53.509072 # File "/lava-14368401/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11352 00:45:53.515115 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11353 00:45:53.518842 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11354 00:45:53.525663 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11355 00:45:53.526227 #
11356 00:45:53.532304 # ----------------------------------------------------------------------
11357 00:45:53.535683 # Ran 9 tests in 0.052s
11358 00:45:53.536181 #
11359 00:45:53.536514 # FAILED (errors=9)
11360 00:45:53.541732 # test_async (tpm2_tests.AsyncTest.test_async) ... ok
11361 00:45:53.548906 # test_flush_invalid_context (tpm2_tests.AsyncTest.test_flush_invalid_context) ... ok
11362 00:45:53.549440 #
11363 00:45:53.555263 # ----------------------------------------------------------------------
11364 00:45:53.558661 # Ran 2 tests in 0.030s
11365 00:45:53.559181 #
11366 00:45:53.559527 # OK
11367 00:45:53.562404 ok 1 selftests: tpm2: test_smoke.sh
11368 00:45:53.565407 # selftests: tpm2: test_space.sh
11369 00:45:53.572319 # test_flush_context (tpm2_tests.SpaceTest.test_flush_context) ... ERROR
11370 00:45:53.575045 # test_get_handles (tpm2_tests.SpaceTest.test_get_handles) ... ERROR
11371 00:45:53.581685 # test_invalid_cc (tpm2_tests.SpaceTest.test_invalid_cc) ... ERROR
11372 00:45:53.588560 # test_make_two_spaces (tpm2_tests.SpaceTest.test_make_two_spaces) ... ERROR
11373 00:45:53.589112 #
11374 00:45:53.595318 # ======================================================================
11375 00:45:53.601811 # ERROR: test_flush_context (tpm2_tests.SpaceTest.test_flush_context)
11376 00:45:53.608281 # ----------------------------------------------------------------------
11377 00:45:53.611508 # Traceback (most recent call last):
11378 00:45:53.625005 # File "/lava-14368401/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 261, in test_flush_context
11379 00:45:53.627850 # root1 = space1.create_root_key()
11380 00:45:53.631435 # ^^^^^^^^^^^^^^^^^^^^^^^^
11381 00:45:53.641299 # File "/lava-14368401/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11382 00:45:53.645126 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11383 00:45:53.651404 # ^^^^^^^^^^^^^^^^^^
11384 00:45:53.661137 # File "/lava-14368401/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11385 00:45:53.665023 # raise ProtocolError(cc, rc)
11386 00:45:53.671712 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11387 00:45:53.672223 #
11388 00:45:53.678098 # ======================================================================
11389 00:45:53.681361 # ERROR: test_get_handles (tpm2_tests.SpaceTest.test_get_handles)
11390 00:45:53.688315 # ----------------------------------------------------------------------
11391 00:45:53.691611 # Traceback (most recent call last):
11392 00:45:53.704586 # File "/lava-14368401/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 271, in test_get_handles
11393 00:45:53.705147 # space1.create_root_key()
11394 00:45:53.717813 # File "/lava-14368401/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11395 00:45:53.721032 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11396 00:45:53.728049 # ^^^^^^^^^^^^^^^^^^
11397 00:45:53.738025 # File "/lava-14368401/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11398 00:45:53.741103 # raise ProtocolError(cc, rc)
11399 00:45:53.744689 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11400 00:45:53.745200 #
11401 00:45:53.751498 # ======================================================================
11402 00:45:53.757539 # ERROR: test_invalid_cc (tpm2_tests.SpaceTest.test_invalid_cc)
11403 00:45:53.764503 # ----------------------------------------------------------------------
11404 00:45:53.767892 # Traceback (most recent call last):
11405 00:45:53.778255 # File "/lava-14368401/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 290, in test_invalid_cc
11406 00:45:53.780741 # root1 = space1.create_root_key()
11407 00:45:53.784094 # ^^^^^^^^^^^^^^^^^^^^^^^^
11408 00:45:53.797610 # File "/lava-14368401/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11409 00:45:53.800861 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11410 00:45:53.807408 # ^^^^^^^^^^^^^^^^^^
11411 00:45:53.817144 # File "/lava-14368401/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11412 00:45:53.820830 # raise ProtocolError(cc, rc)
11413 00:45:53.823904 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11414 00:45:53.824421 #
11415 00:45:53.830443 # ======================================================================
11416 00:45:53.836909 # ERROR: test_make_two_spaces (tpm2_tests.SpaceTest.test_make_two_spaces)
11417 00:45:53.843918 # ----------------------------------------------------------------------
11418 00:45:53.846949 # Traceback (most recent call last):
11419 00:45:53.860199 # File "/lava-14368401/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 247, in test_make_two_spaces
11420 00:45:53.863726 # root1 = space1.create_root_key()
11421 00:45:53.866971 # ^^^^^^^^^^^^^^^^^^^^^^^^
11422 00:45:53.876539 # File "/lava-14368401/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11423 00:45:53.883160 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11424 00:45:53.886486 # ^^^^^^^^^^^^^^^^^^
11425 00:45:53.896528 # File "/lava-14368401/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11426 00:45:53.899928 # raise ProtocolError(cc, rc)
11427 00:45:53.906786 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11428 00:45:53.907182 #
11429 00:45:53.912990 # ----------------------------------------------------------------------
11430 00:45:53.916235 # Ran 4 tests in 0.094s
11431 00:45:53.916822 #
11432 00:45:53.917322 # FAILED (errors=4)
11433 00:45:53.919638 not ok 2 selftests: tpm2: test_space.sh # exit=1
11434 00:45:54.584942 tpm2_test_smoke_sh pass
11435 00:45:54.588297 tpm2_test_space_sh fail
11436 00:45:54.658482 + ../../utils/send-to-lava.sh ./output/result.txt
11437 00:45:54.753732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-tpm2 RESULT=pass>
11438 00:45:54.754523 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-tpm2 RESULT=pass
11440 00:45:54.825970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm2_test_smoke_sh RESULT=pass>
11441 00:45:54.826675 Received signal: <TESTCASE> TEST_CASE_ID=tpm2_test_smoke_sh RESULT=pass
11443 00:45:54.893103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm2_test_space_sh RESULT=fail>
11444 00:45:54.893740 Received signal: <TESTCASE> TEST_CASE_ID=tpm2_test_space_sh RESULT=fail
11446 00:45:54.896542 + set +x
11447 00:45:54.900329 <LAVA_SIGNAL_ENDRUN 1_kselftest-tpm2 14368401_1.6.2.3.5>
11448 00:45:54.901116 Received signal: <ENDRUN> 1_kselftest-tpm2 14368401_1.6.2.3.5
11449 00:45:54.901468 Ending use of test pattern.
11450 00:45:54.901759 Ending test lava.1_kselftest-tpm2 (14368401_1.6.2.3.5), duration 11.89
11452 00:45:54.903351 <LAVA_TEST_RUNNER EXIT>
11453 00:45:54.903963 ok: lava_test_shell seems to have completed
11454 00:45:54.904449 shardfile-tpm2: pass
tpm2_test_smoke_sh: pass
tpm2_test_space_sh: fail
11455 00:45:54.904886 end: 3.1 lava-test-shell (duration 00:00:13) [common]
11456 00:45:54.905280 end: 3 lava-test-retry (duration 00:00:13) [common]
11457 00:45:54.905682 start: 4 finalize (timeout 00:07:30) [common]
11458 00:45:54.906075 start: 4.1 power-off (timeout 00:00:30) [common]
11459 00:45:54.906712 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-8', '--port=1', '--command=off']
11460 00:45:55.113194 >> Command sent successfully.
11461 00:45:55.126593 Returned 0 in 0 seconds
11462 00:45:55.227903 end: 4.1 power-off (duration 00:00:00) [common]
11464 00:45:55.229346 start: 4.2 read-feedback (timeout 00:07:30) [common]
11465 00:45:55.230615 Listened to connection for namespace 'common' for up to 1s
11466 00:45:56.231273 Finalising connection for namespace 'common'
11467 00:45:56.231972 Disconnecting from shell: Finalise
11468 00:45:56.232388 / #
11469 00:45:56.333404 end: 4.2 read-feedback (duration 00:00:01) [common]
11470 00:45:56.334079 end: 4 finalize (duration 00:00:01) [common]
11471 00:45:56.334696 Cleaning after the job
11472 00:45:56.335207 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14368401/tftp-deploy-ngfchemh/ramdisk
11473 00:45:56.345408 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14368401/tftp-deploy-ngfchemh/kernel
11474 00:45:56.380873 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14368401/tftp-deploy-ngfchemh/dtb
11475 00:45:56.381177 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14368401/tftp-deploy-ngfchemh/nfsrootfs
11476 00:45:56.449799 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14368401/tftp-deploy-ngfchemh/modules
11477 00:45:56.455274 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14368401
11478 00:45:56.999748 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14368401
11479 00:45:56.999913 Job finished correctly