Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 33
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 24
1 00:39:25.145857 lava-dispatcher, installed at version: 2024.03
2 00:39:25.146059 start: 0 validate
3 00:39:25.146192 Start time: 2024-06-16 00:39:25.146184+00:00 (UTC)
4 00:39:25.146306 Using caching service: 'http://localhost/cache/?uri=%s'
5 00:39:25.146435 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-libcamera%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 00:39:25.398656 Using caching service: 'http://localhost/cache/?uri=%s'
7 00:39:25.399402 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22-24-g0315de64ea248%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 00:39:41.163665 Using caching service: 'http://localhost/cache/?uri=%s'
9 00:39:41.164658 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22-24-g0315de64ea248%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 00:39:41.417734 Using caching service: 'http://localhost/cache/?uri=%s'
11 00:39:41.418431 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-libcamera%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 00:39:41.914080 Using caching service: 'http://localhost/cache/?uri=%s'
13 00:39:41.914774 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22-24-g0315de64ea248%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 00:39:43.921446 validate duration: 18.78
16 00:39:43.921720 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 00:39:43.921821 start: 1.1 download-retry (timeout 00:10:00) [common]
18 00:39:43.921907 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 00:39:43.922029 Not decompressing ramdisk as can be used compressed.
20 00:39:43.922117 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-libcamera/20240313.0/arm64/initrd.cpio.gz
21 00:39:43.922182 saving as /var/lib/lava/dispatcher/tmp/14368371/tftp-deploy-8gvq5l49/ramdisk/initrd.cpio.gz
22 00:39:43.922245 total size: 5628151 (5 MB)
23 00:39:44.172363 progress 0 % (0 MB)
24 00:39:44.174892 progress 5 % (0 MB)
25 00:39:44.177476 progress 10 % (0 MB)
26 00:39:44.179750 progress 15 % (0 MB)
27 00:39:44.182287 progress 20 % (1 MB)
28 00:39:44.184626 progress 25 % (1 MB)
29 00:39:44.187203 progress 30 % (1 MB)
30 00:39:44.189761 progress 35 % (1 MB)
31 00:39:44.191994 progress 40 % (2 MB)
32 00:39:44.194578 progress 45 % (2 MB)
33 00:39:44.196834 progress 50 % (2 MB)
34 00:39:44.199367 progress 55 % (2 MB)
35 00:39:44.202007 progress 60 % (3 MB)
36 00:39:44.204219 progress 65 % (3 MB)
37 00:39:44.206774 progress 70 % (3 MB)
38 00:39:44.209006 progress 75 % (4 MB)
39 00:39:44.211536 progress 80 % (4 MB)
40 00:39:44.213809 progress 85 % (4 MB)
41 00:39:44.216302 progress 90 % (4 MB)
42 00:39:44.218291 progress 95 % (5 MB)
43 00:39:44.219681 progress 100 % (5 MB)
44 00:39:44.219891 5 MB downloaded in 0.30 s (18.03 MB/s)
45 00:39:44.220040 end: 1.1.1 http-download (duration 00:00:00) [common]
47 00:39:44.220273 end: 1.1 download-retry (duration 00:00:00) [common]
48 00:39:44.220363 start: 1.2 download-retry (timeout 00:10:00) [common]
49 00:39:44.220450 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 00:39:44.220574 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-24-g0315de64ea248/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 00:39:44.220645 saving as /var/lib/lava/dispatcher/tmp/14368371/tftp-deploy-8gvq5l49/kernel/Image
52 00:39:44.220742 total size: 54813184 (52 MB)
53 00:39:44.220835 No compression specified
54 00:39:44.222012 progress 0 % (0 MB)
55 00:39:44.235967 progress 5 % (2 MB)
56 00:39:44.250170 progress 10 % (5 MB)
57 00:39:44.264030 progress 15 % (7 MB)
58 00:39:44.278083 progress 20 % (10 MB)
59 00:39:44.292222 progress 25 % (13 MB)
60 00:39:44.306222 progress 30 % (15 MB)
61 00:39:44.320690 progress 35 % (18 MB)
62 00:39:44.335270 progress 40 % (20 MB)
63 00:39:44.349624 progress 45 % (23 MB)
64 00:39:44.363810 progress 50 % (26 MB)
65 00:39:44.378013 progress 55 % (28 MB)
66 00:39:44.391829 progress 60 % (31 MB)
67 00:39:44.405955 progress 65 % (34 MB)
68 00:39:44.419962 progress 70 % (36 MB)
69 00:39:44.434082 progress 75 % (39 MB)
70 00:39:44.448886 progress 80 % (41 MB)
71 00:39:44.463212 progress 85 % (44 MB)
72 00:39:44.477485 progress 90 % (47 MB)
73 00:39:44.491623 progress 95 % (49 MB)
74 00:39:44.505455 progress 100 % (52 MB)
75 00:39:44.505723 52 MB downloaded in 0.28 s (183.43 MB/s)
76 00:39:44.505881 end: 1.2.1 http-download (duration 00:00:00) [common]
78 00:39:44.506119 end: 1.2 download-retry (duration 00:00:00) [common]
79 00:39:44.506205 start: 1.3 download-retry (timeout 00:09:59) [common]
80 00:39:44.506290 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 00:39:44.506426 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-24-g0315de64ea248/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 00:39:44.506496 saving as /var/lib/lava/dispatcher/tmp/14368371/tftp-deploy-8gvq5l49/dtb/mt8192-asurada-spherion-r0.dtb
83 00:39:44.506556 total size: 47258 (0 MB)
84 00:39:44.506616 No compression specified
85 00:39:44.507775 progress 69 % (0 MB)
86 00:39:44.508050 progress 100 % (0 MB)
87 00:39:44.508207 0 MB downloaded in 0.00 s (27.34 MB/s)
88 00:39:44.508330 end: 1.3.1 http-download (duration 00:00:00) [common]
90 00:39:44.508630 end: 1.3 download-retry (duration 00:00:00) [common]
91 00:39:44.508731 start: 1.4 download-retry (timeout 00:09:59) [common]
92 00:39:44.508814 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 00:39:44.508927 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-libcamera/20240313.0/arm64/full.rootfs.tar.xz
94 00:39:44.508995 saving as /var/lib/lava/dispatcher/tmp/14368371/tftp-deploy-8gvq5l49/nfsrootfs/full.rootfs.tar
95 00:39:44.509056 total size: 69067788 (65 MB)
96 00:39:44.509117 Using unxz to decompress xz
97 00:39:44.513207 progress 0 % (0 MB)
98 00:39:44.718435 progress 5 % (3 MB)
99 00:39:44.935379 progress 10 % (6 MB)
100 00:39:45.150973 progress 15 % (9 MB)
101 00:39:45.324469 progress 20 % (13 MB)
102 00:39:45.510421 progress 25 % (16 MB)
103 00:39:45.718962 progress 30 % (19 MB)
104 00:39:45.841097 progress 35 % (23 MB)
105 00:39:45.940628 progress 40 % (26 MB)
106 00:39:46.146412 progress 45 % (29 MB)
107 00:39:46.369216 progress 50 % (32 MB)
108 00:39:46.588188 progress 55 % (36 MB)
109 00:39:46.813286 progress 60 % (39 MB)
110 00:39:47.015324 progress 65 % (42 MB)
111 00:39:47.224999 progress 70 % (46 MB)
112 00:39:47.430287 progress 75 % (49 MB)
113 00:39:47.647916 progress 80 % (52 MB)
114 00:39:47.832361 progress 85 % (56 MB)
115 00:39:48.028007 progress 90 % (59 MB)
116 00:39:48.235973 progress 95 % (62 MB)
117 00:39:48.447206 progress 100 % (65 MB)
118 00:39:48.453596 65 MB downloaded in 3.94 s (16.70 MB/s)
119 00:39:48.453951 end: 1.4.1 http-download (duration 00:00:04) [common]
121 00:39:48.454370 end: 1.4 download-retry (duration 00:00:04) [common]
122 00:39:48.454509 start: 1.5 download-retry (timeout 00:09:55) [common]
123 00:39:48.454642 start: 1.5.1 http-download (timeout 00:09:55) [common]
124 00:39:48.454860 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-24-g0315de64ea248/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 00:39:48.454975 saving as /var/lib/lava/dispatcher/tmp/14368371/tftp-deploy-8gvq5l49/modules/modules.tar
126 00:39:48.455073 total size: 8608736 (8 MB)
127 00:39:48.455177 Using unxz to decompress xz
128 00:39:48.460477 progress 0 % (0 MB)
129 00:39:48.480118 progress 5 % (0 MB)
130 00:39:48.507889 progress 10 % (0 MB)
131 00:39:48.538497 progress 15 % (1 MB)
132 00:39:48.562970 progress 20 % (1 MB)
133 00:39:48.587229 progress 25 % (2 MB)
134 00:39:48.611664 progress 30 % (2 MB)
135 00:39:48.636708 progress 35 % (2 MB)
136 00:39:48.664208 progress 40 % (3 MB)
137 00:39:48.687536 progress 45 % (3 MB)
138 00:39:48.712175 progress 50 % (4 MB)
139 00:39:48.737891 progress 55 % (4 MB)
140 00:39:48.762961 progress 60 % (4 MB)
141 00:39:48.787633 progress 65 % (5 MB)
142 00:39:48.813173 progress 70 % (5 MB)
143 00:39:48.839481 progress 75 % (6 MB)
144 00:39:48.865958 progress 80 % (6 MB)
145 00:39:48.890888 progress 85 % (7 MB)
146 00:39:48.916949 progress 90 % (7 MB)
147 00:39:48.942940 progress 95 % (7 MB)
148 00:39:48.968631 progress 100 % (8 MB)
149 00:39:48.974303 8 MB downloaded in 0.52 s (15.81 MB/s)
150 00:39:48.974620 end: 1.5.1 http-download (duration 00:00:01) [common]
152 00:39:48.975045 end: 1.5 download-retry (duration 00:00:01) [common]
153 00:39:48.975172 start: 1.6 prepare-tftp-overlay (timeout 00:09:55) [common]
154 00:39:48.975299 start: 1.6.1 extract-nfsrootfs (timeout 00:09:55) [common]
155 00:39:50.626477 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/14368371/extract-nfsrootfs-u2n90c2q
156 00:39:50.626691 end: 1.6.1 extract-nfsrootfs (duration 00:00:02) [common]
157 00:39:50.626790 start: 1.6.2 lava-overlay (timeout 00:09:53) [common]
158 00:39:50.626981 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14368371/lava-overlay-r8exq5c0
159 00:39:50.627149 makedir: /var/lib/lava/dispatcher/tmp/14368371/lava-overlay-r8exq5c0/lava-14368371/bin
160 00:39:50.627285 makedir: /var/lib/lava/dispatcher/tmp/14368371/lava-overlay-r8exq5c0/lava-14368371/tests
161 00:39:50.627415 makedir: /var/lib/lava/dispatcher/tmp/14368371/lava-overlay-r8exq5c0/lava-14368371/results
162 00:39:50.627558 Creating /var/lib/lava/dispatcher/tmp/14368371/lava-overlay-r8exq5c0/lava-14368371/bin/lava-add-keys
163 00:39:50.627746 Creating /var/lib/lava/dispatcher/tmp/14368371/lava-overlay-r8exq5c0/lava-14368371/bin/lava-add-sources
164 00:39:50.627878 Creating /var/lib/lava/dispatcher/tmp/14368371/lava-overlay-r8exq5c0/lava-14368371/bin/lava-background-process-start
165 00:39:50.628013 Creating /var/lib/lava/dispatcher/tmp/14368371/lava-overlay-r8exq5c0/lava-14368371/bin/lava-background-process-stop
166 00:39:50.628175 Creating /var/lib/lava/dispatcher/tmp/14368371/lava-overlay-r8exq5c0/lava-14368371/bin/lava-common-functions
167 00:39:50.628334 Creating /var/lib/lava/dispatcher/tmp/14368371/lava-overlay-r8exq5c0/lava-14368371/bin/lava-echo-ipv4
168 00:39:50.628520 Creating /var/lib/lava/dispatcher/tmp/14368371/lava-overlay-r8exq5c0/lava-14368371/bin/lava-install-packages
169 00:39:50.628660 Creating /var/lib/lava/dispatcher/tmp/14368371/lava-overlay-r8exq5c0/lava-14368371/bin/lava-installed-packages
170 00:39:50.628786 Creating /var/lib/lava/dispatcher/tmp/14368371/lava-overlay-r8exq5c0/lava-14368371/bin/lava-os-build
171 00:39:50.628912 Creating /var/lib/lava/dispatcher/tmp/14368371/lava-overlay-r8exq5c0/lava-14368371/bin/lava-probe-channel
172 00:39:50.629038 Creating /var/lib/lava/dispatcher/tmp/14368371/lava-overlay-r8exq5c0/lava-14368371/bin/lava-probe-ip
173 00:39:50.629177 Creating /var/lib/lava/dispatcher/tmp/14368371/lava-overlay-r8exq5c0/lava-14368371/bin/lava-target-ip
174 00:39:50.629338 Creating /var/lib/lava/dispatcher/tmp/14368371/lava-overlay-r8exq5c0/lava-14368371/bin/lava-target-mac
175 00:39:50.629464 Creating /var/lib/lava/dispatcher/tmp/14368371/lava-overlay-r8exq5c0/lava-14368371/bin/lava-target-storage
176 00:39:50.629597 Creating /var/lib/lava/dispatcher/tmp/14368371/lava-overlay-r8exq5c0/lava-14368371/bin/lava-test-case
177 00:39:50.629770 Creating /var/lib/lava/dispatcher/tmp/14368371/lava-overlay-r8exq5c0/lava-14368371/bin/lava-test-event
178 00:39:50.629920 Creating /var/lib/lava/dispatcher/tmp/14368371/lava-overlay-r8exq5c0/lava-14368371/bin/lava-test-feedback
179 00:39:50.630045 Creating /var/lib/lava/dispatcher/tmp/14368371/lava-overlay-r8exq5c0/lava-14368371/bin/lava-test-raise
180 00:39:50.630177 Creating /var/lib/lava/dispatcher/tmp/14368371/lava-overlay-r8exq5c0/lava-14368371/bin/lava-test-reference
181 00:39:50.630302 Creating /var/lib/lava/dispatcher/tmp/14368371/lava-overlay-r8exq5c0/lava-14368371/bin/lava-test-runner
182 00:39:50.630427 Creating /var/lib/lava/dispatcher/tmp/14368371/lava-overlay-r8exq5c0/lava-14368371/bin/lava-test-set
183 00:39:50.630551 Creating /var/lib/lava/dispatcher/tmp/14368371/lava-overlay-r8exq5c0/lava-14368371/bin/lava-test-shell
184 00:39:50.630681 Updating /var/lib/lava/dispatcher/tmp/14368371/lava-overlay-r8exq5c0/lava-14368371/bin/lava-install-packages (oe)
185 00:39:50.630831 Updating /var/lib/lava/dispatcher/tmp/14368371/lava-overlay-r8exq5c0/lava-14368371/bin/lava-installed-packages (oe)
186 00:39:50.630957 Creating /var/lib/lava/dispatcher/tmp/14368371/lava-overlay-r8exq5c0/lava-14368371/environment
187 00:39:50.631061 LAVA metadata
188 00:39:50.631132 - LAVA_JOB_ID=14368371
189 00:39:50.631194 - LAVA_DISPATCHER_IP=192.168.201.1
190 00:39:50.631309 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:53) [common]
191 00:39:50.631376 skipped lava-vland-overlay
192 00:39:50.631450 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
193 00:39:50.631531 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:53) [common]
194 00:39:50.631625 skipped lava-multinode-overlay
195 00:39:50.631735 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
196 00:39:50.631843 start: 1.6.2.3 test-definition (timeout 00:09:53) [common]
197 00:39:50.631953 Loading test definitions
198 00:39:50.632079 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:53) [common]
199 00:39:50.632189 Using /lava-14368371 at stage 0
200 00:39:50.632587 uuid=14368371_1.6.2.3.1 testdef=None
201 00:39:50.632678 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
202 00:39:50.632766 start: 1.6.2.3.2 test-overlay (timeout 00:09:53) [common]
203 00:39:50.633463 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
205 00:39:50.633782 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:53) [common]
206 00:39:50.634412 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
208 00:39:50.634649 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:53) [common]
209 00:39:50.635238 runner path: /var/lib/lava/dispatcher/tmp/14368371/lava-overlay-r8exq5c0/lava-14368371/0/tests/0_lc-compliance test_uuid 14368371_1.6.2.3.1
210 00:39:50.635397 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
212 00:39:50.635683 Creating lava-test-runner.conf files
213 00:39:50.635774 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14368371/lava-overlay-r8exq5c0/lava-14368371/0 for stage 0
214 00:39:50.635895 - 0_lc-compliance
215 00:39:50.636025 end: 1.6.2.3 test-definition (duration 00:00:00) [common]
216 00:39:50.636114 start: 1.6.2.4 compress-overlay (timeout 00:09:53) [common]
217 00:39:50.642778 end: 1.6.2.4 compress-overlay (duration 00:00:00) [common]
218 00:39:50.642931 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:53) [common]
219 00:39:50.643025 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
220 00:39:50.643119 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
221 00:39:50.643208 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:53) [common]
222 00:39:50.816269 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
223 00:39:50.816648 start: 1.6.4 extract-modules (timeout 00:09:53) [common]
224 00:39:50.816769 extracting modules file /var/lib/lava/dispatcher/tmp/14368371/tftp-deploy-8gvq5l49/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14368371/extract-nfsrootfs-u2n90c2q
225 00:39:51.046009 extracting modules file /var/lib/lava/dispatcher/tmp/14368371/tftp-deploy-8gvq5l49/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14368371/extract-overlay-ramdisk-vap8lljd/ramdisk
226 00:39:51.272194 end: 1.6.4 extract-modules (duration 00:00:00) [common]
227 00:39:51.272373 start: 1.6.5 apply-overlay-tftp (timeout 00:09:53) [common]
228 00:39:51.272472 [common] Applying overlay to NFS
229 00:39:51.272544 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14368371/compress-overlay-bgtivobt/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14368371/extract-nfsrootfs-u2n90c2q
230 00:39:51.279333 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
231 00:39:51.279474 start: 1.6.6 configure-preseed-file (timeout 00:09:53) [common]
232 00:39:51.279571 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
233 00:39:51.279666 start: 1.6.7 compress-ramdisk (timeout 00:09:53) [common]
234 00:39:51.279751 Building ramdisk /var/lib/lava/dispatcher/tmp/14368371/extract-overlay-ramdisk-vap8lljd/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14368371/extract-overlay-ramdisk-vap8lljd/ramdisk
235 00:39:51.635208 >> 130405 blocks
236 00:39:53.720495 rename /var/lib/lava/dispatcher/tmp/14368371/extract-overlay-ramdisk-vap8lljd/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14368371/tftp-deploy-8gvq5l49/ramdisk/ramdisk.cpio.gz
237 00:39:53.721034 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
238 00:39:53.721203 start: 1.6.8 prepare-kernel (timeout 00:09:50) [common]
239 00:39:53.721389 start: 1.6.8.1 prepare-fit (timeout 00:09:50) [common]
240 00:39:53.721530 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14368371/tftp-deploy-8gvq5l49/kernel/Image']
241 00:40:08.026474 Returned 0 in 14 seconds
242 00:40:08.127116 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14368371/tftp-deploy-8gvq5l49/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14368371/tftp-deploy-8gvq5l49/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14368371/tftp-deploy-8gvq5l49/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14368371/tftp-deploy-8gvq5l49/kernel/image.itb
243 00:40:08.508135 output: FIT description: Kernel Image image with one or more FDT blobs
244 00:40:08.508513 output: Created: Sun Jun 16 01:40:08 2024
245 00:40:08.508594 output: Image 0 (kernel-1)
246 00:40:08.508661 output: Description:
247 00:40:08.508725 output: Created: Sun Jun 16 01:40:08 2024
248 00:40:08.508788 output: Type: Kernel Image
249 00:40:08.508849 output: Compression: lzma compressed
250 00:40:08.508912 output: Data Size: 13126376 Bytes = 12818.73 KiB = 12.52 MiB
251 00:40:08.508974 output: Architecture: AArch64
252 00:40:08.509036 output: OS: Linux
253 00:40:08.509096 output: Load Address: 0x00000000
254 00:40:08.509154 output: Entry Point: 0x00000000
255 00:40:08.509212 output: Hash algo: crc32
256 00:40:08.509297 output: Hash value: c791a20a
257 00:40:08.509370 output: Image 1 (fdt-1)
258 00:40:08.509425 output: Description: mt8192-asurada-spherion-r0
259 00:40:08.509481 output: Created: Sun Jun 16 01:40:08 2024
260 00:40:08.509537 output: Type: Flat Device Tree
261 00:40:08.509592 output: Compression: uncompressed
262 00:40:08.509645 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
263 00:40:08.509699 output: Architecture: AArch64
264 00:40:08.509753 output: Hash algo: crc32
265 00:40:08.509806 output: Hash value: 0f8e4d2e
266 00:40:08.509859 output: Image 2 (ramdisk-1)
267 00:40:08.509913 output: Description: unavailable
268 00:40:08.509967 output: Created: Sun Jun 16 01:40:08 2024
269 00:40:08.510021 output: Type: RAMDisk Image
270 00:40:08.510074 output: Compression: Unknown Compression
271 00:40:08.510128 output: Data Size: 18726880 Bytes = 18287.97 KiB = 17.86 MiB
272 00:40:08.510182 output: Architecture: AArch64
273 00:40:08.510267 output: OS: Linux
274 00:40:08.510320 output: Load Address: unavailable
275 00:40:08.510373 output: Entry Point: unavailable
276 00:40:08.510427 output: Hash algo: crc32
277 00:40:08.510480 output: Hash value: d6ebf837
278 00:40:08.510533 output: Default Configuration: 'conf-1'
279 00:40:08.510586 output: Configuration 0 (conf-1)
280 00:40:08.510639 output: Description: mt8192-asurada-spherion-r0
281 00:40:08.510711 output: Kernel: kernel-1
282 00:40:08.510780 output: Init Ramdisk: ramdisk-1
283 00:40:08.510832 output: FDT: fdt-1
284 00:40:08.510885 output: Loadables: kernel-1
285 00:40:08.510955 output:
286 00:40:08.511177 end: 1.6.8.1 prepare-fit (duration 00:00:15) [common]
287 00:40:08.511275 end: 1.6.8 prepare-kernel (duration 00:00:15) [common]
288 00:40:08.511380 end: 1.6 prepare-tftp-overlay (duration 00:00:20) [common]
289 00:40:08.511484 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:35) [common]
290 00:40:08.511566 No LXC device requested
291 00:40:08.511647 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
292 00:40:08.511731 start: 1.8 deploy-device-env (timeout 00:09:35) [common]
293 00:40:08.511811 end: 1.8 deploy-device-env (duration 00:00:00) [common]
294 00:40:08.511879 Checking files for TFTP limit of 4294967296 bytes.
295 00:40:08.512408 end: 1 tftp-deploy (duration 00:00:25) [common]
296 00:40:08.512516 start: 2 depthcharge-action (timeout 00:05:00) [common]
297 00:40:08.512608 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
298 00:40:08.512734 substitutions:
299 00:40:08.512800 - {DTB}: 14368371/tftp-deploy-8gvq5l49/dtb/mt8192-asurada-spherion-r0.dtb
300 00:40:08.512867 - {INITRD}: 14368371/tftp-deploy-8gvq5l49/ramdisk/ramdisk.cpio.gz
301 00:40:08.512927 - {KERNEL}: 14368371/tftp-deploy-8gvq5l49/kernel/Image
302 00:40:08.512985 - {LAVA_MAC}: None
303 00:40:08.513042 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/14368371/extract-nfsrootfs-u2n90c2q
304 00:40:08.513098 - {NFS_SERVER_IP}: 192.168.201.1
305 00:40:08.513153 - {PRESEED_CONFIG}: None
306 00:40:08.513208 - {PRESEED_LOCAL}: None
307 00:40:08.513285 - {RAMDISK}: 14368371/tftp-deploy-8gvq5l49/ramdisk/ramdisk.cpio.gz
308 00:40:08.513357 - {ROOT_PART}: None
309 00:40:08.513411 - {ROOT}: None
310 00:40:08.513465 - {SERVER_IP}: 192.168.201.1
311 00:40:08.513519 - {TEE}: None
312 00:40:08.513572 Parsed boot commands:
313 00:40:08.513626 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
314 00:40:08.513809 Parsed boot commands: tftpboot 192.168.201.1 14368371/tftp-deploy-8gvq5l49/kernel/image.itb 14368371/tftp-deploy-8gvq5l49/kernel/cmdline
315 00:40:08.513900 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
316 00:40:08.513989 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
317 00:40:08.514082 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
318 00:40:08.514166 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
319 00:40:08.514258 Not connected, no need to disconnect.
320 00:40:08.514351 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
321 00:40:08.514432 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
322 00:40:08.514502 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-2'
323 00:40:08.518312 Setting prompt string to ['lava-test: # ']
324 00:40:08.518725 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
325 00:40:08.518848 end: 2.2.1 reset-connection (duration 00:00:00) [common]
326 00:40:08.518976 start: 2.2.2 reset-device (timeout 00:05:00) [common]
327 00:40:08.519101 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
328 00:40:08.519315 Calling: ['/usr/local/bin/chromebook-reboot.sh', 'mt8192-asurada-spherion-r0-cbg-2']
329 00:40:22.500085 Returned 0 in 13 seconds
330 00:40:22.600751 end: 2.2.2.1 pdu-reboot (duration 00:00:14) [common]
332 00:40:22.601084 end: 2.2.2 reset-device (duration 00:00:14) [common]
333 00:40:22.601182 start: 2.2.3 depthcharge-start (timeout 00:04:46) [common]
334 00:40:22.601318 Setting prompt string to 'Starting depthcharge on Spherion...'
335 00:40:22.601398 Changing prompt to 'Starting depthcharge on Spherion...'
336 00:40:22.601475 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
337 00:40:22.601880 [Enter `^Ec?' for help]
338 00:40:22.601959
339 00:40:22.602024
340 00:40:22.602086 F0: 102B 0000
341 00:40:22.602145
342 00:40:22.602206 F3: 1001 0000 [0200]
343 00:40:22.602266
344 00:40:22.602323 F3: 1001 0000
345 00:40:22.602383
346 00:40:22.602447 F7: 102D 0000
347 00:40:22.602548
348 00:40:22.602644 F1: 0000 0000
349 00:40:22.602765
350 00:40:22.602823 V0: 0000 0000 [0001]
351 00:40:22.602879
352 00:40:22.602934 00: 0007 8000
353 00:40:22.602993
354 00:40:22.603047 01: 0000 0000
355 00:40:22.603102
356 00:40:22.603156 BP: 0C00 0209 [0000]
357 00:40:22.603209
358 00:40:22.603262 G0: 1182 0000
359 00:40:22.603314
360 00:40:22.603367 EC: 0000 0021 [4000]
361 00:40:22.603420
362 00:40:22.603472 S7: 0000 0000 [0000]
363 00:40:22.603525
364 00:40:22.603578 CC: 0000 0000 [0001]
365 00:40:22.603630
366 00:40:22.603683 T0: 0000 0040 [010F]
367 00:40:22.603736
368 00:40:22.603788 Jump to BL
369 00:40:22.603841
370 00:40:22.603892
371 00:40:22.603945
372 00:40:22.603998 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
373 00:40:22.604056 ARM64: Exception handlers installed.
374 00:40:22.604114 ARM64: Testing exception
375 00:40:22.604170 ARM64: Done test exception
376 00:40:22.604223 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
377 00:40:22.604277 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
378 00:40:22.604331 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
379 00:40:22.604384 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
380 00:40:22.604437 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
381 00:40:22.604491 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
382 00:40:22.604545 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
383 00:40:22.604598 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
384 00:40:22.604651 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
385 00:40:22.604704 WDT: Last reset was cold boot
386 00:40:22.604757 SPI1(PAD0) initialized at 2873684 Hz
387 00:40:22.604810 SPI5(PAD0) initialized at 992727 Hz
388 00:40:22.604862 VBOOT: Loading verstage.
389 00:40:22.604915 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
390 00:40:22.604968 FMAP: Found "FLASH" version 1.1 at 0x20000.
391 00:40:22.605022 FMAP: base = 0x0 size = 0x800000 #areas = 25
392 00:40:22.605075 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
393 00:40:22.605128 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
394 00:40:22.605182 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
395 00:40:22.605235 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
396 00:40:22.605335
397 00:40:22.605390
398 00:40:22.605443 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
399 00:40:22.605497 ARM64: Exception handlers installed.
400 00:40:22.605550 ARM64: Testing exception
401 00:40:22.605603 ARM64: Done test exception
402 00:40:22.605655 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
403 00:40:22.605709 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
404 00:40:22.605762 Probing TPM: . done!
405 00:40:22.605815 TPM ready after 0 ms
406 00:40:22.605867 Connected to device vid:did:rid of 1ae0:0028:00
407 00:40:22.605921 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
408 00:40:22.605975 Initialized TPM device CR50 revision 0
409 00:40:22.606027 tlcl_send_startup: Startup return code is 0
410 00:40:22.606080 TPM: setup succeeded
411 00:40:22.606132 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
412 00:40:22.606186 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
413 00:40:22.606239 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
414 00:40:22.606292 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
415 00:40:22.606345 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
416 00:40:22.606399 in-header: 03 07 00 00 08 00 00 00
417 00:40:22.606451 in-data: aa e4 47 04 13 02 00 00
418 00:40:22.606504 Chrome EC: UHEPI supported
419 00:40:22.606556 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
420 00:40:22.606609 in-header: 03 a9 00 00 08 00 00 00
421 00:40:22.606662 in-data: 84 60 60 08 00 00 00 00
422 00:40:22.606714 Phase 1
423 00:40:22.606767 FMAP: area GBB found @ 3f5000 (12032 bytes)
424 00:40:22.606821 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
425 00:40:22.606874 VB2:vb2_check_recovery() Recovery was requested manually
426 00:40:22.606928 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x7
427 00:40:22.606980 Recovery requested (1009000e)
428 00:40:22.607033 TPM: Extending digest for VBOOT: boot mode into PCR 0
429 00:40:22.607086 tlcl_extend: response is 0
430 00:40:22.607139 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
431 00:40:22.607193 tlcl_extend: response is 0
432 00:40:22.607253 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
433 00:40:22.607354 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
434 00:40:22.607453 BS: bootblock times (exec / console): total (unknown) / 148 ms
435 00:40:22.607568
436 00:40:22.607625
437 00:40:22.607680 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
438 00:40:22.607736 ARM64: Exception handlers installed.
439 00:40:22.607790 ARM64: Testing exception
440 00:40:22.607844 ARM64: Done test exception
441 00:40:22.607897 pmic_efuse_setting: Set efuses in 11 msecs
442 00:40:22.607951 pmwrap_interface_init: Select PMIF_VLD_RDY
443 00:40:22.608011 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
444 00:40:22.608069 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
445 00:40:22.608343 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
446 00:40:22.608406 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
447 00:40:22.608462 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
448 00:40:22.608516 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
449 00:40:22.608570 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
450 00:40:22.608623 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
451 00:40:22.608676 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
452 00:40:22.608730 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
453 00:40:22.608783 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
454 00:40:22.608836 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
455 00:40:22.608889 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
456 00:40:22.608941 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
457 00:40:22.608994 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
458 00:40:22.609048 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
459 00:40:22.609100 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
460 00:40:22.609152 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
461 00:40:22.609205 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
462 00:40:22.609284 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
463 00:40:22.609354 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
464 00:40:22.609408 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
465 00:40:22.609460 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
466 00:40:22.609513 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
467 00:40:22.609565 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
468 00:40:22.609618 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
469 00:40:22.609671 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
470 00:40:22.609723 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
471 00:40:22.609775 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
472 00:40:22.609828 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
473 00:40:22.609881 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
474 00:40:22.609933 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
475 00:40:22.609986 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
476 00:40:22.610039 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
477 00:40:22.610092 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
478 00:40:22.610144 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
479 00:40:22.610197 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
480 00:40:22.610250 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
481 00:40:22.610302 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
482 00:40:22.610355 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
483 00:40:22.610408 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
484 00:40:22.610461 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
485 00:40:22.610513 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
486 00:40:22.610566 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
487 00:40:22.610618 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
488 00:40:22.610671 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
489 00:40:22.610723 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
490 00:40:22.610775 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
491 00:40:22.610828 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
492 00:40:22.610880 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
493 00:40:22.610932 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
494 00:40:22.610984 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
495 00:40:22.611038 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
496 00:40:22.611108 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
497 00:40:22.611163 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
498 00:40:22.611217 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
499 00:40:22.611270 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
500 00:40:22.611332 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
501 00:40:22.611386 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
502 00:40:22.611439 [RTC]rtc_enable_dcxo,68: con=0x406, osc32con=0xde6b, sec=0x0
503 00:40:22.611492 [RTC]rtc_check_state,173: con=406, pwrkey1=a357, pwrkey2=67d2
504 00:40:22.611545 [RTC]rtc_osc_init,62: osc32con val = 0xde6b
505 00:40:22.611598 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
506 00:40:22.611651 [RTC]rtc_get_frequency_meter,154: input=15, output=854
507 00:40:22.611703 [RTC]rtc_get_frequency_meter,154: input=7, output=726
508 00:40:22.611755 [RTC]rtc_get_frequency_meter,154: input=11, output=790
509 00:40:22.611807 [RTC]rtc_get_frequency_meter,154: input=13, output=822
510 00:40:22.611860 [RTC]rtc_get_frequency_meter,154: input=12, output=806
511 00:40:22.611912 [RTC]rtc_get_frequency_meter,154: input=11, output=790
512 00:40:22.611964 [RTC]rtc_get_frequency_meter,154: input=12, output=806
513 00:40:22.612018 [RTC]rtc_eosc_cali,47: left: 11, middle: 11, right: 12
514 00:40:22.612071 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6b
515 00:40:22.612314 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
516 00:40:22.612378 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
517 00:40:22.612433 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
518 00:40:22.612487 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
519 00:40:22.612540 ADC[4]: Raw value=904064 ID=7
520 00:40:22.612594 ADC[3]: Raw value=213546 ID=1
521 00:40:22.612667 RAM Code: 0x71
522 00:40:22.612764 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
523 00:40:22.612825 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
524 00:40:22.612881 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
525 00:40:22.612952 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
526 00:40:22.613021 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
527 00:40:22.613082 in-header: 03 07 00 00 08 00 00 00
528 00:40:22.613179 in-data: aa e4 47 04 13 02 00 00
529 00:40:22.613288 Chrome EC: UHEPI supported
530 00:40:22.613359 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
531 00:40:22.613414 in-header: 03 a9 00 00 08 00 00 00
532 00:40:22.613468 in-data: 84 60 60 08 00 00 00 00
533 00:40:22.613522 MRC: failed to locate region type 0.
534 00:40:22.613575 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
535 00:40:22.613629 DRAM-K: Running full calibration
536 00:40:22.613682 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
537 00:40:22.613735 header.status = 0x0
538 00:40:22.613788 header.version = 0x6 (expected: 0x6)
539 00:40:22.613841 header.size = 0xd00 (expected: 0xd00)
540 00:40:22.613894 header.flags = 0x0
541 00:40:22.613947 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
542 00:40:22.614001 read SPI 0x72590 0x1c583: 12500 us, 9287 KB/s, 74.296 Mbps
543 00:40:22.614055 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
544 00:40:22.614111 dram_init: ddr_geometry: 2
545 00:40:22.614167 [EMI] MDL number = 2
546 00:40:22.614224 [EMI] Get MDL freq = 0
547 00:40:22.614277 dram_init: ddr_type: 0
548 00:40:22.614330 is_discrete_lpddr4: 1
549 00:40:22.614382 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
550 00:40:22.614435
551 00:40:22.614488
552 00:40:22.614540 [Bian_co] ETT version 0.0.0.1
553 00:40:22.614593 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
554 00:40:22.614646
555 00:40:22.614698 dramc_set_vcore_voltage set vcore to 650000
556 00:40:22.614751 Read voltage for 800, 4
557 00:40:22.614804 Vio18 = 0
558 00:40:22.614857 Vcore = 650000
559 00:40:22.614909 Vdram = 0
560 00:40:22.614961 Vddq = 0
561 00:40:22.615013 Vmddr = 0
562 00:40:22.615068 dram_init: config_dvfs: 1
563 00:40:22.615146 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
564 00:40:22.615202 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
565 00:40:22.615255 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
566 00:40:22.615308 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
567 00:40:22.615362 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
568 00:40:22.615415 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
569 00:40:22.615468 MEM_TYPE=3, freq_sel=18
570 00:40:22.615520 sv_algorithm_assistance_LP4_1600
571 00:40:22.615573 ============ PULL DRAM RESETB DOWN ============
572 00:40:22.615627 ========== PULL DRAM RESETB DOWN end =========
573 00:40:22.615680 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
574 00:40:22.615733 ===================================
575 00:40:22.615816 LPDDR4 DRAM CONFIGURATION
576 00:40:22.615872 ===================================
577 00:40:22.615926 EX_ROW_EN[0] = 0x0
578 00:40:22.615979 EX_ROW_EN[1] = 0x0
579 00:40:22.616031 LP4Y_EN = 0x0
580 00:40:22.616084 WORK_FSP = 0x0
581 00:40:22.616137 WL = 0x2
582 00:40:22.616189 RL = 0x2
583 00:40:22.616241 BL = 0x2
584 00:40:22.616293 RPST = 0x0
585 00:40:22.616346 RD_PRE = 0x0
586 00:40:22.616397 WR_PRE = 0x1
587 00:40:22.616450 WR_PST = 0x0
588 00:40:22.616501 DBI_WR = 0x0
589 00:40:22.616554 DBI_RD = 0x0
590 00:40:22.616606 OTF = 0x1
591 00:40:22.616659 ===================================
592 00:40:22.616712 ===================================
593 00:40:22.616765 ANA top config
594 00:40:22.616818 ===================================
595 00:40:22.616871 DLL_ASYNC_EN = 0
596 00:40:22.616924 ALL_SLAVE_EN = 1
597 00:40:22.616976 NEW_RANK_MODE = 1
598 00:40:22.617032 DLL_IDLE_MODE = 1
599 00:40:22.617097 LP45_APHY_COMB_EN = 1
600 00:40:22.617214 TX_ODT_DIS = 1
601 00:40:22.617311 NEW_8X_MODE = 1
602 00:40:22.617367 ===================================
603 00:40:22.617420 ===================================
604 00:40:22.617480 data_rate = 1600
605 00:40:22.617534 CKR = 1
606 00:40:22.617588 DQ_P2S_RATIO = 8
607 00:40:22.617640 ===================================
608 00:40:22.617693 CA_P2S_RATIO = 8
609 00:40:22.617746 DQ_CA_OPEN = 0
610 00:40:22.617798 DQ_SEMI_OPEN = 0
611 00:40:22.617851 CA_SEMI_OPEN = 0
612 00:40:22.617909 CA_FULL_RATE = 0
613 00:40:22.617984 DQ_CKDIV4_EN = 1
614 00:40:22.618055 CA_CKDIV4_EN = 1
615 00:40:22.618109 CA_PREDIV_EN = 0
616 00:40:22.618162 PH8_DLY = 0
617 00:40:22.618232 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
618 00:40:22.618299 DQ_AAMCK_DIV = 4
619 00:40:22.618352 CA_AAMCK_DIV = 4
620 00:40:22.618405 CA_ADMCK_DIV = 4
621 00:40:22.618458 DQ_TRACK_CA_EN = 0
622 00:40:22.618511 CA_PICK = 800
623 00:40:22.618564 CA_MCKIO = 800
624 00:40:22.618617 MCKIO_SEMI = 0
625 00:40:22.618669 PLL_FREQ = 3068
626 00:40:22.618722 DQ_UI_PI_RATIO = 32
627 00:40:22.618775 CA_UI_PI_RATIO = 0
628 00:40:22.618828 ===================================
629 00:40:22.618881 ===================================
630 00:40:22.618933 memory_type:LPDDR4
631 00:40:22.618986 GP_NUM : 10
632 00:40:22.619039 SRAM_EN : 1
633 00:40:22.619098 MD32_EN : 0
634 00:40:22.619185 ===================================
635 00:40:22.619467 [ANA_INIT] >>>>>>>>>>>>>>
636 00:40:22.619531 <<<<<< [CONFIGURE PHASE]: ANA_TX
637 00:40:22.619590 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
638 00:40:22.619644 ===================================
639 00:40:22.619699 data_rate = 1600,PCW = 0X7600
640 00:40:22.619752 ===================================
641 00:40:22.619806 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
642 00:40:22.619859 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
643 00:40:22.619913 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
644 00:40:22.619967 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
645 00:40:22.620020 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
646 00:40:22.620073 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
647 00:40:22.620126 [ANA_INIT] flow start
648 00:40:22.620179 [ANA_INIT] PLL >>>>>>>>
649 00:40:22.620232 [ANA_INIT] PLL <<<<<<<<
650 00:40:22.620285 [ANA_INIT] MIDPI >>>>>>>>
651 00:40:22.620338 [ANA_INIT] MIDPI <<<<<<<<
652 00:40:22.620390 [ANA_INIT] DLL >>>>>>>>
653 00:40:22.620443 [ANA_INIT] flow end
654 00:40:22.620496 ============ LP4 DIFF to SE enter ============
655 00:40:22.620549 ============ LP4 DIFF to SE exit ============
656 00:40:22.620602 [ANA_INIT] <<<<<<<<<<<<<
657 00:40:22.620662 [Flow] Enable top DCM control >>>>>
658 00:40:22.620717 [Flow] Enable top DCM control <<<<<
659 00:40:22.620769 Enable DLL master slave shuffle
660 00:40:22.620822 ==============================================================
661 00:40:22.620875 Gating Mode config
662 00:40:22.620928 ==============================================================
663 00:40:22.620981 Config description:
664 00:40:22.621033 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
665 00:40:22.621088 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
666 00:40:22.621141 SELPH_MODE 0: By rank 1: By Phase
667 00:40:22.621193 ==============================================================
668 00:40:22.621247 GAT_TRACK_EN = 1
669 00:40:22.621331 RX_GATING_MODE = 2
670 00:40:22.621386 RX_GATING_TRACK_MODE = 2
671 00:40:22.621454 SELPH_MODE = 1
672 00:40:22.621507 PICG_EARLY_EN = 1
673 00:40:22.621559 VALID_LAT_VALUE = 1
674 00:40:22.621612 ==============================================================
675 00:40:22.621665 Enter into Gating configuration >>>>
676 00:40:22.621718 Exit from Gating configuration <<<<
677 00:40:22.621771 Enter into DVFS_PRE_config >>>>>
678 00:40:22.621823 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
679 00:40:22.621880 Exit from DVFS_PRE_config <<<<<
680 00:40:22.621933 Enter into PICG configuration >>>>
681 00:40:22.621986 Exit from PICG configuration <<<<
682 00:40:22.622038 [RX_INPUT] configuration >>>>>
683 00:40:22.622092 [RX_INPUT] configuration <<<<<
684 00:40:22.622144 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
685 00:40:22.622198 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
686 00:40:22.622251 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
687 00:40:22.622304 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
688 00:40:22.622357 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
689 00:40:22.622410 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
690 00:40:22.622462 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
691 00:40:22.622515 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
692 00:40:22.622567 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
693 00:40:22.622620 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
694 00:40:22.622673 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
695 00:40:22.622725 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
696 00:40:22.622778 ===================================
697 00:40:22.622831 LPDDR4 DRAM CONFIGURATION
698 00:40:22.622884 ===================================
699 00:40:22.622936 EX_ROW_EN[0] = 0x0
700 00:40:22.622989 EX_ROW_EN[1] = 0x0
701 00:40:22.623041 LP4Y_EN = 0x0
702 00:40:22.623093 WORK_FSP = 0x0
703 00:40:22.623145 WL = 0x2
704 00:40:22.623198 RL = 0x2
705 00:40:22.623249 BL = 0x2
706 00:40:22.623301 RPST = 0x0
707 00:40:22.623380 RD_PRE = 0x0
708 00:40:22.623485 WR_PRE = 0x1
709 00:40:22.623581 WR_PST = 0x0
710 00:40:22.623665 DBI_WR = 0x0
711 00:40:22.623779 DBI_RD = 0x0
712 00:40:22.623861 OTF = 0x1
713 00:40:22.623944 ===================================
714 00:40:22.624028 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
715 00:40:22.624111 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
716 00:40:22.624194 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
717 00:40:22.624278 ===================================
718 00:40:22.624364 LPDDR4 DRAM CONFIGURATION
719 00:40:22.624447 ===================================
720 00:40:22.624529 EX_ROW_EN[0] = 0x10
721 00:40:22.624613 EX_ROW_EN[1] = 0x0
722 00:40:22.624701 LP4Y_EN = 0x0
723 00:40:22.624790 WORK_FSP = 0x0
724 00:40:22.624864 WL = 0x2
725 00:40:22.624931 RL = 0x2
726 00:40:22.624983 BL = 0x2
727 00:40:22.625036 RPST = 0x0
728 00:40:22.625088 RD_PRE = 0x0
729 00:40:22.625141 WR_PRE = 0x1
730 00:40:22.625194 WR_PST = 0x0
731 00:40:22.625247 DBI_WR = 0x0
732 00:40:22.625368 DBI_RD = 0x0
733 00:40:22.625440 OTF = 0x1
734 00:40:22.625494 ===================================
735 00:40:22.625547 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
736 00:40:22.625601 nWR fixed to 40
737 00:40:22.625654 [ModeRegInit_LP4] CH0 RK0
738 00:40:22.625707 [ModeRegInit_LP4] CH0 RK1
739 00:40:22.625760 [ModeRegInit_LP4] CH1 RK0
740 00:40:22.625812 [ModeRegInit_LP4] CH1 RK1
741 00:40:22.625865 match AC timing 13
742 00:40:22.625917 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
743 00:40:22.626166 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
744 00:40:22.626226 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
745 00:40:22.626281 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
746 00:40:22.626336 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
747 00:40:22.626389 [EMI DOE] emi_dcm 0
748 00:40:22.626443 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
749 00:40:22.626497 ==
750 00:40:22.626550 Dram Type= 6, Freq= 0, CH_0, rank 0
751 00:40:22.626603 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
752 00:40:22.626657 ==
753 00:40:22.626709 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
754 00:40:22.626763 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
755 00:40:22.626817 [CA 0] Center 37 (7~68) winsize 62
756 00:40:22.626870 [CA 1] Center 37 (6~68) winsize 63
757 00:40:22.626922 [CA 2] Center 35 (5~65) winsize 61
758 00:40:22.626975 [CA 3] Center 34 (4~65) winsize 62
759 00:40:22.627027 [CA 4] Center 33 (3~64) winsize 62
760 00:40:22.627080 [CA 5] Center 33 (3~64) winsize 62
761 00:40:22.627132
762 00:40:22.627184 [CmdBusTrainingLP45] Vref(ca) range 1: 32
763 00:40:22.627237
764 00:40:22.627290 [CATrainingPosCal] consider 1 rank data
765 00:40:22.627348 u2DelayCellTimex100 = 270/100 ps
766 00:40:22.627429 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
767 00:40:22.627484 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
768 00:40:22.627581 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
769 00:40:22.627634 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
770 00:40:22.627687 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
771 00:40:22.627739 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
772 00:40:22.627791
773 00:40:22.627843 CA PerBit enable=1, Macro0, CA PI delay=33
774 00:40:22.627896
775 00:40:22.627947 [CBTSetCACLKResult] CA Dly = 33
776 00:40:22.628010 CS Dly: 5 (0~36)
777 00:40:22.628063 ==
778 00:40:22.628116 Dram Type= 6, Freq= 0, CH_0, rank 1
779 00:40:22.628168 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
780 00:40:22.628222 ==
781 00:40:22.628275 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
782 00:40:22.628328 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
783 00:40:22.628381 [CA 0] Center 38 (7~69) winsize 63
784 00:40:22.628435 [CA 1] Center 37 (7~68) winsize 62
785 00:40:22.628487 [CA 2] Center 35 (4~66) winsize 63
786 00:40:22.628540 [CA 3] Center 35 (4~66) winsize 63
787 00:40:22.628593 [CA 4] Center 34 (3~65) winsize 63
788 00:40:22.628646 [CA 5] Center 33 (3~64) winsize 62
789 00:40:22.628698
790 00:40:22.628750 [CmdBusTrainingLP45] Vref(ca) range 1: 34
791 00:40:22.628802
792 00:40:22.628854 [CATrainingPosCal] consider 2 rank data
793 00:40:22.628906 u2DelayCellTimex100 = 270/100 ps
794 00:40:22.628959 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
795 00:40:22.629031 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
796 00:40:22.629129 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
797 00:40:22.629213 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
798 00:40:22.629342 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
799 00:40:22.629426 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
800 00:40:22.629535
801 00:40:22.629621 CA PerBit enable=1, Macro0, CA PI delay=33
802 00:40:22.629705
803 00:40:22.629787 [CBTSetCACLKResult] CA Dly = 33
804 00:40:22.629870 CS Dly: 6 (0~38)
805 00:40:22.629952
806 00:40:22.630035 ----->DramcWriteLeveling(PI) begin...
807 00:40:22.630118 ==
808 00:40:22.630201 Dram Type= 6, Freq= 0, CH_0, rank 0
809 00:40:22.630284 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
810 00:40:22.630367 ==
811 00:40:22.630450 Write leveling (Byte 0): 31 => 31
812 00:40:22.630533 Write leveling (Byte 1): 26 => 26
813 00:40:22.630614 DramcWriteLeveling(PI) end<-----
814 00:40:22.630670
815 00:40:22.630723 ==
816 00:40:22.630776 Dram Type= 6, Freq= 0, CH_0, rank 0
817 00:40:22.630829 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
818 00:40:22.630882 ==
819 00:40:22.630935 [Gating] SW mode calibration
820 00:40:22.630988 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
821 00:40:22.631042 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
822 00:40:22.631114 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
823 00:40:22.631199 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
824 00:40:22.631280 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
825 00:40:22.631341 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 00:40:22.631395 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 00:40:22.631449 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 00:40:22.631501 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
829 00:40:22.631554 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
830 00:40:22.631607 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
831 00:40:22.631661 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
832 00:40:22.631713 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
833 00:40:22.631767 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
834 00:40:22.631819 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
835 00:40:22.631872 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
836 00:40:22.631925 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
837 00:40:22.631977 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
838 00:40:22.632029 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
839 00:40:22.632081 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
840 00:40:22.632134 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
841 00:40:22.632186 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
842 00:40:22.632239 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
843 00:40:22.632291 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
844 00:40:22.632345 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
845 00:40:22.632397 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
846 00:40:22.632450 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
847 00:40:22.632502 0 9 4 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
848 00:40:22.632555 0 9 8 | B1->B0 | 2323 3434 | 1 1 | (1 1) (1 1)
849 00:40:22.632608 0 9 12 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
850 00:40:22.632661 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
851 00:40:22.632914 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
852 00:40:22.632976 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
853 00:40:22.633031 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
854 00:40:22.633085 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
855 00:40:22.633137 0 10 4 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 0)
856 00:40:22.633191 0 10 8 | B1->B0 | 3434 2323 | 0 0 | (0 1) (0 0)
857 00:40:22.633243 0 10 12 | B1->B0 | 2727 2323 | 1 0 | (1 0) (0 0)
858 00:40:22.633344 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 00:40:22.633450 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 00:40:22.633564 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 00:40:22.633648 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 00:40:22.633731 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 00:40:22.633815 0 11 4 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
864 00:40:22.633898 0 11 8 | B1->B0 | 2c2c 4545 | 1 1 | (0 0) (0 0)
865 00:40:22.633981 0 11 12 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
866 00:40:22.634082 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
867 00:40:22.634171 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
868 00:40:22.634255 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
869 00:40:22.634375 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
870 00:40:22.634458 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
871 00:40:22.634541 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
872 00:40:22.634624 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
873 00:40:22.634707 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
874 00:40:22.634790 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
875 00:40:22.634873 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
876 00:40:22.634956 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
877 00:40:22.635039 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
878 00:40:22.635122 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
879 00:40:22.635204 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
880 00:40:22.635287 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
881 00:40:22.635374 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
882 00:40:22.635463 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
883 00:40:22.635560 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
884 00:40:22.635646 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
885 00:40:22.635729 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
886 00:40:22.635812 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
887 00:40:22.635895 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
888 00:40:22.635978 Total UI for P1: 0, mck2ui 16
889 00:40:22.636062 best dqsien dly found for B0: ( 0, 14, 2)
890 00:40:22.636145 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
891 00:40:22.636229 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
892 00:40:22.636311 Total UI for P1: 0, mck2ui 16
893 00:40:22.636394 best dqsien dly found for B1: ( 0, 14, 8)
894 00:40:22.636477 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
895 00:40:22.636560 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
896 00:40:22.636641
897 00:40:22.636723 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
898 00:40:22.636806 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
899 00:40:22.636888 [Gating] SW calibration Done
900 00:40:22.636970 ==
901 00:40:22.637052 Dram Type= 6, Freq= 0, CH_0, rank 0
902 00:40:22.637135 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
903 00:40:22.637221 ==
904 00:40:22.637319 RX Vref Scan: 0
905 00:40:22.637388
906 00:40:22.637440 RX Vref 0 -> 0, step: 1
907 00:40:22.637493
908 00:40:22.637545 RX Delay -130 -> 252, step: 16
909 00:40:22.637599 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
910 00:40:22.637652 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
911 00:40:22.637705 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
912 00:40:22.637758 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
913 00:40:22.637811 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
914 00:40:22.637873 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
915 00:40:22.637927 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
916 00:40:22.637980 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
917 00:40:22.638032 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
918 00:40:22.638085 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
919 00:40:22.638138 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
920 00:40:22.638190 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
921 00:40:22.638243 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
922 00:40:22.638295 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
923 00:40:22.638348 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
924 00:40:22.638401 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
925 00:40:22.638453 ==
926 00:40:22.638506 Dram Type= 6, Freq= 0, CH_0, rank 0
927 00:40:22.638559 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
928 00:40:22.638612 ==
929 00:40:22.638664 DQS Delay:
930 00:40:22.638716 DQS0 = 0, DQS1 = 0
931 00:40:22.638769 DQM Delay:
932 00:40:22.638821 DQM0 = 88, DQM1 = 75
933 00:40:22.638873 DQ Delay:
934 00:40:22.638925 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
935 00:40:22.638978 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =93
936 00:40:22.639030 DQ8 =69, DQ9 =53, DQ10 =69, DQ11 =69
937 00:40:22.639082 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
938 00:40:22.639134
939 00:40:22.639190
940 00:40:22.639243 ==
941 00:40:22.639295 Dram Type= 6, Freq= 0, CH_0, rank 0
942 00:40:22.639347 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
943 00:40:22.639400 ==
944 00:40:22.639452
945 00:40:22.639503
946 00:40:22.639555 TX Vref Scan disable
947 00:40:22.639612 == TX Byte 0 ==
948 00:40:22.639689 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
949 00:40:22.639760 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
950 00:40:22.639814 == TX Byte 1 ==
951 00:40:22.639867 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
952 00:40:22.639957 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
953 00:40:22.640010 ==
954 00:40:22.640063 Dram Type= 6, Freq= 0, CH_0, rank 0
955 00:40:22.640115 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
956 00:40:22.640168 ==
957 00:40:22.640220 TX Vref=22, minBit 0, minWin=27, winSum=439
958 00:40:22.640273 TX Vref=24, minBit 1, minWin=27, winSum=441
959 00:40:22.640529 TX Vref=26, minBit 1, minWin=27, winSum=447
960 00:40:22.640590 TX Vref=28, minBit 1, minWin=27, winSum=447
961 00:40:22.640645 TX Vref=30, minBit 1, minWin=27, winSum=447
962 00:40:22.640699 TX Vref=32, minBit 2, minWin=27, winSum=446
963 00:40:22.640752 [TxChooseVref] Worse bit 1, Min win 27, Win sum 447, Final Vref 26
964 00:40:22.640806
965 00:40:22.640859 Final TX Range 1 Vref 26
966 00:40:22.640912
967 00:40:22.640964 ==
968 00:40:22.641017 Dram Type= 6, Freq= 0, CH_0, rank 0
969 00:40:22.641070 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
970 00:40:22.641123 ==
971 00:40:22.641175
972 00:40:22.641226
973 00:40:22.641305 TX Vref Scan disable
974 00:40:22.641372 == TX Byte 0 ==
975 00:40:22.641424 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
976 00:40:22.641478 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
977 00:40:22.641530 == TX Byte 1 ==
978 00:40:22.641582 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
979 00:40:22.641635 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
980 00:40:22.641688
981 00:40:22.641740 [DATLAT]
982 00:40:22.641792 Freq=800, CH0 RK0
983 00:40:22.641846
984 00:40:22.641898 DATLAT Default: 0xa
985 00:40:22.641951 0, 0xFFFF, sum = 0
986 00:40:22.642004 1, 0xFFFF, sum = 0
987 00:40:22.642058 2, 0xFFFF, sum = 0
988 00:40:22.642111 3, 0xFFFF, sum = 0
989 00:40:22.642165 4, 0xFFFF, sum = 0
990 00:40:22.642218 5, 0xFFFF, sum = 0
991 00:40:22.642271 6, 0xFFFF, sum = 0
992 00:40:22.642325 7, 0xFFFF, sum = 0
993 00:40:22.642379 8, 0xFFFF, sum = 0
994 00:40:22.642432 9, 0x0, sum = 1
995 00:40:22.642485 10, 0x0, sum = 2
996 00:40:22.642539 11, 0x0, sum = 3
997 00:40:22.642592 12, 0x0, sum = 4
998 00:40:22.642646 best_step = 10
999 00:40:22.642698
1000 00:40:22.642752 ==
1001 00:40:22.642805 Dram Type= 6, Freq= 0, CH_0, rank 0
1002 00:40:22.642857 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1003 00:40:22.642910 ==
1004 00:40:22.642962 RX Vref Scan: 1
1005 00:40:22.643014
1006 00:40:22.643067 Set Vref Range= 32 -> 127
1007 00:40:22.643119
1008 00:40:22.643171 RX Vref 32 -> 127, step: 1
1009 00:40:22.643223
1010 00:40:22.643275 RX Delay -111 -> 252, step: 8
1011 00:40:22.643328
1012 00:40:22.643379 Set Vref, RX VrefLevel [Byte0]: 32
1013 00:40:22.643432 [Byte1]: 32
1014 00:40:22.643484
1015 00:40:22.643536 Set Vref, RX VrefLevel [Byte0]: 33
1016 00:40:22.643588 [Byte1]: 33
1017 00:40:22.643640
1018 00:40:22.643693 Set Vref, RX VrefLevel [Byte0]: 34
1019 00:40:22.643746 [Byte1]: 34
1020 00:40:22.643799
1021 00:40:22.643851 Set Vref, RX VrefLevel [Byte0]: 35
1022 00:40:22.643904 [Byte1]: 35
1023 00:40:22.643957
1024 00:40:22.644010 Set Vref, RX VrefLevel [Byte0]: 36
1025 00:40:22.644069 [Byte1]: 36
1026 00:40:22.644124
1027 00:40:22.644177 Set Vref, RX VrefLevel [Byte0]: 37
1028 00:40:22.644230 [Byte1]: 37
1029 00:40:22.644282
1030 00:40:22.644334 Set Vref, RX VrefLevel [Byte0]: 38
1031 00:40:22.644386 [Byte1]: 38
1032 00:40:22.644445
1033 00:40:22.644498 Set Vref, RX VrefLevel [Byte0]: 39
1034 00:40:22.644551 [Byte1]: 39
1035 00:40:22.644611
1036 00:40:22.644699 Set Vref, RX VrefLevel [Byte0]: 40
1037 00:40:22.644755 [Byte1]: 40
1038 00:40:22.644808
1039 00:40:22.644876 Set Vref, RX VrefLevel [Byte0]: 41
1040 00:40:22.644941 [Byte1]: 41
1041 00:40:22.644993
1042 00:40:22.645044 Set Vref, RX VrefLevel [Byte0]: 42
1043 00:40:22.645137 [Byte1]: 42
1044 00:40:22.645220
1045 00:40:22.645326 Set Vref, RX VrefLevel [Byte0]: 43
1046 00:40:22.645381 [Byte1]: 43
1047 00:40:22.645464
1048 00:40:22.645546 Set Vref, RX VrefLevel [Byte0]: 44
1049 00:40:22.645600 [Byte1]: 44
1050 00:40:22.645682
1051 00:40:22.645735 Set Vref, RX VrefLevel [Byte0]: 45
1052 00:40:22.645788 [Byte1]: 45
1053 00:40:22.645841
1054 00:40:22.645893 Set Vref, RX VrefLevel [Byte0]: 46
1055 00:40:22.645946 [Byte1]: 46
1056 00:40:22.645999
1057 00:40:22.646051 Set Vref, RX VrefLevel [Byte0]: 47
1058 00:40:22.646103 [Byte1]: 47
1059 00:40:22.646156
1060 00:40:22.646209 Set Vref, RX VrefLevel [Byte0]: 48
1061 00:40:22.646262 [Byte1]: 48
1062 00:40:22.646314
1063 00:40:22.646366 Set Vref, RX VrefLevel [Byte0]: 49
1064 00:40:22.646419 [Byte1]: 49
1065 00:40:22.646471
1066 00:40:22.646524 Set Vref, RX VrefLevel [Byte0]: 50
1067 00:40:22.646576 [Byte1]: 50
1068 00:40:22.646629
1069 00:40:22.646681 Set Vref, RX VrefLevel [Byte0]: 51
1070 00:40:22.646734 [Byte1]: 51
1071 00:40:22.646786
1072 00:40:22.646839 Set Vref, RX VrefLevel [Byte0]: 52
1073 00:40:22.646891 [Byte1]: 52
1074 00:40:22.646943
1075 00:40:22.646996 Set Vref, RX VrefLevel [Byte0]: 53
1076 00:40:22.647048 [Byte1]: 53
1077 00:40:22.647114
1078 00:40:22.647169 Set Vref, RX VrefLevel [Byte0]: 54
1079 00:40:22.647236 [Byte1]: 54
1080 00:40:22.647287
1081 00:40:22.647338 Set Vref, RX VrefLevel [Byte0]: 55
1082 00:40:22.647390 [Byte1]: 55
1083 00:40:22.647442
1084 00:40:22.647493 Set Vref, RX VrefLevel [Byte0]: 56
1085 00:40:22.647545 [Byte1]: 56
1086 00:40:22.647597
1087 00:40:22.647648 Set Vref, RX VrefLevel [Byte0]: 57
1088 00:40:22.647700 [Byte1]: 57
1089 00:40:22.647752
1090 00:40:22.647803 Set Vref, RX VrefLevel [Byte0]: 58
1091 00:40:22.647855 [Byte1]: 58
1092 00:40:22.647906
1093 00:40:22.647957 Set Vref, RX VrefLevel [Byte0]: 59
1094 00:40:22.648008 [Byte1]: 59
1095 00:40:22.648060
1096 00:40:22.648111 Set Vref, RX VrefLevel [Byte0]: 60
1097 00:40:22.648163 [Byte1]: 60
1098 00:40:22.648214
1099 00:40:22.648265 Set Vref, RX VrefLevel [Byte0]: 61
1100 00:40:22.648316 [Byte1]: 61
1101 00:40:22.648368
1102 00:40:22.648452 Set Vref, RX VrefLevel [Byte0]: 62
1103 00:40:22.648535 [Byte1]: 62
1104 00:40:22.648590
1105 00:40:22.648643 Set Vref, RX VrefLevel [Byte0]: 63
1106 00:40:22.648695 [Byte1]: 63
1107 00:40:22.648747
1108 00:40:22.648799 Set Vref, RX VrefLevel [Byte0]: 64
1109 00:40:22.648851 [Byte1]: 64
1110 00:40:22.648903
1111 00:40:22.648955 Set Vref, RX VrefLevel [Byte0]: 65
1112 00:40:22.649007 [Byte1]: 65
1113 00:40:22.649060
1114 00:40:22.649153 Set Vref, RX VrefLevel [Byte0]: 66
1115 00:40:22.649235 [Byte1]: 66
1116 00:40:22.649337
1117 00:40:22.649390 Set Vref, RX VrefLevel [Byte0]: 67
1118 00:40:22.649443 [Byte1]: 67
1119 00:40:22.649494
1120 00:40:22.649545 Set Vref, RX VrefLevel [Byte0]: 68
1121 00:40:22.649597 [Byte1]: 68
1122 00:40:22.649647
1123 00:40:22.649699 Set Vref, RX VrefLevel [Byte0]: 69
1124 00:40:22.649750 [Byte1]: 69
1125 00:40:22.649802
1126 00:40:22.649854 Set Vref, RX VrefLevel [Byte0]: 70
1127 00:40:22.650166 [Byte1]: 70
1128 00:40:22.650245
1129 00:40:22.650300 Set Vref, RX VrefLevel [Byte0]: 71
1130 00:40:22.650404 [Byte1]: 71
1131 00:40:22.650478
1132 00:40:22.650551 Set Vref, RX VrefLevel [Byte0]: 72
1133 00:40:22.650635 [Byte1]: 72
1134 00:40:22.650718
1135 00:40:22.650785 Set Vref, RX VrefLevel [Byte0]: 73
1136 00:40:22.650838 [Byte1]: 73
1137 00:40:22.650889
1138 00:40:22.650940 Final RX Vref Byte 0 = 57 to rank0
1139 00:40:22.650993 Final RX Vref Byte 1 = 59 to rank0
1140 00:40:22.651053 Final RX Vref Byte 0 = 57 to rank1
1141 00:40:22.651153 Final RX Vref Byte 1 = 59 to rank1==
1142 00:40:22.651251 Dram Type= 6, Freq= 0, CH_0, rank 0
1143 00:40:22.651305 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1144 00:40:22.651358 ==
1145 00:40:22.651412 DQS Delay:
1146 00:40:22.651464 DQS0 = 0, DQS1 = 0
1147 00:40:22.651517 DQM Delay:
1148 00:40:22.651569 DQM0 = 87, DQM1 = 76
1149 00:40:22.651621 DQ Delay:
1150 00:40:22.651673 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =84
1151 00:40:22.651725 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1152 00:40:22.651777 DQ8 =68, DQ9 =60, DQ10 =76, DQ11 =72
1153 00:40:22.651828 DQ12 =84, DQ13 =80, DQ14 =84, DQ15 =84
1154 00:40:22.651880
1155 00:40:22.651932
1156 00:40:22.651984 [DQSOSCAuto] RK0, (LSB)MR18= 0x3730, (MSB)MR19= 0x606, tDQSOscB0 = 397 ps tDQSOscB1 = 395 ps
1157 00:40:22.652037 CH0 RK0: MR19=606, MR18=3730
1158 00:40:22.652090 CH0_RK0: MR19=0x606, MR18=0x3730, DQSOSC=395, MR23=63, INC=94, DEC=63
1159 00:40:22.652142
1160 00:40:22.652193 ----->DramcWriteLeveling(PI) begin...
1161 00:40:22.652246 ==
1162 00:40:22.652298 Dram Type= 6, Freq= 0, CH_0, rank 1
1163 00:40:22.652350 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1164 00:40:22.652403 ==
1165 00:40:22.652455 Write leveling (Byte 0): 30 => 30
1166 00:40:22.652506 Write leveling (Byte 1): 30 => 30
1167 00:40:22.652558 DramcWriteLeveling(PI) end<-----
1168 00:40:22.652609
1169 00:40:22.652661 ==
1170 00:40:22.652712 Dram Type= 6, Freq= 0, CH_0, rank 1
1171 00:40:22.652764 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1172 00:40:22.652817 ==
1173 00:40:22.652868 [Gating] SW mode calibration
1174 00:40:22.652921 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1175 00:40:22.652974 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1176 00:40:22.653026 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1177 00:40:22.653078 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1178 00:40:22.653130 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1179 00:40:22.653182 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 00:40:22.653309 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 00:40:22.653392 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1182 00:40:22.653487 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1183 00:40:22.653540 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1184 00:40:22.653593 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1185 00:40:22.653646 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 00:40:22.653698 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 00:40:22.653749 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 00:40:22.653801 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 00:40:22.653853 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 00:40:22.653905 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 00:40:22.653982 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 00:40:22.654048 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1193 00:40:22.654099 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1194 00:40:22.654152 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1195 00:40:22.654203 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1196 00:40:22.654256 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1197 00:40:22.654307 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1198 00:40:22.654358 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1199 00:40:22.654410 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1200 00:40:22.654461 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1201 00:40:22.654513 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1202 00:40:22.654564 0 9 8 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)
1203 00:40:22.654616 0 9 12 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
1204 00:40:22.654667 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1205 00:40:22.654718 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1206 00:40:22.654770 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1207 00:40:22.654821 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1208 00:40:22.654873 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1209 00:40:22.654924 0 10 4 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
1210 00:40:22.654975 0 10 8 | B1->B0 | 3030 2323 | 1 0 | (1 0) (0 0)
1211 00:40:22.655027 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1212 00:40:22.655079 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1213 00:40:22.655131 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1214 00:40:22.655183 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1215 00:40:22.655242 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1216 00:40:22.655294 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1217 00:40:22.655346 0 11 4 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
1218 00:40:22.655398 0 11 8 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
1219 00:40:22.655450 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1220 00:40:22.655501 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1221 00:40:22.655552 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1222 00:40:22.655609 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1223 00:40:22.655661 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1224 00:40:22.655713 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1225 00:40:22.655764 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1226 00:40:22.655816 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1227 00:40:22.655867 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1228 00:40:22.656135 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1229 00:40:22.656199 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1230 00:40:22.656254 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1231 00:40:22.656308 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1232 00:40:22.656361 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1233 00:40:22.656414 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1234 00:40:22.656468 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1235 00:40:22.656521 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1236 00:40:22.656574 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1237 00:40:22.656627 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1238 00:40:22.656680 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1239 00:40:22.656734 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1240 00:40:22.656787 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1241 00:40:22.656839 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1242 00:40:22.656892 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1243 00:40:22.656945 Total UI for P1: 0, mck2ui 16
1244 00:40:22.656999 best dqsien dly found for B0: ( 0, 14, 4)
1245 00:40:22.657079 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1246 00:40:22.657162 Total UI for P1: 0, mck2ui 16
1247 00:40:22.657250 best dqsien dly found for B1: ( 0, 14, 8)
1248 00:40:22.657358 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1249 00:40:22.657468 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1250 00:40:22.657558
1251 00:40:22.657653 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1252 00:40:22.657740 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1253 00:40:22.657822 [Gating] SW calibration Done
1254 00:40:22.657903 ==
1255 00:40:22.657986 Dram Type= 6, Freq= 0, CH_0, rank 1
1256 00:40:22.658067 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1257 00:40:22.658149 ==
1258 00:40:22.658230 RX Vref Scan: 0
1259 00:40:22.658310
1260 00:40:22.658390 RX Vref 0 -> 0, step: 1
1261 00:40:22.658470
1262 00:40:22.658550 RX Delay -130 -> 252, step: 16
1263 00:40:22.658632 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1264 00:40:22.658713 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1265 00:40:22.658794 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1266 00:40:22.658875 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1267 00:40:22.658956 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1268 00:40:22.659037 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
1269 00:40:22.659118 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1270 00:40:22.659199 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1271 00:40:22.659279 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1272 00:40:22.659360 iDelay=206, Bit 9, Center 61 (-50 ~ 173) 224
1273 00:40:22.659442 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
1274 00:40:22.659529 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1275 00:40:22.659644 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1276 00:40:22.659725 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1277 00:40:22.659806 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1278 00:40:22.659887 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1279 00:40:22.659967 ==
1280 00:40:22.660048 Dram Type= 6, Freq= 0, CH_0, rank 1
1281 00:40:22.660129 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1282 00:40:22.660210 ==
1283 00:40:22.660290 DQS Delay:
1284 00:40:22.660375 DQS0 = 0, DQS1 = 0
1285 00:40:22.660456 DQM Delay:
1286 00:40:22.660536 DQM0 = 86, DQM1 = 77
1287 00:40:22.660616 DQ Delay:
1288 00:40:22.660696 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =85
1289 00:40:22.660777 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =93
1290 00:40:22.660858 DQ8 =69, DQ9 =61, DQ10 =77, DQ11 =69
1291 00:40:22.660931 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1292 00:40:22.661033
1293 00:40:22.661129
1294 00:40:22.661236 ==
1295 00:40:22.661338 Dram Type= 6, Freq= 0, CH_0, rank 1
1296 00:40:22.661408 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1297 00:40:22.661480 ==
1298 00:40:22.661581
1299 00:40:22.661673
1300 00:40:22.661822 TX Vref Scan disable
1301 00:40:22.661894 == TX Byte 0 ==
1302 00:40:22.661948 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1303 00:40:22.662001 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1304 00:40:22.662054 == TX Byte 1 ==
1305 00:40:22.662106 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1306 00:40:22.662158 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1307 00:40:22.662210 ==
1308 00:40:22.662263 Dram Type= 6, Freq= 0, CH_0, rank 1
1309 00:40:22.662316 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1310 00:40:22.662368 ==
1311 00:40:22.662420 TX Vref=22, minBit 0, minWin=27, winSum=440
1312 00:40:22.662472 TX Vref=24, minBit 0, minWin=27, winSum=445
1313 00:40:22.662524 TX Vref=26, minBit 2, minWin=27, winSum=449
1314 00:40:22.662576 TX Vref=28, minBit 3, minWin=27, winSum=450
1315 00:40:22.662628 TX Vref=30, minBit 7, minWin=27, winSum=452
1316 00:40:22.662680 TX Vref=32, minBit 4, minWin=27, winSum=448
1317 00:40:22.662732 [TxChooseVref] Worse bit 7, Min win 27, Win sum 452, Final Vref 30
1318 00:40:22.662785
1319 00:40:22.662836 Final TX Range 1 Vref 30
1320 00:40:22.662888
1321 00:40:22.662939 ==
1322 00:40:22.662990 Dram Type= 6, Freq= 0, CH_0, rank 1
1323 00:40:22.663042 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1324 00:40:22.663095 ==
1325 00:40:22.663147
1326 00:40:22.663197
1327 00:40:22.663248 TX Vref Scan disable
1328 00:40:22.663300 == TX Byte 0 ==
1329 00:40:22.663352 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1330 00:40:22.663404 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1331 00:40:22.663456 == TX Byte 1 ==
1332 00:40:22.663507 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1333 00:40:22.663558 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1334 00:40:22.663610
1335 00:40:22.663662 [DATLAT]
1336 00:40:22.663735 Freq=800, CH0 RK1
1337 00:40:22.663802
1338 00:40:22.663853 DATLAT Default: 0xa
1339 00:40:22.663905 0, 0xFFFF, sum = 0
1340 00:40:22.663958 1, 0xFFFF, sum = 0
1341 00:40:22.664010 2, 0xFFFF, sum = 0
1342 00:40:22.664063 3, 0xFFFF, sum = 0
1343 00:40:22.664115 4, 0xFFFF, sum = 0
1344 00:40:22.664167 5, 0xFFFF, sum = 0
1345 00:40:22.664218 6, 0xFFFF, sum = 0
1346 00:40:22.664271 7, 0xFFFF, sum = 0
1347 00:40:22.664323 8, 0xFFFF, sum = 0
1348 00:40:22.664375 9, 0x0, sum = 1
1349 00:40:22.664427 10, 0x0, sum = 2
1350 00:40:22.664480 11, 0x0, sum = 3
1351 00:40:22.664531 12, 0x0, sum = 4
1352 00:40:22.664583 best_step = 10
1353 00:40:22.664634
1354 00:40:22.664685 ==
1355 00:40:22.664736 Dram Type= 6, Freq= 0, CH_0, rank 1
1356 00:40:22.664787 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1357 00:40:22.664839 ==
1358 00:40:22.664890 RX Vref Scan: 0
1359 00:40:22.664941
1360 00:40:22.664993 RX Vref 0 -> 0, step: 1
1361 00:40:22.665044
1362 00:40:22.665095 RX Delay -95 -> 252, step: 8
1363 00:40:22.665146 iDelay=209, Bit 0, Center 84 (-23 ~ 192) 216
1364 00:40:22.665418 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1365 00:40:22.665480 iDelay=209, Bit 2, Center 80 (-31 ~ 192) 224
1366 00:40:22.665534 iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224
1367 00:40:22.665587 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1368 00:40:22.665640 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1369 00:40:22.665692 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1370 00:40:22.665745 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1371 00:40:22.665798 iDelay=209, Bit 8, Center 64 (-47 ~ 176) 224
1372 00:40:22.665851 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
1373 00:40:22.665905 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1374 00:40:22.665958 iDelay=209, Bit 11, Center 72 (-39 ~ 184) 224
1375 00:40:22.666010 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
1376 00:40:22.666062 iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224
1377 00:40:22.666115 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1378 00:40:22.666166 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1379 00:40:22.666227 ==
1380 00:40:22.666317 Dram Type= 6, Freq= 0, CH_0, rank 1
1381 00:40:22.666406 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1382 00:40:22.666504 ==
1383 00:40:22.666578 DQS Delay:
1384 00:40:22.666631 DQS0 = 0, DQS1 = 0
1385 00:40:22.666684 DQM Delay:
1386 00:40:22.666735 DQM0 = 86, DQM1 = 76
1387 00:40:22.666787 DQ Delay:
1388 00:40:22.666839 DQ0 =84, DQ1 =88, DQ2 =80, DQ3 =80
1389 00:40:22.666890 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1390 00:40:22.666942 DQ8 =64, DQ9 =64, DQ10 =80, DQ11 =72
1391 00:40:22.666993 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =84
1392 00:40:22.667045
1393 00:40:22.667095
1394 00:40:22.667147 [DQSOSCAuto] RK1, (LSB)MR18= 0x2b28, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 398 ps
1395 00:40:22.667239 CH0 RK1: MR19=606, MR18=2B28
1396 00:40:22.667291 CH0_RK1: MR19=0x606, MR18=0x2B28, DQSOSC=398, MR23=63, INC=93, DEC=62
1397 00:40:22.667343 [RxdqsGatingPostProcess] freq 800
1398 00:40:22.667394 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1399 00:40:22.667445 Pre-setting of DQS Precalculation
1400 00:40:22.667496 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1401 00:40:22.667547 ==
1402 00:40:22.667598 Dram Type= 6, Freq= 0, CH_1, rank 0
1403 00:40:22.667650 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1404 00:40:22.667701 ==
1405 00:40:22.667753 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1406 00:40:22.667805 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1407 00:40:22.667857 [CA 0] Center 37 (6~68) winsize 63
1408 00:40:22.667908 [CA 1] Center 37 (6~68) winsize 63
1409 00:40:22.667965 [CA 2] Center 35 (5~65) winsize 61
1410 00:40:22.668024 [CA 3] Center 34 (4~65) winsize 62
1411 00:40:22.668076 [CA 4] Center 34 (4~65) winsize 62
1412 00:40:22.668128 [CA 5] Center 33 (3~64) winsize 62
1413 00:40:22.668179
1414 00:40:22.668230 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1415 00:40:22.668282
1416 00:40:22.668333 [CATrainingPosCal] consider 1 rank data
1417 00:40:22.668384 u2DelayCellTimex100 = 270/100 ps
1418 00:40:22.668436 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
1419 00:40:22.668487 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1420 00:40:22.668538 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
1421 00:40:22.668589 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1422 00:40:22.668640 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1423 00:40:22.668691 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1424 00:40:22.668742
1425 00:40:22.668793 CA PerBit enable=1, Macro0, CA PI delay=33
1426 00:40:22.668844
1427 00:40:22.668901 [CBTSetCACLKResult] CA Dly = 33
1428 00:40:22.668987 CS Dly: 4 (0~35)
1429 00:40:22.669067 ==
1430 00:40:22.669148 Dram Type= 6, Freq= 0, CH_1, rank 1
1431 00:40:22.669228 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1432 00:40:22.669338 ==
1433 00:40:22.669391 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1434 00:40:22.669444 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1435 00:40:22.669495 [CA 0] Center 36 (6~67) winsize 62
1436 00:40:22.669547 [CA 1] Center 36 (6~67) winsize 62
1437 00:40:22.669598 [CA 2] Center 34 (4~65) winsize 62
1438 00:40:22.669649 [CA 3] Center 34 (3~65) winsize 63
1439 00:40:22.669700 [CA 4] Center 34 (3~65) winsize 63
1440 00:40:22.669752 [CA 5] Center 34 (3~65) winsize 63
1441 00:40:22.669803
1442 00:40:22.669854 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1443 00:40:22.669906
1444 00:40:22.669959 [CATrainingPosCal] consider 2 rank data
1445 00:40:22.670018 u2DelayCellTimex100 = 270/100 ps
1446 00:40:22.670075 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1447 00:40:22.670127 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1448 00:40:22.670179 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
1449 00:40:22.670230 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1450 00:40:22.670283 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1451 00:40:22.670334 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1452 00:40:22.670384
1453 00:40:22.670436 CA PerBit enable=1, Macro0, CA PI delay=33
1454 00:40:22.670493
1455 00:40:22.670578 [CBTSetCACLKResult] CA Dly = 33
1456 00:40:22.670629 CS Dly: 5 (0~37)
1457 00:40:22.670680
1458 00:40:22.670732 ----->DramcWriteLeveling(PI) begin...
1459 00:40:22.670784 ==
1460 00:40:22.670835 Dram Type= 6, Freq= 0, CH_1, rank 0
1461 00:40:22.670886 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1462 00:40:22.670939 ==
1463 00:40:22.670990 Write leveling (Byte 0): 26 => 26
1464 00:40:22.671041 Write leveling (Byte 1): 27 => 27
1465 00:40:22.671092 DramcWriteLeveling(PI) end<-----
1466 00:40:22.671144
1467 00:40:22.671194 ==
1468 00:40:22.671245 Dram Type= 6, Freq= 0, CH_1, rank 0
1469 00:40:22.671296 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1470 00:40:22.671347 ==
1471 00:40:22.671398 [Gating] SW mode calibration
1472 00:40:22.671449 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1473 00:40:22.671502 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1474 00:40:22.671558 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1475 00:40:22.671633 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1476 00:40:22.671727 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1477 00:40:22.671818 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 00:40:22.671911 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1479 00:40:22.671982 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1480 00:40:22.672034 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1481 00:40:22.672289 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1482 00:40:22.672348 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1483 00:40:22.672401 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 00:40:22.672454 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 00:40:22.672506 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 00:40:22.672558 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 00:40:22.672609 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 00:40:22.672662 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 00:40:22.672714 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 00:40:22.672765 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1491 00:40:22.672817 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1492 00:40:22.672868 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 00:40:22.672919 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1494 00:40:22.672970 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1495 00:40:22.673021 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1496 00:40:22.673072 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1497 00:40:22.673123 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1498 00:40:22.673173 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1499 00:40:22.673225 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1500 00:40:22.673312 0 9 8 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 1)
1501 00:40:22.673409 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1502 00:40:22.673508 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1503 00:40:22.673565 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1504 00:40:22.673616 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1505 00:40:22.673668 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1506 00:40:22.673719 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1507 00:40:22.673770 0 10 4 | B1->B0 | 3131 2f2f | 0 0 | (0 0) (0 0)
1508 00:40:22.673821 0 10 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1509 00:40:22.673872 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1510 00:40:22.673924 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1511 00:40:22.673975 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1512 00:40:22.674026 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1513 00:40:22.674077 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1514 00:40:22.674129 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1515 00:40:22.674180 0 11 4 | B1->B0 | 2626 3030 | 0 0 | (0 0) (0 0)
1516 00:40:22.674231 0 11 8 | B1->B0 | 3b3b 4646 | 1 0 | (0 0) (0 0)
1517 00:40:22.674283 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1518 00:40:22.674334 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1519 00:40:22.674385 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1520 00:40:22.674437 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1521 00:40:22.674489 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1522 00:40:22.674540 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1523 00:40:22.674592 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1524 00:40:22.674643 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1525 00:40:22.674694 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1526 00:40:22.674745 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1527 00:40:22.674796 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1528 00:40:22.674847 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1529 00:40:22.674898 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1530 00:40:22.674949 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1531 00:40:22.675000 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1532 00:40:22.675051 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1533 00:40:22.675102 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1534 00:40:22.675153 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1535 00:40:22.675207 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1536 00:40:22.675275 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1537 00:40:22.675329 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1538 00:40:22.675381 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1539 00:40:22.675432 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1540 00:40:22.675497 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1541 00:40:22.675559 Total UI for P1: 0, mck2ui 16
1542 00:40:22.675612 best dqsien dly found for B0: ( 0, 14, 4)
1543 00:40:22.675663 Total UI for P1: 0, mck2ui 16
1544 00:40:22.675715 best dqsien dly found for B1: ( 0, 14, 4)
1545 00:40:22.675766 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1546 00:40:22.675817 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1547 00:40:22.675868
1548 00:40:22.675920 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1549 00:40:22.675972 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1550 00:40:22.676022 [Gating] SW calibration Done
1551 00:40:22.676073 ==
1552 00:40:22.676125 Dram Type= 6, Freq= 0, CH_1, rank 0
1553 00:40:22.676177 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1554 00:40:22.676229 ==
1555 00:40:22.676280 RX Vref Scan: 0
1556 00:40:22.676331
1557 00:40:22.676383 RX Vref 0 -> 0, step: 1
1558 00:40:22.676434
1559 00:40:22.676485 RX Delay -130 -> 252, step: 16
1560 00:40:22.676536 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1561 00:40:22.676588 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1562 00:40:22.676642 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1563 00:40:22.676704 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1564 00:40:22.676802 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1565 00:40:22.676894 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1566 00:40:22.676989 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1567 00:40:22.677073 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1568 00:40:22.677160 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1569 00:40:22.677243 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1570 00:40:22.677343 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1571 00:40:22.677615 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1572 00:40:22.677704 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1573 00:40:22.677764 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1574 00:40:22.677819 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1575 00:40:22.677873 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1576 00:40:22.677925 ==
1577 00:40:22.677978 Dram Type= 6, Freq= 0, CH_1, rank 0
1578 00:40:22.678030 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1579 00:40:22.678083 ==
1580 00:40:22.678134 DQS Delay:
1581 00:40:22.678185 DQS0 = 0, DQS1 = 0
1582 00:40:22.678237 DQM Delay:
1583 00:40:22.678288 DQM0 = 88, DQM1 = 81
1584 00:40:22.678340 DQ Delay:
1585 00:40:22.678391 DQ0 =93, DQ1 =85, DQ2 =69, DQ3 =85
1586 00:40:22.678443 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1587 00:40:22.678494 DQ8 =77, DQ9 =77, DQ10 =77, DQ11 =77
1588 00:40:22.678545 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1589 00:40:22.678597
1590 00:40:22.678648
1591 00:40:22.678698 ==
1592 00:40:22.678749 Dram Type= 6, Freq= 0, CH_1, rank 0
1593 00:40:22.678801 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1594 00:40:22.678853 ==
1595 00:40:22.678904
1596 00:40:22.678954
1597 00:40:22.679006 TX Vref Scan disable
1598 00:40:22.679058 == TX Byte 0 ==
1599 00:40:22.679109 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1600 00:40:22.679161 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1601 00:40:22.679212 == TX Byte 1 ==
1602 00:40:22.679263 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1603 00:40:22.679314 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1604 00:40:22.679365 ==
1605 00:40:22.679415 Dram Type= 6, Freq= 0, CH_1, rank 0
1606 00:40:22.679466 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1607 00:40:22.679518 ==
1608 00:40:22.679569 TX Vref=22, minBit 4, minWin=27, winSum=447
1609 00:40:22.679620 TX Vref=24, minBit 4, minWin=27, winSum=448
1610 00:40:22.679672 TX Vref=26, minBit 1, minWin=27, winSum=453
1611 00:40:22.679726 TX Vref=28, minBit 4, minWin=27, winSum=454
1612 00:40:22.679777 TX Vref=30, minBit 0, minWin=28, winSum=456
1613 00:40:22.679829 TX Vref=32, minBit 5, minWin=27, winSum=450
1614 00:40:22.679880 [TxChooseVref] Worse bit 0, Min win 28, Win sum 456, Final Vref 30
1615 00:40:22.679933
1616 00:40:22.679994 Final TX Range 1 Vref 30
1617 00:40:22.680047
1618 00:40:22.680098 ==
1619 00:40:22.680149 Dram Type= 6, Freq= 0, CH_1, rank 0
1620 00:40:22.680201 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1621 00:40:22.680253 ==
1622 00:40:22.680304
1623 00:40:22.680354
1624 00:40:22.680405 TX Vref Scan disable
1625 00:40:22.680456 == TX Byte 0 ==
1626 00:40:22.680507 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1627 00:40:22.680559 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1628 00:40:22.680610 == TX Byte 1 ==
1629 00:40:22.680661 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1630 00:40:22.680713 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1631 00:40:22.680764
1632 00:40:22.680814 [DATLAT]
1633 00:40:22.680865 Freq=800, CH1 RK0
1634 00:40:22.680916
1635 00:40:22.680967 DATLAT Default: 0xa
1636 00:40:22.681018 0, 0xFFFF, sum = 0
1637 00:40:22.681071 1, 0xFFFF, sum = 0
1638 00:40:22.681124 2, 0xFFFF, sum = 0
1639 00:40:22.681176 3, 0xFFFF, sum = 0
1640 00:40:22.681228 4, 0xFFFF, sum = 0
1641 00:40:22.681313 5, 0xFFFF, sum = 0
1642 00:40:22.681379 6, 0xFFFF, sum = 0
1643 00:40:22.681432 7, 0xFFFF, sum = 0
1644 00:40:22.681484 8, 0xFFFF, sum = 0
1645 00:40:22.681536 9, 0x0, sum = 1
1646 00:40:22.681588 10, 0x0, sum = 2
1647 00:40:22.681641 11, 0x0, sum = 3
1648 00:40:22.681692 12, 0x0, sum = 4
1649 00:40:22.681745 best_step = 10
1650 00:40:22.681796
1651 00:40:22.681846 ==
1652 00:40:22.681897 Dram Type= 6, Freq= 0, CH_1, rank 0
1653 00:40:22.681949 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1654 00:40:22.682000 ==
1655 00:40:22.682052 RX Vref Scan: 1
1656 00:40:22.682103
1657 00:40:22.682154 Set Vref Range= 32 -> 127
1658 00:40:22.682206
1659 00:40:22.682257 RX Vref 32 -> 127, step: 1
1660 00:40:22.682307
1661 00:40:22.682358 RX Delay -95 -> 252, step: 8
1662 00:40:22.682414
1663 00:40:22.682484 Set Vref, RX VrefLevel [Byte0]: 32
1664 00:40:22.682583 [Byte1]: 32
1665 00:40:22.682678
1666 00:40:22.682779 Set Vref, RX VrefLevel [Byte0]: 33
1667 00:40:22.682833 [Byte1]: 33
1668 00:40:22.682886
1669 00:40:22.682938 Set Vref, RX VrefLevel [Byte0]: 34
1670 00:40:22.682989 [Byte1]: 34
1671 00:40:22.683040
1672 00:40:22.683092 Set Vref, RX VrefLevel [Byte0]: 35
1673 00:40:22.683143 [Byte1]: 35
1674 00:40:22.683195
1675 00:40:22.683245 Set Vref, RX VrefLevel [Byte0]: 36
1676 00:40:22.683297 [Byte1]: 36
1677 00:40:22.683348
1678 00:40:22.683399 Set Vref, RX VrefLevel [Byte0]: 37
1679 00:40:22.683451 [Byte1]: 37
1680 00:40:22.683501
1681 00:40:22.683552 Set Vref, RX VrefLevel [Byte0]: 38
1682 00:40:22.683602 [Byte1]: 38
1683 00:40:22.683654
1684 00:40:22.683705 Set Vref, RX VrefLevel [Byte0]: 39
1685 00:40:22.683756 [Byte1]: 39
1686 00:40:22.683817
1687 00:40:22.683868 Set Vref, RX VrefLevel [Byte0]: 40
1688 00:40:22.683920 [Byte1]: 40
1689 00:40:22.683971
1690 00:40:22.684023 Set Vref, RX VrefLevel [Byte0]: 41
1691 00:40:22.684074 [Byte1]: 41
1692 00:40:22.684125
1693 00:40:22.684175 Set Vref, RX VrefLevel [Byte0]: 42
1694 00:40:22.684227 [Byte1]: 42
1695 00:40:22.684278
1696 00:40:22.684329 Set Vref, RX VrefLevel [Byte0]: 43
1697 00:40:22.684380 [Byte1]: 43
1698 00:40:22.684431
1699 00:40:22.684482 Set Vref, RX VrefLevel [Byte0]: 44
1700 00:40:22.684534 [Byte1]: 44
1701 00:40:22.684584
1702 00:40:22.684635 Set Vref, RX VrefLevel [Byte0]: 45
1703 00:40:22.684724 [Byte1]: 45
1704 00:40:22.684795
1705 00:40:22.684849 Set Vref, RX VrefLevel [Byte0]: 46
1706 00:40:22.684901 [Byte1]: 46
1707 00:40:22.684952
1708 00:40:22.685003 Set Vref, RX VrefLevel [Byte0]: 47
1709 00:40:22.685055 [Byte1]: 47
1710 00:40:22.685105
1711 00:40:22.685156 Set Vref, RX VrefLevel [Byte0]: 48
1712 00:40:22.685208 [Byte1]: 48
1713 00:40:22.685266
1714 00:40:22.685354 Set Vref, RX VrefLevel [Byte0]: 49
1715 00:40:22.685406 [Byte1]: 49
1716 00:40:22.685457
1717 00:40:22.685508 Set Vref, RX VrefLevel [Byte0]: 50
1718 00:40:22.685559 [Byte1]: 50
1719 00:40:22.685610
1720 00:40:22.685661 Set Vref, RX VrefLevel [Byte0]: 51
1721 00:40:22.685713 [Byte1]: 51
1722 00:40:22.685764
1723 00:40:22.685815 Set Vref, RX VrefLevel [Byte0]: 52
1724 00:40:22.685866 [Byte1]: 52
1725 00:40:22.685918
1726 00:40:22.685969 Set Vref, RX VrefLevel [Byte0]: 53
1727 00:40:22.686020 [Byte1]: 53
1728 00:40:22.686071
1729 00:40:22.686122 Set Vref, RX VrefLevel [Byte0]: 54
1730 00:40:22.686173 [Byte1]: 54
1731 00:40:22.686224
1732 00:40:22.686274 Set Vref, RX VrefLevel [Byte0]: 55
1733 00:40:22.686325 [Byte1]: 55
1734 00:40:22.686376
1735 00:40:22.686634 Set Vref, RX VrefLevel [Byte0]: 56
1736 00:40:22.686745 [Byte1]: 56
1737 00:40:22.686833
1738 00:40:22.686918 Set Vref, RX VrefLevel [Byte0]: 57
1739 00:40:22.686974 [Byte1]: 57
1740 00:40:22.687028
1741 00:40:22.687081 Set Vref, RX VrefLevel [Byte0]: 58
1742 00:40:22.687134 [Byte1]: 58
1743 00:40:22.687186
1744 00:40:22.687238 Set Vref, RX VrefLevel [Byte0]: 59
1745 00:40:22.687291 [Byte1]: 59
1746 00:40:22.687343
1747 00:40:22.687395 Set Vref, RX VrefLevel [Byte0]: 60
1748 00:40:22.687492 [Byte1]: 60
1749 00:40:22.687583
1750 00:40:22.687675 Set Vref, RX VrefLevel [Byte0]: 61
1751 00:40:22.687787 [Byte1]: 61
1752 00:40:22.687842
1753 00:40:22.687895 Set Vref, RX VrefLevel [Byte0]: 62
1754 00:40:22.687947 [Byte1]: 62
1755 00:40:22.687999
1756 00:40:22.688050 Set Vref, RX VrefLevel [Byte0]: 63
1757 00:40:22.688102 [Byte1]: 63
1758 00:40:22.688153
1759 00:40:22.688204 Set Vref, RX VrefLevel [Byte0]: 64
1760 00:40:22.688256 [Byte1]: 64
1761 00:40:22.688307
1762 00:40:22.688357 Set Vref, RX VrefLevel [Byte0]: 65
1763 00:40:22.688408 [Byte1]: 65
1764 00:40:22.688459
1765 00:40:22.688510 Set Vref, RX VrefLevel [Byte0]: 66
1766 00:40:22.688561 [Byte1]: 66
1767 00:40:22.688612
1768 00:40:22.688663 Set Vref, RX VrefLevel [Byte0]: 67
1769 00:40:22.688714 [Byte1]: 67
1770 00:40:22.688765
1771 00:40:22.688816 Set Vref, RX VrefLevel [Byte0]: 68
1772 00:40:22.688867 [Byte1]: 68
1773 00:40:22.688918
1774 00:40:22.688968 Set Vref, RX VrefLevel [Byte0]: 69
1775 00:40:22.689019 [Byte1]: 69
1776 00:40:22.689069
1777 00:40:22.689120 Set Vref, RX VrefLevel [Byte0]: 70
1778 00:40:22.689171 [Byte1]: 70
1779 00:40:22.689222
1780 00:40:22.689316 Set Vref, RX VrefLevel [Byte0]: 71
1781 00:40:22.689417 [Byte1]: 71
1782 00:40:22.689468
1783 00:40:22.689519 Set Vref, RX VrefLevel [Byte0]: 72
1784 00:40:22.689593 [Byte1]: 72
1785 00:40:22.689657
1786 00:40:22.689708 Final RX Vref Byte 0 = 60 to rank0
1787 00:40:22.689760 Final RX Vref Byte 1 = 53 to rank0
1788 00:40:22.689811 Final RX Vref Byte 0 = 60 to rank1
1789 00:40:22.689862 Final RX Vref Byte 1 = 53 to rank1==
1790 00:40:22.689914 Dram Type= 6, Freq= 0, CH_1, rank 0
1791 00:40:22.689965 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1792 00:40:22.690017 ==
1793 00:40:22.690069 DQS Delay:
1794 00:40:22.690129 DQS0 = 0, DQS1 = 0
1795 00:40:22.690182 DQM Delay:
1796 00:40:22.690232 DQM0 = 85, DQM1 = 79
1797 00:40:22.690284 DQ Delay:
1798 00:40:22.690334 DQ0 =88, DQ1 =80, DQ2 =76, DQ3 =84
1799 00:40:22.690386 DQ4 =84, DQ5 =96, DQ6 =96, DQ7 =80
1800 00:40:22.690436 DQ8 =64, DQ9 =68, DQ10 =80, DQ11 =76
1801 00:40:22.690487 DQ12 =88, DQ13 =88, DQ14 =84, DQ15 =88
1802 00:40:22.690538
1803 00:40:22.690589
1804 00:40:22.690640 [DQSOSCAuto] RK0, (LSB)MR18= 0x2135, (MSB)MR19= 0x606, tDQSOscB0 = 396 ps tDQSOscB1 = 401 ps
1805 00:40:22.690692 CH1 RK0: MR19=606, MR18=2135
1806 00:40:22.690744 CH1_RK0: MR19=0x606, MR18=0x2135, DQSOSC=396, MR23=63, INC=94, DEC=62
1807 00:40:22.690795
1808 00:40:22.690847 ----->DramcWriteLeveling(PI) begin...
1809 00:40:22.690900 ==
1810 00:40:22.690951 Dram Type= 6, Freq= 0, CH_1, rank 1
1811 00:40:22.691002 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1812 00:40:22.691056 ==
1813 00:40:22.691107 Write leveling (Byte 0): 25 => 25
1814 00:40:22.691159 Write leveling (Byte 1): 30 => 30
1815 00:40:22.691210 DramcWriteLeveling(PI) end<-----
1816 00:40:22.691261
1817 00:40:22.691312 ==
1818 00:40:22.691364 Dram Type= 6, Freq= 0, CH_1, rank 1
1819 00:40:22.691415 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1820 00:40:22.691466 ==
1821 00:40:22.691517 [Gating] SW mode calibration
1822 00:40:22.691569 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1823 00:40:22.691621 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1824 00:40:22.691672 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1825 00:40:22.691724 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1826 00:40:22.691776 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1827 00:40:22.691827 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 00:40:22.691878 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 00:40:22.691929 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 00:40:22.691980 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 00:40:22.692031 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 00:40:22.692082 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 00:40:22.692133 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 00:40:22.692184 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 00:40:22.692235 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 00:40:22.692286 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 00:40:22.692337 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 00:40:22.692389 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 00:40:22.692440 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 00:40:22.692491 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1841 00:40:22.692542 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1842 00:40:22.692593 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 00:40:22.692644 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1844 00:40:22.692696 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1845 00:40:22.692753 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1846 00:40:22.692818 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1847 00:40:22.692909 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1848 00:40:22.693002 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1849 00:40:22.693095 0 9 4 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
1850 00:40:22.693179 0 9 8 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
1851 00:40:22.693282 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1852 00:40:22.693354 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1853 00:40:22.693406 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1854 00:40:22.693458 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1855 00:40:22.693510 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1856 00:40:22.693767 0 10 0 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)
1857 00:40:22.693830 0 10 4 | B1->B0 | 3434 2e2e | 0 0 | (0 1) (0 0)
1858 00:40:22.693883 0 10 8 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
1859 00:40:22.693936 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1860 00:40:22.693988 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1861 00:40:22.694039 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1862 00:40:22.694090 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1863 00:40:22.694142 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1864 00:40:22.694193 0 11 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1865 00:40:22.694245 0 11 4 | B1->B0 | 2e2e 3c3c | 0 0 | (0 0) (0 0)
1866 00:40:22.694296 0 11 8 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
1867 00:40:22.694347 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1868 00:40:22.694399 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1869 00:40:22.694450 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1870 00:40:22.694502 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1871 00:40:22.694553 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1872 00:40:22.694604 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1873 00:40:22.694655 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1874 00:40:22.694707 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1875 00:40:22.694758 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 00:40:22.694810 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1877 00:40:22.694862 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1878 00:40:22.694913 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1879 00:40:22.694964 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1880 00:40:22.695015 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1881 00:40:22.695066 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1882 00:40:22.695117 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1883 00:40:22.695169 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1884 00:40:22.695220 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1885 00:40:22.695272 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1886 00:40:22.695323 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1887 00:40:22.695392 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1888 00:40:22.695447 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1889 00:40:22.695504 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1890 00:40:22.695556 Total UI for P1: 0, mck2ui 16
1891 00:40:22.695608 best dqsien dly found for B0: ( 0, 14, 0)
1892 00:40:22.695660 Total UI for P1: 0, mck2ui 16
1893 00:40:22.695711 best dqsien dly found for B1: ( 0, 14, 2)
1894 00:40:22.695763 best DQS0 dly(MCK, UI, PI) = (0, 14, 0)
1895 00:40:22.695815 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1896 00:40:22.695866
1897 00:40:22.695920 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 0)
1898 00:40:22.695972 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1899 00:40:22.696024 [Gating] SW calibration Done
1900 00:40:22.696075 ==
1901 00:40:22.696126 Dram Type= 6, Freq= 0, CH_1, rank 1
1902 00:40:22.696178 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1903 00:40:22.696230 ==
1904 00:40:22.696281 RX Vref Scan: 0
1905 00:40:22.696332
1906 00:40:22.696383 RX Vref 0 -> 0, step: 1
1907 00:40:22.696433
1908 00:40:22.696485 RX Delay -130 -> 252, step: 16
1909 00:40:22.696536 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1910 00:40:22.696587 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1911 00:40:22.696645 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1912 00:40:22.696698 iDelay=206, Bit 3, Center 77 (-34 ~ 189) 224
1913 00:40:22.696750 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1914 00:40:22.696802 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1915 00:40:22.696853 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1916 00:40:22.696905 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
1917 00:40:22.696956 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1918 00:40:22.697007 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1919 00:40:22.697058 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1920 00:40:22.697110 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1921 00:40:22.697161 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
1922 00:40:22.697212 iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224
1923 00:40:22.697292 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
1924 00:40:22.697360 iDelay=206, Bit 15, Center 93 (-18 ~ 205) 224
1925 00:40:22.697412 ==
1926 00:40:22.697468 Dram Type= 6, Freq= 0, CH_1, rank 1
1927 00:40:22.697565 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1928 00:40:22.697634 ==
1929 00:40:22.697686 DQS Delay:
1930 00:40:22.697737 DQS0 = 0, DQS1 = 0
1931 00:40:22.697788 DQM Delay:
1932 00:40:22.697839 DQM0 = 83, DQM1 = 83
1933 00:40:22.697890 DQ Delay:
1934 00:40:22.697942 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =77
1935 00:40:22.697993 DQ4 =85, DQ5 =93, DQ6 =85, DQ7 =85
1936 00:40:22.698044 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
1937 00:40:22.698095 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1938 00:40:22.698155
1939 00:40:22.698247
1940 00:40:22.698336 ==
1941 00:40:22.698423 Dram Type= 6, Freq= 0, CH_1, rank 1
1942 00:40:22.698519 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1943 00:40:22.698572 ==
1944 00:40:22.698624
1945 00:40:22.698676
1946 00:40:22.698727 TX Vref Scan disable
1947 00:40:22.698779 == TX Byte 0 ==
1948 00:40:22.698831 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1949 00:40:22.698883 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1950 00:40:22.698935 == TX Byte 1 ==
1951 00:40:22.698990 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1952 00:40:22.699058 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1953 00:40:22.699111 ==
1954 00:40:22.944460 Dram Type= 6, Freq= 0, CH_1, rank 1
1955 00:40:22.944625 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1956 00:40:22.944719 ==
1957 00:40:22.944807 TX Vref=22, minBit 1, minWin=27, winSum=447
1958 00:40:22.944894 TX Vref=24, minBit 1, minWin=27, winSum=448
1959 00:40:22.944978 TX Vref=26, minBit 1, minWin=27, winSum=450
1960 00:40:22.945061 TX Vref=28, minBit 6, minWin=27, winSum=452
1961 00:40:22.945144 TX Vref=30, minBit 0, minWin=28, winSum=457
1962 00:40:22.945226 TX Vref=32, minBit 0, minWin=27, winSum=453
1963 00:40:22.945321 [TxChooseVref] Worse bit 0, Min win 28, Win sum 457, Final Vref 30
1964 00:40:22.945389
1965 00:40:22.945652 Final TX Range 1 Vref 30
1966 00:40:22.945712
1967 00:40:22.945766 ==
1968 00:40:22.945820 Dram Type= 6, Freq= 0, CH_1, rank 1
1969 00:40:22.945874 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1970 00:40:22.945926 ==
1971 00:40:22.945978
1972 00:40:22.946031
1973 00:40:22.946082 TX Vref Scan disable
1974 00:40:22.946134 == TX Byte 0 ==
1975 00:40:22.946186 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1976 00:40:22.946237 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1977 00:40:22.946289 == TX Byte 1 ==
1978 00:40:22.946340 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1979 00:40:22.946392 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1980 00:40:22.946443
1981 00:40:22.946494 [DATLAT]
1982 00:40:22.946545 Freq=800, CH1 RK1
1983 00:40:22.946597
1984 00:40:22.946648 DATLAT Default: 0xa
1985 00:40:22.946699 0, 0xFFFF, sum = 0
1986 00:40:22.946751 1, 0xFFFF, sum = 0
1987 00:40:22.946804 2, 0xFFFF, sum = 0
1988 00:40:22.946856 3, 0xFFFF, sum = 0
1989 00:40:22.946908 4, 0xFFFF, sum = 0
1990 00:40:22.946970 5, 0xFFFF, sum = 0
1991 00:40:22.947022 6, 0xFFFF, sum = 0
1992 00:40:22.947075 7, 0xFFFF, sum = 0
1993 00:40:22.947126 8, 0xFFFF, sum = 0
1994 00:40:22.947178 9, 0x0, sum = 1
1995 00:40:22.947230 10, 0x0, sum = 2
1996 00:40:22.947282 11, 0x0, sum = 3
1997 00:40:22.947334 12, 0x0, sum = 4
1998 00:40:22.947386 best_step = 10
1999 00:40:22.947436
2000 00:40:22.947487 ==
2001 00:40:22.947538 Dram Type= 6, Freq= 0, CH_1, rank 1
2002 00:40:22.947589 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2003 00:40:22.947641 ==
2004 00:40:22.947693 RX Vref Scan: 0
2005 00:40:22.947743
2006 00:40:22.947794 RX Vref 0 -> 0, step: 1
2007 00:40:22.947846
2008 00:40:22.947896 RX Delay -95 -> 252, step: 8
2009 00:40:22.947948 iDelay=209, Bit 0, Center 92 (-23 ~ 208) 232
2010 00:40:22.947999 iDelay=209, Bit 1, Center 80 (-39 ~ 200) 240
2011 00:40:22.948055 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
2012 00:40:22.948137 iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224
2013 00:40:22.948192 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
2014 00:40:22.948278 iDelay=209, Bit 5, Center 96 (-15 ~ 208) 224
2015 00:40:22.948395 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
2016 00:40:22.948466 iDelay=209, Bit 7, Center 84 (-31 ~ 200) 232
2017 00:40:22.948519 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
2018 00:40:22.948572 iDelay=209, Bit 9, Center 72 (-39 ~ 184) 224
2019 00:40:22.948624 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
2020 00:40:22.948676 iDelay=209, Bit 11, Center 72 (-39 ~ 184) 224
2021 00:40:22.948727 iDelay=209, Bit 12, Center 88 (-23 ~ 200) 224
2022 00:40:22.948778 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
2023 00:40:22.948829 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2024 00:40:22.948881 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
2025 00:40:22.948965 ==
2026 00:40:22.949054 Dram Type= 6, Freq= 0, CH_1, rank 1
2027 00:40:22.949137 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2028 00:40:22.949218 ==
2029 00:40:22.949343 DQS Delay:
2030 00:40:22.949397 DQS0 = 0, DQS1 = 0
2031 00:40:22.949449 DQM Delay:
2032 00:40:22.949501 DQM0 = 86, DQM1 = 80
2033 00:40:22.949552 DQ Delay:
2034 00:40:22.949604 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =80
2035 00:40:22.949655 DQ4 =84, DQ5 =96, DQ6 =96, DQ7 =84
2036 00:40:22.949707 DQ8 =68, DQ9 =72, DQ10 =80, DQ11 =72
2037 00:40:22.949758 DQ12 =88, DQ13 =88, DQ14 =88, DQ15 =88
2038 00:40:22.949810
2039 00:40:22.949883
2040 00:40:22.949934 [DQSOSCAuto] RK1, (LSB)MR18= 0x213d, (MSB)MR19= 0x606, tDQSOscB0 = 394 ps tDQSOscB1 = 401 ps
2041 00:40:22.949987 CH1 RK1: MR19=606, MR18=213D
2042 00:40:22.950039 CH1_RK1: MR19=0x606, MR18=0x213D, DQSOSC=394, MR23=63, INC=95, DEC=63
2043 00:40:22.950098 [RxdqsGatingPostProcess] freq 800
2044 00:40:22.950181 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2045 00:40:22.950233 Pre-setting of DQS Precalculation
2046 00:40:22.950284 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2047 00:40:22.950335 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2048 00:40:22.950388 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2049 00:40:22.950439
2050 00:40:22.950489
2051 00:40:22.950540 [Calibration Summary] 1600 Mbps
2052 00:40:22.950592 CH 0, Rank 0
2053 00:40:22.950643 SW Impedance : PASS
2054 00:40:22.950695 DUTY Scan : NO K
2055 00:40:22.950746 ZQ Calibration : PASS
2056 00:40:22.950798 Jitter Meter : NO K
2057 00:40:22.950849 CBT Training : PASS
2058 00:40:22.950900 Write leveling : PASS
2059 00:40:22.950951 RX DQS gating : PASS
2060 00:40:22.951002 RX DQ/DQS(RDDQC) : PASS
2061 00:40:22.951052 TX DQ/DQS : PASS
2062 00:40:22.951104 RX DATLAT : PASS
2063 00:40:22.951154 RX DQ/DQS(Engine): PASS
2064 00:40:22.951205 TX OE : NO K
2065 00:40:22.951257 All Pass.
2066 00:40:22.951308
2067 00:40:22.951360 CH 0, Rank 1
2068 00:40:22.951412 SW Impedance : PASS
2069 00:40:22.951463 DUTY Scan : NO K
2070 00:40:22.951514 ZQ Calibration : PASS
2071 00:40:22.951566 Jitter Meter : NO K
2072 00:40:22.951617 CBT Training : PASS
2073 00:40:22.951669 Write leveling : PASS
2074 00:40:22.951720 RX DQS gating : PASS
2075 00:40:22.951772 RX DQ/DQS(RDDQC) : PASS
2076 00:40:22.951828 TX DQ/DQS : PASS
2077 00:40:22.951880 RX DATLAT : PASS
2078 00:40:22.951931 RX DQ/DQS(Engine): PASS
2079 00:40:22.951982 TX OE : NO K
2080 00:40:22.952033 All Pass.
2081 00:40:22.952084
2082 00:40:22.952135 CH 1, Rank 0
2083 00:40:22.952187 SW Impedance : PASS
2084 00:40:22.952238 DUTY Scan : NO K
2085 00:40:22.952290 ZQ Calibration : PASS
2086 00:40:22.952341 Jitter Meter : NO K
2087 00:40:22.952392 CBT Training : PASS
2088 00:40:22.952444 Write leveling : PASS
2089 00:40:22.952495 RX DQS gating : PASS
2090 00:40:22.952546 RX DQ/DQS(RDDQC) : PASS
2091 00:40:22.952611 TX DQ/DQS : PASS
2092 00:40:22.952665 RX DATLAT : PASS
2093 00:40:22.952717 RX DQ/DQS(Engine): PASS
2094 00:40:22.952768 TX OE : NO K
2095 00:40:22.952820 All Pass.
2096 00:40:22.952872
2097 00:40:22.952923 CH 1, Rank 1
2098 00:40:22.952975 SW Impedance : PASS
2099 00:40:22.953026 DUTY Scan : NO K
2100 00:40:22.953078 ZQ Calibration : PASS
2101 00:40:22.953129 Jitter Meter : NO K
2102 00:40:22.953181 CBT Training : PASS
2103 00:40:22.953231 Write leveling : PASS
2104 00:40:22.953321 RX DQS gating : PASS
2105 00:40:22.953396 RX DQ/DQS(RDDQC) : PASS
2106 00:40:22.953450 TX DQ/DQS : PASS
2107 00:40:22.953540 RX DATLAT : PASS
2108 00:40:22.953633 RX DQ/DQS(Engine): PASS
2109 00:40:22.953730 TX OE : NO K
2110 00:40:22.953784 All Pass.
2111 00:40:22.953897
2112 00:40:22.953976 DramC Write-DBI off
2113 00:40:22.954044 PER_BANK_REFRESH: Hybrid Mode
2114 00:40:22.954097 TX_TRACKING: ON
2115 00:40:22.954148 [GetDramInforAfterCalByMRR] Vendor 6.
2116 00:40:22.954201 [GetDramInforAfterCalByMRR] Revision 606.
2117 00:40:22.954253 [GetDramInforAfterCalByMRR] Revision 2 0.
2118 00:40:22.954306 MR0 0x3b3b
2119 00:40:22.954358 MR8 0x5151
2120 00:40:22.954409 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2121 00:40:22.954461
2122 00:40:22.954722 MR0 0x3b3b
2123 00:40:22.954800 MR8 0x5151
2124 00:40:22.954906 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2125 00:40:22.955009
2126 00:40:22.955117 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2127 00:40:22.955217 [FAST_K] Save calibration result to emmc
2128 00:40:22.955307 [FAST_K] Save calibration result to emmc
2129 00:40:22.955390 dram_init: config_dvfs: 1
2130 00:40:22.955471 dramc_set_vcore_voltage set vcore to 662500
2131 00:40:22.955552 Read voltage for 1200, 2
2132 00:40:22.955633 Vio18 = 0
2133 00:40:22.955713 Vcore = 662500
2134 00:40:22.955793 Vdram = 0
2135 00:40:22.955861 Vddq = 0
2136 00:40:22.955914 Vmddr = 0
2137 00:40:22.955966 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2138 00:40:22.956019 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2139 00:40:22.956071 MEM_TYPE=3, freq_sel=15
2140 00:40:22.956122 sv_algorithm_assistance_LP4_1600
2141 00:40:22.956174 ============ PULL DRAM RESETB DOWN ============
2142 00:40:22.956226 ========== PULL DRAM RESETB DOWN end =========
2143 00:40:22.956278 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2144 00:40:22.956330 ===================================
2145 00:40:22.956382 LPDDR4 DRAM CONFIGURATION
2146 00:40:22.956433 ===================================
2147 00:40:22.956485 EX_ROW_EN[0] = 0x0
2148 00:40:22.956537 EX_ROW_EN[1] = 0x0
2149 00:40:22.956588 LP4Y_EN = 0x0
2150 00:40:22.956639 WORK_FSP = 0x0
2151 00:40:22.956691 WL = 0x4
2152 00:40:22.956752 RL = 0x4
2153 00:40:22.956804 BL = 0x2
2154 00:40:22.956855 RPST = 0x0
2155 00:40:22.956906 RD_PRE = 0x0
2156 00:40:22.956957 WR_PRE = 0x1
2157 00:40:22.957009 WR_PST = 0x0
2158 00:40:22.957060 DBI_WR = 0x0
2159 00:40:22.957112 DBI_RD = 0x0
2160 00:40:22.957162 OTF = 0x1
2161 00:40:22.957214 ===================================
2162 00:40:22.957293 ===================================
2163 00:40:22.957360 ANA top config
2164 00:40:22.957412 ===================================
2165 00:40:22.957464 DLL_ASYNC_EN = 0
2166 00:40:22.957515 ALL_SLAVE_EN = 0
2167 00:40:22.957566 NEW_RANK_MODE = 1
2168 00:40:22.957618 DLL_IDLE_MODE = 1
2169 00:40:22.957669 LP45_APHY_COMB_EN = 1
2170 00:40:22.957719 TX_ODT_DIS = 1
2171 00:40:22.957770 NEW_8X_MODE = 1
2172 00:40:22.957831 ===================================
2173 00:40:22.957932 ===================================
2174 00:40:22.957999 data_rate = 2400
2175 00:40:22.958081 CKR = 1
2176 00:40:22.958133 DQ_P2S_RATIO = 8
2177 00:40:22.958184 ===================================
2178 00:40:22.958236 CA_P2S_RATIO = 8
2179 00:40:22.958287 DQ_CA_OPEN = 0
2180 00:40:22.958338 DQ_SEMI_OPEN = 0
2181 00:40:22.958389 CA_SEMI_OPEN = 0
2182 00:40:22.958441 CA_FULL_RATE = 0
2183 00:40:22.958492 DQ_CKDIV4_EN = 0
2184 00:40:22.958543 CA_CKDIV4_EN = 0
2185 00:40:22.958595 CA_PREDIV_EN = 0
2186 00:40:22.958646 PH8_DLY = 17
2187 00:40:22.958698 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2188 00:40:22.958749 DQ_AAMCK_DIV = 4
2189 00:40:22.958801 CA_AAMCK_DIV = 4
2190 00:40:22.958852 CA_ADMCK_DIV = 4
2191 00:40:22.958903 DQ_TRACK_CA_EN = 0
2192 00:40:22.958954 CA_PICK = 1200
2193 00:40:22.959006 CA_MCKIO = 1200
2194 00:40:22.959057 MCKIO_SEMI = 0
2195 00:40:22.959108 PLL_FREQ = 2366
2196 00:40:22.959181 DQ_UI_PI_RATIO = 32
2197 00:40:22.959252 CA_UI_PI_RATIO = 0
2198 00:40:22.959335 ===================================
2199 00:40:22.959432 ===================================
2200 00:40:22.959526 memory_type:LPDDR4
2201 00:40:22.959580 GP_NUM : 10
2202 00:40:22.959633 SRAM_EN : 1
2203 00:40:22.959686 MD32_EN : 0
2204 00:40:22.959737 ===================================
2205 00:40:22.959790 [ANA_INIT] >>>>>>>>>>>>>>
2206 00:40:22.959850 <<<<<< [CONFIGURE PHASE]: ANA_TX
2207 00:40:22.959904 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2208 00:40:22.959956 ===================================
2209 00:40:22.960008 data_rate = 2400,PCW = 0X5b00
2210 00:40:22.960061 ===================================
2211 00:40:22.960113 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2212 00:40:22.960177 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2213 00:40:22.960231 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2214 00:40:22.960284 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2215 00:40:22.960336 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2216 00:40:22.960388 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2217 00:40:22.960440 [ANA_INIT] flow start
2218 00:40:22.960492 [ANA_INIT] PLL >>>>>>>>
2219 00:40:22.960543 [ANA_INIT] PLL <<<<<<<<
2220 00:40:22.960595 [ANA_INIT] MIDPI >>>>>>>>
2221 00:40:22.960646 [ANA_INIT] MIDPI <<<<<<<<
2222 00:40:22.960698 [ANA_INIT] DLL >>>>>>>>
2223 00:40:22.960749 [ANA_INIT] DLL <<<<<<<<
2224 00:40:22.960801 [ANA_INIT] flow end
2225 00:40:22.960853 ============ LP4 DIFF to SE enter ============
2226 00:40:22.960905 ============ LP4 DIFF to SE exit ============
2227 00:40:22.960957 [ANA_INIT] <<<<<<<<<<<<<
2228 00:40:22.961009 [Flow] Enable top DCM control >>>>>
2229 00:40:22.961061 [Flow] Enable top DCM control <<<<<
2230 00:40:22.961112 Enable DLL master slave shuffle
2231 00:40:22.961164 ==============================================================
2232 00:40:22.961216 Gating Mode config
2233 00:40:22.961295 ==============================================================
2234 00:40:22.961362 Config description:
2235 00:40:22.961414 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2236 00:40:22.961467 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2237 00:40:22.961520 SELPH_MODE 0: By rank 1: By Phase
2238 00:40:22.961572 ==============================================================
2239 00:40:22.961625 GAT_TRACK_EN = 1
2240 00:40:22.961676 RX_GATING_MODE = 2
2241 00:40:22.961728 RX_GATING_TRACK_MODE = 2
2242 00:40:22.962013 SELPH_MODE = 1
2243 00:40:22.962143 PICG_EARLY_EN = 1
2244 00:40:22.962200 VALID_LAT_VALUE = 1
2245 00:40:22.962255 ==============================================================
2246 00:40:22.962310 Enter into Gating configuration >>>>
2247 00:40:22.962363 Exit from Gating configuration <<<<
2248 00:40:22.962416 Enter into DVFS_PRE_config >>>>>
2249 00:40:22.962470 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2250 00:40:22.962525 Exit from DVFS_PRE_config <<<<<
2251 00:40:22.962592 Enter into PICG configuration >>>>
2252 00:40:22.962644 Exit from PICG configuration <<<<
2253 00:40:22.962695 [RX_INPUT] configuration >>>>>
2254 00:40:22.962747 [RX_INPUT] configuration <<<<<
2255 00:40:22.962799 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2256 00:40:22.962851 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2257 00:40:22.962902 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2258 00:40:22.962955 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2259 00:40:22.963007 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2260 00:40:22.963059 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2261 00:40:22.963111 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2262 00:40:22.963163 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2263 00:40:22.963215 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2264 00:40:22.963266 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2265 00:40:22.963318 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2266 00:40:22.963370 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2267 00:40:22.963462 ===================================
2268 00:40:22.963515 LPDDR4 DRAM CONFIGURATION
2269 00:40:22.963566 ===================================
2270 00:40:22.963619 EX_ROW_EN[0] = 0x0
2271 00:40:22.963670 EX_ROW_EN[1] = 0x0
2272 00:40:22.963722 LP4Y_EN = 0x0
2273 00:40:22.963773 WORK_FSP = 0x0
2274 00:40:22.963825 WL = 0x4
2275 00:40:22.963876 RL = 0x4
2276 00:40:22.963928 BL = 0x2
2277 00:40:22.963988 RPST = 0x0
2278 00:40:22.964041 RD_PRE = 0x0
2279 00:40:22.964092 WR_PRE = 0x1
2280 00:40:22.964144 WR_PST = 0x0
2281 00:40:22.964195 DBI_WR = 0x0
2282 00:40:22.964247 DBI_RD = 0x0
2283 00:40:22.964298 OTF = 0x1
2284 00:40:22.964355 ===================================
2285 00:40:22.964407 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2286 00:40:22.964459 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2287 00:40:22.964510 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2288 00:40:22.964562 ===================================
2289 00:40:22.964614 LPDDR4 DRAM CONFIGURATION
2290 00:40:22.964665 ===================================
2291 00:40:22.964716 EX_ROW_EN[0] = 0x10
2292 00:40:22.964768 EX_ROW_EN[1] = 0x0
2293 00:40:22.964819 LP4Y_EN = 0x0
2294 00:40:22.964871 WORK_FSP = 0x0
2295 00:40:22.964922 WL = 0x4
2296 00:40:22.964973 RL = 0x4
2297 00:40:22.965024 BL = 0x2
2298 00:40:22.965075 RPST = 0x0
2299 00:40:22.965126 RD_PRE = 0x0
2300 00:40:22.965177 WR_PRE = 0x1
2301 00:40:22.965228 WR_PST = 0x0
2302 00:40:22.965323 DBI_WR = 0x0
2303 00:40:22.965376 DBI_RD = 0x0
2304 00:40:22.965427 OTF = 0x1
2305 00:40:22.965478 ===================================
2306 00:40:22.965530 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2307 00:40:22.965582 ==
2308 00:40:22.965634 Dram Type= 6, Freq= 0, CH_0, rank 0
2309 00:40:22.965686 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2310 00:40:22.965739 ==
2311 00:40:22.965790 [Duty_Offset_Calibration]
2312 00:40:22.965842 B0:2 B1:0 CA:4
2313 00:40:22.965893
2314 00:40:22.965948 [DutyScan_Calibration_Flow] k_type=0
2315 00:40:22.966021
2316 00:40:22.966105 ==CLK 0==
2317 00:40:22.966239 Final CLK duty delay cell = -4
2318 00:40:22.966308 [-4] MAX Duty = 5031%(X100), DQS PI = 32
2319 00:40:22.966401 [-4] MIN Duty = 4844%(X100), DQS PI = 8
2320 00:40:22.966503 [-4] AVG Duty = 4937%(X100)
2321 00:40:22.966573
2322 00:40:22.966626 CH0 CLK Duty spec in!! Max-Min= 187%
2323 00:40:22.966679 [DutyScan_Calibration_Flow] ====Done====
2324 00:40:22.966732
2325 00:40:22.966784 [DutyScan_Calibration_Flow] k_type=1
2326 00:40:22.966835
2327 00:40:22.966886 ==DQS 0 ==
2328 00:40:22.966938 Final DQS duty delay cell = 0
2329 00:40:22.966990 [0] MAX Duty = 5156%(X100), DQS PI = 18
2330 00:40:22.967055 [0] MIN Duty = 5093%(X100), DQS PI = 0
2331 00:40:22.967108 [0] AVG Duty = 5124%(X100)
2332 00:40:22.967159
2333 00:40:22.967210 ==DQS 1 ==
2334 00:40:22.967261 Final DQS duty delay cell = 0
2335 00:40:22.967314 [0] MAX Duty = 5125%(X100), DQS PI = 48
2336 00:40:22.967364 [0] MIN Duty = 4969%(X100), DQS PI = 14
2337 00:40:22.967415 [0] AVG Duty = 5047%(X100)
2338 00:40:22.967466
2339 00:40:22.967517 CH0 DQS 0 Duty spec in!! Max-Min= 63%
2340 00:40:22.967568
2341 00:40:22.967619 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2342 00:40:22.967671 [DutyScan_Calibration_Flow] ====Done====
2343 00:40:22.967721
2344 00:40:22.967772 [DutyScan_Calibration_Flow] k_type=3
2345 00:40:22.967822
2346 00:40:22.967873 ==DQM 0 ==
2347 00:40:22.967924 Final DQM duty delay cell = 0
2348 00:40:22.967975 [0] MAX Duty = 5094%(X100), DQS PI = 20
2349 00:40:22.968027 [0] MIN Duty = 4844%(X100), DQS PI = 44
2350 00:40:22.968077 [0] AVG Duty = 4969%(X100)
2351 00:40:22.968128
2352 00:40:22.968178 ==DQM 1 ==
2353 00:40:22.968229 Final DQM duty delay cell = 0
2354 00:40:22.968281 [0] MAX Duty = 4969%(X100), DQS PI = 2
2355 00:40:22.968332 [0] MIN Duty = 4875%(X100), DQS PI = 14
2356 00:40:22.968383 [0] AVG Duty = 4922%(X100)
2357 00:40:22.968434
2358 00:40:22.968485 CH0 DQM 0 Duty spec in!! Max-Min= 250%
2359 00:40:22.968535
2360 00:40:22.968586 CH0 DQM 1 Duty spec in!! Max-Min= 94%
2361 00:40:22.968637 [DutyScan_Calibration_Flow] ====Done====
2362 00:40:22.968688
2363 00:40:22.968738 [DutyScan_Calibration_Flow] k_type=2
2364 00:40:22.968789
2365 00:40:22.968840 ==DQ 0 ==
2366 00:40:22.968891 Final DQ duty delay cell = 0
2367 00:40:22.968942 [0] MAX Duty = 5125%(X100), DQS PI = 18
2368 00:40:22.968994 [0] MIN Duty = 4938%(X100), DQS PI = 58
2369 00:40:22.969045 [0] AVG Duty = 5031%(X100)
2370 00:40:22.969095
2371 00:40:22.969146 ==DQ 1 ==
2372 00:40:22.969197 Final DQ duty delay cell = 0
2373 00:40:22.969249 [0] MAX Duty = 5125%(X100), DQS PI = 4
2374 00:40:22.969361 [0] MIN Duty = 4938%(X100), DQS PI = 16
2375 00:40:22.969416 [0] AVG Duty = 5031%(X100)
2376 00:40:22.969467
2377 00:40:22.969758 CH0 DQ 0 Duty spec in!! Max-Min= 187%
2378 00:40:22.969920
2379 00:40:22.969978 CH0 DQ 1 Duty spec in!! Max-Min= 187%
2380 00:40:22.970033 [DutyScan_Calibration_Flow] ====Done====
2381 00:40:22.970086 ==
2382 00:40:22.970139 Dram Type= 6, Freq= 0, CH_1, rank 0
2383 00:40:22.970192 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2384 00:40:22.970245 ==
2385 00:40:22.970341 [Duty_Offset_Calibration]
2386 00:40:22.970394 B0:0 B1:-1 CA:3
2387 00:40:22.970446
2388 00:40:22.970498 [DutyScan_Calibration_Flow] k_type=0
2389 00:40:22.970550
2390 00:40:22.970667 ==CLK 0==
2391 00:40:22.970822 Final CLK duty delay cell = -4
2392 00:40:22.970927 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2393 00:40:22.970991 [-4] MIN Duty = 4876%(X100), DQS PI = 36
2394 00:40:22.971045 [-4] AVG Duty = 4938%(X100)
2395 00:40:22.971098
2396 00:40:22.971150 CH1 CLK Duty spec in!! Max-Min= 124%
2397 00:40:22.971203 [DutyScan_Calibration_Flow] ====Done====
2398 00:40:22.971255
2399 00:40:22.971307 [DutyScan_Calibration_Flow] k_type=1
2400 00:40:22.971359
2401 00:40:22.971411 ==DQS 0 ==
2402 00:40:22.971462 Final DQS duty delay cell = 0
2403 00:40:22.971515 [0] MAX Duty = 5187%(X100), DQS PI = 18
2404 00:40:22.971567 [0] MIN Duty = 4907%(X100), DQS PI = 38
2405 00:40:22.971619 [0] AVG Duty = 5047%(X100)
2406 00:40:22.971671
2407 00:40:22.971722 ==DQS 1 ==
2408 00:40:22.971774 Final DQS duty delay cell = 0
2409 00:40:22.971825 [0] MAX Duty = 5156%(X100), DQS PI = 8
2410 00:40:22.971877 [0] MIN Duty = 5000%(X100), DQS PI = 26
2411 00:40:22.971928 [0] AVG Duty = 5078%(X100)
2412 00:40:22.971988
2413 00:40:22.972040 CH1 DQS 0 Duty spec in!! Max-Min= 280%
2414 00:40:22.972091
2415 00:40:22.972143 CH1 DQS 1 Duty spec in!! Max-Min= 156%
2416 00:40:22.972194 [DutyScan_Calibration_Flow] ====Done====
2417 00:40:22.972247
2418 00:40:22.972299 [DutyScan_Calibration_Flow] k_type=3
2419 00:40:22.972350
2420 00:40:22.972400 ==DQM 0 ==
2421 00:40:22.972451 Final DQM duty delay cell = 0
2422 00:40:22.972503 [0] MAX Duty = 5031%(X100), DQS PI = 28
2423 00:40:22.972555 [0] MIN Duty = 4782%(X100), DQS PI = 38
2424 00:40:22.972606 [0] AVG Duty = 4906%(X100)
2425 00:40:22.972656
2426 00:40:22.972708 ==DQM 1 ==
2427 00:40:22.972759 Final DQM duty delay cell = 4
2428 00:40:22.972811 [4] MAX Duty = 5187%(X100), DQS PI = 48
2429 00:40:22.972862 [4] MIN Duty = 5062%(X100), DQS PI = 18
2430 00:40:22.972913 [4] AVG Duty = 5124%(X100)
2431 00:40:22.972964
2432 00:40:22.973016 CH1 DQM 0 Duty spec in!! Max-Min= 249%
2433 00:40:22.973067
2434 00:40:22.973118 CH1 DQM 1 Duty spec in!! Max-Min= 125%
2435 00:40:22.973170 [DutyScan_Calibration_Flow] ====Done====
2436 00:40:22.973221
2437 00:40:22.973325 [DutyScan_Calibration_Flow] k_type=2
2438 00:40:22.973491
2439 00:40:22.973593 ==DQ 0 ==
2440 00:40:22.973651 Final DQ duty delay cell = -4
2441 00:40:22.973705 [-4] MAX Duty = 5000%(X100), DQS PI = 14
2442 00:40:22.973758 [-4] MIN Duty = 4844%(X100), DQS PI = 36
2443 00:40:22.973810 [-4] AVG Duty = 4922%(X100)
2444 00:40:22.973862
2445 00:40:22.973913 ==DQ 1 ==
2446 00:40:22.973965 Final DQ duty delay cell = 0
2447 00:40:22.974018 [0] MAX Duty = 5031%(X100), DQS PI = 34
2448 00:40:22.974069 [0] MIN Duty = 4844%(X100), DQS PI = 62
2449 00:40:22.974120 [0] AVG Duty = 4937%(X100)
2450 00:40:22.974171
2451 00:40:22.974222 CH1 DQ 0 Duty spec in!! Max-Min= 156%
2452 00:40:22.974274
2453 00:40:22.974325 CH1 DQ 1 Duty spec in!! Max-Min= 187%
2454 00:40:22.974376 [DutyScan_Calibration_Flow] ====Done====
2455 00:40:22.974427 nWR fixed to 30
2456 00:40:22.974479 [ModeRegInit_LP4] CH0 RK0
2457 00:40:22.974531 [ModeRegInit_LP4] CH0 RK1
2458 00:40:22.974581 [ModeRegInit_LP4] CH1 RK0
2459 00:40:22.974633 [ModeRegInit_LP4] CH1 RK1
2460 00:40:22.974691 match AC timing 7
2461 00:40:22.974792 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2462 00:40:22.974859 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2463 00:40:22.974958 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2464 00:40:22.975051 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2465 00:40:22.975148 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2466 00:40:22.975205 ==
2467 00:40:22.975260 Dram Type= 6, Freq= 0, CH_0, rank 0
2468 00:40:22.975315 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2469 00:40:22.975368 ==
2470 00:40:22.975422 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2471 00:40:22.975490 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2472 00:40:22.975547 [CA 0] Center 39 (9~70) winsize 62
2473 00:40:22.975614 [CA 1] Center 39 (9~69) winsize 61
2474 00:40:22.975666 [CA 2] Center 35 (5~66) winsize 62
2475 00:40:22.975718 [CA 3] Center 35 (5~66) winsize 62
2476 00:40:22.975769 [CA 4] Center 33 (3~64) winsize 62
2477 00:40:22.975820 [CA 5] Center 33 (3~64) winsize 62
2478 00:40:22.975870
2479 00:40:22.975922 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2480 00:40:22.975974
2481 00:40:22.976026 [CATrainingPosCal] consider 1 rank data
2482 00:40:22.976077 u2DelayCellTimex100 = 270/100 ps
2483 00:40:22.976128 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2484 00:40:22.976180 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2485 00:40:22.976232 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2486 00:40:22.976283 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2487 00:40:22.976334 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2488 00:40:22.976385 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2489 00:40:22.976436
2490 00:40:22.976488 CA PerBit enable=1, Macro0, CA PI delay=33
2491 00:40:22.976539
2492 00:40:22.976590 [CBTSetCACLKResult] CA Dly = 33
2493 00:40:22.976642 CS Dly: 7 (0~38)
2494 00:40:22.976693 ==
2495 00:40:22.976745 Dram Type= 6, Freq= 0, CH_0, rank 1
2496 00:40:22.976824 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2497 00:40:22.976891 ==
2498 00:40:22.976944 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2499 00:40:22.976996 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2500 00:40:22.977048 [CA 0] Center 39 (9~70) winsize 62
2501 00:40:22.977098 [CA 1] Center 39 (9~70) winsize 62
2502 00:40:22.977149 [CA 2] Center 35 (5~66) winsize 62
2503 00:40:22.977200 [CA 3] Center 35 (5~66) winsize 62
2504 00:40:22.977251 [CA 4] Center 34 (4~65) winsize 62
2505 00:40:22.977367 [CA 5] Center 33 (3~64) winsize 62
2506 00:40:22.977447
2507 00:40:22.977520 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2508 00:40:22.977574
2509 00:40:22.977626 [CATrainingPosCal] consider 2 rank data
2510 00:40:22.977677 u2DelayCellTimex100 = 270/100 ps
2511 00:40:22.977732 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2512 00:40:22.977783 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2513 00:40:22.977834 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2514 00:40:22.977886 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2515 00:40:22.977937 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
2516 00:40:22.977988 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2517 00:40:22.978038
2518 00:40:22.978294 CA PerBit enable=1, Macro0, CA PI delay=33
2519 00:40:22.978352
2520 00:40:22.978405 [CBTSetCACLKResult] CA Dly = 33
2521 00:40:22.978456 CS Dly: 8 (0~41)
2522 00:40:22.978508
2523 00:40:22.978560 ----->DramcWriteLeveling(PI) begin...
2524 00:40:22.978613 ==
2525 00:40:22.978665 Dram Type= 6, Freq= 0, CH_0, rank 0
2526 00:40:22.978717 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2527 00:40:22.978769 ==
2528 00:40:22.978820 Write leveling (Byte 0): 33 => 33
2529 00:40:22.978871 Write leveling (Byte 1): 27 => 27
2530 00:40:22.978923 DramcWriteLeveling(PI) end<-----
2531 00:40:22.978974
2532 00:40:22.979025 ==
2533 00:40:22.979076 Dram Type= 6, Freq= 0, CH_0, rank 0
2534 00:40:22.979127 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2535 00:40:22.979178 ==
2536 00:40:22.979230 [Gating] SW mode calibration
2537 00:40:22.979281 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2538 00:40:22.979334 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2539 00:40:22.979385 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2540 00:40:22.979436 0 15 4 | B1->B0 | 2b2b 3434 | 1 1 | (0 0) (1 1)
2541 00:40:22.979488 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2542 00:40:22.979539 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2543 00:40:22.979589 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2544 00:40:22.979640 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2545 00:40:22.979696 0 15 24 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
2546 00:40:22.979753 0 15 28 | B1->B0 | 3434 2626 | 1 0 | (1 1) (0 0)
2547 00:40:22.979818 1 0 0 | B1->B0 | 3434 2323 | 0 0 | (0 1) (0 0)
2548 00:40:22.979872 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2549 00:40:22.979924 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2550 00:40:22.979975 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2551 00:40:22.980144 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2552 00:40:22.980254 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2553 00:40:22.980329 1 0 24 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
2554 00:40:22.980402 1 0 28 | B1->B0 | 2323 4444 | 0 0 | (0 0) (0 0)
2555 00:40:22.980502 1 1 0 | B1->B0 | 2a2a 4646 | 1 0 | (1 1) (0 0)
2556 00:40:22.980581 1 1 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
2557 00:40:22.980637 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2558 00:40:22.980690 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2559 00:40:22.980742 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2560 00:40:22.980794 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2561 00:40:22.980846 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2562 00:40:22.980897 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2563 00:40:22.980949 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2564 00:40:22.981001 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2565 00:40:22.981052 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2566 00:40:22.981103 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2567 00:40:22.981155 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2568 00:40:22.981207 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2569 00:40:22.981270 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2570 00:40:22.981360 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2571 00:40:22.981412 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2572 00:40:22.981465 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2573 00:40:22.981516 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2574 00:40:22.981568 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2575 00:40:22.981619 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2576 00:40:22.981671 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2577 00:40:22.981726 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2578 00:40:22.981787 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2579 00:40:22.981850 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2580 00:40:22.981915 Total UI for P1: 0, mck2ui 16
2581 00:40:22.982009 best dqsien dly found for B0: ( 1, 3, 26)
2582 00:40:22.982093 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2583 00:40:22.982174 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2584 00:40:22.982255 Total UI for P1: 0, mck2ui 16
2585 00:40:22.982337 best dqsien dly found for B1: ( 1, 4, 2)
2586 00:40:22.982417 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2587 00:40:22.982498 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2588 00:40:22.982578
2589 00:40:22.982659 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2590 00:40:22.982740 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2591 00:40:22.982820 [Gating] SW calibration Done
2592 00:40:22.982900 ==
2593 00:40:22.982981 Dram Type= 6, Freq= 0, CH_0, rank 0
2594 00:40:22.983061 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2595 00:40:22.983142 ==
2596 00:40:22.983222 RX Vref Scan: 0
2597 00:40:22.983301
2598 00:40:22.983381 RX Vref 0 -> 0, step: 1
2599 00:40:22.983460
2600 00:40:22.983540 RX Delay -40 -> 252, step: 8
2601 00:40:22.983621 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2602 00:40:22.983702 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2603 00:40:22.983782 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2604 00:40:22.983850 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2605 00:40:22.983936 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2606 00:40:22.984017 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2607 00:40:22.984097 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2608 00:40:22.984178 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2609 00:40:22.984263 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2610 00:40:22.984344 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2611 00:40:22.984424 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2612 00:40:22.984505 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2613 00:40:22.984585 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2614 00:40:22.984666 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2615 00:40:22.984746 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2616 00:40:22.984827 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2617 00:40:22.984906 ==
2618 00:40:22.984986 Dram Type= 6, Freq= 0, CH_0, rank 0
2619 00:40:22.985302 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2620 00:40:22.985381 ==
2621 00:40:22.985443 DQS Delay:
2622 00:40:22.985534 DQS0 = 0, DQS1 = 0
2623 00:40:22.985625 DQM Delay:
2624 00:40:22.985745 DQM0 = 117, DQM1 = 108
2625 00:40:22.985844 DQ Delay:
2626 00:40:22.985927 DQ0 =115, DQ1 =119, DQ2 =119, DQ3 =111
2627 00:40:22.986009 DQ4 =119, DQ5 =111, DQ6 =123, DQ7 =123
2628 00:40:22.986091 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2629 00:40:22.986172 DQ12 =119, DQ13 =111, DQ14 =119, DQ15 =115
2630 00:40:22.986252
2631 00:40:22.986332
2632 00:40:22.986411 ==
2633 00:40:22.986492 Dram Type= 6, Freq= 0, CH_0, rank 0
2634 00:40:22.986573 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2635 00:40:22.986653 ==
2636 00:40:22.986707
2637 00:40:22.986759
2638 00:40:22.986810 TX Vref Scan disable
2639 00:40:22.986862 == TX Byte 0 ==
2640 00:40:22.986913 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2641 00:40:22.986965 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2642 00:40:22.987017 == TX Byte 1 ==
2643 00:40:22.987068 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2644 00:40:22.987119 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2645 00:40:22.987192 ==
2646 00:40:22.987306 Dram Type= 6, Freq= 0, CH_0, rank 0
2647 00:40:22.987359 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2648 00:40:22.987413 ==
2649 00:40:22.987465 TX Vref=22, minBit 5, minWin=25, winSum=416
2650 00:40:22.987517 TX Vref=24, minBit 13, minWin=25, winSum=421
2651 00:40:22.987568 TX Vref=26, minBit 3, minWin=26, winSum=424
2652 00:40:22.987620 TX Vref=28, minBit 10, minWin=26, winSum=435
2653 00:40:22.987672 TX Vref=30, minBit 10, minWin=26, winSum=433
2654 00:40:22.987723 TX Vref=32, minBit 4, minWin=26, winSum=429
2655 00:40:22.987793 [TxChooseVref] Worse bit 10, Min win 26, Win sum 435, Final Vref 28
2656 00:40:22.987846
2657 00:40:22.987898 Final TX Range 1 Vref 28
2658 00:40:22.987950
2659 00:40:22.988001 ==
2660 00:40:22.988052 Dram Type= 6, Freq= 0, CH_0, rank 0
2661 00:40:22.988103 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2662 00:40:22.988155 ==
2663 00:40:22.988206
2664 00:40:22.988257
2665 00:40:22.988308 TX Vref Scan disable
2666 00:40:22.988359 == TX Byte 0 ==
2667 00:40:22.988410 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2668 00:40:22.988462 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2669 00:40:22.988514 == TX Byte 1 ==
2670 00:40:22.988564 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2671 00:40:22.988615 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2672 00:40:22.988666
2673 00:40:22.988717 [DATLAT]
2674 00:40:22.988768 Freq=1200, CH0 RK0
2675 00:40:22.988819
2676 00:40:22.988870 DATLAT Default: 0xd
2677 00:40:22.988920 0, 0xFFFF, sum = 0
2678 00:40:22.988973 1, 0xFFFF, sum = 0
2679 00:40:22.989025 2, 0xFFFF, sum = 0
2680 00:40:22.989077 3, 0xFFFF, sum = 0
2681 00:40:22.989128 4, 0xFFFF, sum = 0
2682 00:40:22.989180 5, 0xFFFF, sum = 0
2683 00:40:22.989232 6, 0xFFFF, sum = 0
2684 00:40:22.989314 7, 0xFFFF, sum = 0
2685 00:40:22.989380 8, 0xFFFF, sum = 0
2686 00:40:22.989431 9, 0xFFFF, sum = 0
2687 00:40:22.989483 10, 0xFFFF, sum = 0
2688 00:40:22.989536 11, 0xFFFF, sum = 0
2689 00:40:22.989587 12, 0x0, sum = 1
2690 00:40:22.989640 13, 0x0, sum = 2
2691 00:40:22.989697 14, 0x0, sum = 3
2692 00:40:22.989750 15, 0x0, sum = 4
2693 00:40:22.989801 best_step = 13
2694 00:40:22.989852
2695 00:40:22.989904 ==
2696 00:40:22.989955 Dram Type= 6, Freq= 0, CH_0, rank 0
2697 00:40:22.990015 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2698 00:40:22.990067 ==
2699 00:40:22.990119 RX Vref Scan: 1
2700 00:40:22.990170
2701 00:40:22.990221 Set Vref Range= 32 -> 127
2702 00:40:22.990272
2703 00:40:22.990323 RX Vref 32 -> 127, step: 1
2704 00:40:22.990374
2705 00:40:22.990424 RX Delay -21 -> 252, step: 4
2706 00:40:22.990475
2707 00:40:22.990525 Set Vref, RX VrefLevel [Byte0]: 32
2708 00:40:22.990577 [Byte1]: 32
2709 00:40:22.990628
2710 00:40:22.990679 Set Vref, RX VrefLevel [Byte0]: 33
2711 00:40:22.990730 [Byte1]: 33
2712 00:40:22.990782
2713 00:40:22.990833 Set Vref, RX VrefLevel [Byte0]: 34
2714 00:40:22.990883 [Byte1]: 34
2715 00:40:22.990939
2716 00:40:22.991000 Set Vref, RX VrefLevel [Byte0]: 35
2717 00:40:22.991083 [Byte1]: 35
2718 00:40:22.991208
2719 00:40:22.991347 Set Vref, RX VrefLevel [Byte0]: 36
2720 00:40:22.991410 [Byte1]: 36
2721 00:40:22.991463
2722 00:40:22.991516 Set Vref, RX VrefLevel [Byte0]: 37
2723 00:40:22.991568 [Byte1]: 37
2724 00:40:22.991620
2725 00:40:22.991672 Set Vref, RX VrefLevel [Byte0]: 38
2726 00:40:22.991768 [Byte1]: 38
2727 00:40:22.991829
2728 00:40:22.991884 Set Vref, RX VrefLevel [Byte0]: 39
2729 00:40:22.991936 [Byte1]: 39
2730 00:40:22.991987
2731 00:40:22.992038 Set Vref, RX VrefLevel [Byte0]: 40
2732 00:40:22.992090 [Byte1]: 40
2733 00:40:22.992140
2734 00:40:22.992209 Set Vref, RX VrefLevel [Byte0]: 41
2735 00:40:22.992264 [Byte1]: 41
2736 00:40:22.992346
2737 00:40:22.992524 Set Vref, RX VrefLevel [Byte0]: 42
2738 00:40:22.992625 [Byte1]: 42
2739 00:40:22.992689
2740 00:40:22.992756 Set Vref, RX VrefLevel [Byte0]: 43
2741 00:40:22.992810 [Byte1]: 43
2742 00:40:22.992862
2743 00:40:22.992914 Set Vref, RX VrefLevel [Byte0]: 44
2744 00:40:22.992967 [Byte1]: 44
2745 00:40:22.993019
2746 00:40:22.993070 Set Vref, RX VrefLevel [Byte0]: 45
2747 00:40:22.993122 [Byte1]: 45
2748 00:40:22.993173
2749 00:40:22.993224 Set Vref, RX VrefLevel [Byte0]: 46
2750 00:40:22.993303 [Byte1]: 46
2751 00:40:22.993369
2752 00:40:22.993421 Set Vref, RX VrefLevel [Byte0]: 47
2753 00:40:22.993472 [Byte1]: 47
2754 00:40:22.993523
2755 00:40:22.993574 Set Vref, RX VrefLevel [Byte0]: 48
2756 00:40:22.993635 [Byte1]: 48
2757 00:40:22.993689
2758 00:40:22.993750 Set Vref, RX VrefLevel [Byte0]: 49
2759 00:40:22.993804 [Byte1]: 49
2760 00:40:22.993856
2761 00:40:22.993907 Set Vref, RX VrefLevel [Byte0]: 50
2762 00:40:22.993958 [Byte1]: 50
2763 00:40:22.994010
2764 00:40:22.994061 Set Vref, RX VrefLevel [Byte0]: 51
2765 00:40:22.994113 [Byte1]: 51
2766 00:40:22.994164
2767 00:40:22.994215 Set Vref, RX VrefLevel [Byte0]: 52
2768 00:40:22.994266 [Byte1]: 52
2769 00:40:22.994326
2770 00:40:22.994379 Set Vref, RX VrefLevel [Byte0]: 53
2771 00:40:22.994430 [Byte1]: 53
2772 00:40:22.994481
2773 00:40:22.994532 Set Vref, RX VrefLevel [Byte0]: 54
2774 00:40:22.994584 [Byte1]: 54
2775 00:40:22.994636
2776 00:40:22.994686 Set Vref, RX VrefLevel [Byte0]: 55
2777 00:40:22.994739 [Byte1]: 55
2778 00:40:22.994790
2779 00:40:22.994841 Set Vref, RX VrefLevel [Byte0]: 56
2780 00:40:22.994892 [Byte1]: 56
2781 00:40:22.994943
2782 00:40:22.994994 Set Vref, RX VrefLevel [Byte0]: 57
2783 00:40:22.995045 [Byte1]: 57
2784 00:40:22.995095
2785 00:40:22.995146 Set Vref, RX VrefLevel [Byte0]: 58
2786 00:40:22.995198 [Byte1]: 58
2787 00:40:22.995308
2788 00:40:22.995648 Set Vref, RX VrefLevel [Byte0]: 59
2789 00:40:22.995719 [Byte1]: 59
2790 00:40:22.995837
2791 00:40:22.995921 Set Vref, RX VrefLevel [Byte0]: 60
2792 00:40:22.996003 [Byte1]: 60
2793 00:40:22.996083
2794 00:40:22.996164 Set Vref, RX VrefLevel [Byte0]: 61
2795 00:40:22.996275 [Byte1]: 61
2796 00:40:22.996355
2797 00:40:22.996439 Set Vref, RX VrefLevel [Byte0]: 62
2798 00:40:22.996504 [Byte1]: 62
2799 00:40:22.996593
2800 00:40:22.996676 Set Vref, RX VrefLevel [Byte0]: 63
2801 00:40:22.996770 [Byte1]: 63
2802 00:40:22.996836
2803 00:40:22.996890 Set Vref, RX VrefLevel [Byte0]: 64
2804 00:40:22.996942 [Byte1]: 64
2805 00:40:22.996995
2806 00:40:22.997047 Set Vref, RX VrefLevel [Byte0]: 65
2807 00:40:22.997099 [Byte1]: 65
2808 00:40:22.997150
2809 00:40:22.997201 Set Vref, RX VrefLevel [Byte0]: 66
2810 00:40:22.997253 [Byte1]: 66
2811 00:40:22.997379
2812 00:40:22.997431 Set Vref, RX VrefLevel [Byte0]: 67
2813 00:40:22.997483 [Byte1]: 67
2814 00:40:22.997534
2815 00:40:22.997586 Set Vref, RX VrefLevel [Byte0]: 68
2816 00:40:22.997637 [Byte1]: 68
2817 00:40:22.997690
2818 00:40:22.997759 Set Vref, RX VrefLevel [Byte0]: 69
2819 00:40:22.997814 [Byte1]: 69
2820 00:40:22.997866
2821 00:40:22.997916 Set Vref, RX VrefLevel [Byte0]: 70
2822 00:40:22.997968 [Byte1]: 70
2823 00:40:22.998019
2824 00:40:22.998070 Final RX Vref Byte 0 = 53 to rank0
2825 00:40:22.998123 Final RX Vref Byte 1 = 58 to rank0
2826 00:40:22.998174 Final RX Vref Byte 0 = 53 to rank1
2827 00:40:22.998226 Final RX Vref Byte 1 = 58 to rank1==
2828 00:40:22.998278 Dram Type= 6, Freq= 0, CH_0, rank 0
2829 00:40:22.998329 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2830 00:40:22.998381 ==
2831 00:40:22.998433 DQS Delay:
2832 00:40:22.998484 DQS0 = 0, DQS1 = 0
2833 00:40:22.998535 DQM Delay:
2834 00:40:22.998586 DQM0 = 117, DQM1 = 105
2835 00:40:22.998637 DQ Delay:
2836 00:40:22.998688 DQ0 =118, DQ1 =116, DQ2 =114, DQ3 =114
2837 00:40:22.998739 DQ4 =118, DQ5 =110, DQ6 =124, DQ7 =122
2838 00:40:22.998790 DQ8 =94, DQ9 =90, DQ10 =106, DQ11 =100
2839 00:40:22.998841 DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =114
2840 00:40:22.998892
2841 00:40:22.998942
2842 00:40:22.998993 [DQSOSCAuto] RK0, (LSB)MR18= 0x601, (MSB)MR19= 0x404, tDQSOscB0 = 409 ps tDQSOscB1 = 407 ps
2843 00:40:22.999046 CH0 RK0: MR19=404, MR18=601
2844 00:40:22.999097 CH0_RK0: MR19=0x404, MR18=0x601, DQSOSC=407, MR23=63, INC=39, DEC=26
2845 00:40:22.999150
2846 00:40:22.999201 ----->DramcWriteLeveling(PI) begin...
2847 00:40:22.999253 ==
2848 00:40:22.999305 Dram Type= 6, Freq= 0, CH_0, rank 1
2849 00:40:22.999356 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2850 00:40:22.999413 ==
2851 00:40:22.999486 Write leveling (Byte 0): 31 => 31
2852 00:40:22.999539 Write leveling (Byte 1): 26 => 26
2853 00:40:22.999591 DramcWriteLeveling(PI) end<-----
2854 00:40:22.999643
2855 00:40:22.999701 ==
2856 00:40:22.999756 Dram Type= 6, Freq= 0, CH_0, rank 1
2857 00:40:22.999807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2858 00:40:22.999860 ==
2859 00:40:22.999911 [Gating] SW mode calibration
2860 00:40:22.999964 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2861 00:40:23.000016 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2862 00:40:23.000068 0 15 0 | B1->B0 | 2626 3434 | 1 1 | (0 0) (1 1)
2863 00:40:23.000120 0 15 4 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
2864 00:40:23.000171 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2865 00:40:23.000222 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2866 00:40:23.000273 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2867 00:40:23.000324 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2868 00:40:23.000375 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2869 00:40:23.000426 0 15 28 | B1->B0 | 3434 2323 | 0 0 | (0 0) (0 0)
2870 00:40:23.000477 1 0 0 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
2871 00:40:23.000528 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2872 00:40:23.000580 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2873 00:40:23.000631 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2874 00:40:23.000682 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2875 00:40:23.000734 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2876 00:40:23.000784 1 0 24 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2877 00:40:23.000835 1 0 28 | B1->B0 | 3030 4646 | 0 0 | (1 1) (0 0)
2878 00:40:23.000886 1 1 0 | B1->B0 | 3d3d 4646 | 1 0 | (0 0) (0 0)
2879 00:40:23.000937 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2880 00:40:23.000988 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2881 00:40:23.001039 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2882 00:40:23.001090 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2883 00:40:23.001141 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2884 00:40:23.001192 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2885 00:40:23.001243 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
2886 00:40:23.001337 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2887 00:40:23.001389 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2888 00:40:23.001440 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2889 00:40:23.001492 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2890 00:40:23.001577 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2891 00:40:23.001658 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2892 00:40:23.001747 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2893 00:40:23.001873 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2894 00:40:23.002015 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2895 00:40:23.002127 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2896 00:40:23.002217 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2897 00:40:23.002306 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2898 00:40:23.002363 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2899 00:40:23.002416 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2900 00:40:23.002469 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2901 00:40:23.002726 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2902 00:40:23.002784 Total UI for P1: 0, mck2ui 16
2903 00:40:23.002846 best dqsien dly found for B0: ( 1, 3, 22)
2904 00:40:23.002900 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2905 00:40:23.002953 Total UI for P1: 0, mck2ui 16
2906 00:40:23.003005 best dqsien dly found for B1: ( 1, 3, 28)
2907 00:40:23.003057 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
2908 00:40:23.003109 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2909 00:40:23.003161
2910 00:40:23.003212 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
2911 00:40:23.003264 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2912 00:40:23.003316 [Gating] SW calibration Done
2913 00:40:23.003367 ==
2914 00:40:23.003418 Dram Type= 6, Freq= 0, CH_0, rank 1
2915 00:40:23.003470 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2916 00:40:23.003522 ==
2917 00:40:23.003573 RX Vref Scan: 0
2918 00:40:23.003623
2919 00:40:23.003674 RX Vref 0 -> 0, step: 1
2920 00:40:23.003725
2921 00:40:23.003776 RX Delay -40 -> 252, step: 8
2922 00:40:23.003827 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2923 00:40:23.003877 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2924 00:40:23.003929 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2925 00:40:23.003980 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2926 00:40:23.004032 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2927 00:40:23.004082 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2928 00:40:23.004207 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2929 00:40:23.004332 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
2930 00:40:23.004419 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2931 00:40:23.004475 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2932 00:40:23.004528 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2933 00:40:23.004580 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2934 00:40:23.004631 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2935 00:40:23.004683 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2936 00:40:23.004734 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2937 00:40:23.004785 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2938 00:40:23.004836 ==
2939 00:40:23.004887 Dram Type= 6, Freq= 0, CH_0, rank 1
2940 00:40:23.004939 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2941 00:40:23.004990 ==
2942 00:40:23.005041 DQS Delay:
2943 00:40:23.005092 DQS0 = 0, DQS1 = 0
2944 00:40:23.005143 DQM Delay:
2945 00:40:23.005194 DQM0 = 115, DQM1 = 109
2946 00:40:23.005246 DQ Delay:
2947 00:40:23.005346 DQ0 =111, DQ1 =119, DQ2 =111, DQ3 =111
2948 00:40:23.005398 DQ4 =119, DQ5 =103, DQ6 =127, DQ7 =119
2949 00:40:23.005450 DQ8 =99, DQ9 =91, DQ10 =111, DQ11 =103
2950 00:40:23.005501 DQ12 =115, DQ13 =119, DQ14 =119, DQ15 =115
2951 00:40:23.005552
2952 00:40:23.005603
2953 00:40:23.005654 ==
2954 00:40:23.005706 Dram Type= 6, Freq= 0, CH_0, rank 1
2955 00:40:23.005757 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2956 00:40:23.005809 ==
2957 00:40:23.005860
2958 00:40:23.005911
2959 00:40:23.005961 TX Vref Scan disable
2960 00:40:23.006012 == TX Byte 0 ==
2961 00:40:23.006062 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2962 00:40:23.006114 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2963 00:40:23.006165 == TX Byte 1 ==
2964 00:40:23.006216 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2965 00:40:23.006268 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2966 00:40:23.006319 ==
2967 00:40:23.006369 Dram Type= 6, Freq= 0, CH_0, rank 1
2968 00:40:23.006426 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2969 00:40:23.006481 ==
2970 00:40:23.006532 TX Vref=22, minBit 3, minWin=25, winSum=415
2971 00:40:23.136438 TX Vref=24, minBit 13, minWin=25, winSum=420
2972 00:40:23.136578 TX Vref=26, minBit 12, minWin=25, winSum=421
2973 00:40:23.136641 TX Vref=28, minBit 2, minWin=26, winSum=427
2974 00:40:23.136700 TX Vref=30, minBit 0, minWin=26, winSum=421
2975 00:40:23.136758 TX Vref=32, minBit 0, minWin=26, winSum=424
2976 00:40:23.136812 [TxChooseVref] Worse bit 2, Min win 26, Win sum 427, Final Vref 28
2977 00:40:23.136867
2978 00:40:23.136920 Final TX Range 1 Vref 28
2979 00:40:23.136973
2980 00:40:23.137025 ==
2981 00:40:23.137078 Dram Type= 6, Freq= 0, CH_0, rank 1
2982 00:40:23.137130 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2983 00:40:23.137184 ==
2984 00:40:23.137236
2985 00:40:23.137339
2986 00:40:23.137393 TX Vref Scan disable
2987 00:40:23.137446 == TX Byte 0 ==
2988 00:40:23.137498 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2989 00:40:23.137550 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2990 00:40:23.137602 == TX Byte 1 ==
2991 00:40:23.137653 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2992 00:40:23.137704 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2993 00:40:23.137756
2994 00:40:23.137807 [DATLAT]
2995 00:40:23.137859 Freq=1200, CH0 RK1
2996 00:40:23.137911
2997 00:40:23.137962 DATLAT Default: 0xd
2998 00:40:23.138014 0, 0xFFFF, sum = 0
2999 00:40:23.138067 1, 0xFFFF, sum = 0
3000 00:40:23.138128 2, 0xFFFF, sum = 0
3001 00:40:23.138183 3, 0xFFFF, sum = 0
3002 00:40:23.138235 4, 0xFFFF, sum = 0
3003 00:40:23.138288 5, 0xFFFF, sum = 0
3004 00:40:23.138339 6, 0xFFFF, sum = 0
3005 00:40:23.138392 7, 0xFFFF, sum = 0
3006 00:40:23.138444 8, 0xFFFF, sum = 0
3007 00:40:23.138495 9, 0xFFFF, sum = 0
3008 00:40:23.138548 10, 0xFFFF, sum = 0
3009 00:40:23.138600 11, 0xFFFF, sum = 0
3010 00:40:23.138651 12, 0x0, sum = 1
3011 00:40:23.138703 13, 0x0, sum = 2
3012 00:40:23.138754 14, 0x0, sum = 3
3013 00:40:23.138806 15, 0x0, sum = 4
3014 00:40:23.138858 best_step = 13
3015 00:40:23.138909
3016 00:40:23.138959 ==
3017 00:40:23.139011 Dram Type= 6, Freq= 0, CH_0, rank 1
3018 00:40:23.139062 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3019 00:40:23.139114 ==
3020 00:40:23.139164 RX Vref Scan: 0
3021 00:40:23.139215
3022 00:40:23.139266 RX Vref 0 -> 0, step: 1
3023 00:40:23.139317
3024 00:40:23.139368 RX Delay -21 -> 252, step: 4
3025 00:40:23.139420 iDelay=195, Bit 0, Center 112 (47 ~ 178) 132
3026 00:40:23.139472 iDelay=195, Bit 1, Center 116 (47 ~ 186) 140
3027 00:40:23.139523 iDelay=195, Bit 2, Center 110 (43 ~ 178) 136
3028 00:40:23.139575 iDelay=195, Bit 3, Center 112 (47 ~ 178) 132
3029 00:40:23.139626 iDelay=195, Bit 4, Center 118 (51 ~ 186) 136
3030 00:40:23.139678 iDelay=195, Bit 5, Center 108 (43 ~ 174) 132
3031 00:40:23.139729 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3032 00:40:23.139780 iDelay=195, Bit 7, Center 122 (55 ~ 190) 136
3033 00:40:23.139831 iDelay=195, Bit 8, Center 94 (27 ~ 162) 136
3034 00:40:23.139882 iDelay=195, Bit 9, Center 92 (27 ~ 158) 132
3035 00:40:23.139940 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
3036 00:40:23.140056 iDelay=195, Bit 11, Center 100 (31 ~ 170) 140
3037 00:40:23.140144 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
3038 00:40:23.140237 iDelay=195, Bit 13, Center 110 (43 ~ 178) 136
3039 00:40:23.140564 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3040 00:40:23.140686 iDelay=195, Bit 15, Center 112 (47 ~ 178) 132
3041 00:40:23.140791 ==
3042 00:40:23.140897 Dram Type= 6, Freq= 0, CH_0, rank 1
3043 00:40:23.141001 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3044 00:40:23.141098 ==
3045 00:40:23.141194 DQS Delay:
3046 00:40:23.141264 DQS0 = 0, DQS1 = 0
3047 00:40:23.141333 DQM Delay:
3048 00:40:23.141417 DQM0 = 115, DQM1 = 106
3049 00:40:23.141498 DQ Delay:
3050 00:40:23.141580 DQ0 =112, DQ1 =116, DQ2 =110, DQ3 =112
3051 00:40:23.141661 DQ4 =118, DQ5 =108, DQ6 =126, DQ7 =122
3052 00:40:23.141742 DQ8 =94, DQ9 =92, DQ10 =110, DQ11 =100
3053 00:40:23.141822 DQ12 =112, DQ13 =110, DQ14 =118, DQ15 =112
3054 00:40:23.141902
3055 00:40:23.141982
3056 00:40:23.142064 [DQSOSCAuto] RK1, (LSB)MR18= 0x1ff, (MSB)MR19= 0x403, tDQSOscB0 = 410 ps tDQSOscB1 = 409 ps
3057 00:40:23.142146 CH0 RK1: MR19=403, MR18=1FF
3058 00:40:23.142228 CH0_RK1: MR19=0x403, MR18=0x1FF, DQSOSC=409, MR23=63, INC=39, DEC=26
3059 00:40:23.142309 [RxdqsGatingPostProcess] freq 1200
3060 00:40:23.142391 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3061 00:40:23.142472 best DQS0 dly(2T, 0.5T) = (0, 11)
3062 00:40:23.142553 best DQS1 dly(2T, 0.5T) = (0, 12)
3063 00:40:23.142633 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3064 00:40:23.142714 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3065 00:40:23.142795 best DQS0 dly(2T, 0.5T) = (0, 11)
3066 00:40:23.142875 best DQS1 dly(2T, 0.5T) = (0, 11)
3067 00:40:23.142956 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3068 00:40:23.143036 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3069 00:40:23.143117 Pre-setting of DQS Precalculation
3070 00:40:23.143198 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3071 00:40:23.143279 ==
3072 00:40:23.143360 Dram Type= 6, Freq= 0, CH_1, rank 0
3073 00:40:23.143441 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3074 00:40:23.143522 ==
3075 00:40:23.143603 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3076 00:40:23.143685 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3077 00:40:23.143749 [CA 0] Center 37 (7~68) winsize 62
3078 00:40:23.143803 [CA 1] Center 37 (7~68) winsize 62
3079 00:40:23.143854 [CA 2] Center 35 (5~65) winsize 61
3080 00:40:23.143906 [CA 3] Center 34 (4~64) winsize 61
3081 00:40:23.143958 [CA 4] Center 35 (5~65) winsize 61
3082 00:40:23.144009 [CA 5] Center 33 (4~63) winsize 60
3083 00:40:23.144061
3084 00:40:23.144112 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3085 00:40:23.144164
3086 00:40:23.144215 [CATrainingPosCal] consider 1 rank data
3087 00:40:23.144267 u2DelayCellTimex100 = 270/100 ps
3088 00:40:23.144319 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3089 00:40:23.144371 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3090 00:40:23.144423 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3091 00:40:23.144475 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3092 00:40:23.144527 CA4 delay=35 (5~65),Diff = 2 PI (9 cell)
3093 00:40:23.144578 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3094 00:40:23.144629
3095 00:40:23.144681 CA PerBit enable=1, Macro0, CA PI delay=33
3096 00:40:23.144742
3097 00:40:23.144795 [CBTSetCACLKResult] CA Dly = 33
3098 00:40:23.144848 CS Dly: 5 (0~36)
3099 00:40:23.144908 ==
3100 00:40:23.145002 Dram Type= 6, Freq= 0, CH_1, rank 1
3101 00:40:23.145094 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3102 00:40:23.145207 ==
3103 00:40:23.145309 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3104 00:40:23.145365 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3105 00:40:23.145419 [CA 0] Center 37 (7~68) winsize 62
3106 00:40:23.145472 [CA 1] Center 38 (8~68) winsize 61
3107 00:40:23.145525 [CA 2] Center 34 (4~65) winsize 62
3108 00:40:23.145578 [CA 3] Center 34 (4~64) winsize 61
3109 00:40:23.145630 [CA 4] Center 34 (4~64) winsize 61
3110 00:40:23.145681 [CA 5] Center 33 (3~63) winsize 61
3111 00:40:23.145741
3112 00:40:23.145794 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3113 00:40:23.145846
3114 00:40:23.145898 [CATrainingPosCal] consider 2 rank data
3115 00:40:23.145950 u2DelayCellTimex100 = 270/100 ps
3116 00:40:23.146002 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3117 00:40:23.146054 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3118 00:40:23.146106 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3119 00:40:23.146158 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3120 00:40:23.146209 CA4 delay=34 (5~64),Diff = 1 PI (4 cell)
3121 00:40:23.146260 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3122 00:40:23.146312
3123 00:40:23.146363 CA PerBit enable=1, Macro0, CA PI delay=33
3124 00:40:23.146416
3125 00:40:23.146467 [CBTSetCACLKResult] CA Dly = 33
3126 00:40:23.146518 CS Dly: 6 (0~39)
3127 00:40:23.146569
3128 00:40:23.146621 ----->DramcWriteLeveling(PI) begin...
3129 00:40:23.146674 ==
3130 00:40:23.146725 Dram Type= 6, Freq= 0, CH_1, rank 0
3131 00:40:23.146777 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3132 00:40:23.146829 ==
3133 00:40:23.146881 Write leveling (Byte 0): 27 => 27
3134 00:40:23.146933 Write leveling (Byte 1): 29 => 29
3135 00:40:23.146985 DramcWriteLeveling(PI) end<-----
3136 00:40:23.147037
3137 00:40:23.147088 ==
3138 00:40:23.147139 Dram Type= 6, Freq= 0, CH_1, rank 0
3139 00:40:23.147191 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3140 00:40:23.147243 ==
3141 00:40:23.147295 [Gating] SW mode calibration
3142 00:40:23.147347 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3143 00:40:23.147399 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3144 00:40:23.147452 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3145 00:40:23.147504 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3146 00:40:23.147556 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3147 00:40:23.147608 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3148 00:40:23.147660 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3149 00:40:23.147728 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3150 00:40:23.147815 0 15 24 | B1->B0 | 3434 3030 | 1 1 | (1 0) (1 0)
3151 00:40:23.147897 0 15 28 | B1->B0 | 2d2d 2323 | 0 0 | (0 1) (1 0)
3152 00:40:23.147951 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3153 00:40:23.148003 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3154 00:40:23.148055 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3155 00:40:23.148107 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3156 00:40:23.148160 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3157 00:40:23.148420 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3158 00:40:23.148513 1 0 24 | B1->B0 | 2726 3434 | 1 0 | (0 0) (0 0)
3159 00:40:23.148614 1 0 28 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
3160 00:40:23.148697 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3161 00:40:23.148779 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3162 00:40:23.148860 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3163 00:40:23.148941 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3164 00:40:23.149022 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3165 00:40:23.149103 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3166 00:40:23.149184 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3167 00:40:23.149347 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3168 00:40:23.149439 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3169 00:40:23.149587 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3170 00:40:23.149670 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3171 00:40:23.149751 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3172 00:40:23.149836 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3173 00:40:23.149903 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3174 00:40:23.150017 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3175 00:40:23.150127 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3176 00:40:23.150222 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3177 00:40:23.150336 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3178 00:40:23.150402 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3179 00:40:23.150458 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3180 00:40:23.150512 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3181 00:40:23.150565 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3182 00:40:23.150618 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3183 00:40:23.150685 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3184 00:40:23.150737 Total UI for P1: 0, mck2ui 16
3185 00:40:23.150790 best dqsien dly found for B0: ( 1, 3, 24)
3186 00:40:23.150842 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3187 00:40:23.150909 Total UI for P1: 0, mck2ui 16
3188 00:40:23.150977 best dqsien dly found for B1: ( 1, 3, 26)
3189 00:40:23.151028 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3190 00:40:23.151080 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3191 00:40:23.151132
3192 00:40:23.151183 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3193 00:40:23.151235 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3194 00:40:23.151293 [Gating] SW calibration Done
3195 00:40:23.151379 ==
3196 00:40:23.151432 Dram Type= 6, Freq= 0, CH_1, rank 0
3197 00:40:23.151484 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3198 00:40:23.151536 ==
3199 00:40:23.151588 RX Vref Scan: 0
3200 00:40:23.151639
3201 00:40:23.151690 RX Vref 0 -> 0, step: 1
3202 00:40:23.151741
3203 00:40:23.151793 RX Delay -40 -> 252, step: 8
3204 00:40:23.151851 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3205 00:40:23.151905 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3206 00:40:23.151957 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3207 00:40:23.152008 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3208 00:40:23.152060 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3209 00:40:23.152111 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3210 00:40:23.152162 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3211 00:40:23.152214 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3212 00:40:23.152265 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3213 00:40:23.152317 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
3214 00:40:23.152368 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3215 00:40:23.152420 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3216 00:40:23.152472 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3217 00:40:23.152523 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3218 00:40:23.152575 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3219 00:40:23.152626 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3220 00:40:23.152677 ==
3221 00:40:23.152728 Dram Type= 6, Freq= 0, CH_1, rank 0
3222 00:40:23.152780 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3223 00:40:23.152832 ==
3224 00:40:23.152883 DQS Delay:
3225 00:40:23.152935 DQS0 = 0, DQS1 = 0
3226 00:40:23.152986 DQM Delay:
3227 00:40:23.153038 DQM0 = 114, DQM1 = 112
3228 00:40:23.153089 DQ Delay:
3229 00:40:23.153141 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =115
3230 00:40:23.153192 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =111
3231 00:40:23.153243 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
3232 00:40:23.153346 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3233 00:40:23.153398
3234 00:40:23.153450
3235 00:40:23.153501 ==
3236 00:40:23.153552 Dram Type= 6, Freq= 0, CH_1, rank 0
3237 00:40:23.153604 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3238 00:40:23.153656 ==
3239 00:40:23.153708
3240 00:40:23.153759
3241 00:40:23.153811 TX Vref Scan disable
3242 00:40:23.153895 == TX Byte 0 ==
3243 00:40:23.153991 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3244 00:40:23.154062 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3245 00:40:23.154115 == TX Byte 1 ==
3246 00:40:23.154168 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3247 00:40:23.154220 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3248 00:40:23.154272 ==
3249 00:40:23.154344 Dram Type= 6, Freq= 0, CH_1, rank 0
3250 00:40:23.154403 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3251 00:40:23.154455 ==
3252 00:40:23.154570 TX Vref=22, minBit 3, minWin=25, winSum=412
3253 00:40:23.154639 TX Vref=24, minBit 1, minWin=25, winSum=420
3254 00:40:23.154742 TX Vref=26, minBit 1, minWin=26, winSum=426
3255 00:40:23.154811 TX Vref=28, minBit 3, minWin=26, winSum=428
3256 00:40:23.154863 TX Vref=30, minBit 2, minWin=26, winSum=430
3257 00:40:23.154915 TX Vref=32, minBit 2, minWin=26, winSum=427
3258 00:40:23.154968 [TxChooseVref] Worse bit 2, Min win 26, Win sum 430, Final Vref 30
3259 00:40:23.155024
3260 00:40:23.155078 Final TX Range 1 Vref 30
3261 00:40:23.155149
3262 00:40:23.155207 ==
3263 00:40:23.155261 Dram Type= 6, Freq= 0, CH_1, rank 0
3264 00:40:23.155313 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3265 00:40:23.155366 ==
3266 00:40:23.155418
3267 00:40:23.155469
3268 00:40:23.155520 TX Vref Scan disable
3269 00:40:23.155572 == TX Byte 0 ==
3270 00:40:23.155631 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3271 00:40:23.155724 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3272 00:40:23.155817 == TX Byte 1 ==
3273 00:40:23.156137 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3274 00:40:23.156202 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3275 00:40:23.156259
3276 00:40:23.156313 [DATLAT]
3277 00:40:23.156366 Freq=1200, CH1 RK0
3278 00:40:23.156419
3279 00:40:23.156471 DATLAT Default: 0xd
3280 00:40:23.156569 0, 0xFFFF, sum = 0
3281 00:40:23.156623 1, 0xFFFF, sum = 0
3282 00:40:23.156676 2, 0xFFFF, sum = 0
3283 00:40:23.156728 3, 0xFFFF, sum = 0
3284 00:40:23.156781 4, 0xFFFF, sum = 0
3285 00:40:23.156833 5, 0xFFFF, sum = 0
3286 00:40:23.156885 6, 0xFFFF, sum = 0
3287 00:40:23.156938 7, 0xFFFF, sum = 0
3288 00:40:23.156991 8, 0xFFFF, sum = 0
3289 00:40:23.157043 9, 0xFFFF, sum = 0
3290 00:40:23.157096 10, 0xFFFF, sum = 0
3291 00:40:23.157148 11, 0xFFFF, sum = 0
3292 00:40:23.157199 12, 0x0, sum = 1
3293 00:40:23.157252 13, 0x0, sum = 2
3294 00:40:23.157348 14, 0x0, sum = 3
3295 00:40:23.157401 15, 0x0, sum = 4
3296 00:40:23.157472 best_step = 13
3297 00:40:23.157525
3298 00:40:23.157647 ==
3299 00:40:23.157700 Dram Type= 6, Freq= 0, CH_1, rank 0
3300 00:40:23.157752 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3301 00:40:23.157804 ==
3302 00:40:23.157856 RX Vref Scan: 1
3303 00:40:23.157908
3304 00:40:23.157959 Set Vref Range= 32 -> 127
3305 00:40:23.158018
3306 00:40:23.158123 RX Vref 32 -> 127, step: 1
3307 00:40:23.158238
3308 00:40:23.158290 RX Delay -13 -> 252, step: 4
3309 00:40:23.158341
3310 00:40:23.158392 Set Vref, RX VrefLevel [Byte0]: 32
3311 00:40:23.158444 [Byte1]: 32
3312 00:40:23.158496
3313 00:40:23.158547 Set Vref, RX VrefLevel [Byte0]: 33
3314 00:40:23.158600 [Byte1]: 33
3315 00:40:23.158651
3316 00:40:23.158702 Set Vref, RX VrefLevel [Byte0]: 34
3317 00:40:23.158754 [Byte1]: 34
3318 00:40:23.158806
3319 00:40:23.158857 Set Vref, RX VrefLevel [Byte0]: 35
3320 00:40:23.158908 [Byte1]: 35
3321 00:40:23.158960
3322 00:40:23.159011 Set Vref, RX VrefLevel [Byte0]: 36
3323 00:40:23.159063 [Byte1]: 36
3324 00:40:23.159115
3325 00:40:23.159166 Set Vref, RX VrefLevel [Byte0]: 37
3326 00:40:23.159218 [Byte1]: 37
3327 00:40:23.159270
3328 00:40:23.159321 Set Vref, RX VrefLevel [Byte0]: 38
3329 00:40:23.159373 [Byte1]: 38
3330 00:40:23.159424
3331 00:40:23.159475 Set Vref, RX VrefLevel [Byte0]: 39
3332 00:40:23.159526 [Byte1]: 39
3333 00:40:23.159577
3334 00:40:23.159628 Set Vref, RX VrefLevel [Byte0]: 40
3335 00:40:23.159679 [Byte1]: 40
3336 00:40:23.159731
3337 00:40:23.159781 Set Vref, RX VrefLevel [Byte0]: 41
3338 00:40:23.159833 [Byte1]: 41
3339 00:40:23.159884
3340 00:40:23.159935 Set Vref, RX VrefLevel [Byte0]: 42
3341 00:40:23.159986 [Byte1]: 42
3342 00:40:23.160037
3343 00:40:23.160087 Set Vref, RX VrefLevel [Byte0]: 43
3344 00:40:23.160138 [Byte1]: 43
3345 00:40:23.160190
3346 00:40:23.160240 Set Vref, RX VrefLevel [Byte0]: 44
3347 00:40:23.160291 [Byte1]: 44
3348 00:40:23.160342
3349 00:40:23.160392 Set Vref, RX VrefLevel [Byte0]: 45
3350 00:40:23.160443 [Byte1]: 45
3351 00:40:23.160494
3352 00:40:23.160544 Set Vref, RX VrefLevel [Byte0]: 46
3353 00:40:23.160595 [Byte1]: 46
3354 00:40:23.160646
3355 00:40:23.160696 Set Vref, RX VrefLevel [Byte0]: 47
3356 00:40:23.160747 [Byte1]: 47
3357 00:40:23.160798
3358 00:40:23.160848 Set Vref, RX VrefLevel [Byte0]: 48
3359 00:40:23.160938 [Byte1]: 48
3360 00:40:23.161039
3361 00:40:23.161130 Set Vref, RX VrefLevel [Byte0]: 49
3362 00:40:23.161242 [Byte1]: 49
3363 00:40:23.161329
3364 00:40:23.161383 Set Vref, RX VrefLevel [Byte0]: 50
3365 00:40:23.161436 [Byte1]: 50
3366 00:40:23.161489
3367 00:40:23.161540 Set Vref, RX VrefLevel [Byte0]: 51
3368 00:40:23.161592 [Byte1]: 51
3369 00:40:23.161655
3370 00:40:23.161724 Set Vref, RX VrefLevel [Byte0]: 52
3371 00:40:23.161793 [Byte1]: 52
3372 00:40:23.161845
3373 00:40:23.161896 Set Vref, RX VrefLevel [Byte0]: 53
3374 00:40:23.161949 [Byte1]: 53
3375 00:40:23.162001
3376 00:40:23.162052 Set Vref, RX VrefLevel [Byte0]: 54
3377 00:40:23.162102 [Byte1]: 54
3378 00:40:23.162153
3379 00:40:23.162204 Set Vref, RX VrefLevel [Byte0]: 55
3380 00:40:23.162256 [Byte1]: 55
3381 00:40:23.162306
3382 00:40:23.162358 Set Vref, RX VrefLevel [Byte0]: 56
3383 00:40:23.162410 [Byte1]: 56
3384 00:40:23.162461
3385 00:40:23.162512 Set Vref, RX VrefLevel [Byte0]: 57
3386 00:40:23.162563 [Byte1]: 57
3387 00:40:23.162614
3388 00:40:23.162666 Set Vref, RX VrefLevel [Byte0]: 58
3389 00:40:23.162717 [Byte1]: 58
3390 00:40:23.162767
3391 00:40:23.162818 Set Vref, RX VrefLevel [Byte0]: 59
3392 00:40:23.162869 [Byte1]: 59
3393 00:40:23.162920
3394 00:40:23.162970 Set Vref, RX VrefLevel [Byte0]: 60
3395 00:40:23.163021 [Byte1]: 60
3396 00:40:23.163072
3397 00:40:23.163123 Set Vref, RX VrefLevel [Byte0]: 61
3398 00:40:23.163174 [Byte1]: 61
3399 00:40:23.163224
3400 00:40:23.163275 Set Vref, RX VrefLevel [Byte0]: 62
3401 00:40:23.163325 [Byte1]: 62
3402 00:40:23.163376
3403 00:40:23.163427 Set Vref, RX VrefLevel [Byte0]: 63
3404 00:40:23.163478 [Byte1]: 63
3405 00:40:23.163529
3406 00:40:23.163580 Set Vref, RX VrefLevel [Byte0]: 64
3407 00:40:23.163631 [Byte1]: 64
3408 00:40:23.163682
3409 00:40:23.163733 Final RX Vref Byte 0 = 51 to rank0
3410 00:40:23.163784 Final RX Vref Byte 1 = 53 to rank0
3411 00:40:23.163836 Final RX Vref Byte 0 = 51 to rank1
3412 00:40:23.163887 Final RX Vref Byte 1 = 53 to rank1==
3413 00:40:23.163938 Dram Type= 6, Freq= 0, CH_1, rank 0
3414 00:40:23.163989 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3415 00:40:23.164041 ==
3416 00:40:23.164094 DQS Delay:
3417 00:40:23.164144 DQS0 = 0, DQS1 = 0
3418 00:40:23.164196 DQM Delay:
3419 00:40:23.164246 DQM0 = 114, DQM1 = 113
3420 00:40:23.164297 DQ Delay:
3421 00:40:23.164372 DQ0 =120, DQ1 =110, DQ2 =106, DQ3 =114
3422 00:40:23.164487 DQ4 =110, DQ5 =122, DQ6 =124, DQ7 =110
3423 00:40:23.164568 DQ8 =98, DQ9 =104, DQ10 =114, DQ11 =106
3424 00:40:23.164648 DQ12 =122, DQ13 =120, DQ14 =120, DQ15 =120
3425 00:40:23.164728
3426 00:40:23.164807
3427 00:40:23.164888 [DQSOSCAuto] RK0, (LSB)MR18= 0xf804, (MSB)MR19= 0x304, tDQSOscB0 = 408 ps tDQSOscB1 = 413 ps
3428 00:40:23.164970 CH1 RK0: MR19=304, MR18=F804
3429 00:40:23.165051 CH1_RK0: MR19=0x304, MR18=0xF804, DQSOSC=408, MR23=63, INC=39, DEC=26
3430 00:40:23.165131
3431 00:40:23.165211 ----->DramcWriteLeveling(PI) begin...
3432 00:40:23.165311 ==
3433 00:40:23.165378 Dram Type= 6, Freq= 0, CH_1, rank 1
3434 00:40:23.165430 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3435 00:40:23.165482 ==
3436 00:40:23.165533 Write leveling (Byte 0): 26 => 26
3437 00:40:23.165585 Write leveling (Byte 1): 27 => 27
3438 00:40:23.165846 DramcWriteLeveling(PI) end<-----
3439 00:40:23.165905
3440 00:40:23.165957 ==
3441 00:40:23.166009 Dram Type= 6, Freq= 0, CH_1, rank 1
3442 00:40:23.166061 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3443 00:40:23.166117 ==
3444 00:40:23.166182 [Gating] SW mode calibration
3445 00:40:23.166272 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3446 00:40:23.166365 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3447 00:40:23.166459 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3448 00:40:23.166530 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3449 00:40:23.166583 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3450 00:40:23.166635 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3451 00:40:23.166687 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3452 00:40:23.166738 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3453 00:40:23.166790 0 15 24 | B1->B0 | 3434 2424 | 0 0 | (1 0) (0 0)
3454 00:40:23.166841 0 15 28 | B1->B0 | 2d2d 2323 | 1 0 | (1 0) (0 0)
3455 00:40:23.166895 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3456 00:40:23.166947 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3457 00:40:23.166998 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3458 00:40:23.167049 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3459 00:40:23.167100 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3460 00:40:23.167151 1 0 20 | B1->B0 | 2323 3030 | 0 1 | (0 0) (0 0)
3461 00:40:23.167202 1 0 24 | B1->B0 | 2525 4646 | 0 0 | (0 0) (0 0)
3462 00:40:23.167253 1 0 28 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
3463 00:40:23.167304 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3464 00:40:23.167356 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3465 00:40:23.167407 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3466 00:40:23.167458 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3467 00:40:23.167509 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3468 00:40:23.167560 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3469 00:40:23.167612 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3470 00:40:23.167662 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3471 00:40:23.167713 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3472 00:40:23.167765 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3473 00:40:23.167816 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3474 00:40:23.167867 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3475 00:40:23.167918 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3476 00:40:23.167969 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3477 00:40:23.168020 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3478 00:40:23.168071 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3479 00:40:23.168122 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3480 00:40:23.168173 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3481 00:40:23.168232 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3482 00:40:23.168284 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3483 00:40:23.168335 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3484 00:40:23.168386 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3485 00:40:23.168438 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3486 00:40:23.168489 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3487 00:40:23.168547 Total UI for P1: 0, mck2ui 16
3488 00:40:23.168678 best dqsien dly found for B0: ( 1, 3, 22)
3489 00:40:23.168804 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3490 00:40:23.168885 Total UI for P1: 0, mck2ui 16
3491 00:40:23.168966 best dqsien dly found for B1: ( 1, 3, 26)
3492 00:40:23.169046 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3493 00:40:23.169127 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3494 00:40:23.169206
3495 00:40:23.169329 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3496 00:40:23.169411 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3497 00:40:23.169491 [Gating] SW calibration Done
3498 00:40:23.169575 ==
3499 00:40:23.169636 Dram Type= 6, Freq= 0, CH_1, rank 1
3500 00:40:23.169689 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3501 00:40:23.169741 ==
3502 00:40:23.169792 RX Vref Scan: 0
3503 00:40:23.169843
3504 00:40:23.169895 RX Vref 0 -> 0, step: 1
3505 00:40:23.169946
3506 00:40:23.169997 RX Delay -40 -> 252, step: 8
3507 00:40:23.170066 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3508 00:40:23.170158 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3509 00:40:23.170236 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3510 00:40:23.170345 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3511 00:40:23.170413 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3512 00:40:23.170465 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3513 00:40:23.170517 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
3514 00:40:23.170569 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3515 00:40:23.170619 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3516 00:40:23.170679 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3517 00:40:23.170783 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3518 00:40:23.170837 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3519 00:40:23.170888 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3520 00:40:23.170953 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3521 00:40:23.171034 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3522 00:40:23.171116 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3523 00:40:23.171167 ==
3524 00:40:23.171218 Dram Type= 6, Freq= 0, CH_1, rank 1
3525 00:40:23.171270 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3526 00:40:23.171321 ==
3527 00:40:23.171374 DQS Delay:
3528 00:40:23.171425 DQS0 = 0, DQS1 = 0
3529 00:40:23.171475 DQM Delay:
3530 00:40:23.171531 DQM0 = 114, DQM1 = 111
3531 00:40:23.171595 DQ Delay:
3532 00:40:23.171690 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =111
3533 00:40:23.171782 DQ4 =115, DQ5 =123, DQ6 =119, DQ7 =111
3534 00:40:23.171904 DQ8 =99, DQ9 =99, DQ10 =111, DQ11 =107
3535 00:40:23.171988 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3536 00:40:23.172068
3537 00:40:23.172148
3538 00:40:23.172232 ==
3539 00:40:23.172320 Dram Type= 6, Freq= 0, CH_1, rank 1
3540 00:40:23.172409 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3541 00:40:23.172465 ==
3542 00:40:23.172517
3543 00:40:23.172569
3544 00:40:23.172620 TX Vref Scan disable
3545 00:40:23.172880 == TX Byte 0 ==
3546 00:40:23.172967 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3547 00:40:23.173050 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3548 00:40:23.173131 == TX Byte 1 ==
3549 00:40:23.173213 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3550 00:40:23.173330 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3551 00:40:23.173385 ==
3552 00:40:23.173437 Dram Type= 6, Freq= 0, CH_1, rank 1
3553 00:40:23.173490 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3554 00:40:23.173542 ==
3555 00:40:23.173595 TX Vref=22, minBit 8, minWin=25, winSum=416
3556 00:40:23.173646 TX Vref=24, minBit 9, minWin=25, winSum=422
3557 00:40:23.173698 TX Vref=26, minBit 9, minWin=25, winSum=426
3558 00:40:23.173750 TX Vref=28, minBit 9, minWin=25, winSum=425
3559 00:40:23.173802 TX Vref=30, minBit 2, minWin=26, winSum=428
3560 00:40:23.173853 TX Vref=32, minBit 9, minWin=25, winSum=426
3561 00:40:23.173904 [TxChooseVref] Worse bit 2, Min win 26, Win sum 428, Final Vref 30
3562 00:40:23.173956
3563 00:40:23.174007 Final TX Range 1 Vref 30
3564 00:40:23.174059
3565 00:40:23.174110 ==
3566 00:40:23.174161 Dram Type= 6, Freq= 0, CH_1, rank 1
3567 00:40:23.174230 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3568 00:40:23.174313 ==
3569 00:40:23.174393
3570 00:40:23.174478
3571 00:40:23.174593 TX Vref Scan disable
3572 00:40:23.174673 == TX Byte 0 ==
3573 00:40:23.174754 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3574 00:40:23.174835 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3575 00:40:23.174915 == TX Byte 1 ==
3576 00:40:23.174995 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3577 00:40:23.175076 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3578 00:40:23.175155
3579 00:40:23.175234 [DATLAT]
3580 00:40:23.175314 Freq=1200, CH1 RK1
3581 00:40:23.175394
3582 00:40:23.175473 DATLAT Default: 0xd
3583 00:40:23.175552 0, 0xFFFF, sum = 0
3584 00:40:23.175634 1, 0xFFFF, sum = 0
3585 00:40:23.175689 2, 0xFFFF, sum = 0
3586 00:40:23.175742 3, 0xFFFF, sum = 0
3587 00:40:23.175794 4, 0xFFFF, sum = 0
3588 00:40:23.175846 5, 0xFFFF, sum = 0
3589 00:40:23.175899 6, 0xFFFF, sum = 0
3590 00:40:23.175951 7, 0xFFFF, sum = 0
3591 00:40:23.176002 8, 0xFFFF, sum = 0
3592 00:40:23.176054 9, 0xFFFF, sum = 0
3593 00:40:23.176106 10, 0xFFFF, sum = 0
3594 00:40:23.176158 11, 0xFFFF, sum = 0
3595 00:40:23.176220 12, 0x0, sum = 1
3596 00:40:23.176284 13, 0x0, sum = 2
3597 00:40:23.176337 14, 0x0, sum = 3
3598 00:40:23.176390 15, 0x0, sum = 4
3599 00:40:23.176442 best_step = 13
3600 00:40:23.176492
3601 00:40:23.176543 ==
3602 00:40:23.176594 Dram Type= 6, Freq= 0, CH_1, rank 1
3603 00:40:23.176645 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3604 00:40:23.176697 ==
3605 00:40:23.176748 RX Vref Scan: 0
3606 00:40:23.176799
3607 00:40:23.176888 RX Vref 0 -> 0, step: 1
3608 00:40:23.176976
3609 00:40:23.177073 RX Delay -13 -> 252, step: 4
3610 00:40:23.177160 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3611 00:40:23.177242 iDelay=195, Bit 1, Center 110 (43 ~ 178) 136
3612 00:40:23.177361 iDelay=195, Bit 2, Center 108 (43 ~ 174) 132
3613 00:40:23.177443 iDelay=195, Bit 3, Center 112 (47 ~ 178) 132
3614 00:40:23.177525 iDelay=195, Bit 4, Center 114 (47 ~ 182) 136
3615 00:40:23.177605 iDelay=195, Bit 5, Center 124 (55 ~ 194) 140
3616 00:40:23.177686 iDelay=195, Bit 6, Center 122 (55 ~ 190) 136
3617 00:40:23.177766 iDelay=195, Bit 7, Center 114 (47 ~ 182) 136
3618 00:40:23.177820 iDelay=195, Bit 8, Center 100 (39 ~ 162) 124
3619 00:40:23.177872 iDelay=195, Bit 9, Center 104 (43 ~ 166) 124
3620 00:40:23.177923 iDelay=195, Bit 10, Center 114 (51 ~ 178) 128
3621 00:40:23.177984 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3622 00:40:23.178036 iDelay=195, Bit 12, Center 120 (59 ~ 182) 124
3623 00:40:23.178088 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3624 00:40:23.178139 iDelay=195, Bit 14, Center 116 (55 ~ 178) 124
3625 00:40:23.178196 iDelay=195, Bit 15, Center 122 (59 ~ 186) 128
3626 00:40:23.178254 ==
3627 00:40:23.178316 Dram Type= 6, Freq= 0, CH_1, rank 1
3628 00:40:23.178369 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3629 00:40:23.178421 ==
3630 00:40:23.178473 DQS Delay:
3631 00:40:23.178524 DQS0 = 0, DQS1 = 0
3632 00:40:23.178576 DQM Delay:
3633 00:40:23.178627 DQM0 = 115, DQM1 = 112
3634 00:40:23.178678 DQ Delay:
3635 00:40:23.178729 DQ0 =118, DQ1 =110, DQ2 =108, DQ3 =112
3636 00:40:23.178781 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =114
3637 00:40:23.178832 DQ8 =100, DQ9 =104, DQ10 =114, DQ11 =106
3638 00:40:23.178883 DQ12 =120, DQ13 =118, DQ14 =116, DQ15 =122
3639 00:40:23.178934
3640 00:40:23.178986
3641 00:40:23.179037 [DQSOSCAuto] RK1, (LSB)MR18= 0xf90b, (MSB)MR19= 0x304, tDQSOscB0 = 405 ps tDQSOscB1 = 412 ps
3642 00:40:23.179089 CH1 RK1: MR19=304, MR18=F90B
3643 00:40:23.179141 CH1_RK1: MR19=0x304, MR18=0xF90B, DQSOSC=405, MR23=63, INC=39, DEC=26
3644 00:40:23.179193 [RxdqsGatingPostProcess] freq 1200
3645 00:40:23.179245 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3646 00:40:23.179296 best DQS0 dly(2T, 0.5T) = (0, 11)
3647 00:40:23.179348 best DQS1 dly(2T, 0.5T) = (0, 11)
3648 00:40:23.179400 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3649 00:40:23.179451 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3650 00:40:23.179502 best DQS0 dly(2T, 0.5T) = (0, 11)
3651 00:40:23.179554 best DQS1 dly(2T, 0.5T) = (0, 11)
3652 00:40:23.179605 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3653 00:40:23.179656 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3654 00:40:23.179707 Pre-setting of DQS Precalculation
3655 00:40:23.179758 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3656 00:40:23.179811 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3657 00:40:23.179862 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3658 00:40:23.179914
3659 00:40:23.179965
3660 00:40:23.180016 [Calibration Summary] 2400 Mbps
3661 00:40:23.180067 CH 0, Rank 0
3662 00:40:23.180118 SW Impedance : PASS
3663 00:40:23.180169 DUTY Scan : NO K
3664 00:40:23.180228 ZQ Calibration : PASS
3665 00:40:23.180280 Jitter Meter : NO K
3666 00:40:23.180331 CBT Training : PASS
3667 00:40:23.180383 Write leveling : PASS
3668 00:40:23.180434 RX DQS gating : PASS
3669 00:40:23.180485 RX DQ/DQS(RDDQC) : PASS
3670 00:40:23.180537 TX DQ/DQS : PASS
3671 00:40:23.180588 RX DATLAT : PASS
3672 00:40:23.180639 RX DQ/DQS(Engine): PASS
3673 00:40:23.180690 TX OE : NO K
3674 00:40:23.180748 All Pass.
3675 00:40:23.180801
3676 00:40:23.180852 CH 0, Rank 1
3677 00:40:23.180903 SW Impedance : PASS
3678 00:40:23.180954 DUTY Scan : NO K
3679 00:40:23.181005 ZQ Calibration : PASS
3680 00:40:23.181056 Jitter Meter : NO K
3681 00:40:23.181107 CBT Training : PASS
3682 00:40:23.181158 Write leveling : PASS
3683 00:40:23.181209 RX DQS gating : PASS
3684 00:40:23.181471 RX DQ/DQS(RDDQC) : PASS
3685 00:40:23.181530 TX DQ/DQS : PASS
3686 00:40:23.181584 RX DATLAT : PASS
3687 00:40:23.181635 RX DQ/DQS(Engine): PASS
3688 00:40:23.181687 TX OE : NO K
3689 00:40:23.181739 All Pass.
3690 00:40:23.181790
3691 00:40:23.181841 CH 1, Rank 0
3692 00:40:23.181892 SW Impedance : PASS
3693 00:40:23.181944 DUTY Scan : NO K
3694 00:40:23.181996 ZQ Calibration : PASS
3695 00:40:23.182047 Jitter Meter : NO K
3696 00:40:23.182098 CBT Training : PASS
3697 00:40:23.182149 Write leveling : PASS
3698 00:40:23.182204 RX DQS gating : PASS
3699 00:40:23.182264 RX DQ/DQS(RDDQC) : PASS
3700 00:40:23.182347 TX DQ/DQS : PASS
3701 00:40:23.182428 RX DATLAT : PASS
3702 00:40:23.182489 RX DQ/DQS(Engine): PASS
3703 00:40:23.182577 TX OE : NO K
3704 00:40:23.182668 All Pass.
3705 00:40:23.182764
3706 00:40:23.182848 CH 1, Rank 1
3707 00:40:23.182930 SW Impedance : PASS
3708 00:40:23.183011 DUTY Scan : NO K
3709 00:40:23.183092 ZQ Calibration : PASS
3710 00:40:23.183172 Jitter Meter : NO K
3711 00:40:23.183252 CBT Training : PASS
3712 00:40:23.183332 Write leveling : PASS
3713 00:40:23.183412 RX DQS gating : PASS
3714 00:40:23.183492 RX DQ/DQS(RDDQC) : PASS
3715 00:40:23.183572 TX DQ/DQS : PASS
3716 00:40:23.183652 RX DATLAT : PASS
3717 00:40:23.183732 RX DQ/DQS(Engine): PASS
3718 00:40:23.183811 TX OE : NO K
3719 00:40:23.183891 All Pass.
3720 00:40:23.183971
3721 00:40:23.184050 DramC Write-DBI off
3722 00:40:23.184130 PER_BANK_REFRESH: Hybrid Mode
3723 00:40:23.184210 TX_TRACKING: ON
3724 00:40:23.184297 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3725 00:40:23.184380 [FAST_K] Save calibration result to emmc
3726 00:40:23.184462 dramc_set_vcore_voltage set vcore to 650000
3727 00:40:23.184542 Read voltage for 600, 5
3728 00:40:23.184622 Vio18 = 0
3729 00:40:23.184701 Vcore = 650000
3730 00:40:23.184781 Vdram = 0
3731 00:40:23.184860 Vddq = 0
3732 00:40:23.184939 Vmddr = 0
3733 00:40:23.185023 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3734 00:40:23.185105 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3735 00:40:23.185216 MEM_TYPE=3, freq_sel=19
3736 00:40:23.185323 sv_algorithm_assistance_LP4_1600
3737 00:40:23.185404 ============ PULL DRAM RESETB DOWN ============
3738 00:40:23.185490 ========== PULL DRAM RESETB DOWN end =========
3739 00:40:23.185581 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3740 00:40:23.185638 ===================================
3741 00:40:23.185712 LPDDR4 DRAM CONFIGURATION
3742 00:40:23.185781 ===================================
3743 00:40:23.185833 EX_ROW_EN[0] = 0x0
3744 00:40:23.185892 EX_ROW_EN[1] = 0x0
3745 00:40:23.185966 LP4Y_EN = 0x0
3746 00:40:23.186063 WORK_FSP = 0x0
3747 00:40:23.186156 WL = 0x2
3748 00:40:23.186238 RL = 0x2
3749 00:40:23.186294 BL = 0x2
3750 00:40:23.186366 RPST = 0x0
3751 00:40:23.186423 RD_PRE = 0x0
3752 00:40:23.186486 WR_PRE = 0x1
3753 00:40:23.186551 WR_PST = 0x0
3754 00:40:23.186606 DBI_WR = 0x0
3755 00:40:23.186657 DBI_RD = 0x0
3756 00:40:23.186708 OTF = 0x1
3757 00:40:23.186760 ===================================
3758 00:40:23.186813 ===================================
3759 00:40:23.186868 ANA top config
3760 00:40:23.186922 ===================================
3761 00:40:23.186982 DLL_ASYNC_EN = 0
3762 00:40:23.187050 ALL_SLAVE_EN = 1
3763 00:40:23.187102 NEW_RANK_MODE = 1
3764 00:40:23.187154 DLL_IDLE_MODE = 1
3765 00:40:23.187206 LP45_APHY_COMB_EN = 1
3766 00:40:23.187257 TX_ODT_DIS = 1
3767 00:40:23.187308 NEW_8X_MODE = 1
3768 00:40:23.187360 ===================================
3769 00:40:23.187418 ===================================
3770 00:40:23.187544 data_rate = 1200
3771 00:40:23.187598 CKR = 1
3772 00:40:23.187650 DQ_P2S_RATIO = 8
3773 00:40:23.187702 ===================================
3774 00:40:23.187754 CA_P2S_RATIO = 8
3775 00:40:23.187807 DQ_CA_OPEN = 0
3776 00:40:23.187858 DQ_SEMI_OPEN = 0
3777 00:40:23.187910 CA_SEMI_OPEN = 0
3778 00:40:23.187961 CA_FULL_RATE = 0
3779 00:40:23.188045 DQ_CKDIV4_EN = 1
3780 00:40:23.188126 CA_CKDIV4_EN = 1
3781 00:40:23.188208 CA_PREDIV_EN = 0
3782 00:40:23.188262 PH8_DLY = 0
3783 00:40:23.188314 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3784 00:40:23.188365 DQ_AAMCK_DIV = 4
3785 00:40:23.188416 CA_AAMCK_DIV = 4
3786 00:40:23.188468 CA_ADMCK_DIV = 4
3787 00:40:23.188519 DQ_TRACK_CA_EN = 0
3788 00:40:23.188570 CA_PICK = 600
3789 00:40:23.188621 CA_MCKIO = 600
3790 00:40:23.188673 MCKIO_SEMI = 0
3791 00:40:23.188724 PLL_FREQ = 2288
3792 00:40:23.188775 DQ_UI_PI_RATIO = 32
3793 00:40:23.188825 CA_UI_PI_RATIO = 0
3794 00:40:23.188880 ===================================
3795 00:40:23.188944 ===================================
3796 00:40:23.189045 memory_type:LPDDR4
3797 00:40:23.189142 GP_NUM : 10
3798 00:40:23.189228 SRAM_EN : 1
3799 00:40:23.189334 MD32_EN : 0
3800 00:40:23.189388 ===================================
3801 00:40:23.189440 [ANA_INIT] >>>>>>>>>>>>>>
3802 00:40:23.189492 <<<<<< [CONFIGURE PHASE]: ANA_TX
3803 00:40:23.189544 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3804 00:40:23.189596 ===================================
3805 00:40:23.189647 data_rate = 1200,PCW = 0X5800
3806 00:40:23.189698 ===================================
3807 00:40:23.189750 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3808 00:40:23.189802 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3809 00:40:23.189853 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3810 00:40:23.189906 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3811 00:40:23.189957 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3812 00:40:23.190009 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3813 00:40:23.190061 [ANA_INIT] flow start
3814 00:40:23.190112 [ANA_INIT] PLL >>>>>>>>
3815 00:40:23.190163 [ANA_INIT] PLL <<<<<<<<
3816 00:40:23.190222 [ANA_INIT] MIDPI >>>>>>>>
3817 00:40:23.190274 [ANA_INIT] MIDPI <<<<<<<<
3818 00:40:23.190325 [ANA_INIT] DLL >>>>>>>>
3819 00:40:23.190376 [ANA_INIT] flow end
3820 00:40:23.190427 ============ LP4 DIFF to SE enter ============
3821 00:40:23.190479 ============ LP4 DIFF to SE exit ============
3822 00:40:23.190530 [ANA_INIT] <<<<<<<<<<<<<
3823 00:40:23.190786 [Flow] Enable top DCM control >>>>>
3824 00:40:23.190844 [Flow] Enable top DCM control <<<<<
3825 00:40:23.190897 Enable DLL master slave shuffle
3826 00:40:23.190948 ==============================================================
3827 00:40:23.191001 Gating Mode config
3828 00:40:23.191052 ==============================================================
3829 00:40:23.191104 Config description:
3830 00:40:23.191155 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3831 00:40:23.191208 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3832 00:40:23.191261 SELPH_MODE 0: By rank 1: By Phase
3833 00:40:23.191312 ==============================================================
3834 00:40:23.191364 GAT_TRACK_EN = 1
3835 00:40:23.191415 RX_GATING_MODE = 2
3836 00:40:23.191466 RX_GATING_TRACK_MODE = 2
3837 00:40:23.191517 SELPH_MODE = 1
3838 00:40:23.191568 PICG_EARLY_EN = 1
3839 00:40:23.191620 VALID_LAT_VALUE = 1
3840 00:40:23.191680 ==============================================================
3841 00:40:23.191749 Enter into Gating configuration >>>>
3842 00:40:23.191817 Exit from Gating configuration <<<<
3843 00:40:23.191870 Enter into DVFS_PRE_config >>>>>
3844 00:40:23.191983 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3845 00:40:23.192039 Exit from DVFS_PRE_config <<<<<
3846 00:40:23.192090 Enter into PICG configuration >>>>
3847 00:40:23.192141 Exit from PICG configuration <<<<
3848 00:40:23.192195 [RX_INPUT] configuration >>>>>
3849 00:40:23.192268 [RX_INPUT] configuration <<<<<
3850 00:40:23.192331 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3851 00:40:23.192387 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3852 00:40:23.192443 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3853 00:40:23.192511 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3854 00:40:23.194160 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3855 00:40:23.200933 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3856 00:40:23.204920 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3857 00:40:23.210848 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3858 00:40:23.214369 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3859 00:40:23.217535 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3860 00:40:23.220544 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3861 00:40:23.227361 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3862 00:40:23.230544 ===================================
3863 00:40:23.234234 LPDDR4 DRAM CONFIGURATION
3864 00:40:23.236976 ===================================
3865 00:40:23.237061 EX_ROW_EN[0] = 0x0
3866 00:40:23.241524 EX_ROW_EN[1] = 0x0
3867 00:40:23.241606 LP4Y_EN = 0x0
3868 00:40:23.243564 WORK_FSP = 0x0
3869 00:40:23.243645 WL = 0x2
3870 00:40:23.247081 RL = 0x2
3871 00:40:23.247162 BL = 0x2
3872 00:40:23.250351 RPST = 0x0
3873 00:40:23.250431 RD_PRE = 0x0
3874 00:40:23.253532 WR_PRE = 0x1
3875 00:40:23.253618 WR_PST = 0x0
3876 00:40:23.257851 DBI_WR = 0x0
3877 00:40:23.260129 DBI_RD = 0x0
3878 00:40:23.260214 OTF = 0x1
3879 00:40:23.263492 ===================================
3880 00:40:23.266689 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3881 00:40:23.270306 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3882 00:40:23.276593 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3883 00:40:23.280210 ===================================
3884 00:40:23.283416 LPDDR4 DRAM CONFIGURATION
3885 00:40:23.286660 ===================================
3886 00:40:23.286743 EX_ROW_EN[0] = 0x10
3887 00:40:23.290427 EX_ROW_EN[1] = 0x0
3888 00:40:23.290524 LP4Y_EN = 0x0
3889 00:40:23.294084 WORK_FSP = 0x0
3890 00:40:23.294202 WL = 0x2
3891 00:40:23.296244 RL = 0x2
3892 00:40:23.296324 BL = 0x2
3893 00:40:23.299769 RPST = 0x0
3894 00:40:23.299877 RD_PRE = 0x0
3895 00:40:23.303889 WR_PRE = 0x1
3896 00:40:23.303969 WR_PST = 0x0
3897 00:40:23.306154 DBI_WR = 0x0
3898 00:40:23.309306 DBI_RD = 0x0
3899 00:40:23.309386 OTF = 0x1
3900 00:40:23.313656 ===================================
3901 00:40:23.319442 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3902 00:40:23.323253 nWR fixed to 30
3903 00:40:23.326613 [ModeRegInit_LP4] CH0 RK0
3904 00:40:23.326694 [ModeRegInit_LP4] CH0 RK1
3905 00:40:23.329866 [ModeRegInit_LP4] CH1 RK0
3906 00:40:23.333447 [ModeRegInit_LP4] CH1 RK1
3907 00:40:23.333529 match AC timing 17
3908 00:40:23.339812 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3909 00:40:23.342822 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3910 00:40:23.346518 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3911 00:40:23.353132 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3912 00:40:23.355999 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3913 00:40:23.356082 ==
3914 00:40:23.359690 Dram Type= 6, Freq= 0, CH_0, rank 0
3915 00:40:23.362865 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3916 00:40:23.362947 ==
3917 00:40:23.369234 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3918 00:40:23.376234 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3919 00:40:23.379121 [CA 0] Center 36 (6~67) winsize 62
3920 00:40:23.382880 [CA 1] Center 36 (5~67) winsize 63
3921 00:40:23.386054 [CA 2] Center 34 (4~65) winsize 62
3922 00:40:23.389465 [CA 3] Center 34 (4~65) winsize 62
3923 00:40:23.392632 [CA 4] Center 33 (3~64) winsize 62
3924 00:40:23.396159 [CA 5] Center 33 (2~64) winsize 63
3925 00:40:23.396290
3926 00:40:23.399091 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3927 00:40:23.399199
3928 00:40:23.403649 [CATrainingPosCal] consider 1 rank data
3929 00:40:23.405608 u2DelayCellTimex100 = 270/100 ps
3930 00:40:23.409224 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3931 00:40:23.412376 CA1 delay=36 (5~67),Diff = 3 PI (28 cell)
3932 00:40:23.415758 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3933 00:40:23.418978 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3934 00:40:23.425511 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3935 00:40:23.428873 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
3936 00:40:23.428994
3937 00:40:23.433025 CA PerBit enable=1, Macro0, CA PI delay=33
3938 00:40:23.433152
3939 00:40:23.435820 [CBTSetCACLKResult] CA Dly = 33
3940 00:40:23.435901 CS Dly: 5 (0~36)
3941 00:40:23.435965 ==
3942 00:40:23.439000 Dram Type= 6, Freq= 0, CH_0, rank 1
3943 00:40:23.445192 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3944 00:40:23.445347 ==
3945 00:40:23.448758 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3946 00:40:23.455797 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3947 00:40:23.458874 [CA 0] Center 36 (6~67) winsize 62
3948 00:40:23.462281 [CA 1] Center 36 (6~67) winsize 62
3949 00:40:23.465023 [CA 2] Center 34 (4~65) winsize 62
3950 00:40:23.468940 [CA 3] Center 34 (3~65) winsize 63
3951 00:40:23.471644 [CA 4] Center 34 (3~65) winsize 63
3952 00:40:23.475347 [CA 5] Center 33 (3~64) winsize 62
3953 00:40:23.475438
3954 00:40:23.478801 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3955 00:40:23.478884
3956 00:40:23.481710 [CATrainingPosCal] consider 2 rank data
3957 00:40:23.484957 u2DelayCellTimex100 = 270/100 ps
3958 00:40:23.488257 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3959 00:40:23.491786 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3960 00:40:23.498292 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3961 00:40:23.501823 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3962 00:40:23.505104 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3963 00:40:23.507903 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3964 00:40:23.507987
3965 00:40:23.511262 CA PerBit enable=1, Macro0, CA PI delay=33
3966 00:40:23.511343
3967 00:40:23.514856 [CBTSetCACLKResult] CA Dly = 33
3968 00:40:23.518572 CS Dly: 5 (0~37)
3969 00:40:23.518673
3970 00:40:23.521510 ----->DramcWriteLeveling(PI) begin...
3971 00:40:23.521594 ==
3972 00:40:23.524595 Dram Type= 6, Freq= 0, CH_0, rank 0
3973 00:40:23.527925 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3974 00:40:23.528035 ==
3975 00:40:23.531592 Write leveling (Byte 0): 33 => 33
3976 00:40:23.534931 Write leveling (Byte 1): 31 => 31
3977 00:40:23.537959 DramcWriteLeveling(PI) end<-----
3978 00:40:23.538041
3979 00:40:23.538105 ==
3980 00:40:23.541986 Dram Type= 6, Freq= 0, CH_0, rank 0
3981 00:40:23.544389 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3982 00:40:23.544475 ==
3983 00:40:23.547763 [Gating] SW mode calibration
3984 00:40:23.554807 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3985 00:40:23.562147 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3986 00:40:23.564105 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3987 00:40:23.567288 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3988 00:40:23.574626 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3989 00:40:23.577412 0 9 12 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
3990 00:40:23.581371 0 9 16 | B1->B0 | 2f2f 2626 | 1 0 | (1 0) (0 0)
3991 00:40:23.587086 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3992 00:40:23.590358 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3993 00:40:23.593789 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3994 00:40:23.600235 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3995 00:40:23.603810 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3996 00:40:23.607321 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3997 00:40:23.614223 0 10 12 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (0 0)
3998 00:40:23.617287 0 10 16 | B1->B0 | 3838 3f3f | 1 0 | (0 0) (0 0)
3999 00:40:23.620748 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4000 00:40:23.626996 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4001 00:40:23.630286 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4002 00:40:23.633184 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4003 00:40:23.640525 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4004 00:40:23.644332 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4005 00:40:23.646972 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4006 00:40:23.653208 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4007 00:40:23.657500 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4008 00:40:23.659587 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4009 00:40:23.666838 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4010 00:40:23.669759 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4011 00:40:23.673401 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4012 00:40:23.679383 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4013 00:40:23.682719 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4014 00:40:23.686062 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4015 00:40:23.692683 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4016 00:40:23.696018 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4017 00:40:23.699271 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4018 00:40:23.705679 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4019 00:40:23.709170 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4020 00:40:23.712597 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4021 00:40:23.719184 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4022 00:40:23.719272 Total UI for P1: 0, mck2ui 16
4023 00:40:23.725972 best dqsien dly found for B0: ( 0, 13, 8)
4024 00:40:23.728696 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4025 00:40:23.732497 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4026 00:40:23.735543 Total UI for P1: 0, mck2ui 16
4027 00:40:23.739812 best dqsien dly found for B1: ( 0, 13, 16)
4028 00:40:23.742169 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4029 00:40:23.745474 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4030 00:40:23.745601
4031 00:40:23.752153 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4032 00:40:23.755222 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4033 00:40:23.758581 [Gating] SW calibration Done
4034 00:40:23.758729 ==
4035 00:40:23.762165 Dram Type= 6, Freq= 0, CH_0, rank 0
4036 00:40:23.764875 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4037 00:40:23.764995 ==
4038 00:40:23.765072 RX Vref Scan: 0
4039 00:40:23.765165
4040 00:40:23.768424 RX Vref 0 -> 0, step: 1
4041 00:40:23.768560
4042 00:40:23.771899 RX Delay -230 -> 252, step: 16
4043 00:40:23.775834 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4044 00:40:23.781826 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4045 00:40:23.785431 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4046 00:40:23.788371 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4047 00:40:23.791524 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4048 00:40:23.795013 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4049 00:40:23.802001 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4050 00:40:23.804978 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4051 00:40:23.807925 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4052 00:40:23.811459 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4053 00:40:23.818398 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4054 00:40:23.821021 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4055 00:40:23.824442 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4056 00:40:23.827963 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4057 00:40:23.834508 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4058 00:40:23.837387 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4059 00:40:23.837494 ==
4060 00:40:23.841188 Dram Type= 6, Freq= 0, CH_0, rank 0
4061 00:40:23.844514 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4062 00:40:23.844645 ==
4063 00:40:23.848322 DQS Delay:
4064 00:40:23.848417 DQS0 = 0, DQS1 = 0
4065 00:40:23.848483 DQM Delay:
4066 00:40:23.850714 DQM0 = 46, DQM1 = 35
4067 00:40:23.850805 DQ Delay:
4068 00:40:23.854473 DQ0 =41, DQ1 =49, DQ2 =41, DQ3 =41
4069 00:40:23.857446 DQ4 =49, DQ5 =33, DQ6 =57, DQ7 =57
4070 00:40:23.860718 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =33
4071 00:40:23.863912 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =41
4072 00:40:23.864014
4073 00:40:23.864080
4074 00:40:23.864139 ==
4075 00:40:23.867349 Dram Type= 6, Freq= 0, CH_0, rank 0
4076 00:40:23.874002 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4077 00:40:23.874127 ==
4078 00:40:23.874196
4079 00:40:23.874256
4080 00:40:23.877018 TX Vref Scan disable
4081 00:40:23.877103 == TX Byte 0 ==
4082 00:40:23.884069 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4083 00:40:23.886918 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4084 00:40:23.887013 == TX Byte 1 ==
4085 00:40:23.893657 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4086 00:40:23.897004 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4087 00:40:23.897110 ==
4088 00:40:23.900711 Dram Type= 6, Freq= 0, CH_0, rank 0
4089 00:40:23.903537 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4090 00:40:23.903638 ==
4091 00:40:23.903708
4092 00:40:23.903768
4093 00:40:23.906781 TX Vref Scan disable
4094 00:40:23.910148 == TX Byte 0 ==
4095 00:40:23.913444 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4096 00:40:23.916456 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4097 00:40:23.920425 == TX Byte 1 ==
4098 00:40:23.923261 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4099 00:40:23.926727 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4100 00:40:23.926832
4101 00:40:23.930073 [DATLAT]
4102 00:40:23.930177 Freq=600, CH0 RK0
4103 00:40:23.930243
4104 00:40:23.933382 DATLAT Default: 0x9
4105 00:40:23.933519 0, 0xFFFF, sum = 0
4106 00:40:23.936405 1, 0xFFFF, sum = 0
4107 00:40:23.936498 2, 0xFFFF, sum = 0
4108 00:40:23.939730 3, 0xFFFF, sum = 0
4109 00:40:23.939818 4, 0xFFFF, sum = 0
4110 00:40:23.943196 5, 0xFFFF, sum = 0
4111 00:40:23.946439 6, 0xFFFF, sum = 0
4112 00:40:23.946526 7, 0xFFFF, sum = 0
4113 00:40:23.946591 8, 0x0, sum = 1
4114 00:40:23.949974 9, 0x0, sum = 2
4115 00:40:23.950059 10, 0x0, sum = 3
4116 00:40:23.952813 11, 0x0, sum = 4
4117 00:40:23.952897 best_step = 9
4118 00:40:23.952962
4119 00:40:23.953022 ==
4120 00:40:23.956383 Dram Type= 6, Freq= 0, CH_0, rank 0
4121 00:40:23.962934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4122 00:40:23.963025 ==
4123 00:40:23.963092 RX Vref Scan: 1
4124 00:40:23.963152
4125 00:40:23.966023 RX Vref 0 -> 0, step: 1
4126 00:40:23.966105
4127 00:40:23.969599 RX Delay -195 -> 252, step: 8
4128 00:40:23.969682
4129 00:40:23.972505 Set Vref, RX VrefLevel [Byte0]: 53
4130 00:40:23.976108 [Byte1]: 58
4131 00:40:23.976217
4132 00:40:23.979856 Final RX Vref Byte 0 = 53 to rank0
4133 00:40:23.983033 Final RX Vref Byte 1 = 58 to rank0
4134 00:40:23.985925 Final RX Vref Byte 0 = 53 to rank1
4135 00:40:23.989487 Final RX Vref Byte 1 = 58 to rank1==
4136 00:40:23.992361 Dram Type= 6, Freq= 0, CH_0, rank 0
4137 00:40:23.995783 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4138 00:40:23.995869 ==
4139 00:40:23.998964 DQS Delay:
4140 00:40:23.999047 DQS0 = 0, DQS1 = 0
4141 00:40:24.002116 DQM Delay:
4142 00:40:24.002234 DQM0 = 40, DQM1 = 32
4143 00:40:24.002314 DQ Delay:
4144 00:40:24.005767 DQ0 =44, DQ1 =40, DQ2 =36, DQ3 =36
4145 00:40:24.008993 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =44
4146 00:40:24.012189 DQ8 =24, DQ9 =16, DQ10 =32, DQ11 =28
4147 00:40:24.015583 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4148 00:40:24.015666
4149 00:40:24.015731
4150 00:40:24.025228 [DQSOSCAuto] RK0, (LSB)MR18= 0x554c, (MSB)MR19= 0x808, tDQSOscB0 = 395 ps tDQSOscB1 = 393 ps
4151 00:40:24.028761 CH0 RK0: MR19=808, MR18=554C
4152 00:40:24.035971 CH0_RK0: MR19=0x808, MR18=0x554C, DQSOSC=393, MR23=63, INC=169, DEC=113
4153 00:40:24.036063
4154 00:40:24.038514 ----->DramcWriteLeveling(PI) begin...
4155 00:40:24.038597 ==
4156 00:40:24.042061 Dram Type= 6, Freq= 0, CH_0, rank 1
4157 00:40:24.045209 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4158 00:40:24.045353 ==
4159 00:40:24.048753 Write leveling (Byte 0): 33 => 33
4160 00:40:24.051764 Write leveling (Byte 1): 30 => 30
4161 00:40:24.055339 DramcWriteLeveling(PI) end<-----
4162 00:40:24.055529
4163 00:40:24.055623 ==
4164 00:40:24.058464 Dram Type= 6, Freq= 0, CH_0, rank 1
4165 00:40:24.061597 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4166 00:40:24.061767 ==
4167 00:40:24.064927 [Gating] SW mode calibration
4168 00:40:24.072225 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4169 00:40:24.078304 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4170 00:40:24.081896 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4171 00:40:24.087870 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4172 00:40:24.091410 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4173 00:40:24.094434 0 9 12 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
4174 00:40:24.101099 0 9 16 | B1->B0 | 2f2f 2424 | 0 0 | (0 0) (0 0)
4175 00:40:24.104397 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4176 00:40:24.107489 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4177 00:40:24.114325 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4178 00:40:24.116993 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4179 00:40:24.121001 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4180 00:40:24.127447 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4181 00:40:24.130548 0 10 12 | B1->B0 | 2323 3535 | 0 0 | (0 0) (0 0)
4182 00:40:24.133823 0 10 16 | B1->B0 | 3e3e 4646 | 0 0 | (1 1) (0 0)
4183 00:40:24.140448 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4184 00:40:24.144260 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4185 00:40:24.147777 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4186 00:40:24.153652 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4187 00:40:24.157059 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4188 00:40:24.160790 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4189 00:40:24.166518 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4190 00:40:24.170104 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4191 00:40:24.173513 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4192 00:40:24.179706 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4193 00:40:24.183458 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4194 00:40:24.186710 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4195 00:40:24.193240 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4196 00:40:24.196221 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4197 00:40:24.199625 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4198 00:40:24.206457 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4199 00:40:24.209709 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4200 00:40:24.212843 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4201 00:40:24.219470 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4202 00:40:24.222825 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4203 00:40:24.225896 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4204 00:40:24.232601 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4205 00:40:24.235563 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4206 00:40:24.238927 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4207 00:40:24.242276 Total UI for P1: 0, mck2ui 16
4208 00:40:24.245539 best dqsien dly found for B0: ( 0, 13, 14)
4209 00:40:24.248914 Total UI for P1: 0, mck2ui 16
4210 00:40:24.252470 best dqsien dly found for B1: ( 0, 13, 14)
4211 00:40:24.255881 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4212 00:40:24.258773 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4213 00:40:24.261979
4214 00:40:24.265467 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4215 00:40:24.268992 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4216 00:40:24.271845 [Gating] SW calibration Done
4217 00:40:24.271961 ==
4218 00:40:24.275457 Dram Type= 6, Freq= 0, CH_0, rank 1
4219 00:40:24.278717 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4220 00:40:24.278797 ==
4221 00:40:24.278861 RX Vref Scan: 0
4222 00:40:24.281705
4223 00:40:24.281789 RX Vref 0 -> 0, step: 1
4224 00:40:24.281855
4225 00:40:24.285210 RX Delay -230 -> 252, step: 16
4226 00:40:24.288327 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4227 00:40:24.294914 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4228 00:40:24.298231 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4229 00:40:24.301705 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4230 00:40:24.304657 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4231 00:40:24.308160 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4232 00:40:24.314885 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4233 00:40:24.318662 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4234 00:40:24.321457 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4235 00:40:24.324640 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4236 00:40:24.331176 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4237 00:40:24.334293 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4238 00:40:24.337783 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4239 00:40:24.340770 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4240 00:40:24.347605 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4241 00:40:24.350857 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4242 00:40:24.350939 ==
4243 00:40:24.354226 Dram Type= 6, Freq= 0, CH_0, rank 1
4244 00:40:24.357839 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4245 00:40:24.357922 ==
4246 00:40:24.361122 DQS Delay:
4247 00:40:24.361203 DQS0 = 0, DQS1 = 0
4248 00:40:24.364101 DQM Delay:
4249 00:40:24.364183 DQM0 = 43, DQM1 = 31
4250 00:40:24.364249 DQ Delay:
4251 00:40:24.367554 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4252 00:40:24.370614 DQ4 =41, DQ5 =33, DQ6 =57, DQ7 =49
4253 00:40:24.374000 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
4254 00:40:24.377245 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =33
4255 00:40:24.377349
4256 00:40:24.377413
4257 00:40:24.381119 ==
4258 00:40:24.384618 Dram Type= 6, Freq= 0, CH_0, rank 1
4259 00:40:24.386870 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4260 00:40:24.386999 ==
4261 00:40:24.387105
4262 00:40:24.387201
4263 00:40:24.390336 TX Vref Scan disable
4264 00:40:24.390420 == TX Byte 0 ==
4265 00:40:24.396635 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4266 00:40:24.400460 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4267 00:40:24.400553 == TX Byte 1 ==
4268 00:40:24.406674 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4269 00:40:24.410923 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4270 00:40:24.411005 ==
4271 00:40:24.413476 Dram Type= 6, Freq= 0, CH_0, rank 1
4272 00:40:24.416547 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4273 00:40:24.416673 ==
4274 00:40:24.416782
4275 00:40:24.416873
4276 00:40:24.419690 TX Vref Scan disable
4277 00:40:24.423286 == TX Byte 0 ==
4278 00:40:24.426426 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4279 00:40:24.433364 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4280 00:40:24.433448 == TX Byte 1 ==
4281 00:40:24.436726 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4282 00:40:24.443208 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4283 00:40:24.443290
4284 00:40:24.443355 [DATLAT]
4285 00:40:24.443414 Freq=600, CH0 RK1
4286 00:40:24.443473
4287 00:40:24.446270 DATLAT Default: 0x9
4288 00:40:24.446351 0, 0xFFFF, sum = 0
4289 00:40:24.449750 1, 0xFFFF, sum = 0
4290 00:40:24.453038 2, 0xFFFF, sum = 0
4291 00:40:24.453120 3, 0xFFFF, sum = 0
4292 00:40:24.456266 4, 0xFFFF, sum = 0
4293 00:40:24.456349 5, 0xFFFF, sum = 0
4294 00:40:24.459698 6, 0xFFFF, sum = 0
4295 00:40:24.459781 7, 0xFFFF, sum = 0
4296 00:40:24.462969 8, 0x0, sum = 1
4297 00:40:24.463052 9, 0x0, sum = 2
4298 00:40:24.463118 10, 0x0, sum = 3
4299 00:40:24.466297 11, 0x0, sum = 4
4300 00:40:24.466411 best_step = 9
4301 00:40:24.466478
4302 00:40:24.469402 ==
4303 00:40:24.469484 Dram Type= 6, Freq= 0, CH_0, rank 1
4304 00:40:24.476167 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4305 00:40:24.476250 ==
4306 00:40:24.476315 RX Vref Scan: 0
4307 00:40:24.476375
4308 00:40:24.479410 RX Vref 0 -> 0, step: 1
4309 00:40:24.479491
4310 00:40:24.482515 RX Delay -195 -> 252, step: 8
4311 00:40:24.489100 iDelay=197, Bit 0, Center 40 (-107 ~ 188) 296
4312 00:40:24.492696 iDelay=197, Bit 1, Center 44 (-107 ~ 196) 304
4313 00:40:24.495788 iDelay=197, Bit 2, Center 36 (-115 ~ 188) 304
4314 00:40:24.499052 iDelay=197, Bit 3, Center 40 (-107 ~ 188) 296
4315 00:40:24.502572 iDelay=197, Bit 4, Center 44 (-107 ~ 196) 304
4316 00:40:24.508856 iDelay=197, Bit 5, Center 28 (-123 ~ 180) 304
4317 00:40:24.512244 iDelay=197, Bit 6, Center 48 (-99 ~ 196) 296
4318 00:40:24.515257 iDelay=197, Bit 7, Center 44 (-107 ~ 196) 304
4319 00:40:24.518672 iDelay=197, Bit 8, Center 24 (-131 ~ 180) 312
4320 00:40:24.525566 iDelay=197, Bit 9, Center 16 (-139 ~ 172) 312
4321 00:40:24.528690 iDelay=197, Bit 10, Center 36 (-123 ~ 196) 320
4322 00:40:24.531865 iDelay=197, Bit 11, Center 28 (-123 ~ 180) 304
4323 00:40:24.535714 iDelay=197, Bit 12, Center 40 (-115 ~ 196) 312
4324 00:40:24.541747 iDelay=197, Bit 13, Center 40 (-115 ~ 196) 312
4325 00:40:24.545729 iDelay=197, Bit 14, Center 40 (-115 ~ 196) 312
4326 00:40:24.548720 iDelay=197, Bit 15, Center 40 (-115 ~ 196) 312
4327 00:40:24.548801 ==
4328 00:40:24.552193 Dram Type= 6, Freq= 0, CH_0, rank 1
4329 00:40:24.554824 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4330 00:40:24.558645 ==
4331 00:40:24.558727 DQS Delay:
4332 00:40:24.558791 DQS0 = 0, DQS1 = 0
4333 00:40:24.561531 DQM Delay:
4334 00:40:24.561612 DQM0 = 40, DQM1 = 33
4335 00:40:24.564933 DQ Delay:
4336 00:40:24.567960 DQ0 =40, DQ1 =44, DQ2 =36, DQ3 =40
4337 00:40:24.568042 DQ4 =44, DQ5 =28, DQ6 =48, DQ7 =44
4338 00:40:24.571745 DQ8 =24, DQ9 =16, DQ10 =36, DQ11 =28
4339 00:40:24.577953 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4340 00:40:24.578034
4341 00:40:24.578097
4342 00:40:24.584999 [DQSOSCAuto] RK1, (LSB)MR18= 0x4c48, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 395 ps
4343 00:40:24.587728 CH0 RK1: MR19=808, MR18=4C48
4344 00:40:24.594391 CH0_RK1: MR19=0x808, MR18=0x4C48, DQSOSC=395, MR23=63, INC=168, DEC=112
4345 00:40:24.597636 [RxdqsGatingPostProcess] freq 600
4346 00:40:24.601265 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4347 00:40:24.604186 Pre-setting of DQS Precalculation
4348 00:40:24.611008 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4349 00:40:24.611089 ==
4350 00:40:24.614299 Dram Type= 6, Freq= 0, CH_1, rank 0
4351 00:40:24.617793 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4352 00:40:24.617874 ==
4353 00:40:24.624525 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4354 00:40:24.630717 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4355 00:40:24.634158 [CA 0] Center 35 (5~66) winsize 62
4356 00:40:24.637624 [CA 1] Center 35 (5~66) winsize 62
4357 00:40:24.640454 [CA 2] Center 34 (4~65) winsize 62
4358 00:40:24.644437 [CA 3] Center 34 (3~65) winsize 63
4359 00:40:24.647224 [CA 4] Center 34 (4~65) winsize 62
4360 00:40:24.650551 [CA 5] Center 33 (3~64) winsize 62
4361 00:40:24.650632
4362 00:40:24.654252 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4363 00:40:24.654333
4364 00:40:24.657377 [CATrainingPosCal] consider 1 rank data
4365 00:40:24.660637 u2DelayCellTimex100 = 270/100 ps
4366 00:40:24.663734 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4367 00:40:24.667499 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4368 00:40:24.670764 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4369 00:40:24.673924 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4370 00:40:24.677029 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4371 00:40:24.680340 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4372 00:40:24.680421
4373 00:40:24.687139 CA PerBit enable=1, Macro0, CA PI delay=33
4374 00:40:24.687221
4375 00:40:24.689915 [CBTSetCACLKResult] CA Dly = 33
4376 00:40:24.689997 CS Dly: 4 (0~35)
4377 00:40:24.690062 ==
4378 00:40:24.693173 Dram Type= 6, Freq= 0, CH_1, rank 1
4379 00:40:24.696512 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4380 00:40:24.696599 ==
4381 00:40:24.702999 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4382 00:40:24.709734 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4383 00:40:24.713540 [CA 0] Center 35 (5~66) winsize 62
4384 00:40:24.716686 [CA 1] Center 35 (5~66) winsize 62
4385 00:40:24.720189 [CA 2] Center 34 (4~65) winsize 62
4386 00:40:24.723766 [CA 3] Center 34 (3~65) winsize 63
4387 00:40:24.726487 [CA 4] Center 34 (3~65) winsize 63
4388 00:40:24.730051 [CA 5] Center 34 (3~65) winsize 63
4389 00:40:24.730208
4390 00:40:24.733116 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4391 00:40:24.733249
4392 00:40:24.736348 [CATrainingPosCal] consider 2 rank data
4393 00:40:24.739230 u2DelayCellTimex100 = 270/100 ps
4394 00:40:24.742857 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4395 00:40:24.746777 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4396 00:40:24.749579 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4397 00:40:24.755870 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4398 00:40:24.759900 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4399 00:40:24.762552 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4400 00:40:24.762688
4401 00:40:24.766042 CA PerBit enable=1, Macro0, CA PI delay=33
4402 00:40:24.766220
4403 00:40:24.769186 [CBTSetCACLKResult] CA Dly = 33
4404 00:40:24.769396 CS Dly: 4 (0~36)
4405 00:40:24.769498
4406 00:40:24.773191 ----->DramcWriteLeveling(PI) begin...
4407 00:40:24.773362 ==
4408 00:40:24.775990 Dram Type= 6, Freq= 0, CH_1, rank 0
4409 00:40:24.782567 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4410 00:40:24.782764 ==
4411 00:40:24.786244 Write leveling (Byte 0): 29 => 29
4412 00:40:24.789557 Write leveling (Byte 1): 29 => 29
4413 00:40:24.789807 DramcWriteLeveling(PI) end<-----
4414 00:40:24.792213
4415 00:40:24.792377 ==
4416 00:40:24.795817 Dram Type= 6, Freq= 0, CH_1, rank 0
4417 00:40:24.799241 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4418 00:40:24.799526 ==
4419 00:40:24.802891 [Gating] SW mode calibration
4420 00:40:24.809903 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4421 00:40:24.815801 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4422 00:40:24.819003 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4423 00:40:24.821881 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4424 00:40:24.828348 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4425 00:40:24.831570 0 9 12 | B1->B0 | 2f2f 2d2d | 0 0 | (0 0) (1 1)
4426 00:40:24.835406 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
4427 00:40:24.838834 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4428 00:40:24.845139 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4429 00:40:24.848057 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4430 00:40:24.854778 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4431 00:40:24.858583 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4432 00:40:24.861401 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4433 00:40:24.868116 0 10 12 | B1->B0 | 2f2f 3737 | 0 1 | (0 0) (0 0)
4434 00:40:24.871259 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4435 00:40:24.874569 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4436 00:40:24.881294 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4437 00:40:24.884736 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4438 00:40:24.887806 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4439 00:40:24.894140 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4440 00:40:24.898183 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4441 00:40:24.900972 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4442 00:40:24.907741 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4443 00:40:24.911071 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4444 00:40:24.913892 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4445 00:40:24.920503 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4446 00:40:24.923903 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4447 00:40:24.927161 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4448 00:40:24.933608 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4449 00:40:24.937416 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4450 00:40:24.940648 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4451 00:40:24.947067 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4452 00:40:24.950850 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4453 00:40:24.953463 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4454 00:40:24.959942 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4455 00:40:24.963684 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4456 00:40:24.967064 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4457 00:40:24.973580 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4458 00:40:24.977153 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4459 00:40:24.979730 Total UI for P1: 0, mck2ui 16
4460 00:40:24.983227 best dqsien dly found for B0: ( 0, 13, 12)
4461 00:40:24.987306 Total UI for P1: 0, mck2ui 16
4462 00:40:24.989946 best dqsien dly found for B1: ( 0, 13, 14)
4463 00:40:24.993073 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4464 00:40:24.996531 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4465 00:40:24.996612
4466 00:40:24.999922 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4467 00:40:25.003237 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4468 00:40:25.006719 [Gating] SW calibration Done
4469 00:40:25.006799 ==
4470 00:40:25.010212 Dram Type= 6, Freq= 0, CH_1, rank 0
4471 00:40:25.013114 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4472 00:40:25.016445 ==
4473 00:40:25.016526 RX Vref Scan: 0
4474 00:40:25.016590
4475 00:40:25.019461 RX Vref 0 -> 0, step: 1
4476 00:40:25.019541
4477 00:40:25.022681 RX Delay -230 -> 252, step: 16
4478 00:40:25.026653 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4479 00:40:25.029521 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4480 00:40:25.032759 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4481 00:40:25.039463 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4482 00:40:25.042498 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4483 00:40:25.046191 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4484 00:40:25.049159 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4485 00:40:25.052650 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4486 00:40:25.059903 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4487 00:40:25.062224 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4488 00:40:25.065957 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4489 00:40:25.069983 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4490 00:40:25.075497 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4491 00:40:25.078928 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4492 00:40:25.082733 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4493 00:40:25.085775 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4494 00:40:25.089437 ==
4495 00:40:25.091694 Dram Type= 6, Freq= 0, CH_1, rank 0
4496 00:40:25.095167 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4497 00:40:25.095247 ==
4498 00:40:25.095310 DQS Delay:
4499 00:40:25.098489 DQS0 = 0, DQS1 = 0
4500 00:40:25.098569 DQM Delay:
4501 00:40:25.101713 DQM0 = 43, DQM1 = 39
4502 00:40:25.101875 DQ Delay:
4503 00:40:25.105213 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =41
4504 00:40:25.109204 DQ4 =41, DQ5 =57, DQ6 =49, DQ7 =41
4505 00:40:25.111703 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4506 00:40:25.115392 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =41
4507 00:40:25.115471
4508 00:40:25.115534
4509 00:40:25.115593 ==
4510 00:40:25.118249 Dram Type= 6, Freq= 0, CH_1, rank 0
4511 00:40:25.121778 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4512 00:40:25.121858 ==
4513 00:40:25.121922
4514 00:40:25.121980
4515 00:40:25.125116 TX Vref Scan disable
4516 00:40:25.128485 == TX Byte 0 ==
4517 00:40:25.131565 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4518 00:40:25.134657 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4519 00:40:25.138071 == TX Byte 1 ==
4520 00:40:25.141497 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4521 00:40:25.144624 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4522 00:40:25.144704 ==
4523 00:40:25.148438 Dram Type= 6, Freq= 0, CH_1, rank 0
4524 00:40:25.154598 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4525 00:40:25.154678 ==
4526 00:40:25.154742
4527 00:40:25.154800
4528 00:40:25.154856 TX Vref Scan disable
4529 00:40:25.158934 == TX Byte 0 ==
4530 00:40:25.162483 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4531 00:40:25.168777 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4532 00:40:25.168857 == TX Byte 1 ==
4533 00:40:25.172194 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4534 00:40:25.179021 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4535 00:40:25.179117
4536 00:40:25.179194 [DATLAT]
4537 00:40:25.179282 Freq=600, CH1 RK0
4538 00:40:25.179369
4539 00:40:25.182095 DATLAT Default: 0x9
4540 00:40:25.182178 0, 0xFFFF, sum = 0
4541 00:40:25.185689 1, 0xFFFF, sum = 0
4542 00:40:25.189083 2, 0xFFFF, sum = 0
4543 00:40:25.189217 3, 0xFFFF, sum = 0
4544 00:40:25.192433 4, 0xFFFF, sum = 0
4545 00:40:25.192541 5, 0xFFFF, sum = 0
4546 00:40:25.195774 6, 0xFFFF, sum = 0
4547 00:40:25.195880 7, 0xFFFF, sum = 0
4548 00:40:25.198435 8, 0x0, sum = 1
4549 00:40:25.198543 9, 0x0, sum = 2
4550 00:40:25.198615 10, 0x0, sum = 3
4551 00:40:25.202129 11, 0x0, sum = 4
4552 00:40:25.202245 best_step = 9
4553 00:40:25.202318
4554 00:40:25.202380 ==
4555 00:40:25.205415 Dram Type= 6, Freq= 0, CH_1, rank 0
4556 00:40:25.211621 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4557 00:40:25.211774 ==
4558 00:40:25.211845 RX Vref Scan: 1
4559 00:40:25.211924
4560 00:40:25.215598 RX Vref 0 -> 0, step: 1
4561 00:40:25.215691
4562 00:40:25.218936 RX Delay -179 -> 252, step: 8
4563 00:40:25.219055
4564 00:40:25.221586 Set Vref, RX VrefLevel [Byte0]: 51
4565 00:40:25.225157 [Byte1]: 53
4566 00:40:25.225240
4567 00:40:25.228313 Final RX Vref Byte 0 = 51 to rank0
4568 00:40:25.231644 Final RX Vref Byte 1 = 53 to rank0
4569 00:40:25.235253 Final RX Vref Byte 0 = 51 to rank1
4570 00:40:25.238491 Final RX Vref Byte 1 = 53 to rank1==
4571 00:40:25.241729 Dram Type= 6, Freq= 0, CH_1, rank 0
4572 00:40:25.245099 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4573 00:40:25.248087 ==
4574 00:40:25.248200 DQS Delay:
4575 00:40:25.248290 DQS0 = 0, DQS1 = 0
4576 00:40:25.251251 DQM Delay:
4577 00:40:25.251375 DQM0 = 41, DQM1 = 34
4578 00:40:25.255056 DQ Delay:
4579 00:40:25.257771 DQ0 =48, DQ1 =40, DQ2 =32, DQ3 =44
4580 00:40:25.257965 DQ4 =36, DQ5 =48, DQ6 =52, DQ7 =32
4581 00:40:25.261078 DQ8 =20, DQ9 =24, DQ10 =32, DQ11 =28
4582 00:40:25.267380 DQ12 =44, DQ13 =44, DQ14 =40, DQ15 =40
4583 00:40:25.267590
4584 00:40:25.267747
4585 00:40:25.274503 [DQSOSCAuto] RK0, (LSB)MR18= 0x3952, (MSB)MR19= 0x808, tDQSOscB0 = 394 ps tDQSOscB1 = 399 ps
4586 00:40:25.277749 CH1 RK0: MR19=808, MR18=3952
4587 00:40:25.284493 CH1_RK0: MR19=0x808, MR18=0x3952, DQSOSC=394, MR23=63, INC=168, DEC=112
4588 00:40:25.284714
4589 00:40:25.287627 ----->DramcWriteLeveling(PI) begin...
4590 00:40:25.287845 ==
4591 00:40:25.291012 Dram Type= 6, Freq= 0, CH_1, rank 1
4592 00:40:25.293899 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4593 00:40:25.294131 ==
4594 00:40:25.297787 Write leveling (Byte 0): 30 => 30
4595 00:40:25.300714 Write leveling (Byte 1): 31 => 31
4596 00:40:25.304293 DramcWriteLeveling(PI) end<-----
4597 00:40:25.304419
4598 00:40:25.304517 ==
4599 00:40:25.307920 Dram Type= 6, Freq= 0, CH_1, rank 1
4600 00:40:25.310995 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4601 00:40:25.311106 ==
4602 00:40:25.314037 [Gating] SW mode calibration
4603 00:40:25.320253 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4604 00:40:25.327004 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4605 00:40:25.330500 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4606 00:40:25.336782 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4607 00:40:25.339991 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4608 00:40:25.343575 0 9 12 | B1->B0 | 3030 2929 | 1 1 | (1 0) (1 0)
4609 00:40:25.349846 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4610 00:40:25.353603 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4611 00:40:25.356821 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4612 00:40:25.363262 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4613 00:40:25.367120 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4614 00:40:25.369637 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4615 00:40:25.376635 0 10 8 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
4616 00:40:25.379712 0 10 12 | B1->B0 | 3333 3f3f | 0 0 | (0 0) (0 0)
4617 00:40:25.383460 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4618 00:40:25.389189 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4619 00:40:25.392484 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4620 00:40:25.396065 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4621 00:40:25.402824 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4622 00:40:25.405956 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4623 00:40:25.409737 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4624 00:40:25.416031 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4625 00:40:25.419174 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4626 00:40:25.422798 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4627 00:40:25.429823 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4628 00:40:25.433028 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4629 00:40:25.435682 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4630 00:40:25.442126 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4631 00:40:25.445631 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4632 00:40:25.448906 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4633 00:40:25.455611 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4634 00:40:25.458661 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4635 00:40:25.462667 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4636 00:40:25.468627 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4637 00:40:25.471964 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4638 00:40:25.475383 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4639 00:40:25.482179 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4640 00:40:25.485302 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4641 00:40:25.488527 Total UI for P1: 0, mck2ui 16
4642 00:40:25.491904 best dqsien dly found for B0: ( 0, 13, 8)
4643 00:40:25.495072 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4644 00:40:25.498166 Total UI for P1: 0, mck2ui 16
4645 00:40:25.501809 best dqsien dly found for B1: ( 0, 13, 12)
4646 00:40:25.504735 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4647 00:40:25.511723 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4648 00:40:25.512202
4649 00:40:25.515027 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4650 00:40:25.518507 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4651 00:40:25.521367 [Gating] SW calibration Done
4652 00:40:25.521763 ==
4653 00:40:25.525501 Dram Type= 6, Freq= 0, CH_1, rank 1
4654 00:40:25.528745 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4655 00:40:25.529200 ==
4656 00:40:25.529782 RX Vref Scan: 0
4657 00:40:25.531394
4658 00:40:25.531754 RX Vref 0 -> 0, step: 1
4659 00:40:25.532052
4660 00:40:25.535186 RX Delay -230 -> 252, step: 16
4661 00:40:25.538188 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4662 00:40:25.545104 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4663 00:40:25.547979 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4664 00:40:25.551352 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4665 00:40:25.554310 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4666 00:40:25.557691 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4667 00:40:25.563990 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4668 00:40:25.567874 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4669 00:40:25.570873 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4670 00:40:25.574172 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4671 00:40:25.580719 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4672 00:40:25.584169 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4673 00:40:25.587563 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4674 00:40:25.590579 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4675 00:40:25.597561 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4676 00:40:25.600741 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4677 00:40:25.601063 ==
4678 00:40:25.603785 Dram Type= 6, Freq= 0, CH_1, rank 1
4679 00:40:25.606950 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4680 00:40:25.607185 ==
4681 00:40:25.610186 DQS Delay:
4682 00:40:25.610374 DQS0 = 0, DQS1 = 0
4683 00:40:25.613245 DQM Delay:
4684 00:40:25.613463 DQM0 = 42, DQM1 = 39
4685 00:40:25.613584 DQ Delay:
4686 00:40:25.616935 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =41
4687 00:40:25.620188 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4688 00:40:25.623288 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4689 00:40:25.626444 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =49
4690 00:40:25.626572
4691 00:40:25.626661
4692 00:40:25.630091 ==
4693 00:40:25.630273 Dram Type= 6, Freq= 0, CH_1, rank 1
4694 00:40:25.636827 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4695 00:40:25.637004 ==
4696 00:40:25.637111
4697 00:40:25.637209
4698 00:40:25.640193 TX Vref Scan disable
4699 00:40:25.640300 == TX Byte 0 ==
4700 00:40:25.645976 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4701 00:40:25.649698 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4702 00:40:25.649859 == TX Byte 1 ==
4703 00:40:25.656830 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4704 00:40:25.659441 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4705 00:40:25.659588 ==
4706 00:40:25.662962 Dram Type= 6, Freq= 0, CH_1, rank 1
4707 00:40:25.666040 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4708 00:40:25.666141 ==
4709 00:40:25.666215
4710 00:40:25.666284
4711 00:40:25.669370 TX Vref Scan disable
4712 00:40:25.672429 == TX Byte 0 ==
4713 00:40:25.675596 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4714 00:40:25.679267 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4715 00:40:25.682639 == TX Byte 1 ==
4716 00:40:25.685661 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4717 00:40:25.688961 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4718 00:40:25.692578
4719 00:40:25.692740 [DATLAT]
4720 00:40:25.692850 Freq=600, CH1 RK1
4721 00:40:25.692949
4722 00:40:25.695844 DATLAT Default: 0x9
4723 00:40:25.695990 0, 0xFFFF, sum = 0
4724 00:40:25.698860 1, 0xFFFF, sum = 0
4725 00:40:25.699008 2, 0xFFFF, sum = 0
4726 00:40:25.701924 3, 0xFFFF, sum = 0
4727 00:40:25.705658 4, 0xFFFF, sum = 0
4728 00:40:25.705808 5, 0xFFFF, sum = 0
4729 00:40:25.708749 6, 0xFFFF, sum = 0
4730 00:40:25.708944 7, 0xFFFF, sum = 0
4731 00:40:25.712335 8, 0x0, sum = 1
4732 00:40:25.712484 9, 0x0, sum = 2
4733 00:40:25.712601 10, 0x0, sum = 3
4734 00:40:25.715686 11, 0x0, sum = 4
4735 00:40:25.715814 best_step = 9
4736 00:40:25.715913
4737 00:40:25.716007 ==
4738 00:40:25.718551 Dram Type= 6, Freq= 0, CH_1, rank 1
4739 00:40:25.725223 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4740 00:40:25.725358 ==
4741 00:40:25.725439 RX Vref Scan: 0
4742 00:40:25.725513
4743 00:40:25.728549 RX Vref 0 -> 0, step: 1
4744 00:40:25.728639
4745 00:40:25.731929 RX Delay -179 -> 252, step: 8
4746 00:40:25.738441 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4747 00:40:25.741385 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4748 00:40:25.751842 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4749 00:40:25.751980 iDelay=205, Bit 3, Center 36 (-123 ~ 196) 320
4750 00:40:25.752051 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4751 00:40:25.757977 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4752 00:40:25.761249 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4753 00:40:25.764624 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4754 00:40:25.767771 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4755 00:40:25.774714 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4756 00:40:25.777768 iDelay=205, Bit 10, Center 40 (-115 ~ 196) 312
4757 00:40:25.781377 iDelay=205, Bit 11, Center 28 (-131 ~ 188) 320
4758 00:40:25.784199 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4759 00:40:25.790878 iDelay=205, Bit 13, Center 44 (-107 ~ 196) 304
4760 00:40:25.794146 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4761 00:40:25.797542 iDelay=205, Bit 15, Center 44 (-115 ~ 204) 320
4762 00:40:25.797634 ==
4763 00:40:25.800806 Dram Type= 6, Freq= 0, CH_1, rank 1
4764 00:40:25.804330 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4765 00:40:25.807620 ==
4766 00:40:25.807708 DQS Delay:
4767 00:40:25.807773 DQS0 = 0, DQS1 = 0
4768 00:40:25.810444 DQM Delay:
4769 00:40:25.810532 DQM0 = 37, DQM1 = 35
4770 00:40:25.814159 DQ Delay:
4771 00:40:25.817782 DQ0 =40, DQ1 =36, DQ2 =24, DQ3 =36
4772 00:40:25.817869 DQ4 =36, DQ5 =48, DQ6 =48, DQ7 =32
4773 00:40:25.820874 DQ8 =20, DQ9 =24, DQ10 =40, DQ11 =28
4774 00:40:25.823776 DQ12 =44, DQ13 =44, DQ14 =40, DQ15 =44
4775 00:40:25.827083
4776 00:40:25.827170
4777 00:40:25.834394 [DQSOSCAuto] RK1, (LSB)MR18= 0x3a5f, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
4778 00:40:25.837975 CH1 RK1: MR19=808, MR18=3A5F
4779 00:40:25.843839 CH1_RK1: MR19=0x808, MR18=0x3A5F, DQSOSC=391, MR23=63, INC=171, DEC=114
4780 00:40:25.847395 [RxdqsGatingPostProcess] freq 600
4781 00:40:25.850449 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4782 00:40:25.853809 Pre-setting of DQS Precalculation
4783 00:40:25.860763 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4784 00:40:25.866880 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4785 00:40:25.873596 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4786 00:40:25.873780
4787 00:40:25.873892
4788 00:40:25.877408 [Calibration Summary] 1200 Mbps
4789 00:40:25.877546 CH 0, Rank 0
4790 00:40:25.880784 SW Impedance : PASS
4791 00:40:25.883617 DUTY Scan : NO K
4792 00:40:25.884252 ZQ Calibration : PASS
4793 00:40:25.887312 Jitter Meter : NO K
4794 00:40:25.889933 CBT Training : PASS
4795 00:40:25.890317 Write leveling : PASS
4796 00:40:25.893696 RX DQS gating : PASS
4797 00:40:25.896600 RX DQ/DQS(RDDQC) : PASS
4798 00:40:25.896987 TX DQ/DQS : PASS
4799 00:40:25.900255 RX DATLAT : PASS
4800 00:40:25.904000 RX DQ/DQS(Engine): PASS
4801 00:40:25.904481 TX OE : NO K
4802 00:40:25.906568 All Pass.
4803 00:40:25.907064
4804 00:40:25.907529 CH 0, Rank 1
4805 00:40:25.909955 SW Impedance : PASS
4806 00:40:25.910459 DUTY Scan : NO K
4807 00:40:25.912948 ZQ Calibration : PASS
4808 00:40:25.916524 Jitter Meter : NO K
4809 00:40:25.916959 CBT Training : PASS
4810 00:40:25.920106 Write leveling : PASS
4811 00:40:25.923006 RX DQS gating : PASS
4812 00:40:25.923497 RX DQ/DQS(RDDQC) : PASS
4813 00:40:25.927177 TX DQ/DQS : PASS
4814 00:40:25.929658 RX DATLAT : PASS
4815 00:40:25.930103 RX DQ/DQS(Engine): PASS
4816 00:40:25.932979 TX OE : NO K
4817 00:40:25.933431 All Pass.
4818 00:40:25.933768
4819 00:40:25.936151 CH 1, Rank 0
4820 00:40:25.936569 SW Impedance : PASS
4821 00:40:25.939213 DUTY Scan : NO K
4822 00:40:25.939633 ZQ Calibration : PASS
4823 00:40:25.943176 Jitter Meter : NO K
4824 00:40:25.946616 CBT Training : PASS
4825 00:40:25.947082 Write leveling : PASS
4826 00:40:25.949569 RX DQS gating : PASS
4827 00:40:25.952920 RX DQ/DQS(RDDQC) : PASS
4828 00:40:25.953490 TX DQ/DQS : PASS
4829 00:40:25.956062 RX DATLAT : PASS
4830 00:40:25.959540 RX DQ/DQS(Engine): PASS
4831 00:40:25.959958 TX OE : NO K
4832 00:40:25.962502 All Pass.
4833 00:40:25.962920
4834 00:40:25.963256 CH 1, Rank 1
4835 00:40:25.965694 SW Impedance : PASS
4836 00:40:25.966207 DUTY Scan : NO K
4837 00:40:25.969509 ZQ Calibration : PASS
4838 00:40:25.972657 Jitter Meter : NO K
4839 00:40:25.973131 CBT Training : PASS
4840 00:40:25.975831 Write leveling : PASS
4841 00:40:25.979040 RX DQS gating : PASS
4842 00:40:25.979465 RX DQ/DQS(RDDQC) : PASS
4843 00:40:25.982554 TX DQ/DQS : PASS
4844 00:40:25.985717 RX DATLAT : PASS
4845 00:40:25.986236 RX DQ/DQS(Engine): PASS
4846 00:40:25.988627 TX OE : NO K
4847 00:40:25.989048 All Pass.
4848 00:40:25.989425
4849 00:40:25.991998 DramC Write-DBI off
4850 00:40:25.995668 PER_BANK_REFRESH: Hybrid Mode
4851 00:40:25.996158 TX_TRACKING: ON
4852 00:40:26.005133 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4853 00:40:26.008893 [FAST_K] Save calibration result to emmc
4854 00:40:26.011977 dramc_set_vcore_voltage set vcore to 662500
4855 00:40:26.015518 Read voltage for 933, 3
4856 00:40:26.016033 Vio18 = 0
4857 00:40:26.016370 Vcore = 662500
4858 00:40:26.018722 Vdram = 0
4859 00:40:26.019142 Vddq = 0
4860 00:40:26.019471 Vmddr = 0
4861 00:40:26.025736 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4862 00:40:26.028372 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4863 00:40:26.031722 MEM_TYPE=3, freq_sel=17
4864 00:40:26.034885 sv_algorithm_assistance_LP4_1600
4865 00:40:26.039214 ============ PULL DRAM RESETB DOWN ============
4866 00:40:26.041934 ========== PULL DRAM RESETB DOWN end =========
4867 00:40:26.048559 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4868 00:40:26.052112 ===================================
4869 00:40:26.054655 LPDDR4 DRAM CONFIGURATION
4870 00:40:26.058404 ===================================
4871 00:40:26.058827 EX_ROW_EN[0] = 0x0
4872 00:40:26.061117 EX_ROW_EN[1] = 0x0
4873 00:40:26.061601 LP4Y_EN = 0x0
4874 00:40:26.065006 WORK_FSP = 0x0
4875 00:40:26.065466 WL = 0x3
4876 00:40:26.068113 RL = 0x3
4877 00:40:26.068549 BL = 0x2
4878 00:40:26.071055 RPST = 0x0
4879 00:40:26.071538 RD_PRE = 0x0
4880 00:40:26.074429 WR_PRE = 0x1
4881 00:40:26.074848 WR_PST = 0x0
4882 00:40:26.077966 DBI_WR = 0x0
4883 00:40:26.081480 DBI_RD = 0x0
4884 00:40:26.081992 OTF = 0x1
4885 00:40:26.084558 ===================================
4886 00:40:26.087945 ===================================
4887 00:40:26.088472 ANA top config
4888 00:40:26.090987 ===================================
4889 00:40:26.094430 DLL_ASYNC_EN = 0
4890 00:40:26.098066 ALL_SLAVE_EN = 1
4891 00:40:26.101321 NEW_RANK_MODE = 1
4892 00:40:26.104306 DLL_IDLE_MODE = 1
4893 00:40:26.104892 LP45_APHY_COMB_EN = 1
4894 00:40:26.107628 TX_ODT_DIS = 1
4895 00:40:26.110843 NEW_8X_MODE = 1
4896 00:40:26.114760 ===================================
4897 00:40:26.117899 ===================================
4898 00:40:26.120526 data_rate = 1866
4899 00:40:26.124231 CKR = 1
4900 00:40:26.127648 DQ_P2S_RATIO = 8
4901 00:40:26.128158 ===================================
4902 00:40:26.130864 CA_P2S_RATIO = 8
4903 00:40:26.134340 DQ_CA_OPEN = 0
4904 00:40:26.137386 DQ_SEMI_OPEN = 0
4905 00:40:26.140688 CA_SEMI_OPEN = 0
4906 00:40:26.144085 CA_FULL_RATE = 0
4907 00:40:26.144613 DQ_CKDIV4_EN = 1
4908 00:40:26.147596 CA_CKDIV4_EN = 1
4909 00:40:26.150866 CA_PREDIV_EN = 0
4910 00:40:26.154328 PH8_DLY = 0
4911 00:40:26.157138 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4912 00:40:26.160148 DQ_AAMCK_DIV = 4
4913 00:40:26.163707 CA_AAMCK_DIV = 4
4914 00:40:26.164221 CA_ADMCK_DIV = 4
4915 00:40:26.167436 DQ_TRACK_CA_EN = 0
4916 00:40:26.170209 CA_PICK = 933
4917 00:40:26.174083 CA_MCKIO = 933
4918 00:40:26.177185 MCKIO_SEMI = 0
4919 00:40:26.180369 PLL_FREQ = 3732
4920 00:40:26.183092 DQ_UI_PI_RATIO = 32
4921 00:40:26.183512 CA_UI_PI_RATIO = 0
4922 00:40:26.186957 ===================================
4923 00:40:26.189953 ===================================
4924 00:40:26.193435 memory_type:LPDDR4
4925 00:40:26.197054 GP_NUM : 10
4926 00:40:26.197627 SRAM_EN : 1
4927 00:40:26.199840 MD32_EN : 0
4928 00:40:26.202866 ===================================
4929 00:40:26.206531 [ANA_INIT] >>>>>>>>>>>>>>
4930 00:40:26.209909 <<<<<< [CONFIGURE PHASE]: ANA_TX
4931 00:40:26.213447 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4932 00:40:26.216501 ===================================
4933 00:40:26.216930 data_rate = 1866,PCW = 0X8f00
4934 00:40:26.220522 ===================================
4935 00:40:26.223069 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4936 00:40:26.229827 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4937 00:40:26.236000 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4938 00:40:26.239615 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4939 00:40:26.242742 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4940 00:40:26.246387 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4941 00:40:26.249564 [ANA_INIT] flow start
4942 00:40:26.252905 [ANA_INIT] PLL >>>>>>>>
4943 00:40:26.253365 [ANA_INIT] PLL <<<<<<<<
4944 00:40:26.255989 [ANA_INIT] MIDPI >>>>>>>>
4945 00:40:26.259142 [ANA_INIT] MIDPI <<<<<<<<
4946 00:40:26.259561 [ANA_INIT] DLL >>>>>>>>
4947 00:40:26.262297 [ANA_INIT] flow end
4948 00:40:26.265970 ============ LP4 DIFF to SE enter ============
4949 00:40:26.272647 ============ LP4 DIFF to SE exit ============
4950 00:40:26.273160 [ANA_INIT] <<<<<<<<<<<<<
4951 00:40:26.275834 [Flow] Enable top DCM control >>>>>
4952 00:40:26.278939 [Flow] Enable top DCM control <<<<<
4953 00:40:26.282276 Enable DLL master slave shuffle
4954 00:40:26.289311 ==============================================================
4955 00:40:26.289832 Gating Mode config
4956 00:40:26.295151 ==============================================================
4957 00:40:26.298566 Config description:
4958 00:40:26.308590 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4959 00:40:26.315256 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4960 00:40:26.318776 SELPH_MODE 0: By rank 1: By Phase
4961 00:40:26.324815 ==============================================================
4962 00:40:26.328170 GAT_TRACK_EN = 1
4963 00:40:26.331063 RX_GATING_MODE = 2
4964 00:40:26.335026 RX_GATING_TRACK_MODE = 2
4965 00:40:26.335541 SELPH_MODE = 1
4966 00:40:26.338798 PICG_EARLY_EN = 1
4967 00:40:26.341936 VALID_LAT_VALUE = 1
4968 00:40:26.348174 ==============================================================
4969 00:40:26.351563 Enter into Gating configuration >>>>
4970 00:40:26.354347 Exit from Gating configuration <<<<
4971 00:40:26.357667 Enter into DVFS_PRE_config >>>>>
4972 00:40:26.367870 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4973 00:40:26.370824 Exit from DVFS_PRE_config <<<<<
4974 00:40:26.374109 Enter into PICG configuration >>>>
4975 00:40:26.377841 Exit from PICG configuration <<<<
4976 00:40:26.381222 [RX_INPUT] configuration >>>>>
4977 00:40:26.384180 [RX_INPUT] configuration <<<<<
4978 00:40:26.387308 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4979 00:40:26.394080 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4980 00:40:26.400543 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4981 00:40:26.407363 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4982 00:40:26.413706 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4983 00:40:26.420613 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4984 00:40:26.424193 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4985 00:40:26.427362 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4986 00:40:26.430072 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4987 00:40:26.436939 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4988 00:40:26.440031 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4989 00:40:26.443464 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4990 00:40:26.447247 ===================================
4991 00:40:26.450228 LPDDR4 DRAM CONFIGURATION
4992 00:40:26.453508 ===================================
4993 00:40:26.454035 EX_ROW_EN[0] = 0x0
4994 00:40:26.456653 EX_ROW_EN[1] = 0x0
4995 00:40:26.460550 LP4Y_EN = 0x0
4996 00:40:26.460968 WORK_FSP = 0x0
4997 00:40:26.463180 WL = 0x3
4998 00:40:26.463597 RL = 0x3
4999 00:40:26.466492 BL = 0x2
5000 00:40:26.466914 RPST = 0x0
5001 00:40:26.469943 RD_PRE = 0x0
5002 00:40:26.470361 WR_PRE = 0x1
5003 00:40:26.473213 WR_PST = 0x0
5004 00:40:26.473651 DBI_WR = 0x0
5005 00:40:26.476224 DBI_RD = 0x0
5006 00:40:26.476646 OTF = 0x1
5007 00:40:26.479652 ===================================
5008 00:40:26.483204 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5009 00:40:26.490006 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5010 00:40:26.493073 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5011 00:40:26.496170 ===================================
5012 00:40:26.499041 LPDDR4 DRAM CONFIGURATION
5013 00:40:26.502673 ===================================
5014 00:40:26.503118 EX_ROW_EN[0] = 0x10
5015 00:40:26.505880 EX_ROW_EN[1] = 0x0
5016 00:40:26.509013 LP4Y_EN = 0x0
5017 00:40:26.509473 WORK_FSP = 0x0
5018 00:40:26.512562 WL = 0x3
5019 00:40:26.512980 RL = 0x3
5020 00:40:26.516131 BL = 0x2
5021 00:40:26.516552 RPST = 0x0
5022 00:40:26.519547 RD_PRE = 0x0
5023 00:40:26.519966 WR_PRE = 0x1
5024 00:40:26.522529 WR_PST = 0x0
5025 00:40:26.522951 DBI_WR = 0x0
5026 00:40:26.525353 DBI_RD = 0x0
5027 00:40:26.525777 OTF = 0x1
5028 00:40:26.528902 ===================================
5029 00:40:26.534972 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5030 00:40:26.539504 nWR fixed to 30
5031 00:40:26.542885 [ModeRegInit_LP4] CH0 RK0
5032 00:40:26.543068 [ModeRegInit_LP4] CH0 RK1
5033 00:40:26.546145 [ModeRegInit_LP4] CH1 RK0
5034 00:40:26.549802 [ModeRegInit_LP4] CH1 RK1
5035 00:40:26.549933 match AC timing 9
5036 00:40:26.555927 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5037 00:40:26.559446 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5038 00:40:26.562707 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5039 00:40:26.569207 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5040 00:40:26.572746 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5041 00:40:26.572831 ==
5042 00:40:26.575988 Dram Type= 6, Freq= 0, CH_0, rank 0
5043 00:40:26.580197 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5044 00:40:26.580653 ==
5045 00:40:26.586006 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5046 00:40:26.592973 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5047 00:40:26.596506 [CA 0] Center 37 (7~68) winsize 62
5048 00:40:26.599477 [CA 1] Center 37 (7~68) winsize 62
5049 00:40:26.603407 [CA 2] Center 34 (4~65) winsize 62
5050 00:40:26.606132 [CA 3] Center 34 (4~65) winsize 62
5051 00:40:26.609702 [CA 4] Center 33 (3~64) winsize 62
5052 00:40:26.613081 [CA 5] Center 33 (3~63) winsize 61
5053 00:40:26.613537
5054 00:40:26.616327 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5055 00:40:26.616738
5056 00:40:26.619549 [CATrainingPosCal] consider 1 rank data
5057 00:40:26.622671 u2DelayCellTimex100 = 270/100 ps
5058 00:40:26.626183 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5059 00:40:26.629242 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5060 00:40:26.632608 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5061 00:40:26.635573 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5062 00:40:26.642984 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5063 00:40:26.645883 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5064 00:40:26.646302
5065 00:40:26.648949 CA PerBit enable=1, Macro0, CA PI delay=33
5066 00:40:26.649391
5067 00:40:26.652291 [CBTSetCACLKResult] CA Dly = 33
5068 00:40:26.652711 CS Dly: 6 (0~37)
5069 00:40:26.653041 ==
5070 00:40:26.655785 Dram Type= 6, Freq= 0, CH_0, rank 1
5071 00:40:26.662088 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5072 00:40:26.662512 ==
5073 00:40:26.665606 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5074 00:40:26.671943 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5075 00:40:26.675772 [CA 0] Center 38 (7~69) winsize 63
5076 00:40:26.678534 [CA 1] Center 37 (7~68) winsize 62
5077 00:40:26.682113 [CA 2] Center 34 (4~65) winsize 62
5078 00:40:26.685232 [CA 3] Center 34 (4~65) winsize 62
5079 00:40:26.688393 [CA 4] Center 33 (3~64) winsize 62
5080 00:40:26.691754 [CA 5] Center 33 (3~63) winsize 61
5081 00:40:26.692310
5082 00:40:26.694890 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5083 00:40:26.695331
5084 00:40:26.698469 [CATrainingPosCal] consider 2 rank data
5085 00:40:26.701801 u2DelayCellTimex100 = 270/100 ps
5086 00:40:26.705203 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5087 00:40:26.708360 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5088 00:40:26.714869 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5089 00:40:26.718131 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5090 00:40:26.721485 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5091 00:40:26.724772 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5092 00:40:26.725192
5093 00:40:26.728271 CA PerBit enable=1, Macro0, CA PI delay=33
5094 00:40:26.728688
5095 00:40:26.731567 [CBTSetCACLKResult] CA Dly = 33
5096 00:40:26.731989 CS Dly: 7 (0~39)
5097 00:40:26.732321
5098 00:40:26.734779 ----->DramcWriteLeveling(PI) begin...
5099 00:40:26.738238 ==
5100 00:40:26.741679 Dram Type= 6, Freq= 0, CH_0, rank 0
5101 00:40:26.745003 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5102 00:40:26.745452 ==
5103 00:40:26.748539 Write leveling (Byte 0): 30 => 30
5104 00:40:26.751193 Write leveling (Byte 1): 29 => 29
5105 00:40:26.754683 DramcWriteLeveling(PI) end<-----
5106 00:40:26.755102
5107 00:40:26.755432 ==
5108 00:40:26.757763 Dram Type= 6, Freq= 0, CH_0, rank 0
5109 00:40:26.761390 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5110 00:40:26.761816 ==
5111 00:40:26.764342 [Gating] SW mode calibration
5112 00:40:26.771708 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5113 00:40:26.777627 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5114 00:40:26.781686 0 14 0 | B1->B0 | 2928 3434 | 1 0 | (0 0) (0 0)
5115 00:40:26.784286 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5116 00:40:26.790909 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5117 00:40:26.794056 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5118 00:40:26.797358 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5119 00:40:26.804127 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5120 00:40:26.807623 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5121 00:40:26.811513 0 14 28 | B1->B0 | 3434 2a2a | 0 0 | (0 0) (1 1)
5122 00:40:26.817005 0 15 0 | B1->B0 | 2f2f 2424 | 1 0 | (1 1) (1 0)
5123 00:40:26.820737 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5124 00:40:26.824205 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5125 00:40:26.830066 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5126 00:40:26.834224 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5127 00:40:26.836960 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5128 00:40:26.843675 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5129 00:40:26.846912 0 15 28 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
5130 00:40:26.850818 1 0 0 | B1->B0 | 3837 4646 | 1 0 | (0 0) (0 0)
5131 00:40:26.857213 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5132 00:40:26.860263 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5133 00:40:26.863683 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5134 00:40:26.870572 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5135 00:40:26.873428 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5136 00:40:26.876754 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5137 00:40:26.883465 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5138 00:40:26.886465 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5139 00:40:26.889674 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5140 00:40:26.896255 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5141 00:40:26.899355 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5142 00:40:26.902913 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5143 00:40:26.909211 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5144 00:40:26.912806 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5145 00:40:26.916276 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5146 00:40:26.922598 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5147 00:40:26.926289 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5148 00:40:26.929699 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5149 00:40:26.935717 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5150 00:40:26.939140 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5151 00:40:26.943445 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5152 00:40:26.949060 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5153 00:40:26.952362 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
5154 00:40:26.955992 Total UI for P1: 0, mck2ui 16
5155 00:40:26.958828 best dqsien dly found for B0: ( 1, 2, 24)
5156 00:40:26.962623 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5157 00:40:26.968887 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5158 00:40:26.972372 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5159 00:40:26.975559 Total UI for P1: 0, mck2ui 16
5160 00:40:26.978819 best dqsien dly found for B1: ( 1, 3, 2)
5161 00:40:26.982564 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5162 00:40:26.985720 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5163 00:40:26.986230
5164 00:40:26.989359 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5165 00:40:26.992346 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5166 00:40:26.995919 [Gating] SW calibration Done
5167 00:40:26.996646 ==
5168 00:40:26.999021 Dram Type= 6, Freq= 0, CH_0, rank 0
5169 00:40:27.002028 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5170 00:40:27.002443 ==
5171 00:40:27.005552 RX Vref Scan: 0
5172 00:40:27.005962
5173 00:40:27.008931 RX Vref 0 -> 0, step: 1
5174 00:40:27.009481
5175 00:40:27.009818 RX Delay -80 -> 252, step: 8
5176 00:40:27.015537 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5177 00:40:27.019128 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5178 00:40:27.022434 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5179 00:40:27.025324 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5180 00:40:27.028577 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5181 00:40:27.031702 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5182 00:40:27.038773 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5183 00:40:27.041629 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5184 00:40:27.045699 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5185 00:40:27.048810 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5186 00:40:27.051836 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5187 00:40:27.058296 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5188 00:40:27.061195 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5189 00:40:27.064935 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5190 00:40:27.068618 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5191 00:40:27.071300 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5192 00:40:27.071823 ==
5193 00:40:27.075587 Dram Type= 6, Freq= 0, CH_0, rank 0
5194 00:40:27.081772 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5195 00:40:27.082186 ==
5196 00:40:27.082513 DQS Delay:
5197 00:40:27.082815 DQS0 = 0, DQS1 = 0
5198 00:40:27.084668 DQM Delay:
5199 00:40:27.085219 DQM0 = 100, DQM1 = 89
5200 00:40:27.087962 DQ Delay:
5201 00:40:27.091664 DQ0 =103, DQ1 =99, DQ2 =95, DQ3 =95
5202 00:40:27.094635 DQ4 =103, DQ5 =87, DQ6 =111, DQ7 =107
5203 00:40:27.098107 DQ8 =83, DQ9 =75, DQ10 =91, DQ11 =83
5204 00:40:27.101661 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5205 00:40:27.102091
5206 00:40:27.102432
5207 00:40:27.102733 ==
5208 00:40:27.104369 Dram Type= 6, Freq= 0, CH_0, rank 0
5209 00:40:27.108114 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5210 00:40:27.108653 ==
5211 00:40:27.109133
5212 00:40:27.109642
5213 00:40:27.110903 TX Vref Scan disable
5214 00:40:27.114427 == TX Byte 0 ==
5215 00:40:27.117857 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5216 00:40:27.121119 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5217 00:40:27.124420 == TX Byte 1 ==
5218 00:40:27.127924 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5219 00:40:27.130794 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5220 00:40:27.131314 ==
5221 00:40:27.134658 Dram Type= 6, Freq= 0, CH_0, rank 0
5222 00:40:27.140617 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5223 00:40:27.141149 ==
5224 00:40:27.141597
5225 00:40:27.142091
5226 00:40:27.142535 TX Vref Scan disable
5227 00:40:27.144855 == TX Byte 0 ==
5228 00:40:27.148008 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5229 00:40:27.154735 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5230 00:40:27.155233 == TX Byte 1 ==
5231 00:40:27.157847 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5232 00:40:27.164207 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5233 00:40:27.164679
5234 00:40:27.165012 [DATLAT]
5235 00:40:27.165359 Freq=933, CH0 RK0
5236 00:40:27.165668
5237 00:40:27.168033 DATLAT Default: 0xd
5238 00:40:27.171351 0, 0xFFFF, sum = 0
5239 00:40:27.171876 1, 0xFFFF, sum = 0
5240 00:40:27.174507 2, 0xFFFF, sum = 0
5241 00:40:27.175075 3, 0xFFFF, sum = 0
5242 00:40:27.177338 4, 0xFFFF, sum = 0
5243 00:40:27.177723 5, 0xFFFF, sum = 0
5244 00:40:27.180808 6, 0xFFFF, sum = 0
5245 00:40:27.181406 7, 0xFFFF, sum = 0
5246 00:40:27.184166 8, 0xFFFF, sum = 0
5247 00:40:27.184694 9, 0xFFFF, sum = 0
5248 00:40:27.187339 10, 0x0, sum = 1
5249 00:40:27.187855 11, 0x0, sum = 2
5250 00:40:27.191126 12, 0x0, sum = 3
5251 00:40:27.191619 13, 0x0, sum = 4
5252 00:40:27.193966 best_step = 11
5253 00:40:27.194537
5254 00:40:27.195007 ==
5255 00:40:27.197085 Dram Type= 6, Freq= 0, CH_0, rank 0
5256 00:40:27.200289 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5257 00:40:27.200724 ==
5258 00:40:27.201154 RX Vref Scan: 1
5259 00:40:27.203660
5260 00:40:27.204085 RX Vref 0 -> 0, step: 1
5261 00:40:27.204558
5262 00:40:27.207770 RX Delay -61 -> 252, step: 4
5263 00:40:27.208186
5264 00:40:27.210580 Set Vref, RX VrefLevel [Byte0]: 53
5265 00:40:27.213434 [Byte1]: 58
5266 00:40:27.217541
5267 00:40:27.217954 Final RX Vref Byte 0 = 53 to rank0
5268 00:40:27.220775 Final RX Vref Byte 1 = 58 to rank0
5269 00:40:27.223572 Final RX Vref Byte 0 = 53 to rank1
5270 00:40:27.227224 Final RX Vref Byte 1 = 58 to rank1==
5271 00:40:27.230272 Dram Type= 6, Freq= 0, CH_0, rank 0
5272 00:40:27.236928 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5273 00:40:27.237119 ==
5274 00:40:27.237279 DQS Delay:
5275 00:40:27.239811 DQS0 = 0, DQS1 = 0
5276 00:40:27.239971 DQM Delay:
5277 00:40:27.240140 DQM0 = 99, DQM1 = 87
5278 00:40:27.243471 DQ Delay:
5279 00:40:27.246471 DQ0 =100, DQ1 =98, DQ2 =94, DQ3 =96
5280 00:40:27.249637 DQ4 =100, DQ5 =90, DQ6 =108, DQ7 =106
5281 00:40:27.253198 DQ8 =78, DQ9 =74, DQ10 =88, DQ11 =84
5282 00:40:27.256883 DQ12 =96, DQ13 =92, DQ14 =96, DQ15 =94
5283 00:40:27.256983
5284 00:40:27.257061
5285 00:40:27.263166 [DQSOSCAuto] RK0, (LSB)MR18= 0x1b16, (MSB)MR19= 0x505, tDQSOscB0 = 414 ps tDQSOscB1 = 413 ps
5286 00:40:27.266374 CH0 RK0: MR19=505, MR18=1B16
5287 00:40:27.272990 CH0_RK0: MR19=0x505, MR18=0x1B16, DQSOSC=413, MR23=63, INC=63, DEC=42
5288 00:40:27.273092
5289 00:40:27.276032 ----->DramcWriteLeveling(PI) begin...
5290 00:40:27.276134 ==
5291 00:40:27.279747 Dram Type= 6, Freq= 0, CH_0, rank 1
5292 00:40:27.283074 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5293 00:40:27.283250 ==
5294 00:40:27.286137 Write leveling (Byte 0): 33 => 33
5295 00:40:27.289491 Write leveling (Byte 1): 25 => 25
5296 00:40:27.292914 DramcWriteLeveling(PI) end<-----
5297 00:40:27.293054
5298 00:40:27.293149 ==
5299 00:40:27.295878 Dram Type= 6, Freq= 0, CH_0, rank 1
5300 00:40:27.302242 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5301 00:40:27.302395 ==
5302 00:40:27.302514 [Gating] SW mode calibration
5303 00:40:27.313064 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5304 00:40:27.316004 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5305 00:40:27.322742 0 14 0 | B1->B0 | 2e2e 3434 | 0 1 | (0 0) (1 1)
5306 00:40:27.326696 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5307 00:40:27.329055 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5308 00:40:27.336146 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5309 00:40:27.339322 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5310 00:40:27.342466 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5311 00:40:27.349055 0 14 24 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
5312 00:40:27.352407 0 14 28 | B1->B0 | 3333 2a2a | 0 0 | (0 0) (0 0)
5313 00:40:27.355608 0 15 0 | B1->B0 | 2f2f 2323 | 0 0 | (0 1) (0 0)
5314 00:40:27.362292 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5315 00:40:27.365417 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5316 00:40:27.368702 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5317 00:40:27.375351 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5318 00:40:27.378384 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5319 00:40:27.382173 0 15 24 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
5320 00:40:27.388464 0 15 28 | B1->B0 | 3030 4141 | 0 0 | (0 0) (1 1)
5321 00:40:27.391422 1 0 0 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
5322 00:40:27.394837 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5323 00:40:27.401233 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5324 00:40:27.404901 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5325 00:40:27.408142 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5326 00:40:27.414560 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5327 00:40:27.418198 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5328 00:40:27.420949 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5329 00:40:27.427482 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5330 00:40:27.431520 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5331 00:40:27.434427 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5332 00:40:27.440851 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5333 00:40:27.444358 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5334 00:40:27.448066 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5335 00:40:27.454260 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5336 00:40:27.457248 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5337 00:40:27.460612 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5338 00:40:27.467160 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5339 00:40:27.470880 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5340 00:40:27.474390 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5341 00:40:27.480529 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5342 00:40:27.483595 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5343 00:40:27.486716 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5344 00:40:27.493731 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5345 00:40:27.496892 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5346 00:40:27.500193 Total UI for P1: 0, mck2ui 16
5347 00:40:27.503765 best dqsien dly found for B0: ( 1, 2, 26)
5348 00:40:27.506909 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5349 00:40:27.509859 Total UI for P1: 0, mck2ui 16
5350 00:40:27.513564 best dqsien dly found for B1: ( 1, 3, 0)
5351 00:40:27.516438 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5352 00:40:27.520540 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5353 00:40:27.521051
5354 00:40:27.526575 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5355 00:40:27.530216 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5356 00:40:27.530625 [Gating] SW calibration Done
5357 00:40:27.533308 ==
5358 00:40:27.536174 Dram Type= 6, Freq= 0, CH_0, rank 1
5359 00:40:27.539836 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5360 00:40:27.540253 ==
5361 00:40:27.540581 RX Vref Scan: 0
5362 00:40:27.540887
5363 00:40:27.543472 RX Vref 0 -> 0, step: 1
5364 00:40:27.543884
5365 00:40:27.546079 RX Delay -80 -> 252, step: 8
5366 00:40:27.549351 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5367 00:40:27.552674 iDelay=200, Bit 1, Center 99 (0 ~ 199) 200
5368 00:40:27.556098 iDelay=200, Bit 2, Center 95 (0 ~ 191) 192
5369 00:40:27.563469 iDelay=200, Bit 3, Center 91 (-8 ~ 191) 200
5370 00:40:27.566165 iDelay=200, Bit 4, Center 103 (8 ~ 199) 192
5371 00:40:27.568935 iDelay=200, Bit 5, Center 87 (-8 ~ 183) 192
5372 00:40:27.572678 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5373 00:40:27.575654 iDelay=200, Bit 7, Center 103 (8 ~ 199) 192
5374 00:40:27.578871 iDelay=200, Bit 8, Center 87 (0 ~ 175) 176
5375 00:40:27.585645 iDelay=200, Bit 9, Center 79 (-8 ~ 167) 176
5376 00:40:27.588722 iDelay=200, Bit 10, Center 91 (0 ~ 183) 184
5377 00:40:27.592083 iDelay=200, Bit 11, Center 87 (0 ~ 175) 176
5378 00:40:27.595369 iDelay=200, Bit 12, Center 99 (8 ~ 191) 184
5379 00:40:27.598679 iDelay=200, Bit 13, Center 99 (8 ~ 191) 184
5380 00:40:27.605240 iDelay=200, Bit 14, Center 99 (8 ~ 191) 184
5381 00:40:27.608425 iDelay=200, Bit 15, Center 99 (8 ~ 191) 184
5382 00:40:27.608520 ==
5383 00:40:27.611714 Dram Type= 6, Freq= 0, CH_0, rank 1
5384 00:40:27.615057 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5385 00:40:27.615222 ==
5386 00:40:27.615298 DQS Delay:
5387 00:40:27.618620 DQS0 = 0, DQS1 = 0
5388 00:40:27.618782 DQM Delay:
5389 00:40:27.621739 DQM0 = 97, DQM1 = 92
5390 00:40:27.621886 DQ Delay:
5391 00:40:27.625341 DQ0 =95, DQ1 =99, DQ2 =95, DQ3 =91
5392 00:40:27.628390 DQ4 =103, DQ5 =87, DQ6 =103, DQ7 =103
5393 00:40:27.631944 DQ8 =87, DQ9 =79, DQ10 =91, DQ11 =87
5394 00:40:27.635286 DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =99
5395 00:40:27.635447
5396 00:40:27.635519
5397 00:40:27.635579 ==
5398 00:40:27.638304 Dram Type= 6, Freq= 0, CH_0, rank 1
5399 00:40:27.644822 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5400 00:40:27.644929 ==
5401 00:40:27.645020
5402 00:40:27.645107
5403 00:40:27.645192 TX Vref Scan disable
5404 00:40:27.648438 == TX Byte 0 ==
5405 00:40:27.651863 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5406 00:40:27.658522 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5407 00:40:27.658691 == TX Byte 1 ==
5408 00:40:27.661834 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5409 00:40:27.667693 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5410 00:40:27.667857 ==
5411 00:40:27.671350 Dram Type= 6, Freq= 0, CH_0, rank 1
5412 00:40:27.674749 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5413 00:40:27.674878 ==
5414 00:40:27.674974
5415 00:40:27.675061
5416 00:40:27.677921 TX Vref Scan disable
5417 00:40:27.682121 == TX Byte 0 ==
5418 00:40:27.684438 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5419 00:40:27.687831 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5420 00:40:27.691311 == TX Byte 1 ==
5421 00:40:27.694466 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5422 00:40:27.697660 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5423 00:40:27.697861
5424 00:40:27.698019 [DATLAT]
5425 00:40:27.701306 Freq=933, CH0 RK1
5426 00:40:27.701625
5427 00:40:27.704151 DATLAT Default: 0xb
5428 00:40:27.704603 0, 0xFFFF, sum = 0
5429 00:40:27.707684 1, 0xFFFF, sum = 0
5430 00:40:27.707986 2, 0xFFFF, sum = 0
5431 00:40:27.710876 3, 0xFFFF, sum = 0
5432 00:40:27.711268 4, 0xFFFF, sum = 0
5433 00:40:27.714684 5, 0xFFFF, sum = 0
5434 00:40:27.715072 6, 0xFFFF, sum = 0
5435 00:40:27.717380 7, 0xFFFF, sum = 0
5436 00:40:27.717788 8, 0xFFFF, sum = 0
5437 00:40:27.720631 9, 0xFFFF, sum = 0
5438 00:40:27.721018 10, 0x0, sum = 1
5439 00:40:27.724140 11, 0x0, sum = 2
5440 00:40:27.724526 12, 0x0, sum = 3
5441 00:40:27.727670 13, 0x0, sum = 4
5442 00:40:27.728056 best_step = 11
5443 00:40:27.728359
5444 00:40:27.728640 ==
5445 00:40:27.730980 Dram Type= 6, Freq= 0, CH_0, rank 1
5446 00:40:27.734029 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5447 00:40:27.737093 ==
5448 00:40:27.737397 RX Vref Scan: 0
5449 00:40:27.737620
5450 00:40:27.740913 RX Vref 0 -> 0, step: 1
5451 00:40:27.741125
5452 00:40:27.743863 RX Delay -53 -> 252, step: 4
5453 00:40:27.747408 iDelay=195, Bit 0, Center 94 (7 ~ 182) 176
5454 00:40:27.750183 iDelay=195, Bit 1, Center 98 (7 ~ 190) 184
5455 00:40:27.753272 iDelay=195, Bit 2, Center 90 (-1 ~ 182) 184
5456 00:40:27.760354 iDelay=195, Bit 3, Center 96 (7 ~ 186) 180
5457 00:40:27.763497 iDelay=195, Bit 4, Center 100 (11 ~ 190) 180
5458 00:40:27.766695 iDelay=195, Bit 5, Center 88 (-1 ~ 178) 180
5459 00:40:27.770400 iDelay=195, Bit 6, Center 108 (23 ~ 194) 172
5460 00:40:27.773859 iDelay=195, Bit 7, Center 104 (15 ~ 194) 180
5461 00:40:27.779844 iDelay=195, Bit 8, Center 80 (-5 ~ 166) 172
5462 00:40:27.783529 iDelay=195, Bit 9, Center 76 (-9 ~ 162) 172
5463 00:40:27.786879 iDelay=195, Bit 10, Center 90 (-1 ~ 182) 184
5464 00:40:27.789618 iDelay=195, Bit 11, Center 82 (-5 ~ 170) 176
5465 00:40:27.792781 iDelay=195, Bit 12, Center 92 (3 ~ 182) 180
5466 00:40:27.800672 iDelay=195, Bit 13, Center 94 (3 ~ 186) 184
5467 00:40:27.803305 iDelay=195, Bit 14, Center 98 (7 ~ 190) 184
5468 00:40:27.806600 iDelay=195, Bit 15, Center 96 (11 ~ 182) 172
5469 00:40:27.806835 ==
5470 00:40:27.809821 Dram Type= 6, Freq= 0, CH_0, rank 1
5471 00:40:27.812828 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5472 00:40:27.812979 ==
5473 00:40:27.816181 DQS Delay:
5474 00:40:27.816331 DQS0 = 0, DQS1 = 0
5475 00:40:27.819776 DQM Delay:
5476 00:40:27.819925 DQM0 = 97, DQM1 = 88
5477 00:40:27.820045 DQ Delay:
5478 00:40:27.823146 DQ0 =94, DQ1 =98, DQ2 =90, DQ3 =96
5479 00:40:27.825885 DQ4 =100, DQ5 =88, DQ6 =108, DQ7 =104
5480 00:40:27.829241 DQ8 =80, DQ9 =76, DQ10 =90, DQ11 =82
5481 00:40:27.832895 DQ12 =92, DQ13 =94, DQ14 =98, DQ15 =96
5482 00:40:27.833066
5483 00:40:27.833202
5484 00:40:27.843070 [DQSOSCAuto] RK1, (LSB)MR18= 0x1a17, (MSB)MR19= 0x505, tDQSOscB0 = 414 ps tDQSOscB1 = 413 ps
5485 00:40:27.846835 CH0 RK1: MR19=505, MR18=1A17
5486 00:40:27.853014 CH0_RK1: MR19=0x505, MR18=0x1A17, DQSOSC=413, MR23=63, INC=63, DEC=42
5487 00:40:27.853686 [RxdqsGatingPostProcess] freq 933
5488 00:40:27.859362 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5489 00:40:27.862866 best DQS0 dly(2T, 0.5T) = (0, 10)
5490 00:40:27.865658 best DQS1 dly(2T, 0.5T) = (0, 11)
5491 00:40:27.869244 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5492 00:40:27.872725 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5493 00:40:27.875730 best DQS0 dly(2T, 0.5T) = (0, 10)
5494 00:40:27.878958 best DQS1 dly(2T, 0.5T) = (0, 11)
5495 00:40:27.882602 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5496 00:40:27.885772 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5497 00:40:27.889304 Pre-setting of DQS Precalculation
5498 00:40:27.892050 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5499 00:40:27.892488 ==
5500 00:40:27.895062 Dram Type= 6, Freq= 0, CH_1, rank 0
5501 00:40:27.902203 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5502 00:40:27.902547 ==
5503 00:40:27.905063 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5504 00:40:27.911909 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5505 00:40:27.914763 [CA 0] Center 36 (6~67) winsize 62
5506 00:40:27.918132 [CA 1] Center 36 (6~67) winsize 62
5507 00:40:27.921637 [CA 2] Center 34 (4~64) winsize 61
5508 00:40:27.925114 [CA 3] Center 34 (4~64) winsize 61
5509 00:40:27.927917 [CA 4] Center 34 (4~64) winsize 61
5510 00:40:27.931913 [CA 5] Center 33 (3~64) winsize 62
5511 00:40:27.932108
5512 00:40:27.934939 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5513 00:40:27.935174
5514 00:40:27.938124 [CATrainingPosCal] consider 1 rank data
5515 00:40:27.941253 u2DelayCellTimex100 = 270/100 ps
5516 00:40:27.944979 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5517 00:40:27.951153 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5518 00:40:27.954750 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5519 00:40:27.958285 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5520 00:40:27.961449 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5521 00:40:27.964655 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5522 00:40:27.965037
5523 00:40:27.967888 CA PerBit enable=1, Macro0, CA PI delay=33
5524 00:40:27.968301
5525 00:40:27.971231 [CBTSetCACLKResult] CA Dly = 33
5526 00:40:27.971726 CS Dly: 5 (0~36)
5527 00:40:27.974479 ==
5528 00:40:27.978104 Dram Type= 6, Freq= 0, CH_1, rank 1
5529 00:40:27.981330 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5530 00:40:27.981769 ==
5531 00:40:27.987915 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5532 00:40:27.991130 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5533 00:40:27.994941 [CA 0] Center 36 (6~67) winsize 62
5534 00:40:27.998576 [CA 1] Center 36 (6~67) winsize 62
5535 00:40:28.001297 [CA 2] Center 34 (4~65) winsize 62
5536 00:40:28.005022 [CA 3] Center 33 (3~64) winsize 62
5537 00:40:28.008020 [CA 4] Center 33 (3~64) winsize 62
5538 00:40:28.011539 [CA 5] Center 33 (3~64) winsize 62
5539 00:40:28.011955
5540 00:40:28.014486 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5541 00:40:28.014904
5542 00:40:28.017743 [CATrainingPosCal] consider 2 rank data
5543 00:40:28.021202 u2DelayCellTimex100 = 270/100 ps
5544 00:40:28.024432 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5545 00:40:28.030955 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5546 00:40:28.034293 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5547 00:40:28.037660 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5548 00:40:28.040855 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5549 00:40:28.044415 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5550 00:40:28.044715
5551 00:40:28.047899 CA PerBit enable=1, Macro0, CA PI delay=33
5552 00:40:28.048196
5553 00:40:28.051133 [CBTSetCACLKResult] CA Dly = 33
5554 00:40:28.054497 CS Dly: 6 (0~38)
5555 00:40:28.054896
5556 00:40:28.057728 ----->DramcWriteLeveling(PI) begin...
5557 00:40:28.058030 ==
5558 00:40:28.060650 Dram Type= 6, Freq= 0, CH_1, rank 0
5559 00:40:28.063904 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5560 00:40:28.064207 ==
5561 00:40:28.066982 Write leveling (Byte 0): 24 => 24
5562 00:40:28.070298 Write leveling (Byte 1): 25 => 25
5563 00:40:28.073857 DramcWriteLeveling(PI) end<-----
5564 00:40:28.074154
5565 00:40:28.074387 ==
5566 00:40:28.076924 Dram Type= 6, Freq= 0, CH_1, rank 0
5567 00:40:28.080254 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5568 00:40:28.080639 ==
5569 00:40:28.084039 [Gating] SW mode calibration
5570 00:40:28.090170 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5571 00:40:28.097168 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5572 00:40:28.099892 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5573 00:40:28.106771 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5574 00:40:28.109994 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5575 00:40:28.113660 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5576 00:40:28.120068 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5577 00:40:28.123491 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5578 00:40:28.126355 0 14 24 | B1->B0 | 3434 2f2f | 0 0 | (0 0) (0 0)
5579 00:40:28.133221 0 14 28 | B1->B0 | 2a2a 2525 | 0 0 | (1 0) (0 0)
5580 00:40:28.136392 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5581 00:40:28.139476 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5582 00:40:28.146385 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5583 00:40:28.149676 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5584 00:40:28.153024 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5585 00:40:28.159782 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5586 00:40:28.162409 0 15 24 | B1->B0 | 2323 2828 | 0 0 | (0 0) (1 1)
5587 00:40:28.165827 0 15 28 | B1->B0 | 3a3a 4545 | 0 1 | (0 0) (0 0)
5588 00:40:28.172415 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5589 00:40:28.175929 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5590 00:40:28.179133 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5591 00:40:28.185967 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5592 00:40:28.189384 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5593 00:40:28.192351 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5594 00:40:28.199009 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5595 00:40:28.202094 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5596 00:40:28.205733 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5597 00:40:28.212297 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5598 00:40:28.215368 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5599 00:40:28.218962 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5600 00:40:28.225771 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5601 00:40:28.228357 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5602 00:40:28.232172 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5603 00:40:28.238426 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5604 00:40:28.242070 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5605 00:40:28.245043 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5606 00:40:28.251601 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5607 00:40:28.254759 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5608 00:40:28.258195 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5609 00:40:28.264760 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5610 00:40:28.268127 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5611 00:40:28.271805 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5612 00:40:28.274524 Total UI for P1: 0, mck2ui 16
5613 00:40:28.277587 best dqsien dly found for B0: ( 1, 2, 24)
5614 00:40:28.284339 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5615 00:40:28.284863 Total UI for P1: 0, mck2ui 16
5616 00:40:28.291135 best dqsien dly found for B1: ( 1, 2, 26)
5617 00:40:28.294651 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5618 00:40:28.297391 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5619 00:40:28.297936
5620 00:40:28.300795 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5621 00:40:28.304331 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5622 00:40:28.307856 [Gating] SW calibration Done
5623 00:40:28.308372 ==
5624 00:40:28.310896 Dram Type= 6, Freq= 0, CH_1, rank 0
5625 00:40:28.314088 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5626 00:40:28.314510 ==
5627 00:40:28.317734 RX Vref Scan: 0
5628 00:40:28.318147
5629 00:40:28.318476 RX Vref 0 -> 0, step: 1
5630 00:40:28.318786
5631 00:40:28.320486 RX Delay -80 -> 252, step: 8
5632 00:40:28.324366 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5633 00:40:28.330578 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5634 00:40:28.334046 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5635 00:40:28.337484 iDelay=208, Bit 3, Center 99 (0 ~ 199) 200
5636 00:40:28.340541 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5637 00:40:28.344386 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5638 00:40:28.347207 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5639 00:40:28.353437 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5640 00:40:28.356920 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5641 00:40:28.360234 iDelay=208, Bit 9, Center 87 (-8 ~ 183) 192
5642 00:40:28.363494 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5643 00:40:28.366579 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5644 00:40:28.373232 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5645 00:40:28.376423 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5646 00:40:28.380427 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5647 00:40:28.383413 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5648 00:40:28.383837 ==
5649 00:40:28.387000 Dram Type= 6, Freq= 0, CH_1, rank 0
5650 00:40:28.393060 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5651 00:40:28.393624 ==
5652 00:40:28.394050 DQS Delay:
5653 00:40:28.394371 DQS0 = 0, DQS1 = 0
5654 00:40:28.396799 DQM Delay:
5655 00:40:28.397553 DQM0 = 100, DQM1 = 96
5656 00:40:28.399858 DQ Delay:
5657 00:40:28.403503 DQ0 =103, DQ1 =95, DQ2 =91, DQ3 =99
5658 00:40:28.406821 DQ4 =95, DQ5 =111, DQ6 =111, DQ7 =95
5659 00:40:28.410213 DQ8 =83, DQ9 =87, DQ10 =95, DQ11 =91
5660 00:40:28.412946 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =103
5661 00:40:28.413397
5662 00:40:28.413739
5663 00:40:28.414061 ==
5664 00:40:28.416074 Dram Type= 6, Freq= 0, CH_1, rank 0
5665 00:40:28.420202 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5666 00:40:28.420628 ==
5667 00:40:28.420962
5668 00:40:28.421312
5669 00:40:28.422877 TX Vref Scan disable
5670 00:40:28.426364 == TX Byte 0 ==
5671 00:40:28.429888 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5672 00:40:28.432646 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5673 00:40:28.435817 == TX Byte 1 ==
5674 00:40:28.439021 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5675 00:40:28.442408 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5676 00:40:28.442833 ==
5677 00:40:28.445611 Dram Type= 6, Freq= 0, CH_1, rank 0
5678 00:40:28.452382 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5679 00:40:28.452809 ==
5680 00:40:28.453142
5681 00:40:28.453504
5682 00:40:28.453810 TX Vref Scan disable
5683 00:40:28.456090 == TX Byte 0 ==
5684 00:40:28.459090 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5685 00:40:28.466081 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5686 00:40:28.466349 == TX Byte 1 ==
5687 00:40:28.468937 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5688 00:40:28.475619 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5689 00:40:28.475775
5690 00:40:28.475896 [DATLAT]
5691 00:40:28.476024 Freq=933, CH1 RK0
5692 00:40:28.476178
5693 00:40:28.478974 DATLAT Default: 0xd
5694 00:40:28.479148 0, 0xFFFF, sum = 0
5695 00:40:28.481987 1, 0xFFFF, sum = 0
5696 00:40:28.485617 2, 0xFFFF, sum = 0
5697 00:40:28.485733 3, 0xFFFF, sum = 0
5698 00:40:28.488677 4, 0xFFFF, sum = 0
5699 00:40:28.488792 5, 0xFFFF, sum = 0
5700 00:40:28.492073 6, 0xFFFF, sum = 0
5701 00:40:28.492175 7, 0xFFFF, sum = 0
5702 00:40:28.495486 8, 0xFFFF, sum = 0
5703 00:40:28.495602 9, 0xFFFF, sum = 0
5704 00:40:28.498647 10, 0x0, sum = 1
5705 00:40:28.498763 11, 0x0, sum = 2
5706 00:40:28.501796 12, 0x0, sum = 3
5707 00:40:28.501910 13, 0x0, sum = 4
5708 00:40:28.502002 best_step = 11
5709 00:40:28.505185
5710 00:40:28.505310 ==
5711 00:40:28.508521 Dram Type= 6, Freq= 0, CH_1, rank 0
5712 00:40:28.511738 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5713 00:40:28.511853 ==
5714 00:40:28.511945 RX Vref Scan: 1
5715 00:40:28.512064
5716 00:40:28.515090 RX Vref 0 -> 0, step: 1
5717 00:40:28.515203
5718 00:40:28.518167 RX Delay -53 -> 252, step: 4
5719 00:40:28.518247
5720 00:40:28.521586 Set Vref, RX VrefLevel [Byte0]: 51
5721 00:40:28.524760 [Byte1]: 53
5722 00:40:28.528578
5723 00:40:28.528659 Final RX Vref Byte 0 = 51 to rank0
5724 00:40:28.531618 Final RX Vref Byte 1 = 53 to rank0
5725 00:40:28.534743 Final RX Vref Byte 0 = 51 to rank1
5726 00:40:28.538392 Final RX Vref Byte 1 = 53 to rank1==
5727 00:40:28.541503 Dram Type= 6, Freq= 0, CH_1, rank 0
5728 00:40:28.548035 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5729 00:40:28.548126 ==
5730 00:40:28.548191 DQS Delay:
5731 00:40:28.551575 DQS0 = 0, DQS1 = 0
5732 00:40:28.551657 DQM Delay:
5733 00:40:28.551721 DQM0 = 99, DQM1 = 95
5734 00:40:28.555184 DQ Delay:
5735 00:40:28.557979 DQ0 =104, DQ1 =94, DQ2 =88, DQ3 =100
5736 00:40:28.561288 DQ4 =96, DQ5 =108, DQ6 =108, DQ7 =94
5737 00:40:28.564418 DQ8 =82, DQ9 =86, DQ10 =92, DQ11 =90
5738 00:40:28.568164 DQ12 =102, DQ13 =104, DQ14 =102, DQ15 =104
5739 00:40:28.568247
5740 00:40:28.568311
5741 00:40:28.574384 [DQSOSCAuto] RK0, (LSB)MR18= 0x919, (MSB)MR19= 0x505, tDQSOscB0 = 413 ps tDQSOscB1 = 419 ps
5742 00:40:28.578246 CH1 RK0: MR19=505, MR18=919
5743 00:40:28.584590 CH1_RK0: MR19=0x505, MR18=0x919, DQSOSC=413, MR23=63, INC=63, DEC=42
5744 00:40:28.584678
5745 00:40:28.587696 ----->DramcWriteLeveling(PI) begin...
5746 00:40:28.587780 ==
5747 00:40:28.591534 Dram Type= 6, Freq= 0, CH_1, rank 1
5748 00:40:28.594135 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5749 00:40:28.594220 ==
5750 00:40:28.597927 Write leveling (Byte 0): 28 => 28
5751 00:40:28.601143 Write leveling (Byte 1): 30 => 30
5752 00:40:28.604430 DramcWriteLeveling(PI) end<-----
5753 00:40:28.604519
5754 00:40:28.604585 ==
5755 00:40:28.607412 Dram Type= 6, Freq= 0, CH_1, rank 1
5756 00:40:28.613767 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5757 00:40:28.613858 ==
5758 00:40:28.613924 [Gating] SW mode calibration
5759 00:40:28.623804 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5760 00:40:28.627082 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5761 00:40:28.633631 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5762 00:40:28.637353 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5763 00:40:28.640472 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5764 00:40:28.643614 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5765 00:40:28.650407 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5766 00:40:28.653309 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5767 00:40:28.660108 0 14 24 | B1->B0 | 3434 3030 | 0 0 | (0 0) (0 0)
5768 00:40:28.663362 0 14 28 | B1->B0 | 2929 2323 | 1 0 | (1 1) (1 0)
5769 00:40:28.666981 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5770 00:40:28.673340 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5771 00:40:28.676604 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5772 00:40:28.679951 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5773 00:40:28.686383 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5774 00:40:28.689802 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5775 00:40:28.693215 0 15 24 | B1->B0 | 2c2c 3737 | 0 0 | (0 0) (0 0)
5776 00:40:28.696418 0 15 28 | B1->B0 | 3a3a 4646 | 1 0 | (0 0) (0 0)
5777 00:40:28.703175 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5778 00:40:28.706323 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5779 00:40:28.709508 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5780 00:40:28.716482 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5781 00:40:28.720075 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5782 00:40:28.723316 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5783 00:40:28.729219 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5784 00:40:28.732806 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5785 00:40:28.736408 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5786 00:40:28.742637 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5787 00:40:28.745800 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5788 00:40:28.749659 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5789 00:40:28.755714 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5790 00:40:28.759051 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5791 00:40:28.765395 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5792 00:40:28.769237 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5793 00:40:28.772207 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5794 00:40:28.778857 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5795 00:40:28.782116 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5796 00:40:28.786075 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5797 00:40:28.792402 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5798 00:40:28.795604 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5799 00:40:28.799308 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5800 00:40:28.805289 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5801 00:40:28.808358 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5802 00:40:28.811846 Total UI for P1: 0, mck2ui 16
5803 00:40:28.815345 best dqsien dly found for B0: ( 1, 2, 26)
5804 00:40:28.818692 Total UI for P1: 0, mck2ui 16
5805 00:40:28.821547 best dqsien dly found for B1: ( 1, 2, 26)
5806 00:40:28.825438 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5807 00:40:28.828098 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5808 00:40:28.828251
5809 00:40:28.831814 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5810 00:40:28.834767 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5811 00:40:28.838211 [Gating] SW calibration Done
5812 00:40:28.838324 ==
5813 00:40:28.841147 Dram Type= 6, Freq= 0, CH_1, rank 1
5814 00:40:28.844826 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5815 00:40:28.848151 ==
5816 00:40:28.848252 RX Vref Scan: 0
5817 00:40:28.848331
5818 00:40:28.851446 RX Vref 0 -> 0, step: 1
5819 00:40:28.851547
5820 00:40:28.854596 RX Delay -80 -> 252, step: 8
5821 00:40:28.857599 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5822 00:40:28.861158 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5823 00:40:28.864707 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5824 00:40:28.867571 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5825 00:40:28.870953 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5826 00:40:28.877599 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5827 00:40:28.880981 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5828 00:40:28.884834 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5829 00:40:28.887978 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5830 00:40:28.891006 iDelay=208, Bit 9, Center 87 (-8 ~ 183) 192
5831 00:40:28.894538 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5832 00:40:28.901156 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5833 00:40:28.904733 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5834 00:40:28.907417 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5835 00:40:28.911236 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5836 00:40:28.914024 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5837 00:40:28.917300 ==
5838 00:40:28.917722 Dram Type= 6, Freq= 0, CH_1, rank 1
5839 00:40:28.923802 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5840 00:40:28.924032 ==
5841 00:40:28.924213 DQS Delay:
5842 00:40:28.927317 DQS0 = 0, DQS1 = 0
5843 00:40:28.927542 DQM Delay:
5844 00:40:28.930160 DQM0 = 97, DQM1 = 95
5845 00:40:28.930401 DQ Delay:
5846 00:40:28.933596 DQ0 =103, DQ1 =95, DQ2 =87, DQ3 =95
5847 00:40:28.937115 DQ4 =95, DQ5 =107, DQ6 =103, DQ7 =95
5848 00:40:28.940107 DQ8 =83, DQ9 =87, DQ10 =95, DQ11 =91
5849 00:40:28.943679 DQ12 =103, DQ13 =103, DQ14 =99, DQ15 =103
5850 00:40:28.943796
5851 00:40:28.943886
5852 00:40:28.943970 ==
5853 00:40:28.946721 Dram Type= 6, Freq= 0, CH_1, rank 1
5854 00:40:28.950304 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5855 00:40:28.950419 ==
5856 00:40:28.950577
5857 00:40:28.953540
5858 00:40:28.953629 TX Vref Scan disable
5859 00:40:28.956745 == TX Byte 0 ==
5860 00:40:28.960407 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5861 00:40:28.963911 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5862 00:40:28.966828 == TX Byte 1 ==
5863 00:40:28.970128 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5864 00:40:28.973218 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5865 00:40:28.973350 ==
5866 00:40:28.977031 Dram Type= 6, Freq= 0, CH_1, rank 1
5867 00:40:28.983276 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5868 00:40:28.983358 ==
5869 00:40:28.983422
5870 00:40:28.983482
5871 00:40:28.983600 TX Vref Scan disable
5872 00:40:28.987637 == TX Byte 0 ==
5873 00:40:28.990970 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5874 00:40:28.997536 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5875 00:40:28.997675 == TX Byte 1 ==
5876 00:40:29.000585 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5877 00:40:29.007408 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5878 00:40:29.007513
5879 00:40:29.007586 [DATLAT]
5880 00:40:29.007646 Freq=933, CH1 RK1
5881 00:40:29.007704
5882 00:40:29.010369 DATLAT Default: 0xb
5883 00:40:29.010503 0, 0xFFFF, sum = 0
5884 00:40:29.013922 1, 0xFFFF, sum = 0
5885 00:40:29.017087 2, 0xFFFF, sum = 0
5886 00:40:29.017215 3, 0xFFFF, sum = 0
5887 00:40:29.020179 4, 0xFFFF, sum = 0
5888 00:40:29.020278 5, 0xFFFF, sum = 0
5889 00:40:29.023611 6, 0xFFFF, sum = 0
5890 00:40:29.023738 7, 0xFFFF, sum = 0
5891 00:40:29.027189 8, 0xFFFF, sum = 0
5892 00:40:29.027294 9, 0xFFFF, sum = 0
5893 00:40:29.030677 10, 0x0, sum = 1
5894 00:40:29.030809 11, 0x0, sum = 2
5895 00:40:29.033588 12, 0x0, sum = 3
5896 00:40:29.033669 13, 0x0, sum = 4
5897 00:40:29.037387 best_step = 11
5898 00:40:29.037468
5899 00:40:29.037532 ==
5900 00:40:29.040239 Dram Type= 6, Freq= 0, CH_1, rank 1
5901 00:40:29.043636 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5902 00:40:29.044326 ==
5903 00:40:29.044805 RX Vref Scan: 0
5904 00:40:29.046903
5905 00:40:29.047436 RX Vref 0 -> 0, step: 1
5906 00:40:29.047767
5907 00:40:29.050119 RX Delay -53 -> 252, step: 4
5908 00:40:29.057319 iDelay=199, Bit 0, Center 104 (15 ~ 194) 180
5909 00:40:29.060022 iDelay=199, Bit 1, Center 94 (-1 ~ 190) 192
5910 00:40:29.063351 iDelay=199, Bit 2, Center 86 (-5 ~ 178) 184
5911 00:40:29.066710 iDelay=199, Bit 3, Center 94 (3 ~ 186) 184
5912 00:40:29.069983 iDelay=199, Bit 4, Center 96 (3 ~ 190) 188
5913 00:40:29.073292 iDelay=199, Bit 5, Center 106 (15 ~ 198) 184
5914 00:40:29.079815 iDelay=199, Bit 6, Center 106 (15 ~ 198) 184
5915 00:40:29.083037 iDelay=199, Bit 7, Center 94 (3 ~ 186) 184
5916 00:40:29.086433 iDelay=199, Bit 8, Center 80 (-9 ~ 170) 180
5917 00:40:29.089853 iDelay=199, Bit 9, Center 84 (-5 ~ 174) 180
5918 00:40:29.093297 iDelay=199, Bit 10, Center 94 (3 ~ 186) 184
5919 00:40:29.100152 iDelay=199, Bit 11, Center 86 (-5 ~ 178) 184
5920 00:40:29.103084 iDelay=199, Bit 12, Center 100 (11 ~ 190) 180
5921 00:40:29.106411 iDelay=199, Bit 13, Center 102 (11 ~ 194) 184
5922 00:40:29.109738 iDelay=199, Bit 14, Center 98 (7 ~ 190) 184
5923 00:40:29.112770 iDelay=199, Bit 15, Center 102 (11 ~ 194) 184
5924 00:40:29.116877 ==
5925 00:40:29.117173 Dram Type= 6, Freq= 0, CH_1, rank 1
5926 00:40:29.122561 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5927 00:40:29.122787 ==
5928 00:40:29.122966 DQS Delay:
5929 00:40:29.125954 DQS0 = 0, DQS1 = 0
5930 00:40:29.126136 DQM Delay:
5931 00:40:29.129297 DQM0 = 97, DQM1 = 93
5932 00:40:29.129448 DQ Delay:
5933 00:40:29.132285 DQ0 =104, DQ1 =94, DQ2 =86, DQ3 =94
5934 00:40:29.135987 DQ4 =96, DQ5 =106, DQ6 =106, DQ7 =94
5935 00:40:29.139012 DQ8 =80, DQ9 =84, DQ10 =94, DQ11 =86
5936 00:40:29.142125 DQ12 =100, DQ13 =102, DQ14 =98, DQ15 =102
5937 00:40:29.142239
5938 00:40:29.142330
5939 00:40:29.153050 [DQSOSCAuto] RK1, (LSB)MR18= 0x1027, (MSB)MR19= 0x505, tDQSOscB0 = 409 ps tDQSOscB1 = 416 ps
5940 00:40:29.153170 CH1 RK1: MR19=505, MR18=1027
5941 00:40:29.159331 CH1_RK1: MR19=0x505, MR18=0x1027, DQSOSC=409, MR23=63, INC=64, DEC=43
5942 00:40:29.162409 [RxdqsGatingPostProcess] freq 933
5943 00:40:29.168861 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5944 00:40:29.172103 best DQS0 dly(2T, 0.5T) = (0, 10)
5945 00:40:29.175260 best DQS1 dly(2T, 0.5T) = (0, 10)
5946 00:40:29.178482 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5947 00:40:29.182095 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5948 00:40:29.182187 best DQS0 dly(2T, 0.5T) = (0, 10)
5949 00:40:29.185987 best DQS1 dly(2T, 0.5T) = (0, 10)
5950 00:40:29.188542 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5951 00:40:29.191877 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5952 00:40:29.195102 Pre-setting of DQS Precalculation
5953 00:40:29.202044 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5954 00:40:29.208559 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5955 00:40:29.215148 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5956 00:40:29.215345
5957 00:40:29.215449
5958 00:40:29.218386 [Calibration Summary] 1866 Mbps
5959 00:40:29.218533 CH 0, Rank 0
5960 00:40:29.221746 SW Impedance : PASS
5961 00:40:29.224837 DUTY Scan : NO K
5962 00:40:29.225079 ZQ Calibration : PASS
5963 00:40:29.228294 Jitter Meter : NO K
5964 00:40:29.231734 CBT Training : PASS
5965 00:40:29.231905 Write leveling : PASS
5966 00:40:29.235006 RX DQS gating : PASS
5967 00:40:29.238100 RX DQ/DQS(RDDQC) : PASS
5968 00:40:29.238297 TX DQ/DQS : PASS
5969 00:40:29.241650 RX DATLAT : PASS
5970 00:40:29.244521 RX DQ/DQS(Engine): PASS
5971 00:40:29.244812 TX OE : NO K
5972 00:40:29.248430 All Pass.
5973 00:40:29.248902
5974 00:40:29.249220 CH 0, Rank 1
5975 00:40:29.252224 SW Impedance : PASS
5976 00:40:29.252700 DUTY Scan : NO K
5977 00:40:29.255099 ZQ Calibration : PASS
5978 00:40:29.258831 Jitter Meter : NO K
5979 00:40:29.259417 CBT Training : PASS
5980 00:40:29.261935 Write leveling : PASS
5981 00:40:29.264627 RX DQS gating : PASS
5982 00:40:29.265044 RX DQ/DQS(RDDQC) : PASS
5983 00:40:29.267914 TX DQ/DQS : PASS
5984 00:40:29.271149 RX DATLAT : PASS
5985 00:40:29.271570 RX DQ/DQS(Engine): PASS
5986 00:40:29.274432 TX OE : NO K
5987 00:40:29.274844 All Pass.
5988 00:40:29.275168
5989 00:40:29.277857 CH 1, Rank 0
5990 00:40:29.278275 SW Impedance : PASS
5991 00:40:29.281201 DUTY Scan : NO K
5992 00:40:29.284328 ZQ Calibration : PASS
5993 00:40:29.284743 Jitter Meter : NO K
5994 00:40:29.287920 CBT Training : PASS
5995 00:40:29.291176 Write leveling : PASS
5996 00:40:29.291698 RX DQS gating : PASS
5997 00:40:29.294489 RX DQ/DQS(RDDQC) : PASS
5998 00:40:29.294912 TX DQ/DQS : PASS
5999 00:40:29.297960 RX DATLAT : PASS
6000 00:40:29.301699 RX DQ/DQS(Engine): PASS
6001 00:40:29.302115 TX OE : NO K
6002 00:40:29.304539 All Pass.
6003 00:40:29.304952
6004 00:40:29.305323 CH 1, Rank 1
6005 00:40:29.307585 SW Impedance : PASS
6006 00:40:29.308000 DUTY Scan : NO K
6007 00:40:29.311195 ZQ Calibration : PASS
6008 00:40:29.315050 Jitter Meter : NO K
6009 00:40:29.315565 CBT Training : PASS
6010 00:40:29.317734 Write leveling : PASS
6011 00:40:29.320918 RX DQS gating : PASS
6012 00:40:29.321388 RX DQ/DQS(RDDQC) : PASS
6013 00:40:29.324245 TX DQ/DQS : PASS
6014 00:40:29.327401 RX DATLAT : PASS
6015 00:40:29.327817 RX DQ/DQS(Engine): PASS
6016 00:40:29.330735 TX OE : NO K
6017 00:40:29.331150 All Pass.
6018 00:40:29.331477
6019 00:40:29.334368 DramC Write-DBI off
6020 00:40:29.337657 PER_BANK_REFRESH: Hybrid Mode
6021 00:40:29.338072 TX_TRACKING: ON
6022 00:40:29.347469 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6023 00:40:29.351410 [FAST_K] Save calibration result to emmc
6024 00:40:29.354430 dramc_set_vcore_voltage set vcore to 650000
6025 00:40:29.357217 Read voltage for 400, 6
6026 00:40:29.357650 Vio18 = 0
6027 00:40:29.357980 Vcore = 650000
6028 00:40:29.361001 Vdram = 0
6029 00:40:29.361445 Vddq = 0
6030 00:40:29.361772 Vmddr = 0
6031 00:40:29.366840 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6032 00:40:29.370183 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6033 00:40:29.373739 MEM_TYPE=3, freq_sel=20
6034 00:40:29.376770 sv_algorithm_assistance_LP4_800
6035 00:40:29.380276 ============ PULL DRAM RESETB DOWN ============
6036 00:40:29.383497 ========== PULL DRAM RESETB DOWN end =========
6037 00:40:29.390185 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6038 00:40:29.393657 ===================================
6039 00:40:29.396637 LPDDR4 DRAM CONFIGURATION
6040 00:40:29.400359 ===================================
6041 00:40:29.400773 EX_ROW_EN[0] = 0x0
6042 00:40:29.403429 EX_ROW_EN[1] = 0x0
6043 00:40:29.403847 LP4Y_EN = 0x0
6044 00:40:29.407113 WORK_FSP = 0x0
6045 00:40:29.407528 WL = 0x2
6046 00:40:29.410093 RL = 0x2
6047 00:40:29.410525 BL = 0x2
6048 00:40:29.413311 RPST = 0x0
6049 00:40:29.413754 RD_PRE = 0x0
6050 00:40:29.416264 WR_PRE = 0x1
6051 00:40:29.416688 WR_PST = 0x0
6052 00:40:29.419972 DBI_WR = 0x0
6053 00:40:29.423044 DBI_RD = 0x0
6054 00:40:29.423459 OTF = 0x1
6055 00:40:29.426744 ===================================
6056 00:40:29.429719 ===================================
6057 00:40:29.430139 ANA top config
6058 00:40:29.433559 ===================================
6059 00:40:29.436360 DLL_ASYNC_EN = 0
6060 00:40:29.439625 ALL_SLAVE_EN = 1
6061 00:40:29.443102 NEW_RANK_MODE = 1
6062 00:40:29.446188 DLL_IDLE_MODE = 1
6063 00:40:29.446602 LP45_APHY_COMB_EN = 1
6064 00:40:29.449651 TX_ODT_DIS = 1
6065 00:40:29.452896 NEW_8X_MODE = 1
6066 00:40:29.456306 ===================================
6067 00:40:29.459345 ===================================
6068 00:40:29.462381 data_rate = 800
6069 00:40:29.465999 CKR = 1
6070 00:40:29.469728 DQ_P2S_RATIO = 4
6071 00:40:29.472333 ===================================
6072 00:40:29.472752 CA_P2S_RATIO = 4
6073 00:40:29.475674 DQ_CA_OPEN = 0
6074 00:40:29.479412 DQ_SEMI_OPEN = 1
6075 00:40:29.482650 CA_SEMI_OPEN = 1
6076 00:40:29.485864 CA_FULL_RATE = 0
6077 00:40:29.489023 DQ_CKDIV4_EN = 0
6078 00:40:29.489788 CA_CKDIV4_EN = 1
6079 00:40:29.492284 CA_PREDIV_EN = 0
6080 00:40:29.495337 PH8_DLY = 0
6081 00:40:29.498882 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6082 00:40:29.502020 DQ_AAMCK_DIV = 0
6083 00:40:29.505366 CA_AAMCK_DIV = 0
6084 00:40:29.505786 CA_ADMCK_DIV = 4
6085 00:40:29.508524 DQ_TRACK_CA_EN = 0
6086 00:40:29.512261 CA_PICK = 800
6087 00:40:29.515506 CA_MCKIO = 400
6088 00:40:29.518392 MCKIO_SEMI = 400
6089 00:40:29.521587 PLL_FREQ = 3016
6090 00:40:29.525784 DQ_UI_PI_RATIO = 32
6091 00:40:29.528641 CA_UI_PI_RATIO = 32
6092 00:40:29.531582 ===================================
6093 00:40:29.534771 ===================================
6094 00:40:29.535195 memory_type:LPDDR4
6095 00:40:29.538292 GP_NUM : 10
6096 00:40:29.542131 SRAM_EN : 1
6097 00:40:29.542543 MD32_EN : 0
6098 00:40:29.545319 ===================================
6099 00:40:29.548668 [ANA_INIT] >>>>>>>>>>>>>>
6100 00:40:29.551799 <<<<<< [CONFIGURE PHASE]: ANA_TX
6101 00:40:29.555251 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6102 00:40:29.558024 ===================================
6103 00:40:29.562011 data_rate = 800,PCW = 0X7400
6104 00:40:29.565155 ===================================
6105 00:40:29.568377 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6106 00:40:29.571462 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6107 00:40:29.584652 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6108 00:40:29.588078 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6109 00:40:29.590986 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6110 00:40:29.594439 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6111 00:40:29.598200 [ANA_INIT] flow start
6112 00:40:29.601050 [ANA_INIT] PLL >>>>>>>>
6113 00:40:29.601523 [ANA_INIT] PLL <<<<<<<<
6114 00:40:29.604391 [ANA_INIT] MIDPI >>>>>>>>
6115 00:40:29.607372 [ANA_INIT] MIDPI <<<<<<<<
6116 00:40:29.607787 [ANA_INIT] DLL >>>>>>>>
6117 00:40:29.611006 [ANA_INIT] flow end
6118 00:40:29.614232 ============ LP4 DIFF to SE enter ============
6119 00:40:29.617684 ============ LP4 DIFF to SE exit ============
6120 00:40:29.620791 [ANA_INIT] <<<<<<<<<<<<<
6121 00:40:29.624344 [Flow] Enable top DCM control >>>>>
6122 00:40:29.627257 [Flow] Enable top DCM control <<<<<
6123 00:40:29.630389 Enable DLL master slave shuffle
6124 00:40:29.637312 ==============================================================
6125 00:40:29.637765 Gating Mode config
6126 00:40:29.643579 ==============================================================
6127 00:40:29.647384 Config description:
6128 00:40:29.653868 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6129 00:40:29.663764 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6130 00:40:29.667470 SELPH_MODE 0: By rank 1: By Phase
6131 00:40:29.672977 ==============================================================
6132 00:40:29.676343 GAT_TRACK_EN = 0
6133 00:40:29.679875 RX_GATING_MODE = 2
6134 00:40:29.680384 RX_GATING_TRACK_MODE = 2
6135 00:40:29.682899 SELPH_MODE = 1
6136 00:40:29.686299 PICG_EARLY_EN = 1
6137 00:40:29.689968 VALID_LAT_VALUE = 1
6138 00:40:29.696175 ==============================================================
6139 00:40:29.699311 Enter into Gating configuration >>>>
6140 00:40:29.702794 Exit from Gating configuration <<<<
6141 00:40:29.706731 Enter into DVFS_PRE_config >>>>>
6142 00:40:29.716447 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6143 00:40:29.719175 Exit from DVFS_PRE_config <<<<<
6144 00:40:29.722517 Enter into PICG configuration >>>>
6145 00:40:29.725957 Exit from PICG configuration <<<<
6146 00:40:29.729223 [RX_INPUT] configuration >>>>>
6147 00:40:29.732706 [RX_INPUT] configuration <<<<<
6148 00:40:29.735907 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6149 00:40:29.742107 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6150 00:40:29.748963 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6151 00:40:29.755865 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6152 00:40:29.762586 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6153 00:40:29.765675 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6154 00:40:29.772059 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6155 00:40:29.775608 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6156 00:40:29.778854 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6157 00:40:29.782185 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6158 00:40:29.788568 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6159 00:40:29.791449 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6160 00:40:29.794727 ===================================
6161 00:40:29.797943 LPDDR4 DRAM CONFIGURATION
6162 00:40:29.801746 ===================================
6163 00:40:29.802163 EX_ROW_EN[0] = 0x0
6164 00:40:29.804747 EX_ROW_EN[1] = 0x0
6165 00:40:29.805291 LP4Y_EN = 0x0
6166 00:40:29.808165 WORK_FSP = 0x0
6167 00:40:29.811758 WL = 0x2
6168 00:40:29.812175 RL = 0x2
6169 00:40:29.814588 BL = 0x2
6170 00:40:29.815004 RPST = 0x0
6171 00:40:29.817832 RD_PRE = 0x0
6172 00:40:29.818296 WR_PRE = 0x1
6173 00:40:29.821812 WR_PST = 0x0
6174 00:40:29.822227 DBI_WR = 0x0
6175 00:40:29.824348 DBI_RD = 0x0
6176 00:40:29.824763 OTF = 0x1
6177 00:40:29.827963 ===================================
6178 00:40:29.831033 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6179 00:40:29.837537 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6180 00:40:29.840998 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6181 00:40:29.844167 ===================================
6182 00:40:29.847545 LPDDR4 DRAM CONFIGURATION
6183 00:40:29.850698 ===================================
6184 00:40:29.851116 EX_ROW_EN[0] = 0x10
6185 00:40:29.854148 EX_ROW_EN[1] = 0x0
6186 00:40:29.857635 LP4Y_EN = 0x0
6187 00:40:29.858052 WORK_FSP = 0x0
6188 00:40:29.860427 WL = 0x2
6189 00:40:29.860843 RL = 0x2
6190 00:40:29.864403 BL = 0x2
6191 00:40:29.864919 RPST = 0x0
6192 00:40:29.867603 RD_PRE = 0x0
6193 00:40:29.868045 WR_PRE = 0x1
6194 00:40:29.870449 WR_PST = 0x0
6195 00:40:29.870996 DBI_WR = 0x0
6196 00:40:29.873709 DBI_RD = 0x0
6197 00:40:29.874124 OTF = 0x1
6198 00:40:29.877490 ===================================
6199 00:40:29.883971 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6200 00:40:29.888551 nWR fixed to 30
6201 00:40:29.891487 [ModeRegInit_LP4] CH0 RK0
6202 00:40:29.891925 [ModeRegInit_LP4] CH0 RK1
6203 00:40:29.895187 [ModeRegInit_LP4] CH1 RK0
6204 00:40:29.897943 [ModeRegInit_LP4] CH1 RK1
6205 00:40:29.898464 match AC timing 19
6206 00:40:29.904958 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6207 00:40:29.908089 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6208 00:40:29.911400 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6209 00:40:29.917927 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6210 00:40:29.922049 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6211 00:40:29.922468 ==
6212 00:40:29.924737 Dram Type= 6, Freq= 0, CH_0, rank 0
6213 00:40:29.927622 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6214 00:40:29.928142 ==
6215 00:40:29.934740 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6216 00:40:29.941316 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6217 00:40:29.944295 [CA 0] Center 36 (8~64) winsize 57
6218 00:40:29.947699 [CA 1] Center 36 (8~64) winsize 57
6219 00:40:29.951028 [CA 2] Center 36 (8~64) winsize 57
6220 00:40:29.954092 [CA 3] Center 36 (8~64) winsize 57
6221 00:40:29.957548 [CA 4] Center 36 (8~64) winsize 57
6222 00:40:29.957978 [CA 5] Center 36 (8~64) winsize 57
6223 00:40:29.961222
6224 00:40:29.964162 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6225 00:40:29.964577
6226 00:40:29.967938 [CATrainingPosCal] consider 1 rank data
6227 00:40:29.970735 u2DelayCellTimex100 = 270/100 ps
6228 00:40:29.973875 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6229 00:40:29.977506 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6230 00:40:29.980972 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6231 00:40:29.984047 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6232 00:40:29.987237 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6233 00:40:29.990536 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6234 00:40:29.990954
6235 00:40:29.993957 CA PerBit enable=1, Macro0, CA PI delay=36
6236 00:40:29.994373
6237 00:40:29.997302 [CBTSetCACLKResult] CA Dly = 36
6238 00:40:30.001120 CS Dly: 1 (0~32)
6239 00:40:30.001646 ==
6240 00:40:30.003852 Dram Type= 6, Freq= 0, CH_0, rank 1
6241 00:40:30.007258 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6242 00:40:30.007679 ==
6243 00:40:30.014083 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6244 00:40:30.020560 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6245 00:40:30.023791 [CA 0] Center 36 (8~64) winsize 57
6246 00:40:30.026944 [CA 1] Center 36 (8~64) winsize 57
6247 00:40:30.027481 [CA 2] Center 36 (8~64) winsize 57
6248 00:40:30.030372 [CA 3] Center 36 (8~64) winsize 57
6249 00:40:30.033750 [CA 4] Center 36 (8~64) winsize 57
6250 00:40:30.036665 [CA 5] Center 36 (8~64) winsize 57
6251 00:40:30.037085
6252 00:40:30.040202 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6253 00:40:30.043583
6254 00:40:30.047001 [CATrainingPosCal] consider 2 rank data
6255 00:40:30.047419 u2DelayCellTimex100 = 270/100 ps
6256 00:40:30.053864 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6257 00:40:30.057206 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6258 00:40:30.060192 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6259 00:40:30.063311 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6260 00:40:30.067237 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6261 00:40:30.069864 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6262 00:40:30.070282
6263 00:40:30.073526 CA PerBit enable=1, Macro0, CA PI delay=36
6264 00:40:30.073942
6265 00:40:30.076302 [CBTSetCACLKResult] CA Dly = 36
6266 00:40:30.080022 CS Dly: 1 (0~32)
6267 00:40:30.080577
6268 00:40:30.083612 ----->DramcWriteLeveling(PI) begin...
6269 00:40:30.084145 ==
6270 00:40:30.086748 Dram Type= 6, Freq= 0, CH_0, rank 0
6271 00:40:30.089662 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6272 00:40:30.090090 ==
6273 00:40:30.092979 Write leveling (Byte 0): 40 => 8
6274 00:40:30.096183 Write leveling (Byte 1): 40 => 8
6275 00:40:30.099879 DramcWriteLeveling(PI) end<-----
6276 00:40:30.100401
6277 00:40:30.100734 ==
6278 00:40:30.102704 Dram Type= 6, Freq= 0, CH_0, rank 0
6279 00:40:30.106433 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6280 00:40:30.106962 ==
6281 00:40:30.109350 [Gating] SW mode calibration
6282 00:40:30.115960 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6283 00:40:30.122607 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6284 00:40:30.126008 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6285 00:40:30.132744 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6286 00:40:30.136063 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6287 00:40:30.138639 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6288 00:40:30.146072 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6289 00:40:30.148746 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6290 00:40:30.152237 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6291 00:40:30.158769 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6292 00:40:30.161835 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6293 00:40:30.165244 Total UI for P1: 0, mck2ui 16
6294 00:40:30.168770 best dqsien dly found for B0: ( 0, 14, 24)
6295 00:40:30.172057 Total UI for P1: 0, mck2ui 16
6296 00:40:30.175207 best dqsien dly found for B1: ( 0, 14, 24)
6297 00:40:30.178590 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6298 00:40:30.181871 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6299 00:40:30.182361
6300 00:40:30.184914 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6301 00:40:30.188175 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6302 00:40:30.191619 [Gating] SW calibration Done
6303 00:40:30.192032 ==
6304 00:40:30.195502 Dram Type= 6, Freq= 0, CH_0, rank 0
6305 00:40:30.198023 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6306 00:40:30.201425 ==
6307 00:40:30.201843 RX Vref Scan: 0
6308 00:40:30.202175
6309 00:40:30.204709 RX Vref 0 -> 0, step: 1
6310 00:40:30.205123
6311 00:40:30.208138 RX Delay -410 -> 252, step: 16
6312 00:40:30.211209 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6313 00:40:30.215334 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6314 00:40:30.217843 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6315 00:40:30.224485 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6316 00:40:30.228095 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6317 00:40:30.230856 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6318 00:40:30.234426 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6319 00:40:30.241171 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6320 00:40:30.244689 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6321 00:40:30.247317 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6322 00:40:30.254086 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6323 00:40:30.257420 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6324 00:40:30.260825 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6325 00:40:30.263730 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6326 00:40:30.270472 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6327 00:40:30.274377 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6328 00:40:30.274796 ==
6329 00:40:30.276847 Dram Type= 6, Freq= 0, CH_0, rank 0
6330 00:40:30.280293 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6331 00:40:30.280714 ==
6332 00:40:30.283540 DQS Delay:
6333 00:40:30.283948 DQS0 = 35, DQS1 = 59
6334 00:40:30.286975 DQM Delay:
6335 00:40:30.287383 DQM0 = 4, DQM1 = 16
6336 00:40:30.287703 DQ Delay:
6337 00:40:30.290408 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6338 00:40:30.293326 DQ4 =0, DQ5 =0, DQ6 =16, DQ7 =16
6339 00:40:30.296998 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6340 00:40:30.300277 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6341 00:40:30.300691
6342 00:40:30.301013
6343 00:40:30.301354 ==
6344 00:40:30.303311 Dram Type= 6, Freq= 0, CH_0, rank 0
6345 00:40:30.310431 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6346 00:40:30.310852 ==
6347 00:40:30.311177
6348 00:40:30.311479
6349 00:40:30.311766 TX Vref Scan disable
6350 00:40:30.313587 == TX Byte 0 ==
6351 00:40:30.316845 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6352 00:40:30.319965 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6353 00:40:30.323278 == TX Byte 1 ==
6354 00:40:30.326847 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6355 00:40:30.330002 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6356 00:40:30.330420 ==
6357 00:40:30.333110 Dram Type= 6, Freq= 0, CH_0, rank 0
6358 00:40:30.339780 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6359 00:40:30.340200 ==
6360 00:40:30.340529
6361 00:40:30.340938
6362 00:40:30.343147 TX Vref Scan disable
6363 00:40:30.343559 == TX Byte 0 ==
6364 00:40:30.346413 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6365 00:40:30.352792 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6366 00:40:30.353209 == TX Byte 1 ==
6367 00:40:30.356249 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6368 00:40:30.359534 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6369 00:40:30.362778
6370 00:40:30.363188 [DATLAT]
6371 00:40:30.363514 Freq=400, CH0 RK0
6372 00:40:30.363825
6373 00:40:30.366342 DATLAT Default: 0xf
6374 00:40:30.366866 0, 0xFFFF, sum = 0
6375 00:40:30.369200 1, 0xFFFF, sum = 0
6376 00:40:30.369686 2, 0xFFFF, sum = 0
6377 00:40:30.372920 3, 0xFFFF, sum = 0
6378 00:40:30.376241 4, 0xFFFF, sum = 0
6379 00:40:30.376700 5, 0xFFFF, sum = 0
6380 00:40:30.379135 6, 0xFFFF, sum = 0
6381 00:40:30.379657 7, 0xFFFF, sum = 0
6382 00:40:30.382420 8, 0xFFFF, sum = 0
6383 00:40:30.382837 9, 0xFFFF, sum = 0
6384 00:40:30.385891 10, 0xFFFF, sum = 0
6385 00:40:30.386312 11, 0xFFFF, sum = 0
6386 00:40:30.389352 12, 0xFFFF, sum = 0
6387 00:40:30.389773 13, 0x0, sum = 1
6388 00:40:30.392563 14, 0x0, sum = 2
6389 00:40:30.392978 15, 0x0, sum = 3
6390 00:40:30.395602 16, 0x0, sum = 4
6391 00:40:30.396020 best_step = 14
6392 00:40:30.396351
6393 00:40:30.396652 ==
6394 00:40:30.398747 Dram Type= 6, Freq= 0, CH_0, rank 0
6395 00:40:30.402256 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6396 00:40:30.405625 ==
6397 00:40:30.406037 RX Vref Scan: 1
6398 00:40:30.406365
6399 00:40:30.408836 RX Vref 0 -> 0, step: 1
6400 00:40:30.409402
6401 00:40:30.412309 RX Delay -359 -> 252, step: 8
6402 00:40:30.412723
6403 00:40:30.416097 Set Vref, RX VrefLevel [Byte0]: 53
6404 00:40:30.419044 [Byte1]: 58
6405 00:40:30.419560
6406 00:40:30.422195 Final RX Vref Byte 0 = 53 to rank0
6407 00:40:30.425150 Final RX Vref Byte 1 = 58 to rank0
6408 00:40:30.428518 Final RX Vref Byte 0 = 53 to rank1
6409 00:40:30.431885 Final RX Vref Byte 1 = 58 to rank1==
6410 00:40:30.435618 Dram Type= 6, Freq= 0, CH_0, rank 0
6411 00:40:30.438546 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6412 00:40:30.441606 ==
6413 00:40:30.442126 DQS Delay:
6414 00:40:30.442464 DQS0 = 44, DQS1 = 60
6415 00:40:30.445021 DQM Delay:
6416 00:40:30.445561 DQM0 = 10, DQM1 = 16
6417 00:40:30.448200 DQ Delay:
6418 00:40:30.448727 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =4
6419 00:40:30.451546 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6420 00:40:30.455132 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =12
6421 00:40:30.458138 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6422 00:40:30.458556
6423 00:40:30.458884
6424 00:40:30.468186 [DQSOSCAuto] RK0, (LSB)MR18= 0xa396, (MSB)MR19= 0xc0c, tDQSOscB0 = 391 ps tDQSOscB1 = 389 ps
6425 00:40:30.472215 CH0 RK0: MR19=C0C, MR18=A396
6426 00:40:30.477696 CH0_RK0: MR19=0xC0C, MR18=0xA396, DQSOSC=389, MR23=63, INC=390, DEC=260
6427 00:40:30.478124 ==
6428 00:40:30.481763 Dram Type= 6, Freq= 0, CH_0, rank 1
6429 00:40:30.484823 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6430 00:40:30.485243 ==
6431 00:40:30.488272 [Gating] SW mode calibration
6432 00:40:30.494632 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6433 00:40:30.501185 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6434 00:40:30.504213 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6435 00:40:30.507582 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6436 00:40:30.514142 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6437 00:40:30.517244 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6438 00:40:30.520781 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6439 00:40:30.527692 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6440 00:40:30.530842 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6441 00:40:30.533955 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6442 00:40:30.540769 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6443 00:40:30.541372 Total UI for P1: 0, mck2ui 16
6444 00:40:30.547063 best dqsien dly found for B0: ( 0, 14, 24)
6445 00:40:30.547481 Total UI for P1: 0, mck2ui 16
6446 00:40:30.553933 best dqsien dly found for B1: ( 0, 14, 24)
6447 00:40:30.557240 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6448 00:40:30.560801 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6449 00:40:30.561304
6450 00:40:30.563220 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6451 00:40:30.566528 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6452 00:40:30.570263 [Gating] SW calibration Done
6453 00:40:30.570681 ==
6454 00:40:30.573498 Dram Type= 6, Freq= 0, CH_0, rank 1
6455 00:40:30.576594 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6456 00:40:30.577219 ==
6457 00:40:30.580132 RX Vref Scan: 0
6458 00:40:30.580586
6459 00:40:30.580935 RX Vref 0 -> 0, step: 1
6460 00:40:30.581443
6461 00:40:30.583560 RX Delay -410 -> 252, step: 16
6462 00:40:30.590581 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6463 00:40:30.593601 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6464 00:40:30.596655 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6465 00:40:30.600047 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6466 00:40:30.606469 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6467 00:40:30.610151 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6468 00:40:30.612914 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6469 00:40:30.616320 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6470 00:40:30.622926 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6471 00:40:30.626128 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6472 00:40:30.629340 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6473 00:40:30.636249 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6474 00:40:30.639398 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6475 00:40:30.642545 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6476 00:40:30.645764 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6477 00:40:30.652455 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6478 00:40:30.652876 ==
6479 00:40:30.655701 Dram Type= 6, Freq= 0, CH_0, rank 1
6480 00:40:30.658986 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6481 00:40:30.659417 ==
6482 00:40:30.659755 DQS Delay:
6483 00:40:30.662120 DQS0 = 35, DQS1 = 59
6484 00:40:30.662535 DQM Delay:
6485 00:40:30.666001 DQM0 = 6, DQM1 = 16
6486 00:40:30.666451 DQ Delay:
6487 00:40:30.668945 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =0
6488 00:40:30.672432 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6489 00:40:30.675764 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6490 00:40:30.679018 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6491 00:40:30.679486
6492 00:40:30.679923
6493 00:40:30.680402 ==
6494 00:40:30.682217 Dram Type= 6, Freq= 0, CH_0, rank 1
6495 00:40:30.685230 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6496 00:40:30.685722 ==
6497 00:40:30.686162
6498 00:40:30.686576
6499 00:40:30.688592 TX Vref Scan disable
6500 00:40:30.691838 == TX Byte 0 ==
6501 00:40:30.695156 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6502 00:40:30.698459 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6503 00:40:30.702275 == TX Byte 1 ==
6504 00:40:30.705161 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6505 00:40:30.708310 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6506 00:40:30.708726 ==
6507 00:40:30.711808 Dram Type= 6, Freq= 0, CH_0, rank 1
6508 00:40:30.715611 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6509 00:40:30.716057 ==
6510 00:40:30.716492
6511 00:40:30.718916
6512 00:40:30.719448 TX Vref Scan disable
6513 00:40:30.722183 == TX Byte 0 ==
6514 00:40:30.725463 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6515 00:40:30.728421 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6516 00:40:30.732320 == TX Byte 1 ==
6517 00:40:30.735780 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6518 00:40:30.738673 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6519 00:40:30.739102
6520 00:40:30.739538 [DATLAT]
6521 00:40:30.741625 Freq=400, CH0 RK1
6522 00:40:30.742056
6523 00:40:30.745462 DATLAT Default: 0xe
6524 00:40:30.745894 0, 0xFFFF, sum = 0
6525 00:40:30.748251 1, 0xFFFF, sum = 0
6526 00:40:30.748814 2, 0xFFFF, sum = 0
6527 00:40:30.752280 3, 0xFFFF, sum = 0
6528 00:40:30.752843 4, 0xFFFF, sum = 0
6529 00:40:30.755076 5, 0xFFFF, sum = 0
6530 00:40:30.755515 6, 0xFFFF, sum = 0
6531 00:40:30.757956 7, 0xFFFF, sum = 0
6532 00:40:30.758391 8, 0xFFFF, sum = 0
6533 00:40:30.761854 9, 0xFFFF, sum = 0
6534 00:40:30.762387 10, 0xFFFF, sum = 0
6535 00:40:30.765048 11, 0xFFFF, sum = 0
6536 00:40:30.765617 12, 0xFFFF, sum = 0
6537 00:40:30.768026 13, 0x0, sum = 1
6538 00:40:30.768557 14, 0x0, sum = 2
6539 00:40:30.771468 15, 0x0, sum = 3
6540 00:40:30.772005 16, 0x0, sum = 4
6541 00:40:30.774288 best_step = 14
6542 00:40:30.774701
6543 00:40:30.775028 ==
6544 00:40:30.777626 Dram Type= 6, Freq= 0, CH_0, rank 1
6545 00:40:30.780846 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6546 00:40:30.781309 ==
6547 00:40:30.784632 RX Vref Scan: 0
6548 00:40:30.785072
6549 00:40:30.785569 RX Vref 0 -> 0, step: 1
6550 00:40:30.786101
6551 00:40:30.787695 RX Delay -359 -> 252, step: 8
6552 00:40:30.795582 iDelay=209, Bit 0, Center -36 (-271 ~ 200) 472
6553 00:40:30.799047 iDelay=209, Bit 1, Center -32 (-271 ~ 208) 480
6554 00:40:30.802719 iDelay=209, Bit 2, Center -40 (-279 ~ 200) 480
6555 00:40:30.808875 iDelay=209, Bit 3, Center -36 (-271 ~ 200) 472
6556 00:40:30.812450 iDelay=209, Bit 4, Center -32 (-271 ~ 208) 480
6557 00:40:30.815714 iDelay=209, Bit 5, Center -44 (-279 ~ 192) 472
6558 00:40:30.819254 iDelay=209, Bit 6, Center -28 (-263 ~ 208) 472
6559 00:40:30.825392 iDelay=209, Bit 7, Center -28 (-263 ~ 208) 472
6560 00:40:30.828875 iDelay=209, Bit 8, Center -52 (-295 ~ 192) 488
6561 00:40:30.831796 iDelay=209, Bit 9, Center -60 (-303 ~ 184) 488
6562 00:40:30.835213 iDelay=209, Bit 10, Center -44 (-287 ~ 200) 488
6563 00:40:30.842169 iDelay=209, Bit 11, Center -52 (-295 ~ 192) 488
6564 00:40:30.845037 iDelay=209, Bit 12, Center -36 (-279 ~ 208) 488
6565 00:40:30.848674 iDelay=209, Bit 13, Center -36 (-279 ~ 208) 488
6566 00:40:30.852073 iDelay=209, Bit 14, Center -36 (-279 ~ 208) 488
6567 00:40:30.858464 iDelay=209, Bit 15, Center -36 (-279 ~ 208) 488
6568 00:40:30.858983 ==
6569 00:40:30.862349 Dram Type= 6, Freq= 0, CH_0, rank 1
6570 00:40:30.865963 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6571 00:40:30.866381 ==
6572 00:40:30.866711 DQS Delay:
6573 00:40:30.868604 DQS0 = 44, DQS1 = 60
6574 00:40:30.869014 DQM Delay:
6575 00:40:30.871376 DQM0 = 9, DQM1 = 16
6576 00:40:30.871787 DQ Delay:
6577 00:40:30.875193 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =8
6578 00:40:30.878080 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =16
6579 00:40:30.881398 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6580 00:40:30.884515 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6581 00:40:30.884967
6582 00:40:30.885331
6583 00:40:30.894784 [DQSOSCAuto] RK1, (LSB)MR18= 0x8e87, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 392 ps
6584 00:40:30.895306 CH0 RK1: MR19=C0C, MR18=8E87
6585 00:40:30.901158 CH0_RK1: MR19=0xC0C, MR18=0x8E87, DQSOSC=392, MR23=63, INC=384, DEC=256
6586 00:40:30.904899 [RxdqsGatingPostProcess] freq 400
6587 00:40:30.912077 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6588 00:40:30.914757 best DQS0 dly(2T, 0.5T) = (0, 10)
6589 00:40:30.918092 best DQS1 dly(2T, 0.5T) = (0, 10)
6590 00:40:30.921311 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6591 00:40:30.924398 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6592 00:40:30.927904 best DQS0 dly(2T, 0.5T) = (0, 10)
6593 00:40:30.928459 best DQS1 dly(2T, 0.5T) = (0, 10)
6594 00:40:30.931402 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6595 00:40:30.934476 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6596 00:40:30.938280 Pre-setting of DQS Precalculation
6597 00:40:30.944497 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6598 00:40:30.945053 ==
6599 00:40:30.947343 Dram Type= 6, Freq= 0, CH_1, rank 0
6600 00:40:30.951011 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6601 00:40:30.951643 ==
6602 00:40:30.957934 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6603 00:40:30.964308 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6604 00:40:30.967612 [CA 0] Center 36 (8~64) winsize 57
6605 00:40:30.971050 [CA 1] Center 36 (8~64) winsize 57
6606 00:40:30.971607 [CA 2] Center 36 (8~64) winsize 57
6607 00:40:30.974006 [CA 3] Center 36 (8~64) winsize 57
6608 00:40:30.977167 [CA 4] Center 36 (8~64) winsize 57
6609 00:40:30.980850 [CA 5] Center 36 (8~64) winsize 57
6610 00:40:30.981351
6611 00:40:30.983887 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6612 00:40:30.987086
6613 00:40:30.990628 [CATrainingPosCal] consider 1 rank data
6614 00:40:30.991170 u2DelayCellTimex100 = 270/100 ps
6615 00:40:30.997622 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6616 00:40:31.000077 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6617 00:40:31.003607 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6618 00:40:31.007457 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6619 00:40:31.010245 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6620 00:40:31.013831 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6621 00:40:31.014283
6622 00:40:31.016956 CA PerBit enable=1, Macro0, CA PI delay=36
6623 00:40:31.017550
6624 00:40:31.020025 [CBTSetCACLKResult] CA Dly = 36
6625 00:40:31.023268 CS Dly: 1 (0~32)
6626 00:40:31.023714 ==
6627 00:40:31.027331 Dram Type= 6, Freq= 0, CH_1, rank 1
6628 00:40:31.029706 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6629 00:40:31.030166 ==
6630 00:40:31.036960 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6631 00:40:31.040003 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6632 00:40:31.043346 [CA 0] Center 36 (8~64) winsize 57
6633 00:40:31.046804 [CA 1] Center 36 (8~64) winsize 57
6634 00:40:31.049772 [CA 2] Center 36 (8~64) winsize 57
6635 00:40:31.052986 [CA 3] Center 36 (8~64) winsize 57
6636 00:40:31.056702 [CA 4] Center 36 (8~64) winsize 57
6637 00:40:31.059595 [CA 5] Center 36 (8~64) winsize 57
6638 00:40:31.060007
6639 00:40:31.063117 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6640 00:40:31.063531
6641 00:40:31.066201 [CATrainingPosCal] consider 2 rank data
6642 00:40:31.069634 u2DelayCellTimex100 = 270/100 ps
6643 00:40:31.072701 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6644 00:40:31.079683 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6645 00:40:31.083005 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6646 00:40:31.085895 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6647 00:40:31.089525 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6648 00:40:31.092450 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6649 00:40:31.092866
6650 00:40:31.096275 CA PerBit enable=1, Macro0, CA PI delay=36
6651 00:40:31.096687
6652 00:40:31.099143 [CBTSetCACLKResult] CA Dly = 36
6653 00:40:31.102727 CS Dly: 1 (0~32)
6654 00:40:31.103179
6655 00:40:31.106443 ----->DramcWriteLeveling(PI) begin...
6656 00:40:31.106979 ==
6657 00:40:31.109633 Dram Type= 6, Freq= 0, CH_1, rank 0
6658 00:40:31.112210 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6659 00:40:31.112625 ==
6660 00:40:31.115734 Write leveling (Byte 0): 40 => 8
6661 00:40:31.119080 Write leveling (Byte 1): 40 => 8
6662 00:40:31.122699 DramcWriteLeveling(PI) end<-----
6663 00:40:31.123108
6664 00:40:31.123432 ==
6665 00:40:31.125643 Dram Type= 6, Freq= 0, CH_1, rank 0
6666 00:40:31.129392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6667 00:40:31.129928 ==
6668 00:40:31.132180 [Gating] SW mode calibration
6669 00:40:31.139244 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6670 00:40:31.145901 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6671 00:40:31.148924 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6672 00:40:31.152472 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6673 00:40:31.159002 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6674 00:40:31.161879 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6675 00:40:31.165422 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6676 00:40:31.171846 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6677 00:40:31.175002 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6678 00:40:31.178160 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6679 00:40:31.184871 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6680 00:40:31.188299 Total UI for P1: 0, mck2ui 16
6681 00:40:31.191768 best dqsien dly found for B0: ( 0, 14, 24)
6682 00:40:31.192294 Total UI for P1: 0, mck2ui 16
6683 00:40:31.198543 best dqsien dly found for B1: ( 0, 14, 24)
6684 00:40:31.201168 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6685 00:40:31.204866 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6686 00:40:31.205491
6687 00:40:31.208214 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6688 00:40:31.211339 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6689 00:40:31.214755 [Gating] SW calibration Done
6690 00:40:31.215184 ==
6691 00:40:31.218271 Dram Type= 6, Freq= 0, CH_1, rank 0
6692 00:40:31.221071 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6693 00:40:31.221555 ==
6694 00:40:31.225032 RX Vref Scan: 0
6695 00:40:31.225612
6696 00:40:31.228164 RX Vref 0 -> 0, step: 1
6697 00:40:31.228591
6698 00:40:31.229026 RX Delay -410 -> 252, step: 16
6699 00:40:31.234704 iDelay=230, Bit 0, Center -19 (-266 ~ 229) 496
6700 00:40:31.237501 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6701 00:40:31.241360 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6702 00:40:31.244589 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6703 00:40:31.251374 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6704 00:40:31.254910 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6705 00:40:31.257939 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6706 00:40:31.264324 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6707 00:40:31.267283 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6708 00:40:31.271426 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6709 00:40:31.274407 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6710 00:40:31.280910 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6711 00:40:31.284201 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6712 00:40:31.287282 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6713 00:40:31.291655 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6714 00:40:31.297054 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6715 00:40:31.297513 ==
6716 00:40:31.300438 Dram Type= 6, Freq= 0, CH_1, rank 0
6717 00:40:31.304088 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6718 00:40:31.304668 ==
6719 00:40:31.305169 DQS Delay:
6720 00:40:31.307820 DQS0 = 35, DQS1 = 51
6721 00:40:31.308446 DQM Delay:
6722 00:40:31.310319 DQM0 = 6, DQM1 = 13
6723 00:40:31.310784 DQ Delay:
6724 00:40:31.313465 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0
6725 00:40:31.316868 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6726 00:40:31.320389 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6727 00:40:31.323359 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =16
6728 00:40:31.323777
6729 00:40:31.324105
6730 00:40:31.324412 ==
6731 00:40:31.326747 Dram Type= 6, Freq= 0, CH_1, rank 0
6732 00:40:31.329838 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6733 00:40:31.330261 ==
6734 00:40:31.330595
6735 00:40:31.333362
6736 00:40:31.333778 TX Vref Scan disable
6737 00:40:31.336745 == TX Byte 0 ==
6738 00:40:31.340503 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6739 00:40:31.343552 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6740 00:40:31.346434 == TX Byte 1 ==
6741 00:40:31.349793 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6742 00:40:31.353339 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6743 00:40:31.353758 ==
6744 00:40:31.356929 Dram Type= 6, Freq= 0, CH_1, rank 0
6745 00:40:31.359719 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6746 00:40:31.360292 ==
6747 00:40:31.363324
6748 00:40:31.363742
6749 00:40:31.364071 TX Vref Scan disable
6750 00:40:31.366255 == TX Byte 0 ==
6751 00:40:31.369945 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6752 00:40:31.372979 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6753 00:40:31.376581 == TX Byte 1 ==
6754 00:40:31.379799 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6755 00:40:31.383026 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6756 00:40:31.383446
6757 00:40:31.383774 [DATLAT]
6758 00:40:31.386367 Freq=400, CH1 RK0
6759 00:40:31.386789
6760 00:40:31.389664 DATLAT Default: 0xf
6761 00:40:31.390106 0, 0xFFFF, sum = 0
6762 00:40:31.392594 1, 0xFFFF, sum = 0
6763 00:40:31.393022 2, 0xFFFF, sum = 0
6764 00:40:31.396379 3, 0xFFFF, sum = 0
6765 00:40:31.396806 4, 0xFFFF, sum = 0
6766 00:40:31.399831 5, 0xFFFF, sum = 0
6767 00:40:31.400273 6, 0xFFFF, sum = 0
6768 00:40:31.402629 7, 0xFFFF, sum = 0
6769 00:40:31.403054 8, 0xFFFF, sum = 0
6770 00:40:31.406884 9, 0xFFFF, sum = 0
6771 00:40:31.407420 10, 0xFFFF, sum = 0
6772 00:40:31.409199 11, 0xFFFF, sum = 0
6773 00:40:31.409672 12, 0xFFFF, sum = 0
6774 00:40:31.412955 13, 0x0, sum = 1
6775 00:40:31.413415 14, 0x0, sum = 2
6776 00:40:31.416118 15, 0x0, sum = 3
6777 00:40:31.416828 16, 0x0, sum = 4
6778 00:40:31.419141 best_step = 14
6779 00:40:31.419789
6780 00:40:31.420350 ==
6781 00:40:31.422772 Dram Type= 6, Freq= 0, CH_1, rank 0
6782 00:40:31.425792 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6783 00:40:31.426216 ==
6784 00:40:31.429279 RX Vref Scan: 1
6785 00:40:31.429701
6786 00:40:31.430031 RX Vref 0 -> 0, step: 1
6787 00:40:31.430646
6788 00:40:31.432223 RX Delay -343 -> 252, step: 8
6789 00:40:31.432644
6790 00:40:31.435948 Set Vref, RX VrefLevel [Byte0]: 51
6791 00:40:31.439206 [Byte1]: 53
6792 00:40:31.443827
6793 00:40:31.444289 Final RX Vref Byte 0 = 51 to rank0
6794 00:40:31.447116 Final RX Vref Byte 1 = 53 to rank0
6795 00:40:31.450746 Final RX Vref Byte 0 = 51 to rank1
6796 00:40:31.454122 Final RX Vref Byte 1 = 53 to rank1==
6797 00:40:31.456923 Dram Type= 6, Freq= 0, CH_1, rank 0
6798 00:40:31.463995 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6799 00:40:31.464504 ==
6800 00:40:31.464839 DQS Delay:
6801 00:40:31.467451 DQS0 = 44, DQS1 = 52
6802 00:40:31.467869 DQM Delay:
6803 00:40:31.468202 DQM0 = 10, DQM1 = 10
6804 00:40:31.470627 DQ Delay:
6805 00:40:31.473949 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =12
6806 00:40:31.476674 DQ4 =8, DQ5 =16, DQ6 =24, DQ7 =4
6807 00:40:31.477093 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
6808 00:40:31.480200 DQ12 =20, DQ13 =20, DQ14 =16, DQ15 =16
6809 00:40:31.483132
6810 00:40:31.483551
6811 00:40:31.490239 [DQSOSCAuto] RK0, (LSB)MR18= 0x6f96, (MSB)MR19= 0xc0c, tDQSOscB0 = 391 ps tDQSOscB1 = 395 ps
6812 00:40:31.493437 CH1 RK0: MR19=C0C, MR18=6F96
6813 00:40:31.500106 CH1_RK0: MR19=0xC0C, MR18=0x6F96, DQSOSC=391, MR23=63, INC=386, DEC=257
6814 00:40:31.500530 ==
6815 00:40:31.503464 Dram Type= 6, Freq= 0, CH_1, rank 1
6816 00:40:31.506316 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6817 00:40:31.506740 ==
6818 00:40:31.509814 [Gating] SW mode calibration
6819 00:40:31.516484 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6820 00:40:31.523106 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6821 00:40:31.526387 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6822 00:40:31.529397 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6823 00:40:31.536047 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6824 00:40:31.539543 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6825 00:40:31.543163 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6826 00:40:31.549362 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6827 00:40:31.552794 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6828 00:40:31.556032 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6829 00:40:31.563172 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6830 00:40:31.563676 Total UI for P1: 0, mck2ui 16
6831 00:40:31.569219 best dqsien dly found for B0: ( 0, 14, 24)
6832 00:40:31.569758 Total UI for P1: 0, mck2ui 16
6833 00:40:31.576084 best dqsien dly found for B1: ( 0, 14, 24)
6834 00:40:31.578972 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6835 00:40:31.582214 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6836 00:40:31.582638
6837 00:40:31.585435 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6838 00:40:31.589067 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6839 00:40:31.592177 [Gating] SW calibration Done
6840 00:40:31.592746 ==
6841 00:40:31.595185 Dram Type= 6, Freq= 0, CH_1, rank 1
6842 00:40:31.598590 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6843 00:40:31.599104 ==
6844 00:40:31.601990 RX Vref Scan: 0
6845 00:40:31.602410
6846 00:40:31.605345 RX Vref 0 -> 0, step: 1
6847 00:40:31.605766
6848 00:40:31.606102 RX Delay -410 -> 252, step: 16
6849 00:40:31.612216 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6850 00:40:31.615228 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6851 00:40:31.618633 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6852 00:40:31.625198 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6853 00:40:31.628582 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6854 00:40:31.631725 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6855 00:40:31.635328 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6856 00:40:31.641702 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6857 00:40:31.645550 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6858 00:40:31.648186 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6859 00:40:31.651646 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6860 00:40:31.658449 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6861 00:40:31.661447 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6862 00:40:31.665142 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6863 00:40:31.668309 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6864 00:40:31.674425 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6865 00:40:31.674887 ==
6866 00:40:31.677712 Dram Type= 6, Freq= 0, CH_1, rank 1
6867 00:40:31.681115 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6868 00:40:31.681718 ==
6869 00:40:31.682062 DQS Delay:
6870 00:40:31.684481 DQS0 = 43, DQS1 = 51
6871 00:40:31.685021 DQM Delay:
6872 00:40:31.688224 DQM0 = 9, DQM1 = 14
6873 00:40:31.688730 DQ Delay:
6874 00:40:31.691361 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6875 00:40:31.694246 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =8
6876 00:40:31.698359 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6877 00:40:31.700974 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =24
6878 00:40:31.701615
6879 00:40:31.702026
6880 00:40:31.702343 ==
6881 00:40:31.704163 Dram Type= 6, Freq= 0, CH_1, rank 1
6882 00:40:31.707975 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6883 00:40:31.708523 ==
6884 00:40:31.708861
6885 00:40:31.710976
6886 00:40:31.711567 TX Vref Scan disable
6887 00:40:31.714141 == TX Byte 0 ==
6888 00:40:31.717147 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6889 00:40:31.720784 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6890 00:40:31.723821 == TX Byte 1 ==
6891 00:40:31.727304 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6892 00:40:31.730722 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6893 00:40:31.731421 ==
6894 00:40:31.734167 Dram Type= 6, Freq= 0, CH_1, rank 1
6895 00:40:31.737175 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6896 00:40:31.740255 ==
6897 00:40:31.740672
6898 00:40:31.741003
6899 00:40:31.741354 TX Vref Scan disable
6900 00:40:31.743967 == TX Byte 0 ==
6901 00:40:31.747168 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6902 00:40:31.750817 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6903 00:40:31.753802 == TX Byte 1 ==
6904 00:40:31.756897 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6905 00:40:31.760542 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6906 00:40:31.761075
6907 00:40:31.761447 [DATLAT]
6908 00:40:31.764050 Freq=400, CH1 RK1
6909 00:40:31.764568
6910 00:40:31.767285 DATLAT Default: 0xe
6911 00:40:31.767708 0, 0xFFFF, sum = 0
6912 00:40:31.769921 1, 0xFFFF, sum = 0
6913 00:40:31.770347 2, 0xFFFF, sum = 0
6914 00:40:31.773763 3, 0xFFFF, sum = 0
6915 00:40:31.774280 4, 0xFFFF, sum = 0
6916 00:40:31.777487 5, 0xFFFF, sum = 0
6917 00:40:31.778019 6, 0xFFFF, sum = 0
6918 00:40:31.780411 7, 0xFFFF, sum = 0
6919 00:40:31.780836 8, 0xFFFF, sum = 0
6920 00:40:31.783676 9, 0xFFFF, sum = 0
6921 00:40:31.784104 10, 0xFFFF, sum = 0
6922 00:40:31.786486 11, 0xFFFF, sum = 0
6923 00:40:31.786929 12, 0xFFFF, sum = 0
6924 00:40:31.790022 13, 0x0, sum = 1
6925 00:40:31.790447 14, 0x0, sum = 2
6926 00:40:31.793550 15, 0x0, sum = 3
6927 00:40:31.793975 16, 0x0, sum = 4
6928 00:40:31.797429 best_step = 14
6929 00:40:31.797967
6930 00:40:31.798303 ==
6931 00:40:31.800404 Dram Type= 6, Freq= 0, CH_1, rank 1
6932 00:40:31.803978 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6933 00:40:31.804497 ==
6934 00:40:31.806769 RX Vref Scan: 0
6935 00:40:31.807187
6936 00:40:31.807518 RX Vref 0 -> 0, step: 1
6937 00:40:31.807827
6938 00:40:31.810026 RX Delay -343 -> 252, step: 8
6939 00:40:31.818230 iDelay=217, Bit 0, Center -32 (-271 ~ 208) 480
6940 00:40:31.821122 iDelay=217, Bit 1, Center -40 (-287 ~ 208) 496
6941 00:40:31.824908 iDelay=217, Bit 2, Center -48 (-295 ~ 200) 496
6942 00:40:31.830801 iDelay=217, Bit 3, Center -40 (-287 ~ 208) 496
6943 00:40:31.834026 iDelay=217, Bit 4, Center -40 (-287 ~ 208) 496
6944 00:40:31.837931 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6945 00:40:31.840680 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6946 00:40:31.847299 iDelay=217, Bit 7, Center -40 (-287 ~ 208) 496
6947 00:40:31.850991 iDelay=217, Bit 8, Center -52 (-295 ~ 192) 488
6948 00:40:31.853815 iDelay=217, Bit 9, Center -52 (-295 ~ 192) 488
6949 00:40:31.857296 iDelay=217, Bit 10, Center -40 (-287 ~ 208) 496
6950 00:40:31.863717 iDelay=217, Bit 11, Center -48 (-287 ~ 192) 480
6951 00:40:31.866879 iDelay=217, Bit 12, Center -36 (-279 ~ 208) 488
6952 00:40:31.870252 iDelay=217, Bit 13, Center -36 (-279 ~ 208) 488
6953 00:40:31.873509 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6954 00:40:31.880444 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6955 00:40:31.880856 ==
6956 00:40:31.884020 Dram Type= 6, Freq= 0, CH_1, rank 1
6957 00:40:31.886988 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6958 00:40:31.887404 ==
6959 00:40:31.890319 DQS Delay:
6960 00:40:31.890728 DQS0 = 48, DQS1 = 52
6961 00:40:31.891055 DQM Delay:
6962 00:40:31.893613 DQM0 = 11, DQM1 = 10
6963 00:40:31.894024 DQ Delay:
6964 00:40:31.896957 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6965 00:40:31.899859 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =8
6966 00:40:31.903471 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6967 00:40:31.906608 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6968 00:40:31.907024
6969 00:40:31.907349
6970 00:40:31.916330 [DQSOSCAuto] RK1, (LSB)MR18= 0x79b1, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 394 ps
6971 00:40:31.916880 CH1 RK1: MR19=C0C, MR18=79B1
6972 00:40:31.922847 CH1_RK1: MR19=0xC0C, MR18=0x79B1, DQSOSC=387, MR23=63, INC=394, DEC=262
6973 00:40:31.925818 [RxdqsGatingPostProcess] freq 400
6974 00:40:31.932828 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6975 00:40:31.936316 best DQS0 dly(2T, 0.5T) = (0, 10)
6976 00:40:31.939924 best DQS1 dly(2T, 0.5T) = (0, 10)
6977 00:40:31.942395 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6978 00:40:31.945998 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6979 00:40:31.949655 best DQS0 dly(2T, 0.5T) = (0, 10)
6980 00:40:31.952430 best DQS1 dly(2T, 0.5T) = (0, 10)
6981 00:40:31.956019 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6982 00:40:31.958809 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6983 00:40:31.962503 Pre-setting of DQS Precalculation
6984 00:40:31.965798 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6985 00:40:31.972503 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6986 00:40:31.979167 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6987 00:40:31.979684
6988 00:40:31.980145
6989 00:40:31.982583 [Calibration Summary] 800 Mbps
6990 00:40:31.985606 CH 0, Rank 0
6991 00:40:31.986078 SW Impedance : PASS
6992 00:40:31.988967 DUTY Scan : NO K
6993 00:40:31.992079 ZQ Calibration : PASS
6994 00:40:31.992588 Jitter Meter : NO K
6995 00:40:31.995270 CBT Training : PASS
6996 00:40:31.998796 Write leveling : PASS
6997 00:40:31.999209 RX DQS gating : PASS
6998 00:40:32.002223 RX DQ/DQS(RDDQC) : PASS
6999 00:40:32.005093 TX DQ/DQS : PASS
7000 00:40:32.005552 RX DATLAT : PASS
7001 00:40:32.008790 RX DQ/DQS(Engine): PASS
7002 00:40:32.012123 TX OE : NO K
7003 00:40:32.012538 All Pass.
7004 00:40:32.012878
7005 00:40:32.013217 CH 0, Rank 1
7006 00:40:32.015081 SW Impedance : PASS
7007 00:40:32.018662 DUTY Scan : NO K
7008 00:40:32.019074 ZQ Calibration : PASS
7009 00:40:32.021845 Jitter Meter : NO K
7010 00:40:32.022258 CBT Training : PASS
7011 00:40:32.024908 Write leveling : NO K
7012 00:40:32.028396 RX DQS gating : PASS
7013 00:40:32.028841 RX DQ/DQS(RDDQC) : PASS
7014 00:40:32.031874 TX DQ/DQS : PASS
7015 00:40:32.034788 RX DATLAT : PASS
7016 00:40:32.035302 RX DQ/DQS(Engine): PASS
7017 00:40:32.038103 TX OE : NO K
7018 00:40:32.038610 All Pass.
7019 00:40:32.038942
7020 00:40:32.041363 CH 1, Rank 0
7021 00:40:32.041798 SW Impedance : PASS
7022 00:40:32.045049 DUTY Scan : NO K
7023 00:40:32.048212 ZQ Calibration : PASS
7024 00:40:32.048750 Jitter Meter : NO K
7025 00:40:32.051306 CBT Training : PASS
7026 00:40:32.054841 Write leveling : PASS
7027 00:40:32.055297 RX DQS gating : PASS
7028 00:40:32.058667 RX DQ/DQS(RDDQC) : PASS
7029 00:40:32.061577 TX DQ/DQS : PASS
7030 00:40:32.062115 RX DATLAT : PASS
7031 00:40:32.065072 RX DQ/DQS(Engine): PASS
7032 00:40:32.067957 TX OE : NO K
7033 00:40:32.068373 All Pass.
7034 00:40:32.068788
7035 00:40:32.069099 CH 1, Rank 1
7036 00:40:32.071348 SW Impedance : PASS
7037 00:40:32.074531 DUTY Scan : NO K
7038 00:40:32.075084 ZQ Calibration : PASS
7039 00:40:32.077880 Jitter Meter : NO K
7040 00:40:32.080619 CBT Training : PASS
7041 00:40:32.081044 Write leveling : NO K
7042 00:40:32.084380 RX DQS gating : PASS
7043 00:40:32.087186 RX DQ/DQS(RDDQC) : PASS
7044 00:40:32.087600 TX DQ/DQS : PASS
7045 00:40:32.091438 RX DATLAT : PASS
7046 00:40:32.094018 RX DQ/DQS(Engine): PASS
7047 00:40:32.094562 TX OE : NO K
7048 00:40:32.097458 All Pass.
7049 00:40:32.097865
7050 00:40:32.098190 DramC Write-DBI off
7051 00:40:32.100466 PER_BANK_REFRESH: Hybrid Mode
7052 00:40:32.100929 TX_TRACKING: ON
7053 00:40:32.110290 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7054 00:40:32.114423 [FAST_K] Save calibration result to emmc
7055 00:40:32.117037 dramc_set_vcore_voltage set vcore to 725000
7056 00:40:32.120645 Read voltage for 1600, 0
7057 00:40:32.121058 Vio18 = 0
7058 00:40:32.123844 Vcore = 725000
7059 00:40:32.124259 Vdram = 0
7060 00:40:32.124587 Vddq = 0
7061 00:40:32.127239 Vmddr = 0
7062 00:40:32.130568 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7063 00:40:32.137131 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7064 00:40:32.137622 MEM_TYPE=3, freq_sel=13
7065 00:40:32.140249 sv_algorithm_assistance_LP4_3733
7066 00:40:32.147303 ============ PULL DRAM RESETB DOWN ============
7067 00:40:32.150234 ========== PULL DRAM RESETB DOWN end =========
7068 00:40:32.153637 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7069 00:40:32.156700 ===================================
7070 00:40:32.160216 LPDDR4 DRAM CONFIGURATION
7071 00:40:32.163499 ===================================
7072 00:40:32.166478 EX_ROW_EN[0] = 0x0
7073 00:40:32.166896 EX_ROW_EN[1] = 0x0
7074 00:40:32.169802 LP4Y_EN = 0x0
7075 00:40:32.170216 WORK_FSP = 0x1
7076 00:40:32.173424 WL = 0x5
7077 00:40:32.173840 RL = 0x5
7078 00:40:32.176663 BL = 0x2
7079 00:40:32.177181 RPST = 0x0
7080 00:40:32.180034 RD_PRE = 0x0
7081 00:40:32.180449 WR_PRE = 0x1
7082 00:40:32.183332 WR_PST = 0x1
7083 00:40:32.184055 DBI_WR = 0x0
7084 00:40:32.186373 DBI_RD = 0x0
7085 00:40:32.186789 OTF = 0x1
7086 00:40:32.189706 ===================================
7087 00:40:32.193449 ===================================
7088 00:40:32.196359 ANA top config
7089 00:40:32.199727 ===================================
7090 00:40:32.203029 DLL_ASYNC_EN = 0
7091 00:40:32.203488 ALL_SLAVE_EN = 0
7092 00:40:32.206283 NEW_RANK_MODE = 1
7093 00:40:32.209539 DLL_IDLE_MODE = 1
7094 00:40:32.213449 LP45_APHY_COMB_EN = 1
7095 00:40:32.214001 TX_ODT_DIS = 0
7096 00:40:32.216063 NEW_8X_MODE = 1
7097 00:40:32.219224 ===================================
7098 00:40:32.222737 ===================================
7099 00:40:32.225884 data_rate = 3200
7100 00:40:32.229119 CKR = 1
7101 00:40:32.232462 DQ_P2S_RATIO = 8
7102 00:40:32.235800 ===================================
7103 00:40:32.238910 CA_P2S_RATIO = 8
7104 00:40:32.242460 DQ_CA_OPEN = 0
7105 00:40:32.242880 DQ_SEMI_OPEN = 0
7106 00:40:32.245331 CA_SEMI_OPEN = 0
7107 00:40:32.249546 CA_FULL_RATE = 0
7108 00:40:32.252481 DQ_CKDIV4_EN = 0
7109 00:40:32.256171 CA_CKDIV4_EN = 0
7110 00:40:32.259655 CA_PREDIV_EN = 0
7111 00:40:32.260209 PH8_DLY = 12
7112 00:40:32.262591 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7113 00:40:32.266194 DQ_AAMCK_DIV = 4
7114 00:40:32.268587 CA_AAMCK_DIV = 4
7115 00:40:32.272336 CA_ADMCK_DIV = 4
7116 00:40:32.275446 DQ_TRACK_CA_EN = 0
7117 00:40:32.279031 CA_PICK = 1600
7118 00:40:32.279584 CA_MCKIO = 1600
7119 00:40:32.282075 MCKIO_SEMI = 0
7120 00:40:32.285232 PLL_FREQ = 3068
7121 00:40:32.288800 DQ_UI_PI_RATIO = 32
7122 00:40:32.291804 CA_UI_PI_RATIO = 0
7123 00:40:32.295839 ===================================
7124 00:40:32.298702 ===================================
7125 00:40:32.301574 memory_type:LPDDR4
7126 00:40:32.302042 GP_NUM : 10
7127 00:40:32.304975 SRAM_EN : 1
7128 00:40:32.308254 MD32_EN : 0
7129 00:40:32.311367 ===================================
7130 00:40:32.311825 [ANA_INIT] >>>>>>>>>>>>>>
7131 00:40:32.314850 <<<<<< [CONFIGURE PHASE]: ANA_TX
7132 00:40:32.318394 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7133 00:40:32.321551 ===================================
7134 00:40:32.324689 data_rate = 3200,PCW = 0X7600
7135 00:40:32.327648 ===================================
7136 00:40:32.331142 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7137 00:40:32.337865 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7138 00:40:32.341329 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7139 00:40:32.347784 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7140 00:40:32.350794 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7141 00:40:32.354378 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7142 00:40:32.354928 [ANA_INIT] flow start
7143 00:40:32.357551 [ANA_INIT] PLL >>>>>>>>
7144 00:40:32.360802 [ANA_INIT] PLL <<<<<<<<
7145 00:40:32.364285 [ANA_INIT] MIDPI >>>>>>>>
7146 00:40:32.364727 [ANA_INIT] MIDPI <<<<<<<<
7147 00:40:32.367752 [ANA_INIT] DLL >>>>>>>>
7148 00:40:32.371313 [ANA_INIT] DLL <<<<<<<<
7149 00:40:32.371835 [ANA_INIT] flow end
7150 00:40:32.373990 ============ LP4 DIFF to SE enter ============
7151 00:40:32.380819 ============ LP4 DIFF to SE exit ============
7152 00:40:32.381507 [ANA_INIT] <<<<<<<<<<<<<
7153 00:40:32.384365 [Flow] Enable top DCM control >>>>>
7154 00:40:32.387550 [Flow] Enable top DCM control <<<<<
7155 00:40:32.390838 Enable DLL master slave shuffle
7156 00:40:32.397036 ==============================================================
7157 00:40:32.397563 Gating Mode config
7158 00:40:32.404058 ==============================================================
7159 00:40:32.407520 Config description:
7160 00:40:32.417413 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7161 00:40:32.423711 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7162 00:40:32.427461 SELPH_MODE 0: By rank 1: By Phase
7163 00:40:32.433450 ==============================================================
7164 00:40:32.437068 GAT_TRACK_EN = 1
7165 00:40:32.440139 RX_GATING_MODE = 2
7166 00:40:32.443189 RX_GATING_TRACK_MODE = 2
7167 00:40:32.446520 SELPH_MODE = 1
7168 00:40:32.447083 PICG_EARLY_EN = 1
7169 00:40:32.449714 VALID_LAT_VALUE = 1
7170 00:40:32.456582 ==============================================================
7171 00:40:32.459372 Enter into Gating configuration >>>>
7172 00:40:32.463579 Exit from Gating configuration <<<<
7173 00:40:32.466383 Enter into DVFS_PRE_config >>>>>
7174 00:40:32.476462 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7175 00:40:32.479719 Exit from DVFS_PRE_config <<<<<
7176 00:40:32.482781 Enter into PICG configuration >>>>
7177 00:40:32.486149 Exit from PICG configuration <<<<
7178 00:40:32.489325 [RX_INPUT] configuration >>>>>
7179 00:40:32.492795 [RX_INPUT] configuration <<<<<
7180 00:40:32.499690 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7181 00:40:32.502834 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7182 00:40:32.510046 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7183 00:40:32.516238 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7184 00:40:32.522634 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7185 00:40:32.529055 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7186 00:40:32.532047 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7187 00:40:32.535196 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7188 00:40:32.538330 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7189 00:40:32.545240 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7190 00:40:32.548427 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7191 00:40:32.551962 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7192 00:40:32.555203 ===================================
7193 00:40:32.558582 LPDDR4 DRAM CONFIGURATION
7194 00:40:32.561385 ===================================
7195 00:40:32.565001 EX_ROW_EN[0] = 0x0
7196 00:40:32.565496 EX_ROW_EN[1] = 0x0
7197 00:40:32.568042 LP4Y_EN = 0x0
7198 00:40:32.568647 WORK_FSP = 0x1
7199 00:40:32.571766 WL = 0x5
7200 00:40:32.572272 RL = 0x5
7201 00:40:32.574522 BL = 0x2
7202 00:40:32.574933 RPST = 0x0
7203 00:40:32.577944 RD_PRE = 0x0
7204 00:40:32.578357 WR_PRE = 0x1
7205 00:40:32.581216 WR_PST = 0x1
7206 00:40:32.581742 DBI_WR = 0x0
7207 00:40:32.584704 DBI_RD = 0x0
7208 00:40:32.585116 OTF = 0x1
7209 00:40:32.588089 ===================================
7210 00:40:32.595030 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7211 00:40:32.597988 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7212 00:40:32.600858 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7213 00:40:32.604246 ===================================
7214 00:40:32.607755 LPDDR4 DRAM CONFIGURATION
7215 00:40:32.610792 ===================================
7216 00:40:32.614333 EX_ROW_EN[0] = 0x10
7217 00:40:32.614762 EX_ROW_EN[1] = 0x0
7218 00:40:32.617668 LP4Y_EN = 0x0
7219 00:40:32.618221 WORK_FSP = 0x1
7220 00:40:32.621072 WL = 0x5
7221 00:40:32.621696 RL = 0x5
7222 00:40:32.624010 BL = 0x2
7223 00:40:32.624445 RPST = 0x0
7224 00:40:32.627512 RD_PRE = 0x0
7225 00:40:32.628025 WR_PRE = 0x1
7226 00:40:32.631129 WR_PST = 0x1
7227 00:40:32.631644 DBI_WR = 0x0
7228 00:40:32.634244 DBI_RD = 0x0
7229 00:40:32.634653 OTF = 0x1
7230 00:40:32.637758 ===================================
7231 00:40:32.644383 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7232 00:40:32.644891 ==
7233 00:40:32.647434 Dram Type= 6, Freq= 0, CH_0, rank 0
7234 00:40:32.653811 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7235 00:40:32.654227 ==
7236 00:40:32.654558 [Duty_Offset_Calibration]
7237 00:40:32.657074 B0:2 B1:0 CA:4
7238 00:40:32.657568
7239 00:40:32.660681 [DutyScan_Calibration_Flow] k_type=0
7240 00:40:32.668927
7241 00:40:32.669416 ==CLK 0==
7242 00:40:32.672348 Final CLK duty delay cell = -4
7243 00:40:32.675887 [-4] MAX Duty = 5031%(X100), DQS PI = 30
7244 00:40:32.679254 [-4] MIN Duty = 4844%(X100), DQS PI = 0
7245 00:40:32.682451 [-4] AVG Duty = 4937%(X100)
7246 00:40:32.682862
7247 00:40:32.685634 CH0 CLK Duty spec in!! Max-Min= 187%
7248 00:40:32.689305 [DutyScan_Calibration_Flow] ====Done====
7249 00:40:32.689715
7250 00:40:32.692255 [DutyScan_Calibration_Flow] k_type=1
7251 00:40:32.710030
7252 00:40:32.710565 ==DQS 0 ==
7253 00:40:32.713007 Final DQS duty delay cell = 0
7254 00:40:32.716433 [0] MAX Duty = 5218%(X100), DQS PI = 38
7255 00:40:32.719706 [0] MIN Duty = 5093%(X100), DQS PI = 0
7256 00:40:32.720222 [0] AVG Duty = 5155%(X100)
7257 00:40:32.722811
7258 00:40:32.723264 ==DQS 1 ==
7259 00:40:32.725915 Final DQS duty delay cell = 0
7260 00:40:32.729692 [0] MAX Duty = 5156%(X100), DQS PI = 2
7261 00:40:32.732941 [0] MIN Duty = 4969%(X100), DQS PI = 10
7262 00:40:32.733384 [0] AVG Duty = 5062%(X100)
7263 00:40:32.736201
7264 00:40:32.739615 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7265 00:40:32.740029
7266 00:40:32.742376 CH0 DQS 1 Duty spec in!! Max-Min= 187%
7267 00:40:32.745956 [DutyScan_Calibration_Flow] ====Done====
7268 00:40:32.746472
7269 00:40:32.749144 [DutyScan_Calibration_Flow] k_type=3
7270 00:40:32.766733
7271 00:40:32.767282 ==DQM 0 ==
7272 00:40:32.770086 Final DQM duty delay cell = 0
7273 00:40:32.773190 [0] MAX Duty = 5124%(X100), DQS PI = 22
7274 00:40:32.776372 [0] MIN Duty = 4844%(X100), DQS PI = 54
7275 00:40:32.779719 [0] AVG Duty = 4984%(X100)
7276 00:40:32.780280
7277 00:40:32.780645 ==DQM 1 ==
7278 00:40:32.783499 Final DQM duty delay cell = 0
7279 00:40:32.786069 [0] MAX Duty = 4969%(X100), DQS PI = 0
7280 00:40:32.789878 [0] MIN Duty = 4844%(X100), DQS PI = 12
7281 00:40:32.792970 [0] AVG Duty = 4906%(X100)
7282 00:40:32.793657
7283 00:40:32.796327 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7284 00:40:32.796880
7285 00:40:32.799456 CH0 DQM 1 Duty spec in!! Max-Min= 125%
7286 00:40:32.802779 [DutyScan_Calibration_Flow] ====Done====
7287 00:40:32.803232
7288 00:40:32.806150 [DutyScan_Calibration_Flow] k_type=2
7289 00:40:32.823932
7290 00:40:32.824499 ==DQ 0 ==
7291 00:40:32.827067 Final DQ duty delay cell = 0
7292 00:40:32.830445 [0] MAX Duty = 5156%(X100), DQS PI = 28
7293 00:40:32.833640 [0] MIN Duty = 4938%(X100), DQS PI = 12
7294 00:40:32.834095 [0] AVG Duty = 5047%(X100)
7295 00:40:32.837199
7296 00:40:32.837751 ==DQ 1 ==
7297 00:40:32.840345 Final DQ duty delay cell = 0
7298 00:40:32.843626 [0] MAX Duty = 5187%(X100), DQS PI = 2
7299 00:40:32.846909 [0] MIN Duty = 4938%(X100), DQS PI = 12
7300 00:40:32.847364 [0] AVG Duty = 5062%(X100)
7301 00:40:32.847726
7302 00:40:32.850491 CH0 DQ 0 Duty spec in!! Max-Min= 218%
7303 00:40:32.853368
7304 00:40:32.857336 CH0 DQ 1 Duty spec in!! Max-Min= 249%
7305 00:40:32.860490 [DutyScan_Calibration_Flow] ====Done====
7306 00:40:32.861034 ==
7307 00:40:32.863120 Dram Type= 6, Freq= 0, CH_1, rank 0
7308 00:40:32.866995 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7309 00:40:32.867533 ==
7310 00:40:32.869867 [Duty_Offset_Calibration]
7311 00:40:32.870281 B0:0 B1:-1 CA:3
7312 00:40:32.870606
7313 00:40:32.873045 [DutyScan_Calibration_Flow] k_type=0
7314 00:40:32.884029
7315 00:40:32.884583 ==CLK 0==
7316 00:40:32.887335 Final CLK duty delay cell = 0
7317 00:40:32.890356 [0] MAX Duty = 5187%(X100), DQS PI = 26
7318 00:40:32.893688 [0] MIN Duty = 5000%(X100), DQS PI = 54
7319 00:40:32.896779 [0] AVG Duty = 5093%(X100)
7320 00:40:32.897189
7321 00:40:32.900399 CH1 CLK Duty spec in!! Max-Min= 187%
7322 00:40:32.904431 [DutyScan_Calibration_Flow] ====Done====
7323 00:40:32.904892
7324 00:40:32.906812 [DutyScan_Calibration_Flow] k_type=1
7325 00:40:32.923113
7326 00:40:32.923673 ==DQS 0 ==
7327 00:40:32.925810 Final DQS duty delay cell = 0
7328 00:40:32.929431 [0] MAX Duty = 5218%(X100), DQS PI = 30
7329 00:40:32.933051 [0] MIN Duty = 4907%(X100), DQS PI = 40
7330 00:40:32.936184 [0] AVG Duty = 5062%(X100)
7331 00:40:32.936601
7332 00:40:32.936924 ==DQS 1 ==
7333 00:40:32.939191 Final DQS duty delay cell = -4
7334 00:40:32.943192 [-4] MAX Duty = 5000%(X100), DQS PI = 28
7335 00:40:32.945890 [-4] MIN Duty = 4844%(X100), DQS PI = 0
7336 00:40:32.949325 [-4] AVG Duty = 4922%(X100)
7337 00:40:32.949735
7338 00:40:32.952514 CH1 DQS 0 Duty spec in!! Max-Min= 311%
7339 00:40:32.952921
7340 00:40:32.955499 CH1 DQS 1 Duty spec in!! Max-Min= 156%
7341 00:40:32.960306 [DutyScan_Calibration_Flow] ====Done====
7342 00:40:32.960915
7343 00:40:32.963022 [DutyScan_Calibration_Flow] k_type=3
7344 00:40:32.980361
7345 00:40:32.980919 ==DQM 0 ==
7346 00:40:32.983772 Final DQM duty delay cell = 0
7347 00:40:32.986508 [0] MAX Duty = 5031%(X100), DQS PI = 28
7348 00:40:32.989621 [0] MIN Duty = 4782%(X100), DQS PI = 40
7349 00:40:32.993395 [0] AVG Duty = 4906%(X100)
7350 00:40:32.993869
7351 00:40:32.994272 ==DQM 1 ==
7352 00:40:32.996376 Final DQM duty delay cell = 0
7353 00:40:32.999941 [0] MAX Duty = 4969%(X100), DQS PI = 30
7354 00:40:33.002888 [0] MIN Duty = 4844%(X100), DQS PI = 0
7355 00:40:33.006316 [0] AVG Duty = 4906%(X100)
7356 00:40:33.006819
7357 00:40:33.009407 CH1 DQM 0 Duty spec in!! Max-Min= 249%
7358 00:40:33.009861
7359 00:40:33.013486 CH1 DQM 1 Duty spec in!! Max-Min= 125%
7360 00:40:33.016477 [DutyScan_Calibration_Flow] ====Done====
7361 00:40:33.016980
7362 00:40:33.019743 [DutyScan_Calibration_Flow] k_type=2
7363 00:40:33.036011
7364 00:40:33.036575 ==DQ 0 ==
7365 00:40:33.039478 Final DQ duty delay cell = -4
7366 00:40:33.042991 [-4] MAX Duty = 4938%(X100), DQS PI = 8
7367 00:40:33.045725 [-4] MIN Duty = 4813%(X100), DQS PI = 36
7368 00:40:33.049065 [-4] AVG Duty = 4875%(X100)
7369 00:40:33.049610
7370 00:40:33.049975 ==DQ 1 ==
7371 00:40:33.052328 Final DQ duty delay cell = 0
7372 00:40:33.055817 [0] MAX Duty = 5031%(X100), DQS PI = 30
7373 00:40:33.058988 [0] MIN Duty = 4844%(X100), DQS PI = 60
7374 00:40:33.062085 [0] AVG Duty = 4937%(X100)
7375 00:40:33.062540
7376 00:40:33.065627 CH1 DQ 0 Duty spec in!! Max-Min= 125%
7377 00:40:33.066188
7378 00:40:33.069606 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7379 00:40:33.072200 [DutyScan_Calibration_Flow] ====Done====
7380 00:40:33.075273 nWR fixed to 30
7381 00:40:33.078993 [ModeRegInit_LP4] CH0 RK0
7382 00:40:33.079448 [ModeRegInit_LP4] CH0 RK1
7383 00:40:33.082025 [ModeRegInit_LP4] CH1 RK0
7384 00:40:33.085251 [ModeRegInit_LP4] CH1 RK1
7385 00:40:33.085866 match AC timing 5
7386 00:40:33.092412 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7387 00:40:33.095626 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7388 00:40:33.098635 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7389 00:40:33.105562 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7390 00:40:33.108198 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7391 00:40:33.111566 [MiockJmeterHQA]
7392 00:40:33.111974
7393 00:40:33.115303 [DramcMiockJmeter] u1RxGatingPI = 0
7394 00:40:33.115818 0 : 4255, 4029
7395 00:40:33.116154 4 : 4365, 4140
7396 00:40:33.118517 8 : 4257, 4029
7397 00:40:33.118930 12 : 4253, 4026
7398 00:40:33.121729 16 : 4255, 4029
7399 00:40:33.122145 20 : 4253, 4026
7400 00:40:33.125044 24 : 4363, 4138
7401 00:40:33.125510 28 : 4363, 4138
7402 00:40:33.125844 32 : 4253, 4026
7403 00:40:33.128198 36 : 4252, 4027
7404 00:40:33.128717 40 : 4253, 4027
7405 00:40:33.131486 44 : 4252, 4027
7406 00:40:33.132003 48 : 4255, 4029
7407 00:40:33.134681 52 : 4363, 4138
7408 00:40:33.135098 56 : 4250, 4027
7409 00:40:33.138371 60 : 4250, 4027
7410 00:40:33.138787 64 : 4250, 4026
7411 00:40:33.139116 68 : 4253, 4029
7412 00:40:33.141946 72 : 4250, 4027
7413 00:40:33.142465 76 : 4361, 4138
7414 00:40:33.144721 80 : 4360, 4138
7415 00:40:33.145240 84 : 4250, 4027
7416 00:40:33.148351 88 : 4250, 4027
7417 00:40:33.148878 92 : 4250, 4027
7418 00:40:33.151442 96 : 4250, 2759
7419 00:40:33.151860 100 : 4252, 0
7420 00:40:33.152192 104 : 4250, 0
7421 00:40:33.154797 108 : 4250, 0
7422 00:40:33.155314 112 : 4253, 0
7423 00:40:33.158020 116 : 4250, 0
7424 00:40:33.158542 120 : 4361, 0
7425 00:40:33.159048 124 : 4250, 0
7426 00:40:33.161243 128 : 4250, 0
7427 00:40:33.161803 132 : 4250, 0
7428 00:40:33.164209 136 : 4360, 0
7429 00:40:33.164660 140 : 4361, 0
7430 00:40:33.165020 144 : 4250, 0
7431 00:40:33.167606 148 : 4250, 0
7432 00:40:33.168034 152 : 4252, 0
7433 00:40:33.168365 156 : 4361, 0
7434 00:40:33.170981 160 : 4361, 0
7435 00:40:33.171426 164 : 4363, 0
7436 00:40:33.174626 168 : 4250, 0
7437 00:40:33.175045 172 : 4250, 0
7438 00:40:33.175382 176 : 4250, 0
7439 00:40:33.177451 180 : 4250, 0
7440 00:40:33.177878 184 : 4250, 0
7441 00:40:33.180675 188 : 4250, 0
7442 00:40:33.181104 192 : 4363, 0
7443 00:40:33.181486 196 : 4250, 0
7444 00:40:33.184213 200 : 4250, 0
7445 00:40:33.184631 204 : 4252, 0
7446 00:40:33.187505 208 : 4361, 0
7447 00:40:33.187922 212 : 4361, 0
7448 00:40:33.188256 216 : 4363, 0
7449 00:40:33.191031 220 : 4250, 889
7450 00:40:33.191467 224 : 4250, 4014
7451 00:40:33.193995 228 : 4361, 4137
7452 00:40:33.194422 232 : 4250, 4027
7453 00:40:33.197291 236 : 4250, 4027
7454 00:40:33.197721 240 : 4363, 4140
7455 00:40:33.200903 244 : 4250, 4027
7456 00:40:33.201372 248 : 4250, 4027
7457 00:40:33.203948 252 : 4252, 4027
7458 00:40:33.204372 256 : 4252, 4029
7459 00:40:33.207081 260 : 4250, 4027
7460 00:40:33.207522 264 : 4250, 4027
7461 00:40:33.207963 268 : 4361, 4138
7462 00:40:33.210867 272 : 4250, 4027
7463 00:40:33.211328 276 : 4250, 4027
7464 00:40:33.213968 280 : 4361, 4137
7465 00:40:33.214395 284 : 4250, 4027
7466 00:40:33.217622 288 : 4250, 4027
7467 00:40:33.218046 292 : 4363, 4140
7468 00:40:33.220902 296 : 4250, 4027
7469 00:40:33.221572 300 : 4250, 4027
7470 00:40:33.223952 304 : 4250, 4027
7471 00:40:33.224380 308 : 4252, 4029
7472 00:40:33.227353 312 : 4250, 4027
7473 00:40:33.227907 316 : 4250, 4027
7474 00:40:33.230557 320 : 4361, 4137
7475 00:40:33.231079 324 : 4250, 4027
7476 00:40:33.233435 328 : 4250, 4027
7477 00:40:33.233854 332 : 4361, 3934
7478 00:40:33.234185 336 : 4250, 1343
7479 00:40:33.236954
7480 00:40:33.237400 MIOCK jitter meter ch=0
7481 00:40:33.237731
7482 00:40:33.240124 1T = (336-100) = 236 dly cells
7483 00:40:33.247413 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7484 00:40:33.247930 ==
7485 00:40:33.249938 Dram Type= 6, Freq= 0, CH_0, rank 0
7486 00:40:33.253508 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7487 00:40:33.254019 ==
7488 00:40:33.260497 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7489 00:40:33.263203 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7490 00:40:33.266718 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7491 00:40:33.273295 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7492 00:40:33.282816 [CA 0] Center 43 (13~74) winsize 62
7493 00:40:33.286146 [CA 1] Center 42 (12~73) winsize 62
7494 00:40:33.289514 [CA 2] Center 37 (8~67) winsize 60
7495 00:40:33.292606 [CA 3] Center 37 (7~67) winsize 61
7496 00:40:33.295913 [CA 4] Center 36 (6~66) winsize 61
7497 00:40:33.299378 [CA 5] Center 35 (5~66) winsize 62
7498 00:40:33.299835
7499 00:40:33.302715 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7500 00:40:33.303274
7501 00:40:33.305776 [CATrainingPosCal] consider 1 rank data
7502 00:40:33.308896 u2DelayCellTimex100 = 275/100 ps
7503 00:40:33.315616 CA0 delay=43 (13~74),Diff = 8 PI (28 cell)
7504 00:40:33.319748 CA1 delay=42 (12~73),Diff = 7 PI (24 cell)
7505 00:40:33.321932 CA2 delay=37 (8~67),Diff = 2 PI (7 cell)
7506 00:40:33.325504 CA3 delay=37 (7~67),Diff = 2 PI (7 cell)
7507 00:40:33.328595 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7508 00:40:33.332179 CA5 delay=35 (5~66),Diff = 0 PI (0 cell)
7509 00:40:33.332751
7510 00:40:33.335475 CA PerBit enable=1, Macro0, CA PI delay=35
7511 00:40:33.336079
7512 00:40:33.338699 [CBTSetCACLKResult] CA Dly = 35
7513 00:40:33.341835 CS Dly: 10 (0~41)
7514 00:40:33.345428 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7515 00:40:33.348537 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7516 00:40:33.349025 ==
7517 00:40:33.352094 Dram Type= 6, Freq= 0, CH_0, rank 1
7518 00:40:33.358832 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7519 00:40:33.359389 ==
7520 00:40:33.362264 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7521 00:40:33.368039 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7522 00:40:33.371955 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7523 00:40:33.377900 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7524 00:40:33.386480 [CA 0] Center 43 (13~74) winsize 62
7525 00:40:33.389380 [CA 1] Center 43 (13~73) winsize 61
7526 00:40:33.392409 [CA 2] Center 38 (9~68) winsize 60
7527 00:40:33.396110 [CA 3] Center 38 (9~68) winsize 60
7528 00:40:33.399647 [CA 4] Center 36 (6~66) winsize 61
7529 00:40:33.402821 [CA 5] Center 36 (6~66) winsize 61
7530 00:40:33.403343
7531 00:40:33.406195 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7532 00:40:33.406615
7533 00:40:33.409912 [CATrainingPosCal] consider 2 rank data
7534 00:40:33.412515 u2DelayCellTimex100 = 275/100 ps
7535 00:40:33.419124 CA0 delay=43 (13~74),Diff = 7 PI (24 cell)
7536 00:40:33.422316 CA1 delay=43 (13~73),Diff = 7 PI (24 cell)
7537 00:40:33.425710 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
7538 00:40:33.428923 CA3 delay=38 (9~67),Diff = 2 PI (7 cell)
7539 00:40:33.432315 CA4 delay=36 (6~66),Diff = 0 PI (0 cell)
7540 00:40:33.435971 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7541 00:40:33.436522
7542 00:40:33.439129 CA PerBit enable=1, Macro0, CA PI delay=36
7543 00:40:33.439561
7544 00:40:33.441823 [CBTSetCACLKResult] CA Dly = 36
7545 00:40:33.445608 CS Dly: 11 (0~44)
7546 00:40:33.448748 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7547 00:40:33.452191 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7548 00:40:33.452724
7549 00:40:33.455521 ----->DramcWriteLeveling(PI) begin...
7550 00:40:33.456071 ==
7551 00:40:33.458619 Dram Type= 6, Freq= 0, CH_0, rank 0
7552 00:40:33.464942 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7553 00:40:33.465492 ==
7554 00:40:33.468800 Write leveling (Byte 0): 35 => 35
7555 00:40:33.472236 Write leveling (Byte 1): 26 => 26
7556 00:40:33.472781 DramcWriteLeveling(PI) end<-----
7557 00:40:33.475099
7558 00:40:33.475623 ==
7559 00:40:33.478036 Dram Type= 6, Freq= 0, CH_0, rank 0
7560 00:40:33.481439 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7561 00:40:33.481863 ==
7562 00:40:33.485705 [Gating] SW mode calibration
7563 00:40:33.491677 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7564 00:40:33.497857 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7565 00:40:33.501222 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7566 00:40:33.505246 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7567 00:40:33.508388 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7568 00:40:33.514543 1 4 12 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
7569 00:40:33.518208 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7570 00:40:33.521828 1 4 20 | B1->B0 | 2e2e 3434 | 0 1 | (0 0) (1 1)
7571 00:40:33.528777 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7572 00:40:33.531722 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7573 00:40:33.534891 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7574 00:40:33.541173 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7575 00:40:33.544348 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7576 00:40:33.547570 1 5 12 | B1->B0 | 3434 2929 | 1 1 | (1 1) (1 0)
7577 00:40:33.554680 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7578 00:40:33.557651 1 5 20 | B1->B0 | 2c2c 2323 | 0 0 | (0 1) (0 0)
7579 00:40:33.561010 1 5 24 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
7580 00:40:33.567828 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7581 00:40:33.570584 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7582 00:40:33.573936 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7583 00:40:33.580319 1 6 8 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
7584 00:40:33.584042 1 6 12 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
7585 00:40:33.586960 1 6 16 | B1->B0 | 2626 4646 | 0 0 | (0 0) (0 0)
7586 00:40:33.593726 1 6 20 | B1->B0 | 3c3c 4646 | 1 0 | (0 0) (0 0)
7587 00:40:33.597004 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7588 00:40:33.599997 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7589 00:40:33.606828 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7590 00:40:33.609907 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7591 00:40:33.613483 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7592 00:40:33.620089 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7593 00:40:33.623050 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7594 00:40:33.626910 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7595 00:40:33.633187 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7596 00:40:33.636320 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7597 00:40:33.639685 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7598 00:40:33.646122 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7599 00:40:33.649500 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7600 00:40:33.652751 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7601 00:40:33.659830 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7602 00:40:33.662555 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7603 00:40:33.665889 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7604 00:40:33.672880 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7605 00:40:33.675817 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7606 00:40:33.679280 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7607 00:40:33.686338 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7608 00:40:33.689610 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7609 00:40:33.692621 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7610 00:40:33.696246 Total UI for P1: 0, mck2ui 16
7611 00:40:33.699250 best dqsien dly found for B0: ( 1, 9, 10)
7612 00:40:33.705975 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7613 00:40:33.708845 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7614 00:40:33.712193 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7615 00:40:33.715980 Total UI for P1: 0, mck2ui 16
7616 00:40:33.719272 best dqsien dly found for B1: ( 1, 9, 22)
7617 00:40:33.722197 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7618 00:40:33.725759 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7619 00:40:33.729045
7620 00:40:33.732702 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7621 00:40:33.735251 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7622 00:40:33.738527 [Gating] SW calibration Done
7623 00:40:33.738762 ==
7624 00:40:33.742260 Dram Type= 6, Freq= 0, CH_0, rank 0
7625 00:40:33.744885 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7626 00:40:33.745075 ==
7627 00:40:33.748758 RX Vref Scan: 0
7628 00:40:33.748916
7629 00:40:33.749074 RX Vref 0 -> 0, step: 1
7630 00:40:33.749273
7631 00:40:33.751613 RX Delay 0 -> 252, step: 8
7632 00:40:33.754922 iDelay=192, Bit 0, Center 131 (80 ~ 183) 104
7633 00:40:33.761645 iDelay=192, Bit 1, Center 135 (80 ~ 191) 112
7634 00:40:33.765003 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7635 00:40:33.768683 iDelay=192, Bit 3, Center 127 (72 ~ 183) 112
7636 00:40:33.771302 iDelay=192, Bit 4, Center 135 (80 ~ 191) 112
7637 00:40:33.774540 iDelay=192, Bit 5, Center 119 (64 ~ 175) 112
7638 00:40:33.780997 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
7639 00:40:33.784282 iDelay=192, Bit 7, Center 139 (88 ~ 191) 104
7640 00:40:33.788009 iDelay=192, Bit 8, Center 119 (64 ~ 175) 112
7641 00:40:33.790808 iDelay=192, Bit 9, Center 111 (56 ~ 167) 112
7642 00:40:33.794624 iDelay=192, Bit 10, Center 127 (80 ~ 175) 96
7643 00:40:33.801199 iDelay=192, Bit 11, Center 123 (72 ~ 175) 104
7644 00:40:33.804168 iDelay=192, Bit 12, Center 135 (80 ~ 191) 112
7645 00:40:33.807391 iDelay=192, Bit 13, Center 131 (80 ~ 183) 104
7646 00:40:33.810676 iDelay=192, Bit 14, Center 135 (80 ~ 191) 112
7647 00:40:33.817003 iDelay=192, Bit 15, Center 135 (80 ~ 191) 112
7648 00:40:33.817095 ==
7649 00:40:33.820382 Dram Type= 6, Freq= 0, CH_0, rank 0
7650 00:40:33.823907 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7651 00:40:33.823994 ==
7652 00:40:33.824080 DQS Delay:
7653 00:40:33.827028 DQS0 = 0, DQS1 = 0
7654 00:40:33.827114 DQM Delay:
7655 00:40:33.830579 DQM0 = 131, DQM1 = 127
7656 00:40:33.830664 DQ Delay:
7657 00:40:33.833386 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
7658 00:40:33.837394 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =139
7659 00:40:33.840150 DQ8 =119, DQ9 =111, DQ10 =127, DQ11 =123
7660 00:40:33.843405 DQ12 =135, DQ13 =131, DQ14 =135, DQ15 =135
7661 00:40:33.843491
7662 00:40:33.846576
7663 00:40:33.846660 ==
7664 00:40:33.850274 Dram Type= 6, Freq= 0, CH_0, rank 0
7665 00:40:33.853666 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7666 00:40:33.853751 ==
7667 00:40:33.853852
7668 00:40:33.853951
7669 00:40:33.857120 TX Vref Scan disable
7670 00:40:33.857294 == TX Byte 0 ==
7671 00:40:33.863298 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7672 00:40:33.866868 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7673 00:40:33.866953 == TX Byte 1 ==
7674 00:40:33.873529 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7675 00:40:33.876648 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7676 00:40:33.876809 ==
7677 00:40:33.879889 Dram Type= 6, Freq= 0, CH_0, rank 0
7678 00:40:33.883239 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7679 00:40:33.883360 ==
7680 00:40:33.897662
7681 00:40:33.901069 TX Vref early break, caculate TX vref
7682 00:40:33.904219 TX Vref=16, minBit 1, minWin=22, winSum=366
7683 00:40:33.907501 TX Vref=18, minBit 6, minWin=22, winSum=379
7684 00:40:33.910756 TX Vref=20, minBit 1, minWin=23, winSum=389
7685 00:40:33.914112 TX Vref=22, minBit 4, minWin=24, winSum=398
7686 00:40:33.917326 TX Vref=24, minBit 7, minWin=24, winSum=410
7687 00:40:33.924117 TX Vref=26, minBit 1, minWin=25, winSum=417
7688 00:40:33.927550 TX Vref=28, minBit 1, minWin=25, winSum=420
7689 00:40:33.930381 TX Vref=30, minBit 2, minWin=25, winSum=416
7690 00:40:33.933685 TX Vref=32, minBit 1, minWin=24, winSum=409
7691 00:40:33.937526 TX Vref=34, minBit 2, minWin=23, winSum=394
7692 00:40:33.944080 [TxChooseVref] Worse bit 1, Min win 25, Win sum 420, Final Vref 28
7693 00:40:33.944513
7694 00:40:33.947412 Final TX Range 0 Vref 28
7695 00:40:33.947799
7696 00:40:33.948104 ==
7697 00:40:33.950498 Dram Type= 6, Freq= 0, CH_0, rank 0
7698 00:40:33.954038 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7699 00:40:33.954520 ==
7700 00:40:33.954865
7701 00:40:33.955172
7702 00:40:33.957360 TX Vref Scan disable
7703 00:40:33.963946 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7704 00:40:33.964378 == TX Byte 0 ==
7705 00:40:33.966684 u2DelayCellOfst[0]=14 cells (4 PI)
7706 00:40:33.970217 u2DelayCellOfst[1]=17 cells (5 PI)
7707 00:40:33.973307 u2DelayCellOfst[2]=14 cells (4 PI)
7708 00:40:33.977146 u2DelayCellOfst[3]=14 cells (4 PI)
7709 00:40:33.979995 u2DelayCellOfst[4]=10 cells (3 PI)
7710 00:40:33.983547 u2DelayCellOfst[5]=0 cells (0 PI)
7711 00:40:33.987433 u2DelayCellOfst[6]=17 cells (5 PI)
7712 00:40:33.990098 u2DelayCellOfst[7]=17 cells (5 PI)
7713 00:40:33.993538 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7714 00:40:33.996734 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7715 00:40:33.999451 == TX Byte 1 ==
7716 00:40:34.002832 u2DelayCellOfst[8]=0 cells (0 PI)
7717 00:40:34.006604 u2DelayCellOfst[9]=0 cells (0 PI)
7718 00:40:34.009373 u2DelayCellOfst[10]=3 cells (1 PI)
7719 00:40:34.012757 u2DelayCellOfst[11]=3 cells (1 PI)
7720 00:40:34.012929 u2DelayCellOfst[12]=7 cells (2 PI)
7721 00:40:34.015748 u2DelayCellOfst[13]=7 cells (2 PI)
7722 00:40:34.019148 u2DelayCellOfst[14]=14 cells (4 PI)
7723 00:40:34.022499 u2DelayCellOfst[15]=10 cells (3 PI)
7724 00:40:34.029123 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7725 00:40:34.032966 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7726 00:40:34.033050 DramC Write-DBI on
7727 00:40:34.033117 ==
7728 00:40:34.035840 Dram Type= 6, Freq= 0, CH_0, rank 0
7729 00:40:34.042328 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7730 00:40:34.042411 ==
7731 00:40:34.042476
7732 00:40:34.042536
7733 00:40:34.045991 TX Vref Scan disable
7734 00:40:34.046424 == TX Byte 0 ==
7735 00:40:34.052880 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
7736 00:40:34.053439 == TX Byte 1 ==
7737 00:40:34.056469 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
7738 00:40:34.059790 DramC Write-DBI off
7739 00:40:34.060211
7740 00:40:34.060545 [DATLAT]
7741 00:40:34.063373 Freq=1600, CH0 RK0
7742 00:40:34.063969
7743 00:40:34.064310 DATLAT Default: 0xf
7744 00:40:34.066433 0, 0xFFFF, sum = 0
7745 00:40:34.066860 1, 0xFFFF, sum = 0
7746 00:40:34.069097 2, 0xFFFF, sum = 0
7747 00:40:34.069550 3, 0xFFFF, sum = 0
7748 00:40:34.072717 4, 0xFFFF, sum = 0
7749 00:40:34.073144 5, 0xFFFF, sum = 0
7750 00:40:34.076138 6, 0xFFFF, sum = 0
7751 00:40:34.076703 7, 0xFFFF, sum = 0
7752 00:40:34.079290 8, 0xFFFF, sum = 0
7753 00:40:34.083004 9, 0xFFFF, sum = 0
7754 00:40:34.083432 10, 0xFFFF, sum = 0
7755 00:40:34.086272 11, 0xFFFF, sum = 0
7756 00:40:34.086701 12, 0xFFFF, sum = 0
7757 00:40:34.088921 13, 0xFFFF, sum = 0
7758 00:40:34.089375 14, 0x0, sum = 1
7759 00:40:34.092715 15, 0x0, sum = 2
7760 00:40:34.093140 16, 0x0, sum = 3
7761 00:40:34.095736 17, 0x0, sum = 4
7762 00:40:34.096163 best_step = 15
7763 00:40:34.096561
7764 00:40:34.096882 ==
7765 00:40:34.099154 Dram Type= 6, Freq= 0, CH_0, rank 0
7766 00:40:34.102347 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7767 00:40:34.102920 ==
7768 00:40:34.105405 RX Vref Scan: 1
7769 00:40:34.105826
7770 00:40:34.108925 Set Vref Range= 24 -> 127
7771 00:40:34.109384
7772 00:40:34.109720 RX Vref 24 -> 127, step: 1
7773 00:40:34.112198
7774 00:40:34.112614 RX Delay 11 -> 252, step: 4
7775 00:40:34.112946
7776 00:40:34.115897 Set Vref, RX VrefLevel [Byte0]: 24
7777 00:40:34.118681 [Byte1]: 24
7778 00:40:34.122486
7779 00:40:34.122905 Set Vref, RX VrefLevel [Byte0]: 25
7780 00:40:34.125734 [Byte1]: 25
7781 00:40:34.129814
7782 00:40:34.130235 Set Vref, RX VrefLevel [Byte0]: 26
7783 00:40:34.133370 [Byte1]: 26
7784 00:40:34.137519
7785 00:40:34.137938 Set Vref, RX VrefLevel [Byte0]: 27
7786 00:40:34.140965 [Byte1]: 27
7787 00:40:34.145145
7788 00:40:34.145625 Set Vref, RX VrefLevel [Byte0]: 28
7789 00:40:34.148556 [Byte1]: 28
7790 00:40:34.152465
7791 00:40:34.152764 Set Vref, RX VrefLevel [Byte0]: 29
7792 00:40:34.155999 [Byte1]: 29
7793 00:40:34.160391
7794 00:40:34.160573 Set Vref, RX VrefLevel [Byte0]: 30
7795 00:40:34.163317 [Byte1]: 30
7796 00:40:34.167570
7797 00:40:34.167722 Set Vref, RX VrefLevel [Byte0]: 31
7798 00:40:34.170942 [Byte1]: 31
7799 00:40:34.175906
7800 00:40:34.176020 Set Vref, RX VrefLevel [Byte0]: 32
7801 00:40:34.178758 [Byte1]: 32
7802 00:40:34.183204
7803 00:40:34.183306 Set Vref, RX VrefLevel [Byte0]: 33
7804 00:40:34.186027 [Byte1]: 33
7805 00:40:34.190566
7806 00:40:34.193936 Set Vref, RX VrefLevel [Byte0]: 34
7807 00:40:34.194019 [Byte1]: 34
7808 00:40:34.198490
7809 00:40:34.198571 Set Vref, RX VrefLevel [Byte0]: 35
7810 00:40:34.201750 [Byte1]: 35
7811 00:40:34.205946
7812 00:40:34.206028 Set Vref, RX VrefLevel [Byte0]: 36
7813 00:40:34.209117 [Byte1]: 36
7814 00:40:34.213457
7815 00:40:34.213605 Set Vref, RX VrefLevel [Byte0]: 37
7816 00:40:34.216856 [Byte1]: 37
7817 00:40:34.221114
7818 00:40:34.221320 Set Vref, RX VrefLevel [Byte0]: 38
7819 00:40:34.224673 [Byte1]: 38
7820 00:40:34.228941
7821 00:40:34.229102 Set Vref, RX VrefLevel [Byte0]: 39
7822 00:40:34.232096 [Byte1]: 39
7823 00:40:34.236381
7824 00:40:34.236555 Set Vref, RX VrefLevel [Byte0]: 40
7825 00:40:34.239853 [Byte1]: 40
7826 00:40:34.243791
7827 00:40:34.243944 Set Vref, RX VrefLevel [Byte0]: 41
7828 00:40:34.246980 [Byte1]: 41
7829 00:40:34.251993
7830 00:40:34.252506 Set Vref, RX VrefLevel [Byte0]: 42
7831 00:40:34.255080 [Byte1]: 42
7832 00:40:34.259611
7833 00:40:34.260027 Set Vref, RX VrefLevel [Byte0]: 43
7834 00:40:34.262960 [Byte1]: 43
7835 00:40:34.267275
7836 00:40:34.267691 Set Vref, RX VrefLevel [Byte0]: 44
7837 00:40:34.271324 [Byte1]: 44
7838 00:40:34.275010
7839 00:40:34.275428 Set Vref, RX VrefLevel [Byte0]: 45
7840 00:40:34.277886 [Byte1]: 45
7841 00:40:34.282367
7842 00:40:34.282850 Set Vref, RX VrefLevel [Byte0]: 46
7843 00:40:34.285637 [Byte1]: 46
7844 00:40:34.289519
7845 00:40:34.292868 Set Vref, RX VrefLevel [Byte0]: 47
7846 00:40:34.296291 [Byte1]: 47
7847 00:40:34.296712
7848 00:40:34.299473 Set Vref, RX VrefLevel [Byte0]: 48
7849 00:40:34.302804 [Byte1]: 48
7850 00:40:34.303229
7851 00:40:34.305992 Set Vref, RX VrefLevel [Byte0]: 49
7852 00:40:34.309155 [Byte1]: 49
7853 00:40:34.313292
7854 00:40:34.313780 Set Vref, RX VrefLevel [Byte0]: 50
7855 00:40:34.316247 [Byte1]: 50
7856 00:40:34.320671
7857 00:40:34.321086 Set Vref, RX VrefLevel [Byte0]: 51
7858 00:40:34.323597 [Byte1]: 51
7859 00:40:34.328295
7860 00:40:34.328709 Set Vref, RX VrefLevel [Byte0]: 52
7861 00:40:34.331277 [Byte1]: 52
7862 00:40:34.335718
7863 00:40:34.336299 Set Vref, RX VrefLevel [Byte0]: 53
7864 00:40:34.338574 [Byte1]: 53
7865 00:40:34.342899
7866 00:40:34.343494 Set Vref, RX VrefLevel [Byte0]: 54
7867 00:40:34.346499 [Byte1]: 54
7868 00:40:34.351333
7869 00:40:34.351869 Set Vref, RX VrefLevel [Byte0]: 55
7870 00:40:34.354457 [Byte1]: 55
7871 00:40:34.358454
7872 00:40:34.358954 Set Vref, RX VrefLevel [Byte0]: 56
7873 00:40:34.361831 [Byte1]: 56
7874 00:40:34.365901
7875 00:40:34.366337 Set Vref, RX VrefLevel [Byte0]: 57
7876 00:40:34.369556 [Byte1]: 57
7877 00:40:34.373573
7878 00:40:34.374000 Set Vref, RX VrefLevel [Byte0]: 58
7879 00:40:34.376935 [Byte1]: 58
7880 00:40:34.381495
7881 00:40:34.381924 Set Vref, RX VrefLevel [Byte0]: 59
7882 00:40:34.384604 [Byte1]: 59
7883 00:40:34.388965
7884 00:40:34.389517 Set Vref, RX VrefLevel [Byte0]: 60
7885 00:40:34.391953 [Byte1]: 60
7886 00:40:34.396425
7887 00:40:34.396870 Set Vref, RX VrefLevel [Byte0]: 61
7888 00:40:34.399550 [Byte1]: 61
7889 00:40:34.404522
7890 00:40:34.404965 Set Vref, RX VrefLevel [Byte0]: 62
7891 00:40:34.407436 [Byte1]: 62
7892 00:40:34.412185
7893 00:40:34.412703 Set Vref, RX VrefLevel [Byte0]: 63
7894 00:40:34.415339 [Byte1]: 63
7895 00:40:34.419027
7896 00:40:34.419457 Set Vref, RX VrefLevel [Byte0]: 64
7897 00:40:34.423552 [Byte1]: 64
7898 00:40:34.426815
7899 00:40:34.427243 Set Vref, RX VrefLevel [Byte0]: 65
7900 00:40:34.430037 [Byte1]: 65
7901 00:40:34.434873
7902 00:40:34.435413 Set Vref, RX VrefLevel [Byte0]: 66
7903 00:40:34.437788 [Byte1]: 66
7904 00:40:34.442672
7905 00:40:34.443234 Set Vref, RX VrefLevel [Byte0]: 67
7906 00:40:34.445745 [Byte1]: 67
7907 00:40:34.449836
7908 00:40:34.450257 Set Vref, RX VrefLevel [Byte0]: 68
7909 00:40:34.453395 [Byte1]: 68
7910 00:40:34.457805
7911 00:40:34.458328 Set Vref, RX VrefLevel [Byte0]: 69
7912 00:40:34.460956 [Byte1]: 69
7913 00:40:34.465447
7914 00:40:34.466006 Set Vref, RX VrefLevel [Byte0]: 70
7915 00:40:34.468545 [Byte1]: 70
7916 00:40:34.472738
7917 00:40:34.473359 Set Vref, RX VrefLevel [Byte0]: 71
7918 00:40:34.475834 [Byte1]: 71
7919 00:40:34.480604
7920 00:40:34.481136 Set Vref, RX VrefLevel [Byte0]: 72
7921 00:40:34.483249 [Byte1]: 72
7922 00:40:34.488147
7923 00:40:34.488776 Set Vref, RX VrefLevel [Byte0]: 73
7924 00:40:34.490916 [Byte1]: 73
7925 00:40:34.495416
7926 00:40:34.495863 Set Vref, RX VrefLevel [Byte0]: 74
7927 00:40:34.498978 [Byte1]: 74
7928 00:40:34.502961
7929 00:40:34.503439 Final RX Vref Byte 0 = 57 to rank0
7930 00:40:34.505984 Final RX Vref Byte 1 = 57 to rank0
7931 00:40:34.509440 Final RX Vref Byte 0 = 57 to rank1
7932 00:40:34.513348 Final RX Vref Byte 1 = 57 to rank1==
7933 00:40:34.516176 Dram Type= 6, Freq= 0, CH_0, rank 0
7934 00:40:34.522769 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7935 00:40:34.523308 ==
7936 00:40:34.523769 DQS Delay:
7937 00:40:34.526135 DQS0 = 0, DQS1 = 0
7938 00:40:34.526651 DQM Delay:
7939 00:40:34.527106 DQM0 = 128, DQM1 = 124
7940 00:40:34.529208 DQ Delay:
7941 00:40:34.532655 DQ0 =130, DQ1 =130, DQ2 =126, DQ3 =124
7942 00:40:34.536291 DQ4 =132, DQ5 =118, DQ6 =136, DQ7 =134
7943 00:40:34.539409 DQ8 =112, DQ9 =112, DQ10 =126, DQ11 =120
7944 00:40:34.542503 DQ12 =130, DQ13 =130, DQ14 =134, DQ15 =132
7945 00:40:34.542922
7946 00:40:34.543251
7947 00:40:34.543669
7948 00:40:34.546151 [DramC_TX_OE_Calibration] TA2
7949 00:40:34.549350 Original DQ_B0 (3 6) =30, OEN = 27
7950 00:40:34.552997 Original DQ_B1 (3 6) =30, OEN = 27
7951 00:40:34.556182 24, 0x0, End_B0=24 End_B1=24
7952 00:40:34.556719 25, 0x0, End_B0=25 End_B1=25
7953 00:40:34.559540 26, 0x0, End_B0=26 End_B1=26
7954 00:40:34.563180 27, 0x0, End_B0=27 End_B1=27
7955 00:40:34.566347 28, 0x0, End_B0=28 End_B1=28
7956 00:40:34.569107 29, 0x0, End_B0=29 End_B1=29
7957 00:40:34.569581 30, 0x0, End_B0=30 End_B1=30
7958 00:40:34.572969 31, 0x4141, End_B0=30 End_B1=30
7959 00:40:34.576227 Byte0 end_step=30 best_step=27
7960 00:40:34.579480 Byte1 end_step=30 best_step=27
7961 00:40:34.582770 Byte0 TX OE(2T, 0.5T) = (3, 3)
7962 00:40:34.585598 Byte1 TX OE(2T, 0.5T) = (3, 3)
7963 00:40:34.586019
7964 00:40:34.586352
7965 00:40:34.592446 [DQSOSCAuto] RK0, (LSB)MR18= 0x1714, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 398 ps
7966 00:40:34.595783 CH0 RK0: MR19=303, MR18=1714
7967 00:40:34.602158 CH0_RK0: MR19=0x303, MR18=0x1714, DQSOSC=398, MR23=63, INC=23, DEC=15
7968 00:40:34.602580
7969 00:40:34.605297 ----->DramcWriteLeveling(PI) begin...
7970 00:40:34.605788 ==
7971 00:40:34.608581 Dram Type= 6, Freq= 0, CH_0, rank 1
7972 00:40:34.612148 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7973 00:40:34.612633 ==
7974 00:40:34.616004 Write leveling (Byte 0): 35 => 35
7975 00:40:34.618375 Write leveling (Byte 1): 27 => 27
7976 00:40:34.621816 DramcWriteLeveling(PI) end<-----
7977 00:40:34.622248
7978 00:40:34.622687 ==
7979 00:40:34.625244 Dram Type= 6, Freq= 0, CH_0, rank 1
7980 00:40:34.629155 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7981 00:40:34.631694 ==
7982 00:40:34.632136 [Gating] SW mode calibration
7983 00:40:34.641403 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7984 00:40:34.644947 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7985 00:40:34.648396 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7986 00:40:34.655205 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7987 00:40:34.657912 1 4 8 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
7988 00:40:34.661862 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7989 00:40:34.668709 1 4 16 | B1->B0 | 2828 3434 | 0 1 | (0 0) (1 1)
7990 00:40:34.671279 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7991 00:40:34.674396 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7992 00:40:34.681492 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7993 00:40:34.684746 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7994 00:40:34.687829 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7995 00:40:34.694305 1 5 8 | B1->B0 | 3434 2e2e | 1 1 | (1 1) (1 0)
7996 00:40:34.697622 1 5 12 | B1->B0 | 3434 2626 | 1 0 | (1 1) (0 0)
7997 00:40:34.701155 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7998 00:40:34.707956 1 5 20 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
7999 00:40:34.710707 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8000 00:40:34.713867 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8001 00:40:34.720614 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8002 00:40:34.724056 1 6 4 | B1->B0 | 2323 2929 | 0 0 | (0 0) (1 1)
8003 00:40:34.727055 1 6 8 | B1->B0 | 2323 3636 | 0 1 | (0 0) (0 0)
8004 00:40:34.733590 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8005 00:40:34.737394 1 6 16 | B1->B0 | 3636 4646 | 0 0 | (0 0) (0 0)
8006 00:40:34.740203 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8007 00:40:34.747406 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8008 00:40:34.750682 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8009 00:40:34.753286 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8010 00:40:34.759806 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8011 00:40:34.763774 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8012 00:40:34.769896 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8013 00:40:34.773081 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8014 00:40:34.776646 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8015 00:40:34.782995 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8016 00:40:34.785961 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8017 00:40:34.790004 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8018 00:40:34.796000 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8019 00:40:34.799678 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8020 00:40:34.802612 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8021 00:40:34.809452 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8022 00:40:34.813814 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8023 00:40:34.816558 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8024 00:40:34.822741 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8025 00:40:34.825760 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8026 00:40:34.829034 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8027 00:40:34.835780 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8028 00:40:34.839032 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8029 00:40:34.842188 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8030 00:40:34.845746 Total UI for P1: 0, mck2ui 16
8031 00:40:34.849036 best dqsien dly found for B0: ( 1, 9, 10)
8032 00:40:34.852582 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8033 00:40:34.859055 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8034 00:40:34.862372 Total UI for P1: 0, mck2ui 16
8035 00:40:34.865586 best dqsien dly found for B1: ( 1, 9, 18)
8036 00:40:34.868588 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8037 00:40:34.872116 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8038 00:40:34.872726
8039 00:40:34.875556 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8040 00:40:34.878406 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8041 00:40:34.882102 [Gating] SW calibration Done
8042 00:40:34.882634 ==
8043 00:40:34.885152 Dram Type= 6, Freq= 0, CH_0, rank 1
8044 00:40:34.889004 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8045 00:40:34.889663 ==
8046 00:40:34.892821 RX Vref Scan: 0
8047 00:40:34.893548
8048 00:40:34.895805 RX Vref 0 -> 0, step: 1
8049 00:40:34.896255
8050 00:40:34.896689 RX Delay 0 -> 252, step: 8
8051 00:40:34.902259 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
8052 00:40:34.904942 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8053 00:40:34.908183 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
8054 00:40:34.911563 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8055 00:40:34.918283 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8056 00:40:34.921566 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8057 00:40:34.924420 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8058 00:40:34.928045 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8059 00:40:34.931412 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8060 00:40:34.937632 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8061 00:40:34.941235 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8062 00:40:34.944616 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8063 00:40:34.948048 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8064 00:40:34.950933 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8065 00:40:34.957370 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8066 00:40:34.961192 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8067 00:40:34.961805 ==
8068 00:40:34.964407 Dram Type= 6, Freq= 0, CH_0, rank 1
8069 00:40:34.967827 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8070 00:40:34.968380 ==
8071 00:40:34.971250 DQS Delay:
8072 00:40:34.971671 DQS0 = 0, DQS1 = 0
8073 00:40:34.972002 DQM Delay:
8074 00:40:34.974349 DQM0 = 131, DQM1 = 127
8075 00:40:34.974768 DQ Delay:
8076 00:40:34.977547 DQ0 =127, DQ1 =131, DQ2 =131, DQ3 =127
8077 00:40:34.980627 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =139
8078 00:40:34.987560 DQ8 =119, DQ9 =111, DQ10 =131, DQ11 =119
8079 00:40:34.990688 DQ12 =131, DQ13 =135, DQ14 =135, DQ15 =135
8080 00:40:34.991108
8081 00:40:34.991438
8082 00:40:34.991747 ==
8083 00:40:34.993579 Dram Type= 6, Freq= 0, CH_0, rank 1
8084 00:40:34.997254 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8085 00:40:34.997719 ==
8086 00:40:34.998051
8087 00:40:34.998359
8088 00:40:35.000515 TX Vref Scan disable
8089 00:40:35.003976 == TX Byte 0 ==
8090 00:40:35.007430 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8091 00:40:35.010446 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8092 00:40:35.014091 == TX Byte 1 ==
8093 00:40:35.016733 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8094 00:40:35.020153 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8095 00:40:35.020573 ==
8096 00:40:35.023421 Dram Type= 6, Freq= 0, CH_0, rank 1
8097 00:40:35.030080 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8098 00:40:35.030578 ==
8099 00:40:35.043642
8100 00:40:35.046414 TX Vref early break, caculate TX vref
8101 00:40:35.050383 TX Vref=16, minBit 2, minWin=23, winSum=383
8102 00:40:35.053420 TX Vref=18, minBit 2, minWin=24, winSum=391
8103 00:40:35.056402 TX Vref=20, minBit 0, minWin=24, winSum=398
8104 00:40:35.060101 TX Vref=22, minBit 8, minWin=24, winSum=406
8105 00:40:35.063350 TX Vref=24, minBit 1, minWin=25, winSum=413
8106 00:40:35.069854 TX Vref=26, minBit 4, minWin=25, winSum=420
8107 00:40:35.073323 TX Vref=28, minBit 3, minWin=25, winSum=421
8108 00:40:35.076468 TX Vref=30, minBit 0, minWin=25, winSum=416
8109 00:40:35.079731 TX Vref=32, minBit 1, minWin=24, winSum=408
8110 00:40:35.082739 TX Vref=34, minBit 1, minWin=24, winSum=402
8111 00:40:35.089585 TX Vref=36, minBit 1, minWin=23, winSum=391
8112 00:40:35.092665 [TxChooseVref] Worse bit 3, Min win 25, Win sum 421, Final Vref 28
8113 00:40:35.093184
8114 00:40:35.096141 Final TX Range 0 Vref 28
8115 00:40:35.096574
8116 00:40:35.096906 ==
8117 00:40:35.099250 Dram Type= 6, Freq= 0, CH_0, rank 1
8118 00:40:35.102613 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8119 00:40:35.103031 ==
8120 00:40:35.105972
8121 00:40:35.106389
8122 00:40:35.106721 TX Vref Scan disable
8123 00:40:35.112605 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8124 00:40:35.113028 == TX Byte 0 ==
8125 00:40:35.115944 u2DelayCellOfst[0]=10 cells (3 PI)
8126 00:40:35.119443 u2DelayCellOfst[1]=14 cells (4 PI)
8127 00:40:35.122849 u2DelayCellOfst[2]=7 cells (2 PI)
8128 00:40:35.125960 u2DelayCellOfst[3]=10 cells (3 PI)
8129 00:40:35.129360 u2DelayCellOfst[4]=7 cells (2 PI)
8130 00:40:35.132468 u2DelayCellOfst[5]=0 cells (0 PI)
8131 00:40:35.135849 u2DelayCellOfst[6]=14 cells (4 PI)
8132 00:40:35.138749 u2DelayCellOfst[7]=14 cells (4 PI)
8133 00:40:35.142166 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8134 00:40:35.145560 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8135 00:40:35.149418 == TX Byte 1 ==
8136 00:40:35.152704 u2DelayCellOfst[8]=0 cells (0 PI)
8137 00:40:35.155385 u2DelayCellOfst[9]=0 cells (0 PI)
8138 00:40:35.159029 u2DelayCellOfst[10]=3 cells (1 PI)
8139 00:40:35.162026 u2DelayCellOfst[11]=3 cells (1 PI)
8140 00:40:35.166000 u2DelayCellOfst[12]=10 cells (3 PI)
8141 00:40:35.169034 u2DelayCellOfst[13]=10 cells (3 PI)
8142 00:40:35.171952 u2DelayCellOfst[14]=14 cells (4 PI)
8143 00:40:35.172372 u2DelayCellOfst[15]=10 cells (3 PI)
8144 00:40:35.178561 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8145 00:40:35.181864 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8146 00:40:35.185247 DramC Write-DBI on
8147 00:40:35.185692 ==
8148 00:40:35.188572 Dram Type= 6, Freq= 0, CH_0, rank 1
8149 00:40:35.191994 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8150 00:40:35.192524 ==
8151 00:40:35.192861
8152 00:40:35.193169
8153 00:40:35.194691 TX Vref Scan disable
8154 00:40:35.198160 == TX Byte 0 ==
8155 00:40:35.201917 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
8156 00:40:35.202340 == TX Byte 1 ==
8157 00:40:35.208717 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8158 00:40:35.209142 DramC Write-DBI off
8159 00:40:35.209525
8160 00:40:35.209842 [DATLAT]
8161 00:40:35.211510 Freq=1600, CH0 RK1
8162 00:40:35.211929
8163 00:40:35.214835 DATLAT Default: 0xf
8164 00:40:35.215255 0, 0xFFFF, sum = 0
8165 00:40:35.217968 1, 0xFFFF, sum = 0
8166 00:40:35.218393 2, 0xFFFF, sum = 0
8167 00:40:35.221567 3, 0xFFFF, sum = 0
8168 00:40:35.222003 4, 0xFFFF, sum = 0
8169 00:40:35.224684 5, 0xFFFF, sum = 0
8170 00:40:35.225108 6, 0xFFFF, sum = 0
8171 00:40:35.227574 7, 0xFFFF, sum = 0
8172 00:40:35.227995 8, 0xFFFF, sum = 0
8173 00:40:35.231105 9, 0xFFFF, sum = 0
8174 00:40:35.231532 10, 0xFFFF, sum = 0
8175 00:40:35.234249 11, 0xFFFF, sum = 0
8176 00:40:35.234674 12, 0xFFFF, sum = 0
8177 00:40:35.237616 13, 0xFFFF, sum = 0
8178 00:40:35.238040 14, 0x0, sum = 1
8179 00:40:35.241110 15, 0x0, sum = 2
8180 00:40:35.241564 16, 0x0, sum = 3
8181 00:40:35.244908 17, 0x0, sum = 4
8182 00:40:35.245387 best_step = 15
8183 00:40:35.245912
8184 00:40:35.246419 ==
8185 00:40:35.247583 Dram Type= 6, Freq= 0, CH_0, rank 1
8186 00:40:35.253987 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8187 00:40:35.254457 ==
8188 00:40:35.254792 RX Vref Scan: 0
8189 00:40:35.255102
8190 00:40:35.257627 RX Vref 0 -> 0, step: 1
8191 00:40:35.258043
8192 00:40:35.261120 RX Delay 11 -> 252, step: 4
8193 00:40:35.264156 iDelay=187, Bit 0, Center 126 (75 ~ 178) 104
8194 00:40:35.267970 iDelay=187, Bit 1, Center 130 (79 ~ 182) 104
8195 00:40:35.271104 iDelay=187, Bit 2, Center 124 (75 ~ 174) 100
8196 00:40:35.277636 iDelay=187, Bit 3, Center 126 (75 ~ 178) 104
8197 00:40:35.280919 iDelay=187, Bit 4, Center 130 (83 ~ 178) 96
8198 00:40:35.284024 iDelay=187, Bit 5, Center 118 (63 ~ 174) 112
8199 00:40:35.287273 iDelay=187, Bit 6, Center 136 (87 ~ 186) 100
8200 00:40:35.290855 iDelay=187, Bit 7, Center 134 (83 ~ 186) 104
8201 00:40:35.297325 iDelay=187, Bit 8, Center 114 (63 ~ 166) 104
8202 00:40:35.300536 iDelay=187, Bit 9, Center 110 (59 ~ 162) 104
8203 00:40:35.303937 iDelay=187, Bit 10, Center 124 (71 ~ 178) 108
8204 00:40:35.307422 iDelay=187, Bit 11, Center 118 (67 ~ 170) 104
8205 00:40:35.313751 iDelay=187, Bit 12, Center 128 (75 ~ 182) 108
8206 00:40:35.317350 iDelay=187, Bit 13, Center 128 (79 ~ 178) 100
8207 00:40:35.320717 iDelay=187, Bit 14, Center 134 (83 ~ 186) 104
8208 00:40:35.323895 iDelay=187, Bit 15, Center 130 (79 ~ 182) 104
8209 00:40:35.324316 ==
8210 00:40:35.326964 Dram Type= 6, Freq= 0, CH_0, rank 1
8211 00:40:35.333582 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8212 00:40:35.334093 ==
8213 00:40:35.334644 DQS Delay:
8214 00:40:35.336692 DQS0 = 0, DQS1 = 0
8215 00:40:35.337109 DQM Delay:
8216 00:40:35.337503 DQM0 = 128, DQM1 = 123
8217 00:40:35.340514 DQ Delay:
8218 00:40:35.343670 DQ0 =126, DQ1 =130, DQ2 =124, DQ3 =126
8219 00:40:35.347349 DQ4 =130, DQ5 =118, DQ6 =136, DQ7 =134
8220 00:40:35.349997 DQ8 =114, DQ9 =110, DQ10 =124, DQ11 =118
8221 00:40:35.353624 DQ12 =128, DQ13 =128, DQ14 =134, DQ15 =130
8222 00:40:35.354043
8223 00:40:35.354369
8224 00:40:35.354672
8225 00:40:35.357205 [DramC_TX_OE_Calibration] TA2
8226 00:40:35.359922 Original DQ_B0 (3 6) =30, OEN = 27
8227 00:40:35.363191 Original DQ_B1 (3 6) =30, OEN = 27
8228 00:40:35.366697 24, 0x0, End_B0=24 End_B1=24
8229 00:40:35.367122 25, 0x0, End_B0=25 End_B1=25
8230 00:40:35.369744 26, 0x0, End_B0=26 End_B1=26
8231 00:40:35.373411 27, 0x0, End_B0=27 End_B1=27
8232 00:40:35.376465 28, 0x0, End_B0=28 End_B1=28
8233 00:40:35.379472 29, 0x0, End_B0=29 End_B1=29
8234 00:40:35.379899 30, 0x0, End_B0=30 End_B1=30
8235 00:40:35.383437 31, 0x4141, End_B0=30 End_B1=30
8236 00:40:35.386713 Byte0 end_step=30 best_step=27
8237 00:40:35.389394 Byte1 end_step=30 best_step=27
8238 00:40:35.393776 Byte0 TX OE(2T, 0.5T) = (3, 3)
8239 00:40:35.396196 Byte1 TX OE(2T, 0.5T) = (3, 3)
8240 00:40:35.396611
8241 00:40:35.396939
8242 00:40:35.402892 [DQSOSCAuto] RK1, (LSB)MR18= 0x1513, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 399 ps
8243 00:40:35.406146 CH0 RK1: MR19=303, MR18=1513
8244 00:40:35.413337 CH0_RK1: MR19=0x303, MR18=0x1513, DQSOSC=399, MR23=63, INC=23, DEC=15
8245 00:40:35.416142 [RxdqsGatingPostProcess] freq 1600
8246 00:40:35.422939 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8247 00:40:35.423591 best DQS0 dly(2T, 0.5T) = (1, 1)
8248 00:40:35.425998 best DQS1 dly(2T, 0.5T) = (1, 1)
8249 00:40:35.429481 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8250 00:40:35.432414 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8251 00:40:35.435530 best DQS0 dly(2T, 0.5T) = (1, 1)
8252 00:40:35.438728 best DQS1 dly(2T, 0.5T) = (1, 1)
8253 00:40:35.442569 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8254 00:40:35.445738 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8255 00:40:35.449028 Pre-setting of DQS Precalculation
8256 00:40:35.452748 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8257 00:40:35.453309 ==
8258 00:40:35.455948 Dram Type= 6, Freq= 0, CH_1, rank 0
8259 00:40:35.462493 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8260 00:40:35.462919 ==
8261 00:40:35.465880 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8262 00:40:35.471885 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8263 00:40:35.475409 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8264 00:40:35.481952 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8265 00:40:35.490145 [CA 0] Center 42 (12~72) winsize 61
8266 00:40:35.493310 [CA 1] Center 42 (12~72) winsize 61
8267 00:40:35.496567 [CA 2] Center 38 (9~68) winsize 60
8268 00:40:35.499617 [CA 3] Center 37 (8~66) winsize 59
8269 00:40:35.503646 [CA 4] Center 38 (8~68) winsize 61
8270 00:40:35.506141 [CA 5] Center 36 (7~66) winsize 60
8271 00:40:35.506561
8272 00:40:35.509468 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8273 00:40:35.509890
8274 00:40:35.516173 [CATrainingPosCal] consider 1 rank data
8275 00:40:35.516707 u2DelayCellTimex100 = 275/100 ps
8276 00:40:35.522816 CA0 delay=42 (12~72),Diff = 6 PI (21 cell)
8277 00:40:35.525816 CA1 delay=42 (12~72),Diff = 6 PI (21 cell)
8278 00:40:35.529219 CA2 delay=38 (9~68),Diff = 2 PI (7 cell)
8279 00:40:35.532590 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8280 00:40:35.535856 CA4 delay=38 (8~68),Diff = 2 PI (7 cell)
8281 00:40:35.539006 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8282 00:40:35.539430
8283 00:40:35.542879 CA PerBit enable=1, Macro0, CA PI delay=36
8284 00:40:35.543302
8285 00:40:35.545892 [CBTSetCACLKResult] CA Dly = 36
8286 00:40:35.548958 CS Dly: 8 (0~39)
8287 00:40:35.552173 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8288 00:40:35.555559 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8289 00:40:35.555973 ==
8290 00:40:35.559118 Dram Type= 6, Freq= 0, CH_1, rank 1
8291 00:40:35.565399 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8292 00:40:35.565816 ==
8293 00:40:35.568561 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8294 00:40:35.575180 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8295 00:40:35.578822 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8296 00:40:35.584964 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8297 00:40:35.592733 [CA 0] Center 42 (12~72) winsize 61
8298 00:40:35.596366 [CA 1] Center 42 (13~72) winsize 60
8299 00:40:35.599721 [CA 2] Center 38 (9~68) winsize 60
8300 00:40:35.602731 [CA 3] Center 37 (8~67) winsize 60
8301 00:40:35.605763 [CA 4] Center 38 (8~68) winsize 61
8302 00:40:35.609232 [CA 5] Center 37 (8~67) winsize 60
8303 00:40:35.609683
8304 00:40:35.612737 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8305 00:40:35.613312
8306 00:40:35.619282 [CATrainingPosCal] consider 2 rank data
8307 00:40:35.619756 u2DelayCellTimex100 = 275/100 ps
8308 00:40:35.626025 CA0 delay=42 (12~72),Diff = 5 PI (17 cell)
8309 00:40:35.629186 CA1 delay=42 (13~72),Diff = 5 PI (17 cell)
8310 00:40:35.632024 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8311 00:40:35.635969 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8312 00:40:35.639324 CA4 delay=38 (8~68),Diff = 1 PI (3 cell)
8313 00:40:35.642714 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8314 00:40:35.643326
8315 00:40:35.645583 CA PerBit enable=1, Macro0, CA PI delay=37
8316 00:40:35.646162
8317 00:40:35.648858 [CBTSetCACLKResult] CA Dly = 37
8318 00:40:35.651985 CS Dly: 9 (0~42)
8319 00:40:35.655336 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8320 00:40:35.658556 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8321 00:40:35.659063
8322 00:40:35.661788 ----->DramcWriteLeveling(PI) begin...
8323 00:40:35.662210 ==
8324 00:40:35.665411 Dram Type= 6, Freq= 0, CH_1, rank 0
8325 00:40:35.672370 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8326 00:40:35.672812 ==
8327 00:40:35.675574 Write leveling (Byte 0): 24 => 24
8328 00:40:35.678905 Write leveling (Byte 1): 26 => 26
8329 00:40:35.679319 DramcWriteLeveling(PI) end<-----
8330 00:40:35.681845
8331 00:40:35.682256 ==
8332 00:40:35.685112 Dram Type= 6, Freq= 0, CH_1, rank 0
8333 00:40:35.688570 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8334 00:40:35.689028 ==
8335 00:40:35.692133 [Gating] SW mode calibration
8336 00:40:35.698152 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8337 00:40:35.701331 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8338 00:40:35.707758 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8339 00:40:35.711925 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8340 00:40:35.715010 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8341 00:40:35.721219 1 4 12 | B1->B0 | 2525 3333 | 0 1 | (0 0) (0 0)
8342 00:40:35.724563 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8343 00:40:35.727756 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8344 00:40:35.733973 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8345 00:40:35.737321 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8346 00:40:35.744195 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8347 00:40:35.747656 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8348 00:40:35.750918 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8349 00:40:35.757915 1 5 12 | B1->B0 | 3131 2727 | 1 0 | (1 0) (1 0)
8350 00:40:35.760676 1 5 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8351 00:40:35.764343 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8352 00:40:35.771267 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8353 00:40:35.774161 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8354 00:40:35.777565 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8355 00:40:35.783949 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8356 00:40:35.787408 1 6 8 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
8357 00:40:35.790754 1 6 12 | B1->B0 | 3434 4646 | 1 0 | (0 0) (0 0)
8358 00:40:35.797697 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8359 00:40:35.800503 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8360 00:40:35.803490 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8361 00:40:35.807070 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8362 00:40:35.813628 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8363 00:40:35.816944 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8364 00:40:35.820638 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8365 00:40:35.827091 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8366 00:40:35.830102 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8367 00:40:35.833335 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8368 00:40:35.839806 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8369 00:40:35.843439 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8370 00:40:35.846787 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8371 00:40:35.853459 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8372 00:40:35.856887 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8373 00:40:35.860459 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8374 00:40:35.866254 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8375 00:40:35.870347 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8376 00:40:35.873450 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8377 00:40:35.879667 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8378 00:40:35.883064 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8379 00:40:35.886138 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8380 00:40:35.892883 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8381 00:40:35.896665 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8382 00:40:35.899341 Total UI for P1: 0, mck2ui 16
8383 00:40:35.902330 best dqsien dly found for B0: ( 1, 9, 10)
8384 00:40:35.905870 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8385 00:40:35.912495 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8386 00:40:35.915719 Total UI for P1: 0, mck2ui 16
8387 00:40:35.919218 best dqsien dly found for B1: ( 1, 9, 14)
8388 00:40:35.922329 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8389 00:40:35.925367 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8390 00:40:35.925781
8391 00:40:35.928796 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8392 00:40:35.932676 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8393 00:40:35.935826 [Gating] SW calibration Done
8394 00:40:35.936366 ==
8395 00:40:35.939600 Dram Type= 6, Freq= 0, CH_1, rank 0
8396 00:40:35.942293 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8397 00:40:35.945553 ==
8398 00:40:35.946066 RX Vref Scan: 0
8399 00:40:35.946524
8400 00:40:35.948754 RX Vref 0 -> 0, step: 1
8401 00:40:35.949232
8402 00:40:35.949721 RX Delay 0 -> 252, step: 8
8403 00:40:35.955054 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8404 00:40:35.958623 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8405 00:40:35.961695 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8406 00:40:35.965573 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8407 00:40:35.968293 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8408 00:40:35.975186 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8409 00:40:35.979064 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8410 00:40:35.981708 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8411 00:40:35.985283 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8412 00:40:35.988277 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8413 00:40:35.995013 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8414 00:40:35.998145 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8415 00:40:36.001325 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8416 00:40:36.005189 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8417 00:40:36.011786 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8418 00:40:36.015110 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8419 00:40:36.015530 ==
8420 00:40:36.017881 Dram Type= 6, Freq= 0, CH_1, rank 0
8421 00:40:36.021014 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8422 00:40:36.021540 ==
8423 00:40:36.024467 DQS Delay:
8424 00:40:36.024880 DQS0 = 0, DQS1 = 0
8425 00:40:36.025207 DQM Delay:
8426 00:40:36.027493 DQM0 = 134, DQM1 = 130
8427 00:40:36.027907 DQ Delay:
8428 00:40:36.031207 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8429 00:40:36.034296 DQ4 =131, DQ5 =143, DQ6 =147, DQ7 =127
8430 00:40:36.041345 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =127
8431 00:40:36.044782 DQ12 =139, DQ13 =143, DQ14 =135, DQ15 =135
8432 00:40:36.045208
8433 00:40:36.045585
8434 00:40:36.045895 ==
8435 00:40:36.047534 Dram Type= 6, Freq= 0, CH_1, rank 0
8436 00:40:36.051230 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8437 00:40:36.051681 ==
8438 00:40:36.052211
8439 00:40:36.052541
8440 00:40:36.054056 TX Vref Scan disable
8441 00:40:36.057610 == TX Byte 0 ==
8442 00:40:36.061227 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8443 00:40:36.064189 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8444 00:40:36.067535 == TX Byte 1 ==
8445 00:40:36.070833 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8446 00:40:36.073965 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8447 00:40:36.074437 ==
8448 00:40:36.077702 Dram Type= 6, Freq= 0, CH_1, rank 0
8449 00:40:36.081015 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8450 00:40:36.084309 ==
8451 00:40:36.095886
8452 00:40:36.099715 TX Vref early break, caculate TX vref
8453 00:40:36.102465 TX Vref=16, minBit 9, minWin=21, winSum=371
8454 00:40:36.106537 TX Vref=18, minBit 8, minWin=22, winSum=377
8455 00:40:36.109300 TX Vref=20, minBit 8, minWin=23, winSum=386
8456 00:40:36.112551 TX Vref=22, minBit 8, minWin=23, winSum=394
8457 00:40:36.115979 TX Vref=24, minBit 9, minWin=24, winSum=409
8458 00:40:36.122753 TX Vref=26, minBit 3, minWin=25, winSum=416
8459 00:40:36.125954 TX Vref=28, minBit 9, minWin=25, winSum=417
8460 00:40:36.128634 TX Vref=30, minBit 0, minWin=25, winSum=415
8461 00:40:36.132083 TX Vref=32, minBit 11, minWin=23, winSum=405
8462 00:40:36.135627 TX Vref=34, minBit 9, minWin=23, winSum=399
8463 00:40:36.138824 TX Vref=36, minBit 9, minWin=22, winSum=387
8464 00:40:36.145520 [TxChooseVref] Worse bit 9, Min win 25, Win sum 417, Final Vref 28
8465 00:40:36.145931
8466 00:40:36.149099 Final TX Range 0 Vref 28
8467 00:40:36.149684
8468 00:40:36.150024 ==
8469 00:40:36.152007 Dram Type= 6, Freq= 0, CH_1, rank 0
8470 00:40:36.155181 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8471 00:40:36.155727 ==
8472 00:40:36.159223
8473 00:40:36.159743
8474 00:40:36.160168 TX Vref Scan disable
8475 00:40:36.165160 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8476 00:40:36.165827 == TX Byte 0 ==
8477 00:40:36.168237 u2DelayCellOfst[0]=14 cells (4 PI)
8478 00:40:36.171621 u2DelayCellOfst[1]=10 cells (3 PI)
8479 00:40:36.175228 u2DelayCellOfst[2]=0 cells (0 PI)
8480 00:40:36.178266 u2DelayCellOfst[3]=7 cells (2 PI)
8481 00:40:36.181707 u2DelayCellOfst[4]=10 cells (3 PI)
8482 00:40:36.184762 u2DelayCellOfst[5]=14 cells (4 PI)
8483 00:40:36.188132 u2DelayCellOfst[6]=17 cells (5 PI)
8484 00:40:36.191328 u2DelayCellOfst[7]=7 cells (2 PI)
8485 00:40:36.194967 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8486 00:40:36.198810 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8487 00:40:36.201614 == TX Byte 1 ==
8488 00:40:36.204523 u2DelayCellOfst[8]=0 cells (0 PI)
8489 00:40:36.208201 u2DelayCellOfst[9]=3 cells (1 PI)
8490 00:40:36.211392 u2DelayCellOfst[10]=10 cells (3 PI)
8491 00:40:36.214591 u2DelayCellOfst[11]=3 cells (1 PI)
8492 00:40:36.217758 u2DelayCellOfst[12]=14 cells (4 PI)
8493 00:40:36.221290 u2DelayCellOfst[13]=14 cells (4 PI)
8494 00:40:36.224663 u2DelayCellOfst[14]=17 cells (5 PI)
8495 00:40:36.227388 u2DelayCellOfst[15]=17 cells (5 PI)
8496 00:40:36.231139 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8497 00:40:36.234451 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8498 00:40:36.237422 DramC Write-DBI on
8499 00:40:36.237866 ==
8500 00:40:36.241158 Dram Type= 6, Freq= 0, CH_1, rank 0
8501 00:40:36.244244 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8502 00:40:36.244665 ==
8503 00:40:36.244994
8504 00:40:36.245345
8505 00:40:36.247699 TX Vref Scan disable
8506 00:40:36.248206 == TX Byte 0 ==
8507 00:40:36.254400 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8508 00:40:36.254879 == TX Byte 1 ==
8509 00:40:36.260807 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8510 00:40:36.261347 DramC Write-DBI off
8511 00:40:36.261685
8512 00:40:36.261995 [DATLAT]
8513 00:40:36.264264 Freq=1600, CH1 RK0
8514 00:40:36.264770
8515 00:40:36.267442 DATLAT Default: 0xf
8516 00:40:36.267860 0, 0xFFFF, sum = 0
8517 00:40:36.271009 1, 0xFFFF, sum = 0
8518 00:40:36.271517 2, 0xFFFF, sum = 0
8519 00:40:36.274302 3, 0xFFFF, sum = 0
8520 00:40:36.274793 4, 0xFFFF, sum = 0
8521 00:40:36.276979 5, 0xFFFF, sum = 0
8522 00:40:36.277451 6, 0xFFFF, sum = 0
8523 00:40:36.280461 7, 0xFFFF, sum = 0
8524 00:40:36.280884 8, 0xFFFF, sum = 0
8525 00:40:36.283629 9, 0xFFFF, sum = 0
8526 00:40:36.284052 10, 0xFFFF, sum = 0
8527 00:40:36.287608 11, 0xFFFF, sum = 0
8528 00:40:36.288126 12, 0xFFFF, sum = 0
8529 00:40:36.290571 13, 0xFFFF, sum = 0
8530 00:40:36.290994 14, 0x0, sum = 1
8531 00:40:36.293879 15, 0x0, sum = 2
8532 00:40:36.294305 16, 0x0, sum = 3
8533 00:40:36.297106 17, 0x0, sum = 4
8534 00:40:36.297569 best_step = 15
8535 00:40:36.297901
8536 00:40:36.298209 ==
8537 00:40:36.300310 Dram Type= 6, Freq= 0, CH_1, rank 0
8538 00:40:36.307696 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8539 00:40:36.308222 ==
8540 00:40:36.308698 RX Vref Scan: 1
8541 00:40:36.309047
8542 00:40:36.310292 Set Vref Range= 24 -> 127
8543 00:40:36.310682
8544 00:40:36.313369 RX Vref 24 -> 127, step: 1
8545 00:40:36.313786
8546 00:40:36.314153 RX Delay 19 -> 252, step: 4
8547 00:40:36.316866
8548 00:40:36.317319 Set Vref, RX VrefLevel [Byte0]: 24
8549 00:40:36.320831 [Byte1]: 24
8550 00:40:36.324880
8551 00:40:36.325461 Set Vref, RX VrefLevel [Byte0]: 25
8552 00:40:36.327422 [Byte1]: 25
8553 00:40:36.332166
8554 00:40:36.332646 Set Vref, RX VrefLevel [Byte0]: 26
8555 00:40:36.334993 [Byte1]: 26
8556 00:40:36.339301
8557 00:40:36.339845 Set Vref, RX VrefLevel [Byte0]: 27
8558 00:40:36.342644 [Byte1]: 27
8559 00:40:36.347082
8560 00:40:36.347497 Set Vref, RX VrefLevel [Byte0]: 28
8561 00:40:36.350456 [Byte1]: 28
8562 00:40:36.354441
8563 00:40:36.354927 Set Vref, RX VrefLevel [Byte0]: 29
8564 00:40:36.357983 [Byte1]: 29
8565 00:40:36.362254
8566 00:40:36.362679 Set Vref, RX VrefLevel [Byte0]: 30
8567 00:40:36.365375 [Byte1]: 30
8568 00:40:36.369921
8569 00:40:36.370335 Set Vref, RX VrefLevel [Byte0]: 31
8570 00:40:36.372935 [Byte1]: 31
8571 00:40:36.378284
8572 00:40:36.378786 Set Vref, RX VrefLevel [Byte0]: 32
8573 00:40:36.380825 [Byte1]: 32
8574 00:40:36.384879
8575 00:40:36.385430 Set Vref, RX VrefLevel [Byte0]: 33
8576 00:40:36.388023 [Byte1]: 33
8577 00:40:36.392447
8578 00:40:36.392857 Set Vref, RX VrefLevel [Byte0]: 34
8579 00:40:36.395880 [Byte1]: 34
8580 00:40:36.400501
8581 00:40:36.401020 Set Vref, RX VrefLevel [Byte0]: 35
8582 00:40:36.403522 [Byte1]: 35
8583 00:40:36.407717
8584 00:40:36.408220 Set Vref, RX VrefLevel [Byte0]: 36
8585 00:40:36.410971 [Byte1]: 36
8586 00:40:36.416068
8587 00:40:36.416573 Set Vref, RX VrefLevel [Byte0]: 37
8588 00:40:36.418655 [Byte1]: 37
8589 00:40:36.423391
8590 00:40:36.423919 Set Vref, RX VrefLevel [Byte0]: 38
8591 00:40:36.427056 [Byte1]: 38
8592 00:40:36.430652
8593 00:40:36.431165 Set Vref, RX VrefLevel [Byte0]: 39
8594 00:40:36.433703 [Byte1]: 39
8595 00:40:36.438396
8596 00:40:36.439124 Set Vref, RX VrefLevel [Byte0]: 40
8597 00:40:36.441499 [Byte1]: 40
8598 00:40:36.445401
8599 00:40:36.445903 Set Vref, RX VrefLevel [Byte0]: 41
8600 00:40:36.449077 [Byte1]: 41
8601 00:40:36.453037
8602 00:40:36.453561 Set Vref, RX VrefLevel [Byte0]: 42
8603 00:40:36.456824 [Byte1]: 42
8604 00:40:36.460575
8605 00:40:36.461072 Set Vref, RX VrefLevel [Byte0]: 43
8606 00:40:36.463867 [Byte1]: 43
8607 00:40:36.468249
8608 00:40:36.468668 Set Vref, RX VrefLevel [Byte0]: 44
8609 00:40:36.471831 [Byte1]: 44
8610 00:40:36.476317
8611 00:40:36.476829 Set Vref, RX VrefLevel [Byte0]: 45
8612 00:40:36.479061 [Byte1]: 45
8613 00:40:36.483900
8614 00:40:36.484387 Set Vref, RX VrefLevel [Byte0]: 46
8615 00:40:36.486906 [Byte1]: 46
8616 00:40:36.491026
8617 00:40:36.491440 Set Vref, RX VrefLevel [Byte0]: 47
8618 00:40:36.494627 [Byte1]: 47
8619 00:40:36.498660
8620 00:40:36.499074 Set Vref, RX VrefLevel [Byte0]: 48
8621 00:40:36.501827 [Byte1]: 48
8622 00:40:36.506412
8623 00:40:36.506825 Set Vref, RX VrefLevel [Byte0]: 49
8624 00:40:36.509318 [Byte1]: 49
8625 00:40:36.513517
8626 00:40:36.513930 Set Vref, RX VrefLevel [Byte0]: 50
8627 00:40:36.517064 [Byte1]: 50
8628 00:40:36.521400
8629 00:40:36.521936 Set Vref, RX VrefLevel [Byte0]: 51
8630 00:40:36.524339 [Byte1]: 51
8631 00:40:36.528900
8632 00:40:36.529353 Set Vref, RX VrefLevel [Byte0]: 52
8633 00:40:36.532287 [Byte1]: 52
8634 00:40:36.536791
8635 00:40:36.537356 Set Vref, RX VrefLevel [Byte0]: 53
8636 00:40:36.539696 [Byte1]: 53
8637 00:40:36.544056
8638 00:40:36.544550 Set Vref, RX VrefLevel [Byte0]: 54
8639 00:40:36.547086 [Byte1]: 54
8640 00:40:36.551337
8641 00:40:36.551752 Set Vref, RX VrefLevel [Byte0]: 55
8642 00:40:36.554735 [Byte1]: 55
8643 00:40:36.559312
8644 00:40:36.559819 Set Vref, RX VrefLevel [Byte0]: 56
8645 00:40:36.562340 [Byte1]: 56
8646 00:40:36.566636
8647 00:40:36.567053 Set Vref, RX VrefLevel [Byte0]: 57
8648 00:40:36.570163 [Byte1]: 57
8649 00:40:36.574638
8650 00:40:36.575143 Set Vref, RX VrefLevel [Byte0]: 58
8651 00:40:36.577655 [Byte1]: 58
8652 00:40:36.581665
8653 00:40:36.582145 Set Vref, RX VrefLevel [Byte0]: 59
8654 00:40:36.585762 [Byte1]: 59
8655 00:40:36.589592
8656 00:40:36.590009 Set Vref, RX VrefLevel [Byte0]: 60
8657 00:40:36.592753 [Byte1]: 60
8658 00:40:36.597124
8659 00:40:36.597576 Set Vref, RX VrefLevel [Byte0]: 61
8660 00:40:36.600321 [Byte1]: 61
8661 00:40:36.604289
8662 00:40:36.604704 Set Vref, RX VrefLevel [Byte0]: 62
8663 00:40:36.608074 [Byte1]: 62
8664 00:40:36.612090
8665 00:40:36.612504 Set Vref, RX VrefLevel [Byte0]: 63
8666 00:40:36.615692 [Byte1]: 63
8667 00:40:36.620061
8668 00:40:36.620579 Set Vref, RX VrefLevel [Byte0]: 64
8669 00:40:36.623107 [Byte1]: 64
8670 00:40:36.627261
8671 00:40:36.627677 Set Vref, RX VrefLevel [Byte0]: 65
8672 00:40:36.630587 [Byte1]: 65
8673 00:40:36.635420
8674 00:40:36.635904 Set Vref, RX VrefLevel [Byte0]: 66
8675 00:40:36.638117 [Byte1]: 66
8676 00:40:36.642749
8677 00:40:36.643167 Set Vref, RX VrefLevel [Byte0]: 67
8678 00:40:36.645487 [Byte1]: 67
8679 00:40:36.650558
8680 00:40:36.651044 Set Vref, RX VrefLevel [Byte0]: 68
8681 00:40:36.653124 [Byte1]: 68
8682 00:40:36.657656
8683 00:40:36.658069 Set Vref, RX VrefLevel [Byte0]: 69
8684 00:40:36.661033 [Byte1]: 69
8685 00:40:36.665181
8686 00:40:36.665692 Set Vref, RX VrefLevel [Byte0]: 70
8687 00:40:36.668402 [Byte1]: 70
8688 00:40:36.672616
8689 00:40:36.673058 Final RX Vref Byte 0 = 60 to rank0
8690 00:40:36.676057 Final RX Vref Byte 1 = 60 to rank0
8691 00:40:36.679028 Final RX Vref Byte 0 = 60 to rank1
8692 00:40:36.682721 Final RX Vref Byte 1 = 60 to rank1==
8693 00:40:36.685614 Dram Type= 6, Freq= 0, CH_1, rank 0
8694 00:40:36.693063 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8695 00:40:36.693638 ==
8696 00:40:36.693979 DQS Delay:
8697 00:40:36.695537 DQS0 = 0, DQS1 = 0
8698 00:40:36.695950 DQM Delay:
8699 00:40:36.696275 DQM0 = 132, DQM1 = 128
8700 00:40:36.699296 DQ Delay:
8701 00:40:36.702221 DQ0 =138, DQ1 =128, DQ2 =118, DQ3 =132
8702 00:40:36.705314 DQ4 =128, DQ5 =142, DQ6 =144, DQ7 =128
8703 00:40:36.708781 DQ8 =114, DQ9 =116, DQ10 =128, DQ11 =120
8704 00:40:36.712106 DQ12 =138, DQ13 =138, DQ14 =134, DQ15 =136
8705 00:40:36.712520
8706 00:40:36.712849
8707 00:40:36.713329
8708 00:40:36.715678 [DramC_TX_OE_Calibration] TA2
8709 00:40:36.719152 Original DQ_B0 (3 6) =30, OEN = 27
8710 00:40:36.722079 Original DQ_B1 (3 6) =30, OEN = 27
8711 00:40:36.725194 24, 0x0, End_B0=24 End_B1=24
8712 00:40:36.728793 25, 0x0, End_B0=25 End_B1=25
8713 00:40:36.729328 26, 0x0, End_B0=26 End_B1=26
8714 00:40:36.732014 27, 0x0, End_B0=27 End_B1=27
8715 00:40:36.734878 28, 0x0, End_B0=28 End_B1=28
8716 00:40:36.738618 29, 0x0, End_B0=29 End_B1=29
8717 00:40:36.739041 30, 0x0, End_B0=30 End_B1=30
8718 00:40:36.741815 31, 0x4141, End_B0=30 End_B1=30
8719 00:40:36.745221 Byte0 end_step=30 best_step=27
8720 00:40:36.748566 Byte1 end_step=30 best_step=27
8721 00:40:36.752164 Byte0 TX OE(2T, 0.5T) = (3, 3)
8722 00:40:36.754608 Byte1 TX OE(2T, 0.5T) = (3, 3)
8723 00:40:36.755022
8724 00:40:36.755350
8725 00:40:36.761599 [DQSOSCAuto] RK0, (LSB)MR18= 0x111a, (MSB)MR19= 0x303, tDQSOscB0 = 396 ps tDQSOscB1 = 401 ps
8726 00:40:36.764836 CH1 RK0: MR19=303, MR18=111A
8727 00:40:36.771315 CH1_RK0: MR19=0x303, MR18=0x111A, DQSOSC=396, MR23=63, INC=23, DEC=15
8728 00:40:36.771791
8729 00:40:36.774284 ----->DramcWriteLeveling(PI) begin...
8730 00:40:36.774705 ==
8731 00:40:36.777747 Dram Type= 6, Freq= 0, CH_1, rank 1
8732 00:40:36.781195 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8733 00:40:36.784240 ==
8734 00:40:36.784734 Write leveling (Byte 0): 24 => 24
8735 00:40:36.787433 Write leveling (Byte 1): 24 => 24
8736 00:40:36.790620 DramcWriteLeveling(PI) end<-----
8737 00:40:36.791034
8738 00:40:36.791358 ==
8739 00:40:36.793811 Dram Type= 6, Freq= 0, CH_1, rank 1
8740 00:40:36.800791 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8741 00:40:36.801327 ==
8742 00:40:36.804067 [Gating] SW mode calibration
8743 00:40:36.810523 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8744 00:40:36.813539 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8745 00:40:36.820502 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8746 00:40:36.824236 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8747 00:40:36.827252 1 4 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8748 00:40:36.833501 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8749 00:40:36.836785 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8750 00:40:36.840383 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8751 00:40:36.846638 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8752 00:40:36.850413 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8753 00:40:36.853124 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8754 00:40:36.859601 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8755 00:40:36.863502 1 5 8 | B1->B0 | 3434 2424 | 1 0 | (1 0) (1 0)
8756 00:40:36.866134 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8757 00:40:36.873324 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8758 00:40:36.876378 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8759 00:40:36.880303 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8760 00:40:36.886536 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8761 00:40:36.889786 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8762 00:40:36.892863 1 6 4 | B1->B0 | 2323 2828 | 0 0 | (0 0) (1 1)
8763 00:40:36.899310 1 6 8 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8764 00:40:36.902983 1 6 12 | B1->B0 | 2a2a 4646 | 0 0 | (1 1) (0 0)
8765 00:40:36.905720 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8766 00:40:36.912278 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8767 00:40:36.915900 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8768 00:40:36.919244 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8769 00:40:36.925367 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8770 00:40:36.928799 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8771 00:40:36.932445 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8772 00:40:36.938426 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8773 00:40:36.942349 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8774 00:40:36.945239 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8775 00:40:36.951994 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8776 00:40:36.955161 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8777 00:40:36.958664 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8778 00:40:36.965307 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8779 00:40:36.968875 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8780 00:40:36.971864 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8781 00:40:36.978264 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8782 00:40:36.981634 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8783 00:40:36.985089 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8784 00:40:36.991631 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8785 00:40:36.995123 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8786 00:40:36.998184 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8787 00:40:37.005248 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8788 00:40:37.007993 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8789 00:40:37.011213 Total UI for P1: 0, mck2ui 16
8790 00:40:37.014760 best dqsien dly found for B0: ( 1, 9, 6)
8791 00:40:37.017642 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8792 00:40:37.021211 Total UI for P1: 0, mck2ui 16
8793 00:40:37.024591 best dqsien dly found for B1: ( 1, 9, 12)
8794 00:40:37.028087 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8795 00:40:37.030959 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8796 00:40:37.034408
8797 00:40:37.037996 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8798 00:40:37.040580 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8799 00:40:37.044077 [Gating] SW calibration Done
8800 00:40:37.044590 ==
8801 00:40:37.047239 Dram Type= 6, Freq= 0, CH_1, rank 1
8802 00:40:37.051281 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8803 00:40:37.051797 ==
8804 00:40:37.053644 RX Vref Scan: 0
8805 00:40:37.054062
8806 00:40:37.054431 RX Vref 0 -> 0, step: 1
8807 00:40:37.054796
8808 00:40:37.057061 RX Delay 0 -> 252, step: 8
8809 00:40:37.060204 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8810 00:40:37.063667 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8811 00:40:37.070431 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8812 00:40:37.073909 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8813 00:40:37.077043 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8814 00:40:37.080938 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8815 00:40:37.083411 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8816 00:40:37.089705 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8817 00:40:37.093461 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8818 00:40:37.096796 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8819 00:40:37.099854 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8820 00:40:37.106336 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8821 00:40:37.109703 iDelay=200, Bit 12, Center 139 (80 ~ 199) 120
8822 00:40:37.112952 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8823 00:40:37.116166 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8824 00:40:37.122778 iDelay=200, Bit 15, Center 139 (80 ~ 199) 120
8825 00:40:37.123192 ==
8826 00:40:37.125895 Dram Type= 6, Freq= 0, CH_1, rank 1
8827 00:40:37.129703 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8828 00:40:37.130123 ==
8829 00:40:37.130454 DQS Delay:
8830 00:40:37.132539 DQS0 = 0, DQS1 = 0
8831 00:40:37.132953 DQM Delay:
8832 00:40:37.136604 DQM0 = 132, DQM1 = 131
8833 00:40:37.137119 DQ Delay:
8834 00:40:37.139804 DQ0 =135, DQ1 =131, DQ2 =119, DQ3 =127
8835 00:40:37.142789 DQ4 =131, DQ5 =143, DQ6 =139, DQ7 =131
8836 00:40:37.146073 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =127
8837 00:40:37.149674 DQ12 =139, DQ13 =143, DQ14 =135, DQ15 =139
8838 00:40:37.150097
8839 00:40:37.150423
8840 00:40:37.152667 ==
8841 00:40:37.156454 Dram Type= 6, Freq= 0, CH_1, rank 1
8842 00:40:37.158891 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8843 00:40:37.159305 ==
8844 00:40:37.159656
8845 00:40:37.159962
8846 00:40:37.162751 TX Vref Scan disable
8847 00:40:37.163259 == TX Byte 0 ==
8848 00:40:37.168986 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8849 00:40:37.171772 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8850 00:40:37.172297 == TX Byte 1 ==
8851 00:40:37.179011 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8852 00:40:37.181842 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8853 00:40:37.182267 ==
8854 00:40:37.185376 Dram Type= 6, Freq= 0, CH_1, rank 1
8855 00:40:37.188698 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8856 00:40:37.189119 ==
8857 00:40:37.202968
8858 00:40:37.206189 TX Vref early break, caculate TX vref
8859 00:40:37.209702 TX Vref=16, minBit 5, minWin=23, winSum=385
8860 00:40:37.212765 TX Vref=18, minBit 9, minWin=23, winSum=391
8861 00:40:37.216164 TX Vref=20, minBit 1, minWin=23, winSum=397
8862 00:40:37.219151 TX Vref=22, minBit 5, minWin=24, winSum=405
8863 00:40:37.222860 TX Vref=24, minBit 5, minWin=24, winSum=412
8864 00:40:37.229137 TX Vref=26, minBit 3, minWin=25, winSum=420
8865 00:40:37.232184 TX Vref=28, minBit 0, minWin=26, winSum=421
8866 00:40:37.235737 TX Vref=30, minBit 15, minWin=25, winSum=424
8867 00:40:37.239242 TX Vref=32, minBit 0, minWin=25, winSum=414
8868 00:40:37.242512 TX Vref=34, minBit 9, minWin=24, winSum=407
8869 00:40:37.248816 TX Vref=36, minBit 0, minWin=23, winSum=395
8870 00:40:37.252059 [TxChooseVref] Worse bit 0, Min win 26, Win sum 421, Final Vref 28
8871 00:40:37.252480
8872 00:40:37.255330 Final TX Range 0 Vref 28
8873 00:40:37.255752
8874 00:40:37.256121 ==
8875 00:40:37.259176 Dram Type= 6, Freq= 0, CH_1, rank 1
8876 00:40:37.262116 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8877 00:40:37.265372 ==
8878 00:40:37.265795
8879 00:40:37.266126
8880 00:40:37.266438 TX Vref Scan disable
8881 00:40:37.272277 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8882 00:40:37.272702 == TX Byte 0 ==
8883 00:40:37.275348 u2DelayCellOfst[0]=14 cells (4 PI)
8884 00:40:37.278869 u2DelayCellOfst[1]=10 cells (3 PI)
8885 00:40:37.281964 u2DelayCellOfst[2]=0 cells (0 PI)
8886 00:40:37.285588 u2DelayCellOfst[3]=3 cells (1 PI)
8887 00:40:37.288446 u2DelayCellOfst[4]=7 cells (2 PI)
8888 00:40:37.291925 u2DelayCellOfst[5]=14 cells (4 PI)
8889 00:40:37.295005 u2DelayCellOfst[6]=14 cells (4 PI)
8890 00:40:37.298570 u2DelayCellOfst[7]=3 cells (1 PI)
8891 00:40:37.301691 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8892 00:40:37.304921 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8893 00:40:37.308082 == TX Byte 1 ==
8894 00:40:37.311667 u2DelayCellOfst[8]=0 cells (0 PI)
8895 00:40:37.314658 u2DelayCellOfst[9]=3 cells (1 PI)
8896 00:40:37.318063 u2DelayCellOfst[10]=14 cells (4 PI)
8897 00:40:37.321155 u2DelayCellOfst[11]=7 cells (2 PI)
8898 00:40:37.325038 u2DelayCellOfst[12]=17 cells (5 PI)
8899 00:40:37.328208 u2DelayCellOfst[13]=17 cells (5 PI)
8900 00:40:37.331160 u2DelayCellOfst[14]=21 cells (6 PI)
8901 00:40:37.334741 u2DelayCellOfst[15]=17 cells (5 PI)
8902 00:40:37.338001 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8903 00:40:37.341376 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8904 00:40:37.344450 DramC Write-DBI on
8905 00:40:37.344866 ==
8906 00:40:37.347252 Dram Type= 6, Freq= 0, CH_1, rank 1
8907 00:40:37.350698 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8908 00:40:37.351119 ==
8909 00:40:37.351446
8910 00:40:37.351747
8911 00:40:37.353948 TX Vref Scan disable
8912 00:40:37.357795 == TX Byte 0 ==
8913 00:40:37.360615 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8914 00:40:37.361035 == TX Byte 1 ==
8915 00:40:37.367469 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
8916 00:40:37.367954 DramC Write-DBI off
8917 00:40:37.368305
8918 00:40:37.368636 [DATLAT]
8919 00:40:37.370833 Freq=1600, CH1 RK1
8920 00:40:37.371250
8921 00:40:37.373838 DATLAT Default: 0xf
8922 00:40:37.374257 0, 0xFFFF, sum = 0
8923 00:40:37.377218 1, 0xFFFF, sum = 0
8924 00:40:37.377780 2, 0xFFFF, sum = 0
8925 00:40:37.380248 3, 0xFFFF, sum = 0
8926 00:40:37.380706 4, 0xFFFF, sum = 0
8927 00:40:37.383450 5, 0xFFFF, sum = 0
8928 00:40:37.383871 6, 0xFFFF, sum = 0
8929 00:40:37.387097 7, 0xFFFF, sum = 0
8930 00:40:37.387519 8, 0xFFFF, sum = 0
8931 00:40:37.390038 9, 0xFFFF, sum = 0
8932 00:40:37.390459 10, 0xFFFF, sum = 0
8933 00:40:37.393445 11, 0xFFFF, sum = 0
8934 00:40:37.393867 12, 0xFFFF, sum = 0
8935 00:40:37.396893 13, 0xFFFF, sum = 0
8936 00:40:37.397427 14, 0x0, sum = 1
8937 00:40:37.399913 15, 0x0, sum = 2
8938 00:40:37.400337 16, 0x0, sum = 3
8939 00:40:37.403314 17, 0x0, sum = 4
8940 00:40:37.403803 best_step = 15
8941 00:40:37.404133
8942 00:40:37.404440 ==
8943 00:40:37.406482 Dram Type= 6, Freq= 0, CH_1, rank 1
8944 00:40:37.413109 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8945 00:40:37.413603 ==
8946 00:40:37.413940 RX Vref Scan: 0
8947 00:40:37.414249
8948 00:40:37.416657 RX Vref 0 -> 0, step: 1
8949 00:40:37.417072
8950 00:40:37.419962 RX Delay 19 -> 252, step: 4
8951 00:40:37.423205 iDelay=195, Bit 0, Center 134 (83 ~ 186) 104
8952 00:40:37.426947 iDelay=195, Bit 1, Center 128 (75 ~ 182) 108
8953 00:40:37.433710 iDelay=195, Bit 2, Center 118 (63 ~ 174) 112
8954 00:40:37.436424 iDelay=195, Bit 3, Center 128 (75 ~ 182) 108
8955 00:40:37.439972 iDelay=195, Bit 4, Center 130 (75 ~ 186) 112
8956 00:40:37.442848 iDelay=195, Bit 5, Center 142 (91 ~ 194) 104
8957 00:40:37.446350 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
8958 00:40:37.452791 iDelay=195, Bit 7, Center 128 (75 ~ 182) 108
8959 00:40:37.455916 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
8960 00:40:37.459743 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8961 00:40:37.463235 iDelay=195, Bit 10, Center 130 (79 ~ 182) 104
8962 00:40:37.466008 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8963 00:40:37.472677 iDelay=195, Bit 12, Center 138 (87 ~ 190) 104
8964 00:40:37.476422 iDelay=195, Bit 13, Center 136 (83 ~ 190) 108
8965 00:40:37.479531 iDelay=195, Bit 14, Center 134 (83 ~ 186) 104
8966 00:40:37.482423 iDelay=195, Bit 15, Center 136 (83 ~ 190) 108
8967 00:40:37.482888 ==
8968 00:40:37.485941 Dram Type= 6, Freq= 0, CH_1, rank 1
8969 00:40:37.493089 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8970 00:40:37.493702 ==
8971 00:40:37.494068 DQS Delay:
8972 00:40:37.495563 DQS0 = 0, DQS1 = 0
8973 00:40:37.496020 DQM Delay:
8974 00:40:37.499436 DQM0 = 130, DQM1 = 128
8975 00:40:37.499850 DQ Delay:
8976 00:40:37.502125 DQ0 =134, DQ1 =128, DQ2 =118, DQ3 =128
8977 00:40:37.505729 DQ4 =130, DQ5 =142, DQ6 =138, DQ7 =128
8978 00:40:37.509042 DQ8 =116, DQ9 =118, DQ10 =130, DQ11 =120
8979 00:40:37.512413 DQ12 =138, DQ13 =136, DQ14 =134, DQ15 =136
8980 00:40:37.512835
8981 00:40:37.513164
8982 00:40:37.513556
8983 00:40:37.515840 [DramC_TX_OE_Calibration] TA2
8984 00:40:37.519254 Original DQ_B0 (3 6) =30, OEN = 27
8985 00:40:37.522454 Original DQ_B1 (3 6) =30, OEN = 27
8986 00:40:37.525686 24, 0x0, End_B0=24 End_B1=24
8987 00:40:37.528962 25, 0x0, End_B0=25 End_B1=25
8988 00:40:37.529429 26, 0x0, End_B0=26 End_B1=26
8989 00:40:37.532107 27, 0x0, End_B0=27 End_B1=27
8990 00:40:37.535339 28, 0x0, End_B0=28 End_B1=28
8991 00:40:37.538881 29, 0x0, End_B0=29 End_B1=29
8992 00:40:37.542008 30, 0x0, End_B0=30 End_B1=30
8993 00:40:37.542431 31, 0x4141, End_B0=30 End_B1=30
8994 00:40:37.545334 Byte0 end_step=30 best_step=27
8995 00:40:37.548757 Byte1 end_step=30 best_step=27
8996 00:40:37.552301 Byte0 TX OE(2T, 0.5T) = (3, 3)
8997 00:40:37.555102 Byte1 TX OE(2T, 0.5T) = (3, 3)
8998 00:40:37.555519
8999 00:40:37.555931
9000 00:40:37.562025 [DQSOSCAuto] RK1, (LSB)MR18= 0x1220, (MSB)MR19= 0x303, tDQSOscB0 = 393 ps tDQSOscB1 = 400 ps
9001 00:40:37.565563 CH1 RK1: MR19=303, MR18=1220
9002 00:40:37.571581 CH1_RK1: MR19=0x303, MR18=0x1220, DQSOSC=393, MR23=63, INC=23, DEC=15
9003 00:40:37.575307 [RxdqsGatingPostProcess] freq 1600
9004 00:40:37.581509 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9005 00:40:37.585234 best DQS0 dly(2T, 0.5T) = (1, 1)
9006 00:40:37.585679 best DQS1 dly(2T, 0.5T) = (1, 1)
9007 00:40:37.587886 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9008 00:40:37.591537 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9009 00:40:37.594427 best DQS0 dly(2T, 0.5T) = (1, 1)
9010 00:40:37.597943 best DQS1 dly(2T, 0.5T) = (1, 1)
9011 00:40:37.601459 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9012 00:40:37.604803 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9013 00:40:37.608215 Pre-setting of DQS Precalculation
9014 00:40:37.610890 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9015 00:40:37.620955 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9016 00:40:37.627569 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9017 00:40:37.628106
9018 00:40:37.628444
9019 00:40:37.630427 [Calibration Summary] 3200 Mbps
9020 00:40:37.630846 CH 0, Rank 0
9021 00:40:37.634269 SW Impedance : PASS
9022 00:40:37.637517 DUTY Scan : NO K
9023 00:40:37.638158 ZQ Calibration : PASS
9024 00:40:37.640789 Jitter Meter : NO K
9025 00:40:37.643909 CBT Training : PASS
9026 00:40:37.644487 Write leveling : PASS
9027 00:40:37.647089 RX DQS gating : PASS
9028 00:40:37.647505 RX DQ/DQS(RDDQC) : PASS
9029 00:40:37.650594 TX DQ/DQS : PASS
9030 00:40:37.654009 RX DATLAT : PASS
9031 00:40:37.654433 RX DQ/DQS(Engine): PASS
9032 00:40:37.657489 TX OE : PASS
9033 00:40:37.657908 All Pass.
9034 00:40:37.658239
9035 00:40:37.660641 CH 0, Rank 1
9036 00:40:37.661053 SW Impedance : PASS
9037 00:40:37.663575 DUTY Scan : NO K
9038 00:40:37.667258 ZQ Calibration : PASS
9039 00:40:37.667775 Jitter Meter : NO K
9040 00:40:37.670366 CBT Training : PASS
9041 00:40:37.674024 Write leveling : PASS
9042 00:40:37.674443 RX DQS gating : PASS
9043 00:40:37.677539 RX DQ/DQS(RDDQC) : PASS
9044 00:40:37.680913 TX DQ/DQS : PASS
9045 00:40:37.681460 RX DATLAT : PASS
9046 00:40:37.683625 RX DQ/DQS(Engine): PASS
9047 00:40:37.687533 TX OE : PASS
9048 00:40:37.688047 All Pass.
9049 00:40:37.688380
9050 00:40:37.688689 CH 1, Rank 0
9051 00:40:37.690495 SW Impedance : PASS
9052 00:40:37.693762 DUTY Scan : NO K
9053 00:40:37.694176 ZQ Calibration : PASS
9054 00:40:37.697410 Jitter Meter : NO K
9055 00:40:37.700092 CBT Training : PASS
9056 00:40:37.700512 Write leveling : PASS
9057 00:40:37.703729 RX DQS gating : PASS
9058 00:40:37.706916 RX DQ/DQS(RDDQC) : PASS
9059 00:40:37.707427 TX DQ/DQS : PASS
9060 00:40:37.709928 RX DATLAT : PASS
9061 00:40:37.710346 RX DQ/DQS(Engine): PASS
9062 00:40:37.713793 TX OE : PASS
9063 00:40:37.714212 All Pass.
9064 00:40:37.714541
9065 00:40:37.716896 CH 1, Rank 1
9066 00:40:37.717346 SW Impedance : PASS
9067 00:40:37.720038 DUTY Scan : NO K
9068 00:40:37.723051 ZQ Calibration : PASS
9069 00:40:37.723465 Jitter Meter : NO K
9070 00:40:37.726599 CBT Training : PASS
9071 00:40:37.729917 Write leveling : PASS
9072 00:40:37.730334 RX DQS gating : PASS
9073 00:40:37.733140 RX DQ/DQS(RDDQC) : PASS
9074 00:40:37.736682 TX DQ/DQS : PASS
9075 00:40:37.737195 RX DATLAT : PASS
9076 00:40:37.740085 RX DQ/DQS(Engine): PASS
9077 00:40:37.743040 TX OE : PASS
9078 00:40:37.743458 All Pass.
9079 00:40:37.743787
9080 00:40:37.746165 DramC Write-DBI on
9081 00:40:37.746598 PER_BANK_REFRESH: Hybrid Mode
9082 00:40:37.749926 TX_TRACKING: ON
9083 00:40:37.759331 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9084 00:40:37.766616 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9085 00:40:37.772784 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9086 00:40:37.776494 [FAST_K] Save calibration result to emmc
9087 00:40:37.779455 sync common calibartion params.
9088 00:40:37.782477 sync cbt_mode0:1, 1:1
9089 00:40:37.782893 dram_init: ddr_geometry: 2
9090 00:40:37.786331 dram_init: ddr_geometry: 2
9091 00:40:37.789478 dram_init: ddr_geometry: 2
9092 00:40:37.792696 0:dram_rank_size:100000000
9093 00:40:37.793117 1:dram_rank_size:100000000
9094 00:40:37.799445 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9095 00:40:37.802937 DFS_SHUFFLE_HW_MODE: ON
9096 00:40:37.805805 dramc_set_vcore_voltage set vcore to 725000
9097 00:40:37.808733 Read voltage for 1600, 0
9098 00:40:37.809233 Vio18 = 0
9099 00:40:37.809619 Vcore = 725000
9100 00:40:37.812107 Vdram = 0
9101 00:40:37.812518 Vddq = 0
9102 00:40:37.812947 Vmddr = 0
9103 00:40:37.815508 switch to 3200 Mbps bootup
9104 00:40:37.815948 [DramcRunTimeConfig]
9105 00:40:37.819281 PHYPLL
9106 00:40:37.819747 DPM_CONTROL_AFTERK: ON
9107 00:40:37.822160 PER_BANK_REFRESH: ON
9108 00:40:37.825777 REFRESH_OVERHEAD_REDUCTION: ON
9109 00:40:37.826291 CMD_PICG_NEW_MODE: OFF
9110 00:40:37.828545 XRTWTW_NEW_MODE: ON
9111 00:40:37.829030 XRTRTR_NEW_MODE: ON
9112 00:40:37.832014 TX_TRACKING: ON
9113 00:40:37.832431 RDSEL_TRACKING: OFF
9114 00:40:37.835437 DQS Precalculation for DVFS: ON
9115 00:40:37.838351 RX_TRACKING: OFF
9116 00:40:37.838768 HW_GATING DBG: ON
9117 00:40:37.841874 ZQCS_ENABLE_LP4: ON
9118 00:40:37.842383 RX_PICG_NEW_MODE: ON
9119 00:40:37.845290 TX_PICG_NEW_MODE: ON
9120 00:40:37.848509 ENABLE_RX_DCM_DPHY: ON
9121 00:40:37.851704 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9122 00:40:37.852190 DUMMY_READ_FOR_TRACKING: OFF
9123 00:40:37.854994 !!! SPM_CONTROL_AFTERK: OFF
9124 00:40:37.858288 !!! SPM could not control APHY
9125 00:40:37.861817 IMPEDANCE_TRACKING: ON
9126 00:40:37.862233 TEMP_SENSOR: ON
9127 00:40:37.865183 HW_SAVE_FOR_SR: OFF
9128 00:40:37.865624 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9129 00:40:37.871380 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9130 00:40:37.871890 Read ODT Tracking: ON
9131 00:40:37.875154 Refresh Rate DeBounce: ON
9132 00:40:37.875667 DFS_NO_QUEUE_FLUSH: ON
9133 00:40:37.878461 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9134 00:40:37.881920 ENABLE_DFS_RUNTIME_MRW: OFF
9135 00:40:37.884618 DDR_RESERVE_NEW_MODE: ON
9136 00:40:37.887882 MR_CBT_SWITCH_FREQ: ON
9137 00:40:37.888400 =========================
9138 00:40:37.907926 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9139 00:40:37.910716 dram_init: ddr_geometry: 2
9140 00:40:37.929312 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9141 00:40:37.932585 dram_init: dram init end (result: 0)
9142 00:40:37.939513 DRAM-K: Full calibration passed in 24395 msecs
9143 00:40:37.942634 MRC: failed to locate region type 0.
9144 00:40:37.943095 DRAM rank0 size:0x100000000,
9145 00:40:37.946032 DRAM rank1 size=0x100000000
9146 00:40:37.955847 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9147 00:40:37.962406 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9148 00:40:37.968878 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9149 00:40:37.975461 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9150 00:40:37.979003 DRAM rank0 size:0x100000000,
9151 00:40:37.981837 DRAM rank1 size=0x100000000
9152 00:40:37.982264 CBMEM:
9153 00:40:37.985939 IMD: root @ 0xfffff000 254 entries.
9154 00:40:37.988430 IMD: root @ 0xffffec00 62 entries.
9155 00:40:37.991921 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9156 00:40:37.995495 WARNING: RO_VPD is uninitialized or empty.
9157 00:40:38.002192 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9158 00:40:38.009140 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9159 00:40:38.022139 read SPI 0x42894 0xe01e: 6226 us, 9215 KB/s, 73.720 Mbps
9160 00:40:38.033491 BS: romstage times (exec / console): total (unknown) / 23927 ms
9161 00:40:38.033969
9162 00:40:38.034301
9163 00:40:38.043528 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9164 00:40:38.046303 ARM64: Exception handlers installed.
9165 00:40:38.049963 ARM64: Testing exception
9166 00:40:38.053174 ARM64: Done test exception
9167 00:40:38.053686 Enumerating buses...
9168 00:40:38.056228 Show all devs... Before device enumeration.
9169 00:40:38.059284 Root Device: enabled 1
9170 00:40:38.063329 CPU_CLUSTER: 0: enabled 1
9171 00:40:38.063839 CPU: 00: enabled 1
9172 00:40:38.065892 Compare with tree...
9173 00:40:38.066304 Root Device: enabled 1
9174 00:40:38.069189 CPU_CLUSTER: 0: enabled 1
9175 00:40:38.072841 CPU: 00: enabled 1
9176 00:40:38.073253 Root Device scanning...
9177 00:40:38.075784 scan_static_bus for Root Device
9178 00:40:38.079052 CPU_CLUSTER: 0 enabled
9179 00:40:38.083077 scan_static_bus for Root Device done
9180 00:40:38.085728 scan_bus: bus Root Device finished in 8 msecs
9181 00:40:38.086145 done
9182 00:40:38.092241 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9183 00:40:38.095824 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9184 00:40:38.102378 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9185 00:40:38.105678 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9186 00:40:38.109035 Allocating resources...
9187 00:40:38.112697 Reading resources...
9188 00:40:38.115709 Root Device read_resources bus 0 link: 0
9189 00:40:38.118707 DRAM rank0 size:0x100000000,
9190 00:40:38.119124 DRAM rank1 size=0x100000000
9191 00:40:38.125853 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9192 00:40:38.126366 CPU: 00 missing read_resources
9193 00:40:38.132123 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9194 00:40:38.135857 Root Device read_resources bus 0 link: 0 done
9195 00:40:38.138783 Done reading resources.
9196 00:40:38.141955 Show resources in subtree (Root Device)...After reading.
9197 00:40:38.145702 Root Device child on link 0 CPU_CLUSTER: 0
9198 00:40:38.149364 CPU_CLUSTER: 0 child on link 0 CPU: 00
9199 00:40:38.158627 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9200 00:40:38.159047 CPU: 00
9201 00:40:38.162082 Root Device assign_resources, bus 0 link: 0
9202 00:40:38.165374 CPU_CLUSTER: 0 missing set_resources
9203 00:40:38.172240 Root Device assign_resources, bus 0 link: 0 done
9204 00:40:38.172723 Done setting resources.
9205 00:40:38.178294 Show resources in subtree (Root Device)...After assigning values.
9206 00:40:38.182443 Root Device child on link 0 CPU_CLUSTER: 0
9207 00:40:38.184958 CPU_CLUSTER: 0 child on link 0 CPU: 00
9208 00:40:38.195392 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9209 00:40:38.195969 CPU: 00
9210 00:40:38.198508 Done allocating resources.
9211 00:40:38.204673 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9212 00:40:38.205148 Enabling resources...
9213 00:40:38.208371 done.
9214 00:40:38.211183 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9215 00:40:38.214866 Initializing devices...
9216 00:40:38.215280 Root Device init
9217 00:40:38.218154 init hardware done!
9218 00:40:38.218570 0x00000018: ctrlr->caps
9219 00:40:38.221314 52.000 MHz: ctrlr->f_max
9220 00:40:38.224313 0.400 MHz: ctrlr->f_min
9221 00:40:38.224737 0x40ff8080: ctrlr->voltages
9222 00:40:38.228005 sclk: 390625
9223 00:40:38.228420 Bus Width = 1
9224 00:40:38.231351 sclk: 390625
9225 00:40:38.231765 Bus Width = 1
9226 00:40:38.234473 Early init status = 3
9227 00:40:38.238137 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9228 00:40:38.241230 in-header: 03 fc 00 00 01 00 00 00
9229 00:40:38.244653 in-data: 00
9230 00:40:38.247381 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9231 00:40:38.252081 in-header: 03 fd 00 00 00 00 00 00
9232 00:40:38.255757 in-data:
9233 00:40:38.258891 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9234 00:40:38.262107 in-header: 03 fc 00 00 01 00 00 00
9235 00:40:38.265473 in-data: 00
9236 00:40:38.268758 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9237 00:40:38.273356 in-header: 03 fd 00 00 00 00 00 00
9238 00:40:38.276868 in-data:
9239 00:40:38.279979 [SSUSB] Setting up USB HOST controller...
9240 00:40:38.283224 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9241 00:40:38.286750 [SSUSB] phy power-on done.
9242 00:40:38.289948 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9243 00:40:38.296432 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9244 00:40:38.299545 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9245 00:40:38.306453 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9246 00:40:38.312841 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9247 00:40:38.319391 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9248 00:40:38.325702 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9249 00:40:38.332341 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9250 00:40:38.335965 SPM: binary array size = 0x9dc
9251 00:40:38.339387 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9252 00:40:38.345682 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9253 00:40:38.352451 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9254 00:40:38.358593 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9255 00:40:38.362505 configure_display: Starting display init
9256 00:40:38.396384 anx7625_power_on_init: Init interface.
9257 00:40:38.399790 anx7625_disable_pd_protocol: Disabled PD feature.
9258 00:40:38.403162 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9259 00:40:38.431065 anx7625_start_dp_work: Secure OCM version=00
9260 00:40:38.434335 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9261 00:40:38.449178 sp_tx_get_edid_block: EDID Block = 1
9262 00:40:38.551736 Extracted contents:
9263 00:40:38.555132 header: 00 ff ff ff ff ff ff 00
9264 00:40:38.558979 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9265 00:40:38.561517 version: 01 04
9266 00:40:38.565011 basic params: 95 1f 11 78 0a
9267 00:40:38.568644 chroma info: 76 90 94 55 54 90 27 21 50 54
9268 00:40:38.571681 established: 00 00 00
9269 00:40:38.577945 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9270 00:40:38.581481 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9271 00:40:38.588565 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9272 00:40:38.594352 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9273 00:40:38.601498 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9274 00:40:38.604337 extensions: 00
9275 00:40:38.604749 checksum: fb
9276 00:40:38.605075
9277 00:40:38.610913 Manufacturer: IVO Model 57d Serial Number 0
9278 00:40:38.611370 Made week 0 of 2020
9279 00:40:38.613970 EDID version: 1.4
9280 00:40:38.614564 Digital display
9281 00:40:38.617292 6 bits per primary color channel
9282 00:40:38.620869 DisplayPort interface
9283 00:40:38.621315 Maximum image size: 31 cm x 17 cm
9284 00:40:38.624059 Gamma: 220%
9285 00:40:38.624468 Check DPMS levels
9286 00:40:38.630560 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9287 00:40:38.633952 First detailed timing is preferred timing
9288 00:40:38.634372 Established timings supported:
9289 00:40:38.637738 Standard timings supported:
9290 00:40:38.640625 Detailed timings
9291 00:40:38.644077 Hex of detail: 383680a07038204018303c0035ae10000019
9292 00:40:38.650410 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9293 00:40:38.654008 0780 0798 07c8 0820 hborder 0
9294 00:40:38.656784 0438 043b 0447 0458 vborder 0
9295 00:40:38.660551 -hsync -vsync
9296 00:40:38.660968 Did detailed timing
9297 00:40:38.666855 Hex of detail: 000000000000000000000000000000000000
9298 00:40:38.670218 Manufacturer-specified data, tag 0
9299 00:40:38.673417 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9300 00:40:38.679003 ASCII string: InfoVision
9301 00:40:38.680431 Hex of detail: 000000fe00523134304e574635205248200a
9302 00:40:38.683901 ASCII string: R140NWF5 RH
9303 00:40:38.684316 Checksum
9304 00:40:38.686537 Checksum: 0xfb (valid)
9305 00:40:38.689911 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9306 00:40:38.693559 DSI data_rate: 832800000 bps
9307 00:40:38.699738 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9308 00:40:38.703206 anx7625_parse_edid: pixelclock(138800).
9309 00:40:38.706443 hactive(1920), hsync(48), hfp(24), hbp(88)
9310 00:40:38.709854 vactive(1080), vsync(12), vfp(3), vbp(17)
9311 00:40:38.712790 anx7625_dsi_config: config dsi.
9312 00:40:38.719735 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9313 00:40:38.734045 anx7625_dsi_config: success to config DSI
9314 00:40:38.736867 anx7625_dp_start: MIPI phy setup OK.
9315 00:40:38.740344 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9316 00:40:38.744023 mtk_ddp_mode_set invalid vrefresh 60
9317 00:40:38.746811 main_disp_path_setup
9318 00:40:38.747225 ovl_layer_smi_id_en
9319 00:40:38.750120 ovl_layer_smi_id_en
9320 00:40:38.750538 ccorr_config
9321 00:40:38.750867 aal_config
9322 00:40:38.753581 gamma_config
9323 00:40:38.753994 postmask_config
9324 00:40:38.757109 dither_config
9325 00:40:38.759853 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9326 00:40:38.766371 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9327 00:40:38.769858 Root Device init finished in 551 msecs
9328 00:40:38.773340 CPU_CLUSTER: 0 init
9329 00:40:38.780067 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9330 00:40:38.786260 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9331 00:40:38.786720 APU_MBOX 0x190000b0 = 0x10001
9332 00:40:38.789622 APU_MBOX 0x190001b0 = 0x10001
9333 00:40:38.792851 APU_MBOX 0x190005b0 = 0x10001
9334 00:40:38.796560 APU_MBOX 0x190006b0 = 0x10001
9335 00:40:38.802953 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9336 00:40:38.812671 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9337 00:40:38.825098 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9338 00:40:38.831808 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9339 00:40:38.843555 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9340 00:40:38.852302 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9341 00:40:38.856128 CPU_CLUSTER: 0 init finished in 81 msecs
9342 00:40:38.859107 Devices initialized
9343 00:40:38.862123 Show all devs... After init.
9344 00:40:38.862538 Root Device: enabled 1
9345 00:40:38.866117 CPU_CLUSTER: 0: enabled 1
9346 00:40:38.868828 CPU: 00: enabled 1
9347 00:40:38.872620 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9348 00:40:38.875771 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9349 00:40:38.879026 ELOG: NV offset 0x57f000 size 0x1000
9350 00:40:38.885516 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9351 00:40:38.892052 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9352 00:40:38.895861 ELOG: Event(17) added with size 13 at 2024-06-16 00:40:38 UTC
9353 00:40:38.902642 out: cmd=0x121: 03 db 21 01 00 00 00 00
9354 00:40:38.905184 in-header: 03 01 00 00 2c 00 00 00
9355 00:40:38.914985 in-data: 3c 72 00 00 00 00 00 00 0a 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9356 00:40:38.921933 ELOG: Event(A1) added with size 10 at 2024-06-16 00:40:38 UTC
9357 00:40:38.928655 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
9358 00:40:38.935516 ELOG: Event(A0) added with size 9 at 2024-06-16 00:40:38 UTC
9359 00:40:38.938576 elog_add_boot_reason: Logged dev mode boot
9360 00:40:38.944976 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9361 00:40:38.945529 Finalize devices...
9362 00:40:38.948393 Devices finalized
9363 00:40:38.951432 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9364 00:40:38.955228 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
9365 00:40:38.958100 in-header: 03 07 00 00 08 00 00 00
9366 00:40:38.961650 in-data: aa e4 47 04 13 02 00 00
9367 00:40:38.965020 Chrome EC: UHEPI supported
9368 00:40:38.971971 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
9369 00:40:38.974603 in-header: 03 a9 00 00 08 00 00 00
9370 00:40:38.978172 in-data: 84 60 60 08 00 00 00 00
9371 00:40:38.984748 ELOG: Event(91) added with size 10 at 2024-06-16 00:40:38 UTC
9372 00:40:38.988265 Chrome EC: clear events_b mask to 0x0000000020004000
9373 00:40:38.994865 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
9374 00:40:38.998301 in-header: 03 fd 00 00 00 00 00 00
9375 00:40:39.001354 in-data:
9376 00:40:39.005142 BS: BS_WRITE_TABLES entry times (exec / console): 3 / 46 ms
9377 00:40:39.008235 Writing coreboot table at 0xffe64000
9378 00:40:39.014635 0. 000000000010a000-0000000000113fff: RAMSTAGE
9379 00:40:39.018092 1. 0000000040000000-00000000400fffff: RAM
9380 00:40:39.021098 2. 0000000040100000-000000004032afff: RAMSTAGE
9381 00:40:39.024566 3. 000000004032b000-00000000545fffff: RAM
9382 00:40:39.028579 4. 0000000054600000-000000005465ffff: BL31
9383 00:40:39.031887 5. 0000000054660000-00000000ffe63fff: RAM
9384 00:40:39.038145 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9385 00:40:39.041410 7. 0000000100000000-000000023fffffff: RAM
9386 00:40:39.044496 Passing 5 GPIOs to payload:
9387 00:40:39.048021 NAME | PORT | POLARITY | VALUE
9388 00:40:39.054753 EC in RW | 0x000000aa | low | undefined
9389 00:40:39.058203 EC interrupt | 0x00000005 | low | undefined
9390 00:40:39.064576 TPM interrupt | 0x000000ab | high | undefined
9391 00:40:39.067894 SD card detect | 0x00000011 | high | undefined
9392 00:40:39.071158 speaker enable | 0x00000093 | high | undefined
9393 00:40:39.074370 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9394 00:40:39.078486 in-header: 03 f9 00 00 02 00 00 00
9395 00:40:39.081012 in-data: 02 00
9396 00:40:39.084730 ADC[4]: Raw value=902955 ID=7
9397 00:40:39.087921 ADC[3]: Raw value=213546 ID=1
9398 00:40:39.088476 RAM Code: 0x71
9399 00:40:39.091690 ADC[6]: Raw value=74630 ID=0
9400 00:40:39.094198 ADC[5]: Raw value=213177 ID=1
9401 00:40:39.094662 SKU Code: 0x1
9402 00:40:39.100852 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 928f
9403 00:40:39.101566 coreboot table: 964 bytes.
9404 00:40:39.105010 IMD ROOT 0. 0xfffff000 0x00001000
9405 00:40:39.107159 IMD SMALL 1. 0xffffe000 0x00001000
9406 00:40:39.110946 RO MCACHE 2. 0xffffc000 0x00001104
9407 00:40:39.114070 CONSOLE 3. 0xfff7c000 0x00080000
9408 00:40:39.117481 FMAP 4. 0xfff7b000 0x00000452
9409 00:40:39.120786 TIME STAMP 5. 0xfff7a000 0x00000910
9410 00:40:39.124082 VBOOT WORK 6. 0xfff66000 0x00014000
9411 00:40:39.127414 RAMOOPS 7. 0xffe66000 0x00100000
9412 00:40:39.130211 COREBOOT 8. 0xffe64000 0x00002000
9413 00:40:39.133375 IMD small region:
9414 00:40:39.137235 IMD ROOT 0. 0xffffec00 0x00000400
9415 00:40:39.140890 VPD 1. 0xffffeb80 0x0000006c
9416 00:40:39.143693 MMC STATUS 2. 0xffffeb60 0x00000004
9417 00:40:39.150228 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9418 00:40:39.156819 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9419 00:40:39.195013 read SPI 0x3990ec 0x4f1b0: 34849 us, 9297 KB/s, 74.376 Mbps
9420 00:40:39.198909 Checking segment from ROM address 0x40100000
9421 00:40:39.201704 Checking segment from ROM address 0x4010001c
9422 00:40:39.208948 Loading segment from ROM address 0x40100000
9423 00:40:39.209520 code (compression=0)
9424 00:40:39.218331 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9425 00:40:39.225359 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9426 00:40:39.228086 it's not compressed!
9427 00:40:39.231472 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9428 00:40:39.237847 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9429 00:40:39.255618 Loading segment from ROM address 0x4010001c
9430 00:40:39.256097 Entry Point 0x80000000
9431 00:40:39.259029 Loaded segments
9432 00:40:39.262678 BS: BS_PAYLOAD_LOAD run times (exec / console): 49 / 61 ms
9433 00:40:39.269058 Jumping to boot code at 0x80000000(0xffe64000)
9434 00:40:39.275496 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9435 00:40:39.281938 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9436 00:40:39.289987 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9437 00:40:39.293327 Checking segment from ROM address 0x40100000
9438 00:40:39.297333 Checking segment from ROM address 0x4010001c
9439 00:40:39.303156 Loading segment from ROM address 0x40100000
9440 00:40:39.303596 code (compression=1)
9441 00:40:39.309857 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9442 00:40:39.319602 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9443 00:40:39.320031 using LZMA
9444 00:40:39.328099 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9445 00:40:39.335008 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9446 00:40:39.338382 Loading segment from ROM address 0x4010001c
9447 00:40:39.341592 Entry Point 0x54601000
9448 00:40:39.341817 Loaded segments
9449 00:40:39.344769 NOTICE: MT8192 bl31_setup
9450 00:40:39.351733 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9451 00:40:39.354963 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9452 00:40:39.358662 WARNING: region 0:
9453 00:40:39.361458 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9454 00:40:39.361588 WARNING: region 1:
9455 00:40:39.367944 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9456 00:40:39.371989 WARNING: region 2:
9457 00:40:39.374833 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9458 00:40:39.378214 WARNING: region 3:
9459 00:40:39.381100 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9460 00:40:39.384605 WARNING: region 4:
9461 00:40:39.391487 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9462 00:40:39.391618 WARNING: region 5:
9463 00:40:39.394534 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9464 00:40:39.397780 WARNING: region 6:
9465 00:40:39.400970 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9466 00:40:39.404209 WARNING: region 7:
9467 00:40:39.407734 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9468 00:40:39.414283 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9469 00:40:39.417663 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9470 00:40:39.424256 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9471 00:40:39.427405 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9472 00:40:39.430699 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9473 00:40:39.437858 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9474 00:40:39.441037 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9475 00:40:39.444725 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9476 00:40:39.450757 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9477 00:40:39.454052 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9478 00:40:39.460930 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9479 00:40:39.463773 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9480 00:40:39.467289 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9481 00:40:39.473561 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9482 00:40:39.477359 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9483 00:40:39.481084 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9484 00:40:39.487269 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9485 00:40:39.491137 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9486 00:40:39.496845 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9487 00:40:39.500151 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9488 00:40:39.507209 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9489 00:40:39.510252 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9490 00:40:39.513334 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9491 00:40:39.520261 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9492 00:40:39.523670 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9493 00:40:39.529990 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9494 00:40:39.533230 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9495 00:40:39.536404 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9496 00:40:39.542960 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9497 00:40:39.546781 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9498 00:40:39.553255 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9499 00:40:39.556112 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9500 00:40:39.559937 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9501 00:40:39.562737 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9502 00:40:39.569534 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9503 00:40:39.572519 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9504 00:40:39.575758 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9505 00:40:39.582640 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9506 00:40:39.585866 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9507 00:40:39.589097 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9508 00:40:39.592496 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9509 00:40:39.598767 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9510 00:40:39.602163 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9511 00:40:39.606085 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9512 00:40:39.608987 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9513 00:40:39.615344 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9514 00:40:39.619128 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9515 00:40:39.621711 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9516 00:40:39.629157 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9517 00:40:39.631862 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9518 00:40:39.638188 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9519 00:40:39.641770 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9520 00:40:39.645170 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9521 00:40:39.651793 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9522 00:40:39.655194 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9523 00:40:39.661581 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9524 00:40:39.664849 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9525 00:40:39.671448 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9526 00:40:39.674891 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9527 00:40:39.681159 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9528 00:40:39.684730 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9529 00:40:39.688174 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9530 00:40:39.695827 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9531 00:40:39.697811 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9532 00:40:39.704570 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9533 00:40:39.708209 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9534 00:40:39.714661 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9535 00:40:39.717915 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9536 00:40:39.724454 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9537 00:40:39.727618 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9538 00:40:39.731428 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9539 00:40:39.737663 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9540 00:40:39.741977 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9541 00:40:39.747895 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9542 00:40:39.751164 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9543 00:40:39.757389 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9544 00:40:39.760751 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9545 00:40:39.767448 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9546 00:40:39.770847 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9547 00:40:39.774118 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9548 00:40:39.780924 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9549 00:40:39.783962 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9550 00:40:39.791107 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9551 00:40:39.793874 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9552 00:40:39.800566 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9553 00:40:39.803732 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9554 00:40:39.810868 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9555 00:40:39.813894 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9556 00:40:39.817014 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9557 00:40:39.824286 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9558 00:40:39.826763 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9559 00:40:39.834305 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9560 00:40:39.836751 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9561 00:40:39.843654 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9562 00:40:39.846710 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9563 00:40:39.853191 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9564 00:40:39.856549 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9565 00:40:39.859795 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9566 00:40:39.863040 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9567 00:40:39.869726 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9568 00:40:39.873453 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9569 00:40:39.876495 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9570 00:40:39.883113 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9571 00:40:39.886385 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9572 00:40:39.892942 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9573 00:40:39.896988 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9574 00:40:39.899507 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9575 00:40:39.905983 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9576 00:40:39.909669 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9577 00:40:39.915978 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9578 00:40:39.919594 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9579 00:40:39.922526 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9580 00:40:39.929243 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9581 00:40:39.932384 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9582 00:40:39.938999 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9583 00:40:39.942347 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9584 00:40:39.945816 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9585 00:40:39.952690 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9586 00:40:39.955778 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9587 00:40:39.959273 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9588 00:40:39.962195 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9589 00:40:39.968573 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9590 00:40:39.972231 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9591 00:40:39.975652 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9592 00:40:39.981954 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9593 00:40:39.985289 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9594 00:40:39.988347 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9595 00:40:39.995149 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9596 00:40:39.998361 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9597 00:40:40.004857 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9598 00:40:40.008342 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9599 00:40:40.014859 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9600 00:40:40.017951 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9601 00:40:40.021838 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9602 00:40:40.027870 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9603 00:40:40.031467 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9604 00:40:40.037964 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9605 00:40:40.041003 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9606 00:40:40.044574 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9607 00:40:40.051644 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9608 00:40:40.054221 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9609 00:40:40.060890 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9610 00:40:40.064528 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9611 00:40:40.067350 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9612 00:40:40.073990 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9613 00:40:40.077380 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9614 00:40:40.084010 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9615 00:40:40.087829 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9616 00:40:40.090736 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9617 00:40:40.097364 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9618 00:40:40.101108 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9619 00:40:40.103946 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9620 00:40:40.110728 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9621 00:40:40.114277 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9622 00:40:40.120670 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9623 00:40:40.123819 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9624 00:40:40.130391 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9625 00:40:40.133377 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9626 00:40:40.136846 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9627 00:40:40.143728 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9628 00:40:40.146910 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9629 00:40:40.152986 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9630 00:40:40.156324 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9631 00:40:40.159669 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9632 00:40:40.166968 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9633 00:40:40.169894 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9634 00:40:40.176505 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9635 00:40:40.179751 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9636 00:40:40.183193 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9637 00:40:40.189659 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9638 00:40:40.192650 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9639 00:40:40.199233 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9640 00:40:40.202466 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9641 00:40:40.205739 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9642 00:40:40.212206 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9643 00:40:40.215757 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9644 00:40:40.222161 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9645 00:40:40.225712 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9646 00:40:40.229664 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9647 00:40:40.235865 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9648 00:40:40.238574 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9649 00:40:40.245185 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9650 00:40:40.248559 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9651 00:40:40.252219 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9652 00:40:40.258973 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9653 00:40:40.261848 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9654 00:40:40.268478 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9655 00:40:40.272743 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9656 00:40:40.275204 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9657 00:40:40.281570 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9658 00:40:40.285129 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9659 00:40:40.291987 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9660 00:40:40.294625 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9661 00:40:40.301585 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9662 00:40:40.304782 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9663 00:40:40.308198 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9664 00:40:40.314624 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9665 00:40:40.318055 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9666 00:40:40.324744 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9667 00:40:40.327702 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9668 00:40:40.334997 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9669 00:40:40.337614 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9670 00:40:40.340887 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9671 00:40:40.348223 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9672 00:40:40.350993 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9673 00:40:40.357751 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9674 00:40:40.360892 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9675 00:40:40.364878 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9676 00:40:40.371312 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9677 00:40:40.374352 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9678 00:40:40.381152 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9679 00:40:40.384649 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9680 00:40:40.391659 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9681 00:40:40.394217 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9682 00:40:40.397446 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9683 00:40:40.404225 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9684 00:40:40.407077 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9685 00:40:40.414011 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9686 00:40:40.416928 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9687 00:40:40.424202 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9688 00:40:40.427474 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9689 00:40:40.430589 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9690 00:40:40.437210 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9691 00:40:40.440484 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9692 00:40:40.447453 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9693 00:40:40.450050 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9694 00:40:40.457022 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9695 00:40:40.459948 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9696 00:40:40.463538 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9697 00:40:40.469955 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9698 00:40:40.473637 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9699 00:40:40.476910 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9700 00:40:40.480113 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9701 00:40:40.483160 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9702 00:40:40.489950 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9703 00:40:40.493252 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9704 00:40:40.499970 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9705 00:40:40.503089 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9706 00:40:40.506705 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9707 00:40:40.513286 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9708 00:40:40.516033 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9709 00:40:40.522518 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9710 00:40:40.526637 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9711 00:40:40.529628 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9712 00:40:40.535865 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9713 00:40:40.539110 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9714 00:40:40.545775 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9715 00:40:40.548875 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9716 00:40:40.552383 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9717 00:40:40.558542 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9718 00:40:40.561999 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9719 00:40:40.565567 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9720 00:40:40.572426 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9721 00:40:40.575268 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9722 00:40:40.578539 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9723 00:40:40.585576 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9724 00:40:40.588589 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9725 00:40:40.595075 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9726 00:40:40.598671 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9727 00:40:40.601812 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9728 00:40:40.608105 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9729 00:40:40.611923 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9730 00:40:40.618238 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9731 00:40:40.621980 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9732 00:40:40.624391 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9733 00:40:40.631348 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9734 00:40:40.634572 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9735 00:40:40.637709 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9736 00:40:40.644556 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9737 00:40:40.647533 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9738 00:40:40.651332 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9739 00:40:40.654528 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9740 00:40:40.661045 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9741 00:40:40.664554 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9742 00:40:40.667907 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9743 00:40:40.671344 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9744 00:40:40.677731 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9745 00:40:40.681136 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9746 00:40:40.684197 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9747 00:40:40.688015 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9748 00:40:40.693742 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9749 00:40:40.697361 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9750 00:40:40.700725 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9751 00:40:40.707168 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9752 00:40:40.710675 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9753 00:40:40.717065 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9754 00:40:40.720079 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9755 00:40:40.727158 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9756 00:40:40.730697 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9757 00:40:40.733701 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9758 00:40:40.740272 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9759 00:40:40.743151 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9760 00:40:40.749859 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9761 00:40:40.753351 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9762 00:40:40.759905 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9763 00:40:40.763699 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9764 00:40:40.766154 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9765 00:40:40.772743 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9766 00:40:40.776515 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9767 00:40:40.782589 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9768 00:40:40.785877 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9769 00:40:40.790215 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9770 00:40:40.795854 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9771 00:40:40.799049 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9772 00:40:40.805925 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9773 00:40:40.809174 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9774 00:40:40.816265 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9775 00:40:40.819038 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9776 00:40:40.822601 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9777 00:40:40.829189 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9778 00:40:40.831988 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9779 00:40:40.838849 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9780 00:40:40.841791 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9781 00:40:40.845309 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9782 00:40:40.851996 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9783 00:40:40.855379 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9784 00:40:40.861586 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9785 00:40:40.865239 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9786 00:40:40.871776 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9787 00:40:40.875088 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9788 00:40:40.878821 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9789 00:40:40.885167 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9790 00:40:40.888680 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9791 00:40:40.895293 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9792 00:40:40.898269 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9793 00:40:40.901371 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9794 00:40:40.908511 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9795 00:40:40.911297 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9796 00:40:40.917940 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9797 00:40:40.922051 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9798 00:40:40.928157 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9799 00:40:40.931720 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9800 00:40:40.934724 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9801 00:40:40.940785 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9802 00:40:40.945042 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9803 00:40:40.951204 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9804 00:40:40.954319 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9805 00:40:40.957536 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9806 00:40:40.964387 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9807 00:40:40.967204 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9808 00:40:40.974014 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9809 00:40:40.977367 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9810 00:40:40.984485 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9811 00:40:40.987416 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9812 00:40:40.990884 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9813 00:40:40.997001 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9814 00:40:41.000299 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9815 00:40:41.007091 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9816 00:40:41.010420 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9817 00:40:41.016856 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9818 00:40:41.020091 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9819 00:40:41.023271 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9820 00:40:41.030275 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9821 00:40:41.033627 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9822 00:40:41.039689 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9823 00:40:41.043352 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9824 00:40:41.049396 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9825 00:40:41.053096 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9826 00:40:41.056840 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9827 00:40:41.062868 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9828 00:40:41.065972 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9829 00:40:41.072557 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9830 00:40:41.076362 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9831 00:40:41.082534 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9832 00:40:41.086116 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9833 00:40:41.093008 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9834 00:40:41.096311 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9835 00:40:41.099510 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9836 00:40:41.105874 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9837 00:40:41.109124 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9838 00:40:41.115953 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9839 00:40:41.118955 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9840 00:40:41.125949 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9841 00:40:41.128656 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9842 00:40:41.135558 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9843 00:40:41.138904 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9844 00:40:41.142112 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9845 00:40:41.149092 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9846 00:40:41.152195 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9847 00:40:41.158527 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9848 00:40:41.161952 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9849 00:40:41.168763 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9850 00:40:41.171867 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9851 00:40:41.178312 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9852 00:40:41.182121 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9853 00:40:41.185042 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9854 00:40:41.192026 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9855 00:40:41.194903 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9856 00:40:41.201786 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9857 00:40:41.205206 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9858 00:40:41.211654 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9859 00:40:41.215015 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9860 00:40:41.221405 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9861 00:40:41.224777 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9862 00:40:41.228230 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9863 00:40:41.234273 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9864 00:40:41.237923 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9865 00:40:41.244752 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9866 00:40:41.248175 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9867 00:40:41.254386 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9868 00:40:41.257552 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9869 00:40:41.261212 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9870 00:40:41.267442 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9871 00:40:41.270914 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9872 00:40:41.277208 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9873 00:40:41.281076 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9874 00:40:41.287484 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9875 00:40:41.290583 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9876 00:40:41.297536 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9877 00:40:41.300996 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9878 00:40:41.307217 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9879 00:40:41.310440 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9880 00:40:41.317459 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9881 00:40:41.320043 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9882 00:40:41.326897 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9883 00:40:41.330253 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9884 00:40:41.337164 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9885 00:40:41.339966 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9886 00:40:41.346935 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9887 00:40:41.349857 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9888 00:40:41.356971 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9889 00:40:41.359612 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9890 00:40:41.366735 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9891 00:40:41.369585 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9892 00:40:41.376222 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9893 00:40:41.379602 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9894 00:40:41.386159 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9895 00:40:41.389580 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9896 00:40:41.396058 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9897 00:40:41.399318 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9898 00:40:41.406017 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9899 00:40:41.409212 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9900 00:40:41.415947 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9901 00:40:41.419577 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9902 00:40:41.422837 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9903 00:40:41.425898 INFO: [APUAPC] vio 0
9904 00:40:41.432691 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9905 00:40:41.435729 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9906 00:40:41.439542 INFO: [APUAPC] D0_APC_0: 0x400510
9907 00:40:41.442297 INFO: [APUAPC] D0_APC_1: 0x0
9908 00:40:41.445571 INFO: [APUAPC] D0_APC_2: 0x1540
9909 00:40:41.448715 INFO: [APUAPC] D0_APC_3: 0x0
9910 00:40:41.452212 INFO: [APUAPC] D1_APC_0: 0xffffffff
9911 00:40:41.455646 INFO: [APUAPC] D1_APC_1: 0xffffffff
9912 00:40:41.458859 INFO: [APUAPC] D1_APC_2: 0x3fffff
9913 00:40:41.462216 INFO: [APUAPC] D1_APC_3: 0x0
9914 00:40:41.465742 INFO: [APUAPC] D2_APC_0: 0xffffffff
9915 00:40:41.468412 INFO: [APUAPC] D2_APC_1: 0xffffffff
9916 00:40:41.472048 INFO: [APUAPC] D2_APC_2: 0x3fffff
9917 00:40:41.475424 INFO: [APUAPC] D2_APC_3: 0x0
9918 00:40:41.478482 INFO: [APUAPC] D3_APC_0: 0xffffffff
9919 00:40:41.482109 INFO: [APUAPC] D3_APC_1: 0xffffffff
9920 00:40:41.485393 INFO: [APUAPC] D3_APC_2: 0x3fffff
9921 00:40:41.485916 INFO: [APUAPC] D3_APC_3: 0x0
9922 00:40:41.491905 INFO: [APUAPC] D4_APC_0: 0xffffffff
9923 00:40:41.495295 INFO: [APUAPC] D4_APC_1: 0xffffffff
9924 00:40:41.498563 INFO: [APUAPC] D4_APC_2: 0x3fffff
9925 00:40:41.498982 INFO: [APUAPC] D4_APC_3: 0x0
9926 00:40:41.501813 INFO: [APUAPC] D5_APC_0: 0xffffffff
9927 00:40:41.505605 INFO: [APUAPC] D5_APC_1: 0xffffffff
9928 00:40:41.508569 INFO: [APUAPC] D5_APC_2: 0x3fffff
9929 00:40:41.511667 INFO: [APUAPC] D5_APC_3: 0x0
9930 00:40:41.514970 INFO: [APUAPC] D6_APC_0: 0xffffffff
9931 00:40:41.518526 INFO: [APUAPC] D6_APC_1: 0xffffffff
9932 00:40:41.521607 INFO: [APUAPC] D6_APC_2: 0x3fffff
9933 00:40:41.525105 INFO: [APUAPC] D6_APC_3: 0x0
9934 00:40:41.528363 INFO: [APUAPC] D7_APC_0: 0xffffffff
9935 00:40:41.531338 INFO: [APUAPC] D7_APC_1: 0xffffffff
9936 00:40:41.534437 INFO: [APUAPC] D7_APC_2: 0x3fffff
9937 00:40:41.538321 INFO: [APUAPC] D7_APC_3: 0x0
9938 00:40:41.541356 INFO: [APUAPC] D8_APC_0: 0xffffffff
9939 00:40:41.544666 INFO: [APUAPC] D8_APC_1: 0xffffffff
9940 00:40:41.548407 INFO: [APUAPC] D8_APC_2: 0x3fffff
9941 00:40:41.551417 INFO: [APUAPC] D8_APC_3: 0x0
9942 00:40:41.554683 INFO: [APUAPC] D9_APC_0: 0xffffffff
9943 00:40:41.557851 INFO: [APUAPC] D9_APC_1: 0xffffffff
9944 00:40:41.561227 INFO: [APUAPC] D9_APC_2: 0x3fffff
9945 00:40:41.564764 INFO: [APUAPC] D9_APC_3: 0x0
9946 00:40:41.568122 INFO: [APUAPC] D10_APC_0: 0xffffffff
9947 00:40:41.570983 INFO: [APUAPC] D10_APC_1: 0xffffffff
9948 00:40:41.574188 INFO: [APUAPC] D10_APC_2: 0x3fffff
9949 00:40:41.577415 INFO: [APUAPC] D10_APC_3: 0x0
9950 00:40:41.581025 INFO: [APUAPC] D11_APC_0: 0xffffffff
9951 00:40:41.584378 INFO: [APUAPC] D11_APC_1: 0xffffffff
9952 00:40:41.588409 INFO: [APUAPC] D11_APC_2: 0x3fffff
9953 00:40:41.591746 INFO: [APUAPC] D11_APC_3: 0x0
9954 00:40:41.594165 INFO: [APUAPC] D12_APC_0: 0xffffffff
9955 00:40:41.597643 INFO: [APUAPC] D12_APC_1: 0xffffffff
9956 00:40:41.600993 INFO: [APUAPC] D12_APC_2: 0x3fffff
9957 00:40:41.604101 INFO: [APUAPC] D12_APC_3: 0x0
9958 00:40:41.607533 INFO: [APUAPC] D13_APC_0: 0xffffffff
9959 00:40:41.611072 INFO: [APUAPC] D13_APC_1: 0xffffffff
9960 00:40:41.614660 INFO: [APUAPC] D13_APC_2: 0x3fffff
9961 00:40:41.617577 INFO: [APUAPC] D13_APC_3: 0x0
9962 00:40:41.621214 INFO: [APUAPC] D14_APC_0: 0xffffffff
9963 00:40:41.624487 INFO: [APUAPC] D14_APC_1: 0xffffffff
9964 00:40:41.627616 INFO: [APUAPC] D14_APC_2: 0x3fffff
9965 00:40:41.630235 INFO: [APUAPC] D14_APC_3: 0x0
9966 00:40:41.633950 INFO: [APUAPC] D15_APC_0: 0xffffffff
9967 00:40:41.637169 INFO: [APUAPC] D15_APC_1: 0xffffffff
9968 00:40:41.640405 INFO: [APUAPC] D15_APC_2: 0x3fffff
9969 00:40:41.643862 INFO: [APUAPC] D15_APC_3: 0x0
9970 00:40:41.647276 INFO: [APUAPC] APC_CON: 0x4
9971 00:40:41.650417 INFO: [NOCDAPC] D0_APC_0: 0x0
9972 00:40:41.653705 INFO: [NOCDAPC] D0_APC_1: 0x0
9973 00:40:41.656967 INFO: [NOCDAPC] D1_APC_0: 0x0
9974 00:40:41.660473 INFO: [NOCDAPC] D1_APC_1: 0xfff
9975 00:40:41.663571 INFO: [NOCDAPC] D2_APC_0: 0x0
9976 00:40:41.667365 INFO: [NOCDAPC] D2_APC_1: 0xfff
9977 00:40:41.667807 INFO: [NOCDAPC] D3_APC_0: 0x0
9978 00:40:41.670467 INFO: [NOCDAPC] D3_APC_1: 0xfff
9979 00:40:41.673746 INFO: [NOCDAPC] D4_APC_0: 0x0
9980 00:40:41.676928 INFO: [NOCDAPC] D4_APC_1: 0xfff
9981 00:40:41.680504 INFO: [NOCDAPC] D5_APC_0: 0x0
9982 00:40:41.683674 INFO: [NOCDAPC] D5_APC_1: 0xfff
9983 00:40:41.686730 INFO: [NOCDAPC] D6_APC_0: 0x0
9984 00:40:41.690794 INFO: [NOCDAPC] D6_APC_1: 0xfff
9985 00:40:41.693381 INFO: [NOCDAPC] D7_APC_0: 0x0
9986 00:40:41.696685 INFO: [NOCDAPC] D7_APC_1: 0xfff
9987 00:40:41.700462 INFO: [NOCDAPC] D8_APC_0: 0x0
9988 00:40:41.703080 INFO: [NOCDAPC] D8_APC_1: 0xfff
9989 00:40:41.703499 INFO: [NOCDAPC] D9_APC_0: 0x0
9990 00:40:41.706409 INFO: [NOCDAPC] D9_APC_1: 0xfff
9991 00:40:41.709729 INFO: [NOCDAPC] D10_APC_0: 0x0
9992 00:40:41.713318 INFO: [NOCDAPC] D10_APC_1: 0xfff
9993 00:40:41.716362 INFO: [NOCDAPC] D11_APC_0: 0x0
9994 00:40:41.719516 INFO: [NOCDAPC] D11_APC_1: 0xfff
9995 00:40:41.722843 INFO: [NOCDAPC] D12_APC_0: 0x0
9996 00:40:41.726995 INFO: [NOCDAPC] D12_APC_1: 0xfff
9997 00:40:41.729825 INFO: [NOCDAPC] D13_APC_0: 0x0
9998 00:40:41.733394 INFO: [NOCDAPC] D13_APC_1: 0xfff
9999 00:40:41.736732 INFO: [NOCDAPC] D14_APC_0: 0x0
10000 00:40:41.739653 INFO: [NOCDAPC] D14_APC_1: 0xfff
10001 00:40:41.742608 INFO: [NOCDAPC] D15_APC_0: 0x0
10002 00:40:41.746544 INFO: [NOCDAPC] D15_APC_1: 0xfff
10003 00:40:41.749490 INFO: [NOCDAPC] APC_CON: 0x4
10004 00:40:41.752961 INFO: [APUAPC] set_apusys_apc done
10005 00:40:41.756248 INFO: [DEVAPC] devapc_init done
10006 00:40:41.759082 INFO: GICv3 without legacy support detected.
10007 00:40:41.762708 INFO: ARM GICv3 driver initialized in EL3
10008 00:40:41.766116 INFO: Maximum SPI INTID supported: 639
10009 00:40:41.769524 INFO: BL31: Initializing runtime services
10010 00:40:41.775825 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10011 00:40:41.779220 INFO: SPM: enable CPC mode
10012 00:40:41.782570 INFO: mcdi ready for mcusys-off-idle and system suspend
10013 00:40:41.789027 INFO: BL31: Preparing for EL3 exit to normal world
10014 00:40:41.792575 INFO: Entry point address = 0x80000000
10015 00:40:41.795296 INFO: SPSR = 0x8
10016 00:40:41.799795
10017 00:40:41.800390
10018 00:40:41.800822
10019 00:40:41.802999 Starting depthcharge on Spherion...
10020 00:40:41.803552
10021 00:40:41.804044 Wipe memory regions:
10022 00:40:41.804547
10023 00:40:41.807245 end: 2.2.3 depthcharge-start (duration 00:00:19) [common]
10024 00:40:41.807866 start: 2.2.4 bootloader-commands (timeout 00:04:27) [common]
10025 00:40:41.808305 Setting prompt string to ['asurada:']
10026 00:40:41.808820 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:27)
10027 00:40:41.809707 [0x00000040000000, 0x00000054600000)
10028 00:40:41.928903
10029 00:40:41.929405 [0x00000054660000, 0x00000080000000)
10030 00:40:42.189445
10031 00:40:42.189963 [0x000000821a7280, 0x000000ffe64000)
10032 00:40:42.934151
10033 00:40:42.934287 [0x00000100000000, 0x00000240000000)
10034 00:40:44.824322
10035 00:40:44.827593 Initializing XHCI USB controller at 0x11200000.
10036 00:40:45.866085
10037 00:40:45.868893 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10038 00:40:45.868985
10039 00:40:45.869050
10040 00:40:45.869362 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10042 00:40:45.969668 asurada: tftpboot 192.168.201.1 14368371/tftp-deploy-8gvq5l49/kernel/image.itb 14368371/tftp-deploy-8gvq5l49/kernel/cmdline
10043 00:40:45.969799 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10044 00:40:45.969885 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:23)
10045 00:40:45.974190 tftpboot 192.168.201.1 14368371/tftp-deploy-8gvq5l49/kernel/image.ittp-deploy-8gvq5l49/kernel/cmdline
10046 00:40:45.974273
10047 00:40:45.974337 Waiting for link
10048 00:40:46.132403
10049 00:40:46.132529 R8152: Initializing
10050 00:40:46.132603
10051 00:40:46.135530 Version 6 (ocp_data = 5c30)
10052 00:40:46.135630
10053 00:40:46.139195 R8152: Done initializing
10054 00:40:46.139274
10055 00:40:46.139337 Adding net device
10056 00:40:48.013153
10057 00:40:48.013338 done.
10058 00:40:48.013406
10059 00:40:48.013473 MAC: 00:24:32:30:7c:7b
10060 00:40:48.013536
10061 00:40:48.016104 Sending DHCP discover... done.
10062 00:40:48.016182
10063 00:40:48.019960 Waiting for reply... done.
10064 00:40:48.020035
10065 00:40:48.022577 Sending DHCP request... done.
10066 00:40:48.022649
10067 00:40:48.026463 Waiting for reply... done.
10068 00:40:48.026538
10069 00:40:48.026602 My ip is 192.168.201.14
10070 00:40:48.026659
10071 00:40:48.029402 The DHCP server ip is 192.168.201.1
10072 00:40:48.029480
10073 00:40:48.036047 TFTP server IP predefined by user: 192.168.201.1
10074 00:40:48.036128
10075 00:40:48.042440 Bootfile predefined by user: 14368371/tftp-deploy-8gvq5l49/kernel/image.itb
10076 00:40:48.042515
10077 00:40:48.045658 Sending tftp read request... done.
10078 00:40:48.045739
10079 00:40:48.049416 Waiting for the transfer...
10080 00:40:48.049494
10081 00:40:48.579218 00000000 ################################################################
10082 00:40:48.579409
10083 00:40:49.102384 00080000 ################################################################
10084 00:40:49.102567
10085 00:40:49.625643 00100000 ################################################################
10086 00:40:49.625779
10087 00:40:50.164987 00180000 ################################################################
10088 00:40:50.165145
10089 00:40:50.697889 00200000 ################################################################
10090 00:40:50.698023
10091 00:40:51.241022 00280000 ################################################################
10092 00:40:51.241160
10093 00:40:51.768530 00300000 ################################################################
10094 00:40:51.768703
10095 00:40:52.295033 00380000 ################################################################
10096 00:40:52.295207
10097 00:40:52.819843 00400000 ################################################################
10098 00:40:52.820019
10099 00:40:53.348977 00480000 ################################################################
10100 00:40:53.349146
10101 00:40:53.892697 00500000 ################################################################
10102 00:40:53.892859
10103 00:40:54.428103 00580000 ################################################################
10104 00:40:54.428272
10105 00:40:54.955763 00600000 ################################################################
10106 00:40:54.955941
10107 00:40:55.481466 00680000 ################################################################
10108 00:40:55.481615
10109 00:40:56.003058 00700000 ################################################################
10110 00:40:56.003224
10111 00:40:56.530343 00780000 ################################################################
10112 00:40:56.530483
10113 00:40:57.062613 00800000 ################################################################
10114 00:40:57.062779
10115 00:40:57.589861 00880000 ################################################################
10116 00:40:57.590005
10117 00:40:58.128341 00900000 ################################################################
10118 00:40:58.128497
10119 00:40:58.647807 00980000 ################################################################
10120 00:40:58.647957
10121 00:40:59.179609 00a00000 ################################################################
10122 00:40:59.179745
10123 00:40:59.701861 00a80000 ################################################################
10124 00:40:59.702017
10125 00:41:00.231081 00b00000 ################################################################
10126 00:41:00.231213
10127 00:41:00.750646 00b80000 ################################################################
10128 00:41:00.750780
10129 00:41:01.274269 00c00000 ################################################################
10130 00:41:01.274406
10131 00:41:01.805721 00c80000 ################################################################
10132 00:41:01.805856
10133 00:41:02.352231 00d00000 ################################################################
10134 00:41:02.352381
10135 00:41:02.884362 00d80000 ################################################################
10136 00:41:02.884496
10137 00:41:03.411276 00e00000 ################################################################
10138 00:41:03.411447
10139 00:41:03.956626 00e80000 ################################################################
10140 00:41:03.956752
10141 00:41:04.599412 00f00000 ################################################################
10142 00:41:04.599912
10143 00:41:05.267314 00f80000 ################################################################
10144 00:41:05.267995
10145 00:41:05.940328 01000000 ################################################################
10146 00:41:05.940812
10147 00:41:06.568315 01080000 ################################################################
10148 00:41:06.568445
10149 00:41:07.142906 01100000 ################################################################
10150 00:41:07.143063
10151 00:41:07.704534 01180000 ################################################################
10152 00:41:07.704667
10153 00:41:08.302706 01200000 ################################################################
10154 00:41:08.302868
10155 00:41:08.882785 01280000 ################################################################
10156 00:41:08.882919
10157 00:41:09.483899 01300000 ################################################################
10158 00:41:09.484028
10159 00:41:10.049093 01380000 ################################################################
10160 00:41:10.049262
10161 00:41:10.583338 01400000 ################################################################
10162 00:41:10.583486
10163 00:41:11.153180 01480000 ################################################################
10164 00:41:11.153363
10165 00:41:11.722742 01500000 ################################################################
10166 00:41:11.722890
10167 00:41:12.347377 01580000 ################################################################
10168 00:41:12.347894
10169 00:41:13.016005 01600000 ################################################################
10170 00:41:13.016519
10171 00:41:13.602365 01680000 ################################################################
10172 00:41:13.602501
10173 00:41:14.191713 01700000 ################################################################
10174 00:41:14.191848
10175 00:41:14.884530 01780000 ################################################################
10176 00:41:14.884707
10177 00:41:15.550464 01800000 ################################################################
10178 00:41:15.550603
10179 00:41:16.126396 01880000 ################################################################
10180 00:41:16.126530
10181 00:41:16.685701 01900000 ################################################################
10182 00:41:16.685837
10183 00:41:17.256896 01980000 ################################################################
10184 00:41:17.257032
10185 00:41:17.806049 01a00000 ################################################################
10186 00:41:17.806210
10187 00:41:18.377781 01a80000 ################################################################
10188 00:41:18.377918
10189 00:41:18.968396 01b00000 ################################################################
10190 00:41:18.968546
10191 00:41:19.523827 01b80000 ################################################################
10192 00:41:19.523984
10193 00:41:20.075082 01c00000 ################################################################
10194 00:41:20.075214
10195 00:41:20.636786 01c80000 ################################################################
10196 00:41:20.636994
10197 00:41:21.178565 01d00000 ################################################################
10198 00:41:21.178697
10199 00:41:21.712646 01d80000 ################################################################
10200 00:41:21.712784
10201 00:41:22.169118 01e00000 ####################################################### done.
10202 00:41:22.169286
10203 00:41:22.172189 The bootfile was 31902546 bytes long.
10204 00:41:22.175377
10205 00:41:22.175488 Sending tftp read request... done.
10206 00:41:22.175581
10207 00:41:22.178758 Waiting for the transfer...
10208 00:41:22.178872
10209 00:41:22.182489 00000000 # done.
10210 00:41:22.182594
10211 00:41:22.188831 Command line loaded dynamically from TFTP file: 14368371/tftp-deploy-8gvq5l49/kernel/cmdline
10212 00:41:22.188956
10213 00:41:22.211611 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14368371/extract-nfsrootfs-u2n90c2q,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10214 00:41:22.211709
10215 00:41:22.211774 Loading FIT.
10216 00:41:22.211835
10217 00:41:22.214772 Image ramdisk-1 has 18726880 bytes.
10218 00:41:22.214855
10219 00:41:22.218170 Image fdt-1 has 47258 bytes.
10220 00:41:22.218251
10221 00:41:22.221395 Image kernel-1 has 13126376 bytes.
10222 00:41:22.221477
10223 00:41:22.231275 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10224 00:41:22.231357
10225 00:41:22.247642 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10226 00:41:22.247733
10227 00:41:22.254211 Choosing best match conf-1 for compat google,spherion-rev2.
10228 00:41:22.254319
10229 00:41:22.262184 Connected to device vid:did:rid of 1ae0:0028:00
10230 00:41:22.269840
10231 00:41:22.273739 tpm_get_response: command 0x17b, return code 0x0
10232 00:41:22.273821
10233 00:41:22.279816 ec_init: CrosEC protocol v3 supported (256, 248)
10234 00:41:22.279903
10235 00:41:22.283291 tpm_cleanup: add release locality here.
10236 00:41:22.283373
10237 00:41:22.286551 Shutting down all USB controllers.
10238 00:41:22.286633
10239 00:41:22.289710 Removing current net device
10240 00:41:22.289785
10241 00:41:22.296711 Exiting depthcharge with code 4 at timestamp: 69704845
10242 00:41:22.296812
10243 00:41:22.300104 LZMA decompressing kernel-1 to 0x821a6718
10244 00:41:22.300204
10245 00:41:22.302960 LZMA decompressing kernel-1 to 0x40000000
10246 00:41:23.920179
10247 00:41:23.920772 jumping to kernel
10248 00:41:23.922769 end: 2.2.4 bootloader-commands (duration 00:00:42) [common]
10249 00:41:23.923302 start: 2.2.5 auto-login-action (timeout 00:03:45) [common]
10250 00:41:23.923680 Setting prompt string to ['Linux version [0-9]']
10251 00:41:23.924031 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10252 00:41:23.924380 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10253 00:41:24.002952
10254 00:41:24.006113 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10255 00:41:24.009840 start: 2.2.5.1 login-action (timeout 00:03:45) [common]
10256 00:41:24.010336 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10257 00:41:24.010701 Setting prompt string to []
10258 00:41:24.011071 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10259 00:41:24.011419 Using line separator: #'\n'#
10260 00:41:24.011717 No login prompt set.
10261 00:41:24.012024 Parsing kernel messages
10262 00:41:24.012304 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10263 00:41:24.012832 [login-action] Waiting for messages, (timeout 00:03:44)
10264 00:41:24.013183 Waiting using forced prompt support (timeout 00:01:52)
10265 00:41:24.028899 [ 0.000000] Linux version 6.1.92-cip22 (KernelCI@build-j232175-arm64-gcc-10-defconfig-arm64-chromebook-7lg8d) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sun Jun 16 00:28:47 UTC 2024
10266 00:41:24.032387 [ 0.000000] random: crng init done
10267 00:41:24.038813 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10268 00:41:24.041984 [ 0.000000] efi: UEFI not found.
10269 00:41:24.048666 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10270 00:41:24.058452 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10271 00:41:24.065333 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10272 00:41:24.075093 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10273 00:41:24.081809 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10274 00:41:24.088429 [ 0.000000] printk: bootconsole [mtk8250] enabled
10275 00:41:24.095189 [ 0.000000] NUMA: No NUMA configuration found
10276 00:41:24.101671 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10277 00:41:24.105247 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10278 00:41:24.108402 [ 0.000000] Zone ranges:
10279 00:41:24.115123 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10280 00:41:24.118112 [ 0.000000] DMA32 empty
10281 00:41:24.124976 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10282 00:41:24.128307 [ 0.000000] Movable zone start for each node
10283 00:41:24.131585 [ 0.000000] Early memory node ranges
10284 00:41:24.138222 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10285 00:41:24.144423 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10286 00:41:24.151674 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10287 00:41:24.158292 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10288 00:41:24.161412 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10289 00:41:24.171041 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10290 00:41:24.226863 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10291 00:41:24.234265 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10292 00:41:24.240279 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10293 00:41:24.243996 [ 0.000000] psci: probing for conduit method from DT.
10294 00:41:24.250578 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10295 00:41:24.253211 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10296 00:41:24.259684 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10297 00:41:24.262960 [ 0.000000] psci: SMC Calling Convention v1.2
10298 00:41:24.269948 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10299 00:41:24.272947 [ 0.000000] Detected VIPT I-cache on CPU0
10300 00:41:24.279597 [ 0.000000] CPU features: detected: GIC system register CPU interface
10301 00:41:24.286680 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10302 00:41:24.292607 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10303 00:41:24.299796 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10304 00:41:24.309174 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10305 00:41:24.315789 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10306 00:41:24.319495 [ 0.000000] alternatives: applying boot alternatives
10307 00:41:24.325983 [ 0.000000] Fallback order for Node 0: 0
10308 00:41:24.332622 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10309 00:41:24.336013 [ 0.000000] Policy zone: Normal
10310 00:41:24.359132 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14368371/extract-nfsrootfs-u2n90c2q,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10311 00:41:24.369064 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10312 00:41:24.380610 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10313 00:41:24.389955 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10314 00:41:24.396709 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10315 00:41:24.399726 <6>[ 0.000000] software IO TLB: area num 8.
10316 00:41:24.456673 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10317 00:41:24.606514 <6>[ 0.000000] Memory: 7945772K/8385536K available (18112K kernel code, 4120K rwdata, 22644K rodata, 8512K init, 616K bss, 406996K reserved, 32768K cma-reserved)
10318 00:41:24.612834 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10319 00:41:24.619305 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10320 00:41:24.622408 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10321 00:41:24.629582 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10322 00:41:24.635876 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10323 00:41:24.638904 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10324 00:41:24.649084 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10325 00:41:24.655869 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10326 00:41:24.662411 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10327 00:41:24.668968 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10328 00:41:24.672312 <6>[ 0.000000] GICv3: 608 SPIs implemented
10329 00:41:24.675793 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10330 00:41:24.682452 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10331 00:41:24.685399 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10332 00:41:24.692593 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10333 00:41:24.705534 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10334 00:41:24.718274 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10335 00:41:24.725340 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10336 00:41:24.732532 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10337 00:41:24.746214 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10338 00:41:24.752608 <6>[ 0.000001] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10339 00:41:24.759599 <6>[ 0.009234] Console: colour dummy device 80x25
10340 00:41:24.769413 <6>[ 0.013953] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10341 00:41:24.775710 <6>[ 0.024394] pid_max: default: 32768 minimum: 301
10342 00:41:24.778826 <6>[ 0.029265] LSM: Security Framework initializing
10343 00:41:24.786139 <6>[ 0.034203] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10344 00:41:24.795577 <6>[ 0.042066] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10345 00:41:24.802451 <6>[ 0.051485] cblist_init_generic: Setting adjustable number of callback queues.
10346 00:41:24.808753 <6>[ 0.058929] cblist_init_generic: Setting shift to 3 and lim to 1.
10347 00:41:24.818845 <6>[ 0.065268] cblist_init_generic: Setting adjustable number of callback queues.
10348 00:41:24.825186 <6>[ 0.072695] cblist_init_generic: Setting shift to 3 and lim to 1.
10349 00:41:24.828662 <6>[ 0.079096] rcu: Hierarchical SRCU implementation.
10350 00:41:24.835664 <6>[ 0.084111] rcu: Max phase no-delay instances is 1000.
10351 00:41:24.842644 <6>[ 0.091177] EFI services will not be available.
10352 00:41:24.845137 <6>[ 0.096163] smp: Bringing up secondary CPUs ...
10353 00:41:24.853710 <6>[ 0.101214] Detected VIPT I-cache on CPU1
10354 00:41:24.860371 <6>[ 0.101287] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10355 00:41:24.866681 <6>[ 0.101318] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10356 00:41:24.870236 <6>[ 0.101655] Detected VIPT I-cache on CPU2
10357 00:41:24.876802 <6>[ 0.101707] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10358 00:41:24.886589 <6>[ 0.101725] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10359 00:41:24.890295 <6>[ 0.101983] Detected VIPT I-cache on CPU3
10360 00:41:24.896836 <6>[ 0.102030] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10361 00:41:24.903276 <6>[ 0.102044] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10362 00:41:24.906317 <6>[ 0.102349] CPU features: detected: Spectre-v4
10363 00:41:24.913492 <6>[ 0.102355] CPU features: detected: Spectre-BHB
10364 00:41:24.916174 <6>[ 0.102360] Detected PIPT I-cache on CPU4
10365 00:41:24.922568 <6>[ 0.102419] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10366 00:41:24.929580 <6>[ 0.102435] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10367 00:41:24.935893 <6>[ 0.102727] Detected PIPT I-cache on CPU5
10368 00:41:24.942300 <6>[ 0.102791] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10369 00:41:24.949448 <6>[ 0.102807] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10370 00:41:24.952256 <6>[ 0.103087] Detected PIPT I-cache on CPU6
10371 00:41:24.958931 <6>[ 0.103152] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10372 00:41:24.969127 <6>[ 0.103168] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10373 00:41:24.972193 <6>[ 0.103464] Detected PIPT I-cache on CPU7
10374 00:41:24.978836 <6>[ 0.103530] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10375 00:41:24.985598 <6>[ 0.103546] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10376 00:41:24.988558 <6>[ 0.103593] smp: Brought up 1 node, 8 CPUs
10377 00:41:24.995471 <6>[ 0.244888] SMP: Total of 8 processors activated.
10378 00:41:24.998866 <6>[ 0.249809] CPU features: detected: 32-bit EL0 Support
10379 00:41:25.008897 <6>[ 0.255173] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10380 00:41:25.015118 <6>[ 0.263973] CPU features: detected: Common not Private translations
10381 00:41:25.021660 <6>[ 0.270449] CPU features: detected: CRC32 instructions
10382 00:41:25.028669 <6>[ 0.275800] CPU features: detected: RCpc load-acquire (LDAPR)
10383 00:41:25.031698 <6>[ 0.281760] CPU features: detected: LSE atomic instructions
10384 00:41:25.038111 <6>[ 0.287541] CPU features: detected: Privileged Access Never
10385 00:41:25.044392 <6>[ 0.293321] CPU features: detected: RAS Extension Support
10386 00:41:25.051729 <6>[ 0.298929] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10387 00:41:25.053890 <6>[ 0.306147] CPU: All CPU(s) started at EL2
10388 00:41:25.060322 <6>[ 0.310464] alternatives: applying system-wide alternatives
10389 00:41:25.070961 <6>[ 0.321314] devtmpfs: initialized
10390 00:41:25.086247 <6>[ 0.330188] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10391 00:41:25.092923 <6>[ 0.340146] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10392 00:41:25.099212 <6>[ 0.348185] pinctrl core: initialized pinctrl subsystem
10393 00:41:25.103013 <6>[ 0.354870] DMI not present or invalid.
10394 00:41:25.109174 <6>[ 0.359281] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10395 00:41:25.119077 <6>[ 0.366048] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10396 00:41:25.125758 <6>[ 0.373635] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10397 00:41:25.136058 <6>[ 0.381854] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10398 00:41:25.138778 <6>[ 0.390099] audit: initializing netlink subsys (disabled)
10399 00:41:25.148899 <5>[ 0.395788] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10400 00:41:25.155397 <6>[ 0.396505] thermal_sys: Registered thermal governor 'step_wise'
10401 00:41:25.161937 <6>[ 0.403752] thermal_sys: Registered thermal governor 'power_allocator'
10402 00:41:25.165306 <6>[ 0.410007] cpuidle: using governor menu
10403 00:41:25.172369 <6>[ 0.420966] NET: Registered PF_QIPCRTR protocol family
10404 00:41:25.178864 <6>[ 0.426451] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10405 00:41:25.185171 <6>[ 0.433553] ASID allocator initialised with 32768 entries
10406 00:41:25.189365 <6>[ 0.440134] Serial: AMBA PL011 UART driver
10407 00:41:25.198951 <4>[ 0.448972] Trying to register duplicate clock ID: 134
10408 00:41:25.257135 <6>[ 0.510651] KASLR enabled
10409 00:41:25.271288 <6>[ 0.518351] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10410 00:41:25.278186 <6>[ 0.525366] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10411 00:41:25.284494 <6>[ 0.531857] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10412 00:41:25.291651 <6>[ 0.538862] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10413 00:41:25.297696 <6>[ 0.545351] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10414 00:41:25.304777 <6>[ 0.552357] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10415 00:41:25.310802 <6>[ 0.558844] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10416 00:41:25.316976 <6>[ 0.565851] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10417 00:41:25.320545 <6>[ 0.573365] ACPI: Interpreter disabled.
10418 00:41:25.329838 <6>[ 0.579813] iommu: Default domain type: Translated
10419 00:41:25.335777 <6>[ 0.584926] iommu: DMA domain TLB invalidation policy: strict mode
10420 00:41:25.339212 <5>[ 0.591590] SCSI subsystem initialized
10421 00:41:25.345845 <6>[ 0.595758] usbcore: registered new interface driver usbfs
10422 00:41:25.353368 <6>[ 0.601490] usbcore: registered new interface driver hub
10423 00:41:25.355922 <6>[ 0.607041] usbcore: registered new device driver usb
10424 00:41:25.363086 <6>[ 0.613142] pps_core: LinuxPPS API ver. 1 registered
10425 00:41:25.372649 <6>[ 0.618336] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10426 00:41:25.376070 <6>[ 0.627683] PTP clock support registered
10427 00:41:25.379216 <6>[ 0.631929] EDAC MC: Ver: 3.0.0
10428 00:41:25.386755 <6>[ 0.637084] FPGA manager framework
10429 00:41:25.393117 <6>[ 0.640769] Advanced Linux Sound Architecture Driver Initialized.
10430 00:41:25.396410 <6>[ 0.647540] vgaarb: loaded
10431 00:41:25.402903 <6>[ 0.650636] clocksource: Switched to clocksource arch_sys_counter
10432 00:41:25.406344 <5>[ 0.657072] VFS: Disk quotas dquot_6.6.0
10433 00:41:25.412796 <6>[ 0.661260] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10434 00:41:25.416300 <6>[ 0.668448] pnp: PnP ACPI: disabled
10435 00:41:25.424447 <6>[ 0.675172] NET: Registered PF_INET protocol family
10436 00:41:25.434337 <6>[ 0.680770] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10437 00:41:25.445894 <6>[ 0.693093] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10438 00:41:25.455684 <6>[ 0.701907] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10439 00:41:25.462678 <6>[ 0.709880] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10440 00:41:25.472023 <6>[ 0.718582] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10441 00:41:25.479309 <6>[ 0.728336] TCP: Hash tables configured (established 65536 bind 65536)
10442 00:41:25.485301 <6>[ 0.735199] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10443 00:41:25.495048 <6>[ 0.742397] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10444 00:41:25.501870 <6>[ 0.750098] NET: Registered PF_UNIX/PF_LOCAL protocol family
10445 00:41:25.508420 <6>[ 0.756255] RPC: Registered named UNIX socket transport module.
10446 00:41:25.511846 <6>[ 0.762407] RPC: Registered udp transport module.
10447 00:41:25.518092 <6>[ 0.767340] RPC: Registered tcp transport module.
10448 00:41:25.524963 <6>[ 0.772270] RPC: Registered tcp NFSv4.1 backchannel transport module.
10449 00:41:25.528409 <6>[ 0.778937] PCI: CLS 0 bytes, default 64
10450 00:41:25.531720 <6>[ 0.783270] Unpacking initramfs...
10451 00:41:25.555791 <6>[ 0.802758] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10452 00:41:25.565241 <6>[ 0.811411] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10453 00:41:25.568683 <6>[ 0.820253] kvm [1]: IPA Size Limit: 40 bits
10454 00:41:25.575392 <6>[ 0.824779] kvm [1]: GICv3: no GICV resource entry
10455 00:41:25.578685 <6>[ 0.829803] kvm [1]: disabling GICv2 emulation
10456 00:41:25.584984 <6>[ 0.834491] kvm [1]: GIC system register CPU interface enabled
10457 00:41:25.588576 <6>[ 0.840665] kvm [1]: vgic interrupt IRQ18
10458 00:41:25.595182 <6>[ 0.845032] kvm [1]: VHE mode initialized successfully
10459 00:41:25.601668 <5>[ 0.851535] Initialise system trusted keyrings
10460 00:41:25.608551 <6>[ 0.856401] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10461 00:41:25.615890 <6>[ 0.866385] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10462 00:41:25.622374 <5>[ 0.872761] NFS: Registering the id_resolver key type
10463 00:41:25.626424 <5>[ 0.878061] Key type id_resolver registered
10464 00:41:25.632815 <5>[ 0.882474] Key type id_legacy registered
10465 00:41:25.639219 <6>[ 0.886754] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10466 00:41:25.646168 <6>[ 0.893676] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10467 00:41:25.652433 <6>[ 0.901403] 9p: Installing v9fs 9p2000 file system support
10468 00:41:25.689053 <5>[ 0.939183] Key type asymmetric registered
10469 00:41:25.692453 <5>[ 0.943515] Asymmetric key parser 'x509' registered
10470 00:41:25.702138 <6>[ 0.948704] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10471 00:41:25.704914 <6>[ 0.956331] io scheduler mq-deadline registered
10472 00:41:25.708235 <6>[ 0.961097] io scheduler kyber registered
10473 00:41:25.727905 <6>[ 0.978102] EINJ: ACPI disabled.
10474 00:41:25.760297 <4>[ 1.004262] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10475 00:41:25.770225 <4>[ 1.014904] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10476 00:41:25.785419 <6>[ 1.036049] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10477 00:41:25.794027 <6>[ 1.044083] printk: console [ttyS0] disabled
10478 00:41:25.822221 <6>[ 1.068715] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10479 00:41:25.828101 <6>[ 1.078191] printk: console [ttyS0] enabled
10480 00:41:25.831603 <6>[ 1.078191] printk: console [ttyS0] enabled
10481 00:41:25.838026 <6>[ 1.087091] printk: bootconsole [mtk8250] disabled
10482 00:41:25.841571 <6>[ 1.087091] printk: bootconsole [mtk8250] disabled
10483 00:41:25.847689 <6>[ 1.098302] SuperH (H)SCI(F) driver initialized
10484 00:41:25.851462 <6>[ 1.103580] msm_serial: driver initialized
10485 00:41:25.865495 <6>[ 1.112526] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10486 00:41:25.874958 <6>[ 1.121072] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10487 00:41:25.881823 <6>[ 1.129615] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10488 00:41:25.891633 <6>[ 1.138241] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10489 00:41:25.901818 <6>[ 1.146948] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10490 00:41:25.908290 <6>[ 1.155661] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10491 00:41:25.919147 <6>[ 1.164208] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10492 00:41:25.925390 <6>[ 1.173018] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10493 00:41:25.934700 <6>[ 1.181560] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10494 00:41:25.946793 <6>[ 1.197243] loop: module loaded
10495 00:41:25.953446 <6>[ 1.203219] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10496 00:41:25.976059 <4>[ 1.226511] mtk-pmic-keys: Failed to locate of_node [id: -1]
10497 00:41:25.983052 <6>[ 1.233350] megasas: 07.719.03.00-rc1
10498 00:41:25.992255 <6>[ 1.243003] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10499 00:41:26.003759 <6>[ 1.254010] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10500 00:41:26.019857 <6>[ 1.270565] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10501 00:41:26.075569 <6>[ 1.319776] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9
10502 00:41:26.327348 <6>[ 1.577787] Freeing initrd memory: 18284K
10503 00:41:26.338803 <6>[ 1.589366] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10504 00:41:26.349942 <6>[ 1.600289] tun: Universal TUN/TAP device driver, 1.6
10505 00:41:26.354091 <6>[ 1.606335] thunder_xcv, ver 1.0
10506 00:41:26.356653 <6>[ 1.609843] thunder_bgx, ver 1.0
10507 00:41:26.359914 <6>[ 1.613341] nicpf, ver 1.0
10508 00:41:26.370142 <6>[ 1.617374] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10509 00:41:26.373296 <6>[ 1.624850] hns3: Copyright (c) 2017 Huawei Corporation.
10510 00:41:26.376742 <6>[ 1.630441] hclge is initializing
10511 00:41:26.383528 <6>[ 1.634016] e1000: Intel(R) PRO/1000 Network Driver
10512 00:41:26.390458 <6>[ 1.639144] e1000: Copyright (c) 1999-2006 Intel Corporation.
10513 00:41:26.393447 <6>[ 1.645158] e1000e: Intel(R) PRO/1000 Network Driver
10514 00:41:26.399878 <6>[ 1.650373] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10515 00:41:26.406739 <6>[ 1.656559] igb: Intel(R) Gigabit Ethernet Network Driver
10516 00:41:26.413586 <6>[ 1.662209] igb: Copyright (c) 2007-2014 Intel Corporation.
10517 00:41:26.419775 <6>[ 1.668050] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10518 00:41:26.426606 <6>[ 1.674568] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10519 00:41:26.429966 <6>[ 1.681026] sky2: driver version 1.30
10520 00:41:26.436493 <6>[ 1.685959] usbcore: registered new device driver r8152-cfgselector
10521 00:41:26.442915 <6>[ 1.692494] usbcore: registered new interface driver r8152
10522 00:41:26.449581 <6>[ 1.698310] VFIO - User Level meta-driver version: 0.3
10523 00:41:26.456496 <6>[ 1.706530] usbcore: registered new interface driver usb-storage
10524 00:41:26.463213 <6>[ 1.712975] usbcore: registered new device driver onboard-usb-hub
10525 00:41:26.471560 <6>[ 1.722172] mt6397-rtc mt6359-rtc: registered as rtc0
10526 00:41:26.482042 <6>[ 1.727639] mt6397-rtc mt6359-rtc: setting system clock to 2024-06-16T00:41:25 UTC (1718498485)
10527 00:41:26.485342 <6>[ 1.737210] i2c_dev: i2c /dev entries driver
10528 00:41:26.498963 <4>[ 1.749308] cpu cpu0: supply cpu not found, using dummy regulator
10529 00:41:26.506005 <4>[ 1.755745] cpu cpu1: supply cpu not found, using dummy regulator
10530 00:41:26.512321 <4>[ 1.762148] cpu cpu2: supply cpu not found, using dummy regulator
10531 00:41:26.519339 <4>[ 1.768568] cpu cpu3: supply cpu not found, using dummy regulator
10532 00:41:26.525669 <4>[ 1.774967] cpu cpu4: supply cpu not found, using dummy regulator
10533 00:41:26.533339 <4>[ 1.781366] cpu cpu5: supply cpu not found, using dummy regulator
10534 00:41:26.539487 <4>[ 1.787764] cpu cpu6: supply cpu not found, using dummy regulator
10535 00:41:26.545743 <4>[ 1.794163] cpu cpu7: supply cpu not found, using dummy regulator
10536 00:41:26.564741 <6>[ 1.814820] cpu cpu0: EM: created perf domain
10537 00:41:26.568174 <6>[ 1.819764] cpu cpu4: EM: created perf domain
10538 00:41:26.575525 <6>[ 1.825385] sdhci: Secure Digital Host Controller Interface driver
10539 00:41:26.582043 <6>[ 1.831818] sdhci: Copyright(c) Pierre Ossman
10540 00:41:26.588649 <6>[ 1.836775] Synopsys Designware Multimedia Card Interface Driver
10541 00:41:26.595313 <6>[ 1.843418] sdhci-pltfm: SDHCI platform and OF driver helper
10542 00:41:26.598204 <6>[ 1.843473] mmc0: CQHCI version 5.10
10543 00:41:26.605356 <6>[ 1.853523] ledtrig-cpu: registered to indicate activity on CPUs
10544 00:41:26.611759 <6>[ 1.860578] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10545 00:41:26.618437 <6>[ 1.867634] usbcore: registered new interface driver usbhid
10546 00:41:26.621644 <6>[ 1.873466] usbhid: USB HID core driver
10547 00:41:26.628661 <6>[ 1.877658] spi_master spi0: will run message pump with realtime priority
10548 00:41:26.677779 <6>[ 1.921146] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10549 00:41:26.696903 <6>[ 1.936817] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10550 00:41:26.700818 <6>[ 1.948541] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x15814
10551 00:41:26.707597 <6>[ 1.951581] cros-ec-spi spi0.0: Chrome EC device registered
10552 00:41:26.710570 <6>[ 1.962243] mmc0: Command Queue Engine enabled
10553 00:41:26.716755 <6>[ 1.967026] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10554 00:41:26.724164 <6>[ 1.974422] mmcblk0: mmc0:0001 DA4128 116 GiB
10555 00:41:26.734090 <6>[ 1.975897] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10556 00:41:26.740981 <6>[ 1.983003] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10557 00:41:26.743926 <6>[ 1.989501] NET: Registered PF_PACKET protocol family
10558 00:41:26.750265 <6>[ 1.995782] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10559 00:41:26.753720 <6>[ 1.999742] 9pnet: Installing 9P2000 support
10560 00:41:26.760535 <6>[ 2.005572] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10561 00:41:26.763867 <5>[ 2.009440] Key type dns_resolver registered
10562 00:41:26.770089 <6>[ 2.015314] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10563 00:41:26.773250 <6>[ 2.019706] registered taskstats version 1
10564 00:41:26.780103 <5>[ 2.030052] Loading compiled-in X.509 certificates
10565 00:41:26.808062 <4>[ 2.052211] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10566 00:41:26.818101 <4>[ 2.063000] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10567 00:41:26.836418 <6>[ 2.086431] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10568 00:41:26.842568 <6>[ 2.093303] xhci-mtk 11200000.usb: xHCI Host Controller
10569 00:41:26.849469 <6>[ 2.098813] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10570 00:41:26.859472 <6>[ 2.106686] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10571 00:41:26.866296 <6>[ 2.116133] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10572 00:41:26.872745 <6>[ 2.122238] xhci-mtk 11200000.usb: xHCI Host Controller
10573 00:41:26.879143 <6>[ 2.127835] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10574 00:41:26.885995 <6>[ 2.135505] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10575 00:41:26.893110 <6>[ 2.143363] hub 1-0:1.0: USB hub found
10576 00:41:26.896606 <6>[ 2.147398] hub 1-0:1.0: 1 port detected
10577 00:41:26.906266 <6>[ 2.151692] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10578 00:41:26.909409 <6>[ 2.160454] hub 2-0:1.0: USB hub found
10579 00:41:26.913074 <6>[ 2.164477] hub 2-0:1.0: 1 port detected
10580 00:41:26.921832 <6>[ 2.172675] mtk-msdc 11f70000.mmc: Got CD GPIO
10581 00:41:26.938995 <6>[ 2.186238] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10582 00:41:26.949168 <6>[ 2.194779] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10583 00:41:26.956040 <6>[ 2.203271] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10584 00:41:26.965472 <6>[ 2.211624] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10585 00:41:26.972339 <6>[ 2.219965] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10586 00:41:26.982171 <6>[ 2.228318] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10587 00:41:26.988686 <6>[ 2.236658] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10588 00:41:26.998225 <6>[ 2.245008] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10589 00:41:27.005559 <6>[ 2.253346] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10590 00:41:27.015363 <6>[ 2.261695] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10591 00:41:27.021748 <6>[ 2.270035] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10592 00:41:27.032152 <6>[ 2.278387] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10593 00:41:27.038929 <6>[ 2.286729] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10594 00:41:27.048715 <6>[ 2.295078] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10595 00:41:27.054827 <6>[ 2.303417] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10596 00:41:27.061597 <6>[ 2.312168] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10597 00:41:27.068666 <6>[ 2.319351] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10598 00:41:27.075547 <6>[ 2.326125] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10599 00:41:27.085760 <6>[ 2.332919] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10600 00:41:27.092105 <6>[ 2.339841] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10601 00:41:27.098613 <6>[ 2.346698] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10602 00:41:27.108678 <6>[ 2.355827] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10603 00:41:27.118406 <6>[ 2.364946] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10604 00:41:27.128238 <6>[ 2.374239] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10605 00:41:27.138757 <6>[ 2.383706] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10606 00:41:27.148079 <6>[ 2.393174] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10607 00:41:27.154979 <6>[ 2.402293] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10608 00:41:27.165328 <6>[ 2.411759] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10609 00:41:27.175129 <6>[ 2.420878] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10610 00:41:27.184770 <6>[ 2.430175] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10611 00:41:27.194629 <6>[ 2.440364] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10612 00:41:27.204349 <6>[ 2.451944] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10613 00:41:27.211843 <6>[ 2.462581] Trying to probe devices needed for running init ...
10614 00:41:27.222414 <3>[ 2.469828] mt8192-audio 11210000.syscon:mt8192-afe-pcm: could not get audiosys reset:-517
10615 00:41:27.331589 <6>[ 2.578791] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10616 00:41:27.486433 <6>[ 2.736525] hub 1-1:1.0: USB hub found
10617 00:41:27.489662 <6>[ 2.741051] hub 1-1:1.0: 4 ports detected
10618 00:41:27.501646 <6>[ 2.751861] hub 1-1:1.0: USB hub found
10619 00:41:27.505334 <6>[ 2.756225] hub 1-1:1.0: 4 ports detected
10620 00:41:27.612002 <6>[ 2.859077] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10621 00:41:27.637185 <6>[ 2.887741] hub 2-1:1.0: USB hub found
10622 00:41:27.640850 <6>[ 2.892174] hub 2-1:1.0: 3 ports detected
10623 00:41:27.652020 <6>[ 2.902523] hub 2-1:1.0: USB hub found
10624 00:41:27.655459 <6>[ 2.907042] hub 2-1:1.0: 3 ports detected
10625 00:41:27.827666 <6>[ 3.074962] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10626 00:41:27.960394 <6>[ 3.210832] hub 1-1.4:1.0: USB hub found
10627 00:41:27.963733 <6>[ 3.215458] hub 1-1.4:1.0: 2 ports detected
10628 00:41:27.975953 <6>[ 3.226486] hub 1-1.4:1.0: USB hub found
10629 00:41:27.979353 <6>[ 3.231057] hub 1-1.4:1.0: 2 ports detected
10630 00:41:28.040289 <6>[ 3.287170] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10631 00:41:28.148311 <6>[ 3.395595] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10632 00:41:28.184579 <4>[ 3.431685] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10633 00:41:28.194692 <4>[ 3.440777] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10634 00:41:28.233816 <6>[ 3.484536] r8152 2-1.3:1.0 eth0: v1.12.13
10635 00:41:28.275744 <6>[ 3.522762] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10636 00:41:28.467458 <6>[ 3.714797] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10637 00:41:29.823193 <6>[ 5.073638] r8152 2-1.3:1.0 eth0: carrier on
10638 00:41:32.551354 <5>[ 5.098753] Sending DHCP requests .., OK
10639 00:41:32.558134 <6>[ 7.807101] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.14
10640 00:41:32.561291 <6>[ 7.815394] IP-Config: Complete:
10641 00:41:32.574790 <6>[ 7.818893] device=eth0, hwaddr=00:24:32:30:7c:7b, ipaddr=192.168.201.14, mask=255.255.255.0, gw=192.168.201.1
10642 00:41:32.581455 <6>[ 7.829602] host=mt8192-asurada-spherion-r0-cbg-2, domain=lava-rack, nis-domain=(none)
10643 00:41:32.587831 <6>[ 7.838219] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10644 00:41:32.594829 <6>[ 7.838229] nameserver0=192.168.201.1
10645 00:41:32.598012 <6>[ 7.850389] clk: Disabling unused clocks
10646 00:41:32.601661 <6>[ 7.855906] ALSA device list:
10647 00:41:32.607744 <6>[ 7.859160] No soundcards found.
10648 00:41:32.615504 <6>[ 7.866541] Freeing unused kernel memory: 8512K
10649 00:41:32.618535 <6>[ 7.871431] Run /init as init process
10650 00:41:32.627999 Loading, please wait...
10651 00:41:32.657254 Starting systemd-udevd version 252.22-1~deb12u1
10652 00:41:32.940040 <6>[ 8.187968] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10653 00:41:32.953671 <6>[ 8.201155] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10654 00:41:32.960019 <6>[ 8.203622] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10655 00:41:32.966684 <6>[ 8.204343] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10656 00:41:32.976647 <6>[ 8.204351] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10657 00:41:32.986672 <4>[ 8.204550] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10658 00:41:32.993299 <6>[ 8.205203] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10659 00:41:32.999954 <6>[ 8.205211] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10660 00:41:33.009770 <6>[ 8.205537] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10661 00:41:33.016492 <6>[ 8.205587] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10662 00:41:33.026347 <6>[ 8.205592] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10663 00:41:33.032757 <6>[ 8.205600] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10664 00:41:33.039899 <6>[ 8.212989] remoteproc remoteproc0: scp is available
10665 00:41:33.046511 <6>[ 8.216661] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10666 00:41:33.053241 <6>[ 8.224344] remoteproc remoteproc0: powering up scp
10667 00:41:33.063494 <6>[ 8.233257] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10668 00:41:33.069855 <3>[ 8.236841] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10669 00:41:33.076901 <3>[ 8.236855] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10670 00:41:33.086970 <3>[ 8.236858] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10671 00:41:33.094157 <3>[ 8.236945] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10672 00:41:33.103487 <3>[ 8.236949] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10673 00:41:33.110341 <3>[ 8.236951] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10674 00:41:33.120104 <3>[ 8.236958] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10675 00:41:33.126636 <3>[ 8.236962] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10676 00:41:33.133316 <3>[ 8.239241] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10677 00:41:33.142841 <3>[ 8.240503] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10678 00:41:33.150077 <3>[ 8.240520] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10679 00:41:33.159704 <3>[ 8.240529] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10680 00:41:33.166721 <3>[ 8.240643] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10681 00:41:33.176711 <3>[ 8.240651] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10682 00:41:33.183433 <3>[ 8.240658] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10683 00:41:33.192955 <3>[ 8.240671] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10684 00:41:33.199619 <3>[ 8.240677] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10685 00:41:33.206098 <3>[ 8.240720] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10686 00:41:33.216360 <6>[ 8.241192] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10687 00:41:33.222770 <6>[ 8.241232] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10688 00:41:33.229584 <6>[ 8.241738] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10689 00:41:33.232757 <6>[ 8.241807] mc: Linux media interface: v0.10
10690 00:41:33.239027 <6>[ 8.266771] videodev: Linux video capture interface: v2.00
10691 00:41:33.249629 <4>[ 8.280795] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10692 00:41:33.252383 <4>[ 8.280795] Fallback method does not support PEC.
10693 00:41:33.259186 <4>[ 8.282213] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10694 00:41:33.268847 <3>[ 8.305591] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10695 00:41:33.275470 <4>[ 8.309628] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10696 00:41:33.285743 <3>[ 8.340656] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10697 00:41:33.291940 <6>[ 8.372160] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10698 00:41:33.301962 <6>[ 8.383793] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10699 00:41:33.308402 <6>[ 8.391241] pci_bus 0000:00: root bus resource [bus 00-ff]
10700 00:41:33.315637 <6>[ 8.398913] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10701 00:41:33.325005 <6>[ 8.406944] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10702 00:41:33.331948 <6>[ 8.406953] remoteproc remoteproc0: remote processor scp is now up
10703 00:41:33.338057 <6>[ 8.406973] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10704 00:41:33.348288 <6>[ 8.406979] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10705 00:41:33.354670 <6>[ 8.407021] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10706 00:41:33.360763 <6>[ 8.407047] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10707 00:41:33.370992 <6>[ 8.415748] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10708 00:41:33.374821 <6>[ 8.423293] pci 0000:00:00.0: supports D1 D2
10709 00:41:33.384717 <6>[ 8.446661] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10710 00:41:33.390506 <6>[ 8.447555] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10711 00:41:33.397608 <6>[ 8.481727] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10712 00:41:33.407263 <6>[ 8.487240] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10713 00:41:33.413598 <6>[ 8.493106] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10714 00:41:33.420469 <6>[ 8.495813] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10715 00:41:33.423733 <6>[ 8.496882] Bluetooth: Core ver 2.22
10716 00:41:33.430783 <6>[ 8.497324] NET: Registered PF_BLUETOOTH protocol family
10717 00:41:33.436968 <6>[ 8.497330] Bluetooth: HCI device and connection manager initialized
10718 00:41:33.443307 <6>[ 8.497361] Bluetooth: HCI socket layer initialized
10719 00:41:33.446810 <6>[ 8.497373] Bluetooth: L2CAP socket layer initialized
10720 00:41:33.453483 <6>[ 8.497391] Bluetooth: SCO socket layer initialized
10721 00:41:33.460237 <6>[ 8.517877] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10722 00:41:33.466565 <6>[ 8.525382] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10723 00:41:33.479763 <6>[ 8.533765] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10724 00:41:33.486377 <6>[ 8.541443] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10725 00:41:33.492882 <6>[ 8.548522] usbcore: registered new interface driver uvcvideo
10726 00:41:33.499683 <6>[ 8.558382] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10727 00:41:33.506071 <6>[ 8.559310] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10728 00:41:33.512959 <6>[ 8.571869] usbcore: registered new interface driver btusb
10729 00:41:33.522683 <4>[ 8.572829] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10730 00:41:33.529445 <3>[ 8.572836] Bluetooth: hci0: Failed to load firmware file (-2)
10731 00:41:33.536044 <3>[ 8.572837] Bluetooth: hci0: Failed to set up firmware (-2)
10732 00:41:33.546065 <4>[ 8.572840] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10733 00:41:33.549131 <6>[ 8.579767] pci 0000:01:00.0: supports D1 D2
10734 00:41:33.555828 <6>[ 8.806490] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10735 00:41:33.574819 <6>[ 8.822821] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10736 00:41:33.581688 <6>[ 8.829724] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10737 00:41:33.588035 <6>[ 8.837804] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10738 00:41:33.597972 <6>[ 8.845803] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10739 00:41:33.604808 <6>[ 8.853804] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10740 00:41:33.614863 <6>[ 8.861805] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10741 00:41:33.617826 <6>[ 8.869804] pci 0000:00:00.0: PCI bridge to [bus 01]
10742 00:41:33.627773 <6>[ 8.875021] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10743 00:41:33.634345 <6>[ 8.883148] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10744 00:41:33.642112 <6>[ 8.889968] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10745 00:41:33.647780 <6>[ 8.896796] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10746 00:41:33.662904 <5>[ 8.910696] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10747 00:41:33.687010 <5>[ 8.934783] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10748 00:41:33.693867 <5>[ 8.942205] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10749 00:41:33.703558 <4>[ 8.950655] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10750 00:41:33.710282 <6>[ 8.959541] cfg80211: failed to load regulatory.db
10751 00:41:33.756353 <6>[ 9.004099] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10752 00:41:33.762921 <6>[ 9.011615] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10753 00:41:33.787632 <6>[ 9.038290] mt7921e 0000:01:00.0: ASIC revision: 79610010
10754 00:41:33.891186 <6>[ 9.138969] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10755 00:41:33.894425 <6>[ 9.138969]
10756 00:41:33.898314 Begin: Loading essential drivers ... done.
10757 00:41:33.901063 Begin: Running /scripts/init-premount ... done.
10758 00:41:33.908223 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10759 00:41:33.917803 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10760 00:41:33.921162 Device /sys/class/net/eth0 found
10761 00:41:33.921628 done.
10762 00:41:33.928200 Begin: Waiting up to 180 secs for any network device to become available ... done.
10763 00:41:33.983696 IP-Config: eth0 hardware address 00:24:32:30:7c:7b mtu 1500 DHCP
10764 00:41:33.992147 IP-Config: eth0 complete (dhcp from 192.168.201.1):
10765 00:41:33.999052 address: 192.168.201.14 broadcast: 192.168.201.255 netmask: 255.255.255.0
10766 00:41:34.005643 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10767 00:41:34.011780 host : mt8192-asurada-spherion-r0-cbg-2
10768 00:41:34.018676 domain : lava-rack
10769 00:41:34.022466 rootserver: 192.168.201.1 rootpath:
10770 00:41:34.025509 filename :
10771 00:41:34.162349 <6>[ 9.410053] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10772 00:41:34.162502 done.
10773 00:41:34.172439 Begin: Running /scripts/nfs-bottom ... done.
10774 00:41:34.190054 Begin: Running /scripts/init-bottom ... done.
10775 00:41:35.526542 <6>[ 10.778090] NET: Registered PF_INET6 protocol family
10776 00:41:35.533548 <6>[ 10.785045] Segment Routing with IPv6
10777 00:41:35.536974 <6>[ 10.789024] In-situ OAM (IOAM) with IPv6
10778 00:41:35.707971 <30>[ 10.932970] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10779 00:41:35.714628 <30>[ 10.966138] systemd[1]: Detected architecture arm64.
10780 00:41:35.721930
10781 00:41:35.725362 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10782 00:41:35.725450
10783 00:41:35.748739 <30>[ 11.000133] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10784 00:41:36.843981 <30>[ 12.092583] systemd[1]: Queued start job for default target graphical.target.
10785 00:41:36.884136 <30>[ 12.132033] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10786 00:41:36.890295 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10787 00:41:36.913216 <30>[ 12.160775] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10788 00:41:36.921995 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10789 00:41:36.940354 <30>[ 12.188658] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10790 00:41:36.950087 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10791 00:41:36.967740 <30>[ 12.216289] systemd[1]: Created slice user.slice - User and Session Slice.
10792 00:41:36.974706 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10793 00:41:36.998671 <30>[ 12.243357] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10794 00:41:37.008162 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10795 00:41:37.026497 <30>[ 12.271164] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10796 00:41:37.032699 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10797 00:41:37.061162 <30>[ 12.299575] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10798 00:41:37.070991 <30>[ 12.319541] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10799 00:41:37.077794 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10800 00:41:37.094494 <30>[ 12.342940] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10801 00:41:37.101155 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10802 00:41:37.118472 <30>[ 12.367010] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10803 00:41:37.128360 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10804 00:41:37.143134 <30>[ 12.395002] systemd[1]: Reached target paths.target - Path Units.
10805 00:41:37.152961 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10806 00:41:37.170971 <30>[ 12.419382] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10807 00:41:37.177293 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10808 00:41:37.191782 <30>[ 12.442919] systemd[1]: Reached target slices.target - Slice Units.
10809 00:41:37.201573 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10810 00:41:37.215821 <30>[ 12.467330] systemd[1]: Reached target swap.target - Swaps.
10811 00:41:37.222284 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10812 00:41:37.242970 <30>[ 12.491451] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10813 00:41:37.252894 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10814 00:41:37.271530 <30>[ 12.519416] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10815 00:41:37.281106 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10816 00:41:37.303148 <30>[ 12.550417] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10817 00:41:37.311932 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10818 00:41:37.328713 <30>[ 12.576540] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10819 00:41:37.338235 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10820 00:41:37.356227 <30>[ 12.604320] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10821 00:41:37.363181 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10822 00:41:37.384768 <30>[ 12.632824] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10823 00:41:37.394394 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10824 00:41:37.414955 <30>[ 12.662611] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10825 00:41:37.423981 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10826 00:41:37.438909 <30>[ 12.687415] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10827 00:41:37.448464 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10828 00:41:37.506813 <30>[ 12.755134] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10829 00:41:37.513108 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10830 00:41:37.535347 <30>[ 12.783905] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10831 00:41:37.542412 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10832 00:41:37.567581 <30>[ 12.815791] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10833 00:41:37.574009 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10834 00:41:37.602342 <30>[ 12.843594] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10835 00:41:37.618115 <30>[ 12.866253] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10836 00:41:37.628120 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10837 00:41:37.653029 <30>[ 12.900955] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10838 00:41:37.659421 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10839 00:41:37.684568 <30>[ 12.932557] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10840 00:41:37.691008 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10841 00:41:37.716614 <30>[ 12.965075] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10842 00:41:37.723698 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10843 00:41:37.733434 <6>[ 12.980153] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10844 00:41:37.734019
10845 00:41:37.775659 <30>[ 13.023893] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10846 00:41:37.785248 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10847 00:41:37.808622 <30>[ 13.057122] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10848 00:41:37.815862 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10849 00:41:37.846969 <6>[ 13.098416] fuse: init (API version 7.37)
10850 00:41:37.867325 <30>[ 13.115822] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10851 00:41:37.873831 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10852 00:41:37.904659 <30>[ 13.153057] systemd[1]: Starting systemd-journald.service - Journal Service...
10853 00:41:37.911552 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10854 00:41:37.975691 <30>[ 13.224155] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10855 00:41:37.982425 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10856 00:41:38.010830 <30>[ 13.255715] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10857 00:41:38.018072 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10858 00:41:38.040168 <30>[ 13.288223] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10859 00:41:38.050314 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10860 00:41:38.063779 <3>[ 13.311464] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10861 00:41:38.079078 <30>[ 13.327161] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10862 00:41:38.086050 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10863 00:41:38.097550 <3>[ 13.345359] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10864 00:41:38.113168 <30>[ 13.360709] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
10865 00:41:38.118997 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10866 00:41:38.139510 <30>[ 13.387549] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
10867 00:41:38.149535 <3>[ 13.387828] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10868 00:41:38.155744 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10869 00:41:38.175628 <30>[ 13.423296] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
10870 00:41:38.182172 <3>[ 13.427511] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10871 00:41:38.192074 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10872 00:41:38.212449 <30>[ 13.459897] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
10873 00:41:38.222326 <3>[ 13.463003] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10874 00:41:38.228563 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10875 00:41:38.249385 <30>[ 13.496925] systemd[1]: modprobe@configfs.service: Deactivated successfully.
10876 00:41:38.255508 <3>[ 13.500368] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10877 00:41:38.265644 <30>[ 13.505241] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
10878 00:41:38.275309 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10879 00:41:38.290590 <3>[ 13.538616] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10880 00:41:38.300672 <30>[ 13.548675] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
10881 00:41:38.307624 <30>[ 13.556524] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
10882 00:41:38.324045 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m <3>[ 13.570311] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10883 00:41:38.324482 - Load Kernel Module dm_mod.
10884 00:41:38.346663 <30>[ 13.597172] systemd[1]: modprobe@drm.service: Deactivated successfully.
10885 00:41:38.356194 <3>[ 13.602690] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10886 00:41:38.362922 <30>[ 13.605028] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
10887 00:41:38.372962 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10888 00:41:38.387579 <3>[ 13.635544] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10889 00:41:38.400427 <30>[ 13.648705] systemd[1]: modprobe@efi_pstore.service: Deactivated successfully.
10890 00:41:38.410781 <30>[ 13.657728] systemd[1]: Finished modprobe@efi_pstore.service - Load Kernel Module efi_pstore.
10891 00:41:38.417690 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10892 00:41:38.433618 <30>[ 13.684725] systemd[1]: modprobe@fuse.service: Deactivated successfully.
10893 00:41:38.444691 <30>[ 13.692657] systemd[1]: Finished modprobe@fuse.service - Load Kernel Module fuse.
10894 00:41:38.450912 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
10895 00:41:38.472116 <30>[ 13.720096] systemd[1]: Started systemd-journald.service - Journal Service.
10896 00:41:38.478419 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10897 00:41:38.508312 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10898 00:41:38.538646 [[0;32m OK [0m] Finished [0<4>[ 13.778429] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10899 00:41:38.544844 <3>[ 13.794944] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10900 00:41:38.551619 ;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10901 00:41:38.574178 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10902 00:41:38.596953 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
10903 00:41:38.620629 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10904 00:41:38.641562 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10905 00:41:38.691025 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
10906 00:41:38.713307 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10907 00:41:38.735764 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10908 00:41:38.759000 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10909 00:41:38.784643 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10910 00:41:38.813382 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10911 00:41:38.823371 <46>[ 14.072252] systemd-journald[301]: Received client request to flush runtime journal.
10912 00:41:38.851519 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
10913 00:41:38.872608 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10914 00:41:38.892672 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10915 00:41:38.912251 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10916 00:41:39.959062 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10917 00:41:40.019650 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10918 00:41:40.277669 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10919 00:41:40.388514 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10920 00:41:40.407281 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10921 00:41:40.426523 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10922 00:41:40.479161 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10923 00:41:40.502619 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10924 00:41:40.759394 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10925 00:41:40.846699 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
10926 00:41:40.879865 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10927 00:41:41.186039 [[0;32m OK [0m] Finished [0;1;39msystemd-tm<6>[ 16.435247] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10928 00:41:41.189332 pfiles-…te Volatile Files and Directories.
10929 00:41:41.214019 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
10930 00:41:41.265363 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
10931 00:41:41.371847 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10932 00:41:41.394871 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10933 00:41:41.422536 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
10934 00:41:41.502820 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
10935 00:41:41.551108 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10936 00:41:41.574910 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
10937 00:41:41.587400 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
10938 00:41:41.607180 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
10939 00:41:41.639449 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
10940 00:41:41.683324 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10941 00:41:41.707628 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
10942 00:41:41.730850 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10943 00:41:41.746296 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10944 00:41:41.762248 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
10945 00:41:41.789843 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
10946 00:41:41.810155 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
10947 00:41:41.826863 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
10948 00:41:41.846260 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
10949 00:41:41.866283 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
10950 00:41:41.882529 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
10951 00:41:41.900801 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
10952 00:41:41.918768 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
10953 00:41:41.934766 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
10954 00:41:41.984232 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
10955 00:41:42.019423 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
10956 00:41:42.131528 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
10957 00:41:42.156552 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
10958 00:41:42.200611 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
10959 00:41:42.247470 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
10960 00:41:42.270368 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
10961 00:41:42.291167 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
10962 00:41:42.419328 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
10963 00:41:42.494467 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
10964 00:41:42.513439 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
10965 00:41:42.533702 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
10966 00:41:42.551827 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
10967 00:41:42.597670 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
10968 00:41:42.650256 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
10969 00:41:42.735097
10970 00:41:42.738552 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
10971 00:41:42.738975
10972 00:41:42.741484 debian-bookworm-arm64 login: root (automatic login)
10973 00:41:42.741907
10974 00:41:43.066285 Linux debian-bookworm-arm64 6.1.92-cip22 #1 SMP PREEMPT Sun Jun 16 00:28:47 UTC 2024 aarch64
10975 00:41:43.066790
10976 00:41:43.072932 The programs included with the Debian GNU/Linux system are free software;
10977 00:41:43.079879 the exact distribution terms for each program are described in the
10978 00:41:43.083204 individual files in /usr/share/doc/*/copyright.
10979 00:41:43.083623
10980 00:41:43.089744 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10981 00:41:43.092657 permitted by applicable law.
10982 00:41:43.206865 Matched prompt #10: / #
10984 00:41:43.207995 Setting prompt string to ['/ #']
10985 00:41:43.208776 end: 2.2.5.1 login-action (duration 00:00:19) [common]
10987 00:41:43.209908 end: 2.2.5 auto-login-action (duration 00:00:19) [common]
10988 00:41:43.210345 start: 2.2.6 expect-shell-connection (timeout 00:03:25) [common]
10989 00:41:43.210708 Setting prompt string to ['/ #']
10990 00:41:43.211020 Forcing a shell prompt, looking for ['/ #']
10992 00:41:43.261805 / #
10993 00:41:43.262420 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10994 00:41:43.262866 Waiting using forced prompt support (timeout 00:02:30)
10995 00:41:43.268092
10996 00:41:43.269003 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10997 00:41:43.269653 start: 2.2.7 export-device-env (timeout 00:03:25) [common]
10999 00:41:43.370776 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14368371/extract-nfsrootfs-u2n90c2q'
11000 00:41:43.377074 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14368371/extract-nfsrootfs-u2n90c2q'
11002 00:41:43.478808 / # export NFS_SERVER_IP='192.168.201.1'
11003 00:41:43.485625 export NFS_SERVER_IP='192.168.201.1'
11004 00:41:43.486554 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11005 00:41:43.487041 end: 2.2 depthcharge-retry (duration 00:01:35) [common]
11006 00:41:43.487511 end: 2 depthcharge-action (duration 00:01:35) [common]
11007 00:41:43.488052 start: 3 lava-test-retry (timeout 00:30:00) [common]
11008 00:41:43.488535 start: 3.1 lava-test-shell (timeout 00:30:00) [common]
11009 00:41:43.488951 Using namespace: common
11011 00:41:43.590210 / # #
11012 00:41:43.590874 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:30:00)
11013 00:41:43.597025 #
11014 00:41:43.597927 Using /lava-14368371
11016 00:41:43.699215 / # export SHELL=/bin/sh
11017 00:41:43.705653 export SHELL=/bin/sh
11019 00:41:43.807269 / # . /lava-14368371/environment
11020 00:41:43.813525 . /lava-14368371/environment
11022 00:41:43.922359 / # /lava-14368371/bin/lava-test-runner /lava-14368371/0
11023 00:41:43.923005 Test shell timeout: 10s (minimum of the action and connection timeout)
11024 00:41:43.929252 /lava-14368371/bin/lava-test-runner /lava-14368371/0
11025 00:41:44.205400 + export TESTRUN_ID=0_lc-compliance
11026 00:41:44.211445 + cd /lava-14368371/0/tests/0_lc-compliance
11027 00:41:44.211865 + cat uuid
11028 00:41:44.224655 + UUID=14368371_1.6.2.3.1
11029 00:41:44.225094 + set +x
11030 00:41:44.231383 <LAVA_SIGNAL_STARTRUN 0_lc-compliance 14368371_1.6.2.3.1>
11031 00:41:44.232084 Received signal: <STARTRUN> 0_lc-compliance 14368371_1.6.2.3.1
11032 00:41:44.232458 Starting test lava.0_lc-compliance (14368371_1.6.2.3.1)
11033 00:41:44.232884 Skipping test definition patterns.
11034 00:41:44.234650 + /usr/bin/lc-compliance-parser.sh
11035 00:41:46.126752 [0:00:21.257556846] [405] [1;32m INFO [1;37mCamera [1;34mcamera_manager.cpp:284 [0mlibcamera v0.0.0+1-01935edb
11036 00:41:46.129950 Using camera /base/soc/usb@11200000-1.4.1:1.0-04f2:b741
11037 00:41:46.150399 [0:00:21.281188231] [405] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11038 00:41:46.211173 [0:00:21.342561154] [405] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11039 00:41:46.232478 [==========] Running 120 tests from 1 test suite.
11040 00:41:46.270649 [0:00:21.402071154] [405] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11041 00:41:46.324933 [0:00:21.456184923] [405] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11042 00:41:46.328318 [----------] Global test environment set-up.
11043 00:41:46.420590 [----------] 120 tests from CaptureTests/SingleStream
11044 00:41:46.510099 [ RUN ] CaptureTests/SingleStream.Capture/Raw_1
11045 00:41:46.587980 <LAVA_SIGNAL_TESTSET START CaptureTests/SingleStream>
11046 00:41:46.588774 Received signal: <TESTSET> START CaptureTests/SingleStream
11047 00:41:46.589142 Starting test_set CaptureTests/SingleStream
11048 00:41:46.590815 Camera needs 4 requests, can't test only 1
11049 00:41:46.689669 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11050 00:41:46.754363 [0:00:21.885755539] [405] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11051 00:41:46.789392
11052 00:41:46.897602 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_1 (63 ms)
11053 00:41:47.010524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_1 RESULT=skip>
11054 00:41:47.011262 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_1 RESULT=skip
11056 00:41:47.030584 [ RUN ] CaptureTests/SingleStream.Capture/Raw_2
11057 00:41:47.101235 Camera needs 4 requests, can't test only 2
11058 00:41:47.194342 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11059 00:41:47.281836
11060 00:41:47.375392 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_2 (58 ms)
11061 00:41:47.447935 [0:00:22.579003770] [405] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11062 00:41:47.486369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_2 RESULT=skip>
11063 00:41:47.487066 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_2 RESULT=skip
11065 00:41:47.505215 [ RUN ] CaptureTests/SingleStream.Capture/Raw_3
11066 00:41:47.559321 Camera needs 4 requests, can't test only 3
11067 00:41:47.636501 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11068 00:41:47.716229
11069 00:41:47.799385 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_3 (54 ms)
11070 00:41:47.894424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_3 RESULT=skip>
11071 00:41:47.895270 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_3 RESULT=skip
11073 00:41:47.911996 [ RUN ] CaptureTests/SingleStream.Capture/Raw_5
11074 00:41:47.971197 [ OK ] CaptureTests/SingleStream.Capture/Raw_5 (429 ms)
11075 00:41:48.072436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_5 RESULT=pass>
11076 00:41:48.073229 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_5 RESULT=pass
11078 00:41:48.091822 [ RUN ] CaptureTests/SingleStream.Capture/Raw_8
11079 00:41:48.150637 [ OK ] CaptureTests/SingleStream.Capture/Raw_8 (693 ms)
11080 00:41:48.255642 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_8 RESULT=pass>
11081 00:41:48.256411 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_8 RESULT=pass
11083 00:41:48.276605 [ RUN ] CaptureTests/SingleStream.Capture/Raw_13
11084 00:41:48.701561 [0:00:23.832985077] [405] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11085 00:41:48.704923 [ OK ] CaptureTests/SingleStream.Capture/Raw_13 (1253 ms)
11086 00:41:48.800269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_13 RESULT=pass>
11087 00:41:48.800564 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_13 RESULT=pass
11089 00:41:48.816045 [ RUN ] CaptureTests/SingleStream.Capture/Raw_21
11090 00:41:50.516917 [0:00:25.647904770] [405] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11091 00:41:50.519958 [ OK ] CaptureTests/SingleStream.Capture/Raw_21 (1814 ms)
11092 00:41:50.620609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_21 RESULT=pass>
11093 00:41:50.621384 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_21 RESULT=pass
11095 00:41:50.638871 [ RUN ] CaptureTests/SingleStream.Capture/Raw_34
11096 00:41:53.241008 [0:00:28.373076001] [405] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11097 00:41:53.244766 [ OK ] CaptureTests/SingleStream.Capture/Raw_34 (2725 ms)
11098 00:41:53.337418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_34 RESULT=pass>
11099 00:41:53.338152 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_34 RESULT=pass
11101 00:41:53.355968 [ RUN ] CaptureTests/SingleStream.Capture/Raw_55
11102 00:41:57.428843 [ OK ] CaptureTests/SingleStream.Capture/Raw_55 (4194 ms)
11103 00:41:57.438170 [0:00:32.567605693] [405] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11104 00:41:57.540104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_55 RESULT=pass>
11105 00:41:57.540833 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_55 RESULT=pass
11107 00:41:57.559807 [ RUN ] CaptureTests/SingleStream.Capture/Raw_89
11108 00:42:02.709802 <6>[ 37.966983] vpu: disabling
11109 00:42:02.712856 <6>[ 37.970085] vproc2: disabling
11110 00:42:02.717107 <6>[ 37.973831] vproc1: disabling
11111 00:42:02.720801 <6>[ 37.977853] vaud18: disabling
11112 00:42:02.727377 <6>[ 37.981603] vsram_others: disabling
11113 00:42:02.730665 <6>[ 37.985807] va09: disabling
11114 00:42:02.734092 <6>[ 37.989179] vsram_md: disabling
11115 00:42:02.737049 <6>[ 37.992964] Vgpu: disabling
11116 00:42:04.009340 [0:00:39.142484924] [405] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11117 00:42:04.012688 [ OK ] CaptureTests/SingleStream.Capture/Raw_89 (6574 ms)
11118 00:42:04.061970 [0:00:39.195348155] [405] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11119 00:42:04.114276 [0:00:39.247135694] [405] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11120 00:42:04.120799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_89 RESULT=pass>
11121 00:42:04.121480 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_89 RESULT=pass
11123 00:42:04.140347 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_1
11124 00:42:04.165719 [0:00:39.298926232] [405] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11125 00:42:04.208696 Camera needs 4 requests, can't test only 1
11126 00:42:04.301385 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11127 00:42:04.385562
11128 00:42:04.481326 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_1 (53 ms)
11129 00:42:04.588884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_1 RESULT=skip>
11130 00:42:04.589667 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_1 RESULT=skip
11132 00:42:04.607169 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_2
11133 00:42:04.669305 Camera needs 4 requests, can't test only 2
11134 00:42:04.758378 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11135 00:42:04.841492
11136 00:42:04.858932 [0:00:39.992255694] [405] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11137 00:42:04.938300 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_2 (51 ms)
11138 00:42:05.040016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_2 RESULT=skip>
11139 00:42:05.040735 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_2 RESULT=skip
11141 00:42:05.058978 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_3
11142 00:42:05.120626 Camera needs 4 requests, can't test only 3
11143 00:42:05.210711 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11144 00:42:05.298857
11145 00:42:05.395123 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_3 (51 ms)
11146 00:42:05.502866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_3 RESULT=skip>
11147 00:42:05.503573 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_3 RESULT=skip
11149 00:42:05.522343 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_5
11150 00:42:05.586764 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_5 (693 ms)
11151 00:42:05.698017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_5 RESULT=pass>
11152 00:42:05.698320 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_5 RESULT=pass
11154 00:42:05.715086 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_8
11155 00:42:05.762440 [0:00:40.895910001] [405] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11156 00:42:05.779946 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_8 (903 ms)
11157 00:42:05.879471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_8 RESULT=pass>
11158 00:42:05.879842 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_8 RESULT=pass
11160 00:42:05.896672 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_13
11161 00:42:07.017294 [0:00:42.150814848] [405] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11162 00:42:07.024242 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_13 (1254 ms)
11163 00:42:07.115891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_13 RESULT=pass>
11164 00:42:07.116629 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_13 RESULT=pass
11166 00:42:07.135365 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_21
11167 00:42:08.833079 [0:00:43.966923079] [405] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11168 00:42:08.839159 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_21 (1815 ms)
11169 00:42:08.936876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_21 RESULT=pass>
11170 00:42:08.937173 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_21 RESULT=pass
11172 00:42:08.954439 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_34
11173 00:42:11.559617 [0:00:46.693692694] [405] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11174 00:42:11.566568 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_34 (2726 ms)
11175 00:42:11.648971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_34 RESULT=pass>
11176 00:42:11.649312 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_34 RESULT=pass
11178 00:42:11.666171 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_55
11179 00:42:15.754830 [0:00:50.888865233] [405] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11180 00:42:15.761123 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_55 (4195 ms)
11181 00:42:15.868208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_55 RESULT=pass>
11182 00:42:15.868918 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_55 RESULT=pass
11184 00:42:15.887554 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_89
11185 00:42:22.329829 [0:00:57.464501233] [405] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11186 00:42:22.336088 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_89 (6575 ms)
11187 00:42:22.382673 [0:00:57.517349233] [405] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11188 00:42:22.434955 [0:00:57.570255002] [405] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11189 00:42:22.443134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_89 RESULT=pass>
11190 00:42:22.443815 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_89 RESULT=pass
11192 00:42:22.462259 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_1
11193 00:42:22.488817 [0:00:57.623394541] [405] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11194 00:42:22.527659 Camera needs 4 requests, can't test only 1
11195 00:42:22.617818 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11196 00:42:22.706708
11197 00:42:22.803962 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_1 (52 ms)
11198 00:42:22.912995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_1 RESULT=skip>
11199 00:42:22.913768 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_1 RESULT=skip
11201 00:42:22.931160 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_2
11202 00:42:22.989491 Camera needs 4 requests, can't test only 2
11203 00:42:23.074985 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11204 00:42:23.156782
11205 00:42:23.181404 [0:00:58.316771233] [405] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11206 00:42:23.258037 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_2 (53 ms)
11207 00:42:23.365032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_2 RESULT=skip>
11208 00:42:23.365824 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_2 RESULT=skip
11210 00:42:23.382968 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_3
11211 00:42:23.447206 Camera needs 4 requests, can't test only 3
11212 00:42:23.539930 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11213 00:42:23.630490
11214 00:42:23.727236 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_3 (52 ms)
11215 00:42:23.836392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_3 RESULT=skip>
11216 00:42:23.837110 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_3 RESULT=skip
11218 00:42:23.855573 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_5
11219 00:42:23.920270 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_5 (693 ms)
11220 00:42:24.026969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_5 RESULT=pass>
11221 00:42:24.027697 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_5 RESULT=pass
11223 00:42:24.043117 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_8
11224 00:42:24.086522 [0:00:59.221412079] [405] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11225 00:42:24.105534 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_8 (904 ms)
11226 00:42:24.214280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_8 RESULT=pass>
11227 00:42:24.215002 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_8 RESULT=pass
11229 00:42:24.233501 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_13
11230 00:42:25.341433 [0:01:00.476722772] [405] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11231 00:42:25.348473 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_13 (1255 ms)
11232 00:42:25.446075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_13 RESULT=pass>
11233 00:42:25.446998 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_13 RESULT=pass
11235 00:42:25.464851 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_21
11236 00:42:27.155155 [0:01:02.291372849] [405] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11237 00:42:27.161808 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_21 (1814 ms)
11238 00:42:27.238982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_21 RESULT=pass>
11239 00:42:27.239314 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_21 RESULT=pass
11241 00:42:27.254049 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_34
11242 00:42:29.881537 [0:01:05.018102080] [405] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11243 00:42:29.888291 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_34 (2726 ms)
11244 00:42:29.971266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_34 RESULT=pass>
11245 00:42:29.971611 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_34 RESULT=pass
11247 00:42:29.987439 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_55
11248 00:42:34.076303 [0:01:09.213421619] [405] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11249 00:42:34.083081 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_55 (4195 ms)
11250 00:42:34.163109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_55 RESULT=pass>
11251 00:42:34.163398 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_55 RESULT=pass
11253 00:42:34.179134 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_89
11254 00:42:40.651541 [0:01:15.789327157] [405] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11255 00:42:40.658615 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_89 (6575 ms)
11256 00:42:40.703695 [0:01:15.841357850] [405] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11257 00:42:40.742101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_89 RESULT=pass>
11258 00:42:40.742376 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_89 RESULT=pass
11260 00:42:40.759199 [0:01:15.896166542] [405] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11261 00:42:40.761577 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_1
11262 00:42:40.812318 [0:01:15.949879465] [405] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11263 00:42:40.815380 Camera needs 4 requests, can't test only 1
11264 00:42:40.896466 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11265 00:42:40.973897
11266 00:42:41.056334 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_1 (52 ms)
11267 00:42:41.145595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_1 RESULT=skip>
11268 00:42:41.145897 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_1 RESULT=skip
11270 00:42:41.161730 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_2
11271 00:42:41.215766 Camera needs 4 requests, can't test only 2
11272 00:42:41.291450 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11273 00:42:41.364327
11274 00:42:41.447516 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_2 (54 ms)
11275 00:42:41.506863 [0:01:16.644691465] [405] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11276 00:42:41.536154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_2 RESULT=skip>
11277 00:42:41.536422 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_2 RESULT=skip
11279 00:42:41.551422 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_3
11280 00:42:41.607723 Camera needs 4 requests, can't test only 3
11281 00:42:41.687242 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11282 00:42:41.764835
11283 00:42:41.844703 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_3 (53 ms)
11284 00:42:41.933164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_3 RESULT=skip>
11285 00:42:41.933491 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_3 RESULT=skip
11287 00:42:41.950403 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_5
11288 00:42:42.003203 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_5 (694 ms)
11289 00:42:42.095898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_5 RESULT=pass>
11290 00:42:42.096185 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_5 RESULT=pass
11292 00:42:42.111896 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_8
11293 00:42:42.412040 [0:01:17.550140773] [405] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11294 00:42:42.418649 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_8 (905 ms)
11295 00:42:42.498273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_8 RESULT=pass>
11296 00:42:42.498547 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_8 RESULT=pass
11298 00:42:42.513884 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_13
11299 00:42:43.667105 [0:01:18.805020465] [405] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11300 00:42:43.673758 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_13 (1254 ms)
11301 00:42:43.754763 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_13 RESULT=pass>
11302 00:42:43.755046 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_13 RESULT=pass
11304 00:42:43.772188 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_21
11305 00:42:45.481426 [0:01:20.619812696] [405] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11306 00:42:45.488664 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_21 (1814 ms)
11307 00:42:45.564617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_21 RESULT=pass>
11308 00:42:45.564891 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_21 RESULT=pass
11310 00:42:45.579420 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_34
11311 00:42:48.206129 [0:01:23.344680312] [405] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11312 00:42:48.212725 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_34 (2724 ms)
11313 00:42:48.290612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_34 RESULT=pass>
11314 00:42:48.290910 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_34 RESULT=pass
11316 00:42:48.306055 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_55
11317 00:42:52.401311 [0:01:27.540069389] [405] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11318 00:42:52.407648 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_55 (4195 ms)
11319 00:42:52.490946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_55 RESULT=pass>
11320 00:42:52.491276 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_55 RESULT=pass
11322 00:42:52.505472 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_89
11323 00:42:58.975459 [0:01:34.115154774] [405] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11324 00:42:58.981963 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_89 (6575 ms)
11325 00:42:59.027161 [0:01:34.166712005] [405] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11326 00:42:59.065570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_89 RESULT=pass>
11327 00:42:59.065895 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_89 RESULT=pass
11329 00:42:59.078683 [0:01:34.218694774] [405] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11330 00:42:59.085223 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_1
11331 00:42:59.132090 [0:01:34.271794389] [405] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11332 00:42:59.135330 Camera needs 4 requests, can't test only 1
11333 00:42:59.218399 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11334 00:42:59.292843
11335 00:42:59.376267 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_1 (51 ms)
11336 00:42:59.470182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_1 RESULT=skip>
11337 00:42:59.470512 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_1 RESULT=skip
11339 00:42:59.487013 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_2
11340 00:42:59.542699 Camera needs 4 requests, can't test only 2
11341 00:42:59.627171 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11342 00:42:59.703661
11343 00:42:59.788752 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_2 (51 ms)
11344 00:42:59.881690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_2 RESULT=skip>
11345 00:42:59.882030 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_2 RESULT=skip
11347 00:42:59.897044 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_3
11348 00:42:59.951750 Camera needs 4 requests, can't test only 3
11349 00:43:00.028126 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11350 00:43:00.101496
11351 00:43:00.186281 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_3 (52 ms)
11352 00:43:00.278177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_3 RESULT=skip>
11353 00:43:00.278508 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_3 RESULT=skip
11355 00:43:00.293821 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_5
11356 00:43:01.210769 [0:01:36.350688082] [405] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11357 00:43:01.217541 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_5 (2078 ms)
11358 00:43:01.304383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_5 RESULT=pass>
11359 00:43:01.304708 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_5 RESULT=pass
11361 00:43:01.321650 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_8
11362 00:43:03.917098 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_8 (2713 ms)
11363 00:43:03.929860 [0:01:39.066563005] [405] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11364 00:43:04.016222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_8 RESULT=pass>
11365 00:43:04.016989 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_8 RESULT=pass
11367 00:43:04.033206 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_13
11368 00:43:07.673963 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_13 (3757 ms)
11369 00:43:07.686700 [0:01:42.824395928] [405] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11370 00:43:07.764366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_13 RESULT=pass>
11371 00:43:07.764696 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_13 RESULT=pass
11373 00:43:07.780439 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_21
11374 00:43:13.113181 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_21 (5439 ms)
11375 00:43:13.125957 [0:01:48.264028236] [405] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11376 00:43:13.213725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_21 RESULT=pass>
11377 00:43:13.214098 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_21 RESULT=pass
11379 00:43:13.228330 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_34
11380 00:43:21.284632 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_34 (8170 ms)
11381 00:43:21.297485 [0:01:56.436615698] [405] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11382 00:43:21.405618 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_34 RESULT=pass>
11383 00:43:21.406334 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_34 RESULT=pass
11385 00:43:21.425625 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_55
11386 00:43:33.862615 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_55 (12577 ms)
11387 00:43:33.875553 [0:02:09.016591468] [405] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11388 00:43:33.955845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_55 RESULT=pass>
11389 00:43:33.956136 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_55 RESULT=pass
11391 00:43:33.971410 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_89
11392 00:43:53.582017 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_89 (19719 ms)
11393 00:43:53.595446 [0:02:28.738211239] [405] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11394 00:43:53.644680 [0:02:28.790737393] [405] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11395 00:43:53.681243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_89 RESULT=pass>
11396 00:43:53.681687 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_89 RESULT=pass
11398 00:43:53.697617 [0:02:28.843389623] [405] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11399 00:43:53.704264 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_1
11400 00:43:53.751276 [0:02:28.897160469] [405] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11401 00:43:53.761400 Camera needs 4 requests, can't test only 1
11402 00:43:53.851128 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11403 00:43:53.934106
11404 00:43:54.030054 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_1 (52 ms)
11405 00:43:54.134798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_1 RESULT=skip>
11406 00:43:54.135237 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_1 RESULT=skip
11408 00:43:54.147247 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_2
11409 00:43:54.202838 Camera needs 4 requests, can't test only 2
11410 00:43:54.286170 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11411 00:43:54.366597
11412 00:43:54.458004 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_2 (52 ms)
11413 00:43:54.548344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_2 RESULT=skip>
11414 00:43:54.548639 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_2 RESULT=skip
11416 00:43:54.560506 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_3
11417 00:43:54.614994 Camera needs 4 requests, can't test only 3
11418 00:43:54.704791 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11419 00:43:54.792269
11420 00:43:54.891098 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_3 (53 ms)
11421 00:43:54.994451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_3 RESULT=skip>
11422 00:43:54.995299 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_3 RESULT=skip
11424 00:43:55.010380 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_5
11425 00:43:55.829310 [0:02:30.975073316] [405] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11426 00:43:55.836017 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_5 (2078 ms)
11427 00:43:55.937815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_5 RESULT=pass>
11428 00:43:55.938094 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_5 RESULT=pass
11430 00:43:55.951765 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_8
11431 00:43:58.533159 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_8 (2708 ms)
11432 00:43:58.543275 [0:02:33.686017085] [405] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11433 00:43:58.639823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_8 RESULT=pass>
11434 00:43:58.640619 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_8 RESULT=pass
11436 00:43:58.656452 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_13
11437 00:44:02.291507 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_13 (3758 ms)
11438 00:44:02.301431 [0:02:37.444515393] [405] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11439 00:44:02.402539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_13 RESULT=pass>
11440 00:44:02.403264 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_13 RESULT=pass
11442 00:44:02.418013 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_21
11443 00:44:07.730665 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_21 (5439 ms)
11444 00:44:07.740542 [0:02:42.884516009] [405] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11445 00:44:07.840244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_21 RESULT=pass>
11446 00:44:07.841036 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_21 RESULT=pass
11448 00:44:07.857975 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_34
11449 00:44:15.901392 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_34 (8171 ms)
11450 00:44:15.912025 [0:02:51.055848625] [405] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11451 00:44:16.010332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_34 RESULT=pass>
11452 00:44:16.011162 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_34 RESULT=pass
11454 00:44:16.024969 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_55
11455 00:44:28.481583 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_55 (12581 ms)
11456 00:44:28.491092 [0:03:03.637869241] [405] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11457 00:44:28.606389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_55 RESULT=pass>
11458 00:44:28.607323 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_55 RESULT=pass
11460 00:44:28.621208 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_89
11461 00:44:48.199640 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_89 (19719 ms)
11462 00:44:48.210184 [0:03:23.359128473] [405] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11463 00:44:48.260279 [0:03:23.412343550] [405] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11464 00:44:48.297996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_89 RESULT=pass>
11465 00:44:48.298307 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_89 RESULT=pass
11467 00:44:48.314218 [0:03:23.465893011] [405] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11468 00:44:48.320399 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_1
11469 00:44:48.368393 [0:03:23.520141703] [405] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11470 00:44:48.370988 Camera needs 4 requests, can't test only 1
11471 00:44:48.442696 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11472 00:44:48.518937
11473 00:44:48.600530 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_1 (53 ms)
11474 00:44:48.690072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_1 RESULT=skip>
11475 00:44:48.690365 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_1 RESULT=skip
11477 00:44:48.702552 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_2
11478 00:44:48.753889 Camera needs 4 requests, can't test only 2
11479 00:44:48.832118 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11480 00:44:48.904814
11481 00:44:48.988393 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_2 (53 ms)
11482 00:44:49.078245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_2 RESULT=skip>
11483 00:44:49.078561 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_2 RESULT=skip
11485 00:44:49.090706 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_3
11486 00:44:49.146241 Camera needs 4 requests, can't test only 3
11487 00:44:49.225123 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11488 00:44:49.299049
11489 00:44:49.383593 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_3 (54 ms)
11490 00:44:49.471638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_3 RESULT=skip>
11491 00:44:49.471939 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_3 RESULT=skip
11493 00:44:49.485194 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_5
11494 00:44:50.447886 [0:03:25.599201704] [405] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11495 00:44:50.453329 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_5 (2078 ms)
11496 00:44:50.542017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_5 RESULT=pass>
11497 00:44:50.542322 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_5 RESULT=pass
11499 00:44:50.554595 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_8
11500 00:44:53.150283 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_8 (2708 ms)
11501 00:44:53.161307 [0:03:28.309153550] [405] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11502 00:44:53.244397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_8 RESULT=pass>
11503 00:44:53.244693 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_8 RESULT=pass
11505 00:44:53.256827 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_13
11506 00:44:56.909096 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_13 (3759 ms)
11507 00:44:56.919937 [0:03:32.068460089] [405] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11508 00:44:57.002001 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_13 RESULT=pass>
11509 00:44:57.002324 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_13 RESULT=pass
11511 00:44:57.013161 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_21
11512 00:45:02.348095 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_21 (5439 ms)
11513 00:45:02.357442 [0:03:37.508532397] [405] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11514 00:45:02.437622 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_21 RESULT=pass>
11515 00:45:02.437945 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_21 RESULT=pass
11517 00:45:02.450371 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_34
11518 00:45:10.520368 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_34 (8171 ms)
11519 00:45:10.530418 [0:03:45.682059320] [405] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11520 00:45:10.632198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_34 RESULT=pass>
11521 00:45:10.633005 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_34 RESULT=pass
11523 00:45:10.646169 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_55
11524 00:45:23.099407 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_55 (12578 ms)
11525 00:45:23.108839 [0:03:58.262032936] [405] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11526 00:45:23.210326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_55 RESULT=pass>
11527 00:45:23.211084 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_55 RESULT=pass
11529 00:45:23.224636 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_89
11530 00:45:42.819244 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_89 (19720 ms)
11531 00:45:42.828678 [0:04:17.984072014] [405] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11532 00:45:42.878949 [0:04:18.037026861] [405] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11533 00:45:42.916944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_89 RESULT=pass>
11534 00:45:42.917221 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_89 RESULT=pass
11536 00:45:42.931611 [0:04:18.090263322] [405] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11537 00:45:42.938524 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_1
11538 00:45:42.985694 [0:04:18.144389861] [405] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11539 00:45:42.989077 Camera needs 4 requests, can't test only 1
11540 00:45:43.063721 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11541 00:45:43.137799
11542 00:45:43.217899 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_1 (51 ms)
11543 00:45:43.307087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_1 RESULT=skip>
11544 00:45:43.307390 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_1 RESULT=skip
11546 00:45:43.319014 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_2
11547 00:45:43.372769 Camera needs 4 requests, can't test only 2
11548 00:45:43.453627 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11549 00:45:43.529028
11550 00:45:43.616896 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_2 (54 ms)
11551 00:45:43.713829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_2 RESULT=skip>
11552 00:45:43.714162 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_2 RESULT=skip
11554 00:45:43.726635 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_3
11555 00:45:43.778593 Camera needs 4 requests, can't test only 3
11556 00:45:43.854043 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11557 00:45:43.928119
11558 00:45:44.011950 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_3 (54 ms)
11559 00:45:44.100168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_3 RESULT=skip>
11560 00:45:44.100462 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_3 RESULT=skip
11562 00:45:44.110194 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_5
11563 00:45:45.064819 [0:04:20.223525630] [405] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11564 00:45:45.071488 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_5 (2078 ms)
11565 00:45:45.151214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_5 RESULT=pass>
11566 00:45:45.151517 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_5 RESULT=pass
11568 00:45:45.162322 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_8
11569 00:45:47.769215 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_8 (2709 ms)
11570 00:45:47.778871 [0:04:22.934549092] [405] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11571 00:45:47.858625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_8 RESULT=pass>
11572 00:45:47.858989 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_8 RESULT=pass
11574 00:45:47.870754 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_13
11575 00:45:51.527587 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_13 (3758 ms)
11576 00:45:51.537561 [0:04:26.693707707] [405] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11577 00:45:51.626505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_13 RESULT=pass>
11578 00:45:51.626836 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_13 RESULT=pass
11580 00:45:51.637530 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_21
11581 00:45:56.965493 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_21 (5438 ms)
11582 00:45:56.975677 [0:04:32.132154477] [405] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11583 00:45:57.063436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_21 RESULT=pass>
11584 00:45:57.063769 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_21 RESULT=pass
11586 00:45:57.076258 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_34
11587 00:46:05.138170 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_34 (8173 ms)
11588 00:46:05.148101 [0:04:40.306118708] [405] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11589 00:46:05.249363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_34 RESULT=pass>
11590 00:46:05.250114 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_34 RESULT=pass
11592 00:46:05.263326 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_55
11593 00:46:17.717458 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_55 (12578 ms)
11594 00:46:17.727403 [0:04:52.886373016] [405] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11595 00:46:17.827253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_55 RESULT=pass>
11596 00:46:17.828013 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_55 RESULT=pass
11598 00:46:17.842648 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_89
11599 00:46:37.435701 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_89 (19718 ms)
11600 00:46:37.445673 [0:05:12.607425864] [405] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11601 00:46:37.531566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_89 RESULT=pass>
11602 00:46:37.531866 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_89 RESULT=pass
11604 00:46:37.544188 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_1
11605 00:46:37.849179 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_1 (414 ms)
11606 00:46:37.861794 [0:05:13.023291941] [405] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11607 00:46:37.948831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_1 RESULT=pass>
11608 00:46:37.949116 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_1 RESULT=pass
11610 00:46:37.965948 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_2
11611 00:46:38.336100 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_2 (487 ms)
11612 00:46:38.349347 [0:05:13.511018941] [405] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11613 00:46:38.432116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_2 RESULT=pass>
11614 00:46:38.432424 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_2 RESULT=pass
11616 00:46:38.446033 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_3
11617 00:46:38.900078 [0:05:14.064422249] [405] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11618 00:46:38.905735 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_3 (555 ms)
11619 00:46:38.989401 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_3 RESULT=pass>
11620 00:46:38.989685 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_3 RESULT=pass
11622 00:46:39.003900 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_5
11623 00:46:39.594093 [0:05:14.759209018] [405] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11624 00:46:39.600638 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_5 (694 ms)
11625 00:46:39.680052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_5 RESULT=pass>
11626 00:46:39.680370 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_5 RESULT=pass
11628 00:46:39.695248 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_8
11629 00:46:40.499836 [0:05:15.664809941] [405] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11630 00:46:40.506827 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_8 (905 ms)
11631 00:46:40.587350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_8 RESULT=pass>
11632 00:46:40.587656 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_8 RESULT=pass
11634 00:46:40.603462 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_13
11635 00:46:41.754382 [0:05:16.919522479] [405] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11636 00:46:41.760999 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_13 (1254 ms)
11637 00:46:41.846488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_13 RESULT=pass>
11638 00:46:41.846839 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_13 RESULT=pass
11640 00:46:41.862984 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_21
11641 00:46:43.569309 [0:05:18.734854941] [405] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11642 00:46:43.576390 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_21 (1815 ms)
11643 00:46:43.666320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_21 RESULT=pass>
11644 00:46:43.666622 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_21 RESULT=pass
11646 00:46:43.681359 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_34
11647 00:46:46.295193 [0:05:21.460354864] [405] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11648 00:46:46.301359 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_34 (2725 ms)
11649 00:46:46.402900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_34 RESULT=pass>
11650 00:46:46.403634 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_34 RESULT=pass
11652 00:46:46.421093 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_55
11653 00:46:50.481042 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_55 (4194 ms)
11654 00:46:50.494382 [0:05:25.654220942] [405] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11655 00:46:50.574453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_55 RESULT=pass>
11656 00:46:50.574761 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_55 RESULT=pass
11658 00:46:50.589116 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_89
11659 00:46:57.064079 [0:05:32.230544173] [405] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11660 00:46:57.070357 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_89 (6575 ms)
11661 00:46:57.175718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_89 RESULT=pass>
11662 00:46:57.176514 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_89 RESULT=pass
11664 00:46:57.194777 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_1
11665 00:46:57.478814 [0:05:32.645512173] [405] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11666 00:46:57.485425 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_1 (414 ms)
11667 00:46:57.590967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_1 RESULT=pass>
11668 00:46:57.591661 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_1 RESULT=pass
11670 00:46:57.605369 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_2
11671 00:46:57.963240 [0:05:33.130146634] [405] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11672 00:46:57.969761 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_2 (484 ms)
11673 00:46:58.072989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_2 RESULT=pass>
11674 00:46:58.073743 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_2 RESULT=pass
11676 00:46:58.088434 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_3
11677 00:46:58.518124 [0:05:33.684958173] [405] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11678 00:46:58.524911 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_3 (554 ms)
11679 00:46:58.622261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_3 RESULT=pass>
11680 00:46:58.622546 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_3 RESULT=pass
11682 00:46:58.633632 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_5
11683 00:46:59.213014 [0:05:34.379789942] [405] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11684 00:46:59.219592 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_5 (694 ms)
11685 00:46:59.322255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_5 RESULT=pass>
11686 00:46:59.323093 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_5 RESULT=pass
11688 00:46:59.338079 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_8
11689 00:47:00.119479 [0:05:35.286205481] [405] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11690 00:47:00.126312 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_8 (906 ms)
11691 00:47:00.228804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_8 RESULT=pass>
11692 00:47:00.229507 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_8 RESULT=pass
11694 00:47:00.243700 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_13
11695 00:47:01.374488 [0:05:36.541463788] [405] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11696 00:47:01.380855 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_13 (1255 ms)
11697 00:47:01.481571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_13 RESULT=pass>
11698 00:47:01.482272 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_13 RESULT=pass
11700 00:47:01.496395 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_21
11701 00:47:03.189617 [0:05:38.356583096] [405] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11702 00:47:03.195545 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_21 (1815 ms)
11703 00:47:03.290614 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_21 RESULT=pass>
11704 00:47:03.290940 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_21 RESULT=pass
11706 00:47:03.303071 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_34
11707 00:47:05.915451 [0:05:41.083376712] [405] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11708 00:47:05.921818 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_34 (2726 ms)
11709 00:47:06.012780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_34 RESULT=pass>
11710 00:47:06.013500 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_34 RESULT=pass
11712 00:47:06.027394 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_55
11713 00:47:10.110395 [0:05:45.278879943] [405] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11714 00:47:10.116743 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_55 (4195 ms)
11715 00:47:10.203131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_55 RESULT=pass>
11716 00:47:10.203449 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_55 RESULT=pass
11718 00:47:10.216779 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_89
11719 00:47:16.686019 [0:05:51.854932251] [405] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11720 00:47:16.692738 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_89 (6575 ms)
11721 00:47:16.781834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_89 RESULT=pass>
11722 00:47:16.782161 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_89 RESULT=pass
11724 00:47:16.795378 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_1
11725 00:47:17.099995 [0:05:52.269212405] [405] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11726 00:47:17.106556 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_1 (414 ms)
11727 00:47:17.195562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_1 RESULT=pass>
11728 00:47:17.196275 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_1 RESULT=pass
11730 00:47:17.211000 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_2
11731 00:47:17.585164 [0:05:52.754293328] [405] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11732 00:47:17.591418 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_2 (484 ms)
11733 00:47:17.673851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_2 RESULT=pass>
11734 00:47:17.674188 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_2 RESULT=pass
11736 00:47:17.684483 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_3
11737 00:47:18.140375 [0:05:53.309793097] [405] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11738 00:47:18.146956 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_3 (555 ms)
11739 00:47:18.236762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_3 RESULT=pass>
11740 00:47:18.237130 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_3 RESULT=pass
11742 00:47:18.249168 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_5
11743 00:47:18.835411 [0:05:54.004955789] [405] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11744 00:47:18.841865 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_5 (695 ms)
11745 00:47:18.928637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_5 RESULT=pass>
11746 00:47:18.928955 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_5 RESULT=pass
11748 00:47:18.940869 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_8
11749 00:47:19.742978 [0:05:54.911918174] [405] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11750 00:47:19.749219 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_8 (906 ms)
11751 00:47:19.840152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_8 RESULT=pass>
11752 00:47:19.840476 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_8 RESULT=pass
11754 00:47:19.851705 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_13
11755 00:47:20.997065 [0:05:56.166644405] [405] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11756 00:47:21.003560 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_13 (1254 ms)
11757 00:47:21.086029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_13 RESULT=pass>
11758 00:47:21.086378 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_13 RESULT=pass
11760 00:47:21.096986 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_21
11761 00:47:22.811267 [0:05:57.981330943] [405] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11762 00:47:22.817905 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_21 (1814 ms)
11763 00:47:22.906145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_21 RESULT=pass>
11764 00:47:22.906474 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_21 RESULT=pass
11766 00:47:22.918857 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_34
11767 00:47:25.536322 [0:06:00.706182944] [405] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11768 00:47:25.542394 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_34 (2724 ms)
11769 00:47:25.631411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_34 RESULT=pass>
11770 00:47:25.631738 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_34 RESULT=pass
11772 00:47:25.642621 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_55
11773 00:47:29.730615 [0:06:04.901313021] [405] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11774 00:47:29.737490 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_55 (4194 ms)
11775 00:47:29.823137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_55 RESULT=pass>
11776 00:47:29.823473 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_55 RESULT=pass
11778 00:47:29.836294 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_89
11779 00:47:36.306500 [0:06:11.477142098] [405] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11780 00:47:36.313455 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_89 (6575 ms)
11781 00:47:36.397804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_89 RESULT=pass>
11782 00:47:36.398129 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_89 RESULT=pass
11784 00:47:36.410390 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_1
11785 00:47:36.720692 [0:06:11.892092098] [405] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11786 00:47:36.727113 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_1 (414 ms)
11787 00:47:36.812244 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_1 RESULT=pass
11789 00:47:36.815527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_1 RESULT=pass>
11790 00:47:36.828924 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_2
11791 00:47:37.206107 [0:06:12.377413944] [405] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11792 00:47:37.212507 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_2 (485 ms)
11793 00:47:37.297472 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_2 RESULT=pass
11795 00:47:37.299993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_2 RESULT=pass>
11796 00:47:37.312720 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_3
11797 00:47:37.760521 [0:06:12.932210252] [405] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11798 00:47:37.767511 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_3 (554 ms)
11799 00:47:37.850286 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_3 RESULT=pass
11801 00:47:37.852991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_3 RESULT=pass>
11802 00:47:37.865255 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_5
11803 00:47:38.455761 [0:06:13.627252560] [405] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11804 00:47:38.462586 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_5 (694 ms)
11805 00:47:38.546239 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_5 RESULT=pass
11807 00:47:38.548999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_5 RESULT=pass>
11808 00:47:38.561730 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_8
11809 00:47:39.360908 [0:06:14.532732714] [405] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11810 00:47:39.368141 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_8 (905 ms)
11811 00:47:39.452179 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_8 RESULT=pass
11813 00:47:39.454804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_8 RESULT=pass>
11814 00:47:39.467161 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_13
11815 00:47:40.615454 [0:06:15.787504021] [405] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11816 00:47:40.622056 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_13 (1254 ms)
11817 00:47:40.708397 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_13 RESULT=pass
11819 00:47:40.711559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_13 RESULT=pass>
11820 00:47:40.723689 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_21
11821 00:47:42.430625 [0:06:17.602724560] [405] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11822 00:47:42.437465 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_21 (1815 ms)
11823 00:47:42.524068 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_21 RESULT=pass
11825 00:47:42.527328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_21 RESULT=pass>
11826 00:47:42.540506 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_34
11827 00:47:45.156183 [0:06:20.328227945] [405] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11828 00:47:45.162097 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_34 (2725 ms)
11829 00:47:45.255725 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_34 RESULT=pass
11831 00:47:45.258138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_34 RESULT=pass>
11832 00:47:45.270863 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_55
11833 00:47:49.350737 [0:06:24.523529483] [405] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11834 00:47:49.357635 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_55 (4195 ms)
11835 00:47:49.453782 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_55 RESULT=pass
11837 00:47:49.456556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_55 RESULT=pass>
11838 00:47:49.472561 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_89
11839 00:47:55.921566 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_89 (6575 ms)
11840 00:47:56.021847 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_89 RESULT=pass
11842 00:47:56.025168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_89 RESULT=pass>
11843 00:47:56.039259 [----------] 120 tests from CaptureTests/SingleStream (369820 ms total)
11844 00:47:56.126997
11845 00:47:56.220987 [----------] Global test environment tear-down
11846 00:47:56.310730 [==========] 120 tests from 1 test suite ran. (369820 ms total)
11847 00:47:56.400429 <LAVA_SIGNAL_TESTSET STOP>
11848 00:47:56.401209 Received signal: <TESTSET> STOP
11849 00:47:56.401618 Closing test_set CaptureTests/SingleStream
11850 00:47:56.403812 + set +x
11851 00:47:56.406916 <LAVA_SIGNAL_ENDRUN 0_lc-compliance 14368371_1.6.2.3.1>
11852 00:47:56.407588 Received signal: <ENDRUN> 0_lc-compliance 14368371_1.6.2.3.1
11853 00:47:56.407981 Ending use of test pattern.
11854 00:47:56.408336 Ending test lava.0_lc-compliance (14368371_1.6.2.3.1), duration 372.18
11856 00:47:56.410367 <LAVA_TEST_RUNNER EXIT>
11857 00:47:56.411065 ok: lava_test_shell seems to have completed
11858 00:47:56.420242 Capture/Raw_1:
result: skip
set: CaptureTests/SingleStream
Capture/Raw_13:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_2:
result: skip
set: CaptureTests/SingleStream
Capture/Raw_21:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_3:
result: skip
set: CaptureTests/SingleStream
Capture/Raw_34:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_5:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_55:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_8:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_89:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_1:
result: skip
set: CaptureTests/SingleStream
Capture/StillCapture_13:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_2:
result: skip
set: CaptureTests/SingleStream
Capture/StillCapture_21:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_3:
result: skip
set: CaptureTests/SingleStream
Capture/StillCapture_34:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_5:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_55:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_8:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_89:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_1:
result: skip
set: CaptureTests/SingleStream
Capture/VideoRecording_13:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_2:
result: skip
set: CaptureTests/SingleStream
Capture/VideoRecording_21:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_3:
result: skip
set: CaptureTests/SingleStream
Capture/VideoRecording_34:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_5:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_55:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_8:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_89:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_1:
result: skip
set: CaptureTests/SingleStream
Capture/Viewfinder_13:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_2:
result: skip
set: CaptureTests/SingleStream
Capture/Viewfinder_21:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_3:
result: skip
set: CaptureTests/SingleStream
Capture/Viewfinder_34:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_5:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_55:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_8:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Raw_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Raw_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Raw_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_89:
result: pass
set: CaptureTests/SingleStream
11859 00:47:56.421114 end: 3.1 lava-test-shell (duration 00:06:13) [common]
11860 00:47:56.421597 end: 3 lava-test-retry (duration 00:06:13) [common]
11861 00:47:56.422041 start: 4 finalize (timeout 00:10:00) [common]
11862 00:47:56.422477 start: 4.1 power-off (timeout 00:00:30) [common]
11863 00:47:56.423284 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-2', '--port=1', '--command=off']
11864 00:47:56.676928 >> Command sent successfully.
11865 00:47:56.686865 Returned 0 in 0 seconds
11866 00:47:56.788206 end: 4.1 power-off (duration 00:00:00) [common]
11868 00:47:56.789952 start: 4.2 read-feedback (timeout 00:10:00) [common]
11869 00:47:56.791342 Listened to connection for namespace 'common' for up to 1s
11870 00:47:57.791456 Finalising connection for namespace 'common'
11871 00:47:57.792142 Disconnecting from shell: Finalise
11872 00:47:57.792596 / #
11873 00:47:57.893775 end: 4.2 read-feedback (duration 00:00:01) [common]
11874 00:47:57.894512 end: 4 finalize (duration 00:00:01) [common]
11875 00:47:57.895116 Cleaning after the job
11876 00:47:57.895639 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14368371/tftp-deploy-8gvq5l49/ramdisk
11877 00:47:57.900207 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14368371/tftp-deploy-8gvq5l49/kernel
11878 00:47:57.910619 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14368371/tftp-deploy-8gvq5l49/dtb
11879 00:47:57.910784 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14368371/tftp-deploy-8gvq5l49/nfsrootfs
11880 00:47:57.951442 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14368371/tftp-deploy-8gvq5l49/modules
11881 00:47:57.956919 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14368371
11882 00:47:58.214947 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14368371
11883 00:47:58.215127 Job finished correctly