Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 22
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 24
1 00:39:35.912911 lava-dispatcher, installed at version: 2024.03
2 00:39:35.913131 start: 0 validate
3 00:39:35.913270 Start time: 2024-06-16 00:39:35.913262+00:00 (UTC)
4 00:39:35.913389 Using caching service: 'http://localhost/cache/?uri=%s'
5 00:39:35.913521 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 00:39:36.165185 Using caching service: 'http://localhost/cache/?uri=%s'
7 00:39:36.165466 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22-24-g0315de64ea248%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 00:39:36.423356 Using caching service: 'http://localhost/cache/?uri=%s'
9 00:39:36.424192 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22-24-g0315de64ea248%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 00:40:07.831908 Using caching service: 'http://localhost/cache/?uri=%s'
11 00:40:07.832550 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22-24-g0315de64ea248%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 00:40:08.333008 validate duration: 32.42
14 00:40:08.333268 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 00:40:08.333375 start: 1.1 download-retry (timeout 00:10:00) [common]
16 00:40:08.333469 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 00:40:08.333597 Not decompressing ramdisk as can be used compressed.
18 00:40:08.333680 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 00:40:08.333744 saving as /var/lib/lava/dispatcher/tmp/14368366/tftp-deploy-h8e7f32o/ramdisk/rootfs.cpio.gz
20 00:40:08.333810 total size: 8181887 (7 MB)
21 00:40:11.206944 progress 0 % (0 MB)
22 00:40:11.219525 progress 5 % (0 MB)
23 00:40:11.231281 progress 10 % (0 MB)
24 00:40:11.241185 progress 15 % (1 MB)
25 00:40:11.247042 progress 20 % (1 MB)
26 00:40:11.251938 progress 25 % (1 MB)
27 00:40:11.255796 progress 30 % (2 MB)
28 00:40:11.259522 progress 35 % (2 MB)
29 00:40:11.262741 progress 40 % (3 MB)
30 00:40:11.265902 progress 45 % (3 MB)
31 00:40:11.268579 progress 50 % (3 MB)
32 00:40:11.271288 progress 55 % (4 MB)
33 00:40:11.273666 progress 60 % (4 MB)
34 00:40:11.276131 progress 65 % (5 MB)
35 00:40:11.278359 progress 70 % (5 MB)
36 00:40:11.280566 progress 75 % (5 MB)
37 00:40:11.282624 progress 80 % (6 MB)
38 00:40:11.284787 progress 85 % (6 MB)
39 00:40:11.286822 progress 90 % (7 MB)
40 00:40:11.288980 progress 95 % (7 MB)
41 00:40:11.291037 progress 100 % (7 MB)
42 00:40:11.291232 7 MB downloaded in 2.96 s (2.64 MB/s)
43 00:40:11.291383 end: 1.1.1 http-download (duration 00:00:03) [common]
45 00:40:11.291619 end: 1.1 download-retry (duration 00:00:03) [common]
46 00:40:11.291705 start: 1.2 download-retry (timeout 00:09:57) [common]
47 00:40:11.291787 start: 1.2.1 http-download (timeout 00:09:57) [common]
48 00:40:11.291924 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-24-g0315de64ea248/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 00:40:11.291993 saving as /var/lib/lava/dispatcher/tmp/14368366/tftp-deploy-h8e7f32o/kernel/Image
50 00:40:11.292053 total size: 54813184 (52 MB)
51 00:40:11.292113 No compression specified
52 00:40:11.293265 progress 0 % (0 MB)
53 00:40:11.307116 progress 5 % (2 MB)
54 00:40:11.321173 progress 10 % (5 MB)
55 00:40:11.335467 progress 15 % (7 MB)
56 00:40:11.349661 progress 20 % (10 MB)
57 00:40:11.363763 progress 25 % (13 MB)
58 00:40:11.377782 progress 30 % (15 MB)
59 00:40:11.392256 progress 35 % (18 MB)
60 00:40:11.406633 progress 40 % (20 MB)
61 00:40:11.420553 progress 45 % (23 MB)
62 00:40:11.434770 progress 50 % (26 MB)
63 00:40:11.449249 progress 55 % (28 MB)
64 00:40:11.463430 progress 60 % (31 MB)
65 00:40:11.478058 progress 65 % (34 MB)
66 00:40:11.491878 progress 70 % (36 MB)
67 00:40:11.505979 progress 75 % (39 MB)
68 00:40:11.519962 progress 80 % (41 MB)
69 00:40:11.533606 progress 85 % (44 MB)
70 00:40:11.547494 progress 90 % (47 MB)
71 00:40:11.561321 progress 95 % (49 MB)
72 00:40:11.575037 progress 100 % (52 MB)
73 00:40:11.575339 52 MB downloaded in 0.28 s (184.53 MB/s)
74 00:40:11.575500 end: 1.2.1 http-download (duration 00:00:00) [common]
76 00:40:11.575777 end: 1.2 download-retry (duration 00:00:00) [common]
77 00:40:11.575864 start: 1.3 download-retry (timeout 00:09:57) [common]
78 00:40:11.575948 start: 1.3.1 http-download (timeout 00:09:57) [common]
79 00:40:11.576087 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-24-g0315de64ea248/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 00:40:11.576156 saving as /var/lib/lava/dispatcher/tmp/14368366/tftp-deploy-h8e7f32o/dtb/mt8192-asurada-spherion-r0.dtb
81 00:40:11.576217 total size: 47258 (0 MB)
82 00:40:11.576278 No compression specified
83 00:40:11.577408 progress 69 % (0 MB)
84 00:40:11.577680 progress 100 % (0 MB)
85 00:40:11.577840 0 MB downloaded in 0.00 s (27.80 MB/s)
86 00:40:11.577964 end: 1.3.1 http-download (duration 00:00:00) [common]
88 00:40:11.578212 end: 1.3 download-retry (duration 00:00:00) [common]
89 00:40:11.578312 start: 1.4 download-retry (timeout 00:09:57) [common]
90 00:40:11.578392 start: 1.4.1 http-download (timeout 00:09:57) [common]
91 00:40:11.578502 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-24-g0315de64ea248/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 00:40:11.578569 saving as /var/lib/lava/dispatcher/tmp/14368366/tftp-deploy-h8e7f32o/modules/modules.tar
93 00:40:11.578628 total size: 8608736 (8 MB)
94 00:40:11.578688 Using unxz to decompress xz
95 00:40:11.582712 progress 0 % (0 MB)
96 00:40:11.602233 progress 5 % (0 MB)
97 00:40:11.630083 progress 10 % (0 MB)
98 00:40:11.660915 progress 15 % (1 MB)
99 00:40:11.685083 progress 20 % (1 MB)
100 00:40:11.709310 progress 25 % (2 MB)
101 00:40:11.734068 progress 30 % (2 MB)
102 00:40:11.760333 progress 35 % (2 MB)
103 00:40:11.789581 progress 40 % (3 MB)
104 00:40:11.813724 progress 45 % (3 MB)
105 00:40:11.839582 progress 50 % (4 MB)
106 00:40:11.867408 progress 55 % (4 MB)
107 00:40:11.894365 progress 60 % (4 MB)
108 00:40:11.920699 progress 65 % (5 MB)
109 00:40:11.946662 progress 70 % (5 MB)
110 00:40:11.974147 progress 75 % (6 MB)
111 00:40:12.001352 progress 80 % (6 MB)
112 00:40:12.026463 progress 85 % (7 MB)
113 00:40:12.052483 progress 90 % (7 MB)
114 00:40:12.078388 progress 95 % (7 MB)
115 00:40:12.103934 progress 100 % (8 MB)
116 00:40:12.109559 8 MB downloaded in 0.53 s (15.46 MB/s)
117 00:40:12.109818 end: 1.4.1 http-download (duration 00:00:01) [common]
119 00:40:12.110081 end: 1.4 download-retry (duration 00:00:01) [common]
120 00:40:12.110212 start: 1.5 prepare-tftp-overlay (timeout 00:09:56) [common]
121 00:40:12.110309 start: 1.5.1 extract-nfsrootfs (timeout 00:09:56) [common]
122 00:40:12.110391 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 00:40:12.110476 start: 1.5.2 lava-overlay (timeout 00:09:56) [common]
124 00:40:12.110742 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14368366/lava-overlay-y5pdkcn2
125 00:40:12.110911 makedir: /var/lib/lava/dispatcher/tmp/14368366/lava-overlay-y5pdkcn2/lava-14368366/bin
126 00:40:12.111016 makedir: /var/lib/lava/dispatcher/tmp/14368366/lava-overlay-y5pdkcn2/lava-14368366/tests
127 00:40:12.111120 makedir: /var/lib/lava/dispatcher/tmp/14368366/lava-overlay-y5pdkcn2/lava-14368366/results
128 00:40:12.111235 Creating /var/lib/lava/dispatcher/tmp/14368366/lava-overlay-y5pdkcn2/lava-14368366/bin/lava-add-keys
129 00:40:12.111382 Creating /var/lib/lava/dispatcher/tmp/14368366/lava-overlay-y5pdkcn2/lava-14368366/bin/lava-add-sources
130 00:40:12.111519 Creating /var/lib/lava/dispatcher/tmp/14368366/lava-overlay-y5pdkcn2/lava-14368366/bin/lava-background-process-start
131 00:40:12.111650 Creating /var/lib/lava/dispatcher/tmp/14368366/lava-overlay-y5pdkcn2/lava-14368366/bin/lava-background-process-stop
132 00:40:12.111775 Creating /var/lib/lava/dispatcher/tmp/14368366/lava-overlay-y5pdkcn2/lava-14368366/bin/lava-common-functions
133 00:40:12.111899 Creating /var/lib/lava/dispatcher/tmp/14368366/lava-overlay-y5pdkcn2/lava-14368366/bin/lava-echo-ipv4
134 00:40:12.112025 Creating /var/lib/lava/dispatcher/tmp/14368366/lava-overlay-y5pdkcn2/lava-14368366/bin/lava-install-packages
135 00:40:12.112153 Creating /var/lib/lava/dispatcher/tmp/14368366/lava-overlay-y5pdkcn2/lava-14368366/bin/lava-installed-packages
136 00:40:12.112282 Creating /var/lib/lava/dispatcher/tmp/14368366/lava-overlay-y5pdkcn2/lava-14368366/bin/lava-os-build
137 00:40:12.112412 Creating /var/lib/lava/dispatcher/tmp/14368366/lava-overlay-y5pdkcn2/lava-14368366/bin/lava-probe-channel
138 00:40:12.112553 Creating /var/lib/lava/dispatcher/tmp/14368366/lava-overlay-y5pdkcn2/lava-14368366/bin/lava-probe-ip
139 00:40:12.112723 Creating /var/lib/lava/dispatcher/tmp/14368366/lava-overlay-y5pdkcn2/lava-14368366/bin/lava-target-ip
140 00:40:12.112863 Creating /var/lib/lava/dispatcher/tmp/14368366/lava-overlay-y5pdkcn2/lava-14368366/bin/lava-target-mac
141 00:40:12.112992 Creating /var/lib/lava/dispatcher/tmp/14368366/lava-overlay-y5pdkcn2/lava-14368366/bin/lava-target-storage
142 00:40:12.113123 Creating /var/lib/lava/dispatcher/tmp/14368366/lava-overlay-y5pdkcn2/lava-14368366/bin/lava-test-case
143 00:40:12.113247 Creating /var/lib/lava/dispatcher/tmp/14368366/lava-overlay-y5pdkcn2/lava-14368366/bin/lava-test-event
144 00:40:12.113368 Creating /var/lib/lava/dispatcher/tmp/14368366/lava-overlay-y5pdkcn2/lava-14368366/bin/lava-test-feedback
145 00:40:12.113495 Creating /var/lib/lava/dispatcher/tmp/14368366/lava-overlay-y5pdkcn2/lava-14368366/bin/lava-test-raise
146 00:40:12.113618 Creating /var/lib/lava/dispatcher/tmp/14368366/lava-overlay-y5pdkcn2/lava-14368366/bin/lava-test-reference
147 00:40:12.113740 Creating /var/lib/lava/dispatcher/tmp/14368366/lava-overlay-y5pdkcn2/lava-14368366/bin/lava-test-runner
148 00:40:12.113861 Creating /var/lib/lava/dispatcher/tmp/14368366/lava-overlay-y5pdkcn2/lava-14368366/bin/lava-test-set
149 00:40:12.113994 Creating /var/lib/lava/dispatcher/tmp/14368366/lava-overlay-y5pdkcn2/lava-14368366/bin/lava-test-shell
150 00:40:12.114122 Updating /var/lib/lava/dispatcher/tmp/14368366/lava-overlay-y5pdkcn2/lava-14368366/bin/lava-install-packages (oe)
151 00:40:12.114287 Updating /var/lib/lava/dispatcher/tmp/14368366/lava-overlay-y5pdkcn2/lava-14368366/bin/lava-installed-packages (oe)
152 00:40:12.114422 Creating /var/lib/lava/dispatcher/tmp/14368366/lava-overlay-y5pdkcn2/lava-14368366/environment
153 00:40:12.114561 LAVA metadata
154 00:40:12.114661 - LAVA_JOB_ID=14368366
155 00:40:12.114758 - LAVA_DISPATCHER_IP=192.168.201.1
156 00:40:12.114899 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:56) [common]
157 00:40:12.114995 skipped lava-vland-overlay
158 00:40:12.115100 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 00:40:12.115212 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:56) [common]
160 00:40:12.115305 skipped lava-multinode-overlay
161 00:40:12.115386 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 00:40:12.115482 start: 1.5.2.3 test-definition (timeout 00:09:56) [common]
163 00:40:12.115567 Loading test definitions
164 00:40:12.115661 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:56) [common]
165 00:40:12.115736 Using /lava-14368366 at stage 0
166 00:40:12.116149 uuid=14368366_1.5.2.3.1 testdef=None
167 00:40:12.116280 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 00:40:12.116401 start: 1.5.2.3.2 test-overlay (timeout 00:09:56) [common]
169 00:40:12.116969 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 00:40:12.117202 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:56) [common]
172 00:40:12.117845 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 00:40:12.118075 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:56) [common]
175 00:40:12.118816 runner path: /var/lib/lava/dispatcher/tmp/14368366/lava-overlay-y5pdkcn2/lava-14368366/0/tests/0_dmesg test_uuid 14368366_1.5.2.3.1
176 00:40:12.118975 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 00:40:12.119189 Creating lava-test-runner.conf files
179 00:40:12.119254 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14368366/lava-overlay-y5pdkcn2/lava-14368366/0 for stage 0
180 00:40:12.119349 - 0_dmesg
181 00:40:12.119445 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 00:40:12.119531 start: 1.5.2.4 compress-overlay (timeout 00:09:56) [common]
183 00:40:12.127373 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 00:40:12.127496 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:56) [common]
185 00:40:12.127585 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 00:40:12.127673 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 00:40:12.127760 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:56) [common]
188 00:40:12.375537 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:00) [common]
189 00:40:12.375923 start: 1.5.4 extract-modules (timeout 00:09:56) [common]
190 00:40:12.376036 extracting modules file /var/lib/lava/dispatcher/tmp/14368366/tftp-deploy-h8e7f32o/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14368366/extract-overlay-ramdisk-o88_6hru/ramdisk
191 00:40:12.598027 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 00:40:12.598216 start: 1.5.5 apply-overlay-tftp (timeout 00:09:56) [common]
193 00:40:12.598320 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14368366/compress-overlay-px31comv/overlay-1.5.2.4.tar.gz to ramdisk
194 00:40:12.598392 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14368366/compress-overlay-px31comv/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14368366/extract-overlay-ramdisk-o88_6hru/ramdisk
195 00:40:12.605040 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 00:40:12.605170 start: 1.5.6 configure-preseed-file (timeout 00:09:56) [common]
197 00:40:12.605261 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 00:40:12.605356 start: 1.5.7 compress-ramdisk (timeout 00:09:56) [common]
199 00:40:12.605440 Building ramdisk /var/lib/lava/dispatcher/tmp/14368366/extract-overlay-ramdisk-o88_6hru/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14368366/extract-overlay-ramdisk-o88_6hru/ramdisk
200 00:40:13.026991 >> 145187 blocks
201 00:40:15.362641 rename /var/lib/lava/dispatcher/tmp/14368366/extract-overlay-ramdisk-o88_6hru/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14368366/tftp-deploy-h8e7f32o/ramdisk/ramdisk.cpio.gz
202 00:40:15.363199 end: 1.5.7 compress-ramdisk (duration 00:00:03) [common]
203 00:40:15.363375 start: 1.5.8 prepare-kernel (timeout 00:09:53) [common]
204 00:40:15.363519 start: 1.5.8.1 prepare-fit (timeout 00:09:53) [common]
205 00:40:15.363675 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14368366/tftp-deploy-h8e7f32o/kernel/Image']
206 00:40:29.993721 Returned 0 in 14 seconds
207 00:40:30.094444 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14368366/tftp-deploy-h8e7f32o/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14368366/tftp-deploy-h8e7f32o/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14368366/tftp-deploy-h8e7f32o/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14368366/tftp-deploy-h8e7f32o/kernel/image.itb
208 00:40:30.521141 output: FIT description: Kernel Image image with one or more FDT blobs
209 00:40:30.521586 output: Created: Sun Jun 16 01:40:30 2024
210 00:40:30.521703 output: Image 0 (kernel-1)
211 00:40:30.521800 output: Description:
212 00:40:30.521891 output: Created: Sun Jun 16 01:40:30 2024
213 00:40:30.521984 output: Type: Kernel Image
214 00:40:30.522079 output: Compression: lzma compressed
215 00:40:30.522197 output: Data Size: 13126376 Bytes = 12818.73 KiB = 12.52 MiB
216 00:40:30.522312 output: Architecture: AArch64
217 00:40:30.522425 output: OS: Linux
218 00:40:30.522552 output: Load Address: 0x00000000
219 00:40:30.522678 output: Entry Point: 0x00000000
220 00:40:30.522802 output: Hash algo: crc32
221 00:40:30.522906 output: Hash value: c791a20a
222 00:40:30.523014 output: Image 1 (fdt-1)
223 00:40:30.523121 output: Description: mt8192-asurada-spherion-r0
224 00:40:30.523210 output: Created: Sun Jun 16 01:40:30 2024
225 00:40:30.523296 output: Type: Flat Device Tree
226 00:40:30.523382 output: Compression: uncompressed
227 00:40:30.523468 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
228 00:40:30.523554 output: Architecture: AArch64
229 00:40:30.523638 output: Hash algo: crc32
230 00:40:30.523724 output: Hash value: 0f8e4d2e
231 00:40:30.523809 output: Image 2 (ramdisk-1)
232 00:40:30.523893 output: Description: unavailable
233 00:40:30.523979 output: Created: Sun Jun 16 01:40:30 2024
234 00:40:30.524064 output: Type: RAMDisk Image
235 00:40:30.524149 output: Compression: Unknown Compression
236 00:40:30.524233 output: Data Size: 21377299 Bytes = 20876.27 KiB = 20.39 MiB
237 00:40:30.524319 output: Architecture: AArch64
238 00:40:30.524403 output: OS: Linux
239 00:40:30.524538 output: Load Address: unavailable
240 00:40:30.524669 output: Entry Point: unavailable
241 00:40:30.524812 output: Hash algo: crc32
242 00:40:30.524912 output: Hash value: 2ded4bfd
243 00:40:30.524997 output: Default Configuration: 'conf-1'
244 00:40:30.525081 output: Configuration 0 (conf-1)
245 00:40:30.525165 output: Description: mt8192-asurada-spherion-r0
246 00:40:30.525250 output: Kernel: kernel-1
247 00:40:30.525336 output: Init Ramdisk: ramdisk-1
248 00:40:30.525423 output: FDT: fdt-1
249 00:40:30.525508 output: Loadables: kernel-1
250 00:40:30.525593 output:
251 00:40:30.525868 end: 1.5.8.1 prepare-fit (duration 00:00:15) [common]
252 00:40:30.526012 end: 1.5.8 prepare-kernel (duration 00:00:15) [common]
253 00:40:30.526190 end: 1.5 prepare-tftp-overlay (duration 00:00:18) [common]
254 00:40:30.526345 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:38) [common]
255 00:40:30.526499 No LXC device requested
256 00:40:30.526621 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 00:40:30.526776 start: 1.7 deploy-device-env (timeout 00:09:38) [common]
258 00:40:30.526970 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 00:40:30.527077 Checking files for TFTP limit of 4294967296 bytes.
260 00:40:30.527823 end: 1 tftp-deploy (duration 00:00:22) [common]
261 00:40:30.527974 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 00:40:30.528111 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 00:40:30.528289 substitutions:
264 00:40:30.528392 - {DTB}: 14368366/tftp-deploy-h8e7f32o/dtb/mt8192-asurada-spherion-r0.dtb
265 00:40:30.528510 - {INITRD}: 14368366/tftp-deploy-h8e7f32o/ramdisk/ramdisk.cpio.gz
266 00:40:30.528619 - {KERNEL}: 14368366/tftp-deploy-h8e7f32o/kernel/Image
267 00:40:30.528711 - {LAVA_MAC}: None
268 00:40:30.528801 - {PRESEED_CONFIG}: None
269 00:40:30.528889 - {PRESEED_LOCAL}: None
270 00:40:30.528978 - {RAMDISK}: 14368366/tftp-deploy-h8e7f32o/ramdisk/ramdisk.cpio.gz
271 00:40:30.529067 - {ROOT_PART}: None
272 00:40:30.529156 - {ROOT}: None
273 00:40:30.529242 - {SERVER_IP}: 192.168.201.1
274 00:40:30.529331 - {TEE}: None
275 00:40:30.529420 Parsed boot commands:
276 00:40:30.529508 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 00:40:30.529773 Parsed boot commands: tftpboot 192.168.201.1 14368366/tftp-deploy-h8e7f32o/kernel/image.itb 14368366/tftp-deploy-h8e7f32o/kernel/cmdline
278 00:40:30.529918 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 00:40:30.530044 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 00:40:30.530203 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 00:40:30.530356 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 00:40:30.530513 Not connected, no need to disconnect.
283 00:40:30.530705 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 00:40:30.530826 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 00:40:30.530933 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-9'
286 00:40:30.535869 Setting prompt string to ['lava-test: # ']
287 00:40:30.536407 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 00:40:30.536581 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 00:40:30.536761 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 00:40:30.536928 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 00:40:30.537214 Calling: ['/usr/local/bin/chromebook-reboot.sh', 'mt8192-asurada-spherion-r0-cbg-9']
292 00:40:44.517248 Returned 0 in 13 seconds
293 00:40:44.618242 end: 2.2.2.1 pdu-reboot (duration 00:00:14) [common]
295 00:40:44.618563 end: 2.2.2 reset-device (duration 00:00:14) [common]
296 00:40:44.618663 start: 2.2.3 depthcharge-start (timeout 00:04:46) [common]
297 00:40:44.618752 Setting prompt string to 'Starting depthcharge on Spherion...'
298 00:40:44.618817 Changing prompt to 'Starting depthcharge on Spherion...'
299 00:40:44.618883 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
300 00:40:44.619336 [Enter `^Ec?' for help]
301 00:40:44.619420 �
302 00:40:44.619498
303 00:40:44.619560 F0: 102B 0000
304 00:40:44.619620
305 00:40:44.619675 F3: 1001 0000 [0200]
306 00:40:44.619733
307 00:40:44.619790 F3: 1001 0000
308 00:40:44.619849
309 00:40:44.619905 F7: 102D 0000
310 00:40:44.619960
311 00:40:44.620013 F1: 0000 0000
312 00:40:44.620066
313 00:40:44.620118 V0: 0000 0000 [0001]
314 00:40:44.620171
315 00:40:44.620223 00: 0007 8000
316 00:40:44.620278
317 00:40:44.620331 01: 0000 0000
318 00:40:44.620385
319 00:40:44.620437 BP: 0C00 0209 [0000]
320 00:40:44.620489
321 00:40:44.620540 G0: 1182 0000
322 00:40:44.620592
323 00:40:44.620644 EC: 0000 0021 [4000]
324 00:40:44.620695
325 00:40:44.620762 S7: 0000 0000 [0000]
326 00:40:44.620828
327 00:40:44.620880 CC: 0000 0000 [0001]
328 00:40:44.620932
329 00:40:44.620984 T0: 0000 0040 [010F]
330 00:40:44.621115
331 00:40:44.621210 Jump to BL
332 00:40:44.621266
333 00:40:44.621319
334 00:40:44.621372
335 00:40:44.621425 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
336 00:40:44.621506 ARM64: Exception handlers installed.
337 00:40:44.621575 ARM64: Testing exception
338 00:40:44.621629 ARM64: Done test exception
339 00:40:44.621684 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
340 00:40:44.621740 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
341 00:40:44.621794 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
342 00:40:44.621848 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
343 00:40:44.621905 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
344 00:40:44.621959 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
345 00:40:44.622012 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
346 00:40:44.622065 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
347 00:40:44.622119 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
348 00:40:44.622197 WDT: Last reset was cold boot
349 00:40:44.622266 SPI1(PAD0) initialized at 2873684 Hz
350 00:40:44.622320 SPI5(PAD0) initialized at 992727 Hz
351 00:40:44.622373 VBOOT: Loading verstage.
352 00:40:44.622425 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
353 00:40:44.622477 FMAP: Found "FLASH" version 1.1 at 0x20000.
354 00:40:44.622531 FMAP: base = 0x0 size = 0x800000 #areas = 25
355 00:40:44.622584 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
356 00:40:44.622637 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
357 00:40:44.622690 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
358 00:40:44.622743 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
359 00:40:44.622795
360 00:40:44.622847
361 00:40:44.622900 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
362 00:40:44.622953 ARM64: Exception handlers installed.
363 00:40:44.623021 ARM64: Testing exception
364 00:40:44.623088 ARM64: Done test exception
365 00:40:44.623155 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
366 00:40:44.623210 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
367 00:40:44.623307 Probing TPM: . done!
368 00:40:44.623359 TPM ready after 0 ms
369 00:40:44.623411 Connected to device vid:did:rid of 1ae0:0028:00
370 00:40:44.623529 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
371 00:40:44.623583 Initialized TPM device CR50 revision 0
372 00:40:44.623668 tlcl_send_startup: Startup return code is 0
373 00:40:44.623756 TPM: setup succeeded
374 00:40:44.623827 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
375 00:40:44.623881 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
376 00:40:44.623935 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
377 00:40:44.623989 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 00:40:44.624042 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
379 00:40:44.624097 in-header: 03 07 00 00 08 00 00 00
380 00:40:44.624151 in-data: aa e4 47 04 13 02 00 00
381 00:40:44.624204 Chrome EC: UHEPI supported
382 00:40:44.624257 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
383 00:40:44.624311 in-header: 03 a9 00 00 08 00 00 00
384 00:40:44.624365 in-data: 84 60 60 08 00 00 00 00
385 00:40:44.624419 Phase 1
386 00:40:44.624472 FMAP: area GBB found @ 3f5000 (12032 bytes)
387 00:40:44.624527 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
388 00:40:44.624582 VB2:vb2_check_recovery() Recovery was requested manually
389 00:40:44.624637 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x7
390 00:40:44.624691 Recovery requested (1009000e)
391 00:40:44.624745 TPM: Extending digest for VBOOT: boot mode into PCR 0
392 00:40:44.624804 tlcl_extend: response is 0
393 00:40:44.624899 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
394 00:40:44.624975 tlcl_extend: response is 0
395 00:40:44.625032 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
396 00:40:44.625107 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
397 00:40:44.625162 BS: bootblock times (exec / console): total (unknown) / 148 ms
398 00:40:44.625217
399 00:40:44.625270
400 00:40:44.625323 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
401 00:40:44.625574 ARM64: Exception handlers installed.
402 00:40:44.625655 ARM64: Testing exception
403 00:40:44.625765 ARM64: Done test exception
404 00:40:44.625859 pmic_efuse_setting: Set efuses in 11 msecs
405 00:40:44.625947 pmwrap_interface_init: Select PMIF_VLD_RDY
406 00:40:44.626031 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
407 00:40:44.626120 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
408 00:40:44.626235 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
409 00:40:44.626290 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
410 00:40:44.626346 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
411 00:40:44.626400 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
412 00:40:44.626454 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
413 00:40:44.626510 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
414 00:40:44.626563 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
415 00:40:44.626616 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
416 00:40:44.626669 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
417 00:40:44.626722 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
418 00:40:44.626774 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
419 00:40:44.626827 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
420 00:40:44.626880 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
421 00:40:44.626933 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
422 00:40:44.626986 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
423 00:40:44.627039 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
424 00:40:44.627091 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
425 00:40:44.627148 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
426 00:40:44.627200 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
427 00:40:44.627253 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
428 00:40:44.627306 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
429 00:40:44.627358 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
430 00:40:44.627410 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
431 00:40:44.627463 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
432 00:40:44.627515 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
433 00:40:44.627567 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
434 00:40:44.627620 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
435 00:40:44.627671 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
436 00:40:44.627724 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
437 00:40:44.627779 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
438 00:40:44.627832 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
439 00:40:44.627884 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
440 00:40:44.627936 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
441 00:40:44.627989 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
442 00:40:44.628041 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
443 00:40:44.628094 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
444 00:40:44.628146 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
445 00:40:44.628198 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
446 00:40:44.628250 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
447 00:40:44.628302 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
448 00:40:44.628354 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
449 00:40:44.628407 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
450 00:40:44.628459 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
451 00:40:44.628510 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
452 00:40:44.628562 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
453 00:40:44.628615 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
454 00:40:44.628667 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
455 00:40:44.628722 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
456 00:40:44.628775 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
457 00:40:44.628828 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x6b6d 0x5bf0 0x8100 0x4c 0xf0f 0x9248
458 00:40:44.628881 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
459 00:40:44.628934 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
460 00:40:44.628987 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
461 00:40:44.629040 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
462 00:40:44.629093 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
463 00:40:44.629146 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
464 00:40:44.629198 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 00:40:44.629251 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6c, sec=0x29
466 00:40:44.629303 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
467 00:40:44.629356 [RTC]rtc_osc_init,62: osc32con val = 0xde6c
468 00:40:44.629408 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
469 00:40:44.629461 [RTC]rtc_get_frequency_meter,154: input=15, output=836
470 00:40:44.629513 [RTC]rtc_get_frequency_meter,154: input=7, output=709
471 00:40:44.629565 [RTC]rtc_get_frequency_meter,154: input=11, output=772
472 00:40:44.629812 [RTC]rtc_get_frequency_meter,154: input=13, output=804
473 00:40:44.629941 [RTC]rtc_get_frequency_meter,154: input=12, output=788
474 00:40:44.630054 [RTC]rtc_get_frequency_meter,154: input=12, output=787
475 00:40:44.630138 [RTC]rtc_get_frequency_meter,154: input=13, output=804
476 00:40:44.630237 [RTC]rtc_eosc_cali,47: left: 12, middle: 12, right: 13
477 00:40:44.630291 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6c
478 00:40:44.630344 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
479 00:40:44.630397 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
480 00:40:44.630449 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
481 00:40:44.630502 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
482 00:40:44.630554 ADC[4]: Raw value=901922 ID=7
483 00:40:44.630606 ADC[3]: Raw value=213652 ID=1
484 00:40:44.630658 RAM Code: 0x71
485 00:40:44.630711 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
486 00:40:44.630764 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
487 00:40:44.630817 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
488 00:40:44.630871 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
489 00:40:44.630923 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
490 00:40:44.630976 in-header: 03 07 00 00 08 00 00 00
491 00:40:44.631028 in-data: aa e4 47 04 13 02 00 00
492 00:40:44.631080 Chrome EC: UHEPI supported
493 00:40:44.631132 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
494 00:40:44.631185 in-header: 03 a9 00 00 08 00 00 00
495 00:40:44.631237 in-data: 84 60 60 08 00 00 00 00
496 00:40:44.631289 MRC: failed to locate region type 0.
497 00:40:44.631342 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
498 00:40:44.631395 DRAM-K: Running full calibration
499 00:40:44.631448 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
500 00:40:44.631500 header.status = 0x0
501 00:40:44.631552 header.version = 0x6 (expected: 0x6)
502 00:40:44.631604 header.size = 0xd00 (expected: 0xd00)
503 00:40:44.631657 header.flags = 0x0
504 00:40:44.631708 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
505 00:40:44.631761 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
506 00:40:44.631814 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
507 00:40:44.631866 dram_init: ddr_geometry: 2
508 00:40:44.631918 [EMI] MDL number = 2
509 00:40:44.631970 [EMI] Get MDL freq = 0
510 00:40:44.632022 dram_init: ddr_type: 0
511 00:40:44.632073 is_discrete_lpddr4: 1
512 00:40:44.632124 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
513 00:40:44.632176
514 00:40:44.632228
515 00:40:44.632279 [Bian_co] ETT version 0.0.0.1
516 00:40:44.632330 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
517 00:40:44.632383
518 00:40:44.632435 dramc_set_vcore_voltage set vcore to 650000
519 00:40:44.632487 Read voltage for 800, 4
520 00:40:44.632539 Vio18 = 0
521 00:40:44.632591 Vcore = 650000
522 00:40:44.632642 Vdram = 0
523 00:40:44.632693 Vddq = 0
524 00:40:44.632745 Vmddr = 0
525 00:40:44.632796 dram_init: config_dvfs: 1
526 00:40:44.632847 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
527 00:40:44.632899 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
528 00:40:44.632951 [SwImpedanceCal] DRVP=8, DRVN=16, ODTN=9
529 00:40:44.633003 freq_region=0, Reg: DRVP=8, DRVN=16, ODTN=9
530 00:40:44.633056 [SwImpedanceCal] DRVP=14, DRVN=24, ODTN=9
531 00:40:44.633107 freq_region=1, Reg: DRVP=14, DRVN=24, ODTN=9
532 00:40:44.633160 MEM_TYPE=3, freq_sel=18
533 00:40:44.633227 sv_algorithm_assistance_LP4_1600
534 00:40:44.633294 ============ PULL DRAM RESETB DOWN ============
535 00:40:44.633346 ========== PULL DRAM RESETB DOWN end =========
536 00:40:44.633399 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
537 00:40:44.633451 ===================================
538 00:40:44.633503 LPDDR4 DRAM CONFIGURATION
539 00:40:44.633554 ===================================
540 00:40:44.633607 EX_ROW_EN[0] = 0x0
541 00:40:44.633658 EX_ROW_EN[1] = 0x0
542 00:40:44.633710 LP4Y_EN = 0x0
543 00:40:44.633761 WORK_FSP = 0x0
544 00:40:44.633813 WL = 0x2
545 00:40:44.633864 RL = 0x2
546 00:40:44.633916 BL = 0x2
547 00:40:44.633968 RPST = 0x0
548 00:40:44.634020 RD_PRE = 0x0
549 00:40:44.634072 WR_PRE = 0x1
550 00:40:44.634124 WR_PST = 0x0
551 00:40:44.634199 DBI_WR = 0x0
552 00:40:44.634267 DBI_RD = 0x0
553 00:40:44.634318 OTF = 0x1
554 00:40:44.634371 ===================================
555 00:40:44.634423 ===================================
556 00:40:44.634475 ANA top config
557 00:40:44.634527 ===================================
558 00:40:44.634579 DLL_ASYNC_EN = 0
559 00:40:44.634631 ALL_SLAVE_EN = 1
560 00:40:44.634683 NEW_RANK_MODE = 1
561 00:40:44.634739 DLL_IDLE_MODE = 1
562 00:40:44.634791 LP45_APHY_COMB_EN = 1
563 00:40:44.634843 TX_ODT_DIS = 1
564 00:40:44.634895 NEW_8X_MODE = 1
565 00:40:44.634947 ===================================
566 00:40:44.635000 ===================================
567 00:40:44.635052 data_rate = 1600
568 00:40:44.635104 CKR = 1
569 00:40:44.635156 DQ_P2S_RATIO = 8
570 00:40:44.635208 ===================================
571 00:40:44.635260 CA_P2S_RATIO = 8
572 00:40:44.635312 DQ_CA_OPEN = 0
573 00:40:44.635364 DQ_SEMI_OPEN = 0
574 00:40:44.635415 CA_SEMI_OPEN = 0
575 00:40:44.635467 CA_FULL_RATE = 0
576 00:40:44.635519 DQ_CKDIV4_EN = 1
577 00:40:44.635570 CA_CKDIV4_EN = 1
578 00:40:44.635622 CA_PREDIV_EN = 0
579 00:40:44.635674 PH8_DLY = 0
580 00:40:44.635726 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
581 00:40:44.635804 DQ_AAMCK_DIV = 4
582 00:40:44.635859 CA_AAMCK_DIV = 4
583 00:40:44.635925 CA_ADMCK_DIV = 4
584 00:40:44.635977 DQ_TRACK_CA_EN = 0
585 00:40:44.636029 CA_PICK = 800
586 00:40:44.636097 CA_MCKIO = 800
587 00:40:44.636163 MCKIO_SEMI = 0
588 00:40:44.636452 PLL_FREQ = 3068
589 00:40:44.636545 DQ_UI_PI_RATIO = 32
590 00:40:44.636601 CA_UI_PI_RATIO = 0
591 00:40:44.636655 ===================================
592 00:40:44.636710 ===================================
593 00:40:44.636763 memory_type:LPDDR4
594 00:40:44.636817 GP_NUM : 10
595 00:40:44.636871 SRAM_EN : 1
596 00:40:44.636925 MD32_EN : 0
597 00:40:44.636978 ===================================
598 00:40:44.637032 [ANA_INIT] >>>>>>>>>>>>>>
599 00:40:44.637085 <<<<<< [CONFIGURE PHASE]: ANA_TX
600 00:40:44.637142 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
601 00:40:44.637196 ===================================
602 00:40:44.637262 data_rate = 1600,PCW = 0X7600
603 00:40:44.637315 ===================================
604 00:40:44.637367 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
605 00:40:44.637419 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
606 00:40:44.637472 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 00:40:44.637525 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
608 00:40:44.637578 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
609 00:40:44.637631 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
610 00:40:44.637684 [ANA_INIT] flow start
611 00:40:44.637736 [ANA_INIT] PLL >>>>>>>>
612 00:40:44.637788 [ANA_INIT] PLL <<<<<<<<
613 00:40:44.637840 [ANA_INIT] MIDPI >>>>>>>>
614 00:40:44.637892 [ANA_INIT] MIDPI <<<<<<<<
615 00:40:44.637944 [ANA_INIT] DLL >>>>>>>>
616 00:40:44.637995 [ANA_INIT] flow end
617 00:40:44.638046 ============ LP4 DIFF to SE enter ============
618 00:40:44.638099 ============ LP4 DIFF to SE exit ============
619 00:40:44.638152 [ANA_INIT] <<<<<<<<<<<<<
620 00:40:44.638245 [Flow] Enable top DCM control >>>>>
621 00:40:44.638298 [Flow] Enable top DCM control <<<<<
622 00:40:44.638351 Enable DLL master slave shuffle
623 00:40:44.638404 ==============================================================
624 00:40:44.638456 Gating Mode config
625 00:40:44.638507 ==============================================================
626 00:40:44.638560 Config description:
627 00:40:44.638611 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
628 00:40:44.638665 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
629 00:40:44.638718 SELPH_MODE 0: By rank 1: By Phase
630 00:40:44.638771 ==============================================================
631 00:40:44.638823 GAT_TRACK_EN = 1
632 00:40:44.638875 RX_GATING_MODE = 2
633 00:40:44.638927 RX_GATING_TRACK_MODE = 2
634 00:40:44.638979 SELPH_MODE = 1
635 00:40:44.639030 PICG_EARLY_EN = 1
636 00:40:44.639118 VALID_LAT_VALUE = 1
637 00:40:44.639196 ==============================================================
638 00:40:44.639255 Enter into Gating configuration >>>>
639 00:40:44.639309 Exit from Gating configuration <<<<
640 00:40:44.639393 Enter into DVFS_PRE_config >>>>>
641 00:40:44.639446 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
642 00:40:44.639502 Exit from DVFS_PRE_config <<<<<
643 00:40:44.639555 Enter into PICG configuration >>>>
644 00:40:44.639607 Exit from PICG configuration <<<<
645 00:40:44.639659 [RX_INPUT] configuration >>>>>
646 00:40:44.639711 [RX_INPUT] configuration <<<<<
647 00:40:44.639764 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
648 00:40:44.639817 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
649 00:40:44.639869 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
650 00:40:44.639921 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
651 00:40:44.639973 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
652 00:40:44.640026 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
653 00:40:44.640078 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
654 00:40:44.640130 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
655 00:40:44.640182 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
656 00:40:44.640235 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
657 00:40:44.640286 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
658 00:40:44.640339 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
659 00:40:44.640391 ===================================
660 00:40:44.640443 LPDDR4 DRAM CONFIGURATION
661 00:40:44.640495 ===================================
662 00:40:44.640547 EX_ROW_EN[0] = 0x0
663 00:40:44.640599 EX_ROW_EN[1] = 0x0
664 00:40:44.640651 LP4Y_EN = 0x0
665 00:40:44.640703 WORK_FSP = 0x0
666 00:40:44.640755 WL = 0x2
667 00:40:44.640806 RL = 0x2
668 00:40:44.640858 BL = 0x2
669 00:40:44.640912 RPST = 0x0
670 00:40:44.640964 RD_PRE = 0x0
671 00:40:44.641016 WR_PRE = 0x1
672 00:40:44.641067 WR_PST = 0x0
673 00:40:44.641119 DBI_WR = 0x0
674 00:40:44.641171 DBI_RD = 0x0
675 00:40:44.641222 OTF = 0x1
676 00:40:44.641275 ===================================
677 00:40:44.641327 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
678 00:40:44.641380 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
679 00:40:44.641432 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
680 00:40:44.641485 ===================================
681 00:40:44.641537 LPDDR4 DRAM CONFIGURATION
682 00:40:44.641589 ===================================
683 00:40:44.641642 EX_ROW_EN[0] = 0x10
684 00:40:44.641694 EX_ROW_EN[1] = 0x0
685 00:40:44.641746 LP4Y_EN = 0x0
686 00:40:44.641798 WORK_FSP = 0x0
687 00:40:44.641850 WL = 0x2
688 00:40:44.641901 RL = 0x2
689 00:40:44.641952 BL = 0x2
690 00:40:44.642004 RPST = 0x0
691 00:40:44.642055 RD_PRE = 0x0
692 00:40:44.642106 WR_PRE = 0x1
693 00:40:44.642222 WR_PST = 0x0
694 00:40:44.642295 DBI_WR = 0x0
695 00:40:44.642348 DBI_RD = 0x0
696 00:40:44.642400 OTF = 0x1
697 00:40:44.642452 ===================================
698 00:40:44.642706 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
699 00:40:44.642765 nWR fixed to 40
700 00:40:44.642819 [ModeRegInit_LP4] CH0 RK0
701 00:40:44.642873 [ModeRegInit_LP4] CH0 RK1
702 00:40:44.642925 [ModeRegInit_LP4] CH1 RK0
703 00:40:44.642977 [ModeRegInit_LP4] CH1 RK1
704 00:40:44.643029 match AC timing 13
705 00:40:44.643081 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
706 00:40:44.643134 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
707 00:40:44.643186 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
708 00:40:44.643239 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
709 00:40:44.643292 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
710 00:40:44.643344 [EMI DOE] emi_dcm 0
711 00:40:44.643396 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
712 00:40:44.643448 ==
713 00:40:44.643500 Dram Type= 6, Freq= 0, CH_0, rank 0
714 00:40:44.643553 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
715 00:40:44.643605 ==
716 00:40:44.643658 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
717 00:40:44.643710 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
718 00:40:44.643763 [CA 0] Center 37 (6~68) winsize 63
719 00:40:44.643815 [CA 1] Center 37 (7~68) winsize 62
720 00:40:44.643868 [CA 2] Center 34 (4~65) winsize 62
721 00:40:44.643920 [CA 3] Center 34 (4~65) winsize 62
722 00:40:44.643971 [CA 4] Center 33 (3~64) winsize 62
723 00:40:44.644023 [CA 5] Center 33 (3~64) winsize 62
724 00:40:44.644074
725 00:40:44.644126 [CmdBusTrainingLP45] Vref(ca) range 1: 32
726 00:40:44.644178
727 00:40:44.644230 [CATrainingPosCal] consider 1 rank data
728 00:40:44.644283 u2DelayCellTimex100 = 270/100 ps
729 00:40:44.644335 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
730 00:40:44.644387 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
731 00:40:44.644439 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
732 00:40:44.644492 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
733 00:40:44.644544 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
734 00:40:44.644596 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
735 00:40:44.644647
736 00:40:44.644699 CA PerBit enable=1, Macro0, CA PI delay=33
737 00:40:44.644751
738 00:40:44.644803 [CBTSetCACLKResult] CA Dly = 33
739 00:40:44.644855 CS Dly: 6 (0~37)
740 00:40:44.644907 ==
741 00:40:44.644959 Dram Type= 6, Freq= 0, CH_0, rank 1
742 00:40:44.645011 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
743 00:40:44.645064 ==
744 00:40:44.645116 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
745 00:40:44.645169 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
746 00:40:44.645221 [CA 0] Center 37 (6~68) winsize 63
747 00:40:44.645273 [CA 1] Center 37 (7~68) winsize 62
748 00:40:44.645325 [CA 2] Center 34 (4~65) winsize 62
749 00:40:44.645377 [CA 3] Center 34 (4~65) winsize 62
750 00:40:44.645429 [CA 4] Center 33 (3~64) winsize 62
751 00:40:44.645481 [CA 5] Center 33 (3~64) winsize 62
752 00:40:44.645532
753 00:40:44.645584 [CmdBusTrainingLP45] Vref(ca) range 1: 32
754 00:40:44.645636
755 00:40:44.645688 [CATrainingPosCal] consider 2 rank data
756 00:40:44.645740 u2DelayCellTimex100 = 270/100 ps
757 00:40:44.645792 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
758 00:40:44.645844 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
759 00:40:44.645896 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
760 00:40:44.645949 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
761 00:40:44.646001 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
762 00:40:44.646052 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
763 00:40:44.646104
764 00:40:44.646155 CA PerBit enable=1, Macro0, CA PI delay=33
765 00:40:44.646257
766 00:40:44.646310 [CBTSetCACLKResult] CA Dly = 33
767 00:40:44.646362 CS Dly: 6 (0~38)
768 00:40:44.646414
769 00:40:44.646466 ----->DramcWriteLeveling(PI) begin...
770 00:40:44.646520 ==
771 00:40:44.646572 Dram Type= 6, Freq= 0, CH_0, rank 0
772 00:40:44.646625 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
773 00:40:44.646678 ==
774 00:40:44.646730 Write leveling (Byte 0): 34 => 34
775 00:40:44.646783 Write leveling (Byte 1): 29 => 29
776 00:40:44.646835 DramcWriteLeveling(PI) end<-----
777 00:40:44.646888
778 00:40:44.646975 ==
779 00:40:44.647028 Dram Type= 6, Freq= 0, CH_0, rank 0
780 00:40:44.647081 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
781 00:40:44.647133 ==
782 00:40:44.647185 [Gating] SW mode calibration
783 00:40:44.647307 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
784 00:40:44.647401 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
785 00:40:44.647486 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
786 00:40:44.647570 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
787 00:40:44.647655 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
788 00:40:44.647722 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 00:40:44.647776 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 00:40:44.647829 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 00:40:44.647881 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 00:40:44.647934 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 00:40:44.647986 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 00:40:44.648039 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 00:40:44.648091 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 00:40:44.648143 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 00:40:44.648195 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 00:40:44.648247 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 00:40:44.648299 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 00:40:44.648352 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 00:40:44.648404 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 00:40:44.648456 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 00:40:44.648508 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
804 00:40:44.648560 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 00:40:44.648613 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 00:40:44.648664 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 00:40:44.648716 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 00:40:44.648969 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 00:40:44.649031 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 00:40:44.649085 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 00:40:44.649139 0 9 8 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (0 0)
812 00:40:44.649192 0 9 12 | B1->B0 | 2b2b 3434 | 0 1 | (0 0) (1 1)
813 00:40:44.649244 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
814 00:40:44.649297 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 00:40:44.649349 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 00:40:44.649402 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 00:40:44.649454 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 00:40:44.649507 0 10 4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
819 00:40:44.649559 0 10 8 | B1->B0 | 3232 2c2c | 1 1 | (1 1) (1 0)
820 00:40:44.649611 0 10 12 | B1->B0 | 2a2a 2323 | 0 0 | (1 1) (0 0)
821 00:40:44.649663 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 00:40:44.649716 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 00:40:44.649768 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 00:40:44.649860 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 00:40:44.649929 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 00:40:44.650012 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 00:40:44.650066 0 11 8 | B1->B0 | 2424 3b3b | 0 0 | (0 0) (0 0)
828 00:40:44.650119 0 11 12 | B1->B0 | 4040 4646 | 1 0 | (0 0) (0 0)
829 00:40:44.650185 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
830 00:40:44.650253 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 00:40:44.650305 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 00:40:44.650357 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 00:40:44.650409 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 00:40:44.650461 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 00:40:44.650513 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
836 00:40:44.650565 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
837 00:40:44.650617 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 00:40:44.650669 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 00:40:44.650721 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 00:40:44.650773 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 00:40:44.650825 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 00:40:44.650877 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 00:40:44.650947 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 00:40:44.651030 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 00:40:44.651096 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 00:40:44.651148 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 00:40:44.651201 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 00:40:44.651254 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 00:40:44.651307 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 00:40:44.651359 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 00:40:44.651411 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
852 00:40:44.651463 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
853 00:40:44.651515 Total UI for P1: 0, mck2ui 16
854 00:40:44.651568 best dqsien dly found for B0: ( 0, 14, 8)
855 00:40:44.651620 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
856 00:40:44.651672 Total UI for P1: 0, mck2ui 16
857 00:40:44.651724 best dqsien dly found for B1: ( 0, 14, 10)
858 00:40:44.651776 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
859 00:40:44.651828 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
860 00:40:44.651881
861 00:40:44.651933 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
862 00:40:44.651985 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
863 00:40:44.652037 [Gating] SW calibration Done
864 00:40:44.652089 ==
865 00:40:44.652141 Dram Type= 6, Freq= 0, CH_0, rank 0
866 00:40:44.652193 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
867 00:40:44.652246 ==
868 00:40:44.652298 RX Vref Scan: 0
869 00:40:44.652350
870 00:40:44.652402 RX Vref 0 -> 0, step: 1
871 00:40:44.652453
872 00:40:44.652506 RX Delay -130 -> 252, step: 16
873 00:40:44.652558 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
874 00:40:44.652611 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
875 00:40:44.652662 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
876 00:40:44.652714 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
877 00:40:44.652766 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
878 00:40:44.652819 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
879 00:40:44.652870 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
880 00:40:44.652922 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
881 00:40:44.652974 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
882 00:40:44.653026 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
883 00:40:44.653078 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
884 00:40:44.653130 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
885 00:40:44.653182 iDelay=222, Bit 12, Center 69 (-50 ~ 189) 240
886 00:40:44.653234 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
887 00:40:44.653285 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
888 00:40:44.653338 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
889 00:40:44.653389 ==
890 00:40:44.653441 Dram Type= 6, Freq= 0, CH_0, rank 0
891 00:40:44.653493 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
892 00:40:44.653546 ==
893 00:40:44.653598 DQS Delay:
894 00:40:44.653650 DQS0 = 0, DQS1 = 0
895 00:40:44.653702 DQM Delay:
896 00:40:44.653754 DQM0 = 85, DQM1 = 73
897 00:40:44.653807 DQ Delay:
898 00:40:44.653859 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
899 00:40:44.653911 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
900 00:40:44.653963 DQ8 =69, DQ9 =69, DQ10 =69, DQ11 =69
901 00:40:44.654016 DQ12 =69, DQ13 =77, DQ14 =85, DQ15 =77
902 00:40:44.654068
903 00:40:44.654119
904 00:40:44.654181 ==
905 00:40:44.654235 Dram Type= 6, Freq= 0, CH_0, rank 0
906 00:40:44.654288 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
907 00:40:44.654342 ==
908 00:40:44.654395
909 00:40:44.654446
910 00:40:44.654498 TX Vref Scan disable
911 00:40:44.654551 == TX Byte 0 ==
912 00:40:44.654603 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
913 00:40:44.654853 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
914 00:40:44.654917 == TX Byte 1 ==
915 00:40:44.654970 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
916 00:40:44.655023 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
917 00:40:44.655076 ==
918 00:40:44.655130 Dram Type= 6, Freq= 0, CH_0, rank 0
919 00:40:44.655183 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
920 00:40:44.655236 ==
921 00:40:44.655289 TX Vref=22, minBit 1, minWin=27, winSum=441
922 00:40:44.655342 TX Vref=24, minBit 5, minWin=27, winSum=443
923 00:40:44.655395 TX Vref=26, minBit 8, minWin=27, winSum=443
924 00:40:44.655447 TX Vref=28, minBit 8, minWin=27, winSum=447
925 00:40:44.655500 TX Vref=30, minBit 8, minWin=27, winSum=445
926 00:40:44.655553 TX Vref=32, minBit 4, minWin=27, winSum=444
927 00:40:44.655605 [TxChooseVref] Worse bit 8, Min win 27, Win sum 447, Final Vref 28
928 00:40:44.655659
929 00:40:44.655712 Final TX Range 1 Vref 28
930 00:40:44.655765
931 00:40:44.655816 ==
932 00:40:44.655869 Dram Type= 6, Freq= 0, CH_0, rank 0
933 00:40:44.655921 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 00:40:44.655973 ==
935 00:40:44.656026
936 00:40:44.656077
937 00:40:44.656128 TX Vref Scan disable
938 00:40:44.656181 == TX Byte 0 ==
939 00:40:44.656234 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
940 00:40:44.656286 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
941 00:40:44.656338 == TX Byte 1 ==
942 00:40:44.656390 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
943 00:40:44.656447 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
944 00:40:44.656499
945 00:40:44.656551 [DATLAT]
946 00:40:44.656603 Freq=800, CH0 RK0
947 00:40:44.656655
948 00:40:44.656707 DATLAT Default: 0xa
949 00:40:44.656758 0, 0xFFFF, sum = 0
950 00:40:44.656811 1, 0xFFFF, sum = 0
951 00:40:44.656864 2, 0xFFFF, sum = 0
952 00:40:44.656917 3, 0xFFFF, sum = 0
953 00:40:44.656969 4, 0xFFFF, sum = 0
954 00:40:44.657022 5, 0xFFFF, sum = 0
955 00:40:44.657075 6, 0xFFFF, sum = 0
956 00:40:44.657128 7, 0xFFFF, sum = 0
957 00:40:44.657180 8, 0xFFFF, sum = 0
958 00:40:44.657233 9, 0x0, sum = 1
959 00:40:44.657286 10, 0x0, sum = 2
960 00:40:44.657338 11, 0x0, sum = 3
961 00:40:44.657391 12, 0x0, sum = 4
962 00:40:44.657443 best_step = 10
963 00:40:44.657495
964 00:40:44.657547 ==
965 00:40:44.657598 Dram Type= 6, Freq= 0, CH_0, rank 0
966 00:40:44.657651 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
967 00:40:44.657704 ==
968 00:40:44.657756 RX Vref Scan: 1
969 00:40:44.657808
970 00:40:44.657860 Set Vref Range= 32 -> 127
971 00:40:44.657912
972 00:40:44.657963 RX Vref 32 -> 127, step: 1
973 00:40:44.658015
974 00:40:44.658066 RX Delay -95 -> 252, step: 8
975 00:40:44.658118
976 00:40:44.658182 Set Vref, RX VrefLevel [Byte0]: 32
977 00:40:44.658237 [Byte1]: 32
978 00:40:44.658289
979 00:40:44.658341 Set Vref, RX VrefLevel [Byte0]: 33
980 00:40:44.658393 [Byte1]: 33
981 00:40:44.658446
982 00:40:44.658497 Set Vref, RX VrefLevel [Byte0]: 34
983 00:40:44.658550 [Byte1]: 34
984 00:40:44.658601
985 00:40:44.658653 Set Vref, RX VrefLevel [Byte0]: 35
986 00:40:44.658705 [Byte1]: 35
987 00:40:44.658758
988 00:40:44.658811 Set Vref, RX VrefLevel [Byte0]: 36
989 00:40:44.658863 [Byte1]: 36
990 00:40:44.658915
991 00:40:44.658968 Set Vref, RX VrefLevel [Byte0]: 37
992 00:40:44.659020 [Byte1]: 37
993 00:40:44.659071
994 00:40:44.659123 Set Vref, RX VrefLevel [Byte0]: 38
995 00:40:44.659176 [Byte1]: 38
996 00:40:44.659228
997 00:40:44.659280 Set Vref, RX VrefLevel [Byte0]: 39
998 00:40:44.659332 [Byte1]: 39
999 00:40:44.659384
1000 00:40:44.659436 Set Vref, RX VrefLevel [Byte0]: 40
1001 00:40:44.659488 [Byte1]: 40
1002 00:40:44.659539
1003 00:40:44.659591 Set Vref, RX VrefLevel [Byte0]: 41
1004 00:40:44.659643 [Byte1]: 41
1005 00:40:44.659695
1006 00:40:44.659747 Set Vref, RX VrefLevel [Byte0]: 42
1007 00:40:44.659799 [Byte1]: 42
1008 00:40:44.659851
1009 00:40:44.659903 Set Vref, RX VrefLevel [Byte0]: 43
1010 00:40:44.659956 [Byte1]: 43
1011 00:40:44.660008
1012 00:40:44.660060 Set Vref, RX VrefLevel [Byte0]: 44
1013 00:40:44.660113 [Byte1]: 44
1014 00:40:44.660165
1015 00:40:44.660217 Set Vref, RX VrefLevel [Byte0]: 45
1016 00:40:44.660269 [Byte1]: 45
1017 00:40:44.660322
1018 00:40:44.660375 Set Vref, RX VrefLevel [Byte0]: 46
1019 00:40:44.660428 [Byte1]: 46
1020 00:40:44.660479
1021 00:40:44.660531 Set Vref, RX VrefLevel [Byte0]: 47
1022 00:40:44.660582 [Byte1]: 47
1023 00:40:44.660634
1024 00:40:44.660686 Set Vref, RX VrefLevel [Byte0]: 48
1025 00:40:44.660749 [Byte1]: 48
1026 00:40:44.660846
1027 00:40:44.660936 Set Vref, RX VrefLevel [Byte0]: 49
1028 00:40:44.661019 [Byte1]: 49
1029 00:40:44.661100
1030 00:40:44.661183 Set Vref, RX VrefLevel [Byte0]: 50
1031 00:40:44.661238 [Byte1]: 50
1032 00:40:44.661291
1033 00:40:44.661344 Set Vref, RX VrefLevel [Byte0]: 51
1034 00:40:44.661397 [Byte1]: 51
1035 00:40:44.661449
1036 00:40:44.661501 Set Vref, RX VrefLevel [Byte0]: 52
1037 00:40:44.661554 [Byte1]: 52
1038 00:40:44.661606
1039 00:40:44.661658 Set Vref, RX VrefLevel [Byte0]: 53
1040 00:40:44.661710 [Byte1]: 53
1041 00:40:44.661762
1042 00:40:44.661814 Set Vref, RX VrefLevel [Byte0]: 54
1043 00:40:44.661866 [Byte1]: 54
1044 00:40:44.661918
1045 00:40:44.661970 Set Vref, RX VrefLevel [Byte0]: 55
1046 00:40:44.662022 [Byte1]: 55
1047 00:40:44.662074
1048 00:40:44.662125 Set Vref, RX VrefLevel [Byte0]: 56
1049 00:40:44.662204 [Byte1]: 56
1050 00:40:44.662270
1051 00:40:44.662322 Set Vref, RX VrefLevel [Byte0]: 57
1052 00:40:44.662374 [Byte1]: 57
1053 00:40:44.662426
1054 00:40:44.662478 Set Vref, RX VrefLevel [Byte0]: 58
1055 00:40:44.662530 [Byte1]: 58
1056 00:40:44.662583
1057 00:40:44.662634 Set Vref, RX VrefLevel [Byte0]: 59
1058 00:40:44.662686 [Byte1]: 59
1059 00:40:44.662737
1060 00:40:44.662789 Set Vref, RX VrefLevel [Byte0]: 60
1061 00:40:44.662840 [Byte1]: 60
1062 00:40:44.662892
1063 00:40:44.662944 Set Vref, RX VrefLevel [Byte0]: 61
1064 00:40:44.662995 [Byte1]: 61
1065 00:40:44.663047
1066 00:40:44.663099 Set Vref, RX VrefLevel [Byte0]: 62
1067 00:40:44.663150 [Byte1]: 62
1068 00:40:44.663202
1069 00:40:44.663253 Set Vref, RX VrefLevel [Byte0]: 63
1070 00:40:44.663305 [Byte1]: 63
1071 00:40:44.663357
1072 00:40:44.663408 Set Vref, RX VrefLevel [Byte0]: 64
1073 00:40:44.663460 [Byte1]: 64
1074 00:40:44.663512
1075 00:40:44.663563 Set Vref, RX VrefLevel [Byte0]: 65
1076 00:40:44.663615 [Byte1]: 65
1077 00:40:44.663666
1078 00:40:44.663915 Set Vref, RX VrefLevel [Byte0]: 66
1079 00:40:44.663975 [Byte1]: 66
1080 00:40:44.664029
1081 00:40:44.664080 Set Vref, RX VrefLevel [Byte0]: 67
1082 00:40:44.664133 [Byte1]: 67
1083 00:40:44.664185
1084 00:40:44.664237 Set Vref, RX VrefLevel [Byte0]: 68
1085 00:40:44.664289 [Byte1]: 68
1086 00:40:44.664341
1087 00:40:44.664393 Set Vref, RX VrefLevel [Byte0]: 69
1088 00:40:44.664444 [Byte1]: 69
1089 00:40:44.664497
1090 00:40:44.664548 Set Vref, RX VrefLevel [Byte0]: 70
1091 00:40:44.664600 [Byte1]: 70
1092 00:40:44.664652
1093 00:40:44.664703 Set Vref, RX VrefLevel [Byte0]: 71
1094 00:40:44.664755 [Byte1]: 71
1095 00:40:44.664807
1096 00:40:44.664859 Set Vref, RX VrefLevel [Byte0]: 72
1097 00:40:44.664910 [Byte1]: 72
1098 00:40:44.664962
1099 00:40:44.665013 Set Vref, RX VrefLevel [Byte0]: 73
1100 00:40:44.665065 [Byte1]: 73
1101 00:40:44.665117
1102 00:40:44.665206 Set Vref, RX VrefLevel [Byte0]: 74
1103 00:40:44.665269 [Byte1]: 74
1104 00:40:44.665322
1105 00:40:44.665373 Set Vref, RX VrefLevel [Byte0]: 75
1106 00:40:44.665425 [Byte1]: 75
1107 00:40:44.665477
1108 00:40:44.665528 Set Vref, RX VrefLevel [Byte0]: 76
1109 00:40:44.665580 [Byte1]: 76
1110 00:40:44.665631
1111 00:40:44.665683 Set Vref, RX VrefLevel [Byte0]: 77
1112 00:40:44.665734 [Byte1]: 77
1113 00:40:44.665786
1114 00:40:44.665837 Set Vref, RX VrefLevel [Byte0]: 78
1115 00:40:44.665888 [Byte1]: 78
1116 00:40:44.665940
1117 00:40:44.665992 Set Vref, RX VrefLevel [Byte0]: 79
1118 00:40:44.666043 [Byte1]: 79
1119 00:40:44.666095
1120 00:40:44.666146 Set Vref, RX VrefLevel [Byte0]: 80
1121 00:40:44.666242 [Byte1]: 80
1122 00:40:44.666295
1123 00:40:44.666346 Set Vref, RX VrefLevel [Byte0]: 81
1124 00:40:44.666398 [Byte1]: 81
1125 00:40:44.666450
1126 00:40:44.666502 Final RX Vref Byte 0 = 62 to rank0
1127 00:40:44.666554 Final RX Vref Byte 1 = 58 to rank0
1128 00:40:44.666606 Final RX Vref Byte 0 = 62 to rank1
1129 00:40:44.666658 Final RX Vref Byte 1 = 58 to rank1==
1130 00:40:44.666710 Dram Type= 6, Freq= 0, CH_0, rank 0
1131 00:40:44.666762 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1132 00:40:44.666814 ==
1133 00:40:44.666867 DQS Delay:
1134 00:40:44.666918 DQS0 = 0, DQS1 = 0
1135 00:40:44.666970 DQM Delay:
1136 00:40:44.667020 DQM0 = 86, DQM1 = 75
1137 00:40:44.667072 DQ Delay:
1138 00:40:44.667123 DQ0 =84, DQ1 =88, DQ2 =84, DQ3 =84
1139 00:40:44.667175 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =96
1140 00:40:44.667226 DQ8 =68, DQ9 =64, DQ10 =76, DQ11 =68
1141 00:40:44.667278 DQ12 =80, DQ13 =76, DQ14 =88, DQ15 =84
1142 00:40:44.667329
1143 00:40:44.667380
1144 00:40:44.667431 [DQSOSCAuto] RK0, (LSB)MR18= 0x4728, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 392 ps
1145 00:40:44.667484 CH0 RK0: MR19=606, MR18=4728
1146 00:40:44.667536 CH0_RK0: MR19=0x606, MR18=0x4728, DQSOSC=392, MR23=63, INC=96, DEC=64
1147 00:40:44.667588
1148 00:40:44.667639 ----->DramcWriteLeveling(PI) begin...
1149 00:40:44.667692 ==
1150 00:40:44.667763 Dram Type= 6, Freq= 0, CH_0, rank 1
1151 00:40:44.667817 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1152 00:40:44.667870 ==
1153 00:40:44.667922 Write leveling (Byte 0): 33 => 33
1154 00:40:44.667974 Write leveling (Byte 1): 29 => 29
1155 00:40:44.668026 DramcWriteLeveling(PI) end<-----
1156 00:40:44.668077
1157 00:40:44.668128 ==
1158 00:40:44.668180 Dram Type= 6, Freq= 0, CH_0, rank 1
1159 00:40:44.668232 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1160 00:40:44.668283 ==
1161 00:40:44.668335 [Gating] SW mode calibration
1162 00:40:44.668387 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1163 00:40:44.668440 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1164 00:40:44.668492 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1165 00:40:44.668544 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1166 00:40:44.668596 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1167 00:40:44.668648 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1168 00:40:44.668700 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 00:40:44.668752 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 00:40:44.668803 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 00:40:44.668855 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 00:40:44.668906 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 00:40:44.668958 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 00:40:44.669009 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 00:40:44.669060 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 00:40:44.669111 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 00:40:44.669163 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 00:40:44.669214 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 00:40:44.669265 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 00:40:44.669317 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 00:40:44.669368 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1182 00:40:44.669420 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1183 00:40:44.669472 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1184 00:40:44.669524 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1185 00:40:44.669576 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 00:40:44.669627 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 00:40:44.669679 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 00:40:44.669730 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 00:40:44.669781 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 00:40:44.669833 0 9 8 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
1191 00:40:44.669884 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1192 00:40:44.669936 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1193 00:40:44.669988 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1194 00:40:44.670039 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1195 00:40:44.670090 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1196 00:40:44.670142 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1197 00:40:44.670433 0 10 4 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
1198 00:40:44.670494 0 10 8 | B1->B0 | 3030 2323 | 0 0 | (0 1) (0 0)
1199 00:40:44.670547 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1200 00:40:44.670600 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1201 00:40:44.670653 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1202 00:40:44.670704 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1203 00:40:44.670756 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1204 00:40:44.670807 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1205 00:40:44.670859 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1206 00:40:44.670911 0 11 8 | B1->B0 | 2828 4040 | 0 1 | (0 0) (0 0)
1207 00:40:44.670962 0 11 12 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
1208 00:40:44.671014 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1209 00:40:44.671066 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1210 00:40:44.671117 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1211 00:40:44.671168 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1212 00:40:44.671220 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1213 00:40:44.671272 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1214 00:40:44.671324 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 00:40:44.671375 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 00:40:44.671427 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 00:40:44.671479 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 00:40:44.671531 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1219 00:40:44.671582 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1220 00:40:44.671634 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1221 00:40:44.671685 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1222 00:40:44.671775 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1223 00:40:44.671827 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1224 00:40:44.671879 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1225 00:40:44.671930 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1226 00:40:44.671981 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1227 00:40:44.672032 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1228 00:40:44.672084 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1229 00:40:44.672135 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1230 00:40:44.672186 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1231 00:40:44.672237 Total UI for P1: 0, mck2ui 16
1232 00:40:44.672290 best dqsien dly found for B0: ( 0, 14, 6)
1233 00:40:44.672342 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1234 00:40:44.672393 Total UI for P1: 0, mck2ui 16
1235 00:40:44.672445 best dqsien dly found for B1: ( 0, 14, 8)
1236 00:40:44.672497 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1237 00:40:44.672548 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1238 00:40:44.672599
1239 00:40:44.672651 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1240 00:40:44.672703 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1241 00:40:44.672755 [Gating] SW calibration Done
1242 00:40:44.672809 ==
1243 00:40:44.672862 Dram Type= 6, Freq= 0, CH_0, rank 1
1244 00:40:44.672913 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1245 00:40:44.672966 ==
1246 00:40:44.673018 RX Vref Scan: 0
1247 00:40:44.673069
1248 00:40:44.673120 RX Vref 0 -> 0, step: 1
1249 00:40:44.673172
1250 00:40:44.673223 RX Delay -130 -> 252, step: 16
1251 00:40:44.673275 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1252 00:40:44.673327 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1253 00:40:44.673379 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1254 00:40:44.673430 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1255 00:40:44.673481 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1256 00:40:44.673533 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1257 00:40:44.673584 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1258 00:40:44.673635 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1259 00:40:44.673686 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1260 00:40:44.673738 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1261 00:40:44.673789 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1262 00:40:44.673841 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1263 00:40:44.673893 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1264 00:40:44.673944 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1265 00:40:44.673996 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1266 00:40:44.674047 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1267 00:40:44.674099 ==
1268 00:40:44.674150 Dram Type= 6, Freq= 0, CH_0, rank 1
1269 00:40:44.674248 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1270 00:40:44.674301 ==
1271 00:40:44.674353 DQS Delay:
1272 00:40:44.674404 DQS0 = 0, DQS1 = 0
1273 00:40:44.674457 DQM Delay:
1274 00:40:44.674508 DQM0 = 85, DQM1 = 77
1275 00:40:44.674559 DQ Delay:
1276 00:40:44.674611 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
1277 00:40:44.674663 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
1278 00:40:44.674714 DQ8 =69, DQ9 =61, DQ10 =77, DQ11 =69
1279 00:40:44.674765 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1280 00:40:44.674817
1281 00:40:44.674869
1282 00:40:44.674919 ==
1283 00:40:44.674970 Dram Type= 6, Freq= 0, CH_0, rank 1
1284 00:40:44.675022 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1285 00:40:44.675074 ==
1286 00:40:44.675125
1287 00:40:44.675176
1288 00:40:44.675227 TX Vref Scan disable
1289 00:40:44.675278 == TX Byte 0 ==
1290 00:40:44.675330 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1291 00:40:44.675382 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1292 00:40:44.675434 == TX Byte 1 ==
1293 00:40:44.675485 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1294 00:40:44.675537 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1295 00:40:44.675588 ==
1296 00:40:44.675639 Dram Type= 6, Freq= 0, CH_0, rank 1
1297 00:40:44.675690 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1298 00:40:44.675742 ==
1299 00:40:44.675793 TX Vref=22, minBit 8, minWin=27, winSum=443
1300 00:40:44.675844 TX Vref=24, minBit 9, minWin=27, winSum=449
1301 00:40:44.675896 TX Vref=26, minBit 9, minWin=27, winSum=449
1302 00:40:44.675947 TX Vref=28, minBit 9, minWin=27, winSum=447
1303 00:40:44.675999 TX Vref=30, minBit 9, minWin=27, winSum=449
1304 00:40:44.676050 TX Vref=32, minBit 8, minWin=27, winSum=445
1305 00:40:44.676298 [TxChooseVref] Worse bit 9, Min win 27, Win sum 449, Final Vref 24
1306 00:40:44.676363
1307 00:40:44.676415 Final TX Range 1 Vref 24
1308 00:40:44.676467
1309 00:40:44.676519 ==
1310 00:40:44.676570 Dram Type= 6, Freq= 0, CH_0, rank 1
1311 00:40:44.676622 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1312 00:40:44.676673 ==
1313 00:40:44.676724
1314 00:40:44.676775
1315 00:40:44.676825 TX Vref Scan disable
1316 00:40:44.676877 == TX Byte 0 ==
1317 00:40:44.676928 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1318 00:40:44.676980 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1319 00:40:44.677031 == TX Byte 1 ==
1320 00:40:44.677082 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1321 00:40:44.677133 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1322 00:40:44.677185
1323 00:40:44.677237 [DATLAT]
1324 00:40:44.677288 Freq=800, CH0 RK1
1325 00:40:44.677339
1326 00:40:44.677390 DATLAT Default: 0xa
1327 00:40:44.677442 0, 0xFFFF, sum = 0
1328 00:40:44.677494 1, 0xFFFF, sum = 0
1329 00:40:44.677546 2, 0xFFFF, sum = 0
1330 00:40:44.677598 3, 0xFFFF, sum = 0
1331 00:40:44.677650 4, 0xFFFF, sum = 0
1332 00:40:44.677703 5, 0xFFFF, sum = 0
1333 00:40:44.677755 6, 0xFFFF, sum = 0
1334 00:40:44.677806 7, 0xFFFF, sum = 0
1335 00:40:44.677857 8, 0xFFFF, sum = 0
1336 00:40:44.677910 9, 0x0, sum = 1
1337 00:40:44.677962 10, 0x0, sum = 2
1338 00:40:44.678014 11, 0x0, sum = 3
1339 00:40:44.678066 12, 0x0, sum = 4
1340 00:40:44.678117 best_step = 10
1341 00:40:44.678198
1342 00:40:44.678268 ==
1343 00:40:44.678320 Dram Type= 6, Freq= 0, CH_0, rank 1
1344 00:40:44.678372 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1345 00:40:44.678423 ==
1346 00:40:44.678474 RX Vref Scan: 0
1347 00:40:44.678525
1348 00:40:44.678576 RX Vref 0 -> 0, step: 1
1349 00:40:44.678627
1350 00:40:44.678677 RX Delay -111 -> 252, step: 8
1351 00:40:44.678728 iDelay=209, Bit 0, Center 80 (-31 ~ 192) 224
1352 00:40:44.678780 iDelay=209, Bit 1, Center 92 (-23 ~ 208) 232
1353 00:40:44.678831 iDelay=209, Bit 2, Center 80 (-31 ~ 192) 224
1354 00:40:44.678882 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1355 00:40:44.678933 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
1356 00:40:44.678984 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1357 00:40:44.679034 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
1358 00:40:44.679085 iDelay=209, Bit 7, Center 92 (-23 ~ 208) 232
1359 00:40:44.679136 iDelay=209, Bit 8, Center 68 (-47 ~ 184) 232
1360 00:40:44.679187 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
1361 00:40:44.679238 iDelay=209, Bit 10, Center 80 (-39 ~ 200) 240
1362 00:40:44.679289 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
1363 00:40:44.679340 iDelay=209, Bit 12, Center 84 (-31 ~ 200) 232
1364 00:40:44.679391 iDelay=209, Bit 13, Center 84 (-31 ~ 200) 232
1365 00:40:44.679442 iDelay=209, Bit 14, Center 84 (-31 ~ 200) 232
1366 00:40:44.679492 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1367 00:40:44.679543 ==
1368 00:40:44.679594 Dram Type= 6, Freq= 0, CH_0, rank 1
1369 00:40:44.679645 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1370 00:40:44.679696 ==
1371 00:40:44.679747 DQS Delay:
1372 00:40:44.679798 DQS0 = 0, DQS1 = 0
1373 00:40:44.679849 DQM Delay:
1374 00:40:44.679899 DQM0 = 85, DQM1 = 77
1375 00:40:44.679950 DQ Delay:
1376 00:40:44.680001 DQ0 =80, DQ1 =92, DQ2 =80, DQ3 =84
1377 00:40:44.680053 DQ4 =84, DQ5 =76, DQ6 =92, DQ7 =92
1378 00:40:44.680105 DQ8 =68, DQ9 =64, DQ10 =80, DQ11 =68
1379 00:40:44.680155 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =84
1380 00:40:44.680206
1381 00:40:44.680257
1382 00:40:44.680308 [DQSOSCAuto] RK1, (LSB)MR18= 0x4309, (MSB)MR19= 0x606, tDQSOscB0 = 407 ps tDQSOscB1 = 393 ps
1383 00:40:44.680360 CH0 RK1: MR19=606, MR18=4309
1384 00:40:44.680411 CH0_RK1: MR19=0x606, MR18=0x4309, DQSOSC=393, MR23=63, INC=95, DEC=63
1385 00:40:44.680462 [RxdqsGatingPostProcess] freq 800
1386 00:40:44.680513 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1387 00:40:44.680565 Pre-setting of DQS Precalculation
1388 00:40:44.680615 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1389 00:40:44.680666 ==
1390 00:40:44.680717 Dram Type= 6, Freq= 0, CH_1, rank 0
1391 00:40:44.680768 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1392 00:40:44.680819 ==
1393 00:40:44.680870 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1394 00:40:44.680922 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1395 00:40:44.680973 [CA 0] Center 36 (6~67) winsize 62
1396 00:40:44.681024 [CA 1] Center 36 (6~67) winsize 62
1397 00:40:44.681075 [CA 2] Center 34 (4~65) winsize 62
1398 00:40:44.681126 [CA 3] Center 34 (3~65) winsize 63
1399 00:40:44.681176 [CA 4] Center 34 (4~65) winsize 62
1400 00:40:44.681227 [CA 5] Center 34 (3~65) winsize 63
1401 00:40:44.681278
1402 00:40:44.681329 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1403 00:40:44.681380
1404 00:40:44.681431 [CATrainingPosCal] consider 1 rank data
1405 00:40:44.681481 u2DelayCellTimex100 = 270/100 ps
1406 00:40:44.681533 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1407 00:40:44.681584 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1408 00:40:44.681634 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1409 00:40:44.681685 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1410 00:40:44.681736 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1411 00:40:44.681787 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1412 00:40:44.681837
1413 00:40:44.681888 CA PerBit enable=1, Macro0, CA PI delay=34
1414 00:40:44.681938
1415 00:40:44.681989 [CBTSetCACLKResult] CA Dly = 34
1416 00:40:44.682040 CS Dly: 5 (0~36)
1417 00:40:44.682091 ==
1418 00:40:44.682141 Dram Type= 6, Freq= 0, CH_1, rank 1
1419 00:40:44.682233 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1420 00:40:44.682285 ==
1421 00:40:44.682337 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1422 00:40:44.682388 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1423 00:40:44.682439 [CA 0] Center 36 (6~67) winsize 62
1424 00:40:44.682490 [CA 1] Center 36 (6~67) winsize 62
1425 00:40:44.682541 [CA 2] Center 34 (4~65) winsize 62
1426 00:40:44.682591 [CA 3] Center 34 (3~65) winsize 63
1427 00:40:44.682642 [CA 4] Center 34 (4~65) winsize 62
1428 00:40:44.682693 [CA 5] Center 33 (3~64) winsize 62
1429 00:40:44.682743
1430 00:40:44.682794 [CmdBusTrainingLP45] Vref(ca) range 1: 30
1431 00:40:44.682845
1432 00:40:44.682896 [CATrainingPosCal] consider 2 rank data
1433 00:40:44.682947 u2DelayCellTimex100 = 270/100 ps
1434 00:40:44.682998 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1435 00:40:44.683049 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1436 00:40:44.683099 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1437 00:40:44.683150 CA3 delay=34 (3~65),Diff = 1 PI (7 cell)
1438 00:40:44.683201 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1439 00:40:44.683251 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1440 00:40:44.683302
1441 00:40:44.683548 CA PerBit enable=1, Macro0, CA PI delay=33
1442 00:40:44.683605
1443 00:40:44.683658 [CBTSetCACLKResult] CA Dly = 33
1444 00:40:44.683710 CS Dly: 6 (0~38)
1445 00:40:44.683761
1446 00:40:44.683813 ----->DramcWriteLeveling(PI) begin...
1447 00:40:44.683865 ==
1448 00:40:44.683917 Dram Type= 6, Freq= 0, CH_1, rank 0
1449 00:40:44.683968 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1450 00:40:44.684019 ==
1451 00:40:44.684071 Write leveling (Byte 0): 27 => 27
1452 00:40:44.684122 Write leveling (Byte 1): 28 => 28
1453 00:40:44.684173 DramcWriteLeveling(PI) end<-----
1454 00:40:44.684225
1455 00:40:44.684276 ==
1456 00:40:44.684327 Dram Type= 6, Freq= 0, CH_1, rank 0
1457 00:40:44.684379 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1458 00:40:44.684430 ==
1459 00:40:44.684481 [Gating] SW mode calibration
1460 00:40:44.684532 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1461 00:40:44.684584 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1462 00:40:44.684636 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1463 00:40:44.684687 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1464 00:40:44.684739 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 00:40:44.684790 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 00:40:44.684841 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 00:40:44.684892 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 00:40:44.684943 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 00:40:44.684994 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 00:40:44.685045 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 00:40:44.685097 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 00:40:44.685147 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 00:40:44.685198 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 00:40:44.685249 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 00:40:44.685300 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 00:40:44.685351 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 00:40:44.685402 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 00:40:44.685453 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1479 00:40:44.685504 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
1480 00:40:44.685555 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1481 00:40:44.685606 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1482 00:40:44.685657 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1483 00:40:44.685708 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 00:40:44.685759 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 00:40:44.685810 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 00:40:44.685861 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 00:40:44.685912 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 00:40:44.685963 0 9 8 | B1->B0 | 2828 2f2f | 1 0 | (0 0) (0 0)
1489 00:40:44.686013 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1490 00:40:44.686066 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1491 00:40:44.686117 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1492 00:40:44.686220 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1493 00:40:44.686288 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1494 00:40:44.686339 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1495 00:40:44.686390 0 10 4 | B1->B0 | 3434 3232 | 0 0 | (0 0) (0 0)
1496 00:40:44.686441 0 10 8 | B1->B0 | 2525 2525 | 1 0 | (1 0) (0 0)
1497 00:40:44.686491 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1498 00:40:44.686542 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1499 00:40:44.686593 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1500 00:40:44.686645 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1501 00:40:44.686696 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1502 00:40:44.686747 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1503 00:40:44.686798 0 11 4 | B1->B0 | 2424 2f2f | 1 1 | (0 0) (0 0)
1504 00:40:44.686849 0 11 8 | B1->B0 | 3d3d 4141 | 0 0 | (0 0) (0 0)
1505 00:40:44.686901 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1506 00:40:44.686952 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1507 00:40:44.687002 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1508 00:40:44.687053 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1509 00:40:44.687104 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1510 00:40:44.687155 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1511 00:40:44.687206 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1512 00:40:44.687256 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1513 00:40:44.687307 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 00:40:44.687358 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 00:40:44.687409 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1516 00:40:44.687459 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1517 00:40:44.687510 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1518 00:40:44.687561 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1519 00:40:44.687611 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1520 00:40:44.687662 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1521 00:40:44.687713 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1522 00:40:44.687764 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1523 00:40:44.687816 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1524 00:40:44.687867 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1525 00:40:44.687918 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1526 00:40:44.687969 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1527 00:40:44.688020 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1528 00:40:44.688071 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1529 00:40:44.688121 Total UI for P1: 0, mck2ui 16
1530 00:40:44.688173 best dqsien dly found for B0: ( 0, 14, 4)
1531 00:40:44.688416 Total UI for P1: 0, mck2ui 16
1532 00:40:44.688474 best dqsien dly found for B1: ( 0, 14, 6)
1533 00:40:44.688528 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1534 00:40:44.688579 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1535 00:40:44.688630
1536 00:40:44.688681 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1537 00:40:44.688732 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1538 00:40:44.688783 [Gating] SW calibration Done
1539 00:40:44.688835 ==
1540 00:40:44.688886 Dram Type= 6, Freq= 0, CH_1, rank 0
1541 00:40:44.688938 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1542 00:40:44.688990 ==
1543 00:40:44.689041 RX Vref Scan: 0
1544 00:40:44.689092
1545 00:40:44.689142 RX Vref 0 -> 0, step: 1
1546 00:40:44.689193
1547 00:40:44.689243 RX Delay -130 -> 252, step: 16
1548 00:40:44.689294 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1549 00:40:44.689345 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1550 00:40:44.689434 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1551 00:40:44.689518 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1552 00:40:44.689589 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1553 00:40:44.689659 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1554 00:40:44.689725 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1555 00:40:44.689776 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1556 00:40:44.689827 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1557 00:40:44.689878 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1558 00:40:44.689930 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1559 00:40:44.689980 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1560 00:40:44.690032 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1561 00:40:44.690083 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1562 00:40:44.690135 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1563 00:40:44.690223 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1564 00:40:44.690275 ==
1565 00:40:44.690326 Dram Type= 6, Freq= 0, CH_1, rank 0
1566 00:40:44.690377 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1567 00:40:44.690429 ==
1568 00:40:44.690480 DQS Delay:
1569 00:40:44.690531 DQS0 = 0, DQS1 = 0
1570 00:40:44.690581 DQM Delay:
1571 00:40:44.690632 DQM0 = 89, DQM1 = 78
1572 00:40:44.690682 DQ Delay:
1573 00:40:44.690733 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =85
1574 00:40:44.690784 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1575 00:40:44.690835 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1576 00:40:44.690886 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1577 00:40:44.690937
1578 00:40:44.690987
1579 00:40:44.691038 ==
1580 00:40:44.691088 Dram Type= 6, Freq= 0, CH_1, rank 0
1581 00:40:44.691139 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1582 00:40:44.691189 ==
1583 00:40:44.691240
1584 00:40:44.691290
1585 00:40:44.691340 TX Vref Scan disable
1586 00:40:44.691391 == TX Byte 0 ==
1587 00:40:44.691442 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1588 00:40:44.691493 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1589 00:40:44.691545 == TX Byte 1 ==
1590 00:40:44.691596 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1591 00:40:44.691647 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1592 00:40:44.691698 ==
1593 00:40:44.691748 Dram Type= 6, Freq= 0, CH_1, rank 0
1594 00:40:44.691799 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1595 00:40:44.691850 ==
1596 00:40:44.691901 TX Vref=22, minBit 8, minWin=26, winSum=444
1597 00:40:44.691952 TX Vref=24, minBit 9, minWin=27, winSum=449
1598 00:40:44.692004 TX Vref=26, minBit 9, minWin=27, winSum=447
1599 00:40:44.692055 TX Vref=28, minBit 10, minWin=27, winSum=449
1600 00:40:44.692106 TX Vref=30, minBit 8, minWin=27, winSum=447
1601 00:40:44.692158 TX Vref=32, minBit 8, minWin=27, winSum=449
1602 00:40:44.692210 [TxChooseVref] Worse bit 9, Min win 27, Win sum 449, Final Vref 24
1603 00:40:44.692264
1604 00:40:44.692325 Final TX Range 1 Vref 24
1605 00:40:44.692414
1606 00:40:44.692481 ==
1607 00:40:44.692534 Dram Type= 6, Freq= 0, CH_1, rank 0
1608 00:40:44.692586 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1609 00:40:44.692638 ==
1610 00:40:44.692689
1611 00:40:44.692740
1612 00:40:44.692790 TX Vref Scan disable
1613 00:40:44.692842 == TX Byte 0 ==
1614 00:40:44.692893 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1615 00:40:44.692944 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1616 00:40:44.692995 == TX Byte 1 ==
1617 00:40:44.693046 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1618 00:40:44.693097 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1619 00:40:44.693149
1620 00:40:44.693199 [DATLAT]
1621 00:40:44.693250 Freq=800, CH1 RK0
1622 00:40:44.693301
1623 00:40:44.693352 DATLAT Default: 0xa
1624 00:40:44.693403 0, 0xFFFF, sum = 0
1625 00:40:44.693456 1, 0xFFFF, sum = 0
1626 00:40:44.693508 2, 0xFFFF, sum = 0
1627 00:40:44.693560 3, 0xFFFF, sum = 0
1628 00:40:44.693612 4, 0xFFFF, sum = 0
1629 00:40:44.693663 5, 0xFFFF, sum = 0
1630 00:40:44.693715 6, 0xFFFF, sum = 0
1631 00:40:44.693767 7, 0xFFFF, sum = 0
1632 00:40:44.693818 8, 0xFFFF, sum = 0
1633 00:40:44.693870 9, 0x0, sum = 1
1634 00:40:44.693922 10, 0x0, sum = 2
1635 00:40:44.693974 11, 0x0, sum = 3
1636 00:40:44.694025 12, 0x0, sum = 4
1637 00:40:44.694077 best_step = 10
1638 00:40:44.694128
1639 00:40:44.694205 ==
1640 00:40:44.694270 Dram Type= 6, Freq= 0, CH_1, rank 0
1641 00:40:44.694321 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1642 00:40:44.694373 ==
1643 00:40:44.694424 RX Vref Scan: 1
1644 00:40:44.694475
1645 00:40:44.694525 Set Vref Range= 32 -> 127
1646 00:40:44.694577
1647 00:40:44.694628 RX Vref 32 -> 127, step: 1
1648 00:40:44.694679
1649 00:40:44.694729 RX Delay -95 -> 252, step: 8
1650 00:40:44.694780
1651 00:40:44.694831 Set Vref, RX VrefLevel [Byte0]: 32
1652 00:40:44.694882 [Byte1]: 32
1653 00:40:44.694933
1654 00:40:44.694984 Set Vref, RX VrefLevel [Byte0]: 33
1655 00:40:44.695035 [Byte1]: 33
1656 00:40:44.695086
1657 00:40:44.695137 Set Vref, RX VrefLevel [Byte0]: 34
1658 00:40:44.695189 [Byte1]: 34
1659 00:40:44.695240
1660 00:40:44.695290 Set Vref, RX VrefLevel [Byte0]: 35
1661 00:40:44.695341 [Byte1]: 35
1662 00:40:44.695392
1663 00:40:44.695442 Set Vref, RX VrefLevel [Byte0]: 36
1664 00:40:44.695493 [Byte1]: 36
1665 00:40:44.695544
1666 00:40:44.695595 Set Vref, RX VrefLevel [Byte0]: 37
1667 00:40:44.695646 [Byte1]: 37
1668 00:40:44.695697
1669 00:40:44.695748 Set Vref, RX VrefLevel [Byte0]: 38
1670 00:40:44.695799 [Byte1]: 38
1671 00:40:44.695849
1672 00:40:44.695899 Set Vref, RX VrefLevel [Byte0]: 39
1673 00:40:44.695950 [Byte1]: 39
1674 00:40:44.696001
1675 00:40:44.696052 Set Vref, RX VrefLevel [Byte0]: 40
1676 00:40:44.696103 [Byte1]: 40
1677 00:40:44.696154
1678 00:40:44.696204 Set Vref, RX VrefLevel [Byte0]: 41
1679 00:40:44.696255 [Byte1]: 41
1680 00:40:44.696305
1681 00:40:44.696355 Set Vref, RX VrefLevel [Byte0]: 42
1682 00:40:44.696406 [Byte1]: 42
1683 00:40:44.696458
1684 00:40:44.696508 Set Vref, RX VrefLevel [Byte0]: 43
1685 00:40:44.696767 [Byte1]: 43
1686 00:40:44.696828
1687 00:40:44.696880 Set Vref, RX VrefLevel [Byte0]: 44
1688 00:40:44.696933 [Byte1]: 44
1689 00:40:44.696985
1690 00:40:44.697037 Set Vref, RX VrefLevel [Byte0]: 45
1691 00:40:44.697088 [Byte1]: 45
1692 00:40:44.697139
1693 00:40:44.697190 Set Vref, RX VrefLevel [Byte0]: 46
1694 00:40:44.697241 [Byte1]: 46
1695 00:40:44.697293
1696 00:40:44.697344 Set Vref, RX VrefLevel [Byte0]: 47
1697 00:40:44.697395 [Byte1]: 47
1698 00:40:44.697446
1699 00:40:44.697497 Set Vref, RX VrefLevel [Byte0]: 48
1700 00:40:44.697548 [Byte1]: 48
1701 00:40:44.697599
1702 00:40:44.697649 Set Vref, RX VrefLevel [Byte0]: 49
1703 00:40:44.697700 [Byte1]: 49
1704 00:40:44.697751
1705 00:40:44.697801 Set Vref, RX VrefLevel [Byte0]: 50
1706 00:40:44.697853 [Byte1]: 50
1707 00:40:44.697904
1708 00:40:44.697955 Set Vref, RX VrefLevel [Byte0]: 51
1709 00:40:44.698006 [Byte1]: 51
1710 00:40:44.698057
1711 00:40:44.698107 Set Vref, RX VrefLevel [Byte0]: 52
1712 00:40:44.698159 [Byte1]: 52
1713 00:40:44.698252
1714 00:40:44.698303 Set Vref, RX VrefLevel [Byte0]: 53
1715 00:40:44.698354 [Byte1]: 53
1716 00:40:44.698406
1717 00:40:44.698457 Set Vref, RX VrefLevel [Byte0]: 54
1718 00:40:44.698508 [Byte1]: 54
1719 00:40:44.698559
1720 00:40:44.698610 Set Vref, RX VrefLevel [Byte0]: 55
1721 00:40:44.698661 [Byte1]: 55
1722 00:40:44.698713
1723 00:40:44.698763 Set Vref, RX VrefLevel [Byte0]: 56
1724 00:40:44.698814 [Byte1]: 56
1725 00:40:44.698865
1726 00:40:44.698915 Set Vref, RX VrefLevel [Byte0]: 57
1727 00:40:44.698967 [Byte1]: 57
1728 00:40:44.699018
1729 00:40:44.699069 Set Vref, RX VrefLevel [Byte0]: 58
1730 00:40:44.699120 [Byte1]: 58
1731 00:40:44.699171
1732 00:40:44.699222 Set Vref, RX VrefLevel [Byte0]: 59
1733 00:40:44.699273 [Byte1]: 59
1734 00:40:44.699324
1735 00:40:44.699375 Set Vref, RX VrefLevel [Byte0]: 60
1736 00:40:44.699425 [Byte1]: 60
1737 00:40:44.699476
1738 00:40:44.699527 Set Vref, RX VrefLevel [Byte0]: 61
1739 00:40:44.699577 [Byte1]: 61
1740 00:40:44.699628
1741 00:40:44.699678 Set Vref, RX VrefLevel [Byte0]: 62
1742 00:40:44.699729 [Byte1]: 62
1743 00:40:44.699780
1744 00:40:44.699830 Set Vref, RX VrefLevel [Byte0]: 63
1745 00:40:44.699880 [Byte1]: 63
1746 00:40:44.699931
1747 00:40:44.699982 Set Vref, RX VrefLevel [Byte0]: 64
1748 00:40:44.700033 [Byte1]: 64
1749 00:40:44.700084
1750 00:40:44.700135 Set Vref, RX VrefLevel [Byte0]: 65
1751 00:40:44.700186 [Byte1]: 65
1752 00:40:44.700237
1753 00:40:44.700288 Set Vref, RX VrefLevel [Byte0]: 66
1754 00:40:44.700338 [Byte1]: 66
1755 00:40:44.700388
1756 00:40:44.700439 Set Vref, RX VrefLevel [Byte0]: 67
1757 00:40:44.700490 [Byte1]: 67
1758 00:40:44.700541
1759 00:40:44.700592 Set Vref, RX VrefLevel [Byte0]: 68
1760 00:40:44.700643 [Byte1]: 68
1761 00:40:44.700693
1762 00:40:44.700744 Set Vref, RX VrefLevel [Byte0]: 69
1763 00:40:44.700795 [Byte1]: 69
1764 00:40:44.700845
1765 00:40:44.700895 Set Vref, RX VrefLevel [Byte0]: 70
1766 00:40:44.700946 [Byte1]: 70
1767 00:40:44.700997
1768 00:40:44.701047 Set Vref, RX VrefLevel [Byte0]: 71
1769 00:40:44.701098 [Byte1]: 71
1770 00:40:44.701148
1771 00:40:44.701199 Set Vref, RX VrefLevel [Byte0]: 72
1772 00:40:44.701249 [Byte1]: 72
1773 00:40:44.701306
1774 00:40:44.701357 Set Vref, RX VrefLevel [Byte0]: 73
1775 00:40:44.701407 [Byte1]: 73
1776 00:40:44.701457
1777 00:40:44.701508 Set Vref, RX VrefLevel [Byte0]: 74
1778 00:40:44.701558 [Byte1]: 74
1779 00:40:44.701609
1780 00:40:44.701659 Set Vref, RX VrefLevel [Byte0]: 75
1781 00:40:44.701710 [Byte1]: 75
1782 00:40:44.701761
1783 00:40:44.701811 Set Vref, RX VrefLevel [Byte0]: 76
1784 00:40:44.701862 [Byte1]: 76
1785 00:40:44.701912
1786 00:40:44.701963 Final RX Vref Byte 0 = 51 to rank0
1787 00:40:44.702015 Final RX Vref Byte 1 = 64 to rank0
1788 00:40:44.702066 Final RX Vref Byte 0 = 51 to rank1
1789 00:40:44.702117 Final RX Vref Byte 1 = 64 to rank1==
1790 00:40:44.702173 Dram Type= 6, Freq= 0, CH_1, rank 0
1791 00:40:44.702259 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1792 00:40:44.702311 ==
1793 00:40:44.702362 DQS Delay:
1794 00:40:44.702412 DQS0 = 0, DQS1 = 0
1795 00:40:44.702462 DQM Delay:
1796 00:40:44.702513 DQM0 = 86, DQM1 = 78
1797 00:40:44.702563 DQ Delay:
1798 00:40:44.702614 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =80
1799 00:40:44.702665 DQ4 =84, DQ5 =96, DQ6 =96, DQ7 =84
1800 00:40:44.702716 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1801 00:40:44.702766 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =88
1802 00:40:44.702817
1803 00:40:44.702867
1804 00:40:44.702918 [DQSOSCAuto] RK0, (LSB)MR18= 0x301c, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 397 ps
1805 00:40:44.702971 CH1 RK0: MR19=606, MR18=301C
1806 00:40:44.703022 CH1_RK0: MR19=0x606, MR18=0x301C, DQSOSC=397, MR23=63, INC=93, DEC=62
1807 00:40:44.703073
1808 00:40:44.703123 ----->DramcWriteLeveling(PI) begin...
1809 00:40:44.703176 ==
1810 00:40:44.703227 Dram Type= 6, Freq= 0, CH_1, rank 1
1811 00:40:44.703278 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1812 00:40:44.703329 ==
1813 00:40:44.703380 Write leveling (Byte 0): 28 => 28
1814 00:40:44.703432 Write leveling (Byte 1): 28 => 28
1815 00:40:44.703484 DramcWriteLeveling(PI) end<-----
1816 00:40:44.703535
1817 00:40:44.703585 ==
1818 00:40:44.703636 Dram Type= 6, Freq= 0, CH_1, rank 1
1819 00:40:44.703688 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1820 00:40:44.703739 ==
1821 00:40:44.703790 [Gating] SW mode calibration
1822 00:40:44.703841 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1823 00:40:44.703893 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1824 00:40:44.703945 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1825 00:40:44.703996 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1826 00:40:44.704047 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 00:40:44.704098 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 00:40:44.704149 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 00:40:44.704200 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 00:40:44.704251 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 00:40:44.704504 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 00:40:44.704562 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 00:40:44.704615 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 00:40:44.704667 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 00:40:44.704719 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 00:40:44.704770 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 00:40:44.704821 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 00:40:44.704873 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 00:40:44.704924 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 00:40:44.704975 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 00:40:44.705026 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1842 00:40:44.705078 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 00:40:44.705129 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1844 00:40:44.705181 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1845 00:40:44.705232 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1846 00:40:44.705283 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1847 00:40:44.705335 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1848 00:40:44.705386 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1849 00:40:44.705438 0 9 4 | B1->B0 | 2323 2323 | 1 0 | (1 1) (0 0)
1850 00:40:44.705489 0 9 8 | B1->B0 | 2e2e 2424 | 1 1 | (1 1) (1 1)
1851 00:40:44.705541 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1852 00:40:44.705632 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1853 00:40:44.705683 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1854 00:40:44.705735 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1855 00:40:44.705785 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1856 00:40:44.705836 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1857 00:40:44.705888 0 10 4 | B1->B0 | 3434 3434 | 0 1 | (0 1) (1 0)
1858 00:40:44.705939 0 10 8 | B1->B0 | 2929 2e2e | 0 0 | (1 1) (1 1)
1859 00:40:44.705990 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1860 00:40:44.706041 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1861 00:40:44.706092 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1862 00:40:44.706143 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1863 00:40:44.706234 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1864 00:40:44.706286 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1865 00:40:44.706337 0 11 4 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
1866 00:40:44.706387 0 11 8 | B1->B0 | 4646 3838 | 0 0 | (0 0) (0 0)
1867 00:40:44.706439 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1868 00:40:44.706507 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1869 00:40:44.706604 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1870 00:40:44.706673 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1871 00:40:44.706735 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1872 00:40:44.706788 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1873 00:40:44.706840 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1874 00:40:44.706907 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1875 00:40:44.706972 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 00:40:44.707023 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1877 00:40:44.707074 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1878 00:40:44.707125 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1879 00:40:44.707176 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1880 00:40:44.707277 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1881 00:40:44.707342 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1882 00:40:44.707394 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1883 00:40:44.707446 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1884 00:40:44.707497 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1885 00:40:44.707549 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1886 00:40:44.707599 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1887 00:40:44.707650 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1888 00:40:44.707701 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1889 00:40:44.707752 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1890 00:40:44.707803 Total UI for P1: 0, mck2ui 16
1891 00:40:44.707855 best dqsien dly found for B1: ( 0, 14, 2)
1892 00:40:44.707906 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1893 00:40:44.707958 Total UI for P1: 0, mck2ui 16
1894 00:40:44.708008 best dqsien dly found for B0: ( 0, 14, 4)
1895 00:40:44.708059 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1896 00:40:44.708111 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1897 00:40:44.708162
1898 00:40:44.708212 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1899 00:40:44.708264 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1900 00:40:44.708314 [Gating] SW calibration Done
1901 00:40:44.708366 ==
1902 00:40:44.708417 Dram Type= 6, Freq= 0, CH_1, rank 1
1903 00:40:44.708468 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1904 00:40:44.708519 ==
1905 00:40:44.708570 RX Vref Scan: 0
1906 00:40:44.708621
1907 00:40:44.708671 RX Vref 0 -> 0, step: 1
1908 00:40:44.708722
1909 00:40:44.708772 RX Delay -130 -> 252, step: 16
1910 00:40:44.708823 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1911 00:40:44.708874 iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224
1912 00:40:44.708925 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1913 00:40:44.708975 iDelay=222, Bit 3, Center 77 (-34 ~ 189) 224
1914 00:40:44.709026 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1915 00:40:44.709077 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1916 00:40:44.709127 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1917 00:40:44.709178 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1918 00:40:44.709229 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1919 00:40:44.968494 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1920 00:40:44.968629 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1921 00:40:44.968906 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1922 00:40:44.968971 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1923 00:40:44.969029 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1924 00:40:44.969086 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1925 00:40:44.969140 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1926 00:40:44.969193 ==
1927 00:40:44.969247 Dram Type= 6, Freq= 0, CH_1, rank 1
1928 00:40:44.969300 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1929 00:40:44.969353 ==
1930 00:40:44.969405 DQS Delay:
1931 00:40:44.969457 DQS0 = 0, DQS1 = 0
1932 00:40:44.969508 DQM Delay:
1933 00:40:44.969560 DQM0 = 85, DQM1 = 78
1934 00:40:44.969611 DQ Delay:
1935 00:40:44.969662 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1936 00:40:44.969714 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1937 00:40:44.969765 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1938 00:40:44.969837 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1939 00:40:44.969892
1940 00:40:44.969943
1941 00:40:44.969994 ==
1942 00:40:44.970044 Dram Type= 6, Freq= 0, CH_1, rank 1
1943 00:40:44.970095 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1944 00:40:44.970147 ==
1945 00:40:44.970239
1946 00:40:44.970290
1947 00:40:44.970341 TX Vref Scan disable
1948 00:40:44.970393 == TX Byte 0 ==
1949 00:40:44.970444 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1950 00:40:44.970495 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1951 00:40:44.970547 == TX Byte 1 ==
1952 00:40:44.970597 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1953 00:40:44.970649 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1954 00:40:44.970699 ==
1955 00:40:44.970750 Dram Type= 6, Freq= 0, CH_1, rank 1
1956 00:40:44.970801 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1957 00:40:44.970852 ==
1958 00:40:44.970902 TX Vref=22, minBit 9, minWin=26, winSum=444
1959 00:40:44.970954 TX Vref=24, minBit 9, minWin=27, winSum=447
1960 00:40:44.971004 TX Vref=26, minBit 8, minWin=27, winSum=449
1961 00:40:44.971055 TX Vref=28, minBit 13, minWin=27, winSum=450
1962 00:40:44.971106 TX Vref=30, minBit 13, minWin=27, winSum=449
1963 00:40:44.971157 TX Vref=32, minBit 8, minWin=27, winSum=451
1964 00:40:44.971208 [TxChooseVref] Worse bit 8, Min win 27, Win sum 451, Final Vref 32
1965 00:40:44.971259
1966 00:40:44.971310 Final TX Range 1 Vref 32
1967 00:40:44.971361
1968 00:40:44.971411 ==
1969 00:40:44.971461 Dram Type= 6, Freq= 0, CH_1, rank 1
1970 00:40:44.971512 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1971 00:40:44.971563 ==
1972 00:40:44.971612
1973 00:40:44.971662
1974 00:40:44.971712 TX Vref Scan disable
1975 00:40:44.971762 == TX Byte 0 ==
1976 00:40:44.971813 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1977 00:40:44.971863 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1978 00:40:44.971914 == TX Byte 1 ==
1979 00:40:44.971964 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1980 00:40:44.972015 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1981 00:40:44.972065
1982 00:40:44.972115 [DATLAT]
1983 00:40:44.972166 Freq=800, CH1 RK1
1984 00:40:44.972217
1985 00:40:44.972267 DATLAT Default: 0xa
1986 00:40:44.972317 0, 0xFFFF, sum = 0
1987 00:40:44.972368 1, 0xFFFF, sum = 0
1988 00:40:44.972420 2, 0xFFFF, sum = 0
1989 00:40:44.972471 3, 0xFFFF, sum = 0
1990 00:40:44.972522 4, 0xFFFF, sum = 0
1991 00:40:44.972573 5, 0xFFFF, sum = 0
1992 00:40:44.972625 6, 0xFFFF, sum = 0
1993 00:40:44.972675 7, 0xFFFF, sum = 0
1994 00:40:44.972727 8, 0xFFFF, sum = 0
1995 00:40:44.972778 9, 0x0, sum = 1
1996 00:40:44.972829 10, 0x0, sum = 2
1997 00:40:44.972880 11, 0x0, sum = 3
1998 00:40:44.972945 12, 0x0, sum = 4
1999 00:40:44.973002 best_step = 10
2000 00:40:44.973053
2001 00:40:44.973104 ==
2002 00:40:44.973158 Dram Type= 6, Freq= 0, CH_1, rank 1
2003 00:40:44.973210 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2004 00:40:44.973262 ==
2005 00:40:44.973312 RX Vref Scan: 0
2006 00:40:44.973363
2007 00:40:44.973413 RX Vref 0 -> 0, step: 1
2008 00:40:44.973464
2009 00:40:44.973514 RX Delay -95 -> 252, step: 8
2010 00:40:44.973565 iDelay=217, Bit 0, Center 88 (-23 ~ 200) 224
2011 00:40:44.973616 iDelay=217, Bit 1, Center 80 (-31 ~ 192) 224
2012 00:40:44.973667 iDelay=217, Bit 2, Center 76 (-31 ~ 184) 216
2013 00:40:44.973717 iDelay=217, Bit 3, Center 84 (-23 ~ 192) 216
2014 00:40:44.973768 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
2015 00:40:44.973818 iDelay=217, Bit 5, Center 96 (-15 ~ 208) 224
2016 00:40:44.973868 iDelay=217, Bit 6, Center 100 (-15 ~ 216) 232
2017 00:40:44.973919 iDelay=217, Bit 7, Center 84 (-31 ~ 200) 232
2018 00:40:44.973970 iDelay=217, Bit 8, Center 68 (-47 ~ 184) 232
2019 00:40:44.974020 iDelay=217, Bit 9, Center 72 (-39 ~ 184) 224
2020 00:40:44.974071 iDelay=217, Bit 10, Center 84 (-31 ~ 200) 232
2021 00:40:44.974122 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
2022 00:40:44.974201 iDelay=217, Bit 12, Center 88 (-23 ~ 200) 224
2023 00:40:44.974267 iDelay=217, Bit 13, Center 88 (-23 ~ 200) 224
2024 00:40:44.974318 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
2025 00:40:44.974368 iDelay=217, Bit 15, Center 88 (-31 ~ 208) 240
2026 00:40:44.974419 ==
2027 00:40:44.974469 Dram Type= 6, Freq= 0, CH_1, rank 1
2028 00:40:44.974520 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2029 00:40:44.974571 ==
2030 00:40:44.974621 DQS Delay:
2031 00:40:44.974671 DQS0 = 0, DQS1 = 0
2032 00:40:44.974722 DQM Delay:
2033 00:40:44.974773 DQM0 = 86, DQM1 = 80
2034 00:40:44.974824 DQ Delay:
2035 00:40:44.974874 DQ0 =88, DQ1 =80, DQ2 =76, DQ3 =84
2036 00:40:44.974925 DQ4 =84, DQ5 =96, DQ6 =100, DQ7 =84
2037 00:40:44.974975 DQ8 =68, DQ9 =72, DQ10 =84, DQ11 =68
2038 00:40:44.975026 DQ12 =88, DQ13 =88, DQ14 =84, DQ15 =88
2039 00:40:44.975076
2040 00:40:44.975126
2041 00:40:44.975177 [DQSOSCAuto] RK1, (LSB)MR18= 0x1f18, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 402 ps
2042 00:40:44.975230 CH1 RK1: MR19=606, MR18=1F18
2043 00:40:44.975281 CH1_RK1: MR19=0x606, MR18=0x1F18, DQSOSC=402, MR23=63, INC=91, DEC=60
2044 00:40:44.975332 [RxdqsGatingPostProcess] freq 800
2045 00:40:44.975383 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2046 00:40:44.975434 Pre-setting of DQS Precalculation
2047 00:40:44.975485 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2048 00:40:44.975536 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2049 00:40:44.975588 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2050 00:40:44.975639
2051 00:40:44.975690
2052 00:40:44.975740 [Calibration Summary] 1600 Mbps
2053 00:40:44.975791 CH 0, Rank 0
2054 00:40:44.975842 SW Impedance : PASS
2055 00:40:44.975892 DUTY Scan : NO K
2056 00:40:44.975944 ZQ Calibration : PASS
2057 00:40:44.975994 Jitter Meter : NO K
2058 00:40:44.976045 CBT Training : PASS
2059 00:40:44.976096 Write leveling : PASS
2060 00:40:44.976147 RX DQS gating : PASS
2061 00:40:44.976198 RX DQ/DQS(RDDQC) : PASS
2062 00:40:44.976248 TX DQ/DQS : PASS
2063 00:40:44.976500 RX DATLAT : PASS
2064 00:40:44.976560 RX DQ/DQS(Engine): PASS
2065 00:40:44.976613 TX OE : NO K
2066 00:40:44.976665 All Pass.
2067 00:40:44.976717
2068 00:40:44.976768 CH 0, Rank 1
2069 00:40:44.976820 SW Impedance : PASS
2070 00:40:44.976872 DUTY Scan : NO K
2071 00:40:44.976923 ZQ Calibration : PASS
2072 00:40:44.976975 Jitter Meter : NO K
2073 00:40:44.977026 CBT Training : PASS
2074 00:40:44.977078 Write leveling : PASS
2075 00:40:44.977129 RX DQS gating : PASS
2076 00:40:44.977180 RX DQ/DQS(RDDQC) : PASS
2077 00:40:44.977231 TX DQ/DQS : PASS
2078 00:40:44.977283 RX DATLAT : PASS
2079 00:40:44.977335 RX DQ/DQS(Engine): PASS
2080 00:40:44.977386 TX OE : NO K
2081 00:40:44.977459 All Pass.
2082 00:40:44.977523
2083 00:40:44.977575 CH 1, Rank 0
2084 00:40:44.977625 SW Impedance : PASS
2085 00:40:44.977676 DUTY Scan : NO K
2086 00:40:44.977728 ZQ Calibration : PASS
2087 00:40:44.977779 Jitter Meter : NO K
2088 00:40:44.977829 CBT Training : PASS
2089 00:40:44.977881 Write leveling : PASS
2090 00:40:44.977931 RX DQS gating : PASS
2091 00:40:44.977982 RX DQ/DQS(RDDQC) : PASS
2092 00:40:44.978033 TX DQ/DQS : PASS
2093 00:40:44.978085 RX DATLAT : PASS
2094 00:40:44.978137 RX DQ/DQS(Engine): PASS
2095 00:40:44.978243 TX OE : NO K
2096 00:40:44.978324 All Pass.
2097 00:40:44.978405
2098 00:40:44.978499 CH 1, Rank 1
2099 00:40:44.978565 SW Impedance : PASS
2100 00:40:44.978620 DUTY Scan : NO K
2101 00:40:44.978671 ZQ Calibration : PASS
2102 00:40:44.978723 Jitter Meter : NO K
2103 00:40:44.978774 CBT Training : PASS
2104 00:40:44.978825 Write leveling : PASS
2105 00:40:44.978877 RX DQS gating : PASS
2106 00:40:44.978928 RX DQ/DQS(RDDQC) : PASS
2107 00:40:44.978978 TX DQ/DQS : PASS
2108 00:40:44.979029 RX DATLAT : PASS
2109 00:40:44.979080 RX DQ/DQS(Engine): PASS
2110 00:40:44.979132 TX OE : NO K
2111 00:40:44.979183 All Pass.
2112 00:40:44.979234
2113 00:40:44.979285 DramC Write-DBI off
2114 00:40:44.979337 PER_BANK_REFRESH: Hybrid Mode
2115 00:40:44.979388 TX_TRACKING: ON
2116 00:40:44.979479 [GetDramInforAfterCalByMRR] Vendor 6.
2117 00:40:44.979531 [GetDramInforAfterCalByMRR] Revision 606.
2118 00:40:44.979582 [GetDramInforAfterCalByMRR] Revision 2 0.
2119 00:40:44.979633 MR0 0x3b3b
2120 00:40:44.979684 MR8 0x5151
2121 00:40:44.979745 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2122 00:40:44.979806
2123 00:40:44.979859 MR0 0x3b3b
2124 00:40:44.979910 MR8 0x5151
2125 00:40:44.979961 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2126 00:40:44.980013
2127 00:40:44.980065 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2128 00:40:44.980118 [FAST_K] Save calibration result to emmc
2129 00:40:44.980170 [FAST_K] Save calibration result to emmc
2130 00:40:44.980222 dram_init: config_dvfs: 1
2131 00:40:44.980274 dramc_set_vcore_voltage set vcore to 662500
2132 00:40:44.980325 Read voltage for 1200, 2
2133 00:40:44.980376 Vio18 = 0
2134 00:40:44.980427 Vcore = 662500
2135 00:40:44.980478 Vdram = 0
2136 00:40:44.980529 Vddq = 0
2137 00:40:44.980580 Vmddr = 0
2138 00:40:44.980631 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2139 00:40:44.980683 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2140 00:40:44.980735 MEM_TYPE=3, freq_sel=15
2141 00:40:44.980786 sv_algorithm_assistance_LP4_1600
2142 00:40:44.980838 ============ PULL DRAM RESETB DOWN ============
2143 00:40:44.980890 ========== PULL DRAM RESETB DOWN end =========
2144 00:40:44.980942 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2145 00:40:44.980993 ===================================
2146 00:40:44.981044 LPDDR4 DRAM CONFIGURATION
2147 00:40:44.981095 ===================================
2148 00:40:44.981147 EX_ROW_EN[0] = 0x0
2149 00:40:44.981198 EX_ROW_EN[1] = 0x0
2150 00:40:44.981249 LP4Y_EN = 0x0
2151 00:40:44.981300 WORK_FSP = 0x0
2152 00:40:44.981351 WL = 0x4
2153 00:40:44.981428 RL = 0x4
2154 00:40:44.981492 BL = 0x2
2155 00:40:44.981549 RPST = 0x0
2156 00:40:44.981626 RD_PRE = 0x0
2157 00:40:44.981681 WR_PRE = 0x1
2158 00:40:44.981733 WR_PST = 0x0
2159 00:40:44.981783 DBI_WR = 0x0
2160 00:40:44.981834 DBI_RD = 0x0
2161 00:40:44.981885 OTF = 0x1
2162 00:40:44.981936 ===================================
2163 00:40:44.981988 ===================================
2164 00:40:44.982039 ANA top config
2165 00:40:44.982090 ===================================
2166 00:40:44.982141 DLL_ASYNC_EN = 0
2167 00:40:44.982225 ALL_SLAVE_EN = 0
2168 00:40:44.982291 NEW_RANK_MODE = 1
2169 00:40:44.982344 DLL_IDLE_MODE = 1
2170 00:40:44.982395 LP45_APHY_COMB_EN = 1
2171 00:40:44.982445 TX_ODT_DIS = 1
2172 00:40:44.982497 NEW_8X_MODE = 1
2173 00:40:44.982549 ===================================
2174 00:40:44.982600 ===================================
2175 00:40:44.982651 data_rate = 2400
2176 00:40:44.982702 CKR = 1
2177 00:40:44.982753 DQ_P2S_RATIO = 8
2178 00:40:44.982809 ===================================
2179 00:40:44.982874 CA_P2S_RATIO = 8
2180 00:40:44.982927 DQ_CA_OPEN = 0
2181 00:40:44.982978 DQ_SEMI_OPEN = 0
2182 00:40:44.983029 CA_SEMI_OPEN = 0
2183 00:40:44.983080 CA_FULL_RATE = 0
2184 00:40:44.983131 DQ_CKDIV4_EN = 0
2185 00:40:44.983182 CA_CKDIV4_EN = 0
2186 00:40:44.983233 CA_PREDIV_EN = 0
2187 00:40:44.983284 PH8_DLY = 17
2188 00:40:44.983334 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2189 00:40:44.983386 DQ_AAMCK_DIV = 4
2190 00:40:44.983437 CA_AAMCK_DIV = 4
2191 00:40:44.983488 CA_ADMCK_DIV = 4
2192 00:40:44.983539 DQ_TRACK_CA_EN = 0
2193 00:40:44.983590 CA_PICK = 1200
2194 00:40:44.983642 CA_MCKIO = 1200
2195 00:40:44.983694 MCKIO_SEMI = 0
2196 00:40:44.983745 PLL_FREQ = 2366
2197 00:40:44.983797 DQ_UI_PI_RATIO = 32
2198 00:40:44.983849 CA_UI_PI_RATIO = 0
2199 00:40:44.983902 ===================================
2200 00:40:44.983953 ===================================
2201 00:40:44.984005 memory_type:LPDDR4
2202 00:40:44.984057 GP_NUM : 10
2203 00:40:44.984109 SRAM_EN : 1
2204 00:40:44.984160 MD32_EN : 0
2205 00:40:44.984212 ===================================
2206 00:40:44.984264 [ANA_INIT] >>>>>>>>>>>>>>
2207 00:40:44.984315 <<<<<< [CONFIGURE PHASE]: ANA_TX
2208 00:40:44.984367 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2209 00:40:44.984417 ===================================
2210 00:40:44.984469 data_rate = 2400,PCW = 0X5b00
2211 00:40:44.984520 ===================================
2212 00:40:44.984800 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2213 00:40:44.984862 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2214 00:40:44.984916 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2215 00:40:44.984969 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2216 00:40:44.985021 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2217 00:40:44.985073 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2218 00:40:44.985125 [ANA_INIT] flow start
2219 00:40:44.985176 [ANA_INIT] PLL >>>>>>>>
2220 00:40:44.985228 [ANA_INIT] PLL <<<<<<<<
2221 00:40:44.985279 [ANA_INIT] MIDPI >>>>>>>>
2222 00:40:44.985330 [ANA_INIT] MIDPI <<<<<<<<
2223 00:40:44.985382 [ANA_INIT] DLL >>>>>>>>
2224 00:40:44.985433 [ANA_INIT] DLL <<<<<<<<
2225 00:40:44.985484 [ANA_INIT] flow end
2226 00:40:44.985535 ============ LP4 DIFF to SE enter ============
2227 00:40:44.985586 ============ LP4 DIFF to SE exit ============
2228 00:40:44.985638 [ANA_INIT] <<<<<<<<<<<<<
2229 00:40:44.985689 [Flow] Enable top DCM control >>>>>
2230 00:40:44.985740 [Flow] Enable top DCM control <<<<<
2231 00:40:44.985791 Enable DLL master slave shuffle
2232 00:40:44.985841 ==============================================================
2233 00:40:44.985893 Gating Mode config
2234 00:40:44.985944 ==============================================================
2235 00:40:44.985995 Config description:
2236 00:40:44.986046 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2237 00:40:44.986099 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2238 00:40:44.986151 SELPH_MODE 0: By rank 1: By Phase
2239 00:40:44.986259 ==============================================================
2240 00:40:44.986323 GAT_TRACK_EN = 1
2241 00:40:44.986375 RX_GATING_MODE = 2
2242 00:40:44.986427 RX_GATING_TRACK_MODE = 2
2243 00:40:44.986478 SELPH_MODE = 1
2244 00:40:44.986529 PICG_EARLY_EN = 1
2245 00:40:44.986580 VALID_LAT_VALUE = 1
2246 00:40:44.986631 ==============================================================
2247 00:40:44.986683 Enter into Gating configuration >>>>
2248 00:40:44.986735 Exit from Gating configuration <<<<
2249 00:40:44.986786 Enter into DVFS_PRE_config >>>>>
2250 00:40:44.986838 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2251 00:40:44.986892 Exit from DVFS_PRE_config <<<<<
2252 00:40:44.986943 Enter into PICG configuration >>>>
2253 00:40:44.986995 Exit from PICG configuration <<<<
2254 00:40:44.987046 [RX_INPUT] configuration >>>>>
2255 00:40:44.987097 [RX_INPUT] configuration <<<<<
2256 00:40:44.987148 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2257 00:40:44.987199 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2258 00:40:44.987251 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2259 00:40:44.987302 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2260 00:40:44.987354 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2261 00:40:44.987405 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2262 00:40:44.987482 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2263 00:40:44.987537 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2264 00:40:44.987692 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2265 00:40:44.987763 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2266 00:40:44.987815 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2267 00:40:44.987867 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2268 00:40:44.987919 ===================================
2269 00:40:44.987971 LPDDR4 DRAM CONFIGURATION
2270 00:40:44.988022 ===================================
2271 00:40:44.988074 EX_ROW_EN[0] = 0x0
2272 00:40:44.988125 EX_ROW_EN[1] = 0x0
2273 00:40:44.988176 LP4Y_EN = 0x0
2274 00:40:44.988227 WORK_FSP = 0x0
2275 00:40:44.988278 WL = 0x4
2276 00:40:44.988328 RL = 0x4
2277 00:40:44.988379 BL = 0x2
2278 00:40:44.988430 RPST = 0x0
2279 00:40:44.988481 RD_PRE = 0x0
2280 00:40:44.988532 WR_PRE = 0x1
2281 00:40:44.988583 WR_PST = 0x0
2282 00:40:44.988634 DBI_WR = 0x0
2283 00:40:44.988685 DBI_RD = 0x0
2284 00:40:44.988736 OTF = 0x1
2285 00:40:44.988787 ===================================
2286 00:40:44.988838 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2287 00:40:44.988889 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2288 00:40:44.988941 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2289 00:40:44.988992 ===================================
2290 00:40:44.989043 LPDDR4 DRAM CONFIGURATION
2291 00:40:44.989094 ===================================
2292 00:40:44.989145 EX_ROW_EN[0] = 0x10
2293 00:40:44.989196 EX_ROW_EN[1] = 0x0
2294 00:40:44.989246 LP4Y_EN = 0x0
2295 00:40:44.989297 WORK_FSP = 0x0
2296 00:40:44.989347 WL = 0x4
2297 00:40:44.989398 RL = 0x4
2298 00:40:44.989468 BL = 0x2
2299 00:40:44.989521 RPST = 0x0
2300 00:40:44.989572 RD_PRE = 0x0
2301 00:40:44.989623 WR_PRE = 0x1
2302 00:40:44.989673 WR_PST = 0x0
2303 00:40:44.989724 DBI_WR = 0x0
2304 00:40:44.989774 DBI_RD = 0x0
2305 00:40:44.989824 OTF = 0x1
2306 00:40:44.989875 ===================================
2307 00:40:44.989926 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2308 00:40:44.989978 ==
2309 00:40:44.990029 Dram Type= 6, Freq= 0, CH_0, rank 0
2310 00:40:44.990080 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2311 00:40:44.990131 ==
2312 00:40:44.990210 [Duty_Offset_Calibration]
2313 00:40:44.990276 B0:1 B1:-1 CA:0
2314 00:40:44.990327
2315 00:40:44.990377 [DutyScan_Calibration_Flow] k_type=0
2316 00:40:44.990428
2317 00:40:44.990479 ==CLK 0==
2318 00:40:44.990530 Final CLK duty delay cell = 0
2319 00:40:44.990581 [0] MAX Duty = 5094%(X100), DQS PI = 16
2320 00:40:44.990633 [0] MIN Duty = 4875%(X100), DQS PI = 8
2321 00:40:44.990683 [0] AVG Duty = 4984%(X100)
2322 00:40:44.990733
2323 00:40:44.990784 CH0 CLK Duty spec in!! Max-Min= 219%
2324 00:40:44.990835 [DutyScan_Calibration_Flow] ====Done====
2325 00:40:44.990885
2326 00:40:44.991137 [DutyScan_Calibration_Flow] k_type=1
2327 00:40:44.991194
2328 00:40:44.991246 ==DQS 0 ==
2329 00:40:44.991297 Final DQS duty delay cell = -4
2330 00:40:44.991349 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2331 00:40:44.991400 [-4] MIN Duty = 4875%(X100), DQS PI = 54
2332 00:40:44.991451 [-4] AVG Duty = 4968%(X100)
2333 00:40:44.991501
2334 00:40:44.991552 ==DQS 1 ==
2335 00:40:44.991603 Final DQS duty delay cell = 0
2336 00:40:44.991653 [0] MAX Duty = 5125%(X100), DQS PI = 54
2337 00:40:44.991706 [0] MIN Duty = 5000%(X100), DQS PI = 22
2338 00:40:44.991756 [0] AVG Duty = 5062%(X100)
2339 00:40:44.991807
2340 00:40:44.991857 CH0 DQS 0 Duty spec in!! Max-Min= 187%
2341 00:40:44.991908
2342 00:40:44.991959 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2343 00:40:44.992010 [DutyScan_Calibration_Flow] ====Done====
2344 00:40:44.992060
2345 00:40:44.992110 [DutyScan_Calibration_Flow] k_type=3
2346 00:40:44.992161
2347 00:40:44.992212 ==DQM 0 ==
2348 00:40:44.992263 Final DQM duty delay cell = 0
2349 00:40:44.992313 [0] MAX Duty = 5062%(X100), DQS PI = 16
2350 00:40:44.992364 [0] MIN Duty = 4875%(X100), DQS PI = 8
2351 00:40:44.992414 [0] AVG Duty = 4968%(X100)
2352 00:40:44.992464
2353 00:40:44.992515 ==DQM 1 ==
2354 00:40:44.992566 Final DQM duty delay cell = 4
2355 00:40:44.992616 [4] MAX Duty = 5187%(X100), DQS PI = 56
2356 00:40:44.992667 [4] MIN Duty = 4969%(X100), DQS PI = 26
2357 00:40:44.992718 [4] AVG Duty = 5078%(X100)
2358 00:40:44.992768
2359 00:40:44.992818 CH0 DQM 0 Duty spec in!! Max-Min= 187%
2360 00:40:44.992868
2361 00:40:44.992919 CH0 DQM 1 Duty spec in!! Max-Min= 218%
2362 00:40:44.992969 [DutyScan_Calibration_Flow] ====Done====
2363 00:40:44.993020
2364 00:40:44.993070 [DutyScan_Calibration_Flow] k_type=2
2365 00:40:44.993120
2366 00:40:44.993170 ==DQ 0 ==
2367 00:40:44.993221 Final DQ duty delay cell = -4
2368 00:40:44.993292 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2369 00:40:44.993347 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2370 00:40:44.993399 [-4] AVG Duty = 4969%(X100)
2371 00:40:44.993450
2372 00:40:44.993500 ==DQ 1 ==
2373 00:40:44.993551 Final DQ duty delay cell = 0
2374 00:40:44.993603 [0] MAX Duty = 5125%(X100), DQS PI = 52
2375 00:40:44.993653 [0] MIN Duty = 4969%(X100), DQS PI = 38
2376 00:40:44.993704 [0] AVG Duty = 5047%(X100)
2377 00:40:44.993754
2378 00:40:44.993805 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2379 00:40:44.993857
2380 00:40:44.993907 CH0 DQ 1 Duty spec in!! Max-Min= 156%
2381 00:40:44.993958 [DutyScan_Calibration_Flow] ====Done====
2382 00:40:44.994009 ==
2383 00:40:44.994060 Dram Type= 6, Freq= 0, CH_1, rank 0
2384 00:40:44.994110 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2385 00:40:44.994170 ==
2386 00:40:44.994262 [Duty_Offset_Calibration]
2387 00:40:44.994313 B0:-1 B1:1 CA:1
2388 00:40:44.994364
2389 00:40:44.994414 [DutyScan_Calibration_Flow] k_type=0
2390 00:40:44.994465
2391 00:40:44.994516 ==CLK 0==
2392 00:40:44.994566 Final CLK duty delay cell = 0
2393 00:40:44.994617 [0] MAX Duty = 5156%(X100), DQS PI = 22
2394 00:40:44.994668 [0] MIN Duty = 4969%(X100), DQS PI = 60
2395 00:40:44.994719 [0] AVG Duty = 5062%(X100)
2396 00:40:44.994769
2397 00:40:44.994819 CH1 CLK Duty spec in!! Max-Min= 187%
2398 00:40:44.994870 [DutyScan_Calibration_Flow] ====Done====
2399 00:40:44.994921
2400 00:40:44.994971 [DutyScan_Calibration_Flow] k_type=1
2401 00:40:44.995022
2402 00:40:44.995072 ==DQS 0 ==
2403 00:40:44.995123 Final DQS duty delay cell = 0
2404 00:40:44.995174 [0] MAX Duty = 5125%(X100), DQS PI = 48
2405 00:40:44.995225 [0] MIN Duty = 4875%(X100), DQS PI = 8
2406 00:40:44.995276 [0] AVG Duty = 5000%(X100)
2407 00:40:44.995327
2408 00:40:44.995377 ==DQS 1 ==
2409 00:40:44.995427 Final DQS duty delay cell = 0
2410 00:40:44.995478 [0] MAX Duty = 5062%(X100), DQS PI = 12
2411 00:40:44.995529 [0] MIN Duty = 4969%(X100), DQS PI = 56
2412 00:40:44.995580 [0] AVG Duty = 5015%(X100)
2413 00:40:44.995630
2414 00:40:44.995681 CH1 DQS 0 Duty spec in!! Max-Min= 250%
2415 00:40:44.995731
2416 00:40:44.995781 CH1 DQS 1 Duty spec in!! Max-Min= 93%
2417 00:40:44.995832 [DutyScan_Calibration_Flow] ====Done====
2418 00:40:44.995883
2419 00:40:44.995934 [DutyScan_Calibration_Flow] k_type=3
2420 00:40:44.995984
2421 00:40:44.996035 ==DQM 0 ==
2422 00:40:44.996086 Final DQM duty delay cell = -4
2423 00:40:44.996138 [-4] MAX Duty = 5031%(X100), DQS PI = 32
2424 00:40:44.996188 [-4] MIN Duty = 4844%(X100), DQS PI = 8
2425 00:40:44.996243 [-4] AVG Duty = 4937%(X100)
2426 00:40:44.996309
2427 00:40:44.996362 ==DQM 1 ==
2428 00:40:44.996413 Final DQM duty delay cell = 0
2429 00:40:44.996464 [0] MAX Duty = 5187%(X100), DQS PI = 6
2430 00:40:44.996515 [0] MIN Duty = 4969%(X100), DQS PI = 28
2431 00:40:44.996566 [0] AVG Duty = 5078%(X100)
2432 00:40:44.996616
2433 00:40:44.996666 CH1 DQM 0 Duty spec in!! Max-Min= 187%
2434 00:40:44.996717
2435 00:40:44.996768 CH1 DQM 1 Duty spec in!! Max-Min= 218%
2436 00:40:44.996818 [DutyScan_Calibration_Flow] ====Done====
2437 00:40:44.996868
2438 00:40:44.996919 [DutyScan_Calibration_Flow] k_type=2
2439 00:40:44.996970
2440 00:40:44.997019 ==DQ 0 ==
2441 00:40:44.997070 Final DQ duty delay cell = 0
2442 00:40:44.997121 [0] MAX Duty = 5156%(X100), DQS PI = 28
2443 00:40:44.997171 [0] MIN Duty = 4907%(X100), DQS PI = 6
2444 00:40:44.997221 [0] AVG Duty = 5031%(X100)
2445 00:40:44.997271
2446 00:40:44.997321 ==DQ 1 ==
2447 00:40:44.997372 Final DQ duty delay cell = 0
2448 00:40:44.997423 [0] MAX Duty = 5124%(X100), DQS PI = 10
2449 00:40:44.997473 [0] MIN Duty = 4969%(X100), DQS PI = 34
2450 00:40:44.997523 [0] AVG Duty = 5046%(X100)
2451 00:40:44.997573
2452 00:40:44.997624 CH1 DQ 0 Duty spec in!! Max-Min= 249%
2453 00:40:44.997674
2454 00:40:44.997724 CH1 DQ 1 Duty spec in!! Max-Min= 155%
2455 00:40:44.997778 [DutyScan_Calibration_Flow] ====Done====
2456 00:40:44.997842 nWR fixed to 30
2457 00:40:44.997894 [ModeRegInit_LP4] CH0 RK0
2458 00:40:44.997944 [ModeRegInit_LP4] CH0 RK1
2459 00:40:44.997994 [ModeRegInit_LP4] CH1 RK0
2460 00:40:44.998045 [ModeRegInit_LP4] CH1 RK1
2461 00:40:44.998095 match AC timing 7
2462 00:40:44.998145 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2463 00:40:44.998231 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2464 00:40:44.998283 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2465 00:40:44.998335 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2466 00:40:44.998386 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2467 00:40:44.998437 ==
2468 00:40:44.998488 Dram Type= 6, Freq= 0, CH_0, rank 0
2469 00:40:44.998539 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2470 00:40:44.998590 ==
2471 00:40:44.998640 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2472 00:40:44.998691 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2473 00:40:44.998742 [CA 0] Center 39 (9~70) winsize 62
2474 00:40:44.998793 [CA 1] Center 39 (9~69) winsize 61
2475 00:40:44.998843 [CA 2] Center 35 (5~66) winsize 62
2476 00:40:44.998894 [CA 3] Center 35 (5~66) winsize 62
2477 00:40:44.998944 [CA 4] Center 33 (4~63) winsize 60
2478 00:40:44.999196 [CA 5] Center 33 (3~63) winsize 61
2479 00:40:44.999253
2480 00:40:44.999305 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2481 00:40:44.999357
2482 00:40:44.999407 [CATrainingPosCal] consider 1 rank data
2483 00:40:44.999483 u2DelayCellTimex100 = 270/100 ps
2484 00:40:44.999537 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2485 00:40:44.999589 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2486 00:40:44.999641 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2487 00:40:44.999692 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2488 00:40:44.999744 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
2489 00:40:44.999801 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2490 00:40:44.999861
2491 00:40:44.999912 CA PerBit enable=1, Macro0, CA PI delay=33
2492 00:40:44.999963
2493 00:40:45.000014 [CBTSetCACLKResult] CA Dly = 33
2494 00:40:45.000065 CS Dly: 8 (0~39)
2495 00:40:45.000115 ==
2496 00:40:45.000166 Dram Type= 6, Freq= 0, CH_0, rank 1
2497 00:40:45.000217 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2498 00:40:45.000269 ==
2499 00:40:45.000320 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2500 00:40:45.000371 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2501 00:40:45.000423 [CA 0] Center 39 (9~70) winsize 62
2502 00:40:45.000475 [CA 1] Center 39 (9~70) winsize 62
2503 00:40:45.000526 [CA 2] Center 35 (5~66) winsize 62
2504 00:40:45.000577 [CA 3] Center 34 (4~65) winsize 62
2505 00:40:45.000628 [CA 4] Center 33 (3~64) winsize 62
2506 00:40:45.000678 [CA 5] Center 33 (3~63) winsize 61
2507 00:40:45.000729
2508 00:40:45.000779 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2509 00:40:45.000830
2510 00:40:45.000880 [CATrainingPosCal] consider 2 rank data
2511 00:40:45.000931 u2DelayCellTimex100 = 270/100 ps
2512 00:40:45.000981 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2513 00:40:45.001032 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2514 00:40:45.001082 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2515 00:40:45.001133 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
2516 00:40:45.001184 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
2517 00:40:45.001234 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2518 00:40:45.001284
2519 00:40:45.001334 CA PerBit enable=1, Macro0, CA PI delay=33
2520 00:40:45.001385
2521 00:40:45.001435 [CBTSetCACLKResult] CA Dly = 33
2522 00:40:45.001485 CS Dly: 8 (0~40)
2523 00:40:45.001536
2524 00:40:45.001586 ----->DramcWriteLeveling(PI) begin...
2525 00:40:45.001639 ==
2526 00:40:45.001689 Dram Type= 6, Freq= 0, CH_0, rank 0
2527 00:40:45.001740 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2528 00:40:45.001794 ==
2529 00:40:45.001875 Write leveling (Byte 0): 32 => 32
2530 00:40:45.001954 Write leveling (Byte 1): 27 => 27
2531 00:40:45.002007 DramcWriteLeveling(PI) end<-----
2532 00:40:45.002058
2533 00:40:45.002110 ==
2534 00:40:45.002170 Dram Type= 6, Freq= 0, CH_0, rank 0
2535 00:40:45.002256 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2536 00:40:45.002308 ==
2537 00:40:45.002359 [Gating] SW mode calibration
2538 00:40:45.002410 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2539 00:40:45.002461 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2540 00:40:45.002512 0 15 0 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (1 1)
2541 00:40:45.002563 0 15 4 | B1->B0 | 2929 3434 | 0 1 | (0 0) (1 1)
2542 00:40:45.002639 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2543 00:40:45.002693 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2544 00:40:45.002744 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2545 00:40:45.002795 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2546 00:40:45.002846 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2547 00:40:45.002897 0 15 28 | B1->B0 | 3434 2d2d | 1 1 | (1 1) (1 0)
2548 00:40:45.002949 1 0 0 | B1->B0 | 3232 2323 | 0 0 | (0 1) (0 0)
2549 00:40:45.002999 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2550 00:40:45.003051 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2551 00:40:45.003102 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2552 00:40:45.003153 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2553 00:40:45.003203 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2554 00:40:45.003254 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2555 00:40:45.003306 1 0 28 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
2556 00:40:45.003357 1 1 0 | B1->B0 | 2626 4444 | 0 0 | (1 1) (0 0)
2557 00:40:45.003407 1 1 4 | B1->B0 | 3f3f 4646 | 1 0 | (0 0) (0 0)
2558 00:40:45.003458 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2559 00:40:45.003509 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2560 00:40:45.003560 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2561 00:40:45.003611 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2562 00:40:45.003662 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2563 00:40:45.003713 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2564 00:40:45.003763 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2565 00:40:45.003814 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2566 00:40:45.003865 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2567 00:40:45.003915 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2568 00:40:45.003966 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2569 00:40:45.004016 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2570 00:40:45.004067 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2571 00:40:45.004117 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2572 00:40:45.004168 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2573 00:40:45.004219 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2574 00:40:45.004269 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2575 00:40:45.004320 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2576 00:40:45.004371 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2577 00:40:45.004422 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2578 00:40:45.004473 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2579 00:40:45.004523 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2580 00:40:45.004574 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2581 00:40:45.004625 Total UI for P1: 0, mck2ui 16
2582 00:40:45.004677 best dqsien dly found for B0: ( 1, 3, 28)
2583 00:40:45.004927 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2584 00:40:45.004985 Total UI for P1: 0, mck2ui 16
2585 00:40:45.005038 best dqsien dly found for B1: ( 1, 4, 0)
2586 00:40:45.005090 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2587 00:40:45.005141 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2588 00:40:45.005193
2589 00:40:45.005243 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2590 00:40:45.005294 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2591 00:40:45.005345 [Gating] SW calibration Done
2592 00:40:45.005396 ==
2593 00:40:45.005447 Dram Type= 6, Freq= 0, CH_0, rank 0
2594 00:40:45.005498 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2595 00:40:45.005550 ==
2596 00:40:45.005601 RX Vref Scan: 0
2597 00:40:45.005652
2598 00:40:45.005703 RX Vref 0 -> 0, step: 1
2599 00:40:45.005754
2600 00:40:45.005804 RX Delay -40 -> 252, step: 8
2601 00:40:45.005855 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2602 00:40:45.005906 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2603 00:40:45.005966 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2604 00:40:45.006053 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2605 00:40:45.006133 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2606 00:40:45.006240 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2607 00:40:45.006293 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2608 00:40:45.006344 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2609 00:40:45.006395 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2610 00:40:45.006446 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2611 00:40:45.006496 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2612 00:40:45.006547 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2613 00:40:45.006599 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2614 00:40:45.006650 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2615 00:40:45.006701 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2616 00:40:45.006751 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2617 00:40:45.006802 ==
2618 00:40:45.006853 Dram Type= 6, Freq= 0, CH_0, rank 0
2619 00:40:45.006904 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2620 00:40:45.006956 ==
2621 00:40:45.007006 DQS Delay:
2622 00:40:45.007057 DQS0 = 0, DQS1 = 0
2623 00:40:45.007108 DQM Delay:
2624 00:40:45.007159 DQM0 = 119, DQM1 = 107
2625 00:40:45.007209 DQ Delay:
2626 00:40:45.007260 DQ0 =119, DQ1 =119, DQ2 =115, DQ3 =115
2627 00:40:45.007311 DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =127
2628 00:40:45.007362 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =103
2629 00:40:45.007413 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2630 00:40:45.007464
2631 00:40:45.007514
2632 00:40:45.007565 ==
2633 00:40:45.007615 Dram Type= 6, Freq= 0, CH_0, rank 0
2634 00:40:45.007666 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2635 00:40:45.007717 ==
2636 00:40:45.007767
2637 00:40:45.007817
2638 00:40:45.007868 TX Vref Scan disable
2639 00:40:45.007919 == TX Byte 0 ==
2640 00:40:45.007970 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2641 00:40:45.008021 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2642 00:40:45.008072 == TX Byte 1 ==
2643 00:40:45.008123 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2644 00:40:45.008174 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2645 00:40:45.008225 ==
2646 00:40:45.008276 Dram Type= 6, Freq= 0, CH_0, rank 0
2647 00:40:45.008326 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2648 00:40:45.008377 ==
2649 00:40:45.008428 TX Vref=22, minBit 4, minWin=25, winSum=422
2650 00:40:45.008479 TX Vref=24, minBit 0, minWin=26, winSum=422
2651 00:40:45.008530 TX Vref=26, minBit 1, minWin=26, winSum=432
2652 00:40:45.008580 TX Vref=28, minBit 1, minWin=27, winSum=439
2653 00:40:45.008632 TX Vref=30, minBit 5, minWin=26, winSum=435
2654 00:40:45.008683 TX Vref=32, minBit 5, minWin=26, winSum=433
2655 00:40:45.008733 [TxChooseVref] Worse bit 1, Min win 27, Win sum 439, Final Vref 28
2656 00:40:45.008785
2657 00:40:45.008836 Final TX Range 1 Vref 28
2658 00:40:45.008886
2659 00:40:45.008936 ==
2660 00:40:45.008987 Dram Type= 6, Freq= 0, CH_0, rank 0
2661 00:40:45.009038 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2662 00:40:45.009089 ==
2663 00:40:45.009139
2664 00:40:45.009203
2665 00:40:45.009258 TX Vref Scan disable
2666 00:40:45.009309 == TX Byte 0 ==
2667 00:40:45.009360 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2668 00:40:45.009412 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2669 00:40:45.009462 == TX Byte 1 ==
2670 00:40:45.009514 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
2671 00:40:45.009564 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
2672 00:40:45.009615
2673 00:40:45.009666 [DATLAT]
2674 00:40:45.009716 Freq=1200, CH0 RK0
2675 00:40:45.009767
2676 00:40:45.009817 DATLAT Default: 0xd
2677 00:40:45.009868 0, 0xFFFF, sum = 0
2678 00:40:45.009920 1, 0xFFFF, sum = 0
2679 00:40:45.009971 2, 0xFFFF, sum = 0
2680 00:40:45.010022 3, 0xFFFF, sum = 0
2681 00:40:45.010074 4, 0xFFFF, sum = 0
2682 00:40:45.010125 5, 0xFFFF, sum = 0
2683 00:40:45.010216 6, 0xFFFF, sum = 0
2684 00:40:45.010268 7, 0xFFFF, sum = 0
2685 00:40:45.010320 8, 0xFFFF, sum = 0
2686 00:40:45.010372 9, 0xFFFF, sum = 0
2687 00:40:45.010424 10, 0xFFFF, sum = 0
2688 00:40:45.010475 11, 0xFFFF, sum = 0
2689 00:40:45.010527 12, 0x0, sum = 1
2690 00:40:45.010578 13, 0x0, sum = 2
2691 00:40:45.010629 14, 0x0, sum = 3
2692 00:40:45.010680 15, 0x0, sum = 4
2693 00:40:45.010732 best_step = 13
2694 00:40:45.010782
2695 00:40:45.010832 ==
2696 00:40:45.010882 Dram Type= 6, Freq= 0, CH_0, rank 0
2697 00:40:45.010934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2698 00:40:45.010986 ==
2699 00:40:45.011036 RX Vref Scan: 1
2700 00:40:45.011086
2701 00:40:45.011137 Set Vref Range= 32 -> 127
2702 00:40:45.011187
2703 00:40:45.011238 RX Vref 32 -> 127, step: 1
2704 00:40:45.011288
2705 00:40:45.011338 RX Delay -21 -> 252, step: 4
2706 00:40:45.011388
2707 00:40:45.011439 Set Vref, RX VrefLevel [Byte0]: 32
2708 00:40:45.011490 [Byte1]: 32
2709 00:40:45.011541
2710 00:40:45.011591 Set Vref, RX VrefLevel [Byte0]: 33
2711 00:40:45.011642 [Byte1]: 33
2712 00:40:45.011692
2713 00:40:45.011743 Set Vref, RX VrefLevel [Byte0]: 34
2714 00:40:45.011793 [Byte1]: 34
2715 00:40:45.011844
2716 00:40:45.011894 Set Vref, RX VrefLevel [Byte0]: 35
2717 00:40:45.011945 [Byte1]: 35
2718 00:40:45.011995
2719 00:40:45.012045 Set Vref, RX VrefLevel [Byte0]: 36
2720 00:40:45.012096 [Byte1]: 36
2721 00:40:45.012146
2722 00:40:45.012196 Set Vref, RX VrefLevel [Byte0]: 37
2723 00:40:45.012246 [Byte1]: 37
2724 00:40:45.012297
2725 00:40:45.012363 Set Vref, RX VrefLevel [Byte0]: 38
2726 00:40:45.012418 [Byte1]: 38
2727 00:40:45.012469
2728 00:40:45.012520 Set Vref, RX VrefLevel [Byte0]: 39
2729 00:40:45.012570 [Byte1]: 39
2730 00:40:45.012621
2731 00:40:45.012671 Set Vref, RX VrefLevel [Byte0]: 40
2732 00:40:45.012722 [Byte1]: 40
2733 00:40:45.012772
2734 00:40:45.012822 Set Vref, RX VrefLevel [Byte0]: 41
2735 00:40:45.012873 [Byte1]: 41
2736 00:40:45.012923
2737 00:40:45.013171 Set Vref, RX VrefLevel [Byte0]: 42
2738 00:40:45.013229 [Byte1]: 42
2739 00:40:45.013282
2740 00:40:45.013333 Set Vref, RX VrefLevel [Byte0]: 43
2741 00:40:45.013385 [Byte1]: 43
2742 00:40:45.013437
2743 00:40:45.013488 Set Vref, RX VrefLevel [Byte0]: 44
2744 00:40:45.013538 [Byte1]: 44
2745 00:40:45.013589
2746 00:40:45.013640 Set Vref, RX VrefLevel [Byte0]: 45
2747 00:40:45.013690 [Byte1]: 45
2748 00:40:45.013760
2749 00:40:45.013844 Set Vref, RX VrefLevel [Byte0]: 46
2750 00:40:45.013908 [Byte1]: 46
2751 00:40:45.013958
2752 00:40:45.014008 Set Vref, RX VrefLevel [Byte0]: 47
2753 00:40:45.014059 [Byte1]: 47
2754 00:40:45.014109
2755 00:40:45.014168 Set Vref, RX VrefLevel [Byte0]: 48
2756 00:40:45.014256 [Byte1]: 48
2757 00:40:45.014306
2758 00:40:45.014357 Set Vref, RX VrefLevel [Byte0]: 49
2759 00:40:45.014408 [Byte1]: 49
2760 00:40:45.014458
2761 00:40:45.014509 Set Vref, RX VrefLevel [Byte0]: 50
2762 00:40:45.014560 [Byte1]: 50
2763 00:40:45.014611
2764 00:40:45.014661 Set Vref, RX VrefLevel [Byte0]: 51
2765 00:40:45.014711 [Byte1]: 51
2766 00:40:45.014762
2767 00:40:45.014812 Set Vref, RX VrefLevel [Byte0]: 52
2768 00:40:45.014863 [Byte1]: 52
2769 00:40:45.014914
2770 00:40:45.014964 Set Vref, RX VrefLevel [Byte0]: 53
2771 00:40:45.015015 [Byte1]: 53
2772 00:40:45.015065
2773 00:40:45.015116 Set Vref, RX VrefLevel [Byte0]: 54
2774 00:40:45.015166 [Byte1]: 54
2775 00:40:45.015217
2776 00:40:45.015267 Set Vref, RX VrefLevel [Byte0]: 55
2777 00:40:45.015318 [Byte1]: 55
2778 00:40:45.015368
2779 00:40:45.015418 Set Vref, RX VrefLevel [Byte0]: 56
2780 00:40:45.015469 [Byte1]: 56
2781 00:40:45.015520
2782 00:40:45.015570 Set Vref, RX VrefLevel [Byte0]: 57
2783 00:40:45.015622 [Byte1]: 57
2784 00:40:45.015672
2785 00:40:45.015723 Set Vref, RX VrefLevel [Byte0]: 58
2786 00:40:45.015773 [Byte1]: 58
2787 00:40:45.015824
2788 00:40:45.015874 Set Vref, RX VrefLevel [Byte0]: 59
2789 00:40:45.015925 [Byte1]: 59
2790 00:40:45.015975
2791 00:40:45.016026 Set Vref, RX VrefLevel [Byte0]: 60
2792 00:40:45.016098 [Byte1]: 60
2793 00:40:45.016151
2794 00:40:45.016202 Set Vref, RX VrefLevel [Byte0]: 61
2795 00:40:45.016252 [Byte1]: 61
2796 00:40:45.016303
2797 00:40:45.016354 Set Vref, RX VrefLevel [Byte0]: 62
2798 00:40:45.016405 [Byte1]: 62
2799 00:40:45.016455
2800 00:40:45.016506 Set Vref, RX VrefLevel [Byte0]: 63
2801 00:40:45.016556 [Byte1]: 63
2802 00:40:45.016607
2803 00:40:45.016658 Set Vref, RX VrefLevel [Byte0]: 64
2804 00:40:45.016708 [Byte1]: 64
2805 00:40:45.016759
2806 00:40:45.016809 Set Vref, RX VrefLevel [Byte0]: 65
2807 00:40:45.016860 [Byte1]: 65
2808 00:40:45.016910
2809 00:40:45.016961 Set Vref, RX VrefLevel [Byte0]: 66
2810 00:40:45.017012 [Byte1]: 66
2811 00:40:45.017062
2812 00:40:45.017113 Set Vref, RX VrefLevel [Byte0]: 67
2813 00:40:45.017163 [Byte1]: 67
2814 00:40:45.017213
2815 00:40:45.017263 Set Vref, RX VrefLevel [Byte0]: 68
2816 00:40:45.017313 [Byte1]: 68
2817 00:40:45.017363
2818 00:40:45.017414 Set Vref, RX VrefLevel [Byte0]: 69
2819 00:40:45.017464 [Byte1]: 69
2820 00:40:45.017515
2821 00:40:45.017565 Set Vref, RX VrefLevel [Byte0]: 70
2822 00:40:45.017614 [Byte1]: 70
2823 00:40:45.017665
2824 00:40:45.017715 Set Vref, RX VrefLevel [Byte0]: 71
2825 00:40:45.017766 [Byte1]: 71
2826 00:40:45.017816
2827 00:40:45.017866 Set Vref, RX VrefLevel [Byte0]: 72
2828 00:40:45.017917 [Byte1]: 72
2829 00:40:45.017967
2830 00:40:45.018016 Set Vref, RX VrefLevel [Byte0]: 73
2831 00:40:45.018067 [Byte1]: 73
2832 00:40:45.018118
2833 00:40:45.018172 Set Vref, RX VrefLevel [Byte0]: 74
2834 00:40:45.018257 [Byte1]: 74
2835 00:40:45.018307
2836 00:40:45.018357 Set Vref, RX VrefLevel [Byte0]: 75
2837 00:40:45.018407 [Byte1]: 75
2838 00:40:45.018458
2839 00:40:45.018509 Set Vref, RX VrefLevel [Byte0]: 76
2840 00:40:45.018559 [Byte1]: 76
2841 00:40:45.018609
2842 00:40:45.018660 Set Vref, RX VrefLevel [Byte0]: 77
2843 00:40:45.018710 [Byte1]: 77
2844 00:40:45.018761
2845 00:40:45.018811 Set Vref, RX VrefLevel [Byte0]: 78
2846 00:40:45.018861 [Byte1]: 78
2847 00:40:45.018913
2848 00:40:45.018963 Final RX Vref Byte 0 = 60 to rank0
2849 00:40:45.019014 Final RX Vref Byte 1 = 49 to rank0
2850 00:40:45.019065 Final RX Vref Byte 0 = 60 to rank1
2851 00:40:45.019116 Final RX Vref Byte 1 = 49 to rank1==
2852 00:40:45.019167 Dram Type= 6, Freq= 0, CH_0, rank 0
2853 00:40:45.019218 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2854 00:40:45.019283 ==
2855 00:40:45.019338 DQS Delay:
2856 00:40:45.019390 DQS0 = 0, DQS1 = 0
2857 00:40:45.019441 DQM Delay:
2858 00:40:45.019491 DQM0 = 119, DQM1 = 106
2859 00:40:45.019543 DQ Delay:
2860 00:40:45.019593 DQ0 =116, DQ1 =120, DQ2 =116, DQ3 =114
2861 00:40:45.019644 DQ4 =120, DQ5 =114, DQ6 =126, DQ7 =126
2862 00:40:45.019695 DQ8 =96, DQ9 =92, DQ10 =108, DQ11 =100
2863 00:40:45.019746 DQ12 =110, DQ13 =110, DQ14 =118, DQ15 =116
2864 00:40:45.019797
2865 00:40:45.019846
2866 00:40:45.019897 [DQSOSCAuto] RK0, (LSB)MR18= 0x13ff, (MSB)MR19= 0x403, tDQSOscB0 = 410 ps tDQSOscB1 = 402 ps
2867 00:40:45.019950 CH0 RK0: MR19=403, MR18=13FF
2868 00:40:45.020001 CH0_RK0: MR19=0x403, MR18=0x13FF, DQSOSC=402, MR23=63, INC=40, DEC=27
2869 00:40:45.020052
2870 00:40:45.020102 ----->DramcWriteLeveling(PI) begin...
2871 00:40:45.020155 ==
2872 00:40:45.020206 Dram Type= 6, Freq= 0, CH_0, rank 1
2873 00:40:45.020257 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2874 00:40:45.020308 ==
2875 00:40:45.020359 Write leveling (Byte 0): 32 => 32
2876 00:40:45.020409 Write leveling (Byte 1): 29 => 29
2877 00:40:45.020460 DramcWriteLeveling(PI) end<-----
2878 00:40:45.020510
2879 00:40:45.020561 ==
2880 00:40:45.020611 Dram Type= 6, Freq= 0, CH_0, rank 1
2881 00:40:45.020662 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2882 00:40:45.020712 ==
2883 00:40:45.020763 [Gating] SW mode calibration
2884 00:40:45.020814 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2885 00:40:45.020865 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2886 00:40:45.020916 0 15 0 | B1->B0 | 2424 3434 | 0 0 | (0 0) (0 0)
2887 00:40:45.020967 0 15 4 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
2888 00:40:45.021215 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2889 00:40:45.021272 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2890 00:40:45.021324 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2891 00:40:45.021376 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2892 00:40:45.021426 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2893 00:40:45.021477 0 15 28 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 1)
2894 00:40:45.021528 1 0 0 | B1->B0 | 2b2b 2323 | 1 0 | (1 0) (1 0)
2895 00:40:45.021579 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2896 00:40:45.021630 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2897 00:40:45.021681 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2898 00:40:45.021732 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2899 00:40:45.021782 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2900 00:40:45.021833 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2901 00:40:45.021884 1 0 28 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
2902 00:40:45.021935 1 1 0 | B1->B0 | 3535 4646 | 0 0 | (0 0) (0 0)
2903 00:40:45.021986 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2904 00:40:45.022037 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2905 00:40:45.022088 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2906 00:40:45.022138 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2907 00:40:45.022223 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2908 00:40:45.022288 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2909 00:40:45.022339 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2910 00:40:45.022410 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2911 00:40:45.022464 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2912 00:40:45.022515 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2913 00:40:45.022566 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2914 00:40:45.022616 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2915 00:40:45.022667 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2916 00:40:45.022718 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2917 00:40:45.022769 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2918 00:40:45.022819 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2919 00:40:45.022870 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2920 00:40:45.022920 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2921 00:40:45.022971 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2922 00:40:45.023021 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2923 00:40:45.023072 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2924 00:40:45.023122 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2925 00:40:45.023173 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2926 00:40:45.023223 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2927 00:40:45.023274 Total UI for P1: 0, mck2ui 16
2928 00:40:45.023326 best dqsien dly found for B0: ( 1, 3, 28)
2929 00:40:45.023377 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2930 00:40:45.023428 Total UI for P1: 0, mck2ui 16
2931 00:40:45.023478 best dqsien dly found for B1: ( 1, 4, 0)
2932 00:40:45.023529 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2933 00:40:45.023580 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2934 00:40:45.023631
2935 00:40:45.023682 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2936 00:40:45.023732 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2937 00:40:45.023783 [Gating] SW calibration Done
2938 00:40:45.158553 ==
2939 00:40:45.158686 Dram Type= 6, Freq= 0, CH_0, rank 1
2940 00:40:45.158752 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2941 00:40:45.158810 ==
2942 00:40:45.158866 RX Vref Scan: 0
2943 00:40:45.158922
2944 00:40:45.158975 RX Vref 0 -> 0, step: 1
2945 00:40:45.159028
2946 00:40:45.159080 RX Delay -40 -> 252, step: 8
2947 00:40:45.159133 iDelay=200, Bit 0, Center 115 (48 ~ 183) 136
2948 00:40:45.159186 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2949 00:40:45.159238 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2950 00:40:45.159290 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2951 00:40:45.159342 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2952 00:40:45.159393 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2953 00:40:45.159444 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2954 00:40:45.159495 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2955 00:40:45.159546 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2956 00:40:45.159598 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2957 00:40:45.159649 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2958 00:40:45.159700 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2959 00:40:45.159751 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2960 00:40:45.159802 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2961 00:40:45.159853 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2962 00:40:45.159904 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2963 00:40:45.159955 ==
2964 00:40:45.160006 Dram Type= 6, Freq= 0, CH_0, rank 1
2965 00:40:45.160057 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2966 00:40:45.160109 ==
2967 00:40:45.160160 DQS Delay:
2968 00:40:45.160211 DQS0 = 0, DQS1 = 0
2969 00:40:45.160262 DQM Delay:
2970 00:40:45.160314 DQM0 = 117, DQM1 = 107
2971 00:40:45.160364 DQ Delay:
2972 00:40:45.160415 DQ0 =115, DQ1 =119, DQ2 =111, DQ3 =115
2973 00:40:45.160467 DQ4 =119, DQ5 =111, DQ6 =123, DQ7 =123
2974 00:40:45.160519 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =103
2975 00:40:45.160570 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =111
2976 00:40:45.160621
2977 00:40:45.160672
2978 00:40:45.160722 ==
2979 00:40:45.160774 Dram Type= 6, Freq= 0, CH_0, rank 1
2980 00:40:45.160825 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2981 00:40:45.160876 ==
2982 00:40:45.160927
2983 00:40:45.160977
2984 00:40:45.161027 TX Vref Scan disable
2985 00:40:45.161078 == TX Byte 0 ==
2986 00:40:45.161129 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2987 00:40:45.161180 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2988 00:40:45.161232 == TX Byte 1 ==
2989 00:40:45.161282 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2990 00:40:45.161333 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2991 00:40:45.161384 ==
2992 00:40:45.161435 Dram Type= 6, Freq= 0, CH_0, rank 1
2993 00:40:45.161485 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2994 00:40:45.161536 ==
2995 00:40:45.161797 TX Vref=22, minBit 5, minWin=25, winSum=424
2996 00:40:45.161856 TX Vref=24, minBit 5, minWin=25, winSum=425
2997 00:40:45.161909 TX Vref=26, minBit 4, minWin=26, winSum=431
2998 00:40:45.161979 TX Vref=28, minBit 1, minWin=26, winSum=433
2999 00:40:45.162044 TX Vref=30, minBit 12, minWin=26, winSum=433
3000 00:40:45.162095 TX Vref=32, minBit 11, minWin=26, winSum=430
3001 00:40:45.162147 [TxChooseVref] Worse bit 1, Min win 26, Win sum 433, Final Vref 28
3002 00:40:45.162236
3003 00:40:45.162289 Final TX Range 1 Vref 28
3004 00:40:45.162340
3005 00:40:45.162391 ==
3006 00:40:45.162442 Dram Type= 6, Freq= 0, CH_0, rank 1
3007 00:40:45.162493 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3008 00:40:45.162544 ==
3009 00:40:45.162594
3010 00:40:45.162645
3011 00:40:45.162695 TX Vref Scan disable
3012 00:40:45.162745 == TX Byte 0 ==
3013 00:40:45.162796 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
3014 00:40:45.162848 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
3015 00:40:45.162899 == TX Byte 1 ==
3016 00:40:45.162949 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3017 00:40:45.163001 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3018 00:40:45.163051
3019 00:40:45.163101 [DATLAT]
3020 00:40:45.163152 Freq=1200, CH0 RK1
3021 00:40:45.163202
3022 00:40:45.163252 DATLAT Default: 0xd
3023 00:40:45.163303 0, 0xFFFF, sum = 0
3024 00:40:45.163356 1, 0xFFFF, sum = 0
3025 00:40:45.163407 2, 0xFFFF, sum = 0
3026 00:40:45.163459 3, 0xFFFF, sum = 0
3027 00:40:45.163511 4, 0xFFFF, sum = 0
3028 00:40:45.163562 5, 0xFFFF, sum = 0
3029 00:40:45.163613 6, 0xFFFF, sum = 0
3030 00:40:45.163665 7, 0xFFFF, sum = 0
3031 00:40:45.163755 8, 0xFFFF, sum = 0
3032 00:40:45.163868 9, 0xFFFF, sum = 0
3033 00:40:45.163925 10, 0xFFFF, sum = 0
3034 00:40:45.163978 11, 0xFFFF, sum = 0
3035 00:40:45.164030 12, 0x0, sum = 1
3036 00:40:45.164081 13, 0x0, sum = 2
3037 00:40:45.164133 14, 0x0, sum = 3
3038 00:40:45.164185 15, 0x0, sum = 4
3039 00:40:45.164237 best_step = 13
3040 00:40:45.164288
3041 00:40:45.164339 ==
3042 00:40:45.164390 Dram Type= 6, Freq= 0, CH_0, rank 1
3043 00:40:45.164442 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3044 00:40:45.164493 ==
3045 00:40:45.164544 RX Vref Scan: 0
3046 00:40:45.164594
3047 00:40:45.164645 RX Vref 0 -> 0, step: 1
3048 00:40:45.164696
3049 00:40:45.164747 RX Delay -21 -> 252, step: 4
3050 00:40:45.164798 iDelay=199, Bit 0, Center 112 (47 ~ 178) 132
3051 00:40:45.164850 iDelay=199, Bit 1, Center 118 (47 ~ 190) 144
3052 00:40:45.164901 iDelay=199, Bit 2, Center 110 (43 ~ 178) 136
3053 00:40:45.164952 iDelay=199, Bit 3, Center 114 (43 ~ 186) 144
3054 00:40:45.165003 iDelay=199, Bit 4, Center 116 (47 ~ 186) 140
3055 00:40:45.165053 iDelay=199, Bit 5, Center 110 (43 ~ 178) 136
3056 00:40:45.165105 iDelay=199, Bit 6, Center 126 (55 ~ 198) 144
3057 00:40:45.165156 iDelay=199, Bit 7, Center 124 (55 ~ 194) 140
3058 00:40:45.165206 iDelay=199, Bit 8, Center 96 (27 ~ 166) 140
3059 00:40:45.165257 iDelay=199, Bit 9, Center 94 (27 ~ 162) 136
3060 00:40:45.165309 iDelay=199, Bit 10, Center 110 (43 ~ 178) 136
3061 00:40:45.165360 iDelay=199, Bit 11, Center 100 (35 ~ 166) 132
3062 00:40:45.165411 iDelay=199, Bit 12, Center 112 (47 ~ 178) 132
3063 00:40:45.165462 iDelay=199, Bit 13, Center 114 (47 ~ 182) 136
3064 00:40:45.165514 iDelay=199, Bit 14, Center 118 (55 ~ 182) 128
3065 00:40:45.165565 iDelay=199, Bit 15, Center 116 (51 ~ 182) 132
3066 00:40:45.165616 ==
3067 00:40:45.165667 Dram Type= 6, Freq= 0, CH_0, rank 1
3068 00:40:45.165719 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3069 00:40:45.165770 ==
3070 00:40:45.165821 DQS Delay:
3071 00:40:45.165872 DQS0 = 0, DQS1 = 0
3072 00:40:45.165924 DQM Delay:
3073 00:40:45.165974 DQM0 = 116, DQM1 = 107
3074 00:40:45.166025 DQ Delay:
3075 00:40:45.166076 DQ0 =112, DQ1 =118, DQ2 =110, DQ3 =114
3076 00:40:45.166127 DQ4 =116, DQ5 =110, DQ6 =126, DQ7 =124
3077 00:40:45.166206 DQ8 =96, DQ9 =94, DQ10 =110, DQ11 =100
3078 00:40:45.166273 DQ12 =112, DQ13 =114, DQ14 =118, DQ15 =116
3079 00:40:45.166324
3080 00:40:45.166375
3081 00:40:45.166426 [DQSOSCAuto] RK1, (LSB)MR18= 0x10ea, (MSB)MR19= 0x403, tDQSOscB0 = 419 ps tDQSOscB1 = 403 ps
3082 00:40:45.166479 CH0 RK1: MR19=403, MR18=10EA
3083 00:40:45.166531 CH0_RK1: MR19=0x403, MR18=0x10EA, DQSOSC=403, MR23=63, INC=40, DEC=26
3084 00:40:45.166582 [RxdqsGatingPostProcess] freq 1200
3085 00:40:45.166633 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3086 00:40:45.166685 best DQS0 dly(2T, 0.5T) = (0, 11)
3087 00:40:45.166737 best DQS1 dly(2T, 0.5T) = (0, 12)
3088 00:40:45.166788 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3089 00:40:45.166839 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3090 00:40:45.166891 best DQS0 dly(2T, 0.5T) = (0, 11)
3091 00:40:45.166942 best DQS1 dly(2T, 0.5T) = (0, 12)
3092 00:40:45.166993 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3093 00:40:45.167045 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3094 00:40:45.167095 Pre-setting of DQS Precalculation
3095 00:40:45.167146 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3096 00:40:45.167198 ==
3097 00:40:45.167249 Dram Type= 6, Freq= 0, CH_1, rank 0
3098 00:40:45.167300 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3099 00:40:45.167351 ==
3100 00:40:45.167403 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3101 00:40:45.167454 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3102 00:40:45.167506 [CA 0] Center 38 (8~68) winsize 61
3103 00:40:45.167557 [CA 1] Center 37 (7~68) winsize 62
3104 00:40:45.167608 [CA 2] Center 34 (4~64) winsize 61
3105 00:40:45.167658 [CA 3] Center 33 (3~64) winsize 62
3106 00:40:45.167709 [CA 4] Center 34 (4~64) winsize 61
3107 00:40:45.167760 [CA 5] Center 33 (3~64) winsize 62
3108 00:40:45.167811
3109 00:40:45.167863 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3110 00:40:45.167914
3111 00:40:45.168011 [CATrainingPosCal] consider 1 rank data
3112 00:40:45.168074 u2DelayCellTimex100 = 270/100 ps
3113 00:40:45.168127 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3114 00:40:45.168179 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3115 00:40:45.168230 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3116 00:40:45.168282 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3117 00:40:45.168333 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3118 00:40:45.168384 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3119 00:40:45.168447
3120 00:40:45.168502 CA PerBit enable=1, Macro0, CA PI delay=33
3121 00:40:45.168554
3122 00:40:45.168605 [CBTSetCACLKResult] CA Dly = 33
3123 00:40:45.168657 CS Dly: 6 (0~37)
3124 00:40:45.168708 ==
3125 00:40:45.168759 Dram Type= 6, Freq= 0, CH_1, rank 1
3126 00:40:45.168811 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3127 00:40:45.168863 ==
3128 00:40:45.168914 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3129 00:40:45.169162 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
3130 00:40:45.169220 [CA 0] Center 37 (8~67) winsize 60
3131 00:40:45.169273 [CA 1] Center 37 (7~68) winsize 62
3132 00:40:45.169326 [CA 2] Center 34 (4~65) winsize 62
3133 00:40:45.169378 [CA 3] Center 33 (3~64) winsize 62
3134 00:40:45.169428 [CA 4] Center 34 (4~64) winsize 61
3135 00:40:45.169480 [CA 5] Center 33 (3~64) winsize 62
3136 00:40:45.169531
3137 00:40:45.169582 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3138 00:40:45.169633
3139 00:40:45.169684 [CATrainingPosCal] consider 2 rank data
3140 00:40:45.169736 u2DelayCellTimex100 = 270/100 ps
3141 00:40:45.169787 CA0 delay=37 (8~67),Diff = 4 PI (19 cell)
3142 00:40:45.169839 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3143 00:40:45.169890 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3144 00:40:45.169941 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3145 00:40:45.169993 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3146 00:40:45.170044 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3147 00:40:45.170095
3148 00:40:45.170146 CA PerBit enable=1, Macro0, CA PI delay=33
3149 00:40:45.170242
3150 00:40:45.170294 [CBTSetCACLKResult] CA Dly = 33
3151 00:40:45.170346 CS Dly: 7 (0~40)
3152 00:40:45.170397
3153 00:40:45.170448 ----->DramcWriteLeveling(PI) begin...
3154 00:40:45.170501 ==
3155 00:40:45.170552 Dram Type= 6, Freq= 0, CH_1, rank 0
3156 00:40:45.170604 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3157 00:40:45.170655 ==
3158 00:40:45.170706 Write leveling (Byte 0): 25 => 25
3159 00:40:45.170757 Write leveling (Byte 1): 28 => 28
3160 00:40:45.170808 DramcWriteLeveling(PI) end<-----
3161 00:40:45.170859
3162 00:40:45.170927 ==
3163 00:40:45.170992 Dram Type= 6, Freq= 0, CH_1, rank 0
3164 00:40:45.171045 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3165 00:40:45.171097 ==
3166 00:40:45.171148 [Gating] SW mode calibration
3167 00:40:45.171200 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3168 00:40:45.171253 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3169 00:40:45.171305 0 15 0 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
3170 00:40:45.171357 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3171 00:40:45.171408 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3172 00:40:45.171460 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3173 00:40:45.171511 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3174 00:40:45.171563 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3175 00:40:45.171614 0 15 24 | B1->B0 | 3434 2c2c | 1 1 | (1 1) (1 0)
3176 00:40:45.171665 0 15 28 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
3177 00:40:45.171717 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3178 00:40:45.171768 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3179 00:40:45.171819 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3180 00:40:45.171871 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3181 00:40:45.171922 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3182 00:40:45.171973 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3183 00:40:45.172024 1 0 24 | B1->B0 | 2c2c 3a3a | 0 1 | (0 0) (0 0)
3184 00:40:45.172076 1 0 28 | B1->B0 | 4444 4646 | 1 0 | (0 0) (0 0)
3185 00:40:45.172127 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3186 00:40:45.172178 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3187 00:40:45.172229 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3188 00:40:45.172280 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3189 00:40:45.172331 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3190 00:40:45.172382 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3191 00:40:45.172433 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3192 00:40:45.172483 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3193 00:40:45.172534 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3194 00:40:45.172585 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3195 00:40:45.172636 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3196 00:40:45.172687 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3197 00:40:45.172738 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3198 00:40:45.172789 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3199 00:40:45.172839 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3200 00:40:45.172890 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3201 00:40:45.172940 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3202 00:40:45.172991 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3203 00:40:45.173043 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3204 00:40:45.173093 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3205 00:40:45.173144 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3206 00:40:45.173195 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3207 00:40:45.173246 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3208 00:40:45.173297 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3209 00:40:45.173348 Total UI for P1: 0, mck2ui 16
3210 00:40:45.173400 best dqsien dly found for B0: ( 1, 3, 24)
3211 00:40:45.173452 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3212 00:40:45.173502 Total UI for P1: 0, mck2ui 16
3213 00:40:45.173554 best dqsien dly found for B1: ( 1, 3, 26)
3214 00:40:45.173605 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3215 00:40:45.173656 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3216 00:40:45.173706
3217 00:40:45.173787 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3218 00:40:45.173839 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3219 00:40:45.173889 [Gating] SW calibration Done
3220 00:40:45.173940 ==
3221 00:40:45.173991 Dram Type= 6, Freq= 0, CH_1, rank 0
3222 00:40:45.174042 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3223 00:40:45.174093 ==
3224 00:40:45.174144 RX Vref Scan: 0
3225 00:40:45.174234
3226 00:40:45.174286 RX Vref 0 -> 0, step: 1
3227 00:40:45.174337
3228 00:40:45.174388 RX Delay -40 -> 252, step: 8
3229 00:40:45.174439 iDelay=200, Bit 0, Center 123 (48 ~ 199) 152
3230 00:40:45.174490 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3231 00:40:45.174541 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
3232 00:40:45.174592 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3233 00:40:45.174643 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3234 00:40:45.174887 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3235 00:40:45.174944 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3236 00:40:45.174997 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3237 00:40:45.175048 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3238 00:40:45.175100 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
3239 00:40:45.175152 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3240 00:40:45.175204 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
3241 00:40:45.175254 iDelay=200, Bit 12, Center 115 (40 ~ 191) 152
3242 00:40:45.175305 iDelay=200, Bit 13, Center 115 (40 ~ 191) 152
3243 00:40:45.175357 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
3244 00:40:45.175408 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3245 00:40:45.175459 ==
3246 00:40:45.175510 Dram Type= 6, Freq= 0, CH_1, rank 0
3247 00:40:45.175561 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3248 00:40:45.175613 ==
3249 00:40:45.175664 DQS Delay:
3250 00:40:45.175715 DQS0 = 0, DQS1 = 0
3251 00:40:45.175766 DQM Delay:
3252 00:40:45.175817 DQM0 = 117, DQM1 = 108
3253 00:40:45.175868 DQ Delay:
3254 00:40:45.175919 DQ0 =123, DQ1 =111, DQ2 =111, DQ3 =115
3255 00:40:45.175970 DQ4 =111, DQ5 =127, DQ6 =123, DQ7 =115
3256 00:40:45.176021 DQ8 =95, DQ9 =103, DQ10 =111, DQ11 =95
3257 00:40:45.176072 DQ12 =115, DQ13 =115, DQ14 =115, DQ15 =119
3258 00:40:45.176122
3259 00:40:45.176172
3260 00:40:45.176223 ==
3261 00:40:45.176273 Dram Type= 6, Freq= 0, CH_1, rank 0
3262 00:40:45.176324 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3263 00:40:45.176376 ==
3264 00:40:45.176427
3265 00:40:45.176478
3266 00:40:45.176528 TX Vref Scan disable
3267 00:40:45.176579 == TX Byte 0 ==
3268 00:40:45.176630 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3269 00:40:45.176681 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3270 00:40:45.176733 == TX Byte 1 ==
3271 00:40:45.176783 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3272 00:40:45.176834 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3273 00:40:45.176886 ==
3274 00:40:45.176937 Dram Type= 6, Freq= 0, CH_1, rank 0
3275 00:40:45.176988 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3276 00:40:45.177039 ==
3277 00:40:45.177090 TX Vref=22, minBit 8, minWin=25, winSum=422
3278 00:40:45.177142 TX Vref=24, minBit 9, minWin=25, winSum=426
3279 00:40:45.177194 TX Vref=26, minBit 9, minWin=25, winSum=431
3280 00:40:45.177246 TX Vref=28, minBit 8, minWin=26, winSum=434
3281 00:40:45.177297 TX Vref=30, minBit 11, minWin=25, winSum=434
3282 00:40:45.177348 TX Vref=32, minBit 9, minWin=25, winSum=428
3283 00:40:45.177400 [TxChooseVref] Worse bit 8, Min win 26, Win sum 434, Final Vref 28
3284 00:40:45.177452
3285 00:40:45.177503 Final TX Range 1 Vref 28
3286 00:40:45.177554
3287 00:40:45.177604 ==
3288 00:40:45.177655 Dram Type= 6, Freq= 0, CH_1, rank 0
3289 00:40:45.177706 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3290 00:40:45.177757 ==
3291 00:40:45.177808
3292 00:40:45.177858
3293 00:40:45.177909 TX Vref Scan disable
3294 00:40:45.177960 == TX Byte 0 ==
3295 00:40:45.178010 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3296 00:40:45.178061 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3297 00:40:45.178112 == TX Byte 1 ==
3298 00:40:45.178169 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3299 00:40:45.178258 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3300 00:40:45.178308
3301 00:40:45.178358 [DATLAT]
3302 00:40:45.178408 Freq=1200, CH1 RK0
3303 00:40:45.178460
3304 00:40:45.178510 DATLAT Default: 0xd
3305 00:40:45.178560 0, 0xFFFF, sum = 0
3306 00:40:45.178612 1, 0xFFFF, sum = 0
3307 00:40:45.178702 2, 0xFFFF, sum = 0
3308 00:40:45.178781 3, 0xFFFF, sum = 0
3309 00:40:45.178834 4, 0xFFFF, sum = 0
3310 00:40:45.178886 5, 0xFFFF, sum = 0
3311 00:40:45.178938 6, 0xFFFF, sum = 0
3312 00:40:45.178989 7, 0xFFFF, sum = 0
3313 00:40:45.179040 8, 0xFFFF, sum = 0
3314 00:40:45.179091 9, 0xFFFF, sum = 0
3315 00:40:45.179142 10, 0xFFFF, sum = 0
3316 00:40:45.179193 11, 0xFFFF, sum = 0
3317 00:40:45.179244 12, 0x0, sum = 1
3318 00:40:45.179295 13, 0x0, sum = 2
3319 00:40:45.179345 14, 0x0, sum = 3
3320 00:40:45.179396 15, 0x0, sum = 4
3321 00:40:45.179447 best_step = 13
3322 00:40:45.179496
3323 00:40:45.179546 ==
3324 00:40:45.179597 Dram Type= 6, Freq= 0, CH_1, rank 0
3325 00:40:45.179647 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3326 00:40:45.179698 ==
3327 00:40:45.179748 RX Vref Scan: 1
3328 00:40:45.179828
3329 00:40:45.179878 Set Vref Range= 32 -> 127
3330 00:40:45.179929
3331 00:40:45.179979 RX Vref 32 -> 127, step: 1
3332 00:40:45.180030
3333 00:40:45.180080 RX Delay -21 -> 252, step: 4
3334 00:40:45.180131
3335 00:40:45.180181 Set Vref, RX VrefLevel [Byte0]: 32
3336 00:40:45.180232 [Byte1]: 32
3337 00:40:45.180283
3338 00:40:45.180332 Set Vref, RX VrefLevel [Byte0]: 33
3339 00:40:45.180385 [Byte1]: 33
3340 00:40:45.180435
3341 00:40:45.180485 Set Vref, RX VrefLevel [Byte0]: 34
3342 00:40:45.180536 [Byte1]: 34
3343 00:40:45.180586
3344 00:40:45.180636 Set Vref, RX VrefLevel [Byte0]: 35
3345 00:40:45.180686 [Byte1]: 35
3346 00:40:45.180737
3347 00:40:45.180786 Set Vref, RX VrefLevel [Byte0]: 36
3348 00:40:45.180836 [Byte1]: 36
3349 00:40:45.180886
3350 00:40:45.180936 Set Vref, RX VrefLevel [Byte0]: 37
3351 00:40:45.180985 [Byte1]: 37
3352 00:40:45.181036
3353 00:40:45.181086 Set Vref, RX VrefLevel [Byte0]: 38
3354 00:40:45.181137 [Byte1]: 38
3355 00:40:45.181187
3356 00:40:45.181237 Set Vref, RX VrefLevel [Byte0]: 39
3357 00:40:45.181288 [Byte1]: 39
3358 00:40:45.181338
3359 00:40:45.181388 Set Vref, RX VrefLevel [Byte0]: 40
3360 00:40:45.181438 [Byte1]: 40
3361 00:40:45.181489
3362 00:40:45.181538 Set Vref, RX VrefLevel [Byte0]: 41
3363 00:40:45.181589 [Byte1]: 41
3364 00:40:45.181640
3365 00:40:45.181690 Set Vref, RX VrefLevel [Byte0]: 42
3366 00:40:45.181740 [Byte1]: 42
3367 00:40:45.181791
3368 00:40:45.181877 Set Vref, RX VrefLevel [Byte0]: 43
3369 00:40:45.181927 [Byte1]: 43
3370 00:40:45.181978
3371 00:40:45.182028 Set Vref, RX VrefLevel [Byte0]: 44
3372 00:40:45.182079 [Byte1]: 44
3373 00:40:45.182129
3374 00:40:45.182204 Set Vref, RX VrefLevel [Byte0]: 45
3375 00:40:45.182268 [Byte1]: 45
3376 00:40:45.182319
3377 00:40:45.182370 Set Vref, RX VrefLevel [Byte0]: 46
3378 00:40:45.182420 [Byte1]: 46
3379 00:40:45.182470
3380 00:40:45.182520 Set Vref, RX VrefLevel [Byte0]: 47
3381 00:40:45.182571 [Byte1]: 47
3382 00:40:45.182621
3383 00:40:45.182671 Set Vref, RX VrefLevel [Byte0]: 48
3384 00:40:45.182721 [Byte1]: 48
3385 00:40:45.182772
3386 00:40:45.182822 Set Vref, RX VrefLevel [Byte0]: 49
3387 00:40:45.182873 [Byte1]: 49
3388 00:40:45.182923
3389 00:40:45.182973 Set Vref, RX VrefLevel [Byte0]: 50
3390 00:40:45.183024 [Byte1]: 50
3391 00:40:45.183074
3392 00:40:45.183125 Set Vref, RX VrefLevel [Byte0]: 51
3393 00:40:45.183372 [Byte1]: 51
3394 00:40:45.183433
3395 00:40:45.183485 Set Vref, RX VrefLevel [Byte0]: 52
3396 00:40:45.183536 [Byte1]: 52
3397 00:40:45.183587
3398 00:40:45.183638 Set Vref, RX VrefLevel [Byte0]: 53
3399 00:40:45.183688 [Byte1]: 53
3400 00:40:45.183739
3401 00:40:45.183789 Set Vref, RX VrefLevel [Byte0]: 54
3402 00:40:45.183839 [Byte1]: 54
3403 00:40:45.183889
3404 00:40:45.183939 Set Vref, RX VrefLevel [Byte0]: 55
3405 00:40:45.183990 [Byte1]: 55
3406 00:40:45.184040
3407 00:40:45.184091 Set Vref, RX VrefLevel [Byte0]: 56
3408 00:40:45.184141 [Byte1]: 56
3409 00:40:45.184192
3410 00:40:45.184242 Set Vref, RX VrefLevel [Byte0]: 57
3411 00:40:45.184293 [Byte1]: 57
3412 00:40:45.184343
3413 00:40:45.184403 Set Vref, RX VrefLevel [Byte0]: 58
3414 00:40:45.184477 [Byte1]: 58
3415 00:40:45.184531
3416 00:40:45.184582 Set Vref, RX VrefLevel [Byte0]: 59
3417 00:40:45.184634 [Byte1]: 59
3418 00:40:45.184685
3419 00:40:45.184735 Set Vref, RX VrefLevel [Byte0]: 60
3420 00:40:45.184786 [Byte1]: 60
3421 00:40:45.184837
3422 00:40:45.184887 Set Vref, RX VrefLevel [Byte0]: 61
3423 00:40:45.184939 [Byte1]: 61
3424 00:40:45.184990
3425 00:40:45.185040 Set Vref, RX VrefLevel [Byte0]: 62
3426 00:40:45.185091 [Byte1]: 62
3427 00:40:45.185142
3428 00:40:45.185193 Set Vref, RX VrefLevel [Byte0]: 63
3429 00:40:45.185243 [Byte1]: 63
3430 00:40:45.185294
3431 00:40:45.185344 Set Vref, RX VrefLevel [Byte0]: 64
3432 00:40:45.185394 [Byte1]: 64
3433 00:40:45.185445
3434 00:40:45.185495 Set Vref, RX VrefLevel [Byte0]: 65
3435 00:40:45.185546 [Byte1]: 65
3436 00:40:45.185596
3437 00:40:45.185646 Set Vref, RX VrefLevel [Byte0]: 66
3438 00:40:45.185697 [Byte1]: 66
3439 00:40:45.185748
3440 00:40:45.185833 Set Vref, RX VrefLevel [Byte0]: 67
3441 00:40:45.185884 [Byte1]: 67
3442 00:40:45.185934
3443 00:40:45.185985 Set Vref, RX VrefLevel [Byte0]: 68
3444 00:40:45.186035 [Byte1]: 68
3445 00:40:45.186086
3446 00:40:45.186136 Final RX Vref Byte 0 = 52 to rank0
3447 00:40:45.186213 Final RX Vref Byte 1 = 53 to rank0
3448 00:40:45.186279 Final RX Vref Byte 0 = 52 to rank1
3449 00:40:45.186330 Final RX Vref Byte 1 = 53 to rank1==
3450 00:40:45.186381 Dram Type= 6, Freq= 0, CH_1, rank 0
3451 00:40:45.186432 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3452 00:40:45.186483 ==
3453 00:40:45.186534 DQS Delay:
3454 00:40:45.186585 DQS0 = 0, DQS1 = 0
3455 00:40:45.186636 DQM Delay:
3456 00:40:45.186686 DQM0 = 116, DQM1 = 110
3457 00:40:45.186736 DQ Delay:
3458 00:40:45.186787 DQ0 =120, DQ1 =112, DQ2 =110, DQ3 =112
3459 00:40:45.186837 DQ4 =114, DQ5 =128, DQ6 =124, DQ7 =112
3460 00:40:45.186888 DQ8 =98, DQ9 =104, DQ10 =112, DQ11 =100
3461 00:40:45.186940 DQ12 =118, DQ13 =116, DQ14 =118, DQ15 =118
3462 00:40:45.186990
3463 00:40:45.187040
3464 00:40:45.187090 [DQSOSCAuto] RK0, (LSB)MR18= 0x5f8, (MSB)MR19= 0x403, tDQSOscB0 = 413 ps tDQSOscB1 = 408 ps
3465 00:40:45.187142 CH1 RK0: MR19=403, MR18=5F8
3466 00:40:45.187193 CH1_RK0: MR19=0x403, MR18=0x5F8, DQSOSC=408, MR23=63, INC=39, DEC=26
3467 00:40:45.187245
3468 00:40:45.187294 ----->DramcWriteLeveling(PI) begin...
3469 00:40:45.187346 ==
3470 00:40:45.187397 Dram Type= 6, Freq= 0, CH_1, rank 1
3471 00:40:45.187448 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3472 00:40:45.187498 ==
3473 00:40:45.187548 Write leveling (Byte 0): 24 => 24
3474 00:40:45.187599 Write leveling (Byte 1): 29 => 29
3475 00:40:45.187650 DramcWriteLeveling(PI) end<-----
3476 00:40:45.187700
3477 00:40:45.187750 ==
3478 00:40:45.187801 Dram Type= 6, Freq= 0, CH_1, rank 1
3479 00:40:45.187851 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3480 00:40:45.187902 ==
3481 00:40:45.187953 [Gating] SW mode calibration
3482 00:40:45.188004 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3483 00:40:45.188055 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3484 00:40:45.188106 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3485 00:40:45.188157 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3486 00:40:45.188208 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3487 00:40:45.188258 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3488 00:40:45.188309 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3489 00:40:45.188359 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3490 00:40:45.188409 0 15 24 | B1->B0 | 2d2d 3333 | 0 0 | (1 0) (0 1)
3491 00:40:45.188460 0 15 28 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
3492 00:40:45.188510 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3493 00:40:45.188561 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3494 00:40:45.188611 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3495 00:40:45.188661 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3496 00:40:45.188712 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3497 00:40:45.188763 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3498 00:40:45.188813 1 0 24 | B1->B0 | 3838 2c2c | 1 1 | (0 0) (0 0)
3499 00:40:45.188864 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3500 00:40:45.188915 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3501 00:40:45.188966 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3502 00:40:45.189017 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3503 00:40:45.189068 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3504 00:40:45.189118 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3505 00:40:45.189168 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3506 00:40:45.189219 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3507 00:40:45.189269 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3508 00:40:45.189319 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3509 00:40:45.189369 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3510 00:40:45.189420 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3511 00:40:45.189470 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3512 00:40:45.189521 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3513 00:40:45.189571 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3514 00:40:45.189621 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3515 00:40:45.189900 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3516 00:40:45.190028 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3517 00:40:45.190112 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3518 00:40:45.190225 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3519 00:40:45.190279 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3520 00:40:45.190330 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3521 00:40:45.190382 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3522 00:40:45.190434 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3523 00:40:45.190485 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3524 00:40:45.190536 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3525 00:40:45.190587 Total UI for P1: 0, mck2ui 16
3526 00:40:45.190638 best dqsien dly found for B0: ( 1, 3, 26)
3527 00:40:45.190695 Total UI for P1: 0, mck2ui 16
3528 00:40:45.190770 best dqsien dly found for B1: ( 1, 3, 26)
3529 00:40:45.190824 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3530 00:40:45.190876 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3531 00:40:45.190927
3532 00:40:45.190978 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3533 00:40:45.191029 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3534 00:40:45.191080 [Gating] SW calibration Done
3535 00:40:45.191131 ==
3536 00:40:45.191183 Dram Type= 6, Freq= 0, CH_1, rank 1
3537 00:40:45.191235 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3538 00:40:45.191287 ==
3539 00:40:45.191337 RX Vref Scan: 0
3540 00:40:45.191388
3541 00:40:45.191438 RX Vref 0 -> 0, step: 1
3542 00:40:45.191490
3543 00:40:45.191541 RX Delay -40 -> 252, step: 8
3544 00:40:45.191592 iDelay=208, Bit 0, Center 119 (48 ~ 191) 144
3545 00:40:45.191643 iDelay=208, Bit 1, Center 111 (40 ~ 183) 144
3546 00:40:45.191693 iDelay=208, Bit 2, Center 103 (32 ~ 175) 144
3547 00:40:45.191744 iDelay=208, Bit 3, Center 111 (40 ~ 183) 144
3548 00:40:45.191795 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152
3549 00:40:45.191846 iDelay=208, Bit 5, Center 123 (48 ~ 199) 152
3550 00:40:45.191897 iDelay=208, Bit 6, Center 131 (56 ~ 207) 152
3551 00:40:45.191948 iDelay=208, Bit 7, Center 115 (40 ~ 191) 152
3552 00:40:45.191999 iDelay=208, Bit 8, Center 95 (24 ~ 167) 144
3553 00:40:45.192050 iDelay=208, Bit 9, Center 103 (32 ~ 175) 144
3554 00:40:45.192100 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3555 00:40:45.192151 iDelay=208, Bit 11, Center 99 (24 ~ 175) 152
3556 00:40:45.192202 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3557 00:40:45.192252 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3558 00:40:45.192303 iDelay=208, Bit 14, Center 115 (40 ~ 191) 152
3559 00:40:45.192354 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3560 00:40:45.192404 ==
3561 00:40:45.192455 Dram Type= 6, Freq= 0, CH_1, rank 1
3562 00:40:45.192506 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3563 00:40:45.192557 ==
3564 00:40:45.192607 DQS Delay:
3565 00:40:45.192658 DQS0 = 0, DQS1 = 0
3566 00:40:45.192708 DQM Delay:
3567 00:40:45.192759 DQM0 = 116, DQM1 = 110
3568 00:40:45.192809 DQ Delay:
3569 00:40:45.192859 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =111
3570 00:40:45.192910 DQ4 =115, DQ5 =123, DQ6 =131, DQ7 =115
3571 00:40:45.192961 DQ8 =95, DQ9 =103, DQ10 =111, DQ11 =99
3572 00:40:45.193012 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3573 00:40:45.193063
3574 00:40:45.193113
3575 00:40:45.193163 ==
3576 00:40:45.193214 Dram Type= 6, Freq= 0, CH_1, rank 1
3577 00:40:45.193265 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3578 00:40:45.193316 ==
3579 00:40:45.193366
3580 00:40:45.193416
3581 00:40:45.193466 TX Vref Scan disable
3582 00:40:45.193516 == TX Byte 0 ==
3583 00:40:45.193567 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3584 00:40:45.193618 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3585 00:40:45.193668 == TX Byte 1 ==
3586 00:40:45.193719 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3587 00:40:45.193769 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3588 00:40:45.193820 ==
3589 00:40:45.193871 Dram Type= 6, Freq= 0, CH_1, rank 1
3590 00:40:45.193922 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3591 00:40:45.193973 ==
3592 00:40:45.194023 TX Vref=22, minBit 8, minWin=25, winSum=423
3593 00:40:45.194075 TX Vref=24, minBit 8, minWin=26, winSum=430
3594 00:40:45.194126 TX Vref=26, minBit 8, minWin=26, winSum=434
3595 00:40:45.194219 TX Vref=28, minBit 9, minWin=26, winSum=434
3596 00:40:45.194272 TX Vref=30, minBit 8, minWin=26, winSum=437
3597 00:40:45.194323 TX Vref=32, minBit 7, minWin=26, winSum=433
3598 00:40:45.194374 [TxChooseVref] Worse bit 8, Min win 26, Win sum 437, Final Vref 30
3599 00:40:45.194425
3600 00:40:45.194476 Final TX Range 1 Vref 30
3601 00:40:45.194527
3602 00:40:45.194577 ==
3603 00:40:45.194628 Dram Type= 6, Freq= 0, CH_1, rank 1
3604 00:40:45.194679 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3605 00:40:45.194729 ==
3606 00:40:45.194779
3607 00:40:45.194830
3608 00:40:45.194880 TX Vref Scan disable
3609 00:40:45.194930 == TX Byte 0 ==
3610 00:40:45.194980 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3611 00:40:45.195030 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3612 00:40:45.195080 == TX Byte 1 ==
3613 00:40:45.195131 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3614 00:40:45.195181 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3615 00:40:45.195231
3616 00:40:45.195281 [DATLAT]
3617 00:40:45.195333 Freq=1200, CH1 RK1
3618 00:40:45.195383
3619 00:40:45.195433 DATLAT Default: 0xd
3620 00:40:45.195484 0, 0xFFFF, sum = 0
3621 00:40:45.195536 1, 0xFFFF, sum = 0
3622 00:40:45.195587 2, 0xFFFF, sum = 0
3623 00:40:45.195638 3, 0xFFFF, sum = 0
3624 00:40:45.195703 4, 0xFFFF, sum = 0
3625 00:40:45.195770 5, 0xFFFF, sum = 0
3626 00:40:45.195823 6, 0xFFFF, sum = 0
3627 00:40:45.195875 7, 0xFFFF, sum = 0
3628 00:40:45.195926 8, 0xFFFF, sum = 0
3629 00:40:45.195977 9, 0xFFFF, sum = 0
3630 00:40:45.196028 10, 0xFFFF, sum = 0
3631 00:40:45.196079 11, 0xFFFF, sum = 0
3632 00:40:45.196130 12, 0x0, sum = 1
3633 00:40:45.196182 13, 0x0, sum = 2
3634 00:40:45.196233 14, 0x0, sum = 3
3635 00:40:45.196284 15, 0x0, sum = 4
3636 00:40:45.196335 best_step = 13
3637 00:40:45.196385
3638 00:40:45.196436 ==
3639 00:40:45.196487 Dram Type= 6, Freq= 0, CH_1, rank 1
3640 00:40:45.196537 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3641 00:40:45.196589 ==
3642 00:40:45.196639 RX Vref Scan: 0
3643 00:40:45.196690
3644 00:40:45.196741 RX Vref 0 -> 0, step: 1
3645 00:40:45.196791
3646 00:40:45.196841 RX Delay -21 -> 252, step: 4
3647 00:40:45.196891 iDelay=199, Bit 0, Center 120 (51 ~ 190) 140
3648 00:40:45.196942 iDelay=199, Bit 1, Center 112 (47 ~ 178) 132
3649 00:40:45.196992 iDelay=199, Bit 2, Center 108 (43 ~ 174) 132
3650 00:40:45.197043 iDelay=199, Bit 3, Center 112 (47 ~ 178) 132
3651 00:40:45.197093 iDelay=199, Bit 4, Center 116 (47 ~ 186) 140
3652 00:40:45.197337 iDelay=199, Bit 5, Center 126 (59 ~ 194) 136
3653 00:40:45.197395 iDelay=199, Bit 6, Center 130 (63 ~ 198) 136
3654 00:40:45.197447 iDelay=199, Bit 7, Center 116 (51 ~ 182) 132
3655 00:40:45.197498 iDelay=199, Bit 8, Center 96 (31 ~ 162) 132
3656 00:40:45.197549 iDelay=199, Bit 9, Center 100 (35 ~ 166) 132
3657 00:40:45.197600 iDelay=199, Bit 10, Center 110 (43 ~ 178) 136
3658 00:40:45.197651 iDelay=199, Bit 11, Center 100 (35 ~ 166) 132
3659 00:40:45.197702 iDelay=199, Bit 12, Center 118 (51 ~ 186) 136
3660 00:40:45.197753 iDelay=199, Bit 13, Center 118 (51 ~ 186) 136
3661 00:40:45.197803 iDelay=199, Bit 14, Center 118 (51 ~ 186) 136
3662 00:40:45.197854 iDelay=199, Bit 15, Center 120 (51 ~ 190) 140
3663 00:40:45.197905 ==
3664 00:40:45.197956 Dram Type= 6, Freq= 0, CH_1, rank 1
3665 00:40:45.198007 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3666 00:40:45.198058 ==
3667 00:40:45.198108 DQS Delay:
3668 00:40:45.198158 DQS0 = 0, DQS1 = 0
3669 00:40:45.198251 DQM Delay:
3670 00:40:45.198302 DQM0 = 117, DQM1 = 110
3671 00:40:45.198353 DQ Delay:
3672 00:40:45.198403 DQ0 =120, DQ1 =112, DQ2 =108, DQ3 =112
3673 00:40:45.198454 DQ4 =116, DQ5 =126, DQ6 =130, DQ7 =116
3674 00:40:45.198505 DQ8 =96, DQ9 =100, DQ10 =110, DQ11 =100
3675 00:40:45.198556 DQ12 =118, DQ13 =118, DQ14 =118, DQ15 =120
3676 00:40:45.198606
3677 00:40:45.198657
3678 00:40:45.198707 [DQSOSCAuto] RK1, (LSB)MR18= 0xf8f3, (MSB)MR19= 0x303, tDQSOscB0 = 415 ps tDQSOscB1 = 413 ps
3679 00:40:45.198759 CH1 RK1: MR19=303, MR18=F8F3
3680 00:40:45.198809 CH1_RK1: MR19=0x303, MR18=0xF8F3, DQSOSC=413, MR23=63, INC=38, DEC=25
3681 00:40:45.198861 [RxdqsGatingPostProcess] freq 1200
3682 00:40:45.198911 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3683 00:40:45.198962 best DQS0 dly(2T, 0.5T) = (0, 11)
3684 00:40:45.199012 best DQS1 dly(2T, 0.5T) = (0, 11)
3685 00:40:45.199063 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3686 00:40:45.199114 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3687 00:40:45.199165 best DQS0 dly(2T, 0.5T) = (0, 11)
3688 00:40:45.199215 best DQS1 dly(2T, 0.5T) = (0, 11)
3689 00:40:45.199265 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3690 00:40:45.199316 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3691 00:40:45.199366 Pre-setting of DQS Precalculation
3692 00:40:45.199416 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3693 00:40:45.199467 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3694 00:40:45.199518 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3695 00:40:45.199569
3696 00:40:45.199619
3697 00:40:45.199671 [Calibration Summary] 2400 Mbps
3698 00:40:45.199721 CH 0, Rank 0
3699 00:40:45.199772 SW Impedance : PASS
3700 00:40:45.199823 DUTY Scan : NO K
3701 00:40:45.199873 ZQ Calibration : PASS
3702 00:40:45.199923 Jitter Meter : NO K
3703 00:40:45.199974 CBT Training : PASS
3704 00:40:45.200024 Write leveling : PASS
3705 00:40:45.200075 RX DQS gating : PASS
3706 00:40:45.200125 RX DQ/DQS(RDDQC) : PASS
3707 00:40:45.200175 TX DQ/DQS : PASS
3708 00:40:45.200226 RX DATLAT : PASS
3709 00:40:45.200276 RX DQ/DQS(Engine): PASS
3710 00:40:45.200327 TX OE : NO K
3711 00:40:45.200377 All Pass.
3712 00:40:45.200427
3713 00:40:45.200478 CH 0, Rank 1
3714 00:40:45.200528 SW Impedance : PASS
3715 00:40:45.200579 DUTY Scan : NO K
3716 00:40:45.200629 ZQ Calibration : PASS
3717 00:40:45.200679 Jitter Meter : NO K
3718 00:40:45.200730 CBT Training : PASS
3719 00:40:45.200779 Write leveling : PASS
3720 00:40:45.200829 RX DQS gating : PASS
3721 00:40:45.200880 RX DQ/DQS(RDDQC) : PASS
3722 00:40:45.200930 TX DQ/DQS : PASS
3723 00:40:45.200980 RX DATLAT : PASS
3724 00:40:45.201030 RX DQ/DQS(Engine): PASS
3725 00:40:45.201081 TX OE : NO K
3726 00:40:45.201131 All Pass.
3727 00:40:45.201182
3728 00:40:45.201232 CH 1, Rank 0
3729 00:40:45.201283 SW Impedance : PASS
3730 00:40:45.201333 DUTY Scan : NO K
3731 00:40:45.201384 ZQ Calibration : PASS
3732 00:40:45.201434 Jitter Meter : NO K
3733 00:40:45.201485 CBT Training : PASS
3734 00:40:45.201536 Write leveling : PASS
3735 00:40:45.201586 RX DQS gating : PASS
3736 00:40:45.201637 RX DQ/DQS(RDDQC) : PASS
3737 00:40:45.201687 TX DQ/DQS : PASS
3738 00:40:45.201738 RX DATLAT : PASS
3739 00:40:45.201789 RX DQ/DQS(Engine): PASS
3740 00:40:45.201839 TX OE : NO K
3741 00:40:45.201891 All Pass.
3742 00:40:45.201941
3743 00:40:45.201992 CH 1, Rank 1
3744 00:40:45.202042 SW Impedance : PASS
3745 00:40:45.202093 DUTY Scan : NO K
3746 00:40:45.202143 ZQ Calibration : PASS
3747 00:40:45.202225 Jitter Meter : NO K
3748 00:40:45.202290 CBT Training : PASS
3749 00:40:45.202341 Write leveling : PASS
3750 00:40:45.202391 RX DQS gating : PASS
3751 00:40:45.202442 RX DQ/DQS(RDDQC) : PASS
3752 00:40:45.202492 TX DQ/DQS : PASS
3753 00:40:45.202543 RX DATLAT : PASS
3754 00:40:45.202593 RX DQ/DQS(Engine): PASS
3755 00:40:45.202644 TX OE : NO K
3756 00:40:45.202695 All Pass.
3757 00:40:45.202745
3758 00:40:45.202794 DramC Write-DBI off
3759 00:40:45.202844 PER_BANK_REFRESH: Hybrid Mode
3760 00:40:45.202895 TX_TRACKING: ON
3761 00:40:45.202946 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3762 00:40:45.202997 [FAST_K] Save calibration result to emmc
3763 00:40:45.203048 dramc_set_vcore_voltage set vcore to 650000
3764 00:40:45.203099 Read voltage for 600, 5
3765 00:40:45.203149 Vio18 = 0
3766 00:40:45.203200 Vcore = 650000
3767 00:40:45.203250 Vdram = 0
3768 00:40:45.203300 Vddq = 0
3769 00:40:45.203350 Vmddr = 0
3770 00:40:45.203401 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3771 00:40:45.203452 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3772 00:40:45.203503 MEM_TYPE=3, freq_sel=19
3773 00:40:45.203554 sv_algorithm_assistance_LP4_1600
3774 00:40:45.203604 ============ PULL DRAM RESETB DOWN ============
3775 00:40:45.203656 ========== PULL DRAM RESETB DOWN end =========
3776 00:40:45.203707 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3777 00:40:45.203758 ===================================
3778 00:40:45.203816 LPDDR4 DRAM CONFIGURATION
3779 00:40:45.203869 ===================================
3780 00:40:45.203920 EX_ROW_EN[0] = 0x0
3781 00:40:45.203970 EX_ROW_EN[1] = 0x0
3782 00:40:45.204021 LP4Y_EN = 0x0
3783 00:40:45.204073 WORK_FSP = 0x0
3784 00:40:45.204122 WL = 0x2
3785 00:40:45.204172 RL = 0x2
3786 00:40:45.204222 BL = 0x2
3787 00:40:45.204273 RPST = 0x0
3788 00:40:45.204322 RD_PRE = 0x0
3789 00:40:45.204373 WR_PRE = 0x1
3790 00:40:45.204423 WR_PST = 0x0
3791 00:40:45.204473 DBI_WR = 0x0
3792 00:40:45.204523 DBI_RD = 0x0
3793 00:40:45.204573 OTF = 0x1
3794 00:40:45.204813 ===================================
3795 00:40:45.204870 ===================================
3796 00:40:45.204922 ANA top config
3797 00:40:45.204973 ===================================
3798 00:40:45.205025 DLL_ASYNC_EN = 0
3799 00:40:45.205075 ALL_SLAVE_EN = 1
3800 00:40:45.205126 NEW_RANK_MODE = 1
3801 00:40:45.205177 DLL_IDLE_MODE = 1
3802 00:40:45.205227 LP45_APHY_COMB_EN = 1
3803 00:40:45.205277 TX_ODT_DIS = 1
3804 00:40:45.205328 NEW_8X_MODE = 1
3805 00:40:45.205378 ===================================
3806 00:40:45.205429 ===================================
3807 00:40:45.205481 data_rate = 1200
3808 00:40:45.205531 CKR = 1
3809 00:40:45.205582 DQ_P2S_RATIO = 8
3810 00:40:45.205632 ===================================
3811 00:40:45.205682 CA_P2S_RATIO = 8
3812 00:40:45.205733 DQ_CA_OPEN = 0
3813 00:40:45.205783 DQ_SEMI_OPEN = 0
3814 00:40:45.205834 CA_SEMI_OPEN = 0
3815 00:40:45.205884 CA_FULL_RATE = 0
3816 00:40:45.205935 DQ_CKDIV4_EN = 1
3817 00:40:45.205985 CA_CKDIV4_EN = 1
3818 00:40:45.206034 CA_PREDIV_EN = 0
3819 00:40:45.206085 PH8_DLY = 0
3820 00:40:45.206155 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3821 00:40:45.206250 DQ_AAMCK_DIV = 4
3822 00:40:45.206301 CA_AAMCK_DIV = 4
3823 00:40:45.206353 CA_ADMCK_DIV = 4
3824 00:40:45.206403 DQ_TRACK_CA_EN = 0
3825 00:40:45.206453 CA_PICK = 600
3826 00:40:45.206503 CA_MCKIO = 600
3827 00:40:45.206554 MCKIO_SEMI = 0
3828 00:40:45.206605 PLL_FREQ = 2288
3829 00:40:45.206656 DQ_UI_PI_RATIO = 32
3830 00:40:45.206706 CA_UI_PI_RATIO = 0
3831 00:40:45.206757 ===================================
3832 00:40:45.206808 ===================================
3833 00:40:45.206859 memory_type:LPDDR4
3834 00:40:45.206909 GP_NUM : 10
3835 00:40:45.206959 SRAM_EN : 1
3836 00:40:45.207009 MD32_EN : 0
3837 00:40:45.207060 ===================================
3838 00:40:45.207111 [ANA_INIT] >>>>>>>>>>>>>>
3839 00:40:45.207161 <<<<<< [CONFIGURE PHASE]: ANA_TX
3840 00:40:45.207212 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3841 00:40:45.207275 ===================================
3842 00:40:45.210255 data_rate = 1200,PCW = 0X5800
3843 00:40:45.213672 ===================================
3844 00:40:45.216956 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3845 00:40:45.223330 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3846 00:40:45.229762 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3847 00:40:45.233653 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3848 00:40:45.236323 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3849 00:40:45.239908 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3850 00:40:45.243039 [ANA_INIT] flow start
3851 00:40:45.243119 [ANA_INIT] PLL >>>>>>>>
3852 00:40:45.246857 [ANA_INIT] PLL <<<<<<<<
3853 00:40:45.249595 [ANA_INIT] MIDPI >>>>>>>>
3854 00:40:45.253191 [ANA_INIT] MIDPI <<<<<<<<
3855 00:40:45.253270 [ANA_INIT] DLL >>>>>>>>
3856 00:40:45.256704 [ANA_INIT] flow end
3857 00:40:45.259812 ============ LP4 DIFF to SE enter ============
3858 00:40:45.263239 ============ LP4 DIFF to SE exit ============
3859 00:40:45.266284 [ANA_INIT] <<<<<<<<<<<<<
3860 00:40:45.269827 [Flow] Enable top DCM control >>>>>
3861 00:40:45.273197 [Flow] Enable top DCM control <<<<<
3862 00:40:45.275958 Enable DLL master slave shuffle
3863 00:40:45.282537 ==============================================================
3864 00:40:45.282622 Gating Mode config
3865 00:40:45.289496 ==============================================================
3866 00:40:45.289577 Config description:
3867 00:40:45.299260 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3868 00:40:45.305925 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3869 00:40:45.312454 SELPH_MODE 0: By rank 1: By Phase
3870 00:40:45.315648 ==============================================================
3871 00:40:45.318953 GAT_TRACK_EN = 1
3872 00:40:45.322478 RX_GATING_MODE = 2
3873 00:40:45.325470 RX_GATING_TRACK_MODE = 2
3874 00:40:45.328996 SELPH_MODE = 1
3875 00:40:45.332127 PICG_EARLY_EN = 1
3876 00:40:45.335905 VALID_LAT_VALUE = 1
3877 00:40:45.342092 ==============================================================
3878 00:40:45.345495 Enter into Gating configuration >>>>
3879 00:40:45.348921 Exit from Gating configuration <<<<
3880 00:40:45.352293 Enter into DVFS_PRE_config >>>>>
3881 00:40:45.361902 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3882 00:40:45.365104 Exit from DVFS_PRE_config <<<<<
3883 00:40:45.368583 Enter into PICG configuration >>>>
3884 00:40:45.371964 Exit from PICG configuration <<<<
3885 00:40:45.375515 [RX_INPUT] configuration >>>>>
3886 00:40:45.375597 [RX_INPUT] configuration <<<<<
3887 00:40:45.381900 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3888 00:40:45.388223 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3889 00:40:45.395039 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3890 00:40:45.398498 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3891 00:40:45.405170 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3892 00:40:45.411542 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3893 00:40:45.414753 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3894 00:40:45.418083 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3895 00:40:45.424710 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3896 00:40:45.428033 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3897 00:40:45.431326 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3898 00:40:45.438092 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3899 00:40:45.441154 ===================================
3900 00:40:45.441242 LPDDR4 DRAM CONFIGURATION
3901 00:40:45.444577 ===================================
3902 00:40:45.447635 EX_ROW_EN[0] = 0x0
3903 00:40:45.450873 EX_ROW_EN[1] = 0x0
3904 00:40:45.450953 LP4Y_EN = 0x0
3905 00:40:45.454142 WORK_FSP = 0x0
3906 00:40:45.454264 WL = 0x2
3907 00:40:45.457760 RL = 0x2
3908 00:40:45.457844 BL = 0x2
3909 00:40:45.460945 RPST = 0x0
3910 00:40:45.461026 RD_PRE = 0x0
3911 00:40:45.463974 WR_PRE = 0x1
3912 00:40:45.464055 WR_PST = 0x0
3913 00:40:45.467594 DBI_WR = 0x0
3914 00:40:45.467676 DBI_RD = 0x0
3915 00:40:45.471195 OTF = 0x1
3916 00:40:45.473797 ===================================
3917 00:40:45.477345 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3918 00:40:45.480864 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3919 00:40:45.487308 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3920 00:40:45.490299 ===================================
3921 00:40:45.490386 LPDDR4 DRAM CONFIGURATION
3922 00:40:45.493730 ===================================
3923 00:40:45.497187 EX_ROW_EN[0] = 0x10
3924 00:40:45.500639 EX_ROW_EN[1] = 0x0
3925 00:40:45.500722 LP4Y_EN = 0x0
3926 00:40:45.503596 WORK_FSP = 0x0
3927 00:40:45.503677 WL = 0x2
3928 00:40:45.507116 RL = 0x2
3929 00:40:45.507198 BL = 0x2
3930 00:40:45.510350 RPST = 0x0
3931 00:40:45.510431 RD_PRE = 0x0
3932 00:40:45.513426 WR_PRE = 0x1
3933 00:40:45.513507 WR_PST = 0x0
3934 00:40:45.516953 DBI_WR = 0x0
3935 00:40:45.517075 DBI_RD = 0x0
3936 00:40:45.520075 OTF = 0x1
3937 00:40:45.523568 ===================================
3938 00:40:45.529858 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3939 00:40:45.533433 nWR fixed to 30
3940 00:40:45.536549 [ModeRegInit_LP4] CH0 RK0
3941 00:40:45.536632 [ModeRegInit_LP4] CH0 RK1
3942 00:40:45.540092 [ModeRegInit_LP4] CH1 RK0
3943 00:40:45.543583 [ModeRegInit_LP4] CH1 RK1
3944 00:40:45.543664 match AC timing 17
3945 00:40:45.550100 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3946 00:40:45.552983 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3947 00:40:45.556782 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3948 00:40:45.563003 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3949 00:40:45.566685 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3950 00:40:45.566863 ==
3951 00:40:45.569751 Dram Type= 6, Freq= 0, CH_0, rank 0
3952 00:40:45.573603 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3953 00:40:45.573690 ==
3954 00:40:45.579790 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3955 00:40:45.586577 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3956 00:40:45.589427 [CA 0] Center 36 (6~66) winsize 61
3957 00:40:45.593246 [CA 1] Center 36 (6~66) winsize 61
3958 00:40:45.596249 [CA 2] Center 34 (4~65) winsize 62
3959 00:40:45.599535 [CA 3] Center 34 (4~65) winsize 62
3960 00:40:45.602520 [CA 4] Center 33 (3~64) winsize 62
3961 00:40:45.606311 [CA 5] Center 33 (3~64) winsize 62
3962 00:40:45.606392
3963 00:40:45.609299 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3964 00:40:45.609379
3965 00:40:45.612573 [CATrainingPosCal] consider 1 rank data
3966 00:40:45.616037 u2DelayCellTimex100 = 270/100 ps
3967 00:40:45.619300 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3968 00:40:45.622473 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3969 00:40:45.625665 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3970 00:40:45.628941 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3971 00:40:45.635844 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3972 00:40:45.639193 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3973 00:40:45.639279
3974 00:40:45.642354 CA PerBit enable=1, Macro0, CA PI delay=33
3975 00:40:45.642435
3976 00:40:45.645627 [CBTSetCACLKResult] CA Dly = 33
3977 00:40:45.645707 CS Dly: 4 (0~35)
3978 00:40:45.645771 ==
3979 00:40:45.648825 Dram Type= 6, Freq= 0, CH_0, rank 1
3980 00:40:45.655531 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3981 00:40:45.655620 ==
3982 00:40:45.658574 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3983 00:40:45.665284 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3984 00:40:45.668599 [CA 0] Center 35 (5~66) winsize 62
3985 00:40:45.672039 [CA 1] Center 36 (6~66) winsize 61
3986 00:40:45.675009 [CA 2] Center 33 (3~64) winsize 62
3987 00:40:45.678094 [CA 3] Center 33 (3~64) winsize 62
3988 00:40:45.681581 [CA 4] Center 33 (3~64) winsize 62
3989 00:40:45.684725 [CA 5] Center 33 (3~64) winsize 62
3990 00:40:45.684808
3991 00:40:45.688441 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3992 00:40:45.688527
3993 00:40:45.691558 [CATrainingPosCal] consider 2 rank data
3994 00:40:45.694895 u2DelayCellTimex100 = 270/100 ps
3995 00:40:45.698449 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3996 00:40:45.704592 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3997 00:40:45.708209 CA2 delay=34 (4~64),Diff = 1 PI (9 cell)
3998 00:40:45.711359 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
3999 00:40:45.715030 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4000 00:40:45.718044 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4001 00:40:45.718126
4002 00:40:45.721121 CA PerBit enable=1, Macro0, CA PI delay=33
4003 00:40:45.721234
4004 00:40:45.724419 [CBTSetCACLKResult] CA Dly = 33
4005 00:40:45.727832 CS Dly: 4 (0~36)
4006 00:40:45.727917
4007 00:40:45.730960 ----->DramcWriteLeveling(PI) begin...
4008 00:40:45.731081 ==
4009 00:40:45.734086 Dram Type= 6, Freq= 0, CH_0, rank 0
4010 00:40:45.737505 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4011 00:40:45.737591 ==
4012 00:40:45.740809 Write leveling (Byte 0): 34 => 34
4013 00:40:45.744226 Write leveling (Byte 1): 30 => 30
4014 00:40:45.747456 DramcWriteLeveling(PI) end<-----
4015 00:40:45.747543
4016 00:40:45.747609 ==
4017 00:40:45.750549 Dram Type= 6, Freq= 0, CH_0, rank 0
4018 00:40:45.753909 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4019 00:40:45.753992 ==
4020 00:40:45.757440 [Gating] SW mode calibration
4021 00:40:45.764033 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4022 00:40:45.770414 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4023 00:40:45.774092 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4024 00:40:45.777255 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4025 00:40:45.783545 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4026 00:40:45.787138 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4027 00:40:45.790439 0 9 16 | B1->B0 | 2f2f 2525 | 1 0 | (1 0) (0 0)
4028 00:40:45.796916 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4029 00:40:45.800292 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4030 00:40:45.803856 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4031 00:40:45.810699 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4032 00:40:45.813694 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4033 00:40:45.817003 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4034 00:40:45.823733 0 10 12 | B1->B0 | 2424 3030 | 0 0 | (0 0) (0 0)
4035 00:40:45.826769 0 10 16 | B1->B0 | 3636 4343 | 1 0 | (0 0) (0 0)
4036 00:40:45.830492 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4037 00:40:45.836865 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4038 00:40:45.840137 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4039 00:40:45.843145 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4040 00:40:45.849729 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4041 00:40:45.853303 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4042 00:40:45.856514 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4043 00:40:45.863001 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4044 00:40:45.866353 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4045 00:40:45.869824 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4046 00:40:45.876150 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4047 00:40:45.879355 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4048 00:40:45.882689 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4049 00:40:45.889809 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4050 00:40:45.892707 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4051 00:40:45.895805 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4052 00:40:45.902696 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4053 00:40:45.906008 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4054 00:40:45.909103 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4055 00:40:45.915720 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4056 00:40:45.918804 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4057 00:40:45.922319 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4058 00:40:45.929617 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4059 00:40:45.932289 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4060 00:40:45.935478 Total UI for P1: 0, mck2ui 16
4061 00:40:45.938804 best dqsien dly found for B0: ( 0, 13, 14)
4062 00:40:45.942288 Total UI for P1: 0, mck2ui 16
4063 00:40:45.945303 best dqsien dly found for B1: ( 0, 13, 14)
4064 00:40:45.948648 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4065 00:40:45.951734 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4066 00:40:45.951815
4067 00:40:45.955399 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4068 00:40:45.961814 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4069 00:40:45.961903 [Gating] SW calibration Done
4070 00:40:45.961967 ==
4071 00:40:45.965058 Dram Type= 6, Freq= 0, CH_0, rank 0
4072 00:40:45.971684 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4073 00:40:45.971768 ==
4074 00:40:45.971831 RX Vref Scan: 0
4075 00:40:45.971890
4076 00:40:45.975360 RX Vref 0 -> 0, step: 1
4077 00:40:45.975441
4078 00:40:45.978336 RX Delay -230 -> 252, step: 16
4079 00:40:45.981612 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4080 00:40:45.985167 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4081 00:40:45.991566 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4082 00:40:45.994785 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4083 00:40:45.998045 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
4084 00:40:46.001226 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4085 00:40:46.004487 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4086 00:40:46.011407 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4087 00:40:46.014562 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4088 00:40:46.017751 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4089 00:40:46.020945 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4090 00:40:46.027777 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4091 00:40:46.031119 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4092 00:40:46.034334 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4093 00:40:46.037522 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4094 00:40:46.044090 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4095 00:40:46.044180 ==
4096 00:40:46.047777 Dram Type= 6, Freq= 0, CH_0, rank 0
4097 00:40:46.051184 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4098 00:40:46.051269 ==
4099 00:40:46.051333 DQS Delay:
4100 00:40:46.054065 DQS0 = 0, DQS1 = 0
4101 00:40:46.054145 DQM Delay:
4102 00:40:46.057372 DQM0 = 42, DQM1 = 30
4103 00:40:46.057455 DQ Delay:
4104 00:40:46.060968 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =41
4105 00:40:46.063974 DQ4 =49, DQ5 =33, DQ6 =49, DQ7 =49
4106 00:40:46.067598 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4107 00:40:46.070424 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =33
4108 00:40:46.070506
4109 00:40:46.070569
4110 00:40:46.070627 ==
4111 00:40:46.073802 Dram Type= 6, Freq= 0, CH_0, rank 0
4112 00:40:46.077052 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4113 00:40:46.080452 ==
4114 00:40:46.080531
4115 00:40:46.080593
4116 00:40:46.080651 TX Vref Scan disable
4117 00:40:46.083985 == TX Byte 0 ==
4118 00:40:46.087272 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4119 00:40:46.093501 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4120 00:40:46.093601 == TX Byte 1 ==
4121 00:40:46.097257 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4122 00:40:46.103773 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4123 00:40:46.103855 ==
4124 00:40:46.107137 Dram Type= 6, Freq= 0, CH_0, rank 0
4125 00:40:46.110334 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4126 00:40:46.110414 ==
4127 00:40:46.110478
4128 00:40:46.110536
4129 00:40:46.113432 TX Vref Scan disable
4130 00:40:46.117059 == TX Byte 0 ==
4131 00:40:46.120249 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4132 00:40:46.123549 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4133 00:40:46.126920 == TX Byte 1 ==
4134 00:40:46.130011 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4135 00:40:46.133210 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4136 00:40:46.133292
4137 00:40:46.133355 [DATLAT]
4138 00:40:46.137013 Freq=600, CH0 RK0
4139 00:40:46.137094
4140 00:40:46.139841 DATLAT Default: 0x9
4141 00:40:46.139920 0, 0xFFFF, sum = 0
4142 00:40:46.143198 1, 0xFFFF, sum = 0
4143 00:40:46.143280 2, 0xFFFF, sum = 0
4144 00:40:46.146482 3, 0xFFFF, sum = 0
4145 00:40:46.146563 4, 0xFFFF, sum = 0
4146 00:40:46.149522 5, 0xFFFF, sum = 0
4147 00:40:46.149606 6, 0xFFFF, sum = 0
4148 00:40:46.153285 7, 0xFFFF, sum = 0
4149 00:40:46.153366 8, 0x0, sum = 1
4150 00:40:46.156482 9, 0x0, sum = 2
4151 00:40:46.156569 10, 0x0, sum = 3
4152 00:40:46.159839 11, 0x0, sum = 4
4153 00:40:46.159920 best_step = 9
4154 00:40:46.159983
4155 00:40:46.160041 ==
4156 00:40:46.163033 Dram Type= 6, Freq= 0, CH_0, rank 0
4157 00:40:46.166445 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4158 00:40:46.166531 ==
4159 00:40:46.169760 RX Vref Scan: 1
4160 00:40:46.169838
4161 00:40:46.172856 RX Vref 0 -> 0, step: 1
4162 00:40:46.172934
4163 00:40:46.172997 RX Delay -195 -> 252, step: 8
4164 00:40:46.173056
4165 00:40:46.176610 Set Vref, RX VrefLevel [Byte0]: 60
4166 00:40:46.179361 [Byte1]: 49
4167 00:40:46.184601
4168 00:40:46.184680 Final RX Vref Byte 0 = 60 to rank0
4169 00:40:46.187811 Final RX Vref Byte 1 = 49 to rank0
4170 00:40:46.190897 Final RX Vref Byte 0 = 60 to rank1
4171 00:40:46.194032 Final RX Vref Byte 1 = 49 to rank1==
4172 00:40:46.197645 Dram Type= 6, Freq= 0, CH_0, rank 0
4173 00:40:46.204378 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4174 00:40:46.204460 ==
4175 00:40:46.204522 DQS Delay:
4176 00:40:46.207283 DQS0 = 0, DQS1 = 0
4177 00:40:46.207363 DQM Delay:
4178 00:40:46.207426 DQM0 = 44, DQM1 = 32
4179 00:40:46.210602 DQ Delay:
4180 00:40:46.213719 DQ0 =44, DQ1 =44, DQ2 =40, DQ3 =40
4181 00:40:46.217381 DQ4 =44, DQ5 =36, DQ6 =52, DQ7 =52
4182 00:40:46.220679 DQ8 =24, DQ9 =20, DQ10 =32, DQ11 =24
4183 00:40:46.223698 DQ12 =36, DQ13 =36, DQ14 =44, DQ15 =40
4184 00:40:46.223788
4185 00:40:46.223852
4186 00:40:46.230628 [DQSOSCAuto] RK0, (LSB)MR18= 0x653c, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 390 ps
4187 00:40:46.233865 CH0 RK0: MR19=808, MR18=653C
4188 00:40:46.240504 CH0_RK0: MR19=0x808, MR18=0x653C, DQSOSC=390, MR23=63, INC=172, DEC=114
4189 00:40:46.240599
4190 00:40:46.243438 ----->DramcWriteLeveling(PI) begin...
4191 00:40:46.243522 ==
4192 00:40:46.246904 Dram Type= 6, Freq= 0, CH_0, rank 1
4193 00:40:46.250087 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4194 00:40:46.250195 ==
4195 00:40:46.253474 Write leveling (Byte 0): 31 => 31
4196 00:40:46.256553 Write leveling (Byte 1): 31 => 31
4197 00:40:46.259873 DramcWriteLeveling(PI) end<-----
4198 00:40:46.259953
4199 00:40:46.260017 ==
4200 00:40:46.263566 Dram Type= 6, Freq= 0, CH_0, rank 1
4201 00:40:46.269790 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4202 00:40:46.269876 ==
4203 00:40:46.269940 [Gating] SW mode calibration
4204 00:40:46.279847 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4205 00:40:46.283248 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4206 00:40:46.286445 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4207 00:40:46.292988 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4208 00:40:46.296234 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4209 00:40:46.299711 0 9 12 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 0)
4210 00:40:46.306666 0 9 16 | B1->B0 | 2d2d 2626 | 0 0 | (0 1) (0 0)
4211 00:40:46.309435 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4212 00:40:46.312637 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4213 00:40:46.319348 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4214 00:40:46.322718 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4215 00:40:46.326047 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4216 00:40:46.332650 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4217 00:40:46.336162 0 10 12 | B1->B0 | 2a2a 2626 | 0 0 | (0 0) (0 0)
4218 00:40:46.339177 0 10 16 | B1->B0 | 3939 4242 | 1 0 | (0 0) (0 0)
4219 00:40:46.345773 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4220 00:40:46.349039 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4221 00:40:46.352233 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4222 00:40:46.359100 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4223 00:40:46.362040 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4224 00:40:46.365406 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4225 00:40:46.372382 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4226 00:40:46.375214 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4227 00:40:46.378860 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4228 00:40:46.385124 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4229 00:40:46.388920 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4230 00:40:46.391856 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4231 00:40:46.398167 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4232 00:40:46.401848 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4233 00:40:46.405654 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4234 00:40:46.411756 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4235 00:40:46.414674 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4236 00:40:46.421655 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4237 00:40:46.424867 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4238 00:40:46.427832 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4239 00:40:46.434480 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4240 00:40:46.437945 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4241 00:40:46.441648 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4242 00:40:46.447677 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4243 00:40:46.447767 Total UI for P1: 0, mck2ui 16
4244 00:40:46.454083 best dqsien dly found for B0: ( 0, 13, 14)
4245 00:40:46.454221 Total UI for P1: 0, mck2ui 16
4246 00:40:46.457312 best dqsien dly found for B1: ( 0, 13, 12)
4247 00:40:46.464254 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4248 00:40:46.467141 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4249 00:40:46.467228
4250 00:40:46.470914 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4251 00:40:46.473887 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4252 00:40:46.477087 [Gating] SW calibration Done
4253 00:40:46.477203 ==
4254 00:40:46.480741 Dram Type= 6, Freq= 0, CH_0, rank 1
4255 00:40:46.483591 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4256 00:40:46.483675 ==
4257 00:40:46.487212 RX Vref Scan: 0
4258 00:40:46.487294
4259 00:40:46.487360 RX Vref 0 -> 0, step: 1
4260 00:40:46.490116
4261 00:40:46.490205 RX Delay -230 -> 252, step: 16
4262 00:40:46.497010 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4263 00:40:46.500042 iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336
4264 00:40:46.503166 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4265 00:40:46.506903 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4266 00:40:46.513629 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4267 00:40:46.516385 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4268 00:40:46.519628 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4269 00:40:46.522970 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4270 00:40:46.526611 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4271 00:40:46.533088 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4272 00:40:46.536098 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4273 00:40:46.539724 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4274 00:40:46.543196 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4275 00:40:46.549372 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4276 00:40:46.552516 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4277 00:40:46.555992 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4278 00:40:46.556081 ==
4279 00:40:46.559254 Dram Type= 6, Freq= 0, CH_0, rank 1
4280 00:40:46.566024 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4281 00:40:46.566117 ==
4282 00:40:46.566210 DQS Delay:
4283 00:40:46.568812 DQS0 = 0, DQS1 = 0
4284 00:40:46.568895 DQM Delay:
4285 00:40:46.568960 DQM0 = 43, DQM1 = 35
4286 00:40:46.572611 DQ Delay:
4287 00:40:46.575595 DQ0 =41, DQ1 =49, DQ2 =41, DQ3 =41
4288 00:40:46.578774 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4289 00:40:46.582054 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =25
4290 00:40:46.585572 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =41
4291 00:40:46.585657
4292 00:40:46.585721
4293 00:40:46.585780 ==
4294 00:40:46.588644 Dram Type= 6, Freq= 0, CH_0, rank 1
4295 00:40:46.592369 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4296 00:40:46.592469 ==
4297 00:40:46.592535
4298 00:40:46.592595
4299 00:40:46.595247 TX Vref Scan disable
4300 00:40:46.598906 == TX Byte 0 ==
4301 00:40:46.602191 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4302 00:40:46.605760 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4303 00:40:46.608665 == TX Byte 1 ==
4304 00:40:46.612233 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4305 00:40:46.615236 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4306 00:40:46.615319 ==
4307 00:40:46.618368 Dram Type= 6, Freq= 0, CH_0, rank 1
4308 00:40:46.622059 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4309 00:40:46.625429 ==
4310 00:40:46.625511
4311 00:40:46.625575
4312 00:40:46.625634 TX Vref Scan disable
4313 00:40:46.629006 == TX Byte 0 ==
4314 00:40:46.632096 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4315 00:40:46.638909 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4316 00:40:46.638995 == TX Byte 1 ==
4317 00:40:46.642148 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4318 00:40:46.648654 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4319 00:40:46.648755
4320 00:40:46.648820 [DATLAT]
4321 00:40:46.648880 Freq=600, CH0 RK1
4322 00:40:46.648938
4323 00:40:46.651868 DATLAT Default: 0x9
4324 00:40:46.655654 0, 0xFFFF, sum = 0
4325 00:40:46.655740 1, 0xFFFF, sum = 0
4326 00:40:46.658518 2, 0xFFFF, sum = 0
4327 00:40:46.658600 3, 0xFFFF, sum = 0
4328 00:40:46.662138 4, 0xFFFF, sum = 0
4329 00:40:46.662251 5, 0xFFFF, sum = 0
4330 00:40:46.665237 6, 0xFFFF, sum = 0
4331 00:40:46.665320 7, 0xFFFF, sum = 0
4332 00:40:46.668438 8, 0x0, sum = 1
4333 00:40:46.668534 9, 0x0, sum = 2
4334 00:40:46.671861 10, 0x0, sum = 3
4335 00:40:46.671943 11, 0x0, sum = 4
4336 00:40:46.672008 best_step = 9
4337 00:40:46.672066
4338 00:40:46.674992 ==
4339 00:40:46.678326 Dram Type= 6, Freq= 0, CH_0, rank 1
4340 00:40:46.681980 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4341 00:40:46.682065 ==
4342 00:40:46.682128 RX Vref Scan: 0
4343 00:40:46.682229
4344 00:40:46.684911 RX Vref 0 -> 0, step: 1
4345 00:40:46.684990
4346 00:40:46.688028 RX Delay -179 -> 252, step: 8
4347 00:40:46.694894 iDelay=205, Bit 0, Center 40 (-107 ~ 188) 296
4348 00:40:46.698036 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4349 00:40:46.701463 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4350 00:40:46.704501 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4351 00:40:46.711252 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4352 00:40:46.714828 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4353 00:40:46.717853 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4354 00:40:46.721276 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4355 00:40:46.724621 iDelay=205, Bit 8, Center 28 (-123 ~ 180) 304
4356 00:40:46.731314 iDelay=205, Bit 9, Center 20 (-131 ~ 172) 304
4357 00:40:46.734290 iDelay=205, Bit 10, Center 36 (-115 ~ 188) 304
4358 00:40:46.738107 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4359 00:40:46.741070 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4360 00:40:46.747526 iDelay=205, Bit 13, Center 44 (-107 ~ 196) 304
4361 00:40:46.750981 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4362 00:40:46.754088 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4363 00:40:46.754198 ==
4364 00:40:46.757650 Dram Type= 6, Freq= 0, CH_0, rank 1
4365 00:40:46.761080 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4366 00:40:46.763909 ==
4367 00:40:46.763988 DQS Delay:
4368 00:40:46.764051 DQS0 = 0, DQS1 = 0
4369 00:40:46.767157 DQM Delay:
4370 00:40:46.767238 DQM0 = 41, DQM1 = 36
4371 00:40:46.770518 DQ Delay:
4372 00:40:46.773814 DQ0 =40, DQ1 =44, DQ2 =36, DQ3 =40
4373 00:40:46.773894 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =48
4374 00:40:46.777430 DQ8 =28, DQ9 =20, DQ10 =36, DQ11 =28
4375 00:40:46.783671 DQ12 =44, DQ13 =44, DQ14 =48, DQ15 =44
4376 00:40:46.783757
4377 00:40:46.783821
4378 00:40:46.790764 [DQSOSCAuto] RK1, (LSB)MR18= 0x6618, (MSB)MR19= 0x808, tDQSOscB0 = 405 ps tDQSOscB1 = 390 ps
4379 00:40:46.793467 CH0 RK1: MR19=808, MR18=6618
4380 00:40:46.800492 CH0_RK1: MR19=0x808, MR18=0x6618, DQSOSC=390, MR23=63, INC=172, DEC=114
4381 00:40:46.803351 [RxdqsGatingPostProcess] freq 600
4382 00:40:46.806686 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4383 00:40:46.810207 Pre-setting of DQS Precalculation
4384 00:40:46.816719 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4385 00:40:46.816804 ==
4386 00:40:46.819998 Dram Type= 6, Freq= 0, CH_1, rank 0
4387 00:40:46.823217 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4388 00:40:46.823299 ==
4389 00:40:46.829739 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4390 00:40:46.836371 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4391 00:40:46.839928 [CA 0] Center 35 (5~66) winsize 62
4392 00:40:46.842854 [CA 1] Center 35 (5~66) winsize 62
4393 00:40:46.846453 [CA 2] Center 34 (3~65) winsize 63
4394 00:40:46.849571 [CA 3] Center 33 (3~64) winsize 62
4395 00:40:46.853205 [CA 4] Center 34 (4~64) winsize 61
4396 00:40:46.856034 [CA 5] Center 33 (3~64) winsize 62
4397 00:40:46.856116
4398 00:40:46.859598 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4399 00:40:46.859679
4400 00:40:46.862736 [CATrainingPosCal] consider 1 rank data
4401 00:40:46.866175 u2DelayCellTimex100 = 270/100 ps
4402 00:40:46.869563 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4403 00:40:46.872559 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4404 00:40:46.876161 CA2 delay=34 (3~65),Diff = 1 PI (9 cell)
4405 00:40:46.879375 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4406 00:40:46.883231 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4407 00:40:46.886217 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4408 00:40:46.886298
4409 00:40:46.892734 CA PerBit enable=1, Macro0, CA PI delay=33
4410 00:40:46.892818
4411 00:40:46.892883 [CBTSetCACLKResult] CA Dly = 33
4412 00:40:46.896272 CS Dly: 4 (0~35)
4413 00:40:46.896353 ==
4414 00:40:46.899444 Dram Type= 6, Freq= 0, CH_1, rank 1
4415 00:40:46.902362 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4416 00:40:46.902443 ==
4417 00:40:46.909058 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4418 00:40:46.915853 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4419 00:40:46.918909 [CA 0] Center 35 (5~66) winsize 62
4420 00:40:46.922117 [CA 1] Center 36 (6~66) winsize 61
4421 00:40:46.925597 [CA 2] Center 34 (4~65) winsize 62
4422 00:40:46.928686 [CA 3] Center 34 (3~65) winsize 63
4423 00:40:46.932424 [CA 4] Center 34 (4~65) winsize 62
4424 00:40:46.935526 [CA 5] Center 34 (3~65) winsize 63
4425 00:40:46.935608
4426 00:40:46.938749 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4427 00:40:46.938830
4428 00:40:46.941697 [CATrainingPosCal] consider 2 rank data
4429 00:40:46.945241 u2DelayCellTimex100 = 270/100 ps
4430 00:40:46.948183 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4431 00:40:46.951513 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4432 00:40:46.955385 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4433 00:40:46.961679 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4434 00:40:46.965212 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4435 00:40:46.968639 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4436 00:40:46.968719
4437 00:40:46.971384 CA PerBit enable=1, Macro0, CA PI delay=33
4438 00:40:46.971465
4439 00:40:46.974639 [CBTSetCACLKResult] CA Dly = 33
4440 00:40:46.974720 CS Dly: 5 (0~37)
4441 00:40:46.974784
4442 00:40:46.978025 ----->DramcWriteLeveling(PI) begin...
4443 00:40:46.981148 ==
4444 00:40:46.981229 Dram Type= 6, Freq= 0, CH_1, rank 0
4445 00:40:46.988082 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4446 00:40:46.988165 ==
4447 00:40:46.991168 Write leveling (Byte 0): 30 => 30
4448 00:40:46.994367 Write leveling (Byte 1): 30 => 30
4449 00:40:46.997964 DramcWriteLeveling(PI) end<-----
4450 00:40:46.998044
4451 00:40:46.998108 ==
4452 00:40:47.001287 Dram Type= 6, Freq= 0, CH_1, rank 0
4453 00:40:47.004796 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4454 00:40:47.004877 ==
4455 00:40:47.007909 [Gating] SW mode calibration
4456 00:40:47.014741 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4457 00:40:47.020932 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4458 00:40:47.024038 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4459 00:40:47.027412 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4460 00:40:47.030661 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4461 00:40:47.037539 0 9 12 | B1->B0 | 2f2f 2d2d | 0 1 | (1 0) (1 0)
4462 00:40:47.040892 0 9 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4463 00:40:47.044214 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4464 00:40:47.050980 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4465 00:40:47.053896 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4466 00:40:47.057579 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4467 00:40:47.063891 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4468 00:40:47.067080 0 10 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4469 00:40:47.070699 0 10 12 | B1->B0 | 3636 3b3b | 0 1 | (0 0) (0 0)
4470 00:40:47.077288 0 10 16 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
4471 00:40:47.080570 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4472 00:40:47.084061 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4473 00:40:47.090407 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4474 00:40:47.093516 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4475 00:40:47.096869 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4476 00:40:47.103863 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4477 00:40:47.107161 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4478 00:40:47.110582 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4479 00:40:47.116632 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4480 00:40:47.120169 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4481 00:40:47.123360 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4482 00:40:47.129903 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4483 00:40:47.133513 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4484 00:40:47.136552 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4485 00:40:47.143215 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4486 00:40:47.146313 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4487 00:40:47.149997 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4488 00:40:47.156145 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4489 00:40:47.159793 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4490 00:40:47.162928 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4491 00:40:47.170025 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4492 00:40:47.172741 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4493 00:40:47.176031 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4494 00:40:47.182714 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4495 00:40:47.186325 Total UI for P1: 0, mck2ui 16
4496 00:40:47.189214 best dqsien dly found for B0: ( 0, 13, 12)
4497 00:40:47.192412 Total UI for P1: 0, mck2ui 16
4498 00:40:47.196266 best dqsien dly found for B1: ( 0, 13, 12)
4499 00:40:47.199380 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4500 00:40:47.202455 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4501 00:40:47.202536
4502 00:40:47.205911 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4503 00:40:47.209241 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4504 00:40:47.212784 [Gating] SW calibration Done
4505 00:40:47.212865 ==
4506 00:40:47.215544 Dram Type= 6, Freq= 0, CH_1, rank 0
4507 00:40:47.219229 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4508 00:40:47.219310 ==
4509 00:40:47.222406 RX Vref Scan: 0
4510 00:40:47.222487
4511 00:40:47.225569 RX Vref 0 -> 0, step: 1
4512 00:40:47.225649
4513 00:40:47.225713 RX Delay -230 -> 252, step: 16
4514 00:40:47.232364 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4515 00:40:47.235594 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4516 00:40:47.239345 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4517 00:40:47.242040 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4518 00:40:47.249161 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4519 00:40:47.252418 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4520 00:40:47.255756 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4521 00:40:47.259039 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4522 00:40:47.265263 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4523 00:40:47.268498 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4524 00:40:47.271748 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4525 00:40:47.275301 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4526 00:40:47.281726 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4527 00:40:47.284963 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4528 00:40:47.288591 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4529 00:40:47.292054 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4530 00:40:47.292141 ==
4531 00:40:47.294802 Dram Type= 6, Freq= 0, CH_1, rank 0
4532 00:40:47.301429 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4533 00:40:47.301566 ==
4534 00:40:47.301669 DQS Delay:
4535 00:40:47.305069 DQS0 = 0, DQS1 = 0
4536 00:40:47.305150 DQM Delay:
4537 00:40:47.305216 DQM0 = 47, DQM1 = 39
4538 00:40:47.308361 DQ Delay:
4539 00:40:47.311416 DQ0 =57, DQ1 =41, DQ2 =41, DQ3 =41
4540 00:40:47.314839 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4541 00:40:47.318297 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =25
4542 00:40:47.321368 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4543 00:40:47.321449
4544 00:40:47.321513
4545 00:40:47.321571 ==
4546 00:40:47.324473 Dram Type= 6, Freq= 0, CH_1, rank 0
4547 00:40:47.327743 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4548 00:40:47.327832 ==
4549 00:40:47.327896
4550 00:40:47.327955
4551 00:40:47.331331 TX Vref Scan disable
4552 00:40:47.334320 == TX Byte 0 ==
4553 00:40:47.337672 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4554 00:40:47.341018 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4555 00:40:47.344295 == TX Byte 1 ==
4556 00:40:47.347812 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4557 00:40:47.351256 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4558 00:40:47.351337 ==
4559 00:40:47.354288 Dram Type= 6, Freq= 0, CH_1, rank 0
4560 00:40:47.357546 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4561 00:40:47.360944 ==
4562 00:40:47.361024
4563 00:40:47.361088
4564 00:40:47.361147 TX Vref Scan disable
4565 00:40:47.364805 == TX Byte 0 ==
4566 00:40:47.368158 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4567 00:40:47.374512 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4568 00:40:47.374594 == TX Byte 1 ==
4569 00:40:47.377742 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4570 00:40:47.384993 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4571 00:40:47.385077
4572 00:40:47.385142 [DATLAT]
4573 00:40:47.385203 Freq=600, CH1 RK0
4574 00:40:47.385262
4575 00:40:47.387817 DATLAT Default: 0x9
4576 00:40:47.391337 0, 0xFFFF, sum = 0
4577 00:40:47.391420 1, 0xFFFF, sum = 0
4578 00:40:47.394498 2, 0xFFFF, sum = 0
4579 00:40:47.394580 3, 0xFFFF, sum = 0
4580 00:40:47.398287 4, 0xFFFF, sum = 0
4581 00:40:47.398371 5, 0xFFFF, sum = 0
4582 00:40:47.400892 6, 0xFFFF, sum = 0
4583 00:40:47.400974 7, 0xFFFF, sum = 0
4584 00:40:47.404347 8, 0x0, sum = 1
4585 00:40:47.404429 9, 0x0, sum = 2
4586 00:40:47.407661 10, 0x0, sum = 3
4587 00:40:47.407743 11, 0x0, sum = 4
4588 00:40:47.407830 best_step = 9
4589 00:40:47.407894
4590 00:40:47.411128 ==
4591 00:40:47.414073 Dram Type= 6, Freq= 0, CH_1, rank 0
4592 00:40:47.417254 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4593 00:40:47.417410 ==
4594 00:40:47.417476 RX Vref Scan: 1
4595 00:40:47.417576
4596 00:40:47.420392 RX Vref 0 -> 0, step: 1
4597 00:40:47.420472
4598 00:40:47.423954 RX Delay -179 -> 252, step: 8
4599 00:40:47.424036
4600 00:40:47.427479 Set Vref, RX VrefLevel [Byte0]: 52
4601 00:40:47.430751 [Byte1]: 53
4602 00:40:47.430834
4603 00:40:47.433768 Final RX Vref Byte 0 = 52 to rank0
4604 00:40:47.437191 Final RX Vref Byte 1 = 53 to rank0
4605 00:40:47.440513 Final RX Vref Byte 0 = 52 to rank1
4606 00:40:47.443801 Final RX Vref Byte 1 = 53 to rank1==
4607 00:40:47.447201 Dram Type= 6, Freq= 0, CH_1, rank 0
4608 00:40:47.453433 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4609 00:40:47.453520 ==
4610 00:40:47.453585 DQS Delay:
4611 00:40:47.453646 DQS0 = 0, DQS1 = 0
4612 00:40:47.456936 DQM Delay:
4613 00:40:47.457016 DQM0 = 47, DQM1 = 36
4614 00:40:47.460669 DQ Delay:
4615 00:40:47.463920 DQ0 =56, DQ1 =40, DQ2 =40, DQ3 =44
4616 00:40:47.464001 DQ4 =44, DQ5 =56, DQ6 =56, DQ7 =44
4617 00:40:47.467002 DQ8 =24, DQ9 =24, DQ10 =40, DQ11 =28
4618 00:40:47.473225 DQ12 =44, DQ13 =44, DQ14 =44, DQ15 =44
4619 00:40:47.473312
4620 00:40:47.473376
4621 00:40:47.480012 [DQSOSCAuto] RK0, (LSB)MR18= 0x4f34, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 394 ps
4622 00:40:47.483036 CH1 RK0: MR19=808, MR18=4F34
4623 00:40:47.489727 CH1_RK0: MR19=0x808, MR18=0x4F34, DQSOSC=394, MR23=63, INC=168, DEC=112
4624 00:40:47.489847
4625 00:40:47.492966 ----->DramcWriteLeveling(PI) begin...
4626 00:40:47.493089 ==
4627 00:40:47.496441 Dram Type= 6, Freq= 0, CH_1, rank 1
4628 00:40:47.499917 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4629 00:40:47.500029 ==
4630 00:40:47.503022 Write leveling (Byte 0): 29 => 29
4631 00:40:47.506118 Write leveling (Byte 1): 32 => 32
4632 00:40:47.509617 DramcWriteLeveling(PI) end<-----
4633 00:40:47.509698
4634 00:40:47.509761 ==
4635 00:40:47.513236 Dram Type= 6, Freq= 0, CH_1, rank 1
4636 00:40:47.516245 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4637 00:40:47.519528 ==
4638 00:40:47.519609 [Gating] SW mode calibration
4639 00:40:47.526134 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4640 00:40:47.532806 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4641 00:40:47.536101 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4642 00:40:47.542380 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4643 00:40:47.545993 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4644 00:40:47.549195 0 9 12 | B1->B0 | 2f2f 3333 | 0 0 | (0 0) (0 1)
4645 00:40:47.555534 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4646 00:40:47.559064 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4647 00:40:47.562135 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4648 00:40:47.568782 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4649 00:40:47.572349 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4650 00:40:47.575525 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4651 00:40:47.582314 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4652 00:40:47.585417 0 10 12 | B1->B0 | 3131 2828 | 0 0 | (0 0) (0 0)
4653 00:40:47.588862 0 10 16 | B1->B0 | 4545 4040 | 0 0 | (0 0) (0 0)
4654 00:40:47.595322 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4655 00:40:47.598664 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4656 00:40:47.602087 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4657 00:40:47.608713 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4658 00:40:47.611698 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4659 00:40:47.615281 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4660 00:40:47.621463 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4661 00:40:47.624975 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4662 00:40:47.628144 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4663 00:40:47.635056 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4664 00:40:47.638343 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4665 00:40:47.641581 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4666 00:40:47.648524 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4667 00:40:47.651535 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4668 00:40:47.655032 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4669 00:40:47.661187 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4670 00:40:47.664688 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4671 00:40:47.668183 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4672 00:40:47.674884 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4673 00:40:47.678017 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4674 00:40:47.681181 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4675 00:40:47.688116 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4676 00:40:47.691154 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4677 00:40:47.694682 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4678 00:40:47.697631 Total UI for P1: 0, mck2ui 16
4679 00:40:47.701052 best dqsien dly found for B0: ( 0, 13, 14)
4680 00:40:47.704320 Total UI for P1: 0, mck2ui 16
4681 00:40:47.707612 best dqsien dly found for B1: ( 0, 13, 14)
4682 00:40:47.711297 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4683 00:40:47.714166 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4684 00:40:47.714284
4685 00:40:47.720687 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4686 00:40:47.724117 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4687 00:40:47.727486 [Gating] SW calibration Done
4688 00:40:47.727569 ==
4689 00:40:47.730834 Dram Type= 6, Freq= 0, CH_1, rank 1
4690 00:40:47.734180 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4691 00:40:47.734301 ==
4692 00:40:47.734391 RX Vref Scan: 0
4693 00:40:47.734479
4694 00:40:47.737430 RX Vref 0 -> 0, step: 1
4695 00:40:47.737509
4696 00:40:47.740461 RX Delay -230 -> 252, step: 16
4697 00:40:47.744305 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4698 00:40:47.750526 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4699 00:40:47.753537 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4700 00:40:47.757304 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4701 00:40:47.760345 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4702 00:40:47.763801 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4703 00:40:47.770020 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4704 00:40:47.773494 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4705 00:40:47.776979 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4706 00:40:47.780179 iDelay=218, Bit 9, Center 25 (-150 ~ 201) 352
4707 00:40:47.786857 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4708 00:40:47.790513 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4709 00:40:47.793604 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4710 00:40:47.796872 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4711 00:40:47.803334 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4712 00:40:47.806815 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4713 00:40:47.806896 ==
4714 00:40:47.809682 Dram Type= 6, Freq= 0, CH_1, rank 1
4715 00:40:47.813212 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4716 00:40:47.813317 ==
4717 00:40:47.816541 DQS Delay:
4718 00:40:47.816615 DQS0 = 0, DQS1 = 0
4719 00:40:47.816677 DQM Delay:
4720 00:40:47.819935 DQM0 = 43, DQM1 = 37
4721 00:40:47.820015 DQ Delay:
4722 00:40:47.823472 DQ0 =49, DQ1 =41, DQ2 =25, DQ3 =41
4723 00:40:47.826587 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =33
4724 00:40:47.829525 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4725 00:40:47.833018 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4726 00:40:47.833108
4727 00:40:47.833174
4728 00:40:47.833234 ==
4729 00:40:47.836295 Dram Type= 6, Freq= 0, CH_1, rank 1
4730 00:40:47.842941 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4731 00:40:47.843023 ==
4732 00:40:47.843088
4733 00:40:47.843148
4734 00:40:47.843205 TX Vref Scan disable
4735 00:40:47.846736 == TX Byte 0 ==
4736 00:40:47.849817 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4737 00:40:47.856693 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4738 00:40:47.856778 == TX Byte 1 ==
4739 00:40:47.859903 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4740 00:40:47.866870 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4741 00:40:47.866952 ==
4742 00:40:47.870081 Dram Type= 6, Freq= 0, CH_1, rank 1
4743 00:40:47.873090 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4744 00:40:47.873170 ==
4745 00:40:47.873233
4746 00:40:47.873291
4747 00:40:47.876698 TX Vref Scan disable
4748 00:40:47.879837 == TX Byte 0 ==
4749 00:40:47.882935 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4750 00:40:47.885904 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4751 00:40:47.889492 == TX Byte 1 ==
4752 00:40:47.892875 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4753 00:40:47.896155 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4754 00:40:47.896232
4755 00:40:47.896360 [DATLAT]
4756 00:40:47.899394 Freq=600, CH1 RK1
4757 00:40:47.899463
4758 00:40:47.902909 DATLAT Default: 0x9
4759 00:40:47.902992 0, 0xFFFF, sum = 0
4760 00:40:47.906285 1, 0xFFFF, sum = 0
4761 00:40:47.906357 2, 0xFFFF, sum = 0
4762 00:40:47.909361 3, 0xFFFF, sum = 0
4763 00:40:47.909444 4, 0xFFFF, sum = 0
4764 00:40:47.912702 5, 0xFFFF, sum = 0
4765 00:40:47.912785 6, 0xFFFF, sum = 0
4766 00:40:47.915968 7, 0xFFFF, sum = 0
4767 00:40:47.916052 8, 0x0, sum = 1
4768 00:40:47.919152 9, 0x0, sum = 2
4769 00:40:47.919235 10, 0x0, sum = 3
4770 00:40:47.922650 11, 0x0, sum = 4
4771 00:40:47.922732 best_step = 9
4772 00:40:47.922796
4773 00:40:47.922856 ==
4774 00:40:47.925833 Dram Type= 6, Freq= 0, CH_1, rank 1
4775 00:40:47.929807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4776 00:40:47.929890 ==
4777 00:40:47.932989 RX Vref Scan: 0
4778 00:40:47.933071
4779 00:40:47.935766 RX Vref 0 -> 0, step: 1
4780 00:40:47.935847
4781 00:40:47.935911 RX Delay -195 -> 252, step: 8
4782 00:40:47.943584 iDelay=213, Bit 0, Center 48 (-99 ~ 196) 296
4783 00:40:47.947130 iDelay=213, Bit 1, Center 40 (-107 ~ 188) 296
4784 00:40:47.950087 iDelay=213, Bit 2, Center 32 (-115 ~ 180) 296
4785 00:40:47.953816 iDelay=213, Bit 3, Center 40 (-107 ~ 188) 296
4786 00:40:47.960257 iDelay=213, Bit 4, Center 44 (-107 ~ 196) 304
4787 00:40:47.963547 iDelay=213, Bit 5, Center 56 (-91 ~ 204) 296
4788 00:40:47.966531 iDelay=213, Bit 6, Center 60 (-91 ~ 212) 304
4789 00:40:47.969875 iDelay=213, Bit 7, Center 44 (-107 ~ 196) 304
4790 00:40:47.976657 iDelay=213, Bit 8, Center 24 (-131 ~ 180) 312
4791 00:40:47.980070 iDelay=213, Bit 9, Center 24 (-131 ~ 180) 312
4792 00:40:47.983325 iDelay=213, Bit 10, Center 36 (-115 ~ 188) 304
4793 00:40:47.986238 iDelay=213, Bit 11, Center 28 (-123 ~ 180) 304
4794 00:40:47.993198 iDelay=213, Bit 12, Center 48 (-107 ~ 204) 312
4795 00:40:47.996320 iDelay=213, Bit 13, Center 44 (-107 ~ 196) 304
4796 00:40:47.999687 iDelay=213, Bit 14, Center 44 (-107 ~ 196) 304
4797 00:40:48.002712 iDelay=213, Bit 15, Center 48 (-107 ~ 204) 312
4798 00:40:48.002822 ==
4799 00:40:48.006007 Dram Type= 6, Freq= 0, CH_1, rank 1
4800 00:40:48.012764 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4801 00:40:48.012849 ==
4802 00:40:48.012914 DQS Delay:
4803 00:40:48.016176 DQS0 = 0, DQS1 = 0
4804 00:40:48.016258 DQM Delay:
4805 00:40:48.016322 DQM0 = 45, DQM1 = 37
4806 00:40:48.019038 DQ Delay:
4807 00:40:48.022729 DQ0 =48, DQ1 =40, DQ2 =32, DQ3 =40
4808 00:40:48.025933 DQ4 =44, DQ5 =56, DQ6 =60, DQ7 =44
4809 00:40:48.029047 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =28
4810 00:40:48.032405 DQ12 =48, DQ13 =44, DQ14 =44, DQ15 =48
4811 00:40:48.032490
4812 00:40:48.032554
4813 00:40:48.038975 [DQSOSCAuto] RK1, (LSB)MR18= 0x2f24, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 400 ps
4814 00:40:48.042794 CH1 RK1: MR19=808, MR18=2F24
4815 00:40:48.049005 CH1_RK1: MR19=0x808, MR18=0x2F24, DQSOSC=400, MR23=63, INC=163, DEC=109
4816 00:40:48.052392 [RxdqsGatingPostProcess] freq 600
4817 00:40:48.055925 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4818 00:40:48.058940 Pre-setting of DQS Precalculation
4819 00:40:48.065372 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4820 00:40:48.072459 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4821 00:40:48.078804 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4822 00:40:48.078896
4823 00:40:48.078981
4824 00:40:48.081930 [Calibration Summary] 1200 Mbps
4825 00:40:48.085695 CH 0, Rank 0
4826 00:40:48.085778 SW Impedance : PASS
4827 00:40:48.088833 DUTY Scan : NO K
4828 00:40:48.088915 ZQ Calibration : PASS
4829 00:40:48.092305 Jitter Meter : NO K
4830 00:40:48.095721 CBT Training : PASS
4831 00:40:48.095803 Write leveling : PASS
4832 00:40:48.098815 RX DQS gating : PASS
4833 00:40:48.101863 RX DQ/DQS(RDDQC) : PASS
4834 00:40:48.101944 TX DQ/DQS : PASS
4835 00:40:48.104937 RX DATLAT : PASS
4836 00:40:48.108670 RX DQ/DQS(Engine): PASS
4837 00:40:48.108779 TX OE : NO K
4838 00:40:48.111996 All Pass.
4839 00:40:48.112078
4840 00:40:48.112143 CH 0, Rank 1
4841 00:40:48.114996 SW Impedance : PASS
4842 00:40:48.115076 DUTY Scan : NO K
4843 00:40:48.118233 ZQ Calibration : PASS
4844 00:40:48.121651 Jitter Meter : NO K
4845 00:40:48.121732 CBT Training : PASS
4846 00:40:48.124977 Write leveling : PASS
4847 00:40:48.128443 RX DQS gating : PASS
4848 00:40:48.128524 RX DQ/DQS(RDDQC) : PASS
4849 00:40:48.131523 TX DQ/DQS : PASS
4850 00:40:48.135039 RX DATLAT : PASS
4851 00:40:48.135121 RX DQ/DQS(Engine): PASS
4852 00:40:48.137968 TX OE : NO K
4853 00:40:48.138050 All Pass.
4854 00:40:48.138114
4855 00:40:48.141461 CH 1, Rank 0
4856 00:40:48.141559 SW Impedance : PASS
4857 00:40:48.144620 DUTY Scan : NO K
4858 00:40:48.148340 ZQ Calibration : PASS
4859 00:40:48.148446 Jitter Meter : NO K
4860 00:40:48.151356 CBT Training : PASS
4861 00:40:48.154779 Write leveling : PASS
4862 00:40:48.154861 RX DQS gating : PASS
4863 00:40:48.158113 RX DQ/DQS(RDDQC) : PASS
4864 00:40:48.158204 TX DQ/DQS : PASS
4865 00:40:48.161549 RX DATLAT : PASS
4866 00:40:48.164736 RX DQ/DQS(Engine): PASS
4867 00:40:48.164844 TX OE : NO K
4868 00:40:48.167668 All Pass.
4869 00:40:48.167749
4870 00:40:48.167813 CH 1, Rank 1
4871 00:40:48.170931 SW Impedance : PASS
4872 00:40:48.171011 DUTY Scan : NO K
4873 00:40:48.174405 ZQ Calibration : PASS
4874 00:40:48.177507 Jitter Meter : NO K
4875 00:40:48.177588 CBT Training : PASS
4876 00:40:48.180828 Write leveling : PASS
4877 00:40:48.184330 RX DQS gating : PASS
4878 00:40:48.184412 RX DQ/DQS(RDDQC) : PASS
4879 00:40:48.187662 TX DQ/DQS : PASS
4880 00:40:48.190806 RX DATLAT : PASS
4881 00:40:48.190888 RX DQ/DQS(Engine): PASS
4882 00:40:48.193927 TX OE : NO K
4883 00:40:48.194009 All Pass.
4884 00:40:48.194073
4885 00:40:48.197653 DramC Write-DBI off
4886 00:40:48.200677 PER_BANK_REFRESH: Hybrid Mode
4887 00:40:48.200758 TX_TRACKING: ON
4888 00:40:48.210305 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4889 00:40:48.213748 [FAST_K] Save calibration result to emmc
4890 00:40:48.216941 dramc_set_vcore_voltage set vcore to 662500
4891 00:40:48.220519 Read voltage for 933, 3
4892 00:40:48.220602 Vio18 = 0
4893 00:40:48.220686 Vcore = 662500
4894 00:40:48.223923 Vdram = 0
4895 00:40:48.224017 Vddq = 0
4896 00:40:48.224100 Vmddr = 0
4897 00:40:48.230139 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4898 00:40:48.233734 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4899 00:40:48.237003 MEM_TYPE=3, freq_sel=17
4900 00:40:48.240258 sv_algorithm_assistance_LP4_1600
4901 00:40:48.243761 ============ PULL DRAM RESETB DOWN ============
4902 00:40:48.249988 ========== PULL DRAM RESETB DOWN end =========
4903 00:40:48.253266 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4904 00:40:48.256663 ===================================
4905 00:40:48.259981 LPDDR4 DRAM CONFIGURATION
4906 00:40:48.263310 ===================================
4907 00:40:48.263392 EX_ROW_EN[0] = 0x0
4908 00:40:48.266865 EX_ROW_EN[1] = 0x0
4909 00:40:48.266948 LP4Y_EN = 0x0
4910 00:40:48.269764 WORK_FSP = 0x0
4911 00:40:48.269847 WL = 0x3
4912 00:40:48.273116 RL = 0x3
4913 00:40:48.273200 BL = 0x2
4914 00:40:48.276379 RPST = 0x0
4915 00:40:48.280006 RD_PRE = 0x0
4916 00:40:48.280113 WR_PRE = 0x1
4917 00:40:48.283038 WR_PST = 0x0
4918 00:40:48.283145 DBI_WR = 0x0
4919 00:40:48.286464 DBI_RD = 0x0
4920 00:40:48.286545 OTF = 0x1
4921 00:40:48.289791 ===================================
4922 00:40:48.293394 ===================================
4923 00:40:48.296244 ANA top config
4924 00:40:48.299699 ===================================
4925 00:40:48.299783 DLL_ASYNC_EN = 0
4926 00:40:48.302935 ALL_SLAVE_EN = 1
4927 00:40:48.306421 NEW_RANK_MODE = 1
4928 00:40:48.309892 DLL_IDLE_MODE = 1
4929 00:40:48.310003 LP45_APHY_COMB_EN = 1
4930 00:40:48.312965 TX_ODT_DIS = 1
4931 00:40:48.316323 NEW_8X_MODE = 1
4932 00:40:48.319235 ===================================
4933 00:40:48.322949 ===================================
4934 00:40:48.326083 data_rate = 1866
4935 00:40:48.329127 CKR = 1
4936 00:40:48.332952 DQ_P2S_RATIO = 8
4937 00:40:48.335892 ===================================
4938 00:40:48.335974 CA_P2S_RATIO = 8
4939 00:40:48.339122 DQ_CA_OPEN = 0
4940 00:40:48.342446 DQ_SEMI_OPEN = 0
4941 00:40:48.345662 CA_SEMI_OPEN = 0
4942 00:40:48.348937 CA_FULL_RATE = 0
4943 00:40:48.352512 DQ_CKDIV4_EN = 1
4944 00:40:48.352595 CA_CKDIV4_EN = 1
4945 00:40:48.355517 CA_PREDIV_EN = 0
4946 00:40:48.358703 PH8_DLY = 0
4947 00:40:48.362102 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4948 00:40:48.365553 DQ_AAMCK_DIV = 4
4949 00:40:48.368568 CA_AAMCK_DIV = 4
4950 00:40:48.368651 CA_ADMCK_DIV = 4
4951 00:40:48.372228 DQ_TRACK_CA_EN = 0
4952 00:40:48.375597 CA_PICK = 933
4953 00:40:48.378655 CA_MCKIO = 933
4954 00:40:48.381734 MCKIO_SEMI = 0
4955 00:40:48.385298 PLL_FREQ = 3732
4956 00:40:48.388777 DQ_UI_PI_RATIO = 32
4957 00:40:48.391527 CA_UI_PI_RATIO = 0
4958 00:40:48.395209 ===================================
4959 00:40:48.398595 ===================================
4960 00:40:48.398701 memory_type:LPDDR4
4961 00:40:48.401661 GP_NUM : 10
4962 00:40:48.404892 SRAM_EN : 1
4963 00:40:48.404979 MD32_EN : 0
4964 00:40:48.408197 ===================================
4965 00:40:48.411395 [ANA_INIT] >>>>>>>>>>>>>>
4966 00:40:48.414562 <<<<<< [CONFIGURE PHASE]: ANA_TX
4967 00:40:48.417966 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4968 00:40:48.421581 ===================================
4969 00:40:48.424598 data_rate = 1866,PCW = 0X8f00
4970 00:40:48.427951 ===================================
4971 00:40:48.431312 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4972 00:40:48.434326 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4973 00:40:48.440955 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4974 00:40:48.444128 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4975 00:40:48.447977 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4976 00:40:48.453982 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4977 00:40:48.454095 [ANA_INIT] flow start
4978 00:40:48.457505 [ANA_INIT] PLL >>>>>>>>
4979 00:40:48.460303 [ANA_INIT] PLL <<<<<<<<
4980 00:40:48.460413 [ANA_INIT] MIDPI >>>>>>>>
4981 00:40:48.463886 [ANA_INIT] MIDPI <<<<<<<<
4982 00:40:48.467617 [ANA_INIT] DLL >>>>>>>>
4983 00:40:48.467701 [ANA_INIT] flow end
4984 00:40:48.473690 ============ LP4 DIFF to SE enter ============
4985 00:40:48.477417 ============ LP4 DIFF to SE exit ============
4986 00:40:48.477500 [ANA_INIT] <<<<<<<<<<<<<
4987 00:40:48.480717 [Flow] Enable top DCM control >>>>>
4988 00:40:48.484048 [Flow] Enable top DCM control <<<<<
4989 00:40:48.487296 Enable DLL master slave shuffle
4990 00:40:48.493712 ==============================================================
4991 00:40:48.497035 Gating Mode config
4992 00:40:48.500505 ==============================================================
4993 00:40:48.503573 Config description:
4994 00:40:48.513338 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4995 00:40:48.519910 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4996 00:40:48.523118 SELPH_MODE 0: By rank 1: By Phase
4997 00:40:48.529347 ==============================================================
4998 00:40:48.532988 GAT_TRACK_EN = 1
4999 00:40:48.536318 RX_GATING_MODE = 2
5000 00:40:48.539403 RX_GATING_TRACK_MODE = 2
5001 00:40:48.542559 SELPH_MODE = 1
5002 00:40:48.545995 PICG_EARLY_EN = 1
5003 00:40:48.546086 VALID_LAT_VALUE = 1
5004 00:40:48.552319 ==============================================================
5005 00:40:48.556123 Enter into Gating configuration >>>>
5006 00:40:48.559209 Exit from Gating configuration <<<<
5007 00:40:48.562350 Enter into DVFS_PRE_config >>>>>
5008 00:40:48.575712 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5009 00:40:48.575815 Exit from DVFS_PRE_config <<<<<
5010 00:40:48.578724 Enter into PICG configuration >>>>
5011 00:40:48.582425 Exit from PICG configuration <<<<
5012 00:40:48.585407 [RX_INPUT] configuration >>>>>
5013 00:40:48.589104 [RX_INPUT] configuration <<<<<
5014 00:40:48.595563 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5015 00:40:48.598831 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5016 00:40:48.605249 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5017 00:40:48.612030 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5018 00:40:48.618690 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5019 00:40:48.625007 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5020 00:40:48.628366 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5021 00:40:48.631904 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5022 00:40:48.635311 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5023 00:40:48.641506 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5024 00:40:48.644762 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5025 00:40:48.648055 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5026 00:40:48.651320 ===================================
5027 00:40:48.654746 LPDDR4 DRAM CONFIGURATION
5028 00:40:48.657840 ===================================
5029 00:40:48.661531 EX_ROW_EN[0] = 0x0
5030 00:40:48.661647 EX_ROW_EN[1] = 0x0
5031 00:40:48.664946 LP4Y_EN = 0x0
5032 00:40:48.665045 WORK_FSP = 0x0
5033 00:40:48.667895 WL = 0x3
5034 00:40:48.667980 RL = 0x3
5035 00:40:48.671365 BL = 0x2
5036 00:40:48.671466 RPST = 0x0
5037 00:40:48.674362 RD_PRE = 0x0
5038 00:40:48.674465 WR_PRE = 0x1
5039 00:40:48.677750 WR_PST = 0x0
5040 00:40:48.677847 DBI_WR = 0x0
5041 00:40:48.680928 DBI_RD = 0x0
5042 00:40:48.681026 OTF = 0x1
5043 00:40:48.684214 ===================================
5044 00:40:48.690880 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5045 00:40:48.694148 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5046 00:40:48.697594 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5047 00:40:48.701035 ===================================
5048 00:40:48.704267 LPDDR4 DRAM CONFIGURATION
5049 00:40:48.707402 ===================================
5050 00:40:48.710425 EX_ROW_EN[0] = 0x10
5051 00:40:48.710508 EX_ROW_EN[1] = 0x0
5052 00:40:48.713863 LP4Y_EN = 0x0
5053 00:40:48.713979 WORK_FSP = 0x0
5054 00:40:48.717256 WL = 0x3
5055 00:40:48.717336 RL = 0x3
5056 00:40:48.720934 BL = 0x2
5057 00:40:48.721014 RPST = 0x0
5058 00:40:48.723987 RD_PRE = 0x0
5059 00:40:48.724068 WR_PRE = 0x1
5060 00:40:48.727128 WR_PST = 0x0
5061 00:40:48.730550 DBI_WR = 0x0
5062 00:40:48.730658 DBI_RD = 0x0
5063 00:40:48.733500 OTF = 0x1
5064 00:40:48.736784 ===================================
5065 00:40:48.740327 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5066 00:40:48.745390 nWR fixed to 30
5067 00:40:48.748791 [ModeRegInit_LP4] CH0 RK0
5068 00:40:48.748875 [ModeRegInit_LP4] CH0 RK1
5069 00:40:48.752202 [ModeRegInit_LP4] CH1 RK0
5070 00:40:48.755439 [ModeRegInit_LP4] CH1 RK1
5071 00:40:48.755561 match AC timing 9
5072 00:40:48.761820 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5073 00:40:48.765011 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5074 00:40:48.768724 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5075 00:40:48.775200 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5076 00:40:48.778506 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5077 00:40:48.778582 ==
5078 00:40:48.782001 Dram Type= 6, Freq= 0, CH_0, rank 0
5079 00:40:48.785188 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5080 00:40:48.785269 ==
5081 00:40:48.791599 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5082 00:40:48.798148 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5083 00:40:48.801678 [CA 0] Center 37 (7~68) winsize 62
5084 00:40:48.804827 [CA 1] Center 37 (7~68) winsize 62
5085 00:40:48.808176 [CA 2] Center 34 (4~65) winsize 62
5086 00:40:48.811386 [CA 3] Center 35 (5~65) winsize 61
5087 00:40:48.815304 [CA 4] Center 33 (3~64) winsize 62
5088 00:40:48.818427 [CA 5] Center 33 (3~63) winsize 61
5089 00:40:48.818529
5090 00:40:48.821626 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5091 00:40:48.821723
5092 00:40:48.824681 [CATrainingPosCal] consider 1 rank data
5093 00:40:48.828120 u2DelayCellTimex100 = 270/100 ps
5094 00:40:48.831469 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5095 00:40:48.834541 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5096 00:40:48.837646 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5097 00:40:48.844202 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5098 00:40:48.847643 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5099 00:40:48.851054 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5100 00:40:48.851132
5101 00:40:48.854097 CA PerBit enable=1, Macro0, CA PI delay=33
5102 00:40:48.854224
5103 00:40:48.857705 [CBTSetCACLKResult] CA Dly = 33
5104 00:40:48.857809 CS Dly: 7 (0~38)
5105 00:40:48.857902 ==
5106 00:40:48.860601 Dram Type= 6, Freq= 0, CH_0, rank 1
5107 00:40:48.867706 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5108 00:40:48.867785 ==
5109 00:40:48.870637 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5110 00:40:48.877136 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5111 00:40:48.880387 [CA 0] Center 37 (7~68) winsize 62
5112 00:40:48.883903 [CA 1] Center 37 (7~68) winsize 62
5113 00:40:48.887049 [CA 2] Center 34 (4~65) winsize 62
5114 00:40:48.890361 [CA 3] Center 34 (4~65) winsize 62
5115 00:40:48.894037 [CA 4] Center 33 (3~64) winsize 62
5116 00:40:48.896920 [CA 5] Center 33 (3~63) winsize 61
5117 00:40:48.897016
5118 00:40:48.900627 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5119 00:40:48.900723
5120 00:40:48.903730 [CATrainingPosCal] consider 2 rank data
5121 00:40:48.907025 u2DelayCellTimex100 = 270/100 ps
5122 00:40:48.910684 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5123 00:40:48.917158 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5124 00:40:48.920063 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5125 00:40:48.923652 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5126 00:40:48.926713 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5127 00:40:48.929992 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5128 00:40:48.930100
5129 00:40:48.933777 CA PerBit enable=1, Macro0, CA PI delay=33
5130 00:40:48.933908
5131 00:40:48.936770 [CBTSetCACLKResult] CA Dly = 33
5132 00:40:48.940575 CS Dly: 7 (0~39)
5133 00:40:48.940677
5134 00:40:48.943103 ----->DramcWriteLeveling(PI) begin...
5135 00:40:48.943205 ==
5136 00:40:48.946567 Dram Type= 6, Freq= 0, CH_0, rank 0
5137 00:40:48.950035 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5138 00:40:48.950155 ==
5139 00:40:48.953278 Write leveling (Byte 0): 34 => 34
5140 00:40:48.956803 Write leveling (Byte 1): 29 => 29
5141 00:40:48.959799 DramcWriteLeveling(PI) end<-----
5142 00:40:48.959901
5143 00:40:48.960008 ==
5144 00:40:48.963475 Dram Type= 6, Freq= 0, CH_0, rank 0
5145 00:40:48.966345 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5146 00:40:48.966421 ==
5147 00:40:48.969746 [Gating] SW mode calibration
5148 00:40:48.976186 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5149 00:40:48.983007 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5150 00:40:48.986168 0 14 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
5151 00:40:48.989813 0 14 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5152 00:40:48.996195 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5153 00:40:48.999529 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5154 00:40:49.002699 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5155 00:40:49.009375 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5156 00:40:49.012761 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5157 00:40:49.016126 0 14 28 | B1->B0 | 3434 2b2b | 1 0 | (1 1) (0 0)
5158 00:40:49.022376 0 15 0 | B1->B0 | 3131 2626 | 1 0 | (1 0) (0 0)
5159 00:40:49.025879 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5160 00:40:49.029110 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5161 00:40:49.035694 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5162 00:40:49.039464 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5163 00:40:49.042531 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5164 00:40:49.049126 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5165 00:40:49.052288 0 15 28 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
5166 00:40:49.055717 1 0 0 | B1->B0 | 3232 4141 | 0 0 | (0 0) (0 0)
5167 00:40:49.062053 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5168 00:40:49.065240 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5169 00:40:49.068881 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5170 00:40:49.075188 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5171 00:40:49.078480 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5172 00:40:49.082068 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5173 00:40:49.088327 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5174 00:40:49.091737 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5175 00:40:49.095039 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5176 00:40:49.101664 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5177 00:40:49.105303 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5178 00:40:49.108418 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5179 00:40:49.114796 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5180 00:40:49.118454 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5181 00:40:49.121298 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5182 00:40:49.128197 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5183 00:40:49.131478 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5184 00:40:49.134794 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5185 00:40:49.141470 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5186 00:40:49.144587 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5187 00:40:49.148172 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5188 00:40:49.154554 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5189 00:40:49.157842 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5190 00:40:49.161349 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5191 00:40:49.164620 Total UI for P1: 0, mck2ui 16
5192 00:40:49.167577 best dqsien dly found for B0: ( 1, 2, 28)
5193 00:40:49.174310 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5194 00:40:49.177449 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5195 00:40:49.181359 Total UI for P1: 0, mck2ui 16
5196 00:40:49.184125 best dqsien dly found for B1: ( 1, 3, 2)
5197 00:40:49.187353 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5198 00:40:49.190868 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5199 00:40:49.190953
5200 00:40:49.193935 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5201 00:40:49.197264 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5202 00:40:49.200667 [Gating] SW calibration Done
5203 00:40:49.200755 ==
5204 00:40:49.203610 Dram Type= 6, Freq= 0, CH_0, rank 0
5205 00:40:49.210530 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5206 00:40:49.210655 ==
5207 00:40:49.210740 RX Vref Scan: 0
5208 00:40:49.210820
5209 00:40:49.213613 RX Vref 0 -> 0, step: 1
5210 00:40:49.213696
5211 00:40:49.217012 RX Delay -80 -> 252, step: 8
5212 00:40:49.221041 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5213 00:40:49.223535 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5214 00:40:49.226882 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5215 00:40:49.230135 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5216 00:40:49.236712 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5217 00:40:49.239858 iDelay=208, Bit 5, Center 87 (-16 ~ 191) 208
5218 00:40:49.243293 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5219 00:40:49.246445 iDelay=208, Bit 7, Center 103 (0 ~ 207) 208
5220 00:40:49.249892 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5221 00:40:49.253040 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5222 00:40:49.259822 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5223 00:40:49.262966 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5224 00:40:49.266325 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5225 00:40:49.269669 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5226 00:40:49.273259 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5227 00:40:49.279937 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5228 00:40:49.280046 ==
5229 00:40:49.283527 Dram Type= 6, Freq= 0, CH_0, rank 0
5230 00:40:49.286744 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5231 00:40:49.286822 ==
5232 00:40:49.286884 DQS Delay:
5233 00:40:49.289711 DQS0 = 0, DQS1 = 0
5234 00:40:49.289806 DQM Delay:
5235 00:40:49.292833 DQM0 = 98, DQM1 = 87
5236 00:40:49.292911 DQ Delay:
5237 00:40:49.295937 DQ0 =99, DQ1 =99, DQ2 =95, DQ3 =95
5238 00:40:49.299326 DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =103
5239 00:40:49.302599 DQ8 =79, DQ9 =79, DQ10 =83, DQ11 =79
5240 00:40:49.306028 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5241 00:40:49.306129
5242 00:40:49.306245
5243 00:40:49.306305 ==
5244 00:40:49.309217 Dram Type= 6, Freq= 0, CH_0, rank 0
5245 00:40:49.312855 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5246 00:40:49.316034 ==
5247 00:40:49.316136
5248 00:40:49.316225
5249 00:40:49.316314 TX Vref Scan disable
5250 00:40:49.319099 == TX Byte 0 ==
5251 00:40:49.322265 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5252 00:40:49.325947 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5253 00:40:49.329169 == TX Byte 1 ==
5254 00:40:49.332543 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5255 00:40:49.336189 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5256 00:40:49.338871 ==
5257 00:40:49.342093 Dram Type= 6, Freq= 0, CH_0, rank 0
5258 00:40:49.345278 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5259 00:40:49.345386 ==
5260 00:40:49.345491
5261 00:40:49.345588
5262 00:40:49.348582 TX Vref Scan disable
5263 00:40:49.348684 == TX Byte 0 ==
5264 00:40:49.355615 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5265 00:40:49.358675 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5266 00:40:49.358779 == TX Byte 1 ==
5267 00:40:49.365337 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5268 00:40:49.368706 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5269 00:40:49.368806
5270 00:40:49.368905 [DATLAT]
5271 00:40:49.371773 Freq=933, CH0 RK0
5272 00:40:49.371871
5273 00:40:49.371971 DATLAT Default: 0xd
5274 00:40:49.375521 0, 0xFFFF, sum = 0
5275 00:40:49.375610 1, 0xFFFF, sum = 0
5276 00:40:49.378587 2, 0xFFFF, sum = 0
5277 00:40:49.381935 3, 0xFFFF, sum = 0
5278 00:40:49.382040 4, 0xFFFF, sum = 0
5279 00:40:49.385412 5, 0xFFFF, sum = 0
5280 00:40:49.385529 6, 0xFFFF, sum = 0
5281 00:40:49.388355 7, 0xFFFF, sum = 0
5282 00:40:49.388474 8, 0xFFFF, sum = 0
5283 00:40:49.391776 9, 0xFFFF, sum = 0
5284 00:40:49.391847 10, 0x0, sum = 1
5285 00:40:49.394883 11, 0x0, sum = 2
5286 00:40:49.394982 12, 0x0, sum = 3
5287 00:40:49.398292 13, 0x0, sum = 4
5288 00:40:49.398367 best_step = 11
5289 00:40:49.398448
5290 00:40:49.398509 ==
5291 00:40:49.401215 Dram Type= 6, Freq= 0, CH_0, rank 0
5292 00:40:49.404860 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5293 00:40:49.404957 ==
5294 00:40:49.408003 RX Vref Scan: 1
5295 00:40:49.408074
5296 00:40:49.411251 RX Vref 0 -> 0, step: 1
5297 00:40:49.411350
5298 00:40:49.411433 RX Delay -61 -> 252, step: 4
5299 00:40:49.414532
5300 00:40:49.417838 Set Vref, RX VrefLevel [Byte0]: 60
5301 00:40:49.417937 [Byte1]: 49
5302 00:40:49.422811
5303 00:40:49.422916 Final RX Vref Byte 0 = 60 to rank0
5304 00:40:49.425939 Final RX Vref Byte 1 = 49 to rank0
5305 00:40:49.429311 Final RX Vref Byte 0 = 60 to rank1
5306 00:40:49.432664 Final RX Vref Byte 1 = 49 to rank1==
5307 00:40:49.436123 Dram Type= 6, Freq= 0, CH_0, rank 0
5308 00:40:49.442609 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5309 00:40:49.442719 ==
5310 00:40:49.442812 DQS Delay:
5311 00:40:49.442903 DQS0 = 0, DQS1 = 0
5312 00:40:49.445979 DQM Delay:
5313 00:40:49.446077 DQM0 = 96, DQM1 = 84
5314 00:40:49.449536 DQ Delay:
5315 00:40:49.452789 DQ0 =96, DQ1 =98, DQ2 =92, DQ3 =92
5316 00:40:49.456191 DQ4 =96, DQ5 =88, DQ6 =106, DQ7 =106
5317 00:40:49.459297 DQ8 =76, DQ9 =74, DQ10 =86, DQ11 =78
5318 00:40:49.462616 DQ12 =88, DQ13 =88, DQ14 =94, DQ15 =92
5319 00:40:49.462716
5320 00:40:49.462810
5321 00:40:49.469117 [DQSOSCAuto] RK0, (LSB)MR18= 0x2a10, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 408 ps
5322 00:40:49.472391 CH0 RK0: MR19=505, MR18=2A10
5323 00:40:49.479473 CH0_RK0: MR19=0x505, MR18=0x2A10, DQSOSC=408, MR23=63, INC=65, DEC=43
5324 00:40:49.479579
5325 00:40:49.482237 ----->DramcWriteLeveling(PI) begin...
5326 00:40:49.482343 ==
5327 00:40:49.485596 Dram Type= 6, Freq= 0, CH_0, rank 1
5328 00:40:49.488911 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5329 00:40:49.488984 ==
5330 00:40:49.492226 Write leveling (Byte 0): 33 => 33
5331 00:40:49.496040 Write leveling (Byte 1): 32 => 32
5332 00:40:49.498875 DramcWriteLeveling(PI) end<-----
5333 00:40:49.498949
5334 00:40:49.499011 ==
5335 00:40:49.502445 Dram Type= 6, Freq= 0, CH_0, rank 1
5336 00:40:49.505518 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5337 00:40:49.508686 ==
5338 00:40:49.508787 [Gating] SW mode calibration
5339 00:40:49.518416 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5340 00:40:49.521973 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5341 00:40:49.525172 0 14 0 | B1->B0 | 2828 3232 | 0 0 | (0 0) (0 0)
5342 00:40:49.532150 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5343 00:40:49.535230 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5344 00:40:49.538340 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5345 00:40:49.545458 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5346 00:40:49.548678 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5347 00:40:49.551977 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5348 00:40:49.558600 0 14 28 | B1->B0 | 3434 2f2f | 0 1 | (0 0) (1 1)
5349 00:40:49.561842 0 15 0 | B1->B0 | 2e2e 2424 | 1 0 | (1 0) (0 0)
5350 00:40:49.564917 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5351 00:40:49.571812 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5352 00:40:49.575116 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5353 00:40:49.578076 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5354 00:40:49.585130 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5355 00:40:49.587922 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5356 00:40:49.591392 0 15 28 | B1->B0 | 2323 3433 | 0 1 | (0 0) (0 0)
5357 00:40:49.598283 1 0 0 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
5358 00:40:49.601558 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5359 00:40:49.604523 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5360 00:40:49.611270 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5361 00:40:49.614998 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5362 00:40:49.617894 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5363 00:40:49.624407 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5364 00:40:49.627786 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5365 00:40:49.631507 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5366 00:40:49.637727 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5367 00:40:49.641016 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5368 00:40:49.644691 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5369 00:40:49.651050 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5370 00:40:49.654071 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5371 00:40:49.657339 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5372 00:40:49.664196 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5373 00:40:49.667586 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5374 00:40:49.671053 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5375 00:40:49.677379 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5376 00:40:49.680666 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5377 00:40:49.683751 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5378 00:40:49.691099 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5379 00:40:49.693716 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5380 00:40:49.697431 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5381 00:40:49.703621 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5382 00:40:49.707012 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5383 00:40:49.710124 Total UI for P1: 0, mck2ui 16
5384 00:40:49.713379 best dqsien dly found for B0: ( 1, 3, 0)
5385 00:40:49.716856 Total UI for P1: 0, mck2ui 16
5386 00:40:49.719966 best dqsien dly found for B1: ( 1, 3, 0)
5387 00:40:49.723583 best DQS0 dly(MCK, UI, PI) = (1, 3, 0)
5388 00:40:49.727002 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5389 00:40:49.727107
5390 00:40:49.730468 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 0)
5391 00:40:49.733170 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5392 00:40:49.737064 [Gating] SW calibration Done
5393 00:40:49.737171 ==
5394 00:40:49.740150 Dram Type= 6, Freq= 0, CH_0, rank 1
5395 00:40:49.743304 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5396 00:40:49.743407 ==
5397 00:40:49.746788 RX Vref Scan: 0
5398 00:40:49.746861
5399 00:40:49.750091 RX Vref 0 -> 0, step: 1
5400 00:40:49.750222
5401 00:40:49.750289 RX Delay -80 -> 252, step: 8
5402 00:40:49.756782 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5403 00:40:49.759749 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5404 00:40:49.763225 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5405 00:40:49.766287 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5406 00:40:49.770055 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5407 00:40:49.773067 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5408 00:40:49.780016 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5409 00:40:49.783201 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5410 00:40:49.786411 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5411 00:40:49.789407 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5412 00:40:49.792899 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5413 00:40:49.799240 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5414 00:40:49.802586 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5415 00:40:49.806442 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5416 00:40:49.809660 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5417 00:40:49.812837 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5418 00:40:49.812933 ==
5419 00:40:49.816045 Dram Type= 6, Freq= 0, CH_0, rank 1
5420 00:40:49.822658 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5421 00:40:49.822732 ==
5422 00:40:49.822816 DQS Delay:
5423 00:40:49.825972 DQS0 = 0, DQS1 = 0
5424 00:40:49.826068 DQM Delay:
5425 00:40:49.826157 DQM0 = 97, DQM1 = 88
5426 00:40:49.829165 DQ Delay:
5427 00:40:49.832182 DQ0 =95, DQ1 =99, DQ2 =91, DQ3 =91
5428 00:40:49.835894 DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =107
5429 00:40:49.839295 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =79
5430 00:40:49.842257 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5431 00:40:49.842328
5432 00:40:49.842387
5433 00:40:49.842449 ==
5434 00:40:49.845892 Dram Type= 6, Freq= 0, CH_0, rank 1
5435 00:40:49.849040 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5436 00:40:49.849136 ==
5437 00:40:49.849226
5438 00:40:49.849312
5439 00:40:49.852274 TX Vref Scan disable
5440 00:40:49.855806 == TX Byte 0 ==
5441 00:40:49.858506 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5442 00:40:49.861901 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5443 00:40:49.865283 == TX Byte 1 ==
5444 00:40:49.868481 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5445 00:40:49.871997 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5446 00:40:49.872109 ==
5447 00:40:49.875531 Dram Type= 6, Freq= 0, CH_0, rank 1
5448 00:40:49.881523 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5449 00:40:49.881690 ==
5450 00:40:49.881788
5451 00:40:49.881875
5452 00:40:49.881977 TX Vref Scan disable
5453 00:40:49.885790 == TX Byte 0 ==
5454 00:40:49.889082 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5455 00:40:49.895512 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5456 00:40:49.895601 == TX Byte 1 ==
5457 00:40:49.899020 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5458 00:40:49.905288 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5459 00:40:49.905426
5460 00:40:49.905528 [DATLAT]
5461 00:40:49.905615 Freq=933, CH0 RK1
5462 00:40:49.905713
5463 00:40:49.908806 DATLAT Default: 0xb
5464 00:40:49.912286 0, 0xFFFF, sum = 0
5465 00:40:49.912403 1, 0xFFFF, sum = 0
5466 00:40:49.915098 2, 0xFFFF, sum = 0
5467 00:40:49.915171 3, 0xFFFF, sum = 0
5468 00:40:49.918158 4, 0xFFFF, sum = 0
5469 00:40:49.918298 5, 0xFFFF, sum = 0
5470 00:40:49.921617 6, 0xFFFF, sum = 0
5471 00:40:49.921708 7, 0xFFFF, sum = 0
5472 00:40:49.925406 8, 0xFFFF, sum = 0
5473 00:40:49.925506 9, 0xFFFF, sum = 0
5474 00:40:49.928671 10, 0x0, sum = 1
5475 00:40:49.928773 11, 0x0, sum = 2
5476 00:40:49.931522 12, 0x0, sum = 3
5477 00:40:49.931627 13, 0x0, sum = 4
5478 00:40:49.935117 best_step = 11
5479 00:40:49.935194
5480 00:40:49.935257 ==
5481 00:40:49.938093 Dram Type= 6, Freq= 0, CH_0, rank 1
5482 00:40:49.941617 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5483 00:40:49.941713 ==
5484 00:40:49.941811 RX Vref Scan: 0
5485 00:40:49.945039
5486 00:40:49.945109 RX Vref 0 -> 0, step: 1
5487 00:40:49.945168
5488 00:40:49.948120 RX Delay -61 -> 252, step: 4
5489 00:40:49.954725 iDelay=203, Bit 0, Center 92 (-1 ~ 186) 188
5490 00:40:49.958149 iDelay=203, Bit 1, Center 96 (-1 ~ 194) 196
5491 00:40:49.961740 iDelay=203, Bit 2, Center 90 (-1 ~ 182) 184
5492 00:40:49.964650 iDelay=203, Bit 3, Center 94 (-1 ~ 190) 192
5493 00:40:49.967851 iDelay=203, Bit 4, Center 96 (3 ~ 190) 188
5494 00:40:49.971598 iDelay=203, Bit 5, Center 86 (-9 ~ 182) 192
5495 00:40:49.977709 iDelay=203, Bit 6, Center 104 (7 ~ 202) 196
5496 00:40:49.981305 iDelay=203, Bit 7, Center 104 (11 ~ 198) 188
5497 00:40:49.984457 iDelay=203, Bit 8, Center 78 (-13 ~ 170) 184
5498 00:40:49.987605 iDelay=203, Bit 9, Center 74 (-17 ~ 166) 184
5499 00:40:49.990988 iDelay=203, Bit 10, Center 88 (-5 ~ 182) 188
5500 00:40:49.997406 iDelay=203, Bit 11, Center 78 (-13 ~ 170) 184
5501 00:40:50.001066 iDelay=203, Bit 12, Center 92 (-1 ~ 186) 188
5502 00:40:50.004338 iDelay=203, Bit 13, Center 92 (-1 ~ 186) 188
5503 00:40:50.007906 iDelay=203, Bit 14, Center 94 (3 ~ 186) 184
5504 00:40:50.010807 iDelay=203, Bit 15, Center 92 (-1 ~ 186) 188
5505 00:40:50.014110 ==
5506 00:40:50.017397 Dram Type= 6, Freq= 0, CH_0, rank 1
5507 00:40:50.020615 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5508 00:40:50.020769 ==
5509 00:40:50.020941 DQS Delay:
5510 00:40:50.024026 DQS0 = 0, DQS1 = 0
5511 00:40:50.024174 DQM Delay:
5512 00:40:50.027679 DQM0 = 95, DQM1 = 86
5513 00:40:50.027826 DQ Delay:
5514 00:40:50.030360 DQ0 =92, DQ1 =96, DQ2 =90, DQ3 =94
5515 00:40:50.033763 DQ4 =96, DQ5 =86, DQ6 =104, DQ7 =104
5516 00:40:50.036948 DQ8 =78, DQ9 =74, DQ10 =88, DQ11 =78
5517 00:40:50.040246 DQ12 =92, DQ13 =92, DQ14 =94, DQ15 =92
5518 00:40:50.040400
5519 00:40:50.040541
5520 00:40:50.047097 [DQSOSCAuto] RK1, (LSB)MR18= 0x25f5, (MSB)MR19= 0x504, tDQSOscB0 = 425 ps tDQSOscB1 = 410 ps
5521 00:40:50.050104 CH0 RK1: MR19=504, MR18=25F5
5522 00:40:50.056781 CH0_RK1: MR19=0x504, MR18=0x25F5, DQSOSC=410, MR23=63, INC=64, DEC=42
5523 00:40:50.060255 [RxdqsGatingPostProcess] freq 933
5524 00:40:50.066772 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5525 00:40:50.069979 best DQS0 dly(2T, 0.5T) = (0, 10)
5526 00:40:50.073421 best DQS1 dly(2T, 0.5T) = (0, 11)
5527 00:40:50.076266 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5528 00:40:50.079922 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5529 00:40:50.080080 best DQS0 dly(2T, 0.5T) = (0, 11)
5530 00:40:50.082869 best DQS1 dly(2T, 0.5T) = (0, 11)
5531 00:40:50.086292 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
5532 00:40:50.089789 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5533 00:40:50.093093 Pre-setting of DQS Precalculation
5534 00:40:50.099903 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5535 00:40:50.100064 ==
5536 00:40:50.102818 Dram Type= 6, Freq= 0, CH_1, rank 0
5537 00:40:50.105985 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5538 00:40:50.106146 ==
5539 00:40:50.112720 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5540 00:40:50.119241 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5541 00:40:50.122788 [CA 0] Center 36 (6~67) winsize 62
5542 00:40:50.125872 [CA 1] Center 36 (6~67) winsize 62
5543 00:40:50.129347 [CA 2] Center 34 (4~65) winsize 62
5544 00:40:50.132807 [CA 3] Center 33 (3~64) winsize 62
5545 00:40:50.136078 [CA 4] Center 34 (4~64) winsize 61
5546 00:40:50.139174 [CA 5] Center 33 (3~64) winsize 62
5547 00:40:50.139253
5548 00:40:50.142447 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5549 00:40:50.142526
5550 00:40:50.145619 [CATrainingPosCal] consider 1 rank data
5551 00:40:50.149064 u2DelayCellTimex100 = 270/100 ps
5552 00:40:50.152286 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5553 00:40:50.156292 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5554 00:40:50.158898 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5555 00:40:50.162428 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5556 00:40:50.165675 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5557 00:40:50.169094 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5558 00:40:50.169196
5559 00:40:50.176193 CA PerBit enable=1, Macro0, CA PI delay=33
5560 00:40:50.176296
5561 00:40:50.176396 [CBTSetCACLKResult] CA Dly = 33
5562 00:40:50.178737 CS Dly: 6 (0~37)
5563 00:40:50.178833 ==
5564 00:40:50.181903 Dram Type= 6, Freq= 0, CH_1, rank 1
5565 00:40:50.185412 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5566 00:40:50.185536 ==
5567 00:40:50.192028 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5568 00:40:50.198681 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5569 00:40:50.201713 [CA 0] Center 36 (6~67) winsize 62
5570 00:40:50.205443 [CA 1] Center 36 (6~67) winsize 62
5571 00:40:50.208606 [CA 2] Center 34 (4~65) winsize 62
5572 00:40:50.211697 [CA 3] Center 34 (3~65) winsize 63
5573 00:40:50.215266 [CA 4] Center 34 (4~65) winsize 62
5574 00:40:50.218501 [CA 5] Center 33 (3~64) winsize 62
5575 00:40:50.218587
5576 00:40:50.221487 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5577 00:40:50.221571
5578 00:40:50.224672 [CATrainingPosCal] consider 2 rank data
5579 00:40:50.228281 u2DelayCellTimex100 = 270/100 ps
5580 00:40:50.231306 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5581 00:40:50.234789 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5582 00:40:50.238247 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5583 00:40:50.241282 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5584 00:40:50.248365 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5585 00:40:50.251702 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5586 00:40:50.251873
5587 00:40:50.254541 CA PerBit enable=1, Macro0, CA PI delay=33
5588 00:40:50.254663
5589 00:40:50.258122 [CBTSetCACLKResult] CA Dly = 33
5590 00:40:50.258252 CS Dly: 7 (0~39)
5591 00:40:50.258333
5592 00:40:50.261483 ----->DramcWriteLeveling(PI) begin...
5593 00:40:50.261618 ==
5594 00:40:50.264849 Dram Type= 6, Freq= 0, CH_1, rank 0
5595 00:40:50.270791 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5596 00:40:50.270957 ==
5597 00:40:50.274342 Write leveling (Byte 0): 26 => 26
5598 00:40:50.277525 Write leveling (Byte 1): 30 => 30
5599 00:40:50.277688 DramcWriteLeveling(PI) end<-----
5600 00:40:50.281385
5601 00:40:50.281577 ==
5602 00:40:50.284412 Dram Type= 6, Freq= 0, CH_1, rank 0
5603 00:40:50.287951 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5604 00:40:50.288040 ==
5605 00:40:50.290886 [Gating] SW mode calibration
5606 00:40:50.297604 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5607 00:40:50.300659 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5608 00:40:50.307579 0 14 0 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
5609 00:40:50.311042 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5610 00:40:50.314065 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5611 00:40:50.320760 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5612 00:40:50.323867 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5613 00:40:50.327024 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5614 00:40:50.333410 0 14 24 | B1->B0 | 3434 3333 | 1 0 | (1 0) (0 0)
5615 00:40:50.336820 0 14 28 | B1->B0 | 2f2f 2a2a | 1 0 | (0 0) (0 0)
5616 00:40:50.340689 0 15 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5617 00:40:50.346712 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5618 00:40:50.350451 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5619 00:40:50.353584 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5620 00:40:50.360096 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5621 00:40:50.363416 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5622 00:40:50.366593 0 15 24 | B1->B0 | 2525 2424 | 0 0 | (0 0) (1 1)
5623 00:40:50.373342 0 15 28 | B1->B0 | 3131 3838 | 0 0 | (0 0) (0 0)
5624 00:40:50.376805 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5625 00:40:50.380199 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5626 00:40:50.386323 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5627 00:40:50.389936 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5628 00:40:50.392987 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5629 00:40:50.399674 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5630 00:40:50.403316 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5631 00:40:50.406863 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5632 00:40:50.412927 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5633 00:40:50.416250 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5634 00:40:50.419653 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5635 00:40:50.426809 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5636 00:40:50.429637 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5637 00:40:50.433092 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5638 00:40:50.439451 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5639 00:40:50.443066 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5640 00:40:50.446339 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5641 00:40:50.452455 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5642 00:40:50.456318 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5643 00:40:50.459318 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5644 00:40:50.465720 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5645 00:40:50.469070 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5646 00:40:50.472325 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5647 00:40:50.478927 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5648 00:40:50.482603 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5649 00:40:50.485450 Total UI for P1: 0, mck2ui 16
5650 00:40:50.488987 best dqsien dly found for B0: ( 1, 2, 26)
5651 00:40:50.492191 Total UI for P1: 0, mck2ui 16
5652 00:40:50.495393 best dqsien dly found for B1: ( 1, 2, 28)
5653 00:40:50.498792 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5654 00:40:50.502640 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5655 00:40:50.502723
5656 00:40:50.505398 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5657 00:40:50.509119 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5658 00:40:50.512304 [Gating] SW calibration Done
5659 00:40:50.512385 ==
5660 00:40:50.515654 Dram Type= 6, Freq= 0, CH_1, rank 0
5661 00:40:50.522416 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5662 00:40:50.522497 ==
5663 00:40:50.522561 RX Vref Scan: 0
5664 00:40:50.522621
5665 00:40:50.525310 RX Vref 0 -> 0, step: 1
5666 00:40:50.525390
5667 00:40:50.528501 RX Delay -80 -> 252, step: 8
5668 00:40:50.532246 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5669 00:40:50.535431 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5670 00:40:50.538233 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5671 00:40:50.541626 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5672 00:40:50.548539 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5673 00:40:50.551795 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5674 00:40:50.554921 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5675 00:40:50.558182 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5676 00:40:50.561580 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5677 00:40:50.564735 iDelay=208, Bit 9, Center 83 (-16 ~ 183) 200
5678 00:40:50.571701 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5679 00:40:50.574940 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5680 00:40:50.578156 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5681 00:40:50.581421 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5682 00:40:50.584420 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5683 00:40:50.591054 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5684 00:40:50.591135 ==
5685 00:40:50.594721 Dram Type= 6, Freq= 0, CH_1, rank 0
5686 00:40:50.598032 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5687 00:40:50.598159 ==
5688 00:40:50.598266 DQS Delay:
5689 00:40:50.601174 DQS0 = 0, DQS1 = 0
5690 00:40:50.601295 DQM Delay:
5691 00:40:50.604282 DQM0 = 101, DQM1 = 91
5692 00:40:50.604418 DQ Delay:
5693 00:40:50.607934 DQ0 =107, DQ1 =99, DQ2 =95, DQ3 =99
5694 00:40:50.611301 DQ4 =95, DQ5 =111, DQ6 =111, DQ7 =95
5695 00:40:50.614140 DQ8 =75, DQ9 =83, DQ10 =91, DQ11 =83
5696 00:40:50.617811 DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =99
5697 00:40:50.617962
5698 00:40:50.618068
5699 00:40:50.618184 ==
5700 00:40:50.620851 Dram Type= 6, Freq= 0, CH_1, rank 0
5701 00:40:50.627372 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5702 00:40:50.627549 ==
5703 00:40:50.627651
5704 00:40:50.627742
5705 00:40:50.627838 TX Vref Scan disable
5706 00:40:50.630759 == TX Byte 0 ==
5707 00:40:50.634019 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5708 00:40:50.637309 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5709 00:40:50.641408 == TX Byte 1 ==
5710 00:40:50.643868 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5711 00:40:50.650512 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5712 00:40:50.650671 ==
5713 00:40:50.653835 Dram Type= 6, Freq= 0, CH_1, rank 0
5714 00:40:50.656871 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5715 00:40:50.657047 ==
5716 00:40:50.657137
5717 00:40:50.657233
5718 00:40:50.660504 TX Vref Scan disable
5719 00:40:50.660592 == TX Byte 0 ==
5720 00:40:50.666866 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5721 00:40:50.670019 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5722 00:40:50.673817 == TX Byte 1 ==
5723 00:40:50.676848 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5724 00:40:50.680111 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5725 00:40:50.680203
5726 00:40:50.680276 [DATLAT]
5727 00:40:50.683214 Freq=933, CH1 RK0
5728 00:40:50.683373
5729 00:40:50.683480 DATLAT Default: 0xd
5730 00:40:50.686939 0, 0xFFFF, sum = 0
5731 00:40:50.690294 1, 0xFFFF, sum = 0
5732 00:40:50.690391 2, 0xFFFF, sum = 0
5733 00:40:50.693154 3, 0xFFFF, sum = 0
5734 00:40:50.693247 4, 0xFFFF, sum = 0
5735 00:40:50.696978 5, 0xFFFF, sum = 0
5736 00:40:50.697074 6, 0xFFFF, sum = 0
5737 00:40:50.700093 7, 0xFFFF, sum = 0
5738 00:40:50.700188 8, 0xFFFF, sum = 0
5739 00:40:50.703107 9, 0xFFFF, sum = 0
5740 00:40:50.703192 10, 0x0, sum = 1
5741 00:40:50.706767 11, 0x0, sum = 2
5742 00:40:50.706851 12, 0x0, sum = 3
5743 00:40:50.709944 13, 0x0, sum = 4
5744 00:40:50.710028 best_step = 11
5745 00:40:50.710108
5746 00:40:50.710184 ==
5747 00:40:50.713109 Dram Type= 6, Freq= 0, CH_1, rank 0
5748 00:40:50.716948 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5749 00:40:50.717036 ==
5750 00:40:50.719759 RX Vref Scan: 1
5751 00:40:50.719839
5752 00:40:50.723015 RX Vref 0 -> 0, step: 1
5753 00:40:50.723099
5754 00:40:50.723164 RX Delay -69 -> 252, step: 4
5755 00:40:50.726324
5756 00:40:50.726407 Set Vref, RX VrefLevel [Byte0]: 52
5757 00:40:50.729774 [Byte1]: 53
5758 00:40:50.734758
5759 00:40:50.734860 Final RX Vref Byte 0 = 52 to rank0
5760 00:40:50.738177 Final RX Vref Byte 1 = 53 to rank0
5761 00:40:50.741285 Final RX Vref Byte 0 = 52 to rank1
5762 00:40:50.744349 Final RX Vref Byte 1 = 53 to rank1==
5763 00:40:50.747767 Dram Type= 6, Freq= 0, CH_1, rank 0
5764 00:40:50.754102 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5765 00:40:50.754222 ==
5766 00:40:50.754290 DQS Delay:
5767 00:40:50.757838 DQS0 = 0, DQS1 = 0
5768 00:40:50.757949 DQM Delay:
5769 00:40:50.758043 DQM0 = 100, DQM1 = 93
5770 00:40:50.761109 DQ Delay:
5771 00:40:50.764073 DQ0 =104, DQ1 =98, DQ2 =92, DQ3 =98
5772 00:40:50.767865 DQ4 =96, DQ5 =110, DQ6 =110, DQ7 =96
5773 00:40:50.770988 DQ8 =80, DQ9 =84, DQ10 =92, DQ11 =86
5774 00:40:50.774314 DQ12 =100, DQ13 =100, DQ14 =100, DQ15 =104
5775 00:40:50.774397
5776 00:40:50.774464
5777 00:40:50.780881 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a0a, (MSB)MR19= 0x505, tDQSOscB0 = 418 ps tDQSOscB1 = 413 ps
5778 00:40:50.783871 CH1 RK0: MR19=505, MR18=1A0A
5779 00:40:50.790607 CH1_RK0: MR19=0x505, MR18=0x1A0A, DQSOSC=413, MR23=63, INC=63, DEC=42
5780 00:40:50.790713
5781 00:40:50.793859 ----->DramcWriteLeveling(PI) begin...
5782 00:40:50.793947 ==
5783 00:40:50.797316 Dram Type= 6, Freq= 0, CH_1, rank 1
5784 00:40:50.800533 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5785 00:40:50.804308 ==
5786 00:40:50.804398 Write leveling (Byte 0): 26 => 26
5787 00:40:50.806996 Write leveling (Byte 1): 29 => 29
5788 00:40:50.810559 DramcWriteLeveling(PI) end<-----
5789 00:40:50.810644
5790 00:40:50.810709 ==
5791 00:40:50.814017 Dram Type= 6, Freq= 0, CH_1, rank 1
5792 00:40:50.820411 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5793 00:40:50.820510 ==
5794 00:40:50.820577 [Gating] SW mode calibration
5795 00:40:50.830322 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5796 00:40:50.833933 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5797 00:40:50.840780 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5798 00:40:50.843901 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5799 00:40:50.846791 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5800 00:40:50.853468 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5801 00:40:50.857136 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5802 00:40:50.860071 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5803 00:40:50.863624 0 14 24 | B1->B0 | 3131 3434 | 1 1 | (1 0) (1 0)
5804 00:40:50.870440 0 14 28 | B1->B0 | 2d2d 3030 | 0 0 | (0 0) (0 0)
5805 00:40:50.873469 0 15 0 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
5806 00:40:50.877028 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5807 00:40:50.883194 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5808 00:40:50.886801 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5809 00:40:50.889624 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5810 00:40:50.896335 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5811 00:40:50.899968 0 15 24 | B1->B0 | 2e2e 2726 | 0 1 | (0 0) (0 0)
5812 00:40:50.903308 0 15 28 | B1->B0 | 3636 3333 | 0 0 | (0 0) (0 0)
5813 00:40:50.909936 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5814 00:40:50.912717 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5815 00:40:50.916691 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5816 00:40:50.922686 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5817 00:40:50.926177 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5818 00:40:50.929336 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5819 00:40:50.935986 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5820 00:40:50.939444 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5821 00:40:50.942689 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5822 00:40:50.949158 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5823 00:40:50.952627 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5824 00:40:50.955727 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5825 00:40:50.962762 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5826 00:40:50.966109 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5827 00:40:50.969300 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5828 00:40:50.975831 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5829 00:40:50.979116 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5830 00:40:50.982105 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5831 00:40:50.988678 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5832 00:40:50.992325 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5833 00:40:50.995600 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5834 00:40:51.002081 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5835 00:40:51.005269 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5836 00:40:51.008773 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5837 00:40:51.011983 Total UI for P1: 0, mck2ui 16
5838 00:40:51.014989 best dqsien dly found for B1: ( 1, 2, 26)
5839 00:40:51.022027 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5840 00:40:51.024954 Total UI for P1: 0, mck2ui 16
5841 00:40:51.028330 best dqsien dly found for B0: ( 1, 2, 28)
5842 00:40:51.031554 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5843 00:40:51.035372 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5844 00:40:51.035453
5845 00:40:51.038372 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5846 00:40:51.041528 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5847 00:40:51.045408 [Gating] SW calibration Done
5848 00:40:51.045487 ==
5849 00:40:51.048408 Dram Type= 6, Freq= 0, CH_1, rank 1
5850 00:40:51.051535 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5851 00:40:51.051615 ==
5852 00:40:51.054639 RX Vref Scan: 0
5853 00:40:51.054743
5854 00:40:51.058040 RX Vref 0 -> 0, step: 1
5855 00:40:51.058148
5856 00:40:51.058256 RX Delay -80 -> 252, step: 8
5857 00:40:51.064553 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5858 00:40:51.067827 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5859 00:40:51.071144 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5860 00:40:51.074857 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5861 00:40:51.077732 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5862 00:40:51.081196 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5863 00:40:51.087665 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5864 00:40:51.091400 iDelay=208, Bit 7, Center 99 (0 ~ 199) 200
5865 00:40:51.094153 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5866 00:40:51.097488 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5867 00:40:51.101228 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5868 00:40:51.107708 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5869 00:40:51.111290 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5870 00:40:51.114354 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5871 00:40:51.117684 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5872 00:40:51.121253 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5873 00:40:51.121333 ==
5874 00:40:51.124402 Dram Type= 6, Freq= 0, CH_1, rank 1
5875 00:40:51.131338 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5876 00:40:51.131420 ==
5877 00:40:51.131484 DQS Delay:
5878 00:40:51.133933 DQS0 = 0, DQS1 = 0
5879 00:40:51.134013 DQM Delay:
5880 00:40:51.137430 DQM0 = 100, DQM1 = 90
5881 00:40:51.137510 DQ Delay:
5882 00:40:51.140705 DQ0 =107, DQ1 =95, DQ2 =87, DQ3 =95
5883 00:40:51.144085 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =99
5884 00:40:51.147454 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =83
5885 00:40:51.150902 DQ12 =99, DQ13 =99, DQ14 =95, DQ15 =99
5886 00:40:51.150982
5887 00:40:51.151045
5888 00:40:51.151104 ==
5889 00:40:51.154077 Dram Type= 6, Freq= 0, CH_1, rank 1
5890 00:40:51.157402 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5891 00:40:51.157482 ==
5892 00:40:51.157545
5893 00:40:51.157604
5894 00:40:51.160888 TX Vref Scan disable
5895 00:40:51.163954 == TX Byte 0 ==
5896 00:40:51.167037 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5897 00:40:51.170302 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5898 00:40:51.173736 == TX Byte 1 ==
5899 00:40:51.177337 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5900 00:40:51.180398 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5901 00:40:51.180491 ==
5902 00:40:51.183937 Dram Type= 6, Freq= 0, CH_1, rank 1
5903 00:40:51.190310 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5904 00:40:51.190391 ==
5905 00:40:51.190456
5906 00:40:51.190515
5907 00:40:51.190572 TX Vref Scan disable
5908 00:40:51.194313 == TX Byte 0 ==
5909 00:40:51.197251 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5910 00:40:51.204039 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5911 00:40:51.204119 == TX Byte 1 ==
5912 00:40:51.207427 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5913 00:40:51.213735 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5914 00:40:51.213815
5915 00:40:51.213879 [DATLAT]
5916 00:40:51.213939 Freq=933, CH1 RK1
5917 00:40:51.213997
5918 00:40:51.217126 DATLAT Default: 0xb
5919 00:40:51.220452 0, 0xFFFF, sum = 0
5920 00:40:51.220541 1, 0xFFFF, sum = 0
5921 00:40:51.223624 2, 0xFFFF, sum = 0
5922 00:40:51.223704 3, 0xFFFF, sum = 0
5923 00:40:51.227081 4, 0xFFFF, sum = 0
5924 00:40:51.227162 5, 0xFFFF, sum = 0
5925 00:40:51.230198 6, 0xFFFF, sum = 0
5926 00:40:51.230312 7, 0xFFFF, sum = 0
5927 00:40:51.233582 8, 0xFFFF, sum = 0
5928 00:40:51.233663 9, 0xFFFF, sum = 0
5929 00:40:51.236810 10, 0x0, sum = 1
5930 00:40:51.236892 11, 0x0, sum = 2
5931 00:40:51.240736 12, 0x0, sum = 3
5932 00:40:51.240816 13, 0x0, sum = 4
5933 00:40:51.240882 best_step = 11
5934 00:40:51.243744
5935 00:40:51.243823 ==
5936 00:40:51.247262 Dram Type= 6, Freq= 0, CH_1, rank 1
5937 00:40:51.250067 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5938 00:40:51.250148 ==
5939 00:40:51.250254 RX Vref Scan: 0
5940 00:40:51.250315
5941 00:40:51.253671 RX Vref 0 -> 0, step: 1
5942 00:40:51.253750
5943 00:40:51.256736 RX Delay -61 -> 252, step: 4
5944 00:40:51.263766 iDelay=207, Bit 0, Center 104 (15 ~ 194) 180
5945 00:40:51.267043 iDelay=207, Bit 1, Center 94 (7 ~ 182) 176
5946 00:40:51.270192 iDelay=207, Bit 2, Center 90 (3 ~ 178) 176
5947 00:40:51.273553 iDelay=207, Bit 3, Center 98 (15 ~ 182) 168
5948 00:40:51.276591 iDelay=207, Bit 4, Center 100 (7 ~ 194) 188
5949 00:40:51.279942 iDelay=207, Bit 5, Center 112 (23 ~ 202) 180
5950 00:40:51.286649 iDelay=207, Bit 6, Center 112 (19 ~ 206) 188
5951 00:40:51.289931 iDelay=207, Bit 7, Center 98 (7 ~ 190) 184
5952 00:40:51.293149 iDelay=207, Bit 8, Center 84 (-5 ~ 174) 180
5953 00:40:51.296440 iDelay=207, Bit 9, Center 84 (-5 ~ 174) 180
5954 00:40:51.299597 iDelay=207, Bit 10, Center 94 (3 ~ 186) 184
5955 00:40:51.306075 iDelay=207, Bit 11, Center 84 (-5 ~ 174) 180
5956 00:40:51.309569 iDelay=207, Bit 12, Center 100 (7 ~ 194) 188
5957 00:40:51.312676 iDelay=207, Bit 13, Center 98 (7 ~ 190) 184
5958 00:40:51.316286 iDelay=207, Bit 14, Center 102 (15 ~ 190) 176
5959 00:40:51.319609 iDelay=207, Bit 15, Center 104 (15 ~ 194) 180
5960 00:40:51.322727 ==
5961 00:40:51.322807 Dram Type= 6, Freq= 0, CH_1, rank 1
5962 00:40:51.329298 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5963 00:40:51.329378 ==
5964 00:40:51.329443 DQS Delay:
5965 00:40:51.332820 DQS0 = 0, DQS1 = 0
5966 00:40:51.332900 DQM Delay:
5967 00:40:51.335955 DQM0 = 101, DQM1 = 93
5968 00:40:51.336034 DQ Delay:
5969 00:40:51.339418 DQ0 =104, DQ1 =94, DQ2 =90, DQ3 =98
5970 00:40:51.342510 DQ4 =100, DQ5 =112, DQ6 =112, DQ7 =98
5971 00:40:51.345648 DQ8 =84, DQ9 =84, DQ10 =94, DQ11 =84
5972 00:40:51.349532 DQ12 =100, DQ13 =98, DQ14 =102, DQ15 =104
5973 00:40:51.349612
5974 00:40:51.349674
5975 00:40:51.355601 [DQSOSCAuto] RK1, (LSB)MR18= 0xa03, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 418 ps
5976 00:40:51.359043 CH1 RK1: MR19=505, MR18=A03
5977 00:40:51.365604 CH1_RK1: MR19=0x505, MR18=0xA03, DQSOSC=418, MR23=63, INC=62, DEC=41
5978 00:40:51.368948 [RxdqsGatingPostProcess] freq 933
5979 00:40:51.375689 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5980 00:40:51.379066 best DQS0 dly(2T, 0.5T) = (0, 10)
5981 00:40:51.382442 best DQS1 dly(2T, 0.5T) = (0, 10)
5982 00:40:51.385178 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5983 00:40:51.388693 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5984 00:40:51.388772 best DQS0 dly(2T, 0.5T) = (0, 10)
5985 00:40:51.392097 best DQS1 dly(2T, 0.5T) = (0, 10)
5986 00:40:51.395171 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5987 00:40:51.398338 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5988 00:40:51.401729 Pre-setting of DQS Precalculation
5989 00:40:51.408350 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5990 00:40:51.415019 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5991 00:40:51.421621 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5992 00:40:51.421700
5993 00:40:51.421764
5994 00:40:51.425163 [Calibration Summary] 1866 Mbps
5995 00:40:51.425274 CH 0, Rank 0
5996 00:40:51.428486 SW Impedance : PASS
5997 00:40:51.431435 DUTY Scan : NO K
5998 00:40:51.431515 ZQ Calibration : PASS
5999 00:40:51.434985 Jitter Meter : NO K
6000 00:40:51.438141 CBT Training : PASS
6001 00:40:51.438259 Write leveling : PASS
6002 00:40:51.441355 RX DQS gating : PASS
6003 00:40:51.444840 RX DQ/DQS(RDDQC) : PASS
6004 00:40:51.444919 TX DQ/DQS : PASS
6005 00:40:51.448103 RX DATLAT : PASS
6006 00:40:51.451521 RX DQ/DQS(Engine): PASS
6007 00:40:51.451599 TX OE : NO K
6008 00:40:51.454754 All Pass.
6009 00:40:51.454833
6010 00:40:51.454896 CH 0, Rank 1
6011 00:40:51.457973 SW Impedance : PASS
6012 00:40:51.458052 DUTY Scan : NO K
6013 00:40:51.461085 ZQ Calibration : PASS
6014 00:40:51.464728 Jitter Meter : NO K
6015 00:40:51.464808 CBT Training : PASS
6016 00:40:51.467651 Write leveling : PASS
6017 00:40:51.471054 RX DQS gating : PASS
6018 00:40:51.471133 RX DQ/DQS(RDDQC) : PASS
6019 00:40:51.474407 TX DQ/DQS : PASS
6020 00:40:51.477738 RX DATLAT : PASS
6021 00:40:51.477817 RX DQ/DQS(Engine): PASS
6022 00:40:51.480744 TX OE : NO K
6023 00:40:51.480830 All Pass.
6024 00:40:51.480893
6025 00:40:51.484334 CH 1, Rank 0
6026 00:40:51.484415 SW Impedance : PASS
6027 00:40:51.487805 DUTY Scan : NO K
6028 00:40:51.490848 ZQ Calibration : PASS
6029 00:40:51.490928 Jitter Meter : NO K
6030 00:40:51.493967 CBT Training : PASS
6031 00:40:51.494047 Write leveling : PASS
6032 00:40:51.497317 RX DQS gating : PASS
6033 00:40:51.500953 RX DQ/DQS(RDDQC) : PASS
6034 00:40:51.501033 TX DQ/DQS : PASS
6035 00:40:51.504423 RX DATLAT : PASS
6036 00:40:51.507190 RX DQ/DQS(Engine): PASS
6037 00:40:51.507270 TX OE : NO K
6038 00:40:51.510561 All Pass.
6039 00:40:51.510641
6040 00:40:51.510719 CH 1, Rank 1
6041 00:40:51.513906 SW Impedance : PASS
6042 00:40:51.513985 DUTY Scan : NO K
6043 00:40:51.517569 ZQ Calibration : PASS
6044 00:40:51.521111 Jitter Meter : NO K
6045 00:40:51.521192 CBT Training : PASS
6046 00:40:51.524188 Write leveling : PASS
6047 00:40:51.527376 RX DQS gating : PASS
6048 00:40:51.527456 RX DQ/DQS(RDDQC) : PASS
6049 00:40:51.530510 TX DQ/DQS : PASS
6050 00:40:51.533745 RX DATLAT : PASS
6051 00:40:51.533825 RX DQ/DQS(Engine): PASS
6052 00:40:51.537193 TX OE : NO K
6053 00:40:51.537275 All Pass.
6054 00:40:51.537339
6055 00:40:51.540590 DramC Write-DBI off
6056 00:40:51.544082 PER_BANK_REFRESH: Hybrid Mode
6057 00:40:51.544176 TX_TRACKING: ON
6058 00:40:51.553511 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6059 00:40:51.557011 [FAST_K] Save calibration result to emmc
6060 00:40:51.560378 dramc_set_vcore_voltage set vcore to 650000
6061 00:40:51.563525 Read voltage for 400, 6
6062 00:40:51.563605 Vio18 = 0
6063 00:40:51.563669 Vcore = 650000
6064 00:40:51.566735 Vdram = 0
6065 00:40:51.566815 Vddq = 0
6066 00:40:51.566880 Vmddr = 0
6067 00:40:51.573584 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6068 00:40:51.577133 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6069 00:40:51.580241 MEM_TYPE=3, freq_sel=20
6070 00:40:51.583606 sv_algorithm_assistance_LP4_800
6071 00:40:51.586811 ============ PULL DRAM RESETB DOWN ============
6072 00:40:51.589946 ========== PULL DRAM RESETB DOWN end =========
6073 00:40:51.596862 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6074 00:40:51.600448 ===================================
6075 00:40:51.600529 LPDDR4 DRAM CONFIGURATION
6076 00:40:51.603068 ===================================
6077 00:40:51.606619 EX_ROW_EN[0] = 0x0
6078 00:40:51.609964 EX_ROW_EN[1] = 0x0
6079 00:40:51.610069 LP4Y_EN = 0x0
6080 00:40:51.613382 WORK_FSP = 0x0
6081 00:40:51.613471 WL = 0x2
6082 00:40:51.616603 RL = 0x2
6083 00:40:51.616683 BL = 0x2
6084 00:40:51.619714 RPST = 0x0
6085 00:40:51.619794 RD_PRE = 0x0
6086 00:40:51.623352 WR_PRE = 0x1
6087 00:40:51.623432 WR_PST = 0x0
6088 00:40:51.626411 DBI_WR = 0x0
6089 00:40:51.626491 DBI_RD = 0x0
6090 00:40:51.629752 OTF = 0x1
6091 00:40:51.633326 ===================================
6092 00:40:51.636833 ===================================
6093 00:40:51.636949 ANA top config
6094 00:40:51.639473 ===================================
6095 00:40:51.642804 DLL_ASYNC_EN = 0
6096 00:40:51.646070 ALL_SLAVE_EN = 1
6097 00:40:51.649265 NEW_RANK_MODE = 1
6098 00:40:51.652826 DLL_IDLE_MODE = 1
6099 00:40:51.652905 LP45_APHY_COMB_EN = 1
6100 00:40:51.655898 TX_ODT_DIS = 1
6101 00:40:51.659539 NEW_8X_MODE = 1
6102 00:40:51.662556 ===================================
6103 00:40:51.665980 ===================================
6104 00:40:51.669297 data_rate = 800
6105 00:40:51.672590 CKR = 1
6106 00:40:51.672670 DQ_P2S_RATIO = 4
6107 00:40:51.675795 ===================================
6108 00:40:51.679119 CA_P2S_RATIO = 4
6109 00:40:51.682318 DQ_CA_OPEN = 0
6110 00:40:51.685686 DQ_SEMI_OPEN = 1
6111 00:40:51.689164 CA_SEMI_OPEN = 1
6112 00:40:51.692009 CA_FULL_RATE = 0
6113 00:40:51.692089 DQ_CKDIV4_EN = 0
6114 00:40:51.695850 CA_CKDIV4_EN = 1
6115 00:40:51.699122 CA_PREDIV_EN = 0
6116 00:40:51.702003 PH8_DLY = 0
6117 00:40:51.706043 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6118 00:40:51.708562 DQ_AAMCK_DIV = 0
6119 00:40:51.708662 CA_AAMCK_DIV = 0
6120 00:40:51.712055 CA_ADMCK_DIV = 4
6121 00:40:51.715370 DQ_TRACK_CA_EN = 0
6122 00:40:51.718639 CA_PICK = 800
6123 00:40:51.722305 CA_MCKIO = 400
6124 00:40:51.725132 MCKIO_SEMI = 400
6125 00:40:51.728589 PLL_FREQ = 3016
6126 00:40:51.731900 DQ_UI_PI_RATIO = 32
6127 00:40:51.731980 CA_UI_PI_RATIO = 32
6128 00:40:51.735159 ===================================
6129 00:40:51.738474 ===================================
6130 00:40:51.741645 memory_type:LPDDR4
6131 00:40:51.744894 GP_NUM : 10
6132 00:40:51.744999 SRAM_EN : 1
6133 00:40:51.748586 MD32_EN : 0
6134 00:40:51.751707 ===================================
6135 00:40:51.754964 [ANA_INIT] >>>>>>>>>>>>>>
6136 00:40:51.758407 <<<<<< [CONFIGURE PHASE]: ANA_TX
6137 00:40:51.761386 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6138 00:40:51.764601 ===================================
6139 00:40:51.764701 data_rate = 800,PCW = 0X7400
6140 00:40:51.768207 ===================================
6141 00:40:51.771381 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6142 00:40:51.778041 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6143 00:40:51.791338 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6144 00:40:51.794297 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6145 00:40:51.798058 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6146 00:40:51.800931 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6147 00:40:51.804414 [ANA_INIT] flow start
6148 00:40:51.804494 [ANA_INIT] PLL >>>>>>>>
6149 00:40:51.807401 [ANA_INIT] PLL <<<<<<<<
6150 00:40:51.810915 [ANA_INIT] MIDPI >>>>>>>>
6151 00:40:51.814131 [ANA_INIT] MIDPI <<<<<<<<
6152 00:40:51.814258 [ANA_INIT] DLL >>>>>>>>
6153 00:40:51.817461 [ANA_INIT] flow end
6154 00:40:51.821017 ============ LP4 DIFF to SE enter ============
6155 00:40:51.824352 ============ LP4 DIFF to SE exit ============
6156 00:40:51.827579 [ANA_INIT] <<<<<<<<<<<<<
6157 00:40:51.830421 [Flow] Enable top DCM control >>>>>
6158 00:40:51.834093 [Flow] Enable top DCM control <<<<<
6159 00:40:51.837171 Enable DLL master slave shuffle
6160 00:40:51.844018 ==============================================================
6161 00:40:51.844106 Gating Mode config
6162 00:40:51.850553 ==============================================================
6163 00:40:51.850632 Config description:
6164 00:40:51.860268 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6165 00:40:51.866999 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6166 00:40:51.873782 SELPH_MODE 0: By rank 1: By Phase
6167 00:40:51.876820 ==============================================================
6168 00:40:51.880397 GAT_TRACK_EN = 0
6169 00:40:51.883742 RX_GATING_MODE = 2
6170 00:40:51.886979 RX_GATING_TRACK_MODE = 2
6171 00:40:51.890431 SELPH_MODE = 1
6172 00:40:51.893428 PICG_EARLY_EN = 1
6173 00:40:51.896821 VALID_LAT_VALUE = 1
6174 00:40:51.903367 ==============================================================
6175 00:40:51.906840 Enter into Gating configuration >>>>
6176 00:40:51.910356 Exit from Gating configuration <<<<
6177 00:40:51.913276 Enter into DVFS_PRE_config >>>>>
6178 00:40:51.922840 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6179 00:40:51.926645 Exit from DVFS_PRE_config <<<<<
6180 00:40:51.929940 Enter into PICG configuration >>>>
6181 00:40:51.932773 Exit from PICG configuration <<<<
6182 00:40:51.936606 [RX_INPUT] configuration >>>>>
6183 00:40:51.936687 [RX_INPUT] configuration <<<<<
6184 00:40:51.942653 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6185 00:40:51.949592 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6186 00:40:51.955931 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6187 00:40:51.959613 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6188 00:40:51.965587 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6189 00:40:51.972471 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6190 00:40:51.975688 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6191 00:40:51.982441 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6192 00:40:51.985621 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6193 00:40:51.989038 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6194 00:40:51.992325 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6195 00:40:51.998781 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6196 00:40:52.002112 ===================================
6197 00:40:52.002247 LPDDR4 DRAM CONFIGURATION
6198 00:40:52.005604 ===================================
6199 00:40:52.009017 EX_ROW_EN[0] = 0x0
6200 00:40:52.012225 EX_ROW_EN[1] = 0x0
6201 00:40:52.012304 LP4Y_EN = 0x0
6202 00:40:52.015050 WORK_FSP = 0x0
6203 00:40:52.015130 WL = 0x2
6204 00:40:52.018421 RL = 0x2
6205 00:40:52.018501 BL = 0x2
6206 00:40:52.021997 RPST = 0x0
6207 00:40:52.022076 RD_PRE = 0x0
6208 00:40:52.025266 WR_PRE = 0x1
6209 00:40:52.025345 WR_PST = 0x0
6210 00:40:52.028071 DBI_WR = 0x0
6211 00:40:52.028150 DBI_RD = 0x0
6212 00:40:52.031704 OTF = 0x1
6213 00:40:52.035018 ===================================
6214 00:40:52.038429 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6215 00:40:52.041522 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6216 00:40:52.048369 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6217 00:40:52.051202 ===================================
6218 00:40:52.054701 LPDDR4 DRAM CONFIGURATION
6219 00:40:52.057775 ===================================
6220 00:40:52.057855 EX_ROW_EN[0] = 0x10
6221 00:40:52.061255 EX_ROW_EN[1] = 0x0
6222 00:40:52.061335 LP4Y_EN = 0x0
6223 00:40:52.064462 WORK_FSP = 0x0
6224 00:40:52.064541 WL = 0x2
6225 00:40:52.067872 RL = 0x2
6226 00:40:52.067951 BL = 0x2
6227 00:40:52.070756 RPST = 0x0
6228 00:40:52.070838 RD_PRE = 0x0
6229 00:40:52.074105 WR_PRE = 0x1
6230 00:40:52.074238 WR_PST = 0x0
6231 00:40:52.077727 DBI_WR = 0x0
6232 00:40:52.080897 DBI_RD = 0x0
6233 00:40:52.080977 OTF = 0x1
6234 00:40:52.084613 ===================================
6235 00:40:52.090668 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6236 00:40:52.094294 nWR fixed to 30
6237 00:40:52.097611 [ModeRegInit_LP4] CH0 RK0
6238 00:40:52.097691 [ModeRegInit_LP4] CH0 RK1
6239 00:40:52.101179 [ModeRegInit_LP4] CH1 RK0
6240 00:40:52.104195 [ModeRegInit_LP4] CH1 RK1
6241 00:40:52.104275 match AC timing 19
6242 00:40:52.110690 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6243 00:40:52.113913 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6244 00:40:52.117528 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6245 00:40:52.124190 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6246 00:40:52.127033 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6247 00:40:52.127114 ==
6248 00:40:52.130575 Dram Type= 6, Freq= 0, CH_0, rank 0
6249 00:40:52.133986 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6250 00:40:52.134065 ==
6251 00:40:52.140354 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6252 00:40:52.146994 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6253 00:40:52.150389 [CA 0] Center 36 (8~64) winsize 57
6254 00:40:52.153580 [CA 1] Center 36 (8~64) winsize 57
6255 00:40:52.156700 [CA 2] Center 36 (8~64) winsize 57
6256 00:40:52.159917 [CA 3] Center 36 (8~64) winsize 57
6257 00:40:52.163250 [CA 4] Center 36 (8~64) winsize 57
6258 00:40:52.166708 [CA 5] Center 36 (8~64) winsize 57
6259 00:40:52.166812
6260 00:40:52.170059 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6261 00:40:52.170168
6262 00:40:52.173432 [CATrainingPosCal] consider 1 rank data
6263 00:40:52.176747 u2DelayCellTimex100 = 270/100 ps
6264 00:40:52.179701 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6265 00:40:52.182965 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6266 00:40:52.186813 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6267 00:40:52.190337 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6268 00:40:52.193346 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6269 00:40:52.196748 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6270 00:40:52.196850
6271 00:40:52.203145 CA PerBit enable=1, Macro0, CA PI delay=36
6272 00:40:52.203248
6273 00:40:52.203338 [CBTSetCACLKResult] CA Dly = 36
6274 00:40:52.206334 CS Dly: 1 (0~32)
6275 00:40:52.206412 ==
6276 00:40:52.209890 Dram Type= 6, Freq= 0, CH_0, rank 1
6277 00:40:52.212669 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6278 00:40:52.212756 ==
6279 00:40:52.219341 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6280 00:40:52.226006 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6281 00:40:52.229379 [CA 0] Center 36 (8~64) winsize 57
6282 00:40:52.232701 [CA 1] Center 36 (8~64) winsize 57
6283 00:40:52.239601 [CA 2] Center 36 (8~64) winsize 57
6284 00:40:52.239684 [CA 3] Center 36 (8~64) winsize 57
6285 00:40:52.242456 [CA 4] Center 36 (8~64) winsize 57
6286 00:40:52.242537 [CA 5] Center 36 (8~64) winsize 57
6287 00:40:52.242601
6288 00:40:52.251977 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6289 00:40:52.252072
6290 00:40:52.252688 [CATrainingPosCal] consider 2 rank data
6291 00:40:52.255796 u2DelayCellTimex100 = 270/100 ps
6292 00:40:52.259357 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6293 00:40:52.262338 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6294 00:40:52.265791 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6295 00:40:52.269020 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6296 00:40:52.272276 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6297 00:40:52.275374 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6298 00:40:52.275453
6299 00:40:52.278834 CA PerBit enable=1, Macro0, CA PI delay=36
6300 00:40:52.278914
6301 00:40:52.282295 [CBTSetCACLKResult] CA Dly = 36
6302 00:40:52.285552 CS Dly: 1 (0~32)
6303 00:40:52.285631
6304 00:40:52.288680 ----->DramcWriteLeveling(PI) begin...
6305 00:40:52.288761 ==
6306 00:40:52.292348 Dram Type= 6, Freq= 0, CH_0, rank 0
6307 00:40:52.295510 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6308 00:40:52.295590 ==
6309 00:40:52.298850 Write leveling (Byte 0): 40 => 8
6310 00:40:52.301886 Write leveling (Byte 1): 32 => 0
6311 00:40:52.305342 DramcWriteLeveling(PI) end<-----
6312 00:40:52.305421
6313 00:40:52.305484 ==
6314 00:40:52.308781 Dram Type= 6, Freq= 0, CH_0, rank 0
6315 00:40:52.311877 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6316 00:40:52.311957 ==
6317 00:40:52.315610 [Gating] SW mode calibration
6318 00:40:52.322013 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6319 00:40:52.328915 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6320 00:40:52.331642 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6321 00:40:52.338721 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6322 00:40:52.341837 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6323 00:40:52.344902 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6324 00:40:52.351677 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6325 00:40:52.354664 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6326 00:40:52.358035 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6327 00:40:52.364823 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6328 00:40:52.368059 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6329 00:40:52.371356 Total UI for P1: 0, mck2ui 16
6330 00:40:52.375133 best dqsien dly found for B0: ( 0, 14, 24)
6331 00:40:52.377685 Total UI for P1: 0, mck2ui 16
6332 00:40:52.381157 best dqsien dly found for B1: ( 0, 14, 24)
6333 00:40:52.384466 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6334 00:40:52.387578 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6335 00:40:52.387654
6336 00:40:52.391215 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6337 00:40:52.394755 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6338 00:40:52.397579 [Gating] SW calibration Done
6339 00:40:52.397684 ==
6340 00:40:52.401149 Dram Type= 6, Freq= 0, CH_0, rank 0
6341 00:40:52.404684 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6342 00:40:52.407808 ==
6343 00:40:52.407906 RX Vref Scan: 0
6344 00:40:52.407994
6345 00:40:52.410993 RX Vref 0 -> 0, step: 1
6346 00:40:52.411101
6347 00:40:52.414099 RX Delay -410 -> 252, step: 16
6348 00:40:52.417489 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6349 00:40:52.420925 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6350 00:40:52.427202 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6351 00:40:52.430710 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6352 00:40:52.434046 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6353 00:40:52.437570 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6354 00:40:52.440729 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6355 00:40:52.447427 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6356 00:40:52.450146 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6357 00:40:52.453587 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6358 00:40:52.460079 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6359 00:40:52.463371 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6360 00:40:52.466647 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6361 00:40:52.470037 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6362 00:40:52.477125 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6363 00:40:52.480068 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6364 00:40:52.480160 ==
6365 00:40:52.483404 Dram Type= 6, Freq= 0, CH_0, rank 0
6366 00:40:52.487046 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6367 00:40:52.487155 ==
6368 00:40:52.489774 DQS Delay:
6369 00:40:52.489853 DQS0 = 43, DQS1 = 59
6370 00:40:52.493306 DQM Delay:
6371 00:40:52.493386 DQM0 = 10, DQM1 = 11
6372 00:40:52.493450 DQ Delay:
6373 00:40:52.496514 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6374 00:40:52.499834 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6375 00:40:52.503189 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6376 00:40:52.506431 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6377 00:40:52.506505
6378 00:40:52.506572
6379 00:40:52.506634 ==
6380 00:40:52.509696 Dram Type= 6, Freq= 0, CH_0, rank 0
6381 00:40:52.516472 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6382 00:40:52.516577 ==
6383 00:40:52.516667
6384 00:40:52.516752
6385 00:40:52.516841 TX Vref Scan disable
6386 00:40:52.519793 == TX Byte 0 ==
6387 00:40:52.522754 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6388 00:40:52.526044 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6389 00:40:52.529182 == TX Byte 1 ==
6390 00:40:52.532582 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6391 00:40:52.539373 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6392 00:40:52.539477 ==
6393 00:40:52.542955 Dram Type= 6, Freq= 0, CH_0, rank 0
6394 00:40:52.545931 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6395 00:40:52.546035 ==
6396 00:40:52.546155
6397 00:40:52.546275
6398 00:40:52.549053 TX Vref Scan disable
6399 00:40:52.549152 == TX Byte 0 ==
6400 00:40:52.552713 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6401 00:40:52.559069 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6402 00:40:52.559153 == TX Byte 1 ==
6403 00:40:52.562226 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6404 00:40:52.568765 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6405 00:40:52.568869
6406 00:40:52.568967 [DATLAT]
6407 00:40:52.572053 Freq=400, CH0 RK0
6408 00:40:52.572156
6409 00:40:52.572253 DATLAT Default: 0xf
6410 00:40:52.575373 0, 0xFFFF, sum = 0
6411 00:40:52.575471 1, 0xFFFF, sum = 0
6412 00:40:52.578907 2, 0xFFFF, sum = 0
6413 00:40:52.579003 3, 0xFFFF, sum = 0
6414 00:40:52.582152 4, 0xFFFF, sum = 0
6415 00:40:52.582261 5, 0xFFFF, sum = 0
6416 00:40:52.585528 6, 0xFFFF, sum = 0
6417 00:40:52.585599 7, 0xFFFF, sum = 0
6418 00:40:52.588831 8, 0xFFFF, sum = 0
6419 00:40:52.588933 9, 0xFFFF, sum = 0
6420 00:40:52.592045 10, 0xFFFF, sum = 0
6421 00:40:52.592144 11, 0xFFFF, sum = 0
6422 00:40:52.595525 12, 0xFFFF, sum = 0
6423 00:40:52.595629 13, 0x0, sum = 1
6424 00:40:52.599008 14, 0x0, sum = 2
6425 00:40:52.599097 15, 0x0, sum = 3
6426 00:40:52.602121 16, 0x0, sum = 4
6427 00:40:52.602227 best_step = 14
6428 00:40:52.602292
6429 00:40:52.602352 ==
6430 00:40:52.605019 Dram Type= 6, Freq= 0, CH_0, rank 0
6431 00:40:52.612063 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6432 00:40:52.612170 ==
6433 00:40:52.612269 RX Vref Scan: 1
6434 00:40:52.612367
6435 00:40:52.614942 RX Vref 0 -> 0, step: 1
6436 00:40:52.615026
6437 00:40:52.618105 RX Delay -359 -> 252, step: 8
6438 00:40:52.618235
6439 00:40:52.621893 Set Vref, RX VrefLevel [Byte0]: 60
6440 00:40:52.624820 [Byte1]: 49
6441 00:40:52.628215
6442 00:40:52.628314 Final RX Vref Byte 0 = 60 to rank0
6443 00:40:52.631881 Final RX Vref Byte 1 = 49 to rank0
6444 00:40:52.634673 Final RX Vref Byte 0 = 60 to rank1
6445 00:40:52.637951 Final RX Vref Byte 1 = 49 to rank1==
6446 00:40:52.641880 Dram Type= 6, Freq= 0, CH_0, rank 0
6447 00:40:52.648299 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6448 00:40:52.648404 ==
6449 00:40:52.648504 DQS Delay:
6450 00:40:52.651424 DQS0 = 48, DQS1 = 60
6451 00:40:52.651525 DQM Delay:
6452 00:40:52.651627 DQM0 = 11, DQM1 = 12
6453 00:40:52.655143 DQ Delay:
6454 00:40:52.657679 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8
6455 00:40:52.661020 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6456 00:40:52.664411 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =4
6457 00:40:52.667719 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6458 00:40:52.667818
6459 00:40:52.667915
6460 00:40:52.674358 [DQSOSCAuto] RK0, (LSB)MR18= 0xc385, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 385 ps
6461 00:40:52.677550 CH0 RK0: MR19=C0C, MR18=C385
6462 00:40:52.684272 CH0_RK0: MR19=0xC0C, MR18=0xC385, DQSOSC=385, MR23=63, INC=398, DEC=265
6463 00:40:52.684377 ==
6464 00:40:52.687584 Dram Type= 6, Freq= 0, CH_0, rank 1
6465 00:40:52.690509 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6466 00:40:52.690590 ==
6467 00:40:52.693913 [Gating] SW mode calibration
6468 00:40:52.700564 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6469 00:40:52.707185 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6470 00:40:52.710832 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6471 00:40:52.713708 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6472 00:40:52.720559 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6473 00:40:52.723908 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6474 00:40:52.727098 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6475 00:40:52.733563 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6476 00:40:52.736927 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6477 00:40:52.740088 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6478 00:40:52.746888 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6479 00:40:52.750522 Total UI for P1: 0, mck2ui 16
6480 00:40:52.753370 best dqsien dly found for B0: ( 0, 14, 24)
6481 00:40:52.756538 Total UI for P1: 0, mck2ui 16
6482 00:40:52.760424 best dqsien dly found for B1: ( 0, 14, 24)
6483 00:40:52.763427 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6484 00:40:52.766489 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6485 00:40:52.766560
6486 00:40:52.770382 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6487 00:40:52.773248 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6488 00:40:52.776527 [Gating] SW calibration Done
6489 00:40:52.776622 ==
6490 00:40:52.780061 Dram Type= 6, Freq= 0, CH_0, rank 1
6491 00:40:52.783083 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6492 00:40:52.783182 ==
6493 00:40:52.786476 RX Vref Scan: 0
6494 00:40:52.786574
6495 00:40:52.789732 RX Vref 0 -> 0, step: 1
6496 00:40:52.789826
6497 00:40:52.789916 RX Delay -410 -> 252, step: 16
6498 00:40:52.796794 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6499 00:40:52.800232 iDelay=230, Bit 1, Center -27 (-282 ~ 229) 512
6500 00:40:52.803124 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6501 00:40:52.809753 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6502 00:40:52.813122 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6503 00:40:52.816179 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6504 00:40:52.819773 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6505 00:40:52.826032 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6506 00:40:52.829461 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6507 00:40:52.832733 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6508 00:40:52.836268 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6509 00:40:52.842786 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6510 00:40:52.845950 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6511 00:40:52.849471 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6512 00:40:52.852986 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6513 00:40:52.859183 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6514 00:40:52.859281 ==
6515 00:40:52.862523 Dram Type= 6, Freq= 0, CH_0, rank 1
6516 00:40:52.865615 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6517 00:40:52.865715 ==
6518 00:40:52.865805 DQS Delay:
6519 00:40:52.869144 DQS0 = 43, DQS1 = 51
6520 00:40:52.869239 DQM Delay:
6521 00:40:52.872060 DQM0 = 9, DQM1 = 9
6522 00:40:52.872156 DQ Delay:
6523 00:40:52.875800 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =0
6524 00:40:52.879133 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6525 00:40:52.882063 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6526 00:40:52.885069 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6527 00:40:52.885165
6528 00:40:52.885254
6529 00:40:52.885339 ==
6530 00:40:52.888412 Dram Type= 6, Freq= 0, CH_0, rank 1
6531 00:40:52.892171 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6532 00:40:52.892267 ==
6533 00:40:52.895466
6534 00:40:52.895564
6535 00:40:52.895654 TX Vref Scan disable
6536 00:40:52.898851 == TX Byte 0 ==
6537 00:40:52.901984 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6538 00:40:52.904991 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6539 00:40:52.908438 == TX Byte 1 ==
6540 00:40:52.911820 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6541 00:40:52.915389 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6542 00:40:52.915485 ==
6543 00:40:52.918358 Dram Type= 6, Freq= 0, CH_0, rank 1
6544 00:40:52.921593 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6545 00:40:52.924892 ==
6546 00:40:52.924977
6547 00:40:52.925040
6548 00:40:52.925098 TX Vref Scan disable
6549 00:40:52.928350 == TX Byte 0 ==
6550 00:40:52.931522 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6551 00:40:52.935314 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6552 00:40:52.938505 == TX Byte 1 ==
6553 00:40:52.941414 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6554 00:40:52.944740 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6555 00:40:52.944820
6556 00:40:52.948080 [DATLAT]
6557 00:40:52.948158 Freq=400, CH0 RK1
6558 00:40:52.948221
6559 00:40:52.951292 DATLAT Default: 0xe
6560 00:40:52.951370 0, 0xFFFF, sum = 0
6561 00:40:52.954547 1, 0xFFFF, sum = 0
6562 00:40:52.954655 2, 0xFFFF, sum = 0
6563 00:40:52.957989 3, 0xFFFF, sum = 0
6564 00:40:52.958068 4, 0xFFFF, sum = 0
6565 00:40:52.961070 5, 0xFFFF, sum = 0
6566 00:40:52.961150 6, 0xFFFF, sum = 0
6567 00:40:52.964664 7, 0xFFFF, sum = 0
6568 00:40:52.964743 8, 0xFFFF, sum = 0
6569 00:40:52.968021 9, 0xFFFF, sum = 0
6570 00:40:52.968100 10, 0xFFFF, sum = 0
6571 00:40:52.971381 11, 0xFFFF, sum = 0
6572 00:40:52.974112 12, 0xFFFF, sum = 0
6573 00:40:52.974228 13, 0x0, sum = 1
6574 00:40:52.974292 14, 0x0, sum = 2
6575 00:40:52.977522 15, 0x0, sum = 3
6576 00:40:52.977602 16, 0x0, sum = 4
6577 00:40:52.981150 best_step = 14
6578 00:40:52.981228
6579 00:40:52.981290 ==
6580 00:40:52.984262 Dram Type= 6, Freq= 0, CH_0, rank 1
6581 00:40:52.987815 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6582 00:40:52.987919 ==
6583 00:40:52.990783 RX Vref Scan: 0
6584 00:40:52.990860
6585 00:40:52.990922 RX Vref 0 -> 0, step: 1
6586 00:40:52.990980
6587 00:40:52.994196 RX Delay -343 -> 252, step: 8
6588 00:40:53.002356 iDelay=217, Bit 0, Center -40 (-279 ~ 200) 480
6589 00:40:53.005682 iDelay=217, Bit 1, Center -36 (-279 ~ 208) 488
6590 00:40:53.009235 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6591 00:40:53.012294 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6592 00:40:53.018844 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6593 00:40:53.022390 iDelay=217, Bit 5, Center -44 (-287 ~ 200) 488
6594 00:40:53.025537 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6595 00:40:53.028827 iDelay=217, Bit 7, Center -28 (-271 ~ 216) 488
6596 00:40:53.035414 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
6597 00:40:53.038775 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6598 00:40:53.041930 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6599 00:40:53.048749 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6600 00:40:53.052209 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6601 00:40:53.055405 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6602 00:40:53.058499 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6603 00:40:53.065219 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6604 00:40:53.065297 ==
6605 00:40:53.068680 Dram Type= 6, Freq= 0, CH_0, rank 1
6606 00:40:53.072000 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6607 00:40:53.072079 ==
6608 00:40:53.072142 DQS Delay:
6609 00:40:53.075300 DQS0 = 44, DQS1 = 60
6610 00:40:53.075378 DQM Delay:
6611 00:40:53.078926 DQM0 = 8, DQM1 = 14
6612 00:40:53.079004 DQ Delay:
6613 00:40:53.081670 DQ0 =4, DQ1 =8, DQ2 =4, DQ3 =8
6614 00:40:53.084901 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6615 00:40:53.088435 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6616 00:40:53.091859 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =24
6617 00:40:53.091937
6618 00:40:53.091998
6619 00:40:53.098169 [DQSOSCAuto] RK1, (LSB)MR18= 0xb844, (MSB)MR19= 0xc0c, tDQSOscB0 = 401 ps tDQSOscB1 = 386 ps
6620 00:40:53.101399 CH0 RK1: MR19=C0C, MR18=B844
6621 00:40:53.107962 CH0_RK1: MR19=0xC0C, MR18=0xB844, DQSOSC=386, MR23=63, INC=396, DEC=264
6622 00:40:53.111710 [RxdqsGatingPostProcess] freq 400
6623 00:40:53.118183 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6624 00:40:53.121273 best DQS0 dly(2T, 0.5T) = (0, 10)
6625 00:40:53.121351 best DQS1 dly(2T, 0.5T) = (0, 10)
6626 00:40:53.124799 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6627 00:40:53.128334 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6628 00:40:53.131049 best DQS0 dly(2T, 0.5T) = (0, 10)
6629 00:40:53.134441 best DQS1 dly(2T, 0.5T) = (0, 10)
6630 00:40:53.137838 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6631 00:40:53.141055 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6632 00:40:53.144375 Pre-setting of DQS Precalculation
6633 00:40:53.150789 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6634 00:40:53.150867 ==
6635 00:40:53.154308 Dram Type= 6, Freq= 0, CH_1, rank 0
6636 00:40:53.157609 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6637 00:40:53.157688 ==
6638 00:40:53.164245 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6639 00:40:53.170833 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6640 00:40:53.174051 [CA 0] Center 36 (8~64) winsize 57
6641 00:40:53.174156 [CA 1] Center 36 (8~64) winsize 57
6642 00:40:53.177173 [CA 2] Center 36 (8~64) winsize 57
6643 00:40:53.181079 [CA 3] Center 36 (8~64) winsize 57
6644 00:40:53.184297 [CA 4] Center 36 (8~64) winsize 57
6645 00:40:53.187133 [CA 5] Center 36 (8~64) winsize 57
6646 00:40:53.187213
6647 00:40:53.190596 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6648 00:40:53.190677
6649 00:40:53.197014 [CATrainingPosCal] consider 1 rank data
6650 00:40:53.197094 u2DelayCellTimex100 = 270/100 ps
6651 00:40:53.200418 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6652 00:40:53.206915 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6653 00:40:53.210360 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6654 00:40:53.213585 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6655 00:40:53.216843 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6656 00:40:53.220158 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6657 00:40:53.220263
6658 00:40:53.223427 CA PerBit enable=1, Macro0, CA PI delay=36
6659 00:40:53.223511
6660 00:40:53.227034 [CBTSetCACLKResult] CA Dly = 36
6661 00:40:53.230126 CS Dly: 1 (0~32)
6662 00:40:53.230252 ==
6663 00:40:53.233334 Dram Type= 6, Freq= 0, CH_1, rank 1
6664 00:40:53.236471 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6665 00:40:53.236552 ==
6666 00:40:53.243286 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6667 00:40:53.246885 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6668 00:40:53.249876 [CA 0] Center 36 (8~64) winsize 57
6669 00:40:53.253255 [CA 1] Center 36 (8~64) winsize 57
6670 00:40:53.256442 [CA 2] Center 36 (8~64) winsize 57
6671 00:40:53.259757 [CA 3] Center 36 (8~64) winsize 57
6672 00:40:53.263236 [CA 4] Center 36 (8~64) winsize 57
6673 00:40:53.266556 [CA 5] Center 36 (8~64) winsize 57
6674 00:40:53.266636
6675 00:40:53.269804 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6676 00:40:53.269909
6677 00:40:53.272986 [CATrainingPosCal] consider 2 rank data
6678 00:40:53.276564 u2DelayCellTimex100 = 270/100 ps
6679 00:40:53.279788 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6680 00:40:53.282832 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6681 00:40:53.289362 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6682 00:40:53.292649 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6683 00:40:53.295903 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6684 00:40:53.299760 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6685 00:40:53.299840
6686 00:40:53.302888 CA PerBit enable=1, Macro0, CA PI delay=36
6687 00:40:53.302968
6688 00:40:53.305990 [CBTSetCACLKResult] CA Dly = 36
6689 00:40:53.306070 CS Dly: 1 (0~32)
6690 00:40:53.306133
6691 00:40:53.312694 ----->DramcWriteLeveling(PI) begin...
6692 00:40:53.312775 ==
6693 00:40:53.316052 Dram Type= 6, Freq= 0, CH_1, rank 0
6694 00:40:53.319522 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6695 00:40:53.319603 ==
6696 00:40:53.322323 Write leveling (Byte 0): 40 => 8
6697 00:40:53.325689 Write leveling (Byte 1): 32 => 0
6698 00:40:53.329361 DramcWriteLeveling(PI) end<-----
6699 00:40:53.329441
6700 00:40:53.329504 ==
6701 00:40:53.332509 Dram Type= 6, Freq= 0, CH_1, rank 0
6702 00:40:53.335576 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6703 00:40:53.335656 ==
6704 00:40:53.339103 [Gating] SW mode calibration
6705 00:40:53.345836 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6706 00:40:53.352425 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6707 00:40:53.355605 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6708 00:40:53.359041 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6709 00:40:53.365804 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6710 00:40:53.368829 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6711 00:40:53.372438 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6712 00:40:53.379231 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6713 00:40:53.381954 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6714 00:40:53.385580 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6715 00:40:53.392240 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6716 00:40:53.392319 Total UI for P1: 0, mck2ui 16
6717 00:40:53.395772 best dqsien dly found for B0: ( 0, 14, 24)
6718 00:40:53.398855 Total UI for P1: 0, mck2ui 16
6719 00:40:53.401839 best dqsien dly found for B1: ( 0, 14, 24)
6720 00:40:53.408406 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6721 00:40:53.411744 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6722 00:40:53.411821
6723 00:40:53.414896 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6724 00:40:53.418469 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6725 00:40:53.421868 [Gating] SW calibration Done
6726 00:40:53.421946 ==
6727 00:40:53.425371 Dram Type= 6, Freq= 0, CH_1, rank 0
6728 00:40:53.428553 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6729 00:40:53.428659 ==
6730 00:40:53.431681 RX Vref Scan: 0
6731 00:40:53.431759
6732 00:40:53.431820 RX Vref 0 -> 0, step: 1
6733 00:40:53.431878
6734 00:40:53.434928 RX Delay -410 -> 252, step: 16
6735 00:40:53.441575 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6736 00:40:53.444620 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6737 00:40:53.448384 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6738 00:40:53.451554 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6739 00:40:53.458071 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6740 00:40:53.461336 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6741 00:40:53.464812 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6742 00:40:53.468057 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6743 00:40:53.474813 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6744 00:40:53.477780 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6745 00:40:53.480983 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6746 00:40:53.484436 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6747 00:40:53.491610 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6748 00:40:53.494685 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6749 00:40:53.497669 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6750 00:40:53.504386 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6751 00:40:53.504492 ==
6752 00:40:53.507761 Dram Type= 6, Freq= 0, CH_1, rank 0
6753 00:40:53.510463 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6754 00:40:53.510542 ==
6755 00:40:53.510642 DQS Delay:
6756 00:40:53.513912 DQS0 = 43, DQS1 = 51
6757 00:40:53.513990 DQM Delay:
6758 00:40:53.517100 DQM0 = 12, DQM1 = 14
6759 00:40:53.517179 DQ Delay:
6760 00:40:53.520651 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6761 00:40:53.523759 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6762 00:40:53.527240 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =0
6763 00:40:53.530520 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6764 00:40:53.530598
6765 00:40:53.530662
6766 00:40:53.530720 ==
6767 00:40:53.534014 Dram Type= 6, Freq= 0, CH_1, rank 0
6768 00:40:53.537274 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6769 00:40:53.537353 ==
6770 00:40:53.537417
6771 00:40:53.537474
6772 00:40:53.540212 TX Vref Scan disable
6773 00:40:53.540290 == TX Byte 0 ==
6774 00:40:53.547035 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6775 00:40:53.550461 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6776 00:40:53.550539 == TX Byte 1 ==
6777 00:40:53.556978 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6778 00:40:53.560402 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6779 00:40:53.560498 ==
6780 00:40:53.564158 Dram Type= 6, Freq= 0, CH_1, rank 0
6781 00:40:53.567223 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6782 00:40:53.567302 ==
6783 00:40:53.567365
6784 00:40:53.567423
6785 00:40:53.570099 TX Vref Scan disable
6786 00:40:53.573332 == TX Byte 0 ==
6787 00:40:53.576975 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6788 00:40:53.580280 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6789 00:40:53.583187 == TX Byte 1 ==
6790 00:40:53.586670 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6791 00:40:53.589936 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6792 00:40:53.590014
6793 00:40:53.590076 [DATLAT]
6794 00:40:53.593234 Freq=400, CH1 RK0
6795 00:40:53.593313
6796 00:40:53.596737 DATLAT Default: 0xf
6797 00:40:53.596815 0, 0xFFFF, sum = 0
6798 00:40:53.600018 1, 0xFFFF, sum = 0
6799 00:40:53.600120 2, 0xFFFF, sum = 0
6800 00:40:53.603470 3, 0xFFFF, sum = 0
6801 00:40:53.603550 4, 0xFFFF, sum = 0
6802 00:40:53.606455 5, 0xFFFF, sum = 0
6803 00:40:53.606535 6, 0xFFFF, sum = 0
6804 00:40:53.609394 7, 0xFFFF, sum = 0
6805 00:40:53.609474 8, 0xFFFF, sum = 0
6806 00:40:53.613274 9, 0xFFFF, sum = 0
6807 00:40:53.613354 10, 0xFFFF, sum = 0
6808 00:40:53.616240 11, 0xFFFF, sum = 0
6809 00:40:53.616348 12, 0xFFFF, sum = 0
6810 00:40:53.619473 13, 0x0, sum = 1
6811 00:40:53.619552 14, 0x0, sum = 2
6812 00:40:53.622970 15, 0x0, sum = 3
6813 00:40:53.623049 16, 0x0, sum = 4
6814 00:40:53.626056 best_step = 14
6815 00:40:53.626134
6816 00:40:53.626236 ==
6817 00:40:53.629413 Dram Type= 6, Freq= 0, CH_1, rank 0
6818 00:40:53.632989 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6819 00:40:53.633068 ==
6820 00:40:53.636107 RX Vref Scan: 1
6821 00:40:53.636206
6822 00:40:53.636302 RX Vref 0 -> 0, step: 1
6823 00:40:53.636390
6824 00:40:53.639301 RX Delay -343 -> 252, step: 8
6825 00:40:53.639379
6826 00:40:53.642620 Set Vref, RX VrefLevel [Byte0]: 52
6827 00:40:53.645831 [Byte1]: 53
6828 00:40:53.650986
6829 00:40:53.651065 Final RX Vref Byte 0 = 52 to rank0
6830 00:40:53.654067 Final RX Vref Byte 1 = 53 to rank0
6831 00:40:53.657210 Final RX Vref Byte 0 = 52 to rank1
6832 00:40:53.660897 Final RX Vref Byte 1 = 53 to rank1==
6833 00:40:53.664342 Dram Type= 6, Freq= 0, CH_1, rank 0
6834 00:40:53.670763 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6835 00:40:53.670843 ==
6836 00:40:53.670906 DQS Delay:
6837 00:40:53.674120 DQS0 = 44, DQS1 = 56
6838 00:40:53.674235 DQM Delay:
6839 00:40:53.674299 DQM0 = 7, DQM1 = 12
6840 00:40:53.677177 DQ Delay:
6841 00:40:53.680748 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =4
6842 00:40:53.680827 DQ4 =4, DQ5 =20, DQ6 =16, DQ7 =0
6843 00:40:53.684073 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6844 00:40:53.687007 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =20
6845 00:40:53.687086
6846 00:40:53.687148
6847 00:40:53.697067 [DQSOSCAuto] RK0, (LSB)MR18= 0xa075, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 389 ps
6848 00:40:53.700177 CH1 RK0: MR19=C0C, MR18=A075
6849 00:40:53.707006 CH1_RK0: MR19=0xC0C, MR18=0xA075, DQSOSC=389, MR23=63, INC=390, DEC=260
6850 00:40:53.707085 ==
6851 00:40:53.710256 Dram Type= 6, Freq= 0, CH_1, rank 1
6852 00:40:53.713711 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6853 00:40:53.713789 ==
6854 00:40:53.716805 [Gating] SW mode calibration
6855 00:40:53.723737 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6856 00:40:53.730112 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6857 00:40:53.733570 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6858 00:40:53.736627 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6859 00:40:53.743690 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6860 00:40:53.746432 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6861 00:40:53.750024 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6862 00:40:53.756741 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6863 00:40:53.759581 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6864 00:40:53.763391 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6865 00:40:53.769642 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6866 00:40:53.769797 Total UI for P1: 0, mck2ui 16
6867 00:40:53.776064 best dqsien dly found for B0: ( 0, 14, 24)
6868 00:40:53.776211 Total UI for P1: 0, mck2ui 16
6869 00:40:53.782492 best dqsien dly found for B1: ( 0, 14, 24)
6870 00:40:53.786135 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6871 00:40:53.789352 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6872 00:40:53.789436
6873 00:40:53.792712 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6874 00:40:53.796010 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6875 00:40:53.799018 [Gating] SW calibration Done
6876 00:40:53.799098 ==
6877 00:40:53.802417 Dram Type= 6, Freq= 0, CH_1, rank 1
6878 00:40:53.806037 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6879 00:40:53.806118 ==
6880 00:40:53.809317 RX Vref Scan: 0
6881 00:40:53.809397
6882 00:40:53.809461 RX Vref 0 -> 0, step: 1
6883 00:40:53.809521
6884 00:40:53.812376 RX Delay -410 -> 252, step: 16
6885 00:40:53.819107 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6886 00:40:53.822135 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6887 00:40:53.825499 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6888 00:40:53.828648 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6889 00:40:53.835426 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6890 00:40:53.838988 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6891 00:40:53.841873 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6892 00:40:53.845662 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6893 00:40:53.852183 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6894 00:40:53.855569 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6895 00:40:53.858615 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6896 00:40:53.864997 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6897 00:40:53.868466 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6898 00:40:53.871673 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6899 00:40:53.874928 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6900 00:40:53.881749 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6901 00:40:53.881828 ==
6902 00:40:53.884859 Dram Type= 6, Freq= 0, CH_1, rank 1
6903 00:40:53.888022 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6904 00:40:53.888100 ==
6905 00:40:53.888165 DQS Delay:
6906 00:40:53.891307 DQS0 = 43, DQS1 = 51
6907 00:40:53.891386 DQM Delay:
6908 00:40:53.894808 DQM0 = 12, DQM1 = 14
6909 00:40:53.894894 DQ Delay:
6910 00:40:53.897871 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6911 00:40:53.901550 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6912 00:40:53.904842 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =0
6913 00:40:53.908273 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6914 00:40:53.908358
6915 00:40:53.908421
6916 00:40:53.908480 ==
6917 00:40:53.911407 Dram Type= 6, Freq= 0, CH_1, rank 1
6918 00:40:53.914510 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6919 00:40:53.914591 ==
6920 00:40:53.914656
6921 00:40:53.914715
6922 00:40:53.917787 TX Vref Scan disable
6923 00:40:53.921175 == TX Byte 0 ==
6924 00:40:53.924721 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6925 00:40:53.928090 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6926 00:40:53.931318 == TX Byte 1 ==
6927 00:40:53.934310 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6928 00:40:53.937748 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6929 00:40:53.937858 ==
6930 00:40:53.941069 Dram Type= 6, Freq= 0, CH_1, rank 1
6931 00:40:53.944172 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6932 00:40:53.944276 ==
6933 00:40:53.947498
6934 00:40:53.947600
6935 00:40:53.947688 TX Vref Scan disable
6936 00:40:53.950895 == TX Byte 0 ==
6937 00:40:53.954519 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6938 00:40:53.957612 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6939 00:40:53.960555 == TX Byte 1 ==
6940 00:40:53.963969 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6941 00:40:53.967370 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6942 00:40:53.967451
6943 00:40:53.967527 [DATLAT]
6944 00:40:53.970377 Freq=400, CH1 RK1
6945 00:40:53.970449
6946 00:40:53.973803 DATLAT Default: 0xe
6947 00:40:53.973906 0, 0xFFFF, sum = 0
6948 00:40:53.977504 1, 0xFFFF, sum = 0
6949 00:40:53.977584 2, 0xFFFF, sum = 0
6950 00:40:53.980455 3, 0xFFFF, sum = 0
6951 00:40:53.980535 4, 0xFFFF, sum = 0
6952 00:40:53.983501 5, 0xFFFF, sum = 0
6953 00:40:53.983580 6, 0xFFFF, sum = 0
6954 00:40:53.987366 7, 0xFFFF, sum = 0
6955 00:40:53.987446 8, 0xFFFF, sum = 0
6956 00:40:53.990491 9, 0xFFFF, sum = 0
6957 00:40:53.990571 10, 0xFFFF, sum = 0
6958 00:40:53.993899 11, 0xFFFF, sum = 0
6959 00:40:53.993978 12, 0xFFFF, sum = 0
6960 00:40:53.997213 13, 0x0, sum = 1
6961 00:40:53.997292 14, 0x0, sum = 2
6962 00:40:54.000215 15, 0x0, sum = 3
6963 00:40:54.000294 16, 0x0, sum = 4
6964 00:40:54.003964 best_step = 14
6965 00:40:54.004042
6966 00:40:54.004104 ==
6967 00:40:54.006888 Dram Type= 6, Freq= 0, CH_1, rank 1
6968 00:40:54.010156 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6969 00:40:54.010256 ==
6970 00:40:54.013697 RX Vref Scan: 0
6971 00:40:54.013801
6972 00:40:54.013913 RX Vref 0 -> 0, step: 1
6973 00:40:54.014003
6974 00:40:54.016653 RX Delay -343 -> 252, step: 8
6975 00:40:54.024763 iDelay=225, Bit 0, Center -28 (-271 ~ 216) 488
6976 00:40:54.028325 iDelay=225, Bit 1, Center -44 (-287 ~ 200) 488
6977 00:40:54.031508 iDelay=225, Bit 2, Center -44 (-287 ~ 200) 488
6978 00:40:54.037951 iDelay=225, Bit 3, Center -40 (-279 ~ 200) 480
6979 00:40:54.041171 iDelay=225, Bit 4, Center -40 (-287 ~ 208) 496
6980 00:40:54.044406 iDelay=225, Bit 5, Center -28 (-271 ~ 216) 488
6981 00:40:54.047602 iDelay=225, Bit 6, Center -24 (-271 ~ 224) 496
6982 00:40:54.054098 iDelay=225, Bit 7, Center -40 (-287 ~ 208) 496
6983 00:40:54.057763 iDelay=225, Bit 8, Center -56 (-303 ~ 192) 496
6984 00:40:54.061126 iDelay=225, Bit 9, Center -56 (-303 ~ 192) 496
6985 00:40:54.064711 iDelay=225, Bit 10, Center -48 (-295 ~ 200) 496
6986 00:40:54.070887 iDelay=225, Bit 11, Center -52 (-295 ~ 192) 488
6987 00:40:54.074048 iDelay=225, Bit 12, Center -36 (-287 ~ 216) 504
6988 00:40:54.077222 iDelay=225, Bit 13, Center -40 (-287 ~ 208) 496
6989 00:40:54.083873 iDelay=225, Bit 14, Center -40 (-287 ~ 208) 496
6990 00:40:54.087307 iDelay=225, Bit 15, Center -36 (-287 ~ 216) 504
6991 00:40:54.087385 ==
6992 00:40:54.090678 Dram Type= 6, Freq= 0, CH_1, rank 1
6993 00:40:54.093715 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6994 00:40:54.093794 ==
6995 00:40:54.097151 DQS Delay:
6996 00:40:54.097229 DQS0 = 44, DQS1 = 56
6997 00:40:54.097291 DQM Delay:
6998 00:40:54.100330 DQM0 = 8, DQM1 = 10
6999 00:40:54.100408 DQ Delay:
7000 00:40:54.103697 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =4
7001 00:40:54.106538 DQ4 =4, DQ5 =16, DQ6 =20, DQ7 =4
7002 00:40:54.110055 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
7003 00:40:54.113470 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =20
7004 00:40:54.113584
7005 00:40:54.113650
7006 00:40:54.123288 [DQSOSCAuto] RK1, (LSB)MR18= 0x6a59, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 396 ps
7007 00:40:54.123368 CH1 RK1: MR19=C0C, MR18=6A59
7008 00:40:54.130016 CH1_RK1: MR19=0xC0C, MR18=0x6A59, DQSOSC=396, MR23=63, INC=376, DEC=251
7009 00:40:54.132970 [RxdqsGatingPostProcess] freq 400
7010 00:40:54.139703 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7011 00:40:54.143333 best DQS0 dly(2T, 0.5T) = (0, 10)
7012 00:40:54.146405 best DQS1 dly(2T, 0.5T) = (0, 10)
7013 00:40:54.149729 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7014 00:40:54.152967 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7015 00:40:54.156189 best DQS0 dly(2T, 0.5T) = (0, 10)
7016 00:40:54.159400 best DQS1 dly(2T, 0.5T) = (0, 10)
7017 00:40:54.162783 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7018 00:40:54.165810 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7019 00:40:54.165909 Pre-setting of DQS Precalculation
7020 00:40:54.172657 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7021 00:40:54.178959 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7022 00:40:54.185793 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7023 00:40:54.185872
7024 00:40:54.185934
7025 00:40:54.189269 [Calibration Summary] 800 Mbps
7026 00:40:54.192563 CH 0, Rank 0
7027 00:40:54.192641 SW Impedance : PASS
7028 00:40:54.196047 DUTY Scan : NO K
7029 00:40:54.198924 ZQ Calibration : PASS
7030 00:40:54.199003 Jitter Meter : NO K
7031 00:40:54.202081 CBT Training : PASS
7032 00:40:54.205534 Write leveling : PASS
7033 00:40:54.205605 RX DQS gating : PASS
7034 00:40:54.208935 RX DQ/DQS(RDDQC) : PASS
7035 00:40:54.209014 TX DQ/DQS : PASS
7036 00:40:54.212277 RX DATLAT : PASS
7037 00:40:54.215419 RX DQ/DQS(Engine): PASS
7038 00:40:54.215498 TX OE : NO K
7039 00:40:54.219089 All Pass.
7040 00:40:54.219167
7041 00:40:54.219230 CH 0, Rank 1
7042 00:40:54.222543 SW Impedance : PASS
7043 00:40:54.222622 DUTY Scan : NO K
7044 00:40:54.225760 ZQ Calibration : PASS
7045 00:40:54.228735 Jitter Meter : NO K
7046 00:40:54.228815 CBT Training : PASS
7047 00:40:54.231913 Write leveling : NO K
7048 00:40:54.235492 RX DQS gating : PASS
7049 00:40:54.235571 RX DQ/DQS(RDDQC) : PASS
7050 00:40:54.238833 TX DQ/DQS : PASS
7051 00:40:54.242358 RX DATLAT : PASS
7052 00:40:54.242436 RX DQ/DQS(Engine): PASS
7053 00:40:54.245725 TX OE : NO K
7054 00:40:54.245804 All Pass.
7055 00:40:54.245867
7056 00:40:54.248636 CH 1, Rank 0
7057 00:40:54.248714 SW Impedance : PASS
7058 00:40:54.251926 DUTY Scan : NO K
7059 00:40:54.255614 ZQ Calibration : PASS
7060 00:40:54.255692 Jitter Meter : NO K
7061 00:40:54.258820 CBT Training : PASS
7062 00:40:54.261677 Write leveling : PASS
7063 00:40:54.261755 RX DQS gating : PASS
7064 00:40:54.265074 RX DQ/DQS(RDDQC) : PASS
7065 00:40:54.268223 TX DQ/DQS : PASS
7066 00:40:54.268301 RX DATLAT : PASS
7067 00:40:54.271642 RX DQ/DQS(Engine): PASS
7068 00:40:54.275160 TX OE : NO K
7069 00:40:54.275238 All Pass.
7070 00:40:54.275301
7071 00:40:54.275358 CH 1, Rank 1
7072 00:40:54.278519 SW Impedance : PASS
7073 00:40:54.281877 DUTY Scan : NO K
7074 00:40:54.281955 ZQ Calibration : PASS
7075 00:40:54.285180 Jitter Meter : NO K
7076 00:40:54.285259 CBT Training : PASS
7077 00:40:54.288344 Write leveling : NO K
7078 00:40:54.291463 RX DQS gating : PASS
7079 00:40:54.291542 RX DQ/DQS(RDDQC) : PASS
7080 00:40:54.295323 TX DQ/DQS : PASS
7081 00:40:54.297982 RX DATLAT : PASS
7082 00:40:54.298060 RX DQ/DQS(Engine): PASS
7083 00:40:54.301413 TX OE : NO K
7084 00:40:54.301492 All Pass.
7085 00:40:54.301555
7086 00:40:54.304512 DramC Write-DBI off
7087 00:40:54.308072 PER_BANK_REFRESH: Hybrid Mode
7088 00:40:54.308151 TX_TRACKING: ON
7089 00:40:54.317735 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7090 00:40:54.320949 [FAST_K] Save calibration result to emmc
7091 00:40:54.324261 dramc_set_vcore_voltage set vcore to 725000
7092 00:40:54.327851 Read voltage for 1600, 0
7093 00:40:54.327924 Vio18 = 0
7094 00:40:54.330825 Vcore = 725000
7095 00:40:54.330899 Vdram = 0
7096 00:40:54.330960 Vddq = 0
7097 00:40:54.331018 Vmddr = 0
7098 00:40:54.337730 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7099 00:40:54.344221 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7100 00:40:54.344300 MEM_TYPE=3, freq_sel=13
7101 00:40:54.347699 sv_algorithm_assistance_LP4_3733
7102 00:40:54.350876 ============ PULL DRAM RESETB DOWN ============
7103 00:40:54.357236 ========== PULL DRAM RESETB DOWN end =========
7104 00:40:54.360540 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7105 00:40:54.364212 ===================================
7106 00:40:54.367552 LPDDR4 DRAM CONFIGURATION
7107 00:40:54.370577 ===================================
7108 00:40:54.370656 EX_ROW_EN[0] = 0x0
7109 00:40:54.373854 EX_ROW_EN[1] = 0x0
7110 00:40:54.373932 LP4Y_EN = 0x0
7111 00:40:54.377199 WORK_FSP = 0x1
7112 00:40:54.380539 WL = 0x5
7113 00:40:54.380617 RL = 0x5
7114 00:40:54.383773 BL = 0x2
7115 00:40:54.383851 RPST = 0x0
7116 00:40:54.387009 RD_PRE = 0x0
7117 00:40:54.387087 WR_PRE = 0x1
7118 00:40:54.390413 WR_PST = 0x1
7119 00:40:54.390492 DBI_WR = 0x0
7120 00:40:54.393848 DBI_RD = 0x0
7121 00:40:54.393926 OTF = 0x1
7122 00:40:54.397171 ===================================
7123 00:40:54.400279 ===================================
7124 00:40:54.403431 ANA top config
7125 00:40:54.406692 ===================================
7126 00:40:54.406860 DLL_ASYNC_EN = 0
7127 00:40:54.410321 ALL_SLAVE_EN = 0
7128 00:40:54.413269 NEW_RANK_MODE = 1
7129 00:40:54.416527 DLL_IDLE_MODE = 1
7130 00:40:54.419965 LP45_APHY_COMB_EN = 1
7131 00:40:54.420044 TX_ODT_DIS = 0
7132 00:40:54.423213 NEW_8X_MODE = 1
7133 00:40:54.426424 ===================================
7134 00:40:54.430091 ===================================
7135 00:40:54.433000 data_rate = 3200
7136 00:40:54.436696 CKR = 1
7137 00:40:54.439782 DQ_P2S_RATIO = 8
7138 00:40:54.443243 ===================================
7139 00:40:54.446330 CA_P2S_RATIO = 8
7140 00:40:54.446408 DQ_CA_OPEN = 0
7141 00:40:54.449544 DQ_SEMI_OPEN = 0
7142 00:40:54.452946 CA_SEMI_OPEN = 0
7143 00:40:54.456669 CA_FULL_RATE = 0
7144 00:40:54.459400 DQ_CKDIV4_EN = 0
7145 00:40:54.462626 CA_CKDIV4_EN = 0
7146 00:40:54.462705 CA_PREDIV_EN = 0
7147 00:40:54.466373 PH8_DLY = 12
7148 00:40:54.469476 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7149 00:40:54.472382 DQ_AAMCK_DIV = 4
7150 00:40:54.475694 CA_AAMCK_DIV = 4
7151 00:40:54.479066 CA_ADMCK_DIV = 4
7152 00:40:54.482461 DQ_TRACK_CA_EN = 0
7153 00:40:54.482539 CA_PICK = 1600
7154 00:40:54.485422 CA_MCKIO = 1600
7155 00:40:54.489124 MCKIO_SEMI = 0
7156 00:40:54.492685 PLL_FREQ = 3068
7157 00:40:54.495574 DQ_UI_PI_RATIO = 32
7158 00:40:54.499021 CA_UI_PI_RATIO = 0
7159 00:40:54.502291 ===================================
7160 00:40:54.505516 ===================================
7161 00:40:54.508691 memory_type:LPDDR4
7162 00:40:54.508795 GP_NUM : 10
7163 00:40:54.512249 SRAM_EN : 1
7164 00:40:54.512327 MD32_EN : 0
7165 00:40:54.515385 ===================================
7166 00:40:54.518825 [ANA_INIT] >>>>>>>>>>>>>>
7167 00:40:54.521865 <<<<<< [CONFIGURE PHASE]: ANA_TX
7168 00:40:54.525249 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7169 00:40:54.528500 ===================================
7170 00:40:54.531650 data_rate = 3200,PCW = 0X7600
7171 00:40:54.535291 ===================================
7172 00:40:54.538951 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7173 00:40:54.544867 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7174 00:40:54.548093 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7175 00:40:54.554956 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7176 00:40:54.558252 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7177 00:40:54.561768 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7178 00:40:54.561848 [ANA_INIT] flow start
7179 00:40:54.564628 [ANA_INIT] PLL >>>>>>>>
7180 00:40:54.567813 [ANA_INIT] PLL <<<<<<<<
7181 00:40:54.567892 [ANA_INIT] MIDPI >>>>>>>>
7182 00:40:54.571074 [ANA_INIT] MIDPI <<<<<<<<
7183 00:40:54.574866 [ANA_INIT] DLL >>>>>>>>
7184 00:40:54.578394 [ANA_INIT] DLL <<<<<<<<
7185 00:40:54.578473 [ANA_INIT] flow end
7186 00:40:54.581415 ============ LP4 DIFF to SE enter ============
7187 00:40:54.587651 ============ LP4 DIFF to SE exit ============
7188 00:40:54.587730 [ANA_INIT] <<<<<<<<<<<<<
7189 00:40:54.590815 [Flow] Enable top DCM control >>>>>
7190 00:40:54.594147 [Flow] Enable top DCM control <<<<<
7191 00:40:54.597588 Enable DLL master slave shuffle
7192 00:40:54.604048 ==============================================================
7193 00:40:54.604127 Gating Mode config
7194 00:40:54.610869 ==============================================================
7195 00:40:54.613894 Config description:
7196 00:40:54.623761 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7197 00:40:54.630445 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7198 00:40:54.633549 SELPH_MODE 0: By rank 1: By Phase
7199 00:40:54.640714 ==============================================================
7200 00:40:54.643790 GAT_TRACK_EN = 1
7201 00:40:54.647139 RX_GATING_MODE = 2
7202 00:40:54.650321 RX_GATING_TRACK_MODE = 2
7203 00:40:54.650400 SELPH_MODE = 1
7204 00:40:54.653645 PICG_EARLY_EN = 1
7205 00:40:54.656873 VALID_LAT_VALUE = 1
7206 00:40:54.663668 ==============================================================
7207 00:40:54.666719 Enter into Gating configuration >>>>
7208 00:40:54.669804 Exit from Gating configuration <<<<
7209 00:40:54.673210 Enter into DVFS_PRE_config >>>>>
7210 00:40:54.683405 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7211 00:40:54.686750 Exit from DVFS_PRE_config <<<<<
7212 00:40:54.689576 Enter into PICG configuration >>>>
7213 00:40:54.693249 Exit from PICG configuration <<<<
7214 00:40:54.696517 [RX_INPUT] configuration >>>>>
7215 00:40:54.700006 [RX_INPUT] configuration <<<<<
7216 00:40:54.703306 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7217 00:40:54.709945 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7218 00:40:54.716209 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7219 00:40:54.722915 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7220 00:40:54.729606 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7221 00:40:54.736351 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7222 00:40:54.739654 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7223 00:40:54.742396 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7224 00:40:54.746076 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7225 00:40:54.752447 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7226 00:40:54.755790 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7227 00:40:54.759119 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7228 00:40:54.762598 ===================================
7229 00:40:54.765691 LPDDR4 DRAM CONFIGURATION
7230 00:40:54.768685 ===================================
7231 00:40:54.768786 EX_ROW_EN[0] = 0x0
7232 00:40:54.772560 EX_ROW_EN[1] = 0x0
7233 00:40:54.772654 LP4Y_EN = 0x0
7234 00:40:54.775388 WORK_FSP = 0x1
7235 00:40:54.778997 WL = 0x5
7236 00:40:54.779076 RL = 0x5
7237 00:40:54.782425 BL = 0x2
7238 00:40:54.782492 RPST = 0x0
7239 00:40:54.785300 RD_PRE = 0x0
7240 00:40:54.785393 WR_PRE = 0x1
7241 00:40:54.788794 WR_PST = 0x1
7242 00:40:54.788861 DBI_WR = 0x0
7243 00:40:54.792235 DBI_RD = 0x0
7244 00:40:54.792335 OTF = 0x1
7245 00:40:54.795705 ===================================
7246 00:40:54.798755 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7247 00:40:54.805338 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7248 00:40:54.808801 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7249 00:40:54.812238 ===================================
7250 00:40:54.814895 LPDDR4 DRAM CONFIGURATION
7251 00:40:54.818178 ===================================
7252 00:40:54.818292 EX_ROW_EN[0] = 0x10
7253 00:40:54.821748 EX_ROW_EN[1] = 0x0
7254 00:40:54.824724 LP4Y_EN = 0x0
7255 00:40:54.824825 WORK_FSP = 0x1
7256 00:40:54.828496 WL = 0x5
7257 00:40:54.828578 RL = 0x5
7258 00:40:54.831679 BL = 0x2
7259 00:40:54.831746 RPST = 0x0
7260 00:40:54.834890 RD_PRE = 0x0
7261 00:40:54.834961 WR_PRE = 0x1
7262 00:40:54.837912 WR_PST = 0x1
7263 00:40:54.838005 DBI_WR = 0x0
7264 00:40:54.841426 DBI_RD = 0x0
7265 00:40:54.841496 OTF = 0x1
7266 00:40:54.844817 ===================================
7267 00:40:54.851101 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7268 00:40:54.851194 ==
7269 00:40:54.854382 Dram Type= 6, Freq= 0, CH_0, rank 0
7270 00:40:54.857858 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7271 00:40:54.861225 ==
7272 00:40:54.861304 [Duty_Offset_Calibration]
7273 00:40:54.864095 B0:1 B1:-1 CA:0
7274 00:40:54.864175
7275 00:40:54.867528 [DutyScan_Calibration_Flow] k_type=0
7276 00:40:54.876540
7277 00:40:54.876662 ==CLK 0==
7278 00:40:54.880189 Final CLK duty delay cell = 0
7279 00:40:54.883282 [0] MAX Duty = 5125%(X100), DQS PI = 20
7280 00:40:54.886951 [0] MIN Duty = 4907%(X100), DQS PI = 6
7281 00:40:54.889783 [0] AVG Duty = 5016%(X100)
7282 00:40:54.889861
7283 00:40:54.893160 CH0 CLK Duty spec in!! Max-Min= 218%
7284 00:40:54.896474 [DutyScan_Calibration_Flow] ====Done====
7285 00:40:54.896553
7286 00:40:54.899851 [DutyScan_Calibration_Flow] k_type=1
7287 00:40:54.915945
7288 00:40:54.916023 ==DQS 0 ==
7289 00:40:54.919057 Final DQS duty delay cell = -4
7290 00:40:54.922678 [-4] MAX Duty = 4969%(X100), DQS PI = 18
7291 00:40:54.925937 [-4] MIN Duty = 4844%(X100), DQS PI = 48
7292 00:40:54.929121 [-4] AVG Duty = 4906%(X100)
7293 00:40:54.929225
7294 00:40:54.929314 ==DQS 1 ==
7295 00:40:54.932506 Final DQS duty delay cell = 0
7296 00:40:54.935825 [0] MAX Duty = 5156%(X100), DQS PI = 2
7297 00:40:54.938985 [0] MIN Duty = 5000%(X100), DQS PI = 18
7298 00:40:54.942215 [0] AVG Duty = 5078%(X100)
7299 00:40:54.942294
7300 00:40:54.945949 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7301 00:40:54.946027
7302 00:40:54.948903 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7303 00:40:54.952336 [DutyScan_Calibration_Flow] ====Done====
7304 00:40:54.952527
7305 00:40:54.955255 [DutyScan_Calibration_Flow] k_type=3
7306 00:40:54.973508
7307 00:40:54.973660 ==DQM 0 ==
7308 00:40:54.976648 Final DQM duty delay cell = 0
7309 00:40:54.980202 [0] MAX Duty = 5124%(X100), DQS PI = 22
7310 00:40:54.983452 [0] MIN Duty = 4875%(X100), DQS PI = 10
7311 00:40:54.986657 [0] AVG Duty = 4999%(X100)
7312 00:40:54.986735
7313 00:40:54.986797 ==DQM 1 ==
7314 00:40:54.990421 Final DQM duty delay cell = 0
7315 00:40:54.993076 [0] MAX Duty = 5031%(X100), DQS PI = 54
7316 00:40:54.997002 [0] MIN Duty = 4782%(X100), DQS PI = 20
7317 00:40:55.000297 [0] AVG Duty = 4906%(X100)
7318 00:40:55.000370
7319 00:40:55.003665 CH0 DQM 0 Duty spec in!! Max-Min= 249%
7320 00:40:55.003744
7321 00:40:55.006777 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7322 00:40:55.009872 [DutyScan_Calibration_Flow] ====Done====
7323 00:40:55.009950
7324 00:40:55.013057 [DutyScan_Calibration_Flow] k_type=2
7325 00:40:55.029592
7326 00:40:55.029672 ==DQ 0 ==
7327 00:40:55.033075 Final DQ duty delay cell = -4
7328 00:40:55.036596 [-4] MAX Duty = 5031%(X100), DQS PI = 26
7329 00:40:55.039639 [-4] MIN Duty = 4876%(X100), DQS PI = 54
7330 00:40:55.043090 [-4] AVG Duty = 4953%(X100)
7331 00:40:55.043169
7332 00:40:55.043231 ==DQ 1 ==
7333 00:40:55.046427 Final DQ duty delay cell = 0
7334 00:40:55.049498 [0] MAX Duty = 5125%(X100), DQS PI = 50
7335 00:40:55.052686 [0] MIN Duty = 4969%(X100), DQS PI = 38
7336 00:40:55.056083 [0] AVG Duty = 5047%(X100)
7337 00:40:55.056163
7338 00:40:55.059147 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7339 00:40:55.059225
7340 00:40:55.062831 CH0 DQ 1 Duty spec in!! Max-Min= 156%
7341 00:40:55.066364 [DutyScan_Calibration_Flow] ====Done====
7342 00:40:55.066442 ==
7343 00:40:55.069592 Dram Type= 6, Freq= 0, CH_1, rank 0
7344 00:40:55.072886 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7345 00:40:55.072965 ==
7346 00:40:55.075677 [Duty_Offset_Calibration]
7347 00:40:55.079230 B0:-1 B1:1 CA:2
7348 00:40:55.079308
7349 00:40:55.082023 [DutyScan_Calibration_Flow] k_type=0
7350 00:40:55.090302
7351 00:40:55.090392 ==CLK 0==
7352 00:40:55.093413 Final CLK duty delay cell = 0
7353 00:40:55.096719 [0] MAX Duty = 5187%(X100), DQS PI = 22
7354 00:40:55.099961 [0] MIN Duty = 4969%(X100), DQS PI = 62
7355 00:40:55.103479 [0] AVG Duty = 5078%(X100)
7356 00:40:55.103560
7357 00:40:55.106566 CH1 CLK Duty spec in!! Max-Min= 218%
7358 00:40:55.110211 [DutyScan_Calibration_Flow] ====Done====
7359 00:40:55.110316
7360 00:40:55.112871 [DutyScan_Calibration_Flow] k_type=1
7361 00:40:55.130071
7362 00:40:55.130170 ==DQS 0 ==
7363 00:40:55.133438 Final DQS duty delay cell = 0
7364 00:40:55.136921 [0] MAX Duty = 5124%(X100), DQS PI = 18
7365 00:40:55.140317 [0] MIN Duty = 4907%(X100), DQS PI = 10
7366 00:40:55.143495 [0] AVG Duty = 5015%(X100)
7367 00:40:55.143575
7368 00:40:55.143638 ==DQS 1 ==
7369 00:40:55.146849 Final DQS duty delay cell = 0
7370 00:40:55.150287 [0] MAX Duty = 5093%(X100), DQS PI = 26
7371 00:40:55.153426 [0] MIN Duty = 4969%(X100), DQS PI = 54
7372 00:40:55.156603 [0] AVG Duty = 5031%(X100)
7373 00:40:55.156703
7374 00:40:55.159679 CH1 DQS 0 Duty spec in!! Max-Min= 217%
7375 00:40:55.159767
7376 00:40:55.163314 CH1 DQS 1 Duty spec in!! Max-Min= 124%
7377 00:40:55.166759 [DutyScan_Calibration_Flow] ====Done====
7378 00:40:55.166878
7379 00:40:55.169567 [DutyScan_Calibration_Flow] k_type=3
7380 00:40:55.187363
7381 00:40:55.187472 ==DQM 0 ==
7382 00:40:55.190303 Final DQM duty delay cell = 0
7383 00:40:55.193866 [0] MAX Duty = 5218%(X100), DQS PI = 36
7384 00:40:55.197275 [0] MIN Duty = 5031%(X100), DQS PI = 8
7385 00:40:55.200134 [0] AVG Duty = 5124%(X100)
7386 00:40:55.200271
7387 00:40:55.200413 ==DQM 1 ==
7388 00:40:55.203820 Final DQM duty delay cell = 0
7389 00:40:55.207058 [0] MAX Duty = 5156%(X100), DQS PI = 6
7390 00:40:55.209985 [0] MIN Duty = 4969%(X100), DQS PI = 28
7391 00:40:55.213411 [0] AVG Duty = 5062%(X100)
7392 00:40:55.213513
7393 00:40:55.216681 CH1 DQM 0 Duty spec in!! Max-Min= 187%
7394 00:40:55.216791
7395 00:40:55.220113 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7396 00:40:55.223409 [DutyScan_Calibration_Flow] ====Done====
7397 00:40:55.223551
7398 00:40:55.226467 [DutyScan_Calibration_Flow] k_type=2
7399 00:40:55.244142
7400 00:40:55.244295 ==DQ 0 ==
7401 00:40:55.247514 Final DQ duty delay cell = 0
7402 00:40:55.250697 [0] MAX Duty = 5156%(X100), DQS PI = 30
7403 00:40:55.253985 [0] MIN Duty = 4906%(X100), DQS PI = 8
7404 00:40:55.254097 [0] AVG Duty = 5031%(X100)
7405 00:40:55.257435
7406 00:40:55.257576 ==DQ 1 ==
7407 00:40:55.260443 Final DQ duty delay cell = 0
7408 00:40:55.263788 [0] MAX Duty = 5156%(X100), DQS PI = 10
7409 00:40:55.266950 [0] MIN Duty = 4938%(X100), DQS PI = 60
7410 00:40:55.267041 [0] AVG Duty = 5047%(X100)
7411 00:40:55.270277
7412 00:40:55.273845 CH1 DQ 0 Duty spec in!! Max-Min= 250%
7413 00:40:55.273988
7414 00:40:55.276874 CH1 DQ 1 Duty spec in!! Max-Min= 218%
7415 00:40:55.280131 [DutyScan_Calibration_Flow] ====Done====
7416 00:40:55.283435 nWR fixed to 30
7417 00:40:55.283549 [ModeRegInit_LP4] CH0 RK0
7418 00:40:55.287024 [ModeRegInit_LP4] CH0 RK1
7419 00:40:55.289877 [ModeRegInit_LP4] CH1 RK0
7420 00:40:55.293586 [ModeRegInit_LP4] CH1 RK1
7421 00:40:55.293681 match AC timing 5
7422 00:40:55.299748 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7423 00:40:55.303280 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7424 00:40:55.306529 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7425 00:40:55.312917 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7426 00:40:55.316335 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7427 00:40:55.316450 [MiockJmeterHQA]
7428 00:40:55.316537
7429 00:40:55.319555 [DramcMiockJmeter] u1RxGatingPI = 0
7430 00:40:55.322845 0 : 4368, 4140
7431 00:40:55.322928 4 : 4255, 4029
7432 00:40:55.326129 8 : 4363, 4137
7433 00:40:55.326222 12 : 4258, 4029
7434 00:40:55.329690 16 : 4253, 4027
7435 00:40:55.329765 20 : 4370, 4140
7436 00:40:55.329828 24 : 4366, 4138
7437 00:40:55.332608 28 : 4253, 4026
7438 00:40:55.332680 32 : 4252, 4027
7439 00:40:55.336109 36 : 4252, 4027
7440 00:40:55.336183 40 : 4363, 4137
7441 00:40:55.339318 44 : 4252, 4027
7442 00:40:55.339393 48 : 4361, 4137
7443 00:40:55.342558 52 : 4252, 4027
7444 00:40:55.342659 56 : 4250, 4027
7445 00:40:55.342762 60 : 4250, 4026
7446 00:40:55.346012 64 : 4252, 4029
7447 00:40:55.346121 68 : 4361, 4137
7448 00:40:55.349344 72 : 4250, 4027
7449 00:40:55.349418 76 : 4360, 4137
7450 00:40:55.352763 80 : 4250, 4026
7451 00:40:55.352846 84 : 4250, 4027
7452 00:40:55.355642 88 : 4250, 4026
7453 00:40:55.355727 92 : 4361, 448
7454 00:40:55.355793 96 : 4250, 0
7455 00:40:55.358970 100 : 4252, 0
7456 00:40:55.359056 104 : 4361, 0
7457 00:40:55.362287 108 : 4255, 0
7458 00:40:55.362387 112 : 4250, 0
7459 00:40:55.362454 116 : 4250, 0
7460 00:40:55.365672 120 : 4250, 0
7461 00:40:55.365756 124 : 4363, 0
7462 00:40:55.365821 128 : 4253, 0
7463 00:40:55.369163 132 : 4252, 0
7464 00:40:55.369249 136 : 4250, 0
7465 00:40:55.372694 140 : 4252, 0
7466 00:40:55.372778 144 : 4361, 0
7467 00:40:55.372843 148 : 4249, 0
7468 00:40:55.375790 152 : 4250, 0
7469 00:40:55.375872 156 : 4250, 0
7470 00:40:55.378767 160 : 4361, 0
7471 00:40:55.378850 164 : 4360, 0
7472 00:40:55.378915 168 : 4250, 0
7473 00:40:55.382026 172 : 4250, 0
7474 00:40:55.382136 176 : 4250, 0
7475 00:40:55.385320 180 : 4252, 0
7476 00:40:55.385403 184 : 4250, 0
7477 00:40:55.385469 188 : 4249, 0
7478 00:40:55.388961 192 : 4252, 0
7479 00:40:55.389051 196 : 4361, 0
7480 00:40:55.392203 200 : 4251, 0
7481 00:40:55.392287 204 : 4250, 0
7482 00:40:55.392353 208 : 4250, 0
7483 00:40:55.395389 212 : 4360, 0
7484 00:40:55.395471 216 : 4360, 0
7485 00:40:55.398981 220 : 4250, 0
7486 00:40:55.399063 224 : 4250, 172
7487 00:40:55.399128 228 : 4252, 3682
7488 00:40:55.401807 232 : 4360, 4138
7489 00:40:55.401889 236 : 4250, 4027
7490 00:40:55.405386 240 : 4250, 4027
7491 00:40:55.405480 244 : 4250, 4027
7492 00:40:55.408579 248 : 4252, 4030
7493 00:40:55.408660 252 : 4249, 4027
7494 00:40:55.412300 256 : 4250, 4026
7495 00:40:55.412383 260 : 4250, 4027
7496 00:40:55.414961 264 : 4252, 4029
7497 00:40:55.415042 268 : 4249, 4027
7498 00:40:55.418400 272 : 4361, 4137
7499 00:40:55.418482 276 : 4361, 4137
7500 00:40:55.421684 280 : 4250, 4027
7501 00:40:55.421765 284 : 4363, 4140
7502 00:40:55.421830 288 : 4249, 4027
7503 00:40:55.425169 292 : 4250, 4026
7504 00:40:55.425250 296 : 4250, 4027
7505 00:40:55.428523 300 : 4252, 4029
7506 00:40:55.428605 304 : 4249, 4027
7507 00:40:55.431921 308 : 4250, 4026
7508 00:40:55.432003 312 : 4250, 4027
7509 00:40:55.434875 316 : 4252, 4029
7510 00:40:55.434956 320 : 4249, 4027
7511 00:40:55.438180 324 : 4360, 4137
7512 00:40:55.438289 328 : 4361, 4137
7513 00:40:55.441342 332 : 4250, 4027
7514 00:40:55.441422 336 : 4363, 3967
7515 00:40:55.444803 340 : 4249, 1559
7516 00:40:55.444886
7517 00:40:55.444950 MIOCK jitter meter ch=0
7518 00:40:55.445010
7519 00:40:55.448365 1T = (340-92) = 248 dly cells
7520 00:40:55.454881 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 262/100 ps
7521 00:40:55.454965 ==
7522 00:40:55.457801 Dram Type= 6, Freq= 0, CH_0, rank 0
7523 00:40:55.461294 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7524 00:40:55.461377 ==
7525 00:40:55.467662 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7526 00:40:55.471153 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7527 00:40:55.474452 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7528 00:40:55.481363 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7529 00:40:55.491195 [CA 0] Center 43 (12~74) winsize 63
7530 00:40:55.494367 [CA 1] Center 43 (13~73) winsize 61
7531 00:40:55.497775 [CA 2] Center 38 (9~68) winsize 60
7532 00:40:55.501201 [CA 3] Center 38 (9~68) winsize 60
7533 00:40:55.504149 [CA 4] Center 36 (7~66) winsize 60
7534 00:40:55.507701 [CA 5] Center 36 (6~66) winsize 61
7535 00:40:55.507794
7536 00:40:55.510997 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7537 00:40:55.511083
7538 00:40:55.517192 [CATrainingPosCal] consider 1 rank data
7539 00:40:55.517289 u2DelayCellTimex100 = 262/100 ps
7540 00:40:55.524134 CA0 delay=43 (12~74),Diff = 7 PI (26 cell)
7541 00:40:55.527071 CA1 delay=43 (13~73),Diff = 7 PI (26 cell)
7542 00:40:55.530382 CA2 delay=38 (9~68),Diff = 2 PI (7 cell)
7543 00:40:55.533687 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7544 00:40:55.537130 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7545 00:40:55.540742 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7546 00:40:55.540821
7547 00:40:55.543774 CA PerBit enable=1, Macro0, CA PI delay=36
7548 00:40:55.543875
7549 00:40:55.546905 [CBTSetCACLKResult] CA Dly = 36
7550 00:40:55.550142 CS Dly: 11 (0~42)
7551 00:40:55.553346 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7552 00:40:55.556948 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7553 00:40:55.557028 ==
7554 00:40:55.560232 Dram Type= 6, Freq= 0, CH_0, rank 1
7555 00:40:55.566662 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7556 00:40:55.566746 ==
7557 00:40:55.570110 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7558 00:40:55.576947 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7559 00:40:55.579695 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7560 00:40:55.586473 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7561 00:40:55.594427 [CA 0] Center 43 (13~74) winsize 62
7562 00:40:55.598053 [CA 1] Center 44 (14~74) winsize 61
7563 00:40:55.600939 [CA 2] Center 38 (9~68) winsize 60
7564 00:40:55.603944 [CA 3] Center 38 (9~68) winsize 60
7565 00:40:55.607489 [CA 4] Center 36 (7~66) winsize 60
7566 00:40:55.611360 [CA 5] Center 36 (6~66) winsize 61
7567 00:40:55.611439
7568 00:40:55.614462 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7569 00:40:55.614541
7570 00:40:55.617588 [CATrainingPosCal] consider 2 rank data
7571 00:40:55.620581 u2DelayCellTimex100 = 262/100 ps
7572 00:40:55.627269 CA0 delay=43 (13~74),Diff = 7 PI (26 cell)
7573 00:40:55.630690 CA1 delay=43 (14~73),Diff = 7 PI (26 cell)
7574 00:40:55.634277 CA2 delay=38 (9~68),Diff = 2 PI (7 cell)
7575 00:40:55.637511 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7576 00:40:55.640487 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7577 00:40:55.643976 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7578 00:40:55.644055
7579 00:40:55.646966 CA PerBit enable=1, Macro0, CA PI delay=36
7580 00:40:55.647040
7581 00:40:55.650861 [CBTSetCACLKResult] CA Dly = 36
7582 00:40:55.653951 CS Dly: 11 (0~43)
7583 00:40:55.656886 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7584 00:40:55.660294 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7585 00:40:55.660387
7586 00:40:55.663865 ----->DramcWriteLeveling(PI) begin...
7587 00:40:55.663966 ==
7588 00:40:55.666933 Dram Type= 6, Freq= 0, CH_0, rank 0
7589 00:40:55.673310 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7590 00:40:55.673389 ==
7591 00:40:55.676662 Write leveling (Byte 0): 34 => 34
7592 00:40:55.680261 Write leveling (Byte 1): 26 => 26
7593 00:40:55.680339 DramcWriteLeveling(PI) end<-----
7594 00:40:55.683387
7595 00:40:55.683465 ==
7596 00:40:55.686800 Dram Type= 6, Freq= 0, CH_0, rank 0
7597 00:40:55.690092 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7598 00:40:55.690229 ==
7599 00:40:55.693869 [Gating] SW mode calibration
7600 00:40:55.699954 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7601 00:40:55.703225 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7602 00:40:55.710087 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7603 00:40:55.713111 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7604 00:40:55.716654 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7605 00:40:55.723201 1 4 12 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
7606 00:40:55.726733 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7607 00:40:55.729880 1 4 20 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)
7608 00:40:55.735998 1 4 24 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
7609 00:40:55.740023 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7610 00:40:55.742936 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7611 00:40:55.749259 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7612 00:40:55.752726 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7613 00:40:55.755771 1 5 12 | B1->B0 | 3434 2b2b | 1 0 | (1 1) (0 0)
7614 00:40:55.762712 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7615 00:40:55.765744 1 5 20 | B1->B0 | 3333 2323 | 0 0 | (0 1) (0 0)
7616 00:40:55.769038 1 5 24 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
7617 00:40:55.775477 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7618 00:40:55.778587 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7619 00:40:55.785845 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7620 00:40:55.788651 1 6 8 | B1->B0 | 2323 2524 | 0 1 | (0 0) (0 0)
7621 00:40:55.792171 1 6 12 | B1->B0 | 2323 3535 | 0 1 | (0 0) (0 0)
7622 00:40:55.798776 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7623 00:40:55.801883 1 6 20 | B1->B0 | 2e2e 4646 | 0 0 | (0 0) (0 0)
7624 00:40:55.805038 1 6 24 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
7625 00:40:55.811646 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7626 00:40:55.814874 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7627 00:40:55.818088 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7628 00:40:55.824999 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7629 00:40:55.828269 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7630 00:40:55.831439 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7631 00:40:55.838118 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7632 00:40:55.841105 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7633 00:40:55.845124 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7634 00:40:55.851498 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7635 00:40:55.854726 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7636 00:40:55.857723 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7637 00:40:55.864660 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7638 00:40:55.867943 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7639 00:40:55.871240 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7640 00:40:55.877321 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7641 00:40:55.880858 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7642 00:40:55.884228 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7643 00:40:55.890769 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7644 00:40:55.893725 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7645 00:40:55.897303 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7646 00:40:55.903687 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7647 00:40:55.903766 Total UI for P1: 0, mck2ui 16
7648 00:40:55.910865 best dqsien dly found for B0: ( 1, 9, 10)
7649 00:40:55.913892 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7650 00:40:55.917260 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7651 00:40:55.923733 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7652 00:40:55.923821 Total UI for P1: 0, mck2ui 16
7653 00:40:55.926889 best dqsien dly found for B1: ( 1, 9, 20)
7654 00:40:55.933396 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7655 00:40:55.936936 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7656 00:40:55.937015
7657 00:40:55.940441 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7658 00:40:55.943895 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7659 00:40:55.946802 [Gating] SW calibration Done
7660 00:40:55.946879 ==
7661 00:40:55.949853 Dram Type= 6, Freq= 0, CH_0, rank 0
7662 00:40:55.953504 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7663 00:40:55.953580 ==
7664 00:40:55.956822 RX Vref Scan: 0
7665 00:40:55.956917
7666 00:40:55.957008 RX Vref 0 -> 0, step: 1
7667 00:40:55.957090
7668 00:40:55.960150 RX Delay 0 -> 252, step: 8
7669 00:40:55.963555 iDelay=200, Bit 0, Center 135 (88 ~ 183) 96
7670 00:40:55.970087 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7671 00:40:55.973053 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
7672 00:40:55.976257 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7673 00:40:55.980220 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7674 00:40:55.983354 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7675 00:40:55.989725 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
7676 00:40:55.992937 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7677 00:40:55.996241 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7678 00:40:55.999592 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7679 00:40:56.002976 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
7680 00:40:56.009658 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7681 00:40:56.012691 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7682 00:40:56.016415 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7683 00:40:56.019627 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7684 00:40:56.022930 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7685 00:40:56.026245 ==
7686 00:40:56.029280 Dram Type= 6, Freq= 0, CH_0, rank 0
7687 00:40:56.032750 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7688 00:40:56.032823 ==
7689 00:40:56.032884 DQS Delay:
7690 00:40:56.036238 DQS0 = 0, DQS1 = 0
7691 00:40:56.036331 DQM Delay:
7692 00:40:56.039816 DQM0 = 135, DQM1 = 126
7693 00:40:56.039897 DQ Delay:
7694 00:40:56.042881 DQ0 =135, DQ1 =139, DQ2 =131, DQ3 =131
7695 00:40:56.046157 DQ4 =135, DQ5 =123, DQ6 =143, DQ7 =147
7696 00:40:56.049416 DQ8 =119, DQ9 =115, DQ10 =127, DQ11 =119
7697 00:40:56.052872 DQ12 =131, DQ13 =135, DQ14 =135, DQ15 =131
7698 00:40:56.052976
7699 00:40:56.053067
7700 00:40:56.056305 ==
7701 00:40:56.056383 Dram Type= 6, Freq= 0, CH_0, rank 0
7702 00:40:56.062673 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7703 00:40:56.062753 ==
7704 00:40:56.062815
7705 00:40:56.062873
7706 00:40:56.065757 TX Vref Scan disable
7707 00:40:56.065836 == TX Byte 0 ==
7708 00:40:56.069330 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7709 00:40:56.075629 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
7710 00:40:56.075709 == TX Byte 1 ==
7711 00:40:56.078919 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7712 00:40:56.085752 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7713 00:40:56.085830 ==
7714 00:40:56.088797 Dram Type= 6, Freq= 0, CH_0, rank 0
7715 00:40:56.091854 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7716 00:40:56.091934 ==
7717 00:40:56.106283
7718 00:40:56.108889 TX Vref early break, caculate TX vref
7719 00:40:56.112657 TX Vref=16, minBit 0, minWin=23, winSum=372
7720 00:40:56.115780 TX Vref=18, minBit 8, minWin=22, winSum=378
7721 00:40:56.119043 TX Vref=20, minBit 1, minWin=23, winSum=387
7722 00:40:56.122395 TX Vref=22, minBit 1, minWin=24, winSum=399
7723 00:40:56.125424 TX Vref=24, minBit 4, minWin=24, winSum=409
7724 00:40:56.132285 TX Vref=26, minBit 0, minWin=25, winSum=414
7725 00:40:56.135528 TX Vref=28, minBit 1, minWin=25, winSum=414
7726 00:40:56.138862 TX Vref=30, minBit 4, minWin=24, winSum=412
7727 00:40:56.142090 TX Vref=32, minBit 4, minWin=23, winSum=399
7728 00:40:56.145507 TX Vref=34, minBit 4, minWin=23, winSum=388
7729 00:40:56.152189 [TxChooseVref] Worse bit 0, Min win 25, Win sum 414, Final Vref 26
7730 00:40:56.152270
7731 00:40:56.155430 Final TX Range 0 Vref 26
7732 00:40:56.155502
7733 00:40:56.155563 ==
7734 00:40:56.158579 Dram Type= 6, Freq= 0, CH_0, rank 0
7735 00:40:56.161761 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7736 00:40:56.161830 ==
7737 00:40:56.161890
7738 00:40:56.161946
7739 00:40:56.165400 TX Vref Scan disable
7740 00:40:56.171779 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
7741 00:40:56.171858 == TX Byte 0 ==
7742 00:40:56.175439 u2DelayCellOfst[0]=14 cells (4 PI)
7743 00:40:56.178248 u2DelayCellOfst[1]=18 cells (5 PI)
7744 00:40:56.181439 u2DelayCellOfst[2]=14 cells (4 PI)
7745 00:40:56.184936 u2DelayCellOfst[3]=14 cells (4 PI)
7746 00:40:56.187974 u2DelayCellOfst[4]=11 cells (3 PI)
7747 00:40:56.191427 u2DelayCellOfst[5]=0 cells (0 PI)
7748 00:40:56.194872 u2DelayCellOfst[6]=18 cells (5 PI)
7749 00:40:56.198180 u2DelayCellOfst[7]=22 cells (6 PI)
7750 00:40:56.201406 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
7751 00:40:56.205023 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
7752 00:40:56.208251 == TX Byte 1 ==
7753 00:40:56.211469 u2DelayCellOfst[8]=0 cells (0 PI)
7754 00:40:56.214437 u2DelayCellOfst[9]=3 cells (1 PI)
7755 00:40:56.217727 u2DelayCellOfst[10]=7 cells (2 PI)
7756 00:40:56.220953 u2DelayCellOfst[11]=3 cells (1 PI)
7757 00:40:56.221032 u2DelayCellOfst[12]=11 cells (3 PI)
7758 00:40:56.224269 u2DelayCellOfst[13]=14 cells (4 PI)
7759 00:40:56.227698 u2DelayCellOfst[14]=14 cells (4 PI)
7760 00:40:56.231047 u2DelayCellOfst[15]=11 cells (3 PI)
7761 00:40:56.237883 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
7762 00:40:56.240986 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7763 00:40:56.241066 DramC Write-DBI on
7764 00:40:56.244349 ==
7765 00:40:56.247863 Dram Type= 6, Freq= 0, CH_0, rank 0
7766 00:40:56.251080 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7767 00:40:56.251160 ==
7768 00:40:56.251223
7769 00:40:56.251280
7770 00:40:56.253892 TX Vref Scan disable
7771 00:40:56.253997 == TX Byte 0 ==
7772 00:40:56.260825 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
7773 00:40:56.260905 == TX Byte 1 ==
7774 00:40:56.264020 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
7775 00:40:56.267138 DramC Write-DBI off
7776 00:40:56.267217
7777 00:40:56.267280 [DATLAT]
7778 00:40:56.270478 Freq=1600, CH0 RK0
7779 00:40:56.270583
7780 00:40:56.270673 DATLAT Default: 0xf
7781 00:40:56.273591 0, 0xFFFF, sum = 0
7782 00:40:56.273671 1, 0xFFFF, sum = 0
7783 00:40:56.276944 2, 0xFFFF, sum = 0
7784 00:40:56.280364 3, 0xFFFF, sum = 0
7785 00:40:56.280445 4, 0xFFFF, sum = 0
7786 00:40:56.283623 5, 0xFFFF, sum = 0
7787 00:40:56.283704 6, 0xFFFF, sum = 0
7788 00:40:56.286969 7, 0xFFFF, sum = 0
7789 00:40:56.287050 8, 0xFFFF, sum = 0
7790 00:40:56.290045 9, 0xFFFF, sum = 0
7791 00:40:56.290151 10, 0xFFFF, sum = 0
7792 00:40:56.293648 11, 0xFFFF, sum = 0
7793 00:40:56.293728 12, 0xFFFF, sum = 0
7794 00:40:56.296492 13, 0xFFFF, sum = 0
7795 00:40:56.296573 14, 0x0, sum = 1
7796 00:40:56.300057 15, 0x0, sum = 2
7797 00:40:56.300138 16, 0x0, sum = 3
7798 00:40:56.303183 17, 0x0, sum = 4
7799 00:40:56.303263 best_step = 15
7800 00:40:56.303381
7801 00:40:56.303482 ==
7802 00:40:56.306738 Dram Type= 6, Freq= 0, CH_0, rank 0
7803 00:40:56.313005 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7804 00:40:56.313085 ==
7805 00:40:56.313147 RX Vref Scan: 1
7806 00:40:56.313207
7807 00:40:56.316799 Set Vref Range= 24 -> 127
7808 00:40:56.316878
7809 00:40:56.320173 RX Vref 24 -> 127, step: 1
7810 00:40:56.320250
7811 00:40:56.320313 RX Delay 19 -> 252, step: 4
7812 00:40:56.323230
7813 00:40:56.323308 Set Vref, RX VrefLevel [Byte0]: 24
7814 00:40:56.326193 [Byte1]: 24
7815 00:40:56.330393
7816 00:40:56.330473 Set Vref, RX VrefLevel [Byte0]: 25
7817 00:40:56.334001 [Byte1]: 25
7818 00:40:56.338526
7819 00:40:56.338604 Set Vref, RX VrefLevel [Byte0]: 26
7820 00:40:56.341943 [Byte1]: 26
7821 00:40:56.345817
7822 00:40:56.345895 Set Vref, RX VrefLevel [Byte0]: 27
7823 00:40:56.349165 [Byte1]: 27
7824 00:40:56.353649
7825 00:40:56.353727 Set Vref, RX VrefLevel [Byte0]: 28
7826 00:40:56.356434 [Byte1]: 28
7827 00:40:56.361034
7828 00:40:56.361112 Set Vref, RX VrefLevel [Byte0]: 29
7829 00:40:56.364302 [Byte1]: 29
7830 00:40:56.368363
7831 00:40:56.368442 Set Vref, RX VrefLevel [Byte0]: 30
7832 00:40:56.371600 [Byte1]: 30
7833 00:40:56.376042
7834 00:40:56.376120 Set Vref, RX VrefLevel [Byte0]: 31
7835 00:40:56.379202 [Byte1]: 31
7836 00:40:56.383662
7837 00:40:56.383740 Set Vref, RX VrefLevel [Byte0]: 32
7838 00:40:56.386826 [Byte1]: 32
7839 00:40:56.391210
7840 00:40:56.391288 Set Vref, RX VrefLevel [Byte0]: 33
7841 00:40:56.394522 [Byte1]: 33
7842 00:40:56.398969
7843 00:40:56.399061 Set Vref, RX VrefLevel [Byte0]: 34
7844 00:40:56.401972 [Byte1]: 34
7845 00:40:56.406299
7846 00:40:56.406377 Set Vref, RX VrefLevel [Byte0]: 35
7847 00:40:56.412805 [Byte1]: 35
7848 00:40:56.412906
7849 00:40:56.416240 Set Vref, RX VrefLevel [Byte0]: 36
7850 00:40:56.419430 [Byte1]: 36
7851 00:40:56.419549
7852 00:40:56.422625 Set Vref, RX VrefLevel [Byte0]: 37
7853 00:40:56.425890 [Byte1]: 37
7854 00:40:56.425969
7855 00:40:56.429530 Set Vref, RX VrefLevel [Byte0]: 38
7856 00:40:56.432711 [Byte1]: 38
7857 00:40:56.436690
7858 00:40:56.436803 Set Vref, RX VrefLevel [Byte0]: 39
7859 00:40:56.440046 [Byte1]: 39
7860 00:40:56.444040
7861 00:40:56.444145 Set Vref, RX VrefLevel [Byte0]: 40
7862 00:40:56.447346 [Byte1]: 40
7863 00:40:56.451783
7864 00:40:56.451862 Set Vref, RX VrefLevel [Byte0]: 41
7865 00:40:56.455511 [Byte1]: 41
7866 00:40:56.459167
7867 00:40:56.459278 Set Vref, RX VrefLevel [Byte0]: 42
7868 00:40:56.462622 [Byte1]: 42
7869 00:40:56.466810
7870 00:40:56.466889 Set Vref, RX VrefLevel [Byte0]: 43
7871 00:40:56.470399 [Byte1]: 43
7872 00:40:56.474557
7873 00:40:56.474636 Set Vref, RX VrefLevel [Byte0]: 44
7874 00:40:56.478252 [Byte1]: 44
7875 00:40:56.482313
7876 00:40:56.482392 Set Vref, RX VrefLevel [Byte0]: 45
7877 00:40:56.485655 [Byte1]: 45
7878 00:40:56.489701
7879 00:40:56.489780 Set Vref, RX VrefLevel [Byte0]: 46
7880 00:40:56.493208 [Byte1]: 46
7881 00:40:56.497463
7882 00:40:56.497542 Set Vref, RX VrefLevel [Byte0]: 47
7883 00:40:56.500324 [Byte1]: 47
7884 00:40:56.505005
7885 00:40:56.505084 Set Vref, RX VrefLevel [Byte0]: 48
7886 00:40:56.508293 [Byte1]: 48
7887 00:40:56.512500
7888 00:40:56.512579 Set Vref, RX VrefLevel [Byte0]: 49
7889 00:40:56.515867 [Byte1]: 49
7890 00:40:56.520229
7891 00:40:56.520308 Set Vref, RX VrefLevel [Byte0]: 50
7892 00:40:56.523148 [Byte1]: 50
7893 00:40:56.527684
7894 00:40:56.527763 Set Vref, RX VrefLevel [Byte0]: 51
7895 00:40:56.530522 [Byte1]: 51
7896 00:40:56.535319
7897 00:40:56.535398 Set Vref, RX VrefLevel [Byte0]: 52
7898 00:40:56.538241 [Byte1]: 52
7899 00:40:56.542764
7900 00:40:56.542842 Set Vref, RX VrefLevel [Byte0]: 53
7901 00:40:56.546089 [Byte1]: 53
7902 00:40:56.550379
7903 00:40:56.550459 Set Vref, RX VrefLevel [Byte0]: 54
7904 00:40:56.553336 [Byte1]: 54
7905 00:40:56.557873
7906 00:40:56.557952 Set Vref, RX VrefLevel [Byte0]: 55
7907 00:40:56.561347 [Byte1]: 55
7908 00:40:56.565186
7909 00:40:56.565265 Set Vref, RX VrefLevel [Byte0]: 56
7910 00:40:56.568532 [Byte1]: 56
7911 00:40:56.573176
7912 00:40:56.573255 Set Vref, RX VrefLevel [Byte0]: 57
7913 00:40:56.576098 [Byte1]: 57
7914 00:40:56.580385
7915 00:40:56.580465 Set Vref, RX VrefLevel [Byte0]: 58
7916 00:40:56.583698 [Byte1]: 58
7917 00:40:56.588172
7918 00:40:56.588267 Set Vref, RX VrefLevel [Byte0]: 59
7919 00:40:56.591369 [Byte1]: 59
7920 00:40:56.595644
7921 00:40:56.595746 Set Vref, RX VrefLevel [Byte0]: 60
7922 00:40:56.598690 [Byte1]: 60
7923 00:40:56.603201
7924 00:40:56.603280 Set Vref, RX VrefLevel [Byte0]: 61
7925 00:40:56.606478 [Byte1]: 61
7926 00:40:56.610604
7927 00:40:56.610683 Set Vref, RX VrefLevel [Byte0]: 62
7928 00:40:56.613903 [Byte1]: 62
7929 00:40:56.618215
7930 00:40:56.618294 Set Vref, RX VrefLevel [Byte0]: 63
7931 00:40:56.621529 [Byte1]: 63
7932 00:40:56.625855
7933 00:40:56.625934 Set Vref, RX VrefLevel [Byte0]: 64
7934 00:40:56.629093 [Byte1]: 64
7935 00:40:56.633658
7936 00:40:56.633737 Set Vref, RX VrefLevel [Byte0]: 65
7937 00:40:56.636954 [Byte1]: 65
7938 00:40:56.641148
7939 00:40:56.641227 Set Vref, RX VrefLevel [Byte0]: 66
7940 00:40:56.644163 [Byte1]: 66
7941 00:40:56.649002
7942 00:40:56.649080 Set Vref, RX VrefLevel [Byte0]: 67
7943 00:40:56.651902 [Byte1]: 67
7944 00:40:56.656167
7945 00:40:56.656247 Set Vref, RX VrefLevel [Byte0]: 68
7946 00:40:56.659241 [Byte1]: 68
7947 00:40:56.663788
7948 00:40:56.663867 Set Vref, RX VrefLevel [Byte0]: 69
7949 00:40:56.666977 [Byte1]: 69
7950 00:40:56.671374
7951 00:40:56.671452 Set Vref, RX VrefLevel [Byte0]: 70
7952 00:40:56.674765 [Byte1]: 70
7953 00:40:56.678779
7954 00:40:56.678858 Set Vref, RX VrefLevel [Byte0]: 71
7955 00:40:56.682467 [Byte1]: 71
7956 00:40:56.686598
7957 00:40:56.686677 Set Vref, RX VrefLevel [Byte0]: 72
7958 00:40:56.689861 [Byte1]: 72
7959 00:40:56.694308
7960 00:40:56.694387 Set Vref, RX VrefLevel [Byte0]: 73
7961 00:40:56.697383 [Byte1]: 73
7962 00:40:56.701600
7963 00:40:56.701679 Set Vref, RX VrefLevel [Byte0]: 74
7964 00:40:56.704959 [Byte1]: 74
7965 00:40:56.709327
7966 00:40:56.709406 Set Vref, RX VrefLevel [Byte0]: 75
7967 00:40:56.712343 [Byte1]: 75
7968 00:40:56.716781
7969 00:40:56.716890 Set Vref, RX VrefLevel [Byte0]: 76
7970 00:40:56.719850 [Byte1]: 76
7971 00:40:56.724627
7972 00:40:56.724706 Set Vref, RX VrefLevel [Byte0]: 77
7973 00:40:56.727981 [Byte1]: 77
7974 00:40:56.731837
7975 00:40:56.731916 Set Vref, RX VrefLevel [Byte0]: 78
7976 00:40:56.735013 [Byte1]: 78
7977 00:40:56.739351
7978 00:40:56.742794 Set Vref, RX VrefLevel [Byte0]: 79
7979 00:40:56.746200 [Byte1]: 79
7980 00:40:56.746294
7981 00:40:56.749607 Final RX Vref Byte 0 = 66 to rank0
7982 00:40:56.752408 Final RX Vref Byte 1 = 57 to rank0
7983 00:40:56.756189 Final RX Vref Byte 0 = 66 to rank1
7984 00:40:56.759026 Final RX Vref Byte 1 = 57 to rank1==
7985 00:40:56.762314 Dram Type= 6, Freq= 0, CH_0, rank 0
7986 00:40:56.765802 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7987 00:40:56.765886 ==
7988 00:40:56.765950 DQS Delay:
7989 00:40:56.769382 DQS0 = 0, DQS1 = 0
7990 00:40:56.769461 DQM Delay:
7991 00:40:56.772431 DQM0 = 133, DQM1 = 122
7992 00:40:56.772511 DQ Delay:
7993 00:40:56.775819 DQ0 =130, DQ1 =136, DQ2 =132, DQ3 =132
7994 00:40:56.779335 DQ4 =134, DQ5 =122, DQ6 =140, DQ7 =142
7995 00:40:56.782461 DQ8 =114, DQ9 =110, DQ10 =122, DQ11 =118
7996 00:40:56.785780 DQ12 =128, DQ13 =126, DQ14 =134, DQ15 =128
7997 00:40:56.785859
7998 00:40:56.785921
7999 00:40:56.789162
8000 00:40:56.789241 [DramC_TX_OE_Calibration] TA2
8001 00:40:56.792143 Original DQ_B0 (3 6) =30, OEN = 27
8002 00:40:56.795397 Original DQ_B1 (3 6) =30, OEN = 27
8003 00:40:56.798943 24, 0x0, End_B0=24 End_B1=24
8004 00:40:56.802572 25, 0x0, End_B0=25 End_B1=25
8005 00:40:56.805457 26, 0x0, End_B0=26 End_B1=26
8006 00:40:56.805537 27, 0x0, End_B0=27 End_B1=27
8007 00:40:56.808839 28, 0x0, End_B0=28 End_B1=28
8008 00:40:56.812061 29, 0x0, End_B0=29 End_B1=29
8009 00:40:56.815222 30, 0x0, End_B0=30 End_B1=30
8010 00:40:56.818529 31, 0x4141, End_B0=30 End_B1=30
8011 00:40:56.818609 Byte0 end_step=30 best_step=27
8012 00:40:56.821877 Byte1 end_step=30 best_step=27
8013 00:40:56.825045 Byte0 TX OE(2T, 0.5T) = (3, 3)
8014 00:40:56.828602 Byte1 TX OE(2T, 0.5T) = (3, 3)
8015 00:40:56.828682
8016 00:40:56.828744
8017 00:40:56.838459 [DQSOSCAuto] RK0, (LSB)MR18= 0x2516, (MSB)MR19= 0x303, tDQSOscB0 = 398 ps tDQSOscB1 = 391 ps
8018 00:40:56.838566 CH0 RK0: MR19=303, MR18=2516
8019 00:40:56.844964 CH0_RK0: MR19=0x303, MR18=0x2516, DQSOSC=391, MR23=63, INC=24, DEC=16
8020 00:40:56.845046
8021 00:40:56.848190 ----->DramcWriteLeveling(PI) begin...
8022 00:40:56.848272 ==
8023 00:40:56.851792 Dram Type= 6, Freq= 0, CH_0, rank 1
8024 00:40:56.858506 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8025 00:40:56.858587 ==
8026 00:40:56.861510 Write leveling (Byte 0): 36 => 36
8027 00:40:56.864906 Write leveling (Byte 1): 28 => 28
8028 00:40:56.864986 DramcWriteLeveling(PI) end<-----
8029 00:40:56.865049
8030 00:40:56.868085 ==
8031 00:40:56.871490 Dram Type= 6, Freq= 0, CH_0, rank 1
8032 00:40:56.874765 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8033 00:40:56.874890 ==
8034 00:40:56.877859 [Gating] SW mode calibration
8035 00:40:56.884640 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8036 00:40:56.888008 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8037 00:40:56.894109 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8038 00:40:56.897843 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8039 00:40:56.900778 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8040 00:40:56.907652 1 4 12 | B1->B0 | 2323 2423 | 0 1 | (0 0) (0 0)
8041 00:40:56.910787 1 4 16 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (1 1)
8042 00:40:56.914280 1 4 20 | B1->B0 | 2d2d 3434 | 1 1 | (1 1) (1 1)
8043 00:40:56.920963 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8044 00:40:56.924030 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8045 00:40:56.927508 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8046 00:40:56.933875 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8047 00:40:56.937616 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8048 00:40:56.940729 1 5 12 | B1->B0 | 3434 3232 | 1 0 | (1 0) (0 1)
8049 00:40:56.947338 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (1 0)
8050 00:40:56.950451 1 5 20 | B1->B0 | 2a2a 2323 | 0 0 | (1 1) (0 0)
8051 00:40:56.953851 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8052 00:40:56.960574 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8053 00:40:56.963700 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8054 00:40:56.967026 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8055 00:40:56.973326 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8056 00:40:56.976725 1 6 12 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
8057 00:40:56.980145 1 6 16 | B1->B0 | 2727 4545 | 1 0 | (0 0) (0 0)
8058 00:40:56.986582 1 6 20 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
8059 00:40:56.989981 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8060 00:40:56.993097 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8061 00:40:57.000189 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8062 00:40:57.002678 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8063 00:40:57.009202 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8064 00:40:57.012682 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8065 00:40:57.015931 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8066 00:40:57.022471 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8067 00:40:57.025911 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8068 00:40:57.029356 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8069 00:40:57.035933 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8070 00:40:57.038976 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8071 00:40:57.042977 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8072 00:40:57.048926 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8073 00:40:57.052138 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8074 00:40:57.056108 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8075 00:40:57.059239 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8076 00:40:57.065857 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8077 00:40:57.068810 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8078 00:40:57.072294 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8079 00:40:57.079012 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8080 00:40:57.082331 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8081 00:40:57.085776 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8082 00:40:57.089221 Total UI for P1: 0, mck2ui 16
8083 00:40:57.092594 best dqsien dly found for B0: ( 1, 9, 12)
8084 00:40:57.099214 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8085 00:40:57.102082 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8086 00:40:57.105419 Total UI for P1: 0, mck2ui 16
8087 00:40:57.108619 best dqsien dly found for B1: ( 1, 9, 18)
8088 00:40:57.111926 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8089 00:40:57.115409 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8090 00:40:57.115488
8091 00:40:57.118695 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8092 00:40:57.125164 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8093 00:40:57.125240 [Gating] SW calibration Done
8094 00:40:57.125301 ==
8095 00:40:57.128724 Dram Type= 6, Freq= 0, CH_0, rank 1
8096 00:40:57.135266 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8097 00:40:57.135344 ==
8098 00:40:57.135407 RX Vref Scan: 0
8099 00:40:57.135465
8100 00:40:57.138673 RX Vref 0 -> 0, step: 1
8101 00:40:57.138751
8102 00:40:57.141853 RX Delay 0 -> 252, step: 8
8103 00:40:57.145303 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8104 00:40:57.148844 iDelay=200, Bit 1, Center 139 (80 ~ 199) 120
8105 00:40:57.151985 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8106 00:40:57.155163 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8107 00:40:57.162001 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8108 00:40:57.165156 iDelay=200, Bit 5, Center 123 (64 ~ 183) 120
8109 00:40:57.168300 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8110 00:40:57.171754 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8111 00:40:57.174798 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8112 00:40:57.181445 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8113 00:40:57.184906 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8114 00:40:57.188352 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8115 00:40:57.191548 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8116 00:40:57.198051 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8117 00:40:57.201627 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120
8118 00:40:57.204696 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8119 00:40:57.204780 ==
8120 00:40:57.207824 Dram Type= 6, Freq= 0, CH_0, rank 1
8121 00:40:57.210983 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8122 00:40:57.211068 ==
8123 00:40:57.214280 DQS Delay:
8124 00:40:57.214356 DQS0 = 0, DQS1 = 0
8125 00:40:57.217686 DQM Delay:
8126 00:40:57.217768 DQM0 = 133, DQM1 = 128
8127 00:40:57.220865 DQ Delay:
8128 00:40:57.224065 DQ0 =135, DQ1 =139, DQ2 =127, DQ3 =127
8129 00:40:57.227453 DQ4 =135, DQ5 =123, DQ6 =139, DQ7 =143
8130 00:40:57.230941 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =123
8131 00:40:57.233902 DQ12 =135, DQ13 =135, DQ14 =139, DQ15 =135
8132 00:40:57.233976
8133 00:40:57.234081
8134 00:40:57.234205 ==
8135 00:40:57.237228 Dram Type= 6, Freq= 0, CH_0, rank 1
8136 00:40:57.240455 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8137 00:40:57.240536 ==
8138 00:40:57.243822
8139 00:40:57.243893
8140 00:40:57.243953 TX Vref Scan disable
8141 00:40:57.247227 == TX Byte 0 ==
8142 00:40:57.250341 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8143 00:40:57.253640 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8144 00:40:57.256973 == TX Byte 1 ==
8145 00:40:57.260357 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8146 00:40:57.263550 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8147 00:40:57.263629 ==
8148 00:40:57.266762 Dram Type= 6, Freq= 0, CH_0, rank 1
8149 00:40:57.273271 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8150 00:40:57.273350 ==
8151 00:40:57.286488
8152 00:40:57.289386 TX Vref early break, caculate TX vref
8153 00:40:57.292841 TX Vref=16, minBit 3, minWin=22, winSum=378
8154 00:40:57.296140 TX Vref=18, minBit 0, minWin=23, winSum=388
8155 00:40:57.299519 TX Vref=20, minBit 1, minWin=23, winSum=390
8156 00:40:57.302987 TX Vref=22, minBit 0, minWin=24, winSum=403
8157 00:40:57.306272 TX Vref=24, minBit 0, minWin=25, winSum=411
8158 00:40:57.312849 TX Vref=26, minBit 3, minWin=24, winSum=412
8159 00:40:57.316357 TX Vref=28, minBit 4, minWin=24, winSum=412
8160 00:40:57.319141 TX Vref=30, minBit 0, minWin=24, winSum=406
8161 00:40:57.322493 TX Vref=32, minBit 0, minWin=24, winSum=399
8162 00:40:57.326018 TX Vref=34, minBit 0, minWin=23, winSum=384
8163 00:40:57.332165 [TxChooseVref] Worse bit 0, Min win 25, Win sum 411, Final Vref 24
8164 00:40:57.332257
8165 00:40:57.335510 Final TX Range 0 Vref 24
8166 00:40:57.335592
8167 00:40:57.335694 ==
8168 00:40:57.339251 Dram Type= 6, Freq= 0, CH_0, rank 1
8169 00:40:57.342068 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8170 00:40:57.342147 ==
8171 00:40:57.342265
8172 00:40:57.342340
8173 00:40:57.345773 TX Vref Scan disable
8174 00:40:57.352333 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8175 00:40:57.352414 == TX Byte 0 ==
8176 00:40:57.355221 u2DelayCellOfst[0]=14 cells (4 PI)
8177 00:40:57.358956 u2DelayCellOfst[1]=18 cells (5 PI)
8178 00:40:57.361919 u2DelayCellOfst[2]=14 cells (4 PI)
8179 00:40:57.365306 u2DelayCellOfst[3]=14 cells (4 PI)
8180 00:40:57.368832 u2DelayCellOfst[4]=11 cells (3 PI)
8181 00:40:57.372153 u2DelayCellOfst[5]=0 cells (0 PI)
8182 00:40:57.375270 u2DelayCellOfst[6]=18 cells (5 PI)
8183 00:40:57.378718 u2DelayCellOfst[7]=18 cells (5 PI)
8184 00:40:57.381859 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8185 00:40:57.385180 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8186 00:40:57.388459 == TX Byte 1 ==
8187 00:40:57.391741 u2DelayCellOfst[8]=0 cells (0 PI)
8188 00:40:57.394735 u2DelayCellOfst[9]=0 cells (0 PI)
8189 00:40:57.398617 u2DelayCellOfst[10]=7 cells (2 PI)
8190 00:40:57.401788 u2DelayCellOfst[11]=0 cells (0 PI)
8191 00:40:57.401863 u2DelayCellOfst[12]=11 cells (3 PI)
8192 00:40:57.405155 u2DelayCellOfst[13]=11 cells (3 PI)
8193 00:40:57.407959 u2DelayCellOfst[14]=18 cells (5 PI)
8194 00:40:57.411467 u2DelayCellOfst[15]=11 cells (3 PI)
8195 00:40:57.418402 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8196 00:40:57.421276 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8197 00:40:57.421357 DramC Write-DBI on
8198 00:40:57.424492 ==
8199 00:40:57.428021 Dram Type= 6, Freq= 0, CH_0, rank 1
8200 00:40:57.431277 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8201 00:40:57.431356 ==
8202 00:40:57.431418
8203 00:40:57.431475
8204 00:40:57.435183 TX Vref Scan disable
8205 00:40:57.435262 == TX Byte 0 ==
8206 00:40:57.440971 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
8207 00:40:57.441050 == TX Byte 1 ==
8208 00:40:57.444302 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8209 00:40:57.447878 DramC Write-DBI off
8210 00:40:57.447957
8211 00:40:57.448018 [DATLAT]
8212 00:40:57.450974 Freq=1600, CH0 RK1
8213 00:40:57.451052
8214 00:40:57.451114 DATLAT Default: 0xf
8215 00:40:57.454083 0, 0xFFFF, sum = 0
8216 00:40:57.454173 1, 0xFFFF, sum = 0
8217 00:40:57.457477 2, 0xFFFF, sum = 0
8218 00:40:57.460815 3, 0xFFFF, sum = 0
8219 00:40:57.460895 4, 0xFFFF, sum = 0
8220 00:40:57.464509 5, 0xFFFF, sum = 0
8221 00:40:57.464589 6, 0xFFFF, sum = 0
8222 00:40:57.467556 7, 0xFFFF, sum = 0
8223 00:40:57.467636 8, 0xFFFF, sum = 0
8224 00:40:57.470657 9, 0xFFFF, sum = 0
8225 00:40:57.470737 10, 0xFFFF, sum = 0
8226 00:40:57.474183 11, 0xFFFF, sum = 0
8227 00:40:57.474276 12, 0xFFFF, sum = 0
8228 00:40:57.477113 13, 0xFFFF, sum = 0
8229 00:40:57.477228 14, 0x0, sum = 1
8230 00:40:57.480752 15, 0x0, sum = 2
8231 00:40:57.480879 16, 0x0, sum = 3
8232 00:40:57.484142 17, 0x0, sum = 4
8233 00:40:57.484245 best_step = 15
8234 00:40:57.484309
8235 00:40:57.484404 ==
8236 00:40:57.487446 Dram Type= 6, Freq= 0, CH_0, rank 1
8237 00:40:57.493467 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8238 00:40:57.493546 ==
8239 00:40:57.493609 RX Vref Scan: 0
8240 00:40:57.493668
8241 00:40:57.496940 RX Vref 0 -> 0, step: 1
8242 00:40:57.497018
8243 00:40:57.500363 RX Delay 11 -> 252, step: 4
8244 00:40:57.503664 iDelay=195, Bit 0, Center 128 (79 ~ 178) 100
8245 00:40:57.506758 iDelay=195, Bit 1, Center 132 (79 ~ 186) 108
8246 00:40:57.510091 iDelay=195, Bit 2, Center 124 (71 ~ 178) 108
8247 00:40:57.516469 iDelay=195, Bit 3, Center 128 (75 ~ 182) 108
8248 00:40:57.519943 iDelay=195, Bit 4, Center 130 (79 ~ 182) 104
8249 00:40:57.523342 iDelay=195, Bit 5, Center 120 (67 ~ 174) 108
8250 00:40:57.526773 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
8251 00:40:57.530343 iDelay=195, Bit 7, Center 138 (87 ~ 190) 104
8252 00:40:57.536376 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
8253 00:40:57.539690 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8254 00:40:57.542826 iDelay=195, Bit 10, Center 126 (71 ~ 182) 112
8255 00:40:57.546148 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8256 00:40:57.552981 iDelay=195, Bit 12, Center 130 (79 ~ 182) 104
8257 00:40:57.556464 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8258 00:40:57.559603 iDelay=195, Bit 14, Center 136 (83 ~ 190) 108
8259 00:40:57.562839 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8260 00:40:57.562917 ==
8261 00:40:57.566040 Dram Type= 6, Freq= 0, CH_0, rank 1
8262 00:40:57.572354 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8263 00:40:57.572462 ==
8264 00:40:57.572527 DQS Delay:
8265 00:40:57.575809 DQS0 = 0, DQS1 = 0
8266 00:40:57.575919 DQM Delay:
8267 00:40:57.579125 DQM0 = 129, DQM1 = 125
8268 00:40:57.579204 DQ Delay:
8269 00:40:57.582054 DQ0 =128, DQ1 =132, DQ2 =124, DQ3 =128
8270 00:40:57.585703 DQ4 =130, DQ5 =120, DQ6 =138, DQ7 =138
8271 00:40:57.589091 DQ8 =116, DQ9 =112, DQ10 =126, DQ11 =120
8272 00:40:57.592312 DQ12 =130, DQ13 =132, DQ14 =136, DQ15 =132
8273 00:40:57.592391
8274 00:40:57.592453
8275 00:40:57.592511
8276 00:40:57.595540 [DramC_TX_OE_Calibration] TA2
8277 00:40:57.598767 Original DQ_B0 (3 6) =30, OEN = 27
8278 00:40:57.602539 Original DQ_B1 (3 6) =30, OEN = 27
8279 00:40:57.605323 24, 0x0, End_B0=24 End_B1=24
8280 00:40:57.608758 25, 0x0, End_B0=25 End_B1=25
8281 00:40:57.608843 26, 0x0, End_B0=26 End_B1=26
8282 00:40:57.612072 27, 0x0, End_B0=27 End_B1=27
8283 00:40:57.615682 28, 0x0, End_B0=28 End_B1=28
8284 00:40:57.618917 29, 0x0, End_B0=29 End_B1=29
8285 00:40:57.618996 30, 0x0, End_B0=30 End_B1=30
8286 00:40:57.622394 31, 0x4545, End_B0=30 End_B1=30
8287 00:40:57.625434 Byte0 end_step=30 best_step=27
8288 00:40:57.628471 Byte1 end_step=30 best_step=27
8289 00:40:57.631764 Byte0 TX OE(2T, 0.5T) = (3, 3)
8290 00:40:57.635283 Byte1 TX OE(2T, 0.5T) = (3, 3)
8291 00:40:57.635361
8292 00:40:57.635428
8293 00:40:57.641955 [DQSOSCAuto] RK1, (LSB)MR18= 0x2104, (MSB)MR19= 0x303, tDQSOscB0 = 408 ps tDQSOscB1 = 393 ps
8294 00:40:57.645298 CH0 RK1: MR19=303, MR18=2104
8295 00:40:57.651824 CH0_RK1: MR19=0x303, MR18=0x2104, DQSOSC=393, MR23=63, INC=23, DEC=15
8296 00:40:57.655316 [RxdqsGatingPostProcess] freq 1600
8297 00:40:57.661482 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8298 00:40:57.661562 best DQS0 dly(2T, 0.5T) = (1, 1)
8299 00:40:57.665000 best DQS1 dly(2T, 0.5T) = (1, 1)
8300 00:40:57.668384 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8301 00:40:57.671397 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8302 00:40:57.674531 best DQS0 dly(2T, 0.5T) = (1, 1)
8303 00:40:57.678123 best DQS1 dly(2T, 0.5T) = (1, 1)
8304 00:40:57.681174 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8305 00:40:57.684686 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8306 00:40:57.687868 Pre-setting of DQS Precalculation
8307 00:40:57.691282 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8308 00:40:57.694791 ==
8309 00:40:57.694867 Dram Type= 6, Freq= 0, CH_1, rank 0
8310 00:40:57.701373 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8311 00:40:57.701456 ==
8312 00:40:57.704862 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8313 00:40:57.711353 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8314 00:40:57.714806 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8315 00:40:57.720996 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8316 00:40:57.728635 [CA 0] Center 42 (13~72) winsize 60
8317 00:40:57.732103 [CA 1] Center 42 (13~72) winsize 60
8318 00:40:57.735381 [CA 2] Center 37 (9~66) winsize 58
8319 00:40:57.738723 [CA 3] Center 37 (8~67) winsize 60
8320 00:40:57.742064 [CA 4] Center 38 (8~68) winsize 61
8321 00:40:57.745852 [CA 5] Center 37 (8~67) winsize 60
8322 00:40:57.745935
8323 00:40:57.748634 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8324 00:40:57.748706
8325 00:40:57.755256 [CATrainingPosCal] consider 1 rank data
8326 00:40:57.755334 u2DelayCellTimex100 = 262/100 ps
8327 00:40:57.761858 CA0 delay=42 (13~72),Diff = 5 PI (18 cell)
8328 00:40:57.765480 CA1 delay=42 (13~72),Diff = 5 PI (18 cell)
8329 00:40:57.768609 CA2 delay=37 (9~66),Diff = 0 PI (0 cell)
8330 00:40:57.771889 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8331 00:40:57.775544 CA4 delay=38 (8~68),Diff = 1 PI (3 cell)
8332 00:40:57.778349 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8333 00:40:57.778422
8334 00:40:57.781451 CA PerBit enable=1, Macro0, CA PI delay=37
8335 00:40:57.781520
8336 00:40:57.784865 [CBTSetCACLKResult] CA Dly = 37
8337 00:40:57.788278 CS Dly: 8 (0~39)
8338 00:40:57.791510 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8339 00:40:57.794802 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8340 00:40:57.794900 ==
8341 00:40:57.798006 Dram Type= 6, Freq= 0, CH_1, rank 1
8342 00:40:57.804972 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8343 00:40:57.805073 ==
8344 00:40:57.808341 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8345 00:40:57.811376 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8346 00:40:57.817997 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8347 00:40:57.824726 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8348 00:40:57.832084 [CA 0] Center 43 (14~72) winsize 59
8349 00:40:57.835362 [CA 1] Center 43 (13~73) winsize 61
8350 00:40:57.838784 [CA 2] Center 37 (8~67) winsize 60
8351 00:40:57.841818 [CA 3] Center 37 (8~67) winsize 60
8352 00:40:57.845374 [CA 4] Center 37 (8~67) winsize 60
8353 00:40:57.848846 [CA 5] Center 37 (8~67) winsize 60
8354 00:40:57.848945
8355 00:40:57.852381 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8356 00:40:57.852459
8357 00:40:57.858379 [CATrainingPosCal] consider 2 rank data
8358 00:40:57.858458 u2DelayCellTimex100 = 262/100 ps
8359 00:40:57.864796 CA0 delay=43 (14~72),Diff = 6 PI (22 cell)
8360 00:40:57.868194 CA1 delay=42 (13~72),Diff = 5 PI (18 cell)
8361 00:40:57.871924 CA2 delay=37 (9~66),Diff = 0 PI (0 cell)
8362 00:40:57.875186 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8363 00:40:57.878425 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
8364 00:40:57.881931 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8365 00:40:57.882035
8366 00:40:57.884837 CA PerBit enable=1, Macro0, CA PI delay=37
8367 00:40:57.884950
8368 00:40:57.888353 [CBTSetCACLKResult] CA Dly = 37
8369 00:40:57.891558 CS Dly: 10 (0~43)
8370 00:40:57.894888 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8371 00:40:57.897767 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8372 00:40:57.897864
8373 00:40:57.901278 ----->DramcWriteLeveling(PI) begin...
8374 00:40:57.901349 ==
8375 00:40:57.904529 Dram Type= 6, Freq= 0, CH_1, rank 0
8376 00:40:57.911314 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8377 00:40:57.911404 ==
8378 00:40:57.914698 Write leveling (Byte 0): 25 => 25
8379 00:40:57.918065 Write leveling (Byte 1): 27 => 27
8380 00:40:57.918195 DramcWriteLeveling(PI) end<-----
8381 00:40:57.920936
8382 00:40:57.921037 ==
8383 00:40:57.924347 Dram Type= 6, Freq= 0, CH_1, rank 0
8384 00:40:57.927634 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8385 00:40:57.927706 ==
8386 00:40:57.930749 [Gating] SW mode calibration
8387 00:40:57.938029 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8388 00:40:57.940916 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8389 00:40:57.947204 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8390 00:40:57.950656 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8391 00:40:57.957549 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8392 00:40:57.960428 1 4 12 | B1->B0 | 2f2f 3333 | 0 1 | (0 0) (1 1)
8393 00:40:57.963844 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8394 00:40:57.970803 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8395 00:40:57.973910 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8396 00:40:57.976958 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8397 00:40:57.983677 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8398 00:40:57.987009 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8399 00:40:57.989947 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8400 00:40:57.996671 1 5 12 | B1->B0 | 3333 2424 | 0 0 | (0 0) (1 0)
8401 00:40:58.000102 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8402 00:40:58.002997 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8403 00:40:58.009597 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8404 00:40:58.013124 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8405 00:40:58.016098 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8406 00:40:58.023087 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8407 00:40:58.026130 1 6 8 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
8408 00:40:58.029629 1 6 12 | B1->B0 | 3d3d 4343 | 0 0 | (0 0) (0 0)
8409 00:40:58.036205 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8410 00:40:58.039678 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8411 00:40:58.042874 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8412 00:40:58.049494 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8413 00:40:58.052811 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8414 00:40:58.056034 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8415 00:40:58.062354 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8416 00:40:58.066031 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8417 00:40:58.068849 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8418 00:40:58.075509 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8419 00:40:58.079030 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8420 00:40:58.082326 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8421 00:40:58.088514 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8422 00:40:58.092099 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8423 00:40:58.095262 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8424 00:40:58.102081 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8425 00:40:58.104914 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8426 00:40:58.108347 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8427 00:40:58.114830 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8428 00:40:58.118218 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8429 00:40:58.121589 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8430 00:40:58.128221 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8431 00:40:58.131574 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8432 00:40:58.134924 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8433 00:40:58.138034 Total UI for P1: 0, mck2ui 16
8434 00:40:58.141459 best dqsien dly found for B0: ( 1, 9, 8)
8435 00:40:58.148024 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8436 00:40:58.148138 Total UI for P1: 0, mck2ui 16
8437 00:40:58.154653 best dqsien dly found for B1: ( 1, 9, 12)
8438 00:40:58.157882 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8439 00:40:58.161226 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8440 00:40:58.161326
8441 00:40:58.164724 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8442 00:40:58.167962 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8443 00:40:58.170967 [Gating] SW calibration Done
8444 00:40:58.171065 ==
8445 00:40:58.174269 Dram Type= 6, Freq= 0, CH_1, rank 0
8446 00:40:58.178186 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8447 00:40:58.178281 ==
8448 00:40:58.180974 RX Vref Scan: 0
8449 00:40:58.181053
8450 00:40:58.181116 RX Vref 0 -> 0, step: 1
8451 00:40:58.181175
8452 00:40:58.184191 RX Delay 0 -> 252, step: 8
8453 00:40:58.187351 iDelay=208, Bit 0, Center 143 (88 ~ 199) 112
8454 00:40:58.193955 iDelay=208, Bit 1, Center 131 (80 ~ 183) 104
8455 00:40:58.197551 iDelay=208, Bit 2, Center 127 (72 ~ 183) 112
8456 00:40:58.200410 iDelay=208, Bit 3, Center 139 (88 ~ 191) 104
8457 00:40:58.204093 iDelay=208, Bit 4, Center 135 (80 ~ 191) 112
8458 00:40:58.207699 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8459 00:40:58.213733 iDelay=208, Bit 6, Center 147 (96 ~ 199) 104
8460 00:40:58.217094 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8461 00:40:58.220536 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8462 00:40:58.223988 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8463 00:40:58.230132 iDelay=208, Bit 10, Center 131 (80 ~ 183) 104
8464 00:40:58.233672 iDelay=208, Bit 11, Center 123 (72 ~ 175) 104
8465 00:40:58.237000 iDelay=208, Bit 12, Center 139 (88 ~ 191) 104
8466 00:40:58.240119 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8467 00:40:58.243493 iDelay=208, Bit 14, Center 139 (80 ~ 199) 120
8468 00:40:58.249896 iDelay=208, Bit 15, Center 139 (88 ~ 191) 104
8469 00:40:58.249999 ==
8470 00:40:58.253397 Dram Type= 6, Freq= 0, CH_1, rank 0
8471 00:40:58.256605 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8472 00:40:58.256710 ==
8473 00:40:58.256798 DQS Delay:
8474 00:40:58.259952 DQS0 = 0, DQS1 = 0
8475 00:40:58.260056 DQM Delay:
8476 00:40:58.262960 DQM0 = 138, DQM1 = 131
8477 00:40:58.263042 DQ Delay:
8478 00:40:58.266614 DQ0 =143, DQ1 =131, DQ2 =127, DQ3 =139
8479 00:40:58.269918 DQ4 =135, DQ5 =151, DQ6 =147, DQ7 =135
8480 00:40:58.273734 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
8481 00:40:58.279635 DQ12 =139, DQ13 =139, DQ14 =139, DQ15 =139
8482 00:40:58.279719
8483 00:40:58.279815
8484 00:40:58.279900 ==
8485 00:40:58.283227 Dram Type= 6, Freq= 0, CH_1, rank 0
8486 00:40:58.286142 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8487 00:40:58.286257 ==
8488 00:40:58.286318
8489 00:40:58.286391
8490 00:40:58.289544 TX Vref Scan disable
8491 00:40:58.289641 == TX Byte 0 ==
8492 00:40:58.296191 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8493 00:40:58.299507 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8494 00:40:58.299605 == TX Byte 1 ==
8495 00:40:58.306196 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8496 00:40:58.309482 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8497 00:40:58.309567 ==
8498 00:40:58.312451 Dram Type= 6, Freq= 0, CH_1, rank 0
8499 00:40:58.315667 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8500 00:40:58.315768 ==
8501 00:40:58.329745
8502 00:40:58.332922 TX Vref early break, caculate TX vref
8503 00:40:58.336129 TX Vref=16, minBit 10, minWin=22, winSum=382
8504 00:40:58.339802 TX Vref=18, minBit 0, minWin=23, winSum=393
8505 00:40:58.342609 TX Vref=20, minBit 10, minWin=23, winSum=397
8506 00:40:58.346019 TX Vref=22, minBit 5, minWin=24, winSum=408
8507 00:40:58.352728 TX Vref=24, minBit 0, minWin=25, winSum=416
8508 00:40:58.356074 TX Vref=26, minBit 13, minWin=25, winSum=427
8509 00:40:58.359301 TX Vref=28, minBit 5, minWin=25, winSum=424
8510 00:40:58.362863 TX Vref=30, minBit 15, minWin=25, winSum=419
8511 00:40:58.366136 TX Vref=32, minBit 13, minWin=24, winSum=410
8512 00:40:58.369306 TX Vref=34, minBit 5, minWin=23, winSum=399
8513 00:40:58.375648 [TxChooseVref] Worse bit 13, Min win 25, Win sum 427, Final Vref 26
8514 00:40:58.375745
8515 00:40:58.378886 Final TX Range 0 Vref 26
8516 00:40:58.378964
8517 00:40:58.379027 ==
8518 00:40:58.382627 Dram Type= 6, Freq= 0, CH_1, rank 0
8519 00:40:58.385728 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8520 00:40:58.385802 ==
8521 00:40:58.388661
8522 00:40:58.388780
8523 00:40:58.388903 TX Vref Scan disable
8524 00:40:58.395259 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8525 00:40:58.395359 == TX Byte 0 ==
8526 00:40:58.398839 u2DelayCellOfst[0]=18 cells (5 PI)
8527 00:40:58.402105 u2DelayCellOfst[1]=14 cells (4 PI)
8528 00:40:58.405466 u2DelayCellOfst[2]=0 cells (0 PI)
8529 00:40:58.408799 u2DelayCellOfst[3]=7 cells (2 PI)
8530 00:40:58.412172 u2DelayCellOfst[4]=7 cells (2 PI)
8531 00:40:58.415518 u2DelayCellOfst[5]=22 cells (6 PI)
8532 00:40:58.418309 u2DelayCellOfst[6]=22 cells (6 PI)
8533 00:40:58.421723 u2DelayCellOfst[7]=3 cells (1 PI)
8534 00:40:58.425154 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8535 00:40:58.428527 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8536 00:40:58.432083 == TX Byte 1 ==
8537 00:40:58.434907 u2DelayCellOfst[8]=0 cells (0 PI)
8538 00:40:58.438681 u2DelayCellOfst[9]=3 cells (1 PI)
8539 00:40:58.441827 u2DelayCellOfst[10]=11 cells (3 PI)
8540 00:40:58.444774 u2DelayCellOfst[11]=7 cells (2 PI)
8541 00:40:58.448018 u2DelayCellOfst[12]=14 cells (4 PI)
8542 00:40:58.451360 u2DelayCellOfst[13]=14 cells (4 PI)
8543 00:40:58.454659 u2DelayCellOfst[14]=18 cells (5 PI)
8544 00:40:58.457844 u2DelayCellOfst[15]=18 cells (5 PI)
8545 00:40:58.461101 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8546 00:40:58.464711 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8547 00:40:58.467805 DramC Write-DBI on
8548 00:40:58.467903 ==
8549 00:40:58.471068 Dram Type= 6, Freq= 0, CH_1, rank 0
8550 00:40:58.474631 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8551 00:40:58.474710 ==
8552 00:40:58.474772
8553 00:40:58.474830
8554 00:40:58.478344 TX Vref Scan disable
8555 00:40:58.478422 == TX Byte 0 ==
8556 00:40:58.484426 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8557 00:40:58.484505 == TX Byte 1 ==
8558 00:40:58.487908 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8559 00:40:58.491319 DramC Write-DBI off
8560 00:40:58.491397
8561 00:40:58.491458 [DATLAT]
8562 00:40:58.494603 Freq=1600, CH1 RK0
8563 00:40:58.494706
8564 00:40:58.494796 DATLAT Default: 0xf
8565 00:40:58.497606 0, 0xFFFF, sum = 0
8566 00:40:58.501012 1, 0xFFFF, sum = 0
8567 00:40:58.501091 2, 0xFFFF, sum = 0
8568 00:40:58.504327 3, 0xFFFF, sum = 0
8569 00:40:58.504407 4, 0xFFFF, sum = 0
8570 00:40:58.507390 5, 0xFFFF, sum = 0
8571 00:40:58.507469 6, 0xFFFF, sum = 0
8572 00:40:58.510939 7, 0xFFFF, sum = 0
8573 00:40:58.511018 8, 0xFFFF, sum = 0
8574 00:40:58.514055 9, 0xFFFF, sum = 0
8575 00:40:58.514183 10, 0xFFFF, sum = 0
8576 00:40:58.517562 11, 0xFFFF, sum = 0
8577 00:40:58.517641 12, 0xFFFF, sum = 0
8578 00:40:58.521176 13, 0xFFFF, sum = 0
8579 00:40:58.521255 14, 0x0, sum = 1
8580 00:40:58.524280 15, 0x0, sum = 2
8581 00:40:58.524359 16, 0x0, sum = 3
8582 00:40:58.527198 17, 0x0, sum = 4
8583 00:40:58.527277 best_step = 15
8584 00:40:58.527340
8585 00:40:58.527397 ==
8586 00:40:58.530636 Dram Type= 6, Freq= 0, CH_1, rank 0
8587 00:40:58.537290 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8588 00:40:58.537370 ==
8589 00:40:58.537436 RX Vref Scan: 1
8590 00:40:58.537494
8591 00:40:58.540586 Set Vref Range= 24 -> 127
8592 00:40:58.540663
8593 00:40:58.544237 RX Vref 24 -> 127, step: 1
8594 00:40:58.544315
8595 00:40:58.544377 RX Delay 19 -> 252, step: 4
8596 00:40:58.544435
8597 00:40:58.546885 Set Vref, RX VrefLevel [Byte0]: 24
8598 00:40:58.550453 [Byte1]: 24
8599 00:40:58.554488
8600 00:40:58.554620 Set Vref, RX VrefLevel [Byte0]: 25
8601 00:40:58.557711 [Byte1]: 25
8602 00:40:58.561868
8603 00:40:58.561972 Set Vref, RX VrefLevel [Byte0]: 26
8604 00:40:58.565284 [Byte1]: 26
8605 00:40:58.570034
8606 00:40:58.570169 Set Vref, RX VrefLevel [Byte0]: 27
8607 00:40:58.572740 [Byte1]: 27
8608 00:40:58.577410
8609 00:40:58.577487 Set Vref, RX VrefLevel [Byte0]: 28
8610 00:40:58.580492 [Byte1]: 28
8611 00:40:58.584819
8612 00:40:58.584901 Set Vref, RX VrefLevel [Byte0]: 29
8613 00:40:58.588015 [Byte1]: 29
8614 00:40:58.592728
8615 00:40:58.592867 Set Vref, RX VrefLevel [Byte0]: 30
8616 00:40:58.595911 [Byte1]: 30
8617 00:40:58.600231
8618 00:40:58.600353 Set Vref, RX VrefLevel [Byte0]: 31
8619 00:40:58.603028 [Byte1]: 31
8620 00:40:58.607436
8621 00:40:58.607515 Set Vref, RX VrefLevel [Byte0]: 32
8622 00:40:58.610708 [Byte1]: 32
8623 00:40:58.615120
8624 00:40:58.615234 Set Vref, RX VrefLevel [Byte0]: 33
8625 00:40:58.618451 [Byte1]: 33
8626 00:40:58.622440
8627 00:40:58.622519 Set Vref, RX VrefLevel [Byte0]: 34
8628 00:40:58.626279 [Byte1]: 34
8629 00:40:58.630420
8630 00:40:58.630539 Set Vref, RX VrefLevel [Byte0]: 35
8631 00:40:58.633638 [Byte1]: 35
8632 00:40:58.637979
8633 00:40:58.638090 Set Vref, RX VrefLevel [Byte0]: 36
8634 00:40:58.641157 [Byte1]: 36
8635 00:40:58.645344
8636 00:40:58.645449 Set Vref, RX VrefLevel [Byte0]: 37
8637 00:40:58.648646 [Byte1]: 37
8638 00:40:58.653023
8639 00:40:58.656253 Set Vref, RX VrefLevel [Byte0]: 38
8640 00:40:58.659383 [Byte1]: 38
8641 00:40:58.659462
8642 00:40:58.662844 Set Vref, RX VrefLevel [Byte0]: 39
8643 00:40:58.666142 [Byte1]: 39
8644 00:40:58.666272
8645 00:40:58.668997 Set Vref, RX VrefLevel [Byte0]: 40
8646 00:40:58.672485 [Byte1]: 40
8647 00:40:58.672584
8648 00:40:58.675909 Set Vref, RX VrefLevel [Byte0]: 41
8649 00:40:58.679192 [Byte1]: 41
8650 00:40:58.683345
8651 00:40:58.683419 Set Vref, RX VrefLevel [Byte0]: 42
8652 00:40:58.689682 [Byte1]: 42
8653 00:40:58.689821
8654 00:40:58.693168 Set Vref, RX VrefLevel [Byte0]: 43
8655 00:40:58.696032 [Byte1]: 43
8656 00:40:58.696141
8657 00:40:58.699571 Set Vref, RX VrefLevel [Byte0]: 44
8658 00:40:58.702955 [Byte1]: 44
8659 00:40:58.706294
8660 00:40:58.706370 Set Vref, RX VrefLevel [Byte0]: 45
8661 00:40:58.709534 [Byte1]: 45
8662 00:40:58.713531
8663 00:40:58.713610 Set Vref, RX VrefLevel [Byte0]: 46
8664 00:40:58.716723 [Byte1]: 46
8665 00:40:58.720969
8666 00:40:58.721080 Set Vref, RX VrefLevel [Byte0]: 47
8667 00:40:58.724252 [Byte1]: 47
8668 00:40:58.728473
8669 00:40:58.728554 Set Vref, RX VrefLevel [Byte0]: 48
8670 00:40:58.731866 [Byte1]: 48
8671 00:40:58.736524
8672 00:40:58.736602 Set Vref, RX VrefLevel [Byte0]: 49
8673 00:40:58.739400 [Byte1]: 49
8674 00:40:58.743594
8675 00:40:58.743698 Set Vref, RX VrefLevel [Byte0]: 50
8676 00:40:58.747611 [Byte1]: 50
8677 00:40:58.751516
8678 00:40:58.751595 Set Vref, RX VrefLevel [Byte0]: 51
8679 00:40:58.754956 [Byte1]: 51
8680 00:40:58.759168
8681 00:40:58.759276 Set Vref, RX VrefLevel [Byte0]: 52
8682 00:40:58.762843 [Byte1]: 52
8683 00:40:58.766500
8684 00:40:58.766571 Set Vref, RX VrefLevel [Byte0]: 53
8685 00:40:58.770099 [Byte1]: 53
8686 00:40:58.774042
8687 00:40:58.774145 Set Vref, RX VrefLevel [Byte0]: 54
8688 00:40:58.777184 [Byte1]: 54
8689 00:40:58.781736
8690 00:40:58.781809 Set Vref, RX VrefLevel [Byte0]: 55
8691 00:40:58.784913 [Byte1]: 55
8692 00:40:58.789322
8693 00:40:58.789421 Set Vref, RX VrefLevel [Byte0]: 56
8694 00:40:58.792349 [Byte1]: 56
8695 00:40:58.796771
8696 00:40:58.796878 Set Vref, RX VrefLevel [Byte0]: 57
8697 00:40:58.799975 [Byte1]: 57
8698 00:40:58.804279
8699 00:40:58.804382 Set Vref, RX VrefLevel [Byte0]: 58
8700 00:40:58.807546 [Byte1]: 58
8701 00:40:58.812281
8702 00:40:58.812362 Set Vref, RX VrefLevel [Byte0]: 59
8703 00:40:58.815270 [Byte1]: 59
8704 00:40:58.819557
8705 00:40:58.819635 Set Vref, RX VrefLevel [Byte0]: 60
8706 00:40:58.822880 [Byte1]: 60
8707 00:40:58.827100
8708 00:40:58.827183 Set Vref, RX VrefLevel [Byte0]: 61
8709 00:40:58.830514 [Byte1]: 61
8710 00:40:58.834716
8711 00:40:58.834844 Set Vref, RX VrefLevel [Byte0]: 62
8712 00:40:58.838412 [Byte1]: 62
8713 00:40:58.842383
8714 00:40:58.842470 Set Vref, RX VrefLevel [Byte0]: 63
8715 00:40:58.845763 [Byte1]: 63
8716 00:40:58.849753
8717 00:40:58.849923 Set Vref, RX VrefLevel [Byte0]: 64
8718 00:40:58.853145 [Byte1]: 64
8719 00:40:58.857540
8720 00:40:58.857707 Set Vref, RX VrefLevel [Byte0]: 65
8721 00:40:58.861051 [Byte1]: 65
8722 00:40:58.865015
8723 00:40:58.865171 Set Vref, RX VrefLevel [Byte0]: 66
8724 00:40:58.868719 [Byte1]: 66
8725 00:40:58.872841
8726 00:40:58.873001 Set Vref, RX VrefLevel [Byte0]: 67
8727 00:40:58.875829 [Byte1]: 67
8728 00:40:58.880202
8729 00:40:58.880339 Set Vref, RX VrefLevel [Byte0]: 68
8730 00:40:58.883371 [Byte1]: 68
8731 00:40:58.888206
8732 00:40:58.888284 Set Vref, RX VrefLevel [Byte0]: 69
8733 00:40:58.890888 [Byte1]: 69
8734 00:40:58.895498
8735 00:40:58.895574 Set Vref, RX VrefLevel [Byte0]: 70
8736 00:40:58.898759 [Byte1]: 70
8737 00:40:58.902676
8738 00:40:58.902749 Set Vref, RX VrefLevel [Byte0]: 71
8739 00:40:58.905853 [Byte1]: 71
8740 00:40:58.910501
8741 00:40:58.910651 Set Vref, RX VrefLevel [Byte0]: 72
8742 00:40:58.913653 [Byte1]: 72
8743 00:40:58.917922
8744 00:40:58.918036 Set Vref, RX VrefLevel [Byte0]: 73
8745 00:40:58.921590 [Byte1]: 73
8746 00:40:58.925696
8747 00:40:58.925797 Set Vref, RX VrefLevel [Byte0]: 74
8748 00:40:58.928715 [Byte1]: 74
8749 00:40:58.933307
8750 00:40:58.933387 Final RX Vref Byte 0 = 53 to rank0
8751 00:40:58.936442 Final RX Vref Byte 1 = 57 to rank0
8752 00:40:58.939558 Final RX Vref Byte 0 = 53 to rank1
8753 00:40:58.943279 Final RX Vref Byte 1 = 57 to rank1==
8754 00:40:58.946286 Dram Type= 6, Freq= 0, CH_1, rank 0
8755 00:40:58.952696 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8756 00:40:58.952794 ==
8757 00:40:58.952872 DQS Delay:
8758 00:40:58.956093 DQS0 = 0, DQS1 = 0
8759 00:40:58.956172 DQM Delay:
8760 00:40:58.956233 DQM0 = 134, DQM1 = 129
8761 00:40:58.959219 DQ Delay:
8762 00:40:58.962723 DQ0 =142, DQ1 =128, DQ2 =124, DQ3 =130
8763 00:40:58.966012 DQ4 =132, DQ5 =148, DQ6 =144, DQ7 =130
8764 00:40:58.969164 DQ8 =116, DQ9 =116, DQ10 =132, DQ11 =118
8765 00:40:58.972865 DQ12 =136, DQ13 =138, DQ14 =138, DQ15 =138
8766 00:40:58.972943
8767 00:40:58.973005
8768 00:40:58.973063
8769 00:40:58.975794 [DramC_TX_OE_Calibration] TA2
8770 00:40:58.979065 Original DQ_B0 (3 6) =30, OEN = 27
8771 00:40:58.982409 Original DQ_B1 (3 6) =30, OEN = 27
8772 00:40:58.985960 24, 0x0, End_B0=24 End_B1=24
8773 00:40:58.989232 25, 0x0, End_B0=25 End_B1=25
8774 00:40:58.989350 26, 0x0, End_B0=26 End_B1=26
8775 00:40:58.992817 27, 0x0, End_B0=27 End_B1=27
8776 00:40:58.995979 28, 0x0, End_B0=28 End_B1=28
8777 00:40:58.999149 29, 0x0, End_B0=29 End_B1=29
8778 00:40:58.999261 30, 0x0, End_B0=30 End_B1=30
8779 00:40:59.002461 31, 0x4141, End_B0=30 End_B1=30
8780 00:40:59.005805 Byte0 end_step=30 best_step=27
8781 00:40:59.008636 Byte1 end_step=30 best_step=27
8782 00:40:59.011994 Byte0 TX OE(2T, 0.5T) = (3, 3)
8783 00:40:59.015929 Byte1 TX OE(2T, 0.5T) = (3, 3)
8784 00:40:59.016039
8785 00:40:59.016140
8786 00:40:59.022262 [DQSOSCAuto] RK0, (LSB)MR18= 0x190e, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 397 ps
8787 00:40:59.025210 CH1 RK0: MR19=303, MR18=190E
8788 00:40:59.031972 CH1_RK0: MR19=0x303, MR18=0x190E, DQSOSC=397, MR23=63, INC=23, DEC=15
8789 00:40:59.032054
8790 00:40:59.035306 ----->DramcWriteLeveling(PI) begin...
8791 00:40:59.035388 ==
8792 00:40:59.038414 Dram Type= 6, Freq= 0, CH_1, rank 1
8793 00:40:59.042070 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8794 00:40:59.042193 ==
8795 00:40:59.044901 Write leveling (Byte 0): 26 => 26
8796 00:40:59.048032 Write leveling (Byte 1): 27 => 27
8797 00:40:59.051852 DramcWriteLeveling(PI) end<-----
8798 00:40:59.051955
8799 00:40:59.052056 ==
8800 00:40:59.054782 Dram Type= 6, Freq= 0, CH_1, rank 1
8801 00:40:59.058087 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8802 00:40:59.061416 ==
8803 00:40:59.061491 [Gating] SW mode calibration
8804 00:40:59.071360 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8805 00:40:59.075151 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8806 00:40:59.078028 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8807 00:40:59.084593 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8808 00:40:59.087956 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8809 00:40:59.091447 1 4 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
8810 00:40:59.097825 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8811 00:40:59.101271 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8812 00:40:59.104706 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8813 00:40:59.111387 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8814 00:40:59.114601 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8815 00:40:59.118005 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8816 00:40:59.124377 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8817 00:40:59.127927 1 5 12 | B1->B0 | 2727 3434 | 0 1 | (1 0) (1 0)
8818 00:40:59.130882 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8819 00:40:59.137778 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8820 00:40:59.141084 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8821 00:40:59.144128 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8822 00:40:59.150838 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8823 00:40:59.154335 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8824 00:40:59.157459 1 6 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8825 00:40:59.163814 1 6 12 | B1->B0 | 4444 2424 | 0 1 | (0 0) (0 0)
8826 00:40:59.167222 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8827 00:40:59.170617 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8828 00:40:59.177050 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8829 00:40:59.180569 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8830 00:40:59.183724 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8831 00:40:59.190321 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8832 00:40:59.193547 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8833 00:40:59.197025 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8834 00:40:59.203907 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8835 00:40:59.207061 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8836 00:40:59.210144 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8837 00:40:59.217198 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8838 00:40:59.220300 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8839 00:40:59.223337 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8840 00:40:59.230298 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8841 00:40:59.233596 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8842 00:40:59.236505 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8843 00:40:59.243326 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8844 00:40:59.246456 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8845 00:40:59.250124 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8846 00:40:59.256193 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8847 00:40:59.259495 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8848 00:40:59.262923 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8849 00:40:59.269535 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8850 00:40:59.272859 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8851 00:40:59.275949 Total UI for P1: 0, mck2ui 16
8852 00:40:59.279308 best dqsien dly found for B0: ( 1, 9, 10)
8853 00:40:59.283045 Total UI for P1: 0, mck2ui 16
8854 00:40:59.286195 best dqsien dly found for B1: ( 1, 9, 10)
8855 00:40:59.289638 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8856 00:40:59.292486 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8857 00:40:59.292570
8858 00:40:59.295773 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8859 00:40:59.302758 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8860 00:40:59.302836 [Gating] SW calibration Done
8861 00:40:59.302898 ==
8862 00:40:59.305564 Dram Type= 6, Freq= 0, CH_1, rank 1
8863 00:40:59.312036 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8864 00:40:59.312115 ==
8865 00:40:59.312178 RX Vref Scan: 0
8866 00:40:59.312236
8867 00:40:59.315563 RX Vref 0 -> 0, step: 1
8868 00:40:59.315648
8869 00:40:59.318623 RX Delay 0 -> 252, step: 8
8870 00:40:59.322227 iDelay=208, Bit 0, Center 139 (80 ~ 199) 120
8871 00:40:59.325347 iDelay=208, Bit 1, Center 131 (72 ~ 191) 120
8872 00:40:59.328849 iDelay=208, Bit 2, Center 123 (64 ~ 183) 120
8873 00:40:59.335437 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8874 00:40:59.338768 iDelay=208, Bit 4, Center 131 (72 ~ 191) 120
8875 00:40:59.341835 iDelay=208, Bit 5, Center 147 (88 ~ 207) 120
8876 00:40:59.345115 iDelay=208, Bit 6, Center 147 (88 ~ 207) 120
8877 00:40:59.348698 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8878 00:40:59.355141 iDelay=208, Bit 8, Center 115 (56 ~ 175) 120
8879 00:40:59.358440 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8880 00:40:59.361806 iDelay=208, Bit 10, Center 131 (72 ~ 191) 120
8881 00:40:59.365115 iDelay=208, Bit 11, Center 119 (64 ~ 175) 112
8882 00:40:59.368276 iDelay=208, Bit 12, Center 139 (80 ~ 199) 120
8883 00:40:59.374848 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8884 00:40:59.378537 iDelay=208, Bit 14, Center 131 (72 ~ 191) 120
8885 00:40:59.381961 iDelay=208, Bit 15, Center 139 (80 ~ 199) 120
8886 00:40:59.382082 ==
8887 00:40:59.384848 Dram Type= 6, Freq= 0, CH_1, rank 1
8888 00:40:59.388110 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8889 00:40:59.391853 ==
8890 00:40:59.391924 DQS Delay:
8891 00:40:59.391982 DQS0 = 0, DQS1 = 0
8892 00:40:59.394874 DQM Delay:
8893 00:40:59.394985 DQM0 = 136, DQM1 = 128
8894 00:40:59.398307 DQ Delay:
8895 00:40:59.401685 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8896 00:40:59.404559 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =135
8897 00:40:59.407920 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =119
8898 00:40:59.411286 DQ12 =139, DQ13 =139, DQ14 =131, DQ15 =139
8899 00:40:59.411360
8900 00:40:59.411448
8901 00:40:59.411503 ==
8902 00:40:59.414349 Dram Type= 6, Freq= 0, CH_1, rank 1
8903 00:40:59.417940 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8904 00:40:59.418005 ==
8905 00:40:59.420878
8906 00:40:59.420948
8907 00:40:59.421006 TX Vref Scan disable
8908 00:40:59.424609 == TX Byte 0 ==
8909 00:40:59.428053 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8910 00:40:59.430989 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8911 00:40:59.434307 == TX Byte 1 ==
8912 00:40:59.437557 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8913 00:40:59.441230 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8914 00:40:59.441301 ==
8915 00:40:59.444512 Dram Type= 6, Freq= 0, CH_1, rank 1
8916 00:40:59.450678 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8917 00:40:59.450755 ==
8918 00:40:59.462984
8919 00:40:59.466279 TX Vref early break, caculate TX vref
8920 00:40:59.469110 TX Vref=16, minBit 0, minWin=23, winSum=390
8921 00:40:59.472679 TX Vref=18, minBit 1, minWin=24, winSum=402
8922 00:40:59.476103 TX Vref=20, minBit 0, minWin=24, winSum=409
8923 00:40:59.478904 TX Vref=22, minBit 1, minWin=25, winSum=415
8924 00:40:59.482254 TX Vref=24, minBit 0, minWin=26, winSum=426
8925 00:40:59.488743 TX Vref=26, minBit 0, minWin=25, winSum=424
8926 00:40:59.492499 TX Vref=28, minBit 0, minWin=26, winSum=428
8927 00:40:59.495432 TX Vref=30, minBit 0, minWin=25, winSum=421
8928 00:40:59.498776 TX Vref=32, minBit 5, minWin=24, winSum=412
8929 00:40:59.502343 TX Vref=34, minBit 0, minWin=24, winSum=404
8930 00:40:59.508714 [TxChooseVref] Worse bit 0, Min win 26, Win sum 428, Final Vref 28
8931 00:40:59.508797
8932 00:40:59.512061 Final TX Range 0 Vref 28
8933 00:40:59.512140
8934 00:40:59.512202 ==
8935 00:40:59.515545 Dram Type= 6, Freq= 0, CH_1, rank 1
8936 00:40:59.518891 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8937 00:40:59.518969 ==
8938 00:40:59.519035
8939 00:40:59.519095
8940 00:40:59.522109 TX Vref Scan disable
8941 00:40:59.528647 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8942 00:40:59.528752 == TX Byte 0 ==
8943 00:40:59.531969 u2DelayCellOfst[0]=18 cells (5 PI)
8944 00:40:59.534988 u2DelayCellOfst[1]=14 cells (4 PI)
8945 00:40:59.538488 u2DelayCellOfst[2]=0 cells (0 PI)
8946 00:40:59.541735 u2DelayCellOfst[3]=7 cells (2 PI)
8947 00:40:59.545154 u2DelayCellOfst[4]=11 cells (3 PI)
8948 00:40:59.548654 u2DelayCellOfst[5]=22 cells (6 PI)
8949 00:40:59.551472 u2DelayCellOfst[6]=22 cells (6 PI)
8950 00:40:59.554975 u2DelayCellOfst[7]=7 cells (2 PI)
8951 00:40:59.557928 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8952 00:40:59.561521 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8953 00:40:59.564890 == TX Byte 1 ==
8954 00:40:59.568312 u2DelayCellOfst[8]=0 cells (0 PI)
8955 00:40:59.571115 u2DelayCellOfst[9]=3 cells (1 PI)
8956 00:40:59.574617 u2DelayCellOfst[10]=14 cells (4 PI)
8957 00:40:59.577642 u2DelayCellOfst[11]=3 cells (1 PI)
8958 00:40:59.577714 u2DelayCellOfst[12]=18 cells (5 PI)
8959 00:40:59.581182 u2DelayCellOfst[13]=18 cells (5 PI)
8960 00:40:59.584330 u2DelayCellOfst[14]=22 cells (6 PI)
8961 00:40:59.587913 u2DelayCellOfst[15]=18 cells (5 PI)
8962 00:40:59.594038 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8963 00:40:59.597772 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8964 00:40:59.597879 DramC Write-DBI on
8965 00:40:59.600956 ==
8966 00:40:59.604094 Dram Type= 6, Freq= 0, CH_1, rank 1
8967 00:40:59.607187 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8968 00:40:59.607271 ==
8969 00:40:59.607356
8970 00:40:59.607436
8971 00:40:59.610532 TX Vref Scan disable
8972 00:40:59.610616 == TX Byte 0 ==
8973 00:40:59.617393 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8974 00:40:59.617475 == TX Byte 1 ==
8975 00:40:59.620731 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8976 00:40:59.624113 DramC Write-DBI off
8977 00:40:59.624195
8978 00:40:59.624279 [DATLAT]
8979 00:40:59.627410 Freq=1600, CH1 RK1
8980 00:40:59.627492
8981 00:40:59.627576 DATLAT Default: 0xf
8982 00:40:59.630475 0, 0xFFFF, sum = 0
8983 00:40:59.630560 1, 0xFFFF, sum = 0
8984 00:40:59.633863 2, 0xFFFF, sum = 0
8985 00:40:59.633948 3, 0xFFFF, sum = 0
8986 00:40:59.637123 4, 0xFFFF, sum = 0
8987 00:40:59.637207 5, 0xFFFF, sum = 0
8988 00:40:59.640373 6, 0xFFFF, sum = 0
8989 00:40:59.643620 7, 0xFFFF, sum = 0
8990 00:40:59.643703 8, 0xFFFF, sum = 0
8991 00:40:59.647058 9, 0xFFFF, sum = 0
8992 00:40:59.647141 10, 0xFFFF, sum = 0
8993 00:40:59.650184 11, 0xFFFF, sum = 0
8994 00:40:59.650282 12, 0xFFFF, sum = 0
8995 00:40:59.653573 13, 0xFFFF, sum = 0
8996 00:40:59.653657 14, 0x0, sum = 1
8997 00:40:59.656996 15, 0x0, sum = 2
8998 00:40:59.657076 16, 0x0, sum = 3
8999 00:40:59.660403 17, 0x0, sum = 4
9000 00:40:59.660476 best_step = 15
9001 00:40:59.660536
9002 00:40:59.660614 ==
9003 00:40:59.663304 Dram Type= 6, Freq= 0, CH_1, rank 1
9004 00:40:59.666997 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9005 00:40:59.670444 ==
9006 00:40:59.670532 RX Vref Scan: 0
9007 00:40:59.670607
9008 00:40:59.673682 RX Vref 0 -> 0, step: 1
9009 00:40:59.673748
9010 00:40:59.676920 RX Delay 11 -> 252, step: 4
9011 00:40:59.680316 iDelay=199, Bit 0, Center 138 (87 ~ 190) 104
9012 00:40:59.683607 iDelay=199, Bit 1, Center 128 (75 ~ 182) 108
9013 00:40:59.686462 iDelay=199, Bit 2, Center 122 (67 ~ 178) 112
9014 00:40:59.693124 iDelay=199, Bit 3, Center 130 (79 ~ 182) 104
9015 00:40:59.696526 iDelay=199, Bit 4, Center 134 (79 ~ 190) 112
9016 00:40:59.699671 iDelay=199, Bit 5, Center 142 (91 ~ 194) 104
9017 00:40:59.702891 iDelay=199, Bit 6, Center 144 (91 ~ 198) 108
9018 00:40:59.706596 iDelay=199, Bit 7, Center 130 (79 ~ 182) 104
9019 00:40:59.713251 iDelay=199, Bit 8, Center 114 (59 ~ 170) 112
9020 00:40:59.716032 iDelay=199, Bit 9, Center 114 (59 ~ 170) 112
9021 00:40:59.719494 iDelay=199, Bit 10, Center 126 (71 ~ 182) 112
9022 00:40:59.722754 iDelay=199, Bit 11, Center 118 (67 ~ 170) 104
9023 00:40:59.729283 iDelay=199, Bit 12, Center 134 (79 ~ 190) 112
9024 00:40:59.732814 iDelay=199, Bit 13, Center 136 (83 ~ 190) 108
9025 00:40:59.736134 iDelay=199, Bit 14, Center 134 (79 ~ 190) 112
9026 00:40:59.739054 iDelay=199, Bit 15, Center 138 (83 ~ 194) 112
9027 00:40:59.739157 ==
9028 00:40:59.742513 Dram Type= 6, Freq= 0, CH_1, rank 1
9029 00:40:59.749131 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9030 00:40:59.749236 ==
9031 00:40:59.749332 DQS Delay:
9032 00:40:59.749424 DQS0 = 0, DQS1 = 0
9033 00:40:59.752542 DQM Delay:
9034 00:40:59.752625 DQM0 = 133, DQM1 = 126
9035 00:40:59.756018 DQ Delay:
9036 00:40:59.759425 DQ0 =138, DQ1 =128, DQ2 =122, DQ3 =130
9037 00:40:59.762550 DQ4 =134, DQ5 =142, DQ6 =144, DQ7 =130
9038 00:40:59.765774 DQ8 =114, DQ9 =114, DQ10 =126, DQ11 =118
9039 00:40:59.768840 DQ12 =134, DQ13 =136, DQ14 =134, DQ15 =138
9040 00:40:59.768922
9041 00:40:59.769006
9042 00:40:59.769084
9043 00:40:59.772226 [DramC_TX_OE_Calibration] TA2
9044 00:40:59.775798 Original DQ_B0 (3 6) =30, OEN = 27
9045 00:40:59.778845 Original DQ_B1 (3 6) =30, OEN = 27
9046 00:40:59.782490 24, 0x0, End_B0=24 End_B1=24
9047 00:40:59.782574 25, 0x0, End_B0=25 End_B1=25
9048 00:40:59.785482 26, 0x0, End_B0=26 End_B1=26
9049 00:40:59.788519 27, 0x0, End_B0=27 End_B1=27
9050 00:40:59.791835 28, 0x0, End_B0=28 End_B1=28
9051 00:40:59.794950 29, 0x0, End_B0=29 End_B1=29
9052 00:40:59.795048 30, 0x0, End_B0=30 End_B1=30
9053 00:40:59.798423 31, 0x4545, End_B0=30 End_B1=30
9054 00:40:59.801961 Byte0 end_step=30 best_step=27
9055 00:40:59.805661 Byte1 end_step=30 best_step=27
9056 00:40:59.808176 Byte0 TX OE(2T, 0.5T) = (3, 3)
9057 00:40:59.811315 Byte1 TX OE(2T, 0.5T) = (3, 3)
9058 00:40:59.811398
9059 00:40:59.811513
9060 00:40:59.817993 [DQSOSCAuto] RK1, (LSB)MR18= 0xd09, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 403 ps
9061 00:40:59.821293 CH1 RK1: MR19=303, MR18=D09
9062 00:40:59.828149 CH1_RK1: MR19=0x303, MR18=0xD09, DQSOSC=403, MR23=63, INC=22, DEC=15
9063 00:40:59.831486 [RxdqsGatingPostProcess] freq 1600
9064 00:40:59.834873 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9065 00:40:59.838040 best DQS0 dly(2T, 0.5T) = (1, 1)
9066 00:40:59.841288 best DQS1 dly(2T, 0.5T) = (1, 1)
9067 00:40:59.844863 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9068 00:40:59.847909 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9069 00:40:59.851058 best DQS0 dly(2T, 0.5T) = (1, 1)
9070 00:40:59.854358 best DQS1 dly(2T, 0.5T) = (1, 1)
9071 00:40:59.857744 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9072 00:40:59.861330 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9073 00:40:59.864471 Pre-setting of DQS Precalculation
9074 00:40:59.867761 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9075 00:40:59.877806 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9076 00:40:59.884130 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9077 00:40:59.884240
9078 00:40:59.884339
9079 00:40:59.887397 [Calibration Summary] 3200 Mbps
9080 00:40:59.887474 CH 0, Rank 0
9081 00:40:59.890890 SW Impedance : PASS
9082 00:40:59.890968 DUTY Scan : NO K
9083 00:40:59.894195 ZQ Calibration : PASS
9084 00:40:59.897145 Jitter Meter : NO K
9085 00:40:59.897222 CBT Training : PASS
9086 00:40:59.900743 Write leveling : PASS
9087 00:40:59.903835 RX DQS gating : PASS
9088 00:40:59.903945 RX DQ/DQS(RDDQC) : PASS
9089 00:40:59.907468 TX DQ/DQS : PASS
9090 00:40:59.910561 RX DATLAT : PASS
9091 00:40:59.910640 RX DQ/DQS(Engine): PASS
9092 00:40:59.913795 TX OE : PASS
9093 00:40:59.913873 All Pass.
9094 00:40:59.913936
9095 00:40:59.916775 CH 0, Rank 1
9096 00:40:59.916847 SW Impedance : PASS
9097 00:40:59.920290 DUTY Scan : NO K
9098 00:40:59.923432 ZQ Calibration : PASS
9099 00:40:59.923505 Jitter Meter : NO K
9100 00:40:59.927081 CBT Training : PASS
9101 00:40:59.930311 Write leveling : PASS
9102 00:40:59.930384 RX DQS gating : PASS
9103 00:40:59.933274 RX DQ/DQS(RDDQC) : PASS
9104 00:40:59.933370 TX DQ/DQS : PASS
9105 00:40:59.936900 RX DATLAT : PASS
9106 00:40:59.939803 RX DQ/DQS(Engine): PASS
9107 00:40:59.939914 TX OE : PASS
9108 00:40:59.943052 All Pass.
9109 00:40:59.943164
9110 00:40:59.943260 CH 1, Rank 0
9111 00:40:59.946468 SW Impedance : PASS
9112 00:40:59.946574 DUTY Scan : NO K
9113 00:40:59.949987 ZQ Calibration : PASS
9114 00:40:59.953387 Jitter Meter : NO K
9115 00:40:59.953471 CBT Training : PASS
9116 00:40:59.956508 Write leveling : PASS
9117 00:40:59.959637 RX DQS gating : PASS
9118 00:40:59.959710 RX DQ/DQS(RDDQC) : PASS
9119 00:40:59.963221 TX DQ/DQS : PASS
9120 00:40:59.966688 RX DATLAT : PASS
9121 00:40:59.966760 RX DQ/DQS(Engine): PASS
9122 00:40:59.969529 TX OE : PASS
9123 00:40:59.969599 All Pass.
9124 00:40:59.969675
9125 00:40:59.972895 CH 1, Rank 1
9126 00:40:59.972975 SW Impedance : PASS
9127 00:40:59.976265 DUTY Scan : NO K
9128 00:40:59.979320 ZQ Calibration : PASS
9129 00:40:59.979400 Jitter Meter : NO K
9130 00:40:59.982519 CBT Training : PASS
9131 00:40:59.985734 Write leveling : PASS
9132 00:40:59.985832 RX DQS gating : PASS
9133 00:40:59.989379 RX DQ/DQS(RDDQC) : PASS
9134 00:40:59.992450 TX DQ/DQS : PASS
9135 00:40:59.992576 RX DATLAT : PASS
9136 00:40:59.996090 RX DQ/DQS(Engine): PASS
9137 00:40:59.998778 TX OE : PASS
9138 00:40:59.998857 All Pass.
9139 00:40:59.998919
9140 00:41:00.002045 DramC Write-DBI on
9141 00:41:00.002127 PER_BANK_REFRESH: Hybrid Mode
9142 00:41:00.005324 TX_TRACKING: ON
9143 00:41:00.015251 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9144 00:41:00.022126 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9145 00:41:00.028504 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9146 00:41:00.031899 [FAST_K] Save calibration result to emmc
9147 00:41:00.035143 sync common calibartion params.
9148 00:41:00.038477 sync cbt_mode0:1, 1:1
9149 00:41:00.038551 dram_init: ddr_geometry: 2
9150 00:41:00.041656 dram_init: ddr_geometry: 2
9151 00:41:00.044946 dram_init: ddr_geometry: 2
9152 00:41:00.048448 0:dram_rank_size:100000000
9153 00:41:00.048557 1:dram_rank_size:100000000
9154 00:41:00.055146 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9155 00:41:00.058113 DFS_SHUFFLE_HW_MODE: ON
9156 00:41:00.061548 dramc_set_vcore_voltage set vcore to 725000
9157 00:41:00.065113 Read voltage for 1600, 0
9158 00:41:00.065214 Vio18 = 0
9159 00:41:00.065304 Vcore = 725000
9160 00:41:00.068411 Vdram = 0
9161 00:41:00.068484 Vddq = 0
9162 00:41:00.068544 Vmddr = 0
9163 00:41:00.071413 switch to 3200 Mbps bootup
9164 00:41:00.071486 [DramcRunTimeConfig]
9165 00:41:00.074590 PHYPLL
9166 00:41:00.074664 DPM_CONTROL_AFTERK: ON
9167 00:41:00.077939 PER_BANK_REFRESH: ON
9168 00:41:00.081276 REFRESH_OVERHEAD_REDUCTION: ON
9169 00:41:00.081382 CMD_PICG_NEW_MODE: OFF
9170 00:41:00.085027 XRTWTW_NEW_MODE: ON
9171 00:41:00.085125 XRTRTR_NEW_MODE: ON
9172 00:41:00.088106 TX_TRACKING: ON
9173 00:41:00.088180 RDSEL_TRACKING: OFF
9174 00:41:00.091354 DQS Precalculation for DVFS: ON
9175 00:41:00.094891 RX_TRACKING: OFF
9176 00:41:00.094998 HW_GATING DBG: ON
9177 00:41:00.097854 ZQCS_ENABLE_LP4: ON
9178 00:41:00.097925 RX_PICG_NEW_MODE: ON
9179 00:41:00.101263 TX_PICG_NEW_MODE: ON
9180 00:41:00.104736 ENABLE_RX_DCM_DPHY: ON
9181 00:41:00.104826 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9182 00:41:00.108026 DUMMY_READ_FOR_TRACKING: OFF
9183 00:41:00.111336 !!! SPM_CONTROL_AFTERK: OFF
9184 00:41:00.114533 !!! SPM could not control APHY
9185 00:41:00.114609 IMPEDANCE_TRACKING: ON
9186 00:41:00.118144 TEMP_SENSOR: ON
9187 00:41:00.118242 HW_SAVE_FOR_SR: OFF
9188 00:41:00.121125 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9189 00:41:00.124286 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9190 00:41:00.127624 Read ODT Tracking: ON
9191 00:41:00.131206 Refresh Rate DeBounce: ON
9192 00:41:00.131305 DFS_NO_QUEUE_FLUSH: ON
9193 00:41:00.134149 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9194 00:41:00.137801 ENABLE_DFS_RUNTIME_MRW: OFF
9195 00:41:00.141146 DDR_RESERVE_NEW_MODE: ON
9196 00:41:00.141226 MR_CBT_SWITCH_FREQ: ON
9197 00:41:00.144361 =========================
9198 00:41:00.163209 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9199 00:41:00.166400 dram_init: ddr_geometry: 2
9200 00:41:00.185014 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9201 00:41:00.188200 dram_init: dram init end (result: 0)
9202 00:41:00.195042 DRAM-K: Full calibration passed in 24636 msecs
9203 00:41:00.198011 MRC: failed to locate region type 0.
9204 00:41:00.198119 DRAM rank0 size:0x100000000,
9205 00:41:00.201365 DRAM rank1 size=0x100000000
9206 00:41:00.211292 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9207 00:41:00.217747 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9208 00:41:00.224698 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9209 00:41:00.234402 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9210 00:41:00.234483 DRAM rank0 size:0x100000000,
9211 00:41:00.237921 DRAM rank1 size=0x100000000
9212 00:41:00.237999 CBMEM:
9213 00:41:00.240960 IMD: root @ 0xfffff000 254 entries.
9214 00:41:00.244449 IMD: root @ 0xffffec00 62 entries.
9215 00:41:00.247803 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9216 00:41:00.254053 WARNING: RO_VPD is uninitialized or empty.
9217 00:41:00.257813 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9218 00:41:00.265037 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9219 00:41:00.277854 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9220 00:41:00.289491 BS: romstage times (exec / console): total (unknown) / 24128 ms
9221 00:41:00.289573
9222 00:41:00.289635
9223 00:41:00.299618 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9224 00:41:00.302607 ARM64: Exception handlers installed.
9225 00:41:00.305917 ARM64: Testing exception
9226 00:41:00.309013 ARM64: Done test exception
9227 00:41:00.309110 Enumerating buses...
9228 00:41:00.312299 Show all devs... Before device enumeration.
9229 00:41:00.315652 Root Device: enabled 1
9230 00:41:00.319124 CPU_CLUSTER: 0: enabled 1
9231 00:41:00.319196 CPU: 00: enabled 1
9232 00:41:00.322349 Compare with tree...
9233 00:41:00.322433 Root Device: enabled 1
9234 00:41:00.325882 CPU_CLUSTER: 0: enabled 1
9235 00:41:00.328992 CPU: 00: enabled 1
9236 00:41:00.329065 Root Device scanning...
9237 00:41:00.332066 scan_static_bus for Root Device
9238 00:41:00.335192 CPU_CLUSTER: 0 enabled
9239 00:41:00.338844 scan_static_bus for Root Device done
9240 00:41:00.342280 scan_bus: bus Root Device finished in 8 msecs
9241 00:41:00.342352 done
9242 00:41:00.348763 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9243 00:41:00.352172 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9244 00:41:00.358559 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9245 00:41:00.361766 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9246 00:41:00.365204 Allocating resources...
9247 00:41:00.368736 Reading resources...
9248 00:41:00.371818 Root Device read_resources bus 0 link: 0
9249 00:41:00.375004 DRAM rank0 size:0x100000000,
9250 00:41:00.375083 DRAM rank1 size=0x100000000
9251 00:41:00.378169 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9252 00:41:00.381702 CPU: 00 missing read_resources
9253 00:41:00.388165 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9254 00:41:00.391373 Root Device read_resources bus 0 link: 0 done
9255 00:41:00.394641 Done reading resources.
9256 00:41:00.398543 Show resources in subtree (Root Device)...After reading.
9257 00:41:00.401339 Root Device child on link 0 CPU_CLUSTER: 0
9258 00:41:00.405058 CPU_CLUSTER: 0 child on link 0 CPU: 00
9259 00:41:00.414702 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9260 00:41:00.414787 CPU: 00
9261 00:41:00.417871 Root Device assign_resources, bus 0 link: 0
9262 00:41:00.421283 CPU_CLUSTER: 0 missing set_resources
9263 00:41:00.427744 Root Device assign_resources, bus 0 link: 0 done
9264 00:41:00.427819 Done setting resources.
9265 00:41:00.434419 Show resources in subtree (Root Device)...After assigning values.
9266 00:41:00.437597 Root Device child on link 0 CPU_CLUSTER: 0
9267 00:41:00.441141 CPU_CLUSTER: 0 child on link 0 CPU: 00
9268 00:41:00.451233 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9269 00:41:00.451313 CPU: 00
9270 00:41:00.454496 Done allocating resources.
9271 00:41:00.460912 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9272 00:41:00.460992 Enabling resources...
9273 00:41:00.461094 done.
9274 00:41:00.467782 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9275 00:41:00.470704 Initializing devices...
9276 00:41:00.470793 Root Device init
9277 00:41:00.474179 init hardware done!
9278 00:41:00.474252 0x00000018: ctrlr->caps
9279 00:41:00.477437 52.000 MHz: ctrlr->f_max
9280 00:41:00.480663 0.400 MHz: ctrlr->f_min
9281 00:41:00.480765 0x40ff8080: ctrlr->voltages
9282 00:41:00.484041 sclk: 390625
9283 00:41:00.484145 Bus Width = 1
9284 00:41:00.484235 sclk: 390625
9285 00:41:00.487327 Bus Width = 1
9286 00:41:00.490663 Early init status = 3
9287 00:41:00.494082 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9288 00:41:00.497605 in-header: 03 fc 00 00 01 00 00 00
9289 00:41:00.501061 in-data: 00
9290 00:41:00.503932 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9291 00:41:00.509564 in-header: 03 fd 00 00 00 00 00 00
9292 00:41:00.513075 in-data:
9293 00:41:00.516210 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9294 00:41:00.520835 in-header: 03 fc 00 00 01 00 00 00
9295 00:41:00.524272 in-data: 00
9296 00:41:00.527474 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9297 00:41:00.532764 in-header: 03 fd 00 00 00 00 00 00
9298 00:41:00.536408 in-data:
9299 00:41:00.539540 [SSUSB] Setting up USB HOST controller...
9300 00:41:00.542873 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9301 00:41:00.546080 [SSUSB] phy power-on done.
9302 00:41:00.549374 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9303 00:41:00.556128 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9304 00:41:00.559362 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9305 00:41:00.565873 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9306 00:41:00.572385 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9307 00:41:00.578777 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9308 00:41:00.585530 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9309 00:41:00.592281 read SPI 0x705bc 0x1f6a: 925 us, 8694 KB/s, 69.552 Mbps
9310 00:41:00.595478 SPM: binary array size = 0x9dc
9311 00:41:00.599004 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9312 00:41:00.605085 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9313 00:41:00.611868 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9314 00:41:00.618432 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9315 00:41:00.621641 configure_display: Starting display init
9316 00:41:00.655836 anx7625_power_on_init: Init interface.
9317 00:41:00.659246 anx7625_disable_pd_protocol: Disabled PD feature.
9318 00:41:00.662462 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9319 00:41:00.690364 anx7625_start_dp_work: Secure OCM version=00
9320 00:41:00.693487 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9321 00:41:00.708559 sp_tx_get_edid_block: EDID Block = 1
9322 00:41:00.810985 Extracted contents:
9323 00:41:00.814491 header: 00 ff ff ff ff ff ff 00
9324 00:41:00.817892 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9325 00:41:00.820715 version: 01 04
9326 00:41:00.824338 basic params: 95 1f 11 78 0a
9327 00:41:00.827505 chroma info: 76 90 94 55 54 90 27 21 50 54
9328 00:41:00.831129 established: 00 00 00
9329 00:41:00.837151 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9330 00:41:00.843779 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9331 00:41:00.847245 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9332 00:41:00.854143 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9333 00:41:00.860164 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9334 00:41:00.863609 extensions: 00
9335 00:41:00.863689 checksum: fb
9336 00:41:00.863772
9337 00:41:00.870453 Manufacturer: IVO Model 57d Serial Number 0
9338 00:41:00.870532 Made week 0 of 2020
9339 00:41:00.873513 EDID version: 1.4
9340 00:41:00.873592 Digital display
9341 00:41:00.876816 6 bits per primary color channel
9342 00:41:00.879865 DisplayPort interface
9343 00:41:00.879947 Maximum image size: 31 cm x 17 cm
9344 00:41:00.883327 Gamma: 220%
9345 00:41:00.883406 Check DPMS levels
9346 00:41:00.889935 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9347 00:41:00.893472 First detailed timing is preferred timing
9348 00:41:00.896608 Established timings supported:
9349 00:41:00.896692 Standard timings supported:
9350 00:41:00.900216 Detailed timings
9351 00:41:00.903121 Hex of detail: 383680a07038204018303c0035ae10000019
9352 00:41:00.909773 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9353 00:41:00.912911 0780 0798 07c8 0820 hborder 0
9354 00:41:00.916072 0438 043b 0447 0458 vborder 0
9355 00:41:00.920018 -hsync -vsync
9356 00:41:00.920129 Did detailed timing
9357 00:41:00.926186 Hex of detail: 000000000000000000000000000000000000
9358 00:41:00.929525 Manufacturer-specified data, tag 0
9359 00:41:00.932469 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9360 00:41:00.936455 ASCII string: InfoVision
9361 00:41:00.939229 Hex of detail: 000000fe00523134304e574635205248200a
9362 00:41:00.942152 ASCII string: R140NWF5 RH
9363 00:41:00.942268 Checksum
9364 00:41:00.945826 Checksum: 0xfb (valid)
9365 00:41:00.949262 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9366 00:41:00.952364 DSI data_rate: 832800000 bps
9367 00:41:00.958823 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9368 00:41:00.962367 anx7625_parse_edid: pixelclock(138800).
9369 00:41:00.965359 hactive(1920), hsync(48), hfp(24), hbp(88)
9370 00:41:00.968948 vactive(1080), vsync(12), vfp(3), vbp(17)
9371 00:41:00.972181 anx7625_dsi_config: config dsi.
9372 00:41:00.978884 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9373 00:41:00.993132 anx7625_dsi_config: success to config DSI
9374 00:41:00.996359 anx7625_dp_start: MIPI phy setup OK.
9375 00:41:00.999829 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9376 00:41:01.003135 mtk_ddp_mode_set invalid vrefresh 60
9377 00:41:01.006634 main_disp_path_setup
9378 00:41:01.006720 ovl_layer_smi_id_en
9379 00:41:01.009404 ovl_layer_smi_id_en
9380 00:41:01.009473 ccorr_config
9381 00:41:01.009531 aal_config
9382 00:41:01.012778 gamma_config
9383 00:41:01.012930 postmask_config
9384 00:41:01.016132 dither_config
9385 00:41:01.019675 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9386 00:41:01.025753 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9387 00:41:01.029504 Root Device init finished in 555 msecs
9388 00:41:01.032541 CPU_CLUSTER: 0 init
9389 00:41:01.039384 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9390 00:41:01.045866 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9391 00:41:01.045968 APU_MBOX 0x190000b0 = 0x10001
9392 00:41:01.049264 APU_MBOX 0x190001b0 = 0x10001
9393 00:41:01.053170 APU_MBOX 0x190005b0 = 0x10001
9394 00:41:01.055946 APU_MBOX 0x190006b0 = 0x10001
9395 00:41:01.062038 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9396 00:41:01.072106 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9397 00:41:01.084256 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9398 00:41:01.091069 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9399 00:41:01.102907 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9400 00:41:01.111879 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9401 00:41:01.115284 CPU_CLUSTER: 0 init finished in 81 msecs
9402 00:41:01.118631 Devices initialized
9403 00:41:01.121900 Show all devs... After init.
9404 00:41:01.121970 Root Device: enabled 1
9405 00:41:01.125522 CPU_CLUSTER: 0: enabled 1
9406 00:41:01.128067 CPU: 00: enabled 1
9407 00:41:01.131615 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9408 00:41:01.134737 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9409 00:41:01.138306 ELOG: NV offset 0x57f000 size 0x1000
9410 00:41:01.145145 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9411 00:41:01.151620 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9412 00:41:01.155165 ELOG: Event(17) added with size 13 at 2024-06-16 00:41:00 UTC
9413 00:41:01.161548 out: cmd=0x121: 03 db 21 01 00 00 00 00
9414 00:41:01.164701 in-header: 03 2d 00 00 2c 00 00 00
9415 00:41:01.177756 in-data: 0f 73 00 00 00 00 00 00 0a 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9416 00:41:01.181284 ELOG: Event(A1) added with size 10 at 2024-06-16 00:41:00 UTC
9417 00:41:01.187751 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
9418 00:41:01.194361 ELOG: Event(A0) added with size 9 at 2024-06-16 00:41:00 UTC
9419 00:41:01.197893 elog_add_boot_reason: Logged dev mode boot
9420 00:41:01.204531 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9421 00:41:01.204609 Finalize devices...
9422 00:41:01.207489 Devices finalized
9423 00:41:01.210985 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9424 00:41:01.213914 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
9425 00:41:01.217647 in-header: 03 07 00 00 08 00 00 00
9426 00:41:01.220640 in-data: aa e4 47 04 13 02 00 00
9427 00:41:01.223832 Chrome EC: UHEPI supported
9428 00:41:01.230538 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
9429 00:41:01.233771 in-header: 03 a9 00 00 08 00 00 00
9430 00:41:01.237052 in-data: 84 60 60 08 00 00 00 00
9431 00:41:01.243657 ELOG: Event(91) added with size 10 at 2024-06-16 00:41:00 UTC
9432 00:41:01.247294 Chrome EC: clear events_b mask to 0x0000000020004000
9433 00:41:01.254062 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
9434 00:41:01.257292 in-header: 03 fd 00 00 00 00 00 00
9435 00:41:01.260245 in-data:
9436 00:41:01.264142 BS: BS_WRITE_TABLES entry times (exec / console): 2 / 46 ms
9437 00:41:01.267147 Writing coreboot table at 0xffe64000
9438 00:41:01.273775 0. 000000000010a000-0000000000113fff: RAMSTAGE
9439 00:41:01.277024 1. 0000000040000000-00000000400fffff: RAM
9440 00:41:01.280110 2. 0000000040100000-000000004032afff: RAMSTAGE
9441 00:41:01.283634 3. 000000004032b000-00000000545fffff: RAM
9442 00:41:01.286948 4. 0000000054600000-000000005465ffff: BL31
9443 00:41:01.293926 5. 0000000054660000-00000000ffe63fff: RAM
9444 00:41:01.296877 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9445 00:41:01.300291 7. 0000000100000000-000000023fffffff: RAM
9446 00:41:01.303427 Passing 5 GPIOs to payload:
9447 00:41:01.306514 NAME | PORT | POLARITY | VALUE
9448 00:41:01.313288 EC in RW | 0x000000aa | low | undefined
9449 00:41:01.316457 EC interrupt | 0x00000005 | low | undefined
9450 00:41:01.323124 TPM interrupt | 0x000000ab | high | undefined
9451 00:41:01.326513 SD card detect | 0x00000011 | high | undefined
9452 00:41:01.329923 speaker enable | 0x00000093 | high | undefined
9453 00:41:01.336238 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9454 00:41:01.339536 in-header: 03 f9 00 00 02 00 00 00
9455 00:41:01.339615 in-data: 02 00
9456 00:41:01.343053 ADC[4]: Raw value=904139 ID=7
9457 00:41:01.346357 ADC[3]: Raw value=213652 ID=1
9458 00:41:01.346433 RAM Code: 0x71
9459 00:41:01.350158 ADC[6]: Raw value=75036 ID=0
9460 00:41:01.352807 ADC[5]: Raw value=213282 ID=1
9461 00:41:01.352905 SKU Code: 0x1
9462 00:41:01.359423 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 400f
9463 00:41:01.362482 coreboot table: 964 bytes.
9464 00:41:01.366124 IMD ROOT 0. 0xfffff000 0x00001000
9465 00:41:01.369538 IMD SMALL 1. 0xffffe000 0x00001000
9466 00:41:01.372665 RO MCACHE 2. 0xffffc000 0x00001104
9467 00:41:01.375727 CONSOLE 3. 0xfff7c000 0x00080000
9468 00:41:01.379220 FMAP 4. 0xfff7b000 0x00000452
9469 00:41:01.382669 TIME STAMP 5. 0xfff7a000 0x00000910
9470 00:41:01.385721 VBOOT WORK 6. 0xfff66000 0x00014000
9471 00:41:01.389124 RAMOOPS 7. 0xffe66000 0x00100000
9472 00:41:01.392663 COREBOOT 8. 0xffe64000 0x00002000
9473 00:41:01.392767 IMD small region:
9474 00:41:01.395358 IMD ROOT 0. 0xffffec00 0x00000400
9475 00:41:01.399080 VPD 1. 0xffffeb80 0x0000006c
9476 00:41:01.402052 MMC STATUS 2. 0xffffeb60 0x00000004
9477 00:41:01.408583 BS: BS_WRITE_TABLES run times (exec / console): 2 / 137 ms
9478 00:41:01.415583 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9479 00:41:01.455303 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9480 00:41:01.458406 Checking segment from ROM address 0x40100000
9481 00:41:01.465325 Checking segment from ROM address 0x4010001c
9482 00:41:01.468186 Loading segment from ROM address 0x40100000
9483 00:41:01.468257 code (compression=0)
9484 00:41:01.478282 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9485 00:41:01.484713 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9486 00:41:01.484787 it's not compressed!
9487 00:41:01.491525 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9488 00:41:01.498411 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9489 00:41:01.516044 Loading segment from ROM address 0x4010001c
9490 00:41:01.516123 Entry Point 0x80000000
9491 00:41:01.518820 Loaded segments
9492 00:41:01.522302 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9493 00:41:01.529026 Jumping to boot code at 0x80000000(0xffe64000)
9494 00:41:01.535526 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9495 00:41:01.542027 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9496 00:41:01.550348 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9497 00:41:01.553101 Checking segment from ROM address 0x40100000
9498 00:41:01.556731 Checking segment from ROM address 0x4010001c
9499 00:41:01.563396 Loading segment from ROM address 0x40100000
9500 00:41:01.563494 code (compression=1)
9501 00:41:01.569848 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9502 00:41:01.579470 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9503 00:41:01.579546 using LZMA
9504 00:41:01.588595 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9505 00:41:01.594705 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9506 00:41:01.598285 Loading segment from ROM address 0x4010001c
9507 00:41:01.601436 Entry Point 0x54601000
9508 00:41:01.601535 Loaded segments
9509 00:41:01.604446 NOTICE: MT8192 bl31_setup
9510 00:41:01.611833 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9511 00:41:01.615287 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9512 00:41:01.618468 WARNING: region 0:
9513 00:41:01.621934 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9514 00:41:01.622007 WARNING: region 1:
9515 00:41:01.628759 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9516 00:41:01.631794 WARNING: region 2:
9517 00:41:01.634882 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9518 00:41:01.638337 WARNING: region 3:
9519 00:41:01.644915 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9520 00:41:01.645006 WARNING: region 4:
9521 00:41:01.651911 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9522 00:41:01.651990 WARNING: region 5:
9523 00:41:01.654535 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9524 00:41:01.658157 WARNING: region 6:
9525 00:41:01.661521 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9526 00:41:01.664354 WARNING: region 7:
9527 00:41:01.667723 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9528 00:41:01.674559 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9529 00:41:01.677736 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9530 00:41:01.684481 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9531 00:41:01.687686 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9532 00:41:01.690936 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9533 00:41:01.697774 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9534 00:41:01.700667 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9535 00:41:01.707510 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9536 00:41:01.710701 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9537 00:41:01.713963 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9538 00:41:01.720266 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9539 00:41:01.723538 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9540 00:41:01.730469 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9541 00:41:01.734057 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9542 00:41:01.736587 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9543 00:41:01.743386 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9544 00:41:01.746763 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9545 00:41:01.749878 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9546 00:41:01.756571 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9547 00:41:01.760248 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9548 00:41:01.766595 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9549 00:41:01.770110 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9550 00:41:01.773322 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9551 00:41:01.779803 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9552 00:41:01.783089 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9553 00:41:01.789794 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9554 00:41:01.793030 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9555 00:41:01.796161 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9556 00:41:01.803043 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9557 00:41:01.806256 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9558 00:41:01.812884 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9559 00:41:01.816047 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9560 00:41:01.819388 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9561 00:41:01.826288 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9562 00:41:01.829270 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9563 00:41:01.832482 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9564 00:41:01.836075 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9565 00:41:01.842602 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9566 00:41:01.845689 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9567 00:41:01.849444 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9568 00:41:01.852351 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9569 00:41:01.859350 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9570 00:41:01.862196 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9571 00:41:01.866057 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9572 00:41:01.869169 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9573 00:41:01.875663 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9574 00:41:01.878922 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9575 00:41:01.882318 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9576 00:41:01.889070 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9577 00:41:01.892014 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9578 00:41:01.898981 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9579 00:41:01.901955 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9580 00:41:01.905276 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9581 00:41:01.912076 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9582 00:41:01.915144 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9583 00:41:01.921615 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9584 00:41:01.925338 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9585 00:41:01.931711 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9586 00:41:01.935656 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9587 00:41:01.938430 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9588 00:41:01.945505 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9589 00:41:01.948336 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9590 00:41:01.955139 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9591 00:41:01.958153 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9592 00:41:01.964724 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9593 00:41:01.968219 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9594 00:41:01.974805 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9595 00:41:01.978334 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9596 00:41:01.981621 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9597 00:41:01.988183 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9598 00:41:01.991508 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9599 00:41:01.998327 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9600 00:41:02.001092 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9601 00:41:02.007805 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9602 00:41:02.011680 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9603 00:41:02.017718 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9604 00:41:02.021160 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9605 00:41:02.027970 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9606 00:41:02.031165 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9607 00:41:02.034126 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9608 00:41:02.041250 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9609 00:41:02.044241 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9610 00:41:02.050732 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9611 00:41:02.054432 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9612 00:41:02.060717 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9613 00:41:02.063772 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9614 00:41:02.070617 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9615 00:41:02.073810 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9616 00:41:02.077170 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9617 00:41:02.083766 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9618 00:41:02.087070 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9619 00:41:02.093548 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9620 00:41:02.097014 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9621 00:41:02.103437 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9622 00:41:02.107116 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9623 00:41:02.113497 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9624 00:41:02.116960 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9625 00:41:02.120055 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9626 00:41:02.123677 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9627 00:41:02.130072 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9628 00:41:02.133107 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9629 00:41:02.136379 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9630 00:41:02.143034 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9631 00:41:02.146580 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9632 00:41:02.153335 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9633 00:41:02.156390 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9634 00:41:02.159787 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9635 00:41:02.166579 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9636 00:41:02.169832 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9637 00:41:02.176529 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9638 00:41:02.179488 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9639 00:41:02.182774 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9640 00:41:02.189511 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9641 00:41:02.192748 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9642 00:41:02.199544 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9643 00:41:02.202561 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9644 00:41:02.206425 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9645 00:41:02.212776 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9646 00:41:02.215878 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9647 00:41:02.219359 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9648 00:41:02.222450 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9649 00:41:02.228905 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9650 00:41:02.232317 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9651 00:41:02.235616 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9652 00:41:02.242251 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9653 00:41:02.245778 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9654 00:41:02.249083 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9655 00:41:02.255633 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9656 00:41:02.258708 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9657 00:41:02.265380 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9658 00:41:02.268718 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9659 00:41:02.272241 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9660 00:41:02.278565 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9661 00:41:02.281952 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9662 00:41:02.288331 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9663 00:41:02.291740 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9664 00:41:02.295112 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9665 00:41:02.301478 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9666 00:41:02.305168 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9667 00:41:02.311469 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9668 00:41:02.314977 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9669 00:41:02.318104 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9670 00:41:02.324897 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9671 00:41:02.328246 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9672 00:41:02.334501 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9673 00:41:02.337821 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9674 00:41:02.341133 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9675 00:41:02.348105 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9676 00:41:02.351118 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9677 00:41:02.357554 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9678 00:41:02.360895 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9679 00:41:02.363970 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9680 00:41:02.370800 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9681 00:41:02.374300 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9682 00:41:02.380981 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9683 00:41:02.384236 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9684 00:41:02.387215 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9685 00:41:02.393997 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9686 00:41:02.397455 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9687 00:41:02.404174 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9688 00:41:02.406820 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9689 00:41:02.410498 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9690 00:41:02.417209 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9691 00:41:02.420290 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9692 00:41:02.426731 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9693 00:41:02.429919 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9694 00:41:02.433246 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9695 00:41:02.440052 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9696 00:41:02.443123 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9697 00:41:02.449942 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9698 00:41:02.453256 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9699 00:41:02.457028 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9700 00:41:02.463585 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9701 00:41:02.466621 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9702 00:41:02.473030 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9703 00:41:02.476291 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9704 00:41:02.479765 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9705 00:41:02.486378 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9706 00:41:02.489835 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9707 00:41:02.496664 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9708 00:41:02.499780 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9709 00:41:02.503292 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9710 00:41:02.509580 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9711 00:41:02.513043 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9712 00:41:02.519541 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9713 00:41:02.522850 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9714 00:41:02.526107 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9715 00:41:02.532677 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9716 00:41:02.535921 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9717 00:41:02.542892 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9718 00:41:02.546238 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9719 00:41:02.549359 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9720 00:41:02.555807 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9721 00:41:02.559204 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9722 00:41:02.565726 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9723 00:41:02.568932 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9724 00:41:02.575828 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9725 00:41:02.579450 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9726 00:41:02.582458 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9727 00:41:02.589286 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9728 00:41:02.592548 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9729 00:41:02.598818 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9730 00:41:02.602477 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9731 00:41:02.605451 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9732 00:41:02.612110 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9733 00:41:02.615484 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9734 00:41:02.621851 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9735 00:41:02.625307 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9736 00:41:02.632117 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9737 00:41:02.634960 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9738 00:41:02.638738 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9739 00:41:02.645473 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9740 00:41:02.648839 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9741 00:41:02.655138 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9742 00:41:02.658568 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9743 00:41:02.664923 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9744 00:41:02.668577 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9745 00:41:02.671592 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9746 00:41:02.678228 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9747 00:41:02.681561 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9748 00:41:02.688082 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9749 00:41:02.692022 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9750 00:41:02.694714 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9751 00:41:02.701576 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9752 00:41:02.704917 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9753 00:41:02.711133 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9754 00:41:02.714383 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9755 00:41:02.721463 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9756 00:41:02.724250 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9757 00:41:02.727607 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9758 00:41:02.731015 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9759 00:41:02.737466 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9760 00:41:02.741341 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9761 00:41:02.744580 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9762 00:41:02.751095 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9763 00:41:02.754532 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9764 00:41:02.757681 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9765 00:41:02.764018 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9766 00:41:02.767496 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9767 00:41:02.770656 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9768 00:41:02.777561 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9769 00:41:02.780778 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9770 00:41:02.786897 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9771 00:41:02.790513 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9772 00:41:02.793658 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9773 00:41:02.800795 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9774 00:41:02.803600 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9775 00:41:02.810268 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9776 00:41:02.813708 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9777 00:41:02.817233 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9778 00:41:02.823585 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9779 00:41:02.827183 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9780 00:41:02.830045 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9781 00:41:02.836866 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9782 00:41:02.840411 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9783 00:41:02.843579 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9784 00:41:02.850172 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9785 00:41:02.853563 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9786 00:41:02.856972 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9787 00:41:02.863265 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9788 00:41:02.866735 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9789 00:41:02.873087 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9790 00:41:02.876447 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9791 00:41:02.880329 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9792 00:41:02.886433 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9793 00:41:02.889823 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9794 00:41:02.896175 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9795 00:41:02.899752 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9796 00:41:02.903129 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9797 00:41:02.906090 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9798 00:41:02.912715 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9799 00:41:02.916001 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9800 00:41:02.919449 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9801 00:41:02.922694 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9802 00:41:02.929650 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9803 00:41:02.932509 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9804 00:41:02.935807 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9805 00:41:02.939730 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9806 00:41:02.945954 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9807 00:41:02.949009 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9808 00:41:02.952446 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9809 00:41:02.955855 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9810 00:41:02.962396 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9811 00:41:02.965698 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9812 00:41:02.972364 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9813 00:41:02.975454 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9814 00:41:02.982131 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9815 00:41:02.985752 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9816 00:41:02.991888 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9817 00:41:02.995313 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9818 00:41:02.998725 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9819 00:41:03.005299 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9820 00:41:03.008186 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9821 00:41:03.014832 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9822 00:41:03.018313 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9823 00:41:03.021651 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9824 00:41:03.028188 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9825 00:41:03.031507 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9826 00:41:03.038353 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9827 00:41:03.041671 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9828 00:41:03.047755 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9829 00:41:03.051000 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9830 00:41:03.054270 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9831 00:41:03.061242 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9832 00:41:03.064463 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9833 00:41:03.071180 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9834 00:41:03.074116 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9835 00:41:03.077880 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9836 00:41:03.084085 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9837 00:41:03.087332 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9838 00:41:03.094346 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9839 00:41:03.097199 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9840 00:41:03.103687 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9841 00:41:03.107754 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9842 00:41:03.110488 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9843 00:41:03.117400 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9844 00:41:03.120591 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9845 00:41:03.127145 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9846 00:41:03.130481 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9847 00:41:03.133758 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9848 00:41:03.140453 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9849 00:41:03.143838 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9850 00:41:03.150494 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9851 00:41:03.153211 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9852 00:41:03.159936 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9853 00:41:03.163391 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9854 00:41:03.166794 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9855 00:41:03.173369 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9856 00:41:03.176260 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9857 00:41:03.183164 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9858 00:41:03.186641 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9859 00:41:03.189361 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9860 00:41:03.196283 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9861 00:41:03.199332 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9862 00:41:03.205930 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9863 00:41:03.209468 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9864 00:41:03.215976 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9865 00:41:03.219126 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9866 00:41:03.222353 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9867 00:41:03.229099 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9868 00:41:03.232604 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9869 00:41:03.239269 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9870 00:41:03.242716 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9871 00:41:03.249649 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9872 00:41:03.252210 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9873 00:41:03.255524 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9874 00:41:03.261969 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9875 00:41:03.265590 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9876 00:41:03.271908 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9877 00:41:03.275114 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9878 00:41:03.278517 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9879 00:41:03.285398 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9880 00:41:03.288889 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9881 00:41:03.295608 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9882 00:41:03.298927 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9883 00:41:03.302112 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9884 00:41:03.308820 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9885 00:41:03.312251 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9886 00:41:03.318417 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9887 00:41:03.321823 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9888 00:41:03.328175 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9889 00:41:03.331539 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9890 00:41:03.338185 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9891 00:41:03.341289 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9892 00:41:03.344602 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9893 00:41:03.351470 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9894 00:41:03.354493 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9895 00:41:03.361193 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9896 00:41:03.364650 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9897 00:41:03.371551 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9898 00:41:03.374457 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9899 00:41:03.381264 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9900 00:41:03.384424 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9901 00:41:03.387560 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9902 00:41:03.394345 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9903 00:41:03.397603 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9904 00:41:03.404071 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9905 00:41:03.407569 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9906 00:41:03.414039 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9907 00:41:03.417259 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9908 00:41:03.423927 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9909 00:41:03.427516 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9910 00:41:03.430479 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9911 00:41:03.437144 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9912 00:41:03.440779 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9913 00:41:03.447089 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9914 00:41:03.450183 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9915 00:41:03.456785 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9916 00:41:03.460376 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9917 00:41:03.466609 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9918 00:41:03.470135 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9919 00:41:03.476572 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9920 00:41:03.480120 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9921 00:41:03.483052 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9922 00:41:03.489634 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9923 00:41:03.493189 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9924 00:41:03.499790 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9925 00:41:03.502876 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9926 00:41:03.509591 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9927 00:41:03.512663 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9928 00:41:03.519271 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9929 00:41:03.522723 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9930 00:41:03.526287 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9931 00:41:03.532553 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9932 00:41:03.536277 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9933 00:41:03.542417 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9934 00:41:03.545937 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9935 00:41:03.552669 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9936 00:41:03.555851 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9937 00:41:03.562013 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9938 00:41:03.565406 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9939 00:41:03.572071 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9940 00:41:03.575310 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9941 00:41:03.578851 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9942 00:41:03.585495 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9943 00:41:03.588730 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9944 00:41:03.595495 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9945 00:41:03.598582 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9946 00:41:03.605428 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9947 00:41:03.608643 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9948 00:41:03.615014 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9949 00:41:03.618108 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9950 00:41:03.624691 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9951 00:41:03.628060 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9952 00:41:03.634962 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9953 00:41:03.641189 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9954 00:41:03.645217 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9955 00:41:03.651600 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9956 00:41:03.654513 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9957 00:41:03.661163 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9958 00:41:03.664394 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9959 00:41:03.671124 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9960 00:41:03.674301 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9961 00:41:03.681542 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9962 00:41:03.684146 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9963 00:41:03.684222 INFO: [APUAPC] vio 0
9964 00:41:03.692041 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9965 00:41:03.695427 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9966 00:41:03.698888 INFO: [APUAPC] D0_APC_0: 0x400510
9967 00:41:03.701866 INFO: [APUAPC] D0_APC_1: 0x0
9968 00:41:03.704738 INFO: [APUAPC] D0_APC_2: 0x1540
9969 00:41:03.708267 INFO: [APUAPC] D0_APC_3: 0x0
9970 00:41:03.711353 INFO: [APUAPC] D1_APC_0: 0xffffffff
9971 00:41:03.714723 INFO: [APUAPC] D1_APC_1: 0xffffffff
9972 00:41:03.718304 INFO: [APUAPC] D1_APC_2: 0x3fffff
9973 00:41:03.721230 INFO: [APUAPC] D1_APC_3: 0x0
9974 00:41:03.724860 INFO: [APUAPC] D2_APC_0: 0xffffffff
9975 00:41:03.727980 INFO: [APUAPC] D2_APC_1: 0xffffffff
9976 00:41:03.731462 INFO: [APUAPC] D2_APC_2: 0x3fffff
9977 00:41:03.734439 INFO: [APUAPC] D2_APC_3: 0x0
9978 00:41:03.738029 INFO: [APUAPC] D3_APC_0: 0xffffffff
9979 00:41:03.741273 INFO: [APUAPC] D3_APC_1: 0xffffffff
9980 00:41:03.744344 INFO: [APUAPC] D3_APC_2: 0x3fffff
9981 00:41:03.747675 INFO: [APUAPC] D3_APC_3: 0x0
9982 00:41:03.751135 INFO: [APUAPC] D4_APC_0: 0xffffffff
9983 00:41:03.754772 INFO: [APUAPC] D4_APC_1: 0xffffffff
9984 00:41:03.758153 INFO: [APUAPC] D4_APC_2: 0x3fffff
9985 00:41:03.761379 INFO: [APUAPC] D4_APC_3: 0x0
9986 00:41:03.764793 INFO: [APUAPC] D5_APC_0: 0xffffffff
9987 00:41:03.768259 INFO: [APUAPC] D5_APC_1: 0xffffffff
9988 00:41:03.770928 INFO: [APUAPC] D5_APC_2: 0x3fffff
9989 00:41:03.774659 INFO: [APUAPC] D5_APC_3: 0x0
9990 00:41:03.777690 INFO: [APUAPC] D6_APC_0: 0xffffffff
9991 00:41:03.780928 INFO: [APUAPC] D6_APC_1: 0xffffffff
9992 00:41:03.784300 INFO: [APUAPC] D6_APC_2: 0x3fffff
9993 00:41:03.784376 INFO: [APUAPC] D6_APC_3: 0x0
9994 00:41:03.790759 INFO: [APUAPC] D7_APC_0: 0xffffffff
9995 00:41:03.794153 INFO: [APUAPC] D7_APC_1: 0xffffffff
9996 00:41:03.797390 INFO: [APUAPC] D7_APC_2: 0x3fffff
9997 00:41:03.797462 INFO: [APUAPC] D7_APC_3: 0x0
9998 00:41:03.804112 INFO: [APUAPC] D8_APC_0: 0xffffffff
9999 00:41:03.806961 INFO: [APUAPC] D8_APC_1: 0xffffffff
10000 00:41:03.810349 INFO: [APUAPC] D8_APC_2: 0x3fffff
10001 00:41:03.810419 INFO: [APUAPC] D8_APC_3: 0x0
10002 00:41:03.813694 INFO: [APUAPC] D9_APC_0: 0xffffffff
10003 00:41:03.820142 INFO: [APUAPC] D9_APC_1: 0xffffffff
10004 00:41:03.823430 INFO: [APUAPC] D9_APC_2: 0x3fffff
10005 00:41:03.823503 INFO: [APUAPC] D9_APC_3: 0x0
10006 00:41:03.826886 INFO: [APUAPC] D10_APC_0: 0xffffffff
10007 00:41:03.833707 INFO: [APUAPC] D10_APC_1: 0xffffffff
10008 00:41:03.836950 INFO: [APUAPC] D10_APC_2: 0x3fffff
10009 00:41:03.837050 INFO: [APUAPC] D10_APC_3: 0x0
10010 00:41:03.843128 INFO: [APUAPC] D11_APC_0: 0xffffffff
10011 00:41:03.846464 INFO: [APUAPC] D11_APC_1: 0xffffffff
10012 00:41:03.849822 INFO: [APUAPC] D11_APC_2: 0x3fffff
10013 00:41:03.849925 INFO: [APUAPC] D11_APC_3: 0x0
10014 00:41:03.856412 INFO: [APUAPC] D12_APC_0: 0xffffffff
10015 00:41:03.859568 INFO: [APUAPC] D12_APC_1: 0xffffffff
10016 00:41:03.863262 INFO: [APUAPC] D12_APC_2: 0x3fffff
10017 00:41:03.866529 INFO: [APUAPC] D12_APC_3: 0x0
10018 00:41:03.869667 INFO: [APUAPC] D13_APC_0: 0xffffffff
10019 00:41:03.873090 INFO: [APUAPC] D13_APC_1: 0xffffffff
10020 00:41:03.876475 INFO: [APUAPC] D13_APC_2: 0x3fffff
10021 00:41:03.879946 INFO: [APUAPC] D13_APC_3: 0x0
10022 00:41:03.883393 INFO: [APUAPC] D14_APC_0: 0xffffffff
10023 00:41:03.886080 INFO: [APUAPC] D14_APC_1: 0xffffffff
10024 00:41:03.889402 INFO: [APUAPC] D14_APC_2: 0x3fffff
10025 00:41:03.893090 INFO: [APUAPC] D14_APC_3: 0x0
10026 00:41:03.896192 INFO: [APUAPC] D15_APC_0: 0xffffffff
10027 00:41:03.899680 INFO: [APUAPC] D15_APC_1: 0xffffffff
10028 00:41:03.902943 INFO: [APUAPC] D15_APC_2: 0x3fffff
10029 00:41:03.906448 INFO: [APUAPC] D15_APC_3: 0x0
10030 00:41:03.906534 INFO: [APUAPC] APC_CON: 0x4
10031 00:41:03.909178 INFO: [NOCDAPC] D0_APC_0: 0x0
10032 00:41:03.913033 INFO: [NOCDAPC] D0_APC_1: 0x0
10033 00:41:03.916340 INFO: [NOCDAPC] D1_APC_0: 0x0
10034 00:41:03.919265 INFO: [NOCDAPC] D1_APC_1: 0xfff
10035 00:41:03.922638 INFO: [NOCDAPC] D2_APC_0: 0x0
10036 00:41:03.925901 INFO: [NOCDAPC] D2_APC_1: 0xfff
10037 00:41:03.929221 INFO: [NOCDAPC] D3_APC_0: 0x0
10038 00:41:03.932383 INFO: [NOCDAPC] D3_APC_1: 0xfff
10039 00:41:03.935738 INFO: [NOCDAPC] D4_APC_0: 0x0
10040 00:41:03.939020 INFO: [NOCDAPC] D4_APC_1: 0xfff
10041 00:41:03.939089 INFO: [NOCDAPC] D5_APC_0: 0x0
10042 00:41:03.942549 INFO: [NOCDAPC] D5_APC_1: 0xfff
10043 00:41:03.945731 INFO: [NOCDAPC] D6_APC_0: 0x0
10044 00:41:03.949580 INFO: [NOCDAPC] D6_APC_1: 0xfff
10045 00:41:03.952298 INFO: [NOCDAPC] D7_APC_0: 0x0
10046 00:41:03.955553 INFO: [NOCDAPC] D7_APC_1: 0xfff
10047 00:41:03.959114 INFO: [NOCDAPC] D8_APC_0: 0x0
10048 00:41:03.962114 INFO: [NOCDAPC] D8_APC_1: 0xfff
10049 00:41:03.965902 INFO: [NOCDAPC] D9_APC_0: 0x0
10050 00:41:03.968877 INFO: [NOCDAPC] D9_APC_1: 0xfff
10051 00:41:03.972159 INFO: [NOCDAPC] D10_APC_0: 0x0
10052 00:41:03.975400 INFO: [NOCDAPC] D10_APC_1: 0xfff
10053 00:41:03.975469 INFO: [NOCDAPC] D11_APC_0: 0x0
10054 00:41:03.978948 INFO: [NOCDAPC] D11_APC_1: 0xfff
10055 00:41:03.982122 INFO: [NOCDAPC] D12_APC_0: 0x0
10056 00:41:03.985561 INFO: [NOCDAPC] D12_APC_1: 0xfff
10057 00:41:03.988852 INFO: [NOCDAPC] D13_APC_0: 0x0
10058 00:41:03.992257 INFO: [NOCDAPC] D13_APC_1: 0xfff
10059 00:41:03.995144 INFO: [NOCDAPC] D14_APC_0: 0x0
10060 00:41:03.998609 INFO: [NOCDAPC] D14_APC_1: 0xfff
10061 00:41:04.002059 INFO: [NOCDAPC] D15_APC_0: 0x0
10062 00:41:04.005425 INFO: [NOCDAPC] D15_APC_1: 0xfff
10063 00:41:04.008922 INFO: [NOCDAPC] APC_CON: 0x4
10064 00:41:04.012130 INFO: [APUAPC] set_apusys_apc done
10065 00:41:04.015225 INFO: [DEVAPC] devapc_init done
10066 00:41:04.018309 INFO: GICv3 without legacy support detected.
10067 00:41:04.021947 INFO: ARM GICv3 driver initialized in EL3
10068 00:41:04.025345 INFO: Maximum SPI INTID supported: 639
10069 00:41:04.031637 INFO: BL31: Initializing runtime services
10070 00:41:04.035264 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10071 00:41:04.038382 INFO: SPM: enable CPC mode
10072 00:41:04.044860 INFO: mcdi ready for mcusys-off-idle and system suspend
10073 00:41:04.048042 INFO: BL31: Preparing for EL3 exit to normal world
10074 00:41:04.051162 INFO: Entry point address = 0x80000000
10075 00:41:04.054474 INFO: SPSR = 0x8
10076 00:41:04.060088
10077 00:41:04.060163
10078 00:41:04.060258
10079 00:41:04.063481 Starting depthcharge on Spherion...
10080 00:41:04.063564
10081 00:41:04.063623 Wipe memory regions:
10082 00:41:04.063679
10083 00:41:04.064701 end: 2.2.3 depthcharge-start (duration 00:00:19) [common]
10084 00:41:04.064832 start: 2.2.4 bootloader-commands (timeout 00:04:26) [common]
10085 00:41:04.064937 Setting prompt string to ['asurada:']
10086 00:41:04.065049 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:26)
10087 00:41:04.066812 [0x00000040000000, 0x00000054600000)
10088 00:41:04.188820
10089 00:41:04.188978 [0x00000054660000, 0x00000080000000)
10090 00:41:04.449631
10091 00:41:04.449766 [0x000000821a7280, 0x000000ffe64000)
10092 00:41:05.194240
10093 00:41:05.194370 [0x00000100000000, 0x00000240000000)
10094 00:41:07.083599
10095 00:41:07.087083 Initializing XHCI USB controller at 0x11200000.
10096 00:41:08.125271
10097 00:41:08.128406 [firmware-asurada-13885.B-collabora] Dec 14 2021 15:21:43
10098 00:41:08.128514
10099 00:41:08.128608
10100 00:41:08.128966 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10102 00:41:08.229331 asurada: tftpboot 192.168.201.1 14368366/tftp-deploy-h8e7f32o/kernel/image.itb 14368366/tftp-deploy-h8e7f32o/kernel/cmdline
10103 00:41:08.229476 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10104 00:41:08.229602 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:22)
10105 00:41:08.234173 tftpboot 192.168.201.1 14368366/tftp-deploy-h8e7f32o/kernel/image.itp-deploy-h8e7f32o/kernel/cmdline
10106 00:41:08.234267
10107 00:41:08.234330 Waiting for link
10108 00:41:08.392561
10109 00:41:08.392709 R8152: Initializing
10110 00:41:08.392780
10111 00:41:08.395373 Version 6 (ocp_data = 5c30)
10112 00:41:08.395494
10113 00:41:08.398730 R8152: Done initializing
10114 00:41:08.398815
10115 00:41:08.398877 Adding net device
10116 00:41:10.304752
10117 00:41:10.304890 done.
10118 00:41:10.304955
10119 00:41:10.305019 MAC: 00:e0:4c:68:02:81
10120 00:41:10.305079
10121 00:41:10.307524 Sending DHCP discover... done.
10122 00:41:10.307628
10123 00:41:10.310811 Waiting for reply... done.
10124 00:41:10.310887
10125 00:41:10.314242 Sending DHCP request... done.
10126 00:41:10.314346
10127 00:41:10.318407 Waiting for reply... done.
10128 00:41:10.318491
10129 00:41:10.318577 My ip is 192.168.201.14
10130 00:41:10.318654
10131 00:41:10.322045 The DHCP server ip is 192.168.201.1
10132 00:41:10.322151
10133 00:41:10.328136 TFTP server IP predefined by user: 192.168.201.1
10134 00:41:10.328237
10135 00:41:10.335112 Bootfile predefined by user: 14368366/tftp-deploy-h8e7f32o/kernel/image.itb
10136 00:41:10.335190
10137 00:41:10.338487 Sending tftp read request... done.
10138 00:41:10.338567
10139 00:41:10.341981 Waiting for the transfer...
10140 00:41:10.342085
10141 00:41:10.863694 00000000 ################################################################
10142 00:41:10.863840
10143 00:41:11.385373 00080000 ################################################################
10144 00:41:11.385519
10145 00:41:11.907964 00100000 ################################################################
10146 00:41:11.908148
10147 00:41:12.498079 00180000 ################################################################
10148 00:41:12.498274
10149 00:41:13.143291 00200000 ################################################################
10150 00:41:13.143816
10151 00:41:13.798613 00280000 ################################################################
10152 00:41:13.799193
10153 00:41:14.430797 00300000 ################################################################
10154 00:41:14.430933
10155 00:41:14.974478 00380000 ################################################################
10156 00:41:14.974606
10157 00:41:15.503938 00400000 ################################################################
10158 00:41:15.504072
10159 00:41:16.056936 00480000 ################################################################
10160 00:41:16.057081
10161 00:41:16.608062 00500000 ################################################################
10162 00:41:16.608265
10163 00:41:17.198106 00580000 ################################################################
10164 00:41:17.198287
10165 00:41:17.753275 00600000 ################################################################
10166 00:41:17.753406
10167 00:41:18.342107 00680000 ################################################################
10168 00:41:18.342259
10169 00:41:18.932357 00700000 ################################################################
10170 00:41:18.932873
10171 00:41:19.572390 00780000 ################################################################
10172 00:41:19.572522
10173 00:41:20.143745 00800000 ################################################################
10174 00:41:20.144266
10175 00:41:20.812269 00880000 ################################################################
10176 00:41:20.812826
10177 00:41:21.485521 00900000 ################################################################
10178 00:41:21.486006
10179 00:41:22.095889 00980000 ################################################################
10180 00:41:22.096037
10181 00:41:22.723529 00a00000 ################################################################
10182 00:41:22.724015
10183 00:41:23.397909 00a80000 ################################################################
10184 00:41:23.398459
10185 00:41:24.020327 00b00000 ################################################################
10186 00:41:24.020466
10187 00:41:24.600375 00b80000 ################################################################
10188 00:41:24.600528
10189 00:41:25.190298 00c00000 ################################################################
10190 00:41:25.190443
10191 00:41:25.849576 00c80000 ################################################################
10192 00:41:25.850071
10193 00:41:26.500987 00d00000 ################################################################
10194 00:41:26.501125
10195 00:41:27.141441 00d80000 ################################################################
10196 00:41:27.141991
10197 00:41:27.705594 00e00000 ################################################################
10198 00:41:27.705737
10199 00:41:28.311831 00e80000 ################################################################
10200 00:41:28.311978
10201 00:41:28.914423 00f00000 ################################################################
10202 00:41:28.914985
10203 00:41:29.544745 00f80000 ################################################################
10204 00:41:29.544886
10205 00:41:30.176296 01000000 ################################################################
10206 00:41:30.176934
10207 00:41:30.807555 01080000 ################################################################
10208 00:41:30.807692
10209 00:41:31.386396 01100000 ################################################################
10210 00:41:31.386571
10211 00:41:32.004124 01180000 ################################################################
10212 00:41:32.004270
10213 00:41:32.612935 01200000 ################################################################
10214 00:41:32.613078
10215 00:41:33.255503 01280000 ################################################################
10216 00:41:33.256009
10217 00:41:33.916598 01300000 ################################################################
10218 00:41:33.917144
10219 00:41:34.567245 01380000 ################################################################
10220 00:41:34.567761
10221 00:41:35.217033 01400000 ################################################################
10222 00:41:35.217214
10223 00:41:35.808722 01480000 ################################################################
10224 00:41:35.808862
10225 00:41:36.438805 01500000 ################################################################
10226 00:41:36.439303
10227 00:41:37.124696 01580000 ################################################################
10228 00:41:37.125215
10229 00:41:37.832895 01600000 ################################################################
10230 00:41:37.833396
10231 00:41:38.523517 01680000 ################################################################
10232 00:41:38.524070
10233 00:41:39.216545 01700000 ################################################################
10234 00:41:39.217051
10235 00:41:39.912351 01780000 ################################################################
10236 00:41:39.912853
10237 00:41:40.614422 01800000 ################################################################
10238 00:41:40.614932
10239 00:41:41.307567 01880000 ################################################################
10240 00:41:41.308128
10241 00:41:42.008208 01900000 ################################################################
10242 00:41:42.008704
10243 00:41:42.711707 01980000 ################################################################
10244 00:41:42.712223
10245 00:41:43.413866 01a00000 ################################################################
10246 00:41:43.414456
10247 00:41:44.138087 01a80000 ################################################################
10248 00:41:44.138637
10249 00:41:44.861447 01b00000 ################################################################
10250 00:41:44.862029
10251 00:41:45.581658 01b80000 ################################################################
10252 00:41:45.582154
10253 00:41:46.292995 01c00000 ################################################################
10254 00:41:46.293503
10255 00:41:47.001961 01c80000 ################################################################
10256 00:41:47.002633
10257 00:41:47.694391 01d00000 ################################################################
10258 00:41:47.694894
10259 00:41:48.383570 01d80000 ################################################################
10260 00:41:48.384154
10261 00:41:49.077646 01e00000 ################################################################
10262 00:41:49.077786
10263 00:41:49.761726 01e80000 ################################################################
10264 00:41:49.762298
10265 00:41:50.424055 01f00000 ################################################################
10266 00:41:50.424218
10267 00:41:51.094225 01f80000 ################################################################
10268 00:41:51.094810
10269 00:41:51.771111 02000000 ################################################################
10270 00:41:51.771683
10271 00:41:52.397604 02080000 ########################################################## done.
10272 00:41:52.398101
10273 00:41:52.400203 The bootfile was 34552966 bytes long.
10274 00:41:52.400647
10275 00:41:52.404111 Sending tftp read request... done.
10276 00:41:52.404685
10277 00:41:52.407573 Waiting for the transfer...
10278 00:41:52.407988
10279 00:41:52.408309 00000000 # done.
10280 00:41:52.408620
10281 00:41:52.414055 Command line loaded dynamically from TFTP file: 14368366/tftp-deploy-h8e7f32o/kernel/cmdline
10282 00:41:52.414491
10283 00:41:52.430596 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10284 00:41:52.431075
10285 00:41:52.431423 Loading FIT.
10286 00:41:52.431732
10287 00:41:52.433804 Image ramdisk-1 has 21377299 bytes.
10288 00:41:52.434251
10289 00:41:52.437608 Image fdt-1 has 47258 bytes.
10290 00:41:52.438114
10291 00:41:52.440928 Image kernel-1 has 13126376 bytes.
10292 00:41:52.441336
10293 00:41:52.447391 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10294 00:41:52.447920
10295 00:41:52.466582 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10296 00:41:52.467098
10297 00:41:52.469897 Choosing best match conf-1 for compat google,spherion-rev2.
10298 00:41:52.475117
10299 00:41:52.479296 Connected to device vid:did:rid of 1ae0:0028:00
10300 00:41:52.486431
10301 00:41:52.489711 tpm_get_response: command 0x17b, return code 0x0
10302 00:41:52.490134
10303 00:41:52.493062 ec_init: CrosEC protocol v3 supported (256, 248)
10304 00:41:52.497161
10305 00:41:52.500791 tpm_cleanup: add release locality here.
10306 00:41:52.501302
10307 00:41:52.501623 Shutting down all USB controllers.
10308 00:41:52.503610
10309 00:41:52.504012 Removing current net device
10310 00:41:52.504333
10311 00:41:52.510417 Exiting depthcharge with code 4 at timestamp: 77904299
10312 00:41:52.510821
10313 00:41:52.513617 LZMA decompressing kernel-1 to 0x821a6718
10314 00:41:52.514021
10315 00:41:52.516661 LZMA decompressing kernel-1 to 0x40000000
10316 00:41:54.133476
10317 00:41:54.133614 jumping to kernel
10318 00:41:54.134100 end: 2.2.4 bootloader-commands (duration 00:00:50) [common]
10319 00:41:54.134210 start: 2.2.5 auto-login-action (timeout 00:03:36) [common]
10320 00:41:54.134291 Setting prompt string to ['Linux version [0-9]']
10321 00:41:54.134365 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10322 00:41:54.134438 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10323 00:41:54.215728
10324 00:41:54.219280 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10325 00:41:54.222609 start: 2.2.5.1 login-action (timeout 00:03:36) [common]
10326 00:41:54.223131 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10327 00:41:54.223527 Setting prompt string to []
10328 00:41:54.223948 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10329 00:41:54.224338 Using line separator: #'\n'#
10330 00:41:54.224679 No login prompt set.
10331 00:41:54.225013 Parsing kernel messages
10332 00:41:54.225321 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10333 00:41:54.226013 [login-action] Waiting for messages, (timeout 00:03:36)
10334 00:41:54.226443 Waiting using forced prompt support (timeout 00:01:48)
10335 00:41:54.242507 [ 0.000000] Linux version 6.1.92-cip22 (KernelCI@build-j232175-arm64-gcc-10-defconfig-arm64-chromebook-7lg8d) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sun Jun 16 00:28:47 UTC 2024
10336 00:41:54.245521 [ 0.000000] random: crng init done
10337 00:41:54.252274 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10338 00:41:54.255402 [ 0.000000] efi: UEFI not found.
10339 00:41:54.262194 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10340 00:41:54.272086 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10341 00:41:54.282023 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10342 00:41:54.288125 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10343 00:41:54.294775 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10344 00:41:54.301654 [ 0.000000] printk: bootconsole [mtk8250] enabled
10345 00:41:54.307848 [ 0.000000] NUMA: No NUMA configuration found
10346 00:41:54.314540 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10347 00:41:54.321541 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10348 00:41:54.322050 [ 0.000000] Zone ranges:
10349 00:41:54.327608 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10350 00:41:54.331058 [ 0.000000] DMA32 empty
10351 00:41:54.337626 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10352 00:41:54.341066 [ 0.000000] Movable zone start for each node
10353 00:41:54.344553 [ 0.000000] Early memory node ranges
10354 00:41:54.350647 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10355 00:41:54.357314 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10356 00:41:54.363937 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10357 00:41:54.370574 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10358 00:41:54.376947 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10359 00:41:54.383517 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10360 00:41:54.440438 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10361 00:41:54.446805 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10362 00:41:54.454257 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10363 00:41:54.456934 [ 0.000000] psci: probing for conduit method from DT.
10364 00:41:54.463411 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10365 00:41:54.467253 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10366 00:41:54.473366 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10367 00:41:54.477481 [ 0.000000] psci: SMC Calling Convention v1.2
10368 00:41:54.483200 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10369 00:41:54.487073 [ 0.000000] Detected VIPT I-cache on CPU0
10370 00:41:54.493514 [ 0.000000] CPU features: detected: GIC system register CPU interface
10371 00:41:54.499703 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10372 00:41:54.506234 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10373 00:41:54.512792 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10374 00:41:54.522905 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10375 00:41:54.529077 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10376 00:41:54.532300 [ 0.000000] alternatives: applying boot alternatives
10377 00:41:54.539312 [ 0.000000] Fallback order for Node 0: 0
10378 00:41:54.545923 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10379 00:41:54.549207 [ 0.000000] Policy zone: Normal
10380 00:41:54.562227 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10381 00:41:54.572010 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10382 00:41:54.584104 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10383 00:41:54.594072 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10384 00:41:54.600858 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10385 00:41:54.603854 <6>[ 0.000000] software IO TLB: area num 8.
10386 00:41:54.660304 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10387 00:41:54.809510 <6>[ 0.000000] Memory: 7943184K/8385536K available (18112K kernel code, 4120K rwdata, 22644K rodata, 8512K init, 616K bss, 409584K reserved, 32768K cma-reserved)
10388 00:41:54.816348 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10389 00:41:54.822661 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10390 00:41:54.825909 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10391 00:41:54.832622 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10392 00:41:54.839067 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10393 00:41:54.842560 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10394 00:41:54.852423 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10395 00:41:54.859287 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10396 00:41:54.865528 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10397 00:41:54.872314 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10398 00:41:54.875529 <6>[ 0.000000] GICv3: 608 SPIs implemented
10399 00:41:54.878784 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10400 00:41:54.885284 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10401 00:41:54.888842 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10402 00:41:54.895498 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10403 00:41:54.908230 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10404 00:41:54.921649 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10405 00:41:54.929181 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10406 00:41:54.935855 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10407 00:41:54.948864 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10408 00:41:54.955660 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10409 00:41:54.962398 <6>[ 0.009232] Console: colour dummy device 80x25
10410 00:41:54.972111 <6>[ 0.013960] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10411 00:41:54.978655 <6>[ 0.024401] pid_max: default: 32768 minimum: 301
10412 00:41:54.982333 <6>[ 0.029302] LSM: Security Framework initializing
10413 00:41:54.988777 <6>[ 0.034240] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10414 00:41:54.998494 <6>[ 0.042055] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10415 00:41:55.008834 <6>[ 0.051471] cblist_init_generic: Setting adjustable number of callback queues.
10416 00:41:55.011940 <6>[ 0.058915] cblist_init_generic: Setting shift to 3 and lim to 1.
10417 00:41:55.021664 <6>[ 0.065294] cblist_init_generic: Setting adjustable number of callback queues.
10418 00:41:55.028502 <6>[ 0.072720] cblist_init_generic: Setting shift to 3 and lim to 1.
10419 00:41:55.031758 <6>[ 0.079121] rcu: Hierarchical SRCU implementation.
10420 00:41:55.038127 <6>[ 0.084136] rcu: Max phase no-delay instances is 1000.
10421 00:41:55.044696 <6>[ 0.091191] EFI services will not be available.
10422 00:41:55.048264 <6>[ 0.096182] smp: Bringing up secondary CPUs ...
10423 00:41:55.056720 <6>[ 0.101231] Detected VIPT I-cache on CPU1
10424 00:41:55.063380 <6>[ 0.101301] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10425 00:41:55.069926 <6>[ 0.101334] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10426 00:41:55.073345 <6>[ 0.101669] Detected VIPT I-cache on CPU2
10427 00:41:55.080025 <6>[ 0.101723] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10428 00:41:55.089825 <6>[ 0.101741] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10429 00:41:55.093219 <6>[ 0.101999] Detected VIPT I-cache on CPU3
10430 00:41:55.099339 <6>[ 0.102045] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10431 00:41:55.106101 <6>[ 0.102059] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10432 00:41:55.113145 <6>[ 0.102363] CPU features: detected: Spectre-v4
10433 00:41:55.116225 <6>[ 0.102369] CPU features: detected: Spectre-BHB
10434 00:41:55.119255 <6>[ 0.102374] Detected PIPT I-cache on CPU4
10435 00:41:55.125873 <6>[ 0.102433] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10436 00:41:55.132512 <6>[ 0.102451] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10437 00:41:55.139326 <6>[ 0.102745] Detected PIPT I-cache on CPU5
10438 00:41:55.145707 <6>[ 0.102808] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10439 00:41:55.152217 <6>[ 0.102824] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10440 00:41:55.155563 <6>[ 0.103106] Detected PIPT I-cache on CPU6
10441 00:41:55.165515 <6>[ 0.103172] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10442 00:41:55.172065 <6>[ 0.103188] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10443 00:41:55.175406 <6>[ 0.103484] Detected PIPT I-cache on CPU7
10444 00:41:55.182322 <6>[ 0.103548] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10445 00:41:55.188738 <6>[ 0.103564] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10446 00:41:55.191880 <6>[ 0.103612] smp: Brought up 1 node, 8 CPUs
10447 00:41:55.198582 <6>[ 0.245064] SMP: Total of 8 processors activated.
10448 00:41:55.204856 <6>[ 0.249985] CPU features: detected: 32-bit EL0 Support
10449 00:41:55.211766 <6>[ 0.255348] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10450 00:41:55.218545 <6>[ 0.264148] CPU features: detected: Common not Private translations
10451 00:41:55.224859 <6>[ 0.270623] CPU features: detected: CRC32 instructions
10452 00:41:55.231456 <6>[ 0.276008] CPU features: detected: RCpc load-acquire (LDAPR)
10453 00:41:55.235184 <6>[ 0.281968] CPU features: detected: LSE atomic instructions
10454 00:41:55.241771 <6>[ 0.287785] CPU features: detected: Privileged Access Never
10455 00:41:55.248029 <6>[ 0.293565] CPU features: detected: RAS Extension Support
10456 00:41:55.254869 <6>[ 0.299174] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10457 00:41:55.258039 <6>[ 0.306439] CPU: All CPU(s) started at EL2
10458 00:41:55.264459 <6>[ 0.310755] alternatives: applying system-wide alternatives
10459 00:41:55.274571 <6>[ 0.321632] devtmpfs: initialized
10460 00:41:55.290544 <6>[ 0.330480] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10461 00:41:55.296976 <6>[ 0.340437] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10462 00:41:55.303095 <6>[ 0.348247] pinctrl core: initialized pinctrl subsystem
10463 00:41:55.306470 <6>[ 0.354924] DMI not present or invalid.
10464 00:41:55.313092 <6>[ 0.359335] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10465 00:41:55.323304 <6>[ 0.366187] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10466 00:41:55.330021 <6>[ 0.373774] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10467 00:41:55.339549 <6>[ 0.381991] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10468 00:41:55.342766 <6>[ 0.390235] audit: initializing netlink subsys (disabled)
10469 00:41:55.352648 <5>[ 0.395926] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10470 00:41:55.359286 <6>[ 0.396643] thermal_sys: Registered thermal governor 'step_wise'
10471 00:41:55.366141 <6>[ 0.403894] thermal_sys: Registered thermal governor 'power_allocator'
10472 00:41:55.369580 <6>[ 0.410150] cpuidle: using governor menu
10473 00:41:55.375371 <6>[ 0.421112] NET: Registered PF_QIPCRTR protocol family
10474 00:41:55.381882 <6>[ 0.426589] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10475 00:41:55.388437 <6>[ 0.433692] ASID allocator initialised with 32768 entries
10476 00:41:55.391962 <6>[ 0.440267] Serial: AMBA PL011 UART driver
10477 00:41:55.402664 <4>[ 0.449150] Trying to register duplicate clock ID: 134
10478 00:41:55.460699 <6>[ 0.510632] KASLR enabled
10479 00:41:55.474955 <6>[ 0.518339] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10480 00:41:55.481197 <6>[ 0.525353] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10481 00:41:55.488220 <6>[ 0.531844] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10482 00:41:55.494800 <6>[ 0.538850] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10483 00:41:55.501218 <6>[ 0.545337] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10484 00:41:55.507648 <6>[ 0.552340] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10485 00:41:55.514370 <6>[ 0.558826] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10486 00:41:55.521295 <6>[ 0.565830] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10487 00:41:55.524755 <6>[ 0.573351] ACPI: Interpreter disabled.
10488 00:41:55.533286 <6>[ 0.579779] iommu: Default domain type: Translated
10489 00:41:55.540018 <6>[ 0.584893] iommu: DMA domain TLB invalidation policy: strict mode
10490 00:41:55.543290 <5>[ 0.591553] SCSI subsystem initialized
10491 00:41:55.549733 <6>[ 0.595722] usbcore: registered new interface driver usbfs
10492 00:41:55.556416 <6>[ 0.601453] usbcore: registered new interface driver hub
10493 00:41:55.559692 <6>[ 0.607006] usbcore: registered new device driver usb
10494 00:41:55.566211 <6>[ 0.613110] pps_core: LinuxPPS API ver. 1 registered
10495 00:41:55.575922 <6>[ 0.618303] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10496 00:41:55.579416 <6>[ 0.627650] PTP clock support registered
10497 00:41:55.582480 <6>[ 0.631894] EDAC MC: Ver: 3.0.0
10498 00:41:55.590215 <6>[ 0.637038] FPGA manager framework
10499 00:41:55.596820 <6>[ 0.640722] Advanced Linux Sound Architecture Driver Initialized.
10500 00:41:55.599764 <6>[ 0.647500] vgaarb: loaded
10501 00:41:55.606216 <6>[ 0.650645] clocksource: Switched to clocksource arch_sys_counter
10502 00:41:55.609705 <5>[ 0.657080] VFS: Disk quotas dquot_6.6.0
10503 00:41:55.616142 <6>[ 0.661266] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10504 00:41:55.619444 <6>[ 0.668459] pnp: PnP ACPI: disabled
10505 00:41:55.628323 <6>[ 0.675178] NET: Registered PF_INET protocol family
10506 00:41:55.638548 <6>[ 0.680775] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10507 00:41:55.649482 <6>[ 0.693113] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10508 00:41:55.659918 <6>[ 0.701928] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10509 00:41:55.666330 <6>[ 0.709901] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10510 00:41:55.675560 <6>[ 0.718600] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10511 00:41:55.682509 <6>[ 0.728354] TCP: Hash tables configured (established 65536 bind 65536)
10512 00:41:55.688765 <6>[ 0.735219] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10513 00:41:55.698734 <6>[ 0.742420] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10514 00:41:55.705209 <6>[ 0.750108] NET: Registered PF_UNIX/PF_LOCAL protocol family
10515 00:41:55.711805 <6>[ 0.756261] RPC: Registered named UNIX socket transport module.
10516 00:41:55.715148 <6>[ 0.762415] RPC: Registered udp transport module.
10517 00:41:55.721803 <6>[ 0.767348] RPC: Registered tcp transport module.
10518 00:41:55.728519 <6>[ 0.772280] RPC: Registered tcp NFSv4.1 backchannel transport module.
10519 00:41:55.731940 <6>[ 0.778947] PCI: CLS 0 bytes, default 64
10520 00:41:55.735046 <6>[ 0.783263] Unpacking initramfs...
10521 00:41:55.751678 <6>[ 0.795190] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10522 00:41:55.761730 <6>[ 0.803832] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10523 00:41:55.765103 <6>[ 0.812655] kvm [1]: IPA Size Limit: 40 bits
10524 00:41:55.772588 <6>[ 0.817172] kvm [1]: GICv3: no GICV resource entry
10525 00:41:55.774774 <6>[ 0.822193] kvm [1]: disabling GICv2 emulation
10526 00:41:55.781363 <6>[ 0.826878] kvm [1]: GIC system register CPU interface enabled
10527 00:41:55.784600 <6>[ 0.833040] kvm [1]: vgic interrupt IRQ18
10528 00:41:55.791585 <6>[ 0.837392] kvm [1]: VHE mode initialized successfully
10529 00:41:55.797645 <5>[ 0.843909] Initialise system trusted keyrings
10530 00:41:55.804382 <6>[ 0.848708] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10531 00:41:55.812608 <6>[ 0.858842] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10532 00:41:55.818708 <5>[ 0.865229] NFS: Registering the id_resolver key type
10533 00:41:55.822281 <5>[ 0.870530] Key type id_resolver registered
10534 00:41:55.828786 <5>[ 0.874946] Key type id_legacy registered
10535 00:41:55.835568 <6>[ 0.879232] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10536 00:41:55.842222 <6>[ 0.886152] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10537 00:41:55.848385 <6>[ 0.893866] 9p: Installing v9fs 9p2000 file system support
10538 00:41:55.884609 <5>[ 0.931128] Key type asymmetric registered
10539 00:41:55.887819 <5>[ 0.935468] Asymmetric key parser 'x509' registered
10540 00:41:55.897922 <6>[ 0.940633] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10541 00:41:55.901535 <6>[ 0.948249] io scheduler mq-deadline registered
10542 00:41:55.904917 <6>[ 0.953029] io scheduler kyber registered
10543 00:41:55.923639 <6>[ 0.970158] EINJ: ACPI disabled.
10544 00:41:55.956521 <4>[ 0.996321] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10545 00:41:55.966209 <4>[ 1.006976] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10546 00:41:55.981263 <6>[ 1.027770] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10547 00:41:55.989232 <6>[ 1.035859] printk: console [ttyS0] disabled
10548 00:41:56.017087 <6>[ 1.060487] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10549 00:41:56.023724 <6>[ 1.069961] printk: console [ttyS0] enabled
10550 00:41:56.026907 <6>[ 1.069961] printk: console [ttyS0] enabled
10551 00:41:56.033889 <6>[ 1.078856] printk: bootconsole [mtk8250] disabled
10552 00:41:56.037014 <6>[ 1.078856] printk: bootconsole [mtk8250] disabled
10553 00:41:56.043403 <6>[ 1.090065] SuperH (H)SCI(F) driver initialized
10554 00:41:56.046673 <6>[ 1.095359] msm_serial: driver initialized
10555 00:41:56.061334 <6>[ 1.104361] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10556 00:41:56.071100 <6>[ 1.112909] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10557 00:41:56.077637 <6>[ 1.121451] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10558 00:41:56.087418 <6>[ 1.130078] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10559 00:41:56.097862 <6>[ 1.138786] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10560 00:41:56.104163 <6>[ 1.147505] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10561 00:41:56.113766 <6>[ 1.156045] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10562 00:41:56.120445 <6>[ 1.164855] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10563 00:41:56.130213 <6>[ 1.173397] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10564 00:41:56.142065 <6>[ 1.188630] loop: module loaded
10565 00:41:56.148521 <6>[ 1.194627] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10566 00:41:56.171641 <4>[ 1.217887] mtk-pmic-keys: Failed to locate of_node [id: -1]
10567 00:41:56.177914 <6>[ 1.224696] megasas: 07.719.03.00-rc1
10568 00:41:56.188118 <6>[ 1.234286] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10569 00:41:56.199776 <6>[ 1.246015] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10570 00:41:56.216331 <6>[ 1.262581] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10571 00:41:56.276488 <6>[ 1.316313] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10572 00:41:56.641530 <6>[ 1.688235] Freeing initrd memory: 20872K
10573 00:41:56.657399 <6>[ 1.704134] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10574 00:41:56.668337 <6>[ 1.714918] tun: Universal TUN/TAP device driver, 1.6
10575 00:41:56.671613 <6>[ 1.720965] thunder_xcv, ver 1.0
10576 00:41:56.674923 <6>[ 1.724472] thunder_bgx, ver 1.0
10577 00:41:56.678964 <6>[ 1.727967] nicpf, ver 1.0
10578 00:41:56.689118 <6>[ 1.731991] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10579 00:41:56.692213 <6>[ 1.739467] hns3: Copyright (c) 2017 Huawei Corporation.
10580 00:41:56.699253 <6>[ 1.745053] hclge is initializing
10581 00:41:56.702035 <6>[ 1.748627] e1000: Intel(R) PRO/1000 Network Driver
10582 00:41:56.708795 <6>[ 1.753756] e1000: Copyright (c) 1999-2006 Intel Corporation.
10583 00:41:56.712524 <6>[ 1.759769] e1000e: Intel(R) PRO/1000 Network Driver
10584 00:41:56.718575 <6>[ 1.764984] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10585 00:41:56.726244 <6>[ 1.771170] igb: Intel(R) Gigabit Ethernet Network Driver
10586 00:41:56.732068 <6>[ 1.776819] igb: Copyright (c) 2007-2014 Intel Corporation.
10587 00:41:56.738432 <6>[ 1.782658] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10588 00:41:56.745124 <6>[ 1.789176] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10589 00:41:56.748264 <6>[ 1.795636] sky2: driver version 1.30
10590 00:41:56.754685 <6>[ 1.800557] usbcore: registered new device driver r8152-cfgselector
10591 00:41:56.761597 <6>[ 1.807092] usbcore: registered new interface driver r8152
10592 00:41:56.767890 <6>[ 1.812907] VFIO - User Level meta-driver version: 0.3
10593 00:41:56.774458 <6>[ 1.821119] usbcore: registered new interface driver usb-storage
10594 00:41:56.780953 <6>[ 1.827562] usbcore: registered new device driver onboard-usb-hub
10595 00:41:56.790271 <6>[ 1.836737] mt6397-rtc mt6359-rtc: registered as rtc0
10596 00:41:56.800413 <6>[ 1.842195] mt6397-rtc mt6359-rtc: setting system clock to 2024-06-16T00:41:56 UTC (1718498516)
10597 00:41:56.803304 <6>[ 1.851785] i2c_dev: i2c /dev entries driver
10598 00:41:56.817179 <4>[ 1.863779] cpu cpu0: supply cpu not found, using dummy regulator
10599 00:41:56.823893 <4>[ 1.870206] cpu cpu1: supply cpu not found, using dummy regulator
10600 00:41:56.830301 <4>[ 1.876631] cpu cpu2: supply cpu not found, using dummy regulator
10601 00:41:56.836749 <4>[ 1.883037] cpu cpu3: supply cpu not found, using dummy regulator
10602 00:41:56.843265 <4>[ 1.889435] cpu cpu4: supply cpu not found, using dummy regulator
10603 00:41:56.850145 <4>[ 1.895851] cpu cpu5: supply cpu not found, using dummy regulator
10604 00:41:56.856894 <4>[ 1.902250] cpu cpu6: supply cpu not found, using dummy regulator
10605 00:41:56.863303 <4>[ 1.908647] cpu cpu7: supply cpu not found, using dummy regulator
10606 00:41:56.882648 <6>[ 1.929282] cpu cpu0: EM: created perf domain
10607 00:41:56.885765 <6>[ 1.934218] cpu cpu4: EM: created perf domain
10608 00:41:56.893256 <6>[ 1.939806] sdhci: Secure Digital Host Controller Interface driver
10609 00:41:56.899551 <6>[ 1.946240] sdhci: Copyright(c) Pierre Ossman
10610 00:41:56.906512 <6>[ 1.951193] Synopsys Designware Multimedia Card Interface Driver
10611 00:41:56.909929 <6>[ 1.957813] mmc0: CQHCI version 5.10
10612 00:41:56.916576 <6>[ 1.957822] sdhci-pltfm: SDHCI platform and OF driver helper
10613 00:41:56.923064 <6>[ 1.968633] ledtrig-cpu: registered to indicate activity on CPUs
10614 00:41:56.929560 <6>[ 1.975607] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10615 00:41:56.936278 <6>[ 1.982663] usbcore: registered new interface driver usbhid
10616 00:41:56.939905 <6>[ 1.988484] usbhid: USB HID core driver
10617 00:41:56.949369 <6>[ 1.992697] spi_master spi0: will run message pump with realtime priority
10618 00:41:56.989486 <6>[ 2.030037] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10619 00:41:57.008362 <6>[ 2.045318] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10620 00:41:57.011617 <6>[ 2.054046] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x15414
10621 00:41:57.018983 <6>[ 2.065787] cros-ec-spi spi0.0: Chrome EC device registered
10622 00:41:57.025360 <6>[ 2.071819] mmc0: Command Queue Engine enabled
10623 00:41:57.031996 <6>[ 2.076583] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10624 00:41:57.038577 <6>[ 2.084474] mmcblk0: mmc0:0001 DA4128 116 GiB
10625 00:41:57.047122 <6>[ 2.093747] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10626 00:41:57.055304 <6>[ 2.101400] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10627 00:41:57.065189 <6>[ 2.106983] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10628 00:41:57.071519 <6>[ 2.107405] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10629 00:41:57.075355 <6>[ 2.117627] NET: Registered PF_PACKET protocol family
10630 00:41:57.081520 <6>[ 2.122334] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10631 00:41:57.084459 <6>[ 2.126898] 9pnet: Installing 9P2000 support
10632 00:41:57.091680 <5>[ 2.137892] Key type dns_resolver registered
10633 00:41:57.095118 <6>[ 2.142888] registered taskstats version 1
10634 00:41:57.101295 <5>[ 2.147260] Loading compiled-in X.509 certificates
10635 00:41:57.130914 <4>[ 2.170986] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10636 00:41:57.141225 <4>[ 2.181720] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10637 00:41:57.155758 <6>[ 2.202307] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10638 00:41:57.162862 <6>[ 2.209339] xhci-mtk 11200000.usb: xHCI Host Controller
10639 00:41:57.169247 <6>[ 2.214837] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10640 00:41:57.179499 <6>[ 2.222690] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10641 00:41:57.186145 <6>[ 2.232129] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10642 00:41:57.193000 <6>[ 2.238208] xhci-mtk 11200000.usb: xHCI Host Controller
10643 00:41:57.199170 <6>[ 2.243695] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10644 00:41:57.206364 <6>[ 2.251346] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10645 00:41:57.213170 <6>[ 2.258974] hub 1-0:1.0: USB hub found
10646 00:41:57.216678 <6>[ 2.262993] hub 1-0:1.0: 1 port detected
10647 00:41:57.222646 <6>[ 2.267277] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10648 00:41:57.229254 <6>[ 2.275809] hub 2-0:1.0: USB hub found
10649 00:41:57.232255 <6>[ 2.279816] hub 2-0:1.0: 1 port detected
10650 00:41:57.240253 <6>[ 2.286747] mtk-msdc 11f70000.mmc: Got CD GPIO
10651 00:41:57.254504 <6>[ 2.297553] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10652 00:41:57.263956 <6>[ 2.305942] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10653 00:41:57.270538 <6>[ 2.314284] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10654 00:41:57.280856 <6>[ 2.322626] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10655 00:41:57.287110 <6>[ 2.330965] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10656 00:41:57.296957 <6>[ 2.339305] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10657 00:41:57.304742 <6>[ 2.347644] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10658 00:41:57.313569 <6>[ 2.355983] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10659 00:41:57.320770 <6>[ 2.364330] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10660 00:41:57.330397 <6>[ 2.372671] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10661 00:41:57.337459 <6>[ 2.381008] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10662 00:41:57.346791 <6>[ 2.389351] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10663 00:41:57.353484 <6>[ 2.397688] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10664 00:41:57.363349 <6>[ 2.406026] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10665 00:41:57.369908 <6>[ 2.414365] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10666 00:41:57.376827 <6>[ 2.423071] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10667 00:41:57.383537 <6>[ 2.430206] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10668 00:41:57.390221 <6>[ 2.437005] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10669 00:41:57.400586 <6>[ 2.443769] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10670 00:41:57.406863 <6>[ 2.450718] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10671 00:41:57.413609 <6>[ 2.457602] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10672 00:41:57.423500 <6>[ 2.466747] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10673 00:41:57.433446 <6>[ 2.475868] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10674 00:41:57.443484 <6>[ 2.485163] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10675 00:41:57.453340 <6>[ 2.494629] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10676 00:41:57.462994 <6>[ 2.504099] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10677 00:41:57.469589 <6>[ 2.513219] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10678 00:41:57.479627 <6>[ 2.522686] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10679 00:41:57.489846 <6>[ 2.531805] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10680 00:41:57.499368 <6>[ 2.541103] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10681 00:41:57.509318 <6>[ 2.551262] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10682 00:41:57.519522 <6>[ 2.562984] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10683 00:41:57.643313 <6>[ 2.686927] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10684 00:41:57.798277 <6>[ 2.845005] hub 1-1:1.0: USB hub found
10685 00:41:57.801500 <6>[ 2.849526] hub 1-1:1.0: 4 ports detected
10686 00:41:57.813790 <6>[ 2.860384] hub 1-1:1.0: USB hub found
10687 00:41:57.816904 <6>[ 2.864735] hub 1-1:1.0: 4 ports detected
10688 00:41:57.923913 <6>[ 2.967161] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10689 00:41:57.949476 <6>[ 2.996390] hub 2-1:1.0: USB hub found
10690 00:41:57.952542 <6>[ 3.000890] hub 2-1:1.0: 3 ports detected
10691 00:41:57.964495 <6>[ 3.011302] hub 2-1:1.0: USB hub found
10692 00:41:57.967894 <6>[ 3.015729] hub 2-1:1.0: 3 ports detected
10693 00:41:58.139576 <6>[ 3.182965] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10694 00:41:58.271810 <6>[ 3.318834] hub 1-1.4:1.0: USB hub found
10695 00:41:58.274744 <6>[ 3.323499] hub 1-1.4:1.0: 2 ports detected
10696 00:41:58.288127 <6>[ 3.335246] hub 1-1.4:1.0: USB hub found
10697 00:41:58.291353 <6>[ 3.339824] hub 1-1.4:1.0: 2 ports detected
10698 00:41:58.351138 <6>[ 3.395166] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10699 00:41:58.459539 <6>[ 3.503595] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10700 00:41:58.496564 <4>[ 3.540597] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10701 00:41:58.506707 <4>[ 3.549779] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10702 00:41:58.545148 <6>[ 3.592542] r8152 2-1.3:1.0 eth0: v1.12.13
10703 00:41:58.587239 <6>[ 3.630992] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10704 00:41:58.782537 <6>[ 3.826801] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10705 00:42:00.286535 <6>[ 5.333703] r8152 2-1.3:1.0 eth0: carrier on
10706 00:42:02.603337 <5>[ 5.354729] Sending DHCP requests .., OK
10707 00:42:02.610365 <6>[ 7.655146] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.14
10708 00:42:02.613256 <6>[ 7.663438] IP-Config: Complete:
10709 00:42:02.626533 <6>[ 7.666929] device=eth0, hwaddr=00:e0:4c:68:02:81, ipaddr=192.168.201.14, mask=255.255.255.0, gw=192.168.201.1
10710 00:42:02.633126 <6>[ 7.677642] host=mt8192-asurada-spherion-r0-cbg-9, domain=lava-rack, nis-domain=(none)
10711 00:42:02.643154 <6>[ 7.686260] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10712 00:42:02.646234 <6>[ 7.686269] nameserver0=192.168.201.1
10713 00:42:02.649839 <6>[ 7.698383] clk: Disabling unused clocks
10714 00:42:02.653260 <6>[ 7.703868] ALSA device list:
10715 00:42:02.659971 <6>[ 7.707169] No soundcards found.
10716 00:42:02.667543 <6>[ 7.714773] Freeing unused kernel memory: 8512K
10717 00:42:02.671223 <6>[ 7.719768] Run /init as init process
10718 00:42:02.696215 Starting syslogd: OK
10719 00:42:02.699061 Starting klogd: OK
10720 00:42:02.709704 Running sysctl: OK
10721 00:42:02.719709 Populating /dev using udev: <30>[ 7.766705] udevd[197]: starting version 3.2.9
10722 00:42:02.728241 <27>[ 7.775298] udevd[197]: specified user 'tss' unknown
10723 00:42:02.735052 <27>[ 7.780742] udevd[197]: specified group 'tss' unknown
10724 00:42:02.741703 <30>[ 7.787279] udevd[198]: starting eudev-3.2.9
10725 00:42:02.760228 <27>[ 7.807378] udevd[198]: specified user 'tss' unknown
10726 00:42:02.766924 <27>[ 7.812798] udevd[198]: specified group 'tss' unknown
10727 00:42:02.909503 <6>[ 7.953247] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10728 00:42:02.915975 <6>[ 7.953336] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10729 00:42:02.928406 <6>[ 7.971496] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10730 00:42:02.938055 <6>[ 7.975978] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10731 00:42:02.944225 <3>[ 7.977737] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10732 00:42:02.951117 <3>[ 7.977753] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10733 00:42:02.960741 <3>[ 7.977761] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10734 00:42:02.967180 <3>[ 7.979288] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10735 00:42:02.977064 <3>[ 7.979316] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10736 00:42:02.983662 <3>[ 7.979324] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10737 00:42:02.993721 <3>[ 7.979340] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10738 00:42:03.000135 <3>[ 7.979350] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10739 00:42:03.009935 <3>[ 7.979523] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10740 00:42:03.016528 <3>[ 7.979642] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10741 00:42:03.026852 <3>[ 7.979652] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10742 00:42:03.033234 <3>[ 7.979662] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10743 00:42:03.043322 <3>[ 7.979711] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10744 00:42:03.050107 <3>[ 7.979719] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10745 00:42:03.056594 <3>[ 7.979726] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10746 00:42:03.066020 <3>[ 7.979733] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10747 00:42:03.073223 <3>[ 7.979740] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10748 00:42:03.082760 <3>[ 7.979779] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10749 00:42:03.089425 <6>[ 7.980904] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10750 00:42:03.100075 <6>[ 7.988356] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10751 00:42:03.106738 <6>[ 7.989181] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10752 00:42:03.113195 <6>[ 7.992036] remoteproc remoteproc0: scp is available
10753 00:42:03.116562 <6>[ 7.992937] remoteproc remoteproc0: powering up scp
10754 00:42:03.126405 <6>[ 7.992949] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10755 00:42:03.129638 <6>[ 7.992976] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10756 00:42:03.139874 <4>[ 8.030238] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10757 00:42:03.146114 <6>[ 8.030969] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10758 00:42:03.156096 <4>[ 8.037217] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10759 00:42:03.162656 <4>[ 8.045325] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10760 00:42:03.169239 <6>[ 8.053801] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10761 00:42:03.179503 <4>[ 8.057863] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10762 00:42:03.186047 <4>[ 8.057863] Fallback method does not support PEC.
10763 00:42:03.189080 <6>[ 8.071181] mc: Linux media interface: v0.10
10764 00:42:03.195715 <6>[ 8.077458] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10765 00:42:03.205631 <6>[ 8.077870] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10766 00:42:03.212520 <3>[ 8.087489] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10767 00:42:03.221996 <6>[ 8.094260] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10768 00:42:03.228783 <6>[ 8.118530] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10769 00:42:03.235169 <6>[ 8.118541] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10770 00:42:03.245195 <6>[ 8.124419] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10771 00:42:03.248807 <6>[ 8.124445] pci_bus 0000:00: root bus resource [bus 00-ff]
10772 00:42:03.255134 <6>[ 8.124463] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10773 00:42:03.265300 <6>[ 8.124470] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10774 00:42:03.271316 <6>[ 8.124631] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10775 00:42:03.281292 <6>[ 8.124683] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10776 00:42:03.284686 <6>[ 8.124822] pci 0000:00:00.0: supports D1 D2
10777 00:42:03.291328 <6>[ 8.124829] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10778 00:42:03.297784 <6>[ 8.126466] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10779 00:42:03.307756 <6>[ 8.126475] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10780 00:42:03.317469 <6>[ 8.129293] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10781 00:42:03.324039 <6>[ 8.134610] remoteproc remoteproc0: remote processor scp is now up
10782 00:42:03.333936 <6>[ 8.236807] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10783 00:42:03.340891 <3>[ 8.241189] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10784 00:42:03.347170 <6>[ 8.241352] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10785 00:42:03.354091 <6>[ 8.241384] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10786 00:42:03.364115 <6>[ 8.241404] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10787 00:42:03.370522 <6>[ 8.241421] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10788 00:42:03.373850 <6>[ 8.241541] pci 0000:01:00.0: supports D1 D2
10789 00:42:03.380387 <6>[ 8.241545] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10790 00:42:03.390241 <6>[ 8.242450] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10791 00:42:03.397212 <6>[ 8.246975] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10792 00:42:03.403621 <6>[ 8.254849] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10793 00:42:03.413519 <6>[ 8.257656] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10794 00:42:03.423308 <6>[ 8.265686] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10795 00:42:03.433527 <6>[ 8.273918] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10796 00:42:03.439950 <6>[ 8.282143] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10797 00:42:03.446259 <6>[ 8.296589] videodev: Linux video capture interface: v2.00
10798 00:42:03.452863 <6>[ 8.302027] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10799 00:42:03.456156 <6>[ 8.319369] Bluetooth: Core ver 2.22
10800 00:42:03.466057 <6>[ 8.325112] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10801 00:42:03.472802 <6>[ 8.325127] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10802 00:42:03.479141 <6>[ 8.332671] NET: Registered PF_BLUETOOTH protocol family
10803 00:42:03.482727 <6>[ 8.337124] pci 0000:00:00.0: PCI bridge to [bus 01]
10804 00:42:03.489103 <6>[ 8.343975] Bluetooth: HCI device and connection manager initialized
10805 00:42:03.495806 <6>[ 8.343994] Bluetooth: HCI socket layer initialized
10806 00:42:03.502438 <6>[ 8.351795] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10807 00:42:03.509047 <6>[ 8.360912] Bluetooth: L2CAP socket layer initialized
10808 00:42:03.515304 <6>[ 8.369323] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10809 00:42:03.522141 <6>[ 8.370296] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10810 00:42:03.535484 <6>[ 8.371846] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10811 00:42:03.542493 <6>[ 8.372109] usbcore: registered new interface driver uvcvideo
10812 00:42:03.545084 <6>[ 8.375604] Bluetooth: SCO socket layer initialized
10813 00:42:03.551729 <6>[ 8.385743] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10814 00:42:03.558966 <6>[ 8.394883] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10815 00:42:03.565071 <6>[ 8.400694] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10816 00:42:03.571641 <6>[ 8.450696] usbcore: registered new interface driver btusb
10817 00:42:03.581455 <4>[ 8.451772] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10818 00:42:03.588556 <3>[ 8.451789] Bluetooth: hci0: Failed to load firmware file (-2)
10819 00:42:03.591272 <3>[ 8.451796] Bluetooth: hci0: Failed to set up firmware (-2)
10820 00:42:03.604513 <4>[ 8.451802] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10821 00:42:03.611126 <5>[ 8.478150] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10822 00:42:03.647442 <5>[ 8.691775] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10823 00:42:03.654374 <5>[ 8.698918] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10824 00:42:03.663866 <4>[ 8.707322] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10825 00:42:03.667315 <6>[ 8.716197] cfg80211: failed to load regulatory.db
10826 00:42:03.714698 <6>[ 8.758620] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10827 00:42:03.721329 <6>[ 8.766128] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10828 00:42:03.745107 <6>[ 8.792807] mt7921e 0000:01:00.0: ASIC revision: 79610010
10829 00:42:03.846405 <6>[ 8.890409] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10830 00:42:03.849551 <6>[ 8.890409]
10831 00:42:03.850123 done
10832 00:42:03.860924 Saving random seed: OK
10833 00:42:03.871274 Starting network: ip: RTNETLINK answers: File exists
10834 00:42:03.874437 FAIL
10835 00:42:03.915438 Starting dropbear sshd: <6>[ 8.962021] NET: Registered PF_INET6 protocol family
10836 00:42:03.921877 <6>[ 8.968920] Segment Routing with IPv6
10837 00:42:03.925022 <6>[ 8.972885] In-situ OAM (IOAM) with IPv6
10838 00:42:03.928490 OK
10839 00:42:03.937973 /bin/sh: can't access tty; job control turned off
10840 00:42:03.939246 Matched prompt #10: / #
10842 00:42:03.940302 Setting prompt string to ['/ #']
10843 00:42:03.940757 end: 2.2.5.1 login-action (duration 00:00:10) [common]
10845 00:42:03.941790 end: 2.2.5 auto-login-action (duration 00:00:10) [common]
10846 00:42:03.942297 start: 2.2.6 expect-shell-connection (timeout 00:03:27) [common]
10847 00:42:03.942684 Setting prompt string to ['/ #']
10848 00:42:03.943010 Forcing a shell prompt, looking for ['/ #']
10850 00:42:03.993796 / #
10851 00:42:03.994477 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10852 00:42:03.994918 Waiting using forced prompt support (timeout 00:02:30)
10853 00:42:04.000364
10854 00:42:04.001280 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10855 00:42:04.002027 start: 2.2.7 export-device-env (timeout 00:03:27) [common]
10856 00:42:04.002583 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10857 00:42:04.003052 end: 2.2 depthcharge-retry (duration 00:01:33) [common]
10858 00:42:04.003548 end: 2 depthcharge-action (duration 00:01:33) [common]
10859 00:42:04.004020 start: 3 lava-test-retry (timeout 00:01:00) [common]
10860 00:42:04.004490 start: 3.1 lava-test-shell (timeout 00:01:00) [common]
10861 00:42:04.004889 Using namespace: common
10863 00:42:04.106130 / # #
10864 00:42:04.106843 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
10865 00:42:04.150744 #<6>[ 9.157246] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10866 00:42:04.151293
10867 00:42:04.151998 Using /lava-14368366
10869 00:42:04.253100 / # export SHELL=/bin/sh
10870 00:42:04.260280 export SHELL=/bin/sh
10872 00:42:04.362356 / # . /lava-14368366/environment
10873 00:42:04.369391 . /lava-14368366/environment
10875 00:42:04.471182 / # /lava-14368366/bin/lava-test-runner /lava-14368366/0
10876 00:42:04.471372 Test shell timeout: 10s (minimum of the action and connection timeout)
10877 00:42:04.476228 /lava-14368366/bin/lava-test-runner /lava-14368366/0
10878 00:42:04.494556 + export 'TESTRUN_ID=0_dmesg'
10879 00:42:04.501540 + c<8>[ 9.548070] <LAVA_SIGNAL_STARTRUN 0_dmesg 14368366_1.5.2.3.1>
10880 00:42:04.502385 Received signal: <STARTRUN> 0_dmesg 14368366_1.5.2.3.1
10881 00:42:04.502791 Starting test lava.0_dmesg (14368366_1.5.2.3.1)
10882 00:42:04.503222 Skipping test definition patterns.
10883 00:42:04.504774 d /lava-14368366/0/tests/0_dmesg
10884 00:42:04.505220 + cat uuid
10885 00:42:04.508206 + UUID=14368366_1.5.2.3.1
10886 00:42:04.508664 + set +x
10887 00:42:04.514840 + KERNELCI_LAVA=y /bin/sh /opt/kernelci/dmesg.sh
10888 00:42:04.524200 <8>[ 9.566944] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0>
10889 00:42:04.524916 Received signal: <TESTCASE> TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0
10891 00:42:04.543129 <8>[ 9.587383] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0>
10892 00:42:04.543815 Received signal: <TESTCASE> TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0
10894 00:42:04.561829 <8>[ 9.606300] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0>
10895 00:42:04.562802 Received signal: <TESTCASE> TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0
10897 00:42:04.568824 + <8>[ 9.615683] <LAVA_SIGNAL_ENDRUN 0_dmesg 14368366_1.5.2.3.1>
10898 00:42:04.569287 set +x
10899 00:42:04.569909 Received signal: <ENDRUN> 0_dmesg 14368366_1.5.2.3.1
10900 00:42:04.570457 Ending use of test pattern.
10901 00:42:04.571108 Ending test lava.0_dmesg (14368366_1.5.2.3.1), duration 0.07
10903 00:42:04.573508 <LAVA_TEST_RUNNER EXIT>
10904 00:42:04.574230 ok: lava_test_shell seems to have completed
10905 00:42:04.574945 alert: pass
crit: pass
emerg: pass
10906 00:42:04.575612 end: 3.1 lava-test-shell (duration 00:00:01) [common]
10907 00:42:04.576086 end: 3 lava-test-retry (duration 00:00:01) [common]
10908 00:42:04.576552 start: 4 finalize (timeout 00:08:04) [common]
10909 00:42:04.577020 start: 4.1 power-off (timeout 00:00:30) [common]
10910 00:42:04.577843 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-9', '--port=1', '--command=off']
10911 00:42:04.829792 >> Command sent successfully.
10912 00:42:04.840205 Returned 0 in 0 seconds
10913 00:42:04.941592 end: 4.1 power-off (duration 00:00:00) [common]
10915 00:42:04.943125 start: 4.2 read-feedback (timeout 00:08:03) [common]
10916 00:42:04.944424 Listened to connection for namespace 'common' for up to 1s
10917 00:42:05.945037 Finalising connection for namespace 'common'
10918 00:42:05.945696 Disconnecting from shell: Finalise
10919 00:42:05.946052 / #
10920 00:42:06.047123 end: 4.2 read-feedback (duration 00:00:01) [common]
10921 00:42:06.047779 end: 4 finalize (duration 00:00:01) [common]
10922 00:42:06.048320 Cleaning after the job
10923 00:42:06.048806 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14368366/tftp-deploy-h8e7f32o/ramdisk
10924 00:42:06.058969 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14368366/tftp-deploy-h8e7f32o/kernel
10925 00:42:06.085407 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14368366/tftp-deploy-h8e7f32o/dtb
10926 00:42:06.085868 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14368366/tftp-deploy-h8e7f32o/modules
10927 00:42:06.096317 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14368366
10928 00:42:06.140395 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14368366
10929 00:42:06.140573 Job finished correctly