Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 41
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 25
1 00:39:26.259370 lava-dispatcher, installed at version: 2024.03
2 00:39:26.259606 start: 0 validate
3 00:39:26.259726 Start time: 2024-06-16 00:39:26.259719+00:00 (UTC)
4 00:39:26.259865 Using caching service: 'http://localhost/cache/?uri=%s'
5 00:39:26.260011 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 00:39:26.512710 Using caching service: 'http://localhost/cache/?uri=%s'
7 00:39:26.512883 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22-24-g0315de64ea248%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 00:39:26.763107 Using caching service: 'http://localhost/cache/?uri=%s'
9 00:39:26.763868 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22-24-g0315de64ea248%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 00:39:42.163181 Using caching service: 'http://localhost/cache/?uri=%s'
11 00:39:42.163827 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 00:39:42.660992 Using caching service: 'http://localhost/cache/?uri=%s'
13 00:39:42.661637 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22-24-g0315de64ea248%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 00:39:42.920557 validate duration: 16.66
16 00:39:42.921764 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 00:39:42.922351 start: 1.1 download-retry (timeout 00:10:00) [common]
18 00:39:42.922848 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 00:39:42.923601 Not decompressing ramdisk as can be used compressed.
20 00:39:42.924057 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm/20240313.0/arm64/initrd.cpio.gz
21 00:39:42.924388 saving as /var/lib/lava/dispatcher/tmp/14368404/tftp-deploy-4qyk1yvl/ramdisk/initrd.cpio.gz
22 00:39:42.924709 total size: 5628182 (5 MB)
23 00:39:45.237586 progress 0 % (0 MB)
24 00:39:45.242767 progress 5 % (0 MB)
25 00:39:45.244305 progress 10 % (0 MB)
26 00:39:45.245684 progress 15 % (0 MB)
27 00:39:45.247254 progress 20 % (1 MB)
28 00:39:45.248631 progress 25 % (1 MB)
29 00:39:45.250148 progress 30 % (1 MB)
30 00:39:45.251699 progress 35 % (1 MB)
31 00:39:45.253043 progress 40 % (2 MB)
32 00:39:45.254571 progress 45 % (2 MB)
33 00:39:45.255888 progress 50 % (2 MB)
34 00:39:45.257344 progress 55 % (2 MB)
35 00:39:45.258855 progress 60 % (3 MB)
36 00:39:45.260161 progress 65 % (3 MB)
37 00:39:45.261635 progress 70 % (3 MB)
38 00:39:45.262983 progress 75 % (4 MB)
39 00:39:45.264475 progress 80 % (4 MB)
40 00:39:45.265776 progress 85 % (4 MB)
41 00:39:45.267316 progress 90 % (4 MB)
42 00:39:45.268806 progress 95 % (5 MB)
43 00:39:45.270121 progress 100 % (5 MB)
44 00:39:45.270362 5 MB downloaded in 2.35 s (2.29 MB/s)
45 00:39:45.270509 end: 1.1.1 http-download (duration 00:00:02) [common]
47 00:39:45.270725 end: 1.1 download-retry (duration 00:00:02) [common]
48 00:39:45.270805 start: 1.2 download-retry (timeout 00:09:58) [common]
49 00:39:45.270881 start: 1.2.1 http-download (timeout 00:09:58) [common]
50 00:39:45.271006 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-24-g0315de64ea248/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 00:39:45.271068 saving as /var/lib/lava/dispatcher/tmp/14368404/tftp-deploy-4qyk1yvl/kernel/Image
52 00:39:45.271120 total size: 54813184 (52 MB)
53 00:39:45.271173 No compression specified
54 00:39:45.272110 progress 0 % (0 MB)
55 00:39:45.285713 progress 5 % (2 MB)
56 00:39:45.299261 progress 10 % (5 MB)
57 00:39:45.312495 progress 15 % (7 MB)
58 00:39:45.326019 progress 20 % (10 MB)
59 00:39:45.339760 progress 25 % (13 MB)
60 00:39:45.353117 progress 30 % (15 MB)
61 00:39:45.366591 progress 35 % (18 MB)
62 00:39:45.380195 progress 40 % (20 MB)
63 00:39:45.394481 progress 45 % (23 MB)
64 00:39:45.408320 progress 50 % (26 MB)
65 00:39:45.422155 progress 55 % (28 MB)
66 00:39:45.436155 progress 60 % (31 MB)
67 00:39:45.450312 progress 65 % (34 MB)
68 00:39:45.464310 progress 70 % (36 MB)
69 00:39:45.478345 progress 75 % (39 MB)
70 00:39:45.492128 progress 80 % (41 MB)
71 00:39:45.505681 progress 85 % (44 MB)
72 00:39:45.519403 progress 90 % (47 MB)
73 00:39:45.533055 progress 95 % (49 MB)
74 00:39:45.547259 progress 100 % (52 MB)
75 00:39:45.547504 52 MB downloaded in 0.28 s (189.14 MB/s)
76 00:39:45.547658 end: 1.2.1 http-download (duration 00:00:00) [common]
78 00:39:45.547871 end: 1.2 download-retry (duration 00:00:00) [common]
79 00:39:45.547955 start: 1.3 download-retry (timeout 00:09:57) [common]
80 00:39:45.548032 start: 1.3.1 http-download (timeout 00:09:57) [common]
81 00:39:45.548162 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-24-g0315de64ea248/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 00:39:45.548228 saving as /var/lib/lava/dispatcher/tmp/14368404/tftp-deploy-4qyk1yvl/dtb/mt8192-asurada-spherion-r0.dtb
83 00:39:45.548283 total size: 47258 (0 MB)
84 00:39:45.548338 No compression specified
85 00:39:45.549459 progress 69 % (0 MB)
86 00:39:45.549721 progress 100 % (0 MB)
87 00:39:45.549870 0 MB downloaded in 0.00 s (28.44 MB/s)
88 00:39:45.549982 end: 1.3.1 http-download (duration 00:00:00) [common]
90 00:39:45.550185 end: 1.3 download-retry (duration 00:00:00) [common]
91 00:39:45.550307 start: 1.4 download-retry (timeout 00:09:57) [common]
92 00:39:45.550385 start: 1.4.1 http-download (timeout 00:09:57) [common]
93 00:39:45.550491 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm/20240313.0/arm64/full.rootfs.tar.xz
94 00:39:45.550550 saving as /var/lib/lava/dispatcher/tmp/14368404/tftp-deploy-4qyk1yvl/nfsrootfs/full.rootfs.tar
95 00:39:45.550603 total size: 107552908 (102 MB)
96 00:39:45.550657 Using unxz to decompress xz
97 00:39:45.551863 progress 0 % (0 MB)
98 00:39:45.832168 progress 5 % (5 MB)
99 00:39:46.145960 progress 10 % (10 MB)
100 00:39:46.456853 progress 15 % (15 MB)
101 00:39:46.767968 progress 20 % (20 MB)
102 00:39:47.035231 progress 25 % (25 MB)
103 00:39:47.328557 progress 30 % (30 MB)
104 00:39:47.621366 progress 35 % (35 MB)
105 00:39:47.791273 progress 40 % (41 MB)
106 00:39:47.986384 progress 45 % (46 MB)
107 00:39:48.294091 progress 50 % (51 MB)
108 00:39:48.589872 progress 55 % (56 MB)
109 00:39:48.902522 progress 60 % (61 MB)
110 00:39:49.213581 progress 65 % (66 MB)
111 00:39:49.528870 progress 70 % (71 MB)
112 00:39:49.847051 progress 75 % (76 MB)
113 00:39:50.148413 progress 80 % (82 MB)
114 00:39:50.453451 progress 85 % (87 MB)
115 00:39:50.752694 progress 90 % (92 MB)
116 00:39:51.064966 progress 95 % (97 MB)
117 00:39:51.381112 progress 100 % (102 MB)
118 00:39:51.399298 102 MB downloaded in 5.85 s (17.54 MB/s)
119 00:39:51.399719 end: 1.4.1 http-download (duration 00:00:06) [common]
121 00:39:51.400238 end: 1.4 download-retry (duration 00:00:06) [common]
122 00:39:51.400422 start: 1.5 download-retry (timeout 00:09:52) [common]
123 00:39:51.400596 start: 1.5.1 http-download (timeout 00:09:52) [common]
124 00:39:51.400860 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-24-g0315de64ea248/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 00:39:51.401001 saving as /var/lib/lava/dispatcher/tmp/14368404/tftp-deploy-4qyk1yvl/modules/modules.tar
126 00:39:51.401124 total size: 8608736 (8 MB)
127 00:39:51.401248 Using unxz to decompress xz
128 00:39:51.403873 progress 0 % (0 MB)
129 00:39:51.433045 progress 5 % (0 MB)
130 00:39:51.460570 progress 10 % (0 MB)
131 00:39:51.488256 progress 15 % (1 MB)
132 00:39:51.511448 progress 20 % (1 MB)
133 00:39:51.534681 progress 25 % (2 MB)
134 00:39:51.558408 progress 30 % (2 MB)
135 00:39:51.582676 progress 35 % (2 MB)
136 00:39:51.608572 progress 40 % (3 MB)
137 00:39:51.630590 progress 45 % (3 MB)
138 00:39:51.655846 progress 50 % (4 MB)
139 00:39:51.681044 progress 55 % (4 MB)
140 00:39:51.705148 progress 60 % (4 MB)
141 00:39:51.729046 progress 65 % (5 MB)
142 00:39:51.753360 progress 70 % (5 MB)
143 00:39:51.779312 progress 75 % (6 MB)
144 00:39:51.806365 progress 80 % (6 MB)
145 00:39:51.831230 progress 85 % (7 MB)
146 00:39:51.857331 progress 90 % (7 MB)
147 00:39:51.883036 progress 95 % (7 MB)
148 00:39:51.908452 progress 100 % (8 MB)
149 00:39:51.913966 8 MB downloaded in 0.51 s (16.01 MB/s)
150 00:39:51.914131 end: 1.5.1 http-download (duration 00:00:01) [common]
152 00:39:51.914386 end: 1.5 download-retry (duration 00:00:01) [common]
153 00:39:51.914466 start: 1.6 prepare-tftp-overlay (timeout 00:09:51) [common]
154 00:39:51.914541 start: 1.6.1 extract-nfsrootfs (timeout 00:09:51) [common]
155 00:39:54.081004 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/14368404/extract-nfsrootfs-_3z5vp51
156 00:39:54.081212 end: 1.6.1 extract-nfsrootfs (duration 00:00:02) [common]
157 00:39:54.081304 start: 1.6.2 lava-overlay (timeout 00:09:49) [common]
158 00:39:54.081448 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14368404/lava-overlay-o8g75r6x
159 00:39:54.081563 makedir: /var/lib/lava/dispatcher/tmp/14368404/lava-overlay-o8g75r6x/lava-14368404/bin
160 00:39:54.081653 makedir: /var/lib/lava/dispatcher/tmp/14368404/lava-overlay-o8g75r6x/lava-14368404/tests
161 00:39:54.081740 makedir: /var/lib/lava/dispatcher/tmp/14368404/lava-overlay-o8g75r6x/lava-14368404/results
162 00:39:54.081819 Creating /var/lib/lava/dispatcher/tmp/14368404/lava-overlay-o8g75r6x/lava-14368404/bin/lava-add-keys
163 00:39:54.081942 Creating /var/lib/lava/dispatcher/tmp/14368404/lava-overlay-o8g75r6x/lava-14368404/bin/lava-add-sources
164 00:39:54.082057 Creating /var/lib/lava/dispatcher/tmp/14368404/lava-overlay-o8g75r6x/lava-14368404/bin/lava-background-process-start
165 00:39:54.082172 Creating /var/lib/lava/dispatcher/tmp/14368404/lava-overlay-o8g75r6x/lava-14368404/bin/lava-background-process-stop
166 00:39:54.082451 Creating /var/lib/lava/dispatcher/tmp/14368404/lava-overlay-o8g75r6x/lava-14368404/bin/lava-common-functions
167 00:39:54.082568 Creating /var/lib/lava/dispatcher/tmp/14368404/lava-overlay-o8g75r6x/lava-14368404/bin/lava-echo-ipv4
168 00:39:54.082682 Creating /var/lib/lava/dispatcher/tmp/14368404/lava-overlay-o8g75r6x/lava-14368404/bin/lava-install-packages
169 00:39:54.082794 Creating /var/lib/lava/dispatcher/tmp/14368404/lava-overlay-o8g75r6x/lava-14368404/bin/lava-installed-packages
170 00:39:54.082905 Creating /var/lib/lava/dispatcher/tmp/14368404/lava-overlay-o8g75r6x/lava-14368404/bin/lava-os-build
171 00:39:54.083015 Creating /var/lib/lava/dispatcher/tmp/14368404/lava-overlay-o8g75r6x/lava-14368404/bin/lava-probe-channel
172 00:39:54.083127 Creating /var/lib/lava/dispatcher/tmp/14368404/lava-overlay-o8g75r6x/lava-14368404/bin/lava-probe-ip
173 00:39:54.083238 Creating /var/lib/lava/dispatcher/tmp/14368404/lava-overlay-o8g75r6x/lava-14368404/bin/lava-target-ip
174 00:39:54.083349 Creating /var/lib/lava/dispatcher/tmp/14368404/lava-overlay-o8g75r6x/lava-14368404/bin/lava-target-mac
175 00:39:54.083462 Creating /var/lib/lava/dispatcher/tmp/14368404/lava-overlay-o8g75r6x/lava-14368404/bin/lava-target-storage
176 00:39:54.083575 Creating /var/lib/lava/dispatcher/tmp/14368404/lava-overlay-o8g75r6x/lava-14368404/bin/lava-test-case
177 00:39:54.083687 Creating /var/lib/lava/dispatcher/tmp/14368404/lava-overlay-o8g75r6x/lava-14368404/bin/lava-test-event
178 00:39:54.083796 Creating /var/lib/lava/dispatcher/tmp/14368404/lava-overlay-o8g75r6x/lava-14368404/bin/lava-test-feedback
179 00:39:54.083904 Creating /var/lib/lava/dispatcher/tmp/14368404/lava-overlay-o8g75r6x/lava-14368404/bin/lava-test-raise
180 00:39:54.084014 Creating /var/lib/lava/dispatcher/tmp/14368404/lava-overlay-o8g75r6x/lava-14368404/bin/lava-test-reference
181 00:39:54.084124 Creating /var/lib/lava/dispatcher/tmp/14368404/lava-overlay-o8g75r6x/lava-14368404/bin/lava-test-runner
182 00:39:54.084233 Creating /var/lib/lava/dispatcher/tmp/14368404/lava-overlay-o8g75r6x/lava-14368404/bin/lava-test-set
183 00:39:54.084341 Creating /var/lib/lava/dispatcher/tmp/14368404/lava-overlay-o8g75r6x/lava-14368404/bin/lava-test-shell
184 00:39:54.084453 Updating /var/lib/lava/dispatcher/tmp/14368404/lava-overlay-o8g75r6x/lava-14368404/bin/lava-install-packages (oe)
185 00:39:54.084587 Updating /var/lib/lava/dispatcher/tmp/14368404/lava-overlay-o8g75r6x/lava-14368404/bin/lava-installed-packages (oe)
186 00:39:54.084695 Creating /var/lib/lava/dispatcher/tmp/14368404/lava-overlay-o8g75r6x/lava-14368404/environment
187 00:39:54.084780 LAVA metadata
188 00:39:54.084843 - LAVA_JOB_ID=14368404
189 00:39:54.084899 - LAVA_DISPATCHER_IP=192.168.201.1
190 00:39:54.084989 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:49) [common]
191 00:39:54.085043 skipped lava-vland-overlay
192 00:39:54.085109 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
193 00:39:54.085178 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:49) [common]
194 00:39:54.085230 skipped lava-multinode-overlay
195 00:39:54.085293 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
196 00:39:54.085361 start: 1.6.2.3 test-definition (timeout 00:09:49) [common]
197 00:39:54.085423 Loading test definitions
198 00:39:54.085513 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:49) [common]
199 00:39:54.085574 Using /lava-14368404 at stage 0
200 00:39:54.085865 uuid=14368404_1.6.2.3.1 testdef=None
201 00:39:54.085945 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
202 00:39:54.086019 start: 1.6.2.3.2 test-overlay (timeout 00:09:49) [common]
203 00:39:54.086491 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
205 00:39:54.086687 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:49) [common]
206 00:39:54.087274 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
208 00:39:54.087480 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:49) [common]
209 00:39:54.088050 runner path: /var/lib/lava/dispatcher/tmp/14368404/lava-overlay-o8g75r6x/lava-14368404/0/tests/0_dmesg test_uuid 14368404_1.6.2.3.1
210 00:39:54.088192 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
212 00:39:54.088373 Creating lava-test-runner.conf files
213 00:39:54.088428 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14368404/lava-overlay-o8g75r6x/lava-14368404/0 for stage 0
214 00:39:54.088538 - 0_dmesg
215 00:39:54.088702 end: 1.6.2.3 test-definition (duration 00:00:00) [common]
216 00:39:54.088781 start: 1.6.2.4 compress-overlay (timeout 00:09:49) [common]
217 00:39:54.094086 end: 1.6.2.4 compress-overlay (duration 00:00:00) [common]
218 00:39:54.094183 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:49) [common]
219 00:39:54.094530 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
220 00:39:54.094610 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
221 00:39:54.094687 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:49) [common]
222 00:39:54.252821 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
223 00:39:54.252970 start: 1.6.4 extract-modules (timeout 00:09:49) [common]
224 00:39:54.253046 extracting modules file /var/lib/lava/dispatcher/tmp/14368404/tftp-deploy-4qyk1yvl/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14368404/extract-nfsrootfs-_3z5vp51
225 00:39:54.472501 extracting modules file /var/lib/lava/dispatcher/tmp/14368404/tftp-deploy-4qyk1yvl/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14368404/extract-overlay-ramdisk-d6z1etnd/ramdisk
226 00:39:54.698088 end: 1.6.4 extract-modules (duration 00:00:00) [common]
227 00:39:54.698340 start: 1.6.5 apply-overlay-tftp (timeout 00:09:48) [common]
228 00:39:54.698425 [common] Applying overlay to NFS
229 00:39:54.698485 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14368404/compress-overlay-raozgmp_/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14368404/extract-nfsrootfs-_3z5vp51
230 00:39:54.704640 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
231 00:39:54.704736 start: 1.6.6 configure-preseed-file (timeout 00:09:48) [common]
232 00:39:54.704816 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
233 00:39:54.704893 start: 1.6.7 compress-ramdisk (timeout 00:09:48) [common]
234 00:39:54.704958 Building ramdisk /var/lib/lava/dispatcher/tmp/14368404/extract-overlay-ramdisk-d6z1etnd/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14368404/extract-overlay-ramdisk-d6z1etnd/ramdisk
235 00:39:55.030074 >> 130405 blocks
236 00:39:57.102356 rename /var/lib/lava/dispatcher/tmp/14368404/extract-overlay-ramdisk-d6z1etnd/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14368404/tftp-deploy-4qyk1yvl/ramdisk/ramdisk.cpio.gz
237 00:39:57.102584 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
238 00:39:57.102719 start: 1.6.8 prepare-kernel (timeout 00:09:46) [common]
239 00:39:57.102835 start: 1.6.8.1 prepare-fit (timeout 00:09:46) [common]
240 00:39:57.102941 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14368404/tftp-deploy-4qyk1yvl/kernel/Image']
241 00:40:11.234729 Returned 0 in 14 seconds
242 00:40:11.335261 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14368404/tftp-deploy-4qyk1yvl/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14368404/tftp-deploy-4qyk1yvl/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14368404/tftp-deploy-4qyk1yvl/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14368404/tftp-deploy-4qyk1yvl/kernel/image.itb
243 00:40:11.812913 output: FIT description: Kernel Image image with one or more FDT blobs
244 00:40:11.813068 output: Created: Sun Jun 16 01:40:11 2024
245 00:40:11.813142 output: Image 0 (kernel-1)
246 00:40:11.813206 output: Description:
247 00:40:11.813264 output: Created: Sun Jun 16 01:40:11 2024
248 00:40:11.813332 output: Type: Kernel Image
249 00:40:11.813391 output: Compression: lzma compressed
250 00:40:11.813478 output: Data Size: 13126376 Bytes = 12818.73 KiB = 12.52 MiB
251 00:40:11.813562 output: Architecture: AArch64
252 00:40:11.813611 output: OS: Linux
253 00:40:11.813661 output: Load Address: 0x00000000
254 00:40:11.813722 output: Entry Point: 0x00000000
255 00:40:11.813773 output: Hash algo: crc32
256 00:40:11.813824 output: Hash value: c791a20a
257 00:40:11.813873 output: Image 1 (fdt-1)
258 00:40:11.813920 output: Description: mt8192-asurada-spherion-r0
259 00:40:11.813969 output: Created: Sun Jun 16 01:40:11 2024
260 00:40:11.814017 output: Type: Flat Device Tree
261 00:40:11.814066 output: Compression: uncompressed
262 00:40:11.814114 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
263 00:40:11.814162 output: Architecture: AArch64
264 00:40:11.814221 output: Hash algo: crc32
265 00:40:11.814308 output: Hash value: 0f8e4d2e
266 00:40:11.814360 output: Image 2 (ramdisk-1)
267 00:40:11.814414 output: Description: unavailable
268 00:40:11.814464 output: Created: Sun Jun 16 01:40:11 2024
269 00:40:11.814519 output: Type: RAMDisk Image
270 00:40:11.814569 output: Compression: uncompressed
271 00:40:11.814617 output: Data Size: 18734127 Bytes = 18295.05 KiB = 17.87 MiB
272 00:40:11.814666 output: Architecture: AArch64
273 00:40:11.814713 output: OS: Linux
274 00:40:11.814761 output: Load Address: unavailable
275 00:40:11.814808 output: Entry Point: unavailable
276 00:40:11.814855 output: Hash algo: crc32
277 00:40:11.814902 output: Hash value: 0b294f46
278 00:40:11.814950 output: Default Configuration: 'conf-1'
279 00:40:11.814998 output: Configuration 0 (conf-1)
280 00:40:11.815045 output: Description: mt8192-asurada-spherion-r0
281 00:40:11.815093 output: Kernel: kernel-1
282 00:40:11.815140 output: Init Ramdisk: ramdisk-1
283 00:40:11.815187 output: FDT: fdt-1
284 00:40:11.815234 output: Loadables: kernel-1
285 00:40:11.815281 output:
286 00:40:11.815419 end: 1.6.8.1 prepare-fit (duration 00:00:15) [common]
287 00:40:11.815508 end: 1.6.8 prepare-kernel (duration 00:00:15) [common]
288 00:40:11.815598 end: 1.6 prepare-tftp-overlay (duration 00:00:20) [common]
289 00:40:11.815679 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:31) [common]
290 00:40:11.815749 No LXC device requested
291 00:40:11.815816 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
292 00:40:11.815892 start: 1.8 deploy-device-env (timeout 00:09:31) [common]
293 00:40:11.815963 end: 1.8 deploy-device-env (duration 00:00:00) [common]
294 00:40:11.816021 Checking files for TFTP limit of 4294967296 bytes.
295 00:40:11.816473 end: 1 tftp-deploy (duration 00:00:29) [common]
296 00:40:11.816570 start: 2 depthcharge-action (timeout 00:05:00) [common]
297 00:40:11.816655 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
298 00:40:11.816767 substitutions:
299 00:40:11.816827 - {DTB}: 14368404/tftp-deploy-4qyk1yvl/dtb/mt8192-asurada-spherion-r0.dtb
300 00:40:11.816883 - {INITRD}: 14368404/tftp-deploy-4qyk1yvl/ramdisk/ramdisk.cpio.gz
301 00:40:11.816935 - {KERNEL}: 14368404/tftp-deploy-4qyk1yvl/kernel/Image
302 00:40:11.816985 - {LAVA_MAC}: None
303 00:40:11.817036 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/14368404/extract-nfsrootfs-_3z5vp51
304 00:40:11.817085 - {NFS_SERVER_IP}: 192.168.201.1
305 00:40:11.817134 - {PRESEED_CONFIG}: None
306 00:40:11.817189 - {PRESEED_LOCAL}: None
307 00:40:11.817239 - {RAMDISK}: 14368404/tftp-deploy-4qyk1yvl/ramdisk/ramdisk.cpio.gz
308 00:40:11.817288 - {ROOT_PART}: None
309 00:40:11.817335 - {ROOT}: None
310 00:40:11.817383 - {SERVER_IP}: 192.168.201.1
311 00:40:11.817431 - {TEE}: None
312 00:40:11.817479 Parsed boot commands:
313 00:40:11.817526 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
314 00:40:11.817678 Parsed boot commands: tftpboot 192.168.201.1 14368404/tftp-deploy-4qyk1yvl/kernel/image.itb 14368404/tftp-deploy-4qyk1yvl/kernel/cmdline
315 00:40:11.817762 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
316 00:40:11.817837 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
317 00:40:11.817915 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
318 00:40:11.817991 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
319 00:40:11.818052 Not connected, no need to disconnect.
320 00:40:11.818118 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
321 00:40:11.818191 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
322 00:40:11.818312 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-4'
323 00:40:11.821839 Setting prompt string to ['lava-test: # ']
324 00:40:11.822175 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
325 00:40:11.822315 end: 2.2.1 reset-connection (duration 00:00:00) [common]
326 00:40:11.822426 start: 2.2.2 reset-device (timeout 00:05:00) [common]
327 00:40:11.822511 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
328 00:40:11.822756 Calling: ['/usr/local/bin/chromebook-reboot.sh', 'mt8192-asurada-spherion-r0-cbg-4']
329 00:40:25.353081 Returned 0 in 13 seconds
330 00:40:25.454029 end: 2.2.2.1 pdu-reboot (duration 00:00:14) [common]
332 00:40:25.455445 end: 2.2.2 reset-device (duration 00:00:14) [common]
333 00:40:25.455945 start: 2.2.3 depthcharge-start (timeout 00:04:46) [common]
334 00:40:25.456393 Setting prompt string to 'Starting depthcharge on Spherion...'
335 00:40:25.456828 Changing prompt to 'Starting depthcharge on Spherion...'
336 00:40:25.457188 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
337 00:40:25.459009 [Enter `^Ec?' for help]
338 00:40:25.459400
339 00:40:25.459750
340 00:40:25.460154 F0: 102B 0000
341 00:40:25.460456
342 00:40:25.460724 F3: 1001 0000 [0200]
343 00:40:25.460995
344 00:40:25.461271 F3: 1001 0000
345 00:40:25.461531
346 00:40:25.461786 F7: 102D 0000
347 00:40:25.462037
348 00:40:25.462329 F1: 0000 0000
349 00:40:25.462588
350 00:40:25.462849 V0: 0000 0000 [0001]
351 00:40:25.463107
352 00:40:25.463388 00: 0007 8000
353 00:40:25.463775
354 00:40:25.464059 01: 0000 0000
355 00:40:25.464333
356 00:40:25.464600 BP: 0C00 0209 [0000]
357 00:40:25.464979
358 00:40:25.465236 G0: 1182 0000
359 00:40:25.465484
360 00:40:25.465736 EC: 0000 0021 [4000]
361 00:40:25.465986
362 00:40:25.466262 S7: 0000 0000 [0000]
363 00:40:25.466522
364 00:40:25.466883 CC: 0000 0000 [0001]
365 00:40:25.467141
366 00:40:25.467389 T0: 0000 0040 [010F]
367 00:40:25.467640
368 00:40:25.467888 Jump to BL
369 00:40:25.468135
370 00:40:25.468380
371 00:40:25.468624
372 00:40:25.468828 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
373 00:40:25.469018 ARM64: Exception handlers installed.
374 00:40:25.469198 ARM64: Testing exception
375 00:40:25.469374 ARM64: Done test exception
376 00:40:25.469549 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
377 00:40:25.469727 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
378 00:40:25.469993 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
379 00:40:25.470289 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
380 00:40:25.470482 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
381 00:40:25.470663 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
382 00:40:25.470843 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
383 00:40:25.471022 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
384 00:40:25.471199 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
385 00:40:25.471379 WDT: Last reset was cold boot
386 00:40:25.471555 SPI1(PAD0) initialized at 2873684 Hz
387 00:40:25.471730 SPI5(PAD0) initialized at 992727 Hz
388 00:40:25.471908 VBOOT: Loading verstage.
389 00:40:25.472088 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
390 00:40:25.472266 FMAP: Found "FLASH" version 1.1 at 0x20000.
391 00:40:25.472445 FMAP: base = 0x0 size = 0x800000 #areas = 25
392 00:40:25.472622 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
393 00:40:25.472802 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
394 00:40:25.472981 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
395 00:40:25.473158 read SPI 0x96554 0xa1eb: 4594 us, 9022 KB/s, 72.176 Mbps
396 00:40:25.473419
397 00:40:25.473604
398 00:40:25.473772 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
399 00:40:25.473910 ARM64: Exception handlers installed.
400 00:40:25.474044 ARM64: Testing exception
401 00:40:25.474179 ARM64: Done test exception
402 00:40:25.474358 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
403 00:40:25.474498 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
404 00:40:25.474633 Probing TPM: . done!
405 00:40:25.474767 TPM ready after 0 ms
406 00:40:25.474900 Connected to device vid:did:rid of 1ae0:0028:00
407 00:40:25.475032 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
408 00:40:25.475167 Initialized TPM device CR50 revision 0
409 00:40:25.475301 tlcl_send_startup: Startup return code is 0
410 00:40:25.475435 TPM: setup succeeded
411 00:40:25.475568 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
412 00:40:25.475702 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
413 00:40:25.475836 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
414 00:40:25.475972 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
415 00:40:25.476104 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
416 00:40:25.476242 in-header: 03 07 00 00 08 00 00 00
417 00:40:25.476376 in-data: aa e4 47 04 13 02 00 00
418 00:40:25.476510 Chrome EC: UHEPI supported
419 00:40:25.476643 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
420 00:40:25.476851 in-header: 03 a9 00 00 08 00 00 00
421 00:40:25.476996 in-data: 84 60 60 08 00 00 00 00
422 00:40:25.477130 Phase 1
423 00:40:25.477264 FMAP: area GBB found @ 3f5000 (12032 bytes)
424 00:40:25.477400 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
425 00:40:25.477536 VB2:vb2_check_recovery() Recovery was requested manually
426 00:40:25.477670 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x7
427 00:40:25.477804 Recovery requested (1009000e)
428 00:40:25.477938 TPM: Extending digest for VBOOT: boot mode into PCR 0
429 00:40:25.478073 tlcl_extend: response is 0
430 00:40:25.478221 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
431 00:40:25.478388 tlcl_extend: response is 0
432 00:40:25.478526 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
433 00:40:25.478664 read SPI 0x210d4 0x2173b: 15146 us, 9046 KB/s, 72.368 Mbps
434 00:40:25.478799 BS: bootblock times (exec / console): total (unknown) / 148 ms
435 00:40:25.478907
436 00:40:25.479011
437 00:40:25.479118 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
438 00:40:25.479228 ARM64: Exception handlers installed.
439 00:40:25.479334 ARM64: Testing exception
440 00:40:25.479440 ARM64: Done test exception
441 00:40:25.479547 pmic_efuse_setting: Set efuses in 11 msecs
442 00:40:25.479654 pmwrap_interface_init: Select PMIF_VLD_RDY
443 00:40:25.479773 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
444 00:40:25.479917 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
445 00:40:25.480272 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
446 00:40:25.480403 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
447 00:40:25.480514 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
448 00:40:25.480623 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
449 00:40:25.480732 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
450 00:40:25.480841 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
451 00:40:25.480956 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
452 00:40:25.481081 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
453 00:40:25.481189 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
454 00:40:25.481298 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
455 00:40:25.481405 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
456 00:40:25.481511 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
457 00:40:25.481620 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
458 00:40:25.481728 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
459 00:40:25.481849 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
460 00:40:25.481959 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
461 00:40:25.482065 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
462 00:40:25.482173 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
463 00:40:25.482307 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
464 00:40:25.482455 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
465 00:40:25.482566 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
466 00:40:25.482674 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
467 00:40:25.482782 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
468 00:40:25.482890 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
469 00:40:25.483016 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
470 00:40:25.483128 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
471 00:40:25.483235 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
472 00:40:25.483345 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
473 00:40:25.483454 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
474 00:40:25.483579 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
475 00:40:25.483810 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
476 00:40:25.484005 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
477 00:40:25.484199 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
478 00:40:25.484335 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
479 00:40:25.484429 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
480 00:40:25.484521 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
481 00:40:25.484699 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
482 00:40:25.484893 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
483 00:40:25.485070 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
484 00:40:25.485167 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
485 00:40:25.485340 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
486 00:40:25.485535 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
487 00:40:25.485716 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
488 00:40:25.485910 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
489 00:40:25.486104 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
490 00:40:25.486311 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
491 00:40:25.486508 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
492 00:40:25.486703 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
493 00:40:25.486898 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
494 00:40:25.487095 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
495 00:40:25.487297 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
496 00:40:25.487493 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
497 00:40:25.487681 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
498 00:40:25.487782 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
499 00:40:25.487978 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
500 00:40:25.488174 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
501 00:40:25.488369 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
502 00:40:25.488566 [RTC]rtc_enable_dcxo,68: con=0x406, osc32con=0xde70, sec=0x4
503 00:40:25.488751 [RTC]rtc_check_state,173: con=406, pwrkey1=a357, pwrkey2=67d2
504 00:40:25.488883 [RTC]rtc_osc_init,62: osc32con val = 0xde70
505 00:40:25.488967 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
506 00:40:25.489047 [RTC]rtc_get_frequency_meter,154: input=15, output=765
507 00:40:25.489146 [RTC]rtc_get_frequency_meter,154: input=23, output=949
508 00:40:25.489284 [RTC]rtc_get_frequency_meter,154: input=19, output=857
509 00:40:25.489407 [RTC]rtc_get_frequency_meter,154: input=17, output=811
510 00:40:25.489530 [RTC]rtc_get_frequency_meter,154: input=16, output=788
511 00:40:25.489656 [RTC]rtc_get_frequency_meter,154: input=16, output=788
512 00:40:25.489802 [RTC]rtc_get_frequency_meter,154: input=17, output=810
513 00:40:25.489970 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
514 00:40:25.490112 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
515 00:40:25.490462 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
516 00:40:25.490645 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
517 00:40:25.490808 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
518 00:40:25.490968 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
519 00:40:25.491129 ADC[4]: Raw value=670432 ID=5
520 00:40:25.491267 ADC[3]: Raw value=212549 ID=1
521 00:40:25.491389 RAM Code: 0x51
522 00:40:25.491514 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
523 00:40:25.491639 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
524 00:40:25.491764 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-4GB' @0x75180 size 0x8 in mcache @0x00107f9c
525 00:40:25.491887 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
526 00:40:25.492009 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
527 00:40:25.492131 in-header: 03 07 00 00 08 00 00 00
528 00:40:25.492253 in-data: aa e4 47 04 13 02 00 00
529 00:40:25.492375 Chrome EC: UHEPI supported
530 00:40:25.492498 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
531 00:40:25.492621 in-header: 03 a9 00 00 08 00 00 00
532 00:40:25.492742 in-data: 84 60 60 08 00 00 00 00
533 00:40:25.492863 MRC: failed to locate region type 0.
534 00:40:25.492988 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
535 00:40:25.493110 DRAM-K: Running full calibration
536 00:40:25.493233 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
537 00:40:25.493354 header.status = 0x0
538 00:40:25.493475 header.version = 0x6 (expected: 0x6)
539 00:40:25.493596 header.size = 0xd00 (expected: 0xd00)
540 00:40:25.493725 header.flags = 0x0
541 00:40:25.493832 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
542 00:40:25.493941 read SPI 0x72590 0x1c583: 12502 us, 9286 KB/s, 74.288 Mbps
543 00:40:25.494050 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
544 00:40:25.494157 dram_init: ddr_geometry: 0
545 00:40:25.494276 [EMI] MDL number = 0
546 00:40:25.494383 [EMI] Get MDL freq = 0
547 00:40:25.494489 dram_init: ddr_type: 0
548 00:40:25.494595 is_discrete_lpddr4: 1
549 00:40:25.494701 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
550 00:40:25.494806
551 00:40:25.494912
552 00:40:25.495017 [Bian_co] ETT version 0.0.0.1
553 00:40:25.495125 dram_type 6, R0 cbt_mode 0, R1 cbt_mode 0 VENDOR=6
554 00:40:25.495230
555 00:40:25.495336 dramc_set_vcore_voltage set vcore to 650000
556 00:40:25.495444 Read voltage for 800, 4
557 00:40:25.495550 Vio18 = 0
558 00:40:25.495655 Vcore = 650000
559 00:40:25.495760 Vdram = 0
560 00:40:25.495866 Vddq = 0
561 00:40:25.495970 Vmddr = 0
562 00:40:25.496076 dram_init: config_dvfs: 1
563 00:40:25.496184 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
564 00:40:25.496292 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
565 00:40:25.496399 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
566 00:40:25.496505 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
567 00:40:25.496612 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
568 00:40:25.496730 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
569 00:40:25.496803 MEM_TYPE=3, freq_sel=18
570 00:40:25.496871 sv_algorithm_assistance_LP4_1600
571 00:40:25.496940 ============ PULL DRAM RESETB DOWN ============
572 00:40:25.497012 ========== PULL DRAM RESETB DOWN end =========
573 00:40:25.497080 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
574 00:40:25.497148 ===================================
575 00:40:25.497216 LPDDR4 DRAM CONFIGURATION
576 00:40:25.497284 ===================================
577 00:40:25.497352 EX_ROW_EN[0] = 0x0
578 00:40:25.497418 EX_ROW_EN[1] = 0x0
579 00:40:25.497485 LP4Y_EN = 0x0
580 00:40:25.497551 WORK_FSP = 0x0
581 00:40:25.497618 WL = 0x2
582 00:40:25.497685 RL = 0x2
583 00:40:25.497750 BL = 0x2
584 00:40:25.497818 RPST = 0x0
585 00:40:25.497884 RD_PRE = 0x0
586 00:40:25.497951 WR_PRE = 0x1
587 00:40:25.498017 WR_PST = 0x0
588 00:40:25.498082 DBI_WR = 0x0
589 00:40:25.498150 DBI_RD = 0x0
590 00:40:25.498226 OTF = 0x1
591 00:40:25.498298 ===================================
592 00:40:25.498366 ===================================
593 00:40:25.498433 ANA top config
594 00:40:25.498500 ===================================
595 00:40:25.498573 DLL_ASYNC_EN = 0
596 00:40:25.498641 ALL_SLAVE_EN = 1
597 00:40:25.498717 NEW_RANK_MODE = 1
598 00:40:25.498782 DLL_IDLE_MODE = 1
599 00:40:25.498842 LP45_APHY_COMB_EN = 1
600 00:40:25.498906 TX_ODT_DIS = 1
601 00:40:25.498966 NEW_8X_MODE = 1
602 00:40:25.499026 ===================================
603 00:40:25.499086 ===================================
604 00:40:25.499146 data_rate = 1600
605 00:40:25.499205 CKR = 1
606 00:40:25.499265 DQ_P2S_RATIO = 8
607 00:40:25.499324 ===================================
608 00:40:25.499384 CA_P2S_RATIO = 8
609 00:40:25.499443 DQ_CA_OPEN = 0
610 00:40:25.499502 DQ_SEMI_OPEN = 0
611 00:40:25.499561 CA_SEMI_OPEN = 0
612 00:40:25.499621 CA_FULL_RATE = 0
613 00:40:25.499680 DQ_CKDIV4_EN = 1
614 00:40:25.499739 CA_CKDIV4_EN = 1
615 00:40:25.499798 CA_PREDIV_EN = 0
616 00:40:25.499857 PH8_DLY = 0
617 00:40:25.499916 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
618 00:40:25.499975 DQ_AAMCK_DIV = 4
619 00:40:25.500034 CA_AAMCK_DIV = 4
620 00:40:25.500094 CA_ADMCK_DIV = 4
621 00:40:25.500153 DQ_TRACK_CA_EN = 0
622 00:40:25.500212 CA_PICK = 800
623 00:40:25.500270 CA_MCKIO = 800
624 00:40:25.500330 MCKIO_SEMI = 0
625 00:40:25.500388 PLL_FREQ = 3068
626 00:40:25.500448 DQ_UI_PI_RATIO = 32
627 00:40:25.500507 CA_UI_PI_RATIO = 0
628 00:40:25.500567 ===================================
629 00:40:25.500627 ===================================
630 00:40:25.500687 memory_type:LPDDR4
631 00:40:25.500746 GP_NUM : 10
632 00:40:25.500806 SRAM_EN : 1
633 00:40:25.500865 MD32_EN : 0
634 00:40:25.500924 ===================================
635 00:40:25.501206 [ANA_INIT] >>>>>>>>>>>>>>
636 00:40:25.501277 <<<<<< [CONFIGURE PHASE]: ANA_TX
637 00:40:25.501364 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
638 00:40:25.501484 ===================================
639 00:40:25.501590 data_rate = 1600,PCW = 0X7600
640 00:40:25.501696 ===================================
641 00:40:25.501818 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
642 00:40:25.501921 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
643 00:40:25.502026 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
644 00:40:25.502123 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
645 00:40:25.502231 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
646 00:40:25.502338 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
647 00:40:25.502442 [ANA_INIT] flow start
648 00:40:25.502544 [ANA_INIT] PLL >>>>>>>>
649 00:40:25.502655 [ANA_INIT] PLL <<<<<<<<
650 00:40:25.502770 [ANA_INIT] MIDPI >>>>>>>>
651 00:40:25.502868 [ANA_INIT] MIDPI <<<<<<<<
652 00:40:25.502962 [ANA_INIT] DLL >>>>>>>>
653 00:40:25.503059 [ANA_INIT] flow end
654 00:40:25.503167 ============ LP4 DIFF to SE enter ============
655 00:40:25.503269 ============ LP4 DIFF to SE exit ============
656 00:40:25.503365 [ANA_INIT] <<<<<<<<<<<<<
657 00:40:25.503459 [Flow] Enable top DCM control >>>>>
658 00:40:25.503554 [Flow] Enable top DCM control <<<<<
659 00:40:25.503649 Enable DLL master slave shuffle
660 00:40:25.503753 ==============================================================
661 00:40:25.503839 Gating Mode config
662 00:40:25.503925 ==============================================================
663 00:40:25.504011 Config description:
664 00:40:25.504098 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
665 00:40:25.504186 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
666 00:40:25.504273 SELPH_MODE 0: By rank 1: By Phase
667 00:40:25.504360 ==============================================================
668 00:40:25.504446 GAT_TRACK_EN = 1
669 00:40:25.504532 RX_GATING_MODE = 2
670 00:40:25.504617 RX_GATING_TRACK_MODE = 2
671 00:40:25.504710 SELPH_MODE = 1
672 00:40:25.504805 PICG_EARLY_EN = 1
673 00:40:25.504909 VALID_LAT_VALUE = 1
674 00:40:25.504998 ==============================================================
675 00:40:25.505085 Enter into Gating configuration >>>>
676 00:40:25.505172 Exit from Gating configuration <<<<
677 00:40:25.505257 Enter into DVFS_PRE_config >>>>>
678 00:40:25.505346 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
679 00:40:25.505436 Exit from DVFS_PRE_config <<<<<
680 00:40:25.505522 Enter into PICG configuration >>>>
681 00:40:25.505608 Exit from PICG configuration <<<<
682 00:40:25.505694 [RX_INPUT] configuration >>>>>
683 00:40:25.505780 [RX_INPUT] configuration <<<<<
684 00:40:25.505866 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
685 00:40:25.505953 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
686 00:40:25.506041 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
687 00:40:25.506129 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
688 00:40:25.506221 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
689 00:40:25.506310 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
690 00:40:25.506397 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
691 00:40:25.506483 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
692 00:40:25.506569 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
693 00:40:25.506656 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
694 00:40:25.506741 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
695 00:40:25.506827 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
696 00:40:25.506913 ===================================
697 00:40:25.507009 LPDDR4 DRAM CONFIGURATION
698 00:40:25.507104 ===================================
699 00:40:25.507192 EX_ROW_EN[0] = 0x0
700 00:40:25.507277 EX_ROW_EN[1] = 0x0
701 00:40:25.507362 LP4Y_EN = 0x0
702 00:40:25.507447 WORK_FSP = 0x0
703 00:40:25.507532 WL = 0x2
704 00:40:25.507617 RL = 0x2
705 00:40:25.507711 BL = 0x2
706 00:40:25.507809 RPST = 0x0
707 00:40:25.507901 RD_PRE = 0x0
708 00:40:25.507984 WR_PRE = 0x1
709 00:40:25.508040 WR_PST = 0x0
710 00:40:25.508095 DBI_WR = 0x0
711 00:40:25.508149 DBI_RD = 0x0
712 00:40:25.508203 OTF = 0x1
713 00:40:25.508257 ===================================
714 00:40:25.508312 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
715 00:40:25.508366 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
716 00:40:25.508420 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
717 00:40:25.508474 ===================================
718 00:40:25.508529 LPDDR4 DRAM CONFIGURATION
719 00:40:25.508582 ===================================
720 00:40:25.508636 EX_ROW_EN[0] = 0x10
721 00:40:25.508703 EX_ROW_EN[1] = 0x0
722 00:40:25.508751 LP4Y_EN = 0x0
723 00:40:25.508800 WORK_FSP = 0x0
724 00:40:25.508850 WL = 0x2
725 00:40:25.508898 RL = 0x2
726 00:40:25.508947 BL = 0x2
727 00:40:25.508996 RPST = 0x0
728 00:40:25.509044 RD_PRE = 0x0
729 00:40:25.509092 WR_PRE = 0x1
730 00:40:25.509140 WR_PST = 0x0
731 00:40:25.509189 DBI_WR = 0x0
732 00:40:25.509237 DBI_RD = 0x0
733 00:40:25.509286 OTF = 0x1
734 00:40:25.509335 ===================================
735 00:40:25.509384 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
736 00:40:25.509433 nWR fixed to 40
737 00:40:25.509482 [ModeRegInit_LP4] CH0 RK0
738 00:40:25.509531 [ModeRegInit_LP4] CH0 RK1
739 00:40:25.509580 [ModeRegInit_LP4] CH1 RK0
740 00:40:25.509629 [ModeRegInit_LP4] CH1 RK1
741 00:40:25.509678 match AC timing 12
742 00:40:25.509727 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 0
743 00:40:25.509777 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
744 00:40:25.510022 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
745 00:40:25.510081 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
746 00:40:25.510133 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
747 00:40:25.510183 [EMI DOE] emi_dcm 0
748 00:40:25.510247 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
749 00:40:25.510298 ==
750 00:40:25.510348 Dram Type= 6, Freq= 0, CH_0, rank 0
751 00:40:25.510397 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
752 00:40:25.510448 ==
753 00:40:25.510498 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
754 00:40:25.510548 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
755 00:40:25.510598 [CA 0] Center 37 (7~68) winsize 62
756 00:40:25.510647 [CA 1] Center 37 (7~68) winsize 62
757 00:40:25.510697 [CA 2] Center 35 (5~66) winsize 62
758 00:40:25.510747 [CA 3] Center 35 (4~66) winsize 63
759 00:40:25.510796 [CA 4] Center 34 (4~65) winsize 62
760 00:40:25.510845 [CA 5] Center 34 (4~64) winsize 61
761 00:40:25.510894
762 00:40:25.510943 [CmdBusTrainingLP45] Vref(ca) range 1: 32
763 00:40:25.510992
764 00:40:25.511040 [CATrainingPosCal] consider 1 rank data
765 00:40:25.511090 u2DelayCellTimex100 = 270/100 ps
766 00:40:25.511139 CA0 delay=37 (7~68),Diff = 3 PI (21 cell)
767 00:40:25.511189 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
768 00:40:25.511238 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
769 00:40:25.511287 CA3 delay=35 (4~66),Diff = 1 PI (7 cell)
770 00:40:25.511335 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
771 00:40:25.511385 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
772 00:40:25.511433
773 00:40:25.511482 CA PerBit enable=1, Macro0, CA PI delay=34
774 00:40:25.511531
775 00:40:25.511580 [CBTSetCACLKResult] CA Dly = 34
776 00:40:25.511630 CS Dly: 5 (0~36)
777 00:40:25.511678 ==
778 00:40:25.511728 Dram Type= 6, Freq= 0, CH_0, rank 1
779 00:40:25.511777 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
780 00:40:25.511827 ==
781 00:40:25.511876 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
782 00:40:25.511926 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
783 00:40:25.511974 [CA 0] Center 37 (7~68) winsize 62
784 00:40:25.512023 [CA 1] Center 37 (6~68) winsize 63
785 00:40:25.512072 [CA 2] Center 35 (5~66) winsize 62
786 00:40:25.512121 [CA 3] Center 35 (4~66) winsize 63
787 00:40:25.512170 [CA 4] Center 33 (3~64) winsize 62
788 00:40:25.512219 [CA 5] Center 34 (3~65) winsize 63
789 00:40:25.512268
790 00:40:25.512317 [CmdBusTrainingLP45] Vref(ca) range 1: 34
791 00:40:25.512366
792 00:40:25.512415 [CATrainingPosCal] consider 2 rank data
793 00:40:25.512464 u2DelayCellTimex100 = 270/100 ps
794 00:40:25.512514 CA0 delay=37 (7~68),Diff = 3 PI (21 cell)
795 00:40:25.512563 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
796 00:40:25.512612 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
797 00:40:25.512661 CA3 delay=35 (4~66),Diff = 1 PI (7 cell)
798 00:40:25.512737 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
799 00:40:25.512817 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
800 00:40:25.512897
801 00:40:25.512977 CA PerBit enable=1, Macro0, CA PI delay=34
802 00:40:25.513054
803 00:40:25.513130 [CBTSetCACLKResult] CA Dly = 34
804 00:40:25.513182 CS Dly: 5 (0~37)
805 00:40:25.513235
806 00:40:25.513304 ----->DramcWriteLeveling(PI) begin...
807 00:40:25.513358 ==
808 00:40:25.513410 Dram Type= 6, Freq= 0, CH_0, rank 0
809 00:40:25.513460 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
810 00:40:25.513510 ==
811 00:40:25.513560 Write leveling (Byte 0): 29 => 29
812 00:40:25.513610 Write leveling (Byte 1): 28 => 28
813 00:40:25.513672 DramcWriteLeveling(PI) end<-----
814 00:40:25.513720
815 00:40:25.513768 ==
816 00:40:25.513815 Dram Type= 6, Freq= 0, CH_0, rank 0
817 00:40:25.513863 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
818 00:40:25.513912 ==
819 00:40:25.513960 [Gating] SW mode calibration
820 00:40:25.514009 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
821 00:40:25.514057 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
822 00:40:25.514106 0 6 0 | B1->B0 | 3434 3333 | 0 0 | (0 0) (0 0)
823 00:40:25.514156 0 6 4 | B1->B0 | 2626 2727 | 0 0 | (0 0) (0 0)
824 00:40:25.514230 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 00:40:25.514294 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 00:40:25.514342 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 00:40:25.514390 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 00:40:25.514438 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
829 00:40:25.514486 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
830 00:40:25.514535 0 7 0 | B1->B0 | 2424 2a2a | 0 0 | (0 0) (0 0)
831 00:40:25.514583 0 7 4 | B1->B0 | 3939 4444 | 1 0 | (0 0) (0 0)
832 00:40:25.514631 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 00:40:25.514679 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 00:40:25.514727 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 00:40:25.514783 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
836 00:40:25.514834 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
837 00:40:25.514883 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
838 00:40:25.514931 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
839 00:40:25.514979 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 00:40:25.515026 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 00:40:25.515075 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 00:40:25.515122 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 00:40:25.515170 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 00:40:25.515218 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 00:40:25.515266 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 00:40:25.515314 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 00:40:25.515362 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 00:40:25.515410 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 00:40:25.515457 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 00:40:25.515506 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 00:40:25.515553 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
852 00:40:25.515819 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
853 00:40:25.515909 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
854 00:40:25.515990 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
855 00:40:25.516040 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
856 00:40:25.516090 Total UI for P1: 0, mck2ui 16
857 00:40:25.516140 best dqsien dly found for B0: ( 0, 10, 0)
858 00:40:25.516203 Total UI for P1: 0, mck2ui 16
859 00:40:25.516251 best dqsien dly found for B1: ( 0, 10, 0)
860 00:40:25.516317 best DQS0 dly(MCK, UI, PI) = (0, 10, 0)
861 00:40:25.516430 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
862 00:40:25.516489
863 00:40:25.516538 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 0)
864 00:40:25.516588 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
865 00:40:25.516636 [Gating] SW calibration Done
866 00:40:25.516684 ==
867 00:40:25.516733 Dram Type= 6, Freq= 0, CH_0, rank 0
868 00:40:25.516781 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
869 00:40:25.516829 ==
870 00:40:25.516878 RX Vref Scan: 0
871 00:40:25.516950
872 00:40:25.517045 RX Vref 0 -> 0, step: 1
873 00:40:25.517121
874 00:40:25.517170 RX Delay -130 -> 252, step: 16
875 00:40:25.517218 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
876 00:40:25.517266 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
877 00:40:25.517331 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
878 00:40:25.517383 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
879 00:40:25.517433 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
880 00:40:25.517481 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
881 00:40:25.517530 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
882 00:40:25.517578 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
883 00:40:25.517627 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
884 00:40:25.517675 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
885 00:40:25.517723 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
886 00:40:25.517771 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
887 00:40:25.517820 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
888 00:40:25.517868 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
889 00:40:25.517916 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
890 00:40:25.517964 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
891 00:40:25.518012 ==
892 00:40:25.518061 Dram Type= 6, Freq= 0, CH_0, rank 0
893 00:40:25.518109 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
894 00:40:25.518158 ==
895 00:40:25.518206 DQS Delay:
896 00:40:25.518315 DQS0 = 0, DQS1 = 0
897 00:40:25.518364 DQM Delay:
898 00:40:25.518411 DQM0 = 81, DQM1 = 74
899 00:40:25.518459 DQ Delay:
900 00:40:25.518507 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =77
901 00:40:25.518556 DQ4 =77, DQ5 =69, DQ6 =93, DQ7 =93
902 00:40:25.518604 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =69
903 00:40:25.518651 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
904 00:40:25.518699
905 00:40:25.518746
906 00:40:25.518793 ==
907 00:40:25.518841 Dram Type= 6, Freq= 0, CH_0, rank 0
908 00:40:25.518892 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
909 00:40:25.518940 ==
910 00:40:25.518988
911 00:40:25.519035
912 00:40:25.519082 TX Vref Scan disable
913 00:40:25.519130 == TX Byte 0 ==
914 00:40:25.519177 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
915 00:40:25.519226 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
916 00:40:25.519273 == TX Byte 1 ==
917 00:40:25.519322 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
918 00:40:25.519370 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
919 00:40:25.519417 ==
920 00:40:25.519465 Dram Type= 6, Freq= 0, CH_0, rank 0
921 00:40:25.519514 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
922 00:40:25.519585 ==
923 00:40:25.519637 TX Vref=22, minBit 2, minWin=27, winSum=444
924 00:40:25.519686 TX Vref=24, minBit 4, minWin=27, winSum=446
925 00:40:25.519737 TX Vref=26, minBit 2, minWin=27, winSum=447
926 00:40:25.519786 TX Vref=28, minBit 0, minWin=28, winSum=454
927 00:40:25.519835 TX Vref=30, minBit 1, minWin=28, winSum=456
928 00:40:25.519883 TX Vref=32, minBit 5, minWin=27, winSum=451
929 00:40:25.519931 [TxChooseVref] Worse bit 1, Min win 28, Win sum 456, Final Vref 30
930 00:40:25.519979
931 00:40:25.520027 Final TX Range 1 Vref 30
932 00:40:25.520075
933 00:40:25.520122 ==
934 00:40:25.520171 Dram Type= 6, Freq= 0, CH_0, rank 0
935 00:40:25.520219 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
936 00:40:25.520267 ==
937 00:40:25.520315
938 00:40:25.520362
939 00:40:25.520409 TX Vref Scan disable
940 00:40:25.520457 == TX Byte 0 ==
941 00:40:25.520505 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
942 00:40:25.520553 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
943 00:40:25.520601 == TX Byte 1 ==
944 00:40:25.520649 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
945 00:40:25.520754 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
946 00:40:25.520827
947 00:40:25.520877 [DATLAT]
948 00:40:25.520926 Freq=800, CH0 RK0
949 00:40:25.520975
950 00:40:25.521024 DATLAT Default: 0xa
951 00:40:25.521073 0, 0xFFFF, sum = 0
952 00:40:25.521122 1, 0xFFFF, sum = 0
953 00:40:25.521172 2, 0xFFFF, sum = 0
954 00:40:25.521221 3, 0xFFFF, sum = 0
955 00:40:25.521272 4, 0xFFFF, sum = 0
956 00:40:25.521321 5, 0xFFFF, sum = 0
957 00:40:25.521370 6, 0xFFFF, sum = 0
958 00:40:25.521418 7, 0xFFFF, sum = 0
959 00:40:25.521467 8, 0x0, sum = 1
960 00:40:25.521515 9, 0x0, sum = 2
961 00:40:25.521564 10, 0x0, sum = 3
962 00:40:25.521613 11, 0x0, sum = 4
963 00:40:25.521663 best_step = 9
964 00:40:25.521711
965 00:40:25.521758 ==
966 00:40:25.521806 Dram Type= 6, Freq= 0, CH_0, rank 0
967 00:40:25.521854 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
968 00:40:25.521903 ==
969 00:40:25.521951 RX Vref Scan: 1
970 00:40:25.521999
971 00:40:25.522047 Set Vref Range= 32 -> 127
972 00:40:25.522094
973 00:40:25.522142 RX Vref 32 -> 127, step: 1
974 00:40:25.522189
975 00:40:25.522295 RX Delay -111 -> 252, step: 8
976 00:40:25.522357
977 00:40:25.522406 Set Vref, RX VrefLevel [Byte0]: 32
978 00:40:25.522455 [Byte1]: 32
979 00:40:25.522503
980 00:40:25.522551 Set Vref, RX VrefLevel [Byte0]: 33
981 00:40:25.522599 [Byte1]: 33
982 00:40:25.522647
983 00:40:25.522719 Set Vref, RX VrefLevel [Byte0]: 34
984 00:40:25.522768 [Byte1]: 34
985 00:40:25.522863
986 00:40:25.522930 Set Vref, RX VrefLevel [Byte0]: 35
987 00:40:25.522978 [Byte1]: 35
988 00:40:25.523026
989 00:40:25.523072 Set Vref, RX VrefLevel [Byte0]: 36
990 00:40:25.523120 [Byte1]: 36
991 00:40:25.523168
992 00:40:25.523215 Set Vref, RX VrefLevel [Byte0]: 37
993 00:40:25.523263 [Byte1]: 37
994 00:40:25.523310
995 00:40:25.523357 Set Vref, RX VrefLevel [Byte0]: 38
996 00:40:25.523404 [Byte1]: 38
997 00:40:25.523453
998 00:40:25.523500 Set Vref, RX VrefLevel [Byte0]: 39
999 00:40:25.523548 [Byte1]: 39
1000 00:40:25.523595
1001 00:40:25.523834 Set Vref, RX VrefLevel [Byte0]: 40
1002 00:40:25.523891 [Byte1]: 40
1003 00:40:25.523955
1004 00:40:25.524047 Set Vref, RX VrefLevel [Byte0]: 41
1005 00:40:25.524097 [Byte1]: 41
1006 00:40:25.524146
1007 00:40:25.524195 Set Vref, RX VrefLevel [Byte0]: 42
1008 00:40:25.524243 [Byte1]: 42
1009 00:40:25.524292
1010 00:40:25.524340 Set Vref, RX VrefLevel [Byte0]: 43
1011 00:40:25.524388 [Byte1]: 43
1012 00:40:25.524437
1013 00:40:25.524484 Set Vref, RX VrefLevel [Byte0]: 44
1014 00:40:25.524532 [Byte1]: 44
1015 00:40:25.524581
1016 00:40:25.524629 Set Vref, RX VrefLevel [Byte0]: 45
1017 00:40:25.524677 [Byte1]: 45
1018 00:40:25.524726
1019 00:40:25.524774 Set Vref, RX VrefLevel [Byte0]: 46
1020 00:40:25.524822 [Byte1]: 46
1021 00:40:25.524870
1022 00:40:25.524919 Set Vref, RX VrefLevel [Byte0]: 47
1023 00:40:25.524969 [Byte1]: 47
1024 00:40:25.525017
1025 00:40:25.525065 Set Vref, RX VrefLevel [Byte0]: 48
1026 00:40:25.525113 [Byte1]: 48
1027 00:40:25.525161
1028 00:40:25.525209 Set Vref, RX VrefLevel [Byte0]: 49
1029 00:40:25.525257 [Byte1]: 49
1030 00:40:25.525304
1031 00:40:25.525351 Set Vref, RX VrefLevel [Byte0]: 50
1032 00:40:25.525400 [Byte1]: 50
1033 00:40:25.525447
1034 00:40:25.525495 Set Vref, RX VrefLevel [Byte0]: 51
1035 00:40:25.525543 [Byte1]: 51
1036 00:40:25.525590
1037 00:40:25.525638 Set Vref, RX VrefLevel [Byte0]: 52
1038 00:40:25.525686 [Byte1]: 52
1039 00:40:25.525733
1040 00:40:25.525781 Set Vref, RX VrefLevel [Byte0]: 53
1041 00:40:25.525829 [Byte1]: 53
1042 00:40:25.525876
1043 00:40:25.525923 Set Vref, RX VrefLevel [Byte0]: 54
1044 00:40:25.525971 [Byte1]: 54
1045 00:40:25.526019
1046 00:40:25.526076 Set Vref, RX VrefLevel [Byte0]: 55
1047 00:40:25.526160 [Byte1]: 55
1048 00:40:25.526272
1049 00:40:25.526323 Set Vref, RX VrefLevel [Byte0]: 56
1050 00:40:25.526372 [Byte1]: 56
1051 00:40:25.526421
1052 00:40:25.526499 Set Vref, RX VrefLevel [Byte0]: 57
1053 00:40:25.526563 [Byte1]: 57
1054 00:40:25.526612
1055 00:40:25.526661 Set Vref, RX VrefLevel [Byte0]: 58
1056 00:40:25.526740 [Byte1]: 58
1057 00:40:25.526790
1058 00:40:25.526838 Set Vref, RX VrefLevel [Byte0]: 59
1059 00:40:25.526902 [Byte1]: 59
1060 00:40:25.526966
1061 00:40:25.527044 Set Vref, RX VrefLevel [Byte0]: 60
1062 00:40:25.527107 [Byte1]: 60
1063 00:40:25.527155
1064 00:40:25.527246 Set Vref, RX VrefLevel [Byte0]: 61
1065 00:40:25.527295 [Byte1]: 61
1066 00:40:25.527344
1067 00:40:25.527393 Set Vref, RX VrefLevel [Byte0]: 62
1068 00:40:25.527442 [Byte1]: 62
1069 00:40:25.527491
1070 00:40:25.527539 Set Vref, RX VrefLevel [Byte0]: 63
1071 00:40:25.527591 [Byte1]: 63
1072 00:40:25.527651
1073 00:40:25.527700 Set Vref, RX VrefLevel [Byte0]: 64
1074 00:40:25.527751 [Byte1]: 64
1075 00:40:25.527800
1076 00:40:25.527863 Set Vref, RX VrefLevel [Byte0]: 65
1077 00:40:25.527911 [Byte1]: 65
1078 00:40:25.527959
1079 00:40:25.528007 Set Vref, RX VrefLevel [Byte0]: 66
1080 00:40:25.528055 [Byte1]: 66
1081 00:40:25.528102
1082 00:40:25.528150 Set Vref, RX VrefLevel [Byte0]: 67
1083 00:40:25.528198 [Byte1]: 67
1084 00:40:25.528246
1085 00:40:25.528295 Set Vref, RX VrefLevel [Byte0]: 68
1086 00:40:25.528343 [Byte1]: 68
1087 00:40:25.528391
1088 00:40:25.528439 Set Vref, RX VrefLevel [Byte0]: 69
1089 00:40:25.528487 [Byte1]: 69
1090 00:40:25.528535
1091 00:40:25.528583 Set Vref, RX VrefLevel [Byte0]: 70
1092 00:40:25.528632 [Byte1]: 70
1093 00:40:25.528680
1094 00:40:25.528728 Set Vref, RX VrefLevel [Byte0]: 71
1095 00:40:25.528777 [Byte1]: 71
1096 00:40:25.528825
1097 00:40:25.528873 Set Vref, RX VrefLevel [Byte0]: 72
1098 00:40:25.528922 [Byte1]: 72
1099 00:40:25.528970
1100 00:40:25.529017 Final RX Vref Byte 0 = 54 to rank0
1101 00:40:25.529065 Final RX Vref Byte 1 = 55 to rank0
1102 00:40:25.529114 Final RX Vref Byte 0 = 54 to rank1
1103 00:40:25.529162 Final RX Vref Byte 1 = 55 to rank1==
1104 00:40:25.529211 Dram Type= 6, Freq= 0, CH_0, rank 0
1105 00:40:25.529260 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1106 00:40:25.529309 ==
1107 00:40:25.529357 DQS Delay:
1108 00:40:25.529405 DQS0 = 0, DQS1 = 0
1109 00:40:25.529454 DQM Delay:
1110 00:40:25.529502 DQM0 = 83, DQM1 = 73
1111 00:40:25.529550 DQ Delay:
1112 00:40:25.529598 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1113 00:40:25.529646 DQ4 =88, DQ5 =72, DQ6 =92, DQ7 =92
1114 00:40:25.529694 DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =64
1115 00:40:25.529742 DQ12 =80, DQ13 =76, DQ14 =84, DQ15 =84
1116 00:40:25.529790
1117 00:40:25.529855
1118 00:40:25.529908 [DQSOSCAuto] RK0, (LSB)MR18= 0x4141, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
1119 00:40:25.529958 CH0 RK0: MR19=606, MR18=4141
1120 00:40:25.530007 CH0_RK0: MR19=0x606, MR18=0x4141, DQSOSC=393, MR23=63, INC=95, DEC=63
1121 00:40:25.530056
1122 00:40:25.530104 ----->DramcWriteLeveling(PI) begin...
1123 00:40:25.530154 ==
1124 00:40:25.530203 Dram Type= 6, Freq= 0, CH_0, rank 1
1125 00:40:25.530296 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1126 00:40:25.530346 ==
1127 00:40:25.530395 Write leveling (Byte 0): 32 => 32
1128 00:40:25.530443 Write leveling (Byte 1): 28 => 28
1129 00:40:25.530491 DramcWriteLeveling(PI) end<-----
1130 00:40:25.530539
1131 00:40:25.530587 ==
1132 00:40:25.530636 Dram Type= 6, Freq= 0, CH_0, rank 1
1133 00:40:25.530684 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1134 00:40:25.530733 ==
1135 00:40:25.530781 [Gating] SW mode calibration
1136 00:40:25.530829 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1137 00:40:25.530878 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1138 00:40:25.530927 0 6 0 | B1->B0 | 3232 3030 | 0 0 | (0 1) (0 0)
1139 00:40:25.530975 0 6 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1140 00:40:25.531024 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1141 00:40:25.531072 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1142 00:40:25.531120 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1143 00:40:25.531168 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1144 00:40:25.531216 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1145 00:40:25.531265 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1146 00:40:25.531506 0 7 0 | B1->B0 | 2e2e 3333 | 0 1 | (1 1) (0 0)
1147 00:40:25.531561 0 7 4 | B1->B0 | 4343 4646 | 1 0 | (0 0) (0 0)
1148 00:40:25.531611 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1149 00:40:25.531660 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1150 00:40:25.531708 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1151 00:40:25.531757 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1152 00:40:25.531805 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1153 00:40:25.531854 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1154 00:40:25.531901 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1155 00:40:25.531950 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1156 00:40:25.531998 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1157 00:40:25.532047 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1158 00:40:25.532095 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1159 00:40:25.532143 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1160 00:40:25.532191 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1161 00:40:25.532240 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1162 00:40:25.532287 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1163 00:40:25.532336 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1164 00:40:25.532384 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1165 00:40:25.532433 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1166 00:40:25.532481 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1167 00:40:25.532530 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1168 00:40:25.532578 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1169 00:40:25.532626 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1170 00:40:25.532674 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1171 00:40:25.532722 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1172 00:40:25.532770 Total UI for P1: 0, mck2ui 16
1173 00:40:25.532819 best dqsien dly found for B0: ( 0, 10, 0)
1174 00:40:25.532868 Total UI for P1: 0, mck2ui 16
1175 00:40:25.532917 best dqsien dly found for B1: ( 0, 10, 0)
1176 00:40:25.532988 best DQS0 dly(MCK, UI, PI) = (0, 10, 0)
1177 00:40:25.533039 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
1178 00:40:25.533088
1179 00:40:25.533136 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 0)
1180 00:40:25.533185 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
1181 00:40:25.533234 [Gating] SW calibration Done
1182 00:40:25.533282 ==
1183 00:40:25.533330 Dram Type= 6, Freq= 0, CH_0, rank 1
1184 00:40:25.533379 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1185 00:40:25.533428 ==
1186 00:40:25.533477 RX Vref Scan: 0
1187 00:40:25.533525
1188 00:40:25.533573 RX Vref 0 -> 0, step: 1
1189 00:40:25.533638
1190 00:40:25.533700 RX Delay -130 -> 252, step: 16
1191 00:40:25.533749 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1192 00:40:25.533798 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1193 00:40:25.533847 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
1194 00:40:25.533895 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1195 00:40:25.533943 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1196 00:40:25.533991 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1197 00:40:25.534039 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1198 00:40:25.534086 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1199 00:40:25.534134 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1200 00:40:25.534182 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1201 00:40:25.534291 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1202 00:40:25.534340 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1203 00:40:25.534389 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1204 00:40:25.534437 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1205 00:40:25.534486 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1206 00:40:25.534534 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1207 00:40:25.534582 ==
1208 00:40:25.534630 Dram Type= 6, Freq= 0, CH_0, rank 1
1209 00:40:25.534679 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1210 00:40:25.534728 ==
1211 00:40:25.534775 DQS Delay:
1212 00:40:25.534823 DQS0 = 0, DQS1 = 0
1213 00:40:25.534871 DQM Delay:
1214 00:40:25.534919 DQM0 = 82, DQM1 = 73
1215 00:40:25.534967 DQ Delay:
1216 00:40:25.535014 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =77
1217 00:40:25.535062 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
1218 00:40:25.535110 DQ8 =53, DQ9 =53, DQ10 =69, DQ11 =69
1219 00:40:25.535158 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1220 00:40:25.535207
1221 00:40:25.535254
1222 00:40:25.535302 ==
1223 00:40:25.535349 Dram Type= 6, Freq= 0, CH_0, rank 1
1224 00:40:25.535398 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1225 00:40:25.535446 ==
1226 00:40:25.535494
1227 00:40:25.535541
1228 00:40:25.535589 TX Vref Scan disable
1229 00:40:25.535637 == TX Byte 0 ==
1230 00:40:25.535685 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1231 00:40:25.535734 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1232 00:40:25.535782 == TX Byte 1 ==
1233 00:40:25.535830 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1234 00:40:25.535878 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1235 00:40:25.535925 ==
1236 00:40:25.535973 Dram Type= 6, Freq= 0, CH_0, rank 1
1237 00:40:25.536021 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1238 00:40:25.536069 ==
1239 00:40:25.536117 TX Vref=22, minBit 0, minWin=28, winSum=449
1240 00:40:25.536165 TX Vref=24, minBit 0, minWin=28, winSum=450
1241 00:40:25.536214 TX Vref=26, minBit 1, minWin=28, winSum=454
1242 00:40:25.536263 TX Vref=28, minBit 4, minWin=28, winSum=459
1243 00:40:25.536310 TX Vref=30, minBit 5, minWin=28, winSum=460
1244 00:40:25.536358 TX Vref=32, minBit 1, minWin=28, winSum=456
1245 00:40:25.536428 [TxChooseVref] Worse bit 5, Min win 28, Win sum 460, Final Vref 30
1246 00:40:25.536480
1247 00:40:25.536528 Final TX Range 1 Vref 30
1248 00:40:25.536576
1249 00:40:25.536624 ==
1250 00:40:25.536672 Dram Type= 6, Freq= 0, CH_0, rank 1
1251 00:40:25.536720 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1252 00:40:25.536769 ==
1253 00:40:25.536817
1254 00:40:25.536864
1255 00:40:25.536910 TX Vref Scan disable
1256 00:40:25.536958 == TX Byte 0 ==
1257 00:40:25.537007 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1258 00:40:25.537055 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1259 00:40:25.537104 == TX Byte 1 ==
1260 00:40:25.537151 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1261 00:40:25.537201 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1262 00:40:25.537249
1263 00:40:25.537311 [DATLAT]
1264 00:40:25.537392 Freq=800, CH0 RK1
1265 00:40:25.537472
1266 00:40:25.537752 DATLAT Default: 0x9
1267 00:40:25.537837 0, 0xFFFF, sum = 0
1268 00:40:25.537921 1, 0xFFFF, sum = 0
1269 00:40:25.538003 2, 0xFFFF, sum = 0
1270 00:40:25.538085 3, 0xFFFF, sum = 0
1271 00:40:25.538166 4, 0xFFFF, sum = 0
1272 00:40:25.538290 5, 0xFFFF, sum = 0
1273 00:40:25.538372 6, 0xFFFF, sum = 0
1274 00:40:25.538451 7, 0xFFFF, sum = 0
1275 00:40:25.538529 8, 0x0, sum = 1
1276 00:40:25.538607 9, 0x0, sum = 2
1277 00:40:25.538685 10, 0x0, sum = 3
1278 00:40:25.538764 11, 0x0, sum = 4
1279 00:40:25.538842 best_step = 9
1280 00:40:25.538917
1281 00:40:25.538993 ==
1282 00:40:25.539069 Dram Type= 6, Freq= 0, CH_0, rank 1
1283 00:40:25.539147 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1284 00:40:25.539223 ==
1285 00:40:25.539299 RX Vref Scan: 0
1286 00:40:25.539375
1287 00:40:25.539451 RX Vref 0 -> 0, step: 1
1288 00:40:25.539526
1289 00:40:25.539602 RX Delay -111 -> 252, step: 8
1290 00:40:25.539689 iDelay=217, Bit 0, Center 84 (-31 ~ 200) 232
1291 00:40:25.539769 iDelay=217, Bit 1, Center 88 (-31 ~ 208) 240
1292 00:40:25.539847 iDelay=217, Bit 2, Center 84 (-31 ~ 200) 232
1293 00:40:25.539924 iDelay=217, Bit 3, Center 80 (-39 ~ 200) 240
1294 00:40:25.540001 iDelay=217, Bit 4, Center 88 (-31 ~ 208) 240
1295 00:40:25.540077 iDelay=217, Bit 5, Center 76 (-39 ~ 192) 232
1296 00:40:25.540183 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1297 00:40:25.540261 iDelay=217, Bit 7, Center 96 (-23 ~ 216) 240
1298 00:40:25.540338 iDelay=217, Bit 8, Center 64 (-47 ~ 176) 224
1299 00:40:25.540415 iDelay=217, Bit 9, Center 60 (-55 ~ 176) 232
1300 00:40:25.540492 iDelay=217, Bit 10, Center 76 (-39 ~ 192) 232
1301 00:40:25.540569 iDelay=217, Bit 11, Center 64 (-47 ~ 176) 224
1302 00:40:25.540645 iDelay=217, Bit 12, Center 80 (-31 ~ 192) 224
1303 00:40:25.540723 iDelay=217, Bit 13, Center 80 (-39 ~ 200) 240
1304 00:40:25.540800 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
1305 00:40:25.540876 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
1306 00:40:25.540952 ==
1307 00:40:25.541029 Dram Type= 6, Freq= 0, CH_0, rank 1
1308 00:40:25.541106 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1309 00:40:25.541183 ==
1310 00:40:25.541259 DQS Delay:
1311 00:40:25.541334 DQS0 = 0, DQS1 = 0
1312 00:40:25.541426 DQM Delay:
1313 00:40:25.541516 DQM0 = 86, DQM1 = 74
1314 00:40:25.541592 DQ Delay:
1315 00:40:25.541668 DQ0 =84, DQ1 =88, DQ2 =84, DQ3 =80
1316 00:40:25.541745 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =96
1317 00:40:25.541821 DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =64
1318 00:40:25.541897 DQ12 =80, DQ13 =80, DQ14 =84, DQ15 =84
1319 00:40:25.541972
1320 00:40:25.542048
1321 00:40:25.542125 [DQSOSCAuto] RK1, (LSB)MR18= 0x4b4b, (MSB)MR19= 0x606, tDQSOscB0 = 391 ps tDQSOscB1 = 391 ps
1322 00:40:25.542202 CH0 RK1: MR19=606, MR18=4B4B
1323 00:40:25.542318 CH0_RK1: MR19=0x606, MR18=0x4B4B, DQSOSC=391, MR23=63, INC=96, DEC=64
1324 00:40:25.542395 [RxdqsGatingPostProcess] freq 800
1325 00:40:25.542472 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1326 00:40:25.542549 Pre-setting of DQS Precalculation
1327 00:40:25.542625 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1328 00:40:25.542701 ==
1329 00:40:25.542778 Dram Type= 6, Freq= 0, CH_1, rank 0
1330 00:40:25.542855 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1331 00:40:25.542906 ==
1332 00:40:25.542955 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1333 00:40:25.543004 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1334 00:40:25.543053 [CA 0] Center 37 (6~68) winsize 63
1335 00:40:25.543101 [CA 1] Center 37 (6~68) winsize 63
1336 00:40:25.543149 [CA 2] Center 34 (4~65) winsize 62
1337 00:40:25.543197 [CA 3] Center 34 (4~65) winsize 62
1338 00:40:25.543246 [CA 4] Center 33 (3~64) winsize 62
1339 00:40:25.543310 [CA 5] Center 33 (3~64) winsize 62
1340 00:40:25.543373
1341 00:40:25.543420 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1342 00:40:25.543468
1343 00:40:25.543515 [CATrainingPosCal] consider 1 rank data
1344 00:40:25.543563 u2DelayCellTimex100 = 270/100 ps
1345 00:40:25.543641 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
1346 00:40:25.543688 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1347 00:40:25.543736 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1348 00:40:25.543784 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1349 00:40:25.543832 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1350 00:40:25.543879 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1351 00:40:25.543927
1352 00:40:25.543975 CA PerBit enable=1, Macro0, CA PI delay=33
1353 00:40:25.544023
1354 00:40:25.544070 [CBTSetCACLKResult] CA Dly = 33
1355 00:40:25.544118 CS Dly: 4 (0~35)
1356 00:40:25.544165 ==
1357 00:40:25.544213 Dram Type= 6, Freq= 0, CH_1, rank 1
1358 00:40:25.544262 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1359 00:40:25.544310 ==
1360 00:40:25.544358 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1361 00:40:25.544406 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1362 00:40:25.544454 [CA 0] Center 37 (6~68) winsize 63
1363 00:40:25.544502 [CA 1] Center 37 (6~68) winsize 63
1364 00:40:25.544548 [CA 2] Center 34 (4~65) winsize 62
1365 00:40:25.544595 [CA 3] Center 34 (4~65) winsize 62
1366 00:40:25.544642 [CA 4] Center 33 (3~64) winsize 62
1367 00:40:25.544690 [CA 5] Center 33 (3~64) winsize 62
1368 00:40:25.544737
1369 00:40:25.544785 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1370 00:40:25.544834
1371 00:40:25.544881 [CATrainingPosCal] consider 2 rank data
1372 00:40:25.544929 u2DelayCellTimex100 = 270/100 ps
1373 00:40:25.544976 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
1374 00:40:25.545024 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1375 00:40:25.545072 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1376 00:40:25.545120 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1377 00:40:25.545168 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1378 00:40:25.545215 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1379 00:40:25.545262
1380 00:40:25.545309 CA PerBit enable=1, Macro0, CA PI delay=33
1381 00:40:25.545387
1382 00:40:25.545435 [CBTSetCACLKResult] CA Dly = 33
1383 00:40:25.545482 CS Dly: 4 (0~36)
1384 00:40:25.545529
1385 00:40:25.545576 ----->DramcWriteLeveling(PI) begin...
1386 00:40:25.545625 ==
1387 00:40:25.545672 Dram Type= 6, Freq= 0, CH_1, rank 0
1388 00:40:25.545720 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1389 00:40:25.545768 ==
1390 00:40:25.545816 Write leveling (Byte 0): 27 => 27
1391 00:40:25.545863 Write leveling (Byte 1): 21 => 21
1392 00:40:25.545910 DramcWriteLeveling(PI) end<-----
1393 00:40:25.545957
1394 00:40:25.546003 ==
1395 00:40:25.546050 Dram Type= 6, Freq= 0, CH_1, rank 0
1396 00:40:25.546099 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1397 00:40:25.546147 ==
1398 00:40:25.546194 [Gating] SW mode calibration
1399 00:40:25.546458 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1400 00:40:25.546513 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1401 00:40:25.546563 0 6 0 | B1->B0 | 2f2f 2828 | 1 0 | (1 0) (0 0)
1402 00:40:25.546611 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1403 00:40:25.546745 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1404 00:40:25.546812 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1405 00:40:25.546862 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1406 00:40:25.546911 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1407 00:40:25.546975 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1408 00:40:25.547022 0 6 28 | B1->B0 | 2424 2e2e | 1 1 | (0 0) (0 0)
1409 00:40:25.547070 0 7 0 | B1->B0 | 2e2e 3a3a | 0 0 | (0 0) (0 0)
1410 00:40:25.547118 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1411 00:40:25.547166 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1412 00:40:25.547214 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1413 00:40:25.547261 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1414 00:40:25.547309 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1415 00:40:25.547356 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1416 00:40:25.547404 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1417 00:40:25.547451 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1418 00:40:25.547498 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1419 00:40:25.547545 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1420 00:40:25.547593 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1421 00:40:25.547640 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1422 00:40:25.547688 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1423 00:40:25.547735 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1424 00:40:25.547783 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1425 00:40:25.547831 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1426 00:40:25.547879 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1427 00:40:25.547926 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1428 00:40:25.547974 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1429 00:40:25.548023 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1430 00:40:25.548071 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1431 00:40:25.548119 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1432 00:40:25.548167 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1433 00:40:25.548215 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1434 00:40:25.548262 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1435 00:40:25.548309 Total UI for P1: 0, mck2ui 16
1436 00:40:25.548357 best dqsien dly found for B0: ( 0, 9, 30)
1437 00:40:25.548405 Total UI for P1: 0, mck2ui 16
1438 00:40:25.548454 best dqsien dly found for B1: ( 0, 10, 0)
1439 00:40:25.548505 best DQS0 dly(MCK, UI, PI) = (0, 9, 30)
1440 00:40:25.548553 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
1441 00:40:25.548600
1442 00:40:25.548648 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 30)
1443 00:40:25.548696 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
1444 00:40:25.548744 [Gating] SW calibration Done
1445 00:40:25.548792 ==
1446 00:40:25.548840 Dram Type= 6, Freq= 0, CH_1, rank 0
1447 00:40:25.548888 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1448 00:40:25.548936 ==
1449 00:40:25.548983 RX Vref Scan: 0
1450 00:40:25.549029
1451 00:40:25.549076 RX Vref 0 -> 0, step: 1
1452 00:40:25.549124
1453 00:40:25.549171 RX Delay -130 -> 252, step: 16
1454 00:40:25.549218 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1455 00:40:25.549266 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1456 00:40:25.549314 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1457 00:40:25.549361 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1458 00:40:25.549409 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1459 00:40:25.549457 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1460 00:40:25.549536 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1461 00:40:25.549584 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1462 00:40:25.549632 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1463 00:40:25.549678 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1464 00:40:25.549726 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1465 00:40:25.549773 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1466 00:40:25.549821 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1467 00:40:25.549869 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1468 00:40:25.549916 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1469 00:40:25.549963 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1470 00:40:25.550010 ==
1471 00:40:25.550093 Dram Type= 6, Freq= 0, CH_1, rank 0
1472 00:40:25.550180 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1473 00:40:25.550287 ==
1474 00:40:25.550338 DQS Delay:
1475 00:40:25.550386 DQS0 = 0, DQS1 = 0
1476 00:40:25.550433 DQM Delay:
1477 00:40:25.550481 DQM0 = 81, DQM1 = 73
1478 00:40:25.550528 DQ Delay:
1479 00:40:25.550576 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1480 00:40:25.550624 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1481 00:40:25.550672 DQ8 =53, DQ9 =61, DQ10 =77, DQ11 =69
1482 00:40:25.550721 DQ12 =77, DQ13 =85, DQ14 =77, DQ15 =85
1483 00:40:25.550769
1484 00:40:25.550817
1485 00:40:25.550864 ==
1486 00:40:25.550911 Dram Type= 6, Freq= 0, CH_1, rank 0
1487 00:40:25.550959 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1488 00:40:25.551007 ==
1489 00:40:25.551054
1490 00:40:25.551101
1491 00:40:25.551147 TX Vref Scan disable
1492 00:40:25.551194 == TX Byte 0 ==
1493 00:40:25.551241 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1494 00:40:25.551305 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1495 00:40:25.551353 == TX Byte 1 ==
1496 00:40:25.551402 Update DQ dly =571 (2 ,1, 27) DQ OEN =(1 ,6)
1497 00:40:25.551450 Update DQM dly =571 (2 ,1, 27) DQM OEN =(1 ,6)
1498 00:40:25.551499 ==
1499 00:40:25.551548 Dram Type= 6, Freq= 0, CH_1, rank 0
1500 00:40:25.551597 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1501 00:40:25.551646 ==
1502 00:40:25.551694 TX Vref=22, minBit 0, minWin=27, winSum=446
1503 00:40:25.551743 TX Vref=24, minBit 0, minWin=28, winSum=451
1504 00:40:25.551792 TX Vref=26, minBit 0, minWin=28, winSum=455
1505 00:40:25.551841 TX Vref=28, minBit 3, minWin=28, winSum=458
1506 00:40:25.552087 TX Vref=30, minBit 0, minWin=28, winSum=459
1507 00:40:25.552147 TX Vref=32, minBit 0, minWin=28, winSum=459
1508 00:40:25.552197 [TxChooseVref] Worse bit 0, Min win 28, Win sum 459, Final Vref 30
1509 00:40:25.552247
1510 00:40:25.552297 Final TX Range 1 Vref 30
1511 00:40:25.552346
1512 00:40:25.552395 ==
1513 00:40:25.552444 Dram Type= 6, Freq= 0, CH_1, rank 0
1514 00:40:25.552494 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1515 00:40:25.552543 ==
1516 00:40:25.552592
1517 00:40:25.552640
1518 00:40:25.552687 TX Vref Scan disable
1519 00:40:25.552736 == TX Byte 0 ==
1520 00:40:25.552784 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1521 00:40:25.552834 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1522 00:40:25.552883 == TX Byte 1 ==
1523 00:40:25.552931 Update DQ dly =571 (2 ,1, 27) DQ OEN =(1 ,6)
1524 00:40:25.552981 Update DQM dly =571 (2 ,1, 27) DQM OEN =(1 ,6)
1525 00:40:25.553030
1526 00:40:25.553107 [DATLAT]
1527 00:40:25.553159 Freq=800, CH1 RK0
1528 00:40:25.553208
1529 00:40:25.553257 DATLAT Default: 0xa
1530 00:40:25.553306 0, 0xFFFF, sum = 0
1531 00:40:25.553357 1, 0xFFFF, sum = 0
1532 00:40:25.553406 2, 0xFFFF, sum = 0
1533 00:40:25.553455 3, 0xFFFF, sum = 0
1534 00:40:25.553505 4, 0xFFFF, sum = 0
1535 00:40:25.553554 5, 0xFFFF, sum = 0
1536 00:40:25.553604 6, 0xFFFF, sum = 0
1537 00:40:25.553653 7, 0xFFFF, sum = 0
1538 00:40:25.553702 8, 0x0, sum = 1
1539 00:40:25.553752 9, 0x0, sum = 2
1540 00:40:25.553801 10, 0x0, sum = 3
1541 00:40:25.553850 11, 0x0, sum = 4
1542 00:40:25.553899 best_step = 9
1543 00:40:25.553947
1544 00:40:25.553995 ==
1545 00:40:25.554043 Dram Type= 6, Freq= 0, CH_1, rank 0
1546 00:40:25.554093 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1547 00:40:25.554143 ==
1548 00:40:25.554191 RX Vref Scan: 1
1549 00:40:25.554254
1550 00:40:25.554304 Set Vref Range= 32 -> 127
1551 00:40:25.554352
1552 00:40:25.554400 RX Vref 32 -> 127, step: 1
1553 00:40:25.554448
1554 00:40:25.554495 RX Delay -111 -> 252, step: 8
1555 00:40:25.554543
1556 00:40:25.554591 Set Vref, RX VrefLevel [Byte0]: 32
1557 00:40:25.554640 [Byte1]: 32
1558 00:40:25.554689
1559 00:40:25.554737 Set Vref, RX VrefLevel [Byte0]: 33
1560 00:40:25.554785 [Byte1]: 33
1561 00:40:25.554834
1562 00:40:25.554882 Set Vref, RX VrefLevel [Byte0]: 34
1563 00:40:25.554931 [Byte1]: 34
1564 00:40:25.554980
1565 00:40:25.555028 Set Vref, RX VrefLevel [Byte0]: 35
1566 00:40:25.555077 [Byte1]: 35
1567 00:40:25.555125
1568 00:40:25.555174 Set Vref, RX VrefLevel [Byte0]: 36
1569 00:40:25.555224 [Byte1]: 36
1570 00:40:25.555273
1571 00:40:25.555321 Set Vref, RX VrefLevel [Byte0]: 37
1572 00:40:25.555370 [Byte1]: 37
1573 00:40:25.555418
1574 00:40:25.555466 Set Vref, RX VrefLevel [Byte0]: 38
1575 00:40:25.555514 [Byte1]: 38
1576 00:40:25.555561
1577 00:40:25.555609 Set Vref, RX VrefLevel [Byte0]: 39
1578 00:40:25.555658 [Byte1]: 39
1579 00:40:25.555706
1580 00:40:25.555754 Set Vref, RX VrefLevel [Byte0]: 40
1581 00:40:25.555803 [Byte1]: 40
1582 00:40:25.555851
1583 00:40:25.555899 Set Vref, RX VrefLevel [Byte0]: 41
1584 00:40:25.555948 [Byte1]: 41
1585 00:40:25.555996
1586 00:40:25.556043 Set Vref, RX VrefLevel [Byte0]: 42
1587 00:40:25.556092 [Byte1]: 42
1588 00:40:25.556165
1589 00:40:25.556217 Set Vref, RX VrefLevel [Byte0]: 43
1590 00:40:25.556267 [Byte1]: 43
1591 00:40:25.556316
1592 00:40:25.556365 Set Vref, RX VrefLevel [Byte0]: 44
1593 00:40:25.556414 [Byte1]: 44
1594 00:40:25.556463
1595 00:40:25.556511 Set Vref, RX VrefLevel [Byte0]: 45
1596 00:40:25.556560 [Byte1]: 45
1597 00:40:25.556609
1598 00:40:25.556658 Set Vref, RX VrefLevel [Byte0]: 46
1599 00:40:25.556706 [Byte1]: 46
1600 00:40:25.556755
1601 00:40:25.556802 Set Vref, RX VrefLevel [Byte0]: 47
1602 00:40:25.556851 [Byte1]: 47
1603 00:40:25.556900
1604 00:40:25.556948 Set Vref, RX VrefLevel [Byte0]: 48
1605 00:40:25.556996 [Byte1]: 48
1606 00:40:25.557044
1607 00:40:25.557093 Set Vref, RX VrefLevel [Byte0]: 49
1608 00:40:25.557143 [Byte1]: 49
1609 00:40:25.557191
1610 00:40:25.557239 Set Vref, RX VrefLevel [Byte0]: 50
1611 00:40:25.557289 [Byte1]: 50
1612 00:40:25.557337
1613 00:40:25.557386 Set Vref, RX VrefLevel [Byte0]: 51
1614 00:40:25.557434 [Byte1]: 51
1615 00:40:25.557482
1616 00:40:25.557530 Set Vref, RX VrefLevel [Byte0]: 52
1617 00:40:25.557578 [Byte1]: 52
1618 00:40:25.557627
1619 00:40:25.557675 Set Vref, RX VrefLevel [Byte0]: 53
1620 00:40:25.557724 [Byte1]: 53
1621 00:40:25.557772
1622 00:40:25.557820 Set Vref, RX VrefLevel [Byte0]: 54
1623 00:40:25.557891 [Byte1]: 54
1624 00:40:25.557965
1625 00:40:25.558017 Set Vref, RX VrefLevel [Byte0]: 55
1626 00:40:25.558066 [Byte1]: 55
1627 00:40:25.558115
1628 00:40:25.558164 Set Vref, RX VrefLevel [Byte0]: 56
1629 00:40:25.558221 [Byte1]: 56
1630 00:40:25.558273
1631 00:40:25.558322 Set Vref, RX VrefLevel [Byte0]: 57
1632 00:40:25.558370 [Byte1]: 57
1633 00:40:25.558419
1634 00:40:25.558468 Set Vref, RX VrefLevel [Byte0]: 58
1635 00:40:25.558516 [Byte1]: 58
1636 00:40:25.558564
1637 00:40:25.558612 Set Vref, RX VrefLevel [Byte0]: 59
1638 00:40:25.558660 [Byte1]: 59
1639 00:40:25.558708
1640 00:40:25.558756 Set Vref, RX VrefLevel [Byte0]: 60
1641 00:40:25.558804 [Byte1]: 60
1642 00:40:25.558852
1643 00:40:25.558900 Set Vref, RX VrefLevel [Byte0]: 61
1644 00:40:25.558948 [Byte1]: 61
1645 00:40:25.558996
1646 00:40:25.559044 Set Vref, RX VrefLevel [Byte0]: 62
1647 00:40:25.559092 [Byte1]: 62
1648 00:40:25.559141
1649 00:40:25.559189 Set Vref, RX VrefLevel [Byte0]: 63
1650 00:40:25.559238 [Byte1]: 63
1651 00:40:25.559286
1652 00:40:25.559335 Set Vref, RX VrefLevel [Byte0]: 64
1653 00:40:25.559384 [Byte1]: 64
1654 00:40:25.559432
1655 00:40:25.559479 Set Vref, RX VrefLevel [Byte0]: 65
1656 00:40:25.559528 [Byte1]: 65
1657 00:40:25.559575
1658 00:40:25.559623 Set Vref, RX VrefLevel [Byte0]: 66
1659 00:40:25.559672 [Byte1]: 66
1660 00:40:25.559720
1661 00:40:25.559767 Set Vref, RX VrefLevel [Byte0]: 67
1662 00:40:25.559815 [Byte1]: 67
1663 00:40:25.559887
1664 00:40:25.559939 Set Vref, RX VrefLevel [Byte0]: 68
1665 00:40:25.559989 [Byte1]: 68
1666 00:40:25.560037
1667 00:40:25.560085 Set Vref, RX VrefLevel [Byte0]: 69
1668 00:40:25.560133 [Byte1]: 69
1669 00:40:25.560182
1670 00:40:25.560229 Set Vref, RX VrefLevel [Byte0]: 70
1671 00:40:25.560277 [Byte1]: 70
1672 00:40:25.560325
1673 00:40:25.560373 Set Vref, RX VrefLevel [Byte0]: 71
1674 00:40:25.560422 [Byte1]: 71
1675 00:40:25.560471
1676 00:40:25.560715 Set Vref, RX VrefLevel [Byte0]: 72
1677 00:40:25.560771 [Byte1]: 72
1678 00:40:25.560820
1679 00:40:25.560869 Set Vref, RX VrefLevel [Byte0]: 73
1680 00:40:25.560917 [Byte1]: 73
1681 00:40:25.560966
1682 00:40:25.561015 Set Vref, RX VrefLevel [Byte0]: 74
1683 00:40:25.561063 [Byte1]: 74
1684 00:40:25.561112
1685 00:40:25.561160 Set Vref, RX VrefLevel [Byte0]: 75
1686 00:40:25.561208 [Byte1]: 75
1687 00:40:25.561257
1688 00:40:25.561305 Final RX Vref Byte 0 = 60 to rank0
1689 00:40:25.561354 Final RX Vref Byte 1 = 55 to rank0
1690 00:40:25.561403 Final RX Vref Byte 0 = 60 to rank1
1691 00:40:25.561451 Final RX Vref Byte 1 = 55 to rank1==
1692 00:40:25.561500 Dram Type= 6, Freq= 0, CH_1, rank 0
1693 00:40:25.561549 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1694 00:40:25.561597 ==
1695 00:40:25.561647 DQS Delay:
1696 00:40:25.561695 DQS0 = 0, DQS1 = 0
1697 00:40:25.561743 DQM Delay:
1698 00:40:25.561791 DQM0 = 81, DQM1 = 74
1699 00:40:25.561839 DQ Delay:
1700 00:40:25.561887 DQ0 =88, DQ1 =76, DQ2 =72, DQ3 =76
1701 00:40:25.561935 DQ4 =80, DQ5 =92, DQ6 =88, DQ7 =76
1702 00:40:25.561984 DQ8 =60, DQ9 =64, DQ10 =76, DQ11 =64
1703 00:40:25.562032 DQ12 =84, DQ13 =84, DQ14 =80, DQ15 =84
1704 00:40:25.562081
1705 00:40:25.562129
1706 00:40:25.562176 [DQSOSCAuto] RK0, (LSB)MR18= 0x5454, (MSB)MR19= 0x606, tDQSOscB0 = 388 ps tDQSOscB1 = 388 ps
1707 00:40:25.562235 CH1 RK0: MR19=606, MR18=5454
1708 00:40:25.562285 CH1_RK0: MR19=0x606, MR18=0x5454, DQSOSC=388, MR23=63, INC=98, DEC=65
1709 00:40:25.562334
1710 00:40:25.562382 ----->DramcWriteLeveling(PI) begin...
1711 00:40:25.562432 ==
1712 00:40:25.562482 Dram Type= 6, Freq= 0, CH_1, rank 1
1713 00:40:25.562531 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1714 00:40:25.562580 ==
1715 00:40:25.562629 Write leveling (Byte 0): 26 => 26
1716 00:40:25.562677 Write leveling (Byte 1): 26 => 26
1717 00:40:25.562726 DramcWriteLeveling(PI) end<-----
1718 00:40:25.562775
1719 00:40:25.562823 ==
1720 00:40:25.562876 Dram Type= 6, Freq= 0, CH_1, rank 1
1721 00:40:25.562938 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1722 00:40:25.563005 ==
1723 00:40:25.563055 [Gating] SW mode calibration
1724 00:40:25.563105 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1725 00:40:25.563155 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1726 00:40:25.563204 0 6 0 | B1->B0 | 2f2f 2323 | 0 0 | (1 1) (0 0)
1727 00:40:25.563253 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1728 00:40:25.563301 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1729 00:40:25.563350 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1730 00:40:25.563398 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1731 00:40:25.563446 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1732 00:40:25.563496 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1733 00:40:25.563544 0 6 28 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (1 1)
1734 00:40:25.563594 0 7 0 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
1735 00:40:25.563642 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1736 00:40:25.563691 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1737 00:40:25.563739 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1738 00:40:25.563788 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1739 00:40:25.563837 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1740 00:40:25.563885 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1741 00:40:25.563934 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1742 00:40:25.563983 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1743 00:40:25.564031 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1744 00:40:25.564079 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1745 00:40:25.564127 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1746 00:40:25.564176 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1747 00:40:25.564225 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1748 00:40:25.564273 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1749 00:40:25.564321 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1750 00:40:25.564370 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1751 00:40:25.564418 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1752 00:40:25.564466 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1753 00:40:25.564514 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1754 00:40:25.564563 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1755 00:40:25.564611 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1756 00:40:25.564660 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1757 00:40:25.564709 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1758 00:40:25.564757 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1759 00:40:25.564805 Total UI for P1: 0, mck2ui 16
1760 00:40:25.564854 best dqsien dly found for B0: ( 0, 9, 28)
1761 00:40:25.564902 Total UI for P1: 0, mck2ui 16
1762 00:40:25.564950 best dqsien dly found for B1: ( 0, 9, 30)
1763 00:40:25.564998 best DQS0 dly(MCK, UI, PI) = (0, 9, 28)
1764 00:40:25.565046 best DQS1 dly(MCK, UI, PI) = (0, 9, 30)
1765 00:40:25.565095
1766 00:40:25.565143 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 28)
1767 00:40:25.565192 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 30)
1768 00:40:25.565242 [Gating] SW calibration Done
1769 00:40:25.565291 ==
1770 00:40:25.565339 Dram Type= 6, Freq= 0, CH_1, rank 1
1771 00:40:25.565388 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1772 00:40:25.565437 ==
1773 00:40:25.565486 RX Vref Scan: 0
1774 00:40:25.565535
1775 00:40:25.565584 RX Vref 0 -> 0, step: 1
1776 00:40:25.565632
1777 00:40:25.565680 RX Delay -130 -> 252, step: 16
1778 00:40:25.565729 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1779 00:40:25.565778 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1780 00:40:25.565827 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1781 00:40:25.565875 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1782 00:40:25.565923 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1783 00:40:25.565971 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1784 00:40:25.566024 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1785 00:40:25.566092 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1786 00:40:25.566143 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1787 00:40:25.566383 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1788 00:40:25.566439 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1789 00:40:25.566490 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1790 00:40:25.566540 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1791 00:40:25.566589 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1792 00:40:25.566638 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1793 00:40:25.566687 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1794 00:40:25.566737 ==
1795 00:40:25.566786 Dram Type= 6, Freq= 0, CH_1, rank 1
1796 00:40:25.566835 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1797 00:40:25.566885 ==
1798 00:40:25.566933 DQS Delay:
1799 00:40:25.566981 DQS0 = 0, DQS1 = 0
1800 00:40:25.567029 DQM Delay:
1801 00:40:25.567078 DQM0 = 83, DQM1 = 73
1802 00:40:25.567126 DQ Delay:
1803 00:40:25.567175 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =85
1804 00:40:25.567224 DQ4 =85, DQ5 =93, DQ6 =85, DQ7 =77
1805 00:40:25.567271 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =61
1806 00:40:25.567320 DQ12 =85, DQ13 =85, DQ14 =77, DQ15 =85
1807 00:40:25.567369
1808 00:40:25.567418
1809 00:40:25.567466 ==
1810 00:40:25.567515 Dram Type= 6, Freq= 0, CH_1, rank 1
1811 00:40:25.567564 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1812 00:40:25.567612 ==
1813 00:40:25.567661
1814 00:40:25.567708
1815 00:40:25.567756 TX Vref Scan disable
1816 00:40:25.567805 == TX Byte 0 ==
1817 00:40:25.567853 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1818 00:40:25.567902 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1819 00:40:25.567950 == TX Byte 1 ==
1820 00:40:25.567999 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1821 00:40:25.568047 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1822 00:40:25.568095 ==
1823 00:40:25.568143 Dram Type= 6, Freq= 0, CH_1, rank 1
1824 00:40:25.568191 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1825 00:40:25.568240 ==
1826 00:40:25.568287 TX Vref=22, minBit 0, minWin=27, winSum=449
1827 00:40:25.568337 TX Vref=24, minBit 0, minWin=27, winSum=451
1828 00:40:25.568385 TX Vref=26, minBit 8, minWin=27, winSum=459
1829 00:40:25.568434 TX Vref=28, minBit 0, minWin=28, winSum=456
1830 00:40:25.568483 TX Vref=30, minBit 0, minWin=28, winSum=456
1831 00:40:25.568531 TX Vref=32, minBit 0, minWin=28, winSum=455
1832 00:40:25.568580 [TxChooseVref] Worse bit 0, Min win 28, Win sum 456, Final Vref 28
1833 00:40:25.568629
1834 00:40:25.568676 Final TX Range 1 Vref 28
1835 00:40:25.568724
1836 00:40:25.568772 ==
1837 00:40:25.568820 Dram Type= 6, Freq= 0, CH_1, rank 1
1838 00:40:25.568869 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1839 00:40:25.568918 ==
1840 00:40:25.568966
1841 00:40:25.569014
1842 00:40:25.569062 TX Vref Scan disable
1843 00:40:25.569110 == TX Byte 0 ==
1844 00:40:25.569159 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1845 00:40:25.569207 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1846 00:40:25.569255 == TX Byte 1 ==
1847 00:40:25.569303 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1848 00:40:25.569352 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1849 00:40:25.569402
1850 00:40:25.569449 [DATLAT]
1851 00:40:25.569497 Freq=800, CH1 RK1
1852 00:40:25.569545
1853 00:40:25.569593 DATLAT Default: 0x9
1854 00:40:25.569669 0, 0xFFFF, sum = 0
1855 00:40:25.569722 1, 0xFFFF, sum = 0
1856 00:40:25.569773 2, 0xFFFF, sum = 0
1857 00:40:25.569823 3, 0xFFFF, sum = 0
1858 00:40:25.569873 4, 0xFFFF, sum = 0
1859 00:40:25.569923 5, 0xFFFF, sum = 0
1860 00:40:25.569972 6, 0xFFFF, sum = 0
1861 00:40:25.570022 7, 0xFFFF, sum = 0
1862 00:40:25.570071 8, 0x0, sum = 1
1863 00:40:25.570120 9, 0x0, sum = 2
1864 00:40:25.570169 10, 0x0, sum = 3
1865 00:40:25.570224 11, 0x0, sum = 4
1866 00:40:25.570274 best_step = 9
1867 00:40:25.570322
1868 00:40:25.570370 ==
1869 00:40:25.570418 Dram Type= 6, Freq= 0, CH_1, rank 1
1870 00:40:25.570467 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1871 00:40:25.570515 ==
1872 00:40:25.570563 RX Vref Scan: 0
1873 00:40:25.570611
1874 00:40:25.570659 RX Vref 0 -> 0, step: 1
1875 00:40:25.570708
1876 00:40:25.570756 RX Delay -111 -> 252, step: 8
1877 00:40:25.570804 iDelay=217, Bit 0, Center 88 (-23 ~ 200) 224
1878 00:40:25.570853 iDelay=217, Bit 1, Center 76 (-39 ~ 192) 232
1879 00:40:25.570902 iDelay=217, Bit 2, Center 76 (-39 ~ 192) 232
1880 00:40:25.570951 iDelay=217, Bit 3, Center 80 (-39 ~ 200) 240
1881 00:40:25.570999 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
1882 00:40:25.571048 iDelay=217, Bit 5, Center 96 (-23 ~ 216) 240
1883 00:40:25.571097 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1884 00:40:25.571146 iDelay=217, Bit 7, Center 84 (-31 ~ 200) 232
1885 00:40:25.571195 iDelay=217, Bit 8, Center 60 (-55 ~ 176) 232
1886 00:40:25.571244 iDelay=217, Bit 9, Center 64 (-47 ~ 176) 224
1887 00:40:25.571292 iDelay=217, Bit 10, Center 72 (-47 ~ 192) 240
1888 00:40:25.571341 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
1889 00:40:25.571390 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
1890 00:40:25.571439 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
1891 00:40:25.571487 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
1892 00:40:25.571535 iDelay=217, Bit 15, Center 80 (-31 ~ 192) 224
1893 00:40:25.571584 ==
1894 00:40:25.571631 Dram Type= 6, Freq= 0, CH_1, rank 1
1895 00:40:25.571680 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1896 00:40:25.571729 ==
1897 00:40:25.571778 DQS Delay:
1898 00:40:25.571826 DQS0 = 0, DQS1 = 0
1899 00:40:25.571874 DQM Delay:
1900 00:40:25.571922 DQM0 = 84, DQM1 = 74
1901 00:40:25.571970 DQ Delay:
1902 00:40:25.572019 DQ0 =88, DQ1 =76, DQ2 =76, DQ3 =80
1903 00:40:25.572068 DQ4 =84, DQ5 =96, DQ6 =92, DQ7 =84
1904 00:40:25.572117 DQ8 =60, DQ9 =64, DQ10 =72, DQ11 =68
1905 00:40:25.572166 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =80
1906 00:40:25.572214
1907 00:40:25.572262
1908 00:40:25.572310 [DQSOSCAuto] RK1, (LSB)MR18= 0x4646, (MSB)MR19= 0x606, tDQSOscB0 = 392 ps tDQSOscB1 = 392 ps
1909 00:40:25.572359 CH1 RK1: MR19=606, MR18=4646
1910 00:40:25.572408 CH1_RK1: MR19=0x606, MR18=0x4646, DQSOSC=392, MR23=63, INC=96, DEC=64
1911 00:40:25.572456 [RxdqsGatingPostProcess] freq 800
1912 00:40:25.572505 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1913 00:40:25.572554 Pre-setting of DQS Precalculation
1914 00:40:25.572602 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1915 00:40:25.572659 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
1916 00:40:25.572722 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
1917 00:40:25.572772
1918 00:40:25.572820
1919 00:40:25.572868 [Calibration Summary] 1600 Mbps
1920 00:40:25.572916 CH 0, Rank 0
1921 00:40:25.572964 SW Impedance : PASS
1922 00:40:25.573013 DUTY Scan : NO K
1923 00:40:25.573062 ZQ Calibration : PASS
1924 00:40:25.573111 Jitter Meter : NO K
1925 00:40:25.573159 CBT Training : PASS
1926 00:40:25.573208 Write leveling : PASS
1927 00:40:25.573442 RX DQS gating : PASS
1928 00:40:25.573497 RX DQ/DQS(RDDQC) : PASS
1929 00:40:25.573548 TX DQ/DQS : PASS
1930 00:40:25.573597 RX DATLAT : PASS
1931 00:40:25.573646 RX DQ/DQS(Engine): PASS
1932 00:40:25.573694 TX OE : NO K
1933 00:40:25.573743 All Pass.
1934 00:40:25.573791
1935 00:40:25.573839 CH 0, Rank 1
1936 00:40:25.573887 SW Impedance : PASS
1937 00:40:25.573936 DUTY Scan : NO K
1938 00:40:25.573984 ZQ Calibration : PASS
1939 00:40:25.574033 Jitter Meter : NO K
1940 00:40:25.574081 CBT Training : PASS
1941 00:40:25.574130 Write leveling : PASS
1942 00:40:25.574178 RX DQS gating : PASS
1943 00:40:25.574232 RX DQ/DQS(RDDQC) : PASS
1944 00:40:25.574282 TX DQ/DQS : PASS
1945 00:40:25.574330 RX DATLAT : PASS
1946 00:40:25.574378 RX DQ/DQS(Engine): PASS
1947 00:40:25.574426 TX OE : NO K
1948 00:40:25.574474 All Pass.
1949 00:40:25.574523
1950 00:40:25.574571 CH 1, Rank 0
1951 00:40:25.574619 SW Impedance : PASS
1952 00:40:25.574667 DUTY Scan : NO K
1953 00:40:25.574716 ZQ Calibration : PASS
1954 00:40:25.574763 Jitter Meter : NO K
1955 00:40:25.574811 CBT Training : PASS
1956 00:40:25.574859 Write leveling : PASS
1957 00:40:25.574907 RX DQS gating : PASS
1958 00:40:25.574955 RX DQ/DQS(RDDQC) : PASS
1959 00:40:25.575003 TX DQ/DQS : PASS
1960 00:40:25.575051 RX DATLAT : PASS
1961 00:40:25.575100 RX DQ/DQS(Engine): PASS
1962 00:40:25.575148 TX OE : NO K
1963 00:40:25.575197 All Pass.
1964 00:40:25.575245
1965 00:40:25.575293 CH 1, Rank 1
1966 00:40:25.575340 SW Impedance : PASS
1967 00:40:25.575388 DUTY Scan : NO K
1968 00:40:25.575436 ZQ Calibration : PASS
1969 00:40:25.575484 Jitter Meter : NO K
1970 00:40:25.575533 CBT Training : PASS
1971 00:40:25.575581 Write leveling : PASS
1972 00:40:25.575629 RX DQS gating : PASS
1973 00:40:25.723450 RX DQ/DQS(RDDQC) : PASS
1974 00:40:25.723888 TX DQ/DQS : PASS
1975 00:40:25.724203 RX DATLAT : PASS
1976 00:40:25.724483 RX DQ/DQS(Engine): PASS
1977 00:40:25.724750 TX OE : NO K
1978 00:40:25.725011 All Pass.
1979 00:40:25.725263
1980 00:40:25.725516 DramC Write-DBI off
1981 00:40:25.725770 PER_BANK_REFRESH: Hybrid Mode
1982 00:40:25.726066 TX_TRACKING: ON
1983 00:40:25.726449 [GetDramInforAfterCalByMRR] Vendor 6.
1984 00:40:25.726713 [GetDramInforAfterCalByMRR] Revision 606.
1985 00:40:25.726965 [GetDramInforAfterCalByMRR] Revision 2 0.
1986 00:40:25.727210 MR0 0x3939
1987 00:40:25.727454 MR8 0x1111
1988 00:40:25.727701 RK0, DieNum 1, Density 16Gb, RKsize 16Gb.
1989 00:40:25.727967
1990 00:40:25.728331 MR0 0x3939
1991 00:40:25.728626 MR8 0x1111
1992 00:40:25.728967 RK1, DieNum 1, Density 16Gb, RKsize 16Gb.
1993 00:40:25.729228
1994 00:40:25.729475 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
1995 00:40:25.729729 [FAST_K] Save calibration result to emmc
1996 00:40:25.729978 [FAST_K] Save calibration result to emmc
1997 00:40:25.730258 dram_init: config_dvfs: 1
1998 00:40:25.730520 dramc_set_vcore_voltage set vcore to 662500
1999 00:40:25.730772 Read voltage for 1200, 2
2000 00:40:25.731019 Vio18 = 0
2001 00:40:25.731264 Vcore = 662500
2002 00:40:25.731510 Vdram = 0
2003 00:40:25.731765 Vddq = 0
2004 00:40:25.732063 Vmddr = 0
2005 00:40:25.732404 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2006 00:40:25.732666 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2007 00:40:25.732917 MEM_TYPE=3, freq_sel=15
2008 00:40:25.733162 sv_algorithm_assistance_LP4_1600
2009 00:40:25.733410 ============ PULL DRAM RESETB DOWN ============
2010 00:40:25.733661 ========== PULL DRAM RESETB DOWN end =========
2011 00:40:25.733911 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2012 00:40:25.734161 ===================================
2013 00:40:25.734459 LPDDR4 DRAM CONFIGURATION
2014 00:40:25.734713 ===================================
2015 00:40:25.734962 EX_ROW_EN[0] = 0x0
2016 00:40:25.735282 EX_ROW_EN[1] = 0x0
2017 00:40:25.735605 LP4Y_EN = 0x0
2018 00:40:25.735859 WORK_FSP = 0x0
2019 00:40:25.736106 WL = 0x4
2020 00:40:25.736350 RL = 0x4
2021 00:40:25.736592 BL = 0x2
2022 00:40:25.736835 RPST = 0x0
2023 00:40:25.737079 RD_PRE = 0x0
2024 00:40:25.737336 WR_PRE = 0x1
2025 00:40:25.737582 WR_PST = 0x0
2026 00:40:25.737827 DBI_WR = 0x0
2027 00:40:25.738071 DBI_RD = 0x0
2028 00:40:25.738357 OTF = 0x1
2029 00:40:25.738730 ===================================
2030 00:40:25.738997 ===================================
2031 00:40:25.739247 ANA top config
2032 00:40:25.739493 ===================================
2033 00:40:25.739740 DLL_ASYNC_EN = 0
2034 00:40:25.739986 ALL_SLAVE_EN = 0
2035 00:40:25.740231 NEW_RANK_MODE = 1
2036 00:40:25.740479 DLL_IDLE_MODE = 1
2037 00:40:25.740724 LP45_APHY_COMB_EN = 1
2038 00:40:25.740967 TX_ODT_DIS = 1
2039 00:40:25.741212 NEW_8X_MODE = 1
2040 00:40:25.741463 ===================================
2041 00:40:25.741771 ===================================
2042 00:40:25.742027 data_rate = 2400
2043 00:40:25.742356 CKR = 1
2044 00:40:25.742697 DQ_P2S_RATIO = 8
2045 00:40:25.742977 ===================================
2046 00:40:25.743356 CA_P2S_RATIO = 8
2047 00:40:25.743620 DQ_CA_OPEN = 0
2048 00:40:25.743871 DQ_SEMI_OPEN = 0
2049 00:40:25.744118 CA_SEMI_OPEN = 0
2050 00:40:25.744363 CA_FULL_RATE = 0
2051 00:40:25.744607 DQ_CKDIV4_EN = 0
2052 00:40:25.744854 CA_CKDIV4_EN = 0
2053 00:40:25.745099 CA_PREDIV_EN = 0
2054 00:40:25.745347 PH8_DLY = 17
2055 00:40:25.745609 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2056 00:40:25.746056 DQ_AAMCK_DIV = 4
2057 00:40:25.746529 CA_AAMCK_DIV = 4
2058 00:40:25.746951 CA_ADMCK_DIV = 4
2059 00:40:25.747350 DQ_TRACK_CA_EN = 0
2060 00:40:25.747746 CA_PICK = 1200
2061 00:40:25.748142 CA_MCKIO = 1200
2062 00:40:25.748536 MCKIO_SEMI = 0
2063 00:40:25.748931 PLL_FREQ = 2366
2064 00:40:25.749345 DQ_UI_PI_RATIO = 32
2065 00:40:25.749626 CA_UI_PI_RATIO = 0
2066 00:40:25.749881 ===================================
2067 00:40:25.750134 ===================================
2068 00:40:25.750440 memory_type:LPDDR4
2069 00:40:25.750693 GP_NUM : 10
2070 00:40:25.750942 SRAM_EN : 1
2071 00:40:25.751186 MD32_EN : 0
2072 00:40:25.751430 ===================================
2073 00:40:25.751678 [ANA_INIT] >>>>>>>>>>>>>>
2074 00:40:25.752018 <<<<<< [CONFIGURE PHASE]: ANA_TX
2075 00:40:25.752364 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2076 00:40:25.752624 ===================================
2077 00:40:25.753232 data_rate = 2400,PCW = 0X5b00
2078 00:40:25.753513 ===================================
2079 00:40:25.753864 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2080 00:40:25.754056 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2081 00:40:25.754262 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2082 00:40:25.754448 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2083 00:40:25.754630 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2084 00:40:25.754808 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2085 00:40:25.754984 [ANA_INIT] flow start
2086 00:40:25.755159 [ANA_INIT] PLL >>>>>>>>
2087 00:40:25.755335 [ANA_INIT] PLL <<<<<<<<
2088 00:40:25.755530 [ANA_INIT] MIDPI >>>>>>>>
2089 00:40:25.755797 [ANA_INIT] MIDPI <<<<<<<<
2090 00:40:25.755984 [ANA_INIT] DLL >>>>>>>>
2091 00:40:25.756161 [ANA_INIT] DLL <<<<<<<<
2092 00:40:25.756341 [ANA_INIT] flow end
2093 00:40:25.756516 ============ LP4 DIFF to SE enter ============
2094 00:40:25.756694 ============ LP4 DIFF to SE exit ============
2095 00:40:25.756873 [ANA_INIT] <<<<<<<<<<<<<
2096 00:40:25.757052 [Flow] Enable top DCM control >>>>>
2097 00:40:25.757233 [Flow] Enable top DCM control <<<<<
2098 00:40:25.757411 Enable DLL master slave shuffle
2099 00:40:25.757589 ==============================================================
2100 00:40:25.757769 Gating Mode config
2101 00:40:25.757950 ==============================================================
2102 00:40:25.758127 Config description:
2103 00:40:25.758320 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2104 00:40:25.758502 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2105 00:40:25.758698 SELPH_MODE 0: By rank 1: By Phase
2106 00:40:25.758909 ==============================================================
2107 00:40:25.759050 GAT_TRACK_EN = 1
2108 00:40:25.759185 RX_GATING_MODE = 2
2109 00:40:25.759319 RX_GATING_TRACK_MODE = 2
2110 00:40:25.759453 SELPH_MODE = 1
2111 00:40:25.759587 PICG_EARLY_EN = 1
2112 00:40:25.759720 VALID_LAT_VALUE = 1
2113 00:40:25.759854 ==============================================================
2114 00:40:25.759988 Enter into Gating configuration >>>>
2115 00:40:25.760123 Exit from Gating configuration <<<<
2116 00:40:25.760256 Enter into DVFS_PRE_config >>>>>
2117 00:40:25.760391 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2118 00:40:25.760529 Exit from DVFS_PRE_config <<<<<
2119 00:40:25.760661 Enter into PICG configuration >>>>
2120 00:40:25.760795 Exit from PICG configuration <<<<
2121 00:40:25.760926 [RX_INPUT] configuration >>>>>
2122 00:40:25.761059 [RX_INPUT] configuration <<<<<
2123 00:40:25.761191 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2124 00:40:25.761326 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2125 00:40:25.761460 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2126 00:40:25.761594 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2127 00:40:25.761728 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2128 00:40:25.761929 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2129 00:40:25.762076 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2130 00:40:25.762223 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2131 00:40:25.762363 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2132 00:40:25.762498 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2133 00:40:25.762630 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2134 00:40:25.762763 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2135 00:40:25.762898 ===================================
2136 00:40:25.763033 LPDDR4 DRAM CONFIGURATION
2137 00:40:25.763168 ===================================
2138 00:40:25.763302 EX_ROW_EN[0] = 0x0
2139 00:40:25.763436 EX_ROW_EN[1] = 0x0
2140 00:40:25.763577 LP4Y_EN = 0x0
2141 00:40:25.763801 WORK_FSP = 0x0
2142 00:40:25.763928 WL = 0x4
2143 00:40:25.764037 RL = 0x4
2144 00:40:25.764144 BL = 0x2
2145 00:40:25.764250 RPST = 0x0
2146 00:40:25.764356 RD_PRE = 0x0
2147 00:40:25.764462 WR_PRE = 0x1
2148 00:40:25.764566 WR_PST = 0x0
2149 00:40:25.764671 DBI_WR = 0x0
2150 00:40:25.764777 DBI_RD = 0x0
2151 00:40:25.764884 OTF = 0x1
2152 00:40:25.764992 ===================================
2153 00:40:25.765101 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2154 00:40:25.765209 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2155 00:40:25.765315 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2156 00:40:25.765423 ===================================
2157 00:40:25.765531 LPDDR4 DRAM CONFIGURATION
2158 00:40:25.765637 ===================================
2159 00:40:25.765743 EX_ROW_EN[0] = 0x10
2160 00:40:25.765850 EX_ROW_EN[1] = 0x0
2161 00:40:25.765956 LP4Y_EN = 0x0
2162 00:40:25.766062 WORK_FSP = 0x0
2163 00:40:25.766167 WL = 0x4
2164 00:40:25.766291 RL = 0x4
2165 00:40:25.766398 BL = 0x2
2166 00:40:25.766504 RPST = 0x0
2167 00:40:25.766610 RD_PRE = 0x0
2168 00:40:25.766714 WR_PRE = 0x1
2169 00:40:25.766819 WR_PST = 0x0
2170 00:40:25.766925 DBI_WR = 0x0
2171 00:40:25.767031 DBI_RD = 0x0
2172 00:40:25.767137 OTF = 0x1
2173 00:40:25.767243 ===================================
2174 00:40:25.767351 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2175 00:40:25.767460 ==
2176 00:40:25.767567 Dram Type= 6, Freq= 0, CH_0, rank 0
2177 00:40:25.767675 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2178 00:40:25.767782 ==
2179 00:40:25.767952 [Duty_Offset_Calibration]
2180 00:40:25.768068 B0:0 B1:2 CA:1
2181 00:40:25.768176
2182 00:40:25.768283 [DutyScan_Calibration_Flow] k_type=0
2183 00:40:25.768390
2184 00:40:25.768496 ==CLK 0==
2185 00:40:25.768605 Final CLK duty delay cell = 0
2186 00:40:25.768728 [0] MAX Duty = 5093%(X100), DQS PI = 12
2187 00:40:25.768857 [0] MIN Duty = 4938%(X100), DQS PI = 52
2188 00:40:25.768951 [0] AVG Duty = 5015%(X100)
2189 00:40:25.769040
2190 00:40:25.769363 CH0 CLK Duty spec in!! Max-Min= 155%
2191 00:40:25.769465 [DutyScan_Calibration_Flow] ====Done====
2192 00:40:25.769557
2193 00:40:25.769653 [DutyScan_Calibration_Flow] k_type=1
2194 00:40:25.769745
2195 00:40:25.769835 ==DQS 0 ==
2196 00:40:25.769926 Final DQS duty delay cell = 0
2197 00:40:25.770018 [0] MAX Duty = 5125%(X100), DQS PI = 32
2198 00:40:25.770109 [0] MIN Duty = 5031%(X100), DQS PI = 4
2199 00:40:25.770199 [0] AVG Duty = 5078%(X100)
2200 00:40:25.770300
2201 00:40:25.770389 ==DQS 1 ==
2202 00:40:25.770478 Final DQS duty delay cell = 0
2203 00:40:25.770567 [0] MAX Duty = 5031%(X100), DQS PI = 54
2204 00:40:25.770657 [0] MIN Duty = 4906%(X100), DQS PI = 14
2205 00:40:25.770746 [0] AVG Duty = 4968%(X100)
2206 00:40:25.770834
2207 00:40:25.770922 CH0 DQS 0 Duty spec in!! Max-Min= 94%
2208 00:40:25.771011
2209 00:40:25.771099 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2210 00:40:25.771188 [DutyScan_Calibration_Flow] ====Done====
2211 00:40:25.771277
2212 00:40:25.771365 [DutyScan_Calibration_Flow] k_type=3
2213 00:40:25.771454
2214 00:40:25.771542 ==DQM 0 ==
2215 00:40:25.771632 Final DQM duty delay cell = 0
2216 00:40:25.771723 [0] MAX Duty = 5156%(X100), DQS PI = 22
2217 00:40:25.771811 [0] MIN Duty = 4969%(X100), DQS PI = 40
2218 00:40:25.771901 [0] AVG Duty = 5062%(X100)
2219 00:40:25.772005
2220 00:40:25.772116 ==DQM 1 ==
2221 00:40:25.772207 Final DQM duty delay cell = 4
2222 00:40:25.772299 [4] MAX Duty = 5187%(X100), DQS PI = 54
2223 00:40:25.772390 [4] MIN Duty = 5000%(X100), DQS PI = 16
2224 00:40:25.772481 [4] AVG Duty = 5093%(X100)
2225 00:40:25.772570
2226 00:40:25.772658 CH0 DQM 0 Duty spec in!! Max-Min= 187%
2227 00:40:25.772747
2228 00:40:25.772836 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2229 00:40:25.772925 [DutyScan_Calibration_Flow] ====Done====
2230 00:40:25.773014
2231 00:40:25.773102 [DutyScan_Calibration_Flow] k_type=2
2232 00:40:25.773190
2233 00:40:25.773278 ==DQ 0 ==
2234 00:40:25.773367 Final DQ duty delay cell = -4
2235 00:40:25.773457 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2236 00:40:25.773548 [-4] MIN Duty = 4782%(X100), DQS PI = 54
2237 00:40:25.773638 [-4] AVG Duty = 4922%(X100)
2238 00:40:25.773730
2239 00:40:25.773828 ==DQ 1 ==
2240 00:40:25.773906 Final DQ duty delay cell = -4
2241 00:40:25.773983 [-4] MAX Duty = 5062%(X100), DQS PI = 6
2242 00:40:25.774060 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2243 00:40:25.774138 [-4] AVG Duty = 4984%(X100)
2244 00:40:25.774224
2245 00:40:25.774305 CH0 DQ 0 Duty spec in!! Max-Min= 280%
2246 00:40:25.774381
2247 00:40:25.774457 CH0 DQ 1 Duty spec in!! Max-Min= 155%
2248 00:40:25.774533 [DutyScan_Calibration_Flow] ====Done====
2249 00:40:25.774610 ==
2250 00:40:25.774687 Dram Type= 6, Freq= 0, CH_1, rank 0
2251 00:40:25.774764 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2252 00:40:25.774842 ==
2253 00:40:25.774919 [Duty_Offset_Calibration]
2254 00:40:25.774995 B0:0 B1:5 CA:-5
2255 00:40:25.775072
2256 00:40:25.775148 [DutyScan_Calibration_Flow] k_type=0
2257 00:40:25.775261
2258 00:40:25.775347 ==CLK 0==
2259 00:40:25.775424 Final CLK duty delay cell = 0
2260 00:40:25.775502 [0] MAX Duty = 5094%(X100), DQS PI = 24
2261 00:40:25.775580 [0] MIN Duty = 4875%(X100), DQS PI = 48
2262 00:40:25.775657 [0] AVG Duty = 4984%(X100)
2263 00:40:25.775733
2264 00:40:25.775822 CH1 CLK Duty spec in!! Max-Min= 219%
2265 00:40:25.775954 [DutyScan_Calibration_Flow] ====Done====
2266 00:40:25.776041
2267 00:40:25.776118 [DutyScan_Calibration_Flow] k_type=1
2268 00:40:25.776197
2269 00:40:25.776275 ==DQS 0 ==
2270 00:40:25.776352 Final DQS duty delay cell = 0
2271 00:40:25.776431 [0] MAX Duty = 5125%(X100), DQS PI = 16
2272 00:40:25.776508 [0] MIN Duty = 4875%(X100), DQS PI = 40
2273 00:40:25.776585 [0] AVG Duty = 5000%(X100)
2274 00:40:25.776660
2275 00:40:25.776734 ==DQS 1 ==
2276 00:40:25.776810 Final DQS duty delay cell = -4
2277 00:40:25.776887 [-4] MAX Duty = 5031%(X100), DQS PI = 20
2278 00:40:25.776965 [-4] MIN Duty = 4876%(X100), DQS PI = 44
2279 00:40:25.777041 [-4] AVG Duty = 4953%(X100)
2280 00:40:25.777117
2281 00:40:25.777193 CH1 DQS 0 Duty spec in!! Max-Min= 250%
2282 00:40:25.777271
2283 00:40:25.777346 CH1 DQS 1 Duty spec in!! Max-Min= 155%
2284 00:40:25.777423 [DutyScan_Calibration_Flow] ====Done====
2285 00:40:25.777499
2286 00:40:25.777575 [DutyScan_Calibration_Flow] k_type=3
2287 00:40:25.777652
2288 00:40:25.777728 ==DQM 0 ==
2289 00:40:25.777804 Final DQM duty delay cell = -4
2290 00:40:25.777881 [-4] MAX Duty = 5093%(X100), DQS PI = 32
2291 00:40:25.777958 [-4] MIN Duty = 4844%(X100), DQS PI = 40
2292 00:40:25.778034 [-4] AVG Duty = 4968%(X100)
2293 00:40:25.778111
2294 00:40:25.778186 ==DQM 1 ==
2295 00:40:25.778275 Final DQM duty delay cell = -4
2296 00:40:25.778353 [-4] MAX Duty = 5062%(X100), DQS PI = 4
2297 00:40:25.778430 [-4] MIN Duty = 4906%(X100), DQS PI = 42
2298 00:40:25.778507 [-4] AVG Duty = 4984%(X100)
2299 00:40:25.778582
2300 00:40:25.778661 CH1 DQM 0 Duty spec in!! Max-Min= 249%
2301 00:40:25.778774
2302 00:40:25.778844 CH1 DQM 1 Duty spec in!! Max-Min= 156%
2303 00:40:25.778912 [DutyScan_Calibration_Flow] ====Done====
2304 00:40:25.778979
2305 00:40:25.779047 [DutyScan_Calibration_Flow] k_type=2
2306 00:40:25.779115
2307 00:40:25.779182 ==DQ 0 ==
2308 00:40:25.779249 Final DQ duty delay cell = 0
2309 00:40:25.779317 [0] MAX Duty = 5062%(X100), DQS PI = 0
2310 00:40:25.779385 [0] MIN Duty = 4938%(X100), DQS PI = 44
2311 00:40:25.779452 [0] AVG Duty = 5000%(X100)
2312 00:40:25.779519
2313 00:40:25.779584 ==DQ 1 ==
2314 00:40:25.779652 Final DQ duty delay cell = 0
2315 00:40:25.779719 [0] MAX Duty = 5000%(X100), DQS PI = 6
2316 00:40:25.779787 [0] MIN Duty = 4907%(X100), DQS PI = 0
2317 00:40:25.779855 [0] AVG Duty = 4953%(X100)
2318 00:40:25.779922
2319 00:40:25.779989 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2320 00:40:25.780057
2321 00:40:25.780124 CH1 DQ 1 Duty spec in!! Max-Min= 93%
2322 00:40:25.780191 [DutyScan_Calibration_Flow] ====Done====
2323 00:40:25.780258 nWR fixed to 30
2324 00:40:25.780325 [ModeRegInit_LP4] CH0 RK0
2325 00:40:25.780393 [ModeRegInit_LP4] CH0 RK1
2326 00:40:25.780459 [ModeRegInit_LP4] CH1 RK0
2327 00:40:25.780525 [ModeRegInit_LP4] CH1 RK1
2328 00:40:25.780592 match AC timing 6
2329 00:40:25.780658 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 0
2330 00:40:25.780726 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2331 00:40:25.780792 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2332 00:40:25.780858 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2333 00:40:25.780924 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2334 00:40:25.780991 ==
2335 00:40:25.781058 Dram Type= 6, Freq= 0, CH_0, rank 0
2336 00:40:25.781125 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2337 00:40:25.781192 ==
2338 00:40:25.781258 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2339 00:40:25.781324 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2340 00:40:25.781391 [CA 0] Center 39 (9~70) winsize 62
2341 00:40:25.781457 [CA 1] Center 39 (8~70) winsize 63
2342 00:40:25.781523 [CA 2] Center 36 (5~67) winsize 63
2343 00:40:25.781793 [CA 3] Center 35 (5~66) winsize 62
2344 00:40:25.781868 [CA 4] Center 34 (3~65) winsize 63
2345 00:40:25.781936 [CA 5] Center 33 (3~64) winsize 62
2346 00:40:25.782002
2347 00:40:25.782069 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2348 00:40:25.782136
2349 00:40:25.782202 [CATrainingPosCal] consider 1 rank data
2350 00:40:25.782286 u2DelayCellTimex100 = 270/100 ps
2351 00:40:25.782354 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2352 00:40:25.782420 CA1 delay=39 (8~70),Diff = 6 PI (28 cell)
2353 00:40:25.782488 CA2 delay=36 (5~67),Diff = 3 PI (14 cell)
2354 00:40:25.782554 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2355 00:40:25.782619 CA4 delay=34 (3~65),Diff = 1 PI (4 cell)
2356 00:40:25.782685 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2357 00:40:25.782750
2358 00:40:25.782815 CA PerBit enable=1, Macro0, CA PI delay=33
2359 00:40:25.782880
2360 00:40:25.782945 [CBTSetCACLKResult] CA Dly = 33
2361 00:40:25.783010 CS Dly: 7 (0~38)
2362 00:40:25.783076 ==
2363 00:40:25.783142 Dram Type= 6, Freq= 0, CH_0, rank 1
2364 00:40:25.783208 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2365 00:40:25.783275 ==
2366 00:40:25.783342 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2367 00:40:25.783409 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2368 00:40:25.783475 [CA 0] Center 39 (9~70) winsize 62
2369 00:40:25.783544 [CA 1] Center 39 (8~70) winsize 63
2370 00:40:25.783610 [CA 2] Center 36 (5~67) winsize 63
2371 00:40:25.783687 [CA 3] Center 35 (4~66) winsize 63
2372 00:40:25.783746 [CA 4] Center 33 (3~64) winsize 62
2373 00:40:25.783804 [CA 5] Center 34 (3~65) winsize 63
2374 00:40:25.783862
2375 00:40:25.783920 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2376 00:40:25.783979
2377 00:40:25.784037 [CATrainingPosCal] consider 2 rank data
2378 00:40:25.784095 u2DelayCellTimex100 = 270/100 ps
2379 00:40:25.784153 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2380 00:40:25.784212 CA1 delay=39 (8~70),Diff = 6 PI (28 cell)
2381 00:40:25.784271 CA2 delay=36 (5~67),Diff = 3 PI (14 cell)
2382 00:40:25.784329 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2383 00:40:25.784387 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2384 00:40:25.784446 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2385 00:40:25.784504
2386 00:40:25.784563 CA PerBit enable=1, Macro0, CA PI delay=33
2387 00:40:25.784621
2388 00:40:25.784678 [CBTSetCACLKResult] CA Dly = 33
2389 00:40:25.784762 CS Dly: 7 (0~39)
2390 00:40:25.784827
2391 00:40:25.784887 ----->DramcWriteLeveling(PI) begin...
2392 00:40:25.784947 ==
2393 00:40:25.785006 Dram Type= 6, Freq= 0, CH_0, rank 0
2394 00:40:25.785066 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2395 00:40:25.785125 ==
2396 00:40:25.785184 Write leveling (Byte 0): 27 => 27
2397 00:40:25.785243 Write leveling (Byte 1): 27 => 27
2398 00:40:25.785302 DramcWriteLeveling(PI) end<-----
2399 00:40:25.785362
2400 00:40:25.785420 ==
2401 00:40:25.785480 Dram Type= 6, Freq= 0, CH_0, rank 0
2402 00:40:25.785539 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2403 00:40:25.785599 ==
2404 00:40:25.785659 [Gating] SW mode calibration
2405 00:40:25.785718 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2406 00:40:25.785778 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2407 00:40:25.785837 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2408 00:40:25.785898 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2409 00:40:25.785964 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2410 00:40:25.786024 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2411 00:40:25.786083 0 11 16 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
2412 00:40:25.786142 0 11 20 | B1->B0 | 2c2c 2727 | 0 0 | (1 0) (0 0)
2413 00:40:25.786201 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2414 00:40:25.786266 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2415 00:40:25.786324 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2416 00:40:25.786383 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2417 00:40:25.786442 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2418 00:40:25.786501 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2419 00:40:25.786560 0 12 16 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
2420 00:40:25.786619 0 12 20 | B1->B0 | 3535 3c3c | 0 1 | (0 0) (0 0)
2421 00:40:25.786678 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2422 00:40:25.786737 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2423 00:40:25.786795 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2424 00:40:25.786854 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2425 00:40:25.786912 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2426 00:40:25.786971 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2427 00:40:25.787031 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2428 00:40:25.787090 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2429 00:40:25.787149 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2430 00:40:25.787208 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2431 00:40:25.787266 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2432 00:40:25.787325 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2433 00:40:25.787383 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2434 00:40:25.787442 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2435 00:40:25.787501 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2436 00:40:25.787560 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2437 00:40:25.787620 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2438 00:40:25.787679 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2439 00:40:25.787738 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2440 00:40:25.787796 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2441 00:40:25.787855 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2442 00:40:25.787914 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2443 00:40:25.787974 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2444 00:40:25.788033 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2445 00:40:25.788092 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2446 00:40:25.788151 Total UI for P1: 0, mck2ui 16
2447 00:40:25.788211 best dqsien dly found for B0: ( 0, 15, 18)
2448 00:40:25.788270 Total UI for P1: 0, mck2ui 16
2449 00:40:25.788525 best dqsien dly found for B1: ( 0, 15, 18)
2450 00:40:25.788591 best DQS0 dly(MCK, UI, PI) = (0, 15, 18)
2451 00:40:25.788652 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
2452 00:40:25.788724
2453 00:40:25.788777 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 18)
2454 00:40:25.788830 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
2455 00:40:25.788884 [Gating] SW calibration Done
2456 00:40:25.788937 ==
2457 00:40:25.788990 Dram Type= 6, Freq= 0, CH_0, rank 0
2458 00:40:25.789043 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2459 00:40:25.789097 ==
2460 00:40:25.789150 RX Vref Scan: 0
2461 00:40:25.789202
2462 00:40:25.789254 RX Vref 0 -> 0, step: 1
2463 00:40:25.789306
2464 00:40:25.789358 RX Delay -40 -> 252, step: 8
2465 00:40:25.789411 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2466 00:40:25.789464 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2467 00:40:25.789517 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2468 00:40:25.789570 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2469 00:40:25.789622 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2470 00:40:25.789675 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2471 00:40:25.789728 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2472 00:40:25.789781 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2473 00:40:25.789833 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2474 00:40:25.789887 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2475 00:40:25.789940 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2476 00:40:25.789993 iDelay=200, Bit 11, Center 103 (40 ~ 167) 128
2477 00:40:25.790045 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2478 00:40:25.790098 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2479 00:40:25.790151 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
2480 00:40:25.790205 iDelay=200, Bit 15, Center 115 (40 ~ 191) 152
2481 00:40:25.790266 ==
2482 00:40:25.790320 Dram Type= 6, Freq= 0, CH_0, rank 0
2483 00:40:25.790373 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2484 00:40:25.790427 ==
2485 00:40:25.790479 DQS Delay:
2486 00:40:25.790531 DQS0 = 0, DQS1 = 0
2487 00:40:25.790583 DQM Delay:
2488 00:40:25.790636 DQM0 = 115, DQM1 = 106
2489 00:40:25.790689 DQ Delay:
2490 00:40:25.790742 DQ0 =111, DQ1 =115, DQ2 =115, DQ3 =107
2491 00:40:25.790794 DQ4 =123, DQ5 =103, DQ6 =123, DQ7 =123
2492 00:40:25.790847 DQ8 =95, DQ9 =91, DQ10 =103, DQ11 =103
2493 00:40:25.790899 DQ12 =111, DQ13 =115, DQ14 =115, DQ15 =115
2494 00:40:25.790951
2495 00:40:25.791003
2496 00:40:25.791054 ==
2497 00:40:25.791106 Dram Type= 6, Freq= 0, CH_0, rank 0
2498 00:40:25.791159 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2499 00:40:25.791212 ==
2500 00:40:25.791265
2501 00:40:25.791317
2502 00:40:25.791370 TX Vref Scan disable
2503 00:40:25.791422 == TX Byte 0 ==
2504 00:40:25.791475 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2505 00:40:25.791528 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2506 00:40:25.791580 == TX Byte 1 ==
2507 00:40:25.791631 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2508 00:40:25.791684 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2509 00:40:25.791736 ==
2510 00:40:25.791789 Dram Type= 6, Freq= 0, CH_0, rank 0
2511 00:40:25.791842 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2512 00:40:25.791895 ==
2513 00:40:25.791947 TX Vref=22, minBit 8, minWin=24, winSum=413
2514 00:40:25.792001 TX Vref=24, minBit 15, minWin=25, winSum=425
2515 00:40:25.792054 TX Vref=26, minBit 15, minWin=25, winSum=431
2516 00:40:25.792107 TX Vref=28, minBit 8, minWin=26, winSum=433
2517 00:40:25.792160 TX Vref=30, minBit 5, minWin=26, winSum=434
2518 00:40:25.792213 TX Vref=32, minBit 5, minWin=26, winSum=435
2519 00:40:25.792266 [TxChooseVref] Worse bit 5, Min win 26, Win sum 435, Final Vref 32
2520 00:40:25.792319
2521 00:40:25.792373 Final TX Range 1 Vref 32
2522 00:40:25.792426
2523 00:40:25.792478 ==
2524 00:40:25.792531 Dram Type= 6, Freq= 0, CH_0, rank 0
2525 00:40:25.792584 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2526 00:40:25.792637 ==
2527 00:40:25.792689
2528 00:40:25.792741
2529 00:40:25.792793 TX Vref Scan disable
2530 00:40:25.792846 == TX Byte 0 ==
2531 00:40:25.792899 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2532 00:40:25.792952 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2533 00:40:25.793005 == TX Byte 1 ==
2534 00:40:25.793057 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
2535 00:40:25.793109 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
2536 00:40:25.793161
2537 00:40:25.793214 [DATLAT]
2538 00:40:25.793267 Freq=1200, CH0 RK0
2539 00:40:25.793320
2540 00:40:25.793372 DATLAT Default: 0xd
2541 00:40:25.793424 0, 0xFFFF, sum = 0
2542 00:40:25.793478 1, 0xFFFF, sum = 0
2543 00:40:25.793532 2, 0xFFFF, sum = 0
2544 00:40:25.793586 3, 0xFFFF, sum = 0
2545 00:40:25.793639 4, 0xFFFF, sum = 0
2546 00:40:25.793701 5, 0xFFFF, sum = 0
2547 00:40:25.793749 6, 0xFFFF, sum = 0
2548 00:40:25.793798 7, 0xFFFF, sum = 0
2549 00:40:25.793846 8, 0xFFFF, sum = 0
2550 00:40:25.793895 9, 0xFFFF, sum = 0
2551 00:40:25.793944 10, 0xFFFF, sum = 0
2552 00:40:25.793992 11, 0x0, sum = 1
2553 00:40:25.794040 12, 0x0, sum = 2
2554 00:40:25.794089 13, 0x0, sum = 3
2555 00:40:25.794138 14, 0x0, sum = 4
2556 00:40:25.794186 best_step = 12
2557 00:40:25.794256
2558 00:40:25.794305 ==
2559 00:40:25.794354 Dram Type= 6, Freq= 0, CH_0, rank 0
2560 00:40:25.794403 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2561 00:40:25.794451 ==
2562 00:40:25.794499 RX Vref Scan: 1
2563 00:40:25.794548
2564 00:40:25.794596 Set Vref Range= 32 -> 127
2565 00:40:25.794643
2566 00:40:25.794692 RX Vref 32 -> 127, step: 1
2567 00:40:25.794740
2568 00:40:25.794788 RX Delay -21 -> 252, step: 4
2569 00:40:25.794836
2570 00:40:25.794884 Set Vref, RX VrefLevel [Byte0]: 32
2571 00:40:25.794931 [Byte1]: 32
2572 00:40:25.794980
2573 00:40:25.795027 Set Vref, RX VrefLevel [Byte0]: 33
2574 00:40:25.795076 [Byte1]: 33
2575 00:40:25.795124
2576 00:40:25.795171 Set Vref, RX VrefLevel [Byte0]: 34
2577 00:40:25.795219 [Byte1]: 34
2578 00:40:25.795267
2579 00:40:25.795315 Set Vref, RX VrefLevel [Byte0]: 35
2580 00:40:25.795363 [Byte1]: 35
2581 00:40:25.795411
2582 00:40:25.795459 Set Vref, RX VrefLevel [Byte0]: 36
2583 00:40:25.795507 [Byte1]: 36
2584 00:40:25.795555
2585 00:40:25.795603 Set Vref, RX VrefLevel [Byte0]: 37
2586 00:40:25.795651 [Byte1]: 37
2587 00:40:25.795699
2588 00:40:25.795746 Set Vref, RX VrefLevel [Byte0]: 38
2589 00:40:25.795794 [Byte1]: 38
2590 00:40:25.795842
2591 00:40:25.795889 Set Vref, RX VrefLevel [Byte0]: 39
2592 00:40:25.795937 [Byte1]: 39
2593 00:40:25.795985
2594 00:40:25.796033 Set Vref, RX VrefLevel [Byte0]: 40
2595 00:40:25.796081 [Byte1]: 40
2596 00:40:25.796128
2597 00:40:25.796176 Set Vref, RX VrefLevel [Byte0]: 41
2598 00:40:25.796224 [Byte1]: 41
2599 00:40:25.796272
2600 00:40:25.796320 Set Vref, RX VrefLevel [Byte0]: 42
2601 00:40:25.796368 [Byte1]: 42
2602 00:40:25.796417
2603 00:40:25.796464 Set Vref, RX VrefLevel [Byte0]: 43
2604 00:40:25.796698 [Byte1]: 43
2605 00:40:25.796753
2606 00:40:25.796802 Set Vref, RX VrefLevel [Byte0]: 44
2607 00:40:25.796851 [Byte1]: 44
2608 00:40:25.796899
2609 00:40:25.796948 Set Vref, RX VrefLevel [Byte0]: 45
2610 00:40:25.796996 [Byte1]: 45
2611 00:40:25.797044
2612 00:40:25.797091 Set Vref, RX VrefLevel [Byte0]: 46
2613 00:40:25.797140 [Byte1]: 46
2614 00:40:25.797189
2615 00:40:25.797236 Set Vref, RX VrefLevel [Byte0]: 47
2616 00:40:25.797285 [Byte1]: 47
2617 00:40:25.797333
2618 00:40:25.797381 Set Vref, RX VrefLevel [Byte0]: 48
2619 00:40:25.797428 [Byte1]: 48
2620 00:40:25.797476
2621 00:40:25.797523 Set Vref, RX VrefLevel [Byte0]: 49
2622 00:40:25.797571 [Byte1]: 49
2623 00:40:25.797619
2624 00:40:25.797666 Set Vref, RX VrefLevel [Byte0]: 50
2625 00:40:25.797714 [Byte1]: 50
2626 00:40:25.797762
2627 00:40:25.797809 Set Vref, RX VrefLevel [Byte0]: 51
2628 00:40:25.797857 [Byte1]: 51
2629 00:40:25.797905
2630 00:40:25.797952 Set Vref, RX VrefLevel [Byte0]: 52
2631 00:40:25.797999 [Byte1]: 52
2632 00:40:25.798046
2633 00:40:25.798094 Set Vref, RX VrefLevel [Byte0]: 53
2634 00:40:25.798142 [Byte1]: 53
2635 00:40:25.798190
2636 00:40:25.798248 Set Vref, RX VrefLevel [Byte0]: 54
2637 00:40:25.798297 [Byte1]: 54
2638 00:40:25.798344
2639 00:40:25.798392 Set Vref, RX VrefLevel [Byte0]: 55
2640 00:40:25.798439 [Byte1]: 55
2641 00:40:25.798487
2642 00:40:25.798534 Set Vref, RX VrefLevel [Byte0]: 56
2643 00:40:25.798582 [Byte1]: 56
2644 00:40:25.798630
2645 00:40:25.798678 Set Vref, RX VrefLevel [Byte0]: 57
2646 00:40:25.798738 [Byte1]: 57
2647 00:40:25.798785
2648 00:40:25.798831 Set Vref, RX VrefLevel [Byte0]: 58
2649 00:40:25.798879 [Byte1]: 58
2650 00:40:25.798925
2651 00:40:25.798971 Set Vref, RX VrefLevel [Byte0]: 59
2652 00:40:25.799019 [Byte1]: 59
2653 00:40:25.799066
2654 00:40:25.799112 Set Vref, RX VrefLevel [Byte0]: 60
2655 00:40:25.799159 [Byte1]: 60
2656 00:40:25.799206
2657 00:40:25.799253 Set Vref, RX VrefLevel [Byte0]: 61
2658 00:40:25.799299 [Byte1]: 61
2659 00:40:25.799346
2660 00:40:25.799393 Set Vref, RX VrefLevel [Byte0]: 62
2661 00:40:25.799439 [Byte1]: 62
2662 00:40:25.799485
2663 00:40:25.799531 Set Vref, RX VrefLevel [Byte0]: 63
2664 00:40:25.799578 [Byte1]: 63
2665 00:40:25.799625
2666 00:40:25.799671 Set Vref, RX VrefLevel [Byte0]: 64
2667 00:40:25.799717 [Byte1]: 64
2668 00:40:25.799764
2669 00:40:25.799810 Set Vref, RX VrefLevel [Byte0]: 65
2670 00:40:25.799857 [Byte1]: 65
2671 00:40:25.799903
2672 00:40:25.799949 Set Vref, RX VrefLevel [Byte0]: 66
2673 00:40:25.799996 [Byte1]: 66
2674 00:40:25.800042
2675 00:40:25.800089 Final RX Vref Byte 0 = 46 to rank0
2676 00:40:25.800136 Final RX Vref Byte 1 = 50 to rank0
2677 00:40:25.800184 Final RX Vref Byte 0 = 46 to rank1
2678 00:40:25.800231 Final RX Vref Byte 1 = 50 to rank1==
2679 00:40:25.800278 Dram Type= 6, Freq= 0, CH_0, rank 0
2680 00:40:25.800326 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2681 00:40:25.800373 ==
2682 00:40:25.800420 DQS Delay:
2683 00:40:25.800466 DQS0 = 0, DQS1 = 0
2684 00:40:25.800513 DQM Delay:
2685 00:40:25.800560 DQM0 = 114, DQM1 = 105
2686 00:40:25.800607 DQ Delay:
2687 00:40:25.800653 DQ0 =110, DQ1 =114, DQ2 =112, DQ3 =108
2688 00:40:25.800700 DQ4 =118, DQ5 =106, DQ6 =124, DQ7 =120
2689 00:40:25.800748 DQ8 =94, DQ9 =86, DQ10 =106, DQ11 =98
2690 00:40:25.800795 DQ12 =114, DQ13 =112, DQ14 =118, DQ15 =116
2691 00:40:25.800841
2692 00:40:25.800887
2693 00:40:25.800934 [DQSOSCAuto] RK0, (LSB)MR18= 0xa0a, (MSB)MR19= 0x404, tDQSOscB0 = 406 ps tDQSOscB1 = 406 ps
2694 00:40:25.800983 CH0 RK0: MR19=404, MR18=A0A
2695 00:40:25.801030 CH0_RK0: MR19=0x404, MR18=0xA0A, DQSOSC=406, MR23=63, INC=39, DEC=26
2696 00:40:25.801078
2697 00:40:25.801124 ----->DramcWriteLeveling(PI) begin...
2698 00:40:25.801172 ==
2699 00:40:25.801219 Dram Type= 6, Freq= 0, CH_0, rank 1
2700 00:40:25.801266 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2701 00:40:25.801314 ==
2702 00:40:25.801361 Write leveling (Byte 0): 28 => 28
2703 00:40:25.801409 Write leveling (Byte 1): 24 => 24
2704 00:40:25.801456 DramcWriteLeveling(PI) end<-----
2705 00:40:25.801502
2706 00:40:25.801548 ==
2707 00:40:25.801595 Dram Type= 6, Freq= 0, CH_0, rank 1
2708 00:40:25.801642 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2709 00:40:25.801689 ==
2710 00:40:25.801735 [Gating] SW mode calibration
2711 00:40:25.801782 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2712 00:40:25.801830 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2713 00:40:25.801877 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2714 00:40:25.801924 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2715 00:40:25.801971 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2716 00:40:25.802018 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2717 00:40:25.802065 0 11 16 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 1)
2718 00:40:25.802112 0 11 20 | B1->B0 | 2f2f 2525 | 0 0 | (1 0) (0 0)
2719 00:40:25.802159 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2720 00:40:25.802206 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2721 00:40:25.802297 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2722 00:40:25.802345 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2723 00:40:25.802391 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2724 00:40:25.802438 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2725 00:40:25.802485 0 12 16 | B1->B0 | 2424 3333 | 0 1 | (0 0) (0 0)
2726 00:40:25.802532 0 12 20 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
2727 00:40:25.802579 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2728 00:40:25.802625 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2729 00:40:25.802672 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2730 00:40:25.802720 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2731 00:40:25.802767 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2732 00:40:25.802814 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2733 00:40:25.802861 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2734 00:40:25.802908 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2735 00:40:25.803142 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2736 00:40:25.803195 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2737 00:40:25.803244 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2738 00:40:25.803292 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2739 00:40:25.803339 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2740 00:40:25.803387 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2741 00:40:25.803434 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2742 00:40:25.803482 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2743 00:40:25.803529 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2744 00:40:25.803576 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2745 00:40:25.803623 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2746 00:40:25.803671 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2747 00:40:25.803718 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2748 00:40:25.803768 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2749 00:40:25.803815 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2750 00:40:25.803863 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2751 00:40:25.803910 Total UI for P1: 0, mck2ui 16
2752 00:40:25.803957 best dqsien dly found for B0: ( 0, 15, 16)
2753 00:40:25.804004 Total UI for P1: 0, mck2ui 16
2754 00:40:25.804052 best dqsien dly found for B1: ( 0, 15, 16)
2755 00:40:25.804099 best DQS0 dly(MCK, UI, PI) = (0, 15, 16)
2756 00:40:25.804146 best DQS1 dly(MCK, UI, PI) = (0, 15, 16)
2757 00:40:25.804193
2758 00:40:25.804240 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 16)
2759 00:40:25.804288 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 16)
2760 00:40:25.804335 [Gating] SW calibration Done
2761 00:40:25.804381 ==
2762 00:40:25.804428 Dram Type= 6, Freq= 0, CH_0, rank 1
2763 00:40:25.804476 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2764 00:40:25.804523 ==
2765 00:40:25.804570 RX Vref Scan: 0
2766 00:40:25.804618
2767 00:40:25.804664 RX Vref 0 -> 0, step: 1
2768 00:40:25.804712
2769 00:40:25.804758 RX Delay -40 -> 252, step: 8
2770 00:40:25.804806 iDelay=200, Bit 0, Center 107 (32 ~ 183) 152
2771 00:40:25.804853 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2772 00:40:25.804899 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2773 00:40:25.804947 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2774 00:40:25.804995 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2775 00:40:25.805042 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2776 00:40:25.805090 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
2777 00:40:25.805136 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2778 00:40:25.805183 iDelay=200, Bit 8, Center 91 (24 ~ 159) 136
2779 00:40:25.805231 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2780 00:40:25.805277 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
2781 00:40:25.805324 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2782 00:40:25.805372 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2783 00:40:25.805419 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2784 00:40:25.805465 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2785 00:40:25.805512 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2786 00:40:25.805559 ==
2787 00:40:25.805606 Dram Type= 6, Freq= 0, CH_0, rank 1
2788 00:40:25.805653 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2789 00:40:25.805700 ==
2790 00:40:25.805746 DQS Delay:
2791 00:40:25.805793 DQS0 = 0, DQS1 = 0
2792 00:40:25.805839 DQM Delay:
2793 00:40:25.805886 DQM0 = 114, DQM1 = 107
2794 00:40:25.805933 DQ Delay:
2795 00:40:25.805979 DQ0 =107, DQ1 =115, DQ2 =115, DQ3 =111
2796 00:40:25.806027 DQ4 =115, DQ5 =107, DQ6 =119, DQ7 =123
2797 00:40:25.806074 DQ8 =91, DQ9 =95, DQ10 =107, DQ11 =99
2798 00:40:25.806121 DQ12 =115, DQ13 =115, DQ14 =119, DQ15 =115
2799 00:40:25.806168
2800 00:40:25.806237
2801 00:40:25.806299 ==
2802 00:40:25.806346 Dram Type= 6, Freq= 0, CH_0, rank 1
2803 00:40:25.806394 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2804 00:40:25.806441 ==
2805 00:40:25.806488
2806 00:40:25.806535
2807 00:40:25.806581 TX Vref Scan disable
2808 00:40:25.806628 == TX Byte 0 ==
2809 00:40:25.806675 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2810 00:40:25.806723 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2811 00:40:25.806770 == TX Byte 1 ==
2812 00:40:25.806816 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
2813 00:40:25.806863 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
2814 00:40:25.806910 ==
2815 00:40:25.806957 Dram Type= 6, Freq= 0, CH_0, rank 1
2816 00:40:25.807004 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2817 00:40:25.807052 ==
2818 00:40:25.807099 TX Vref=22, minBit 9, minWin=25, winSum=422
2819 00:40:25.807146 TX Vref=24, minBit 9, minWin=25, winSum=426
2820 00:40:25.807193 TX Vref=26, minBit 8, minWin=25, winSum=427
2821 00:40:25.807240 TX Vref=28, minBit 8, minWin=26, winSum=433
2822 00:40:25.807287 TX Vref=30, minBit 8, minWin=25, winSum=432
2823 00:40:25.807334 TX Vref=32, minBit 8, minWin=25, winSum=434
2824 00:40:25.807382 [TxChooseVref] Worse bit 8, Min win 26, Win sum 433, Final Vref 28
2825 00:40:25.807429
2826 00:40:25.807475 Final TX Range 1 Vref 28
2827 00:40:25.807523
2828 00:40:25.807569 ==
2829 00:40:25.807616 Dram Type= 6, Freq= 0, CH_0, rank 1
2830 00:40:25.807662 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2831 00:40:25.807709 ==
2832 00:40:25.807756
2833 00:40:25.807803
2834 00:40:25.807849 TX Vref Scan disable
2835 00:40:25.807896 == TX Byte 0 ==
2836 00:40:25.807943 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2837 00:40:25.807989 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2838 00:40:25.808036 == TX Byte 1 ==
2839 00:40:25.808085 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
2840 00:40:25.808132 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
2841 00:40:25.808179
2842 00:40:25.808225 [DATLAT]
2843 00:40:25.808272 Freq=1200, CH0 RK1
2844 00:40:25.808319
2845 00:40:25.808365 DATLAT Default: 0xc
2846 00:40:25.808411 0, 0xFFFF, sum = 0
2847 00:40:25.808459 1, 0xFFFF, sum = 0
2848 00:40:25.808508 2, 0xFFFF, sum = 0
2849 00:40:25.808555 3, 0xFFFF, sum = 0
2850 00:40:25.808602 4, 0xFFFF, sum = 0
2851 00:40:25.808649 5, 0xFFFF, sum = 0
2852 00:40:25.808697 6, 0xFFFF, sum = 0
2853 00:40:25.808745 7, 0xFFFF, sum = 0
2854 00:40:25.808792 8, 0xFFFF, sum = 0
2855 00:40:25.808839 9, 0xFFFF, sum = 0
2856 00:40:25.808889 10, 0xFFFF, sum = 0
2857 00:40:25.808942 11, 0x0, sum = 1
2858 00:40:25.809033 12, 0x0, sum = 2
2859 00:40:25.809118 13, 0x0, sum = 3
2860 00:40:25.809195 14, 0x0, sum = 4
2861 00:40:25.809272 best_step = 12
2862 00:40:25.809346
2863 00:40:25.809421 ==
2864 00:40:25.809496 Dram Type= 6, Freq= 0, CH_0, rank 1
2865 00:40:25.809570 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2866 00:40:25.809622 ==
2867 00:40:25.809670 RX Vref Scan: 0
2868 00:40:25.809718
2869 00:40:25.809765 RX Vref 0 -> 0, step: 1
2870 00:40:25.809812
2871 00:40:25.810046 RX Delay -21 -> 252, step: 4
2872 00:40:25.810100 iDelay=195, Bit 0, Center 110 (39 ~ 182) 144
2873 00:40:25.810149 iDelay=195, Bit 1, Center 116 (43 ~ 190) 148
2874 00:40:25.810197 iDelay=195, Bit 2, Center 112 (43 ~ 182) 140
2875 00:40:25.810278 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
2876 00:40:25.810339 iDelay=195, Bit 4, Center 118 (47 ~ 190) 144
2877 00:40:25.810387 iDelay=195, Bit 5, Center 108 (39 ~ 178) 140
2878 00:40:25.810434 iDelay=195, Bit 6, Center 124 (55 ~ 194) 140
2879 00:40:25.810481 iDelay=195, Bit 7, Center 122 (51 ~ 194) 144
2880 00:40:25.810529 iDelay=195, Bit 8, Center 94 (31 ~ 158) 128
2881 00:40:25.810576 iDelay=195, Bit 9, Center 90 (27 ~ 154) 128
2882 00:40:25.810624 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
2883 00:40:25.810671 iDelay=195, Bit 11, Center 96 (35 ~ 158) 124
2884 00:40:25.810718 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
2885 00:40:25.810765 iDelay=195, Bit 13, Center 112 (47 ~ 178) 132
2886 00:40:25.810812 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
2887 00:40:25.810860 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
2888 00:40:25.810907 ==
2889 00:40:25.810956 Dram Type= 6, Freq= 0, CH_0, rank 1
2890 00:40:25.811003 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2891 00:40:25.811051 ==
2892 00:40:25.811098 DQS Delay:
2893 00:40:25.811144 DQS0 = 0, DQS1 = 0
2894 00:40:25.811191 DQM Delay:
2895 00:40:25.811237 DQM0 = 114, DQM1 = 105
2896 00:40:25.811284 DQ Delay:
2897 00:40:25.811331 DQ0 =110, DQ1 =116, DQ2 =112, DQ3 =108
2898 00:40:25.811379 DQ4 =118, DQ5 =108, DQ6 =124, DQ7 =122
2899 00:40:25.811425 DQ8 =94, DQ9 =90, DQ10 =110, DQ11 =96
2900 00:40:25.811473 DQ12 =112, DQ13 =112, DQ14 =118, DQ15 =114
2901 00:40:25.811520
2902 00:40:25.811567
2903 00:40:25.811613 [DQSOSCAuto] RK1, (LSB)MR18= 0x1717, (MSB)MR19= 0x404, tDQSOscB0 = 401 ps tDQSOscB1 = 401 ps
2904 00:40:25.811661 CH0 RK1: MR19=404, MR18=1717
2905 00:40:25.811709 CH0_RK1: MR19=0x404, MR18=0x1717, DQSOSC=401, MR23=63, INC=40, DEC=27
2906 00:40:25.811757 [RxdqsGatingPostProcess] freq 1200
2907 00:40:25.811804 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2908 00:40:25.811852 Pre-setting of DQS Precalculation
2909 00:40:25.811900 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
2910 00:40:25.811947 ==
2911 00:40:25.811994 Dram Type= 6, Freq= 0, CH_1, rank 0
2912 00:40:25.812041 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2913 00:40:25.812089 ==
2914 00:40:25.812136 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2915 00:40:25.812183 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2916 00:40:25.812231 [CA 0] Center 37 (7~68) winsize 62
2917 00:40:25.812277 [CA 1] Center 37 (7~68) winsize 62
2918 00:40:25.812324 [CA 2] Center 34 (4~65) winsize 62
2919 00:40:25.812371 [CA 3] Center 33 (3~64) winsize 62
2920 00:40:25.812417 [CA 4] Center 32 (2~63) winsize 62
2921 00:40:25.812463 [CA 5] Center 32 (1~63) winsize 63
2922 00:40:25.812509
2923 00:40:25.812555 [CmdBusTrainingLP45] Vref(ca) range 1: 39
2924 00:40:25.812602
2925 00:40:25.812649 [CATrainingPosCal] consider 1 rank data
2926 00:40:25.812696 u2DelayCellTimex100 = 270/100 ps
2927 00:40:25.812743 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2928 00:40:25.812790 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
2929 00:40:25.812837 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
2930 00:40:25.812884 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2931 00:40:25.812931 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
2932 00:40:25.812976 CA5 delay=32 (1~63),Diff = 0 PI (0 cell)
2933 00:40:25.813023
2934 00:40:25.813069 CA PerBit enable=1, Macro0, CA PI delay=32
2935 00:40:25.813116
2936 00:40:25.813164 [CBTSetCACLKResult] CA Dly = 32
2937 00:40:25.813210 CS Dly: 6 (0~37)
2938 00:40:25.813257 ==
2939 00:40:25.813303 Dram Type= 6, Freq= 0, CH_1, rank 1
2940 00:40:25.813351 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2941 00:40:25.813399 ==
2942 00:40:25.813446 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2943 00:40:25.813493 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2944 00:40:25.813541 [CA 0] Center 37 (7~68) winsize 62
2945 00:40:25.813588 [CA 1] Center 37 (7~68) winsize 62
2946 00:40:25.813637 [CA 2] Center 33 (3~64) winsize 62
2947 00:40:25.813684 [CA 3] Center 33 (3~64) winsize 62
2948 00:40:25.813730 [CA 4] Center 32 (2~63) winsize 62
2949 00:40:25.813777 [CA 5] Center 32 (1~63) winsize 63
2950 00:40:25.813824
2951 00:40:25.813870 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2952 00:40:25.813917
2953 00:40:25.813964 [CATrainingPosCal] consider 2 rank data
2954 00:40:25.814011 u2DelayCellTimex100 = 270/100 ps
2955 00:40:25.814058 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2956 00:40:25.814105 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
2957 00:40:25.814151 CA2 delay=34 (4~64),Diff = 2 PI (9 cell)
2958 00:40:25.814198 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2959 00:40:25.814284 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
2960 00:40:25.814345 CA5 delay=32 (1~63),Diff = 0 PI (0 cell)
2961 00:40:25.814391
2962 00:40:25.814437 CA PerBit enable=1, Macro0, CA PI delay=32
2963 00:40:25.814484
2964 00:40:25.814531 [CBTSetCACLKResult] CA Dly = 32
2965 00:40:25.814578 CS Dly: 6 (0~38)
2966 00:40:25.814624
2967 00:40:25.814671 ----->DramcWriteLeveling(PI) begin...
2968 00:40:25.944051 ==
2969 00:40:25.944523 Dram Type= 6, Freq= 0, CH_1, rank 0
2970 00:40:25.944862 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2971 00:40:25.945168 ==
2972 00:40:25.945457 Write leveling (Byte 0): 23 => 23
2973 00:40:25.945740 Write leveling (Byte 1): 20 => 20
2974 00:40:25.946016 DramcWriteLeveling(PI) end<-----
2975 00:40:25.946321
2976 00:40:25.946596 ==
2977 00:40:25.946868 Dram Type= 6, Freq= 0, CH_1, rank 0
2978 00:40:25.947118 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2979 00:40:25.947368 ==
2980 00:40:25.947612 [Gating] SW mode calibration
2981 00:40:25.947857 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2982 00:40:25.948106 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2983 00:40:25.948356 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2984 00:40:25.948601 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2985 00:40:25.948846 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2986 00:40:25.949090 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2987 00:40:25.949336 0 11 16 | B1->B0 | 3030 2c2c | 0 0 | (0 0) (1 0)
2988 00:40:25.949943 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2989 00:40:25.950261 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2990 00:40:25.950528 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2991 00:40:25.950774 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2992 00:40:25.951025 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2993 00:40:25.951274 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2994 00:40:25.951522 0 12 12 | B1->B0 | 2525 3131 | 0 0 | (0 0) (0 0)
2995 00:40:25.951770 0 12 16 | B1->B0 | 3131 4545 | 1 0 | (0 0) (0 0)
2996 00:40:25.952015 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2997 00:40:25.952259 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2998 00:40:25.952517 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2999 00:40:25.952762 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3000 00:40:25.953006 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3001 00:40:25.953249 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3002 00:40:25.953492 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3003 00:40:25.953739 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3004 00:40:25.953985 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3005 00:40:25.954263 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3006 00:40:25.954525 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3007 00:40:25.954770 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3008 00:40:25.955013 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3009 00:40:25.955252 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3010 00:40:25.955493 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3011 00:40:25.955734 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3012 00:40:25.955977 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3013 00:40:25.956219 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3014 00:40:25.956460 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3015 00:40:25.956704 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3016 00:40:25.956947 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3017 00:40:25.957190 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3018 00:40:25.957433 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3019 00:40:25.957679 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3020 00:40:25.957926 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3021 00:40:25.958171 Total UI for P1: 0, mck2ui 16
3022 00:40:25.958441 best dqsien dly found for B0: ( 0, 15, 14)
3023 00:40:25.958687 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3024 00:40:25.958930 Total UI for P1: 0, mck2ui 16
3025 00:40:25.959180 best dqsien dly found for B1: ( 0, 15, 18)
3026 00:40:25.959425 best DQS0 dly(MCK, UI, PI) = (0, 15, 14)
3027 00:40:25.959669 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
3028 00:40:25.959911
3029 00:40:25.960155 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 14)
3030 00:40:25.960401 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
3031 00:40:25.960646 [Gating] SW calibration Done
3032 00:40:25.960889 ==
3033 00:40:25.961133 Dram Type= 6, Freq= 0, CH_1, rank 0
3034 00:40:25.961381 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3035 00:40:25.961628 ==
3036 00:40:25.961869 RX Vref Scan: 0
3037 00:40:25.962108
3038 00:40:25.962371 RX Vref 0 -> 0, step: 1
3039 00:40:25.962616
3040 00:40:25.962857 RX Delay -40 -> 252, step: 8
3041 00:40:25.963100 iDelay=200, Bit 0, Center 119 (40 ~ 199) 160
3042 00:40:25.963343 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3043 00:40:25.963585 iDelay=200, Bit 2, Center 107 (32 ~ 183) 152
3044 00:40:25.963829 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3045 00:40:25.964070 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3046 00:40:25.964311 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3047 00:40:25.964551 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3048 00:40:25.964795 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3049 00:40:25.965038 iDelay=200, Bit 8, Center 87 (16 ~ 159) 144
3050 00:40:25.965280 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3051 00:40:25.965524 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
3052 00:40:25.965766 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3053 00:40:25.966012 iDelay=200, Bit 12, Center 115 (40 ~ 191) 152
3054 00:40:25.966277 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3055 00:40:25.966526 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3056 00:40:25.966772 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3057 00:40:25.967016 ==
3058 00:40:25.967264 Dram Type= 6, Freq= 0, CH_1, rank 0
3059 00:40:25.967511 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3060 00:40:25.967759 ==
3061 00:40:25.968004 DQS Delay:
3062 00:40:25.968250 DQS0 = 0, DQS1 = 0
3063 00:40:25.968495 DQM Delay:
3064 00:40:25.968735 DQM0 = 115, DQM1 = 108
3065 00:40:25.968979 DQ Delay:
3066 00:40:25.969224 DQ0 =119, DQ1 =107, DQ2 =107, DQ3 =115
3067 00:40:25.969470 DQ4 =115, DQ5 =123, DQ6 =123, DQ7 =115
3068 00:40:25.969717 DQ8 =87, DQ9 =99, DQ10 =107, DQ11 =103
3069 00:40:25.969961 DQ12 =115, DQ13 =119, DQ14 =119, DQ15 =119
3070 00:40:25.970205
3071 00:40:25.970465
3072 00:40:25.970706 ==
3073 00:40:25.970950 Dram Type= 6, Freq= 0, CH_1, rank 0
3074 00:40:25.971196 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3075 00:40:25.971439 ==
3076 00:40:25.971686
3077 00:40:25.971929
3078 00:40:25.972173 TX Vref Scan disable
3079 00:40:25.972417 == TX Byte 0 ==
3080 00:40:25.972663 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
3081 00:40:25.972909 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
3082 00:40:25.973156 == TX Byte 1 ==
3083 00:40:25.973401 Update DQ dly =836 (3 ,1, 36) DQ OEN =(2 ,6)
3084 00:40:25.973664 Update DQM dly =836 (3 ,1, 36) DQM OEN =(2 ,6)
3085 00:40:25.973837 ==
3086 00:40:25.974010 Dram Type= 6, Freq= 0, CH_1, rank 0
3087 00:40:25.974185 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3088 00:40:25.974435 ==
3089 00:40:25.974614 TX Vref=22, minBit 9, minWin=25, winSum=418
3090 00:40:25.974793 TX Vref=24, minBit 9, minWin=25, winSum=419
3091 00:40:25.974970 TX Vref=26, minBit 8, minWin=26, winSum=430
3092 00:40:25.975147 TX Vref=28, minBit 9, minWin=25, winSum=433
3093 00:40:25.975323 TX Vref=30, minBit 9, minWin=25, winSum=432
3094 00:40:25.975497 TX Vref=32, minBit 9, minWin=26, winSum=435
3095 00:40:25.975958 [TxChooseVref] Worse bit 9, Min win 26, Win sum 435, Final Vref 32
3096 00:40:25.976155
3097 00:40:25.976335 Final TX Range 1 Vref 32
3098 00:40:25.976511
3099 00:40:25.976684 ==
3100 00:40:25.976861 Dram Type= 6, Freq= 0, CH_1, rank 0
3101 00:40:25.977037 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3102 00:40:25.977215 ==
3103 00:40:25.977389
3104 00:40:25.977564
3105 00:40:25.977737 TX Vref Scan disable
3106 00:40:25.977914 == TX Byte 0 ==
3107 00:40:25.978089 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
3108 00:40:25.978296 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
3109 00:40:25.978478 == TX Byte 1 ==
3110 00:40:25.978654 Update DQ dly =836 (3 ,1, 36) DQ OEN =(2 ,6)
3111 00:40:25.978802 Update DQM dly =836 (3 ,1, 36) DQM OEN =(2 ,6)
3112 00:40:25.978934
3113 00:40:25.979064 [DATLAT]
3114 00:40:25.979194 Freq=1200, CH1 RK0
3115 00:40:25.979327
3116 00:40:25.979457 DATLAT Default: 0xd
3117 00:40:25.979588 0, 0xFFFF, sum = 0
3118 00:40:25.979724 1, 0xFFFF, sum = 0
3119 00:40:25.979858 2, 0xFFFF, sum = 0
3120 00:40:25.979992 3, 0xFFFF, sum = 0
3121 00:40:25.980124 4, 0xFFFF, sum = 0
3122 00:40:25.980257 5, 0xFFFF, sum = 0
3123 00:40:25.980390 6, 0xFFFF, sum = 0
3124 00:40:25.980524 7, 0xFFFF, sum = 0
3125 00:40:25.980656 8, 0xFFFF, sum = 0
3126 00:40:25.980788 9, 0xFFFF, sum = 0
3127 00:40:25.980919 10, 0xFFFF, sum = 0
3128 00:40:25.981048 11, 0x0, sum = 1
3129 00:40:25.981179 12, 0x0, sum = 2
3130 00:40:25.981311 13, 0x0, sum = 3
3131 00:40:25.981445 14, 0x0, sum = 4
3132 00:40:25.981583 best_step = 12
3133 00:40:25.981713
3134 00:40:25.981844 ==
3135 00:40:25.981976 Dram Type= 6, Freq= 0, CH_1, rank 0
3136 00:40:25.982109 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3137 00:40:25.982253 ==
3138 00:40:25.982407 RX Vref Scan: 1
3139 00:40:25.982547
3140 00:40:25.982679 Set Vref Range= 32 -> 127
3141 00:40:25.982810
3142 00:40:25.982942 RX Vref 32 -> 127, step: 1
3143 00:40:25.983072
3144 00:40:25.983202 RX Delay -29 -> 252, step: 4
3145 00:40:25.983333
3146 00:40:25.983464 Set Vref, RX VrefLevel [Byte0]: 32
3147 00:40:25.983597 [Byte1]: 32
3148 00:40:25.983725
3149 00:40:25.983830 Set Vref, RX VrefLevel [Byte0]: 33
3150 00:40:25.983934 [Byte1]: 33
3151 00:40:25.984040
3152 00:40:25.984145 Set Vref, RX VrefLevel [Byte0]: 34
3153 00:40:25.984249 [Byte1]: 34
3154 00:40:25.984354
3155 00:40:25.984460 Set Vref, RX VrefLevel [Byte0]: 35
3156 00:40:25.984565 [Byte1]: 35
3157 00:40:25.984672
3158 00:40:25.984776 Set Vref, RX VrefLevel [Byte0]: 36
3159 00:40:25.984882 [Byte1]: 36
3160 00:40:25.984989
3161 00:40:25.985095 Set Vref, RX VrefLevel [Byte0]: 37
3162 00:40:25.985201 [Byte1]: 37
3163 00:40:25.985306
3164 00:40:25.985411 Set Vref, RX VrefLevel [Byte0]: 38
3165 00:40:25.985515 [Byte1]: 38
3166 00:40:25.985620
3167 00:40:25.985723 Set Vref, RX VrefLevel [Byte0]: 39
3168 00:40:25.985828 [Byte1]: 39
3169 00:40:25.985933
3170 00:40:25.986036 Set Vref, RX VrefLevel [Byte0]: 40
3171 00:40:25.986143 [Byte1]: 40
3172 00:40:25.986257
3173 00:40:25.986364 Set Vref, RX VrefLevel [Byte0]: 41
3174 00:40:25.986470 [Byte1]: 41
3175 00:40:25.986577
3176 00:40:25.986682 Set Vref, RX VrefLevel [Byte0]: 42
3177 00:40:25.986788 [Byte1]: 42
3178 00:40:25.986891
3179 00:40:25.986996 Set Vref, RX VrefLevel [Byte0]: 43
3180 00:40:25.987101 [Byte1]: 43
3181 00:40:25.987206
3182 00:40:25.987312 Set Vref, RX VrefLevel [Byte0]: 44
3183 00:40:25.987419 [Byte1]: 44
3184 00:40:25.987523
3185 00:40:25.987628 Set Vref, RX VrefLevel [Byte0]: 45
3186 00:40:25.987734 [Byte1]: 45
3187 00:40:25.987840
3188 00:40:25.987944 Set Vref, RX VrefLevel [Byte0]: 46
3189 00:40:25.988049 [Byte1]: 46
3190 00:40:25.988154
3191 00:40:25.988291 Set Vref, RX VrefLevel [Byte0]: 47
3192 00:40:25.988401 [Byte1]: 47
3193 00:40:25.988508
3194 00:40:25.988614 Set Vref, RX VrefLevel [Byte0]: 48
3195 00:40:25.988728 [Byte1]: 48
3196 00:40:25.988816
3197 00:40:25.988904 Set Vref, RX VrefLevel [Byte0]: 49
3198 00:40:25.988993 [Byte1]: 49
3199 00:40:25.989081
3200 00:40:25.989168 Set Vref, RX VrefLevel [Byte0]: 50
3201 00:40:25.989257 [Byte1]: 50
3202 00:40:25.989346
3203 00:40:25.989433 Set Vref, RX VrefLevel [Byte0]: 51
3204 00:40:25.989522 [Byte1]: 51
3205 00:40:25.989610
3206 00:40:25.989698 Set Vref, RX VrefLevel [Byte0]: 52
3207 00:40:25.989787 [Byte1]: 52
3208 00:40:25.989875
3209 00:40:25.989963 Set Vref, RX VrefLevel [Byte0]: 53
3210 00:40:25.990051 [Byte1]: 53
3211 00:40:25.990140
3212 00:40:25.990237 Set Vref, RX VrefLevel [Byte0]: 54
3213 00:40:25.990327 [Byte1]: 54
3214 00:40:25.990420
3215 00:40:25.990508 Set Vref, RX VrefLevel [Byte0]: 55
3216 00:40:25.990597 [Byte1]: 55
3217 00:40:25.990686
3218 00:40:25.990774 Set Vref, RX VrefLevel [Byte0]: 56
3219 00:40:25.990861 [Byte1]: 56
3220 00:40:25.990949
3221 00:40:25.991036 Set Vref, RX VrefLevel [Byte0]: 57
3222 00:40:25.991125 [Byte1]: 57
3223 00:40:25.991213
3224 00:40:25.991302 Set Vref, RX VrefLevel [Byte0]: 58
3225 00:40:25.991390 [Byte1]: 58
3226 00:40:25.991477
3227 00:40:25.991565 Set Vref, RX VrefLevel [Byte0]: 59
3228 00:40:25.991653 [Byte1]: 59
3229 00:40:25.991740
3230 00:40:25.991827 Set Vref, RX VrefLevel [Byte0]: 60
3231 00:40:25.991915 [Byte1]: 60
3232 00:40:25.992003
3233 00:40:25.992091 Set Vref, RX VrefLevel [Byte0]: 61
3234 00:40:25.992179 [Byte1]: 61
3235 00:40:25.992266
3236 00:40:25.992388 Set Vref, RX VrefLevel [Byte0]: 62
3237 00:40:25.992482 [Byte1]: 62
3238 00:40:25.992571
3239 00:40:25.992660 Set Vref, RX VrefLevel [Byte0]: 63
3240 00:40:25.992749 [Byte1]: 63
3241 00:40:25.992838
3242 00:40:25.992928 Set Vref, RX VrefLevel [Byte0]: 64
3243 00:40:25.993017 [Byte1]: 64
3244 00:40:25.993106
3245 00:40:25.993194 Set Vref, RX VrefLevel [Byte0]: 65
3246 00:40:25.993283 [Byte1]: 65
3247 00:40:25.993372
3248 00:40:25.993460 Set Vref, RX VrefLevel [Byte0]: 66
3249 00:40:25.993548 [Byte1]: 66
3250 00:40:25.993635
3251 00:40:25.993728 Final RX Vref Byte 0 = 57 to rank0
3252 00:40:25.993806 Final RX Vref Byte 1 = 50 to rank0
3253 00:40:25.993884 Final RX Vref Byte 0 = 57 to rank1
3254 00:40:25.993959 Final RX Vref Byte 1 = 50 to rank1==
3255 00:40:25.994035 Dram Type= 6, Freq= 0, CH_1, rank 0
3256 00:40:25.994112 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3257 00:40:25.994189 ==
3258 00:40:25.994275 DQS Delay:
3259 00:40:25.994352 DQS0 = 0, DQS1 = 0
3260 00:40:25.994428 DQM Delay:
3261 00:40:25.994504 DQM0 = 115, DQM1 = 105
3262 00:40:25.994580 DQ Delay:
3263 00:40:25.994656 DQ0 =118, DQ1 =110, DQ2 =106, DQ3 =114
3264 00:40:25.994731 DQ4 =114, DQ5 =124, DQ6 =120, DQ7 =114
3265 00:40:25.994807 DQ8 =86, DQ9 =94, DQ10 =108, DQ11 =96
3266 00:40:25.995093 DQ12 =112, DQ13 =114, DQ14 =114, DQ15 =116
3267 00:40:25.995179
3268 00:40:25.995257
3269 00:40:25.995335 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a1a, (MSB)MR19= 0x404, tDQSOscB0 = 400 ps tDQSOscB1 = 400 ps
3270 00:40:25.995414 CH1 RK0: MR19=404, MR18=1A1A
3271 00:40:25.995491 CH1_RK0: MR19=0x404, MR18=0x1A1A, DQSOSC=400, MR23=63, INC=40, DEC=27
3272 00:40:25.995569
3273 00:40:25.995645 ----->DramcWriteLeveling(PI) begin...
3274 00:40:25.995725 ==
3275 00:40:25.995801 Dram Type= 6, Freq= 0, CH_1, rank 1
3276 00:40:25.995878 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3277 00:40:25.995957 ==
3278 00:40:25.996034 Write leveling (Byte 0): 22 => 22
3279 00:40:25.996111 Write leveling (Byte 1): 20 => 20
3280 00:40:25.996188 DramcWriteLeveling(PI) end<-----
3281 00:40:25.996264
3282 00:40:25.996338 ==
3283 00:40:25.996415 Dram Type= 6, Freq= 0, CH_1, rank 1
3284 00:40:25.996492 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3285 00:40:25.996568 ==
3286 00:40:25.996645 [Gating] SW mode calibration
3287 00:40:25.996723 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3288 00:40:25.996801 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
3289 00:40:25.996878 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3290 00:40:25.996955 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3291 00:40:25.997031 0 11 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
3292 00:40:25.997108 0 11 12 | B1->B0 | 3434 2a2a | 1 1 | (1 0) (1 0)
3293 00:40:25.997184 0 11 16 | B1->B0 | 2e2e 2323 | 0 0 | (1 0) (0 0)
3294 00:40:25.997260 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3295 00:40:25.997338 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3296 00:40:25.997414 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3297 00:40:25.997491 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3298 00:40:25.997567 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3299 00:40:25.997643 0 12 8 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
3300 00:40:25.997721 0 12 12 | B1->B0 | 2323 3e3e | 0 1 | (0 0) (0 0)
3301 00:40:25.997798 0 12 16 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0)
3302 00:40:25.997873 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3303 00:40:25.997948 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3304 00:40:25.998024 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3305 00:40:25.998101 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3306 00:40:25.998178 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3307 00:40:25.998265 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3308 00:40:25.998342 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3309 00:40:25.998419 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3310 00:40:25.998495 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3311 00:40:25.998571 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3312 00:40:25.998647 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3313 00:40:25.998732 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3314 00:40:25.998800 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3315 00:40:25.998866 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3316 00:40:25.998934 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3317 00:40:25.999000 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3318 00:40:25.999067 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3319 00:40:25.999133 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3320 00:40:25.999199 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3321 00:40:25.999266 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3322 00:40:25.999333 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3323 00:40:25.999399 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3324 00:40:25.999466 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3325 00:40:25.999532 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3326 00:40:25.999599 Total UI for P1: 0, mck2ui 16
3327 00:40:25.999667 best dqsien dly found for B0: ( 0, 15, 10)
3328 00:40:25.999735 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3329 00:40:25.999802 Total UI for P1: 0, mck2ui 16
3330 00:40:25.999869 best dqsien dly found for B1: ( 0, 15, 16)
3331 00:40:25.999936 best DQS0 dly(MCK, UI, PI) = (0, 15, 10)
3332 00:40:26.000003 best DQS1 dly(MCK, UI, PI) = (0, 15, 16)
3333 00:40:26.000069
3334 00:40:26.000134 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 10)
3335 00:40:26.000200 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 16)
3336 00:40:26.000267 [Gating] SW calibration Done
3337 00:40:26.000344 ==
3338 00:40:26.000411 Dram Type= 6, Freq= 0, CH_1, rank 1
3339 00:40:26.000477 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3340 00:40:26.000544 ==
3341 00:40:26.000610 RX Vref Scan: 0
3342 00:40:26.000676
3343 00:40:26.000743 RX Vref 0 -> 0, step: 1
3344 00:40:26.000809
3345 00:40:26.000875 RX Delay -40 -> 252, step: 8
3346 00:40:26.000942 iDelay=208, Bit 0, Center 119 (48 ~ 191) 144
3347 00:40:26.001009 iDelay=208, Bit 1, Center 115 (40 ~ 191) 152
3348 00:40:26.001075 iDelay=208, Bit 2, Center 103 (32 ~ 175) 144
3349 00:40:26.001141 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3350 00:40:26.001207 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152
3351 00:40:26.001274 iDelay=208, Bit 5, Center 127 (48 ~ 207) 160
3352 00:40:26.001340 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3353 00:40:26.001407 iDelay=208, Bit 7, Center 115 (40 ~ 191) 152
3354 00:40:26.001472 iDelay=208, Bit 8, Center 91 (16 ~ 167) 152
3355 00:40:26.001538 iDelay=208, Bit 9, Center 91 (16 ~ 167) 152
3356 00:40:26.001605 iDelay=208, Bit 10, Center 107 (32 ~ 183) 152
3357 00:40:26.001671 iDelay=208, Bit 11, Center 99 (24 ~ 175) 152
3358 00:40:26.001737 iDelay=208, Bit 12, Center 115 (40 ~ 191) 152
3359 00:40:26.001803 iDelay=208, Bit 13, Center 115 (40 ~ 191) 152
3360 00:40:26.001870 iDelay=208, Bit 14, Center 115 (40 ~ 191) 152
3361 00:40:26.001937 iDelay=208, Bit 15, Center 111 (40 ~ 183) 144
3362 00:40:26.002002 ==
3363 00:40:26.002069 Dram Type= 6, Freq= 0, CH_1, rank 1
3364 00:40:26.002137 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3365 00:40:26.002204 ==
3366 00:40:26.002280 DQS Delay:
3367 00:40:26.002353 DQS0 = 0, DQS1 = 0
3368 00:40:26.002420 DQM Delay:
3369 00:40:26.002487 DQM0 = 116, DQM1 = 105
3370 00:40:26.002556 DQ Delay:
3371 00:40:26.002826 DQ0 =119, DQ1 =115, DQ2 =103, DQ3 =115
3372 00:40:26.002904 DQ4 =115, DQ5 =127, DQ6 =123, DQ7 =115
3373 00:40:26.002974 DQ8 =91, DQ9 =91, DQ10 =107, DQ11 =99
3374 00:40:26.003040 DQ12 =115, DQ13 =115, DQ14 =115, DQ15 =111
3375 00:40:26.003107
3376 00:40:26.003174
3377 00:40:26.003241 ==
3378 00:40:26.003308 Dram Type= 6, Freq= 0, CH_1, rank 1
3379 00:40:26.003376 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3380 00:40:26.003444 ==
3381 00:40:26.003511
3382 00:40:26.003577
3383 00:40:26.003643 TX Vref Scan disable
3384 00:40:26.003717 == TX Byte 0 ==
3385 00:40:26.003775 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3386 00:40:26.003834 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3387 00:40:26.003894 == TX Byte 1 ==
3388 00:40:26.003952 Update DQ dly =836 (3 ,1, 36) DQ OEN =(2 ,6)
3389 00:40:26.004011 Update DQM dly =836 (3 ,1, 36) DQM OEN =(2 ,6)
3390 00:40:26.004071 ==
3391 00:40:26.004140 Dram Type= 6, Freq= 0, CH_1, rank 1
3392 00:40:26.004211 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3393 00:40:26.004271 ==
3394 00:40:26.004331 TX Vref=22, minBit 9, minWin=25, winSum=420
3395 00:40:26.004391 TX Vref=24, minBit 3, minWin=26, winSum=429
3396 00:40:26.004451 TX Vref=26, minBit 9, minWin=25, winSum=425
3397 00:40:26.004511 TX Vref=28, minBit 3, minWin=26, winSum=429
3398 00:40:26.004570 TX Vref=30, minBit 9, minWin=26, winSum=433
3399 00:40:26.004630 TX Vref=32, minBit 0, minWin=26, winSum=429
3400 00:40:26.004689 [TxChooseVref] Worse bit 9, Min win 26, Win sum 433, Final Vref 30
3401 00:40:26.004749
3402 00:40:26.004808 Final TX Range 1 Vref 30
3403 00:40:26.004868
3404 00:40:26.004926 ==
3405 00:40:26.004986 Dram Type= 6, Freq= 0, CH_1, rank 1
3406 00:40:26.005045 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3407 00:40:26.005104 ==
3408 00:40:26.005163
3409 00:40:26.005222
3410 00:40:26.005280 TX Vref Scan disable
3411 00:40:26.005339 == TX Byte 0 ==
3412 00:40:26.005400 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3413 00:40:26.005460 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3414 00:40:26.005520 == TX Byte 1 ==
3415 00:40:26.005579 Update DQ dly =836 (3 ,1, 36) DQ OEN =(2 ,6)
3416 00:40:26.005638 Update DQM dly =836 (3 ,1, 36) DQM OEN =(2 ,6)
3417 00:40:26.005697
3418 00:40:26.005756 [DATLAT]
3419 00:40:26.005815 Freq=1200, CH1 RK1
3420 00:40:26.005874
3421 00:40:26.005933 DATLAT Default: 0xc
3422 00:40:26.005991 0, 0xFFFF, sum = 0
3423 00:40:26.006051 1, 0xFFFF, sum = 0
3424 00:40:26.006110 2, 0xFFFF, sum = 0
3425 00:40:26.006170 3, 0xFFFF, sum = 0
3426 00:40:26.006241 4, 0xFFFF, sum = 0
3427 00:40:26.006307 5, 0xFFFF, sum = 0
3428 00:40:26.006369 6, 0xFFFF, sum = 0
3429 00:40:26.006429 7, 0xFFFF, sum = 0
3430 00:40:26.006489 8, 0xFFFF, sum = 0
3431 00:40:26.006549 9, 0xFFFF, sum = 0
3432 00:40:26.006608 10, 0xFFFF, sum = 0
3433 00:40:26.006668 11, 0x0, sum = 1
3434 00:40:26.006727 12, 0x0, sum = 2
3435 00:40:26.006786 13, 0x0, sum = 3
3436 00:40:26.006845 14, 0x0, sum = 4
3437 00:40:26.006905 best_step = 12
3438 00:40:26.006963
3439 00:40:26.007022 ==
3440 00:40:26.007082 Dram Type= 6, Freq= 0, CH_1, rank 1
3441 00:40:26.007141 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3442 00:40:26.007201 ==
3443 00:40:26.007260 RX Vref Scan: 0
3444 00:40:26.007319
3445 00:40:26.007379 RX Vref 0 -> 0, step: 1
3446 00:40:26.007439
3447 00:40:26.007497 RX Delay -29 -> 252, step: 4
3448 00:40:26.007556 iDelay=199, Bit 0, Center 114 (43 ~ 186) 144
3449 00:40:26.007616 iDelay=199, Bit 1, Center 110 (39 ~ 182) 144
3450 00:40:26.007674 iDelay=199, Bit 2, Center 106 (39 ~ 174) 136
3451 00:40:26.007732 iDelay=199, Bit 3, Center 112 (43 ~ 182) 140
3452 00:40:26.007790 iDelay=199, Bit 4, Center 116 (47 ~ 186) 140
3453 00:40:26.007849 iDelay=199, Bit 5, Center 124 (51 ~ 198) 148
3454 00:40:26.007909 iDelay=199, Bit 6, Center 122 (51 ~ 194) 144
3455 00:40:26.007969 iDelay=199, Bit 7, Center 112 (43 ~ 182) 140
3456 00:40:26.008028 iDelay=199, Bit 8, Center 86 (19 ~ 154) 136
3457 00:40:26.008087 iDelay=199, Bit 9, Center 92 (27 ~ 158) 132
3458 00:40:26.008146 iDelay=199, Bit 10, Center 108 (43 ~ 174) 132
3459 00:40:26.008205 iDelay=199, Bit 11, Center 98 (31 ~ 166) 136
3460 00:40:26.008264 iDelay=199, Bit 12, Center 112 (43 ~ 182) 140
3461 00:40:26.008322 iDelay=199, Bit 13, Center 110 (43 ~ 178) 136
3462 00:40:26.008380 iDelay=199, Bit 14, Center 114 (43 ~ 186) 144
3463 00:40:26.008439 iDelay=199, Bit 15, Center 110 (43 ~ 178) 136
3464 00:40:26.008497 ==
3465 00:40:26.008556 Dram Type= 6, Freq= 0, CH_1, rank 1
3466 00:40:26.008615 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3467 00:40:26.008674 ==
3468 00:40:26.008743 DQS Delay:
3469 00:40:26.008796 DQS0 = 0, DQS1 = 0
3470 00:40:26.008859 DQM Delay:
3471 00:40:26.008917 DQM0 = 114, DQM1 = 103
3472 00:40:26.008971 DQ Delay:
3473 00:40:26.009025 DQ0 =114, DQ1 =110, DQ2 =106, DQ3 =112
3474 00:40:26.009079 DQ4 =116, DQ5 =124, DQ6 =122, DQ7 =112
3475 00:40:26.009132 DQ8 =86, DQ9 =92, DQ10 =108, DQ11 =98
3476 00:40:26.009185 DQ12 =112, DQ13 =110, DQ14 =114, DQ15 =110
3477 00:40:26.009253
3478 00:40:26.009345
3479 00:40:26.009435 [DQSOSCAuto] RK1, (LSB)MR18= 0xe0e, (MSB)MR19= 0x404, tDQSOscB0 = 404 ps tDQSOscB1 = 404 ps
3480 00:40:26.009522 CH1 RK1: MR19=404, MR18=E0E
3481 00:40:26.009608 CH1_RK1: MR19=0x404, MR18=0xE0E, DQSOSC=404, MR23=63, INC=40, DEC=26
3482 00:40:26.009698 [RxdqsGatingPostProcess] freq 1200
3483 00:40:26.009801 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
3484 00:40:26.009869 Pre-setting of DQS Precalculation
3485 00:40:26.009924 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
3486 00:40:26.009979 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3487 00:40:26.010033 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3488 00:40:26.010088
3489 00:40:26.010142
3490 00:40:26.010196 [Calibration Summary] 2400 Mbps
3491 00:40:26.010263 CH 0, Rank 0
3492 00:40:26.010323 SW Impedance : PASS
3493 00:40:26.010379 DUTY Scan : NO K
3494 00:40:26.010432 ZQ Calibration : PASS
3495 00:40:26.010484 Jitter Meter : NO K
3496 00:40:26.010539 CBT Training : PASS
3497 00:40:26.010592 Write leveling : PASS
3498 00:40:26.010646 RX DQS gating : PASS
3499 00:40:26.010699 RX DQ/DQS(RDDQC) : PASS
3500 00:40:26.010752 TX DQ/DQS : PASS
3501 00:40:26.010804 RX DATLAT : PASS
3502 00:40:26.010857 RX DQ/DQS(Engine): PASS
3503 00:40:26.010910 TX OE : NO K
3504 00:40:26.010963 All Pass.
3505 00:40:26.011016
3506 00:40:26.011069 CH 0, Rank 1
3507 00:40:26.011122 SW Impedance : PASS
3508 00:40:26.011176 DUTY Scan : NO K
3509 00:40:26.011229 ZQ Calibration : PASS
3510 00:40:26.011282 Jitter Meter : NO K
3511 00:40:26.011334 CBT Training : PASS
3512 00:40:26.011387 Write leveling : PASS
3513 00:40:26.011440 RX DQS gating : PASS
3514 00:40:26.011492 RX DQ/DQS(RDDQC) : PASS
3515 00:40:26.011741 TX DQ/DQS : PASS
3516 00:40:26.011802 RX DATLAT : PASS
3517 00:40:26.011856 RX DQ/DQS(Engine): PASS
3518 00:40:26.011909 TX OE : NO K
3519 00:40:26.011962 All Pass.
3520 00:40:26.012019
3521 00:40:26.012072 CH 1, Rank 0
3522 00:40:26.012125 SW Impedance : PASS
3523 00:40:26.012178 DUTY Scan : NO K
3524 00:40:26.012231 ZQ Calibration : PASS
3525 00:40:26.012284 Jitter Meter : NO K
3526 00:40:26.012343 CBT Training : PASS
3527 00:40:26.012397 Write leveling : PASS
3528 00:40:26.012450 RX DQS gating : PASS
3529 00:40:26.012503 RX DQ/DQS(RDDQC) : PASS
3530 00:40:26.012556 TX DQ/DQS : PASS
3531 00:40:26.012609 RX DATLAT : PASS
3532 00:40:26.012662 RX DQ/DQS(Engine): PASS
3533 00:40:26.012714 TX OE : NO K
3534 00:40:26.012767 All Pass.
3535 00:40:26.012823
3536 00:40:26.012884 CH 1, Rank 1
3537 00:40:26.012945 SW Impedance : PASS
3538 00:40:26.013006 DUTY Scan : NO K
3539 00:40:26.013065 ZQ Calibration : PASS
3540 00:40:26.013124 Jitter Meter : NO K
3541 00:40:26.013182 CBT Training : PASS
3542 00:40:26.013241 Write leveling : PASS
3543 00:40:26.013299 RX DQS gating : PASS
3544 00:40:26.013357 RX DQ/DQS(RDDQC) : PASS
3545 00:40:26.013415 TX DQ/DQS : PASS
3546 00:40:26.013474 RX DATLAT : PASS
3547 00:40:26.013533 RX DQ/DQS(Engine): PASS
3548 00:40:26.013591 TX OE : NO K
3549 00:40:26.013649 All Pass.
3550 00:40:26.013717
3551 00:40:26.013767 DramC Write-DBI off
3552 00:40:26.013817 PER_BANK_REFRESH: Hybrid Mode
3553 00:40:26.013867 TX_TRACKING: ON
3554 00:40:26.013915 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3555 00:40:26.013965 [FAST_K] Save calibration result to emmc
3556 00:40:26.014013 dramc_set_vcore_voltage set vcore to 650000
3557 00:40:26.014062 Read voltage for 600, 5
3558 00:40:26.014110 Vio18 = 0
3559 00:40:26.014159 Vcore = 650000
3560 00:40:26.014207 Vdram = 0
3561 00:40:26.014266 Vddq = 0
3562 00:40:26.014315 Vmddr = 0
3563 00:40:26.014362 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3564 00:40:26.014411 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3565 00:40:26.014460 MEM_TYPE=3, freq_sel=19
3566 00:40:26.014509 sv_algorithm_assistance_LP4_1600
3567 00:40:26.014558 ============ PULL DRAM RESETB DOWN ============
3568 00:40:26.014608 ========== PULL DRAM RESETB DOWN end =========
3569 00:40:26.014657 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3570 00:40:26.014705 ===================================
3571 00:40:26.014754 LPDDR4 DRAM CONFIGURATION
3572 00:40:26.014802 ===================================
3573 00:40:26.014850 EX_ROW_EN[0] = 0x0
3574 00:40:26.014898 EX_ROW_EN[1] = 0x0
3575 00:40:26.014946 LP4Y_EN = 0x0
3576 00:40:26.014993 WORK_FSP = 0x0
3577 00:40:26.015041 WL = 0x2
3578 00:40:26.015090 RL = 0x2
3579 00:40:26.015138 BL = 0x2
3580 00:40:26.015186 RPST = 0x0
3581 00:40:26.015234 RD_PRE = 0x0
3582 00:40:26.015282 WR_PRE = 0x1
3583 00:40:26.015329 WR_PST = 0x0
3584 00:40:26.015377 DBI_WR = 0x0
3585 00:40:26.015424 DBI_RD = 0x0
3586 00:40:26.015471 OTF = 0x1
3587 00:40:26.015519 ===================================
3588 00:40:26.015568 ===================================
3589 00:40:26.015616 ANA top config
3590 00:40:26.015664 ===================================
3591 00:40:26.015712 DLL_ASYNC_EN = 0
3592 00:40:26.015760 ALL_SLAVE_EN = 1
3593 00:40:26.015807 NEW_RANK_MODE = 1
3594 00:40:26.015856 DLL_IDLE_MODE = 1
3595 00:40:26.015904 LP45_APHY_COMB_EN = 1
3596 00:40:26.015952 TX_ODT_DIS = 1
3597 00:40:26.016000 NEW_8X_MODE = 1
3598 00:40:26.016049 ===================================
3599 00:40:26.016097 ===================================
3600 00:40:26.016145 data_rate = 1200
3601 00:40:26.016193 CKR = 1
3602 00:40:26.016241 DQ_P2S_RATIO = 8
3603 00:40:26.016291 ===================================
3604 00:40:26.016342 CA_P2S_RATIO = 8
3605 00:40:26.016390 DQ_CA_OPEN = 0
3606 00:40:26.016440 DQ_SEMI_OPEN = 0
3607 00:40:26.016494 CA_SEMI_OPEN = 0
3608 00:40:26.016547 CA_FULL_RATE = 0
3609 00:40:26.016601 DQ_CKDIV4_EN = 1
3610 00:40:26.016655 CA_CKDIV4_EN = 1
3611 00:40:26.016708 CA_PREDIV_EN = 0
3612 00:40:26.016761 PH8_DLY = 0
3613 00:40:26.016815 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3614 00:40:26.016868 DQ_AAMCK_DIV = 4
3615 00:40:26.016921 CA_AAMCK_DIV = 4
3616 00:40:26.016975 CA_ADMCK_DIV = 4
3617 00:40:26.017028 DQ_TRACK_CA_EN = 0
3618 00:40:26.017080 CA_PICK = 600
3619 00:40:26.017134 CA_MCKIO = 600
3620 00:40:26.017188 MCKIO_SEMI = 0
3621 00:40:26.017241 PLL_FREQ = 2288
3622 00:40:26.017295 DQ_UI_PI_RATIO = 32
3623 00:40:26.017348 CA_UI_PI_RATIO = 0
3624 00:40:26.017401 ===================================
3625 00:40:26.017455 ===================================
3626 00:40:26.017508 memory_type:LPDDR4
3627 00:40:26.017560 GP_NUM : 10
3628 00:40:26.017612 SRAM_EN : 1
3629 00:40:26.017665 MD32_EN : 0
3630 00:40:26.017719 ===================================
3631 00:40:26.017772 [ANA_INIT] >>>>>>>>>>>>>>
3632 00:40:26.017824 <<<<<< [CONFIGURE PHASE]: ANA_TX
3633 00:40:26.017877 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3634 00:40:26.017931 ===================================
3635 00:40:26.017984 data_rate = 1200,PCW = 0X5800
3636 00:40:26.018037 ===================================
3637 00:40:26.018090 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3638 00:40:26.018144 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3639 00:40:26.018198 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3640 00:40:26.018259 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3641 00:40:26.018316 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3642 00:40:26.018367 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3643 00:40:26.018417 [ANA_INIT] flow start
3644 00:40:26.018466 [ANA_INIT] PLL >>>>>>>>
3645 00:40:26.018514 [ANA_INIT] PLL <<<<<<<<
3646 00:40:26.018562 [ANA_INIT] MIDPI >>>>>>>>
3647 00:40:26.018611 [ANA_INIT] MIDPI <<<<<<<<
3648 00:40:26.018672 [ANA_INIT] DLL >>>>>>>>
3649 00:40:26.018719 [ANA_INIT] flow end
3650 00:40:26.018766 ============ LP4 DIFF to SE enter ============
3651 00:40:26.018814 ============ LP4 DIFF to SE exit ============
3652 00:40:26.018862 [ANA_INIT] <<<<<<<<<<<<<
3653 00:40:26.018909 [Flow] Enable top DCM control >>>>>
3654 00:40:26.019148 [Flow] Enable top DCM control <<<<<
3655 00:40:26.019204 Enable DLL master slave shuffle
3656 00:40:26.019254 ==============================================================
3657 00:40:26.019303 Gating Mode config
3658 00:40:26.019352 ==============================================================
3659 00:40:26.019399 Config description:
3660 00:40:26.019447 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3661 00:40:26.019497 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3662 00:40:26.019545 SELPH_MODE 0: By rank 1: By Phase
3663 00:40:26.019592 ==============================================================
3664 00:40:26.019641 GAT_TRACK_EN = 1
3665 00:40:26.019688 RX_GATING_MODE = 2
3666 00:40:26.019735 RX_GATING_TRACK_MODE = 2
3667 00:40:26.019782 SELPH_MODE = 1
3668 00:40:26.019829 PICG_EARLY_EN = 1
3669 00:40:26.019877 VALID_LAT_VALUE = 1
3670 00:40:26.019924 ==============================================================
3671 00:40:26.019972 Enter into Gating configuration >>>>
3672 00:40:26.020019 Exit from Gating configuration <<<<
3673 00:40:26.020067 Enter into DVFS_PRE_config >>>>>
3674 00:40:26.020114 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3675 00:40:26.020163 Exit from DVFS_PRE_config <<<<<
3676 00:40:26.020211 Enter into PICG configuration >>>>
3677 00:40:26.020258 Exit from PICG configuration <<<<
3678 00:40:26.020310 [RX_INPUT] configuration >>>>>
3679 00:40:26.020359 [RX_INPUT] configuration <<<<<
3680 00:40:26.020407 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3681 00:40:26.020455 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3682 00:40:26.020503 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3683 00:40:26.020553 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3684 00:40:26.020601 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3685 00:40:26.020648 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3686 00:40:26.020696 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3687 00:40:26.020744 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3688 00:40:26.020792 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3689 00:40:26.020840 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3690 00:40:26.020888 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3691 00:40:26.020935 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3692 00:40:26.020983 ===================================
3693 00:40:26.021030 LPDDR4 DRAM CONFIGURATION
3694 00:40:26.021078 ===================================
3695 00:40:26.021125 EX_ROW_EN[0] = 0x0
3696 00:40:26.021172 EX_ROW_EN[1] = 0x0
3697 00:40:26.021220 LP4Y_EN = 0x0
3698 00:40:26.021267 WORK_FSP = 0x0
3699 00:40:26.021313 WL = 0x2
3700 00:40:26.021360 RL = 0x2
3701 00:40:26.021406 BL = 0x2
3702 00:40:26.021453 RPST = 0x0
3703 00:40:26.021499 RD_PRE = 0x0
3704 00:40:26.021546 WR_PRE = 0x1
3705 00:40:26.021593 WR_PST = 0x0
3706 00:40:26.021640 DBI_WR = 0x0
3707 00:40:26.021687 DBI_RD = 0x0
3708 00:40:26.021733 OTF = 0x1
3709 00:40:26.021780 ===================================
3710 00:40:26.021827 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3711 00:40:26.021874 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3712 00:40:26.021921 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3713 00:40:26.021968 ===================================
3714 00:40:26.022015 LPDDR4 DRAM CONFIGURATION
3715 00:40:26.022062 ===================================
3716 00:40:26.022110 EX_ROW_EN[0] = 0x10
3717 00:40:26.022157 EX_ROW_EN[1] = 0x0
3718 00:40:26.022204 LP4Y_EN = 0x0
3719 00:40:26.022302 WORK_FSP = 0x0
3720 00:40:26.022377 WL = 0x2
3721 00:40:26.022448 RL = 0x2
3722 00:40:26.022497 BL = 0x2
3723 00:40:26.022545 RPST = 0x0
3724 00:40:26.022592 RD_PRE = 0x0
3725 00:40:26.022639 WR_PRE = 0x1
3726 00:40:26.022687 WR_PST = 0x0
3727 00:40:26.022734 DBI_WR = 0x0
3728 00:40:26.022780 DBI_RD = 0x0
3729 00:40:26.022828 OTF = 0x1
3730 00:40:26.022875 ===================================
3731 00:40:26.022923 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3732 00:40:26.022972 nWR fixed to 30
3733 00:40:26.023019 [ModeRegInit_LP4] CH0 RK0
3734 00:40:26.023066 [ModeRegInit_LP4] CH0 RK1
3735 00:40:26.023113 [ModeRegInit_LP4] CH1 RK0
3736 00:40:26.023160 [ModeRegInit_LP4] CH1 RK1
3737 00:40:26.023206 match AC timing 16
3738 00:40:26.023252 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 0
3739 00:40:26.023300 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3740 00:40:26.023347 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3741 00:40:26.023396 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3742 00:40:26.023443 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3743 00:40:26.023490 ==
3744 00:40:26.023538 Dram Type= 6, Freq= 0, CH_0, rank 0
3745 00:40:26.023585 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3746 00:40:26.023633 ==
3747 00:40:26.023679 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3748 00:40:26.023727 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3749 00:40:26.023776 [CA 0] Center 35 (5~66) winsize 62
3750 00:40:26.023823 [CA 1] Center 35 (5~66) winsize 62
3751 00:40:26.023871 [CA 2] Center 34 (4~65) winsize 62
3752 00:40:26.023917 [CA 3] Center 34 (4~65) winsize 62
3753 00:40:26.023964 [CA 4] Center 33 (3~64) winsize 62
3754 00:40:26.024011 [CA 5] Center 33 (3~64) winsize 62
3755 00:40:26.024058
3756 00:40:26.024104 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3757 00:40:26.024151
3758 00:40:26.024197 [CATrainingPosCal] consider 1 rank data
3759 00:40:26.024244 u2DelayCellTimex100 = 270/100 ps
3760 00:40:26.024292 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
3761 00:40:26.024345 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3762 00:40:26.024466 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3763 00:40:26.024775 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3764 00:40:26.024858 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3765 00:40:26.024935 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3766 00:40:26.025011
3767 00:40:26.025086 CA PerBit enable=1, Macro0, CA PI delay=33
3768 00:40:26.025161
3769 00:40:26.025237 [CBTSetCACLKResult] CA Dly = 33
3770 00:40:26.025313 CS Dly: 4 (0~35)
3771 00:40:26.025388 ==
3772 00:40:26.025464 Dram Type= 6, Freq= 0, CH_0, rank 1
3773 00:40:26.025540 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3774 00:40:26.025615 ==
3775 00:40:26.025692 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3776 00:40:26.025769 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3777 00:40:26.025845 [CA 0] Center 35 (5~66) winsize 62
3778 00:40:26.025921 [CA 1] Center 35 (5~66) winsize 62
3779 00:40:26.025997 [CA 2] Center 34 (4~65) winsize 62
3780 00:40:26.026072 [CA 3] Center 34 (4~65) winsize 62
3781 00:40:26.026148 [CA 4] Center 33 (3~64) winsize 62
3782 00:40:26.026233 [CA 5] Center 33 (3~64) winsize 62
3783 00:40:26.026350
3784 00:40:26.026426 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3785 00:40:26.026501
3786 00:40:26.026576 [CATrainingPosCal] consider 2 rank data
3787 00:40:26.026651 u2DelayCellTimex100 = 270/100 ps
3788 00:40:26.026727 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
3789 00:40:26.026803 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3790 00:40:26.026878 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3791 00:40:26.026954 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3792 00:40:26.027030 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3793 00:40:26.027105 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3794 00:40:26.027179
3795 00:40:26.027255 CA PerBit enable=1, Macro0, CA PI delay=33
3796 00:40:26.027329
3797 00:40:26.027404 [CBTSetCACLKResult] CA Dly = 33
3798 00:40:26.027479 CS Dly: 4 (0~36)
3799 00:40:26.027554
3800 00:40:26.027629 ----->DramcWriteLeveling(PI) begin...
3801 00:40:26.027705 ==
3802 00:40:26.027780 Dram Type= 6, Freq= 0, CH_0, rank 0
3803 00:40:26.027856 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3804 00:40:26.027932 ==
3805 00:40:26.028008 Write leveling (Byte 0): 32 => 32
3806 00:40:26.028083 Write leveling (Byte 1): 29 => 29
3807 00:40:26.028158 DramcWriteLeveling(PI) end<-----
3808 00:40:26.028233
3809 00:40:26.028307 ==
3810 00:40:26.028383 Dram Type= 6, Freq= 0, CH_0, rank 0
3811 00:40:26.028460 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3812 00:40:26.028581 ==
3813 00:40:26.028633 [Gating] SW mode calibration
3814 00:40:26.028682 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3815 00:40:26.028731 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
3816 00:40:26.028780 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3817 00:40:26.028828 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3818 00:40:26.028876 0 5 8 | B1->B0 | 3232 3030 | 1 1 | (0 0) (0 0)
3819 00:40:26.028925 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3820 00:40:26.028972 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3821 00:40:26.029019 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3822 00:40:26.029067 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3823 00:40:26.029114 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3824 00:40:26.029163 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3825 00:40:26.029211 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3826 00:40:26.029259 0 6 8 | B1->B0 | 2f2f 3030 | 0 1 | (0 0) (0 0)
3827 00:40:26.029306 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3828 00:40:26.029354 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3829 00:40:26.029401 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3830 00:40:26.029448 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3831 00:40:26.029496 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3832 00:40:26.029544 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3833 00:40:26.029592 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3834 00:40:26.029639 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3835 00:40:26.029686 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3836 00:40:26.029734 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3837 00:40:26.029781 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3838 00:40:26.029828 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3839 00:40:26.029874 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3840 00:40:26.029922 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3841 00:40:26.029970 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3842 00:40:26.030018 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3843 00:40:26.030066 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3844 00:40:26.030113 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3845 00:40:26.030162 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3846 00:40:26.030215 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3847 00:40:26.030307 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3848 00:40:26.030355 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3849 00:40:26.030402 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3850 00:40:26.030450 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3851 00:40:26.030498 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3852 00:40:26.030545 Total UI for P1: 0, mck2ui 16
3853 00:40:26.030593 best dqsien dly found for B0: ( 0, 9, 8)
3854 00:40:26.030641 Total UI for P1: 0, mck2ui 16
3855 00:40:26.030689 best dqsien dly found for B1: ( 0, 9, 8)
3856 00:40:26.030736 best DQS0 dly(MCK, UI, PI) = (0, 9, 8)
3857 00:40:26.030783 best DQS1 dly(MCK, UI, PI) = (0, 9, 8)
3858 00:40:26.030830
3859 00:40:26.030877 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 8)
3860 00:40:26.030924 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 8)
3861 00:40:26.030971 [Gating] SW calibration Done
3862 00:40:26.031019 ==
3863 00:40:26.031068 Dram Type= 6, Freq= 0, CH_0, rank 0
3864 00:40:26.031116 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3865 00:40:26.031164 ==
3866 00:40:26.031211 RX Vref Scan: 0
3867 00:40:26.031258
3868 00:40:26.031304 RX Vref 0 -> 0, step: 1
3869 00:40:26.031352
3870 00:40:26.031399 RX Delay -230 -> 252, step: 16
3871 00:40:26.031446 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
3872 00:40:26.031494 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
3873 00:40:26.031727 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
3874 00:40:26.031782 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
3875 00:40:26.031831 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
3876 00:40:26.031879 iDelay=218, Bit 5, Center 33 (-118 ~ 185) 304
3877 00:40:26.031927 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
3878 00:40:26.031974 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
3879 00:40:26.032022 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
3880 00:40:26.032070 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
3881 00:40:26.032118 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
3882 00:40:26.032167 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
3883 00:40:26.032215 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
3884 00:40:26.032263 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
3885 00:40:26.032311 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
3886 00:40:26.032359 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
3887 00:40:26.032407 ==
3888 00:40:26.032454 Dram Type= 6, Freq= 0, CH_0, rank 0
3889 00:40:26.032502 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3890 00:40:26.032551 ==
3891 00:40:26.032598 DQS Delay:
3892 00:40:26.032645 DQS0 = 0, DQS1 = 0
3893 00:40:26.032692 DQM Delay:
3894 00:40:26.032740 DQM0 = 43, DQM1 = 34
3895 00:40:26.032787 DQ Delay:
3896 00:40:26.032836 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
3897 00:40:26.032884 DQ4 =49, DQ5 =33, DQ6 =49, DQ7 =49
3898 00:40:26.032931 DQ8 =25, DQ9 =17, DQ10 =41, DQ11 =25
3899 00:40:26.032979 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
3900 00:40:26.033026
3901 00:40:26.033073
3902 00:40:26.033120 ==
3903 00:40:26.033167 Dram Type= 6, Freq= 0, CH_0, rank 0
3904 00:40:26.033214 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3905 00:40:26.033262 ==
3906 00:40:26.033309
3907 00:40:26.033356
3908 00:40:26.033403 TX Vref Scan disable
3909 00:40:26.033451 == TX Byte 0 ==
3910 00:40:26.033499 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
3911 00:40:26.033547 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
3912 00:40:26.033595 == TX Byte 1 ==
3913 00:40:26.033642 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
3914 00:40:26.033689 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
3915 00:40:26.033736 ==
3916 00:40:26.033784 Dram Type= 6, Freq= 0, CH_0, rank 0
3917 00:40:26.033832 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3918 00:40:26.033880 ==
3919 00:40:26.033927
3920 00:40:26.033973
3921 00:40:26.034019 TX Vref Scan disable
3922 00:40:26.034494 == TX Byte 0 ==
3923 00:40:26.038090 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
3924 00:40:26.044394 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
3925 00:40:26.044533 == TX Byte 1 ==
3926 00:40:26.047851 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
3927 00:40:26.054406 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
3928 00:40:26.054548
3929 00:40:26.054610 [DATLAT]
3930 00:40:26.054665 Freq=600, CH0 RK0
3931 00:40:26.054719
3932 00:40:26.057505 DATLAT Default: 0x9
3933 00:40:26.057644 0, 0xFFFF, sum = 0
3934 00:40:26.060829 1, 0xFFFF, sum = 0
3935 00:40:26.064319 2, 0xFFFF, sum = 0
3936 00:40:26.064459 3, 0xFFFF, sum = 0
3937 00:40:26.067514 4, 0xFFFF, sum = 0
3938 00:40:26.067655 5, 0xFFFF, sum = 0
3939 00:40:26.070784 6, 0xFFFF, sum = 0
3940 00:40:26.070923 7, 0x0, sum = 1
3941 00:40:26.070990 8, 0x0, sum = 2
3942 00:40:26.074721 9, 0x0, sum = 3
3943 00:40:26.074868 10, 0x0, sum = 4
3944 00:40:26.077698 best_step = 8
3945 00:40:26.077844
3946 00:40:26.077910 ==
3947 00:40:26.081099 Dram Type= 6, Freq= 0, CH_0, rank 0
3948 00:40:26.084524 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3949 00:40:26.084684 ==
3950 00:40:26.087719 RX Vref Scan: 1
3951 00:40:26.087878
3952 00:40:26.087955 RX Vref 0 -> 0, step: 1
3953 00:40:26.088023
3954 00:40:26.091344 RX Delay -195 -> 252, step: 8
3955 00:40:26.091511
3956 00:40:26.094259 Set Vref, RX VrefLevel [Byte0]: 46
3957 00:40:26.097657 [Byte1]: 50
3958 00:40:26.101879
3959 00:40:26.102071 Final RX Vref Byte 0 = 46 to rank0
3960 00:40:26.105092 Final RX Vref Byte 1 = 50 to rank0
3961 00:40:26.108691 Final RX Vref Byte 0 = 46 to rank1
3962 00:40:26.111921 Final RX Vref Byte 1 = 50 to rank1==
3963 00:40:26.114728 Dram Type= 6, Freq= 0, CH_0, rank 0
3964 00:40:26.121538 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3965 00:40:26.121821 ==
3966 00:40:26.121995 DQS Delay:
3967 00:40:26.122153 DQS0 = 0, DQS1 = 0
3968 00:40:26.257843 DQM Delay:
3969 00:40:26.258350 DQM0 = 40, DQM1 = 30
3970 00:40:26.258689 DQ Delay:
3971 00:40:26.258995 DQ0 =36, DQ1 =40, DQ2 =36, DQ3 =36
3972 00:40:26.259297 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =48
3973 00:40:26.259631 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =20
3974 00:40:26.259915 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
3975 00:40:26.260192
3976 00:40:26.260499
3977 00:40:26.260806 [DQSOSCAuto] RK0, (LSB)MR18= 0x5353, (MSB)MR19= 0x808, tDQSOscB0 = 394 ps tDQSOscB1 = 394 ps
3978 00:40:26.261101 CH0 RK0: MR19=808, MR18=5353
3979 00:40:26.261403 CH0_RK0: MR19=0x808, MR18=0x5353, DQSOSC=394, MR23=63, INC=168, DEC=112
3980 00:40:26.261686
3981 00:40:26.261959 ----->DramcWriteLeveling(PI) begin...
3982 00:40:26.262285 ==
3983 00:40:26.262576 Dram Type= 6, Freq= 0, CH_0, rank 1
3984 00:40:26.262852 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3985 00:40:26.263128 ==
3986 00:40:26.263402 Write leveling (Byte 0): 31 => 31
3987 00:40:26.263676 Write leveling (Byte 1): 31 => 31
3988 00:40:26.263945 DramcWriteLeveling(PI) end<-----
3989 00:40:26.264216
3990 00:40:26.264482 ==
3991 00:40:26.264754 Dram Type= 6, Freq= 0, CH_0, rank 1
3992 00:40:26.265025 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3993 00:40:26.265299 ==
3994 00:40:26.265748 [Gating] SW mode calibration
3995 00:40:26.266106 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3996 00:40:26.266440 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
3997 00:40:26.266724 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3998 00:40:26.267001 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3999 00:40:26.267275 0 5 8 | B1->B0 | 3333 3030 | 1 1 | (1 1) (1 1)
4000 00:40:26.267551 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4001 00:40:26.267830 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4002 00:40:26.268078 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4003 00:40:26.268323 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4004 00:40:26.268567 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4005 00:40:26.268814 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4006 00:40:26.269058 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4007 00:40:26.269303 0 6 8 | B1->B0 | 3131 3333 | 0 1 | (0 0) (0 0)
4008 00:40:26.269549 0 6 12 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
4009 00:40:26.269801 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4010 00:40:26.270106 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4011 00:40:26.270403 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4012 00:40:26.270712 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4013 00:40:26.274149 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4014 00:40:26.280937 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4015 00:40:26.283878 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4016 00:40:26.287389 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4017 00:40:26.294252 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4018 00:40:26.297451 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4019 00:40:26.300854 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4020 00:40:26.307454 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4021 00:40:26.310950 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4022 00:40:26.314122 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4023 00:40:26.320839 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4024 00:40:26.323814 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4025 00:40:26.327097 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4026 00:40:26.333659 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4027 00:40:26.337144 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4028 00:40:26.340350 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4029 00:40:26.346940 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4030 00:40:26.350096 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4031 00:40:26.353258 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4032 00:40:26.356573 Total UI for P1: 0, mck2ui 16
4033 00:40:26.359843 best dqsien dly found for B0: ( 0, 9, 6)
4034 00:40:26.363281 Total UI for P1: 0, mck2ui 16
4035 00:40:26.366772 best dqsien dly found for B1: ( 0, 9, 6)
4036 00:40:26.369892 best DQS0 dly(MCK, UI, PI) = (0, 9, 6)
4037 00:40:26.372953 best DQS1 dly(MCK, UI, PI) = (0, 9, 6)
4038 00:40:26.373059
4039 00:40:26.379587 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 6)
4040 00:40:26.383162 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 6)
4041 00:40:26.383248 [Gating] SW calibration Done
4042 00:40:26.386052 ==
4043 00:40:26.389754 Dram Type= 6, Freq= 0, CH_0, rank 1
4044 00:40:26.393199 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4045 00:40:26.393343 ==
4046 00:40:26.393411 RX Vref Scan: 0
4047 00:40:26.393470
4048 00:40:26.396319 RX Vref 0 -> 0, step: 1
4049 00:40:26.396436
4050 00:40:26.399804 RX Delay -230 -> 252, step: 16
4051 00:40:26.403141 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4052 00:40:26.406445 iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336
4053 00:40:26.412902 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4054 00:40:26.416276 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4055 00:40:26.419578 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
4056 00:40:26.423091 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4057 00:40:26.429236 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4058 00:40:26.432627 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4059 00:40:26.436020 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4060 00:40:26.439339 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4061 00:40:26.442563 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4062 00:40:26.449480 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4063 00:40:26.452433 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4064 00:40:26.456207 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4065 00:40:26.459376 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4066 00:40:26.465956 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4067 00:40:26.466288 ==
4068 00:40:26.469676 Dram Type= 6, Freq= 0, CH_0, rank 1
4069 00:40:26.472588 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4070 00:40:26.472872 ==
4071 00:40:26.473092 DQS Delay:
4072 00:40:26.476104 DQS0 = 0, DQS1 = 0
4073 00:40:26.476708 DQM Delay:
4074 00:40:26.479296 DQM0 = 43, DQM1 = 33
4075 00:40:26.479689 DQ Delay:
4076 00:40:26.482794 DQ0 =41, DQ1 =49, DQ2 =41, DQ3 =33
4077 00:40:26.486048 DQ4 =49, DQ5 =33, DQ6 =49, DQ7 =49
4078 00:40:26.489521 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
4079 00:40:26.492693 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4080 00:40:26.493178
4081 00:40:26.493491
4082 00:40:26.493771 ==
4083 00:40:26.495919 Dram Type= 6, Freq= 0, CH_0, rank 1
4084 00:40:26.499470 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4085 00:40:26.502449 ==
4086 00:40:26.502845
4087 00:40:26.503149
4088 00:40:26.503432 TX Vref Scan disable
4089 00:40:26.505829 == TX Byte 0 ==
4090 00:40:26.509380 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4091 00:40:26.512335 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4092 00:40:26.515790 == TX Byte 1 ==
4093 00:40:26.519303 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4094 00:40:26.522097 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4095 00:40:26.526054 ==
4096 00:40:26.529054 Dram Type= 6, Freq= 0, CH_0, rank 1
4097 00:40:26.532618 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4098 00:40:26.533016 ==
4099 00:40:26.533325
4100 00:40:26.533605
4101 00:40:26.535303 TX Vref Scan disable
4102 00:40:26.535696 == TX Byte 0 ==
4103 00:40:26.541877 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4104 00:40:26.545652 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4105 00:40:26.546132 == TX Byte 1 ==
4106 00:40:26.552065 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4107 00:40:26.555488 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4108 00:40:26.555982
4109 00:40:26.556300 [DATLAT]
4110 00:40:26.558886 Freq=600, CH0 RK1
4111 00:40:26.559318
4112 00:40:26.559636 DATLAT Default: 0x8
4113 00:40:26.562071 0, 0xFFFF, sum = 0
4114 00:40:26.562535 1, 0xFFFF, sum = 0
4115 00:40:26.565286 2, 0xFFFF, sum = 0
4116 00:40:26.569125 3, 0xFFFF, sum = 0
4117 00:40:26.569523 4, 0xFFFF, sum = 0
4118 00:40:26.572241 5, 0xFFFF, sum = 0
4119 00:40:26.572637 6, 0xFFFF, sum = 0
4120 00:40:26.575460 7, 0x0, sum = 1
4121 00:40:26.575855 8, 0x0, sum = 2
4122 00:40:26.576167 9, 0x0, sum = 3
4123 00:40:26.578615 10, 0x0, sum = 4
4124 00:40:26.579072 best_step = 8
4125 00:40:26.579381
4126 00:40:26.579665 ==
4127 00:40:26.581806 Dram Type= 6, Freq= 0, CH_0, rank 1
4128 00:40:26.588747 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4129 00:40:26.589163 ==
4130 00:40:26.589479 RX Vref Scan: 0
4131 00:40:26.589769
4132 00:40:26.592691 RX Vref 0 -> 0, step: 1
4133 00:40:26.593081
4134 00:40:26.595378 RX Delay -195 -> 252, step: 8
4135 00:40:26.598581 iDelay=205, Bit 0, Center 36 (-115 ~ 188) 304
4136 00:40:26.605682 iDelay=205, Bit 1, Center 40 (-115 ~ 196) 312
4137 00:40:26.608705 iDelay=205, Bit 2, Center 40 (-115 ~ 196) 312
4138 00:40:26.611851 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4139 00:40:26.615183 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4140 00:40:26.618575 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4141 00:40:26.625146 iDelay=205, Bit 6, Center 44 (-107 ~ 196) 304
4142 00:40:26.628461 iDelay=205, Bit 7, Center 52 (-99 ~ 204) 304
4143 00:40:26.631914 iDelay=205, Bit 8, Center 20 (-131 ~ 172) 304
4144 00:40:26.635158 iDelay=205, Bit 9, Center 20 (-131 ~ 172) 304
4145 00:40:26.641664 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4146 00:40:26.645463 iDelay=205, Bit 11, Center 20 (-131 ~ 172) 304
4147 00:40:26.648595 iDelay=205, Bit 12, Center 40 (-107 ~ 188) 296
4148 00:40:26.651803 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4149 00:40:26.658582 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4150 00:40:26.662099 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4151 00:40:26.662522 ==
4152 00:40:26.665107 Dram Type= 6, Freq= 0, CH_0, rank 1
4153 00:40:26.668880 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4154 00:40:26.669275 ==
4155 00:40:26.672194 DQS Delay:
4156 00:40:26.672582 DQS0 = 0, DQS1 = 0
4157 00:40:26.672886 DQM Delay:
4158 00:40:26.675291 DQM0 = 40, DQM1 = 32
4159 00:40:26.675681 DQ Delay:
4160 00:40:26.678153 DQ0 =36, DQ1 =40, DQ2 =40, DQ3 =36
4161 00:40:26.681555 DQ4 =44, DQ5 =32, DQ6 =44, DQ7 =52
4162 00:40:26.684950 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =20
4163 00:40:26.688195 DQ12 =40, DQ13 =40, DQ14 =44, DQ15 =44
4164 00:40:26.688702
4165 00:40:26.689053
4166 00:40:26.698141 [DQSOSCAuto] RK1, (LSB)MR18= 0x7070, (MSB)MR19= 0x808, tDQSOscB0 = 388 ps tDQSOscB1 = 388 ps
4167 00:40:26.698596 CH0 RK1: MR19=808, MR18=7070
4168 00:40:26.705169 CH0_RK1: MR19=0x808, MR18=0x7070, DQSOSC=388, MR23=63, INC=174, DEC=116
4169 00:40:26.708435 [RxdqsGatingPostProcess] freq 600
4170 00:40:26.714931 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4171 00:40:26.718076 Pre-setting of DQS Precalculation
4172 00:40:26.721473 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4173 00:40:26.721868 ==
4174 00:40:26.724452 Dram Type= 6, Freq= 0, CH_1, rank 0
4175 00:40:26.731836 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4176 00:40:26.732233 ==
4177 00:40:26.734745 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4178 00:40:26.741532 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
4179 00:40:26.744537 [CA 0] Center 35 (5~66) winsize 62
4180 00:40:26.748473 [CA 1] Center 35 (4~66) winsize 63
4181 00:40:26.751293 [CA 2] Center 33 (3~64) winsize 62
4182 00:40:26.754957 [CA 3] Center 33 (3~64) winsize 62
4183 00:40:26.758085 [CA 4] Center 33 (2~64) winsize 63
4184 00:40:26.761372 [CA 5] Center 33 (2~64) winsize 63
4185 00:40:26.761854
4186 00:40:26.764748 [CmdBusTrainingLP45] Vref(ca) range 1: 39
4187 00:40:26.765142
4188 00:40:26.768104 [CATrainingPosCal] consider 1 rank data
4189 00:40:26.771371 u2DelayCellTimex100 = 270/100 ps
4190 00:40:26.774711 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4191 00:40:26.778199 CA1 delay=35 (4~66),Diff = 2 PI (19 cell)
4192 00:40:26.781980 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
4193 00:40:26.788441 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4194 00:40:26.791413 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
4195 00:40:26.794694 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4196 00:40:26.795226
4197 00:40:26.797838 CA PerBit enable=1, Macro0, CA PI delay=33
4198 00:40:26.798350
4199 00:40:26.801061 [CBTSetCACLKResult] CA Dly = 33
4200 00:40:26.801540 CS Dly: 4 (0~35)
4201 00:40:26.801856 ==
4202 00:40:26.805115 Dram Type= 6, Freq= 0, CH_1, rank 1
4203 00:40:26.810928 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4204 00:40:26.811414 ==
4205 00:40:26.814205 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4206 00:40:26.820930 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4207 00:40:26.824306 [CA 0] Center 35 (4~66) winsize 63
4208 00:40:26.828156 [CA 1] Center 34 (4~65) winsize 62
4209 00:40:26.830826 [CA 2] Center 33 (3~64) winsize 62
4210 00:40:26.834519 [CA 3] Center 33 (3~64) winsize 62
4211 00:40:26.837666 [CA 4] Center 32 (2~63) winsize 62
4212 00:40:26.841328 [CA 5] Center 32 (2~63) winsize 62
4213 00:40:26.841824
4214 00:40:26.844114 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4215 00:40:26.844509
4216 00:40:26.847773 [CATrainingPosCal] consider 2 rank data
4217 00:40:26.851326 u2DelayCellTimex100 = 270/100 ps
4218 00:40:26.854566 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
4219 00:40:26.861174 CA1 delay=34 (4~65),Diff = 2 PI (19 cell)
4220 00:40:26.864080 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
4221 00:40:26.867503 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
4222 00:40:26.870714 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
4223 00:40:26.873946 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
4224 00:40:26.874464
4225 00:40:26.877621 CA PerBit enable=1, Macro0, CA PI delay=32
4226 00:40:26.878018
4227 00:40:26.880702 [CBTSetCACLKResult] CA Dly = 32
4228 00:40:26.884290 CS Dly: 4 (0~35)
4229 00:40:26.884830
4230 00:40:26.887185 ----->DramcWriteLeveling(PI) begin...
4231 00:40:26.887592 ==
4232 00:40:26.890460 Dram Type= 6, Freq= 0, CH_1, rank 0
4233 00:40:26.893837 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4234 00:40:26.894384 ==
4235 00:40:26.897384 Write leveling (Byte 0): 28 => 28
4236 00:40:26.900475 Write leveling (Byte 1): 27 => 27
4237 00:40:26.903921 DramcWriteLeveling(PI) end<-----
4238 00:40:26.904453
4239 00:40:26.904770 ==
4240 00:40:26.907054 Dram Type= 6, Freq= 0, CH_1, rank 0
4241 00:40:26.910367 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4242 00:40:26.910762 ==
4243 00:40:26.913685 [Gating] SW mode calibration
4244 00:40:26.920259 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4245 00:40:26.926908 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4246 00:40:26.930350 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4247 00:40:26.933516 0 5 4 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
4248 00:40:26.940510 0 5 8 | B1->B0 | 2f2f 2424 | 0 0 | (1 1) (1 1)
4249 00:40:26.943925 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4250 00:40:26.947251 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4251 00:40:26.954447 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4252 00:40:26.957109 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4253 00:40:26.960276 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4254 00:40:26.967435 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4255 00:40:26.970437 0 6 4 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
4256 00:40:26.973691 0 6 8 | B1->B0 | 3333 4343 | 0 0 | (0 0) (0 0)
4257 00:40:26.976681 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4258 00:40:26.983650 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4259 00:40:26.986658 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4260 00:40:26.989974 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4261 00:40:26.997422 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4262 00:40:26.999890 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4263 00:40:27.003989 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4264 00:40:27.010515 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4265 00:40:27.013567 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4266 00:40:27.017041 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4267 00:40:27.023796 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4268 00:40:27.026622 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4269 00:40:27.030140 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4270 00:40:27.036820 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4271 00:40:27.039979 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4272 00:40:27.043199 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4273 00:40:27.049932 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4274 00:40:27.053356 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4275 00:40:27.056473 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4276 00:40:27.063036 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4277 00:40:27.066639 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4278 00:40:27.069957 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4279 00:40:27.076335 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4280 00:40:27.079474 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4281 00:40:27.083097 Total UI for P1: 0, mck2ui 16
4282 00:40:27.086392 best dqsien dly found for B1: ( 0, 9, 6)
4283 00:40:27.089731 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4284 00:40:27.093123 Total UI for P1: 0, mck2ui 16
4285 00:40:27.095967 best dqsien dly found for B0: ( 0, 9, 6)
4286 00:40:27.099619 best DQS0 dly(MCK, UI, PI) = (0, 9, 6)
4287 00:40:27.103130 best DQS1 dly(MCK, UI, PI) = (0, 9, 6)
4288 00:40:27.103521
4289 00:40:27.106073 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 6)
4290 00:40:27.112858 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 6)
4291 00:40:27.113380 [Gating] SW calibration Done
4292 00:40:27.115998 ==
4293 00:40:27.116436 Dram Type= 6, Freq= 0, CH_1, rank 0
4294 00:40:27.122916 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4295 00:40:27.123306 ==
4296 00:40:27.123613 RX Vref Scan: 0
4297 00:40:27.123896
4298 00:40:27.125984 RX Vref 0 -> 0, step: 1
4299 00:40:27.126485
4300 00:40:27.129234 RX Delay -230 -> 252, step: 16
4301 00:40:27.132468 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4302 00:40:27.136311 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4303 00:40:27.142390 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4304 00:40:27.146078 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4305 00:40:27.149388 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4306 00:40:27.152566 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4307 00:40:27.156277 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4308 00:40:27.162497 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4309 00:40:27.165898 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4310 00:40:27.169437 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4311 00:40:27.172715 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4312 00:40:27.179380 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4313 00:40:27.182463 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4314 00:40:27.185823 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4315 00:40:27.188906 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4316 00:40:27.195558 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4317 00:40:27.195965 ==
4318 00:40:27.198952 Dram Type= 6, Freq= 0, CH_1, rank 0
4319 00:40:27.202117 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4320 00:40:27.202638 ==
4321 00:40:27.202953 DQS Delay:
4322 00:40:27.205979 DQS0 = 0, DQS1 = 0
4323 00:40:27.206484 DQM Delay:
4324 00:40:27.208878 DQM0 = 38, DQM1 = 32
4325 00:40:27.209344 DQ Delay:
4326 00:40:27.212493 DQ0 =41, DQ1 =33, DQ2 =33, DQ3 =33
4327 00:40:27.215551 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4328 00:40:27.218950 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4329 00:40:27.222011 DQ12 =41, DQ13 =49, DQ14 =33, DQ15 =49
4330 00:40:27.222446
4331 00:40:27.222883
4332 00:40:27.223174 ==
4333 00:40:27.225379 Dram Type= 6, Freq= 0, CH_1, rank 0
4334 00:40:27.228517 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4335 00:40:27.228904 ==
4336 00:40:27.229206
4337 00:40:27.231875
4338 00:40:27.232253 TX Vref Scan disable
4339 00:40:27.235214 == TX Byte 0 ==
4340 00:40:27.238646 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4341 00:40:27.241808 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4342 00:40:27.245270 == TX Byte 1 ==
4343 00:40:27.248557 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4344 00:40:27.251924 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4345 00:40:27.252311 ==
4346 00:40:27.255077 Dram Type= 6, Freq= 0, CH_1, rank 0
4347 00:40:27.261823 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4348 00:40:27.262318 ==
4349 00:40:27.262759
4350 00:40:27.263147
4351 00:40:27.265274 TX Vref Scan disable
4352 00:40:27.265660 == TX Byte 0 ==
4353 00:40:27.271631 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4354 00:40:27.274959 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4355 00:40:27.275343 == TX Byte 1 ==
4356 00:40:27.281470 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4357 00:40:27.284924 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4358 00:40:27.285311
4359 00:40:27.285612 [DATLAT]
4360 00:40:27.287994 Freq=600, CH1 RK0
4361 00:40:27.288374
4362 00:40:27.288669 DATLAT Default: 0x9
4363 00:40:27.291652 0, 0xFFFF, sum = 0
4364 00:40:27.292137 1, 0xFFFF, sum = 0
4365 00:40:27.294944 2, 0xFFFF, sum = 0
4366 00:40:27.295334 3, 0xFFFF, sum = 0
4367 00:40:27.298273 4, 0xFFFF, sum = 0
4368 00:40:27.298668 5, 0xFFFF, sum = 0
4369 00:40:27.301673 6, 0xFFFF, sum = 0
4370 00:40:27.302064 7, 0x0, sum = 1
4371 00:40:27.304844 8, 0x0, sum = 2
4372 00:40:27.305234 9, 0x0, sum = 3
4373 00:40:27.309010 10, 0x0, sum = 4
4374 00:40:27.309513 best_step = 8
4375 00:40:27.309834
4376 00:40:27.310111 ==
4377 00:40:27.311923 Dram Type= 6, Freq= 0, CH_1, rank 0
4378 00:40:27.318247 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4379 00:40:27.318640 ==
4380 00:40:27.318943 RX Vref Scan: 1
4381 00:40:27.319280
4382 00:40:27.321472 RX Vref 0 -> 0, step: 1
4383 00:40:27.321851
4384 00:40:27.324836 RX Delay -195 -> 252, step: 8
4385 00:40:27.325223
4386 00:40:27.328080 Set Vref, RX VrefLevel [Byte0]: 57
4387 00:40:27.331301 [Byte1]: 50
4388 00:40:27.331687
4389 00:40:27.334782 Final RX Vref Byte 0 = 57 to rank0
4390 00:40:27.337801 Final RX Vref Byte 1 = 50 to rank0
4391 00:40:27.341567 Final RX Vref Byte 0 = 57 to rank1
4392 00:40:27.344779 Final RX Vref Byte 1 = 50 to rank1==
4393 00:40:27.348160 Dram Type= 6, Freq= 0, CH_1, rank 0
4394 00:40:27.351030 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4395 00:40:27.351441 ==
4396 00:40:27.354455 DQS Delay:
4397 00:40:27.354846 DQS0 = 0, DQS1 = 0
4398 00:40:27.355150 DQM Delay:
4399 00:40:27.357548 DQM0 = 37, DQM1 = 29
4400 00:40:27.357935 DQ Delay:
4401 00:40:27.361196 DQ0 =40, DQ1 =28, DQ2 =28, DQ3 =36
4402 00:40:27.364316 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =36
4403 00:40:27.367617 DQ8 =8, DQ9 =20, DQ10 =32, DQ11 =20
4404 00:40:27.371488 DQ12 =40, DQ13 =40, DQ14 =36, DQ15 =40
4405 00:40:27.371979
4406 00:40:27.372294
4407 00:40:27.380964 [DQSOSCAuto] RK0, (LSB)MR18= 0x7e7e, (MSB)MR19= 0x808, tDQSOscB0 = 386 ps tDQSOscB1 = 386 ps
4408 00:40:27.384203 CH1 RK0: MR19=808, MR18=7E7E
4409 00:40:27.387615 CH1_RK0: MR19=0x808, MR18=0x7E7E, DQSOSC=386, MR23=63, INC=176, DEC=117
4410 00:40:27.388088
4411 00:40:27.391611 ----->DramcWriteLeveling(PI) begin...
4412 00:40:27.394528 ==
4413 00:40:27.397988 Dram Type= 6, Freq= 0, CH_1, rank 1
4414 00:40:27.400899 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4415 00:40:27.401337 ==
4416 00:40:27.403994 Write leveling (Byte 0): 28 => 28
4417 00:40:27.407552 Write leveling (Byte 1): 29 => 29
4418 00:40:27.410709 DramcWriteLeveling(PI) end<-----
4419 00:40:27.411100
4420 00:40:27.411409 ==
4421 00:40:27.413959 Dram Type= 6, Freq= 0, CH_1, rank 1
4422 00:40:27.417824 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4423 00:40:27.418334 ==
4424 00:40:27.421143 [Gating] SW mode calibration
4425 00:40:27.427774 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4426 00:40:27.434307 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4427 00:40:27.437431 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4428 00:40:27.441029 0 5 4 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
4429 00:40:27.447750 0 5 8 | B1->B0 | 3030 2626 | 1 0 | (0 0) (0 0)
4430 00:40:27.451087 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4431 00:40:27.454343 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4432 00:40:27.457733 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4433 00:40:27.463904 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4434 00:40:27.467013 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4435 00:40:27.470446 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4436 00:40:27.477517 0 6 4 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
4437 00:40:27.480622 0 6 8 | B1->B0 | 3838 4545 | 0 0 | (0 0) (0 0)
4438 00:40:27.483651 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4439 00:40:27.490646 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4440 00:40:27.494123 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4441 00:40:27.497097 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4442 00:40:27.504073 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4443 00:40:27.507366 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4444 00:40:27.510934 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4445 00:40:27.516988 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4446 00:40:27.520495 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4447 00:40:27.523681 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4448 00:40:27.530478 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4449 00:40:27.533438 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4450 00:40:27.537492 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4451 00:40:27.543353 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4452 00:40:27.546933 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4453 00:40:27.550195 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4454 00:40:27.557377 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4455 00:40:27.560125 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4456 00:40:27.563467 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4457 00:40:27.570395 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4458 00:40:27.573842 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4459 00:40:27.576966 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4460 00:40:27.583395 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4461 00:40:27.587169 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4462 00:40:27.590201 Total UI for P1: 0, mck2ui 16
4463 00:40:27.593886 best dqsien dly found for B0: ( 0, 9, 4)
4464 00:40:27.596863 Total UI for P1: 0, mck2ui 16
4465 00:40:27.600450 best dqsien dly found for B1: ( 0, 9, 6)
4466 00:40:27.603500 best DQS0 dly(MCK, UI, PI) = (0, 9, 4)
4467 00:40:27.606704 best DQS1 dly(MCK, UI, PI) = (0, 9, 6)
4468 00:40:27.607131
4469 00:40:27.610185 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 4)
4470 00:40:27.613763 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 6)
4471 00:40:27.616677 [Gating] SW calibration Done
4472 00:40:27.617304 ==
4473 00:40:27.619794 Dram Type= 6, Freq= 0, CH_1, rank 1
4474 00:40:27.623135 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4475 00:40:27.623627 ==
4476 00:40:27.626426 RX Vref Scan: 0
4477 00:40:27.626853
4478 00:40:27.629750 RX Vref 0 -> 0, step: 1
4479 00:40:27.630315
4480 00:40:27.630639 RX Delay -230 -> 252, step: 16
4481 00:40:27.636612 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4482 00:40:27.640016 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4483 00:40:27.643351 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4484 00:40:27.646785 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4485 00:40:27.653182 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4486 00:40:27.656389 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4487 00:40:27.660314 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4488 00:40:27.662790 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4489 00:40:27.666682 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4490 00:40:27.673323 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4491 00:40:27.676490 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4492 00:40:27.680102 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4493 00:40:27.683052 iDelay=218, Bit 12, Center 41 (-134 ~ 217) 352
4494 00:40:27.689747 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4495 00:40:27.693407 iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352
4496 00:40:27.696399 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4497 00:40:27.696996 ==
4498 00:40:27.699751 Dram Type= 6, Freq= 0, CH_1, rank 1
4499 00:40:27.703093 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4500 00:40:27.706423 ==
4501 00:40:27.706935 DQS Delay:
4502 00:40:27.707274 DQS0 = 0, DQS1 = 0
4503 00:40:27.710112 DQM Delay:
4504 00:40:27.710671 DQM0 = 39, DQM1 = 32
4505 00:40:27.713366 DQ Delay:
4506 00:40:27.716075 DQ0 =41, DQ1 =33, DQ2 =33, DQ3 =33
4507 00:40:27.716507 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =33
4508 00:40:27.719559 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4509 00:40:27.723000 DQ12 =41, DQ13 =49, DQ14 =41, DQ15 =41
4510 00:40:27.725966
4511 00:40:27.726471
4512 00:40:27.726790 ==
4513 00:40:27.729375 Dram Type= 6, Freq= 0, CH_1, rank 1
4514 00:40:27.732613 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4515 00:40:27.733075 ==
4516 00:40:27.733397
4517 00:40:27.733682
4518 00:40:27.735882 TX Vref Scan disable
4519 00:40:27.736273 == TX Byte 0 ==
4520 00:40:27.742925 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4521 00:40:27.745808 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4522 00:40:27.746405 == TX Byte 1 ==
4523 00:40:27.752252 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4524 00:40:27.756310 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4525 00:40:27.756705 ==
4526 00:40:27.759106 Dram Type= 6, Freq= 0, CH_1, rank 1
4527 00:40:27.762333 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4528 00:40:27.762734 ==
4529 00:40:27.763045
4530 00:40:27.763331
4531 00:40:27.766085 TX Vref Scan disable
4532 00:40:27.769272 == TX Byte 0 ==
4533 00:40:27.772802 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4534 00:40:27.775796 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4535 00:40:27.778897 == TX Byte 1 ==
4536 00:40:27.782684 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4537 00:40:27.785946 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4538 00:40:27.788734
4539 00:40:27.789123 [DATLAT]
4540 00:40:27.789431 Freq=600, CH1 RK1
4541 00:40:27.789719
4542 00:40:27.792244 DATLAT Default: 0x8
4543 00:40:27.792566 0, 0xFFFF, sum = 0
4544 00:40:27.795460 1, 0xFFFF, sum = 0
4545 00:40:27.795859 2, 0xFFFF, sum = 0
4546 00:40:27.799028 3, 0xFFFF, sum = 0
4547 00:40:27.799429 4, 0xFFFF, sum = 0
4548 00:40:27.802040 5, 0xFFFF, sum = 0
4549 00:40:27.805301 6, 0xFFFF, sum = 0
4550 00:40:27.805702 7, 0x0, sum = 1
4551 00:40:27.806015 8, 0x0, sum = 2
4552 00:40:27.808902 9, 0x0, sum = 3
4553 00:40:27.809297 10, 0x0, sum = 4
4554 00:40:27.812288 best_step = 8
4555 00:40:27.812681
4556 00:40:27.812985 ==
4557 00:40:27.815428 Dram Type= 6, Freq= 0, CH_1, rank 1
4558 00:40:27.818870 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4559 00:40:27.819297 ==
4560 00:40:27.821994 RX Vref Scan: 0
4561 00:40:27.822484
4562 00:40:27.822884 RX Vref 0 -> 0, step: 1
4563 00:40:27.823257
4564 00:40:27.825406 RX Delay -195 -> 252, step: 8
4565 00:40:27.832382 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4566 00:40:27.835656 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4567 00:40:27.838749 iDelay=205, Bit 2, Center 28 (-131 ~ 188) 320
4568 00:40:27.842395 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4569 00:40:27.849042 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4570 00:40:27.852290 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4571 00:40:27.855621 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4572 00:40:27.858999 iDelay=205, Bit 7, Center 36 (-123 ~ 196) 320
4573 00:40:27.865329 iDelay=205, Bit 8, Center 12 (-147 ~ 172) 320
4574 00:40:27.868658 iDelay=205, Bit 9, Center 16 (-139 ~ 172) 312
4575 00:40:27.871819 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4576 00:40:27.875164 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4577 00:40:27.882262 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4578 00:40:27.885098 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4579 00:40:27.888909 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4580 00:40:27.891687 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4581 00:40:27.892096 ==
4582 00:40:27.895236 Dram Type= 6, Freq= 0, CH_1, rank 1
4583 00:40:27.902041 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4584 00:40:27.902474 ==
4585 00:40:27.902786 DQS Delay:
4586 00:40:27.905184 DQS0 = 0, DQS1 = 0
4587 00:40:27.905573 DQM Delay:
4588 00:40:27.905883 DQM0 = 37, DQM1 = 28
4589 00:40:27.908659 DQ Delay:
4590 00:40:27.911812 DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =32
4591 00:40:27.914872 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =36
4592 00:40:27.918132 DQ8 =12, DQ9 =16, DQ10 =28, DQ11 =20
4593 00:40:27.921468 DQ12 =36, DQ13 =40, DQ14 =36, DQ15 =40
4594 00:40:27.921860
4595 00:40:27.922168
4596 00:40:27.928445 [DQSOSCAuto] RK1, (LSB)MR18= 0x6060, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 391 ps
4597 00:40:27.931471 CH1 RK1: MR19=808, MR18=6060
4598 00:40:27.938249 CH1_RK1: MR19=0x808, MR18=0x6060, DQSOSC=391, MR23=63, INC=171, DEC=114
4599 00:40:27.941563 [RxdqsGatingPostProcess] freq 600
4600 00:40:27.944883 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4601 00:40:27.948046 Pre-setting of DQS Precalculation
4602 00:40:27.955160 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4603 00:40:27.961453 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4604 00:40:27.967753 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4605 00:40:27.968155
4606 00:40:27.968458
4607 00:40:27.971152 [Calibration Summary] 1200 Mbps
4608 00:40:27.971542 CH 0, Rank 0
4609 00:40:27.974552 SW Impedance : PASS
4610 00:40:27.977681 DUTY Scan : NO K
4611 00:40:27.978074 ZQ Calibration : PASS
4612 00:40:27.980903 Jitter Meter : NO K
4613 00:40:27.984295 CBT Training : PASS
4614 00:40:27.984688 Write leveling : PASS
4615 00:40:27.987958 RX DQS gating : PASS
4616 00:40:27.991167 RX DQ/DQS(RDDQC) : PASS
4617 00:40:27.991557 TX DQ/DQS : PASS
4618 00:40:27.994428 RX DATLAT : PASS
4619 00:40:27.997995 RX DQ/DQS(Engine): PASS
4620 00:40:27.998508 TX OE : NO K
4621 00:40:28.001012 All Pass.
4622 00:40:28.001395
4623 00:40:28.001695 CH 0, Rank 1
4624 00:40:28.004673 SW Impedance : PASS
4625 00:40:28.005147 DUTY Scan : NO K
4626 00:40:28.007869 ZQ Calibration : PASS
4627 00:40:28.010982 Jitter Meter : NO K
4628 00:40:28.011375 CBT Training : PASS
4629 00:40:28.014325 Write leveling : PASS
4630 00:40:28.017663 RX DQS gating : PASS
4631 00:40:28.018136 RX DQ/DQS(RDDQC) : PASS
4632 00:40:28.020981 TX DQ/DQS : PASS
4633 00:40:28.021371 RX DATLAT : PASS
4634 00:40:28.023963 RX DQ/DQS(Engine): PASS
4635 00:40:28.027856 TX OE : NO K
4636 00:40:28.028330 All Pass.
4637 00:40:28.028634
4638 00:40:28.028909 CH 1, Rank 0
4639 00:40:28.030769 SW Impedance : PASS
4640 00:40:28.034322 DUTY Scan : NO K
4641 00:40:28.034758 ZQ Calibration : PASS
4642 00:40:28.037849 Jitter Meter : NO K
4643 00:40:28.041190 CBT Training : PASS
4644 00:40:28.041663 Write leveling : PASS
4645 00:40:28.044056 RX DQS gating : PASS
4646 00:40:28.047170 RX DQ/DQS(RDDQC) : PASS
4647 00:40:28.047563 TX DQ/DQS : PASS
4648 00:40:28.050698 RX DATLAT : PASS
4649 00:40:28.054424 RX DQ/DQS(Engine): PASS
4650 00:40:28.054892 TX OE : NO K
4651 00:40:28.057643 All Pass.
4652 00:40:28.058114
4653 00:40:28.058483 CH 1, Rank 1
4654 00:40:28.061201 SW Impedance : PASS
4655 00:40:28.061670 DUTY Scan : NO K
4656 00:40:28.064216 ZQ Calibration : PASS
4657 00:40:28.067545 Jitter Meter : NO K
4658 00:40:28.068024 CBT Training : PASS
4659 00:40:28.071300 Write leveling : PASS
4660 00:40:28.073752 RX DQS gating : PASS
4661 00:40:28.074141 RX DQ/DQS(RDDQC) : PASS
4662 00:40:28.077566 TX DQ/DQS : PASS
4663 00:40:28.078039 RX DATLAT : PASS
4664 00:40:28.081099 RX DQ/DQS(Engine): PASS
4665 00:40:28.084648 TX OE : NO K
4666 00:40:28.085119 All Pass.
4667 00:40:28.085429
4668 00:40:28.087364 DramC Write-DBI off
4669 00:40:28.090818 PER_BANK_REFRESH: Hybrid Mode
4670 00:40:28.091288 TX_TRACKING: ON
4671 00:40:28.100761 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4672 00:40:28.104164 [FAST_K] Save calibration result to emmc
4673 00:40:28.107495 dramc_set_vcore_voltage set vcore to 662500
4674 00:40:28.108018 Read voltage for 933, 3
4675 00:40:28.110708 Vio18 = 0
4676 00:40:28.111140 Vcore = 662500
4677 00:40:28.111478 Vdram = 0
4678 00:40:28.114169 Vddq = 0
4679 00:40:28.114717 Vmddr = 0
4680 00:40:28.117516 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4681 00:40:28.123599 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4682 00:40:28.126905 MEM_TYPE=3, freq_sel=17
4683 00:40:28.130314 sv_algorithm_assistance_LP4_1600
4684 00:40:28.133550 ============ PULL DRAM RESETB DOWN ============
4685 00:40:28.137019 ========== PULL DRAM RESETB DOWN end =========
4686 00:40:28.143706 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4687 00:40:28.147298 ===================================
4688 00:40:28.147773 LPDDR4 DRAM CONFIGURATION
4689 00:40:28.150183 ===================================
4690 00:40:28.154068 EX_ROW_EN[0] = 0x0
4691 00:40:28.154586 EX_ROW_EN[1] = 0x0
4692 00:40:28.157206 LP4Y_EN = 0x0
4693 00:40:28.157674 WORK_FSP = 0x0
4694 00:40:28.160517 WL = 0x3
4695 00:40:28.163649 RL = 0x3
4696 00:40:28.164035 BL = 0x2
4697 00:40:28.167064 RPST = 0x0
4698 00:40:28.167451 RD_PRE = 0x0
4699 00:40:28.170055 WR_PRE = 0x1
4700 00:40:28.170476 WR_PST = 0x0
4701 00:40:28.173605 DBI_WR = 0x0
4702 00:40:28.174071 DBI_RD = 0x0
4703 00:40:28.176793 OTF = 0x1
4704 00:40:28.180458 ===================================
4705 00:40:28.183450 ===================================
4706 00:40:28.183842 ANA top config
4707 00:40:28.186623 ===================================
4708 00:40:28.190043 DLL_ASYNC_EN = 0
4709 00:40:28.193798 ALL_SLAVE_EN = 1
4710 00:40:28.194311 NEW_RANK_MODE = 1
4711 00:40:28.197081 DLL_IDLE_MODE = 1
4712 00:40:28.200570 LP45_APHY_COMB_EN = 1
4713 00:40:28.203942 TX_ODT_DIS = 1
4714 00:40:28.206649 NEW_8X_MODE = 1
4715 00:40:28.210428 ===================================
4716 00:40:28.210822 ===================================
4717 00:40:28.213410 data_rate = 1866
4718 00:40:28.216729 CKR = 1
4719 00:40:28.220076 DQ_P2S_RATIO = 8
4720 00:40:28.223257 ===================================
4721 00:40:28.226675 CA_P2S_RATIO = 8
4722 00:40:28.229991 DQ_CA_OPEN = 0
4723 00:40:28.233703 DQ_SEMI_OPEN = 0
4724 00:40:28.234093 CA_SEMI_OPEN = 0
4725 00:40:28.236646 CA_FULL_RATE = 0
4726 00:40:28.240081 DQ_CKDIV4_EN = 1
4727 00:40:28.243223 CA_CKDIV4_EN = 1
4728 00:40:28.247104 CA_PREDIV_EN = 0
4729 00:40:28.250184 PH8_DLY = 0
4730 00:40:28.250713 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4731 00:40:28.253712 DQ_AAMCK_DIV = 4
4732 00:40:28.256496 CA_AAMCK_DIV = 4
4733 00:40:28.260000 CA_ADMCK_DIV = 4
4734 00:40:28.263077 DQ_TRACK_CA_EN = 0
4735 00:40:28.266597 CA_PICK = 933
4736 00:40:28.267084 CA_MCKIO = 933
4737 00:40:28.269904 MCKIO_SEMI = 0
4738 00:40:28.273231 PLL_FREQ = 3732
4739 00:40:28.276587 DQ_UI_PI_RATIO = 32
4740 00:40:28.279935 CA_UI_PI_RATIO = 0
4741 00:40:28.282851 ===================================
4742 00:40:28.286167 ===================================
4743 00:40:28.290133 memory_type:LPDDR4
4744 00:40:28.290632 GP_NUM : 10
4745 00:40:28.293542 SRAM_EN : 1
4746 00:40:28.294013 MD32_EN : 0
4747 00:40:28.296336 ===================================
4748 00:40:28.299671 [ANA_INIT] >>>>>>>>>>>>>>
4749 00:40:28.302798 <<<<<< [CONFIGURE PHASE]: ANA_TX
4750 00:40:28.306548 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4751 00:40:28.309511 ===================================
4752 00:40:28.312888 data_rate = 1866,PCW = 0X8f00
4753 00:40:28.316397 ===================================
4754 00:40:28.319493 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4755 00:40:28.325993 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4756 00:40:28.329404 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4757 00:40:28.336059 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4758 00:40:28.339304 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4759 00:40:28.343178 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4760 00:40:28.343652 [ANA_INIT] flow start
4761 00:40:28.346188 [ANA_INIT] PLL >>>>>>>>
4762 00:40:28.349619 [ANA_INIT] PLL <<<<<<<<
4763 00:40:28.350087 [ANA_INIT] MIDPI >>>>>>>>
4764 00:40:28.352780 [ANA_INIT] MIDPI <<<<<<<<
4765 00:40:28.356815 [ANA_INIT] DLL >>>>>>>>
4766 00:40:28.357304 [ANA_INIT] flow end
4767 00:40:28.362668 ============ LP4 DIFF to SE enter ============
4768 00:40:28.365839 ============ LP4 DIFF to SE exit ============
4769 00:40:28.369338 [ANA_INIT] <<<<<<<<<<<<<
4770 00:40:28.372750 [Flow] Enable top DCM control >>>>>
4771 00:40:28.375973 [Flow] Enable top DCM control <<<<<
4772 00:40:28.376408 Enable DLL master slave shuffle
4773 00:40:28.383154 ==============================================================
4774 00:40:28.385895 Gating Mode config
4775 00:40:28.389332 ==============================================================
4776 00:40:28.392559 Config description:
4777 00:40:28.402539 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4778 00:40:28.409317 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4779 00:40:28.412740 SELPH_MODE 0: By rank 1: By Phase
4780 00:40:28.419168 ==============================================================
4781 00:40:28.422832 GAT_TRACK_EN = 1
4782 00:40:28.426093 RX_GATING_MODE = 2
4783 00:40:28.429586 RX_GATING_TRACK_MODE = 2
4784 00:40:28.430102 SELPH_MODE = 1
4785 00:40:28.432555 PICG_EARLY_EN = 1
4786 00:40:28.435671 VALID_LAT_VALUE = 1
4787 00:40:28.442434 ==============================================================
4788 00:40:28.445990 Enter into Gating configuration >>>>
4789 00:40:28.449144 Exit from Gating configuration <<<<
4790 00:40:28.452241 Enter into DVFS_PRE_config >>>>>
4791 00:40:28.462416 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4792 00:40:28.465233 Exit from DVFS_PRE_config <<<<<
4793 00:40:28.469090 Enter into PICG configuration >>>>
4794 00:40:28.472427 Exit from PICG configuration <<<<
4795 00:40:28.475588 [RX_INPUT] configuration >>>>>
4796 00:40:28.479290 [RX_INPUT] configuration <<<<<
4797 00:40:28.482524 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4798 00:40:28.488555 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4799 00:40:28.495324 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4800 00:40:28.501827 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4801 00:40:28.508439 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4802 00:40:28.512402 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4803 00:40:28.518058 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4804 00:40:28.521791 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4805 00:40:28.525102 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4806 00:40:28.528285 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4807 00:40:28.535040 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4808 00:40:28.538702 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4809 00:40:28.542005 ===================================
4810 00:40:28.545346 LPDDR4 DRAM CONFIGURATION
4811 00:40:28.548456 ===================================
4812 00:40:28.548942 EX_ROW_EN[0] = 0x0
4813 00:40:28.552208 EX_ROW_EN[1] = 0x0
4814 00:40:28.552678 LP4Y_EN = 0x0
4815 00:40:28.555028 WORK_FSP = 0x0
4816 00:40:28.555421 WL = 0x3
4817 00:40:28.558111 RL = 0x3
4818 00:40:28.558543 BL = 0x2
4819 00:40:28.561854 RPST = 0x0
4820 00:40:28.562393 RD_PRE = 0x0
4821 00:40:28.565255 WR_PRE = 0x1
4822 00:40:28.568627 WR_PST = 0x0
4823 00:40:28.569112 DBI_WR = 0x0
4824 00:40:28.571454 DBI_RD = 0x0
4825 00:40:28.571928 OTF = 0x1
4826 00:40:28.574970 ===================================
4827 00:40:28.578270 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4828 00:40:28.581889 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4829 00:40:28.588622 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4830 00:40:28.591570 ===================================
4831 00:40:28.595112 LPDDR4 DRAM CONFIGURATION
4832 00:40:28.598157 ===================================
4833 00:40:28.598743 EX_ROW_EN[0] = 0x10
4834 00:40:28.601952 EX_ROW_EN[1] = 0x0
4835 00:40:28.602450 LP4Y_EN = 0x0
4836 00:40:28.604372 WORK_FSP = 0x0
4837 00:40:28.604804 WL = 0x3
4838 00:40:28.607719 RL = 0x3
4839 00:40:28.608153 BL = 0x2
4840 00:40:28.611171 RPST = 0x0
4841 00:40:28.611673 RD_PRE = 0x0
4842 00:40:28.614391 WR_PRE = 0x1
4843 00:40:28.614868 WR_PST = 0x0
4844 00:40:28.617522 DBI_WR = 0x0
4845 00:40:28.621355 DBI_RD = 0x0
4846 00:40:28.621750 OTF = 0x1
4847 00:40:28.624581 ===================================
4848 00:40:28.631077 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
4849 00:40:28.634608 nWR fixed to 30
4850 00:40:28.638103 [ModeRegInit_LP4] CH0 RK0
4851 00:40:28.638531 [ModeRegInit_LP4] CH0 RK1
4852 00:40:28.640951 [ModeRegInit_LP4] CH1 RK0
4853 00:40:28.644638 [ModeRegInit_LP4] CH1 RK1
4854 00:40:28.645042 match AC timing 8
4855 00:40:28.651210 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 0
4856 00:40:28.654579 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
4857 00:40:28.657861 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
4858 00:40:28.664613 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
4859 00:40:28.667943 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
4860 00:40:28.668335 ==
4861 00:40:28.671183 Dram Type= 6, Freq= 0, CH_0, rank 0
4862 00:40:28.674650 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4863 00:40:28.675124 ==
4864 00:40:28.681502 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4865 00:40:28.687837 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4866 00:40:28.691387 [CA 0] Center 39 (8~70) winsize 63
4867 00:40:28.694354 [CA 1] Center 39 (8~70) winsize 63
4868 00:40:28.697545 [CA 2] Center 36 (6~67) winsize 62
4869 00:40:28.701312 [CA 3] Center 36 (6~66) winsize 61
4870 00:40:28.704284 [CA 4] Center 34 (4~65) winsize 62
4871 00:40:28.707992 [CA 5] Center 34 (4~65) winsize 62
4872 00:40:28.708476
4873 00:40:28.711106 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4874 00:40:28.711499
4875 00:40:28.714354 [CATrainingPosCal] consider 1 rank data
4876 00:40:28.717557 u2DelayCellTimex100 = 270/100 ps
4877 00:40:28.721564 CA0 delay=39 (8~70),Diff = 5 PI (31 cell)
4878 00:40:28.723748 CA1 delay=39 (8~70),Diff = 5 PI (31 cell)
4879 00:40:28.727493 CA2 delay=36 (6~67),Diff = 2 PI (12 cell)
4880 00:40:28.731145 CA3 delay=36 (6~66),Diff = 2 PI (12 cell)
4881 00:40:28.734111 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4882 00:40:28.740537 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4883 00:40:28.740987
4884 00:40:28.743884 CA PerBit enable=1, Macro0, CA PI delay=34
4885 00:40:28.744358
4886 00:40:28.747144 [CBTSetCACLKResult] CA Dly = 34
4887 00:40:28.747539 CS Dly: 7 (0~38)
4888 00:40:28.747849 ==
4889 00:40:28.750601 Dram Type= 6, Freq= 0, CH_0, rank 1
4890 00:40:28.754208 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4891 00:40:28.757253 ==
4892 00:40:28.760565 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4893 00:40:28.767117 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4894 00:40:28.770183 [CA 0] Center 38 (8~69) winsize 62
4895 00:40:28.774017 [CA 1] Center 38 (7~69) winsize 63
4896 00:40:28.776805 [CA 2] Center 36 (5~67) winsize 63
4897 00:40:28.780513 [CA 3] Center 35 (5~66) winsize 62
4898 00:40:28.783706 [CA 4] Center 34 (4~65) winsize 62
4899 00:40:28.786788 [CA 5] Center 34 (4~65) winsize 62
4900 00:40:28.787258
4901 00:40:28.790199 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4902 00:40:28.790640
4903 00:40:28.793519 [CATrainingPosCal] consider 2 rank data
4904 00:40:28.797017 u2DelayCellTimex100 = 270/100 ps
4905 00:40:28.800647 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4906 00:40:28.803415 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4907 00:40:28.806761 CA2 delay=36 (6~67),Diff = 2 PI (12 cell)
4908 00:40:28.813187 CA3 delay=36 (6~66),Diff = 2 PI (12 cell)
4909 00:40:28.816721 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4910 00:40:28.819941 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4911 00:40:28.820348
4912 00:40:28.823638 CA PerBit enable=1, Macro0, CA PI delay=34
4913 00:40:28.824079
4914 00:40:28.826724 [CBTSetCACLKResult] CA Dly = 34
4915 00:40:28.827125 CS Dly: 7 (0~39)
4916 00:40:28.827524
4917 00:40:28.829802 ----->DramcWriteLeveling(PI) begin...
4918 00:40:28.833074 ==
4919 00:40:28.833563 Dram Type= 6, Freq= 0, CH_0, rank 0
4920 00:40:28.839726 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4921 00:40:28.840126 ==
4922 00:40:28.843177 Write leveling (Byte 0): 28 => 28
4923 00:40:28.846388 Write leveling (Byte 1): 26 => 26
4924 00:40:28.849927 DramcWriteLeveling(PI) end<-----
4925 00:40:28.850359
4926 00:40:28.850760 ==
4927 00:40:28.853037 Dram Type= 6, Freq= 0, CH_0, rank 0
4928 00:40:28.856311 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4929 00:40:28.856827 ==
4930 00:40:28.859605 [Gating] SW mode calibration
4931 00:40:28.866150 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
4932 00:40:28.873151 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
4933 00:40:28.876605 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4934 00:40:28.879660 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4935 00:40:28.886629 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4936 00:40:28.889715 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4937 00:40:28.893028 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4938 00:40:28.896617 0 10 20 | B1->B0 | 3434 2f2f | 0 0 | (0 1) (0 1)
4939 00:40:28.903181 0 10 24 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
4940 00:40:28.906317 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4941 00:40:28.909612 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4942 00:40:28.915690 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4943 00:40:28.919187 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4944 00:40:28.923007 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4945 00:40:28.929014 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4946 00:40:28.932676 0 11 20 | B1->B0 | 2424 3030 | 0 0 | (0 0) (0 0)
4947 00:40:28.935508 0 11 24 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
4948 00:40:28.942053 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4949 00:40:28.945772 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4950 00:40:28.948844 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4951 00:40:28.955952 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4952 00:40:28.958827 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4953 00:40:28.962206 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4954 00:40:28.968830 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4955 00:40:28.972615 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4956 00:40:28.975192 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4957 00:40:28.982354 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4958 00:40:28.985736 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4959 00:40:28.989041 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4960 00:40:28.995309 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4961 00:40:28.998295 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4962 00:40:29.001736 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4963 00:40:29.008415 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4964 00:40:29.011612 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4965 00:40:29.014914 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4966 00:40:29.022017 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4967 00:40:29.024955 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4968 00:40:29.028053 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4969 00:40:29.034701 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4970 00:40:29.038255 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4971 00:40:29.041633 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4972 00:40:29.048025 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4973 00:40:29.048418 Total UI for P1: 0, mck2ui 16
4974 00:40:29.054508 best dqsien dly found for B0: ( 0, 14, 22)
4975 00:40:29.054967 Total UI for P1: 0, mck2ui 16
4976 00:40:29.061546 best dqsien dly found for B1: ( 0, 14, 22)
4977 00:40:29.064495 best DQS0 dly(MCK, UI, PI) = (0, 14, 22)
4978 00:40:29.067848 best DQS1 dly(MCK, UI, PI) = (0, 14, 22)
4979 00:40:29.068241
4980 00:40:29.071839 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 22)
4981 00:40:29.074759 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 22)
4982 00:40:29.078171 [Gating] SW calibration Done
4983 00:40:29.078706 ==
4984 00:40:29.081224 Dram Type= 6, Freq= 0, CH_0, rank 0
4985 00:40:29.084425 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4986 00:40:29.084826 ==
4987 00:40:29.088020 RX Vref Scan: 0
4988 00:40:29.088492
4989 00:40:29.088852 RX Vref 0 -> 0, step: 1
4990 00:40:29.091043
4991 00:40:29.091435 RX Delay -80 -> 252, step: 8
4992 00:40:29.097687 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
4993 00:40:29.101318 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
4994 00:40:29.104173 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
4995 00:40:29.107859 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
4996 00:40:29.111109 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
4997 00:40:29.114201 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
4998 00:40:29.117848 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
4999 00:40:29.124104 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5000 00:40:29.127590 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5001 00:40:29.130647 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5002 00:40:29.134128 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5003 00:40:29.137371 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5004 00:40:29.143803 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5005 00:40:29.147332 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5006 00:40:29.151442 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5007 00:40:29.153920 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5008 00:40:29.154422 ==
5009 00:40:29.157057 Dram Type= 6, Freq= 0, CH_0, rank 0
5010 00:40:29.163983 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5011 00:40:29.164629 ==
5012 00:40:29.164958 DQS Delay:
5013 00:40:29.165242 DQS0 = 0, DQS1 = 0
5014 00:40:29.167087 DQM Delay:
5015 00:40:29.167472 DQM0 = 96, DQM1 = 85
5016 00:40:29.170452 DQ Delay:
5017 00:40:29.173772 DQ0 =91, DQ1 =95, DQ2 =95, DQ3 =91
5018 00:40:29.176920 DQ4 =99, DQ5 =87, DQ6 =103, DQ7 =107
5019 00:40:29.180068 DQ8 =75, DQ9 =71, DQ10 =83, DQ11 =75
5020 00:40:29.183896 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5021 00:40:29.184330
5022 00:40:29.184654
5023 00:40:29.184964 ==
5024 00:40:29.186928 Dram Type= 6, Freq= 0, CH_0, rank 0
5025 00:40:29.190199 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5026 00:40:29.190714 ==
5027 00:40:29.191025
5028 00:40:29.191356
5029 00:40:29.193730 TX Vref Scan disable
5030 00:40:29.194406 == TX Byte 0 ==
5031 00:40:29.199909 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5032 00:40:29.203576 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5033 00:40:29.206897 == TX Byte 1 ==
5034 00:40:29.210371 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5035 00:40:29.213305 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5036 00:40:29.213719 ==
5037 00:40:29.216817 Dram Type= 6, Freq= 0, CH_0, rank 0
5038 00:40:29.219745 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5039 00:40:29.223077 ==
5040 00:40:29.223547
5041 00:40:29.223985
5042 00:40:29.224442 TX Vref Scan disable
5043 00:40:29.226718 == TX Byte 0 ==
5044 00:40:29.229965 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5045 00:40:29.236721 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5046 00:40:29.237111 == TX Byte 1 ==
5047 00:40:29.239875 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5048 00:40:29.246566 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5049 00:40:29.247034
5050 00:40:29.247348 [DATLAT]
5051 00:40:29.247632 Freq=933, CH0 RK0
5052 00:40:29.247908
5053 00:40:29.250267 DATLAT Default: 0xd
5054 00:40:29.250695 0, 0xFFFF, sum = 0
5055 00:40:29.253628 1, 0xFFFF, sum = 0
5056 00:40:29.256837 2, 0xFFFF, sum = 0
5057 00:40:29.257351 3, 0xFFFF, sum = 0
5058 00:40:29.260239 4, 0xFFFF, sum = 0
5059 00:40:29.260758 5, 0xFFFF, sum = 0
5060 00:40:29.263263 6, 0xFFFF, sum = 0
5061 00:40:29.263700 7, 0xFFFF, sum = 0
5062 00:40:29.266405 8, 0xFFFF, sum = 0
5063 00:40:29.266844 9, 0xFFFF, sum = 0
5064 00:40:29.269731 10, 0x0, sum = 1
5065 00:40:29.270185 11, 0x0, sum = 2
5066 00:40:29.273254 12, 0x0, sum = 3
5067 00:40:29.273769 13, 0x0, sum = 4
5068 00:40:29.274121 best_step = 11
5069 00:40:29.274499
5070 00:40:29.276599 ==
5071 00:40:29.279959 Dram Type= 6, Freq= 0, CH_0, rank 0
5072 00:40:29.283349 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5073 00:40:29.283861 ==
5074 00:40:29.284208 RX Vref Scan: 1
5075 00:40:29.284523
5076 00:40:29.286798 RX Vref 0 -> 0, step: 1
5077 00:40:29.287309
5078 00:40:29.289980 RX Delay -69 -> 252, step: 4
5079 00:40:29.290541
5080 00:40:29.293305 Set Vref, RX VrefLevel [Byte0]: 46
5081 00:40:29.296615 [Byte1]: 50
5082 00:40:29.297123
5083 00:40:29.299962 Final RX Vref Byte 0 = 46 to rank0
5084 00:40:29.303073 Final RX Vref Byte 1 = 50 to rank0
5085 00:40:29.306443 Final RX Vref Byte 0 = 46 to rank1
5086 00:40:29.309813 Final RX Vref Byte 1 = 50 to rank1==
5087 00:40:29.313019 Dram Type= 6, Freq= 0, CH_0, rank 0
5088 00:40:29.316276 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5089 00:40:29.319391 ==
5090 00:40:29.319822 DQS Delay:
5091 00:40:29.320163 DQS0 = 0, DQS1 = 0
5092 00:40:29.322874 DQM Delay:
5093 00:40:29.323302 DQM0 = 97, DQM1 = 87
5094 00:40:29.326016 DQ Delay:
5095 00:40:29.329593 DQ0 =94, DQ1 =98, DQ2 =96, DQ3 =92
5096 00:40:29.332645 DQ4 =100, DQ5 =88, DQ6 =104, DQ7 =104
5097 00:40:29.335885 DQ8 =78, DQ9 =72, DQ10 =88, DQ11 =78
5098 00:40:29.339223 DQ12 =94, DQ13 =94, DQ14 =100, DQ15 =98
5099 00:40:29.339609
5100 00:40:29.339914
5101 00:40:29.346001 [DQSOSCAuto] RK0, (LSB)MR18= 0x2929, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 408 ps
5102 00:40:29.349509 CH0 RK0: MR19=505, MR18=2929
5103 00:40:29.356084 CH0_RK0: MR19=0x505, MR18=0x2929, DQSOSC=408, MR23=63, INC=65, DEC=43
5104 00:40:29.356560
5105 00:40:29.359331 ----->DramcWriteLeveling(PI) begin...
5106 00:40:29.359852 ==
5107 00:40:29.362445 Dram Type= 6, Freq= 0, CH_0, rank 1
5108 00:40:29.366196 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5109 00:40:29.366760 ==
5110 00:40:29.369043 Write leveling (Byte 0): 29 => 29
5111 00:40:29.372297 Write leveling (Byte 1): 28 => 28
5112 00:40:29.376280 DramcWriteLeveling(PI) end<-----
5113 00:40:29.376788
5114 00:40:29.377127 ==
5115 00:40:29.379157 Dram Type= 6, Freq= 0, CH_0, rank 1
5116 00:40:29.382140 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5117 00:40:29.382613 ==
5118 00:40:29.385453 [Gating] SW mode calibration
5119 00:40:29.392119 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5120 00:40:29.399190 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5121 00:40:29.402035 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5122 00:40:29.408679 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5123 00:40:29.412279 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5124 00:40:29.415546 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5125 00:40:29.421716 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5126 00:40:29.424850 0 10 20 | B1->B0 | 3030 2a2a | 1 1 | (1 1) (1 0)
5127 00:40:29.428354 0 10 24 | B1->B0 | 2323 2323 | 1 0 | (1 0) (0 0)
5128 00:40:29.434901 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5129 00:40:29.438296 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5130 00:40:29.441590 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5131 00:40:29.448403 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5132 00:40:29.451414 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5133 00:40:29.455061 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5134 00:40:29.461759 0 11 20 | B1->B0 | 2c2c 3838 | 0 0 | (1 1) (1 1)
5135 00:40:29.464671 0 11 24 | B1->B0 | 3d3d 4646 | 0 0 | (1 1) (0 0)
5136 00:40:29.467644 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5137 00:40:29.474379 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5138 00:40:29.477825 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5139 00:40:29.481098 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5140 00:40:29.487627 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5141 00:40:29.490925 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5142 00:40:29.494188 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5143 00:40:29.500814 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5144 00:40:29.504106 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5145 00:40:29.507406 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5146 00:40:29.514252 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5147 00:40:29.517711 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5148 00:40:29.520841 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5149 00:40:29.527569 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5150 00:40:29.530991 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5151 00:40:29.533931 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5152 00:40:29.540576 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5153 00:40:29.544071 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5154 00:40:29.547030 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5155 00:40:29.554180 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5156 00:40:29.557237 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5157 00:40:29.560231 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5158 00:40:29.566988 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5159 00:40:29.570358 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5160 00:40:29.573696 Total UI for P1: 0, mck2ui 16
5161 00:40:29.577315 best dqsien dly found for B0: ( 0, 14, 20)
5162 00:40:29.579938 Total UI for P1: 0, mck2ui 16
5163 00:40:29.583426 best dqsien dly found for B1: ( 0, 14, 20)
5164 00:40:29.586502 best DQS0 dly(MCK, UI, PI) = (0, 14, 20)
5165 00:40:29.589789 best DQS1 dly(MCK, UI, PI) = (0, 14, 20)
5166 00:40:29.590244
5167 00:40:29.593001 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 20)
5168 00:40:29.597185 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 20)
5169 00:40:29.599881 [Gating] SW calibration Done
5170 00:40:29.600321 ==
5171 00:40:29.603449 Dram Type= 6, Freq= 0, CH_0, rank 1
5172 00:40:29.609942 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5173 00:40:29.610493 ==
5174 00:40:29.610845 RX Vref Scan: 0
5175 00:40:29.611194
5176 00:40:29.613033 RX Vref 0 -> 0, step: 1
5177 00:40:29.613465
5178 00:40:29.616628 RX Delay -80 -> 252, step: 8
5179 00:40:29.619558 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5180 00:40:29.622813 iDelay=200, Bit 1, Center 99 (0 ~ 199) 200
5181 00:40:29.626429 iDelay=200, Bit 2, Center 95 (0 ~ 191) 192
5182 00:40:29.629583 iDelay=200, Bit 3, Center 91 (0 ~ 183) 184
5183 00:40:29.633086 iDelay=200, Bit 4, Center 99 (8 ~ 191) 184
5184 00:40:29.639440 iDelay=200, Bit 5, Center 87 (-8 ~ 183) 192
5185 00:40:29.643008 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5186 00:40:29.646195 iDelay=200, Bit 7, Center 103 (8 ~ 199) 192
5187 00:40:29.649554 iDelay=200, Bit 8, Center 75 (-16 ~ 167) 184
5188 00:40:29.652716 iDelay=200, Bit 9, Center 71 (-24 ~ 167) 192
5189 00:40:29.659569 iDelay=200, Bit 10, Center 83 (-16 ~ 183) 200
5190 00:40:29.662562 iDelay=200, Bit 11, Center 79 (-16 ~ 175) 192
5191 00:40:29.666095 iDelay=200, Bit 12, Center 91 (-8 ~ 191) 200
5192 00:40:29.669266 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5193 00:40:29.672569 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5194 00:40:29.679280 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5195 00:40:29.679776 ==
5196 00:40:29.682454 Dram Type= 6, Freq= 0, CH_0, rank 1
5197 00:40:29.685992 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5198 00:40:29.686549 ==
5199 00:40:29.686896 DQS Delay:
5200 00:40:29.689027 DQS0 = 0, DQS1 = 0
5201 00:40:29.689460 DQM Delay:
5202 00:40:29.692385 DQM0 = 97, DQM1 = 85
5203 00:40:29.692897 DQ Delay:
5204 00:40:29.695755 DQ0 =95, DQ1 =99, DQ2 =95, DQ3 =91
5205 00:40:29.698964 DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =103
5206 00:40:29.702514 DQ8 =75, DQ9 =71, DQ10 =83, DQ11 =79
5207 00:40:29.705540 DQ12 =91, DQ13 =95, DQ14 =95, DQ15 =95
5208 00:40:29.706057
5209 00:40:29.706452
5210 00:40:29.706770 ==
5211 00:40:29.708756 Dram Type= 6, Freq= 0, CH_0, rank 1
5212 00:40:29.711970 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5213 00:40:29.712407 ==
5214 00:40:29.712759
5215 00:40:29.715408
5216 00:40:29.715837 TX Vref Scan disable
5217 00:40:29.718692 == TX Byte 0 ==
5218 00:40:29.722283 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5219 00:40:29.725672 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5220 00:40:29.729296 == TX Byte 1 ==
5221 00:40:29.732554 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5222 00:40:29.735313 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5223 00:40:29.735873 ==
5224 00:40:29.739012 Dram Type= 6, Freq= 0, CH_0, rank 1
5225 00:40:29.745889 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5226 00:40:29.746540 ==
5227 00:40:29.746892
5228 00:40:29.747202
5229 00:40:29.747513 TX Vref Scan disable
5230 00:40:29.750109 == TX Byte 0 ==
5231 00:40:29.752828 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5232 00:40:29.760151 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5233 00:40:29.760661 == TX Byte 1 ==
5234 00:40:29.763172 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5235 00:40:29.769547 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5236 00:40:29.770063
5237 00:40:29.770446 [DATLAT]
5238 00:40:29.770763 Freq=933, CH0 RK1
5239 00:40:29.771067
5240 00:40:29.772878 DATLAT Default: 0xb
5241 00:40:29.773388 0, 0xFFFF, sum = 0
5242 00:40:29.775811 1, 0xFFFF, sum = 0
5243 00:40:29.776251 2, 0xFFFF, sum = 0
5244 00:40:29.779118 3, 0xFFFF, sum = 0
5245 00:40:29.782484 4, 0xFFFF, sum = 0
5246 00:40:29.782923 5, 0xFFFF, sum = 0
5247 00:40:29.786465 6, 0xFFFF, sum = 0
5248 00:40:29.786980 7, 0xFFFF, sum = 0
5249 00:40:29.789997 8, 0xFFFF, sum = 0
5250 00:40:29.790605 9, 0xFFFF, sum = 0
5251 00:40:29.792718 10, 0x0, sum = 1
5252 00:40:29.793233 11, 0x0, sum = 2
5253 00:40:29.796070 12, 0x0, sum = 3
5254 00:40:29.796585 13, 0x0, sum = 4
5255 00:40:29.796933 best_step = 11
5256 00:40:29.797244
5257 00:40:29.799318 ==
5258 00:40:29.802562 Dram Type= 6, Freq= 0, CH_0, rank 1
5259 00:40:29.806433 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5260 00:40:29.806952 ==
5261 00:40:29.807296 RX Vref Scan: 0
5262 00:40:29.807615
5263 00:40:29.809288 RX Vref 0 -> 0, step: 1
5264 00:40:29.809719
5265 00:40:29.812718 RX Delay -69 -> 252, step: 4
5266 00:40:29.816365 iDelay=199, Bit 0, Center 92 (3 ~ 182) 180
5267 00:40:29.822431 iDelay=199, Bit 1, Center 100 (7 ~ 194) 188
5268 00:40:29.825943 iDelay=199, Bit 2, Center 96 (7 ~ 186) 180
5269 00:40:29.828915 iDelay=199, Bit 3, Center 90 (3 ~ 178) 176
5270 00:40:29.832208 iDelay=199, Bit 4, Center 100 (11 ~ 190) 180
5271 00:40:29.835657 iDelay=199, Bit 5, Center 90 (-5 ~ 186) 192
5272 00:40:29.842396 iDelay=199, Bit 6, Center 104 (15 ~ 194) 180
5273 00:40:29.845913 iDelay=199, Bit 7, Center 108 (19 ~ 198) 180
5274 00:40:29.848810 iDelay=199, Bit 8, Center 76 (-9 ~ 162) 172
5275 00:40:29.852353 iDelay=199, Bit 9, Center 72 (-17 ~ 162) 180
5276 00:40:29.855806 iDelay=199, Bit 10, Center 88 (-5 ~ 182) 188
5277 00:40:29.859115 iDelay=199, Bit 11, Center 78 (-9 ~ 166) 176
5278 00:40:29.865884 iDelay=199, Bit 12, Center 92 (3 ~ 182) 180
5279 00:40:29.868989 iDelay=199, Bit 13, Center 90 (-1 ~ 182) 184
5280 00:40:29.872974 iDelay=199, Bit 14, Center 96 (7 ~ 186) 180
5281 00:40:29.875662 iDelay=199, Bit 15, Center 94 (3 ~ 186) 184
5282 00:40:29.876181 ==
5283 00:40:29.878957 Dram Type= 6, Freq= 0, CH_0, rank 1
5284 00:40:29.882048 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5285 00:40:29.885328 ==
5286 00:40:29.885839 DQS Delay:
5287 00:40:29.886181 DQS0 = 0, DQS1 = 0
5288 00:40:29.888661 DQM Delay:
5289 00:40:29.889166 DQM0 = 97, DQM1 = 85
5290 00:40:29.892067 DQ Delay:
5291 00:40:29.895424 DQ0 =92, DQ1 =100, DQ2 =96, DQ3 =90
5292 00:40:29.899099 DQ4 =100, DQ5 =90, DQ6 =104, DQ7 =108
5293 00:40:29.902627 DQ8 =76, DQ9 =72, DQ10 =88, DQ11 =78
5294 00:40:29.906098 DQ12 =92, DQ13 =90, DQ14 =96, DQ15 =94
5295 00:40:29.906716
5296 00:40:29.907062
5297 00:40:29.911914 [DQSOSCAuto] RK1, (LSB)MR18= 0x3434, (MSB)MR19= 0x505, tDQSOscB0 = 405 ps tDQSOscB1 = 405 ps
5298 00:40:29.914972 CH0 RK1: MR19=505, MR18=3434
5299 00:40:29.922151 CH0_RK1: MR19=0x505, MR18=0x3434, DQSOSC=405, MR23=63, INC=66, DEC=44
5300 00:40:29.925401 [RxdqsGatingPostProcess] freq 933
5301 00:40:29.928678 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5302 00:40:29.932267 Pre-setting of DQS Precalculation
5303 00:40:29.938024 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5304 00:40:29.938505 ==
5305 00:40:29.941643 Dram Type= 6, Freq= 0, CH_1, rank 0
5306 00:40:29.945034 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5307 00:40:29.945550 ==
5308 00:40:29.951622 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5309 00:40:29.958563 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
5310 00:40:29.962180 [CA 0] Center 37 (7~68) winsize 62
5311 00:40:29.965311 [CA 1] Center 37 (6~68) winsize 63
5312 00:40:29.968082 [CA 2] Center 34 (4~65) winsize 62
5313 00:40:29.971703 [CA 3] Center 34 (4~65) winsize 62
5314 00:40:29.974859 [CA 4] Center 33 (2~64) winsize 63
5315 00:40:29.977934 [CA 5] Center 33 (3~64) winsize 62
5316 00:40:29.978387
5317 00:40:29.980972 [CmdBusTrainingLP45] Vref(ca) range 1: 39
5318 00:40:29.981397
5319 00:40:29.984859 [CATrainingPosCal] consider 1 rank data
5320 00:40:29.988141 u2DelayCellTimex100 = 270/100 ps
5321 00:40:29.991264 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5322 00:40:29.994639 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5323 00:40:29.997966 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5324 00:40:30.001565 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5325 00:40:30.004956 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
5326 00:40:30.008439 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5327 00:40:30.008956
5328 00:40:30.011443 CA PerBit enable=1, Macro0, CA PI delay=33
5329 00:40:30.014538
5330 00:40:30.014970 [CBTSetCACLKResult] CA Dly = 33
5331 00:40:30.018111 CS Dly: 5 (0~36)
5332 00:40:30.018570 ==
5333 00:40:30.021151 Dram Type= 6, Freq= 0, CH_1, rank 1
5334 00:40:30.024446 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5335 00:40:30.024874 ==
5336 00:40:30.031530 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5337 00:40:30.037769 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5338 00:40:30.041063 [CA 0] Center 37 (6~68) winsize 63
5339 00:40:30.044776 [CA 1] Center 37 (6~68) winsize 63
5340 00:40:30.048265 [CA 2] Center 34 (4~65) winsize 62
5341 00:40:30.051142 [CA 3] Center 34 (4~65) winsize 62
5342 00:40:30.054550 [CA 4] Center 33 (2~64) winsize 63
5343 00:40:30.057932 [CA 5] Center 32 (2~63) winsize 62
5344 00:40:30.058433
5345 00:40:30.061431 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5346 00:40:30.062114
5347 00:40:30.064354 [CATrainingPosCal] consider 2 rank data
5348 00:40:30.067787 u2DelayCellTimex100 = 270/100 ps
5349 00:40:30.070825 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5350 00:40:30.074629 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5351 00:40:30.078060 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5352 00:40:30.081145 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5353 00:40:30.084448 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
5354 00:40:30.088273 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5355 00:40:30.088740
5356 00:40:30.091312 CA PerBit enable=1, Macro0, CA PI delay=33
5357 00:40:30.094528
5358 00:40:30.094994 [CBTSetCACLKResult] CA Dly = 33
5359 00:40:30.097720 CS Dly: 5 (0~37)
5360 00:40:30.098184
5361 00:40:30.101023 ----->DramcWriteLeveling(PI) begin...
5362 00:40:30.101503 ==
5363 00:40:30.104252 Dram Type= 6, Freq= 0, CH_1, rank 0
5364 00:40:30.107495 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5365 00:40:30.107967 ==
5366 00:40:30.111164 Write leveling (Byte 0): 24 => 24
5367 00:40:30.113962 Write leveling (Byte 1): 25 => 25
5368 00:40:30.117942 DramcWriteLeveling(PI) end<-----
5369 00:40:30.118450
5370 00:40:30.118760 ==
5371 00:40:30.120993 Dram Type= 6, Freq= 0, CH_1, rank 0
5372 00:40:30.124394 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5373 00:40:30.127849 ==
5374 00:40:30.128316 [Gating] SW mode calibration
5375 00:40:30.133921 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5376 00:40:30.140924 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5377 00:40:30.144492 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5378 00:40:30.150783 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5379 00:40:30.153999 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5380 00:40:30.157516 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5381 00:40:30.163950 0 10 16 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (0 0)
5382 00:40:30.167450 0 10 20 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (1 0)
5383 00:40:30.170676 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5384 00:40:30.177432 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5385 00:40:30.180665 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5386 00:40:30.184287 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5387 00:40:30.190467 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5388 00:40:30.194127 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5389 00:40:30.197351 0 11 16 | B1->B0 | 2323 3232 | 0 1 | (0 0) (0 0)
5390 00:40:30.203955 0 11 20 | B1->B0 | 2626 4646 | 0 0 | (0 0) (0 0)
5391 00:40:30.207040 0 11 24 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
5392 00:40:30.210818 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5393 00:40:30.217509 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5394 00:40:30.220442 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5395 00:40:30.223662 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5396 00:40:30.226838 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5397 00:40:30.233732 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5398 00:40:30.237085 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5399 00:40:30.240528 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5400 00:40:30.247127 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5401 00:40:30.250806 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5402 00:40:30.253652 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5403 00:40:30.260354 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5404 00:40:30.263645 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5405 00:40:30.267202 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5406 00:40:30.273426 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5407 00:40:30.276871 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5408 00:40:30.280114 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5409 00:40:30.286742 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5410 00:40:30.290639 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5411 00:40:30.293639 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5412 00:40:30.300294 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5413 00:40:30.303283 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5414 00:40:30.306734 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5415 00:40:30.310252 Total UI for P1: 0, mck2ui 16
5416 00:40:30.313704 best dqsien dly found for B0: ( 0, 14, 16)
5417 00:40:30.316837 Total UI for P1: 0, mck2ui 16
5418 00:40:30.320287 best dqsien dly found for B1: ( 0, 14, 16)
5419 00:40:30.323286 best DQS0 dly(MCK, UI, PI) = (0, 14, 16)
5420 00:40:30.326746 best DQS1 dly(MCK, UI, PI) = (0, 14, 16)
5421 00:40:30.327135
5422 00:40:30.333453 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 16)
5423 00:40:30.336794 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 16)
5424 00:40:30.337183 [Gating] SW calibration Done
5425 00:40:30.340174 ==
5426 00:40:30.343611 Dram Type= 6, Freq= 0, CH_1, rank 0
5427 00:40:30.346482 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5428 00:40:30.346875 ==
5429 00:40:30.347179 RX Vref Scan: 0
5430 00:40:30.347460
5431 00:40:30.349720 RX Vref 0 -> 0, step: 1
5432 00:40:30.350105
5433 00:40:30.353161 RX Delay -80 -> 252, step: 8
5434 00:40:30.356131 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5435 00:40:30.359855 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5436 00:40:30.366496 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5437 00:40:30.369839 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5438 00:40:30.372947 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5439 00:40:30.376561 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5440 00:40:30.379432 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5441 00:40:30.382661 iDelay=208, Bit 7, Center 95 (-8 ~ 199) 208
5442 00:40:30.389150 iDelay=208, Bit 8, Center 71 (-24 ~ 167) 192
5443 00:40:30.393030 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5444 00:40:30.396089 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5445 00:40:30.399472 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5446 00:40:30.402436 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5447 00:40:30.409197 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5448 00:40:30.412343 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5449 00:40:30.415846 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5450 00:40:30.416340 ==
5451 00:40:30.418751 Dram Type= 6, Freq= 0, CH_1, rank 0
5452 00:40:30.422492 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5453 00:40:30.422912 ==
5454 00:40:30.425755 DQS Delay:
5455 00:40:30.426270 DQS0 = 0, DQS1 = 0
5456 00:40:30.429051 DQM Delay:
5457 00:40:30.429522 DQM0 = 94, DQM1 = 86
5458 00:40:30.429980 DQ Delay:
5459 00:40:30.432376 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =91
5460 00:40:30.435658 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =95
5461 00:40:30.439165 DQ8 =71, DQ9 =75, DQ10 =91, DQ11 =75
5462 00:40:30.442138 DQ12 =95, DQ13 =95, DQ14 =91, DQ15 =99
5463 00:40:30.442555
5464 00:40:30.442860
5465 00:40:30.445340 ==
5466 00:40:30.449040 Dram Type= 6, Freq= 0, CH_1, rank 0
5467 00:40:30.452153 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5468 00:40:30.452620 ==
5469 00:40:30.452948
5470 00:40:30.453246
5471 00:40:30.455110 TX Vref Scan disable
5472 00:40:30.455547 == TX Byte 0 ==
5473 00:40:30.462023 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5474 00:40:30.465317 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5475 00:40:30.465830 == TX Byte 1 ==
5476 00:40:30.471963 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5477 00:40:30.475209 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5478 00:40:30.475914 ==
5479 00:40:30.478464 Dram Type= 6, Freq= 0, CH_1, rank 0
5480 00:40:30.481627 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5481 00:40:30.482073 ==
5482 00:40:30.482502
5483 00:40:30.482826
5484 00:40:30.485098 TX Vref Scan disable
5485 00:40:30.488568 == TX Byte 0 ==
5486 00:40:30.491730 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5487 00:40:30.495255 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5488 00:40:30.498062 == TX Byte 1 ==
5489 00:40:30.501805 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5490 00:40:30.505067 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5491 00:40:30.505542
5492 00:40:30.508093 [DATLAT]
5493 00:40:30.508480 Freq=933, CH1 RK0
5494 00:40:30.508780
5495 00:40:30.511545 DATLAT Default: 0xd
5496 00:40:30.511930 0, 0xFFFF, sum = 0
5497 00:40:30.515276 1, 0xFFFF, sum = 0
5498 00:40:30.515674 2, 0xFFFF, sum = 0
5499 00:40:30.518419 3, 0xFFFF, sum = 0
5500 00:40:30.518812 4, 0xFFFF, sum = 0
5501 00:40:30.521452 5, 0xFFFF, sum = 0
5502 00:40:30.521931 6, 0xFFFF, sum = 0
5503 00:40:30.525134 7, 0xFFFF, sum = 0
5504 00:40:30.525525 8, 0xFFFF, sum = 0
5505 00:40:30.528078 9, 0xFFFF, sum = 0
5506 00:40:30.528474 10, 0x0, sum = 1
5507 00:40:30.531273 11, 0x0, sum = 2
5508 00:40:30.531665 12, 0x0, sum = 3
5509 00:40:30.534543 13, 0x0, sum = 4
5510 00:40:30.534938 best_step = 11
5511 00:40:30.535239
5512 00:40:30.535524 ==
5513 00:40:30.537777 Dram Type= 6, Freq= 0, CH_1, rank 0
5514 00:40:30.544805 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5515 00:40:30.545275 ==
5516 00:40:30.545581 RX Vref Scan: 1
5517 00:40:30.545917
5518 00:40:30.547789 RX Vref 0 -> 0, step: 1
5519 00:40:30.548173
5520 00:40:30.551228 RX Delay -69 -> 252, step: 4
5521 00:40:30.551614
5522 00:40:30.554537 Set Vref, RX VrefLevel [Byte0]: 57
5523 00:40:30.558096 [Byte1]: 50
5524 00:40:30.558614
5525 00:40:30.561199 Final RX Vref Byte 0 = 57 to rank0
5526 00:40:30.564357 Final RX Vref Byte 1 = 50 to rank0
5527 00:40:30.568091 Final RX Vref Byte 0 = 57 to rank1
5528 00:40:30.570941 Final RX Vref Byte 1 = 50 to rank1==
5529 00:40:30.574924 Dram Type= 6, Freq= 0, CH_1, rank 0
5530 00:40:30.577847 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5531 00:40:30.578369 ==
5532 00:40:30.581091 DQS Delay:
5533 00:40:30.581475 DQS0 = 0, DQS1 = 0
5534 00:40:30.583966 DQM Delay:
5535 00:40:30.584371 DQM0 = 93, DQM1 = 88
5536 00:40:30.584681 DQ Delay:
5537 00:40:30.587632 DQ0 =96, DQ1 =90, DQ2 =86, DQ3 =90
5538 00:40:30.590742 DQ4 =94, DQ5 =104, DQ6 =100, DQ7 =90
5539 00:40:30.594066 DQ8 =72, DQ9 =78, DQ10 =88, DQ11 =80
5540 00:40:30.597618 DQ12 =94, DQ13 =98, DQ14 =96, DQ15 =98
5541 00:40:30.598173
5542 00:40:30.598546
5543 00:40:30.607519 [DQSOSCAuto] RK0, (LSB)MR18= 0x3e3e, (MSB)MR19= 0x505, tDQSOscB0 = 402 ps tDQSOscB1 = 402 ps
5544 00:40:30.610681 CH1 RK0: MR19=505, MR18=3E3E
5545 00:40:30.617449 CH1_RK0: MR19=0x505, MR18=0x3E3E, DQSOSC=402, MR23=63, INC=67, DEC=44
5546 00:40:30.617938
5547 00:40:30.620774 ----->DramcWriteLeveling(PI) begin...
5548 00:40:30.621288 ==
5549 00:40:30.624330 Dram Type= 6, Freq= 0, CH_1, rank 1
5550 00:40:30.627413 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5551 00:40:30.627900 ==
5552 00:40:30.630402 Write leveling (Byte 0): 23 => 23
5553 00:40:30.633795 Write leveling (Byte 1): 24 => 24
5554 00:40:30.636990 DramcWriteLeveling(PI) end<-----
5555 00:40:30.637511
5556 00:40:30.637828 ==
5557 00:40:30.640497 Dram Type= 6, Freq= 0, CH_1, rank 1
5558 00:40:30.643588 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5559 00:40:30.643987 ==
5560 00:40:30.647097 [Gating] SW mode calibration
5561 00:40:30.653597 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5562 00:40:30.660550 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5563 00:40:30.663591 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5564 00:40:30.666985 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5565 00:40:30.673740 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5566 00:40:30.676506 0 10 12 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
5567 00:40:30.680384 0 10 16 | B1->B0 | 3434 2a2a | 0 0 | (0 1) (0 0)
5568 00:40:30.686639 0 10 20 | B1->B0 | 3030 2323 | 0 0 | (1 1) (0 0)
5569 00:40:30.690050 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5570 00:40:30.693385 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5571 00:40:30.700183 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5572 00:40:30.703196 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5573 00:40:30.706612 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5574 00:40:30.713216 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5575 00:40:30.716375 0 11 16 | B1->B0 | 2323 3939 | 0 0 | (0 0) (0 0)
5576 00:40:30.719743 0 11 20 | B1->B0 | 3535 4646 | 0 0 | (0 0) (0 0)
5577 00:40:30.726660 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5578 00:40:30.729498 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5579 00:40:30.733282 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5580 00:40:30.739554 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5581 00:40:30.742787 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5582 00:40:30.746576 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5583 00:40:30.752801 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5584 00:40:30.756399 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5585 00:40:30.759395 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5586 00:40:30.766188 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5587 00:40:30.769702 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5588 00:40:30.773189 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5589 00:40:30.779354 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5590 00:40:30.782669 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5591 00:40:30.785990 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5592 00:40:30.793150 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5593 00:40:30.796095 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5594 00:40:30.798998 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5595 00:40:30.805607 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5596 00:40:30.808970 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5597 00:40:30.812444 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5598 00:40:30.818710 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5599 00:40:30.821940 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5600 00:40:30.825489 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5601 00:40:30.828669 Total UI for P1: 0, mck2ui 16
5602 00:40:30.831804 best dqsien dly found for B0: ( 0, 14, 18)
5603 00:40:30.835251 Total UI for P1: 0, mck2ui 16
5604 00:40:30.838207 best dqsien dly found for B1: ( 0, 14, 18)
5605 00:40:30.841667 best DQS0 dly(MCK, UI, PI) = (0, 14, 18)
5606 00:40:30.844919 best DQS1 dly(MCK, UI, PI) = (0, 14, 18)
5607 00:40:30.845097
5608 00:40:30.851801 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 18)
5609 00:40:30.855402 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 18)
5610 00:40:30.855876 [Gating] SW calibration Done
5611 00:40:30.858515 ==
5612 00:40:30.862193 Dram Type= 6, Freq= 0, CH_1, rank 1
5613 00:40:30.865107 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5614 00:40:30.865499 ==
5615 00:40:30.865783 RX Vref Scan: 0
5616 00:40:30.865987
5617 00:40:30.868246 RX Vref 0 -> 0, step: 1
5618 00:40:30.868523
5619 00:40:30.871523 RX Delay -80 -> 252, step: 8
5620 00:40:30.874812 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5621 00:40:30.878202 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5622 00:40:30.881814 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5623 00:40:30.888233 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5624 00:40:30.891524 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5625 00:40:30.894963 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5626 00:40:30.898671 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5627 00:40:30.901690 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5628 00:40:30.905294 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5629 00:40:30.911802 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5630 00:40:30.915452 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5631 00:40:30.918186 iDelay=208, Bit 11, Center 79 (-24 ~ 183) 208
5632 00:40:30.921727 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5633 00:40:30.924934 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5634 00:40:30.929046 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5635 00:40:30.935036 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5636 00:40:30.935438 ==
5637 00:40:30.938755 Dram Type= 6, Freq= 0, CH_1, rank 1
5638 00:40:30.941441 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5639 00:40:30.941831 ==
5640 00:40:30.942140 DQS Delay:
5641 00:40:30.944948 DQS0 = 0, DQS1 = 0
5642 00:40:30.945338 DQM Delay:
5643 00:40:30.948511 DQM0 = 98, DQM1 = 88
5644 00:40:30.948917 DQ Delay:
5645 00:40:30.951872 DQ0 =103, DQ1 =95, DQ2 =87, DQ3 =99
5646 00:40:30.954728 DQ4 =99, DQ5 =107, DQ6 =103, DQ7 =95
5647 00:40:30.958291 DQ8 =75, DQ9 =75, DQ10 =87, DQ11 =79
5648 00:40:30.961808 DQ12 =99, DQ13 =99, DQ14 =95, DQ15 =99
5649 00:40:30.962252
5650 00:40:30.962586
5651 00:40:30.962891 ==
5652 00:40:30.964631 Dram Type= 6, Freq= 0, CH_1, rank 1
5653 00:40:30.967840 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5654 00:40:30.971448 ==
5655 00:40:30.971855
5656 00:40:30.972174
5657 00:40:30.972456 TX Vref Scan disable
5658 00:40:30.974552 == TX Byte 0 ==
5659 00:40:30.978057 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5660 00:40:30.981350 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5661 00:40:30.984286 == TX Byte 1 ==
5662 00:40:30.987861 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5663 00:40:30.991056 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5664 00:40:30.994279 ==
5665 00:40:30.997713 Dram Type= 6, Freq= 0, CH_1, rank 1
5666 00:40:31.000988 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5667 00:40:31.001111 ==
5668 00:40:31.001208
5669 00:40:31.001294
5670 00:40:31.004222 TX Vref Scan disable
5671 00:40:31.004342 == TX Byte 0 ==
5672 00:40:31.010947 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5673 00:40:31.014101 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5674 00:40:31.014243 == TX Byte 1 ==
5675 00:40:31.021560 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5676 00:40:31.024410 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5677 00:40:31.024585
5678 00:40:31.024681 [DATLAT]
5679 00:40:31.027986 Freq=933, CH1 RK1
5680 00:40:31.028102
5681 00:40:31.028187 DATLAT Default: 0xb
5682 00:40:31.030675 0, 0xFFFF, sum = 0
5683 00:40:31.030783 1, 0xFFFF, sum = 0
5684 00:40:31.033881 2, 0xFFFF, sum = 0
5685 00:40:31.033989 3, 0xFFFF, sum = 0
5686 00:40:31.037732 4, 0xFFFF, sum = 0
5687 00:40:31.038132 5, 0xFFFF, sum = 0
5688 00:40:31.041208 6, 0xFFFF, sum = 0
5689 00:40:31.041602 7, 0xFFFF, sum = 0
5690 00:40:31.044288 8, 0xFFFF, sum = 0
5691 00:40:31.047785 9, 0xFFFF, sum = 0
5692 00:40:31.048183 10, 0x0, sum = 1
5693 00:40:31.048495 11, 0x0, sum = 2
5694 00:40:31.051187 12, 0x0, sum = 3
5695 00:40:31.051583 13, 0x0, sum = 4
5696 00:40:31.054310 best_step = 11
5697 00:40:31.054708
5698 00:40:31.055016 ==
5699 00:40:31.057810 Dram Type= 6, Freq= 0, CH_1, rank 1
5700 00:40:31.060852 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5701 00:40:31.061245 ==
5702 00:40:31.064179 RX Vref Scan: 0
5703 00:40:31.064567
5704 00:40:31.064872 RX Vref 0 -> 0, step: 1
5705 00:40:31.065155
5706 00:40:31.067110 RX Delay -69 -> 252, step: 4
5707 00:40:31.075055 iDelay=203, Bit 0, Center 98 (7 ~ 190) 184
5708 00:40:31.078179 iDelay=203, Bit 1, Center 92 (-1 ~ 186) 188
5709 00:40:31.081620 iDelay=203, Bit 2, Center 88 (-5 ~ 182) 188
5710 00:40:31.084696 iDelay=203, Bit 3, Center 92 (-1 ~ 186) 188
5711 00:40:31.087958 iDelay=203, Bit 4, Center 94 (-1 ~ 190) 192
5712 00:40:31.091280 iDelay=203, Bit 5, Center 106 (11 ~ 202) 192
5713 00:40:31.097920 iDelay=203, Bit 6, Center 104 (11 ~ 198) 188
5714 00:40:31.101187 iDelay=203, Bit 7, Center 94 (-1 ~ 190) 192
5715 00:40:31.104262 iDelay=203, Bit 8, Center 74 (-17 ~ 166) 184
5716 00:40:31.107675 iDelay=203, Bit 9, Center 76 (-17 ~ 170) 188
5717 00:40:31.111187 iDelay=203, Bit 10, Center 88 (-5 ~ 182) 188
5718 00:40:31.117588 iDelay=203, Bit 11, Center 80 (-13 ~ 174) 188
5719 00:40:31.121313 iDelay=203, Bit 12, Center 96 (3 ~ 190) 188
5720 00:40:31.124987 iDelay=203, Bit 13, Center 96 (7 ~ 186) 180
5721 00:40:31.127974 iDelay=203, Bit 14, Center 96 (-1 ~ 194) 196
5722 00:40:31.131614 iDelay=203, Bit 15, Center 96 (7 ~ 186) 180
5723 00:40:31.131840 ==
5724 00:40:31.134700 Dram Type= 6, Freq= 0, CH_1, rank 1
5725 00:40:31.141139 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5726 00:40:31.141366 ==
5727 00:40:31.141544 DQS Delay:
5728 00:40:31.144474 DQS0 = 0, DQS1 = 0
5729 00:40:31.144697 DQM Delay:
5730 00:40:31.144875 DQM0 = 96, DQM1 = 87
5731 00:40:31.147743 DQ Delay:
5732 00:40:31.151016 DQ0 =98, DQ1 =92, DQ2 =88, DQ3 =92
5733 00:40:31.154402 DQ4 =94, DQ5 =106, DQ6 =104, DQ7 =94
5734 00:40:31.157837 DQ8 =74, DQ9 =76, DQ10 =88, DQ11 =80
5735 00:40:31.161206 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =96
5736 00:40:31.161650
5737 00:40:31.161939
5738 00:40:31.167654 [DQSOSCAuto] RK1, (LSB)MR18= 0x2525, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 410 ps
5739 00:40:31.171281 CH1 RK1: MR19=505, MR18=2525
5740 00:40:31.177943 CH1_RK1: MR19=0x505, MR18=0x2525, DQSOSC=410, MR23=63, INC=64, DEC=42
5741 00:40:31.180830 [RxdqsGatingPostProcess] freq 933
5742 00:40:31.184424 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5743 00:40:31.187490 Pre-setting of DQS Precalculation
5744 00:40:31.194177 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5745 00:40:31.200706 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5746 00:40:31.207636 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5747 00:40:31.208029
5748 00:40:31.208337
5749 00:40:31.210769 [Calibration Summary] 1866 Mbps
5750 00:40:31.214318 CH 0, Rank 0
5751 00:40:31.214713 SW Impedance : PASS
5752 00:40:31.217367 DUTY Scan : NO K
5753 00:40:31.220719 ZQ Calibration : PASS
5754 00:40:31.221260 Jitter Meter : NO K
5755 00:40:31.224064 CBT Training : PASS
5756 00:40:31.227362 Write leveling : PASS
5757 00:40:31.227790 RX DQS gating : PASS
5758 00:40:31.230718 RX DQ/DQS(RDDQC) : PASS
5759 00:40:31.231114 TX DQ/DQS : PASS
5760 00:40:31.233908 RX DATLAT : PASS
5761 00:40:31.237460 RX DQ/DQS(Engine): PASS
5762 00:40:31.238065 TX OE : NO K
5763 00:40:31.240244 All Pass.
5764 00:40:31.240636
5765 00:40:31.240945 CH 0, Rank 1
5766 00:40:31.243756 SW Impedance : PASS
5767 00:40:31.244150 DUTY Scan : NO K
5768 00:40:31.246891 ZQ Calibration : PASS
5769 00:40:31.250812 Jitter Meter : NO K
5770 00:40:31.251217 CBT Training : PASS
5771 00:40:31.253947 Write leveling : PASS
5772 00:40:31.257055 RX DQS gating : PASS
5773 00:40:31.257451 RX DQ/DQS(RDDQC) : PASS
5774 00:40:31.260384 TX DQ/DQS : PASS
5775 00:40:31.263674 RX DATLAT : PASS
5776 00:40:31.264069 RX DQ/DQS(Engine): PASS
5777 00:40:31.267098 TX OE : NO K
5778 00:40:31.267495 All Pass.
5779 00:40:31.267922
5780 00:40:31.270519 CH 1, Rank 0
5781 00:40:31.270911 SW Impedance : PASS
5782 00:40:31.273687 DUTY Scan : NO K
5783 00:40:31.276699 ZQ Calibration : PASS
5784 00:40:31.276980 Jitter Meter : NO K
5785 00:40:31.280013 CBT Training : PASS
5786 00:40:31.283640 Write leveling : PASS
5787 00:40:31.283852 RX DQS gating : PASS
5788 00:40:31.286576 RX DQ/DQS(RDDQC) : PASS
5789 00:40:31.286746 TX DQ/DQS : PASS
5790 00:40:31.289833 RX DATLAT : PASS
5791 00:40:31.293205 RX DQ/DQS(Engine): PASS
5792 00:40:31.293348 TX OE : NO K
5793 00:40:31.296602 All Pass.
5794 00:40:31.296723
5795 00:40:31.296819 CH 1, Rank 1
5796 00:40:31.299897 SW Impedance : PASS
5797 00:40:31.300020 DUTY Scan : NO K
5798 00:40:31.303320 ZQ Calibration : PASS
5799 00:40:31.306815 Jitter Meter : NO K
5800 00:40:31.306912 CBT Training : PASS
5801 00:40:31.310318 Write leveling : PASS
5802 00:40:31.313265 RX DQS gating : PASS
5803 00:40:31.313350 RX DQ/DQS(RDDQC) : PASS
5804 00:40:31.316542 TX DQ/DQS : PASS
5805 00:40:31.320165 RX DATLAT : PASS
5806 00:40:31.320244 RX DQ/DQS(Engine): PASS
5807 00:40:31.323695 TX OE : NO K
5808 00:40:31.323772 All Pass.
5809 00:40:31.323833
5810 00:40:31.326566 DramC Write-DBI off
5811 00:40:31.329850 PER_BANK_REFRESH: Hybrid Mode
5812 00:40:31.329927 TX_TRACKING: ON
5813 00:40:31.340454 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
5814 00:40:31.343362 [FAST_K] Save calibration result to emmc
5815 00:40:31.346919 dramc_set_vcore_voltage set vcore to 650000
5816 00:40:31.350012 Read voltage for 400, 6
5817 00:40:31.350481 Vio18 = 0
5818 00:40:31.350795 Vcore = 650000
5819 00:40:31.353256 Vdram = 0
5820 00:40:31.353645 Vddq = 0
5821 00:40:31.353952 Vmddr = 0
5822 00:40:31.360001 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
5823 00:40:31.363497 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
5824 00:40:31.366961 MEM_TYPE=3, freq_sel=20
5825 00:40:31.370137 sv_algorithm_assistance_LP4_800
5826 00:40:31.373320 ============ PULL DRAM RESETB DOWN ============
5827 00:40:31.376880 ========== PULL DRAM RESETB DOWN end =========
5828 00:40:31.383474 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5829 00:40:31.386529 ===================================
5830 00:40:31.387009 LPDDR4 DRAM CONFIGURATION
5831 00:40:31.389829 ===================================
5832 00:40:31.393531 EX_ROW_EN[0] = 0x0
5833 00:40:31.396679 EX_ROW_EN[1] = 0x0
5834 00:40:31.397070 LP4Y_EN = 0x0
5835 00:40:31.400255 WORK_FSP = 0x0
5836 00:40:31.400677 WL = 0x2
5837 00:40:31.403371 RL = 0x2
5838 00:40:31.403760 BL = 0x2
5839 00:40:31.406639 RPST = 0x0
5840 00:40:31.407076 RD_PRE = 0x0
5841 00:40:31.410012 WR_PRE = 0x1
5842 00:40:31.410449 WR_PST = 0x0
5843 00:40:31.413246 DBI_WR = 0x0
5844 00:40:31.413639 DBI_RD = 0x0
5845 00:40:31.416666 OTF = 0x1
5846 00:40:31.420030 ===================================
5847 00:40:31.423076 ===================================
5848 00:40:31.423472 ANA top config
5849 00:40:31.426467 ===================================
5850 00:40:31.430074 DLL_ASYNC_EN = 0
5851 00:40:31.433188 ALL_SLAVE_EN = 1
5852 00:40:31.433577 NEW_RANK_MODE = 1
5853 00:40:31.436705 DLL_IDLE_MODE = 1
5854 00:40:31.439972 LP45_APHY_COMB_EN = 1
5855 00:40:31.443511 TX_ODT_DIS = 1
5856 00:40:31.446768 NEW_8X_MODE = 1
5857 00:40:31.449574 ===================================
5858 00:40:31.453334 ===================================
5859 00:40:31.453983 data_rate = 800
5860 00:40:31.456448 CKR = 1
5861 00:40:31.459656 DQ_P2S_RATIO = 4
5862 00:40:31.463595 ===================================
5863 00:40:31.466202 CA_P2S_RATIO = 4
5864 00:40:31.469551 DQ_CA_OPEN = 0
5865 00:40:31.472710 DQ_SEMI_OPEN = 1
5866 00:40:31.472921 CA_SEMI_OPEN = 1
5867 00:40:31.476164 CA_FULL_RATE = 0
5868 00:40:31.479367 DQ_CKDIV4_EN = 0
5869 00:40:31.482516 CA_CKDIV4_EN = 1
5870 00:40:31.485928 CA_PREDIV_EN = 0
5871 00:40:31.488968 PH8_DLY = 0
5872 00:40:31.489090 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
5873 00:40:31.492641 DQ_AAMCK_DIV = 0
5874 00:40:31.496355 CA_AAMCK_DIV = 0
5875 00:40:31.499305 CA_ADMCK_DIV = 4
5876 00:40:31.502174 DQ_TRACK_CA_EN = 0
5877 00:40:31.505737 CA_PICK = 800
5878 00:40:31.508967 CA_MCKIO = 400
5879 00:40:31.509052 MCKIO_SEMI = 400
5880 00:40:31.512477 PLL_FREQ = 3016
5881 00:40:31.515381 DQ_UI_PI_RATIO = 32
5882 00:40:31.518828 CA_UI_PI_RATIO = 32
5883 00:40:31.522040 ===================================
5884 00:40:31.525450 ===================================
5885 00:40:31.528879 memory_type:LPDDR4
5886 00:40:31.528964 GP_NUM : 10
5887 00:40:31.532150 SRAM_EN : 1
5888 00:40:31.535341 MD32_EN : 0
5889 00:40:31.538888 ===================================
5890 00:40:31.539009 [ANA_INIT] >>>>>>>>>>>>>>
5891 00:40:31.542205 <<<<<< [CONFIGURE PHASE]: ANA_TX
5892 00:40:31.545477 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5893 00:40:31.548679 ===================================
5894 00:40:31.552220 data_rate = 800,PCW = 0X7400
5895 00:40:31.555922 ===================================
5896 00:40:31.558989 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5897 00:40:31.565341 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5898 00:40:31.575871 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5899 00:40:31.582371 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5900 00:40:31.585318 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5901 00:40:31.589104 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5902 00:40:31.589618 [ANA_INIT] flow start
5903 00:40:31.592183 [ANA_INIT] PLL >>>>>>>>
5904 00:40:31.595979 [ANA_INIT] PLL <<<<<<<<
5905 00:40:31.596411 [ANA_INIT] MIDPI >>>>>>>>
5906 00:40:31.598883 [ANA_INIT] MIDPI <<<<<<<<
5907 00:40:31.602465 [ANA_INIT] DLL >>>>>>>>
5908 00:40:31.602899 [ANA_INIT] flow end
5909 00:40:31.608870 ============ LP4 DIFF to SE enter ============
5910 00:40:31.612243 ============ LP4 DIFF to SE exit ============
5911 00:40:31.615617 [ANA_INIT] <<<<<<<<<<<<<
5912 00:40:31.618710 [Flow] Enable top DCM control >>>>>
5913 00:40:31.622151 [Flow] Enable top DCM control <<<<<
5914 00:40:31.622663 Enable DLL master slave shuffle
5915 00:40:31.628735 ==============================================================
5916 00:40:31.631759 Gating Mode config
5917 00:40:31.634899 ==============================================================
5918 00:40:31.638656 Config description:
5919 00:40:31.648397 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5920 00:40:31.654831 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5921 00:40:31.658541 SELPH_MODE 0: By rank 1: By Phase
5922 00:40:31.665141 ==============================================================
5923 00:40:31.668347 GAT_TRACK_EN = 0
5924 00:40:31.671684 RX_GATING_MODE = 2
5925 00:40:31.675101 RX_GATING_TRACK_MODE = 2
5926 00:40:31.678353 SELPH_MODE = 1
5927 00:40:31.678874 PICG_EARLY_EN = 1
5928 00:40:31.681435 VALID_LAT_VALUE = 1
5929 00:40:31.688059 ==============================================================
5930 00:40:31.691971 Enter into Gating configuration >>>>
5931 00:40:31.694651 Exit from Gating configuration <<<<
5932 00:40:31.698013 Enter into DVFS_PRE_config >>>>>
5933 00:40:31.708337 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5934 00:40:31.711265 Exit from DVFS_PRE_config <<<<<
5935 00:40:31.715132 Enter into PICG configuration >>>>
5936 00:40:31.718109 Exit from PICG configuration <<<<
5937 00:40:31.721726 [RX_INPUT] configuration >>>>>
5938 00:40:31.724900 [RX_INPUT] configuration <<<<<
5939 00:40:31.728007 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5940 00:40:31.734805 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5941 00:40:31.741416 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5942 00:40:31.747981 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5943 00:40:31.754474 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5944 00:40:31.761255 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5945 00:40:31.764573 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5946 00:40:31.767644 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5947 00:40:31.771205 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5948 00:40:31.774308 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5949 00:40:31.781401 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5950 00:40:31.784492 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5951 00:40:31.787873 ===================================
5952 00:40:31.790790 LPDDR4 DRAM CONFIGURATION
5953 00:40:31.793909 ===================================
5954 00:40:31.794398 EX_ROW_EN[0] = 0x0
5955 00:40:31.797502 EX_ROW_EN[1] = 0x0
5956 00:40:31.797951 LP4Y_EN = 0x0
5957 00:40:31.800733 WORK_FSP = 0x0
5958 00:40:31.801184 WL = 0x2
5959 00:40:31.804591 RL = 0x2
5960 00:40:31.805130 BL = 0x2
5961 00:40:31.807505 RPST = 0x0
5962 00:40:31.810817 RD_PRE = 0x0
5963 00:40:31.811352 WR_PRE = 0x1
5964 00:40:31.813917 WR_PST = 0x0
5965 00:40:31.814395 DBI_WR = 0x0
5966 00:40:31.817438 DBI_RD = 0x0
5967 00:40:31.817955 OTF = 0x1
5968 00:40:31.820846 ===================================
5969 00:40:31.824027 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5970 00:40:31.830763 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5971 00:40:31.834479 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5972 00:40:31.837454 ===================================
5973 00:40:31.840446 LPDDR4 DRAM CONFIGURATION
5974 00:40:31.843788 ===================================
5975 00:40:31.844306 EX_ROW_EN[0] = 0x10
5976 00:40:31.847536 EX_ROW_EN[1] = 0x0
5977 00:40:31.848056 LP4Y_EN = 0x0
5978 00:40:31.850439 WORK_FSP = 0x0
5979 00:40:31.850883 WL = 0x2
5980 00:40:31.853698 RL = 0x2
5981 00:40:31.854132 BL = 0x2
5982 00:40:31.857121 RPST = 0x0
5983 00:40:31.857553 RD_PRE = 0x0
5984 00:40:31.861066 WR_PRE = 0x1
5985 00:40:31.863592 WR_PST = 0x0
5986 00:40:31.864030 DBI_WR = 0x0
5987 00:40:31.867072 DBI_RD = 0x0
5988 00:40:31.867560 OTF = 0x1
5989 00:40:31.870651 ===================================
5990 00:40:31.877145 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5991 00:40:31.880765 nWR fixed to 30
5992 00:40:31.884272 [ModeRegInit_LP4] CH0 RK0
5993 00:40:31.884802 [ModeRegInit_LP4] CH0 RK1
5994 00:40:31.887177 [ModeRegInit_LP4] CH1 RK0
5995 00:40:31.890516 [ModeRegInit_LP4] CH1 RK1
5996 00:40:31.890955 match AC timing 18
5997 00:40:31.897431 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 0
5998 00:40:31.900951 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5999 00:40:31.904437 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6000 00:40:31.910752 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6001 00:40:31.913930 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6002 00:40:31.914504 ==
6003 00:40:31.917161 Dram Type= 6, Freq= 0, CH_0, rank 0
6004 00:40:31.920293 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6005 00:40:31.920830 ==
6006 00:40:31.926886 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6007 00:40:31.933646 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6008 00:40:31.936968 [CA 0] Center 36 (8~64) winsize 57
6009 00:40:31.940245 [CA 1] Center 36 (8~64) winsize 57
6010 00:40:31.943594 [CA 2] Center 36 (8~64) winsize 57
6011 00:40:31.946677 [CA 3] Center 36 (8~64) winsize 57
6012 00:40:31.947110 [CA 4] Center 36 (8~64) winsize 57
6013 00:40:31.950397 [CA 5] Center 36 (8~64) winsize 57
6014 00:40:31.950831
6015 00:40:31.956799 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6016 00:40:31.957320
6017 00:40:31.960383 [CATrainingPosCal] consider 1 rank data
6018 00:40:31.963665 u2DelayCellTimex100 = 270/100 ps
6019 00:40:31.966692 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6020 00:40:31.970260 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6021 00:40:31.973704 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6022 00:40:31.977096 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6023 00:40:31.980288 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6024 00:40:31.983280 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6025 00:40:31.983789
6026 00:40:31.986848 CA PerBit enable=1, Macro0, CA PI delay=36
6027 00:40:31.987280
6028 00:40:31.989832 [CBTSetCACLKResult] CA Dly = 36
6029 00:40:31.993612 CS Dly: 1 (0~32)
6030 00:40:31.994129 ==
6031 00:40:31.997100 Dram Type= 6, Freq= 0, CH_0, rank 1
6032 00:40:32.000266 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6033 00:40:32.000790 ==
6034 00:40:32.006528 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6035 00:40:32.013183 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6036 00:40:32.013695 [CA 0] Center 36 (8~64) winsize 57
6037 00:40:32.016559 [CA 1] Center 36 (8~64) winsize 57
6038 00:40:32.020111 [CA 2] Center 36 (8~64) winsize 57
6039 00:40:32.023049 [CA 3] Center 36 (8~64) winsize 57
6040 00:40:32.026366 [CA 4] Center 36 (8~64) winsize 57
6041 00:40:32.030100 [CA 5] Center 36 (8~64) winsize 57
6042 00:40:32.030658
6043 00:40:32.032999 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6044 00:40:32.033433
6045 00:40:32.036582 [CATrainingPosCal] consider 2 rank data
6046 00:40:32.039682 u2DelayCellTimex100 = 270/100 ps
6047 00:40:32.042881 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6048 00:40:32.049356 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6049 00:40:32.053125 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6050 00:40:32.056190 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6051 00:40:32.059500 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6052 00:40:32.062577 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6053 00:40:32.063008
6054 00:40:32.066475 CA PerBit enable=1, Macro0, CA PI delay=36
6055 00:40:32.066908
6056 00:40:32.069220 [CBTSetCACLKResult] CA Dly = 36
6057 00:40:32.069653 CS Dly: 1 (0~32)
6058 00:40:32.073166
6059 00:40:32.076012 ----->DramcWriteLeveling(PI) begin...
6060 00:40:32.076451 ==
6061 00:40:32.079748 Dram Type= 6, Freq= 0, CH_0, rank 0
6062 00:40:32.082974 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6063 00:40:32.083508 ==
6064 00:40:32.085923 Write leveling (Byte 0): 32 => 0
6065 00:40:32.089304 Write leveling (Byte 1): 32 => 0
6066 00:40:32.092694 DramcWriteLeveling(PI) end<-----
6067 00:40:32.093200
6068 00:40:32.093540 ==
6069 00:40:32.096141 Dram Type= 6, Freq= 0, CH_0, rank 0
6070 00:40:32.099066 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6071 00:40:32.099500 ==
6072 00:40:32.102466 [Gating] SW mode calibration
6073 00:40:32.109104 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6074 00:40:32.116099 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6075 00:40:32.119159 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6076 00:40:32.122868 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6077 00:40:32.129246 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6078 00:40:32.132668 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
6079 00:40:32.135584 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6080 00:40:32.142166 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6081 00:40:32.145836 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6082 00:40:32.149413 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
6083 00:40:32.155615 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6084 00:40:32.156133 Total UI for P1: 0, mck2ui 16
6085 00:40:32.158863 best dqsien dly found for B0: ( 0, 10, 16)
6086 00:40:32.162119 Total UI for P1: 0, mck2ui 16
6087 00:40:32.165853 best dqsien dly found for B1: ( 0, 10, 24)
6088 00:40:32.169253 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6089 00:40:32.175224 best DQS1 dly(MCK, UI, PI) = (0, 10, 24)
6090 00:40:32.175718
6091 00:40:32.178863 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6092 00:40:32.182153 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 24)
6093 00:40:32.185340 [Gating] SW calibration Done
6094 00:40:32.185902 ==
6095 00:40:32.188871 Dram Type= 6, Freq= 0, CH_0, rank 0
6096 00:40:32.192026 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6097 00:40:32.192463 ==
6098 00:40:32.195154 RX Vref Scan: 0
6099 00:40:32.195582
6100 00:40:32.195921 RX Vref 0 -> 0, step: 1
6101 00:40:32.196238
6102 00:40:32.198450 RX Delay -410 -> 252, step: 16
6103 00:40:32.205168 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6104 00:40:32.208206 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6105 00:40:32.211719 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6106 00:40:32.215110 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6107 00:40:32.221714 iDelay=230, Bit 4, Center -35 (-298 ~ 229) 528
6108 00:40:32.225055 iDelay=230, Bit 5, Center -51 (-298 ~ 197) 496
6109 00:40:32.228179 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6110 00:40:32.231539 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6111 00:40:32.238392 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6112 00:40:32.241456 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6113 00:40:32.244912 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6114 00:40:32.248257 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6115 00:40:32.254763 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6116 00:40:32.258194 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6117 00:40:32.261533 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6118 00:40:32.268359 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6119 00:40:32.268879 ==
6120 00:40:32.271005 Dram Type= 6, Freq= 0, CH_0, rank 0
6121 00:40:32.274731 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6122 00:40:32.275244 ==
6123 00:40:32.275588 DQS Delay:
6124 00:40:32.278142 DQS0 = 51, DQS1 = 59
6125 00:40:32.278685 DQM Delay:
6126 00:40:32.281082 DQM0 = 12, DQM1 = 16
6127 00:40:32.281511 DQ Delay:
6128 00:40:32.284422 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6129 00:40:32.287692 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6130 00:40:32.291598 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6131 00:40:32.294632 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6132 00:40:32.295067
6133 00:40:32.295431
6134 00:40:32.295749 ==
6135 00:40:32.297416 Dram Type= 6, Freq= 0, CH_0, rank 0
6136 00:40:32.300993 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6137 00:40:32.301510 ==
6138 00:40:32.301855
6139 00:40:32.302164
6140 00:40:32.304587 TX Vref Scan disable
6141 00:40:32.305096 == TX Byte 0 ==
6142 00:40:32.311448 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6143 00:40:32.314531 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6144 00:40:32.315045 == TX Byte 1 ==
6145 00:40:32.321225 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6146 00:40:32.324299 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6147 00:40:32.324733 ==
6148 00:40:32.327679 Dram Type= 6, Freq= 0, CH_0, rank 0
6149 00:40:32.330934 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6150 00:40:32.331370 ==
6151 00:40:32.331711
6152 00:40:32.332018
6153 00:40:32.334378 TX Vref Scan disable
6154 00:40:32.337680 == TX Byte 0 ==
6155 00:40:32.340817 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6156 00:40:32.344717 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6157 00:40:32.347342 == TX Byte 1 ==
6158 00:40:32.351359 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6159 00:40:32.354508 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6160 00:40:32.355025
6161 00:40:32.355363 [DATLAT]
6162 00:40:32.357792 Freq=400, CH0 RK0
6163 00:40:32.358350
6164 00:40:32.358699 DATLAT Default: 0xf
6165 00:40:32.360884 0, 0xFFFF, sum = 0
6166 00:40:32.364432 1, 0xFFFF, sum = 0
6167 00:40:32.364956 2, 0xFFFF, sum = 0
6168 00:40:32.367486 3, 0xFFFF, sum = 0
6169 00:40:32.367925 4, 0xFFFF, sum = 0
6170 00:40:32.371202 5, 0xFFFF, sum = 0
6171 00:40:32.371725 6, 0xFFFF, sum = 0
6172 00:40:32.374399 7, 0xFFFF, sum = 0
6173 00:40:32.374924 8, 0xFFFF, sum = 0
6174 00:40:32.377540 9, 0xFFFF, sum = 0
6175 00:40:32.378059 10, 0xFFFF, sum = 0
6176 00:40:32.381110 11, 0xFFFF, sum = 0
6177 00:40:32.381631 12, 0x0, sum = 1
6178 00:40:32.384104 13, 0x0, sum = 2
6179 00:40:32.384595 14, 0x0, sum = 3
6180 00:40:32.387134 15, 0x0, sum = 4
6181 00:40:32.387573 best_step = 13
6182 00:40:32.387911
6183 00:40:32.388223 ==
6184 00:40:32.390676 Dram Type= 6, Freq= 0, CH_0, rank 0
6185 00:40:32.394001 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6186 00:40:32.397115 ==
6187 00:40:32.397546 RX Vref Scan: 1
6188 00:40:32.397883
6189 00:40:32.400468 RX Vref 0 -> 0, step: 1
6190 00:40:32.400895
6191 00:40:32.404072 RX Delay -359 -> 252, step: 8
6192 00:40:32.404530
6193 00:40:32.407530 Set Vref, RX VrefLevel [Byte0]: 46
6194 00:40:32.410625 [Byte1]: 50
6195 00:40:32.411054
6196 00:40:32.413854 Final RX Vref Byte 0 = 46 to rank0
6197 00:40:32.417464 Final RX Vref Byte 1 = 50 to rank0
6198 00:40:32.420555 Final RX Vref Byte 0 = 46 to rank1
6199 00:40:32.424085 Final RX Vref Byte 1 = 50 to rank1==
6200 00:40:32.427227 Dram Type= 6, Freq= 0, CH_0, rank 0
6201 00:40:32.430764 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6202 00:40:32.431284 ==
6203 00:40:32.433591 DQS Delay:
6204 00:40:32.434106 DQS0 = 52, DQS1 = 68
6205 00:40:32.436786 DQM Delay:
6206 00:40:32.437214 DQM0 = 8, DQM1 = 16
6207 00:40:32.437548 DQ Delay:
6208 00:40:32.440198 DQ0 =4, DQ1 =8, DQ2 =4, DQ3 =4
6209 00:40:32.443647 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =20
6210 00:40:32.446916 DQ8 =8, DQ9 =0, DQ10 =12, DQ11 =8
6211 00:40:32.450201 DQ12 =24, DQ13 =24, DQ14 =28, DQ15 =28
6212 00:40:32.450693
6213 00:40:32.451029
6214 00:40:32.460407 [DQSOSCAuto] RK0, (LSB)MR18= 0xaaaa, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 388 ps
6215 00:40:32.460929 CH0 RK0: MR19=C0C, MR18=AAAA
6216 00:40:32.467307 CH0_RK0: MR19=0xC0C, MR18=0xAAAA, DQSOSC=388, MR23=63, INC=392, DEC=261
6217 00:40:32.467828 ==
6218 00:40:32.470291 Dram Type= 6, Freq= 0, CH_0, rank 1
6219 00:40:32.476780 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6220 00:40:32.477308 ==
6221 00:40:32.480389 [Gating] SW mode calibration
6222 00:40:32.487026 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6223 00:40:32.490555 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6224 00:40:32.497182 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6225 00:40:32.499945 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6226 00:40:32.503468 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6227 00:40:32.510076 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
6228 00:40:32.513205 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6229 00:40:32.516583 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6230 00:40:32.523690 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6231 00:40:32.526843 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
6232 00:40:32.529723 Total UI for P1: 0, mck2ui 16
6233 00:40:32.533089 best dqsien dly found for B0: ( 0, 10, 8)
6234 00:40:32.536695 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6235 00:40:32.540024 Total UI for P1: 0, mck2ui 16
6236 00:40:32.542905 best dqsien dly found for B1: ( 0, 10, 16)
6237 00:40:32.546974 best DQS0 dly(MCK, UI, PI) = (0, 10, 8)
6238 00:40:32.549699 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6239 00:40:32.550130
6240 00:40:32.552876 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 8)
6241 00:40:32.559740 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6242 00:40:32.560244 [Gating] SW calibration Done
6243 00:40:32.562738 ==
6244 00:40:32.563172 Dram Type= 6, Freq= 0, CH_0, rank 1
6245 00:40:32.569373 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6246 00:40:32.569948 ==
6247 00:40:32.570348 RX Vref Scan: 0
6248 00:40:32.570677
6249 00:40:32.572951 RX Vref 0 -> 0, step: 1
6250 00:40:32.573381
6251 00:40:32.576370 RX Delay -410 -> 252, step: 16
6252 00:40:32.579647 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6253 00:40:32.582764 iDelay=230, Bit 1, Center -27 (-282 ~ 229) 512
6254 00:40:32.589559 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6255 00:40:32.592430 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6256 00:40:32.596439 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6257 00:40:32.599445 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6258 00:40:32.606008 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6259 00:40:32.609123 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6260 00:40:32.612929 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6261 00:40:32.616221 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6262 00:40:32.622476 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6263 00:40:32.625942 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6264 00:40:32.629012 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6265 00:40:32.635529 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6266 00:40:32.638799 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6267 00:40:32.642494 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6268 00:40:32.642968 ==
6269 00:40:32.645728 Dram Type= 6, Freq= 0, CH_0, rank 1
6270 00:40:32.649070 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6271 00:40:32.652439 ==
6272 00:40:32.652957 DQS Delay:
6273 00:40:32.653298 DQS0 = 43, DQS1 = 59
6274 00:40:32.655331 DQM Delay:
6275 00:40:32.655762 DQM0 = 8, DQM1 = 16
6276 00:40:32.658646 DQ Delay:
6277 00:40:32.659078 DQ0 =0, DQ1 =16, DQ2 =0, DQ3 =0
6278 00:40:32.662411 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6279 00:40:32.665398 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6280 00:40:32.668924 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6281 00:40:32.669437
6282 00:40:32.669824
6283 00:40:32.672121 ==
6284 00:40:32.672555 Dram Type= 6, Freq= 0, CH_0, rank 1
6285 00:40:32.678617 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6286 00:40:32.679054 ==
6287 00:40:32.679395
6288 00:40:32.679704
6289 00:40:32.682133 TX Vref Scan disable
6290 00:40:32.682878 == TX Byte 0 ==
6291 00:40:32.685670 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6292 00:40:32.692096 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6293 00:40:32.692612 == TX Byte 1 ==
6294 00:40:32.695445 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6295 00:40:32.698762 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6296 00:40:32.702016 ==
6297 00:40:32.705477 Dram Type= 6, Freq= 0, CH_0, rank 1
6298 00:40:32.708374 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6299 00:40:32.708810 ==
6300 00:40:32.709167
6301 00:40:32.709481
6302 00:40:32.711925 TX Vref Scan disable
6303 00:40:32.712441 == TX Byte 0 ==
6304 00:40:32.715490 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6305 00:40:32.721948 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6306 00:40:32.722565 == TX Byte 1 ==
6307 00:40:32.725169 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6308 00:40:32.731837 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6309 00:40:32.732356
6310 00:40:32.732699 [DATLAT]
6311 00:40:32.733010 Freq=400, CH0 RK1
6312 00:40:32.733309
6313 00:40:32.734896 DATLAT Default: 0xd
6314 00:40:32.738277 0, 0xFFFF, sum = 0
6315 00:40:32.738803 1, 0xFFFF, sum = 0
6316 00:40:32.741259 2, 0xFFFF, sum = 0
6317 00:40:32.741699 3, 0xFFFF, sum = 0
6318 00:40:32.744563 4, 0xFFFF, sum = 0
6319 00:40:32.745001 5, 0xFFFF, sum = 0
6320 00:40:32.747923 6, 0xFFFF, sum = 0
6321 00:40:32.748361 7, 0xFFFF, sum = 0
6322 00:40:32.751364 8, 0xFFFF, sum = 0
6323 00:40:32.751802 9, 0xFFFF, sum = 0
6324 00:40:32.754568 10, 0xFFFF, sum = 0
6325 00:40:32.755009 11, 0xFFFF, sum = 0
6326 00:40:32.757981 12, 0x0, sum = 1
6327 00:40:32.758529 13, 0x0, sum = 2
6328 00:40:32.760969 14, 0x0, sum = 3
6329 00:40:32.761409 15, 0x0, sum = 4
6330 00:40:32.764366 best_step = 13
6331 00:40:32.764797
6332 00:40:32.765131 ==
6333 00:40:32.767670 Dram Type= 6, Freq= 0, CH_0, rank 1
6334 00:40:32.770868 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6335 00:40:32.771302 ==
6336 00:40:32.774295 RX Vref Scan: 0
6337 00:40:32.774727
6338 00:40:32.775065 RX Vref 0 -> 0, step: 1
6339 00:40:32.775376
6340 00:40:32.777908 RX Delay -359 -> 252, step: 8
6341 00:40:32.785165 iDelay=217, Bit 0, Center -44 (-287 ~ 200) 488
6342 00:40:32.788310 iDelay=217, Bit 1, Center -40 (-287 ~ 208) 496
6343 00:40:32.791797 iDelay=217, Bit 2, Center -44 (-295 ~ 208) 504
6344 00:40:32.795056 iDelay=217, Bit 3, Center -44 (-287 ~ 200) 488
6345 00:40:32.801932 iDelay=217, Bit 4, Center -40 (-287 ~ 208) 496
6346 00:40:32.805498 iDelay=217, Bit 5, Center -52 (-303 ~ 200) 504
6347 00:40:32.808940 iDelay=217, Bit 6, Center -32 (-279 ~ 216) 496
6348 00:40:32.812348 iDelay=217, Bit 7, Center -32 (-279 ~ 216) 496
6349 00:40:32.818605 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6350 00:40:32.822151 iDelay=217, Bit 9, Center -64 (-311 ~ 184) 496
6351 00:40:32.825485 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6352 00:40:32.828298 iDelay=217, Bit 11, Center -60 (-303 ~ 184) 488
6353 00:40:32.835382 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6354 00:40:32.838498 iDelay=217, Bit 13, Center -44 (-287 ~ 200) 488
6355 00:40:32.841752 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6356 00:40:32.848668 iDelay=217, Bit 15, Center -44 (-287 ~ 200) 488
6357 00:40:32.849182 ==
6358 00:40:32.851934 Dram Type= 6, Freq= 0, CH_0, rank 1
6359 00:40:32.855484 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6360 00:40:32.855960 ==
6361 00:40:32.856298 DQS Delay:
6362 00:40:32.858399 DQS0 = 52, DQS1 = 64
6363 00:40:32.858828 DQM Delay:
6364 00:40:32.861873 DQM0 = 11, DQM1 = 13
6365 00:40:32.862346 DQ Delay:
6366 00:40:32.865320 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =8
6367 00:40:32.868172 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6368 00:40:32.872019 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =4
6369 00:40:32.874774 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =20
6370 00:40:32.875227
6371 00:40:32.875591
6372 00:40:32.881772 [DQSOSCAuto] RK1, (LSB)MR18= 0xd0d0, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 384 ps
6373 00:40:32.884937 CH0 RK1: MR19=C0C, MR18=D0D0
6374 00:40:32.891693 CH0_RK1: MR19=0xC0C, MR18=0xD0D0, DQSOSC=384, MR23=63, INC=400, DEC=267
6375 00:40:32.894563 [RxdqsGatingPostProcess] freq 400
6376 00:40:32.901096 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6377 00:40:32.904641 Pre-setting of DQS Precalculation
6378 00:40:32.907675 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6379 00:40:32.908158 ==
6380 00:40:32.911798 Dram Type= 6, Freq= 0, CH_1, rank 0
6381 00:40:32.914784 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6382 00:40:32.915424 ==
6383 00:40:32.921688 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6384 00:40:32.928029 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
6385 00:40:32.931429 [CA 0] Center 36 (8~64) winsize 57
6386 00:40:32.934796 [CA 1] Center 36 (8~64) winsize 57
6387 00:40:32.937790 [CA 2] Center 36 (8~64) winsize 57
6388 00:40:32.941317 [CA 3] Center 36 (8~64) winsize 57
6389 00:40:32.941758 [CA 4] Center 36 (8~64) winsize 57
6390 00:40:32.944474 [CA 5] Center 36 (8~64) winsize 57
6391 00:40:32.945076
6392 00:40:32.951516 [CmdBusTrainingLP45] Vref(ca) range 1: 39
6393 00:40:32.952037
6394 00:40:32.954403 [CATrainingPosCal] consider 1 rank data
6395 00:40:32.957699 u2DelayCellTimex100 = 270/100 ps
6396 00:40:32.960950 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6397 00:40:32.963998 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6398 00:40:32.967526 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6399 00:40:32.971274 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6400 00:40:32.974407 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6401 00:40:32.977698 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6402 00:40:32.978262
6403 00:40:32.981166 CA PerBit enable=1, Macro0, CA PI delay=36
6404 00:40:32.981683
6405 00:40:32.984207 [CBTSetCACLKResult] CA Dly = 36
6406 00:40:32.988192 CS Dly: 1 (0~32)
6407 00:40:32.988711 ==
6408 00:40:32.991392 Dram Type= 6, Freq= 0, CH_1, rank 1
6409 00:40:32.994554 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6410 00:40:32.995074 ==
6411 00:40:33.000899 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6412 00:40:33.004397 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6413 00:40:33.007998 [CA 0] Center 36 (8~64) winsize 57
6414 00:40:33.015880 [CA 1] Center 36 (8~64) winsize 57
6415 00:40:33.016721 [CA 2] Center 36 (8~64) winsize 57
6416 00:40:33.017631 [CA 3] Center 36 (8~64) winsize 57
6417 00:40:33.020863 [CA 4] Center 36 (8~64) winsize 57
6418 00:40:33.024399 [CA 5] Center 36 (8~64) winsize 57
6419 00:40:33.024915
6420 00:40:33.027460 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6421 00:40:33.027978
6422 00:40:33.030984 [CATrainingPosCal] consider 2 rank data
6423 00:40:33.034269 u2DelayCellTimex100 = 270/100 ps
6424 00:40:33.037479 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6425 00:40:33.043900 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6426 00:40:33.047631 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6427 00:40:33.050418 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6428 00:40:33.054414 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6429 00:40:33.057504 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6430 00:40:33.058022
6431 00:40:33.060561 CA PerBit enable=1, Macro0, CA PI delay=36
6432 00:40:33.060992
6433 00:40:33.064021 [CBTSetCACLKResult] CA Dly = 36
6434 00:40:33.064545 CS Dly: 1 (0~32)
6435 00:40:33.067019
6436 00:40:33.070672 ----->DramcWriteLeveling(PI) begin...
6437 00:40:33.071208 ==
6438 00:40:33.074075 Dram Type= 6, Freq= 0, CH_1, rank 0
6439 00:40:33.077341 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6440 00:40:33.077872 ==
6441 00:40:33.080294 Write leveling (Byte 0): 32 => 0
6442 00:40:33.084437 Write leveling (Byte 1): 32 => 0
6443 00:40:33.087152 DramcWriteLeveling(PI) end<-----
6444 00:40:33.087676
6445 00:40:33.088021 ==
6446 00:40:33.090597 Dram Type= 6, Freq= 0, CH_1, rank 0
6447 00:40:33.093882 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6448 00:40:33.094444 ==
6449 00:40:33.097224 [Gating] SW mode calibration
6450 00:40:33.103426 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6451 00:40:33.110044 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6452 00:40:33.113381 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6453 00:40:33.116695 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6454 00:40:33.123490 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6455 00:40:33.126873 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6456 00:40:33.129896 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6457 00:40:33.136475 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6458 00:40:33.139836 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6459 00:40:33.143129 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6460 00:40:33.146680 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6461 00:40:33.150124 Total UI for P1: 0, mck2ui 16
6462 00:40:33.153304 best dqsien dly found for B0: ( 0, 10, 16)
6463 00:40:33.156512 Total UI for P1: 0, mck2ui 16
6464 00:40:33.160220 best dqsien dly found for B1: ( 0, 10, 16)
6465 00:40:33.163611 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6466 00:40:33.169893 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6467 00:40:33.170455
6468 00:40:33.173477 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6469 00:40:33.176082 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6470 00:40:33.179873 [Gating] SW calibration Done
6471 00:40:33.180307 ==
6472 00:40:33.182924 Dram Type= 6, Freq= 0, CH_1, rank 0
6473 00:40:33.187157 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6474 00:40:33.187674 ==
6475 00:40:33.189616 RX Vref Scan: 0
6476 00:40:33.190126
6477 00:40:33.190507 RX Vref 0 -> 0, step: 1
6478 00:40:33.190828
6479 00:40:33.193043 RX Delay -410 -> 252, step: 16
6480 00:40:33.199330 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6481 00:40:33.202778 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6482 00:40:33.206132 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6483 00:40:33.209671 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6484 00:40:33.215972 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6485 00:40:33.219793 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6486 00:40:33.222632 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6487 00:40:33.226575 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6488 00:40:33.232476 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6489 00:40:33.235915 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6490 00:40:33.239045 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6491 00:40:33.242516 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6492 00:40:33.249435 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6493 00:40:33.252547 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6494 00:40:33.255886 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6495 00:40:33.259491 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6496 00:40:33.262476 ==
6497 00:40:33.262913 Dram Type= 6, Freq= 0, CH_1, rank 0
6498 00:40:33.268971 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6499 00:40:33.269407 ==
6500 00:40:33.269780 DQS Delay:
6501 00:40:33.272425 DQS0 = 43, DQS1 = 59
6502 00:40:33.272948 DQM Delay:
6503 00:40:33.275514 DQM0 = 6, DQM1 = 15
6504 00:40:33.275949 DQ Delay:
6505 00:40:33.279176 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0
6506 00:40:33.282539 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6507 00:40:33.286015 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6508 00:40:33.289326 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6509 00:40:33.289935
6510 00:40:33.290340
6511 00:40:33.290671 ==
6512 00:40:33.292468 Dram Type= 6, Freq= 0, CH_1, rank 0
6513 00:40:33.295670 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6514 00:40:33.296196 ==
6515 00:40:33.296538
6516 00:40:33.296847
6517 00:40:33.299202 TX Vref Scan disable
6518 00:40:33.299634 == TX Byte 0 ==
6519 00:40:33.305631 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6520 00:40:33.309276 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6521 00:40:33.309841 == TX Byte 1 ==
6522 00:40:33.315588 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6523 00:40:33.318640 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6524 00:40:33.319076 ==
6525 00:40:33.321992 Dram Type= 6, Freq= 0, CH_1, rank 0
6526 00:40:33.325785 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6527 00:40:33.326354 ==
6528 00:40:33.326711
6529 00:40:33.327022
6530 00:40:33.328808 TX Vref Scan disable
6531 00:40:33.329240 == TX Byte 0 ==
6532 00:40:33.335474 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6533 00:40:33.339163 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6534 00:40:33.341766 == TX Byte 1 ==
6535 00:40:33.345024 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6536 00:40:33.348642 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6537 00:40:33.349162
6538 00:40:33.349509 [DATLAT]
6539 00:40:33.352217 Freq=400, CH1 RK0
6540 00:40:33.352736
6541 00:40:33.353079 DATLAT Default: 0xf
6542 00:40:33.355023 0, 0xFFFF, sum = 0
6543 00:40:33.355461 1, 0xFFFF, sum = 0
6544 00:40:33.358331 2, 0xFFFF, sum = 0
6545 00:40:33.361887 3, 0xFFFF, sum = 0
6546 00:40:33.362507 4, 0xFFFF, sum = 0
6547 00:40:33.365070 5, 0xFFFF, sum = 0
6548 00:40:33.365515 6, 0xFFFF, sum = 0
6549 00:40:33.368526 7, 0xFFFF, sum = 0
6550 00:40:33.369054 8, 0xFFFF, sum = 0
6551 00:40:33.372015 9, 0xFFFF, sum = 0
6552 00:40:33.372546 10, 0xFFFF, sum = 0
6553 00:40:33.374950 11, 0xFFFF, sum = 0
6554 00:40:33.375395 12, 0x0, sum = 1
6555 00:40:33.378201 13, 0x0, sum = 2
6556 00:40:33.378691 14, 0x0, sum = 3
6557 00:40:33.381603 15, 0x0, sum = 4
6558 00:40:33.382044 best_step = 13
6559 00:40:33.382453
6560 00:40:33.382780 ==
6561 00:40:33.385102 Dram Type= 6, Freq= 0, CH_1, rank 0
6562 00:40:33.388855 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6563 00:40:33.391391 ==
6564 00:40:33.391910 RX Vref Scan: 1
6565 00:40:33.392256
6566 00:40:33.395464 RX Vref 0 -> 0, step: 1
6567 00:40:33.395983
6568 00:40:33.398084 RX Delay -359 -> 252, step: 8
6569 00:40:33.398542
6570 00:40:33.401248 Set Vref, RX VrefLevel [Byte0]: 57
6571 00:40:33.404954 [Byte1]: 50
6572 00:40:33.405392
6573 00:40:33.408054 Final RX Vref Byte 0 = 57 to rank0
6574 00:40:33.411000 Final RX Vref Byte 1 = 50 to rank0
6575 00:40:33.414632 Final RX Vref Byte 0 = 57 to rank1
6576 00:40:33.418160 Final RX Vref Byte 1 = 50 to rank1==
6577 00:40:33.422326 Dram Type= 6, Freq= 0, CH_1, rank 0
6578 00:40:33.424813 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6579 00:40:33.425337 ==
6580 00:40:33.427793 DQS Delay:
6581 00:40:33.428233 DQS0 = 48, DQS1 = 64
6582 00:40:33.431613 DQM Delay:
6583 00:40:33.432134 DQM0 = 7, DQM1 = 16
6584 00:40:33.432479 DQ Delay:
6585 00:40:33.434337 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =4
6586 00:40:33.437974 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =4
6587 00:40:33.441641 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6588 00:40:33.444549 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6589 00:40:33.444987
6590 00:40:33.445330
6591 00:40:33.454444 [DQSOSCAuto] RK0, (LSB)MR18= 0xecec, (MSB)MR19= 0xc0c, tDQSOscB0 = 380 ps tDQSOscB1 = 380 ps
6592 00:40:33.454968 CH1 RK0: MR19=C0C, MR18=ECEC
6593 00:40:33.460917 CH1_RK0: MR19=0xC0C, MR18=0xECEC, DQSOSC=380, MR23=63, INC=409, DEC=272
6594 00:40:33.461357 ==
6595 00:40:33.464388 Dram Type= 6, Freq= 0, CH_1, rank 1
6596 00:40:33.471057 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6597 00:40:33.471577 ==
6598 00:40:33.475007 [Gating] SW mode calibration
6599 00:40:33.481227 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6600 00:40:33.484688 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6601 00:40:33.487745 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6602 00:40:33.494447 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6603 00:40:33.497935 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6604 00:40:33.501272 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6605 00:40:33.507832 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6606 00:40:33.511099 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6607 00:40:33.514894 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6608 00:40:33.521384 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6609 00:40:33.524848 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6610 00:40:33.528217 Total UI for P1: 0, mck2ui 16
6611 00:40:33.531414 best dqsien dly found for B0: ( 0, 10, 16)
6612 00:40:33.534305 Total UI for P1: 0, mck2ui 16
6613 00:40:33.537664 best dqsien dly found for B1: ( 0, 10, 16)
6614 00:40:33.541048 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6615 00:40:33.545073 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6616 00:40:33.545608
6617 00:40:33.547687 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6618 00:40:33.554435 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6619 00:40:33.554943 [Gating] SW calibration Done
6620 00:40:33.555285 ==
6621 00:40:33.557931 Dram Type= 6, Freq= 0, CH_1, rank 1
6622 00:40:33.564639 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6623 00:40:33.565167 ==
6624 00:40:33.565514 RX Vref Scan: 0
6625 00:40:33.565830
6626 00:40:33.567512 RX Vref 0 -> 0, step: 1
6627 00:40:33.568031
6628 00:40:33.570943 RX Delay -410 -> 252, step: 16
6629 00:40:33.574470 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6630 00:40:33.577817 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6631 00:40:33.584577 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6632 00:40:33.587912 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6633 00:40:33.590578 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6634 00:40:33.593883 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6635 00:40:33.600429 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6636 00:40:33.604146 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6637 00:40:33.607214 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6638 00:40:33.610578 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6639 00:40:33.616965 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6640 00:40:33.620581 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6641 00:40:33.623909 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6642 00:40:33.627178 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6643 00:40:33.633923 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6644 00:40:33.637125 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6645 00:40:33.637664 ==
6646 00:40:33.640185 Dram Type= 6, Freq= 0, CH_1, rank 1
6647 00:40:33.643317 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6648 00:40:33.643755 ==
6649 00:40:33.646723 DQS Delay:
6650 00:40:33.647159 DQS0 = 43, DQS1 = 59
6651 00:40:33.649878 DQM Delay:
6652 00:40:33.650353 DQM0 = 10, DQM1 = 17
6653 00:40:33.653432 DQ Delay:
6654 00:40:33.653948 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6655 00:40:33.656920 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6656 00:40:33.660009 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6657 00:40:33.663847 DQ12 =32, DQ13 =24, DQ14 =32, DQ15 =24
6658 00:40:33.664365
6659 00:40:33.664707
6660 00:40:33.665018 ==
6661 00:40:33.666902 Dram Type= 6, Freq= 0, CH_1, rank 1
6662 00:40:33.673586 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6663 00:40:33.674108 ==
6664 00:40:33.674510
6665 00:40:33.674828
6666 00:40:33.675132 TX Vref Scan disable
6667 00:40:33.676405 == TX Byte 0 ==
6668 00:40:33.679974 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6669 00:40:33.683578 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6670 00:40:33.687012 == TX Byte 1 ==
6671 00:40:33.689647 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6672 00:40:33.693275 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6673 00:40:33.693795 ==
6674 00:40:33.696616 Dram Type= 6, Freq= 0, CH_1, rank 1
6675 00:40:33.702904 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6676 00:40:33.703410 ==
6677 00:40:33.703749
6678 00:40:33.704060
6679 00:40:33.706247 TX Vref Scan disable
6680 00:40:33.706770 == TX Byte 0 ==
6681 00:40:33.709766 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6682 00:40:33.713603 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6683 00:40:33.716422 == TX Byte 1 ==
6684 00:40:33.719780 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6685 00:40:33.722858 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6686 00:40:33.723292
6687 00:40:33.726444 [DATLAT]
6688 00:40:33.727226 Freq=400, CH1 RK1
6689 00:40:33.727814
6690 00:40:33.729868 DATLAT Default: 0xd
6691 00:40:33.730331 0, 0xFFFF, sum = 0
6692 00:40:33.733013 1, 0xFFFF, sum = 0
6693 00:40:33.733613 2, 0xFFFF, sum = 0
6694 00:40:33.736034 3, 0xFFFF, sum = 0
6695 00:40:33.736544 4, 0xFFFF, sum = 0
6696 00:40:33.739485 5, 0xFFFF, sum = 0
6697 00:40:33.739922 6, 0xFFFF, sum = 0
6698 00:40:33.742632 7, 0xFFFF, sum = 0
6699 00:40:33.745865 8, 0xFFFF, sum = 0
6700 00:40:33.746389 9, 0xFFFF, sum = 0
6701 00:40:33.749257 10, 0xFFFF, sum = 0
6702 00:40:33.749694 11, 0xFFFF, sum = 0
6703 00:40:33.752712 12, 0x0, sum = 1
6704 00:40:33.753148 13, 0x0, sum = 2
6705 00:40:33.756048 14, 0x0, sum = 3
6706 00:40:33.756505 15, 0x0, sum = 4
6707 00:40:33.756852 best_step = 13
6708 00:40:33.757164
6709 00:40:33.759158 ==
6710 00:40:33.762787 Dram Type= 6, Freq= 0, CH_1, rank 1
6711 00:40:33.766195 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6712 00:40:33.766997 ==
6713 00:40:33.767571 RX Vref Scan: 0
6714 00:40:33.767914
6715 00:40:33.769094 RX Vref 0 -> 0, step: 1
6716 00:40:33.769551
6717 00:40:33.772554 RX Delay -359 -> 252, step: 8
6718 00:40:33.779614 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6719 00:40:33.783003 iDelay=217, Bit 1, Center -44 (-287 ~ 200) 488
6720 00:40:33.786117 iDelay=217, Bit 2, Center -48 (-295 ~ 200) 496
6721 00:40:33.793011 iDelay=217, Bit 3, Center -44 (-287 ~ 200) 488
6722 00:40:33.796707 iDelay=217, Bit 4, Center -40 (-287 ~ 208) 496
6723 00:40:33.799844 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6724 00:40:33.802754 iDelay=217, Bit 6, Center -32 (-279 ~ 216) 496
6725 00:40:33.805898 iDelay=217, Bit 7, Center -40 (-287 ~ 208) 496
6726 00:40:33.812868 iDelay=217, Bit 8, Center -64 (-311 ~ 184) 496
6727 00:40:33.816214 iDelay=217, Bit 9, Center -60 (-311 ~ 192) 504
6728 00:40:33.819458 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6729 00:40:33.826405 iDelay=217, Bit 11, Center -56 (-303 ~ 192) 496
6730 00:40:33.829177 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6731 00:40:33.832973 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6732 00:40:33.835895 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6733 00:40:33.842526 iDelay=217, Bit 15, Center -40 (-279 ~ 200) 480
6734 00:40:33.842994 ==
6735 00:40:33.845917 Dram Type= 6, Freq= 0, CH_1, rank 1
6736 00:40:33.848991 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6737 00:40:33.849527 ==
6738 00:40:33.849972 DQS Delay:
6739 00:40:33.852505 DQS0 = 48, DQS1 = 64
6740 00:40:33.852936 DQM Delay:
6741 00:40:33.855719 DQM0 = 9, DQM1 = 15
6742 00:40:33.856152 DQ Delay:
6743 00:40:33.858944 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
6744 00:40:33.863008 DQ4 =8, DQ5 =20, DQ6 =16, DQ7 =8
6745 00:40:33.865907 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6746 00:40:33.869595 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6747 00:40:33.870106
6748 00:40:33.870504
6749 00:40:33.876030 [DQSOSCAuto] RK1, (LSB)MR18= 0xafaf, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 388 ps
6750 00:40:33.879236 CH1 RK1: MR19=C0C, MR18=AFAF
6751 00:40:33.885904 CH1_RK1: MR19=0xC0C, MR18=0xAFAF, DQSOSC=388, MR23=63, INC=392, DEC=261
6752 00:40:33.889126 [RxdqsGatingPostProcess] freq 400
6753 00:40:33.895855 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6754 00:40:33.896367 Pre-setting of DQS Precalculation
6755 00:40:33.902674 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6756 00:40:33.909263 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6757 00:40:33.915566 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6758 00:40:33.916069
6759 00:40:33.916406
6760 00:40:33.919126 [Calibration Summary] 800 Mbps
6761 00:40:33.922314 CH 0, Rank 0
6762 00:40:33.922745 SW Impedance : PASS
6763 00:40:33.925512 DUTY Scan : NO K
6764 00:40:33.925950 ZQ Calibration : PASS
6765 00:40:33.928731 Jitter Meter : NO K
6766 00:40:33.932109 CBT Training : PASS
6767 00:40:33.932624 Write leveling : PASS
6768 00:40:33.935525 RX DQS gating : PASS
6769 00:40:33.938774 RX DQ/DQS(RDDQC) : PASS
6770 00:40:33.939214 TX DQ/DQS : PASS
6771 00:40:33.942163 RX DATLAT : PASS
6772 00:40:33.945633 RX DQ/DQS(Engine): PASS
6773 00:40:33.946088 TX OE : NO K
6774 00:40:33.949129 All Pass.
6775 00:40:33.949753
6776 00:40:33.950342 CH 0, Rank 1
6777 00:40:33.952129 SW Impedance : PASS
6778 00:40:33.952559 DUTY Scan : NO K
6779 00:40:33.955551 ZQ Calibration : PASS
6780 00:40:33.959043 Jitter Meter : NO K
6781 00:40:33.959471 CBT Training : PASS
6782 00:40:33.961887 Write leveling : NO K
6783 00:40:33.965607 RX DQS gating : PASS
6784 00:40:33.966042 RX DQ/DQS(RDDQC) : PASS
6785 00:40:33.968631 TX DQ/DQS : PASS
6786 00:40:33.971945 RX DATLAT : PASS
6787 00:40:33.972379 RX DQ/DQS(Engine): PASS
6788 00:40:33.975838 TX OE : NO K
6789 00:40:33.976271 All Pass.
6790 00:40:33.976766
6791 00:40:33.977182 CH 1, Rank 0
6792 00:40:33.978577 SW Impedance : PASS
6793 00:40:33.982163 DUTY Scan : NO K
6794 00:40:33.982757 ZQ Calibration : PASS
6795 00:40:33.985178 Jitter Meter : NO K
6796 00:40:33.988830 CBT Training : PASS
6797 00:40:33.989339 Write leveling : PASS
6798 00:40:33.992585 RX DQS gating : PASS
6799 00:40:33.995886 RX DQ/DQS(RDDQC) : PASS
6800 00:40:33.996398 TX DQ/DQS : PASS
6801 00:40:33.999167 RX DATLAT : PASS
6802 00:40:34.002354 RX DQ/DQS(Engine): PASS
6803 00:40:34.002864 TX OE : NO K
6804 00:40:34.005226 All Pass.
6805 00:40:34.005654
6806 00:40:34.005991 CH 1, Rank 1
6807 00:40:34.008731 SW Impedance : PASS
6808 00:40:34.009248 DUTY Scan : NO K
6809 00:40:34.012352 ZQ Calibration : PASS
6810 00:40:34.015248 Jitter Meter : NO K
6811 00:40:34.015762 CBT Training : PASS
6812 00:40:34.018395 Write leveling : NO K
6813 00:40:34.021690 RX DQS gating : PASS
6814 00:40:34.022259 RX DQ/DQS(RDDQC) : PASS
6815 00:40:34.025188 TX DQ/DQS : PASS
6816 00:40:34.025619 RX DATLAT : PASS
6817 00:40:34.028770 RX DQ/DQS(Engine): PASS
6818 00:40:34.032080 TX OE : NO K
6819 00:40:34.032512 All Pass.
6820 00:40:34.032846
6821 00:40:34.035253 DramC Write-DBI off
6822 00:40:34.038763 PER_BANK_REFRESH: Hybrid Mode
6823 00:40:34.039189 TX_TRACKING: ON
6824 00:40:34.048483 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
6825 00:40:34.051954 [FAST_K] Save calibration result to emmc
6826 00:40:34.055120 dramc_set_vcore_voltage set vcore to 725000
6827 00:40:34.058534 Read voltage for 1600, 0
6828 00:40:34.059126 Vio18 = 0
6829 00:40:34.059479 Vcore = 725000
6830 00:40:34.059796 Vdram = 0
6831 00:40:34.061621 Vddq = 0
6832 00:40:34.062050 Vmddr = 0
6833 00:40:34.068407 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
6834 00:40:34.071919 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6835 00:40:34.074941 MEM_TYPE=3, freq_sel=13
6836 00:40:34.078324 sv_algorithm_assistance_LP4_3733
6837 00:40:34.082389 ============ PULL DRAM RESETB DOWN ============
6838 00:40:34.084957 ========== PULL DRAM RESETB DOWN end =========
6839 00:40:34.091585 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6840 00:40:34.094862 ===================================
6841 00:40:34.095376 LPDDR4 DRAM CONFIGURATION
6842 00:40:34.098404 ===================================
6843 00:40:34.101789 EX_ROW_EN[0] = 0x0
6844 00:40:34.105084 EX_ROW_EN[1] = 0x0
6845 00:40:34.105513 LP4Y_EN = 0x0
6846 00:40:34.107947 WORK_FSP = 0x1
6847 00:40:34.108375 WL = 0x5
6848 00:40:34.111725 RL = 0x5
6849 00:40:34.112152 BL = 0x2
6850 00:40:34.114869 RPST = 0x0
6851 00:40:34.115298 RD_PRE = 0x0
6852 00:40:34.118280 WR_PRE = 0x1
6853 00:40:34.118709 WR_PST = 0x1
6854 00:40:34.121284 DBI_WR = 0x0
6855 00:40:34.121798 DBI_RD = 0x0
6856 00:40:34.124878 OTF = 0x1
6857 00:40:34.127998 ===================================
6858 00:40:34.131364 ===================================
6859 00:40:34.131798 ANA top config
6860 00:40:34.135319 ===================================
6861 00:40:34.138094 DLL_ASYNC_EN = 0
6862 00:40:34.141174 ALL_SLAVE_EN = 0
6863 00:40:34.144595 NEW_RANK_MODE = 1
6864 00:40:34.145031 DLL_IDLE_MODE = 1
6865 00:40:34.147985 LP45_APHY_COMB_EN = 1
6866 00:40:34.150936 TX_ODT_DIS = 0
6867 00:40:34.154665 NEW_8X_MODE = 1
6868 00:40:34.157591 ===================================
6869 00:40:34.160804 ===================================
6870 00:40:34.164278 data_rate = 3200
6871 00:40:34.164843 CKR = 1
6872 00:40:34.167602 DQ_P2S_RATIO = 8
6873 00:40:34.171002 ===================================
6874 00:40:34.174467 CA_P2S_RATIO = 8
6875 00:40:34.177896 DQ_CA_OPEN = 0
6876 00:40:34.181236 DQ_SEMI_OPEN = 0
6877 00:40:34.184480 CA_SEMI_OPEN = 0
6878 00:40:34.184989 CA_FULL_RATE = 0
6879 00:40:34.187892 DQ_CKDIV4_EN = 0
6880 00:40:34.191039 CA_CKDIV4_EN = 0
6881 00:40:34.194620 CA_PREDIV_EN = 0
6882 00:40:34.197722 PH8_DLY = 12
6883 00:40:34.200665 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
6884 00:40:34.201063 DQ_AAMCK_DIV = 4
6885 00:40:34.204406 CA_AAMCK_DIV = 4
6886 00:40:34.207990 CA_ADMCK_DIV = 4
6887 00:40:34.210893 DQ_TRACK_CA_EN = 0
6888 00:40:34.214338 CA_PICK = 1600
6889 00:40:34.217379 CA_MCKIO = 1600
6890 00:40:34.217815 MCKIO_SEMI = 0
6891 00:40:34.220628 PLL_FREQ = 3068
6892 00:40:34.224745 DQ_UI_PI_RATIO = 32
6893 00:40:34.227209 CA_UI_PI_RATIO = 0
6894 00:40:34.230853 ===================================
6895 00:40:34.233995 ===================================
6896 00:40:34.237203 memory_type:LPDDR4
6897 00:40:34.237689 GP_NUM : 10
6898 00:40:34.241053 SRAM_EN : 1
6899 00:40:34.243925 MD32_EN : 0
6900 00:40:34.247367 ===================================
6901 00:40:34.247798 [ANA_INIT] >>>>>>>>>>>>>>
6902 00:40:34.250657 <<<<<< [CONFIGURE PHASE]: ANA_TX
6903 00:40:34.254070 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6904 00:40:34.257329 ===================================
6905 00:40:34.260768 data_rate = 3200,PCW = 0X7600
6906 00:40:34.264381 ===================================
6907 00:40:34.267120 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6908 00:40:34.273744 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6909 00:40:34.277157 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6910 00:40:34.283667 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6911 00:40:34.286978 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6912 00:40:34.290285 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6913 00:40:34.293632 [ANA_INIT] flow start
6914 00:40:34.294192 [ANA_INIT] PLL >>>>>>>>
6915 00:40:34.296830 [ANA_INIT] PLL <<<<<<<<
6916 00:40:34.300213 [ANA_INIT] MIDPI >>>>>>>>
6917 00:40:34.300732 [ANA_INIT] MIDPI <<<<<<<<
6918 00:40:34.303607 [ANA_INIT] DLL >>>>>>>>
6919 00:40:34.306853 [ANA_INIT] DLL <<<<<<<<
6920 00:40:34.307324 [ANA_INIT] flow end
6921 00:40:34.313674 ============ LP4 DIFF to SE enter ============
6922 00:40:34.316779 ============ LP4 DIFF to SE exit ============
6923 00:40:34.317314 [ANA_INIT] <<<<<<<<<<<<<
6924 00:40:34.320703 [Flow] Enable top DCM control >>>>>
6925 00:40:34.323301 [Flow] Enable top DCM control <<<<<
6926 00:40:34.326925 Enable DLL master slave shuffle
6927 00:40:34.333898 ==============================================================
6928 00:40:34.336858 Gating Mode config
6929 00:40:34.339923 ==============================================================
6930 00:40:34.343317 Config description:
6931 00:40:34.353438 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6932 00:40:34.359720 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6933 00:40:34.362984 SELPH_MODE 0: By rank 1: By Phase
6934 00:40:34.370153 ==============================================================
6935 00:40:34.373107 GAT_TRACK_EN = 1
6936 00:40:34.376888 RX_GATING_MODE = 2
6937 00:40:34.379985 RX_GATING_TRACK_MODE = 2
6938 00:40:34.380497 SELPH_MODE = 1
6939 00:40:34.382863 PICG_EARLY_EN = 1
6940 00:40:34.386671 VALID_LAT_VALUE = 1
6941 00:40:34.393091 ==============================================================
6942 00:40:34.396440 Enter into Gating configuration >>>>
6943 00:40:34.399919 Exit from Gating configuration <<<<
6944 00:40:34.403325 Enter into DVFS_PRE_config >>>>>
6945 00:40:34.413302 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6946 00:40:34.416650 Exit from DVFS_PRE_config <<<<<
6947 00:40:34.420497 Enter into PICG configuration >>>>
6948 00:40:34.422933 Exit from PICG configuration <<<<
6949 00:40:34.426372 [RX_INPUT] configuration >>>>>
6950 00:40:34.430000 [RX_INPUT] configuration <<<<<
6951 00:40:34.433347 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6952 00:40:34.439811 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6953 00:40:34.446321 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6954 00:40:34.452747 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6955 00:40:34.456456 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6956 00:40:34.462788 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6957 00:40:34.466117 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6958 00:40:34.472797 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6959 00:40:34.476351 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6960 00:40:34.479917 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6961 00:40:34.482706 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6962 00:40:34.489507 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6963 00:40:34.492541 ===================================
6964 00:40:34.496148 LPDDR4 DRAM CONFIGURATION
6965 00:40:34.499405 ===================================
6966 00:40:34.499917 EX_ROW_EN[0] = 0x0
6967 00:40:34.502645 EX_ROW_EN[1] = 0x0
6968 00:40:34.503157 LP4Y_EN = 0x0
6969 00:40:34.505607 WORK_FSP = 0x1
6970 00:40:34.506102 WL = 0x5
6971 00:40:34.509207 RL = 0x5
6972 00:40:34.509639 BL = 0x2
6973 00:40:34.512687 RPST = 0x0
6974 00:40:34.513204 RD_PRE = 0x0
6975 00:40:34.516335 WR_PRE = 0x1
6976 00:40:34.516857 WR_PST = 0x1
6977 00:40:34.519711 DBI_WR = 0x0
6978 00:40:34.520237 DBI_RD = 0x0
6979 00:40:34.522401 OTF = 0x1
6980 00:40:34.525981 ===================================
6981 00:40:34.529340 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6982 00:40:34.532513 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6983 00:40:34.538761 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6984 00:40:34.542305 ===================================
6985 00:40:34.545522 LPDDR4 DRAM CONFIGURATION
6986 00:40:34.548748 ===================================
6987 00:40:34.549183 EX_ROW_EN[0] = 0x10
6988 00:40:34.552064 EX_ROW_EN[1] = 0x0
6989 00:40:34.552511 LP4Y_EN = 0x0
6990 00:40:34.555665 WORK_FSP = 0x1
6991 00:40:34.556101 WL = 0x5
6992 00:40:34.558681 RL = 0x5
6993 00:40:34.559113 BL = 0x2
6994 00:40:34.562292 RPST = 0x0
6995 00:40:34.562728 RD_PRE = 0x0
6996 00:40:34.565645 WR_PRE = 0x1
6997 00:40:34.566079 WR_PST = 0x1
6998 00:40:34.569300 DBI_WR = 0x0
6999 00:40:34.569735 DBI_RD = 0x0
7000 00:40:34.572025 OTF = 0x1
7001 00:40:34.575490 ===================================
7002 00:40:34.581809 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7003 00:40:34.582265 ==
7004 00:40:34.585170 Dram Type= 6, Freq= 0, CH_0, rank 0
7005 00:40:34.588719 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7006 00:40:34.589221 ==
7007 00:40:34.591964 [Duty_Offset_Calibration]
7008 00:40:34.592398 B0:0 B1:2 CA:1
7009 00:40:34.592735
7010 00:40:34.595090 [DutyScan_Calibration_Flow] k_type=0
7011 00:40:34.606013
7012 00:40:34.606550 ==CLK 0==
7013 00:40:34.609493 Final CLK duty delay cell = 0
7014 00:40:34.612774 [0] MAX Duty = 5156%(X100), DQS PI = 22
7015 00:40:34.616250 [0] MIN Duty = 4938%(X100), DQS PI = 50
7016 00:40:34.619494 [0] AVG Duty = 5047%(X100)
7017 00:40:34.619948
7018 00:40:34.623015 CH0 CLK Duty spec in!! Max-Min= 218%
7019 00:40:34.626053 [DutyScan_Calibration_Flow] ====Done====
7020 00:40:34.626521
7021 00:40:34.629701 [DutyScan_Calibration_Flow] k_type=1
7022 00:40:34.646169
7023 00:40:34.646785 ==DQS 0 ==
7024 00:40:34.649536 Final DQS duty delay cell = 0
7025 00:40:34.653056 [0] MAX Duty = 5125%(X100), DQS PI = 32
7026 00:40:34.656256 [0] MIN Duty = 5000%(X100), DQS PI = 8
7027 00:40:34.656684 [0] AVG Duty = 5062%(X100)
7028 00:40:34.659628
7029 00:40:34.660051 ==DQS 1 ==
7030 00:40:34.662664 Final DQS duty delay cell = 0
7031 00:40:34.666179 [0] MAX Duty = 5031%(X100), DQS PI = 46
7032 00:40:34.669420 [0] MIN Duty = 4844%(X100), DQS PI = 18
7033 00:40:34.673082 [0] AVG Duty = 4937%(X100)
7034 00:40:34.673522
7035 00:40:34.676058 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7036 00:40:34.676487
7037 00:40:34.679367 CH0 DQS 1 Duty spec in!! Max-Min= 187%
7038 00:40:34.682557 [DutyScan_Calibration_Flow] ====Done====
7039 00:40:34.683012
7040 00:40:34.686208 [DutyScan_Calibration_Flow] k_type=3
7041 00:40:34.703378
7042 00:40:34.703884 ==DQM 0 ==
7043 00:40:34.706799 Final DQM duty delay cell = 0
7044 00:40:34.709876 [0] MAX Duty = 5187%(X100), DQS PI = 22
7045 00:40:34.713451 [0] MIN Duty = 4907%(X100), DQS PI = 42
7046 00:40:34.716686 [0] AVG Duty = 5047%(X100)
7047 00:40:34.717190
7048 00:40:34.717525 ==DQM 1 ==
7049 00:40:34.720521 Final DQM duty delay cell = 0
7050 00:40:34.723312 [0] MAX Duty = 5031%(X100), DQS PI = 50
7051 00:40:34.727114 [0] MIN Duty = 4782%(X100), DQS PI = 14
7052 00:40:34.730018 [0] AVG Duty = 4906%(X100)
7053 00:40:34.730501
7054 00:40:34.733467 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7055 00:40:34.733898
7056 00:40:34.736795 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7057 00:40:34.740402 [DutyScan_Calibration_Flow] ====Done====
7058 00:40:34.740838
7059 00:40:34.743580 [DutyScan_Calibration_Flow] k_type=2
7060 00:40:34.760115
7061 00:40:34.760629 ==DQ 0 ==
7062 00:40:34.763308 Final DQ duty delay cell = 0
7063 00:40:34.766767 [0] MAX Duty = 5218%(X100), DQS PI = 18
7064 00:40:34.770039 [0] MIN Duty = 4938%(X100), DQS PI = 56
7065 00:40:34.770520 [0] AVG Duty = 5078%(X100)
7066 00:40:34.770866
7067 00:40:34.773598 ==DQ 1 ==
7068 00:40:34.777034 Final DQ duty delay cell = -4
7069 00:40:34.779898 [-4] MAX Duty = 5062%(X100), DQS PI = 4
7070 00:40:34.783131 [-4] MIN Duty = 4844%(X100), DQS PI = 34
7071 00:40:34.783703 [-4] AVG Duty = 4953%(X100)
7072 00:40:34.787072
7073 00:40:34.789973 CH0 DQ 0 Duty spec in!! Max-Min= 280%
7074 00:40:34.790537
7075 00:40:34.793023 CH0 DQ 1 Duty spec in!! Max-Min= 218%
7076 00:40:34.796971 [DutyScan_Calibration_Flow] ====Done====
7077 00:40:34.797478 ==
7078 00:40:34.799814 Dram Type= 6, Freq= 0, CH_1, rank 0
7079 00:40:34.803183 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7080 00:40:34.803741 ==
7081 00:40:34.806398 [Duty_Offset_Calibration]
7082 00:40:34.806919 B0:0 B1:5 CA:-5
7083 00:40:34.807260
7084 00:40:34.809550 [DutyScan_Calibration_Flow] k_type=0
7085 00:40:34.820380
7086 00:40:34.820888 ==CLK 0==
7087 00:40:34.824076 Final CLK duty delay cell = 0
7088 00:40:34.826917 [0] MAX Duty = 5156%(X100), DQS PI = 22
7089 00:40:34.830533 [0] MIN Duty = 4906%(X100), DQS PI = 52
7090 00:40:34.830967 [0] AVG Duty = 5031%(X100)
7091 00:40:34.833787
7092 00:40:34.836985 CH1 CLK Duty spec in!! Max-Min= 250%
7093 00:40:34.840532 [DutyScan_Calibration_Flow] ====Done====
7094 00:40:34.840967
7095 00:40:34.843297 [DutyScan_Calibration_Flow] k_type=1
7096 00:40:34.859330
7097 00:40:34.859766 ==DQS 0 ==
7098 00:40:34.862816 Final DQS duty delay cell = 0
7099 00:40:34.865803 [0] MAX Duty = 5124%(X100), DQS PI = 18
7100 00:40:34.869052 [0] MIN Duty = 4876%(X100), DQS PI = 42
7101 00:40:34.872656 [0] AVG Duty = 5000%(X100)
7102 00:40:34.873231
7103 00:40:34.873575 ==DQS 1 ==
7104 00:40:34.875770 Final DQS duty delay cell = -4
7105 00:40:34.878968 [-4] MAX Duty = 5000%(X100), DQS PI = 18
7106 00:40:34.882196 [-4] MIN Duty = 4844%(X100), DQS PI = 40
7107 00:40:34.885634 [-4] AVG Duty = 4922%(X100)
7108 00:40:34.886067
7109 00:40:34.889067 CH1 DQS 0 Duty spec in!! Max-Min= 248%
7110 00:40:34.889455
7111 00:40:34.892263 CH1 DQS 1 Duty spec in!! Max-Min= 156%
7112 00:40:34.896092 [DutyScan_Calibration_Flow] ====Done====
7113 00:40:34.896606
7114 00:40:34.898982 [DutyScan_Calibration_Flow] k_type=3
7115 00:40:34.915017
7116 00:40:34.915575 ==DQM 0 ==
7117 00:40:34.918664 Final DQM duty delay cell = -4
7118 00:40:34.921464 [-4] MAX Duty = 5062%(X100), DQS PI = 34
7119 00:40:34.925238 [-4] MIN Duty = 4782%(X100), DQS PI = 44
7120 00:40:34.928049 [-4] AVG Duty = 4922%(X100)
7121 00:40:34.928547
7122 00:40:34.928935 ==DQM 1 ==
7123 00:40:34.931456 Final DQM duty delay cell = -4
7124 00:40:34.935191 [-4] MAX Duty = 5031%(X100), DQS PI = 0
7125 00:40:34.938290 [-4] MIN Duty = 4875%(X100), DQS PI = 38
7126 00:40:34.941454 [-4] AVG Duty = 4953%(X100)
7127 00:40:34.941953
7128 00:40:34.945185 CH1 DQM 0 Duty spec in!! Max-Min= 280%
7129 00:40:34.945576
7130 00:40:34.948033 CH1 DQM 1 Duty spec in!! Max-Min= 156%
7131 00:40:34.951679 [DutyScan_Calibration_Flow] ====Done====
7132 00:40:34.952066
7133 00:40:34.954728 [DutyScan_Calibration_Flow] k_type=2
7134 00:40:34.972655
7135 00:40:34.973047 ==DQ 0 ==
7136 00:40:34.975829 Final DQ duty delay cell = 0
7137 00:40:34.979300 [0] MAX Duty = 5062%(X100), DQS PI = 2
7138 00:40:34.982286 [0] MIN Duty = 4938%(X100), DQS PI = 46
7139 00:40:34.982737 [0] AVG Duty = 5000%(X100)
7140 00:40:34.983084
7141 00:40:34.985747 ==DQ 1 ==
7142 00:40:34.988967 Final DQ duty delay cell = 0
7143 00:40:34.992246 [0] MAX Duty = 5031%(X100), DQS PI = 4
7144 00:40:34.995634 [0] MIN Duty = 4875%(X100), DQS PI = 28
7145 00:40:34.996212 [0] AVG Duty = 4953%(X100)
7146 00:40:34.996708
7147 00:40:34.999040 CH1 DQ 0 Duty spec in!! Max-Min= 124%
7148 00:40:35.002049
7149 00:40:35.005530 CH1 DQ 1 Duty spec in!! Max-Min= 156%
7150 00:40:35.008779 [DutyScan_Calibration_Flow] ====Done====
7151 00:40:35.011644 nWR fixed to 30
7152 00:40:35.011971 [ModeRegInit_LP4] CH0 RK0
7153 00:40:35.015101 [ModeRegInit_LP4] CH0 RK1
7154 00:40:35.018371 [ModeRegInit_LP4] CH1 RK0
7155 00:40:35.021765 [ModeRegInit_LP4] CH1 RK1
7156 00:40:35.022009 match AC timing 4
7157 00:40:35.025212 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 0
7158 00:40:35.031745 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7159 00:40:35.034905 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7160 00:40:35.041439 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7161 00:40:35.044671 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7162 00:40:35.044794 [MiockJmeterHQA]
7163 00:40:35.044901
7164 00:40:35.048344 [DramcMiockJmeter] u1RxGatingPI = 0
7165 00:40:35.051395 0 : 4257, 4029
7166 00:40:35.051537 4 : 4252, 4027
7167 00:40:35.055010 8 : 4253, 4026
7168 00:40:35.055162 12 : 4253, 4026
7169 00:40:35.055252 16 : 4252, 4027
7170 00:40:35.058043 20 : 4253, 4027
7171 00:40:35.058203 24 : 4253, 4026
7172 00:40:35.062069 28 : 4252, 4027
7173 00:40:35.062269 32 : 4258, 4029
7174 00:40:35.064860 36 : 4257, 4029
7175 00:40:35.065005 40 : 4252, 4027
7176 00:40:35.068308 44 : 4255, 4029
7177 00:40:35.068452 48 : 4253, 4027
7178 00:40:35.068522 52 : 4363, 4137
7179 00:40:35.071553 56 : 4363, 4138
7180 00:40:35.071671 60 : 4255, 4029
7181 00:40:35.074563 64 : 4253, 4026
7182 00:40:35.074665 68 : 4253, 4027
7183 00:40:35.079128 72 : 4252, 4027
7184 00:40:35.079569 76 : 4363, 4138
7185 00:40:35.079916 80 : 4250, 4027
7186 00:40:35.081670 84 : 4252, 4029
7187 00:40:35.082106 88 : 4250, 4026
7188 00:40:35.085374 92 : 4250, 4027
7189 00:40:35.085890 96 : 4363, 4140
7190 00:40:35.088382 100 : 4250, 1748
7191 00:40:35.088893 104 : 4360, 0
7192 00:40:35.089241 108 : 4360, 0
7193 00:40:35.091596 112 : 4365, 0
7194 00:40:35.092033 116 : 4364, 0
7195 00:40:35.095280 120 : 4250, 0
7196 00:40:35.095799 124 : 4361, 0
7197 00:40:35.096142 128 : 4253, 0
7198 00:40:35.098193 132 : 4250, 0
7199 00:40:35.098671 136 : 4250, 0
7200 00:40:35.101450 140 : 4250, 0
7201 00:40:35.102061 144 : 4250, 0
7202 00:40:35.102663 148 : 4250, 0
7203 00:40:35.104694 152 : 4253, 0
7204 00:40:35.105260 156 : 4250, 0
7205 00:40:35.108136 160 : 4360, 0
7206 00:40:35.108555 164 : 4361, 0
7207 00:40:35.108984 168 : 4250, 0
7208 00:40:35.111260 172 : 4250, 0
7209 00:40:35.111616 176 : 4365, 0
7210 00:40:35.114822 180 : 4250, 0
7211 00:40:35.115259 184 : 4250, 0
7212 00:40:35.115601 188 : 4250, 0
7213 00:40:35.118301 192 : 4253, 0
7214 00:40:35.118740 196 : 4360, 0
7215 00:40:35.119084 200 : 4250, 0
7216 00:40:35.121529 204 : 4252, 0
7217 00:40:35.121963 208 : 4361, 0
7218 00:40:35.124730 212 : 4361, 0
7219 00:40:35.125164 216 : 4363, 0
7220 00:40:35.125513 220 : 4249, 546
7221 00:40:35.128242 224 : 4258, 3996
7222 00:40:35.128679 228 : 4253, 4029
7223 00:40:35.131434 232 : 4360, 4137
7224 00:40:35.131868 236 : 4250, 4027
7225 00:40:35.134756 240 : 4360, 4137
7226 00:40:35.135194 244 : 4250, 4027
7227 00:40:35.138386 248 : 4250, 4027
7228 00:40:35.138826 252 : 4250, 4027
7229 00:40:35.141359 256 : 4250, 4026
7230 00:40:35.141797 260 : 4250, 4026
7231 00:40:35.144649 264 : 4255, 4029
7232 00:40:35.145342 268 : 4250, 4027
7233 00:40:35.147888 272 : 4253, 4029
7234 00:40:35.148330 276 : 4250, 4026
7235 00:40:35.148672 280 : 4255, 4029
7236 00:40:35.151159 284 : 4360, 4138
7237 00:40:35.151598 288 : 4250, 4027
7238 00:40:35.154673 292 : 4360, 4137
7239 00:40:35.155070 296 : 4250, 4027
7240 00:40:35.157945 300 : 4250, 4027
7241 00:40:35.158377 304 : 4250, 4027
7242 00:40:35.161071 308 : 4250, 4026
7243 00:40:35.161465 312 : 4363, 4137
7244 00:40:35.165190 316 : 4250, 4027
7245 00:40:35.165583 320 : 4250, 4027
7246 00:40:35.167740 324 : 4250, 4026
7247 00:40:35.168014 328 : 4255, 4032
7248 00:40:35.170990 332 : 4250, 4027
7249 00:40:35.171202 336 : 4360, 3830
7250 00:40:35.171365 340 : 4250, 1697
7251 00:40:35.174493
7252 00:40:35.174699 MIOCK jitter meter ch=0
7253 00:40:35.174859
7254 00:40:35.177610 1T = (340-100) = 240 dly cells
7255 00:40:35.184346 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 271/100 ps
7256 00:40:35.184487 ==
7257 00:40:35.187309 Dram Type= 6, Freq= 0, CH_0, rank 0
7258 00:40:35.190579 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7259 00:40:35.190709 ==
7260 00:40:35.197486 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7261 00:40:35.200745 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7262 00:40:35.204075 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7263 00:40:35.210610 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7264 00:40:35.219046 [CA 0] Center 41 (11~72) winsize 62
7265 00:40:35.222690 [CA 1] Center 41 (11~72) winsize 62
7266 00:40:35.225600 [CA 2] Center 37 (7~67) winsize 61
7267 00:40:35.229453 [CA 3] Center 37 (7~67) winsize 61
7268 00:40:35.232551 [CA 4] Center 35 (5~66) winsize 62
7269 00:40:35.235691 [CA 5] Center 35 (5~65) winsize 61
7270 00:40:35.235768
7271 00:40:35.239061 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7272 00:40:35.239136
7273 00:40:35.242369 [CATrainingPosCal] consider 1 rank data
7274 00:40:35.245563 u2DelayCellTimex100 = 271/100 ps
7275 00:40:35.249340 CA0 delay=41 (11~72),Diff = 6 PI (21 cell)
7276 00:40:35.255575 CA1 delay=41 (11~72),Diff = 6 PI (21 cell)
7277 00:40:35.258871 CA2 delay=37 (7~67),Diff = 2 PI (7 cell)
7278 00:40:35.262122 CA3 delay=37 (7~67),Diff = 2 PI (7 cell)
7279 00:40:35.265465 CA4 delay=35 (5~66),Diff = 0 PI (0 cell)
7280 00:40:35.268751 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7281 00:40:35.268850
7282 00:40:35.272262 CA PerBit enable=1, Macro0, CA PI delay=35
7283 00:40:35.272361
7284 00:40:35.275280 [CBTSetCACLKResult] CA Dly = 35
7285 00:40:35.278456 CS Dly: 11 (0~42)
7286 00:40:35.281823 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7287 00:40:35.285737 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7288 00:40:35.285813 ==
7289 00:40:35.289480 Dram Type= 6, Freq= 0, CH_0, rank 1
7290 00:40:35.291941 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7291 00:40:35.295177 ==
7292 00:40:35.298455 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7293 00:40:35.301907 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7294 00:40:35.308844 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7295 00:40:35.315152 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7296 00:40:35.321929 [CA 0] Center 42 (12~73) winsize 62
7297 00:40:35.325247 [CA 1] Center 42 (12~73) winsize 62
7298 00:40:35.328812 [CA 2] Center 38 (9~68) winsize 60
7299 00:40:35.331824 [CA 3] Center 37 (8~67) winsize 60
7300 00:40:35.335186 [CA 4] Center 36 (6~66) winsize 61
7301 00:40:35.338317 [CA 5] Center 36 (6~66) winsize 61
7302 00:40:35.338549
7303 00:40:35.341643 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7304 00:40:35.341909
7305 00:40:35.345240 [CATrainingPosCal] consider 2 rank data
7306 00:40:35.348704 u2DelayCellTimex100 = 271/100 ps
7307 00:40:35.351847 CA0 delay=42 (12~72),Diff = 7 PI (25 cell)
7308 00:40:35.358764 CA1 delay=42 (12~72),Diff = 7 PI (25 cell)
7309 00:40:35.361858 CA2 delay=38 (9~67),Diff = 3 PI (10 cell)
7310 00:40:35.365133 CA3 delay=37 (8~67),Diff = 2 PI (7 cell)
7311 00:40:35.368621 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7312 00:40:35.371786 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7313 00:40:35.372173
7314 00:40:35.374960 CA PerBit enable=1, Macro0, CA PI delay=35
7315 00:40:35.375353
7316 00:40:35.378485 [CBTSetCACLKResult] CA Dly = 35
7317 00:40:35.382035 CS Dly: 11 (0~42)
7318 00:40:35.385023 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7319 00:40:35.388430 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7320 00:40:35.388821
7321 00:40:35.391543 ----->DramcWriteLeveling(PI) begin...
7322 00:40:35.391934 ==
7323 00:40:35.394861 Dram Type= 6, Freq= 0, CH_0, rank 0
7324 00:40:35.402342 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7325 00:40:35.402850 ==
7326 00:40:35.404741 Write leveling (Byte 0): 29 => 29
7327 00:40:35.408255 Write leveling (Byte 1): 26 => 26
7328 00:40:35.408694 DramcWriteLeveling(PI) end<-----
7329 00:40:35.409031
7330 00:40:35.411493 ==
7331 00:40:35.414726 Dram Type= 6, Freq= 0, CH_0, rank 0
7332 00:40:35.418298 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7333 00:40:35.418733 ==
7334 00:40:35.421325 [Gating] SW mode calibration
7335 00:40:35.427988 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7336 00:40:35.431259 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7337 00:40:35.438179 0 12 0 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
7338 00:40:35.441314 0 12 4 | B1->B0 | 2c2c 3434 | 0 1 | (0 0) (1 1)
7339 00:40:35.444520 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7340 00:40:35.451612 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7341 00:40:35.454584 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7342 00:40:35.457659 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7343 00:40:35.464577 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7344 00:40:35.468054 0 12 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7345 00:40:35.471027 0 13 0 | B1->B0 | 3434 3232 | 1 0 | (1 0) (1 0)
7346 00:40:35.477639 0 13 4 | B1->B0 | 2b2b 2323 | 0 0 | (1 0) (0 0)
7347 00:40:35.481267 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7348 00:40:35.484649 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7349 00:40:35.487826 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7350 00:40:35.494172 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7351 00:40:35.497989 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7352 00:40:35.501196 0 13 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7353 00:40:35.507946 0 14 0 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
7354 00:40:35.510919 0 14 4 | B1->B0 | 3131 4646 | 1 0 | (0 0) (0 0)
7355 00:40:35.514522 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7356 00:40:35.521254 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7357 00:40:35.524548 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7358 00:40:35.527460 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7359 00:40:35.534629 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7360 00:40:35.537648 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7361 00:40:35.541214 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7362 00:40:35.547706 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7363 00:40:35.551184 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7364 00:40:35.554927 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7365 00:40:35.561101 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7366 00:40:35.564547 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7367 00:40:35.567870 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7368 00:40:35.574382 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7369 00:40:35.577387 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7370 00:40:35.580888 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7371 00:40:35.587263 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7372 00:40:35.591031 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7373 00:40:35.593893 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7374 00:40:35.600663 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7375 00:40:35.604319 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7376 00:40:35.607973 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7377 00:40:35.613822 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7378 00:40:35.617244 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7379 00:40:35.620306 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7380 00:40:35.623812 Total UI for P1: 0, mck2ui 16
7381 00:40:35.627196 best dqsien dly found for B0: ( 1, 1, 0)
7382 00:40:35.630494 Total UI for P1: 0, mck2ui 16
7383 00:40:35.633465 best dqsien dly found for B1: ( 1, 1, 4)
7384 00:40:35.637030 best DQS0 dly(MCK, UI, PI) = (1, 1, 0)
7385 00:40:35.640385 best DQS1 dly(MCK, UI, PI) = (1, 1, 4)
7386 00:40:35.640659
7387 00:40:35.643853 best DQS0 P1 dly(MCK, UI, PI) = (1, 5, 0)
7388 00:40:35.650505 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 4)
7389 00:40:35.650860 [Gating] SW calibration Done
7390 00:40:35.651137 ==
7391 00:40:35.653793 Dram Type= 6, Freq= 0, CH_0, rank 0
7392 00:40:35.660166 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7393 00:40:35.660530 ==
7394 00:40:35.660811 RX Vref Scan: 0
7395 00:40:35.661065
7396 00:40:35.663603 RX Vref 0 -> 0, step: 1
7397 00:40:35.663954
7398 00:40:35.666932 RX Delay 0 -> 252, step: 8
7399 00:40:35.670318 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7400 00:40:35.673725 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
7401 00:40:35.677228 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7402 00:40:35.680381 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7403 00:40:35.686841 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7404 00:40:35.690385 iDelay=200, Bit 5, Center 115 (56 ~ 175) 120
7405 00:40:35.693895 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
7406 00:40:35.697105 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7407 00:40:35.699935 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7408 00:40:35.706954 iDelay=200, Bit 9, Center 107 (56 ~ 159) 104
7409 00:40:35.710315 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7410 00:40:35.713295 iDelay=200, Bit 11, Center 115 (64 ~ 167) 104
7411 00:40:35.716977 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7412 00:40:35.723652 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7413 00:40:35.726983 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7414 00:40:35.729832 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7415 00:40:35.730390 ==
7416 00:40:35.733616 Dram Type= 6, Freq= 0, CH_0, rank 0
7417 00:40:35.736615 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7418 00:40:35.737135 ==
7419 00:40:35.740003 DQS Delay:
7420 00:40:35.740431 DQS0 = 0, DQS1 = 0
7421 00:40:35.743172 DQM Delay:
7422 00:40:35.743772 DQM0 = 130, DQM1 = 123
7423 00:40:35.744123 DQ Delay:
7424 00:40:35.747100 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =127
7425 00:40:35.753177 DQ4 =135, DQ5 =115, DQ6 =139, DQ7 =139
7426 00:40:35.756732 DQ8 =111, DQ9 =107, DQ10 =123, DQ11 =115
7427 00:40:35.760141 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
7428 00:40:35.760667
7429 00:40:35.761003
7430 00:40:35.761317 ==
7431 00:40:35.763272 Dram Type= 6, Freq= 0, CH_0, rank 0
7432 00:40:35.766458 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7433 00:40:35.766897 ==
7434 00:40:35.767234
7435 00:40:35.767537
7436 00:40:35.769691 TX Vref Scan disable
7437 00:40:35.772929 == TX Byte 0 ==
7438 00:40:35.776532 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7439 00:40:35.780045 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7440 00:40:35.783464 == TX Byte 1 ==
7441 00:40:35.786398 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7442 00:40:35.790324 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
7443 00:40:35.790844 ==
7444 00:40:35.793038 Dram Type= 6, Freq= 0, CH_0, rank 0
7445 00:40:35.796302 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7446 00:40:35.799597 ==
7447 00:40:35.810840
7448 00:40:35.814283 TX Vref early break, caculate TX vref
7449 00:40:35.817596 TX Vref=16, minBit 8, minWin=21, winSum=367
7450 00:40:35.820744 TX Vref=18, minBit 8, minWin=22, winSum=380
7451 00:40:35.824220 TX Vref=20, minBit 10, minWin=22, winSum=389
7452 00:40:35.827492 TX Vref=22, minBit 8, minWin=24, winSum=400
7453 00:40:35.830580 TX Vref=24, minBit 9, minWin=24, winSum=403
7454 00:40:35.837320 TX Vref=26, minBit 8, minWin=25, winSum=417
7455 00:40:35.840586 TX Vref=28, minBit 0, minWin=25, winSum=412
7456 00:40:35.843843 TX Vref=30, minBit 8, minWin=24, winSum=411
7457 00:40:35.847157 TX Vref=32, minBit 8, minWin=24, winSum=404
7458 00:40:35.850304 TX Vref=34, minBit 3, minWin=23, winSum=394
7459 00:40:35.857421 [TxChooseVref] Worse bit 8, Min win 25, Win sum 417, Final Vref 26
7460 00:40:35.857945
7461 00:40:35.860449 Final TX Range 0 Vref 26
7462 00:40:35.860886
7463 00:40:35.861224 ==
7464 00:40:35.863948 Dram Type= 6, Freq= 0, CH_0, rank 0
7465 00:40:35.866876 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7466 00:40:35.867422 ==
7467 00:40:35.867934
7468 00:40:35.868438
7469 00:40:35.870173 TX Vref Scan disable
7470 00:40:35.876974 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
7471 00:40:35.877559 == TX Byte 0 ==
7472 00:40:35.880573 u2DelayCellOfst[0]=10 cells (3 PI)
7473 00:40:35.883687 u2DelayCellOfst[1]=18 cells (5 PI)
7474 00:40:35.886967 u2DelayCellOfst[2]=10 cells (3 PI)
7475 00:40:35.890491 u2DelayCellOfst[3]=10 cells (3 PI)
7476 00:40:35.893904 u2DelayCellOfst[4]=7 cells (2 PI)
7477 00:40:35.896922 u2DelayCellOfst[5]=0 cells (0 PI)
7478 00:40:35.900275 u2DelayCellOfst[6]=18 cells (5 PI)
7479 00:40:35.903604 u2DelayCellOfst[7]=18 cells (5 PI)
7480 00:40:35.906794 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7481 00:40:35.910940 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7482 00:40:35.913711 == TX Byte 1 ==
7483 00:40:35.916831 u2DelayCellOfst[8]=3 cells (1 PI)
7484 00:40:35.917224 u2DelayCellOfst[9]=0 cells (0 PI)
7485 00:40:35.920151 u2DelayCellOfst[10]=7 cells (2 PI)
7486 00:40:35.923073 u2DelayCellOfst[11]=7 cells (2 PI)
7487 00:40:35.926457 u2DelayCellOfst[12]=18 cells (5 PI)
7488 00:40:35.929927 u2DelayCellOfst[13]=14 cells (4 PI)
7489 00:40:35.933044 u2DelayCellOfst[14]=18 cells (5 PI)
7490 00:40:35.936491 u2DelayCellOfst[15]=14 cells (4 PI)
7491 00:40:35.940354 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
7492 00:40:35.946472 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
7493 00:40:35.947056 DramC Write-DBI on
7494 00:40:35.947382 ==
7495 00:40:35.950169 Dram Type= 6, Freq= 0, CH_0, rank 0
7496 00:40:35.956756 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7497 00:40:35.957268 ==
7498 00:40:35.957578
7499 00:40:35.957859
7500 00:40:35.958130 TX Vref Scan disable
7501 00:40:35.960159 == TX Byte 0 ==
7502 00:40:35.963444 Update DQM dly =728 (2 ,6, 24) DQM OEN =(3 ,3)
7503 00:40:35.966813 == TX Byte 1 ==
7504 00:40:35.970164 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
7505 00:40:35.973495 DramC Write-DBI off
7506 00:40:35.973912
7507 00:40:35.974378 [DATLAT]
7508 00:40:35.974674 Freq=1600, CH0 RK0
7509 00:40:35.974950
7510 00:40:35.976874 DATLAT Default: 0xf
7511 00:40:35.977263 0, 0xFFFF, sum = 0
7512 00:40:35.980144 1, 0xFFFF, sum = 0
7513 00:40:35.980537 2, 0xFFFF, sum = 0
7514 00:40:35.983601 3, 0xFFFF, sum = 0
7515 00:40:35.986901 4, 0xFFFF, sum = 0
7516 00:40:35.987297 5, 0xFFFF, sum = 0
7517 00:40:35.990026 6, 0xFFFF, sum = 0
7518 00:40:35.990497 7, 0xFFFF, sum = 0
7519 00:40:35.993568 8, 0xFFFF, sum = 0
7520 00:40:35.993989 9, 0xFFFF, sum = 0
7521 00:40:35.996986 10, 0xFFFF, sum = 0
7522 00:40:35.997380 11, 0xFFFF, sum = 0
7523 00:40:35.999955 12, 0xFFF, sum = 0
7524 00:40:36.000353 13, 0x0, sum = 1
7525 00:40:36.003349 14, 0x0, sum = 2
7526 00:40:36.003750 15, 0x0, sum = 3
7527 00:40:36.006565 16, 0x0, sum = 4
7528 00:40:36.006981 best_step = 14
7529 00:40:36.007348
7530 00:40:36.007725 ==
7531 00:40:36.010300 Dram Type= 6, Freq= 0, CH_0, rank 0
7532 00:40:36.013659 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7533 00:40:36.014050 ==
7534 00:40:36.016813 RX Vref Scan: 1
7535 00:40:36.017216
7536 00:40:36.020397 Set Vref Range= 24 -> 127
7537 00:40:36.020819
7538 00:40:36.021298 RX Vref 24 -> 127, step: 1
7539 00:40:36.021690
7540 00:40:36.023306 RX Delay 11 -> 252, step: 4
7541 00:40:36.023810
7542 00:40:36.026709 Set Vref, RX VrefLevel [Byte0]: 24
7543 00:40:36.029889 [Byte1]: 24
7544 00:40:36.033981
7545 00:40:36.034437 Set Vref, RX VrefLevel [Byte0]: 25
7546 00:40:36.036958 [Byte1]: 25
7547 00:40:36.041143
7548 00:40:36.041544 Set Vref, RX VrefLevel [Byte0]: 26
7549 00:40:36.044776 [Byte1]: 26
7550 00:40:36.048616
7551 00:40:36.049029 Set Vref, RX VrefLevel [Byte0]: 27
7552 00:40:36.052380 [Byte1]: 27
7553 00:40:36.056229
7554 00:40:36.056630 Set Vref, RX VrefLevel [Byte0]: 28
7555 00:40:36.059576 [Byte1]: 28
7556 00:40:36.063701
7557 00:40:36.064105 Set Vref, RX VrefLevel [Byte0]: 29
7558 00:40:36.067303 [Byte1]: 29
7559 00:40:36.071333
7560 00:40:36.071734 Set Vref, RX VrefLevel [Byte0]: 30
7561 00:40:36.074641 [Byte1]: 30
7562 00:40:36.079201
7563 00:40:36.079603 Set Vref, RX VrefLevel [Byte0]: 31
7564 00:40:36.082190 [Byte1]: 31
7565 00:40:36.086520
7566 00:40:36.086923 Set Vref, RX VrefLevel [Byte0]: 32
7567 00:40:36.090151 [Byte1]: 32
7568 00:40:36.094627
7569 00:40:36.095030 Set Vref, RX VrefLevel [Byte0]: 33
7570 00:40:36.097755 [Byte1]: 33
7571 00:40:36.101811
7572 00:40:36.102281 Set Vref, RX VrefLevel [Byte0]: 34
7573 00:40:36.105126 [Byte1]: 34
7574 00:40:36.109659
7575 00:40:36.110097 Set Vref, RX VrefLevel [Byte0]: 35
7576 00:40:36.112943 [Byte1]: 35
7577 00:40:36.117334
7578 00:40:36.117785 Set Vref, RX VrefLevel [Byte0]: 36
7579 00:40:36.120665 [Byte1]: 36
7580 00:40:36.124904
7581 00:40:36.125389 Set Vref, RX VrefLevel [Byte0]: 37
7582 00:40:36.128034 [Byte1]: 37
7583 00:40:36.132587
7584 00:40:36.132994 Set Vref, RX VrefLevel [Byte0]: 38
7585 00:40:36.135793 [Byte1]: 38
7586 00:40:36.140361
7587 00:40:36.140765 Set Vref, RX VrefLevel [Byte0]: 39
7588 00:40:36.143065 [Byte1]: 39
7589 00:40:36.147978
7590 00:40:36.148382 Set Vref, RX VrefLevel [Byte0]: 40
7591 00:40:36.150992 [Byte1]: 40
7592 00:40:36.155328
7593 00:40:36.155728 Set Vref, RX VrefLevel [Byte0]: 41
7594 00:40:36.158666 [Byte1]: 41
7595 00:40:36.163041
7596 00:40:36.163491 Set Vref, RX VrefLevel [Byte0]: 42
7597 00:40:36.166267 [Byte1]: 42
7598 00:40:36.170337
7599 00:40:36.170730 Set Vref, RX VrefLevel [Byte0]: 43
7600 00:40:36.173638 [Byte1]: 43
7601 00:40:36.178115
7602 00:40:36.178614 Set Vref, RX VrefLevel [Byte0]: 44
7603 00:40:36.181304 [Byte1]: 44
7604 00:40:36.185905
7605 00:40:36.186380 Set Vref, RX VrefLevel [Byte0]: 45
7606 00:40:36.188959 [Byte1]: 45
7607 00:40:36.193481
7608 00:40:36.193885 Set Vref, RX VrefLevel [Byte0]: 46
7609 00:40:36.196993 [Byte1]: 46
7610 00:40:36.201454
7611 00:40:36.201988 Set Vref, RX VrefLevel [Byte0]: 47
7612 00:40:36.204597 [Byte1]: 47
7613 00:40:36.208759
7614 00:40:36.209240 Set Vref, RX VrefLevel [Byte0]: 48
7615 00:40:36.212388 [Byte1]: 48
7616 00:40:36.216216
7617 00:40:36.216607 Set Vref, RX VrefLevel [Byte0]: 49
7618 00:40:36.219333 [Byte1]: 49
7619 00:40:36.224316
7620 00:40:36.224786 Set Vref, RX VrefLevel [Byte0]: 50
7621 00:40:36.227357 [Byte1]: 50
7622 00:40:36.231212
7623 00:40:36.231688 Set Vref, RX VrefLevel [Byte0]: 51
7624 00:40:36.234996 [Byte1]: 51
7625 00:40:36.238872
7626 00:40:36.239268 Set Vref, RX VrefLevel [Byte0]: 52
7627 00:40:36.242476 [Byte1]: 52
7628 00:40:36.246744
7629 00:40:36.247272 Set Vref, RX VrefLevel [Byte0]: 53
7630 00:40:36.249792 [Byte1]: 53
7631 00:40:36.254397
7632 00:40:36.254803 Set Vref, RX VrefLevel [Byte0]: 54
7633 00:40:36.257623 [Byte1]: 54
7634 00:40:36.261998
7635 00:40:36.262516 Set Vref, RX VrefLevel [Byte0]: 55
7636 00:40:36.265437 [Byte1]: 55
7637 00:40:36.269471
7638 00:40:36.269907 Set Vref, RX VrefLevel [Byte0]: 56
7639 00:40:36.272805 [Byte1]: 56
7640 00:40:36.277035
7641 00:40:36.277470 Set Vref, RX VrefLevel [Byte0]: 57
7642 00:40:36.280410 [Byte1]: 57
7643 00:40:36.284714
7644 00:40:36.285130 Set Vref, RX VrefLevel [Byte0]: 58
7645 00:40:36.288010 [Byte1]: 58
7646 00:40:36.292611
7647 00:40:36.293057 Set Vref, RX VrefLevel [Byte0]: 59
7648 00:40:36.295938 [Byte1]: 59
7649 00:40:36.299958
7650 00:40:36.300490 Set Vref, RX VrefLevel [Byte0]: 60
7651 00:40:36.303419 [Byte1]: 60
7652 00:40:36.307496
7653 00:40:36.307983 Set Vref, RX VrefLevel [Byte0]: 61
7654 00:40:36.311028 [Byte1]: 61
7655 00:40:36.315336
7656 00:40:36.315956 Set Vref, RX VrefLevel [Byte0]: 62
7657 00:40:36.318679 [Byte1]: 62
7658 00:40:36.322806
7659 00:40:36.323335 Set Vref, RX VrefLevel [Byte0]: 63
7660 00:40:36.326169 [Byte1]: 63
7661 00:40:36.330523
7662 00:40:36.331003 Set Vref, RX VrefLevel [Byte0]: 64
7663 00:40:36.333949 [Byte1]: 64
7664 00:40:36.337851
7665 00:40:36.338370 Set Vref, RX VrefLevel [Byte0]: 65
7666 00:40:36.341171 [Byte1]: 65
7667 00:40:36.345517
7668 00:40:36.345948 Set Vref, RX VrefLevel [Byte0]: 66
7669 00:40:36.348856 [Byte1]: 66
7670 00:40:36.353501
7671 00:40:36.354003 Set Vref, RX VrefLevel [Byte0]: 67
7672 00:40:36.356837 [Byte1]: 67
7673 00:40:36.361060
7674 00:40:36.361698 Set Vref, RX VrefLevel [Byte0]: 68
7675 00:40:36.364005 [Byte1]: 68
7676 00:40:36.368528
7677 00:40:36.368986 Set Vref, RX VrefLevel [Byte0]: 69
7678 00:40:36.372127 [Byte1]: 69
7679 00:40:36.376264
7680 00:40:36.376995 Set Vref, RX VrefLevel [Byte0]: 70
7681 00:40:36.379457 [Byte1]: 70
7682 00:40:36.383595
7683 00:40:36.384149 Set Vref, RX VrefLevel [Byte0]: 71
7684 00:40:36.386774 [Byte1]: 71
7685 00:40:36.391118
7686 00:40:36.391680 Final RX Vref Byte 0 = 56 to rank0
7687 00:40:36.394926 Final RX Vref Byte 1 = 55 to rank0
7688 00:40:36.397691 Final RX Vref Byte 0 = 56 to rank1
7689 00:40:36.401254 Final RX Vref Byte 1 = 55 to rank1==
7690 00:40:36.404511 Dram Type= 6, Freq= 0, CH_0, rank 0
7691 00:40:36.410873 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7692 00:40:36.411422 ==
7693 00:40:36.411918 DQS Delay:
7694 00:40:36.414387 DQS0 = 0, DQS1 = 0
7695 00:40:36.415004 DQM Delay:
7696 00:40:36.415481 DQM0 = 127, DQM1 = 120
7697 00:40:36.417861 DQ Delay:
7698 00:40:36.421241 DQ0 =122, DQ1 =128, DQ2 =124, DQ3 =124
7699 00:40:36.424722 DQ4 =130, DQ5 =116, DQ6 =138, DQ7 =134
7700 00:40:36.427778 DQ8 =110, DQ9 =104, DQ10 =120, DQ11 =112
7701 00:40:36.430904 DQ12 =126, DQ13 =126, DQ14 =134, DQ15 =132
7702 00:40:36.431322
7703 00:40:36.431681
7704 00:40:36.431969
7705 00:40:36.434327 [DramC_TX_OE_Calibration] TA2
7706 00:40:36.437469 Original DQ_B0 (3 6) =30, OEN = 27
7707 00:40:36.441116 Original DQ_B1 (3 6) =30, OEN = 27
7708 00:40:36.444463 24, 0x0, End_B0=24 End_B1=24
7709 00:40:36.444862 25, 0x0, End_B0=25 End_B1=25
7710 00:40:36.447838 26, 0x0, End_B0=26 End_B1=26
7711 00:40:36.451051 27, 0x0, End_B0=27 End_B1=27
7712 00:40:36.454157 28, 0x0, End_B0=28 End_B1=28
7713 00:40:36.457417 29, 0x0, End_B0=29 End_B1=29
7714 00:40:36.457815 30, 0x0, End_B0=30 End_B1=30
7715 00:40:36.460490 31, 0x4141, End_B0=30 End_B1=30
7716 00:40:36.464214 Byte0 end_step=30 best_step=27
7717 00:40:36.467622 Byte1 end_step=30 best_step=27
7718 00:40:36.470560 Byte0 TX OE(2T, 0.5T) = (3, 3)
7719 00:40:36.473830 Byte1 TX OE(2T, 0.5T) = (3, 3)
7720 00:40:36.474254
7721 00:40:36.474574
7722 00:40:36.480724 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a1a, (MSB)MR19= 0x303, tDQSOscB0 = 396 ps tDQSOscB1 = 396 ps
7723 00:40:36.483956 CH0 RK0: MR19=303, MR18=1A1A
7724 00:40:36.490651 CH0_RK0: MR19=0x303, MR18=0x1A1A, DQSOSC=396, MR23=63, INC=23, DEC=15
7725 00:40:36.491049
7726 00:40:36.493672 ----->DramcWriteLeveling(PI) begin...
7727 00:40:36.494067 ==
7728 00:40:36.496930 Dram Type= 6, Freq= 0, CH_0, rank 1
7729 00:40:36.500523 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7730 00:40:36.500996 ==
7731 00:40:36.503540 Write leveling (Byte 0): 29 => 29
7732 00:40:36.506852 Write leveling (Byte 1): 27 => 27
7733 00:40:36.510447 DramcWriteLeveling(PI) end<-----
7734 00:40:36.510925
7735 00:40:36.511236 ==
7736 00:40:36.513686 Dram Type= 6, Freq= 0, CH_0, rank 1
7737 00:40:36.516922 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7738 00:40:36.517318 ==
7739 00:40:36.520147 [Gating] SW mode calibration
7740 00:40:36.526906 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7741 00:40:36.533537 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7742 00:40:36.536745 0 12 0 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
7743 00:40:36.543553 0 12 4 | B1->B0 | 2828 3434 | 0 1 | (0 0) (1 1)
7744 00:40:36.546590 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7745 00:40:36.550104 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7746 00:40:36.556480 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7747 00:40:36.560113 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7748 00:40:36.563159 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7749 00:40:36.569815 0 12 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7750 00:40:36.573527 0 13 0 | B1->B0 | 3434 2a2a | 1 1 | (1 0) (1 0)
7751 00:40:36.576635 0 13 4 | B1->B0 | 3030 2323 | 0 0 | (1 0) (0 0)
7752 00:40:36.582921 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7753 00:40:36.586555 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7754 00:40:36.589920 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7755 00:40:36.596794 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7756 00:40:36.599584 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7757 00:40:36.603029 0 13 28 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
7758 00:40:36.609787 0 14 0 | B1->B0 | 2424 4242 | 0 0 | (0 0) (0 0)
7759 00:40:36.612974 0 14 4 | B1->B0 | 3e3e 4646 | 0 0 | (1 1) (0 0)
7760 00:40:36.616020 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7761 00:40:36.622630 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7762 00:40:36.626034 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7763 00:40:36.629266 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7764 00:40:36.635911 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7765 00:40:36.639128 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7766 00:40:36.642704 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7767 00:40:36.646008 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7768 00:40:36.653045 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7769 00:40:36.655906 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7770 00:40:36.659241 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7771 00:40:36.665881 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7772 00:40:36.669028 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7773 00:40:36.672816 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7774 00:40:36.679022 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7775 00:40:36.682376 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7776 00:40:36.685906 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7777 00:40:36.692876 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7778 00:40:36.696211 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7779 00:40:36.699164 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7780 00:40:36.705868 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7781 00:40:36.709110 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7782 00:40:36.712198 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7783 00:40:36.718937 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7784 00:40:36.719332 Total UI for P1: 0, mck2ui 16
7785 00:40:36.725245 best dqsien dly found for B0: ( 1, 0, 30)
7786 00:40:36.728547 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7787 00:40:36.731857 Total UI for P1: 0, mck2ui 16
7788 00:40:36.735029 best dqsien dly found for B1: ( 1, 1, 2)
7789 00:40:36.738413 best DQS0 dly(MCK, UI, PI) = (1, 0, 30)
7790 00:40:36.741556 best DQS1 dly(MCK, UI, PI) = (1, 1, 2)
7791 00:40:36.741677
7792 00:40:36.744940 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 30)
7793 00:40:36.748265 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 2)
7794 00:40:36.751499 [Gating] SW calibration Done
7795 00:40:36.751606 ==
7796 00:40:36.754931 Dram Type= 6, Freq= 0, CH_0, rank 1
7797 00:40:36.758338 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7798 00:40:36.761802 ==
7799 00:40:36.761908 RX Vref Scan: 0
7800 00:40:36.761991
7801 00:40:36.764935 RX Vref 0 -> 0, step: 1
7802 00:40:36.765042
7803 00:40:36.765125 RX Delay 0 -> 252, step: 8
7804 00:40:36.771854 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7805 00:40:36.775161 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
7806 00:40:36.778591 iDelay=200, Bit 2, Center 131 (72 ~ 191) 120
7807 00:40:36.781551 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
7808 00:40:36.788267 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
7809 00:40:36.791712 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7810 00:40:36.794801 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
7811 00:40:36.798287 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7812 00:40:36.801594 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7813 00:40:36.805056 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7814 00:40:36.811660 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7815 00:40:36.814971 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7816 00:40:36.818626 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7817 00:40:36.822126 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7818 00:40:36.828033 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7819 00:40:36.831685 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7820 00:40:36.832301 ==
7821 00:40:36.834583 Dram Type= 6, Freq= 0, CH_0, rank 1
7822 00:40:36.838129 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7823 00:40:36.838605 ==
7824 00:40:36.841539 DQS Delay:
7825 00:40:36.842046 DQS0 = 0, DQS1 = 0
7826 00:40:36.842456 DQM Delay:
7827 00:40:36.844595 DQM0 = 130, DQM1 = 124
7828 00:40:36.845029 DQ Delay:
7829 00:40:36.848086 DQ0 =127, DQ1 =135, DQ2 =131, DQ3 =123
7830 00:40:36.851177 DQ4 =131, DQ5 =119, DQ6 =139, DQ7 =139
7831 00:40:36.854446 DQ8 =111, DQ9 =111, DQ10 =123, DQ11 =119
7832 00:40:36.861337 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =131
7833 00:40:36.861772
7834 00:40:36.862105
7835 00:40:36.862471 ==
7836 00:40:36.864365 Dram Type= 6, Freq= 0, CH_0, rank 1
7837 00:40:36.868007 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7838 00:40:36.868445 ==
7839 00:40:36.868784
7840 00:40:36.869095
7841 00:40:36.871192 TX Vref Scan disable
7842 00:40:36.871629 == TX Byte 0 ==
7843 00:40:36.877888 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7844 00:40:36.881311 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7845 00:40:36.881779 == TX Byte 1 ==
7846 00:40:36.887595 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7847 00:40:36.891562 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7848 00:40:36.892074 ==
7849 00:40:36.894896 Dram Type= 6, Freq= 0, CH_0, rank 1
7850 00:40:36.898092 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7851 00:40:36.898602 ==
7852 00:40:36.912260
7853 00:40:36.915030 TX Vref early break, caculate TX vref
7854 00:40:36.918687 TX Vref=16, minBit 8, minWin=21, winSum=375
7855 00:40:36.921603 TX Vref=18, minBit 8, minWin=22, winSum=385
7856 00:40:36.924714 TX Vref=20, minBit 1, minWin=24, winSum=397
7857 00:40:36.928298 TX Vref=22, minBit 8, minWin=24, winSum=402
7858 00:40:36.931481 TX Vref=24, minBit 7, minWin=24, winSum=405
7859 00:40:36.938424 TX Vref=26, minBit 1, minWin=25, winSum=409
7860 00:40:36.941709 TX Vref=28, minBit 8, minWin=25, winSum=418
7861 00:40:36.944809 TX Vref=30, minBit 8, minWin=24, winSum=410
7862 00:40:36.948231 TX Vref=32, minBit 1, minWin=24, winSum=397
7863 00:40:36.951617 TX Vref=34, minBit 1, minWin=24, winSum=395
7864 00:40:36.958133 [TxChooseVref] Worse bit 8, Min win 25, Win sum 418, Final Vref 28
7865 00:40:36.958602
7866 00:40:36.961732 Final TX Range 0 Vref 28
7867 00:40:36.962162
7868 00:40:36.962564 ==
7869 00:40:36.964662 Dram Type= 6, Freq= 0, CH_0, rank 1
7870 00:40:36.968344 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7871 00:40:36.968784 ==
7872 00:40:36.969091
7873 00:40:36.969373
7874 00:40:36.971661 TX Vref Scan disable
7875 00:40:36.978023 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
7876 00:40:36.978495 == TX Byte 0 ==
7877 00:40:36.981311 u2DelayCellOfst[0]=14 cells (4 PI)
7878 00:40:36.984472 u2DelayCellOfst[1]=18 cells (5 PI)
7879 00:40:36.988002 u2DelayCellOfst[2]=10 cells (3 PI)
7880 00:40:36.991053 u2DelayCellOfst[3]=14 cells (4 PI)
7881 00:40:36.994408 u2DelayCellOfst[4]=10 cells (3 PI)
7882 00:40:36.997768 u2DelayCellOfst[5]=0 cells (0 PI)
7883 00:40:37.001198 u2DelayCellOfst[6]=18 cells (5 PI)
7884 00:40:37.004649 u2DelayCellOfst[7]=18 cells (5 PI)
7885 00:40:37.008011 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7886 00:40:37.011582 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7887 00:40:37.014707 == TX Byte 1 ==
7888 00:40:37.015152 u2DelayCellOfst[8]=3 cells (1 PI)
7889 00:40:37.018009 u2DelayCellOfst[9]=0 cells (0 PI)
7890 00:40:37.021126 u2DelayCellOfst[10]=7 cells (2 PI)
7891 00:40:37.024807 u2DelayCellOfst[11]=3 cells (1 PI)
7892 00:40:37.027943 u2DelayCellOfst[12]=14 cells (4 PI)
7893 00:40:37.031453 u2DelayCellOfst[13]=14 cells (4 PI)
7894 00:40:37.034845 u2DelayCellOfst[14]=18 cells (5 PI)
7895 00:40:37.037924 u2DelayCellOfst[15]=14 cells (4 PI)
7896 00:40:37.041445 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
7897 00:40:37.047988 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7898 00:40:37.048570 DramC Write-DBI on
7899 00:40:37.048954 ==
7900 00:40:37.051045 Dram Type= 6, Freq= 0, CH_0, rank 1
7901 00:40:37.054375 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7902 00:40:37.057730 ==
7903 00:40:37.058161
7904 00:40:37.058529
7905 00:40:37.058840 TX Vref Scan disable
7906 00:40:37.061183 == TX Byte 0 ==
7907 00:40:37.064287 Update DQM dly =728 (2 ,6, 24) DQM OEN =(3 ,3)
7908 00:40:37.067867 == TX Byte 1 ==
7909 00:40:37.071272 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
7910 00:40:37.074134 DramC Write-DBI off
7911 00:40:37.074601
7912 00:40:37.074940 [DATLAT]
7913 00:40:37.075252 Freq=1600, CH0 RK1
7914 00:40:37.075553
7915 00:40:37.077496 DATLAT Default: 0xe
7916 00:40:37.077900 0, 0xFFFF, sum = 0
7917 00:40:37.081020 1, 0xFFFF, sum = 0
7918 00:40:37.084325 2, 0xFFFF, sum = 0
7919 00:40:37.084723 3, 0xFFFF, sum = 0
7920 00:40:37.087512 4, 0xFFFF, sum = 0
7921 00:40:37.087912 5, 0xFFFF, sum = 0
7922 00:40:37.090920 6, 0xFFFF, sum = 0
7923 00:40:37.091320 7, 0xFFFF, sum = 0
7924 00:40:37.094281 8, 0xFFFF, sum = 0
7925 00:40:37.094679 9, 0xFFFF, sum = 0
7926 00:40:37.097833 10, 0xFFFF, sum = 0
7927 00:40:37.098265 11, 0xFFFF, sum = 0
7928 00:40:37.101112 12, 0x8FFF, sum = 0
7929 00:40:37.101510 13, 0x0, sum = 1
7930 00:40:37.104445 14, 0x0, sum = 2
7931 00:40:37.104839 15, 0x0, sum = 3
7932 00:40:37.107708 16, 0x0, sum = 4
7933 00:40:37.108202 best_step = 14
7934 00:40:37.108517
7935 00:40:37.108801 ==
7936 00:40:37.110743 Dram Type= 6, Freq= 0, CH_0, rank 1
7937 00:40:37.114311 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7938 00:40:37.114801 ==
7939 00:40:37.117785 RX Vref Scan: 0
7940 00:40:37.118169
7941 00:40:37.121139 RX Vref 0 -> 0, step: 1
7942 00:40:37.121607
7943 00:40:37.121906 RX Delay 11 -> 252, step: 4
7944 00:40:37.128152 iDelay=195, Bit 0, Center 124 (71 ~ 178) 108
7945 00:40:37.131747 iDelay=195, Bit 1, Center 130 (79 ~ 182) 104
7946 00:40:37.134868 iDelay=195, Bit 2, Center 126 (71 ~ 182) 112
7947 00:40:37.138029 iDelay=195, Bit 3, Center 122 (67 ~ 178) 112
7948 00:40:37.141514 iDelay=195, Bit 4, Center 130 (71 ~ 190) 120
7949 00:40:37.148286 iDelay=195, Bit 5, Center 120 (67 ~ 174) 108
7950 00:40:37.151546 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
7951 00:40:37.155005 iDelay=195, Bit 7, Center 138 (83 ~ 194) 112
7952 00:40:37.158062 iDelay=195, Bit 8, Center 108 (55 ~ 162) 108
7953 00:40:37.161380 iDelay=195, Bit 9, Center 106 (51 ~ 162) 112
7954 00:40:37.168064 iDelay=195, Bit 10, Center 122 (67 ~ 178) 112
7955 00:40:37.171870 iDelay=195, Bit 11, Center 112 (59 ~ 166) 108
7956 00:40:37.175009 iDelay=195, Bit 12, Center 126 (71 ~ 182) 112
7957 00:40:37.178106 iDelay=195, Bit 13, Center 126 (71 ~ 182) 112
7958 00:40:37.181643 iDelay=195, Bit 14, Center 130 (75 ~ 186) 112
7959 00:40:37.188303 iDelay=195, Bit 15, Center 130 (75 ~ 186) 112
7960 00:40:37.188791 ==
7961 00:40:37.191740 Dram Type= 6, Freq= 0, CH_0, rank 1
7962 00:40:37.195181 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7963 00:40:37.195568 ==
7964 00:40:37.195868 DQS Delay:
7965 00:40:37.197925 DQS0 = 0, DQS1 = 0
7966 00:40:37.198430 DQM Delay:
7967 00:40:37.201597 DQM0 = 128, DQM1 = 120
7968 00:40:37.201983 DQ Delay:
7969 00:40:37.204708 DQ0 =124, DQ1 =130, DQ2 =126, DQ3 =122
7970 00:40:37.207949 DQ4 =130, DQ5 =120, DQ6 =138, DQ7 =138
7971 00:40:37.211286 DQ8 =108, DQ9 =106, DQ10 =122, DQ11 =112
7972 00:40:37.217827 DQ12 =126, DQ13 =126, DQ14 =130, DQ15 =130
7973 00:40:37.218305
7974 00:40:37.218616
7975 00:40:37.218897
7976 00:40:37.221127 [DramC_TX_OE_Calibration] TA2
7977 00:40:37.221614 Original DQ_B0 (3 6) =30, OEN = 27
7978 00:40:37.224234 Original DQ_B1 (3 6) =30, OEN = 27
7979 00:40:37.227486 24, 0x0, End_B0=24 End_B1=24
7980 00:40:37.230778 25, 0x0, End_B0=25 End_B1=25
7981 00:40:37.234463 26, 0x0, End_B0=26 End_B1=26
7982 00:40:37.234863 27, 0x0, End_B0=27 End_B1=27
7983 00:40:37.237376 28, 0x0, End_B0=28 End_B1=28
7984 00:40:37.240923 29, 0x0, End_B0=29 End_B1=29
7985 00:40:37.244675 30, 0x0, End_B0=30 End_B1=30
7986 00:40:37.247731 31, 0x4141, End_B0=30 End_B1=30
7987 00:40:37.250627 Byte0 end_step=30 best_step=27
7988 00:40:37.251201 Byte1 end_step=30 best_step=27
7989 00:40:37.254175 Byte0 TX OE(2T, 0.5T) = (3, 3)
7990 00:40:37.257448 Byte1 TX OE(2T, 0.5T) = (3, 3)
7991 00:40:37.257852
7992 00:40:37.258154
7993 00:40:37.267811 [DQSOSCAuto] RK1, (LSB)MR18= 0x2121, (MSB)MR19= 0x303, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
7994 00:40:37.268205 CH0 RK1: MR19=303, MR18=2121
7995 00:40:37.274327 CH0_RK1: MR19=0x303, MR18=0x2121, DQSOSC=393, MR23=63, INC=23, DEC=15
7996 00:40:37.277582 [RxdqsGatingPostProcess] freq 1600
7997 00:40:37.284103 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
7998 00:40:37.287118 Pre-setting of DQS Precalculation
7999 00:40:37.290900 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
8000 00:40:37.291290 ==
8001 00:40:37.293815 Dram Type= 6, Freq= 0, CH_1, rank 0
8002 00:40:37.300696 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8003 00:40:37.301171 ==
8004 00:40:37.304038 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8005 00:40:37.310555 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8006 00:40:37.313657 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8007 00:40:37.320270 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8008 00:40:37.327005 [CA 0] Center 41 (11~71) winsize 61
8009 00:40:37.330303 [CA 1] Center 41 (11~71) winsize 61
8010 00:40:37.333516 [CA 2] Center 37 (8~67) winsize 60
8011 00:40:37.336967 [CA 3] Center 36 (6~66) winsize 61
8012 00:40:37.341046 [CA 4] Center 34 (4~64) winsize 61
8013 00:40:37.343632 [CA 5] Center 34 (4~64) winsize 61
8014 00:40:37.344020
8015 00:40:37.346828 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8016 00:40:37.347258
8017 00:40:37.350299 [CATrainingPosCal] consider 1 rank data
8018 00:40:37.353765 u2DelayCellTimex100 = 271/100 ps
8019 00:40:37.357004 CA0 delay=41 (11~71),Diff = 7 PI (25 cell)
8020 00:40:37.363598 CA1 delay=41 (11~71),Diff = 7 PI (25 cell)
8021 00:40:37.366727 CA2 delay=37 (8~67),Diff = 3 PI (10 cell)
8022 00:40:37.370207 CA3 delay=36 (6~66),Diff = 2 PI (7 cell)
8023 00:40:37.374174 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
8024 00:40:37.377150 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
8025 00:40:37.377739
8026 00:40:37.380154 CA PerBit enable=1, Macro0, CA PI delay=34
8027 00:40:37.380538
8028 00:40:37.384220 [CBTSetCACLKResult] CA Dly = 34
8029 00:40:37.386813 CS Dly: 8 (0~39)
8030 00:40:37.390181 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8031 00:40:37.393596 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8032 00:40:37.394162 ==
8033 00:40:37.397435 Dram Type= 6, Freq= 0, CH_1, rank 1
8034 00:40:37.400337 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8035 00:40:37.403669 ==
8036 00:40:37.406819 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8037 00:40:37.410348 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8038 00:40:37.417017 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8039 00:40:37.420501 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8040 00:40:37.429366 [CA 0] Center 41 (11~71) winsize 61
8041 00:40:37.432979 [CA 1] Center 41 (11~71) winsize 61
8042 00:40:37.436294 [CA 2] Center 36 (7~66) winsize 60
8043 00:40:37.439305 [CA 3] Center 36 (7~65) winsize 59
8044 00:40:37.442880 [CA 4] Center 34 (5~64) winsize 60
8045 00:40:37.446024 [CA 5] Center 34 (4~64) winsize 61
8046 00:40:37.446543
8047 00:40:37.449560 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8048 00:40:37.450022
8049 00:40:37.452730 [CATrainingPosCal] consider 2 rank data
8050 00:40:37.455966 u2DelayCellTimex100 = 271/100 ps
8051 00:40:37.459641 CA0 delay=41 (11~71),Diff = 7 PI (25 cell)
8052 00:40:37.466061 CA1 delay=41 (11~71),Diff = 7 PI (25 cell)
8053 00:40:37.469131 CA2 delay=37 (8~66),Diff = 3 PI (10 cell)
8054 00:40:37.472704 CA3 delay=36 (7~65),Diff = 2 PI (7 cell)
8055 00:40:37.476189 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
8056 00:40:37.479214 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
8057 00:40:37.479603
8058 00:40:37.482516 CA PerBit enable=1, Macro0, CA PI delay=34
8059 00:40:37.482906
8060 00:40:37.485951 [CBTSetCACLKResult] CA Dly = 34
8061 00:40:37.489004 CS Dly: 8 (0~40)
8062 00:40:37.492709 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8063 00:40:37.495927 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8064 00:40:37.496318
8065 00:40:37.499030 ----->DramcWriteLeveling(PI) begin...
8066 00:40:37.499426 ==
8067 00:40:37.502514 Dram Type= 6, Freq= 0, CH_1, rank 0
8068 00:40:37.509321 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8069 00:40:37.509769 ==
8070 00:40:37.512735 Write leveling (Byte 0): 23 => 23
8071 00:40:37.513179 Write leveling (Byte 1): 21 => 21
8072 00:40:37.515676 DramcWriteLeveling(PI) end<-----
8073 00:40:37.516062
8074 00:40:37.519267 ==
8075 00:40:37.519706 Dram Type= 6, Freq= 0, CH_1, rank 0
8076 00:40:37.525516 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8077 00:40:37.525964 ==
8078 00:40:37.529116 [Gating] SW mode calibration
8079 00:40:37.535858 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8080 00:40:37.538924 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8081 00:40:37.545222 0 12 0 | B1->B0 | 2525 3434 | 0 1 | (0 0) (1 1)
8082 00:40:37.548473 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8083 00:40:37.552282 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8084 00:40:37.558885 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8085 00:40:37.562138 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8086 00:40:37.565308 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8087 00:40:37.572369 0 12 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
8088 00:40:37.575248 0 12 28 | B1->B0 | 3434 2626 | 1 0 | (1 1) (1 0)
8089 00:40:37.578716 0 13 0 | B1->B0 | 3131 2323 | 0 0 | (0 1) (1 0)
8090 00:40:37.585125 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8091 00:40:37.588910 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8092 00:40:37.592329 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8093 00:40:37.598488 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8094 00:40:37.602531 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8095 00:40:37.605280 0 13 24 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
8096 00:40:37.612242 0 13 28 | B1->B0 | 2323 4343 | 0 0 | (0 0) (0 0)
8097 00:40:37.615584 0 14 0 | B1->B0 | 3131 4646 | 0 0 | (0 0) (0 0)
8098 00:40:37.618510 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8099 00:40:37.622443 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8100 00:40:37.628697 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8101 00:40:37.631592 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8102 00:40:37.635276 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8103 00:40:37.641979 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8104 00:40:37.645442 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8105 00:40:37.648768 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8106 00:40:37.655237 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8107 00:40:37.658658 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8108 00:40:37.661470 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8109 00:40:37.668228 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8110 00:40:37.671438 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8111 00:40:37.675175 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8112 00:40:37.681583 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8113 00:40:37.684830 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8114 00:40:37.688265 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8115 00:40:37.695553 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8116 00:40:37.698010 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8117 00:40:37.701251 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8118 00:40:37.708339 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8119 00:40:37.711503 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8120 00:40:37.714790 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8121 00:40:37.721614 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8122 00:40:37.722127 Total UI for P1: 0, mck2ui 16
8123 00:40:37.728353 best dqsien dly found for B0: ( 1, 0, 26)
8124 00:40:37.731059 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8125 00:40:37.734827 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8126 00:40:37.738260 Total UI for P1: 0, mck2ui 16
8127 00:40:37.741489 best dqsien dly found for B1: ( 1, 1, 2)
8128 00:40:37.744659 best DQS0 dly(MCK, UI, PI) = (1, 0, 26)
8129 00:40:37.747789 best DQS1 dly(MCK, UI, PI) = (1, 1, 2)
8130 00:40:37.748370
8131 00:40:37.754600 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 26)
8132 00:40:37.757925 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 2)
8133 00:40:37.758611 [Gating] SW calibration Done
8134 00:40:37.759157 ==
8135 00:40:37.761605 Dram Type= 6, Freq= 0, CH_1, rank 0
8136 00:40:37.767832 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8137 00:40:37.768346 ==
8138 00:40:37.768798 RX Vref Scan: 0
8139 00:40:37.769209
8140 00:40:37.770836 RX Vref 0 -> 0, step: 1
8141 00:40:37.771279
8142 00:40:37.774187 RX Delay 0 -> 252, step: 8
8143 00:40:37.777518 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8144 00:40:37.780725 iDelay=200, Bit 1, Center 119 (64 ~ 175) 112
8145 00:40:37.784738 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8146 00:40:37.790944 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
8147 00:40:37.794005 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8148 00:40:37.797778 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8149 00:40:37.801317 iDelay=200, Bit 6, Center 135 (80 ~ 191) 112
8150 00:40:37.804373 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8151 00:40:37.811117 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8152 00:40:37.814408 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8153 00:40:37.817303 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8154 00:40:37.821031 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8155 00:40:37.824377 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8156 00:40:37.830732 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8157 00:40:37.834069 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8158 00:40:37.837757 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8159 00:40:37.838346 ==
8160 00:40:37.840841 Dram Type= 6, Freq= 0, CH_1, rank 0
8161 00:40:37.844606 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8162 00:40:37.845131 ==
8163 00:40:37.847578 DQS Delay:
8164 00:40:37.848003 DQS0 = 0, DQS1 = 0
8165 00:40:37.850811 DQM Delay:
8166 00:40:37.851236 DQM0 = 130, DQM1 = 124
8167 00:40:37.851567 DQ Delay:
8168 00:40:37.857507 DQ0 =135, DQ1 =119, DQ2 =119, DQ3 =131
8169 00:40:37.861065 DQ4 =131, DQ5 =143, DQ6 =135, DQ7 =127
8170 00:40:37.863692 DQ8 =107, DQ9 =115, DQ10 =123, DQ11 =115
8171 00:40:37.867294 DQ12 =131, DQ13 =139, DQ14 =131, DQ15 =135
8172 00:40:37.867894
8173 00:40:37.868240
8174 00:40:37.868623 ==
8175 00:40:37.870369 Dram Type= 6, Freq= 0, CH_1, rank 0
8176 00:40:37.873810 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8177 00:40:37.874206 ==
8178 00:40:37.874552
8179 00:40:37.874837
8180 00:40:37.877288 TX Vref Scan disable
8181 00:40:37.880508 == TX Byte 0 ==
8182 00:40:37.884041 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8183 00:40:37.887116 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
8184 00:40:37.890591 == TX Byte 1 ==
8185 00:40:37.894104 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
8186 00:40:37.897802 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8187 00:40:37.898518 ==
8188 00:40:37.900611 Dram Type= 6, Freq= 0, CH_1, rank 0
8189 00:40:37.903505 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8190 00:40:37.906958 ==
8191 00:40:37.917875
8192 00:40:37.921294 TX Vref early break, caculate TX vref
8193 00:40:37.924662 TX Vref=16, minBit 0, minWin=21, winSum=369
8194 00:40:37.928283 TX Vref=18, minBit 3, minWin=22, winSum=377
8195 00:40:37.931135 TX Vref=20, minBit 0, minWin=23, winSum=391
8196 00:40:37.934287 TX Vref=22, minBit 3, minWin=23, winSum=397
8197 00:40:37.937552 TX Vref=24, minBit 3, minWin=23, winSum=405
8198 00:40:37.944366 TX Vref=26, minBit 1, minWin=24, winSum=414
8199 00:40:37.947651 TX Vref=28, minBit 0, minWin=25, winSum=415
8200 00:40:37.951121 TX Vref=30, minBit 0, minWin=25, winSum=408
8201 00:40:37.954317 TX Vref=32, minBit 1, minWin=24, winSum=401
8202 00:40:37.957489 TX Vref=34, minBit 2, minWin=23, winSum=389
8203 00:40:37.964604 [TxChooseVref] Worse bit 0, Min win 25, Win sum 415, Final Vref 28
8204 00:40:37.965138
8205 00:40:37.967399 Final TX Range 0 Vref 28
8206 00:40:37.967792
8207 00:40:37.968094 ==
8208 00:40:37.970931 Dram Type= 6, Freq= 0, CH_1, rank 0
8209 00:40:37.974131 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8210 00:40:37.974569 ==
8211 00:40:37.974893
8212 00:40:37.975352
8213 00:40:37.977442 TX Vref Scan disable
8214 00:40:37.984418 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8215 00:40:37.984890 == TX Byte 0 ==
8216 00:40:37.988185 u2DelayCellOfst[0]=14 cells (4 PI)
8217 00:40:37.990926 u2DelayCellOfst[1]=10 cells (3 PI)
8218 00:40:37.994168 u2DelayCellOfst[2]=0 cells (0 PI)
8219 00:40:37.997195 u2DelayCellOfst[3]=7 cells (2 PI)
8220 00:40:38.001060 u2DelayCellOfst[4]=7 cells (2 PI)
8221 00:40:38.004457 u2DelayCellOfst[5]=14 cells (4 PI)
8222 00:40:38.007594 u2DelayCellOfst[6]=14 cells (4 PI)
8223 00:40:38.008061 u2DelayCellOfst[7]=7 cells (2 PI)
8224 00:40:38.014328 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
8225 00:40:38.017410 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
8226 00:40:38.020751 == TX Byte 1 ==
8227 00:40:38.021138 u2DelayCellOfst[8]=0 cells (0 PI)
8228 00:40:38.023907 u2DelayCellOfst[9]=7 cells (2 PI)
8229 00:40:38.026998 u2DelayCellOfst[10]=10 cells (3 PI)
8230 00:40:38.030561 u2DelayCellOfst[11]=3 cells (1 PI)
8231 00:40:38.033442 u2DelayCellOfst[12]=18 cells (5 PI)
8232 00:40:38.036926 u2DelayCellOfst[13]=18 cells (5 PI)
8233 00:40:38.040347 u2DelayCellOfst[14]=18 cells (5 PI)
8234 00:40:38.043616 u2DelayCellOfst[15]=18 cells (5 PI)
8235 00:40:38.046760 Update DQ dly =972 (3 ,6, 12) DQ OEN =(3 ,3)
8236 00:40:38.053517 Update DQM dly =974 (3 ,6, 14) DQM OEN =(3 ,3)
8237 00:40:38.053978 DramC Write-DBI on
8238 00:40:38.054328 ==
8239 00:40:38.057294 Dram Type= 6, Freq= 0, CH_1, rank 0
8240 00:40:38.063156 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8241 00:40:38.063546 ==
8242 00:40:38.063847
8243 00:40:38.064121
8244 00:40:38.064382 TX Vref Scan disable
8245 00:40:38.066851 == TX Byte 0 ==
8246 00:40:38.070677 Update DQM dly =719 (2 ,6, 15) DQM OEN =(3 ,3)
8247 00:40:38.073477 == TX Byte 1 ==
8248 00:40:38.076883 Update DQM dly =716 (2 ,6, 12) DQM OEN =(3 ,3)
8249 00:40:38.080924 DramC Write-DBI off
8250 00:40:38.081396
8251 00:40:38.081702 [DATLAT]
8252 00:40:38.082022 Freq=1600, CH1 RK0
8253 00:40:38.082461
8254 00:40:38.083571 DATLAT Default: 0xf
8255 00:40:38.086803 0, 0xFFFF, sum = 0
8256 00:40:38.087248 1, 0xFFFF, sum = 0
8257 00:40:38.090077 2, 0xFFFF, sum = 0
8258 00:40:38.090586 3, 0xFFFF, sum = 0
8259 00:40:38.093735 4, 0xFFFF, sum = 0
8260 00:40:38.094128 5, 0xFFFF, sum = 0
8261 00:40:38.096979 6, 0xFFFF, sum = 0
8262 00:40:38.097440 7, 0xFFFF, sum = 0
8263 00:40:38.100012 8, 0xFFFF, sum = 0
8264 00:40:38.100407 9, 0xFFFF, sum = 0
8265 00:40:38.103588 10, 0xFFFF, sum = 0
8266 00:40:38.103981 11, 0xFFFF, sum = 0
8267 00:40:38.106756 12, 0xF7F, sum = 0
8268 00:40:38.107201 13, 0x0, sum = 1
8269 00:40:38.109806 14, 0x0, sum = 2
8270 00:40:38.110202 15, 0x0, sum = 3
8271 00:40:38.113035 16, 0x0, sum = 4
8272 00:40:38.113477 best_step = 14
8273 00:40:38.113782
8274 00:40:38.114061 ==
8275 00:40:38.116499 Dram Type= 6, Freq= 0, CH_1, rank 0
8276 00:40:38.119580 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8277 00:40:38.123446 ==
8278 00:40:38.123834 RX Vref Scan: 1
8279 00:40:38.124137
8280 00:40:38.126466 Set Vref Range= 24 -> 127
8281 00:40:38.126851
8282 00:40:38.129634 RX Vref 24 -> 127, step: 1
8283 00:40:38.130072
8284 00:40:38.130437 RX Delay 3 -> 252, step: 4
8285 00:40:38.130727
8286 00:40:38.133303 Set Vref, RX VrefLevel [Byte0]: 24
8287 00:40:38.136471 [Byte1]: 24
8288 00:40:38.139953
8289 00:40:38.140335 Set Vref, RX VrefLevel [Byte0]: 25
8290 00:40:38.143391 [Byte1]: 25
8291 00:40:38.147776
8292 00:40:38.148161 Set Vref, RX VrefLevel [Byte0]: 26
8293 00:40:38.151263 [Byte1]: 26
8294 00:40:38.155694
8295 00:40:38.156224 Set Vref, RX VrefLevel [Byte0]: 27
8296 00:40:38.158834 [Byte1]: 27
8297 00:40:38.163009
8298 00:40:38.163475 Set Vref, RX VrefLevel [Byte0]: 28
8299 00:40:38.166467 [Byte1]: 28
8300 00:40:38.170739
8301 00:40:38.171140 Set Vref, RX VrefLevel [Byte0]: 29
8302 00:40:38.174130 [Byte1]: 29
8303 00:40:38.178442
8304 00:40:38.178844 Set Vref, RX VrefLevel [Byte0]: 30
8305 00:40:38.182287 [Byte1]: 30
8306 00:40:38.186193
8307 00:40:38.186614 Set Vref, RX VrefLevel [Byte0]: 31
8308 00:40:38.189397 [Byte1]: 31
8309 00:40:38.193772
8310 00:40:38.194158 Set Vref, RX VrefLevel [Byte0]: 32
8311 00:40:38.197041 [Byte1]: 32
8312 00:40:38.201712
8313 00:40:38.202144 Set Vref, RX VrefLevel [Byte0]: 33
8314 00:40:38.204809 [Byte1]: 33
8315 00:40:38.209384
8316 00:40:38.209853 Set Vref, RX VrefLevel [Byte0]: 34
8317 00:40:38.212991 [Byte1]: 34
8318 00:40:38.217250
8319 00:40:38.217723 Set Vref, RX VrefLevel [Byte0]: 35
8320 00:40:38.219887 [Byte1]: 35
8321 00:40:38.224715
8322 00:40:38.225102 Set Vref, RX VrefLevel [Byte0]: 36
8323 00:40:38.228092 [Byte1]: 36
8324 00:40:38.232014
8325 00:40:38.232465 Set Vref, RX VrefLevel [Byte0]: 37
8326 00:40:38.235337 [Byte1]: 37
8327 00:40:38.239732
8328 00:40:38.240122 Set Vref, RX VrefLevel [Byte0]: 38
8329 00:40:38.243104 [Byte1]: 38
8330 00:40:38.247473
8331 00:40:38.247854 Set Vref, RX VrefLevel [Byte0]: 39
8332 00:40:38.250756 [Byte1]: 39
8333 00:40:38.254778
8334 00:40:38.255181 Set Vref, RX VrefLevel [Byte0]: 40
8335 00:40:38.258055 [Byte1]: 40
8336 00:40:38.262817
8337 00:40:38.263263 Set Vref, RX VrefLevel [Byte0]: 41
8338 00:40:38.265927 [Byte1]: 41
8339 00:40:38.270501
8340 00:40:38.270897 Set Vref, RX VrefLevel [Byte0]: 42
8341 00:40:38.273723 [Byte1]: 42
8342 00:40:38.277803
8343 00:40:38.278186 Set Vref, RX VrefLevel [Byte0]: 43
8344 00:40:38.281433 [Byte1]: 43
8345 00:40:38.285803
8346 00:40:38.286247 Set Vref, RX VrefLevel [Byte0]: 44
8347 00:40:38.289000 [Byte1]: 44
8348 00:40:38.293304
8349 00:40:38.293683 Set Vref, RX VrefLevel [Byte0]: 45
8350 00:40:38.296397 [Byte1]: 45
8351 00:40:38.301037
8352 00:40:38.301419 Set Vref, RX VrefLevel [Byte0]: 46
8353 00:40:38.304462 [Byte1]: 46
8354 00:40:38.308859
8355 00:40:38.309320 Set Vref, RX VrefLevel [Byte0]: 47
8356 00:40:38.312213 [Byte1]: 47
8357 00:40:38.316586
8358 00:40:38.317139 Set Vref, RX VrefLevel [Byte0]: 48
8359 00:40:38.319787 [Byte1]: 48
8360 00:40:38.323707
8361 00:40:38.324386 Set Vref, RX VrefLevel [Byte0]: 49
8362 00:40:38.327449 [Byte1]: 49
8363 00:40:38.331457
8364 00:40:38.331838 Set Vref, RX VrefLevel [Byte0]: 50
8365 00:40:38.334965 [Byte1]: 50
8366 00:40:38.339203
8367 00:40:38.339583 Set Vref, RX VrefLevel [Byte0]: 51
8368 00:40:38.343174 [Byte1]: 51
8369 00:40:38.346773
8370 00:40:38.347156 Set Vref, RX VrefLevel [Byte0]: 52
8371 00:40:38.350373 [Byte1]: 52
8372 00:40:38.354685
8373 00:40:38.355063 Set Vref, RX VrefLevel [Byte0]: 53
8374 00:40:38.357511 [Byte1]: 53
8375 00:40:38.362271
8376 00:40:38.362664 Set Vref, RX VrefLevel [Byte0]: 54
8377 00:40:38.365462 [Byte1]: 54
8378 00:40:38.369543
8379 00:40:38.369924 Set Vref, RX VrefLevel [Byte0]: 55
8380 00:40:38.372993 [Byte1]: 55
8381 00:40:38.377304
8382 00:40:38.377684 Set Vref, RX VrefLevel [Byte0]: 56
8383 00:40:38.380782 [Byte1]: 56
8384 00:40:38.385088
8385 00:40:38.385478 Set Vref, RX VrefLevel [Byte0]: 57
8386 00:40:38.388312 [Byte1]: 57
8387 00:40:38.393056
8388 00:40:38.393460 Set Vref, RX VrefLevel [Byte0]: 58
8389 00:40:38.395963 [Byte1]: 58
8390 00:40:38.400492
8391 00:40:38.400972 Set Vref, RX VrefLevel [Byte0]: 59
8392 00:40:38.406908 [Byte1]: 59
8393 00:40:38.407439
8394 00:40:38.410052 Set Vref, RX VrefLevel [Byte0]: 60
8395 00:40:38.413288 [Byte1]: 60
8396 00:40:38.413673
8397 00:40:38.416811 Set Vref, RX VrefLevel [Byte0]: 61
8398 00:40:38.420063 [Byte1]: 61
8399 00:40:38.423449
8400 00:40:38.423856 Set Vref, RX VrefLevel [Byte0]: 62
8401 00:40:38.426712 [Byte1]: 62
8402 00:40:38.431434
8403 00:40:38.431815 Set Vref, RX VrefLevel [Byte0]: 63
8404 00:40:38.434139 [Byte1]: 63
8405 00:40:38.438679
8406 00:40:38.439167 Set Vref, RX VrefLevel [Byte0]: 64
8407 00:40:38.441787 [Byte1]: 64
8408 00:40:38.446323
8409 00:40:38.446706 Set Vref, RX VrefLevel [Byte0]: 65
8410 00:40:38.449615 [Byte1]: 65
8411 00:40:38.454005
8412 00:40:38.454474 Set Vref, RX VrefLevel [Byte0]: 66
8413 00:40:38.457337 [Byte1]: 66
8414 00:40:38.461793
8415 00:40:38.462178 Set Vref, RX VrefLevel [Byte0]: 67
8416 00:40:38.464828 [Byte1]: 67
8417 00:40:38.469299
8418 00:40:38.469684 Set Vref, RX VrefLevel [Byte0]: 68
8419 00:40:38.472532 [Byte1]: 68
8420 00:40:38.476866
8421 00:40:38.477252 Set Vref, RX VrefLevel [Byte0]: 69
8422 00:40:38.480162 [Byte1]: 69
8423 00:40:38.484560
8424 00:40:38.484947 Set Vref, RX VrefLevel [Byte0]: 70
8425 00:40:38.487770 [Byte1]: 70
8426 00:40:38.492175
8427 00:40:38.492560 Set Vref, RX VrefLevel [Byte0]: 71
8428 00:40:38.495533 [Byte1]: 71
8429 00:40:38.500167
8430 00:40:38.500557 Set Vref, RX VrefLevel [Byte0]: 72
8431 00:40:38.503298 [Byte1]: 72
8432 00:40:38.507614
8433 00:40:38.508003 Set Vref, RX VrefLevel [Byte0]: 73
8434 00:40:38.510715 [Byte1]: 73
8435 00:40:38.515028
8436 00:40:38.515465 Set Vref, RX VrefLevel [Byte0]: 74
8437 00:40:38.518342 [Byte1]: 74
8438 00:40:38.522886
8439 00:40:38.523271 Set Vref, RX VrefLevel [Byte0]: 75
8440 00:40:38.526388 [Byte1]: 75
8441 00:40:38.530669
8442 00:40:38.531059 Set Vref, RX VrefLevel [Byte0]: 76
8443 00:40:38.533810 [Byte1]: 76
8444 00:40:38.538018
8445 00:40:38.538453 Final RX Vref Byte 0 = 59 to rank0
8446 00:40:38.541595 Final RX Vref Byte 1 = 58 to rank0
8447 00:40:38.544924 Final RX Vref Byte 0 = 59 to rank1
8448 00:40:38.548103 Final RX Vref Byte 1 = 58 to rank1==
8449 00:40:38.551203 Dram Type= 6, Freq= 0, CH_1, rank 0
8450 00:40:38.558125 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8451 00:40:38.558556 ==
8452 00:40:38.558866 DQS Delay:
8453 00:40:38.559149 DQS0 = 0, DQS1 = 0
8454 00:40:38.561110 DQM Delay:
8455 00:40:38.561496 DQM0 = 129, DQM1 = 123
8456 00:40:38.564918 DQ Delay:
8457 00:40:38.568051 DQ0 =132, DQ1 =124, DQ2 =118, DQ3 =126
8458 00:40:38.571764 DQ4 =130, DQ5 =142, DQ6 =138, DQ7 =126
8459 00:40:38.574908 DQ8 =106, DQ9 =114, DQ10 =126, DQ11 =110
8460 00:40:38.577655 DQ12 =132, DQ13 =134, DQ14 =132, DQ15 =132
8461 00:40:38.578042
8462 00:40:38.578371
8463 00:40:38.578650
8464 00:40:38.581326 [DramC_TX_OE_Calibration] TA2
8465 00:40:38.584409 Original DQ_B0 (3 6) =30, OEN = 27
8466 00:40:38.587703 Original DQ_B1 (3 6) =30, OEN = 27
8467 00:40:38.591002 24, 0x0, End_B0=24 End_B1=24
8468 00:40:38.591396 25, 0x0, End_B0=25 End_B1=25
8469 00:40:38.594638 26, 0x0, End_B0=26 End_B1=26
8470 00:40:38.597763 27, 0x0, End_B0=27 End_B1=27
8471 00:40:38.600933 28, 0x0, End_B0=28 End_B1=28
8472 00:40:38.604436 29, 0x0, End_B0=29 End_B1=29
8473 00:40:38.604911 30, 0x0, End_B0=30 End_B1=30
8474 00:40:38.607453 31, 0x4141, End_B0=30 End_B1=30
8475 00:40:38.611141 Byte0 end_step=30 best_step=27
8476 00:40:38.614453 Byte1 end_step=30 best_step=27
8477 00:40:38.618042 Byte0 TX OE(2T, 0.5T) = (3, 3)
8478 00:40:38.620885 Byte1 TX OE(2T, 0.5T) = (3, 3)
8479 00:40:38.621347
8480 00:40:38.621658
8481 00:40:38.627697 [DQSOSCAuto] RK0, (LSB)MR18= 0x2d2d, (MSB)MR19= 0x303, tDQSOscB0 = 387 ps tDQSOscB1 = 387 ps
8482 00:40:38.631074 CH1 RK0: MR19=303, MR18=2D2D
8483 00:40:38.637360 CH1_RK0: MR19=0x303, MR18=0x2D2D, DQSOSC=387, MR23=63, INC=24, DEC=16
8484 00:40:38.637801
8485 00:40:38.641130 ----->DramcWriteLeveling(PI) begin...
8486 00:40:38.641525 ==
8487 00:40:38.644174 Dram Type= 6, Freq= 0, CH_1, rank 1
8488 00:40:38.647602 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8489 00:40:38.648043 ==
8490 00:40:38.650744 Write leveling (Byte 0): 20 => 20
8491 00:40:38.654305 Write leveling (Byte 1): 20 => 20
8492 00:40:38.657299 DramcWriteLeveling(PI) end<-----
8493 00:40:38.657687
8494 00:40:38.657992 ==
8495 00:40:38.660718 Dram Type= 6, Freq= 0, CH_1, rank 1
8496 00:40:38.663821 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8497 00:40:38.664270 ==
8498 00:40:38.667452 [Gating] SW mode calibration
8499 00:40:38.674300 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8500 00:40:38.680826 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8501 00:40:38.684548 0 12 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
8502 00:40:38.687379 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8503 00:40:38.694062 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8504 00:40:38.697385 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8505 00:40:38.700660 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8506 00:40:38.707332 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8507 00:40:38.710839 0 12 24 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
8508 00:40:38.714149 0 12 28 | B1->B0 | 3333 2323 | 1 0 | (0 1) (0 0)
8509 00:40:38.721197 0 13 0 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
8510 00:40:38.724197 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8511 00:40:38.727413 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8512 00:40:38.733751 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8513 00:40:38.737337 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8514 00:40:38.740664 0 13 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8515 00:40:38.747396 0 13 24 | B1->B0 | 2323 4141 | 0 0 | (0 0) (0 0)
8516 00:40:38.750388 0 13 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8517 00:40:38.753815 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8518 00:40:38.760480 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8519 00:40:38.763852 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8520 00:40:38.767210 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8521 00:40:38.773781 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8522 00:40:38.777230 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8523 00:40:38.780742 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8524 00:40:38.786895 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8525 00:40:38.790664 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8526 00:40:38.793596 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8527 00:40:38.800339 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8528 00:40:38.803961 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8529 00:40:38.807210 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8530 00:40:38.814014 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8531 00:40:38.817165 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8532 00:40:38.820411 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8533 00:40:38.826962 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8534 00:40:38.830447 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8535 00:40:38.833730 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8536 00:40:38.837076 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8537 00:40:38.843824 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8538 00:40:38.846711 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8539 00:40:38.849911 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8540 00:40:38.856731 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8541 00:40:38.860055 Total UI for P1: 0, mck2ui 16
8542 00:40:38.863074 best dqsien dly found for B0: ( 1, 0, 24)
8543 00:40:38.866526 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8544 00:40:38.870300 Total UI for P1: 0, mck2ui 16
8545 00:40:38.873556 best dqsien dly found for B1: ( 1, 0, 28)
8546 00:40:38.876346 best DQS0 dly(MCK, UI, PI) = (1, 0, 24)
8547 00:40:38.879951 best DQS1 dly(MCK, UI, PI) = (1, 0, 28)
8548 00:40:38.880338
8549 00:40:38.883219 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 24)
8550 00:40:38.889827 best DQS1 P1 dly(MCK, UI, PI) = (1, 4, 28)
8551 00:40:38.890249 [Gating] SW calibration Done
8552 00:40:38.890564 ==
8553 00:40:38.893053 Dram Type= 6, Freq= 0, CH_1, rank 1
8554 00:40:38.899625 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8555 00:40:38.900058 ==
8556 00:40:38.900364 RX Vref Scan: 0
8557 00:40:38.900645
8558 00:40:38.903317 RX Vref 0 -> 0, step: 1
8559 00:40:38.903742
8560 00:40:38.906330 RX Delay 0 -> 252, step: 8
8561 00:40:38.910013 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8562 00:40:38.913703 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8563 00:40:38.916293 iDelay=200, Bit 2, Center 115 (56 ~ 175) 120
8564 00:40:38.920477 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8565 00:40:38.926381 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8566 00:40:38.930023 iDelay=200, Bit 5, Center 139 (80 ~ 199) 120
8567 00:40:38.933116 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8568 00:40:38.936139 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8569 00:40:38.939726 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8570 00:40:38.946478 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8571 00:40:38.949466 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8572 00:40:38.953171 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8573 00:40:38.956142 iDelay=200, Bit 12, Center 135 (72 ~ 199) 128
8574 00:40:38.959670 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8575 00:40:38.965979 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8576 00:40:38.969939 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8577 00:40:38.970451 ==
8578 00:40:38.972616 Dram Type= 6, Freq= 0, CH_1, rank 1
8579 00:40:38.976311 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8580 00:40:38.976590 ==
8581 00:40:38.979157 DQS Delay:
8582 00:40:38.979433 DQS0 = 0, DQS1 = 0
8583 00:40:38.979658 DQM Delay:
8584 00:40:38.982575 DQM0 = 130, DQM1 = 124
8585 00:40:38.982781 DQ Delay:
8586 00:40:38.985910 DQ0 =131, DQ1 =127, DQ2 =115, DQ3 =131
8587 00:40:38.989522 DQ4 =131, DQ5 =139, DQ6 =139, DQ7 =131
8588 00:40:38.996175 DQ8 =107, DQ9 =111, DQ10 =123, DQ11 =115
8589 00:40:38.999017 DQ12 =135, DQ13 =139, DQ14 =131, DQ15 =131
8590 00:40:38.999225
8591 00:40:38.999386
8592 00:40:38.999538 ==
8593 00:40:39.002263 Dram Type= 6, Freq= 0, CH_1, rank 1
8594 00:40:39.005620 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8595 00:40:39.005890 ==
8596 00:40:39.006108
8597 00:40:39.006351
8598 00:40:39.008976 TX Vref Scan disable
8599 00:40:39.012319 == TX Byte 0 ==
8600 00:40:39.015817 Update DQ dly =974 (3 ,6, 14) DQ OEN =(3 ,3)
8601 00:40:39.019215 Update DQM dly =974 (3 ,6, 14) DQM OEN =(3 ,3)
8602 00:40:39.022682 == TX Byte 1 ==
8603 00:40:39.025745 Update DQ dly =974 (3 ,6, 14) DQ OEN =(3 ,3)
8604 00:40:39.029145 Update DQM dly =974 (3 ,6, 14) DQM OEN =(3 ,3)
8605 00:40:39.029643 ==
8606 00:40:39.032783 Dram Type= 6, Freq= 0, CH_1, rank 1
8607 00:40:39.035895 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8608 00:40:39.038880 ==
8609 00:40:39.050535
8610 00:40:39.054039 TX Vref early break, caculate TX vref
8611 00:40:39.057925 TX Vref=16, minBit 7, minWin=22, winSum=386
8612 00:40:39.060568 TX Vref=18, minBit 1, minWin=23, winSum=388
8613 00:40:39.063802 TX Vref=20, minBit 1, minWin=24, winSum=402
8614 00:40:39.067364 TX Vref=22, minBit 1, minWin=24, winSum=410
8615 00:40:39.070676 TX Vref=24, minBit 3, minWin=24, winSum=413
8616 00:40:39.077076 TX Vref=26, minBit 3, minWin=24, winSum=419
8617 00:40:39.080305 TX Vref=28, minBit 1, minWin=25, winSum=422
8618 00:40:39.084061 TX Vref=30, minBit 13, minWin=25, winSum=422
8619 00:40:39.087162 TX Vref=32, minBit 1, minWin=24, winSum=417
8620 00:40:39.090289 TX Vref=34, minBit 0, minWin=24, winSum=406
8621 00:40:39.094272 TX Vref=36, minBit 3, minWin=23, winSum=398
8622 00:40:39.100350 [TxChooseVref] Worse bit 1, Min win 25, Win sum 422, Final Vref 28
8623 00:40:39.100695
8624 00:40:39.103417 Final TX Range 0 Vref 28
8625 00:40:39.103648
8626 00:40:39.103824 ==
8627 00:40:39.106716 Dram Type= 6, Freq= 0, CH_1, rank 1
8628 00:40:39.110562 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8629 00:40:39.110752 ==
8630 00:40:39.110893
8631 00:40:39.111020
8632 00:40:39.113499 TX Vref Scan disable
8633 00:40:39.120094 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8634 00:40:39.120250 == TX Byte 0 ==
8635 00:40:39.123648 u2DelayCellOfst[0]=14 cells (4 PI)
8636 00:40:39.126654 u2DelayCellOfst[1]=7 cells (2 PI)
8637 00:40:39.129560 u2DelayCellOfst[2]=0 cells (0 PI)
8638 00:40:39.132955 u2DelayCellOfst[3]=3 cells (1 PI)
8639 00:40:39.136412 u2DelayCellOfst[4]=7 cells (2 PI)
8640 00:40:39.140286 u2DelayCellOfst[5]=14 cells (4 PI)
8641 00:40:39.143287 u2DelayCellOfst[6]=14 cells (4 PI)
8642 00:40:39.146601 u2DelayCellOfst[7]=3 cells (1 PI)
8643 00:40:39.150308 Update DQ dly =972 (3 ,6, 12) DQ OEN =(3 ,3)
8644 00:40:39.153216 Update DQM dly =974 (3 ,6, 14) DQM OEN =(3 ,3)
8645 00:40:39.156680 == TX Byte 1 ==
8646 00:40:39.160328 u2DelayCellOfst[8]=0 cells (0 PI)
8647 00:40:39.160709 u2DelayCellOfst[9]=3 cells (1 PI)
8648 00:40:39.162954 u2DelayCellOfst[10]=7 cells (2 PI)
8649 00:40:39.166675 u2DelayCellOfst[11]=3 cells (1 PI)
8650 00:40:39.170030 u2DelayCellOfst[12]=14 cells (4 PI)
8651 00:40:39.173252 u2DelayCellOfst[13]=18 cells (5 PI)
8652 00:40:39.176472 u2DelayCellOfst[14]=18 cells (5 PI)
8653 00:40:39.179809 u2DelayCellOfst[15]=18 cells (5 PI)
8654 00:40:39.183088 Update DQ dly =972 (3 ,6, 12) DQ OEN =(3 ,3)
8655 00:40:39.190000 Update DQM dly =974 (3 ,6, 14) DQM OEN =(3 ,3)
8656 00:40:39.190550 DramC Write-DBI on
8657 00:40:39.190895 ==
8658 00:40:39.193079 Dram Type= 6, Freq= 0, CH_1, rank 1
8659 00:40:39.199637 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8660 00:40:39.200029 ==
8661 00:40:39.200329
8662 00:40:39.200603
8663 00:40:39.200866 TX Vref Scan disable
8664 00:40:39.203215 == TX Byte 0 ==
8665 00:40:39.206933 Update DQM dly =716 (2 ,6, 12) DQM OEN =(3 ,3)
8666 00:40:39.210608 == TX Byte 1 ==
8667 00:40:39.213496 Update DQM dly =715 (2 ,6, 11) DQM OEN =(3 ,3)
8668 00:40:39.216664 DramC Write-DBI off
8669 00:40:39.217051
8670 00:40:39.217355 [DATLAT]
8671 00:40:39.217634 Freq=1600, CH1 RK1
8672 00:40:39.217906
8673 00:40:39.220213 DATLAT Default: 0xe
8674 00:40:39.220599 0, 0xFFFF, sum = 0
8675 00:40:39.223189 1, 0xFFFF, sum = 0
8676 00:40:39.226881 2, 0xFFFF, sum = 0
8677 00:40:39.227344 3, 0xFFFF, sum = 0
8678 00:40:39.230134 4, 0xFFFF, sum = 0
8679 00:40:39.230548 5, 0xFFFF, sum = 0
8680 00:40:39.233612 6, 0xFFFF, sum = 0
8681 00:40:39.234006 7, 0xFFFF, sum = 0
8682 00:40:39.236539 8, 0xFFFF, sum = 0
8683 00:40:39.236931 9, 0xFFFF, sum = 0
8684 00:40:39.240120 10, 0xFFFF, sum = 0
8685 00:40:39.240517 11, 0xFFFF, sum = 0
8686 00:40:39.243121 12, 0x8F7F, sum = 0
8687 00:40:39.243515 13, 0x0, sum = 1
8688 00:40:39.246530 14, 0x0, sum = 2
8689 00:40:39.247067 15, 0x0, sum = 3
8690 00:40:39.249984 16, 0x0, sum = 4
8691 00:40:39.250588 best_step = 14
8692 00:40:39.251086
8693 00:40:39.251536 ==
8694 00:40:39.253454 Dram Type= 6, Freq= 0, CH_1, rank 1
8695 00:40:39.256974 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8696 00:40:39.259578 ==
8697 00:40:39.259856 RX Vref Scan: 0
8698 00:40:39.260073
8699 00:40:39.262988 RX Vref 0 -> 0, step: 1
8700 00:40:39.263200
8701 00:40:39.263366 RX Delay 3 -> 252, step: 4
8702 00:40:39.270308 iDelay=195, Bit 0, Center 128 (75 ~ 182) 108
8703 00:40:39.273396 iDelay=195, Bit 1, Center 124 (71 ~ 178) 108
8704 00:40:39.276877 iDelay=195, Bit 2, Center 118 (67 ~ 170) 104
8705 00:40:39.279951 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
8706 00:40:39.283625 iDelay=195, Bit 4, Center 126 (71 ~ 182) 112
8707 00:40:39.290077 iDelay=195, Bit 5, Center 138 (83 ~ 194) 112
8708 00:40:39.293618 iDelay=195, Bit 6, Center 136 (83 ~ 190) 108
8709 00:40:39.296641 iDelay=195, Bit 7, Center 126 (71 ~ 182) 112
8710 00:40:39.299834 iDelay=195, Bit 8, Center 104 (47 ~ 162) 116
8711 00:40:39.303053 iDelay=195, Bit 9, Center 108 (55 ~ 162) 108
8712 00:40:39.309698 iDelay=195, Bit 10, Center 122 (67 ~ 178) 112
8713 00:40:39.313320 iDelay=195, Bit 11, Center 114 (59 ~ 170) 112
8714 00:40:39.316343 iDelay=195, Bit 12, Center 132 (75 ~ 190) 116
8715 00:40:39.319648 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8716 00:40:39.326152 iDelay=195, Bit 14, Center 134 (79 ~ 190) 112
8717 00:40:39.329636 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8718 00:40:39.329715 ==
8719 00:40:39.332879 Dram Type= 6, Freq= 0, CH_1, rank 1
8720 00:40:39.336696 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8721 00:40:39.336783 ==
8722 00:40:39.339525 DQS Delay:
8723 00:40:39.339607 DQS0 = 0, DQS1 = 0
8724 00:40:39.339667 DQM Delay:
8725 00:40:39.343441 DQM0 = 127, DQM1 = 122
8726 00:40:39.343582 DQ Delay:
8727 00:40:39.346455 DQ0 =128, DQ1 =124, DQ2 =118, DQ3 =124
8728 00:40:39.349743 DQ4 =126, DQ5 =138, DQ6 =136, DQ7 =126
8729 00:40:39.352649 DQ8 =104, DQ9 =108, DQ10 =122, DQ11 =114
8730 00:40:39.359543 DQ12 =132, DQ13 =132, DQ14 =134, DQ15 =132
8731 00:40:39.359621
8732 00:40:39.359681
8733 00:40:39.359735
8734 00:40:39.362377 [DramC_TX_OE_Calibration] TA2
8735 00:40:39.366176 Original DQ_B0 (3 6) =30, OEN = 27
8736 00:40:39.366268 Original DQ_B1 (3 6) =30, OEN = 27
8737 00:40:39.369374 24, 0x0, End_B0=24 End_B1=24
8738 00:40:39.372861 25, 0x0, End_B0=25 End_B1=25
8739 00:40:39.375946 26, 0x0, End_B0=26 End_B1=26
8740 00:40:39.379580 27, 0x0, End_B0=27 End_B1=27
8741 00:40:39.379669 28, 0x0, End_B0=28 End_B1=28
8742 00:40:39.382837 29, 0x0, End_B0=29 End_B1=29
8743 00:40:39.386118 30, 0x0, End_B0=30 End_B1=30
8744 00:40:39.389432 31, 0x4141, End_B0=30 End_B1=30
8745 00:40:39.392701 Byte0 end_step=30 best_step=27
8746 00:40:39.392886 Byte1 end_step=30 best_step=27
8747 00:40:39.396338 Byte0 TX OE(2T, 0.5T) = (3, 3)
8748 00:40:39.399234 Byte1 TX OE(2T, 0.5T) = (3, 3)
8749 00:40:39.399363
8750 00:40:39.399462
8751 00:40:39.409754 [DQSOSCAuto] RK1, (LSB)MR18= 0x1e1e, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 394 ps
8752 00:40:39.410152 CH1 RK1: MR19=303, MR18=1E1E
8753 00:40:39.416096 CH1_RK1: MR19=0x303, MR18=0x1E1E, DQSOSC=394, MR23=63, INC=23, DEC=15
8754 00:40:39.419522 [RxdqsGatingPostProcess] freq 1600
8755 00:40:39.426038 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
8756 00:40:39.429701 Pre-setting of DQS Precalculation
8757 00:40:39.433204 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
8758 00:40:39.442848 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
8759 00:40:39.449233 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8760 00:40:39.449721
8761 00:40:39.450059
8762 00:40:39.452936 [Calibration Summary] 3200 Mbps
8763 00:40:39.453417 CH 0, Rank 0
8764 00:40:39.456197 SW Impedance : PASS
8765 00:40:39.456628 DUTY Scan : NO K
8766 00:40:39.459708 ZQ Calibration : PASS
8767 00:40:39.462996 Jitter Meter : NO K
8768 00:40:39.463503 CBT Training : PASS
8769 00:40:39.466209 Write leveling : PASS
8770 00:40:39.469577 RX DQS gating : PASS
8771 00:40:39.470089 RX DQ/DQS(RDDQC) : PASS
8772 00:40:39.473017 TX DQ/DQS : PASS
8773 00:40:39.473503 RX DATLAT : PASS
8774 00:40:39.476032 RX DQ/DQS(Engine): PASS
8775 00:40:39.479088 TX OE : PASS
8776 00:40:39.479638 All Pass.
8777 00:40:39.479993
8778 00:40:39.480308 CH 0, Rank 1
8779 00:40:39.482685 SW Impedance : PASS
8780 00:40:39.485794 DUTY Scan : NO K
8781 00:40:39.486536 ZQ Calibration : PASS
8782 00:40:39.489788 Jitter Meter : NO K
8783 00:40:39.492611 CBT Training : PASS
8784 00:40:39.492999 Write leveling : PASS
8785 00:40:39.495858 RX DQS gating : PASS
8786 00:40:39.499614 RX DQ/DQS(RDDQC) : PASS
8787 00:40:39.500223 TX DQ/DQS : PASS
8788 00:40:39.503091 RX DATLAT : PASS
8789 00:40:39.506306 RX DQ/DQS(Engine): PASS
8790 00:40:39.506928 TX OE : PASS
8791 00:40:39.508962 All Pass.
8792 00:40:39.509547
8793 00:40:39.510035 CH 1, Rank 0
8794 00:40:39.512425 SW Impedance : PASS
8795 00:40:39.512933 DUTY Scan : NO K
8796 00:40:39.515668 ZQ Calibration : PASS
8797 00:40:39.519500 Jitter Meter : NO K
8798 00:40:39.519948 CBT Training : PASS
8799 00:40:39.522460 Write leveling : PASS
8800 00:40:39.525924 RX DQS gating : PASS
8801 00:40:39.526451 RX DQ/DQS(RDDQC) : PASS
8802 00:40:39.528800 TX DQ/DQS : PASS
8803 00:40:39.529192 RX DATLAT : PASS
8804 00:40:39.532187 RX DQ/DQS(Engine): PASS
8805 00:40:39.535880 TX OE : PASS
8806 00:40:39.536270 All Pass.
8807 00:40:39.536573
8808 00:40:39.536856 CH 1, Rank 1
8809 00:40:39.539251 SW Impedance : PASS
8810 00:40:39.542192 DUTY Scan : NO K
8811 00:40:39.542865 ZQ Calibration : PASS
8812 00:40:39.545860 Jitter Meter : NO K
8813 00:40:39.549008 CBT Training : PASS
8814 00:40:39.549395 Write leveling : PASS
8815 00:40:39.552219 RX DQS gating : PASS
8816 00:40:39.555531 RX DQ/DQS(RDDQC) : PASS
8817 00:40:39.555917 TX DQ/DQS : PASS
8818 00:40:39.558721 RX DATLAT : PASS
8819 00:40:39.561973 RX DQ/DQS(Engine): PASS
8820 00:40:39.562441 TX OE : PASS
8821 00:40:39.565581 All Pass.
8822 00:40:39.565967
8823 00:40:39.566321 DramC Write-DBI on
8824 00:40:39.568757 PER_BANK_REFRESH: Hybrid Mode
8825 00:40:39.569327 TX_TRACKING: ON
8826 00:40:39.578852 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
8827 00:40:39.588557 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
8828 00:40:39.595151 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8829 00:40:39.598529 [FAST_K] Save calibration result to emmc
8830 00:40:39.601890 sync common calibartion params.
8831 00:40:39.602417 sync cbt_mode0:0, 1:0
8832 00:40:39.605467 dram_init: ddr_geometry: 0
8833 00:40:39.608437 dram_init: ddr_geometry: 0
8834 00:40:39.608824 dram_init: ddr_geometry: 0
8835 00:40:39.611986 0:dram_rank_size:80000000
8836 00:40:39.614999 1:dram_rank_size:80000000
8837 00:40:39.618405 sync rank num:2, rank0_size:0x80000000, rank1_size:0x80000000
8838 00:40:39.621825 DFS_SHUFFLE_HW_MODE: ON
8839 00:40:39.624858 dramc_set_vcore_voltage set vcore to 725000
8840 00:40:39.628593 Read voltage for 1600, 0
8841 00:40:39.629072 Vio18 = 0
8842 00:40:39.632385 Vcore = 725000
8843 00:40:39.632854 Vdram = 0
8844 00:40:39.633168 Vddq = 0
8845 00:40:39.635079 Vmddr = 0
8846 00:40:39.635465 switch to 3200 Mbps bootup
8847 00:40:39.638182 [DramcRunTimeConfig]
8848 00:40:39.638881 PHYPLL
8849 00:40:39.641473 DPM_CONTROL_AFTERK: ON
8850 00:40:39.641858 PER_BANK_REFRESH: ON
8851 00:40:39.644820 REFRESH_OVERHEAD_REDUCTION: ON
8852 00:40:39.648593 CMD_PICG_NEW_MODE: OFF
8853 00:40:39.649068 XRTWTW_NEW_MODE: ON
8854 00:40:39.651297 XRTRTR_NEW_MODE: ON
8855 00:40:39.651684 TX_TRACKING: ON
8856 00:40:39.654738 RDSEL_TRACKING: OFF
8857 00:40:39.658192 DQS Precalculation for DVFS: ON
8858 00:40:39.658626 RX_TRACKING: OFF
8859 00:40:39.661433 HW_GATING DBG: ON
8860 00:40:39.661821 ZQCS_ENABLE_LP4: ON
8861 00:40:39.664806 RX_PICG_NEW_MODE: ON
8862 00:40:39.665194 TX_PICG_NEW_MODE: ON
8863 00:40:39.668389 ENABLE_RX_DCM_DPHY: ON
8864 00:40:39.671709 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
8865 00:40:39.674560 DUMMY_READ_FOR_TRACKING: OFF
8866 00:40:39.674949 !!! SPM_CONTROL_AFTERK: OFF
8867 00:40:39.677883 !!! SPM could not control APHY
8868 00:40:39.681357 IMPEDANCE_TRACKING: ON
8869 00:40:39.681738 TEMP_SENSOR: ON
8870 00:40:39.684814 HW_SAVE_FOR_SR: OFF
8871 00:40:39.688104 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
8872 00:40:39.691166 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
8873 00:40:39.691552 Read ODT Tracking: ON
8874 00:40:39.694298 Refresh Rate DeBounce: ON
8875 00:40:39.698078 DFS_NO_QUEUE_FLUSH: ON
8876 00:40:39.701173 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
8877 00:40:39.701558 ENABLE_DFS_RUNTIME_MRW: OFF
8878 00:40:39.704479 DDR_RESERVE_NEW_MODE: ON
8879 00:40:39.708182 MR_CBT_SWITCH_FREQ: ON
8880 00:40:39.708649 =========================
8881 00:40:39.728099 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
8882 00:40:39.731200 dram_init: ddr_geometry: 0
8883 00:40:39.749795 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
8884 00:40:39.753180 dram_init: dram init end (result: 0)
8885 00:40:39.760026 DRAM-K: Full calibration passed in 23374 msecs
8886 00:40:39.763113 MRC: failed to locate region type 0.
8887 00:40:39.763547 DRAM rank0 size:0x80000000,
8888 00:40:39.766061 DRAM rank1 size=0x80000000
8889 00:40:39.776181 Mapping address range [0x40000000:0x140000000) as cacheable | read-write | non-secure | normal
8890 00:40:39.782824 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
8891 00:40:39.789834 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
8892 00:40:39.795893 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
8893 00:40:39.799109 DRAM rank0 size:0x80000000,
8894 00:40:39.802337 DRAM rank1 size=0x80000000
8895 00:40:39.802767 CBMEM:
8896 00:40:39.805628 IMD: root @ 0xfffff000 254 entries.
8897 00:40:39.809235 IMD: root @ 0xffffec00 62 entries.
8898 00:40:39.812717 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
8899 00:40:39.815795 WARNING: RO_VPD is uninitialized or empty.
8900 00:40:39.821999 FMAP: area RW_VPD found @ 577000 (16384 bytes)
8901 00:40:39.829179 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
8902 00:40:39.841765 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
8903 00:40:39.853183 BS: romstage times (exec / console): total (unknown) / 22914 ms
8904 00:40:39.853695
8905 00:40:39.854035
8906 00:40:39.863648 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
8907 00:40:39.866466 ARM64: Exception handlers installed.
8908 00:40:39.869900 ARM64: Testing exception
8909 00:40:39.873066 ARM64: Done test exception
8910 00:40:39.873555 Enumerating buses...
8911 00:40:39.876401 Show all devs... Before device enumeration.
8912 00:40:39.879824 Root Device: enabled 1
8913 00:40:39.882915 CPU_CLUSTER: 0: enabled 1
8914 00:40:39.883303 CPU: 00: enabled 1
8915 00:40:39.886354 Compare with tree...
8916 00:40:39.886742 Root Device: enabled 1
8917 00:40:39.889747 CPU_CLUSTER: 0: enabled 1
8918 00:40:39.893081 CPU: 00: enabled 1
8919 00:40:39.893548 Root Device scanning...
8920 00:40:39.896383 scan_static_bus for Root Device
8921 00:40:39.899771 CPU_CLUSTER: 0 enabled
8922 00:40:39.903200 scan_static_bus for Root Device done
8923 00:40:39.906310 scan_bus: bus Root Device finished in 8 msecs
8924 00:40:39.906705 done
8925 00:40:39.913270 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
8926 00:40:39.916982 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
8927 00:40:39.923166 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
8928 00:40:39.926447 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
8929 00:40:39.929895 Allocating resources...
8930 00:40:39.933137 Reading resources...
8931 00:40:39.936125 Root Device read_resources bus 0 link: 0
8932 00:40:39.936562 DRAM rank0 size:0x80000000,
8933 00:40:39.939706 DRAM rank1 size=0x80000000
8934 00:40:39.942547 CPU_CLUSTER: 0 read_resources bus 0 link: 0
8935 00:40:39.946064 CPU: 00 missing read_resources
8936 00:40:39.950043 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
8937 00:40:39.956380 Root Device read_resources bus 0 link: 0 done
8938 00:40:39.956899 Done reading resources.
8939 00:40:39.962608 Show resources in subtree (Root Device)...After reading.
8940 00:40:39.966457 Root Device child on link 0 CPU_CLUSTER: 0
8941 00:40:39.969563 CPU_CLUSTER: 0 child on link 0 CPU: 00
8942 00:40:39.979351 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8943 00:40:39.979848 CPU: 00
8944 00:40:39.982867 Root Device assign_resources, bus 0 link: 0
8945 00:40:39.986044 CPU_CLUSTER: 0 missing set_resources
8946 00:40:39.989310 Root Device assign_resources, bus 0 link: 0 done
8947 00:40:39.993030 Done setting resources.
8948 00:40:39.999649 Show resources in subtree (Root Device)...After assigning values.
8949 00:40:40.002812 Root Device child on link 0 CPU_CLUSTER: 0
8950 00:40:40.006160 CPU_CLUSTER: 0 child on link 0 CPU: 00
8951 00:40:40.015794 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8952 00:40:40.016231 CPU: 00
8953 00:40:40.019133 Done allocating resources.
8954 00:40:40.022613 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
8955 00:40:40.026020 Enabling resources...
8956 00:40:40.026456 done.
8957 00:40:40.032907 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
8958 00:40:40.033297 Initializing devices...
8959 00:40:40.035971 Root Device init
8960 00:40:40.036358 init hardware done!
8961 00:40:40.039236 0x00000018: ctrlr->caps
8962 00:40:40.042748 52.000 MHz: ctrlr->f_max
8963 00:40:40.043142 0.400 MHz: ctrlr->f_min
8964 00:40:40.045726 0x40ff8080: ctrlr->voltages
8965 00:40:40.046121 sclk: 390625
8966 00:40:40.048932 Bus Width = 1
8967 00:40:40.049320 sclk: 390625
8968 00:40:40.049623 Bus Width = 1
8969 00:40:40.052683 Early init status = 3
8970 00:40:40.056601 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
8971 00:40:40.060415 in-header: 03 fc 00 00 01 00 00 00
8972 00:40:40.064159 in-data: 00
8973 00:40:40.067309 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
8974 00:40:40.071983 in-header: 03 fd 00 00 00 00 00 00
8975 00:40:40.075325 in-data:
8976 00:40:40.078418 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
8977 00:40:40.082673 in-header: 03 fc 00 00 01 00 00 00
8978 00:40:40.085712 in-data: 00
8979 00:40:40.088604 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
8980 00:40:40.093789 in-header: 03 fd 00 00 00 00 00 00
8981 00:40:40.097433 in-data:
8982 00:40:40.100520 [SSUSB] Setting up USB HOST controller...
8983 00:40:40.103993 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
8984 00:40:40.107099 [SSUSB] phy power-on done.
8985 00:40:40.110298 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
8986 00:40:40.117418 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
8987 00:40:40.120484 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
8988 00:40:40.126675 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
8989 00:40:40.133857 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
8990 00:40:40.140566 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
8991 00:40:40.147286 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
8992 00:40:40.153470 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
8993 00:40:40.156559 SPM: binary array size = 0x9dc
8994 00:40:40.160371 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
8995 00:40:40.167022 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
8996 00:40:40.173222 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
8997 00:40:40.179559 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
8998 00:40:40.183077 configure_display: Starting display init
8999 00:40:40.217069 anx7625_power_on_init: Init interface.
9000 00:40:40.220433 anx7625_disable_pd_protocol: Disabled PD feature.
9001 00:40:40.223571 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9002 00:40:40.251718 anx7625_start_dp_work: Secure OCM version=00
9003 00:40:40.254625 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9004 00:40:40.269707 sp_tx_get_edid_block: EDID Block = 1
9005 00:40:40.372011 Extracted contents:
9006 00:40:40.375347 header: 00 ff ff ff ff ff ff 00
9007 00:40:40.378608 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9008 00:40:40.381924 version: 01 04
9009 00:40:40.385353 basic params: 95 1f 11 78 0a
9010 00:40:40.388528 chroma info: 76 90 94 55 54 90 27 21 50 54
9011 00:40:40.392006 established: 00 00 00
9012 00:40:40.398499 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9013 00:40:40.401661 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9014 00:40:40.408201 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9015 00:40:40.415298 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9016 00:40:40.421916 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9017 00:40:40.425100 extensions: 00
9018 00:40:40.425488 checksum: fb
9019 00:40:40.425792
9020 00:40:40.428434 Manufacturer: IVO Model 57d Serial Number 0
9021 00:40:40.431831 Made week 0 of 2020
9022 00:40:40.432231 EDID version: 1.4
9023 00:40:40.435008 Digital display
9024 00:40:40.438392 6 bits per primary color channel
9025 00:40:40.438790 DisplayPort interface
9026 00:40:40.441628 Maximum image size: 31 cm x 17 cm
9027 00:40:40.444853 Gamma: 220%
9028 00:40:40.445243 Check DPMS levels
9029 00:40:40.448454 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9030 00:40:40.451638 First detailed timing is preferred timing
9031 00:40:40.454719 Established timings supported:
9032 00:40:40.458286 Standard timings supported:
9033 00:40:40.461302 Detailed timings
9034 00:40:40.464842 Hex of detail: 383680a07038204018303c0035ae10000019
9035 00:40:40.468145 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9036 00:40:40.474805 0780 0798 07c8 0820 hborder 0
9037 00:40:40.478308 0438 043b 0447 0458 vborder 0
9038 00:40:40.481596 -hsync -vsync
9039 00:40:40.482172 Did detailed timing
9040 00:40:40.488312 Hex of detail: 000000000000000000000000000000000000
9041 00:40:40.488708 Manufacturer-specified data, tag 0
9042 00:40:40.494493 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9043 00:40:40.497907 ASCII string: InfoVision
9044 00:40:40.501432 Hex of detail: 000000fe00523134304e574635205248200a
9045 00:40:40.504529 ASCII string: R140NWF5 RH
9046 00:40:40.504920 Checksum
9047 00:40:40.508028 Checksum: 0xfb (valid)
9048 00:40:40.511284 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9049 00:40:40.514773 DSI data_rate: 832800000 bps
9050 00:40:40.521012 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9051 00:40:40.524332 anx7625_parse_edid: pixelclock(138800).
9052 00:40:40.527761 hactive(1920), hsync(48), hfp(24), hbp(88)
9053 00:40:40.530970 vactive(1080), vsync(12), vfp(3), vbp(17)
9054 00:40:40.534153 anx7625_dsi_config: config dsi.
9055 00:40:40.541067 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9056 00:40:40.554334 anx7625_dsi_config: success to config DSI
9057 00:40:40.557503 anx7625_dp_start: MIPI phy setup OK.
9058 00:40:40.560832 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9059 00:40:40.563827 mtk_ddp_mode_set invalid vrefresh 60
9060 00:40:40.567128 main_disp_path_setup
9061 00:40:40.567516 ovl_layer_smi_id_en
9062 00:40:40.570566 ovl_layer_smi_id_en
9063 00:40:40.570952 ccorr_config
9064 00:40:40.571253 aal_config
9065 00:40:40.573829 gamma_config
9066 00:40:40.574274 postmask_config
9067 00:40:40.577357 dither_config
9068 00:40:40.580471 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9069 00:40:40.587383 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9070 00:40:40.590669 Root Device init finished in 552 msecs
9071 00:40:40.591058 CPU_CLUSTER: 0 init
9072 00:40:40.600566 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9073 00:40:40.603848 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9074 00:40:40.607187 APU_MBOX 0x190000b0 = 0x10001
9075 00:40:40.610357 APU_MBOX 0x190001b0 = 0x10001
9076 00:40:40.613640 APU_MBOX 0x190005b0 = 0x10001
9077 00:40:40.616921 APU_MBOX 0x190006b0 = 0x10001
9078 00:40:40.620390 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9079 00:40:40.633155 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9080 00:40:40.645475 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9081 00:40:40.651761 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9082 00:40:40.663469 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9083 00:40:40.672545 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9084 00:40:40.676002 CPU_CLUSTER: 0 init finished in 81 msecs
9085 00:40:40.679171 Devices initialized
9086 00:40:40.682857 Show all devs... After init.
9087 00:40:40.683272 Root Device: enabled 1
9088 00:40:40.685859 CPU_CLUSTER: 0: enabled 1
9089 00:40:40.689228 CPU: 00: enabled 1
9090 00:40:40.692846 BS: BS_DEV_INIT run times (exec / console): 210 / 447 ms
9091 00:40:40.696218 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9092 00:40:40.698995 ELOG: NV offset 0x57f000 size 0x1000
9093 00:40:40.705629 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9094 00:40:40.712564 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9095 00:40:40.715925 ELOG: Event(17) added with size 13 at 2024-06-16 00:40:40 UTC
9096 00:40:40.719124 out: cmd=0x121: 03 db 21 01 00 00 00 00
9097 00:40:40.722726 in-header: 03 6b 00 00 2c 00 00 00
9098 00:40:40.735829 in-data: d8 6c 00 00 00 00 00 00 0a 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9099 00:40:40.742835 ELOG: Event(A1) added with size 10 at 2024-06-16 00:40:40 UTC
9100 00:40:40.749817 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
9101 00:40:40.752657 ELOG: Event(A0) added with size 9 at 2024-06-16 00:40:40 UTC
9102 00:40:40.759474 elog_add_boot_reason: Logged dev mode boot
9103 00:40:40.762796 BS: BS_POST_DEVICE entry times (exec / console): 1 / 64 ms
9104 00:40:40.765993 Finalize devices...
9105 00:40:40.766491 Devices finalized
9106 00:40:40.772865 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9107 00:40:40.775992 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
9108 00:40:40.779345 in-header: 03 07 00 00 08 00 00 00
9109 00:40:40.782661 in-data: aa e4 47 04 13 02 00 00
9110 00:40:40.785841 Chrome EC: UHEPI supported
9111 00:40:40.792801 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
9112 00:40:40.795714 in-header: 03 a9 00 00 08 00 00 00
9113 00:40:40.799261 in-data: 84 60 60 08 00 00 00 00
9114 00:40:40.802499 ELOG: Event(91) added with size 10 at 2024-06-16 00:40:40 UTC
9115 00:40:40.809137 Chrome EC: clear events_b mask to 0x0000000020004000
9116 00:40:40.816119 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
9117 00:40:40.819593 in-header: 03 fd 00 00 00 00 00 00
9118 00:40:40.819985 in-data:
9119 00:40:40.826090 BS: BS_WRITE_TABLES entry times (exec / console): 2 / 46 ms
9120 00:40:40.829496 Writing coreboot table at 0xffe64000
9121 00:40:40.832820 0. 000000000010a000-0000000000113fff: RAMSTAGE
9122 00:40:40.836352 1. 0000000040000000-00000000400fffff: RAM
9123 00:40:40.839448 2. 0000000040100000-000000004032afff: RAMSTAGE
9124 00:40:40.842689 3. 000000004032b000-00000000545fffff: RAM
9125 00:40:40.849183 4. 0000000054600000-000000005465ffff: BL31
9126 00:40:40.852927 5. 0000000054660000-00000000ffe63fff: RAM
9127 00:40:40.855866 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9128 00:40:40.862437 7. 0000000100000000-000000013fffffff: RAM
9129 00:40:40.862882 Passing 5 GPIOs to payload:
9130 00:40:40.869161 NAME | PORT | POLARITY | VALUE
9131 00:40:40.872615 EC in RW | 0x000000aa | low | undefined
9132 00:40:40.875909 EC interrupt | 0x00000005 | low | undefined
9133 00:40:40.882949 TPM interrupt | 0x000000ab | high | undefined
9134 00:40:40.886325 SD card detect | 0x00000011 | high | undefined
9135 00:40:40.892485 speaker enable | 0x00000093 | high | undefined
9136 00:40:40.895731 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9137 00:40:40.899692 in-header: 03 f8 00 00 02 00 00 00
9138 00:40:40.900085 in-data: 03 00
9139 00:40:40.902653 ADC[4]: Raw value=668958 ID=5
9140 00:40:40.905937 ADC[3]: Raw value=212549 ID=1
9141 00:40:40.906452 RAM Code: 0x51
9142 00:40:40.909416 ADC[6]: Raw value=74778 ID=0
9143 00:40:40.912400 ADC[5]: Raw value=211812 ID=1
9144 00:40:40.912838 SKU Code: 0x1
9145 00:40:40.918740 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 24ad
9146 00:40:40.922516 coreboot table: 964 bytes.
9147 00:40:40.925824 IMD ROOT 0. 0xfffff000 0x00001000
9148 00:40:40.929010 IMD SMALL 1. 0xffffe000 0x00001000
9149 00:40:40.932207 RO MCACHE 2. 0xffffc000 0x00001104
9150 00:40:40.935536 CONSOLE 3. 0xfff7c000 0x00080000
9151 00:40:40.939136 FMAP 4. 0xfff7b000 0x00000452
9152 00:40:40.942618 TIME STAMP 5. 0xfff7a000 0x00000910
9153 00:40:40.945802 VBOOT WORK 6. 0xfff66000 0x00014000
9154 00:40:40.949228 RAMOOPS 7. 0xffe66000 0x00100000
9155 00:40:40.952370 COREBOOT 8. 0xffe64000 0x00002000
9156 00:40:40.952755 IMD small region:
9157 00:40:40.955642 IMD ROOT 0. 0xffffec00 0x00000400
9158 00:40:40.958842 VPD 1. 0xffffeb80 0x0000006c
9159 00:40:40.962348 MMC STATUS 2. 0xffffeb60 0x00000004
9160 00:40:40.969233 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9161 00:40:40.975554 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9162 00:40:41.014483 read SPI 0x3990ec 0x4f1b0: 34847 us, 9298 KB/s, 74.384 Mbps
9163 00:40:41.017653 Checking segment from ROM address 0x40100000
9164 00:40:41.021156 Checking segment from ROM address 0x4010001c
9165 00:40:41.028102 Loading segment from ROM address 0x40100000
9166 00:40:41.028495 code (compression=0)
9167 00:40:41.037995 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9168 00:40:41.044139 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9169 00:40:41.044533 it's not compressed!
9170 00:40:41.051171 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9171 00:40:41.057288 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9172 00:40:41.074996 Loading segment from ROM address 0x4010001c
9173 00:40:41.075386 Entry Point 0x80000000
9174 00:40:41.078346 Loaded segments
9175 00:40:41.081945 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9176 00:40:41.088245 Jumping to boot code at 0x80000000(0xffe64000)
9177 00:40:41.095159 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9178 00:40:41.102026 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9179 00:40:41.110280 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9180 00:40:41.112775 Checking segment from ROM address 0x40100000
9181 00:40:41.116045 Checking segment from ROM address 0x4010001c
9182 00:40:41.122856 Loading segment from ROM address 0x40100000
9183 00:40:41.123243 code (compression=1)
9184 00:40:41.129436 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9185 00:40:41.139248 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9186 00:40:41.139637 using LZMA
9187 00:40:41.147703 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9188 00:40:41.154289 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9189 00:40:41.157566 Loading segment from ROM address 0x4010001c
9190 00:40:41.157955 Entry Point 0x54601000
9191 00:40:41.161028 Loaded segments
9192 00:40:41.164334 NOTICE: MT8192 bl31_setup
9193 00:40:41.171393 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9194 00:40:41.174457 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9195 00:40:41.178281 WARNING: region 0:
9196 00:40:41.181172 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9197 00:40:41.181559 WARNING: region 1:
9198 00:40:41.187811 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9199 00:40:41.191041 WARNING: region 2:
9200 00:40:41.194578 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9201 00:40:41.197755 WARNING: region 3:
9202 00:40:41.201129 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9203 00:40:41.204568 WARNING: region 4:
9204 00:40:41.210990 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9205 00:40:41.211381 WARNING: region 5:
9206 00:40:41.214584 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9207 00:40:41.217903 WARNING: region 6:
9208 00:40:41.221173 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9209 00:40:41.224902 WARNING: region 7:
9210 00:40:41.227970 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9211 00:40:41.234619 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9212 00:40:41.238027 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9213 00:40:41.241163 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9214 00:40:41.247859 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9215 00:40:41.251687 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9216 00:40:41.254744 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9217 00:40:41.260951 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9218 00:40:41.264607 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9219 00:40:41.271031 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9220 00:40:41.274531 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9221 00:40:41.277753 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9222 00:40:41.284314 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9223 00:40:41.287959 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9224 00:40:41.291413 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9225 00:40:41.297488 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9226 00:40:41.301189 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9227 00:40:41.307396 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9228 00:40:41.310990 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9229 00:40:41.314190 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9230 00:40:41.320836 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9231 00:40:41.324045 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9232 00:40:41.327589 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9233 00:40:41.334036 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9234 00:40:41.337596 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9235 00:40:41.344494 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9236 00:40:41.347440 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9237 00:40:41.354184 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9238 00:40:41.357679 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9239 00:40:41.360697 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9240 00:40:41.367083 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9241 00:40:41.370506 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9242 00:40:41.377771 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9243 00:40:41.380510 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9244 00:40:41.384113 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9245 00:40:41.387682 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9246 00:40:41.393970 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9247 00:40:41.397221 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9248 00:40:41.400742 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9249 00:40:41.404522 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9250 00:40:41.407036 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9251 00:40:41.413761 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9252 00:40:41.417216 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9253 00:40:41.420689 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9254 00:40:41.424285 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9255 00:40:41.430458 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9256 00:40:41.434041 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9257 00:40:41.437100 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9258 00:40:41.443799 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9259 00:40:41.447025 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9260 00:40:41.449847 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9261 00:40:41.456586 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9262 00:40:41.459968 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9263 00:40:41.466432 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9264 00:40:41.469760 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9265 00:40:41.476645 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9266 00:40:41.479934 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9267 00:40:41.483374 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9268 00:40:41.489779 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9269 00:40:41.493225 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9270 00:40:41.499834 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9271 00:40:41.503080 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9272 00:40:41.509839 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9273 00:40:41.513202 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9274 00:40:41.520089 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9275 00:40:41.523005 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9276 00:40:41.526556 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9277 00:40:41.533379 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9278 00:40:41.536665 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9279 00:40:41.543286 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9280 00:40:41.546879 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9281 00:40:41.553311 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9282 00:40:41.556448 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9283 00:40:41.559850 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9284 00:40:41.566236 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9285 00:40:41.569571 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9286 00:40:41.576311 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9287 00:40:41.579888 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9288 00:40:41.586479 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9289 00:40:41.589733 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9290 00:40:41.593271 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9291 00:40:41.599872 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9292 00:40:41.603327 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9293 00:40:41.609801 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9294 00:40:41.612991 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9295 00:40:41.619761 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9296 00:40:41.623176 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9297 00:40:41.626480 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9298 00:40:41.633008 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9299 00:40:41.636149 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9300 00:40:41.643347 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9301 00:40:41.646506 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9302 00:40:41.653221 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9303 00:40:41.656534 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9304 00:40:41.659620 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9305 00:40:41.666425 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9306 00:40:41.669648 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9307 00:40:41.676104 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9308 00:40:41.679495 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9309 00:40:41.682944 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9310 00:40:41.686195 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9311 00:40:41.693353 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9312 00:40:41.696051 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9313 00:40:41.699561 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9314 00:40:41.706198 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9315 00:40:41.709688 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9316 00:40:41.716282 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9317 00:40:41.719200 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9318 00:40:41.726165 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9319 00:40:41.729072 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9320 00:40:41.732526 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9321 00:40:41.739392 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9322 00:40:41.742682 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9323 00:40:41.749072 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9324 00:40:41.752383 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9325 00:40:41.755922 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9326 00:40:41.762617 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9327 00:40:41.766542 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9328 00:40:41.769461 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9329 00:40:41.776005 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9330 00:40:41.779243 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9331 00:40:41.782487 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9332 00:40:41.785677 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9333 00:40:41.792134 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9334 00:40:41.795527 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9335 00:40:41.798947 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9336 00:40:41.805649 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9337 00:40:41.809323 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9338 00:40:41.812431 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9339 00:40:41.819364 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9340 00:40:41.822098 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9341 00:40:41.828857 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9342 00:40:41.832550 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9343 00:40:41.835723 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9344 00:40:41.841925 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9345 00:40:41.845115 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9346 00:40:41.851754 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9347 00:40:41.855914 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9348 00:40:41.858539 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9349 00:40:41.865510 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9350 00:40:41.868440 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9351 00:40:41.874888 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9352 00:40:41.878523 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9353 00:40:41.881744 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9354 00:40:41.888348 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9355 00:40:41.891848 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9356 00:40:41.898646 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9357 00:40:41.902196 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9358 00:40:41.905159 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9359 00:40:41.911660 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9360 00:40:41.915153 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9361 00:40:41.921665 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9362 00:40:41.924814 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9363 00:40:41.928290 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9364 00:40:41.934885 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9365 00:40:41.938087 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9366 00:40:41.941560 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9367 00:40:41.948248 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9368 00:40:41.951392 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9369 00:40:41.958082 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9370 00:40:41.961676 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9371 00:40:41.965069 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9372 00:40:41.971453 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9373 00:40:41.975026 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9374 00:40:41.981392 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9375 00:40:41.984816 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9376 00:40:41.988750 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9377 00:40:41.994581 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9378 00:40:41.998338 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9379 00:40:42.001248 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9380 00:40:42.007955 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9381 00:40:42.011312 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9382 00:40:42.017887 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9383 00:40:42.021297 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9384 00:40:42.024530 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9385 00:40:42.031624 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9386 00:40:42.034993 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9387 00:40:42.041349 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9388 00:40:42.044764 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9389 00:40:42.048036 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9390 00:40:42.054716 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9391 00:40:42.057818 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9392 00:40:42.064813 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9393 00:40:42.067663 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9394 00:40:42.071391 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9395 00:40:42.077614 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9396 00:40:42.081162 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9397 00:40:42.084363 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9398 00:40:42.091136 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9399 00:40:42.094187 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9400 00:40:42.101119 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9401 00:40:42.104294 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9402 00:40:42.110783 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9403 00:40:42.114330 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9404 00:40:42.118069 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9405 00:40:42.124118 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9406 00:40:42.127522 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9407 00:40:42.134396 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9408 00:40:42.137684 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9409 00:40:42.141173 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9410 00:40:42.147571 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9411 00:40:42.150871 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9412 00:40:42.157587 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9413 00:40:42.161157 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9414 00:40:42.167303 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9415 00:40:42.170880 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9416 00:40:42.174059 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9417 00:40:42.180999 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9418 00:40:42.183945 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9419 00:40:42.190876 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9420 00:40:42.194097 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9421 00:40:42.197420 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9422 00:40:42.203895 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9423 00:40:42.207300 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9424 00:40:42.214232 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9425 00:40:42.217333 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9426 00:40:42.220740 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9427 00:40:42.227521 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9428 00:40:42.230815 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9429 00:40:42.237181 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9430 00:40:42.240607 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9431 00:40:42.247753 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9432 00:40:42.250768 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9433 00:40:42.253906 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9434 00:40:42.260650 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9435 00:40:42.264130 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9436 00:40:42.270707 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9437 00:40:42.274128 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9438 00:40:42.277219 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9439 00:40:42.283753 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9440 00:40:42.287246 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9441 00:40:42.290756 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9442 00:40:42.294157 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9443 00:40:42.300560 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9444 00:40:42.304097 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9445 00:40:42.307687 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9446 00:40:42.313805 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9447 00:40:42.317390 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9448 00:40:42.320813 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9449 00:40:42.327611 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9450 00:40:42.330944 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9451 00:40:42.337460 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9452 00:40:42.340673 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9453 00:40:42.344201 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9454 00:40:42.350757 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9455 00:40:42.354071 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9456 00:40:42.357346 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9457 00:40:42.364079 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9458 00:40:42.367461 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9459 00:40:42.370881 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9460 00:40:42.377441 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9461 00:40:42.380582 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9462 00:40:42.387686 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9463 00:40:42.390400 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9464 00:40:42.393783 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9465 00:40:42.400577 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9466 00:40:42.403545 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9467 00:40:42.407209 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9468 00:40:42.413617 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9469 00:40:42.416937 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9470 00:40:42.420273 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9471 00:40:42.426934 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9472 00:40:42.430128 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9473 00:40:42.436940 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9474 00:40:42.440347 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9475 00:40:42.443685 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9476 00:40:42.450422 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9477 00:40:42.453258 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9478 00:40:42.456911 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9479 00:40:42.463406 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9480 00:40:42.466996 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9481 00:40:42.469800 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9482 00:40:42.473230 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9483 00:40:42.480245 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9484 00:40:42.483454 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9485 00:40:42.486650 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9486 00:40:42.489868 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9487 00:40:42.496574 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9488 00:40:42.500134 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9489 00:40:42.503381 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9490 00:40:42.506944 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9491 00:40:42.513088 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9492 00:40:42.516638 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9493 00:40:42.520116 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9494 00:40:42.526482 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9495 00:40:42.529812 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9496 00:40:42.536659 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9497 00:40:42.539988 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9498 00:40:42.543155 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9499 00:40:42.550072 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9500 00:40:42.553109 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9501 00:40:42.556942 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9502 00:40:42.563205 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9503 00:40:42.566421 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9504 00:40:42.573527 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9505 00:40:42.576618 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9506 00:40:42.583446 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9507 00:40:42.586668 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9508 00:40:42.589774 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9509 00:40:42.596629 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9510 00:40:42.599794 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9511 00:40:42.606278 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9512 00:40:42.609855 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9513 00:40:42.613274 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9514 00:40:42.619647 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9515 00:40:42.622925 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9516 00:40:42.629903 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9517 00:40:42.633218 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9518 00:40:42.636204 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9519 00:40:42.643258 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9520 00:40:42.646315 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9521 00:40:42.653754 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9522 00:40:42.656270 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9523 00:40:42.663054 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9524 00:40:42.666386 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9525 00:40:42.669799 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9526 00:40:42.676420 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9527 00:40:42.679394 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9528 00:40:42.686307 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9529 00:40:42.689554 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9530 00:40:42.692955 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9531 00:40:42.699384 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9532 00:40:42.703516 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9533 00:40:42.709427 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9534 00:40:42.712804 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9535 00:40:42.716797 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9536 00:40:42.722912 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9537 00:40:42.726144 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9538 00:40:42.733295 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9539 00:40:42.735942 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9540 00:40:42.739527 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9541 00:40:42.746350 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9542 00:40:42.749216 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9543 00:40:42.756044 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9544 00:40:42.759506 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9545 00:40:42.762788 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9546 00:40:42.769676 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9547 00:40:42.773111 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9548 00:40:42.779703 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9549 00:40:42.782516 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9550 00:40:42.785905 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9551 00:40:42.792531 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9552 00:40:42.796362 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9553 00:40:42.802706 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9554 00:40:42.806082 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9555 00:40:42.812634 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9556 00:40:42.816330 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9557 00:40:42.819312 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9558 00:40:42.826007 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9559 00:40:42.829299 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9560 00:40:42.832603 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9561 00:40:42.839615 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9562 00:40:42.842920 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9563 00:40:42.849527 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9564 00:40:42.852537 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9565 00:40:42.855929 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9566 00:40:42.862885 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9567 00:40:42.865907 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9568 00:40:42.872794 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9569 00:40:42.875875 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9570 00:40:42.882773 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9571 00:40:42.886047 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9572 00:40:42.889639 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9573 00:40:42.895838 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9574 00:40:42.899143 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9575 00:40:42.906025 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9576 00:40:42.909128 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9577 00:40:42.915786 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9578 00:40:42.919489 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9579 00:40:42.925986 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9580 00:40:42.929522 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9581 00:40:42.932631 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9582 00:40:42.939254 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9583 00:40:42.942634 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9584 00:40:42.949185 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9585 00:40:42.952771 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9586 00:40:42.959106 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9587 00:40:42.962482 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9588 00:40:42.966086 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9589 00:40:42.972437 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9590 00:40:42.975814 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9591 00:40:42.982330 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9592 00:40:42.985987 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9593 00:40:42.992412 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9594 00:40:42.995824 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9595 00:40:42.999274 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9596 00:40:43.006115 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9597 00:40:43.009138 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9598 00:40:43.015621 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9599 00:40:43.019020 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9600 00:40:43.025863 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9601 00:40:43.029133 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9602 00:40:43.032760 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9603 00:40:43.038900 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9604 00:40:43.042415 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9605 00:40:43.049285 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9606 00:40:43.052663 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9607 00:40:43.058986 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9608 00:40:43.062367 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9609 00:40:43.065429 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9610 00:40:43.072064 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9611 00:40:43.075388 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9612 00:40:43.082028 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9613 00:40:43.085412 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9614 00:40:43.089130 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9615 00:40:43.095465 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9616 00:40:43.098552 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9617 00:40:43.105441 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9618 00:40:43.109134 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9619 00:40:43.115924 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9620 00:40:43.119329 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9621 00:40:43.125716 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9622 00:40:43.128816 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9623 00:40:43.135373 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9624 00:40:43.138877 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9625 00:40:43.145527 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9626 00:40:43.148930 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9627 00:40:43.155443 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9628 00:40:43.158952 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9629 00:40:43.165666 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9630 00:40:43.168697 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9631 00:40:43.175422 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9632 00:40:43.178854 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9633 00:40:43.185360 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9634 00:40:43.188874 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9635 00:40:43.195289 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9636 00:40:43.198577 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9637 00:40:43.205126 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9638 00:40:43.208892 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9639 00:40:43.215327 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9640 00:40:43.218658 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9641 00:40:43.225626 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9642 00:40:43.228815 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9643 00:40:43.235427 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9644 00:40:43.238595 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9645 00:40:43.242112 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9646 00:40:43.245594 INFO: [APUAPC] vio 0
9647 00:40:43.248446 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9648 00:40:43.255569 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9649 00:40:43.258769 INFO: [APUAPC] D0_APC_0: 0x400510
9650 00:40:43.262013 INFO: [APUAPC] D0_APC_1: 0x0
9651 00:40:43.264965 INFO: [APUAPC] D0_APC_2: 0x1540
9652 00:40:43.265058 INFO: [APUAPC] D0_APC_3: 0x0
9653 00:40:43.271791 INFO: [APUAPC] D1_APC_0: 0xffffffff
9654 00:40:43.275196 INFO: [APUAPC] D1_APC_1: 0xffffffff
9655 00:40:43.278167 INFO: [APUAPC] D1_APC_2: 0x3fffff
9656 00:40:43.278287 INFO: [APUAPC] D1_APC_3: 0x0
9657 00:40:43.281488 INFO: [APUAPC] D2_APC_0: 0xffffffff
9658 00:40:43.288492 INFO: [APUAPC] D2_APC_1: 0xffffffff
9659 00:40:43.288570 INFO: [APUAPC] D2_APC_2: 0x3fffff
9660 00:40:43.291574 INFO: [APUAPC] D2_APC_3: 0x0
9661 00:40:43.294838 INFO: [APUAPC] D3_APC_0: 0xffffffff
9662 00:40:43.298295 INFO: [APUAPC] D3_APC_1: 0xffffffff
9663 00:40:43.301344 INFO: [APUAPC] D3_APC_2: 0x3fffff
9664 00:40:43.305020 INFO: [APUAPC] D3_APC_3: 0x0
9665 00:40:43.307991 INFO: [APUAPC] D4_APC_0: 0xffffffff
9666 00:40:43.311306 INFO: [APUAPC] D4_APC_1: 0xffffffff
9667 00:40:43.314769 INFO: [APUAPC] D4_APC_2: 0x3fffff
9668 00:40:43.318126 INFO: [APUAPC] D4_APC_3: 0x0
9669 00:40:43.321458 INFO: [APUAPC] D5_APC_0: 0xffffffff
9670 00:40:43.324580 INFO: [APUAPC] D5_APC_1: 0xffffffff
9671 00:40:43.328199 INFO: [APUAPC] D5_APC_2: 0x3fffff
9672 00:40:43.331300 INFO: [APUAPC] D5_APC_3: 0x0
9673 00:40:43.334688 INFO: [APUAPC] D6_APC_0: 0xffffffff
9674 00:40:43.338005 INFO: [APUAPC] D6_APC_1: 0xffffffff
9675 00:40:43.341356 INFO: [APUAPC] D6_APC_2: 0x3fffff
9676 00:40:43.344590 INFO: [APUAPC] D6_APC_3: 0x0
9677 00:40:43.347586 INFO: [APUAPC] D7_APC_0: 0xffffffff
9678 00:40:43.351325 INFO: [APUAPC] D7_APC_1: 0xffffffff
9679 00:40:43.354342 INFO: [APUAPC] D7_APC_2: 0x3fffff
9680 00:40:43.357733 INFO: [APUAPC] D7_APC_3: 0x0
9681 00:40:43.361024 INFO: [APUAPC] D8_APC_0: 0xffffffff
9682 00:40:43.364375 INFO: [APUAPC] D8_APC_1: 0xffffffff
9683 00:40:43.368409 INFO: [APUAPC] D8_APC_2: 0x3fffff
9684 00:40:43.371169 INFO: [APUAPC] D8_APC_3: 0x0
9685 00:40:43.374340 INFO: [APUAPC] D9_APC_0: 0xffffffff
9686 00:40:43.378043 INFO: [APUAPC] D9_APC_1: 0xffffffff
9687 00:40:43.380762 INFO: [APUAPC] D9_APC_2: 0x3fffff
9688 00:40:43.384615 INFO: [APUAPC] D9_APC_3: 0x0
9689 00:40:43.387587 INFO: [APUAPC] D10_APC_0: 0xffffffff
9690 00:40:43.391421 INFO: [APUAPC] D10_APC_1: 0xffffffff
9691 00:40:43.394296 INFO: [APUAPC] D10_APC_2: 0x3fffff
9692 00:40:43.397529 INFO: [APUAPC] D10_APC_3: 0x0
9693 00:40:43.401205 INFO: [APUAPC] D11_APC_0: 0xffffffff
9694 00:40:43.404137 INFO: [APUAPC] D11_APC_1: 0xffffffff
9695 00:40:43.407237 INFO: [APUAPC] D11_APC_2: 0x3fffff
9696 00:40:43.410681 INFO: [APUAPC] D11_APC_3: 0x0
9697 00:40:43.414341 INFO: [APUAPC] D12_APC_0: 0xffffffff
9698 00:40:43.417557 INFO: [APUAPC] D12_APC_1: 0xffffffff
9699 00:40:43.420933 INFO: [APUAPC] D12_APC_2: 0x3fffff
9700 00:40:43.424279 INFO: [APUAPC] D12_APC_3: 0x0
9701 00:40:43.427462 INFO: [APUAPC] D13_APC_0: 0xffffffff
9702 00:40:43.430517 INFO: [APUAPC] D13_APC_1: 0xffffffff
9703 00:40:43.434008 INFO: [APUAPC] D13_APC_2: 0x3fffff
9704 00:40:43.437358 INFO: [APUAPC] D13_APC_3: 0x0
9705 00:40:43.440694 INFO: [APUAPC] D14_APC_0: 0xffffffff
9706 00:40:43.444231 INFO: [APUAPC] D14_APC_1: 0xffffffff
9707 00:40:43.447107 INFO: [APUAPC] D14_APC_2: 0x3fffff
9708 00:40:43.450490 INFO: [APUAPC] D14_APC_3: 0x0
9709 00:40:43.453791 INFO: [APUAPC] D15_APC_0: 0xffffffff
9710 00:40:43.457133 INFO: [APUAPC] D15_APC_1: 0xffffffff
9711 00:40:43.460549 INFO: [APUAPC] D15_APC_2: 0x3fffff
9712 00:40:43.463947 INFO: [APUAPC] D15_APC_3: 0x0
9713 00:40:43.467288 INFO: [APUAPC] APC_CON: 0x4
9714 00:40:43.470322 INFO: [NOCDAPC] D0_APC_0: 0x0
9715 00:40:43.473477 INFO: [NOCDAPC] D0_APC_1: 0x0
9716 00:40:43.476749 INFO: [NOCDAPC] D1_APC_0: 0x0
9717 00:40:43.476825 INFO: [NOCDAPC] D1_APC_1: 0xfff
9718 00:40:43.480381 INFO: [NOCDAPC] D2_APC_0: 0x0
9719 00:40:43.483880 INFO: [NOCDAPC] D2_APC_1: 0xfff
9720 00:40:43.486755 INFO: [NOCDAPC] D3_APC_0: 0x0
9721 00:40:43.490301 INFO: [NOCDAPC] D3_APC_1: 0xfff
9722 00:40:43.493515 INFO: [NOCDAPC] D4_APC_0: 0x0
9723 00:40:43.497215 INFO: [NOCDAPC] D4_APC_1: 0xfff
9724 00:40:43.500472 INFO: [NOCDAPC] D5_APC_0: 0x0
9725 00:40:43.503478 INFO: [NOCDAPC] D5_APC_1: 0xfff
9726 00:40:43.507054 INFO: [NOCDAPC] D6_APC_0: 0x0
9727 00:40:43.510049 INFO: [NOCDAPC] D6_APC_1: 0xfff
9728 00:40:43.510150 INFO: [NOCDAPC] D7_APC_0: 0x0
9729 00:40:43.513457 INFO: [NOCDAPC] D7_APC_1: 0xfff
9730 00:40:43.516739 INFO: [NOCDAPC] D8_APC_0: 0x0
9731 00:40:43.520227 INFO: [NOCDAPC] D8_APC_1: 0xfff
9732 00:40:43.523649 INFO: [NOCDAPC] D9_APC_0: 0x0
9733 00:40:43.526820 INFO: [NOCDAPC] D9_APC_1: 0xfff
9734 00:40:43.530575 INFO: [NOCDAPC] D10_APC_0: 0x0
9735 00:40:43.533429 INFO: [NOCDAPC] D10_APC_1: 0xfff
9736 00:40:43.536990 INFO: [NOCDAPC] D11_APC_0: 0x0
9737 00:40:43.539868 INFO: [NOCDAPC] D11_APC_1: 0xfff
9738 00:40:43.543650 INFO: [NOCDAPC] D12_APC_0: 0x0
9739 00:40:43.546586 INFO: [NOCDAPC] D12_APC_1: 0xfff
9740 00:40:43.549912 INFO: [NOCDAPC] D13_APC_0: 0x0
9741 00:40:43.549989 INFO: [NOCDAPC] D13_APC_1: 0xfff
9742 00:40:43.553202 INFO: [NOCDAPC] D14_APC_0: 0x0
9743 00:40:43.556827 INFO: [NOCDAPC] D14_APC_1: 0xfff
9744 00:40:43.560076 INFO: [NOCDAPC] D15_APC_0: 0x0
9745 00:40:43.564008 INFO: [NOCDAPC] D15_APC_1: 0xfff
9746 00:40:43.566514 INFO: [NOCDAPC] APC_CON: 0x4
9747 00:40:43.570000 INFO: [APUAPC] set_apusys_apc done
9748 00:40:43.573092 INFO: [DEVAPC] devapc_init done
9749 00:40:43.576449 INFO: GICv3 without legacy support detected.
9750 00:40:43.579884 INFO: ARM GICv3 driver initialized in EL3
9751 00:40:43.586469 INFO: Maximum SPI INTID supported: 639
9752 00:40:43.589680 INFO: BL31: Initializing runtime services
9753 00:40:43.596530 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9754 00:40:43.596608 INFO: SPM: enable CPC mode
9755 00:40:43.603079 INFO: mcdi ready for mcusys-off-idle and system suspend
9756 00:40:43.606499 INFO: BL31: Preparing for EL3 exit to normal world
9757 00:40:43.609999 INFO: Entry point address = 0x80000000
9758 00:40:43.613393 INFO: SPSR = 0x8
9759 00:40:43.619256
9760 00:40:43.619332
9761 00:40:43.619392
9762 00:40:43.622416 Starting depthcharge on Spherion...
9763 00:40:43.622493
9764 00:40:43.622554 Wipe memory regions:
9765 00:40:43.622609
9766 00:40:43.623177 end: 2.2.3 depthcharge-start (duration 00:00:18) [common]
9767 00:40:43.623269 start: 2.2.4 bootloader-commands (timeout 00:04:28) [common]
9768 00:40:43.623346 Setting prompt string to ['asurada:']
9769 00:40:43.623417 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:28)
9770 00:40:43.625709 [0x00000040000000, 0x00000054600000)
9771 00:40:43.748030
9772 00:40:43.748131 [0x00000054660000, 0x00000080000000)
9773 00:40:44.008334
9774 00:40:44.008448 [0x000000821a7280, 0x000000ffe64000)
9775 00:40:44.753247
9776 00:40:44.753362 [0x00000100000000, 0x00000140000000)
9777 00:40:45.133935
9778 00:40:45.136697 Initializing XHCI USB controller at 0x11200000.
9779 00:40:46.175399
9780 00:40:46.178670 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
9781 00:40:46.178749
9782 00:40:46.178810
9783 00:40:46.179079 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9785 00:40:46.279424 asurada: tftpboot 192.168.201.1 14368404/tftp-deploy-4qyk1yvl/kernel/image.itb 14368404/tftp-deploy-4qyk1yvl/kernel/cmdline
9786 00:40:46.279607 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9787 00:40:46.279717 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:26)
9788 00:40:46.283546 tftpboot 192.168.201.1 14368404/tftp-deploy-4qyk1yvl/kernel/image.itp-deploy-4qyk1yvl/kernel/cmdline
9789 00:40:46.283625
9790 00:40:46.283686 Waiting for link
9791 00:40:46.441899
9792 00:40:46.442015 R8152: Initializing
9793 00:40:46.442076
9794 00:40:46.445016 Version 9 (ocp_data = 6010)
9795 00:40:46.445093
9796 00:40:46.448681 R8152: Done initializing
9797 00:40:46.448758
9798 00:40:46.448818 Adding net device
9799 00:40:48.462698
9800 00:40:48.462813 done.
9801 00:40:48.462873
9802 00:40:48.462929 MAC: 00:e0:4c:68:03:bd
9803 00:40:48.462981
9804 00:40:48.465791 Sending DHCP discover... done.
9805 00:40:48.465867
9806 00:40:48.469668 Waiting for reply... done.
9807 00:40:48.469771
9808 00:40:48.472391 Sending DHCP request... done.
9809 00:40:48.472474
9810 00:40:48.477383 Waiting for reply... done.
9811 00:40:48.477478
9812 00:40:48.477560 My ip is 192.168.201.16
9813 00:40:48.477640
9814 00:40:48.480658 The DHCP server ip is 192.168.201.1
9815 00:40:48.480747
9816 00:40:48.486961 TFTP server IP predefined by user: 192.168.201.1
9817 00:40:48.487054
9818 00:40:48.493484 Bootfile predefined by user: 14368404/tftp-deploy-4qyk1yvl/kernel/image.itb
9819 00:40:48.493578
9820 00:40:48.496934 Sending tftp read request... done.
9821 00:40:48.497030
9822 00:40:48.501057 Waiting for the transfer...
9823 00:40:48.501148
9824 00:40:48.750754 00000000 ################################################################
9825 00:40:48.750892
9826 00:40:48.996826 00080000 ################################################################
9827 00:40:48.996987
9828 00:40:49.239476 00100000 ################################################################
9829 00:40:49.239593
9830 00:40:49.489356 00180000 ################################################################
9831 00:40:49.489468
9832 00:40:49.738395 00200000 ################################################################
9833 00:40:49.738510
9834 00:40:49.995149 00280000 ################################################################
9835 00:40:49.995283
9836 00:40:50.251017 00300000 ################################################################
9837 00:40:50.251134
9838 00:40:50.496859 00380000 ################################################################
9839 00:40:50.496974
9840 00:40:50.751501 00400000 ################################################################
9841 00:40:50.751616
9842 00:40:51.004790 00480000 ################################################################
9843 00:40:51.004906
9844 00:40:51.267135 00500000 ################################################################
9845 00:40:51.267288
9846 00:40:51.528913 00580000 ################################################################
9847 00:40:51.529097
9848 00:40:51.776689 00600000 ################################################################
9849 00:40:51.776803
9850 00:40:52.020534 00680000 ################################################################
9851 00:40:52.020642
9852 00:40:52.268357 00700000 ################################################################
9853 00:40:52.268488
9854 00:40:52.517479 00780000 ################################################################
9855 00:40:52.517634
9856 00:40:52.764711 00800000 ################################################################
9857 00:40:52.764868
9858 00:40:53.014836 00880000 ################################################################
9859 00:40:53.014963
9860 00:40:53.260858 00900000 ################################################################
9861 00:40:53.260979
9862 00:40:53.506531 00980000 ################################################################
9863 00:40:53.506653
9864 00:40:53.752275 00a00000 ################################################################
9865 00:40:53.752395
9866 00:40:53.995775 00a80000 ################################################################
9867 00:40:53.995898
9868 00:40:54.242089 00b00000 ################################################################
9869 00:40:54.242217
9870 00:40:54.488766 00b80000 ################################################################
9871 00:40:54.488901
9872 00:40:54.734046 00c00000 ################################################################
9873 00:40:54.734186
9874 00:40:54.997562 00c80000 ################################################################
9875 00:40:54.997681
9876 00:40:55.244487 00d00000 ################################################################
9877 00:40:55.244670
9878 00:40:55.494321 00d80000 ################################################################
9879 00:40:55.494436
9880 00:40:55.744343 00e00000 ################################################################
9881 00:40:55.744455
9882 00:40:55.991062 00e80000 ################################################################
9883 00:40:55.991177
9884 00:40:56.239352 00f00000 ################################################################
9885 00:40:56.239495
9886 00:40:56.487000 00f80000 ################################################################
9887 00:40:56.487116
9888 00:40:56.737346 01000000 ################################################################
9889 00:40:56.737460
9890 00:40:56.983769 01080000 ################################################################
9891 00:40:56.983892
9892 00:40:57.233191 01100000 ################################################################
9893 00:40:57.233299
9894 00:40:57.480676 01180000 ################################################################
9895 00:40:57.480803
9896 00:40:57.728197 01200000 ################################################################
9897 00:40:57.728322
9898 00:40:57.977611 01280000 ################################################################
9899 00:40:57.977753
9900 00:40:58.227780 01300000 ################################################################
9901 00:40:58.227901
9902 00:40:58.477691 01380000 ################################################################
9903 00:40:58.477814
9904 00:40:58.724902 01400000 ################################################################
9905 00:40:58.725016
9906 00:40:58.974629 01480000 ################################################################
9907 00:40:58.974742
9908 00:40:59.223193 01500000 ################################################################
9909 00:40:59.223303
9910 00:40:59.477686 01580000 ################################################################
9911 00:40:59.477818
9912 00:40:59.730305 01600000 ################################################################
9913 00:40:59.730412
9914 00:40:59.981023 01680000 ################################################################
9915 00:40:59.981136
9916 00:41:00.230740 01700000 ################################################################
9917 00:41:00.230848
9918 00:41:00.485514 01780000 ################################################################
9919 00:41:00.485624
9920 00:41:00.750356 01800000 ################################################################
9921 00:41:00.750464
9922 00:41:00.999100 01880000 ################################################################
9923 00:41:00.999210
9924 00:41:01.261501 01900000 ################################################################
9925 00:41:01.261608
9926 00:41:01.528597 01980000 ################################################################
9927 00:41:01.528713
9928 00:41:01.813502 01a00000 ################################################################
9929 00:41:01.813608
9930 00:41:02.094869 01a80000 ################################################################
9931 00:41:02.094973
9932 00:41:02.367089 01b00000 ################################################################
9933 00:41:02.367203
9934 00:41:02.628325 01b80000 ################################################################
9935 00:41:02.628436
9936 00:41:02.876556 01c00000 ################################################################
9937 00:41:02.876661
9938 00:41:03.126857 01c80000 ################################################################
9939 00:41:03.126993
9940 00:41:03.381928 01d00000 ################################################################
9941 00:41:03.382045
9942 00:41:03.630760 01d80000 ################################################################
9943 00:41:03.630872
9944 00:41:03.846123 01e00000 ######################################################## done.
9945 00:41:03.846293
9946 00:41:03.849750 The bootfile was 31909786 bytes long.
9947 00:41:03.849833
9948 00:41:03.852982 Sending tftp read request... done.
9949 00:41:03.853070
9950 00:41:03.856369 Waiting for the transfer...
9951 00:41:03.856518
9952 00:41:03.856590 00000000 # done.
9953 00:41:03.856657
9954 00:41:03.866474 Command line loaded dynamically from TFTP file: 14368404/tftp-deploy-4qyk1yvl/kernel/cmdline
9955 00:41:03.866640
9956 00:41:03.886416 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14368404/extract-nfsrootfs-_3z5vp51,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
9957 00:41:03.886993
9958 00:41:03.890312 Loading FIT.
9959 00:41:03.890734
9960 00:41:03.892997 Image ramdisk-1 has 18734127 bytes.
9961 00:41:03.893438
9962 00:41:03.893772 Image fdt-1 has 47258 bytes.
9963 00:41:03.894080
9964 00:41:03.896375 Image kernel-1 has 13126376 bytes.
9965 00:41:03.896842
9966 00:41:03.906647 Compat preference: google,spherion-rev3-sku1 google,spherion-rev3 google,spherion-sku1 google,spherion
9967 00:41:03.907168
9968 00:41:03.922979 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 (match) google,spherion-rev2 google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
9969 00:41:03.923506
9970 00:41:03.930262 Choosing best match conf-1 for compat google,spherion-rev3.
9971 00:41:03.933036
9972 00:41:03.938448 Connected to device vid:did:rid of 1ae0:0028:00
9973 00:41:03.945404
9974 00:41:03.948295 tpm_get_response: command 0x17b, return code 0x0
9975 00:41:03.948808
9976 00:41:03.951310 ec_init: CrosEC protocol v3 supported (256, 248)
9977 00:41:03.955564
9978 00:41:03.958584 tpm_cleanup: add release locality here.
9979 00:41:03.959019
9980 00:41:03.959353 Shutting down all USB controllers.
9981 00:41:03.961844
9982 00:41:03.962358 Removing current net device
9983 00:41:03.962706
9984 00:41:03.968859 Exiting depthcharge with code 4 at timestamp: 48533291
9985 00:41:03.969359
9986 00:41:03.972118 LZMA decompressing kernel-1 to 0x821a6718
9987 00:41:03.972648
9988 00:41:03.975958 LZMA decompressing kernel-1 to 0x40000000
9989 00:41:05.591576
9990 00:41:05.592076 jumping to kernel
9991 00:41:05.593776 end: 2.2.4 bootloader-commands (duration 00:00:22) [common]
9992 00:41:05.594323 start: 2.2.5 auto-login-action (timeout 00:04:06) [common]
9993 00:41:05.594712 Setting prompt string to ['Linux version [0-9]']
9994 00:41:05.595066 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9995 00:41:05.595415 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
9996 00:41:05.641962
9997 00:41:05.645406 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
9998 00:41:05.649249 start: 2.2.5.1 login-action (timeout 00:04:06) [common]
9999 00:41:05.649813 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10000 00:41:05.650196 Setting prompt string to []
10001 00:41:05.650675 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10002 00:41:05.651034 Using line separator: #'\n'#
10003 00:41:05.651354 No login prompt set.
10004 00:41:05.651685 Parsing kernel messages
10005 00:41:05.651998 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10006 00:41:05.652532 [login-action] Waiting for messages, (timeout 00:04:06)
10007 00:41:05.652867 Waiting using forced prompt support (timeout 00:02:03)
10008 00:41:05.668585 [ 0.000000] Linux version 6.1.92-cip22 (KernelCI@build-j232175-arm64-gcc-10-defconfig-arm64-chromebook-7lg8d) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sun Jun 16 00:28:47 UTC 2024
10009 00:41:05.671903 [ 0.000000] random: crng init done
10010 00:41:05.678723 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10011 00:41:05.682251 [ 0.000000] efi: UEFI not found.
10012 00:41:05.688283 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10013 00:41:05.695245 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10014 00:41:05.705213 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10015 00:41:05.714963 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10016 00:41:05.721228 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10017 00:41:05.727757 [ 0.000000] printk: bootconsole [mtk8250] enabled
10018 00:41:05.734373 [ 0.000000] NUMA: No NUMA configuration found
10019 00:41:05.741188 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000013fffffff]
10020 00:41:05.744691 [ 0.000000] NUMA: NODE_DATA [mem 0x13f7d5a00-0x13f7d7fff]
10021 00:41:05.747600 [ 0.000000] Zone ranges:
10022 00:41:05.754343 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10023 00:41:05.757321 [ 0.000000] DMA32 empty
10024 00:41:05.764128 [ 0.000000] Normal [mem 0x0000000100000000-0x000000013fffffff]
10025 00:41:05.767497 [ 0.000000] Movable zone start for each node
10026 00:41:05.770614 [ 0.000000] Early memory node ranges
10027 00:41:05.777323 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10028 00:41:05.783950 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10029 00:41:05.790463 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10030 00:41:05.797081 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10031 00:41:05.803542 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000013fffffff]
10032 00:41:05.810152 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000013fffffff]
10033 00:41:05.840279 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10034 00:41:05.846660 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10035 00:41:05.853397 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10036 00:41:05.856675 [ 0.000000] psci: probing for conduit method from DT.
10037 00:41:05.863200 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10038 00:41:05.866402 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10039 00:41:05.873273 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10040 00:41:05.876668 [ 0.000000] psci: SMC Calling Convention v1.2
10041 00:41:05.883236 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10042 00:41:05.886629 [ 0.000000] Detected VIPT I-cache on CPU0
10043 00:41:05.893126 [ 0.000000] CPU features: detected: GIC system register CPU interface
10044 00:41:05.899778 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10045 00:41:05.906182 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10046 00:41:05.912636 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10047 00:41:05.919182 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10048 00:41:05.929524 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10049 00:41:05.932631 [ 0.000000] alternatives: applying boot alternatives
10050 00:41:05.939437 [ 0.000000] Fallback order for Node 0: 0
10051 00:41:05.945855 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1031424
10052 00:41:05.949391 [ 0.000000] Policy zone: Normal
10053 00:41:05.972068 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14368404/extract-nfsrootfs-_3z5vp51,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10054 00:41:05.981982 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10055 00:41:05.991895 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10056 00:41:05.998509 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
10057 00:41:06.005044 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10058 00:41:06.011511 <6>[ 0.000000] software IO TLB: area num 8.
10059 00:41:06.067851 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10060 00:41:06.148319 <6>[ 0.000000] Memory: 3831352K/4191232K available (18112K kernel code, 4120K rwdata, 22644K rodata, 8512K init, 616K bss, 327112K reserved, 32768K cma-reserved)
10061 00:41:06.154968 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10062 00:41:06.161663 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10063 00:41:06.165100 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10064 00:41:06.171647 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10065 00:41:06.178301 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10066 00:41:06.181599 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10067 00:41:06.191360 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10068 00:41:06.197930 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10069 00:41:06.204868 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10070 00:41:06.211133 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10071 00:41:06.214308 <6>[ 0.000000] GICv3: 608 SPIs implemented
10072 00:41:06.217861 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10073 00:41:06.224306 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10074 00:41:06.227502 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10075 00:41:06.234349 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10076 00:41:06.248075 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10077 00:41:06.257885 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10078 00:41:06.267968 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10079 00:41:06.274900 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10080 00:41:06.288289 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10081 00:41:06.294838 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10082 00:41:06.301259 <6>[ 0.009231] Console: colour dummy device 80x25
10083 00:41:06.311440 <6>[ 0.013958] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10084 00:41:06.317808 <6>[ 0.024463] pid_max: default: 32768 minimum: 301
10085 00:41:06.321053 <6>[ 0.029334] LSM: Security Framework initializing
10086 00:41:06.327674 <6>[ 0.034246] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10087 00:41:06.337779 <6>[ 0.041901] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10088 00:41:06.344630 <6>[ 0.051081] cblist_init_generic: Setting adjustable number of callback queues.
10089 00:41:06.351087 <6>[ 0.058572] cblist_init_generic: Setting shift to 3 and lim to 1.
10090 00:41:06.361517 <6>[ 0.064950] cblist_init_generic: Setting adjustable number of callback queues.
10091 00:41:06.364459 <6>[ 0.072422] cblist_init_generic: Setting shift to 3 and lim to 1.
10092 00:41:06.371727 <6>[ 0.078823] rcu: Hierarchical SRCU implementation.
10093 00:41:06.377833 <6>[ 0.083839] rcu: Max phase no-delay instances is 1000.
10094 00:41:06.384460 <6>[ 0.090866] EFI services will not be available.
10095 00:41:06.387704 <6>[ 0.095816] smp: Bringing up secondary CPUs ...
10096 00:41:06.395320 <6>[ 0.100861] Detected VIPT I-cache on CPU1
10097 00:41:06.401824 <6>[ 0.100931] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10098 00:41:06.408727 <6>[ 0.100961] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10099 00:41:06.411985 <6>[ 0.101288] Detected VIPT I-cache on CPU2
10100 00:41:06.418439 <6>[ 0.101338] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10101 00:41:06.425236 <6>[ 0.101354] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10102 00:41:06.431858 <6>[ 0.101612] Detected VIPT I-cache on CPU3
10103 00:41:06.438182 <6>[ 0.101660] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10104 00:41:06.445053 <6>[ 0.101673] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10105 00:41:06.448264 <6>[ 0.101973] CPU features: detected: Spectre-v4
10106 00:41:06.454878 <6>[ 0.101979] CPU features: detected: Spectre-BHB
10107 00:41:06.458243 <6>[ 0.101984] Detected PIPT I-cache on CPU4
10108 00:41:06.465009 <6>[ 0.102042] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10109 00:41:06.471481 <6>[ 0.102058] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10110 00:41:06.478066 <6>[ 0.102350] Detected PIPT I-cache on CPU5
10111 00:41:06.485058 <6>[ 0.102413] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10112 00:41:06.491368 <6>[ 0.102429] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10113 00:41:06.494944 <6>[ 0.102708] Detected PIPT I-cache on CPU6
10114 00:41:06.501480 <6>[ 0.102770] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10115 00:41:06.507896 <6>[ 0.102786] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10116 00:41:06.514301 <6>[ 0.103085] Detected PIPT I-cache on CPU7
10117 00:41:06.521057 <6>[ 0.103151] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10118 00:41:06.527788 <6>[ 0.103167] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10119 00:41:06.531182 <6>[ 0.103214] smp: Brought up 1 node, 8 CPUs
10120 00:41:06.537617 <6>[ 0.244617] SMP: Total of 8 processors activated.
10121 00:41:06.541264 <6>[ 0.249538] CPU features: detected: 32-bit EL0 Support
10122 00:41:06.550886 <6>[ 0.254934] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10123 00:41:06.557691 <6>[ 0.263735] CPU features: detected: Common not Private translations
10124 00:41:06.564243 <6>[ 0.270210] CPU features: detected: CRC32 instructions
10125 00:41:06.567762 <6>[ 0.275562] CPU features: detected: RCpc load-acquire (LDAPR)
10126 00:41:06.574300 <6>[ 0.281522] CPU features: detected: LSE atomic instructions
10127 00:41:06.581240 <6>[ 0.287304] CPU features: detected: Privileged Access Never
10128 00:41:06.587691 <6>[ 0.293083] CPU features: detected: RAS Extension Support
10129 00:41:06.594046 <6>[ 0.298692] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10130 00:41:06.597205 <6>[ 0.305956] CPU: All CPU(s) started at EL2
10131 00:41:06.604174 <6>[ 0.310300] alternatives: applying system-wide alternatives
10132 00:41:06.612712 <6>[ 0.320241] devtmpfs: initialized
10133 00:41:06.626917 <6>[ 0.328428] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10134 00:41:06.633597 <6>[ 0.338388] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10135 00:41:06.640141 <6>[ 0.346442] pinctrl core: initialized pinctrl subsystem
10136 00:41:06.643790 <6>[ 0.353133] DMI not present or invalid.
10137 00:41:06.650333 <6>[ 0.357536] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10138 00:41:06.659895 <6>[ 0.364385] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
10139 00:41:06.666800 <6>[ 0.371833] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10140 00:41:06.676563 <6>[ 0.379926] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10141 00:41:06.680013 <6>[ 0.388081] audit: initializing netlink subsys (disabled)
10142 00:41:06.689759 <5>[ 0.393774] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10143 00:41:06.696294 <6>[ 0.394486] thermal_sys: Registered thermal governor 'step_wise'
10144 00:41:06.703313 <6>[ 0.401741] thermal_sys: Registered thermal governor 'power_allocator'
10145 00:41:06.706401 <6>[ 0.407997] cpuidle: using governor menu
10146 00:41:06.712959 <6>[ 0.418956] NET: Registered PF_QIPCRTR protocol family
10147 00:41:06.719385 <6>[ 0.424439] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10148 00:41:06.723041 <6>[ 0.431541] ASID allocator initialised with 32768 entries
10149 00:41:06.730038 <6>[ 0.438105] Serial: AMBA PL011 UART driver
10150 00:41:06.738941 <4>[ 0.446925] Trying to register duplicate clock ID: 134
10151 00:41:06.797024 <6>[ 0.508308] KASLR enabled
10152 00:41:06.811803 <6>[ 0.515990] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10153 00:41:06.818029 <6>[ 0.523003] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10154 00:41:06.824532 <6>[ 0.529492] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10155 00:41:06.831077 <6>[ 0.536498] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10156 00:41:06.838102 <6>[ 0.542985] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10157 00:41:06.844290 <6>[ 0.549991] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10158 00:41:06.850772 <6>[ 0.556478] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10159 00:41:06.857487 <6>[ 0.563485] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10160 00:41:06.860983 <6>[ 0.570924] ACPI: Interpreter disabled.
10161 00:41:06.869680 <6>[ 0.577331] iommu: Default domain type: Translated
10162 00:41:06.876112 <6>[ 0.582479] iommu: DMA domain TLB invalidation policy: strict mode
10163 00:41:06.879740 <5>[ 0.589136] SCSI subsystem initialized
10164 00:41:06.886104 <6>[ 0.593385] usbcore: registered new interface driver usbfs
10165 00:41:06.892734 <6>[ 0.599117] usbcore: registered new interface driver hub
10166 00:41:06.895828 <6>[ 0.604669] usbcore: registered new device driver usb
10167 00:41:06.902791 <6>[ 0.610783] pps_core: LinuxPPS API ver. 1 registered
10168 00:41:06.913180 <6>[ 0.615977] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10169 00:41:06.915986 <6>[ 0.625322] PTP clock support registered
10170 00:41:06.919308 <6>[ 0.629565] EDAC MC: Ver: 3.0.0
10171 00:41:06.926945 <6>[ 0.634738] FPGA manager framework
10172 00:41:06.933397 <6>[ 0.638413] Advanced Linux Sound Architecture Driver Initialized.
10173 00:41:06.936711 <6>[ 0.645188] vgaarb: loaded
10174 00:41:06.943563 <6>[ 0.648338] clocksource: Switched to clocksource arch_sys_counter
10175 00:41:06.946526 <5>[ 0.654780] VFS: Disk quotas dquot_6.6.0
10176 00:41:06.953203 <6>[ 0.658966] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10177 00:41:06.956253 <6>[ 0.666153] pnp: PnP ACPI: disabled
10178 00:41:06.964984 <6>[ 0.672859] NET: Registered PF_INET protocol family
10179 00:41:06.971294 <6>[ 0.678247] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
10180 00:41:06.983833 <6>[ 0.688268] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
10181 00:41:06.994123 <6>[ 0.697053] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10182 00:41:07.000120 <6>[ 0.705019] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
10183 00:41:07.006956 <6>[ 0.713420] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear)
10184 00:41:07.017839 <6>[ 0.722077] TCP: Hash tables configured (established 32768 bind 32768)
10185 00:41:07.024057 <6>[ 0.728937] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear)
10186 00:41:07.030693 <6>[ 0.735956] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear)
10187 00:41:07.037152 <6>[ 0.743478] NET: Registered PF_UNIX/PF_LOCAL protocol family
10188 00:41:07.043901 <6>[ 0.749620] RPC: Registered named UNIX socket transport module.
10189 00:41:07.046891 <6>[ 0.755773] RPC: Registered udp transport module.
10190 00:41:07.053480 <6>[ 0.760706] RPC: Registered tcp transport module.
10191 00:41:07.060269 <6>[ 0.765636] RPC: Registered tcp NFSv4.1 backchannel transport module.
10192 00:41:07.063509 <6>[ 0.772305] PCI: CLS 0 bytes, default 64
10193 00:41:07.066865 <6>[ 0.776639] Unpacking initramfs...
10194 00:41:07.091737 <6>[ 0.796428] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10195 00:41:07.101803 <6>[ 0.805079] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10196 00:41:07.105123 <6>[ 0.813915] kvm [1]: IPA Size Limit: 40 bits
10197 00:41:07.111703 <6>[ 0.818441] kvm [1]: GICv3: no GICV resource entry
10198 00:41:07.115181 <6>[ 0.823462] kvm [1]: disabling GICv2 emulation
10199 00:41:07.121348 <6>[ 0.828146] kvm [1]: GIC system register CPU interface enabled
10200 00:41:07.124849 <6>[ 0.834302] kvm [1]: vgic interrupt IRQ18
10201 00:41:07.131323 <6>[ 0.838652] kvm [1]: VHE mode initialized successfully
10202 00:41:07.138063 <5>[ 0.845025] Initialise system trusted keyrings
10203 00:41:07.144461 <6>[ 0.849823] workingset: timestamp_bits=42 max_order=20 bucket_order=0
10204 00:41:07.152068 <6>[ 0.859841] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10205 00:41:07.158734 <5>[ 0.866233] NFS: Registering the id_resolver key type
10206 00:41:07.161699 <5>[ 0.871535] Key type id_resolver registered
10207 00:41:07.168736 <5>[ 0.875950] Key type id_legacy registered
10208 00:41:07.175327 <6>[ 0.880235] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10209 00:41:07.181728 <6>[ 0.887156] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10210 00:41:07.188657 <6>[ 0.894861] 9p: Installing v9fs 9p2000 file system support
10211 00:41:07.225604 <5>[ 0.933615] Key type asymmetric registered
10212 00:41:07.228900 <5>[ 0.937946] Asymmetric key parser 'x509' registered
10213 00:41:07.238876 <6>[ 0.943089] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10214 00:41:07.242083 <6>[ 0.950702] io scheduler mq-deadline registered
10215 00:41:07.245514 <6>[ 0.955460] io scheduler kyber registered
10216 00:41:07.264653 <6>[ 0.972452] EINJ: ACPI disabled.
10217 00:41:07.296785 <4>[ 0.998222] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10218 00:41:07.306884 <4>[ 1.008866] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10219 00:41:07.321945 <6>[ 1.029636] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10220 00:41:07.329547 <6>[ 1.037581] printk: console [ttyS0] disabled
10221 00:41:07.357923 <6>[ 1.062223] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10222 00:41:07.364287 <6>[ 1.071708] printk: console [ttyS0] enabled
10223 00:41:07.368016 <6>[ 1.071708] printk: console [ttyS0] enabled
10224 00:41:07.374505 <6>[ 1.080601] printk: bootconsole [mtk8250] disabled
10225 00:41:07.377667 <6>[ 1.080601] printk: bootconsole [mtk8250] disabled
10226 00:41:07.384369 <6>[ 1.091681] SuperH (H)SCI(F) driver initialized
10227 00:41:07.387675 <6>[ 1.096954] msm_serial: driver initialized
10228 00:41:07.401445 <6>[ 1.105887] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10229 00:41:07.411593 <6>[ 1.114433] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10230 00:41:07.417922 <6>[ 1.122975] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10231 00:41:07.427793 <6>[ 1.131602] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10232 00:41:07.437224 <6>[ 1.140308] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10233 00:41:07.444084 <6>[ 1.149022] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10234 00:41:07.454116 <6>[ 1.157562] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10235 00:41:07.460841 <6>[ 1.166356] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10236 00:41:07.470965 <6>[ 1.174897] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10237 00:41:07.482424 <6>[ 1.190303] loop: module loaded
10238 00:41:07.488663 <6>[ 1.196263] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10239 00:41:07.511487 <4>[ 1.219474] mtk-pmic-keys: Failed to locate of_node [id: -1]
10240 00:41:07.518298 <6>[ 1.226266] megasas: 07.719.03.00-rc1
10241 00:41:07.527658 <6>[ 1.235856] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10242 00:41:07.535980 <6>[ 1.243727] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10243 00:41:07.552466 <6>[ 1.260436] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10244 00:41:07.608933 <6>[ 1.310185] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2
10245 00:41:07.850871 <6>[ 1.558952] Freeing initrd memory: 18292K
10246 00:41:07.862297 <6>[ 1.570646] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10247 00:41:07.873274 <6>[ 1.581482] tun: Universal TUN/TAP device driver, 1.6
10248 00:41:07.876697 <6>[ 1.587535] thunder_xcv, ver 1.0
10249 00:41:07.880333 <6>[ 1.591039] thunder_bgx, ver 1.0
10250 00:41:07.883580 <6>[ 1.594538] nicpf, ver 1.0
10251 00:41:07.893960 <6>[ 1.598544] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10252 00:41:07.897302 <6>[ 1.606020] hns3: Copyright (c) 2017 Huawei Corporation.
10253 00:41:07.900656 <6>[ 1.611608] hclge is initializing
10254 00:41:07.907312 <6>[ 1.615187] e1000: Intel(R) PRO/1000 Network Driver
10255 00:41:07.914188 <6>[ 1.620318] e1000: Copyright (c) 1999-2006 Intel Corporation.
10256 00:41:07.917084 <6>[ 1.626330] e1000e: Intel(R) PRO/1000 Network Driver
10257 00:41:07.924016 <6>[ 1.631546] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10258 00:41:07.930646 <6>[ 1.637731] igb: Intel(R) Gigabit Ethernet Network Driver
10259 00:41:07.937104 <6>[ 1.643382] igb: Copyright (c) 2007-2014 Intel Corporation.
10260 00:41:07.943890 <6>[ 1.649222] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10261 00:41:07.950473 <6>[ 1.655739] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10262 00:41:07.953511 <6>[ 1.662199] sky2: driver version 1.30
10263 00:41:07.960433 <6>[ 1.667127] usbcore: registered new device driver r8152-cfgselector
10264 00:41:07.967022 <6>[ 1.673664] usbcore: registered new interface driver r8152
10265 00:41:07.970240 <6>[ 1.679475] VFIO - User Level meta-driver version: 0.3
10266 00:41:07.979719 <6>[ 1.687684] usbcore: registered new interface driver usb-storage
10267 00:41:07.986030 <6>[ 1.694126] usbcore: registered new device driver onboard-usb-hub
10268 00:41:07.995222 <6>[ 1.703240] mt6397-rtc mt6359-rtc: registered as rtc0
10269 00:41:08.004884 <6>[ 1.708704] mt6397-rtc mt6359-rtc: setting system clock to 2024-06-16T00:41:07 UTC (1718498467)
10270 00:41:08.008193 <6>[ 1.718263] i2c_dev: i2c /dev entries driver
10271 00:41:08.022442 <4>[ 1.730169] cpu cpu0: supply cpu not found, using dummy regulator
10272 00:41:08.028507 <4>[ 1.736593] cpu cpu1: supply cpu not found, using dummy regulator
10273 00:41:08.035625 <4>[ 1.742995] cpu cpu2: supply cpu not found, using dummy regulator
10274 00:41:08.042196 <4>[ 1.749399] cpu cpu3: supply cpu not found, using dummy regulator
10275 00:41:08.048623 <4>[ 1.755793] cpu cpu4: supply cpu not found, using dummy regulator
10276 00:41:08.055150 <4>[ 1.762209] cpu cpu5: supply cpu not found, using dummy regulator
10277 00:41:08.061844 <4>[ 1.768603] cpu cpu6: supply cpu not found, using dummy regulator
10278 00:41:08.068504 <4>[ 1.774996] cpu cpu7: supply cpu not found, using dummy regulator
10279 00:41:08.088419 <6>[ 1.796620] cpu cpu0: EM: created perf domain
10280 00:41:08.091788 <6>[ 1.801550] cpu cpu4: EM: created perf domain
10281 00:41:08.099302 <6>[ 1.807053] sdhci: Secure Digital Host Controller Interface driver
10282 00:41:08.105575 <6>[ 1.813486] sdhci: Copyright(c) Pierre Ossman
10283 00:41:08.112249 <6>[ 1.818388] Synopsys Designware Multimedia Card Interface Driver
10284 00:41:08.118826 <6>[ 1.824993] sdhci-pltfm: SDHCI platform and OF driver helper
10285 00:41:08.122509 <6>[ 1.825102] mmc0: CQHCI version 5.10
10286 00:41:08.128785 <6>[ 1.835275] ledtrig-cpu: registered to indicate activity on CPUs
10287 00:41:08.135403 <6>[ 1.842335] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10288 00:41:08.142176 <6>[ 1.849369] usbcore: registered new interface driver usbhid
10289 00:41:08.145291 <6>[ 1.855190] usbhid: USB HID core driver
10290 00:41:08.152088 <6>[ 1.859373] spi_master spi0: will run message pump with realtime priority
10291 00:41:08.194596 <6>[ 1.896079] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10292 00:41:08.212696 <6>[ 1.911138] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10293 00:41:08.216302 <3>[ 1.919664] mtk-msdc 11f60000.mmc: phase error: [map:0]
10294 00:41:08.223480 <3>[ 1.930035] mtk-msdc 11f60000.mmc: Failed to get DLY1 delay!
10295 00:41:08.229624 <3>[ 1.935961] mtk-msdc 11f60000.mmc: Failed to tuning DS pin delay!
10296 00:41:08.233536 <3>[ 1.942324] mmc0: error -5 whilst initialising MMC card
10297 00:41:08.239963 <6>[ 1.942471] cros-ec-spi spi0.0: Chrome EC device registered
10298 00:41:08.260933 <6>[ 1.965797] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10299 00:41:08.268097 <6>[ 1.976078] NET: Registered PF_PACKET protocol family
10300 00:41:08.271304 <6>[ 1.981476] 9pnet: Installing 9P2000 support
10301 00:41:08.277953 <5>[ 1.986031] Key type dns_resolver registered
10302 00:41:08.281214 <6>[ 1.991024] registered taskstats version 1
10303 00:41:08.288067 <5>[ 1.995399] Loading compiled-in X.509 certificates
10304 00:41:08.315416 <4>[ 2.016725] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10305 00:41:08.325059 <4>[ 2.027540] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10306 00:41:08.343456 <6>[ 2.051511] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10307 00:41:08.349966 <6>[ 2.058301] xhci-mtk 11200000.usb: xHCI Host Controller
10308 00:41:08.356704 <6>[ 2.063802] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10309 00:41:08.363440 <3>[ 2.068368] mtk-msdc 11f60000.mmc: phase error: [map:0]
10310 00:41:08.373103 <6>[ 2.071663] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10311 00:41:08.380048 <3>[ 2.076932] mtk-msdc 11f60000.mmc: Failed to get DLY1 delay!
10312 00:41:08.386432 <6>[ 2.086352] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10313 00:41:08.390007 <3>[ 2.092223] mtk-msdc 11f60000.mmc: Failed to tuning DS pin delay!
10314 00:41:08.396853 <6>[ 2.098401] xhci-mtk 11200000.usb: xHCI Host Controller
10315 00:41:08.403453 <3>[ 2.104582] mmc0: error -5 whilst initialising MMC card
10316 00:41:08.409857 <6>[ 2.110060] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10317 00:41:08.417120 <6>[ 2.123181] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10318 00:41:08.423277 <6>[ 2.130958] hub 1-0:1.0: USB hub found
10319 00:41:08.427056 <6>[ 2.134977] hub 1-0:1.0: 1 port detected
10320 00:41:08.433776 <6>[ 2.139240] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10321 00:41:08.439911 <6>[ 2.147952] hub 2-0:1.0: USB hub found
10322 00:41:08.443442 <6>[ 2.151969] hub 2-0:1.0: 1 port detected
10323 00:41:08.450814 <6>[ 2.158708] mtk-msdc 11f70000.mmc: Got CD GPIO
10324 00:41:08.462671 <6>[ 2.167524] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10325 00:41:08.472965 <6>[ 2.175907] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10326 00:41:08.479401 <6>[ 2.184248] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10327 00:41:08.489143 <6>[ 2.192585] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10328 00:41:08.495954 <6>[ 2.200922] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10329 00:41:08.505850 <6>[ 2.209260] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10330 00:41:08.512724 <6>[ 2.217600] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10331 00:41:08.519227 <6>[ 2.223893] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x17c14
10332 00:41:08.526701 <6>[ 2.225937] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10333 00:41:08.535523 <6>[ 2.225940] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10334 00:41:08.542593 <6>[ 2.225943] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10335 00:41:08.552148 <6>[ 2.225945] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10336 00:41:08.558983 <6>[ 2.225948] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10337 00:41:08.569033 <6>[ 2.225950] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10338 00:41:08.576178 <6>[ 2.225952] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10339 00:41:08.585536 <6>[ 2.225954] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10340 00:41:08.592369 <6>[ 2.226276] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10341 00:41:08.599462 <6>[ 2.305552] mmc0: Command Queue Engine enabled
10342 00:41:08.602768 <6>[ 2.305873] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10343 00:41:08.608807 <6>[ 2.310274] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10344 00:41:08.615897 <6>[ 2.317016] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10345 00:41:08.622294 <6>[ 2.324108] mmcblk0: mmc0:0001 DA4064 58.2 GiB
10346 00:41:08.628747 <6>[ 2.330215] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10347 00:41:08.635184 <6>[ 2.340516] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10348 00:41:08.641558 <6>[ 2.341759] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10349 00:41:08.644888 <6>[ 2.348619] mmcblk0boot0: mmc0:0001 DA4064 4.00 MiB
10350 00:41:08.654706 <6>[ 2.354176] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10351 00:41:08.661499 <6>[ 2.359844] mmcblk0boot1: mmc0:0001 DA4064 4.00 MiB
10352 00:41:08.668126 <6>[ 2.368363] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10353 00:41:08.678238 <6>[ 2.368367] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10354 00:41:08.687936 <6>[ 2.368370] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10355 00:41:08.697613 <6>[ 2.368374] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10356 00:41:08.704195 <6>[ 2.374221] mmcblk0rpmb: mmc0:0001 DA4064 16.0 MiB, chardev (507:0)
10357 00:41:08.714351 <6>[ 2.382702] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10358 00:41:08.723991 <6>[ 2.382706] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10359 00:41:08.730918 <6>[ 2.382709] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10360 00:41:08.740512 <6>[ 2.445132] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10361 00:41:08.750610 <6>[ 2.454425] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10362 00:41:08.760503 <6>[ 2.464585] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10363 00:41:08.771416 <6>[ 2.476376] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10364 00:41:08.779844 <6>[ 2.488111] Trying to probe devices needed for running init ...
10365 00:41:08.790420 <3>[ 2.495439] mt8192-audio 11210000.syscon:mt8192-afe-pcm: could not get audiosys reset:-517
10366 00:41:08.832128 <6>[ 2.536869] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10367 00:41:08.859781 <6>[ 2.568058] hub 2-1:1.0: USB hub found
10368 00:41:08.863266 <6>[ 2.572509] hub 2-1:1.0: 3 ports detected
10369 00:41:08.873434 <6>[ 2.581356] hub 2-1:1.0: USB hub found
10370 00:41:08.876313 <6>[ 2.585833] hub 2-1:1.0: 3 ports detected
10371 00:41:08.983693 <6>[ 2.688611] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10372 00:41:09.138472 <6>[ 2.846221] hub 1-1:1.0: USB hub found
10373 00:41:09.141239 <6>[ 2.850682] hub 1-1:1.0: 4 ports detected
10374 00:41:09.154525 <6>[ 2.862711] hub 1-1:1.0: USB hub found
10375 00:41:09.157648 <6>[ 2.867130] hub 1-1:1.0: 4 ports detected
10376 00:41:09.215846 <6>[ 2.920727] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10377 00:41:09.324347 <6>[ 3.029026] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10378 00:41:09.355751 <4>[ 3.060780] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10379 00:41:09.366106 <4>[ 3.069876] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10380 00:41:09.405479 <6>[ 3.113510] r8152 2-1.3:1.0 eth0: v1.12.13
10381 00:41:09.479690 <6>[ 3.184641] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10382 00:41:09.612462 <6>[ 3.320449] hub 1-1.4:1.0: USB hub found
10383 00:41:09.615602 <6>[ 3.325109] hub 1-1.4:1.0: 2 ports detected
10384 00:41:09.628611 <6>[ 3.336142] hub 1-1.4:1.0: USB hub found
10385 00:41:09.631787 <6>[ 3.340747] hub 1-1.4:1.0: 2 ports detected
10386 00:41:09.927735 <6>[ 3.632693] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10387 00:41:10.123334 <6>[ 3.828487] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10388 00:41:11.019096 <6>[ 4.727500] r8152 2-1.3:1.0 eth0: carrier on
10389 00:41:13.671627 <5>[ 4.756463] Sending DHCP requests .., OK
10390 00:41:13.677836 <6>[ 7.384737] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.16
10391 00:41:13.681453 <6>[ 7.393026] IP-Config: Complete:
10392 00:41:13.694482 <6>[ 7.396522] device=eth0, hwaddr=00:e0:4c:68:03:bd, ipaddr=192.168.201.16, mask=255.255.255.0, gw=192.168.201.1
10393 00:41:13.701239 <6>[ 7.407246] host=mt8192-asurada-spherion-r0-cbg-4, domain=lava-rack, nis-domain=(none)
10394 00:41:13.708175 <6>[ 7.415866] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10395 00:41:13.714297 <6>[ 7.415875] nameserver0=192.168.201.1
10396 00:41:13.717543 <6>[ 7.428011] clk: Disabling unused clocks
10397 00:41:13.721692 <6>[ 7.433712] ALSA device list:
10398 00:41:13.727929 <6>[ 7.436952] No soundcards found.
10399 00:41:13.735099 <6>[ 7.444273] Freeing unused kernel memory: 8512K
10400 00:41:13.738524 <6>[ 7.449275] Run /init as init process
10401 00:41:13.747326 Loading, please wait...
10402 00:41:13.776351 Starting systemd-udevd version 252.22-1~deb12u1
10403 00:41:14.016653 <6>[ 7.722598] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10404 00:41:14.023656 <6>[ 7.731693] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10405 00:41:14.033435 <6>[ 7.737474] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10406 00:41:14.043607 <6>[ 7.739304] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10407 00:41:14.050497 <6>[ 7.747320] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10408 00:41:14.060262 <6>[ 7.755962] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10409 00:41:14.067138 <4>[ 7.764047] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10410 00:41:14.073453 <6>[ 7.764780] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10411 00:41:14.080320 <6>[ 7.768350] remoteproc remoteproc0: scp is available
10412 00:41:14.086853 <6>[ 7.768405] remoteproc remoteproc0: powering up scp
10413 00:41:14.093543 <6>[ 7.768409] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10414 00:41:14.100279 <6>[ 7.768428] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10415 00:41:14.107242 <6>[ 7.779349] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10416 00:41:14.113732 <3>[ 7.781000] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10417 00:41:14.124205 <3>[ 7.781008] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10418 00:41:14.130704 <3>[ 7.781011] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10419 00:41:14.141046 <3>[ 7.781056] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10420 00:41:14.148139 <3>[ 7.781059] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10421 00:41:14.158014 <3>[ 7.781062] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10422 00:41:14.164378 <3>[ 7.781066] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10423 00:41:14.171198 <3>[ 7.781068] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10424 00:41:14.180904 <3>[ 7.781082] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10425 00:41:14.187636 <3>[ 7.781103] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10426 00:41:14.197490 <3>[ 7.781107] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10427 00:41:14.204294 <3>[ 7.781110] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10428 00:41:14.214188 <3>[ 7.781127] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10429 00:41:14.220887 <3>[ 7.781130] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10430 00:41:14.230608 <3>[ 7.781132] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10431 00:41:14.237126 <3>[ 7.781135] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10432 00:41:14.247182 <3>[ 7.781138] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10433 00:41:14.253537 <3>[ 7.781155] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10434 00:41:14.260175 <6>[ 7.782085] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10435 00:41:14.266612 <6>[ 7.802685] mc: Linux media interface: v0.10
10436 00:41:14.273350 <4>[ 7.803129] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10437 00:41:14.279861 <4>[ 7.803278] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10438 00:41:14.289688 <6>[ 7.807947] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10439 00:41:14.296324 <4>[ 7.808147] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10440 00:41:14.303065 <4>[ 7.808147] Fallback method does not support PEC.
10441 00:41:14.310007 <3>[ 7.822329] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10442 00:41:14.319625 <6>[ 7.829923] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10443 00:41:14.326401 <6>[ 7.838786] videodev: Linux video capture interface: v2.00
10444 00:41:14.333175 <6>[ 7.845850] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10445 00:41:14.339541 <6>[ 7.845861] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10446 00:41:14.349687 <6>[ 7.845869] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10447 00:41:14.358945 <3>[ 7.858540] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10448 00:41:14.365622 <6>[ 7.894135] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10449 00:41:14.372163 <6>[ 7.894179] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10450 00:41:14.379309 <6>[ 7.894187] remoteproc remoteproc0: remote processor scp is now up
10451 00:41:14.385448 <6>[ 7.897764] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10452 00:41:14.395975 <6>[ 7.906219] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10453 00:41:14.405253 <6>[ 7.906938] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10454 00:41:14.412279 <6>[ 7.910704] pci_bus 0000:00: root bus resource [bus 00-ff]
10455 00:41:14.421921 <6>[ 7.919393] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10456 00:41:14.428639 <6>[ 7.920005] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10457 00:41:14.438692 <6>[ 7.922033] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10458 00:41:14.445094 <6>[ 7.926861] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10459 00:41:14.448164 <6>[ 7.976025] Bluetooth: Core ver 2.22
10460 00:41:14.458320 <6>[ 7.979974] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10461 00:41:14.465000 <6>[ 7.987642] NET: Registered PF_BLUETOOTH protocol family
10462 00:41:14.471422 <6>[ 7.994523] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10463 00:41:14.478886 <6>[ 7.995450] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10464 00:41:14.491443 <6>[ 7.996674] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10465 00:41:14.494427 <6>[ 7.996825] usbcore: registered new interface driver uvcvideo
10466 00:41:14.501258 <6>[ 8.002397] Bluetooth: HCI device and connection manager initialized
10467 00:41:14.510880 <6>[ 8.016044] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10468 00:41:14.514326 <6>[ 8.024812] Bluetooth: HCI socket layer initialized
10469 00:41:14.520848 <6>[ 8.032775] pci 0000:00:00.0: supports D1 D2
10470 00:41:14.524472 <6>[ 8.038439] Bluetooth: L2CAP socket layer initialized
10471 00:41:14.530803 <6>[ 8.046254] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10472 00:41:14.541028 <6>[ 8.047211] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10473 00:41:14.547311 <6>[ 8.047347] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10474 00:41:14.550470 <6>[ 8.054079] Bluetooth: SCO socket layer initialized
10475 00:41:14.557460 <6>[ 8.120697] usbcore: registered new interface driver btusb
10476 00:41:14.567811 <4>[ 8.121732] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10477 00:41:14.573921 <3>[ 8.121746] Bluetooth: hci0: Failed to load firmware file (-2)
10478 00:41:14.580880 <3>[ 8.121751] Bluetooth: hci0: Failed to set up firmware (-2)
10479 00:41:14.590722 <4>[ 8.121756] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10480 00:41:14.597209 <6>[ 8.126015] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10481 00:41:14.603556 <6>[ 8.310110] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10482 00:41:14.610130 <6>[ 8.317594] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10483 00:41:14.620201 <6>[ 8.325136] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10484 00:41:14.623546 <6>[ 8.332712] pci 0000:01:00.0: supports D1 D2
10485 00:41:14.630247 <6>[ 8.337232] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10486 00:41:14.646754 <6>[ 8.352494] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10487 00:41:14.653187 <6>[ 8.359404] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10488 00:41:14.659682 <6>[ 8.367483] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10489 00:41:14.669809 <6>[ 8.375479] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10490 00:41:14.676252 <6>[ 8.383478] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10491 00:41:14.686191 <6>[ 8.391479] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10492 00:41:14.689461 <6>[ 8.399478] pci 0000:00:00.0: PCI bridge to [bus 01]
10493 00:41:14.699598 <6>[ 8.404694] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10494 00:41:14.706355 <6>[ 8.412822] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10495 00:41:14.712795 <6>[ 8.419615] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10496 00:41:14.719320 <6>[ 8.426344] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10497 00:41:14.741549 <5>[ 8.447059] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10498 00:41:14.759803 <5>[ 8.465320] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10499 00:41:14.766040 <5>[ 8.473316] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10500 00:41:14.776113 <4>[ 8.481817] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10501 00:41:14.782589 <6>[ 8.490710] cfg80211: failed to load regulatory.db
10502 00:41:14.841268 <6>[ 8.546693] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10503 00:41:14.847582 <6>[ 8.554251] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10504 00:41:14.872560 <6>[ 8.581200] mt7921e 0000:01:00.0: ASIC revision: 79610010
10505 00:41:14.977032 <6>[ 8.682226] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10506 00:41:14.980144 <6>[ 8.682226]
10507 00:41:14.990334 Begin: Loading essential drivers ... done.
10508 00:41:14.993528 Begin: Running /scripts/init-premount ... done.
10509 00:41:15.000199 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10510 00:41:15.010472 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10511 00:41:15.013525 Device /sys/class/net/eth0 found
10512 00:41:15.014049 done.
10513 00:41:15.039538 Begin: Waiting up to 180 secs for any network device to become available ... done.
10514 00:41:15.099455 IP-Config: eth0 hardware address 00:e0:4c:68:03:bd mtu 1500 DHCP
10515 00:41:15.105836 IP-Config: eth0 complete (dhcp from 192.168.201.1):
10516 00:41:15.112352 address: 192.168.201.16 broadcast: 192.168.201.255 netmask: 255.255.255.0
10517 00:41:15.119397 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10518 00:41:15.125670 host : mt8192-asurada-spherion-r0-cbg-4
10519 00:41:15.132308 domain : lava-rack
10520 00:41:15.135615 rootserver: 192.168.201.1 rootpath:
10521 00:41:15.135710 filename :
10522 00:41:15.139267 done.
10523 00:41:15.142342 Begin: Running /scripts/nfs-bottom ... done.
10524 00:41:15.151411 Begin: Running /scripts/init-bottom ... done.
10525 00:41:15.247736 <6>[ 8.953678] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10526 00:41:16.445293 <6>[ 10.154875] NET: Registered PF_INET6 protocol family
10527 00:41:16.452736 <6>[ 10.162288] Segment Routing with IPv6
10528 00:41:16.456087 <6>[ 10.166275] In-situ OAM (IOAM) with IPv6
10529 00:41:16.833007 <30>[ 10.515442] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10530 00:41:16.838901 <30>[ 10.548575] systemd[1]: Detected architecture arm64.
10531 00:41:16.846633
10532 00:41:16.850026 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10533 00:41:16.850117
10534 00:41:16.876108 <30>[ 10.585721] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10535 00:41:17.935172 <30>[ 11.641540] systemd[1]: Queued start job for default target graphical.target.
10536 00:41:17.971952 <30>[ 11.677755] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10537 00:41:17.978272 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10538 00:41:18.000775 <30>[ 11.706452] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10539 00:41:18.010436 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10540 00:41:18.028413 <30>[ 11.734383] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10541 00:41:18.038440 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10542 00:41:18.056878 <30>[ 11.762811] systemd[1]: Created slice user.slice - User and Session Slice.
10543 00:41:18.063190 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10544 00:41:18.086735 <30>[ 11.789519] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10545 00:41:18.096432 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10546 00:41:18.114067 <30>[ 11.816875] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10547 00:41:18.120674 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10548 00:41:18.149213 <30>[ 11.845288] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10549 00:41:18.159100 <30>[ 11.865186] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10550 00:41:18.165803 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10551 00:41:18.183769 <30>[ 11.889011] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10552 00:41:18.192704 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10553 00:41:18.211404 <30>[ 11.917162] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10554 00:41:18.221083 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10555 00:41:18.235697 <30>[ 11.945136] systemd[1]: Reached target paths.target - Path Units.
10556 00:41:18.246193 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10557 00:41:18.263127 <30>[ 11.969097] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10558 00:41:18.269560 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10559 00:41:18.283616 <30>[ 11.992623] systemd[1]: Reached target slices.target - Slice Units.
10560 00:41:18.293091 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10561 00:41:18.307921 <30>[ 12.017109] systemd[1]: Reached target swap.target - Swaps.
10562 00:41:18.314490 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10563 00:41:18.335020 <30>[ 12.041135] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10564 00:41:18.344940 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10565 00:41:18.363368 <30>[ 12.069167] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10566 00:41:18.373524 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10567 00:41:18.393944 <30>[ 12.099863] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10568 00:41:18.403649 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10569 00:41:18.420199 <30>[ 12.126060] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10570 00:41:18.430069 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10571 00:41:18.447658 <30>[ 12.153272] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10572 00:41:18.454046 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10573 00:41:18.472034 <30>[ 12.178064] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10574 00:41:18.482134 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10575 00:41:18.501558 <30>[ 12.207571] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10576 00:41:18.511482 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10577 00:41:18.527282 <30>[ 12.233096] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10578 00:41:18.536839 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10579 00:41:18.595327 <30>[ 12.300849] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10580 00:41:18.601383 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10581 00:41:18.622746 <30>[ 12.329268] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10582 00:41:18.629409 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10583 00:41:18.654980 <30>[ 12.361266] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10584 00:41:18.661133 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10585 00:41:18.689697 <30>[ 12.389268] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10586 00:41:18.731495 <30>[ 12.437245] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10587 00:41:18.741228 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10588 00:41:18.764469 <30>[ 12.470516] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10589 00:41:18.771205 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10590 00:41:18.795708 <30>[ 12.501753] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10591 00:41:18.802295 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10592 00:41:18.826621 <30>[ 12.532706] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10593 00:41:18.833444 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10594 00:41:18.843197 <6>[ 12.547603] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10595 00:41:18.855350 <30>[ 12.561457] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10596 00:41:18.865394 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10597 00:41:18.888569 <30>[ 12.594262] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10598 00:41:18.894983 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10599 00:41:18.920772 <30>[ 12.626482] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10600 00:41:18.927138 Startin<6>[ 12.635260] fuse: init (API version 7.37)
10601 00:41:18.933553 g [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10602 00:41:18.975467 <30>[ 12.681499] systemd[1]: Starting systemd-journald.service - Journal Service...
10603 00:41:18.982047 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10604 00:41:19.015375 <30>[ 12.721053] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10605 00:41:19.021952 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10606 00:41:19.052112 <30>[ 12.754847] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10607 00:41:19.058499 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10608 00:41:19.084666 <30>[ 12.790767] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10609 00:41:19.094714 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10610 00:41:19.111863 <3>[ 12.817867] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10611 00:41:19.121618 <30>[ 12.822987] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10612 00:41:19.128330 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10613 00:41:19.144355 <3>[ 12.850353] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10614 00:41:19.161096 <30>[ 12.867064] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
10615 00:41:19.167736 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10616 00:41:19.184732 <3>[ 12.890667] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10617 00:41:19.194780 <30>[ 12.900659] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
10618 00:41:19.201804 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10619 00:41:19.211914 <3>[ 12.918221] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10620 00:41:19.222167 <30>[ 12.928042] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
10621 00:41:19.228703 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10622 00:41:19.241496 <3>[ 12.947363] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10623 00:41:19.251592 <30>[ 12.957826] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
10624 00:41:19.262104 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10625 00:41:19.272394 <3>[ 12.978258] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10626 00:41:19.282835 <30>[ 12.988738] systemd[1]: modprobe@configfs.service: Deactivated successfully.
10627 00:41:19.290059 <30>[ 12.997205] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
10628 00:41:19.300419 [[0;32m OK [<3>[ 13.007002] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10629 00:41:19.310120 0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10630 00:41:19.327863 <30>[ 13.033568] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
10631 00:41:19.334572 <3>[ 13.036596] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10632 00:41:19.344265 <30>[ 13.041641] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
10633 00:41:19.351133 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10634 00:41:19.365869 <3>[ 13.071752] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10635 00:41:19.376411 <30>[ 13.082381] systemd[1]: modprobe@drm.service: Deactivated successfully.
10636 00:41:19.383544 <30>[ 13.090154] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
10637 00:41:19.396615 [[0;32m OK [0m] Finished [0<3>[ 13.099827] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10638 00:41:19.399648 ;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10639 00:41:19.420414 <30>[ 13.125620] systemd[1]: modprobe@efi_pstore.service: Deactivated successfully.
10640 00:41:19.427168 <3>[ 13.131508] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10641 00:41:19.436569 <30>[ 13.133683] systemd[1]: Finished modprobe@efi_pstore.service - Load Kernel Module efi_pstore.
10642 00:41:19.443316 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10643 00:41:19.464016 <30>[ 13.170068] systemd[1]: modprobe@fuse.service: Deactivated successfully.
10644 00:41:19.470699 <30>[ 13.177779] systemd[1]: Finished modprobe@fuse.service - Load Kernel Module fuse.
10645 00:41:19.477527 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
10646 00:41:19.499201 <30>[ 13.205313] systemd[1]: Started systemd-journald.service - Journal Service.
10647 00:41:19.512222 <4>[ 13.206040] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10648 00:41:19.522150 <3>[ 13.228393] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10649 00:41:19.529201 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10650 00:41:19.557210 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10651 00:41:19.576370 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10652 00:41:19.595544 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10653 00:41:19.616013 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
10654 00:41:19.635493 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10655 00:41:19.657897 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10656 00:41:19.698872 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
10657 00:41:19.722800 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10658 00:41:19.791599 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10659 00:41:19.815263 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10660 00:41:19.842443 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10661 00:41:19.866166 Startin<46>[ 13.573308] systemd-journald[307]: Received client request to flush runtime journal.
10662 00:41:19.872416 g [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10663 00:41:19.915499 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
10664 00:41:19.939328 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10665 00:41:19.966202 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10666 00:41:19.984342 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10667 00:41:20.003503 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10668 00:41:20.063198 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10669 00:41:21.273613 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10670 00:41:21.312182 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10671 00:41:21.330750 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10672 00:41:21.346161 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10673 00:41:21.395041 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10674 00:41:21.425326 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10675 00:41:21.574335 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10676 00:41:21.635513 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
10677 00:41:21.672888 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10678 00:41:21.879387 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10679 00:41:21.905221 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10680 00:41:21.927229 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10681 00:41:22.015344 <6>[ 15.725036] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10682 00:41:22.024800 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
10683 00:41:22.087796 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
10684 00:41:22.183130 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
10685 00:41:22.202664 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
10686 00:41:22.219573 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10687 00:41:22.239516 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
10688 00:41:22.259008 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10689 00:41:22.283305 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
10690 00:41:22.323506 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
10691 00:41:22.349786 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10692 00:41:22.359691 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10693 00:41:22.378098 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
10694 00:41:22.403991 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
10695 00:41:22.428427 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
10696 00:41:22.446291 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
10697 00:41:22.464201 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
10698 00:41:22.515473 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
10699 00:41:22.533834 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
10700 00:41:22.552122 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
10701 00:41:22.570067 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
10702 00:41:22.576425 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
10703 00:41:22.631302 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
10704 00:41:22.668245 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
10705 00:41:22.743949 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
10706 00:41:22.773877 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
10707 00:41:22.798069 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
10708 00:41:22.860087 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
10709 00:41:22.919301 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
10710 00:41:22.951885 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
10711 00:41:22.963082 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
10712 00:41:22.978985 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
10713 00:41:22.998149 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
10714 00:41:23.027936 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
10715 00:41:23.205212 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
10716 00:41:23.217589 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
10717 00:41:23.234990 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
10718 00:41:23.296027 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
10719 00:41:23.342865 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
10720 00:41:23.438064
10721 00:41:23.441394 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
10722 00:41:23.441473
10723 00:41:23.444993 debian-bookworm-arm64 login: root (automatic login)
10724 00:41:23.445060
10725 00:41:23.664993 Linux debian-bookworm-arm64 6.1.92-cip22 #1 SMP PREEMPT Sun Jun 16 00:28:47 UTC 2024 aarch64
10726 00:41:23.665118
10727 00:41:23.671940 The programs included with the Debian GNU/Linux system are free software;
10728 00:41:23.678130 the exact distribution terms for each program are described in the
10729 00:41:23.681289 individual files in /usr/share/doc/*/copyright.
10730 00:41:23.681369
10731 00:41:23.688246 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10732 00:41:23.691221 permitted by applicable law.
10733 00:41:23.763473 Matched prompt #10: / #
10735 00:41:23.763712 Setting prompt string to ['/ #']
10736 00:41:23.763799 end: 2.2.5.1 login-action (duration 00:00:18) [common]
10738 00:41:23.763989 end: 2.2.5 auto-login-action (duration 00:00:18) [common]
10739 00:41:23.764100 start: 2.2.6 expect-shell-connection (timeout 00:03:48) [common]
10740 00:41:23.764171 Setting prompt string to ['/ #']
10741 00:41:23.764226 Forcing a shell prompt, looking for ['/ #']
10743 00:41:23.814418 / #
10744 00:41:23.814668 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10745 00:41:23.814789 Waiting using forced prompt support (timeout 00:02:30)
10746 00:41:23.819742
10747 00:41:23.820113 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10748 00:41:23.820279 start: 2.2.7 export-device-env (timeout 00:03:48) [common]
10750 00:41:23.920882 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14368404/extract-nfsrootfs-_3z5vp51'
10751 00:41:23.927535 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14368404/extract-nfsrootfs-_3z5vp51'
10753 00:41:24.029235 / # export NFS_SERVER_IP='192.168.201.1'
10754 00:41:24.035915 export NFS_SERVER_IP='192.168.201.1'
10755 00:41:24.036706 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10756 00:41:24.037201 end: 2.2 depthcharge-retry (duration 00:01:12) [common]
10757 00:41:24.037684 end: 2 depthcharge-action (duration 00:01:12) [common]
10758 00:41:24.038155 start: 3 lava-test-retry (timeout 00:01:00) [common]
10759 00:41:24.038905 start: 3.1 lava-test-shell (timeout 00:01:00) [common]
10760 00:41:24.039314 Using namespace: common
10762 00:41:24.140368 / # #
10763 00:41:24.141045 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
10764 00:41:24.146912 #
10765 00:41:24.147594 Using /lava-14368404
10767 00:41:24.248394 / # export SHELL=/bin/sh
10768 00:41:24.253563 export SHELL=/bin/sh
10770 00:41:24.354162 / # . /lava-14368404/environment
10771 00:41:24.360403 . /lava-14368404/environment
10773 00:41:24.466302 / # /lava-14368404/bin/lava-test-runner /lava-14368404/0
10774 00:41:24.466966 Test shell timeout: 10s (minimum of the action and connection timeout)
10775 00:41:24.472844 /lava-14368404/bin/lava-test-runner /lava-14368404/0
10776 00:41:24.674592 + export TESTRUN_ID=0_dmesg
10777 00:41:24.677993 + cd /lava-14368404/0/tests/0_dmesg
10778 00:41:24.681272 + cat uuid
10779 00:41:24.692149 + UUID=14368404_1.<8>[ 18.398813] <LAVA_SIGNAL_STARTRUN 0_dmesg 14368404_1.6.2.3.1>
10780 00:41:24.692607 6.2.3.1
10781 00:41:24.692960 + set +x
10782 00:41:24.693558 Received signal: <STARTRUN> 0_dmesg 14368404_1.6.2.3.1
10783 00:41:24.694071 Starting test lava.0_dmesg (14368404_1.6.2.3.1)
10784 00:41:24.694591 Skipping test definition patterns.
10785 00:41:24.698463 + KERNELCI_LAVA=y /bin/sh /opt/kernelci/dmesg.sh
10786 00:41:24.785573 <8>[ 18.492214] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0>
10787 00:41:24.785906 Received signal: <TESTCASE> TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0
10789 00:41:24.853060 <8>[ 18.559659] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0>
10790 00:41:24.853778 Received signal: <TESTCASE> TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0
10792 00:41:24.921998 <8>[ 18.628729] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0>
10793 00:41:24.922300 Received signal: <TESTCASE> TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0
10795 00:41:24.924832 + set +x
10796 00:41:24.928680 <8>[ 18.638465] <LAVA_SIGNAL_ENDRUN 0_dmesg 14368404_1.6.2.3.1>
10797 00:41:24.928969 Received signal: <ENDRUN> 0_dmesg 14368404_1.6.2.3.1
10798 00:41:24.929080 Ending use of test pattern.
10799 00:41:24.929200 Ending test lava.0_dmesg (14368404_1.6.2.3.1), duration 0.24
10801 00:41:24.933594 <LAVA_TEST_RUNNER EXIT>
10802 00:41:24.933870 ok: lava_test_shell seems to have completed
10803 00:41:24.934041 alert: pass
crit: pass
emerg: pass
10804 00:41:24.934201 end: 3.1 lava-test-shell (duration 00:00:01) [common]
10805 00:41:24.934337 end: 3 lava-test-retry (duration 00:00:01) [common]
10806 00:41:24.934468 start: 4 finalize (timeout 00:08:18) [common]
10807 00:41:24.934602 start: 4.1 power-off (timeout 00:00:30) [common]
10808 00:41:24.934915 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-4', '--port=1', '--command=off']
10809 00:41:25.169032 >> Command sent successfully.
10810 00:41:25.183662 Returned 0 in 0 seconds
10811 00:41:25.285047 end: 4.1 power-off (duration 00:00:00) [common]
10813 00:41:25.286887 start: 4.2 read-feedback (timeout 00:08:18) [common]
10814 00:41:25.288355 Listened to connection for namespace 'common' for up to 1s
10815 00:41:26.288908 Finalising connection for namespace 'common'
10816 00:41:26.289570 Disconnecting from shell: Finalise
10817 00:41:26.289983 / #
10818 00:41:26.390895 end: 4.2 read-feedback (duration 00:00:01) [common]
10819 00:41:26.391553 end: 4 finalize (duration 00:00:01) [common]
10820 00:41:26.392171 Cleaning after the job
10821 00:41:26.392683 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14368404/tftp-deploy-4qyk1yvl/ramdisk
10822 00:41:26.402877 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14368404/tftp-deploy-4qyk1yvl/kernel
10823 00:41:26.437238 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14368404/tftp-deploy-4qyk1yvl/dtb
10824 00:41:26.437555 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14368404/tftp-deploy-4qyk1yvl/nfsrootfs
10825 00:41:26.501061 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14368404/tftp-deploy-4qyk1yvl/modules
10826 00:41:26.506805 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14368404
10827 00:41:26.812976 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14368404
10828 00:41:26.813148 Job finished correctly