Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 29
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 23
1 00:44:52.536158 lava-dispatcher, installed at version: 2024.03
2 00:44:52.536403 start: 0 validate
3 00:44:52.536523 Start time: 2024-06-16 00:44:52.536516+00:00 (UTC)
4 00:44:52.536667 Using caching service: 'http://localhost/cache/?uri=%s'
5 00:44:52.536809 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-igt%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 00:44:52.827827 Using caching service: 'http://localhost/cache/?uri=%s'
7 00:44:52.827995 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22-24-g0315de64ea248%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 00:44:53.076094 Using caching service: 'http://localhost/cache/?uri=%s'
9 00:44:53.076280 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22-24-g0315de64ea248%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 00:44:53.324709 Using caching service: 'http://localhost/cache/?uri=%s'
11 00:44:53.324863 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22-24-g0315de64ea248%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 00:44:53.575573 validate duration: 1.04
14 00:44:53.575854 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 00:44:53.575969 start: 1.1 download-retry (timeout 00:10:00) [common]
16 00:44:53.576060 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 00:44:53.576225 Not decompressing ramdisk as can be used compressed.
18 00:44:53.576317 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-igt/20240313.0/arm64/rootfs.cpio.gz
19 00:44:53.576391 saving as /var/lib/lava/dispatcher/tmp/14368423/tftp-deploy-t4bmfn5s/ramdisk/rootfs.cpio.gz
20 00:44:53.576460 total size: 47897469 (45 MB)
21 00:44:53.577493 progress 0 % (0 MB)
22 00:44:53.589689 progress 5 % (2 MB)
23 00:44:53.601708 progress 10 % (4 MB)
24 00:44:53.613624 progress 15 % (6 MB)
25 00:44:53.625651 progress 20 % (9 MB)
26 00:44:53.637672 progress 25 % (11 MB)
27 00:44:53.649728 progress 30 % (13 MB)
28 00:44:53.661744 progress 35 % (16 MB)
29 00:44:53.673953 progress 40 % (18 MB)
30 00:44:53.685889 progress 45 % (20 MB)
31 00:44:53.697750 progress 50 % (22 MB)
32 00:44:53.710126 progress 55 % (25 MB)
33 00:44:53.722688 progress 60 % (27 MB)
34 00:44:53.734740 progress 65 % (29 MB)
35 00:44:53.746813 progress 70 % (32 MB)
36 00:44:53.758855 progress 75 % (34 MB)
37 00:44:53.770873 progress 80 % (36 MB)
38 00:44:53.782970 progress 85 % (38 MB)
39 00:44:53.794857 progress 90 % (41 MB)
40 00:44:53.806654 progress 95 % (43 MB)
41 00:44:53.818496 progress 100 % (45 MB)
42 00:44:53.818791 45 MB downloaded in 0.24 s (188.50 MB/s)
43 00:44:53.818954 end: 1.1.1 http-download (duration 00:00:00) [common]
45 00:44:53.819175 end: 1.1 download-retry (duration 00:00:00) [common]
46 00:44:53.819255 start: 1.2 download-retry (timeout 00:10:00) [common]
47 00:44:53.819331 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 00:44:53.819468 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-24-g0315de64ea248/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 00:44:53.819530 saving as /var/lib/lava/dispatcher/tmp/14368423/tftp-deploy-t4bmfn5s/kernel/Image
50 00:44:53.819583 total size: 54813184 (52 MB)
51 00:44:53.819637 No compression specified
52 00:44:53.820656 progress 0 % (0 MB)
53 00:44:53.834299 progress 5 % (2 MB)
54 00:44:53.848138 progress 10 % (5 MB)
55 00:44:53.861741 progress 15 % (7 MB)
56 00:44:53.875587 progress 20 % (10 MB)
57 00:44:53.889302 progress 25 % (13 MB)
58 00:44:53.902825 progress 30 % (15 MB)
59 00:44:53.916530 progress 35 % (18 MB)
60 00:44:53.930332 progress 40 % (20 MB)
61 00:44:53.943998 progress 45 % (23 MB)
62 00:44:53.957956 progress 50 % (26 MB)
63 00:44:53.971779 progress 55 % (28 MB)
64 00:44:53.986230 progress 60 % (31 MB)
65 00:44:54.001294 progress 65 % (34 MB)
66 00:44:54.015629 progress 70 % (36 MB)
67 00:44:54.029470 progress 75 % (39 MB)
68 00:44:54.043362 progress 80 % (41 MB)
69 00:44:54.057290 progress 85 % (44 MB)
70 00:44:54.071225 progress 90 % (47 MB)
71 00:44:54.085052 progress 95 % (49 MB)
72 00:44:54.098558 progress 100 % (52 MB)
73 00:44:54.098822 52 MB downloaded in 0.28 s (187.20 MB/s)
74 00:44:54.098978 end: 1.2.1 http-download (duration 00:00:00) [common]
76 00:44:54.099189 end: 1.2 download-retry (duration 00:00:00) [common]
77 00:44:54.099271 start: 1.3 download-retry (timeout 00:09:59) [common]
78 00:44:54.099347 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 00:44:54.099481 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-24-g0315de64ea248/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 00:44:54.099544 saving as /var/lib/lava/dispatcher/tmp/14368423/tftp-deploy-t4bmfn5s/dtb/mt8192-asurada-spherion-r0.dtb
81 00:44:54.099598 total size: 47258 (0 MB)
82 00:44:54.099652 No compression specified
83 00:44:54.100695 progress 69 % (0 MB)
84 00:44:54.100980 progress 100 % (0 MB)
85 00:44:54.101129 0 MB downloaded in 0.00 s (29.49 MB/s)
86 00:44:54.101245 end: 1.3.1 http-download (duration 00:00:00) [common]
88 00:44:54.101447 end: 1.3 download-retry (duration 00:00:00) [common]
89 00:44:54.101525 start: 1.4 download-retry (timeout 00:09:59) [common]
90 00:44:54.101610 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 00:44:54.101718 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-24-g0315de64ea248/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 00:44:54.101780 saving as /var/lib/lava/dispatcher/tmp/14368423/tftp-deploy-t4bmfn5s/modules/modules.tar
93 00:44:54.101834 total size: 8608736 (8 MB)
94 00:44:54.101889 Using unxz to decompress xz
95 00:44:54.103232 progress 0 % (0 MB)
96 00:44:54.122305 progress 5 % (0 MB)
97 00:44:54.148147 progress 10 % (0 MB)
98 00:44:54.176194 progress 15 % (1 MB)
99 00:44:54.199689 progress 20 % (1 MB)
100 00:44:54.223881 progress 25 % (2 MB)
101 00:44:54.247286 progress 30 % (2 MB)
102 00:44:54.271406 progress 35 % (2 MB)
103 00:44:54.297619 progress 40 % (3 MB)
104 00:44:54.320535 progress 45 % (3 MB)
105 00:44:54.344688 progress 50 % (4 MB)
106 00:44:54.369288 progress 55 % (4 MB)
107 00:44:54.393481 progress 60 % (4 MB)
108 00:44:54.417943 progress 65 % (5 MB)
109 00:44:54.442657 progress 70 % (5 MB)
110 00:44:54.468305 progress 75 % (6 MB)
111 00:44:54.493626 progress 80 % (6 MB)
112 00:44:54.518000 progress 85 % (7 MB)
113 00:44:54.542829 progress 90 % (7 MB)
114 00:44:54.567815 progress 95 % (7 MB)
115 00:44:54.592386 progress 100 % (8 MB)
116 00:44:54.597644 8 MB downloaded in 0.50 s (16.56 MB/s)
117 00:44:54.597829 end: 1.4.1 http-download (duration 00:00:00) [common]
119 00:44:54.598042 end: 1.4 download-retry (duration 00:00:00) [common]
120 00:44:54.598123 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 00:44:54.598200 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 00:44:54.598274 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 00:44:54.598346 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 00:44:54.598516 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14368423/lava-overlay-swiozsac
125 00:44:54.598632 makedir: /var/lib/lava/dispatcher/tmp/14368423/lava-overlay-swiozsac/lava-14368423/bin
126 00:44:54.598720 makedir: /var/lib/lava/dispatcher/tmp/14368423/lava-overlay-swiozsac/lava-14368423/tests
127 00:44:54.598805 makedir: /var/lib/lava/dispatcher/tmp/14368423/lava-overlay-swiozsac/lava-14368423/results
128 00:44:54.598892 Creating /var/lib/lava/dispatcher/tmp/14368423/lava-overlay-swiozsac/lava-14368423/bin/lava-add-keys
129 00:44:54.599024 Creating /var/lib/lava/dispatcher/tmp/14368423/lava-overlay-swiozsac/lava-14368423/bin/lava-add-sources
130 00:44:54.599139 Creating /var/lib/lava/dispatcher/tmp/14368423/lava-overlay-swiozsac/lava-14368423/bin/lava-background-process-start
131 00:44:54.599256 Creating /var/lib/lava/dispatcher/tmp/14368423/lava-overlay-swiozsac/lava-14368423/bin/lava-background-process-stop
132 00:44:54.599378 Creating /var/lib/lava/dispatcher/tmp/14368423/lava-overlay-swiozsac/lava-14368423/bin/lava-common-functions
133 00:44:54.599492 Creating /var/lib/lava/dispatcher/tmp/14368423/lava-overlay-swiozsac/lava-14368423/bin/lava-echo-ipv4
134 00:44:54.599606 Creating /var/lib/lava/dispatcher/tmp/14368423/lava-overlay-swiozsac/lava-14368423/bin/lava-install-packages
135 00:44:54.599716 Creating /var/lib/lava/dispatcher/tmp/14368423/lava-overlay-swiozsac/lava-14368423/bin/lava-installed-packages
136 00:44:54.599826 Creating /var/lib/lava/dispatcher/tmp/14368423/lava-overlay-swiozsac/lava-14368423/bin/lava-os-build
137 00:44:54.599935 Creating /var/lib/lava/dispatcher/tmp/14368423/lava-overlay-swiozsac/lava-14368423/bin/lava-probe-channel
138 00:44:54.600044 Creating /var/lib/lava/dispatcher/tmp/14368423/lava-overlay-swiozsac/lava-14368423/bin/lava-probe-ip
139 00:44:54.600152 Creating /var/lib/lava/dispatcher/tmp/14368423/lava-overlay-swiozsac/lava-14368423/bin/lava-target-ip
140 00:44:54.600260 Creating /var/lib/lava/dispatcher/tmp/14368423/lava-overlay-swiozsac/lava-14368423/bin/lava-target-mac
141 00:44:54.600368 Creating /var/lib/lava/dispatcher/tmp/14368423/lava-overlay-swiozsac/lava-14368423/bin/lava-target-storage
142 00:44:54.600478 Creating /var/lib/lava/dispatcher/tmp/14368423/lava-overlay-swiozsac/lava-14368423/bin/lava-test-case
143 00:44:54.600586 Creating /var/lib/lava/dispatcher/tmp/14368423/lava-overlay-swiozsac/lava-14368423/bin/lava-test-event
144 00:44:54.600694 Creating /var/lib/lava/dispatcher/tmp/14368423/lava-overlay-swiozsac/lava-14368423/bin/lava-test-feedback
145 00:44:54.600801 Creating /var/lib/lava/dispatcher/tmp/14368423/lava-overlay-swiozsac/lava-14368423/bin/lava-test-raise
146 00:44:54.600908 Creating /var/lib/lava/dispatcher/tmp/14368423/lava-overlay-swiozsac/lava-14368423/bin/lava-test-reference
147 00:44:54.601015 Creating /var/lib/lava/dispatcher/tmp/14368423/lava-overlay-swiozsac/lava-14368423/bin/lava-test-runner
148 00:44:54.601123 Creating /var/lib/lava/dispatcher/tmp/14368423/lava-overlay-swiozsac/lava-14368423/bin/lava-test-set
149 00:44:54.601233 Creating /var/lib/lava/dispatcher/tmp/14368423/lava-overlay-swiozsac/lava-14368423/bin/lava-test-shell
150 00:44:54.601343 Updating /var/lib/lava/dispatcher/tmp/14368423/lava-overlay-swiozsac/lava-14368423/bin/lava-install-packages (oe)
151 00:44:54.601479 Updating /var/lib/lava/dispatcher/tmp/14368423/lava-overlay-swiozsac/lava-14368423/bin/lava-installed-packages (oe)
152 00:44:54.601627 Creating /var/lib/lava/dispatcher/tmp/14368423/lava-overlay-swiozsac/lava-14368423/environment
153 00:44:54.601711 LAVA metadata
154 00:44:54.601774 - LAVA_JOB_ID=14368423
155 00:44:54.601827 - LAVA_DISPATCHER_IP=192.168.201.1
156 00:44:54.601915 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 00:44:54.601970 skipped lava-vland-overlay
158 00:44:54.602033 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 00:44:54.602111 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 00:44:54.602173 skipped lava-multinode-overlay
161 00:44:54.602252 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 00:44:54.602322 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 00:44:54.602384 Loading test definitions
164 00:44:54.602456 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 00:44:54.602513 Using /lava-14368423 at stage 0
166 00:44:54.602815 uuid=14368423_1.5.2.3.1 testdef=None
167 00:44:54.602894 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 00:44:54.602968 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 00:44:54.603399 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 00:44:54.603601 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 00:44:54.604160 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 00:44:54.604431 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 00:44:54.604968 runner path: /var/lib/lava/dispatcher/tmp/14368423/lava-overlay-swiozsac/lava-14368423/0/tests/0_igt-gpu-panfrost test_uuid 14368423_1.5.2.3.1
176 00:44:54.605111 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 00:44:54.605303 Creating lava-test-runner.conf files
179 00:44:54.605358 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14368423/lava-overlay-swiozsac/lava-14368423/0 for stage 0
180 00:44:54.605437 - 0_igt-gpu-panfrost
181 00:44:54.605525 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 00:44:54.605662 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 00:44:54.611710 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 00:44:54.611831 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 00:44:54.611911 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 00:44:54.611994 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 00:44:54.612103 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 00:44:56.348813 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:02) [common]
189 00:44:56.348966 start: 1.5.4 extract-modules (timeout 00:09:57) [common]
190 00:44:56.349047 extracting modules file /var/lib/lava/dispatcher/tmp/14368423/tftp-deploy-t4bmfn5s/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14368423/extract-overlay-ramdisk-me5e5xap/ramdisk
191 00:44:56.591363 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 00:44:56.591514 start: 1.5.5 apply-overlay-tftp (timeout 00:09:57) [common]
193 00:44:56.591591 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14368423/compress-overlay-3kp0q_sf/overlay-1.5.2.4.tar.gz to ramdisk
194 00:44:56.591651 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14368423/compress-overlay-3kp0q_sf/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14368423/extract-overlay-ramdisk-me5e5xap/ramdisk
195 00:44:56.600186 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 00:44:56.600321 start: 1.5.6 configure-preseed-file (timeout 00:09:57) [common]
197 00:44:56.600402 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 00:44:56.600478 start: 1.5.7 compress-ramdisk (timeout 00:09:57) [common]
199 00:44:56.600548 Building ramdisk /var/lib/lava/dispatcher/tmp/14368423/extract-overlay-ramdisk-me5e5xap/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14368423/extract-overlay-ramdisk-me5e5xap/ramdisk
200 00:44:57.752332 >> 465988 blocks
201 00:45:04.151006 rename /var/lib/lava/dispatcher/tmp/14368423/extract-overlay-ramdisk-me5e5xap/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14368423/tftp-deploy-t4bmfn5s/ramdisk/ramdisk.cpio.gz
202 00:45:04.151181 end: 1.5.7 compress-ramdisk (duration 00:00:08) [common]
203 00:45:04.151269 start: 1.5.8 prepare-kernel (timeout 00:09:49) [common]
204 00:45:04.151347 start: 1.5.8.1 prepare-fit (timeout 00:09:49) [common]
205 00:45:04.151424 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14368423/tftp-deploy-t4bmfn5s/kernel/Image']
206 00:45:17.482160 Returned 0 in 13 seconds
207 00:45:17.582934 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14368423/tftp-deploy-t4bmfn5s/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14368423/tftp-deploy-t4bmfn5s/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14368423/tftp-deploy-t4bmfn5s/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14368423/tftp-deploy-t4bmfn5s/kernel/image.itb
208 00:45:18.610602 output: FIT description: Kernel Image image with one or more FDT blobs
209 00:45:18.610736 output: Created: Sun Jun 16 01:45:18 2024
210 00:45:18.610802 output: Image 0 (kernel-1)
211 00:45:18.610856 output: Description:
212 00:45:18.610911 output: Created: Sun Jun 16 01:45:18 2024
213 00:45:18.610968 output: Type: Kernel Image
214 00:45:18.611023 output: Compression: lzma compressed
215 00:45:18.611082 output: Data Size: 13126376 Bytes = 12818.73 KiB = 12.52 MiB
216 00:45:18.611136 output: Architecture: AArch64
217 00:45:18.611191 output: OS: Linux
218 00:45:18.611246 output: Load Address: 0x00000000
219 00:45:18.611300 output: Entry Point: 0x00000000
220 00:45:18.611354 output: Hash algo: crc32
221 00:45:18.611406 output: Hash value: c791a20a
222 00:45:18.611462 output: Image 1 (fdt-1)
223 00:45:18.611513 output: Description: mt8192-asurada-spherion-r0
224 00:45:18.611563 output: Created: Sun Jun 16 01:45:18 2024
225 00:45:18.611615 output: Type: Flat Device Tree
226 00:45:18.611662 output: Compression: uncompressed
227 00:45:18.611714 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
228 00:45:18.611765 output: Architecture: AArch64
229 00:45:18.611816 output: Hash algo: crc32
230 00:45:18.611862 output: Hash value: 0f8e4d2e
231 00:45:18.611909 output: Image 2 (ramdisk-1)
232 00:45:18.611956 output: Description: unavailable
233 00:45:18.612002 output: Created: Sun Jun 16 01:45:18 2024
234 00:45:18.612049 output: Type: RAMDisk Image
235 00:45:18.612096 output: Compression: uncompressed
236 00:45:18.612151 output: Data Size: 61006101 Bytes = 59576.27 KiB = 58.18 MiB
237 00:45:18.612233 output: Architecture: AArch64
238 00:45:18.612280 output: OS: Linux
239 00:45:18.612326 output: Load Address: unavailable
240 00:45:18.612373 output: Entry Point: unavailable
241 00:45:18.612419 output: Hash algo: crc32
242 00:45:18.612466 output: Hash value: f187f01a
243 00:45:18.612511 output: Default Configuration: 'conf-1'
244 00:45:18.612557 output: Configuration 0 (conf-1)
245 00:45:18.612604 output: Description: mt8192-asurada-spherion-r0
246 00:45:18.612651 output: Kernel: kernel-1
247 00:45:18.612698 output: Init Ramdisk: ramdisk-1
248 00:45:18.612746 output: FDT: fdt-1
249 00:45:18.612793 output: Loadables: kernel-1
250 00:45:18.612839 output:
251 00:45:18.612971 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
252 00:45:18.613054 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
253 00:45:18.613140 end: 1.5 prepare-tftp-overlay (duration 00:00:24) [common]
254 00:45:18.613221 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:35) [common]
255 00:45:18.613289 No LXC device requested
256 00:45:18.613360 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 00:45:18.613434 start: 1.7 deploy-device-env (timeout 00:09:35) [common]
258 00:45:18.613503 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 00:45:18.613589 Checking files for TFTP limit of 4294967296 bytes.
260 00:45:18.614048 end: 1 tftp-deploy (duration 00:00:25) [common]
261 00:45:18.614148 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 00:45:18.614255 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 00:45:18.614396 substitutions:
264 00:45:18.614460 - {DTB}: 14368423/tftp-deploy-t4bmfn5s/dtb/mt8192-asurada-spherion-r0.dtb
265 00:45:18.614522 - {INITRD}: 14368423/tftp-deploy-t4bmfn5s/ramdisk/ramdisk.cpio.gz
266 00:45:18.614578 - {KERNEL}: 14368423/tftp-deploy-t4bmfn5s/kernel/Image
267 00:45:18.614629 - {LAVA_MAC}: None
268 00:45:18.614680 - {PRESEED_CONFIG}: None
269 00:45:18.614731 - {PRESEED_LOCAL}: None
270 00:45:18.614780 - {RAMDISK}: 14368423/tftp-deploy-t4bmfn5s/ramdisk/ramdisk.cpio.gz
271 00:45:18.614838 - {ROOT_PART}: None
272 00:45:18.614888 - {ROOT}: None
273 00:45:18.614937 - {SERVER_IP}: 192.168.201.1
274 00:45:18.614985 - {TEE}: None
275 00:45:18.615035 Parsed boot commands:
276 00:45:18.615083 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 00:45:18.615228 Parsed boot commands: tftpboot 192.168.201.1 14368423/tftp-deploy-t4bmfn5s/kernel/image.itb 14368423/tftp-deploy-t4bmfn5s/kernel/cmdline
278 00:45:18.615309 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 00:45:18.615386 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 00:45:18.615466 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 00:45:18.615540 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 00:45:18.615602 Not connected, no need to disconnect.
283 00:45:18.615670 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 00:45:18.615743 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 00:45:18.615801 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-0'
286 00:45:18.619066 Setting prompt string to ['lava-test: # ']
287 00:45:18.619381 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 00:45:18.619480 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 00:45:18.619574 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 00:45:18.619659 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 00:45:18.619838 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-0', '--port=1', '--command=reboot']
292 00:45:27.754927 >> Command sent successfully.
293 00:45:27.758480 Returned 0 in 9 seconds
294 00:45:27.858795 end: 2.2.2.1 pdu-reboot (duration 00:00:09) [common]
296 00:45:27.859069 end: 2.2.2 reset-device (duration 00:00:09) [common]
297 00:45:27.859170 start: 2.2.3 depthcharge-start (timeout 00:04:51) [common]
298 00:45:27.859256 Setting prompt string to 'Starting depthcharge on Spherion...'
299 00:45:27.859315 Changing prompt to 'Starting depthcharge on Spherion...'
300 00:45:27.859380 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 00:45:27.859732 [Enter `^Ec?' for help]
302 00:45:29.361363
303 00:45:29.361497
304 00:45:29.361582 F0: 102B 0000
305 00:45:29.361658
306 00:45:29.361713 F3: 1001 0000 [0200]
307 00:45:29.365152
308 00:45:29.365231 F3: 1001 0000
309 00:45:29.365293
310 00:45:29.365348 F7: 102D 0000
311 00:45:29.365404
312 00:45:29.365459 F1: 0000 0000
313 00:45:29.368854
314 00:45:29.368935 V0: 0000 0000 [0001]
315 00:45:29.368995
316 00:45:29.369049 00: 0007 8000
317 00:45:29.369103
318 00:45:29.372749 01: 0000 0000
319 00:45:29.372825
320 00:45:29.372883 BP: 0C00 0209 [0000]
321 00:45:29.372937
322 00:45:29.376435 G0: 1182 0000
323 00:45:29.376510
324 00:45:29.376568 EC: 0000 0021 [4000]
325 00:45:29.376621
326 00:45:29.380172 S7: 0000 0000 [0000]
327 00:45:29.380246
328 00:45:29.380303 CC: 0000 0000 [0001]
329 00:45:29.380356
330 00:45:29.383887 T0: 0000 0040 [010F]
331 00:45:29.383965
332 00:45:29.384022 Jump to BL
333 00:45:29.384076
334 00:45:29.408494
335 00:45:29.408573
336 00:45:29.416207 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
337 00:45:29.420042 ARM64: Exception handlers installed.
338 00:45:29.423883 ARM64: Testing exception
339 00:45:29.423984 ARM64: Done test exception
340 00:45:29.431096 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
341 00:45:29.441455 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
342 00:45:29.448170 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
343 00:45:29.459450 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
344 00:45:29.465510 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
345 00:45:29.476033 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
346 00:45:29.485856 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
347 00:45:29.492907 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
348 00:45:29.511369 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
349 00:45:29.514681 WDT: Last reset was cold boot
350 00:45:29.518124 SPI1(PAD0) initialized at 2873684 Hz
351 00:45:29.521286 SPI5(PAD0) initialized at 992727 Hz
352 00:45:29.524753 VBOOT: Loading verstage.
353 00:45:29.531007 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
354 00:45:29.534597 FMAP: Found "FLASH" version 1.1 at 0x20000.
355 00:45:29.537583 FMAP: base = 0x0 size = 0x800000 #areas = 25
356 00:45:29.540953 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
357 00:45:29.548929 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
358 00:45:29.555040 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
359 00:45:29.566289 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
360 00:45:29.566365
361 00:45:29.566424
362 00:45:29.576344 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
363 00:45:29.579690 ARM64: Exception handlers installed.
364 00:45:29.582856 ARM64: Testing exception
365 00:45:29.582932 ARM64: Done test exception
366 00:45:29.589528 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
367 00:45:29.592801 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
368 00:45:29.607070 Probing TPM: . done!
369 00:45:29.607149 TPM ready after 0 ms
370 00:45:29.614050 Connected to device vid:did:rid of 1ae0:0028:00
371 00:45:29.620709 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
372 00:45:29.661377 Initialized TPM device CR50 revision 0
373 00:45:29.672573 tlcl_send_startup: Startup return code is 0
374 00:45:29.672650 TPM: setup succeeded
375 00:45:29.684626 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
376 00:45:29.692761 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
377 00:45:29.703029 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
378 00:45:29.712103 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
379 00:45:29.715230 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
380 00:45:29.718931 in-header: 03 07 00 00 08 00 00 00
381 00:45:29.722096 in-data: aa e4 47 04 13 02 00 00
382 00:45:29.725849 Chrome EC: UHEPI supported
383 00:45:29.732084 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
384 00:45:29.735935 in-header: 03 a9 00 00 08 00 00 00
385 00:45:29.739142 in-data: 84 60 60 08 00 00 00 00
386 00:45:29.739218 Phase 1
387 00:45:29.742411 FMAP: area GBB found @ 3f5000 (12032 bytes)
388 00:45:29.748983 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
389 00:45:29.755258 VB2:vb2_check_recovery() Recovery was requested manually
390 00:45:29.759186 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x7
391 00:45:29.762406 Recovery requested (1009000e)
392 00:45:29.770343 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 00:45:29.776271 tlcl_extend: response is 0
394 00:45:29.784300 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 00:45:29.789742 tlcl_extend: response is 0
396 00:45:29.796070 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 00:45:29.817512 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
398 00:45:29.824469 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 00:45:29.824546
400 00:45:29.824604
401 00:45:29.834699 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 00:45:29.837740 ARM64: Exception handlers installed.
403 00:45:29.837815 ARM64: Testing exception
404 00:45:29.841249 ARM64: Done test exception
405 00:45:29.862031 pmic_efuse_setting: Set efuses in 11 msecs
406 00:45:29.865836 pmwrap_interface_init: Select PMIF_VLD_RDY
407 00:45:29.872547 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 00:45:29.875827 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 00:45:29.882622 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 00:45:29.885831 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 00:45:29.892687 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 00:45:29.895893 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 00:45:29.899083 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 00:45:29.905585 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 00:45:29.908977 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 00:45:29.915969 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 00:45:29.919185 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 00:45:29.922673 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 00:45:29.929194 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 00:45:29.935987 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 00:45:29.939258 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 00:45:29.946083 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 00:45:29.952821 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 00:45:29.955918 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 00:45:29.962271 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 00:45:29.969168 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 00:45:29.975795 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 00:45:29.979582 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 00:45:29.986325 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 00:45:29.989527 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 00:45:29.996108 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 00:45:30.002879 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 00:45:30.006181 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 00:45:30.012775 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 00:45:30.016115 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 00:45:30.022664 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 00:45:30.025977 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 00:45:30.032614 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 00:45:30.035777 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 00:45:30.042867 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 00:45:30.046202 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 00:45:30.052446 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 00:45:30.056002 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 00:45:30.063337 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 00:45:30.066400 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 00:45:30.070095 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 00:45:30.073474 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 00:45:30.080197 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 00:45:30.083457 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 00:45:30.086870 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 00:45:30.093392 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 00:45:30.096487 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 00:45:30.099819 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 00:45:30.103208 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 00:45:30.110435 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 00:45:30.113689 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 00:45:30.117100 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 00:45:30.126963 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x6b6d 0x5bf0 0x8100 0x4c 0xf0f 0x9248
459 00:45:30.133652 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 00:45:30.136932 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 00:45:30.146980 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 00:45:30.153214 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 00:45:30.160033 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 00:45:30.163536 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 00:45:30.166650 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 00:45:30.175299 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x25
467 00:45:30.181740 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 00:45:30.184781 [RTC]rtc_osc_init,62: osc32con val = 0xde70
469 00:45:30.188117 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 00:45:30.199497 [RTC]rtc_get_frequency_meter,154: input=15, output=759
471 00:45:30.209246 [RTC]rtc_get_frequency_meter,154: input=23, output=942
472 00:45:30.218886 [RTC]rtc_get_frequency_meter,154: input=19, output=851
473 00:45:30.228215 [RTC]rtc_get_frequency_meter,154: input=17, output=805
474 00:45:30.237793 [RTC]rtc_get_frequency_meter,154: input=16, output=783
475 00:45:30.246938 [RTC]rtc_get_frequency_meter,154: input=16, output=782
476 00:45:30.256777 [RTC]rtc_get_frequency_meter,154: input=17, output=805
477 00:45:30.259838 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
478 00:45:30.267188 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
479 00:45:30.270298 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
480 00:45:30.274083 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
481 00:45:30.280207 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
482 00:45:30.283619 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
483 00:45:30.287122 ADC[4]: Raw value=906203 ID=7
484 00:45:30.287191 ADC[3]: Raw value=213441 ID=1
485 00:45:30.290743 RAM Code: 0x71
486 00:45:30.293864 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
487 00:45:30.300561 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
488 00:45:30.307082 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
489 00:45:30.313969 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
490 00:45:30.317523 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
491 00:45:30.320558 in-header: 03 07 00 00 08 00 00 00
492 00:45:30.324424 in-data: aa e4 47 04 13 02 00 00
493 00:45:30.327754 Chrome EC: UHEPI supported
494 00:45:30.334241 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
495 00:45:30.337709 in-header: 03 a9 00 00 08 00 00 00
496 00:45:30.341078 in-data: 84 60 60 08 00 00 00 00
497 00:45:30.343756 MRC: failed to locate region type 0.
498 00:45:30.350932 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
499 00:45:30.353560 DRAM-K: Running full calibration
500 00:45:30.360324 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
501 00:45:30.360392 header.status = 0x0
502 00:45:30.364086 header.version = 0x6 (expected: 0x6)
503 00:45:30.367338 header.size = 0xd00 (expected: 0xd00)
504 00:45:30.370856 header.flags = 0x0
505 00:45:30.377225 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
506 00:45:30.394054 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
507 00:45:30.400696 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
508 00:45:30.404296 dram_init: ddr_geometry: 2
509 00:45:30.404394 [EMI] MDL number = 2
510 00:45:30.407365 [EMI] Get MDL freq = 0
511 00:45:30.411309 dram_init: ddr_type: 0
512 00:45:30.411384 is_discrete_lpddr4: 1
513 00:45:30.413996 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
514 00:45:30.414071
515 00:45:30.414129
516 00:45:30.417835 [Bian_co] ETT version 0.0.0.1
517 00:45:30.424698 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
518 00:45:30.424773
519 00:45:30.427549 dramc_set_vcore_voltage set vcore to 650000
520 00:45:30.427624 Read voltage for 800, 4
521 00:45:30.431373 Vio18 = 0
522 00:45:30.431448 Vcore = 650000
523 00:45:30.431507 Vdram = 0
524 00:45:30.434296 Vddq = 0
525 00:45:30.434370 Vmddr = 0
526 00:45:30.437603 dram_init: config_dvfs: 1
527 00:45:30.441118 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
528 00:45:30.447714 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
529 00:45:30.451077 [SwImpedanceCal] DRVP=10, DRVN=16, ODTN=9
530 00:45:30.454343 freq_region=0, Reg: DRVP=10, DRVN=16, ODTN=9
531 00:45:30.457697 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
532 00:45:30.460914 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
533 00:45:30.465031 MEM_TYPE=3, freq_sel=18
534 00:45:30.468770 sv_algorithm_assistance_LP4_1600
535 00:45:30.472495 ============ PULL DRAM RESETB DOWN ============
536 00:45:30.476458 ========== PULL DRAM RESETB DOWN end =========
537 00:45:30.479770 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
538 00:45:30.483588 ===================================
539 00:45:30.487090 LPDDR4 DRAM CONFIGURATION
540 00:45:30.491041 ===================================
541 00:45:30.491116 EX_ROW_EN[0] = 0x0
542 00:45:30.494836 EX_ROW_EN[1] = 0x0
543 00:45:30.494911 LP4Y_EN = 0x0
544 00:45:30.498101 WORK_FSP = 0x0
545 00:45:30.498177 WL = 0x2
546 00:45:30.502093 RL = 0x2
547 00:45:30.502169 BL = 0x2
548 00:45:30.502227 RPST = 0x0
549 00:45:30.505393 RD_PRE = 0x0
550 00:45:30.505491 WR_PRE = 0x1
551 00:45:30.509169 WR_PST = 0x0
552 00:45:30.509269 DBI_WR = 0x0
553 00:45:30.512217 DBI_RD = 0x0
554 00:45:30.515675 OTF = 0x1
555 00:45:30.519422 ===================================
556 00:45:30.519500 ===================================
557 00:45:30.522118 ANA top config
558 00:45:30.525445 ===================================
559 00:45:30.528838 DLL_ASYNC_EN = 0
560 00:45:30.528939 ALL_SLAVE_EN = 1
561 00:45:30.532074 NEW_RANK_MODE = 1
562 00:45:30.535844 DLL_IDLE_MODE = 1
563 00:45:30.538994 LP45_APHY_COMB_EN = 1
564 00:45:30.539069 TX_ODT_DIS = 1
565 00:45:30.542183 NEW_8X_MODE = 1
566 00:45:30.545823 ===================================
567 00:45:30.548844 ===================================
568 00:45:30.552222 data_rate = 1600
569 00:45:30.555779 CKR = 1
570 00:45:30.558937 DQ_P2S_RATIO = 8
571 00:45:30.561993 ===================================
572 00:45:30.565443 CA_P2S_RATIO = 8
573 00:45:30.565543 DQ_CA_OPEN = 0
574 00:45:30.568851 DQ_SEMI_OPEN = 0
575 00:45:30.572283 CA_SEMI_OPEN = 0
576 00:45:30.575262 CA_FULL_RATE = 0
577 00:45:30.578967 DQ_CKDIV4_EN = 1
578 00:45:30.582279 CA_CKDIV4_EN = 1
579 00:45:30.582352 CA_PREDIV_EN = 0
580 00:45:30.585578 PH8_DLY = 0
581 00:45:30.589119 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
582 00:45:30.592410 DQ_AAMCK_DIV = 4
583 00:45:30.595757 CA_AAMCK_DIV = 4
584 00:45:30.598979 CA_ADMCK_DIV = 4
585 00:45:30.599077 DQ_TRACK_CA_EN = 0
586 00:45:30.602206 CA_PICK = 800
587 00:45:30.605383 CA_MCKIO = 800
588 00:45:30.608586 MCKIO_SEMI = 0
589 00:45:30.611941 PLL_FREQ = 3068
590 00:45:30.616049 DQ_UI_PI_RATIO = 32
591 00:45:30.618664 CA_UI_PI_RATIO = 0
592 00:45:30.622344 ===================================
593 00:45:30.626007 ===================================
594 00:45:30.626078 memory_type:LPDDR4
595 00:45:30.628998 GP_NUM : 10
596 00:45:30.629059 SRAM_EN : 1
597 00:45:30.632710 MD32_EN : 0
598 00:45:30.635921 ===================================
599 00:45:30.639283 [ANA_INIT] >>>>>>>>>>>>>>
600 00:45:30.642435 <<<<<< [CONFIGURE PHASE]: ANA_TX
601 00:45:30.645568 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
602 00:45:30.648792 ===================================
603 00:45:30.648857 data_rate = 1600,PCW = 0X7600
604 00:45:30.652087 ===================================
605 00:45:30.655949 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
606 00:45:30.662626 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 00:45:30.669235 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
608 00:45:30.672518 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
609 00:45:30.675951 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
610 00:45:30.679332 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
611 00:45:30.682505 [ANA_INIT] flow start
612 00:45:30.682584 [ANA_INIT] PLL >>>>>>>>
613 00:45:30.685663 [ANA_INIT] PLL <<<<<<<<
614 00:45:30.689514 [ANA_INIT] MIDPI >>>>>>>>
615 00:45:30.692760 [ANA_INIT] MIDPI <<<<<<<<
616 00:45:30.692860 [ANA_INIT] DLL >>>>>>>>
617 00:45:30.696078 [ANA_INIT] flow end
618 00:45:30.699465 ============ LP4 DIFF to SE enter ============
619 00:45:30.702755 ============ LP4 DIFF to SE exit ============
620 00:45:30.706096 [ANA_INIT] <<<<<<<<<<<<<
621 00:45:30.709285 [Flow] Enable top DCM control >>>>>
622 00:45:30.712437 [Flow] Enable top DCM control <<<<<
623 00:45:30.716069 Enable DLL master slave shuffle
624 00:45:30.719381 ==============================================================
625 00:45:30.722800 Gating Mode config
626 00:45:30.729353 ==============================================================
627 00:45:30.729452 Config description:
628 00:45:30.739529 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
629 00:45:30.746092 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
630 00:45:30.749380 SELPH_MODE 0: By rank 1: By Phase
631 00:45:30.756420 ==============================================================
632 00:45:30.759760 GAT_TRACK_EN = 1
633 00:45:30.763097 RX_GATING_MODE = 2
634 00:45:30.766450 RX_GATING_TRACK_MODE = 2
635 00:45:30.769743 SELPH_MODE = 1
636 00:45:30.773165 PICG_EARLY_EN = 1
637 00:45:30.776553 VALID_LAT_VALUE = 1
638 00:45:30.779757 ==============================================================
639 00:45:30.782739 Enter into Gating configuration >>>>
640 00:45:30.786295 Exit from Gating configuration <<<<
641 00:45:30.789454 Enter into DVFS_PRE_config >>>>>
642 00:45:30.799580 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
643 00:45:30.803241 Exit from DVFS_PRE_config <<<<<
644 00:45:30.806279 Enter into PICG configuration >>>>
645 00:45:30.809571 Exit from PICG configuration <<<<
646 00:45:30.813119 [RX_INPUT] configuration >>>>>
647 00:45:30.816226 [RX_INPUT] configuration <<<<<
648 00:45:30.822624 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
649 00:45:30.825796 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
650 00:45:30.833096 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
651 00:45:30.839169 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
652 00:45:30.846192 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
653 00:45:30.852483 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
654 00:45:30.855804 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
655 00:45:30.859257 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
656 00:45:30.863033 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
657 00:45:30.869477 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
658 00:45:30.872918 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
659 00:45:30.876278 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
660 00:45:30.879649 ===================================
661 00:45:30.883058 LPDDR4 DRAM CONFIGURATION
662 00:45:30.886467 ===================================
663 00:45:30.886542 EX_ROW_EN[0] = 0x0
664 00:45:30.889183 EX_ROW_EN[1] = 0x0
665 00:45:30.889258 LP4Y_EN = 0x0
666 00:45:30.892522 WORK_FSP = 0x0
667 00:45:30.892597 WL = 0x2
668 00:45:30.895892 RL = 0x2
669 00:45:30.899243 BL = 0x2
670 00:45:30.899318 RPST = 0x0
671 00:45:30.902462 RD_PRE = 0x0
672 00:45:30.902536 WR_PRE = 0x1
673 00:45:30.906174 WR_PST = 0x0
674 00:45:30.906249 DBI_WR = 0x0
675 00:45:30.909667 DBI_RD = 0x0
676 00:45:30.909767 OTF = 0x1
677 00:45:30.912456 ===================================
678 00:45:30.916173 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
679 00:45:30.922624 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
680 00:45:30.926407 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
681 00:45:30.929540 ===================================
682 00:45:30.933219 LPDDR4 DRAM CONFIGURATION
683 00:45:30.936277 ===================================
684 00:45:30.936353 EX_ROW_EN[0] = 0x10
685 00:45:30.939495 EX_ROW_EN[1] = 0x0
686 00:45:30.939571 LP4Y_EN = 0x0
687 00:45:30.942951 WORK_FSP = 0x0
688 00:45:30.943027 WL = 0x2
689 00:45:30.946470 RL = 0x2
690 00:45:30.946545 BL = 0x2
691 00:45:30.949597 RPST = 0x0
692 00:45:30.949673 RD_PRE = 0x0
693 00:45:30.952868 WR_PRE = 0x1
694 00:45:30.952943 WR_PST = 0x0
695 00:45:30.956580 DBI_WR = 0x0
696 00:45:30.956655 DBI_RD = 0x0
697 00:45:30.959522 OTF = 0x1
698 00:45:30.962922 ===================================
699 00:45:30.969481 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
700 00:45:30.973167 nWR fixed to 40
701 00:45:30.976673 [ModeRegInit_LP4] CH0 RK0
702 00:45:30.976749 [ModeRegInit_LP4] CH0 RK1
703 00:45:30.979983 [ModeRegInit_LP4] CH1 RK0
704 00:45:30.982698 [ModeRegInit_LP4] CH1 RK1
705 00:45:30.982799 match AC timing 13
706 00:45:30.989992 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
707 00:45:30.993437 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
708 00:45:30.996165 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
709 00:45:31.002928 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
710 00:45:31.006225 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
711 00:45:31.006328 [EMI DOE] emi_dcm 0
712 00:45:31.013706 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
713 00:45:31.013782 ==
714 00:45:31.016292 Dram Type= 6, Freq= 0, CH_0, rank 0
715 00:45:31.019769 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
716 00:45:31.019845 ==
717 00:45:31.026521 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
718 00:45:31.029745 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
719 00:45:31.039991 [CA 0] Center 36 (6~67) winsize 62
720 00:45:31.043651 [CA 1] Center 36 (6~67) winsize 62
721 00:45:31.047602 [CA 2] Center 34 (4~65) winsize 62
722 00:45:31.051016 [CA 3] Center 33 (3~64) winsize 62
723 00:45:31.054410 [CA 4] Center 33 (3~64) winsize 62
724 00:45:31.057906 [CA 5] Center 32 (2~62) winsize 61
725 00:45:31.057981
726 00:45:31.061758 [CmdBusTrainingLP45] Vref(ca) range 1: 34
727 00:45:31.061834
728 00:45:31.065512 [CATrainingPosCal] consider 1 rank data
729 00:45:31.068634 u2DelayCellTimex100 = 270/100 ps
730 00:45:31.071765 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
731 00:45:31.075178 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
732 00:45:31.078725 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
733 00:45:31.081762 CA3 delay=33 (3~64),Diff = 1 PI (7 cell)
734 00:45:31.085227 CA4 delay=33 (3~64),Diff = 1 PI (7 cell)
735 00:45:31.088876 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
736 00:45:31.088951
737 00:45:31.091710 CA PerBit enable=1, Macro0, CA PI delay=32
738 00:45:31.091786
739 00:45:31.095057 [CBTSetCACLKResult] CA Dly = 32
740 00:45:31.098415 CS Dly: 5 (0~36)
741 00:45:31.098489 ==
742 00:45:31.101895 Dram Type= 6, Freq= 0, CH_0, rank 1
743 00:45:31.105171 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
744 00:45:31.105250 ==
745 00:45:31.111795 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
746 00:45:31.118362 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
747 00:45:31.126384 [CA 0] Center 36 (6~67) winsize 62
748 00:45:31.129756 [CA 1] Center 36 (6~67) winsize 62
749 00:45:31.133124 [CA 2] Center 34 (4~65) winsize 62
750 00:45:31.136489 [CA 3] Center 34 (3~65) winsize 63
751 00:45:31.139880 [CA 4] Center 32 (2~63) winsize 62
752 00:45:31.143172 [CA 5] Center 32 (2~63) winsize 62
753 00:45:31.143247
754 00:45:31.146420 [CmdBusTrainingLP45] Vref(ca) range 1: 34
755 00:45:31.146519
756 00:45:31.149755 [CATrainingPosCal] consider 2 rank data
757 00:45:31.153089 u2DelayCellTimex100 = 270/100 ps
758 00:45:31.156320 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
759 00:45:31.159633 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
760 00:45:31.166619 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
761 00:45:31.169604 CA3 delay=33 (3~64),Diff = 1 PI (7 cell)
762 00:45:31.173084 CA4 delay=33 (3~63),Diff = 1 PI (7 cell)
763 00:45:31.176469 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
764 00:45:31.176544
765 00:45:31.179702 CA PerBit enable=1, Macro0, CA PI delay=32
766 00:45:31.179777
767 00:45:31.183061 [CBTSetCACLKResult] CA Dly = 32
768 00:45:31.183136 CS Dly: 5 (0~37)
769 00:45:31.183194
770 00:45:31.186389 ----->DramcWriteLeveling(PI) begin...
771 00:45:31.189377 ==
772 00:45:31.192673 Dram Type= 6, Freq= 0, CH_0, rank 0
773 00:45:31.196053 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
774 00:45:31.196128 ==
775 00:45:31.199784 Write leveling (Byte 0): 33 => 33
776 00:45:31.202711 Write leveling (Byte 1): 30 => 30
777 00:45:31.206306 DramcWriteLeveling(PI) end<-----
778 00:45:31.206407
779 00:45:31.206494 ==
780 00:45:31.209320 Dram Type= 6, Freq= 0, CH_0, rank 0
781 00:45:31.213025 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 00:45:31.213101 ==
783 00:45:31.216401 [Gating] SW mode calibration
784 00:45:31.223046 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
785 00:45:31.226462 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
786 00:45:31.233322 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
787 00:45:31.236615 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
788 00:45:31.239899 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
789 00:45:31.246516 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 00:45:31.249910 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 00:45:31.253233 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 00:45:31.259836 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 00:45:31.263050 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 00:45:31.266810 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 00:45:31.273313 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 00:45:31.276729 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 00:45:31.280143 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 00:45:31.283384 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 00:45:31.290192 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 00:45:31.293174 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 00:45:31.296616 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 00:45:31.303152 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 00:45:31.306766 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
804 00:45:31.309826 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
805 00:45:31.316472 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 00:45:31.320271 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 00:45:31.323275 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 00:45:31.330020 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 00:45:31.333485 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 00:45:31.337240 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 00:45:31.343956 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 00:45:31.346594 0 9 8 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (0 0)
813 00:45:31.349965 0 9 12 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
814 00:45:31.353404 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 00:45:31.360102 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 00:45:31.363379 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 00:45:31.367250 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 00:45:31.373684 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 00:45:31.376846 0 10 4 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
820 00:45:31.380018 0 10 8 | B1->B0 | 3131 2626 | 1 0 | (1 1) (1 0)
821 00:45:31.386726 0 10 12 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
822 00:45:31.390179 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 00:45:31.393430 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 00:45:31.400649 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 00:45:31.403757 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 00:45:31.407336 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 00:45:31.413591 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 00:45:31.417344 0 11 8 | B1->B0 | 3131 4141 | 0 1 | (1 1) (0 0)
829 00:45:31.420736 0 11 12 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
830 00:45:31.427250 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 00:45:31.430623 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 00:45:31.433876 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 00:45:31.437216 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 00:45:31.443710 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 00:45:31.447420 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
836 00:45:31.450429 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
837 00:45:31.457158 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
838 00:45:31.460842 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 00:45:31.464142 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 00:45:31.470625 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 00:45:31.474048 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 00:45:31.477273 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 00:45:31.484021 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 00:45:31.487140 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 00:45:31.491019 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 00:45:31.497135 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 00:45:31.500544 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 00:45:31.504403 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 00:45:31.507753 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 00:45:31.514233 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 00:45:31.517522 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
852 00:45:31.520813 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
853 00:45:31.524408 Total UI for P1: 0, mck2ui 16
854 00:45:31.527393 best dqsien dly found for B0: ( 0, 14, 4)
855 00:45:31.534123 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
856 00:45:31.534198 Total UI for P1: 0, mck2ui 16
857 00:45:31.541026 best dqsien dly found for B1: ( 0, 14, 8)
858 00:45:31.544237 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
859 00:45:31.547457 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
860 00:45:31.547532
861 00:45:31.550762 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
862 00:45:31.554163 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
863 00:45:31.557388 [Gating] SW calibration Done
864 00:45:31.557462 ==
865 00:45:31.560650 Dram Type= 6, Freq= 0, CH_0, rank 0
866 00:45:31.564387 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
867 00:45:31.564485 ==
868 00:45:31.567799 RX Vref Scan: 0
869 00:45:31.567874
870 00:45:31.567932 RX Vref 0 -> 0, step: 1
871 00:45:31.567985
872 00:45:31.570777 RX Delay -130 -> 252, step: 16
873 00:45:31.574199 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
874 00:45:31.580766 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
875 00:45:31.584001 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
876 00:45:31.587402 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
877 00:45:31.590757 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
878 00:45:31.594454 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
879 00:45:31.597837 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
880 00:45:31.604411 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
881 00:45:31.607637 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
882 00:45:31.611037 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
883 00:45:31.614503 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
884 00:45:31.617943 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
885 00:45:31.624518 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
886 00:45:31.627922 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
887 00:45:31.631155 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
888 00:45:31.634457 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
889 00:45:31.634532 ==
890 00:45:31.637807 Dram Type= 6, Freq= 0, CH_0, rank 0
891 00:45:31.644625 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
892 00:45:31.644724 ==
893 00:45:31.644811 DQS Delay:
894 00:45:31.647646 DQS0 = 0, DQS1 = 0
895 00:45:31.647721 DQM Delay:
896 00:45:31.647780 DQM0 = 91, DQM1 = 86
897 00:45:31.651188 DQ Delay:
898 00:45:31.654471 DQ0 =93, DQ1 =93, DQ2 =85, DQ3 =93
899 00:45:31.658132 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =101
900 00:45:31.661403 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =77
901 00:45:31.664924 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
902 00:45:31.665011
903 00:45:31.665070
904 00:45:31.665138 ==
905 00:45:31.668204 Dram Type= 6, Freq= 0, CH_0, rank 0
906 00:45:31.671206 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
907 00:45:31.671302 ==
908 00:45:31.671386
909 00:45:31.671471
910 00:45:31.674711 TX Vref Scan disable
911 00:45:31.674780 == TX Byte 0 ==
912 00:45:31.681360 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
913 00:45:31.684563 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
914 00:45:31.684629 == TX Byte 1 ==
915 00:45:31.691335 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
916 00:45:31.694601 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
917 00:45:31.694676 ==
918 00:45:31.698150 Dram Type= 6, Freq= 0, CH_0, rank 0
919 00:45:31.700912 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
920 00:45:31.701021 ==
921 00:45:31.715779 TX Vref=22, minBit 8, minWin=27, winSum=447
922 00:45:31.718936 TX Vref=24, minBit 8, minWin=27, winSum=451
923 00:45:31.722409 TX Vref=26, minBit 8, minWin=27, winSum=455
924 00:45:31.725780 TX Vref=28, minBit 7, minWin=28, winSum=457
925 00:45:31.729127 TX Vref=30, minBit 5, minWin=28, winSum=457
926 00:45:31.732506 TX Vref=32, minBit 1, minWin=28, winSum=454
927 00:45:31.739011 [TxChooseVref] Worse bit 7, Min win 28, Win sum 457, Final Vref 28
928 00:45:31.739098
929 00:45:31.742317 Final TX Range 1 Vref 28
930 00:45:31.742413
931 00:45:31.742486 ==
932 00:45:31.745527 Dram Type= 6, Freq= 0, CH_0, rank 0
933 00:45:31.748989 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 00:45:31.749092 ==
935 00:45:31.749173
936 00:45:31.749246
937 00:45:31.752291 TX Vref Scan disable
938 00:45:31.755334 == TX Byte 0 ==
939 00:45:31.758941 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
940 00:45:31.762574 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
941 00:45:31.765920 == TX Byte 1 ==
942 00:45:31.769140 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
943 00:45:31.772218 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
944 00:45:31.772317
945 00:45:31.775628 [DATLAT]
946 00:45:31.775757 Freq=800, CH0 RK0
947 00:45:31.775862
948 00:45:31.778825 DATLAT Default: 0xa
949 00:45:31.778910 0, 0xFFFF, sum = 0
950 00:45:31.782072 1, 0xFFFF, sum = 0
951 00:45:31.782188 2, 0xFFFF, sum = 0
952 00:45:31.785499 3, 0xFFFF, sum = 0
953 00:45:31.785606 4, 0xFFFF, sum = 0
954 00:45:31.788934 5, 0xFFFF, sum = 0
955 00:45:31.789036 6, 0xFFFF, sum = 0
956 00:45:31.792325 7, 0xFFFF, sum = 0
957 00:45:31.792403 8, 0xFFFF, sum = 0
958 00:45:31.795579 9, 0x0, sum = 1
959 00:45:31.795658 10, 0x0, sum = 2
960 00:45:31.798796 11, 0x0, sum = 3
961 00:45:31.798872 12, 0x0, sum = 4
962 00:45:31.802810 best_step = 10
963 00:45:31.802884
964 00:45:31.802942 ==
965 00:45:31.805987 Dram Type= 6, Freq= 0, CH_0, rank 0
966 00:45:31.809157 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
967 00:45:31.809265 ==
968 00:45:31.812495 RX Vref Scan: 1
969 00:45:31.812575
970 00:45:31.812635 Set Vref Range= 32 -> 127
971 00:45:31.812690
972 00:45:31.815939 RX Vref 32 -> 127, step: 1
973 00:45:31.816016
974 00:45:31.819055 RX Delay -79 -> 252, step: 8
975 00:45:31.819138
976 00:45:31.822386 Set Vref, RX VrefLevel [Byte0]: 32
977 00:45:31.825887 [Byte1]: 32
978 00:45:31.825965
979 00:45:31.829141 Set Vref, RX VrefLevel [Byte0]: 33
980 00:45:31.832496 [Byte1]: 33
981 00:45:31.832574
982 00:45:31.835998 Set Vref, RX VrefLevel [Byte0]: 34
983 00:45:31.839249 [Byte1]: 34
984 00:45:31.842970
985 00:45:31.843046 Set Vref, RX VrefLevel [Byte0]: 35
986 00:45:31.846390 [Byte1]: 35
987 00:45:31.850313
988 00:45:31.850416 Set Vref, RX VrefLevel [Byte0]: 36
989 00:45:31.853618 [Byte1]: 36
990 00:45:31.858364
991 00:45:31.858463 Set Vref, RX VrefLevel [Byte0]: 37
992 00:45:31.861685 [Byte1]: 37
993 00:45:31.865662
994 00:45:31.865738 Set Vref, RX VrefLevel [Byte0]: 38
995 00:45:31.869019 [Byte1]: 38
996 00:45:31.873446
997 00:45:31.873552 Set Vref, RX VrefLevel [Byte0]: 39
998 00:45:31.876455 [Byte1]: 39
999 00:45:31.880619
1000 00:45:31.880695 Set Vref, RX VrefLevel [Byte0]: 40
1001 00:45:31.884163 [Byte1]: 40
1002 00:45:31.888332
1003 00:45:31.888408 Set Vref, RX VrefLevel [Byte0]: 41
1004 00:45:31.891787 [Byte1]: 41
1005 00:45:31.895709
1006 00:45:31.895785 Set Vref, RX VrefLevel [Byte0]: 42
1007 00:45:31.899119 [Byte1]: 42
1008 00:45:31.903642
1009 00:45:31.903720 Set Vref, RX VrefLevel [Byte0]: 43
1010 00:45:31.906939 [Byte1]: 43
1011 00:45:31.911019
1012 00:45:31.911094 Set Vref, RX VrefLevel [Byte0]: 44
1013 00:45:31.914432 [Byte1]: 44
1014 00:45:31.918473
1015 00:45:31.918548 Set Vref, RX VrefLevel [Byte0]: 45
1016 00:45:31.921777 [Byte1]: 45
1017 00:45:31.926058
1018 00:45:31.926133 Set Vref, RX VrefLevel [Byte0]: 46
1019 00:45:31.929590 [Byte1]: 46
1020 00:45:31.933605
1021 00:45:31.933709 Set Vref, RX VrefLevel [Byte0]: 47
1022 00:45:31.936895 [Byte1]: 47
1023 00:45:31.941157
1024 00:45:31.941232 Set Vref, RX VrefLevel [Byte0]: 48
1025 00:45:31.944340 [Byte1]: 48
1026 00:45:31.949040
1027 00:45:31.949115 Set Vref, RX VrefLevel [Byte0]: 49
1028 00:45:31.952248 [Byte1]: 49
1029 00:45:31.956173
1030 00:45:31.956248 Set Vref, RX VrefLevel [Byte0]: 50
1031 00:45:31.959370 [Byte1]: 50
1032 00:45:31.964055
1033 00:45:31.964130 Set Vref, RX VrefLevel [Byte0]: 51
1034 00:45:31.967199 [Byte1]: 51
1035 00:45:31.971222
1036 00:45:31.971297 Set Vref, RX VrefLevel [Byte0]: 52
1037 00:45:31.974586 [Byte1]: 52
1038 00:45:31.979219
1039 00:45:31.979293 Set Vref, RX VrefLevel [Byte0]: 53
1040 00:45:31.982515 [Byte1]: 53
1041 00:45:31.986448
1042 00:45:31.986523 Set Vref, RX VrefLevel [Byte0]: 54
1043 00:45:31.989647 [Byte1]: 54
1044 00:45:31.994362
1045 00:45:31.994438 Set Vref, RX VrefLevel [Byte0]: 55
1046 00:45:31.997443 [Byte1]: 55
1047 00:45:32.001512
1048 00:45:32.001634 Set Vref, RX VrefLevel [Byte0]: 56
1049 00:45:32.005071 [Byte1]: 56
1050 00:45:32.009174
1051 00:45:32.009251 Set Vref, RX VrefLevel [Byte0]: 57
1052 00:45:32.012545 [Byte1]: 57
1053 00:45:32.016684
1054 00:45:32.016759 Set Vref, RX VrefLevel [Byte0]: 58
1055 00:45:32.020092 [Byte1]: 58
1056 00:45:32.024220
1057 00:45:32.024321 Set Vref, RX VrefLevel [Byte0]: 59
1058 00:45:32.027525 [Byte1]: 59
1059 00:45:32.031655
1060 00:45:32.031729 Set Vref, RX VrefLevel [Byte0]: 60
1061 00:45:32.035051 [Byte1]: 60
1062 00:45:32.038993
1063 00:45:32.039091 Set Vref, RX VrefLevel [Byte0]: 61
1064 00:45:32.042909 [Byte1]: 61
1065 00:45:32.046670
1066 00:45:32.046745 Set Vref, RX VrefLevel [Byte0]: 62
1067 00:45:32.050229 [Byte1]: 62
1068 00:45:32.054250
1069 00:45:32.054324 Set Vref, RX VrefLevel [Byte0]: 63
1070 00:45:32.057610 [Byte1]: 63
1071 00:45:32.062128
1072 00:45:32.062218 Set Vref, RX VrefLevel [Byte0]: 64
1073 00:45:32.065514 [Byte1]: 64
1074 00:45:32.069489
1075 00:45:32.069602 Set Vref, RX VrefLevel [Byte0]: 65
1076 00:45:32.072606 [Byte1]: 65
1077 00:45:32.076977
1078 00:45:32.077053 Set Vref, RX VrefLevel [Byte0]: 66
1079 00:45:32.080419 [Byte1]: 66
1080 00:45:32.084439
1081 00:45:32.084540 Set Vref, RX VrefLevel [Byte0]: 67
1082 00:45:32.087789 [Byte1]: 67
1083 00:45:32.092332
1084 00:45:32.092414 Set Vref, RX VrefLevel [Byte0]: 68
1085 00:45:32.095419 [Byte1]: 68
1086 00:45:32.100013
1087 00:45:32.100089 Set Vref, RX VrefLevel [Byte0]: 69
1088 00:45:32.103322 [Byte1]: 69
1089 00:45:32.107431
1090 00:45:32.107506 Set Vref, RX VrefLevel [Byte0]: 70
1091 00:45:32.110698 [Byte1]: 70
1092 00:45:32.114944
1093 00:45:32.115020 Set Vref, RX VrefLevel [Byte0]: 71
1094 00:45:32.118480 [Byte1]: 71
1095 00:45:32.122505
1096 00:45:32.122581 Set Vref, RX VrefLevel [Byte0]: 72
1097 00:45:32.125806 [Byte1]: 72
1098 00:45:32.129865
1099 00:45:32.129940 Set Vref, RX VrefLevel [Byte0]: 73
1100 00:45:32.133201 [Byte1]: 73
1101 00:45:32.137861
1102 00:45:32.137936 Set Vref, RX VrefLevel [Byte0]: 74
1103 00:45:32.140585 [Byte1]: 74
1104 00:45:32.144757
1105 00:45:32.144856 Set Vref, RX VrefLevel [Byte0]: 75
1106 00:45:32.148103 [Byte1]: 75
1107 00:45:32.152633
1108 00:45:32.152778 Set Vref, RX VrefLevel [Byte0]: 76
1109 00:45:32.155871 [Byte1]: 76
1110 00:45:32.160421
1111 00:45:32.160520 Set Vref, RX VrefLevel [Byte0]: 77
1112 00:45:32.163675 [Byte1]: 77
1113 00:45:32.167623
1114 00:45:32.167715 Set Vref, RX VrefLevel [Byte0]: 78
1115 00:45:32.171007 [Byte1]: 78
1116 00:45:32.175414
1117 00:45:32.175490 Final RX Vref Byte 0 = 54 to rank0
1118 00:45:32.178553 Final RX Vref Byte 1 = 59 to rank0
1119 00:45:32.182150 Final RX Vref Byte 0 = 54 to rank1
1120 00:45:32.185233 Final RX Vref Byte 1 = 59 to rank1==
1121 00:45:32.188822 Dram Type= 6, Freq= 0, CH_0, rank 0
1122 00:45:32.192269 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1123 00:45:32.195351 ==
1124 00:45:32.195427 DQS Delay:
1125 00:45:32.195486 DQS0 = 0, DQS1 = 0
1126 00:45:32.198853 DQM Delay:
1127 00:45:32.198929 DQM0 = 92, DQM1 = 86
1128 00:45:32.202238 DQ Delay:
1129 00:45:32.202313 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1130 00:45:32.205594 DQ4 =92, DQ5 =80, DQ6 =100, DQ7 =100
1131 00:45:32.208722 DQ8 =76, DQ9 =80, DQ10 =88, DQ11 =76
1132 00:45:32.212012 DQ12 =92, DQ13 =92, DQ14 =92, DQ15 =92
1133 00:45:32.215438
1134 00:45:32.215514
1135 00:45:32.222194 [DQSOSCAuto] RK0, (LSB)MR18= 0x5248, (MSB)MR19= 0x606, tDQSOscB0 = 391 ps tDQSOscB1 = 389 ps
1136 00:45:32.225514 CH0 RK0: MR19=606, MR18=5248
1137 00:45:32.232065 CH0_RK0: MR19=0x606, MR18=0x5248, DQSOSC=389, MR23=63, INC=97, DEC=65
1138 00:45:32.232142
1139 00:45:32.235585 ----->DramcWriteLeveling(PI) begin...
1140 00:45:32.235662 ==
1141 00:45:32.238730 Dram Type= 6, Freq= 0, CH_0, rank 1
1142 00:45:32.242293 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1143 00:45:32.242370 ==
1144 00:45:32.245653 Write leveling (Byte 0): 32 => 32
1145 00:45:32.249047 Write leveling (Byte 1): 27 => 27
1146 00:45:32.252411 DramcWriteLeveling(PI) end<-----
1147 00:45:32.252487
1148 00:45:32.252545 ==
1149 00:45:32.255699 Dram Type= 6, Freq= 0, CH_0, rank 1
1150 00:45:32.259059 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1151 00:45:32.259134 ==
1152 00:45:32.262419 [Gating] SW mode calibration
1153 00:45:32.269285 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1154 00:45:32.316379 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1155 00:45:32.316463 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1156 00:45:32.316704 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1157 00:45:32.316770 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1158 00:45:32.316825 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 00:45:32.317309 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 00:45:32.317401 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 00:45:32.317653 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 00:45:32.317713 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 00:45:32.317768 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 00:45:32.330485 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 00:45:32.330564 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 00:45:32.331316 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 00:45:32.334092 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 00:45:32.337391 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 00:45:32.340469 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 00:45:32.344170 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 00:45:32.347733 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 00:45:32.354191 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 00:45:32.357485 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1174 00:45:32.361106 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 00:45:32.367877 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 00:45:32.370881 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 00:45:32.374413 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 00:45:32.380996 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 00:45:32.384228 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 00:45:32.387608 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 00:45:32.394099 0 9 8 | B1->B0 | 2c2c 2a2a | 1 1 | (1 1) (1 1)
1182 00:45:32.397388 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1183 00:45:32.400813 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1184 00:45:32.407573 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1185 00:45:32.410859 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1186 00:45:32.414462 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1187 00:45:32.421001 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1188 00:45:32.424305 0 10 4 | B1->B0 | 3333 3333 | 1 0 | (1 1) (0 0)
1189 00:45:32.427741 0 10 8 | B1->B0 | 2727 2929 | 0 0 | (1 1) (0 1)
1190 00:45:32.431196 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 00:45:32.437764 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 00:45:32.441058 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 00:45:32.444343 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 00:45:32.450724 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1195 00:45:32.454153 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1196 00:45:32.457513 0 11 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1197 00:45:32.464469 0 11 8 | B1->B0 | 3d3d 3737 | 0 0 | (0 0) (0 0)
1198 00:45:32.468116 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1199 00:45:32.471489 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1200 00:45:32.478084 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1201 00:45:32.481273 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1202 00:45:32.484302 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1203 00:45:32.491029 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1204 00:45:32.494338 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1205 00:45:32.498248 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1206 00:45:32.504348 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 00:45:32.507638 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 00:45:32.511066 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 00:45:32.514518 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 00:45:32.521302 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 00:45:32.524500 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 00:45:32.528006 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 00:45:32.534767 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 00:45:32.538189 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 00:45:32.541647 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 00:45:32.547827 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 00:45:32.551616 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 00:45:32.554404 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1219 00:45:32.561032 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1220 00:45:32.564865 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1221 00:45:32.567968 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1222 00:45:32.574717 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1223 00:45:32.574794 Total UI for P1: 0, mck2ui 16
1224 00:45:32.578185 best dqsien dly found for B0: ( 0, 14, 8)
1225 00:45:32.581480 Total UI for P1: 0, mck2ui 16
1226 00:45:32.584498 best dqsien dly found for B1: ( 0, 14, 8)
1227 00:45:32.590930 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1228 00:45:32.594376 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1229 00:45:32.594456
1230 00:45:32.597919 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1231 00:45:32.601080 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1232 00:45:32.604466 [Gating] SW calibration Done
1233 00:45:32.604561 ==
1234 00:45:32.607956 Dram Type= 6, Freq= 0, CH_0, rank 1
1235 00:45:32.611217 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1236 00:45:32.611337 ==
1237 00:45:32.611426 RX Vref Scan: 0
1238 00:45:32.611514
1239 00:45:32.614699 RX Vref 0 -> 0, step: 1
1240 00:45:32.614788
1241 00:45:32.618169 RX Delay -130 -> 252, step: 16
1242 00:45:32.621424 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
1243 00:45:32.624776 iDelay=206, Bit 1, Center 93 (-18 ~ 205) 224
1244 00:45:32.631503 iDelay=206, Bit 2, Center 93 (-18 ~ 205) 224
1245 00:45:32.634792 iDelay=206, Bit 3, Center 93 (-18 ~ 205) 224
1246 00:45:32.638107 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1247 00:45:32.641492 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
1248 00:45:32.644335 iDelay=206, Bit 6, Center 101 (-2 ~ 205) 208
1249 00:45:32.651558 iDelay=206, Bit 7, Center 101 (-2 ~ 205) 208
1250 00:45:32.654427 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1251 00:45:32.658113 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1252 00:45:32.661436 iDelay=206, Bit 10, Center 85 (-18 ~ 189) 208
1253 00:45:32.664809 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1254 00:45:32.671550 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
1255 00:45:32.674343 iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224
1256 00:45:32.678251 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
1257 00:45:32.681433 iDelay=206, Bit 15, Center 93 (-18 ~ 205) 224
1258 00:45:32.681500 ==
1259 00:45:32.684871 Dram Type= 6, Freq= 0, CH_0, rank 1
1260 00:45:32.691292 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1261 00:45:32.691364 ==
1262 00:45:32.691424 DQS Delay:
1263 00:45:32.691481 DQS0 = 0, DQS1 = 0
1264 00:45:32.695152 DQM Delay:
1265 00:45:32.695216 DQM0 = 93, DQM1 = 84
1266 00:45:32.697890 DQ Delay:
1267 00:45:32.701218 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =93
1268 00:45:32.704499 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =101
1269 00:45:32.707994 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
1270 00:45:32.711267 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1271 00:45:32.711344
1272 00:45:32.711402
1273 00:45:32.711456 ==
1274 00:45:32.714718 Dram Type= 6, Freq= 0, CH_0, rank 1
1275 00:45:32.717924 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1276 00:45:32.718001 ==
1277 00:45:32.718061
1278 00:45:32.718117
1279 00:45:32.721276 TX Vref Scan disable
1280 00:45:32.721353 == TX Byte 0 ==
1281 00:45:32.728569 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1282 00:45:32.732032 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1283 00:45:32.732115 == TX Byte 1 ==
1284 00:45:32.738381 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1285 00:45:32.741302 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1286 00:45:32.741380 ==
1287 00:45:32.744678 Dram Type= 6, Freq= 0, CH_0, rank 1
1288 00:45:32.748463 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1289 00:45:32.748539 ==
1290 00:45:32.762290 TX Vref=22, minBit 8, minWin=27, winSum=452
1291 00:45:32.766043 TX Vref=24, minBit 1, minWin=28, winSum=456
1292 00:45:32.769434 TX Vref=26, minBit 1, minWin=28, winSum=457
1293 00:45:32.772840 TX Vref=28, minBit 4, minWin=28, winSum=459
1294 00:45:32.776151 TX Vref=30, minBit 2, minWin=28, winSum=456
1295 00:45:32.779534 TX Vref=32, minBit 2, minWin=28, winSum=453
1296 00:45:32.786137 [TxChooseVref] Worse bit 4, Min win 28, Win sum 459, Final Vref 28
1297 00:45:32.786214
1298 00:45:32.789449 Final TX Range 1 Vref 28
1299 00:45:32.789526
1300 00:45:32.789596 ==
1301 00:45:32.792793 Dram Type= 6, Freq= 0, CH_0, rank 1
1302 00:45:32.796243 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1303 00:45:32.796320 ==
1304 00:45:32.796380
1305 00:45:32.796435
1306 00:45:32.798825 TX Vref Scan disable
1307 00:45:32.802262 == TX Byte 0 ==
1308 00:45:32.806204 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1309 00:45:32.809412 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1310 00:45:32.812423 == TX Byte 1 ==
1311 00:45:32.815667 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1312 00:45:32.819541 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1313 00:45:32.819612
1314 00:45:32.822935 [DATLAT]
1315 00:45:32.822999 Freq=800, CH0 RK1
1316 00:45:32.823060
1317 00:45:32.826064 DATLAT Default: 0xa
1318 00:45:32.826132 0, 0xFFFF, sum = 0
1319 00:45:32.829695 1, 0xFFFF, sum = 0
1320 00:45:32.829760 2, 0xFFFF, sum = 0
1321 00:45:32.832416 3, 0xFFFF, sum = 0
1322 00:45:32.832515 4, 0xFFFF, sum = 0
1323 00:45:32.836032 5, 0xFFFF, sum = 0
1324 00:45:32.836093 6, 0xFFFF, sum = 0
1325 00:45:32.839470 7, 0xFFFF, sum = 0
1326 00:45:32.839542 8, 0xFFFF, sum = 0
1327 00:45:32.842557 9, 0x0, sum = 1
1328 00:45:32.842623 10, 0x0, sum = 2
1329 00:45:32.846169 11, 0x0, sum = 3
1330 00:45:32.846230 12, 0x0, sum = 4
1331 00:45:32.849084 best_step = 10
1332 00:45:32.849149
1333 00:45:32.849202 ==
1334 00:45:32.852385 Dram Type= 6, Freq= 0, CH_0, rank 1
1335 00:45:32.855967 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1336 00:45:32.856038 ==
1337 00:45:32.859282 RX Vref Scan: 0
1338 00:45:32.859345
1339 00:45:32.859399 RX Vref 0 -> 0, step: 1
1340 00:45:32.859459
1341 00:45:32.862505 RX Delay -95 -> 252, step: 8
1342 00:45:32.869555 iDelay=209, Bit 0, Center 92 (-15 ~ 200) 216
1343 00:45:32.872620 iDelay=209, Bit 1, Center 96 (-7 ~ 200) 208
1344 00:45:32.875862 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1345 00:45:32.879176 iDelay=209, Bit 3, Center 92 (-15 ~ 200) 216
1346 00:45:32.882585 iDelay=209, Bit 4, Center 96 (-15 ~ 208) 224
1347 00:45:32.886437 iDelay=209, Bit 5, Center 84 (-23 ~ 192) 216
1348 00:45:32.892928 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1349 00:45:32.896312 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1350 00:45:32.899710 iDelay=209, Bit 8, Center 76 (-31 ~ 184) 216
1351 00:45:32.903049 iDelay=209, Bit 9, Center 72 (-31 ~ 176) 208
1352 00:45:32.906386 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1353 00:45:32.913049 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1354 00:45:32.916293 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1355 00:45:32.919446 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1356 00:45:32.922477 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1357 00:45:32.929799 iDelay=209, Bit 15, Center 92 (-15 ~ 200) 216
1358 00:45:32.929869 ==
1359 00:45:32.933020 Dram Type= 6, Freq= 0, CH_0, rank 1
1360 00:45:32.936394 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1361 00:45:32.936461 ==
1362 00:45:32.936519 DQS Delay:
1363 00:45:32.939794 DQS0 = 0, DQS1 = 0
1364 00:45:32.939855 DQM Delay:
1365 00:45:32.942983 DQM0 = 93, DQM1 = 82
1366 00:45:32.943050 DQ Delay:
1367 00:45:32.946389 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =92
1368 00:45:32.949738 DQ4 =96, DQ5 =84, DQ6 =100, DQ7 =100
1369 00:45:32.952839 DQ8 =76, DQ9 =72, DQ10 =84, DQ11 =76
1370 00:45:32.955957 DQ12 =84, DQ13 =84, DQ14 =92, DQ15 =92
1371 00:45:32.956021
1372 00:45:32.956073
1373 00:45:32.962963 [DQSOSCAuto] RK1, (LSB)MR18= 0x4718, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 392 ps
1374 00:45:32.965997 CH0 RK1: MR19=606, MR18=4718
1375 00:45:32.973068 CH0_RK1: MR19=0x606, MR18=0x4718, DQSOSC=392, MR23=63, INC=96, DEC=64
1376 00:45:32.976219 [RxdqsGatingPostProcess] freq 800
1377 00:45:32.982739 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1378 00:45:32.982814 Pre-setting of DQS Precalculation
1379 00:45:32.989560 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1380 00:45:32.989631 ==
1381 00:45:32.992980 Dram Type= 6, Freq= 0, CH_1, rank 0
1382 00:45:32.996393 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1383 00:45:32.996459 ==
1384 00:45:33.002786 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1385 00:45:33.009505 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1386 00:45:33.017729 [CA 0] Center 36 (6~67) winsize 62
1387 00:45:33.020970 [CA 1] Center 36 (6~67) winsize 62
1388 00:45:33.024249 [CA 2] Center 34 (4~65) winsize 62
1389 00:45:33.027434 [CA 3] Center 34 (4~65) winsize 62
1390 00:45:33.030980 [CA 4] Center 35 (5~65) winsize 61
1391 00:45:33.034119 [CA 5] Center 34 (4~65) winsize 62
1392 00:45:33.034192
1393 00:45:33.037488 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1394 00:45:33.037556
1395 00:45:33.040953 [CATrainingPosCal] consider 1 rank data
1396 00:45:33.044285 u2DelayCellTimex100 = 270/100 ps
1397 00:45:33.047517 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1398 00:45:33.050830 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1399 00:45:33.054206 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1400 00:45:33.061462 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1401 00:45:33.064803 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1402 00:45:33.068050 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1403 00:45:33.068119
1404 00:45:33.071134 CA PerBit enable=1, Macro0, CA PI delay=34
1405 00:45:33.071208
1406 00:45:33.074532 [CBTSetCACLKResult] CA Dly = 34
1407 00:45:33.074623 CS Dly: 5 (0~36)
1408 00:45:33.074711 ==
1409 00:45:33.078036 Dram Type= 6, Freq= 0, CH_1, rank 1
1410 00:45:33.084560 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1411 00:45:33.084630 ==
1412 00:45:33.088023 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1413 00:45:33.094654 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1414 00:45:33.103712 [CA 0] Center 36 (6~67) winsize 62
1415 00:45:33.107111 [CA 1] Center 37 (6~68) winsize 63
1416 00:45:33.110274 [CA 2] Center 35 (4~66) winsize 63
1417 00:45:33.113773 [CA 3] Center 34 (4~65) winsize 62
1418 00:45:33.116876 [CA 4] Center 34 (4~65) winsize 62
1419 00:45:33.120620 [CA 5] Center 34 (4~65) winsize 62
1420 00:45:33.120749
1421 00:45:33.123619 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1422 00:45:33.123690
1423 00:45:33.127110 [CATrainingPosCal] consider 2 rank data
1424 00:45:33.130049 u2DelayCellTimex100 = 270/100 ps
1425 00:45:33.133730 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1426 00:45:33.137070 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1427 00:45:33.143618 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1428 00:45:33.147081 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1429 00:45:33.150362 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1430 00:45:33.153510 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1431 00:45:33.153615
1432 00:45:33.156878 CA PerBit enable=1, Macro0, CA PI delay=34
1433 00:45:33.156952
1434 00:45:33.160323 [CBTSetCACLKResult] CA Dly = 34
1435 00:45:33.160394 CS Dly: 6 (0~38)
1436 00:45:33.160484
1437 00:45:33.164088 ----->DramcWriteLeveling(PI) begin...
1438 00:45:33.164160 ==
1439 00:45:33.167121 Dram Type= 6, Freq= 0, CH_1, rank 0
1440 00:45:33.174215 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1441 00:45:33.174312 ==
1442 00:45:33.176873 Write leveling (Byte 0): 26 => 26
1443 00:45:33.180245 Write leveling (Byte 1): 30 => 30
1444 00:45:33.180314 DramcWriteLeveling(PI) end<-----
1445 00:45:33.183603
1446 00:45:33.183674 ==
1447 00:45:33.186729 Dram Type= 6, Freq= 0, CH_1, rank 0
1448 00:45:33.190773 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1449 00:45:33.190842 ==
1450 00:45:33.193433 [Gating] SW mode calibration
1451 00:45:33.200197 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1452 00:45:33.203491 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1453 00:45:33.210279 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1454 00:45:33.213621 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1455 00:45:33.216769 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1456 00:45:33.223606 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 00:45:33.227267 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 00:45:33.230444 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 00:45:33.236961 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 00:45:33.240360 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 00:45:33.243866 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 00:45:33.250469 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 00:45:33.253815 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 00:45:33.257097 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 00:45:33.260448 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 00:45:33.266903 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 00:45:33.270163 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 00:45:33.273463 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 00:45:33.280512 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1470 00:45:33.284069 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 00:45:33.287450 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 00:45:33.293961 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 00:45:33.297402 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 00:45:33.300704 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 00:45:33.307523 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 00:45:33.310822 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 00:45:33.313656 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 00:45:33.320324 0 9 4 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
1479 00:45:33.323748 0 9 8 | B1->B0 | 2d2d 3434 | 1 1 | (1 1) (1 1)
1480 00:45:33.326963 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1481 00:45:33.334011 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1482 00:45:33.337081 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1483 00:45:33.340490 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1484 00:45:33.346935 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1485 00:45:33.350445 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1486 00:45:33.353834 0 10 4 | B1->B0 | 3333 2f2f | 0 0 | (0 1) (0 1)
1487 00:45:33.357176 0 10 8 | B1->B0 | 2626 2323 | 0 0 | (0 0) (1 0)
1488 00:45:33.364021 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 00:45:33.367645 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 00:45:33.370381 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 00:45:33.377422 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 00:45:33.380694 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 00:45:33.383650 0 11 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1494 00:45:33.390753 0 11 4 | B1->B0 | 2929 3737 | 0 0 | (0 0) (0 0)
1495 00:45:33.393629 0 11 8 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
1496 00:45:33.397501 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1497 00:45:33.404042 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1498 00:45:33.407264 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1499 00:45:33.410385 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1500 00:45:33.416991 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1501 00:45:33.420417 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1502 00:45:33.423827 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1503 00:45:33.430567 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 00:45:33.433846 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 00:45:33.437130 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 00:45:33.440871 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 00:45:33.447692 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 00:45:33.451031 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 00:45:33.453778 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 00:45:33.460509 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 00:45:33.463823 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 00:45:33.467195 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 00:45:33.473997 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 00:45:33.477335 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 00:45:33.480587 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1516 00:45:33.487671 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1517 00:45:33.491151 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1518 00:45:33.494363 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1519 00:45:33.497198 Total UI for P1: 0, mck2ui 16
1520 00:45:33.500691 best dqsien dly found for B1: ( 0, 14, 2)
1521 00:45:33.507598 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1522 00:45:33.507672 Total UI for P1: 0, mck2ui 16
1523 00:45:33.510691 best dqsien dly found for B0: ( 0, 14, 4)
1524 00:45:33.517471 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1525 00:45:33.521177 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1526 00:45:33.521291
1527 00:45:33.524300 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1528 00:45:33.527951 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1529 00:45:33.530917 [Gating] SW calibration Done
1530 00:45:33.530987 ==
1531 00:45:33.534024 Dram Type= 6, Freq= 0, CH_1, rank 0
1532 00:45:33.537449 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1533 00:45:33.537544 ==
1534 00:45:33.537649 RX Vref Scan: 0
1535 00:45:33.537708
1536 00:45:33.540716 RX Vref 0 -> 0, step: 1
1537 00:45:33.540777
1538 00:45:33.544540 RX Delay -130 -> 252, step: 16
1539 00:45:33.547669 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1540 00:45:33.550911 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1541 00:45:33.558096 iDelay=222, Bit 2, Center 85 (-18 ~ 189) 208
1542 00:45:33.561352 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1543 00:45:33.564051 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1544 00:45:33.567530 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1545 00:45:33.571049 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1546 00:45:33.577540 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1547 00:45:33.580970 iDelay=222, Bit 8, Center 85 (-18 ~ 189) 208
1548 00:45:33.584233 iDelay=222, Bit 9, Center 85 (-18 ~ 189) 208
1549 00:45:33.587621 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1550 00:45:33.591451 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1551 00:45:33.598127 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1552 00:45:33.600746 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1553 00:45:33.604126 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1554 00:45:33.607451 iDelay=222, Bit 15, Center 101 (-2 ~ 205) 208
1555 00:45:33.607520 ==
1556 00:45:33.611040 Dram Type= 6, Freq= 0, CH_1, rank 0
1557 00:45:33.614763 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1558 00:45:33.617924 ==
1559 00:45:33.617993 DQS Delay:
1560 00:45:33.618049 DQS0 = 0, DQS1 = 0
1561 00:45:33.621113 DQM Delay:
1562 00:45:33.621203 DQM0 = 93, DQM1 = 90
1563 00:45:33.624364 DQ Delay:
1564 00:45:33.624427 DQ0 =93, DQ1 =85, DQ2 =85, DQ3 =93
1565 00:45:33.627718 DQ4 =93, DQ5 =109, DQ6 =93, DQ7 =93
1566 00:45:33.631019 DQ8 =85, DQ9 =85, DQ10 =85, DQ11 =85
1567 00:45:33.634885 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =101
1568 00:45:33.634960
1569 00:45:33.638033
1570 00:45:33.638108 ==
1571 00:45:33.641202 Dram Type= 6, Freq= 0, CH_1, rank 0
1572 00:45:33.644922 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1573 00:45:33.644998 ==
1574 00:45:33.645057
1575 00:45:33.645110
1576 00:45:33.647955 TX Vref Scan disable
1577 00:45:33.648035 == TX Byte 0 ==
1578 00:45:33.654416 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1579 00:45:33.657881 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1580 00:45:33.657956 == TX Byte 1 ==
1581 00:45:33.664806 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1582 00:45:33.667899 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1583 00:45:33.667975 ==
1584 00:45:33.671395 Dram Type= 6, Freq= 0, CH_1, rank 0
1585 00:45:33.674307 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1586 00:45:33.674383 ==
1587 00:45:33.688332 TX Vref=22, minBit 1, minWin=26, winSum=437
1588 00:45:33.691613 TX Vref=24, minBit 1, minWin=26, winSum=439
1589 00:45:33.695037 TX Vref=26, minBit 1, minWin=26, winSum=444
1590 00:45:33.698240 TX Vref=28, minBit 0, minWin=27, winSum=444
1591 00:45:33.702049 TX Vref=30, minBit 1, minWin=27, winSum=446
1592 00:45:33.705400 TX Vref=32, minBit 1, minWin=27, winSum=447
1593 00:45:33.711414 [TxChooseVref] Worse bit 1, Min win 27, Win sum 447, Final Vref 32
1594 00:45:33.711496
1595 00:45:33.714827 Final TX Range 1 Vref 32
1596 00:45:33.714908
1597 00:45:33.714967 ==
1598 00:45:33.718679 Dram Type= 6, Freq= 0, CH_1, rank 0
1599 00:45:33.721608 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1600 00:45:33.721687 ==
1601 00:45:33.721750
1602 00:45:33.721803
1603 00:45:33.725429 TX Vref Scan disable
1604 00:45:33.728419 == TX Byte 0 ==
1605 00:45:33.731611 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1606 00:45:33.735442 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1607 00:45:33.738126 == TX Byte 1 ==
1608 00:45:33.742067 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1609 00:45:33.745101 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1610 00:45:33.745167
1611 00:45:33.748176 [DATLAT]
1612 00:45:33.748244 Freq=800, CH1 RK0
1613 00:45:33.748299
1614 00:45:33.751471 DATLAT Default: 0xa
1615 00:45:33.751531 0, 0xFFFF, sum = 0
1616 00:45:33.754911 1, 0xFFFF, sum = 0
1617 00:45:33.754974 2, 0xFFFF, sum = 0
1618 00:45:33.758165 3, 0xFFFF, sum = 0
1619 00:45:33.758227 4, 0xFFFF, sum = 0
1620 00:45:33.761453 5, 0xFFFF, sum = 0
1621 00:45:33.761511 6, 0xFFFF, sum = 0
1622 00:45:33.765436 7, 0xFFFF, sum = 0
1623 00:45:33.765495 8, 0xFFFF, sum = 0
1624 00:45:33.768871 9, 0x0, sum = 1
1625 00:45:33.768937 10, 0x0, sum = 2
1626 00:45:33.771534 11, 0x0, sum = 3
1627 00:45:33.771593 12, 0x0, sum = 4
1628 00:45:33.775372 best_step = 10
1629 00:45:33.775440
1630 00:45:33.775493 ==
1631 00:45:33.778596 Dram Type= 6, Freq= 0, CH_1, rank 0
1632 00:45:33.781964 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1633 00:45:33.782032 ==
1634 00:45:33.785281 RX Vref Scan: 1
1635 00:45:33.785383
1636 00:45:33.785435 Set Vref Range= 32 -> 127
1637 00:45:33.785485
1638 00:45:33.788311 RX Vref 32 -> 127, step: 1
1639 00:45:33.788369
1640 00:45:33.792017 RX Delay -63 -> 252, step: 8
1641 00:45:33.792079
1642 00:45:33.794915 Set Vref, RX VrefLevel [Byte0]: 32
1643 00:45:33.798322 [Byte1]: 32
1644 00:45:33.798385
1645 00:45:33.801856 Set Vref, RX VrefLevel [Byte0]: 33
1646 00:45:33.805077 [Byte1]: 33
1647 00:45:33.808493
1648 00:45:33.808570 Set Vref, RX VrefLevel [Byte0]: 34
1649 00:45:33.811487 [Byte1]: 34
1650 00:45:33.816229
1651 00:45:33.816304 Set Vref, RX VrefLevel [Byte0]: 35
1652 00:45:33.818970 [Byte1]: 35
1653 00:45:33.823561
1654 00:45:33.823631 Set Vref, RX VrefLevel [Byte0]: 36
1655 00:45:33.826846 [Byte1]: 36
1656 00:45:33.830854
1657 00:45:33.830917 Set Vref, RX VrefLevel [Byte0]: 37
1658 00:45:33.833967 [Byte1]: 37
1659 00:45:33.838534
1660 00:45:33.838601 Set Vref, RX VrefLevel [Byte0]: 38
1661 00:45:33.841380 [Byte1]: 38
1662 00:45:33.845857
1663 00:45:33.845923 Set Vref, RX VrefLevel [Byte0]: 39
1664 00:45:33.849162 [Byte1]: 39
1665 00:45:33.853001
1666 00:45:33.853069 Set Vref, RX VrefLevel [Byte0]: 40
1667 00:45:33.856683 [Byte1]: 40
1668 00:45:33.860619
1669 00:45:33.860680 Set Vref, RX VrefLevel [Byte0]: 41
1670 00:45:33.863971 [Byte1]: 41
1671 00:45:33.868792
1672 00:45:33.868854 Set Vref, RX VrefLevel [Byte0]: 42
1673 00:45:33.871945 [Byte1]: 42
1674 00:45:33.875929
1675 00:45:33.875992 Set Vref, RX VrefLevel [Byte0]: 43
1676 00:45:33.879289 [Byte1]: 43
1677 00:45:33.883360
1678 00:45:33.883419 Set Vref, RX VrefLevel [Byte0]: 44
1679 00:45:33.886684 [Byte1]: 44
1680 00:45:33.890818
1681 00:45:33.890879 Set Vref, RX VrefLevel [Byte0]: 45
1682 00:45:33.894134 [Byte1]: 45
1683 00:45:33.898177
1684 00:45:33.898235 Set Vref, RX VrefLevel [Byte0]: 46
1685 00:45:33.901423 [Byte1]: 46
1686 00:45:33.905970
1687 00:45:33.906044 Set Vref, RX VrefLevel [Byte0]: 47
1688 00:45:33.909267 [Byte1]: 47
1689 00:45:33.913443
1690 00:45:33.913512 Set Vref, RX VrefLevel [Byte0]: 48
1691 00:45:33.916802 [Byte1]: 48
1692 00:45:33.920976
1693 00:45:33.921054 Set Vref, RX VrefLevel [Byte0]: 49
1694 00:45:33.923880 [Byte1]: 49
1695 00:45:33.928150
1696 00:45:33.928218 Set Vref, RX VrefLevel [Byte0]: 50
1697 00:45:33.931331 [Byte1]: 50
1698 00:45:33.936001
1699 00:45:33.936075 Set Vref, RX VrefLevel [Byte0]: 51
1700 00:45:33.939178 [Byte1]: 51
1701 00:45:33.943407
1702 00:45:33.943475 Set Vref, RX VrefLevel [Byte0]: 52
1703 00:45:33.946579 [Byte1]: 52
1704 00:45:33.951128
1705 00:45:33.951198 Set Vref, RX VrefLevel [Byte0]: 53
1706 00:45:33.954251 [Byte1]: 53
1707 00:45:33.958389
1708 00:45:33.958452 Set Vref, RX VrefLevel [Byte0]: 54
1709 00:45:33.961647 [Byte1]: 54
1710 00:45:33.965589
1711 00:45:33.965658 Set Vref, RX VrefLevel [Byte0]: 55
1712 00:45:33.969311 [Byte1]: 55
1713 00:45:33.973416
1714 00:45:33.973477 Set Vref, RX VrefLevel [Byte0]: 56
1715 00:45:33.976574 [Byte1]: 56
1716 00:45:33.980722
1717 00:45:33.980790 Set Vref, RX VrefLevel [Byte0]: 57
1718 00:45:33.984110 [Byte1]: 57
1719 00:45:33.988130
1720 00:45:33.988189 Set Vref, RX VrefLevel [Byte0]: 58
1721 00:45:33.991722 [Byte1]: 58
1722 00:45:33.995732
1723 00:45:33.995797 Set Vref, RX VrefLevel [Byte0]: 59
1724 00:45:33.999164 [Byte1]: 59
1725 00:45:34.003045
1726 00:45:34.003116 Set Vref, RX VrefLevel [Byte0]: 60
1727 00:45:34.006947 [Byte1]: 60
1728 00:45:34.011091
1729 00:45:34.011154 Set Vref, RX VrefLevel [Byte0]: 61
1730 00:45:34.014413 [Byte1]: 61
1731 00:45:34.018410
1732 00:45:34.018471 Set Vref, RX VrefLevel [Byte0]: 62
1733 00:45:34.021818 [Byte1]: 62
1734 00:45:34.025919
1735 00:45:34.025982 Set Vref, RX VrefLevel [Byte0]: 63
1736 00:45:34.029177 [Byte1]: 63
1737 00:45:34.033861
1738 00:45:34.033927 Set Vref, RX VrefLevel [Byte0]: 64
1739 00:45:34.037006 [Byte1]: 64
1740 00:45:34.040471
1741 00:45:34.040533 Set Vref, RX VrefLevel [Byte0]: 65
1742 00:45:34.044294 [Byte1]: 65
1743 00:45:34.048335
1744 00:45:34.048406 Set Vref, RX VrefLevel [Byte0]: 66
1745 00:45:34.051792 [Byte1]: 66
1746 00:45:34.055942
1747 00:45:34.056010 Set Vref, RX VrefLevel [Byte0]: 67
1748 00:45:34.059194 [Byte1]: 67
1749 00:45:34.063105
1750 00:45:34.063179 Set Vref, RX VrefLevel [Byte0]: 68
1751 00:45:34.066373 [Byte1]: 68
1752 00:45:34.071123
1753 00:45:34.071189 Set Vref, RX VrefLevel [Byte0]: 69
1754 00:45:34.074098 [Byte1]: 69
1755 00:45:34.078132
1756 00:45:34.078198 Set Vref, RX VrefLevel [Byte0]: 70
1757 00:45:34.081533 [Byte1]: 70
1758 00:45:34.085519
1759 00:45:34.085601 Set Vref, RX VrefLevel [Byte0]: 71
1760 00:45:34.089152 [Byte1]: 71
1761 00:45:34.093769
1762 00:45:34.093838 Set Vref, RX VrefLevel [Byte0]: 72
1763 00:45:34.096432 [Byte1]: 72
1764 00:45:34.100739
1765 00:45:34.100808 Set Vref, RX VrefLevel [Byte0]: 73
1766 00:45:34.104078 [Byte1]: 73
1767 00:45:34.108113
1768 00:45:34.108182 Set Vref, RX VrefLevel [Byte0]: 74
1769 00:45:34.111444 [Byte1]: 74
1770 00:45:34.115515
1771 00:45:34.115579 Set Vref, RX VrefLevel [Byte0]: 75
1772 00:45:34.118920 [Byte1]: 75
1773 00:45:34.123056
1774 00:45:34.123131 Set Vref, RX VrefLevel [Byte0]: 76
1775 00:45:34.126447 [Byte1]: 76
1776 00:45:34.130504
1777 00:45:34.130567 Final RX Vref Byte 0 = 54 to rank0
1778 00:45:34.133836 Final RX Vref Byte 1 = 54 to rank0
1779 00:45:34.137698 Final RX Vref Byte 0 = 54 to rank1
1780 00:45:34.141113 Final RX Vref Byte 1 = 54 to rank1==
1781 00:45:34.144454 Dram Type= 6, Freq= 0, CH_1, rank 0
1782 00:45:34.150884 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1783 00:45:34.150952 ==
1784 00:45:34.151008 DQS Delay:
1785 00:45:34.151060 DQS0 = 0, DQS1 = 0
1786 00:45:34.154055 DQM Delay:
1787 00:45:34.154121 DQM0 = 94, DQM1 = 89
1788 00:45:34.157233 DQ Delay:
1789 00:45:34.160640 DQ0 =96, DQ1 =88, DQ2 =84, DQ3 =88
1790 00:45:34.164035 DQ4 =96, DQ5 =108, DQ6 =104, DQ7 =92
1791 00:45:34.164095 DQ8 =80, DQ9 =80, DQ10 =88, DQ11 =84
1792 00:45:34.170483 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =96
1793 00:45:34.170551
1794 00:45:34.170605
1795 00:45:34.177670 [DQSOSCAuto] RK0, (LSB)MR18= 0x2e4a, (MSB)MR19= 0x606, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
1796 00:45:34.181021 CH1 RK0: MR19=606, MR18=2E4A
1797 00:45:34.187737 CH1_RK0: MR19=0x606, MR18=0x2E4A, DQSOSC=391, MR23=63, INC=96, DEC=64
1798 00:45:34.187801
1799 00:45:34.190810 ----->DramcWriteLeveling(PI) begin...
1800 00:45:34.190874 ==
1801 00:45:34.193904 Dram Type= 6, Freq= 0, CH_1, rank 1
1802 00:45:34.197437 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1803 00:45:34.197507 ==
1804 00:45:34.201045 Write leveling (Byte 0): 28 => 28
1805 00:45:34.204447 Write leveling (Byte 1): 29 => 29
1806 00:45:34.207696 DramcWriteLeveling(PI) end<-----
1807 00:45:34.207771
1808 00:45:34.207829 ==
1809 00:45:34.211128 Dram Type= 6, Freq= 0, CH_1, rank 1
1810 00:45:34.214045 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1811 00:45:34.214130 ==
1812 00:45:34.217258 [Gating] SW mode calibration
1813 00:45:34.224237 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1814 00:45:34.230623 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1815 00:45:34.233963 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1816 00:45:34.237272 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1817 00:45:34.244599 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 00:45:34.247271 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 00:45:34.251341 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 00:45:34.258011 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 00:45:34.261014 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 00:45:34.263997 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 00:45:34.271326 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 00:45:34.274356 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 00:45:34.277659 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 00:45:34.280934 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 00:45:34.287606 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 00:45:34.291056 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 00:45:34.294308 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 00:45:34.301302 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 00:45:34.304613 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1832 00:45:34.307804 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1833 00:45:34.314625 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1834 00:45:34.317774 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 00:45:34.321491 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 00:45:34.328166 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 00:45:34.331298 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 00:45:34.334267 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 00:45:34.340950 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 00:45:34.344284 0 9 4 | B1->B0 | 2929 2323 | 1 0 | (0 0) (0 0)
1841 00:45:34.347620 0 9 8 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
1842 00:45:34.351197 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1843 00:45:34.357941 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1844 00:45:34.361141 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1845 00:45:34.364536 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1846 00:45:34.371518 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1847 00:45:34.374577 0 10 0 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
1848 00:45:34.377802 0 10 4 | B1->B0 | 2a2a 2f2f | 1 1 | (1 0) (1 1)
1849 00:45:34.384632 0 10 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
1850 00:45:34.388073 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1851 00:45:34.391442 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1852 00:45:34.398086 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1853 00:45:34.401409 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1854 00:45:34.405322 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1855 00:45:34.408556 0 11 0 | B1->B0 | 2726 2323 | 1 0 | (0 0) (0 0)
1856 00:45:34.415282 0 11 4 | B1->B0 | 3c3c 2e2e | 1 0 | (0 0) (1 1)
1857 00:45:34.418705 0 11 8 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
1858 00:45:34.422154 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1859 00:45:34.428493 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1860 00:45:34.431735 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1861 00:45:34.435577 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1862 00:45:34.441995 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1863 00:45:34.445159 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1864 00:45:34.448486 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1865 00:45:34.455082 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1866 00:45:34.458441 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 00:45:34.461566 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1868 00:45:34.468612 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1869 00:45:34.471631 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 00:45:34.475022 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 00:45:34.482055 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 00:45:34.484860 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 00:45:34.488257 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 00:45:34.491549 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 00:45:34.498793 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 00:45:34.502122 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1877 00:45:34.505440 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1878 00:45:34.512118 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1879 00:45:34.515318 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1880 00:45:34.518674 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1881 00:45:34.522059 Total UI for P1: 0, mck2ui 16
1882 00:45:34.525376 best dqsien dly found for B1: ( 0, 14, 2)
1883 00:45:34.532032 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1884 00:45:34.535257 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1885 00:45:34.538662 Total UI for P1: 0, mck2ui 16
1886 00:45:34.541913 best dqsien dly found for B0: ( 0, 14, 6)
1887 00:45:34.545260 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1888 00:45:34.548649 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1889 00:45:34.548710
1890 00:45:34.552222 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1891 00:45:34.555126 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1892 00:45:34.558458 [Gating] SW calibration Done
1893 00:45:34.558521 ==
1894 00:45:34.562423 Dram Type= 6, Freq= 0, CH_1, rank 1
1895 00:45:34.565653 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1896 00:45:34.565719 ==
1897 00:45:34.568947 RX Vref Scan: 0
1898 00:45:34.569011
1899 00:45:34.572230 RX Vref 0 -> 0, step: 1
1900 00:45:34.572340
1901 00:45:34.572401 RX Delay -130 -> 252, step: 16
1902 00:45:34.578846 iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208
1903 00:45:34.582399 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1904 00:45:34.585617 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1905 00:45:34.588899 iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208
1906 00:45:34.592006 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1907 00:45:34.598811 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1908 00:45:34.602380 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1909 00:45:34.605763 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1910 00:45:34.608833 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1911 00:45:34.611885 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1912 00:45:34.618751 iDelay=222, Bit 10, Center 93 (-18 ~ 205) 224
1913 00:45:34.622523 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1914 00:45:34.625353 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1915 00:45:34.629090 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1916 00:45:34.632521 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1917 00:45:34.639210 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1918 00:45:34.639286 ==
1919 00:45:34.642468 Dram Type= 6, Freq= 0, CH_1, rank 1
1920 00:45:34.645852 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1921 00:45:34.645927 ==
1922 00:45:34.645985 DQS Delay:
1923 00:45:34.649192 DQS0 = 0, DQS1 = 0
1924 00:45:34.649266 DQM Delay:
1925 00:45:34.652586 DQM0 = 92, DQM1 = 87
1926 00:45:34.652661 DQ Delay:
1927 00:45:34.655787 DQ0 =101, DQ1 =85, DQ2 =77, DQ3 =85
1928 00:45:34.659020 DQ4 =85, DQ5 =109, DQ6 =101, DQ7 =93
1929 00:45:34.662424 DQ8 =77, DQ9 =77, DQ10 =93, DQ11 =77
1930 00:45:34.665770 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1931 00:45:34.665845
1932 00:45:34.665903
1933 00:45:34.665958 ==
1934 00:45:34.668679 Dram Type= 6, Freq= 0, CH_1, rank 1
1935 00:45:34.671907 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1936 00:45:34.671982 ==
1937 00:45:34.675685
1938 00:45:34.675760
1939 00:45:34.675818 TX Vref Scan disable
1940 00:45:34.678828 == TX Byte 0 ==
1941 00:45:34.682106 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1942 00:45:34.685556 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1943 00:45:34.688874 == TX Byte 1 ==
1944 00:45:34.692265 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1945 00:45:34.695668 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1946 00:45:34.695743 ==
1947 00:45:34.698775 Dram Type= 6, Freq= 0, CH_1, rank 1
1948 00:45:34.705348 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1949 00:45:34.705424 ==
1950 00:45:34.717369 TX Vref=22, minBit 1, minWin=26, winSum=442
1951 00:45:34.720513 TX Vref=24, minBit 0, minWin=27, winSum=446
1952 00:45:34.724261 TX Vref=26, minBit 0, minWin=27, winSum=448
1953 00:45:34.727174 TX Vref=28, minBit 2, minWin=27, winSum=452
1954 00:45:34.730551 TX Vref=30, minBit 2, minWin=27, winSum=453
1955 00:45:34.734278 TX Vref=32, minBit 2, minWin=27, winSum=449
1956 00:45:34.740841 [TxChooseVref] Worse bit 2, Min win 27, Win sum 453, Final Vref 30
1957 00:45:34.740916
1958 00:45:34.744409 Final TX Range 1 Vref 30
1959 00:45:34.744484
1960 00:45:34.744542 ==
1961 00:45:34.747626 Dram Type= 6, Freq= 0, CH_1, rank 1
1962 00:45:34.750679 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1963 00:45:34.750755 ==
1964 00:45:34.750813
1965 00:45:34.750867
1966 00:45:34.754288 TX Vref Scan disable
1967 00:45:34.757426 == TX Byte 0 ==
1968 00:45:34.760711 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1969 00:45:34.764059 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1970 00:45:34.767545 == TX Byte 1 ==
1971 00:45:34.771177 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1972 00:45:34.774284 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1973 00:45:34.774359
1974 00:45:34.777309 [DATLAT]
1975 00:45:34.777385 Freq=800, CH1 RK1
1976 00:45:34.777443
1977 00:45:34.780890 DATLAT Default: 0xa
1978 00:45:34.780965 0, 0xFFFF, sum = 0
1979 00:45:34.784449 1, 0xFFFF, sum = 0
1980 00:45:34.784526 2, 0xFFFF, sum = 0
1981 00:45:34.787428 3, 0xFFFF, sum = 0
1982 00:45:34.787504 4, 0xFFFF, sum = 0
1983 00:45:34.790806 5, 0xFFFF, sum = 0
1984 00:45:34.790882 6, 0xFFFF, sum = 0
1985 00:45:34.794127 7, 0xFFFF, sum = 0
1986 00:45:34.794203 8, 0xFFFF, sum = 0
1987 00:45:34.797334 9, 0x0, sum = 1
1988 00:45:34.797410 10, 0x0, sum = 2
1989 00:45:34.800798 11, 0x0, sum = 3
1990 00:45:34.800873 12, 0x0, sum = 4
1991 00:45:34.804048 best_step = 10
1992 00:45:34.804141
1993 00:45:34.804223 ==
1994 00:45:34.807285 Dram Type= 6, Freq= 0, CH_1, rank 1
1995 00:45:34.810680 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1996 00:45:34.810755 ==
1997 00:45:34.814038 RX Vref Scan: 0
1998 00:45:34.814115
1999 00:45:34.814172 RX Vref 0 -> 0, step: 1
2000 00:45:34.814226
2001 00:45:34.817441 RX Delay -79 -> 252, step: 8
2002 00:45:34.824108 iDelay=209, Bit 0, Center 104 (9 ~ 200) 192
2003 00:45:34.828077 iDelay=209, Bit 1, Center 92 (-7 ~ 192) 200
2004 00:45:34.830688 iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200
2005 00:45:34.834044 iDelay=209, Bit 3, Center 92 (-7 ~ 192) 200
2006 00:45:34.837370 iDelay=209, Bit 4, Center 92 (-7 ~ 192) 200
2007 00:45:34.841222 iDelay=209, Bit 5, Center 108 (9 ~ 208) 200
2008 00:45:34.847371 iDelay=209, Bit 6, Center 108 (9 ~ 208) 200
2009 00:45:34.850796 iDelay=209, Bit 7, Center 96 (-7 ~ 200) 208
2010 00:45:34.854647 iDelay=209, Bit 8, Center 80 (-23 ~ 184) 208
2011 00:45:34.857828 iDelay=209, Bit 9, Center 80 (-23 ~ 184) 208
2012 00:45:34.860764 iDelay=209, Bit 10, Center 92 (-15 ~ 200) 216
2013 00:45:34.864232 iDelay=209, Bit 11, Center 88 (-15 ~ 192) 208
2014 00:45:34.871201 iDelay=209, Bit 12, Center 100 (-7 ~ 208) 216
2015 00:45:34.874540 iDelay=209, Bit 13, Center 96 (-7 ~ 200) 208
2016 00:45:34.877867 iDelay=209, Bit 14, Center 96 (-7 ~ 200) 208
2017 00:45:34.880892 iDelay=209, Bit 15, Center 96 (-7 ~ 200) 208
2018 00:45:34.880970 ==
2019 00:45:34.884197 Dram Type= 6, Freq= 0, CH_1, rank 1
2020 00:45:34.890991 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2021 00:45:34.891066 ==
2022 00:45:34.891130 DQS Delay:
2023 00:45:34.891184 DQS0 = 0, DQS1 = 0
2024 00:45:34.894575 DQM Delay:
2025 00:45:34.894649 DQM0 = 97, DQM1 = 91
2026 00:45:34.897480 DQ Delay:
2027 00:45:34.901380 DQ0 =104, DQ1 =92, DQ2 =84, DQ3 =92
2028 00:45:34.904753 DQ4 =92, DQ5 =108, DQ6 =108, DQ7 =96
2029 00:45:34.908148 DQ8 =80, DQ9 =80, DQ10 =92, DQ11 =88
2030 00:45:34.911264 DQ12 =100, DQ13 =96, DQ14 =96, DQ15 =96
2031 00:45:34.911330
2032 00:45:34.911390
2033 00:45:34.917795 [DQSOSCAuto] RK1, (LSB)MR18= 0x4b15, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 391 ps
2034 00:45:34.921075 CH1 RK1: MR19=606, MR18=4B15
2035 00:45:34.927560 CH1_RK1: MR19=0x606, MR18=0x4B15, DQSOSC=391, MR23=63, INC=96, DEC=64
2036 00:45:34.930995 [RxdqsGatingPostProcess] freq 800
2037 00:45:34.934445 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2038 00:45:34.937851 Pre-setting of DQS Precalculation
2039 00:45:34.944645 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2040 00:45:34.951299 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2041 00:45:34.958091 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2042 00:45:34.958162
2043 00:45:34.958219
2044 00:45:34.961127 [Calibration Summary] 1600 Mbps
2045 00:45:34.961193 CH 0, Rank 0
2046 00:45:34.964376 SW Impedance : PASS
2047 00:45:34.967628 DUTY Scan : NO K
2048 00:45:34.967687 ZQ Calibration : PASS
2049 00:45:34.971557 Jitter Meter : NO K
2050 00:45:34.974951 CBT Training : PASS
2051 00:45:34.975014 Write leveling : PASS
2052 00:45:34.978247 RX DQS gating : PASS
2053 00:45:34.978312 RX DQ/DQS(RDDQC) : PASS
2054 00:45:34.981476 TX DQ/DQS : PASS
2055 00:45:34.984587 RX DATLAT : PASS
2056 00:45:34.984657 RX DQ/DQS(Engine): PASS
2057 00:45:34.988074 TX OE : NO K
2058 00:45:34.988138 All Pass.
2059 00:45:34.988191
2060 00:45:34.991436 CH 0, Rank 1
2061 00:45:34.991500 SW Impedance : PASS
2062 00:45:34.995084 DUTY Scan : NO K
2063 00:45:34.997971 ZQ Calibration : PASS
2064 00:45:34.998034 Jitter Meter : NO K
2065 00:45:35.001626 CBT Training : PASS
2066 00:45:35.004629 Write leveling : PASS
2067 00:45:35.004697 RX DQS gating : PASS
2068 00:45:35.008000 RX DQ/DQS(RDDQC) : PASS
2069 00:45:35.011723 TX DQ/DQS : PASS
2070 00:45:35.011794 RX DATLAT : PASS
2071 00:45:35.014693 RX DQ/DQS(Engine): PASS
2072 00:45:35.014761 TX OE : NO K
2073 00:45:35.017873 All Pass.
2074 00:45:35.017938
2075 00:45:35.017995 CH 1, Rank 0
2076 00:45:35.021528 SW Impedance : PASS
2077 00:45:35.021639 DUTY Scan : NO K
2078 00:45:35.024564 ZQ Calibration : PASS
2079 00:45:35.028519 Jitter Meter : NO K
2080 00:45:35.028586 CBT Training : PASS
2081 00:45:35.031824 Write leveling : PASS
2082 00:45:35.035007 RX DQS gating : PASS
2083 00:45:35.035074 RX DQ/DQS(RDDQC) : PASS
2084 00:45:35.038452 TX DQ/DQS : PASS
2085 00:45:35.041723 RX DATLAT : PASS
2086 00:45:35.041786 RX DQ/DQS(Engine): PASS
2087 00:45:35.045157 TX OE : NO K
2088 00:45:35.045222 All Pass.
2089 00:45:35.045274
2090 00:45:35.045324 CH 1, Rank 1
2091 00:45:35.048461 SW Impedance : PASS
2092 00:45:35.051837 DUTY Scan : NO K
2093 00:45:35.051903 ZQ Calibration : PASS
2094 00:45:35.055247 Jitter Meter : NO K
2095 00:45:35.058523 CBT Training : PASS
2096 00:45:35.058584 Write leveling : PASS
2097 00:45:35.061564 RX DQS gating : PASS
2098 00:45:35.065278 RX DQ/DQS(RDDQC) : PASS
2099 00:45:35.065341 TX DQ/DQS : PASS
2100 00:45:35.068974 RX DATLAT : PASS
2101 00:45:35.072081 RX DQ/DQS(Engine): PASS
2102 00:45:35.072146 TX OE : NO K
2103 00:45:35.072201 All Pass.
2104 00:45:35.075102
2105 00:45:35.075161 DramC Write-DBI off
2106 00:45:35.078397 PER_BANK_REFRESH: Hybrid Mode
2107 00:45:35.078459 TX_TRACKING: ON
2108 00:45:35.081672 [GetDramInforAfterCalByMRR] Vendor 6.
2109 00:45:35.085067 [GetDramInforAfterCalByMRR] Revision 606.
2110 00:45:35.091821 [GetDramInforAfterCalByMRR] Revision 2 0.
2111 00:45:35.091889 MR0 0x3b3b
2112 00:45:35.091943 MR8 0x5151
2113 00:45:35.095191 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2114 00:45:35.095254
2115 00:45:35.098554 MR0 0x3b3b
2116 00:45:35.098614 MR8 0x5151
2117 00:45:35.101858 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2118 00:45:35.101920
2119 00:45:35.112018 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2120 00:45:35.115483 [FAST_K] Save calibration result to emmc
2121 00:45:35.118799 [FAST_K] Save calibration result to emmc
2122 00:45:35.122151 dram_init: config_dvfs: 1
2123 00:45:35.125447 dramc_set_vcore_voltage set vcore to 662500
2124 00:45:35.125539 Read voltage for 1200, 2
2125 00:45:35.128770 Vio18 = 0
2126 00:45:35.128845 Vcore = 662500
2127 00:45:35.128902 Vdram = 0
2128 00:45:35.132719 Vddq = 0
2129 00:45:35.132795 Vmddr = 0
2130 00:45:35.135473 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2131 00:45:35.142077 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2132 00:45:35.145543 MEM_TYPE=3, freq_sel=15
2133 00:45:35.149316 sv_algorithm_assistance_LP4_1600
2134 00:45:35.152151 ============ PULL DRAM RESETB DOWN ============
2135 00:45:35.155359 ========== PULL DRAM RESETB DOWN end =========
2136 00:45:35.159558 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2137 00:45:35.162154 ===================================
2138 00:45:35.165472 LPDDR4 DRAM CONFIGURATION
2139 00:45:35.168897 ===================================
2140 00:45:35.172603 EX_ROW_EN[0] = 0x0
2141 00:45:35.172678 EX_ROW_EN[1] = 0x0
2142 00:45:35.175606 LP4Y_EN = 0x0
2143 00:45:35.175681 WORK_FSP = 0x0
2144 00:45:35.179310 WL = 0x4
2145 00:45:35.179385 RL = 0x4
2146 00:45:35.182318 BL = 0x2
2147 00:45:35.182393 RPST = 0x0
2148 00:45:35.185885 RD_PRE = 0x0
2149 00:45:35.185959 WR_PRE = 0x1
2150 00:45:35.189155 WR_PST = 0x0
2151 00:45:35.189230 DBI_WR = 0x0
2152 00:45:35.192586 DBI_RD = 0x0
2153 00:45:35.192660 OTF = 0x1
2154 00:45:35.196028 ===================================
2155 00:45:35.199310 ===================================
2156 00:45:35.202664 ANA top config
2157 00:45:35.206130 ===================================
2158 00:45:35.209450 DLL_ASYNC_EN = 0
2159 00:45:35.209525 ALL_SLAVE_EN = 0
2160 00:45:35.212767 NEW_RANK_MODE = 1
2161 00:45:35.216037 DLL_IDLE_MODE = 1
2162 00:45:35.219356 LP45_APHY_COMB_EN = 1
2163 00:45:35.219431 TX_ODT_DIS = 1
2164 00:45:35.222602 NEW_8X_MODE = 1
2165 00:45:35.225835 ===================================
2166 00:45:35.229530 ===================================
2167 00:45:35.232574 data_rate = 2400
2168 00:45:35.235988 CKR = 1
2169 00:45:35.239413 DQ_P2S_RATIO = 8
2170 00:45:35.243050 ===================================
2171 00:45:35.243115 CA_P2S_RATIO = 8
2172 00:45:35.245988 DQ_CA_OPEN = 0
2173 00:45:35.249525 DQ_SEMI_OPEN = 0
2174 00:45:35.252518 CA_SEMI_OPEN = 0
2175 00:45:35.256075 CA_FULL_RATE = 0
2176 00:45:35.259169 DQ_CKDIV4_EN = 0
2177 00:45:35.259235 CA_CKDIV4_EN = 0
2178 00:45:35.262601 CA_PREDIV_EN = 0
2179 00:45:35.265992 PH8_DLY = 17
2180 00:45:35.269448 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2181 00:45:35.272601 DQ_AAMCK_DIV = 4
2182 00:45:35.276408 CA_AAMCK_DIV = 4
2183 00:45:35.276475 CA_ADMCK_DIV = 4
2184 00:45:35.279495 DQ_TRACK_CA_EN = 0
2185 00:45:35.282492 CA_PICK = 1200
2186 00:45:35.286148 CA_MCKIO = 1200
2187 00:45:35.289196 MCKIO_SEMI = 0
2188 00:45:35.292408 PLL_FREQ = 2366
2189 00:45:35.296172 DQ_UI_PI_RATIO = 32
2190 00:45:35.296243 CA_UI_PI_RATIO = 0
2191 00:45:35.299590 ===================================
2192 00:45:35.303073 ===================================
2193 00:45:35.306437 memory_type:LPDDR4
2194 00:45:35.309674 GP_NUM : 10
2195 00:45:35.309744 SRAM_EN : 1
2196 00:45:35.313088 MD32_EN : 0
2197 00:45:35.316360 ===================================
2198 00:45:35.319676 [ANA_INIT] >>>>>>>>>>>>>>
2199 00:45:35.323025 <<<<<< [CONFIGURE PHASE]: ANA_TX
2200 00:45:35.326288 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2201 00:45:35.329430 ===================================
2202 00:45:35.329497 data_rate = 2400,PCW = 0X5b00
2203 00:45:35.332625 ===================================
2204 00:45:35.336471 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2205 00:45:35.343016 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2206 00:45:35.349712 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2207 00:45:35.352990 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2208 00:45:35.356693 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2209 00:45:35.359867 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2210 00:45:35.363082 [ANA_INIT] flow start
2211 00:45:35.363151 [ANA_INIT] PLL >>>>>>>>
2212 00:45:35.366113 [ANA_INIT] PLL <<<<<<<<
2213 00:45:35.369497 [ANA_INIT] MIDPI >>>>>>>>
2214 00:45:35.373322 [ANA_INIT] MIDPI <<<<<<<<
2215 00:45:35.373394 [ANA_INIT] DLL >>>>>>>>
2216 00:45:35.376396 [ANA_INIT] DLL <<<<<<<<
2217 00:45:35.376463 [ANA_INIT] flow end
2218 00:45:35.383012 ============ LP4 DIFF to SE enter ============
2219 00:45:35.386254 ============ LP4 DIFF to SE exit ============
2220 00:45:35.389470 [ANA_INIT] <<<<<<<<<<<<<
2221 00:45:35.393073 [Flow] Enable top DCM control >>>>>
2222 00:45:35.396310 [Flow] Enable top DCM control <<<<<
2223 00:45:35.396381 Enable DLL master slave shuffle
2224 00:45:35.402848 ==============================================================
2225 00:45:35.406512 Gating Mode config
2226 00:45:35.409536 ==============================================================
2227 00:45:35.413097 Config description:
2228 00:45:35.423100 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2229 00:45:35.429843 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2230 00:45:35.433052 SELPH_MODE 0: By rank 1: By Phase
2231 00:45:35.439924 ==============================================================
2232 00:45:35.443235 GAT_TRACK_EN = 1
2233 00:45:35.446709 RX_GATING_MODE = 2
2234 00:45:35.450053 RX_GATING_TRACK_MODE = 2
2235 00:45:35.450130 SELPH_MODE = 1
2236 00:45:35.453446 PICG_EARLY_EN = 1
2237 00:45:35.456650 VALID_LAT_VALUE = 1
2238 00:45:35.463177 ==============================================================
2239 00:45:35.466293 Enter into Gating configuration >>>>
2240 00:45:35.469931 Exit from Gating configuration <<<<
2241 00:45:35.473322 Enter into DVFS_PRE_config >>>>>
2242 00:45:35.483091 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2243 00:45:35.486204 Exit from DVFS_PRE_config <<<<<
2244 00:45:35.489634 Enter into PICG configuration >>>>
2245 00:45:35.492972 Exit from PICG configuration <<<<
2246 00:45:35.496192 [RX_INPUT] configuration >>>>>
2247 00:45:35.499444 [RX_INPUT] configuration <<<<<
2248 00:45:35.502897 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2249 00:45:35.509584 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2250 00:45:35.516673 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2251 00:45:35.523269 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2252 00:45:35.526440 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2253 00:45:35.533120 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2254 00:45:35.536721 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2255 00:45:35.543218 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2256 00:45:35.546347 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2257 00:45:35.550011 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2258 00:45:35.553237 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2259 00:45:35.559958 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2260 00:45:35.563358 ===================================
2261 00:45:35.563423 LPDDR4 DRAM CONFIGURATION
2262 00:45:35.566518 ===================================
2263 00:45:35.569750 EX_ROW_EN[0] = 0x0
2264 00:45:35.573125 EX_ROW_EN[1] = 0x0
2265 00:45:35.573187 LP4Y_EN = 0x0
2266 00:45:35.576467 WORK_FSP = 0x0
2267 00:45:35.576529 WL = 0x4
2268 00:45:35.579648 RL = 0x4
2269 00:45:35.579712 BL = 0x2
2270 00:45:35.583176 RPST = 0x0
2271 00:45:35.583240 RD_PRE = 0x0
2272 00:45:35.586646 WR_PRE = 0x1
2273 00:45:35.586710 WR_PST = 0x0
2274 00:45:35.589944 DBI_WR = 0x0
2275 00:45:35.590010 DBI_RD = 0x0
2276 00:45:35.593145 OTF = 0x1
2277 00:45:35.596501 ===================================
2278 00:45:35.599830 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2279 00:45:35.603031 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2280 00:45:35.609770 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2281 00:45:35.613111 ===================================
2282 00:45:35.613177 LPDDR4 DRAM CONFIGURATION
2283 00:45:35.616419 ===================================
2284 00:45:35.619594 EX_ROW_EN[0] = 0x10
2285 00:45:35.619663 EX_ROW_EN[1] = 0x0
2286 00:45:35.623084 LP4Y_EN = 0x0
2287 00:45:35.623152 WORK_FSP = 0x0
2288 00:45:35.626341 WL = 0x4
2289 00:45:35.626408 RL = 0x4
2290 00:45:35.630024 BL = 0x2
2291 00:45:35.633157 RPST = 0x0
2292 00:45:35.633224 RD_PRE = 0x0
2293 00:45:35.636369 WR_PRE = 0x1
2294 00:45:35.636432 WR_PST = 0x0
2295 00:45:35.639887 DBI_WR = 0x0
2296 00:45:35.639956 DBI_RD = 0x0
2297 00:45:35.643234 OTF = 0x1
2298 00:45:35.646247 ===================================
2299 00:45:35.649719 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2300 00:45:35.652893 ==
2301 00:45:35.656226 Dram Type= 6, Freq= 0, CH_0, rank 0
2302 00:45:35.659761 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2303 00:45:35.659860 ==
2304 00:45:35.663445 [Duty_Offset_Calibration]
2305 00:45:35.663553 B0:2 B1:1 CA:1
2306 00:45:35.663642
2307 00:45:35.666751 [DutyScan_Calibration_Flow] k_type=0
2308 00:45:35.676026
2309 00:45:35.676114 ==CLK 0==
2310 00:45:35.679378 Final CLK duty delay cell = 0
2311 00:45:35.682753 [0] MAX Duty = 5187%(X100), DQS PI = 24
2312 00:45:35.686085 [0] MIN Duty = 4844%(X100), DQS PI = 48
2313 00:45:35.686172 [0] AVG Duty = 5015%(X100)
2314 00:45:35.689368
2315 00:45:35.692652 CH0 CLK Duty spec in!! Max-Min= 343%
2316 00:45:35.695913 [DutyScan_Calibration_Flow] ====Done====
2317 00:45:35.696007
2318 00:45:35.699037 [DutyScan_Calibration_Flow] k_type=1
2319 00:45:35.714284
2320 00:45:35.714387 ==DQS 0 ==
2321 00:45:35.717535 Final DQS duty delay cell = -4
2322 00:45:35.720949 [-4] MAX Duty = 5124%(X100), DQS PI = 24
2323 00:45:35.724241 [-4] MIN Duty = 4751%(X100), DQS PI = 62
2324 00:45:35.728196 [-4] AVG Duty = 4937%(X100)
2325 00:45:35.728298
2326 00:45:35.728382 ==DQS 1 ==
2327 00:45:35.730946 Final DQS duty delay cell = 0
2328 00:45:35.734803 [0] MAX Duty = 5156%(X100), DQS PI = 0
2329 00:45:35.738109 [0] MIN Duty = 5000%(X100), DQS PI = 32
2330 00:45:35.741509 [0] AVG Duty = 5078%(X100)
2331 00:45:35.741623
2332 00:45:35.744670 CH0 DQS 0 Duty spec in!! Max-Min= 373%
2333 00:45:35.744743
2334 00:45:35.748049 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2335 00:45:35.751260 [DutyScan_Calibration_Flow] ====Done====
2336 00:45:35.751334
2337 00:45:35.754600 [DutyScan_Calibration_Flow] k_type=3
2338 00:45:35.771112
2339 00:45:35.771186 ==DQM 0 ==
2340 00:45:35.774742 Final DQM duty delay cell = 0
2341 00:45:35.777974 [0] MAX Duty = 5156%(X100), DQS PI = 30
2342 00:45:35.781253 [0] MIN Duty = 4907%(X100), DQS PI = 56
2343 00:45:35.781327 [0] AVG Duty = 5031%(X100)
2344 00:45:35.784735
2345 00:45:35.784809 ==DQM 1 ==
2346 00:45:35.788173 Final DQM duty delay cell = 0
2347 00:45:35.791601 [0] MAX Duty = 5093%(X100), DQS PI = 0
2348 00:45:35.794915 [0] MIN Duty = 5031%(X100), DQS PI = 14
2349 00:45:35.794990 [0] AVG Duty = 5062%(X100)
2350 00:45:35.798263
2351 00:45:35.801624 CH0 DQM 0 Duty spec in!! Max-Min= 249%
2352 00:45:35.801699
2353 00:45:35.805035 CH0 DQM 1 Duty spec in!! Max-Min= 62%
2354 00:45:35.808271 [DutyScan_Calibration_Flow] ====Done====
2355 00:45:35.808355
2356 00:45:35.811370 [DutyScan_Calibration_Flow] k_type=2
2357 00:45:35.827655
2358 00:45:35.827731 ==DQ 0 ==
2359 00:45:35.831217 Final DQ duty delay cell = 0
2360 00:45:35.834796 [0] MAX Duty = 5062%(X100), DQS PI = 32
2361 00:45:35.837905 [0] MIN Duty = 4844%(X100), DQS PI = 62
2362 00:45:35.837980 [0] AVG Duty = 4953%(X100)
2363 00:45:35.838039
2364 00:45:35.841629 ==DQ 1 ==
2365 00:45:35.841704 Final DQ duty delay cell = 0
2366 00:45:35.847756 [0] MAX Duty = 5093%(X100), DQS PI = 24
2367 00:45:35.851629 [0] MIN Duty = 4907%(X100), DQS PI = 36
2368 00:45:35.851705 [0] AVG Duty = 5000%(X100)
2369 00:45:35.851764
2370 00:45:35.855011 CH0 DQ 0 Duty spec in!! Max-Min= 218%
2371 00:45:35.855086
2372 00:45:35.858453 CH0 DQ 1 Duty spec in!! Max-Min= 186%
2373 00:45:35.864401 [DutyScan_Calibration_Flow] ====Done====
2374 00:45:35.864477 ==
2375 00:45:35.868064 Dram Type= 6, Freq= 0, CH_1, rank 0
2376 00:45:35.871537 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2377 00:45:35.871605 ==
2378 00:45:35.874908 [Duty_Offset_Calibration]
2379 00:45:35.874973 B0:1 B1:0 CA:0
2380 00:45:35.875028
2381 00:45:35.878157 [DutyScan_Calibration_Flow] k_type=0
2382 00:45:35.886955
2383 00:45:35.887019 ==CLK 0==
2384 00:45:35.890248 Final CLK duty delay cell = -4
2385 00:45:35.893526 [-4] MAX Duty = 5000%(X100), DQS PI = 20
2386 00:45:35.896877 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2387 00:45:35.900097 [-4] AVG Duty = 4953%(X100)
2388 00:45:35.900161
2389 00:45:35.903938 CH1 CLK Duty spec in!! Max-Min= 93%
2390 00:45:35.907344 [DutyScan_Calibration_Flow] ====Done====
2391 00:45:35.907411
2392 00:45:35.910059 [DutyScan_Calibration_Flow] k_type=1
2393 00:45:35.926353
2394 00:45:35.926451 ==DQS 0 ==
2395 00:45:35.929919 Final DQS duty delay cell = 0
2396 00:45:35.933323 [0] MAX Duty = 5062%(X100), DQS PI = 22
2397 00:45:35.936408 [0] MIN Duty = 4875%(X100), DQS PI = 0
2398 00:45:35.936475 [0] AVG Duty = 4968%(X100)
2399 00:45:35.940068
2400 00:45:35.940132 ==DQS 1 ==
2401 00:45:35.943025 Final DQS duty delay cell = 0
2402 00:45:35.946479 [0] MAX Duty = 5187%(X100), DQS PI = 18
2403 00:45:35.950148 [0] MIN Duty = 4938%(X100), DQS PI = 58
2404 00:45:35.950219 [0] AVG Duty = 5062%(X100)
2405 00:45:35.953089
2406 00:45:35.956711 CH1 DQS 0 Duty spec in!! Max-Min= 187%
2407 00:45:35.956777
2408 00:45:35.959977 CH1 DQS 1 Duty spec in!! Max-Min= 249%
2409 00:45:35.963416 [DutyScan_Calibration_Flow] ====Done====
2410 00:45:35.963479
2411 00:45:35.966771 [DutyScan_Calibration_Flow] k_type=3
2412 00:45:35.982929
2413 00:45:35.982993 ==DQM 0 ==
2414 00:45:35.986161 Final DQM duty delay cell = 0
2415 00:45:35.989475 [0] MAX Duty = 5156%(X100), DQS PI = 6
2416 00:45:35.992824 [0] MIN Duty = 5031%(X100), DQS PI = 0
2417 00:45:35.996264 [0] AVG Duty = 5093%(X100)
2418 00:45:35.996326
2419 00:45:35.996379 ==DQM 1 ==
2420 00:45:35.999566 Final DQM duty delay cell = 0
2421 00:45:36.003104 [0] MAX Duty = 5031%(X100), DQS PI = 26
2422 00:45:36.006205 [0] MIN Duty = 4875%(X100), DQS PI = 36
2423 00:45:36.010005 [0] AVG Duty = 4953%(X100)
2424 00:45:36.010095
2425 00:45:36.012694 CH1 DQM 0 Duty spec in!! Max-Min= 125%
2426 00:45:36.012752
2427 00:45:36.015950 CH1 DQM 1 Duty spec in!! Max-Min= 156%
2428 00:45:36.019200 [DutyScan_Calibration_Flow] ====Done====
2429 00:45:36.019261
2430 00:45:36.022454 [DutyScan_Calibration_Flow] k_type=2
2431 00:45:36.038834
2432 00:45:36.038910 ==DQ 0 ==
2433 00:45:36.042197 Final DQ duty delay cell = -4
2434 00:45:36.045511 [-4] MAX Duty = 5062%(X100), DQS PI = 8
2435 00:45:36.048786 [-4] MIN Duty = 4906%(X100), DQS PI = 44
2436 00:45:36.051987 [-4] AVG Duty = 4984%(X100)
2437 00:45:36.052054
2438 00:45:36.052113 ==DQ 1 ==
2439 00:45:36.055600 Final DQ duty delay cell = 0
2440 00:45:36.058684 [0] MAX Duty = 5125%(X100), DQS PI = 20
2441 00:45:36.062387 [0] MIN Duty = 4969%(X100), DQS PI = 12
2442 00:45:36.062452 [0] AVG Duty = 5047%(X100)
2443 00:45:36.062511
2444 00:45:36.065826 CH1 DQ 0 Duty spec in!! Max-Min= 156%
2445 00:45:36.068695
2446 00:45:36.072584 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2447 00:45:36.075906 [DutyScan_Calibration_Flow] ====Done====
2448 00:45:36.079145 nWR fixed to 30
2449 00:45:36.079209 [ModeRegInit_LP4] CH0 RK0
2450 00:45:36.082614 [ModeRegInit_LP4] CH0 RK1
2451 00:45:36.085887 [ModeRegInit_LP4] CH1 RK0
2452 00:45:36.089030 [ModeRegInit_LP4] CH1 RK1
2453 00:45:36.089088 match AC timing 7
2454 00:45:36.092363 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2455 00:45:36.098997 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2456 00:45:36.102308 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2457 00:45:36.105674 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2458 00:45:36.112422 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2459 00:45:36.112488 ==
2460 00:45:36.115837 Dram Type= 6, Freq= 0, CH_0, rank 0
2461 00:45:36.119271 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2462 00:45:36.119331 ==
2463 00:45:36.125864 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2464 00:45:36.129051 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2465 00:45:36.138993 [CA 0] Center 39 (8~70) winsize 63
2466 00:45:36.142591 [CA 1] Center 39 (8~70) winsize 63
2467 00:45:36.145616 [CA 2] Center 35 (5~66) winsize 62
2468 00:45:36.149086 [CA 3] Center 34 (4~65) winsize 62
2469 00:45:36.152247 [CA 4] Center 33 (3~64) winsize 62
2470 00:45:36.155754 [CA 5] Center 32 (3~62) winsize 60
2471 00:45:36.155821
2472 00:45:36.159122 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2473 00:45:36.159191
2474 00:45:36.162168 [CATrainingPosCal] consider 1 rank data
2475 00:45:36.165411 u2DelayCellTimex100 = 270/100 ps
2476 00:45:36.169165 CA0 delay=39 (8~70),Diff = 7 PI (33 cell)
2477 00:45:36.172366 CA1 delay=39 (8~70),Diff = 7 PI (33 cell)
2478 00:45:36.179099 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2479 00:45:36.182293 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2480 00:45:36.185659 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2481 00:45:36.189324 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2482 00:45:36.189385
2483 00:45:36.192668 CA PerBit enable=1, Macro0, CA PI delay=32
2484 00:45:36.192736
2485 00:45:36.196035 [CBTSetCACLKResult] CA Dly = 32
2486 00:45:36.196106 CS Dly: 6 (0~37)
2487 00:45:36.196168 ==
2488 00:45:36.199363 Dram Type= 6, Freq= 0, CH_0, rank 1
2489 00:45:36.205449 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2490 00:45:36.205522 ==
2491 00:45:36.208866 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2492 00:45:36.215705 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2493 00:45:36.224383 [CA 0] Center 38 (8~69) winsize 62
2494 00:45:36.228256 [CA 1] Center 38 (8~69) winsize 62
2495 00:45:36.231655 [CA 2] Center 35 (4~66) winsize 63
2496 00:45:36.234467 [CA 3] Center 34 (4~65) winsize 62
2497 00:45:36.237757 [CA 4] Center 33 (3~64) winsize 62
2498 00:45:36.241167 [CA 5] Center 32 (2~62) winsize 61
2499 00:45:36.241232
2500 00:45:36.244667 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2501 00:45:36.244746
2502 00:45:36.247980 [CATrainingPosCal] consider 2 rank data
2503 00:45:36.251271 u2DelayCellTimex100 = 270/100 ps
2504 00:45:36.254567 CA0 delay=38 (8~69),Diff = 6 PI (28 cell)
2505 00:45:36.258293 CA1 delay=38 (8~69),Diff = 6 PI (28 cell)
2506 00:45:36.264785 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2507 00:45:36.268141 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2508 00:45:36.271265 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2509 00:45:36.274926 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2510 00:45:36.275001
2511 00:45:36.278363 CA PerBit enable=1, Macro0, CA PI delay=32
2512 00:45:36.278438
2513 00:45:36.281498 [CBTSetCACLKResult] CA Dly = 32
2514 00:45:36.281608 CS Dly: 6 (0~38)
2515 00:45:36.281666
2516 00:45:36.285021 ----->DramcWriteLeveling(PI) begin...
2517 00:45:36.285097 ==
2518 00:45:36.288087 Dram Type= 6, Freq= 0, CH_0, rank 0
2519 00:45:36.294917 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2520 00:45:36.294994 ==
2521 00:45:36.297939 Write leveling (Byte 0): 33 => 33
2522 00:45:36.301813 Write leveling (Byte 1): 31 => 31
2523 00:45:36.301890 DramcWriteLeveling(PI) end<-----
2524 00:45:36.304633
2525 00:45:36.304722 ==
2526 00:45:36.308308 Dram Type= 6, Freq= 0, CH_0, rank 0
2527 00:45:36.311352 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2528 00:45:36.311423 ==
2529 00:45:36.314872 [Gating] SW mode calibration
2530 00:45:36.321651 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2531 00:45:36.324931 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2532 00:45:36.331557 0 15 0 | B1->B0 | 2424 3434 | 0 0 | (0 0) (0 0)
2533 00:45:36.334905 0 15 4 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
2534 00:45:36.338262 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2535 00:45:36.345114 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2536 00:45:36.348442 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2537 00:45:36.351825 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2538 00:45:36.358554 0 15 24 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
2539 00:45:36.361686 0 15 28 | B1->B0 | 3434 2323 | 0 0 | (0 0) (0 0)
2540 00:45:36.365030 1 0 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
2541 00:45:36.371732 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2542 00:45:36.375092 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2543 00:45:36.378241 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2544 00:45:36.382191 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2545 00:45:36.388258 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2546 00:45:36.392146 1 0 24 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
2547 00:45:36.395252 1 0 28 | B1->B0 | 2525 4444 | 0 0 | (0 0) (0 0)
2548 00:45:36.401612 1 1 0 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
2549 00:45:36.405167 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2550 00:45:36.408763 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2551 00:45:36.415237 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2552 00:45:36.418818 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2553 00:45:36.421681 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2554 00:45:36.428444 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2555 00:45:36.431978 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2556 00:45:36.435348 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2557 00:45:36.441779 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2558 00:45:36.445278 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2559 00:45:36.448625 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2560 00:45:36.455491 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2561 00:45:36.458716 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2562 00:45:36.462029 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2563 00:45:36.465221 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2564 00:45:36.471930 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 00:45:36.475201 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2566 00:45:36.479096 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2567 00:45:36.485632 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2568 00:45:36.488991 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2569 00:45:36.492006 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2570 00:45:36.498631 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2571 00:45:36.502094 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2572 00:45:36.505764 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2573 00:45:36.509012 Total UI for P1: 0, mck2ui 16
2574 00:45:36.512221 best dqsien dly found for B0: ( 1, 3, 26)
2575 00:45:36.518862 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2576 00:45:36.518935 Total UI for P1: 0, mck2ui 16
2577 00:45:36.521881 best dqsien dly found for B1: ( 1, 3, 30)
2578 00:45:36.528641 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2579 00:45:36.532410 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2580 00:45:36.532494
2581 00:45:36.535483 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2582 00:45:36.538557 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2583 00:45:36.542481 [Gating] SW calibration Done
2584 00:45:36.542552 ==
2585 00:45:36.545525 Dram Type= 6, Freq= 0, CH_0, rank 0
2586 00:45:36.548833 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2587 00:45:36.548906 ==
2588 00:45:36.552060 RX Vref Scan: 0
2589 00:45:36.552132
2590 00:45:36.552201 RX Vref 0 -> 0, step: 1
2591 00:45:36.552268
2592 00:45:36.555676 RX Delay -40 -> 252, step: 8
2593 00:45:36.559332 iDelay=200, Bit 0, Center 123 (48 ~ 199) 152
2594 00:45:36.562327 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2595 00:45:36.568812 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2596 00:45:36.572291 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2597 00:45:36.575497 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2598 00:45:36.578887 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2599 00:45:36.582172 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2600 00:45:36.588859 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2601 00:45:36.592239 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2602 00:45:36.595615 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
2603 00:45:36.598722 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2604 00:45:36.602079 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2605 00:45:36.609013 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2606 00:45:36.612058 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2607 00:45:36.615570 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2608 00:45:36.618525 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2609 00:45:36.618596 ==
2610 00:45:36.622278 Dram Type= 6, Freq= 0, CH_0, rank 0
2611 00:45:36.628723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2612 00:45:36.628794 ==
2613 00:45:36.628890 DQS Delay:
2614 00:45:36.632271 DQS0 = 0, DQS1 = 0
2615 00:45:36.632344 DQM Delay:
2616 00:45:36.632417 DQM0 = 121, DQM1 = 113
2617 00:45:36.635663 DQ Delay:
2618 00:45:36.638951 DQ0 =123, DQ1 =123, DQ2 =119, DQ3 =119
2619 00:45:36.641988 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2620 00:45:36.645698 DQ8 =99, DQ9 =107, DQ10 =111, DQ11 =107
2621 00:45:36.648694 DQ12 =115, DQ13 =123, DQ14 =123, DQ15 =119
2622 00:45:36.648786
2623 00:45:36.648863
2624 00:45:36.648931 ==
2625 00:45:36.652389 Dram Type= 6, Freq= 0, CH_0, rank 0
2626 00:45:36.655885 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2627 00:45:36.655955 ==
2628 00:45:36.659058
2629 00:45:36.659124
2630 00:45:36.659200 TX Vref Scan disable
2631 00:45:36.662164 == TX Byte 0 ==
2632 00:45:36.665345 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2633 00:45:36.669156 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2634 00:45:36.672149 == TX Byte 1 ==
2635 00:45:36.675341 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2636 00:45:36.678711 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2637 00:45:36.678804 ==
2638 00:45:36.682059 Dram Type= 6, Freq= 0, CH_0, rank 0
2639 00:45:36.688887 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2640 00:45:36.688958 ==
2641 00:45:36.699617 TX Vref=22, minBit 0, minWin=25, winSum=410
2642 00:45:36.702879 TX Vref=24, minBit 0, minWin=25, winSum=412
2643 00:45:36.706285 TX Vref=26, minBit 8, minWin=25, winSum=414
2644 00:45:36.709677 TX Vref=28, minBit 1, minWin=26, winSum=421
2645 00:45:36.712986 TX Vref=30, minBit 12, minWin=25, winSum=422
2646 00:45:36.716341 TX Vref=32, minBit 0, minWin=26, winSum=421
2647 00:45:36.722592 [TxChooseVref] Worse bit 1, Min win 26, Win sum 421, Final Vref 28
2648 00:45:36.722662
2649 00:45:36.726074 Final TX Range 1 Vref 28
2650 00:45:36.726143
2651 00:45:36.726220 ==
2652 00:45:36.729692 Dram Type= 6, Freq= 0, CH_0, rank 0
2653 00:45:36.732842 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2654 00:45:36.732913 ==
2655 00:45:36.732992
2656 00:45:36.733061
2657 00:45:36.736528 TX Vref Scan disable
2658 00:45:36.739579 == TX Byte 0 ==
2659 00:45:36.743000 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2660 00:45:36.746297 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2661 00:45:36.749723 == TX Byte 1 ==
2662 00:45:36.752822 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2663 00:45:36.756407 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2664 00:45:36.756505
2665 00:45:36.759440 [DATLAT]
2666 00:45:36.759516 Freq=1200, CH0 RK0
2667 00:45:36.759589
2668 00:45:36.763227 DATLAT Default: 0xd
2669 00:45:36.763296 0, 0xFFFF, sum = 0
2670 00:45:36.766517 1, 0xFFFF, sum = 0
2671 00:45:36.766584 2, 0xFFFF, sum = 0
2672 00:45:36.769859 3, 0xFFFF, sum = 0
2673 00:45:36.769949 4, 0xFFFF, sum = 0
2674 00:45:36.773016 5, 0xFFFF, sum = 0
2675 00:45:36.773102 6, 0xFFFF, sum = 0
2676 00:45:36.776360 7, 0xFFFF, sum = 0
2677 00:45:36.776457 8, 0xFFFF, sum = 0
2678 00:45:36.779369 9, 0xFFFF, sum = 0
2679 00:45:36.779437 10, 0xFFFF, sum = 0
2680 00:45:36.783010 11, 0xFFFF, sum = 0
2681 00:45:36.783096 12, 0x0, sum = 1
2682 00:45:36.786183 13, 0x0, sum = 2
2683 00:45:36.786250 14, 0x0, sum = 3
2684 00:45:36.789531 15, 0x0, sum = 4
2685 00:45:36.789672 best_step = 13
2686 00:45:36.789750
2687 00:45:36.789817 ==
2688 00:45:36.792952 Dram Type= 6, Freq= 0, CH_0, rank 0
2689 00:45:36.799565 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2690 00:45:36.799635 ==
2691 00:45:36.799707 RX Vref Scan: 1
2692 00:45:36.799801
2693 00:45:36.802948 Set Vref Range= 32 -> 127
2694 00:45:36.803014
2695 00:45:36.806203 RX Vref 32 -> 127, step: 1
2696 00:45:36.806269
2697 00:45:36.809632 RX Delay -13 -> 252, step: 4
2698 00:45:36.809701
2699 00:45:36.812855 Set Vref, RX VrefLevel [Byte0]: 32
2700 00:45:36.816187 [Byte1]: 32
2701 00:45:36.816255
2702 00:45:36.819570 Set Vref, RX VrefLevel [Byte0]: 33
2703 00:45:36.822947 [Byte1]: 33
2704 00:45:36.823014
2705 00:45:36.826423 Set Vref, RX VrefLevel [Byte0]: 34
2706 00:45:36.829470 [Byte1]: 34
2707 00:45:36.833288
2708 00:45:36.833422 Set Vref, RX VrefLevel [Byte0]: 35
2709 00:45:36.836639 [Byte1]: 35
2710 00:45:36.841575
2711 00:45:36.841713 Set Vref, RX VrefLevel [Byte0]: 36
2712 00:45:36.844949 [Byte1]: 36
2713 00:45:36.849391
2714 00:45:36.849527 Set Vref, RX VrefLevel [Byte0]: 37
2715 00:45:36.852402 [Byte1]: 37
2716 00:45:36.857005
2717 00:45:36.857123 Set Vref, RX VrefLevel [Byte0]: 38
2718 00:45:36.860303 [Byte1]: 38
2719 00:45:36.865148
2720 00:45:36.865298 Set Vref, RX VrefLevel [Byte0]: 39
2721 00:45:36.868603 [Byte1]: 39
2722 00:45:36.872721
2723 00:45:36.872839 Set Vref, RX VrefLevel [Byte0]: 40
2724 00:45:36.876572 [Byte1]: 40
2725 00:45:36.880939
2726 00:45:36.881035 Set Vref, RX VrefLevel [Byte0]: 41
2727 00:45:36.884224 [Byte1]: 41
2728 00:45:36.888799
2729 00:45:36.888870 Set Vref, RX VrefLevel [Byte0]: 42
2730 00:45:36.892355 [Byte1]: 42
2731 00:45:36.896644
2732 00:45:36.896717 Set Vref, RX VrefLevel [Byte0]: 43
2733 00:45:36.899990 [Byte1]: 43
2734 00:45:36.904658
2735 00:45:36.904729 Set Vref, RX VrefLevel [Byte0]: 44
2736 00:45:36.908005 [Byte1]: 44
2737 00:45:36.912599
2738 00:45:36.912671 Set Vref, RX VrefLevel [Byte0]: 45
2739 00:45:36.915951 [Byte1]: 45
2740 00:45:36.920579
2741 00:45:36.920672 Set Vref, RX VrefLevel [Byte0]: 46
2742 00:45:36.923292 [Byte1]: 46
2743 00:45:36.927940
2744 00:45:36.928039 Set Vref, RX VrefLevel [Byte0]: 47
2745 00:45:36.931378 [Byte1]: 47
2746 00:45:36.936043
2747 00:45:36.936122 Set Vref, RX VrefLevel [Byte0]: 48
2748 00:45:36.939372 [Byte1]: 48
2749 00:45:36.944192
2750 00:45:36.944286 Set Vref, RX VrefLevel [Byte0]: 49
2751 00:45:36.947106 [Byte1]: 49
2752 00:45:36.951560
2753 00:45:36.951652 Set Vref, RX VrefLevel [Byte0]: 50
2754 00:45:36.954894 [Byte1]: 50
2755 00:45:36.959634
2756 00:45:36.959704 Set Vref, RX VrefLevel [Byte0]: 51
2757 00:45:36.962946 [Byte1]: 51
2758 00:45:36.967515
2759 00:45:36.967583 Set Vref, RX VrefLevel [Byte0]: 52
2760 00:45:36.970610 [Byte1]: 52
2761 00:45:36.975344
2762 00:45:36.975412 Set Vref, RX VrefLevel [Byte0]: 53
2763 00:45:36.978617 [Byte1]: 53
2764 00:45:36.983209
2765 00:45:36.983284 Set Vref, RX VrefLevel [Byte0]: 54
2766 00:45:36.986748 [Byte1]: 54
2767 00:45:36.991577
2768 00:45:36.991647 Set Vref, RX VrefLevel [Byte0]: 55
2769 00:45:36.994788 [Byte1]: 55
2770 00:45:36.998957
2771 00:45:36.999023 Set Vref, RX VrefLevel [Byte0]: 56
2772 00:45:37.002346 [Byte1]: 56
2773 00:45:37.007160
2774 00:45:37.007255 Set Vref, RX VrefLevel [Byte0]: 57
2775 00:45:37.010146 [Byte1]: 57
2776 00:45:37.014774
2777 00:45:37.014847 Set Vref, RX VrefLevel [Byte0]: 58
2778 00:45:37.018057 [Byte1]: 58
2779 00:45:37.022775
2780 00:45:37.022839 Set Vref, RX VrefLevel [Byte0]: 59
2781 00:45:37.026165 [Byte1]: 59
2782 00:45:37.030780
2783 00:45:37.030851 Set Vref, RX VrefLevel [Byte0]: 60
2784 00:45:37.034031 [Byte1]: 60
2785 00:45:37.038922
2786 00:45:37.038990 Set Vref, RX VrefLevel [Byte0]: 61
2787 00:45:37.042130 [Byte1]: 61
2788 00:45:37.046295
2789 00:45:37.046363 Set Vref, RX VrefLevel [Byte0]: 62
2790 00:45:37.049623 [Byte1]: 62
2791 00:45:37.054581
2792 00:45:37.054647 Set Vref, RX VrefLevel [Byte0]: 63
2793 00:45:37.057473 [Byte1]: 63
2794 00:45:37.062623
2795 00:45:37.062692 Set Vref, RX VrefLevel [Byte0]: 64
2796 00:45:37.065342 [Byte1]: 64
2797 00:45:37.070052
2798 00:45:37.070122 Set Vref, RX VrefLevel [Byte0]: 65
2799 00:45:37.073305 [Byte1]: 65
2800 00:45:37.078053
2801 00:45:37.078121 Set Vref, RX VrefLevel [Byte0]: 66
2802 00:45:37.081338 [Byte1]: 66
2803 00:45:37.085923
2804 00:45:37.085991 Set Vref, RX VrefLevel [Byte0]: 67
2805 00:45:37.089259 [Byte1]: 67
2806 00:45:37.093604
2807 00:45:37.093705 Set Vref, RX VrefLevel [Byte0]: 68
2808 00:45:37.097192 [Byte1]: 68
2809 00:45:37.101488
2810 00:45:37.101576 Set Vref, RX VrefLevel [Byte0]: 69
2811 00:45:37.105124 [Byte1]: 69
2812 00:45:37.109718
2813 00:45:37.109825 Set Vref, RX VrefLevel [Byte0]: 70
2814 00:45:37.112763 [Byte1]: 70
2815 00:45:37.117410
2816 00:45:37.117487 Final RX Vref Byte 0 = 57 to rank0
2817 00:45:37.120741 Final RX Vref Byte 1 = 49 to rank0
2818 00:45:37.124293 Final RX Vref Byte 0 = 57 to rank1
2819 00:45:37.127302 Final RX Vref Byte 1 = 49 to rank1==
2820 00:45:37.130788 Dram Type= 6, Freq= 0, CH_0, rank 0
2821 00:45:37.134300 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2822 00:45:37.137920 ==
2823 00:45:37.137989 DQS Delay:
2824 00:45:37.138050 DQS0 = 0, DQS1 = 0
2825 00:45:37.140721 DQM Delay:
2826 00:45:37.140791 DQM0 = 120, DQM1 = 111
2827 00:45:37.144619 DQ Delay:
2828 00:45:37.147906 DQ0 =120, DQ1 =120, DQ2 =120, DQ3 =118
2829 00:45:37.151135 DQ4 =122, DQ5 =112, DQ6 =126, DQ7 =126
2830 00:45:37.154441 DQ8 =98, DQ9 =100, DQ10 =112, DQ11 =106
2831 00:45:37.157783 DQ12 =116, DQ13 =116, DQ14 =124, DQ15 =120
2832 00:45:37.157848
2833 00:45:37.157902
2834 00:45:37.164512 [DQSOSCAuto] RK0, (LSB)MR18= 0x140d, (MSB)MR19= 0x404, tDQSOscB0 = 405 ps tDQSOscB1 = 402 ps
2835 00:45:37.168065 CH0 RK0: MR19=404, MR18=140D
2836 00:45:37.174372 CH0_RK0: MR19=0x404, MR18=0x140D, DQSOSC=402, MR23=63, INC=40, DEC=27
2837 00:45:37.174439
2838 00:45:37.177574 ----->DramcWriteLeveling(PI) begin...
2839 00:45:37.177642 ==
2840 00:45:37.180891 Dram Type= 6, Freq= 0, CH_0, rank 1
2841 00:45:37.184420 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2842 00:45:37.184488 ==
2843 00:45:37.187722 Write leveling (Byte 0): 35 => 35
2844 00:45:37.191038 Write leveling (Byte 1): 29 => 29
2845 00:45:37.194444 DramcWriteLeveling(PI) end<-----
2846 00:45:37.194506
2847 00:45:37.194566 ==
2848 00:45:37.197874 Dram Type= 6, Freq= 0, CH_0, rank 1
2849 00:45:37.201178 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2850 00:45:37.204477 ==
2851 00:45:37.204539 [Gating] SW mode calibration
2852 00:45:37.214880 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2853 00:45:37.217964 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2854 00:45:37.221293 0 15 0 | B1->B0 | 3434 2f2f | 0 0 | (0 0) (1 1)
2855 00:45:37.228224 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2856 00:45:37.231185 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2857 00:45:37.234732 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2858 00:45:37.241200 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2859 00:45:37.244482 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2860 00:45:37.248238 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2861 00:45:37.254807 0 15 28 | B1->B0 | 3131 2e2e | 0 0 | (0 1) (0 1)
2862 00:45:37.257888 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
2863 00:45:37.261604 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2864 00:45:37.268075 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2865 00:45:37.271286 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2866 00:45:37.274958 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2867 00:45:37.278191 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2868 00:45:37.284907 1 0 24 | B1->B0 | 2626 2323 | 1 0 | (0 0) (0 0)
2869 00:45:37.288313 1 0 28 | B1->B0 | 3b3b 3b3b | 0 0 | (1 1) (0 0)
2870 00:45:37.291725 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2871 00:45:37.298476 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2872 00:45:37.301762 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2873 00:45:37.304552 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2874 00:45:37.311279 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2875 00:45:37.314565 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2876 00:45:37.317935 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2877 00:45:37.324849 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
2878 00:45:37.328213 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
2879 00:45:37.331589 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2880 00:45:37.338111 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2881 00:45:37.341738 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2882 00:45:37.344858 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2883 00:45:37.348129 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2884 00:45:37.354556 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2885 00:45:37.358045 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2886 00:45:37.361378 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2887 00:45:37.368340 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2888 00:45:37.371802 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2889 00:45:37.374999 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2890 00:45:37.381342 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2891 00:45:37.384858 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2892 00:45:37.387985 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2893 00:45:37.394774 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2894 00:45:37.397804 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
2895 00:45:37.401704 Total UI for P1: 0, mck2ui 16
2896 00:45:37.404475 best dqsien dly found for B1: ( 1, 3, 28)
2897 00:45:37.408277 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2898 00:45:37.411660 Total UI for P1: 0, mck2ui 16
2899 00:45:37.415039 best dqsien dly found for B0: ( 1, 3, 30)
2900 00:45:37.417741 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2901 00:45:37.421119 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2902 00:45:37.421181
2903 00:45:37.428045 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2904 00:45:37.431164 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2905 00:45:37.431229 [Gating] SW calibration Done
2906 00:45:37.434621 ==
2907 00:45:37.437892 Dram Type= 6, Freq= 0, CH_0, rank 1
2908 00:45:37.441180 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2909 00:45:37.441249 ==
2910 00:45:37.441305 RX Vref Scan: 0
2911 00:45:37.441357
2912 00:45:37.444563 RX Vref 0 -> 0, step: 1
2913 00:45:37.444622
2914 00:45:37.448242 RX Delay -40 -> 252, step: 8
2915 00:45:37.451343 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2916 00:45:37.454575 iDelay=200, Bit 1, Center 123 (56 ~ 191) 136
2917 00:45:37.461333 iDelay=200, Bit 2, Center 123 (56 ~ 191) 136
2918 00:45:37.464538 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2919 00:45:37.467769 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2920 00:45:37.471162 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2921 00:45:37.474321 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2922 00:45:37.477979 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2923 00:45:37.484394 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2924 00:45:37.487671 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
2925 00:45:37.491505 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2926 00:45:37.494451 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2927 00:45:37.497694 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2928 00:45:37.504438 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2929 00:45:37.507894 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2930 00:45:37.510931 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
2931 00:45:37.511001 ==
2932 00:45:37.514609 Dram Type= 6, Freq= 0, CH_0, rank 1
2933 00:45:37.517457 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2934 00:45:37.521510 ==
2935 00:45:37.521625 DQS Delay:
2936 00:45:37.521686 DQS0 = 0, DQS1 = 0
2937 00:45:37.524166 DQM Delay:
2938 00:45:37.524250 DQM0 = 122, DQM1 = 112
2939 00:45:37.527543 DQ Delay:
2940 00:45:37.531404 DQ0 =119, DQ1 =123, DQ2 =123, DQ3 =119
2941 00:45:37.534518 DQ4 =127, DQ5 =115, DQ6 =127, DQ7 =127
2942 00:45:37.537644 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =103
2943 00:45:37.540902 DQ12 =115, DQ13 =119, DQ14 =123, DQ15 =123
2944 00:45:37.540977
2945 00:45:37.541037
2946 00:45:37.541092 ==
2947 00:45:37.544406 Dram Type= 6, Freq= 0, CH_0, rank 1
2948 00:45:37.547832 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2949 00:45:37.547897 ==
2950 00:45:37.547951
2951 00:45:37.548002
2952 00:45:37.551157 TX Vref Scan disable
2953 00:45:37.554416 == TX Byte 0 ==
2954 00:45:37.557524 Update DQ dly =855 (3 ,2, 23) DQ OEN =(2 ,7)
2955 00:45:37.560885 Update DQM dly =855 (3 ,2, 23) DQM OEN =(2 ,7)
2956 00:45:37.564239 == TX Byte 1 ==
2957 00:45:37.567556 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2958 00:45:37.571381 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2959 00:45:37.571457 ==
2960 00:45:37.574783 Dram Type= 6, Freq= 0, CH_0, rank 1
2961 00:45:37.577946 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2962 00:45:37.581215 ==
2963 00:45:37.592021 TX Vref=22, minBit 1, minWin=24, winSum=412
2964 00:45:37.595157 TX Vref=24, minBit 3, minWin=25, winSum=416
2965 00:45:37.598638 TX Vref=26, minBit 3, minWin=26, winSum=427
2966 00:45:37.601414 TX Vref=28, minBit 1, minWin=26, winSum=427
2967 00:45:37.604687 TX Vref=30, minBit 2, minWin=26, winSum=431
2968 00:45:37.611476 TX Vref=32, minBit 5, minWin=25, winSum=426
2969 00:45:37.614639 [TxChooseVref] Worse bit 2, Min win 26, Win sum 431, Final Vref 30
2970 00:45:37.614712
2971 00:45:37.618448 Final TX Range 1 Vref 30
2972 00:45:37.618537
2973 00:45:37.618620 ==
2974 00:45:37.621703 Dram Type= 6, Freq= 0, CH_0, rank 1
2975 00:45:37.624655 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2976 00:45:37.624722 ==
2977 00:45:37.628095
2978 00:45:37.628183
2979 00:45:37.628264 TX Vref Scan disable
2980 00:45:37.631405 == TX Byte 0 ==
2981 00:45:37.635043 Update DQ dly =855 (3 ,2, 23) DQ OEN =(2 ,7)
2982 00:45:37.638040 Update DQM dly =855 (3 ,2, 23) DQM OEN =(2 ,7)
2983 00:45:37.641563 == TX Byte 1 ==
2984 00:45:37.645078 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2985 00:45:37.648446 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2986 00:45:37.651509
2987 00:45:37.651601 [DATLAT]
2988 00:45:37.651681 Freq=1200, CH0 RK1
2989 00:45:37.651759
2990 00:45:37.654611 DATLAT Default: 0xd
2991 00:45:37.654676 0, 0xFFFF, sum = 0
2992 00:45:37.658281 1, 0xFFFF, sum = 0
2993 00:45:37.658346 2, 0xFFFF, sum = 0
2994 00:45:37.661616 3, 0xFFFF, sum = 0
2995 00:45:37.664750 4, 0xFFFF, sum = 0
2996 00:45:37.664814 5, 0xFFFF, sum = 0
2997 00:45:37.667749 6, 0xFFFF, sum = 0
2998 00:45:37.667820 7, 0xFFFF, sum = 0
2999 00:45:37.671071 8, 0xFFFF, sum = 0
3000 00:45:37.671133 9, 0xFFFF, sum = 0
3001 00:45:37.675037 10, 0xFFFF, sum = 0
3002 00:45:37.675105 11, 0xFFFF, sum = 0
3003 00:45:37.677708 12, 0x0, sum = 1
3004 00:45:37.677794 13, 0x0, sum = 2
3005 00:45:37.681666 14, 0x0, sum = 3
3006 00:45:37.681744 15, 0x0, sum = 4
3007 00:45:37.684349 best_step = 13
3008 00:45:37.684413
3009 00:45:37.684471 ==
3010 00:45:37.687633 Dram Type= 6, Freq= 0, CH_0, rank 1
3011 00:45:37.691521 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3012 00:45:37.691596 ==
3013 00:45:37.691655 RX Vref Scan: 0
3014 00:45:37.691748
3015 00:45:37.694694 RX Vref 0 -> 0, step: 1
3016 00:45:37.694769
3017 00:45:37.697997 RX Delay -13 -> 252, step: 4
3018 00:45:37.701368 iDelay=195, Bit 0, Center 120 (51 ~ 190) 140
3019 00:45:37.707915 iDelay=195, Bit 1, Center 120 (55 ~ 186) 132
3020 00:45:37.711327 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
3021 00:45:37.714770 iDelay=195, Bit 3, Center 118 (51 ~ 186) 136
3022 00:45:37.718039 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
3023 00:45:37.720687 iDelay=195, Bit 5, Center 116 (51 ~ 182) 132
3024 00:45:37.727420 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3025 00:45:37.730592 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3026 00:45:37.734002 iDelay=195, Bit 8, Center 100 (35 ~ 166) 132
3027 00:45:37.737319 iDelay=195, Bit 9, Center 98 (31 ~ 166) 136
3028 00:45:37.740774 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3029 00:45:37.747793 iDelay=195, Bit 11, Center 102 (39 ~ 166) 128
3030 00:45:37.750928 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
3031 00:45:37.753918 iDelay=195, Bit 13, Center 116 (55 ~ 178) 124
3032 00:45:37.757420 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3033 00:45:37.764128 iDelay=195, Bit 15, Center 118 (55 ~ 182) 128
3034 00:45:37.764221 ==
3035 00:45:37.767702 Dram Type= 6, Freq= 0, CH_0, rank 1
3036 00:45:37.770984 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3037 00:45:37.771074 ==
3038 00:45:37.771155 DQS Delay:
3039 00:45:37.774339 DQS0 = 0, DQS1 = 0
3040 00:45:37.774427 DQM Delay:
3041 00:45:37.777267 DQM0 = 120, DQM1 = 110
3042 00:45:37.777358 DQ Delay:
3043 00:45:37.780873 DQ0 =120, DQ1 =120, DQ2 =118, DQ3 =118
3044 00:45:37.784125 DQ4 =122, DQ5 =116, DQ6 =126, DQ7 =126
3045 00:45:37.787426 DQ8 =100, DQ9 =98, DQ10 =110, DQ11 =102
3046 00:45:37.790932 DQ12 =114, DQ13 =116, DQ14 =122, DQ15 =118
3047 00:45:37.791005
3048 00:45:37.791063
3049 00:45:37.800774 [DQSOSCAuto] RK1, (LSB)MR18= 0xff0, (MSB)MR19= 0x403, tDQSOscB0 = 416 ps tDQSOscB1 = 404 ps
3050 00:45:37.803751 CH0 RK1: MR19=403, MR18=FF0
3051 00:45:37.807440 CH0_RK1: MR19=0x403, MR18=0xFF0, DQSOSC=404, MR23=63, INC=40, DEC=26
3052 00:45:37.810846 [RxdqsGatingPostProcess] freq 1200
3053 00:45:37.817009 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3054 00:45:37.820507 best DQS0 dly(2T, 0.5T) = (0, 11)
3055 00:45:37.823921 best DQS1 dly(2T, 0.5T) = (0, 11)
3056 00:45:37.827309 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3057 00:45:37.830490 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3058 00:45:37.834042 best DQS0 dly(2T, 0.5T) = (0, 11)
3059 00:45:37.837268 best DQS1 dly(2T, 0.5T) = (0, 11)
3060 00:45:37.840676 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3061 00:45:37.843931 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3062 00:45:37.847265 Pre-setting of DQS Precalculation
3063 00:45:37.850596 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3064 00:45:37.850687 ==
3065 00:45:37.854081 Dram Type= 6, Freq= 0, CH_1, rank 0
3066 00:45:37.856635 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3067 00:45:37.856726 ==
3068 00:45:37.863650 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3069 00:45:37.870093 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3070 00:45:37.878030 [CA 0] Center 37 (7~68) winsize 62
3071 00:45:37.881225 [CA 1] Center 37 (7~68) winsize 62
3072 00:45:37.884491 [CA 2] Center 35 (5~65) winsize 61
3073 00:45:37.888217 [CA 3] Center 34 (4~64) winsize 61
3074 00:45:37.891079 [CA 4] Center 34 (4~64) winsize 61
3075 00:45:37.894692 [CA 5] Center 33 (3~63) winsize 61
3076 00:45:37.894768
3077 00:45:37.897983 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3078 00:45:37.898059
3079 00:45:37.901674 [CATrainingPosCal] consider 1 rank data
3080 00:45:37.904927 u2DelayCellTimex100 = 270/100 ps
3081 00:45:37.908042 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3082 00:45:37.911179 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3083 00:45:37.918030 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3084 00:45:37.920975 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3085 00:45:37.924327 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3086 00:45:37.927904 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3087 00:45:37.927999
3088 00:45:37.931350 CA PerBit enable=1, Macro0, CA PI delay=33
3089 00:45:37.931445
3090 00:45:37.934406 [CBTSetCACLKResult] CA Dly = 33
3091 00:45:37.934502 CS Dly: 7 (0~38)
3092 00:45:37.937812 ==
3093 00:45:37.937904 Dram Type= 6, Freq= 0, CH_1, rank 1
3094 00:45:37.944562 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3095 00:45:37.944656 ==
3096 00:45:37.947965 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3097 00:45:37.954468 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3098 00:45:37.963823 [CA 0] Center 37 (7~68) winsize 62
3099 00:45:37.967074 [CA 1] Center 38 (7~69) winsize 63
3100 00:45:37.970260 [CA 2] Center 35 (5~65) winsize 61
3101 00:45:37.973594 [CA 3] Center 34 (4~65) winsize 62
3102 00:45:37.976720 [CA 4] Center 34 (4~65) winsize 62
3103 00:45:37.980384 [CA 5] Center 34 (4~64) winsize 61
3104 00:45:37.980472
3105 00:45:37.983649 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3106 00:45:37.983715
3107 00:45:37.986922 [CATrainingPosCal] consider 2 rank data
3108 00:45:37.990305 u2DelayCellTimex100 = 270/100 ps
3109 00:45:37.993675 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3110 00:45:37.996954 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3111 00:45:38.003424 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3112 00:45:38.007357 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3113 00:45:38.010000 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3114 00:45:38.013334 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3115 00:45:38.013425
3116 00:45:38.016658 CA PerBit enable=1, Macro0, CA PI delay=33
3117 00:45:38.016745
3118 00:45:38.020459 [CBTSetCACLKResult] CA Dly = 33
3119 00:45:38.020549 CS Dly: 8 (0~41)
3120 00:45:38.020630
3121 00:45:38.023735 ----->DramcWriteLeveling(PI) begin...
3122 00:45:38.027060 ==
3123 00:45:38.027127 Dram Type= 6, Freq= 0, CH_1, rank 0
3124 00:45:38.033314 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3125 00:45:38.033407 ==
3126 00:45:38.036646 Write leveling (Byte 0): 25 => 25
3127 00:45:38.039908 Write leveling (Byte 1): 27 => 27
3128 00:45:38.043390 DramcWriteLeveling(PI) end<-----
3129 00:45:38.043477
3130 00:45:38.043557 ==
3131 00:45:38.046614 Dram Type= 6, Freq= 0, CH_1, rank 0
3132 00:45:38.049891 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3133 00:45:38.049976 ==
3134 00:45:38.052959 [Gating] SW mode calibration
3135 00:45:38.059537 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3136 00:45:38.066387 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3137 00:45:38.069728 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3138 00:45:38.072963 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3139 00:45:38.079670 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3140 00:45:38.082928 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3141 00:45:38.085926 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3142 00:45:38.092635 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3143 00:45:38.095863 0 15 24 | B1->B0 | 3232 2d2d | 0 0 | (0 1) (0 1)
3144 00:45:38.099195 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3145 00:45:38.105962 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3146 00:45:38.109043 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3147 00:45:38.112579 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3148 00:45:38.119628 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3149 00:45:38.122915 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3150 00:45:38.126114 1 0 20 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
3151 00:45:38.132938 1 0 24 | B1->B0 | 3535 4444 | 0 0 | (1 1) (0 0)
3152 00:45:38.136261 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3153 00:45:38.139695 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3154 00:45:38.143068 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3155 00:45:38.148969 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3156 00:45:38.152862 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3157 00:45:38.156191 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3158 00:45:38.162569 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3159 00:45:38.165664 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3160 00:45:38.169058 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3161 00:45:38.175674 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3162 00:45:38.179053 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3163 00:45:38.182449 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3164 00:45:38.188926 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3165 00:45:38.192422 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3166 00:45:38.195682 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3167 00:45:38.202566 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3168 00:45:38.205433 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3169 00:45:38.208981 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3170 00:45:38.215509 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3171 00:45:38.219317 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3172 00:45:38.222370 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3173 00:45:38.228767 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3174 00:45:38.232162 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3175 00:45:38.235448 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3176 00:45:38.242207 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3177 00:45:38.245604 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3178 00:45:38.248997 Total UI for P1: 0, mck2ui 16
3179 00:45:38.252264 best dqsien dly found for B0: ( 1, 3, 26)
3180 00:45:38.255728 Total UI for P1: 0, mck2ui 16
3181 00:45:38.259150 best dqsien dly found for B1: ( 1, 3, 26)
3182 00:45:38.262434 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3183 00:45:38.265214 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3184 00:45:38.265290
3185 00:45:38.268681 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3186 00:45:38.272115 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3187 00:45:38.275419 [Gating] SW calibration Done
3188 00:45:38.275495 ==
3189 00:45:38.279339 Dram Type= 6, Freq= 0, CH_1, rank 0
3190 00:45:38.282014 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3191 00:45:38.282090 ==
3192 00:45:38.285292 RX Vref Scan: 0
3193 00:45:38.285394
3194 00:45:38.288673 RX Vref 0 -> 0, step: 1
3195 00:45:38.288748
3196 00:45:38.288808 RX Delay -40 -> 252, step: 8
3197 00:45:38.295311 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3198 00:45:38.299062 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3199 00:45:38.301865 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3200 00:45:38.305429 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3201 00:45:38.308882 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3202 00:45:38.315210 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3203 00:45:38.318383 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3204 00:45:38.321958 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
3205 00:45:38.325473 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3206 00:45:38.328803 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3207 00:45:38.335242 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3208 00:45:38.338514 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3209 00:45:38.341752 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3210 00:45:38.345184 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3211 00:45:38.351579 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3212 00:45:38.355346 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3213 00:45:38.355440 ==
3214 00:45:38.358756 Dram Type= 6, Freq= 0, CH_1, rank 0
3215 00:45:38.362074 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3216 00:45:38.362139 ==
3217 00:45:38.362205 DQS Delay:
3218 00:45:38.364944 DQS0 = 0, DQS1 = 0
3219 00:45:38.365031 DQM Delay:
3220 00:45:38.368194 DQM0 = 120, DQM1 = 116
3221 00:45:38.368281 DQ Delay:
3222 00:45:38.371584 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3223 00:45:38.375003 DQ4 =119, DQ5 =127, DQ6 =127, DQ7 =123
3224 00:45:38.378420 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =111
3225 00:45:38.381753 DQ12 =123, DQ13 =127, DQ14 =123, DQ15 =123
3226 00:45:38.385081
3227 00:45:38.385169
3228 00:45:38.385248 ==
3229 00:45:38.388458 Dram Type= 6, Freq= 0, CH_1, rank 0
3230 00:45:38.391757 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3231 00:45:38.391852 ==
3232 00:45:38.391931
3233 00:45:38.392007
3234 00:45:38.395048 TX Vref Scan disable
3235 00:45:38.395140 == TX Byte 0 ==
3236 00:45:38.401606 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3237 00:45:38.405020 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3238 00:45:38.405113 == TX Byte 1 ==
3239 00:45:38.412034 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3240 00:45:38.415020 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3241 00:45:38.415116 ==
3242 00:45:38.418244 Dram Type= 6, Freq= 0, CH_1, rank 0
3243 00:45:38.421666 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3244 00:45:38.421754 ==
3245 00:45:38.433612 TX Vref=22, minBit 9, minWin=24, winSum=409
3246 00:45:38.437058 TX Vref=24, minBit 9, minWin=25, winSum=418
3247 00:45:38.440327 TX Vref=26, minBit 1, minWin=26, winSum=426
3248 00:45:38.444198 TX Vref=28, minBit 1, minWin=26, winSum=426
3249 00:45:38.447077 TX Vref=30, minBit 2, minWin=26, winSum=429
3250 00:45:38.450561 TX Vref=32, minBit 2, minWin=26, winSum=430
3251 00:45:38.457034 [TxChooseVref] Worse bit 2, Min win 26, Win sum 430, Final Vref 32
3252 00:45:38.457132
3253 00:45:38.460259 Final TX Range 1 Vref 32
3254 00:45:38.460354
3255 00:45:38.460434 ==
3256 00:45:38.463705 Dram Type= 6, Freq= 0, CH_1, rank 0
3257 00:45:38.466843 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3258 00:45:38.466907 ==
3259 00:45:38.470506
3260 00:45:38.470581
3261 00:45:38.470636 TX Vref Scan disable
3262 00:45:38.473600 == TX Byte 0 ==
3263 00:45:38.476871 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3264 00:45:38.480144 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3265 00:45:38.483644 == TX Byte 1 ==
3266 00:45:38.486878 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3267 00:45:38.490526 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3268 00:45:38.493817
3269 00:45:38.493905 [DATLAT]
3270 00:45:38.493987 Freq=1200, CH1 RK0
3271 00:45:38.494074
3272 00:45:38.497226 DATLAT Default: 0xd
3273 00:45:38.497315 0, 0xFFFF, sum = 0
3274 00:45:38.500500 1, 0xFFFF, sum = 0
3275 00:45:38.500596 2, 0xFFFF, sum = 0
3276 00:45:38.503932 3, 0xFFFF, sum = 0
3277 00:45:38.504055 4, 0xFFFF, sum = 0
3278 00:45:38.507162 5, 0xFFFF, sum = 0
3279 00:45:38.507226 6, 0xFFFF, sum = 0
3280 00:45:38.510499 7, 0xFFFF, sum = 0
3281 00:45:38.513839 8, 0xFFFF, sum = 0
3282 00:45:38.513930 9, 0xFFFF, sum = 0
3283 00:45:38.517083 10, 0xFFFF, sum = 0
3284 00:45:38.517171 11, 0xFFFF, sum = 0
3285 00:45:38.520259 12, 0x0, sum = 1
3286 00:45:38.520347 13, 0x0, sum = 2
3287 00:45:38.523506 14, 0x0, sum = 3
3288 00:45:38.523587 15, 0x0, sum = 4
3289 00:45:38.523648 best_step = 13
3290 00:45:38.523702
3291 00:45:38.526699 ==
3292 00:45:38.530108 Dram Type= 6, Freq= 0, CH_1, rank 0
3293 00:45:38.533476 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3294 00:45:38.533577 ==
3295 00:45:38.533653 RX Vref Scan: 1
3296 00:45:38.533708
3297 00:45:38.536666 Set Vref Range= 32 -> 127
3298 00:45:38.536742
3299 00:45:38.539997 RX Vref 32 -> 127, step: 1
3300 00:45:38.540073
3301 00:45:38.543303 RX Delay -5 -> 252, step: 4
3302 00:45:38.543379
3303 00:45:38.546754 Set Vref, RX VrefLevel [Byte0]: 32
3304 00:45:38.550034 [Byte1]: 32
3305 00:45:38.550110
3306 00:45:38.553337 Set Vref, RX VrefLevel [Byte0]: 33
3307 00:45:38.556779 [Byte1]: 33
3308 00:45:38.556853
3309 00:45:38.559934 Set Vref, RX VrefLevel [Byte0]: 34
3310 00:45:38.563514 [Byte1]: 34
3311 00:45:38.567600
3312 00:45:38.567675 Set Vref, RX VrefLevel [Byte0]: 35
3313 00:45:38.570820 [Byte1]: 35
3314 00:45:38.575588
3315 00:45:38.575663 Set Vref, RX VrefLevel [Byte0]: 36
3316 00:45:38.578914 [Byte1]: 36
3317 00:45:38.583280
3318 00:45:38.583355 Set Vref, RX VrefLevel [Byte0]: 37
3319 00:45:38.586404 [Byte1]: 37
3320 00:45:38.591388
3321 00:45:38.591463 Set Vref, RX VrefLevel [Byte0]: 38
3322 00:45:38.594664 [Byte1]: 38
3323 00:45:38.598794
3324 00:45:38.598869 Set Vref, RX VrefLevel [Byte0]: 39
3325 00:45:38.602106 [Byte1]: 39
3326 00:45:38.607034
3327 00:45:38.607109 Set Vref, RX VrefLevel [Byte0]: 40
3328 00:45:38.610303 [Byte1]: 40
3329 00:45:38.614963
3330 00:45:38.615038 Set Vref, RX VrefLevel [Byte0]: 41
3331 00:45:38.618209 [Byte1]: 41
3332 00:45:38.622939
3333 00:45:38.623025 Set Vref, RX VrefLevel [Byte0]: 42
3334 00:45:38.625814 [Byte1]: 42
3335 00:45:38.630296
3336 00:45:38.630411 Set Vref, RX VrefLevel [Byte0]: 43
3337 00:45:38.633471 [Byte1]: 43
3338 00:45:38.638206
3339 00:45:38.638296 Set Vref, RX VrefLevel [Byte0]: 44
3340 00:45:38.641579 [Byte1]: 44
3341 00:45:38.646023
3342 00:45:38.646091 Set Vref, RX VrefLevel [Byte0]: 45
3343 00:45:38.649211 [Byte1]: 45
3344 00:45:38.653944
3345 00:45:38.654010 Set Vref, RX VrefLevel [Byte0]: 46
3346 00:45:38.657312 [Byte1]: 46
3347 00:45:38.661930
3348 00:45:38.662007 Set Vref, RX VrefLevel [Byte0]: 47
3349 00:45:38.665290 [Byte1]: 47
3350 00:45:38.669936
3351 00:45:38.670001 Set Vref, RX VrefLevel [Byte0]: 48
3352 00:45:38.673288 [Byte1]: 48
3353 00:45:38.677349
3354 00:45:38.677430 Set Vref, RX VrefLevel [Byte0]: 49
3355 00:45:38.680705 [Byte1]: 49
3356 00:45:38.685334
3357 00:45:38.685426 Set Vref, RX VrefLevel [Byte0]: 50
3358 00:45:38.688558 [Byte1]: 50
3359 00:45:38.693043
3360 00:45:38.693129 Set Vref, RX VrefLevel [Byte0]: 51
3361 00:45:38.696386 [Byte1]: 51
3362 00:45:38.701027
3363 00:45:38.701113 Set Vref, RX VrefLevel [Byte0]: 52
3364 00:45:38.704379 [Byte1]: 52
3365 00:45:38.708960
3366 00:45:38.709051 Set Vref, RX VrefLevel [Byte0]: 53
3367 00:45:38.712298 [Byte1]: 53
3368 00:45:38.716530
3369 00:45:38.716625 Set Vref, RX VrefLevel [Byte0]: 54
3370 00:45:38.720304 [Byte1]: 54
3371 00:45:38.724596
3372 00:45:38.724683 Set Vref, RX VrefLevel [Byte0]: 55
3373 00:45:38.728184 [Byte1]: 55
3374 00:45:38.732332
3375 00:45:38.732396 Set Vref, RX VrefLevel [Byte0]: 56
3376 00:45:38.735916 [Byte1]: 56
3377 00:45:38.740494
3378 00:45:38.740562 Set Vref, RX VrefLevel [Byte0]: 57
3379 00:45:38.743298 [Byte1]: 57
3380 00:45:38.748315
3381 00:45:38.748390 Set Vref, RX VrefLevel [Byte0]: 58
3382 00:45:38.751159 [Byte1]: 58
3383 00:45:38.756108
3384 00:45:38.756183 Set Vref, RX VrefLevel [Byte0]: 59
3385 00:45:38.759407 [Byte1]: 59
3386 00:45:38.763950
3387 00:45:38.764025 Set Vref, RX VrefLevel [Byte0]: 60
3388 00:45:38.767534 [Byte1]: 60
3389 00:45:38.771783
3390 00:45:38.771858 Set Vref, RX VrefLevel [Byte0]: 61
3391 00:45:38.774824 [Byte1]: 61
3392 00:45:38.779416
3393 00:45:38.779491 Set Vref, RX VrefLevel [Byte0]: 62
3394 00:45:38.782709 [Byte1]: 62
3395 00:45:38.787342
3396 00:45:38.787417 Set Vref, RX VrefLevel [Byte0]: 63
3397 00:45:38.790549 [Byte1]: 63
3398 00:45:38.795181
3399 00:45:38.795256 Set Vref, RX VrefLevel [Byte0]: 64
3400 00:45:38.798426 [Byte1]: 64
3401 00:45:38.803206
3402 00:45:38.803281 Set Vref, RX VrefLevel [Byte0]: 65
3403 00:45:38.806484 [Byte1]: 65
3404 00:45:38.811290
3405 00:45:38.811392 Set Vref, RX VrefLevel [Byte0]: 66
3406 00:45:38.814549 [Byte1]: 66
3407 00:45:38.819081
3408 00:45:38.819150 Set Vref, RX VrefLevel [Byte0]: 67
3409 00:45:38.822073 [Byte1]: 67
3410 00:45:38.826607
3411 00:45:38.826673 Set Vref, RX VrefLevel [Byte0]: 68
3412 00:45:38.829959 [Byte1]: 68
3413 00:45:38.834463
3414 00:45:38.834530 Final RX Vref Byte 0 = 55 to rank0
3415 00:45:38.837694 Final RX Vref Byte 1 = 50 to rank0
3416 00:45:38.841385 Final RX Vref Byte 0 = 55 to rank1
3417 00:45:38.844783 Final RX Vref Byte 1 = 50 to rank1==
3418 00:45:38.848135 Dram Type= 6, Freq= 0, CH_1, rank 0
3419 00:45:38.854145 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3420 00:45:38.854226 ==
3421 00:45:38.854284 DQS Delay:
3422 00:45:38.857422 DQS0 = 0, DQS1 = 0
3423 00:45:38.857513 DQM Delay:
3424 00:45:38.857632 DQM0 = 120, DQM1 = 116
3425 00:45:38.860772 DQ Delay:
3426 00:45:38.864054 DQ0 =124, DQ1 =114, DQ2 =110, DQ3 =118
3427 00:45:38.867726 DQ4 =120, DQ5 =128, DQ6 =130, DQ7 =120
3428 00:45:38.870966 DQ8 =104, DQ9 =106, DQ10 =118, DQ11 =110
3429 00:45:38.874241 DQ12 =122, DQ13 =124, DQ14 =124, DQ15 =126
3430 00:45:38.874328
3431 00:45:38.874412
3432 00:45:38.884242 [DQSOSCAuto] RK0, (LSB)MR18= 0x215, (MSB)MR19= 0x404, tDQSOscB0 = 401 ps tDQSOscB1 = 409 ps
3433 00:45:38.884339 CH1 RK0: MR19=404, MR18=215
3434 00:45:38.890883 CH1_RK0: MR19=0x404, MR18=0x215, DQSOSC=401, MR23=63, INC=40, DEC=27
3435 00:45:38.890953
3436 00:45:38.894237 ----->DramcWriteLeveling(PI) begin...
3437 00:45:38.894304 ==
3438 00:45:38.897558 Dram Type= 6, Freq= 0, CH_1, rank 1
3439 00:45:38.900720 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3440 00:45:38.904463 ==
3441 00:45:38.904553 Write leveling (Byte 0): 26 => 26
3442 00:45:38.907695 Write leveling (Byte 1): 30 => 30
3443 00:45:38.911083 DramcWriteLeveling(PI) end<-----
3444 00:45:38.911153
3445 00:45:38.911226 ==
3446 00:45:38.914417 Dram Type= 6, Freq= 0, CH_1, rank 1
3447 00:45:38.921147 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3448 00:45:38.921237 ==
3449 00:45:38.924480 [Gating] SW mode calibration
3450 00:45:38.930715 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3451 00:45:38.934324 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3452 00:45:38.940944 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3453 00:45:38.944060 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3454 00:45:38.947236 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3455 00:45:38.954005 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3456 00:45:38.957356 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3457 00:45:38.960567 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
3458 00:45:38.963931 0 15 24 | B1->B0 | 2c2c 3434 | 0 1 | (1 0) (1 0)
3459 00:45:38.970640 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
3460 00:45:38.974085 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3461 00:45:38.977466 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3462 00:45:38.983765 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3463 00:45:38.987085 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3464 00:45:38.991134 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3465 00:45:38.997324 1 0 20 | B1->B0 | 2929 2323 | 1 0 | (0 0) (0 0)
3466 00:45:39.000711 1 0 24 | B1->B0 | 4141 2929 | 0 1 | (0 0) (0 0)
3467 00:45:39.004100 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3468 00:45:39.010957 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3469 00:45:39.013878 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3470 00:45:39.017355 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3471 00:45:39.023588 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3472 00:45:39.027130 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3473 00:45:39.030407 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3474 00:45:39.036970 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3475 00:45:39.040645 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3476 00:45:39.043596 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3477 00:45:39.050124 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3478 00:45:39.053628 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3479 00:45:39.056784 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3480 00:45:39.063451 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3481 00:45:39.066621 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3482 00:45:39.070165 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3483 00:45:39.076602 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3484 00:45:39.080040 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3485 00:45:39.083412 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3486 00:45:39.090318 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3487 00:45:39.093713 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3488 00:45:39.096987 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3489 00:45:39.103761 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3490 00:45:39.106980 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3491 00:45:39.110063 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3492 00:45:39.113151 Total UI for P1: 0, mck2ui 16
3493 00:45:39.117113 best dqsien dly found for B1: ( 1, 3, 22)
3494 00:45:39.119912 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3495 00:45:39.123398 Total UI for P1: 0, mck2ui 16
3496 00:45:39.126671 best dqsien dly found for B0: ( 1, 3, 28)
3497 00:45:39.130247 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3498 00:45:39.133389 best DQS1 dly(MCK, UI, PI) = (1, 3, 22)
3499 00:45:39.137352
3500 00:45:39.140016 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3501 00:45:39.143416 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 22)
3502 00:45:39.146385 [Gating] SW calibration Done
3503 00:45:39.146476 ==
3504 00:45:39.150321 Dram Type= 6, Freq= 0, CH_1, rank 1
3505 00:45:39.153350 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3506 00:45:39.153455 ==
3507 00:45:39.153559 RX Vref Scan: 0
3508 00:45:39.156928
3509 00:45:39.156993 RX Vref 0 -> 0, step: 1
3510 00:45:39.157059
3511 00:45:39.159858 RX Delay -40 -> 252, step: 8
3512 00:45:39.163358 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3513 00:45:39.166684 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3514 00:45:39.173094 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3515 00:45:39.176360 iDelay=200, Bit 3, Center 119 (56 ~ 183) 128
3516 00:45:39.179770 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3517 00:45:39.183125 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3518 00:45:39.186594 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3519 00:45:39.193009 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
3520 00:45:39.196844 iDelay=200, Bit 8, Center 107 (40 ~ 175) 136
3521 00:45:39.200180 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3522 00:45:39.203455 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3523 00:45:39.206898 iDelay=200, Bit 11, Center 115 (48 ~ 183) 136
3524 00:45:39.212965 iDelay=200, Bit 12, Center 127 (56 ~ 199) 144
3525 00:45:39.216879 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3526 00:45:39.219957 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3527 00:45:39.223135 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3528 00:45:39.223229 ==
3529 00:45:39.226579 Dram Type= 6, Freq= 0, CH_1, rank 1
3530 00:45:39.233162 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3531 00:45:39.233232 ==
3532 00:45:39.233291 DQS Delay:
3533 00:45:39.233381 DQS0 = 0, DQS1 = 0
3534 00:45:39.236534 DQM Delay:
3535 00:45:39.236624 DQM0 = 120, DQM1 = 118
3536 00:45:39.239839 DQ Delay:
3537 00:45:39.243049 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3538 00:45:39.246944 DQ4 =115, DQ5 =131, DQ6 =131, DQ7 =123
3539 00:45:39.249716 DQ8 =107, DQ9 =107, DQ10 =115, DQ11 =115
3540 00:45:39.253165 DQ12 =127, DQ13 =127, DQ14 =123, DQ15 =123
3541 00:45:39.253232
3542 00:45:39.253304
3543 00:45:39.253372 ==
3544 00:45:39.256323 Dram Type= 6, Freq= 0, CH_1, rank 1
3545 00:45:39.260106 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3546 00:45:39.260206 ==
3547 00:45:39.263451
3548 00:45:39.263544
3549 00:45:39.263634 TX Vref Scan disable
3550 00:45:39.266671 == TX Byte 0 ==
3551 00:45:39.269887 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3552 00:45:39.273501 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3553 00:45:39.276561 == TX Byte 1 ==
3554 00:45:39.279886 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3555 00:45:39.283144 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3556 00:45:39.283249 ==
3557 00:45:39.287114 Dram Type= 6, Freq= 0, CH_1, rank 1
3558 00:45:39.290294 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3559 00:45:39.293604 ==
3560 00:45:39.303794 TX Vref=22, minBit 9, minWin=25, winSum=420
3561 00:45:39.306963 TX Vref=24, minBit 1, minWin=26, winSum=425
3562 00:45:39.310325 TX Vref=26, minBit 2, minWin=26, winSum=431
3563 00:45:39.313655 TX Vref=28, minBit 8, minWin=26, winSum=432
3564 00:45:39.317048 TX Vref=30, minBit 9, minWin=26, winSum=435
3565 00:45:39.323662 TX Vref=32, minBit 9, minWin=26, winSum=434
3566 00:45:39.326892 [TxChooseVref] Worse bit 9, Min win 26, Win sum 435, Final Vref 30
3567 00:45:39.326976
3568 00:45:39.330553 Final TX Range 1 Vref 30
3569 00:45:39.330629
3570 00:45:39.330688 ==
3571 00:45:39.333896 Dram Type= 6, Freq= 0, CH_1, rank 1
3572 00:45:39.337280 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3573 00:45:39.337359 ==
3574 00:45:39.340593
3575 00:45:39.340668
3576 00:45:39.340727 TX Vref Scan disable
3577 00:45:39.344045 == TX Byte 0 ==
3578 00:45:39.347339 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3579 00:45:39.350117 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3580 00:45:39.354116 == TX Byte 1 ==
3581 00:45:39.357184 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3582 00:45:39.360518 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3583 00:45:39.360596
3584 00:45:39.363960 [DATLAT]
3585 00:45:39.364064 Freq=1200, CH1 RK1
3586 00:45:39.364122
3587 00:45:39.367221 DATLAT Default: 0xd
3588 00:45:39.367311 0, 0xFFFF, sum = 0
3589 00:45:39.370280 1, 0xFFFF, sum = 0
3590 00:45:39.370356 2, 0xFFFF, sum = 0
3591 00:45:39.373282 3, 0xFFFF, sum = 0
3592 00:45:39.373358 4, 0xFFFF, sum = 0
3593 00:45:39.376774 5, 0xFFFF, sum = 0
3594 00:45:39.380374 6, 0xFFFF, sum = 0
3595 00:45:39.380451 7, 0xFFFF, sum = 0
3596 00:45:39.383839 8, 0xFFFF, sum = 0
3597 00:45:39.383929 9, 0xFFFF, sum = 0
3598 00:45:39.386828 10, 0xFFFF, sum = 0
3599 00:45:39.386905 11, 0xFFFF, sum = 0
3600 00:45:39.389840 12, 0x0, sum = 1
3601 00:45:39.389915 13, 0x0, sum = 2
3602 00:45:39.393254 14, 0x0, sum = 3
3603 00:45:39.393331 15, 0x0, sum = 4
3604 00:45:39.393391 best_step = 13
3605 00:45:39.396742
3606 00:45:39.396816 ==
3607 00:45:39.400284 Dram Type= 6, Freq= 0, CH_1, rank 1
3608 00:45:39.403556 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3609 00:45:39.403633 ==
3610 00:45:39.403722 RX Vref Scan: 0
3611 00:45:39.403776
3612 00:45:39.406674 RX Vref 0 -> 0, step: 1
3613 00:45:39.406751
3614 00:45:39.409870 RX Delay -5 -> 252, step: 4
3615 00:45:39.413580 iDelay=195, Bit 0, Center 122 (59 ~ 186) 128
3616 00:45:39.420092 iDelay=195, Bit 1, Center 116 (55 ~ 178) 124
3617 00:45:39.423357 iDelay=195, Bit 2, Center 110 (51 ~ 170) 120
3618 00:45:39.426741 iDelay=195, Bit 3, Center 116 (59 ~ 174) 116
3619 00:45:39.430214 iDelay=195, Bit 4, Center 116 (55 ~ 178) 124
3620 00:45:39.433391 iDelay=195, Bit 5, Center 132 (71 ~ 194) 124
3621 00:45:39.440037 iDelay=195, Bit 6, Center 130 (67 ~ 194) 128
3622 00:45:39.443285 iDelay=195, Bit 7, Center 120 (59 ~ 182) 124
3623 00:45:39.446582 iDelay=195, Bit 8, Center 106 (47 ~ 166) 120
3624 00:45:39.449854 iDelay=195, Bit 9, Center 108 (47 ~ 170) 124
3625 00:45:39.453097 iDelay=195, Bit 10, Center 116 (55 ~ 178) 124
3626 00:45:39.460006 iDelay=195, Bit 11, Center 110 (51 ~ 170) 120
3627 00:45:39.463373 iDelay=195, Bit 12, Center 126 (63 ~ 190) 128
3628 00:45:39.466529 iDelay=195, Bit 13, Center 124 (67 ~ 182) 116
3629 00:45:39.469955 iDelay=195, Bit 14, Center 124 (67 ~ 182) 116
3630 00:45:39.473373 iDelay=195, Bit 15, Center 124 (63 ~ 186) 124
3631 00:45:39.476728 ==
3632 00:45:39.480069 Dram Type= 6, Freq= 0, CH_1, rank 1
3633 00:45:39.483206 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3634 00:45:39.483283 ==
3635 00:45:39.483343 DQS Delay:
3636 00:45:39.486335 DQS0 = 0, DQS1 = 0
3637 00:45:39.486446 DQM Delay:
3638 00:45:39.489778 DQM0 = 120, DQM1 = 117
3639 00:45:39.489854 DQ Delay:
3640 00:45:39.493336 DQ0 =122, DQ1 =116, DQ2 =110, DQ3 =116
3641 00:45:39.496606 DQ4 =116, DQ5 =132, DQ6 =130, DQ7 =120
3642 00:45:39.499696 DQ8 =106, DQ9 =108, DQ10 =116, DQ11 =110
3643 00:45:39.503432 DQ12 =126, DQ13 =124, DQ14 =124, DQ15 =124
3644 00:45:39.503508
3645 00:45:39.503566
3646 00:45:39.513238 [DQSOSCAuto] RK1, (LSB)MR18= 0x13ef, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 402 ps
3647 00:45:39.513354 CH1 RK1: MR19=403, MR18=13EF
3648 00:45:39.520160 CH1_RK1: MR19=0x403, MR18=0x13EF, DQSOSC=402, MR23=63, INC=40, DEC=27
3649 00:45:39.523150 [RxdqsGatingPostProcess] freq 1200
3650 00:45:39.529815 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3651 00:45:39.533181 best DQS0 dly(2T, 0.5T) = (0, 11)
3652 00:45:39.536446 best DQS1 dly(2T, 0.5T) = (0, 11)
3653 00:45:39.539636 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3654 00:45:39.542882 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3655 00:45:39.546601 best DQS0 dly(2T, 0.5T) = (0, 11)
3656 00:45:39.549945 best DQS1 dly(2T, 0.5T) = (0, 11)
3657 00:45:39.553197 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3658 00:45:39.556556 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3659 00:45:39.556624 Pre-setting of DQS Precalculation
3660 00:45:39.563308 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3661 00:45:39.569934 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3662 00:45:39.576634 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3663 00:45:39.576711
3664 00:45:39.576770
3665 00:45:39.579363 [Calibration Summary] 2400 Mbps
3666 00:45:39.582698 CH 0, Rank 0
3667 00:45:39.582774 SW Impedance : PASS
3668 00:45:39.585936 DUTY Scan : NO K
3669 00:45:39.589359 ZQ Calibration : PASS
3670 00:45:39.589435 Jitter Meter : NO K
3671 00:45:39.592680 CBT Training : PASS
3672 00:45:39.596048 Write leveling : PASS
3673 00:45:39.596125 RX DQS gating : PASS
3674 00:45:39.599510 RX DQ/DQS(RDDQC) : PASS
3675 00:45:39.599586 TX DQ/DQS : PASS
3676 00:45:39.603035 RX DATLAT : PASS
3677 00:45:39.605839 RX DQ/DQS(Engine): PASS
3678 00:45:39.605915 TX OE : NO K
3679 00:45:39.609590 All Pass.
3680 00:45:39.609680
3681 00:45:39.609768 CH 0, Rank 1
3682 00:45:39.612321 SW Impedance : PASS
3683 00:45:39.612398 DUTY Scan : NO K
3684 00:45:39.616038 ZQ Calibration : PASS
3685 00:45:39.619263 Jitter Meter : NO K
3686 00:45:39.619339 CBT Training : PASS
3687 00:45:39.622282 Write leveling : PASS
3688 00:45:39.625954 RX DQS gating : PASS
3689 00:45:39.626045 RX DQ/DQS(RDDQC) : PASS
3690 00:45:39.629398 TX DQ/DQS : PASS
3691 00:45:39.632277 RX DATLAT : PASS
3692 00:45:39.632353 RX DQ/DQS(Engine): PASS
3693 00:45:39.635932 TX OE : NO K
3694 00:45:39.636009 All Pass.
3695 00:45:39.636073
3696 00:45:39.639001 CH 1, Rank 0
3697 00:45:39.639078 SW Impedance : PASS
3698 00:45:39.642277 DUTY Scan : NO K
3699 00:45:39.645507 ZQ Calibration : PASS
3700 00:45:39.645615 Jitter Meter : NO K
3701 00:45:39.648846 CBT Training : PASS
3702 00:45:39.652666 Write leveling : PASS
3703 00:45:39.652773 RX DQS gating : PASS
3704 00:45:39.656008 RX DQ/DQS(RDDQC) : PASS
3705 00:45:39.656085 TX DQ/DQS : PASS
3706 00:45:39.659253 RX DATLAT : PASS
3707 00:45:39.662530 RX DQ/DQS(Engine): PASS
3708 00:45:39.662606 TX OE : NO K
3709 00:45:39.665879 All Pass.
3710 00:45:39.665954
3711 00:45:39.666015 CH 1, Rank 1
3712 00:45:39.669151 SW Impedance : PASS
3713 00:45:39.669245 DUTY Scan : NO K
3714 00:45:39.672573 ZQ Calibration : PASS
3715 00:45:39.675837 Jitter Meter : NO K
3716 00:45:39.675927 CBT Training : PASS
3717 00:45:39.679076 Write leveling : PASS
3718 00:45:39.682189 RX DQS gating : PASS
3719 00:45:39.682262 RX DQ/DQS(RDDQC) : PASS
3720 00:45:39.685453 TX DQ/DQS : PASS
3721 00:45:39.688718 RX DATLAT : PASS
3722 00:45:39.688794 RX DQ/DQS(Engine): PASS
3723 00:45:39.692632 TX OE : NO K
3724 00:45:39.692708 All Pass.
3725 00:45:39.692768
3726 00:45:39.695344 DramC Write-DBI off
3727 00:45:39.698649 PER_BANK_REFRESH: Hybrid Mode
3728 00:45:39.698726 TX_TRACKING: ON
3729 00:45:39.708845 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3730 00:45:39.712012 [FAST_K] Save calibration result to emmc
3731 00:45:39.715712 dramc_set_vcore_voltage set vcore to 650000
3732 00:45:39.719249 Read voltage for 600, 5
3733 00:45:39.719325 Vio18 = 0
3734 00:45:39.719385 Vcore = 650000
3735 00:45:39.722250 Vdram = 0
3736 00:45:39.722326 Vddq = 0
3737 00:45:39.722386 Vmddr = 0
3738 00:45:39.729118 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3739 00:45:39.732487 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3740 00:45:39.735648 MEM_TYPE=3, freq_sel=19
3741 00:45:39.738912 sv_algorithm_assistance_LP4_1600
3742 00:45:39.742414 ============ PULL DRAM RESETB DOWN ============
3743 00:45:39.745532 ========== PULL DRAM RESETB DOWN end =========
3744 00:45:39.752444 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3745 00:45:39.755837 ===================================
3746 00:45:39.755912 LPDDR4 DRAM CONFIGURATION
3747 00:45:39.759123 ===================================
3748 00:45:39.762682 EX_ROW_EN[0] = 0x0
3749 00:45:39.765436 EX_ROW_EN[1] = 0x0
3750 00:45:39.765536 LP4Y_EN = 0x0
3751 00:45:39.768835 WORK_FSP = 0x0
3752 00:45:39.768911 WL = 0x2
3753 00:45:39.772084 RL = 0x2
3754 00:45:39.772201 BL = 0x2
3755 00:45:39.775467 RPST = 0x0
3756 00:45:39.775583 RD_PRE = 0x0
3757 00:45:39.778810 WR_PRE = 0x1
3758 00:45:39.778885 WR_PST = 0x0
3759 00:45:39.782158 DBI_WR = 0x0
3760 00:45:39.782233 DBI_RD = 0x0
3761 00:45:39.785478 OTF = 0x1
3762 00:45:39.788722 ===================================
3763 00:45:39.792062 ===================================
3764 00:45:39.792137 ANA top config
3765 00:45:39.795453 ===================================
3766 00:45:39.798688 DLL_ASYNC_EN = 0
3767 00:45:39.802092 ALL_SLAVE_EN = 1
3768 00:45:39.802168 NEW_RANK_MODE = 1
3769 00:45:39.805416 DLL_IDLE_MODE = 1
3770 00:45:39.808920 LP45_APHY_COMB_EN = 1
3771 00:45:39.812379 TX_ODT_DIS = 1
3772 00:45:39.815658 NEW_8X_MODE = 1
3773 00:45:39.819056 ===================================
3774 00:45:39.822295 ===================================
3775 00:45:39.822365 data_rate = 1200
3776 00:45:39.825820 CKR = 1
3777 00:45:39.828493 DQ_P2S_RATIO = 8
3778 00:45:39.832377 ===================================
3779 00:45:39.835575 CA_P2S_RATIO = 8
3780 00:45:39.838706 DQ_CA_OPEN = 0
3781 00:45:39.841977 DQ_SEMI_OPEN = 0
3782 00:45:39.842049 CA_SEMI_OPEN = 0
3783 00:45:39.845276 CA_FULL_RATE = 0
3784 00:45:39.848952 DQ_CKDIV4_EN = 1
3785 00:45:39.851864 CA_CKDIV4_EN = 1
3786 00:45:39.855298 CA_PREDIV_EN = 0
3787 00:45:39.858645 PH8_DLY = 0
3788 00:45:39.858713 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3789 00:45:39.861658 DQ_AAMCK_DIV = 4
3790 00:45:39.864992 CA_AAMCK_DIV = 4
3791 00:45:39.868437 CA_ADMCK_DIV = 4
3792 00:45:39.872041 DQ_TRACK_CA_EN = 0
3793 00:45:39.874921 CA_PICK = 600
3794 00:45:39.874997 CA_MCKIO = 600
3795 00:45:39.878669 MCKIO_SEMI = 0
3796 00:45:39.881810 PLL_FREQ = 2288
3797 00:45:39.885178 DQ_UI_PI_RATIO = 32
3798 00:45:39.888480 CA_UI_PI_RATIO = 0
3799 00:45:39.891791 ===================================
3800 00:45:39.895241 ===================================
3801 00:45:39.898271 memory_type:LPDDR4
3802 00:45:39.898353 GP_NUM : 10
3803 00:45:39.902205 SRAM_EN : 1
3804 00:45:39.902292 MD32_EN : 0
3805 00:45:39.904907 ===================================
3806 00:45:39.908316 [ANA_INIT] >>>>>>>>>>>>>>
3807 00:45:39.911633 <<<<<< [CONFIGURE PHASE]: ANA_TX
3808 00:45:39.915088 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3809 00:45:39.918504 ===================================
3810 00:45:39.921726 data_rate = 1200,PCW = 0X5800
3811 00:45:39.925063 ===================================
3812 00:45:39.928436 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3813 00:45:39.935284 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3814 00:45:39.938538 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3815 00:45:39.944999 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3816 00:45:39.948898 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3817 00:45:39.951584 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3818 00:45:39.951652 [ANA_INIT] flow start
3819 00:45:39.954885 [ANA_INIT] PLL >>>>>>>>
3820 00:45:39.958206 [ANA_INIT] PLL <<<<<<<<
3821 00:45:39.958271 [ANA_INIT] MIDPI >>>>>>>>
3822 00:45:39.961649 [ANA_INIT] MIDPI <<<<<<<<
3823 00:45:39.964896 [ANA_INIT] DLL >>>>>>>>
3824 00:45:39.964958 [ANA_INIT] flow end
3825 00:45:39.971627 ============ LP4 DIFF to SE enter ============
3826 00:45:39.974968 ============ LP4 DIFF to SE exit ============
3827 00:45:39.975040 [ANA_INIT] <<<<<<<<<<<<<
3828 00:45:39.978277 [Flow] Enable top DCM control >>>>>
3829 00:45:39.981877 [Flow] Enable top DCM control <<<<<
3830 00:45:39.984857 Enable DLL master slave shuffle
3831 00:45:39.991408 ==============================================================
3832 00:45:39.994896 Gating Mode config
3833 00:45:39.998167 ==============================================================
3834 00:45:40.001636 Config description:
3835 00:45:40.011523 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3836 00:45:40.018336 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3837 00:45:40.021563 SELPH_MODE 0: By rank 1: By Phase
3838 00:45:40.028509 ==============================================================
3839 00:45:40.031237 GAT_TRACK_EN = 1
3840 00:45:40.034586 RX_GATING_MODE = 2
3841 00:45:40.037966 RX_GATING_TRACK_MODE = 2
3842 00:45:40.038039 SELPH_MODE = 1
3843 00:45:40.041305 PICG_EARLY_EN = 1
3844 00:45:40.044684 VALID_LAT_VALUE = 1
3845 00:45:40.051596 ==============================================================
3846 00:45:40.054924 Enter into Gating configuration >>>>
3847 00:45:40.058309 Exit from Gating configuration <<<<
3848 00:45:40.061651 Enter into DVFS_PRE_config >>>>>
3849 00:45:40.071695 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3850 00:45:40.074966 Exit from DVFS_PRE_config <<<<<
3851 00:45:40.078307 Enter into PICG configuration >>>>
3852 00:45:40.081581 Exit from PICG configuration <<<<
3853 00:45:40.084650 [RX_INPUT] configuration >>>>>
3854 00:45:40.088238 [RX_INPUT] configuration <<<<<
3855 00:45:40.091260 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3856 00:45:40.097654 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3857 00:45:40.104672 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3858 00:45:40.111521 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3859 00:45:40.114517 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3860 00:45:40.121327 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3861 00:45:40.124621 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3862 00:45:40.131281 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3863 00:45:40.134760 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3864 00:45:40.137650 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3865 00:45:40.141430 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3866 00:45:40.147729 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3867 00:45:40.151088 ===================================
3868 00:45:40.151163 LPDDR4 DRAM CONFIGURATION
3869 00:45:40.154343 ===================================
3870 00:45:40.157933 EX_ROW_EN[0] = 0x0
3871 00:45:40.161038 EX_ROW_EN[1] = 0x0
3872 00:45:40.161112 LP4Y_EN = 0x0
3873 00:45:40.164333 WORK_FSP = 0x0
3874 00:45:40.164409 WL = 0x2
3875 00:45:40.167688 RL = 0x2
3876 00:45:40.167763 BL = 0x2
3877 00:45:40.171133 RPST = 0x0
3878 00:45:40.171208 RD_PRE = 0x0
3879 00:45:40.174508 WR_PRE = 0x1
3880 00:45:40.174583 WR_PST = 0x0
3881 00:45:40.177797 DBI_WR = 0x0
3882 00:45:40.177873 DBI_RD = 0x0
3883 00:45:40.181122 OTF = 0x1
3884 00:45:40.184509 ===================================
3885 00:45:40.187844 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3886 00:45:40.190977 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3887 00:45:40.197670 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3888 00:45:40.201334 ===================================
3889 00:45:40.201410 LPDDR4 DRAM CONFIGURATION
3890 00:45:40.204305 ===================================
3891 00:45:40.208005 EX_ROW_EN[0] = 0x10
3892 00:45:40.210796 EX_ROW_EN[1] = 0x0
3893 00:45:40.210872 LP4Y_EN = 0x0
3894 00:45:40.214443 WORK_FSP = 0x0
3895 00:45:40.214518 WL = 0x2
3896 00:45:40.217880 RL = 0x2
3897 00:45:40.217955 BL = 0x2
3898 00:45:40.220785 RPST = 0x0
3899 00:45:40.220860 RD_PRE = 0x0
3900 00:45:40.224352 WR_PRE = 0x1
3901 00:45:40.224427 WR_PST = 0x0
3902 00:45:40.227892 DBI_WR = 0x0
3903 00:45:40.227967 DBI_RD = 0x0
3904 00:45:40.231138 OTF = 0x1
3905 00:45:40.234183 ===================================
3906 00:45:40.240865 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3907 00:45:40.244132 nWR fixed to 30
3908 00:45:40.244209 [ModeRegInit_LP4] CH0 RK0
3909 00:45:40.247207 [ModeRegInit_LP4] CH0 RK1
3910 00:45:40.250670 [ModeRegInit_LP4] CH1 RK0
3911 00:45:40.253968 [ModeRegInit_LP4] CH1 RK1
3912 00:45:40.254067 match AC timing 17
3913 00:45:40.257912 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3914 00:45:40.263987 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3915 00:45:40.267629 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3916 00:45:40.270923 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3917 00:45:40.277676 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3918 00:45:40.277752 ==
3919 00:45:40.281011 Dram Type= 6, Freq= 0, CH_0, rank 0
3920 00:45:40.284349 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3921 00:45:40.284426 ==
3922 00:45:40.291093 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3923 00:45:40.294532 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3924 00:45:40.299166 [CA 0] Center 35 (5~66) winsize 62
3925 00:45:40.301888 [CA 1] Center 35 (5~66) winsize 62
3926 00:45:40.305136 [CA 2] Center 33 (3~64) winsize 62
3927 00:45:40.309020 [CA 3] Center 33 (2~64) winsize 63
3928 00:45:40.311737 [CA 4] Center 33 (2~64) winsize 63
3929 00:45:40.315542 [CA 5] Center 32 (2~63) winsize 62
3930 00:45:40.315619
3931 00:45:40.318709 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3932 00:45:40.318817
3933 00:45:40.321886 [CATrainingPosCal] consider 1 rank data
3934 00:45:40.325577 u2DelayCellTimex100 = 270/100 ps
3935 00:45:40.328609 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3936 00:45:40.335511 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3937 00:45:40.338902 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3938 00:45:40.341796 CA3 delay=33 (2~64),Diff = 1 PI (9 cell)
3939 00:45:40.345278 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3940 00:45:40.348374 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3941 00:45:40.348463
3942 00:45:40.351789 CA PerBit enable=1, Macro0, CA PI delay=32
3943 00:45:40.351877
3944 00:45:40.355177 [CBTSetCACLKResult] CA Dly = 32
3945 00:45:40.355264 CS Dly: 5 (0~36)
3946 00:45:40.358489 ==
3947 00:45:40.361618 Dram Type= 6, Freq= 0, CH_0, rank 1
3948 00:45:40.365178 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3949 00:45:40.365267 ==
3950 00:45:40.368128 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3951 00:45:40.374751 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3952 00:45:40.379485 [CA 0] Center 35 (5~66) winsize 62
3953 00:45:40.382260 [CA 1] Center 35 (5~66) winsize 62
3954 00:45:40.385397 [CA 2] Center 33 (3~64) winsize 62
3955 00:45:40.388740 [CA 3] Center 33 (3~64) winsize 62
3956 00:45:40.392102 [CA 4] Center 33 (2~64) winsize 63
3957 00:45:40.395472 [CA 5] Center 32 (2~63) winsize 62
3958 00:45:40.395548
3959 00:45:40.398574 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3960 00:45:40.398650
3961 00:45:40.401963 [CATrainingPosCal] consider 2 rank data
3962 00:45:40.405376 u2DelayCellTimex100 = 270/100 ps
3963 00:45:40.408798 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3964 00:45:40.411966 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3965 00:45:40.418657 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3966 00:45:40.422563 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
3967 00:45:40.425083 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3968 00:45:40.428492 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3969 00:45:40.428567
3970 00:45:40.432326 CA PerBit enable=1, Macro0, CA PI delay=32
3971 00:45:40.432419
3972 00:45:40.435614 [CBTSetCACLKResult] CA Dly = 32
3973 00:45:40.435690 CS Dly: 5 (0~36)
3974 00:45:40.435749
3975 00:45:40.438929 ----->DramcWriteLeveling(PI) begin...
3976 00:45:40.442078 ==
3977 00:45:40.445088 Dram Type= 6, Freq= 0, CH_0, rank 0
3978 00:45:40.448810 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3979 00:45:40.448903 ==
3980 00:45:40.451889 Write leveling (Byte 0): 33 => 33
3981 00:45:40.455437 Write leveling (Byte 1): 32 => 32
3982 00:45:40.458787 DramcWriteLeveling(PI) end<-----
3983 00:45:40.458877
3984 00:45:40.458949 ==
3985 00:45:40.462211 Dram Type= 6, Freq= 0, CH_0, rank 0
3986 00:45:40.465542 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3987 00:45:40.465627 ==
3988 00:45:40.468897 [Gating] SW mode calibration
3989 00:45:40.475292 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3990 00:45:40.478627 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3991 00:45:40.485408 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3992 00:45:40.488944 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3993 00:45:40.492117 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3994 00:45:40.498536 0 9 12 | B1->B0 | 3434 2a2a | 1 0 | (1 1) (0 0)
3995 00:45:40.502192 0 9 16 | B1->B0 | 2f2f 2323 | 0 0 | (1 1) (0 0)
3996 00:45:40.505009 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3997 00:45:40.511722 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3998 00:45:40.515505 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3999 00:45:40.518903 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4000 00:45:40.525637 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4001 00:45:40.528633 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4002 00:45:40.531899 0 10 12 | B1->B0 | 2424 3333 | 1 0 | (0 0) (0 0)
4003 00:45:40.538649 0 10 16 | B1->B0 | 3131 4646 | 0 0 | (0 0) (0 0)
4004 00:45:40.541888 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4005 00:45:40.545308 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4006 00:45:40.551742 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4007 00:45:40.555137 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4008 00:45:40.558556 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4009 00:45:40.561918 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4010 00:45:40.568861 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4011 00:45:40.571654 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4012 00:45:40.575462 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4013 00:45:40.582254 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4014 00:45:40.585116 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4015 00:45:40.588978 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4016 00:45:40.595684 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4017 00:45:40.598460 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4018 00:45:40.601761 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4019 00:45:40.608476 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4020 00:45:40.612026 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4021 00:45:40.615245 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4022 00:45:40.622276 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4023 00:45:40.625307 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4024 00:45:40.628344 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4025 00:45:40.635553 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4026 00:45:40.638666 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4027 00:45:40.641839 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4028 00:45:40.645683 Total UI for P1: 0, mck2ui 16
4029 00:45:40.648927 best dqsien dly found for B0: ( 0, 13, 12)
4030 00:45:40.652253 Total UI for P1: 0, mck2ui 16
4031 00:45:40.655485 best dqsien dly found for B1: ( 0, 13, 14)
4032 00:45:40.658698 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4033 00:45:40.662096 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4034 00:45:40.662172
4035 00:45:40.668809 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4036 00:45:40.672175 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4037 00:45:40.672252 [Gating] SW calibration Done
4038 00:45:40.675571 ==
4039 00:45:40.675649 Dram Type= 6, Freq= 0, CH_0, rank 0
4040 00:45:40.682043 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4041 00:45:40.682120 ==
4042 00:45:40.682197 RX Vref Scan: 0
4043 00:45:40.682266
4044 00:45:40.685075 RX Vref 0 -> 0, step: 1
4045 00:45:40.685166
4046 00:45:40.688496 RX Delay -230 -> 252, step: 16
4047 00:45:40.691776 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4048 00:45:40.695227 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4049 00:45:40.702037 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4050 00:45:40.705214 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4051 00:45:40.708591 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4052 00:45:40.711935 iDelay=218, Bit 5, Center 49 (-102 ~ 201) 304
4053 00:45:40.715266 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4054 00:45:40.721826 iDelay=218, Bit 7, Center 65 (-86 ~ 217) 304
4055 00:45:40.725138 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4056 00:45:40.728272 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4057 00:45:40.732024 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4058 00:45:40.735498 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4059 00:45:40.742014 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4060 00:45:40.745175 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4061 00:45:40.748541 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4062 00:45:40.755026 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4063 00:45:40.755098 ==
4064 00:45:40.758434 Dram Type= 6, Freq= 0, CH_0, rank 0
4065 00:45:40.761687 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4066 00:45:40.761779 ==
4067 00:45:40.761892 DQS Delay:
4068 00:45:40.765099 DQS0 = 0, DQS1 = 0
4069 00:45:40.765192 DQM Delay:
4070 00:45:40.768443 DQM0 = 54, DQM1 = 44
4071 00:45:40.768538 DQ Delay:
4072 00:45:40.771777 DQ0 =49, DQ1 =57, DQ2 =49, DQ3 =49
4073 00:45:40.775183 DQ4 =49, DQ5 =49, DQ6 =65, DQ7 =65
4074 00:45:40.778509 DQ8 =33, DQ9 =25, DQ10 =49, DQ11 =41
4075 00:45:40.781783 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =49
4076 00:45:40.781845
4077 00:45:40.781900
4078 00:45:40.781950 ==
4079 00:45:40.784606 Dram Type= 6, Freq= 0, CH_0, rank 0
4080 00:45:40.787967 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4081 00:45:40.788051 ==
4082 00:45:40.788115
4083 00:45:40.788170
4084 00:45:40.791316 TX Vref Scan disable
4085 00:45:40.794576 == TX Byte 0 ==
4086 00:45:40.798295 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4087 00:45:40.801343 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4088 00:45:40.805145 == TX Byte 1 ==
4089 00:45:40.807868 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4090 00:45:40.811455 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4091 00:45:40.811550 ==
4092 00:45:40.814855 Dram Type= 6, Freq= 0, CH_0, rank 0
4093 00:45:40.821139 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4094 00:45:40.821216 ==
4095 00:45:40.821296
4096 00:45:40.821366
4097 00:45:40.821419 TX Vref Scan disable
4098 00:45:40.825697 == TX Byte 0 ==
4099 00:45:40.828731 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4100 00:45:40.831963 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4101 00:45:40.835275 == TX Byte 1 ==
4102 00:45:40.838724 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4103 00:45:40.845329 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4104 00:45:40.845430
4105 00:45:40.845490 [DATLAT]
4106 00:45:40.845552 Freq=600, CH0 RK0
4107 00:45:40.845621
4108 00:45:40.848641 DATLAT Default: 0x9
4109 00:45:40.848732 0, 0xFFFF, sum = 0
4110 00:45:40.851899 1, 0xFFFF, sum = 0
4111 00:45:40.851978 2, 0xFFFF, sum = 0
4112 00:45:40.855679 3, 0xFFFF, sum = 0
4113 00:45:40.858696 4, 0xFFFF, sum = 0
4114 00:45:40.858788 5, 0xFFFF, sum = 0
4115 00:45:40.862164 6, 0xFFFF, sum = 0
4116 00:45:40.862242 7, 0xFFFF, sum = 0
4117 00:45:40.865432 8, 0x0, sum = 1
4118 00:45:40.865556 9, 0x0, sum = 2
4119 00:45:40.865636 10, 0x0, sum = 3
4120 00:45:40.868550 11, 0x0, sum = 4
4121 00:45:40.868643 best_step = 9
4122 00:45:40.868702
4123 00:45:40.868756 ==
4124 00:45:40.872048 Dram Type= 6, Freq= 0, CH_0, rank 0
4125 00:45:40.878923 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4126 00:45:40.879000 ==
4127 00:45:40.879059 RX Vref Scan: 1
4128 00:45:40.879143
4129 00:45:40.881981 RX Vref 0 -> 0, step: 1
4130 00:45:40.882057
4131 00:45:40.885319 RX Delay -179 -> 252, step: 8
4132 00:45:40.885410
4133 00:45:40.888640 Set Vref, RX VrefLevel [Byte0]: 57
4134 00:45:40.892033 [Byte1]: 49
4135 00:45:40.892109
4136 00:45:40.895370 Final RX Vref Byte 0 = 57 to rank0
4137 00:45:40.898753 Final RX Vref Byte 1 = 49 to rank0
4138 00:45:40.902093 Final RX Vref Byte 0 = 57 to rank1
4139 00:45:40.905231 Final RX Vref Byte 1 = 49 to rank1==
4140 00:45:40.908621 Dram Type= 6, Freq= 0, CH_0, rank 0
4141 00:45:40.911999 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4142 00:45:40.912089 ==
4143 00:45:40.915408 DQS Delay:
4144 00:45:40.915519 DQS0 = 0, DQS1 = 0
4145 00:45:40.915608 DQM Delay:
4146 00:45:40.918342 DQM0 = 54, DQM1 = 45
4147 00:45:40.918428 DQ Delay:
4148 00:45:40.921917 DQ0 =52, DQ1 =56, DQ2 =52, DQ3 =52
4149 00:45:40.925092 DQ4 =56, DQ5 =44, DQ6 =60, DQ7 =60
4150 00:45:40.928489 DQ8 =32, DQ9 =36, DQ10 =48, DQ11 =40
4151 00:45:40.931879 DQ12 =52, DQ13 =48, DQ14 =56, DQ15 =52
4152 00:45:40.931966
4153 00:45:40.932049
4154 00:45:40.941959 [DQSOSCAuto] RK0, (LSB)MR18= 0x776a, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 387 ps
4155 00:45:40.942048 CH0 RK0: MR19=808, MR18=776A
4156 00:45:40.948505 CH0_RK0: MR19=0x808, MR18=0x776A, DQSOSC=387, MR23=63, INC=175, DEC=116
4157 00:45:40.948582
4158 00:45:40.951957 ----->DramcWriteLeveling(PI) begin...
4159 00:45:40.955345 ==
4160 00:45:40.958787 Dram Type= 6, Freq= 0, CH_0, rank 1
4161 00:45:40.962128 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4162 00:45:40.962205 ==
4163 00:45:40.965306 Write leveling (Byte 0): 33 => 33
4164 00:45:40.968686 Write leveling (Byte 1): 29 => 29
4165 00:45:40.972029 DramcWriteLeveling(PI) end<-----
4166 00:45:40.972104
4167 00:45:40.972184 ==
4168 00:45:40.975387 Dram Type= 6, Freq= 0, CH_0, rank 1
4169 00:45:40.978700 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4170 00:45:40.978776 ==
4171 00:45:40.981933 [Gating] SW mode calibration
4172 00:45:40.988337 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4173 00:45:40.992261 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4174 00:45:40.998571 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4175 00:45:41.002101 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4176 00:45:41.005408 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4177 00:45:41.011686 0 9 12 | B1->B0 | 3434 3232 | 1 1 | (1 0) (1 0)
4178 00:45:41.015083 0 9 16 | B1->B0 | 2929 2929 | 0 0 | (1 1) (1 1)
4179 00:45:41.018329 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4180 00:45:41.025092 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4181 00:45:41.028442 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4182 00:45:41.031851 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4183 00:45:41.038700 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4184 00:45:41.041936 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4185 00:45:41.044967 0 10 12 | B1->B0 | 2626 2d2d | 0 0 | (0 0) (0 0)
4186 00:45:41.052022 0 10 16 | B1->B0 | 3d3d 4141 | 0 0 | (1 1) (1 1)
4187 00:45:41.055030 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4188 00:45:41.058528 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4189 00:45:41.065318 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4190 00:45:41.068421 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4191 00:45:41.071844 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4192 00:45:41.078559 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4193 00:45:41.081709 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4194 00:45:41.085073 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4195 00:45:41.088454 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4196 00:45:41.095070 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4197 00:45:41.098312 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4198 00:45:41.102161 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4199 00:45:41.108783 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4200 00:45:41.111585 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4201 00:45:41.114801 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4202 00:45:41.121481 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4203 00:45:41.125102 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4204 00:45:41.128082 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4205 00:45:41.134721 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4206 00:45:41.138031 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4207 00:45:41.141289 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4208 00:45:41.147947 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4209 00:45:41.151427 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4210 00:45:41.154769 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4211 00:45:41.158144 Total UI for P1: 0, mck2ui 16
4212 00:45:41.161417 best dqsien dly found for B0: ( 0, 13, 12)
4213 00:45:41.164577 Total UI for P1: 0, mck2ui 16
4214 00:45:41.168064 best dqsien dly found for B1: ( 0, 13, 14)
4215 00:45:41.171475 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4216 00:45:41.174548 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4217 00:45:41.174625
4218 00:45:41.181688 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4219 00:45:41.184483 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4220 00:45:41.188197 [Gating] SW calibration Done
4221 00:45:41.188274 ==
4222 00:45:41.191231 Dram Type= 6, Freq= 0, CH_0, rank 1
4223 00:45:41.194761 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4224 00:45:41.194839 ==
4225 00:45:41.194899 RX Vref Scan: 0
4226 00:45:41.194954
4227 00:45:41.198118 RX Vref 0 -> 0, step: 1
4228 00:45:41.198195
4229 00:45:41.201530 RX Delay -230 -> 252, step: 16
4230 00:45:41.204736 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4231 00:45:41.208102 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4232 00:45:41.214646 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4233 00:45:41.217827 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4234 00:45:41.221259 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4235 00:45:41.224672 iDelay=218, Bit 5, Center 49 (-102 ~ 201) 304
4236 00:45:41.231292 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4237 00:45:41.234491 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4238 00:45:41.238149 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4239 00:45:41.241020 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4240 00:45:41.244775 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4241 00:45:41.251068 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4242 00:45:41.254540 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4243 00:45:41.257872 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4244 00:45:41.261230 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4245 00:45:41.268081 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4246 00:45:41.268157 ==
4247 00:45:41.271347 Dram Type= 6, Freq= 0, CH_0, rank 1
4248 00:45:41.274647 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4249 00:45:41.274723 ==
4250 00:45:41.274783 DQS Delay:
4251 00:45:41.278000 DQS0 = 0, DQS1 = 0
4252 00:45:41.278077 DQM Delay:
4253 00:45:41.281446 DQM0 = 52, DQM1 = 43
4254 00:45:41.281538 DQ Delay:
4255 00:45:41.284736 DQ0 =49, DQ1 =49, DQ2 =49, DQ3 =49
4256 00:45:41.288242 DQ4 =57, DQ5 =49, DQ6 =57, DQ7 =57
4257 00:45:41.291430 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =33
4258 00:45:41.294520 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4259 00:45:41.294608
4260 00:45:41.294689
4261 00:45:41.294770 ==
4262 00:45:41.297729 Dram Type= 6, Freq= 0, CH_0, rank 1
4263 00:45:41.301126 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4264 00:45:41.301213 ==
4265 00:45:41.304240
4266 00:45:41.304371
4267 00:45:41.304452 TX Vref Scan disable
4268 00:45:41.308050 == TX Byte 0 ==
4269 00:45:41.311199 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4270 00:45:41.314143 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4271 00:45:41.317409 == TX Byte 1 ==
4272 00:45:41.320731 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4273 00:45:41.324346 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4274 00:45:41.327541 ==
4275 00:45:41.327632 Dram Type= 6, Freq= 0, CH_0, rank 1
4276 00:45:41.334047 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4277 00:45:41.334125 ==
4278 00:45:41.334186
4279 00:45:41.334242
4280 00:45:41.337375 TX Vref Scan disable
4281 00:45:41.337438 == TX Byte 0 ==
4282 00:45:41.344116 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4283 00:45:41.347409 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4284 00:45:41.347485 == TX Byte 1 ==
4285 00:45:41.354120 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4286 00:45:41.357291 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4287 00:45:41.357368
4288 00:45:41.357426 [DATLAT]
4289 00:45:41.360785 Freq=600, CH0 RK1
4290 00:45:41.360862
4291 00:45:41.360921 DATLAT Default: 0x9
4292 00:45:41.364242 0, 0xFFFF, sum = 0
4293 00:45:41.364320 1, 0xFFFF, sum = 0
4294 00:45:41.367148 2, 0xFFFF, sum = 0
4295 00:45:41.367225 3, 0xFFFF, sum = 0
4296 00:45:41.370587 4, 0xFFFF, sum = 0
4297 00:45:41.373964 5, 0xFFFF, sum = 0
4298 00:45:41.374041 6, 0xFFFF, sum = 0
4299 00:45:41.377355 7, 0xFFFF, sum = 0
4300 00:45:41.377432 8, 0x0, sum = 1
4301 00:45:41.377492 9, 0x0, sum = 2
4302 00:45:41.380724 10, 0x0, sum = 3
4303 00:45:41.380801 11, 0x0, sum = 4
4304 00:45:41.384187 best_step = 9
4305 00:45:41.384263
4306 00:45:41.384322 ==
4307 00:45:41.387441 Dram Type= 6, Freq= 0, CH_0, rank 1
4308 00:45:41.390753 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4309 00:45:41.390829 ==
4310 00:45:41.393455 RX Vref Scan: 0
4311 00:45:41.393552
4312 00:45:41.393628 RX Vref 0 -> 0, step: 1
4313 00:45:41.393683
4314 00:45:41.396749 RX Delay -163 -> 252, step: 8
4315 00:45:41.404320 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4316 00:45:41.407635 iDelay=205, Bit 1, Center 56 (-83 ~ 196) 280
4317 00:45:41.411000 iDelay=205, Bit 2, Center 52 (-91 ~ 196) 288
4318 00:45:41.414349 iDelay=205, Bit 3, Center 52 (-91 ~ 196) 288
4319 00:45:41.417597 iDelay=205, Bit 4, Center 56 (-83 ~ 196) 280
4320 00:45:41.424063 iDelay=205, Bit 5, Center 44 (-99 ~ 188) 288
4321 00:45:41.427785 iDelay=205, Bit 6, Center 56 (-83 ~ 196) 280
4322 00:45:41.431346 iDelay=205, Bit 7, Center 64 (-75 ~ 204) 280
4323 00:45:41.434207 iDelay=205, Bit 8, Center 36 (-107 ~ 180) 288
4324 00:45:41.437368 iDelay=205, Bit 9, Center 36 (-107 ~ 180) 288
4325 00:45:41.444521 iDelay=205, Bit 10, Center 48 (-91 ~ 188) 280
4326 00:45:41.447238 iDelay=205, Bit 11, Center 36 (-107 ~ 180) 288
4327 00:45:41.450717 iDelay=205, Bit 12, Center 52 (-83 ~ 188) 272
4328 00:45:41.454464 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4329 00:45:41.461085 iDelay=205, Bit 14, Center 56 (-83 ~ 196) 280
4330 00:45:41.464429 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4331 00:45:41.464508 ==
4332 00:45:41.467646 Dram Type= 6, Freq= 0, CH_0, rank 1
4333 00:45:41.470673 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4334 00:45:41.470749 ==
4335 00:45:41.474006 DQS Delay:
4336 00:45:41.474082 DQS0 = 0, DQS1 = 0
4337 00:45:41.474141 DQM Delay:
4338 00:45:41.477300 DQM0 = 54, DQM1 = 46
4339 00:45:41.477375 DQ Delay:
4340 00:45:41.480499 DQ0 =52, DQ1 =56, DQ2 =52, DQ3 =52
4341 00:45:41.483860 DQ4 =56, DQ5 =44, DQ6 =56, DQ7 =64
4342 00:45:41.487034 DQ8 =36, DQ9 =36, DQ10 =48, DQ11 =36
4343 00:45:41.490722 DQ12 =52, DQ13 =52, DQ14 =56, DQ15 =52
4344 00:45:41.490798
4345 00:45:41.490857
4346 00:45:41.500686 [DQSOSCAuto] RK1, (LSB)MR18= 0x6b2b, (MSB)MR19= 0x808, tDQSOscB0 = 401 ps tDQSOscB1 = 389 ps
4347 00:45:41.500761 CH0 RK1: MR19=808, MR18=6B2B
4348 00:45:41.507360 CH0_RK1: MR19=0x808, MR18=0x6B2B, DQSOSC=389, MR23=63, INC=173, DEC=115
4349 00:45:41.510828 [RxdqsGatingPostProcess] freq 600
4350 00:45:41.517478 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4351 00:45:41.520750 Pre-setting of DQS Precalculation
4352 00:45:41.524188 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4353 00:45:41.524263 ==
4354 00:45:41.527394 Dram Type= 6, Freq= 0, CH_1, rank 0
4355 00:45:41.534018 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4356 00:45:41.534094 ==
4357 00:45:41.537342 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4358 00:45:41.543930 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4359 00:45:41.547089 [CA 0] Center 36 (5~67) winsize 63
4360 00:45:41.550099 [CA 1] Center 36 (5~67) winsize 63
4361 00:45:41.553652 [CA 2] Center 34 (4~65) winsize 62
4362 00:45:41.556584 [CA 3] Center 34 (4~65) winsize 62
4363 00:45:41.559986 [CA 4] Center 34 (4~65) winsize 62
4364 00:45:41.563539 [CA 5] Center 34 (3~65) winsize 63
4365 00:45:41.563614
4366 00:45:41.566904 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4367 00:45:41.566980
4368 00:45:41.569908 [CATrainingPosCal] consider 1 rank data
4369 00:45:41.573205 u2DelayCellTimex100 = 270/100 ps
4370 00:45:41.576958 CA0 delay=36 (5~67),Diff = 2 PI (19 cell)
4371 00:45:41.580334 CA1 delay=36 (5~67),Diff = 2 PI (19 cell)
4372 00:45:41.586948 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4373 00:45:41.590276 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4374 00:45:41.593586 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4375 00:45:41.596872 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4376 00:45:41.596963
4377 00:45:41.600255 CA PerBit enable=1, Macro0, CA PI delay=34
4378 00:45:41.600345
4379 00:45:41.603557 [CBTSetCACLKResult] CA Dly = 34
4380 00:45:41.603632 CS Dly: 5 (0~36)
4381 00:45:41.603691 ==
4382 00:45:41.606968 Dram Type= 6, Freq= 0, CH_1, rank 1
4383 00:45:41.613712 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4384 00:45:41.613789 ==
4385 00:45:41.616893 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4386 00:45:41.623524 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4387 00:45:41.626773 [CA 0] Center 36 (6~67) winsize 62
4388 00:45:41.630135 [CA 1] Center 36 (5~67) winsize 63
4389 00:45:41.633417 [CA 2] Center 34 (4~65) winsize 62
4390 00:45:41.636621 [CA 3] Center 34 (4~65) winsize 62
4391 00:45:41.639947 [CA 4] Center 34 (4~65) winsize 62
4392 00:45:41.643344 [CA 5] Center 34 (3~65) winsize 63
4393 00:45:41.643431
4394 00:45:41.646621 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4395 00:45:41.646691
4396 00:45:41.649978 [CATrainingPosCal] consider 2 rank data
4397 00:45:41.653204 u2DelayCellTimex100 = 270/100 ps
4398 00:45:41.657083 CA0 delay=36 (6~67),Diff = 2 PI (19 cell)
4399 00:45:41.663655 CA1 delay=36 (5~67),Diff = 2 PI (19 cell)
4400 00:45:41.666653 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4401 00:45:41.670331 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4402 00:45:41.673403 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4403 00:45:41.676474 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4404 00:45:41.676535
4405 00:45:41.680023 CA PerBit enable=1, Macro0, CA PI delay=34
4406 00:45:41.680100
4407 00:45:41.683282 [CBTSetCACLKResult] CA Dly = 34
4408 00:45:41.683363 CS Dly: 6 (0~38)
4409 00:45:41.683434
4410 00:45:41.686590 ----->DramcWriteLeveling(PI) begin...
4411 00:45:41.689892 ==
4412 00:45:41.693442 Dram Type= 6, Freq= 0, CH_1, rank 0
4413 00:45:41.696642 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4414 00:45:41.696719 ==
4415 00:45:41.700493 Write leveling (Byte 0): 30 => 30
4416 00:45:41.703859 Write leveling (Byte 1): 30 => 30
4417 00:45:41.707239 DramcWriteLeveling(PI) end<-----
4418 00:45:41.707317
4419 00:45:41.707378 ==
4420 00:45:41.710528 Dram Type= 6, Freq= 0, CH_1, rank 0
4421 00:45:41.713949 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4422 00:45:41.714028 ==
4423 00:45:41.716690 [Gating] SW mode calibration
4424 00:45:41.723416 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4425 00:45:41.727251 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4426 00:45:41.733431 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4427 00:45:41.736871 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4428 00:45:41.740267 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4429 00:45:41.746724 0 9 12 | B1->B0 | 2f2f 2d2d | 1 0 | (1 0) (0 0)
4430 00:45:41.750082 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4431 00:45:41.753378 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4432 00:45:41.759975 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4433 00:45:41.763388 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4434 00:45:41.766710 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4435 00:45:41.773814 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4436 00:45:41.776704 0 10 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
4437 00:45:41.779982 0 10 12 | B1->B0 | 3737 3737 | 0 0 | (0 0) (0 0)
4438 00:45:41.786630 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4439 00:45:41.789731 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4440 00:45:41.793446 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4441 00:45:41.800072 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4442 00:45:41.802920 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4443 00:45:41.806408 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4444 00:45:41.813169 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4445 00:45:41.816469 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4446 00:45:41.819988 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4447 00:45:41.826710 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4448 00:45:41.829439 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4449 00:45:41.832795 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4450 00:45:41.839641 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4451 00:45:41.842758 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4452 00:45:41.846479 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4453 00:45:41.853226 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4454 00:45:41.856670 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4455 00:45:41.860312 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4456 00:45:41.863053 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4457 00:45:41.869975 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4458 00:45:41.872880 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4459 00:45:41.876136 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4460 00:45:41.883087 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4461 00:45:41.886285 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4462 00:45:41.889685 Total UI for P1: 0, mck2ui 16
4463 00:45:41.892906 best dqsien dly found for B0: ( 0, 13, 10)
4464 00:45:41.896338 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4465 00:45:41.899578 Total UI for P1: 0, mck2ui 16
4466 00:45:41.902906 best dqsien dly found for B1: ( 0, 13, 12)
4467 00:45:41.906079 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4468 00:45:41.909314 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4469 00:45:41.909391
4470 00:45:41.916225 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4471 00:45:41.919353 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4472 00:45:41.922593 [Gating] SW calibration Done
4473 00:45:41.922669 ==
4474 00:45:41.926103 Dram Type= 6, Freq= 0, CH_1, rank 0
4475 00:45:41.929481 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4476 00:45:41.929565 ==
4477 00:45:41.929642 RX Vref Scan: 0
4478 00:45:41.929697
4479 00:45:41.932806 RX Vref 0 -> 0, step: 1
4480 00:45:41.932882
4481 00:45:41.936247 RX Delay -230 -> 252, step: 16
4482 00:45:41.939712 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4483 00:45:41.943031 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4484 00:45:41.949640 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4485 00:45:41.952851 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4486 00:45:41.956205 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4487 00:45:41.959640 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4488 00:45:41.966333 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4489 00:45:41.969540 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4490 00:45:41.972610 iDelay=218, Bit 8, Center 41 (-102 ~ 185) 288
4491 00:45:41.976341 iDelay=218, Bit 9, Center 41 (-102 ~ 185) 288
4492 00:45:41.979672 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4493 00:45:41.985889 iDelay=218, Bit 11, Center 49 (-102 ~ 201) 304
4494 00:45:41.989588 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4495 00:45:41.992866 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4496 00:45:41.995846 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4497 00:45:42.002470 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4498 00:45:42.002547 ==
4499 00:45:42.006080 Dram Type= 6, Freq= 0, CH_1, rank 0
4500 00:45:42.009223 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4501 00:45:42.009299 ==
4502 00:45:42.009359 DQS Delay:
4503 00:45:42.012337 DQS0 = 0, DQS1 = 0
4504 00:45:42.012413 DQM Delay:
4505 00:45:42.016213 DQM0 = 52, DQM1 = 49
4506 00:45:42.016289 DQ Delay:
4507 00:45:42.019136 DQ0 =57, DQ1 =49, DQ2 =49, DQ3 =49
4508 00:45:42.023033 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49
4509 00:45:42.026099 DQ8 =41, DQ9 =41, DQ10 =49, DQ11 =49
4510 00:45:42.029205 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4511 00:45:42.029281
4512 00:45:42.029392
4513 00:45:42.029447 ==
4514 00:45:42.032469 Dram Type= 6, Freq= 0, CH_1, rank 0
4515 00:45:42.035924 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4516 00:45:42.036032 ==
4517 00:45:42.039147
4518 00:45:42.039223
4519 00:45:42.039282 TX Vref Scan disable
4520 00:45:42.042329 == TX Byte 0 ==
4521 00:45:42.045717 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4522 00:45:42.049106 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4523 00:45:42.052280 == TX Byte 1 ==
4524 00:45:42.055524 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4525 00:45:42.058928 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4526 00:45:42.062382 ==
4527 00:45:42.062458 Dram Type= 6, Freq= 0, CH_1, rank 0
4528 00:45:42.069251 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4529 00:45:42.069357 ==
4530 00:45:42.069417
4531 00:45:42.069473
4532 00:45:42.072524 TX Vref Scan disable
4533 00:45:42.072600 == TX Byte 0 ==
4534 00:45:42.079179 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4535 00:45:42.082502 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4536 00:45:42.082580 == TX Byte 1 ==
4537 00:45:42.089206 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4538 00:45:42.092736 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4539 00:45:42.092876
4540 00:45:42.092936 [DATLAT]
4541 00:45:42.095732 Freq=600, CH1 RK0
4542 00:45:42.095809
4543 00:45:42.095869 DATLAT Default: 0x9
4544 00:45:42.098919 0, 0xFFFF, sum = 0
4545 00:45:42.098999 1, 0xFFFF, sum = 0
4546 00:45:42.102257 2, 0xFFFF, sum = 0
4547 00:45:42.102336 3, 0xFFFF, sum = 0
4548 00:45:42.105895 4, 0xFFFF, sum = 0
4549 00:45:42.105974 5, 0xFFFF, sum = 0
4550 00:45:42.108972 6, 0xFFFF, sum = 0
4551 00:45:42.109103 7, 0xFFFF, sum = 0
4552 00:45:42.112599 8, 0x0, sum = 1
4553 00:45:42.112700 9, 0x0, sum = 2
4554 00:45:42.115712 10, 0x0, sum = 3
4555 00:45:42.115834 11, 0x0, sum = 4
4556 00:45:42.119029 best_step = 9
4557 00:45:42.119125
4558 00:45:42.119210 ==
4559 00:45:42.122278 Dram Type= 6, Freq= 0, CH_1, rank 0
4560 00:45:42.125827 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4561 00:45:42.125893 ==
4562 00:45:42.129114 RX Vref Scan: 1
4563 00:45:42.129199
4564 00:45:42.129279 RX Vref 0 -> 0, step: 1
4565 00:45:42.129356
4566 00:45:42.132406 RX Delay -147 -> 252, step: 8
4567 00:45:42.132496
4568 00:45:42.135692 Set Vref, RX VrefLevel [Byte0]: 55
4569 00:45:42.138630 [Byte1]: 50
4570 00:45:42.142333
4571 00:45:42.142427 Final RX Vref Byte 0 = 55 to rank0
4572 00:45:42.145532 Final RX Vref Byte 1 = 50 to rank0
4573 00:45:42.149274 Final RX Vref Byte 0 = 55 to rank1
4574 00:45:42.152315 Final RX Vref Byte 1 = 50 to rank1==
4575 00:45:42.155653 Dram Type= 6, Freq= 0, CH_1, rank 0
4576 00:45:42.162330 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4577 00:45:42.162399 ==
4578 00:45:42.162458 DQS Delay:
4579 00:45:42.162513 DQS0 = 0, DQS1 = 0
4580 00:45:42.165693 DQM Delay:
4581 00:45:42.165754 DQM0 = 48, DQM1 = 45
4582 00:45:42.169018 DQ Delay:
4583 00:45:42.172309 DQ0 =52, DQ1 =40, DQ2 =36, DQ3 =44
4584 00:45:42.172369 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4585 00:45:42.175630 DQ8 =32, DQ9 =36, DQ10 =44, DQ11 =36
4586 00:45:42.178981 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =56
4587 00:45:42.182361
4588 00:45:42.182419
4589 00:45:42.189138 [DQSOSCAuto] RK0, (LSB)MR18= 0x4e74, (MSB)MR19= 0x808, tDQSOscB0 = 388 ps tDQSOscB1 = 395 ps
4590 00:45:42.192394 CH1 RK0: MR19=808, MR18=4E74
4591 00:45:42.199045 CH1_RK0: MR19=0x808, MR18=0x4E74, DQSOSC=388, MR23=63, INC=174, DEC=116
4592 00:45:42.199111
4593 00:45:42.202223 ----->DramcWriteLeveling(PI) begin...
4594 00:45:42.202287 ==
4595 00:45:42.205846 Dram Type= 6, Freq= 0, CH_1, rank 1
4596 00:45:42.209144 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4597 00:45:42.209229 ==
4598 00:45:42.212338 Write leveling (Byte 0): 29 => 29
4599 00:45:42.215598 Write leveling (Byte 1): 31 => 31
4600 00:45:42.218968 DramcWriteLeveling(PI) end<-----
4601 00:45:42.219044
4602 00:45:42.219103 ==
4603 00:45:42.222309 Dram Type= 6, Freq= 0, CH_1, rank 1
4604 00:45:42.225679 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4605 00:45:42.225756 ==
4606 00:45:42.228772 [Gating] SW mode calibration
4607 00:45:42.235509 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4608 00:45:42.242279 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4609 00:45:42.245751 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4610 00:45:42.248988 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4611 00:45:42.255499 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
4612 00:45:42.258602 0 9 12 | B1->B0 | 2d2d 2e2e | 0 0 | (0 0) (0 0)
4613 00:45:42.262272 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4614 00:45:42.268786 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4615 00:45:42.272393 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4616 00:45:42.275557 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4617 00:45:42.282174 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4618 00:45:42.285420 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4619 00:45:42.288911 0 10 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4620 00:45:42.295699 0 10 12 | B1->B0 | 3333 3636 | 1 0 | (0 0) (1 1)
4621 00:45:42.299119 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4622 00:45:42.301870 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4623 00:45:42.308371 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4624 00:45:42.311989 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4625 00:45:42.314969 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4626 00:45:42.322071 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4627 00:45:42.325334 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4628 00:45:42.328661 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4629 00:45:42.335190 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4630 00:45:42.338472 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4631 00:45:42.341681 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4632 00:45:42.348309 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4633 00:45:42.351763 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4634 00:45:42.354919 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4635 00:45:42.361416 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4636 00:45:42.365227 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4637 00:45:42.368415 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4638 00:45:42.374653 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4639 00:45:42.378283 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4640 00:45:42.381823 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4641 00:45:42.388501 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4642 00:45:42.391455 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4643 00:45:42.394833 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4644 00:45:42.398203 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4645 00:45:42.401404 Total UI for P1: 0, mck2ui 16
4646 00:45:42.404703 best dqsien dly found for B0: ( 0, 13, 10)
4647 00:45:42.408147 Total UI for P1: 0, mck2ui 16
4648 00:45:42.411531 best dqsien dly found for B1: ( 0, 13, 10)
4649 00:45:42.414793 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4650 00:45:42.421567 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4651 00:45:42.421659
4652 00:45:42.424705 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4653 00:45:42.428386 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4654 00:45:42.431487 [Gating] SW calibration Done
4655 00:45:42.431598 ==
4656 00:45:42.434770 Dram Type= 6, Freq= 0, CH_1, rank 1
4657 00:45:42.437968 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4658 00:45:42.438036 ==
4659 00:45:42.438101 RX Vref Scan: 0
4660 00:45:42.441831
4661 00:45:42.441918 RX Vref 0 -> 0, step: 1
4662 00:45:42.441999
4663 00:45:42.445073 RX Delay -230 -> 252, step: 16
4664 00:45:42.447794 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4665 00:45:42.455156 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4666 00:45:42.458473 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4667 00:45:42.461706 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4668 00:45:42.464978 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4669 00:45:42.468243 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4670 00:45:42.475061 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4671 00:45:42.478247 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4672 00:45:42.481558 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4673 00:45:42.484944 iDelay=218, Bit 9, Center 41 (-118 ~ 201) 320
4674 00:45:42.491438 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4675 00:45:42.494709 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4676 00:45:42.497680 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4677 00:45:42.501360 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4678 00:45:42.507665 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4679 00:45:42.511229 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4680 00:45:42.511317 ==
4681 00:45:42.514559 Dram Type= 6, Freq= 0, CH_1, rank 1
4682 00:45:42.517772 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4683 00:45:42.517861 ==
4684 00:45:42.517942 DQS Delay:
4685 00:45:42.520822 DQS0 = 0, DQS1 = 0
4686 00:45:42.520883 DQM Delay:
4687 00:45:42.524619 DQM0 = 46, DQM1 = 48
4688 00:45:42.524686 DQ Delay:
4689 00:45:42.527957 DQ0 =49, DQ1 =41, DQ2 =33, DQ3 =41
4690 00:45:42.531150 DQ4 =41, DQ5 =65, DQ6 =57, DQ7 =41
4691 00:45:42.534357 DQ8 =33, DQ9 =41, DQ10 =49, DQ11 =41
4692 00:45:42.537522 DQ12 =57, DQ13 =57, DQ14 =49, DQ15 =57
4693 00:45:42.537635
4694 00:45:42.537717
4695 00:45:42.537775 ==
4696 00:45:42.541458 Dram Type= 6, Freq= 0, CH_1, rank 1
4697 00:45:42.544585 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4698 00:45:42.547678 ==
4699 00:45:42.547765
4700 00:45:42.547844
4701 00:45:42.547921 TX Vref Scan disable
4702 00:45:42.550813 == TX Byte 0 ==
4703 00:45:42.554205 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4704 00:45:42.557484 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4705 00:45:42.560938 == TX Byte 1 ==
4706 00:45:42.564314 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4707 00:45:42.570789 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4708 00:45:42.570859 ==
4709 00:45:42.574251 Dram Type= 6, Freq= 0, CH_1, rank 1
4710 00:45:42.577519 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4711 00:45:42.577638 ==
4712 00:45:42.577695
4713 00:45:42.577747
4714 00:45:42.580878 TX Vref Scan disable
4715 00:45:42.584095 == TX Byte 0 ==
4716 00:45:42.587560 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4717 00:45:42.590728 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4718 00:45:42.593990 == TX Byte 1 ==
4719 00:45:42.597334 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4720 00:45:42.600679 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4721 00:45:42.600766
4722 00:45:42.600848 [DATLAT]
4723 00:45:42.604058 Freq=600, CH1 RK1
4724 00:45:42.604142
4725 00:45:42.604221 DATLAT Default: 0x9
4726 00:45:42.607331 0, 0xFFFF, sum = 0
4727 00:45:42.610643 1, 0xFFFF, sum = 0
4728 00:45:42.610704 2, 0xFFFF, sum = 0
4729 00:45:42.614419 3, 0xFFFF, sum = 0
4730 00:45:42.614509 4, 0xFFFF, sum = 0
4731 00:45:42.617127 5, 0xFFFF, sum = 0
4732 00:45:42.617215 6, 0xFFFF, sum = 0
4733 00:45:42.620355 7, 0xFFFF, sum = 0
4734 00:45:42.620441 8, 0x0, sum = 1
4735 00:45:42.623642 9, 0x0, sum = 2
4736 00:45:42.623704 10, 0x0, sum = 3
4737 00:45:42.623757 11, 0x0, sum = 4
4738 00:45:42.626905 best_step = 9
4739 00:45:42.626988
4740 00:45:42.627065 ==
4741 00:45:42.630415 Dram Type= 6, Freq= 0, CH_1, rank 1
4742 00:45:42.633916 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4743 00:45:42.634002 ==
4744 00:45:42.637135 RX Vref Scan: 0
4745 00:45:42.637220
4746 00:45:42.637299 RX Vref 0 -> 0, step: 1
4747 00:45:42.640164
4748 00:45:42.640252 RX Delay -163 -> 252, step: 8
4749 00:45:42.647633 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4750 00:45:42.650906 iDelay=205, Bit 1, Center 44 (-99 ~ 188) 288
4751 00:45:42.654276 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4752 00:45:42.657493 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4753 00:45:42.664567 iDelay=205, Bit 4, Center 44 (-99 ~ 188) 288
4754 00:45:42.667539 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4755 00:45:42.670748 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4756 00:45:42.674641 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4757 00:45:42.678008 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4758 00:45:42.684558 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4759 00:45:42.687802 iDelay=205, Bit 10, Center 48 (-99 ~ 196) 296
4760 00:45:42.691220 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4761 00:45:42.694463 iDelay=205, Bit 12, Center 56 (-91 ~ 204) 296
4762 00:45:42.697483 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4763 00:45:42.704646 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4764 00:45:42.707974 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4765 00:45:42.708038 ==
4766 00:45:42.711313 Dram Type= 6, Freq= 0, CH_1, rank 1
4767 00:45:42.714637 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4768 00:45:42.714715 ==
4769 00:45:42.717796 DQS Delay:
4770 00:45:42.717873 DQS0 = 0, DQS1 = 0
4771 00:45:42.717932 DQM Delay:
4772 00:45:42.721365 DQM0 = 48, DQM1 = 45
4773 00:45:42.721464 DQ Delay:
4774 00:45:42.724664 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4775 00:45:42.727993 DQ4 =44, DQ5 =60, DQ6 =60, DQ7 =48
4776 00:45:42.731310 DQ8 =32, DQ9 =32, DQ10 =48, DQ11 =40
4777 00:45:42.734642 DQ12 =56, DQ13 =52, DQ14 =52, DQ15 =52
4778 00:45:42.734718
4779 00:45:42.734778
4780 00:45:42.744787 [DQSOSCAuto] RK1, (LSB)MR18= 0x6d24, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 389 ps
4781 00:45:42.744865 CH1 RK1: MR19=808, MR18=6D24
4782 00:45:42.751304 CH1_RK1: MR19=0x808, MR18=0x6D24, DQSOSC=389, MR23=63, INC=173, DEC=115
4783 00:45:42.754628 [RxdqsGatingPostProcess] freq 600
4784 00:45:42.761783 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4785 00:45:42.764648 Pre-setting of DQS Precalculation
4786 00:45:42.767672 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4787 00:45:42.774445 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4788 00:45:42.781137 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4789 00:45:42.784384
4790 00:45:42.784460
4791 00:45:42.784519 [Calibration Summary] 1200 Mbps
4792 00:45:42.787910 CH 0, Rank 0
4793 00:45:42.787987 SW Impedance : PASS
4794 00:45:42.791147 DUTY Scan : NO K
4795 00:45:42.794635 ZQ Calibration : PASS
4796 00:45:42.794712 Jitter Meter : NO K
4797 00:45:42.797586 CBT Training : PASS
4798 00:45:42.800935 Write leveling : PASS
4799 00:45:42.801012 RX DQS gating : PASS
4800 00:45:42.804089 RX DQ/DQS(RDDQC) : PASS
4801 00:45:42.807661 TX DQ/DQS : PASS
4802 00:45:42.807759 RX DATLAT : PASS
4803 00:45:42.811514 RX DQ/DQS(Engine): PASS
4804 00:45:42.814808 TX OE : NO K
4805 00:45:42.814898 All Pass.
4806 00:45:42.814979
4807 00:45:42.815060 CH 0, Rank 1
4808 00:45:42.818126 SW Impedance : PASS
4809 00:45:42.820775 DUTY Scan : NO K
4810 00:45:42.820869 ZQ Calibration : PASS
4811 00:45:42.824726 Jitter Meter : NO K
4812 00:45:42.824804 CBT Training : PASS
4813 00:45:42.827877 Write leveling : PASS
4814 00:45:42.831163 RX DQS gating : PASS
4815 00:45:42.831240 RX DQ/DQS(RDDQC) : PASS
4816 00:45:42.834537 TX DQ/DQS : PASS
4817 00:45:42.837863 RX DATLAT : PASS
4818 00:45:42.837985 RX DQ/DQS(Engine): PASS
4819 00:45:42.841063 TX OE : NO K
4820 00:45:42.841156 All Pass.
4821 00:45:42.841239
4822 00:45:42.844349 CH 1, Rank 0
4823 00:45:42.844437 SW Impedance : PASS
4824 00:45:42.847717 DUTY Scan : NO K
4825 00:45:42.851006 ZQ Calibration : PASS
4826 00:45:42.851068 Jitter Meter : NO K
4827 00:45:42.854179 CBT Training : PASS
4828 00:45:42.857558 Write leveling : PASS
4829 00:45:42.857636 RX DQS gating : PASS
4830 00:45:42.860924 RX DQ/DQS(RDDQC) : PASS
4831 00:45:42.864270 TX DQ/DQS : PASS
4832 00:45:42.864348 RX DATLAT : PASS
4833 00:45:42.867602 RX DQ/DQS(Engine): PASS
4834 00:45:42.867678 TX OE : NO K
4835 00:45:42.870996 All Pass.
4836 00:45:42.871072
4837 00:45:42.871131 CH 1, Rank 1
4838 00:45:42.874388 SW Impedance : PASS
4839 00:45:42.874465 DUTY Scan : NO K
4840 00:45:42.877836 ZQ Calibration : PASS
4841 00:45:42.881137 Jitter Meter : NO K
4842 00:45:42.881215 CBT Training : PASS
4843 00:45:42.884474 Write leveling : PASS
4844 00:45:42.887709 RX DQS gating : PASS
4845 00:45:42.887785 RX DQ/DQS(RDDQC) : PASS
4846 00:45:42.891404 TX DQ/DQS : PASS
4847 00:45:42.894313 RX DATLAT : PASS
4848 00:45:42.894388 RX DQ/DQS(Engine): PASS
4849 00:45:42.897800 TX OE : NO K
4850 00:45:42.897877 All Pass.
4851 00:45:42.897936
4852 00:45:42.901198 DramC Write-DBI off
4853 00:45:42.904383 PER_BANK_REFRESH: Hybrid Mode
4854 00:45:42.904474 TX_TRACKING: ON
4855 00:45:42.914457 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4856 00:45:42.918036 [FAST_K] Save calibration result to emmc
4857 00:45:42.921057 dramc_set_vcore_voltage set vcore to 662500
4858 00:45:42.924379 Read voltage for 933, 3
4859 00:45:42.924474 Vio18 = 0
4860 00:45:42.924558 Vcore = 662500
4861 00:45:42.927850 Vdram = 0
4862 00:45:42.927952 Vddq = 0
4863 00:45:42.928047 Vmddr = 0
4864 00:45:42.934778 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4865 00:45:42.937851 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4866 00:45:42.941093 MEM_TYPE=3, freq_sel=17
4867 00:45:42.944495 sv_algorithm_assistance_LP4_1600
4868 00:45:42.947808 ============ PULL DRAM RESETB DOWN ============
4869 00:45:42.951060 ========== PULL DRAM RESETB DOWN end =========
4870 00:45:42.957635 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4871 00:45:42.961027 ===================================
4872 00:45:42.961124 LPDDR4 DRAM CONFIGURATION
4873 00:45:42.964311 ===================================
4874 00:45:42.967784 EX_ROW_EN[0] = 0x0
4875 00:45:42.971002 EX_ROW_EN[1] = 0x0
4876 00:45:42.971067 LP4Y_EN = 0x0
4877 00:45:42.974301 WORK_FSP = 0x0
4878 00:45:42.974381 WL = 0x3
4879 00:45:42.977649 RL = 0x3
4880 00:45:42.977734 BL = 0x2
4881 00:45:42.981088 RPST = 0x0
4882 00:45:42.981175 RD_PRE = 0x0
4883 00:45:42.984530 WR_PRE = 0x1
4884 00:45:42.984617 WR_PST = 0x0
4885 00:45:42.987980 DBI_WR = 0x0
4886 00:45:42.988058 DBI_RD = 0x0
4887 00:45:42.991332 OTF = 0x1
4888 00:45:42.994580 ===================================
4889 00:45:42.997871 ===================================
4890 00:45:42.997935 ANA top config
4891 00:45:43.001265 ===================================
4892 00:45:43.004607 DLL_ASYNC_EN = 0
4893 00:45:43.008025 ALL_SLAVE_EN = 1
4894 00:45:43.008090 NEW_RANK_MODE = 1
4895 00:45:43.011046 DLL_IDLE_MODE = 1
4896 00:45:43.014390 LP45_APHY_COMB_EN = 1
4897 00:45:43.017769 TX_ODT_DIS = 1
4898 00:45:43.021003 NEW_8X_MODE = 1
4899 00:45:43.024336 ===================================
4900 00:45:43.027434 ===================================
4901 00:45:43.027522 data_rate = 1866
4902 00:45:43.030714 CKR = 1
4903 00:45:43.034296 DQ_P2S_RATIO = 8
4904 00:45:43.037994 ===================================
4905 00:45:43.041087 CA_P2S_RATIO = 8
4906 00:45:43.044267 DQ_CA_OPEN = 0
4907 00:45:43.047759 DQ_SEMI_OPEN = 0
4908 00:45:43.047824 CA_SEMI_OPEN = 0
4909 00:45:43.050665 CA_FULL_RATE = 0
4910 00:45:43.053894 DQ_CKDIV4_EN = 1
4911 00:45:43.057604 CA_CKDIV4_EN = 1
4912 00:45:43.060623 CA_PREDIV_EN = 0
4913 00:45:43.064072 PH8_DLY = 0
4914 00:45:43.064150 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4915 00:45:43.068023 DQ_AAMCK_DIV = 4
4916 00:45:43.070725 CA_AAMCK_DIV = 4
4917 00:45:43.073930 CA_ADMCK_DIV = 4
4918 00:45:43.077205 DQ_TRACK_CA_EN = 0
4919 00:45:43.080915 CA_PICK = 933
4920 00:45:43.081002 CA_MCKIO = 933
4921 00:45:43.083902 MCKIO_SEMI = 0
4922 00:45:43.087227 PLL_FREQ = 3732
4923 00:45:43.090601 DQ_UI_PI_RATIO = 32
4924 00:45:43.093917 CA_UI_PI_RATIO = 0
4925 00:45:43.097295 ===================================
4926 00:45:43.100404 ===================================
4927 00:45:43.103802 memory_type:LPDDR4
4928 00:45:43.103886 GP_NUM : 10
4929 00:45:43.107123 SRAM_EN : 1
4930 00:45:43.107183 MD32_EN : 0
4931 00:45:43.110495 ===================================
4932 00:45:43.113729 [ANA_INIT] >>>>>>>>>>>>>>
4933 00:45:43.117699 <<<<<< [CONFIGURE PHASE]: ANA_TX
4934 00:45:43.120882 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4935 00:45:43.123595 ===================================
4936 00:45:43.126983 data_rate = 1866,PCW = 0X8f00
4937 00:45:43.130302 ===================================
4938 00:45:43.133513 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4939 00:45:43.140762 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4940 00:45:43.143742 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4941 00:45:43.150341 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4942 00:45:43.153674 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4943 00:45:43.157062 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4944 00:45:43.157180 [ANA_INIT] flow start
4945 00:45:43.160317 [ANA_INIT] PLL >>>>>>>>
4946 00:45:43.163638 [ANA_INIT] PLL <<<<<<<<
4947 00:45:43.163731 [ANA_INIT] MIDPI >>>>>>>>
4948 00:45:43.166837 [ANA_INIT] MIDPI <<<<<<<<
4949 00:45:43.170510 [ANA_INIT] DLL >>>>>>>>
4950 00:45:43.170599 [ANA_INIT] flow end
4951 00:45:43.177062 ============ LP4 DIFF to SE enter ============
4952 00:45:43.180084 ============ LP4 DIFF to SE exit ============
4953 00:45:43.180180 [ANA_INIT] <<<<<<<<<<<<<
4954 00:45:43.183614 [Flow] Enable top DCM control >>>>>
4955 00:45:43.186663 [Flow] Enable top DCM control <<<<<
4956 00:45:43.190500 Enable DLL master slave shuffle
4957 00:45:43.197448 ==============================================================
4958 00:45:43.200104 Gating Mode config
4959 00:45:43.203903 ==============================================================
4960 00:45:43.206931 Config description:
4961 00:45:43.216977 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4962 00:45:43.223632 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4963 00:45:43.226607 SELPH_MODE 0: By rank 1: By Phase
4964 00:45:43.233402 ==============================================================
4965 00:45:43.237177 GAT_TRACK_EN = 1
4966 00:45:43.240385 RX_GATING_MODE = 2
4967 00:45:43.240485 RX_GATING_TRACK_MODE = 2
4968 00:45:43.243644 SELPH_MODE = 1
4969 00:45:43.246963 PICG_EARLY_EN = 1
4970 00:45:43.250253 VALID_LAT_VALUE = 1
4971 00:45:43.256626 ==============================================================
4972 00:45:43.260023 Enter into Gating configuration >>>>
4973 00:45:43.263329 Exit from Gating configuration <<<<
4974 00:45:43.266650 Enter into DVFS_PRE_config >>>>>
4975 00:45:43.276640 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4976 00:45:43.279995 Exit from DVFS_PRE_config <<<<<
4977 00:45:43.283274 Enter into PICG configuration >>>>
4978 00:45:43.286435 Exit from PICG configuration <<<<
4979 00:45:43.290015 [RX_INPUT] configuration >>>>>
4980 00:45:43.293023 [RX_INPUT] configuration <<<<<
4981 00:45:43.296968 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4982 00:45:43.303472 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4983 00:45:43.310232 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4984 00:45:43.316443 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4985 00:45:43.320653 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4986 00:45:43.326596 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4987 00:45:43.329806 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4988 00:45:43.336569 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4989 00:45:43.339955 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4990 00:45:43.343167 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4991 00:45:43.346347 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4992 00:45:43.352935 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4993 00:45:43.356914 ===================================
4994 00:45:43.356990 LPDDR4 DRAM CONFIGURATION
4995 00:45:43.360069 ===================================
4996 00:45:43.363363 EX_ROW_EN[0] = 0x0
4997 00:45:43.366670 EX_ROW_EN[1] = 0x0
4998 00:45:43.366747 LP4Y_EN = 0x0
4999 00:45:43.370114 WORK_FSP = 0x0
5000 00:45:43.370190 WL = 0x3
5001 00:45:43.373359 RL = 0x3
5002 00:45:43.373433 BL = 0x2
5003 00:45:43.376638 RPST = 0x0
5004 00:45:43.376712 RD_PRE = 0x0
5005 00:45:43.379913 WR_PRE = 0x1
5006 00:45:43.379989 WR_PST = 0x0
5007 00:45:43.383238 DBI_WR = 0x0
5008 00:45:43.383313 DBI_RD = 0x0
5009 00:45:43.386521 OTF = 0x1
5010 00:45:43.389926 ===================================
5011 00:45:43.393346 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5012 00:45:43.396507 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5013 00:45:43.403195 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5014 00:45:43.406402 ===================================
5015 00:45:43.406479 LPDDR4 DRAM CONFIGURATION
5016 00:45:43.409683 ===================================
5017 00:45:43.412924 EX_ROW_EN[0] = 0x10
5018 00:45:43.416239 EX_ROW_EN[1] = 0x0
5019 00:45:43.416331 LP4Y_EN = 0x0
5020 00:45:43.419606 WORK_FSP = 0x0
5021 00:45:43.419696 WL = 0x3
5022 00:45:43.422980 RL = 0x3
5023 00:45:43.423044 BL = 0x2
5024 00:45:43.426377 RPST = 0x0
5025 00:45:43.426443 RD_PRE = 0x0
5026 00:45:43.429524 WR_PRE = 0x1
5027 00:45:43.429648 WR_PST = 0x0
5028 00:45:43.432838 DBI_WR = 0x0
5029 00:45:43.432940 DBI_RD = 0x0
5030 00:45:43.436407 OTF = 0x1
5031 00:45:43.439561 ===================================
5032 00:45:43.446179 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5033 00:45:43.449433 nWR fixed to 30
5034 00:45:43.449524 [ModeRegInit_LP4] CH0 RK0
5035 00:45:43.452843 [ModeRegInit_LP4] CH0 RK1
5036 00:45:43.455891 [ModeRegInit_LP4] CH1 RK0
5037 00:45:43.459361 [ModeRegInit_LP4] CH1 RK1
5038 00:45:43.459448 match AC timing 9
5039 00:45:43.462538 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5040 00:45:43.466027 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5041 00:45:43.472631 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5042 00:45:43.475939 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5043 00:45:43.482623 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5044 00:45:43.482702 ==
5045 00:45:43.485918 Dram Type= 6, Freq= 0, CH_0, rank 0
5046 00:45:43.489733 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5047 00:45:43.489837 ==
5048 00:45:43.496323 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5049 00:45:43.502926 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5050 00:45:43.506169 [CA 0] Center 37 (6~68) winsize 63
5051 00:45:43.509080 [CA 1] Center 37 (7~68) winsize 62
5052 00:45:43.512607 [CA 2] Center 34 (4~65) winsize 62
5053 00:45:43.516365 [CA 3] Center 34 (3~65) winsize 63
5054 00:45:43.519789 [CA 4] Center 33 (3~64) winsize 62
5055 00:45:43.519882 [CA 5] Center 32 (2~62) winsize 61
5056 00:45:43.519969
5057 00:45:43.525866 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5058 00:45:43.525949
5059 00:45:43.529299 [CATrainingPosCal] consider 1 rank data
5060 00:45:43.532597 u2DelayCellTimex100 = 270/100 ps
5061 00:45:43.535913 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5062 00:45:43.539127 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5063 00:45:43.542540 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5064 00:45:43.545980 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5065 00:45:43.549213 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5066 00:45:43.552654 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5067 00:45:43.552734
5068 00:45:43.555997 CA PerBit enable=1, Macro0, CA PI delay=32
5069 00:45:43.556074
5070 00:45:43.559286 [CBTSetCACLKResult] CA Dly = 32
5071 00:45:43.562360 CS Dly: 5 (0~36)
5072 00:45:43.562481 ==
5073 00:45:43.565981 Dram Type= 6, Freq= 0, CH_0, rank 1
5074 00:45:43.568982 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5075 00:45:43.569097 ==
5076 00:45:43.576336 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5077 00:45:43.582898 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5078 00:45:43.585642 [CA 0] Center 37 (6~68) winsize 63
5079 00:45:43.588912 [CA 1] Center 37 (7~68) winsize 62
5080 00:45:43.592392 [CA 2] Center 34 (4~65) winsize 62
5081 00:45:43.595746 [CA 3] Center 34 (3~65) winsize 63
5082 00:45:43.599208 [CA 4] Center 33 (3~63) winsize 61
5083 00:45:43.599292 [CA 5] Center 32 (2~62) winsize 61
5084 00:45:43.602737
5085 00:45:43.605967 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5086 00:45:43.606037
5087 00:45:43.609394 [CATrainingPosCal] consider 2 rank data
5088 00:45:43.612674 u2DelayCellTimex100 = 270/100 ps
5089 00:45:43.615947 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5090 00:45:43.619007 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5091 00:45:43.622682 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5092 00:45:43.625486 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5093 00:45:43.629031 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5094 00:45:43.632291 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5095 00:45:43.632393
5096 00:45:43.639010 CA PerBit enable=1, Macro0, CA PI delay=32
5097 00:45:43.639116
5098 00:45:43.639212 [CBTSetCACLKResult] CA Dly = 32
5099 00:45:43.642238 CS Dly: 5 (0~37)
5100 00:45:43.642328
5101 00:45:43.645613 ----->DramcWriteLeveling(PI) begin...
5102 00:45:43.645700 ==
5103 00:45:43.649013 Dram Type= 6, Freq= 0, CH_0, rank 0
5104 00:45:43.652445 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5105 00:45:43.652524 ==
5106 00:45:43.655698 Write leveling (Byte 0): 34 => 34
5107 00:45:43.659093 Write leveling (Byte 1): 32 => 32
5108 00:45:43.662505 DramcWriteLeveling(PI) end<-----
5109 00:45:43.662610
5110 00:45:43.662720 ==
5111 00:45:43.665724 Dram Type= 6, Freq= 0, CH_0, rank 0
5112 00:45:43.668966 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5113 00:45:43.672410 ==
5114 00:45:43.672483 [Gating] SW mode calibration
5115 00:45:43.681851 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5116 00:45:43.685217 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5117 00:45:43.688687 0 14 0 | B1->B0 | 2a2a 3434 | 1 1 | (1 1) (1 1)
5118 00:45:43.695251 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5119 00:45:43.698571 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5120 00:45:43.701648 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5121 00:45:43.708831 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5122 00:45:43.711632 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5123 00:45:43.715278 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 1)
5124 00:45:43.721943 0 14 28 | B1->B0 | 3434 2424 | 1 0 | (1 1) (1 0)
5125 00:45:43.725226 0 15 0 | B1->B0 | 2d2d 2323 | 1 0 | (1 0) (0 0)
5126 00:45:43.728665 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5127 00:45:43.735160 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5128 00:45:43.738411 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5129 00:45:43.741793 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5130 00:45:43.748329 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5131 00:45:43.751910 0 15 24 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
5132 00:45:43.755272 0 15 28 | B1->B0 | 2626 3a3a | 0 1 | (0 0) (0 0)
5133 00:45:43.761821 1 0 0 | B1->B0 | 3535 4646 | 0 0 | (0 0) (0 0)
5134 00:45:43.765270 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5135 00:45:43.768729 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5136 00:45:43.775260 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5137 00:45:43.778642 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5138 00:45:43.781364 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5139 00:45:43.788036 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5140 00:45:43.791294 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5141 00:45:43.794602 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5142 00:45:43.801293 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5143 00:45:43.804669 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5144 00:45:43.807967 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5145 00:45:43.814579 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5146 00:45:43.817947 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5147 00:45:43.821269 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5148 00:45:43.824428 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5149 00:45:43.831331 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5150 00:45:43.834596 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5151 00:45:43.837934 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5152 00:45:43.844566 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5153 00:45:43.848153 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5154 00:45:43.851105 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5155 00:45:43.857936 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5156 00:45:43.861145 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5157 00:45:43.864444 Total UI for P1: 0, mck2ui 16
5158 00:45:43.867634 best dqsien dly found for B0: ( 1, 2, 26)
5159 00:45:43.871047 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5160 00:45:43.874662 Total UI for P1: 0, mck2ui 16
5161 00:45:43.878038 best dqsien dly found for B1: ( 1, 2, 28)
5162 00:45:43.881153 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5163 00:45:43.884327 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5164 00:45:43.884404
5165 00:45:43.891438 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5166 00:45:43.894762 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5167 00:45:43.898049 [Gating] SW calibration Done
5168 00:45:43.898126 ==
5169 00:45:43.901338 Dram Type= 6, Freq= 0, CH_0, rank 0
5170 00:45:43.904655 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5171 00:45:43.904734 ==
5172 00:45:43.904794 RX Vref Scan: 0
5173 00:45:43.904871
5174 00:45:43.908048 RX Vref 0 -> 0, step: 1
5175 00:45:43.908125
5176 00:45:43.910832 RX Delay -80 -> 252, step: 8
5177 00:45:43.914011 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5178 00:45:43.917324 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5179 00:45:43.924054 iDelay=208, Bit 2, Center 103 (16 ~ 191) 176
5180 00:45:43.927321 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5181 00:45:43.931175 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5182 00:45:43.934516 iDelay=208, Bit 5, Center 91 (0 ~ 183) 184
5183 00:45:43.937289 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5184 00:45:43.940627 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5185 00:45:43.947647 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5186 00:45:43.950389 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5187 00:45:43.953752 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5188 00:45:43.957598 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5189 00:45:43.960893 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5190 00:45:43.964003 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5191 00:45:43.970487 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5192 00:45:43.973909 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5193 00:45:43.974033 ==
5194 00:45:43.977216 Dram Type= 6, Freq= 0, CH_0, rank 0
5195 00:45:43.980393 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5196 00:45:43.980469 ==
5197 00:45:43.983964 DQS Delay:
5198 00:45:43.984054 DQS0 = 0, DQS1 = 0
5199 00:45:43.984143 DQM Delay:
5200 00:45:43.987432 DQM0 = 105, DQM1 = 94
5201 00:45:43.987523 DQ Delay:
5202 00:45:43.990440 DQ0 =107, DQ1 =107, DQ2 =103, DQ3 =99
5203 00:45:43.994145 DQ4 =107, DQ5 =91, DQ6 =115, DQ7 =115
5204 00:45:43.997391 DQ8 =83, DQ9 =87, DQ10 =95, DQ11 =91
5205 00:45:44.000814 DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =99
5206 00:45:44.000905
5207 00:45:44.000977
5208 00:45:44.001060 ==
5209 00:45:44.003679 Dram Type= 6, Freq= 0, CH_0, rank 0
5210 00:45:44.010309 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5211 00:45:44.010386 ==
5212 00:45:44.010446
5213 00:45:44.010500
5214 00:45:44.010552 TX Vref Scan disable
5215 00:45:44.013997 == TX Byte 0 ==
5216 00:45:44.017665 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5217 00:45:44.024410 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5218 00:45:44.024486 == TX Byte 1 ==
5219 00:45:44.027641 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5220 00:45:44.034347 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5221 00:45:44.034417 ==
5222 00:45:44.037559 Dram Type= 6, Freq= 0, CH_0, rank 0
5223 00:45:44.041110 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5224 00:45:44.041216 ==
5225 00:45:44.041301
5226 00:45:44.041369
5227 00:45:44.044413 TX Vref Scan disable
5228 00:45:44.044501 == TX Byte 0 ==
5229 00:45:44.051042 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5230 00:45:44.054245 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5231 00:45:44.054338 == TX Byte 1 ==
5232 00:45:44.060857 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5233 00:45:44.064143 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5234 00:45:44.064234
5235 00:45:44.064316 [DATLAT]
5236 00:45:44.067348 Freq=933, CH0 RK0
5237 00:45:44.067435
5238 00:45:44.067515 DATLAT Default: 0xd
5239 00:45:44.071111 0, 0xFFFF, sum = 0
5240 00:45:44.071177 1, 0xFFFF, sum = 0
5241 00:45:44.074143 2, 0xFFFF, sum = 0
5242 00:45:44.074211 3, 0xFFFF, sum = 0
5243 00:45:44.077631 4, 0xFFFF, sum = 0
5244 00:45:44.077708 5, 0xFFFF, sum = 0
5245 00:45:44.081002 6, 0xFFFF, sum = 0
5246 00:45:44.081079 7, 0xFFFF, sum = 0
5247 00:45:44.084402 8, 0xFFFF, sum = 0
5248 00:45:44.087780 9, 0xFFFF, sum = 0
5249 00:45:44.087856 10, 0x0, sum = 1
5250 00:45:44.087916 11, 0x0, sum = 2
5251 00:45:44.090814 12, 0x0, sum = 3
5252 00:45:44.090890 13, 0x0, sum = 4
5253 00:45:44.094086 best_step = 11
5254 00:45:44.094161
5255 00:45:44.094219 ==
5256 00:45:44.097925 Dram Type= 6, Freq= 0, CH_0, rank 0
5257 00:45:44.100944 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5258 00:45:44.101035 ==
5259 00:45:44.104309 RX Vref Scan: 1
5260 00:45:44.104384
5261 00:45:44.104442 RX Vref 0 -> 0, step: 1
5262 00:45:44.104498
5263 00:45:44.107673 RX Delay -53 -> 252, step: 4
5264 00:45:44.107761
5265 00:45:44.111163 Set Vref, RX VrefLevel [Byte0]: 57
5266 00:45:44.114310 [Byte1]: 49
5267 00:45:44.118032
5268 00:45:44.118121 Final RX Vref Byte 0 = 57 to rank0
5269 00:45:44.121521 Final RX Vref Byte 1 = 49 to rank0
5270 00:45:44.125255 Final RX Vref Byte 0 = 57 to rank1
5271 00:45:44.128242 Final RX Vref Byte 1 = 49 to rank1==
5272 00:45:44.131585 Dram Type= 6, Freq= 0, CH_0, rank 0
5273 00:45:44.138235 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5274 00:45:44.138327 ==
5275 00:45:44.138409 DQS Delay:
5276 00:45:44.138486 DQS0 = 0, DQS1 = 0
5277 00:45:44.141671 DQM Delay:
5278 00:45:44.141761 DQM0 = 105, DQM1 = 95
5279 00:45:44.145112 DQ Delay:
5280 00:45:44.148457 DQ0 =104, DQ1 =106, DQ2 =104, DQ3 =102
5281 00:45:44.151916 DQ4 =106, DQ5 =96, DQ6 =112, DQ7 =110
5282 00:45:44.154911 DQ8 =82, DQ9 =84, DQ10 =98, DQ11 =90
5283 00:45:44.158265 DQ12 =102, DQ13 =100, DQ14 =104, DQ15 =104
5284 00:45:44.158342
5285 00:45:44.158400
5286 00:45:44.164914 [DQSOSCAuto] RK0, (LSB)MR18= 0x352c, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 405 ps
5287 00:45:44.168250 CH0 RK0: MR19=505, MR18=352C
5288 00:45:44.174732 CH0_RK0: MR19=0x505, MR18=0x352C, DQSOSC=405, MR23=63, INC=66, DEC=44
5289 00:45:44.174808
5290 00:45:44.177991 ----->DramcWriteLeveling(PI) begin...
5291 00:45:44.178083 ==
5292 00:45:44.181603 Dram Type= 6, Freq= 0, CH_0, rank 1
5293 00:45:44.184710 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5294 00:45:44.184808 ==
5295 00:45:44.188084 Write leveling (Byte 0): 33 => 33
5296 00:45:44.191485 Write leveling (Byte 1): 29 => 29
5297 00:45:44.194852 DramcWriteLeveling(PI) end<-----
5298 00:45:44.194961
5299 00:45:44.195076 ==
5300 00:45:44.198043 Dram Type= 6, Freq= 0, CH_0, rank 1
5301 00:45:44.204910 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5302 00:45:44.204987 ==
5303 00:45:44.205045 [Gating] SW mode calibration
5304 00:45:44.214556 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5305 00:45:44.217929 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5306 00:45:44.221148 0 14 0 | B1->B0 | 3333 3131 | 0 1 | (0 0) (1 1)
5307 00:45:44.228115 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5308 00:45:44.231470 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5309 00:45:44.234925 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5310 00:45:44.240958 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5311 00:45:44.244405 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5312 00:45:44.247575 0 14 24 | B1->B0 | 3434 3333 | 0 1 | (0 0) (1 1)
5313 00:45:44.254298 0 14 28 | B1->B0 | 2c2c 2c2c | 0 0 | (0 1) (0 1)
5314 00:45:44.257614 0 15 0 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
5315 00:45:44.261225 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5316 00:45:44.267755 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5317 00:45:44.271020 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5318 00:45:44.274522 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5319 00:45:44.281102 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5320 00:45:44.284396 0 15 24 | B1->B0 | 2626 2525 | 0 0 | (0 0) (0 0)
5321 00:45:44.287637 0 15 28 | B1->B0 | 4040 3837 | 0 1 | (0 0) (0 0)
5322 00:45:44.294387 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5323 00:45:44.297734 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5324 00:45:44.301140 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5325 00:45:44.307725 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5326 00:45:44.311081 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5327 00:45:44.314147 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5328 00:45:44.321133 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5329 00:45:44.324581 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5330 00:45:44.327778 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5331 00:45:44.330910 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5332 00:45:44.337677 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5333 00:45:44.340977 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5334 00:45:44.344437 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5335 00:45:44.350851 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5336 00:45:44.354176 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5337 00:45:44.357621 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5338 00:45:44.364129 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5339 00:45:44.367441 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5340 00:45:44.370840 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5341 00:45:44.377361 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5342 00:45:44.380569 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5343 00:45:44.384185 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5344 00:45:44.390349 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5345 00:45:44.393806 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5346 00:45:44.397246 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5347 00:45:44.400143 Total UI for P1: 0, mck2ui 16
5348 00:45:44.403919 best dqsien dly found for B1: ( 1, 2, 30)
5349 00:45:44.410526 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5350 00:45:44.410619 Total UI for P1: 0, mck2ui 16
5351 00:45:44.416899 best dqsien dly found for B0: ( 1, 2, 30)
5352 00:45:44.420014 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5353 00:45:44.423569 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5354 00:45:44.423664
5355 00:45:44.427276 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5356 00:45:44.430387 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5357 00:45:44.433676 [Gating] SW calibration Done
5358 00:45:44.433743 ==
5359 00:45:44.436742 Dram Type= 6, Freq= 0, CH_0, rank 1
5360 00:45:44.440035 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5361 00:45:44.440125 ==
5362 00:45:44.443332 RX Vref Scan: 0
5363 00:45:44.443400
5364 00:45:44.443454 RX Vref 0 -> 0, step: 1
5365 00:45:44.443506
5366 00:45:44.446714 RX Delay -80 -> 252, step: 8
5367 00:45:44.450014 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5368 00:45:44.457282 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5369 00:45:44.460647 iDelay=208, Bit 2, Center 103 (8 ~ 199) 192
5370 00:45:44.463321 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5371 00:45:44.467179 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5372 00:45:44.470468 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5373 00:45:44.477227 iDelay=208, Bit 6, Center 107 (16 ~ 199) 184
5374 00:45:44.480377 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5375 00:45:44.483663 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5376 00:45:44.487082 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5377 00:45:44.489784 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5378 00:45:44.493194 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5379 00:45:44.499877 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5380 00:45:44.503320 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5381 00:45:44.506675 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5382 00:45:44.510650 iDelay=208, Bit 15, Center 103 (16 ~ 191) 176
5383 00:45:44.510726 ==
5384 00:45:44.513627 Dram Type= 6, Freq= 0, CH_0, rank 1
5385 00:45:44.516562 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5386 00:45:44.520278 ==
5387 00:45:44.520353 DQS Delay:
5388 00:45:44.520412 DQS0 = 0, DQS1 = 0
5389 00:45:44.523082 DQM Delay:
5390 00:45:44.523157 DQM0 = 104, DQM1 = 94
5391 00:45:44.526514 DQ Delay:
5392 00:45:44.529853 DQ0 =103, DQ1 =107, DQ2 =103, DQ3 =99
5393 00:45:44.533244 DQ4 =107, DQ5 =95, DQ6 =107, DQ7 =115
5394 00:45:44.536499 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =87
5395 00:45:44.539925 DQ12 =99, DQ13 =99, DQ14 =103, DQ15 =103
5396 00:45:44.540000
5397 00:45:44.540059
5398 00:45:44.540112 ==
5399 00:45:44.543271 Dram Type= 6, Freq= 0, CH_0, rank 1
5400 00:45:44.546689 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5401 00:45:44.546766 ==
5402 00:45:44.546835
5403 00:45:44.546894
5404 00:45:44.549910 TX Vref Scan disable
5405 00:45:44.549987 == TX Byte 0 ==
5406 00:45:44.556768 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5407 00:45:44.559764 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5408 00:45:44.559856 == TX Byte 1 ==
5409 00:45:44.566665 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5410 00:45:44.570329 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5411 00:45:44.570421 ==
5412 00:45:44.573693 Dram Type= 6, Freq= 0, CH_0, rank 1
5413 00:45:44.576953 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5414 00:45:44.577029 ==
5415 00:45:44.577089
5416 00:45:44.580335
5417 00:45:44.580410 TX Vref Scan disable
5418 00:45:44.583580 == TX Byte 0 ==
5419 00:45:44.586720 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5420 00:45:44.590121 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5421 00:45:44.593399 == TX Byte 1 ==
5422 00:45:44.596708 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5423 00:45:44.599966 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5424 00:45:44.603256
5425 00:45:44.603331 [DATLAT]
5426 00:45:44.603390 Freq=933, CH0 RK1
5427 00:45:44.603445
5428 00:45:44.606613 DATLAT Default: 0xb
5429 00:45:44.606688 0, 0xFFFF, sum = 0
5430 00:45:44.609985 1, 0xFFFF, sum = 0
5431 00:45:44.610060 2, 0xFFFF, sum = 0
5432 00:45:44.613356 3, 0xFFFF, sum = 0
5433 00:45:44.613489 4, 0xFFFF, sum = 0
5434 00:45:44.616780 5, 0xFFFF, sum = 0
5435 00:45:44.616856 6, 0xFFFF, sum = 0
5436 00:45:44.619911 7, 0xFFFF, sum = 0
5437 00:45:44.623257 8, 0xFFFF, sum = 0
5438 00:45:44.623333 9, 0xFFFF, sum = 0
5439 00:45:44.626630 10, 0x0, sum = 1
5440 00:45:44.626706 11, 0x0, sum = 2
5441 00:45:44.626766 12, 0x0, sum = 3
5442 00:45:44.629940 13, 0x0, sum = 4
5443 00:45:44.630016 best_step = 11
5444 00:45:44.630074
5445 00:45:44.630128 ==
5446 00:45:44.633237 Dram Type= 6, Freq= 0, CH_0, rank 1
5447 00:45:44.640009 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5448 00:45:44.640084 ==
5449 00:45:44.640143 RX Vref Scan: 0
5450 00:45:44.640197
5451 00:45:44.643446 RX Vref 0 -> 0, step: 1
5452 00:45:44.643521
5453 00:45:44.646805 RX Delay -53 -> 252, step: 4
5454 00:45:44.649951 iDelay=199, Bit 0, Center 102 (11 ~ 194) 184
5455 00:45:44.656160 iDelay=199, Bit 1, Center 106 (23 ~ 190) 168
5456 00:45:44.659789 iDelay=199, Bit 2, Center 102 (15 ~ 190) 176
5457 00:45:44.663359 iDelay=199, Bit 3, Center 102 (15 ~ 190) 176
5458 00:45:44.666443 iDelay=199, Bit 4, Center 106 (19 ~ 194) 176
5459 00:45:44.670162 iDelay=199, Bit 5, Center 98 (11 ~ 186) 176
5460 00:45:44.676241 iDelay=199, Bit 6, Center 110 (27 ~ 194) 168
5461 00:45:44.679610 iDelay=199, Bit 7, Center 110 (23 ~ 198) 176
5462 00:45:44.683128 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5463 00:45:44.686510 iDelay=199, Bit 9, Center 82 (-1 ~ 166) 168
5464 00:45:44.689764 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5465 00:45:44.692961 iDelay=199, Bit 11, Center 88 (7 ~ 170) 164
5466 00:45:44.699576 iDelay=199, Bit 12, Center 100 (19 ~ 182) 164
5467 00:45:44.703533 iDelay=199, Bit 13, Center 98 (15 ~ 182) 168
5468 00:45:44.706345 iDelay=199, Bit 14, Center 104 (23 ~ 186) 164
5469 00:45:44.709658 iDelay=199, Bit 15, Center 102 (19 ~ 186) 168
5470 00:45:44.709751 ==
5471 00:45:44.713077 Dram Type= 6, Freq= 0, CH_0, rank 1
5472 00:45:44.719792 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5473 00:45:44.719869 ==
5474 00:45:44.719944 DQS Delay:
5475 00:45:44.720013 DQS0 = 0, DQS1 = 0
5476 00:45:44.723243 DQM Delay:
5477 00:45:44.723319 DQM0 = 104, DQM1 = 94
5478 00:45:44.726415 DQ Delay:
5479 00:45:44.729746 DQ0 =102, DQ1 =106, DQ2 =102, DQ3 =102
5480 00:45:44.733132 DQ4 =106, DQ5 =98, DQ6 =110, DQ7 =110
5481 00:45:44.736561 DQ8 =84, DQ9 =82, DQ10 =94, DQ11 =88
5482 00:45:44.739240 DQ12 =100, DQ13 =98, DQ14 =104, DQ15 =102
5483 00:45:44.739330
5484 00:45:44.739404
5485 00:45:44.746041 [DQSOSCAuto] RK1, (LSB)MR18= 0x2a03, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 408 ps
5486 00:45:44.749357 CH0 RK1: MR19=505, MR18=2A03
5487 00:45:44.756476 CH0_RK1: MR19=0x505, MR18=0x2A03, DQSOSC=408, MR23=63, INC=65, DEC=43
5488 00:45:44.759746 [RxdqsGatingPostProcess] freq 933
5489 00:45:44.766045 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5490 00:45:44.766121 best DQS0 dly(2T, 0.5T) = (0, 10)
5491 00:45:44.769749 best DQS1 dly(2T, 0.5T) = (0, 10)
5492 00:45:44.772872 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5493 00:45:44.776281 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5494 00:45:44.779686 best DQS0 dly(2T, 0.5T) = (0, 10)
5495 00:45:44.782928 best DQS1 dly(2T, 0.5T) = (0, 10)
5496 00:45:44.786264 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5497 00:45:44.789107 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5498 00:45:44.793020 Pre-setting of DQS Precalculation
5499 00:45:44.799572 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5500 00:45:44.799647 ==
5501 00:45:44.802942 Dram Type= 6, Freq= 0, CH_1, rank 0
5502 00:45:44.806166 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5503 00:45:44.806272 ==
5504 00:45:44.812544 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5505 00:45:44.816194 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5506 00:45:44.819741 [CA 0] Center 36 (6~67) winsize 62
5507 00:45:44.823716 [CA 1] Center 36 (6~67) winsize 62
5508 00:45:44.826749 [CA 2] Center 35 (5~65) winsize 61
5509 00:45:44.829999 [CA 3] Center 34 (4~65) winsize 62
5510 00:45:44.833145 [CA 4] Center 34 (4~64) winsize 61
5511 00:45:44.836835 [CA 5] Center 33 (3~64) winsize 62
5512 00:45:44.836910
5513 00:45:44.839871 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5514 00:45:44.839947
5515 00:45:44.843385 [CATrainingPosCal] consider 1 rank data
5516 00:45:44.846689 u2DelayCellTimex100 = 270/100 ps
5517 00:45:44.849965 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5518 00:45:44.853395 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5519 00:45:44.859988 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5520 00:45:44.863332 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5521 00:45:44.866647 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5522 00:45:44.869891 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5523 00:45:44.869966
5524 00:45:44.873131 CA PerBit enable=1, Macro0, CA PI delay=33
5525 00:45:44.873207
5526 00:45:44.876352 [CBTSetCACLKResult] CA Dly = 33
5527 00:45:44.876427 CS Dly: 6 (0~37)
5528 00:45:44.876502 ==
5529 00:45:44.880316 Dram Type= 6, Freq= 0, CH_1, rank 1
5530 00:45:44.886271 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5531 00:45:44.886348 ==
5532 00:45:44.889712 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5533 00:45:44.896357 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5534 00:45:44.900256 [CA 0] Center 36 (6~67) winsize 62
5535 00:45:44.903521 [CA 1] Center 37 (7~68) winsize 62
5536 00:45:44.906199 [CA 2] Center 35 (5~65) winsize 61
5537 00:45:44.910120 [CA 3] Center 34 (4~65) winsize 62
5538 00:45:44.913444 [CA 4] Center 34 (4~65) winsize 62
5539 00:45:44.916665 [CA 5] Center 33 (3~64) winsize 62
5540 00:45:44.916733
5541 00:45:44.919984 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5542 00:45:44.920076
5543 00:45:44.923360 [CATrainingPosCal] consider 2 rank data
5544 00:45:44.926691 u2DelayCellTimex100 = 270/100 ps
5545 00:45:44.930102 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5546 00:45:44.932871 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5547 00:45:44.939931 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5548 00:45:44.942864 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5549 00:45:44.946675 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5550 00:45:44.949539 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5551 00:45:44.949672
5552 00:45:44.952868 CA PerBit enable=1, Macro0, CA PI delay=33
5553 00:45:44.952958
5554 00:45:44.956070 [CBTSetCACLKResult] CA Dly = 33
5555 00:45:44.956160 CS Dly: 7 (0~40)
5556 00:45:44.956243
5557 00:45:44.963445 ----->DramcWriteLeveling(PI) begin...
5558 00:45:44.963538 ==
5559 00:45:44.966339 Dram Type= 6, Freq= 0, CH_1, rank 0
5560 00:45:44.969899 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5561 00:45:44.969969 ==
5562 00:45:44.972831 Write leveling (Byte 0): 24 => 24
5563 00:45:44.976176 Write leveling (Byte 1): 26 => 26
5564 00:45:44.979487 DramcWriteLeveling(PI) end<-----
5565 00:45:44.979578
5566 00:45:44.979661 ==
5567 00:45:44.982912 Dram Type= 6, Freq= 0, CH_1, rank 0
5568 00:45:44.986108 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5569 00:45:44.986173 ==
5570 00:45:44.989237 [Gating] SW mode calibration
5571 00:45:44.996240 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5572 00:45:45.002909 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5573 00:45:45.006225 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5574 00:45:45.009495 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5575 00:45:45.016010 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5576 00:45:45.019367 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5577 00:45:45.022713 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5578 00:45:45.029486 0 14 20 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5579 00:45:45.032719 0 14 24 | B1->B0 | 3434 2f2f | 0 1 | (0 0) (1 1)
5580 00:45:45.036034 0 14 28 | B1->B0 | 2c2c 2323 | 0 0 | (1 0) (1 0)
5581 00:45:45.042833 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5582 00:45:45.046211 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5583 00:45:45.049517 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5584 00:45:45.052765 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5585 00:45:45.059303 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5586 00:45:45.062548 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5587 00:45:45.065919 0 15 24 | B1->B0 | 2525 3333 | 0 0 | (0 0) (0 0)
5588 00:45:45.072523 0 15 28 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
5589 00:45:45.075889 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5590 00:45:45.079033 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5591 00:45:45.085896 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5592 00:45:45.089079 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5593 00:45:45.092308 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5594 00:45:45.099068 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5595 00:45:45.102414 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5596 00:45:45.105863 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5597 00:45:45.112290 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5598 00:45:45.115550 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5599 00:45:45.119237 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5600 00:45:45.126144 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5601 00:45:45.128931 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5602 00:45:45.132487 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5603 00:45:45.139263 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5604 00:45:45.142594 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5605 00:45:45.145958 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5606 00:45:45.152009 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5607 00:45:45.155270 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5608 00:45:45.158694 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5609 00:45:45.165365 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5610 00:45:45.169136 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5611 00:45:45.172314 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5612 00:45:45.175768 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5613 00:45:45.179067 Total UI for P1: 0, mck2ui 16
5614 00:45:45.182117 best dqsien dly found for B0: ( 1, 2, 24)
5615 00:45:45.185297 Total UI for P1: 0, mck2ui 16
5616 00:45:45.189201 best dqsien dly found for B1: ( 1, 2, 26)
5617 00:45:45.191901 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5618 00:45:45.198539 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5619 00:45:45.198657
5620 00:45:45.202507 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5621 00:45:45.205217 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5622 00:45:45.208570 [Gating] SW calibration Done
5623 00:45:45.208659 ==
5624 00:45:45.211967 Dram Type= 6, Freq= 0, CH_1, rank 0
5625 00:45:45.215361 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5626 00:45:45.215458 ==
5627 00:45:45.218733 RX Vref Scan: 0
5628 00:45:45.218841
5629 00:45:45.219057 RX Vref 0 -> 0, step: 1
5630 00:45:45.219163
5631 00:45:45.221892 RX Delay -80 -> 252, step: 8
5632 00:45:45.225152 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5633 00:45:45.228558 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5634 00:45:45.235130 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5635 00:45:45.238366 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5636 00:45:45.241844 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5637 00:45:45.245111 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5638 00:45:45.248251 iDelay=208, Bit 6, Center 107 (16 ~ 199) 184
5639 00:45:45.251690 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5640 00:45:45.258371 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5641 00:45:45.261820 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5642 00:45:45.264899 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5643 00:45:45.268689 iDelay=208, Bit 11, Center 95 (8 ~ 183) 176
5644 00:45:45.271613 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5645 00:45:45.274994 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5646 00:45:45.281507 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5647 00:45:45.285293 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5648 00:45:45.285382 ==
5649 00:45:45.288248 Dram Type= 6, Freq= 0, CH_1, rank 0
5650 00:45:45.291789 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5651 00:45:45.291878 ==
5652 00:45:45.295246 DQS Delay:
5653 00:45:45.295335 DQS0 = 0, DQS1 = 0
5654 00:45:45.295418 DQM Delay:
5655 00:45:45.298419 DQM0 = 101, DQM1 = 98
5656 00:45:45.298505 DQ Delay:
5657 00:45:45.301437 DQ0 =103, DQ1 =95, DQ2 =91, DQ3 =99
5658 00:45:45.304517 DQ4 =99, DQ5 =111, DQ6 =107, DQ7 =103
5659 00:45:45.307902 DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =95
5660 00:45:45.311394 DQ12 =107, DQ13 =103, DQ14 =99, DQ15 =107
5661 00:45:45.311458
5662 00:45:45.314634
5663 00:45:45.314710 ==
5664 00:45:45.318050 Dram Type= 6, Freq= 0, CH_1, rank 0
5665 00:45:45.321397 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5666 00:45:45.321485 ==
5667 00:45:45.321587
5668 00:45:45.321656
5669 00:45:45.324719 TX Vref Scan disable
5670 00:45:45.324806 == TX Byte 0 ==
5671 00:45:45.331355 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5672 00:45:45.334678 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5673 00:45:45.334756 == TX Byte 1 ==
5674 00:45:45.341347 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5675 00:45:45.344624 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5676 00:45:45.344714 ==
5677 00:45:45.348065 Dram Type= 6, Freq= 0, CH_1, rank 0
5678 00:45:45.351491 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5679 00:45:45.351579 ==
5680 00:45:45.351659
5681 00:45:45.351736
5682 00:45:45.354887 TX Vref Scan disable
5683 00:45:45.357617 == TX Byte 0 ==
5684 00:45:45.360866 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5685 00:45:45.364670 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5686 00:45:45.367791 == TX Byte 1 ==
5687 00:45:45.370846 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5688 00:45:45.374432 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5689 00:45:45.374491
5690 00:45:45.377638 [DATLAT]
5691 00:45:45.377696 Freq=933, CH1 RK0
5692 00:45:45.377748
5693 00:45:45.380996 DATLAT Default: 0xd
5694 00:45:45.381083 0, 0xFFFF, sum = 0
5695 00:45:45.384393 1, 0xFFFF, sum = 0
5696 00:45:45.384482 2, 0xFFFF, sum = 0
5697 00:45:45.387644 3, 0xFFFF, sum = 0
5698 00:45:45.387744 4, 0xFFFF, sum = 0
5699 00:45:45.390921 5, 0xFFFF, sum = 0
5700 00:45:45.390986 6, 0xFFFF, sum = 0
5701 00:45:45.394633 7, 0xFFFF, sum = 0
5702 00:45:45.394699 8, 0xFFFF, sum = 0
5703 00:45:45.397592 9, 0xFFFF, sum = 0
5704 00:45:45.397678 10, 0x0, sum = 1
5705 00:45:45.401238 11, 0x0, sum = 2
5706 00:45:45.401305 12, 0x0, sum = 3
5707 00:45:45.404366 13, 0x0, sum = 4
5708 00:45:45.404455 best_step = 11
5709 00:45:45.404533
5710 00:45:45.404610 ==
5711 00:45:45.407472 Dram Type= 6, Freq= 0, CH_1, rank 0
5712 00:45:45.410940 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5713 00:45:45.414143 ==
5714 00:45:45.414268 RX Vref Scan: 1
5715 00:45:45.414346
5716 00:45:45.417353 RX Vref 0 -> 0, step: 1
5717 00:45:45.417435
5718 00:45:45.421120 RX Delay -45 -> 252, step: 4
5719 00:45:45.421192
5720 00:45:45.424167 Set Vref, RX VrefLevel [Byte0]: 55
5721 00:45:45.427350 [Byte1]: 50
5722 00:45:45.427425
5723 00:45:45.431198 Final RX Vref Byte 0 = 55 to rank0
5724 00:45:45.434519 Final RX Vref Byte 1 = 50 to rank0
5725 00:45:45.437952 Final RX Vref Byte 0 = 55 to rank1
5726 00:45:45.440601 Final RX Vref Byte 1 = 50 to rank1==
5727 00:45:45.443983 Dram Type= 6, Freq= 0, CH_1, rank 0
5728 00:45:45.447346 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5729 00:45:45.447439 ==
5730 00:45:45.450608 DQS Delay:
5731 00:45:45.450674 DQS0 = 0, DQS1 = 0
5732 00:45:45.450730 DQM Delay:
5733 00:45:45.453868 DQM0 = 103, DQM1 = 99
5734 00:45:45.453931 DQ Delay:
5735 00:45:45.457165 DQ0 =106, DQ1 =98, DQ2 =94, DQ3 =102
5736 00:45:45.460571 DQ4 =104, DQ5 =112, DQ6 =110, DQ7 =102
5737 00:45:45.463862 DQ8 =90, DQ9 =90, DQ10 =98, DQ11 =92
5738 00:45:45.467256 DQ12 =108, DQ13 =104, DQ14 =108, DQ15 =106
5739 00:45:45.467339
5740 00:45:45.467417
5741 00:45:45.477691 [DQSOSCAuto] RK0, (LSB)MR18= 0x1c34, (MSB)MR19= 0x505, tDQSOscB0 = 405 ps tDQSOscB1 = 412 ps
5742 00:45:45.481006 CH1 RK0: MR19=505, MR18=1C34
5743 00:45:45.487536 CH1_RK0: MR19=0x505, MR18=0x1C34, DQSOSC=405, MR23=63, INC=66, DEC=44
5744 00:45:45.487628
5745 00:45:45.490953 ----->DramcWriteLeveling(PI) begin...
5746 00:45:45.491022 ==
5747 00:45:45.493662 Dram Type= 6, Freq= 0, CH_1, rank 1
5748 00:45:45.497598 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5749 00:45:45.497699 ==
5750 00:45:45.500754 Write leveling (Byte 0): 28 => 28
5751 00:45:45.504236 Write leveling (Byte 1): 27 => 27
5752 00:45:45.507230 DramcWriteLeveling(PI) end<-----
5753 00:45:45.507317
5754 00:45:45.507398 ==
5755 00:45:45.510712 Dram Type= 6, Freq= 0, CH_1, rank 1
5756 00:45:45.514055 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5757 00:45:45.514119 ==
5758 00:45:45.517220 [Gating] SW mode calibration
5759 00:45:45.523933 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5760 00:45:45.530841 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5761 00:45:45.533957 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5762 00:45:45.537272 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5763 00:45:45.543634 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5764 00:45:45.547013 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5765 00:45:45.550431 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5766 00:45:45.557043 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (0 0) (1 1)
5767 00:45:45.560308 0 14 24 | B1->B0 | 2e2e 3131 | 0 0 | (1 0) (0 0)
5768 00:45:45.563810 0 14 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
5769 00:45:45.570490 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5770 00:45:45.573810 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5771 00:45:45.576908 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5772 00:45:45.583616 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5773 00:45:45.587052 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5774 00:45:45.590172 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5775 00:45:45.596940 0 15 24 | B1->B0 | 3535 2c2c | 0 0 | (0 0) (1 1)
5776 00:45:45.600334 0 15 28 | B1->B0 | 4646 3c3c | 0 0 | (0 0) (0 0)
5777 00:45:45.603561 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5778 00:45:45.610202 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5779 00:45:45.613526 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5780 00:45:45.617010 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5781 00:45:45.620236 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5782 00:45:45.626748 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5783 00:45:45.630077 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5784 00:45:45.633763 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5785 00:45:45.640355 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5786 00:45:45.643669 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5787 00:45:45.646522 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5788 00:45:45.653290 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5789 00:45:45.656734 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5790 00:45:45.660369 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5791 00:45:45.666458 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5792 00:45:45.669936 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5793 00:45:45.673455 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5794 00:45:45.679943 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5795 00:45:45.683019 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5796 00:45:45.686718 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5797 00:45:45.693212 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5798 00:45:45.696538 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5799 00:45:45.699937 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5800 00:45:45.706738 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5801 00:45:45.706868 Total UI for P1: 0, mck2ui 16
5802 00:45:45.713241 best dqsien dly found for B1: ( 1, 2, 26)
5803 00:45:45.716628 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5804 00:45:45.719912 Total UI for P1: 0, mck2ui 16
5805 00:45:45.723210 best dqsien dly found for B0: ( 1, 2, 28)
5806 00:45:45.726638 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5807 00:45:45.729853 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5808 00:45:45.729953
5809 00:45:45.733209 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5810 00:45:45.736586 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5811 00:45:45.740041 [Gating] SW calibration Done
5812 00:45:45.740116 ==
5813 00:45:45.743268 Dram Type= 6, Freq= 0, CH_1, rank 1
5814 00:45:45.746027 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5815 00:45:45.746103 ==
5816 00:45:45.749694 RX Vref Scan: 0
5817 00:45:45.749769
5818 00:45:45.752604 RX Vref 0 -> 0, step: 1
5819 00:45:45.752703
5820 00:45:45.752788 RX Delay -80 -> 252, step: 8
5821 00:45:45.759906 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5822 00:45:45.763112 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5823 00:45:45.766402 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5824 00:45:45.769712 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5825 00:45:45.773034 iDelay=208, Bit 4, Center 95 (8 ~ 183) 176
5826 00:45:45.776368 iDelay=208, Bit 5, Center 119 (32 ~ 207) 176
5827 00:45:45.782938 iDelay=208, Bit 6, Center 119 (32 ~ 207) 176
5828 00:45:45.786352 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5829 00:45:45.789733 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5830 00:45:45.792784 iDelay=208, Bit 9, Center 91 (0 ~ 183) 184
5831 00:45:45.796409 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5832 00:45:45.799454 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5833 00:45:45.806127 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5834 00:45:45.809405 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5835 00:45:45.812753 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5836 00:45:45.816461 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5837 00:45:45.816576 ==
5838 00:45:45.819640 Dram Type= 6, Freq= 0, CH_1, rank 1
5839 00:45:45.826250 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5840 00:45:45.826345 ==
5841 00:45:45.826445 DQS Delay:
5842 00:45:45.829668 DQS0 = 0, DQS1 = 0
5843 00:45:45.829755 DQM Delay:
5844 00:45:45.829837 DQM0 = 103, DQM1 = 98
5845 00:45:45.832887 DQ Delay:
5846 00:45:45.836308 DQ0 =107, DQ1 =99, DQ2 =91, DQ3 =99
5847 00:45:45.839572 DQ4 =95, DQ5 =119, DQ6 =119, DQ7 =99
5848 00:45:45.842904 DQ8 =87, DQ9 =91, DQ10 =99, DQ11 =91
5849 00:45:45.846321 DQ12 =107, DQ13 =103, DQ14 =103, DQ15 =107
5850 00:45:45.846410
5851 00:45:45.846511
5852 00:45:45.846595 ==
5853 00:45:45.849631 Dram Type= 6, Freq= 0, CH_1, rank 1
5854 00:45:45.852957 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5855 00:45:45.853022 ==
5856 00:45:45.853075
5857 00:45:45.853125
5858 00:45:45.856087 TX Vref Scan disable
5859 00:45:45.859211 == TX Byte 0 ==
5860 00:45:45.862606 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5861 00:45:45.865843 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5862 00:45:45.869442 == TX Byte 1 ==
5863 00:45:45.872838 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5864 00:45:45.875834 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5865 00:45:45.875922 ==
5866 00:45:45.879764 Dram Type= 6, Freq= 0, CH_1, rank 1
5867 00:45:45.883006 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5868 00:45:45.885850 ==
5869 00:45:45.885913
5870 00:45:45.885972
5871 00:45:45.886024 TX Vref Scan disable
5872 00:45:45.889825 == TX Byte 0 ==
5873 00:45:45.893176 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5874 00:45:45.899805 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5875 00:45:45.899882 == TX Byte 1 ==
5876 00:45:45.902579 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5877 00:45:45.909314 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5878 00:45:45.909406
5879 00:45:45.909466 [DATLAT]
5880 00:45:45.909521 Freq=933, CH1 RK1
5881 00:45:45.909620
5882 00:45:45.913154 DATLAT Default: 0xb
5883 00:45:45.913246 0, 0xFFFF, sum = 0
5884 00:45:45.915996 1, 0xFFFF, sum = 0
5885 00:45:45.916089 2, 0xFFFF, sum = 0
5886 00:45:45.919788 3, 0xFFFF, sum = 0
5887 00:45:45.919881 4, 0xFFFF, sum = 0
5888 00:45:45.922941 5, 0xFFFF, sum = 0
5889 00:45:45.923035 6, 0xFFFF, sum = 0
5890 00:45:45.926354 7, 0xFFFF, sum = 0
5891 00:45:45.929426 8, 0xFFFF, sum = 0
5892 00:45:45.929520 9, 0xFFFF, sum = 0
5893 00:45:45.932918 10, 0x0, sum = 1
5894 00:45:45.933012 11, 0x0, sum = 2
5895 00:45:45.933109 12, 0x0, sum = 3
5896 00:45:45.936225 13, 0x0, sum = 4
5897 00:45:45.936332 best_step = 11
5898 00:45:45.936406
5899 00:45:45.939569 ==
5900 00:45:45.939644 Dram Type= 6, Freq= 0, CH_1, rank 1
5901 00:45:45.946003 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5902 00:45:45.946092 ==
5903 00:45:45.946167 RX Vref Scan: 0
5904 00:45:45.946236
5905 00:45:45.949534 RX Vref 0 -> 0, step: 1
5906 00:45:45.949691
5907 00:45:45.952872 RX Delay -45 -> 252, step: 4
5908 00:45:45.956190 iDelay=203, Bit 0, Center 108 (27 ~ 190) 164
5909 00:45:45.962446 iDelay=203, Bit 1, Center 98 (15 ~ 182) 168
5910 00:45:45.966167 iDelay=203, Bit 2, Center 94 (11 ~ 178) 168
5911 00:45:45.969473 iDelay=203, Bit 3, Center 100 (19 ~ 182) 164
5912 00:45:45.972584 iDelay=203, Bit 4, Center 100 (19 ~ 182) 164
5913 00:45:45.975878 iDelay=203, Bit 5, Center 118 (35 ~ 202) 168
5914 00:45:45.982636 iDelay=203, Bit 6, Center 114 (31 ~ 198) 168
5915 00:45:45.986230 iDelay=203, Bit 7, Center 104 (19 ~ 190) 172
5916 00:45:45.989223 iDelay=203, Bit 8, Center 92 (11 ~ 174) 164
5917 00:45:45.993024 iDelay=203, Bit 9, Center 90 (3 ~ 178) 176
5918 00:45:45.996056 iDelay=203, Bit 10, Center 102 (19 ~ 186) 168
5919 00:45:45.999571 iDelay=203, Bit 11, Center 94 (11 ~ 178) 168
5920 00:45:46.005762 iDelay=203, Bit 12, Center 108 (19 ~ 198) 180
5921 00:45:46.009465 iDelay=203, Bit 13, Center 108 (27 ~ 190) 164
5922 00:45:46.012649 iDelay=203, Bit 14, Center 106 (27 ~ 186) 160
5923 00:45:46.015929 iDelay=203, Bit 15, Center 108 (23 ~ 194) 172
5924 00:45:46.016020 ==
5925 00:45:46.019267 Dram Type= 6, Freq= 0, CH_1, rank 1
5926 00:45:46.025580 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5927 00:45:46.025660 ==
5928 00:45:46.025719 DQS Delay:
5929 00:45:46.029452 DQS0 = 0, DQS1 = 0
5930 00:45:46.029544 DQM Delay:
5931 00:45:46.032674 DQM0 = 104, DQM1 = 101
5932 00:45:46.032748 DQ Delay:
5933 00:45:46.035910 DQ0 =108, DQ1 =98, DQ2 =94, DQ3 =100
5934 00:45:46.039255 DQ4 =100, DQ5 =118, DQ6 =114, DQ7 =104
5935 00:45:46.042288 DQ8 =92, DQ9 =90, DQ10 =102, DQ11 =94
5936 00:45:46.046012 DQ12 =108, DQ13 =108, DQ14 =106, DQ15 =108
5937 00:45:46.046088
5938 00:45:46.046146
5939 00:45:46.052762 [DQSOSCAuto] RK1, (LSB)MR18= 0x3003, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 406 ps
5940 00:45:46.055730 CH1 RK1: MR19=505, MR18=3003
5941 00:45:46.062402 CH1_RK1: MR19=0x505, MR18=0x3003, DQSOSC=406, MR23=63, INC=65, DEC=43
5942 00:45:46.065767 [RxdqsGatingPostProcess] freq 933
5943 00:45:46.072457 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5944 00:45:46.075964 best DQS0 dly(2T, 0.5T) = (0, 10)
5945 00:45:46.076039 best DQS1 dly(2T, 0.5T) = (0, 10)
5946 00:45:46.079267 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5947 00:45:46.082239 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5948 00:45:46.085554 best DQS0 dly(2T, 0.5T) = (0, 10)
5949 00:45:46.088933 best DQS1 dly(2T, 0.5T) = (0, 10)
5950 00:45:46.092162 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5951 00:45:46.095847 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5952 00:45:46.098817 Pre-setting of DQS Precalculation
5953 00:45:46.105982 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5954 00:45:46.112248 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5955 00:45:46.118957 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5956 00:45:46.119056
5957 00:45:46.119148
5958 00:45:46.122256 [Calibration Summary] 1866 Mbps
5959 00:45:46.122326 CH 0, Rank 0
5960 00:45:46.125476 SW Impedance : PASS
5961 00:45:46.128717 DUTY Scan : NO K
5962 00:45:46.128806 ZQ Calibration : PASS
5963 00:45:46.132008 Jitter Meter : NO K
5964 00:45:46.135882 CBT Training : PASS
5965 00:45:46.135972 Write leveling : PASS
5966 00:45:46.139068 RX DQS gating : PASS
5967 00:45:46.139156 RX DQ/DQS(RDDQC) : PASS
5968 00:45:46.142222 TX DQ/DQS : PASS
5969 00:45:46.145860 RX DATLAT : PASS
5970 00:45:46.145953 RX DQ/DQS(Engine): PASS
5971 00:45:46.149079 TX OE : NO K
5972 00:45:46.149169 All Pass.
5973 00:45:46.149257
5974 00:45:46.152407 CH 0, Rank 1
5975 00:45:46.152495 SW Impedance : PASS
5976 00:45:46.155462 DUTY Scan : NO K
5977 00:45:46.158722 ZQ Calibration : PASS
5978 00:45:46.158785 Jitter Meter : NO K
5979 00:45:46.162463 CBT Training : PASS
5980 00:45:46.165659 Write leveling : PASS
5981 00:45:46.165747 RX DQS gating : PASS
5982 00:45:46.168792 RX DQ/DQS(RDDQC) : PASS
5983 00:45:46.172191 TX DQ/DQS : PASS
5984 00:45:46.172278 RX DATLAT : PASS
5985 00:45:46.175649 RX DQ/DQS(Engine): PASS
5986 00:45:46.179009 TX OE : NO K
5987 00:45:46.179076 All Pass.
5988 00:45:46.179146
5989 00:45:46.179213 CH 1, Rank 0
5990 00:45:46.182208 SW Impedance : PASS
5991 00:45:46.185709 DUTY Scan : NO K
5992 00:45:46.185795 ZQ Calibration : PASS
5993 00:45:46.188740 Jitter Meter : NO K
5994 00:45:46.192135 CBT Training : PASS
5995 00:45:46.192225 Write leveling : PASS
5996 00:45:46.195517 RX DQS gating : PASS
5997 00:45:46.195605 RX DQ/DQS(RDDQC) : PASS
5998 00:45:46.198603 TX DQ/DQS : PASS
5999 00:45:46.201912 RX DATLAT : PASS
6000 00:45:46.201977 RX DQ/DQS(Engine): PASS
6001 00:45:46.205689 TX OE : NO K
6002 00:45:46.205754 All Pass.
6003 00:45:46.205807
6004 00:45:46.208909 CH 1, Rank 1
6005 00:45:46.208995 SW Impedance : PASS
6006 00:45:46.212068 DUTY Scan : NO K
6007 00:45:46.215201 ZQ Calibration : PASS
6008 00:45:46.215268 Jitter Meter : NO K
6009 00:45:46.218499 CBT Training : PASS
6010 00:45:46.222016 Write leveling : PASS
6011 00:45:46.222123 RX DQS gating : PASS
6012 00:45:46.225108 RX DQ/DQS(RDDQC) : PASS
6013 00:45:46.228640 TX DQ/DQS : PASS
6014 00:45:46.228737 RX DATLAT : PASS
6015 00:45:46.231842 RX DQ/DQS(Engine): PASS
6016 00:45:46.235195 TX OE : NO K
6017 00:45:46.235283 All Pass.
6018 00:45:46.235364
6019 00:45:46.235446 DramC Write-DBI off
6020 00:45:46.238517 PER_BANK_REFRESH: Hybrid Mode
6021 00:45:46.242086 TX_TRACKING: ON
6022 00:45:46.248942 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6023 00:45:46.251932 [FAST_K] Save calibration result to emmc
6024 00:45:46.258873 dramc_set_vcore_voltage set vcore to 650000
6025 00:45:46.258951 Read voltage for 400, 6
6026 00:45:46.261481 Vio18 = 0
6027 00:45:46.261610 Vcore = 650000
6028 00:45:46.261691 Vdram = 0
6029 00:45:46.265173 Vddq = 0
6030 00:45:46.265265 Vmddr = 0
6031 00:45:46.268784 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6032 00:45:46.274769 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6033 00:45:46.278599 MEM_TYPE=3, freq_sel=20
6034 00:45:46.278705 sv_algorithm_assistance_LP4_800
6035 00:45:46.284890 ============ PULL DRAM RESETB DOWN ============
6036 00:45:46.288571 ========== PULL DRAM RESETB DOWN end =========
6037 00:45:46.291859 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6038 00:45:46.294797 ===================================
6039 00:45:46.298578 LPDDR4 DRAM CONFIGURATION
6040 00:45:46.301847 ===================================
6041 00:45:46.304939 EX_ROW_EN[0] = 0x0
6042 00:45:46.305066 EX_ROW_EN[1] = 0x0
6043 00:45:46.308080 LP4Y_EN = 0x0
6044 00:45:46.308143 WORK_FSP = 0x0
6045 00:45:46.311665 WL = 0x2
6046 00:45:46.311752 RL = 0x2
6047 00:45:46.314737 BL = 0x2
6048 00:45:46.314830 RPST = 0x0
6049 00:45:46.318158 RD_PRE = 0x0
6050 00:45:46.318222 WR_PRE = 0x1
6051 00:45:46.321303 WR_PST = 0x0
6052 00:45:46.321392 DBI_WR = 0x0
6053 00:45:46.325129 DBI_RD = 0x0
6054 00:45:46.327795 OTF = 0x1
6055 00:45:46.327884 ===================================
6056 00:45:46.331618 ===================================
6057 00:45:46.334908 ANA top config
6058 00:45:46.338046 ===================================
6059 00:45:46.341886 DLL_ASYNC_EN = 0
6060 00:45:46.341951 ALL_SLAVE_EN = 1
6061 00:45:46.344569 NEW_RANK_MODE = 1
6062 00:45:46.348155 DLL_IDLE_MODE = 1
6063 00:45:46.351438 LP45_APHY_COMB_EN = 1
6064 00:45:46.354465 TX_ODT_DIS = 1
6065 00:45:46.354539 NEW_8X_MODE = 1
6066 00:45:46.358021 ===================================
6067 00:45:46.361550 ===================================
6068 00:45:46.364828 data_rate = 800
6069 00:45:46.367812 CKR = 1
6070 00:45:46.371515 DQ_P2S_RATIO = 4
6071 00:45:46.374732 ===================================
6072 00:45:46.377976 CA_P2S_RATIO = 4
6073 00:45:46.378052 DQ_CA_OPEN = 0
6074 00:45:46.381187 DQ_SEMI_OPEN = 1
6075 00:45:46.384897 CA_SEMI_OPEN = 1
6076 00:45:46.387965 CA_FULL_RATE = 0
6077 00:45:46.391763 DQ_CKDIV4_EN = 0
6078 00:45:46.394795 CA_CKDIV4_EN = 1
6079 00:45:46.394888 CA_PREDIV_EN = 0
6080 00:45:46.397941 PH8_DLY = 0
6081 00:45:46.401475 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6082 00:45:46.404574 DQ_AAMCK_DIV = 0
6083 00:45:46.407810 CA_AAMCK_DIV = 0
6084 00:45:46.411234 CA_ADMCK_DIV = 4
6085 00:45:46.411310 DQ_TRACK_CA_EN = 0
6086 00:45:46.414899 CA_PICK = 800
6087 00:45:46.418209 CA_MCKIO = 400
6088 00:45:46.421374 MCKIO_SEMI = 400
6089 00:45:46.425131 PLL_FREQ = 3016
6090 00:45:46.428388 DQ_UI_PI_RATIO = 32
6091 00:45:46.431433 CA_UI_PI_RATIO = 32
6092 00:45:46.434633 ===================================
6093 00:45:46.438179 ===================================
6094 00:45:46.438249 memory_type:LPDDR4
6095 00:45:46.441183 GP_NUM : 10
6096 00:45:46.444423 SRAM_EN : 1
6097 00:45:46.444495 MD32_EN : 0
6098 00:45:46.448069 ===================================
6099 00:45:46.451491 [ANA_INIT] >>>>>>>>>>>>>>
6100 00:45:46.454730 <<<<<< [CONFIGURE PHASE]: ANA_TX
6101 00:45:46.457995 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6102 00:45:46.461125 ===================================
6103 00:45:46.464854 data_rate = 800,PCW = 0X7400
6104 00:45:46.467768 ===================================
6105 00:45:46.471133 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6106 00:45:46.474311 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6107 00:45:46.487849 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6108 00:45:46.491107 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6109 00:45:46.494740 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6110 00:45:46.497772 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6111 00:45:46.500962 [ANA_INIT] flow start
6112 00:45:46.501040 [ANA_INIT] PLL >>>>>>>>
6113 00:45:46.504472 [ANA_INIT] PLL <<<<<<<<
6114 00:45:46.507860 [ANA_INIT] MIDPI >>>>>>>>
6115 00:45:46.511447 [ANA_INIT] MIDPI <<<<<<<<
6116 00:45:46.511522 [ANA_INIT] DLL >>>>>>>>
6117 00:45:46.514548 [ANA_INIT] flow end
6118 00:45:46.517721 ============ LP4 DIFF to SE enter ============
6119 00:45:46.521451 ============ LP4 DIFF to SE exit ============
6120 00:45:46.524192 [ANA_INIT] <<<<<<<<<<<<<
6121 00:45:46.528023 [Flow] Enable top DCM control >>>>>
6122 00:45:46.531226 [Flow] Enable top DCM control <<<<<
6123 00:45:46.534504 Enable DLL master slave shuffle
6124 00:45:46.540946 ==============================================================
6125 00:45:46.541052 Gating Mode config
6126 00:45:46.547649 ==============================================================
6127 00:45:46.547726 Config description:
6128 00:45:46.557990 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6129 00:45:46.564643 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6130 00:45:46.570997 SELPH_MODE 0: By rank 1: By Phase
6131 00:45:46.574234 ==============================================================
6132 00:45:46.577454 GAT_TRACK_EN = 0
6133 00:45:46.581342 RX_GATING_MODE = 2
6134 00:45:46.584521 RX_GATING_TRACK_MODE = 2
6135 00:45:46.587945 SELPH_MODE = 1
6136 00:45:46.590880 PICG_EARLY_EN = 1
6137 00:45:46.594696 VALID_LAT_VALUE = 1
6138 00:45:46.597684 ==============================================================
6139 00:45:46.600905 Enter into Gating configuration >>>>
6140 00:45:46.604037 Exit from Gating configuration <<<<
6141 00:45:46.607723 Enter into DVFS_PRE_config >>>>>
6142 00:45:46.620957 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6143 00:45:46.624200 Exit from DVFS_PRE_config <<<<<
6144 00:45:46.624301 Enter into PICG configuration >>>>
6145 00:45:46.627526 Exit from PICG configuration <<<<
6146 00:45:46.630893 [RX_INPUT] configuration >>>>>
6147 00:45:46.634478 [RX_INPUT] configuration <<<<<
6148 00:45:46.640994 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6149 00:45:46.644286 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6150 00:45:46.650810 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6151 00:45:46.657356 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6152 00:45:46.664217 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6153 00:45:46.670987 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6154 00:45:46.674404 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6155 00:45:46.677476 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6156 00:45:46.680986 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6157 00:45:46.687283 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6158 00:45:46.690551 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6159 00:45:46.694226 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6160 00:45:46.697270 ===================================
6161 00:45:46.700583 LPDDR4 DRAM CONFIGURATION
6162 00:45:46.703698 ===================================
6163 00:45:46.707605 EX_ROW_EN[0] = 0x0
6164 00:45:46.707683 EX_ROW_EN[1] = 0x0
6165 00:45:46.710822 LP4Y_EN = 0x0
6166 00:45:46.710898 WORK_FSP = 0x0
6167 00:45:46.714131 WL = 0x2
6168 00:45:46.714207 RL = 0x2
6169 00:45:46.717098 BL = 0x2
6170 00:45:46.717173 RPST = 0x0
6171 00:45:46.720562 RD_PRE = 0x0
6172 00:45:46.720637 WR_PRE = 0x1
6173 00:45:46.723930 WR_PST = 0x0
6174 00:45:46.724006 DBI_WR = 0x0
6175 00:45:46.727593 DBI_RD = 0x0
6176 00:45:46.727683 OTF = 0x1
6177 00:45:46.730736 ===================================
6178 00:45:46.737099 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6179 00:45:46.740452 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6180 00:45:46.743583 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6181 00:45:46.746923 ===================================
6182 00:45:46.750110 LPDDR4 DRAM CONFIGURATION
6183 00:45:46.753789 ===================================
6184 00:45:46.753864 EX_ROW_EN[0] = 0x10
6185 00:45:46.756869 EX_ROW_EN[1] = 0x0
6186 00:45:46.760387 LP4Y_EN = 0x0
6187 00:45:46.760463 WORK_FSP = 0x0
6188 00:45:46.763695 WL = 0x2
6189 00:45:46.763770 RL = 0x2
6190 00:45:46.766899 BL = 0x2
6191 00:45:46.766996 RPST = 0x0
6192 00:45:46.770088 RD_PRE = 0x0
6193 00:45:46.770163 WR_PRE = 0x1
6194 00:45:46.773760 WR_PST = 0x0
6195 00:45:46.773835 DBI_WR = 0x0
6196 00:45:46.776974 DBI_RD = 0x0
6197 00:45:46.777049 OTF = 0x1
6198 00:45:46.780323 ===================================
6199 00:45:46.787304 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6200 00:45:46.791682 nWR fixed to 30
6201 00:45:46.794515 [ModeRegInit_LP4] CH0 RK0
6202 00:45:46.794590 [ModeRegInit_LP4] CH0 RK1
6203 00:45:46.797847 [ModeRegInit_LP4] CH1 RK0
6204 00:45:46.801053 [ModeRegInit_LP4] CH1 RK1
6205 00:45:46.801128 match AC timing 19
6206 00:45:46.807589 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6207 00:45:46.811402 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6208 00:45:46.814531 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6209 00:45:46.820969 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6210 00:45:46.824849 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6211 00:45:46.824924 ==
6212 00:45:46.827995 Dram Type= 6, Freq= 0, CH_0, rank 0
6213 00:45:46.830950 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6214 00:45:46.831026 ==
6215 00:45:46.837975 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6216 00:45:46.844697 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6217 00:45:46.847919 [CA 0] Center 36 (8~64) winsize 57
6218 00:45:46.851155 [CA 1] Center 36 (8~64) winsize 57
6219 00:45:46.854357 [CA 2] Center 36 (8~64) winsize 57
6220 00:45:46.854433 [CA 3] Center 36 (8~64) winsize 57
6221 00:45:46.858161 [CA 4] Center 36 (8~64) winsize 57
6222 00:45:46.861192 [CA 5] Center 36 (8~64) winsize 57
6223 00:45:46.861269
6224 00:45:46.864795 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6225 00:45:46.867604
6226 00:45:46.871237 [CATrainingPosCal] consider 1 rank data
6227 00:45:46.871313 u2DelayCellTimex100 = 270/100 ps
6228 00:45:46.877466 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6229 00:45:46.880833 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6230 00:45:46.884263 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6231 00:45:46.888050 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6232 00:45:46.891198 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6233 00:45:46.894461 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6234 00:45:46.894537
6235 00:45:46.897695 CA PerBit enable=1, Macro0, CA PI delay=36
6236 00:45:46.897771
6237 00:45:46.900938 [CBTSetCACLKResult] CA Dly = 36
6238 00:45:46.904206 CS Dly: 1 (0~32)
6239 00:45:46.904282 ==
6240 00:45:46.907939 Dram Type= 6, Freq= 0, CH_0, rank 1
6241 00:45:46.911376 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6242 00:45:46.911452 ==
6243 00:45:46.917678 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6244 00:45:46.920899 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6245 00:45:46.924502 [CA 0] Center 36 (8~64) winsize 57
6246 00:45:46.927715 [CA 1] Center 36 (8~64) winsize 57
6247 00:45:46.930968 [CA 2] Center 36 (8~64) winsize 57
6248 00:45:46.934859 [CA 3] Center 36 (8~64) winsize 57
6249 00:45:46.938010 [CA 4] Center 36 (8~64) winsize 57
6250 00:45:46.941118 [CA 5] Center 36 (8~64) winsize 57
6251 00:45:46.941215
6252 00:45:46.944600 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6253 00:45:46.944677
6254 00:45:46.948015 [CATrainingPosCal] consider 2 rank data
6255 00:45:46.950930 u2DelayCellTimex100 = 270/100 ps
6256 00:45:46.954326 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6257 00:45:46.958228 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6258 00:45:46.961419 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6259 00:45:46.964686 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6260 00:45:46.971182 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6261 00:45:46.974428 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6262 00:45:46.974504
6263 00:45:46.977542 CA PerBit enable=1, Macro0, CA PI delay=36
6264 00:45:46.977637
6265 00:45:46.980862 [CBTSetCACLKResult] CA Dly = 36
6266 00:45:46.980930 CS Dly: 1 (0~32)
6267 00:45:46.980985
6268 00:45:46.984766 ----->DramcWriteLeveling(PI) begin...
6269 00:45:46.984842 ==
6270 00:45:46.987744 Dram Type= 6, Freq= 0, CH_0, rank 0
6271 00:45:46.994606 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6272 00:45:46.994707 ==
6273 00:45:46.998133 Write leveling (Byte 0): 40 => 8
6274 00:45:46.998244 Write leveling (Byte 1): 40 => 8
6275 00:45:47.001106 DramcWriteLeveling(PI) end<-----
6276 00:45:47.001181
6277 00:45:47.001239 ==
6278 00:45:47.004768 Dram Type= 6, Freq= 0, CH_0, rank 0
6279 00:45:47.010798 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6280 00:45:47.010888 ==
6281 00:45:47.014640 [Gating] SW mode calibration
6282 00:45:47.021028 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6283 00:45:47.024070 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6284 00:45:47.031250 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6285 00:45:47.034224 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6286 00:45:47.037443 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6287 00:45:47.041034 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6288 00:45:47.047526 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6289 00:45:47.050776 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6290 00:45:47.054553 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6291 00:45:47.061122 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6292 00:45:47.064005 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6293 00:45:47.067825 Total UI for P1: 0, mck2ui 16
6294 00:45:47.071021 best dqsien dly found for B0: ( 0, 14, 24)
6295 00:45:47.074273 Total UI for P1: 0, mck2ui 16
6296 00:45:47.077429 best dqsien dly found for B1: ( 0, 14, 24)
6297 00:45:47.080618 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6298 00:45:47.084627 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6299 00:45:47.084695
6300 00:45:47.087713 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6301 00:45:47.094170 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6302 00:45:47.094260 [Gating] SW calibration Done
6303 00:45:47.094320 ==
6304 00:45:47.097416 Dram Type= 6, Freq= 0, CH_0, rank 0
6305 00:45:47.104390 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6306 00:45:47.104529 ==
6307 00:45:47.104590 RX Vref Scan: 0
6308 00:45:47.104643
6309 00:45:47.107441 RX Vref 0 -> 0, step: 1
6310 00:45:47.107506
6311 00:45:47.110912 RX Delay -410 -> 252, step: 16
6312 00:45:47.114598 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6313 00:45:47.117294 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6314 00:45:47.124065 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6315 00:45:47.127263 iDelay=230, Bit 3, Center -27 (-266 ~ 213) 480
6316 00:45:47.131176 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6317 00:45:47.134423 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6318 00:45:47.140507 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6319 00:45:47.144136 iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480
6320 00:45:47.147109 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6321 00:45:47.150500 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6322 00:45:47.157135 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6323 00:45:47.160394 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6324 00:45:47.163572 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6325 00:45:47.167356 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6326 00:45:47.174011 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6327 00:45:47.177145 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6328 00:45:47.177213 ==
6329 00:45:47.180453 Dram Type= 6, Freq= 0, CH_0, rank 0
6330 00:45:47.183738 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6331 00:45:47.183806 ==
6332 00:45:47.186859 DQS Delay:
6333 00:45:47.186927 DQS0 = 27, DQS1 = 35
6334 00:45:47.190647 DQM Delay:
6335 00:45:47.190717 DQM0 = 8, DQM1 = 11
6336 00:45:47.190773 DQ Delay:
6337 00:45:47.193949 DQ0 =8, DQ1 =16, DQ2 =0, DQ3 =0
6338 00:45:47.197008 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6339 00:45:47.200209 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6340 00:45:47.203417 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6341 00:45:47.203485
6342 00:45:47.203544
6343 00:45:47.203597 ==
6344 00:45:47.207335 Dram Type= 6, Freq= 0, CH_0, rank 0
6345 00:45:47.210581 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6346 00:45:47.213786 ==
6347 00:45:47.213852
6348 00:45:47.213913
6349 00:45:47.213965 TX Vref Scan disable
6350 00:45:47.216906 == TX Byte 0 ==
6351 00:45:47.220521 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6352 00:45:47.223602 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6353 00:45:47.227100 == TX Byte 1 ==
6354 00:45:47.230193 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6355 00:45:47.233757 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6356 00:45:47.233823 ==
6357 00:45:47.236605 Dram Type= 6, Freq= 0, CH_0, rank 0
6358 00:45:47.243693 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6359 00:45:47.243763 ==
6360 00:45:47.243821
6361 00:45:47.243873
6362 00:45:47.243928 TX Vref Scan disable
6363 00:45:47.247059 == TX Byte 0 ==
6364 00:45:47.250378 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6365 00:45:47.253579 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6366 00:45:47.256606 == TX Byte 1 ==
6367 00:45:47.260250 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6368 00:45:47.263530 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6369 00:45:47.263595
6370 00:45:47.266948 [DATLAT]
6371 00:45:47.267013 Freq=400, CH0 RK0
6372 00:45:47.267068
6373 00:45:47.270062 DATLAT Default: 0xf
6374 00:45:47.270127 0, 0xFFFF, sum = 0
6375 00:45:47.273058 1, 0xFFFF, sum = 0
6376 00:45:47.273120 2, 0xFFFF, sum = 0
6377 00:45:47.276651 3, 0xFFFF, sum = 0
6378 00:45:47.276719 4, 0xFFFF, sum = 0
6379 00:45:47.280306 5, 0xFFFF, sum = 0
6380 00:45:47.280372 6, 0xFFFF, sum = 0
6381 00:45:47.283501 7, 0xFFFF, sum = 0
6382 00:45:47.283567 8, 0xFFFF, sum = 0
6383 00:45:47.286680 9, 0xFFFF, sum = 0
6384 00:45:47.286748 10, 0xFFFF, sum = 0
6385 00:45:47.290425 11, 0xFFFF, sum = 0
6386 00:45:47.290496 12, 0xFFFF, sum = 0
6387 00:45:47.293688 13, 0x0, sum = 1
6388 00:45:47.293760 14, 0x0, sum = 2
6389 00:45:47.296882 15, 0x0, sum = 3
6390 00:45:47.296950 16, 0x0, sum = 4
6391 00:45:47.300040 best_step = 14
6392 00:45:47.300103
6393 00:45:47.300182 ==
6394 00:45:47.303644 Dram Type= 6, Freq= 0, CH_0, rank 0
6395 00:45:47.306861 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6396 00:45:47.306952 ==
6397 00:45:47.310033 RX Vref Scan: 1
6398 00:45:47.310245
6399 00:45:47.310324 RX Vref 0 -> 0, step: 1
6400 00:45:47.310379
6401 00:45:47.313846 RX Delay -311 -> 252, step: 8
6402 00:45:47.313911
6403 00:45:47.317053 Set Vref, RX VrefLevel [Byte0]: 57
6404 00:45:47.319951 [Byte1]: 49
6405 00:45:47.324476
6406 00:45:47.324593 Final RX Vref Byte 0 = 57 to rank0
6407 00:45:47.328019 Final RX Vref Byte 1 = 49 to rank0
6408 00:45:47.331148 Final RX Vref Byte 0 = 57 to rank1
6409 00:45:47.334257 Final RX Vref Byte 1 = 49 to rank1==
6410 00:45:47.337443 Dram Type= 6, Freq= 0, CH_0, rank 0
6411 00:45:47.344494 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6412 00:45:47.344587 ==
6413 00:45:47.344686 DQS Delay:
6414 00:45:47.347845 DQS0 = 28, DQS1 = 36
6415 00:45:47.347914 DQM Delay:
6416 00:45:47.347970 DQM0 = 11, DQM1 = 13
6417 00:45:47.351255 DQ Delay:
6418 00:45:47.354529 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =8
6419 00:45:47.354604 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6420 00:45:47.357430 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =4
6421 00:45:47.361166 DQ12 =20, DQ13 =16, DQ14 =24, DQ15 =20
6422 00:45:47.361236
6423 00:45:47.364340
6424 00:45:47.371257 [DQSOSCAuto] RK0, (LSB)MR18= 0xd2be, (MSB)MR19= 0xc0c, tDQSOscB0 = 386 ps tDQSOscB1 = 383 ps
6425 00:45:47.374539 CH0 RK0: MR19=C0C, MR18=D2BE
6426 00:45:47.381120 CH0_RK0: MR19=0xC0C, MR18=0xD2BE, DQSOSC=383, MR23=63, INC=402, DEC=268
6427 00:45:47.381192 ==
6428 00:45:47.383978 Dram Type= 6, Freq= 0, CH_0, rank 1
6429 00:45:47.387331 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6430 00:45:47.387397 ==
6431 00:45:47.390947 [Gating] SW mode calibration
6432 00:45:47.397755 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6433 00:45:47.404114 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6434 00:45:47.407763 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6435 00:45:47.410960 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6436 00:45:47.414138 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6437 00:45:47.421167 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6438 00:45:47.424374 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6439 00:45:47.427636 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6440 00:45:47.434433 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6441 00:45:47.437509 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6442 00:45:47.441231 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6443 00:45:47.444402 Total UI for P1: 0, mck2ui 16
6444 00:45:47.447615 best dqsien dly found for B0: ( 0, 14, 24)
6445 00:45:47.450976 Total UI for P1: 0, mck2ui 16
6446 00:45:47.454352 best dqsien dly found for B1: ( 0, 14, 24)
6447 00:45:47.457696 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6448 00:45:47.461003 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6449 00:45:47.461070
6450 00:45:47.467605 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6451 00:45:47.470919 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6452 00:45:47.473948 [Gating] SW calibration Done
6453 00:45:47.474011 ==
6454 00:45:47.477167 Dram Type= 6, Freq= 0, CH_0, rank 1
6455 00:45:47.480393 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6456 00:45:47.480465 ==
6457 00:45:47.480521 RX Vref Scan: 0
6458 00:45:47.480575
6459 00:45:47.484198 RX Vref 0 -> 0, step: 1
6460 00:45:47.484262
6461 00:45:47.487188 RX Delay -410 -> 252, step: 16
6462 00:45:47.490762 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6463 00:45:47.497061 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6464 00:45:47.500410 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6465 00:45:47.504108 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6466 00:45:47.507336 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6467 00:45:47.513968 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6468 00:45:47.516954 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6469 00:45:47.520753 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6470 00:45:47.524070 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6471 00:45:47.530456 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6472 00:45:47.533679 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6473 00:45:47.536754 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6474 00:45:47.540839 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6475 00:45:47.546827 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6476 00:45:47.550778 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6477 00:45:47.553981 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6478 00:45:47.554049 ==
6479 00:45:47.557132 Dram Type= 6, Freq= 0, CH_0, rank 1
6480 00:45:47.560403 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6481 00:45:47.563675 ==
6482 00:45:47.563775 DQS Delay:
6483 00:45:47.563863 DQS0 = 27, DQS1 = 35
6484 00:45:47.566916 DQM Delay:
6485 00:45:47.566978 DQM0 = 12, DQM1 = 11
6486 00:45:47.570209 DQ Delay:
6487 00:45:47.570278 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6488 00:45:47.573495 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6489 00:45:47.576754 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6490 00:45:47.580459 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6491 00:45:47.580528
6492 00:45:47.580586
6493 00:45:47.583741 ==
6494 00:45:47.583804 Dram Type= 6, Freq= 0, CH_0, rank 1
6495 00:45:47.589992 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6496 00:45:47.590061 ==
6497 00:45:47.590117
6498 00:45:47.590169
6499 00:45:47.593617 TX Vref Scan disable
6500 00:45:47.593718 == TX Byte 0 ==
6501 00:45:47.596843 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6502 00:45:47.600434 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6503 00:45:47.603564 == TX Byte 1 ==
6504 00:45:47.606562 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6505 00:45:47.610091 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6506 00:45:47.613383 ==
6507 00:45:47.617001 Dram Type= 6, Freq= 0, CH_0, rank 1
6508 00:45:47.619825 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6509 00:45:47.619927 ==
6510 00:45:47.620009
6511 00:45:47.620096
6512 00:45:47.623078 TX Vref Scan disable
6513 00:45:47.623149 == TX Byte 0 ==
6514 00:45:47.626299 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6515 00:45:47.632931 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6516 00:45:47.633004 == TX Byte 1 ==
6517 00:45:47.636896 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6518 00:45:47.643018 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6519 00:45:47.643088
6520 00:45:47.643172 [DATLAT]
6521 00:45:47.643281 Freq=400, CH0 RK1
6522 00:45:47.643364
6523 00:45:47.646237 DATLAT Default: 0xe
6524 00:45:47.646303 0, 0xFFFF, sum = 0
6525 00:45:47.649563 1, 0xFFFF, sum = 0
6526 00:45:47.649643 2, 0xFFFF, sum = 0
6527 00:45:47.653282 3, 0xFFFF, sum = 0
6528 00:45:47.656162 4, 0xFFFF, sum = 0
6529 00:45:47.656229 5, 0xFFFF, sum = 0
6530 00:45:47.660036 6, 0xFFFF, sum = 0
6531 00:45:47.660103 7, 0xFFFF, sum = 0
6532 00:45:47.663288 8, 0xFFFF, sum = 0
6533 00:45:47.663356 9, 0xFFFF, sum = 0
6534 00:45:47.666505 10, 0xFFFF, sum = 0
6535 00:45:47.666571 11, 0xFFFF, sum = 0
6536 00:45:47.669693 12, 0xFFFF, sum = 0
6537 00:45:47.669764 13, 0x0, sum = 1
6538 00:45:47.672831 14, 0x0, sum = 2
6539 00:45:47.672898 15, 0x0, sum = 3
6540 00:45:47.676679 16, 0x0, sum = 4
6541 00:45:47.676745 best_step = 14
6542 00:45:47.676800
6543 00:45:47.676852 ==
6544 00:45:47.679316 Dram Type= 6, Freq= 0, CH_0, rank 1
6545 00:45:47.683166 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6546 00:45:47.685872 ==
6547 00:45:47.685933 RX Vref Scan: 0
6548 00:45:47.685987
6549 00:45:47.689114 RX Vref 0 -> 0, step: 1
6550 00:45:47.689177
6551 00:45:47.693047 RX Delay -311 -> 252, step: 8
6552 00:45:47.696203 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6553 00:45:47.702947 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6554 00:45:47.706090 iDelay=217, Bit 2, Center -20 (-247 ~ 208) 456
6555 00:45:47.709396 iDelay=217, Bit 3, Center -20 (-247 ~ 208) 456
6556 00:45:47.712881 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6557 00:45:47.719175 iDelay=217, Bit 5, Center -24 (-247 ~ 200) 448
6558 00:45:47.722799 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6559 00:45:47.725754 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6560 00:45:47.729081 iDelay=217, Bit 8, Center -32 (-255 ~ 192) 448
6561 00:45:47.735857 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6562 00:45:47.739335 iDelay=217, Bit 10, Center -20 (-239 ~ 200) 440
6563 00:45:47.742603 iDelay=217, Bit 11, Center -28 (-247 ~ 192) 440
6564 00:45:47.749141 iDelay=217, Bit 12, Center -20 (-239 ~ 200) 440
6565 00:45:47.752012 iDelay=217, Bit 13, Center -20 (-239 ~ 200) 440
6566 00:45:47.755648 iDelay=217, Bit 14, Center -12 (-231 ~ 208) 440
6567 00:45:47.758851 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6568 00:45:47.758917 ==
6569 00:45:47.762356 Dram Type= 6, Freq= 0, CH_0, rank 1
6570 00:45:47.768669 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6571 00:45:47.768737 ==
6572 00:45:47.768794 DQS Delay:
6573 00:45:47.771922 DQS0 = 24, DQS1 = 32
6574 00:45:47.771988 DQM Delay:
6575 00:45:47.772047 DQM0 = 7, DQM1 = 9
6576 00:45:47.775769 DQ Delay:
6577 00:45:47.779082 DQ0 =8, DQ1 =8, DQ2 =4, DQ3 =4
6578 00:45:47.779147 DQ4 =8, DQ5 =0, DQ6 =12, DQ7 =16
6579 00:45:47.782336 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6580 00:45:47.785444 DQ12 =12, DQ13 =12, DQ14 =20, DQ15 =16
6581 00:45:47.785521
6582 00:45:47.788678
6583 00:45:47.795203 [DQSOSCAuto] RK1, (LSB)MR18= 0xbc5b, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 386 ps
6584 00:45:47.798413 CH0 RK1: MR19=C0C, MR18=BC5B
6585 00:45:47.805278 CH0_RK1: MR19=0xC0C, MR18=0xBC5B, DQSOSC=386, MR23=63, INC=396, DEC=264
6586 00:45:47.808443 [RxdqsGatingPostProcess] freq 400
6587 00:45:47.812506 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6588 00:45:47.815114 best DQS0 dly(2T, 0.5T) = (0, 10)
6589 00:45:47.818771 best DQS1 dly(2T, 0.5T) = (0, 10)
6590 00:45:47.822017 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6591 00:45:47.825221 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6592 00:45:47.828359 best DQS0 dly(2T, 0.5T) = (0, 10)
6593 00:45:47.831844 best DQS1 dly(2T, 0.5T) = (0, 10)
6594 00:45:47.835232 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6595 00:45:47.838613 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6596 00:45:47.842002 Pre-setting of DQS Precalculation
6597 00:45:47.845032 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6598 00:45:47.845119 ==
6599 00:45:47.848735 Dram Type= 6, Freq= 0, CH_1, rank 0
6600 00:45:47.855085 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6601 00:45:47.855159 ==
6602 00:45:47.858571 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6603 00:45:47.865332 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6604 00:45:47.868435 [CA 0] Center 36 (8~64) winsize 57
6605 00:45:47.871521 [CA 1] Center 36 (8~64) winsize 57
6606 00:45:47.875112 [CA 2] Center 36 (8~64) winsize 57
6607 00:45:47.878250 [CA 3] Center 36 (8~64) winsize 57
6608 00:45:47.881790 [CA 4] Center 36 (8~64) winsize 57
6609 00:45:47.884941 [CA 5] Center 36 (8~64) winsize 57
6610 00:45:47.885009
6611 00:45:47.888214 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6612 00:45:47.888276
6613 00:45:47.891463 [CATrainingPosCal] consider 1 rank data
6614 00:45:47.895419 u2DelayCellTimex100 = 270/100 ps
6615 00:45:47.898609 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6616 00:45:47.901810 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6617 00:45:47.905110 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6618 00:45:47.908371 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6619 00:45:47.911515 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6620 00:45:47.915419 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6621 00:45:47.915484
6622 00:45:47.921484 CA PerBit enable=1, Macro0, CA PI delay=36
6623 00:45:47.921582
6624 00:45:47.921642 [CBTSetCACLKResult] CA Dly = 36
6625 00:45:47.925206 CS Dly: 1 (0~32)
6626 00:45:47.925270 ==
6627 00:45:47.928555 Dram Type= 6, Freq= 0, CH_1, rank 1
6628 00:45:47.931664 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6629 00:45:47.931728 ==
6630 00:45:47.937943 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6631 00:45:47.945039 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6632 00:45:47.948030 [CA 0] Center 36 (8~64) winsize 57
6633 00:45:47.951251 [CA 1] Center 36 (8~64) winsize 57
6634 00:45:47.954591 [CA 2] Center 36 (8~64) winsize 57
6635 00:45:47.954657 [CA 3] Center 36 (8~64) winsize 57
6636 00:45:47.957907 [CA 4] Center 36 (8~64) winsize 57
6637 00:45:47.961263 [CA 5] Center 36 (8~64) winsize 57
6638 00:45:47.961328
6639 00:45:47.968040 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6640 00:45:47.968118
6641 00:45:47.971252 [CATrainingPosCal] consider 2 rank data
6642 00:45:47.975011 u2DelayCellTimex100 = 270/100 ps
6643 00:45:47.978140 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6644 00:45:47.981129 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6645 00:45:47.984716 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6646 00:45:47.988088 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6647 00:45:47.991269 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6648 00:45:47.994630 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6649 00:45:47.994697
6650 00:45:47.998029 CA PerBit enable=1, Macro0, CA PI delay=36
6651 00:45:47.998103
6652 00:45:48.001327 [CBTSetCACLKResult] CA Dly = 36
6653 00:45:48.004574 CS Dly: 1 (0~32)
6654 00:45:48.004638
6655 00:45:48.008031 ----->DramcWriteLeveling(PI) begin...
6656 00:45:48.008096 ==
6657 00:45:48.011046 Dram Type= 6, Freq= 0, CH_1, rank 0
6658 00:45:48.014244 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6659 00:45:48.014316 ==
6660 00:45:48.018105 Write leveling (Byte 0): 40 => 8
6661 00:45:48.021281 Write leveling (Byte 1): 40 => 8
6662 00:45:48.024434 DramcWriteLeveling(PI) end<-----
6663 00:45:48.024498
6664 00:45:48.024556 ==
6665 00:45:48.028005 Dram Type= 6, Freq= 0, CH_1, rank 0
6666 00:45:48.031246 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6667 00:45:48.031317 ==
6668 00:45:48.034468 [Gating] SW mode calibration
6669 00:45:48.041062 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6670 00:45:48.048079 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6671 00:45:48.050988 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6672 00:45:48.054418 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6673 00:45:48.060930 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6674 00:45:48.064523 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6675 00:45:48.067558 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6676 00:45:48.074624 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6677 00:45:48.077755 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6678 00:45:48.081210 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6679 00:45:48.087825 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6680 00:45:48.087896 Total UI for P1: 0, mck2ui 16
6681 00:45:48.094131 best dqsien dly found for B0: ( 0, 14, 24)
6682 00:45:48.094207 Total UI for P1: 0, mck2ui 16
6683 00:45:48.097701 best dqsien dly found for B1: ( 0, 14, 24)
6684 00:45:48.104598 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6685 00:45:48.107953 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6686 00:45:48.108020
6687 00:45:48.110718 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6688 00:45:48.114244 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6689 00:45:48.118118 [Gating] SW calibration Done
6690 00:45:48.118188 ==
6691 00:45:48.121250 Dram Type= 6, Freq= 0, CH_1, rank 0
6692 00:45:48.124648 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6693 00:45:48.124722 ==
6694 00:45:48.127911 RX Vref Scan: 0
6695 00:45:48.127974
6696 00:45:48.128029 RX Vref 0 -> 0, step: 1
6697 00:45:48.128081
6698 00:45:48.131104 RX Delay -410 -> 252, step: 16
6699 00:45:48.134647 iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480
6700 00:45:48.140849 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6701 00:45:48.144530 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6702 00:45:48.147783 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6703 00:45:48.150934 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6704 00:45:48.157475 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6705 00:45:48.161077 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6706 00:45:48.163904 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6707 00:45:48.167678 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6708 00:45:48.174130 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6709 00:45:48.177187 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6710 00:45:48.180638 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6711 00:45:48.186910 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6712 00:45:48.190547 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6713 00:45:48.194042 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6714 00:45:48.197389 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6715 00:45:48.197460 ==
6716 00:45:48.200216 Dram Type= 6, Freq= 0, CH_1, rank 0
6717 00:45:48.207231 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6718 00:45:48.207309 ==
6719 00:45:48.207370 DQS Delay:
6720 00:45:48.210325 DQS0 = 35, DQS1 = 35
6721 00:45:48.210402 DQM Delay:
6722 00:45:48.214078 DQM0 = 17, DQM1 = 12
6723 00:45:48.214154 DQ Delay:
6724 00:45:48.217372 DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =16
6725 00:45:48.220176 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16
6726 00:45:48.223758 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6727 00:45:48.227345 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =16
6728 00:45:48.227421
6729 00:45:48.227480
6730 00:45:48.227533 ==
6731 00:45:48.230416 Dram Type= 6, Freq= 0, CH_1, rank 0
6732 00:45:48.233657 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6733 00:45:48.233733 ==
6734 00:45:48.233792
6735 00:45:48.233846
6736 00:45:48.236926 TX Vref Scan disable
6737 00:45:48.237001 == TX Byte 0 ==
6738 00:45:48.244035 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6739 00:45:48.247128 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6740 00:45:48.247204 == TX Byte 1 ==
6741 00:45:48.250647 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6742 00:45:48.257372 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6743 00:45:48.257448 ==
6744 00:45:48.260576 Dram Type= 6, Freq= 0, CH_1, rank 0
6745 00:45:48.263690 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6746 00:45:48.263768 ==
6747 00:45:48.263827
6748 00:45:48.263882
6749 00:45:48.267501 TX Vref Scan disable
6750 00:45:48.267576 == TX Byte 0 ==
6751 00:45:48.273828 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6752 00:45:48.276989 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6753 00:45:48.277064 == TX Byte 1 ==
6754 00:45:48.283727 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6755 00:45:48.287008 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6756 00:45:48.287084
6757 00:45:48.287142 [DATLAT]
6758 00:45:48.290746 Freq=400, CH1 RK0
6759 00:45:48.290822
6760 00:45:48.290880 DATLAT Default: 0xf
6761 00:45:48.294145 0, 0xFFFF, sum = 0
6762 00:45:48.294222 1, 0xFFFF, sum = 0
6763 00:45:48.297315 2, 0xFFFF, sum = 0
6764 00:45:48.297391 3, 0xFFFF, sum = 0
6765 00:45:48.300369 4, 0xFFFF, sum = 0
6766 00:45:48.300446 5, 0xFFFF, sum = 0
6767 00:45:48.304011 6, 0xFFFF, sum = 0
6768 00:45:48.304112 7, 0xFFFF, sum = 0
6769 00:45:48.307125 8, 0xFFFF, sum = 0
6770 00:45:48.307202 9, 0xFFFF, sum = 0
6771 00:45:48.310300 10, 0xFFFF, sum = 0
6772 00:45:48.310377 11, 0xFFFF, sum = 0
6773 00:45:48.313978 12, 0xFFFF, sum = 0
6774 00:45:48.314054 13, 0x0, sum = 1
6775 00:45:48.317118 14, 0x0, sum = 2
6776 00:45:48.317195 15, 0x0, sum = 3
6777 00:45:48.320424 16, 0x0, sum = 4
6778 00:45:48.320500 best_step = 14
6779 00:45:48.320558
6780 00:45:48.320612 ==
6781 00:45:48.323708 Dram Type= 6, Freq= 0, CH_1, rank 0
6782 00:45:48.330489 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6783 00:45:48.330580 ==
6784 00:45:48.330664 RX Vref Scan: 1
6785 00:45:48.330747
6786 00:45:48.333426 RX Vref 0 -> 0, step: 1
6787 00:45:48.333503
6788 00:45:48.336976 RX Delay -311 -> 252, step: 8
6789 00:45:48.337052
6790 00:45:48.340135 Set Vref, RX VrefLevel [Byte0]: 55
6791 00:45:48.343523 [Byte1]: 50
6792 00:45:48.343598
6793 00:45:48.346909 Final RX Vref Byte 0 = 55 to rank0
6794 00:45:48.350083 Final RX Vref Byte 1 = 50 to rank0
6795 00:45:48.353415 Final RX Vref Byte 0 = 55 to rank1
6796 00:45:48.357048 Final RX Vref Byte 1 = 50 to rank1==
6797 00:45:48.360194 Dram Type= 6, Freq= 0, CH_1, rank 0
6798 00:45:48.363478 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6799 00:45:48.363554 ==
6800 00:45:48.366637 DQS Delay:
6801 00:45:48.366713 DQS0 = 32, DQS1 = 32
6802 00:45:48.370014 DQM Delay:
6803 00:45:48.370094 DQM0 = 13, DQM1 = 10
6804 00:45:48.373703 DQ Delay:
6805 00:45:48.373827 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6806 00:45:48.376842 DQ4 =16, DQ5 =24, DQ6 =20, DQ7 =12
6807 00:45:48.380276 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6808 00:45:48.383199 DQ12 =20, DQ13 =20, DQ14 =16, DQ15 =20
6809 00:45:48.383274
6810 00:45:48.383333
6811 00:45:48.393942 [DQSOSCAuto] RK0, (LSB)MR18= 0x95ce, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 391 ps
6812 00:45:48.397023 CH1 RK0: MR19=C0C, MR18=95CE
6813 00:45:48.400178 CH1_RK0: MR19=0xC0C, MR18=0x95CE, DQSOSC=384, MR23=63, INC=400, DEC=267
6814 00:45:48.403349 ==
6815 00:45:48.406988 Dram Type= 6, Freq= 0, CH_1, rank 1
6816 00:45:48.410199 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6817 00:45:48.410275 ==
6818 00:45:48.413240 [Gating] SW mode calibration
6819 00:45:48.419897 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6820 00:45:48.423738 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6821 00:45:48.430233 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6822 00:45:48.433370 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6823 00:45:48.436685 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6824 00:45:48.443736 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6825 00:45:48.446608 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6826 00:45:48.450353 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6827 00:45:48.456734 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6828 00:45:48.460038 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6829 00:45:48.463264 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6830 00:45:48.466502 Total UI for P1: 0, mck2ui 16
6831 00:45:48.470202 best dqsien dly found for B0: ( 0, 14, 24)
6832 00:45:48.473115 Total UI for P1: 0, mck2ui 16
6833 00:45:48.476516 best dqsien dly found for B1: ( 0, 14, 24)
6834 00:45:48.479738 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6835 00:45:48.483628 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6836 00:45:48.483703
6837 00:45:48.486868 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6838 00:45:48.493374 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6839 00:45:48.493450 [Gating] SW calibration Done
6840 00:45:48.496413 ==
6841 00:45:48.496503 Dram Type= 6, Freq= 0, CH_1, rank 1
6842 00:45:48.502938 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6843 00:45:48.503014 ==
6844 00:45:48.503072 RX Vref Scan: 0
6845 00:45:48.503126
6846 00:45:48.506784 RX Vref 0 -> 0, step: 1
6847 00:45:48.506860
6848 00:45:48.510011 RX Delay -410 -> 252, step: 16
6849 00:45:48.513650 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6850 00:45:48.516851 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6851 00:45:48.523008 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6852 00:45:48.526617 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6853 00:45:48.529817 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6854 00:45:48.533139 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6855 00:45:48.540141 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6856 00:45:48.543483 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6857 00:45:48.546538 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6858 00:45:48.549746 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6859 00:45:48.556550 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6860 00:45:48.559659 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6861 00:45:48.562880 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6862 00:45:48.566474 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6863 00:45:48.573355 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6864 00:45:48.576596 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6865 00:45:48.576664 ==
6866 00:45:48.579718 Dram Type= 6, Freq= 0, CH_1, rank 1
6867 00:45:48.582978 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6868 00:45:48.583053 ==
6869 00:45:48.586450 DQS Delay:
6870 00:45:48.586548 DQS0 = 35, DQS1 = 35
6871 00:45:48.589847 DQM Delay:
6872 00:45:48.589922 DQM0 = 18, DQM1 = 13
6873 00:45:48.589981 DQ Delay:
6874 00:45:48.593329 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6875 00:45:48.596440 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6876 00:45:48.599638 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6877 00:45:48.602968 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6878 00:45:48.603043
6879 00:45:48.603102
6880 00:45:48.603155 ==
6881 00:45:48.606613 Dram Type= 6, Freq= 0, CH_1, rank 1
6882 00:45:48.613009 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6883 00:45:48.613099 ==
6884 00:45:48.613172
6885 00:45:48.613226
6886 00:45:48.613278 TX Vref Scan disable
6887 00:45:48.616261 == TX Byte 0 ==
6888 00:45:48.619785 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6889 00:45:48.622855 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6890 00:45:48.626436 == TX Byte 1 ==
6891 00:45:48.629341 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6892 00:45:48.632848 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6893 00:45:48.632924 ==
6894 00:45:48.636524 Dram Type= 6, Freq= 0, CH_1, rank 1
6895 00:45:48.643001 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6896 00:45:48.643077 ==
6897 00:45:48.643137
6898 00:45:48.643190
6899 00:45:48.643241 TX Vref Scan disable
6900 00:45:48.646183 == TX Byte 0 ==
6901 00:45:48.649504 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6902 00:45:48.652696 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6903 00:45:48.656003 == TX Byte 1 ==
6904 00:45:48.659724 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6905 00:45:48.662717 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6906 00:45:48.662822
6907 00:45:48.665915 [DATLAT]
6908 00:45:48.666004 Freq=400, CH1 RK1
6909 00:45:48.666063
6910 00:45:48.669145 DATLAT Default: 0xe
6911 00:45:48.669221 0, 0xFFFF, sum = 0
6912 00:45:48.672432 1, 0xFFFF, sum = 0
6913 00:45:48.672509 2, 0xFFFF, sum = 0
6914 00:45:48.676082 3, 0xFFFF, sum = 0
6915 00:45:48.676174 4, 0xFFFF, sum = 0
6916 00:45:48.679531 5, 0xFFFF, sum = 0
6917 00:45:48.679637 6, 0xFFFF, sum = 0
6918 00:45:48.682897 7, 0xFFFF, sum = 0
6919 00:45:48.682974 8, 0xFFFF, sum = 0
6920 00:45:48.686325 9, 0xFFFF, sum = 0
6921 00:45:48.686402 10, 0xFFFF, sum = 0
6922 00:45:48.689435 11, 0xFFFF, sum = 0
6923 00:45:48.692618 12, 0xFFFF, sum = 0
6924 00:45:48.692695 13, 0x0, sum = 1
6925 00:45:48.692754 14, 0x0, sum = 2
6926 00:45:48.696322 15, 0x0, sum = 3
6927 00:45:48.696399 16, 0x0, sum = 4
6928 00:45:48.699192 best_step = 14
6929 00:45:48.699267
6930 00:45:48.699326 ==
6931 00:45:48.702936 Dram Type= 6, Freq= 0, CH_1, rank 1
6932 00:45:48.706244 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6933 00:45:48.706349 ==
6934 00:45:48.709440 RX Vref Scan: 0
6935 00:45:48.709514
6936 00:45:48.709615 RX Vref 0 -> 0, step: 1
6937 00:45:48.709672
6938 00:45:48.712564 RX Delay -311 -> 252, step: 8
6939 00:45:48.721198 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
6940 00:45:48.724065 iDelay=217, Bit 1, Center -24 (-247 ~ 200) 448
6941 00:45:48.727676 iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440
6942 00:45:48.730950 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6943 00:45:48.737826 iDelay=217, Bit 4, Center -20 (-239 ~ 200) 440
6944 00:45:48.741359 iDelay=217, Bit 5, Center -8 (-231 ~ 216) 448
6945 00:45:48.744478 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6946 00:45:48.747762 iDelay=217, Bit 7, Center -16 (-239 ~ 208) 448
6947 00:45:48.754129 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6948 00:45:48.757417 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6949 00:45:48.760639 iDelay=217, Bit 10, Center -20 (-247 ~ 208) 456
6950 00:45:48.764259 iDelay=217, Bit 11, Center -24 (-247 ~ 200) 448
6951 00:45:48.770570 iDelay=217, Bit 12, Center -12 (-239 ~ 216) 456
6952 00:45:48.773876 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
6953 00:45:48.777136 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6954 00:45:48.784109 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
6955 00:45:48.784180 ==
6956 00:45:48.787379 Dram Type= 6, Freq= 0, CH_1, rank 1
6957 00:45:48.790268 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6958 00:45:48.790333 ==
6959 00:45:48.790398 DQS Delay:
6960 00:45:48.793745 DQS0 = 28, DQS1 = 36
6961 00:45:48.793809 DQM Delay:
6962 00:45:48.797155 DQM0 = 10, DQM1 = 15
6963 00:45:48.797221 DQ Delay:
6964 00:45:48.800214 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =4
6965 00:45:48.804194 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =12
6966 00:45:48.806717 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =12
6967 00:45:48.810378 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =24
6968 00:45:48.810443
6969 00:45:48.810498
6970 00:45:48.817036 [DQSOSCAuto] RK1, (LSB)MR18= 0xc959, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 384 ps
6971 00:45:48.820232 CH1 RK1: MR19=C0C, MR18=C959
6972 00:45:48.827132 CH1_RK1: MR19=0xC0C, MR18=0xC959, DQSOSC=384, MR23=63, INC=400, DEC=267
6973 00:45:48.830010 [RxdqsGatingPostProcess] freq 400
6974 00:45:48.836919 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6975 00:45:48.836997 best DQS0 dly(2T, 0.5T) = (0, 10)
6976 00:45:48.840093 best DQS1 dly(2T, 0.5T) = (0, 10)
6977 00:45:48.843309 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6978 00:45:48.846922 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6979 00:45:48.850137 best DQS0 dly(2T, 0.5T) = (0, 10)
6980 00:45:48.853870 best DQS1 dly(2T, 0.5T) = (0, 10)
6981 00:45:48.857326 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6982 00:45:48.860049 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6983 00:45:48.863719 Pre-setting of DQS Precalculation
6984 00:45:48.870114 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6985 00:45:48.876777 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6986 00:45:48.883199 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6987 00:45:48.883268
6988 00:45:48.883324
6989 00:45:48.887131 [Calibration Summary] 800 Mbps
6990 00:45:48.887196 CH 0, Rank 0
6991 00:45:48.890336 SW Impedance : PASS
6992 00:45:48.890399 DUTY Scan : NO K
6993 00:45:48.893581 ZQ Calibration : PASS
6994 00:45:48.896981 Jitter Meter : NO K
6995 00:45:48.897044 CBT Training : PASS
6996 00:45:48.899945 Write leveling : PASS
6997 00:45:48.903514 RX DQS gating : PASS
6998 00:45:48.903577 RX DQ/DQS(RDDQC) : PASS
6999 00:45:48.906856 TX DQ/DQS : PASS
7000 00:45:48.910293 RX DATLAT : PASS
7001 00:45:48.910383 RX DQ/DQS(Engine): PASS
7002 00:45:48.913465 TX OE : NO K
7003 00:45:48.913526 All Pass.
7004 00:45:48.913631
7005 00:45:48.916708 CH 0, Rank 1
7006 00:45:48.916770 SW Impedance : PASS
7007 00:45:48.919984 DUTY Scan : NO K
7008 00:45:48.923186 ZQ Calibration : PASS
7009 00:45:48.923253 Jitter Meter : NO K
7010 00:45:48.926873 CBT Training : PASS
7011 00:45:48.929975 Write leveling : NO K
7012 00:45:48.930041 RX DQS gating : PASS
7013 00:45:48.933422 RX DQ/DQS(RDDQC) : PASS
7014 00:45:48.933488 TX DQ/DQS : PASS
7015 00:45:48.936729 RX DATLAT : PASS
7016 00:45:48.940236 RX DQ/DQS(Engine): PASS
7017 00:45:48.940302 TX OE : NO K
7018 00:45:48.943511 All Pass.
7019 00:45:48.943574
7020 00:45:48.943634 CH 1, Rank 0
7021 00:45:48.946544 SW Impedance : PASS
7022 00:45:48.946614 DUTY Scan : NO K
7023 00:45:48.950158 ZQ Calibration : PASS
7024 00:45:48.953093 Jitter Meter : NO K
7025 00:45:48.953162 CBT Training : PASS
7026 00:45:48.956681 Write leveling : PASS
7027 00:45:48.959893 RX DQS gating : PASS
7028 00:45:48.959960 RX DQ/DQS(RDDQC) : PASS
7029 00:45:48.963073 TX DQ/DQS : PASS
7030 00:45:48.966488 RX DATLAT : PASS
7031 00:45:48.966550 RX DQ/DQS(Engine): PASS
7032 00:45:48.969947 TX OE : NO K
7033 00:45:48.970013 All Pass.
7034 00:45:48.970070
7035 00:45:48.973531 CH 1, Rank 1
7036 00:45:48.973619 SW Impedance : PASS
7037 00:45:48.976682 DUTY Scan : NO K
7038 00:45:48.979676 ZQ Calibration : PASS
7039 00:45:48.979743 Jitter Meter : NO K
7040 00:45:48.983302 CBT Training : PASS
7041 00:45:48.983369 Write leveling : NO K
7042 00:45:48.986547 RX DQS gating : PASS
7043 00:45:48.989832 RX DQ/DQS(RDDQC) : PASS
7044 00:45:48.989897 TX DQ/DQS : PASS
7045 00:45:48.993074 RX DATLAT : PASS
7046 00:45:48.996961 RX DQ/DQS(Engine): PASS
7047 00:45:48.997028 TX OE : NO K
7048 00:45:49.000330 All Pass.
7049 00:45:49.000391
7050 00:45:49.000444 DramC Write-DBI off
7051 00:45:49.003549 PER_BANK_REFRESH: Hybrid Mode
7052 00:45:49.003613 TX_TRACKING: ON
7053 00:45:49.013098 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7054 00:45:49.016729 [FAST_K] Save calibration result to emmc
7055 00:45:49.019512 dramc_set_vcore_voltage set vcore to 725000
7056 00:45:49.023156 Read voltage for 1600, 0
7057 00:45:49.023229 Vio18 = 0
7058 00:45:49.026297 Vcore = 725000
7059 00:45:49.026366 Vdram = 0
7060 00:45:49.026423 Vddq = 0
7061 00:45:49.030100 Vmddr = 0
7062 00:45:49.033442 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7063 00:45:49.039868 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7064 00:45:49.039936 MEM_TYPE=3, freq_sel=13
7065 00:45:49.043023 sv_algorithm_assistance_LP4_3733
7066 00:45:49.049411 ============ PULL DRAM RESETB DOWN ============
7067 00:45:49.053031 ========== PULL DRAM RESETB DOWN end =========
7068 00:45:49.056026 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7069 00:45:49.060203 ===================================
7070 00:45:49.062997 LPDDR4 DRAM CONFIGURATION
7071 00:45:49.066300 ===================================
7072 00:45:49.066369 EX_ROW_EN[0] = 0x0
7073 00:45:49.069781 EX_ROW_EN[1] = 0x0
7074 00:45:49.073074 LP4Y_EN = 0x0
7075 00:45:49.073147 WORK_FSP = 0x1
7076 00:45:49.076281 WL = 0x5
7077 00:45:49.076351 RL = 0x5
7078 00:45:49.079864 BL = 0x2
7079 00:45:49.079932 RPST = 0x0
7080 00:45:49.082757 RD_PRE = 0x0
7081 00:45:49.082821 WR_PRE = 0x1
7082 00:45:49.086682 WR_PST = 0x1
7083 00:45:49.086778 DBI_WR = 0x0
7084 00:45:49.089530 DBI_RD = 0x0
7085 00:45:49.089611 OTF = 0x1
7086 00:45:49.092694 ===================================
7087 00:45:49.095987 ===================================
7088 00:45:49.099972 ANA top config
7089 00:45:49.102612 ===================================
7090 00:45:49.102683 DLL_ASYNC_EN = 0
7091 00:45:49.106611 ALL_SLAVE_EN = 0
7092 00:45:49.109868 NEW_RANK_MODE = 1
7093 00:45:49.113002 DLL_IDLE_MODE = 1
7094 00:45:49.116136 LP45_APHY_COMB_EN = 1
7095 00:45:49.116206 TX_ODT_DIS = 0
7096 00:45:49.119923 NEW_8X_MODE = 1
7097 00:45:49.123085 ===================================
7098 00:45:49.126117 ===================================
7099 00:45:49.129708 data_rate = 3200
7100 00:45:49.132923 CKR = 1
7101 00:45:49.136254 DQ_P2S_RATIO = 8
7102 00:45:49.139357 ===================================
7103 00:45:49.139429 CA_P2S_RATIO = 8
7104 00:45:49.143167 DQ_CA_OPEN = 0
7105 00:45:49.146385 DQ_SEMI_OPEN = 0
7106 00:45:49.149633 CA_SEMI_OPEN = 0
7107 00:45:49.152746 CA_FULL_RATE = 0
7108 00:45:49.156572 DQ_CKDIV4_EN = 0
7109 00:45:49.156647 CA_CKDIV4_EN = 0
7110 00:45:49.159726 CA_PREDIV_EN = 0
7111 00:45:49.162840 PH8_DLY = 12
7112 00:45:49.166588 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7113 00:45:49.169670 DQ_AAMCK_DIV = 4
7114 00:45:49.173087 CA_AAMCK_DIV = 4
7115 00:45:49.173180 CA_ADMCK_DIV = 4
7116 00:45:49.176304 DQ_TRACK_CA_EN = 0
7117 00:45:49.179677 CA_PICK = 1600
7118 00:45:49.183198 CA_MCKIO = 1600
7119 00:45:49.186729 MCKIO_SEMI = 0
7120 00:45:49.189897 PLL_FREQ = 3068
7121 00:45:49.192953 DQ_UI_PI_RATIO = 32
7122 00:45:49.193047 CA_UI_PI_RATIO = 0
7123 00:45:49.196506 ===================================
7124 00:45:49.199899 ===================================
7125 00:45:49.202770 memory_type:LPDDR4
7126 00:45:49.206304 GP_NUM : 10
7127 00:45:49.206373 SRAM_EN : 1
7128 00:45:49.209977 MD32_EN : 0
7129 00:45:49.213241 ===================================
7130 00:45:49.216520 [ANA_INIT] >>>>>>>>>>>>>>
7131 00:45:49.219778 <<<<<< [CONFIGURE PHASE]: ANA_TX
7132 00:45:49.222875 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7133 00:45:49.226059 ===================================
7134 00:45:49.226135 data_rate = 3200,PCW = 0X7600
7135 00:45:49.229286 ===================================
7136 00:45:49.233136 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7137 00:45:49.239135 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7138 00:45:49.245982 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7139 00:45:49.249291 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7140 00:45:49.252475 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7141 00:45:49.255887 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7142 00:45:49.259025 [ANA_INIT] flow start
7143 00:45:49.259099 [ANA_INIT] PLL >>>>>>>>
7144 00:45:49.262731 [ANA_INIT] PLL <<<<<<<<
7145 00:45:49.265750 [ANA_INIT] MIDPI >>>>>>>>
7146 00:45:49.269127 [ANA_INIT] MIDPI <<<<<<<<
7147 00:45:49.269194 [ANA_INIT] DLL >>>>>>>>
7148 00:45:49.272199 [ANA_INIT] DLL <<<<<<<<
7149 00:45:49.275828 [ANA_INIT] flow end
7150 00:45:49.278850 ============ LP4 DIFF to SE enter ============
7151 00:45:49.282639 ============ LP4 DIFF to SE exit ============
7152 00:45:49.285931 [ANA_INIT] <<<<<<<<<<<<<
7153 00:45:49.288974 [Flow] Enable top DCM control >>>>>
7154 00:45:49.292380 [Flow] Enable top DCM control <<<<<
7155 00:45:49.295650 Enable DLL master slave shuffle
7156 00:45:49.299463 ==============================================================
7157 00:45:49.302497 Gating Mode config
7158 00:45:49.305752 ==============================================================
7159 00:45:49.308986 Config description:
7160 00:45:49.318843 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7161 00:45:49.325702 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7162 00:45:49.329683 SELPH_MODE 0: By rank 1: By Phase
7163 00:45:49.335941 ==============================================================
7164 00:45:49.339188 GAT_TRACK_EN = 1
7165 00:45:49.342429 RX_GATING_MODE = 2
7166 00:45:49.345656 RX_GATING_TRACK_MODE = 2
7167 00:45:49.348829 SELPH_MODE = 1
7168 00:45:49.352057 PICG_EARLY_EN = 1
7169 00:45:49.352133 VALID_LAT_VALUE = 1
7170 00:45:49.358795 ==============================================================
7171 00:45:49.362293 Enter into Gating configuration >>>>
7172 00:45:49.365595 Exit from Gating configuration <<<<
7173 00:45:49.368857 Enter into DVFS_PRE_config >>>>>
7174 00:45:49.379320 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7175 00:45:49.382403 Exit from DVFS_PRE_config <<<<<
7176 00:45:49.385767 Enter into PICG configuration >>>>
7177 00:45:49.388843 Exit from PICG configuration <<<<
7178 00:45:49.392748 [RX_INPUT] configuration >>>>>
7179 00:45:49.395934 [RX_INPUT] configuration <<<<<
7180 00:45:49.399152 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7181 00:45:49.405471 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7182 00:45:49.412146 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7183 00:45:49.418622 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7184 00:45:49.425715 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7185 00:45:49.432402 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7186 00:45:49.435576 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7187 00:45:49.439137 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7188 00:45:49.442332 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7189 00:45:49.445287 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7190 00:45:49.452445 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7191 00:45:49.455586 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7192 00:45:49.458723 ===================================
7193 00:45:49.461965 LPDDR4 DRAM CONFIGURATION
7194 00:45:49.465126 ===================================
7195 00:45:49.465202 EX_ROW_EN[0] = 0x0
7196 00:45:49.468916 EX_ROW_EN[1] = 0x0
7197 00:45:49.468991 LP4Y_EN = 0x0
7198 00:45:49.472107 WORK_FSP = 0x1
7199 00:45:49.472181 WL = 0x5
7200 00:45:49.475313 RL = 0x5
7201 00:45:49.475388 BL = 0x2
7202 00:45:49.478931 RPST = 0x0
7203 00:45:49.481834 RD_PRE = 0x0
7204 00:45:49.481909 WR_PRE = 0x1
7205 00:45:49.485275 WR_PST = 0x1
7206 00:45:49.485376 DBI_WR = 0x0
7207 00:45:49.488380 DBI_RD = 0x0
7208 00:45:49.488473 OTF = 0x1
7209 00:45:49.491577 ===================================
7210 00:45:49.495189 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7211 00:45:49.498383 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7212 00:45:49.505376 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7213 00:45:49.508497 ===================================
7214 00:45:49.512051 LPDDR4 DRAM CONFIGURATION
7215 00:45:49.515498 ===================================
7216 00:45:49.515566 EX_ROW_EN[0] = 0x10
7217 00:45:49.518610 EX_ROW_EN[1] = 0x0
7218 00:45:49.518697 LP4Y_EN = 0x0
7219 00:45:49.522222 WORK_FSP = 0x1
7220 00:45:49.522293 WL = 0x5
7221 00:45:49.525303 RL = 0x5
7222 00:45:49.525398 BL = 0x2
7223 00:45:49.528398 RPST = 0x0
7224 00:45:49.528466 RD_PRE = 0x0
7225 00:45:49.531622 WR_PRE = 0x1
7226 00:45:49.531697 WR_PST = 0x1
7227 00:45:49.535424 DBI_WR = 0x0
7228 00:45:49.535517 DBI_RD = 0x0
7229 00:45:49.538407 OTF = 0x1
7230 00:45:49.542075 ===================================
7231 00:45:49.548136 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7232 00:45:49.548228 ==
7233 00:45:49.552207 Dram Type= 6, Freq= 0, CH_0, rank 0
7234 00:45:49.554955 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7235 00:45:49.555060 ==
7236 00:45:49.558256 [Duty_Offset_Calibration]
7237 00:45:49.558325 B0:2 B1:1 CA:1
7238 00:45:49.558382
7239 00:45:49.561578 [DutyScan_Calibration_Flow] k_type=0
7240 00:45:49.572836
7241 00:45:49.572911 ==CLK 0==
7242 00:45:49.576690 Final CLK duty delay cell = 0
7243 00:45:49.579890 [0] MAX Duty = 5187%(X100), DQS PI = 22
7244 00:45:49.583132 [0] MIN Duty = 4876%(X100), DQS PI = 48
7245 00:45:49.583207 [0] AVG Duty = 5031%(X100)
7246 00:45:49.586251
7247 00:45:49.589424 CH0 CLK Duty spec in!! Max-Min= 311%
7248 00:45:49.592715 [DutyScan_Calibration_Flow] ====Done====
7249 00:45:49.592829
7250 00:45:49.595855 [DutyScan_Calibration_Flow] k_type=1
7251 00:45:49.611813
7252 00:45:49.611903 ==DQS 0 ==
7253 00:45:49.615249 Final DQS duty delay cell = -4
7254 00:45:49.619032 [-4] MAX Duty = 5125%(X100), DQS PI = 26
7255 00:45:49.622333 [-4] MIN Duty = 4657%(X100), DQS PI = 0
7256 00:45:49.625478 [-4] AVG Duty = 4891%(X100)
7257 00:45:49.625606
7258 00:45:49.625669 ==DQS 1 ==
7259 00:45:49.628634 Final DQS duty delay cell = 0
7260 00:45:49.631926 [0] MAX Duty = 5187%(X100), DQS PI = 20
7261 00:45:49.635444 [0] MIN Duty = 5031%(X100), DQS PI = 52
7262 00:45:49.638601 [0] AVG Duty = 5109%(X100)
7263 00:45:49.638686
7264 00:45:49.642244 CH0 DQS 0 Duty spec in!! Max-Min= 468%
7265 00:45:49.642309
7266 00:45:49.645285 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7267 00:45:49.648419 [DutyScan_Calibration_Flow] ====Done====
7268 00:45:49.648527
7269 00:45:49.651708 [DutyScan_Calibration_Flow] k_type=3
7270 00:45:49.669357
7271 00:45:49.669462 ==DQM 0 ==
7272 00:45:49.672614 Final DQM duty delay cell = 0
7273 00:45:49.676381 [0] MAX Duty = 5187%(X100), DQS PI = 32
7274 00:45:49.679486 [0] MIN Duty = 4876%(X100), DQS PI = 60
7275 00:45:49.682766 [0] AVG Duty = 5031%(X100)
7276 00:45:49.682859
7277 00:45:49.682945 ==DQM 1 ==
7278 00:45:49.686016 Final DQM duty delay cell = 0
7279 00:45:49.689205 [0] MAX Duty = 5187%(X100), DQS PI = 4
7280 00:45:49.693076 [0] MIN Duty = 5031%(X100), DQS PI = 48
7281 00:45:49.695756 [0] AVG Duty = 5109%(X100)
7282 00:45:49.695824
7283 00:45:49.699524 CH0 DQM 0 Duty spec in!! Max-Min= 311%
7284 00:45:49.699594
7285 00:45:49.702720 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7286 00:45:49.706118 [DutyScan_Calibration_Flow] ====Done====
7287 00:45:49.706206
7288 00:45:49.709273 [DutyScan_Calibration_Flow] k_type=2
7289 00:45:49.726708
7290 00:45:49.726784 ==DQ 0 ==
7291 00:45:49.730243 Final DQ duty delay cell = 0
7292 00:45:49.733506 [0] MAX Duty = 5062%(X100), DQS PI = 26
7293 00:45:49.737007 [0] MIN Duty = 4907%(X100), DQS PI = 0
7294 00:45:49.737082 [0] AVG Duty = 4984%(X100)
7295 00:45:49.737142
7296 00:45:49.740482 ==DQ 1 ==
7297 00:45:49.740571 Final DQ duty delay cell = 0
7298 00:45:49.746750 [0] MAX Duty = 5125%(X100), DQS PI = 6
7299 00:45:49.750162 [0] MIN Duty = 4907%(X100), DQS PI = 34
7300 00:45:49.750254 [0] AVG Duty = 5016%(X100)
7301 00:45:49.750407
7302 00:45:49.753408 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7303 00:45:49.753508
7304 00:45:49.756832 CH0 DQ 1 Duty spec in!! Max-Min= 218%
7305 00:45:49.763888 [DutyScan_Calibration_Flow] ====Done====
7306 00:45:49.763964 ==
7307 00:45:49.767057 Dram Type= 6, Freq= 0, CH_1, rank 0
7308 00:45:49.770302 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7309 00:45:49.770378 ==
7310 00:45:49.773586 [Duty_Offset_Calibration]
7311 00:45:49.773662 B0:1 B1:0 CA:0
7312 00:45:49.773721
7313 00:45:49.776525 [DutyScan_Calibration_Flow] k_type=0
7314 00:45:49.785826
7315 00:45:49.785929 ==CLK 0==
7316 00:45:49.789276 Final CLK duty delay cell = -4
7317 00:45:49.792444 [-4] MAX Duty = 4969%(X100), DQS PI = 22
7318 00:45:49.796280 [-4] MIN Duty = 4844%(X100), DQS PI = 2
7319 00:45:49.799512 [-4] AVG Duty = 4906%(X100)
7320 00:45:49.799587
7321 00:45:49.802798 CH1 CLK Duty spec in!! Max-Min= 125%
7322 00:45:49.806033 [DutyScan_Calibration_Flow] ====Done====
7323 00:45:49.806108
7324 00:45:49.809200 [DutyScan_Calibration_Flow] k_type=1
7325 00:45:49.826278
7326 00:45:49.826375 ==DQS 0 ==
7327 00:45:49.829499 Final DQS duty delay cell = 0
7328 00:45:49.832638 [0] MAX Duty = 5062%(X100), DQS PI = 8
7329 00:45:49.835682 [0] MIN Duty = 4844%(X100), DQS PI = 0
7330 00:45:49.835757 [0] AVG Duty = 4953%(X100)
7331 00:45:49.839403
7332 00:45:49.839477 ==DQS 1 ==
7333 00:45:49.842925 Final DQS duty delay cell = 0
7334 00:45:49.846077 [0] MAX Duty = 5249%(X100), DQS PI = 16
7335 00:45:49.849382 [0] MIN Duty = 4938%(X100), DQS PI = 8
7336 00:45:49.849457 [0] AVG Duty = 5093%(X100)
7337 00:45:49.849516
7338 00:45:49.855877 CH1 DQS 0 Duty spec in!! Max-Min= 218%
7339 00:45:49.855976
7340 00:45:49.858970 CH1 DQS 1 Duty spec in!! Max-Min= 311%
7341 00:45:49.862530 [DutyScan_Calibration_Flow] ====Done====
7342 00:45:49.862603
7343 00:45:49.865519 [DutyScan_Calibration_Flow] k_type=3
7344 00:45:49.882635
7345 00:45:49.882712 ==DQM 0 ==
7346 00:45:49.885878 Final DQM duty delay cell = 0
7347 00:45:49.889124 [0] MAX Duty = 5187%(X100), DQS PI = 10
7348 00:45:49.892879 [0] MIN Duty = 4938%(X100), DQS PI = 48
7349 00:45:49.895787 [0] AVG Duty = 5062%(X100)
7350 00:45:49.895857
7351 00:45:49.895957 ==DQM 1 ==
7352 00:45:49.899252 Final DQM duty delay cell = 0
7353 00:45:49.902895 [0] MAX Duty = 5093%(X100), DQS PI = 16
7354 00:45:49.906077 [0] MIN Duty = 4907%(X100), DQS PI = 34
7355 00:45:49.909211 [0] AVG Duty = 5000%(X100)
7356 00:45:49.909309
7357 00:45:49.912543 CH1 DQM 0 Duty spec in!! Max-Min= 249%
7358 00:45:49.912621
7359 00:45:49.916000 CH1 DQM 1 Duty spec in!! Max-Min= 186%
7360 00:45:49.919409 [DutyScan_Calibration_Flow] ====Done====
7361 00:45:49.919508
7362 00:45:49.922536 [DutyScan_Calibration_Flow] k_type=2
7363 00:45:49.939090
7364 00:45:49.939165 ==DQ 0 ==
7365 00:45:49.942479 Final DQ duty delay cell = -4
7366 00:45:49.945650 [-4] MAX Duty = 5031%(X100), DQS PI = 10
7367 00:45:49.948710 [-4] MIN Duty = 4875%(X100), DQS PI = 46
7368 00:45:49.952417 [-4] AVG Duty = 4953%(X100)
7369 00:45:49.952492
7370 00:45:49.952550 ==DQ 1 ==
7371 00:45:49.955637 Final DQ duty delay cell = 0
7372 00:45:49.958853 [0] MAX Duty = 5156%(X100), DQS PI = 18
7373 00:45:49.961955 [0] MIN Duty = 4938%(X100), DQS PI = 8
7374 00:45:49.962031 [0] AVG Duty = 5047%(X100)
7375 00:45:49.965705
7376 00:45:49.968800 CH1 DQ 0 Duty spec in!! Max-Min= 156%
7377 00:45:49.968898
7378 00:45:49.971958 CH1 DQ 1 Duty spec in!! Max-Min= 218%
7379 00:45:49.975171 [DutyScan_Calibration_Flow] ====Done====
7380 00:45:49.978915 nWR fixed to 30
7381 00:45:49.979007 [ModeRegInit_LP4] CH0 RK0
7382 00:45:49.981953 [ModeRegInit_LP4] CH0 RK1
7383 00:45:49.985740 [ModeRegInit_LP4] CH1 RK0
7384 00:45:49.988884 [ModeRegInit_LP4] CH1 RK1
7385 00:45:49.988951 match AC timing 5
7386 00:45:49.995326 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7387 00:45:49.998818 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7388 00:45:50.002077 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7389 00:45:50.008837 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7390 00:45:50.012307 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7391 00:45:50.012375 [MiockJmeterHQA]
7392 00:45:50.012430
7393 00:45:50.015256 [DramcMiockJmeter] u1RxGatingPI = 0
7394 00:45:50.018867 0 : 4366, 4137
7395 00:45:50.018944 4 : 4253, 4027
7396 00:45:50.021773 8 : 4365, 4140
7397 00:45:50.021849 12 : 4363, 4137
7398 00:45:50.021909 16 : 4250, 4024
7399 00:45:50.025335 20 : 4253, 4026
7400 00:45:50.025411 24 : 4252, 4027
7401 00:45:50.028474 28 : 4255, 4029
7402 00:45:50.028551 32 : 4252, 4027
7403 00:45:50.031716 36 : 4253, 4027
7404 00:45:50.031792 40 : 4363, 4137
7405 00:45:50.031870 44 : 4252, 4027
7406 00:45:50.035089 48 : 4253, 4026
7407 00:45:50.035191 52 : 4252, 4027
7408 00:45:50.038903 56 : 4252, 4027
7409 00:45:50.038980 60 : 4253, 4027
7410 00:45:50.041968 64 : 4363, 4139
7411 00:45:50.042044 68 : 4360, 4138
7412 00:45:50.045282 72 : 4250, 4027
7413 00:45:50.045358 76 : 4252, 4027
7414 00:45:50.045435 80 : 4250, 4027
7415 00:45:50.048880 84 : 4250, 4027
7416 00:45:50.048981 88 : 4250, 54
7417 00:45:50.051955 92 : 4361, 0
7418 00:45:50.052041 96 : 4252, 0
7419 00:45:50.052102 100 : 4250, 0
7420 00:45:50.054979 104 : 4250, 0
7421 00:45:50.055056 108 : 4253, 0
7422 00:45:50.058586 112 : 4360, 0
7423 00:45:50.058664 116 : 4360, 0
7424 00:45:50.058723 120 : 4255, 0
7425 00:45:50.061848 124 : 4360, 0
7426 00:45:50.061949 128 : 4361, 0
7427 00:45:50.065007 132 : 4250, 0
7428 00:45:50.065074 136 : 4252, 0
7429 00:45:50.065166 140 : 4250, 0
7430 00:45:50.068153 144 : 4250, 0
7431 00:45:50.068243 148 : 4360, 0
7432 00:45:50.068326 152 : 4250, 0
7433 00:45:50.071873 156 : 4250, 0
7434 00:45:50.071937 160 : 4255, 0
7435 00:45:50.075051 164 : 4360, 0
7436 00:45:50.075117 168 : 4361, 0
7437 00:45:50.075174 172 : 4250, 0
7438 00:45:50.078411 176 : 4360, 0
7439 00:45:50.078498 180 : 4249, 0
7440 00:45:50.081446 184 : 4250, 0
7441 00:45:50.081554 188 : 4249, 0
7442 00:45:50.081645 192 : 4250, 0
7443 00:45:50.085266 196 : 4249, 0
7444 00:45:50.085342 200 : 4250, 0
7445 00:45:50.088409 204 : 4250, 1311
7446 00:45:50.088486 208 : 4252, 4027
7447 00:45:50.091637 212 : 4250, 4027
7448 00:45:50.091713 216 : 4250, 4027
7449 00:45:50.091774 220 : 4249, 4027
7450 00:45:50.094847 224 : 4250, 4027
7451 00:45:50.094923 228 : 4250, 4027
7452 00:45:50.098486 232 : 4250, 4027
7453 00:45:50.098568 236 : 4250, 4027
7454 00:45:50.102138 240 : 4360, 4137
7455 00:45:50.102215 244 : 4361, 4137
7456 00:45:50.105052 248 : 4250, 4027
7457 00:45:50.105153 252 : 4250, 4027
7458 00:45:50.108113 256 : 4360, 4137
7459 00:45:50.108205 260 : 4250, 4027
7460 00:45:50.111568 264 : 4250, 4026
7461 00:45:50.111644 268 : 4250, 4027
7462 00:45:50.115215 272 : 4249, 4027
7463 00:45:50.115291 276 : 4250, 4027
7464 00:45:50.115350 280 : 4250, 4027
7465 00:45:50.118464 284 : 4250, 4027
7466 00:45:50.118540 288 : 4250, 4027
7467 00:45:50.121524 292 : 4360, 4137
7468 00:45:50.121646 296 : 4360, 4138
7469 00:45:50.124828 300 : 4250, 4027
7470 00:45:50.124905 304 : 4250, 4027
7471 00:45:50.128736 308 : 4360, 4102
7472 00:45:50.128815 312 : 4250, 2349
7473 00:45:50.131771 316 : 4250, 3
7474 00:45:50.131866
7475 00:45:50.131938 MIOCK jitter meter ch=0
7476 00:45:50.131991
7477 00:45:50.134716 1T = (316-88) = 228 dly cells
7478 00:45:50.141220 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 285/100 ps
7479 00:45:50.141313 ==
7480 00:45:50.145058 Dram Type= 6, Freq= 0, CH_0, rank 0
7481 00:45:50.148385 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7482 00:45:50.148460 ==
7483 00:45:50.154974 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7484 00:45:50.158214 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7485 00:45:50.161225 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7486 00:45:50.168178 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7487 00:45:50.177963 [CA 0] Center 43 (13~74) winsize 62
7488 00:45:50.181093 [CA 1] Center 43 (13~74) winsize 62
7489 00:45:50.184745 [CA 2] Center 38 (9~68) winsize 60
7490 00:45:50.187953 [CA 3] Center 38 (8~68) winsize 61
7491 00:45:50.191128 [CA 4] Center 36 (7~66) winsize 60
7492 00:45:50.194374 [CA 5] Center 36 (7~65) winsize 59
7493 00:45:50.194450
7494 00:45:50.198094 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7495 00:45:50.198169
7496 00:45:50.201181 [CATrainingPosCal] consider 1 rank data
7497 00:45:50.204393 u2DelayCellTimex100 = 285/100 ps
7498 00:45:50.207702 CA0 delay=43 (13~74),Diff = 7 PI (23 cell)
7499 00:45:50.214422 CA1 delay=43 (13~74),Diff = 7 PI (23 cell)
7500 00:45:50.217777 CA2 delay=38 (9~68),Diff = 2 PI (6 cell)
7501 00:45:50.221235 CA3 delay=38 (8~68),Diff = 2 PI (6 cell)
7502 00:45:50.224433 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7503 00:45:50.227432 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
7504 00:45:50.227545
7505 00:45:50.231010 CA PerBit enable=1, Macro0, CA PI delay=36
7506 00:45:50.231108
7507 00:45:50.234279 [CBTSetCACLKResult] CA Dly = 36
7508 00:45:50.237556 CS Dly: 9 (0~40)
7509 00:45:50.240616 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7510 00:45:50.244493 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7511 00:45:50.244586 ==
7512 00:45:50.247754 Dram Type= 6, Freq= 0, CH_0, rank 1
7513 00:45:50.250902 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7514 00:45:50.250997 ==
7515 00:45:50.257603 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7516 00:45:50.260586 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7517 00:45:50.267326 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7518 00:45:50.270987 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7519 00:45:50.280590 [CA 0] Center 42 (12~72) winsize 61
7520 00:45:50.284241 [CA 1] Center 42 (12~73) winsize 62
7521 00:45:50.287705 [CA 2] Center 38 (8~68) winsize 61
7522 00:45:50.290896 [CA 3] Center 38 (8~68) winsize 61
7523 00:45:50.294043 [CA 4] Center 35 (5~65) winsize 61
7524 00:45:50.297203 [CA 5] Center 35 (5~65) winsize 61
7525 00:45:50.297278
7526 00:45:50.301084 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7527 00:45:50.301159
7528 00:45:50.304193 [CATrainingPosCal] consider 2 rank data
7529 00:45:50.307389 u2DelayCellTimex100 = 285/100 ps
7530 00:45:50.313911 CA0 delay=42 (13~72),Diff = 6 PI (20 cell)
7531 00:45:50.317045 CA1 delay=43 (13~73),Diff = 7 PI (23 cell)
7532 00:45:50.320290 CA2 delay=38 (9~68),Diff = 2 PI (6 cell)
7533 00:45:50.324244 CA3 delay=38 (8~68),Diff = 2 PI (6 cell)
7534 00:45:50.327417 CA4 delay=36 (7~65),Diff = 0 PI (0 cell)
7535 00:45:50.330505 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
7536 00:45:50.330580
7537 00:45:50.333977 CA PerBit enable=1, Macro0, CA PI delay=36
7538 00:45:50.334052
7539 00:45:50.336883 [CBTSetCACLKResult] CA Dly = 36
7540 00:45:50.340504 CS Dly: 10 (0~42)
7541 00:45:50.343671 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7542 00:45:50.347073 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7543 00:45:50.347148
7544 00:45:50.350501 ----->DramcWriteLeveling(PI) begin...
7545 00:45:50.350593 ==
7546 00:45:50.353607 Dram Type= 6, Freq= 0, CH_0, rank 0
7547 00:45:50.360402 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7548 00:45:50.360479 ==
7549 00:45:50.363677 Write leveling (Byte 0): 36 => 36
7550 00:45:50.363754 Write leveling (Byte 1): 29 => 29
7551 00:45:50.367177 DramcWriteLeveling(PI) end<-----
7552 00:45:50.367254
7553 00:45:50.367314 ==
7554 00:45:50.370325 Dram Type= 6, Freq= 0, CH_0, rank 0
7555 00:45:50.377299 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7556 00:45:50.377377 ==
7557 00:45:50.380397 [Gating] SW mode calibration
7558 00:45:50.386839 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7559 00:45:50.390617 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7560 00:45:50.397099 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7561 00:45:50.400536 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7562 00:45:50.403599 1 4 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (1 1)
7563 00:45:50.410568 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (0 0)
7564 00:45:50.413963 1 4 16 | B1->B0 | 2323 3737 | 0 0 | (0 0) (1 1)
7565 00:45:50.417189 1 4 20 | B1->B0 | 3333 3535 | 1 0 | (0 0) (0 0)
7566 00:45:50.423527 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7567 00:45:50.426653 1 4 28 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)
7568 00:45:50.430070 1 5 0 | B1->B0 | 3434 3636 | 1 1 | (1 1) (1 1)
7569 00:45:50.436959 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7570 00:45:50.440255 1 5 8 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 0)
7571 00:45:50.443483 1 5 12 | B1->B0 | 3434 2828 | 1 0 | (1 1) (1 0)
7572 00:45:50.446591 1 5 16 | B1->B0 | 3434 2625 | 1 1 | (1 0) (0 0)
7573 00:45:50.453384 1 5 20 | B1->B0 | 2a2a 2323 | 0 0 | (1 0) (0 0)
7574 00:45:50.457133 1 5 24 | B1->B0 | 2323 2524 | 0 1 | (0 0) (1 1)
7575 00:45:50.459991 1 5 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7576 00:45:50.466925 1 6 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7577 00:45:50.470079 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7578 00:45:50.473693 1 6 8 | B1->B0 | 2323 2e2d | 0 1 | (0 0) (0 0)
7579 00:45:50.479911 1 6 12 | B1->B0 | 2323 4544 | 0 1 | (0 0) (0 0)
7580 00:45:50.483312 1 6 16 | B1->B0 | 2828 4646 | 0 0 | (0 0) (0 0)
7581 00:45:50.487018 1 6 20 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
7582 00:45:50.493320 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7583 00:45:50.496797 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7584 00:45:50.499751 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7585 00:45:50.506706 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7586 00:45:50.509690 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7587 00:45:50.513030 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7588 00:45:50.519917 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7589 00:45:50.522952 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7590 00:45:50.526287 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7591 00:45:50.533365 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7592 00:45:50.536484 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7593 00:45:50.539874 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7594 00:45:50.546359 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7595 00:45:50.549960 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7596 00:45:50.553145 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7597 00:45:50.559582 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7598 00:45:50.562927 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7599 00:45:50.566092 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7600 00:45:50.573008 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7601 00:45:50.576447 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7602 00:45:50.579695 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7603 00:45:50.586070 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7604 00:45:50.589339 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7605 00:45:50.592502 Total UI for P1: 0, mck2ui 16
7606 00:45:50.596011 best dqsien dly found for B0: ( 1, 9, 12)
7607 00:45:50.599646 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7608 00:45:50.602460 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7609 00:45:50.605881 Total UI for P1: 0, mck2ui 16
7610 00:45:50.609085 best dqsien dly found for B1: ( 1, 9, 20)
7611 00:45:50.612561 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
7612 00:45:50.619343 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7613 00:45:50.619419
7614 00:45:50.622849 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
7615 00:45:50.625859 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7616 00:45:50.629157 [Gating] SW calibration Done
7617 00:45:50.629235 ==
7618 00:45:50.632167 Dram Type= 6, Freq= 0, CH_0, rank 0
7619 00:45:50.636108 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7620 00:45:50.636185 ==
7621 00:45:50.638893 RX Vref Scan: 0
7622 00:45:50.638997
7623 00:45:50.639058 RX Vref 0 -> 0, step: 1
7624 00:45:50.639114
7625 00:45:50.642569 RX Delay 0 -> 252, step: 8
7626 00:45:50.645745 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
7627 00:45:50.648988 iDelay=200, Bit 1, Center 143 (88 ~ 199) 112
7628 00:45:50.655439 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
7629 00:45:50.659359 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7630 00:45:50.662529 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7631 00:45:50.665798 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7632 00:45:50.668995 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7633 00:45:50.675432 iDelay=200, Bit 7, Center 143 (96 ~ 191) 96
7634 00:45:50.679112 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
7635 00:45:50.682359 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
7636 00:45:50.685775 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
7637 00:45:50.688628 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
7638 00:45:50.695707 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
7639 00:45:50.698915 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7640 00:45:50.702101 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7641 00:45:50.705308 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7642 00:45:50.705385 ==
7643 00:45:50.709251 Dram Type= 6, Freq= 0, CH_0, rank 0
7644 00:45:50.715393 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7645 00:45:50.715471 ==
7646 00:45:50.715531 DQS Delay:
7647 00:45:50.718594 DQS0 = 0, DQS1 = 0
7648 00:45:50.718669 DQM Delay:
7649 00:45:50.718728 DQM0 = 137, DQM1 = 129
7650 00:45:50.722005 DQ Delay:
7651 00:45:50.725781 DQ0 =135, DQ1 =143, DQ2 =135, DQ3 =131
7652 00:45:50.728927 DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =143
7653 00:45:50.732185 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
7654 00:45:50.735678 DQ12 =135, DQ13 =135, DQ14 =139, DQ15 =135
7655 00:45:50.735753
7656 00:45:50.735811
7657 00:45:50.735865 ==
7658 00:45:50.739177 Dram Type= 6, Freq= 0, CH_0, rank 0
7659 00:45:50.741935 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7660 00:45:50.745206 ==
7661 00:45:50.745280
7662 00:45:50.745338
7663 00:45:50.745391 TX Vref Scan disable
7664 00:45:50.748761 == TX Byte 0 ==
7665 00:45:50.752047 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7666 00:45:50.755450 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7667 00:45:50.758843 == TX Byte 1 ==
7668 00:45:50.762071 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7669 00:45:50.765341 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7670 00:45:50.768426 ==
7671 00:45:50.772151 Dram Type= 6, Freq= 0, CH_0, rank 0
7672 00:45:50.775299 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7673 00:45:50.775376 ==
7674 00:45:50.786563
7675 00:45:50.790430 TX Vref early break, caculate TX vref
7676 00:45:50.793583 TX Vref=16, minBit 0, minWin=23, winSum=376
7677 00:45:50.797236 TX Vref=18, minBit 1, minWin=23, winSum=384
7678 00:45:50.799964 TX Vref=20, minBit 0, minWin=24, winSum=399
7679 00:45:50.803657 TX Vref=22, minBit 3, minWin=24, winSum=409
7680 00:45:50.806569 TX Vref=24, minBit 2, minWin=24, winSum=417
7681 00:45:50.813653 TX Vref=26, minBit 0, minWin=25, winSum=424
7682 00:45:50.816797 TX Vref=28, minBit 1, minWin=25, winSum=425
7683 00:45:50.820015 TX Vref=30, minBit 1, minWin=24, winSum=410
7684 00:45:50.823153 TX Vref=32, minBit 6, minWin=23, winSum=401
7685 00:45:50.829652 [TxChooseVref] Worse bit 1, Min win 25, Win sum 425, Final Vref 28
7686 00:45:50.829726
7687 00:45:50.833356 Final TX Range 0 Vref 28
7688 00:45:50.833451
7689 00:45:50.833543 ==
7690 00:45:50.836519 Dram Type= 6, Freq= 0, CH_0, rank 0
7691 00:45:50.839745 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7692 00:45:50.839836 ==
7693 00:45:50.839908
7694 00:45:50.839980
7695 00:45:50.842960 TX Vref Scan disable
7696 00:45:50.846947 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
7697 00:45:50.849432 == TX Byte 0 ==
7698 00:45:50.853342 u2DelayCellOfst[0]=10 cells (3 PI)
7699 00:45:50.856341 u2DelayCellOfst[1]=13 cells (4 PI)
7700 00:45:50.859992 u2DelayCellOfst[2]=10 cells (3 PI)
7701 00:45:50.863106 u2DelayCellOfst[3]=10 cells (3 PI)
7702 00:45:50.866440 u2DelayCellOfst[4]=6 cells (2 PI)
7703 00:45:50.869857 u2DelayCellOfst[5]=0 cells (0 PI)
7704 00:45:50.869932 u2DelayCellOfst[6]=17 cells (5 PI)
7705 00:45:50.872964 u2DelayCellOfst[7]=13 cells (4 PI)
7706 00:45:50.879477 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7707 00:45:50.883043 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7708 00:45:50.883117 == TX Byte 1 ==
7709 00:45:50.886025 u2DelayCellOfst[8]=0 cells (0 PI)
7710 00:45:50.889670 u2DelayCellOfst[9]=0 cells (0 PI)
7711 00:45:50.892721 u2DelayCellOfst[10]=6 cells (2 PI)
7712 00:45:50.896659 u2DelayCellOfst[11]=6 cells (2 PI)
7713 00:45:50.899303 u2DelayCellOfst[12]=10 cells (3 PI)
7714 00:45:50.903179 u2DelayCellOfst[13]=10 cells (3 PI)
7715 00:45:50.906471 u2DelayCellOfst[14]=13 cells (4 PI)
7716 00:45:50.909590 u2DelayCellOfst[15]=10 cells (3 PI)
7717 00:45:50.913026 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7718 00:45:50.915869 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7719 00:45:50.919577 DramC Write-DBI on
7720 00:45:50.919652 ==
7721 00:45:50.922709 Dram Type= 6, Freq= 0, CH_0, rank 0
7722 00:45:50.925928 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7723 00:45:50.926004 ==
7724 00:45:50.926063
7725 00:45:50.929213
7726 00:45:50.929288 TX Vref Scan disable
7727 00:45:50.932907 == TX Byte 0 ==
7728 00:45:50.935770 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7729 00:45:50.939256 == TX Byte 1 ==
7730 00:45:50.942870 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
7731 00:45:50.942962 DramC Write-DBI off
7732 00:45:50.943034
7733 00:45:50.946125 [DATLAT]
7734 00:45:50.946202 Freq=1600, CH0 RK0
7735 00:45:50.946263
7736 00:45:50.949361 DATLAT Default: 0xf
7737 00:45:50.949436 0, 0xFFFF, sum = 0
7738 00:45:50.952532 1, 0xFFFF, sum = 0
7739 00:45:50.952608 2, 0xFFFF, sum = 0
7740 00:45:50.955807 3, 0xFFFF, sum = 0
7741 00:45:50.955885 4, 0xFFFF, sum = 0
7742 00:45:50.959006 5, 0xFFFF, sum = 0
7743 00:45:50.959096 6, 0xFFFF, sum = 0
7744 00:45:50.962860 7, 0xFFFF, sum = 0
7745 00:45:50.965879 8, 0xFFFF, sum = 0
7746 00:45:50.965972 9, 0xFFFF, sum = 0
7747 00:45:50.968932 10, 0xFFFF, sum = 0
7748 00:45:50.969036 11, 0xFFFF, sum = 0
7749 00:45:50.972983 12, 0xFFFF, sum = 0
7750 00:45:50.973100 13, 0xFFFF, sum = 0
7751 00:45:50.976017 14, 0x0, sum = 1
7752 00:45:50.976107 15, 0x0, sum = 2
7753 00:45:50.979048 16, 0x0, sum = 3
7754 00:45:50.979140 17, 0x0, sum = 4
7755 00:45:50.982876 best_step = 15
7756 00:45:50.982964
7757 00:45:50.983022 ==
7758 00:45:50.985986 Dram Type= 6, Freq= 0, CH_0, rank 0
7759 00:45:50.989084 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7760 00:45:50.989198 ==
7761 00:45:50.989284 RX Vref Scan: 1
7762 00:45:50.989379
7763 00:45:50.992379 Set Vref Range= 24 -> 127
7764 00:45:50.992454
7765 00:45:50.995882 RX Vref 24 -> 127, step: 1
7766 00:45:50.995972
7767 00:45:50.999224 RX Delay 19 -> 252, step: 4
7768 00:45:50.999299
7769 00:45:51.002371 Set Vref, RX VrefLevel [Byte0]: 24
7770 00:45:51.005664 [Byte1]: 24
7771 00:45:51.005739
7772 00:45:51.009320 Set Vref, RX VrefLevel [Byte0]: 25
7773 00:45:51.012787 [Byte1]: 25
7774 00:45:51.012865
7775 00:45:51.016021 Set Vref, RX VrefLevel [Byte0]: 26
7776 00:45:51.019049 [Byte1]: 26
7777 00:45:51.022669
7778 00:45:51.022740 Set Vref, RX VrefLevel [Byte0]: 27
7779 00:45:51.026087 [Byte1]: 27
7780 00:45:51.030018
7781 00:45:51.030089 Set Vref, RX VrefLevel [Byte0]: 28
7782 00:45:51.033859 [Byte1]: 28
7783 00:45:51.037670
7784 00:45:51.037765 Set Vref, RX VrefLevel [Byte0]: 29
7785 00:45:51.041383 [Byte1]: 29
7786 00:45:51.045141
7787 00:45:51.045212 Set Vref, RX VrefLevel [Byte0]: 30
7788 00:45:51.048727 [Byte1]: 30
7789 00:45:51.053224
7790 00:45:51.053323 Set Vref, RX VrefLevel [Byte0]: 31
7791 00:45:51.056465 [Byte1]: 31
7792 00:45:51.060313
7793 00:45:51.060385 Set Vref, RX VrefLevel [Byte0]: 32
7794 00:45:51.064119 [Byte1]: 32
7795 00:45:51.068024
7796 00:45:51.068093 Set Vref, RX VrefLevel [Byte0]: 33
7797 00:45:51.071135 [Byte1]: 33
7798 00:45:51.075526
7799 00:45:51.075599 Set Vref, RX VrefLevel [Byte0]: 34
7800 00:45:51.078893 [Byte1]: 34
7801 00:45:51.083311
7802 00:45:51.083381 Set Vref, RX VrefLevel [Byte0]: 35
7803 00:45:51.086614 [Byte1]: 35
7804 00:45:51.091205
7805 00:45:51.091297 Set Vref, RX VrefLevel [Byte0]: 36
7806 00:45:51.094373 [Byte1]: 36
7807 00:45:51.098212
7808 00:45:51.098285 Set Vref, RX VrefLevel [Byte0]: 37
7809 00:45:51.101971 [Byte1]: 37
7810 00:45:51.106148
7811 00:45:51.106217 Set Vref, RX VrefLevel [Byte0]: 38
7812 00:45:51.109211 [Byte1]: 38
7813 00:45:51.113641
7814 00:45:51.113711 Set Vref, RX VrefLevel [Byte0]: 39
7815 00:45:51.117047 [Byte1]: 39
7816 00:45:51.121108
7817 00:45:51.121175 Set Vref, RX VrefLevel [Byte0]: 40
7818 00:45:51.124116 [Byte1]: 40
7819 00:45:51.128760
7820 00:45:51.128830 Set Vref, RX VrefLevel [Byte0]: 41
7821 00:45:51.131807 [Byte1]: 41
7822 00:45:51.136304
7823 00:45:51.136370 Set Vref, RX VrefLevel [Byte0]: 42
7824 00:45:51.139709 [Byte1]: 42
7825 00:45:51.143987
7826 00:45:51.144080 Set Vref, RX VrefLevel [Byte0]: 43
7827 00:45:51.147342 [Byte1]: 43
7828 00:45:51.151351
7829 00:45:51.151421 Set Vref, RX VrefLevel [Byte0]: 44
7830 00:45:51.154476 [Byte1]: 44
7831 00:45:51.159343
7832 00:45:51.159435 Set Vref, RX VrefLevel [Byte0]: 45
7833 00:45:51.162070 [Byte1]: 45
7834 00:45:51.166356
7835 00:45:51.166431 Set Vref, RX VrefLevel [Byte0]: 46
7836 00:45:51.169637 [Byte1]: 46
7837 00:45:51.173972
7838 00:45:51.174050 Set Vref, RX VrefLevel [Byte0]: 47
7839 00:45:51.177663 [Byte1]: 47
7840 00:45:51.181618
7841 00:45:51.181694 Set Vref, RX VrefLevel [Byte0]: 48
7842 00:45:51.184906 [Byte1]: 48
7843 00:45:51.189282
7844 00:45:51.189357 Set Vref, RX VrefLevel [Byte0]: 49
7845 00:45:51.192522 [Byte1]: 49
7846 00:45:51.197096
7847 00:45:51.197171 Set Vref, RX VrefLevel [Byte0]: 50
7848 00:45:51.200215 [Byte1]: 50
7849 00:45:51.204799
7850 00:45:51.204874 Set Vref, RX VrefLevel [Byte0]: 51
7851 00:45:51.208039 [Byte1]: 51
7852 00:45:51.211881
7853 00:45:51.211956 Set Vref, RX VrefLevel [Byte0]: 52
7854 00:45:51.215557 [Byte1]: 52
7855 00:45:51.219752
7856 00:45:51.219826 Set Vref, RX VrefLevel [Byte0]: 53
7857 00:45:51.222968 [Byte1]: 53
7858 00:45:51.227212
7859 00:45:51.227311 Set Vref, RX VrefLevel [Byte0]: 54
7860 00:45:51.230311 [Byte1]: 54
7861 00:45:51.234934
7862 00:45:51.235009 Set Vref, RX VrefLevel [Byte0]: 55
7863 00:45:51.237755 [Byte1]: 55
7864 00:45:51.242366
7865 00:45:51.242441 Set Vref, RX VrefLevel [Byte0]: 56
7866 00:45:51.245598 [Byte1]: 56
7867 00:45:51.250056
7868 00:45:51.250152 Set Vref, RX VrefLevel [Byte0]: 57
7869 00:45:51.253313 [Byte1]: 57
7870 00:45:51.257753
7871 00:45:51.257823 Set Vref, RX VrefLevel [Byte0]: 58
7872 00:45:51.260676 [Byte1]: 58
7873 00:45:51.265498
7874 00:45:51.265648 Set Vref, RX VrefLevel [Byte0]: 59
7875 00:45:51.268145 [Byte1]: 59
7876 00:45:51.272811
7877 00:45:51.272906 Set Vref, RX VrefLevel [Byte0]: 60
7878 00:45:51.276186 [Byte1]: 60
7879 00:45:51.280293
7880 00:45:51.280364 Set Vref, RX VrefLevel [Byte0]: 61
7881 00:45:51.283426 [Byte1]: 61
7882 00:45:51.287620
7883 00:45:51.287689 Set Vref, RX VrefLevel [Byte0]: 62
7884 00:45:51.290815 [Byte1]: 62
7885 00:45:51.295268
7886 00:45:51.295360 Set Vref, RX VrefLevel [Byte0]: 63
7887 00:45:51.298593 [Byte1]: 63
7888 00:45:51.303131
7889 00:45:51.303200 Set Vref, RX VrefLevel [Byte0]: 64
7890 00:45:51.306331 [Byte1]: 64
7891 00:45:51.310219
7892 00:45:51.310288 Set Vref, RX VrefLevel [Byte0]: 65
7893 00:45:51.313972 [Byte1]: 65
7894 00:45:51.317847
7895 00:45:51.317943 Set Vref, RX VrefLevel [Byte0]: 66
7896 00:45:51.321043 [Byte1]: 66
7897 00:45:51.325909
7898 00:45:51.326004 Set Vref, RX VrefLevel [Byte0]: 67
7899 00:45:51.328988 [Byte1]: 67
7900 00:45:51.333432
7901 00:45:51.333521 Set Vref, RX VrefLevel [Byte0]: 68
7902 00:45:51.336511 [Byte1]: 68
7903 00:45:51.340811
7904 00:45:51.340929 Set Vref, RX VrefLevel [Byte0]: 69
7905 00:45:51.343733 [Byte1]: 69
7906 00:45:51.348347
7907 00:45:51.348440 Set Vref, RX VrefLevel [Byte0]: 70
7908 00:45:51.351408 [Byte1]: 70
7909 00:45:51.356001
7910 00:45:51.356074 Set Vref, RX VrefLevel [Byte0]: 71
7911 00:45:51.359183 [Byte1]: 71
7912 00:45:51.363743
7913 00:45:51.363817 Set Vref, RX VrefLevel [Byte0]: 72
7914 00:45:51.366476 [Byte1]: 72
7915 00:45:51.370749
7916 00:45:51.370817 Set Vref, RX VrefLevel [Byte0]: 73
7917 00:45:51.374264 [Byte1]: 73
7918 00:45:51.378500
7919 00:45:51.378574 Set Vref, RX VrefLevel [Byte0]: 74
7920 00:45:51.381639 [Byte1]: 74
7921 00:45:51.385859
7922 00:45:51.385930 Set Vref, RX VrefLevel [Byte0]: 75
7923 00:45:51.389357 [Byte1]: 75
7924 00:45:51.393821
7925 00:45:51.393889 Final RX Vref Byte 0 = 57 to rank0
7926 00:45:51.397302 Final RX Vref Byte 1 = 56 to rank0
7927 00:45:51.400376 Final RX Vref Byte 0 = 57 to rank1
7928 00:45:51.404001 Final RX Vref Byte 1 = 56 to rank1==
7929 00:45:51.407085 Dram Type= 6, Freq= 0, CH_0, rank 0
7930 00:45:51.413642 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7931 00:45:51.413736 ==
7932 00:45:51.413829 DQS Delay:
7933 00:45:51.413921 DQS0 = 0, DQS1 = 0
7934 00:45:51.416839 DQM Delay:
7935 00:45:51.416927 DQM0 = 134, DQM1 = 127
7936 00:45:51.420041 DQ Delay:
7937 00:45:51.423987 DQ0 =134, DQ1 =138, DQ2 =134, DQ3 =132
7938 00:45:51.427360 DQ4 =134, DQ5 =124, DQ6 =138, DQ7 =138
7939 00:45:51.430416 DQ8 =116, DQ9 =118, DQ10 =128, DQ11 =120
7940 00:45:51.433898 DQ12 =130, DQ13 =132, DQ14 =138, DQ15 =134
7941 00:45:51.433968
7942 00:45:51.434042
7943 00:45:51.434140
7944 00:45:51.437057 [DramC_TX_OE_Calibration] TA2
7945 00:45:51.440269 Original DQ_B0 (3 6) =30, OEN = 27
7946 00:45:51.443422 Original DQ_B1 (3 6) =30, OEN = 27
7947 00:45:51.447283 24, 0x0, End_B0=24 End_B1=24
7948 00:45:51.447352 25, 0x0, End_B0=25 End_B1=25
7949 00:45:51.450403 26, 0x0, End_B0=26 End_B1=26
7950 00:45:51.453358 27, 0x0, End_B0=27 End_B1=27
7951 00:45:51.456899 28, 0x0, End_B0=28 End_B1=28
7952 00:45:51.457000 29, 0x0, End_B0=29 End_B1=29
7953 00:45:51.460131 30, 0x0, End_B0=30 End_B1=30
7954 00:45:51.463609 31, 0x4141, End_B0=30 End_B1=30
7955 00:45:51.467105 Byte0 end_step=30 best_step=27
7956 00:45:51.470142 Byte1 end_step=30 best_step=27
7957 00:45:51.473428 Byte0 TX OE(2T, 0.5T) = (3, 3)
7958 00:45:51.473520 Byte1 TX OE(2T, 0.5T) = (3, 3)
7959 00:45:51.477149
7960 00:45:51.477216
7961 00:45:51.483618 [DQSOSCAuto] RK0, (LSB)MR18= 0x2824, (MSB)MR19= 0x303, tDQSOscB0 = 391 ps tDQSOscB1 = 389 ps
7962 00:45:51.486907 CH0 RK0: MR19=303, MR18=2824
7963 00:45:51.493255 CH0_RK0: MR19=0x303, MR18=0x2824, DQSOSC=389, MR23=63, INC=24, DEC=16
7964 00:45:51.493350
7965 00:45:51.496840 ----->DramcWriteLeveling(PI) begin...
7966 00:45:51.496932 ==
7967 00:45:51.500341 Dram Type= 6, Freq= 0, CH_0, rank 1
7968 00:45:51.503537 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7969 00:45:51.503605 ==
7970 00:45:51.506997 Write leveling (Byte 0): 34 => 34
7971 00:45:51.510344 Write leveling (Byte 1): 29 => 29
7972 00:45:51.513611 DramcWriteLeveling(PI) end<-----
7973 00:45:51.513703
7974 00:45:51.513776 ==
7975 00:45:51.516607 Dram Type= 6, Freq= 0, CH_0, rank 1
7976 00:45:51.520049 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7977 00:45:51.520120 ==
7978 00:45:51.523305 [Gating] SW mode calibration
7979 00:45:51.529825 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7980 00:45:51.536843 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7981 00:45:51.539965 1 4 0 | B1->B0 | 2323 2423 | 0 1 | (0 0) (0 0)
7982 00:45:51.543606 1 4 4 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
7983 00:45:51.549868 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7984 00:45:51.553168 1 4 12 | B1->B0 | 2424 2b2b | 0 0 | (0 0) (0 0)
7985 00:45:51.556331 1 4 16 | B1->B0 | 2e2e 3535 | 1 1 | (1 1) (1 1)
7986 00:45:51.563059 1 4 20 | B1->B0 | 3434 3636 | 1 0 | (1 1) (0 0)
7987 00:45:51.566812 1 4 24 | B1->B0 | 3434 3737 | 1 1 | (1 1) (0 0)
7988 00:45:51.569950 1 4 28 | B1->B0 | 3434 3838 | 1 1 | (1 1) (1 1)
7989 00:45:51.576609 1 5 0 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
7990 00:45:51.579598 1 5 4 | B1->B0 | 3434 0 | 1 1 | (1 1) (0 0)
7991 00:45:51.583472 1 5 8 | B1->B0 | 3434 3c3b | 1 1 | (1 1) (0 0)
7992 00:45:51.589520 1 5 12 | B1->B0 | 3434 3535 | 1 1 | (1 0) (1 0)
7993 00:45:51.593027 1 5 16 | B1->B0 | 2e2e 2a2a | 0 0 | (0 1) (0 0)
7994 00:45:51.596603 1 5 20 | B1->B0 | 2323 2424 | 0 1 | (0 0) (0 0)
7995 00:45:51.602999 1 5 24 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
7996 00:45:51.606445 1 5 28 | B1->B0 | 2323 2a29 | 0 1 | (0 0) (0 0)
7997 00:45:51.609649 1 6 0 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
7998 00:45:51.613516 1 6 4 | B1->B0 | 2323 2a29 | 0 1 | (0 0) (0 0)
7999 00:45:51.619859 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8000 00:45:51.622701 1 6 12 | B1->B0 | 2424 3b3a | 0 1 | (0 0) (0 0)
8001 00:45:51.626290 1 6 16 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
8002 00:45:51.633086 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8003 00:45:51.635937 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8004 00:45:51.639931 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8005 00:45:51.646152 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8006 00:45:51.649707 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8007 00:45:51.653354 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8008 00:45:51.659729 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8009 00:45:51.662998 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8010 00:45:51.666197 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8011 00:45:51.672919 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8012 00:45:51.676125 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8013 00:45:51.679160 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8014 00:45:51.686442 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8015 00:45:51.689643 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8016 00:45:51.693015 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8017 00:45:51.699640 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8018 00:45:51.702848 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8019 00:45:51.706086 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8020 00:45:51.712975 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8021 00:45:51.716106 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8022 00:45:51.719754 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8023 00:45:51.725990 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8024 00:45:51.729112 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8025 00:45:51.732504 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8026 00:45:51.736282 Total UI for P1: 0, mck2ui 16
8027 00:45:51.739310 best dqsien dly found for B0: ( 1, 9, 12)
8028 00:45:51.742326 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8029 00:45:51.746085 Total UI for P1: 0, mck2ui 16
8030 00:45:51.749313 best dqsien dly found for B1: ( 1, 9, 14)
8031 00:45:51.752601 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8032 00:45:51.759242 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8033 00:45:51.759339
8034 00:45:51.762238 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8035 00:45:51.766094 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8036 00:45:51.769409 [Gating] SW calibration Done
8037 00:45:51.769514 ==
8038 00:45:51.772542 Dram Type= 6, Freq= 0, CH_0, rank 1
8039 00:45:51.775694 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8040 00:45:51.775786 ==
8041 00:45:51.779111 RX Vref Scan: 0
8042 00:45:51.779199
8043 00:45:51.779320 RX Vref 0 -> 0, step: 1
8044 00:45:51.779401
8045 00:45:51.782669 RX Delay 0 -> 252, step: 8
8046 00:45:51.785744 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8047 00:45:51.789422 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8048 00:45:51.795671 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8049 00:45:51.799450 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8050 00:45:51.802552 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8051 00:45:51.806116 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8052 00:45:51.809424 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
8053 00:45:51.815887 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8054 00:45:51.818943 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8055 00:45:51.822739 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8056 00:45:51.825884 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8057 00:45:51.829081 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8058 00:45:51.836088 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8059 00:45:51.839214 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8060 00:45:51.842534 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8061 00:45:51.845718 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8062 00:45:51.845810 ==
8063 00:45:51.848922 Dram Type= 6, Freq= 0, CH_0, rank 1
8064 00:45:51.855636 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8065 00:45:51.855733 ==
8066 00:45:51.855821 DQS Delay:
8067 00:45:51.858933 DQS0 = 0, DQS1 = 0
8068 00:45:51.859024 DQM Delay:
8069 00:45:51.859107 DQM0 = 136, DQM1 = 128
8070 00:45:51.862248 DQ Delay:
8071 00:45:51.865796 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
8072 00:45:51.869225 DQ4 =139, DQ5 =127, DQ6 =139, DQ7 =143
8073 00:45:51.872225 DQ8 =119, DQ9 =119, DQ10 =127, DQ11 =119
8074 00:45:51.875589 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8075 00:45:51.875677
8076 00:45:51.875760
8077 00:45:51.875843 ==
8078 00:45:51.878939 Dram Type= 6, Freq= 0, CH_0, rank 1
8079 00:45:51.882225 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8080 00:45:51.885295 ==
8081 00:45:51.885385
8082 00:45:51.885467
8083 00:45:51.885554 TX Vref Scan disable
8084 00:45:51.888945 == TX Byte 0 ==
8085 00:45:51.892407 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8086 00:45:51.895491 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8087 00:45:51.898979 == TX Byte 1 ==
8088 00:45:51.901921 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8089 00:45:51.905089 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8090 00:45:51.908664 ==
8091 00:45:51.911880 Dram Type= 6, Freq= 0, CH_0, rank 1
8092 00:45:51.915060 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8093 00:45:51.915154 ==
8094 00:45:51.928232
8095 00:45:51.931307 TX Vref early break, caculate TX vref
8096 00:45:51.934857 TX Vref=16, minBit 1, minWin=22, winSum=388
8097 00:45:51.938008 TX Vref=18, minBit 0, minWin=23, winSum=398
8098 00:45:51.941307 TX Vref=20, minBit 1, minWin=24, winSum=405
8099 00:45:51.944466 TX Vref=22, minBit 1, minWin=24, winSum=414
8100 00:45:51.948308 TX Vref=24, minBit 1, minWin=25, winSum=421
8101 00:45:51.955127 TX Vref=26, minBit 1, minWin=25, winSum=425
8102 00:45:51.958381 TX Vref=28, minBit 7, minWin=25, winSum=426
8103 00:45:51.961723 TX Vref=30, minBit 0, minWin=25, winSum=414
8104 00:45:51.964885 TX Vref=32, minBit 0, minWin=25, winSum=411
8105 00:45:51.967736 TX Vref=34, minBit 0, minWin=24, winSum=401
8106 00:45:51.974798 [TxChooseVref] Worse bit 7, Min win 25, Win sum 426, Final Vref 28
8107 00:45:51.974872
8108 00:45:51.977795 Final TX Range 0 Vref 28
8109 00:45:51.977909
8110 00:45:51.977998 ==
8111 00:45:51.981273 Dram Type= 6, Freq= 0, CH_0, rank 1
8112 00:45:51.984507 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8113 00:45:51.984573 ==
8114 00:45:51.984627
8115 00:45:51.984678
8116 00:45:51.988005 TX Vref Scan disable
8117 00:45:51.994761 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8118 00:45:51.994886 == TX Byte 0 ==
8119 00:45:51.997747 u2DelayCellOfst[0]=10 cells (3 PI)
8120 00:45:52.000847 u2DelayCellOfst[1]=13 cells (4 PI)
8121 00:45:52.004653 u2DelayCellOfst[2]=10 cells (3 PI)
8122 00:45:52.007758 u2DelayCellOfst[3]=10 cells (3 PI)
8123 00:45:52.011219 u2DelayCellOfst[4]=6 cells (2 PI)
8124 00:45:52.014321 u2DelayCellOfst[5]=0 cells (0 PI)
8125 00:45:52.017913 u2DelayCellOfst[6]=17 cells (5 PI)
8126 00:45:52.017976 u2DelayCellOfst[7]=13 cells (4 PI)
8127 00:45:52.024250 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8128 00:45:52.027855 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8129 00:45:52.027924 == TX Byte 1 ==
8130 00:45:52.031122 u2DelayCellOfst[8]=0 cells (0 PI)
8131 00:45:52.034264 u2DelayCellOfst[9]=0 cells (0 PI)
8132 00:45:52.037415 u2DelayCellOfst[10]=6 cells (2 PI)
8133 00:45:52.041098 u2DelayCellOfst[11]=3 cells (1 PI)
8134 00:45:52.044713 u2DelayCellOfst[12]=10 cells (3 PI)
8135 00:45:52.047900 u2DelayCellOfst[13]=10 cells (3 PI)
8136 00:45:52.051178 u2DelayCellOfst[14]=13 cells (4 PI)
8137 00:45:52.054365 u2DelayCellOfst[15]=10 cells (3 PI)
8138 00:45:52.057572 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8139 00:45:52.064025 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8140 00:45:52.064101 DramC Write-DBI on
8141 00:45:52.064159 ==
8142 00:45:52.067906 Dram Type= 6, Freq= 0, CH_0, rank 1
8143 00:45:52.071115 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8144 00:45:52.074417 ==
8145 00:45:52.074510
8146 00:45:52.074604
8147 00:45:52.074689 TX Vref Scan disable
8148 00:45:52.077410 == TX Byte 0 ==
8149 00:45:52.081122 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
8150 00:45:52.084447 == TX Byte 1 ==
8151 00:45:52.087660 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8152 00:45:52.090914 DramC Write-DBI off
8153 00:45:52.091002
8154 00:45:52.091085 [DATLAT]
8155 00:45:52.091151 Freq=1600, CH0 RK1
8156 00:45:52.091204
8157 00:45:52.094109 DATLAT Default: 0xf
8158 00:45:52.097619 0, 0xFFFF, sum = 0
8159 00:45:52.097711 1, 0xFFFF, sum = 0
8160 00:45:52.100852 2, 0xFFFF, sum = 0
8161 00:45:52.100915 3, 0xFFFF, sum = 0
8162 00:45:52.103977 4, 0xFFFF, sum = 0
8163 00:45:52.104064 5, 0xFFFF, sum = 0
8164 00:45:52.107315 6, 0xFFFF, sum = 0
8165 00:45:52.107401 7, 0xFFFF, sum = 0
8166 00:45:52.110743 8, 0xFFFF, sum = 0
8167 00:45:52.110853 9, 0xFFFF, sum = 0
8168 00:45:52.114209 10, 0xFFFF, sum = 0
8169 00:45:52.114329 11, 0xFFFF, sum = 0
8170 00:45:52.117496 12, 0xFFFF, sum = 0
8171 00:45:52.117603 13, 0xFFFF, sum = 0
8172 00:45:52.120494 14, 0x0, sum = 1
8173 00:45:52.120588 15, 0x0, sum = 2
8174 00:45:52.123693 16, 0x0, sum = 3
8175 00:45:52.123787 17, 0x0, sum = 4
8176 00:45:52.127024 best_step = 15
8177 00:45:52.127115
8178 00:45:52.127197 ==
8179 00:45:52.130980 Dram Type= 6, Freq= 0, CH_0, rank 1
8180 00:45:52.134070 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8181 00:45:52.134140 ==
8182 00:45:52.137269 RX Vref Scan: 0
8183 00:45:52.137363
8184 00:45:52.137447 RX Vref 0 -> 0, step: 1
8185 00:45:52.137525
8186 00:45:52.140598 RX Delay 19 -> 252, step: 4
8187 00:45:52.146913 iDelay=191, Bit 0, Center 134 (83 ~ 186) 104
8188 00:45:52.150520 iDelay=191, Bit 1, Center 138 (91 ~ 186) 96
8189 00:45:52.153483 iDelay=191, Bit 2, Center 130 (79 ~ 182) 104
8190 00:45:52.156641 iDelay=191, Bit 3, Center 134 (83 ~ 186) 104
8191 00:45:52.160349 iDelay=191, Bit 4, Center 136 (87 ~ 186) 100
8192 00:45:52.163561 iDelay=191, Bit 5, Center 124 (71 ~ 178) 108
8193 00:45:52.170666 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8194 00:45:52.173909 iDelay=191, Bit 7, Center 140 (91 ~ 190) 100
8195 00:45:52.177036 iDelay=191, Bit 8, Center 118 (67 ~ 170) 104
8196 00:45:52.180225 iDelay=191, Bit 9, Center 116 (63 ~ 170) 108
8197 00:45:52.183929 iDelay=191, Bit 10, Center 128 (79 ~ 178) 100
8198 00:45:52.190317 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8199 00:45:52.193582 iDelay=191, Bit 12, Center 132 (83 ~ 182) 100
8200 00:45:52.196723 iDelay=191, Bit 13, Center 134 (83 ~ 186) 104
8201 00:45:52.199883 iDelay=191, Bit 14, Center 136 (83 ~ 190) 108
8202 00:45:52.207104 iDelay=191, Bit 15, Center 134 (83 ~ 186) 104
8203 00:45:52.207181 ==
8204 00:45:52.210312 Dram Type= 6, Freq= 0, CH_0, rank 1
8205 00:45:52.213497 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8206 00:45:52.213610 ==
8207 00:45:52.213671 DQS Delay:
8208 00:45:52.217046 DQS0 = 0, DQS1 = 0
8209 00:45:52.217121 DQM Delay:
8210 00:45:52.220527 DQM0 = 134, DQM1 = 127
8211 00:45:52.220602 DQ Delay:
8212 00:45:52.223353 DQ0 =134, DQ1 =138, DQ2 =130, DQ3 =134
8213 00:45:52.226767 DQ4 =136, DQ5 =124, DQ6 =140, DQ7 =140
8214 00:45:52.230349 DQ8 =118, DQ9 =116, DQ10 =128, DQ11 =118
8215 00:45:52.233202 DQ12 =132, DQ13 =134, DQ14 =136, DQ15 =134
8216 00:45:52.233293
8217 00:45:52.233376
8218 00:45:52.233461
8219 00:45:52.236582 [DramC_TX_OE_Calibration] TA2
8220 00:45:52.239942 Original DQ_B0 (3 6) =30, OEN = 27
8221 00:45:52.243141 Original DQ_B1 (3 6) =30, OEN = 27
8222 00:45:52.246727 24, 0x0, End_B0=24 End_B1=24
8223 00:45:52.250113 25, 0x0, End_B0=25 End_B1=25
8224 00:45:52.250209 26, 0x0, End_B0=26 End_B1=26
8225 00:45:52.253183 27, 0x0, End_B0=27 End_B1=27
8226 00:45:52.256341 28, 0x0, End_B0=28 End_B1=28
8227 00:45:52.259656 29, 0x0, End_B0=29 End_B1=29
8228 00:45:52.263487 30, 0x0, End_B0=30 End_B1=30
8229 00:45:52.263562 31, 0x4141, End_B0=30 End_B1=30
8230 00:45:52.266309 Byte0 end_step=30 best_step=27
8231 00:45:52.269780 Byte1 end_step=30 best_step=27
8232 00:45:52.273247 Byte0 TX OE(2T, 0.5T) = (3, 3)
8233 00:45:52.276530 Byte1 TX OE(2T, 0.5T) = (3, 3)
8234 00:45:52.276598
8235 00:45:52.276657
8236 00:45:52.282967 [DQSOSCAuto] RK1, (LSB)MR18= 0x220a, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 392 ps
8237 00:45:52.286245 CH0 RK1: MR19=303, MR18=220A
8238 00:45:52.292585 CH0_RK1: MR19=0x303, MR18=0x220A, DQSOSC=392, MR23=63, INC=24, DEC=16
8239 00:45:52.296339 [RxdqsGatingPostProcess] freq 1600
8240 00:45:52.302873 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8241 00:45:52.306050 best DQS0 dly(2T, 0.5T) = (1, 1)
8242 00:45:52.306118 best DQS1 dly(2T, 0.5T) = (1, 1)
8243 00:45:52.309285 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8244 00:45:52.312479 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8245 00:45:52.316448 best DQS0 dly(2T, 0.5T) = (1, 1)
8246 00:45:52.319607 best DQS1 dly(2T, 0.5T) = (1, 1)
8247 00:45:52.322691 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8248 00:45:52.325888 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8249 00:45:52.329499 Pre-setting of DQS Precalculation
8250 00:45:52.333218 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8251 00:45:52.333311 ==
8252 00:45:52.336310 Dram Type= 6, Freq= 0, CH_1, rank 0
8253 00:45:52.342737 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8254 00:45:52.342807 ==
8255 00:45:52.346031 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8256 00:45:52.353076 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8257 00:45:52.356065 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8258 00:45:52.363049 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8259 00:45:52.370881 [CA 0] Center 41 (12~71) winsize 60
8260 00:45:52.374045 [CA 1] Center 41 (12~71) winsize 60
8261 00:45:52.377464 [CA 2] Center 38 (9~68) winsize 60
8262 00:45:52.380294 [CA 3] Center 37 (9~66) winsize 58
8263 00:45:52.384027 [CA 4] Center 37 (8~67) winsize 60
8264 00:45:52.387314 [CA 5] Center 36 (7~66) winsize 60
8265 00:45:52.387411
8266 00:45:52.390321 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8267 00:45:52.390390
8268 00:45:52.393625 [CATrainingPosCal] consider 1 rank data
8269 00:45:52.397119 u2DelayCellTimex100 = 285/100 ps
8270 00:45:52.400999 CA0 delay=41 (12~71),Diff = 5 PI (17 cell)
8271 00:45:52.407477 CA1 delay=41 (12~71),Diff = 5 PI (17 cell)
8272 00:45:52.410813 CA2 delay=38 (9~68),Diff = 2 PI (6 cell)
8273 00:45:52.414050 CA3 delay=37 (9~66),Diff = 1 PI (3 cell)
8274 00:45:52.417295 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8275 00:45:52.420478 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8276 00:45:52.420569
8277 00:45:52.423735 CA PerBit enable=1, Macro0, CA PI delay=36
8278 00:45:52.423840
8279 00:45:52.427557 [CBTSetCACLKResult] CA Dly = 36
8280 00:45:52.427647 CS Dly: 10 (0~41)
8281 00:45:52.433919 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8282 00:45:52.437579 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8283 00:45:52.437684 ==
8284 00:45:52.440510 Dram Type= 6, Freq= 0, CH_1, rank 1
8285 00:45:52.443672 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8286 00:45:52.443763 ==
8287 00:45:52.450376 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8288 00:45:52.454001 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8289 00:45:52.460585 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8290 00:45:52.463615 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8291 00:45:52.474120 [CA 0] Center 41 (12~71) winsize 60
8292 00:45:52.477196 [CA 1] Center 41 (11~72) winsize 62
8293 00:45:52.480622 [CA 2] Center 38 (9~68) winsize 60
8294 00:45:52.483685 [CA 3] Center 38 (8~68) winsize 61
8295 00:45:52.487251 [CA 4] Center 38 (8~68) winsize 61
8296 00:45:52.490627 [CA 5] Center 36 (7~66) winsize 60
8297 00:45:52.490702
8298 00:45:52.493496 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8299 00:45:52.493617
8300 00:45:52.497296 [CATrainingPosCal] consider 2 rank data
8301 00:45:52.500318 u2DelayCellTimex100 = 285/100 ps
8302 00:45:52.503897 CA0 delay=41 (12~71),Diff = 5 PI (17 cell)
8303 00:45:52.510463 CA1 delay=41 (12~71),Diff = 5 PI (17 cell)
8304 00:45:52.513565 CA2 delay=38 (9~68),Diff = 2 PI (6 cell)
8305 00:45:52.516831 CA3 delay=37 (9~66),Diff = 1 PI (3 cell)
8306 00:45:52.520625 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8307 00:45:52.523772 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8308 00:45:52.523862
8309 00:45:52.526987 CA PerBit enable=1, Macro0, CA PI delay=36
8310 00:45:52.527076
8311 00:45:52.530193 [CBTSetCACLKResult] CA Dly = 36
8312 00:45:52.533522 CS Dly: 12 (0~45)
8313 00:45:52.537402 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8314 00:45:52.540609 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8315 00:45:52.540696
8316 00:45:52.543732 ----->DramcWriteLeveling(PI) begin...
8317 00:45:52.543821 ==
8318 00:45:52.546765 Dram Type= 6, Freq= 0, CH_1, rank 0
8319 00:45:52.550386 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8320 00:45:52.553884 ==
8321 00:45:52.553948 Write leveling (Byte 0): 25 => 25
8322 00:45:52.557029 Write leveling (Byte 1): 26 => 26
8323 00:45:52.560447 DramcWriteLeveling(PI) end<-----
8324 00:45:52.560546
8325 00:45:52.560634 ==
8326 00:45:52.563501 Dram Type= 6, Freq= 0, CH_1, rank 0
8327 00:45:52.570354 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8328 00:45:52.570430 ==
8329 00:45:52.570489 [Gating] SW mode calibration
8330 00:45:52.580520 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8331 00:45:52.583971 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8332 00:45:52.589999 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8333 00:45:52.593716 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8334 00:45:52.596710 1 4 8 | B1->B0 | 2323 2423 | 0 1 | (0 0) (1 1)
8335 00:45:52.603082 1 4 12 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
8336 00:45:52.606634 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8337 00:45:52.609825 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8338 00:45:52.613236 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8339 00:45:52.620182 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8340 00:45:52.623464 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8341 00:45:52.626897 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8342 00:45:52.633291 1 5 8 | B1->B0 | 3434 2727 | 1 1 | (1 0) (1 0)
8343 00:45:52.636411 1 5 12 | B1->B0 | 2828 2323 | 0 0 | (1 1) (1 0)
8344 00:45:52.639764 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8345 00:45:52.646310 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8346 00:45:52.650149 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8347 00:45:52.653185 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8348 00:45:52.659803 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8349 00:45:52.663435 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8350 00:45:52.666279 1 6 8 | B1->B0 | 2525 4141 | 0 0 | (0 0) (0 0)
8351 00:45:52.673284 1 6 12 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
8352 00:45:52.676419 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8353 00:45:52.679495 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8354 00:45:52.686697 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8355 00:45:52.689921 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8356 00:45:52.693102 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8357 00:45:52.699875 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8358 00:45:52.703057 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8359 00:45:52.706379 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8360 00:45:52.712772 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8361 00:45:52.716551 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8362 00:45:52.719739 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8363 00:45:52.726050 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8364 00:45:52.729616 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8365 00:45:52.733091 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8366 00:45:52.739720 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8367 00:45:52.743042 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8368 00:45:52.746405 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8369 00:45:52.749672 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8370 00:45:52.755968 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8371 00:45:52.759142 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8372 00:45:52.762736 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8373 00:45:52.769361 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8374 00:45:52.772590 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8375 00:45:52.776141 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8376 00:45:52.782379 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8377 00:45:52.786064 Total UI for P1: 0, mck2ui 16
8378 00:45:52.789247 best dqsien dly found for B0: ( 1, 9, 10)
8379 00:45:52.792659 Total UI for P1: 0, mck2ui 16
8380 00:45:52.796012 best dqsien dly found for B1: ( 1, 9, 10)
8381 00:45:52.799189 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8382 00:45:52.802234 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8383 00:45:52.802301
8384 00:45:52.805928 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8385 00:45:52.809185 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8386 00:45:52.812512 [Gating] SW calibration Done
8387 00:45:52.812575 ==
8388 00:45:52.815785 Dram Type= 6, Freq= 0, CH_1, rank 0
8389 00:45:52.818901 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8390 00:45:52.818968 ==
8391 00:45:52.822668 RX Vref Scan: 0
8392 00:45:52.822728
8393 00:45:52.825757 RX Vref 0 -> 0, step: 1
8394 00:45:52.825843
8395 00:45:52.825924 RX Delay 0 -> 252, step: 8
8396 00:45:52.832676 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8397 00:45:52.835976 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8398 00:45:52.839147 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8399 00:45:52.842301 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8400 00:45:52.845778 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8401 00:45:52.848646 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8402 00:45:52.855374 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8403 00:45:52.859016 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8404 00:45:52.862296 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
8405 00:45:52.865573 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8406 00:45:52.868714 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8407 00:45:52.875328 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8408 00:45:52.879090 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8409 00:45:52.882326 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
8410 00:45:52.885335 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8411 00:45:52.888711 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8412 00:45:52.892096 ==
8413 00:45:52.895571 Dram Type= 6, Freq= 0, CH_1, rank 0
8414 00:45:52.899002 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8415 00:45:52.899072 ==
8416 00:45:52.899132 DQS Delay:
8417 00:45:52.902410 DQS0 = 0, DQS1 = 0
8418 00:45:52.902497 DQM Delay:
8419 00:45:52.905311 DQM0 = 136, DQM1 = 132
8420 00:45:52.905395 DQ Delay:
8421 00:45:52.908363 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8422 00:45:52.912000 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =135
8423 00:45:52.915259 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =127
8424 00:45:52.918568 DQ12 =139, DQ13 =139, DQ14 =139, DQ15 =139
8425 00:45:52.918631
8426 00:45:52.918684
8427 00:45:52.922455 ==
8428 00:45:52.922528 Dram Type= 6, Freq= 0, CH_1, rank 0
8429 00:45:52.928612 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8430 00:45:52.928701 ==
8431 00:45:52.928782
8432 00:45:52.928861
8433 00:45:52.931793 TX Vref Scan disable
8434 00:45:52.931855 == TX Byte 0 ==
8435 00:45:52.934912 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8436 00:45:52.941486 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8437 00:45:52.941594 == TX Byte 1 ==
8438 00:45:52.945303 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8439 00:45:52.951805 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8440 00:45:52.951890 ==
8441 00:45:52.954924 Dram Type= 6, Freq= 0, CH_1, rank 0
8442 00:45:52.958355 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8443 00:45:52.958450 ==
8444 00:45:52.971053
8445 00:45:52.974035 TX Vref early break, caculate TX vref
8446 00:45:52.977776 TX Vref=16, minBit 1, minWin=23, winSum=381
8447 00:45:52.980864 TX Vref=18, minBit 0, minWin=23, winSum=388
8448 00:45:52.984495 TX Vref=20, minBit 0, minWin=24, winSum=401
8449 00:45:52.987673 TX Vref=22, minBit 1, minWin=24, winSum=410
8450 00:45:52.990880 TX Vref=24, minBit 0, minWin=25, winSum=417
8451 00:45:52.997703 TX Vref=26, minBit 0, minWin=25, winSum=424
8452 00:45:53.000696 TX Vref=28, minBit 0, minWin=25, winSum=429
8453 00:45:53.003929 TX Vref=30, minBit 2, minWin=25, winSum=425
8454 00:45:53.007620 TX Vref=32, minBit 0, minWin=24, winSum=413
8455 00:45:53.010518 TX Vref=34, minBit 0, minWin=23, winSum=403
8456 00:45:53.017139 [TxChooseVref] Worse bit 0, Min win 25, Win sum 429, Final Vref 28
8457 00:45:53.017218
8458 00:45:53.020651 Final TX Range 0 Vref 28
8459 00:45:53.020728
8460 00:45:53.020788 ==
8461 00:45:53.024051 Dram Type= 6, Freq= 0, CH_1, rank 0
8462 00:45:53.027116 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8463 00:45:53.027192 ==
8464 00:45:53.027251
8465 00:45:53.027305
8466 00:45:53.030948 TX Vref Scan disable
8467 00:45:53.037331 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8468 00:45:53.037443 == TX Byte 0 ==
8469 00:45:53.040367 u2DelayCellOfst[0]=20 cells (6 PI)
8470 00:45:53.043697 u2DelayCellOfst[1]=13 cells (4 PI)
8471 00:45:53.047576 u2DelayCellOfst[2]=0 cells (0 PI)
8472 00:45:53.050874 u2DelayCellOfst[3]=10 cells (3 PI)
8473 00:45:53.054120 u2DelayCellOfst[4]=10 cells (3 PI)
8474 00:45:53.057422 u2DelayCellOfst[5]=20 cells (6 PI)
8475 00:45:53.060679 u2DelayCellOfst[6]=20 cells (6 PI)
8476 00:45:53.063974 u2DelayCellOfst[7]=10 cells (3 PI)
8477 00:45:53.067423 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8478 00:45:53.070494 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8479 00:45:53.074272 == TX Byte 1 ==
8480 00:45:53.074371 u2DelayCellOfst[8]=0 cells (0 PI)
8481 00:45:53.077343 u2DelayCellOfst[9]=3 cells (1 PI)
8482 00:45:53.080842 u2DelayCellOfst[10]=13 cells (4 PI)
8483 00:45:53.083962 u2DelayCellOfst[11]=3 cells (1 PI)
8484 00:45:53.087484 u2DelayCellOfst[12]=13 cells (4 PI)
8485 00:45:53.090559 u2DelayCellOfst[13]=17 cells (5 PI)
8486 00:45:53.093997 u2DelayCellOfst[14]=17 cells (5 PI)
8487 00:45:53.097129 u2DelayCellOfst[15]=17 cells (5 PI)
8488 00:45:53.100220 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8489 00:45:53.106844 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8490 00:45:53.106911 DramC Write-DBI on
8491 00:45:53.106982 ==
8492 00:45:53.110393 Dram Type= 6, Freq= 0, CH_1, rank 0
8493 00:45:53.113999 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8494 00:45:53.116967 ==
8495 00:45:53.117055
8496 00:45:53.117137
8497 00:45:53.117219 TX Vref Scan disable
8498 00:45:53.120153 == TX Byte 0 ==
8499 00:45:53.123748 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8500 00:45:53.127307 == TX Byte 1 ==
8501 00:45:53.130423 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8502 00:45:53.133569 DramC Write-DBI off
8503 00:45:53.133631
8504 00:45:53.133688 [DATLAT]
8505 00:45:53.133743 Freq=1600, CH1 RK0
8506 00:45:53.133795
8507 00:45:53.137003 DATLAT Default: 0xf
8508 00:45:53.137092 0, 0xFFFF, sum = 0
8509 00:45:53.140494 1, 0xFFFF, sum = 0
8510 00:45:53.140586 2, 0xFFFF, sum = 0
8511 00:45:53.144111 3, 0xFFFF, sum = 0
8512 00:45:53.147313 4, 0xFFFF, sum = 0
8513 00:45:53.147401 5, 0xFFFF, sum = 0
8514 00:45:53.150551 6, 0xFFFF, sum = 0
8515 00:45:53.150615 7, 0xFFFF, sum = 0
8516 00:45:53.153814 8, 0xFFFF, sum = 0
8517 00:45:53.153874 9, 0xFFFF, sum = 0
8518 00:45:53.157006 10, 0xFFFF, sum = 0
8519 00:45:53.157098 11, 0xFFFF, sum = 0
8520 00:45:53.160148 12, 0xFFFF, sum = 0
8521 00:45:53.160237 13, 0xFFFF, sum = 0
8522 00:45:53.163444 14, 0x0, sum = 1
8523 00:45:53.163533 15, 0x0, sum = 2
8524 00:45:53.166690 16, 0x0, sum = 3
8525 00:45:53.166780 17, 0x0, sum = 4
8526 00:45:53.170439 best_step = 15
8527 00:45:53.170502
8528 00:45:53.170555 ==
8529 00:45:53.173347 Dram Type= 6, Freq= 0, CH_1, rank 0
8530 00:45:53.177027 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8531 00:45:53.177092 ==
8532 00:45:53.177148 RX Vref Scan: 1
8533 00:45:53.180285
8534 00:45:53.180373 Set Vref Range= 24 -> 127
8535 00:45:53.180453
8536 00:45:53.183512 RX Vref 24 -> 127, step: 1
8537 00:45:53.183596
8538 00:45:53.187310 RX Delay 27 -> 252, step: 4
8539 00:45:53.187370
8540 00:45:53.190299 Set Vref, RX VrefLevel [Byte0]: 24
8541 00:45:53.194015 [Byte1]: 24
8542 00:45:53.194101
8543 00:45:53.197276 Set Vref, RX VrefLevel [Byte0]: 25
8544 00:45:53.200312 [Byte1]: 25
8545 00:45:53.200378
8546 00:45:53.203989 Set Vref, RX VrefLevel [Byte0]: 26
8547 00:45:53.207140 [Byte1]: 26
8548 00:45:53.211056
8549 00:45:53.211127 Set Vref, RX VrefLevel [Byte0]: 27
8550 00:45:53.214242 [Byte1]: 27
8551 00:45:53.218042
8552 00:45:53.218135 Set Vref, RX VrefLevel [Byte0]: 28
8553 00:45:53.221697 [Byte1]: 28
8554 00:45:53.225884
8555 00:45:53.225966 Set Vref, RX VrefLevel [Byte0]: 29
8556 00:45:53.229430 [Byte1]: 29
8557 00:45:53.232882
8558 00:45:53.232978 Set Vref, RX VrefLevel [Byte0]: 30
8559 00:45:53.236698 [Byte1]: 30
8560 00:45:53.240827
8561 00:45:53.240898 Set Vref, RX VrefLevel [Byte0]: 31
8562 00:45:53.243800 [Byte1]: 31
8563 00:45:53.248328
8564 00:45:53.248395 Set Vref, RX VrefLevel [Byte0]: 32
8565 00:45:53.251916 [Byte1]: 32
8566 00:45:53.255936
8567 00:45:53.256027 Set Vref, RX VrefLevel [Byte0]: 33
8568 00:45:53.259165 [Byte1]: 33
8569 00:45:53.263649
8570 00:45:53.263716 Set Vref, RX VrefLevel [Byte0]: 34
8571 00:45:53.266675 [Byte1]: 34
8572 00:45:53.270565
8573 00:45:53.270629 Set Vref, RX VrefLevel [Byte0]: 35
8574 00:45:53.273887 [Byte1]: 35
8575 00:45:53.278132
8576 00:45:53.278198 Set Vref, RX VrefLevel [Byte0]: 36
8577 00:45:53.281654 [Byte1]: 36
8578 00:45:53.286290
8579 00:45:53.286363 Set Vref, RX VrefLevel [Byte0]: 37
8580 00:45:53.288907 [Byte1]: 37
8581 00:45:53.293226
8582 00:45:53.293315 Set Vref, RX VrefLevel [Byte0]: 38
8583 00:45:53.296949 [Byte1]: 38
8584 00:45:53.300765
8585 00:45:53.300833 Set Vref, RX VrefLevel [Byte0]: 39
8586 00:45:53.303996 [Byte1]: 39
8587 00:45:53.308420
8588 00:45:53.308486 Set Vref, RX VrefLevel [Byte0]: 40
8589 00:45:53.311603 [Byte1]: 40
8590 00:45:53.316249
8591 00:45:53.316338 Set Vref, RX VrefLevel [Byte0]: 41
8592 00:45:53.319158 [Byte1]: 41
8593 00:45:53.323740
8594 00:45:53.323840 Set Vref, RX VrefLevel [Byte0]: 42
8595 00:45:53.326674 [Byte1]: 42
8596 00:45:53.330825
8597 00:45:53.330919 Set Vref, RX VrefLevel [Byte0]: 43
8598 00:45:53.334204 [Byte1]: 43
8599 00:45:53.338749
8600 00:45:53.338841 Set Vref, RX VrefLevel [Byte0]: 44
8601 00:45:53.341648 [Byte1]: 44
8602 00:45:53.346260
8603 00:45:53.346351 Set Vref, RX VrefLevel [Byte0]: 45
8604 00:45:53.349786 [Byte1]: 45
8605 00:45:53.353429
8606 00:45:53.353522 Set Vref, RX VrefLevel [Byte0]: 46
8607 00:45:53.357002 [Byte1]: 46
8608 00:45:53.361518
8609 00:45:53.361642 Set Vref, RX VrefLevel [Byte0]: 47
8610 00:45:53.364670 [Byte1]: 47
8611 00:45:53.368479
8612 00:45:53.368564 Set Vref, RX VrefLevel [Byte0]: 48
8613 00:45:53.372389 [Byte1]: 48
8614 00:45:53.376223
8615 00:45:53.376306 Set Vref, RX VrefLevel [Byte0]: 49
8616 00:45:53.379403 [Byte1]: 49
8617 00:45:53.383699
8618 00:45:53.383784 Set Vref, RX VrefLevel [Byte0]: 50
8619 00:45:53.386882 [Byte1]: 50
8620 00:45:53.391393
8621 00:45:53.391477 Set Vref, RX VrefLevel [Byte0]: 51
8622 00:45:53.394556 [Byte1]: 51
8623 00:45:53.399089
8624 00:45:53.399171 Set Vref, RX VrefLevel [Byte0]: 52
8625 00:45:53.402182 [Byte1]: 52
8626 00:45:53.406458
8627 00:45:53.406517 Set Vref, RX VrefLevel [Byte0]: 53
8628 00:45:53.409680 [Byte1]: 53
8629 00:45:53.413718
8630 00:45:53.413806 Set Vref, RX VrefLevel [Byte0]: 54
8631 00:45:53.417448 [Byte1]: 54
8632 00:45:53.421406
8633 00:45:53.421466 Set Vref, RX VrefLevel [Byte0]: 55
8634 00:45:53.424498 [Byte1]: 55
8635 00:45:53.429248
8636 00:45:53.429312 Set Vref, RX VrefLevel [Byte0]: 56
8637 00:45:53.432347 [Byte1]: 56
8638 00:45:53.436360
8639 00:45:53.436448 Set Vref, RX VrefLevel [Byte0]: 57
8640 00:45:53.439881 [Byte1]: 57
8641 00:45:53.444073
8642 00:45:53.444135 Set Vref, RX VrefLevel [Byte0]: 58
8643 00:45:53.447333 [Byte1]: 58
8644 00:45:53.451535
8645 00:45:53.451624 Set Vref, RX VrefLevel [Byte0]: 59
8646 00:45:53.454623 [Byte1]: 59
8647 00:45:53.459477
8648 00:45:53.459546 Set Vref, RX VrefLevel [Byte0]: 60
8649 00:45:53.462629 [Byte1]: 60
8650 00:45:53.466497
8651 00:45:53.466584 Set Vref, RX VrefLevel [Byte0]: 61
8652 00:45:53.469860 [Byte1]: 61
8653 00:45:53.474402
8654 00:45:53.474492 Set Vref, RX VrefLevel [Byte0]: 62
8655 00:45:53.477483 [Byte1]: 62
8656 00:45:53.481909
8657 00:45:53.481981 Set Vref, RX VrefLevel [Byte0]: 63
8658 00:45:53.485112 [Byte1]: 63
8659 00:45:53.489488
8660 00:45:53.489609 Set Vref, RX VrefLevel [Byte0]: 64
8661 00:45:53.492442 [Byte1]: 64
8662 00:45:53.496937
8663 00:45:53.497025 Set Vref, RX VrefLevel [Byte0]: 65
8664 00:45:53.500219 [Byte1]: 65
8665 00:45:53.504662
8666 00:45:53.504757 Set Vref, RX VrefLevel [Byte0]: 66
8667 00:45:53.507800 [Byte1]: 66
8668 00:45:53.511978
8669 00:45:53.512071 Set Vref, RX VrefLevel [Byte0]: 67
8670 00:45:53.515031 [Byte1]: 67
8671 00:45:53.519404
8672 00:45:53.519480 Set Vref, RX VrefLevel [Byte0]: 68
8673 00:45:53.522555 [Byte1]: 68
8674 00:45:53.527048
8675 00:45:53.527123 Set Vref, RX VrefLevel [Byte0]: 69
8676 00:45:53.530234 [Byte1]: 69
8677 00:45:53.534685
8678 00:45:53.534759 Set Vref, RX VrefLevel [Byte0]: 70
8679 00:45:53.537886 [Byte1]: 70
8680 00:45:53.541914
8681 00:45:53.541990 Set Vref, RX VrefLevel [Byte0]: 71
8682 00:45:53.545212 [Byte1]: 71
8683 00:45:53.549679
8684 00:45:53.549754 Set Vref, RX VrefLevel [Byte0]: 72
8685 00:45:53.552553 [Byte1]: 72
8686 00:45:53.557270
8687 00:45:53.557345 Set Vref, RX VrefLevel [Byte0]: 73
8688 00:45:53.560237 [Byte1]: 73
8689 00:45:53.564774
8690 00:45:53.564849 Set Vref, RX VrefLevel [Byte0]: 74
8691 00:45:53.567768 [Byte1]: 74
8692 00:45:53.571856
8693 00:45:53.571957 Set Vref, RX VrefLevel [Byte0]: 75
8694 00:45:53.575482 [Byte1]: 75
8695 00:45:53.579700
8696 00:45:53.579766 Set Vref, RX VrefLevel [Byte0]: 76
8697 00:45:53.582767 [Byte1]: 76
8698 00:45:53.586979
8699 00:45:53.587072 Final RX Vref Byte 0 = 59 to rank0
8700 00:45:53.590206 Final RX Vref Byte 1 = 56 to rank0
8701 00:45:53.594070 Final RX Vref Byte 0 = 59 to rank1
8702 00:45:53.597037 Final RX Vref Byte 1 = 56 to rank1==
8703 00:45:53.600961 Dram Type= 6, Freq= 0, CH_1, rank 0
8704 00:45:53.606851 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8705 00:45:53.606963 ==
8706 00:45:53.607046 DQS Delay:
8707 00:45:53.610586 DQS0 = 0, DQS1 = 0
8708 00:45:53.610673 DQM Delay:
8709 00:45:53.610764 DQM0 = 134, DQM1 = 131
8710 00:45:53.613687 DQ Delay:
8711 00:45:53.616870 DQ0 =140, DQ1 =128, DQ2 =122, DQ3 =130
8712 00:45:53.619875 DQ4 =134, DQ5 =144, DQ6 =142, DQ7 =134
8713 00:45:53.623590 DQ8 =116, DQ9 =122, DQ10 =132, DQ11 =124
8714 00:45:53.626727 DQ12 =138, DQ13 =138, DQ14 =140, DQ15 =140
8715 00:45:53.626823
8716 00:45:53.626906
8717 00:45:53.626988
8718 00:45:53.630008 [DramC_TX_OE_Calibration] TA2
8719 00:45:53.633266 Original DQ_B0 (3 6) =30, OEN = 27
8720 00:45:53.636639 Original DQ_B1 (3 6) =30, OEN = 27
8721 00:45:53.639765 24, 0x0, End_B0=24 End_B1=24
8722 00:45:53.639866 25, 0x0, End_B0=25 End_B1=25
8723 00:45:53.643465 26, 0x0, End_B0=26 End_B1=26
8724 00:45:53.646594 27, 0x0, End_B0=27 End_B1=27
8725 00:45:53.649832 28, 0x0, End_B0=28 End_B1=28
8726 00:45:53.653492 29, 0x0, End_B0=29 End_B1=29
8727 00:45:53.653619 30, 0x0, End_B0=30 End_B1=30
8728 00:45:53.656688 31, 0x4545, End_B0=30 End_B1=30
8729 00:45:53.659835 Byte0 end_step=30 best_step=27
8730 00:45:53.663380 Byte1 end_step=30 best_step=27
8731 00:45:53.666349 Byte0 TX OE(2T, 0.5T) = (3, 3)
8732 00:45:53.669937 Byte1 TX OE(2T, 0.5T) = (3, 3)
8733 00:45:53.670012
8734 00:45:53.670070
8735 00:45:53.676642 [DQSOSCAuto] RK0, (LSB)MR18= 0x1927, (MSB)MR19= 0x303, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
8736 00:45:53.679879 CH1 RK0: MR19=303, MR18=1927
8737 00:45:53.686411 CH1_RK0: MR19=0x303, MR18=0x1927, DQSOSC=390, MR23=63, INC=24, DEC=16
8738 00:45:53.686488
8739 00:45:53.689919 ----->DramcWriteLeveling(PI) begin...
8740 00:45:53.689998 ==
8741 00:45:53.693115 Dram Type= 6, Freq= 0, CH_1, rank 1
8742 00:45:53.696363 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8743 00:45:53.696456 ==
8744 00:45:53.699895 Write leveling (Byte 0): 27 => 27
8745 00:45:53.702894 Write leveling (Byte 1): 27 => 27
8746 00:45:53.706463 DramcWriteLeveling(PI) end<-----
8747 00:45:53.706538
8748 00:45:53.706596 ==
8749 00:45:53.709531 Dram Type= 6, Freq= 0, CH_1, rank 1
8750 00:45:53.713428 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8751 00:45:53.713533 ==
8752 00:45:53.716655 [Gating] SW mode calibration
8753 00:45:53.722974 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8754 00:45:53.729838 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8755 00:45:53.732944 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8756 00:45:53.739357 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8757 00:45:53.742620 1 4 8 | B1->B0 | 2c2c 2323 | 1 0 | (1 1) (0 0)
8758 00:45:53.746519 1 4 12 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 1)
8759 00:45:53.752570 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8760 00:45:53.756032 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8761 00:45:53.759739 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8762 00:45:53.762924 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8763 00:45:53.769368 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8764 00:45:53.772954 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8765 00:45:53.775827 1 5 8 | B1->B0 | 2f2f 3434 | 1 1 | (1 0) (1 1)
8766 00:45:53.782514 1 5 12 | B1->B0 | 2424 2828 | 0 0 | (0 0) (0 0)
8767 00:45:53.786337 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8768 00:45:53.789498 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8769 00:45:53.795897 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8770 00:45:53.799017 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8771 00:45:53.802816 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8772 00:45:53.809253 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8773 00:45:53.812793 1 6 8 | B1->B0 | 3636 2323 | 1 0 | (0 0) (0 0)
8774 00:45:53.815523 1 6 12 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
8775 00:45:53.822591 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8776 00:45:53.826015 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8777 00:45:53.829230 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8778 00:45:53.836007 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8779 00:45:53.839257 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8780 00:45:53.842324 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8781 00:45:53.848874 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8782 00:45:53.852711 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8783 00:45:53.855909 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8784 00:45:53.862357 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8785 00:45:53.865899 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8786 00:45:53.869667 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8787 00:45:53.875873 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8788 00:45:53.879011 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8789 00:45:53.882717 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8790 00:45:53.885609 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8791 00:45:53.892329 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8792 00:45:53.895483 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8793 00:45:53.899417 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8794 00:45:53.905742 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8795 00:45:53.908998 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8796 00:45:53.912113 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8797 00:45:53.918942 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8798 00:45:53.922364 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8799 00:45:53.925866 Total UI for P1: 0, mck2ui 16
8800 00:45:53.928692 best dqsien dly found for B1: ( 1, 9, 6)
8801 00:45:53.932228 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8802 00:45:53.936057 Total UI for P1: 0, mck2ui 16
8803 00:45:53.939187 best dqsien dly found for B0: ( 1, 9, 14)
8804 00:45:53.942368 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8805 00:45:53.945659 best DQS1 dly(MCK, UI, PI) = (1, 9, 6)
8806 00:45:53.945734
8807 00:45:53.952106 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8808 00:45:53.955950 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 6)
8809 00:45:53.959244 [Gating] SW calibration Done
8810 00:45:53.959319 ==
8811 00:45:53.962520 Dram Type= 6, Freq= 0, CH_1, rank 1
8812 00:45:53.965765 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8813 00:45:53.965841 ==
8814 00:45:53.965900 RX Vref Scan: 0
8815 00:45:53.965954
8816 00:45:53.968819 RX Vref 0 -> 0, step: 1
8817 00:45:53.968901
8818 00:45:53.972218 RX Delay 0 -> 252, step: 8
8819 00:45:53.975465 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8820 00:45:53.979262 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8821 00:45:53.982125 iDelay=208, Bit 2, Center 123 (72 ~ 175) 104
8822 00:45:53.988525 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104
8823 00:45:53.992154 iDelay=208, Bit 4, Center 131 (80 ~ 183) 104
8824 00:45:53.995758 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8825 00:45:53.998933 iDelay=208, Bit 6, Center 143 (88 ~ 199) 112
8826 00:45:54.001898 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8827 00:45:54.008902 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8828 00:45:54.012174 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8829 00:45:54.015425 iDelay=208, Bit 10, Center 135 (80 ~ 191) 112
8830 00:45:54.018656 iDelay=208, Bit 11, Center 127 (72 ~ 183) 112
8831 00:45:54.021851 iDelay=208, Bit 12, Center 143 (88 ~ 199) 112
8832 00:45:54.028808 iDelay=208, Bit 13, Center 143 (88 ~ 199) 112
8833 00:45:54.031771 iDelay=208, Bit 14, Center 139 (88 ~ 191) 104
8834 00:45:54.035926 iDelay=208, Bit 15, Center 143 (88 ~ 199) 112
8835 00:45:54.036024 ==
8836 00:45:54.038780 Dram Type= 6, Freq= 0, CH_1, rank 1
8837 00:45:54.041864 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8838 00:45:54.045259 ==
8839 00:45:54.045349 DQS Delay:
8840 00:45:54.045430 DQS0 = 0, DQS1 = 0
8841 00:45:54.048721 DQM Delay:
8842 00:45:54.048814 DQM0 = 136, DQM1 = 133
8843 00:45:54.051758 DQ Delay:
8844 00:45:54.055569 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =131
8845 00:45:54.058906 DQ4 =131, DQ5 =151, DQ6 =143, DQ7 =135
8846 00:45:54.062040 DQ8 =119, DQ9 =119, DQ10 =135, DQ11 =127
8847 00:45:54.065152 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8848 00:45:54.065227
8849 00:45:54.065285
8850 00:45:54.065339 ==
8851 00:45:54.068953 Dram Type= 6, Freq= 0, CH_1, rank 1
8852 00:45:54.072306 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8853 00:45:54.072382 ==
8854 00:45:54.072441
8855 00:45:54.075348
8856 00:45:54.075424 TX Vref Scan disable
8857 00:45:54.078336 == TX Byte 0 ==
8858 00:45:54.081538 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8859 00:45:54.085406 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8860 00:45:54.088474 == TX Byte 1 ==
8861 00:45:54.092429 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8862 00:45:54.095387 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8863 00:45:54.095462 ==
8864 00:45:54.098431 Dram Type= 6, Freq= 0, CH_1, rank 1
8865 00:45:54.104863 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8866 00:45:54.104988 ==
8867 00:45:54.116125
8868 00:45:54.120050 TX Vref early break, caculate TX vref
8869 00:45:54.123377 TX Vref=16, minBit 2, minWin=23, winSum=387
8870 00:45:54.126503 TX Vref=18, minBit 2, minWin=23, winSum=393
8871 00:45:54.129691 TX Vref=20, minBit 0, minWin=24, winSum=406
8872 00:45:54.133355 TX Vref=22, minBit 0, minWin=24, winSum=411
8873 00:45:54.136659 TX Vref=24, minBit 0, minWin=25, winSum=417
8874 00:45:54.143158 TX Vref=26, minBit 0, minWin=25, winSum=425
8875 00:45:54.146233 TX Vref=28, minBit 0, minWin=25, winSum=428
8876 00:45:54.149681 TX Vref=30, minBit 0, minWin=25, winSum=419
8877 00:45:54.153084 TX Vref=32, minBit 0, minWin=25, winSum=413
8878 00:45:54.156171 TX Vref=34, minBit 0, minWin=24, winSum=404
8879 00:45:54.162887 [TxChooseVref] Worse bit 0, Min win 25, Win sum 428, Final Vref 28
8880 00:45:54.162964
8881 00:45:54.166532 Final TX Range 0 Vref 28
8882 00:45:54.166607
8883 00:45:54.166665 ==
8884 00:45:54.169555 Dram Type= 6, Freq= 0, CH_1, rank 1
8885 00:45:54.172917 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8886 00:45:54.172993 ==
8887 00:45:54.173052
8888 00:45:54.173105
8889 00:45:54.176146 TX Vref Scan disable
8890 00:45:54.183112 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8891 00:45:54.183230 == TX Byte 0 ==
8892 00:45:54.186070 u2DelayCellOfst[0]=17 cells (5 PI)
8893 00:45:54.189662 u2DelayCellOfst[1]=10 cells (3 PI)
8894 00:45:54.192900 u2DelayCellOfst[2]=0 cells (0 PI)
8895 00:45:54.196603 u2DelayCellOfst[3]=6 cells (2 PI)
8896 00:45:54.199543 u2DelayCellOfst[4]=6 cells (2 PI)
8897 00:45:54.203051 u2DelayCellOfst[5]=17 cells (5 PI)
8898 00:45:54.203127 u2DelayCellOfst[6]=17 cells (5 PI)
8899 00:45:54.206316 u2DelayCellOfst[7]=6 cells (2 PI)
8900 00:45:54.213158 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8901 00:45:54.216147 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8902 00:45:54.216238 == TX Byte 1 ==
8903 00:45:54.219535 u2DelayCellOfst[8]=0 cells (0 PI)
8904 00:45:54.223266 u2DelayCellOfst[9]=3 cells (1 PI)
8905 00:45:54.226278 u2DelayCellOfst[10]=10 cells (3 PI)
8906 00:45:54.229495 u2DelayCellOfst[11]=3 cells (1 PI)
8907 00:45:54.233336 u2DelayCellOfst[12]=13 cells (4 PI)
8908 00:45:54.236390 u2DelayCellOfst[13]=13 cells (4 PI)
8909 00:45:54.239537 u2DelayCellOfst[14]=13 cells (4 PI)
8910 00:45:54.242771 u2DelayCellOfst[15]=17 cells (5 PI)
8911 00:45:54.246639 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8912 00:45:54.249728 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8913 00:45:54.252934 DramC Write-DBI on
8914 00:45:54.253033 ==
8915 00:45:54.256593 Dram Type= 6, Freq= 0, CH_1, rank 1
8916 00:45:54.259555 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8917 00:45:54.259646 ==
8918 00:45:54.259767
8919 00:45:54.259869
8920 00:45:54.263186 TX Vref Scan disable
8921 00:45:54.266347 == TX Byte 0 ==
8922 00:45:54.269922 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8923 00:45:54.269983 == TX Byte 1 ==
8924 00:45:54.276125 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8925 00:45:54.276216 DramC Write-DBI off
8926 00:45:54.276302
8927 00:45:54.279842 [DATLAT]
8928 00:45:54.279933 Freq=1600, CH1 RK1
8929 00:45:54.280013
8930 00:45:54.283271 DATLAT Default: 0xf
8931 00:45:54.283345 0, 0xFFFF, sum = 0
8932 00:45:54.286291 1, 0xFFFF, sum = 0
8933 00:45:54.286393 2, 0xFFFF, sum = 0
8934 00:45:54.289631 3, 0xFFFF, sum = 0
8935 00:45:54.289709 4, 0xFFFF, sum = 0
8936 00:45:54.292795 5, 0xFFFF, sum = 0
8937 00:45:54.292880 6, 0xFFFF, sum = 0
8938 00:45:54.295951 7, 0xFFFF, sum = 0
8939 00:45:54.296038 8, 0xFFFF, sum = 0
8940 00:45:54.299305 9, 0xFFFF, sum = 0
8941 00:45:54.299397 10, 0xFFFF, sum = 0
8942 00:45:54.302593 11, 0xFFFF, sum = 0
8943 00:45:54.306371 12, 0xFFFF, sum = 0
8944 00:45:54.306458 13, 0xFFFF, sum = 0
8945 00:45:54.309519 14, 0x0, sum = 1
8946 00:45:54.309624 15, 0x0, sum = 2
8947 00:45:54.312849 16, 0x0, sum = 3
8948 00:45:54.312939 17, 0x0, sum = 4
8949 00:45:54.313021 best_step = 15
8950 00:45:54.313116
8951 00:45:54.316130 ==
8952 00:45:54.319241 Dram Type= 6, Freq= 0, CH_1, rank 1
8953 00:45:54.322501 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8954 00:45:54.322589 ==
8955 00:45:54.322669 RX Vref Scan: 0
8956 00:45:54.322748
8957 00:45:54.326174 RX Vref 0 -> 0, step: 1
8958 00:45:54.326268
8959 00:45:54.329309 RX Delay 19 -> 252, step: 4
8960 00:45:54.332763 iDelay=195, Bit 0, Center 138 (91 ~ 186) 96
8961 00:45:54.336118 iDelay=195, Bit 1, Center 130 (83 ~ 178) 96
8962 00:45:54.342853 iDelay=195, Bit 2, Center 122 (71 ~ 174) 104
8963 00:45:54.346562 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
8964 00:45:54.349656 iDelay=195, Bit 4, Center 130 (83 ~ 178) 96
8965 00:45:54.352894 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
8966 00:45:54.356084 iDelay=195, Bit 6, Center 144 (95 ~ 194) 100
8967 00:45:54.359349 iDelay=195, Bit 7, Center 134 (83 ~ 186) 104
8968 00:45:54.366034 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
8969 00:45:54.369301 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8970 00:45:54.372470 iDelay=195, Bit 10, Center 132 (83 ~ 182) 100
8971 00:45:54.376270 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
8972 00:45:54.379436 iDelay=195, Bit 12, Center 140 (87 ~ 194) 108
8973 00:45:54.386227 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
8974 00:45:54.389703 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
8975 00:45:54.392836 iDelay=195, Bit 15, Center 140 (91 ~ 190) 100
8976 00:45:54.392913 ==
8977 00:45:54.396175 Dram Type= 6, Freq= 0, CH_1, rank 1
8978 00:45:54.399310 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8979 00:45:54.402505 ==
8980 00:45:54.402581 DQS Delay:
8981 00:45:54.402641 DQS0 = 0, DQS1 = 0
8982 00:45:54.406143 DQM Delay:
8983 00:45:54.406220 DQM0 = 134, DQM1 = 130
8984 00:45:54.409029 DQ Delay:
8985 00:45:54.412440 DQ0 =138, DQ1 =130, DQ2 =122, DQ3 =130
8986 00:45:54.416126 DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =134
8987 00:45:54.419576 DQ8 =116, DQ9 =118, DQ10 =132, DQ11 =124
8988 00:45:54.422441 DQ12 =140, DQ13 =138, DQ14 =136, DQ15 =140
8989 00:45:54.422517
8990 00:45:54.422576
8991 00:45:54.422629
8992 00:45:54.425846 [DramC_TX_OE_Calibration] TA2
8993 00:45:54.428930 Original DQ_B0 (3 6) =30, OEN = 27
8994 00:45:54.432761 Original DQ_B1 (3 6) =30, OEN = 27
8995 00:45:54.432837 24, 0x0, End_B0=24 End_B1=24
8996 00:45:54.436067 25, 0x0, End_B0=25 End_B1=25
8997 00:45:54.439182 26, 0x0, End_B0=26 End_B1=26
8998 00:45:54.442849 27, 0x0, End_B0=27 End_B1=27
8999 00:45:54.445742 28, 0x0, End_B0=28 End_B1=28
9000 00:45:54.445818 29, 0x0, End_B0=29 End_B1=29
9001 00:45:54.449416 30, 0x0, End_B0=30 End_B1=30
9002 00:45:54.452391 31, 0x4141, End_B0=30 End_B1=30
9003 00:45:54.455628 Byte0 end_step=30 best_step=27
9004 00:45:54.459212 Byte1 end_step=30 best_step=27
9005 00:45:54.462419 Byte0 TX OE(2T, 0.5T) = (3, 3)
9006 00:45:54.462489 Byte1 TX OE(2T, 0.5T) = (3, 3)
9007 00:45:54.462584
9008 00:45:54.462652
9009 00:45:54.472258 [DQSOSCAuto] RK1, (LSB)MR18= 0x2409, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 391 ps
9010 00:45:54.476193 CH1 RK1: MR19=303, MR18=2409
9011 00:45:54.482388 CH1_RK1: MR19=0x303, MR18=0x2409, DQSOSC=391, MR23=63, INC=24, DEC=16
9012 00:45:54.482472 [RxdqsGatingPostProcess] freq 1600
9013 00:45:54.488806 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9014 00:45:54.492623 best DQS0 dly(2T, 0.5T) = (1, 1)
9015 00:45:54.495529 best DQS1 dly(2T, 0.5T) = (1, 1)
9016 00:45:54.498922 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9017 00:45:54.502539 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9018 00:45:54.505720 best DQS0 dly(2T, 0.5T) = (1, 1)
9019 00:45:54.509035 best DQS1 dly(2T, 0.5T) = (1, 1)
9020 00:45:54.512179 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9021 00:45:54.512256 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9022 00:45:54.516024 Pre-setting of DQS Precalculation
9023 00:45:54.522211 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9024 00:45:54.528983 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9025 00:45:54.535637 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9026 00:45:54.535735
9027 00:45:54.535810
9028 00:45:54.538882 [Calibration Summary] 3200 Mbps
9029 00:45:54.542002 CH 0, Rank 0
9030 00:45:54.542077 SW Impedance : PASS
9031 00:45:54.545781 DUTY Scan : NO K
9032 00:45:54.549065 ZQ Calibration : PASS
9033 00:45:54.549140 Jitter Meter : NO K
9034 00:45:54.552249 CBT Training : PASS
9035 00:45:54.552324 Write leveling : PASS
9036 00:45:54.555780 RX DQS gating : PASS
9037 00:45:54.558591 RX DQ/DQS(RDDQC) : PASS
9038 00:45:54.558666 TX DQ/DQS : PASS
9039 00:45:54.562242 RX DATLAT : PASS
9040 00:45:54.565409 RX DQ/DQS(Engine): PASS
9041 00:45:54.565485 TX OE : PASS
9042 00:45:54.569145 All Pass.
9043 00:45:54.569222
9044 00:45:54.569319 CH 0, Rank 1
9045 00:45:54.572429 SW Impedance : PASS
9046 00:45:54.572504 DUTY Scan : NO K
9047 00:45:54.575645 ZQ Calibration : PASS
9048 00:45:54.579463 Jitter Meter : NO K
9049 00:45:54.579538 CBT Training : PASS
9050 00:45:54.582714 Write leveling : PASS
9051 00:45:54.585776 RX DQS gating : PASS
9052 00:45:54.585851 RX DQ/DQS(RDDQC) : PASS
9053 00:45:54.588999 TX DQ/DQS : PASS
9054 00:45:54.589074 RX DATLAT : PASS
9055 00:45:54.592862 RX DQ/DQS(Engine): PASS
9056 00:45:54.595779 TX OE : PASS
9057 00:45:54.595856 All Pass.
9058 00:45:54.595920
9059 00:45:54.596001 CH 1, Rank 0
9060 00:45:54.599009 SW Impedance : PASS
9061 00:45:54.602396 DUTY Scan : NO K
9062 00:45:54.602471 ZQ Calibration : PASS
9063 00:45:54.605481 Jitter Meter : NO K
9064 00:45:54.608549 CBT Training : PASS
9065 00:45:54.608625 Write leveling : PASS
9066 00:45:54.611981 RX DQS gating : PASS
9067 00:45:54.615879 RX DQ/DQS(RDDQC) : PASS
9068 00:45:54.615955 TX DQ/DQS : PASS
9069 00:45:54.618960 RX DATLAT : PASS
9070 00:45:54.622211 RX DQ/DQS(Engine): PASS
9071 00:45:54.622286 TX OE : PASS
9072 00:45:54.625424 All Pass.
9073 00:45:54.625524
9074 00:45:54.625600 CH 1, Rank 1
9075 00:45:54.628976 SW Impedance : PASS
9076 00:45:54.629051 DUTY Scan : NO K
9077 00:45:54.632596 ZQ Calibration : PASS
9078 00:45:54.635441 Jitter Meter : NO K
9079 00:45:54.635518 CBT Training : PASS
9080 00:45:54.639273 Write leveling : PASS
9081 00:45:54.639350 RX DQS gating : PASS
9082 00:45:54.642594 RX DQ/DQS(RDDQC) : PASS
9083 00:45:54.645808 TX DQ/DQS : PASS
9084 00:45:54.645901 RX DATLAT : PASS
9085 00:45:54.648892 RX DQ/DQS(Engine): PASS
9086 00:45:54.652074 TX OE : PASS
9087 00:45:54.652151 All Pass.
9088 00:45:54.652208
9089 00:45:54.655283 DramC Write-DBI on
9090 00:45:54.655359 PER_BANK_REFRESH: Hybrid Mode
9091 00:45:54.658488 TX_TRACKING: ON
9092 00:45:54.668878 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9093 00:45:54.675385 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9094 00:45:54.681921 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9095 00:45:54.685185 [FAST_K] Save calibration result to emmc
9096 00:45:54.688727 sync common calibartion params.
9097 00:45:54.691663 sync cbt_mode0:1, 1:1
9098 00:45:54.691757 dram_init: ddr_geometry: 2
9099 00:45:54.694855 dram_init: ddr_geometry: 2
9100 00:45:54.698685 dram_init: ddr_geometry: 2
9101 00:45:54.701938 0:dram_rank_size:100000000
9102 00:45:54.702016 1:dram_rank_size:100000000
9103 00:45:54.708276 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9104 00:45:54.711547 DFS_SHUFFLE_HW_MODE: ON
9105 00:45:54.714786 dramc_set_vcore_voltage set vcore to 725000
9106 00:45:54.717958 Read voltage for 1600, 0
9107 00:45:54.718035 Vio18 = 0
9108 00:45:54.718095 Vcore = 725000
9109 00:45:54.721624 Vdram = 0
9110 00:45:54.721700 Vddq = 0
9111 00:45:54.721760 Vmddr = 0
9112 00:45:54.725069 switch to 3200 Mbps bootup
9113 00:45:54.725169 [DramcRunTimeConfig]
9114 00:45:54.727937 PHYPLL
9115 00:45:54.728014 DPM_CONTROL_AFTERK: ON
9116 00:45:54.731306 PER_BANK_REFRESH: ON
9117 00:45:54.734948 REFRESH_OVERHEAD_REDUCTION: ON
9118 00:45:54.735037 CMD_PICG_NEW_MODE: OFF
9119 00:45:54.738504 XRTWTW_NEW_MODE: ON
9120 00:45:54.738581 XRTRTR_NEW_MODE: ON
9121 00:45:54.741339 TX_TRACKING: ON
9122 00:45:54.741416 RDSEL_TRACKING: OFF
9123 00:45:54.744881 DQS Precalculation for DVFS: ON
9124 00:45:54.747943 RX_TRACKING: OFF
9125 00:45:54.748020 HW_GATING DBG: ON
9126 00:45:54.751420 ZQCS_ENABLE_LP4: ON
9127 00:45:54.751497 RX_PICG_NEW_MODE: ON
9128 00:45:54.755019 TX_PICG_NEW_MODE: ON
9129 00:45:54.755097 ENABLE_RX_DCM_DPHY: ON
9130 00:45:54.758289 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9131 00:45:54.761591 DUMMY_READ_FOR_TRACKING: OFF
9132 00:45:54.764843 !!! SPM_CONTROL_AFTERK: OFF
9133 00:45:54.768020 !!! SPM could not control APHY
9134 00:45:54.768098 IMPEDANCE_TRACKING: ON
9135 00:45:54.771602 TEMP_SENSOR: ON
9136 00:45:54.771703 HW_SAVE_FOR_SR: OFF
9137 00:45:54.774702 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9138 00:45:54.777960 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9139 00:45:54.781944 Read ODT Tracking: ON
9140 00:45:54.785114 Refresh Rate DeBounce: ON
9141 00:45:54.785190 DFS_NO_QUEUE_FLUSH: ON
9142 00:45:54.788500 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9143 00:45:54.791621 ENABLE_DFS_RUNTIME_MRW: OFF
9144 00:45:54.794861 DDR_RESERVE_NEW_MODE: ON
9145 00:45:54.794937 MR_CBT_SWITCH_FREQ: ON
9146 00:45:54.797743 =========================
9147 00:45:54.816961 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9148 00:45:54.820114 dram_init: ddr_geometry: 2
9149 00:45:54.838099 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9150 00:45:54.841415 dram_init: dram init end (result: 0)
9151 00:45:54.848034 DRAM-K: Full calibration passed in 24482 msecs
9152 00:45:54.851444 MRC: failed to locate region type 0.
9153 00:45:54.851537 DRAM rank0 size:0x100000000,
9154 00:45:54.854851 DRAM rank1 size=0x100000000
9155 00:45:54.864675 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9156 00:45:54.871743 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9157 00:45:54.878120 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9158 00:45:54.884974 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9159 00:45:54.888024 DRAM rank0 size:0x100000000,
9160 00:45:54.891227 DRAM rank1 size=0x100000000
9161 00:45:54.891317 CBMEM:
9162 00:45:54.894572 IMD: root @ 0xfffff000 254 entries.
9163 00:45:54.898368 IMD: root @ 0xffffec00 62 entries.
9164 00:45:54.901704 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9165 00:45:54.904689 WARNING: RO_VPD is uninitialized or empty.
9166 00:45:54.910953 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9167 00:45:54.918237 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9168 00:45:54.931160 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9169 00:45:54.942574 BS: romstage times (exec / console): total (unknown) / 24011 ms
9170 00:45:54.942654
9171 00:45:54.942713
9172 00:45:54.952159 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9173 00:45:54.955700 ARM64: Exception handlers installed.
9174 00:45:54.958957 ARM64: Testing exception
9175 00:45:54.962369 ARM64: Done test exception
9176 00:45:54.962436 Enumerating buses...
9177 00:45:54.965673 Show all devs... Before device enumeration.
9178 00:45:54.968808 Root Device: enabled 1
9179 00:45:54.972107 CPU_CLUSTER: 0: enabled 1
9180 00:45:54.972173 CPU: 00: enabled 1
9181 00:45:54.975398 Compare with tree...
9182 00:45:54.975462 Root Device: enabled 1
9183 00:45:54.979391 CPU_CLUSTER: 0: enabled 1
9184 00:45:54.982094 CPU: 00: enabled 1
9185 00:45:54.982160 Root Device scanning...
9186 00:45:54.985416 scan_static_bus for Root Device
9187 00:45:54.989110 CPU_CLUSTER: 0 enabled
9188 00:45:54.992079 scan_static_bus for Root Device done
9189 00:45:54.995249 scan_bus: bus Root Device finished in 8 msecs
9190 00:45:54.995319 done
9191 00:45:55.002413 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9192 00:45:55.005744 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9193 00:45:55.012137 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9194 00:45:55.015367 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9195 00:45:55.019063 Allocating resources...
9196 00:45:55.022337 Reading resources...
9197 00:45:55.025364 Root Device read_resources bus 0 link: 0
9198 00:45:55.025458 DRAM rank0 size:0x100000000,
9199 00:45:55.028821 DRAM rank1 size=0x100000000
9200 00:45:55.032375 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9201 00:45:55.035645 CPU: 00 missing read_resources
9202 00:45:55.038647 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9203 00:45:55.045687 Root Device read_resources bus 0 link: 0 done
9204 00:45:55.045764 Done reading resources.
9205 00:45:55.052157 Show resources in subtree (Root Device)...After reading.
9206 00:45:55.055374 Root Device child on link 0 CPU_CLUSTER: 0
9207 00:45:55.058980 CPU_CLUSTER: 0 child on link 0 CPU: 00
9208 00:45:55.068851 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9209 00:45:55.068923 CPU: 00
9210 00:45:55.072568 Root Device assign_resources, bus 0 link: 0
9211 00:45:55.075588 CPU_CLUSTER: 0 missing set_resources
9212 00:45:55.078633 Root Device assign_resources, bus 0 link: 0 done
9213 00:45:55.081946 Done setting resources.
9214 00:45:55.089237 Show resources in subtree (Root Device)...After assigning values.
9215 00:45:55.092049 Root Device child on link 0 CPU_CLUSTER: 0
9216 00:45:55.095317 CPU_CLUSTER: 0 child on link 0 CPU: 00
9217 00:45:55.105662 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9218 00:45:55.105736 CPU: 00
9219 00:45:55.108746 Done allocating resources.
9220 00:45:55.112033 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9221 00:45:55.115244 Enabling resources...
9222 00:45:55.115311 done.
9223 00:45:55.122290 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9224 00:45:55.122358 Initializing devices...
9225 00:45:55.125583 Root Device init
9226 00:45:55.125724 init hardware done!
9227 00:45:55.128685 0x00000018: ctrlr->caps
9228 00:45:55.131882 52.000 MHz: ctrlr->f_max
9229 00:45:55.131977 0.400 MHz: ctrlr->f_min
9230 00:45:55.135799 0x40ff8080: ctrlr->voltages
9231 00:45:55.135895 sclk: 390625
9232 00:45:55.138893 Bus Width = 1
9233 00:45:55.138981 sclk: 390625
9234 00:45:55.139060 Bus Width = 1
9235 00:45:55.142258 Early init status = 3
9236 00:45:55.145376 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9237 00:45:55.150031 in-header: 03 fc 00 00 01 00 00 00
9238 00:45:55.153634 in-data: 00
9239 00:45:55.156694 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9240 00:45:55.161360 in-header: 03 fd 00 00 00 00 00 00
9241 00:45:55.164612 in-data:
9242 00:45:55.167650 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9243 00:45:55.171815 in-header: 03 fc 00 00 01 00 00 00
9244 00:45:55.174780 in-data: 00
9245 00:45:55.177946 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9246 00:45:55.183856 in-header: 03 fd 00 00 00 00 00 00
9247 00:45:55.186938 in-data:
9248 00:45:55.189964 [SSUSB] Setting up USB HOST controller...
9249 00:45:55.193655 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9250 00:45:55.196839 [SSUSB] phy power-on done.
9251 00:45:55.199895 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9252 00:45:55.206715 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9253 00:45:55.210117 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9254 00:45:55.216446 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9255 00:45:55.223252 read SPI 0x50eb0 0x2ad3: 1175 us, 9330 KB/s, 74.640 Mbps
9256 00:45:55.229644 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9257 00:45:55.236518 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9258 00:45:55.243175 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9259 00:45:55.246992 SPM: binary array size = 0x9dc
9260 00:45:55.249665 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9261 00:45:55.256847 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9262 00:45:55.263451 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9263 00:45:55.266532 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9264 00:45:55.273349 configure_display: Starting display init
9265 00:45:55.306945 anx7625_power_on_init: Init interface.
9266 00:45:55.310144 anx7625_disable_pd_protocol: Disabled PD feature.
9267 00:45:55.313376 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9268 00:45:55.341530 anx7625_start_dp_work: Secure OCM version=00
9269 00:45:55.344769 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9270 00:45:55.359657 sp_tx_get_edid_block: EDID Block = 1
9271 00:45:55.462406 Extracted contents:
9272 00:45:55.465540 header: 00 ff ff ff ff ff ff 00
9273 00:45:55.468868 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9274 00:45:55.472117 version: 01 04
9275 00:45:55.475454 basic params: 95 1f 11 78 0a
9276 00:45:55.478620 chroma info: 76 90 94 55 54 90 27 21 50 54
9277 00:45:55.481806 established: 00 00 00
9278 00:45:55.488397 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9279 00:45:55.492156 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9280 00:45:55.498487 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9281 00:45:55.504919 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9282 00:45:55.511371 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9283 00:45:55.514977 extensions: 00
9284 00:45:55.515054 checksum: fb
9285 00:45:55.515114
9286 00:45:55.518409 Manufacturer: IVO Model 57d Serial Number 0
9287 00:45:55.521687 Made week 0 of 2020
9288 00:45:55.521763 EDID version: 1.4
9289 00:45:55.524704 Digital display
9290 00:45:55.528007 6 bits per primary color channel
9291 00:45:55.528084 DisplayPort interface
9292 00:45:55.531261 Maximum image size: 31 cm x 17 cm
9293 00:45:55.534628 Gamma: 220%
9294 00:45:55.534703 Check DPMS levels
9295 00:45:55.537862 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9296 00:45:55.544598 First detailed timing is preferred timing
9297 00:45:55.544727 Established timings supported:
9298 00:45:55.548381 Standard timings supported:
9299 00:45:55.551265 Detailed timings
9300 00:45:55.554428 Hex of detail: 383680a07038204018303c0035ae10000019
9301 00:45:55.557890 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9302 00:45:55.564685 0780 0798 07c8 0820 hborder 0
9303 00:45:55.567733 0438 043b 0447 0458 vborder 0
9304 00:45:55.571258 -hsync -vsync
9305 00:45:55.571334 Did detailed timing
9306 00:45:55.577710 Hex of detail: 000000000000000000000000000000000000
9307 00:45:55.577799 Manufacturer-specified data, tag 0
9308 00:45:55.584938 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9309 00:45:55.588038 ASCII string: InfoVision
9310 00:45:55.591365 Hex of detail: 000000fe00523134304e574635205248200a
9311 00:45:55.594631 ASCII string: R140NWF5 RH
9312 00:45:55.594718 Checksum
9313 00:45:55.597904 Checksum: 0xfb (valid)
9314 00:45:55.601119 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9315 00:45:55.604416 DSI data_rate: 832800000 bps
9316 00:45:55.608074 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9317 00:45:55.614610 anx7625_parse_edid: pixelclock(138800).
9318 00:45:55.617790 hactive(1920), hsync(48), hfp(24), hbp(88)
9319 00:45:55.621041 vactive(1080), vsync(12), vfp(3), vbp(17)
9320 00:45:55.624886 anx7625_dsi_config: config dsi.
9321 00:45:55.631209 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9322 00:45:55.644021 anx7625_dsi_config: success to config DSI
9323 00:45:55.647055 anx7625_dp_start: MIPI phy setup OK.
9324 00:45:55.650620 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9325 00:45:55.653870 mtk_ddp_mode_set invalid vrefresh 60
9326 00:45:55.657604 main_disp_path_setup
9327 00:45:55.657695 ovl_layer_smi_id_en
9328 00:45:55.660743 ovl_layer_smi_id_en
9329 00:45:55.660861 ccorr_config
9330 00:45:55.660962 aal_config
9331 00:45:55.663818 gamma_config
9332 00:45:55.663924 postmask_config
9333 00:45:55.667148 dither_config
9334 00:45:55.670367 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9335 00:45:55.677505 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9336 00:45:55.680934 Root Device init finished in 552 msecs
9337 00:45:55.681025 CPU_CLUSTER: 0 init
9338 00:45:55.690574 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9339 00:45:55.693964 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9340 00:45:55.697390 APU_MBOX 0x190000b0 = 0x10001
9341 00:45:55.700459 APU_MBOX 0x190001b0 = 0x10001
9342 00:45:55.703787 APU_MBOX 0x190005b0 = 0x10001
9343 00:45:55.707380 APU_MBOX 0x190006b0 = 0x10001
9344 00:45:55.710501 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9345 00:45:55.723375 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9346 00:45:55.735641 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9347 00:45:55.742030 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9348 00:45:55.753435 read SPI 0x61c74 0xe8ef: 6411 us, 9301 KB/s, 74.408 Mbps
9349 00:45:55.762993 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9350 00:45:55.766154 CPU_CLUSTER: 0 init finished in 81 msecs
9351 00:45:55.769337 Devices initialized
9352 00:45:55.772608 Show all devs... After init.
9353 00:45:55.772684 Root Device: enabled 1
9354 00:45:55.775770 CPU_CLUSTER: 0: enabled 1
9355 00:45:55.779178 CPU: 00: enabled 1
9356 00:45:55.783041 BS: BS_DEV_INIT run times (exec / console): 210 / 447 ms
9357 00:45:55.786178 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9358 00:45:55.789255 ELOG: NV offset 0x57f000 size 0x1000
9359 00:45:55.796398 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9360 00:45:55.802860 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9361 00:45:55.806135 ELOG: Event(17) added with size 13 at 2024-06-16 00:45:56 UTC
9362 00:45:55.809324 out: cmd=0x121: 03 db 21 01 00 00 00 00
9363 00:45:55.813047 in-header: 03 55 00 00 2c 00 00 00
9364 00:45:55.826167 in-data: e8 72 00 00 00 00 00 00 0a 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9365 00:45:55.833087 ELOG: Event(A1) added with size 10 at 2024-06-16 00:45:56 UTC
9366 00:45:55.840082 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
9367 00:45:55.843219 ELOG: Event(A0) added with size 9 at 2024-06-16 00:45:56 UTC
9368 00:45:55.849725 elog_add_boot_reason: Logged dev mode boot
9369 00:45:55.853488 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9370 00:45:55.856643 Finalize devices...
9371 00:45:55.856710 Devices finalized
9372 00:45:55.863004 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9373 00:45:55.866716 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
9374 00:45:55.869882 in-header: 03 07 00 00 08 00 00 00
9375 00:45:55.873154 in-data: aa e4 47 04 13 02 00 00
9376 00:45:55.873246 Chrome EC: UHEPI supported
9377 00:45:55.879765 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
9378 00:45:55.883443 in-header: 03 a9 00 00 08 00 00 00
9379 00:45:55.886763 in-data: 84 60 60 08 00 00 00 00
9380 00:45:55.893576 ELOG: Event(91) added with size 10 at 2024-06-16 00:45:56 UTC
9381 00:45:55.896747 Chrome EC: clear events_b mask to 0x0000000020004000
9382 00:45:55.903321 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
9383 00:45:55.907589 in-header: 03 fd 00 00 00 00 00 00
9384 00:45:55.911239 in-data:
9385 00:45:55.914328 BS: BS_WRITE_TABLES entry times (exec / console): 2 / 46 ms
9386 00:45:55.917600 Writing coreboot table at 0xffe64000
9387 00:45:55.924566 0. 000000000010a000-0000000000113fff: RAMSTAGE
9388 00:45:55.927632 1. 0000000040000000-00000000400fffff: RAM
9389 00:45:55.931595 2. 0000000040100000-000000004032afff: RAMSTAGE
9390 00:45:55.934744 3. 000000004032b000-00000000545fffff: RAM
9391 00:45:55.937861 4. 0000000054600000-000000005465ffff: BL31
9392 00:45:55.941446 5. 0000000054660000-00000000ffe63fff: RAM
9393 00:45:55.947904 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9394 00:45:55.951171 7. 0000000100000000-000000023fffffff: RAM
9395 00:45:55.954395 Passing 5 GPIOs to payload:
9396 00:45:55.957696 NAME | PORT | POLARITY | VALUE
9397 00:45:55.964456 EC in RW | 0x000000aa | low | undefined
9398 00:45:55.968002 EC interrupt | 0x00000005 | low | undefined
9399 00:45:55.971204 TPM interrupt | 0x000000ab | high | undefined
9400 00:45:55.977913 SD card detect | 0x00000011 | high | undefined
9401 00:45:55.981150 speaker enable | 0x00000093 | high | undefined
9402 00:45:55.984320 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9403 00:45:55.987489 in-header: 03 f9 00 00 02 00 00 00
9404 00:45:55.991201 in-data: 02 00
9405 00:45:55.994426 ADC[4]: Raw value=904726 ID=7
9406 00:45:55.994502 ADC[3]: Raw value=213441 ID=1
9407 00:45:55.997940 RAM Code: 0x71
9408 00:45:56.001076 ADC[6]: Raw value=75332 ID=0
9409 00:45:56.001153 ADC[5]: Raw value=212703 ID=1
9410 00:45:56.004365 SKU Code: 0x1
9411 00:45:56.007452 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 201c
9412 00:45:56.010693 coreboot table: 964 bytes.
9413 00:45:56.014539 IMD ROOT 0. 0xfffff000 0x00001000
9414 00:45:56.017578 IMD SMALL 1. 0xffffe000 0x00001000
9415 00:45:56.021147 RO MCACHE 2. 0xffffc000 0x00001104
9416 00:45:56.024292 CONSOLE 3. 0xfff7c000 0x00080000
9417 00:45:56.027620 FMAP 4. 0xfff7b000 0x00000452
9418 00:45:56.030751 TIME STAMP 5. 0xfff7a000 0x00000910
9419 00:45:56.034007 VBOOT WORK 6. 0xfff66000 0x00014000
9420 00:45:56.037895 RAMOOPS 7. 0xffe66000 0x00100000
9421 00:45:56.041052 COREBOOT 8. 0xffe64000 0x00002000
9422 00:45:56.044212 IMD small region:
9423 00:45:56.047343 IMD ROOT 0. 0xffffec00 0x00000400
9424 00:45:56.051140 VPD 1. 0xffffeb80 0x0000006c
9425 00:45:56.054329 MMC STATUS 2. 0xffffeb60 0x00000004
9426 00:45:56.057495 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9427 00:45:56.063950 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9428 00:45:56.104605 read SPI 0x3990ec 0x4f1b0: 34851 us, 9297 KB/s, 74.376 Mbps
9429 00:45:56.108127 Checking segment from ROM address 0x40100000
9430 00:45:56.111398 Checking segment from ROM address 0x4010001c
9431 00:45:56.118333 Loading segment from ROM address 0x40100000
9432 00:45:56.118425 code (compression=0)
9433 00:45:56.128252 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9434 00:45:56.134916 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9435 00:45:56.135039 it's not compressed!
9436 00:45:56.141510 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9437 00:45:56.144618 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9438 00:45:56.165083 Loading segment from ROM address 0x4010001c
9439 00:45:56.165177 Entry Point 0x80000000
9440 00:45:56.168319 Loaded segments
9441 00:45:56.172261 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9442 00:45:56.178548 Jumping to boot code at 0x80000000(0xffe64000)
9443 00:45:56.185528 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9444 00:45:56.191590 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9445 00:45:56.199865 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9446 00:45:56.202954 Checking segment from ROM address 0x40100000
9447 00:45:56.206417 Checking segment from ROM address 0x4010001c
9448 00:45:56.212921 Loading segment from ROM address 0x40100000
9449 00:45:56.212999 code (compression=1)
9450 00:45:56.219728 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9451 00:45:56.229657 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9452 00:45:56.229734 using LZMA
9453 00:45:56.237943 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9454 00:45:56.244644 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9455 00:45:56.247759 Loading segment from ROM address 0x4010001c
9456 00:45:56.247835 Entry Point 0x54601000
9457 00:45:56.251562 Loaded segments
9458 00:45:56.254746 NOTICE: MT8192 bl31_setup
9459 00:45:56.261724 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9460 00:45:56.264890 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9461 00:45:56.268173 WARNING: region 0:
9462 00:45:56.271475 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9463 00:45:56.271550 WARNING: region 1:
9464 00:45:56.278676 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9465 00:45:56.281880 WARNING: region 2:
9466 00:45:56.285182 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9467 00:45:56.288454 WARNING: region 3:
9468 00:45:56.291639 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9469 00:45:56.295398 WARNING: region 4:
9470 00:45:56.301418 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9471 00:45:56.301519 WARNING: region 5:
9472 00:45:56.305284 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9473 00:45:56.308543 WARNING: region 6:
9474 00:45:56.311756 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9475 00:45:56.311831 WARNING: region 7:
9476 00:45:56.318003 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9477 00:45:56.325070 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9478 00:45:56.328077 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9479 00:45:56.331547 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9480 00:45:56.338537 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9481 00:45:56.341581 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9482 00:45:56.345028 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9483 00:45:56.351660 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9484 00:45:56.355068 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9485 00:45:56.361375 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9486 00:45:56.364859 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9487 00:45:56.368116 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9488 00:45:56.374894 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9489 00:45:56.377966 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9490 00:45:56.381785 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9491 00:45:56.388011 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9492 00:45:56.391158 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9493 00:45:56.398178 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9494 00:45:56.401212 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9495 00:45:56.404912 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9496 00:45:56.411294 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9497 00:45:56.414438 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9498 00:45:56.418079 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9499 00:45:56.424958 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9500 00:45:56.428184 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9501 00:45:56.434563 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9502 00:45:56.438090 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9503 00:45:56.441247 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9504 00:45:56.448081 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9505 00:45:56.451199 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9506 00:45:56.457970 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9507 00:45:56.461294 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9508 00:45:56.464294 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9509 00:45:56.471328 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9510 00:45:56.474147 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9511 00:45:56.477791 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9512 00:45:56.480890 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9513 00:45:56.487848 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9514 00:45:56.491250 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9515 00:45:56.494199 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9516 00:45:56.497686 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9517 00:45:56.504622 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9518 00:45:56.507726 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9519 00:45:56.511342 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9520 00:45:56.514257 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9521 00:45:56.520737 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9522 00:45:56.524346 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9523 00:45:56.527431 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9524 00:45:56.534510 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9525 00:45:56.537719 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9526 00:45:56.541024 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9527 00:45:56.547652 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9528 00:45:56.550902 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9529 00:45:56.558107 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9530 00:45:56.561266 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9531 00:45:56.564738 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9532 00:45:56.571230 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9533 00:45:56.574402 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9534 00:45:56.581303 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9535 00:45:56.584473 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9536 00:45:56.591080 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9537 00:45:56.594274 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9538 00:45:56.598105 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9539 00:45:56.604190 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9540 00:45:56.607677 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9541 00:45:56.614318 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9542 00:45:56.617838 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9543 00:45:56.624306 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9544 00:45:56.627723 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9545 00:45:56.634144 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9546 00:45:56.637358 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9547 00:45:56.640492 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9548 00:45:56.647736 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9549 00:45:56.650757 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9550 00:45:56.657720 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9551 00:45:56.660959 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9552 00:45:56.667429 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9553 00:45:56.670507 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9554 00:45:56.677226 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9555 00:45:56.680769 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9556 00:45:56.683921 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9557 00:45:56.690696 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9558 00:45:56.693879 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9559 00:45:56.700916 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9560 00:45:56.703978 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9561 00:45:56.710360 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9562 00:45:56.714033 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9563 00:45:56.717001 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9564 00:45:56.724125 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9565 00:45:56.727731 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9566 00:45:56.733872 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9567 00:45:56.736982 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9568 00:45:56.744080 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9569 00:45:56.747280 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9570 00:45:56.750369 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9571 00:45:56.757332 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9572 00:45:56.760259 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9573 00:45:56.767125 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9574 00:45:56.770414 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9575 00:45:56.774310 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9576 00:45:56.777506 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9577 00:45:56.784150 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9578 00:45:56.787241 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9579 00:45:56.790529 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9580 00:45:56.796932 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9581 00:45:56.800447 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9582 00:45:56.807376 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9583 00:45:56.810569 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9584 00:45:56.814033 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9585 00:45:56.820865 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9586 00:45:56.823957 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9587 00:45:56.827054 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9588 00:45:56.834162 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9589 00:45:56.837410 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9590 00:45:56.843970 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9591 00:45:56.846982 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9592 00:45:56.853516 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9593 00:45:56.857138 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9594 00:45:56.860418 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9595 00:45:56.863673 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9596 00:45:56.870637 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9597 00:45:56.873734 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9598 00:45:56.877238 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9599 00:45:56.880489 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9600 00:45:56.886869 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9601 00:45:56.890100 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9602 00:45:56.893968 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9603 00:45:56.900273 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9604 00:45:56.903631 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9605 00:45:56.910345 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9606 00:45:56.913461 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9607 00:45:56.917008 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9608 00:45:56.923344 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9609 00:45:56.926970 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9610 00:45:56.933675 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9611 00:45:56.936947 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9612 00:45:56.940178 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9613 00:45:56.946527 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9614 00:45:56.949967 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9615 00:45:56.956685 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9616 00:45:56.960280 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9617 00:45:56.963486 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9618 00:45:56.969976 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9619 00:45:56.973168 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9620 00:45:56.976684 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9621 00:45:56.983190 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9622 00:45:56.986657 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9623 00:45:56.993112 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9624 00:45:56.996680 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9625 00:45:56.999890 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9626 00:45:57.007013 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9627 00:45:57.010388 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9628 00:45:57.016948 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9629 00:45:57.019943 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9630 00:45:57.023067 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9631 00:45:57.030418 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9632 00:45:57.033841 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9633 00:45:57.039890 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9634 00:45:57.043109 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9635 00:45:57.046566 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9636 00:45:57.053661 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9637 00:45:57.056969 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9638 00:45:57.060172 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9639 00:45:57.066930 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9640 00:45:57.070292 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9641 00:45:57.076681 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9642 00:45:57.080441 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9643 00:45:57.083602 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9644 00:45:57.090046 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9645 00:45:57.093830 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9646 00:45:57.097038 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9647 00:45:57.103525 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9648 00:45:57.107017 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9649 00:45:57.113509 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9650 00:45:57.116562 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9651 00:45:57.120100 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9652 00:45:57.126689 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9653 00:45:57.130030 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9654 00:45:57.136847 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9655 00:45:57.140060 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9656 00:45:57.143220 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9657 00:45:57.150099 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9658 00:45:57.153712 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9659 00:45:57.156808 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9660 00:45:57.163626 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9661 00:45:57.166591 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9662 00:45:57.173405 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9663 00:45:57.176992 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9664 00:45:57.180016 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9665 00:45:57.186791 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9666 00:45:57.190108 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9667 00:45:57.197068 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9668 00:45:57.200264 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9669 00:45:57.203466 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9670 00:45:57.209864 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9671 00:45:57.213720 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9672 00:45:57.220282 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9673 00:45:57.223467 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9674 00:45:57.230168 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9675 00:45:57.233424 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9676 00:45:57.237010 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9677 00:45:57.243380 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9678 00:45:57.246528 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9679 00:45:57.253501 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9680 00:45:57.256396 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9681 00:45:57.260222 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9682 00:45:57.267125 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9683 00:45:57.270218 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9684 00:45:57.276630 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9685 00:45:57.280238 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9686 00:45:57.283186 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9687 00:45:57.290117 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9688 00:45:57.293381 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9689 00:45:57.300040 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9690 00:45:57.303607 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9691 00:45:57.309784 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9692 00:45:57.313660 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9693 00:45:57.316922 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9694 00:45:57.323361 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9695 00:45:57.326606 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9696 00:45:57.333107 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9697 00:45:57.336987 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9698 00:45:57.340349 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9699 00:45:57.346892 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9700 00:45:57.350042 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9701 00:45:57.356984 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9702 00:45:57.360166 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9703 00:45:57.366374 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9704 00:45:57.370007 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9705 00:45:57.373078 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9706 00:45:57.376519 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9707 00:45:57.383048 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9708 00:45:57.386264 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9709 00:45:57.389988 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9710 00:45:57.393237 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9711 00:45:57.399455 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9712 00:45:57.403249 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9713 00:45:57.409664 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9714 00:45:57.413162 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9715 00:45:57.416719 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9716 00:45:57.422916 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9717 00:45:57.426474 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9718 00:45:57.429786 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9719 00:45:57.436302 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9720 00:45:57.439471 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9721 00:45:57.442733 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9722 00:45:57.449707 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9723 00:45:57.452923 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9724 00:45:57.459758 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9725 00:45:57.462790 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9726 00:45:57.466100 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9727 00:45:57.472906 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9728 00:45:57.476603 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9729 00:45:57.479677 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9730 00:45:57.486419 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9731 00:45:57.489340 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9732 00:45:57.492614 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9733 00:45:57.499370 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9734 00:45:57.503006 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9735 00:45:57.506129 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9736 00:45:57.512743 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9737 00:45:57.515934 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9738 00:45:57.522671 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9739 00:45:57.526354 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9740 00:45:57.529689 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9741 00:45:57.536319 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9742 00:45:57.539555 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9743 00:45:57.542685 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9744 00:45:57.549436 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9745 00:45:57.552866 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9746 00:45:57.556055 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9747 00:45:57.562642 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9748 00:45:57.566227 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9749 00:45:57.569127 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9750 00:45:57.572364 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9751 00:45:57.576109 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9752 00:45:57.582683 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9753 00:45:57.585745 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9754 00:45:57.589470 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9755 00:45:57.592707 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9756 00:45:57.599128 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9757 00:45:57.602292 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9758 00:45:57.606255 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9759 00:45:57.612574 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9760 00:45:57.615828 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9761 00:45:57.622821 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9762 00:45:57.626077 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9763 00:45:57.629154 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9764 00:45:57.635658 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9765 00:45:57.638991 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9766 00:45:57.646040 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9767 00:45:57.649127 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9768 00:45:57.652622 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9769 00:45:57.659419 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9770 00:45:57.662564 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9771 00:45:57.669002 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9772 00:45:57.672157 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9773 00:45:57.678546 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9774 00:45:57.681967 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9775 00:45:57.685690 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9776 00:45:57.692390 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9777 00:45:57.695621 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9778 00:45:57.702128 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9779 00:45:57.705394 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9780 00:45:57.708562 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9781 00:45:57.715578 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9782 00:45:57.718706 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9783 00:45:57.725698 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9784 00:45:57.728681 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9785 00:45:57.732452 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9786 00:45:57.738630 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9787 00:45:57.742380 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9788 00:45:57.748932 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9789 00:45:57.752304 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9790 00:45:57.755357 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9791 00:45:57.761922 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9792 00:45:57.765481 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9793 00:45:57.772311 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9794 00:45:57.775821 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9795 00:45:57.778732 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9796 00:45:57.785574 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9797 00:45:57.788786 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9798 00:45:57.795251 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9799 00:45:57.798758 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9800 00:45:57.802381 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9801 00:45:57.808788 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9802 00:45:57.812079 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9803 00:45:57.818537 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9804 00:45:57.821675 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9805 00:45:57.828818 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9806 00:45:57.831971 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9807 00:45:57.835002 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9808 00:45:57.841845 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9809 00:45:57.845079 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9810 00:45:57.852063 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9811 00:45:57.855197 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9812 00:45:57.858437 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9813 00:45:57.865377 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9814 00:45:57.868373 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9815 00:45:57.871925 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9816 00:45:57.878321 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9817 00:45:57.881781 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9818 00:45:57.888674 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9819 00:45:57.891785 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9820 00:45:57.898401 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9821 00:45:57.901668 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9822 00:45:57.904798 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9823 00:45:57.911401 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9824 00:45:57.914717 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9825 00:45:57.921525 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9826 00:45:57.924871 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9827 00:45:57.928072 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9828 00:45:57.935190 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9829 00:45:57.938355 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9830 00:45:57.945203 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9831 00:45:57.948075 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9832 00:45:57.951576 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9833 00:45:57.958402 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9834 00:45:57.961573 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9835 00:45:57.968442 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9836 00:45:57.971739 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9837 00:45:57.978068 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9838 00:45:57.981200 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9839 00:45:57.984478 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9840 00:45:57.991316 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9841 00:45:57.994725 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9842 00:45:58.001185 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9843 00:45:58.004708 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9844 00:45:58.011228 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9845 00:45:58.014461 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9846 00:45:58.021122 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9847 00:45:58.024532 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9848 00:45:58.027836 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9849 00:45:58.034523 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9850 00:45:58.037737 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9851 00:45:58.044919 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9852 00:45:58.048095 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9853 00:45:58.054353 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9854 00:45:58.057942 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9855 00:45:58.060919 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9856 00:45:58.068191 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9857 00:45:58.071235 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9858 00:45:58.077665 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9859 00:45:58.080823 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9860 00:45:58.087902 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9861 00:45:58.091166 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9862 00:45:58.094321 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9863 00:45:58.101013 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9864 00:45:58.104130 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9865 00:45:58.111309 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9866 00:45:58.114308 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9867 00:45:58.121207 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9868 00:45:58.124399 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9869 00:45:58.131018 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9870 00:45:58.134206 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9871 00:45:58.137725 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9872 00:45:58.144226 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9873 00:45:58.147588 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9874 00:45:58.154300 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9875 00:45:58.157453 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9876 00:45:58.164479 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9877 00:45:58.167712 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9878 00:45:58.170867 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9879 00:45:58.177743 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9880 00:45:58.181024 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9881 00:45:58.187429 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9882 00:45:58.190653 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9883 00:45:58.197194 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9884 00:45:58.200993 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9885 00:45:58.204122 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9886 00:45:58.210697 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9887 00:45:58.213798 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9888 00:45:58.220936 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9889 00:45:58.223780 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9890 00:45:58.230911 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9891 00:45:58.234146 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9892 00:45:58.240923 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9893 00:45:58.243707 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9894 00:45:58.250876 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9895 00:45:58.254029 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9896 00:45:58.260733 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9897 00:45:58.263826 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9898 00:45:58.270461 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9899 00:45:58.274075 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9900 00:45:58.280778 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9901 00:45:58.283739 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9902 00:45:58.290799 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9903 00:45:58.294157 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9904 00:45:58.300513 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9905 00:45:58.303683 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9906 00:45:58.310402 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9907 00:45:58.314030 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9908 00:45:58.320480 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9909 00:45:58.323594 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9910 00:45:58.330632 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9911 00:45:58.334093 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9912 00:45:58.337301 INFO: [APUAPC] vio 0
9913 00:45:58.340451 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9914 00:45:58.343659 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9915 00:45:58.346911 INFO: [APUAPC] D0_APC_0: 0x400510
9916 00:45:58.350459 INFO: [APUAPC] D0_APC_1: 0x0
9917 00:45:58.353943 INFO: [APUAPC] D0_APC_2: 0x1540
9918 00:45:58.357035 INFO: [APUAPC] D0_APC_3: 0x0
9919 00:45:58.360365 INFO: [APUAPC] D1_APC_0: 0xffffffff
9920 00:45:58.364258 INFO: [APUAPC] D1_APC_1: 0xffffffff
9921 00:45:58.367372 INFO: [APUAPC] D1_APC_2: 0x3fffff
9922 00:45:58.370558 INFO: [APUAPC] D1_APC_3: 0x0
9923 00:45:58.373725 INFO: [APUAPC] D2_APC_0: 0xffffffff
9924 00:45:58.376965 INFO: [APUAPC] D2_APC_1: 0xffffffff
9925 00:45:58.380786 INFO: [APUAPC] D2_APC_2: 0x3fffff
9926 00:45:58.383916 INFO: [APUAPC] D2_APC_3: 0x0
9927 00:45:58.387340 INFO: [APUAPC] D3_APC_0: 0xffffffff
9928 00:45:58.390938 INFO: [APUAPC] D3_APC_1: 0xffffffff
9929 00:45:58.394747 INFO: [APUAPC] D3_APC_2: 0x3fffff
9930 00:45:58.397076 INFO: [APUAPC] D3_APC_3: 0x0
9931 00:45:58.400863 INFO: [APUAPC] D4_APC_0: 0xffffffff
9932 00:45:58.403713 INFO: [APUAPC] D4_APC_1: 0xffffffff
9933 00:45:58.407093 INFO: [APUAPC] D4_APC_2: 0x3fffff
9934 00:45:58.410291 INFO: [APUAPC] D4_APC_3: 0x0
9935 00:45:58.413920 INFO: [APUAPC] D5_APC_0: 0xffffffff
9936 00:45:58.416905 INFO: [APUAPC] D5_APC_1: 0xffffffff
9937 00:45:58.420380 INFO: [APUAPC] D5_APC_2: 0x3fffff
9938 00:45:58.424162 INFO: [APUAPC] D5_APC_3: 0x0
9939 00:45:58.427352 INFO: [APUAPC] D6_APC_0: 0xffffffff
9940 00:45:58.430504 INFO: [APUAPC] D6_APC_1: 0xffffffff
9941 00:45:58.433846 INFO: [APUAPC] D6_APC_2: 0x3fffff
9942 00:45:58.433921 INFO: [APUAPC] D6_APC_3: 0x0
9943 00:45:58.437476 INFO: [APUAPC] D7_APC_0: 0xffffffff
9944 00:45:58.443972 INFO: [APUAPC] D7_APC_1: 0xffffffff
9945 00:45:58.447299 INFO: [APUAPC] D7_APC_2: 0x3fffff
9946 00:45:58.447374 INFO: [APUAPC] D7_APC_3: 0x0
9947 00:45:58.450646 INFO: [APUAPC] D8_APC_0: 0xffffffff
9948 00:45:58.453878 INFO: [APUAPC] D8_APC_1: 0xffffffff
9949 00:45:58.457498 INFO: [APUAPC] D8_APC_2: 0x3fffff
9950 00:45:58.460447 INFO: [APUAPC] D8_APC_3: 0x0
9951 00:45:58.464007 INFO: [APUAPC] D9_APC_0: 0xffffffff
9952 00:45:58.467113 INFO: [APUAPC] D9_APC_1: 0xffffffff
9953 00:45:58.470367 INFO: [APUAPC] D9_APC_2: 0x3fffff
9954 00:45:58.474200 INFO: [APUAPC] D9_APC_3: 0x0
9955 00:45:58.477461 INFO: [APUAPC] D10_APC_0: 0xffffffff
9956 00:45:58.480744 INFO: [APUAPC] D10_APC_1: 0xffffffff
9957 00:45:58.483991 INFO: [APUAPC] D10_APC_2: 0x3fffff
9958 00:45:58.487245 INFO: [APUAPC] D10_APC_3: 0x0
9959 00:45:58.490367 INFO: [APUAPC] D11_APC_0: 0xffffffff
9960 00:45:58.493482 INFO: [APUAPC] D11_APC_1: 0xffffffff
9961 00:45:58.497381 INFO: [APUAPC] D11_APC_2: 0x3fffff
9962 00:45:58.500342 INFO: [APUAPC] D11_APC_3: 0x0
9963 00:45:58.503684 INFO: [APUAPC] D12_APC_0: 0xffffffff
9964 00:45:58.507613 INFO: [APUAPC] D12_APC_1: 0xffffffff
9965 00:45:58.510579 INFO: [APUAPC] D12_APC_2: 0x3fffff
9966 00:45:58.514074 INFO: [APUAPC] D12_APC_3: 0x0
9967 00:45:58.517169 INFO: [APUAPC] D13_APC_0: 0xffffffff
9968 00:45:58.520802 INFO: [APUAPC] D13_APC_1: 0xffffffff
9969 00:45:58.523770 INFO: [APUAPC] D13_APC_2: 0x3fffff
9970 00:45:58.527272 INFO: [APUAPC] D13_APC_3: 0x0
9971 00:45:58.530675 INFO: [APUAPC] D14_APC_0: 0xffffffff
9972 00:45:58.533754 INFO: [APUAPC] D14_APC_1: 0xffffffff
9973 00:45:58.537222 INFO: [APUAPC] D14_APC_2: 0x3fffff
9974 00:45:58.540217 INFO: [APUAPC] D14_APC_3: 0x0
9975 00:45:58.543909 INFO: [APUAPC] D15_APC_0: 0xffffffff
9976 00:45:58.546867 INFO: [APUAPC] D15_APC_1: 0xffffffff
9977 00:45:58.550170 INFO: [APUAPC] D15_APC_2: 0x3fffff
9978 00:45:58.553684 INFO: [APUAPC] D15_APC_3: 0x0
9979 00:45:58.557261 INFO: [APUAPC] APC_CON: 0x4
9980 00:45:58.560679 INFO: [NOCDAPC] D0_APC_0: 0x0
9981 00:45:58.564056 INFO: [NOCDAPC] D0_APC_1: 0x0
9982 00:45:58.567102 INFO: [NOCDAPC] D1_APC_0: 0x0
9983 00:45:58.570515 INFO: [NOCDAPC] D1_APC_1: 0xfff
9984 00:45:58.573879 INFO: [NOCDAPC] D2_APC_0: 0x0
9985 00:45:58.573954 INFO: [NOCDAPC] D2_APC_1: 0xfff
9986 00:45:58.577076 INFO: [NOCDAPC] D3_APC_0: 0x0
9987 00:45:58.580337 INFO: [NOCDAPC] D3_APC_1: 0xfff
9988 00:45:58.583593 INFO: [NOCDAPC] D4_APC_0: 0x0
9989 00:45:58.587009 INFO: [NOCDAPC] D4_APC_1: 0xfff
9990 00:45:58.590656 INFO: [NOCDAPC] D5_APC_0: 0x0
9991 00:45:58.593943 INFO: [NOCDAPC] D5_APC_1: 0xfff
9992 00:45:58.597057 INFO: [NOCDAPC] D6_APC_0: 0x0
9993 00:45:58.600821 INFO: [NOCDAPC] D6_APC_1: 0xfff
9994 00:45:58.603846 INFO: [NOCDAPC] D7_APC_0: 0x0
9995 00:45:58.607056 INFO: [NOCDAPC] D7_APC_1: 0xfff
9996 00:45:58.607130 INFO: [NOCDAPC] D8_APC_0: 0x0
9997 00:45:58.610331 INFO: [NOCDAPC] D8_APC_1: 0xfff
9998 00:45:58.613556 INFO: [NOCDAPC] D9_APC_0: 0x0
9999 00:45:58.616827 INFO: [NOCDAPC] D9_APC_1: 0xfff
10000 00:45:58.620415 INFO: [NOCDAPC] D10_APC_0: 0x0
10001 00:45:58.624068 INFO: [NOCDAPC] D10_APC_1: 0xfff
10002 00:45:58.627199 INFO: [NOCDAPC] D11_APC_0: 0x0
10003 00:45:58.630440 INFO: [NOCDAPC] D11_APC_1: 0xfff
10004 00:45:58.633602 INFO: [NOCDAPC] D12_APC_0: 0x0
10005 00:45:58.637227 INFO: [NOCDAPC] D12_APC_1: 0xfff
10006 00:45:58.640472 INFO: [NOCDAPC] D13_APC_0: 0x0
10007 00:45:58.644019 INFO: [NOCDAPC] D13_APC_1: 0xfff
10008 00:45:58.644094 INFO: [NOCDAPC] D14_APC_0: 0x0
10009 00:45:58.646916 INFO: [NOCDAPC] D14_APC_1: 0xfff
10010 00:45:58.650308 INFO: [NOCDAPC] D15_APC_0: 0x0
10011 00:45:58.653429 INFO: [NOCDAPC] D15_APC_1: 0xfff
10012 00:45:58.657019 INFO: [NOCDAPC] APC_CON: 0x4
10013 00:45:58.660661 INFO: [APUAPC] set_apusys_apc done
10014 00:45:58.663753 INFO: [DEVAPC] devapc_init done
10015 00:45:58.667498 INFO: GICv3 without legacy support detected.
10016 00:45:58.673680 INFO: ARM GICv3 driver initialized in EL3
10017 00:45:58.677596 INFO: Maximum SPI INTID supported: 639
10018 00:45:58.680780 INFO: BL31: Initializing runtime services
10019 00:45:58.687256 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10020 00:45:58.687331 INFO: SPM: enable CPC mode
10021 00:45:58.693849 INFO: mcdi ready for mcusys-off-idle and system suspend
10022 00:45:58.696931 INFO: BL31: Preparing for EL3 exit to normal world
10023 00:45:58.700642 INFO: Entry point address = 0x80000000
10024 00:45:58.703862 INFO: SPSR = 0x8
10025 00:45:58.709690
10026 00:45:58.709764
10027 00:45:58.709822
10028 00:45:58.712897 Starting depthcharge on Spherion...
10029 00:45:58.712971
10030 00:45:58.713028 Wipe memory regions:
10031 00:45:58.713081
10032 00:45:58.713760 end: 2.2.3 depthcharge-start (duration 00:00:31) [common]
10033 00:45:58.713873 start: 2.2.4 bootloader-commands (timeout 00:04:20) [common]
10034 00:45:58.713962 Setting prompt string to ['asurada:']
10035 00:45:58.714034 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:20)
10036 00:45:58.716089 [0x00000040000000, 0x00000054600000)
10037 00:45:58.838710
10038 00:45:58.838810 [0x00000054660000, 0x00000080000000)
10039 00:45:59.099154
10040 00:45:59.099278 [0x000000821a7280, 0x000000ffe64000)
10041 00:45:59.842733
10042 00:45:59.842846 [0x00000100000000, 0x00000240000000)
10043 00:46:01.729098
10044 00:46:01.732253 Initializing XHCI USB controller at 0x11200000.
10045 00:46:02.770258
10046 00:46:02.774102 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10047 00:46:02.774173
10048 00:46:02.774231
10049 00:46:02.774494 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10051 00:46:02.874772 asurada: tftpboot 192.168.201.1 14368423/tftp-deploy-t4bmfn5s/kernel/image.itb 14368423/tftp-deploy-t4bmfn5s/kernel/cmdline
10052 00:46:02.874967 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10053 00:46:02.875051 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:16)
10054 00:46:02.879185 tftpboot 192.168.201.1 14368423/tftp-deploy-t4bmfn5s/kernel/image.ittp-deploy-t4bmfn5s/kernel/cmdline
10055 00:46:02.879280
10056 00:46:02.879365 Waiting for link
10057 00:46:03.037305
10058 00:46:03.037478 R8152: Initializing
10059 00:46:03.037590
10060 00:46:03.040246 Version 9 (ocp_data = 6010)
10061 00:46:03.040368
10062 00:46:03.043603 R8152: Done initializing
10063 00:46:03.043774
10064 00:46:03.043859 Adding net device
10065 00:46:04.992014
10066 00:46:04.992140 done.
10067 00:46:04.992200
10068 00:46:04.992254 MAC: 00:e0:4c:78:7a:aa
10069 00:46:04.992306
10070 00:46:04.995178 Sending DHCP discover... done.
10071 00:46:04.995254
10072 00:46:04.998378 Waiting for reply... done.
10073 00:46:04.998453
10074 00:46:05.002052 Sending DHCP request... done.
10075 00:46:05.002128
10076 00:46:05.002185 Waiting for reply... done.
10077 00:46:05.002240
10078 00:46:05.005373 My ip is 192.168.201.12
10079 00:46:05.005447
10080 00:46:05.008679 The DHCP server ip is 192.168.201.1
10081 00:46:05.008755
10082 00:46:05.012019 TFTP server IP predefined by user: 192.168.201.1
10083 00:46:05.012095
10084 00:46:05.018860 Bootfile predefined by user: 14368423/tftp-deploy-t4bmfn5s/kernel/image.itb
10085 00:46:05.018936
10086 00:46:05.021723 Sending tftp read request... done.
10087 00:46:05.021798
10088 00:46:05.025519 Waiting for the transfer...
10089 00:46:05.025638
10090 00:46:05.283328 00000000 ################################################################
10091 00:46:05.283438
10092 00:46:05.541309 00080000 ################################################################
10093 00:46:05.541416
10094 00:46:05.792471 00100000 ################################################################
10095 00:46:05.792604
10096 00:46:06.047135 00180000 ################################################################
10097 00:46:06.047276
10098 00:46:06.311929 00200000 ################################################################
10099 00:46:06.312065
10100 00:46:06.577534 00280000 ################################################################
10101 00:46:06.577738
10102 00:46:06.840973 00300000 ################################################################
10103 00:46:06.841102
10104 00:46:07.093717 00380000 ################################################################
10105 00:46:07.093860
10106 00:46:07.356243 00400000 ################################################################
10107 00:46:07.356382
10108 00:46:07.605786 00480000 ################################################################
10109 00:46:07.605921
10110 00:46:07.883964 00500000 ################################################################
10111 00:46:07.884101
10112 00:46:08.140348 00580000 ################################################################
10113 00:46:08.140458
10114 00:46:08.391958 00600000 ################################################################
10115 00:46:08.392092
10116 00:46:08.653513 00680000 ################################################################
10117 00:46:08.653643
10118 00:46:08.902498 00700000 ################################################################
10119 00:46:08.902639
10120 00:46:09.161052 00780000 ################################################################
10121 00:46:09.161176
10122 00:46:09.412381 00800000 ################################################################
10123 00:46:09.412507
10124 00:46:09.684257 00880000 ################################################################
10125 00:46:09.684401
10126 00:46:09.973125 00900000 ################################################################
10127 00:46:09.973246
10128 00:46:10.241640 00980000 ################################################################
10129 00:46:10.241764
10130 00:46:10.504079 00a00000 ################################################################
10131 00:46:10.504205
10132 00:46:10.763743 00a80000 ################################################################
10133 00:46:10.763894
10134 00:46:11.012031 00b00000 ################################################################
10135 00:46:11.012154
10136 00:46:11.264172 00b80000 ################################################################
10137 00:46:11.264296
10138 00:46:11.517863 00c00000 ################################################################
10139 00:46:11.517987
10140 00:46:11.776921 00c80000 ################################################################
10141 00:46:11.777045
10142 00:46:12.040116 00d00000 ################################################################
10143 00:46:12.040241
10144 00:46:12.296468 00d80000 ################################################################
10145 00:46:12.296605
10146 00:46:12.553940 00e00000 ################################################################
10147 00:46:12.554055
10148 00:46:12.806896 00e80000 ################################################################
10149 00:46:12.807047
10150 00:46:13.055620 00f00000 ################################################################
10151 00:46:13.055744
10152 00:46:13.318011 00f80000 ################################################################
10153 00:46:13.318166
10154 00:46:13.580075 01000000 ################################################################
10155 00:46:13.580205
10156 00:46:13.841199 01080000 ################################################################
10157 00:46:13.841323
10158 00:46:14.094108 01100000 ################################################################
10159 00:46:14.094229
10160 00:46:14.357486 01180000 ################################################################
10161 00:46:14.357628
10162 00:46:14.623559 01200000 ################################################################
10163 00:46:14.623674
10164 00:46:14.888313 01280000 ################################################################
10165 00:46:14.888455
10166 00:46:15.157104 01300000 ################################################################
10167 00:46:15.157236
10168 00:46:15.405597 01380000 ################################################################
10169 00:46:15.405774
10170 00:46:15.658750 01400000 ################################################################
10171 00:46:15.658873
10172 00:46:15.937700 01480000 ################################################################
10173 00:46:15.937818
10174 00:46:16.199003 01500000 ################################################################
10175 00:46:16.199140
10176 00:46:16.460939 01580000 ################################################################
10177 00:46:16.461054
10178 00:46:16.713482 01600000 ################################################################
10179 00:46:16.713628
10180 00:46:16.975215 01680000 ################################################################
10181 00:46:16.975329
10182 00:46:17.227808 01700000 ################################################################
10183 00:46:17.227994
10184 00:46:17.479502 01780000 ################################################################
10185 00:46:17.479620
10186 00:46:17.757658 01800000 ################################################################
10187 00:46:17.757792
10188 00:46:18.028813 01880000 ################################################################
10189 00:46:18.028955
10190 00:46:18.287071 01900000 ################################################################
10191 00:46:18.287205
10192 00:46:18.561497 01980000 ################################################################
10193 00:46:18.561625
10194 00:46:18.823938 01a00000 ################################################################
10195 00:46:18.824049
10196 00:46:19.076251 01a80000 ################################################################
10197 00:46:19.076399
10198 00:46:19.330364 01b00000 ################################################################
10199 00:46:19.330500
10200 00:46:19.581823 01b80000 ################################################################
10201 00:46:19.581944
10202 00:46:19.837049 01c00000 ################################################################
10203 00:46:19.837166
10204 00:46:20.086926 01c80000 ################################################################
10205 00:46:20.087040
10206 00:46:20.340322 01d00000 ################################################################
10207 00:46:20.340435
10208 00:46:20.606011 01d80000 ################################################################
10209 00:46:20.606139
10210 00:46:20.866521 01e00000 ################################################################
10211 00:46:20.866697
10212 00:46:21.129832 01e80000 ################################################################
10213 00:46:21.129944
10214 00:46:21.379633 01f00000 ################################################################
10215 00:46:21.379761
10216 00:46:21.632141 01f80000 ################################################################
10217 00:46:21.632253
10218 00:46:21.894927 02000000 ################################################################
10219 00:46:21.895069
10220 00:46:22.150888 02080000 ################################################################
10221 00:46:22.151000
10222 00:46:22.408921 02100000 ################################################################
10223 00:46:22.409032
10224 00:46:22.675861 02180000 ################################################################
10225 00:46:22.676002
10226 00:46:22.932267 02200000 ################################################################
10227 00:46:22.932400
10228 00:46:23.185982 02280000 ################################################################
10229 00:46:23.186096
10230 00:46:23.432544 02300000 ################################################################
10231 00:46:23.432659
10232 00:46:23.679600 02380000 ################################################################
10233 00:46:23.679742
10234 00:46:23.926776 02400000 ################################################################
10235 00:46:23.926900
10236 00:46:24.203791 02480000 ################################################################
10237 00:46:24.203926
10238 00:46:24.460572 02500000 ################################################################
10239 00:46:24.460684
10240 00:46:24.728197 02580000 ################################################################
10241 00:46:24.728327
10242 00:46:25.001450 02600000 ################################################################
10243 00:46:25.001623
10244 00:46:25.259906 02680000 ################################################################
10245 00:46:25.260041
10246 00:46:25.523034 02700000 ################################################################
10247 00:46:25.523146
10248 00:46:25.792022 02780000 ################################################################
10249 00:46:25.792135
10250 00:46:26.043241 02800000 ################################################################
10251 00:46:26.043369
10252 00:46:26.300527 02880000 ################################################################
10253 00:46:26.300640
10254 00:46:26.556615 02900000 ################################################################
10255 00:46:26.556729
10256 00:46:26.811871 02980000 ################################################################
10257 00:46:26.812006
10258 00:46:27.065198 02a00000 ################################################################
10259 00:46:27.065321
10260 00:46:27.327673 02a80000 ################################################################
10261 00:46:27.327812
10262 00:46:27.576275 02b00000 ################################################################
10263 00:46:27.576413
10264 00:46:27.837724 02b80000 ################################################################
10265 00:46:27.837869
10266 00:46:28.097538 02c00000 ################################################################
10267 00:46:28.097693
10268 00:46:28.358034 02c80000 ################################################################
10269 00:46:28.358183
10270 00:46:28.612024 02d00000 ################################################################
10271 00:46:28.612165
10272 00:46:28.861563 02d80000 ################################################################
10273 00:46:28.861703
10274 00:46:29.131790 02e00000 ################################################################
10275 00:46:29.131919
10276 00:46:29.391687 02e80000 ################################################################
10277 00:46:29.391810
10278 00:46:29.642943 02f00000 ################################################################
10279 00:46:29.643059
10280 00:46:29.894599 02f80000 ################################################################
10281 00:46:29.894738
10282 00:46:30.150532 03000000 ################################################################
10283 00:46:30.150653
10284 00:46:30.404161 03080000 ################################################################
10285 00:46:30.404284
10286 00:46:30.657030 03100000 ################################################################
10287 00:46:30.657146
10288 00:46:30.929441 03180000 ################################################################
10289 00:46:30.929615
10290 00:46:31.199461 03200000 ################################################################
10291 00:46:31.199585
10292 00:46:31.459464 03280000 ################################################################
10293 00:46:31.459585
10294 00:46:31.730689 03300000 ################################################################
10295 00:46:31.730812
10296 00:46:31.989433 03380000 ################################################################
10297 00:46:31.989621
10298 00:46:32.249177 03400000 ################################################################
10299 00:46:32.249298
10300 00:46:32.522583 03480000 ################################################################
10301 00:46:32.522706
10302 00:46:32.781708 03500000 ################################################################
10303 00:46:32.781830
10304 00:46:33.037913 03580000 ################################################################
10305 00:46:33.038036
10306 00:46:33.301530 03600000 ################################################################
10307 00:46:33.301685
10308 00:46:33.566699 03680000 ################################################################
10309 00:46:33.566819
10310 00:46:33.825389 03700000 ################################################################
10311 00:46:33.825554
10312 00:46:34.078322 03780000 ################################################################
10313 00:46:34.078457
10314 00:46:34.354694 03800000 ################################################################
10315 00:46:34.354815
10316 00:46:34.599469 03880000 ################################################################
10317 00:46:34.599591
10318 00:46:34.867521 03900000 ################################################################
10319 00:46:34.867639
10320 00:46:35.161010 03980000 ################################################################
10321 00:46:35.161128
10322 00:46:35.426799 03a00000 ################################################################
10323 00:46:35.426941
10324 00:46:35.704526 03a80000 ################################################################
10325 00:46:35.704649
10326 00:46:35.990949 03b00000 ################################################################
10327 00:46:35.991068
10328 00:46:36.291666 03b80000 ################################################################
10329 00:46:36.291783
10330 00:46:36.581869 03c00000 ################################################################
10331 00:46:36.581989
10332 00:46:36.867923 03c80000 ################################################################
10333 00:46:36.868069
10334 00:46:37.149471 03d00000 ################################################################
10335 00:46:37.149597
10336 00:46:37.446983 03d80000 ################################################################
10337 00:46:37.447106
10338 00:46:37.731514 03e00000 ################################################################
10339 00:46:37.731638
10340 00:46:37.997479 03e80000 ################################################################
10341 00:46:37.997617
10342 00:46:38.249583 03f00000 ################################################################
10343 00:46:38.249691
10344 00:46:38.511983 03f80000 ################################################################
10345 00:46:38.512098
10346 00:46:38.766798 04000000 ################################################################
10347 00:46:38.766914
10348 00:46:39.021445 04080000 ################################################################
10349 00:46:39.021615
10350 00:46:39.271633 04100000 ################################################################
10351 00:46:39.271742
10352 00:46:39.547119 04180000 ################################################################
10353 00:46:39.547235
10354 00:46:39.839546 04200000 ################################################################
10355 00:46:39.839672
10356 00:46:40.134099 04280000 ################################################################
10357 00:46:40.134223
10358 00:46:40.429751 04300000 ################################################################
10359 00:46:40.429880
10360 00:46:40.726320 04380000 ################################################################
10361 00:46:40.726454
10362 00:46:41.019424 04400000 ################################################################
10363 00:46:41.019550
10364 00:46:41.316898 04480000 ################################################################
10365 00:46:41.317019
10366 00:46:41.691899 04500000 ################################################################
10367 00:46:41.692356
10368 00:46:42.020816 04580000 ################################################################
10369 00:46:42.020937
10370 00:46:42.321353 04600000 ################################################################
10371 00:46:42.321474
10372 00:46:42.462076 04680000 ################################ done.
10373 00:46:42.462182
10374 00:46:42.465458 The bootfile was 74181762 bytes long.
10375 00:46:42.465571
10376 00:46:42.468929 Sending tftp read request... done.
10377 00:46:42.469013
10378 00:46:42.472076 Waiting for the transfer...
10379 00:46:42.472164
10380 00:46:42.472231 00000000 # done.
10381 00:46:42.472294
10382 00:46:42.482209 Command line loaded dynamically from TFTP file: 14368423/tftp-deploy-t4bmfn5s/kernel/cmdline
10383 00:46:42.482344
10384 00:46:42.495671 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10385 00:46:42.495863
10386 00:46:42.495997 Loading FIT.
10387 00:46:42.496105
10388 00:46:42.498693 Image ramdisk-1 has 61006101 bytes.
10389 00:46:42.498841
10390 00:46:42.501876 Image fdt-1 has 47258 bytes.
10391 00:46:42.502090
10392 00:46:42.505124 Image kernel-1 has 13126376 bytes.
10393 00:46:42.505387
10394 00:46:42.514945 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10395 00:46:42.515166
10396 00:46:42.532043 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10397 00:46:42.532279
10398 00:46:42.538548 Choosing best match conf-1 for compat google,spherion-rev2.
10399 00:46:42.538623
10400 00:46:42.542427 Connected to device vid:did:rid of 1ae0:0028:00
10401 00:46:42.552522
10402 00:46:42.556244 tpm_get_response: command 0x17b, return code 0x0
10403 00:46:42.556319
10404 00:46:42.559323 ec_init: CrosEC protocol v3 supported (256, 248)
10405 00:46:42.562400
10406 00:46:42.566214 tpm_cleanup: add release locality here.
10407 00:46:42.566289
10408 00:46:42.569161 Shutting down all USB controllers.
10409 00:46:42.569235
10410 00:46:42.572486 Removing current net device
10411 00:46:42.572560
10412 00:46:42.575888 Exiting depthcharge with code 4 at timestamp: 73166063
10413 00:46:42.575964
10414 00:46:42.579203 LZMA decompressing kernel-1 to 0x821a6718
10415 00:46:42.579277
10416 00:46:42.585678 LZMA decompressing kernel-1 to 0x40000000
10417 00:46:44.202172
10418 00:46:44.202716 jumping to kernel
10419 00:46:44.204867 end: 2.2.4 bootloader-commands (duration 00:00:45) [common]
10420 00:46:44.205376 start: 2.2.5 auto-login-action (timeout 00:03:34) [common]
10421 00:46:44.205822 Setting prompt string to ['Linux version [0-9]']
10422 00:46:44.206173 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10423 00:46:44.206542 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10424 00:46:44.284363
10425 00:46:44.288125 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10426 00:46:44.291833 start: 2.2.5.1 login-action (timeout 00:03:34) [common]
10427 00:46:44.292403 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10428 00:46:44.292778 Setting prompt string to []
10429 00:46:44.293185 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10430 00:46:44.293582 Using line separator: #'\n'#
10431 00:46:44.294081 No login prompt set.
10432 00:46:44.294431 Parsing kernel messages
10433 00:46:44.294722 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10434 00:46:44.295253 [login-action] Waiting for messages, (timeout 00:03:34)
10435 00:46:44.295598 Waiting using forced prompt support (timeout 00:01:47)
10436 00:46:44.311239 [ 0.000000] Linux version 6.1.92-cip22 (KernelCI@build-j232175-arm64-gcc-10-defconfig-arm64-chromebook-7lg8d) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sun Jun 16 00:28:47 UTC 2024
10437 00:46:44.314249 [ 0.000000] random: crng init done
10438 00:46:44.321270 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10439 00:46:44.324197 [ 0.000000] efi: UEFI not found.
10440 00:46:44.330842 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10441 00:46:44.337479 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10442 00:46:44.347406 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10443 00:46:44.357519 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10444 00:46:44.363979 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10445 00:46:44.367277 [ 0.000000] printk: bootconsole [mtk8250] enabled
10446 00:46:44.376040 [ 0.000000] NUMA: No NUMA configuration found
10447 00:46:44.382834 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10448 00:46:44.389725 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10449 00:46:44.390200 [ 0.000000] Zone ranges:
10450 00:46:44.396719 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10451 00:46:44.399993 [ 0.000000] DMA32 empty
10452 00:46:44.406308 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10453 00:46:44.409292 [ 0.000000] Movable zone start for each node
10454 00:46:44.412549 [ 0.000000] Early memory node ranges
10455 00:46:44.419422 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10456 00:46:44.426176 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10457 00:46:44.432778 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10458 00:46:44.439069 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10459 00:46:44.445951 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10460 00:46:44.452746 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10461 00:46:44.508770 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10462 00:46:44.515225 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10463 00:46:44.522285 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10464 00:46:44.525476 [ 0.000000] psci: probing for conduit method from DT.
10465 00:46:44.532167 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10466 00:46:44.535232 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10467 00:46:44.542513 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10468 00:46:44.545768 [ 0.000000] psci: SMC Calling Convention v1.2
10469 00:46:44.552415 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10470 00:46:44.555096 [ 0.000000] Detected VIPT I-cache on CPU0
10471 00:46:44.561823 [ 0.000000] CPU features: detected: GIC system register CPU interface
10472 00:46:44.568572 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10473 00:46:44.575401 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10474 00:46:44.581930 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10475 00:46:44.588414 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10476 00:46:44.598499 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10477 00:46:44.601601 [ 0.000000] alternatives: applying boot alternatives
10478 00:46:44.608190 [ 0.000000] Fallback order for Node 0: 0
10479 00:46:44.614501 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10480 00:46:44.618095 [ 0.000000] Policy zone: Normal
10481 00:46:44.631154 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10482 00:46:44.641401 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10483 00:46:44.653309 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10484 00:46:44.663632 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10485 00:46:44.669995 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10486 00:46:44.673470 <6>[ 0.000000] software IO TLB: area num 8.
10487 00:46:44.729684 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10488 00:46:44.879471 <6>[ 0.000000] Memory: 7904484K/8385536K available (18112K kernel code, 4120K rwdata, 22644K rodata, 8512K init, 616K bss, 448284K reserved, 32768K cma-reserved)
10489 00:46:44.885683 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10490 00:46:44.892867 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10491 00:46:44.895961 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10492 00:46:44.902708 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10493 00:46:44.909207 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10494 00:46:44.912315 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10495 00:46:44.922277 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10496 00:46:44.929126 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10497 00:46:44.935253 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10498 00:46:44.942144 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10499 00:46:44.945578 <6>[ 0.000000] GICv3: 608 SPIs implemented
10500 00:46:44.948809 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10501 00:46:44.955564 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10502 00:46:44.958421 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10503 00:46:44.965239 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10504 00:46:44.978464 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10505 00:46:44.991811 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10506 00:46:44.998227 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10507 00:46:45.005917 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10508 00:46:45.018625 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10509 00:46:45.025350 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10510 00:46:45.032325 <6>[ 0.009183] Console: colour dummy device 80x25
10511 00:46:45.042021 <6>[ 0.013913] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10512 00:46:45.048872 <6>[ 0.024354] pid_max: default: 32768 minimum: 301
10513 00:46:45.051746 <6>[ 0.029256] LSM: Security Framework initializing
10514 00:46:45.058480 <6>[ 0.034224] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10515 00:46:45.069283 <6>[ 0.042037] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10516 00:46:45.075916 <6>[ 0.051456] cblist_init_generic: Setting adjustable number of callback queues.
10517 00:46:45.082251 <6>[ 0.058899] cblist_init_generic: Setting shift to 3 and lim to 1.
10518 00:46:45.092181 <6>[ 0.065278] cblist_init_generic: Setting adjustable number of callback queues.
10519 00:46:45.095321 <6>[ 0.072751] cblist_init_generic: Setting shift to 3 and lim to 1.
10520 00:46:45.101951 <6>[ 0.079151] rcu: Hierarchical SRCU implementation.
10521 00:46:45.108577 <6>[ 0.084166] rcu: Max phase no-delay instances is 1000.
10522 00:46:45.115421 <6>[ 0.091194] EFI services will not be available.
10523 00:46:45.118441 <6>[ 0.096149] smp: Bringing up secondary CPUs ...
10524 00:46:45.126754 <6>[ 0.101198] Detected VIPT I-cache on CPU1
10525 00:46:45.132892 <6>[ 0.101269] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10526 00:46:45.140194 <6>[ 0.101299] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10527 00:46:45.142841 <6>[ 0.101637] Detected VIPT I-cache on CPU2
10528 00:46:45.149739 <6>[ 0.101690] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10529 00:46:45.159682 <6>[ 0.101708] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10530 00:46:45.163041 <6>[ 0.101969] Detected VIPT I-cache on CPU3
10531 00:46:45.169305 <6>[ 0.102016] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10532 00:46:45.176213 <6>[ 0.102029] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10533 00:46:45.179446 <6>[ 0.102335] CPU features: detected: Spectre-v4
10534 00:46:45.186360 <6>[ 0.102341] CPU features: detected: Spectre-BHB
10535 00:46:45.189454 <6>[ 0.102347] Detected PIPT I-cache on CPU4
10536 00:46:45.196650 <6>[ 0.102407] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10537 00:46:45.202768 <6>[ 0.102424] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10538 00:46:45.209687 <6>[ 0.102717] Detected PIPT I-cache on CPU5
10539 00:46:45.216323 <6>[ 0.102782] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10540 00:46:45.223049 <6>[ 0.102798] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10541 00:46:45.226142 <6>[ 0.103080] Detected PIPT I-cache on CPU6
10542 00:46:45.232682 <6>[ 0.103148] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10543 00:46:45.239397 <6>[ 0.103164] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10544 00:46:45.246081 <6>[ 0.103463] Detected PIPT I-cache on CPU7
10545 00:46:45.252321 <6>[ 0.103530] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10546 00:46:45.258965 <6>[ 0.103546] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10547 00:46:45.262102 <6>[ 0.103593] smp: Brought up 1 node, 8 CPUs
10548 00:46:45.269024 <6>[ 0.245077] SMP: Total of 8 processors activated.
10549 00:46:45.272137 <6>[ 0.249998] CPU features: detected: 32-bit EL0 Support
10550 00:46:45.282148 <6>[ 0.255362] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10551 00:46:45.289067 <6>[ 0.264163] CPU features: detected: Common not Private translations
10552 00:46:45.292328 <6>[ 0.270679] CPU features: detected: CRC32 instructions
10553 00:46:45.298969 <6>[ 0.276030] CPU features: detected: RCpc load-acquire (LDAPR)
10554 00:46:45.305976 <6>[ 0.281990] CPU features: detected: LSE atomic instructions
10555 00:46:45.312043 <6>[ 0.287772] CPU features: detected: Privileged Access Never
10556 00:46:45.315763 <6>[ 0.293551] CPU features: detected: RAS Extension Support
10557 00:46:45.325735 <6>[ 0.299160] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10558 00:46:45.328909 <6>[ 0.306378] CPU: All CPU(s) started at EL2
10559 00:46:45.335623 <6>[ 0.310695] alternatives: applying system-wide alternatives
10560 00:46:45.344573 <6>[ 0.321509] devtmpfs: initialized
10561 00:46:45.357298 <6>[ 0.330453] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10562 00:46:45.366334 <6>[ 0.340416] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10563 00:46:45.373505 <6>[ 0.348439] pinctrl core: initialized pinctrl subsystem
10564 00:46:45.376553 <6>[ 0.355205] DMI not present or invalid.
10565 00:46:45.383397 <6>[ 0.359622] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10566 00:46:45.393129 <6>[ 0.366486] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10567 00:46:45.399986 <6>[ 0.374076] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10568 00:46:45.409419 <6>[ 0.382301] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10569 00:46:45.412735 <6>[ 0.390546] audit: initializing netlink subsys (disabled)
10570 00:46:45.422932 <5>[ 0.396240] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10571 00:46:45.429303 <6>[ 0.396997] thermal_sys: Registered thermal governor 'step_wise'
10572 00:46:45.436402 <6>[ 0.404206] thermal_sys: Registered thermal governor 'power_allocator'
10573 00:46:45.439605 <6>[ 0.410462] cpuidle: using governor menu
10574 00:46:45.445870 <6>[ 0.421423] NET: Registered PF_QIPCRTR protocol family
10575 00:46:45.452886 <6>[ 0.426904] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10576 00:46:45.455725 <6>[ 0.434007] ASID allocator initialised with 32768 entries
10577 00:46:45.463531 <6>[ 0.440634] Serial: AMBA PL011 UART driver
10578 00:46:45.472696 <4>[ 0.449842] Trying to register duplicate clock ID: 134
10579 00:46:45.533135 <6>[ 0.513588] KASLR enabled
10580 00:46:45.547898 <6>[ 0.521291] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10581 00:46:45.554050 <6>[ 0.528303] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10582 00:46:45.560813 <6>[ 0.534793] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10583 00:46:45.567363 <6>[ 0.541799] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10584 00:46:45.574099 <6>[ 0.548285] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10585 00:46:45.580621 <6>[ 0.555288] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10586 00:46:45.586837 <6>[ 0.561775] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10587 00:46:45.594002 <6>[ 0.568779] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10588 00:46:45.597160 <6>[ 0.576250] ACPI: Interpreter disabled.
10589 00:46:45.606164 <6>[ 0.582750] iommu: Default domain type: Translated
10590 00:46:45.612250 <6>[ 0.587899] iommu: DMA domain TLB invalidation policy: strict mode
10591 00:46:45.615256 <5>[ 0.594557] SCSI subsystem initialized
10592 00:46:45.622337 <6>[ 0.598800] usbcore: registered new interface driver usbfs
10593 00:46:45.628859 <6>[ 0.604534] usbcore: registered new interface driver hub
10594 00:46:45.631989 <6>[ 0.610087] usbcore: registered new device driver usb
10595 00:46:45.639236 <6>[ 0.616250] pps_core: LinuxPPS API ver. 1 registered
10596 00:46:45.649118 <6>[ 0.621446] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10597 00:46:45.652644 <6>[ 0.630792] PTP clock support registered
10598 00:46:45.656211 <6>[ 0.635035] EDAC MC: Ver: 3.0.0
10599 00:46:45.663470 <6>[ 0.640246] FPGA manager framework
10600 00:46:45.669640 <6>[ 0.643921] Advanced Linux Sound Architecture Driver Initialized.
10601 00:46:45.672763 <6>[ 0.650693] vgaarb: loaded
10602 00:46:45.679555 <6>[ 0.653838] clocksource: Switched to clocksource arch_sys_counter
10603 00:46:45.682489 <5>[ 0.660283] VFS: Disk quotas dquot_6.6.0
10604 00:46:45.689659 <6>[ 0.664471] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10605 00:46:45.692399 <6>[ 0.671665] pnp: PnP ACPI: disabled
10606 00:46:45.701309 <6>[ 0.678404] NET: Registered PF_INET protocol family
10607 00:46:45.711474 <6>[ 0.683995] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10608 00:46:45.722603 <6>[ 0.696344] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10609 00:46:45.732113 <6>[ 0.705158] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10610 00:46:45.739047 <6>[ 0.713126] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10611 00:46:45.749369 <6>[ 0.721830] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10612 00:46:45.755367 <6>[ 0.731578] TCP: Hash tables configured (established 65536 bind 65536)
10613 00:46:45.762410 <6>[ 0.738442] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10614 00:46:45.771982 <6>[ 0.745643] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10615 00:46:45.778715 <6>[ 0.753346] NET: Registered PF_UNIX/PF_LOCAL protocol family
10616 00:46:45.781989 <6>[ 0.759494] RPC: Registered named UNIX socket transport module.
10617 00:46:45.788399 <6>[ 0.765649] RPC: Registered udp transport module.
10618 00:46:45.791695 <6>[ 0.770580] RPC: Registered tcp transport module.
10619 00:46:45.798935 <6>[ 0.775513] RPC: Registered tcp NFSv4.1 backchannel transport module.
10620 00:46:45.805428 <6>[ 0.782179] PCI: CLS 0 bytes, default 64
10621 00:46:45.808444 <6>[ 0.786549] Unpacking initramfs...
10622 00:46:45.815380 <6>[ 0.790290] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10623 00:46:45.824964 <6>[ 0.798922] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10624 00:46:45.828808 <6>[ 0.807685] kvm [1]: IPA Size Limit: 40 bits
10625 00:46:45.835391 <6>[ 0.812213] kvm [1]: GICv3: no GICV resource entry
10626 00:46:45.838599 <6>[ 0.817235] kvm [1]: disabling GICv2 emulation
10627 00:46:45.845161 <6>[ 0.821920] kvm [1]: GIC system register CPU interface enabled
10628 00:46:45.852293 <6>[ 0.828086] kvm [1]: vgic interrupt IRQ18
10629 00:46:45.858085 <6>[ 0.833921] kvm [1]: VHE mode initialized successfully
10630 00:46:45.861613 <5>[ 0.840293] Initialise system trusted keyrings
10631 00:46:45.868197 <6>[ 0.845115] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10632 00:46:45.877898 <6>[ 0.855121] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10633 00:46:45.884654 <5>[ 0.861477] NFS: Registering the id_resolver key type
10634 00:46:45.888073 <5>[ 0.866774] Key type id_resolver registered
10635 00:46:45.894839 <5>[ 0.871190] Key type id_legacy registered
10636 00:46:45.901532 <6>[ 0.875471] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10637 00:46:45.908715 <6>[ 0.882394] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10638 00:46:45.914496 <6>[ 0.890105] 9p: Installing v9fs 9p2000 file system support
10639 00:46:45.951271 <5>[ 0.928323] Key type asymmetric registered
10640 00:46:45.954394 <5>[ 0.932653] Asymmetric key parser 'x509' registered
10641 00:46:45.964474 <6>[ 0.937787] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10642 00:46:45.967958 <6>[ 0.945403] io scheduler mq-deadline registered
10643 00:46:45.970992 <6>[ 0.950167] io scheduler kyber registered
10644 00:46:45.990483 <6>[ 0.967571] EINJ: ACPI disabled.
10645 00:46:46.023869 <4>[ 0.994351] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10646 00:46:46.033703 <4>[ 1.004982] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10647 00:46:46.048884 <6>[ 1.026234] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10648 00:46:46.056584 <6>[ 1.034168] printk: console [ttyS0] disabled
10649 00:46:46.085136 <6>[ 1.058793] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10650 00:46:46.091470 <6>[ 1.068264] printk: console [ttyS0] enabled
10651 00:46:46.095164 <6>[ 1.068264] printk: console [ttyS0] enabled
10652 00:46:46.101692 <6>[ 1.077158] printk: bootconsole [mtk8250] disabled
10653 00:46:46.104564 <6>[ 1.077158] printk: bootconsole [mtk8250] disabled
10654 00:46:46.111457 <6>[ 1.088200] SuperH (H)SCI(F) driver initialized
10655 00:46:46.114673 <6>[ 1.093486] msm_serial: driver initialized
10656 00:46:46.128974 <6>[ 1.102493] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10657 00:46:46.138462 <6>[ 1.111035] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10658 00:46:46.145769 <6>[ 1.119578] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10659 00:46:46.155081 <6>[ 1.128208] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10660 00:46:46.165432 <6>[ 1.136914] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10661 00:46:46.171708 <6>[ 1.145634] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10662 00:46:46.181610 <6>[ 1.154174] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10663 00:46:46.188615 <6>[ 1.162974] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10664 00:46:46.198160 <6>[ 1.171517] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10665 00:46:46.210275 <6>[ 1.187256] loop: module loaded
10666 00:46:46.216324 <6>[ 1.193194] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10667 00:46:46.239560 <4>[ 1.216500] mtk-pmic-keys: Failed to locate of_node [id: -1]
10668 00:46:46.246505 <6>[ 1.223239] megasas: 07.719.03.00-rc1
10669 00:46:46.255906 <6>[ 1.233099] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10670 00:46:46.268392 <6>[ 1.245228] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10671 00:46:46.317143 <6>[ 1.294331] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10672 00:46:46.372463 <6>[ 1.342858] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10673 00:46:48.503517 <6>[ 3.481056] Freeing initrd memory: 59572K
10674 00:46:48.515225 <6>[ 3.492673] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10675 00:46:48.526684 <6>[ 3.503896] tun: Universal TUN/TAP device driver, 1.6
10676 00:46:48.529270 <6>[ 3.510014] thunder_xcv, ver 1.0
10677 00:46:48.533079 <6>[ 3.513510] thunder_bgx, ver 1.0
10678 00:46:48.536655 <6>[ 3.517009] nicpf, ver 1.0
10679 00:46:48.547075 <6>[ 3.521086] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10680 00:46:48.549816 <6>[ 3.528562] hns3: Copyright (c) 2017 Huawei Corporation.
10681 00:46:48.553395 <6>[ 3.534155] hclge is initializing
10682 00:46:48.560184 <6>[ 3.537734] e1000: Intel(R) PRO/1000 Network Driver
10683 00:46:48.566848 <6>[ 3.542864] e1000: Copyright (c) 1999-2006 Intel Corporation.
10684 00:46:48.570090 <6>[ 3.548878] e1000e: Intel(R) PRO/1000 Network Driver
10685 00:46:48.576413 <6>[ 3.554093] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10686 00:46:48.583278 <6>[ 3.560281] igb: Intel(R) Gigabit Ethernet Network Driver
10687 00:46:48.589755 <6>[ 3.565931] igb: Copyright (c) 2007-2014 Intel Corporation.
10688 00:46:48.596741 <6>[ 3.571768] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10689 00:46:48.603322 <6>[ 3.578285] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10690 00:46:48.606313 <6>[ 3.584753] sky2: driver version 1.30
10691 00:46:48.613482 <6>[ 3.589723] usbcore: registered new device driver r8152-cfgselector
10692 00:46:48.619775 <6>[ 3.596261] usbcore: registered new interface driver r8152
10693 00:46:48.626694 <6>[ 3.602079] VFIO - User Level meta-driver version: 0.3
10694 00:46:48.633029 <6>[ 3.610436] usbcore: registered new interface driver usb-storage
10695 00:46:48.639963 <6>[ 3.616888] usbcore: registered new device driver onboard-usb-hub
10696 00:46:48.648759 <6>[ 3.626169] mt6397-rtc mt6359-rtc: registered as rtc0
10697 00:46:48.659214 <6>[ 3.631635] mt6397-rtc mt6359-rtc: setting system clock to 2024-06-16T00:46:48 UTC (1718498808)
10698 00:46:48.661867 <6>[ 3.641241] i2c_dev: i2c /dev entries driver
10699 00:46:48.675809 <4>[ 3.653466] cpu cpu0: supply cpu not found, using dummy regulator
10700 00:46:48.682492 <4>[ 3.659897] cpu cpu1: supply cpu not found, using dummy regulator
10701 00:46:48.689059 <4>[ 3.666304] cpu cpu2: supply cpu not found, using dummy regulator
10702 00:46:48.695846 <4>[ 3.672708] cpu cpu3: supply cpu not found, using dummy regulator
10703 00:46:48.702243 <4>[ 3.679122] cpu cpu4: supply cpu not found, using dummy regulator
10704 00:46:48.709755 <4>[ 3.685524] cpu cpu5: supply cpu not found, using dummy regulator
10705 00:46:48.715431 <4>[ 3.691922] cpu cpu6: supply cpu not found, using dummy regulator
10706 00:46:48.721935 <4>[ 3.698320] cpu cpu7: supply cpu not found, using dummy regulator
10707 00:46:48.741102 <6>[ 3.718994] cpu cpu0: EM: created perf domain
10708 00:46:48.745043 <6>[ 3.723834] cpu cpu4: EM: created perf domain
10709 00:46:48.751712 <6>[ 3.729438] sdhci: Secure Digital Host Controller Interface driver
10710 00:46:48.758867 <6>[ 3.735871] sdhci: Copyright(c) Pierre Ossman
10711 00:46:48.765185 <6>[ 3.740824] Synopsys Designware Multimedia Card Interface Driver
10712 00:46:48.771511 <6>[ 3.747488] sdhci-pltfm: SDHCI platform and OF driver helper
10713 00:46:48.774863 <6>[ 3.747539] mmc0: CQHCI version 5.10
10714 00:46:48.781367 <6>[ 3.757887] ledtrig-cpu: registered to indicate activity on CPUs
10715 00:46:48.788202 <6>[ 3.764908] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10716 00:46:48.795075 <6>[ 3.771987] usbcore: registered new interface driver usbhid
10717 00:46:48.798414 <6>[ 3.777809] usbhid: USB HID core driver
10718 00:46:48.804922 <6>[ 3.782015] spi_master spi0: will run message pump with realtime priority
10719 00:46:48.849394 <6>[ 3.820306] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10720 00:46:48.869010 <6>[ 3.835759] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10721 00:46:48.871944 <6>[ 3.849967] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x15014
10722 00:46:48.878932 <6>[ 3.856240] cros-ec-spi spi0.0: Chrome EC device registered
10723 00:46:48.885618 <6>[ 3.862264] mmc0: Command Queue Engine enabled
10724 00:46:48.891854 <6>[ 3.867023] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10725 00:46:48.895292 <6>[ 3.874686] mmcblk0: mmc0:0001 DA4128 116 GiB
10726 00:46:48.906578 <6>[ 3.884221] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10727 00:46:48.914238 <6>[ 3.891800] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10728 00:46:48.921140 <6>[ 3.897875] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10729 00:46:48.930741 <6>[ 3.897923] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10730 00:46:48.937517 <6>[ 3.903737] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10731 00:46:48.941229 <6>[ 3.913399] NET: Registered PF_PACKET protocol family
10732 00:46:48.947791 <6>[ 3.924309] 9pnet: Installing 9P2000 support
10733 00:46:48.950436 <5>[ 3.928877] Key type dns_resolver registered
10734 00:46:48.954117 <6>[ 3.933884] registered taskstats version 1
10735 00:46:48.960506 <5>[ 3.938256] Loading compiled-in X.509 certificates
10736 00:46:48.988679 <4>[ 3.959521] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10737 00:46:48.998312 <4>[ 3.970263] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10738 00:46:49.017304 <6>[ 3.994398] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10739 00:46:49.023493 <6>[ 4.001239] xhci-mtk 11200000.usb: xHCI Host Controller
10740 00:46:49.030424 <6>[ 4.006746] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10741 00:46:49.040210 <6>[ 4.014599] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10742 00:46:49.047009 <6>[ 4.024031] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10743 00:46:49.053819 <6>[ 4.030125] xhci-mtk 11200000.usb: xHCI Host Controller
10744 00:46:49.060627 <6>[ 4.035617] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10745 00:46:49.067216 <6>[ 4.043374] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10746 00:46:49.074041 <6>[ 4.051295] hub 1-0:1.0: USB hub found
10747 00:46:49.077087 <6>[ 4.055346] hub 1-0:1.0: 1 port detected
10748 00:46:49.087008 <6>[ 4.059657] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10749 00:46:49.090594 <6>[ 4.068431] hub 2-0:1.0: USB hub found
10750 00:46:49.093730 <6>[ 4.072453] hub 2-0:1.0: 1 port detected
10751 00:46:49.102704 <6>[ 4.080445] mtk-msdc 11f70000.mmc: Got CD GPIO
10752 00:46:49.121237 <6>[ 4.094942] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10753 00:46:49.130687 <6>[ 4.103345] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10754 00:46:49.137253 <6>[ 4.111688] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10755 00:46:49.146862 <6>[ 4.120027] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10756 00:46:49.153676 <6>[ 4.128365] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10757 00:46:49.163897 <6>[ 4.136703] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10758 00:46:49.170472 <6>[ 4.145040] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10759 00:46:49.179997 <6>[ 4.153379] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10760 00:46:49.186987 <6>[ 4.161717] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10761 00:46:49.196668 <6>[ 4.170056] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10762 00:46:49.203336 <6>[ 4.178405] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10763 00:46:49.213394 <6>[ 4.186743] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10764 00:46:49.219975 <6>[ 4.195081] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10765 00:46:49.229940 <6>[ 4.203421] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10766 00:46:49.237343 <6>[ 4.211760] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10767 00:46:49.243315 <6>[ 4.220482] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10768 00:46:49.250029 <6>[ 4.227687] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10769 00:46:49.256907 <6>[ 4.234473] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10770 00:46:49.267036 <6>[ 4.241249] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10771 00:46:49.273581 <6>[ 4.248243] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10772 00:46:49.280382 <6>[ 4.255094] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10773 00:46:49.290264 <6>[ 4.264227] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10774 00:46:49.299929 <6>[ 4.273347] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10775 00:46:49.309821 <6>[ 4.282641] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10776 00:46:49.319677 <6>[ 4.292108] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10777 00:46:49.329526 <6>[ 4.301575] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10778 00:46:49.336339 <6>[ 4.310694] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10779 00:46:49.346179 <6>[ 4.320161] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10780 00:46:49.356239 <6>[ 4.329280] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10781 00:46:49.366438 <6>[ 4.338578] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10782 00:46:49.376827 <6>[ 4.348737] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10783 00:46:49.386345 <6>[ 4.360609] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10784 00:46:49.484064 <6>[ 4.458435] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10785 00:46:49.513040 <6>[ 4.490600] hub 2-1:1.0: USB hub found
10786 00:46:49.516062 <6>[ 4.495119] hub 2-1:1.0: 3 ports detected
10787 00:46:49.527183 <6>[ 4.504730] hub 2-1:1.0: USB hub found
10788 00:46:49.530776 <6>[ 4.509107] hub 2-1:1.0: 3 ports detected
10789 00:46:49.636036 <6>[ 4.610116] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10790 00:46:49.790793 <6>[ 4.768231] hub 1-1:1.0: USB hub found
10791 00:46:49.794244 <6>[ 4.772733] hub 1-1:1.0: 4 ports detected
10792 00:46:49.806956 <6>[ 4.784461] hub 1-1:1.0: USB hub found
10793 00:46:49.810218 <6>[ 4.788960] hub 1-1:1.0: 4 ports detected
10794 00:46:49.872138 <6>[ 4.846380] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10795 00:46:49.980587 <6>[ 4.954902] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10796 00:46:50.016618 <4>[ 4.990552] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10797 00:46:50.026456 <4>[ 4.999652] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10798 00:46:50.070124 <6>[ 5.047291] r8152 2-1.3:1.0 eth0: v1.12.13
10799 00:46:50.140138 <6>[ 5.114152] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10800 00:46:50.272813 <6>[ 5.250280] hub 1-1.4:1.0: USB hub found
10801 00:46:50.276134 <6>[ 5.254966] hub 1-1.4:1.0: 2 ports detected
10802 00:46:50.291620 <6>[ 5.268682] hub 1-1.4:1.0: USB hub found
10803 00:46:50.294186 <6>[ 5.273292] hub 1-1.4:1.0: 2 ports detected
10804 00:46:50.592337 <6>[ 5.566178] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10805 00:46:50.787707 <6>[ 5.762002] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10806 00:46:51.670273 <6>[ 6.647816] r8152 2-1.3:1.0 eth0: carrier on
10807 00:46:54.707518 <5>[ 6.678027] Sending DHCP requests .., OK
10808 00:46:54.714648 <6>[ 9.690401] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.12
10809 00:46:54.717880 <6>[ 9.698709] IP-Config: Complete:
10810 00:46:54.731064 <6>[ 9.702213] device=eth0, hwaddr=00:e0:4c:78:7a:aa, ipaddr=192.168.201.12, mask=255.255.255.0, gw=192.168.201.1
10811 00:46:54.737664 <6>[ 9.712938] host=mt8192-asurada-spherion-r0-cbg-0, domain=lava-rack, nis-domain=(none)
10812 00:46:54.744153 <6>[ 9.721591] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10813 00:46:54.751034 <6>[ 9.721602] nameserver0=192.168.201.1
10814 00:46:54.754190 <6>[ 9.733755] clk: Disabling unused clocks
10815 00:46:54.758138 <6>[ 9.739370] ALSA device list:
10816 00:46:54.764659 <6>[ 9.742690] No soundcards found.
10817 00:46:54.772797 <6>[ 9.750561] Freeing unused kernel memory: 8512K
10818 00:46:54.775870 <6>[ 9.755467] Run /init as init process
10819 00:46:54.806104 <6>[ 9.784386] NET: Registered PF_INET6 protocol family
10820 00:46:54.813500 <6>[ 9.791526] Segment Routing with IPv6
10821 00:46:54.816999 <6>[ 9.795482] In-situ OAM (IOAM) with IPv6
10822 00:46:54.857378 <30>[ 9.809201] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10823 00:46:54.864361 <30>[ 9.842261] systemd[1]: Detected architecture arm64.
10824 00:46:54.864852
10825 00:46:54.870995 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10826 00:46:54.871503
10827 00:46:54.884283 <30>[ 9.862306] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10828 00:46:55.007009 <30>[ 9.981584] systemd[1]: Queued start job for default target graphical.target.
10829 00:46:55.049251 <30>[ 10.024082] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10830 00:46:55.055868 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10831 00:46:55.076197 <30>[ 10.050746] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10832 00:46:55.086137 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10833 00:46:55.105408 <30>[ 10.079738] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10834 00:46:55.115169 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10835 00:46:55.132686 <30>[ 10.107518] systemd[1]: Created slice user.slice - User and Session Slice.
10836 00:46:55.139307 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10837 00:46:55.162838 <30>[ 10.134803] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10838 00:46:55.173095 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10839 00:46:55.190764 <30>[ 10.162334] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10840 00:46:55.197042 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10841 00:46:55.225406 <30>[ 10.190697] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10842 00:46:55.235184 <30>[ 10.210624] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10843 00:46:55.242365 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10844 00:46:55.259252 <30>[ 10.234181] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10845 00:46:55.265771 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10846 00:46:55.283304 <30>[ 10.258230] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10847 00:46:55.293585 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10848 00:46:55.308464 <30>[ 10.286337] systemd[1]: Reached target paths.target - Path Units.
10849 00:46:55.318250 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10850 00:46:55.335454 <30>[ 10.310599] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10851 00:46:55.342352 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10852 00:46:55.356041 <30>[ 10.334142] systemd[1]: Reached target slices.target - Slice Units.
10853 00:46:55.365857 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10854 00:46:55.379956 <30>[ 10.358555] systemd[1]: Reached target swap.target - Swaps.
10855 00:46:55.386191 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10856 00:46:55.407503 <30>[ 10.382665] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10857 00:46:55.417480 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10858 00:46:55.436103 <30>[ 10.411171] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10859 00:46:55.445501 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10860 00:46:55.464572 <30>[ 10.439865] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10861 00:46:55.474122 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10862 00:46:55.491597 <30>[ 10.466927] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10863 00:46:55.501533 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10864 00:46:55.520485 <30>[ 10.495546] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10865 00:46:55.526567 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10866 00:46:55.548038 <30>[ 10.522912] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10867 00:46:55.557840 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10868 00:46:55.575489 <30>[ 10.550699] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10869 00:46:55.585221 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10870 00:46:55.639592 <30>[ 10.614421] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10871 00:46:55.646090 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10872 00:46:55.670180 <30>[ 10.645171] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10873 00:46:55.676572 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10874 00:46:55.701250 <30>[ 10.676369] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10875 00:46:55.707376 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10876 00:46:55.733890 <30>[ 10.702464] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10877 00:46:55.746569 <30>[ 10.721679] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10878 00:46:55.756624 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10879 00:46:55.779763 <30>[ 10.755234] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10880 00:46:55.786543 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10881 00:46:55.848216 <30>[ 10.822893] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10882 00:46:55.857282 Startin<6>[ 10.832277] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10883 00:46:55.863861 g [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10884 00:46:55.888569 <30>[ 10.863968] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10885 00:46:55.894882 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10886 00:46:55.955439 <30>[ 10.930683] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10887 00:46:55.964935 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10888 00:46:55.988482 <30>[ 10.963634] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10889 00:46:55.995101 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10890 00:46:56.024280 <30>[ 10.999752] systemd[1]: Starting systemd-journald.service - Journal Service...
10891 00:46:56.031124 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10892 00:46:56.049137 <30>[ 11.024833] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10893 00:46:56.056109 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10894 00:46:56.081234 <30>[ 11.053136] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10895 00:46:56.087288 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10896 00:46:56.111272 <30>[ 11.086622] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10897 00:46:56.120960 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10898 00:46:56.144519 <30>[ 11.119693] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10899 00:46:56.150630 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10900 00:46:56.174548 <30>[ 11.149639] systemd[1]: Started systemd-journald.service - Journal Service.
10901 00:46:56.180625 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10902 00:46:56.201462 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10903 00:46:56.219900 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10904 00:46:56.240375 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10905 00:46:56.260391 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10906 00:46:56.281284 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10907 00:46:56.300832 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10908 00:46:56.325836 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10909 00:46:56.350098 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10910 00:46:56.374144 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10911 00:46:56.393826 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10912 00:46:56.412546 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10913 00:46:56.433736 [[0;1;31mFAILED[0m] Failed to start [0;1;39msystemd-re…ount Root and Kernel File Systems.
10914 00:46:56.451772 See 'systemctl status systemd-remount-fs.service' for details.
10915 00:46:56.476481 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10916 00:46:56.502109 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10917 00:46:56.568108 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10918 00:46:56.592662 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10919 00:46:56.613165 <46>[ 11.588517] systemd-journald[185]: Received client request to flush runtime journal.
10920 00:46:56.620151 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10921 00:46:56.642802 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10922 00:46:56.667126 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10923 00:46:56.698538 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10924 00:46:56.720326 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10925 00:46:56.740304 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10926 00:46:56.760388 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10927 00:46:56.780493 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10928 00:46:56.827085 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10929 00:46:56.849683 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10930 00:46:56.867078 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10931 00:46:56.882926 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10932 00:46:56.935540 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10933 00:46:56.960051 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10934 00:46:56.983361 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10935 00:46:57.015047 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10936 00:46:57.039563 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10937 00:46:57.056879 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10938 00:46:57.115089 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10939 00:46:57.134344 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10940 00:46:57.159738 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10941 00:46:57.268338 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10942 00:46:57.286486 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10943 00:46:57.306073 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
10944 00:46:57.325497 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
10945 00:46:57.344183 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
10946 00:46:57.363900 [[0;32m OK [0m] Listening on [0;1;39mdbus.s<6>[ 12.339715] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10947 00:46:57.373857 ocket[…- D-Bus System Message<6>[ 12.349001] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10948 00:46:57.380973 <6>[ 12.349695] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10949 00:46:57.384263 Bus Socket.
10950 00:46:57.390576 <6>[ 12.366733] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10951 00:46:57.401085 <6>[ 12.367300] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10952 00:46:57.410669 <6>[ 12.376412] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10953 00:46:57.414109 <6>[ 12.383568] remoteproc remoteproc0: scp is available
10954 00:46:57.420364 <6>[ 12.383643] remoteproc remoteproc0: powering up scp
10955 00:46:57.427129 <6>[ 12.383648] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10956 00:46:57.434169 <6>[ 12.383671] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10957 00:46:57.440632 <6>[ 12.384487] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10958 00:46:57.450824 <4>[ 12.425909] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10959 00:46:57.460587 <3>[ 12.427093] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10960 00:46:57.470691 [[0;32m OK [<6>[ 12.435574] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10961 00:46:57.476946 <3>[ 12.443165] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10962 00:46:57.483482 <3>[ 12.443177] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10963 00:46:57.493743 0m] Reached targ<3>[ 12.445160] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10964 00:46:57.503679 et [0;1;39msock<6>[ 12.452764] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10965 00:46:57.513227 ets.target[0m -<4>[ 12.457543] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10966 00:46:57.520291 <4>[ 12.459487] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10967 00:46:57.520369 Socket Units.
10968 00:46:57.527071 <6>[ 12.459869] mc: Linux media interface: v0.10
10969 00:46:57.533609 <3>[ 12.460807] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10970 00:46:57.543126 <6>[ 12.478784] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10971 00:46:57.550496 <3>[ 12.487784] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10972 00:46:57.550573
10973 00:46:57.557506 <6>[ 12.495279] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10974 00:46:57.563740 <6>[ 12.496417] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10975 00:46:57.573985 <3>[ 12.503686] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10976 00:46:57.580275 <6>[ 12.509605] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10977 00:46:57.590599 <6>[ 12.509788] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10978 00:46:57.597268 <6>[ 12.509788] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10979 00:46:57.604540 <6>[ 12.509803] remoteproc remoteproc0: remote processor scp is now up
10980 00:46:57.611553 <6>[ 12.513543] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10981 00:46:57.614591 <6>[ 12.513555] pci_bus 0000:00: root bus resource [bus 00-ff]
10982 00:46:57.621790 <6>[ 12.513565] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10983 00:46:57.631529 <6>[ 12.513570] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10984 00:46:57.637968 <6>[ 12.513614] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10985 00:46:57.647976 <6>[ 12.513634] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10986 00:46:57.651533 <6>[ 12.513713] pci 0000:00:00.0: supports D1 D2
10987 00:46:57.658218 <6>[ 12.513717] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10988 00:46:57.665661 <3>[ 12.517683] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10989 00:46:57.675849 <4>[ 12.520485] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10990 00:46:57.679122 <4>[ 12.520485] Fallback method does not support PEC.
10991 00:46:57.689921 <6>[ 12.525587] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10992 00:46:57.696291 <3>[ 12.533760] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10993 00:46:57.706736 <6>[ 12.533925] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10994 00:46:57.710512 <6>[ 12.534058] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10995 00:46:57.720451 <6>[ 12.534093] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10996 00:46:57.727262 <6>[ 12.534115] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10997 00:46:57.733553 <6>[ 12.534133] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10998 00:46:57.737323 <6>[ 12.534257] pci 0000:01:00.0: supports D1 D2
10999 00:46:57.747413 <6>[ 12.534261] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
11000 00:46:57.750582 <6>[ 12.541566] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
11001 00:46:57.760785 <3>[ 12.549300] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11002 00:46:57.767429 <3>[ 12.549304] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11003 00:46:57.777903 <3>[ 12.549308] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11004 00:46:57.784846 <3>[ 12.549415] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11005 00:46:57.791453 <3>[ 12.549421] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11006 00:46:57.801586 <3>[ 12.550998] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11007 00:46:57.807842 <6>[ 12.557555] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
11008 00:46:57.818534 <6>[ 12.558781] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
11009 00:46:57.825289 <6>[ 12.560549] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
11010 00:46:57.835373 <3>[ 12.565334] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11011 00:46:57.841816 <6>[ 12.569480] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
11012 00:46:57.854979 <6>[ 12.573152] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
11013 00:46:57.861795 <6>[ 12.573467] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
11014 00:46:57.871843 <6>[ 12.573844] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
11015 00:46:57.878424 <3>[ 12.580892] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11016 00:46:57.888441 <6>[ 12.587318] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
11017 00:46:57.891664 <6>[ 12.587879] videodev: Linux video capture interface: v2.00
11018 00:46:57.901535 <3>[ 12.594180] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11019 00:46:57.907946 <6>[ 12.599927] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
11020 00:46:57.918040 <3>[ 12.606111] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11021 00:46:57.924861 <3>[ 12.606862] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
11022 00:46:57.934791 <3>[ 12.607080] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11023 00:46:57.937977 <6>[ 12.608118] Bluetooth: Core ver 2.22
11024 00:46:57.944528 <6>[ 12.608313] NET: Registered PF_BLUETOOTH protocol family
11025 00:46:57.951491 <6>[ 12.608323] Bluetooth: HCI device and connection manager initialized
11026 00:46:57.954548 <6>[ 12.608364] Bluetooth: HCI socket layer initialized
11027 00:46:57.960950 <6>[ 12.608395] Bluetooth: L2CAP socket layer initialized
11028 00:46:57.964603 <6>[ 12.608430] Bluetooth: SCO socket layer initialized
11029 00:46:57.974728 <6>[ 12.616955] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
11030 00:46:57.981095 <6>[ 12.643013] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
11031 00:46:57.987389 <6>[ 12.650149] pci 0000:00:00.0: PCI bridge to [bus 01]
11032 00:46:57.994265 <3>[ 12.661484] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11033 00:46:58.004128 <3>[ 12.662909] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
11034 00:46:58.011072 <6>[ 12.664964] usbcore: registered new interface driver btusb
11035 00:46:58.020957 <4>[ 12.665614] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
11036 00:46:58.027493 <3>[ 12.665623] Bluetooth: hci0: Failed to load firmware file (-2)
11037 00:46:58.030626 <3>[ 12.665626] Bluetooth: hci0: Failed to set up firmware (-2)
11038 00:46:58.040644 <4>[ 12.665630] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
11039 00:46:58.054097 <6>[ 12.666068] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
11040 00:46:58.060817 <6>[ 12.666155] usbcore: registered new interface driver uvcvideo
11041 00:46:58.067047 <6>[ 12.673167] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
11042 00:46:58.073718 <6>[ 12.673840] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
11043 00:46:58.084035 <3>[ 12.676613] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11044 00:46:58.093836 <3>[ 12.700441] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11045 00:46:58.100655 <6>[ 12.703629] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
11046 00:46:58.107006 <3>[ 12.732517] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11047 00:46:58.113773 <6>[ 12.736790] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
11048 00:46:58.123601 <3>[ 12.765466] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11049 00:46:58.129982 <6>[ 12.768835] pcieport 0000:00:00.0: AER: enabled with IRQ 283
11050 00:46:58.137063 <3>[ 12.800160] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11051 00:46:58.146428 <5>[ 12.831601] cfg80211: Loading compiled-in X.509 certificates for regulatory database
11052 00:46:58.153382 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
11053 00:46:58.160790 <5>[ 13.139611] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
11054 00:46:58.171863 <5>[ 13.146695] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
11055 00:46:58.181859 <4>[ 13.155109] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
11056 00:46:58.185190 <6>[ 13.163991] cfg80211: failed to load regulatory.db
11057 00:46:58.214321 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11058 00:46:58.227983 <6>[ 13.203493] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
11059 00:46:58.234923 <6>[ 13.211189] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
11060 00:46:58.255820 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management..<6>[ 13.234274] mt7921e 0000:01:00.0: ASIC revision: 79610010
11061 00:46:58.255898 .
11062 00:46:58.303923 Starting [0;1;39msyste<46>[ 13.264757] systemd-journald[185]: Data hash table of /var/log/journal/c3f909ee3e324895ab90ff2613af9260/system.journal has a fill level at 75.2 (1539 of 2047 items, 524288 file size, 340 bytes per hash table item), suggesting rotation.
11063 00:46:58.320502 md-user-sess…v<46>[ 13.287167] systemd-journald[185]: /var/log/journal/c3f909ee3e324895ab90ff2613af9260/system.journal: Journal header limits reached or header out-of-date, rotating.
11064 00:46:58.323659 ice[0m - Permit User Sessions...
11065 00:46:58.347558 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11066 00:46:58.357872 <6>[ 13.331964] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
11067 00:46:58.357950 <6>[ 13.331964]
11068 00:46:58.384945 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11069 00:46:58.443063 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11070 00:46:58.464220 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
11071 00:46:58.484118 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
11072 00:46:58.503403 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11073 00:46:58.562344 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11074 00:46:58.612392 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11075 00:46:58.626644 <6>[ 13.602391] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
11076 00:46:58.637327 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11077 00:46:58.653486 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11078 00:46:58.672765 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11079 00:46:58.740226 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
11080 00:46:58.764739 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11081 00:46:58.789217 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11082 00:46:58.860278 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11083 00:46:58.878164 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11084 00:46:58.902109 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11085 00:46:58.958856
11086 00:46:58.962477 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11087 00:46:58.962552
11088 00:46:58.965678 debian-bookworm-arm64 login: root (automatic login)
11089 00:46:58.965753
11090 00:46:58.978079 Linux debian-bookworm-arm64 6.1.92-cip22 #1 SMP PREEMPT Sun Jun 16 00:28:47 UTC 2024 aarch64
11091 00:46:58.978154
11092 00:46:58.984436 The programs included with the Debian GNU/Linux system are free software;
11093 00:46:58.991326 the exact distribution terms for each program are described in the
11094 00:46:58.994471 individual files in /usr/share/doc/*/copyright.
11095 00:46:58.994575
11096 00:46:59.001480 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11097 00:46:59.004609 permitted by applicable law.
11098 00:46:59.004978 Matched prompt #10: / #
11100 00:46:59.005159 Setting prompt string to ['/ #']
11101 00:46:59.005244 end: 2.2.5.1 login-action (duration 00:00:15) [common]
11103 00:46:59.005418 end: 2.2.5 auto-login-action (duration 00:00:15) [common]
11104 00:46:59.005494 start: 2.2.6 expect-shell-connection (timeout 00:03:20) [common]
11105 00:46:59.005583 Setting prompt string to ['/ #']
11106 00:46:59.005654 Forcing a shell prompt, looking for ['/ #']
11108 00:46:59.055857 / #
11109 00:46:59.056003 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11110 00:46:59.056071 Waiting using forced prompt support (timeout 00:02:30)
11111 00:46:59.060970
11112 00:46:59.061230 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11113 00:46:59.061321 start: 2.2.7 export-device-env (timeout 00:03:20) [common]
11114 00:46:59.061406 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11115 00:46:59.061486 end: 2.2 depthcharge-retry (duration 00:01:40) [common]
11116 00:46:59.061591 end: 2 depthcharge-action (duration 00:01:40) [common]
11117 00:46:59.061682 start: 3 lava-test-retry (timeout 00:07:55) [common]
11118 00:46:59.061762 start: 3.1 lava-test-shell (timeout 00:07:55) [common]
11119 00:46:59.061828 Using namespace: common
11121 00:46:59.162137 / # #
11122 00:46:59.162300 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11123 00:46:59.167780 #
11124 00:46:59.168032 Using /lava-14368423
11126 00:46:59.268346 / # export SHELL=/bin/sh
11127 00:46:59.273533 export SHELL=/bin/sh
11129 00:46:59.374050 / # . /lava-14368423/environment
11130 00:46:59.379489 . /lava-14368423/environment
11132 00:46:59.480005 / # /lava-14368423/bin/lava-test-runner /lava-14368423/0
11133 00:46:59.480164 Test shell timeout: 10s (minimum of the action and connection timeout)
11134 00:46:59.485514 /lava-14368423/bin/lava-test-runner /lava-14368423/0
11135 00:46:59.497446 <6>[ 14.476205] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11136 00:46:59.514264 + export TESTRUN_ID=0_igt-gpu-panf<8>[ 14.492580] <LAVA_SIGNAL_STARTRUN 0_igt-gpu-panfrost 14368423_1.5.2.3.1>
11137 00:46:59.514516 Received signal: <STARTRUN> 0_igt-gpu-panfrost 14368423_1.5.2.3.1
11138 00:46:59.514584 Starting test lava.0_igt-gpu-panfrost (14368423_1.5.2.3.1)
11139 00:46:59.514660 Skipping test definition patterns.
11140 00:46:59.517342 rost
11141 00:46:59.521113 + cd /lava-14368423/0/tests/0_igt-gpu-panfrost
11142 00:46:59.521189 + cat uuid
11143 00:46:59.524168 + UUID=14368423_1.5.2.3.1
11144 00:46:59.524244 + set +x
11145 00:46:59.533998 + IGT_FORCE_DRIVER=panfrost /usr/bin/igt-parser.sh panfrost_gem_new panfrost_get_param panfrost_prime panfrost_submit
11146 00:46:59.540452 <8>[ 14.519637] <LAVA_SIGNAL_TESTSET START panfrost_gem_new>
11147 00:46:59.540696 Received signal: <TESTSET> START panfrost_gem_new
11148 00:46:59.540766 Starting test_set panfrost_gem_new
11149 00:46:59.561696 <14>[ 14.541096] [IGT] panfrost_gem_new: executing
11150 00:46:59.568522 IGT-Version: 1.28-ga44ebfe (aarc<14>[ 14.548204] [IGT] panfrost_gem_new: exiting, ret=77
11151 00:46:59.571711 h64) (Linux: 6.1.92-cip22 aarch64)
11152 00:46:59.581906 Received signal: <TESTCASE> TEST_CASE_ID=gem-new-4096 RESULT=skip
11154 00:46:59.585387 Using IGT_SRANDOM=1718498819 for randomisati<8>[ 14.559746] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-new-4096 RESULT=skip>
11155 00:46:59.585463 on
11156 00:46:59.591882 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
11157 00:46:59.595398 Test requirement: !(fd<0)
11158 00:46:59.601512 No known gpu found for chipset flags 0x32 (panf<14>[ 14.581304] [IGT] panfrost_gem_new: executing
11159 00:46:59.601631 rost)
11160 00:46:59.611970 Last errno: 2, No such fi<14>[ 14.588757] [IGT] panfrost_gem_new: exiting, ret=77
11161 00:46:59.612046 le or directory
11162 00:46:59.615148 [1mSubtest gem-new-4096: SKIP (0.000s)[0m
11163 00:46:59.622049 IG<8>[ 14.599165] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-new-0 RESULT=skip>
11164 00:46:59.622294 Received signal: <TESTCASE> TEST_CASE_ID=gem-new-0 RESULT=skip
11166 00:46:59.628322 T-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11167 00:46:59.631528 Using IGT_SRANDOM=1718498819 for randomisation
11168 00:46:59.638447 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
11169 00:46:59.641420 Test requirement: !(fd<0)
11170 00:46:59.647912 No known gpu found for chipset flags 0x32 (panfrost)
11171 00:46:59.651585 Last errno:<14>[ 14.631446] [IGT] panfrost_gem_new: executing
11172 00:46:59.655154 2, No such file or directory
11173 00:46:59.661285 [1mSubtest gem-n<14>[ 14.639873] [IGT] panfrost_gem_new: exiting, ret=77
11174 00:46:59.664554 ew-0: SKIP (0.000s)[0m
11175 00:46:59.674609 IGT-Version: 1.28-ga44ebfe (aarch64) (L<8>[ 14.651538] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-new-zeroed RESULT=skip>
11176 00:46:59.674858 Received signal: <TESTCASE> TEST_CASE_ID=gem-new-zeroed RESULT=skip
11178 00:46:59.678359 inux: 6.1.92-cip22 aarch64)
11179 00:46:59.681514 Usi<8>[ 14.660238] <LAVA_SIGNAL_TESTSET STOP>
11180 00:46:59.681801 Received signal: <TESTSET> STOP
11181 00:46:59.681863 Closing test_set panfrost_gem_new
11182 00:46:59.684603 ng IGT_SRANDOM=1718498819 for randomisation
11183 00:46:59.691197 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
11184 00:46:59.694862 Test requirement: !(fd<0)
11185 00:46:59.697748 No known gpu found for chipset flags 0x32 (panfrost)
11186 00:46:59.704511 <8>[ 14.683030] <LAVA_SIGNAL_TESTSET START panfrost_get_param>
11187 00:46:59.704754 Received signal: <TESTSET> START panfrost_get_param
11188 00:46:59.704822 Starting test_set panfrost_get_param
11189 00:46:59.707971 Last errno: 2, No such file or directory
11190 00:46:59.714429 [1mSubtest gem-new-zeroed: SKIP (0.000s)[0m
11191 00:46:59.724042 <14>[ 14.703040] [IGT] panfrost_get_param: executing
11192 00:46:59.730786 IGT-Version: 1.28-ga44ebfe (aarc<14>[ 14.710159] [IGT] panfrost_get_param: exiting, ret=77
11193 00:46:59.733777 h64) (Linux: 6.1.92-cip22 aarch64)
11194 00:46:59.743861 Using IGT_SRANDOM=1718498819<8>[ 14.721138] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=base-params RESULT=skip>
11195 00:46:59.744110 Received signal: <TESTCASE> TEST_CASE_ID=base-params RESULT=skip
11197 00:46:59.747081 for randomisation
11198 00:46:59.753714 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
11199 00:46:59.756822 Test requirement: !(fd<0)
11200 00:46:59.763546 No known gpu found for chipset <14>[ 14.742236] [IGT] panfrost_get_param: executing
11201 00:46:59.766695 flags 0x32 (panfrost)
11202 00:46:59.770487 Last errn<14>[ 14.749710] [IGT] panfrost_get_param: exiting, ret=77
11203 00:46:59.773527 o: 2, No such file or directory
11204 00:46:59.776743 [1mSubtest base-params: SKIP (0.000s)[0m
11205 00:46:59.787114 IGT<8>[ 14.761647] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=get-bad-param RESULT=skip>
11206 00:46:59.787357 Received signal: <TESTCASE> TEST_CASE_ID=get-bad-param RESULT=skip
11208 00:46:59.790280 -Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11209 00:46:59.796693 Using IGT_SRANDOM=1718498819 for randomisation
11210 00:46:59.806615 Test requirement not met in function drm_open_driver, file ../l<14>[ 14.784388] [IGT] panfrost_get_param: executing
11211 00:46:59.806691 ib/drmtest.c:694:
11212 00:46:59.813856 Test requirem<14>[ 14.792154] [IGT] panfrost_get_param: exiting, ret=77
11213 00:46:59.816808 ent: !(fd<0)
11214 00:46:59.820287 No known gpu found for chipset flags 0x32 (panfrost)
11215 00:46:59.826950 Last errno: <8>[ 14.804231] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=get-bad-padding RESULT=skip>
11216 00:46:59.827192 Received signal: <TESTCASE> TEST_CASE_ID=get-bad-padding RESULT=skip
11218 00:46:59.830137 2, No such file or directory
11219 00:46:59.833561 Received signal: <TESTSET> STOP
11220 00:46:59.833635 Closing test_set panfrost_get_param
11221 00:46:59.836557 [<8>[ 14.814099] <LAVA_SIGNAL_TESTSET STOP>
11222 00:46:59.839780 1mSubtest get-bad-param: SKIP (0.000s)[0m
11223 00:46:59.846575 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11224 00:46:59.849738 Using IGT_SRANDOM=1718498819 for randomisation
11225 00:46:59.859868 Test requirement not met in function drm_open_dr<8>[ 14.837159] <LAVA_SIGNAL_TESTSET START panfrost_prime>
11226 00:46:59.860112 Received signal: <TESTSET> START panfrost_prime
11227 00:46:59.860213 Starting test_set panfrost_prime
11228 00:46:59.863280 iver, file ../lib/drmtest.c:694:
11229 00:46:59.863354 Test requirement: !(fd<0)
11230 00:46:59.869938 No known gpu found for chipset flags 0x32 (panfrost)
11231 00:46:59.873475 Last errno: 2, No such file or directory
11232 00:46:59.876649 [1<14>[ 14.856771] [IGT] panfrost_prime: executing
11233 00:46:59.886145 mSubtest get-bad-padding: SKIP (<14>[ 14.863612] [IGT] panfrost_prime: exiting, ret=77
11234 00:46:59.886221 0.000s)[0m
11235 00:46:59.896595 Received signal: <TESTCASE> TEST_CASE_ID=gem-prime-import RESULT=skip
11237 00:46:59.899575 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92<8>[ 14.874824] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-prime-import RESULT=skip>
11238 00:46:59.899651 -cip22 aarch64)
11239 00:46:59.905993 Using IGT_SRAND<8>[ 14.883562] <LAVA_SIGNAL_TESTSET STOP>
11240 00:46:59.906068 OM=1718498819 for randomisation
11241 00:46:59.906292 Received signal: <TESTSET> STOP
11242 00:46:59.906351 Closing test_set panfrost_prime
11243 00:46:59.916278 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
11244 00:46:59.916354 Test requirement: !(fd<0)
11245 00:46:59.922994 No known gpu found for chipset flags 0x32 (panfrost)
11246 00:46:59.926060 Last errno: 2, No such file or directory
11247 00:46:59.929795 [1mSubtest gem-prime-import: SKIP (0.000s)[0m
11248 00:46:59.936515 <8>[ 14.915827] <LAVA_SIGNAL_TESTSET START panfrost_submit>
11249 00:46:59.936759 Received signal: <TESTSET> START panfrost_submit
11250 00:46:59.936823 Starting test_set panfrost_submit
11251 00:46:59.957070 <14>[ 14.936280] [IGT] panfrost_submit: executing
11252 00:46:59.964116 IGT-Version: 1.28-ga44ebfe (aarc<14>[ 14.943084] [IGT] panfrost_submit: exiting, ret=77
11253 00:46:59.967037 h64) (Linux: 6.1.92-cip22 aarch64)
11254 00:46:59.976895 Using IGT_SRANDOM=1718498819<8>[ 14.953675] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit RESULT=skip>
11255 00:46:59.977139 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit RESULT=skip
11257 00:46:59.980269 for randomisation
11258 00:46:59.986927 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
11259 00:46:59.987002 Test requirement: !(fd<0)
11260 00:46:59.993678 No known gpu found for chipset flags 0x32 (panfrost)
11261 00:46:59.996606 Last errno: 2, No such file or directory
11262 00:47:00.000170 [1mSubtest pan-submit: SKIP (0.000s)[0m
11263 00:47:00.006639 <14>[ 14.985724] [IGT] panfrost_submit: executing
11264 00:47:00.016873 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1<14>[ 14.993829] [IGT] panfrost_submit: exiting, ret=77
11265 00:47:00.016949 .92-cip22 aarch64)
11266 00:47:00.019948 Using IGT_SRANDOM=1718498819 for randomisation
11267 00:47:00.033681 Test requirement not met in <8>[ 15.008170] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-no-jc RESULT=skip>
11268 00:47:00.033925 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-no-jc RESULT=skip
11270 00:47:00.036634 function drm_open_driver, file ../lib/drmtest.c:694:
11271 00:47:00.039789 Test requirement: !(fd<0)
11272 00:47:00.043388 No known gpu found for chipset flags 0x32 (panfrost)
11273 00:47:00.046401 Last errno: 2, No such file or directory
11274 00:47:00.053222 [1mSubtest pan<14>[ 15.032313] [IGT] panfrost_submit: executing
11275 00:47:00.059857 -submit-error-no-jc: SKIP (0.000<14>[ 15.039696] [IGT] panfrost_submit: exiting, ret=77
11276 00:47:00.063553 s)[0m
11277 00:47:00.066937 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11278 00:47:00.076885 Usin<8>[ 15.051014] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-in-syncs RESULT=skip>
11279 00:47:00.077130 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-in-syncs RESULT=skip
11281 00:47:00.080395 g IGT_SRANDOM=1718498820 for randomisation
11282 00:47:00.086289 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
11283 00:47:00.090128 Test requirement: !(fd<0)
11284 00:47:00.096440 No know<14>[ 15.074273] [IGT] panfrost_submit: executing
11285 00:47:00.103361 n gpu found for chipset flags 0x<14>[ 15.081755] [IGT] panfrost_submit: exiting, ret=77
11286 00:47:00.103437 32 (panfrost)
11287 00:47:00.106493 Last errno: 2, No such file or directory
11288 00:47:00.116770 [1mSub<8>[ 15.092828] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-bo-handles RESULT=skip>
11289 00:47:00.117014 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-bo-handles RESULT=skip
11291 00:47:00.122996 test pan-submit-error-bad-in-syncs: SKIP (0.000s)[0m
11292 00:47:00.126389 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11293 00:47:00.132981 Using IGT_SRANDOM=1718498820 for randomisation
11294 00:47:00.139786 Test requirement not <14>[ 15.117592] [IGT] panfrost_submit: executing
11295 00:47:00.146404 met in function drm_open_driver,<14>[ 15.125436] [IGT] panfrost_submit: exiting, ret=77
11296 00:47:00.150070 file ../lib/drmtest.c:694:
11297 00:47:00.153067 Test requirement: !(fd<0)
11298 00:47:00.163263 No known gpu found for c<8>[ 15.136722] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-requirements RESULT=skip>
11299 00:47:00.163510 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-requirements RESULT=skip
11301 00:47:00.166874 hipset flags 0x32 (panfrost)
11302 00:47:00.170020 Last errno: 2, No such file or directory
11303 00:47:00.173310 [1mSubtest pan-submit-error-bad-bo-handles: SKIP (0.000s)[0m
11304 00:47:00.183348 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip2<14>[ 15.162738] [IGT] panfrost_submit: executing
11305 00:47:00.186374 2 aarch64)
11306 00:47:00.192936 Using IGT_SRANDOM=17<14>[ 15.170167] [IGT] panfrost_submit: exiting, ret=77
11307 00:47:00.193012 18498820 for randomisation
11308 00:47:00.206254 Test requirement not met in function<8>[ 15.181298] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-out-sync RESULT=skip>
11309 00:47:00.206497 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-out-sync RESULT=skip
11311 00:47:00.209502 drm_open_driver, file ../lib/drmtest.c:694:
11312 00:47:00.212716 Test requirement: !(fd<0)
11313 00:47:00.216378 No known gpu found for chipset flags 0x32 (panfrost)
11314 00:47:00.219506 Last errno: 2, No such file or directory
11315 00:47:00.226058 [1mSub<14>[ 15.203976] [IGT] panfrost_submit: executing
11316 00:47:00.232587 test pan-submit-error-bad-requir<14>[ 15.212198] [IGT] panfrost_submit: exiting, ret=77
11317 00:47:00.235943 ements: SKIP (0.000s)[0m
11318 00:47:00.245877 IGT-Version: 1.28-ga44ebfe (aarch64) <8>[ 15.223101] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-reset RESULT=skip>
11319 00:47:00.246120 Received signal: <TESTCASE> TEST_CASE_ID=pan-reset RESULT=skip
11321 00:47:00.249490 (Linux: 6.1.92-cip22 aarch64)
11322 00:47:00.252834 Using IGT_SRANDOM=1718498820 for randomisation
11323 00:47:00.259279 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
11324 00:47:00.266005 <14>[ 15.243570] [IGT] panfrost_submit: executing
11325 00:47:00.266080
11326 00:47:00.266138 Test requirement: !(fd<0)
11327 00:47:00.272604 No k<14>[ 15.250863] [IGT] panfrost_submit: exiting, ret=77
11328 00:47:00.275595 nown gpu found for chipset flags 0x32 (panfrost)
11329 00:47:00.285582 Last errno: 2, No such file or<8>[ 15.262553] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-and-close RESULT=skip>
11330 00:47:00.285840 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-and-close RESULT=skip
11332 00:47:00.288654 directory
11333 00:47:00.292395 [1mSubtest pan-submit-error-bad-out-sync: SKIP (0.000s)[0m
11334 00:47:00.298968 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11335 00:47:00.308547 Using IGT_SRANDOM=1718498820 for r<14>[ 15.285863] [IGT] panfrost_submit: executing
11336 00:47:00.308623 andomisation
11337 00:47:00.315262 Test requirement n<14>[ 15.293588] [IGT] panfrost_submit: exiting, ret=77
11338 00:47:00.321603 ot met in function drm_open_driver, file ../lib/drmtest.c:694:
11339 00:47:00.328214 <8>[ 15.304636] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-unhandled-pagefault RESULT=skip>
11340 00:47:00.328457 Received signal: <TESTCASE> TEST_CASE_ID=pan-unhandled-pagefault RESULT=skip
11342 00:47:00.331371 Test requirement: !(fd<0)
11343 00:47:00.334666 No kn<8>[ 15.314393] <LAVA_SIGNAL_TESTSET STOP>
11344 00:47:00.334907 Received signal: <TESTSET> STOP
11345 00:47:00.334969 Closing test_set panfrost_submit
11346 00:47:00.344616 own gpu found fo<8>[ 15.320329] <LAVA_SIGNAL_ENDRUN 0_igt-gpu-panfrost 14368423_1.5.2.3.1>
11347 00:47:00.344693 r chipset flags 0x32 (panfrost)
11348 00:47:00.344918 Received signal: <ENDRUN> 0_igt-gpu-panfrost 14368423_1.5.2.3.1
11349 00:47:00.344991 Ending use of test pattern.
11350 00:47:00.345045 Ending test lava.0_igt-gpu-panfrost (14368423_1.5.2.3.1), duration 0.83
11352 00:47:00.351369 Last errno: 2, No such file or directory
11353 00:47:00.354850 [1mSubtest pan-reset: SKIP (0.000s)[0m
11354 00:47:00.357960 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11355 00:47:00.365658 Using IGT_SRANDOM=1718498820 for randomisation
11356 00:47:00.371526 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
11357 00:47:00.374217 Test requirement: !(fd<0)
11358 00:47:00.377678 No known gpu found for chipset flags 0x32 (panfrost)
11359 00:47:00.380868 Last errno: 2, No such file or directory
11360 00:47:00.387824 [1mSubtest pan-submit-and-close: SKIP (0.000s)[0m
11361 00:47:00.391042 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11362 00:47:00.397245 Using IGT_SRANDOM=1718498820 for randomisation
11363 00:47:00.404187 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
11364 00:47:00.404263 Test requirement: !(fd<0)
11365 00:47:00.410768 No known gpu found for chipset flags 0x32 (panfrost)
11366 00:47:00.413938 Last errno: 2, No such file or directory
11367 00:47:00.417056 [1mSubtest pan-unhandled-pagefault: SKIP (0.000s)[0m
11368 00:47:00.420716 + set +x
11369 00:47:00.420793 <LAVA_TEST_RUNNER EXIT>
11370 00:47:00.421020 ok: lava_test_shell seems to have completed
11371 00:47:00.421312 base-params:
result: skip
set: panfrost_get_param
gem-new-0:
result: skip
set: panfrost_gem_new
gem-new-4096:
result: skip
set: panfrost_gem_new
gem-new-zeroed:
result: skip
set: panfrost_gem_new
gem-prime-import:
result: skip
set: panfrost_prime
get-bad-padding:
result: skip
set: panfrost_get_param
get-bad-param:
result: skip
set: panfrost_get_param
pan-reset:
result: skip
set: panfrost_submit
pan-submit:
result: skip
set: panfrost_submit
pan-submit-and-close:
result: skip
set: panfrost_submit
pan-submit-error-bad-bo-handles:
result: skip
set: panfrost_submit
pan-submit-error-bad-in-syncs:
result: skip
set: panfrost_submit
pan-submit-error-bad-out-sync:
result: skip
set: panfrost_submit
pan-submit-error-bad-requirements:
result: skip
set: panfrost_submit
pan-submit-error-no-jc:
result: skip
set: panfrost_submit
pan-unhandled-pagefault:
result: skip
set: panfrost_submit
11372 00:47:00.421409 end: 3.1 lava-test-shell (duration 00:00:01) [common]
11373 00:47:00.421486 end: 3 lava-test-retry (duration 00:00:01) [common]
11374 00:47:00.421593 start: 4 finalize (timeout 00:07:53) [common]
11375 00:47:00.421687 start: 4.1 power-off (timeout 00:00:30) [common]
11376 00:47:00.421819 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-0', '--port=1', '--command=off']
11377 00:47:02.494871 >> Command sent successfully.
11378 00:47:02.498070 Returned 0 in 2 seconds
11379 00:47:02.598403 end: 4.1 power-off (duration 00:00:02) [common]
11381 00:47:02.598672 start: 4.2 read-feedback (timeout 00:07:51) [common]
11382 00:47:02.598905 Listened to connection for namespace 'common' for up to 1s
11383 00:47:03.599889 Finalising connection for namespace 'common'
11384 00:47:03.600046 Disconnecting from shell: Finalise
11385 00:47:03.600117 / #
11386 00:47:03.700393 end: 4.2 read-feedback (duration 00:00:01) [common]
11387 00:47:03.700534 end: 4 finalize (duration 00:00:03) [common]
11388 00:47:03.700647 Cleaning after the job
11389 00:47:03.700741 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14368423/tftp-deploy-t4bmfn5s/ramdisk
11390 00:47:03.707325 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14368423/tftp-deploy-t4bmfn5s/kernel
11391 00:47:03.722359 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14368423/tftp-deploy-t4bmfn5s/dtb
11392 00:47:03.722533 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14368423/tftp-deploy-t4bmfn5s/modules
11393 00:47:03.727902 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14368423
11394 00:47:03.833506 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14368423
11395 00:47:03.833711 Job finished correctly