Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 27
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 24
1 00:39:32.625787 lava-dispatcher, installed at version: 2024.03
2 00:39:32.626019 start: 0 validate
3 00:39:32.626139 Start time: 2024-06-16 00:39:32.626131+00:00 (UTC)
4 00:39:32.626277 Using caching service: 'http://localhost/cache/?uri=%s'
5 00:39:32.626452 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-igt%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 00:39:32.877267 Using caching service: 'http://localhost/cache/?uri=%s'
7 00:39:32.877428 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22-24-g0315de64ea248%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 00:39:46.385118 Using caching service: 'http://localhost/cache/?uri=%s'
9 00:39:46.386017 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22-24-g0315de64ea248%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 00:39:46.639858 Using caching service: 'http://localhost/cache/?uri=%s'
11 00:39:46.640486 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22-24-g0315de64ea248%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 00:39:48.894487 validate duration: 16.27
14 00:39:48.895821 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 00:39:48.896387 start: 1.1 download-retry (timeout 00:10:00) [common]
16 00:39:48.896871 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 00:39:48.897603 Not decompressing ramdisk as can be used compressed.
18 00:39:48.898099 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-igt/20240313.0/arm64/rootfs.cpio.gz
19 00:39:48.898466 saving as /var/lib/lava/dispatcher/tmp/14368365/tftp-deploy-tu_dj_f6/ramdisk/rootfs.cpio.gz
20 00:39:48.898821 total size: 47897469 (45 MB)
21 00:39:49.151813 progress 0 % (0 MB)
22 00:39:49.164381 progress 5 % (2 MB)
23 00:39:49.176795 progress 10 % (4 MB)
24 00:39:49.189293 progress 15 % (6 MB)
25 00:39:49.201893 progress 20 % (9 MB)
26 00:39:49.215078 progress 25 % (11 MB)
27 00:39:49.227503 progress 30 % (13 MB)
28 00:39:49.239632 progress 35 % (16 MB)
29 00:39:49.251851 progress 40 % (18 MB)
30 00:39:49.263963 progress 45 % (20 MB)
31 00:39:49.276025 progress 50 % (22 MB)
32 00:39:49.288237 progress 55 % (25 MB)
33 00:39:49.300772 progress 60 % (27 MB)
34 00:39:49.313477 progress 65 % (29 MB)
35 00:39:49.325889 progress 70 % (32 MB)
36 00:39:49.338323 progress 75 % (34 MB)
37 00:39:49.350675 progress 80 % (36 MB)
38 00:39:49.362797 progress 85 % (38 MB)
39 00:39:49.375165 progress 90 % (41 MB)
40 00:39:49.387209 progress 95 % (43 MB)
41 00:39:49.399100 progress 100 % (45 MB)
42 00:39:49.399337 45 MB downloaded in 0.50 s (91.26 MB/s)
43 00:39:49.399498 end: 1.1.1 http-download (duration 00:00:01) [common]
45 00:39:49.399747 end: 1.1 download-retry (duration 00:00:01) [common]
46 00:39:49.399860 start: 1.2 download-retry (timeout 00:09:59) [common]
47 00:39:49.400013 start: 1.2.1 http-download (timeout 00:09:59) [common]
48 00:39:49.400188 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-24-g0315de64ea248/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 00:39:49.400254 saving as /var/lib/lava/dispatcher/tmp/14368365/tftp-deploy-tu_dj_f6/kernel/Image
50 00:39:49.400309 total size: 54813184 (52 MB)
51 00:39:49.400364 No compression specified
52 00:39:49.401417 progress 0 % (0 MB)
53 00:39:49.416453 progress 5 % (2 MB)
54 00:39:49.438686 progress 10 % (5 MB)
55 00:39:49.461433 progress 15 % (7 MB)
56 00:39:49.484301 progress 20 % (10 MB)
57 00:39:49.501937 progress 25 % (13 MB)
58 00:39:49.515850 progress 30 % (15 MB)
59 00:39:49.530807 progress 35 % (18 MB)
60 00:39:49.546029 progress 40 % (20 MB)
61 00:39:49.561153 progress 45 % (23 MB)
62 00:39:49.576320 progress 50 % (26 MB)
63 00:39:49.591301 progress 55 % (28 MB)
64 00:39:49.606057 progress 60 % (31 MB)
65 00:39:49.621333 progress 65 % (34 MB)
66 00:39:49.635882 progress 70 % (36 MB)
67 00:39:49.649890 progress 75 % (39 MB)
68 00:39:49.664427 progress 80 % (41 MB)
69 00:39:49.678340 progress 85 % (44 MB)
70 00:39:49.692328 progress 90 % (47 MB)
71 00:39:49.707306 progress 95 % (49 MB)
72 00:39:49.722013 progress 100 % (52 MB)
73 00:39:49.722277 52 MB downloaded in 0.32 s (162.36 MB/s)
74 00:39:49.722437 end: 1.2.1 http-download (duration 00:00:00) [common]
76 00:39:49.722658 end: 1.2 download-retry (duration 00:00:00) [common]
77 00:39:49.722779 start: 1.3 download-retry (timeout 00:09:59) [common]
78 00:39:49.722886 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 00:39:49.723033 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-24-g0315de64ea248/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 00:39:49.723130 saving as /var/lib/lava/dispatcher/tmp/14368365/tftp-deploy-tu_dj_f6/dtb/mt8192-asurada-spherion-r0.dtb
81 00:39:49.723190 total size: 47258 (0 MB)
82 00:39:49.723246 No compression specified
83 00:39:49.724314 progress 69 % (0 MB)
84 00:39:49.724580 progress 100 % (0 MB)
85 00:39:49.724729 0 MB downloaded in 0.00 s (29.32 MB/s)
86 00:39:49.724846 end: 1.3.1 http-download (duration 00:00:00) [common]
88 00:39:49.725054 end: 1.3 download-retry (duration 00:00:00) [common]
89 00:39:49.725132 start: 1.4 download-retry (timeout 00:09:59) [common]
90 00:39:49.725210 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 00:39:49.725321 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-24-g0315de64ea248/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 00:39:49.725385 saving as /var/lib/lava/dispatcher/tmp/14368365/tftp-deploy-tu_dj_f6/modules/modules.tar
93 00:39:49.725440 total size: 8608736 (8 MB)
94 00:39:49.725495 Using unxz to decompress xz
95 00:39:49.727072 progress 0 % (0 MB)
96 00:39:49.746776 progress 5 % (0 MB)
97 00:39:49.774952 progress 10 % (0 MB)
98 00:39:49.804190 progress 15 % (1 MB)
99 00:39:49.829093 progress 20 % (1 MB)
100 00:39:49.853940 progress 25 % (2 MB)
101 00:39:49.878720 progress 30 % (2 MB)
102 00:39:49.904307 progress 35 % (2 MB)
103 00:39:49.932534 progress 40 % (3 MB)
104 00:39:49.956620 progress 45 % (3 MB)
105 00:39:49.981981 progress 50 % (4 MB)
106 00:39:50.008288 progress 55 % (4 MB)
107 00:39:50.034272 progress 60 % (4 MB)
108 00:39:50.059415 progress 65 % (5 MB)
109 00:39:50.084415 progress 70 % (5 MB)
110 00:39:50.110574 progress 75 % (6 MB)
111 00:39:50.137561 progress 80 % (6 MB)
112 00:39:50.163715 progress 85 % (7 MB)
113 00:39:50.190072 progress 90 % (7 MB)
114 00:39:50.215739 progress 95 % (7 MB)
115 00:39:50.242061 progress 100 % (8 MB)
116 00:39:50.248016 8 MB downloaded in 0.52 s (15.71 MB/s)
117 00:39:50.248275 end: 1.4.1 http-download (duration 00:00:01) [common]
119 00:39:50.248616 end: 1.4 download-retry (duration 00:00:01) [common]
120 00:39:50.248735 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 00:39:50.248851 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 00:39:50.248970 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 00:39:50.249082 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 00:39:50.249310 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14368365/lava-overlay-lgpdkh6u
125 00:39:50.249485 makedir: /var/lib/lava/dispatcher/tmp/14368365/lava-overlay-lgpdkh6u/lava-14368365/bin
126 00:39:50.249643 makedir: /var/lib/lava/dispatcher/tmp/14368365/lava-overlay-lgpdkh6u/lava-14368365/tests
127 00:39:50.249774 makedir: /var/lib/lava/dispatcher/tmp/14368365/lava-overlay-lgpdkh6u/lava-14368365/results
128 00:39:50.249906 Creating /var/lib/lava/dispatcher/tmp/14368365/lava-overlay-lgpdkh6u/lava-14368365/bin/lava-add-keys
129 00:39:50.250082 Creating /var/lib/lava/dispatcher/tmp/14368365/lava-overlay-lgpdkh6u/lava-14368365/bin/lava-add-sources
130 00:39:50.250249 Creating /var/lib/lava/dispatcher/tmp/14368365/lava-overlay-lgpdkh6u/lava-14368365/bin/lava-background-process-start
131 00:39:50.250415 Creating /var/lib/lava/dispatcher/tmp/14368365/lava-overlay-lgpdkh6u/lava-14368365/bin/lava-background-process-stop
132 00:39:50.250588 Creating /var/lib/lava/dispatcher/tmp/14368365/lava-overlay-lgpdkh6u/lava-14368365/bin/lava-common-functions
133 00:39:50.250755 Creating /var/lib/lava/dispatcher/tmp/14368365/lava-overlay-lgpdkh6u/lava-14368365/bin/lava-echo-ipv4
134 00:39:50.250922 Creating /var/lib/lava/dispatcher/tmp/14368365/lava-overlay-lgpdkh6u/lava-14368365/bin/lava-install-packages
135 00:39:50.251084 Creating /var/lib/lava/dispatcher/tmp/14368365/lava-overlay-lgpdkh6u/lava-14368365/bin/lava-installed-packages
136 00:39:50.251287 Creating /var/lib/lava/dispatcher/tmp/14368365/lava-overlay-lgpdkh6u/lava-14368365/bin/lava-os-build
137 00:39:50.251456 Creating /var/lib/lava/dispatcher/tmp/14368365/lava-overlay-lgpdkh6u/lava-14368365/bin/lava-probe-channel
138 00:39:50.251621 Creating /var/lib/lava/dispatcher/tmp/14368365/lava-overlay-lgpdkh6u/lava-14368365/bin/lava-probe-ip
139 00:39:50.251794 Creating /var/lib/lava/dispatcher/tmp/14368365/lava-overlay-lgpdkh6u/lava-14368365/bin/lava-target-ip
140 00:39:50.251961 Creating /var/lib/lava/dispatcher/tmp/14368365/lava-overlay-lgpdkh6u/lava-14368365/bin/lava-target-mac
141 00:39:50.252133 Creating /var/lib/lava/dispatcher/tmp/14368365/lava-overlay-lgpdkh6u/lava-14368365/bin/lava-target-storage
142 00:39:50.252302 Creating /var/lib/lava/dispatcher/tmp/14368365/lava-overlay-lgpdkh6u/lava-14368365/bin/lava-test-case
143 00:39:50.252469 Creating /var/lib/lava/dispatcher/tmp/14368365/lava-overlay-lgpdkh6u/lava-14368365/bin/lava-test-event
144 00:39:50.252631 Creating /var/lib/lava/dispatcher/tmp/14368365/lava-overlay-lgpdkh6u/lava-14368365/bin/lava-test-feedback
145 00:39:50.252794 Creating /var/lib/lava/dispatcher/tmp/14368365/lava-overlay-lgpdkh6u/lava-14368365/bin/lava-test-raise
146 00:39:50.252956 Creating /var/lib/lava/dispatcher/tmp/14368365/lava-overlay-lgpdkh6u/lava-14368365/bin/lava-test-reference
147 00:39:50.253127 Creating /var/lib/lava/dispatcher/tmp/14368365/lava-overlay-lgpdkh6u/lava-14368365/bin/lava-test-runner
148 00:39:50.253291 Creating /var/lib/lava/dispatcher/tmp/14368365/lava-overlay-lgpdkh6u/lava-14368365/bin/lava-test-set
149 00:39:50.253456 Creating /var/lib/lava/dispatcher/tmp/14368365/lava-overlay-lgpdkh6u/lava-14368365/bin/lava-test-shell
150 00:39:50.253628 Updating /var/lib/lava/dispatcher/tmp/14368365/lava-overlay-lgpdkh6u/lava-14368365/bin/lava-install-packages (oe)
151 00:39:50.253826 Updating /var/lib/lava/dispatcher/tmp/14368365/lava-overlay-lgpdkh6u/lava-14368365/bin/lava-installed-packages (oe)
152 00:39:50.253995 Creating /var/lib/lava/dispatcher/tmp/14368365/lava-overlay-lgpdkh6u/lava-14368365/environment
153 00:39:50.254126 LAVA metadata
154 00:39:50.254224 - LAVA_JOB_ID=14368365
155 00:39:50.254321 - LAVA_DISPATCHER_IP=192.168.201.1
156 00:39:50.254461 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 00:39:50.254551 skipped lava-vland-overlay
158 00:39:50.254659 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 00:39:50.254770 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 00:39:50.254867 skipped lava-multinode-overlay
161 00:39:50.254973 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 00:39:50.255082 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 00:39:50.255186 Loading test definitions
164 00:39:50.255303 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 00:39:50.255403 Using /lava-14368365 at stage 0
166 00:39:50.255832 uuid=14368365_1.5.2.3.1 testdef=None
167 00:39:50.255959 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 00:39:50.256071 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 00:39:50.256733 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 00:39:50.257057 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 00:39:50.258004 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 00:39:50.258402 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 00:39:50.259257 runner path: /var/lib/lava/dispatcher/tmp/14368365/lava-overlay-lgpdkh6u/lava-14368365/0/tests/0_igt-kms-mediatek test_uuid 14368365_1.5.2.3.1
176 00:39:50.259462 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 00:39:50.259771 Creating lava-test-runner.conf files
179 00:39:50.259869 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14368365/lava-overlay-lgpdkh6u/lava-14368365/0 for stage 0
180 00:39:50.259987 - 0_igt-kms-mediatek
181 00:39:50.260123 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 00:39:50.260250 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 00:39:50.269248 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 00:39:50.269416 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 00:39:50.269537 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 00:39:50.269663 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 00:39:50.269777 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 00:39:52.074315 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:02) [common]
189 00:39:52.074450 start: 1.5.4 extract-modules (timeout 00:09:57) [common]
190 00:39:52.074532 extracting modules file /var/lib/lava/dispatcher/tmp/14368365/tftp-deploy-tu_dj_f6/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14368365/extract-overlay-ramdisk-i7908pji/ramdisk
191 00:39:52.312637 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 00:39:52.312780 start: 1.5.5 apply-overlay-tftp (timeout 00:09:57) [common]
193 00:39:52.312865 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14368365/compress-overlay-lphpfcfp/overlay-1.5.2.4.tar.gz to ramdisk
194 00:39:52.312927 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14368365/compress-overlay-lphpfcfp/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14368365/extract-overlay-ramdisk-i7908pji/ramdisk
195 00:39:52.320394 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 00:39:52.320624 start: 1.5.6 configure-preseed-file (timeout 00:09:57) [common]
197 00:39:52.320754 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 00:39:52.320861 start: 1.5.7 compress-ramdisk (timeout 00:09:57) [common]
199 00:39:52.320956 Building ramdisk /var/lib/lava/dispatcher/tmp/14368365/extract-overlay-ramdisk-i7908pji/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14368365/extract-overlay-ramdisk-i7908pji/ramdisk
200 00:39:53.514809 >> 465988 blocks
201 00:40:00.167541 rename /var/lib/lava/dispatcher/tmp/14368365/extract-overlay-ramdisk-i7908pji/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14368365/tftp-deploy-tu_dj_f6/ramdisk/ramdisk.cpio.gz
202 00:40:00.167774 end: 1.5.7 compress-ramdisk (duration 00:00:08) [common]
203 00:40:00.167911 start: 1.5.8 prepare-kernel (timeout 00:09:49) [common]
204 00:40:00.168027 start: 1.5.8.1 prepare-fit (timeout 00:09:49) [common]
205 00:40:00.168142 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14368365/tftp-deploy-tu_dj_f6/kernel/Image']
206 00:40:15.238019 Returned 0 in 15 seconds
207 00:40:15.338550 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14368365/tftp-deploy-tu_dj_f6/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14368365/tftp-deploy-tu_dj_f6/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14368365/tftp-deploy-tu_dj_f6/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14368365/tftp-deploy-tu_dj_f6/kernel/image.itb
208 00:40:16.278019 output: FIT description: Kernel Image image with one or more FDT blobs
209 00:40:16.278157 output: Created: Sun Jun 16 01:40:16 2024
210 00:40:16.278222 output: Image 0 (kernel-1)
211 00:40:16.278277 output: Description:
212 00:40:16.278335 output: Created: Sun Jun 16 01:40:16 2024
213 00:40:16.278387 output: Type: Kernel Image
214 00:40:16.278436 output: Compression: lzma compressed
215 00:40:16.278491 output: Data Size: 13126376 Bytes = 12818.73 KiB = 12.52 MiB
216 00:40:16.278540 output: Architecture: AArch64
217 00:40:16.278590 output: OS: Linux
218 00:40:16.278639 output: Load Address: 0x00000000
219 00:40:16.278693 output: Entry Point: 0x00000000
220 00:40:16.278741 output: Hash algo: crc32
221 00:40:16.278790 output: Hash value: c791a20a
222 00:40:16.278843 output: Image 1 (fdt-1)
223 00:40:16.278894 output: Description: mt8192-asurada-spherion-r0
224 00:40:16.278949 output: Created: Sun Jun 16 01:40:16 2024
225 00:40:16.279004 output: Type: Flat Device Tree
226 00:40:16.279058 output: Compression: uncompressed
227 00:40:16.279112 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
228 00:40:16.279167 output: Architecture: AArch64
229 00:40:16.279220 output: Hash algo: crc32
230 00:40:16.279271 output: Hash value: 0f8e4d2e
231 00:40:16.279318 output: Image 2 (ramdisk-1)
232 00:40:16.279366 output: Description: unavailable
233 00:40:16.279413 output: Created: Sun Jun 16 01:40:16 2024
234 00:40:16.279461 output: Type: RAMDisk Image
235 00:40:16.279507 output: Compression: uncompressed
236 00:40:16.279554 output: Data Size: 61008144 Bytes = 59578.27 KiB = 58.18 MiB
237 00:40:16.279635 output: Architecture: AArch64
238 00:40:16.279712 output: OS: Linux
239 00:40:16.279763 output: Load Address: unavailable
240 00:40:16.279811 output: Entry Point: unavailable
241 00:40:16.279860 output: Hash algo: crc32
242 00:40:16.279908 output: Hash value: 05e3694d
243 00:40:16.279955 output: Default Configuration: 'conf-1'
244 00:40:16.280003 output: Configuration 0 (conf-1)
245 00:40:16.280050 output: Description: mt8192-asurada-spherion-r0
246 00:40:16.280098 output: Kernel: kernel-1
247 00:40:16.280145 output: Init Ramdisk: ramdisk-1
248 00:40:16.280193 output: FDT: fdt-1
249 00:40:16.280242 output: Loadables: kernel-1
250 00:40:16.280290 output:
251 00:40:16.280425 end: 1.5.8.1 prepare-fit (duration 00:00:16) [common]
252 00:40:16.280509 end: 1.5.8 prepare-kernel (duration 00:00:16) [common]
253 00:40:16.280602 end: 1.5 prepare-tftp-overlay (duration 00:00:26) [common]
254 00:40:16.280690 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:33) [common]
255 00:40:16.280775 No LXC device requested
256 00:40:16.280888 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 00:40:16.281020 start: 1.7 deploy-device-env (timeout 00:09:33) [common]
258 00:40:16.281092 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 00:40:16.281154 Checking files for TFTP limit of 4294967296 bytes.
260 00:40:16.281639 end: 1 tftp-deploy (duration 00:00:27) [common]
261 00:40:16.281738 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 00:40:16.281821 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 00:40:16.281925 substitutions:
264 00:40:16.281985 - {DTB}: 14368365/tftp-deploy-tu_dj_f6/dtb/mt8192-asurada-spherion-r0.dtb
265 00:40:16.282042 - {INITRD}: 14368365/tftp-deploy-tu_dj_f6/ramdisk/ramdisk.cpio.gz
266 00:40:16.282153 - {KERNEL}: 14368365/tftp-deploy-tu_dj_f6/kernel/Image
267 00:40:16.282207 - {LAVA_MAC}: None
268 00:40:16.282258 - {PRESEED_CONFIG}: None
269 00:40:16.282308 - {PRESEED_LOCAL}: None
270 00:40:16.282357 - {RAMDISK}: 14368365/tftp-deploy-tu_dj_f6/ramdisk/ramdisk.cpio.gz
271 00:40:16.282414 - {ROOT_PART}: None
272 00:40:16.282464 - {ROOT}: None
273 00:40:16.282512 - {SERVER_IP}: 192.168.201.1
274 00:40:16.282559 - {TEE}: None
275 00:40:16.282607 Parsed boot commands:
276 00:40:16.282655 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 00:40:16.282805 Parsed boot commands: tftpboot 192.168.201.1 14368365/tftp-deploy-tu_dj_f6/kernel/image.itb 14368365/tftp-deploy-tu_dj_f6/kernel/cmdline
278 00:40:16.282886 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 00:40:16.282962 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 00:40:16.283043 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 00:40:16.283118 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 00:40:16.283179 Not connected, no need to disconnect.
283 00:40:16.283244 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 00:40:16.283313 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 00:40:16.283387 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-0'
286 00:40:16.286780 Setting prompt string to ['lava-test: # ']
287 00:40:16.287104 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 00:40:16.287202 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 00:40:16.287310 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 00:40:16.287392 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 00:40:16.287574 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-0', '--port=1', '--command=reboot']
292 00:40:25.468082 >> Command sent successfully.
293 00:40:25.481307 Returned 0 in 9 seconds
294 00:40:25.582495 end: 2.2.2.1 pdu-reboot (duration 00:00:09) [common]
296 00:40:25.583660 end: 2.2.2 reset-device (duration 00:00:09) [common]
297 00:40:25.584144 start: 2.2.3 depthcharge-start (timeout 00:04:51) [common]
298 00:40:25.584568 Setting prompt string to 'Starting depthcharge on Spherion...'
299 00:40:25.584898 Changing prompt to 'Starting depthcharge on Spherion...'
300 00:40:25.585237 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 00:40:25.586872 [Enter `^Ec?' for help]
302 00:40:26.788129
303 00:40:26.788744
304 00:40:26.789087 F0: 102B 0000
305 00:40:26.789404
306 00:40:26.789778 F3: 1001 0000 [0200]
307 00:40:26.790079
308 00:40:26.791941 F3: 1001 0000
309 00:40:26.792410
310 00:40:26.792891 F7: 102D 0000
311 00:40:26.793188
312 00:40:26.793462 F1: 0000 0000
313 00:40:26.795995
314 00:40:26.796534 V0: 0000 0000 [0001]
315 00:40:26.796973
316 00:40:26.797258 00: 0007 8000
317 00:40:26.797532
318 00:40:26.799503 01: 0000 0000
319 00:40:26.799891
320 00:40:26.800186 BP: 0C00 0209 [0000]
321 00:40:26.800552
322 00:40:26.800822 G0: 1182 0000
323 00:40:26.801082
324 00:40:26.803104 EC: 0000 0021 [4000]
325 00:40:26.803484
326 00:40:26.803782 S7: 0000 0000 [0000]
327 00:40:26.806922
328 00:40:26.807302 CC: 0000 0000 [0001]
329 00:40:26.807598
330 00:40:26.810198 T0: 0000 0040 [010F]
331 00:40:26.810602
332 00:40:26.810905 Jump to BL
333 00:40:26.811178
334 00:40:26.835265
335 00:40:26.835792
336 00:40:26.841409 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
337 00:40:26.844972 ARM64: Exception handlers installed.
338 00:40:26.849029 ARM64: Testing exception
339 00:40:26.852880 ARM64: Done test exception
340 00:40:26.860913 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
341 00:40:26.867661 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
342 00:40:26.875253 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
343 00:40:26.886210 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
344 00:40:26.893727 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
345 00:40:26.901138 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
346 00:40:26.911111 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
347 00:40:26.917632 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
348 00:40:26.937485 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
349 00:40:26.940869 WDT: Last reset was cold boot
350 00:40:26.944910 SPI1(PAD0) initialized at 2873684 Hz
351 00:40:26.948850 SPI5(PAD0) initialized at 992727 Hz
352 00:40:26.952817 VBOOT: Loading verstage.
353 00:40:26.956146 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
354 00:40:26.959863 FMAP: Found "FLASH" version 1.1 at 0x20000.
355 00:40:26.963614 FMAP: base = 0x0 size = 0x800000 #areas = 25
356 00:40:26.967180 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
357 00:40:26.976244 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
358 00:40:26.982943 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
359 00:40:26.992859 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
360 00:40:26.993448
361 00:40:26.993835
362 00:40:27.002903 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
363 00:40:27.006017 ARM64: Exception handlers installed.
364 00:40:27.009299 ARM64: Testing exception
365 00:40:27.009773 ARM64: Done test exception
366 00:40:27.016212 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
367 00:40:27.019225 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
368 00:40:27.033534 Probing TPM: . done!
369 00:40:27.034068 TPM ready after 0 ms
370 00:40:27.040959 Connected to device vid:did:rid of 1ae0:0028:00
371 00:40:27.050448 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
372 00:40:27.088193 Initialized TPM device CR50 revision 0
373 00:40:27.100539 tlcl_send_startup: Startup return code is 0
374 00:40:27.101084 TPM: setup succeeded
375 00:40:27.111845 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
376 00:40:27.120576 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
377 00:40:27.131234 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
378 00:40:27.140043 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
379 00:40:27.143086 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
380 00:40:27.146135 in-header: 03 07 00 00 08 00 00 00
381 00:40:27.149600 in-data: aa e4 47 04 13 02 00 00
382 00:40:27.152762 Chrome EC: UHEPI supported
383 00:40:27.159862 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
384 00:40:27.162807 in-header: 03 a9 00 00 08 00 00 00
385 00:40:27.166093 in-data: 84 60 60 08 00 00 00 00
386 00:40:27.166479 Phase 1
387 00:40:27.169268 FMAP: area GBB found @ 3f5000 (12032 bytes)
388 00:40:27.176194 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
389 00:40:27.182786 VB2:vb2_check_recovery() Recovery was requested manually
390 00:40:27.186069 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x7
391 00:40:27.189445 Recovery requested (1009000e)
392 00:40:27.197770 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 00:40:27.203455 tlcl_extend: response is 0
394 00:40:27.211524 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 00:40:27.217138 tlcl_extend: response is 0
396 00:40:27.223561 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 00:40:27.244288 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
398 00:40:27.250891 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 00:40:27.251317
400 00:40:27.251644
401 00:40:27.260625 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 00:40:27.264616 ARM64: Exception handlers installed.
403 00:40:27.267945 ARM64: Testing exception
404 00:40:27.268606 ARM64: Done test exception
405 00:40:27.289689 pmic_efuse_setting: Set efuses in 11 msecs
406 00:40:27.293088 pmwrap_interface_init: Select PMIF_VLD_RDY
407 00:40:27.299926 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 00:40:27.303121 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 00:40:27.310112 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 00:40:27.313123 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 00:40:27.319970 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 00:40:27.323207 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 00:40:27.326669 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 00:40:27.333285 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 00:40:27.336450 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 00:40:27.343021 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 00:40:27.346333 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 00:40:27.349609 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 00:40:27.356251 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 00:40:27.363213 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 00:40:27.366277 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 00:40:27.372849 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 00:40:27.379912 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 00:40:27.383414 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 00:40:27.389868 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 00:40:27.397173 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 00:40:27.400621 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 00:40:27.406931 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 00:40:27.413079 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 00:40:27.416995 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 00:40:27.423675 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 00:40:27.430148 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 00:40:27.433268 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 00:40:27.440252 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 00:40:27.444024 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 00:40:27.446672 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 00:40:27.453438 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 00:40:27.460513 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 00:40:27.463725 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 00:40:27.470189 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 00:40:27.473874 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 00:40:27.480243 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 00:40:27.483524 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 00:40:27.490760 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 00:40:27.494759 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 00:40:27.497879 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 00:40:27.501363 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 00:40:27.507842 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 00:40:27.511108 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 00:40:27.514403 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 00:40:27.518079 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 00:40:27.525659 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 00:40:27.528802 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 00:40:27.532915 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 00:40:27.536653 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 00:40:27.540477 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 00:40:27.543703 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 00:40:27.553921 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 00:40:27.560700 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 00:40:27.564012 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 00:40:27.574073 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 00:40:27.580951 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 00:40:27.587624 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 00:40:27.590626 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 00:40:27.594311 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 00:40:27.602421 [RTC]rtc_enable_dcxo,68: con=0x406, osc32con=0xde70, sec=0x25
467 00:40:27.609333 [RTC]rtc_check_state,173: con=406, pwrkey1=a357, pwrkey2=67d2
468 00:40:27.612821 [RTC]rtc_osc_init,62: osc32con val = 0xde70
469 00:40:27.615921 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 00:40:27.627325 [RTC]rtc_get_frequency_meter,154: input=15, output=760
471 00:40:27.636929 [RTC]rtc_get_frequency_meter,154: input=23, output=942
472 00:40:27.646530 [RTC]rtc_get_frequency_meter,154: input=19, output=849
473 00:40:27.655665 [RTC]rtc_get_frequency_meter,154: input=17, output=805
474 00:40:27.665417 [RTC]rtc_get_frequency_meter,154: input=16, output=782
475 00:40:27.674606 [RTC]rtc_get_frequency_meter,154: input=16, output=783
476 00:40:27.684802 [RTC]rtc_get_frequency_meter,154: input=17, output=805
477 00:40:27.687773 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
478 00:40:27.694543 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
479 00:40:27.697900 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
480 00:40:27.701457 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
481 00:40:27.708251 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
482 00:40:27.711277 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
483 00:40:27.714592 ADC[4]: Raw value=905465 ID=7
484 00:40:27.715018 ADC[3]: Raw value=213441 ID=1
485 00:40:27.717846 RAM Code: 0x71
486 00:40:27.721118 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
487 00:40:27.727869 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
488 00:40:27.734498 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
489 00:40:27.741302 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
490 00:40:27.744660 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
491 00:40:27.749867 in-header: 03 07 00 00 08 00 00 00
492 00:40:27.751556 in-data: aa e4 47 04 13 02 00 00
493 00:40:27.755003 Chrome EC: UHEPI supported
494 00:40:27.761715 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
495 00:40:27.765000 in-header: 03 a9 00 00 08 00 00 00
496 00:40:27.768292 in-data: 84 60 60 08 00 00 00 00
497 00:40:27.771333 MRC: failed to locate region type 0.
498 00:40:27.777989 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
499 00:40:27.781479 DRAM-K: Running full calibration
500 00:40:27.788548 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
501 00:40:27.788939 header.status = 0x0
502 00:40:27.791305 header.version = 0x6 (expected: 0x6)
503 00:40:27.794703 header.size = 0xd00 (expected: 0xd00)
504 00:40:27.798114 header.flags = 0x0
505 00:40:27.804704 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
506 00:40:27.821462 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
507 00:40:27.828639 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
508 00:40:27.831889 dram_init: ddr_geometry: 2
509 00:40:27.832276 [EMI] MDL number = 2
510 00:40:27.834964 [EMI] Get MDL freq = 0
511 00:40:27.838662 dram_init: ddr_type: 0
512 00:40:27.839085 is_discrete_lpddr4: 1
513 00:40:27.841477 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
514 00:40:27.841886
515 00:40:27.842243
516 00:40:27.844834 [Bian_co] ETT version 0.0.0.1
517 00:40:27.851819 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
518 00:40:27.852212
519 00:40:27.855395 dramc_set_vcore_voltage set vcore to 650000
520 00:40:27.855786 Read voltage for 800, 4
521 00:40:27.858894 Vio18 = 0
522 00:40:27.859284 Vcore = 650000
523 00:40:27.859586 Vdram = 0
524 00:40:27.861685 Vddq = 0
525 00:40:27.862075 Vmddr = 0
526 00:40:27.865087 dram_init: config_dvfs: 1
527 00:40:27.868546 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
528 00:40:27.875350 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
529 00:40:27.878772 [SwImpedanceCal] DRVP=10, DRVN=16, ODTN=9
530 00:40:27.882173 freq_region=0, Reg: DRVP=10, DRVN=16, ODTN=9
531 00:40:27.885324 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
532 00:40:27.888866 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
533 00:40:27.892207 MEM_TYPE=3, freq_sel=18
534 00:40:27.895117 sv_algorithm_assistance_LP4_1600
535 00:40:27.898719 ============ PULL DRAM RESETB DOWN ============
536 00:40:27.901857 ========== PULL DRAM RESETB DOWN end =========
537 00:40:27.908711 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
538 00:40:27.911752 ===================================
539 00:40:27.912141 LPDDR4 DRAM CONFIGURATION
540 00:40:27.915616 ===================================
541 00:40:27.918634 EX_ROW_EN[0] = 0x0
542 00:40:27.922059 EX_ROW_EN[1] = 0x0
543 00:40:27.922451 LP4Y_EN = 0x0
544 00:40:27.925631 WORK_FSP = 0x0
545 00:40:27.926202 WL = 0x2
546 00:40:27.928831 RL = 0x2
547 00:40:27.929233 BL = 0x2
548 00:40:27.932188 RPST = 0x0
549 00:40:27.932628 RD_PRE = 0x0
550 00:40:27.935292 WR_PRE = 0x1
551 00:40:27.935844 WR_PST = 0x0
552 00:40:27.938675 DBI_WR = 0x0
553 00:40:27.939123 DBI_RD = 0x0
554 00:40:27.941646 OTF = 0x1
555 00:40:27.945428 ===================================
556 00:40:27.948711 ===================================
557 00:40:27.949100 ANA top config
558 00:40:27.952022 ===================================
559 00:40:27.955740 DLL_ASYNC_EN = 0
560 00:40:27.958751 ALL_SLAVE_EN = 1
561 00:40:27.959140 NEW_RANK_MODE = 1
562 00:40:27.962450 DLL_IDLE_MODE = 1
563 00:40:27.965831 LP45_APHY_COMB_EN = 1
564 00:40:27.969402 TX_ODT_DIS = 1
565 00:40:27.972154 NEW_8X_MODE = 1
566 00:40:27.972617 ===================================
567 00:40:27.975547 ===================================
568 00:40:27.978939 data_rate = 1600
569 00:40:27.982110 CKR = 1
570 00:40:27.985713 DQ_P2S_RATIO = 8
571 00:40:27.988929 ===================================
572 00:40:27.992332 CA_P2S_RATIO = 8
573 00:40:27.995756 DQ_CA_OPEN = 0
574 00:40:27.999072 DQ_SEMI_OPEN = 0
575 00:40:27.999463 CA_SEMI_OPEN = 0
576 00:40:28.002293 CA_FULL_RATE = 0
577 00:40:28.005434 DQ_CKDIV4_EN = 1
578 00:40:28.009023 CA_CKDIV4_EN = 1
579 00:40:28.012702 CA_PREDIV_EN = 0
580 00:40:28.013093 PH8_DLY = 0
581 00:40:28.015791 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
582 00:40:28.018998 DQ_AAMCK_DIV = 4
583 00:40:28.023035 CA_AAMCK_DIV = 4
584 00:40:28.025827 CA_ADMCK_DIV = 4
585 00:40:28.029160 DQ_TRACK_CA_EN = 0
586 00:40:28.029824 CA_PICK = 800
587 00:40:28.032292 CA_MCKIO = 800
588 00:40:28.036096 MCKIO_SEMI = 0
589 00:40:28.038799 PLL_FREQ = 3068
590 00:40:28.042223 DQ_UI_PI_RATIO = 32
591 00:40:28.046226 CA_UI_PI_RATIO = 0
592 00:40:28.049423 ===================================
593 00:40:28.052608 ===================================
594 00:40:28.053119 memory_type:LPDDR4
595 00:40:28.055964 GP_NUM : 10
596 00:40:28.059510 SRAM_EN : 1
597 00:40:28.059968 MD32_EN : 0
598 00:40:28.062298 ===================================
599 00:40:28.066253 [ANA_INIT] >>>>>>>>>>>>>>
600 00:40:28.069632 <<<<<< [CONFIGURE PHASE]: ANA_TX
601 00:40:28.073041 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
602 00:40:28.076210 ===================================
603 00:40:28.079494 data_rate = 1600,PCW = 0X7600
604 00:40:28.082807 ===================================
605 00:40:28.086041 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
606 00:40:28.089506 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 00:40:28.096188 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
608 00:40:28.099541 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
609 00:40:28.103020 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
610 00:40:28.106364 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
611 00:40:28.109873 [ANA_INIT] flow start
612 00:40:28.113248 [ANA_INIT] PLL >>>>>>>>
613 00:40:28.113719 [ANA_INIT] PLL <<<<<<<<
614 00:40:28.116520 [ANA_INIT] MIDPI >>>>>>>>
615 00:40:28.119497 [ANA_INIT] MIDPI <<<<<<<<
616 00:40:28.120016 [ANA_INIT] DLL >>>>>>>>
617 00:40:28.123241 [ANA_INIT] flow end
618 00:40:28.126150 ============ LP4 DIFF to SE enter ============
619 00:40:28.129268 ============ LP4 DIFF to SE exit ============
620 00:40:28.133285 [ANA_INIT] <<<<<<<<<<<<<
621 00:40:28.136734 [Flow] Enable top DCM control >>>>>
622 00:40:28.139977 [Flow] Enable top DCM control <<<<<
623 00:40:28.143415 Enable DLL master slave shuffle
624 00:40:28.149708 ==============================================================
625 00:40:28.150142 Gating Mode config
626 00:40:28.156501 ==============================================================
627 00:40:28.156990 Config description:
628 00:40:28.166319 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
629 00:40:28.173280 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
630 00:40:28.179820 SELPH_MODE 0: By rank 1: By Phase
631 00:40:28.183548 ==============================================================
632 00:40:28.187010 GAT_TRACK_EN = 1
633 00:40:28.190781 RX_GATING_MODE = 2
634 00:40:28.194027 RX_GATING_TRACK_MODE = 2
635 00:40:28.198336 SELPH_MODE = 1
636 00:40:28.198747 PICG_EARLY_EN = 1
637 00:40:28.202295 VALID_LAT_VALUE = 1
638 00:40:28.209263 ==============================================================
639 00:40:28.213355 Enter into Gating configuration >>>>
640 00:40:28.213781 Exit from Gating configuration <<<<
641 00:40:28.216849 Enter into DVFS_PRE_config >>>>>
642 00:40:28.227496 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
643 00:40:28.231310 Exit from DVFS_PRE_config <<<<<
644 00:40:28.234485 Enter into PICG configuration >>>>
645 00:40:28.237711 Exit from PICG configuration <<<<
646 00:40:28.241056 [RX_INPUT] configuration >>>>>
647 00:40:28.244198 [RX_INPUT] configuration <<<<<
648 00:40:28.247662 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
649 00:40:28.254099 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
650 00:40:28.260808 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
651 00:40:28.267519 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
652 00:40:28.274440 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
653 00:40:28.277443 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
654 00:40:28.284513 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
655 00:40:28.287915 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
656 00:40:28.291195 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
657 00:40:28.294269 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
658 00:40:28.297398 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
659 00:40:28.304380 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
660 00:40:28.307699 ===================================
661 00:40:28.310909 LPDDR4 DRAM CONFIGURATION
662 00:40:28.311491 ===================================
663 00:40:28.314356 EX_ROW_EN[0] = 0x0
664 00:40:28.317802 EX_ROW_EN[1] = 0x0
665 00:40:28.318189 LP4Y_EN = 0x0
666 00:40:28.321247 WORK_FSP = 0x0
667 00:40:28.321702 WL = 0x2
668 00:40:28.324689 RL = 0x2
669 00:40:28.325120 BL = 0x2
670 00:40:28.327960 RPST = 0x0
671 00:40:28.328347 RD_PRE = 0x0
672 00:40:28.331074 WR_PRE = 0x1
673 00:40:28.331466 WR_PST = 0x0
674 00:40:28.334383 DBI_WR = 0x0
675 00:40:28.334785 DBI_RD = 0x0
676 00:40:28.337668 OTF = 0x1
677 00:40:28.341448 ===================================
678 00:40:28.344810 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
679 00:40:28.348168 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
680 00:40:28.354307 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
681 00:40:28.357619 ===================================
682 00:40:28.358049 LPDDR4 DRAM CONFIGURATION
683 00:40:28.361794 ===================================
684 00:40:28.364783 EX_ROW_EN[0] = 0x10
685 00:40:28.365225 EX_ROW_EN[1] = 0x0
686 00:40:28.368481 LP4Y_EN = 0x0
687 00:40:28.371430 WORK_FSP = 0x0
688 00:40:28.371934 WL = 0x2
689 00:40:28.374364 RL = 0x2
690 00:40:28.374791 BL = 0x2
691 00:40:28.377900 RPST = 0x0
692 00:40:28.378324 RD_PRE = 0x0
693 00:40:28.380933 WR_PRE = 0x1
694 00:40:28.381359 WR_PST = 0x0
695 00:40:28.384775 DBI_WR = 0x0
696 00:40:28.385227 DBI_RD = 0x0
697 00:40:28.387954 OTF = 0x1
698 00:40:28.391285 ===================================
699 00:40:28.398057 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
700 00:40:28.401284 nWR fixed to 40
701 00:40:28.401744 [ModeRegInit_LP4] CH0 RK0
702 00:40:28.404541 [ModeRegInit_LP4] CH0 RK1
703 00:40:28.407705 [ModeRegInit_LP4] CH1 RK0
704 00:40:28.408092 [ModeRegInit_LP4] CH1 RK1
705 00:40:28.410872 match AC timing 13
706 00:40:28.413824 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
707 00:40:28.420664 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
708 00:40:28.424289 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
709 00:40:28.427383 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
710 00:40:28.434166 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
711 00:40:28.434555 [EMI DOE] emi_dcm 0
712 00:40:28.437905 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
713 00:40:28.441407 ==
714 00:40:28.444409 Dram Type= 6, Freq= 0, CH_0, rank 0
715 00:40:28.447488 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
716 00:40:28.447877 ==
717 00:40:28.451141 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
718 00:40:28.457465 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
719 00:40:28.467733 [CA 0] Center 36 (6~67) winsize 62
720 00:40:28.470751 [CA 1] Center 36 (6~67) winsize 62
721 00:40:28.474207 [CA 2] Center 34 (4~65) winsize 62
722 00:40:28.477934 [CA 3] Center 33 (3~64) winsize 62
723 00:40:28.480980 [CA 4] Center 33 (3~63) winsize 61
724 00:40:28.484260 [CA 5] Center 32 (3~62) winsize 60
725 00:40:28.484694
726 00:40:28.487906 [CmdBusTrainingLP45] Vref(ca) range 1: 34
727 00:40:28.488312
728 00:40:28.491338 [CATrainingPosCal] consider 1 rank data
729 00:40:28.494743 u2DelayCellTimex100 = 270/100 ps
730 00:40:28.497910 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
731 00:40:28.501239 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
732 00:40:28.504243 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
733 00:40:28.510913 CA3 delay=33 (3~64),Diff = 1 PI (7 cell)
734 00:40:28.514270 CA4 delay=33 (3~63),Diff = 1 PI (7 cell)
735 00:40:28.518214 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
736 00:40:28.518629
737 00:40:28.521513 CA PerBit enable=1, Macro0, CA PI delay=32
738 00:40:28.521957
739 00:40:28.524802 [CBTSetCACLKResult] CA Dly = 32
740 00:40:28.525183 CS Dly: 4 (0~35)
741 00:40:28.525481 ==
742 00:40:28.527810 Dram Type= 6, Freq= 0, CH_0, rank 1
743 00:40:28.534365 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
744 00:40:28.534911 ==
745 00:40:28.537652 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
746 00:40:28.544186 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
747 00:40:28.554018 [CA 0] Center 36 (6~67) winsize 62
748 00:40:28.557320 [CA 1] Center 36 (6~67) winsize 62
749 00:40:28.560466 [CA 2] Center 34 (4~65) winsize 62
750 00:40:28.563873 [CA 3] Center 33 (3~64) winsize 62
751 00:40:28.567523 [CA 4] Center 32 (2~63) winsize 62
752 00:40:28.570898 [CA 5] Center 32 (2~63) winsize 62
753 00:40:28.571355
754 00:40:28.573817 [CmdBusTrainingLP45] Vref(ca) range 1: 34
755 00:40:28.574208
756 00:40:28.577265 [CATrainingPosCal] consider 2 rank data
757 00:40:28.580865 u2DelayCellTimex100 = 270/100 ps
758 00:40:28.584007 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
759 00:40:28.587070 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
760 00:40:28.594154 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
761 00:40:28.597445 CA3 delay=33 (3~64),Diff = 1 PI (7 cell)
762 00:40:28.600813 CA4 delay=33 (3~63),Diff = 1 PI (7 cell)
763 00:40:28.603792 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
764 00:40:28.604340
765 00:40:28.607341 CA PerBit enable=1, Macro0, CA PI delay=32
766 00:40:28.607907
767 00:40:28.610712 [CBTSetCACLKResult] CA Dly = 32
768 00:40:28.611248 CS Dly: 4 (0~36)
769 00:40:28.611698
770 00:40:28.613579 ----->DramcWriteLeveling(PI) begin...
771 00:40:28.617224 ==
772 00:40:28.617663 Dram Type= 6, Freq= 0, CH_0, rank 0
773 00:40:28.624054 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
774 00:40:28.624442 ==
775 00:40:28.626960 Write leveling (Byte 0): 33 => 33
776 00:40:28.630653 Write leveling (Byte 1): 29 => 29
777 00:40:28.631037 DramcWriteLeveling(PI) end<-----
778 00:40:28.633999
779 00:40:28.634381 ==
780 00:40:28.637183 Dram Type= 6, Freq= 0, CH_0, rank 0
781 00:40:28.640958 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 00:40:28.641343 ==
783 00:40:28.643806 [Gating] SW mode calibration
784 00:40:28.650576 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
785 00:40:28.654053 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
786 00:40:28.660503 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
787 00:40:28.663832 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
788 00:40:28.667305 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
789 00:40:28.673860 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 00:40:28.677204 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 00:40:28.680591 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 00:40:28.687364 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 00:40:28.690886 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 00:40:28.694066 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 00:40:28.700792 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 00:40:28.703951 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 00:40:28.707209 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 00:40:28.710653 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 00:40:28.717684 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 00:40:28.720801 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 00:40:28.723749 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 00:40:28.731089 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 00:40:28.734230 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
804 00:40:28.737294 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 00:40:28.744068 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 00:40:28.747589 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 00:40:28.750578 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 00:40:28.757509 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 00:40:28.760613 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 00:40:28.764397 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 00:40:28.768148 0 9 4 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
812 00:40:28.774787 0 9 8 | B1->B0 | 2323 3434 | 1 1 | (1 1) (1 1)
813 00:40:28.778248 0 9 12 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
814 00:40:28.781445 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 00:40:28.788298 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 00:40:28.791643 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 00:40:28.794912 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 00:40:28.802250 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 00:40:28.804863 0 10 4 | B1->B0 | 3434 3232 | 1 1 | (1 1) (0 0)
820 00:40:28.808593 0 10 8 | B1->B0 | 3030 2525 | 0 0 | (0 0) (1 0)
821 00:40:28.811710 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
822 00:40:28.818290 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 00:40:28.821721 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 00:40:28.825411 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 00:40:28.831800 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 00:40:28.834904 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 00:40:28.838676 0 11 4 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
828 00:40:28.845216 0 11 8 | B1->B0 | 2c2c 3f3f | 0 0 | (0 0) (0 0)
829 00:40:28.848564 0 11 12 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
830 00:40:28.851456 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 00:40:28.858677 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 00:40:28.861415 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 00:40:28.865304 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 00:40:28.872019 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 00:40:28.874795 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
836 00:40:28.878235 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
837 00:40:28.885045 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 00:40:28.888664 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 00:40:28.891542 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 00:40:28.898995 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 00:40:28.902081 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 00:40:28.904739 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 00:40:28.908258 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 00:40:28.915012 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 00:40:28.918591 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 00:40:28.921753 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 00:40:28.928964 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 00:40:28.932059 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 00:40:28.934855 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 00:40:28.941492 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 00:40:28.944712 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
852 00:40:28.948341 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
853 00:40:28.951384 Total UI for P1: 0, mck2ui 16
854 00:40:28.955169 best dqsien dly found for B0: ( 0, 14, 4)
855 00:40:28.961719 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
856 00:40:28.962156 Total UI for P1: 0, mck2ui 16
857 00:40:28.967583 best dqsien dly found for B1: ( 0, 14, 10)
858 00:40:28.971324 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
859 00:40:28.975035 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
860 00:40:28.975450
861 00:40:28.978448 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
862 00:40:28.981722 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
863 00:40:28.984915 [Gating] SW calibration Done
864 00:40:28.985309 ==
865 00:40:28.987967 Dram Type= 6, Freq= 0, CH_0, rank 0
866 00:40:28.991730 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
867 00:40:28.992121 ==
868 00:40:28.995095 RX Vref Scan: 0
869 00:40:28.995481
870 00:40:28.995781 RX Vref 0 -> 0, step: 1
871 00:40:28.996061
872 00:40:28.998120 RX Delay -130 -> 252, step: 16
873 00:40:29.001239 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
874 00:40:29.008168 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
875 00:40:29.011705 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
876 00:40:29.015113 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
877 00:40:29.017897 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
878 00:40:29.021226 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
879 00:40:29.028280 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
880 00:40:29.031807 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
881 00:40:29.035178 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
882 00:40:29.038525 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
883 00:40:29.041977 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
884 00:40:29.048686 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
885 00:40:29.051827 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
886 00:40:29.055194 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
887 00:40:29.058401 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
888 00:40:29.061594 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
889 00:40:29.065677 ==
890 00:40:29.066112 Dram Type= 6, Freq= 0, CH_0, rank 0
891 00:40:29.071630 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
892 00:40:29.072017 ==
893 00:40:29.072315 DQS Delay:
894 00:40:29.075005 DQS0 = 0, DQS1 = 0
895 00:40:29.075389 DQM Delay:
896 00:40:29.078178 DQM0 = 89, DQM1 = 80
897 00:40:29.078562 DQ Delay:
898 00:40:29.081920 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85
899 00:40:29.084909 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =101
900 00:40:29.088448 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =77
901 00:40:29.092270 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =85
902 00:40:29.092740
903 00:40:29.093145
904 00:40:29.093608 ==
905 00:40:29.095084 Dram Type= 6, Freq= 0, CH_0, rank 0
906 00:40:29.098117 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
907 00:40:29.098504 ==
908 00:40:29.098800
909 00:40:29.099069
910 00:40:29.101654 TX Vref Scan disable
911 00:40:29.105332 == TX Byte 0 ==
912 00:40:29.108679 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
913 00:40:29.111722 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
914 00:40:29.114951 == TX Byte 1 ==
915 00:40:29.118575 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
916 00:40:29.122239 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
917 00:40:29.122672 ==
918 00:40:29.124896 Dram Type= 6, Freq= 0, CH_0, rank 0
919 00:40:29.128319 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
920 00:40:29.128721 ==
921 00:40:29.143527 TX Vref=22, minBit 8, minWin=27, winSum=447
922 00:40:29.146913 TX Vref=24, minBit 10, minWin=27, winSum=454
923 00:40:29.150394 TX Vref=26, minBit 10, minWin=27, winSum=456
924 00:40:29.153158 TX Vref=28, minBit 0, minWin=28, winSum=456
925 00:40:29.156419 TX Vref=30, minBit 5, minWin=28, winSum=458
926 00:40:29.160304 TX Vref=32, minBit 2, minWin=27, winSum=451
927 00:40:29.166961 [TxChooseVref] Worse bit 5, Min win 28, Win sum 458, Final Vref 30
928 00:40:29.167349
929 00:40:29.170050 Final TX Range 1 Vref 30
930 00:40:29.170439
931 00:40:29.170734 ==
932 00:40:29.173378 Dram Type= 6, Freq= 0, CH_0, rank 0
933 00:40:29.176864 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 00:40:29.177251 ==
935 00:40:29.177611
936 00:40:29.180498
937 00:40:29.180989 TX Vref Scan disable
938 00:40:29.183856 == TX Byte 0 ==
939 00:40:29.186908 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
940 00:40:29.193536 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
941 00:40:29.194102 == TX Byte 1 ==
942 00:40:29.196658 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
943 00:40:29.203214 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
944 00:40:29.203708
945 00:40:29.204018 [DATLAT]
946 00:40:29.204467 Freq=800, CH0 RK0
947 00:40:29.204955
948 00:40:29.206508 DATLAT Default: 0xa
949 00:40:29.206893 0, 0xFFFF, sum = 0
950 00:40:29.210069 1, 0xFFFF, sum = 0
951 00:40:29.210465 2, 0xFFFF, sum = 0
952 00:40:29.213628 3, 0xFFFF, sum = 0
953 00:40:29.214029 4, 0xFFFF, sum = 0
954 00:40:29.216725 5, 0xFFFF, sum = 0
955 00:40:29.220053 6, 0xFFFF, sum = 0
956 00:40:29.220584 7, 0xFFFF, sum = 0
957 00:40:29.223432 8, 0xFFFF, sum = 0
958 00:40:29.223944 9, 0x0, sum = 1
959 00:40:29.224414 10, 0x0, sum = 2
960 00:40:29.226455 11, 0x0, sum = 3
961 00:40:29.226853 12, 0x0, sum = 4
962 00:40:29.230043 best_step = 10
963 00:40:29.230543
964 00:40:29.230938 ==
965 00:40:29.233106 Dram Type= 6, Freq= 0, CH_0, rank 0
966 00:40:29.236624 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
967 00:40:29.237019 ==
968 00:40:29.239822 RX Vref Scan: 1
969 00:40:29.240287
970 00:40:29.240594 Set Vref Range= 32 -> 127
971 00:40:29.240877
972 00:40:29.243260 RX Vref 32 -> 127, step: 1
973 00:40:29.243736
974 00:40:29.246442 RX Delay -95 -> 252, step: 8
975 00:40:29.246835
976 00:40:29.249851 Set Vref, RX VrefLevel [Byte0]: 32
977 00:40:29.253185 [Byte1]: 32
978 00:40:29.253615
979 00:40:29.256890 Set Vref, RX VrefLevel [Byte0]: 33
980 00:40:29.260317 [Byte1]: 33
981 00:40:29.263943
982 00:40:29.264470 Set Vref, RX VrefLevel [Byte0]: 34
983 00:40:29.267178 [Byte1]: 34
984 00:40:29.271140
985 00:40:29.271525 Set Vref, RX VrefLevel [Byte0]: 35
986 00:40:29.274305 [Byte1]: 35
987 00:40:29.279216
988 00:40:29.279706 Set Vref, RX VrefLevel [Byte0]: 36
989 00:40:29.282232 [Byte1]: 36
990 00:40:29.286103
991 00:40:29.286490 Set Vref, RX VrefLevel [Byte0]: 37
992 00:40:29.290329 [Byte1]: 37
993 00:40:29.294189
994 00:40:29.294660 Set Vref, RX VrefLevel [Byte0]: 38
995 00:40:29.297500 [Byte1]: 38
996 00:40:29.301449
997 00:40:29.301919 Set Vref, RX VrefLevel [Byte0]: 39
998 00:40:29.304675 [Byte1]: 39
999 00:40:29.309609
1000 00:40:29.310123 Set Vref, RX VrefLevel [Byte0]: 40
1001 00:40:29.312863 [Byte1]: 40
1002 00:40:29.316665
1003 00:40:29.317095 Set Vref, RX VrefLevel [Byte0]: 41
1004 00:40:29.320078 [Byte1]: 41
1005 00:40:29.324345
1006 00:40:29.324984 Set Vref, RX VrefLevel [Byte0]: 42
1007 00:40:29.327450 [Byte1]: 42
1008 00:40:29.332162
1009 00:40:29.332665 Set Vref, RX VrefLevel [Byte0]: 43
1010 00:40:29.335733 [Byte1]: 43
1011 00:40:29.339838
1012 00:40:29.340267 Set Vref, RX VrefLevel [Byte0]: 44
1013 00:40:29.342773 [Byte1]: 44
1014 00:40:29.347141
1015 00:40:29.347532 Set Vref, RX VrefLevel [Byte0]: 45
1016 00:40:29.350691 [Byte1]: 45
1017 00:40:29.354746
1018 00:40:29.355256 Set Vref, RX VrefLevel [Byte0]: 46
1019 00:40:29.358408 [Byte1]: 46
1020 00:40:29.362390
1021 00:40:29.362780 Set Vref, RX VrefLevel [Byte0]: 47
1022 00:40:29.365711 [Byte1]: 47
1023 00:40:29.369826
1024 00:40:29.370214 Set Vref, RX VrefLevel [Byte0]: 48
1025 00:40:29.373643 [Byte1]: 48
1026 00:40:29.377520
1027 00:40:29.377935 Set Vref, RX VrefLevel [Byte0]: 49
1028 00:40:29.381077 [Byte1]: 49
1029 00:40:29.385455
1030 00:40:29.385878 Set Vref, RX VrefLevel [Byte0]: 50
1031 00:40:29.388664 [Byte1]: 50
1032 00:40:29.392862
1033 00:40:29.393246 Set Vref, RX VrefLevel [Byte0]: 51
1034 00:40:29.396274 [Byte1]: 51
1035 00:40:29.400639
1036 00:40:29.401098 Set Vref, RX VrefLevel [Byte0]: 52
1037 00:40:29.403724 [Byte1]: 52
1038 00:40:29.407740
1039 00:40:29.408124 Set Vref, RX VrefLevel [Byte0]: 53
1040 00:40:29.411965 [Byte1]: 53
1041 00:40:29.415560
1042 00:40:29.415969 Set Vref, RX VrefLevel [Byte0]: 54
1043 00:40:29.418709 [Byte1]: 54
1044 00:40:29.423119
1045 00:40:29.423589 Set Vref, RX VrefLevel [Byte0]: 55
1046 00:40:29.426291 [Byte1]: 55
1047 00:40:29.431186
1048 00:40:29.431638 Set Vref, RX VrefLevel [Byte0]: 56
1049 00:40:29.434356 [Byte1]: 56
1050 00:40:29.438145
1051 00:40:29.438534 Set Vref, RX VrefLevel [Byte0]: 57
1052 00:40:29.441644 [Byte1]: 57
1053 00:40:29.446132
1054 00:40:29.446562 Set Vref, RX VrefLevel [Byte0]: 58
1055 00:40:29.449075 [Byte1]: 58
1056 00:40:29.453431
1057 00:40:29.453975 Set Vref, RX VrefLevel [Byte0]: 59
1058 00:40:29.456925 [Byte1]: 59
1059 00:40:29.461242
1060 00:40:29.461727 Set Vref, RX VrefLevel [Byte0]: 60
1061 00:40:29.464258 [Byte1]: 60
1062 00:40:29.469025
1063 00:40:29.469407 Set Vref, RX VrefLevel [Byte0]: 61
1064 00:40:29.471933 [Byte1]: 61
1065 00:40:29.476565
1066 00:40:29.476950 Set Vref, RX VrefLevel [Byte0]: 62
1067 00:40:29.480013 [Byte1]: 62
1068 00:40:29.484201
1069 00:40:29.484617 Set Vref, RX VrefLevel [Byte0]: 63
1070 00:40:29.487454 [Byte1]: 63
1071 00:40:29.491576
1072 00:40:29.491975 Set Vref, RX VrefLevel [Byte0]: 64
1073 00:40:29.495227 [Byte1]: 64
1074 00:40:29.499300
1075 00:40:29.499697 Set Vref, RX VrefLevel [Byte0]: 65
1076 00:40:29.502622 [Byte1]: 65
1077 00:40:29.506758
1078 00:40:29.507158 Set Vref, RX VrefLevel [Byte0]: 66
1079 00:40:29.509954 [Byte1]: 66
1080 00:40:29.514655
1081 00:40:29.515104 Set Vref, RX VrefLevel [Byte0]: 67
1082 00:40:29.517943 [Byte1]: 67
1083 00:40:29.521886
1084 00:40:29.522357 Set Vref, RX VrefLevel [Byte0]: 68
1085 00:40:29.525042 [Byte1]: 68
1086 00:40:29.530127
1087 00:40:29.530616 Set Vref, RX VrefLevel [Byte0]: 69
1088 00:40:29.533621 [Byte1]: 69
1089 00:40:29.537360
1090 00:40:29.537803 Set Vref, RX VrefLevel [Byte0]: 70
1091 00:40:29.540239 [Byte1]: 70
1092 00:40:29.544898
1093 00:40:29.545384 Set Vref, RX VrefLevel [Byte0]: 71
1094 00:40:29.547912 [Byte1]: 71
1095 00:40:29.552557
1096 00:40:29.553007 Set Vref, RX VrefLevel [Byte0]: 72
1097 00:40:29.555758 [Byte1]: 72
1098 00:40:29.560659
1099 00:40:29.561166 Set Vref, RX VrefLevel [Byte0]: 73
1100 00:40:29.563608 [Byte1]: 73
1101 00:40:29.567904
1102 00:40:29.568323 Set Vref, RX VrefLevel [Byte0]: 74
1103 00:40:29.571018 [Byte1]: 74
1104 00:40:29.575503
1105 00:40:29.575914 Set Vref, RX VrefLevel [Byte0]: 75
1106 00:40:29.578608 [Byte1]: 75
1107 00:40:29.583081
1108 00:40:29.583479 Set Vref, RX VrefLevel [Byte0]: 76
1109 00:40:29.586255 [Byte1]: 76
1110 00:40:29.590262
1111 00:40:29.590674 Set Vref, RX VrefLevel [Byte0]: 77
1112 00:40:29.594265 [Byte1]: 77
1113 00:40:29.597781
1114 00:40:29.598181 Final RX Vref Byte 0 = 54 to rank0
1115 00:40:29.601223 Final RX Vref Byte 1 = 59 to rank0
1116 00:40:29.604552 Final RX Vref Byte 0 = 54 to rank1
1117 00:40:29.607908 Final RX Vref Byte 1 = 59 to rank1==
1118 00:40:29.611403 Dram Type= 6, Freq= 0, CH_0, rank 0
1119 00:40:29.617696 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1120 00:40:29.618101 ==
1121 00:40:29.618506 DQS Delay:
1122 00:40:29.618885 DQS0 = 0, DQS1 = 0
1123 00:40:29.621352 DQM Delay:
1124 00:40:29.621860 DQM0 = 91, DQM1 = 85
1125 00:40:29.624773 DQ Delay:
1126 00:40:29.627845 DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =88
1127 00:40:29.628248 DQ4 =92, DQ5 =80, DQ6 =100, DQ7 =100
1128 00:40:29.631278 DQ8 =72, DQ9 =76, DQ10 =84, DQ11 =76
1129 00:40:29.634591 DQ12 =92, DQ13 =92, DQ14 =96, DQ15 =92
1130 00:40:29.638016
1131 00:40:29.638465
1132 00:40:29.644661 [DQSOSCAuto] RK0, (LSB)MR18= 0x5247, (MSB)MR19= 0x606, tDQSOscB0 = 392 ps tDQSOscB1 = 389 ps
1133 00:40:29.648149 CH0 RK0: MR19=606, MR18=5247
1134 00:40:29.655090 CH0_RK0: MR19=0x606, MR18=0x5247, DQSOSC=389, MR23=63, INC=97, DEC=65
1135 00:40:29.655507
1136 00:40:29.658255 ----->DramcWriteLeveling(PI) begin...
1137 00:40:29.658662 ==
1138 00:40:29.661408 Dram Type= 6, Freq= 0, CH_0, rank 1
1139 00:40:29.664745 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1140 00:40:29.665140 ==
1141 00:40:29.668287 Write leveling (Byte 0): 31 => 31
1142 00:40:29.671588 Write leveling (Byte 1): 30 => 30
1143 00:40:29.675028 DramcWriteLeveling(PI) end<-----
1144 00:40:29.675420
1145 00:40:29.675849 ==
1146 00:40:29.678310 Dram Type= 6, Freq= 0, CH_0, rank 1
1147 00:40:29.681653 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1148 00:40:29.682203 ==
1149 00:40:29.685231 [Gating] SW mode calibration
1150 00:40:29.691976 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1151 00:40:29.698522 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1152 00:40:29.701652 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1153 00:40:29.704700 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1154 00:40:29.752355 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1155 00:40:29.752484 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1156 00:40:29.753071 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 00:40:29.753387 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 00:40:29.753487 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 00:40:29.753612 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 00:40:29.753721 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 00:40:29.753807 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 00:40:29.753919 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 00:40:29.754025 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 00:40:29.754094 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 00:40:29.768226 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 00:40:29.768632 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 00:40:29.771462 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 00:40:29.775114 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 00:40:29.775610 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 00:40:29.781768 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1171 00:40:29.785009 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 00:40:29.788328 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 00:40:29.794952 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 00:40:29.798150 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 00:40:29.801405 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 00:40:29.808320 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 00:40:29.811690 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 00:40:29.814876 0 9 8 | B1->B0 | 2e2e 2f2f | 0 1 | (0 0) (0 0)
1179 00:40:29.821395 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1180 00:40:29.825299 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1181 00:40:29.828538 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1182 00:40:29.831974 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1183 00:40:29.838468 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1184 00:40:29.841713 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1185 00:40:29.844935 0 10 4 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
1186 00:40:29.851849 0 10 8 | B1->B0 | 2424 2525 | 0 0 | (0 0) (1 0)
1187 00:40:29.855355 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 00:40:29.858754 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 00:40:29.864951 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 00:40:29.868249 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 00:40:29.872235 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 00:40:29.878577 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 00:40:29.881881 0 11 4 | B1->B0 | 2525 2323 | 0 1 | (0 0) (0 0)
1194 00:40:29.885301 0 11 8 | B1->B0 | 4040 4141 | 0 0 | (0 0) (0 0)
1195 00:40:29.892017 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1196 00:40:29.895483 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1197 00:40:29.898506 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1198 00:40:29.901709 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1199 00:40:29.908963 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1200 00:40:29.912285 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1201 00:40:29.915336 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1202 00:40:29.921588 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1203 00:40:29.924930 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 00:40:29.928433 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 00:40:29.935082 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 00:40:29.938259 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 00:40:29.942110 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 00:40:29.948759 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 00:40:29.951684 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 00:40:29.954890 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 00:40:29.962010 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 00:40:29.965357 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 00:40:29.968781 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 00:40:29.975278 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 00:40:29.978801 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 00:40:29.981369 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 00:40:29.988276 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 00:40:29.991540 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1219 00:40:29.995039 Total UI for P1: 0, mck2ui 16
1220 00:40:29.998325 best dqsien dly found for B0: ( 0, 14, 6)
1221 00:40:30.001613 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1222 00:40:30.004645 Total UI for P1: 0, mck2ui 16
1223 00:40:30.008360 best dqsien dly found for B1: ( 0, 14, 8)
1224 00:40:30.011447 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1225 00:40:30.014999 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1226 00:40:30.015490
1227 00:40:30.018092 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1228 00:40:30.025305 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1229 00:40:30.025926 [Gating] SW calibration Done
1230 00:40:30.026348 ==
1231 00:40:30.028509 Dram Type= 6, Freq= 0, CH_0, rank 1
1232 00:40:30.035182 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1233 00:40:30.035675 ==
1234 00:40:30.036060 RX Vref Scan: 0
1235 00:40:30.036427
1236 00:40:30.038784 RX Vref 0 -> 0, step: 1
1237 00:40:30.039239
1238 00:40:30.042197 RX Delay -130 -> 252, step: 16
1239 00:40:30.045644 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
1240 00:40:30.048289 iDelay=206, Bit 1, Center 93 (-18 ~ 205) 224
1241 00:40:30.051482 iDelay=206, Bit 2, Center 93 (-18 ~ 205) 224
1242 00:40:30.055510 iDelay=206, Bit 3, Center 93 (-18 ~ 205) 224
1243 00:40:30.062123 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1244 00:40:30.065173 iDelay=206, Bit 5, Center 85 (-34 ~ 205) 240
1245 00:40:30.068634 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1246 00:40:30.072176 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1247 00:40:30.075239 iDelay=206, Bit 8, Center 77 (-34 ~ 189) 224
1248 00:40:30.082187 iDelay=206, Bit 9, Center 77 (-34 ~ 189) 224
1249 00:40:30.085340 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
1250 00:40:30.088637 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1251 00:40:30.091925 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
1252 00:40:30.095228 iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224
1253 00:40:30.101751 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
1254 00:40:30.105156 iDelay=206, Bit 15, Center 93 (-18 ~ 205) 224
1255 00:40:30.105544 ==
1256 00:40:30.108450 Dram Type= 6, Freq= 0, CH_0, rank 1
1257 00:40:30.112184 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1258 00:40:30.112649 ==
1259 00:40:30.115338 DQS Delay:
1260 00:40:30.115823 DQS0 = 0, DQS1 = 0
1261 00:40:30.116234 DQM Delay:
1262 00:40:30.118657 DQM0 = 92, DQM1 = 85
1263 00:40:30.119137 DQ Delay:
1264 00:40:30.121990 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =93
1265 00:40:30.125299 DQ4 =93, DQ5 =85, DQ6 =93, DQ7 =93
1266 00:40:30.129085 DQ8 =77, DQ9 =77, DQ10 =77, DQ11 =77
1267 00:40:30.132321 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1268 00:40:30.132704
1269 00:40:30.132999
1270 00:40:30.133272 ==
1271 00:40:30.135741 Dram Type= 6, Freq= 0, CH_0, rank 1
1272 00:40:30.138941 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1273 00:40:30.142299 ==
1274 00:40:30.142677
1275 00:40:30.142972
1276 00:40:30.143245 TX Vref Scan disable
1277 00:40:30.145763 == TX Byte 0 ==
1278 00:40:30.149107 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1279 00:40:30.152493 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1280 00:40:30.155870 == TX Byte 1 ==
1281 00:40:30.159321 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1282 00:40:30.162663 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1283 00:40:30.165270 ==
1284 00:40:30.165677 Dram Type= 6, Freq= 0, CH_0, rank 1
1285 00:40:30.172091 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1286 00:40:30.172478 ==
1287 00:40:30.184506 TX Vref=22, minBit 8, minWin=27, winSum=448
1288 00:40:30.188175 TX Vref=24, minBit 8, minWin=27, winSum=450
1289 00:40:30.191078 TX Vref=26, minBit 1, minWin=28, winSum=458
1290 00:40:30.194301 TX Vref=28, minBit 4, minWin=28, winSum=459
1291 00:40:30.198016 TX Vref=30, minBit 5, minWin=28, winSum=459
1292 00:40:30.201248 TX Vref=32, minBit 7, minWin=28, winSum=458
1293 00:40:30.207722 [TxChooseVref] Worse bit 4, Min win 28, Win sum 459, Final Vref 28
1294 00:40:30.208206
1295 00:40:30.211135 Final TX Range 1 Vref 28
1296 00:40:30.211588
1297 00:40:30.212052 ==
1298 00:40:30.214787 Dram Type= 6, Freq= 0, CH_0, rank 1
1299 00:40:30.217937 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1300 00:40:30.218405 ==
1301 00:40:30.218839
1302 00:40:30.219128
1303 00:40:30.220955 TX Vref Scan disable
1304 00:40:30.224308 == TX Byte 0 ==
1305 00:40:30.227482 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1306 00:40:30.231597 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1307 00:40:30.234704 == TX Byte 1 ==
1308 00:40:30.238011 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1309 00:40:30.241412 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1310 00:40:30.241863
1311 00:40:30.244451 [DATLAT]
1312 00:40:30.244718 Freq=800, CH0 RK1
1313 00:40:30.244927
1314 00:40:30.247865 DATLAT Default: 0xa
1315 00:40:30.248068 0, 0xFFFF, sum = 0
1316 00:40:30.251278 1, 0xFFFF, sum = 0
1317 00:40:30.251484 2, 0xFFFF, sum = 0
1318 00:40:30.254828 3, 0xFFFF, sum = 0
1319 00:40:30.255031 4, 0xFFFF, sum = 0
1320 00:40:30.258225 5, 0xFFFF, sum = 0
1321 00:40:30.258430 6, 0xFFFF, sum = 0
1322 00:40:30.261568 7, 0xFFFF, sum = 0
1323 00:40:30.261776 8, 0xFFFF, sum = 0
1324 00:40:30.264944 9, 0x0, sum = 1
1325 00:40:30.265156 10, 0x0, sum = 2
1326 00:40:30.268380 11, 0x0, sum = 3
1327 00:40:30.268597 12, 0x0, sum = 4
1328 00:40:30.271014 best_step = 10
1329 00:40:30.271233
1330 00:40:30.271391 ==
1331 00:40:30.274611 Dram Type= 6, Freq= 0, CH_0, rank 1
1332 00:40:30.277978 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1333 00:40:30.278192 ==
1334 00:40:30.281481 RX Vref Scan: 0
1335 00:40:30.281704
1336 00:40:30.281864 RX Vref 0 -> 0, step: 1
1337 00:40:30.282013
1338 00:40:30.284975 RX Delay -79 -> 252, step: 8
1339 00:40:30.291403 iDelay=209, Bit 0, Center 92 (-15 ~ 200) 216
1340 00:40:30.294823 iDelay=209, Bit 1, Center 96 (-7 ~ 200) 208
1341 00:40:30.298394 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1342 00:40:30.301446 iDelay=209, Bit 3, Center 92 (-15 ~ 200) 216
1343 00:40:30.304960 iDelay=209, Bit 4, Center 96 (-15 ~ 208) 224
1344 00:40:30.308008 iDelay=209, Bit 5, Center 84 (-23 ~ 192) 216
1345 00:40:30.314856 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1346 00:40:30.318116 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1347 00:40:30.321339 iDelay=209, Bit 8, Center 72 (-39 ~ 184) 224
1348 00:40:30.324802 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1349 00:40:30.328037 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1350 00:40:30.335094 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1351 00:40:30.338101 iDelay=209, Bit 12, Center 88 (-15 ~ 192) 208
1352 00:40:30.341544 iDelay=209, Bit 13, Center 92 (-15 ~ 200) 216
1353 00:40:30.344567 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1354 00:40:30.348295 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1355 00:40:30.351464 ==
1356 00:40:30.352011 Dram Type= 6, Freq= 0, CH_0, rank 1
1357 00:40:30.358194 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1358 00:40:30.358666 ==
1359 00:40:30.358977 DQS Delay:
1360 00:40:30.361768 DQS0 = 0, DQS1 = 0
1361 00:40:30.362152 DQM Delay:
1362 00:40:30.365101 DQM0 = 93, DQM1 = 82
1363 00:40:30.365486 DQ Delay:
1364 00:40:30.368197 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =92
1365 00:40:30.371501 DQ4 =96, DQ5 =84, DQ6 =100, DQ7 =100
1366 00:40:30.374939 DQ8 =72, DQ9 =68, DQ10 =84, DQ11 =76
1367 00:40:30.378352 DQ12 =88, DQ13 =92, DQ14 =92, DQ15 =88
1368 00:40:30.378739
1369 00:40:30.379034
1370 00:40:30.385154 [DQSOSCAuto] RK1, (LSB)MR18= 0x4414, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 392 ps
1371 00:40:30.388585 CH0 RK1: MR19=606, MR18=4414
1372 00:40:30.395201 CH0_RK1: MR19=0x606, MR18=0x4414, DQSOSC=392, MR23=63, INC=96, DEC=64
1373 00:40:30.398517 [RxdqsGatingPostProcess] freq 800
1374 00:40:30.401946 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1375 00:40:30.405350 Pre-setting of DQS Precalculation
1376 00:40:30.412231 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1377 00:40:30.412642 ==
1378 00:40:30.414955 Dram Type= 6, Freq= 0, CH_1, rank 0
1379 00:40:30.418495 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1380 00:40:30.418903 ==
1381 00:40:30.425186 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1382 00:40:30.431702 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1383 00:40:30.439106 [CA 0] Center 36 (6~67) winsize 62
1384 00:40:30.442233 [CA 1] Center 36 (6~67) winsize 62
1385 00:40:30.445957 [CA 2] Center 35 (4~66) winsize 63
1386 00:40:30.448934 [CA 3] Center 34 (4~65) winsize 62
1387 00:40:30.452455 [CA 4] Center 34 (4~65) winsize 62
1388 00:40:30.455713 [CA 5] Center 34 (4~64) winsize 61
1389 00:40:30.455853
1390 00:40:30.459198 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1391 00:40:30.459338
1392 00:40:30.462522 [CATrainingPosCal] consider 1 rank data
1393 00:40:30.465808 u2DelayCellTimex100 = 270/100 ps
1394 00:40:30.469177 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1395 00:40:30.472439 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1396 00:40:30.479221 CA2 delay=35 (4~66),Diff = 1 PI (7 cell)
1397 00:40:30.482170 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1398 00:40:30.485962 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1399 00:40:30.489064 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1400 00:40:30.489203
1401 00:40:30.492376 CA PerBit enable=1, Macro0, CA PI delay=34
1402 00:40:30.492961
1403 00:40:30.495907 [CBTSetCACLKResult] CA Dly = 34
1404 00:40:30.496416 CS Dly: 6 (0~37)
1405 00:40:30.496878 ==
1406 00:40:30.499224 Dram Type= 6, Freq= 0, CH_1, rank 1
1407 00:40:30.505972 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1408 00:40:30.506547 ==
1409 00:40:30.509464 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1410 00:40:30.515698 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1411 00:40:30.525252 [CA 0] Center 36 (6~67) winsize 62
1412 00:40:30.528596 [CA 1] Center 37 (6~68) winsize 63
1413 00:40:30.531991 [CA 2] Center 35 (5~66) winsize 62
1414 00:40:30.534865 [CA 3] Center 35 (5~65) winsize 61
1415 00:40:30.538263 [CA 4] Center 35 (4~66) winsize 63
1416 00:40:30.541464 [CA 5] Center 34 (4~65) winsize 62
1417 00:40:30.541605
1418 00:40:30.544726 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1419 00:40:30.544838
1420 00:40:30.548339 [CATrainingPosCal] consider 2 rank data
1421 00:40:30.551837 u2DelayCellTimex100 = 270/100 ps
1422 00:40:30.555265 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1423 00:40:30.558618 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1424 00:40:30.564816 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
1425 00:40:30.568118 CA3 delay=35 (5~65),Diff = 1 PI (7 cell)
1426 00:40:30.571883 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1427 00:40:30.574868 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1428 00:40:30.574986
1429 00:40:30.578770 CA PerBit enable=1, Macro0, CA PI delay=34
1430 00:40:30.578888
1431 00:40:30.581960 [CBTSetCACLKResult] CA Dly = 34
1432 00:40:30.582115 CS Dly: 6 (0~38)
1433 00:40:30.582256
1434 00:40:30.584885 ----->DramcWriteLeveling(PI) begin...
1435 00:40:30.585027 ==
1436 00:40:30.588913 Dram Type= 6, Freq= 0, CH_1, rank 0
1437 00:40:30.595458 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1438 00:40:30.595626 ==
1439 00:40:30.598559 Write leveling (Byte 0): 29 => 29
1440 00:40:30.601991 Write leveling (Byte 1): 29 => 29
1441 00:40:30.602134 DramcWriteLeveling(PI) end<-----
1442 00:40:30.602253
1443 00:40:30.605357 ==
1444 00:40:30.608577 Dram Type= 6, Freq= 0, CH_1, rank 0
1445 00:40:30.611793 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1446 00:40:30.611930 ==
1447 00:40:30.615239 [Gating] SW mode calibration
1448 00:40:30.621664 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1449 00:40:30.625677 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1450 00:40:30.632138 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1451 00:40:30.635610 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1452 00:40:30.639023 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1453 00:40:30.645906 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 00:40:30.649338 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 00:40:30.652665 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 00:40:30.658931 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 00:40:30.662701 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 00:40:30.665435 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 00:40:30.669524 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 00:40:30.675992 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 00:40:30.679210 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 00:40:30.682105 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 00:40:30.688995 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 00:40:30.692124 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 00:40:30.695683 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 00:40:30.702160 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 00:40:30.705621 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1468 00:40:30.709215 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 00:40:30.715748 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 00:40:30.718763 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 00:40:30.722146 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 00:40:30.728829 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 00:40:30.732011 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 00:40:30.735899 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 00:40:30.742631 0 9 4 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
1476 00:40:30.746107 0 9 8 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
1477 00:40:30.748819 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1478 00:40:30.752400 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1479 00:40:30.759176 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1480 00:40:30.762522 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1481 00:40:30.766052 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1482 00:40:30.772013 0 10 0 | B1->B0 | 3434 3333 | 1 1 | (1 0) (1 0)
1483 00:40:30.775243 0 10 4 | B1->B0 | 3131 2f2f | 1 0 | (1 0) (1 0)
1484 00:40:30.778703 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1485 00:40:30.785467 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 00:40:30.788909 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 00:40:30.792007 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 00:40:30.798767 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 00:40:30.802392 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 00:40:30.805908 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 00:40:30.812081 0 11 4 | B1->B0 | 2424 3131 | 0 0 | (0 0) (0 0)
1492 00:40:30.815556 0 11 8 | B1->B0 | 4242 4646 | 1 0 | (0 0) (0 0)
1493 00:40:30.819119 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1494 00:40:30.825487 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1495 00:40:30.828936 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1496 00:40:30.832242 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1497 00:40:30.836026 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1498 00:40:30.842252 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1499 00:40:30.845687 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1500 00:40:30.849341 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1501 00:40:30.856102 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 00:40:30.859562 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 00:40:30.862717 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 00:40:30.869738 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 00:40:30.873152 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 00:40:30.876477 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 00:40:30.883147 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 00:40:30.886325 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 00:40:30.889606 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 00:40:30.896033 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 00:40:30.899378 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 00:40:30.902687 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 00:40:30.909202 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 00:40:30.912241 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1515 00:40:30.915659 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1516 00:40:30.919087 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1517 00:40:30.922439 Total UI for P1: 0, mck2ui 16
1518 00:40:30.925818 best dqsien dly found for B0: ( 0, 14, 2)
1519 00:40:30.929313 Total UI for P1: 0, mck2ui 16
1520 00:40:30.932836 best dqsien dly found for B1: ( 0, 14, 4)
1521 00:40:30.936183 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1522 00:40:30.939465 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1523 00:40:30.942884
1524 00:40:30.945618 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1525 00:40:30.949719 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1526 00:40:30.952576 [Gating] SW calibration Done
1527 00:40:30.952653 ==
1528 00:40:30.955732 Dram Type= 6, Freq= 0, CH_1, rank 0
1529 00:40:30.959392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1530 00:40:30.959491 ==
1531 00:40:30.959576 RX Vref Scan: 0
1532 00:40:30.959663
1533 00:40:30.962849 RX Vref 0 -> 0, step: 1
1534 00:40:30.962925
1535 00:40:30.965734 RX Delay -130 -> 252, step: 16
1536 00:40:30.969184 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1537 00:40:30.972544 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1538 00:40:30.979316 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1539 00:40:30.982539 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1540 00:40:30.986027 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1541 00:40:30.989204 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1542 00:40:30.992516 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1543 00:40:30.995876 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1544 00:40:31.002768 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1545 00:40:31.006053 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1546 00:40:31.009256 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1547 00:40:31.012830 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1548 00:40:31.016098 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1549 00:40:31.023000 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1550 00:40:31.025937 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1551 00:40:31.029520 iDelay=222, Bit 15, Center 101 (-2 ~ 205) 208
1552 00:40:31.029604 ==
1553 00:40:31.032968 Dram Type= 6, Freq= 0, CH_1, rank 0
1554 00:40:31.036417 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1555 00:40:31.036496 ==
1556 00:40:31.039851 DQS Delay:
1557 00:40:31.039917 DQS0 = 0, DQS1 = 0
1558 00:40:31.043298 DQM Delay:
1559 00:40:31.043363 DQM0 = 93, DQM1 = 88
1560 00:40:31.043418 DQ Delay:
1561 00:40:31.046074 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1562 00:40:31.049477 DQ4 =93, DQ5 =109, DQ6 =101, DQ7 =93
1563 00:40:31.052979 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =85
1564 00:40:31.056235 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =101
1565 00:40:31.056305
1566 00:40:31.056362
1567 00:40:31.059540 ==
1568 00:40:31.062677 Dram Type= 6, Freq= 0, CH_1, rank 0
1569 00:40:31.066053 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1570 00:40:31.066145 ==
1571 00:40:31.066230
1572 00:40:31.066314
1573 00:40:31.069458 TX Vref Scan disable
1574 00:40:31.069588 == TX Byte 0 ==
1575 00:40:31.076036 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1576 00:40:31.079212 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1577 00:40:31.079294 == TX Byte 1 ==
1578 00:40:31.086376 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1579 00:40:31.089358 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1580 00:40:31.089440 ==
1581 00:40:31.092785 Dram Type= 6, Freq= 0, CH_1, rank 0
1582 00:40:31.096092 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1583 00:40:31.096177 ==
1584 00:40:31.109516 TX Vref=22, minBit 0, minWin=27, winSum=435
1585 00:40:31.112619 TX Vref=24, minBit 2, minWin=26, winSum=442
1586 00:40:31.116246 TX Vref=26, minBit 0, minWin=28, winSum=450
1587 00:40:31.119483 TX Vref=28, minBit 2, minWin=27, winSum=452
1588 00:40:31.123241 TX Vref=30, minBit 5, minWin=27, winSum=454
1589 00:40:31.126325 TX Vref=32, minBit 2, minWin=27, winSum=450
1590 00:40:31.133017 [TxChooseVref] Worse bit 0, Min win 28, Win sum 450, Final Vref 26
1591 00:40:31.133095
1592 00:40:31.136345 Final TX Range 1 Vref 26
1593 00:40:31.136422
1594 00:40:31.136481 ==
1595 00:40:31.139774 Dram Type= 6, Freq= 0, CH_1, rank 0
1596 00:40:31.143033 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1597 00:40:31.143116 ==
1598 00:40:31.143180
1599 00:40:31.143239
1600 00:40:31.146420 TX Vref Scan disable
1601 00:40:31.149858 == TX Byte 0 ==
1602 00:40:31.153295 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1603 00:40:31.156215 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1604 00:40:31.159525 == TX Byte 1 ==
1605 00:40:31.162987 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1606 00:40:31.166469 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1607 00:40:31.166583
1608 00:40:31.170206 [DATLAT]
1609 00:40:31.170355 Freq=800, CH1 RK0
1610 00:40:31.170456
1611 00:40:31.173509 DATLAT Default: 0xa
1612 00:40:31.173716 0, 0xFFFF, sum = 0
1613 00:40:31.176821 1, 0xFFFF, sum = 0
1614 00:40:31.177062 2, 0xFFFF, sum = 0
1615 00:40:31.180126 3, 0xFFFF, sum = 0
1616 00:40:31.180352 4, 0xFFFF, sum = 0
1617 00:40:31.183568 5, 0xFFFF, sum = 0
1618 00:40:31.183855 6, 0xFFFF, sum = 0
1619 00:40:31.186908 7, 0xFFFF, sum = 0
1620 00:40:31.187190 8, 0xFFFF, sum = 0
1621 00:40:31.190518 9, 0x0, sum = 1
1622 00:40:31.190716 10, 0x0, sum = 2
1623 00:40:31.193203 11, 0x0, sum = 3
1624 00:40:31.193514 12, 0x0, sum = 4
1625 00:40:31.197137 best_step = 10
1626 00:40:31.197419
1627 00:40:31.197710 ==
1628 00:40:31.200090 Dram Type= 6, Freq= 0, CH_1, rank 0
1629 00:40:31.203954 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1630 00:40:31.204343 ==
1631 00:40:31.204691 RX Vref Scan: 1
1632 00:40:31.206901
1633 00:40:31.207287 Set Vref Range= 32 -> 127
1634 00:40:31.207634
1635 00:40:31.210509 RX Vref 32 -> 127, step: 1
1636 00:40:31.210878
1637 00:40:31.213611 RX Delay -79 -> 252, step: 8
1638 00:40:31.213894
1639 00:40:31.217185 Set Vref, RX VrefLevel [Byte0]: 32
1640 00:40:31.220619 [Byte1]: 32
1641 00:40:31.220845
1642 00:40:31.223401 Set Vref, RX VrefLevel [Byte0]: 33
1643 00:40:31.226931 [Byte1]: 33
1644 00:40:31.227143
1645 00:40:31.230460 Set Vref, RX VrefLevel [Byte0]: 34
1646 00:40:31.233235 [Byte1]: 34
1647 00:40:31.237363
1648 00:40:31.237494 Set Vref, RX VrefLevel [Byte0]: 35
1649 00:40:31.240494 [Byte1]: 35
1650 00:40:31.244426
1651 00:40:31.244547 Set Vref, RX VrefLevel [Byte0]: 36
1652 00:40:31.247909 [Byte1]: 36
1653 00:40:31.252606
1654 00:40:31.252703 Set Vref, RX VrefLevel [Byte0]: 37
1655 00:40:31.255355 [Byte1]: 37
1656 00:40:31.259600
1657 00:40:31.259684 Set Vref, RX VrefLevel [Byte0]: 38
1658 00:40:31.263006 [Byte1]: 38
1659 00:40:31.267750
1660 00:40:31.267834 Set Vref, RX VrefLevel [Byte0]: 39
1661 00:40:31.270512 [Byte1]: 39
1662 00:40:31.275226
1663 00:40:31.275302 Set Vref, RX VrefLevel [Byte0]: 40
1664 00:40:31.278416 [Byte1]: 40
1665 00:40:31.282678
1666 00:40:31.282753 Set Vref, RX VrefLevel [Byte0]: 41
1667 00:40:31.285902 [Byte1]: 41
1668 00:40:31.289847
1669 00:40:31.289923 Set Vref, RX VrefLevel [Byte0]: 42
1670 00:40:31.293064 [Byte1]: 42
1671 00:40:31.297298
1672 00:40:31.297374 Set Vref, RX VrefLevel [Byte0]: 43
1673 00:40:31.301269 [Byte1]: 43
1674 00:40:31.305374
1675 00:40:31.305449 Set Vref, RX VrefLevel [Byte0]: 44
1676 00:40:31.308090 [Byte1]: 44
1677 00:40:31.312877
1678 00:40:31.312965 Set Vref, RX VrefLevel [Byte0]: 45
1679 00:40:31.315943 [Byte1]: 45
1680 00:40:31.320271
1681 00:40:31.320366 Set Vref, RX VrefLevel [Byte0]: 46
1682 00:40:31.323334 [Byte1]: 46
1683 00:40:31.327463
1684 00:40:31.327577 Set Vref, RX VrefLevel [Byte0]: 47
1685 00:40:31.330925 [Byte1]: 47
1686 00:40:31.335314
1687 00:40:31.335439 Set Vref, RX VrefLevel [Byte0]: 48
1688 00:40:31.338757 [Byte1]: 48
1689 00:40:31.342617
1690 00:40:31.342777 Set Vref, RX VrefLevel [Byte0]: 49
1691 00:40:31.346431 [Byte1]: 49
1692 00:40:31.350519
1693 00:40:31.350706 Set Vref, RX VrefLevel [Byte0]: 50
1694 00:40:31.353798 [Byte1]: 50
1695 00:40:31.358070
1696 00:40:31.358295 Set Vref, RX VrefLevel [Byte0]: 51
1697 00:40:31.361279 [Byte1]: 51
1698 00:40:31.365880
1699 00:40:31.366105 Set Vref, RX VrefLevel [Byte0]: 52
1700 00:40:31.369189 [Byte1]: 52
1701 00:40:31.373297
1702 00:40:31.373520 Set Vref, RX VrefLevel [Byte0]: 53
1703 00:40:31.376740 [Byte1]: 53
1704 00:40:31.380877
1705 00:40:31.381109 Set Vref, RX VrefLevel [Byte0]: 54
1706 00:40:31.384133 [Byte1]: 54
1707 00:40:31.387986
1708 00:40:31.388105 Set Vref, RX VrefLevel [Byte0]: 55
1709 00:40:31.391496 [Byte1]: 55
1710 00:40:31.396043
1711 00:40:31.396183 Set Vref, RX VrefLevel [Byte0]: 56
1712 00:40:31.398743 [Byte1]: 56
1713 00:40:31.403007
1714 00:40:31.403107 Set Vref, RX VrefLevel [Byte0]: 57
1715 00:40:31.406177 [Byte1]: 57
1716 00:40:31.410813
1717 00:40:31.410893 Set Vref, RX VrefLevel [Byte0]: 58
1718 00:40:31.414215 [Byte1]: 58
1719 00:40:31.418260
1720 00:40:31.418336 Set Vref, RX VrefLevel [Byte0]: 59
1721 00:40:31.421557 [Byte1]: 59
1722 00:40:31.425892
1723 00:40:31.425969 Set Vref, RX VrefLevel [Byte0]: 60
1724 00:40:31.429144 [Byte1]: 60
1725 00:40:31.433464
1726 00:40:31.433571 Set Vref, RX VrefLevel [Byte0]: 61
1727 00:40:31.436712 [Byte1]: 61
1728 00:40:31.440858
1729 00:40:31.440934 Set Vref, RX VrefLevel [Byte0]: 62
1730 00:40:31.444145 [Byte1]: 62
1731 00:40:31.448620
1732 00:40:31.448696 Set Vref, RX VrefLevel [Byte0]: 63
1733 00:40:31.451906 [Byte1]: 63
1734 00:40:31.455993
1735 00:40:31.456074 Set Vref, RX VrefLevel [Byte0]: 64
1736 00:40:31.459759 [Byte1]: 64
1737 00:40:31.463844
1738 00:40:31.464297 Set Vref, RX VrefLevel [Byte0]: 65
1739 00:40:31.467216 [Byte1]: 65
1740 00:40:31.471552
1741 00:40:31.471941 Set Vref, RX VrefLevel [Byte0]: 66
1742 00:40:31.474533 [Byte1]: 66
1743 00:40:31.479077
1744 00:40:31.479515 Set Vref, RX VrefLevel [Byte0]: 67
1745 00:40:31.482063 [Byte1]: 67
1746 00:40:31.486761
1747 00:40:31.487109 Set Vref, RX VrefLevel [Byte0]: 68
1748 00:40:31.489530 [Byte1]: 68
1749 00:40:31.494201
1750 00:40:31.494411 Set Vref, RX VrefLevel [Byte0]: 69
1751 00:40:31.497352 [Byte1]: 69
1752 00:40:31.501384
1753 00:40:31.501569 Set Vref, RX VrefLevel [Byte0]: 70
1754 00:40:31.504729 [Byte1]: 70
1755 00:40:31.508670
1756 00:40:31.508825 Set Vref, RX VrefLevel [Byte0]: 71
1757 00:40:31.512033 [Byte1]: 71
1758 00:40:31.516722
1759 00:40:31.516844 Final RX Vref Byte 0 = 58 to rank0
1760 00:40:31.520103 Final RX Vref Byte 1 = 57 to rank0
1761 00:40:31.523347 Final RX Vref Byte 0 = 58 to rank1
1762 00:40:31.526814 Final RX Vref Byte 1 = 57 to rank1==
1763 00:40:31.529922 Dram Type= 6, Freq= 0, CH_1, rank 0
1764 00:40:31.533264 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1765 00:40:31.536531 ==
1766 00:40:31.536684 DQS Delay:
1767 00:40:31.536818 DQS0 = 0, DQS1 = 0
1768 00:40:31.539931 DQM Delay:
1769 00:40:31.540050 DQM0 = 95, DQM1 = 90
1770 00:40:31.543611 DQ Delay:
1771 00:40:31.543732 DQ0 =96, DQ1 =88, DQ2 =84, DQ3 =88
1772 00:40:31.546643 DQ4 =96, DQ5 =108, DQ6 =108, DQ7 =92
1773 00:40:31.549912 DQ8 =80, DQ9 =80, DQ10 =92, DQ11 =84
1774 00:40:31.556490 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =100
1775 00:40:31.556642
1776 00:40:31.556761
1777 00:40:31.563057 [DQSOSCAuto] RK0, (LSB)MR18= 0x314d, (MSB)MR19= 0x606, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
1778 00:40:31.566545 CH1 RK0: MR19=606, MR18=314D
1779 00:40:31.573587 CH1_RK0: MR19=0x606, MR18=0x314D, DQSOSC=390, MR23=63, INC=97, DEC=64
1780 00:40:31.573974
1781 00:40:31.577039 ----->DramcWriteLeveling(PI) begin...
1782 00:40:31.577424 ==
1783 00:40:31.580386 Dram Type= 6, Freq= 0, CH_1, rank 1
1784 00:40:31.583770 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1785 00:40:31.584175 ==
1786 00:40:31.586794 Write leveling (Byte 0): 29 => 29
1787 00:40:31.590344 Write leveling (Byte 1): 29 => 29
1788 00:40:31.593334 DramcWriteLeveling(PI) end<-----
1789 00:40:31.593767
1790 00:40:31.594160 ==
1791 00:40:31.597050 Dram Type= 6, Freq= 0, CH_1, rank 1
1792 00:40:31.600329 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1793 00:40:31.600759 ==
1794 00:40:31.603207 [Gating] SW mode calibration
1795 00:40:31.610040 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1796 00:40:31.616747 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1797 00:40:31.619955 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1798 00:40:31.623685 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1799 00:40:31.630201 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1800 00:40:31.633697 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1801 00:40:31.636981 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1802 00:40:31.643370 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1803 00:40:31.647077 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1804 00:40:31.650031 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1805 00:40:31.656864 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1806 00:40:31.660619 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1807 00:40:31.664007 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1808 00:40:31.667004 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1809 00:40:31.673787 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1810 00:40:31.677037 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1811 00:40:31.680461 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1812 00:40:31.687388 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1813 00:40:31.690625 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1814 00:40:31.693930 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1815 00:40:31.700354 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 00:40:31.704036 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 00:40:31.707218 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 00:40:31.714202 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 00:40:31.717300 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 00:40:31.720666 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 00:40:31.727565 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 00:40:31.730872 0 9 4 | B1->B0 | 2c2c 2323 | 1 0 | (1 1) (1 1)
1823 00:40:31.733889 0 9 8 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
1824 00:40:31.740742 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1825 00:40:31.744094 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1826 00:40:31.747365 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1827 00:40:31.753809 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1828 00:40:31.757177 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1829 00:40:31.760466 0 10 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
1830 00:40:31.763691 0 10 4 | B1->B0 | 2d2d 3030 | 0 0 | (0 0) (1 0)
1831 00:40:31.770242 0 10 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (1 1)
1832 00:40:31.773983 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 00:40:31.777107 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 00:40:31.783712 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 00:40:31.787083 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 00:40:31.790626 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 00:40:31.797500 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 00:40:31.800729 0 11 4 | B1->B0 | 3b3b 2a2a | 0 0 | (0 0) (0 0)
1839 00:40:31.804093 0 11 8 | B1->B0 | 4646 4242 | 0 0 | (0 0) (0 0)
1840 00:40:31.810773 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1841 00:40:31.813851 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1842 00:40:31.817109 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1843 00:40:31.824058 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1844 00:40:31.827287 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1845 00:40:31.830672 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1846 00:40:31.834138 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1847 00:40:31.840940 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1848 00:40:31.844180 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1849 00:40:31.847421 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1850 00:40:31.854534 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1851 00:40:31.857665 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1852 00:40:31.861075 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1853 00:40:31.867355 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1854 00:40:31.870386 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1855 00:40:31.874217 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1856 00:40:31.880665 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1857 00:40:31.883772 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1858 00:40:31.887822 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1859 00:40:31.894238 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1860 00:40:31.897701 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1861 00:40:31.901111 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1862 00:40:31.907688 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1863 00:40:31.908078 Total UI for P1: 0, mck2ui 16
1864 00:40:31.911115 best dqsien dly found for B0: ( 0, 14, 2)
1865 00:40:31.914491 Total UI for P1: 0, mck2ui 16
1866 00:40:31.917847 best dqsien dly found for B1: ( 0, 14, 2)
1867 00:40:31.920998 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1868 00:40:31.924200 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1869 00:40:31.927522
1870 00:40:31.930738 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1871 00:40:31.934582 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1872 00:40:31.937895 [Gating] SW calibration Done
1873 00:40:31.938283 ==
1874 00:40:31.940628 Dram Type= 6, Freq= 0, CH_1, rank 1
1875 00:40:31.944153 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1876 00:40:31.944544 ==
1877 00:40:31.944847 RX Vref Scan: 0
1878 00:40:31.945127
1879 00:40:31.947427 RX Vref 0 -> 0, step: 1
1880 00:40:31.947834
1881 00:40:31.951431 RX Delay -130 -> 252, step: 16
1882 00:40:31.954019 iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208
1883 00:40:31.957810 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1884 00:40:31.964300 iDelay=222, Bit 2, Center 85 (-18 ~ 189) 208
1885 00:40:31.967405 iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208
1886 00:40:31.970879 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1887 00:40:31.974139 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1888 00:40:31.977339 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1889 00:40:31.980739 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1890 00:40:31.987948 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1891 00:40:31.991082 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1892 00:40:31.994241 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1893 00:40:31.997484 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1894 00:40:32.004276 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1895 00:40:32.007398 iDelay=222, Bit 13, Center 101 (-2 ~ 205) 208
1896 00:40:32.011465 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1897 00:40:32.014242 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1898 00:40:32.014630 ==
1899 00:40:32.017569 Dram Type= 6, Freq= 0, CH_1, rank 1
1900 00:40:32.020938 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1901 00:40:32.024945 ==
1902 00:40:32.025410 DQS Delay:
1903 00:40:32.025803 DQS0 = 0, DQS1 = 0
1904 00:40:32.028172 DQM Delay:
1905 00:40:32.028618 DQM0 = 93, DQM1 = 88
1906 00:40:32.028935 DQ Delay:
1907 00:40:32.031316 DQ0 =101, DQ1 =85, DQ2 =85, DQ3 =85
1908 00:40:32.034382 DQ4 =85, DQ5 =109, DQ6 =101, DQ7 =93
1909 00:40:32.038121 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =85
1910 00:40:32.041324 DQ12 =93, DQ13 =101, DQ14 =93, DQ15 =93
1911 00:40:32.041833
1912 00:40:32.044536
1913 00:40:32.044942 ==
1914 00:40:32.048176 Dram Type= 6, Freq= 0, CH_1, rank 1
1915 00:40:32.051255 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1916 00:40:32.051718 ==
1917 00:40:32.052036
1918 00:40:32.052480
1919 00:40:32.054550 TX Vref Scan disable
1920 00:40:32.055027 == TX Byte 0 ==
1921 00:40:32.061260 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1922 00:40:32.064706 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1923 00:40:32.065105 == TX Byte 1 ==
1924 00:40:32.067928 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1925 00:40:32.075058 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1926 00:40:32.075450 ==
1927 00:40:32.078392 Dram Type= 6, Freq= 0, CH_1, rank 1
1928 00:40:32.081513 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1929 00:40:32.081951 ==
1930 00:40:32.094836 TX Vref=22, minBit 2, minWin=27, winSum=446
1931 00:40:32.097692 TX Vref=24, minBit 1, minWin=27, winSum=447
1932 00:40:32.101435 TX Vref=26, minBit 1, minWin=27, winSum=452
1933 00:40:32.104740 TX Vref=28, minBit 1, minWin=27, winSum=456
1934 00:40:32.107903 TX Vref=30, minBit 0, minWin=28, winSum=455
1935 00:40:32.111280 TX Vref=32, minBit 1, minWin=27, winSum=452
1936 00:40:32.118418 [TxChooseVref] Worse bit 0, Min win 28, Win sum 455, Final Vref 30
1937 00:40:32.118942
1938 00:40:32.121158 Final TX Range 1 Vref 30
1939 00:40:32.121675
1940 00:40:32.122000 ==
1941 00:40:32.124597 Dram Type= 6, Freq= 0, CH_1, rank 1
1942 00:40:32.128049 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1943 00:40:32.128443 ==
1944 00:40:32.128747
1945 00:40:32.131571
1946 00:40:32.131958 TX Vref Scan disable
1947 00:40:32.134981 == TX Byte 0 ==
1948 00:40:32.138410 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1949 00:40:32.141489 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1950 00:40:32.144619 == TX Byte 1 ==
1951 00:40:32.148136 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1952 00:40:32.151360 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1953 00:40:32.151774
1954 00:40:32.154595 [DATLAT]
1955 00:40:32.154984 Freq=800, CH1 RK1
1956 00:40:32.155285
1957 00:40:32.158322 DATLAT Default: 0xa
1958 00:40:32.158710 0, 0xFFFF, sum = 0
1959 00:40:32.161654 1, 0xFFFF, sum = 0
1960 00:40:32.162052 2, 0xFFFF, sum = 0
1961 00:40:32.164968 3, 0xFFFF, sum = 0
1962 00:40:32.165371 4, 0xFFFF, sum = 0
1963 00:40:32.168356 5, 0xFFFF, sum = 0
1964 00:40:32.168824 6, 0xFFFF, sum = 0
1965 00:40:32.171624 7, 0xFFFF, sum = 0
1966 00:40:32.172107 8, 0xFFFF, sum = 0
1967 00:40:32.174867 9, 0x0, sum = 1
1968 00:40:32.175364 10, 0x0, sum = 2
1969 00:40:32.178212 11, 0x0, sum = 3
1970 00:40:32.178610 12, 0x0, sum = 4
1971 00:40:32.181445 best_step = 10
1972 00:40:32.181862
1973 00:40:32.182165 ==
1974 00:40:32.185185 Dram Type= 6, Freq= 0, CH_1, rank 1
1975 00:40:32.188345 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1976 00:40:32.188869 ==
1977 00:40:32.192247 RX Vref Scan: 0
1978 00:40:32.192659
1979 00:40:32.192963 RX Vref 0 -> 0, step: 1
1980 00:40:32.193319
1981 00:40:32.194862 RX Delay -79 -> 252, step: 8
1982 00:40:32.201665 iDelay=209, Bit 0, Center 104 (9 ~ 200) 192
1983 00:40:32.205003 iDelay=209, Bit 1, Center 92 (-7 ~ 192) 200
1984 00:40:32.208545 iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200
1985 00:40:32.212144 iDelay=209, Bit 3, Center 92 (-7 ~ 192) 200
1986 00:40:32.215202 iDelay=209, Bit 4, Center 92 (-7 ~ 192) 200
1987 00:40:32.218275 iDelay=209, Bit 5, Center 112 (17 ~ 208) 192
1988 00:40:32.225475 iDelay=209, Bit 6, Center 108 (9 ~ 208) 200
1989 00:40:32.228207 iDelay=209, Bit 7, Center 96 (-7 ~ 200) 208
1990 00:40:32.231655 iDelay=209, Bit 8, Center 80 (-23 ~ 184) 208
1991 00:40:32.235176 iDelay=209, Bit 9, Center 80 (-23 ~ 184) 208
1992 00:40:32.238474 iDelay=209, Bit 10, Center 92 (-7 ~ 192) 200
1993 00:40:32.241826 iDelay=209, Bit 11, Center 88 (-15 ~ 192) 208
1994 00:40:32.248506 iDelay=209, Bit 12, Center 100 (-7 ~ 208) 216
1995 00:40:32.251679 iDelay=209, Bit 13, Center 96 (-7 ~ 200) 208
1996 00:40:32.254941 iDelay=209, Bit 14, Center 96 (-7 ~ 200) 208
1997 00:40:32.258719 iDelay=209, Bit 15, Center 96 (-7 ~ 200) 208
1998 00:40:32.259145 ==
1999 00:40:32.261791 Dram Type= 6, Freq= 0, CH_1, rank 1
2000 00:40:32.268593 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2001 00:40:32.269022 ==
2002 00:40:32.269324 DQS Delay:
2003 00:40:32.269650 DQS0 = 0, DQS1 = 0
2004 00:40:32.271770 DQM Delay:
2005 00:40:32.272155 DQM0 = 97, DQM1 = 91
2006 00:40:32.275472 DQ Delay:
2007 00:40:32.278787 DQ0 =104, DQ1 =92, DQ2 =84, DQ3 =92
2008 00:40:32.281956 DQ4 =92, DQ5 =112, DQ6 =108, DQ7 =96
2009 00:40:32.285361 DQ8 =80, DQ9 =80, DQ10 =92, DQ11 =88
2010 00:40:32.288811 DQ12 =100, DQ13 =96, DQ14 =96, DQ15 =96
2011 00:40:32.289238
2012 00:40:32.289534
2013 00:40:32.295587 [DQSOSCAuto] RK1, (LSB)MR18= 0x4d16, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 390 ps
2014 00:40:32.298612 CH1 RK1: MR19=606, MR18=4D16
2015 00:40:32.305142 CH1_RK1: MR19=0x606, MR18=0x4D16, DQSOSC=390, MR23=63, INC=97, DEC=64
2016 00:40:32.308570 [RxdqsGatingPostProcess] freq 800
2017 00:40:32.311929 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2018 00:40:32.315083 Pre-setting of DQS Precalculation
2019 00:40:32.322152 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2020 00:40:32.328957 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2021 00:40:32.335203 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2022 00:40:32.335640
2023 00:40:32.335944
2024 00:40:32.338579 [Calibration Summary] 1600 Mbps
2025 00:40:32.338967 CH 0, Rank 0
2026 00:40:32.342007 SW Impedance : PASS
2027 00:40:32.345309 DUTY Scan : NO K
2028 00:40:32.345735 ZQ Calibration : PASS
2029 00:40:32.348787 Jitter Meter : NO K
2030 00:40:32.349174 CBT Training : PASS
2031 00:40:32.352195 Write leveling : PASS
2032 00:40:32.355591 RX DQS gating : PASS
2033 00:40:32.356165 RX DQ/DQS(RDDQC) : PASS
2034 00:40:32.358762 TX DQ/DQS : PASS
2035 00:40:32.362172 RX DATLAT : PASS
2036 00:40:32.362563 RX DQ/DQS(Engine): PASS
2037 00:40:32.365705 TX OE : NO K
2038 00:40:32.366116 All Pass.
2039 00:40:32.366419
2040 00:40:32.369167 CH 0, Rank 1
2041 00:40:32.369592 SW Impedance : PASS
2042 00:40:32.372484 DUTY Scan : NO K
2043 00:40:32.375683 ZQ Calibration : PASS
2044 00:40:32.376073 Jitter Meter : NO K
2045 00:40:32.378728 CBT Training : PASS
2046 00:40:32.382574 Write leveling : PASS
2047 00:40:32.383054 RX DQS gating : PASS
2048 00:40:32.385705 RX DQ/DQS(RDDQC) : PASS
2049 00:40:32.389054 TX DQ/DQS : PASS
2050 00:40:32.389443 RX DATLAT : PASS
2051 00:40:32.392253 RX DQ/DQS(Engine): PASS
2052 00:40:32.392679 TX OE : NO K
2053 00:40:32.395616 All Pass.
2054 00:40:32.396000
2055 00:40:32.396455 CH 1, Rank 0
2056 00:40:32.399044 SW Impedance : PASS
2057 00:40:32.399433 DUTY Scan : NO K
2058 00:40:32.402323 ZQ Calibration : PASS
2059 00:40:32.405600 Jitter Meter : NO K
2060 00:40:32.405998 CBT Training : PASS
2061 00:40:32.408739 Write leveling : PASS
2062 00:40:32.411877 RX DQS gating : PASS
2063 00:40:32.412269 RX DQ/DQS(RDDQC) : PASS
2064 00:40:32.415459 TX DQ/DQS : PASS
2065 00:40:32.418794 RX DATLAT : PASS
2066 00:40:32.419272 RX DQ/DQS(Engine): PASS
2067 00:40:32.422020 TX OE : NO K
2068 00:40:32.422414 All Pass.
2069 00:40:32.422855
2070 00:40:32.425354 CH 1, Rank 1
2071 00:40:32.425783 SW Impedance : PASS
2072 00:40:32.428677 DUTY Scan : NO K
2073 00:40:32.431954 ZQ Calibration : PASS
2074 00:40:32.432339 Jitter Meter : NO K
2075 00:40:32.435731 CBT Training : PASS
2076 00:40:32.436151 Write leveling : PASS
2077 00:40:32.439024 RX DQS gating : PASS
2078 00:40:32.442003 RX DQ/DQS(RDDQC) : PASS
2079 00:40:32.442457 TX DQ/DQS : PASS
2080 00:40:32.445693 RX DATLAT : PASS
2081 00:40:32.449105 RX DQ/DQS(Engine): PASS
2082 00:40:32.449494 TX OE : NO K
2083 00:40:32.452508 All Pass.
2084 00:40:32.452953
2085 00:40:32.453259 DramC Write-DBI off
2086 00:40:32.455341 PER_BANK_REFRESH: Hybrid Mode
2087 00:40:32.459320 TX_TRACKING: ON
2088 00:40:32.462536 [GetDramInforAfterCalByMRR] Vendor 6.
2089 00:40:32.465945 [GetDramInforAfterCalByMRR] Revision 606.
2090 00:40:32.469240 [GetDramInforAfterCalByMRR] Revision 2 0.
2091 00:40:32.469659 MR0 0x3b3b
2092 00:40:32.469966 MR8 0x5151
2093 00:40:32.472065 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2094 00:40:32.475489
2095 00:40:32.476001 MR0 0x3b3b
2096 00:40:32.476465 MR8 0x5151
2097 00:40:32.478776 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2098 00:40:32.479279
2099 00:40:32.488787 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2100 00:40:32.492082 [FAST_K] Save calibration result to emmc
2101 00:40:32.495539 [FAST_K] Save calibration result to emmc
2102 00:40:32.498867 dram_init: config_dvfs: 1
2103 00:40:32.501943 dramc_set_vcore_voltage set vcore to 662500
2104 00:40:32.505480 Read voltage for 1200, 2
2105 00:40:32.505905 Vio18 = 0
2106 00:40:32.506207 Vcore = 662500
2107 00:40:32.508861 Vdram = 0
2108 00:40:32.509250 Vddq = 0
2109 00:40:32.509669 Vmddr = 0
2110 00:40:32.515909 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2111 00:40:32.519038 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2112 00:40:32.522378 MEM_TYPE=3, freq_sel=15
2113 00:40:32.525663 sv_algorithm_assistance_LP4_1600
2114 00:40:32.529180 ============ PULL DRAM RESETB DOWN ============
2115 00:40:32.532568 ========== PULL DRAM RESETB DOWN end =========
2116 00:40:32.539221 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2117 00:40:32.542423 ===================================
2118 00:40:32.542815 LPDDR4 DRAM CONFIGURATION
2119 00:40:32.545607 ===================================
2120 00:40:32.548801 EX_ROW_EN[0] = 0x0
2121 00:40:32.552156 EX_ROW_EN[1] = 0x0
2122 00:40:32.552656 LP4Y_EN = 0x0
2123 00:40:32.555421 WORK_FSP = 0x0
2124 00:40:32.555899 WL = 0x4
2125 00:40:32.558921 RL = 0x4
2126 00:40:32.559375 BL = 0x2
2127 00:40:32.562315 RPST = 0x0
2128 00:40:32.562839 RD_PRE = 0x0
2129 00:40:32.565501 WR_PRE = 0x1
2130 00:40:32.565930 WR_PST = 0x0
2131 00:40:32.568830 DBI_WR = 0x0
2132 00:40:32.569219 DBI_RD = 0x0
2133 00:40:32.572210 OTF = 0x1
2134 00:40:32.575595 ===================================
2135 00:40:32.579011 ===================================
2136 00:40:32.579401 ANA top config
2137 00:40:32.582296 ===================================
2138 00:40:32.585898 DLL_ASYNC_EN = 0
2139 00:40:32.588864 ALL_SLAVE_EN = 0
2140 00:40:32.589260 NEW_RANK_MODE = 1
2141 00:40:32.592065 DLL_IDLE_MODE = 1
2142 00:40:32.595408 LP45_APHY_COMB_EN = 1
2143 00:40:32.599244 TX_ODT_DIS = 1
2144 00:40:32.602134 NEW_8X_MODE = 1
2145 00:40:32.605425 ===================================
2146 00:40:32.608834 ===================================
2147 00:40:32.609221 data_rate = 2400
2148 00:40:32.612129 CKR = 1
2149 00:40:32.615588 DQ_P2S_RATIO = 8
2150 00:40:32.619014 ===================================
2151 00:40:32.622252 CA_P2S_RATIO = 8
2152 00:40:32.625506 DQ_CA_OPEN = 0
2153 00:40:32.628633 DQ_SEMI_OPEN = 0
2154 00:40:32.629169 CA_SEMI_OPEN = 0
2155 00:40:32.631666 CA_FULL_RATE = 0
2156 00:40:32.635124 DQ_CKDIV4_EN = 0
2157 00:40:32.638566 CA_CKDIV4_EN = 0
2158 00:40:32.641938 CA_PREDIV_EN = 0
2159 00:40:32.645383 PH8_DLY = 17
2160 00:40:32.645820 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2161 00:40:32.648545 DQ_AAMCK_DIV = 4
2162 00:40:32.652312 CA_AAMCK_DIV = 4
2163 00:40:32.655309 CA_ADMCK_DIV = 4
2164 00:40:32.658970 DQ_TRACK_CA_EN = 0
2165 00:40:32.662096 CA_PICK = 1200
2166 00:40:32.662559 CA_MCKIO = 1200
2167 00:40:32.665330 MCKIO_SEMI = 0
2168 00:40:32.668859 PLL_FREQ = 2366
2169 00:40:32.672204 DQ_UI_PI_RATIO = 32
2170 00:40:32.675452 CA_UI_PI_RATIO = 0
2171 00:40:32.678815 ===================================
2172 00:40:32.682201 ===================================
2173 00:40:32.685698 memory_type:LPDDR4
2174 00:40:32.686180 GP_NUM : 10
2175 00:40:32.689334 SRAM_EN : 1
2176 00:40:32.689867 MD32_EN : 0
2177 00:40:32.692535 ===================================
2178 00:40:32.695519 [ANA_INIT] >>>>>>>>>>>>>>
2179 00:40:32.698901 <<<<<< [CONFIGURE PHASE]: ANA_TX
2180 00:40:32.702166 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2181 00:40:32.706131 ===================================
2182 00:40:32.709525 data_rate = 2400,PCW = 0X5b00
2183 00:40:32.712186 ===================================
2184 00:40:32.715576 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2185 00:40:32.719582 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2186 00:40:32.725441 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2187 00:40:32.732087 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2188 00:40:32.735853 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2189 00:40:32.738717 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2190 00:40:32.739262 [ANA_INIT] flow start
2191 00:40:32.742478 [ANA_INIT] PLL >>>>>>>>
2192 00:40:32.745877 [ANA_INIT] PLL <<<<<<<<
2193 00:40:32.746261 [ANA_INIT] MIDPI >>>>>>>>
2194 00:40:32.750504 [ANA_INIT] MIDPI <<<<<<<<
2195 00:40:32.752039 [ANA_INIT] DLL >>>>>>>>
2196 00:40:32.752643 [ANA_INIT] DLL <<<<<<<<
2197 00:40:32.756026 [ANA_INIT] flow end
2198 00:40:32.758662 ============ LP4 DIFF to SE enter ============
2199 00:40:32.762549 ============ LP4 DIFF to SE exit ============
2200 00:40:32.765606 [ANA_INIT] <<<<<<<<<<<<<
2201 00:40:32.769202 [Flow] Enable top DCM control >>>>>
2202 00:40:32.772342 [Flow] Enable top DCM control <<<<<
2203 00:40:32.775461 Enable DLL master slave shuffle
2204 00:40:32.782692 ==============================================================
2205 00:40:32.783123 Gating Mode config
2206 00:40:32.788893 ==============================================================
2207 00:40:32.789283 Config description:
2208 00:40:32.799812 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2209 00:40:32.806189 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2210 00:40:32.812709 SELPH_MODE 0: By rank 1: By Phase
2211 00:40:32.816185 ==============================================================
2212 00:40:32.819440 GAT_TRACK_EN = 1
2213 00:40:32.822627 RX_GATING_MODE = 2
2214 00:40:32.825765 RX_GATING_TRACK_MODE = 2
2215 00:40:32.829696 SELPH_MODE = 1
2216 00:40:32.833107 PICG_EARLY_EN = 1
2217 00:40:32.835690 VALID_LAT_VALUE = 1
2218 00:40:32.839163 ==============================================================
2219 00:40:32.842621 Enter into Gating configuration >>>>
2220 00:40:32.845854 Exit from Gating configuration <<<<
2221 00:40:32.849463 Enter into DVFS_PRE_config >>>>>
2222 00:40:32.862783 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2223 00:40:32.863241 Exit from DVFS_PRE_config <<<<<
2224 00:40:32.866281 Enter into PICG configuration >>>>
2225 00:40:32.868949 Exit from PICG configuration <<<<
2226 00:40:32.872442 [RX_INPUT] configuration >>>>>
2227 00:40:32.876163 [RX_INPUT] configuration <<<<<
2228 00:40:32.882539 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2229 00:40:32.885924 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2230 00:40:32.892620 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2231 00:40:32.899415 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2232 00:40:32.905738 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2233 00:40:32.912498 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2234 00:40:32.915815 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2235 00:40:32.919910 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2236 00:40:32.922730 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2237 00:40:32.929021 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2238 00:40:32.932760 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2239 00:40:32.936038 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2240 00:40:32.939529 ===================================
2241 00:40:32.942450 LPDDR4 DRAM CONFIGURATION
2242 00:40:32.945688 ===================================
2243 00:40:32.946190 EX_ROW_EN[0] = 0x0
2244 00:40:32.949215 EX_ROW_EN[1] = 0x0
2245 00:40:32.949733 LP4Y_EN = 0x0
2246 00:40:32.952721 WORK_FSP = 0x0
2247 00:40:32.953114 WL = 0x4
2248 00:40:32.956473 RL = 0x4
2249 00:40:32.959713 BL = 0x2
2250 00:40:32.960101 RPST = 0x0
2251 00:40:32.962681 RD_PRE = 0x0
2252 00:40:32.963066 WR_PRE = 0x1
2253 00:40:32.966155 WR_PST = 0x0
2254 00:40:32.966540 DBI_WR = 0x0
2255 00:40:32.969819 DBI_RD = 0x0
2256 00:40:32.970207 OTF = 0x1
2257 00:40:32.972481 ===================================
2258 00:40:32.975834 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2259 00:40:32.979402 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2260 00:40:32.985986 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2261 00:40:32.989838 ===================================
2262 00:40:32.993123 LPDDR4 DRAM CONFIGURATION
2263 00:40:32.996259 ===================================
2264 00:40:32.996646 EX_ROW_EN[0] = 0x10
2265 00:40:33.000013 EX_ROW_EN[1] = 0x0
2266 00:40:33.000410 LP4Y_EN = 0x0
2267 00:40:33.003081 WORK_FSP = 0x0
2268 00:40:33.003471 WL = 0x4
2269 00:40:33.006394 RL = 0x4
2270 00:40:33.006788 BL = 0x2
2271 00:40:33.009632 RPST = 0x0
2272 00:40:33.010026 RD_PRE = 0x0
2273 00:40:33.012811 WR_PRE = 0x1
2274 00:40:33.013218 WR_PST = 0x0
2275 00:40:33.016063 DBI_WR = 0x0
2276 00:40:33.016467 DBI_RD = 0x0
2277 00:40:33.019431 OTF = 0x1
2278 00:40:33.023178 ===================================
2279 00:40:33.029396 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2280 00:40:33.029996 ==
2281 00:40:33.032960 Dram Type= 6, Freq= 0, CH_0, rank 0
2282 00:40:33.036419 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2283 00:40:33.036815 ==
2284 00:40:33.039700 [Duty_Offset_Calibration]
2285 00:40:33.040088 B0:2 B1:1 CA:1
2286 00:40:33.040390
2287 00:40:33.043302 [DutyScan_Calibration_Flow] k_type=0
2288 00:40:33.053362
2289 00:40:33.053808 ==CLK 0==
2290 00:40:33.056864 Final CLK duty delay cell = 0
2291 00:40:33.060406 [0] MAX Duty = 5218%(X100), DQS PI = 24
2292 00:40:33.063683 [0] MIN Duty = 4875%(X100), DQS PI = 0
2293 00:40:33.064075 [0] AVG Duty = 5046%(X100)
2294 00:40:33.064383
2295 00:40:33.066808 CH0 CLK Duty spec in!! Max-Min= 343%
2296 00:40:33.073956 [DutyScan_Calibration_Flow] ====Done====
2297 00:40:33.074452
2298 00:40:33.076688 [DutyScan_Calibration_Flow] k_type=1
2299 00:40:33.091876
2300 00:40:33.092399 ==DQS 0 ==
2301 00:40:33.095041 Final DQS duty delay cell = -4
2302 00:40:33.098863 [-4] MAX Duty = 5124%(X100), DQS PI = 24
2303 00:40:33.102134 [-4] MIN Duty = 4751%(X100), DQS PI = 0
2304 00:40:33.105642 [-4] AVG Duty = 4937%(X100)
2305 00:40:33.106048
2306 00:40:33.106359 ==DQS 1 ==
2307 00:40:33.108900 Final DQS duty delay cell = 0
2308 00:40:33.112256 [0] MAX Duty = 5156%(X100), DQS PI = 62
2309 00:40:33.115548 [0] MIN Duty = 5000%(X100), DQS PI = 32
2310 00:40:33.118955 [0] AVG Duty = 5078%(X100)
2311 00:40:33.119438
2312 00:40:33.121822 CH0 DQS 0 Duty spec in!! Max-Min= 373%
2313 00:40:33.122159
2314 00:40:33.125569 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2315 00:40:33.128691 [DutyScan_Calibration_Flow] ====Done====
2316 00:40:33.128897
2317 00:40:33.131910 [DutyScan_Calibration_Flow] k_type=3
2318 00:40:33.148387
2319 00:40:33.148588 ==DQM 0 ==
2320 00:40:33.151835 Final DQM duty delay cell = 0
2321 00:40:33.155577 [0] MAX Duty = 5156%(X100), DQS PI = 28
2322 00:40:33.158731 [0] MIN Duty = 4875%(X100), DQS PI = 58
2323 00:40:33.158950 [0] AVG Duty = 5015%(X100)
2324 00:40:33.162058
2325 00:40:33.162286 ==DQM 1 ==
2326 00:40:33.165447 Final DQM duty delay cell = 0
2327 00:40:33.168704 [0] MAX Duty = 5093%(X100), DQS PI = 0
2328 00:40:33.171949 [0] MIN Duty = 5031%(X100), DQS PI = 16
2329 00:40:33.172251 [0] AVG Duty = 5062%(X100)
2330 00:40:33.172416
2331 00:40:33.178699 CH0 DQM 0 Duty spec in!! Max-Min= 281%
2332 00:40:33.179197
2333 00:40:33.181978 CH0 DQM 1 Duty spec in!! Max-Min= 62%
2334 00:40:33.185471 [DutyScan_Calibration_Flow] ====Done====
2335 00:40:33.185920
2336 00:40:33.188757 [DutyScan_Calibration_Flow] k_type=2
2337 00:40:33.205151
2338 00:40:33.205608 ==DQ 0 ==
2339 00:40:33.208833 Final DQ duty delay cell = 0
2340 00:40:33.211604 [0] MAX Duty = 5031%(X100), DQS PI = 28
2341 00:40:33.215463 [0] MIN Duty = 4844%(X100), DQS PI = 62
2342 00:40:33.215844 [0] AVG Duty = 4937%(X100)
2343 00:40:33.219129
2344 00:40:33.219585 ==DQ 1 ==
2345 00:40:33.221671 Final DQ duty delay cell = 0
2346 00:40:33.225535 [0] MAX Duty = 5093%(X100), DQS PI = 24
2347 00:40:33.228454 [0] MIN Duty = 4907%(X100), DQS PI = 36
2348 00:40:33.228836 [0] AVG Duty = 5000%(X100)
2349 00:40:33.229130
2350 00:40:33.232171 CH0 DQ 0 Duty spec in!! Max-Min= 187%
2351 00:40:33.235239
2352 00:40:33.235619 CH0 DQ 1 Duty spec in!! Max-Min= 186%
2353 00:40:33.241874 [DutyScan_Calibration_Flow] ====Done====
2354 00:40:33.242373 ==
2355 00:40:33.245393 Dram Type= 6, Freq= 0, CH_1, rank 0
2356 00:40:33.248900 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2357 00:40:33.249330 ==
2358 00:40:33.252309 [Duty_Offset_Calibration]
2359 00:40:33.252737 B0:1 B1:0 CA:0
2360 00:40:33.253047
2361 00:40:33.255183 [DutyScan_Calibration_Flow] k_type=0
2362 00:40:33.264291
2363 00:40:33.264804 ==CLK 0==
2364 00:40:33.267503 Final CLK duty delay cell = -4
2365 00:40:33.271228 [-4] MAX Duty = 5000%(X100), DQS PI = 20
2366 00:40:33.274390 [-4] MIN Duty = 4875%(X100), DQS PI = 50
2367 00:40:33.277602 [-4] AVG Duty = 4937%(X100)
2368 00:40:33.278100
2369 00:40:33.280973 CH1 CLK Duty spec in!! Max-Min= 125%
2370 00:40:33.284175 [DutyScan_Calibration_Flow] ====Done====
2371 00:40:33.284680
2372 00:40:33.287344 [DutyScan_Calibration_Flow] k_type=1
2373 00:40:33.304286
2374 00:40:33.304663 ==DQS 0 ==
2375 00:40:33.307523 Final DQS duty delay cell = 0
2376 00:40:33.310717 [0] MAX Duty = 5062%(X100), DQS PI = 22
2377 00:40:33.314139 [0] MIN Duty = 4844%(X100), DQS PI = 0
2378 00:40:33.314518 [0] AVG Duty = 4953%(X100)
2379 00:40:33.317446
2380 00:40:33.317886 ==DQS 1 ==
2381 00:40:33.321043 Final DQS duty delay cell = 0
2382 00:40:33.324205 [0] MAX Duty = 5218%(X100), DQS PI = 20
2383 00:40:33.327847 [0] MIN Duty = 4969%(X100), DQS PI = 10
2384 00:40:33.328229 [0] AVG Duty = 5093%(X100)
2385 00:40:33.330726
2386 00:40:33.334176 CH1 DQS 0 Duty spec in!! Max-Min= 218%
2387 00:40:33.334557
2388 00:40:33.337780 CH1 DQS 1 Duty spec in!! Max-Min= 249%
2389 00:40:33.340632 [DutyScan_Calibration_Flow] ====Done====
2390 00:40:33.341006
2391 00:40:33.344501 [DutyScan_Calibration_Flow] k_type=3
2392 00:40:33.360859
2393 00:40:33.361258 ==DQM 0 ==
2394 00:40:33.364390 Final DQM duty delay cell = 0
2395 00:40:33.367684 [0] MAX Duty = 5156%(X100), DQS PI = 8
2396 00:40:33.370571 [0] MIN Duty = 4969%(X100), DQS PI = 62
2397 00:40:33.370996 [0] AVG Duty = 5062%(X100)
2398 00:40:33.374315
2399 00:40:33.374688 ==DQM 1 ==
2400 00:40:33.377592 Final DQM duty delay cell = 0
2401 00:40:33.380783 [0] MAX Duty = 5031%(X100), DQS PI = 26
2402 00:40:33.383843 [0] MIN Duty = 4875%(X100), DQS PI = 36
2403 00:40:33.384341 [0] AVG Duty = 4953%(X100)
2404 00:40:33.387331
2405 00:40:33.390698 CH1 DQM 0 Duty spec in!! Max-Min= 187%
2406 00:40:33.391076
2407 00:40:33.394383 CH1 DQM 1 Duty spec in!! Max-Min= 156%
2408 00:40:33.397651 [DutyScan_Calibration_Flow] ====Done====
2409 00:40:33.398054
2410 00:40:33.401125 [DutyScan_Calibration_Flow] k_type=2
2411 00:40:33.416613
2412 00:40:33.416998 ==DQ 0 ==
2413 00:40:33.420044 Final DQ duty delay cell = -4
2414 00:40:33.423520 [-4] MAX Duty = 5094%(X100), DQS PI = 10
2415 00:40:33.426753 [-4] MIN Duty = 4906%(X100), DQS PI = 44
2416 00:40:33.430417 [-4] AVG Duty = 5000%(X100)
2417 00:40:33.430795
2418 00:40:33.431087 ==DQ 1 ==
2419 00:40:33.433372 Final DQ duty delay cell = 0
2420 00:40:33.437190 [0] MAX Duty = 5125%(X100), DQS PI = 20
2421 00:40:33.440702 [0] MIN Duty = 4938%(X100), DQS PI = 34
2422 00:40:33.441136 [0] AVG Duty = 5031%(X100)
2423 00:40:33.443520
2424 00:40:33.446830 CH1 DQ 0 Duty spec in!! Max-Min= 188%
2425 00:40:33.447213
2426 00:40:33.450371 CH1 DQ 1 Duty spec in!! Max-Min= 187%
2427 00:40:33.453150 [DutyScan_Calibration_Flow] ====Done====
2428 00:40:33.456703 nWR fixed to 30
2429 00:40:33.457092 [ModeRegInit_LP4] CH0 RK0
2430 00:40:33.459693 [ModeRegInit_LP4] CH0 RK1
2431 00:40:33.463456 [ModeRegInit_LP4] CH1 RK0
2432 00:40:33.466671 [ModeRegInit_LP4] CH1 RK1
2433 00:40:33.467053 match AC timing 7
2434 00:40:33.470102 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2435 00:40:33.476503 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2436 00:40:33.480168 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2437 00:40:33.486712 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2438 00:40:33.490072 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2439 00:40:33.490494 ==
2440 00:40:33.493822 Dram Type= 6, Freq= 0, CH_0, rank 0
2441 00:40:33.496999 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2442 00:40:33.497387 ==
2443 00:40:33.503262 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2444 00:40:33.507053 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2445 00:40:33.517145 [CA 0] Center 39 (8~70) winsize 63
2446 00:40:33.520443 [CA 1] Center 39 (8~70) winsize 63
2447 00:40:33.523935 [CA 2] Center 35 (5~66) winsize 62
2448 00:40:33.527331 [CA 3] Center 34 (4~65) winsize 62
2449 00:40:33.530171 [CA 4] Center 33 (3~64) winsize 62
2450 00:40:33.533745 [CA 5] Center 32 (3~62) winsize 60
2451 00:40:33.534360
2452 00:40:33.537230 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2453 00:40:33.537802
2454 00:40:33.540449 [CATrainingPosCal] consider 1 rank data
2455 00:40:33.544153 u2DelayCellTimex100 = 270/100 ps
2456 00:40:33.547295 CA0 delay=39 (8~70),Diff = 7 PI (33 cell)
2457 00:40:33.550942 CA1 delay=39 (8~70),Diff = 7 PI (33 cell)
2458 00:40:33.557058 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2459 00:40:33.560615 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2460 00:40:33.564141 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2461 00:40:33.567609 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2462 00:40:33.567999
2463 00:40:33.570909 CA PerBit enable=1, Macro0, CA PI delay=32
2464 00:40:33.571298
2465 00:40:33.573521 [CBTSetCACLKResult] CA Dly = 32
2466 00:40:33.573949 CS Dly: 6 (0~37)
2467 00:40:33.574252 ==
2468 00:40:33.577308 Dram Type= 6, Freq= 0, CH_0, rank 1
2469 00:40:33.584070 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2470 00:40:33.584544 ==
2471 00:40:33.587281 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2472 00:40:33.593917 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2473 00:40:33.602997 [CA 0] Center 38 (8~69) winsize 62
2474 00:40:33.606254 [CA 1] Center 38 (8~69) winsize 62
2475 00:40:33.609256 [CA 2] Center 35 (4~66) winsize 63
2476 00:40:33.612760 [CA 3] Center 34 (4~65) winsize 62
2477 00:40:33.616452 [CA 4] Center 33 (3~63) winsize 61
2478 00:40:33.619396 [CA 5] Center 32 (2~62) winsize 61
2479 00:40:33.619812
2480 00:40:33.622681 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2481 00:40:33.623070
2482 00:40:33.626276 [CATrainingPosCal] consider 2 rank data
2483 00:40:33.629438 u2DelayCellTimex100 = 270/100 ps
2484 00:40:33.632663 CA0 delay=38 (8~69),Diff = 6 PI (28 cell)
2485 00:40:33.636331 CA1 delay=38 (8~69),Diff = 6 PI (28 cell)
2486 00:40:33.639765 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2487 00:40:33.646598 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2488 00:40:33.649660 CA4 delay=33 (3~63),Diff = 1 PI (4 cell)
2489 00:40:33.653113 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2490 00:40:33.653837
2491 00:40:33.656769 CA PerBit enable=1, Macro0, CA PI delay=32
2492 00:40:33.657294
2493 00:40:33.659486 [CBTSetCACLKResult] CA Dly = 32
2494 00:40:33.660020 CS Dly: 7 (0~39)
2495 00:40:33.660359
2496 00:40:33.663025 ----->DramcWriteLeveling(PI) begin...
2497 00:40:33.663567 ==
2498 00:40:33.666573 Dram Type= 6, Freq= 0, CH_0, rank 0
2499 00:40:33.673437 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2500 00:40:33.673918 ==
2501 00:40:33.676262 Write leveling (Byte 0): 33 => 33
2502 00:40:33.679540 Write leveling (Byte 1): 29 => 29
2503 00:40:33.680100 DramcWriteLeveling(PI) end<-----
2504 00:40:33.682743
2505 00:40:33.683267 ==
2506 00:40:33.686131 Dram Type= 6, Freq= 0, CH_0, rank 0
2507 00:40:33.690179 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2508 00:40:33.690561 ==
2509 00:40:33.693466 [Gating] SW mode calibration
2510 00:40:33.699723 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2511 00:40:33.702912 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2512 00:40:33.709718 0 15 0 | B1->B0 | 2323 3333 | 0 1 | (0 0) (1 1)
2513 00:40:33.712885 0 15 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
2514 00:40:33.716582 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2515 00:40:33.723183 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2516 00:40:33.726113 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2517 00:40:33.730000 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2518 00:40:33.736042 0 15 24 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 1)
2519 00:40:33.739688 0 15 28 | B1->B0 | 3232 2424 | 1 0 | (1 1) (1 0)
2520 00:40:33.742786 1 0 0 | B1->B0 | 2a2a 2323 | 1 0 | (1 0) (0 0)
2521 00:40:33.749570 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2522 00:40:33.752828 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2523 00:40:33.756205 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2524 00:40:33.759475 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2525 00:40:33.766220 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2526 00:40:33.769639 1 0 24 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
2527 00:40:33.773138 1 0 28 | B1->B0 | 2e2e 4646 | 0 0 | (0 0) (0 0)
2528 00:40:33.779339 1 1 0 | B1->B0 | 3332 4646 | 1 0 | (0 0) (0 0)
2529 00:40:33.782813 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2530 00:40:33.786067 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2531 00:40:33.793201 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2532 00:40:33.796620 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2533 00:40:33.800121 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2534 00:40:33.806484 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2535 00:40:33.809937 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2536 00:40:33.813430 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2537 00:40:33.820046 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2538 00:40:33.823474 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2539 00:40:33.826811 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2540 00:40:33.829878 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2541 00:40:33.836532 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2542 00:40:33.840393 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2543 00:40:33.843685 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2544 00:40:33.850438 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2545 00:40:33.853514 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2546 00:40:33.857001 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2547 00:40:33.863355 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2548 00:40:33.867298 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2549 00:40:33.870578 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2550 00:40:33.876924 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2551 00:40:33.880322 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2552 00:40:33.883757 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2553 00:40:33.887186 Total UI for P1: 0, mck2ui 16
2554 00:40:33.890425 best dqsien dly found for B0: ( 1, 3, 28)
2555 00:40:33.894037 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2556 00:40:33.897488 Total UI for P1: 0, mck2ui 16
2557 00:40:33.900895 best dqsien dly found for B1: ( 1, 3, 30)
2558 00:40:33.903740 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2559 00:40:33.907240 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2560 00:40:33.910589
2561 00:40:33.914229 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2562 00:40:33.917256 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2563 00:40:33.920727 [Gating] SW calibration Done
2564 00:40:33.921157 ==
2565 00:40:33.924119 Dram Type= 6, Freq= 0, CH_0, rank 0
2566 00:40:33.927463 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2567 00:40:33.927993 ==
2568 00:40:33.928453 RX Vref Scan: 0
2569 00:40:33.928873
2570 00:40:33.930704 RX Vref 0 -> 0, step: 1
2571 00:40:33.931125
2572 00:40:33.934137 RX Delay -40 -> 252, step: 8
2573 00:40:33.937480 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2574 00:40:33.941028 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2575 00:40:33.947278 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2576 00:40:33.950383 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2577 00:40:33.953891 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2578 00:40:33.957656 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2579 00:40:33.960780 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2580 00:40:33.964329 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2581 00:40:33.970917 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2582 00:40:33.974147 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
2583 00:40:33.977665 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2584 00:40:33.980539 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2585 00:40:33.984456 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2586 00:40:33.990621 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2587 00:40:33.994087 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2588 00:40:33.997465 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2589 00:40:33.997948 ==
2590 00:40:34.000992 Dram Type= 6, Freq= 0, CH_0, rank 0
2591 00:40:34.004412 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2592 00:40:34.004922 ==
2593 00:40:34.007999 DQS Delay:
2594 00:40:34.008438 DQS0 = 0, DQS1 = 0
2595 00:40:34.010683 DQM Delay:
2596 00:40:34.011160 DQM0 = 121, DQM1 = 113
2597 00:40:34.014177 DQ Delay:
2598 00:40:34.017605 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2599 00:40:34.021017 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2600 00:40:34.024572 DQ8 =99, DQ9 =107, DQ10 =111, DQ11 =107
2601 00:40:34.027359 DQ12 =119, DQ13 =123, DQ14 =123, DQ15 =119
2602 00:40:34.027759
2603 00:40:34.028063
2604 00:40:34.028345 ==
2605 00:40:34.030807 Dram Type= 6, Freq= 0, CH_0, rank 0
2606 00:40:34.034696 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2607 00:40:34.035170 ==
2608 00:40:34.035546
2609 00:40:34.035849
2610 00:40:34.037834 TX Vref Scan disable
2611 00:40:34.041350 == TX Byte 0 ==
2612 00:40:34.044169 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2613 00:40:34.047591 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2614 00:40:34.051119 == TX Byte 1 ==
2615 00:40:34.054463 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2616 00:40:34.057828 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2617 00:40:34.058388 ==
2618 00:40:34.061070 Dram Type= 6, Freq= 0, CH_0, rank 0
2619 00:40:34.064160 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2620 00:40:34.064571 ==
2621 00:40:34.077844 TX Vref=22, minBit 0, minWin=25, winSum=406
2622 00:40:34.081019 TX Vref=24, minBit 0, minWin=25, winSum=413
2623 00:40:34.084615 TX Vref=26, minBit 0, minWin=26, winSum=425
2624 00:40:34.087777 TX Vref=28, minBit 0, minWin=26, winSum=424
2625 00:40:34.091374 TX Vref=30, minBit 0, minWin=26, winSum=425
2626 00:40:34.094688 TX Vref=32, minBit 13, minWin=25, winSum=420
2627 00:40:34.101010 [TxChooseVref] Worse bit 0, Min win 26, Win sum 425, Final Vref 26
2628 00:40:34.101405
2629 00:40:34.104875 Final TX Range 1 Vref 26
2630 00:40:34.105268
2631 00:40:34.105608 ==
2632 00:40:34.108481 Dram Type= 6, Freq= 0, CH_0, rank 0
2633 00:40:34.111602 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2634 00:40:34.112009 ==
2635 00:40:34.112478
2636 00:40:34.112960
2637 00:40:34.115191 TX Vref Scan disable
2638 00:40:34.117931 == TX Byte 0 ==
2639 00:40:34.121375 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2640 00:40:34.124809 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2641 00:40:34.128196 == TX Byte 1 ==
2642 00:40:34.131859 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2643 00:40:34.134629 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2644 00:40:34.135145
2645 00:40:34.138084 [DATLAT]
2646 00:40:34.138627 Freq=1200, CH0 RK0
2647 00:40:34.138998
2648 00:40:34.141258 DATLAT Default: 0xd
2649 00:40:34.141795 0, 0xFFFF, sum = 0
2650 00:40:34.144629 1, 0xFFFF, sum = 0
2651 00:40:34.145171 2, 0xFFFF, sum = 0
2652 00:40:34.148328 3, 0xFFFF, sum = 0
2653 00:40:34.148875 4, 0xFFFF, sum = 0
2654 00:40:34.151012 5, 0xFFFF, sum = 0
2655 00:40:34.151557 6, 0xFFFF, sum = 0
2656 00:40:34.154638 7, 0xFFFF, sum = 0
2657 00:40:34.155134 8, 0xFFFF, sum = 0
2658 00:40:34.158226 9, 0xFFFF, sum = 0
2659 00:40:34.158730 10, 0xFFFF, sum = 0
2660 00:40:34.161112 11, 0xFFFF, sum = 0
2661 00:40:34.161695 12, 0x0, sum = 1
2662 00:40:34.164542 13, 0x0, sum = 2
2663 00:40:34.165033 14, 0x0, sum = 3
2664 00:40:34.168079 15, 0x0, sum = 4
2665 00:40:34.168616 best_step = 13
2666 00:40:34.169096
2667 00:40:34.169501 ==
2668 00:40:34.171262 Dram Type= 6, Freq= 0, CH_0, rank 0
2669 00:40:34.177614 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2670 00:40:34.177998 ==
2671 00:40:34.178361 RX Vref Scan: 1
2672 00:40:34.178680
2673 00:40:34.181509 Set Vref Range= 32 -> 127
2674 00:40:34.181901
2675 00:40:34.184567 RX Vref 32 -> 127, step: 1
2676 00:40:34.184979
2677 00:40:34.187897 RX Delay -13 -> 252, step: 4
2678 00:40:34.188242
2679 00:40:34.191114 Set Vref, RX VrefLevel [Byte0]: 32
2680 00:40:34.191502 [Byte1]: 32
2681 00:40:34.195574
2682 00:40:34.195849 Set Vref, RX VrefLevel [Byte0]: 33
2683 00:40:34.199354 [Byte1]: 33
2684 00:40:34.203914
2685 00:40:34.207290 Set Vref, RX VrefLevel [Byte0]: 34
2686 00:40:34.207566 [Byte1]: 34
2687 00:40:34.211593
2688 00:40:34.211949 Set Vref, RX VrefLevel [Byte0]: 35
2689 00:40:34.214739 [Byte1]: 35
2690 00:40:34.219441
2691 00:40:34.219823 Set Vref, RX VrefLevel [Byte0]: 36
2692 00:40:34.222894 [Byte1]: 36
2693 00:40:34.227295
2694 00:40:34.227575 Set Vref, RX VrefLevel [Byte0]: 37
2695 00:40:34.230747 [Byte1]: 37
2696 00:40:34.235509
2697 00:40:34.235784 Set Vref, RX VrefLevel [Byte0]: 38
2698 00:40:34.238982 [Byte1]: 38
2699 00:40:34.243827
2700 00:40:34.244175 Set Vref, RX VrefLevel [Byte0]: 39
2701 00:40:34.247069 [Byte1]: 39
2702 00:40:34.251787
2703 00:40:34.252232 Set Vref, RX VrefLevel [Byte0]: 40
2704 00:40:34.254260 [Byte1]: 40
2705 00:40:34.259156
2706 00:40:34.259607 Set Vref, RX VrefLevel [Byte0]: 41
2707 00:40:34.262578 [Byte1]: 41
2708 00:40:34.266871
2709 00:40:34.267253 Set Vref, RX VrefLevel [Byte0]: 42
2710 00:40:34.270356 [Byte1]: 42
2711 00:40:34.275348
2712 00:40:34.275779 Set Vref, RX VrefLevel [Byte0]: 43
2713 00:40:34.278030 [Byte1]: 43
2714 00:40:34.282839
2715 00:40:34.283194 Set Vref, RX VrefLevel [Byte0]: 44
2716 00:40:34.286574 [Byte1]: 44
2717 00:40:34.290784
2718 00:40:34.291141 Set Vref, RX VrefLevel [Byte0]: 45
2719 00:40:34.294190 [Byte1]: 45
2720 00:40:34.298262
2721 00:40:34.298618 Set Vref, RX VrefLevel [Byte0]: 46
2722 00:40:34.302063 [Byte1]: 46
2723 00:40:34.306310
2724 00:40:34.306664 Set Vref, RX VrefLevel [Byte0]: 47
2725 00:40:34.309856 [Byte1]: 47
2726 00:40:34.314429
2727 00:40:34.314789 Set Vref, RX VrefLevel [Byte0]: 48
2728 00:40:34.317388 [Byte1]: 48
2729 00:40:34.322075
2730 00:40:34.322455 Set Vref, RX VrefLevel [Byte0]: 49
2731 00:40:34.325515 [Byte1]: 49
2732 00:40:34.330126
2733 00:40:34.330480 Set Vref, RX VrefLevel [Byte0]: 50
2734 00:40:34.333409 [Byte1]: 50
2735 00:40:34.337639
2736 00:40:34.338100 Set Vref, RX VrefLevel [Byte0]: 51
2737 00:40:34.341136 [Byte1]: 51
2738 00:40:34.345877
2739 00:40:34.346331 Set Vref, RX VrefLevel [Byte0]: 52
2740 00:40:34.349176 [Byte1]: 52
2741 00:40:34.353711
2742 00:40:34.354191 Set Vref, RX VrefLevel [Byte0]: 53
2743 00:40:34.356918 [Byte1]: 53
2744 00:40:34.361982
2745 00:40:34.362461 Set Vref, RX VrefLevel [Byte0]: 54
2746 00:40:34.364746 [Byte1]: 54
2747 00:40:34.369625
2748 00:40:34.370138 Set Vref, RX VrefLevel [Byte0]: 55
2749 00:40:34.373130 [Byte1]: 55
2750 00:40:34.377342
2751 00:40:34.377775 Set Vref, RX VrefLevel [Byte0]: 56
2752 00:40:34.380597 [Byte1]: 56
2753 00:40:34.385326
2754 00:40:34.385850 Set Vref, RX VrefLevel [Byte0]: 57
2755 00:40:34.388613 [Byte1]: 57
2756 00:40:34.393575
2757 00:40:34.394103 Set Vref, RX VrefLevel [Byte0]: 58
2758 00:40:34.396648 [Byte1]: 58
2759 00:40:34.401208
2760 00:40:34.401594 Set Vref, RX VrefLevel [Byte0]: 59
2761 00:40:34.404417 [Byte1]: 59
2762 00:40:34.408639
2763 00:40:34.409004 Set Vref, RX VrefLevel [Byte0]: 60
2764 00:40:34.412170 [Byte1]: 60
2765 00:40:34.416935
2766 00:40:34.417305 Set Vref, RX VrefLevel [Byte0]: 61
2767 00:40:34.420322 [Byte1]: 61
2768 00:40:34.424773
2769 00:40:34.425235 Set Vref, RX VrefLevel [Byte0]: 62
2770 00:40:34.428364 [Byte1]: 62
2771 00:40:34.432532
2772 00:40:34.432964 Set Vref, RX VrefLevel [Byte0]: 63
2773 00:40:34.435808 [Byte1]: 63
2774 00:40:34.440379
2775 00:40:34.440876 Set Vref, RX VrefLevel [Byte0]: 64
2776 00:40:34.443739 [Byte1]: 64
2777 00:40:34.448340
2778 00:40:34.448819 Set Vref, RX VrefLevel [Byte0]: 65
2779 00:40:34.451641 [Byte1]: 65
2780 00:40:34.456560
2781 00:40:34.456916 Set Vref, RX VrefLevel [Byte0]: 66
2782 00:40:34.459879 [Byte1]: 66
2783 00:40:34.464039
2784 00:40:34.464423 Set Vref, RX VrefLevel [Byte0]: 67
2785 00:40:34.470845 [Byte1]: 67
2786 00:40:34.471333
2787 00:40:34.474368 Set Vref, RX VrefLevel [Byte0]: 68
2788 00:40:34.477062 [Byte1]: 68
2789 00:40:34.477422
2790 00:40:34.481243 Set Vref, RX VrefLevel [Byte0]: 69
2791 00:40:34.483946 [Byte1]: 69
2792 00:40:34.487927
2793 00:40:34.488284 Final RX Vref Byte 0 = 55 to rank0
2794 00:40:34.491416 Final RX Vref Byte 1 = 50 to rank0
2795 00:40:34.494949 Final RX Vref Byte 0 = 55 to rank1
2796 00:40:34.497680 Final RX Vref Byte 1 = 50 to rank1==
2797 00:40:34.501198 Dram Type= 6, Freq= 0, CH_0, rank 0
2798 00:40:34.507645 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2799 00:40:34.508018 ==
2800 00:40:34.508300 DQS Delay:
2801 00:40:34.508564 DQS0 = 0, DQS1 = 0
2802 00:40:34.511305 DQM Delay:
2803 00:40:34.511659 DQM0 = 120, DQM1 = 112
2804 00:40:34.514554 DQ Delay:
2805 00:40:34.518070 DQ0 =120, DQ1 =120, DQ2 =120, DQ3 =118
2806 00:40:34.521679 DQ4 =122, DQ5 =112, DQ6 =126, DQ7 =124
2807 00:40:34.524865 DQ8 =100, DQ9 =102, DQ10 =112, DQ11 =106
2808 00:40:34.527645 DQ12 =116, DQ13 =116, DQ14 =124, DQ15 =120
2809 00:40:34.528114
2810 00:40:34.528443
2811 00:40:34.537948 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a13, (MSB)MR19= 0x404, tDQSOscB0 = 402 ps tDQSOscB1 = 400 ps
2812 00:40:34.538471 CH0 RK0: MR19=404, MR18=1A13
2813 00:40:34.544237 CH0_RK0: MR19=0x404, MR18=0x1A13, DQSOSC=400, MR23=63, INC=40, DEC=27
2814 00:40:34.544729
2815 00:40:34.548190 ----->DramcWriteLeveling(PI) begin...
2816 00:40:34.548549 ==
2817 00:40:34.550961 Dram Type= 6, Freq= 0, CH_0, rank 1
2818 00:40:34.554500 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2819 00:40:34.557529 ==
2820 00:40:34.558030 Write leveling (Byte 0): 32 => 32
2821 00:40:34.561387 Write leveling (Byte 1): 31 => 31
2822 00:40:34.564650 DramcWriteLeveling(PI) end<-----
2823 00:40:34.565107
2824 00:40:34.565399 ==
2825 00:40:34.568160 Dram Type= 6, Freq= 0, CH_0, rank 1
2826 00:40:34.574708 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2827 00:40:34.575083 ==
2828 00:40:34.575366 [Gating] SW mode calibration
2829 00:40:34.584614 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2830 00:40:34.588054 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2831 00:40:34.591143 0 15 0 | B1->B0 | 3434 3030 | 0 0 | (0 0) (0 0)
2832 00:40:34.597959 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2833 00:40:34.601318 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2834 00:40:34.604702 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2835 00:40:34.611311 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2836 00:40:34.614747 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2837 00:40:34.618201 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2838 00:40:34.624558 0 15 28 | B1->B0 | 2d2d 2929 | 0 0 | (0 1) (0 0)
2839 00:40:34.627814 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2840 00:40:34.631327 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2841 00:40:34.637981 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2842 00:40:34.641617 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2843 00:40:34.644975 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2844 00:40:34.651445 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2845 00:40:34.655300 1 0 24 | B1->B0 | 2828 2424 | 0 0 | (0 0) (1 1)
2846 00:40:34.658181 1 0 28 | B1->B0 | 4444 4141 | 0 0 | (0 0) (0 0)
2847 00:40:34.665227 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2848 00:40:34.668169 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2849 00:40:34.672019 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2850 00:40:34.675047 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2851 00:40:34.682008 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2852 00:40:34.684766 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2853 00:40:34.688259 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2854 00:40:34.694972 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
2855 00:40:34.698323 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2856 00:40:34.701576 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2857 00:40:34.708653 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2858 00:40:34.711931 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2859 00:40:34.715168 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2860 00:40:34.721509 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2861 00:40:34.725425 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2862 00:40:34.728623 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2863 00:40:34.731881 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2864 00:40:34.738850 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2865 00:40:34.741460 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2866 00:40:34.744930 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2867 00:40:34.751601 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2868 00:40:34.754865 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2869 00:40:34.758331 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2870 00:40:34.764950 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2871 00:40:34.768513 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
2872 00:40:34.771643 Total UI for P1: 0, mck2ui 16
2873 00:40:34.774975 best dqsien dly found for B1: ( 1, 3, 28)
2874 00:40:34.778317 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2875 00:40:34.782328 Total UI for P1: 0, mck2ui 16
2876 00:40:34.785363 best dqsien dly found for B0: ( 1, 3, 30)
2877 00:40:34.788592 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2878 00:40:34.791850 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2879 00:40:34.791966
2880 00:40:34.795420 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2881 00:40:34.801911 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2882 00:40:34.802051 [Gating] SW calibration Done
2883 00:40:34.802128 ==
2884 00:40:34.805400 Dram Type= 6, Freq= 0, CH_0, rank 1
2885 00:40:34.812308 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2886 00:40:34.812466 ==
2887 00:40:34.812555 RX Vref Scan: 0
2888 00:40:34.812634
2889 00:40:34.815349 RX Vref 0 -> 0, step: 1
2890 00:40:34.815462
2891 00:40:34.818756 RX Delay -40 -> 252, step: 8
2892 00:40:34.822178 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2893 00:40:34.825425 iDelay=200, Bit 1, Center 123 (56 ~ 191) 136
2894 00:40:34.828552 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2895 00:40:34.835908 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2896 00:40:34.839053 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2897 00:40:34.842576 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2898 00:40:34.845866 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2899 00:40:34.848927 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2900 00:40:34.852498 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2901 00:40:34.858882 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
2902 00:40:34.862343 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2903 00:40:34.865922 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2904 00:40:34.869373 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2905 00:40:34.872517 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2906 00:40:34.878885 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2907 00:40:34.882169 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
2908 00:40:34.882625 ==
2909 00:40:34.885424 Dram Type= 6, Freq= 0, CH_0, rank 1
2910 00:40:34.888625 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2911 00:40:34.889086 ==
2912 00:40:34.892336 DQS Delay:
2913 00:40:34.892810 DQS0 = 0, DQS1 = 0
2914 00:40:34.893120 DQM Delay:
2915 00:40:34.896017 DQM0 = 122, DQM1 = 112
2916 00:40:34.896464 DQ Delay:
2917 00:40:34.899176 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2918 00:40:34.902555 DQ4 =127, DQ5 =115, DQ6 =127, DQ7 =127
2919 00:40:34.905835 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
2920 00:40:34.912567 DQ12 =115, DQ13 =119, DQ14 =123, DQ15 =123
2921 00:40:34.913040
2922 00:40:34.913349
2923 00:40:34.913680 ==
2924 00:40:34.915880 Dram Type= 6, Freq= 0, CH_0, rank 1
2925 00:40:34.919278 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2926 00:40:34.919670 ==
2927 00:40:34.919974
2928 00:40:34.920251
2929 00:40:34.922772 TX Vref Scan disable
2930 00:40:34.923158 == TX Byte 0 ==
2931 00:40:34.929342 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2932 00:40:34.932563 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2933 00:40:34.933006 == TX Byte 1 ==
2934 00:40:34.938993 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2935 00:40:34.942324 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2936 00:40:34.942716 ==
2937 00:40:34.945607 Dram Type= 6, Freq= 0, CH_0, rank 1
2938 00:40:34.948699 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2939 00:40:34.949095 ==
2940 00:40:34.961771 TX Vref=22, minBit 1, minWin=25, winSum=416
2941 00:40:34.964960 TX Vref=24, minBit 1, minWin=25, winSum=413
2942 00:40:34.968115 TX Vref=26, minBit 1, minWin=25, winSum=420
2943 00:40:34.971919 TX Vref=28, minBit 10, minWin=25, winSum=423
2944 00:40:34.975178 TX Vref=30, minBit 12, minWin=25, winSum=423
2945 00:40:34.981903 TX Vref=32, minBit 0, minWin=26, winSum=422
2946 00:40:34.985245 [TxChooseVref] Worse bit 0, Min win 26, Win sum 422, Final Vref 32
2947 00:40:34.985665
2948 00:40:34.988716 Final TX Range 1 Vref 32
2949 00:40:34.989181
2950 00:40:34.989630 ==
2951 00:40:34.991870 Dram Type= 6, Freq= 0, CH_0, rank 1
2952 00:40:34.995549 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2953 00:40:34.998677 ==
2954 00:40:34.999160
2955 00:40:34.999520
2956 00:40:34.999805 TX Vref Scan disable
2957 00:40:35.002081 == TX Byte 0 ==
2958 00:40:35.005207 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2959 00:40:35.008394 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2960 00:40:35.012188 == TX Byte 1 ==
2961 00:40:35.015201 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2962 00:40:35.018470 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2963 00:40:35.022239
2964 00:40:35.022701 [DATLAT]
2965 00:40:35.023010 Freq=1200, CH0 RK1
2966 00:40:35.023294
2967 00:40:35.025349 DATLAT Default: 0xd
2968 00:40:35.025789 0, 0xFFFF, sum = 0
2969 00:40:35.028628 1, 0xFFFF, sum = 0
2970 00:40:35.029071 2, 0xFFFF, sum = 0
2971 00:40:35.032236 3, 0xFFFF, sum = 0
2972 00:40:35.032715 4, 0xFFFF, sum = 0
2973 00:40:35.034843 5, 0xFFFF, sum = 0
2974 00:40:35.038158 6, 0xFFFF, sum = 0
2975 00:40:35.038554 7, 0xFFFF, sum = 0
2976 00:40:35.041632 8, 0xFFFF, sum = 0
2977 00:40:35.042040 9, 0xFFFF, sum = 0
2978 00:40:35.045321 10, 0xFFFF, sum = 0
2979 00:40:35.045831 11, 0xFFFF, sum = 0
2980 00:40:35.048678 12, 0x0, sum = 1
2981 00:40:35.049166 13, 0x0, sum = 2
2982 00:40:35.051694 14, 0x0, sum = 3
2983 00:40:35.052101 15, 0x0, sum = 4
2984 00:40:35.052410 best_step = 13
2985 00:40:35.052690
2986 00:40:35.055339 ==
2987 00:40:35.058461 Dram Type= 6, Freq= 0, CH_0, rank 1
2988 00:40:35.061430 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2989 00:40:35.061868 ==
2990 00:40:35.062174 RX Vref Scan: 0
2991 00:40:35.062457
2992 00:40:35.065292 RX Vref 0 -> 0, step: 1
2993 00:40:35.065714
2994 00:40:35.068459 RX Delay -13 -> 252, step: 4
2995 00:40:35.071960 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
2996 00:40:35.075096 iDelay=195, Bit 1, Center 122 (55 ~ 190) 136
2997 00:40:35.081766 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
2998 00:40:35.085289 iDelay=195, Bit 3, Center 118 (51 ~ 186) 136
2999 00:40:35.088379 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
3000 00:40:35.091621 iDelay=195, Bit 5, Center 116 (51 ~ 182) 132
3001 00:40:35.095385 iDelay=195, Bit 6, Center 128 (63 ~ 194) 132
3002 00:40:35.101850 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3003 00:40:35.105054 iDelay=195, Bit 8, Center 100 (35 ~ 166) 132
3004 00:40:35.108217 iDelay=195, Bit 9, Center 98 (31 ~ 166) 136
3005 00:40:35.111722 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3006 00:40:35.114876 iDelay=195, Bit 11, Center 102 (39 ~ 166) 128
3007 00:40:35.121650 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
3008 00:40:35.124914 iDelay=195, Bit 13, Center 116 (55 ~ 178) 124
3009 00:40:35.128384 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3010 00:40:35.131882 iDelay=195, Bit 15, Center 120 (55 ~ 186) 132
3011 00:40:35.132348 ==
3012 00:40:35.135225 Dram Type= 6, Freq= 0, CH_0, rank 1
3013 00:40:35.142044 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3014 00:40:35.142513 ==
3015 00:40:35.142849 DQS Delay:
3016 00:40:35.144727 DQS0 = 0, DQS1 = 0
3017 00:40:35.145152 DQM Delay:
3018 00:40:35.148291 DQM0 = 121, DQM1 = 110
3019 00:40:35.148762 DQ Delay:
3020 00:40:35.151639 DQ0 =118, DQ1 =122, DQ2 =118, DQ3 =118
3021 00:40:35.154981 DQ4 =122, DQ5 =116, DQ6 =128, DQ7 =126
3022 00:40:35.158291 DQ8 =100, DQ9 =98, DQ10 =110, DQ11 =102
3023 00:40:35.161405 DQ12 =114, DQ13 =116, DQ14 =122, DQ15 =120
3024 00:40:35.161861
3025 00:40:35.162195
3026 00:40:35.171637 [DQSOSCAuto] RK1, (LSB)MR18= 0x11f2, (MSB)MR19= 0x403, tDQSOscB0 = 415 ps tDQSOscB1 = 403 ps
3027 00:40:35.172151 CH0 RK1: MR19=403, MR18=11F2
3028 00:40:35.178107 CH0_RK1: MR19=0x403, MR18=0x11F2, DQSOSC=403, MR23=63, INC=40, DEC=26
3029 00:40:35.181520 [RxdqsGatingPostProcess] freq 1200
3030 00:40:35.188255 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3031 00:40:35.191117 best DQS0 dly(2T, 0.5T) = (0, 11)
3032 00:40:35.194806 best DQS1 dly(2T, 0.5T) = (0, 11)
3033 00:40:35.198122 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3034 00:40:35.201151 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3035 00:40:35.204500 best DQS0 dly(2T, 0.5T) = (0, 11)
3036 00:40:35.207980 best DQS1 dly(2T, 0.5T) = (0, 11)
3037 00:40:35.208366 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3038 00:40:35.211128 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3039 00:40:35.214395 Pre-setting of DQS Precalculation
3040 00:40:35.221283 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3041 00:40:35.221816 ==
3042 00:40:35.224663 Dram Type= 6, Freq= 0, CH_1, rank 0
3043 00:40:35.228018 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3044 00:40:35.228408 ==
3045 00:40:35.234868 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3046 00:40:35.241242 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3047 00:40:35.248131 [CA 0] Center 37 (7~68) winsize 62
3048 00:40:35.251650 [CA 1] Center 37 (7~68) winsize 62
3049 00:40:35.254843 [CA 2] Center 35 (5~65) winsize 61
3050 00:40:35.258304 [CA 3] Center 34 (4~64) winsize 61
3051 00:40:35.261606 [CA 4] Center 34 (4~64) winsize 61
3052 00:40:35.265111 [CA 5] Center 33 (3~63) winsize 61
3053 00:40:35.265496
3054 00:40:35.268481 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3055 00:40:35.269087
3056 00:40:35.271688 [CATrainingPosCal] consider 1 rank data
3057 00:40:35.274688 u2DelayCellTimex100 = 270/100 ps
3058 00:40:35.278137 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3059 00:40:35.281884 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3060 00:40:35.288637 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3061 00:40:35.291541 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3062 00:40:35.294758 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3063 00:40:35.298007 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3064 00:40:35.298394
3065 00:40:35.301278 CA PerBit enable=1, Macro0, CA PI delay=33
3066 00:40:35.301827
3067 00:40:35.304765 [CBTSetCACLKResult] CA Dly = 33
3068 00:40:35.305242 CS Dly: 7 (0~38)
3069 00:40:35.308305 ==
3070 00:40:35.308775 Dram Type= 6, Freq= 0, CH_1, rank 1
3071 00:40:35.314469 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3072 00:40:35.314965 ==
3073 00:40:35.317923 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3074 00:40:35.324701 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3075 00:40:35.334207 [CA 0] Center 37 (7~68) winsize 62
3076 00:40:35.337341 [CA 1] Center 37 (7~68) winsize 62
3077 00:40:35.340836 [CA 2] Center 35 (5~65) winsize 61
3078 00:40:35.344168 [CA 3] Center 34 (4~65) winsize 62
3079 00:40:35.347649 [CA 4] Center 35 (5~65) winsize 61
3080 00:40:35.350954 [CA 5] Center 34 (4~64) winsize 61
3081 00:40:35.351419
3082 00:40:35.353877 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3083 00:40:35.354262
3084 00:40:35.357681 [CATrainingPosCal] consider 2 rank data
3085 00:40:35.360520 u2DelayCellTimex100 = 270/100 ps
3086 00:40:35.363810 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3087 00:40:35.367453 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3088 00:40:35.374235 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3089 00:40:35.377534 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3090 00:40:35.380916 CA4 delay=34 (5~64),Diff = 1 PI (4 cell)
3091 00:40:35.384335 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3092 00:40:35.384717
3093 00:40:35.387429 CA PerBit enable=1, Macro0, CA PI delay=33
3094 00:40:35.387813
3095 00:40:35.390499 [CBTSetCACLKResult] CA Dly = 33
3096 00:40:35.390882 CS Dly: 8 (0~40)
3097 00:40:35.391178
3098 00:40:35.393767 ----->DramcWriteLeveling(PI) begin...
3099 00:40:35.397165 ==
3100 00:40:35.400564 Dram Type= 6, Freq= 0, CH_1, rank 0
3101 00:40:35.403871 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3102 00:40:35.404301 ==
3103 00:40:35.407163 Write leveling (Byte 0): 25 => 25
3104 00:40:35.410300 Write leveling (Byte 1): 29 => 29
3105 00:40:35.413655 DramcWriteLeveling(PI) end<-----
3106 00:40:35.414039
3107 00:40:35.414337 ==
3108 00:40:35.416972 Dram Type= 6, Freq= 0, CH_1, rank 0
3109 00:40:35.420514 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3110 00:40:35.420959 ==
3111 00:40:35.423880 [Gating] SW mode calibration
3112 00:40:35.430255 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3113 00:40:35.436963 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3114 00:40:35.440363 0 15 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
3115 00:40:35.443656 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3116 00:40:35.450322 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3117 00:40:35.452977 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3118 00:40:35.456375 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3119 00:40:35.463156 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3120 00:40:35.466440 0 15 24 | B1->B0 | 3030 2c2c | 1 0 | (1 0) (0 0)
3121 00:40:35.469512 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
3122 00:40:35.476220 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3123 00:40:35.480003 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3124 00:40:35.483348 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3125 00:40:35.489832 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3126 00:40:35.492908 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3127 00:40:35.496210 1 0 20 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
3128 00:40:35.502965 1 0 24 | B1->B0 | 2e2e 3c3c | 0 0 | (0 0) (0 0)
3129 00:40:35.506312 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3130 00:40:35.509186 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3131 00:40:35.512841 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3132 00:40:35.519222 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3133 00:40:35.522658 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3134 00:40:35.526015 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3135 00:40:35.532754 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3136 00:40:35.536118 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3137 00:40:35.539592 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3138 00:40:35.545671 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3139 00:40:35.549244 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3140 00:40:35.552624 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3141 00:40:35.559255 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3142 00:40:35.562573 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3143 00:40:35.565869 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3144 00:40:35.572669 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3145 00:40:35.575938 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3146 00:40:35.579596 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3147 00:40:35.586171 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3148 00:40:35.589770 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3149 00:40:35.592253 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3150 00:40:35.599064 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3151 00:40:35.602237 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3152 00:40:35.606063 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3153 00:40:35.612206 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3154 00:40:35.612591 Total UI for P1: 0, mck2ui 16
3155 00:40:35.619146 best dqsien dly found for B0: ( 1, 3, 24)
3156 00:40:35.619553 Total UI for P1: 0, mck2ui 16
3157 00:40:35.622238 best dqsien dly found for B1: ( 1, 3, 24)
3158 00:40:35.628796 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3159 00:40:35.632184 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3160 00:40:35.632567
3161 00:40:35.636141 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3162 00:40:35.639411 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3163 00:40:35.642657 [Gating] SW calibration Done
3164 00:40:35.643204 ==
3165 00:40:35.645982 Dram Type= 6, Freq= 0, CH_1, rank 0
3166 00:40:35.649171 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3167 00:40:35.649737 ==
3168 00:40:35.652043 RX Vref Scan: 0
3169 00:40:35.652426
3170 00:40:35.652719 RX Vref 0 -> 0, step: 1
3171 00:40:35.652996
3172 00:40:35.655748 RX Delay -40 -> 252, step: 8
3173 00:40:35.659065 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3174 00:40:35.665326 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3175 00:40:35.668938 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3176 00:40:35.672735 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3177 00:40:35.675393 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3178 00:40:35.678822 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3179 00:40:35.685600 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3180 00:40:35.688955 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3181 00:40:35.692322 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3182 00:40:35.695678 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3183 00:40:35.698789 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3184 00:40:35.705501 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3185 00:40:35.708766 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3186 00:40:35.712036 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3187 00:40:35.715389 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3188 00:40:35.718891 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3189 00:40:35.719283 ==
3190 00:40:35.722131 Dram Type= 6, Freq= 0, CH_1, rank 0
3191 00:40:35.729164 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3192 00:40:35.729591 ==
3193 00:40:35.729914 DQS Delay:
3194 00:40:35.732895 DQS0 = 0, DQS1 = 0
3195 00:40:35.733376 DQM Delay:
3196 00:40:35.735313 DQM0 = 119, DQM1 = 116
3197 00:40:35.735698 DQ Delay:
3198 00:40:35.738790 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3199 00:40:35.742643 DQ4 =119, DQ5 =127, DQ6 =127, DQ7 =119
3200 00:40:35.745253 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =111
3201 00:40:35.748533 DQ12 =123, DQ13 =127, DQ14 =123, DQ15 =123
3202 00:40:35.748919
3203 00:40:35.749217
3204 00:40:35.749490 ==
3205 00:40:35.752359 Dram Type= 6, Freq= 0, CH_1, rank 0
3206 00:40:35.758911 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3207 00:40:35.759322 ==
3208 00:40:35.759795
3209 00:40:35.760095
3210 00:40:35.760502 TX Vref Scan disable
3211 00:40:35.762054 == TX Byte 0 ==
3212 00:40:35.765185 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3213 00:40:35.772256 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3214 00:40:35.772964 == TX Byte 1 ==
3215 00:40:35.775265 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3216 00:40:35.781911 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3217 00:40:35.782305 ==
3218 00:40:35.785350 Dram Type= 6, Freq= 0, CH_1, rank 0
3219 00:40:35.788116 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3220 00:40:35.788626 ==
3221 00:40:35.800198 TX Vref=22, minBit 9, minWin=24, winSum=412
3222 00:40:35.803509 TX Vref=24, minBit 11, minWin=24, winSum=417
3223 00:40:35.806665 TX Vref=26, minBit 9, minWin=25, winSum=425
3224 00:40:35.810217 TX Vref=28, minBit 1, minWin=26, winSum=427
3225 00:40:35.813473 TX Vref=30, minBit 2, minWin=26, winSum=429
3226 00:40:35.819909 TX Vref=32, minBit 1, minWin=26, winSum=429
3227 00:40:35.823219 [TxChooseVref] Worse bit 2, Min win 26, Win sum 429, Final Vref 30
3228 00:40:35.823680
3229 00:40:35.826695 Final TX Range 1 Vref 30
3230 00:40:35.827084
3231 00:40:35.827471 ==
3232 00:40:35.829757 Dram Type= 6, Freq= 0, CH_1, rank 0
3233 00:40:35.833173 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3234 00:40:35.833591 ==
3235 00:40:35.836160
3236 00:40:35.836539
3237 00:40:35.836839 TX Vref Scan disable
3238 00:40:35.839455 == TX Byte 0 ==
3239 00:40:35.842830 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3240 00:40:35.849495 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3241 00:40:35.849915 == TX Byte 1 ==
3242 00:40:35.853021 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3243 00:40:35.859846 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3244 00:40:35.860320
3245 00:40:35.860621 [DATLAT]
3246 00:40:35.860903 Freq=1200, CH1 RK0
3247 00:40:35.861171
3248 00:40:35.863014 DATLAT Default: 0xd
3249 00:40:35.863402 0, 0xFFFF, sum = 0
3250 00:40:35.866408 1, 0xFFFF, sum = 0
3251 00:40:35.869847 2, 0xFFFF, sum = 0
3252 00:40:35.870236 3, 0xFFFF, sum = 0
3253 00:40:35.872677 4, 0xFFFF, sum = 0
3254 00:40:35.873067 5, 0xFFFF, sum = 0
3255 00:40:35.875972 6, 0xFFFF, sum = 0
3256 00:40:35.876360 7, 0xFFFF, sum = 0
3257 00:40:35.879636 8, 0xFFFF, sum = 0
3258 00:40:35.880023 9, 0xFFFF, sum = 0
3259 00:40:35.882753 10, 0xFFFF, sum = 0
3260 00:40:35.883143 11, 0xFFFF, sum = 0
3261 00:40:35.886644 12, 0x0, sum = 1
3262 00:40:35.887033 13, 0x0, sum = 2
3263 00:40:35.889577 14, 0x0, sum = 3
3264 00:40:35.889972 15, 0x0, sum = 4
3265 00:40:35.892761 best_step = 13
3266 00:40:35.893174
3267 00:40:35.893489 ==
3268 00:40:35.896046 Dram Type= 6, Freq= 0, CH_1, rank 0
3269 00:40:35.899662 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3270 00:40:35.900048 ==
3271 00:40:35.900351 RX Vref Scan: 1
3272 00:40:35.900629
3273 00:40:35.902628 Set Vref Range= 32 -> 127
3274 00:40:35.903020
3275 00:40:35.906039 RX Vref 32 -> 127, step: 1
3276 00:40:35.906421
3277 00:40:35.909391 RX Delay -5 -> 252, step: 4
3278 00:40:35.909806
3279 00:40:35.913299 Set Vref, RX VrefLevel [Byte0]: 32
3280 00:40:35.916487 [Byte1]: 32
3281 00:40:35.916872
3282 00:40:35.919266 Set Vref, RX VrefLevel [Byte0]: 33
3283 00:40:35.922794 [Byte1]: 33
3284 00:40:35.926432
3285 00:40:35.926818 Set Vref, RX VrefLevel [Byte0]: 34
3286 00:40:35.929721 [Byte1]: 34
3287 00:40:35.933845
3288 00:40:35.934229 Set Vref, RX VrefLevel [Byte0]: 35
3289 00:40:35.937232 [Byte1]: 35
3290 00:40:35.941734
3291 00:40:35.942243 Set Vref, RX VrefLevel [Byte0]: 36
3292 00:40:35.944810 [Byte1]: 36
3293 00:40:35.949629
3294 00:40:35.950056 Set Vref, RX VrefLevel [Byte0]: 37
3295 00:40:35.954804 [Byte1]: 37
3296 00:40:35.957594
3297 00:40:35.958017 Set Vref, RX VrefLevel [Byte0]: 38
3298 00:40:35.960923 [Byte1]: 38
3299 00:40:35.965046
3300 00:40:35.965430 Set Vref, RX VrefLevel [Byte0]: 39
3301 00:40:35.968823 [Byte1]: 39
3302 00:40:35.973440
3303 00:40:35.974009 Set Vref, RX VrefLevel [Byte0]: 40
3304 00:40:35.976211 [Byte1]: 40
3305 00:40:35.981017
3306 00:40:35.981604 Set Vref, RX VrefLevel [Byte0]: 41
3307 00:40:35.987137 [Byte1]: 41
3308 00:40:35.987672
3309 00:40:35.990537 Set Vref, RX VrefLevel [Byte0]: 42
3310 00:40:35.993807 [Byte1]: 42
3311 00:40:35.994257
3312 00:40:35.997494 Set Vref, RX VrefLevel [Byte0]: 43
3313 00:40:36.000591 [Byte1]: 43
3314 00:40:36.003868
3315 00:40:36.003942 Set Vref, RX VrefLevel [Byte0]: 44
3316 00:40:36.007258 [Byte1]: 44
3317 00:40:36.011623
3318 00:40:36.011697 Set Vref, RX VrefLevel [Byte0]: 45
3319 00:40:36.015531 [Byte1]: 45
3320 00:40:36.019852
3321 00:40:36.019925 Set Vref, RX VrefLevel [Byte0]: 46
3322 00:40:36.023196 [Byte1]: 46
3323 00:40:36.027871
3324 00:40:36.027944 Set Vref, RX VrefLevel [Byte0]: 47
3325 00:40:36.030758 [Byte1]: 47
3326 00:40:36.035778
3327 00:40:36.035845 Set Vref, RX VrefLevel [Byte0]: 48
3328 00:40:36.039048 [Byte1]: 48
3329 00:40:36.043393
3330 00:40:36.043481 Set Vref, RX VrefLevel [Byte0]: 49
3331 00:40:36.046661 [Byte1]: 49
3332 00:40:36.051445
3333 00:40:36.051514 Set Vref, RX VrefLevel [Byte0]: 50
3334 00:40:36.054344 [Byte1]: 50
3335 00:40:36.059178
3336 00:40:36.059245 Set Vref, RX VrefLevel [Byte0]: 51
3337 00:40:36.062539 [Byte1]: 51
3338 00:40:36.066744
3339 00:40:36.066818 Set Vref, RX VrefLevel [Byte0]: 52
3340 00:40:36.070004 [Byte1]: 52
3341 00:40:36.074588
3342 00:40:36.074661 Set Vref, RX VrefLevel [Byte0]: 53
3343 00:40:36.077729 [Byte1]: 53
3344 00:40:36.082419
3345 00:40:36.085772 Set Vref, RX VrefLevel [Byte0]: 54
3346 00:40:36.089008 [Byte1]: 54
3347 00:40:36.089077
3348 00:40:36.092388 Set Vref, RX VrefLevel [Byte0]: 55
3349 00:40:36.095735 [Byte1]: 55
3350 00:40:36.095801
3351 00:40:36.099087 Set Vref, RX VrefLevel [Byte0]: 56
3352 00:40:36.102427 [Byte1]: 56
3353 00:40:36.105834
3354 00:40:36.105906 Set Vref, RX VrefLevel [Byte0]: 57
3355 00:40:36.109182 [Byte1]: 57
3356 00:40:36.114023
3357 00:40:36.114091 Set Vref, RX VrefLevel [Byte0]: 58
3358 00:40:36.117415 [Byte1]: 58
3359 00:40:36.122217
3360 00:40:36.122283 Set Vref, RX VrefLevel [Byte0]: 59
3361 00:40:36.125007 [Byte1]: 59
3362 00:40:36.129758
3363 00:40:36.129824 Set Vref, RX VrefLevel [Byte0]: 60
3364 00:40:36.132952 [Byte1]: 60
3365 00:40:36.137504
3366 00:40:36.137576 Set Vref, RX VrefLevel [Byte0]: 61
3367 00:40:36.140647 [Byte1]: 61
3368 00:40:36.145125
3369 00:40:36.145194 Set Vref, RX VrefLevel [Byte0]: 62
3370 00:40:36.148392 [Byte1]: 62
3371 00:40:36.153521
3372 00:40:36.153631 Set Vref, RX VrefLevel [Byte0]: 63
3373 00:40:36.156528 [Byte1]: 63
3374 00:40:36.161156
3375 00:40:36.161254 Set Vref, RX VrefLevel [Byte0]: 64
3376 00:40:36.164070 [Byte1]: 64
3377 00:40:36.168953
3378 00:40:36.169016 Set Vref, RX VrefLevel [Byte0]: 65
3379 00:40:36.172295 [Byte1]: 65
3380 00:40:36.176626
3381 00:40:36.176716 Set Vref, RX VrefLevel [Byte0]: 66
3382 00:40:36.180079 [Byte1]: 66
3383 00:40:36.184528
3384 00:40:36.184623 Set Vref, RX VrefLevel [Byte0]: 67
3385 00:40:36.187756 [Byte1]: 67
3386 00:40:36.192666
3387 00:40:36.192736 Set Vref, RX VrefLevel [Byte0]: 68
3388 00:40:36.196144 [Byte1]: 68
3389 00:40:36.200137
3390 00:40:36.200201 Set Vref, RX VrefLevel [Byte0]: 69
3391 00:40:36.203606 [Byte1]: 69
3392 00:40:36.208131
3393 00:40:36.208195 Final RX Vref Byte 0 = 56 to rank0
3394 00:40:36.211245 Final RX Vref Byte 1 = 52 to rank0
3395 00:40:36.215160 Final RX Vref Byte 0 = 56 to rank1
3396 00:40:36.217923 Final RX Vref Byte 1 = 52 to rank1==
3397 00:40:36.221256 Dram Type= 6, Freq= 0, CH_1, rank 0
3398 00:40:36.228037 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3399 00:40:36.228110 ==
3400 00:40:36.228167 DQS Delay:
3401 00:40:36.228219 DQS0 = 0, DQS1 = 0
3402 00:40:36.231466 DQM Delay:
3403 00:40:36.231534 DQM0 = 120, DQM1 = 117
3404 00:40:36.234868 DQ Delay:
3405 00:40:36.238323 DQ0 =124, DQ1 =114, DQ2 =110, DQ3 =118
3406 00:40:36.241380 DQ4 =122, DQ5 =128, DQ6 =128, DQ7 =122
3407 00:40:36.245137 DQ8 =104, DQ9 =108, DQ10 =118, DQ11 =112
3408 00:40:36.248306 DQ12 =126, DQ13 =124, DQ14 =124, DQ15 =126
3409 00:40:36.248380
3410 00:40:36.248451
3411 00:40:36.254829 [DQSOSCAuto] RK0, (LSB)MR18= 0x518, (MSB)MR19= 0x404, tDQSOscB0 = 400 ps tDQSOscB1 = 408 ps
3412 00:40:36.258342 CH1 RK0: MR19=404, MR18=518
3413 00:40:36.265266 CH1_RK0: MR19=0x404, MR18=0x518, DQSOSC=400, MR23=63, INC=40, DEC=27
3414 00:40:36.265369
3415 00:40:36.268645 ----->DramcWriteLeveling(PI) begin...
3416 00:40:36.268721 ==
3417 00:40:36.271349 Dram Type= 6, Freq= 0, CH_1, rank 1
3418 00:40:36.274828 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3419 00:40:36.274914 ==
3420 00:40:36.278516 Write leveling (Byte 0): 28 => 28
3421 00:40:36.281523 Write leveling (Byte 1): 29 => 29
3422 00:40:36.284774 DramcWriteLeveling(PI) end<-----
3423 00:40:36.284861
3424 00:40:36.284960 ==
3425 00:40:36.288008 Dram Type= 6, Freq= 0, CH_1, rank 1
3426 00:40:36.294987 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3427 00:40:36.295095 ==
3428 00:40:36.295168 [Gating] SW mode calibration
3429 00:40:36.304695 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3430 00:40:36.307982 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3431 00:40:36.311419 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3432 00:40:36.318117 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3433 00:40:36.321825 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3434 00:40:36.325004 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3435 00:40:36.331209 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3436 00:40:36.334649 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3437 00:40:36.337999 0 15 24 | B1->B0 | 2525 3232 | 1 1 | (1 0) (1 0)
3438 00:40:36.344708 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
3439 00:40:36.348166 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3440 00:40:36.351772 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3441 00:40:36.358033 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3442 00:40:36.361357 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3443 00:40:36.364765 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3444 00:40:36.371516 1 0 20 | B1->B0 | 2828 2323 | 0 0 | (1 1) (0 0)
3445 00:40:36.374902 1 0 24 | B1->B0 | 3d3d 2828 | 0 1 | (1 1) (0 0)
3446 00:40:36.378313 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3447 00:40:36.385031 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3448 00:40:36.388338 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3449 00:40:36.391060 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3450 00:40:36.397839 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3451 00:40:36.401142 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3452 00:40:36.404908 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3453 00:40:36.408155 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3454 00:40:36.414558 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3455 00:40:36.418123 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3456 00:40:36.421071 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3457 00:40:36.428102 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3458 00:40:36.431276 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3459 00:40:36.434598 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3460 00:40:36.441460 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3461 00:40:36.444597 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3462 00:40:36.448250 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3463 00:40:36.454819 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3464 00:40:36.458046 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3465 00:40:36.461714 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3466 00:40:36.467924 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3467 00:40:36.471208 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3468 00:40:36.475189 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3469 00:40:36.481265 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3470 00:40:36.484795 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3471 00:40:36.488332 Total UI for P1: 0, mck2ui 16
3472 00:40:36.491594 best dqsien dly found for B1: ( 1, 3, 22)
3473 00:40:36.494855 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3474 00:40:36.498293 Total UI for P1: 0, mck2ui 16
3475 00:40:36.501809 best dqsien dly found for B0: ( 1, 3, 28)
3476 00:40:36.504750 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3477 00:40:36.508138 best DQS1 dly(MCK, UI, PI) = (1, 3, 22)
3478 00:40:36.508206
3479 00:40:36.511609 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3480 00:40:36.518291 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 22)
3481 00:40:36.518361 [Gating] SW calibration Done
3482 00:40:36.518418 ==
3483 00:40:36.521616 Dram Type= 6, Freq= 0, CH_1, rank 1
3484 00:40:36.527734 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3485 00:40:36.527815 ==
3486 00:40:36.527873 RX Vref Scan: 0
3487 00:40:36.527927
3488 00:40:36.531207 RX Vref 0 -> 0, step: 1
3489 00:40:36.531276
3490 00:40:36.534437 RX Delay -40 -> 252, step: 8
3491 00:40:36.537735 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3492 00:40:36.541072 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3493 00:40:36.544329 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3494 00:40:36.551040 iDelay=200, Bit 3, Center 119 (56 ~ 183) 128
3495 00:40:36.554787 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3496 00:40:36.557945 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3497 00:40:36.560832 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3498 00:40:36.564702 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
3499 00:40:36.567562 iDelay=200, Bit 8, Center 107 (40 ~ 175) 136
3500 00:40:36.574255 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3501 00:40:36.577948 iDelay=200, Bit 10, Center 119 (48 ~ 191) 144
3502 00:40:36.580917 iDelay=200, Bit 11, Center 115 (48 ~ 183) 136
3503 00:40:36.584693 iDelay=200, Bit 12, Center 127 (56 ~ 199) 144
3504 00:40:36.591408 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3505 00:40:36.594261 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3506 00:40:36.597634 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3507 00:40:36.597707 ==
3508 00:40:36.600942 Dram Type= 6, Freq= 0, CH_1, rank 1
3509 00:40:36.604375 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3510 00:40:36.604443 ==
3511 00:40:36.607637 DQS Delay:
3512 00:40:36.607703 DQS0 = 0, DQS1 = 0
3513 00:40:36.611181 DQM Delay:
3514 00:40:36.611246 DQM0 = 120, DQM1 = 118
3515 00:40:36.611305 DQ Delay:
3516 00:40:36.614593 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3517 00:40:36.621201 DQ4 =115, DQ5 =131, DQ6 =131, DQ7 =123
3518 00:40:36.624581 DQ8 =107, DQ9 =107, DQ10 =119, DQ11 =115
3519 00:40:36.627354 DQ12 =127, DQ13 =127, DQ14 =123, DQ15 =123
3520 00:40:36.627421
3521 00:40:36.627477
3522 00:40:36.627529 ==
3523 00:40:36.630709 Dram Type= 6, Freq= 0, CH_1, rank 1
3524 00:40:36.633987 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3525 00:40:36.634054 ==
3526 00:40:36.634110
3527 00:40:36.634161
3528 00:40:36.637368 TX Vref Scan disable
3529 00:40:36.640639 == TX Byte 0 ==
3530 00:40:36.644617 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3531 00:40:36.647739 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3532 00:40:36.651092 == TX Byte 1 ==
3533 00:40:36.654456 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3534 00:40:36.657871 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3535 00:40:36.657939 ==
3536 00:40:36.661302 Dram Type= 6, Freq= 0, CH_1, rank 1
3537 00:40:36.664798 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3538 00:40:36.664868 ==
3539 00:40:36.677666 TX Vref=22, minBit 1, minWin=25, winSum=416
3540 00:40:36.680311 TX Vref=24, minBit 1, minWin=25, winSum=421
3541 00:40:36.683989 TX Vref=26, minBit 0, minWin=26, winSum=427
3542 00:40:36.687332 TX Vref=28, minBit 1, minWin=26, winSum=431
3543 00:40:36.690445 TX Vref=30, minBit 2, minWin=26, winSum=433
3544 00:40:36.697131 TX Vref=32, minBit 1, minWin=26, winSum=431
3545 00:40:36.700272 [TxChooseVref] Worse bit 2, Min win 26, Win sum 433, Final Vref 30
3546 00:40:36.700347
3547 00:40:36.703784 Final TX Range 1 Vref 30
3548 00:40:36.703859
3549 00:40:36.703917 ==
3550 00:40:36.707247 Dram Type= 6, Freq= 0, CH_1, rank 1
3551 00:40:36.710757 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3552 00:40:36.710833 ==
3553 00:40:36.710891
3554 00:40:36.710943
3555 00:40:36.714277 TX Vref Scan disable
3556 00:40:36.717991 == TX Byte 0 ==
3557 00:40:36.721243 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3558 00:40:36.724460 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3559 00:40:36.727721 == TX Byte 1 ==
3560 00:40:36.731119 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3561 00:40:36.734554 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3562 00:40:36.734655
3563 00:40:36.737880 [DATLAT]
3564 00:40:36.737965 Freq=1200, CH1 RK1
3565 00:40:36.738037
3566 00:40:36.740936 DATLAT Default: 0xd
3567 00:40:36.741041 0, 0xFFFF, sum = 0
3568 00:40:36.744432 1, 0xFFFF, sum = 0
3569 00:40:36.744541 2, 0xFFFF, sum = 0
3570 00:40:36.747297 3, 0xFFFF, sum = 0
3571 00:40:36.747378 4, 0xFFFF, sum = 0
3572 00:40:36.751032 5, 0xFFFF, sum = 0
3573 00:40:36.751108 6, 0xFFFF, sum = 0
3574 00:40:36.754292 7, 0xFFFF, sum = 0
3575 00:40:36.754387 8, 0xFFFF, sum = 0
3576 00:40:36.757732 9, 0xFFFF, sum = 0
3577 00:40:36.757808 10, 0xFFFF, sum = 0
3578 00:40:36.761195 11, 0xFFFF, sum = 0
3579 00:40:36.761271 12, 0x0, sum = 1
3580 00:40:36.763946 13, 0x0, sum = 2
3581 00:40:36.764042 14, 0x0, sum = 3
3582 00:40:36.767326 15, 0x0, sum = 4
3583 00:40:36.767401 best_step = 13
3584 00:40:36.767459
3585 00:40:36.767513 ==
3586 00:40:36.770777 Dram Type= 6, Freq= 0, CH_1, rank 1
3587 00:40:36.777403 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3588 00:40:36.777497 ==
3589 00:40:36.777643 RX Vref Scan: 0
3590 00:40:36.777699
3591 00:40:36.780625 RX Vref 0 -> 0, step: 1
3592 00:40:36.780694
3593 00:40:36.784026 RX Delay -5 -> 252, step: 4
3594 00:40:36.787853 iDelay=195, Bit 0, Center 122 (59 ~ 186) 128
3595 00:40:36.791211 iDelay=195, Bit 1, Center 116 (55 ~ 178) 124
3596 00:40:36.797210 iDelay=195, Bit 2, Center 110 (51 ~ 170) 120
3597 00:40:36.800560 iDelay=195, Bit 3, Center 116 (59 ~ 174) 116
3598 00:40:36.803924 iDelay=195, Bit 4, Center 116 (55 ~ 178) 124
3599 00:40:36.807388 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3600 00:40:36.810719 iDelay=195, Bit 6, Center 130 (67 ~ 194) 128
3601 00:40:36.813871 iDelay=195, Bit 7, Center 120 (59 ~ 182) 124
3602 00:40:36.820790 iDelay=195, Bit 8, Center 106 (47 ~ 166) 120
3603 00:40:36.824307 iDelay=195, Bit 9, Center 108 (47 ~ 170) 124
3604 00:40:36.827551 iDelay=195, Bit 10, Center 116 (55 ~ 178) 124
3605 00:40:36.830712 iDelay=195, Bit 11, Center 112 (51 ~ 174) 124
3606 00:40:36.837724 iDelay=195, Bit 12, Center 126 (63 ~ 190) 128
3607 00:40:36.840732 iDelay=195, Bit 13, Center 124 (67 ~ 182) 116
3608 00:40:36.844067 iDelay=195, Bit 14, Center 124 (67 ~ 182) 116
3609 00:40:36.847472 iDelay=195, Bit 15, Center 128 (67 ~ 190) 124
3610 00:40:36.847547 ==
3611 00:40:36.851068 Dram Type= 6, Freq= 0, CH_1, rank 1
3612 00:40:36.854175 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3613 00:40:36.857459 ==
3614 00:40:36.857563 DQS Delay:
3615 00:40:36.857656 DQS0 = 0, DQS1 = 0
3616 00:40:36.860579 DQM Delay:
3617 00:40:36.860653 DQM0 = 120, DQM1 = 118
3618 00:40:36.863941 DQ Delay:
3619 00:40:36.867323 DQ0 =122, DQ1 =116, DQ2 =110, DQ3 =116
3620 00:40:36.870791 DQ4 =116, DQ5 =130, DQ6 =130, DQ7 =120
3621 00:40:36.874182 DQ8 =106, DQ9 =108, DQ10 =116, DQ11 =112
3622 00:40:36.877526 DQ12 =126, DQ13 =124, DQ14 =124, DQ15 =128
3623 00:40:36.877644
3624 00:40:36.877703
3625 00:40:36.884309 [DQSOSCAuto] RK1, (LSB)MR18= 0x13f0, (MSB)MR19= 0x403, tDQSOscB0 = 416 ps tDQSOscB1 = 402 ps
3626 00:40:36.887374 CH1 RK1: MR19=403, MR18=13F0
3627 00:40:36.893836 CH1_RK1: MR19=0x403, MR18=0x13F0, DQSOSC=402, MR23=63, INC=40, DEC=27
3628 00:40:36.897712 [RxdqsGatingPostProcess] freq 1200
3629 00:40:36.904445 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3630 00:40:36.907165 best DQS0 dly(2T, 0.5T) = (0, 11)
3631 00:40:36.907239 best DQS1 dly(2T, 0.5T) = (0, 11)
3632 00:40:36.910547 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3633 00:40:36.913886 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3634 00:40:36.917134 best DQS0 dly(2T, 0.5T) = (0, 11)
3635 00:40:36.920335 best DQS1 dly(2T, 0.5T) = (0, 11)
3636 00:40:36.923743 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3637 00:40:36.927154 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3638 00:40:36.930714 Pre-setting of DQS Precalculation
3639 00:40:36.937149 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3640 00:40:36.944032 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3641 00:40:36.950828 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3642 00:40:36.950904
3643 00:40:36.950962
3644 00:40:36.954546 [Calibration Summary] 2400 Mbps
3645 00:40:36.954620 CH 0, Rank 0
3646 00:40:36.957396 SW Impedance : PASS
3647 00:40:36.960938 DUTY Scan : NO K
3648 00:40:36.961012 ZQ Calibration : PASS
3649 00:40:36.964190 Jitter Meter : NO K
3650 00:40:36.967025 CBT Training : PASS
3651 00:40:36.967099 Write leveling : PASS
3652 00:40:36.970543 RX DQS gating : PASS
3653 00:40:36.973826 RX DQ/DQS(RDDQC) : PASS
3654 00:40:36.973901 TX DQ/DQS : PASS
3655 00:40:36.977203 RX DATLAT : PASS
3656 00:40:36.977296 RX DQ/DQS(Engine): PASS
3657 00:40:36.980458 TX OE : NO K
3658 00:40:36.980552 All Pass.
3659 00:40:36.980641
3660 00:40:36.983761 CH 0, Rank 1
3661 00:40:36.983852 SW Impedance : PASS
3662 00:40:36.987132 DUTY Scan : NO K
3663 00:40:36.990460 ZQ Calibration : PASS
3664 00:40:36.990530 Jitter Meter : NO K
3665 00:40:36.993742 CBT Training : PASS
3666 00:40:36.996877 Write leveling : PASS
3667 00:40:36.996970 RX DQS gating : PASS
3668 00:40:37.000090 RX DQ/DQS(RDDQC) : PASS
3669 00:40:37.003745 TX DQ/DQS : PASS
3670 00:40:37.003820 RX DATLAT : PASS
3671 00:40:37.007043 RX DQ/DQS(Engine): PASS
3672 00:40:37.010502 TX OE : NO K
3673 00:40:37.010594 All Pass.
3674 00:40:37.010654
3675 00:40:37.010708 CH 1, Rank 0
3676 00:40:37.013916 SW Impedance : PASS
3677 00:40:37.016683 DUTY Scan : NO K
3678 00:40:37.016780 ZQ Calibration : PASS
3679 00:40:37.020016 Jitter Meter : NO K
3680 00:40:37.023917 CBT Training : PASS
3681 00:40:37.023991 Write leveling : PASS
3682 00:40:37.026727 RX DQS gating : PASS
3683 00:40:37.030000 RX DQ/DQS(RDDQC) : PASS
3684 00:40:37.030075 TX DQ/DQS : PASS
3685 00:40:37.033408 RX DATLAT : PASS
3686 00:40:37.033481 RX DQ/DQS(Engine): PASS
3687 00:40:37.036837 TX OE : NO K
3688 00:40:37.036911 All Pass.
3689 00:40:37.036969
3690 00:40:37.040170 CH 1, Rank 1
3691 00:40:37.040247 SW Impedance : PASS
3692 00:40:37.043487 DUTY Scan : NO K
3693 00:40:37.046797 ZQ Calibration : PASS
3694 00:40:37.046872 Jitter Meter : NO K
3695 00:40:37.050266 CBT Training : PASS
3696 00:40:37.053806 Write leveling : PASS
3697 00:40:37.053881 RX DQS gating : PASS
3698 00:40:37.057185 RX DQ/DQS(RDDQC) : PASS
3699 00:40:37.060273 TX DQ/DQS : PASS
3700 00:40:37.060377 RX DATLAT : PASS
3701 00:40:37.063891 RX DQ/DQS(Engine): PASS
3702 00:40:37.067184 TX OE : NO K
3703 00:40:37.067259 All Pass.
3704 00:40:37.067318
3705 00:40:37.067378 DramC Write-DBI off
3706 00:40:37.070456 PER_BANK_REFRESH: Hybrid Mode
3707 00:40:37.073791 TX_TRACKING: ON
3708 00:40:37.080427 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3709 00:40:37.083690 [FAST_K] Save calibration result to emmc
3710 00:40:37.089875 dramc_set_vcore_voltage set vcore to 650000
3711 00:40:37.089945 Read voltage for 600, 5
3712 00:40:37.093504 Vio18 = 0
3713 00:40:37.093609 Vcore = 650000
3714 00:40:37.093668 Vdram = 0
3715 00:40:37.096798 Vddq = 0
3716 00:40:37.096862 Vmddr = 0
3717 00:40:37.099775 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3718 00:40:37.106802 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3719 00:40:37.110161 MEM_TYPE=3, freq_sel=19
3720 00:40:37.110230 sv_algorithm_assistance_LP4_1600
3721 00:40:37.116715 ============ PULL DRAM RESETB DOWN ============
3722 00:40:37.119855 ========== PULL DRAM RESETB DOWN end =========
3723 00:40:37.123284 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3724 00:40:37.126512 ===================================
3725 00:40:37.129831 LPDDR4 DRAM CONFIGURATION
3726 00:40:37.133303 ===================================
3727 00:40:37.136744 EX_ROW_EN[0] = 0x0
3728 00:40:37.136804 EX_ROW_EN[1] = 0x0
3729 00:40:37.140149 LP4Y_EN = 0x0
3730 00:40:37.140206 WORK_FSP = 0x0
3731 00:40:37.143519 WL = 0x2
3732 00:40:37.143584 RL = 0x2
3733 00:40:37.146794 BL = 0x2
3734 00:40:37.146862 RPST = 0x0
3735 00:40:37.150267 RD_PRE = 0x0
3736 00:40:37.150333 WR_PRE = 0x1
3737 00:40:37.153694 WR_PST = 0x0
3738 00:40:37.153756 DBI_WR = 0x0
3739 00:40:37.156834 DBI_RD = 0x0
3740 00:40:37.156896 OTF = 0x1
3741 00:40:37.160230 ===================================
3742 00:40:37.163547 ===================================
3743 00:40:37.166753 ANA top config
3744 00:40:37.170135 ===================================
3745 00:40:37.173441 DLL_ASYNC_EN = 0
3746 00:40:37.173503 ALL_SLAVE_EN = 1
3747 00:40:37.176655 NEW_RANK_MODE = 1
3748 00:40:37.180044 DLL_IDLE_MODE = 1
3749 00:40:37.183342 LP45_APHY_COMB_EN = 1
3750 00:40:37.183407 TX_ODT_DIS = 1
3751 00:40:37.186563 NEW_8X_MODE = 1
3752 00:40:37.189819 ===================================
3753 00:40:37.193770 ===================================
3754 00:40:37.196499 data_rate = 1200
3755 00:40:37.200401 CKR = 1
3756 00:40:37.203072 DQ_P2S_RATIO = 8
3757 00:40:37.206396 ===================================
3758 00:40:37.209727 CA_P2S_RATIO = 8
3759 00:40:37.209831 DQ_CA_OPEN = 0
3760 00:40:37.213569 DQ_SEMI_OPEN = 0
3761 00:40:37.216807 CA_SEMI_OPEN = 0
3762 00:40:37.219893 CA_FULL_RATE = 0
3763 00:40:37.222950 DQ_CKDIV4_EN = 1
3764 00:40:37.226527 CA_CKDIV4_EN = 1
3765 00:40:37.226598 CA_PREDIV_EN = 0
3766 00:40:37.229989 PH8_DLY = 0
3767 00:40:37.233311 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3768 00:40:37.236933 DQ_AAMCK_DIV = 4
3769 00:40:37.239683 CA_AAMCK_DIV = 4
3770 00:40:37.242930 CA_ADMCK_DIV = 4
3771 00:40:37.243001 DQ_TRACK_CA_EN = 0
3772 00:40:37.246916 CA_PICK = 600
3773 00:40:37.250233 CA_MCKIO = 600
3774 00:40:37.253501 MCKIO_SEMI = 0
3775 00:40:37.256932 PLL_FREQ = 2288
3776 00:40:37.259744 DQ_UI_PI_RATIO = 32
3777 00:40:37.263077 CA_UI_PI_RATIO = 0
3778 00:40:37.266432 ===================================
3779 00:40:37.266498 ===================================
3780 00:40:37.269847 memory_type:LPDDR4
3781 00:40:37.273139 GP_NUM : 10
3782 00:40:37.273203 SRAM_EN : 1
3783 00:40:37.276435 MD32_EN : 0
3784 00:40:37.279720 ===================================
3785 00:40:37.283034 [ANA_INIT] >>>>>>>>>>>>>>
3786 00:40:37.286405 <<<<<< [CONFIGURE PHASE]: ANA_TX
3787 00:40:37.289748 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3788 00:40:37.292922 ===================================
3789 00:40:37.296072 data_rate = 1200,PCW = 0X5800
3790 00:40:37.296136 ===================================
3791 00:40:37.302733 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3792 00:40:37.306631 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3793 00:40:37.312705 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3794 00:40:37.316083 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3795 00:40:37.319941 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3796 00:40:37.322556 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3797 00:40:37.326062 [ANA_INIT] flow start
3798 00:40:37.329439 [ANA_INIT] PLL >>>>>>>>
3799 00:40:37.329516 [ANA_INIT] PLL <<<<<<<<
3800 00:40:37.332785 [ANA_INIT] MIDPI >>>>>>>>
3801 00:40:37.336619 [ANA_INIT] MIDPI <<<<<<<<
3802 00:40:37.336694 [ANA_INIT] DLL >>>>>>>>
3803 00:40:37.339846 [ANA_INIT] flow end
3804 00:40:37.342953 ============ LP4 DIFF to SE enter ============
3805 00:40:37.346545 ============ LP4 DIFF to SE exit ============
3806 00:40:37.349644 [ANA_INIT] <<<<<<<<<<<<<
3807 00:40:37.353192 [Flow] Enable top DCM control >>>>>
3808 00:40:37.356014 [Flow] Enable top DCM control <<<<<
3809 00:40:37.359964 Enable DLL master slave shuffle
3810 00:40:37.366604 ==============================================================
3811 00:40:37.366682 Gating Mode config
3812 00:40:37.372704 ==============================================================
3813 00:40:37.372770 Config description:
3814 00:40:37.382609 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3815 00:40:37.389481 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3816 00:40:37.396483 SELPH_MODE 0: By rank 1: By Phase
3817 00:40:37.399547 ==============================================================
3818 00:40:37.402652 GAT_TRACK_EN = 1
3819 00:40:37.406370 RX_GATING_MODE = 2
3820 00:40:37.409070 RX_GATING_TRACK_MODE = 2
3821 00:40:37.413102 SELPH_MODE = 1
3822 00:40:37.415886 PICG_EARLY_EN = 1
3823 00:40:37.419241 VALID_LAT_VALUE = 1
3824 00:40:37.425881 ==============================================================
3825 00:40:37.429140 Enter into Gating configuration >>>>
3826 00:40:37.432494 Exit from Gating configuration <<<<
3827 00:40:37.432562 Enter into DVFS_PRE_config >>>>>
3828 00:40:37.445724 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3829 00:40:37.449067 Exit from DVFS_PRE_config <<<<<
3830 00:40:37.452362 Enter into PICG configuration >>>>
3831 00:40:37.455575 Exit from PICG configuration <<<<
3832 00:40:37.455642 [RX_INPUT] configuration >>>>>
3833 00:40:37.459071 [RX_INPUT] configuration <<<<<
3834 00:40:37.466014 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3835 00:40:37.469083 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3836 00:40:37.476047 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3837 00:40:37.482650 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3838 00:40:37.489302 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3839 00:40:37.495423 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3840 00:40:37.498803 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3841 00:40:37.502847 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3842 00:40:37.509257 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3843 00:40:37.512310 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3844 00:40:37.515795 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3845 00:40:37.518704 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3846 00:40:37.522573 ===================================
3847 00:40:37.525865 LPDDR4 DRAM CONFIGURATION
3848 00:40:37.529113 ===================================
3849 00:40:37.532383 EX_ROW_EN[0] = 0x0
3850 00:40:37.532450 EX_ROW_EN[1] = 0x0
3851 00:40:37.535729 LP4Y_EN = 0x0
3852 00:40:37.535799 WORK_FSP = 0x0
3853 00:40:37.538372 WL = 0x2
3854 00:40:37.538437 RL = 0x2
3855 00:40:37.541780 BL = 0x2
3856 00:40:37.541845 RPST = 0x0
3857 00:40:37.545078 RD_PRE = 0x0
3858 00:40:37.549054 WR_PRE = 0x1
3859 00:40:37.549121 WR_PST = 0x0
3860 00:40:37.551794 DBI_WR = 0x0
3861 00:40:37.551859 DBI_RD = 0x0
3862 00:40:37.555200 OTF = 0x1
3863 00:40:37.558441 ===================================
3864 00:40:37.561797 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3865 00:40:37.564975 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3866 00:40:37.568446 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3867 00:40:37.571726 ===================================
3868 00:40:37.575058 LPDDR4 DRAM CONFIGURATION
3869 00:40:37.578497 ===================================
3870 00:40:37.581790 EX_ROW_EN[0] = 0x10
3871 00:40:37.581860 EX_ROW_EN[1] = 0x0
3872 00:40:37.585072 LP4Y_EN = 0x0
3873 00:40:37.585137 WORK_FSP = 0x0
3874 00:40:37.588262 WL = 0x2
3875 00:40:37.588330 RL = 0x2
3876 00:40:37.591895 BL = 0x2
3877 00:40:37.591961 RPST = 0x0
3878 00:40:37.595272 RD_PRE = 0x0
3879 00:40:37.595351 WR_PRE = 0x1
3880 00:40:37.598828 WR_PST = 0x0
3881 00:40:37.601998 DBI_WR = 0x0
3882 00:40:37.602067 DBI_RD = 0x0
3883 00:40:37.604772 OTF = 0x1
3884 00:40:37.608114 ===================================
3885 00:40:37.611350 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3886 00:40:37.616790 nWR fixed to 30
3887 00:40:37.620102 [ModeRegInit_LP4] CH0 RK0
3888 00:40:37.620172 [ModeRegInit_LP4] CH0 RK1
3889 00:40:37.623179 [ModeRegInit_LP4] CH1 RK0
3890 00:40:37.626895 [ModeRegInit_LP4] CH1 RK1
3891 00:40:37.626961 match AC timing 17
3892 00:40:37.633365 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3893 00:40:37.636723 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3894 00:40:37.640050 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3895 00:40:37.646583 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3896 00:40:37.649833 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3897 00:40:37.649926 ==
3898 00:40:37.653122 Dram Type= 6, Freq= 0, CH_0, rank 0
3899 00:40:37.656397 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3900 00:40:37.656486 ==
3901 00:40:37.663256 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3902 00:40:37.669828 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3903 00:40:37.673123 [CA 0] Center 35 (5~66) winsize 62
3904 00:40:37.676490 [CA 1] Center 35 (5~66) winsize 62
3905 00:40:37.679693 [CA 2] Center 33 (3~64) winsize 62
3906 00:40:37.683127 [CA 3] Center 33 (2~64) winsize 63
3907 00:40:37.686532 [CA 4] Center 33 (2~64) winsize 63
3908 00:40:37.689847 [CA 5] Center 32 (2~63) winsize 62
3909 00:40:37.689919
3910 00:40:37.693209 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3911 00:40:37.693299
3912 00:40:37.696547 [CATrainingPosCal] consider 1 rank data
3913 00:40:37.699940 u2DelayCellTimex100 = 270/100 ps
3914 00:40:37.703138 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3915 00:40:37.706817 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3916 00:40:37.709845 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3917 00:40:37.713295 CA3 delay=33 (2~64),Diff = 1 PI (9 cell)
3918 00:40:37.716468 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3919 00:40:37.720406 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3920 00:40:37.720495
3921 00:40:37.726893 CA PerBit enable=1, Macro0, CA PI delay=32
3922 00:40:37.726971
3923 00:40:37.730355 [CBTSetCACLKResult] CA Dly = 32
3924 00:40:37.730444 CS Dly: 5 (0~36)
3925 00:40:37.730526 ==
3926 00:40:37.733101 Dram Type= 6, Freq= 0, CH_0, rank 1
3927 00:40:37.736954 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3928 00:40:37.737043 ==
3929 00:40:37.743525 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3930 00:40:37.750118 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3931 00:40:37.753123 [CA 0] Center 35 (5~66) winsize 62
3932 00:40:37.756824 [CA 1] Center 35 (5~66) winsize 62
3933 00:40:37.759854 [CA 2] Center 33 (3~64) winsize 62
3934 00:40:37.763170 [CA 3] Center 33 (3~64) winsize 62
3935 00:40:37.766722 [CA 4] Center 33 (2~64) winsize 63
3936 00:40:37.769408 [CA 5] Center 32 (2~63) winsize 62
3937 00:40:37.769474
3938 00:40:37.772664 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3939 00:40:37.772733
3940 00:40:37.776159 [CATrainingPosCal] consider 2 rank data
3941 00:40:37.779849 u2DelayCellTimex100 = 270/100 ps
3942 00:40:37.783126 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3943 00:40:37.786500 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3944 00:40:37.789702 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3945 00:40:37.793121 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
3946 00:40:37.799917 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3947 00:40:37.802636 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3948 00:40:37.802741
3949 00:40:37.806158 CA PerBit enable=1, Macro0, CA PI delay=32
3950 00:40:37.806268
3951 00:40:37.809477 [CBTSetCACLKResult] CA Dly = 32
3952 00:40:37.809639 CS Dly: 5 (0~36)
3953 00:40:37.809706
3954 00:40:37.812968 ----->DramcWriteLeveling(PI) begin...
3955 00:40:37.813092 ==
3956 00:40:37.816164 Dram Type= 6, Freq= 0, CH_0, rank 0
3957 00:40:37.822481 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3958 00:40:37.822604 ==
3959 00:40:37.826286 Write leveling (Byte 0): 34 => 34
3960 00:40:37.826371 Write leveling (Byte 1): 31 => 31
3961 00:40:37.829335 DramcWriteLeveling(PI) end<-----
3962 00:40:37.829444
3963 00:40:37.832943 ==
3964 00:40:37.833012 Dram Type= 6, Freq= 0, CH_0, rank 0
3965 00:40:37.839211 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3966 00:40:37.839285 ==
3967 00:40:37.842590 [Gating] SW mode calibration
3968 00:40:37.849231 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3969 00:40:37.852387 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3970 00:40:37.858966 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3971 00:40:37.862584 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3972 00:40:37.865517 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3973 00:40:37.872461 0 9 12 | B1->B0 | 3434 2c2c | 1 1 | (0 0) (0 0)
3974 00:40:37.875529 0 9 16 | B1->B0 | 2e2e 2323 | 1 0 | (1 0) (0 0)
3975 00:40:37.878823 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3976 00:40:37.885464 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3977 00:40:37.889181 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3978 00:40:37.892028 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3979 00:40:37.899179 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3980 00:40:37.901880 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3981 00:40:37.905231 0 10 12 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
3982 00:40:37.911992 0 10 16 | B1->B0 | 3535 4646 | 0 0 | (1 1) (0 0)
3983 00:40:37.915318 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3984 00:40:37.918594 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3985 00:40:37.925365 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3986 00:40:37.928760 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3987 00:40:37.932048 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3988 00:40:37.938791 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3989 00:40:37.942018 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
3990 00:40:37.945727 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3991 00:40:37.948937 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3992 00:40:37.955158 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3993 00:40:37.958463 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3994 00:40:37.962398 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3995 00:40:37.969142 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3996 00:40:37.972340 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3997 00:40:37.975743 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3998 00:40:37.982012 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3999 00:40:37.985252 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4000 00:40:37.988303 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4001 00:40:37.995200 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4002 00:40:37.998724 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4003 00:40:38.002123 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4004 00:40:38.008821 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4005 00:40:38.012155 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4006 00:40:38.014827 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4007 00:40:38.018215 Total UI for P1: 0, mck2ui 16
4008 00:40:38.021522 best dqsien dly found for B0: ( 0, 13, 12)
4009 00:40:38.028198 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4010 00:40:38.028273 Total UI for P1: 0, mck2ui 16
4011 00:40:38.035280 best dqsien dly found for B1: ( 0, 13, 18)
4012 00:40:38.038793 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4013 00:40:38.041484 best DQS1 dly(MCK, UI, PI) = (0, 13, 18)
4014 00:40:38.041579
4015 00:40:38.044897 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4016 00:40:38.048239 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 18)
4017 00:40:38.051698 [Gating] SW calibration Done
4018 00:40:38.051772 ==
4019 00:40:38.054902 Dram Type= 6, Freq= 0, CH_0, rank 0
4020 00:40:38.058038 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4021 00:40:38.058114 ==
4022 00:40:38.061782 RX Vref Scan: 0
4023 00:40:38.061856
4024 00:40:38.061926 RX Vref 0 -> 0, step: 1
4025 00:40:38.062000
4026 00:40:38.064739 RX Delay -230 -> 252, step: 16
4027 00:40:38.071902 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4028 00:40:38.075222 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4029 00:40:38.078634 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4030 00:40:38.082003 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4031 00:40:38.085234 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4032 00:40:38.091804 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4033 00:40:38.095177 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4034 00:40:38.098458 iDelay=218, Bit 7, Center 65 (-86 ~ 217) 304
4035 00:40:38.101874 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4036 00:40:38.105116 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4037 00:40:38.111795 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4038 00:40:38.114608 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4039 00:40:38.118383 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4040 00:40:38.121437 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4041 00:40:38.128163 iDelay=218, Bit 14, Center 65 (-86 ~ 217) 304
4042 00:40:38.131454 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4043 00:40:38.131529 ==
4044 00:40:38.134810 Dram Type= 6, Freq= 0, CH_0, rank 0
4045 00:40:38.138054 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4046 00:40:38.138129 ==
4047 00:40:38.141326 DQS Delay:
4048 00:40:38.141400 DQS0 = 0, DQS1 = 0
4049 00:40:38.141458 DQM Delay:
4050 00:40:38.144769 DQM0 = 52, DQM1 = 47
4051 00:40:38.144843 DQ Delay:
4052 00:40:38.148164 DQ0 =49, DQ1 =57, DQ2 =41, DQ3 =49
4053 00:40:38.151565 DQ4 =49, DQ5 =41, DQ6 =65, DQ7 =65
4054 00:40:38.154956 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4055 00:40:38.158289 DQ12 =49, DQ13 =49, DQ14 =65, DQ15 =57
4056 00:40:38.158364
4057 00:40:38.158421
4058 00:40:38.158473 ==
4059 00:40:38.161479 Dram Type= 6, Freq= 0, CH_0, rank 0
4060 00:40:38.168149 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4061 00:40:38.168224 ==
4062 00:40:38.168282
4063 00:40:38.168334
4064 00:40:38.168384 TX Vref Scan disable
4065 00:40:38.171364 == TX Byte 0 ==
4066 00:40:38.175095 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4067 00:40:38.181416 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4068 00:40:38.181540 == TX Byte 1 ==
4069 00:40:38.185042 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4070 00:40:38.191344 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4071 00:40:38.191428 ==
4072 00:40:38.194801 Dram Type= 6, Freq= 0, CH_0, rank 0
4073 00:40:38.198177 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4074 00:40:38.198252 ==
4075 00:40:38.198310
4076 00:40:38.198364
4077 00:40:38.201450 TX Vref Scan disable
4078 00:40:38.204778 == TX Byte 0 ==
4079 00:40:38.208214 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4080 00:40:38.211536 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4081 00:40:38.214907 == TX Byte 1 ==
4082 00:40:38.218325 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4083 00:40:38.221060 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4084 00:40:38.221127
4085 00:40:38.221183 [DATLAT]
4086 00:40:38.224446 Freq=600, CH0 RK0
4087 00:40:38.224506
4088 00:40:38.227603 DATLAT Default: 0x9
4089 00:40:38.227668 0, 0xFFFF, sum = 0
4090 00:40:38.231169 1, 0xFFFF, sum = 0
4091 00:40:38.231231 2, 0xFFFF, sum = 0
4092 00:40:38.234836 3, 0xFFFF, sum = 0
4093 00:40:38.234900 4, 0xFFFF, sum = 0
4094 00:40:38.237925 5, 0xFFFF, sum = 0
4095 00:40:38.237989 6, 0xFFFF, sum = 0
4096 00:40:38.241506 7, 0xFFFF, sum = 0
4097 00:40:38.241617 8, 0x0, sum = 1
4098 00:40:38.241674 9, 0x0, sum = 2
4099 00:40:38.244347 10, 0x0, sum = 3
4100 00:40:38.244407 11, 0x0, sum = 4
4101 00:40:38.248028 best_step = 9
4102 00:40:38.248112
4103 00:40:38.248217 ==
4104 00:40:38.251387 Dram Type= 6, Freq= 0, CH_0, rank 0
4105 00:40:38.254776 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4106 00:40:38.254839 ==
4107 00:40:38.258075 RX Vref Scan: 1
4108 00:40:38.258150
4109 00:40:38.258205 RX Vref 0 -> 0, step: 1
4110 00:40:38.258256
4111 00:40:38.260952 RX Delay -163 -> 252, step: 8
4112 00:40:38.261052
4113 00:40:38.264306 Set Vref, RX VrefLevel [Byte0]: 55
4114 00:40:38.267753 [Byte1]: 50
4115 00:40:38.271855
4116 00:40:38.271954 Final RX Vref Byte 0 = 55 to rank0
4117 00:40:38.275259 Final RX Vref Byte 1 = 50 to rank0
4118 00:40:38.278645 Final RX Vref Byte 0 = 55 to rank1
4119 00:40:38.282098 Final RX Vref Byte 1 = 50 to rank1==
4120 00:40:38.285343 Dram Type= 6, Freq= 0, CH_0, rank 0
4121 00:40:38.292173 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4122 00:40:38.292266 ==
4123 00:40:38.292348 DQS Delay:
4124 00:40:38.292441 DQS0 = 0, DQS1 = 0
4125 00:40:38.295151 DQM Delay:
4126 00:40:38.295214 DQM0 = 52, DQM1 = 45
4127 00:40:38.298544 DQ Delay:
4128 00:40:38.301666 DQ0 =52, DQ1 =56, DQ2 =48, DQ3 =52
4129 00:40:38.305023 DQ4 =52, DQ5 =44, DQ6 =60, DQ7 =56
4130 00:40:38.305088 DQ8 =32, DQ9 =36, DQ10 =48, DQ11 =40
4131 00:40:38.311931 DQ12 =52, DQ13 =48, DQ14 =56, DQ15 =52
4132 00:40:38.312000
4133 00:40:38.312060
4134 00:40:38.318399 [DQSOSCAuto] RK0, (LSB)MR18= 0x776a, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 387 ps
4135 00:40:38.321768 CH0 RK0: MR19=808, MR18=776A
4136 00:40:38.328399 CH0_RK0: MR19=0x808, MR18=0x776A, DQSOSC=387, MR23=63, INC=175, DEC=116
4137 00:40:38.328472
4138 00:40:38.331625 ----->DramcWriteLeveling(PI) begin...
4139 00:40:38.331695 ==
4140 00:40:38.335054 Dram Type= 6, Freq= 0, CH_0, rank 1
4141 00:40:38.338480 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4142 00:40:38.338545 ==
4143 00:40:38.341949 Write leveling (Byte 0): 33 => 33
4144 00:40:38.345103 Write leveling (Byte 1): 31 => 31
4145 00:40:38.348626 DramcWriteLeveling(PI) end<-----
4146 00:40:38.348694
4147 00:40:38.348754 ==
4148 00:40:38.351790 Dram Type= 6, Freq= 0, CH_0, rank 1
4149 00:40:38.354876 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4150 00:40:38.354940 ==
4151 00:40:38.358291 [Gating] SW mode calibration
4152 00:40:38.365168 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4153 00:40:38.371689 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4154 00:40:38.375070 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4155 00:40:38.378504 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4156 00:40:38.385210 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
4157 00:40:38.387992 0 9 12 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
4158 00:40:38.391369 0 9 16 | B1->B0 | 2828 2626 | 0 0 | (1 1) (0 0)
4159 00:40:38.398353 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4160 00:40:38.401731 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4161 00:40:38.405013 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4162 00:40:38.411463 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4163 00:40:38.415139 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4164 00:40:38.418213 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4165 00:40:38.424978 0 10 12 | B1->B0 | 2424 2424 | 0 0 | (0 0) (0 0)
4166 00:40:38.428052 0 10 16 | B1->B0 | 3c3c 4444 | 1 1 | (0 0) (0 0)
4167 00:40:38.431595 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4168 00:40:38.438340 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4169 00:40:38.441416 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4170 00:40:38.444869 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4171 00:40:38.451928 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4172 00:40:38.455314 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4173 00:40:38.458000 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4174 00:40:38.464777 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4175 00:40:38.468040 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4176 00:40:38.471767 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4177 00:40:38.478063 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4178 00:40:38.481638 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4179 00:40:38.484990 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4180 00:40:38.488208 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4181 00:40:38.495131 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4182 00:40:38.497858 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4183 00:40:38.501238 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4184 00:40:38.508148 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4185 00:40:38.511431 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4186 00:40:38.514746 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4187 00:40:38.521288 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4188 00:40:38.524520 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4189 00:40:38.527818 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4190 00:40:38.534774 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4191 00:40:38.538245 Total UI for P1: 0, mck2ui 16
4192 00:40:38.541438 best dqsien dly found for B0: ( 0, 13, 14)
4193 00:40:38.541506 Total UI for P1: 0, mck2ui 16
4194 00:40:38.547955 best dqsien dly found for B1: ( 0, 13, 14)
4195 00:40:38.551539 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4196 00:40:38.554484 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4197 00:40:38.554553
4198 00:40:38.558031 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4199 00:40:38.561338 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4200 00:40:38.564734 [Gating] SW calibration Done
4201 00:40:38.564803 ==
4202 00:40:38.567882 Dram Type= 6, Freq= 0, CH_0, rank 1
4203 00:40:38.571308 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4204 00:40:38.571378 ==
4205 00:40:38.574671 RX Vref Scan: 0
4206 00:40:38.574740
4207 00:40:38.574796 RX Vref 0 -> 0, step: 1
4208 00:40:38.574850
4209 00:40:38.578210 RX Delay -230 -> 252, step: 16
4210 00:40:38.584812 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4211 00:40:38.587839 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4212 00:40:38.590979 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4213 00:40:38.594829 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4214 00:40:38.597886 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4215 00:40:38.604675 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4216 00:40:38.608154 iDelay=218, Bit 6, Center 49 (-102 ~ 201) 304
4217 00:40:38.610873 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4218 00:40:38.614246 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4219 00:40:38.620771 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4220 00:40:38.624095 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4221 00:40:38.627488 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4222 00:40:38.631250 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4223 00:40:38.637832 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4224 00:40:38.641141 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4225 00:40:38.644552 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4226 00:40:38.644619 ==
4227 00:40:38.647881 Dram Type= 6, Freq= 0, CH_0, rank 1
4228 00:40:38.650717 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4229 00:40:38.650788 ==
4230 00:40:38.653962 DQS Delay:
4231 00:40:38.654029 DQS0 = 0, DQS1 = 0
4232 00:40:38.657304 DQM Delay:
4233 00:40:38.657370 DQM0 = 50, DQM1 = 43
4234 00:40:38.657425 DQ Delay:
4235 00:40:38.661416 DQ0 =49, DQ1 =49, DQ2 =49, DQ3 =49
4236 00:40:38.664121 DQ4 =57, DQ5 =41, DQ6 =49, DQ7 =57
4237 00:40:38.667430 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =33
4238 00:40:38.670646 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4239 00:40:38.670722
4240 00:40:38.670788
4241 00:40:38.674382 ==
4242 00:40:38.677365 Dram Type= 6, Freq= 0, CH_0, rank 1
4243 00:40:38.681012 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4244 00:40:38.681088 ==
4245 00:40:38.681145
4246 00:40:38.681198
4247 00:40:38.683786 TX Vref Scan disable
4248 00:40:38.683875 == TX Byte 0 ==
4249 00:40:38.690516 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4250 00:40:38.694046 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4251 00:40:38.694121 == TX Byte 1 ==
4252 00:40:38.700492 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4253 00:40:38.704332 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4254 00:40:38.704407 ==
4255 00:40:38.707652 Dram Type= 6, Freq= 0, CH_0, rank 1
4256 00:40:38.710639 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4257 00:40:38.710715 ==
4258 00:40:38.710773
4259 00:40:38.710825
4260 00:40:38.713537 TX Vref Scan disable
4261 00:40:38.716989 == TX Byte 0 ==
4262 00:40:38.720842 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4263 00:40:38.723614 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4264 00:40:38.727506 == TX Byte 1 ==
4265 00:40:38.730223 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4266 00:40:38.733470 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4267 00:40:38.733572
4268 00:40:38.736786 [DATLAT]
4269 00:40:38.736851 Freq=600, CH0 RK1
4270 00:40:38.736906
4271 00:40:38.740605 DATLAT Default: 0x9
4272 00:40:38.740671 0, 0xFFFF, sum = 0
4273 00:40:38.743846 1, 0xFFFF, sum = 0
4274 00:40:38.743911 2, 0xFFFF, sum = 0
4275 00:40:38.747246 3, 0xFFFF, sum = 0
4276 00:40:38.747311 4, 0xFFFF, sum = 0
4277 00:40:38.750716 5, 0xFFFF, sum = 0
4278 00:40:38.750785 6, 0xFFFF, sum = 0
4279 00:40:38.753386 7, 0xFFFF, sum = 0
4280 00:40:38.753483 8, 0x0, sum = 1
4281 00:40:38.756903 9, 0x0, sum = 2
4282 00:40:38.756972 10, 0x0, sum = 3
4283 00:40:38.760187 11, 0x0, sum = 4
4284 00:40:38.760252 best_step = 9
4285 00:40:38.760361
4286 00:40:38.760448 ==
4287 00:40:38.763418 Dram Type= 6, Freq= 0, CH_0, rank 1
4288 00:40:38.766814 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4289 00:40:38.770193 ==
4290 00:40:38.770274 RX Vref Scan: 0
4291 00:40:38.770333
4292 00:40:38.773815 RX Vref 0 -> 0, step: 1
4293 00:40:38.773881
4294 00:40:38.776993 RX Delay -163 -> 252, step: 8
4295 00:40:38.780401 iDelay=197, Bit 0, Center 52 (-91 ~ 196) 288
4296 00:40:38.783790 iDelay=197, Bit 1, Center 56 (-83 ~ 196) 280
4297 00:40:38.790133 iDelay=197, Bit 2, Center 52 (-91 ~ 196) 288
4298 00:40:38.793293 iDelay=197, Bit 3, Center 52 (-91 ~ 196) 288
4299 00:40:38.797004 iDelay=197, Bit 4, Center 56 (-83 ~ 196) 280
4300 00:40:38.799955 iDelay=197, Bit 5, Center 44 (-99 ~ 188) 288
4301 00:40:38.803584 iDelay=197, Bit 6, Center 60 (-75 ~ 196) 272
4302 00:40:38.810239 iDelay=197, Bit 7, Center 60 (-75 ~ 196) 272
4303 00:40:38.813613 iDelay=197, Bit 8, Center 36 (-107 ~ 180) 288
4304 00:40:38.816887 iDelay=197, Bit 9, Center 36 (-107 ~ 180) 288
4305 00:40:38.820000 iDelay=197, Bit 10, Center 48 (-91 ~ 188) 280
4306 00:40:38.823723 iDelay=197, Bit 11, Center 36 (-107 ~ 180) 288
4307 00:40:38.830004 iDelay=197, Bit 12, Center 48 (-91 ~ 188) 280
4308 00:40:38.833465 iDelay=197, Bit 13, Center 52 (-91 ~ 196) 288
4309 00:40:38.836915 iDelay=197, Bit 14, Center 56 (-83 ~ 196) 280
4310 00:40:38.840041 iDelay=197, Bit 15, Center 52 (-91 ~ 196) 288
4311 00:40:38.840110 ==
4312 00:40:38.843404 Dram Type= 6, Freq= 0, CH_0, rank 1
4313 00:40:38.850409 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4314 00:40:38.850483 ==
4315 00:40:38.850546 DQS Delay:
4316 00:40:38.853071 DQS0 = 0, DQS1 = 0
4317 00:40:38.853136 DQM Delay:
4318 00:40:38.853194 DQM0 = 54, DQM1 = 45
4319 00:40:38.856490 DQ Delay:
4320 00:40:38.859854 DQ0 =52, DQ1 =56, DQ2 =52, DQ3 =52
4321 00:40:38.863209 DQ4 =56, DQ5 =44, DQ6 =60, DQ7 =60
4322 00:40:38.866482 DQ8 =36, DQ9 =36, DQ10 =48, DQ11 =36
4323 00:40:38.869875 DQ12 =48, DQ13 =52, DQ14 =56, DQ15 =52
4324 00:40:38.869942
4325 00:40:38.869997
4326 00:40:38.876706 [DQSOSCAuto] RK1, (LSB)MR18= 0x6a2a, (MSB)MR19= 0x808, tDQSOscB0 = 401 ps tDQSOscB1 = 389 ps
4327 00:40:38.879951 CH0 RK1: MR19=808, MR18=6A2A
4328 00:40:38.886909 CH0_RK1: MR19=0x808, MR18=0x6A2A, DQSOSC=389, MR23=63, INC=173, DEC=115
4329 00:40:38.889716 [RxdqsGatingPostProcess] freq 600
4330 00:40:38.892961 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4331 00:40:38.896864 Pre-setting of DQS Precalculation
4332 00:40:38.903412 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4333 00:40:38.903484 ==
4334 00:40:38.906790 Dram Type= 6, Freq= 0, CH_1, rank 0
4335 00:40:38.910199 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4336 00:40:38.910271 ==
4337 00:40:38.916544 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4338 00:40:38.923020 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4339 00:40:38.926395 [CA 0] Center 35 (5~66) winsize 62
4340 00:40:38.929876 [CA 1] Center 36 (5~67) winsize 63
4341 00:40:38.933196 [CA 2] Center 34 (4~65) winsize 62
4342 00:40:38.936437 [CA 3] Center 34 (3~65) winsize 63
4343 00:40:38.939612 [CA 4] Center 34 (4~65) winsize 62
4344 00:40:38.939676 [CA 5] Center 34 (4~64) winsize 61
4345 00:40:38.943186
4346 00:40:38.946556 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4347 00:40:38.946620
4348 00:40:38.949454 [CATrainingPosCal] consider 1 rank data
4349 00:40:38.952930 u2DelayCellTimex100 = 270/100 ps
4350 00:40:38.956214 CA0 delay=35 (5~66),Diff = 1 PI (9 cell)
4351 00:40:38.959591 CA1 delay=36 (5~67),Diff = 2 PI (19 cell)
4352 00:40:38.963279 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4353 00:40:38.965987 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
4354 00:40:38.969233 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4355 00:40:38.973152 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4356 00:40:38.973214
4357 00:40:38.975848 CA PerBit enable=1, Macro0, CA PI delay=34
4358 00:40:38.975909
4359 00:40:38.979359 [CBTSetCACLKResult] CA Dly = 34
4360 00:40:38.982756 CS Dly: 6 (0~37)
4361 00:40:38.982827 ==
4362 00:40:38.986208 Dram Type= 6, Freq= 0, CH_1, rank 1
4363 00:40:38.989510 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4364 00:40:38.989625 ==
4365 00:40:38.996259 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4366 00:40:39.002887 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4367 00:40:39.006161 [CA 0] Center 36 (5~67) winsize 63
4368 00:40:39.009318 [CA 1] Center 36 (5~67) winsize 63
4369 00:40:39.012719 [CA 2] Center 34 (4~65) winsize 62
4370 00:40:39.016110 [CA 3] Center 34 (4~65) winsize 62
4371 00:40:39.019253 [CA 4] Center 35 (4~66) winsize 63
4372 00:40:39.022639 [CA 5] Center 34 (3~65) winsize 63
4373 00:40:39.022713
4374 00:40:39.025723 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4375 00:40:39.025795
4376 00:40:39.029146 [CATrainingPosCal] consider 2 rank data
4377 00:40:39.033063 u2DelayCellTimex100 = 270/100 ps
4378 00:40:39.036288 CA0 delay=35 (5~66),Diff = 1 PI (9 cell)
4379 00:40:39.039468 CA1 delay=36 (5~67),Diff = 2 PI (19 cell)
4380 00:40:39.042891 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4381 00:40:39.046276 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4382 00:40:39.049572 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4383 00:40:39.052837 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4384 00:40:39.052903
4385 00:40:39.059448 CA PerBit enable=1, Macro0, CA PI delay=34
4386 00:40:39.059519
4387 00:40:39.059575 [CBTSetCACLKResult] CA Dly = 34
4388 00:40:39.062605 CS Dly: 6 (0~37)
4389 00:40:39.062671
4390 00:40:39.065801 ----->DramcWriteLeveling(PI) begin...
4391 00:40:39.065871 ==
4392 00:40:39.068820 Dram Type= 6, Freq= 0, CH_1, rank 0
4393 00:40:39.072343 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4394 00:40:39.072411 ==
4395 00:40:39.075941 Write leveling (Byte 0): 31 => 31
4396 00:40:39.079096 Write leveling (Byte 1): 31 => 31
4397 00:40:39.082282 DramcWriteLeveling(PI) end<-----
4398 00:40:39.082351
4399 00:40:39.082407 ==
4400 00:40:39.085510 Dram Type= 6, Freq= 0, CH_1, rank 0
4401 00:40:39.088748 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4402 00:40:39.092155 ==
4403 00:40:39.092223 [Gating] SW mode calibration
4404 00:40:39.102109 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4405 00:40:39.105461 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4406 00:40:39.108900 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4407 00:40:39.115489 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4408 00:40:39.118995 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4409 00:40:39.122353 0 9 12 | B1->B0 | 2f2f 2e2e | 0 0 | (1 1) (0 0)
4410 00:40:39.128906 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4411 00:40:39.132148 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4412 00:40:39.135265 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4413 00:40:39.141946 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4414 00:40:39.145227 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4415 00:40:39.149297 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4416 00:40:39.155197 0 10 8 | B1->B0 | 2424 2727 | 0 0 | (0 0) (0 0)
4417 00:40:39.158455 0 10 12 | B1->B0 | 4343 3e3e | 0 0 | (0 0) (0 0)
4418 00:40:39.162453 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4419 00:40:39.168575 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4420 00:40:39.171818 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4421 00:40:39.175244 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4422 00:40:39.181983 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4423 00:40:39.185236 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4424 00:40:39.188390 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4425 00:40:39.195078 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4426 00:40:39.198765 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4427 00:40:39.202193 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4428 00:40:39.205493 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4429 00:40:39.212143 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4430 00:40:39.215368 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4431 00:40:39.218718 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4432 00:40:39.225453 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4433 00:40:39.228812 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4434 00:40:39.232216 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4435 00:40:39.238712 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4436 00:40:39.241713 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4437 00:40:39.245076 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4438 00:40:39.251562 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4439 00:40:39.255449 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4440 00:40:39.258110 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4441 00:40:39.265363 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4442 00:40:39.268517 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4443 00:40:39.271867 Total UI for P1: 0, mck2ui 16
4444 00:40:39.275148 best dqsien dly found for B0: ( 0, 13, 12)
4445 00:40:39.278613 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4446 00:40:39.282139 Total UI for P1: 0, mck2ui 16
4447 00:40:39.284948 best dqsien dly found for B1: ( 0, 13, 14)
4448 00:40:39.288319 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4449 00:40:39.291748 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4450 00:40:39.291817
4451 00:40:39.298238 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4452 00:40:39.301658 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4453 00:40:39.301729 [Gating] SW calibration Done
4454 00:40:39.304879 ==
4455 00:40:39.308231 Dram Type= 6, Freq= 0, CH_1, rank 0
4456 00:40:39.312108 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4457 00:40:39.312184 ==
4458 00:40:39.312242 RX Vref Scan: 0
4459 00:40:39.312295
4460 00:40:39.315379 RX Vref 0 -> 0, step: 1
4461 00:40:39.315445
4462 00:40:39.318234 RX Delay -230 -> 252, step: 16
4463 00:40:39.321835 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4464 00:40:39.325148 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4465 00:40:39.331580 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4466 00:40:39.335199 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4467 00:40:39.338797 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4468 00:40:39.341465 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4469 00:40:39.344908 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4470 00:40:39.351568 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4471 00:40:39.354855 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4472 00:40:39.358062 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4473 00:40:39.361316 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4474 00:40:39.368727 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4475 00:40:39.372035 iDelay=218, Bit 12, Center 65 (-86 ~ 217) 304
4476 00:40:39.375212 iDelay=218, Bit 13, Center 57 (-86 ~ 201) 288
4477 00:40:39.378368 iDelay=218, Bit 14, Center 57 (-86 ~ 201) 288
4478 00:40:39.381559 iDelay=218, Bit 15, Center 65 (-86 ~ 217) 304
4479 00:40:39.384941 ==
4480 00:40:39.385008 Dram Type= 6, Freq= 0, CH_1, rank 0
4481 00:40:39.391770 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4482 00:40:39.391846 ==
4483 00:40:39.391904 DQS Delay:
4484 00:40:39.394439 DQS0 = 0, DQS1 = 0
4485 00:40:39.394505 DQM Delay:
4486 00:40:39.398423 DQM0 = 51, DQM1 = 50
4487 00:40:39.398493 DQ Delay:
4488 00:40:39.401575 DQ0 =57, DQ1 =41, DQ2 =41, DQ3 =41
4489 00:40:39.404781 DQ4 =49, DQ5 =65, DQ6 =65, DQ7 =49
4490 00:40:39.408178 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4491 00:40:39.411510 DQ12 =65, DQ13 =57, DQ14 =57, DQ15 =65
4492 00:40:39.411580
4493 00:40:39.411636
4494 00:40:39.411688 ==
4495 00:40:39.414710 Dram Type= 6, Freq= 0, CH_1, rank 0
4496 00:40:39.418146 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4497 00:40:39.418212 ==
4498 00:40:39.418271
4499 00:40:39.418325
4500 00:40:39.421422 TX Vref Scan disable
4501 00:40:39.424892 == TX Byte 0 ==
4502 00:40:39.427584 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4503 00:40:39.431005 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4504 00:40:39.434326 == TX Byte 1 ==
4505 00:40:39.437711 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4506 00:40:39.441284 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4507 00:40:39.441352 ==
4508 00:40:39.444853 Dram Type= 6, Freq= 0, CH_1, rank 0
4509 00:40:39.447995 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4510 00:40:39.451531 ==
4511 00:40:39.451607
4512 00:40:39.451665
4513 00:40:39.451717 TX Vref Scan disable
4514 00:40:39.454907 == TX Byte 0 ==
4515 00:40:39.458169 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4516 00:40:39.461988 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4517 00:40:39.465312 == TX Byte 1 ==
4518 00:40:39.468195 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4519 00:40:39.471803 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4520 00:40:39.474995
4521 00:40:39.475070 [DATLAT]
4522 00:40:39.475138 Freq=600, CH1 RK0
4523 00:40:39.475272
4524 00:40:39.478402 DATLAT Default: 0x9
4525 00:40:39.478469 0, 0xFFFF, sum = 0
4526 00:40:39.481656 1, 0xFFFF, sum = 0
4527 00:40:39.481722 2, 0xFFFF, sum = 0
4528 00:40:39.485720 3, 0xFFFF, sum = 0
4529 00:40:39.485801 4, 0xFFFF, sum = 0
4530 00:40:39.488426 5, 0xFFFF, sum = 0
4531 00:40:39.488490 6, 0xFFFF, sum = 0
4532 00:40:39.491701 7, 0xFFFF, sum = 0
4533 00:40:39.491775 8, 0x0, sum = 1
4534 00:40:39.495163 9, 0x0, sum = 2
4535 00:40:39.495238 10, 0x0, sum = 3
4536 00:40:39.498462 11, 0x0, sum = 4
4537 00:40:39.498536 best_step = 9
4538 00:40:39.498636
4539 00:40:39.498690 ==
4540 00:40:39.502017 Dram Type= 6, Freq= 0, CH_1, rank 0
4541 00:40:39.508480 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4542 00:40:39.508563 ==
4543 00:40:39.508665 RX Vref Scan: 1
4544 00:40:39.508736
4545 00:40:39.511670 RX Vref 0 -> 0, step: 1
4546 00:40:39.511768
4547 00:40:39.515182 RX Delay -163 -> 252, step: 8
4548 00:40:39.515250
4549 00:40:39.518382 Set Vref, RX VrefLevel [Byte0]: 56
4550 00:40:39.521806 [Byte1]: 52
4551 00:40:39.521874
4552 00:40:39.525057 Final RX Vref Byte 0 = 56 to rank0
4553 00:40:39.528373 Final RX Vref Byte 1 = 52 to rank0
4554 00:40:39.531790 Final RX Vref Byte 0 = 56 to rank1
4555 00:40:39.535149 Final RX Vref Byte 1 = 52 to rank1==
4556 00:40:39.538391 Dram Type= 6, Freq= 0, CH_1, rank 0
4557 00:40:39.541720 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4558 00:40:39.541790 ==
4559 00:40:39.545064 DQS Delay:
4560 00:40:39.545130 DQS0 = 0, DQS1 = 0
4561 00:40:39.545186 DQM Delay:
4562 00:40:39.548541 DQM0 = 48, DQM1 = 46
4563 00:40:39.548604 DQ Delay:
4564 00:40:39.551901 DQ0 =52, DQ1 =40, DQ2 =36, DQ3 =48
4565 00:40:39.555110 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4566 00:40:39.558610 DQ8 =32, DQ9 =36, DQ10 =44, DQ11 =36
4567 00:40:39.561926 DQ12 =56, DQ13 =52, DQ14 =56, DQ15 =60
4568 00:40:39.561988
4569 00:40:39.562045
4570 00:40:39.571624 [DQSOSCAuto] RK0, (LSB)MR18= 0x5176, (MSB)MR19= 0x808, tDQSOscB0 = 387 ps tDQSOscB1 = 394 ps
4571 00:40:39.571698 CH1 RK0: MR19=808, MR18=5176
4572 00:40:39.578459 CH1_RK0: MR19=0x808, MR18=0x5176, DQSOSC=387, MR23=63, INC=175, DEC=116
4573 00:40:39.578528
4574 00:40:39.581413 ----->DramcWriteLeveling(PI) begin...
4575 00:40:39.585054 ==
4576 00:40:39.585122 Dram Type= 6, Freq= 0, CH_1, rank 1
4577 00:40:39.591351 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4578 00:40:39.591428 ==
4579 00:40:39.595004 Write leveling (Byte 0): 30 => 30
4580 00:40:39.598095 Write leveling (Byte 1): 32 => 32
4581 00:40:39.601823 DramcWriteLeveling(PI) end<-----
4582 00:40:39.601891
4583 00:40:39.601946 ==
4584 00:40:39.605213 Dram Type= 6, Freq= 0, CH_1, rank 1
4585 00:40:39.607904 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4586 00:40:39.607972 ==
4587 00:40:39.611331 [Gating] SW mode calibration
4588 00:40:39.617813 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4589 00:40:39.621138 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4590 00:40:39.627833 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4591 00:40:39.631103 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4592 00:40:39.634476 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4593 00:40:39.641245 0 9 12 | B1->B0 | 2f2f 2f2f | 0 0 | (1 1) (0 1)
4594 00:40:39.644400 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4595 00:40:39.647742 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4596 00:40:39.654758 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4597 00:40:39.658012 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4598 00:40:39.661353 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4599 00:40:39.668259 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4600 00:40:39.671551 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4601 00:40:39.674669 0 10 12 | B1->B0 | 3838 3838 | 0 1 | (0 0) (0 0)
4602 00:40:39.681192 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4603 00:40:39.684582 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4604 00:40:39.687837 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4605 00:40:39.694530 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4606 00:40:39.698061 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4607 00:40:39.701405 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4608 00:40:39.707987 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4609 00:40:39.710943 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4610 00:40:39.714191 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4611 00:40:39.721091 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4612 00:40:39.724429 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4613 00:40:39.727806 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4614 00:40:39.731139 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4615 00:40:39.737808 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4616 00:40:39.741048 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4617 00:40:39.744468 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4618 00:40:39.751014 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4619 00:40:39.754308 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4620 00:40:39.757903 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4621 00:40:39.764648 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4622 00:40:39.768045 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4623 00:40:39.771456 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4624 00:40:39.778310 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4625 00:40:39.781440 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4626 00:40:39.784621 Total UI for P1: 0, mck2ui 16
4627 00:40:39.787786 best dqsien dly found for B0: ( 0, 13, 10)
4628 00:40:39.791829 Total UI for P1: 0, mck2ui 16
4629 00:40:39.794629 best dqsien dly found for B1: ( 0, 13, 10)
4630 00:40:39.798159 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4631 00:40:39.801364 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4632 00:40:39.801432
4633 00:40:39.805055 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4634 00:40:39.808366 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4635 00:40:39.811569 [Gating] SW calibration Done
4636 00:40:39.811641 ==
4637 00:40:39.814874 Dram Type= 6, Freq= 0, CH_1, rank 1
4638 00:40:39.817856 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4639 00:40:39.817927 ==
4640 00:40:39.821379 RX Vref Scan: 0
4641 00:40:39.821448
4642 00:40:39.824652 RX Vref 0 -> 0, step: 1
4643 00:40:39.824724
4644 00:40:39.827789 RX Delay -230 -> 252, step: 16
4645 00:40:39.831357 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4646 00:40:39.834249 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4647 00:40:39.837552 iDelay=218, Bit 2, Center 41 (-102 ~ 185) 288
4648 00:40:39.841243 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4649 00:40:39.847657 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4650 00:40:39.851001 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4651 00:40:39.854214 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4652 00:40:39.857447 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4653 00:40:39.864270 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4654 00:40:39.867449 iDelay=218, Bit 9, Center 49 (-102 ~ 201) 304
4655 00:40:39.870844 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4656 00:40:39.874099 iDelay=218, Bit 11, Center 49 (-102 ~ 201) 304
4657 00:40:39.880999 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4658 00:40:39.884459 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4659 00:40:39.887802 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4660 00:40:39.890879 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4661 00:40:39.890948 ==
4662 00:40:39.894035 Dram Type= 6, Freq= 0, CH_1, rank 1
4663 00:40:39.900662 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4664 00:40:39.900732 ==
4665 00:40:39.900792 DQS Delay:
4666 00:40:39.900846 DQS0 = 0, DQS1 = 0
4667 00:40:39.904047 DQM Delay:
4668 00:40:39.904111 DQM0 = 51, DQM1 = 50
4669 00:40:39.907357 DQ Delay:
4670 00:40:39.910743 DQ0 =57, DQ1 =49, DQ2 =41, DQ3 =49
4671 00:40:39.914392 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49
4672 00:40:39.917233 DQ8 =33, DQ9 =49, DQ10 =49, DQ11 =49
4673 00:40:39.920554 DQ12 =57, DQ13 =57, DQ14 =49, DQ15 =57
4674 00:40:39.920630
4675 00:40:39.920700
4676 00:40:39.920754 ==
4677 00:40:39.924523 Dram Type= 6, Freq= 0, CH_1, rank 1
4678 00:40:39.927524 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4679 00:40:39.927597 ==
4680 00:40:39.927654
4681 00:40:39.927707
4682 00:40:39.930875 TX Vref Scan disable
4683 00:40:39.930943 == TX Byte 0 ==
4684 00:40:39.937627 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4685 00:40:39.940816 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4686 00:40:39.940899 == TX Byte 1 ==
4687 00:40:39.947785 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4688 00:40:39.950516 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4689 00:40:39.950586 ==
4690 00:40:39.953870 Dram Type= 6, Freq= 0, CH_1, rank 1
4691 00:40:39.957152 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4692 00:40:39.957223 ==
4693 00:40:39.957280
4694 00:40:39.960238
4695 00:40:39.960305 TX Vref Scan disable
4696 00:40:39.963938 == TX Byte 0 ==
4697 00:40:39.967382 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4698 00:40:39.970761 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4699 00:40:39.973885 == TX Byte 1 ==
4700 00:40:39.977202 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4701 00:40:39.980631 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4702 00:40:39.983993
4703 00:40:39.984061 [DATLAT]
4704 00:40:39.984122 Freq=600, CH1 RK1
4705 00:40:39.984177
4706 00:40:39.987368 DATLAT Default: 0x9
4707 00:40:39.987435 0, 0xFFFF, sum = 0
4708 00:40:39.990815 1, 0xFFFF, sum = 0
4709 00:40:39.990882 2, 0xFFFF, sum = 0
4710 00:40:39.994172 3, 0xFFFF, sum = 0
4711 00:40:39.994245 4, 0xFFFF, sum = 0
4712 00:40:39.997247 5, 0xFFFF, sum = 0
4713 00:40:39.997316 6, 0xFFFF, sum = 0
4714 00:40:40.000947 7, 0xFFFF, sum = 0
4715 00:40:40.001029 8, 0x0, sum = 1
4716 00:40:40.003959 9, 0x0, sum = 2
4717 00:40:40.004023 10, 0x0, sum = 3
4718 00:40:40.007272 11, 0x0, sum = 4
4719 00:40:40.007342 best_step = 9
4720 00:40:40.007397
4721 00:40:40.007448 ==
4722 00:40:40.010593 Dram Type= 6, Freq= 0, CH_1, rank 1
4723 00:40:40.017462 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4724 00:40:40.017568 ==
4725 00:40:40.017642 RX Vref Scan: 0
4726 00:40:40.017696
4727 00:40:40.020649 RX Vref 0 -> 0, step: 1
4728 00:40:40.020722
4729 00:40:40.023629 RX Delay -163 -> 252, step: 8
4730 00:40:40.026998 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4731 00:40:40.033823 iDelay=205, Bit 1, Center 44 (-99 ~ 188) 288
4732 00:40:40.036920 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4733 00:40:40.040142 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4734 00:40:40.043558 iDelay=205, Bit 4, Center 44 (-99 ~ 188) 288
4735 00:40:40.046987 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4736 00:40:40.053824 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4737 00:40:40.057256 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4738 00:40:40.060576 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4739 00:40:40.063912 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4740 00:40:40.067200 iDelay=205, Bit 10, Center 48 (-99 ~ 196) 296
4741 00:40:40.073774 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4742 00:40:40.077209 iDelay=205, Bit 12, Center 52 (-99 ~ 204) 304
4743 00:40:40.080414 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4744 00:40:40.083446 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4745 00:40:40.087230 iDelay=205, Bit 15, Center 56 (-91 ~ 204) 296
4746 00:40:40.090430 ==
4747 00:40:40.090497 Dram Type= 6, Freq= 0, CH_1, rank 1
4748 00:40:40.096949 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4749 00:40:40.097022 ==
4750 00:40:40.097078 DQS Delay:
4751 00:40:40.100405 DQS0 = 0, DQS1 = 0
4752 00:40:40.100469 DQM Delay:
4753 00:40:40.104007 DQM0 = 48, DQM1 = 45
4754 00:40:40.104083 DQ Delay:
4755 00:40:40.107127 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4756 00:40:40.110314 DQ4 =44, DQ5 =60, DQ6 =60, DQ7 =48
4757 00:40:40.113309 DQ8 =32, DQ9 =32, DQ10 =48, DQ11 =40
4758 00:40:40.117183 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =56
4759 00:40:40.117250
4760 00:40:40.117307
4761 00:40:40.123316 [DQSOSCAuto] RK1, (LSB)MR18= 0x6f26, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 389 ps
4762 00:40:40.126686 CH1 RK1: MR19=808, MR18=6F26
4763 00:40:40.133849 CH1_RK1: MR19=0x808, MR18=0x6F26, DQSOSC=389, MR23=63, INC=173, DEC=115
4764 00:40:40.136584 [RxdqsGatingPostProcess] freq 600
4765 00:40:40.143172 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4766 00:40:40.143240 Pre-setting of DQS Precalculation
4767 00:40:40.150237 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4768 00:40:40.156324 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4769 00:40:40.163139 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4770 00:40:40.163210
4771 00:40:40.163267
4772 00:40:40.166470 [Calibration Summary] 1200 Mbps
4773 00:40:40.169763 CH 0, Rank 0
4774 00:40:40.169854 SW Impedance : PASS
4775 00:40:40.173264 DUTY Scan : NO K
4776 00:40:40.176582 ZQ Calibration : PASS
4777 00:40:40.176646 Jitter Meter : NO K
4778 00:40:40.179993 CBT Training : PASS
4779 00:40:40.180055 Write leveling : PASS
4780 00:40:40.183419 RX DQS gating : PASS
4781 00:40:40.186796 RX DQ/DQS(RDDQC) : PASS
4782 00:40:40.186864 TX DQ/DQS : PASS
4783 00:40:40.189834 RX DATLAT : PASS
4784 00:40:40.193145 RX DQ/DQS(Engine): PASS
4785 00:40:40.193239 TX OE : NO K
4786 00:40:40.196674 All Pass.
4787 00:40:40.196734
4788 00:40:40.196786 CH 0, Rank 1
4789 00:40:40.200126 SW Impedance : PASS
4790 00:40:40.200200 DUTY Scan : NO K
4791 00:40:40.203282 ZQ Calibration : PASS
4792 00:40:40.206218 Jitter Meter : NO K
4793 00:40:40.206286 CBT Training : PASS
4794 00:40:40.209684 Write leveling : PASS
4795 00:40:40.213167 RX DQS gating : PASS
4796 00:40:40.213234 RX DQ/DQS(RDDQC) : PASS
4797 00:40:40.216811 TX DQ/DQS : PASS
4798 00:40:40.220013 RX DATLAT : PASS
4799 00:40:40.220081 RX DQ/DQS(Engine): PASS
4800 00:40:40.223349 TX OE : NO K
4801 00:40:40.223424 All Pass.
4802 00:40:40.223483
4803 00:40:40.223536 CH 1, Rank 0
4804 00:40:40.226810 SW Impedance : PASS
4805 00:40:40.229769 DUTY Scan : NO K
4806 00:40:40.229844 ZQ Calibration : PASS
4807 00:40:40.233247 Jitter Meter : NO K
4808 00:40:40.236861 CBT Training : PASS
4809 00:40:40.236936 Write leveling : PASS
4810 00:40:40.239939 RX DQS gating : PASS
4811 00:40:40.243409 RX DQ/DQS(RDDQC) : PASS
4812 00:40:40.243483 TX DQ/DQS : PASS
4813 00:40:40.246839 RX DATLAT : PASS
4814 00:40:40.249992 RX DQ/DQS(Engine): PASS
4815 00:40:40.250067 TX OE : NO K
4816 00:40:40.250125 All Pass.
4817 00:40:40.253150
4818 00:40:40.253223 CH 1, Rank 1
4819 00:40:40.257191 SW Impedance : PASS
4820 00:40:40.257265 DUTY Scan : NO K
4821 00:40:40.259867 ZQ Calibration : PASS
4822 00:40:40.259941 Jitter Meter : NO K
4823 00:40:40.263232 CBT Training : PASS
4824 00:40:40.266529 Write leveling : PASS
4825 00:40:40.266603 RX DQS gating : PASS
4826 00:40:40.269820 RX DQ/DQS(RDDQC) : PASS
4827 00:40:40.273255 TX DQ/DQS : PASS
4828 00:40:40.273328 RX DATLAT : PASS
4829 00:40:40.276749 RX DQ/DQS(Engine): PASS
4830 00:40:40.280181 TX OE : NO K
4831 00:40:40.280251 All Pass.
4832 00:40:40.280306
4833 00:40:40.283653 DramC Write-DBI off
4834 00:40:40.283718 PER_BANK_REFRESH: Hybrid Mode
4835 00:40:40.286364 TX_TRACKING: ON
4836 00:40:40.293189 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4837 00:40:40.299997 [FAST_K] Save calibration result to emmc
4838 00:40:40.303371 dramc_set_vcore_voltage set vcore to 662500
4839 00:40:40.303443 Read voltage for 933, 3
4840 00:40:40.306650 Vio18 = 0
4841 00:40:40.306718 Vcore = 662500
4842 00:40:40.306773 Vdram = 0
4843 00:40:40.309878 Vddq = 0
4844 00:40:40.309946 Vmddr = 0
4845 00:40:40.313030 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4846 00:40:40.319551 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4847 00:40:40.323252 MEM_TYPE=3, freq_sel=17
4848 00:40:40.326562 sv_algorithm_assistance_LP4_1600
4849 00:40:40.329676 ============ PULL DRAM RESETB DOWN ============
4850 00:40:40.333225 ========== PULL DRAM RESETB DOWN end =========
4851 00:40:40.336241 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4852 00:40:40.339662 ===================================
4853 00:40:40.343224 LPDDR4 DRAM CONFIGURATION
4854 00:40:40.346974 ===================================
4855 00:40:40.349938 EX_ROW_EN[0] = 0x0
4856 00:40:40.350006 EX_ROW_EN[1] = 0x0
4857 00:40:40.353513 LP4Y_EN = 0x0
4858 00:40:40.353622 WORK_FSP = 0x0
4859 00:40:40.356422 WL = 0x3
4860 00:40:40.356496 RL = 0x3
4861 00:40:40.360032 BL = 0x2
4862 00:40:40.360106 RPST = 0x0
4863 00:40:40.362962 RD_PRE = 0x0
4864 00:40:40.363036 WR_PRE = 0x1
4865 00:40:40.366340 WR_PST = 0x0
4866 00:40:40.366414 DBI_WR = 0x0
4867 00:40:40.370144 DBI_RD = 0x0
4868 00:40:40.373315 OTF = 0x1
4869 00:40:40.376497 ===================================
4870 00:40:40.379912 ===================================
4871 00:40:40.379985 ANA top config
4872 00:40:40.383343 ===================================
4873 00:40:40.386691 DLL_ASYNC_EN = 0
4874 00:40:40.386766 ALL_SLAVE_EN = 1
4875 00:40:40.390124 NEW_RANK_MODE = 1
4876 00:40:40.392872 DLL_IDLE_MODE = 1
4877 00:40:40.396256 LP45_APHY_COMB_EN = 1
4878 00:40:40.399725 TX_ODT_DIS = 1
4879 00:40:40.399795 NEW_8X_MODE = 1
4880 00:40:40.403105 ===================================
4881 00:40:40.406456 ===================================
4882 00:40:40.409852 data_rate = 1866
4883 00:40:40.413157 CKR = 1
4884 00:40:40.416442 DQ_P2S_RATIO = 8
4885 00:40:40.419692 ===================================
4886 00:40:40.423070 CA_P2S_RATIO = 8
4887 00:40:40.426228 DQ_CA_OPEN = 0
4888 00:40:40.426296 DQ_SEMI_OPEN = 0
4889 00:40:40.429928 CA_SEMI_OPEN = 0
4890 00:40:40.433211 CA_FULL_RATE = 0
4891 00:40:40.436543 DQ_CKDIV4_EN = 1
4892 00:40:40.439991 CA_CKDIV4_EN = 1
4893 00:40:40.440065 CA_PREDIV_EN = 0
4894 00:40:40.443331 PH8_DLY = 0
4895 00:40:40.446578 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4896 00:40:40.450045 DQ_AAMCK_DIV = 4
4897 00:40:40.453055 CA_AAMCK_DIV = 4
4898 00:40:40.456195 CA_ADMCK_DIV = 4
4899 00:40:40.456266 DQ_TRACK_CA_EN = 0
4900 00:40:40.459686 CA_PICK = 933
4901 00:40:40.462904 CA_MCKIO = 933
4902 00:40:40.466716 MCKIO_SEMI = 0
4903 00:40:40.469829 PLL_FREQ = 3732
4904 00:40:40.472989 DQ_UI_PI_RATIO = 32
4905 00:40:40.476220 CA_UI_PI_RATIO = 0
4906 00:40:40.479592 ===================================
4907 00:40:40.482963 ===================================
4908 00:40:40.483025 memory_type:LPDDR4
4909 00:40:40.486297 GP_NUM : 10
4910 00:40:40.489607 SRAM_EN : 1
4911 00:40:40.489674 MD32_EN : 0
4912 00:40:40.492859 ===================================
4913 00:40:40.496173 [ANA_INIT] >>>>>>>>>>>>>>
4914 00:40:40.499549 <<<<<< [CONFIGURE PHASE]: ANA_TX
4915 00:40:40.503086 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4916 00:40:40.506538 ===================================
4917 00:40:40.509924 data_rate = 1866,PCW = 0X8f00
4918 00:40:40.512681 ===================================
4919 00:40:40.516072 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4920 00:40:40.520103 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4921 00:40:40.526700 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4922 00:40:40.529473 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4923 00:40:40.532707 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4924 00:40:40.536458 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4925 00:40:40.539530 [ANA_INIT] flow start
4926 00:40:40.542991 [ANA_INIT] PLL >>>>>>>>
4927 00:40:40.543058 [ANA_INIT] PLL <<<<<<<<
4928 00:40:40.546421 [ANA_INIT] MIDPI >>>>>>>>
4929 00:40:40.549736 [ANA_INIT] MIDPI <<<<<<<<
4930 00:40:40.549849 [ANA_INIT] DLL >>>>>>>>
4931 00:40:40.553031 [ANA_INIT] flow end
4932 00:40:40.556326 ============ LP4 DIFF to SE enter ============
4933 00:40:40.559327 ============ LP4 DIFF to SE exit ============
4934 00:40:40.563077 [ANA_INIT] <<<<<<<<<<<<<
4935 00:40:40.566145 [Flow] Enable top DCM control >>>>>
4936 00:40:40.569754 [Flow] Enable top DCM control <<<<<
4937 00:40:40.572989 Enable DLL master slave shuffle
4938 00:40:40.579470 ==============================================================
4939 00:40:40.579541 Gating Mode config
4940 00:40:40.586268 ==============================================================
4941 00:40:40.586338 Config description:
4942 00:40:40.596420 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4943 00:40:40.603157 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4944 00:40:40.609240 SELPH_MODE 0: By rank 1: By Phase
4945 00:40:40.612725 ==============================================================
4946 00:40:40.616062 GAT_TRACK_EN = 1
4947 00:40:40.619367 RX_GATING_MODE = 2
4948 00:40:40.622540 RX_GATING_TRACK_MODE = 2
4949 00:40:40.626004 SELPH_MODE = 1
4950 00:40:40.629261 PICG_EARLY_EN = 1
4951 00:40:40.632701 VALID_LAT_VALUE = 1
4952 00:40:40.639630 ==============================================================
4953 00:40:40.642902 Enter into Gating configuration >>>>
4954 00:40:40.646365 Exit from Gating configuration <<<<
4955 00:40:40.646437 Enter into DVFS_PRE_config >>>>>
4956 00:40:40.659173 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4957 00:40:40.662547 Exit from DVFS_PRE_config <<<<<
4958 00:40:40.665787 Enter into PICG configuration >>>>
4959 00:40:40.669658 Exit from PICG configuration <<<<
4960 00:40:40.669728 [RX_INPUT] configuration >>>>>
4961 00:40:40.672706 [RX_INPUT] configuration <<<<<
4962 00:40:40.679365 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4963 00:40:40.682871 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4964 00:40:40.689426 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4965 00:40:40.696325 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4966 00:40:40.702520 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4967 00:40:40.709128 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4968 00:40:40.712750 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4969 00:40:40.716004 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4970 00:40:40.722919 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4971 00:40:40.725816 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4972 00:40:40.729519 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4973 00:40:40.732865 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4974 00:40:40.736219 ===================================
4975 00:40:40.739387 LPDDR4 DRAM CONFIGURATION
4976 00:40:40.742729 ===================================
4977 00:40:40.746041 EX_ROW_EN[0] = 0x0
4978 00:40:40.746108 EX_ROW_EN[1] = 0x0
4979 00:40:40.749327 LP4Y_EN = 0x0
4980 00:40:40.749394 WORK_FSP = 0x0
4981 00:40:40.752512 WL = 0x3
4982 00:40:40.752578 RL = 0x3
4983 00:40:40.755724 BL = 0x2
4984 00:40:40.755793 RPST = 0x0
4985 00:40:40.759195 RD_PRE = 0x0
4986 00:40:40.759266 WR_PRE = 0x1
4987 00:40:40.762563 WR_PST = 0x0
4988 00:40:40.762627 DBI_WR = 0x0
4989 00:40:40.766013 DBI_RD = 0x0
4990 00:40:40.766078 OTF = 0x1
4991 00:40:40.769434 ===================================
4992 00:40:40.776147 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4993 00:40:40.779514 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4994 00:40:40.782927 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4995 00:40:40.786167 ===================================
4996 00:40:40.789406 LPDDR4 DRAM CONFIGURATION
4997 00:40:40.793174 ===================================
4998 00:40:40.793300 EX_ROW_EN[0] = 0x10
4999 00:40:40.796231 EX_ROW_EN[1] = 0x0
5000 00:40:40.799122 LP4Y_EN = 0x0
5001 00:40:40.799196 WORK_FSP = 0x0
5002 00:40:40.802528 WL = 0x3
5003 00:40:40.802641 RL = 0x3
5004 00:40:40.805583 BL = 0x2
5005 00:40:40.805665 RPST = 0x0
5006 00:40:40.808825 RD_PRE = 0x0
5007 00:40:40.808886 WR_PRE = 0x1
5008 00:40:40.812261 WR_PST = 0x0
5009 00:40:40.812327 DBI_WR = 0x0
5010 00:40:40.815487 DBI_RD = 0x0
5011 00:40:40.815569 OTF = 0x1
5012 00:40:40.819075 ===================================
5013 00:40:40.825344 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5014 00:40:40.830136 nWR fixed to 30
5015 00:40:40.833525 [ModeRegInit_LP4] CH0 RK0
5016 00:40:40.833603 [ModeRegInit_LP4] CH0 RK1
5017 00:40:40.836907 [ModeRegInit_LP4] CH1 RK0
5018 00:40:40.840675 [ModeRegInit_LP4] CH1 RK1
5019 00:40:40.840768 match AC timing 9
5020 00:40:40.847185 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5021 00:40:40.850099 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5022 00:40:40.853369 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5023 00:40:40.860103 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5024 00:40:40.863325 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5025 00:40:40.863396 ==
5026 00:40:40.866640 Dram Type= 6, Freq= 0, CH_0, rank 0
5027 00:40:40.870234 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5028 00:40:40.870311 ==
5029 00:40:40.877042 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5030 00:40:40.883242 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5031 00:40:40.886707 [CA 0] Center 37 (6~68) winsize 63
5032 00:40:40.890005 [CA 1] Center 37 (7~68) winsize 62
5033 00:40:40.893463 [CA 2] Center 34 (4~65) winsize 62
5034 00:40:40.896874 [CA 3] Center 34 (3~65) winsize 63
5035 00:40:40.900287 [CA 4] Center 33 (2~64) winsize 63
5036 00:40:40.903739 [CA 5] Center 32 (2~62) winsize 61
5037 00:40:40.903816
5038 00:40:40.906874 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5039 00:40:40.906938
5040 00:40:40.909973 [CATrainingPosCal] consider 1 rank data
5041 00:40:40.913099 u2DelayCellTimex100 = 270/100 ps
5042 00:40:40.916459 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5043 00:40:40.920081 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5044 00:40:40.923149 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5045 00:40:40.926489 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5046 00:40:40.929829 CA4 delay=33 (2~64),Diff = 1 PI (6 cell)
5047 00:40:40.933179 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5048 00:40:40.936647
5049 00:40:40.939979 CA PerBit enable=1, Macro0, CA PI delay=32
5050 00:40:40.940049
5051 00:40:40.943428 [CBTSetCACLKResult] CA Dly = 32
5052 00:40:40.943498 CS Dly: 5 (0~36)
5053 00:40:40.943555 ==
5054 00:40:40.946887 Dram Type= 6, Freq= 0, CH_0, rank 1
5055 00:40:40.949581 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5056 00:40:40.949643 ==
5057 00:40:40.956784 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5058 00:40:40.963503 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5059 00:40:40.966730 [CA 0] Center 37 (6~68) winsize 63
5060 00:40:40.969935 [CA 1] Center 37 (7~68) winsize 62
5061 00:40:40.972920 [CA 2] Center 34 (4~65) winsize 62
5062 00:40:40.976341 [CA 3] Center 34 (3~65) winsize 63
5063 00:40:40.979786 [CA 4] Center 32 (2~63) winsize 62
5064 00:40:40.983052 [CA 5] Center 32 (2~62) winsize 61
5065 00:40:40.983120
5066 00:40:40.986197 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5067 00:40:40.986266
5068 00:40:40.989435 [CATrainingPosCal] consider 2 rank data
5069 00:40:40.993019 u2DelayCellTimex100 = 270/100 ps
5070 00:40:40.996175 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5071 00:40:40.999435 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5072 00:40:41.002953 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5073 00:40:41.006220 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5074 00:40:41.013181 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
5075 00:40:41.016499 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5076 00:40:41.016593
5077 00:40:41.019214 CA PerBit enable=1, Macro0, CA PI delay=32
5078 00:40:41.019275
5079 00:40:41.023069 [CBTSetCACLKResult] CA Dly = 32
5080 00:40:41.023136 CS Dly: 5 (0~37)
5081 00:40:41.023195
5082 00:40:41.026117 ----->DramcWriteLeveling(PI) begin...
5083 00:40:41.026184 ==
5084 00:40:41.029561 Dram Type= 6, Freq= 0, CH_0, rank 0
5085 00:40:41.036050 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5086 00:40:41.036122 ==
5087 00:40:41.039461 Write leveling (Byte 0): 31 => 31
5088 00:40:41.039541 Write leveling (Byte 1): 29 => 29
5089 00:40:41.043236 DramcWriteLeveling(PI) end<-----
5090 00:40:41.043307
5091 00:40:41.045937 ==
5092 00:40:41.049365 Dram Type= 6, Freq= 0, CH_0, rank 0
5093 00:40:41.052709 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5094 00:40:41.052775 ==
5095 00:40:41.056062 [Gating] SW mode calibration
5096 00:40:41.062729 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5097 00:40:41.065974 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5098 00:40:41.072849 0 14 0 | B1->B0 | 2d2d 3434 | 1 1 | (1 1) (1 1)
5099 00:40:41.075559 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5100 00:40:41.078985 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5101 00:40:41.086313 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5102 00:40:41.089539 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5103 00:40:41.092121 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5104 00:40:41.098791 0 14 24 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 1)
5105 00:40:41.102416 0 14 28 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
5106 00:40:41.105803 0 15 0 | B1->B0 | 2c2c 2323 | 0 0 | (1 0) (0 0)
5107 00:40:41.112020 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5108 00:40:41.115383 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5109 00:40:41.118686 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5110 00:40:41.124943 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5111 00:40:41.128375 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5112 00:40:41.131849 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5113 00:40:41.138810 0 15 28 | B1->B0 | 2626 4545 | 0 0 | (0 0) (0 0)
5114 00:40:41.142088 1 0 0 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
5115 00:40:41.145297 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5116 00:40:41.151829 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5117 00:40:41.154951 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5118 00:40:41.158358 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5119 00:40:41.165164 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5120 00:40:41.168396 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5121 00:40:41.171526 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5122 00:40:41.178308 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5123 00:40:41.181796 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5124 00:40:41.185261 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5125 00:40:41.191785 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5126 00:40:41.195126 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5127 00:40:41.198481 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5128 00:40:41.205164 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5129 00:40:41.208350 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5130 00:40:41.211705 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5131 00:40:41.218336 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5132 00:40:41.221439 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5133 00:40:41.224608 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5134 00:40:41.228270 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5135 00:40:41.235122 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5136 00:40:41.237844 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5137 00:40:41.241664 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5138 00:40:41.244714 Total UI for P1: 0, mck2ui 16
5139 00:40:41.248016 best dqsien dly found for B0: ( 1, 2, 24)
5140 00:40:41.254513 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5141 00:40:41.258285 Total UI for P1: 0, mck2ui 16
5142 00:40:41.261289 best dqsien dly found for B1: ( 1, 2, 28)
5143 00:40:41.264907 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5144 00:40:41.268255 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5145 00:40:41.268323
5146 00:40:41.271426 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5147 00:40:41.274813 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5148 00:40:41.278075 [Gating] SW calibration Done
5149 00:40:41.278148 ==
5150 00:40:41.281355 Dram Type= 6, Freq= 0, CH_0, rank 0
5151 00:40:41.284734 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5152 00:40:41.284800 ==
5153 00:40:41.288160 RX Vref Scan: 0
5154 00:40:41.288225
5155 00:40:41.288279 RX Vref 0 -> 0, step: 1
5156 00:40:41.291577
5157 00:40:41.291642 RX Delay -80 -> 252, step: 8
5158 00:40:41.298230 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5159 00:40:41.300920 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5160 00:40:41.304191 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5161 00:40:41.307605 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5162 00:40:41.310968 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5163 00:40:41.314257 iDelay=208, Bit 5, Center 95 (8 ~ 183) 176
5164 00:40:41.320935 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5165 00:40:41.324351 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5166 00:40:41.327552 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5167 00:40:41.330889 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5168 00:40:41.334143 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5169 00:40:41.338007 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5170 00:40:41.344690 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5171 00:40:41.347477 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5172 00:40:41.351248 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5173 00:40:41.354290 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5174 00:40:41.354356 ==
5175 00:40:41.357912 Dram Type= 6, Freq= 0, CH_0, rank 0
5176 00:40:41.361295 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5177 00:40:41.364553 ==
5178 00:40:41.364628 DQS Delay:
5179 00:40:41.364686 DQS0 = 0, DQS1 = 0
5180 00:40:41.367662 DQM Delay:
5181 00:40:41.367729 DQM0 = 105, DQM1 = 95
5182 00:40:41.370723 DQ Delay:
5183 00:40:41.374329 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5184 00:40:41.377530 DQ4 =107, DQ5 =95, DQ6 =115, DQ7 =115
5185 00:40:41.380840 DQ8 =83, DQ9 =87, DQ10 =95, DQ11 =91
5186 00:40:41.384068 DQ12 =99, DQ13 =103, DQ14 =103, DQ15 =99
5187 00:40:41.384143
5188 00:40:41.384200
5189 00:40:41.384253 ==
5190 00:40:41.387575 Dram Type= 6, Freq= 0, CH_0, rank 0
5191 00:40:41.390867 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5192 00:40:41.390942 ==
5193 00:40:41.391000
5194 00:40:41.391053
5195 00:40:41.394314 TX Vref Scan disable
5196 00:40:41.394388 == TX Byte 0 ==
5197 00:40:41.401090 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5198 00:40:41.404152 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5199 00:40:41.404226 == TX Byte 1 ==
5200 00:40:41.410642 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5201 00:40:41.414010 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5202 00:40:41.414082 ==
5203 00:40:41.417280 Dram Type= 6, Freq= 0, CH_0, rank 0
5204 00:40:41.420668 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5205 00:40:41.420734 ==
5206 00:40:41.424100
5207 00:40:41.424167
5208 00:40:41.424226 TX Vref Scan disable
5209 00:40:41.427363 == TX Byte 0 ==
5210 00:40:41.430710 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5211 00:40:41.434007 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5212 00:40:41.437409 == TX Byte 1 ==
5213 00:40:41.440740 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5214 00:40:41.447418 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5215 00:40:41.447488
5216 00:40:41.447549 [DATLAT]
5217 00:40:41.447602 Freq=933, CH0 RK0
5218 00:40:41.447653
5219 00:40:41.450757 DATLAT Default: 0xd
5220 00:40:41.450823 0, 0xFFFF, sum = 0
5221 00:40:41.453946 1, 0xFFFF, sum = 0
5222 00:40:41.454013 2, 0xFFFF, sum = 0
5223 00:40:41.456940 3, 0xFFFF, sum = 0
5224 00:40:41.460179 4, 0xFFFF, sum = 0
5225 00:40:41.460248 5, 0xFFFF, sum = 0
5226 00:40:41.464018 6, 0xFFFF, sum = 0
5227 00:40:41.464087 7, 0xFFFF, sum = 0
5228 00:40:41.466919 8, 0xFFFF, sum = 0
5229 00:40:41.466988 9, 0xFFFF, sum = 0
5230 00:40:41.470505 10, 0x0, sum = 1
5231 00:40:41.470578 11, 0x0, sum = 2
5232 00:40:41.473918 12, 0x0, sum = 3
5233 00:40:41.473987 13, 0x0, sum = 4
5234 00:40:41.474044 best_step = 11
5235 00:40:41.474095
5236 00:40:41.477363 ==
5237 00:40:41.480344 Dram Type= 6, Freq= 0, CH_0, rank 0
5238 00:40:41.483596 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5239 00:40:41.483669 ==
5240 00:40:41.483728 RX Vref Scan: 1
5241 00:40:41.483780
5242 00:40:41.487062 RX Vref 0 -> 0, step: 1
5243 00:40:41.487128
5244 00:40:41.490582 RX Delay -53 -> 252, step: 4
5245 00:40:41.490651
5246 00:40:41.493748 Set Vref, RX VrefLevel [Byte0]: 55
5247 00:40:41.497033 [Byte1]: 50
5248 00:40:41.497102
5249 00:40:41.500438 Final RX Vref Byte 0 = 55 to rank0
5250 00:40:41.503817 Final RX Vref Byte 1 = 50 to rank0
5251 00:40:41.507179 Final RX Vref Byte 0 = 55 to rank1
5252 00:40:41.510384 Final RX Vref Byte 1 = 50 to rank1==
5253 00:40:41.513484 Dram Type= 6, Freq= 0, CH_0, rank 0
5254 00:40:41.517345 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5255 00:40:41.517450 ==
5256 00:40:41.519974 DQS Delay:
5257 00:40:41.520039 DQS0 = 0, DQS1 = 0
5258 00:40:41.523959 DQM Delay:
5259 00:40:41.524029 DQM0 = 104, DQM1 = 95
5260 00:40:41.526736 DQ Delay:
5261 00:40:41.530104 DQ0 =104, DQ1 =104, DQ2 =102, DQ3 =102
5262 00:40:41.533359 DQ4 =104, DQ5 =96, DQ6 =112, DQ7 =110
5263 00:40:41.536709 DQ8 =84, DQ9 =86, DQ10 =96, DQ11 =90
5264 00:40:41.540123 DQ12 =100, DQ13 =98, DQ14 =106, DQ15 =104
5265 00:40:41.540193
5266 00:40:41.540249
5267 00:40:41.546858 [DQSOSCAuto] RK0, (LSB)MR18= 0x322a, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 406 ps
5268 00:40:41.550203 CH0 RK0: MR19=505, MR18=322A
5269 00:40:41.557043 CH0_RK0: MR19=0x505, MR18=0x322A, DQSOSC=406, MR23=63, INC=65, DEC=43
5270 00:40:41.557112
5271 00:40:41.560345 ----->DramcWriteLeveling(PI) begin...
5272 00:40:41.560414 ==
5273 00:40:41.563600 Dram Type= 6, Freq= 0, CH_0, rank 1
5274 00:40:41.566769 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5275 00:40:41.566850 ==
5276 00:40:41.570150 Write leveling (Byte 0): 33 => 33
5277 00:40:41.573527 Write leveling (Byte 1): 28 => 28
5278 00:40:41.576961 DramcWriteLeveling(PI) end<-----
5279 00:40:41.577029
5280 00:40:41.577085 ==
5281 00:40:41.580194 Dram Type= 6, Freq= 0, CH_0, rank 1
5282 00:40:41.583194 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5283 00:40:41.583257 ==
5284 00:40:41.586678 [Gating] SW mode calibration
5285 00:40:41.593333 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5286 00:40:41.599956 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5287 00:40:41.603477 0 14 0 | B1->B0 | 3232 3232 | 0 0 | (0 0) (0 0)
5288 00:40:41.610005 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5289 00:40:41.613664 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5290 00:40:41.616835 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5291 00:40:41.623310 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5292 00:40:41.626549 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5293 00:40:41.629619 0 14 24 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5294 00:40:41.636871 0 14 28 | B1->B0 | 2424 2d2d | 1 0 | (1 1) (0 0)
5295 00:40:41.639429 0 15 0 | B1->B0 | 2424 2424 | 0 0 | (0 0) (0 0)
5296 00:40:41.642798 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5297 00:40:41.649759 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5298 00:40:41.652773 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5299 00:40:41.656152 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5300 00:40:41.662796 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5301 00:40:41.666068 0 15 24 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
5302 00:40:41.669388 0 15 28 | B1->B0 | 3c3c 3939 | 0 0 | (0 0) (0 0)
5303 00:40:41.675856 1 0 0 | B1->B0 | 4646 4040 | 0 1 | (0 0) (0 0)
5304 00:40:41.679367 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5305 00:40:41.682885 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5306 00:40:41.686218 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5307 00:40:41.692946 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5308 00:40:41.696048 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5309 00:40:41.699190 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5310 00:40:41.705675 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5311 00:40:41.709146 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5312 00:40:41.712950 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5313 00:40:41.719079 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5314 00:40:41.722708 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5315 00:40:41.725916 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5316 00:40:41.732108 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5317 00:40:41.735514 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5318 00:40:41.739183 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5319 00:40:41.746037 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5320 00:40:41.748685 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5321 00:40:41.752230 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5322 00:40:41.758879 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5323 00:40:41.762702 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5324 00:40:41.765381 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5325 00:40:41.772247 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5326 00:40:41.775501 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5327 00:40:41.778738 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5328 00:40:41.782116 Total UI for P1: 0, mck2ui 16
5329 00:40:41.785411 best dqsien dly found for B0: ( 1, 2, 28)
5330 00:40:41.788868 Total UI for P1: 0, mck2ui 16
5331 00:40:41.792286 best dqsien dly found for B1: ( 1, 2, 28)
5332 00:40:41.795760 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5333 00:40:41.799548 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5334 00:40:41.799619
5335 00:40:41.805415 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5336 00:40:41.808823 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5337 00:40:41.808890 [Gating] SW calibration Done
5338 00:40:41.812106 ==
5339 00:40:41.815223 Dram Type= 6, Freq= 0, CH_0, rank 1
5340 00:40:41.818805 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5341 00:40:41.818873 ==
5342 00:40:41.818929 RX Vref Scan: 0
5343 00:40:41.818981
5344 00:40:41.822241 RX Vref 0 -> 0, step: 1
5345 00:40:41.822308
5346 00:40:41.825475 RX Delay -80 -> 252, step: 8
5347 00:40:41.828801 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5348 00:40:41.832003 iDelay=208, Bit 1, Center 111 (24 ~ 199) 176
5349 00:40:41.835332 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5350 00:40:41.841798 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5351 00:40:41.845320 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5352 00:40:41.848796 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5353 00:40:41.852162 iDelay=208, Bit 6, Center 111 (24 ~ 199) 176
5354 00:40:41.855029 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5355 00:40:41.858584 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5356 00:40:41.865308 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5357 00:40:41.868600 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5358 00:40:41.871488 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5359 00:40:41.874846 iDelay=208, Bit 12, Center 95 (8 ~ 183) 176
5360 00:40:41.878484 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5361 00:40:41.882030 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5362 00:40:41.888072 iDelay=208, Bit 15, Center 103 (16 ~ 191) 176
5363 00:40:41.888167 ==
5364 00:40:41.891611 Dram Type= 6, Freq= 0, CH_0, rank 1
5365 00:40:41.895163 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5366 00:40:41.895252 ==
5367 00:40:41.895335 DQS Delay:
5368 00:40:41.898672 DQS0 = 0, DQS1 = 0
5369 00:40:41.898758 DQM Delay:
5370 00:40:41.901443 DQM0 = 105, DQM1 = 94
5371 00:40:41.901533 DQ Delay:
5372 00:40:41.904930 DQ0 =103, DQ1 =111, DQ2 =99, DQ3 =99
5373 00:40:41.908232 DQ4 =107, DQ5 =95, DQ6 =111, DQ7 =115
5374 00:40:41.911800 DQ8 =87, DQ9 =87, DQ10 =95, DQ11 =87
5375 00:40:41.915225 DQ12 =95, DQ13 =99, DQ14 =103, DQ15 =103
5376 00:40:41.915301
5377 00:40:41.915360
5378 00:40:41.915415 ==
5379 00:40:41.917974 Dram Type= 6, Freq= 0, CH_0, rank 1
5380 00:40:41.925055 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5381 00:40:41.925131 ==
5382 00:40:41.925191
5383 00:40:41.925271
5384 00:40:41.925353 TX Vref Scan disable
5385 00:40:41.928628 == TX Byte 0 ==
5386 00:40:41.932127 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5387 00:40:41.935222 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5388 00:40:41.938902 == TX Byte 1 ==
5389 00:40:41.941696 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5390 00:40:41.945241 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5391 00:40:41.948467 ==
5392 00:40:41.952282 Dram Type= 6, Freq= 0, CH_0, rank 1
5393 00:40:41.955541 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5394 00:40:41.955619 ==
5395 00:40:41.955678
5396 00:40:41.955735
5397 00:40:41.958847 TX Vref Scan disable
5398 00:40:41.958923 == TX Byte 0 ==
5399 00:40:41.965070 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5400 00:40:41.968655 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5401 00:40:41.968731 == TX Byte 1 ==
5402 00:40:41.975187 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5403 00:40:41.978503 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5404 00:40:41.978579
5405 00:40:41.978638 [DATLAT]
5406 00:40:41.981898 Freq=933, CH0 RK1
5407 00:40:41.981974
5408 00:40:41.982033 DATLAT Default: 0xb
5409 00:40:41.984819 0, 0xFFFF, sum = 0
5410 00:40:41.984902 1, 0xFFFF, sum = 0
5411 00:40:41.988164 2, 0xFFFF, sum = 0
5412 00:40:41.988260 3, 0xFFFF, sum = 0
5413 00:40:41.991433 4, 0xFFFF, sum = 0
5414 00:40:41.991548 5, 0xFFFF, sum = 0
5415 00:40:41.994800 6, 0xFFFF, sum = 0
5416 00:40:41.994874 7, 0xFFFF, sum = 0
5417 00:40:41.998348 8, 0xFFFF, sum = 0
5418 00:40:42.002031 9, 0xFFFF, sum = 0
5419 00:40:42.002105 10, 0x0, sum = 1
5420 00:40:42.002166 11, 0x0, sum = 2
5421 00:40:42.004903 12, 0x0, sum = 3
5422 00:40:42.004972 13, 0x0, sum = 4
5423 00:40:42.008362 best_step = 11
5424 00:40:42.008430
5425 00:40:42.008487 ==
5426 00:40:42.011921 Dram Type= 6, Freq= 0, CH_0, rank 1
5427 00:40:42.014820 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5428 00:40:42.014893 ==
5429 00:40:42.018299 RX Vref Scan: 0
5430 00:40:42.018373
5431 00:40:42.018431 RX Vref 0 -> 0, step: 1
5432 00:40:42.018485
5433 00:40:42.021787 RX Delay -45 -> 252, step: 4
5434 00:40:42.029230 iDelay=199, Bit 0, Center 102 (15 ~ 190) 176
5435 00:40:42.032524 iDelay=199, Bit 1, Center 106 (23 ~ 190) 168
5436 00:40:42.035552 iDelay=199, Bit 2, Center 102 (15 ~ 190) 176
5437 00:40:42.038841 iDelay=199, Bit 3, Center 102 (15 ~ 190) 176
5438 00:40:42.042146 iDelay=199, Bit 4, Center 106 (19 ~ 194) 176
5439 00:40:42.048760 iDelay=199, Bit 5, Center 96 (7 ~ 186) 180
5440 00:40:42.052011 iDelay=199, Bit 6, Center 110 (27 ~ 194) 168
5441 00:40:42.055170 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5442 00:40:42.058749 iDelay=199, Bit 8, Center 86 (3 ~ 170) 168
5443 00:40:42.062299 iDelay=199, Bit 9, Center 82 (-1 ~ 166) 168
5444 00:40:42.068533 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5445 00:40:42.071848 iDelay=199, Bit 11, Center 90 (11 ~ 170) 160
5446 00:40:42.075289 iDelay=199, Bit 12, Center 98 (15 ~ 182) 168
5447 00:40:42.078654 iDelay=199, Bit 13, Center 98 (15 ~ 182) 168
5448 00:40:42.081679 iDelay=199, Bit 14, Center 102 (19 ~ 186) 168
5449 00:40:42.088618 iDelay=199, Bit 15, Center 102 (19 ~ 186) 168
5450 00:40:42.088690 ==
5451 00:40:42.092033 Dram Type= 6, Freq= 0, CH_0, rank 1
5452 00:40:42.095207 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5453 00:40:42.095284 ==
5454 00:40:42.095342 DQS Delay:
5455 00:40:42.098248 DQS0 = 0, DQS1 = 0
5456 00:40:42.098318 DQM Delay:
5457 00:40:42.101984 DQM0 = 104, DQM1 = 94
5458 00:40:42.102079 DQ Delay:
5459 00:40:42.105436 DQ0 =102, DQ1 =106, DQ2 =102, DQ3 =102
5460 00:40:42.108297 DQ4 =106, DQ5 =96, DQ6 =110, DQ7 =112
5461 00:40:42.111597 DQ8 =86, DQ9 =82, DQ10 =94, DQ11 =90
5462 00:40:42.115547 DQ12 =98, DQ13 =98, DQ14 =102, DQ15 =102
5463 00:40:42.115621
5464 00:40:42.115679
5465 00:40:42.124878 [DQSOSCAuto] RK1, (LSB)MR18= 0x2e07, (MSB)MR19= 0x505, tDQSOscB0 = 419 ps tDQSOscB1 = 407 ps
5466 00:40:42.124954 CH0 RK1: MR19=505, MR18=2E07
5467 00:40:42.131523 CH0_RK1: MR19=0x505, MR18=0x2E07, DQSOSC=407, MR23=63, INC=65, DEC=43
5468 00:40:42.134979 [RxdqsGatingPostProcess] freq 933
5469 00:40:42.142025 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5470 00:40:42.145115 best DQS0 dly(2T, 0.5T) = (0, 10)
5471 00:40:42.148585 best DQS1 dly(2T, 0.5T) = (0, 10)
5472 00:40:42.151789 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5473 00:40:42.155200 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5474 00:40:42.158560 best DQS0 dly(2T, 0.5T) = (0, 10)
5475 00:40:42.161743 best DQS1 dly(2T, 0.5T) = (0, 10)
5476 00:40:42.161817 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5477 00:40:42.165097 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5478 00:40:42.168476 Pre-setting of DQS Precalculation
5479 00:40:42.174940 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5480 00:40:42.175014 ==
5481 00:40:42.178547 Dram Type= 6, Freq= 0, CH_1, rank 0
5482 00:40:42.181461 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5483 00:40:42.181581 ==
5484 00:40:42.188220 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5485 00:40:42.194828 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5486 00:40:42.197912 [CA 0] Center 36 (6~67) winsize 62
5487 00:40:42.201537 [CA 1] Center 36 (6~67) winsize 62
5488 00:40:42.204821 [CA 2] Center 34 (4~65) winsize 62
5489 00:40:42.208321 [CA 3] Center 34 (4~65) winsize 62
5490 00:40:42.211233 [CA 4] Center 34 (4~64) winsize 61
5491 00:40:42.214768 [CA 5] Center 33 (3~64) winsize 62
5492 00:40:42.214838
5493 00:40:42.218134 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5494 00:40:42.218232
5495 00:40:42.221266 [CATrainingPosCal] consider 1 rank data
5496 00:40:42.224453 u2DelayCellTimex100 = 270/100 ps
5497 00:40:42.227859 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5498 00:40:42.231248 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5499 00:40:42.234738 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5500 00:40:42.238144 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5501 00:40:42.241572 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5502 00:40:42.244916 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5503 00:40:42.244980
5504 00:40:42.248053 CA PerBit enable=1, Macro0, CA PI delay=33
5505 00:40:42.251398
5506 00:40:42.251465 [CBTSetCACLKResult] CA Dly = 33
5507 00:40:42.254533 CS Dly: 7 (0~38)
5508 00:40:42.254599 ==
5509 00:40:42.257952 Dram Type= 6, Freq= 0, CH_1, rank 1
5510 00:40:42.261256 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5511 00:40:42.261322 ==
5512 00:40:42.268411 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5513 00:40:42.274636 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5514 00:40:42.278158 [CA 0] Center 36 (6~67) winsize 62
5515 00:40:42.281389 [CA 1] Center 37 (6~68) winsize 63
5516 00:40:42.284575 [CA 2] Center 35 (4~66) winsize 63
5517 00:40:42.288245 [CA 3] Center 34 (4~65) winsize 62
5518 00:40:42.291295 [CA 4] Center 34 (4~65) winsize 62
5519 00:40:42.294838 [CA 5] Center 34 (4~64) winsize 61
5520 00:40:42.294913
5521 00:40:42.298349 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5522 00:40:42.298467
5523 00:40:42.301187 [CATrainingPosCal] consider 2 rank data
5524 00:40:42.304543 u2DelayCellTimex100 = 270/100 ps
5525 00:40:42.308047 CA0 delay=36 (6~67),Diff = 2 PI (12 cell)
5526 00:40:42.311603 CA1 delay=36 (6~67),Diff = 2 PI (12 cell)
5527 00:40:42.314388 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
5528 00:40:42.318010 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5529 00:40:42.321360 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5530 00:40:42.324885 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5531 00:40:42.324995
5532 00:40:42.331216 CA PerBit enable=1, Macro0, CA PI delay=34
5533 00:40:42.331321
5534 00:40:42.331419 [CBTSetCACLKResult] CA Dly = 34
5535 00:40:42.334387 CS Dly: 8 (0~40)
5536 00:40:42.334477
5537 00:40:42.338010 ----->DramcWriteLeveling(PI) begin...
5538 00:40:42.338100 ==
5539 00:40:42.341489 Dram Type= 6, Freq= 0, CH_1, rank 0
5540 00:40:42.344889 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5541 00:40:42.344967 ==
5542 00:40:42.347609 Write leveling (Byte 0): 25 => 25
5543 00:40:42.351042 Write leveling (Byte 1): 29 => 29
5544 00:40:42.354208 DramcWriteLeveling(PI) end<-----
5545 00:40:42.354279
5546 00:40:42.354338 ==
5547 00:40:42.357594 Dram Type= 6, Freq= 0, CH_1, rank 0
5548 00:40:42.361385 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5549 00:40:42.361459 ==
5550 00:40:42.364711 [Gating] SW mode calibration
5551 00:40:42.371486 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5552 00:40:42.377790 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5553 00:40:42.381154 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5554 00:40:42.388229 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5555 00:40:42.391447 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5556 00:40:42.394897 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5557 00:40:42.398278 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5558 00:40:42.404588 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5559 00:40:42.407723 0 14 24 | B1->B0 | 3232 2f2f | 0 0 | (0 1) (1 0)
5560 00:40:42.411366 0 14 28 | B1->B0 | 2525 2323 | 0 0 | (0 0) (1 0)
5561 00:40:42.418078 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5562 00:40:42.421277 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5563 00:40:42.424549 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5564 00:40:42.431302 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5565 00:40:42.434835 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5566 00:40:42.438183 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5567 00:40:42.444693 0 15 24 | B1->B0 | 2727 3636 | 0 0 | (0 0) (0 0)
5568 00:40:42.447917 0 15 28 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
5569 00:40:42.451504 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5570 00:40:42.458101 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5571 00:40:42.461756 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5572 00:40:42.465006 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5573 00:40:42.471275 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5574 00:40:42.474413 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5575 00:40:42.478137 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5576 00:40:42.485042 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5577 00:40:42.487695 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5578 00:40:42.491098 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5579 00:40:42.497904 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5580 00:40:42.501290 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5581 00:40:42.504682 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5582 00:40:42.511335 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5583 00:40:42.514741 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5584 00:40:42.518064 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5585 00:40:42.521271 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5586 00:40:42.528005 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5587 00:40:42.531278 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5588 00:40:42.534775 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5589 00:40:42.541166 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5590 00:40:42.544572 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5591 00:40:42.547876 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5592 00:40:42.551381 Total UI for P1: 0, mck2ui 16
5593 00:40:42.554738 best dqsien dly found for B0: ( 1, 2, 22)
5594 00:40:42.561472 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5595 00:40:42.561574 Total UI for P1: 0, mck2ui 16
5596 00:40:42.567764 best dqsien dly found for B1: ( 1, 2, 24)
5597 00:40:42.570994 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5598 00:40:42.574349 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5599 00:40:42.574437
5600 00:40:42.577576 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5601 00:40:42.581179 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5602 00:40:42.584471 [Gating] SW calibration Done
5603 00:40:42.584546 ==
5604 00:40:42.587686 Dram Type= 6, Freq= 0, CH_1, rank 0
5605 00:40:42.591143 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5606 00:40:42.591219 ==
5607 00:40:42.594306 RX Vref Scan: 0
5608 00:40:42.594383
5609 00:40:42.594442 RX Vref 0 -> 0, step: 1
5610 00:40:42.594497
5611 00:40:42.597668 RX Delay -80 -> 252, step: 8
5612 00:40:42.600948 iDelay=208, Bit 0, Center 111 (24 ~ 199) 176
5613 00:40:42.607656 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5614 00:40:42.610889 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5615 00:40:42.614236 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5616 00:40:42.617785 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5617 00:40:42.621222 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5618 00:40:42.624692 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5619 00:40:42.631001 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5620 00:40:42.634136 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5621 00:40:42.638080 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5622 00:40:42.641236 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5623 00:40:42.644843 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5624 00:40:42.647779 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5625 00:40:42.654900 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5626 00:40:42.658062 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5627 00:40:42.661414 iDelay=208, Bit 15, Center 103 (16 ~ 191) 176
5628 00:40:42.661509 ==
5629 00:40:42.664796 Dram Type= 6, Freq= 0, CH_1, rank 0
5630 00:40:42.667654 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5631 00:40:42.667746 ==
5632 00:40:42.671333 DQS Delay:
5633 00:40:42.671430 DQS0 = 0, DQS1 = 0
5634 00:40:42.674583 DQM Delay:
5635 00:40:42.674680 DQM0 = 103, DQM1 = 97
5636 00:40:42.674764 DQ Delay:
5637 00:40:42.677927 DQ0 =111, DQ1 =95, DQ2 =91, DQ3 =99
5638 00:40:42.681376 DQ4 =99, DQ5 =115, DQ6 =115, DQ7 =103
5639 00:40:42.684237 DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =91
5640 00:40:42.691028 DQ12 =107, DQ13 =103, DQ14 =103, DQ15 =103
5641 00:40:42.691108
5642 00:40:42.691172
5643 00:40:42.691230 ==
5644 00:40:42.694218 Dram Type= 6, Freq= 0, CH_1, rank 0
5645 00:40:42.698058 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5646 00:40:42.698140 ==
5647 00:40:42.698201
5648 00:40:42.698256
5649 00:40:42.701111 TX Vref Scan disable
5650 00:40:42.701183 == TX Byte 0 ==
5651 00:40:42.707687 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5652 00:40:42.710904 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5653 00:40:42.711003 == TX Byte 1 ==
5654 00:40:42.717696 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5655 00:40:42.721002 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5656 00:40:42.721096 ==
5657 00:40:42.724225 Dram Type= 6, Freq= 0, CH_1, rank 0
5658 00:40:42.727780 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5659 00:40:42.727883 ==
5660 00:40:42.727969
5661 00:40:42.728042
5662 00:40:42.731037 TX Vref Scan disable
5663 00:40:42.734714 == TX Byte 0 ==
5664 00:40:42.737903 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5665 00:40:42.741315 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5666 00:40:42.743994 == TX Byte 1 ==
5667 00:40:42.747614 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5668 00:40:42.751064 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5669 00:40:42.751141
5670 00:40:42.754289 [DATLAT]
5671 00:40:42.754403 Freq=933, CH1 RK0
5672 00:40:42.754469
5673 00:40:42.757459 DATLAT Default: 0xd
5674 00:40:42.757563 0, 0xFFFF, sum = 0
5675 00:40:42.761153 1, 0xFFFF, sum = 0
5676 00:40:42.761224 2, 0xFFFF, sum = 0
5677 00:40:42.763906 3, 0xFFFF, sum = 0
5678 00:40:42.763978 4, 0xFFFF, sum = 0
5679 00:40:42.767810 5, 0xFFFF, sum = 0
5680 00:40:42.767895 6, 0xFFFF, sum = 0
5681 00:40:42.770986 7, 0xFFFF, sum = 0
5682 00:40:42.771056 8, 0xFFFF, sum = 0
5683 00:40:42.774122 9, 0xFFFF, sum = 0
5684 00:40:42.774223 10, 0x0, sum = 1
5685 00:40:42.777592 11, 0x0, sum = 2
5686 00:40:42.777669 12, 0x0, sum = 3
5687 00:40:42.780413 13, 0x0, sum = 4
5688 00:40:42.780481 best_step = 11
5689 00:40:42.780545
5690 00:40:42.780609 ==
5691 00:40:42.783783 Dram Type= 6, Freq= 0, CH_1, rank 0
5692 00:40:42.790502 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5693 00:40:42.790572 ==
5694 00:40:42.790636 RX Vref Scan: 1
5695 00:40:42.790690
5696 00:40:42.794090 RX Vref 0 -> 0, step: 1
5697 00:40:42.794160
5698 00:40:42.797428 RX Delay -45 -> 252, step: 4
5699 00:40:42.797516
5700 00:40:42.800770 Set Vref, RX VrefLevel [Byte0]: 56
5701 00:40:42.804037 [Byte1]: 52
5702 00:40:42.804114
5703 00:40:42.807591 Final RX Vref Byte 0 = 56 to rank0
5704 00:40:42.810363 Final RX Vref Byte 1 = 52 to rank0
5705 00:40:42.813730 Final RX Vref Byte 0 = 56 to rank1
5706 00:40:42.817028 Final RX Vref Byte 1 = 52 to rank1==
5707 00:40:42.820392 Dram Type= 6, Freq= 0, CH_1, rank 0
5708 00:40:42.824195 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5709 00:40:42.824272 ==
5710 00:40:42.827277 DQS Delay:
5711 00:40:42.827350 DQS0 = 0, DQS1 = 0
5712 00:40:42.827408 DQM Delay:
5713 00:40:42.830637 DQM0 = 103, DQM1 = 100
5714 00:40:42.830738 DQ Delay:
5715 00:40:42.833608 DQ0 =106, DQ1 =98, DQ2 =94, DQ3 =102
5716 00:40:42.837164 DQ4 =102, DQ5 =112, DQ6 =112, DQ7 =104
5717 00:40:42.840693 DQ8 =88, DQ9 =90, DQ10 =98, DQ11 =92
5718 00:40:42.844149 DQ12 =108, DQ13 =108, DQ14 =108, DQ15 =108
5719 00:40:42.847280
5720 00:40:42.847351
5721 00:40:42.853855 [DQSOSCAuto] RK0, (LSB)MR18= 0x1930, (MSB)MR19= 0x505, tDQSOscB0 = 406 ps tDQSOscB1 = 413 ps
5722 00:40:42.857143 CH1 RK0: MR19=505, MR18=1930
5723 00:40:42.863356 CH1_RK0: MR19=0x505, MR18=0x1930, DQSOSC=406, MR23=63, INC=65, DEC=43
5724 00:40:42.863437
5725 00:40:42.866829 ----->DramcWriteLeveling(PI) begin...
5726 00:40:42.866909 ==
5727 00:40:42.870458 Dram Type= 6, Freq= 0, CH_1, rank 1
5728 00:40:42.873650 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5729 00:40:42.873728 ==
5730 00:40:42.877500 Write leveling (Byte 0): 26 => 26
5731 00:40:42.880584 Write leveling (Byte 1): 29 => 29
5732 00:40:42.883560 DramcWriteLeveling(PI) end<-----
5733 00:40:42.883654
5734 00:40:42.883724 ==
5735 00:40:42.886844 Dram Type= 6, Freq= 0, CH_1, rank 1
5736 00:40:42.890184 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5737 00:40:42.890260 ==
5738 00:40:42.893375 [Gating] SW mode calibration
5739 00:40:42.900321 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5740 00:40:42.906465 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5741 00:40:42.909872 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5742 00:40:42.913447 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5743 00:40:42.920441 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5744 00:40:42.923758 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5745 00:40:42.927288 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5746 00:40:42.933476 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5747 00:40:42.936937 0 14 24 | B1->B0 | 2f2f 3333 | 1 0 | (1 0) (0 1)
5748 00:40:42.940239 0 14 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
5749 00:40:42.947056 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5750 00:40:42.950410 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5751 00:40:42.953656 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5752 00:40:42.959730 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5753 00:40:42.963087 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5754 00:40:42.966829 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5755 00:40:42.973125 0 15 24 | B1->B0 | 3737 2c2c | 0 0 | (0 0) (0 0)
5756 00:40:42.976489 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5757 00:40:42.979859 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5758 00:40:42.986224 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5759 00:40:42.989626 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5760 00:40:42.992998 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5761 00:40:42.999538 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5762 00:40:43.003145 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5763 00:40:43.006218 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5764 00:40:43.013110 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5765 00:40:43.016396 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5766 00:40:43.019830 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5767 00:40:43.026294 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5768 00:40:43.029799 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5769 00:40:43.033131 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5770 00:40:43.039870 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5771 00:40:43.043195 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5772 00:40:43.046682 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5773 00:40:43.049707 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5774 00:40:43.056360 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5775 00:40:43.059324 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5776 00:40:43.062708 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5777 00:40:43.069990 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5778 00:40:43.073202 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5779 00:40:43.076313 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5780 00:40:43.082735 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5781 00:40:43.085983 Total UI for P1: 0, mck2ui 16
5782 00:40:43.089854 best dqsien dly found for B1: ( 1, 2, 24)
5783 00:40:43.092687 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5784 00:40:43.096112 Total UI for P1: 0, mck2ui 16
5785 00:40:43.099633 best dqsien dly found for B0: ( 1, 2, 26)
5786 00:40:43.103083 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5787 00:40:43.106362 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5788 00:40:43.106460
5789 00:40:43.109759 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5790 00:40:43.113081 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5791 00:40:43.116536 [Gating] SW calibration Done
5792 00:40:43.116602 ==
5793 00:40:43.119300 Dram Type= 6, Freq= 0, CH_1, rank 1
5794 00:40:43.122587 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5795 00:40:43.126241 ==
5796 00:40:43.126310 RX Vref Scan: 0
5797 00:40:43.126368
5798 00:40:43.129668 RX Vref 0 -> 0, step: 1
5799 00:40:43.129736
5800 00:40:43.132524 RX Delay -80 -> 252, step: 8
5801 00:40:43.135836 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5802 00:40:43.139725 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5803 00:40:43.142796 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5804 00:40:43.146150 iDelay=208, Bit 3, Center 95 (8 ~ 183) 176
5805 00:40:43.149615 iDelay=208, Bit 4, Center 95 (8 ~ 183) 176
5806 00:40:43.156326 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5807 00:40:43.159813 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5808 00:40:43.162545 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5809 00:40:43.166078 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5810 00:40:43.169263 iDelay=208, Bit 9, Center 91 (0 ~ 183) 184
5811 00:40:43.172297 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5812 00:40:43.179150 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5813 00:40:43.182610 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5814 00:40:43.185997 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5815 00:40:43.189280 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5816 00:40:43.192376 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5817 00:40:43.195487 ==
5818 00:40:43.195550 Dram Type= 6, Freq= 0, CH_1, rank 1
5819 00:40:43.202271 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5820 00:40:43.202337 ==
5821 00:40:43.202392 DQS Delay:
5822 00:40:43.205826 DQS0 = 0, DQS1 = 0
5823 00:40:43.205892 DQM Delay:
5824 00:40:43.209333 DQM0 = 102, DQM1 = 98
5825 00:40:43.209408 DQ Delay:
5826 00:40:43.212266 DQ0 =107, DQ1 =99, DQ2 =91, DQ3 =95
5827 00:40:43.216051 DQ4 =95, DQ5 =115, DQ6 =115, DQ7 =99
5828 00:40:43.219434 DQ8 =87, DQ9 =91, DQ10 =99, DQ11 =91
5829 00:40:43.222856 DQ12 =107, DQ13 =103, DQ14 =103, DQ15 =107
5830 00:40:43.222957
5831 00:40:43.223042
5832 00:40:43.223123 ==
5833 00:40:43.225657 Dram Type= 6, Freq= 0, CH_1, rank 1
5834 00:40:43.228976 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5835 00:40:43.229054 ==
5836 00:40:43.229116
5837 00:40:43.232395
5838 00:40:43.232472 TX Vref Scan disable
5839 00:40:43.235823 == TX Byte 0 ==
5840 00:40:43.239181 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5841 00:40:43.242425 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5842 00:40:43.245669 == TX Byte 1 ==
5843 00:40:43.249340 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5844 00:40:43.252431 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5845 00:40:43.252511 ==
5846 00:40:43.255818 Dram Type= 6, Freq= 0, CH_1, rank 1
5847 00:40:43.262214 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5848 00:40:43.262292 ==
5849 00:40:43.262352
5850 00:40:43.262407
5851 00:40:43.262459 TX Vref Scan disable
5852 00:40:43.266365 == TX Byte 0 ==
5853 00:40:43.269839 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5854 00:40:43.276182 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5855 00:40:43.276259 == TX Byte 1 ==
5856 00:40:43.279975 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5857 00:40:43.286453 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5858 00:40:43.286529
5859 00:40:43.286586 [DATLAT]
5860 00:40:43.286639 Freq=933, CH1 RK1
5861 00:40:43.286692
5862 00:40:43.289918 DATLAT Default: 0xb
5863 00:40:43.289982 0, 0xFFFF, sum = 0
5864 00:40:43.292606 1, 0xFFFF, sum = 0
5865 00:40:43.296002 2, 0xFFFF, sum = 0
5866 00:40:43.296068 3, 0xFFFF, sum = 0
5867 00:40:43.299325 4, 0xFFFF, sum = 0
5868 00:40:43.299392 5, 0xFFFF, sum = 0
5869 00:40:43.302733 6, 0xFFFF, sum = 0
5870 00:40:43.302803 7, 0xFFFF, sum = 0
5871 00:40:43.305918 8, 0xFFFF, sum = 0
5872 00:40:43.305982 9, 0xFFFF, sum = 0
5873 00:40:43.309225 10, 0x0, sum = 1
5874 00:40:43.309290 11, 0x0, sum = 2
5875 00:40:43.312670 12, 0x0, sum = 3
5876 00:40:43.312741 13, 0x0, sum = 4
5877 00:40:43.312797 best_step = 11
5878 00:40:43.312861
5879 00:40:43.316243 ==
5880 00:40:43.319376 Dram Type= 6, Freq= 0, CH_1, rank 1
5881 00:40:43.323184 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5882 00:40:43.323291 ==
5883 00:40:43.323352 RX Vref Scan: 0
5884 00:40:43.323407
5885 00:40:43.326304 RX Vref 0 -> 0, step: 1
5886 00:40:43.326379
5887 00:40:43.329272 RX Delay -45 -> 252, step: 4
5888 00:40:43.332645 iDelay=203, Bit 0, Center 110 (27 ~ 194) 168
5889 00:40:43.339482 iDelay=203, Bit 1, Center 100 (15 ~ 186) 172
5890 00:40:43.343021 iDelay=203, Bit 2, Center 94 (11 ~ 178) 168
5891 00:40:43.345786 iDelay=203, Bit 3, Center 100 (19 ~ 182) 164
5892 00:40:43.349269 iDelay=203, Bit 4, Center 100 (19 ~ 182) 164
5893 00:40:43.352559 iDelay=203, Bit 5, Center 116 (31 ~ 202) 172
5894 00:40:43.359229 iDelay=203, Bit 6, Center 114 (31 ~ 198) 168
5895 00:40:43.362538 iDelay=203, Bit 7, Center 104 (19 ~ 190) 172
5896 00:40:43.365670 iDelay=203, Bit 8, Center 92 (11 ~ 174) 164
5897 00:40:43.369346 iDelay=203, Bit 9, Center 90 (3 ~ 178) 176
5898 00:40:43.372410 iDelay=203, Bit 10, Center 100 (15 ~ 186) 172
5899 00:40:43.379340 iDelay=203, Bit 11, Center 94 (11 ~ 178) 168
5900 00:40:43.382650 iDelay=203, Bit 12, Center 108 (19 ~ 198) 180
5901 00:40:43.385943 iDelay=203, Bit 13, Center 104 (19 ~ 190) 172
5902 00:40:43.389068 iDelay=203, Bit 14, Center 102 (15 ~ 190) 176
5903 00:40:43.392516 iDelay=203, Bit 15, Center 106 (19 ~ 194) 176
5904 00:40:43.395746 ==
5905 00:40:43.395831 Dram Type= 6, Freq= 0, CH_1, rank 1
5906 00:40:43.402593 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5907 00:40:43.402663 ==
5908 00:40:43.402765 DQS Delay:
5909 00:40:43.406034 DQS0 = 0, DQS1 = 0
5910 00:40:43.406100 DQM Delay:
5911 00:40:43.409484 DQM0 = 104, DQM1 = 99
5912 00:40:43.409599 DQ Delay:
5913 00:40:43.412226 DQ0 =110, DQ1 =100, DQ2 =94, DQ3 =100
5914 00:40:43.415610 DQ4 =100, DQ5 =116, DQ6 =114, DQ7 =104
5915 00:40:43.418798 DQ8 =92, DQ9 =90, DQ10 =100, DQ11 =94
5916 00:40:43.422136 DQ12 =108, DQ13 =104, DQ14 =102, DQ15 =106
5917 00:40:43.422208
5918 00:40:43.422267
5919 00:40:43.432733 [DQSOSCAuto] RK1, (LSB)MR18= 0x3003, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 406 ps
5920 00:40:43.432808 CH1 RK1: MR19=505, MR18=3003
5921 00:40:43.438966 CH1_RK1: MR19=0x505, MR18=0x3003, DQSOSC=406, MR23=63, INC=65, DEC=43
5922 00:40:43.442025 [RxdqsGatingPostProcess] freq 933
5923 00:40:43.448658 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5924 00:40:43.452165 best DQS0 dly(2T, 0.5T) = (0, 10)
5925 00:40:43.455485 best DQS1 dly(2T, 0.5T) = (0, 10)
5926 00:40:43.458941 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5927 00:40:43.462450 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5928 00:40:43.465192 best DQS0 dly(2T, 0.5T) = (0, 10)
5929 00:40:43.465262 best DQS1 dly(2T, 0.5T) = (0, 10)
5930 00:40:43.468425 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5931 00:40:43.471867 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5932 00:40:43.475260 Pre-setting of DQS Precalculation
5933 00:40:43.481846 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5934 00:40:43.488417 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5935 00:40:43.495399 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5936 00:40:43.495479
5937 00:40:43.495540
5938 00:40:43.498131 [Calibration Summary] 1866 Mbps
5939 00:40:43.501868 CH 0, Rank 0
5940 00:40:43.501944 SW Impedance : PASS
5941 00:40:43.505145 DUTY Scan : NO K
5942 00:40:43.508552 ZQ Calibration : PASS
5943 00:40:43.508624 Jitter Meter : NO K
5944 00:40:43.512089 CBT Training : PASS
5945 00:40:43.512184 Write leveling : PASS
5946 00:40:43.514830 RX DQS gating : PASS
5947 00:40:43.518325 RX DQ/DQS(RDDQC) : PASS
5948 00:40:43.518419 TX DQ/DQS : PASS
5949 00:40:43.521731 RX DATLAT : PASS
5950 00:40:43.525045 RX DQ/DQS(Engine): PASS
5951 00:40:43.525119 TX OE : NO K
5952 00:40:43.528384 All Pass.
5953 00:40:43.528455
5954 00:40:43.528512 CH 0, Rank 1
5955 00:40:43.531854 SW Impedance : PASS
5956 00:40:43.531931 DUTY Scan : NO K
5957 00:40:43.534653 ZQ Calibration : PASS
5958 00:40:43.538540 Jitter Meter : NO K
5959 00:40:43.538616 CBT Training : PASS
5960 00:40:43.541678 Write leveling : PASS
5961 00:40:43.544681 RX DQS gating : PASS
5962 00:40:43.544752 RX DQ/DQS(RDDQC) : PASS
5963 00:40:43.548092 TX DQ/DQS : PASS
5964 00:40:43.551816 RX DATLAT : PASS
5965 00:40:43.551930 RX DQ/DQS(Engine): PASS
5966 00:40:43.554487 TX OE : NO K
5967 00:40:43.554581 All Pass.
5968 00:40:43.554664
5969 00:40:43.557956 CH 1, Rank 0
5970 00:40:43.558031 SW Impedance : PASS
5971 00:40:43.561383 DUTY Scan : NO K
5972 00:40:43.564845 ZQ Calibration : PASS
5973 00:40:43.564941 Jitter Meter : NO K
5974 00:40:43.567703 CBT Training : PASS
5975 00:40:43.567795 Write leveling : PASS
5976 00:40:43.571008 RX DQS gating : PASS
5977 00:40:43.574423 RX DQ/DQS(RDDQC) : PASS
5978 00:40:43.574501 TX DQ/DQS : PASS
5979 00:40:43.577904 RX DATLAT : PASS
5980 00:40:43.581154 RX DQ/DQS(Engine): PASS
5981 00:40:43.581232 TX OE : NO K
5982 00:40:43.584552 All Pass.
5983 00:40:43.584628
5984 00:40:43.584688 CH 1, Rank 1
5985 00:40:43.587949 SW Impedance : PASS
5986 00:40:43.588027 DUTY Scan : NO K
5987 00:40:43.591452 ZQ Calibration : PASS
5988 00:40:43.594834 Jitter Meter : NO K
5989 00:40:43.594912 CBT Training : PASS
5990 00:40:43.597441 Write leveling : PASS
5991 00:40:43.601177 RX DQS gating : PASS
5992 00:40:43.601255 RX DQ/DQS(RDDQC) : PASS
5993 00:40:43.604342 TX DQ/DQS : PASS
5994 00:40:43.607395 RX DATLAT : PASS
5995 00:40:43.607473 RX DQ/DQS(Engine): PASS
5996 00:40:43.611136 TX OE : NO K
5997 00:40:43.611213 All Pass.
5998 00:40:43.611272
5999 00:40:43.614414 DramC Write-DBI off
6000 00:40:43.617680 PER_BANK_REFRESH: Hybrid Mode
6001 00:40:43.617757 TX_TRACKING: ON
6002 00:40:43.627821 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6003 00:40:43.630476 [FAST_K] Save calibration result to emmc
6004 00:40:43.634256 dramc_set_vcore_voltage set vcore to 650000
6005 00:40:43.637484 Read voltage for 400, 6
6006 00:40:43.637569 Vio18 = 0
6007 00:40:43.637632 Vcore = 650000
6008 00:40:43.640958 Vdram = 0
6009 00:40:43.641035 Vddq = 0
6010 00:40:43.641094 Vmddr = 0
6011 00:40:43.647127 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6012 00:40:43.651038 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6013 00:40:43.654100 MEM_TYPE=3, freq_sel=20
6014 00:40:43.657342 sv_algorithm_assistance_LP4_800
6015 00:40:43.660560 ============ PULL DRAM RESETB DOWN ============
6016 00:40:43.663767 ========== PULL DRAM RESETB DOWN end =========
6017 00:40:43.670781 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6018 00:40:43.674131 ===================================
6019 00:40:43.674209 LPDDR4 DRAM CONFIGURATION
6020 00:40:43.677483 ===================================
6021 00:40:43.681188 EX_ROW_EN[0] = 0x0
6022 00:40:43.684393 EX_ROW_EN[1] = 0x0
6023 00:40:43.684479 LP4Y_EN = 0x0
6024 00:40:43.687723 WORK_FSP = 0x0
6025 00:40:43.687825 WL = 0x2
6026 00:40:43.690489 RL = 0x2
6027 00:40:43.690567 BL = 0x2
6028 00:40:43.694046 RPST = 0x0
6029 00:40:43.694123 RD_PRE = 0x0
6030 00:40:43.697298 WR_PRE = 0x1
6031 00:40:43.697395 WR_PST = 0x0
6032 00:40:43.700818 DBI_WR = 0x0
6033 00:40:43.700895 DBI_RD = 0x0
6034 00:40:43.704062 OTF = 0x1
6035 00:40:43.707179 ===================================
6036 00:40:43.710555 ===================================
6037 00:40:43.710633 ANA top config
6038 00:40:43.713940 ===================================
6039 00:40:43.717078 DLL_ASYNC_EN = 0
6040 00:40:43.720339 ALL_SLAVE_EN = 1
6041 00:40:43.723611 NEW_RANK_MODE = 1
6042 00:40:43.723689 DLL_IDLE_MODE = 1
6043 00:40:43.727431 LP45_APHY_COMB_EN = 1
6044 00:40:43.730443 TX_ODT_DIS = 1
6045 00:40:43.733876 NEW_8X_MODE = 1
6046 00:40:43.736960 ===================================
6047 00:40:43.740576 ===================================
6048 00:40:43.743921 data_rate = 800
6049 00:40:43.744019 CKR = 1
6050 00:40:43.747086 DQ_P2S_RATIO = 4
6051 00:40:43.750567 ===================================
6052 00:40:43.753970 CA_P2S_RATIO = 4
6053 00:40:43.757287 DQ_CA_OPEN = 0
6054 00:40:43.760487 DQ_SEMI_OPEN = 1
6055 00:40:43.760590 CA_SEMI_OPEN = 1
6056 00:40:43.763602 CA_FULL_RATE = 0
6057 00:40:43.766998 DQ_CKDIV4_EN = 0
6058 00:40:43.770381 CA_CKDIV4_EN = 1
6059 00:40:43.773686 CA_PREDIV_EN = 0
6060 00:40:43.776856 PH8_DLY = 0
6061 00:40:43.776956 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6062 00:40:43.780564 DQ_AAMCK_DIV = 0
6063 00:40:43.783832 CA_AAMCK_DIV = 0
6064 00:40:43.787209 CA_ADMCK_DIV = 4
6065 00:40:43.790551 DQ_TRACK_CA_EN = 0
6066 00:40:43.793820 CA_PICK = 800
6067 00:40:43.797148 CA_MCKIO = 400
6068 00:40:43.797241 MCKIO_SEMI = 400
6069 00:40:43.800630 PLL_FREQ = 3016
6070 00:40:43.803377 DQ_UI_PI_RATIO = 32
6071 00:40:43.806782 CA_UI_PI_RATIO = 32
6072 00:40:43.810123 ===================================
6073 00:40:43.814069 ===================================
6074 00:40:43.816898 memory_type:LPDDR4
6075 00:40:43.816990 GP_NUM : 10
6076 00:40:43.820092 SRAM_EN : 1
6077 00:40:43.823702 MD32_EN : 0
6078 00:40:43.826962 ===================================
6079 00:40:43.827056 [ANA_INIT] >>>>>>>>>>>>>>
6080 00:40:43.830300 <<<<<< [CONFIGURE PHASE]: ANA_TX
6081 00:40:43.833655 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6082 00:40:43.836839 ===================================
6083 00:40:43.840038 data_rate = 800,PCW = 0X7400
6084 00:40:43.843280 ===================================
6085 00:40:43.846909 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6086 00:40:43.853743 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6087 00:40:43.863077 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6088 00:40:43.866994 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6089 00:40:43.873332 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6090 00:40:43.876356 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6091 00:40:43.876456 [ANA_INIT] flow start
6092 00:40:43.880271 [ANA_INIT] PLL >>>>>>>>
6093 00:40:43.883681 [ANA_INIT] PLL <<<<<<<<
6094 00:40:43.883759 [ANA_INIT] MIDPI >>>>>>>>
6095 00:40:43.886914 [ANA_INIT] MIDPI <<<<<<<<
6096 00:40:43.889994 [ANA_INIT] DLL >>>>>>>>
6097 00:40:43.890071 [ANA_INIT] flow end
6098 00:40:43.893498 ============ LP4 DIFF to SE enter ============
6099 00:40:43.900067 ============ LP4 DIFF to SE exit ============
6100 00:40:43.900172 [ANA_INIT] <<<<<<<<<<<<<
6101 00:40:43.903500 [Flow] Enable top DCM control >>>>>
6102 00:40:43.907041 [Flow] Enable top DCM control <<<<<
6103 00:40:43.909749 Enable DLL master slave shuffle
6104 00:40:43.916453 ==============================================================
6105 00:40:43.916532 Gating Mode config
6106 00:40:43.923577 ==============================================================
6107 00:40:43.926288 Config description:
6108 00:40:43.936362 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6109 00:40:43.943050 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6110 00:40:43.946329 SELPH_MODE 0: By rank 1: By Phase
6111 00:40:43.953017 ==============================================================
6112 00:40:43.956255 GAT_TRACK_EN = 0
6113 00:40:43.959606 RX_GATING_MODE = 2
6114 00:40:43.959679 RX_GATING_TRACK_MODE = 2
6115 00:40:43.962941 SELPH_MODE = 1
6116 00:40:43.966364 PICG_EARLY_EN = 1
6117 00:40:43.969942 VALID_LAT_VALUE = 1
6118 00:40:43.976339 ==============================================================
6119 00:40:43.979564 Enter into Gating configuration >>>>
6120 00:40:43.983521 Exit from Gating configuration <<<<
6121 00:40:43.986372 Enter into DVFS_PRE_config >>>>>
6122 00:40:43.996099 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6123 00:40:43.999976 Exit from DVFS_PRE_config <<<<<
6124 00:40:44.003028 Enter into PICG configuration >>>>
6125 00:40:44.006172 Exit from PICG configuration <<<<
6126 00:40:44.009433 [RX_INPUT] configuration >>>>>
6127 00:40:44.012808 [RX_INPUT] configuration <<<<<
6128 00:40:44.016186 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6129 00:40:44.022837 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6130 00:40:44.029398 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6131 00:40:44.036031 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6132 00:40:44.039370 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6133 00:40:44.046132 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6134 00:40:44.049400 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6135 00:40:44.056211 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6136 00:40:44.059516 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6137 00:40:44.062772 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6138 00:40:44.066587 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6139 00:40:44.072616 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6140 00:40:44.075807 ===================================
6141 00:40:44.075878 LPDDR4 DRAM CONFIGURATION
6142 00:40:44.078933 ===================================
6143 00:40:44.082626 EX_ROW_EN[0] = 0x0
6144 00:40:44.086009 EX_ROW_EN[1] = 0x0
6145 00:40:44.086111 LP4Y_EN = 0x0
6146 00:40:44.089279 WORK_FSP = 0x0
6147 00:40:44.089372 WL = 0x2
6148 00:40:44.092420 RL = 0x2
6149 00:40:44.092513 BL = 0x2
6150 00:40:44.095606 RPST = 0x0
6151 00:40:44.095677 RD_PRE = 0x0
6152 00:40:44.099406 WR_PRE = 0x1
6153 00:40:44.099487 WR_PST = 0x0
6154 00:40:44.102625 DBI_WR = 0x0
6155 00:40:44.102702 DBI_RD = 0x0
6156 00:40:44.105683 OTF = 0x1
6157 00:40:44.108740 ===================================
6158 00:40:44.112206 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6159 00:40:44.115842 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6160 00:40:44.122398 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6161 00:40:44.125400 ===================================
6162 00:40:44.125470 LPDDR4 DRAM CONFIGURATION
6163 00:40:44.128735 ===================================
6164 00:40:44.132575 EX_ROW_EN[0] = 0x10
6165 00:40:44.135897 EX_ROW_EN[1] = 0x0
6166 00:40:44.136000 LP4Y_EN = 0x0
6167 00:40:44.139194 WORK_FSP = 0x0
6168 00:40:44.139274 WL = 0x2
6169 00:40:44.142466 RL = 0x2
6170 00:40:44.142537 BL = 0x2
6171 00:40:44.145866 RPST = 0x0
6172 00:40:44.145958 RD_PRE = 0x0
6173 00:40:44.149216 WR_PRE = 0x1
6174 00:40:44.149307 WR_PST = 0x0
6175 00:40:44.151969 DBI_WR = 0x0
6176 00:40:44.152065 DBI_RD = 0x0
6177 00:40:44.155358 OTF = 0x1
6178 00:40:44.158741 ===================================
6179 00:40:44.165465 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6180 00:40:44.168653 nWR fixed to 30
6181 00:40:44.168764 [ModeRegInit_LP4] CH0 RK0
6182 00:40:44.171936 [ModeRegInit_LP4] CH0 RK1
6183 00:40:44.175339 [ModeRegInit_LP4] CH1 RK0
6184 00:40:44.178678 [ModeRegInit_LP4] CH1 RK1
6185 00:40:44.178781 match AC timing 19
6186 00:40:44.185280 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6187 00:40:44.188432 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6188 00:40:44.192271 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6189 00:40:44.195443 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6190 00:40:44.202115 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6191 00:40:44.202210 ==
6192 00:40:44.205324 Dram Type= 6, Freq= 0, CH_0, rank 0
6193 00:40:44.208762 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6194 00:40:44.208830 ==
6195 00:40:44.215376 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6196 00:40:44.221685 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6197 00:40:44.224938 [CA 0] Center 36 (8~64) winsize 57
6198 00:40:44.225014 [CA 1] Center 36 (8~64) winsize 57
6199 00:40:44.228226 [CA 2] Center 36 (8~64) winsize 57
6200 00:40:44.232018 [CA 3] Center 36 (8~64) winsize 57
6201 00:40:44.234933 [CA 4] Center 36 (8~64) winsize 57
6202 00:40:44.238286 [CA 5] Center 36 (8~64) winsize 57
6203 00:40:44.238373
6204 00:40:44.241921 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6205 00:40:44.242014
6206 00:40:44.244930 [CATrainingPosCal] consider 1 rank data
6207 00:40:44.248336 u2DelayCellTimex100 = 270/100 ps
6208 00:40:44.251762 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6209 00:40:44.258500 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6210 00:40:44.262007 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6211 00:40:44.265231 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6212 00:40:44.268605 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6213 00:40:44.272018 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6214 00:40:44.272111
6215 00:40:44.275291 CA PerBit enable=1, Macro0, CA PI delay=36
6216 00:40:44.275393
6217 00:40:44.278568 [CBTSetCACLKResult] CA Dly = 36
6218 00:40:44.278664 CS Dly: 1 (0~32)
6219 00:40:44.281958 ==
6220 00:40:44.282029 Dram Type= 6, Freq= 0, CH_0, rank 1
6221 00:40:44.288148 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6222 00:40:44.288245 ==
6223 00:40:44.291645 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6224 00:40:44.298497 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6225 00:40:44.301650 [CA 0] Center 36 (8~64) winsize 57
6226 00:40:44.304762 [CA 1] Center 36 (8~64) winsize 57
6227 00:40:44.308610 [CA 2] Center 36 (8~64) winsize 57
6228 00:40:44.311768 [CA 3] Center 36 (8~64) winsize 57
6229 00:40:44.314979 [CA 4] Center 36 (8~64) winsize 57
6230 00:40:44.318337 [CA 5] Center 36 (8~64) winsize 57
6231 00:40:44.318420
6232 00:40:44.321696 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6233 00:40:44.321770
6234 00:40:44.324896 [CATrainingPosCal] consider 2 rank data
6235 00:40:44.328168 u2DelayCellTimex100 = 270/100 ps
6236 00:40:44.331264 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6237 00:40:44.335189 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6238 00:40:44.338525 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6239 00:40:44.341271 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6240 00:40:44.345033 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6241 00:40:44.351503 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6242 00:40:44.351589
6243 00:40:44.354841 CA PerBit enable=1, Macro0, CA PI delay=36
6244 00:40:44.354928
6245 00:40:44.357840 [CBTSetCACLKResult] CA Dly = 36
6246 00:40:44.357925 CS Dly: 1 (0~32)
6247 00:40:44.358022
6248 00:40:44.361407 ----->DramcWriteLeveling(PI) begin...
6249 00:40:44.361522 ==
6250 00:40:44.364506 Dram Type= 6, Freq= 0, CH_0, rank 0
6251 00:40:44.371293 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6252 00:40:44.371367 ==
6253 00:40:44.374661 Write leveling (Byte 0): 40 => 8
6254 00:40:44.374748 Write leveling (Byte 1): 40 => 8
6255 00:40:44.377925 DramcWriteLeveling(PI) end<-----
6256 00:40:44.378000
6257 00:40:44.378056 ==
6258 00:40:44.381310 Dram Type= 6, Freq= 0, CH_0, rank 0
6259 00:40:44.387761 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6260 00:40:44.387832 ==
6261 00:40:44.387890 [Gating] SW mode calibration
6262 00:40:44.398094 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6263 00:40:44.401521 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6264 00:40:44.408002 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6265 00:40:44.411291 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6266 00:40:44.414391 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6267 00:40:44.418046 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6268 00:40:44.424358 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6269 00:40:44.427704 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6270 00:40:44.431033 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6271 00:40:44.437608 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6272 00:40:44.440850 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6273 00:40:44.444134 Total UI for P1: 0, mck2ui 16
6274 00:40:44.447618 best dqsien dly found for B0: ( 0, 14, 24)
6275 00:40:44.451072 Total UI for P1: 0, mck2ui 16
6276 00:40:44.454427 best dqsien dly found for B1: ( 0, 14, 24)
6277 00:40:44.457830 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6278 00:40:44.461007 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6279 00:40:44.461080
6280 00:40:44.464102 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6281 00:40:44.471260 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6282 00:40:44.471337 [Gating] SW calibration Done
6283 00:40:44.471396 ==
6284 00:40:44.474020 Dram Type= 6, Freq= 0, CH_0, rank 0
6285 00:40:44.481017 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6286 00:40:44.481097 ==
6287 00:40:44.481156 RX Vref Scan: 0
6288 00:40:44.481210
6289 00:40:44.484257 RX Vref 0 -> 0, step: 1
6290 00:40:44.484321
6291 00:40:44.487484 RX Delay -410 -> 252, step: 16
6292 00:40:44.490702 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6293 00:40:44.494123 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6294 00:40:44.500979 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6295 00:40:44.504331 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6296 00:40:44.507590 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6297 00:40:44.510798 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6298 00:40:44.517473 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6299 00:40:44.520884 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6300 00:40:44.524187 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6301 00:40:44.527417 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6302 00:40:44.533876 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6303 00:40:44.537026 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6304 00:40:44.540751 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6305 00:40:44.544024 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6306 00:40:44.550449 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6307 00:40:44.553902 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6308 00:40:44.553996 ==
6309 00:40:44.557307 Dram Type= 6, Freq= 0, CH_0, rank 0
6310 00:40:44.560659 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6311 00:40:44.560759 ==
6312 00:40:44.564042 DQS Delay:
6313 00:40:44.564133 DQS0 = 27, DQS1 = 35
6314 00:40:44.567328 DQM Delay:
6315 00:40:44.567396 DQM0 = 10, DQM1 = 12
6316 00:40:44.567464 DQ Delay:
6317 00:40:44.570262 DQ0 =8, DQ1 =16, DQ2 =0, DQ3 =8
6318 00:40:44.573499 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =24
6319 00:40:44.576964 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6320 00:40:44.580147 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6321 00:40:44.580256
6322 00:40:44.580349
6323 00:40:44.580438 ==
6324 00:40:44.583470 Dram Type= 6, Freq= 0, CH_0, rank 0
6325 00:40:44.590286 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6326 00:40:44.590387 ==
6327 00:40:44.590472
6328 00:40:44.590561
6329 00:40:44.590644 TX Vref Scan disable
6330 00:40:44.593855 == TX Byte 0 ==
6331 00:40:44.597254 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6332 00:40:44.600208 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6333 00:40:44.603366 == TX Byte 1 ==
6334 00:40:44.606762 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6335 00:40:44.610024 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6336 00:40:44.610122 ==
6337 00:40:44.613755 Dram Type= 6, Freq= 0, CH_0, rank 0
6338 00:40:44.620306 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6339 00:40:44.620402 ==
6340 00:40:44.620488
6341 00:40:44.620566
6342 00:40:44.620647 TX Vref Scan disable
6343 00:40:44.623725 == TX Byte 0 ==
6344 00:40:44.627151 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6345 00:40:44.630674 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6346 00:40:44.634090 == TX Byte 1 ==
6347 00:40:44.636799 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6348 00:40:44.640685 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6349 00:40:44.640775
6350 00:40:44.643924 [DATLAT]
6351 00:40:44.644011 Freq=400, CH0 RK0
6352 00:40:44.644093
6353 00:40:44.647003 DATLAT Default: 0xf
6354 00:40:44.647094 0, 0xFFFF, sum = 0
6355 00:40:44.650064 1, 0xFFFF, sum = 0
6356 00:40:44.650154 2, 0xFFFF, sum = 0
6357 00:40:44.653389 3, 0xFFFF, sum = 0
6358 00:40:44.653478 4, 0xFFFF, sum = 0
6359 00:40:44.657265 5, 0xFFFF, sum = 0
6360 00:40:44.657373 6, 0xFFFF, sum = 0
6361 00:40:44.660197 7, 0xFFFF, sum = 0
6362 00:40:44.660290 8, 0xFFFF, sum = 0
6363 00:40:44.664039 9, 0xFFFF, sum = 0
6364 00:40:44.664147 10, 0xFFFF, sum = 0
6365 00:40:44.667321 11, 0xFFFF, sum = 0
6366 00:40:44.667412 12, 0xFFFF, sum = 0
6367 00:40:44.670732 13, 0x0, sum = 1
6368 00:40:44.670821 14, 0x0, sum = 2
6369 00:40:44.674086 15, 0x0, sum = 3
6370 00:40:44.674177 16, 0x0, sum = 4
6371 00:40:44.677373 best_step = 14
6372 00:40:44.677460
6373 00:40:44.677569 ==
6374 00:40:44.680683 Dram Type= 6, Freq= 0, CH_0, rank 0
6375 00:40:44.683867 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6376 00:40:44.683957 ==
6377 00:40:44.687176 RX Vref Scan: 1
6378 00:40:44.687260
6379 00:40:44.687342 RX Vref 0 -> 0, step: 1
6380 00:40:44.687421
6381 00:40:44.690468 RX Delay -311 -> 252, step: 8
6382 00:40:44.690552
6383 00:40:44.693886 Set Vref, RX VrefLevel [Byte0]: 55
6384 00:40:44.696697 [Byte1]: 50
6385 00:40:44.701319
6386 00:40:44.701413 Final RX Vref Byte 0 = 55 to rank0
6387 00:40:44.704482 Final RX Vref Byte 1 = 50 to rank0
6388 00:40:44.708039 Final RX Vref Byte 0 = 55 to rank1
6389 00:40:44.711588 Final RX Vref Byte 1 = 50 to rank1==
6390 00:40:44.714581 Dram Type= 6, Freq= 0, CH_0, rank 0
6391 00:40:44.721226 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6392 00:40:44.721335 ==
6393 00:40:44.721428 DQS Delay:
6394 00:40:44.721518 DQS0 = 28, DQS1 = 36
6395 00:40:44.724873 DQM Delay:
6396 00:40:44.724968 DQM0 = 10, DQM1 = 12
6397 00:40:44.728112 DQ Delay:
6398 00:40:44.731608 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =8
6399 00:40:44.731718 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6400 00:40:44.734965 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =4
6401 00:40:44.738297 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6402 00:40:44.738395
6403 00:40:44.738481
6404 00:40:44.748323 [DQSOSCAuto] RK0, (LSB)MR18= 0xdbc7, (MSB)MR19= 0xc0c, tDQSOscB0 = 385 ps tDQSOscB1 = 382 ps
6405 00:40:44.751672 CH0 RK0: MR19=C0C, MR18=DBC7
6406 00:40:44.757623 CH0_RK0: MR19=0xC0C, MR18=0xDBC7, DQSOSC=382, MR23=63, INC=404, DEC=269
6407 00:40:44.757723 ==
6408 00:40:44.760949 Dram Type= 6, Freq= 0, CH_0, rank 1
6409 00:40:44.764721 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6410 00:40:44.764818 ==
6411 00:40:44.767937 [Gating] SW mode calibration
6412 00:40:44.774752 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6413 00:40:44.777716 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6414 00:40:44.784278 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6415 00:40:44.787509 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6416 00:40:44.791402 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6417 00:40:44.798033 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6418 00:40:44.801379 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6419 00:40:44.804780 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6420 00:40:44.810814 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6421 00:40:44.814651 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6422 00:40:44.817796 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6423 00:40:44.821092 Total UI for P1: 0, mck2ui 16
6424 00:40:44.824498 best dqsien dly found for B0: ( 0, 14, 24)
6425 00:40:44.827499 Total UI for P1: 0, mck2ui 16
6426 00:40:44.831195 best dqsien dly found for B1: ( 0, 14, 24)
6427 00:40:44.834115 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6428 00:40:44.840732 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6429 00:40:44.840829
6430 00:40:44.844485 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6431 00:40:44.847220 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6432 00:40:44.850507 [Gating] SW calibration Done
6433 00:40:44.850609 ==
6434 00:40:44.853919 Dram Type= 6, Freq= 0, CH_0, rank 1
6435 00:40:44.857251 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6436 00:40:44.857348 ==
6437 00:40:44.857433 RX Vref Scan: 0
6438 00:40:44.860704
6439 00:40:44.860801 RX Vref 0 -> 0, step: 1
6440 00:40:44.860890
6441 00:40:44.863904 RX Delay -410 -> 252, step: 16
6442 00:40:44.867216 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6443 00:40:44.873905 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6444 00:40:44.877235 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6445 00:40:44.880615 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6446 00:40:44.883818 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6447 00:40:44.890701 iDelay=230, Bit 5, Center -19 (-250 ~ 213) 464
6448 00:40:44.893690 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6449 00:40:44.897180 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6450 00:40:44.900213 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6451 00:40:44.907253 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6452 00:40:44.910722 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6453 00:40:44.914113 iDelay=230, Bit 11, Center -27 (-250 ~ 197) 448
6454 00:40:44.916792 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6455 00:40:44.923881 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6456 00:40:44.927246 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6457 00:40:44.930684 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6458 00:40:44.930777 ==
6459 00:40:44.933389 Dram Type= 6, Freq= 0, CH_0, rank 1
6460 00:40:44.940126 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6461 00:40:44.940217 ==
6462 00:40:44.940305 DQS Delay:
6463 00:40:44.943524 DQS0 = 19, DQS1 = 35
6464 00:40:44.943600 DQM Delay:
6465 00:40:44.943685 DQM0 = 5, DQM1 = 11
6466 00:40:44.946605 DQ Delay:
6467 00:40:44.950367 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6468 00:40:44.950460 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6469 00:40:44.953294 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6470 00:40:44.956679 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6471 00:40:44.956770
6472 00:40:44.956855
6473 00:40:44.959980 ==
6474 00:40:44.960071 Dram Type= 6, Freq= 0, CH_0, rank 1
6475 00:40:44.966862 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6476 00:40:44.966960 ==
6477 00:40:44.967054
6478 00:40:44.967143
6479 00:40:44.970093 TX Vref Scan disable
6480 00:40:44.970189 == TX Byte 0 ==
6481 00:40:44.973279 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6482 00:40:44.976943 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6483 00:40:44.980321 == TX Byte 1 ==
6484 00:40:44.983764 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6485 00:40:44.986439 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6486 00:40:44.989852 ==
6487 00:40:44.993160 Dram Type= 6, Freq= 0, CH_0, rank 1
6488 00:40:44.997155 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6489 00:40:44.997248 ==
6490 00:40:44.997333
6491 00:40:44.997416
6492 00:40:45.000314 TX Vref Scan disable
6493 00:40:45.000406 == TX Byte 0 ==
6494 00:40:45.003654 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6495 00:40:45.009973 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6496 00:40:45.010070 == TX Byte 1 ==
6497 00:40:45.013212 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6498 00:40:45.020080 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6499 00:40:45.020178
6500 00:40:45.020266 [DATLAT]
6501 00:40:45.020349 Freq=400, CH0 RK1
6502 00:40:45.020433
6503 00:40:45.023420 DATLAT Default: 0xe
6504 00:40:45.023522 0, 0xFFFF, sum = 0
6505 00:40:45.026785 1, 0xFFFF, sum = 0
6506 00:40:45.026886 2, 0xFFFF, sum = 0
6507 00:40:45.030014 3, 0xFFFF, sum = 0
6508 00:40:45.030110 4, 0xFFFF, sum = 0
6509 00:40:45.033326 5, 0xFFFF, sum = 0
6510 00:40:45.036703 6, 0xFFFF, sum = 0
6511 00:40:45.036769 7, 0xFFFF, sum = 0
6512 00:40:45.040044 8, 0xFFFF, sum = 0
6513 00:40:45.040108 9, 0xFFFF, sum = 0
6514 00:40:45.043388 10, 0xFFFF, sum = 0
6515 00:40:45.043482 11, 0xFFFF, sum = 0
6516 00:40:45.046855 12, 0xFFFF, sum = 0
6517 00:40:45.046921 13, 0x0, sum = 1
6518 00:40:45.050332 14, 0x0, sum = 2
6519 00:40:45.050395 15, 0x0, sum = 3
6520 00:40:45.053083 16, 0x0, sum = 4
6521 00:40:45.053173 best_step = 14
6522 00:40:45.053253
6523 00:40:45.053334 ==
6524 00:40:45.056524 Dram Type= 6, Freq= 0, CH_0, rank 1
6525 00:40:45.059832 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6526 00:40:45.059900 ==
6527 00:40:45.063682 RX Vref Scan: 0
6528 00:40:45.063754
6529 00:40:45.066274 RX Vref 0 -> 0, step: 1
6530 00:40:45.066341
6531 00:40:45.066395 RX Delay -311 -> 252, step: 8
6532 00:40:45.075077 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6533 00:40:45.078746 iDelay=217, Bit 1, Center -12 (-231 ~ 208) 440
6534 00:40:45.081629 iDelay=217, Bit 2, Center -16 (-239 ~ 208) 448
6535 00:40:45.085186 iDelay=217, Bit 3, Center -16 (-239 ~ 208) 448
6536 00:40:45.091859 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6537 00:40:45.095034 iDelay=217, Bit 5, Center -24 (-247 ~ 200) 448
6538 00:40:45.098308 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6539 00:40:45.101576 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6540 00:40:45.108196 iDelay=217, Bit 8, Center -28 (-247 ~ 192) 440
6541 00:40:45.112093 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6542 00:40:45.115213 iDelay=217, Bit 10, Center -20 (-239 ~ 200) 440
6543 00:40:45.118424 iDelay=217, Bit 11, Center -28 (-247 ~ 192) 440
6544 00:40:45.124932 iDelay=217, Bit 12, Center -20 (-239 ~ 200) 440
6545 00:40:45.128269 iDelay=217, Bit 13, Center -20 (-239 ~ 200) 440
6546 00:40:45.131456 iDelay=217, Bit 14, Center -12 (-231 ~ 208) 440
6547 00:40:45.138616 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6548 00:40:45.138703 ==
6549 00:40:45.141347 Dram Type= 6, Freq= 0, CH_0, rank 1
6550 00:40:45.144720 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6551 00:40:45.144821 ==
6552 00:40:45.144906 DQS Delay:
6553 00:40:45.148223 DQS0 = 24, DQS1 = 32
6554 00:40:45.148322 DQM Delay:
6555 00:40:45.151723 DQM0 = 9, DQM1 = 10
6556 00:40:45.151823 DQ Delay:
6557 00:40:45.155123 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =8
6558 00:40:45.158401 DQ4 =8, DQ5 =0, DQ6 =12, DQ7 =16
6559 00:40:45.161772 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =4
6560 00:40:45.164602 DQ12 =12, DQ13 =12, DQ14 =20, DQ15 =16
6561 00:40:45.164701
6562 00:40:45.164788
6563 00:40:45.171386 [DQSOSCAuto] RK1, (LSB)MR18= 0xc363, (MSB)MR19= 0xc0c, tDQSOscB0 = 397 ps tDQSOscB1 = 385 ps
6564 00:40:45.174795 CH0 RK1: MR19=C0C, MR18=C363
6565 00:40:45.181071 CH0_RK1: MR19=0xC0C, MR18=0xC363, DQSOSC=385, MR23=63, INC=398, DEC=265
6566 00:40:45.184992 [RxdqsGatingPostProcess] freq 400
6567 00:40:45.191134 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6568 00:40:45.191205 best DQS0 dly(2T, 0.5T) = (0, 10)
6569 00:40:45.194448 best DQS1 dly(2T, 0.5T) = (0, 10)
6570 00:40:45.198173 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6571 00:40:45.201188 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6572 00:40:45.204822 best DQS0 dly(2T, 0.5T) = (0, 10)
6573 00:40:45.208094 best DQS1 dly(2T, 0.5T) = (0, 10)
6574 00:40:45.211347 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6575 00:40:45.214301 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6576 00:40:45.218007 Pre-setting of DQS Precalculation
6577 00:40:45.221214 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6578 00:40:45.224775 ==
6579 00:40:45.224869 Dram Type= 6, Freq= 0, CH_1, rank 0
6580 00:40:45.231231 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6581 00:40:45.231304 ==
6582 00:40:45.234774 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6583 00:40:45.241425 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6584 00:40:45.244786 [CA 0] Center 36 (8~64) winsize 57
6585 00:40:45.248305 [CA 1] Center 36 (8~64) winsize 57
6586 00:40:45.251444 [CA 2] Center 36 (8~64) winsize 57
6587 00:40:45.254584 [CA 3] Center 36 (8~64) winsize 57
6588 00:40:45.258130 [CA 4] Center 36 (8~64) winsize 57
6589 00:40:45.261395 [CA 5] Center 36 (8~64) winsize 57
6590 00:40:45.261494
6591 00:40:45.264720 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6592 00:40:45.264807
6593 00:40:45.268178 [CATrainingPosCal] consider 1 rank data
6594 00:40:45.271669 u2DelayCellTimex100 = 270/100 ps
6595 00:40:45.275038 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6596 00:40:45.278367 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6597 00:40:45.281334 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6598 00:40:45.285066 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6599 00:40:45.288266 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6600 00:40:45.291399 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6601 00:40:45.294851
6602 00:40:45.298127 CA PerBit enable=1, Macro0, CA PI delay=36
6603 00:40:45.298198
6604 00:40:45.301634 [CBTSetCACLKResult] CA Dly = 36
6605 00:40:45.301700 CS Dly: 1 (0~32)
6606 00:40:45.301757 ==
6607 00:40:45.304997 Dram Type= 6, Freq= 0, CH_1, rank 1
6608 00:40:45.308352 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6609 00:40:45.308441 ==
6610 00:40:45.315076 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6611 00:40:45.321117 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6612 00:40:45.324685 [CA 0] Center 36 (8~64) winsize 57
6613 00:40:45.327668 [CA 1] Center 36 (8~64) winsize 57
6614 00:40:45.331535 [CA 2] Center 36 (8~64) winsize 57
6615 00:40:45.334508 [CA 3] Center 36 (8~64) winsize 57
6616 00:40:45.337736 [CA 4] Center 36 (8~64) winsize 57
6617 00:40:45.337808 [CA 5] Center 36 (8~64) winsize 57
6618 00:40:45.341019
6619 00:40:45.344693 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6620 00:40:45.344795
6621 00:40:45.347784 [CATrainingPosCal] consider 2 rank data
6622 00:40:45.351422 u2DelayCellTimex100 = 270/100 ps
6623 00:40:45.354274 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6624 00:40:45.357603 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6625 00:40:45.361273 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6626 00:40:45.364379 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6627 00:40:45.367675 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6628 00:40:45.371135 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6629 00:40:45.371229
6630 00:40:45.374584 CA PerBit enable=1, Macro0, CA PI delay=36
6631 00:40:45.374655
6632 00:40:45.377478 [CBTSetCACLKResult] CA Dly = 36
6633 00:40:45.380809 CS Dly: 1 (0~32)
6634 00:40:45.380905
6635 00:40:45.384159 ----->DramcWriteLeveling(PI) begin...
6636 00:40:45.384254 ==
6637 00:40:45.387573 Dram Type= 6, Freq= 0, CH_1, rank 0
6638 00:40:45.390994 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6639 00:40:45.391086 ==
6640 00:40:45.394160 Write leveling (Byte 0): 40 => 8
6641 00:40:45.397848 Write leveling (Byte 1): 40 => 8
6642 00:40:45.401319 DramcWriteLeveling(PI) end<-----
6643 00:40:45.401414
6644 00:40:45.401499 ==
6645 00:40:45.404025 Dram Type= 6, Freq= 0, CH_1, rank 0
6646 00:40:45.407379 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6647 00:40:45.407473 ==
6648 00:40:45.410676 [Gating] SW mode calibration
6649 00:40:45.417567 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6650 00:40:45.424367 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6651 00:40:45.427937 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6652 00:40:45.431173 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6653 00:40:45.437398 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6654 00:40:45.441166 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6655 00:40:45.443929 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6656 00:40:45.450601 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6657 00:40:45.453878 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6658 00:40:45.457274 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6659 00:40:45.463817 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6660 00:40:45.467745 Total UI for P1: 0, mck2ui 16
6661 00:40:45.470623 best dqsien dly found for B0: ( 0, 14, 24)
6662 00:40:45.470706 Total UI for P1: 0, mck2ui 16
6663 00:40:45.477297 best dqsien dly found for B1: ( 0, 14, 24)
6664 00:40:45.481008 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6665 00:40:45.484064 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6666 00:40:45.484157
6667 00:40:45.487273 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6668 00:40:45.490408 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6669 00:40:45.493756 [Gating] SW calibration Done
6670 00:40:45.493846 ==
6671 00:40:45.497154 Dram Type= 6, Freq= 0, CH_1, rank 0
6672 00:40:45.500774 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6673 00:40:45.500874 ==
6674 00:40:45.503939 RX Vref Scan: 0
6675 00:40:45.504032
6676 00:40:45.504118 RX Vref 0 -> 0, step: 1
6677 00:40:45.507074
6678 00:40:45.507167 RX Delay -410 -> 252, step: 16
6679 00:40:45.513824 iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480
6680 00:40:45.517225 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6681 00:40:45.520730 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6682 00:40:45.524041 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6683 00:40:45.530244 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6684 00:40:45.533722 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6685 00:40:45.537091 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6686 00:40:45.540361 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6687 00:40:45.547216 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6688 00:40:45.550144 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6689 00:40:45.553896 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6690 00:40:45.557309 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6691 00:40:45.563467 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6692 00:40:45.566938 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6693 00:40:45.570301 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6694 00:40:45.573683 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6695 00:40:45.576984 ==
6696 00:40:45.580615 Dram Type= 6, Freq= 0, CH_1, rank 0
6697 00:40:45.583564 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6698 00:40:45.583656 ==
6699 00:40:45.583739 DQS Delay:
6700 00:40:45.586969 DQS0 = 35, DQS1 = 35
6701 00:40:45.587064 DQM Delay:
6702 00:40:45.590321 DQM0 = 18, DQM1 = 12
6703 00:40:45.590412 DQ Delay:
6704 00:40:45.593584 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6705 00:40:45.597230 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16
6706 00:40:45.600379 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6707 00:40:45.603581 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =16
6708 00:40:45.603671
6709 00:40:45.603732
6710 00:40:45.603806 ==
6711 00:40:45.606730 Dram Type= 6, Freq= 0, CH_1, rank 0
6712 00:40:45.610342 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6713 00:40:45.610435 ==
6714 00:40:45.610519
6715 00:40:45.610604
6716 00:40:45.613419 TX Vref Scan disable
6717 00:40:45.613507 == TX Byte 0 ==
6718 00:40:45.620047 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6719 00:40:45.623724 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6720 00:40:45.623817 == TX Byte 1 ==
6721 00:40:45.630515 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6722 00:40:45.633288 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6723 00:40:45.633355 ==
6724 00:40:45.636858 Dram Type= 6, Freq= 0, CH_1, rank 0
6725 00:40:45.640306 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6726 00:40:45.640400 ==
6727 00:40:45.640488
6728 00:40:45.640572
6729 00:40:45.643819 TX Vref Scan disable
6730 00:40:45.643915 == TX Byte 0 ==
6731 00:40:45.650058 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6732 00:40:45.653348 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6733 00:40:45.653444 == TX Byte 1 ==
6734 00:40:45.660321 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6735 00:40:45.663247 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6736 00:40:45.663345
6737 00:40:45.663441 [DATLAT]
6738 00:40:45.667024 Freq=400, CH1 RK0
6739 00:40:45.667121
6740 00:40:45.667207 DATLAT Default: 0xf
6741 00:40:45.670483 0, 0xFFFF, sum = 0
6742 00:40:45.670587 1, 0xFFFF, sum = 0
6743 00:40:45.673243 2, 0xFFFF, sum = 0
6744 00:40:45.673338 3, 0xFFFF, sum = 0
6745 00:40:45.676590 4, 0xFFFF, sum = 0
6746 00:40:45.676689 5, 0xFFFF, sum = 0
6747 00:40:45.680040 6, 0xFFFF, sum = 0
6748 00:40:45.680143 7, 0xFFFF, sum = 0
6749 00:40:45.683419 8, 0xFFFF, sum = 0
6750 00:40:45.683514 9, 0xFFFF, sum = 0
6751 00:40:45.686845 10, 0xFFFF, sum = 0
6752 00:40:45.690110 11, 0xFFFF, sum = 0
6753 00:40:45.690211 12, 0xFFFF, sum = 0
6754 00:40:45.693467 13, 0x0, sum = 1
6755 00:40:45.693581 14, 0x0, sum = 2
6756 00:40:45.696900 15, 0x0, sum = 3
6757 00:40:45.697003 16, 0x0, sum = 4
6758 00:40:45.697094 best_step = 14
6759 00:40:45.697175
6760 00:40:45.700176 ==
6761 00:40:45.703226 Dram Type= 6, Freq= 0, CH_1, rank 0
6762 00:40:45.707038 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6763 00:40:45.707132 ==
6764 00:40:45.707218 RX Vref Scan: 1
6765 00:40:45.707303
6766 00:40:45.710064 RX Vref 0 -> 0, step: 1
6767 00:40:45.710156
6768 00:40:45.713679 RX Delay -311 -> 252, step: 8
6769 00:40:45.713773
6770 00:40:45.717148 Set Vref, RX VrefLevel [Byte0]: 56
6771 00:40:45.720312 [Byte1]: 52
6772 00:40:45.723155
6773 00:40:45.723260 Final RX Vref Byte 0 = 56 to rank0
6774 00:40:45.727049 Final RX Vref Byte 1 = 52 to rank0
6775 00:40:45.730270 Final RX Vref Byte 0 = 56 to rank1
6776 00:40:45.733454 Final RX Vref Byte 1 = 52 to rank1==
6777 00:40:45.736591 Dram Type= 6, Freq= 0, CH_1, rank 0
6778 00:40:45.743113 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6779 00:40:45.743216 ==
6780 00:40:45.743306 DQS Delay:
6781 00:40:45.746821 DQS0 = 28, DQS1 = 32
6782 00:40:45.746917 DQM Delay:
6783 00:40:45.747006 DQM0 = 9, DQM1 = 9
6784 00:40:45.750176 DQ Delay:
6785 00:40:45.750277 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =8
6786 00:40:45.753211 DQ4 =8, DQ5 =20, DQ6 =16, DQ7 =8
6787 00:40:45.756478 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6788 00:40:45.759891 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6789 00:40:45.759997
6790 00:40:45.760139
6791 00:40:45.769893 [DQSOSCAuto] RK0, (LSB)MR18= 0x9cd5, (MSB)MR19= 0xc0c, tDQSOscB0 = 383 ps tDQSOscB1 = 390 ps
6792 00:40:45.773500 CH1 RK0: MR19=C0C, MR18=9CD5
6793 00:40:45.776537 CH1_RK0: MR19=0xC0C, MR18=0x9CD5, DQSOSC=383, MR23=63, INC=402, DEC=268
6794 00:40:45.780422 ==
6795 00:40:45.783112 Dram Type= 6, Freq= 0, CH_1, rank 1
6796 00:40:45.786490 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6797 00:40:45.786591 ==
6798 00:40:45.789858 [Gating] SW mode calibration
6799 00:40:45.797189 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6800 00:40:45.799988 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6801 00:40:45.806718 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6802 00:40:45.810034 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6803 00:40:45.813377 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6804 00:40:45.819994 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6805 00:40:45.823213 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6806 00:40:45.826401 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6807 00:40:45.833021 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6808 00:40:45.836583 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6809 00:40:45.840016 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6810 00:40:45.843609 Total UI for P1: 0, mck2ui 16
6811 00:40:45.846966 best dqsien dly found for B0: ( 0, 14, 24)
6812 00:40:45.850217 Total UI for P1: 0, mck2ui 16
6813 00:40:45.853434 best dqsien dly found for B1: ( 0, 14, 24)
6814 00:40:45.856398 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6815 00:40:45.859943 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6816 00:40:45.860026
6817 00:40:45.863560 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6818 00:40:45.869608 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6819 00:40:45.869683 [Gating] SW calibration Done
6820 00:40:45.873178 ==
6821 00:40:45.873271 Dram Type= 6, Freq= 0, CH_1, rank 1
6822 00:40:45.879915 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6823 00:40:45.880016 ==
6824 00:40:45.880106 RX Vref Scan: 0
6825 00:40:45.880190
6826 00:40:45.882973 RX Vref 0 -> 0, step: 1
6827 00:40:45.883040
6828 00:40:45.886462 RX Delay -410 -> 252, step: 16
6829 00:40:45.890177 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6830 00:40:45.893380 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6831 00:40:45.900035 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6832 00:40:45.903272 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6833 00:40:45.906144 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6834 00:40:45.909509 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6835 00:40:45.916041 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6836 00:40:45.919433 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6837 00:40:45.922868 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6838 00:40:45.926116 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6839 00:40:45.933021 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6840 00:40:45.936366 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6841 00:40:45.939621 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6842 00:40:45.942706 iDelay=230, Bit 13, Center -11 (-250 ~ 229) 480
6843 00:40:45.949255 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6844 00:40:45.952843 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6845 00:40:45.952936 ==
6846 00:40:45.956257 Dram Type= 6, Freq= 0, CH_1, rank 1
6847 00:40:45.959600 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6848 00:40:45.959677 ==
6849 00:40:45.962913 DQS Delay:
6850 00:40:45.962982 DQS0 = 35, DQS1 = 35
6851 00:40:45.966013 DQM Delay:
6852 00:40:45.966081 DQM0 = 18, DQM1 = 14
6853 00:40:45.966137 DQ Delay:
6854 00:40:45.969758 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6855 00:40:45.972520 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6856 00:40:45.975852 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6857 00:40:45.979194 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =24
6858 00:40:45.979287
6859 00:40:45.979369
6860 00:40:45.979452 ==
6861 00:40:45.982818 Dram Type= 6, Freq= 0, CH_1, rank 1
6862 00:40:45.989425 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6863 00:40:45.989516 ==
6864 00:40:45.989610
6865 00:40:45.989699
6866 00:40:45.989781 TX Vref Scan disable
6867 00:40:45.992651 == TX Byte 0 ==
6868 00:40:45.995876 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6869 00:40:45.999716 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6870 00:40:46.002666 == TX Byte 1 ==
6871 00:40:46.006117 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6872 00:40:46.009373 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6873 00:40:46.009463 ==
6874 00:40:46.012985 Dram Type= 6, Freq= 0, CH_1, rank 1
6875 00:40:46.019651 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6876 00:40:46.019750 ==
6877 00:40:46.019835
6878 00:40:46.019924
6879 00:40:46.019982 TX Vref Scan disable
6880 00:40:46.023064 == TX Byte 0 ==
6881 00:40:46.026343 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6882 00:40:46.029745 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6883 00:40:46.032500 == TX Byte 1 ==
6884 00:40:46.036385 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6885 00:40:46.039738 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6886 00:40:46.039833
6887 00:40:46.043017 [DATLAT]
6888 00:40:46.043118 Freq=400, CH1 RK1
6889 00:40:46.043210
6890 00:40:46.046445 DATLAT Default: 0xe
6891 00:40:46.046535 0, 0xFFFF, sum = 0
6892 00:40:46.049197 1, 0xFFFF, sum = 0
6893 00:40:46.049292 2, 0xFFFF, sum = 0
6894 00:40:46.052611 3, 0xFFFF, sum = 0
6895 00:40:46.052707 4, 0xFFFF, sum = 0
6896 00:40:46.056446 5, 0xFFFF, sum = 0
6897 00:40:46.056540 6, 0xFFFF, sum = 0
6898 00:40:46.059567 7, 0xFFFF, sum = 0
6899 00:40:46.059663 8, 0xFFFF, sum = 0
6900 00:40:46.063096 9, 0xFFFF, sum = 0
6901 00:40:46.063168 10, 0xFFFF, sum = 0
6902 00:40:46.066022 11, 0xFFFF, sum = 0
6903 00:40:46.066120 12, 0xFFFF, sum = 0
6904 00:40:46.069045 13, 0x0, sum = 1
6905 00:40:46.069141 14, 0x0, sum = 2
6906 00:40:46.072648 15, 0x0, sum = 3
6907 00:40:46.072746 16, 0x0, sum = 4
6908 00:40:46.075770 best_step = 14
6909 00:40:46.075865
6910 00:40:46.075948 ==
6911 00:40:46.079055 Dram Type= 6, Freq= 0, CH_1, rank 1
6912 00:40:46.082652 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6913 00:40:46.082747 ==
6914 00:40:46.086051 RX Vref Scan: 0
6915 00:40:46.086122
6916 00:40:46.086205 RX Vref 0 -> 0, step: 1
6917 00:40:46.086287
6918 00:40:46.089454 RX Delay -311 -> 252, step: 8
6919 00:40:46.097586 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
6920 00:40:46.100830 iDelay=217, Bit 1, Center -20 (-239 ~ 200) 440
6921 00:40:46.103914 iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440
6922 00:40:46.107577 iDelay=217, Bit 3, Center -20 (-239 ~ 200) 440
6923 00:40:46.113627 iDelay=217, Bit 4, Center -20 (-239 ~ 200) 440
6924 00:40:46.117466 iDelay=217, Bit 5, Center -8 (-231 ~ 216) 448
6925 00:40:46.120849 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6926 00:40:46.124131 iDelay=217, Bit 7, Center -16 (-239 ~ 208) 448
6927 00:40:46.130304 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6928 00:40:46.133873 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6929 00:40:46.137047 iDelay=217, Bit 10, Center -16 (-239 ~ 208) 448
6930 00:40:46.140846 iDelay=217, Bit 11, Center -28 (-255 ~ 200) 456
6931 00:40:46.147060 iDelay=217, Bit 12, Center -12 (-239 ~ 216) 456
6932 00:40:46.150357 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
6933 00:40:46.153712 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6934 00:40:46.157101 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
6935 00:40:46.160501 ==
6936 00:40:46.163816 Dram Type= 6, Freq= 0, CH_1, rank 1
6937 00:40:46.167264 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6938 00:40:46.167364 ==
6939 00:40:46.167457 DQS Delay:
6940 00:40:46.170565 DQS0 = 28, DQS1 = 36
6941 00:40:46.170657 DQM Delay:
6942 00:40:46.173862 DQM0 = 11, DQM1 = 15
6943 00:40:46.173955 DQ Delay:
6944 00:40:46.176951 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6945 00:40:46.180495 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =12
6946 00:40:46.183797 DQ8 =0, DQ9 =4, DQ10 =20, DQ11 =8
6947 00:40:46.186920 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =24
6948 00:40:46.187000
6949 00:40:46.187060
6950 00:40:46.193705 [DQSOSCAuto] RK1, (LSB)MR18= 0xc958, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 384 ps
6951 00:40:46.197124 CH1 RK1: MR19=C0C, MR18=C958
6952 00:40:46.203996 CH1_RK1: MR19=0xC0C, MR18=0xC958, DQSOSC=384, MR23=63, INC=400, DEC=267
6953 00:40:46.207383 [RxdqsGatingPostProcess] freq 400
6954 00:40:46.210153 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6955 00:40:46.213465 best DQS0 dly(2T, 0.5T) = (0, 10)
6956 00:40:46.217295 best DQS1 dly(2T, 0.5T) = (0, 10)
6957 00:40:46.220380 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6958 00:40:46.224069 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6959 00:40:46.226819 best DQS0 dly(2T, 0.5T) = (0, 10)
6960 00:40:46.230077 best DQS1 dly(2T, 0.5T) = (0, 10)
6961 00:40:46.233495 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6962 00:40:46.237106 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6963 00:40:46.240309 Pre-setting of DQS Precalculation
6964 00:40:46.243859 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6965 00:40:46.253706 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6966 00:40:46.260036 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6967 00:40:46.260136
6968 00:40:46.260220
6969 00:40:46.263347 [Calibration Summary] 800 Mbps
6970 00:40:46.263447 CH 0, Rank 0
6971 00:40:46.266866 SW Impedance : PASS
6972 00:40:46.266939 DUTY Scan : NO K
6973 00:40:46.270276 ZQ Calibration : PASS
6974 00:40:46.273686 Jitter Meter : NO K
6975 00:40:46.273779 CBT Training : PASS
6976 00:40:46.277079 Write leveling : PASS
6977 00:40:46.279895 RX DQS gating : PASS
6978 00:40:46.279994 RX DQ/DQS(RDDQC) : PASS
6979 00:40:46.283353 TX DQ/DQS : PASS
6980 00:40:46.286705 RX DATLAT : PASS
6981 00:40:46.286771 RX DQ/DQS(Engine): PASS
6982 00:40:46.290031 TX OE : NO K
6983 00:40:46.290121 All Pass.
6984 00:40:46.290202
6985 00:40:46.293244 CH 0, Rank 1
6986 00:40:46.293333 SW Impedance : PASS
6987 00:40:46.296939 DUTY Scan : NO K
6988 00:40:46.299861 ZQ Calibration : PASS
6989 00:40:46.299950 Jitter Meter : NO K
6990 00:40:46.303457 CBT Training : PASS
6991 00:40:46.303554 Write leveling : NO K
6992 00:40:46.306497 RX DQS gating : PASS
6993 00:40:46.309856 RX DQ/DQS(RDDQC) : PASS
6994 00:40:46.309929 TX DQ/DQS : PASS
6995 00:40:46.313171 RX DATLAT : PASS
6996 00:40:46.316521 RX DQ/DQS(Engine): PASS
6997 00:40:46.316620 TX OE : NO K
6998 00:40:46.319997 All Pass.
6999 00:40:46.320099
7000 00:40:46.320186 CH 1, Rank 0
7001 00:40:46.323274 SW Impedance : PASS
7002 00:40:46.323372 DUTY Scan : NO K
7003 00:40:46.326573 ZQ Calibration : PASS
7004 00:40:46.329672 Jitter Meter : NO K
7005 00:40:46.329768 CBT Training : PASS
7006 00:40:46.332772 Write leveling : PASS
7007 00:40:46.336601 RX DQS gating : PASS
7008 00:40:46.336706 RX DQ/DQS(RDDQC) : PASS
7009 00:40:46.339819 TX DQ/DQS : PASS
7010 00:40:46.343130 RX DATLAT : PASS
7011 00:40:46.343202 RX DQ/DQS(Engine): PASS
7012 00:40:46.346525 TX OE : NO K
7013 00:40:46.346596 All Pass.
7014 00:40:46.346653
7015 00:40:46.349905 CH 1, Rank 1
7016 00:40:46.349993 SW Impedance : PASS
7017 00:40:46.353247 DUTY Scan : NO K
7018 00:40:46.356622 ZQ Calibration : PASS
7019 00:40:46.356696 Jitter Meter : NO K
7020 00:40:46.359685 CBT Training : PASS
7021 00:40:46.362949 Write leveling : NO K
7022 00:40:46.363039 RX DQS gating : PASS
7023 00:40:46.366026 RX DQ/DQS(RDDQC) : PASS
7024 00:40:46.369130 TX DQ/DQS : PASS
7025 00:40:46.369218 RX DATLAT : PASS
7026 00:40:46.372616 RX DQ/DQS(Engine): PASS
7027 00:40:46.372709 TX OE : NO K
7028 00:40:46.376061 All Pass.
7029 00:40:46.376152
7030 00:40:46.376237 DramC Write-DBI off
7031 00:40:46.379517 PER_BANK_REFRESH: Hybrid Mode
7032 00:40:46.382536 TX_TRACKING: ON
7033 00:40:46.389374 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7034 00:40:46.392795 [FAST_K] Save calibration result to emmc
7035 00:40:46.396221 dramc_set_vcore_voltage set vcore to 725000
7036 00:40:46.399624 Read voltage for 1600, 0
7037 00:40:46.399715 Vio18 = 0
7038 00:40:46.402988 Vcore = 725000
7039 00:40:46.403081 Vdram = 0
7040 00:40:46.403163 Vddq = 0
7041 00:40:46.406265 Vmddr = 0
7042 00:40:46.409362 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7043 00:40:46.416066 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7044 00:40:46.419127 MEM_TYPE=3, freq_sel=13
7045 00:40:46.419221 sv_algorithm_assistance_LP4_3733
7046 00:40:46.425712 ============ PULL DRAM RESETB DOWN ============
7047 00:40:46.429132 ========== PULL DRAM RESETB DOWN end =========
7048 00:40:46.432478 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7049 00:40:46.435246 ===================================
7050 00:40:46.439161 LPDDR4 DRAM CONFIGURATION
7051 00:40:46.442368 ===================================
7052 00:40:46.445366 EX_ROW_EN[0] = 0x0
7053 00:40:46.445468 EX_ROW_EN[1] = 0x0
7054 00:40:46.448955 LP4Y_EN = 0x0
7055 00:40:46.449053 WORK_FSP = 0x1
7056 00:40:46.452053 WL = 0x5
7057 00:40:46.452151 RL = 0x5
7058 00:40:46.455307 BL = 0x2
7059 00:40:46.455403 RPST = 0x0
7060 00:40:46.458744 RD_PRE = 0x0
7061 00:40:46.458835 WR_PRE = 0x1
7062 00:40:46.462096 WR_PST = 0x1
7063 00:40:46.462189 DBI_WR = 0x0
7064 00:40:46.465263 DBI_RD = 0x0
7065 00:40:46.465362 OTF = 0x1
7066 00:40:46.469130 ===================================
7067 00:40:46.471831 ===================================
7068 00:40:46.475210 ANA top config
7069 00:40:46.478987 ===================================
7070 00:40:46.481726 DLL_ASYNC_EN = 0
7071 00:40:46.481821 ALL_SLAVE_EN = 0
7072 00:40:46.485099 NEW_RANK_MODE = 1
7073 00:40:46.488731 DLL_IDLE_MODE = 1
7074 00:40:46.491623 LP45_APHY_COMB_EN = 1
7075 00:40:46.495085 TX_ODT_DIS = 0
7076 00:40:46.495182 NEW_8X_MODE = 1
7077 00:40:46.498627 ===================================
7078 00:40:46.502011 ===================================
7079 00:40:46.505455 data_rate = 3200
7080 00:40:46.508194 CKR = 1
7081 00:40:46.512091 DQ_P2S_RATIO = 8
7082 00:40:46.515600 ===================================
7083 00:40:46.518314 CA_P2S_RATIO = 8
7084 00:40:46.521777 DQ_CA_OPEN = 0
7085 00:40:46.521849 DQ_SEMI_OPEN = 0
7086 00:40:46.524946 CA_SEMI_OPEN = 0
7087 00:40:46.528188 CA_FULL_RATE = 0
7088 00:40:46.531687 DQ_CKDIV4_EN = 0
7089 00:40:46.534761 CA_CKDIV4_EN = 0
7090 00:40:46.538611 CA_PREDIV_EN = 0
7091 00:40:46.538712 PH8_DLY = 12
7092 00:40:46.542084 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7093 00:40:46.544752 DQ_AAMCK_DIV = 4
7094 00:40:46.548746 CA_AAMCK_DIV = 4
7095 00:40:46.552146 CA_ADMCK_DIV = 4
7096 00:40:46.554778 DQ_TRACK_CA_EN = 0
7097 00:40:46.554875 CA_PICK = 1600
7098 00:40:46.558470 CA_MCKIO = 1600
7099 00:40:46.561514 MCKIO_SEMI = 0
7100 00:40:46.565019 PLL_FREQ = 3068
7101 00:40:46.568246 DQ_UI_PI_RATIO = 32
7102 00:40:46.571530 CA_UI_PI_RATIO = 0
7103 00:40:46.575195 ===================================
7104 00:40:46.578595 ===================================
7105 00:40:46.578673 memory_type:LPDDR4
7106 00:40:46.581315 GP_NUM : 10
7107 00:40:46.584657 SRAM_EN : 1
7108 00:40:46.584755 MD32_EN : 0
7109 00:40:46.588083 ===================================
7110 00:40:46.591470 [ANA_INIT] >>>>>>>>>>>>>>
7111 00:40:46.594959 <<<<<< [CONFIGURE PHASE]: ANA_TX
7112 00:40:46.598388 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7113 00:40:46.601708 ===================================
7114 00:40:46.604728 data_rate = 3200,PCW = 0X7600
7115 00:40:46.608263 ===================================
7116 00:40:46.611259 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7117 00:40:46.614893 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7118 00:40:46.621214 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7119 00:40:46.624629 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7120 00:40:46.631383 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7121 00:40:46.634770 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7122 00:40:46.634869 [ANA_INIT] flow start
7123 00:40:46.637860 [ANA_INIT] PLL >>>>>>>>
7124 00:40:46.641009 [ANA_INIT] PLL <<<<<<<<
7125 00:40:46.641106 [ANA_INIT] MIDPI >>>>>>>>
7126 00:40:46.644700 [ANA_INIT] MIDPI <<<<<<<<
7127 00:40:46.647775 [ANA_INIT] DLL >>>>>>>>
7128 00:40:46.647869 [ANA_INIT] DLL <<<<<<<<
7129 00:40:46.651356 [ANA_INIT] flow end
7130 00:40:46.654649 ============ LP4 DIFF to SE enter ============
7131 00:40:46.657371 ============ LP4 DIFF to SE exit ============
7132 00:40:46.660783 [ANA_INIT] <<<<<<<<<<<<<
7133 00:40:46.664230 [Flow] Enable top DCM control >>>>>
7134 00:40:46.667454 [Flow] Enable top DCM control <<<<<
7135 00:40:46.671249 Enable DLL master slave shuffle
7136 00:40:46.677745 ==============================================================
7137 00:40:46.677841 Gating Mode config
7138 00:40:46.684151 ==============================================================
7139 00:40:46.684249 Config description:
7140 00:40:46.694298 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7141 00:40:46.701153 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7142 00:40:46.707613 SELPH_MODE 0: By rank 1: By Phase
7143 00:40:46.710981 ==============================================================
7144 00:40:46.714245 GAT_TRACK_EN = 1
7145 00:40:46.717479 RX_GATING_MODE = 2
7146 00:40:46.721043 RX_GATING_TRACK_MODE = 2
7147 00:40:46.723911 SELPH_MODE = 1
7148 00:40:46.727436 PICG_EARLY_EN = 1
7149 00:40:46.730955 VALID_LAT_VALUE = 1
7150 00:40:46.737695 ==============================================================
7151 00:40:46.740880 Enter into Gating configuration >>>>
7152 00:40:46.744116 Exit from Gating configuration <<<<
7153 00:40:46.744205 Enter into DVFS_PRE_config >>>>>
7154 00:40:46.757028 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7155 00:40:46.760405 Exit from DVFS_PRE_config <<<<<
7156 00:40:46.763831 Enter into PICG configuration >>>>
7157 00:40:46.767241 Exit from PICG configuration <<<<
7158 00:40:46.767321 [RX_INPUT] configuration >>>>>
7159 00:40:46.770564 [RX_INPUT] configuration <<<<<
7160 00:40:46.777428 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7161 00:40:46.780708 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7162 00:40:46.787813 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7163 00:40:46.793689 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7164 00:40:46.800791 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7165 00:40:46.807045 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7166 00:40:46.810833 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7167 00:40:46.814176 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7168 00:40:46.820900 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7169 00:40:46.823656 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7170 00:40:46.826932 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7171 00:40:46.830748 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7172 00:40:46.833819 ===================================
7173 00:40:46.837587 LPDDR4 DRAM CONFIGURATION
7174 00:40:46.840500 ===================================
7175 00:40:46.844091 EX_ROW_EN[0] = 0x0
7176 00:40:46.844195 EX_ROW_EN[1] = 0x0
7177 00:40:46.847149 LP4Y_EN = 0x0
7178 00:40:46.847241 WORK_FSP = 0x1
7179 00:40:46.850416 WL = 0x5
7180 00:40:46.850510 RL = 0x5
7181 00:40:46.853578 BL = 0x2
7182 00:40:46.853673 RPST = 0x0
7183 00:40:46.857364 RD_PRE = 0x0
7184 00:40:46.857466 WR_PRE = 0x1
7185 00:40:46.860341 WR_PST = 0x1
7186 00:40:46.860447 DBI_WR = 0x0
7187 00:40:46.864189 DBI_RD = 0x0
7188 00:40:46.864299 OTF = 0x1
7189 00:40:46.867490 ===================================
7190 00:40:46.873585 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7191 00:40:46.876982 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7192 00:40:46.880351 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7193 00:40:46.883738 ===================================
7194 00:40:46.887110 LPDDR4 DRAM CONFIGURATION
7195 00:40:46.890316 ===================================
7196 00:40:46.893608 EX_ROW_EN[0] = 0x10
7197 00:40:46.893715 EX_ROW_EN[1] = 0x0
7198 00:40:46.896895 LP4Y_EN = 0x0
7199 00:40:46.896973 WORK_FSP = 0x1
7200 00:40:46.900319 WL = 0x5
7201 00:40:46.900417 RL = 0x5
7202 00:40:46.903771 BL = 0x2
7203 00:40:46.903867 RPST = 0x0
7204 00:40:46.907238 RD_PRE = 0x0
7205 00:40:46.907305 WR_PRE = 0x1
7206 00:40:46.910464 WR_PST = 0x1
7207 00:40:46.910532 DBI_WR = 0x0
7208 00:40:46.913621 DBI_RD = 0x0
7209 00:40:46.913716 OTF = 0x1
7210 00:40:46.917243 ===================================
7211 00:40:46.923431 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7212 00:40:46.923506 ==
7213 00:40:46.927170 Dram Type= 6, Freq= 0, CH_0, rank 0
7214 00:40:46.933812 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7215 00:40:46.933887 ==
7216 00:40:46.933950 [Duty_Offset_Calibration]
7217 00:40:46.937203 B0:2 B1:1 CA:1
7218 00:40:46.937276
7219 00:40:46.940612 [DutyScan_Calibration_Flow] k_type=0
7220 00:40:46.949145
7221 00:40:46.949240 ==CLK 0==
7222 00:40:46.952817 Final CLK duty delay cell = 0
7223 00:40:46.956013 [0] MAX Duty = 5156%(X100), DQS PI = 22
7224 00:40:46.959158 [0] MIN Duty = 4876%(X100), DQS PI = 48
7225 00:40:46.959248 [0] AVG Duty = 5016%(X100)
7226 00:40:46.962932
7227 00:40:46.963036 CH0 CLK Duty spec in!! Max-Min= 280%
7228 00:40:46.969650 [DutyScan_Calibration_Flow] ====Done====
7229 00:40:46.969753
7230 00:40:46.972743 [DutyScan_Calibration_Flow] k_type=1
7231 00:40:46.988633
7232 00:40:46.988730 ==DQS 0 ==
7233 00:40:46.991942 Final DQS duty delay cell = -4
7234 00:40:46.995222 [-4] MAX Duty = 5125%(X100), DQS PI = 24
7235 00:40:46.998454 [-4] MIN Duty = 4657%(X100), DQS PI = 0
7236 00:40:47.001714 [-4] AVG Duty = 4891%(X100)
7237 00:40:47.001790
7238 00:40:47.001847 ==DQS 1 ==
7239 00:40:47.005090 Final DQS duty delay cell = 0
7240 00:40:47.008330 [0] MAX Duty = 5187%(X100), DQS PI = 20
7241 00:40:47.011741 [0] MIN Duty = 5031%(X100), DQS PI = 52
7242 00:40:47.015130 [0] AVG Duty = 5109%(X100)
7243 00:40:47.015224
7244 00:40:47.018491 CH0 DQS 0 Duty spec in!! Max-Min= 468%
7245 00:40:47.018588
7246 00:40:47.021769 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7247 00:40:47.025611 [DutyScan_Calibration_Flow] ====Done====
7248 00:40:47.025705
7249 00:40:47.028669 [DutyScan_Calibration_Flow] k_type=3
7250 00:40:47.045316
7251 00:40:47.045423 ==DQM 0 ==
7252 00:40:47.048772 Final DQM duty delay cell = 0
7253 00:40:47.052104 [0] MAX Duty = 5187%(X100), DQS PI = 26
7254 00:40:47.055296 [0] MIN Duty = 4844%(X100), DQS PI = 60
7255 00:40:47.058469 [0] AVG Duty = 5015%(X100)
7256 00:40:47.058568
7257 00:40:47.058661 ==DQM 1 ==
7258 00:40:47.061647 Final DQM duty delay cell = -4
7259 00:40:47.064807 [-4] MAX Duty = 4969%(X100), DQS PI = 22
7260 00:40:47.068137 [-4] MIN Duty = 4813%(X100), DQS PI = 50
7261 00:40:47.071373 [-4] AVG Duty = 4891%(X100)
7262 00:40:47.071506
7263 00:40:47.074992 CH0 DQM 0 Duty spec in!! Max-Min= 343%
7264 00:40:47.075136
7265 00:40:47.078044 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7266 00:40:47.081784 [DutyScan_Calibration_Flow] ====Done====
7267 00:40:47.081929
7268 00:40:47.084985 [DutyScan_Calibration_Flow] k_type=2
7269 00:40:47.102904
7270 00:40:47.103059 ==DQ 0 ==
7271 00:40:47.106143 Final DQ duty delay cell = 0
7272 00:40:47.109503 [0] MAX Duty = 5062%(X100), DQS PI = 26
7273 00:40:47.112807 [0] MIN Duty = 4907%(X100), DQS PI = 0
7274 00:40:47.112901 [0] AVG Duty = 4984%(X100)
7275 00:40:47.112986
7276 00:40:47.116163 ==DQ 1 ==
7277 00:40:47.119082 Final DQ duty delay cell = 0
7278 00:40:47.122412 [0] MAX Duty = 5125%(X100), DQS PI = 22
7279 00:40:47.125804 [0] MIN Duty = 4938%(X100), DQS PI = 32
7280 00:40:47.125902 [0] AVG Duty = 5031%(X100)
7281 00:40:47.125999
7282 00:40:47.129126 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7283 00:40:47.132451
7284 00:40:47.135774 CH0 DQ 1 Duty spec in!! Max-Min= 187%
7285 00:40:47.139042 [DutyScan_Calibration_Flow] ====Done====
7286 00:40:47.139136 ==
7287 00:40:47.142281 Dram Type= 6, Freq= 0, CH_1, rank 0
7288 00:40:47.146164 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7289 00:40:47.146262 ==
7290 00:40:47.149086 [Duty_Offset_Calibration]
7291 00:40:47.149179 B0:1 B1:0 CA:0
7292 00:40:47.149279
7293 00:40:47.152664 [DutyScan_Calibration_Flow] k_type=0
7294 00:40:47.162397
7295 00:40:47.162496 ==CLK 0==
7296 00:40:47.165613 Final CLK duty delay cell = -4
7297 00:40:47.168674 [-4] MAX Duty = 4969%(X100), DQS PI = 20
7298 00:40:47.171747 [-4] MIN Duty = 4844%(X100), DQS PI = 2
7299 00:40:47.175482 [-4] AVG Duty = 4906%(X100)
7300 00:40:47.175581
7301 00:40:47.178661 CH1 CLK Duty spec in!! Max-Min= 125%
7302 00:40:47.181907 [DutyScan_Calibration_Flow] ====Done====
7303 00:40:47.181984
7304 00:40:47.184927 [DutyScan_Calibration_Flow] k_type=1
7305 00:40:47.202129
7306 00:40:47.202237 ==DQS 0 ==
7307 00:40:47.205502 Final DQS duty delay cell = 0
7308 00:40:47.208703 [0] MAX Duty = 5093%(X100), DQS PI = 26
7309 00:40:47.212042 [0] MIN Duty = 4844%(X100), DQS PI = 0
7310 00:40:47.215285 [0] AVG Duty = 4968%(X100)
7311 00:40:47.215377
7312 00:40:47.215459 ==DQS 1 ==
7313 00:40:47.218856 Final DQS duty delay cell = 0
7314 00:40:47.222178 [0] MAX Duty = 5249%(X100), DQS PI = 18
7315 00:40:47.225671 [0] MIN Duty = 4938%(X100), DQS PI = 8
7316 00:40:47.228267 [0] AVG Duty = 5093%(X100)
7317 00:40:47.228362
7318 00:40:47.231733 CH1 DQS 0 Duty spec in!! Max-Min= 249%
7319 00:40:47.231830
7320 00:40:47.235098 CH1 DQS 1 Duty spec in!! Max-Min= 311%
7321 00:40:47.238425 [DutyScan_Calibration_Flow] ====Done====
7322 00:40:47.238513
7323 00:40:47.241915 [DutyScan_Calibration_Flow] k_type=3
7324 00:40:47.258954
7325 00:40:47.259053 ==DQM 0 ==
7326 00:40:47.262105 Final DQM duty delay cell = 0
7327 00:40:47.265155 [0] MAX Duty = 5187%(X100), DQS PI = 10
7328 00:40:47.269063 [0] MIN Duty = 4969%(X100), DQS PI = 46
7329 00:40:47.272212 [0] AVG Duty = 5078%(X100)
7330 00:40:47.272314
7331 00:40:47.272401 ==DQM 1 ==
7332 00:40:47.275391 Final DQM duty delay cell = 0
7333 00:40:47.278675 [0] MAX Duty = 5062%(X100), DQS PI = 24
7334 00:40:47.282065 [0] MIN Duty = 4876%(X100), DQS PI = 50
7335 00:40:47.285297 [0] AVG Duty = 4969%(X100)
7336 00:40:47.285363
7337 00:40:47.288382 CH1 DQM 0 Duty spec in!! Max-Min= 218%
7338 00:40:47.288486
7339 00:40:47.291658 CH1 DQM 1 Duty spec in!! Max-Min= 186%
7340 00:40:47.295482 [DutyScan_Calibration_Flow] ====Done====
7341 00:40:47.295583
7342 00:40:47.298346 [DutyScan_Calibration_Flow] k_type=2
7343 00:40:47.314938
7344 00:40:47.315041 ==DQ 0 ==
7345 00:40:47.318313 Final DQ duty delay cell = -4
7346 00:40:47.321427 [-4] MAX Duty = 5031%(X100), DQS PI = 10
7347 00:40:47.324979 [-4] MIN Duty = 4844%(X100), DQS PI = 48
7348 00:40:47.328333 [-4] AVG Duty = 4937%(X100)
7349 00:40:47.328436
7350 00:40:47.328523 ==DQ 1 ==
7351 00:40:47.331675 Final DQ duty delay cell = 0
7352 00:40:47.335166 [0] MAX Duty = 5124%(X100), DQS PI = 18
7353 00:40:47.337940 [0] MIN Duty = 4938%(X100), DQS PI = 8
7354 00:40:47.341743 [0] AVG Duty = 5031%(X100)
7355 00:40:47.341838
7356 00:40:47.344505 CH1 DQ 0 Duty spec in!! Max-Min= 187%
7357 00:40:47.344598
7358 00:40:47.347997 CH1 DQ 1 Duty spec in!! Max-Min= 186%
7359 00:40:47.351368 [DutyScan_Calibration_Flow] ====Done====
7360 00:40:47.354709 nWR fixed to 30
7361 00:40:47.358168 [ModeRegInit_LP4] CH0 RK0
7362 00:40:47.358264 [ModeRegInit_LP4] CH0 RK1
7363 00:40:47.361427 [ModeRegInit_LP4] CH1 RK0
7364 00:40:47.364775 [ModeRegInit_LP4] CH1 RK1
7365 00:40:47.364873 match AC timing 5
7366 00:40:47.370972 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7367 00:40:47.374361 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7368 00:40:47.378052 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7369 00:40:47.384926 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7370 00:40:47.387864 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7371 00:40:47.387962 [MiockJmeterHQA]
7372 00:40:47.388046
7373 00:40:47.391191 [DramcMiockJmeter] u1RxGatingPI = 0
7374 00:40:47.394436 0 : 4253, 4026
7375 00:40:47.394536 4 : 4365, 4140
7376 00:40:47.398250 8 : 4363, 4138
7377 00:40:47.398344 12 : 4253, 4027
7378 00:40:47.398437 16 : 4365, 4140
7379 00:40:47.400978 20 : 4252, 4027
7380 00:40:47.401075 24 : 4252, 4027
7381 00:40:47.404745 28 : 4255, 4029
7382 00:40:47.404813 32 : 4363, 4137
7383 00:40:47.407781 36 : 4363, 4137
7384 00:40:47.407846 40 : 4363, 4137
7385 00:40:47.411490 44 : 4255, 4029
7386 00:40:47.411568 48 : 4255, 4029
7387 00:40:47.411626 52 : 4252, 4027
7388 00:40:47.414695 56 : 4255, 4029
7389 00:40:47.414791 60 : 4363, 4137
7390 00:40:47.418052 64 : 4250, 4027
7391 00:40:47.418120 68 : 4253, 4027
7392 00:40:47.421251 72 : 4250, 4027
7393 00:40:47.421342 76 : 4252, 4030
7394 00:40:47.424562 80 : 4252, 4030
7395 00:40:47.424669 84 : 4361, 4137
7396 00:40:47.424756 88 : 4361, 251
7397 00:40:47.427863 92 : 4250, 0
7398 00:40:47.427965 96 : 4361, 0
7399 00:40:47.428057 100 : 4360, 0
7400 00:40:47.431201 104 : 4250, 0
7401 00:40:47.431272 108 : 4252, 0
7402 00:40:47.434606 112 : 4250, 0
7403 00:40:47.434674 116 : 4250, 0
7404 00:40:47.434742 120 : 4361, 0
7405 00:40:47.438176 124 : 4250, 0
7406 00:40:47.438241 128 : 4363, 0
7407 00:40:47.441426 132 : 4252, 0
7408 00:40:47.441517 136 : 4252, 0
7409 00:40:47.441592 140 : 4360, 0
7410 00:40:47.444736 144 : 4250, 0
7411 00:40:47.444834 148 : 4250, 0
7412 00:40:47.444917 152 : 4250, 0
7413 00:40:47.447938 156 : 4250, 0
7414 00:40:47.448007 160 : 4252, 0
7415 00:40:47.451212 164 : 4250, 0
7416 00:40:47.451306 168 : 4250, 0
7417 00:40:47.451397 172 : 4361, 0
7418 00:40:47.454627 176 : 4366, 0
7419 00:40:47.454696 180 : 4360, 0
7420 00:40:47.458047 184 : 4250, 0
7421 00:40:47.458117 188 : 4366, 0
7422 00:40:47.458174 192 : 4250, 0
7423 00:40:47.461489 196 : 4250, 0
7424 00:40:47.461598 200 : 4250, 0
7425 00:40:47.464242 204 : 4250, 1113
7426 00:40:47.464345 208 : 4252, 3972
7427 00:40:47.467586 212 : 4250, 4027
7428 00:40:47.467671 216 : 4250, 4026
7429 00:40:47.467731 220 : 4250, 4027
7430 00:40:47.471006 224 : 4361, 4137
7431 00:40:47.471079 228 : 4360, 4137
7432 00:40:47.474414 232 : 4250, 4027
7433 00:40:47.474484 236 : 4360, 4137
7434 00:40:47.478141 240 : 4250, 4026
7435 00:40:47.478243 244 : 4249, 4027
7436 00:40:47.481201 248 : 4249, 4027
7437 00:40:47.481295 252 : 4363, 4139
7438 00:40:47.484460 256 : 4250, 4026
7439 00:40:47.484534 260 : 4249, 4027
7440 00:40:47.487773 264 : 4363, 4140
7441 00:40:47.487875 268 : 4250, 4026
7442 00:40:47.490996 272 : 4250, 4026
7443 00:40:47.491094 276 : 4361, 4137
7444 00:40:47.491163 280 : 4361, 4137
7445 00:40:47.494802 284 : 4250, 4026
7446 00:40:47.494884 288 : 4250, 4027
7447 00:40:47.497758 292 : 4250, 4027
7448 00:40:47.497852 296 : 4250, 4027
7449 00:40:47.501335 300 : 4250, 4027
7450 00:40:47.501405 304 : 4361, 4137
7451 00:40:47.504247 308 : 4250, 4008
7452 00:40:47.504331 312 : 4249, 2206
7453 00:40:47.508019 316 : 4361, 10
7454 00:40:47.508117
7455 00:40:47.508201 MIOCK jitter meter ch=0
7456 00:40:47.508283
7457 00:40:47.511198 1T = (316-88) = 228 dly cells
7458 00:40:47.517401 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 285/100 ps
7459 00:40:47.517497 ==
7460 00:40:47.520950 Dram Type= 6, Freq= 0, CH_0, rank 0
7461 00:40:47.524139 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7462 00:40:47.524208 ==
7463 00:40:47.531137 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7464 00:40:47.534378 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7465 00:40:47.537494 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7466 00:40:47.544164 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7467 00:40:47.554101 [CA 0] Center 43 (12~74) winsize 63
7468 00:40:47.557446 [CA 1] Center 43 (13~74) winsize 62
7469 00:40:47.560996 [CA 2] Center 38 (9~68) winsize 60
7470 00:40:47.563713 [CA 3] Center 38 (8~68) winsize 61
7471 00:40:47.567122 [CA 4] Center 36 (7~66) winsize 60
7472 00:40:47.570452 [CA 5] Center 36 (7~65) winsize 59
7473 00:40:47.570552
7474 00:40:47.573749 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7475 00:40:47.573816
7476 00:40:47.577176 [CATrainingPosCal] consider 1 rank data
7477 00:40:47.580617 u2DelayCellTimex100 = 285/100 ps
7478 00:40:47.583841 CA0 delay=43 (12~74),Diff = 7 PI (23 cell)
7479 00:40:47.590213 CA1 delay=43 (13~74),Diff = 7 PI (23 cell)
7480 00:40:47.593985 CA2 delay=38 (9~68),Diff = 2 PI (6 cell)
7481 00:40:47.597271 CA3 delay=38 (8~68),Diff = 2 PI (6 cell)
7482 00:40:47.600665 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7483 00:40:47.603911 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
7484 00:40:47.604007
7485 00:40:47.607313 CA PerBit enable=1, Macro0, CA PI delay=36
7486 00:40:47.607409
7487 00:40:47.610718 [CBTSetCACLKResult] CA Dly = 36
7488 00:40:47.613690 CS Dly: 9 (0~40)
7489 00:40:47.616694 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7490 00:40:47.620399 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7491 00:40:47.620525 ==
7492 00:40:47.623606 Dram Type= 6, Freq= 0, CH_0, rank 1
7493 00:40:47.626698 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7494 00:40:47.630257 ==
7495 00:40:47.633347 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7496 00:40:47.636966 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7497 00:40:47.643927 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7498 00:40:47.646847 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7499 00:40:47.657014 [CA 0] Center 42 (12~72) winsize 61
7500 00:40:47.660398 [CA 1] Center 42 (12~73) winsize 62
7501 00:40:47.663724 [CA 2] Center 37 (8~67) winsize 60
7502 00:40:47.667047 [CA 3] Center 37 (7~68) winsize 62
7503 00:40:47.670566 [CA 4] Center 35 (5~65) winsize 61
7504 00:40:47.674035 [CA 5] Center 35 (5~65) winsize 61
7505 00:40:47.674161
7506 00:40:47.677462 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7507 00:40:47.677560
7508 00:40:47.680895 [CATrainingPosCal] consider 2 rank data
7509 00:40:47.684365 u2DelayCellTimex100 = 285/100 ps
7510 00:40:47.687598 CA0 delay=42 (12~72),Diff = 6 PI (20 cell)
7511 00:40:47.694220 CA1 delay=43 (13~73),Diff = 7 PI (23 cell)
7512 00:40:47.697023 CA2 delay=38 (9~67),Diff = 2 PI (6 cell)
7513 00:40:47.700774 CA3 delay=38 (8~68),Diff = 2 PI (6 cell)
7514 00:40:47.703926 CA4 delay=36 (7~65),Diff = 0 PI (0 cell)
7515 00:40:47.707057 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
7516 00:40:47.707155
7517 00:40:47.710414 CA PerBit enable=1, Macro0, CA PI delay=36
7518 00:40:47.710509
7519 00:40:47.713922 [CBTSetCACLKResult] CA Dly = 36
7520 00:40:47.717229 CS Dly: 10 (0~42)
7521 00:40:47.720606 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7522 00:40:47.723750 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7523 00:40:47.723852
7524 00:40:47.726819 ----->DramcWriteLeveling(PI) begin...
7525 00:40:47.726915 ==
7526 00:40:47.729918 Dram Type= 6, Freq= 0, CH_0, rank 0
7527 00:40:47.736624 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7528 00:40:47.736721 ==
7529 00:40:47.740221 Write leveling (Byte 0): 35 => 35
7530 00:40:47.740325 Write leveling (Byte 1): 28 => 28
7531 00:40:47.743272 DramcWriteLeveling(PI) end<-----
7532 00:40:47.743363
7533 00:40:47.743447 ==
7534 00:40:47.746989 Dram Type= 6, Freq= 0, CH_0, rank 0
7535 00:40:47.753436 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7536 00:40:47.753539 ==
7537 00:40:47.757139 [Gating] SW mode calibration
7538 00:40:47.763525 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7539 00:40:47.767090 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7540 00:40:47.773135 1 4 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7541 00:40:47.776515 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7542 00:40:47.779932 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7543 00:40:47.786668 1 4 12 | B1->B0 | 2323 3434 | 0 0 | (0 0) (1 1)
7544 00:40:47.790191 1 4 16 | B1->B0 | 2424 3837 | 0 1 | (0 0) (1 1)
7545 00:40:47.793401 1 4 20 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)
7546 00:40:47.796701 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7547 00:40:47.803438 1 4 28 | B1->B0 | 3434 3636 | 1 0 | (1 1) (0 0)
7548 00:40:47.806432 1 5 0 | B1->B0 | 3434 3636 | 1 0 | (1 1) (0 0)
7549 00:40:47.809637 1 5 4 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
7550 00:40:47.816392 1 5 8 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
7551 00:40:47.819781 1 5 12 | B1->B0 | 3434 2424 | 1 0 | (1 1) (1 0)
7552 00:40:47.823202 1 5 16 | B1->B0 | 3333 2a29 | 1 1 | (1 1) (1 0)
7553 00:40:47.830057 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7554 00:40:47.833321 1 5 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7555 00:40:47.836655 1 5 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7556 00:40:47.843319 1 6 0 | B1->B0 | 2323 2625 | 0 1 | (0 0) (0 0)
7557 00:40:47.846345 1 6 4 | B1->B0 | 2323 2928 | 0 1 | (0 0) (0 0)
7558 00:40:47.849903 1 6 8 | B1->B0 | 2323 3636 | 0 0 | (0 0) (0 0)
7559 00:40:47.856496 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7560 00:40:47.859496 1 6 16 | B1->B0 | 2b2b 4646 | 0 0 | (0 0) (0 0)
7561 00:40:47.863024 1 6 20 | B1->B0 | 4545 4645 | 0 1 | (0 0) (0 0)
7562 00:40:47.869703 1 6 24 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
7563 00:40:47.873115 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7564 00:40:47.876808 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7565 00:40:47.882986 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7566 00:40:47.886281 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7567 00:40:47.889774 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7568 00:40:47.896464 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7569 00:40:47.899835 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7570 00:40:47.903315 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7571 00:40:47.909647 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7572 00:40:47.912976 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7573 00:40:47.916335 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7574 00:40:47.923132 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7575 00:40:47.926327 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7576 00:40:47.929741 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7577 00:40:47.935875 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7578 00:40:47.939160 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7579 00:40:47.942668 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7580 00:40:47.945910 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7581 00:40:47.952649 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7582 00:40:47.955869 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7583 00:40:47.959521 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7584 00:40:47.965876 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7585 00:40:47.969191 Total UI for P1: 0, mck2ui 16
7586 00:40:47.972941 best dqsien dly found for B0: ( 1, 9, 12)
7587 00:40:47.975997 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7588 00:40:47.978972 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7589 00:40:47.982665 Total UI for P1: 0, mck2ui 16
7590 00:40:47.985726 best dqsien dly found for B1: ( 1, 9, 20)
7591 00:40:47.989349 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
7592 00:40:47.992431 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7593 00:40:47.995703
7594 00:40:47.999084 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
7595 00:40:48.002466 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7596 00:40:48.005879 [Gating] SW calibration Done
7597 00:40:48.005972 ==
7598 00:40:48.009230 Dram Type= 6, Freq= 0, CH_0, rank 0
7599 00:40:48.012605 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7600 00:40:48.012706 ==
7601 00:40:48.012793 RX Vref Scan: 0
7602 00:40:48.015873
7603 00:40:48.015965 RX Vref 0 -> 0, step: 1
7604 00:40:48.016059
7605 00:40:48.019313 RX Delay 0 -> 252, step: 8
7606 00:40:48.022755 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
7607 00:40:48.025997 iDelay=200, Bit 1, Center 143 (88 ~ 199) 112
7608 00:40:48.032121 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
7609 00:40:48.035768 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7610 00:40:48.039087 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7611 00:40:48.042641 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7612 00:40:48.045967 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
7613 00:40:48.049314 iDelay=200, Bit 7, Center 143 (96 ~ 191) 96
7614 00:40:48.055348 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
7615 00:40:48.058756 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
7616 00:40:48.062166 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
7617 00:40:48.065591 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
7618 00:40:48.072347 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
7619 00:40:48.075466 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7620 00:40:48.078731 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7621 00:40:48.082108 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7622 00:40:48.082194 ==
7623 00:40:48.085085 Dram Type= 6, Freq= 0, CH_0, rank 0
7624 00:40:48.092185 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7625 00:40:48.092289 ==
7626 00:40:48.092377 DQS Delay:
7627 00:40:48.092466 DQS0 = 0, DQS1 = 0
7628 00:40:48.095119 DQM Delay:
7629 00:40:48.095212 DQM0 = 136, DQM1 = 129
7630 00:40:48.098698 DQ Delay:
7631 00:40:48.101904 DQ0 =135, DQ1 =143, DQ2 =135, DQ3 =131
7632 00:40:48.105345 DQ4 =139, DQ5 =123, DQ6 =143, DQ7 =143
7633 00:40:48.108359 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
7634 00:40:48.112029 DQ12 =135, DQ13 =135, DQ14 =139, DQ15 =135
7635 00:40:48.112122
7636 00:40:48.112212
7637 00:40:48.112292 ==
7638 00:40:48.115340 Dram Type= 6, Freq= 0, CH_0, rank 0
7639 00:40:48.118586 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7640 00:40:48.121837 ==
7641 00:40:48.121906
7642 00:40:48.121963
7643 00:40:48.122021 TX Vref Scan disable
7644 00:40:48.125209 == TX Byte 0 ==
7645 00:40:48.128701 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7646 00:40:48.132091 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7647 00:40:48.135439 == TX Byte 1 ==
7648 00:40:48.138773 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7649 00:40:48.141752 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7650 00:40:48.141820 ==
7651 00:40:48.145372 Dram Type= 6, Freq= 0, CH_0, rank 0
7652 00:40:48.152068 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7653 00:40:48.152153 ==
7654 00:40:48.162744
7655 00:40:48.166167 TX Vref early break, caculate TX vref
7656 00:40:48.169683 TX Vref=16, minBit 7, minWin=22, winSum=375
7657 00:40:48.173083 TX Vref=18, minBit 7, minWin=23, winSum=390
7658 00:40:48.176400 TX Vref=20, minBit 7, minWin=23, winSum=400
7659 00:40:48.179679 TX Vref=22, minBit 0, minWin=24, winSum=408
7660 00:40:48.182995 TX Vref=24, minBit 0, minWin=25, winSum=415
7661 00:40:48.189474 TX Vref=26, minBit 0, minWin=25, winSum=428
7662 00:40:48.193073 TX Vref=28, minBit 0, minWin=25, winSum=426
7663 00:40:48.196203 TX Vref=30, minBit 6, minWin=23, winSum=410
7664 00:40:48.199524 TX Vref=32, minBit 1, minWin=24, winSum=403
7665 00:40:48.206157 [TxChooseVref] Worse bit 0, Min win 25, Win sum 428, Final Vref 26
7666 00:40:48.206250
7667 00:40:48.209371 Final TX Range 0 Vref 26
7668 00:40:48.209461
7669 00:40:48.209545 ==
7670 00:40:48.213021 Dram Type= 6, Freq= 0, CH_0, rank 0
7671 00:40:48.215961 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7672 00:40:48.216077 ==
7673 00:40:48.216186
7674 00:40:48.216303
7675 00:40:48.219497 TX Vref Scan disable
7676 00:40:48.226061 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
7677 00:40:48.226159 == TX Byte 0 ==
7678 00:40:48.229640 u2DelayCellOfst[0]=13 cells (4 PI)
7679 00:40:48.232811 u2DelayCellOfst[1]=17 cells (5 PI)
7680 00:40:48.236100 u2DelayCellOfst[2]=13 cells (4 PI)
7681 00:40:48.239301 u2DelayCellOfst[3]=13 cells (4 PI)
7682 00:40:48.242887 u2DelayCellOfst[4]=10 cells (3 PI)
7683 00:40:48.246071 u2DelayCellOfst[5]=0 cells (0 PI)
7684 00:40:48.246153 u2DelayCellOfst[6]=20 cells (6 PI)
7685 00:40:48.249370 u2DelayCellOfst[7]=17 cells (5 PI)
7686 00:40:48.255550 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7687 00:40:48.259075 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7688 00:40:48.259183 == TX Byte 1 ==
7689 00:40:48.262299 u2DelayCellOfst[8]=0 cells (0 PI)
7690 00:40:48.265594 u2DelayCellOfst[9]=0 cells (0 PI)
7691 00:40:48.269018 u2DelayCellOfst[10]=6 cells (2 PI)
7692 00:40:48.272303 u2DelayCellOfst[11]=3 cells (1 PI)
7693 00:40:48.275698 u2DelayCellOfst[12]=10 cells (3 PI)
7694 00:40:48.279088 u2DelayCellOfst[13]=10 cells (3 PI)
7695 00:40:48.282431 u2DelayCellOfst[14]=13 cells (4 PI)
7696 00:40:48.285738 u2DelayCellOfst[15]=10 cells (3 PI)
7697 00:40:48.289091 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7698 00:40:48.292465 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7699 00:40:48.295727 DramC Write-DBI on
7700 00:40:48.295824 ==
7701 00:40:48.298975 Dram Type= 6, Freq= 0, CH_0, rank 0
7702 00:40:48.302619 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7703 00:40:48.302714 ==
7704 00:40:48.302797
7705 00:40:48.302878
7706 00:40:48.305636 TX Vref Scan disable
7707 00:40:48.308985 == TX Byte 0 ==
7708 00:40:48.312344 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7709 00:40:48.315764 == TX Byte 1 ==
7710 00:40:48.319086 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
7711 00:40:48.319181 DramC Write-DBI off
7712 00:40:48.319264
7713 00:40:48.322296 [DATLAT]
7714 00:40:48.322386 Freq=1600, CH0 RK0
7715 00:40:48.322468
7716 00:40:48.326058 DATLAT Default: 0xf
7717 00:40:48.326126 0, 0xFFFF, sum = 0
7718 00:40:48.329569 1, 0xFFFF, sum = 0
7719 00:40:48.329640 2, 0xFFFF, sum = 0
7720 00:40:48.332271 3, 0xFFFF, sum = 0
7721 00:40:48.332362 4, 0xFFFF, sum = 0
7722 00:40:48.336019 5, 0xFFFF, sum = 0
7723 00:40:48.336089 6, 0xFFFF, sum = 0
7724 00:40:48.339288 7, 0xFFFF, sum = 0
7725 00:40:48.339357 8, 0xFFFF, sum = 0
7726 00:40:48.342778 9, 0xFFFF, sum = 0
7727 00:40:48.345762 10, 0xFFFF, sum = 0
7728 00:40:48.345832 11, 0xFFFF, sum = 0
7729 00:40:48.348872 12, 0xFFFF, sum = 0
7730 00:40:48.348948 13, 0xFFFF, sum = 0
7731 00:40:48.352264 14, 0x0, sum = 1
7732 00:40:48.352332 15, 0x0, sum = 2
7733 00:40:48.355638 16, 0x0, sum = 3
7734 00:40:48.355734 17, 0x0, sum = 4
7735 00:40:48.355831 best_step = 15
7736 00:40:48.355912
7737 00:40:48.359127 ==
7738 00:40:48.362596 Dram Type= 6, Freq= 0, CH_0, rank 0
7739 00:40:48.365643 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7740 00:40:48.365715 ==
7741 00:40:48.365780 RX Vref Scan: 1
7742 00:40:48.365833
7743 00:40:48.369269 Set Vref Range= 24 -> 127
7744 00:40:48.369358
7745 00:40:48.372415 RX Vref 24 -> 127, step: 1
7746 00:40:48.372510
7747 00:40:48.375873 RX Delay 19 -> 252, step: 4
7748 00:40:48.375963
7749 00:40:48.379501 Set Vref, RX VrefLevel [Byte0]: 24
7750 00:40:48.382861 [Byte1]: 24
7751 00:40:48.382932
7752 00:40:48.386177 Set Vref, RX VrefLevel [Byte0]: 25
7753 00:40:48.389385 [Byte1]: 25
7754 00:40:48.389453
7755 00:40:48.392993 Set Vref, RX VrefLevel [Byte0]: 26
7756 00:40:48.396396 [Byte1]: 26
7757 00:40:48.396489
7758 00:40:48.399061 Set Vref, RX VrefLevel [Byte0]: 27
7759 00:40:48.402449 [Byte1]: 27
7760 00:40:48.406452
7761 00:40:48.406530 Set Vref, RX VrefLevel [Byte0]: 28
7762 00:40:48.409615 [Byte1]: 28
7763 00:40:48.413976
7764 00:40:48.414046 Set Vref, RX VrefLevel [Byte0]: 29
7765 00:40:48.417244 [Byte1]: 29
7766 00:40:48.421681
7767 00:40:48.421778 Set Vref, RX VrefLevel [Byte0]: 30
7768 00:40:48.425025 [Byte1]: 30
7769 00:40:48.429565
7770 00:40:48.429637 Set Vref, RX VrefLevel [Byte0]: 31
7771 00:40:48.432816 [Byte1]: 31
7772 00:40:48.436927
7773 00:40:48.436997 Set Vref, RX VrefLevel [Byte0]: 32
7774 00:40:48.440349 [Byte1]: 32
7775 00:40:48.444550
7776 00:40:48.444639 Set Vref, RX VrefLevel [Byte0]: 33
7777 00:40:48.447951 [Byte1]: 33
7778 00:40:48.452043
7779 00:40:48.452108 Set Vref, RX VrefLevel [Byte0]: 34
7780 00:40:48.455122 [Byte1]: 34
7781 00:40:48.459716
7782 00:40:48.459800 Set Vref, RX VrefLevel [Byte0]: 35
7783 00:40:48.463185 [Byte1]: 35
7784 00:40:48.467445
7785 00:40:48.467543 Set Vref, RX VrefLevel [Byte0]: 36
7786 00:40:48.470610 [Byte1]: 36
7787 00:40:48.474718
7788 00:40:48.474818 Set Vref, RX VrefLevel [Byte0]: 37
7789 00:40:48.478389 [Byte1]: 37
7790 00:40:48.482138
7791 00:40:48.482252 Set Vref, RX VrefLevel [Byte0]: 38
7792 00:40:48.485825 [Byte1]: 38
7793 00:40:48.489907
7794 00:40:48.490010 Set Vref, RX VrefLevel [Byte0]: 39
7795 00:40:48.493198 [Byte1]: 39
7796 00:40:48.497399
7797 00:40:48.497496 Set Vref, RX VrefLevel [Byte0]: 40
7798 00:40:48.500694 [Byte1]: 40
7799 00:40:48.504795
7800 00:40:48.504899 Set Vref, RX VrefLevel [Byte0]: 41
7801 00:40:48.508192 [Byte1]: 41
7802 00:40:48.512298
7803 00:40:48.512394 Set Vref, RX VrefLevel [Byte0]: 42
7804 00:40:48.515731 [Byte1]: 42
7805 00:40:48.520297
7806 00:40:48.520393 Set Vref, RX VrefLevel [Byte0]: 43
7807 00:40:48.523339 [Byte1]: 43
7808 00:40:48.527826
7809 00:40:48.527924 Set Vref, RX VrefLevel [Byte0]: 44
7810 00:40:48.530971 [Byte1]: 44
7811 00:40:48.535302
7812 00:40:48.535400 Set Vref, RX VrefLevel [Byte0]: 45
7813 00:40:48.538544 [Byte1]: 45
7814 00:40:48.542899
7815 00:40:48.543007 Set Vref, RX VrefLevel [Byte0]: 46
7816 00:40:48.546348 [Byte1]: 46
7817 00:40:48.550348
7818 00:40:48.550419 Set Vref, RX VrefLevel [Byte0]: 47
7819 00:40:48.553658 [Byte1]: 47
7820 00:40:48.558372
7821 00:40:48.558464 Set Vref, RX VrefLevel [Byte0]: 48
7822 00:40:48.561432 [Byte1]: 48
7823 00:40:48.565589
7824 00:40:48.565683 Set Vref, RX VrefLevel [Byte0]: 49
7825 00:40:48.568957 [Byte1]: 49
7826 00:40:48.573453
7827 00:40:48.573555 Set Vref, RX VrefLevel [Byte0]: 50
7828 00:40:48.576474 [Byte1]: 50
7829 00:40:48.580762
7830 00:40:48.580832 Set Vref, RX VrefLevel [Byte0]: 51
7831 00:40:48.584121 [Byte1]: 51
7832 00:40:48.588175
7833 00:40:48.588277 Set Vref, RX VrefLevel [Byte0]: 52
7834 00:40:48.591564 [Byte1]: 52
7835 00:40:48.596124
7836 00:40:48.596232 Set Vref, RX VrefLevel [Byte0]: 53
7837 00:40:48.599294 [Byte1]: 53
7838 00:40:48.603619
7839 00:40:48.603728 Set Vref, RX VrefLevel [Byte0]: 54
7840 00:40:48.606601 [Byte1]: 54
7841 00:40:48.610856
7842 00:40:48.610966 Set Vref, RX VrefLevel [Byte0]: 55
7843 00:40:48.614176 [Byte1]: 55
7844 00:40:48.618941
7845 00:40:48.619037 Set Vref, RX VrefLevel [Byte0]: 56
7846 00:40:48.621688 [Byte1]: 56
7847 00:40:48.626210
7848 00:40:48.626307 Set Vref, RX VrefLevel [Byte0]: 57
7849 00:40:48.629378 [Byte1]: 57
7850 00:40:48.633660
7851 00:40:48.633737 Set Vref, RX VrefLevel [Byte0]: 58
7852 00:40:48.636844 [Byte1]: 58
7853 00:40:48.641287
7854 00:40:48.641382 Set Vref, RX VrefLevel [Byte0]: 59
7855 00:40:48.644354 [Byte1]: 59
7856 00:40:48.649138
7857 00:40:48.649230 Set Vref, RX VrefLevel [Byte0]: 60
7858 00:40:48.652142 [Byte1]: 60
7859 00:40:48.656686
7860 00:40:48.656759 Set Vref, RX VrefLevel [Byte0]: 61
7861 00:40:48.660113 [Byte1]: 61
7862 00:40:48.664141
7863 00:40:48.664211 Set Vref, RX VrefLevel [Byte0]: 62
7864 00:40:48.667619 [Byte1]: 62
7865 00:40:48.671671
7866 00:40:48.671741 Set Vref, RX VrefLevel [Byte0]: 63
7867 00:40:48.674921 [Byte1]: 63
7868 00:40:48.679063
7869 00:40:48.679164 Set Vref, RX VrefLevel [Byte0]: 64
7870 00:40:48.682329 [Byte1]: 64
7871 00:40:48.687000
7872 00:40:48.687077 Set Vref, RX VrefLevel [Byte0]: 65
7873 00:40:48.690167 [Byte1]: 65
7874 00:40:48.694253
7875 00:40:48.694329 Set Vref, RX VrefLevel [Byte0]: 66
7876 00:40:48.697600 [Byte1]: 66
7877 00:40:48.702304
7878 00:40:48.702380 Set Vref, RX VrefLevel [Byte0]: 67
7879 00:40:48.705009 [Byte1]: 67
7880 00:40:48.709613
7881 00:40:48.709690 Set Vref, RX VrefLevel [Byte0]: 68
7882 00:40:48.712911 [Byte1]: 68
7883 00:40:48.717340
7884 00:40:48.717432 Set Vref, RX VrefLevel [Byte0]: 69
7885 00:40:48.720288 [Byte1]: 69
7886 00:40:48.724721
7887 00:40:48.724813 Set Vref, RX VrefLevel [Byte0]: 70
7888 00:40:48.728079 [Byte1]: 70
7889 00:40:48.732297
7890 00:40:48.732389 Set Vref, RX VrefLevel [Byte0]: 71
7891 00:40:48.735680 [Byte1]: 71
7892 00:40:48.740135
7893 00:40:48.740226 Set Vref, RX VrefLevel [Byte0]: 72
7894 00:40:48.743259 [Byte1]: 72
7895 00:40:48.747212
7896 00:40:48.747284 Set Vref, RX VrefLevel [Byte0]: 73
7897 00:40:48.750606 [Byte1]: 73
7898 00:40:48.755083
7899 00:40:48.755174 Set Vref, RX VrefLevel [Byte0]: 74
7900 00:40:48.758258 [Byte1]: 74
7901 00:40:48.762557
7902 00:40:48.762642 Set Vref, RX VrefLevel [Byte0]: 75
7903 00:40:48.765738 [Byte1]: 75
7904 00:40:48.770082
7905 00:40:48.770154 Final RX Vref Byte 0 = 57 to rank0
7906 00:40:48.773472 Final RX Vref Byte 1 = 58 to rank0
7907 00:40:48.776963 Final RX Vref Byte 0 = 57 to rank1
7908 00:40:48.780424 Final RX Vref Byte 1 = 58 to rank1==
7909 00:40:48.783707 Dram Type= 6, Freq= 0, CH_0, rank 0
7910 00:40:48.789956 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7911 00:40:48.790035 ==
7912 00:40:48.790112 DQS Delay:
7913 00:40:48.790257 DQS0 = 0, DQS1 = 0
7914 00:40:48.793430 DQM Delay:
7915 00:40:48.793538 DQM0 = 134, DQM1 = 127
7916 00:40:48.796756 DQ Delay:
7917 00:40:48.799817 DQ0 =134, DQ1 =138, DQ2 =134, DQ3 =132
7918 00:40:48.803348 DQ4 =134, DQ5 =124, DQ6 =138, DQ7 =138
7919 00:40:48.806779 DQ8 =116, DQ9 =118, DQ10 =128, DQ11 =120
7920 00:40:48.809826 DQ12 =130, DQ13 =132, DQ14 =138, DQ15 =134
7921 00:40:48.809919
7922 00:40:48.809977
7923 00:40:48.810031
7924 00:40:48.813124 [DramC_TX_OE_Calibration] TA2
7925 00:40:48.816340 Original DQ_B0 (3 6) =30, OEN = 27
7926 00:40:48.819826 Original DQ_B1 (3 6) =30, OEN = 27
7927 00:40:48.823007 24, 0x0, End_B0=24 End_B1=24
7928 00:40:48.823086 25, 0x0, End_B0=25 End_B1=25
7929 00:40:48.826767 26, 0x0, End_B0=26 End_B1=26
7930 00:40:48.829770 27, 0x0, End_B0=27 End_B1=27
7931 00:40:48.833005 28, 0x0, End_B0=28 End_B1=28
7932 00:40:48.833086 29, 0x0, End_B0=29 End_B1=29
7933 00:40:48.836373 30, 0x0, End_B0=30 End_B1=30
7934 00:40:48.839770 31, 0x4141, End_B0=30 End_B1=30
7935 00:40:48.842983 Byte0 end_step=30 best_step=27
7936 00:40:48.846323 Byte1 end_step=30 best_step=27
7937 00:40:48.849950 Byte0 TX OE(2T, 0.5T) = (3, 3)
7938 00:40:48.850031 Byte1 TX OE(2T, 0.5T) = (3, 3)
7939 00:40:48.853151
7940 00:40:48.853251
7941 00:40:48.859970 [DQSOSCAuto] RK0, (LSB)MR18= 0x2824, (MSB)MR19= 0x303, tDQSOscB0 = 391 ps tDQSOscB1 = 389 ps
7942 00:40:48.863333 CH0 RK0: MR19=303, MR18=2824
7943 00:40:48.869418 CH0_RK0: MR19=0x303, MR18=0x2824, DQSOSC=389, MR23=63, INC=24, DEC=16
7944 00:40:48.869514
7945 00:40:48.873396 ----->DramcWriteLeveling(PI) begin...
7946 00:40:48.873499 ==
7947 00:40:48.876548 Dram Type= 6, Freq= 0, CH_0, rank 1
7948 00:40:48.879488 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7949 00:40:48.879560 ==
7950 00:40:48.883160 Write leveling (Byte 0): 37 => 37
7951 00:40:48.886473 Write leveling (Byte 1): 27 => 27
7952 00:40:48.889690 DramcWriteLeveling(PI) end<-----
7953 00:40:48.889792
7954 00:40:48.889882 ==
7955 00:40:48.893127 Dram Type= 6, Freq= 0, CH_0, rank 1
7956 00:40:48.896558 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7957 00:40:48.896649 ==
7958 00:40:48.899320 [Gating] SW mode calibration
7959 00:40:48.905956 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7960 00:40:48.913099 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7961 00:40:48.916271 1 4 0 | B1->B0 | 2323 2424 | 0 1 | (0 0) (0 0)
7962 00:40:48.919694 1 4 4 | B1->B0 | 2323 2424 | 0 1 | (0 0) (0 0)
7963 00:40:48.926125 1 4 8 | B1->B0 | 2323 2423 | 0 1 | (0 0) (0 0)
7964 00:40:48.929693 1 4 12 | B1->B0 | 2323 2e2d | 0 1 | (0 0) (1 1)
7965 00:40:48.932918 1 4 16 | B1->B0 | 3434 3535 | 0 0 | (0 0) (0 0)
7966 00:40:48.939586 1 4 20 | B1->B0 | 3434 3837 | 1 1 | (1 1) (0 0)
7967 00:40:48.942989 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7968 00:40:48.946179 1 4 28 | B1->B0 | 3434 3938 | 1 1 | (1 1) (1 1)
7969 00:40:48.952692 1 5 0 | B1->B0 | 3434 3635 | 1 1 | (1 1) (1 1)
7970 00:40:48.956061 1 5 4 | B1->B0 | 3434 3939 | 1 0 | (1 1) (1 1)
7971 00:40:48.959675 1 5 8 | B1->B0 | 3434 3838 | 1 1 | (1 1) (1 1)
7972 00:40:48.966277 1 5 12 | B1->B0 | 3434 3232 | 1 0 | (1 0) (1 0)
7973 00:40:48.968996 1 5 16 | B1->B0 | 2e2e 2727 | 0 0 | (0 0) (0 0)
7974 00:40:48.972296 1 5 20 | B1->B0 | 2323 302f | 0 1 | (0 0) (0 0)
7975 00:40:48.979142 1 5 24 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
7976 00:40:48.982229 1 5 28 | B1->B0 | 2323 2c2b | 0 1 | (0 0) (0 0)
7977 00:40:48.986066 1 6 0 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
7978 00:40:48.992379 1 6 4 | B1->B0 | 2323 2929 | 0 1 | (0 0) (0 0)
7979 00:40:48.995508 1 6 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
7980 00:40:48.998868 1 6 12 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
7981 00:40:49.005714 1 6 16 | B1->B0 | 3737 4645 | 0 1 | (0 0) (0 0)
7982 00:40:49.009198 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7983 00:40:49.012567 1 6 24 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
7984 00:40:49.018900 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7985 00:40:49.022312 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7986 00:40:49.025687 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7987 00:40:49.032202 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7988 00:40:49.035757 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7989 00:40:49.039076 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7990 00:40:49.045549 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7991 00:40:49.048576 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7992 00:40:49.052354 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7993 00:40:49.058470 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7994 00:40:49.061860 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7995 00:40:49.065194 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7996 00:40:49.069027 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7997 00:40:49.075149 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7998 00:40:49.079103 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7999 00:40:49.081757 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8000 00:40:49.088802 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8001 00:40:49.091671 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8002 00:40:49.095597 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8003 00:40:49.101999 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8004 00:40:49.105272 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8005 00:40:49.108539 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8006 00:40:49.112047 Total UI for P1: 0, mck2ui 16
8007 00:40:49.115404 best dqsien dly found for B0: ( 1, 9, 12)
8008 00:40:49.118753 Total UI for P1: 0, mck2ui 16
8009 00:40:49.122158 best dqsien dly found for B1: ( 1, 9, 12)
8010 00:40:49.125343 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8011 00:40:49.128772 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8012 00:40:49.128866
8013 00:40:49.135457 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8014 00:40:49.138705 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8015 00:40:49.142144 [Gating] SW calibration Done
8016 00:40:49.142239 ==
8017 00:40:49.145544 Dram Type= 6, Freq= 0, CH_0, rank 1
8018 00:40:49.148939 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8019 00:40:49.149031 ==
8020 00:40:49.149116 RX Vref Scan: 0
8021 00:40:49.149200
8022 00:40:49.152183 RX Vref 0 -> 0, step: 1
8023 00:40:49.152274
8024 00:40:49.155154 RX Delay 0 -> 252, step: 8
8025 00:40:49.158262 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8026 00:40:49.161985 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8027 00:40:49.165263 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8028 00:40:49.171616 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8029 00:40:49.175299 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8030 00:40:49.178473 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8031 00:40:49.181843 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
8032 00:40:49.185318 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8033 00:40:49.192103 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8034 00:40:49.195366 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8035 00:40:49.198602 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8036 00:40:49.201615 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8037 00:40:49.205285 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8038 00:40:49.211635 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8039 00:40:49.215269 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8040 00:40:49.218668 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8041 00:40:49.218775 ==
8042 00:40:49.222049 Dram Type= 6, Freq= 0, CH_0, rank 1
8043 00:40:49.225445 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8044 00:40:49.225542 ==
8045 00:40:49.228726 DQS Delay:
8046 00:40:49.228817 DQS0 = 0, DQS1 = 0
8047 00:40:49.231951 DQM Delay:
8048 00:40:49.232050 DQM0 = 136, DQM1 = 128
8049 00:40:49.235146 DQ Delay:
8050 00:40:49.238510 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
8051 00:40:49.241773 DQ4 =139, DQ5 =127, DQ6 =139, DQ7 =143
8052 00:40:49.245082 DQ8 =119, DQ9 =119, DQ10 =127, DQ11 =119
8053 00:40:49.248479 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8054 00:40:49.248571
8055 00:40:49.248660
8056 00:40:49.248746 ==
8057 00:40:49.251831 Dram Type= 6, Freq= 0, CH_0, rank 1
8058 00:40:49.255249 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8059 00:40:49.255340 ==
8060 00:40:49.255422
8061 00:40:49.255512
8062 00:40:49.258808 TX Vref Scan disable
8063 00:40:49.262049 == TX Byte 0 ==
8064 00:40:49.265375 Update DQ dly =994 (3 ,6, 34) DQ OEN =(3 ,3)
8065 00:40:49.268425 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
8066 00:40:49.271692 == TX Byte 1 ==
8067 00:40:49.274764 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8068 00:40:49.278671 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8069 00:40:49.278751 ==
8070 00:40:49.281898 Dram Type= 6, Freq= 0, CH_0, rank 1
8071 00:40:49.288366 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8072 00:40:49.288467 ==
8073 00:40:49.302007
8074 00:40:49.305400 TX Vref early break, caculate TX vref
8075 00:40:49.308654 TX Vref=16, minBit 1, minWin=23, winSum=386
8076 00:40:49.312029 TX Vref=18, minBit 1, minWin=23, winSum=396
8077 00:40:49.315925 TX Vref=20, minBit 1, minWin=24, winSum=405
8078 00:40:49.319095 TX Vref=22, minBit 4, minWin=24, winSum=413
8079 00:40:49.322768 TX Vref=24, minBit 1, minWin=25, winSum=420
8080 00:40:49.325760 TX Vref=26, minBit 3, minWin=24, winSum=422
8081 00:40:49.332137 TX Vref=28, minBit 1, minWin=25, winSum=421
8082 00:40:49.335521 TX Vref=30, minBit 2, minWin=25, winSum=415
8083 00:40:49.338798 TX Vref=32, minBit 0, minWin=24, winSum=409
8084 00:40:49.342038 TX Vref=34, minBit 0, minWin=24, winSum=403
8085 00:40:49.345681 TX Vref=36, minBit 0, minWin=24, winSum=393
8086 00:40:49.352288 [TxChooseVref] Worse bit 1, Min win 25, Win sum 421, Final Vref 28
8087 00:40:49.352405
8088 00:40:49.355846 Final TX Range 0 Vref 28
8089 00:40:49.355938
8090 00:40:49.356023 ==
8091 00:40:49.358545 Dram Type= 6, Freq= 0, CH_0, rank 1
8092 00:40:49.361926 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8093 00:40:49.362023 ==
8094 00:40:49.362106
8095 00:40:49.362193
8096 00:40:49.365379 TX Vref Scan disable
8097 00:40:49.372367 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8098 00:40:49.372462 == TX Byte 0 ==
8099 00:40:49.375080 u2DelayCellOfst[0]=13 cells (4 PI)
8100 00:40:49.379063 u2DelayCellOfst[1]=17 cells (5 PI)
8101 00:40:49.382263 u2DelayCellOfst[2]=10 cells (3 PI)
8102 00:40:49.385347 u2DelayCellOfst[3]=13 cells (4 PI)
8103 00:40:49.388544 u2DelayCellOfst[4]=10 cells (3 PI)
8104 00:40:49.392057 u2DelayCellOfst[5]=0 cells (0 PI)
8105 00:40:49.395238 u2DelayCellOfst[6]=17 cells (5 PI)
8106 00:40:49.398447 u2DelayCellOfst[7]=17 cells (5 PI)
8107 00:40:49.401764 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8108 00:40:49.405162 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8109 00:40:49.408526 == TX Byte 1 ==
8110 00:40:49.411748 u2DelayCellOfst[8]=0 cells (0 PI)
8111 00:40:49.415085 u2DelayCellOfst[9]=0 cells (0 PI)
8112 00:40:49.415162 u2DelayCellOfst[10]=6 cells (2 PI)
8113 00:40:49.418511 u2DelayCellOfst[11]=3 cells (1 PI)
8114 00:40:49.421798 u2DelayCellOfst[12]=10 cells (3 PI)
8115 00:40:49.425112 u2DelayCellOfst[13]=10 cells (3 PI)
8116 00:40:49.428481 u2DelayCellOfst[14]=13 cells (4 PI)
8117 00:40:49.431604 u2DelayCellOfst[15]=10 cells (3 PI)
8118 00:40:49.438383 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8119 00:40:49.441757 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8120 00:40:49.441861 DramC Write-DBI on
8121 00:40:49.441950 ==
8122 00:40:49.445019 Dram Type= 6, Freq= 0, CH_0, rank 1
8123 00:40:49.451606 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8124 00:40:49.451702 ==
8125 00:40:49.451790
8126 00:40:49.451876
8127 00:40:49.451959 TX Vref Scan disable
8128 00:40:49.456050 == TX Byte 0 ==
8129 00:40:49.459285 Update DQM dly =738 (2 ,6, 34) DQM OEN =(3 ,3)
8130 00:40:49.462635 == TX Byte 1 ==
8131 00:40:49.466023 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8132 00:40:49.469311 DramC Write-DBI off
8133 00:40:49.469405
8134 00:40:49.469491 [DATLAT]
8135 00:40:49.469579 Freq=1600, CH0 RK1
8136 00:40:49.469664
8137 00:40:49.472594 DATLAT Default: 0xf
8138 00:40:49.472685 0, 0xFFFF, sum = 0
8139 00:40:49.475905 1, 0xFFFF, sum = 0
8140 00:40:49.476002 2, 0xFFFF, sum = 0
8141 00:40:49.479230 3, 0xFFFF, sum = 0
8142 00:40:49.482552 4, 0xFFFF, sum = 0
8143 00:40:49.482654 5, 0xFFFF, sum = 0
8144 00:40:49.486021 6, 0xFFFF, sum = 0
8145 00:40:49.486120 7, 0xFFFF, sum = 0
8146 00:40:49.488673 8, 0xFFFF, sum = 0
8147 00:40:49.488764 9, 0xFFFF, sum = 0
8148 00:40:49.492068 10, 0xFFFF, sum = 0
8149 00:40:49.492161 11, 0xFFFF, sum = 0
8150 00:40:49.495947 12, 0xFFFF, sum = 0
8151 00:40:49.496041 13, 0xFFFF, sum = 0
8152 00:40:49.498980 14, 0x0, sum = 1
8153 00:40:49.499073 15, 0x0, sum = 2
8154 00:40:49.502090 16, 0x0, sum = 3
8155 00:40:49.502175 17, 0x0, sum = 4
8156 00:40:49.505763 best_step = 15
8157 00:40:49.505856
8158 00:40:49.505940 ==
8159 00:40:49.508765 Dram Type= 6, Freq= 0, CH_0, rank 1
8160 00:40:49.512263 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8161 00:40:49.512363 ==
8162 00:40:49.515614 RX Vref Scan: 0
8163 00:40:49.515707
8164 00:40:49.515793 RX Vref 0 -> 0, step: 1
8165 00:40:49.515874
8166 00:40:49.518880 RX Delay 19 -> 252, step: 4
8167 00:40:49.522224 iDelay=191, Bit 0, Center 134 (83 ~ 186) 104
8168 00:40:49.529194 iDelay=191, Bit 1, Center 138 (91 ~ 186) 96
8169 00:40:49.532538 iDelay=191, Bit 2, Center 130 (79 ~ 182) 104
8170 00:40:49.535916 iDelay=191, Bit 3, Center 134 (83 ~ 186) 104
8171 00:40:49.538732 iDelay=191, Bit 4, Center 134 (83 ~ 186) 104
8172 00:40:49.542622 iDelay=191, Bit 5, Center 124 (71 ~ 178) 108
8173 00:40:49.548824 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8174 00:40:49.552497 iDelay=191, Bit 7, Center 140 (91 ~ 190) 100
8175 00:40:49.555773 iDelay=191, Bit 8, Center 118 (67 ~ 170) 104
8176 00:40:49.558933 iDelay=191, Bit 9, Center 118 (67 ~ 170) 104
8177 00:40:49.562125 iDelay=191, Bit 10, Center 128 (75 ~ 182) 108
8178 00:40:49.568760 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8179 00:40:49.572168 iDelay=191, Bit 12, Center 132 (83 ~ 182) 100
8180 00:40:49.575321 iDelay=191, Bit 13, Center 134 (83 ~ 186) 104
8181 00:40:49.578642 iDelay=191, Bit 14, Center 136 (83 ~ 190) 108
8182 00:40:49.581956 iDelay=191, Bit 15, Center 134 (83 ~ 186) 104
8183 00:40:49.585282 ==
8184 00:40:49.585383 Dram Type= 6, Freq= 0, CH_0, rank 1
8185 00:40:49.591974 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8186 00:40:49.592069 ==
8187 00:40:49.592160 DQS Delay:
8188 00:40:49.595274 DQS0 = 0, DQS1 = 0
8189 00:40:49.595364 DQM Delay:
8190 00:40:49.598662 DQM0 = 134, DQM1 = 127
8191 00:40:49.598754 DQ Delay:
8192 00:40:49.601995 DQ0 =134, DQ1 =138, DQ2 =130, DQ3 =134
8193 00:40:49.605222 DQ4 =134, DQ5 =124, DQ6 =140, DQ7 =140
8194 00:40:49.608617 DQ8 =118, DQ9 =118, DQ10 =128, DQ11 =118
8195 00:40:49.611854 DQ12 =132, DQ13 =134, DQ14 =136, DQ15 =134
8196 00:40:49.611947
8197 00:40:49.612039
8198 00:40:49.612122
8199 00:40:49.615124 [DramC_TX_OE_Calibration] TA2
8200 00:40:49.618749 Original DQ_B0 (3 6) =30, OEN = 27
8201 00:40:49.621757 Original DQ_B1 (3 6) =30, OEN = 27
8202 00:40:49.624923 24, 0x0, End_B0=24 End_B1=24
8203 00:40:49.628318 25, 0x0, End_B0=25 End_B1=25
8204 00:40:49.628420 26, 0x0, End_B0=26 End_B1=26
8205 00:40:49.631651 27, 0x0, End_B0=27 End_B1=27
8206 00:40:49.635030 28, 0x0, End_B0=28 End_B1=28
8207 00:40:49.638379 29, 0x0, End_B0=29 End_B1=29
8208 00:40:49.641771 30, 0x0, End_B0=30 End_B1=30
8209 00:40:49.641845 31, 0x4141, End_B0=30 End_B1=30
8210 00:40:49.645187 Byte0 end_step=30 best_step=27
8211 00:40:49.648607 Byte1 end_step=30 best_step=27
8212 00:40:49.651260 Byte0 TX OE(2T, 0.5T) = (3, 3)
8213 00:40:49.655076 Byte1 TX OE(2T, 0.5T) = (3, 3)
8214 00:40:49.655167
8215 00:40:49.655257
8216 00:40:49.661461 [DQSOSCAuto] RK1, (LSB)MR18= 0x240c, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 391 ps
8217 00:40:49.664501 CH0 RK1: MR19=303, MR18=240C
8218 00:40:49.671423 CH0_RK1: MR19=0x303, MR18=0x240C, DQSOSC=391, MR23=63, INC=24, DEC=16
8219 00:40:49.674536 [RxdqsGatingPostProcess] freq 1600
8220 00:40:49.681657 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8221 00:40:49.681732 best DQS0 dly(2T, 0.5T) = (1, 1)
8222 00:40:49.684797 best DQS1 dly(2T, 0.5T) = (1, 1)
8223 00:40:49.688181 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8224 00:40:49.691401 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8225 00:40:49.694701 best DQS0 dly(2T, 0.5T) = (1, 1)
8226 00:40:49.698170 best DQS1 dly(2T, 0.5T) = (1, 1)
8227 00:40:49.701655 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8228 00:40:49.704913 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8229 00:40:49.708403 Pre-setting of DQS Precalculation
8230 00:40:49.711557 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8231 00:40:49.711652 ==
8232 00:40:49.714978 Dram Type= 6, Freq= 0, CH_1, rank 0
8233 00:40:49.721649 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8234 00:40:49.721751 ==
8235 00:40:49.724984 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8236 00:40:49.731088 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8237 00:40:49.734733 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8238 00:40:49.741342 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8239 00:40:49.748715 [CA 0] Center 42 (13~71) winsize 59
8240 00:40:49.752055 [CA 1] Center 41 (12~71) winsize 60
8241 00:40:49.755493 [CA 2] Center 38 (9~68) winsize 60
8242 00:40:49.758721 [CA 3] Center 37 (8~67) winsize 60
8243 00:40:49.761952 [CA 4] Center 37 (8~67) winsize 60
8244 00:40:49.765292 [CA 5] Center 37 (8~66) winsize 59
8245 00:40:49.765357
8246 00:40:49.768626 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8247 00:40:49.768727
8248 00:40:49.772345 [CATrainingPosCal] consider 1 rank data
8249 00:40:49.775115 u2DelayCellTimex100 = 285/100 ps
8250 00:40:49.779016 CA0 delay=42 (13~71),Diff = 5 PI (17 cell)
8251 00:40:49.785101 CA1 delay=41 (12~71),Diff = 4 PI (13 cell)
8252 00:40:49.788867 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8253 00:40:49.791860 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8254 00:40:49.795419 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
8255 00:40:49.798644 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8256 00:40:49.798724
8257 00:40:49.802033 CA PerBit enable=1, Macro0, CA PI delay=37
8258 00:40:49.802112
8259 00:40:49.805446 [CBTSetCACLKResult] CA Dly = 37
8260 00:40:49.808790 CS Dly: 10 (0~41)
8261 00:40:49.812330 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8262 00:40:49.815505 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8263 00:40:49.815607 ==
8264 00:40:49.818611 Dram Type= 6, Freq= 0, CH_1, rank 1
8265 00:40:49.822172 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8266 00:40:49.822266 ==
8267 00:40:49.828880 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8268 00:40:49.831682 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8269 00:40:49.838673 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8270 00:40:49.841749 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8271 00:40:49.852120 [CA 0] Center 42 (12~72) winsize 61
8272 00:40:49.855476 [CA 1] Center 42 (13~72) winsize 60
8273 00:40:49.858763 [CA 2] Center 38 (9~68) winsize 60
8274 00:40:49.861471 [CA 3] Center 38 (8~68) winsize 61
8275 00:40:49.864880 [CA 4] Center 38 (9~68) winsize 60
8276 00:40:49.868081 [CA 5] Center 37 (7~67) winsize 61
8277 00:40:49.868148
8278 00:40:49.872063 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8279 00:40:49.872130
8280 00:40:49.875374 [CATrainingPosCal] consider 2 rank data
8281 00:40:49.878408 u2DelayCellTimex100 = 285/100 ps
8282 00:40:49.884928 CA0 delay=42 (13~71),Diff = 5 PI (17 cell)
8283 00:40:49.888282 CA1 delay=42 (13~71),Diff = 5 PI (17 cell)
8284 00:40:49.891498 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8285 00:40:49.894862 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8286 00:40:49.898740 CA4 delay=38 (9~67),Diff = 1 PI (3 cell)
8287 00:40:49.901655 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8288 00:40:49.901734
8289 00:40:49.905334 CA PerBit enable=1, Macro0, CA PI delay=37
8290 00:40:49.905412
8291 00:40:49.908178 [CBTSetCACLKResult] CA Dly = 37
8292 00:40:49.912060 CS Dly: 12 (0~45)
8293 00:40:49.914862 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8294 00:40:49.918337 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8295 00:40:49.918414
8296 00:40:49.921607 ----->DramcWriteLeveling(PI) begin...
8297 00:40:49.921711 ==
8298 00:40:49.924833 Dram Type= 6, Freq= 0, CH_1, rank 0
8299 00:40:49.928245 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8300 00:40:49.931578 ==
8301 00:40:49.935061 Write leveling (Byte 0): 25 => 25
8302 00:40:49.935151 Write leveling (Byte 1): 26 => 26
8303 00:40:49.938442 DramcWriteLeveling(PI) end<-----
8304 00:40:49.938551
8305 00:40:49.938613 ==
8306 00:40:49.941742 Dram Type= 6, Freq= 0, CH_1, rank 0
8307 00:40:49.948458 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8308 00:40:49.948565 ==
8309 00:40:49.951497 [Gating] SW mode calibration
8310 00:40:49.958188 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8311 00:40:49.961698 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8312 00:40:49.968177 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8313 00:40:49.971474 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8314 00:40:49.974798 1 4 8 | B1->B0 | 2323 2f2e | 0 1 | (0 0) (0 0)
8315 00:40:49.981290 1 4 12 | B1->B0 | 2e2e 3434 | 1 1 | (1 1) (1 1)
8316 00:40:49.985107 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8317 00:40:49.988248 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8318 00:40:49.991631 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8319 00:40:49.998190 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8320 00:40:50.001395 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8321 00:40:50.004717 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8322 00:40:50.011391 1 5 8 | B1->B0 | 3434 3030 | 1 1 | (1 0) (1 0)
8323 00:40:50.014595 1 5 12 | B1->B0 | 2a2a 2323 | 0 0 | (0 1) (1 0)
8324 00:40:50.018158 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8325 00:40:50.024629 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8326 00:40:50.027739 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8327 00:40:50.031649 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8328 00:40:50.038332 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8329 00:40:50.041086 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8330 00:40:50.044477 1 6 8 | B1->B0 | 2424 3939 | 0 0 | (0 0) (1 1)
8331 00:40:50.051286 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8332 00:40:50.054648 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8333 00:40:50.057932 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8334 00:40:50.064590 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8335 00:40:50.067773 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8336 00:40:50.071000 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8337 00:40:50.078220 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8338 00:40:50.080880 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8339 00:40:50.084749 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8340 00:40:50.091335 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8341 00:40:50.094498 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8342 00:40:50.097950 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8343 00:40:50.104438 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8344 00:40:50.107769 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8345 00:40:50.111016 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8346 00:40:50.117844 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8347 00:40:50.121177 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8348 00:40:50.124253 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8349 00:40:50.127846 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8350 00:40:50.134155 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8351 00:40:50.138030 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8352 00:40:50.141155 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8353 00:40:50.147712 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8354 00:40:50.151035 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8355 00:40:50.154391 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8356 00:40:50.160925 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8357 00:40:50.164246 Total UI for P1: 0, mck2ui 16
8358 00:40:50.167692 best dqsien dly found for B0: ( 1, 9, 10)
8359 00:40:50.167773 Total UI for P1: 0, mck2ui 16
8360 00:40:50.174535 best dqsien dly found for B1: ( 1, 9, 10)
8361 00:40:50.177799 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8362 00:40:50.181085 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8363 00:40:50.181164
8364 00:40:50.184170 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8365 00:40:50.187660 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8366 00:40:50.191323 [Gating] SW calibration Done
8367 00:40:50.191399 ==
8368 00:40:50.194537 Dram Type= 6, Freq= 0, CH_1, rank 0
8369 00:40:50.197518 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8370 00:40:50.197604 ==
8371 00:40:50.201230 RX Vref Scan: 0
8372 00:40:50.201305
8373 00:40:50.201364 RX Vref 0 -> 0, step: 1
8374 00:40:50.201420
8375 00:40:50.204299 RX Delay 0 -> 252, step: 8
8376 00:40:50.207450 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8377 00:40:50.214248 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8378 00:40:50.217395 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8379 00:40:50.220831 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8380 00:40:50.224164 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8381 00:40:50.227690 iDelay=200, Bit 5, Center 151 (104 ~ 199) 96
8382 00:40:50.234277 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8383 00:40:50.237297 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8384 00:40:50.241258 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
8385 00:40:50.244499 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8386 00:40:50.247656 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8387 00:40:50.254021 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8388 00:40:50.257349 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8389 00:40:50.260810 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8390 00:40:50.264056 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8391 00:40:50.267378 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8392 00:40:50.270685 ==
8393 00:40:50.270758 Dram Type= 6, Freq= 0, CH_1, rank 0
8394 00:40:50.277386 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8395 00:40:50.277460 ==
8396 00:40:50.277526 DQS Delay:
8397 00:40:50.280717 DQS0 = 0, DQS1 = 0
8398 00:40:50.280789 DQM Delay:
8399 00:40:50.284087 DQM0 = 136, DQM1 = 132
8400 00:40:50.284182 DQ Delay:
8401 00:40:50.287406 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8402 00:40:50.290642 DQ4 =131, DQ5 =151, DQ6 =143, DQ7 =135
8403 00:40:50.293728 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =127
8404 00:40:50.297375 DQ12 =139, DQ13 =143, DQ14 =139, DQ15 =139
8405 00:40:50.297449
8406 00:40:50.297507
8407 00:40:50.297567 ==
8408 00:40:50.300483 Dram Type= 6, Freq= 0, CH_1, rank 0
8409 00:40:50.307153 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8410 00:40:50.307227 ==
8411 00:40:50.307295
8412 00:40:50.307352
8413 00:40:50.307404 TX Vref Scan disable
8414 00:40:50.310654 == TX Byte 0 ==
8415 00:40:50.313773 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8416 00:40:50.320439 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8417 00:40:50.320550 == TX Byte 1 ==
8418 00:40:50.323962 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8419 00:40:50.330485 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8420 00:40:50.330559 ==
8421 00:40:50.333969 Dram Type= 6, Freq= 0, CH_1, rank 0
8422 00:40:50.337341 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8423 00:40:50.337413 ==
8424 00:40:50.349194
8425 00:40:50.352507 TX Vref early break, caculate TX vref
8426 00:40:50.355826 TX Vref=16, minBit 0, minWin=23, winSum=382
8427 00:40:50.359165 TX Vref=18, minBit 1, minWin=23, winSum=387
8428 00:40:50.362297 TX Vref=20, minBit 0, minWin=24, winSum=402
8429 00:40:50.365776 TX Vref=22, minBit 3, minWin=24, winSum=408
8430 00:40:50.368933 TX Vref=24, minBit 1, minWin=25, winSum=419
8431 00:40:50.375647 TX Vref=26, minBit 1, minWin=25, winSum=428
8432 00:40:50.379122 TX Vref=28, minBit 0, minWin=26, winSum=430
8433 00:40:50.382476 TX Vref=30, minBit 0, minWin=25, winSum=423
8434 00:40:50.385886 TX Vref=32, minBit 6, minWin=24, winSum=416
8435 00:40:50.389271 TX Vref=34, minBit 0, minWin=24, winSum=405
8436 00:40:50.396025 [TxChooseVref] Worse bit 0, Min win 26, Win sum 430, Final Vref 28
8437 00:40:50.396129
8438 00:40:50.398754 Final TX Range 0 Vref 28
8439 00:40:50.398818
8440 00:40:50.398883 ==
8441 00:40:50.402014 Dram Type= 6, Freq= 0, CH_1, rank 0
8442 00:40:50.405765 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8443 00:40:50.405841 ==
8444 00:40:50.405902
8445 00:40:50.405955
8446 00:40:50.408814 TX Vref Scan disable
8447 00:40:50.415712 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8448 00:40:50.415792 == TX Byte 0 ==
8449 00:40:50.419001 u2DelayCellOfst[0]=17 cells (5 PI)
8450 00:40:50.422241 u2DelayCellOfst[1]=10 cells (3 PI)
8451 00:40:50.425784 u2DelayCellOfst[2]=0 cells (0 PI)
8452 00:40:50.428895 u2DelayCellOfst[3]=6 cells (2 PI)
8453 00:40:50.432153 u2DelayCellOfst[4]=10 cells (3 PI)
8454 00:40:50.435304 u2DelayCellOfst[5]=17 cells (5 PI)
8455 00:40:50.438828 u2DelayCellOfst[6]=17 cells (5 PI)
8456 00:40:50.438899 u2DelayCellOfst[7]=6 cells (2 PI)
8457 00:40:50.445467 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8458 00:40:50.448724 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8459 00:40:50.448796 == TX Byte 1 ==
8460 00:40:50.452464 u2DelayCellOfst[8]=0 cells (0 PI)
8461 00:40:50.455607 u2DelayCellOfst[9]=3 cells (1 PI)
8462 00:40:50.458724 u2DelayCellOfst[10]=13 cells (4 PI)
8463 00:40:50.462075 u2DelayCellOfst[11]=3 cells (1 PI)
8464 00:40:50.465268 u2DelayCellOfst[12]=13 cells (4 PI)
8465 00:40:50.468547 u2DelayCellOfst[13]=17 cells (5 PI)
8466 00:40:50.471693 u2DelayCellOfst[14]=20 cells (6 PI)
8467 00:40:50.475626 u2DelayCellOfst[15]=17 cells (5 PI)
8468 00:40:50.478952 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8469 00:40:50.485091 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8470 00:40:50.485191 DramC Write-DBI on
8471 00:40:50.485263 ==
8472 00:40:50.488531 Dram Type= 6, Freq= 0, CH_1, rank 0
8473 00:40:50.491924 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8474 00:40:50.495236 ==
8475 00:40:50.495314
8476 00:40:50.495374
8477 00:40:50.495430 TX Vref Scan disable
8478 00:40:50.498713 == TX Byte 0 ==
8479 00:40:50.502038 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8480 00:40:50.505445 == TX Byte 1 ==
8481 00:40:50.508276 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8482 00:40:50.511624 DramC Write-DBI off
8483 00:40:50.511697
8484 00:40:50.511759 [DATLAT]
8485 00:40:50.511815 Freq=1600, CH1 RK0
8486 00:40:50.511875
8487 00:40:50.515340 DATLAT Default: 0xf
8488 00:40:50.515411 0, 0xFFFF, sum = 0
8489 00:40:50.518097 1, 0xFFFF, sum = 0
8490 00:40:50.521518 2, 0xFFFF, sum = 0
8491 00:40:50.521607 3, 0xFFFF, sum = 0
8492 00:40:50.524958 4, 0xFFFF, sum = 0
8493 00:40:50.525038 5, 0xFFFF, sum = 0
8494 00:40:50.528409 6, 0xFFFF, sum = 0
8495 00:40:50.528487 7, 0xFFFF, sum = 0
8496 00:40:50.531747 8, 0xFFFF, sum = 0
8497 00:40:50.531817 9, 0xFFFF, sum = 0
8498 00:40:50.534880 10, 0xFFFF, sum = 0
8499 00:40:50.534961 11, 0xFFFF, sum = 0
8500 00:40:50.538148 12, 0xFFFF, sum = 0
8501 00:40:50.538220 13, 0xFFFF, sum = 0
8502 00:40:50.541305 14, 0x0, sum = 1
8503 00:40:50.541386 15, 0x0, sum = 2
8504 00:40:50.544638 16, 0x0, sum = 3
8505 00:40:50.544742 17, 0x0, sum = 4
8506 00:40:50.547951 best_step = 15
8507 00:40:50.548021
8508 00:40:50.548077 ==
8509 00:40:50.551751 Dram Type= 6, Freq= 0, CH_1, rank 0
8510 00:40:50.554574 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8511 00:40:50.554644 ==
8512 00:40:50.558337 RX Vref Scan: 1
8513 00:40:50.558408
8514 00:40:50.558465 Set Vref Range= 24 -> 127
8515 00:40:50.558530
8516 00:40:50.561335 RX Vref 24 -> 127, step: 1
8517 00:40:50.561405
8518 00:40:50.564955 RX Delay 27 -> 252, step: 4
8519 00:40:50.565030
8520 00:40:50.568080 Set Vref, RX VrefLevel [Byte0]: 24
8521 00:40:50.571073 [Byte1]: 24
8522 00:40:50.571146
8523 00:40:50.575068 Set Vref, RX VrefLevel [Byte0]: 25
8524 00:40:50.578376 [Byte1]: 25
8525 00:40:50.578446
8526 00:40:50.581536 Set Vref, RX VrefLevel [Byte0]: 26
8527 00:40:50.584594 [Byte1]: 26
8528 00:40:50.589062
8529 00:40:50.589143 Set Vref, RX VrefLevel [Byte0]: 27
8530 00:40:50.591772 [Byte1]: 27
8531 00:40:50.596492
8532 00:40:50.596562 Set Vref, RX VrefLevel [Byte0]: 28
8533 00:40:50.599275 [Byte1]: 28
8534 00:40:50.604141
8535 00:40:50.604218 Set Vref, RX VrefLevel [Byte0]: 29
8536 00:40:50.606913 [Byte1]: 29
8537 00:40:50.611067
8538 00:40:50.611136 Set Vref, RX VrefLevel [Byte0]: 30
8539 00:40:50.614429 [Byte1]: 30
8540 00:40:50.618659
8541 00:40:50.618733 Set Vref, RX VrefLevel [Byte0]: 31
8542 00:40:50.621834 [Byte1]: 31
8543 00:40:50.626197
8544 00:40:50.626266 Set Vref, RX VrefLevel [Byte0]: 32
8545 00:40:50.629795 [Byte1]: 32
8546 00:40:50.633954
8547 00:40:50.634030 Set Vref, RX VrefLevel [Byte0]: 33
8548 00:40:50.637296 [Byte1]: 33
8549 00:40:50.641169
8550 00:40:50.641238 Set Vref, RX VrefLevel [Byte0]: 34
8551 00:40:50.644436 [Byte1]: 34
8552 00:40:50.650980
8553 00:40:50.651088 Set Vref, RX VrefLevel [Byte0]: 35
8554 00:40:50.652244 [Byte1]: 35
8555 00:40:50.656341
8556 00:40:50.656410 Set Vref, RX VrefLevel [Byte0]: 36
8557 00:40:50.659652 [Byte1]: 36
8558 00:40:50.664219
8559 00:40:50.664295 Set Vref, RX VrefLevel [Byte0]: 37
8560 00:40:50.667134 [Byte1]: 37
8561 00:40:50.671712
8562 00:40:50.671790 Set Vref, RX VrefLevel [Byte0]: 38
8563 00:40:50.674766 [Byte1]: 38
8564 00:40:50.679084
8565 00:40:50.679159 Set Vref, RX VrefLevel [Byte0]: 39
8566 00:40:50.682338 [Byte1]: 39
8567 00:40:50.686951
8568 00:40:50.687026 Set Vref, RX VrefLevel [Byte0]: 40
8569 00:40:50.689991 [Byte1]: 40
8570 00:40:50.694167
8571 00:40:50.694269 Set Vref, RX VrefLevel [Byte0]: 41
8572 00:40:50.697225 [Byte1]: 41
8573 00:40:50.701897
8574 00:40:50.701999 Set Vref, RX VrefLevel [Byte0]: 42
8575 00:40:50.704640 [Byte1]: 42
8576 00:40:50.709396
8577 00:40:50.709502 Set Vref, RX VrefLevel [Byte0]: 43
8578 00:40:50.712793 [Byte1]: 43
8579 00:40:50.716841
8580 00:40:50.716918 Set Vref, RX VrefLevel [Byte0]: 44
8581 00:40:50.720324 [Byte1]: 44
8582 00:40:50.724520
8583 00:40:50.724601 Set Vref, RX VrefLevel [Byte0]: 45
8584 00:40:50.727256 [Byte1]: 45
8585 00:40:50.731865
8586 00:40:50.731935 Set Vref, RX VrefLevel [Byte0]: 46
8587 00:40:50.735108 [Byte1]: 46
8588 00:40:50.738990
8589 00:40:50.739065 Set Vref, RX VrefLevel [Byte0]: 47
8590 00:40:50.742363 [Byte1]: 47
8591 00:40:50.747102
8592 00:40:50.747173 Set Vref, RX VrefLevel [Byte0]: 48
8593 00:40:50.750372 [Byte1]: 48
8594 00:40:50.754385
8595 00:40:50.754457 Set Vref, RX VrefLevel [Byte0]: 49
8596 00:40:50.758048 [Byte1]: 49
8597 00:40:50.761712
8598 00:40:50.761799 Set Vref, RX VrefLevel [Byte0]: 50
8599 00:40:50.764911 [Byte1]: 50
8600 00:40:50.769662
8601 00:40:50.769737 Set Vref, RX VrefLevel [Byte0]: 51
8602 00:40:50.773027 [Byte1]: 51
8603 00:40:50.776908
8604 00:40:50.776986 Set Vref, RX VrefLevel [Byte0]: 52
8605 00:40:50.780061 [Byte1]: 52
8606 00:40:50.784336
8607 00:40:50.784409 Set Vref, RX VrefLevel [Byte0]: 53
8608 00:40:50.787867 [Byte1]: 53
8609 00:40:50.791903
8610 00:40:50.791974 Set Vref, RX VrefLevel [Byte0]: 54
8611 00:40:50.795113 [Byte1]: 54
8612 00:40:50.799813
8613 00:40:50.799889 Set Vref, RX VrefLevel [Byte0]: 55
8614 00:40:50.802842 [Byte1]: 55
8615 00:40:50.807300
8616 00:40:50.807373 Set Vref, RX VrefLevel [Byte0]: 56
8617 00:40:50.810189 [Byte1]: 56
8618 00:40:50.814857
8619 00:40:50.814929 Set Vref, RX VrefLevel [Byte0]: 57
8620 00:40:50.817970 [Byte1]: 57
8621 00:40:50.822463
8622 00:40:50.822539 Set Vref, RX VrefLevel [Byte0]: 58
8623 00:40:50.825209 [Byte1]: 58
8624 00:40:50.830012
8625 00:40:50.830087 Set Vref, RX VrefLevel [Byte0]: 59
8626 00:40:50.832795 [Byte1]: 59
8627 00:40:50.837411
8628 00:40:50.837488 Set Vref, RX VrefLevel [Byte0]: 60
8629 00:40:50.840724 [Byte1]: 60
8630 00:40:50.844515
8631 00:40:50.844586 Set Vref, RX VrefLevel [Byte0]: 61
8632 00:40:50.847879 [Byte1]: 61
8633 00:40:50.852039
8634 00:40:50.852113 Set Vref, RX VrefLevel [Byte0]: 62
8635 00:40:50.855308 [Byte1]: 62
8636 00:40:50.860195
8637 00:40:50.860274 Set Vref, RX VrefLevel [Byte0]: 63
8638 00:40:50.863537 [Byte1]: 63
8639 00:40:50.867182
8640 00:40:50.867275 Set Vref, RX VrefLevel [Byte0]: 64
8641 00:40:50.870878 [Byte1]: 64
8642 00:40:50.874789
8643 00:40:50.874887 Set Vref, RX VrefLevel [Byte0]: 65
8644 00:40:50.878174 [Byte1]: 65
8645 00:40:50.882278
8646 00:40:50.882355 Set Vref, RX VrefLevel [Byte0]: 66
8647 00:40:50.885701 [Byte1]: 66
8648 00:40:50.890337
8649 00:40:50.890413 Set Vref, RX VrefLevel [Byte0]: 67
8650 00:40:50.893685 [Byte1]: 67
8651 00:40:50.897393
8652 00:40:50.897486 Set Vref, RX VrefLevel [Byte0]: 68
8653 00:40:50.900994 [Byte1]: 68
8654 00:40:50.905044
8655 00:40:50.905145 Set Vref, RX VrefLevel [Byte0]: 69
8656 00:40:50.908652 [Byte1]: 69
8657 00:40:50.912368
8658 00:40:50.912471 Set Vref, RX VrefLevel [Byte0]: 70
8659 00:40:50.915748 [Byte1]: 70
8660 00:40:50.920401
8661 00:40:50.920506 Set Vref, RX VrefLevel [Byte0]: 71
8662 00:40:50.923593 [Byte1]: 71
8663 00:40:50.927976
8664 00:40:50.928080 Set Vref, RX VrefLevel [Byte0]: 72
8665 00:40:50.930807 [Byte1]: 72
8666 00:40:50.935095
8667 00:40:50.935170 Set Vref, RX VrefLevel [Byte0]: 73
8668 00:40:50.938263 [Byte1]: 73
8669 00:40:50.942944
8670 00:40:50.943042 Set Vref, RX VrefLevel [Byte0]: 74
8671 00:40:50.946091 [Byte1]: 74
8672 00:40:50.950432
8673 00:40:50.950509 Set Vref, RX VrefLevel [Byte0]: 75
8674 00:40:50.953840 [Byte1]: 75
8675 00:40:50.957827
8676 00:40:50.957897 Set Vref, RX VrefLevel [Byte0]: 76
8677 00:40:50.961349 [Byte1]: 76
8678 00:40:50.965415
8679 00:40:50.965509 Set Vref, RX VrefLevel [Byte0]: 77
8680 00:40:50.968741 [Byte1]: 77
8681 00:40:50.972792
8682 00:40:50.972890 Final RX Vref Byte 0 = 60 to rank0
8683 00:40:50.976063 Final RX Vref Byte 1 = 53 to rank0
8684 00:40:50.979662 Final RX Vref Byte 0 = 60 to rank1
8685 00:40:50.982757 Final RX Vref Byte 1 = 53 to rank1==
8686 00:40:50.985935 Dram Type= 6, Freq= 0, CH_1, rank 0
8687 00:40:50.992710 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8688 00:40:50.992792 ==
8689 00:40:50.992860 DQS Delay:
8690 00:40:50.992937 DQS0 = 0, DQS1 = 0
8691 00:40:50.996044 DQM Delay:
8692 00:40:50.996138 DQM0 = 134, DQM1 = 130
8693 00:40:50.999218 DQ Delay:
8694 00:40:51.002568 DQ0 =140, DQ1 =130, DQ2 =122, DQ3 =130
8695 00:40:51.005956 DQ4 =134, DQ5 =144, DQ6 =144, DQ7 =134
8696 00:40:51.009262 DQ8 =116, DQ9 =120, DQ10 =132, DQ11 =124
8697 00:40:51.012422 DQ12 =138, DQ13 =136, DQ14 =140, DQ15 =140
8698 00:40:51.012520
8699 00:40:51.012612
8700 00:40:51.012691
8701 00:40:51.016112 [DramC_TX_OE_Calibration] TA2
8702 00:40:51.019419 Original DQ_B0 (3 6) =30, OEN = 27
8703 00:40:51.022996 Original DQ_B1 (3 6) =30, OEN = 27
8704 00:40:51.026295 24, 0x0, End_B0=24 End_B1=24
8705 00:40:51.026369 25, 0x0, End_B0=25 End_B1=25
8706 00:40:51.029760 26, 0x0, End_B0=26 End_B1=26
8707 00:40:51.032456 27, 0x0, End_B0=27 End_B1=27
8708 00:40:51.036318 28, 0x0, End_B0=28 End_B1=28
8709 00:40:51.036389 29, 0x0, End_B0=29 End_B1=29
8710 00:40:51.039667 30, 0x0, End_B0=30 End_B1=30
8711 00:40:51.042879 31, 0x4141, End_B0=30 End_B1=30
8712 00:40:51.045785 Byte0 end_step=30 best_step=27
8713 00:40:51.049146 Byte1 end_step=30 best_step=27
8714 00:40:51.052851 Byte0 TX OE(2T, 0.5T) = (3, 3)
8715 00:40:51.052921 Byte1 TX OE(2T, 0.5T) = (3, 3)
8716 00:40:51.055831
8717 00:40:51.055920
8718 00:40:51.062654 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a27, (MSB)MR19= 0x303, tDQSOscB0 = 390 ps tDQSOscB1 = 396 ps
8719 00:40:51.066001 CH1 RK0: MR19=303, MR18=1A27
8720 00:40:51.072710 CH1_RK0: MR19=0x303, MR18=0x1A27, DQSOSC=390, MR23=63, INC=24, DEC=16
8721 00:40:51.072787
8722 00:40:51.075518 ----->DramcWriteLeveling(PI) begin...
8723 00:40:51.075597 ==
8724 00:40:51.078956 Dram Type= 6, Freq= 0, CH_1, rank 1
8725 00:40:51.082330 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8726 00:40:51.082402 ==
8727 00:40:51.085616 Write leveling (Byte 0): 26 => 26
8728 00:40:51.088644 Write leveling (Byte 1): 29 => 29
8729 00:40:51.092220 DramcWriteLeveling(PI) end<-----
8730 00:40:51.092317
8731 00:40:51.092402 ==
8732 00:40:51.095737 Dram Type= 6, Freq= 0, CH_1, rank 1
8733 00:40:51.098961 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8734 00:40:51.099051 ==
8735 00:40:51.102329 [Gating] SW mode calibration
8736 00:40:51.108990 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8737 00:40:51.115810 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8738 00:40:51.119128 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8739 00:40:51.122335 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8740 00:40:51.128969 1 4 8 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
8741 00:40:51.131993 1 4 12 | B1->B0 | 3434 2c2c | 0 0 | (0 0) (0 0)
8742 00:40:51.135204 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8743 00:40:51.141917 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8744 00:40:51.145208 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8745 00:40:51.148671 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8746 00:40:51.155487 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8747 00:40:51.158833 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8748 00:40:51.162306 1 5 8 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 0)
8749 00:40:51.168681 1 5 12 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 1)
8750 00:40:51.171927 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8751 00:40:51.174911 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8752 00:40:51.181962 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8753 00:40:51.185365 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8754 00:40:51.188714 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8755 00:40:51.195299 1 6 4 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
8756 00:40:51.198509 1 6 8 | B1->B0 | 3e3e 2727 | 0 0 | (1 1) (0 0)
8757 00:40:51.201691 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8758 00:40:51.208200 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8759 00:40:51.212052 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8760 00:40:51.215303 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8761 00:40:51.221520 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8762 00:40:51.224864 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8763 00:40:51.228296 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8764 00:40:51.235367 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8765 00:40:51.238368 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8766 00:40:51.241420 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8767 00:40:51.248596 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8768 00:40:51.251948 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8769 00:40:51.255290 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8770 00:40:51.258494 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8771 00:40:51.264947 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8772 00:40:51.268404 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8773 00:40:51.271779 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8774 00:40:51.278545 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8775 00:40:51.281692 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8776 00:40:51.285161 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8777 00:40:51.291718 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8778 00:40:51.294818 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8779 00:40:51.298185 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8780 00:40:51.304583 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8781 00:40:51.308036 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8782 00:40:51.311391 Total UI for P1: 0, mck2ui 16
8783 00:40:51.315130 best dqsien dly found for B1: ( 1, 9, 8)
8784 00:40:51.318443 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8785 00:40:51.321440 Total UI for P1: 0, mck2ui 16
8786 00:40:51.324636 best dqsien dly found for B0: ( 1, 9, 10)
8787 00:40:51.328064 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8788 00:40:51.331391 best DQS1 dly(MCK, UI, PI) = (1, 9, 8)
8789 00:40:51.331482
8790 00:40:51.338170 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8791 00:40:51.341613 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 8)
8792 00:40:51.341697 [Gating] SW calibration Done
8793 00:40:51.344958 ==
8794 00:40:51.348001 Dram Type= 6, Freq= 0, CH_1, rank 1
8795 00:40:51.351244 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8796 00:40:51.351334 ==
8797 00:40:51.351431 RX Vref Scan: 0
8798 00:40:51.351533
8799 00:40:51.354613 RX Vref 0 -> 0, step: 1
8800 00:40:51.354675
8801 00:40:51.358182 RX Delay 0 -> 252, step: 8
8802 00:40:51.361334 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8803 00:40:51.364483 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8804 00:40:51.367885 iDelay=208, Bit 2, Center 123 (72 ~ 175) 104
8805 00:40:51.374327 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104
8806 00:40:51.377670 iDelay=208, Bit 4, Center 131 (80 ~ 183) 104
8807 00:40:51.381035 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8808 00:40:51.384467 iDelay=208, Bit 6, Center 147 (96 ~ 199) 104
8809 00:40:51.387862 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8810 00:40:51.394354 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8811 00:40:51.398109 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8812 00:40:51.401801 iDelay=208, Bit 10, Center 135 (80 ~ 191) 112
8813 00:40:51.404602 iDelay=208, Bit 11, Center 131 (80 ~ 183) 104
8814 00:40:51.408511 iDelay=208, Bit 12, Center 143 (88 ~ 199) 112
8815 00:40:51.414304 iDelay=208, Bit 13, Center 143 (88 ~ 199) 112
8816 00:40:51.418139 iDelay=208, Bit 14, Center 139 (88 ~ 191) 104
8817 00:40:51.421408 iDelay=208, Bit 15, Center 143 (88 ~ 199) 112
8818 00:40:51.421486 ==
8819 00:40:51.424833 Dram Type= 6, Freq= 0, CH_1, rank 1
8820 00:40:51.428044 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8821 00:40:51.428124 ==
8822 00:40:51.431106 DQS Delay:
8823 00:40:51.431185 DQS0 = 0, DQS1 = 0
8824 00:40:51.434836 DQM Delay:
8825 00:40:51.434913 DQM0 = 136, DQM1 = 134
8826 00:40:51.437667 DQ Delay:
8827 00:40:51.440985 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =131
8828 00:40:51.444362 DQ4 =131, DQ5 =151, DQ6 =147, DQ7 =135
8829 00:40:51.447872 DQ8 =119, DQ9 =119, DQ10 =135, DQ11 =131
8830 00:40:51.451337 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8831 00:40:51.451412
8832 00:40:51.451470
8833 00:40:51.451523 ==
8834 00:40:51.454811 Dram Type= 6, Freq= 0, CH_1, rank 1
8835 00:40:51.457699 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8836 00:40:51.457804 ==
8837 00:40:51.457862
8838 00:40:51.457916
8839 00:40:51.460894 TX Vref Scan disable
8840 00:40:51.464529 == TX Byte 0 ==
8841 00:40:51.467996 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8842 00:40:51.470778 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8843 00:40:51.474404 == TX Byte 1 ==
8844 00:40:51.477380 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8845 00:40:51.480895 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8846 00:40:51.480971 ==
8847 00:40:51.484618 Dram Type= 6, Freq= 0, CH_1, rank 1
8848 00:40:51.490735 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8849 00:40:51.490812 ==
8850 00:40:51.502137
8851 00:40:51.505615 TX Vref early break, caculate TX vref
8852 00:40:51.508831 TX Vref=16, minBit 0, minWin=23, winSum=381
8853 00:40:51.512058 TX Vref=18, minBit 0, minWin=23, winSum=389
8854 00:40:51.515262 TX Vref=20, minBit 0, minWin=24, winSum=402
8855 00:40:51.518890 TX Vref=22, minBit 0, minWin=24, winSum=404
8856 00:40:51.522074 TX Vref=24, minBit 0, minWin=25, winSum=416
8857 00:40:51.529003 TX Vref=26, minBit 0, minWin=25, winSum=425
8858 00:40:51.532064 TX Vref=28, minBit 0, minWin=25, winSum=429
8859 00:40:51.535338 TX Vref=30, minBit 1, minWin=25, winSum=417
8860 00:40:51.538870 TX Vref=32, minBit 0, minWin=25, winSum=410
8861 00:40:51.541995 TX Vref=34, minBit 0, minWin=24, winSum=405
8862 00:40:51.548746 [TxChooseVref] Worse bit 0, Min win 25, Win sum 429, Final Vref 28
8863 00:40:51.548820
8864 00:40:51.552188 Final TX Range 0 Vref 28
8865 00:40:51.552266
8866 00:40:51.552326 ==
8867 00:40:51.555696 Dram Type= 6, Freq= 0, CH_1, rank 1
8868 00:40:51.558364 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8869 00:40:51.558443 ==
8870 00:40:51.558503
8871 00:40:51.558559
8872 00:40:51.561844 TX Vref Scan disable
8873 00:40:51.568589 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8874 00:40:51.568696 == TX Byte 0 ==
8875 00:40:51.571824 u2DelayCellOfst[0]=17 cells (5 PI)
8876 00:40:51.575704 u2DelayCellOfst[1]=10 cells (3 PI)
8877 00:40:51.578442 u2DelayCellOfst[2]=0 cells (0 PI)
8878 00:40:51.582124 u2DelayCellOfst[3]=6 cells (2 PI)
8879 00:40:51.585375 u2DelayCellOfst[4]=10 cells (3 PI)
8880 00:40:51.588369 u2DelayCellOfst[5]=17 cells (5 PI)
8881 00:40:51.591879 u2DelayCellOfst[6]=17 cells (5 PI)
8882 00:40:51.591956 u2DelayCellOfst[7]=3 cells (1 PI)
8883 00:40:51.598263 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8884 00:40:51.601823 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8885 00:40:51.601900 == TX Byte 1 ==
8886 00:40:51.605218 u2DelayCellOfst[8]=0 cells (0 PI)
8887 00:40:51.608592 u2DelayCellOfst[9]=3 cells (1 PI)
8888 00:40:51.611920 u2DelayCellOfst[10]=10 cells (3 PI)
8889 00:40:51.615238 u2DelayCellOfst[11]=3 cells (1 PI)
8890 00:40:51.618601 u2DelayCellOfst[12]=13 cells (4 PI)
8891 00:40:51.621979 u2DelayCellOfst[13]=17 cells (5 PI)
8892 00:40:51.624728 u2DelayCellOfst[14]=17 cells (5 PI)
8893 00:40:51.628133 u2DelayCellOfst[15]=17 cells (5 PI)
8894 00:40:51.631515 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8895 00:40:51.638007 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8896 00:40:51.638083 DramC Write-DBI on
8897 00:40:51.638143 ==
8898 00:40:51.641495 Dram Type= 6, Freq= 0, CH_1, rank 1
8899 00:40:51.644741 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8900 00:40:51.647909 ==
8901 00:40:51.647986
8902 00:40:51.648045
8903 00:40:51.648100 TX Vref Scan disable
8904 00:40:51.651362 == TX Byte 0 ==
8905 00:40:51.654921 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8906 00:40:51.657931 == TX Byte 1 ==
8907 00:40:51.661481 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8908 00:40:51.664527 DramC Write-DBI off
8909 00:40:51.664604
8910 00:40:51.664664 [DATLAT]
8911 00:40:51.664720 Freq=1600, CH1 RK1
8912 00:40:51.664773
8913 00:40:51.667872 DATLAT Default: 0xf
8914 00:40:51.667949 0, 0xFFFF, sum = 0
8915 00:40:51.671275 1, 0xFFFF, sum = 0
8916 00:40:51.671353 2, 0xFFFF, sum = 0
8917 00:40:51.674685 3, 0xFFFF, sum = 0
8918 00:40:51.678076 4, 0xFFFF, sum = 0
8919 00:40:51.678154 5, 0xFFFF, sum = 0
8920 00:40:51.681311 6, 0xFFFF, sum = 0
8921 00:40:51.681390 7, 0xFFFF, sum = 0
8922 00:40:51.684483 8, 0xFFFF, sum = 0
8923 00:40:51.684562 9, 0xFFFF, sum = 0
8924 00:40:51.688129 10, 0xFFFF, sum = 0
8925 00:40:51.688207 11, 0xFFFF, sum = 0
8926 00:40:51.691092 12, 0xFFFF, sum = 0
8927 00:40:51.691171 13, 0xFFFF, sum = 0
8928 00:40:51.695075 14, 0x0, sum = 1
8929 00:40:51.695153 15, 0x0, sum = 2
8930 00:40:51.697686 16, 0x0, sum = 3
8931 00:40:51.697764 17, 0x0, sum = 4
8932 00:40:51.701466 best_step = 15
8933 00:40:51.701572
8934 00:40:51.701634 ==
8935 00:40:51.704493 Dram Type= 6, Freq= 0, CH_1, rank 1
8936 00:40:51.707656 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8937 00:40:51.707734 ==
8938 00:40:51.707794 RX Vref Scan: 0
8939 00:40:51.711458
8940 00:40:51.711559 RX Vref 0 -> 0, step: 1
8941 00:40:51.711652
8942 00:40:51.714892 RX Delay 19 -> 252, step: 4
8943 00:40:51.717678 iDelay=195, Bit 0, Center 138 (91 ~ 186) 96
8944 00:40:51.724411 iDelay=195, Bit 1, Center 132 (83 ~ 182) 100
8945 00:40:51.727763 iDelay=195, Bit 2, Center 122 (71 ~ 174) 104
8946 00:40:51.731173 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
8947 00:40:51.734599 iDelay=195, Bit 4, Center 130 (83 ~ 178) 96
8948 00:40:51.738082 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
8949 00:40:51.741359 iDelay=195, Bit 6, Center 144 (95 ~ 194) 100
8950 00:40:51.747792 iDelay=195, Bit 7, Center 134 (83 ~ 186) 104
8951 00:40:51.751133 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
8952 00:40:51.754345 iDelay=195, Bit 9, Center 120 (67 ~ 174) 108
8953 00:40:51.757586 iDelay=195, Bit 10, Center 130 (79 ~ 182) 104
8954 00:40:51.760957 iDelay=195, Bit 11, Center 126 (75 ~ 178) 104
8955 00:40:51.768177 iDelay=195, Bit 12, Center 140 (87 ~ 194) 108
8956 00:40:51.771277 iDelay=195, Bit 13, Center 136 (87 ~ 186) 100
8957 00:40:51.774202 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
8958 00:40:51.777862 iDelay=195, Bit 15, Center 140 (91 ~ 190) 100
8959 00:40:51.777940 ==
8960 00:40:51.781297 Dram Type= 6, Freq= 0, CH_1, rank 1
8961 00:40:51.787370 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8962 00:40:51.787448 ==
8963 00:40:51.787508 DQS Delay:
8964 00:40:51.790886 DQS0 = 0, DQS1 = 0
8965 00:40:51.790965 DQM Delay:
8966 00:40:51.794094 DQM0 = 134, DQM1 = 130
8967 00:40:51.794169 DQ Delay:
8968 00:40:51.797312 DQ0 =138, DQ1 =132, DQ2 =122, DQ3 =130
8969 00:40:51.800753 DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =134
8970 00:40:51.803943 DQ8 =116, DQ9 =120, DQ10 =130, DQ11 =126
8971 00:40:51.807243 DQ12 =140, DQ13 =136, DQ14 =136, DQ15 =140
8972 00:40:51.807336
8973 00:40:51.807408
8974 00:40:51.807462
8975 00:40:51.811013 [DramC_TX_OE_Calibration] TA2
8976 00:40:51.814015 Original DQ_B0 (3 6) =30, OEN = 27
8977 00:40:51.817152 Original DQ_B1 (3 6) =30, OEN = 27
8978 00:40:51.820945 24, 0x0, End_B0=24 End_B1=24
8979 00:40:51.824249 25, 0x0, End_B0=25 End_B1=25
8980 00:40:51.824326 26, 0x0, End_B0=26 End_B1=26
8981 00:40:51.827603 27, 0x0, End_B0=27 End_B1=27
8982 00:40:51.830893 28, 0x0, End_B0=28 End_B1=28
8983 00:40:51.833638 29, 0x0, End_B0=29 End_B1=29
8984 00:40:51.833739 30, 0x0, End_B0=30 End_B1=30
8985 00:40:51.837048 31, 0x4141, End_B0=30 End_B1=30
8986 00:40:51.840438 Byte0 end_step=30 best_step=27
8987 00:40:51.843875 Byte1 end_step=30 best_step=27
8988 00:40:51.847268 Byte0 TX OE(2T, 0.5T) = (3, 3)
8989 00:40:51.850627 Byte1 TX OE(2T, 0.5T) = (3, 3)
8990 00:40:51.850711
8991 00:40:51.850768
8992 00:40:51.857257 [DQSOSCAuto] RK1, (LSB)MR18= 0x260b, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 390 ps
8993 00:40:51.860572 CH1 RK1: MR19=303, MR18=260B
8994 00:40:51.867193 CH1_RK1: MR19=0x303, MR18=0x260B, DQSOSC=390, MR23=63, INC=24, DEC=16
8995 00:40:51.870631 [RxdqsGatingPostProcess] freq 1600
8996 00:40:51.874073 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8997 00:40:51.877400 best DQS0 dly(2T, 0.5T) = (1, 1)
8998 00:40:51.880696 best DQS1 dly(2T, 0.5T) = (1, 1)
8999 00:40:51.883755 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9000 00:40:51.887463 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9001 00:40:51.890403 best DQS0 dly(2T, 0.5T) = (1, 1)
9002 00:40:51.893990 best DQS1 dly(2T, 0.5T) = (1, 1)
9003 00:40:51.897402 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9004 00:40:51.900168 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9005 00:40:51.904039 Pre-setting of DQS Precalculation
9006 00:40:51.907055 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9007 00:40:51.913488 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9008 00:40:51.923942 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9009 00:40:51.924015
9010 00:40:51.924073
9011 00:40:51.926857 [Calibration Summary] 3200 Mbps
9012 00:40:51.926932 CH 0, Rank 0
9013 00:40:51.930015 SW Impedance : PASS
9014 00:40:51.930127 DUTY Scan : NO K
9015 00:40:51.933599 ZQ Calibration : PASS
9016 00:40:51.937145 Jitter Meter : NO K
9017 00:40:51.937221 CBT Training : PASS
9018 00:40:51.940571 Write leveling : PASS
9019 00:40:51.940640 RX DQS gating : PASS
9020 00:40:51.943499 RX DQ/DQS(RDDQC) : PASS
9021 00:40:51.946896 TX DQ/DQS : PASS
9022 00:40:51.946975 RX DATLAT : PASS
9023 00:40:51.950351 RX DQ/DQS(Engine): PASS
9024 00:40:51.953236 TX OE : PASS
9025 00:40:51.953349 All Pass.
9026 00:40:51.953456
9027 00:40:51.953538 CH 0, Rank 1
9028 00:40:51.957082 SW Impedance : PASS
9029 00:40:51.959881 DUTY Scan : NO K
9030 00:40:51.959969 ZQ Calibration : PASS
9031 00:40:51.963104 Jitter Meter : NO K
9032 00:40:51.967137 CBT Training : PASS
9033 00:40:51.967227 Write leveling : PASS
9034 00:40:51.969747 RX DQS gating : PASS
9035 00:40:51.973666 RX DQ/DQS(RDDQC) : PASS
9036 00:40:51.973736 TX DQ/DQS : PASS
9037 00:40:51.977070 RX DATLAT : PASS
9038 00:40:51.980290 RX DQ/DQS(Engine): PASS
9039 00:40:51.980356 TX OE : PASS
9040 00:40:51.983065 All Pass.
9041 00:40:51.983156
9042 00:40:51.983245 CH 1, Rank 0
9043 00:40:51.986417 SW Impedance : PASS
9044 00:40:51.986502 DUTY Scan : NO K
9045 00:40:51.989805 ZQ Calibration : PASS
9046 00:40:51.993091 Jitter Meter : NO K
9047 00:40:51.993161 CBT Training : PASS
9048 00:40:51.996371 Write leveling : PASS
9049 00:40:51.996482 RX DQS gating : PASS
9050 00:40:52.000142 RX DQ/DQS(RDDQC) : PASS
9051 00:40:52.003595 TX DQ/DQS : PASS
9052 00:40:52.003700 RX DATLAT : PASS
9053 00:40:52.006682 RX DQ/DQS(Engine): PASS
9054 00:40:52.009981 TX OE : PASS
9055 00:40:52.010047 All Pass.
9056 00:40:52.010156
9057 00:40:52.010210 CH 1, Rank 1
9058 00:40:52.013130 SW Impedance : PASS
9059 00:40:52.017053 DUTY Scan : NO K
9060 00:40:52.017144 ZQ Calibration : PASS
9061 00:40:52.020110 Jitter Meter : NO K
9062 00:40:52.023351 CBT Training : PASS
9063 00:40:52.023451 Write leveling : PASS
9064 00:40:52.026722 RX DQS gating : PASS
9065 00:40:52.030092 RX DQ/DQS(RDDQC) : PASS
9066 00:40:52.030171 TX DQ/DQS : PASS
9067 00:40:52.033677 RX DATLAT : PASS
9068 00:40:52.033783 RX DQ/DQS(Engine): PASS
9069 00:40:52.036944 TX OE : PASS
9070 00:40:52.037046 All Pass.
9071 00:40:52.037132
9072 00:40:52.040052 DramC Write-DBI on
9073 00:40:52.043213 PER_BANK_REFRESH: Hybrid Mode
9074 00:40:52.043315 TX_TRACKING: ON
9075 00:40:52.053628 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9076 00:40:52.060309 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9077 00:40:52.069737 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9078 00:40:52.073082 [FAST_K] Save calibration result to emmc
9079 00:40:52.073183 sync common calibartion params.
9080 00:40:52.076899 sync cbt_mode0:1, 1:1
9081 00:40:52.079598 dram_init: ddr_geometry: 2
9082 00:40:52.083411 dram_init: ddr_geometry: 2
9083 00:40:52.083510 dram_init: ddr_geometry: 2
9084 00:40:52.086807 0:dram_rank_size:100000000
9085 00:40:52.090054 1:dram_rank_size:100000000
9086 00:40:52.093325 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9087 00:40:52.096630 DFS_SHUFFLE_HW_MODE: ON
9088 00:40:52.100054 dramc_set_vcore_voltage set vcore to 725000
9089 00:40:52.103438 Read voltage for 1600, 0
9090 00:40:52.103529 Vio18 = 0
9091 00:40:52.106126 Vcore = 725000
9092 00:40:52.106192 Vdram = 0
9093 00:40:52.106262 Vddq = 0
9094 00:40:52.106333 Vmddr = 0
9095 00:40:52.109999 switch to 3200 Mbps bootup
9096 00:40:52.112982 [DramcRunTimeConfig]
9097 00:40:52.113049 PHYPLL
9098 00:40:52.116104 DPM_CONTROL_AFTERK: ON
9099 00:40:52.116168 PER_BANK_REFRESH: ON
9100 00:40:52.119899 REFRESH_OVERHEAD_REDUCTION: ON
9101 00:40:52.123105 CMD_PICG_NEW_MODE: OFF
9102 00:40:52.123174 XRTWTW_NEW_MODE: ON
9103 00:40:52.126195 XRTRTR_NEW_MODE: ON
9104 00:40:52.126263 TX_TRACKING: ON
9105 00:40:52.129968 RDSEL_TRACKING: OFF
9106 00:40:52.130056 DQS Precalculation for DVFS: ON
9107 00:40:52.133363 RX_TRACKING: OFF
9108 00:40:52.133453 HW_GATING DBG: ON
9109 00:40:52.136659 ZQCS_ENABLE_LP4: ON
9110 00:40:52.139874 RX_PICG_NEW_MODE: ON
9111 00:40:52.139960 TX_PICG_NEW_MODE: ON
9112 00:40:52.142963 ENABLE_RX_DCM_DPHY: ON
9113 00:40:52.146085 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9114 00:40:52.146155 DUMMY_READ_FOR_TRACKING: OFF
9115 00:40:52.149923 !!! SPM_CONTROL_AFTERK: OFF
9116 00:40:52.153096 !!! SPM could not control APHY
9117 00:40:52.156284 IMPEDANCE_TRACKING: ON
9118 00:40:52.156386 TEMP_SENSOR: ON
9119 00:40:52.159713 HW_SAVE_FOR_SR: OFF
9120 00:40:52.159782 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9121 00:40:52.166281 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9122 00:40:52.166379 Read ODT Tracking: ON
9123 00:40:52.169764 Refresh Rate DeBounce: ON
9124 00:40:52.172568 DFS_NO_QUEUE_FLUSH: ON
9125 00:40:52.175994 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9126 00:40:52.176071 ENABLE_DFS_RUNTIME_MRW: OFF
9127 00:40:52.179796 DDR_RESERVE_NEW_MODE: ON
9128 00:40:52.183154 MR_CBT_SWITCH_FREQ: ON
9129 00:40:52.183232 =========================
9130 00:40:52.203187 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9131 00:40:52.205905 dram_init: ddr_geometry: 2
9132 00:40:52.224075 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9133 00:40:52.227714 dram_init: dram init end (result: 0)
9134 00:40:52.234309 DRAM-K: Full calibration passed in 24441 msecs
9135 00:40:52.237411 MRC: failed to locate region type 0.
9136 00:40:52.237512 DRAM rank0 size:0x100000000,
9137 00:40:52.241266 DRAM rank1 size=0x100000000
9138 00:40:52.251014 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9139 00:40:52.257678 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9140 00:40:52.264422 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9141 00:40:52.271086 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9142 00:40:52.274671 DRAM rank0 size:0x100000000,
9143 00:40:52.277930 DRAM rank1 size=0x100000000
9144 00:40:52.278007 CBMEM:
9145 00:40:52.280607 IMD: root @ 0xfffff000 254 entries.
9146 00:40:52.284058 IMD: root @ 0xffffec00 62 entries.
9147 00:40:52.287843 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9148 00:40:52.291428 WARNING: RO_VPD is uninitialized or empty.
9149 00:40:52.297354 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9150 00:40:52.304579 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9151 00:40:52.317146 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9152 00:40:52.328635 BS: romstage times (exec / console): total (unknown) / 23971 ms
9153 00:40:52.328739
9154 00:40:52.328824
9155 00:40:52.338547 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9156 00:40:52.342127 ARM64: Exception handlers installed.
9157 00:40:52.345088 ARM64: Testing exception
9158 00:40:52.348141 ARM64: Done test exception
9159 00:40:52.348244 Enumerating buses...
9160 00:40:52.352050 Show all devs... Before device enumeration.
9161 00:40:52.354776 Root Device: enabled 1
9162 00:40:52.358120 CPU_CLUSTER: 0: enabled 1
9163 00:40:52.358197 CPU: 00: enabled 1
9164 00:40:52.362004 Compare with tree...
9165 00:40:52.362071 Root Device: enabled 1
9166 00:40:52.365196 CPU_CLUSTER: 0: enabled 1
9167 00:40:52.368201 CPU: 00: enabled 1
9168 00:40:52.368281 Root Device scanning...
9169 00:40:52.371299 scan_static_bus for Root Device
9170 00:40:52.375142 CPU_CLUSTER: 0 enabled
9171 00:40:52.378252 scan_static_bus for Root Device done
9172 00:40:52.382002 scan_bus: bus Root Device finished in 8 msecs
9173 00:40:52.382096 done
9174 00:40:52.388014 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9175 00:40:52.391331 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9176 00:40:52.398001 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9177 00:40:52.401355 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9178 00:40:52.404713 Allocating resources...
9179 00:40:52.404819 Reading resources...
9180 00:40:52.412014 Root Device read_resources bus 0 link: 0
9181 00:40:52.412089 DRAM rank0 size:0x100000000,
9182 00:40:52.414584 DRAM rank1 size=0x100000000
9183 00:40:52.418021 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9184 00:40:52.421348 CPU: 00 missing read_resources
9185 00:40:52.424650 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9186 00:40:52.431379 Root Device read_resources bus 0 link: 0 done
9187 00:40:52.431455 Done reading resources.
9188 00:40:52.438098 Show resources in subtree (Root Device)...After reading.
9189 00:40:52.441340 Root Device child on link 0 CPU_CLUSTER: 0
9190 00:40:52.444464 CPU_CLUSTER: 0 child on link 0 CPU: 00
9191 00:40:52.454799 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9192 00:40:52.454892 CPU: 00
9193 00:40:52.457764 Root Device assign_resources, bus 0 link: 0
9194 00:40:52.461245 CPU_CLUSTER: 0 missing set_resources
9195 00:40:52.464860 Root Device assign_resources, bus 0 link: 0 done
9196 00:40:52.468194 Done setting resources.
9197 00:40:52.474501 Show resources in subtree (Root Device)...After assigning values.
9198 00:40:52.478265 Root Device child on link 0 CPU_CLUSTER: 0
9199 00:40:52.481248 CPU_CLUSTER: 0 child on link 0 CPU: 00
9200 00:40:52.491250 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9201 00:40:52.491355 CPU: 00
9202 00:40:52.494799 Done allocating resources.
9203 00:40:52.498098 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9204 00:40:52.501324 Enabling resources...
9205 00:40:52.501401 done.
9206 00:40:52.508176 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9207 00:40:52.508275 Initializing devices...
9208 00:40:52.511530 Root Device init
9209 00:40:52.511623 init hardware done!
9210 00:40:52.514820 0x00000018: ctrlr->caps
9211 00:40:52.517469 52.000 MHz: ctrlr->f_max
9212 00:40:52.517570 0.400 MHz: ctrlr->f_min
9213 00:40:52.520818 0x40ff8080: ctrlr->voltages
9214 00:40:52.520921 sclk: 390625
9215 00:40:52.524182 Bus Width = 1
9216 00:40:52.524258 sclk: 390625
9217 00:40:52.527636 Bus Width = 1
9218 00:40:52.527711 Early init status = 3
9219 00:40:52.534372 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9220 00:40:52.537882 in-header: 03 fc 00 00 01 00 00 00
9221 00:40:52.537958 in-data: 00
9222 00:40:52.544295 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9223 00:40:52.547573 in-header: 03 fd 00 00 00 00 00 00
9224 00:40:52.550824 in-data:
9225 00:40:52.554105 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9226 00:40:52.558187 in-header: 03 fc 00 00 01 00 00 00
9227 00:40:52.561691 in-data: 00
9228 00:40:52.564850 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9229 00:40:52.570203 in-header: 03 fd 00 00 00 00 00 00
9230 00:40:52.573356 in-data:
9231 00:40:52.576720 [SSUSB] Setting up USB HOST controller...
9232 00:40:52.580363 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9233 00:40:52.583587 [SSUSB] phy power-on done.
9234 00:40:52.586584 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9235 00:40:52.594032 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9236 00:40:52.597070 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9237 00:40:52.603463 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9238 00:40:52.610553 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9239 00:40:52.617401 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9240 00:40:52.623355 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9241 00:40:52.630062 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9242 00:40:52.630134 SPM: binary array size = 0x9dc
9243 00:40:52.636756 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9244 00:40:52.643441 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9245 00:40:52.650034 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9246 00:40:52.653056 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9247 00:40:52.659598 configure_display: Starting display init
9248 00:40:52.693263 anx7625_power_on_init: Init interface.
9249 00:40:52.696753 anx7625_disable_pd_protocol: Disabled PD feature.
9250 00:40:52.700278 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9251 00:40:52.728010 anx7625_start_dp_work: Secure OCM version=00
9252 00:40:52.731372 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9253 00:40:52.746232 sp_tx_get_edid_block: EDID Block = 1
9254 00:40:52.848821 Extracted contents:
9255 00:40:52.851980 header: 00 ff ff ff ff ff ff 00
9256 00:40:52.854843 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9257 00:40:52.858213 version: 01 04
9258 00:40:52.861688 basic params: 95 1f 11 78 0a
9259 00:40:52.864989 chroma info: 76 90 94 55 54 90 27 21 50 54
9260 00:40:52.868286 established: 00 00 00
9261 00:40:52.874642 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9262 00:40:52.878039 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9263 00:40:52.884694 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9264 00:40:52.891456 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9265 00:40:52.898220 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9266 00:40:52.901387 extensions: 00
9267 00:40:52.901487 checksum: fb
9268 00:40:52.901609
9269 00:40:52.904638 Manufacturer: IVO Model 57d Serial Number 0
9270 00:40:52.908075 Made week 0 of 2020
9271 00:40:52.908150 EDID version: 1.4
9272 00:40:52.911200 Digital display
9273 00:40:52.914743 6 bits per primary color channel
9274 00:40:52.914822 DisplayPort interface
9275 00:40:52.918061 Maximum image size: 31 cm x 17 cm
9276 00:40:52.921305 Gamma: 220%
9277 00:40:52.921382 Check DPMS levels
9278 00:40:52.924393 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9279 00:40:52.931142 First detailed timing is preferred timing
9280 00:40:52.931223 Established timings supported:
9281 00:40:52.934639 Standard timings supported:
9282 00:40:52.937690 Detailed timings
9283 00:40:52.941042 Hex of detail: 383680a07038204018303c0035ae10000019
9284 00:40:52.945178 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9285 00:40:52.951362 0780 0798 07c8 0820 hborder 0
9286 00:40:52.954830 0438 043b 0447 0458 vborder 0
9287 00:40:52.958249 -hsync -vsync
9288 00:40:52.958321 Did detailed timing
9289 00:40:52.961083 Hex of detail: 000000000000000000000000000000000000
9290 00:40:52.964735 Manufacturer-specified data, tag 0
9291 00:40:52.971213 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9292 00:40:52.971294 ASCII string: InfoVision
9293 00:40:52.977750 Hex of detail: 000000fe00523134304e574635205248200a
9294 00:40:52.981099 ASCII string: R140NWF5 RH
9295 00:40:52.981202 Checksum
9296 00:40:52.981288 Checksum: 0xfb (valid)
9297 00:40:52.988309 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9298 00:40:52.991017 DSI data_rate: 832800000 bps
9299 00:40:52.994338 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9300 00:40:53.001195 anx7625_parse_edid: pixelclock(138800).
9301 00:40:53.004657 hactive(1920), hsync(48), hfp(24), hbp(88)
9302 00:40:53.007962 vactive(1080), vsync(12), vfp(3), vbp(17)
9303 00:40:53.011170 anx7625_dsi_config: config dsi.
9304 00:40:53.017700 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9305 00:40:53.030835 anx7625_dsi_config: success to config DSI
9306 00:40:53.034034 anx7625_dp_start: MIPI phy setup OK.
9307 00:40:53.037429 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9308 00:40:53.040645 mtk_ddp_mode_set invalid vrefresh 60
9309 00:40:53.043680 main_disp_path_setup
9310 00:40:53.043756 ovl_layer_smi_id_en
9311 00:40:53.047242 ovl_layer_smi_id_en
9312 00:40:53.047319 ccorr_config
9313 00:40:53.047378 aal_config
9314 00:40:53.050331 gamma_config
9315 00:40:53.050407 postmask_config
9316 00:40:53.053739 dither_config
9317 00:40:53.057086 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9318 00:40:53.063946 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9319 00:40:53.067393 Root Device init finished in 553 msecs
9320 00:40:53.067470 CPU_CLUSTER: 0 init
9321 00:40:53.077261 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9322 00:40:53.080284 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9323 00:40:53.083871 APU_MBOX 0x190000b0 = 0x10001
9324 00:40:53.087012 APU_MBOX 0x190001b0 = 0x10001
9325 00:40:53.090355 APU_MBOX 0x190005b0 = 0x10001
9326 00:40:53.093778 APU_MBOX 0x190006b0 = 0x10001
9327 00:40:53.097118 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9328 00:40:53.109661 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9329 00:40:53.121919 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9330 00:40:53.128735 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9331 00:40:53.139935 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9332 00:40:53.149459 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9333 00:40:53.152674 CPU_CLUSTER: 0 init finished in 81 msecs
9334 00:40:53.156385 Devices initialized
9335 00:40:53.159355 Show all devs... After init.
9336 00:40:53.159432 Root Device: enabled 1
9337 00:40:53.162615 CPU_CLUSTER: 0: enabled 1
9338 00:40:53.166009 CPU: 00: enabled 1
9339 00:40:53.169340 BS: BS_DEV_INIT run times (exec / console): 211 / 447 ms
9340 00:40:53.172788 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9341 00:40:53.176283 ELOG: NV offset 0x57f000 size 0x1000
9342 00:40:53.183011 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9343 00:40:53.189683 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9344 00:40:53.193012 ELOG: Event(17) added with size 13 at 2024-06-16 00:40:52 UTC
9345 00:40:53.196394 out: cmd=0x121: 03 db 21 01 00 00 00 00
9346 00:40:53.199738 in-header: 03 a9 00 00 2c 00 00 00
9347 00:40:53.212889 in-data: 95 71 00 00 00 00 00 00 0a 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9348 00:40:53.219945 ELOG: Event(A1) added with size 10 at 2024-06-16 00:40:52 UTC
9349 00:40:53.226173 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
9350 00:40:53.229651 ELOG: Event(A0) added with size 9 at 2024-06-16 00:40:52 UTC
9351 00:40:53.236712 elog_add_boot_reason: Logged dev mode boot
9352 00:40:53.240182 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9353 00:40:53.243329 Finalize devices...
9354 00:40:53.243416 Devices finalized
9355 00:40:53.249947 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9356 00:40:53.253308 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
9357 00:40:53.256664 in-header: 03 07 00 00 08 00 00 00
9358 00:40:53.259399 in-data: aa e4 47 04 13 02 00 00
9359 00:40:53.259480 Chrome EC: UHEPI supported
9360 00:40:53.266272 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
9361 00:40:53.269990 in-header: 03 a9 00 00 08 00 00 00
9362 00:40:53.273306 in-data: 84 60 60 08 00 00 00 00
9363 00:40:53.279991 ELOG: Event(91) added with size 10 at 2024-06-16 00:40:52 UTC
9364 00:40:53.283368 Chrome EC: clear events_b mask to 0x0000000020004000
9365 00:40:53.290217 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
9366 00:40:53.294258 in-header: 03 fd 00 00 00 00 00 00
9367 00:40:53.298156 in-data:
9368 00:40:53.300898 BS: BS_WRITE_TABLES entry times (exec / console): 2 / 46 ms
9369 00:40:53.304337 Writing coreboot table at 0xffe64000
9370 00:40:53.311304 0. 000000000010a000-0000000000113fff: RAMSTAGE
9371 00:40:53.314731 1. 0000000040000000-00000000400fffff: RAM
9372 00:40:53.317999 2. 0000000040100000-000000004032afff: RAMSTAGE
9373 00:40:53.321295 3. 000000004032b000-00000000545fffff: RAM
9374 00:40:53.324571 4. 0000000054600000-000000005465ffff: BL31
9375 00:40:53.327638 5. 0000000054660000-00000000ffe63fff: RAM
9376 00:40:53.334637 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9377 00:40:53.337948 7. 0000000100000000-000000023fffffff: RAM
9378 00:40:53.340900 Passing 5 GPIOs to payload:
9379 00:40:53.344393 NAME | PORT | POLARITY | VALUE
9380 00:40:53.351026 EC in RW | 0x000000aa | low | undefined
9381 00:40:53.354640 EC interrupt | 0x00000005 | low | undefined
9382 00:40:53.358177 TPM interrupt | 0x000000ab | high | undefined
9383 00:40:53.364690 SD card detect | 0x00000011 | high | undefined
9384 00:40:53.367751 speaker enable | 0x00000093 | high | undefined
9385 00:40:53.371126 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9386 00:40:53.374148 in-header: 03 f9 00 00 02 00 00 00
9387 00:40:53.377838 in-data: 02 00
9388 00:40:53.380836 ADC[4]: Raw value=904357 ID=7
9389 00:40:53.380905 ADC[3]: Raw value=213441 ID=1
9390 00:40:53.384602 RAM Code: 0x71
9391 00:40:53.388013 ADC[6]: Raw value=75332 ID=0
9392 00:40:53.388091 ADC[5]: Raw value=213072 ID=1
9393 00:40:53.391358 SKU Code: 0x1
9394 00:40:53.394768 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 9aaf
9395 00:40:53.398285 coreboot table: 964 bytes.
9396 00:40:53.401444 IMD ROOT 0. 0xfffff000 0x00001000
9397 00:40:53.404662 IMD SMALL 1. 0xffffe000 0x00001000
9398 00:40:53.407852 RO MCACHE 2. 0xffffc000 0x00001104
9399 00:40:53.411166 CONSOLE 3. 0xfff7c000 0x00080000
9400 00:40:53.414544 FMAP 4. 0xfff7b000 0x00000452
9401 00:40:53.417945 TIME STAMP 5. 0xfff7a000 0x00000910
9402 00:40:53.421434 VBOOT WORK 6. 0xfff66000 0x00014000
9403 00:40:53.424691 RAMOOPS 7. 0xffe66000 0x00100000
9404 00:40:53.428158 COREBOOT 8. 0xffe64000 0x00002000
9405 00:40:53.431355 IMD small region:
9406 00:40:53.434488 IMD ROOT 0. 0xffffec00 0x00000400
9407 00:40:53.437795 VPD 1. 0xffffeb80 0x0000006c
9408 00:40:53.440923 MMC STATUS 2. 0xffffeb60 0x00000004
9409 00:40:53.444355 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9410 00:40:53.451279 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9411 00:40:53.491539 read SPI 0x3990ec 0x4f1b0: 34851 us, 9297 KB/s, 74.376 Mbps
9412 00:40:53.495098 Checking segment from ROM address 0x40100000
9413 00:40:53.497981 Checking segment from ROM address 0x4010001c
9414 00:40:53.504909 Loading segment from ROM address 0x40100000
9415 00:40:53.504989 code (compression=0)
9416 00:40:53.511343 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9417 00:40:53.522077 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9418 00:40:53.522155 it's not compressed!
9419 00:40:53.528253 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9420 00:40:53.531672 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9421 00:40:53.552093 Loading segment from ROM address 0x4010001c
9422 00:40:53.552174 Entry Point 0x80000000
9423 00:40:53.555445 Loaded segments
9424 00:40:53.558891 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9425 00:40:53.564950 Jumping to boot code at 0x80000000(0xffe64000)
9426 00:40:53.571623 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9427 00:40:53.578156 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9428 00:40:53.586362 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9429 00:40:53.589683 Checking segment from ROM address 0x40100000
9430 00:40:53.592847 Checking segment from ROM address 0x4010001c
9431 00:40:53.599432 Loading segment from ROM address 0x40100000
9432 00:40:53.599510 code (compression=1)
9433 00:40:53.606249 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9434 00:40:53.616222 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9435 00:40:53.616303 using LZMA
9436 00:40:53.624741 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9437 00:40:53.631293 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9438 00:40:53.634938 Loading segment from ROM address 0x4010001c
9439 00:40:53.635016 Entry Point 0x54601000
9440 00:40:53.638417 Loaded segments
9441 00:40:53.641573 NOTICE: MT8192 bl31_setup
9442 00:40:53.648289 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9443 00:40:53.651784 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9444 00:40:53.655017 WARNING: region 0:
9445 00:40:53.658187 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9446 00:40:53.658265 WARNING: region 1:
9447 00:40:53.664958 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9448 00:40:53.668194 WARNING: region 2:
9449 00:40:53.671671 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9450 00:40:53.675159 WARNING: region 3:
9451 00:40:53.678326 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9452 00:40:53.681022 WARNING: region 4:
9453 00:40:53.687892 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9454 00:40:53.687994 WARNING: region 5:
9455 00:40:53.691238 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9456 00:40:53.694631 WARNING: region 6:
9457 00:40:53.698029 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9458 00:40:53.701351 WARNING: region 7:
9459 00:40:53.704815 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9460 00:40:53.711142 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9461 00:40:53.714936 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9462 00:40:53.718130 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9463 00:40:53.724626 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9464 00:40:53.727894 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9465 00:40:53.731835 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9466 00:40:53.738028 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9467 00:40:53.741276 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9468 00:40:53.748407 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9469 00:40:53.751602 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9470 00:40:53.754654 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9471 00:40:53.761620 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9472 00:40:53.764751 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9473 00:40:53.767954 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9474 00:40:53.774543 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9475 00:40:53.777886 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9476 00:40:53.785099 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9477 00:40:53.787863 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9478 00:40:53.791277 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9479 00:40:53.798113 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9480 00:40:53.801635 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9481 00:40:53.805101 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9482 00:40:53.811274 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9483 00:40:53.815189 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9484 00:40:53.821614 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9485 00:40:53.824919 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9486 00:40:53.828231 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9487 00:40:53.835007 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9488 00:40:53.838355 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9489 00:40:53.844817 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9490 00:40:53.848202 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9491 00:40:53.851631 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9492 00:40:53.858349 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9493 00:40:53.861461 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9494 00:40:53.865011 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9495 00:40:53.868429 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9496 00:40:53.874808 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9497 00:40:53.878443 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9498 00:40:53.881512 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9499 00:40:53.884912 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9500 00:40:53.888057 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9501 00:40:53.894737 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9502 00:40:53.898008 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9503 00:40:53.901384 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9504 00:40:53.908109 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9505 00:40:53.912131 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9506 00:40:53.914778 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9507 00:40:53.918156 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9508 00:40:53.925238 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9509 00:40:53.928537 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9510 00:40:53.935063 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9511 00:40:53.938397 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9512 00:40:53.941805 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9513 00:40:53.948421 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9514 00:40:53.951778 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9515 00:40:53.958549 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9516 00:40:53.962020 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9517 00:40:53.968109 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9518 00:40:53.971442 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9519 00:40:53.974758 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9520 00:40:53.981400 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9521 00:40:53.984862 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9522 00:40:53.991329 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9523 00:40:53.994993 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9524 00:40:54.001220 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9525 00:40:54.004907 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9526 00:40:54.008090 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9527 00:40:54.015064 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9528 00:40:54.018439 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9529 00:40:54.025382 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9530 00:40:54.028323 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9531 00:40:54.034910 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9532 00:40:54.038073 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9533 00:40:54.041990 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9534 00:40:54.047991 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9535 00:40:54.051195 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9536 00:40:54.058280 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9537 00:40:54.061693 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9538 00:40:54.068529 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9539 00:40:54.071307 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9540 00:40:54.078146 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9541 00:40:54.081456 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9542 00:40:54.084822 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9543 00:40:54.091720 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9544 00:40:54.094375 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9545 00:40:54.101088 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9546 00:40:54.104521 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9547 00:40:54.111361 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9548 00:40:54.114890 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9549 00:40:54.118186 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9550 00:40:54.124585 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9551 00:40:54.127993 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9552 00:40:54.134279 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9553 00:40:54.137622 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9554 00:40:54.144646 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9555 00:40:54.147662 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9556 00:40:54.150922 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9557 00:40:54.157807 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9558 00:40:54.161245 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9559 00:40:54.164389 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9560 00:40:54.167639 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9561 00:40:54.174566 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9562 00:40:54.177887 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9563 00:40:54.184385 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9564 00:40:54.187765 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9565 00:40:54.191141 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9566 00:40:54.197766 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9567 00:40:54.201153 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9568 00:40:54.207386 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9569 00:40:54.210759 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9570 00:40:54.214323 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9571 00:40:54.220952 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9572 00:40:54.224344 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9573 00:40:54.230614 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9574 00:40:54.234066 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9575 00:40:54.237422 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9576 00:40:54.244006 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9577 00:40:54.247366 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9578 00:40:54.250786 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9579 00:40:54.257636 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9580 00:40:54.261009 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9581 00:40:54.263733 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9582 00:40:54.267491 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9583 00:40:54.274244 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9584 00:40:54.277626 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9585 00:40:54.280812 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9586 00:40:54.287244 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9587 00:40:54.290830 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9588 00:40:54.297457 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9589 00:40:54.300656 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9590 00:40:54.303757 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9591 00:40:54.310878 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9592 00:40:54.314030 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9593 00:40:54.317653 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9594 00:40:54.323988 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9595 00:40:54.327222 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9596 00:40:54.334130 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9597 00:40:54.337639 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9598 00:40:54.340977 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9599 00:40:54.347498 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9600 00:40:54.351072 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9601 00:40:54.354415 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9602 00:40:54.361220 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9603 00:40:54.364676 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9604 00:40:54.370726 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9605 00:40:54.374177 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9606 00:40:54.377666 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9607 00:40:54.384678 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9608 00:40:54.387639 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9609 00:40:54.394203 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9610 00:40:54.397498 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9611 00:40:54.400903 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9612 00:40:54.407706 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9613 00:40:54.410552 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9614 00:40:54.413797 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9615 00:40:54.420725 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9616 00:40:54.424279 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9617 00:40:54.430944 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9618 00:40:54.434186 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9619 00:40:54.437330 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9620 00:40:54.444038 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9621 00:40:54.447369 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9622 00:40:54.454159 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9623 00:40:54.457121 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9624 00:40:54.460770 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9625 00:40:54.467656 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9626 00:40:54.470426 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9627 00:40:54.477149 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9628 00:40:54.480532 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9629 00:40:54.483909 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9630 00:40:54.490534 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9631 00:40:54.493939 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9632 00:40:54.497101 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9633 00:40:54.503793 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9634 00:40:54.507282 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9635 00:40:54.514185 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9636 00:40:54.517045 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9637 00:40:54.520893 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9638 00:40:54.527632 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9639 00:40:54.530939 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9640 00:40:54.537015 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9641 00:40:54.540492 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9642 00:40:54.543734 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9643 00:40:54.550320 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9644 00:40:54.553808 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9645 00:40:54.560236 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9646 00:40:54.563979 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9647 00:40:54.567243 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9648 00:40:54.574043 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9649 00:40:54.576986 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9650 00:40:54.583512 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9651 00:40:54.586973 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9652 00:40:54.590487 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9653 00:40:54.596983 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9654 00:40:54.600842 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9655 00:40:54.606920 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9656 00:40:54.610295 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9657 00:40:54.613621 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9658 00:40:54.620448 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9659 00:40:54.623708 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9660 00:40:54.630424 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9661 00:40:54.633642 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9662 00:40:54.637120 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9663 00:40:54.643951 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9664 00:40:54.647268 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9665 00:40:54.654140 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9666 00:40:54.656855 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9667 00:40:54.660221 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9668 00:40:54.667398 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9669 00:40:54.670747 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9670 00:40:54.676966 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9671 00:40:54.680294 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9672 00:40:54.687452 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9673 00:40:54.690634 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9674 00:40:54.693943 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9675 00:40:54.700304 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9676 00:40:54.703894 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9677 00:40:54.710382 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9678 00:40:54.713970 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9679 00:40:54.717294 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9680 00:40:54.723566 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9681 00:40:54.727266 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9682 00:40:54.733882 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9683 00:40:54.737063 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9684 00:40:54.740554 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9685 00:40:54.747426 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9686 00:40:54.750731 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9687 00:40:54.757272 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9688 00:40:54.760631 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9689 00:40:54.764036 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9690 00:40:54.770569 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9691 00:40:54.773810 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9692 00:40:54.777223 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9693 00:40:54.780611 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9694 00:40:54.787434 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9695 00:40:54.790825 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9696 00:40:54.794024 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9697 00:40:54.800847 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9698 00:40:54.804104 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9699 00:40:54.807243 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9700 00:40:54.813783 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9701 00:40:54.817187 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9702 00:40:54.824016 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9703 00:40:54.826806 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9704 00:40:54.830677 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9705 00:40:54.836964 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9706 00:40:54.840410 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9707 00:40:54.843463 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9708 00:40:54.850467 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9709 00:40:54.853942 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9710 00:40:54.857447 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9711 00:40:54.863564 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9712 00:40:54.867095 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9713 00:40:54.870588 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9714 00:40:54.877166 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9715 00:40:54.880352 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9716 00:40:54.886705 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9717 00:40:54.890049 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9718 00:40:54.893406 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9719 00:40:54.900125 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9720 00:40:54.903375 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9721 00:40:54.906889 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9722 00:40:54.913254 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9723 00:40:54.916555 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9724 00:40:54.923135 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9725 00:40:54.926614 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9726 00:40:54.930135 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9727 00:40:54.936831 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9728 00:40:54.940203 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9729 00:40:54.943415 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9730 00:40:54.946784 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9731 00:40:54.953425 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9732 00:40:54.956532 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9733 00:40:54.959708 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9734 00:40:54.963112 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9735 00:40:54.969915 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9736 00:40:54.973234 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9737 00:40:54.976738 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9738 00:40:54.980139 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9739 00:40:54.986626 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9740 00:40:54.989419 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9741 00:40:54.993164 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9742 00:40:54.999851 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9743 00:40:55.003272 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9744 00:40:55.006625 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9745 00:40:55.013380 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9746 00:40:55.016650 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9747 00:40:55.023084 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9748 00:40:55.026480 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9749 00:40:55.029773 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9750 00:40:55.036660 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9751 00:40:55.040145 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9752 00:40:55.046264 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9753 00:40:55.050076 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9754 00:40:55.053238 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9755 00:40:55.059937 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9756 00:40:55.063407 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9757 00:40:55.070255 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9758 00:40:55.073443 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9759 00:40:55.076711 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9760 00:40:55.083285 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9761 00:40:55.086282 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9762 00:40:55.092955 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9763 00:40:55.096334 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9764 00:40:55.102979 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9765 00:40:55.106286 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9766 00:40:55.109754 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9767 00:40:55.116508 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9768 00:40:55.119937 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9769 00:40:55.126505 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9770 00:40:55.129579 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9771 00:40:55.132979 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9772 00:40:55.139842 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9773 00:40:55.143297 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9774 00:40:55.146082 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9775 00:40:55.152892 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9776 00:40:55.156200 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9777 00:40:55.162991 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9778 00:40:55.166415 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9779 00:40:55.172596 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9780 00:40:55.175940 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9781 00:40:55.179138 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9782 00:40:55.186484 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9783 00:40:55.189167 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9784 00:40:55.195842 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9785 00:40:55.199283 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9786 00:40:55.202566 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9787 00:40:55.209382 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9788 00:40:55.213077 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9789 00:40:55.219029 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9790 00:40:55.222701 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9791 00:40:55.226220 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9792 00:40:55.232642 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9793 00:40:55.235744 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9794 00:40:55.242746 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9795 00:40:55.245878 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9796 00:40:55.252336 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9797 00:40:55.255893 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9798 00:40:55.259299 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9799 00:40:55.265690 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9800 00:40:55.269023 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9801 00:40:55.275644 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9802 00:40:55.279017 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9803 00:40:55.282338 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9804 00:40:55.289033 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9805 00:40:55.292676 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9806 00:40:55.295769 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9807 00:40:55.302721 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9808 00:40:55.306087 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9809 00:40:55.312296 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9810 00:40:55.315493 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9811 00:40:55.322733 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9812 00:40:55.326026 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9813 00:40:55.328873 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9814 00:40:55.335628 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9815 00:40:55.338865 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9816 00:40:55.345598 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9817 00:40:55.348982 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9818 00:40:55.355249 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9819 00:40:55.359146 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9820 00:40:55.365586 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9821 00:40:55.368665 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9822 00:40:55.371879 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9823 00:40:55.379191 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9824 00:40:55.382436 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9825 00:40:55.389049 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9826 00:40:55.392338 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9827 00:40:55.398460 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9828 00:40:55.402316 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9829 00:40:55.405464 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9830 00:40:55.412328 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9831 00:40:55.415070 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9832 00:40:55.421774 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9833 00:40:55.425652 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9834 00:40:55.432218 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9835 00:40:55.435617 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9836 00:40:55.438301 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9837 00:40:55.445073 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9838 00:40:55.448515 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9839 00:40:55.455156 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9840 00:40:55.458557 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9841 00:40:55.465028 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9842 00:40:55.468229 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9843 00:40:55.471767 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9844 00:40:55.478064 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9845 00:40:55.481497 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9846 00:40:55.488200 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9847 00:40:55.491604 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9848 00:40:55.498340 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9849 00:40:55.501761 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9850 00:40:55.504723 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9851 00:40:55.511817 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9852 00:40:55.515236 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9853 00:40:55.521953 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9854 00:40:55.525300 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9855 00:40:55.531918 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9856 00:40:55.535058 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9857 00:40:55.538557 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9858 00:40:55.544690 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9859 00:40:55.548094 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9860 00:40:55.554993 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9861 00:40:55.558212 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9862 00:40:55.561321 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9863 00:40:55.567995 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9864 00:40:55.571317 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9865 00:40:55.578118 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9866 00:40:55.581662 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9867 00:40:55.588559 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9868 00:40:55.591663 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9869 00:40:55.598355 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9870 00:40:55.601751 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9871 00:40:55.608627 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9872 00:40:55.611823 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9873 00:40:55.618083 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9874 00:40:55.621834 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9875 00:40:55.628445 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9876 00:40:55.631507 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9877 00:40:55.634995 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9878 00:40:55.641614 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9879 00:40:55.645456 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9880 00:40:55.651502 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9881 00:40:55.654943 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9882 00:40:55.661691 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9883 00:40:55.664959 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9884 00:40:55.671600 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9885 00:40:55.675040 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9886 00:40:55.681867 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9887 00:40:55.685339 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9888 00:40:55.692043 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9889 00:40:55.695333 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9890 00:40:55.701835 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9891 00:40:55.704818 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9892 00:40:55.711379 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9893 00:40:55.714748 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9894 00:40:55.721622 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9895 00:40:55.721716 INFO: [APUAPC] vio 0
9896 00:40:55.728270 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9897 00:40:55.731501 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9898 00:40:55.735056 INFO: [APUAPC] D0_APC_0: 0x400510
9899 00:40:55.738113 INFO: [APUAPC] D0_APC_1: 0x0
9900 00:40:55.741614 INFO: [APUAPC] D0_APC_2: 0x1540
9901 00:40:55.744631 INFO: [APUAPC] D0_APC_3: 0x0
9902 00:40:55.748033 INFO: [APUAPC] D1_APC_0: 0xffffffff
9903 00:40:55.751705 INFO: [APUAPC] D1_APC_1: 0xffffffff
9904 00:40:55.754698 INFO: [APUAPC] D1_APC_2: 0x3fffff
9905 00:40:55.758227 INFO: [APUAPC] D1_APC_3: 0x0
9906 00:40:55.761643 INFO: [APUAPC] D2_APC_0: 0xffffffff
9907 00:40:55.765134 INFO: [APUAPC] D2_APC_1: 0xffffffff
9908 00:40:55.768675 INFO: [APUAPC] D2_APC_2: 0x3fffff
9909 00:40:55.771858 INFO: [APUAPC] D2_APC_3: 0x0
9910 00:40:55.775055 INFO: [APUAPC] D3_APC_0: 0xffffffff
9911 00:40:55.778391 INFO: [APUAPC] D3_APC_1: 0xffffffff
9912 00:40:55.781875 INFO: [APUAPC] D3_APC_2: 0x3fffff
9913 00:40:55.781950 INFO: [APUAPC] D3_APC_3: 0x0
9914 00:40:55.784781 INFO: [APUAPC] D4_APC_0: 0xffffffff
9915 00:40:55.791305 INFO: [APUAPC] D4_APC_1: 0xffffffff
9916 00:40:55.791383 INFO: [APUAPC] D4_APC_2: 0x3fffff
9917 00:40:55.795266 INFO: [APUAPC] D4_APC_3: 0x0
9918 00:40:55.797984 INFO: [APUAPC] D5_APC_0: 0xffffffff
9919 00:40:55.801299 INFO: [APUAPC] D5_APC_1: 0xffffffff
9920 00:40:55.804644 INFO: [APUAPC] D5_APC_2: 0x3fffff
9921 00:40:55.808072 INFO: [APUAPC] D5_APC_3: 0x0
9922 00:40:55.811314 INFO: [APUAPC] D6_APC_0: 0xffffffff
9923 00:40:55.814921 INFO: [APUAPC] D6_APC_1: 0xffffffff
9924 00:40:55.818020 INFO: [APUAPC] D6_APC_2: 0x3fffff
9925 00:40:55.821346 INFO: [APUAPC] D6_APC_3: 0x0
9926 00:40:55.824795 INFO: [APUAPC] D7_APC_0: 0xffffffff
9927 00:40:55.828193 INFO: [APUAPC] D7_APC_1: 0xffffffff
9928 00:40:55.831746 INFO: [APUAPC] D7_APC_2: 0x3fffff
9929 00:40:55.835023 INFO: [APUAPC] D7_APC_3: 0x0
9930 00:40:55.838401 INFO: [APUAPC] D8_APC_0: 0xffffffff
9931 00:40:55.841797 INFO: [APUAPC] D8_APC_1: 0xffffffff
9932 00:40:55.845199 INFO: [APUAPC] D8_APC_2: 0x3fffff
9933 00:40:55.848611 INFO: [APUAPC] D8_APC_3: 0x0
9934 00:40:55.851877 INFO: [APUAPC] D9_APC_0: 0xffffffff
9935 00:40:55.854834 INFO: [APUAPC] D9_APC_1: 0xffffffff
9936 00:40:55.858070 INFO: [APUAPC] D9_APC_2: 0x3fffff
9937 00:40:55.861360 INFO: [APUAPC] D9_APC_3: 0x0
9938 00:40:55.864737 INFO: [APUAPC] D10_APC_0: 0xffffffff
9939 00:40:55.868548 INFO: [APUAPC] D10_APC_1: 0xffffffff
9940 00:40:55.871604 INFO: [APUAPC] D10_APC_2: 0x3fffff
9941 00:40:55.874582 INFO: [APUAPC] D10_APC_3: 0x0
9942 00:40:55.878637 INFO: [APUAPC] D11_APC_0: 0xffffffff
9943 00:40:55.881339 INFO: [APUAPC] D11_APC_1: 0xffffffff
9944 00:40:55.884761 INFO: [APUAPC] D11_APC_2: 0x3fffff
9945 00:40:55.888328 INFO: [APUAPC] D11_APC_3: 0x0
9946 00:40:55.891672 INFO: [APUAPC] D12_APC_0: 0xffffffff
9947 00:40:55.894493 INFO: [APUAPC] D12_APC_1: 0xffffffff
9948 00:40:55.897879 INFO: [APUAPC] D12_APC_2: 0x3fffff
9949 00:40:55.901386 INFO: [APUAPC] D12_APC_3: 0x0
9950 00:40:55.904735 INFO: [APUAPC] D13_APC_0: 0xffffffff
9951 00:40:55.908000 INFO: [APUAPC] D13_APC_1: 0xffffffff
9952 00:40:55.911464 INFO: [APUAPC] D13_APC_2: 0x3fffff
9953 00:40:55.914867 INFO: [APUAPC] D13_APC_3: 0x0
9954 00:40:55.918285 INFO: [APUAPC] D14_APC_0: 0xffffffff
9955 00:40:55.921621 INFO: [APUAPC] D14_APC_1: 0xffffffff
9956 00:40:55.924775 INFO: [APUAPC] D14_APC_2: 0x3fffff
9957 00:40:55.927926 INFO: [APUAPC] D14_APC_3: 0x0
9958 00:40:55.931300 INFO: [APUAPC] D15_APC_0: 0xffffffff
9959 00:40:55.934631 INFO: [APUAPC] D15_APC_1: 0xffffffff
9960 00:40:55.937936 INFO: [APUAPC] D15_APC_2: 0x3fffff
9961 00:40:55.941345 INFO: [APUAPC] D15_APC_3: 0x0
9962 00:40:55.944765 INFO: [APUAPC] APC_CON: 0x4
9963 00:40:55.948103 INFO: [NOCDAPC] D0_APC_0: 0x0
9964 00:40:55.951382 INFO: [NOCDAPC] D0_APC_1: 0x0
9965 00:40:55.951459 INFO: [NOCDAPC] D1_APC_0: 0x0
9966 00:40:55.954701 INFO: [NOCDAPC] D1_APC_1: 0xfff
9967 00:40:55.958005 INFO: [NOCDAPC] D2_APC_0: 0x0
9968 00:40:55.961144 INFO: [NOCDAPC] D2_APC_1: 0xfff
9969 00:40:55.964196 INFO: [NOCDAPC] D3_APC_0: 0x0
9970 00:40:55.967933 INFO: [NOCDAPC] D3_APC_1: 0xfff
9971 00:40:55.971197 INFO: [NOCDAPC] D4_APC_0: 0x0
9972 00:40:55.974616 INFO: [NOCDAPC] D4_APC_1: 0xfff
9973 00:40:55.977905 INFO: [NOCDAPC] D5_APC_0: 0x0
9974 00:40:55.981162 INFO: [NOCDAPC] D5_APC_1: 0xfff
9975 00:40:55.984393 INFO: [NOCDAPC] D6_APC_0: 0x0
9976 00:40:55.984471 INFO: [NOCDAPC] D6_APC_1: 0xfff
9977 00:40:55.987691 INFO: [NOCDAPC] D7_APC_0: 0x0
9978 00:40:55.990895 INFO: [NOCDAPC] D7_APC_1: 0xfff
9979 00:40:55.994181 INFO: [NOCDAPC] D8_APC_0: 0x0
9980 00:40:55.997607 INFO: [NOCDAPC] D8_APC_1: 0xfff
9981 00:40:56.001116 INFO: [NOCDAPC] D9_APC_0: 0x0
9982 00:40:56.004493 INFO: [NOCDAPC] D9_APC_1: 0xfff
9983 00:40:56.007803 INFO: [NOCDAPC] D10_APC_0: 0x0
9984 00:40:56.010965 INFO: [NOCDAPC] D10_APC_1: 0xfff
9985 00:40:56.014308 INFO: [NOCDAPC] D11_APC_0: 0x0
9986 00:40:56.017692 INFO: [NOCDAPC] D11_APC_1: 0xfff
9987 00:40:56.021088 INFO: [NOCDAPC] D12_APC_0: 0x0
9988 00:40:56.021162 INFO: [NOCDAPC] D12_APC_1: 0xfff
9989 00:40:56.024497 INFO: [NOCDAPC] D13_APC_0: 0x0
9990 00:40:56.027901 INFO: [NOCDAPC] D13_APC_1: 0xfff
9991 00:40:56.031183 INFO: [NOCDAPC] D14_APC_0: 0x0
9992 00:40:56.034415 INFO: [NOCDAPC] D14_APC_1: 0xfff
9993 00:40:56.037506 INFO: [NOCDAPC] D15_APC_0: 0x0
9994 00:40:56.040636 INFO: [NOCDAPC] D15_APC_1: 0xfff
9995 00:40:56.044573 INFO: [NOCDAPC] APC_CON: 0x4
9996 00:40:56.047361 INFO: [APUAPC] set_apusys_apc done
9997 00:40:56.050757 INFO: [DEVAPC] devapc_init done
9998 00:40:56.054046 INFO: GICv3 without legacy support detected.
9999 00:40:56.057451 INFO: ARM GICv3 driver initialized in EL3
10000 00:40:56.060872 INFO: Maximum SPI INTID supported: 639
10001 00:40:56.067597 INFO: BL31: Initializing runtime services
10002 00:40:56.071007 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10003 00:40:56.074271 INFO: SPM: enable CPC mode
10004 00:40:56.081075 INFO: mcdi ready for mcusys-off-idle and system suspend
10005 00:40:56.083999 INFO: BL31: Preparing for EL3 exit to normal world
10006 00:40:56.087908 INFO: Entry point address = 0x80000000
10007 00:40:56.091023 INFO: SPSR = 0x8
10008 00:40:56.096328
10009 00:40:56.096436
10010 00:40:56.096493
10011 00:40:56.099827 Starting depthcharge on Spherion...
10012 00:40:56.099930
10013 00:40:56.099988 Wipe memory regions:
10014 00:40:56.100042
10015 00:40:56.100734 end: 2.2.3 depthcharge-start (duration 00:00:31) [common]
10016 00:40:56.100827 start: 2.2.4 bootloader-commands (timeout 00:04:20) [common]
10017 00:40:56.100920 Setting prompt string to ['asurada:']
10018 00:40:56.100995 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:20)
10019 00:40:56.103081 [0x00000040000000, 0x00000054600000)
10020 00:40:56.225490
10021 00:40:56.225616 [0x00000054660000, 0x00000080000000)
10022 00:40:56.485752
10023 00:40:56.485871 [0x000000821a7280, 0x000000ffe64000)
10024 00:40:57.230781
10025 00:40:57.230907 [0x00000100000000, 0x00000240000000)
10026 00:40:59.121079
10027 00:40:59.124425 Initializing XHCI USB controller at 0x11200000.
10028 00:41:00.162540
10029 00:41:00.166019 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10030 00:41:00.166098
10031 00:41:00.166196
10032 00:41:00.166463 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10034 00:41:00.266799 asurada: tftpboot 192.168.201.1 14368365/tftp-deploy-tu_dj_f6/kernel/image.itb 14368365/tftp-deploy-tu_dj_f6/kernel/cmdline
10035 00:41:00.266972 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10036 00:41:00.267054 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:16)
10037 00:41:00.271640 tftpboot 192.168.201.1 14368365/tftp-deploy-tu_dj_f6/kernel/image.itp-deploy-tu_dj_f6/kernel/cmdline
10038 00:41:00.271718
10039 00:41:00.271778 Waiting for link
10040 00:41:00.429950
10041 00:41:00.430266 R8152: Initializing
10042 00:41:00.430484
10043 00:41:00.433443 Version 9 (ocp_data = 6010)
10044 00:41:00.433773
10045 00:41:00.435993 R8152: Done initializing
10046 00:41:00.436270
10047 00:41:00.436488 Adding net device
10048 00:41:02.384523
10049 00:41:02.384955 done.
10050 00:41:02.385317
10051 00:41:02.385675 MAC: 00:e0:4c:78:7a:aa
10052 00:41:02.386167
10053 00:41:02.387785 Sending DHCP discover... done.
10054 00:41:02.388172
10055 00:41:02.391070 Waiting for reply... done.
10056 00:41:02.391586
10057 00:41:02.394497 Sending DHCP request... done.
10058 00:41:02.394884
10059 00:41:02.397952 Waiting for reply... done.
10060 00:41:02.398342
10061 00:41:02.398644 My ip is 192.168.201.12
10062 00:41:02.398927
10063 00:41:02.401263 The DHCP server ip is 192.168.201.1
10064 00:41:02.401691
10065 00:41:02.408053 TFTP server IP predefined by user: 192.168.201.1
10066 00:41:02.408446
10067 00:41:02.414407 Bootfile predefined by user: 14368365/tftp-deploy-tu_dj_f6/kernel/image.itb
10068 00:41:02.414841
10069 00:41:02.415151 Sending tftp read request... done.
10070 00:41:02.417446
10071 00:41:02.424351 Waiting for the transfer...
10072 00:41:02.424753
10073 00:41:02.717977 00000000 ################################################################
10074 00:41:02.718107
10075 00:41:02.976902 00080000 ################################################################
10076 00:41:02.977013
10077 00:41:03.240185 00100000 ################################################################
10078 00:41:03.240326
10079 00:41:03.516749 00180000 ################################################################
10080 00:41:03.516863
10081 00:41:03.779282 00200000 ################################################################
10082 00:41:03.779395
10083 00:41:04.044962 00280000 ################################################################
10084 00:41:04.045094
10085 00:41:04.306863 00300000 ################################################################
10086 00:41:04.306981
10087 00:41:04.556974 00380000 ################################################################
10088 00:41:04.557085
10089 00:41:04.807588 00400000 ################################################################
10090 00:41:04.807702
10091 00:41:05.060216 00480000 ################################################################
10092 00:41:05.060370
10093 00:41:05.327153 00500000 ################################################################
10094 00:41:05.327285
10095 00:41:05.589784 00580000 ################################################################
10096 00:41:05.589914
10097 00:41:05.859993 00600000 ################################################################
10098 00:41:05.860139
10099 00:41:06.124988 00680000 ################################################################
10100 00:41:06.125141
10101 00:41:06.402372 00700000 ################################################################
10102 00:41:06.402501
10103 00:41:06.678228 00780000 ################################################################
10104 00:41:06.678351
10105 00:41:06.941503 00800000 ################################################################
10106 00:41:06.941683
10107 00:41:07.202031 00880000 ################################################################
10108 00:41:07.202140
10109 00:41:07.466753 00900000 ################################################################
10110 00:41:07.466881
10111 00:41:07.735373 00980000 ################################################################
10112 00:41:07.735485
10113 00:41:07.991898 00a00000 ################################################################
10114 00:41:07.992039
10115 00:41:08.249335 00a80000 ################################################################
10116 00:41:08.249457
10117 00:41:08.513720 00b00000 ################################################################
10118 00:41:08.513836
10119 00:41:08.792256 00b80000 ################################################################
10120 00:41:08.792367
10121 00:41:09.055407 00c00000 ################################################################
10122 00:41:09.055532
10123 00:41:09.332298 00c80000 ################################################################
10124 00:41:09.332442
10125 00:41:09.626061 00d00000 ################################################################
10126 00:41:09.626171
10127 00:41:09.908687 00d80000 ################################################################
10128 00:41:09.908827
10129 00:41:10.180529 00e00000 ################################################################
10130 00:41:10.180640
10131 00:41:10.457375 00e80000 ################################################################
10132 00:41:10.457489
10133 00:41:10.728675 00f00000 ################################################################
10134 00:41:10.728801
10135 00:41:11.019325 00f80000 ################################################################
10136 00:41:11.019461
10137 00:41:11.307760 01000000 ################################################################
10138 00:41:11.307903
10139 00:41:11.594333 01080000 ################################################################
10140 00:41:11.594455
10141 00:41:11.863273 01100000 ################################################################
10142 00:41:11.863396
10143 00:41:12.146865 01180000 ################################################################
10144 00:41:12.146980
10145 00:41:12.418799 01200000 ################################################################
10146 00:41:12.418918
10147 00:41:12.714618 01280000 ################################################################
10148 00:41:12.714735
10149 00:41:12.968144 01300000 ################################################################
10150 00:41:12.968294
10151 00:41:13.241606 01380000 ################################################################
10152 00:41:13.241740
10153 00:41:13.499352 01400000 ################################################################
10154 00:41:13.499493
10155 00:41:13.751552 01480000 ################################################################
10156 00:41:13.751662
10157 00:41:14.011756 01500000 ################################################################
10158 00:41:14.011885
10159 00:41:14.275388 01580000 ################################################################
10160 00:41:14.275500
10161 00:41:14.526461 01600000 ################################################################
10162 00:41:14.526587
10163 00:41:14.781432 01680000 ################################################################
10164 00:41:14.781564
10165 00:41:15.033118 01700000 ################################################################
10166 00:41:15.033243
10167 00:41:15.331451 01780000 ################################################################
10168 00:41:15.331572
10169 00:41:15.628769 01800000 ################################################################
10170 00:41:15.628887
10171 00:41:15.899223 01880000 ################################################################
10172 00:41:15.899337
10173 00:41:16.166167 01900000 ################################################################
10174 00:41:16.166303
10175 00:41:16.422567 01980000 ################################################################
10176 00:41:16.422689
10177 00:41:16.686332 01a00000 ################################################################
10178 00:41:16.686497
10179 00:41:16.954523 01a80000 ################################################################
10180 00:41:16.954638
10181 00:41:17.223569 01b00000 ################################################################
10182 00:41:17.223686
10183 00:41:17.485314 01b80000 ################################################################
10184 00:41:17.485426
10185 00:41:17.736651 01c00000 ################################################################
10186 00:41:17.736765
10187 00:41:17.992959 01c80000 ################################################################
10188 00:41:17.993098
10189 00:41:18.261066 01d00000 ################################################################
10190 00:41:18.261191
10191 00:41:18.553711 01d80000 ################################################################
10192 00:41:18.553833
10193 00:41:18.835028 01e00000 ################################################################
10194 00:41:18.835153
10195 00:41:19.121646 01e80000 ################################################################
10196 00:41:19.121756
10197 00:41:19.378252 01f00000 ################################################################
10198 00:41:19.378380
10199 00:41:19.636639 01f80000 ################################################################
10200 00:41:19.636750
10201 00:41:19.900001 02000000 ################################################################
10202 00:41:19.900114
10203 00:41:20.155416 02080000 ################################################################
10204 00:41:20.155530
10205 00:41:20.423417 02100000 ################################################################
10206 00:41:20.423533
10207 00:41:20.683978 02180000 ################################################################
10208 00:41:20.684088
10209 00:41:20.943746 02200000 ################################################################
10210 00:41:20.943861
10211 00:41:21.196965 02280000 ################################################################
10212 00:41:21.197115
10213 00:41:21.450386 02300000 ################################################################
10214 00:41:21.450524
10215 00:41:21.706483 02380000 ################################################################
10216 00:41:21.706594
10217 00:41:21.976002 02400000 ################################################################
10218 00:41:21.976131
10219 00:41:22.246541 02480000 ################################################################
10220 00:41:22.246684
10221 00:41:22.495690 02500000 ################################################################
10222 00:41:22.495814
10223 00:41:22.764319 02580000 ################################################################
10224 00:41:22.764431
10225 00:41:23.017748 02600000 ################################################################
10226 00:41:23.017876
10227 00:41:23.274884 02680000 ################################################################
10228 00:41:23.275009
10229 00:41:23.539054 02700000 ################################################################
10230 00:41:23.539216
10231 00:41:23.800671 02780000 ################################################################
10232 00:41:23.800808
10233 00:41:24.063061 02800000 ################################################################
10234 00:41:24.063175
10235 00:41:24.320645 02880000 ################################################################
10236 00:41:24.320767
10237 00:41:24.585115 02900000 ################################################################
10238 00:41:24.585228
10239 00:41:24.836136 02980000 ################################################################
10240 00:41:24.836249
10241 00:41:25.090063 02a00000 ################################################################
10242 00:41:25.090175
10243 00:41:25.340396 02a80000 ################################################################
10244 00:41:25.340532
10245 00:41:25.608870 02b00000 ################################################################
10246 00:41:25.609028
10247 00:41:25.866764 02b80000 ################################################################
10248 00:41:25.866874
10249 00:41:26.127072 02c00000 ################################################################
10250 00:41:26.127182
10251 00:41:26.395143 02c80000 ################################################################
10252 00:41:26.395254
10253 00:41:26.652135 02d00000 ################################################################
10254 00:41:26.652282
10255 00:41:26.918804 02d80000 ################################################################
10256 00:41:26.918936
10257 00:41:27.197992 02e00000 ################################################################
10258 00:41:27.198102
10259 00:41:27.461755 02e80000 ################################################################
10260 00:41:27.461880
10261 00:41:27.709774 02f00000 ################################################################
10262 00:41:27.709895
10263 00:41:27.960882 02f80000 ################################################################
10264 00:41:27.961030
10265 00:41:28.209298 03000000 ################################################################
10266 00:41:28.209473
10267 00:41:28.472122 03080000 ################################################################
10268 00:41:28.472257
10269 00:41:28.729517 03100000 ################################################################
10270 00:41:28.729682
10271 00:41:28.987519 03180000 ################################################################
10272 00:41:28.987632
10273 00:41:29.251022 03200000 ################################################################
10274 00:41:29.251141
10275 00:41:29.523936 03280000 ################################################################
10276 00:41:29.524060
10277 00:41:29.780536 03300000 ################################################################
10278 00:41:29.780654
10279 00:41:30.042217 03380000 ################################################################
10280 00:41:30.042342
10281 00:41:30.306908 03400000 ################################################################
10282 00:41:30.307027
10283 00:41:30.580578 03480000 ################################################################
10284 00:41:30.580696
10285 00:41:30.845347 03500000 ################################################################
10286 00:41:30.845478
10287 00:41:31.111837 03580000 ################################################################
10288 00:41:31.111957
10289 00:41:31.362713 03600000 ################################################################
10290 00:41:31.362841
10291 00:41:31.639580 03680000 ################################################################
10292 00:41:31.639696
10293 00:41:31.905377 03700000 ################################################################
10294 00:41:31.905489
10295 00:41:32.182984 03780000 ################################################################
10296 00:41:32.183133
10297 00:41:32.456697 03800000 ################################################################
10298 00:41:32.456828
10299 00:41:32.717444 03880000 ################################################################
10300 00:41:32.717598
10301 00:41:32.985967 03900000 ################################################################
10302 00:41:32.986095
10303 00:41:33.246989 03980000 ################################################################
10304 00:41:33.247114
10305 00:41:33.525360 03a00000 ################################################################
10306 00:41:33.525482
10307 00:41:33.809293 03a80000 ################################################################
10308 00:41:33.809432
10309 00:41:34.076021 03b00000 ################################################################
10310 00:41:34.076145
10311 00:41:34.357072 03b80000 ################################################################
10312 00:41:34.357213
10313 00:41:34.610916 03c00000 ################################################################
10314 00:41:34.611039
10315 00:41:34.879670 03c80000 ################################################################
10316 00:41:34.879784
10317 00:41:35.137088 03d00000 ################################################################
10318 00:41:35.137206
10319 00:41:35.426156 03d80000 ################################################################
10320 00:41:35.426304
10321 00:41:35.724904 03e00000 ################################################################
10322 00:41:35.725028
10323 00:41:36.067193 03e80000 ################################################################
10324 00:41:36.067309
10325 00:41:36.355533 03f00000 ################################################################
10326 00:41:36.355664
10327 00:41:36.646251 03f80000 ################################################################
10328 00:41:36.646383
10329 00:41:36.936761 04000000 ################################################################
10330 00:41:36.936881
10331 00:41:37.184578 04080000 ################################################################
10332 00:41:37.184704
10333 00:41:37.449823 04100000 ################################################################
10334 00:41:37.449946
10335 00:41:37.727525 04180000 ################################################################
10336 00:41:37.727647
10337 00:41:38.020419 04200000 ################################################################
10338 00:41:38.020570
10339 00:41:38.299796 04280000 ################################################################
10340 00:41:38.299920
10341 00:41:38.563182 04300000 ################################################################
10342 00:41:38.563305
10343 00:41:38.831204 04380000 ################################################################
10344 00:41:38.831325
10345 00:41:39.101537 04400000 ################################################################
10346 00:41:39.101684
10347 00:41:39.388111 04480000 ################################################################
10348 00:41:39.388255
10349 00:41:39.674727 04500000 ################################################################
10350 00:41:39.674852
10351 00:41:39.964293 04580000 ################################################################
10352 00:41:39.964417
10353 00:41:40.246428 04600000 ################################################################
10354 00:41:40.246549
10355 00:41:40.377869 04680000 ################################ done.
10356 00:41:40.377996
10357 00:41:40.381036 The bootfile was 74183802 bytes long.
10358 00:41:40.381120
10359 00:41:40.384254 Sending tftp read request... done.
10360 00:41:40.384368
10361 00:41:40.384456 Waiting for the transfer...
10362 00:41:40.384539
10363 00:41:40.387958 00000000 # done.
10364 00:41:40.388056
10365 00:41:40.394500 Command line loaded dynamically from TFTP file: 14368365/tftp-deploy-tu_dj_f6/kernel/cmdline
10366 00:41:40.394606
10367 00:41:40.408038 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10368 00:41:40.408253
10369 00:41:40.410863 Loading FIT.
10370 00:41:40.411022
10371 00:41:40.414255 Image ramdisk-1 has 61008144 bytes.
10372 00:41:40.414419
10373 00:41:40.414541 Image fdt-1 has 47258 bytes.
10374 00:41:40.414655
10375 00:41:40.417772 Image kernel-1 has 13126376 bytes.
10376 00:41:40.418026
10377 00:41:40.427735 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10378 00:41:40.428089
10379 00:41:40.444408 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10380 00:41:40.444923
10381 00:41:40.450997 Choosing best match conf-1 for compat google,spherion-rev2.
10382 00:41:40.455174
10383 00:41:40.459628 Connected to device vid:did:rid of 1ae0:0028:00
10384 00:41:40.467631
10385 00:41:40.471433 tpm_get_response: command 0x17b, return code 0x0
10386 00:41:40.471832
10387 00:41:40.474239 ec_init: CrosEC protocol v3 supported (256, 248)
10388 00:41:40.478533
10389 00:41:40.481729 tpm_cleanup: add release locality here.
10390 00:41:40.482115
10391 00:41:40.482410 Shutting down all USB controllers.
10392 00:41:40.484847
10393 00:41:40.485225 Removing current net device
10394 00:41:40.485519
10395 00:41:40.491596 Exiting depthcharge with code 4 at timestamp: 73653014
10396 00:41:40.491978
10397 00:41:40.494935 LZMA decompressing kernel-1 to 0x821a6718
10398 00:41:40.495315
10399 00:41:40.498429 LZMA decompressing kernel-1 to 0x40000000
10400 00:41:42.115310
10401 00:41:42.115856 jumping to kernel
10402 00:41:42.118198 end: 2.2.4 bootloader-commands (duration 00:00:46) [common]
10403 00:41:42.118741 start: 2.2.5 auto-login-action (timeout 00:03:34) [common]
10404 00:41:42.119114 Setting prompt string to ['Linux version [0-9]']
10405 00:41:42.119457 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10406 00:41:42.119801 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10407 00:41:42.197403
10408 00:41:42.201135 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10409 00:41:42.204788 start: 2.2.5.1 login-action (timeout 00:03:34) [common]
10410 00:41:42.205364 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10411 00:41:42.205897 Setting prompt string to []
10412 00:41:42.206307 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10413 00:41:42.206738 Using line separator: #'\n'#
10414 00:41:42.207068 No login prompt set.
10415 00:41:42.207409 Parsing kernel messages
10416 00:41:42.207728 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10417 00:41:42.208268 [login-action] Waiting for messages, (timeout 00:03:34)
10418 00:41:42.208617 Waiting using forced prompt support (timeout 00:01:47)
10419 00:41:42.224075 [ 0.000000] Linux version 6.1.92-cip22 (KernelCI@build-j232175-arm64-gcc-10-defconfig-arm64-chromebook-7lg8d) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sun Jun 16 00:28:47 UTC 2024
10420 00:41:42.227567 [ 0.000000] random: crng init done
10421 00:41:42.233539 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10422 00:41:42.237270 [ 0.000000] efi: UEFI not found.
10423 00:41:42.243498 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10424 00:41:42.250600 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10425 00:41:42.260014 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10426 00:41:42.270213 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10427 00:41:42.277124 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10428 00:41:42.283185 [ 0.000000] printk: bootconsole [mtk8250] enabled
10429 00:41:42.290355 [ 0.000000] NUMA: No NUMA configuration found
10430 00:41:42.296490 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10431 00:41:42.300456 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10432 00:41:42.303553 [ 0.000000] Zone ranges:
10433 00:41:42.309911 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10434 00:41:42.312973 [ 0.000000] DMA32 empty
10435 00:41:42.319863 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10436 00:41:42.323044 [ 0.000000] Movable zone start for each node
10437 00:41:42.326700 [ 0.000000] Early memory node ranges
10438 00:41:42.333071 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10439 00:41:42.339671 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10440 00:41:42.346830 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10441 00:41:42.353304 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10442 00:41:42.356291 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10443 00:41:42.365827 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10444 00:41:42.422519 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10445 00:41:42.428593 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10446 00:41:42.435842 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10447 00:41:42.438936 [ 0.000000] psci: probing for conduit method from DT.
10448 00:41:42.445351 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10449 00:41:42.449248 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10450 00:41:42.455575 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10451 00:41:42.458862 [ 0.000000] psci: SMC Calling Convention v1.2
10452 00:41:42.465672 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10453 00:41:42.468931 [ 0.000000] Detected VIPT I-cache on CPU0
10454 00:41:42.475335 [ 0.000000] CPU features: detected: GIC system register CPU interface
10455 00:41:42.482096 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10456 00:41:42.488491 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10457 00:41:42.495121 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10458 00:41:42.501482 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10459 00:41:42.511687 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10460 00:41:42.514716 [ 0.000000] alternatives: applying boot alternatives
10461 00:41:42.521509 [ 0.000000] Fallback order for Node 0: 0
10462 00:41:42.528317 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10463 00:41:42.531227 [ 0.000000] Policy zone: Normal
10464 00:41:42.544698 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10465 00:41:42.555007 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10466 00:41:42.566859 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10467 00:41:42.576801 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10468 00:41:42.582936 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10469 00:41:42.586265 <6>[ 0.000000] software IO TLB: area num 8.
10470 00:41:42.642787 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10471 00:41:42.792168 <6>[ 0.000000] Memory: 7904484K/8385536K available (18112K kernel code, 4120K rwdata, 22644K rodata, 8512K init, 616K bss, 448284K reserved, 32768K cma-reserved)
10472 00:41:42.798967 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10473 00:41:42.805734 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10474 00:41:42.808870 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10475 00:41:42.815871 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10476 00:41:42.822015 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10477 00:41:42.825423 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10478 00:41:42.835688 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10479 00:41:42.841845 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10480 00:41:42.845775 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10481 00:41:42.853063 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10482 00:41:42.856237 <6>[ 0.000000] GICv3: 608 SPIs implemented
10483 00:41:42.863586 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10484 00:41:42.866500 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10485 00:41:42.869861 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10486 00:41:42.879408 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10487 00:41:42.889380 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10488 00:41:42.902894 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10489 00:41:42.909374 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10490 00:41:42.918978 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10491 00:41:42.932218 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10492 00:41:42.938856 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10493 00:41:42.945340 <6>[ 0.009230] Console: colour dummy device 80x25
10494 00:41:42.955901 <6>[ 0.013989] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10495 00:41:42.958541 <6>[ 0.024432] pid_max: default: 32768 minimum: 301
10496 00:41:42.965705 <6>[ 0.029303] LSM: Security Framework initializing
10497 00:41:42.972128 <6>[ 0.034270] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10498 00:41:42.981848 <6>[ 0.042084] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10499 00:41:42.988760 <6>[ 0.051500] cblist_init_generic: Setting adjustable number of callback queues.
10500 00:41:42.994984 <6>[ 0.058944] cblist_init_generic: Setting shift to 3 and lim to 1.
10501 00:41:43.004971 <6>[ 0.065284] cblist_init_generic: Setting adjustable number of callback queues.
10502 00:41:43.008352 <6>[ 0.072711] cblist_init_generic: Setting shift to 3 and lim to 1.
10503 00:41:43.015147 <6>[ 0.079111] rcu: Hierarchical SRCU implementation.
10504 00:41:43.021318 <6>[ 0.084126] rcu: Max phase no-delay instances is 1000.
10505 00:41:43.028221 <6>[ 0.091146] EFI services will not be available.
10506 00:41:43.031496 <6>[ 0.096103] smp: Bringing up secondary CPUs ...
10507 00:41:43.039786 <6>[ 0.101183] Detected VIPT I-cache on CPU1
10508 00:41:43.046334 <6>[ 0.101253] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10509 00:41:43.052898 <6>[ 0.101286] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10510 00:41:43.056404 <6>[ 0.101623] Detected VIPT I-cache on CPU2
10511 00:41:43.063540 <6>[ 0.101676] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10512 00:41:43.069959 <6>[ 0.101696] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10513 00:41:43.076163 <6>[ 0.101957] Detected VIPT I-cache on CPU3
10514 00:41:43.082611 <6>[ 0.102007] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10515 00:41:43.089533 <6>[ 0.102022] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10516 00:41:43.092646 <6>[ 0.102327] CPU features: detected: Spectre-v4
10517 00:41:43.099203 <6>[ 0.102333] CPU features: detected: Spectre-BHB
10518 00:41:43.102946 <6>[ 0.102338] Detected PIPT I-cache on CPU4
10519 00:41:43.109621 <6>[ 0.102400] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10520 00:41:43.115865 <6>[ 0.102416] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10521 00:41:43.122504 <6>[ 0.102708] Detected PIPT I-cache on CPU5
10522 00:41:43.129321 <6>[ 0.102769] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10523 00:41:43.136317 <6>[ 0.102785] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10524 00:41:43.139407 <6>[ 0.103067] Detected PIPT I-cache on CPU6
10525 00:41:43.146317 <6>[ 0.103133] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10526 00:41:43.152566 <6>[ 0.103149] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10527 00:41:43.159080 <6>[ 0.103446] Detected PIPT I-cache on CPU7
10528 00:41:43.165860 <6>[ 0.103512] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10529 00:41:43.172624 <6>[ 0.103528] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10530 00:41:43.175639 <6>[ 0.103576] smp: Brought up 1 node, 8 CPUs
10531 00:41:43.179372 <6>[ 0.244863] SMP: Total of 8 processors activated.
10532 00:41:43.185916 <6>[ 0.249784] CPU features: detected: 32-bit EL0 Support
10533 00:41:43.196000 <6>[ 0.255148] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10534 00:41:43.202190 <6>[ 0.263948] CPU features: detected: Common not Private translations
10535 00:41:43.205810 <6>[ 0.270464] CPU features: detected: CRC32 instructions
10536 00:41:43.212224 <6>[ 0.275848] CPU features: detected: RCpc load-acquire (LDAPR)
10537 00:41:43.219274 <6>[ 0.281808] CPU features: detected: LSE atomic instructions
10538 00:41:43.226075 <6>[ 0.287590] CPU features: detected: Privileged Access Never
10539 00:41:43.229572 <6>[ 0.293370] CPU features: detected: RAS Extension Support
10540 00:41:43.235896 <6>[ 0.299013] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10541 00:41:43.242242 <6>[ 0.306233] CPU: All CPU(s) started at EL2
10542 00:41:43.245797 <6>[ 0.310549] alternatives: applying system-wide alternatives
10543 00:41:43.256937 <6>[ 0.321398] devtmpfs: initialized
10544 00:41:43.269631 <6>[ 0.330391] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10545 00:41:43.279733 <6>[ 0.340354] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10546 00:41:43.286384 <6>[ 0.348192] pinctrl core: initialized pinctrl subsystem
10547 00:41:43.289341 <6>[ 0.354880] DMI not present or invalid.
10548 00:41:43.296146 <6>[ 0.359290] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10549 00:41:43.306119 <6>[ 0.366146] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10550 00:41:43.313150 <6>[ 0.373736] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10551 00:41:43.323010 <6>[ 0.381954] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10552 00:41:43.326187 <6>[ 0.390199] audit: initializing netlink subsys (disabled)
10553 00:41:43.336204 <5>[ 0.395895] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10554 00:41:43.339994 <6>[ 0.396625] thermal_sys: Registered thermal governor 'step_wise'
10555 00:41:43.349473 <6>[ 0.403862] thermal_sys: Registered thermal governor 'power_allocator'
10556 00:41:43.352866 <6>[ 0.410116] cpuidle: using governor menu
10557 00:41:43.355806 <6>[ 0.421076] NET: Registered PF_QIPCRTR protocol family
10558 00:41:43.365953 <6>[ 0.426555] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10559 00:41:43.368980 <6>[ 0.433661] ASID allocator initialised with 32768 entries
10560 00:41:43.375834 <6>[ 0.440249] Serial: AMBA PL011 UART driver
10561 00:41:43.384803 <4>[ 0.449133] Trying to register duplicate clock ID: 134
10562 00:41:43.444905 <6>[ 0.512395] KASLR enabled
10563 00:41:43.459261 <6>[ 0.520089] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10564 00:41:43.466073 <6>[ 0.527104] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10565 00:41:43.473145 <6>[ 0.533591] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10566 00:41:43.479060 <6>[ 0.540594] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10567 00:41:43.485736 <6>[ 0.547081] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10568 00:41:43.492523 <6>[ 0.554085] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10569 00:41:43.499265 <6>[ 0.560572] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10570 00:41:43.505510 <6>[ 0.567577] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10571 00:41:43.509120 <6>[ 0.575048] ACPI: Interpreter disabled.
10572 00:41:43.517177 <6>[ 0.581476] iommu: Default domain type: Translated
10573 00:41:43.524206 <6>[ 0.586624] iommu: DMA domain TLB invalidation policy: strict mode
10574 00:41:43.527654 <5>[ 0.593278] SCSI subsystem initialized
10575 00:41:43.533714 <6>[ 0.597526] usbcore: registered new interface driver usbfs
10576 00:41:43.540226 <6>[ 0.603258] usbcore: registered new interface driver hub
10577 00:41:43.543749 <6>[ 0.608810] usbcore: registered new device driver usb
10578 00:41:43.550728 <6>[ 0.614926] pps_core: LinuxPPS API ver. 1 registered
10579 00:41:43.560887 <6>[ 0.620122] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10580 00:41:43.564340 <6>[ 0.629466] PTP clock support registered
10581 00:41:43.567198 <6>[ 0.633709] EDAC MC: Ver: 3.0.0
10582 00:41:43.574619 <6>[ 0.638897] FPGA manager framework
10583 00:41:43.581910 <6>[ 0.642574] Advanced Linux Sound Architecture Driver Initialized.
10584 00:41:43.585007 <6>[ 0.649352] vgaarb: loaded
10585 00:41:43.591481 <6>[ 0.652493] clocksource: Switched to clocksource arch_sys_counter
10586 00:41:43.594596 <5>[ 0.658940] VFS: Disk quotas dquot_6.6.0
10587 00:41:43.600867 <6>[ 0.663125] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10588 00:41:43.604560 <6>[ 0.670318] pnp: PnP ACPI: disabled
10589 00:41:43.613370 <6>[ 0.677071] NET: Registered PF_INET protocol family
10590 00:41:43.620040 <6>[ 0.682657] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10591 00:41:43.634910 <6>[ 0.694992] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10592 00:41:43.644499 <6>[ 0.703810] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10593 00:41:43.650899 <6>[ 0.711780] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10594 00:41:43.657217 <6>[ 0.720480] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10595 00:41:43.670003 <6>[ 0.730238] TCP: Hash tables configured (established 65536 bind 65536)
10596 00:41:43.676329 <6>[ 0.737108] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10597 00:41:43.682955 <6>[ 0.744307] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10598 00:41:43.689874 <6>[ 0.752016] NET: Registered PF_UNIX/PF_LOCAL protocol family
10599 00:41:43.696221 <6>[ 0.758161] RPC: Registered named UNIX socket transport module.
10600 00:41:43.699362 <6>[ 0.764314] RPC: Registered udp transport module.
10601 00:41:43.706284 <6>[ 0.769248] RPC: Registered tcp transport module.
10602 00:41:43.712476 <6>[ 0.774181] RPC: Registered tcp NFSv4.1 backchannel transport module.
10603 00:41:43.715593 <6>[ 0.780845] PCI: CLS 0 bytes, default 64
10604 00:41:43.719317 <6>[ 0.785212] Unpacking initramfs...
10605 00:41:43.729590 <6>[ 0.788953] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10606 00:41:43.736439 <6>[ 0.797583] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10607 00:41:43.742147 <6>[ 0.806394] kvm [1]: IPA Size Limit: 40 bits
10608 00:41:43.746113 <6>[ 0.810920] kvm [1]: GICv3: no GICV resource entry
10609 00:41:43.752136 <6>[ 0.815943] kvm [1]: disabling GICv2 emulation
10610 00:41:43.758694 <6>[ 0.820633] kvm [1]: GIC system register CPU interface enabled
10611 00:41:43.762009 <6>[ 0.826801] kvm [1]: vgic interrupt IRQ18
10612 00:41:43.768657 <6>[ 0.832579] kvm [1]: VHE mode initialized successfully
10613 00:41:43.775218 <5>[ 0.838940] Initialise system trusted keyrings
10614 00:41:43.782282 <6>[ 0.843730] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10615 00:41:43.789445 <6>[ 0.853668] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10616 00:41:43.796362 <5>[ 0.860035] NFS: Registering the id_resolver key type
10617 00:41:43.799542 <5>[ 0.865338] Key type id_resolver registered
10618 00:41:43.806321 <5>[ 0.869754] Key type id_legacy registered
10619 00:41:43.812552 <6>[ 0.874050] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10620 00:41:43.819398 <6>[ 0.880968] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10621 00:41:43.826119 <6>[ 0.888677] 9p: Installing v9fs 9p2000 file system support
10622 00:41:43.862237 <5>[ 0.926121] Key type asymmetric registered
10623 00:41:43.865648 <5>[ 0.930451] Asymmetric key parser 'x509' registered
10624 00:41:43.875026 <6>[ 0.935604] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10625 00:41:43.878232 <6>[ 0.943217] io scheduler mq-deadline registered
10626 00:41:43.881528 <6>[ 0.947977] io scheduler kyber registered
10627 00:41:43.900935 <6>[ 0.965190] EINJ: ACPI disabled.
10628 00:41:43.934367 <4>[ 0.991845] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10629 00:41:43.944236 <4>[ 1.002469] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10630 00:41:43.959229 <6>[ 1.023361] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10631 00:41:43.966984 <6>[ 1.031268] printk: console [ttyS0] disabled
10632 00:41:43.994750 <6>[ 1.055892] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10633 00:41:44.002134 <6>[ 1.065366] printk: console [ttyS0] enabled
10634 00:41:44.004809 <6>[ 1.065366] printk: console [ttyS0] enabled
10635 00:41:44.011807 <6>[ 1.074260] printk: bootconsole [mtk8250] disabled
10636 00:41:44.014881 <6>[ 1.074260] printk: bootconsole [mtk8250] disabled
10637 00:41:44.022237 <6>[ 1.085321] SuperH (H)SCI(F) driver initialized
10638 00:41:44.024809 <6>[ 1.090596] msm_serial: driver initialized
10639 00:41:44.038767 <6>[ 1.099537] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10640 00:41:44.048414 <6>[ 1.108081] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10641 00:41:44.055576 <6>[ 1.116624] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10642 00:41:44.065216 <6>[ 1.125252] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10643 00:41:44.075007 <6>[ 1.133959] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10644 00:41:44.082271 <6>[ 1.142680] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10645 00:41:44.091502 <6>[ 1.151220] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10646 00:41:44.098576 <6>[ 1.160014] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10647 00:41:44.108463 <6>[ 1.168559] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10648 00:41:44.119916 <6>[ 1.184009] loop: module loaded
10649 00:41:44.126360 <6>[ 1.189972] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10650 00:41:44.149019 <4>[ 1.213222] mtk-pmic-keys: Failed to locate of_node [id: -1]
10651 00:41:44.156386 <6>[ 1.219924] megasas: 07.719.03.00-rc1
10652 00:41:44.165593 <6>[ 1.229599] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10653 00:41:44.172216 <6>[ 1.235898] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10654 00:41:44.188500 <6>[ 1.252421] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10655 00:41:44.244185 <6>[ 1.301810] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10656 00:41:46.399487 <6>[ 3.464196] Freeing initrd memory: 59572K
10657 00:41:46.410922 <6>[ 3.475709] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10658 00:41:46.422363 <6>[ 3.486539] tun: Universal TUN/TAP device driver, 1.6
10659 00:41:46.425629 <6>[ 3.492609] thunder_xcv, ver 1.0
10660 00:41:46.429077 <6>[ 3.496107] thunder_bgx, ver 1.0
10661 00:41:46.432123 <6>[ 3.499604] nicpf, ver 1.0
10662 00:41:46.442586 <6>[ 3.503613] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10663 00:41:46.445940 <6>[ 3.511089] hns3: Copyright (c) 2017 Huawei Corporation.
10664 00:41:46.452834 <6>[ 3.516677] hclge is initializing
10665 00:41:46.455580 <6>[ 3.520252] e1000: Intel(R) PRO/1000 Network Driver
10666 00:41:46.462722 <6>[ 3.525381] e1000: Copyright (c) 1999-2006 Intel Corporation.
10667 00:41:46.465962 <6>[ 3.531394] e1000e: Intel(R) PRO/1000 Network Driver
10668 00:41:46.472056 <6>[ 3.536610] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10669 00:41:46.479170 <6>[ 3.542794] igb: Intel(R) Gigabit Ethernet Network Driver
10670 00:41:46.485418 <6>[ 3.548444] igb: Copyright (c) 2007-2014 Intel Corporation.
10671 00:41:46.492821 <6>[ 3.554283] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10672 00:41:46.498785 <6>[ 3.560801] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10673 00:41:46.502160 <6>[ 3.567259] sky2: driver version 1.30
10674 00:41:46.508875 <6>[ 3.572185] usbcore: registered new device driver r8152-cfgselector
10675 00:41:46.515471 <6>[ 3.578720] usbcore: registered new interface driver r8152
10676 00:41:46.522382 <6>[ 3.584557] VFIO - User Level meta-driver version: 0.3
10677 00:41:46.529240 <6>[ 3.592796] usbcore: registered new interface driver usb-storage
10678 00:41:46.535115 <6>[ 3.599235] usbcore: registered new device driver onboard-usb-hub
10679 00:41:46.544079 <6>[ 3.608370] mt6397-rtc mt6359-rtc: registered as rtc0
10680 00:41:46.553818 <6>[ 3.613838] mt6397-rtc mt6359-rtc: setting system clock to 2024-06-16T00:41:46 UTC (1718498506)
10681 00:41:46.557001 <6>[ 3.623398] i2c_dev: i2c /dev entries driver
10682 00:41:46.571194 <4>[ 3.635384] cpu cpu0: supply cpu not found, using dummy regulator
10683 00:41:46.577625 <4>[ 3.641808] cpu cpu1: supply cpu not found, using dummy regulator
10684 00:41:46.584801 <4>[ 3.648210] cpu cpu2: supply cpu not found, using dummy regulator
10685 00:41:46.590798 <4>[ 3.654618] cpu cpu3: supply cpu not found, using dummy regulator
10686 00:41:46.597631 <4>[ 3.661019] cpu cpu4: supply cpu not found, using dummy regulator
10687 00:41:46.603958 <4>[ 3.667440] cpu cpu5: supply cpu not found, using dummy regulator
10688 00:41:46.610790 <4>[ 3.673838] cpu cpu6: supply cpu not found, using dummy regulator
10689 00:41:46.617177 <4>[ 3.680234] cpu cpu7: supply cpu not found, using dummy regulator
10690 00:41:46.636438 <6>[ 3.700891] cpu cpu0: EM: created perf domain
10691 00:41:46.639538 <6>[ 3.705833] cpu cpu4: EM: created perf domain
10692 00:41:46.647008 <6>[ 3.711431] sdhci: Secure Digital Host Controller Interface driver
10693 00:41:46.654081 <6>[ 3.717865] sdhci: Copyright(c) Pierre Ossman
10694 00:41:46.660201 <6>[ 3.722814] Synopsys Designware Multimedia Card Interface Driver
10695 00:41:46.666729 <6>[ 3.729457] sdhci-pltfm: SDHCI platform and OF driver helper
10696 00:41:46.670326 <6>[ 3.729566] mmc0: CQHCI version 5.10
10697 00:41:46.676708 <6>[ 3.739473] ledtrig-cpu: registered to indicate activity on CPUs
10698 00:41:46.683904 <6>[ 3.746433] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10699 00:41:46.689937 <6>[ 3.753505] usbcore: registered new interface driver usbhid
10700 00:41:46.693265 <6>[ 3.759327] usbhid: USB HID core driver
10701 00:41:46.700134 <6>[ 3.763514] spi_master spi0: will run message pump with realtime priority
10702 00:41:46.742445 <6>[ 3.800331] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10703 00:41:46.761424 <6>[ 3.815288] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10704 00:41:46.764529 <6>[ 3.829257] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x17414
10705 00:41:46.771177 <6>[ 3.835620] cros-ec-spi spi0.0: Chrome EC device registered
10706 00:41:46.777834 <6>[ 3.841634] mmc0: Command Queue Engine enabled
10707 00:41:46.784484 <6>[ 3.846378] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10708 00:41:46.788019 <6>[ 3.853862] mmcblk0: mmc0:0001 DA4128 116 GiB
10709 00:41:46.798378 <6>[ 3.862524] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10710 00:41:46.805044 <6>[ 3.869817] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10711 00:41:46.815689 <6>[ 3.874714] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10712 00:41:46.818511 <6>[ 3.875699] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10713 00:41:46.825242 <6>[ 3.885618] NET: Registered PF_PACKET protocol family
10714 00:41:46.832293 <6>[ 3.890207] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10715 00:41:46.835551 <6>[ 3.894965] 9pnet: Installing 9P2000 support
10716 00:41:46.841736 <5>[ 3.905946] Key type dns_resolver registered
10717 00:41:46.845477 <6>[ 3.910929] registered taskstats version 1
10718 00:41:46.851747 <5>[ 3.915313] Loading compiled-in X.509 certificates
10719 00:41:46.880564 <4>[ 3.938498] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10720 00:41:46.890846 <4>[ 3.949293] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10721 00:41:46.905427 <6>[ 3.969913] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10722 00:41:46.912000 <6>[ 3.976701] xhci-mtk 11200000.usb: xHCI Host Controller
10723 00:41:46.918780 <6>[ 3.982211] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10724 00:41:46.929061 <6>[ 3.990070] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10725 00:41:46.936172 <6>[ 3.999505] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10726 00:41:46.942228 <6>[ 4.005699] xhci-mtk 11200000.usb: xHCI Host Controller
10727 00:41:46.949379 <6>[ 4.011194] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10728 00:41:46.955424 <6>[ 4.018856] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10729 00:41:46.962172 <6>[ 4.026714] hub 1-0:1.0: USB hub found
10730 00:41:46.966052 <6>[ 4.030742] hub 1-0:1.0: 1 port detected
10731 00:41:46.975719 <6>[ 4.035018] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10732 00:41:46.979155 <6>[ 4.043781] hub 2-0:1.0: USB hub found
10733 00:41:46.982203 <6>[ 4.047822] hub 2-0:1.0: 1 port detected
10734 00:41:46.990169 <6>[ 4.054827] mtk-msdc 11f70000.mmc: Got CD GPIO
10735 00:41:47.009974 <6>[ 4.070895] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10736 00:41:47.019524 <6>[ 4.079363] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10737 00:41:47.026677 <6>[ 4.087711] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10738 00:41:47.036462 <6>[ 4.096063] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10739 00:41:47.043083 <6>[ 4.104404] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10740 00:41:47.053466 <6>[ 4.112756] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10741 00:41:47.059455 <6>[ 4.121097] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10742 00:41:47.069653 <6>[ 4.129447] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10743 00:41:47.075906 <6>[ 4.137785] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10744 00:41:47.085851 <6>[ 4.146134] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10745 00:41:47.092546 <6>[ 4.154474] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10746 00:41:47.102658 <6>[ 4.162823] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10747 00:41:47.108826 <6>[ 4.171161] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10748 00:41:47.119039 <6>[ 4.179510] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10749 00:41:47.126186 <6>[ 4.187848] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10750 00:41:47.132329 <6>[ 4.196549] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10751 00:41:47.139106 <6>[ 4.203707] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10752 00:41:47.146058 <6>[ 4.210505] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10753 00:41:47.155973 <6>[ 4.217270] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10754 00:41:47.162783 <6>[ 4.224206] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10755 00:41:47.169125 <6>[ 4.231070] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10756 00:41:47.178932 <6>[ 4.240199] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10757 00:41:47.189351 <6>[ 4.249322] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10758 00:41:47.199317 <6>[ 4.258616] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10759 00:41:47.209066 <6>[ 4.268084] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10760 00:41:47.216007 <6>[ 4.277552] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10761 00:41:47.225860 <6>[ 4.286672] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10762 00:41:47.235768 <6>[ 4.296138] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10763 00:41:47.245605 <6>[ 4.305257] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10764 00:41:47.255626 <6>[ 4.314555] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10765 00:41:47.265542 <6>[ 4.324735] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10766 00:41:47.275274 <6>[ 4.336700] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10767 00:41:47.371545 <6>[ 4.432976] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10768 00:41:47.399228 <6>[ 4.463773] hub 2-1:1.0: USB hub found
10769 00:41:47.402273 <6>[ 4.468212] hub 2-1:1.0: 3 ports detected
10770 00:41:47.411674 <6>[ 4.476383] hub 2-1:1.0: USB hub found
10771 00:41:47.414745 <6>[ 4.480807] hub 2-1:1.0: 3 ports detected
10772 00:41:47.523849 <6>[ 4.584712] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10773 00:41:47.678568 <6>[ 4.742921] hub 1-1:1.0: USB hub found
10774 00:41:47.681464 <6>[ 4.747390] hub 1-1:1.0: 4 ports detected
10775 00:41:47.693510 <6>[ 4.758149] hub 1-1:1.0: USB hub found
10776 00:41:47.696619 <6>[ 4.762460] hub 1-1:1.0: 4 ports detected
10777 00:41:47.755371 <6>[ 4.816884] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10778 00:41:47.863864 <6>[ 4.925193] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10779 00:41:47.895533 <4>[ 4.956974] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10780 00:41:47.905740 <4>[ 4.966072] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10781 00:41:47.944556 <6>[ 5.009384] r8152 2-1.3:1.0 eth0: v1.12.13
10782 00:41:48.019609 <6>[ 5.080759] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10783 00:41:48.151340 <6>[ 5.216044] hub 1-1.4:1.0: USB hub found
10784 00:41:48.154777 <6>[ 5.220663] hub 1-1.4:1.0: 2 ports detected
10785 00:41:48.166799 <6>[ 5.231506] hub 1-1.4:1.0: USB hub found
10786 00:41:48.170068 <6>[ 5.236090] hub 1-1.4:1.0: 2 ports detected
10787 00:41:48.467580 <6>[ 5.528825] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10788 00:41:48.667441 <6>[ 5.728743] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10789 00:41:49.605942 <6>[ 6.670620] r8152 2-1.3:1.0 eth0: carrier on
10790 00:41:49.652193 <5>[ 6.700714] Sending DHCP requests ., OK
10791 00:41:49.658649 <6>[ 6.720860] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.12
10792 00:41:49.662254 <6>[ 6.729148] IP-Config: Complete:
10793 00:41:49.674894 <6>[ 6.732678] device=eth0, hwaddr=00:e0:4c:78:7a:aa, ipaddr=192.168.201.12, mask=255.255.255.0, gw=192.168.201.1
10794 00:41:49.681835 <6>[ 6.743401] host=mt8192-asurada-spherion-r0-cbg-0, domain=lava-rack, nis-domain=(none)
10795 00:41:49.688521 <6>[ 6.752019] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10796 00:41:49.695076 <6>[ 6.752029] nameserver0=192.168.201.1
10797 00:41:49.698123 <6>[ 6.764180] clk: Disabling unused clocks
10798 00:41:49.701895 <6>[ 6.769734] ALSA device list:
10799 00:41:49.708101 <6>[ 6.773012] No soundcards found.
10800 00:41:49.716288 <6>[ 6.780685] Freeing unused kernel memory: 8512K
10801 00:41:49.719129 <6>[ 6.785560] Run /init as init process
10802 00:41:49.748943 <6>[ 6.813878] NET: Registered PF_INET6 protocol family
10803 00:41:49.755785 <6>[ 6.820161] Segment Routing with IPv6
10804 00:41:49.759092 <6>[ 6.824095] In-situ OAM (IOAM) with IPv6
10805 00:41:49.801836 <30>[ 6.840175] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10806 00:41:49.808404 <30>[ 6.873244] systemd[1]: Detected architecture arm64.
10807 00:41:49.808902
10808 00:41:49.814843 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10809 00:41:49.815323
10810 00:41:49.828222 <30>[ 6.892924] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10811 00:41:49.958290 <30>[ 7.019788] systemd[1]: Queued start job for default target graphical.target.
10812 00:41:49.996767 <30>[ 7.058326] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10813 00:41:50.003482 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10814 00:41:50.024131 <30>[ 7.085298] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10815 00:41:50.034029 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10816 00:41:50.052378 <30>[ 7.113776] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10817 00:41:50.062307 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10818 00:41:50.079843 <30>[ 7.141323] systemd[1]: Created slice user.slice - User and Session Slice.
10819 00:41:50.086217 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10820 00:41:50.106626 <30>[ 7.164892] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10821 00:41:50.113336 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10822 00:41:50.134779 <30>[ 7.192935] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10823 00:41:50.141651 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10824 00:41:50.169458 <30>[ 7.221217] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10825 00:41:50.179362 <30>[ 7.241118] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10826 00:41:50.186196 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10827 00:41:50.203833 <30>[ 7.265158] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10828 00:41:50.213350 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10829 00:41:50.231653 <30>[ 7.293267] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10830 00:41:50.241906 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10831 00:41:50.256523 <30>[ 7.321282] systemd[1]: Reached target paths.target - Path Units.
10832 00:41:50.266484 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10833 00:41:50.283757 <30>[ 7.345256] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10834 00:41:50.290444 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10835 00:41:50.304150 <30>[ 7.368785] systemd[1]: Reached target slices.target - Slice Units.
10836 00:41:50.314091 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10837 00:41:50.329069 <30>[ 7.393269] systemd[1]: Reached target swap.target - Swaps.
10838 00:41:50.335689 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10839 00:41:50.356400 <30>[ 7.417316] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10840 00:41:50.365882 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10841 00:41:50.384199 <30>[ 7.445778] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10842 00:41:50.394124 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10843 00:41:50.413442 <30>[ 7.475070] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10844 00:41:50.423849 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10845 00:41:50.440380 <30>[ 7.501491] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10846 00:41:50.449637 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10847 00:41:50.468408 <30>[ 7.529391] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10848 00:41:50.474285 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10849 00:41:50.492506 <30>[ 7.553424] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10850 00:41:50.501958 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10851 00:41:50.519998 <30>[ 7.581270] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10852 00:41:50.526663 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10853 00:41:50.571424 <30>[ 7.632752] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10854 00:41:50.578040 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10855 00:41:50.597047 <30>[ 7.658598] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10856 00:41:50.603707 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10857 00:41:50.627909 <30>[ 7.688875] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10858 00:41:50.633681 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10859 00:41:50.662692 <30>[ 7.717313] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10860 00:41:50.676488 <30>[ 7.737898] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10861 00:41:50.686139 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10862 00:41:50.708678 <30>[ 7.770330] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10863 00:41:50.715432 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10864 00:41:50.740824 <30>[ 7.802157] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10865 00:41:50.750401 Startin<6>[ 7.811504] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10866 00:41:50.757064 g [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10867 00:41:50.811646 <30>[ 7.873518] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10868 00:41:50.818668 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10869 00:41:50.844694 <30>[ 7.906310] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10870 00:41:50.851589 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10871 00:41:50.876493 <30>[ 7.938206] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10872 00:41:50.883448 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10873 00:41:50.944326 <30>[ 8.005545] systemd[1]: Starting systemd-journald.service - Journal Service...
10874 00:41:50.950886 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10875 00:41:50.974131 <30>[ 8.035451] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10876 00:41:50.980278 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10877 00:41:51.008146 <30>[ 8.066206] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10878 00:41:51.014873 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10879 00:41:51.040252 <30>[ 8.102130] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10880 00:41:51.050485 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10881 00:41:51.104604 <30>[ 8.165775] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10882 00:41:51.114288 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10883 00:41:51.135721 <30>[ 8.197372] systemd[1]: Started systemd-journald.service - Journal Service.
10884 00:41:51.142304 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10885 00:41:51.161832 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10886 00:41:51.183717 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10887 00:41:51.203721 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10888 00:41:51.220606 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10889 00:41:51.246225 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10890 00:41:51.265925 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10891 00:41:51.290090 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10892 00:41:51.314548 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10893 00:41:51.334973 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10894 00:41:51.352978 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10895 00:41:51.372867 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10896 00:41:51.393799 [[0;1;31mFAILED[0m] Failed to start [0;1;39msystemd-re…ount Root and Kernel File Systems.
10897 00:41:51.407903 See 'systemctl status systemd-remount-fs.service' for details.
10898 00:41:51.418192 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10899 00:41:51.438028 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10900 00:41:51.475992 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10901 00:41:51.497653 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10902 00:41:51.509383 <46>[ 8.570854] systemd-journald[192]: Received client request to flush runtime journal.
10903 00:41:51.520573 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10904 00:41:51.546553 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10905 00:41:51.572469 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10906 00:41:51.600083 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10907 00:41:51.625344 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10908 00:41:51.648669 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10909 00:41:51.672573 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10910 00:41:51.692696 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10911 00:41:51.732247 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10912 00:41:51.762483 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10913 00:41:51.780176 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10914 00:41:51.799248 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10915 00:41:51.843843 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10916 00:41:51.864095 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10917 00:41:51.886789 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10918 00:41:51.940849 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10919 00:41:51.970099 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10920 00:41:51.988815 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10921 00:41:52.036581 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10922 00:41:52.075609 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10923 00:41:52.128023 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10924 00:41:52.237654 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10925 00:41:52.256784 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10926 00:41:52.275528 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
10927 00:41:52.296178 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
10928 00:41:52.315087 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
10929 00:41:52.332653 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
10930 00:41:52.348542 <6>[ 9.410420] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10931 00:41:52.357945 <6>[ 9.418374] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10932 00:41:52.367773 [[0;32m OK [<6>[ 9.427470] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10933 00:41:52.377765 0m] Reached targ<6>[ 9.429204] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10934 00:41:52.381370 et [0;1;39msockets.target[0m - Socket Units.
10935 00:41:52.387776 <6>[ 9.451101] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10936 00:41:52.397980 <3>[ 9.454391] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10937 00:41:52.404193 <6>[ 9.459142] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10938 00:41:52.414276 <4>[ 9.459225] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10939 00:41:52.420886 <3>[ 9.467571] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10940 00:41:52.427586 <6>[ 9.472267] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10941 00:41:52.437766 <6>[ 9.475555] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10942 00:41:52.444545 <3>[ 9.484316] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10943 00:41:52.454033 <6>[ 9.492177] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10944 00:41:52.464293 [[0;32m OK [0m] Reached targ<3>[ 9.526120] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10945 00:41:52.474183 et [0;1;39mbasi<3>[ 9.534939] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10946 00:41:52.484601 c.target[0m - B<3>[ 9.544342] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10947 00:41:52.484749 asic System.
10948 00:41:52.493767 <6>[ 9.545014] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10949 00:41:52.500798 <3>[ 9.553820] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10950 00:41:52.510923 <3>[ 9.553828] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10951 00:41:52.514019 <6>[ 9.555498] remoteproc remoteproc0: scp is available
10952 00:41:52.524026 <3>[ 9.562327] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10953 00:41:52.530348 <6>[ 9.563094] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10954 00:41:52.537219 <6>[ 9.563102] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10955 00:41:52.547774 <6>[ 9.563110] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10956 00:41:52.553689 <6>[ 9.565468] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10957 00:41:52.560659 <6>[ 9.571462] remoteproc remoteproc0: powering up scp
10958 00:41:52.567105 <3>[ 9.575348] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10959 00:41:52.577276 <3>[ 9.575357] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10960 00:41:52.584302 <3>[ 9.575361] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10961 00:41:52.590480 <3>[ 9.575402] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10962 00:41:52.600870 <3>[ 9.575406] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10963 00:41:52.606881 <3>[ 9.575408] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10964 00:41:52.616883 <3>[ 9.575413] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10965 00:41:52.623527 <3>[ 9.575415] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10966 00:41:52.633344 <3>[ 9.575436] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10967 00:41:52.637065 <6>[ 9.579391] pci_bus 0000:00: root bus resource [bus 00-ff]
10968 00:41:52.646886 <6>[ 9.579396] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10969 00:41:52.653765 <6>[ 9.579399] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10970 00:41:52.660566 <6>[ 9.579431] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10971 00:41:52.670396 <6>[ 9.579446] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10972 00:41:52.673659 <6>[ 9.579513] pci 0000:00:00.0: supports D1 D2
10973 00:41:52.680144 <6>[ 9.584765] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10974 00:41:52.690497 <6>[ 9.592831] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10975 00:41:52.696820 <6>[ 9.593818] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10976 00:41:52.703191 <6>[ 9.601491] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10977 00:41:52.710694 <6>[ 9.615062] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10978 00:41:52.717496 <4>[ 9.618534] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10979 00:41:52.724589 <6>[ 9.624613] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10980 00:41:52.730765 <4>[ 9.640388] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10981 00:41:52.737682 <6>[ 9.641193] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10982 00:41:52.747921 <6>[ 9.645882] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10983 00:41:52.754908 <4>[ 9.672022] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10984 00:41:52.761045 <4>[ 9.672022] Fallback method does not support PEC.
10985 00:41:52.768114 <6>[ 9.678198] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10986 00:41:52.777583 <6>[ 9.685195] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10987 00:41:52.780495 <6>[ 9.686991] mc: Linux media interface: v0.10
10988 00:41:52.791014 <6>[ 9.693082] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10989 00:41:52.794213 <6>[ 9.694475] pci 0000:01:00.0: supports D1 D2
10990 00:41:52.805904 <3>[ 9.720598] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10991 00:41:52.812759 <6>[ 9.725212] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10992 00:41:52.820250 <6>[ 9.736649] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10993 00:41:52.826442 <6>[ 9.743117] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10994 00:41:52.832974 <6>[ 9.743534] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10995 00:41:52.839870 <6>[ 9.752199] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10996 00:41:52.851126 <6>[ 9.758804] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10997 00:41:52.857645 <6>[ 9.758815] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10998 00:41:52.867438 <6>[ 9.758827] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10999 00:41:52.870600 <6>[ 9.767086] remoteproc remoteproc0: remote processor scp is now up
11000 00:41:52.881276 <6>[ 9.772733] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
11001 00:41:52.884931 <6>[ 9.772746] pci 0000:00:00.0: PCI bridge to [bus 01]
11002 00:41:52.894935 <6>[ 9.772751] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
11003 00:41:52.901004 <6>[ 9.772969] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
11004 00:41:52.907838 <6>[ 9.783229] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
11005 00:41:52.914353 <6>[ 9.786855] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
11006 00:41:52.924469 <3>[ 9.788607] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11007 00:41:52.931062 <3>[ 9.789384] power_supply sbs-5-000b: driver failed to report `capacity_level' property: -6
11008 00:41:52.937390 <6>[ 9.809595] videodev: Linux video capture interface: v2.00
11009 00:41:52.944337 <6>[ 9.817143] pcieport 0000:00:00.0: AER: enabled with IRQ 282
11010 00:41:52.951015 <6>[ 9.832251] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
11011 00:41:52.957837 <6>[ 9.838548] Bluetooth: Core ver 2.22
11012 00:41:52.964454 <6>[ 9.851081] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
11013 00:41:52.971515 <6>[ 9.852166] NET: Registered PF_BLUETOOTH protocol family
11014 00:41:52.978318 <5>[ 9.853762] cfg80211: Loading compiled-in X.509 certificates for regulatory database
11015 00:41:52.984811 <5>[ 9.869599] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
11016 00:41:52.991689 <6>[ 9.874406] Bluetooth: HCI device and connection manager initialized
11017 00:41:52.998106 <6>[ 9.874432] Bluetooth: HCI socket layer initialized
11018 00:41:53.001336 <6>[ 9.874445] Bluetooth: L2CAP socket layer initialized
11019 00:41:53.008087 <6>[ 9.874460] Bluetooth: SCO socket layer initialized
11020 00:41:53.015239 <3>[ 9.877193] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11021 00:41:53.025073 <3>[ 9.878048] power_supply sbs-5-000b: driver failed to report `current_avg' property: -6
11022 00:41:53.031812 <5>[ 9.881598] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
11023 00:41:53.042790 <3>[ 9.889011] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11024 00:41:53.049131 <6>[ 9.889851] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
11025 00:41:53.056750 <3>[ 9.890117] power_supply sbs-5-000b: driver failed to report `status' property: -6
11026 00:41:53.069748 <6>[ 9.891989] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
11027 00:41:53.073145 <6>[ 9.892111] usbcore: registered new interface driver uvcvideo
11028 00:41:53.083782 <4>[ 9.895664] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
11029 00:41:53.090529 <3>[ 9.916518] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11030 00:41:53.097043 <6>[ 9.919894] cfg80211: failed to load regulatory.db
11031 00:41:53.103572 <6>[ 9.920786] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
11032 00:41:53.113706 <3>[ 9.948522] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11033 00:41:53.117251 <6>[ 9.951788] usbcore: registered new interface driver btusb
11034 00:41:53.130380 <4>[ 9.955905] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
11035 00:41:53.137207 <6>[ 10.020949] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
11036 00:41:53.143474 <3>[ 10.022619] Bluetooth: hci0: Failed to load firmware file (-2)
11037 00:41:53.146611 <6>[ 10.026462] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
11038 00:41:53.153333 <3>[ 10.034734] Bluetooth: hci0: Failed to set up firmware (-2)
11039 00:41:53.163351 <3>[ 10.043161] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11040 00:41:53.173766 <4>[ 10.048276] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
11041 00:41:53.180273 <6>[ 10.060599] mt7921e 0000:01:00.0: ASIC revision: 79610010
11042 00:41:53.186829 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11043 00:41:53.251290 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11044 00:41:53.284434 <46>[ 10.332775] systemd-journald[192]: Data hash table of /var/log/journal/c3f909ee3e324895ab90ff2613af9260/system.journal has a fill level at 75.2 (1540 of 2047 items, 524288 file size, 340 bytes per hash table item), suggesting rotation.
11045 00:41:53.301093 <46>[ 10.354380] systemd-journald[192]: /var/log/journal/c3f909ee3e324895ab90ff2613af9260/system.journal: Journal header limits reached or header out-of-date, rotating.
11046 00:41:53.313968 Starting [0;1;39msystemd-user-sess…vice[0m - Permit<6>[ 10.374750] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
11047 00:41:53.314515 <6>[ 10.374750]
11048 00:41:53.317121 User Sessions...
11049 00:41:53.340966 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11050 00:41:53.371139 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11051 00:41:53.426166 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11052 00:41:53.449678 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
11053 00:41:53.468872 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
11054 00:41:53.488520 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11055 00:41:53.539258 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11056 00:41:53.560092 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11057 00:41:53.584210 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - L<6>[ 10.644961] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
11058 00:41:53.584317 ogin Prompts.
11059 00:41:53.603997 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11060 00:41:53.623647 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11061 00:41:53.679796 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
11062 00:41:53.703577 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11063 00:41:53.728335 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11064 00:41:53.812740 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11065 00:41:53.831379 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11066 00:41:53.855743 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11067 00:41:53.904302
11068 00:41:53.907958 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11069 00:41:53.908045
11070 00:41:53.911167 debian-bookworm-arm64 login: root (automatic login)
11071 00:41:53.911244
11072 00:41:53.923863 Linux debian-bookworm-arm64 6.1.92-cip22 #1 SMP PREEMPT Sun Jun 16 00:28:47 UTC 2024 aarch64
11073 00:41:53.923946
11074 00:41:53.930624 The programs included with the Debian GNU/Linux system are free software;
11075 00:41:53.937296 the exact distribution terms for each program are described in the
11076 00:41:53.940468 individual files in /usr/share/doc/*/copyright.
11077 00:41:53.940544
11078 00:41:53.946697 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11079 00:41:53.950328 permitted by applicable law.
11080 00:41:53.950706 Matched prompt #10: / #
11082 00:41:53.950890 Setting prompt string to ['/ #']
11083 00:41:53.950976 end: 2.2.5.1 login-action (duration 00:00:12) [common]
11085 00:41:53.951149 end: 2.2.5 auto-login-action (duration 00:00:12) [common]
11086 00:41:53.951228 start: 2.2.6 expect-shell-connection (timeout 00:03:22) [common]
11087 00:41:53.951293 Setting prompt string to ['/ #']
11088 00:41:53.951349 Forcing a shell prompt, looking for ['/ #']
11090 00:41:54.001569 / #
11091 00:41:54.001759 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11092 00:41:54.001858 Waiting using forced prompt support (timeout 00:02:30)
11093 00:41:54.006603
11094 00:41:54.006872 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11095 00:41:54.006965 start: 2.2.7 export-device-env (timeout 00:03:22) [common]
11096 00:41:54.007053 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11097 00:41:54.007130 end: 2.2 depthcharge-retry (duration 00:01:38) [common]
11098 00:41:54.007212 end: 2 depthcharge-action (duration 00:01:38) [common]
11099 00:41:54.007292 start: 3 lava-test-retry (timeout 00:07:55) [common]
11100 00:41:54.007376 start: 3.1 lava-test-shell (timeout 00:07:55) [common]
11101 00:41:54.007440 Using namespace: common
11103 00:41:54.107772 / # #
11104 00:41:54.107964 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11105 00:41:54.113339 #
11106 00:41:54.113612 Using /lava-14368365
11108 00:41:54.213948 / # export SHELL=/bin/sh
11109 00:41:54.219264 export SHELL=/bin/sh
11111 00:41:54.319809 / # . /lava-14368365/environment
11112 00:41:54.325427 . /lava-14368365/environment
11114 00:41:54.426000 / # /lava-14368365/bin/lava-test-runner /lava-14368365/0
11115 00:41:54.426191 Test shell timeout: 10s (minimum of the action and connection timeout)
11116 00:41:54.430912 /lava-14368365/bin/lava-test-runner /lava-14368365/0
11117 00:41:54.442079 <6>[ 11.508135] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11118 00:41:54.460562 + export TESTRUN_ID=0_igt-kms-me<8>[ 11.525019] <LAVA_SIGNAL_STARTRUN 0_igt-kms-mediatek 14368365_1.5.2.3.1>
11119 00:41:54.460835 Received signal: <STARTRUN> 0_igt-kms-mediatek 14368365_1.5.2.3.1
11120 00:41:54.460904 Starting test lava.0_igt-kms-mediatek (14368365_1.5.2.3.1)
11121 00:41:54.460992 Skipping test definition patterns.
11122 00:41:54.463448 diatek
11123 00:41:54.467212 + cd /lava-14368365/0/tests/0_igt-kms-mediatek
11124 00:41:54.467290 + cat uuid
11125 00:41:54.470469 + UUID=14368365_1.5.2.3.1
11126 00:41:54.470546 + set +x
11127 00:41:54.490662 + IGT_FORCE_DRIVER=mediatek /usr/bin/igt-parser.sh core_auth core_getclient core_getstats core_getversion core_setmaster_vs_auth drm_read kms_addfb_basic kms_atomic kms_flip_event_leak kms_prop_blob kms_setmode kms_vblank
11128 00:41:54.499659 <8>[ 11.565123] <LAVA_SIGNAL_TESTSET START core_auth>
11129 00:41:54.499915 Received signal: <TESTSET> START core_auth
11130 00:41:54.499985 Starting test_set core_auth
11131 00:41:54.533713 <14>[ 11.599400] [IGT] core_auth: executing
11132 00:41:54.540244 IGT-Version: 1.2<14>[ 11.604045] [IGT] core_auth: starting subtest getclient-simple
11133 00:41:54.550160 8-ga44ebfe (aarc<14>[ 11.611658] [IGT] core_auth: finished subtest getclient-simple, SUCCESS
11134 00:41:54.553410 h64) (Linux: 6.1<14>[ 11.619922] [IGT] core_auth: exiting, ret=0
11135 00:41:54.556934 .92-cip22 aarch64)
11136 00:41:54.560096 Using IGT_SRANDOM=1718498514 for randomisation
11137 00:41:54.570154 Starting subtest: getclient-<8>[ 11.632907] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=getclient-simple RESULT=pass>
11138 00:41:54.570235 simple
11139 00:41:54.570468 Received signal: <TESTCASE> TEST_CASE_ID=getclient-simple RESULT=pass
11141 00:41:54.573700 Opened device: /dev/dri/card0
11142 00:41:54.580065 [1mSubtest getclient-simple: SUCCESS (0.000s)[0m
11143 00:41:54.604196 <14>[ 11.669775] [IGT] core_auth: executing
11144 00:41:54.610689 IGT-Version: 1.2<14>[ 11.674341] [IGT] core_auth: starting subtest getclient-master-drop
11145 00:41:54.620560 8-ga44ebfe (aarc<14>[ 11.682438] [IGT] core_auth: finished subtest getclient-master-drop, SUCCESS
11146 00:41:54.627402 h64) (Linux: 6.1<14>[ 11.691072] [IGT] core_auth: exiting, ret=0
11147 00:41:54.627483 .92-cip22 aarch64)
11148 00:41:54.630632 Using IGT_SRANDOM=1718498514 for randomisation
11149 00:41:54.640724 Starting subtest: getclient-<8>[ 11.704393] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=getclient-master-drop RESULT=pass>
11150 00:41:54.640976 Received signal: <TESTCASE> TEST_CASE_ID=getclient-master-drop RESULT=pass
11152 00:41:54.643701 master-drop
11153 00:41:54.647594 Opened device: /dev/dri/card0
11154 00:41:54.650577 [1mSubtest getclient-master-drop: SUCCESS (0.000s)[0m
11155 00:41:54.676180 <14>[ 11.741910] [IGT] core_auth: executing
11156 00:41:54.682726 IGT-Version: 1.2<14>[ 11.746634] [IGT] core_auth: starting subtest basic-auth
11157 00:41:54.689691 8-ga44ebfe (aarc<14>[ 11.753377] [IGT] core_auth: finished subtest basic-auth, SUCCESS
11158 00:41:54.696263 h64) (Linux: 6.1<14>[ 11.761121] [IGT] core_auth: exiting, ret=0
11159 00:41:54.699338 .92-cip22 aarch64)
11160 00:41:54.703062 Using IGT_SRANDOM=1718498514 for randomisation
11161 00:41:54.709352 Opened devic<8>[ 11.772945] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-auth RESULT=pass>
11162 00:41:54.709600 Received signal: <TESTCASE> TEST_CASE_ID=basic-auth RESULT=pass
11164 00:41:54.712826 e: /dev/dri/card0
11165 00:41:54.715554 Starting subtest: basic-auth
11166 00:41:54.719361 [1mSubtest basic-auth: SUCCESS (0.000s)[0m
11167 00:41:54.738768 <14>[ 11.804330] [IGT] core_auth: executing
11168 00:41:54.745418 IGT-Version: 1.2<14>[ 11.809055] [IGT] core_auth: starting subtest many-magics
11169 00:41:54.748470 8-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11170 00:41:54.755139 Using IGT_SRANDOM=1718498514 for randomisation
11171 00:41:54.761925 Opened device: /dev/dri/card<14>[ 11.826138] [IGT] core_auth: finished subtest many-magics, SUCCESS
11172 00:41:54.762008 0
11173 00:41:54.768257 Starting subt<14>[ 11.833635] [IGT] core_auth: exiting, ret=0
11174 00:41:54.771956 est: many-magics
11175 00:41:54.774821 Reopening device failed after 1020 opens
11176 00:41:54.781520 [1mSubtest many-mag<8>[ 11.846463] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=many-magics RESULT=pass>
11177 00:41:54.781801 Received signal: <TESTCASE> TEST_CASE_ID=many-magics RESULT=pass
11179 00:41:54.788123 ics: SUCCESS (0.<8>[ 11.854718] <LAVA_SIGNAL_TESTSET STOP>
11180 00:41:54.788202 010s)[0m
11181 00:41:54.788432 Received signal: <TESTSET> STOP
11182 00:41:54.788492 Closing test_set core_auth
11183 00:41:54.838691 <14>[ 11.904246] [IGT] core_getclient: executing
11184 00:41:54.845756 IGT-Version: 1.2<14>[ 11.909439] [IGT] core_getclient: exiting, ret=0
11185 00:41:54.848442 8-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11186 00:41:54.858135 Using IGT_SRANDOM=1718498514<8>[ 11.921362] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_getclient RESULT=pass>
11187 00:41:54.858476 Received signal: <TESTCASE> TEST_CASE_ID=core_getclient RESULT=pass
11189 00:41:54.861804 for randomisation
11190 00:41:54.861886 Opened device: /dev/dri/card0
11191 00:41:54.865569 SUCCESS (0.006s)
11192 00:41:54.910036 <14>[ 11.975244] [IGT] core_getstats: executing
11193 00:41:54.916536 IGT-Version: 1.2<14>[ 11.980396] [IGT] core_getstats: exiting, ret=0
11194 00:41:54.919932 8-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11195 00:41:54.930211 Using IGT_SR<8>[ 11.991457] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_getstats RESULT=pass>
11196 00:41:54.930952 Received signal: <TESTCASE> TEST_CASE_ID=core_getstats RESULT=pass
11198 00:41:54.933243 ANDOM=1718498514 for randomisation
11199 00:41:54.933667 Opened device: /dev/dri/card0
11200 00:41:54.936749 SUCCESS (0.006s)
11201 00:41:54.976268 <14>[ 12.041422] [IGT] core_getversion: executing
11202 00:41:54.982822 IGT-Version: 1.2<14>[ 12.046748] [IGT] core_getversion: exiting, ret=0
11203 00:41:54.986436 8-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11204 00:41:54.996282 Using IGT_SRANDOM=1718498514<8>[ 12.058729] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_getversion RESULT=pass>
11205 00:41:54.996922 Received signal: <TESTCASE> TEST_CASE_ID=core_getversion RESULT=pass
11207 00:41:54.999793 for randomisation
11208 00:41:55.002878 Opened device: /dev/dri/card0
11209 00:41:55.003366 SUCCESS (0.006s)
11210 00:41:55.047688 <14>[ 12.112820] [IGT] core_setmaster_vs_auth: executing
11211 00:41:55.054167 IGT-Version: 1.2<14>[ 12.118751] [IGT] core_setmaster_vs_auth: exiting, ret=0
11212 00:41:55.060973 8-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11213 00:41:55.067616 Using IGT_SR<8>[ 12.130846] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_setmaster_vs_auth RESULT=pass>
11214 00:41:55.068341 Received signal: <TESTCASE> TEST_CASE_ID=core_setmaster_vs_auth RESULT=pass
11216 00:41:55.070512 ANDOM=1718498515 for randomisation
11217 00:41:55.074004 Opened device: /dev/dri/card0
11218 00:41:55.077223 SUCCESS (0.007s)
11219 00:41:55.100420 <8>[ 12.165571] <LAVA_SIGNAL_TESTSET START drm_read>
11220 00:41:55.101129 Received signal: <TESTSET> START drm_read
11221 00:41:55.101469 Starting test_set drm_read
11222 00:41:55.126950 <14>[ 12.192481] [IGT] drm_read: executing
11223 00:41:55.133721 IGT-Version: 1.2<14>[ 12.197238] [IGT] drm_read: exiting, ret=77
11224 00:41:55.137481 8-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11225 00:41:55.147234 Using IGT_SRANDOM=1718498515 for randomisati<8>[ 12.210083] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-buffer RESULT=skip>
11226 00:41:55.147754 on
11227 00:41:55.148313 Received signal: <TESTCASE> TEST_CASE_ID=invalid-buffer RESULT=skip
11229 00:41:55.150381 Opened device: /dev/dri/card0
11230 00:41:55.156893 No KMS driver or no outputs, pipes: 16, outputs: 0
11231 00:41:55.159816 [1mSubtest invalid-buffer: SKIP (0.000s)[0m
11232 00:41:55.167437 <14>[ 12.232639] [IGT] drm_read: executing
11233 00:41:55.170522 IGT-Version: 1.2<14>[ 12.237110] [IGT] drm_read: exiting, ret=77
11234 00:41:55.177331 8-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11235 00:41:55.187092 Using IGT_SRANDOM=1718498515<8>[ 12.249048] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=fault-buffer RESULT=skip>
11236 00:41:55.187486 for randomisation
11237 00:41:55.188148 Received signal: <TESTCASE> TEST_CASE_ID=fault-buffer RESULT=skip
11239 00:41:55.190436 Opened device: /dev/dri/card0
11240 00:41:55.194134 No KMS driver or no outputs, pipes: 16, outputs: 0
11241 00:41:55.200707 [1mSubtest fault-buffer: SKIP (0.000s)[0m
11242 00:41:55.215616 <14>[ 12.280533] [IGT] drm_read: executing
11243 00:41:55.221840 IGT-Version: 1.2<14>[ 12.285357] [IGT] drm_read: exiting, ret=77
11244 00:41:55.225022 8-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11245 00:41:55.231731 Using IGT_SR<8>[ 12.296159] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=empty-block RESULT=skip>
11246 00:41:55.232362 Received signal: <TESTCASE> TEST_CASE_ID=empty-block RESULT=skip
11248 00:41:55.235264 ANDOM=1718498515 for randomisation
11249 00:41:55.238809 Opened device: /dev/dri/card0
11250 00:41:55.241816 No KMS driver or no outputs, pipes: 16, outputs: 0
11251 00:41:55.248206 [1mSubtest empty-block: SKIP (0.000s)[0m
11252 00:41:55.251379 <14>[ 12.317726] [IGT] drm_read: executing
11253 00:41:55.258382 IGT-Version: 1.2<14>[ 12.322332] [IGT] drm_read: exiting, ret=77
11254 00:41:55.262255 8-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11255 00:41:55.271730 Using IGT_SRANDOM=1718498515<8>[ 12.334106] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=empty-nonblock RESULT=skip>
11256 00:41:55.272430 Received signal: <TESTCASE> TEST_CASE_ID=empty-nonblock RESULT=skip
11258 00:41:55.274731 for randomisation
11259 00:41:55.275119 Opened device: /dev/dri/card0
11260 00:41:55.281229 No KMS driver or no outputs, pipes: 16, outputs: 0
11261 00:41:55.285229 [1mSubtest empty-nonblock: SKIP (0.000s)[0m
11262 00:41:55.292245 <14>[ 12.357769] [IGT] drm_read: executing
11263 00:41:55.299206 IGT-Version: 1.2<14>[ 12.362351] [IGT] drm_read: exiting, ret=77
11264 00:41:55.302003 8-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11265 00:41:55.312536 Using IGT_SRANDOM=1718498515<8>[ 12.374325] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=short-buffer-block RESULT=skip>
11266 00:41:55.312940 for randomisation
11267 00:41:55.313483 Received signal: <TESTCASE> TEST_CASE_ID=short-buffer-block RESULT=skip
11269 00:41:55.315469 Opened device: /dev/dri/card0
11270 00:41:55.321938 No KMS driver or no outputs, pipes: 16, outputs: 0
11271 00:41:55.325447 [1mSubtest short-buffer-block: SKIP (0.000s)[0m
11272 00:41:55.339606 <14>[ 12.405174] [IGT] drm_read: executing
11273 00:41:55.346173 IGT-Version: 1.2<14>[ 12.410007] [IGT] drm_read: exiting, ret=77
11274 00:41:55.349610 8-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11275 00:41:55.359521 Using IGT_SRANDOM=1718498515<8>[ 12.421987] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=short-buffer-nonblock RESULT=skip>
11276 00:41:55.360018 Received signal: <TESTCASE> TEST_CASE_ID=short-buffer-nonblock RESULT=skip
11278 00:41:55.362510 for randomisation
11279 00:41:55.362783 Opened device: /dev/dri/card0
11280 00:41:55.369275 No KMS driver or no outputs, pipes: 16, outputs: 0
11281 00:41:55.372357 [1mSubtest short-buffer-nonblock: SKIP (0.000s)[0m
11282 00:41:55.387705 <14>[ 12.453480] [IGT] drm_read: executing
11283 00:41:55.394138 IGT-Version: 1.2<14>[ 12.458455] [IGT] drm_read: exiting, ret=77
11284 00:41:55.397538 8-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11285 00:41:55.407618 Using IGT_SR<8>[ 12.469077] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=short-buffer-wakeup RESULT=skip>
11286 00:41:55.407930 Received signal: <TESTCASE> TEST_CASE_ID=short-buffer-wakeup RESULT=skip
11288 00:41:55.414034 ANDOM=1718498515 for randomisati<8>[ 12.478509] <LAVA_SIGNAL_TESTSET STOP>
11289 00:41:55.414149 on
11290 00:41:55.414437 Received signal: <TESTSET> STOP
11291 00:41:55.414554 Closing test_set drm_read
11292 00:41:55.417490 Opened device: /dev/dri/card0
11293 00:41:55.420708 No KMS driver or no outputs, pipes: 16, outputs: 0
11294 00:41:55.424177 [1mSubtest short-buffer-wakeup: SKIP (0.000s)[0m
11295 00:41:55.449736 <8>[ 12.515239] <LAVA_SIGNAL_TESTSET START kms_addfb_basic>
11296 00:41:55.449996 Received signal: <TESTSET> START kms_addfb_basic
11297 00:41:55.450067 Starting test_set kms_addfb_basic
11298 00:41:55.478943 <14>[ 12.544699] [IGT] kms_addfb_basic: executing
11299 00:41:55.492068 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch6<14>[ 12.554300] [IGT] kms_addfb_basic: starting subtest unused-handle
11300 00:41:55.492149 4)
11301 00:41:55.498673 Using IGT_SR<14>[ 12.561735] [IGT] kms_addfb_basic: finished subtest unused-handle, SUCCESS
11302 00:41:55.501762 ANDOM=1718498515 for randomisation
11303 00:41:55.505553 Opened device: /dev/dri/card0
11304 00:41:55.508670 Starting subtest: unused-handle
11305 00:41:55.515419 [1mSubtest <14>[ 12.579304] [IGT] kms_addfb_basic: exiting, ret=0
11306 00:41:55.518414 unused-handle: SUCCESS (0.000s)[0m
11307 00:41:55.528409 Test requirement not met in function igt_re<8>[ 12.591850] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-handle RESULT=pass>
11308 00:41:55.528662 Received signal: <TESTCASE> TEST_CASE_ID=unused-handle RESULT=pass
11310 00:41:55.531804 quire_intel, file ../lib/drmtest.c:880:
11311 00:41:55.534992 Test requirement: is_intel_device(fd)
11312 00:41:55.541877 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11313 00:41:55.548112 Test requirement: is_intel_d<14>[ 12.615583] [IGT] kms_addfb_basic: executing
11314 00:41:55.551253 evice(fd)
11315 00:41:55.554753 No KMS driver or no outputs, pipes: 16, outputs: 0
11316 00:41:55.561436 I<14>[ 12.624848] [IGT] kms_addfb_basic: starting subtest unused-pitches
11317 00:41:55.571856 GT-Version: 1.28<14>[ 12.632637] [IGT] kms_addfb_basic: finished subtest unused-pitches, SUCCESS
11318 00:41:55.574916 -ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11319 00:41:55.585381 Using IGT_SRANDOM=1718498515 for randomisatio<14>[ 12.649360] [IGT] kms_addfb_basic: exiting, ret=0
11320 00:41:55.585467 n
11321 00:41:55.588483 Opened device: /dev/dri/card0
11322 00:41:55.588562 Starting subtest: unused-pitches
11323 00:41:55.598447 [1mSubtest <8>[ 12.661219] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-pitches RESULT=pass>
11324 00:41:55.598700 Received signal: <TESTCASE> TEST_CASE_ID=unused-pitches RESULT=pass
11326 00:41:55.601380 unused-pitches: SUCCESS (0.000s)[0m
11327 00:41:55.608423 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11328 00:41:55.611460 Test requirement: is_intel_device(fd)
11329 00:41:55.618148 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11330 00:41:55.624431 Test requirement: is_intel_<14>[ 12.692160] [IGT] kms_addfb_basic: executing
11331 00:41:55.628318 device(fd)
11332 00:41:55.631391 No KMS driver or no outputs, pipes: 16, outputs: 0
11333 00:41:55.637825 <14>[ 12.701976] [IGT] kms_addfb_basic: starting subtest unused-offsets
11334 00:41:55.647736 IGT-Version: 1.2<14>[ 12.709509] [IGT] kms_addfb_basic: finished subtest unused-offsets, SUCCESS
11335 00:41:55.651356 8-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11336 00:41:55.654456 Using IGT_SRANDOM=1718498515 for randomisation
11337 00:41:55.661138 Opened devic<14>[ 12.726895] [IGT] kms_addfb_basic: exiting, ret=0
11338 00:41:55.664221 e: /dev/dri/card0
11339 00:41:55.667626 Starting subtest: unused-offsets
11340 00:41:55.674640 Received signal: <TESTCASE> TEST_CASE_ID=unused-offsets RESULT=pass
11342 00:41:55.677656 [1mSubtest unused-offsets:<8>[ 12.739407] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-offsets RESULT=pass>
11343 00:41:55.677737 SUCCESS (0.000s)[0m
11344 00:41:55.684149 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11345 00:41:55.687641 Test requirement: is_intel_device(fd)
11346 00:41:55.697512 Test requirement not met in fu<14>[ 12.761204] [IGT] kms_addfb_basic: executing
11347 00:41:55.700666 nction igt_require_intel, file ../lib/drmtest.c:880:
11348 00:41:55.707404 Test requi<14>[ 12.771256] [IGT] kms_addfb_basic: starting subtest unused-modifier
11349 00:41:55.717399 rement: is_intel<14>[ 12.779183] [IGT] kms_addfb_basic: finished subtest unused-modifier, SUCCESS
11350 00:41:55.717502 _device(fd)
11351 00:41:55.724229 No KMS driver or no outputs, pipes: 16, outputs: 0
11352 00:41:55.730679 IGT-Version: 1.28-ga44ebfe (aar<14>[ 12.796110] [IGT] kms_addfb_basic: exiting, ret=0
11353 00:41:55.733828 ch64) (Linux: 6.1.92-cip22 aarch64)
11354 00:41:55.744104 Using IGT_SRANDOM=1718498515 for randomisat<8>[ 12.807945] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-modifier RESULT=pass>
11355 00:41:55.744183 ion
11356 00:41:55.744412 Received signal: <TESTCASE> TEST_CASE_ID=unused-modifier RESULT=pass
11358 00:41:55.747463 Opened device: /dev/dri/card0
11359 00:41:55.750647 Starting subtest: unused-modifier
11360 00:41:55.753674 [1mSubtest unused-modifier: SUCCESS (0.000s)[0m
11361 00:41:55.764042 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11362 00:41:55.767012 Test requirement: is_intel_device(fd)
11363 00:41:55.773915 Test requirement not met in<14>[ 12.838940] [IGT] kms_addfb_basic: executing
11364 00:41:55.777012 function igt_require_intel, file ../lib/drmtest.c:880:
11365 00:41:55.786717 Test re<14>[ 12.848761] [IGT] kms_addfb_basic: starting subtest clobberred-modifier
11366 00:41:55.793455 quirement: is_in<14>[ 12.856438] [IGT] kms_addfb_basic: finished subtest clobberred-modifier, SKIP
11367 00:41:55.796933 tel_device(fd)
11368 00:41:55.800125 No KMS driver or no outputs, pipes: 16, outputs: 0
11369 00:41:55.810171 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux:<14>[ 12.874219] [IGT] kms_addfb_basic: exiting, ret=77
11370 00:41:55.810252 6.1.92-cip22 aarch64)
11371 00:41:55.816703 Using IGT_SRANDOM=1718498515 for randomisation
11372 00:41:55.823523 Opened d<8>[ 12.886976] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clobberred-modifier RESULT=skip>
11373 00:41:55.823781 Received signal: <TESTCASE> TEST_CASE_ID=clobberred-modifier RESULT=skip
11375 00:41:55.826565 evice: /dev/dri/card0
11376 00:41:55.829876 Starting subtest: clobberred-modifier
11377 00:41:55.837032 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:885:
11378 00:41:55.840175 Test requirement: is_i915_device(fd)
11379 00:41:55.843094 [1mSubtest clobberred-modifier: SKIP (0.000s)[0m
11380 00:41:55.853435 Test requirement not met in function <14>[ 12.917810] [IGT] kms_addfb_basic: executing
11381 00:41:55.856467 igt_require_intel, file ../lib/drmtest.c:880:
11382 00:41:55.866726 Test requirement:<14>[ 12.928002] [IGT] kms_addfb_basic: starting subtest invalid-smem-bo-on-discrete
11383 00:41:55.876463 is_intel_device<14>[ 12.936355] [IGT] kms_addfb_basic: finished subtest invalid-smem-bo-on-discrete, SKIP
11384 00:41:55.876540 (fd)
11385 00:41:55.883467 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11386 00:41:55.889721 Test requirement: is_i<14>[ 12.954688] [IGT] kms_addfb_basic: exiting, ret=77
11387 00:41:55.889798 ntel_device(fd)
11388 00:41:55.896542 No KMS driver or no outputs, pipes: 16, outputs: 0
11389 00:41:55.906588 IGT-Version<8>[ 12.967413] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-smem-bo-on-discrete RESULT=skip>
11390 00:41:55.906837 Received signal: <TESTCASE> TEST_CASE_ID=invalid-smem-bo-on-discrete RESULT=skip
11392 00:41:55.909921 : 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11393 00:41:55.913118 Using IGT_SRANDOM=1718498515 for randomisation
11394 00:41:55.916286 Opened device: /dev/dri/card0
11395 00:41:55.920063 Starting subtest: invalid-smem-bo-on-discrete
11396 00:41:55.929560 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11397 00:41:55.933187 Test <14>[ 12.999304] [IGT] kms_addfb_basic: executing
11398 00:41:55.936571 requirement: is_intel_device(fd)
11399 00:41:55.946656 [1mSubtest invalid-smem-bo-on<14>[ 13.009260] [IGT] kms_addfb_basic: starting subtest legacy-format
11400 00:41:55.949591 -discrete: SKIP (0.000s)[0m
11401 00:41:55.956235 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11402 00:41:55.962744 Test requireme<14>[ 13.027032] [IGT] kms_addfb_basic: finished subtest legacy-format, SUCCESS
11403 00:41:55.966494 nt: is_intel_device(fd)
11404 00:41:55.973015 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11405 00:41:55.979828 Tes<14>[ 13.043326] [IGT] kms_addfb_basic: exiting, ret=0
11406 00:41:55.982761 t requirement: is_intel_device(fd)
11407 00:41:55.992730 No KMS driver or no outputs, pipes: 16, outp<8>[ 13.055239] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=legacy-format RESULT=pass>
11408 00:41:55.992810 uts: 0
11409 00:41:55.993041 Received signal: <TESTCASE> TEST_CASE_ID=legacy-format RESULT=pass
11411 00:41:55.999464 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11412 00:41:56.002601 Using IGT_SRANDOM=1718498515 for randomisation
11413 00:41:56.006485 Opened device: /dev/dri/card0
11414 00:41:56.012705 Starting subtest: leg<14>[ 13.077749] [IGT] kms_addfb_basic: executing
11415 00:41:56.012781 acy-format
11416 00:41:56.019155 Successfully fuzzed 10000 {bpp, depth} variations
11417 00:41:56.025908 [1mSubtest legac<14>[ 13.090215] [IGT] kms_addfb_basic: starting subtest no-handle
11418 00:41:56.032547 y-format: SUCCES<14>[ 13.096694] [IGT] kms_addfb_basic: finished subtest no-handle, SUCCESS
11419 00:41:56.036159 S (0.011s)[0m
11420 00:41:56.046351 Test requirement not met in function igt_require_intel, file ../<14>[ 13.110885] [IGT] kms_addfb_basic: exiting, ret=0
11421 00:41:56.049557 lib/drmtest.c:880:
11422 00:41:56.052761 Test requirement: is_intel_device(fd)
11423 00:41:56.059345 Test requirement not <8>[ 13.122605] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=no-handle RESULT=pass>
11424 00:41:56.059593 Received signal: <TESTCASE> TEST_CASE_ID=no-handle RESULT=pass
11426 00:41:56.065759 met in function igt_require_intel, file ../lib/drmtest.c:880:
11427 00:41:56.069502 Test requirement: is_intel_device(fd)
11428 00:41:56.072667 No KMS driver or no outputs, pipes: 16, outputs: 0
11429 00:41:56.079319 IGT-Version: 1.28-ga44<14>[ 13.144995] [IGT] kms_addfb_basic: executing
11430 00:41:56.082574 ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11431 00:41:56.092545 Using IGT_SRANDOM=1718498516 for r<14>[ 13.157261] [IGT] kms_addfb_basic: starting subtest basic
11432 00:41:56.092633 andomisation
11433 00:41:56.099294 Op<14>[ 13.163759] [IGT] kms_addfb_basic: finished subtest basic, SUCCESS
11434 00:41:56.102253 ened device: /dev/dri/card0
11435 00:41:56.105474 Starting subtest: no-handle
11436 00:41:56.112698 [1mSubtest no-handle:<14>[ 13.177305] [IGT] kms_addfb_basic: exiting, ret=0
11437 00:41:56.115845 SUCCESS (0.000s)[0m
11438 00:41:56.125502 Test requirement not met in function igt_require_intel, f<8>[ 13.189573] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=pass>
11439 00:41:56.125764 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=pass
11441 00:41:56.129111 ile ../lib/drmtest.c:880:
11442 00:41:56.132245 Test requirement: is_intel_device(fd)
11443 00:41:56.139108 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11444 00:41:56.145255 Test requirement: is_intel<14>[ 13.210781] [IGT] kms_addfb_basic: executing
11445 00:41:56.145331 _device(fd)
11446 00:41:56.152240 No KMS driver or no outputs, pipes: 16, outputs: 0
11447 00:41:56.158682 IGT-Version: 1.<14>[ 13.223299] [IGT] kms_addfb_basic: starting subtest bad-pitch-0
11448 00:41:56.168825 28-ga44ebfe (aar<14>[ 13.229983] [IGT] kms_addfb_basic: finished subtest bad-pitch-0, SUCCESS
11449 00:41:56.172168 ch64) (Linux: 6.1.92-cip22 aarch64)
11450 00:41:56.178686 Using IGT_SRANDOM=1718498516 for randomisat<14>[ 13.244357] [IGT] kms_addfb_basic: exiting, ret=0
11451 00:41:56.178763 ion
11452 00:41:56.182203 Opened device: /dev/dri/card0
11453 00:41:56.185143 Starting subtest: basic
11454 00:41:56.192016 [1mSubtest basic: <8>[ 13.256662] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-0 RESULT=pass>
11455 00:41:56.192264 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-0 RESULT=pass
11457 00:41:56.195139 SUCCESS (0.000s)[0m
11458 00:41:56.201704 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11459 00:41:56.205064 Test requirement: is_intel_device(fd)
11460 00:41:56.211921 Test requirement not met in fun<14>[ 13.278545] [IGT] kms_addfb_basic: executing
11461 00:41:56.218204 ction igt_require_intel, file ../lib/drmtest.c:880:
11462 00:41:56.228172 Test requirement: is_intel_<14>[ 13.290891] [IGT] kms_addfb_basic: starting subtest bad-pitch-32
11463 00:41:56.228256 device(fd)
11464 00:41:56.235341 No K<14>[ 13.297836] [IGT] kms_addfb_basic: finished subtest bad-pitch-32, SUCCESS
11465 00:41:56.238457 MS driver or no outputs, pipes: 16, outputs: 0
11466 00:41:56.248533 IGT-Version: 1.28-ga44ebfe (aarc<14>[ 13.312073] [IGT] kms_addfb_basic: exiting, ret=0
11467 00:41:56.251686 h64) (Linux: 6.1.92-cip22 aarch64)
11468 00:41:56.261262 Using IGT_SRANDOM=1718498516 for randomisati<8>[ 13.324686] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-32 RESULT=pass>
11469 00:41:56.261339 on
11470 00:41:56.261569 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-32 RESULT=pass
11472 00:41:56.264616 Opened device: /dev/dri/card0
11473 00:41:56.268062 Starting subtest: bad-pitch-0
11474 00:41:56.271197 [1mSubtest bad-pitch-0: SUCCESS (0.000s)[0m
11475 00:41:56.278467 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11476 00:41:56.281344 Test requirement: is_intel_device(fd)
11477 00:41:56.287891 Test requirement not met in function<14>[ 13.355411] [IGT] kms_addfb_basic: executing
11478 00:41:56.294280 igt_require_intel, file ../lib/drmtest.c:880:
11479 00:41:56.297791 Test requirement: is_intel_device(fd)
11480 00:41:56.304536 No KMS dr<14>[ 13.367817] [IGT] kms_addfb_basic: starting subtest bad-pitch-63
11481 00:41:56.314569 iver or no outpu<14>[ 13.375294] [IGT] kms_addfb_basic: finished subtest bad-pitch-63, SUCCESS
11482 00:41:56.314650 ts, pipes: 16, outputs: 0
11483 00:41:56.324603 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-c<14>[ 13.390272] [IGT] kms_addfb_basic: exiting, ret=0
11484 00:41:56.327849 ip22 aarch64)
11485 00:41:56.330936 Using IGT_SRANDOM=1718498516 for randomisation
11486 00:41:56.337512 Opened device: /d<8>[ 13.402460] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-63 RESULT=pass>
11487 00:41:56.337810 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-63 RESULT=pass
11489 00:41:56.341140 ev/dri/card0
11490 00:41:56.344027 Starting subtest: bad-pitch-32
11491 00:41:56.347351 [1mSubtest bad-pitch-32: SUCCESS (0.000s)[0m
11492 00:41:56.357990 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:<14>[ 13.424097] [IGT] kms_addfb_basic: executing
11493 00:41:56.358069
11494 00:41:56.361084 Test requirement: is_intel_device(fd)
11495 00:41:56.370494 Test requirement not met in function ig<14>[ 13.436148] [IGT] kms_addfb_basic: starting subtest bad-pitch-128
11496 00:41:56.380602 t_require_intel,<14>[ 13.443296] [IGT] kms_addfb_basic: finished subtest bad-pitch-128, SUCCESS
11497 00:41:56.384335 file ../lib/drmtest.c:880:
11498 00:41:56.387094 Test requirement: is_intel_device(fd)
11499 00:41:56.393811 No KMS drive<14>[ 13.457614] [IGT] kms_addfb_basic: exiting, ret=0
11500 00:41:56.396854 r or no outputs, pipes: 16, outputs: 0
11501 00:41:56.406809 IGT-Version: 1.28-ga44ebfe (aarch64) (Li<8>[ 13.470391] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-128 RESULT=pass>
11502 00:41:56.407058 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-128 RESULT=pass
11504 00:41:56.410450 nux: 6.1.92-cip22 aarch64)
11505 00:41:56.413584 Using IGT_SRANDOM=1718498516 for randomisation
11506 00:41:56.416776 Opened device: /dev/dri/card0
11507 00:41:56.420544 Starting subtest: bad-pitch-63
11508 00:41:56.423407 [1mSubtest bad-pitch-63: SUCCESS (0.000s)[0m
11509 00:41:56.430233 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11510 00:41:56.434084 T<14>[ 13.500957] [IGT] kms_addfb_basic: executing
11511 00:41:56.436625 est requirement: is_intel_device(fd)
11512 00:41:56.449775 Test requirement not met in function igt_require_intel, fi<14>[ 13.513414] [IGT] kms_addfb_basic: starting subtest bad-pitch-256
11513 00:41:56.459697 le ../lib/drmtes<14>[ 13.520986] [IGT] kms_addfb_basic: finished subtest bad-pitch-256, SUCCESS
11514 00:41:56.459779 t.c:880:
11515 00:41:56.463349 Test requirement: is_intel_device(fd)
11516 00:41:56.470002 No KMS driver or no outputs, pi<14>[ 13.535956] [IGT] kms_addfb_basic: exiting, ret=0
11517 00:41:56.473270 pes: 16, outputs: 0
11518 00:41:56.482881 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 a<8>[ 13.548400] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-256 RESULT=pass>
11519 00:41:56.483129 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-256 RESULT=pass
11521 00:41:56.486639 arch64)
11522 00:41:56.489770 Using IGT_SRANDOM=1718498516 for randomisation
11523 00:41:56.493095 Opened device: /dev/dri/card0
11524 00:41:56.496612 Starting subtest: bad-pitch-128
11525 00:41:56.503397 [1mSubtest bad-pitch-128: SUCCESS (0.0<14>[ 13.569249] [IGT] kms_addfb_basic: executing
11526 00:41:56.503473 00s)[0m
11527 00:41:56.516168 Test requirement not met in function igt_require_intel, file ../lib/dr<14>[ 13.580686] [IGT] kms_addfb_basic: starting subtest bad-pitch-1024
11528 00:41:56.519337 mtest.c:880:
11529 00:41:56.526468 Te<14>[ 13.587899] [IGT] kms_addfb_basic: finished subtest bad-pitch-1024, SUCCESS
11530 00:41:56.529509 st requirement: is_intel_device(fd)
11531 00:41:56.536163 Test requirement not met in function igt_re<14>[ 13.602255] [IGT] kms_addfb_basic: exiting, ret=0
11532 00:41:56.539201 quire_intel, file ../lib/drmtest.c:880:
11533 00:41:56.543111 Test requirement: is_intel_device(fd)
11534 00:41:56.552531 <8>[ 13.615321] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-1024 RESULT=pass>
11535 00:41:56.552780 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-1024 RESULT=pass
11537 00:41:56.556128 No KMS driver or no outputs, pipes: 16, outputs: 0
11538 00:41:56.562854 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11539 00:41:56.565991 Using IGT_SRANDOM=1718498516 for randomisation
11540 00:41:56.572257 Opened d<14>[ 13.637458] [IGT] kms_addfb_basic: executing
11541 00:41:56.572333 evice: /dev/dri/card0
11542 00:41:56.575569 Starting subtest: bad-pitch-256
11543 00:41:56.585730 [1mSubtest bad-pitch-25<14>[ 13.649069] [IGT] kms_addfb_basic: starting subtest bad-pitch-999
11544 00:41:56.592602 6: SUCCESS (0.00<14>[ 13.656128] [IGT] kms_addfb_basic: finished subtest bad-pitch-999, SUCCESS
11545 00:41:56.595708 0s)[0m
11546 00:41:56.605490 Test requirement not met in function igt_require_intel, file ../lib/drm<14>[ 13.670477] [IGT] kms_addfb_basic: exiting, ret=0
11547 00:41:56.605607 test.c:880:
11548 00:41:56.609046 Test requirement: is_intel_device(fd)
11549 00:41:56.618999 Test requirement not met in <8>[ 13.683328] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-999 RESULT=pass>
11550 00:41:56.619250 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-999 RESULT=pass
11552 00:41:56.625587 function igt_require_intel, file ../lib/drmtest.c:880:
11553 00:41:56.628855 Test requirement: is_intel_device(fd)
11554 00:41:56.632205 No KMS driver or no outputs, pipes: 16, outputs: 0
11555 00:41:56.638569 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11556 00:41:56.642221 Using IGT_SRANDOM=1718498516 for randomisation
11557 00:41:56.648959 Opened de<14>[ 13.713935] [IGT] kms_addfb_basic: executing
11558 00:41:56.649036 vice: /dev/dri/card0
11559 00:41:56.651943 Starting subtest: bad-pitch-1024
11560 00:41:56.662343 [1mSubtest bad-pitch-1024: SUCCESS (0.0<14>[ 13.726553] [IGT] kms_addfb_basic: starting subtest bad-pitch-65536
11561 00:41:56.665498 00s)[0m
11562 00:41:56.672277 Test r<14>[ 13.734018] [IGT] kms_addfb_basic: finished subtest bad-pitch-65536, SUCCESS
11563 00:41:56.678348 equirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11564 00:41:56.685281 Te<14>[ 13.749487] [IGT] kms_addfb_basic: exiting, ret=0
11565 00:41:56.688605 st requirement: is_intel_device(fd)
11566 00:41:56.698600 Test requirement not met in function igt_re<8>[ 13.761466] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-65536 RESULT=pass>
11567 00:41:56.698853 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-65536 RESULT=pass
11569 00:41:56.701580 quire_intel, file ../lib/drmtest.c:880:
11570 00:41:56.705386 Test requirement: is_intel_device(fd)
11571 00:41:56.708457 No KMS driver or no outputs, pipes: 16, outputs: 0
11572 00:41:56.715305 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11573 00:41:56.718395 Using IGT_SRANDOM=1718498516 for randomisation
11574 00:41:56.725352 Opened device: /dev/dri/<14>[ 13.792461] [IGT] kms_addfb_basic: executing
11575 00:41:56.728499 card0
11576 00:41:56.728573 Starting subtest: bad-pitch-999
11577 00:41:56.734933 [1mSubtest bad-pitch-999: SUCCESS (0.000s)[0m
11578 00:41:56.741391 Test requirement not me<14>[ 13.806746] [IGT] kms_addfb_basic: starting subtest invalid-get-prop-any
11579 00:41:56.751655 t in function ig<14>[ 13.814224] [IGT] kms_addfb_basic: finished subtest invalid-get-prop-any, SUCCESS
11580 00:41:56.754698 t_require_intel, file ../lib/drmtest.c:880:
11581 00:41:56.761382 Test requirement: i<14>[ 13.827914] [IGT] kms_addfb_basic: exiting, ret=0
11582 00:41:56.764598 s_intel_device(fd)
11583 00:41:56.777963 Test requirement not met in function igt_require_intel, file<8>[ 13.840622] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop-any RESULT=pass>
11584 00:41:56.778214 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop-any RESULT=pass
11586 00:41:56.781343 ../lib/drmtest.c:880:
11587 00:41:56.785074 Test requirement: is_intel_device(fd)
11588 00:41:56.787793 No KMS driver or no outputs, pipes: 16, outputs: 0
11589 00:41:56.798254 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aar<14>[ 13.863736] [IGT] kms_addfb_basic: executing
11590 00:41:56.798334 ch64)
11591 00:41:56.801594 Using IGT_SRANDOM=1718498516 for randomisation
11592 00:41:56.805082 Opened device: /dev/dri/card0
11593 00:41:56.814629 Starting subtest: bad-pitc<14>[ 13.877049] [IGT] kms_addfb_basic: starting subtest invalid-get-prop
11594 00:41:56.814710 h-65536
11595 00:41:56.824858 [1mSub<14>[ 13.885244] [IGT] kms_addfb_basic: finished subtest invalid-get-prop, SUCCESS
11596 00:41:56.827802 test bad-pitch-65536: SUCCESS (0.000s)[0m
11597 00:41:56.830988 Test<14>[ 13.897926] [IGT] kms_addfb_basic: exiting, ret=0
11598 00:41:56.837834 requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11599 00:41:56.847652 <8>[ 13.909668] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop RESULT=pass>
11600 00:41:56.847901 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop RESULT=pass
11602 00:41:56.850996 Test requirement: is_intel_device(fd)
11603 00:41:56.857411 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11604 00:41:56.860746 Test requirement: is_intel_device(fd)
11605 00:41:56.864313 No KMS driver or no outputs, pipes: 16, outputs: 0
11606 00:41:56.873931 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 <14>[ 13.940495] [IGT] kms_addfb_basic: executing
11607 00:41:56.874012 aarch64)
11608 00:41:56.880687 Using IGT_SRANDOM=1718498516 for randomisation
11609 00:41:56.884147 Opened device: /dev/dri/card0
11610 00:41:56.890813 Starting subtest: inval<14>[ 13.955286] [IGT] kms_addfb_basic: starting subtest invalid-set-prop-any
11611 00:41:56.894301 id-get-prop-any
11612 00:41:56.900994 <14>[ 13.962718] [IGT] kms_addfb_basic: finished subtest invalid-set-prop-any, SUCCESS
11613 00:41:56.901073
11614 00:41:56.907591 [1mSubtest invalid-get-prop-any: SUCCESS (0.000s)[0m
11615 00:41:56.910770 Test re<14>[ 13.976402] [IGT] kms_addfb_basic: exiting, ret=0
11616 00:41:56.917504 quirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11617 00:41:56.927427 Tes<8>[ 13.989123] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop-any RESULT=pass>
11618 00:41:56.927678 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop-any RESULT=pass
11620 00:41:56.930685 t requirement: is_intel_device(fd)
11621 00:41:56.937472 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11622 00:41:56.940603 Test requirement: is_intel_device(fd)
11623 00:41:56.943812 N<14>[ 14.010974] [IGT] kms_addfb_basic: executing
11624 00:41:56.950590 o KMS driver or no outputs, pipes: 16, outputs: 0
11625 00:41:56.960298 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aar<14>[ 14.024390] [IGT] kms_addfb_basic: starting subtest invalid-set-prop
11626 00:41:56.960399 ch64)
11627 00:41:56.970051 Using IGT<14>[ 14.032315] [IGT] kms_addfb_basic: finished subtest invalid-set-prop, SUCCESS
11628 00:41:56.973522 _SRANDOM=1718498516 for randomisation
11629 00:41:56.980695 Opened de<14>[ 14.045245] [IGT] kms_addfb_basic: exiting, ret=0
11630 00:41:56.980773 vice: /dev/dri/card0
11631 00:41:56.983706 Starting subtest: invalid-get-prop
11632 00:41:56.993666 [1mSubtest invalid-ge<8>[ 14.056918] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop RESULT=pass>
11633 00:41:56.993914 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop RESULT=pass
11635 00:41:56.996581 t-prop: SUCCESS (0.000s)[0m
11636 00:41:57.003303 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11637 00:41:57.006711 Test requirement: is_intel_device(fd)
11638 00:41:57.013373 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11639 00:41:57.023388 Test requirement: is_intel_device(f<14>[ 14.088024] [IGT] kms_addfb_basic: executing
11640 00:41:57.023467 d)
11641 00:41:57.026425 No KMS driver or no outputs, pipes: 16, outputs: 0
11642 00:41:57.033217 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11643 00:41:57.039802 Using IGT_SRANDOM=17<14>[ 14.104619] [IGT] kms_addfb_basic: starting subtest master-rmfb
11644 00:41:57.049716 18498516 for ran<14>[ 14.112000] [IGT] kms_addfb_basic: finished subtest master-rmfb, SUCCESS
11645 00:41:57.049795 domisation
11646 00:41:57.056512 Opened device: /dev/<14>[ 14.122615] [IGT] kms_addfb_basic: exiting, ret=0
11647 00:41:57.059479 dri/card0
11648 00:41:57.062919 Starting subtest: invalid-set-prop-any
11649 00:41:57.069521 [1mSubtest invalid-set-prop-<8>[ 14.134682] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=master-rmfb RESULT=pass>
11650 00:41:57.069776 Received signal: <TESTCASE> TEST_CASE_ID=master-rmfb RESULT=pass
11652 00:41:57.073050 any: SUCCESS (0.000s)[0m
11653 00:41:57.079380 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11654 00:41:57.082713 Test requirement: is_intel_device(fd)
11655 00:41:57.092977 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11656 00:41:57.096082 Test requirement: is_intel_device(fd)
11657 00:41:57.099594 <14>[ 14.165115] [IGT] kms_addfb_basic: executing
11658 00:41:57.099672
11659 00:41:57.103101 No KMS driver or no outputs, pipes: 16, outputs: 0
11660 00:41:57.109297 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11661 00:41:57.119537 Using IGT_SRANDOM=1718498516 for random<14>[ 14.183944] [IGT] kms_addfb_basic: starting subtest addfb25-modifier-no-flag
11662 00:41:57.122697 isation
11663 00:41:57.129112 Opened <14>[ 14.191736] [IGT] kms_addfb_basic: finished subtest addfb25-modifier-no-flag, SUCCESS
11664 00:41:57.136117 device: /dev/dri<14>[ 14.201504] [IGT] kms_addfb_basic: exiting, ret=0
11665 00:41:57.136196 /card0
11666 00:41:57.139346 Starting subtest: invalid-set-prop
11667 00:41:57.152519 [1mSubtest invalid-set-prop: SUCCES<8>[ 14.214330] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-modifier-no-flag RESULT=pass>
11668 00:41:57.152605 S (0.000s)[0m
11669 00:41:57.152834 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-modifier-no-flag RESULT=pass
11671 00:41:57.158904 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11672 00:41:57.162607 Test requirement: is_intel_device(fd)
11673 00:41:57.172702 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11674 00:41:57.175713 Test requirement: is_intel_device(fd)
11675 00:41:57.179327 No KMS dri<14>[ 14.245607] [IGT] kms_addfb_basic: executing
11676 00:41:57.182225 ver or no outputs, pipes: 16, outputs: 0
11677 00:41:57.188932 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11678 00:41:57.192260 Using IGT_SRANDOM=1718498517 for randomisation
11679 00:41:57.202172 Op<14>[ 14.264669] [IGT] kms_addfb_basic: starting subtest addfb25-bad-modifier
11680 00:41:57.202255 ened device: /dev/dri/card0
11681 00:41:57.205353 Starting subtest: master-rmfb
11682 00:41:57.208700 [1mSubtest master-rmfb: SUCCESS (0.000s)[0m
11683 00:41:57.218723 Test <14>[ 14.280477] [IGT] kms_addfb_basic: finished subtest addfb25-bad-modifier, FAIL
11684 00:41:57.225315 requirement not <14>[ 14.289558] [IGT] kms_addfb_basic: exiting, ret=98
11685 00:41:57.228855 met in function igt_require_intel, file ../lib/drmtest.c:880:
11686 00:41:57.238824 Test requirement:<8>[ 14.302432] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-bad-modifier RESULT=fail>
11687 00:41:57.239078 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-bad-modifier RESULT=fail
11689 00:41:57.242514 is_intel_device(fd)
11690 00:41:57.248701 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11691 00:41:57.252511 Test requirement: is_intel_device(fd)
11692 00:41:57.259147 No KMS driver or no outputs, pi<14>[ 14.324504] [IGT] kms_addfb_basic: executing
11693 00:41:57.262455 pes: 16, outputs: 0
11694 00:41:57.268746 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11695 00:41:57.271960 Using IGT_SRANDOM=1718498517 for randomisation
11696 00:41:57.278755 Opened device: /dev/dri<14>[ 14.343157] [IGT] kms_addfb_basic: exiting, ret=77
11697 00:41:57.278832 /card0
11698 00:41:57.281782 Starting subtest: addfb25-modifier-no-flag
11699 00:41:57.295005 [1mSubtest addfb25-modifier<8>[ 14.356004] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-x-tiled-mismatch-legacy RESULT=skip>
11700 00:41:57.295261 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-x-tiled-mismatch-legacy RESULT=skip
11702 00:41:57.298412 -no-flag: SUCCESS (0.000s)[0m
11703 00:41:57.304726 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11704 00:41:57.307902 Test requirement: is_intel_device(fd)
11705 00:41:57.311357 Test <14>[ 14.378874] [IGT] kms_addfb_basic: executing
11706 00:41:57.317984 requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11707 00:41:57.321376 Test requirement: is_intel_device(fd)
11708 00:41:57.331163 No KMS driver or no outputs, pipes: 16, ou<14>[ 14.396381] [IGT] kms_addfb_basic: exiting, ret=77
11709 00:41:57.331247 tputs: 0
11710 00:41:57.337828 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11711 00:41:57.347527 Us<8>[ 14.409257] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-x-tiled-legacy RESULT=skip>
11712 00:41:57.347778 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-x-tiled-legacy RESULT=skip
11714 00:41:57.351028 ing IGT_SRANDOM=1718498517 for randomisation
11715 00:41:57.354406 Opened device: /dev/dri/card0
11716 00:41:57.357449 Starting subtest: addfb25-bad-modifier
11717 00:41:57.367565 (kms_addfb_basic:438) CRITICAL: Test assertion failure function addfb25_tests, file ../tests/kms_addfb_basic.c:714:
11718 00:41:57.374259 (kms_addfb_basic:438) CRITICAL: Failed<14>[ 14.440485] [IGT] kms_addfb_basic: executing
11719 00:41:57.390264 assertion: igt_ioctl((fd), ((((2U|1U) << (((0+8)+8)+14)) | ((('d')) << (0+8)) | (((0xB8)) << 0) | ((((sizeof(struct drm_mode_fb_cmd2)))) << ((0+8)+8)))), (&f)) == -1
11720 00:41:57.393949 (kms_add<14>[ 14.459795] [IGT] kms_addfb_basic: exiting, ret=77
11721 00:41:57.397079 fb_basic:438) CRITICAL: error: 0 != -1
11722 00:41:57.400144 Stack trace:
11723 00:41:57.413862 #0 ../lib/igt_core.c:1989 __igt_fail_ass<8>[ 14.473299] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-framebuffer-vs-set-tiling RESULT=skip>
11724 00:41:57.413975 ert()
11725 00:41:57.414234 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-framebuffer-vs-set-tiling RESULT=skip
11727 00:41:57.417070 #1 [<unknown>+0xd2634358]
11728 00:41:57.417145 #2 [<unknown>+0xd2635fbc]
11729 00:41:57.420650 #3 [<unknown>+0xd263156c]
11730 00:41:57.423693 #4 [__libc_init_first+0x80]
11731 00:41:57.426840 #5 [__libc_start_main+0x98]
11732 00:41:57.433614 #6 [<unknown>+0xd2<14>[ 14.497508] [IGT] kms_addfb_basic: executing
11733 00:41:57.433694 6315b0]
11734 00:41:57.437121 Subtest addfb25-bad-modifier failed.
11735 00:41:57.437200 **** DEBUG ****
11736 00:41:57.446716 (kms_addfb_basic:438) ioctl_wrappers-DEBUG: Test requirement passed: igt_has_fb_modifiers(fd)
11737 00:41:57.450539 (<14>[ 14.515995] [IGT] kms_addfb_basic: exiting, ret=77
11738 00:41:57.467159 kms_addfb_basic:438) CRITICAL: Test assertion failure function addfb25_tests, fi<8>[ 14.528897] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-x-tiled-legacy RESULT=skip>
11739 00:41:57.467423 Received signal: <TESTCASE> TEST_CASE_ID=basic-x-tiled-legacy RESULT=skip
11741 00:41:57.470112 le ../tests/kms_addfb_basic.c:714:
11742 00:41:57.487088 (kms_addfb_basic:438) CRITICAL: Failed assertion: igt_ioctl((fd), ((((2U|1U) << (((0+8)+8)+14)) | ((('d')) << (0+8)) | (((0xB8)) << 0) | ((((sizeof(struct drm_mode_fb_cmd2)))) << ((0+8)+8)))), (&f)) == -1
11743 00:41:57.493524 (kms_addfb_basic:438) CRITICAL<14>[ 14.559802] [IGT] kms_addfb_basic: executing
11744 00:41:57.496758 : error: 0 != -1
11745 00:41:57.500301 (kms_addfb_basic:438) igt_core-INFO: Stack trace:
11746 00:41:57.506593 (kms_addfb_basic:438) igt_core-INFO: #0 ../lib/igt_core.c:1989 __igt_fail_assert()
11747 00:41:57.513444 (kms_addfb_basic:438)<14>[ 14.579451] [IGT] kms_addfb_basic: exiting, ret=77
11748 00:41:57.520040 igt_core-INFO: #1 [<unknown>+0xd2634358]
11749 00:41:57.529901 (kms_addfb_basic:438) igt_core-INFO<8>[ 14.592576] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=framebuffer-vs-set-tiling RESULT=skip>
11750 00:41:57.530180 Received signal: <TESTCASE> TEST_CASE_ID=framebuffer-vs-set-tiling RESULT=skip
11752 00:41:57.533478 : #2 [<unknown>+0xd2635fbc]
11753 00:41:57.537131 (kms_addfb_basic:438) igt_core-INFO: #3 [<unknown>+0xd263156c]
11754 00:41:57.543748 (kms_addfb_basic:438) igt_core-INFO: #4 [__libc_init_first+0x80]
11755 00:41:57.550230 (kms_addfb_basic:438) igt_core-INFO: #5 [__libc_start_main+0x98]
11756 00:41:57.556470 (kms_addfb_basic:438) igt_core-INFO: <14>[ 14.623756] [IGT] kms_addfb_basic: executing
11757 00:41:57.559802 #6 [<unknown>+0xd26315b0]
11758 00:41:57.563474 **** END ****
11759 00:41:57.566947 [1mSubtest addfb25-bad-modifier: FAIL (0.008s)[0m
11760 00:41:57.579687 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:8<14>[ 14.643316] [IGT] kms_addfb_basic: exiting, ret=77
11761 00:41:57.579774 80:
11762 00:41:57.583096 Test requirement: is_intel_device(fd)
11763 00:41:57.593406 Test requirement not met in function igt_require_int<8>[ 14.657024] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tile-pitch-mismatch RESULT=skip>
11764 00:41:57.593683 Received signal: <TESTCASE> TEST_CASE_ID=tile-pitch-mismatch RESULT=skip
11766 00:41:57.596490 el, file ../lib/drmtest.c:880:
11767 00:41:57.600175 Test requirement: is_intel_device(fd)
11768 00:41:57.606588 No KMS driver or no outputs, pipes: 16, outputs: 0
11769 00:41:57.609812 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11770 00:41:57.616710 Using IGT_SRANDOM=1718498517 for randomisation
11771 00:41:57.616788 Opened device: /dev/dri/card0
11772 00:41:57.623094 Te<14>[ 14.688584] [IGT] kms_addfb_basic: executing
11773 00:41:57.629888 st requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11774 00:41:57.633019 Test requirement: is_intel_device(fd)
11775 00:41:57.643232 [1mSubtest addfb25-x-tiled-mismatch-legacy: SKIP (0.00<14>[ 14.707943] [IGT] kms_addfb_basic: exiting, ret=77
11776 00:41:57.643314 0s)[0m
11777 00:41:57.656730 Test requirement not met in function igt_require_intel,<8>[ 14.719625] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-y-tiled-legacy RESULT=skip>
11778 00:41:57.656985 Received signal: <TESTCASE> TEST_CASE_ID=basic-y-tiled-legacy RESULT=skip
11780 00:41:57.659695 file ../lib/drmtest.c:880:
11781 00:41:57.663094 Test requirement: is_intel_device(fd)
11782 00:41:57.666206 No KMS driver or no outputs, pipes: 16, outputs: 0
11783 00:41:57.673446 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11784 00:41:57.676223 Using IGT_SRANDOM=1718498517 for randomisation
11785 00:41:57.679708 Opened device: /dev/dri/card0
11786 00:41:57.686045 Test requirement not <14>[ 14.751473] [IGT] kms_addfb_basic: executing
11787 00:41:57.692996 met in function igt_require_intel, file ../lib/drmtest.c:880:
11788 00:41:57.696228 Test requirement: is_intel_device(fd)
11789 00:41:57.699781 [1mSubtest addfb25-x-tiled-legacy: SKIP (0.000s)[0m
11790 00:41:57.706278 Test requirement no<14>[ 14.771222] [IGT] kms_addfb_basic: exiting, ret=77
11791 00:41:57.712547 t met in function igt_require_intel, file ../lib/drmtest.c:880:
11792 00:41:57.719500 Test requiremen<8>[ 14.783889] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=size-max RESULT=skip>
11793 00:41:57.719772 Received signal: <TESTCASE> TEST_CASE_ID=size-max RESULT=skip
11795 00:41:57.722666 t: is_intel_device(fd)
11796 00:41:57.726155 No KMS driver or no outputs, pipes: 16, outputs: 0
11797 00:41:57.732802 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11798 00:41:57.736041 Using IGT_SRANDOM=1718498517 for randomisation
11799 00:41:57.739152 Opened device: /dev/dri/card0
11800 00:41:57.749488 Test requirement not met in function igt_require_<14>[ 14.814435] [IGT] kms_addfb_basic: executing
11801 00:41:57.752651 intel, file ../lib/drmtest.c:880:
11802 00:41:57.756416 Test requirement: is_intel_device(fd)
11803 00:41:57.759588 [1mSubtest addfb25-framebuffer-vs-set-tiling: SKIP (0.000s)[0m
11804 00:41:57.769089 Test requirement not met in function<14>[ 14.833445] [IGT] kms_addfb_basic: exiting, ret=77
11805 00:41:57.772220 igt_require_intel, file ../lib/drmtest.c:880:
11806 00:41:57.782125 Test requirement: is_intel_devic<8>[ 14.846747] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=too-wide RESULT=skip>
11807 00:41:57.782205 e(fd)
11808 00:41:57.782433 Received signal: <TESTCASE> TEST_CASE_ID=too-wide RESULT=skip
11810 00:41:57.789079 No KMS driver or no outputs, pipes: 16, outputs: 0
11811 00:41:57.792454 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11812 00:41:57.799010 Using IGT_SRANDOM=1718498517 for randomisation
11813 00:41:57.802364 O<14>[ 14.867715] [IGT] kms_addfb_basic: executing
11814 00:41:57.805863 pened device: /dev/dri/card0
11815 00:41:57.812440 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11816 00:41:57.815567 Test requirement: is_intel_device(fd)
11817 00:41:57.822082 Test re<14>[ 14.886095] [IGT] kms_addfb_basic: exiting, ret=77
11818 00:41:57.828700 quirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11819 00:41:57.835693 Tes<8>[ 14.899049] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=too-high RESULT=skip>
11820 00:41:57.835941 Received signal: <TESTCASE> TEST_CASE_ID=too-high RESULT=skip
11822 00:41:57.838697 t requirement: is_intel_device(fd)
11823 00:41:57.842358 [1mSubtest basic-x-tiled-legacy: SKIP (0.000s)[0m
11824 00:41:57.848433 No KMS driver or no outputs, pipes: 16, outputs: 0
11825 00:41:57.852011 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11826 00:41:57.858709 Using IGT_SRANDOM=1718498517 for randomisation
11827 00:41:57.862007 Opened device: <14>[ 14.929284] [IGT] kms_addfb_basic: executing
11828 00:41:57.864987 /dev/dri/card0
11829 00:41:57.871452 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11830 00:41:57.874785 Test requirement: is_intel_device(fd)
11831 00:41:57.884905 Test requirement not met in function <14>[ 14.948917] [IGT] kms_addfb_basic: exiting, ret=77
11832 00:41:57.887975 igt_require_intel, file ../lib/drmtest.c:880:
11833 00:41:57.898047 Test requirement: is_intel_device<8>[ 14.961728] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bo-too-small RESULT=skip>
11834 00:41:57.898173 (fd)
11835 00:41:57.898401 Received signal: <TESTCASE> TEST_CASE_ID=bo-too-small RESULT=skip
11837 00:41:57.904756 [1mSubtest framebuffer-vs-set-tiling: SKIP (0.000s)[0m
11838 00:41:57.907546 No KMS driver or no outputs, pipes: 16, outputs: 0
11839 00:41:57.918020 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aa<14>[ 14.982849] [IGT] kms_addfb_basic: executing
11840 00:41:57.918129 rch64)
11841 00:41:57.920704 Using IGT_SRANDOM=1718498517 for randomisation
11842 00:41:57.924251 Opened device: /dev/dri/card0
11843 00:41:57.937392 Test requirement not met in function igt_require_intel, file ../lib/drmte<14>[ 15.001387] [IGT] kms_addfb_basic: exiting, ret=77
11844 00:41:57.937503 st.c:880:
11845 00:41:57.940764 Test requirement: is_intel_device(fd)
11846 00:41:57.950962 Test requirement not met in fu<8>[ 15.014230] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=small-bo RESULT=skip>
11847 00:41:57.951221 Received signal: <TESTCASE> TEST_CASE_ID=small-bo RESULT=skip
11849 00:41:57.954208 nction igt_require_intel, file ../lib/drmtest.c:880:
11850 00:41:57.957278 Test requirement: is_intel_device(fd)
11851 00:41:57.964162 [1mSubtest tile-pitch-mismatch: SKIP (0.000s)[0m
11852 00:41:57.970805 No KMS driver or no outputs, pi<14>[ 15.035770] [IGT] kms_addfb_basic: executing
11853 00:41:57.970888 pes: 16, outputs: 0
11854 00:41:57.977319 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11855 00:41:57.981040 Using IGT_SRANDOM=1718498517 for randomisation
11856 00:41:57.991061 Opened device: /dev/dri<14>[ 15.054157] [IGT] kms_addfb_basic: exiting, ret=77
11857 00:41:57.991146 /card0
11858 00:41:58.003814 Test requirement not met in function igt_require_intel, file ../lib/drmt<8>[ 15.067069] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bo-too-small-due-to-tiling RESULT=skip>
11859 00:41:58.003897 est.c:880:
11860 00:41:58.004125 Received signal: <TESTCASE> TEST_CASE_ID=bo-too-small-due-to-tiling RESULT=skip
11862 00:41:58.011038 Test requirement: is_intel_device(fd)
11863 00:41:58.017315 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11864 00:41:58.020432 Test requirement: is_intel_device(fd)
11865 00:41:58.023547 [1mSubtest basic-y-tiled-legacy: SKIP (0.000s)[0m
11866 00:41:58.034033 No KMS driver or no outputs, pipes: 16, outpu<14>[ 15.098897] [IGT] kms_addfb_basic: executing
11867 00:41:58.034117 ts: 0
11868 00:41:58.040205 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11869 00:41:58.043407 Using IGT_SRANDOM=1718498517 for randomisation
11870 00:41:58.047055 Opened device: /dev/dri/card0
11871 00:41:58.053979 Test requirement not m<14>[ 15.118011] [IGT] kms_addfb_basic: exiting, ret=77
11872 00:41:58.060353 et in function igt_require_intel, file ../lib/drmtest.c:880:
11873 00:41:58.066982 Test requirement: <8>[ 15.131298] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-y-tiled-legacy RESULT=skip>
11874 00:41:58.067231 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-y-tiled-legacy RESULT=skip
11876 00:41:58.070409 is_intel_device(fd)
11877 00:41:58.076723 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11878 00:41:58.080518 Test requirement: is_intel_device(fd)
11879 00:41:58.086724 No KMS driver or no outputs, pipes: 16, outputs: 0
11880 00:41:58.090111 [1mSubtest size-max: SKIP (0.000s)[0m
11881 00:41:58.096962 IGT-Version: 1.28-ga44ebfe (aarch64<14>[ 15.162363] [IGT] kms_addfb_basic: executing
11882 00:41:58.100010 ) (Linux: 6.1.92-cip22 aarch64)
11883 00:41:58.103235 Using IGT_SRANDOM=1718498517 for randomisation
11884 00:41:58.106348 Opened device: /dev/dri/card0
11885 00:41:58.116681 Test requirement not met in function igt_require_intel, file ../<14>[ 15.181661] [IGT] kms_addfb_basic: exiting, ret=77
11886 00:41:58.119627 lib/drmtest.c:880:
11887 00:41:58.123472 Test requirement: is_intel_device(fd)
11888 00:41:58.133376 Test requirement not <8>[ 15.194612] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-yf-tiled-legacy RESULT=skip>
11889 00:41:58.133626 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-yf-tiled-legacy RESULT=skip
11891 00:41:58.136168 met in function igt_require_intel, file ../lib/drmtest.c:880:
11892 00:41:58.139736 Test requirement: is_intel_device(fd)
11893 00:41:58.146629 No KMS driver or no outputs, pipes: 16, outputs: 0
11894 00:41:58.149854 [1mSubtest too-wide: SKIP (0.000s)[0m
11895 00:41:58.153030 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11896 00:41:58.159783 Using IGT<14>[ 15.226344] [IGT] kms_addfb_basic: executing
11897 00:41:58.162960 _SRANDOM=1718498517 for randomisation
11898 00:41:58.166155 Opened device: /dev/dri/card0
11899 00:41:58.173254 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11900 00:41:58.179702 Test requirement: is_i<14>[ 15.245389] [IGT] kms_addfb_basic: exiting, ret=77
11901 00:41:58.182972 ntel_device(fd)
11902 00:41:58.196103 Test requirement not met in function igt_require_intel, file ..<8>[ 15.258441] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-y-tiled-small-legacy RESULT=skip>
11903 00:41:58.196188 /lib/drmtest.c:880:
11904 00:41:58.196418 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-y-tiled-small-legacy RESULT=skip
11906 00:41:58.199800 Test requirement: is_intel_device(fd)
11907 00:41:58.206338 No KMS driver or no outputs, pipes: 16, outputs: 0
11908 00:41:58.209396 [1mSubtest too-high: SKIP (0.000s)[0m
11909 00:41:58.216433 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11910 00:41:58.219447 Using IGT_SRANDOM=1718498517 for randomisation
11911 00:41:58.226555 Opened device: /dev<14>[ 15.290753] [IGT] kms_addfb_basic: executing
11912 00:41:58.226635 /dri/card0
11913 00:41:58.232719 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11914 00:41:58.236437 Test requirement: is_intel_device(fd)
11915 00:41:58.246607 Test requirement not met in function igt_<14>[ 15.310710] [IGT] kms_addfb_basic: exiting, ret=77
11916 00:41:58.249758 require_intel, file ../lib/drmtest.c:880:
11917 00:41:58.252940 Test requirement: is_intel_device(fd)
11918 00:41:58.262844 No KMS driver <8>[ 15.324823] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-4-tiled RESULT=skip>
11919 00:41:58.263095 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-4-tiled RESULT=skip
11921 00:41:58.269295 or no outputs, pipes: 16, output<8>[ 15.334429] <LAVA_SIGNAL_TESTSET STOP>
11922 00:41:58.269371 s: 0
11923 00:41:58.269586 Received signal: <TESTSET> STOP
11924 00:41:58.269662 Closing test_set kms_addfb_basic
11925 00:41:58.272874 [1mSubtest bo-too-small: SKIP (0.000s)[0m
11926 00:41:58.279597 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11927 00:41:58.282693 Using IGT_SRANDOM=1718498517 for randomisation
11928 00:41:58.286261 Opened device: /dev/dri/card0
11929 00:41:58.292975 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11930 00:41:58.296094 Test requirement: is_intel_device(fd)
11931 00:41:58.299465 Received signal: <TESTSET> START kms_atomic
11932 00:41:58.299541 Starting test_set kms_atomic
11933 00:41:58.302918 <8>[ 15.366099] <LAVA_SIGNAL_TESTSET START kms_atomic>
11934 00:41:58.302995
11935 00:41:58.309216 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11936 00:41:58.312789 Test requirement: is_intel_device(fd)
11937 00:41:58.316029 No KMS driver or no outputs, pipes: 16, outputs: 0
11938 00:41:58.319300 [1mSubtest small-bo: SKIP (0.000s)[0m
11939 00:41:58.329096 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip<14>[ 15.395110] [IGT] kms_atomic: executing
11940 00:41:58.329179 22 aarch64)
11941 00:41:58.335789 Usi<14>[ 15.400851] [IGT] kms_atomic: exiting, ret=77
11942 00:41:58.339175 ng IGT_SRANDOM=1718498518 for randomisation
11943 00:41:58.342482 Opened device: /dev/dri/card0
11944 00:41:58.349300 Test<8>[ 15.412277] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-overlay-legacy RESULT=skip>
11945 00:41:58.349559 Received signal: <TESTCASE> TEST_CASE_ID=plane-overlay-legacy RESULT=skip
11947 00:41:58.356067 requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11948 00:41:58.359275 Test requirement: is_intel_device(fd)
11949 00:41:58.369229 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11950 00:41:58.372426 Test requirement: is_intel_device(fd)
11951 00:41:58.378660 No KMS driver or no outputs, pipes: 16, output<14>[ 15.444553] [IGT] kms_atomic: executing
11952 00:41:58.378741 s: 0
11953 00:41:58.385738 [1mSubtes<14>[ 15.450881] [IGT] kms_atomic: exiting, ret=77
11954 00:41:58.388689 t bo-too-small-due-to-tiling: SKIP (0.000s)[0m
11955 00:41:58.402190 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch<8>[ 15.465398] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-primary-legacy RESULT=skip>
11956 00:41:58.402276 64)
11957 00:41:58.402507 Received signal: <TESTCASE> TEST_CASE_ID=plane-primary-legacy RESULT=skip
11959 00:41:58.405284 Using IGT_SRANDOM=1718498518 for randomisation
11960 00:41:58.409115 Opened device: /dev/dri/card0
11961 00:41:58.415390 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11962 00:41:58.419114 Test requirement: is_intel_device(fd)
11963 00:41:58.432072 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880<14>[ 15.498442] [IGT] kms_atomic: executing
11964 00:41:58.432154 :
11965 00:41:58.438767 Test requirem<14>[ 15.503593] [IGT] kms_atomic: exiting, ret=77
11966 00:41:58.438846 ent: is_intel_device(fd)
11967 00:41:58.445326 No KMS driver or no outputs, pipes: 16, outputs: 0
11968 00:41:58.455226 [1mSubtest addfb25-y-tiled-legacy<8>[ 15.518609] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-primary-overlay-mutable-zpos RESULT=skip>
11969 00:41:58.455473 Received signal: <TESTCASE> TEST_CASE_ID=plane-primary-overlay-mutable-zpos RESULT=skip
11971 00:41:58.458641 : SKIP (0.000s)[0m
11972 00:41:58.465282 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11973 00:41:58.468390 Using IGT_SRANDOM=1718498518 for randomisation
11974 00:41:58.471699 Opened device: /dev/dri/card0
11975 00:41:58.478671 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11976 00:41:58.485362 Test requirement: is_intel_device(fd<14>[ 15.551349] [IGT] kms_atomic: executing
11977 00:41:58.485439 )
11978 00:41:58.491964 Test requirem<14>[ 15.557608] [IGT] kms_atomic: exiting, ret=77
11979 00:41:58.498512 ent not met in function igt_require_intel, file ../lib/drmtest.c:880:
11980 00:41:58.505313 Test requ<8>[ 15.568955] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-immutable-zpos RESULT=skip>
11981 00:41:58.505569 Received signal: <TESTCASE> TEST_CASE_ID=plane-immutable-zpos RESULT=skip
11983 00:41:58.508645 irement: is_intel_device(fd)
11984 00:41:58.515206 No KMS driver or no outputs, pipes: 16, outputs: 0
11985 00:41:58.518446 [1mSubtest addfb25-yf-tiled-legacy: SKIP (0.000s)[0m
11986 00:41:58.528747 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-ci<14>[ 15.593582] [IGT] kms_atomic: executing
11987 00:41:58.528853 p22 aarch64)
11988 00:41:58.535002 Us<14>[ 15.599033] [IGT] kms_atomic: exiting, ret=77
11989 00:41:58.538589 ing IGT_SRANDOM=1718498518 for randomisation
11990 00:41:58.541905 Opened device: /dev/dri/card0
11991 00:41:58.548234 Tes<8>[ 15.611135] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test-only RESULT=skip>
11992 00:41:58.548486 Received signal: <TESTCASE> TEST_CASE_ID=test-only RESULT=skip
11994 00:41:58.554902 t requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11995 00:41:58.558570 Test requirement: is_intel_device(fd)
11996 00:41:58.565230 Test requirement not met in function igt<14>[ 15.631516] [IGT] kms_atomic: executing
11997 00:41:58.571731 _require_intel, <14>[ 15.637089] [IGT] kms_atomic: exiting, ret=77
11998 00:41:58.574691 file ../lib/drmtest.c:880:
11999 00:41:58.578261 Test requirement: is_intel_device(fd)
12000 00:41:58.585018 No KMS driver<8>[ 15.649130] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-cursor-legacy RESULT=skip>
12001 00:41:58.585286 Received signal: <TESTCASE> TEST_CASE_ID=plane-cursor-legacy RESULT=skip
12003 00:41:58.588296 or no outputs, pipes: 16, outputs: 0
12004 00:41:58.594928 [1mSubtest addfb25-y-tiled-small-legacy: SKIP (0.000s)[0m
12005 00:41:58.601579 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12006 00:41:58.605113 Using IG<14>[ 15.672227] [IGT] kms_atomic: executing
12007 00:41:58.611331 T_SRANDOM=171849<14>[ 15.677279] [IGT] kms_atomic: exiting, ret=77
12008 00:41:58.614507 8518 for randomisation
12009 00:41:58.617675 Opened device: /dev/dri/card0
12010 00:41:58.624879 Received signal: <TESTCASE> TEST_CASE_ID=plane-invalid-params RESULT=skip
12012 00:41:58.627762 Test requirement not met <8>[ 15.689144] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-invalid-params RESULT=skip>
12013 00:41:58.630844 in function igt_require_intel, file ../lib/drmtest.c:880:
12014 00:41:58.634301 Test requirement: is_intel_device(fd)
12015 00:41:58.644532 Test requirement not met in function igt_require_intel, file .<14>[ 15.710867] [IGT] kms_atomic: executing
12016 00:41:58.650651 ./lib/drmtest.c:<14>[ 15.716116] [IGT] kms_atomic: exiting, ret=77
12017 00:41:58.650729 880:
12018 00:41:58.654605 Test requirement: is_intel_device(fd)
12019 00:41:58.664403 No KMS driver or no outputs, pipes:<8>[ 15.728375] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-invalid-params-fence RESULT=skip>
12020 00:41:58.664649 Received signal: <TESTCASE> TEST_CASE_ID=plane-invalid-params-fence RESULT=skip
12022 00:41:58.667716 16, outputs: 0
12023 00:41:58.670972 [1mSubtest addfb25-4-tiled: SKIP (0.000s)[0m
12024 00:41:58.677255 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12025 00:41:58.680845 Using IGT_SRANDOM=1718498518 for randomisation
12026 00:41:58.684083 Opened device: /dev/dri/card0
12027 00:41:58.687489 No KMS driver or no outputs, pipes: 16, outputs: 0
12028 00:41:58.694026 [1mSubt<14>[ 15.760094] [IGT] kms_atomic: executing
12029 00:41:58.700787 est plane-overla<14>[ 15.765653] [IGT] kms_atomic: exiting, ret=77
12030 00:41:58.700866 y-legacy: SKIP (0.000s)[0m
12031 00:41:58.714123 IGT-Version: 1.28-ga44ebfe (aarch64<8>[ 15.776215] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crtc-invalid-params RESULT=skip>
12032 00:41:58.714378 Received signal: <TESTCASE> TEST_CASE_ID=crtc-invalid-params RESULT=skip
12034 00:41:58.717215 ) (Linux: 6.1.92-cip22 aarch64)
12035 00:41:58.720445 Using IGT_SRANDOM=1718498518 for randomisation
12036 00:41:58.723607 Opened device: /dev/dri/card0
12037 00:41:58.727463 No KMS driver or no outputs, pipes: 16, outputs: 0
12038 00:41:58.730645 [1mSubtest plane-primary-legacy: SKIP (0.000s)[0m
12039 00:41:58.737352 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12040 00:41:58.740957 Usi<14>[ 15.807803] [IGT] kms_atomic: executing
12041 00:41:58.747419 ng IGT_SRANDOM=1<14>[ 15.814033] [IGT] kms_atomic: exiting, ret=77
12042 00:41:58.750365 718498518 for randomisation
12043 00:41:58.753879 Opened device: /dev/dri/card0
12044 00:41:58.764086 No KMS driver or no <8>[ 15.825228] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crtc-invalid-params-fence RESULT=skip>
12045 00:41:58.764339 Received signal: <TESTCASE> TEST_CASE_ID=crtc-invalid-params-fence RESULT=skip
12047 00:41:58.767273 outputs, pipes: 16, outputs: 0
12048 00:41:58.770970 [1mSubtest plane-primary-overlay-mutable-zpos: SKIP (0.000s)[0m
12049 00:41:58.781012 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aar<14>[ 15.848346] [IGT] kms_atomic: executing
12050 00:41:58.781095 ch64)
12051 00:41:58.787585 Using IGT<14>[ 15.853109] [IGT] kms_atomic: exiting, ret=77
12052 00:41:58.790603 _SRANDOM=1718498518 for randomisation
12053 00:41:58.800283 Opened device: /dev/dri/c<8>[ 15.864276] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=atomic-invalid-params RESULT=skip>
12054 00:41:58.800365 ard0
12055 00:41:58.800596 Received signal: <TESTCASE> TEST_CASE_ID=atomic-invalid-params RESULT=skip
12057 00:41:58.806855 No KMS driver or no outputs, pipes: 16, outputs: 0
12058 00:41:58.810685 [1mSubtest plane-immutable-zpos: SKIP (0.000s)[0m
12059 00:41:58.820092 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.<14>[ 15.885296] [IGT] kms_atomic: executing
12060 00:41:58.823848 92-cip22 aarch64<14>[ 15.890744] [IGT] kms_atomic: exiting, ret=77
12061 00:41:58.826675 )
12062 00:41:58.830315 Using IGT_SRANDOM=1718498518 for randomisation
12063 00:41:58.840385 Opened device: /dev/dri/card0<8>[ 15.902679] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=atomic-plane-damage RESULT=skip>
12064 00:41:58.840467
12065 00:41:58.840696 Received signal: <TESTCASE> TEST_CASE_ID=atomic-plane-damage RESULT=skip
12067 00:41:58.846990 No KMS driver or no outputs, p<8>[ 15.912555] <LAVA_SIGNAL_TESTSET STOP>
12068 00:41:58.847069 ipes: 16, outputs: 0
12069 00:41:58.847294 Received signal: <TESTSET> STOP
12070 00:41:58.847353 Closing test_set kms_atomic
12071 00:41:58.853315 [1mSubtest test-only: SKIP (0.000s)[0m
12072 00:41:58.856635 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12073 00:41:58.863611 Using IGT_SRANDOM=1718498518 for randomisation
12074 00:41:58.863688 Opened device: /dev/dri/card0
12075 00:41:58.869933 No KMS driver or no outputs, pipes: 16, outputs: 0
12076 00:41:58.873659 [1mSubtest plane-cursor-legacy: SKIP (0.000s)[0m
12077 00:41:58.880218 IGT-V<8>[ 15.944629] <LAVA_SIGNAL_TESTSET START kms_flip_event_leak>
12078 00:41:58.880465 Received signal: <TESTSET> START kms_flip_event_leak
12079 00:41:58.880529 Starting test_set kms_flip_event_leak
12080 00:41:58.886556 ersion: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12081 00:41:58.889843 Using IGT_SRANDOM=1718498518 for randomisation
12082 00:41:58.893186 Opened device: /dev/dri/card0
12083 00:41:58.896742 No KMS driver or no outputs, pipes: 16, outputs: 0
12084 00:41:58.906785 [1mSubtest plane-invalid-params: SKIP (0.000s<14>[ 15.971608] [IGT] kms_flip_event_leak: executing
12085 00:41:58.906866 )[0m
12086 00:41:58.913095 IGT-Versi<14>[ 15.977908] [IGT] kms_flip_event_leak: exiting, ret=77
12087 00:41:58.916696 on: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12088 00:41:58.926706 Using IGT_SRANDOM=1718498518 for rand<8>[ 15.991229] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=skip>
12089 00:41:58.926965 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=skip
12091 00:41:58.930528 omisation
12092 00:41:58.933206 Opened device: /dev/d<8>[ 16.000337] <LAVA_SIGNAL_TESTSET STOP>
12093 00:41:58.933473 Received signal: <TESTSET> STOP
12094 00:41:58.933603 Closing test_set kms_flip_event_leak
12095 00:41:58.936682 ri/card0
12096 00:41:58.939653 No KMS driver or no outputs, pipes: 16, outputs: 0
12097 00:41:58.946612 [1mSubtest plane-invalid-params-fence: SKIP (0.000s)[0m
12098 00:41:58.949736 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12099 00:41:58.956295 Using IGT_SRANDOM=1718498518 for randomisation
12100 00:41:58.956379 Opened device: /dev/dri/card0
12101 00:41:58.962768 No KMS driver or no outputs, pipes: 16, outputs: 0
12102 00:41:58.966406 <8>[ 16.033225] <LAVA_SIGNAL_TESTSET START kms_prop_blob>
12103 00:41:58.966654 Received signal: <TESTSET> START kms_prop_blob
12104 00:41:58.966716 Starting test_set kms_prop_blob
12105 00:41:58.972844 [1mSubtest crtc-invalid-params: SKIP (0.000s)[0m
12106 00:41:58.976066 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12107 00:41:58.982848 Using IGT_SRANDOM=1718498518 for randomisation
12108 00:41:58.986589 Opened device: /dev/dri/card0
12109 00:41:58.989908 No KMS driver or no outputs, pipes: 16, outputs: 0
12110 00:41:58.993214 [1mS<14>[ 16.060464] [IGT] kms_prop_blob: executing
12111 00:41:58.999431 ubtest crtc-inva<14>[ 16.066106] [IGT] kms_prop_blob: starting subtest basic
12112 00:41:59.009792 lid-params-fence<14>[ 16.072556] [IGT] kms_prop_blob: finished subtest basic, SUCCESS
12113 00:41:59.016143 : SKIP (0.000s)<14>[ 16.080356] [IGT] kms_prop_blob: exiting, ret=0
12114 00:41:59.016222 [0m
12115 00:41:59.022655 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12116 00:41:59.029282 Using I<8>[ 16.092383] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=pass>
12117 00:41:59.029529 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=pass
12119 00:41:59.032396 GT_SRANDOM=1718498518 for randomisation
12120 00:41:59.036507 Opened device: /dev/dri/card0
12121 00:41:59.039294 No KMS driver or no outputs, pipes: 16, outputs: 0
12122 00:41:59.045847 [1mSubtest atomic-invalid-params: S<14>[ 16.113726] [IGT] kms_prop_blob: executing
12123 00:41:59.055594 KIP (0.000s)[0m<14>[ 16.118679] [IGT] kms_prop_blob: starting subtest blob-prop-core
12124 00:41:59.055676
12125 00:41:59.062436 IGT-Version: 1<14>[ 16.126105] [IGT] kms_prop_blob: finished subtest blob-prop-core, SUCCESS
12126 00:41:59.069084 .28-ga44ebfe (aa<14>[ 16.134681] [IGT] kms_prop_blob: exiting, ret=0
12127 00:41:59.072432 rch64) (Linux: 6.1.92-cip22 aarch64)
12128 00:41:59.082246 Using IGT_SRANDOM=1718498518 for randomisa<8>[ 16.147142] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-prop-core RESULT=pass>
12129 00:41:59.082500 Received signal: <TESTCASE> TEST_CASE_ID=blob-prop-core RESULT=pass
12131 00:41:59.085456 tion
12132 00:41:59.085535 Opened device: /dev/dri/card0
12133 00:41:59.092328 No KMS driver or no outputs, pipes: 16, outputs: 0
12134 00:41:59.095409 [1mSubtest atomic-plane-damage: SKIP (0.000s)[0m
12135 00:41:59.102306 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12136 00:41:59.105258 Using IGT_SRANDOM=1718498518 for randomisation
12137 00:41:59.112522 Opened device: <14>[ 16.178251] [IGT] kms_prop_blob: executing
12138 00:41:59.112602 /dev/dri/card0
12139 00:41:59.118698 <14>[ 16.183679] [IGT] kms_prop_blob: starting subtest blob-prop-validate
12140 00:41:59.128864 No KMS driver or<14>[ 16.191335] [IGT] kms_prop_blob: finished subtest blob-prop-validate, SUCCESS
12141 00:41:59.135589 no outputs, pip<14>[ 16.200186] [IGT] kms_prop_blob: exiting, ret=0
12142 00:41:59.135672 es: 16, outputs: 0
12143 00:41:59.138727 [1mSubtest basic: SKIP (0.000s)[0m
12144 00:41:59.148616 IGT-Version: 1.28-ga44<8>[ 16.213186] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-prop-validate RESULT=pass>
12145 00:41:59.148869 Received signal: <TESTCASE> TEST_CASE_ID=blob-prop-validate RESULT=pass
12147 00:41:59.152018 ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12148 00:41:59.158670 Using IGT_SRANDOM=1718498519 for randomisation
12149 00:41:59.162018 Opened device: /dev/dri/card0
12150 00:41:59.162097 Starting subtest: basic
12151 00:41:59.168422 [1mSubtes<14>[ 16.234646] [IGT] kms_prop_blob: executing
12152 00:41:59.175257 t basic: SUCCESS<14>[ 16.239740] [IGT] kms_prop_blob: starting subtest blob-prop-lifetime
12153 00:41:59.178833 (0.000s)[0m
12154 00:41:59.185225 I<14>[ 16.247670] [IGT] kms_prop_blob: finished subtest blob-prop-lifetime, SUCCESS
12155 00:41:59.192106 GT-Version: 1.28<14>[ 16.256508] [IGT] kms_prop_blob: exiting, ret=0
12156 00:41:59.195105 -ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12157 00:41:59.205741 Using IGT_SRANDOM=1718498519 <8>[ 16.269169] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-prop-lifetime RESULT=pass>
12158 00:41:59.205995 Received signal: <TESTCASE> TEST_CASE_ID=blob-prop-lifetime RESULT=pass
12160 00:41:59.208666 for randomisation
12161 00:41:59.211809 Opened device: /dev/dri/card0
12162 00:41:59.211888 Starting subtest: blob-prop-core
12163 00:41:59.218422 [1mSubtest blob-prop-core: SUCCESS (0.000s)[0m
12164 00:41:59.225262 IGT-Version: 1.28-ga44ebfe (aarch64) (Linu<14>[ 16.292292] [IGT] kms_prop_blob: executing
12165 00:41:59.234917 x: 6.1.92-cip22 <14>[ 16.297281] [IGT] kms_prop_blob: starting subtest blob-multiple
12166 00:41:59.234997 aarch64)
12167 00:41:59.241566 Using <14>[ 16.304858] [IGT] kms_prop_blob: finished subtest blob-multiple, SUCCESS
12168 00:41:59.248227 IGT_SRANDOM=1718<14>[ 16.313218] [IGT] kms_prop_blob: exiting, ret=0
12169 00:41:59.251325 498519 for randomisation
12170 00:41:59.251402 Opened device: /dev/dri/card0
12171 00:41:59.261517 Starting subtest: blob-<8>[ 16.325543] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-multiple RESULT=pass>
12172 00:41:59.261810 Received signal: <TESTCASE> TEST_CASE_ID=blob-multiple RESULT=pass
12174 00:41:59.264660 prop-validate
12175 00:41:59.267961 [1mSubtest blob-prop-validate: SUCCESS (0.000s)[0m
12176 00:41:59.274641 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12177 00:41:59.278031 Using IGT_SRANDOM=1718498519 for randomisation
12178 00:41:59.281789 Opened device: /dev/dri/card0
12179 00:41:59.284803 Starting subtest: blob-prop-lifetime
12180 00:41:59.287872 [1mSubtest blob-prop-lifetime: SUCCESS (0.000s)[0m
12181 00:41:59.294578 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12182 00:41:59.297807 Using IGT_SRANDOM=1718498519 for randomisation
12183 00:41:59.304838 Opened d<14>[ 16.370048] [IGT] kms_prop_blob: executing
12184 00:41:59.304916 evice: /dev/dri/card0
12185 00:41:59.314476 Starting <14>[ 16.377822] [IGT] kms_prop_blob: starting subtest invalid-get-prop-any
12186 00:41:59.321070 subtest: blob-mu<14>[ 16.385253] [IGT] kms_prop_blob: finished subtest invalid-get-prop-any, SUCCESS
12187 00:41:59.324622 ltiple
12188 00:41:59.327615 [1mSubt<14>[ 16.394260] [IGT] kms_prop_blob: exiting, ret=0
12189 00:41:59.331357 est blob-multiple: SUCCESS (0.000s)[0m
12190 00:41:59.341663 IGT-Version: 1.28-ga44e<8>[ 16.405872] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop-any RESULT=pass>
12191 00:41:59.341916 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop-any RESULT=pass
12193 00:41:59.347632 bfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12194 00:41:59.351446 Using IGT_SRANDOM=1718498519 for randomisation
12195 00:41:59.354468 Opened device: /dev/dri/card0
12196 00:41:59.357354 Starting subtest: invalid-get-prop-any
12197 00:41:59.361275 [1mSubtest <14>[ 16.428213] [IGT] kms_prop_blob: executing
12198 00:41:59.371078 invalid-get-prop<14>[ 16.433964] [IGT] kms_prop_blob: starting subtest invalid-get-prop
12199 00:41:59.377636 -any: SUCCESS (0<14>[ 16.441556] [IGT] kms_prop_blob: finished subtest invalid-get-prop, SUCCESS
12200 00:41:59.381112 .000s)[0m
12201 00:41:59.384199 IGT-<14>[ 16.450403] [IGT] kms_prop_blob: exiting, ret=0
12202 00:41:59.390761 Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12203 00:41:59.397505 <8>[ 16.461114] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop RESULT=pass>
12204 00:41:59.397819 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop RESULT=pass
12206 00:41:59.400581 Using IGT_SRANDOM=1718498519 for randomisation
12207 00:41:59.404366 Opened device: /dev/dri/card0
12208 00:41:59.407327 Starting subtest: invalid-get-prop
12209 00:41:59.417258 [1mSubtest invalid-get-prop: SUCCESS (0.000s<14>[ 16.482529] [IGT] kms_prop_blob: executing
12210 00:41:59.417361 )[0m
12211 00:41:59.424130 <14>[ 16.488229] [IGT] kms_prop_blob: starting subtest invalid-set-prop-any
12212 00:41:59.433888 IGT-Version: 1.2<14>[ 16.495423] [IGT] kms_prop_blob: finished subtest invalid-set-prop-any, SUCCESS
12213 00:41:59.440272 8-ga44ebfe (aarc<14>[ 16.504539] [IGT] kms_prop_blob: exiting, ret=0
12214 00:41:59.443889 h64) (Linux: 6.1.92-cip22 aarch64)
12215 00:41:59.453500 Using IGT_SRANDOM=1718498519<8>[ 16.515276] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop-any RESULT=pass>
12216 00:41:59.453630 for randomisation
12217 00:41:59.453860 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop-any RESULT=pass
12219 00:41:59.457216 Opened device: /dev/dri/card0
12220 00:41:59.460071 Starting subtest: invalid-set-prop-any
12221 00:41:59.466540 [1mSubtest invalid-set-prop-any: SUCCESS (0.000s)[0m
12222 00:41:59.470283 <14>[ 16.537751] [IGT] kms_prop_blob: executing
12223 00:41:59.480105 IGT-Version: 1.2<14>[ 16.542533] [IGT] kms_prop_blob: starting subtest invalid-set-prop
12224 00:41:59.486668 8-ga44ebfe (aarc<14>[ 16.550317] [IGT] kms_prop_blob: finished subtest invalid-set-prop, SUCCESS
12225 00:41:59.493179 h64) (Linux: 6.1<14>[ 16.559102] [IGT] kms_prop_blob: exiting, ret=0
12226 00:41:59.496960 .92-cip22 aarch64)
12227 00:41:59.506670 Using IGT_SRANDOM=1718498519 for randomisati<8>[ 16.569761] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop RESULT=pass>
12228 00:41:59.506754 on
12229 00:41:59.507003 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop RESULT=pass
12231 00:41:59.513382 Opened device: /dev/dri/card<8>[ 16.580547] <LAVA_SIGNAL_TESTSET STOP>
12232 00:41:59.513462 0
12233 00:41:59.513752 Received signal: <TESTSET> STOP
12234 00:41:59.513817 Closing test_set kms_prop_blob
12235 00:41:59.516368 Starting subtest: invalid-set-prop
12236 00:41:59.523504 [1mSubtest invalid-set-prop: SUCCESS (0.000s)[0m
12237 00:41:59.546330 <8>[ 16.612493] <LAVA_SIGNAL_TESTSET START kms_setmode>
12238 00:41:59.546604 Received signal: <TESTSET> START kms_setmode
12239 00:41:59.546676 Starting test_set kms_setmode
12240 00:41:59.566575 <14>[ 16.632571] [IGT] kms_setmode: executing
12241 00:41:59.572914 IGT-Version: 1.2<14>[ 16.637281] [IGT] kms_setmode: starting subtest basic
12242 00:41:59.579699 8-ga44ebfe (aarc<14>[ 16.643880] [IGT] kms_setmode: finished subtest basic, SKIP
12243 00:41:59.586445 h64) (Linux: 6.1<14>[ 16.651234] [IGT] kms_setmode: exiting, ret=77
12244 00:41:59.589560 .92-cip22 aarch64)
12245 00:41:59.592761 Using IGT_SRANDOM=1718498519 for randomisation
12246 00:41:59.599384 Opened devic<8>[ 16.663316] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=skip>
12247 00:41:59.599635 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=skip
12249 00:41:59.602730 e: /dev/dri/card0
12250 00:41:59.602808 Starting subtest: basic
12251 00:41:59.605902 No dynamic tests executed.
12252 00:41:59.609448 [1mSubtest basic: SKIP (0.000s)[0m
12253 00:41:59.619414 <14>[ 16.685869] [IGT] kms_setmode: executing
12254 00:41:59.626422 IGT-Version: 1.2<14>[ 16.690536] [IGT] kms_setmode: starting subtest basic-clone-single-crtc
12255 00:41:59.636586 8-ga44ebfe (aarc<14>[ 16.698681] [IGT] kms_setmode: finished subtest basic-clone-single-crtc, SKIP
12256 00:41:59.642997 h64) (Linux: 6.1<14>[ 16.707606] [IGT] kms_setmode: exiting, ret=77
12257 00:41:59.643080 .92-cip22 aarch64)
12258 00:41:59.656230 Using IGT_SRANDOM=1718498519 for randomisati<8>[ 16.719082] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-clone-single-crtc RESULT=skip>
12259 00:41:59.656318 on
12260 00:41:59.656565 Received signal: <TESTCASE> TEST_CASE_ID=basic-clone-single-crtc RESULT=skip
12262 00:41:59.659914 Opened device: /dev/dri/card0
12263 00:41:59.662904 Starting subtest: basic-clone-single-crtc
12264 00:41:59.666189 No dynamic tests executed.
12265 00:41:59.669369 [1mSubtest basic-clone-single-crtc: SKIP (0.000s)[0m
12266 00:41:59.684233 <14>[ 16.750414] [IGT] kms_setmode: executing
12267 00:41:59.690596 IGT-Version: 1.2<14>[ 16.755330] [IGT] kms_setmode: starting subtest invalid-clone-single-crtc
12268 00:41:59.700689 8-ga44ebfe (aarc<14>[ 16.763581] [IGT] kms_setmode: finished subtest invalid-clone-single-crtc, SKIP
12269 00:41:59.707139 h64) (Linux: 6.1<14>[ 16.772677] [IGT] kms_setmode: exiting, ret=77
12270 00:41:59.710599 .92-cip22 aarch64)
12271 00:41:59.713841 Using IGT_SRANDOM=1718498519 for randomisation
12272 00:41:59.723839 Opened devic<8>[ 16.785643] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-clone-single-crtc RESULT=skip>
12273 00:41:59.723927 e: /dev/dri/card0
12274 00:41:59.724175 Received signal: <TESTCASE> TEST_CASE_ID=invalid-clone-single-crtc RESULT=skip
12276 00:41:59.727417 Starting subtest: invalid-clone-single-crtc
12277 00:41:59.730525 No dynamic tests executed.
12278 00:41:59.737469 [1mSubtest invalid-clone-single-crtc: SKIP (0.000s)[0m
12279 00:41:59.751171 <14>[ 16.817469] [IGT] kms_setmode: executing
12280 00:41:59.761054 IGT-Version: 1.2<14>[ 16.822396] [IGT] kms_setmode: starting subtest invalid-clone-exclusive-crtc
12281 00:41:59.767797 8-ga44ebfe (aarc<14>[ 16.830940] [IGT] kms_setmode: finished subtest invalid-clone-exclusive-crtc, SKIP
12282 00:41:59.774323 h64) (Linux: 6.1<14>[ 16.840273] [IGT] kms_setmode: exiting, ret=77
12283 00:41:59.778065 .92-cip22 aarch64)
12284 00:41:59.781011 Using IGT_SRANDOM=1718498519 for randomisation
12285 00:41:59.791157 Opened device: /dev/dri/card<8>[ 16.853367] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-clone-exclusive-crtc RESULT=skip>
12286 00:41:59.791241 0
12287 00:41:59.791494 Received signal: <TESTCASE> TEST_CASE_ID=invalid-clone-exclusive-crtc RESULT=skip
12289 00:41:59.797660 Starting subtest: invalid-clone-exclusive-crtc
12290 00:41:59.797738 No dynamic tests executed.
12291 00:41:59.804375 [1mSubtest invalid-clone-exclusive-crtc: SKIP (0.000s)[0m
12292 00:41:59.820180 <14>[ 16.886288] [IGT] kms_setmode: executing
12293 00:41:59.826334 IGT-Version: 1.2<14>[ 16.891362] [IGT] kms_setmode: starting subtest clone-exclusive-crtc
12294 00:41:59.836735 8-ga44ebfe (aarc<14>[ 16.899046] [IGT] kms_setmode: finished subtest clone-exclusive-crtc, SKIP
12295 00:41:59.843048 h64) (Linux: 6.1<14>[ 16.907686] [IGT] kms_setmode: exiting, ret=77
12296 00:41:59.843131 .92-cip22 aarch64)
12297 00:41:59.849517 Using IGT_SRANDOM=1718498519 for randomisation
12298 00:41:59.856096 Opened devic<8>[ 16.920578] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clone-exclusive-crtc RESULT=skip>
12299 00:41:59.856349 Received signal: <TESTCASE> TEST_CASE_ID=clone-exclusive-crtc RESULT=skip
12301 00:41:59.859763 e: /dev/dri/card0
12302 00:41:59.862917 Starting subtest: clone-exclusive-crtc
12303 00:41:59.866261 No dynamic tests executed.
12304 00:41:59.869481 [1mSubtest clone-exclusive-crtc: SKIP (0.000s)[0m
12305 00:41:59.885310 <14>[ 16.951697] [IGT] kms_setmode: executing
12306 00:41:59.895601 IGT-Version: 1.2<14>[ 16.956656] [IGT] kms_setmode: starting subtest invalid-clone-single-crtc-stealing
12307 00:41:59.905064 8-ga44ebfe (aarc<14>[ 16.965713] [IGT] kms_setmode: finished subtest invalid-clone-single-crtc-stealing, SKIP
12308 00:41:59.911989 h64) (Linux: 6.1<14>[ 16.975578] [IGT] kms_setmode: exiting, ret=77
12309 00:41:59.912070 .92-cip22 aarch64)
12310 00:41:59.915129 Using IGT_SRANDOM=1718498519 for randomisation
12311 00:41:59.925285 Opened devic<8>[ 16.988480] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-clone-single-crtc-stealing RESULT=skip>
12312 00:41:59.925552 Received signal: <TESTCASE> TEST_CASE_ID=invalid-clone-single-crtc-stealing RESULT=skip
12314 00:41:59.928255 e: /dev/dri/card0
12315 00:41:59.931385 Starting subt<8>[ 16.999372] <LAVA_SIGNAL_TESTSET STOP>
12316 00:41:59.931630 Received signal: <TESTSET> STOP
12317 00:41:59.931697 Closing test_set kms_setmode
12318 00:41:59.934997 est: invalid-clone-single-crtc-stealing
12319 00:41:59.938483 No dynamic tests executed.
12320 00:41:59.944898 [1mSubtest invalid-clone-single-crtc-stealing: SKIP (0.000s)[0m
12321 00:41:59.964940 <8>[ 17.031349] <LAVA_SIGNAL_TESTSET START kms_vblank>
12322 00:41:59.965249 Received signal: <TESTSET> START kms_vblank
12323 00:41:59.965319 Starting test_set kms_vblank
12324 00:41:59.992325 <14>[ 17.058723] [IGT] kms_vblank: executing
12325 00:41:59.999054 IGT-Version: 1.2<14>[ 17.063750] [IGT] kms_vblank: exiting, ret=77
12326 00:42:00.002298 8-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12327 00:42:00.008854 Using IGT_SR<8>[ 17.074891] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid RESULT=skip>
12328 00:42:00.009107 Received signal: <TESTCASE> TEST_CASE_ID=invalid RESULT=skip
12330 00:42:00.012146 ANDOM=1718498520 for randomisation
12331 00:42:00.016003 Opened device: /dev/dri/card0
12332 00:42:00.019034 No KMS driver or no outputs, pipes: 16, outputs: 0
12333 00:42:00.025688 [1mSubtest invalid: SKIP (0.000s)[0m
12334 00:42:00.039381 <14>[ 17.105542] [IGT] kms_vblank: executing
12335 00:42:00.045643 IGT-Version: 1.2<14>[ 17.110545] [IGT] kms_vblank: exiting, ret=77
12336 00:42:00.049200 8-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12337 00:42:00.052157 Using IGT_SRANDOM=1718498520 for randomisation
12338 00:42:00.062315 Opened devic<8>[ 17.125681] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crtc-id RESULT=skip>
12339 00:42:00.062396 e: /dev/dri/card0
12340 00:42:00.062644 Received signal: <TESTCASE> TEST_CASE_ID=crtc-id RESULT=skip
12342 00:42:00.068826 No KMS driver or no outputs, pipes: 16, outputs: 0
12343 00:42:00.071902 [1mSubtest crtc-id: SKIP (0.000s)[0m
12344 00:42:00.080364 <14>[ 17.146834] [IGT] kms_vblank: executing
12345 00:42:00.087174 IGT-Version: 1.2<14>[ 17.151491] [IGT] kms_vblank: exiting, ret=77
12346 00:42:00.090311 8-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12347 00:42:00.100433 Using IGT_SRANDOM=1718498520<8>[ 17.163724] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=accuracy-idle RESULT=skip>
12348 00:42:00.100516 for randomisation
12349 00:42:00.100764 Received signal: <TESTCASE> TEST_CASE_ID=accuracy-idle RESULT=skip
12351 00:42:00.104107 Opened device: /dev/dri/card0
12352 00:42:00.110229 No KMS driver or no outputs, pipes: 16, outputs: 0
12353 00:42:00.113673 [1mSubtest accuracy-idle: SKIP (0.000s)[0m
12354 00:42:00.127738 <14>[ 17.194250] [IGT] kms_vblank: executing
12355 00:42:00.134799 IGT-Version: 1.2<14>[ 17.199325] [IGT] kms_vblank: exiting, ret=77
12356 00:42:00.137794 8-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12357 00:42:00.147869 Using IGT_SRANDOM=1718498520<8>[ 17.210998] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-idle RESULT=skip>
12358 00:42:00.147955 for randomisation
12359 00:42:00.148204 Received signal: <TESTCASE> TEST_CASE_ID=query-idle RESULT=skip
12361 00:42:00.151572 Opened device: /dev/dri/card0
12362 00:42:00.157577 No KMS driver or no outputs, pipes: 16, outputs: 0
12363 00:42:00.160827 [1mSubtest query-idle: SKIP (0.000s)[0m
12364 00:42:00.175246 <14>[ 17.241828] [IGT] kms_vblank: executing
12365 00:42:00.182585 IGT-Version: 1.2<14>[ 17.246797] [IGT] kms_vblank: exiting, ret=77
12366 00:42:00.185609 8-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12367 00:42:00.188760 Using IGT_SRANDOM=1718498520 for randomisation
12368 00:42:00.199239 Opened devic<8>[ 17.261656] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-idle-hang RESULT=skip>
12369 00:42:00.199326 e: /dev/dri/card0
12370 00:42:00.199573 Received signal: <TESTCASE> TEST_CASE_ID=query-idle-hang RESULT=skip
12372 00:42:00.205518 No KMS driver or no outputs, pipes: 16, outputs: 0
12373 00:42:00.208766 [1mSubtest query-idle-hang: SKIP (0.000s)[0m
12374 00:42:00.227264 <14>[ 17.293608] [IGT] kms_vblank: executing
12375 00:42:00.234355 IGT-Version: 1.2<14>[ 17.298639] [IGT] kms_vblank: exiting, ret=77
12376 00:42:00.237460 8-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12377 00:42:00.240992 Using IGT_SRANDOM=1718498520 for randomisation
12378 00:42:00.250668 Opened devic<8>[ 17.313487] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-forked RESULT=skip>
12379 00:42:00.250981 e: /dev/dri/card0
12380 00:42:00.251511 Received signal: <TESTCASE> TEST_CASE_ID=query-forked RESULT=skip
12382 00:42:00.257061 No KMS driver or no outputs, pipes: 16, outputs: 0
12383 00:42:00.260467 [1mSubtest query-forked: SKIP (0.000s)[0m
12384 00:42:00.278222 <14>[ 17.344520] [IGT] kms_vblank: executing
12385 00:42:00.285225 IGT-Version: 1.2<14>[ 17.349506] [IGT] kms_vblank: exiting, ret=77
12386 00:42:00.288267 8-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12387 00:42:00.298404 Using IGT_SRANDOM=1718498520<8>[ 17.361066] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-forked-hang RESULT=skip>
12388 00:42:00.298981 Received signal: <TESTCASE> TEST_CASE_ID=query-forked-hang RESULT=skip
12390 00:42:00.301882 for randomisation
12391 00:42:00.302217 Opened device: /dev/dri/card0
12392 00:42:00.308174 No KMS driver or no outputs, pipes: 16, outputs: 0
12393 00:42:00.311507 [1mSubtest query-forked-hang: SKIP (0.000s)[0m
12394 00:42:00.318277 <14>[ 17.383901] [IGT] kms_vblank: executing
12395 00:42:00.321940 IGT-Version: 1.2<14>[ 17.388657] [IGT] kms_vblank: exiting, ret=77
12396 00:42:00.328266 8-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12397 00:42:00.338164 Using IGT_SRANDOM=1718498520<8>[ 17.400842] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-busy RESULT=skip>
12398 00:42:00.338305 for randomisation
12399 00:42:00.338599 Received signal: <TESTCASE> TEST_CASE_ID=query-busy RESULT=skip
12401 00:42:00.341395 Opened device: /dev/dri/card0
12402 00:42:00.344741 No KMS driver or no outputs, pipes: 16, outputs: 0
12403 00:42:00.347778 [1mSubtest query-busy: SKIP (0.000s)[0m
12404 00:42:00.355529 <14>[ 17.421741] [IGT] kms_vblank: executing
12405 00:42:00.361824 IGT-Version: 1.2<14>[ 17.426361] [IGT] kms_vblank: exiting, ret=77
12406 00:42:00.365471 8-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12407 00:42:00.375443 Using IGT_SRANDOM=1718498520<8>[ 17.438506] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-busy-hang RESULT=skip>
12408 00:42:00.375585 for randomisation
12409 00:42:00.375832 Received signal: <TESTCASE> TEST_CASE_ID=query-busy-hang RESULT=skip
12411 00:42:00.378851 Opened device: /dev/dri/card0
12412 00:42:00.452898 No KMS driver or no outputs, pipes: 16, outputs: 0
12413 00:42:00.453339 [1mSubtest query-busy-hang: SKIP (0.000s)[0m
12414 00:42:00.453662 <14>[ 17.469175] [IGT] kms_vblank: executing
12415 00:42:00.453929 IGT-Version: 1.2<14>[ 17.474217] [IGT] kms_vblank: exiting, ret=77
12416 00:42:00.454178 8-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12417 00:42:00.454424 Using IGT_SRANDOM=1718498520 for randomisation
12418 00:42:00.454661 Opened devic<8>[ 17.489197] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-forked-busy RESULT=skip>
12419 00:42:00.454902 e: /dev/dri/card0
12420 00:42:00.455133 No KMS driver or no outputs, pipes: 16, outputs: 0
12421 00:42:00.455368 [1mSubtest query-forked-busy: SKIP (0.000s)[0m
12422 00:42:00.455844 Received signal: <TESTCASE> TEST_CASE_ID=query-forked-busy RESULT=skip
12424 00:42:00.456696 <14>[ 17.521093] [IGT] kms_vblank: executing
12425 00:42:00.461429 IGT-Version: 1.2<14>[ 17.526013] [IGT] kms_vblank: exiting, ret=77
12426 00:42:00.464902 8-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12427 00:42:00.467942 Using IGT_SRANDOM=1718498520 for randomisation
12428 00:42:00.478282 Opened devic<8>[ 17.541123] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-forked-busy-hang RESULT=skip>
12429 00:42:00.478359 e: /dev/dri/card0
12430 00:42:00.478585 Received signal: <TESTCASE> TEST_CASE_ID=query-forked-busy-hang RESULT=skip
12432 00:42:00.484667 No KMS driver or no outputs, pipes: 16, outputs: 0
12433 00:42:00.487893 [1mSubtest query-forked-busy-hang: SKIP (0.000s)[0m
12434 00:42:00.497013 <14>[ 17.563523] [IGT] kms_vblank: executing
12435 00:42:00.503911 IGT-Version: 1.2<14>[ 17.568172] [IGT] kms_vblank: exiting, ret=77
12436 00:42:00.506852 8-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12437 00:42:00.516924 Using IGT_SRANDOM=1718498520 for randomisati<8>[ 17.581410] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-idle RESULT=skip>
12438 00:42:00.517000 on
12439 00:42:00.517226 Received signal: <TESTCASE> TEST_CASE_ID=wait-idle RESULT=skip
12441 00:42:00.521009 Opened device: /dev/dri/card0
12442 00:42:00.523438 No KMS driver or no outputs, pipes: 16, outputs: 0
12443 00:42:00.530024 [1mSubtest wait-idle: SKIP (0.000s)[0m
12444 00:42:00.546126 <14>[ 17.612413] [IGT] kms_vblank: executing
12445 00:42:00.553028 IGT-Version: 1.2<14>[ 17.617412] [IGT] kms_vblank: exiting, ret=77
12446 00:42:00.556078 8-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12447 00:42:00.566238 Using IGT_SRANDOM=1718498520 for randomisati<8>[ 17.630336] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-idle-hang RESULT=skip>
12448 00:42:00.566315 on
12449 00:42:00.566545 Received signal: <TESTCASE> TEST_CASE_ID=wait-idle-hang RESULT=skip
12451 00:42:00.569568 Opened device: /dev/dri/card0
12452 00:42:00.575900 No KMS driver or no outputs, pipes: 16, outputs: 0
12453 00:42:00.578919 [1mSubtest wait-idle-hang: SKIP (0.000s)[0m
12454 00:42:00.589068 <14>[ 17.655302] [IGT] kms_vblank: executing
12455 00:42:00.595762 IGT-Version: 1.2<14>[ 17.659938] [IGT] kms_vblank: exiting, ret=77
12456 00:42:00.599039 8-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12457 00:42:00.609129 Using IGT_SRANDOM=1718498520<8>[ 17.672368] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-forked RESULT=skip>
12458 00:42:00.609204 for randomisation
12459 00:42:00.609430 Received signal: <TESTCASE> TEST_CASE_ID=wait-forked RESULT=skip
12461 00:42:00.612366 Opened device: /dev/dri/card0
12462 00:42:00.615755 No KMS driver or no outputs, pipes: 16, outputs: 0
12463 00:42:00.621910 [1mSubtest wait-forked: SKIP (0.000s)[0m
12464 00:42:00.636188 <14>[ 17.702581] [IGT] kms_vblank: executing
12465 00:42:00.642648 IGT-Version: 1.2<14>[ 17.707605] [IGT] kms_vblank: exiting, ret=77
12466 00:42:00.646284 8-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12467 00:42:00.649346 Using IGT_SRANDOM=1718498520 for randomisation
12468 00:42:00.659574 Opened devic<8>[ 17.722845] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-forked-hang RESULT=skip>
12469 00:42:00.659652 e: /dev/dri/card0
12470 00:42:00.659880 Received signal: <TESTCASE> TEST_CASE_ID=wait-forked-hang RESULT=skip
12472 00:42:00.666402 No KMS driver or no outputs, pipes: 16, outputs: 0
12473 00:42:00.669538 [1mSubtest wait-forked-hang: SKIP (0.000s)[0m
12474 00:42:00.678274 <14>[ 17.744736] [IGT] kms_vblank: executing
12475 00:42:00.684915 IGT-Version: 1.2<14>[ 17.749578] [IGT] kms_vblank: exiting, ret=77
12476 00:42:00.688722 8-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12477 00:42:00.698033 Using IGT_SRANDOM=1718498520<8>[ 17.761617] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-busy RESULT=skip>
12478 00:42:00.698110 for randomisation
12479 00:42:00.698336 Received signal: <TESTCASE> TEST_CASE_ID=wait-busy RESULT=skip
12481 00:42:00.701908 Opened device: /dev/dri/card0
12482 00:42:00.705043 No KMS driver or no outputs, pipes: 16, outputs: 0
12483 00:42:00.711776 [1mSubtest wait-busy: SKIP (0.000s)[0m
12484 00:42:00.725782 <14>[ 17.792015] [IGT] kms_vblank: executing
12485 00:42:00.732190 IGT-Version: 1.2<14>[ 17.797009] [IGT] kms_vblank: exiting, ret=77
12486 00:42:00.735655 8-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12487 00:42:00.739069 Using IGT_SRANDOM=1718498520 for randomisation
12488 00:42:00.748888 Opened devic<8>[ 17.811792] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-busy-hang RESULT=skip>
12489 00:42:00.748966 e: /dev/dri/card0
12490 00:42:00.749193 Received signal: <TESTCASE> TEST_CASE_ID=wait-busy-hang RESULT=skip
12492 00:42:00.755397 No KMS driver or no outputs, pipes: 16, outputs: 0
12493 00:42:00.759013 [1mSubtest wait-busy-hang: SKIP (0.000s)[0m
12494 00:42:00.777223 <14>[ 17.843370] [IGT] kms_vblank: executing
12495 00:42:00.783400 IGT-Version: 1.2<14>[ 17.848831] [IGT] kms_vblank: exiting, ret=77
12496 00:42:00.786988 8-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12497 00:42:00.790440 Using IGT_SRANDOM=1718498520 for randomisation
12498 00:42:00.800752 Opened devic<8>[ 17.863634] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-forked-busy RESULT=skip>
12499 00:42:00.800830 e: /dev/dri/card0
12500 00:42:00.801058 Received signal: <TESTCASE> TEST_CASE_ID=wait-forked-busy RESULT=skip
12502 00:42:00.807165 No KMS driver or no outputs, pipes: 16, outputs: 0
12503 00:42:00.810176 [1mSubtest wait-forked-busy: SKIP (0.000s)[0m
12504 00:42:00.828973 <14>[ 17.895572] [IGT] kms_vblank: executing
12505 00:42:00.835913 IGT-Version: 1.2<14>[ 17.900909] [IGT] kms_vblank: exiting, ret=77
12506 00:42:00.838974 8-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12507 00:42:00.852159 Using IGT_SRANDOM=1718498520 for randomisati<8>[ 17.914038] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-forked-busy-hang RESULT=skip>
12508 00:42:00.852236 on
12509 00:42:00.852463 Received signal: <TESTCASE> TEST_CASE_ID=wait-forked-busy-hang RESULT=skip
12511 00:42:00.856042 Opened device: /dev/dri/card0
12512 00:42:00.859195 No KMS driver or no outputs, pipes: 16, outputs: 0
12513 00:42:00.862319 [1mSubtest wait-forked-busy-hang: SKIP (0.000s)[0m
12514 00:42:00.870092 <14>[ 17.936746] [IGT] kms_vblank: executing
12515 00:42:00.876978 IGT-Version: 1.2<14>[ 17.941466] [IGT] kms_vblank: exiting, ret=77
12516 00:42:00.880691 8-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12517 00:42:00.890494 Using IGT_SRANDOM=1718498520<8>[ 17.953669] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-idle RESULT=skip>
12518 00:42:00.890738 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-idle RESULT=skip
12520 00:42:00.893490 for randomisation
12521 00:42:00.893589 Opened device: /dev/dri/card0
12522 00:42:00.900300 No KMS driver or no outputs, pipes: 16, outputs: 0
12523 00:42:00.903476 [1mSubtest ts-continuation-idle: SKIP (0.000s)[0m
12524 00:42:00.910588 <14>[ 17.977308] [IGT] kms_vblank: executing
12525 00:42:00.917331 IGT-Version: 1.2<14>[ 17.981952] [IGT] kms_vblank: exiting, ret=77
12526 00:42:00.920997 8-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12527 00:42:00.930848 Using IGT_SRANDOM=1718498521<8>[ 17.993995] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-idle-hang RESULT=skip>
12528 00:42:00.931093 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-idle-hang RESULT=skip
12530 00:42:00.933880 for randomisation
12531 00:42:00.937632 Opened device: /dev/dri/card0
12532 00:42:00.940732 No KMS driver or no outputs, pipes: 16, outputs: 0
12533 00:42:00.943851 [1mSubtest ts-continuation-idle-hang: SKIP (0.000s)[0m
12534 00:42:00.951691 <14>[ 18.018060] [IGT] kms_vblank: executing
12535 00:42:00.958459 IGT-Version: 1.2<14>[ 18.022831] [IGT] kms_vblank: exiting, ret=77
12536 00:42:00.961412 8-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12537 00:42:00.971373 Using IGT_SRANDOM=1718498521<8>[ 18.034791] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-dpms-rpm RESULT=skip>
12538 00:42:00.971617 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-dpms-rpm RESULT=skip
12540 00:42:00.975100 for randomisation
12541 00:42:00.975174 Opened device: /dev/dri/card0
12542 00:42:00.981732 No KMS driver or no outputs, pipes: 16, outputs: 0
12543 00:42:00.984929 [1mSubtest ts-continuation-dpms-rpm: SKIP (0.000s)[0m
12544 00:42:00.991914 <14>[ 18.058528] [IGT] kms_vblank: executing
12545 00:42:00.998659 IGT-Version: 1.2<14>[ 18.063267] [IGT] kms_vblank: exiting, ret=77
12546 00:42:01.002244 8-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12547 00:42:01.011836 Using IGT_SRANDOM=1718498521<8>[ 18.075602] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-dpms-suspend RESULT=skip>
12548 00:42:01.012080 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-dpms-suspend RESULT=skip
12550 00:42:01.015107 for randomisation
12551 00:42:01.018340 Opened device: /dev/dri/card0
12552 00:42:01.021520 No KMS driver or no outputs, pipes: 16, outputs: 0
12553 00:42:01.028183 [1mSubtest ts-continuation-dpms-suspend: SKIP (0.000s)[0m
12554 00:42:01.040492 <14>[ 18.107251] [IGT] kms_vblank: executing
12555 00:42:01.047419 IGT-Version: 1.2<14>[ 18.112233] [IGT] kms_vblank: exiting, ret=77
12556 00:42:01.051158 8-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12557 00:42:01.060573 Using IGT_SRANDOM=1718498521<8>[ 18.123736] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-suspend RESULT=skip>
12558 00:42:01.060819 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-suspend RESULT=skip
12560 00:42:01.064143 for randomisation
12561 00:42:01.067183 Opened device: /dev/dri/card0
12562 00:42:01.070804 No KMS driver or no outputs, pipes: 16, outputs: 0
12563 00:42:01.073835 [1mSubtest ts-continuation-suspend: SKIP (0.000s)[0m
12564 00:42:01.080668 <14>[ 18.146758] [IGT] kms_vblank: executing
12565 00:42:01.087128 IGT-Version: 1.2<14>[ 18.151416] [IGT] kms_vblank: exiting, ret=77
12566 00:42:01.090850 8-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12567 00:42:01.100242 Using IGT_SRANDOM=1718498521<8>[ 18.163764] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-modeset RESULT=skip>
12568 00:42:01.100486 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-modeset RESULT=skip
12570 00:42:01.103878 for randomisation
12571 00:42:01.103953 Opened device: /dev/dri/card0
12572 00:42:01.110802 No KMS driver or no outputs, pipes: 16, outputs: 0
12573 00:42:01.113870 [1mSubtest ts-continuation-modeset: SKIP (0.000s)[0m
12574 00:42:01.128925 <14>[ 18.195215] [IGT] kms_vblank: executing
12575 00:42:01.135503 IGT-Version: 1.2<14>[ 18.200252] [IGT] kms_vblank: exiting, ret=77
12576 00:42:01.138605 8-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12577 00:42:01.148759 Using IGT_SRANDOM=1718498521<8>[ 18.211679] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-modeset-hang RESULT=skip>
12578 00:42:01.149003 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-modeset-hang RESULT=skip
12580 00:42:01.151935 for randomisation
12581 00:42:01.155469 Opened device: /dev/dri/card0
12582 00:42:01.159187 No KMS driver or no outputs, pipes: 16, outputs: 0
12583 00:42:01.165375 [1mSubtest ts-continuation-modeset-hang: SKIP (0.000s)[0m
12584 00:42:01.168395 <14>[ 18.235528] [IGT] kms_vblank: executing
12585 00:42:01.175541 IGT-Version: 1.2<14>[ 18.240187] [IGT] kms_vblank: exiting, ret=77
12586 00:42:01.178486 8-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12587 00:42:01.188644 Using IGT_SRANDOM=1718498521<8>[ 18.252540] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-modeset-rpm RESULT=skip>
12588 00:42:01.188886 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-modeset-rpm RESULT=skip
12590 00:42:01.191632 for randomisation
12591 00:42:01.195590 Opened devic<8>[ 18.262899] <LAVA_SIGNAL_TESTSET STOP>
12592 00:42:01.195830 Received signal: <TESTSET> STOP
12593 00:42:01.195891 Closing test_set kms_vblank
12594 00:42:01.205094 e: /dev/dri/card<8>[ 18.268832] <LAVA_SIGNAL_ENDRUN 0_igt-kms-mediatek 14368365_1.5.2.3.1>
12595 00:42:01.205168 0
12596 00:42:01.205392 Received signal: <ENDRUN> 0_igt-kms-mediatek 14368365_1.5.2.3.1
12597 00:42:01.205465 Ending use of test pattern.
12598 00:42:01.205518 Ending test lava.0_igt-kms-mediatek (14368365_1.5.2.3.1), duration 6.74
12600 00:42:01.208663 No KMS driver or no outputs, pipes: 16, outputs: 0
12601 00:42:01.215087 [1mSubtest ts-continuation-modeset-rpm: SKIP (0.000s)[0m
12602 00:42:01.215162 + set +x
12603 00:42:01.218404 <LAVA_TEST_RUNNER EXIT>
12604 00:42:01.218656 ok: lava_test_shell seems to have completed
12605 00:42:01.220073 accuracy-idle:
result: skip
set: kms_vblank
addfb25-4-tiled:
result: skip
set: kms_addfb_basic
addfb25-bad-modifier:
result: fail
set: kms_addfb_basic
addfb25-framebuffer-vs-set-tiling:
result: skip
set: kms_addfb_basic
addfb25-modifier-no-flag:
result: pass
set: kms_addfb_basic
addfb25-x-tiled-legacy:
result: skip
set: kms_addfb_basic
addfb25-x-tiled-mismatch-legacy:
result: skip
set: kms_addfb_basic
addfb25-y-tiled-legacy:
result: skip
set: kms_addfb_basic
addfb25-y-tiled-small-legacy:
result: skip
set: kms_addfb_basic
addfb25-yf-tiled-legacy:
result: skip
set: kms_addfb_basic
atomic-invalid-params:
result: skip
set: kms_atomic
atomic-plane-damage:
result: skip
set: kms_atomic
bad-pitch-0:
result: pass
set: kms_addfb_basic
bad-pitch-1024:
result: pass
set: kms_addfb_basic
bad-pitch-128:
result: pass
set: kms_addfb_basic
bad-pitch-256:
result: pass
set: kms_addfb_basic
bad-pitch-32:
result: pass
set: kms_addfb_basic
bad-pitch-63:
result: pass
set: kms_addfb_basic
bad-pitch-65536:
result: pass
set: kms_addfb_basic
bad-pitch-999:
result: pass
set: kms_addfb_basic
basic:
result: skip
set: kms_setmode
basic-auth:
result: pass
set: core_auth
basic-clone-single-crtc:
result: skip
set: kms_setmode
basic-x-tiled-legacy:
result: skip
set: kms_addfb_basic
basic-y-tiled-legacy:
result: skip
set: kms_addfb_basic
blob-multiple:
result: pass
set: kms_prop_blob
blob-prop-core:
result: pass
set: kms_prop_blob
blob-prop-lifetime:
result: pass
set: kms_prop_blob
blob-prop-validate:
result: pass
set: kms_prop_blob
bo-too-small:
result: skip
set: kms_addfb_basic
bo-too-small-due-to-tiling:
result: skip
set: kms_addfb_basic
clobberred-modifier:
result: skip
set: kms_addfb_basic
clone-exclusive-crtc:
result: skip
set: kms_setmode
core_getclient: pass
core_getstats: pass
core_getversion: pass
core_setmaster_vs_auth: pass
crtc-id:
result: skip
set: kms_vblank
crtc-invalid-params:
result: skip
set: kms_atomic
crtc-invalid-params-fence:
result: skip
set: kms_atomic
empty-block:
result: skip
set: drm_read
empty-nonblock:
result: skip
set: drm_read
fault-buffer:
result: skip
set: drm_read
framebuffer-vs-set-tiling:
result: skip
set: kms_addfb_basic
getclient-master-drop:
result: pass
set: core_auth
getclient-simple:
result: pass
set: core_auth
invalid:
result: skip
set: kms_vblank
invalid-buffer:
result: skip
set: drm_read
invalid-clone-exclusive-crtc:
result: skip
set: kms_setmode
invalid-clone-single-crtc:
result: skip
set: kms_setmode
invalid-clone-single-crtc-stealing:
result: skip
set: kms_setmode
invalid-get-prop:
result: pass
set: kms_prop_blob
invalid-get-prop-any:
result: pass
set: kms_prop_blob
invalid-set-prop:
result: pass
set: kms_prop_blob
invalid-set-prop-any:
result: pass
set: kms_prop_blob
invalid-smem-bo-on-discrete:
result: skip
set: kms_addfb_basic
legacy-format:
result: pass
set: kms_addfb_basic
many-magics:
result: pass
set: core_auth
master-rmfb:
result: pass
set: kms_addfb_basic
no-handle:
result: pass
set: kms_addfb_basic
plane-cursor-legacy:
result: skip
set: kms_atomic
plane-immutable-zpos:
result: skip
set: kms_atomic
plane-invalid-params:
result: skip
set: kms_atomic
plane-invalid-params-fence:
result: skip
set: kms_atomic
plane-overlay-legacy:
result: skip
set: kms_atomic
plane-primary-legacy:
result: skip
set: kms_atomic
plane-primary-overlay-mutable-zpos:
result: skip
set: kms_atomic
query-busy:
result: skip
set: kms_vblank
query-busy-hang:
result: skip
set: kms_vblank
query-forked:
result: skip
set: kms_vblank
query-forked-busy:
result: skip
set: kms_vblank
query-forked-busy-hang:
result: skip
set: kms_vblank
query-forked-hang:
result: skip
set: kms_vblank
query-idle:
result: skip
set: kms_vblank
query-idle-hang:
result: skip
set: kms_vblank
short-buffer-block:
result: skip
set: drm_read
short-buffer-nonblock:
result: skip
set: drm_read
short-buffer-wakeup:
result: skip
set: drm_read
size-max:
result: skip
set: kms_addfb_basic
small-bo:
result: skip
set: kms_addfb_basic
test-only:
result: skip
set: kms_atomic
tile-pitch-mismatch:
result: skip
set: kms_addfb_basic
too-high:
result: skip
set: kms_addfb_basic
too-wide:
result: skip
set: kms_addfb_basic
ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
ts-continuation-idle:
result: skip
set: kms_vblank
ts-continuation-idle-hang:
result: skip
set: kms_vblank
ts-continuation-modeset:
result: skip
set: kms_vblank
ts-continuation-modeset-hang:
result: skip
set: kms_vblank
ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
ts-continuation-suspend:
result: skip
set: kms_vblank
unused-handle:
result: pass
set: kms_addfb_basic
unused-modifier:
result: pass
set: kms_addfb_basic
unused-offsets:
result: pass
set: kms_addfb_basic
unused-pitches:
result: pass
set: kms_addfb_basic
wait-busy:
result: skip
set: kms_vblank
wait-busy-hang:
result: skip
set: kms_vblank
wait-forked:
result: skip
set: kms_vblank
wait-forked-busy:
result: skip
set: kms_vblank
wait-forked-busy-hang:
result: skip
set: kms_vblank
wait-forked-hang:
result: skip
set: kms_vblank
wait-idle:
result: skip
set: kms_vblank
wait-idle-hang:
result: skip
set: kms_vblank
12606 00:42:01.220222 end: 3.1 lava-test-shell (duration 00:00:07) [common]
12607 00:42:01.220300 end: 3 lava-test-retry (duration 00:00:07) [common]
12608 00:42:01.220381 start: 4 finalize (timeout 00:07:48) [common]
12609 00:42:01.220458 start: 4.1 power-off (timeout 00:00:30) [common]
12610 00:42:01.220583 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-0', '--port=1', '--command=off']
12611 00:42:03.295248 >> Command sent successfully.
12612 00:42:03.298310 Returned 0 in 2 seconds
12613 00:42:03.398656 end: 4.1 power-off (duration 00:00:02) [common]
12615 00:42:03.398945 start: 4.2 read-feedback (timeout 00:07:45) [common]
12616 00:42:03.399208 Listened to connection for namespace 'common' for up to 1s
12617 00:42:04.400158 Finalising connection for namespace 'common'
12618 00:42:04.400344 Disconnecting from shell: Finalise
12619 00:42:04.400436 / #
12620 00:42:04.500705 end: 4.2 read-feedback (duration 00:00:01) [common]
12621 00:42:04.500853 end: 4 finalize (duration 00:00:03) [common]
12622 00:42:04.500978 Cleaning after the job
12623 00:42:04.501075 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14368365/tftp-deploy-tu_dj_f6/ramdisk
12624 00:42:04.507631 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14368365/tftp-deploy-tu_dj_f6/kernel
12625 00:42:04.522726 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14368365/tftp-deploy-tu_dj_f6/dtb
12626 00:42:04.522919 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14368365/tftp-deploy-tu_dj_f6/modules
12627 00:42:04.528700 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14368365
12628 00:42:04.635988 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14368365
12629 00:42:04.636153 Job finished correctly