Boot log: mt8183-kukui-jacuzzi-juniper-sku16
- Errors: 0
- Kernel Errors: 45
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 89
1 00:42:06.549215 lava-dispatcher, installed at version: 2024.03
2 00:42:06.549432 start: 0 validate
3 00:42:06.549553 Start time: 2024-06-16 00:42:06.549544+00:00 (UTC)
4 00:42:06.549689 Using caching service: 'http://localhost/cache/?uri=%s'
5 00:42:06.549834 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 00:42:06.802567 Using caching service: 'http://localhost/cache/?uri=%s'
7 00:42:06.803342 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22-24-g0315de64ea248%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 00:42:07.057157 Using caching service: 'http://localhost/cache/?uri=%s'
9 00:42:07.058131 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22-24-g0315de64ea248%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8183-kukui-jacuzzi-juniper-sku16.dtb exists
10 00:42:07.312042 Using caching service: 'http://localhost/cache/?uri=%s'
11 00:42:07.312657 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 00:42:07.565233 Using caching service: 'http://localhost/cache/?uri=%s'
13 00:42:07.565369 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22-24-g0315de64ea248%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 00:42:07.567521 validate duration: 1.02
16 00:42:07.567743 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 00:42:07.567850 start: 1.1 download-retry (timeout 00:10:00) [common]
18 00:42:07.567944 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 00:42:07.568114 Not decompressing ramdisk as can be used compressed.
20 00:42:07.568217 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 00:42:07.568290 saving as /var/lib/lava/dispatcher/tmp/14368368/tftp-deploy-pdqfsrpp/ramdisk/initrd.cpio.gz
22 00:42:07.568359 total size: 5628169 (5 MB)
23 00:42:07.569281 progress 0 % (0 MB)
24 00:42:07.570888 progress 5 % (0 MB)
25 00:42:07.572423 progress 10 % (0 MB)
26 00:42:07.573778 progress 15 % (0 MB)
27 00:42:07.575319 progress 20 % (1 MB)
28 00:42:07.576689 progress 25 % (1 MB)
29 00:42:07.578200 progress 30 % (1 MB)
30 00:42:07.579694 progress 35 % (1 MB)
31 00:42:07.581031 progress 40 % (2 MB)
32 00:42:07.582567 progress 45 % (2 MB)
33 00:42:07.583894 progress 50 % (2 MB)
34 00:42:07.585387 progress 55 % (2 MB)
35 00:42:07.586918 progress 60 % (3 MB)
36 00:42:07.588246 progress 65 % (3 MB)
37 00:42:07.589734 progress 70 % (3 MB)
38 00:42:07.591118 progress 75 % (4 MB)
39 00:42:07.592600 progress 80 % (4 MB)
40 00:42:07.593924 progress 85 % (4 MB)
41 00:42:07.595453 progress 90 % (4 MB)
42 00:42:07.596943 progress 95 % (5 MB)
43 00:42:07.598338 progress 100 % (5 MB)
44 00:42:07.598549 5 MB downloaded in 0.03 s (177.87 MB/s)
45 00:42:07.598695 end: 1.1.1 http-download (duration 00:00:00) [common]
47 00:42:07.598916 end: 1.1 download-retry (duration 00:00:00) [common]
48 00:42:07.598996 start: 1.2 download-retry (timeout 00:10:00) [common]
49 00:42:07.599071 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 00:42:07.599201 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-24-g0315de64ea248/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 00:42:07.599267 saving as /var/lib/lava/dispatcher/tmp/14368368/tftp-deploy-pdqfsrpp/kernel/Image
52 00:42:07.599321 total size: 54813184 (52 MB)
53 00:42:07.599375 No compression specified
54 00:42:07.600344 progress 0 % (0 MB)
55 00:42:07.614065 progress 5 % (2 MB)
56 00:42:07.627829 progress 10 % (5 MB)
57 00:42:07.641608 progress 15 % (7 MB)
58 00:42:07.655381 progress 20 % (10 MB)
59 00:42:07.669025 progress 25 % (13 MB)
60 00:42:07.682589 progress 30 % (15 MB)
61 00:42:07.696266 progress 35 % (18 MB)
62 00:42:07.709956 progress 40 % (20 MB)
63 00:42:07.723633 progress 45 % (23 MB)
64 00:42:07.737404 progress 50 % (26 MB)
65 00:42:07.751146 progress 55 % (28 MB)
66 00:42:07.764730 progress 60 % (31 MB)
67 00:42:07.778502 progress 65 % (34 MB)
68 00:42:07.792064 progress 70 % (36 MB)
69 00:42:07.805732 progress 75 % (39 MB)
70 00:42:07.819543 progress 80 % (41 MB)
71 00:42:07.833119 progress 85 % (44 MB)
72 00:42:07.846855 progress 90 % (47 MB)
73 00:42:07.860410 progress 95 % (49 MB)
74 00:42:07.873701 progress 100 % (52 MB)
75 00:42:07.873932 52 MB downloaded in 0.27 s (190.36 MB/s)
76 00:42:07.874084 end: 1.2.1 http-download (duration 00:00:00) [common]
78 00:42:07.874298 end: 1.2 download-retry (duration 00:00:00) [common]
79 00:42:07.874380 start: 1.3 download-retry (timeout 00:10:00) [common]
80 00:42:07.874456 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 00:42:07.874585 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-24-g0315de64ea248/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8183-kukui-jacuzzi-juniper-sku16.dtb
82 00:42:07.874647 saving as /var/lib/lava/dispatcher/tmp/14368368/tftp-deploy-pdqfsrpp/dtb/mt8183-kukui-jacuzzi-juniper-sku16.dtb
83 00:42:07.874700 total size: 57695 (0 MB)
84 00:42:07.874752 No compression specified
85 00:42:07.875883 progress 56 % (0 MB)
86 00:42:07.876149 progress 100 % (0 MB)
87 00:42:07.876348 0 MB downloaded in 0.00 s (33.44 MB/s)
88 00:42:07.876475 end: 1.3.1 http-download (duration 00:00:00) [common]
90 00:42:07.876703 end: 1.3 download-retry (duration 00:00:00) [common]
91 00:42:07.876791 start: 1.4 download-retry (timeout 00:10:00) [common]
92 00:42:07.876881 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 00:42:07.876996 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 00:42:07.877060 saving as /var/lib/lava/dispatcher/tmp/14368368/tftp-deploy-pdqfsrpp/nfsrootfs/full.rootfs.tar
95 00:42:07.877146 total size: 120894716 (115 MB)
96 00:42:07.877234 Using unxz to decompress xz
97 00:42:07.878831 progress 0 % (0 MB)
98 00:42:08.225512 progress 5 % (5 MB)
99 00:42:08.567214 progress 10 % (11 MB)
100 00:42:08.905838 progress 15 % (17 MB)
101 00:42:09.226933 progress 20 % (23 MB)
102 00:42:09.531276 progress 25 % (28 MB)
103 00:42:09.877524 progress 30 % (34 MB)
104 00:42:10.199220 progress 35 % (40 MB)
105 00:42:10.369469 progress 40 % (46 MB)
106 00:42:10.550423 progress 45 % (51 MB)
107 00:42:10.851518 progress 50 % (57 MB)
108 00:42:11.203807 progress 55 % (63 MB)
109 00:42:11.538143 progress 60 % (69 MB)
110 00:42:11.875708 progress 65 % (74 MB)
111 00:42:12.211809 progress 70 % (80 MB)
112 00:42:12.555457 progress 75 % (86 MB)
113 00:42:12.880772 progress 80 % (92 MB)
114 00:42:13.214858 progress 85 % (98 MB)
115 00:42:13.546947 progress 90 % (103 MB)
116 00:42:13.862618 progress 95 % (109 MB)
117 00:42:14.210323 progress 100 % (115 MB)
118 00:42:14.215668 115 MB downloaded in 6.34 s (18.19 MB/s)
119 00:42:14.215821 end: 1.4.1 http-download (duration 00:00:06) [common]
121 00:42:14.216028 end: 1.4 download-retry (duration 00:00:06) [common]
122 00:42:14.216106 start: 1.5 download-retry (timeout 00:09:53) [common]
123 00:42:14.216180 start: 1.5.1 http-download (timeout 00:09:53) [common]
124 00:42:14.216307 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-24-g0315de64ea248/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 00:42:14.216366 saving as /var/lib/lava/dispatcher/tmp/14368368/tftp-deploy-pdqfsrpp/modules/modules.tar
126 00:42:14.216419 total size: 8608736 (8 MB)
127 00:42:14.216473 Using unxz to decompress xz
128 00:42:14.217709 progress 0 % (0 MB)
129 00:42:14.236032 progress 5 % (0 MB)
130 00:42:14.261639 progress 10 % (0 MB)
131 00:42:14.288549 progress 15 % (1 MB)
132 00:42:14.311499 progress 20 % (1 MB)
133 00:42:14.334670 progress 25 % (2 MB)
134 00:42:14.357938 progress 30 % (2 MB)
135 00:42:14.381550 progress 35 % (2 MB)
136 00:42:14.407114 progress 40 % (3 MB)
137 00:42:14.429508 progress 45 % (3 MB)
138 00:42:14.453050 progress 50 % (4 MB)
139 00:42:14.477690 progress 55 % (4 MB)
140 00:42:14.501095 progress 60 % (4 MB)
141 00:42:14.524540 progress 65 % (5 MB)
142 00:42:14.548544 progress 70 % (5 MB)
143 00:42:14.573466 progress 75 % (6 MB)
144 00:42:14.598466 progress 80 % (6 MB)
145 00:42:14.622019 progress 85 % (7 MB)
146 00:42:14.646431 progress 90 % (7 MB)
147 00:42:14.670485 progress 95 % (7 MB)
148 00:42:14.694158 progress 100 % (8 MB)
149 00:42:14.699357 8 MB downloaded in 0.48 s (17.00 MB/s)
150 00:42:14.699562 end: 1.5.1 http-download (duration 00:00:00) [common]
152 00:42:14.699887 end: 1.5 download-retry (duration 00:00:00) [common]
153 00:42:14.700001 start: 1.6 prepare-tftp-overlay (timeout 00:09:53) [common]
154 00:42:14.700115 start: 1.6.1 extract-nfsrootfs (timeout 00:09:53) [common]
155 00:42:18.218510 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/14368368/extract-nfsrootfs-vnd37feq
156 00:42:18.218694 end: 1.6.1 extract-nfsrootfs (duration 00:00:04) [common]
157 00:42:18.218788 start: 1.6.2 lava-overlay (timeout 00:09:49) [common]
158 00:42:18.218952 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14368368/lava-overlay-lewf955e
159 00:42:18.219069 makedir: /var/lib/lava/dispatcher/tmp/14368368/lava-overlay-lewf955e/lava-14368368/bin
160 00:42:18.219160 makedir: /var/lib/lava/dispatcher/tmp/14368368/lava-overlay-lewf955e/lava-14368368/tests
161 00:42:18.219247 makedir: /var/lib/lava/dispatcher/tmp/14368368/lava-overlay-lewf955e/lava-14368368/results
162 00:42:18.219329 Creating /var/lib/lava/dispatcher/tmp/14368368/lava-overlay-lewf955e/lava-14368368/bin/lava-add-keys
163 00:42:18.219457 Creating /var/lib/lava/dispatcher/tmp/14368368/lava-overlay-lewf955e/lava-14368368/bin/lava-add-sources
164 00:42:18.219575 Creating /var/lib/lava/dispatcher/tmp/14368368/lava-overlay-lewf955e/lava-14368368/bin/lava-background-process-start
165 00:42:18.219691 Creating /var/lib/lava/dispatcher/tmp/14368368/lava-overlay-lewf955e/lava-14368368/bin/lava-background-process-stop
166 00:42:18.219817 Creating /var/lib/lava/dispatcher/tmp/14368368/lava-overlay-lewf955e/lava-14368368/bin/lava-common-functions
167 00:42:18.219932 Creating /var/lib/lava/dispatcher/tmp/14368368/lava-overlay-lewf955e/lava-14368368/bin/lava-echo-ipv4
168 00:42:18.220045 Creating /var/lib/lava/dispatcher/tmp/14368368/lava-overlay-lewf955e/lava-14368368/bin/lava-install-packages
169 00:42:18.220195 Creating /var/lib/lava/dispatcher/tmp/14368368/lava-overlay-lewf955e/lava-14368368/bin/lava-installed-packages
170 00:42:18.220321 Creating /var/lib/lava/dispatcher/tmp/14368368/lava-overlay-lewf955e/lava-14368368/bin/lava-os-build
171 00:42:18.220433 Creating /var/lib/lava/dispatcher/tmp/14368368/lava-overlay-lewf955e/lava-14368368/bin/lava-probe-channel
172 00:42:18.220546 Creating /var/lib/lava/dispatcher/tmp/14368368/lava-overlay-lewf955e/lava-14368368/bin/lava-probe-ip
173 00:42:18.220686 Creating /var/lib/lava/dispatcher/tmp/14368368/lava-overlay-lewf955e/lava-14368368/bin/lava-target-ip
174 00:42:18.220802 Creating /var/lib/lava/dispatcher/tmp/14368368/lava-overlay-lewf955e/lava-14368368/bin/lava-target-mac
175 00:42:18.220913 Creating /var/lib/lava/dispatcher/tmp/14368368/lava-overlay-lewf955e/lava-14368368/bin/lava-target-storage
176 00:42:18.221028 Creating /var/lib/lava/dispatcher/tmp/14368368/lava-overlay-lewf955e/lava-14368368/bin/lava-test-case
177 00:42:18.221141 Creating /var/lib/lava/dispatcher/tmp/14368368/lava-overlay-lewf955e/lava-14368368/bin/lava-test-event
178 00:42:18.221252 Creating /var/lib/lava/dispatcher/tmp/14368368/lava-overlay-lewf955e/lava-14368368/bin/lava-test-feedback
179 00:42:18.221363 Creating /var/lib/lava/dispatcher/tmp/14368368/lava-overlay-lewf955e/lava-14368368/bin/lava-test-raise
180 00:42:18.221473 Creating /var/lib/lava/dispatcher/tmp/14368368/lava-overlay-lewf955e/lava-14368368/bin/lava-test-reference
181 00:42:18.221585 Creating /var/lib/lava/dispatcher/tmp/14368368/lava-overlay-lewf955e/lava-14368368/bin/lava-test-runner
182 00:42:18.221695 Creating /var/lib/lava/dispatcher/tmp/14368368/lava-overlay-lewf955e/lava-14368368/bin/lava-test-set
183 00:42:18.221805 Creating /var/lib/lava/dispatcher/tmp/14368368/lava-overlay-lewf955e/lava-14368368/bin/lava-test-shell
184 00:42:18.221919 Updating /var/lib/lava/dispatcher/tmp/14368368/lava-overlay-lewf955e/lava-14368368/bin/lava-add-keys (debian)
185 00:42:18.222058 Updating /var/lib/lava/dispatcher/tmp/14368368/lava-overlay-lewf955e/lava-14368368/bin/lava-add-sources (debian)
186 00:42:18.222182 Updating /var/lib/lava/dispatcher/tmp/14368368/lava-overlay-lewf955e/lava-14368368/bin/lava-install-packages (debian)
187 00:42:18.222346 Updating /var/lib/lava/dispatcher/tmp/14368368/lava-overlay-lewf955e/lava-14368368/bin/lava-installed-packages (debian)
188 00:42:18.222467 Updating /var/lib/lava/dispatcher/tmp/14368368/lava-overlay-lewf955e/lava-14368368/bin/lava-os-build (debian)
189 00:42:18.222575 Creating /var/lib/lava/dispatcher/tmp/14368368/lava-overlay-lewf955e/lava-14368368/environment
190 00:42:18.222660 LAVA metadata
191 00:42:18.222723 - LAVA_JOB_ID=14368368
192 00:42:18.222779 - LAVA_DISPATCHER_IP=192.168.201.1
193 00:42:18.222875 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:49) [common]
194 00:42:18.222931 skipped lava-vland-overlay
195 00:42:18.222998 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 00:42:18.223069 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:49) [common]
197 00:42:18.223121 skipped lava-multinode-overlay
198 00:42:18.223184 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 00:42:18.223253 start: 1.6.2.3 test-definition (timeout 00:09:49) [common]
200 00:42:18.223314 Loading test definitions
201 00:42:18.223388 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:49) [common]
202 00:42:18.223444 Using /lava-14368368 at stage 0
203 00:42:18.223714 uuid=14368368_1.6.2.3.1 testdef=None
204 00:42:18.223794 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 00:42:18.223867 start: 1.6.2.3.2 test-overlay (timeout 00:09:49) [common]
206 00:42:18.224262 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 00:42:18.224459 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:49) [common]
209 00:42:18.224950 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 00:42:18.225158 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:49) [common]
212 00:42:18.226160 runner path: /var/lib/lava/dispatcher/tmp/14368368/lava-overlay-lewf955e/lava-14368368/0/tests/0_timesync-off test_uuid 14368368_1.6.2.3.1
213 00:42:18.226364 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 00:42:18.226567 start: 1.6.2.3.5 git-repo-action (timeout 00:09:49) [common]
216 00:42:18.226631 Using /lava-14368368 at stage 0
217 00:42:18.226718 Fetching tests from https://github.com/kernelci/test-definitions.git
218 00:42:18.226796 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/14368368/lava-overlay-lewf955e/lava-14368368/0/tests/1_kselftest-alsa'
219 00:42:20.281096 Running '/usr/bin/git checkout kernelci.org
220 00:42:20.428838 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/14368368/lava-overlay-lewf955e/lava-14368368/0/tests/1_kselftest-alsa/automated/linux/kselftest/kselftest.yaml
221 00:42:20.429197 uuid=14368368_1.6.2.3.5 testdef=None
222 00:42:20.429299 end: 1.6.2.3.5 git-repo-action (duration 00:00:02) [common]
224 00:42:20.429506 start: 1.6.2.3.6 test-overlay (timeout 00:09:47) [common]
225 00:42:20.430153 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 00:42:20.430435 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:47) [common]
228 00:42:20.431549 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 00:42:20.431792 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:47) [common]
231 00:42:20.433227 runner path: /var/lib/lava/dispatcher/tmp/14368368/lava-overlay-lewf955e/lava-14368368/0/tests/1_kselftest-alsa test_uuid 14368368_1.6.2.3.5
232 00:42:20.433342 BOARD='mt8183-kukui-jacuzzi-juniper-sku16'
233 00:42:20.433411 BRANCH='cip'
234 00:42:20.433484 SKIPFILE='/dev/null'
235 00:42:20.433570 SKIP_INSTALL='True'
236 00:42:20.433656 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-24-g0315de64ea248/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 00:42:20.433744 TST_CASENAME=''
238 00:42:20.433862 TST_CMDFILES='alsa'
239 00:42:20.434048 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 00:42:20.434443 Creating lava-test-runner.conf files
242 00:42:20.434535 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14368368/lava-overlay-lewf955e/lava-14368368/0 for stage 0
243 00:42:20.434661 - 0_timesync-off
244 00:42:20.434750 - 1_kselftest-alsa
245 00:42:20.434880 end: 1.6.2.3 test-definition (duration 00:00:02) [common]
246 00:42:20.434993 start: 1.6.2.4 compress-overlay (timeout 00:09:47) [common]
247 00:42:27.521006 end: 1.6.2.4 compress-overlay (duration 00:00:07) [common]
248 00:42:27.521149 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:40) [common]
249 00:42:27.521251 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 00:42:27.521349 end: 1.6.2 lava-overlay (duration 00:00:09) [common]
251 00:42:27.521443 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:40) [common]
252 00:42:27.678433 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 00:42:27.678591 start: 1.6.4 extract-modules (timeout 00:09:40) [common]
254 00:42:27.678693 extracting modules file /var/lib/lava/dispatcher/tmp/14368368/tftp-deploy-pdqfsrpp/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14368368/extract-nfsrootfs-vnd37feq
255 00:42:27.898994 extracting modules file /var/lib/lava/dispatcher/tmp/14368368/tftp-deploy-pdqfsrpp/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14368368/extract-overlay-ramdisk-xpqu1ytv/ramdisk
256 00:42:28.126421 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 00:42:28.126573 start: 1.6.5 apply-overlay-tftp (timeout 00:09:39) [common]
258 00:42:28.126668 [common] Applying overlay to NFS
259 00:42:28.126739 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14368368/compress-overlay-8jxvogpm/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14368368/extract-nfsrootfs-vnd37feq
260 00:42:28.959589 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 00:42:28.959736 start: 1.6.6 configure-preseed-file (timeout 00:09:39) [common]
262 00:42:28.959819 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 00:42:28.959900 start: 1.6.7 compress-ramdisk (timeout 00:09:39) [common]
264 00:42:28.959971 Building ramdisk /var/lib/lava/dispatcher/tmp/14368368/extract-overlay-ramdisk-xpqu1ytv/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14368368/extract-overlay-ramdisk-xpqu1ytv/ramdisk
265 00:42:29.298113 >> 130405 blocks
266 00:42:31.355579 rename /var/lib/lava/dispatcher/tmp/14368368/extract-overlay-ramdisk-xpqu1ytv/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14368368/tftp-deploy-pdqfsrpp/ramdisk/ramdisk.cpio.gz
267 00:42:31.355750 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 00:42:31.355840 start: 1.6.8 prepare-kernel (timeout 00:09:36) [common]
269 00:42:31.355925 start: 1.6.8.1 prepare-fit (timeout 00:09:36) [common]
270 00:42:31.356002 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14368368/tftp-deploy-pdqfsrpp/kernel/Image']
271 00:42:44.586176 Returned 0 in 13 seconds
272 00:42:44.686968 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14368368/tftp-deploy-pdqfsrpp/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14368368/tftp-deploy-pdqfsrpp/dtb/mt8183-kukui-jacuzzi-juniper-sku16.dtb -i /var/lib/lava/dispatcher/tmp/14368368/tftp-deploy-pdqfsrpp/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14368368/tftp-deploy-pdqfsrpp/kernel/image.itb
273 00:42:45.122647 output: FIT description: Kernel Image image with one or more FDT blobs
274 00:42:45.122764 output: Created: Sun Jun 16 01:42:45 2024
275 00:42:45.122827 output: Image 0 (kernel-1)
276 00:42:45.122880 output: Description:
277 00:42:45.122933 output: Created: Sun Jun 16 01:42:45 2024
278 00:42:45.122983 output: Type: Kernel Image
279 00:42:45.123032 output: Compression: lzma compressed
280 00:42:45.123084 output: Data Size: 13126376 Bytes = 12818.73 KiB = 12.52 MiB
281 00:42:45.123135 output: Architecture: AArch64
282 00:42:45.123182 output: OS: Linux
283 00:42:45.123233 output: Load Address: 0x00000000
284 00:42:45.123279 output: Entry Point: 0x00000000
285 00:42:45.123330 output: Hash algo: crc32
286 00:42:45.123381 output: Hash value: c791a20a
287 00:42:45.123435 output: Image 1 (fdt-1)
288 00:42:45.123486 output: Description: mt8183-kukui-jacuzzi-juniper-sku16
289 00:42:45.123538 output: Created: Sun Jun 16 01:42:45 2024
290 00:42:45.123592 output: Type: Flat Device Tree
291 00:42:45.123665 output: Compression: uncompressed
292 00:42:45.123725 output: Data Size: 57695 Bytes = 56.34 KiB = 0.06 MiB
293 00:42:45.123783 output: Architecture: AArch64
294 00:42:45.123835 output: Hash algo: crc32
295 00:42:45.123886 output: Hash value: a9713552
296 00:42:45.123937 output: Image 2 (ramdisk-1)
297 00:42:45.123988 output: Description: unavailable
298 00:42:45.124038 output: Created: Sun Jun 16 01:42:45 2024
299 00:42:45.124088 output: Type: RAMDisk Image
300 00:42:45.124135 output: Compression: uncompressed
301 00:42:45.124181 output: Data Size: 18733210 Bytes = 18294.15 KiB = 17.87 MiB
302 00:42:45.124227 output: Architecture: AArch64
303 00:42:45.124273 output: OS: Linux
304 00:42:45.124319 output: Load Address: unavailable
305 00:42:45.124366 output: Entry Point: unavailable
306 00:42:45.124413 output: Hash algo: crc32
307 00:42:45.124459 output: Hash value: 117461e2
308 00:42:45.124505 output: Default Configuration: 'conf-1'
309 00:42:45.124551 output: Configuration 0 (conf-1)
310 00:42:45.124597 output: Description: mt8183-kukui-jacuzzi-juniper-sku16
311 00:42:45.124643 output: Kernel: kernel-1
312 00:42:45.124689 output: Init Ramdisk: ramdisk-1
313 00:42:45.124736 output: FDT: fdt-1
314 00:42:45.124782 output: Loadables: kernel-1
315 00:42:45.124827 output:
316 00:42:45.124961 end: 1.6.8.1 prepare-fit (duration 00:00:14) [common]
317 00:42:45.125045 end: 1.6.8 prepare-kernel (duration 00:00:14) [common]
318 00:42:45.125134 end: 1.6 prepare-tftp-overlay (duration 00:00:30) [common]
319 00:42:45.125214 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:22) [common]
320 00:42:45.125276 No LXC device requested
321 00:42:45.125343 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 00:42:45.125418 start: 1.8 deploy-device-env (timeout 00:09:22) [common]
323 00:42:45.125484 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 00:42:45.125543 Checking files for TFTP limit of 4294967296 bytes.
325 00:42:45.125984 end: 1 tftp-deploy (duration 00:00:38) [common]
326 00:42:45.126079 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 00:42:45.126161 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 00:42:45.126315 substitutions:
329 00:42:45.126375 - {DTB}: 14368368/tftp-deploy-pdqfsrpp/dtb/mt8183-kukui-jacuzzi-juniper-sku16.dtb
330 00:42:45.126432 - {INITRD}: 14368368/tftp-deploy-pdqfsrpp/ramdisk/ramdisk.cpio.gz
331 00:42:45.126484 - {KERNEL}: 14368368/tftp-deploy-pdqfsrpp/kernel/Image
332 00:42:45.126533 - {LAVA_MAC}: None
333 00:42:45.126582 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/14368368/extract-nfsrootfs-vnd37feq
334 00:42:45.126630 - {NFS_SERVER_IP}: 192.168.201.1
335 00:42:45.126677 - {PRESEED_CONFIG}: None
336 00:42:45.126730 - {PRESEED_LOCAL}: None
337 00:42:45.126778 - {RAMDISK}: 14368368/tftp-deploy-pdqfsrpp/ramdisk/ramdisk.cpio.gz
338 00:42:45.126825 - {ROOT_PART}: None
339 00:42:45.126872 - {ROOT}: None
340 00:42:45.126939 - {SERVER_IP}: 192.168.201.1
341 00:42:45.126990 - {TEE}: None
342 00:42:45.127039 Parsed boot commands:
343 00:42:45.127085 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 00:42:45.127235 Parsed boot commands: tftpboot 192.168.201.1 14368368/tftp-deploy-pdqfsrpp/kernel/image.itb 14368368/tftp-deploy-pdqfsrpp/kernel/cmdline
345 00:42:45.127315 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 00:42:45.127393 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 00:42:45.127471 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 00:42:45.127550 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 00:42:45.127609 Not connected, no need to disconnect.
350 00:42:45.127675 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 00:42:45.127743 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 00:42:45.127804 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8183-kukui-jacuzzi-juniper-sku16-cbg-5'
353 00:42:45.131238 Setting prompt string to ['lava-test: # ']
354 00:42:45.131553 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 00:42:45.131657 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 00:42:45.131756 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 00:42:45.131839 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 00:42:45.132001 Calling: ['/usr/local/bin/chromebook-reboot.sh', 'mt8183-kukui-jacuzzi-juniper-sku16-cbg-5']
359 00:43:07.156054 Returned 0 in 22 seconds
360 00:43:07.256574 end: 2.2.2.1 pdu-reboot (duration 00:00:22) [common]
362 00:43:07.256840 end: 2.2.2 reset-device (duration 00:00:22) [common]
363 00:43:07.256935 start: 2.2.3 depthcharge-start (timeout 00:04:38) [common]
364 00:43:07.257018 Setting prompt string to 'Starting depthcharge on Juniper...'
365 00:43:07.257079 Changing prompt to 'Starting depthcharge on Juniper...'
366 00:43:07.257147 depthcharge-start: Wait for prompt Starting depthcharge on Juniper... (timeout 00:05:00)
367 00:43:07.257572 [Enter `^Ec?' for help]
368 00:43:07.257690 [DL] 00000000 00000000 010701
369 00:43:07.257797
370 00:43:07.257889
371 00:43:07.257977 F0: 102B 0000
372 00:43:07.258061
373 00:43:07.258141 F3: 1006 0033 [0200]
374 00:43:07.258234
375 00:43:07.258294 F3: 4001 00E0 [0200]
376 00:43:07.258350
377 00:43:07.258404 F3: 0000 0000
378 00:43:07.258461
379 00:43:07.258520 V0: 0000 0000 [0001]
380 00:43:07.258582
381 00:43:07.258640 00: 1027 0002
382 00:43:07.258699
383 00:43:07.258758 01: 0000 0000
384 00:43:07.258814
385 00:43:07.258867 BP: 0C00 0251 [0000]
386 00:43:07.258917
387 00:43:07.258966 G0: 1182 0000
388 00:43:07.259014
389 00:43:07.259064 EC: 0004 0000 [0001]
390 00:43:07.259110
391 00:43:07.259156 S7: 0000 0000 [0000]
392 00:43:07.259203
393 00:43:07.259250 CC: 0000 0000 [0001]
394 00:43:07.259296
395 00:43:07.259346 T0: 0000 00DB [000F]
396 00:43:07.259395
397 00:43:07.259441 Jump to BL
398 00:43:07.259488
399 00:43:07.259534
400 00:43:07.259589
401 00:43:07.259638 coreboot-v1.9308_26_0.0.22-10565-g8487d48179 Sun Jan 30 03:25:20 UTC 2022 verstage starting (log level: 8)...
402 00:43:07.259686 ARM64: Exception handlers installed.
403 00:43:07.259734 ARM64: Testing exception
404 00:43:07.259781 ARM64: Done test exception
405 00:43:07.259829 WDT: Last reset was cold boot
406 00:43:07.259879 SPI0(PAD0) initialized at 992727 Hz
407 00:43:07.259928 FMAP: area RW_NVRAM found @ 554000 (8192 bytes)
408 00:43:07.259975 Manufacturer: ef
409 00:43:07.260022 SF: Detected W25Q64DW with sector size 0x1000, total 0x800000
410 00:43:07.260070 Probing TPM: . done!
411 00:43:07.260119 TPM ready after 0 ms
412 00:43:07.260166 Connected to device vid:did:rid of 1ae0:0028:00
413 00:43:07.260214 Firmware version: B2-C:0 RO_B:0.0.11/4d655eab RW_B:0.5.130/cr50_v2.94_mp.110-683b81dc66
414 00:43:07.260262 Initialized TPM device CR50 revision 0
415 00:43:07.260311 tlcl_send_startup: Startup return code is 0
416 00:43:07.260359 TPM: setup succeeded
417 00:43:07.260410 src/security/tpm/tss/tcg-2.0/tss.c:223 index 0x1007 return code 0
418 00:43:07.260460 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
419 00:43:07.260507 in-header: 03 19 00 00 08 00 00 00
420 00:43:07.260554 in-data: a2 e0 47 00 13 00 00 00
421 00:43:07.260600 Chrome EC: UHEPI supported
422 00:43:07.260647 out: cmd=0xa4: 03 5d a4 00 00 00 0c 00 00 01 00 00 f4 fb 00 00 00 00 00 00
423 00:43:07.260698 in-header: 03 a1 00 00 08 00 00 00
424 00:43:07.260745 in-data: 84 60 60 10 00 00 00 00
425 00:43:07.260792 Phase 1
426 00:43:07.260840 FMAP: area GBB found @ 3f5000 (12032 bytes)
427 00:43:07.260887 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x0 / 0x0
428 00:43:07.260935 VB2:vb2_check_recovery() Recovery was requested manually
429 00:43:07.260986 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x0
430 00:43:07.261035 Recovery requested (1009000e)
431 00:43:07.261082 tlcl_extend: response is 0
432 00:43:07.261130 tlcl_extend: response is 0
433 00:43:07.261177
434 00:43:07.261225
435 00:43:07.261272 coreboot-v1.9308_26_0.0.22-10565-g8487d48179 Sun Jan 30 03:25:20 UTC 2022 romstage starting (log level: 8)...
436 00:43:07.261321 ARM64: Exception handlers installed.
437 00:43:07.261369 ARM64: Testing exception
438 00:43:07.261415 ARM64: Done test exception
439 00:43:07.261462 [RTC]rtc_enable_dcxo,41: con=0x482, osc32con=0xaa70, sec=0x2019
440 00:43:07.261512 [RTC]rtc_check_state,142: con=482, pwrkey1=a357, pwrkey2=67d2
441 00:43:07.261562 [RTC]rtc_eosc_cali,157: PMIC_RG_FQMTR_CKSEL=0x4a
442 00:43:07.261610 [RTC]rtc_get_frequency_meter,134: input=0xf, output=777
443 00:43:07.261664 [RTC]rtc_get_frequency_meter,134: input=0x17, output=958
444 00:43:07.261713 [RTC]rtc_get_frequency_meter,134: input=0x13, output=867
445 00:43:07.261763 [RTC]rtc_get_frequency_meter,134: input=0x11, output=823
446 00:43:07.261810 [RTC]rtc_get_frequency_meter,134: input=0x10, output=800
447 00:43:07.261857 [RTC]rtc_get_frequency_meter,134: input=0xf, output=778
448 00:43:07.261904 [RTC]rtc_get_frequency_meter,134: input=0x10, output=801
449 00:43:07.261952 [RTC]rtc_osc_init,208: EOSC32 cali val = 0xaa70
450 00:43:07.261999 [RTC]rtc_boot_common,186: irqsta=0, bbpu=0, con=482
451 00:43:07.262049 [RTC]rtc_bbpu_power_on,373: rtc_write_trigger=1
452 00:43:07.262097 [RTC]rtc_bbpu_power_on,376: done BBPU=0x9
453 00:43:07.262146 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
454 00:43:07.262194 in-header: 03 19 00 00 08 00 00 00
455 00:43:07.262266 in-data: a2 e0 47 00 13 00 00 00
456 00:43:07.262330 Chrome EC: UHEPI supported
457 00:43:07.262377 out: cmd=0xa4: 03 5d a4 00 00 00 0c 00 00 01 00 00 f4 fb 00 00 00 00 00 00
458 00:43:07.262426 in-header: 03 a1 00 00 08 00 00 00
459 00:43:07.262473 in-data: 84 60 60 10 00 00 00 00
460 00:43:07.262520 Skip loading cached calibration data
461 00:43:07.262567 out: cmd=0xa4: 03 7f a4 00 00 00 0c 00 00 01 00 00 d0 ff ff ff 00 00 00 00
462 00:43:07.262617 in-header: 03 a1 00 00 08 00 00 00
463 00:43:07.262666 in-data: 84 60 60 10 00 00 00 00
464 00:43:07.262713 out: cmd=0xa4: 03 79 a4 00 00 00 0c 00 00 01 00 00 f0 7e 11 00 84 60 60 10
465 00:43:07.262761 in-header: 03 a1 00 00 08 00 00 00
466 00:43:07.262809 in-data: 84 60 60 10 00 00 00 00
467 00:43:07.262875 ADC[3]: Raw value=1039942 ID=8
468 00:43:07.262924 Manufacturer: ef
469 00:43:07.262971 SF: Detected W25Q64DW with sector size 0x1000, total 0x800000
470 00:43:07.263019 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
471 00:43:07.263068 CBFS @ 21000 size 3d4000
472 00:43:07.263114 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
473 00:43:07.263165 CBFS: Locating 'sdram-lpddr4x-K4UBE3D4AA-MGCL-4GB'
474 00:43:07.263214 CBFS: Found @ offset 3c880 size 4b
475 00:43:07.263262 DRAM-K: Full Calibration
476 00:43:07.263309 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
477 00:43:07.263360 CBFS @ 21000 size 3d4000
478 00:43:07.263409 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
479 00:43:07.263465 CBFS: Locating 'fallback/dram'
480 00:43:07.263512 CBFS: Found @ offset 24b00 size 12268
481 00:43:07.263558 read SPI 0x45b44 0x1224c: 22775 us, 3263 KB/s, 26.104 Mbps
482 00:43:07.263605 ddr_geometry: 1, config: 0x0
483 00:43:07.263652 header.status = 0x0
484 00:43:07.263700 header.magic = 0x44524d4b (expected: 0x44524d4b)
485 00:43:07.263749 header.version = 0x5 (expected: 0x5)
486 00:43:07.263993 header.size = 0x8f0 (expected: 0x8f0)
487 00:43:07.264083 header.config = 0x0
488 00:43:07.264178 header.flags = 0x0
489 00:43:07.264275 header.checksum = 0x0
490 00:43:07.264372 dram_init: MediaTek DRAM firmware version: 1.5.0, accepting param version 5
491 00:43:07.264459 Set DRAM voltage: vdram1 = 1125000, vddq = 600000
492 00:43:07.264545 Get DRAM voltage to vdram1 = 1125000, vddq = 600000
493 00:43:07.264603 ddr_geometry:1
494 00:43:07.264652 [EMI] new MDL number = 1
495 00:43:07.264699 dram_cbt_mode_extern: 0
496 00:43:07.264777 dram_cbt_mode [RK0]: 0, [RK1]: 0
497 00:43:07.264859 Rank info: 0 emi_setting_index: 1 CONA[0xf053f154]
498 00:43:07.264936
499 00:43:07.265011
500 00:43:07.265089 [Bianco] ETT version 0.0.0.1
501 00:43:07.265166 dram_type 6, R0 cbt_mode 0, R1 cbt_mode 0 VENDOR=6
502 00:43:07.265240
503 00:43:07.265316 vSetVcoreByFreq with vcore:762500, freq=1600
504 00:43:07.265393
505 00:43:07.265469 [DramcInit]
506 00:43:07.265544 AutoRefreshCKEOff AutoREF OFF
507 00:43:07.265618 DDRPhyPLLSetting-CKEOFF
508 00:43:07.265696 DDRPhyPLLSetting-CKEON
509 00:43:07.265770
510 00:43:07.265844 Enable WDQS
511 00:43:07.265924 [ModeRegInit_LP4] CH0 RK0
512 00:43:07.266001 Write Rank0 MR13 =0x18
513 00:43:07.266076 Write Rank0 MR12 =0x5d
514 00:43:07.266151 Write Rank0 MR1 =0x56
515 00:43:07.266232 Write Rank0 MR2 =0x1a
516 00:43:07.266283 Write Rank0 MR11 =0x0
517 00:43:07.266330 Write Rank0 MR22 =0x38
518 00:43:07.266378 Write Rank0 MR14 =0x5d
519 00:43:07.266425 Write Rank0 MR3 =0x30
520 00:43:07.266474 Write Rank0 MR13 =0x58
521 00:43:07.266523 Write Rank0 MR12 =0x5d
522 00:43:07.266571 Write Rank0 MR1 =0x56
523 00:43:07.266632 Write Rank0 MR2 =0x2d
524 00:43:07.266682 Write Rank0 MR11 =0x23
525 00:43:07.266736 Write Rank0 MR22 =0x34
526 00:43:07.266786 Write Rank0 MR14 =0x10
527 00:43:07.266837 Write Rank0 MR3 =0x30
528 00:43:07.266887 Write Rank0 MR13 =0xd8
529 00:43:07.266937 [ModeRegInit_LP4] CH0 RK1
530 00:43:07.266990 Write Rank1 MR13 =0x18
531 00:43:07.267040 Write Rank1 MR12 =0x5d
532 00:43:07.267093 Write Rank1 MR1 =0x56
533 00:43:07.267143 Write Rank1 MR2 =0x1a
534 00:43:07.267194 Write Rank1 MR11 =0x0
535 00:43:07.267244 Write Rank1 MR22 =0x38
536 00:43:07.267297 Write Rank1 MR14 =0x5d
537 00:43:07.267347 Write Rank1 MR3 =0x30
538 00:43:07.267397 Write Rank1 MR13 =0x58
539 00:43:07.267447 Write Rank1 MR12 =0x5d
540 00:43:07.267498 Write Rank1 MR1 =0x56
541 00:43:07.267551 Write Rank1 MR2 =0x2d
542 00:43:07.267603 Write Rank1 MR11 =0x23
543 00:43:07.267659 Write Rank1 MR22 =0x34
544 00:43:07.267713 Write Rank1 MR14 =0x10
545 00:43:07.267765 Write Rank1 MR3 =0x30
546 00:43:07.267815 Write Rank1 MR13 =0xd8
547 00:43:07.267870 [ModeRegInit_LP4] CH1 RK0
548 00:43:07.267920 Write Rank0 MR13 =0x18
549 00:43:07.267970 Write Rank0 MR12 =0x5d
550 00:43:07.268020 Write Rank0 MR1 =0x56
551 00:43:07.268070 Write Rank0 MR2 =0x1a
552 00:43:07.268127 Write Rank0 MR11 =0x0
553 00:43:07.268181 Write Rank0 MR22 =0x38
554 00:43:07.268231 Write Rank0 MR14 =0x5d
555 00:43:07.268282 Write Rank0 MR3 =0x30
556 00:43:07.268331 Write Rank0 MR13 =0x58
557 00:43:07.268386 Write Rank0 MR12 =0x5d
558 00:43:07.268436 Write Rank0 MR1 =0x56
559 00:43:07.268486 Write Rank0 MR2 =0x2d
560 00:43:07.268536 Write Rank0 MR11 =0x23
561 00:43:07.268585 Write Rank0 MR22 =0x34
562 00:43:07.268634 Write Rank0 MR14 =0x10
563 00:43:07.268687 Write Rank0 MR3 =0x30
564 00:43:07.268739 Write Rank0 MR13 =0xd8
565 00:43:07.268789 [ModeRegInit_LP4] CH1 RK1
566 00:43:07.268839 Write Rank1 MR13 =0x18
567 00:43:07.268888 Write Rank1 MR12 =0x5d
568 00:43:07.268940 Write Rank1 MR1 =0x56
569 00:43:07.268990 Write Rank1 MR2 =0x1a
570 00:43:07.269040 Write Rank1 MR11 =0x0
571 00:43:07.269090 Write Rank1 MR22 =0x38
572 00:43:07.269139 Write Rank1 MR14 =0x5d
573 00:43:07.269188 Write Rank1 MR3 =0x30
574 00:43:07.269241 Write Rank1 MR13 =0x58
575 00:43:07.269293 Write Rank1 MR12 =0x5d
576 00:43:07.269343 Write Rank1 MR1 =0x56
577 00:43:07.269393 Write Rank1 MR2 =0x2d
578 00:43:07.269442 Write Rank1 MR11 =0x23
579 00:43:07.269495 Write Rank1 MR22 =0x34
580 00:43:07.269545 Write Rank1 MR14 =0x10
581 00:43:07.269595 Write Rank1 MR3 =0x30
582 00:43:07.269645 Write Rank1 MR13 =0xd8
583 00:43:07.269695 match AC timing 3
584 00:43:07.269748 [DdrUpdateACTimingReg] Freq = 1600, tRFCab = 141, tRFCab_05T = 0, TXREFCNT = 159, tRFCpb = 65, tRFCpb_05T = 0
585 00:43:07.269802 [MiockJmeterHQA]
586 00:43:07.269852 vSetVcoreByFreq with vcore:762500, freq=1600
587 00:43:07.269903
588 00:43:07.269952 MIOCK jitter meter ch=0
589 00:43:07.270003
590 00:43:07.270056 1T = (101-18) = 83 dly cells
591 00:43:07.270108 Clock freq = 1599 MHz, period = 625 ps, 1 dly cell = 753/100 ps
592 00:43:07.270159 vSetVcoreByFreq with vcore:725000, freq=1200
593 00:43:07.270213
594 00:43:07.270268 MIOCK jitter meter ch=0
595 00:43:07.270321
596 00:43:07.270374 1T = (95-17) = 78 dly cells
597 00:43:07.270427 Clock freq = 1599 MHz, period = 625 ps, 1 dly cell = 801/100 ps
598 00:43:07.270478 vSetVcoreByFreq with vcore:725000, freq=800
599 00:43:07.270528
600 00:43:07.270578 MIOCK jitter meter ch=0
601 00:43:07.270627
602 00:43:07.270680 1T = (95-17) = 78 dly cells
603 00:43:07.270731 Clock freq = 1599 MHz, period = 625 ps, 1 dly cell = 801/100 ps
604 00:43:07.270782 vSetVcoreByFreq with vcore:762500, freq=1600
605 00:43:07.270832 vSetVcoreByFreq with vcore:762500, freq=1600
606 00:43:07.270883
607 00:43:07.270936 K DRVP
608 00:43:07.270986 1. OCD DRVP=0 CALOUT=0
609 00:43:07.271040 1. OCD DRVP=1 CALOUT=0
610 00:43:07.271091 1. OCD DRVP=2 CALOUT=0
611 00:43:07.271143 1. OCD DRVP=3 CALOUT=0
612 00:43:07.271193 1. OCD DRVP=4 CALOUT=0
613 00:43:07.271244 1. OCD DRVP=5 CALOUT=0
614 00:43:07.271300 1. OCD DRVP=6 CALOUT=0
615 00:43:07.271351 1. OCD DRVP=7 CALOUT=0
616 00:43:07.271402 1. OCD DRVP=8 CALOUT=1
617 00:43:07.271453
618 00:43:07.271503 1. OCD DRVP calibration OK! DRVP=8
619 00:43:07.271560
620 00:43:07.271614
621 00:43:07.271666
622 00:43:07.271716 K ODTN
623 00:43:07.271766 3. OCD ODTN=0 ,CALOUT=1
624 00:43:07.271820 3. OCD ODTN=1 ,CALOUT=1
625 00:43:07.271872 3. OCD ODTN=2 ,CALOUT=1
626 00:43:07.271926 3. OCD ODTN=3 ,CALOUT=1
627 00:43:07.271977 3. OCD ODTN=4 ,CALOUT=1
628 00:43:07.272028 3. OCD ODTN=5 ,CALOUT=1
629 00:43:07.272078 3. OCD ODTN=6 ,CALOUT=1
630 00:43:07.272135 3. OCD ODTN=7 ,CALOUT=0
631 00:43:07.272191
632 00:43:07.272247 3. OCD ODTN calibration OK! ODTN=7
633 00:43:07.272301
634 00:43:07.272351 [SwImpedanceCal] DRVP=8, DRVN=9, ODTN=7
635 00:43:07.272401 term_option=0, Reg: DRVP=8, DRVN=7, ODTN=15
636 00:43:07.272452 term_option=0, Reg: DRVP=8, DRVN=7, ODTN=15 (After Adjust)
637 00:43:07.272502
638 00:43:07.272555 K DRVP
639 00:43:07.272606 1. OCD DRVP=0 CALOUT=0
640 00:43:07.272657 1. OCD DRVP=1 CALOUT=0
641 00:43:07.272708 1. OCD DRVP=2 CALOUT=0
642 00:43:07.272759 1. OCD DRVP=3 CALOUT=0
643 00:43:07.272819 1. OCD DRVP=4 CALOUT=0
644 00:43:07.272873 1. OCD DRVP=5 CALOUT=0
645 00:43:07.272925 1. OCD DRVP=6 CALOUT=0
646 00:43:07.272976 1. OCD DRVP=7 CALOUT=0
647 00:43:07.273027 1. OCD DRVP=8 CALOUT=0
648 00:43:07.273077 1. OCD DRVP=9 CALOUT=0
649 00:43:07.273128 1. OCD DRVP=10 CALOUT=1
650 00:43:07.273182
651 00:43:07.273424 1. OCD DRVP calibration OK! DRVP=10
652 00:43:07.273535
653 00:43:07.273636
654 00:43:07.273724
655 00:43:07.273808 K ODTN
656 00:43:07.273889 3. OCD ODTN=0 ,CALOUT=1
657 00:43:07.273972 3. OCD ODTN=1 ,CALOUT=1
658 00:43:07.274054 3. OCD ODTN=2 ,CALOUT=1
659 00:43:07.274139 3. OCD ODTN=3 ,CALOUT=1
660 00:43:07.274230 3. OCD ODTN=4 ,CALOUT=1
661 00:43:07.274314 3. OCD ODTN=5 ,CALOUT=1
662 00:43:07.274396 3. OCD ODTN=6 ,CALOUT=1
663 00:43:07.274481 3. OCD ODTN=7 ,CALOUT=1
664 00:43:07.274563 3. OCD ODTN=8 ,CALOUT=1
665 00:43:07.274645 3. OCD ODTN=9 ,CALOUT=1
666 00:43:07.274727 3. OCD ODTN=10 ,CALOUT=1
667 00:43:07.274815 3. OCD ODTN=11 ,CALOUT=1
668 00:43:07.274900 3. OCD ODTN=12 ,CALOUT=1
669 00:43:07.274994 3. OCD ODTN=13 ,CALOUT=1
670 00:43:07.275081 3. OCD ODTN=14 ,CALOUT=1
671 00:43:07.275163 3. OCD ODTN=15 ,CALOUT=0
672 00:43:07.275245
673 00:43:07.275328 3. OCD ODTN calibration OK! ODTN=15
674 00:43:07.275412
675 00:43:07.275493 [SwImpedanceCal] DRVP=10, DRVN=9, ODTN=15
676 00:43:07.275578 term_option=1, Reg: DRVP=10, DRVN=9, ODTN=15
677 00:43:07.275660 term_option=1, Reg: DRVP=10, DRVN=9, ODTN=15 (After Adjust)
678 00:43:07.275740
679 00:43:07.275819 [DramcInit]
680 00:43:07.275902 AutoRefreshCKEOff AutoREF OFF
681 00:43:07.275985 DDRPhyPLLSetting-CKEOFF
682 00:43:07.276065 DDRPhyPLLSetting-CKEON
683 00:43:07.276147
684 00:43:07.276227 Enable WDQS
685 00:43:07.276306 ==
686 00:43:07.276389 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
687 00:43:07.276473 fsp= 1, odt_onoff= 1, Byte mode= 0
688 00:43:07.276555 ==
689 00:43:07.276635 [Duty_Offset_Calibration]
690 00:43:07.276718
691 00:43:07.276797 ===========================
692 00:43:07.276878 B0:1 B1:0 CA:0
693 00:43:07.276960 ==
694 00:43:07.277043 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
695 00:43:07.277124 fsp= 1, odt_onoff= 1, Byte mode= 0
696 00:43:07.277207 ==
697 00:43:07.277287 [Duty_Offset_Calibration]
698 00:43:07.277366
699 00:43:07.277446 ===========================
700 00:43:07.277530 B0:1 B1:0 CA:-1
701 00:43:07.277611 [ModeRegInit_LP4] CH0 RK0
702 00:43:07.277690 Write Rank0 MR13 =0x18
703 00:43:07.277775 Write Rank0 MR12 =0x5d
704 00:43:07.277856 Write Rank0 MR1 =0x56
705 00:43:07.277935 Write Rank0 MR2 =0x1a
706 00:43:07.278018 Write Rank0 MR11 =0x0
707 00:43:07.278099 Write Rank0 MR22 =0x38
708 00:43:07.278179 Write Rank0 MR14 =0x5d
709 00:43:07.278257 Write Rank0 MR3 =0x30
710 00:43:07.278309 Write Rank0 MR13 =0x58
711 00:43:07.278360 Write Rank0 MR12 =0x5d
712 00:43:07.278410 Write Rank0 MR1 =0x56
713 00:43:07.278460 Write Rank0 MR2 =0x2d
714 00:43:07.278510 Write Rank0 MR11 =0x23
715 00:43:07.278563 Write Rank0 MR22 =0x34
716 00:43:07.278615 Write Rank0 MR14 =0x10
717 00:43:07.278666 Write Rank0 MR3 =0x30
718 00:43:07.278716 Write Rank0 MR13 =0xd8
719 00:43:07.278766 [ModeRegInit_LP4] CH0 RK1
720 00:43:07.278816 Write Rank1 MR13 =0x18
721 00:43:07.278869 Write Rank1 MR12 =0x5d
722 00:43:07.278919 Write Rank1 MR1 =0x56
723 00:43:07.278969 Write Rank1 MR2 =0x1a
724 00:43:07.279019 Write Rank1 MR11 =0x0
725 00:43:07.279068 Write Rank1 MR22 =0x38
726 00:43:07.279118 Write Rank1 MR14 =0x5d
727 00:43:07.279171 Write Rank1 MR3 =0x30
728 00:43:07.279223 Write Rank1 MR13 =0x58
729 00:43:07.279273 Write Rank1 MR12 =0x5d
730 00:43:07.279322 Write Rank1 MR1 =0x56
731 00:43:07.279372 Write Rank1 MR2 =0x2d
732 00:43:07.279421 Write Rank1 MR11 =0x23
733 00:43:07.279474 Write Rank1 MR22 =0x34
734 00:43:07.279523 Write Rank1 MR14 =0x10
735 00:43:07.279573 Write Rank1 MR3 =0x30
736 00:43:07.279622 Write Rank1 MR13 =0xd8
737 00:43:07.279673 [ModeRegInit_LP4] CH1 RK0
738 00:43:07.279723 Write Rank0 MR13 =0x18
739 00:43:07.279773 Write Rank0 MR12 =0x5d
740 00:43:07.279826 Write Rank0 MR1 =0x56
741 00:43:07.279877 Write Rank0 MR2 =0x1a
742 00:43:07.279927 Write Rank0 MR11 =0x0
743 00:43:07.279976 Write Rank0 MR22 =0x38
744 00:43:07.280026 Write Rank0 MR14 =0x5d
745 00:43:07.280075 Write Rank0 MR3 =0x30
746 00:43:07.280128 Write Rank0 MR13 =0x58
747 00:43:07.280178 Write Rank0 MR12 =0x5d
748 00:43:07.280227 Write Rank0 MR1 =0x56
749 00:43:07.280277 Write Rank0 MR2 =0x2d
750 00:43:07.280326 Write Rank0 MR11 =0x23
751 00:43:07.280375 Write Rank0 MR22 =0x34
752 00:43:07.280427 Write Rank0 MR14 =0x10
753 00:43:07.280478 Write Rank0 MR3 =0x30
754 00:43:07.280529 Write Rank0 MR13 =0xd8
755 00:43:07.280579 [ModeRegInit_LP4] CH1 RK1
756 00:43:07.280628 Write Rank1 MR13 =0x18
757 00:43:07.280678 Write Rank1 MR12 =0x5d
758 00:43:07.280731 Write Rank1 MR1 =0x56
759 00:43:07.280781 Write Rank1 MR2 =0x1a
760 00:43:07.280831 Write Rank1 MR11 =0x0
761 00:43:07.280881 Write Rank1 MR22 =0x38
762 00:43:07.280931 Write Rank1 MR14 =0x5d
763 00:43:07.280980 Write Rank1 MR3 =0x30
764 00:43:07.281030 Write Rank1 MR13 =0x58
765 00:43:07.281083 Write Rank1 MR12 =0x5d
766 00:43:07.281134 Write Rank1 MR1 =0x56
767 00:43:07.281184 Write Rank1 MR2 =0x2d
768 00:43:07.281233 Write Rank1 MR11 =0x23
769 00:43:07.281283 Write Rank1 MR22 =0x34
770 00:43:07.281333 Write Rank1 MR14 =0x10
771 00:43:07.281386 Write Rank1 MR3 =0x30
772 00:43:07.281436 Write Rank1 MR13 =0xd8
773 00:43:07.281485 match AC timing 3
774 00:43:07.281535 [DdrUpdateACTimingReg] Freq = 1600, tRFCab = 141, tRFCab_05T = 0, TXREFCNT = 159, tRFCpb = 65, tRFCpb_05T = 0
775 00:43:07.281587 DramC Write-DBI off
776 00:43:07.281640 DramC Read-DBI off
777 00:43:07.281690 Write Rank0 MR13 =0x59
778 00:43:07.281741 ==
779 00:43:07.281792 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
780 00:43:07.281843 fsp= 1, odt_onoff= 1, Byte mode= 0
781 00:43:07.281894 ==
782 00:43:07.281946 === u2Vref_new: 0x56 --> 0x2d
783 00:43:07.281998 === u2Vref_new: 0x58 --> 0x38
784 00:43:07.282048 === u2Vref_new: 0x5a --> 0x39
785 00:43:07.282099 === u2Vref_new: 0x5c --> 0x3c
786 00:43:07.282149 === u2Vref_new: 0x5e --> 0x3d
787 00:43:07.282199 === u2Vref_new: 0x60 --> 0xa0
788 00:43:07.282263 [CA 0] Center 33 (4~63) winsize 60
789 00:43:07.282316 [CA 1] Center 34 (6~63) winsize 58
790 00:43:07.282365 [CA 2] Center 27 (-1~56) winsize 58
791 00:43:07.282415 [CA 3] Center 23 (-4~51) winsize 56
792 00:43:07.282464 [CA 4] Center 24 (-3~51) winsize 55
793 00:43:07.282515 [CA 5] Center 28 (-1~58) winsize 60
794 00:43:07.282567
795 00:43:07.282617 [CATrainingPosCal] consider 1 rank data
796 00:43:07.282667 u2DelayCellTimex100 = 753/100 ps
797 00:43:07.282717 CA0 delay=33 (4~63),Diff = 10 PI (12 cell)
798 00:43:07.282767 CA1 delay=34 (6~63),Diff = 11 PI (14 cell)
799 00:43:07.282817 CA2 delay=27 (-1~56),Diff = 4 PI (5 cell)
800 00:43:07.282871 CA3 delay=23 (-4~51),Diff = 0 PI (0 cell)
801 00:43:07.282923 CA4 delay=24 (-3~51),Diff = 1 PI (1 cell)
802 00:43:07.282973 CA5 delay=28 (-1~58),Diff = 5 PI (6 cell)
803 00:43:07.283023
804 00:43:07.283073 CA PerBit enable=1, Macro0, CA PI delay=23
805 00:43:07.283123 === u2Vref_new: 0x56 --> 0x2d
806 00:43:07.283176
807 00:43:07.283227 Vref(ca) range 1: 22
808 00:43:07.283277
809 00:43:07.283326 CS Dly= 10 (41-0-32)
810 00:43:07.283376 Write Rank0 MR13 =0xd8
811 00:43:07.283426 Write Rank0 MR13 =0xd8
812 00:43:07.283480 Write Rank0 MR12 =0x56
813 00:43:07.283531 Write Rank1 MR13 =0x59
814 00:43:07.283580 ==
815 00:43:07.283837 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
816 00:43:07.283896 fsp= 1, odt_onoff= 1, Byte mode= 0
817 00:43:07.283948 ==
818 00:43:07.283998 === u2Vref_new: 0x56 --> 0x2d
819 00:43:07.284052 === u2Vref_new: 0x58 --> 0x38
820 00:43:07.284103 === u2Vref_new: 0x5a --> 0x39
821 00:43:07.284155 === u2Vref_new: 0x5c --> 0x3c
822 00:43:07.284205 === u2Vref_new: 0x5e --> 0x3d
823 00:43:07.284255 === u2Vref_new: 0x60 --> 0xa0
824 00:43:07.284305 [CA 0] Center 34 (5~63) winsize 59
825 00:43:07.284359 [CA 1] Center 34 (5~63) winsize 59
826 00:43:07.284410 [CA 2] Center 28 (0~56) winsize 57
827 00:43:07.284460 [CA 3] Center 23 (-4~51) winsize 56
828 00:43:07.284511 [CA 4] Center 24 (-3~52) winsize 56
829 00:43:07.284561 [CA 5] Center 29 (0~58) winsize 59
830 00:43:07.284611
831 00:43:07.284664 [CATrainingPosCal] consider 2 rank data
832 00:43:07.284716 u2DelayCellTimex100 = 753/100 ps
833 00:43:07.284766 CA0 delay=34 (5~63),Diff = 11 PI (14 cell)
834 00:43:07.284816 CA1 delay=34 (6~63),Diff = 11 PI (14 cell)
835 00:43:07.284867 CA2 delay=28 (0~56),Diff = 5 PI (6 cell)
836 00:43:07.284918 CA3 delay=23 (-4~51),Diff = 0 PI (0 cell)
837 00:43:07.284970 CA4 delay=24 (-3~51),Diff = 1 PI (1 cell)
838 00:43:07.285020 CA5 delay=29 (0~58),Diff = 6 PI (7 cell)
839 00:43:07.285070
840 00:43:07.285119 CA PerBit enable=1, Macro0, CA PI delay=23
841 00:43:07.285169 === u2Vref_new: 0x56 --> 0x2d
842 00:43:07.285219
843 00:43:07.285272 Vref(ca) range 1: 22
844 00:43:07.285324
845 00:43:07.285374 CS Dly= 7 (38-0-32)
846 00:43:07.285423 Write Rank1 MR13 =0xd8
847 00:43:07.285473 Write Rank1 MR13 =0xd8
848 00:43:07.285523 Write Rank1 MR12 =0x56
849 00:43:07.285576 [RankSwap] Rank num 2, (Multi 1), Rank 0
850 00:43:07.285626 Write Rank0 MR2 =0xad
851 00:43:07.285676 [Write Leveling]
852 00:43:07.285725 delay byte0 byte1 byte2 byte3
853 00:43:07.285775
854 00:43:07.285824 10 0 0
855 00:43:07.285880 11 0 0
856 00:43:07.285933 12 0 0
857 00:43:07.285984 13 0 0
858 00:43:07.286035 14 0 0
859 00:43:07.286086 15 0 0
860 00:43:07.286139 16 0 0
861 00:43:07.286190 17 0 0
862 00:43:07.286250 18 0 0
863 00:43:07.286303 19 0 0
864 00:43:07.286354 20 0 0
865 00:43:07.286404 21 0 0
866 00:43:07.286458 22 0 0
867 00:43:07.286510 23 0 0
868 00:43:07.286560 24 0 0
869 00:43:07.286611 25 0 0
870 00:43:07.286663 26 0 0
871 00:43:07.286717 27 0 0
872 00:43:07.286768 28 0 ff
873 00:43:07.286819 29 0 ff
874 00:43:07.286870 30 0 ff
875 00:43:07.286919 31 0 ff
876 00:43:07.286970 32 0 ff
877 00:43:07.287024 33 ff ff
878 00:43:07.287077 34 ff ff
879 00:43:07.287128 35 ff ff
880 00:43:07.287178 36 ff ff
881 00:43:07.287229 37 ff ff
882 00:43:07.287280 38 ff ff
883 00:43:07.287336 39 ff ff
884 00:43:07.287388 pass bytecount = 0xff (0xff: all bytes pass)
885 00:43:07.287438
886 00:43:07.287488 DQS0 dly: 33
887 00:43:07.287538 DQS1 dly: 28
888 00:43:07.287587 Write Rank0 MR2 =0x2d
889 00:43:07.287640 [RankSwap] Rank num 2, (Multi 1), Rank 0
890 00:43:07.287693 Write Rank0 MR1 =0xd6
891 00:43:07.287743 [Gating]
892 00:43:07.287792 ==
893 00:43:07.287842 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
894 00:43:07.287895 fsp= 1, odt_onoff= 1, Byte mode= 0
895 00:43:07.287946 ==
896 00:43:07.287997 3 1 0 |3534 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
897 00:43:07.288049 3 1 4 |3534 2b2b |(11 11)(11 11) |(1 1)(1 0)| 0
898 00:43:07.288101 3 1 8 |3534 3433 |(11 11)(11 11) |(0 0)(0 1)| 0
899 00:43:07.288153 3 1 12 |3534 3535 |(11 11)(11 11) |(0 0)(0 1)| 0
900 00:43:07.288207 3 1 16 |3534 3434 |(11 11)(11 11) |(0 0)(1 1)| 0
901 00:43:07.288259 3 1 20 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
902 00:43:07.288311 3 1 24 |3534 3231 |(11 11)(11 11) |(0 1)(0 1)| 0
903 00:43:07.288401 3 1 28 |3534 1515 |(11 11)(11 11) |(0 1)(0 1)| 0
904 00:43:07.288476 3 2 0 |3d3d 201 |(11 11)(11 11) |(1 1)(0 0)| 0
905 00:43:07.288531 3 2 4 |3d3d 707 |(11 11)(11 11) |(1 1)(1 1)| 0
906 00:43:07.288583 3 2 8 |3d3d 3d3c |(11 11)(11 11) |(1 1)(1 1)| 0
907 00:43:07.288635 3 2 12 |3d3d 3d3c |(11 11)(11 11) |(1 1)(0 0)| 0
908 00:43:07.288690 3 2 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(0 0)| 0
909 00:43:07.288742 3 2 20 |3d3d 3c3b |(11 11)(11 11) |(1 1)(1 1)| 0
910 00:43:07.288795 3 2 24 |3d3d 3a39 |(11 11)(11 11) |(1 1)(1 1)| 0
911 00:43:07.288846 3 2 28 |3d3d 2726 |(11 11)(11 11) |(1 1)(1 1)| 0
912 00:43:07.288898 3 3 0 |3d3d 3c3b |(11 11)(11 11) |(1 1)(1 1)| 0
913 00:43:07.288950 3 3 4 |3d3d 202 |(11 11)(11 11) |(1 1)(1 1)| 0
914 00:43:07.289004 3 3 8 |403 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
915 00:43:07.289056 [Byte 1] Lead/lag falling Transition (3, 3, 8)
916 00:43:07.289106 3 3 12 |3534 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
917 00:43:07.289157 [Byte 0] Lead/lag Transition tap number (1)
918 00:43:07.289210 3 3 16 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
919 00:43:07.289263 3 3 20 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
920 00:43:07.289317 3 3 24 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
921 00:43:07.289370 3 3 28 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
922 00:43:07.289421 3 4 0 |403 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
923 00:43:07.289476 3 4 4 |3d3d 505 |(11 11)(11 11) |(1 1)(1 1)| 0
924 00:43:07.289528 3 4 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
925 00:43:07.289579 3 4 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
926 00:43:07.289631 3 4 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
927 00:43:07.289683 3 4 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
928 00:43:07.289742 3 4 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
929 00:43:07.289833 3 4 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
930 00:43:07.289916 3 5 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
931 00:43:07.290003 3 5 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
932 00:43:07.290086 3 5 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
933 00:43:07.290169 3 5 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
934 00:43:07.290247 3 5 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
935 00:43:07.290304 3 5 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
936 00:43:07.290356 [Byte 0] Lead/lag falling Transition (3, 5, 20)
937 00:43:07.290408 3 5 24 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 1)| 0
938 00:43:07.290460 [Byte 1] Lead/lag falling Transition (3, 5, 24)
939 00:43:07.290708 3 5 28 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 0)| 0
940 00:43:07.290772 [Byte 0] Lead/lag Transition tap number (3)
941 00:43:07.290827 [Byte 1] Lead/lag Transition tap number (2)
942 00:43:07.290879 3 6 0 |404 3e3d |(11 11)(11 11) |(0 0)(0 0)| 0
943 00:43:07.290932 3 6 4 |4646 606 |(0 0)(11 11) |(0 0)(0 0)| 0
944 00:43:07.290983 [Byte 0]First pass (3, 6, 4)
945 00:43:07.291037 3 6 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
946 00:43:07.291089 [Byte 1]First pass (3, 6, 8)
947 00:43:07.291139 3 6 12 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
948 00:43:07.291190 3 6 16 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
949 00:43:07.291242 3 6 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
950 00:43:07.291297 3 6 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
951 00:43:07.291350 3 6 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
952 00:43:07.291401 3 7 0 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
953 00:43:07.291453 3 7 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
954 00:43:07.291506 3 7 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
955 00:43:07.291558 All bytes gating window > 1UI, Early break!
956 00:43:07.291608
957 00:43:07.291669 best DQS0 dly(2T, 0.5T, PI) = (3, 5, 26)
958 00:43:07.291717
959 00:43:07.291766 best DQS1 dly(2T, 0.5T, PI) = (3, 5, 28)
960 00:43:07.291814
961 00:43:07.291891
962 00:43:07.291938
963 00:43:07.291984 best DQS0 P1 dly(2T, 0.5T, PI) = (4, 1, 26)
964 00:43:07.292034
965 00:43:07.292080 best DQS1 P1 dly(2T, 0.5T, PI) = (4, 1, 28)
966 00:43:07.292126
967 00:43:07.292173
968 00:43:07.292220 Write Rank0 MR1 =0x56
969 00:43:07.292269
970 00:43:07.292317 best RODT dly(2T, 0.5T) = (2, 2)
971 00:43:07.292365
972 00:43:07.292411 best RODT dly(2T, 0.5T) = (2, 2)
973 00:43:07.292458 ==
974 00:43:07.292507 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
975 00:43:07.292555 fsp= 1, odt_onoff= 1, Byte mode= 0
976 00:43:07.292602 ==
977 00:43:07.292649 Start DQ dly to find pass range UseTestEngine =0
978 00:43:07.292696 x-axis: bit #, y-axis: DQ dly (-127~63)
979 00:43:07.292746 RX Vref Scan = 0
980 00:43:07.292792 -26, [0] xxxxxxxx xxxxxxxx [MSB]
981 00:43:07.292842 -25, [0] xxxxxxxx xxxxxxxx [MSB]
982 00:43:07.292890 -24, [0] xxxxxxxx xxxxxxxx [MSB]
983 00:43:07.292938 -23, [0] xxxxxxxx xxxxxxxx [MSB]
984 00:43:07.292988 -22, [0] xxxxxxxx xxxxxxxx [MSB]
985 00:43:07.293035 -21, [0] xxxxxxxx xxxxxxxx [MSB]
986 00:43:07.293083 -20, [0] xxxxxxxx xxxxxxxx [MSB]
987 00:43:07.293131 -19, [0] xxxxxxxx xxxxxxxx [MSB]
988 00:43:07.293179 -18, [0] xxxxxxxx xxxxxxxx [MSB]
989 00:43:07.293229 -17, [0] xxxxxxxx xxxxxxxx [MSB]
990 00:43:07.293279 -16, [0] xxxxxxxx xxxxxxxx [MSB]
991 00:43:07.293326 -15, [0] xxxxxxxx xxxxxxxx [MSB]
992 00:43:07.293373 -14, [0] xxxxxxxx xxxxxxxx [MSB]
993 00:43:07.293421 -13, [0] xxxxxxxx xxxxxxxx [MSB]
994 00:43:07.293477 -12, [0] xxxxxxxx xxxxxxxx [MSB]
995 00:43:07.293558 -11, [0] xxxxxxxx xxxxxxxx [MSB]
996 00:43:07.293635 -10, [0] xxxxxxxx xxxxxxxx [MSB]
997 00:43:07.293715 -9, [0] xxxxxxxx xxxxxxxx [MSB]
998 00:43:07.293793 -8, [0] xxxxxxxx xxxxxxxx [MSB]
999 00:43:07.293869 -7, [0] xxxxxxxx xxxxxxxx [MSB]
1000 00:43:07.293948 -6, [0] xxxxxxxx xxxxxxxx [MSB]
1001 00:43:07.294024 -5, [0] xxxxxxxx xxxxxxxx [MSB]
1002 00:43:07.294100 -4, [0] xxxxxxxx xxxxxxxx [MSB]
1003 00:43:07.294180 -3, [0] xxxoxxxx xxxxxxxx [MSB]
1004 00:43:07.294282 -2, [0] xxxoxxxx xxxxxxxx [MSB]
1005 00:43:07.294332 -1, [0] xxxoxoxx xxxxxxxx [MSB]
1006 00:43:07.294380 0, [0] xxxoxooo xxxxxoxx [MSB]
1007 00:43:07.294432 1, [0] xxxoxooo xxxxxoxx [MSB]
1008 00:43:07.294480 2, [0] xxxoxooo ooxxxoxx [MSB]
1009 00:43:07.294528 3, [0] xxxoxooo ooxooooo [MSB]
1010 00:43:07.294576 4, [0] xxxoxooo ooxooooo [MSB]
1011 00:43:07.294625 5, [0] xxxoxooo ooxooooo [MSB]
1012 00:43:07.294676 6, [0] xooooooo oooooooo [MSB]
1013 00:43:07.294724 7, [0] xooooooo oooooooo [MSB]
1014 00:43:07.294774 31, [0] oooxoooo oooooooo [MSB]
1015 00:43:07.294821 32, [0] oooxoxoo oooooooo [MSB]
1016 00:43:07.294869 33, [0] oooxoxxo oooooooo [MSB]
1017 00:43:07.294919 34, [0] oooxoxxo ooooooxo [MSB]
1018 00:43:07.294968 35, [0] oooxoxxo xooxooxo [MSB]
1019 00:43:07.295015 36, [0] oooxoxxo xooxooxo [MSB]
1020 00:43:07.295062 37, [0] oooxoxxx xooxxxxo [MSB]
1021 00:43:07.295110 38, [0] oooxoxxx xooxxxxo [MSB]
1022 00:43:07.295171 39, [0] oooxxxxx xxoxxxxx [MSB]
1023 00:43:07.295225 40, [0] oxoxxxxx xxoxxxxx [MSB]
1024 00:43:07.295275 41, [0] oxxxxxxx xxxxxxxx [MSB]
1025 00:43:07.295323 42, [0] xxxxxxxx xxxxxxxx [MSB]
1026 00:43:07.295371 iDelay=42, Bit 0, Center 24 (8 ~ 41) 34
1027 00:43:07.295418 iDelay=42, Bit 1, Center 22 (6 ~ 39) 34
1028 00:43:07.295470 iDelay=42, Bit 2, Center 23 (6 ~ 40) 35
1029 00:43:07.295517 iDelay=42, Bit 3, Center 13 (-3 ~ 30) 34
1030 00:43:07.295564 iDelay=42, Bit 4, Center 22 (6 ~ 38) 33
1031 00:43:07.295611 iDelay=42, Bit 5, Center 15 (-1 ~ 31) 33
1032 00:43:07.295658 iDelay=42, Bit 6, Center 16 (0 ~ 32) 33
1033 00:43:07.295705 iDelay=42, Bit 7, Center 18 (0 ~ 36) 37
1034 00:43:07.295752 iDelay=42, Bit 8, Center 18 (2 ~ 34) 33
1035 00:43:07.295802 iDelay=42, Bit 9, Center 20 (2 ~ 38) 37
1036 00:43:07.295851 iDelay=42, Bit 10, Center 23 (6 ~ 40) 35
1037 00:43:07.295898 iDelay=42, Bit 11, Center 18 (3 ~ 34) 32
1038 00:43:07.295945 iDelay=42, Bit 12, Center 19 (3 ~ 36) 34
1039 00:43:07.295992 iDelay=42, Bit 13, Center 18 (0 ~ 36) 37
1040 00:43:07.296038 iDelay=42, Bit 14, Center 18 (3 ~ 33) 31
1041 00:43:07.296088 iDelay=42, Bit 15, Center 20 (3 ~ 38) 36
1042 00:43:07.296135 ==
1043 00:43:07.296182 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1044 00:43:07.296229 fsp= 1, odt_onoff= 1, Byte mode= 0
1045 00:43:07.296276 ==
1046 00:43:07.296323 DQS Delay:
1047 00:43:07.296370 DQS0 = 0, DQS1 = 0
1048 00:43:07.296420 DQM Delay:
1049 00:43:07.296468 DQM0 = 19, DQM1 = 19
1050 00:43:07.296515 DQ Delay:
1051 00:43:07.296561 DQ0 =24, DQ1 =22, DQ2 =23, DQ3 =13
1052 00:43:07.296608 DQ4 =22, DQ5 =15, DQ6 =16, DQ7 =18
1053 00:43:07.296655 DQ8 =18, DQ9 =20, DQ10 =23, DQ11 =18
1054 00:43:07.296705 DQ12 =19, DQ13 =18, DQ14 =18, DQ15 =20
1055 00:43:07.296752
1056 00:43:07.296798
1057 00:43:07.296844 DramC Write-DBI off
1058 00:43:07.296890 ==
1059 00:43:07.296937 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1060 00:43:07.296987 fsp= 1, odt_onoff= 1, Byte mode= 0
1061 00:43:07.297035 ==
1062 00:43:07.297082 [TxWindowPerbitCal] calType=2, VrefScanEnable 0
1063 00:43:07.297129
1064 00:43:07.297176 Begin, DQ Scan Range 924~1180
1065 00:43:07.297222
1066 00:43:07.297271
1067 00:43:07.297318 TX Vref Scan disable
1068 00:43:07.297365 924 |3 4 28|[0] xxxxxxxx xxxxxxxx [MSB]
1069 00:43:07.297412 925 |3 4 29|[0] xxxxxxxx xxxxxxxx [MSB]
1070 00:43:07.297660 926 |3 4 30|[0] xxxxxxxx xxxxxxxx [MSB]
1071 00:43:07.297717 927 |3 4 31|[0] xxxxxxxx xxxxxxxx [MSB]
1072 00:43:07.297767 928 |3 4 32|[0] xxxxxxxx xxxxxxxx [MSB]
1073 00:43:07.297816 929 |3 4 33|[0] xxxxxxxx xxxxxxxx [MSB]
1074 00:43:07.297868 930 |3 4 34|[0] xxxxxxxx xxxxxxxx [MSB]
1075 00:43:07.297916 931 |3 4 35|[0] xxxxxxxx xxxxxxxx [MSB]
1076 00:43:07.297965 932 |3 4 36|[0] xxxxxxxx xxxxxxxx [MSB]
1077 00:43:07.298013 933 |3 4 37|[0] xxxxxxxx xxxxxxxx [MSB]
1078 00:43:07.298060 934 |3 4 38|[0] xxxxxxxx xxxxxxxx [MSB]
1079 00:43:07.298108 935 |3 4 39|[0] xxxxxxxx xxxxxxxx [MSB]
1080 00:43:07.298159 936 |3 4 40|[0] xxxxxxxx xxxxxxxx [MSB]
1081 00:43:07.298209 937 |3 4 41|[0] xxxxxxxx xxxxxxxx [MSB]
1082 00:43:07.298301 938 |3 4 42|[0] xxxxxxxx xxxxxxxx [MSB]
1083 00:43:07.298349 939 |3 4 43|[0] xxxxxxxx xxxxxxxx [MSB]
1084 00:43:07.298396 940 |3 4 44|[0] xxxxxxxx xxxxxxxx [MSB]
1085 00:43:07.298448 941 |3 4 45|[0] xxxxxxxx xxxxxxxx [MSB]
1086 00:43:07.298496 942 |3 4 46|[0] xxxxxxxx xxxxxxxx [MSB]
1087 00:43:07.298545 943 |3 4 47|[0] xxxxxxxx xxxxxxxx [MSB]
1088 00:43:07.298592 944 |3 4 48|[0] xxxxxxxx xxxxxxxx [MSB]
1089 00:43:07.298641 945 |3 4 49|[0] xxxxxxxx xxxxxxxx [MSB]
1090 00:43:07.298689 946 |3 4 50|[0] xxxxxxxx xxxxxxxx [MSB]
1091 00:43:07.298741 947 |3 4 51|[0] xxxxxxxx xxxxxxxx [MSB]
1092 00:43:07.298790 948 |3 4 52|[0] xxxxxxxx xxxxxxxx [MSB]
1093 00:43:07.298838 949 |3 4 53|[0] xxxxxxxx xxxxxxxx [MSB]
1094 00:43:07.298886 950 |3 4 54|[0] xxxxxxxx xxxxxxxx [MSB]
1095 00:43:07.298934 951 |3 4 55|[0] xxxxxxxx xxxxxxxx [MSB]
1096 00:43:07.298983 952 |3 4 56|[0] xxxxxxxx xxxxxxxx [MSB]
1097 00:43:07.299034 953 |3 4 57|[0] xxxxxxxx xxxxxxxx [MSB]
1098 00:43:07.299082 954 |3 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
1099 00:43:07.299130 955 |3 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
1100 00:43:07.299177 956 |3 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
1101 00:43:07.299226 957 |3 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
1102 00:43:07.299274 958 |3 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
1103 00:43:07.299325 959 |3 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
1104 00:43:07.299375 960 |3 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
1105 00:43:07.299423 961 |3 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
1106 00:43:07.299471 962 |3 6 2|[0] xxxxxxxx oxxxxxxx [MSB]
1107 00:43:07.299519 963 |3 6 3|[0] xxxxxxxx oxxxxxxx [MSB]
1108 00:43:07.299567 964 |3 6 4|[0] xxxxxxxx oxxoxxxx [MSB]
1109 00:43:07.299618 965 |3 6 5|[0] xxxxxxxx ooxoooox [MSB]
1110 00:43:07.299666 966 |3 6 6|[0] xxxxxxxx ooxoooox [MSB]
1111 00:43:07.299713 967 |3 6 7|[0] xxxxxxxx ooxooooo [MSB]
1112 00:43:07.299762 968 |3 6 8|[0] xxxxxxxx ooxooooo [MSB]
1113 00:43:07.299809 969 |3 6 9|[0] xxxxxxxx oooooooo [MSB]
1114 00:43:07.299856 970 |3 6 10|[0] xxxxxxxx oooooooo [MSB]
1115 00:43:07.299907 971 |3 6 11|[0] xxxoxoxx oooooooo [MSB]
1116 00:43:07.299955 972 |3 6 12|[0] xxxoxooo oooooooo [MSB]
1117 00:43:07.300004 973 |3 6 13|[0] xxxoxooo oooooooo [MSB]
1118 00:43:07.300052 974 |3 6 14|[0] xxxooooo oooooooo [MSB]
1119 00:43:07.300100 975 |3 6 15|[0] xxoooooo oooooooo [MSB]
1120 00:43:07.300148 989 |3 6 29|[0] oooooooo xxxxxxxx [MSB]
1121 00:43:07.300196 990 |3 6 30|[0] oooooooo xxxxxxxx [MSB]
1122 00:43:07.300247 991 |3 6 31|[0] oooooooo xxxxxxxx [MSB]
1123 00:43:07.300294 992 |3 6 32|[0] oooxoxoo xxxxxxxx [MSB]
1124 00:43:07.300342 993 |3 6 33|[0] oooxoxoo xxxxxxxx [MSB]
1125 00:43:07.300390 994 |3 6 34|[0] oooxoxxo xxxxxxxx [MSB]
1126 00:43:07.300438 995 |3 6 35|[0] xxxxxxxx xxxxxxxx [MSB]
1127 00:43:07.300485 Byte0, DQ PI dly=983, DQM PI dly= 983
1128 00:43:07.300535 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 23)
1129 00:43:07.300585
1130 00:43:07.300632 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 23)
1131 00:43:07.300680
1132 00:43:07.300727 Byte1, DQ PI dly=976, DQM PI dly= 976
1133 00:43:07.300774 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 16)
1134 00:43:07.300824
1135 00:43:07.300871 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 16)
1136 00:43:07.300918
1137 00:43:07.300965 ==
1138 00:43:07.301012 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1139 00:43:07.301059 fsp= 1, odt_onoff= 1, Byte mode= 0
1140 00:43:07.301109 ==
1141 00:43:07.301157 [TxWindowPerbitCal] calType=0, VrefScanEnable 1
1142 00:43:07.301205
1143 00:43:07.301253 Begin, DQ Scan Range 952~1016
1144 00:43:07.301299 Write Rank0 MR14 =0x0
1145 00:43:07.301345
1146 00:43:07.301394 CH=0, VrefRange= 0, VrefLevel = 0
1147 00:43:07.301442 TX Bit0 (977~994) 18 985, Bit8 (966~983) 18 974,
1148 00:43:07.301490 TX Bit1 (977~992) 16 984, Bit9 (967~985) 19 976,
1149 00:43:07.301537 TX Bit2 (977~993) 17 985, Bit10 (970~990) 21 980,
1150 00:43:07.301601 TX Bit3 (971~989) 19 980, Bit11 (967~984) 18 975,
1151 00:43:07.301651 TX Bit4 (976~994) 19 985, Bit12 (967~986) 20 976,
1152 00:43:07.301701 TX Bit5 (974~990) 17 982, Bit13 (967~984) 18 975,
1153 00:43:07.301750 TX Bit6 (975~990) 16 982, Bit14 (968~984) 17 976,
1154 00:43:07.301797 TX Bit7 (976~992) 17 984, Bit15 (969~988) 20 978,
1155 00:43:07.301845
1156 00:43:07.301892 Write Rank0 MR14 =0x2
1157 00:43:07.301939
1158 00:43:07.301989 CH=0, VrefRange= 0, VrefLevel = 2
1159 00:43:07.302036 TX Bit0 (977~995) 19 986, Bit8 (965~983) 19 974,
1160 00:43:07.302084 TX Bit1 (977~993) 17 985, Bit9 (967~986) 20 976,
1161 00:43:07.302131 TX Bit2 (976~994) 19 985, Bit10 (970~990) 21 980,
1162 00:43:07.302178 TX Bit3 (970~989) 20 979, Bit11 (966~985) 20 975,
1163 00:43:07.302245 TX Bit4 (976~995) 20 985, Bit12 (967~987) 21 977,
1164 00:43:07.302310 TX Bit5 (974~990) 17 982, Bit13 (967~984) 18 975,
1165 00:43:07.302361 TX Bit6 (975~990) 16 982, Bit14 (968~985) 18 976,
1166 00:43:07.302408 TX Bit7 (975~992) 18 983, Bit15 (969~988) 20 978,
1167 00:43:07.302455
1168 00:43:07.302502 Write Rank0 MR14 =0x4
1169 00:43:07.302549
1170 00:43:07.302599 CH=0, VrefRange= 0, VrefLevel = 4
1171 00:43:07.302648 TX Bit0 (977~996) 20 986, Bit8 (965~984) 20 974,
1172 00:43:07.302695 TX Bit1 (977~993) 17 985, Bit9 (967~986) 20 976,
1173 00:43:07.302743 TX Bit2 (976~994) 19 985, Bit10 (970~990) 21 980,
1174 00:43:07.302790 TX Bit3 (970~990) 21 980, Bit11 (966~986) 21 976,
1175 00:43:07.302838 TX Bit4 (976~995) 20 985, Bit12 (967~987) 21 977,
1176 00:43:07.303078 TX Bit5 (974~990) 17 982, Bit13 (967~985) 19 976,
1177 00:43:07.303132 TX Bit6 (974~990) 17 982, Bit14 (967~985) 19 976,
1178 00:43:07.303182 TX Bit7 (975~992) 18 983, Bit15 (968~989) 22 978,
1179 00:43:07.303230
1180 00:43:07.303278 Write Rank0 MR14 =0x6
1181 00:43:07.303325
1182 00:43:07.303372 CH=0, VrefRange= 0, VrefLevel = 6
1183 00:43:07.303419 TX Bit0 (977~996) 20 986, Bit8 (964~985) 22 974,
1184 00:43:07.303469 TX Bit1 (977~994) 18 985, Bit9 (966~987) 22 976,
1185 00:43:07.303518 TX Bit2 (976~994) 19 985, Bit10 (969~990) 22 979,
1186 00:43:07.303572 TX Bit3 (969~990) 22 979, Bit11 (965~986) 22 975,
1187 00:43:07.303649 TX Bit4 (976~996) 21 986, Bit12 (967~988) 22 977,
1188 00:43:07.303725 TX Bit5 (973~990) 18 981, Bit13 (967~985) 19 976,
1189 00:43:07.303804 TX Bit6 (974~991) 18 982, Bit14 (967~986) 20 976,
1190 00:43:07.303883 TX Bit7 (975~993) 19 984, Bit15 (968~989) 22 978,
1191 00:43:07.303959
1192 00:43:07.304009 Write Rank0 MR14 =0x8
1193 00:43:07.304060
1194 00:43:07.304109 CH=0, VrefRange= 0, VrefLevel = 8
1195 00:43:07.304156 TX Bit0 (976~997) 22 986, Bit8 (964~985) 22 974,
1196 00:43:07.304204 TX Bit1 (976~994) 19 985, Bit9 (967~988) 22 977,
1197 00:43:07.304252 TX Bit2 (976~996) 21 986, Bit10 (969~990) 22 979,
1198 00:43:07.304299 TX Bit3 (969~990) 22 979, Bit11 (965~987) 23 976,
1199 00:43:07.304350 TX Bit4 (976~997) 22 986, Bit12 (967~988) 22 977,
1200 00:43:07.304397 TX Bit5 (973~991) 19 982, Bit13 (966~986) 21 976,
1201 00:43:07.304444 TX Bit6 (974~991) 18 982, Bit14 (966~987) 22 976,
1202 00:43:07.304491 TX Bit7 (974~994) 21 984, Bit15 (968~989) 22 978,
1203 00:43:07.304538
1204 00:43:07.304585 Write Rank0 MR14 =0xa
1205 00:43:07.304635
1206 00:43:07.304683 CH=0, VrefRange= 0, VrefLevel = 10
1207 00:43:07.304731 TX Bit0 (976~997) 22 986, Bit8 (963~985) 23 974,
1208 00:43:07.304779 TX Bit1 (976~994) 19 985, Bit9 (966~988) 23 977,
1209 00:43:07.304827 TX Bit2 (976~996) 21 986, Bit10 (969~991) 23 980,
1210 00:43:07.304874 TX Bit3 (969~990) 22 979, Bit11 (965~988) 24 976,
1211 00:43:07.304928 TX Bit4 (975~997) 23 986, Bit12 (966~989) 24 977,
1212 00:43:07.304976 TX Bit5 (972~991) 20 981, Bit13 (966~987) 22 976,
1213 00:43:07.305024 TX Bit6 (973~991) 19 982, Bit14 (966~988) 23 977,
1214 00:43:07.305071 TX Bit7 (974~994) 21 984, Bit15 (968~990) 23 979,
1215 00:43:07.305118
1216 00:43:07.305165 Write Rank0 MR14 =0xc
1217 00:43:07.305215
1218 00:43:07.305263 CH=0, VrefRange= 0, VrefLevel = 12
1219 00:43:07.305310 TX Bit0 (976~998) 23 987, Bit8 (963~986) 24 974,
1220 00:43:07.305358 TX Bit1 (976~996) 21 986, Bit9 (965~988) 24 976,
1221 00:43:07.305405 TX Bit2 (976~997) 22 986, Bit10 (969~991) 23 980,
1222 00:43:07.305454 TX Bit3 (969~990) 22 979, Bit11 (964~988) 25 976,
1223 00:43:07.305504 TX Bit4 (975~997) 23 986, Bit12 (966~988) 23 977,
1224 00:43:07.305552 TX Bit5 (971~991) 21 981, Bit13 (966~988) 23 977,
1225 00:43:07.305628 TX Bit6 (972~992) 21 982, Bit14 (966~988) 23 977,
1226 00:43:07.305704 TX Bit7 (973~994) 22 983, Bit15 (968~990) 23 979,
1227 00:43:07.305755
1228 00:43:07.305806 Write Rank0 MR14 =0xe
1229 00:43:07.305855
1230 00:43:07.305904 CH=0, VrefRange= 0, VrefLevel = 14
1231 00:43:07.305952 TX Bit0 (976~998) 23 987, Bit8 (963~987) 25 975,
1232 00:43:07.305999 TX Bit1 (976~996) 21 986, Bit9 (965~989) 25 977,
1233 00:43:07.306046 TX Bit2 (975~997) 23 986, Bit10 (969~991) 23 980,
1234 00:43:07.306096 TX Bit3 (968~991) 24 979, Bit11 (964~988) 25 976,
1235 00:43:07.306143 TX Bit4 (975~998) 24 986, Bit12 (966~989) 24 977,
1236 00:43:07.306190 TX Bit5 (971~991) 21 981, Bit13 (966~988) 23 977,
1237 00:43:07.306277 TX Bit6 (972~992) 21 982, Bit14 (965~989) 25 977,
1238 00:43:07.306326 TX Bit7 (973~995) 23 984, Bit15 (968~990) 23 979,
1239 00:43:07.306377
1240 00:43:07.306425 Write Rank0 MR14 =0x10
1241 00:43:07.306473
1242 00:43:07.306518 CH=0, VrefRange= 0, VrefLevel = 16
1243 00:43:07.306565 TX Bit0 (976~998) 23 987, Bit8 (962~988) 27 975,
1244 00:43:07.306612 TX Bit1 (976~997) 22 986, Bit9 (965~989) 25 977,
1245 00:43:07.306662 TX Bit2 (975~998) 24 986, Bit10 (969~991) 23 980,
1246 00:43:07.306710 TX Bit3 (968~991) 24 979, Bit11 (963~989) 27 976,
1247 00:43:07.306756 TX Bit4 (974~998) 25 986, Bit12 (965~989) 25 977,
1248 00:43:07.306803 TX Bit5 (971~992) 22 981, Bit13 (965~988) 24 976,
1249 00:43:07.306850 TX Bit6 (972~993) 22 982, Bit14 (965~989) 25 977,
1250 00:43:07.306897 TX Bit7 (973~995) 23 984, Bit15 (967~991) 25 979,
1251 00:43:07.306946
1252 00:43:07.306993 Write Rank0 MR14 =0x12
1253 00:43:07.307041
1254 00:43:07.307089 CH=0, VrefRange= 0, VrefLevel = 18
1255 00:43:07.307137 TX Bit0 (976~999) 24 987, Bit8 (962~988) 27 975,
1256 00:43:07.307185 TX Bit1 (976~997) 22 986, Bit9 (965~989) 25 977,
1257 00:43:07.307235 TX Bit2 (975~998) 24 986, Bit10 (969~992) 24 980,
1258 00:43:07.307283 TX Bit3 (968~991) 24 979, Bit11 (963~989) 27 976,
1259 00:43:07.307330 TX Bit4 (974~998) 25 986, Bit12 (965~989) 25 977,
1260 00:43:07.307377 TX Bit5 (971~992) 22 981, Bit13 (965~989) 25 977,
1261 00:43:07.307424 TX Bit6 (971~993) 23 982, Bit14 (965~989) 25 977,
1262 00:43:07.307470 TX Bit7 (972~996) 25 984, Bit15 (967~991) 25 979,
1263 00:43:07.307518
1264 00:43:07.307567 Write Rank0 MR14 =0x14
1265 00:43:07.307615
1266 00:43:07.307662 CH=0, VrefRange= 0, VrefLevel = 20
1267 00:43:07.307710 TX Bit0 (976~999) 24 987, Bit8 (963~989) 27 976,
1268 00:43:07.307757 TX Bit1 (976~997) 22 986, Bit9 (964~989) 26 976,
1269 00:43:07.307807 TX Bit2 (975~998) 24 986, Bit10 (968~992) 25 980,
1270 00:43:07.307854 TX Bit3 (968~992) 25 980, Bit11 (963~989) 27 976,
1271 00:43:07.307902 TX Bit4 (974~998) 25 986, Bit12 (965~989) 25 977,
1272 00:43:07.307950 TX Bit5 (970~992) 23 981, Bit13 (964~989) 26 976,
1273 00:43:07.307997 TX Bit6 (971~994) 24 982, Bit14 (964~989) 26 976,
1274 00:43:07.308044 TX Bit7 (971~997) 27 984, Bit15 (967~991) 25 979,
1275 00:43:07.308095
1276 00:43:07.308143 Write Rank0 MR14 =0x16
1277 00:43:07.308190
1278 00:43:07.308424 CH=0, VrefRange= 0, VrefLevel = 22
1279 00:43:07.308477 TX Bit0 (975~999) 25 987, Bit8 (962~989) 28 975,
1280 00:43:07.308526 TX Bit1 (975~997) 23 986, Bit9 (964~989) 26 976,
1281 00:43:07.308573 TX Bit2 (975~998) 24 986, Bit10 (969~991) 23 980,
1282 00:43:07.308625 TX Bit3 (968~992) 25 980, Bit11 (963~989) 27 976,
1283 00:43:07.308674 TX Bit4 (974~999) 26 986, Bit12 (965~989) 25 977,
1284 00:43:07.308751 TX Bit5 (970~993) 24 981, Bit13 (964~989) 26 976,
1285 00:43:07.308827 TX Bit6 (971~995) 25 983, Bit14 (964~989) 26 976,
1286 00:43:07.308874 TX Bit7 (971~997) 27 984, Bit15 (967~991) 25 979,
1287 00:43:07.308924
1288 00:43:07.308970 Write Rank0 MR14 =0x18
1289 00:43:07.309017
1290 00:43:07.309064 CH=0, VrefRange= 0, VrefLevel = 24
1291 00:43:07.309111 TX Bit0 (975~999) 25 987, Bit8 (963~989) 27 976,
1292 00:43:07.309159 TX Bit1 (975~998) 24 986, Bit9 (965~989) 25 977,
1293 00:43:07.309209 TX Bit2 (975~998) 24 986, Bit10 (968~991) 24 979,
1294 00:43:07.309258 TX Bit3 (968~992) 25 980, Bit11 (963~989) 27 976,
1295 00:43:07.309305 TX Bit4 (975~998) 24 986, Bit12 (965~989) 25 977,
1296 00:43:07.309353 TX Bit5 (970~993) 24 981, Bit13 (963~988) 26 975,
1297 00:43:07.309400 TX Bit6 (970~995) 26 982, Bit14 (964~989) 26 976,
1298 00:43:07.309446 TX Bit7 (971~996) 26 983, Bit15 (966~990) 25 978,
1299 00:43:07.309496
1300 00:43:07.309542 Write Rank0 MR14 =0x1a
1301 00:43:07.309589
1302 00:43:07.309635 CH=0, VrefRange= 0, VrefLevel = 26
1303 00:43:07.309682 TX Bit0 (975~999) 25 987, Bit8 (963~989) 27 976,
1304 00:43:07.309729 TX Bit1 (975~998) 24 986, Bit9 (965~989) 25 977,
1305 00:43:07.309780 TX Bit2 (975~998) 24 986, Bit10 (968~991) 24 979,
1306 00:43:07.309829 TX Bit3 (968~992) 25 980, Bit11 (963~989) 27 976,
1307 00:43:07.309876 TX Bit4 (975~998) 24 986, Bit12 (965~989) 25 977,
1308 00:43:07.309924 TX Bit5 (970~993) 24 981, Bit13 (963~988) 26 975,
1309 00:43:07.309971 TX Bit6 (970~995) 26 982, Bit14 (964~989) 26 976,
1310 00:43:07.310018 TX Bit7 (971~996) 26 983, Bit15 (966~990) 25 978,
1311 00:43:07.310067
1312 00:43:07.310114 Write Rank0 MR14 =0x1c
1313 00:43:07.310161
1314 00:43:07.310207 CH=0, VrefRange= 0, VrefLevel = 28
1315 00:43:07.310296 TX Bit0 (975~999) 25 987, Bit8 (963~989) 27 976,
1316 00:43:07.310348 TX Bit1 (975~998) 24 986, Bit9 (965~989) 25 977,
1317 00:43:07.310397 TX Bit2 (975~998) 24 986, Bit10 (968~991) 24 979,
1318 00:43:07.310444 TX Bit3 (968~992) 25 980, Bit11 (963~989) 27 976,
1319 00:43:07.310491 TX Bit4 (975~998) 24 986, Bit12 (965~989) 25 977,
1320 00:43:07.310538 TX Bit5 (970~993) 24 981, Bit13 (963~988) 26 975,
1321 00:43:07.310586 TX Bit6 (970~995) 26 982, Bit14 (964~989) 26 976,
1322 00:43:07.310637 TX Bit7 (971~996) 26 983, Bit15 (966~990) 25 978,
1323 00:43:07.310684
1324 00:43:07.310730 Write Rank0 MR14 =0x1e
1325 00:43:07.310776
1326 00:43:07.310823 CH=0, VrefRange= 0, VrefLevel = 30
1327 00:43:07.310873 TX Bit0 (975~999) 25 987, Bit8 (963~989) 27 976,
1328 00:43:07.310922 TX Bit1 (975~998) 24 986, Bit9 (965~989) 25 977,
1329 00:43:07.310970 TX Bit2 (975~998) 24 986, Bit10 (968~991) 24 979,
1330 00:43:07.311017 TX Bit3 (968~992) 25 980, Bit11 (963~989) 27 976,
1331 00:43:07.311065 TX Bit4 (975~998) 24 986, Bit12 (965~989) 25 977,
1332 00:43:07.311113 TX Bit5 (970~993) 24 981, Bit13 (963~988) 26 975,
1333 00:43:07.311163 TX Bit6 (970~995) 26 982, Bit14 (964~989) 26 976,
1334 00:43:07.311210 TX Bit7 (971~996) 26 983, Bit15 (966~990) 25 978,
1335 00:43:07.311258
1336 00:43:07.311304
1337 00:43:07.311350 TX Vref found, early break! 375< 382
1338 00:43:07.311397 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =753/100 ps
1339 00:43:07.311448 u1DelayCellOfst[0]=9 cells (7 PI)
1340 00:43:07.311497 u1DelayCellOfst[1]=7 cells (6 PI)
1341 00:43:07.311545 u1DelayCellOfst[2]=7 cells (6 PI)
1342 00:43:07.311591 u1DelayCellOfst[3]=0 cells (0 PI)
1343 00:43:07.311638 u1DelayCellOfst[4]=7 cells (6 PI)
1344 00:43:07.311688 u1DelayCellOfst[5]=1 cells (1 PI)
1345 00:43:07.311735 u1DelayCellOfst[6]=2 cells (2 PI)
1346 00:43:07.311782 u1DelayCellOfst[7]=3 cells (3 PI)
1347 00:43:07.311829 Byte0, DQ PI dly=980, DQM PI dly= 983
1348 00:43:07.311878 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 20)
1349 00:43:07.311925
1350 00:43:07.311973 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 20)
1351 00:43:07.312021
1352 00:43:07.312069 u1DelayCellOfst[8]=1 cells (1 PI)
1353 00:43:07.312116 u1DelayCellOfst[9]=2 cells (2 PI)
1354 00:43:07.312163 u1DelayCellOfst[10]=5 cells (4 PI)
1355 00:43:07.312210 u1DelayCellOfst[11]=1 cells (1 PI)
1356 00:43:07.312256 u1DelayCellOfst[12]=2 cells (2 PI)
1357 00:43:07.312305 u1DelayCellOfst[13]=0 cells (0 PI)
1358 00:43:07.312353 u1DelayCellOfst[14]=1 cells (1 PI)
1359 00:43:07.312399 u1DelayCellOfst[15]=3 cells (3 PI)
1360 00:43:07.312446 Byte1, DQ PI dly=975, DQM PI dly= 977
1361 00:43:07.312493 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 15)
1362 00:43:07.312540
1363 00:43:07.312589 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 15)
1364 00:43:07.312637
1365 00:43:07.312682 Write Rank0 MR14 =0x18
1366 00:43:07.312728
1367 00:43:07.312774 Final TX Range 0 Vref 24
1368 00:43:07.312820
1369 00:43:07.312869 [TX_K_DQM_WITH_WDBI] Step1: K DQM with DBI_ON, and check DQM window spec.
1370 00:43:07.312916
1371 00:43:07.312962 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
1372 00:43:07.313009 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
1373 00:43:07.313057 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
1374 00:43:07.313103 Write Rank0 MR3 =0xb0
1375 00:43:07.313153 DramC Write-DBI on
1376 00:43:07.313201 ==
1377 00:43:07.313248 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1378 00:43:07.313295 fsp= 1, odt_onoff= 1, Byte mode= 0
1379 00:43:07.313342 ==
1380 00:43:07.313388 [TxWindowPerbitCal] calType=1, VrefScanEnable 0
1381 00:43:07.313438
1382 00:43:07.313484 Begin, DQ Scan Range 697~761
1383 00:43:07.313530
1384 00:43:07.313575
1385 00:43:07.313620 TX Vref Scan disable
1386 00:43:07.313666 697 |2 4 57|[0] xxxxxxxx xxxxxxxx [MSB]
1387 00:43:07.313717 698 |2 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
1388 00:43:07.313765 699 |2 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
1389 00:43:07.314023 700 |2 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
1390 00:43:07.314077 701 |2 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
1391 00:43:07.314126 702 |2 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
1392 00:43:07.314174 703 |2 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
1393 00:43:07.314242 704 |2 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
1394 00:43:07.314308 705 |2 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
1395 00:43:07.314358 706 |2 6 2|[0] xxxxxxxx oooooooo [MSB]
1396 00:43:07.314405 707 |2 6 3|[0] xxxxxxxx oooooooo [MSB]
1397 00:43:07.314452 708 |2 6 4|[0] xxxxxxxx oooooooo [MSB]
1398 00:43:07.314500 709 |2 6 5|[0] xxxxxxxx oooooooo [MSB]
1399 00:43:07.314547 710 |2 6 6|[0] xxxxxxxx oooooooo [MSB]
1400 00:43:07.314598 711 |2 6 7|[0] xxxxxxxx oooooooo [MSB]
1401 00:43:07.314646 712 |2 6 8|[0] xxxxxxxx oooooooo [MSB]
1402 00:43:07.314693 713 |2 6 9|[0] xxxxxxxx oooooooo [MSB]
1403 00:43:07.314740 734 |2 6 30|[0] oooooooo xxxxxxxx [MSB]
1404 00:43:07.314789 735 |2 6 31|[0] oooooooo xxxxxxxx [MSB]
1405 00:43:07.314836 736 |2 6 32|[0] oooooooo xxxxxxxx [MSB]
1406 00:43:07.314886 737 |2 6 33|[0] oooooooo xxxxxxxx [MSB]
1407 00:43:07.314935 738 |2 6 34|[0] oooooooo xxxxxxxx [MSB]
1408 00:43:07.314982 739 |2 6 35|[0] oooooooo xxxxxxxx [MSB]
1409 00:43:07.315029 740 |2 6 36|[0] oooooooo xxxxxxxx [MSB]
1410 00:43:07.315076 741 |2 6 37|[0] oooooooo xxxxxxxx [MSB]
1411 00:43:07.315122 742 |2 6 38|[0] xxxxxxxx xxxxxxxx [MSB]
1412 00:43:07.315173 Byte0, DQ PI dly=727, DQM PI dly= 727
1413 00:43:07.315220 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 23)
1414 00:43:07.315267
1415 00:43:07.315313 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 23)
1416 00:43:07.315359
1417 00:43:07.315405 Byte1, DQ PI dly=719, DQM PI dly= 719
1418 00:43:07.315453 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 15)
1419 00:43:07.315501
1420 00:43:07.315547 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 15)
1421 00:43:07.315593
1422 00:43:07.315638 Before -1MCK, ucdq_final_ui_large_dqs0 = 2, ucdq_final_ui_large_dqs1 = 2
1423 00:43:07.315686 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
1424 00:43:07.315736 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
1425 00:43:07.315783 Write Rank0 MR3 =0x30
1426 00:43:07.315830 DramC Write-DBI off
1427 00:43:07.315876
1428 00:43:07.315922 [DATLAT]
1429 00:43:07.315969 Freq=1600, CH0 RK0, use_rxtx_scan=0
1430 00:43:07.316018
1431 00:43:07.316067 DATLAT Default: 0xf
1432 00:43:07.316113 7, 0xFFFF, sum=0
1433 00:43:07.316160 8, 0xFFFF, sum=0
1434 00:43:07.316207 9, 0xFFFF, sum=0
1435 00:43:07.316253 10, 0xFFFF, sum=0
1436 00:43:07.316303 11, 0xFFFF, sum=0
1437 00:43:07.316351 12, 0xFFFF, sum=0
1438 00:43:07.316398 13, 0xFFFF, sum=0
1439 00:43:07.316446 14, 0x0, sum=1
1440 00:43:07.316493 15, 0x0, sum=2
1441 00:43:07.316540 16, 0x0, sum=3
1442 00:43:07.316589 17, 0x0, sum=4
1443 00:43:07.316637 pattern=2 first_step=14 total pass=5 best_step=16
1444 00:43:07.316685 ==
1445 00:43:07.316732 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1446 00:43:07.316779 fsp= 1, odt_onoff= 1, Byte mode= 0
1447 00:43:07.316825 ==
1448 00:43:07.316871 Start DQ dly to find pass range UseTestEngine =1
1449 00:43:07.316921 x-axis: bit #, y-axis: DQ dly (-127~63)
1450 00:43:07.316968 RX Vref Scan = 1
1451 00:43:07.317014
1452 00:43:07.317060 RX Vref found, early break!
1453 00:43:07.317106
1454 00:43:07.317151 Final RX Vref 12, apply to both rank0 and 1
1455 00:43:07.317200 ==
1456 00:43:07.317248 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1457 00:43:07.317295 fsp= 1, odt_onoff= 1, Byte mode= 0
1458 00:43:07.317342 ==
1459 00:43:07.317388 DQS Delay:
1460 00:43:07.317434 DQS0 = 0, DQS1 = 0
1461 00:43:07.317483 DQM Delay:
1462 00:43:07.317529 DQM0 = 19, DQM1 = 18
1463 00:43:07.317575 DQ Delay:
1464 00:43:07.317620 DQ0 =24, DQ1 =23, DQ2 =23, DQ3 =13
1465 00:43:07.317666 DQ4 =22, DQ5 =14, DQ6 =17, DQ7 =18
1466 00:43:07.317712 DQ8 =17, DQ9 =19, DQ10 =22, DQ11 =17
1467 00:43:07.317762 DQ12 =19, DQ13 =16, DQ14 =17, DQ15 =20
1468 00:43:07.317809
1469 00:43:07.317855
1470 00:43:07.317900
1471 00:43:07.317946 [DramC_TX_OE_Calibration] TA2
1472 00:43:07.317992 Original DQ_B0 (3 6) =30, OEN = 27
1473 00:43:07.318042 Original DQ_B1 (3 6) =30, OEN = 27
1474 00:43:07.318088 23, 0x0, End_B0=23 End_B1=23
1475 00:43:07.318134 24, 0x0, End_B0=24 End_B1=24
1476 00:43:07.318182 25, 0x0, End_B0=25 End_B1=25
1477 00:43:07.318237 26, 0x0, End_B0=26 End_B1=26
1478 00:43:07.318288 27, 0x0, End_B0=27 End_B1=27
1479 00:43:07.318337 28, 0x0, End_B0=28 End_B1=28
1480 00:43:07.318384 29, 0x0, End_B0=29 End_B1=29
1481 00:43:07.318430 30, 0x0, End_B0=30 End_B1=30
1482 00:43:07.318477 31, 0xFFFF, End_B0=30 End_B1=30
1483 00:43:07.318525 Byte0 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
1484 00:43:07.318576 Byte1 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
1485 00:43:07.318622
1486 00:43:07.318669
1487 00:43:07.318715 Write Rank0 MR23 =0x3f
1488 00:43:07.318761 [DQSOSC]
1489 00:43:07.318808 [DQSOSCAuto] RK0, (LSB)MR18= 0x9f, (MSB)MR19= 0x3, tDQSOscB0 = 339 ps tDQSOscB1 = 0 ps
1490 00:43:07.318858 CH0_RK0: MR19=0x3, MR18=0x9F, DQSOSC=339, MR23=63, INC=21, DEC=32
1491 00:43:07.318906 Write Rank0 MR23 =0x3f
1492 00:43:07.318952 [DQSOSC]
1493 00:43:07.318999 [DQSOSCAuto] RK0, (LSB)MR18= 0x9d, (MSB)MR19= 0x3, tDQSOscB0 = 340 ps tDQSOscB1 = 0 ps
1494 00:43:07.319046 CH0 RK0: MR19=3, MR18=9D
1495 00:43:07.319092 [RankSwap] Rank num 2, (Multi 1), Rank 1
1496 00:43:07.319142 Write Rank0 MR2 =0xad
1497 00:43:07.319188 [Write Leveling]
1498 00:43:07.319234 delay byte0 byte1 byte2 byte3
1499 00:43:07.319280
1500 00:43:07.319325 10 0 0
1501 00:43:07.319372 11 0 0
1502 00:43:07.319422 12 0 0
1503 00:43:07.319471 13 0 0
1504 00:43:07.319518 14 0 0
1505 00:43:07.319564 15 0 0
1506 00:43:07.319613 16 0 0
1507 00:43:07.319661 17 0 0
1508 00:43:07.319711 18 0 0
1509 00:43:07.319757 19 0 0
1510 00:43:07.319804 20 0 0
1511 00:43:07.319851 21 0 0
1512 00:43:07.319899 22 0 0
1513 00:43:07.319945 23 0 0
1514 00:43:07.319995 24 0 0
1515 00:43:07.320044 25 0 0
1516 00:43:07.320091 26 0 0
1517 00:43:07.320137 27 0 0
1518 00:43:07.320183 28 0 0
1519 00:43:07.320232 29 0 0
1520 00:43:07.320279 30 0 ff
1521 00:43:07.320326 31 0 ff
1522 00:43:07.320373 32 0 ff
1523 00:43:07.320420 33 0 ff
1524 00:43:07.320467 34 0 ff
1525 00:43:07.320515 35 ff ff
1526 00:43:07.320566 36 ff ff
1527 00:43:07.320615 37 ff ff
1528 00:43:07.320662 38 ff ff
1529 00:43:07.320709 39 ff ff
1530 00:43:07.320756 40 ff ff
1531 00:43:07.320805 41 ff ff
1532 00:43:07.320852 pass bytecount = 0xff (0xff: all bytes pass)
1533 00:43:07.320899
1534 00:43:07.320945 DQS0 dly: 35
1535 00:43:07.320991 DQS1 dly: 30
1536 00:43:07.321037 Write Rank0 MR2 =0x2d
1537 00:43:07.321086 [RankSwap] Rank num 2, (Multi 1), Rank 0
1538 00:43:07.321134 Write Rank1 MR1 =0xd6
1539 00:43:07.321181 [Gating]
1540 00:43:07.321226 ==
1541 00:43:07.321473 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1542 00:43:07.321527 fsp= 1, odt_onoff= 1, Byte mode= 0
1543 00:43:07.321579 ==
1544 00:43:07.321628 3 1 0 |3534 3534 |(11 11)(11 11) |(0 0)(1 1)| 0
1545 00:43:07.321677 3 1 4 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
1546 00:43:07.321725 3 1 8 |3534 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
1547 00:43:07.321772 3 1 12 |3534 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
1548 00:43:07.321822 3 1 16 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
1549 00:43:07.321871 3 1 20 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
1550 00:43:07.321918 3 1 24 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
1551 00:43:07.321966 3 1 28 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
1552 00:43:07.322014 3 2 0 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
1553 00:43:07.322064 3 2 4 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
1554 00:43:07.322111 3 2 8 |505 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
1555 00:43:07.322161 3 2 12 |3d3d 201 |(11 11)(11 11) |(1 1)(1 1)| 0
1556 00:43:07.322208 3 2 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1557 00:43:07.322266 3 2 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1558 00:43:07.322317 3 2 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1559 00:43:07.322365 3 2 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1560 00:43:07.322413 3 3 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1561 00:43:07.322460 3 3 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1562 00:43:07.322508 3 3 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1563 00:43:07.322557 3 3 12 |3d3d 3d3d |(11 11)(0 0) |(1 1)(1 1)| 0
1564 00:43:07.322607 3 3 16 |908 0 |(11 11)(11 11) |(1 1)(1 1)| 0
1565 00:43:07.322656 3 3 20 |3534 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
1566 00:43:07.322704 [Byte 0] Lead/lag Transition tap number (1)
1567 00:43:07.322750 [Byte 1] Lead/lag falling Transition (3, 3, 20)
1568 00:43:07.322797 3 3 24 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
1569 00:43:07.322846 3 3 28 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
1570 00:43:07.322898 3 4 0 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
1571 00:43:07.322946 3 4 4 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
1572 00:43:07.322993 3 4 8 |201 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
1573 00:43:07.323040 3 4 12 |3d3d 201 |(11 11)(11 11) |(1 1)(1 1)| 0
1574 00:43:07.323087 3 4 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1575 00:43:07.323134 3 4 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1576 00:43:07.323184 3 4 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1577 00:43:07.323233 3 4 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1578 00:43:07.323303 3 5 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1579 00:43:07.323386 3 5 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1580 00:43:07.323438 3 5 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1581 00:43:07.323491 3 5 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1582 00:43:07.323538 3 5 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1583 00:43:07.323586 3 5 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1584 00:43:07.323633 3 5 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1585 00:43:07.323681 3 5 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1586 00:43:07.323731 3 6 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1587 00:43:07.323781 [Byte 0] Lead/lag falling Transition (3, 6, 0)
1588 00:43:07.323828 [Byte 1] Lead/lag falling Transition (3, 6, 0)
1589 00:43:07.323875 3 6 4 |3e3d 3d3d |(11 11)(11 11) |(1 0)(1 0)| 0
1590 00:43:07.323923 [Byte 0] Lead/lag Transition tap number (2)
1591 00:43:07.323971 [Byte 1] Lead/lag Transition tap number (2)
1592 00:43:07.324020 3 6 8 |202 3e3d |(11 11)(11 11) |(0 0)(0 0)| 0
1593 00:43:07.324068 3 6 12 |4646 202 |(10 10)(11 11) |(0 0)(0 0)| 0
1594 00:43:07.324116 3 6 16 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1595 00:43:07.324163 [Byte 0]First pass (3, 6, 16)
1596 00:43:07.324210 [Byte 1]First pass (3, 6, 16)
1597 00:43:07.324257 3 6 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1598 00:43:07.324308 3 6 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1599 00:43:07.324358 3 6 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1600 00:43:07.324406 3 7 0 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1601 00:43:07.324454 3 7 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1602 00:43:07.324501 3 7 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1603 00:43:07.324551 3 7 12 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1604 00:43:07.324599 3 7 16 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1605 00:43:07.324647 All bytes gating window > 1UI, Early break!
1606 00:43:07.324693
1607 00:43:07.324739 best DQS0 dly(2T, 0.5T, PI) = (3, 6, 4)
1608 00:43:07.324785
1609 00:43:07.324833 best DQS1 dly(2T, 0.5T, PI) = (3, 6, 4)
1610 00:43:07.324880
1611 00:43:07.324927
1612 00:43:07.324973
1613 00:43:07.325019 best DQS0 P1 dly(2T, 0.5T, PI) = (4, 2, 4)
1614 00:43:07.325065
1615 00:43:07.325114 best DQS1 P1 dly(2T, 0.5T, PI) = (4, 2, 4)
1616 00:43:07.325160
1617 00:43:07.325204
1618 00:43:07.325250 Write Rank1 MR1 =0x56
1619 00:43:07.325296
1620 00:43:07.325342 best RODT dly(2T, 0.5T) = (2, 3)
1621 00:43:07.325391
1622 00:43:07.325438 best RODT dly(2T, 0.5T) = (2, 3)
1623 00:43:07.325484 ==
1624 00:43:07.325531 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1625 00:43:07.325578 fsp= 1, odt_onoff= 1, Byte mode= 0
1626 00:43:07.325624 ==
1627 00:43:07.325674 Start DQ dly to find pass range UseTestEngine =0
1628 00:43:07.325721 x-axis: bit #, y-axis: DQ dly (-127~63)
1629 00:43:07.325767 RX Vref Scan = 0
1630 00:43:07.325814 -26, [0] xxxxxxxx xxxxxxxx [MSB]
1631 00:43:07.325861 -25, [0] xxxxxxxx xxxxxxxx [MSB]
1632 00:43:07.325909 -24, [0] xxxxxxxx xxxxxxxx [MSB]
1633 00:43:07.325959 -23, [0] xxxxxxxx xxxxxxxx [MSB]
1634 00:43:07.326009 -22, [0] xxxxxxxx xxxxxxxx [MSB]
1635 00:43:07.326057 -21, [0] xxxxxxxx xxxxxxxx [MSB]
1636 00:43:07.326104 -20, [0] xxxxxxxx xxxxxxxx [MSB]
1637 00:43:07.326150 -19, [0] xxxxxxxx xxxxxxxx [MSB]
1638 00:43:07.326198 -18, [0] xxxxxxxx xxxxxxxx [MSB]
1639 00:43:07.326266 -17, [0] xxxxxxxx xxxxxxxx [MSB]
1640 00:43:07.326316 -16, [0] xxxxxxxx xxxxxxxx [MSB]
1641 00:43:07.326364 -15, [0] xxxxxxxx xxxxxxxx [MSB]
1642 00:43:07.326411 -14, [0] xxxxxxxx xxxxxxxx [MSB]
1643 00:43:07.326458 -13, [0] xxxxxxxx xxxxxxxx [MSB]
1644 00:43:07.326697 -12, [0] xxxxxxxx xxxxxxxx [MSB]
1645 00:43:07.326752 -11, [0] xxxxxxxx xxxxxxxx [MSB]
1646 00:43:07.326803 -10, [0] xxxxxxxx xxxxxxxx [MSB]
1647 00:43:07.326851 -9, [0] xxxxxxxx xxxxxxxx [MSB]
1648 00:43:07.326898 -8, [0] xxxxxxxx xxxxxxxx [MSB]
1649 00:43:07.326946 -7, [0] xxxxxxxx xxxxxxxx [MSB]
1650 00:43:07.326994 -6, [0] xxxxxxxx xxxxxxxx [MSB]
1651 00:43:07.327044 -5, [0] xxxxxxxx xxxxxxxx [MSB]
1652 00:43:07.327092 -4, [0] xxxoxxxx xxxxxxxx [MSB]
1653 00:43:07.327142 -3, [0] xxxoxxxx xxxxxxxx [MSB]
1654 00:43:07.327189 -2, [0] xxxoxxxx xxxxxxxx [MSB]
1655 00:43:07.327236 -1, [0] xxxoxoxo xxxxxxxx [MSB]
1656 00:43:07.327286 0, [0] xxxoxooo ooxoxoxx [MSB]
1657 00:43:07.327334 1, [0] xxxoxooo ooxoooox [MSB]
1658 00:43:07.327382 2, [0] xxxoxooo ooxooooo [MSB]
1659 00:43:07.327429 3, [0] xxxoxooo ooxooooo [MSB]
1660 00:43:07.327476 4, [0] xxxooooo ooxooooo [MSB]
1661 00:43:07.327524 5, [0] xooooooo oooooooo [MSB]
1662 00:43:07.327574 6, [0] xooooooo oooooooo [MSB]
1663 00:43:07.327622 33, [0] oooxoooo oooooooo [MSB]
1664 00:43:07.327670 34, [0] oooxoxoo oooooooo [MSB]
1665 00:43:07.327717 35, [0] oooxoxoo oooxooxo [MSB]
1666 00:43:07.327764 36, [0] oooxoxxo xooxooxo [MSB]
1667 00:43:07.327811 37, [0] oooxoxxx xooxoxxo [MSB]
1668 00:43:07.327861 38, [0] oooxoxxx xxoxxxxo [MSB]
1669 00:43:07.327907 39, [0] oooxoxxx xxoxxxxo [MSB]
1670 00:43:07.327954 40, [0] oxoxoxxx xxoxxxxx [MSB]
1671 00:43:07.328002 41, [0] oxxxxxxx xxoxxxxx [MSB]
1672 00:43:07.328050 42, [0] xxxxxxxx xxoxxxxx [MSB]
1673 00:43:07.328096 43, [0] xxxxxxxx xxxxxxxx [MSB]
1674 00:43:07.328146 iDelay=43, Bit 0, Center 24 (7 ~ 41) 35
1675 00:43:07.328196 iDelay=43, Bit 1, Center 22 (5 ~ 39) 35
1676 00:43:07.328242 iDelay=43, Bit 2, Center 22 (5 ~ 40) 36
1677 00:43:07.328289 iDelay=43, Bit 3, Center 14 (-4 ~ 32) 37
1678 00:43:07.328335 iDelay=43, Bit 4, Center 22 (4 ~ 40) 37
1679 00:43:07.328382 iDelay=43, Bit 5, Center 16 (-1 ~ 33) 35
1680 00:43:07.328431 iDelay=43, Bit 6, Center 17 (0 ~ 35) 36
1681 00:43:07.328478 iDelay=43, Bit 7, Center 17 (-1 ~ 36) 38
1682 00:43:07.328525 iDelay=43, Bit 8, Center 17 (0 ~ 35) 36
1683 00:43:07.328571 iDelay=43, Bit 9, Center 18 (0 ~ 37) 38
1684 00:43:07.328618 iDelay=43, Bit 10, Center 23 (5 ~ 42) 38
1685 00:43:07.328665 iDelay=43, Bit 11, Center 17 (0 ~ 34) 35
1686 00:43:07.328714 iDelay=43, Bit 12, Center 19 (1 ~ 37) 37
1687 00:43:07.328762 iDelay=43, Bit 13, Center 18 (0 ~ 36) 37
1688 00:43:07.328808 iDelay=43, Bit 14, Center 17 (1 ~ 34) 34
1689 00:43:07.328855 iDelay=43, Bit 15, Center 20 (2 ~ 39) 38
1690 00:43:07.328902 ==
1691 00:43:07.328948 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1692 00:43:07.328998 fsp= 1, odt_onoff= 1, Byte mode= 0
1693 00:43:07.329046 ==
1694 00:43:07.329092 DQS Delay:
1695 00:43:07.329137 DQS0 = 0, DQS1 = 0
1696 00:43:07.329183 DQM Delay:
1697 00:43:07.329232 DQM0 = 19, DQM1 = 18
1698 00:43:07.329279 DQ Delay:
1699 00:43:07.329327 DQ0 =24, DQ1 =22, DQ2 =22, DQ3 =14
1700 00:43:07.329374 DQ4 =22, DQ5 =16, DQ6 =17, DQ7 =17
1701 00:43:07.329420 DQ8 =17, DQ9 =18, DQ10 =23, DQ11 =17
1702 00:43:07.329467 DQ12 =19, DQ13 =18, DQ14 =17, DQ15 =20
1703 00:43:07.329517
1704 00:43:07.329564
1705 00:43:07.329609 DramC Write-DBI off
1706 00:43:07.329655 ==
1707 00:43:07.329701 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1708 00:43:07.329747 fsp= 1, odt_onoff= 1, Byte mode= 0
1709 00:43:07.329797 ==
1710 00:43:07.329845 [TxWindowPerbitCal] calType=2, VrefScanEnable 0
1711 00:43:07.329892
1712 00:43:07.329938 Begin, DQ Scan Range 926~1182
1713 00:43:07.329985
1714 00:43:07.330030
1715 00:43:07.330079 TX Vref Scan disable
1716 00:43:07.330125 926 |3 4 30|[0] xxxxxxxx xxxxxxxx [MSB]
1717 00:43:07.330173 927 |3 4 31|[0] xxxxxxxx xxxxxxxx [MSB]
1718 00:43:07.330228 928 |3 4 32|[0] xxxxxxxx xxxxxxxx [MSB]
1719 00:43:07.330315 929 |3 4 33|[0] xxxxxxxx xxxxxxxx [MSB]
1720 00:43:07.330365 930 |3 4 34|[0] xxxxxxxx xxxxxxxx [MSB]
1721 00:43:07.330412 931 |3 4 35|[0] xxxxxxxx xxxxxxxx [MSB]
1722 00:43:07.330459 932 |3 4 36|[0] xxxxxxxx xxxxxxxx [MSB]
1723 00:43:07.330506 933 |3 4 37|[0] xxxxxxxx xxxxxxxx [MSB]
1724 00:43:07.330553 934 |3 4 38|[0] xxxxxxxx xxxxxxxx [MSB]
1725 00:43:07.330604 935 |3 4 39|[0] xxxxxxxx xxxxxxxx [MSB]
1726 00:43:07.330652 936 |3 4 40|[0] xxxxxxxx xxxxxxxx [MSB]
1727 00:43:07.330737 937 |3 4 41|[0] xxxxxxxx xxxxxxxx [MSB]
1728 00:43:07.330789 938 |3 4 42|[0] xxxxxxxx xxxxxxxx [MSB]
1729 00:43:07.330840 939 |3 4 43|[0] xxxxxxxx xxxxxxxx [MSB]
1730 00:43:07.330889 940 |3 4 44|[0] xxxxxxxx xxxxxxxx [MSB]
1731 00:43:07.330938 941 |3 4 45|[0] xxxxxxxx xxxxxxxx [MSB]
1732 00:43:07.330986 942 |3 4 46|[0] xxxxxxxx xxxxxxxx [MSB]
1733 00:43:07.331033 943 |3 4 47|[0] xxxxxxxx xxxxxxxx [MSB]
1734 00:43:07.331084 944 |3 4 48|[0] xxxxxxxx xxxxxxxx [MSB]
1735 00:43:07.331132 945 |3 4 49|[0] xxxxxxxx xxxxxxxx [MSB]
1736 00:43:07.331180 946 |3 4 50|[0] xxxxxxxx xxxxxxxx [MSB]
1737 00:43:07.331227 947 |3 4 51|[0] xxxxxxxx xxxxxxxx [MSB]
1738 00:43:07.331275 948 |3 4 52|[0] xxxxxxxx xxxxxxxx [MSB]
1739 00:43:07.331325 949 |3 4 53|[0] xxxxxxxx xxxxxxxx [MSB]
1740 00:43:07.331373 950 |3 4 54|[0] xxxxxxxx xxxxxxxx [MSB]
1741 00:43:07.331423 951 |3 4 55|[0] xxxxxxxx xxxxxxxx [MSB]
1742 00:43:07.331470 952 |3 4 56|[0] xxxxxxxx xxxxxxxx [MSB]
1743 00:43:07.331517 953 |3 4 57|[0] xxxxxxxx xxxxxxxx [MSB]
1744 00:43:07.331564 954 |3 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
1745 00:43:07.331612 955 |3 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
1746 00:43:07.331663 956 |3 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
1747 00:43:07.331710 957 |3 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
1748 00:43:07.331758 958 |3 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
1749 00:43:07.331805 959 |3 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
1750 00:43:07.331851 960 |3 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
1751 00:43:07.331902 961 |3 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
1752 00:43:07.331951 962 |3 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
1753 00:43:07.331998 963 |3 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
1754 00:43:07.332046 964 |3 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
1755 00:43:07.332094 965 |3 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
1756 00:43:07.332141 966 |3 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
1757 00:43:07.332191 967 |3 6 7|[0] xxxxxxxx oxxoxxxx [MSB]
1758 00:43:07.332238 968 |3 6 8|[0] xxxxxxxx ooxoooox [MSB]
1759 00:43:07.332286 969 |3 6 9|[0] xxxxxxxx ooxooooo [MSB]
1760 00:43:07.332333 970 |3 6 10|[0] xxxxxxxx ooxoooox [MSB]
1761 00:43:07.332381 971 |3 6 11|[0] xxxxxxxx ooxooooo [MSB]
1762 00:43:07.332616 972 |3 6 12|[0] xxxxxxxx ooxooooo [MSB]
1763 00:43:07.332673 973 |3 6 13|[0] xxxxxxxx oooooooo [MSB]
1764 00:43:07.332722 974 |3 6 14|[0] xxxoxoox oooooooo [MSB]
1765 00:43:07.332770 975 |3 6 15|[0] xxxoxoox oooooooo [MSB]
1766 00:43:07.332818 976 |3 6 16|[0] xxxoooox oooooooo [MSB]
1767 00:43:07.332866 990 |3 6 30|[0] oooooooo xxxxxxxx [MSB]
1768 00:43:07.332914 991 |3 6 31|[0] oooooooo xxxxxxxx [MSB]
1769 00:43:07.332967 992 |3 6 32|[0] oooooooo xxxxxxxx [MSB]
1770 00:43:07.333016 993 |3 6 33|[0] oooxoooo xxxxxxxx [MSB]
1771 00:43:07.333064 994 |3 6 34|[0] oooxoooo xxxxxxxx [MSB]
1772 00:43:07.333111 995 |3 6 35|[0] oooxoxoo xxxxxxxx [MSB]
1773 00:43:07.333158 996 |3 6 36|[0] oooxoxoo xxxxxxxx [MSB]
1774 00:43:07.333208 997 |3 6 37|[0] oooxoxxo xxxxxxxx [MSB]
1775 00:43:07.333256 998 |3 6 38|[0] xxxxxxxx xxxxxxxx [MSB]
1776 00:43:07.333304 Byte0, DQ PI dly=985, DQM PI dly= 985
1777 00:43:07.333351 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 25)
1778 00:43:07.333398
1779 00:43:07.333444 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 25)
1780 00:43:07.333495
1781 00:43:07.333543 Byte1, DQ PI dly=979, DQM PI dly= 979
1782 00:43:07.333590 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 19)
1783 00:43:07.333637
1784 00:43:07.333683 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 19)
1785 00:43:07.333730
1786 00:43:07.333780 ==
1787 00:43:07.333826 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1788 00:43:07.333873 fsp= 1, odt_onoff= 1, Byte mode= 0
1789 00:43:07.333920 ==
1790 00:43:07.333967 [TxWindowPerbitCal] calType=0, VrefScanEnable 1
1791 00:43:07.334016
1792 00:43:07.334063 Begin, DQ Scan Range 955~1019
1793 00:43:07.334112 Write Rank1 MR14 =0x0
1794 00:43:07.334158
1795 00:43:07.334205 CH=0, VrefRange= 0, VrefLevel = 0
1796 00:43:07.334293 TX Bit0 (979~997) 19 988, Bit8 (968~988) 21 978,
1797 00:43:07.334344 TX Bit1 (978~996) 19 987, Bit9 (970~989) 20 979,
1798 00:43:07.334390 TX Bit2 (978~996) 19 987, Bit10 (975~991) 17 983,
1799 00:43:07.334437 TX Bit3 (975~990) 16 982, Bit11 (969~987) 19 978,
1800 00:43:07.334484 TX Bit4 (977~997) 21 987, Bit12 (972~989) 18 980,
1801 00:43:07.334531 TX Bit5 (976~990) 15 983, Bit13 (971~986) 16 978,
1802 00:43:07.334580 TX Bit6 (976~991) 16 983, Bit14 (972~988) 17 980,
1803 00:43:07.334628 TX Bit7 (978~992) 15 985, Bit15 (973~990) 18 981,
1804 00:43:07.334677
1805 00:43:07.334723 Write Rank1 MR14 =0x2
1806 00:43:07.334768
1807 00:43:07.334814 CH=0, VrefRange= 0, VrefLevel = 2
1808 00:43:07.334864 TX Bit0 (978~998) 21 988, Bit8 (969~988) 20 978,
1809 00:43:07.334912 TX Bit1 (978~996) 19 987, Bit9 (970~989) 20 979,
1810 00:43:07.334958 TX Bit2 (978~997) 20 987, Bit10 (975~991) 17 983,
1811 00:43:07.335005 TX Bit3 (975~990) 16 982, Bit11 (969~988) 20 978,
1812 00:43:07.335051 TX Bit4 (977~997) 21 987, Bit12 (972~989) 18 980,
1813 00:43:07.335098 TX Bit5 (976~991) 16 983, Bit13 (970~987) 18 978,
1814 00:43:07.335147 TX Bit6 (976~991) 16 983, Bit14 (972~989) 18 980,
1815 00:43:07.335196 TX Bit7 (978~993) 16 985, Bit15 (973~990) 18 981,
1816 00:43:07.335242
1817 00:43:07.335288 Write Rank1 MR14 =0x4
1818 00:43:07.335335
1819 00:43:07.335380 CH=0, VrefRange= 0, VrefLevel = 4
1820 00:43:07.335430 TX Bit0 (978~998) 21 988, Bit8 (968~988) 21 978,
1821 00:43:07.335477 TX Bit1 (978~997) 20 987, Bit9 (969~989) 21 979,
1822 00:43:07.335524 TX Bit2 (978~997) 20 987, Bit10 (975~991) 17 983,
1823 00:43:07.335571 TX Bit3 (974~990) 17 982, Bit11 (969~989) 21 979,
1824 00:43:07.335618 TX Bit4 (977~997) 21 987, Bit12 (970~989) 20 979,
1825 00:43:07.335664 TX Bit5 (975~991) 17 983, Bit13 (969~987) 19 978,
1826 00:43:07.335713 TX Bit6 (976~992) 17 984, Bit14 (970~989) 20 979,
1827 00:43:07.335761 TX Bit7 (977~994) 18 985, Bit15 (972~991) 20 981,
1828 00:43:07.335808
1829 00:43:07.335855 Write Rank1 MR14 =0x6
1830 00:43:07.335901
1831 00:43:07.335947 CH=0, VrefRange= 0, VrefLevel = 6
1832 00:43:07.335997 TX Bit0 (978~998) 21 988, Bit8 (968~989) 22 978,
1833 00:43:07.336044 TX Bit1 (978~997) 20 987, Bit9 (969~989) 21 979,
1834 00:43:07.336091 TX Bit2 (978~998) 21 988, Bit10 (975~992) 18 983,
1835 00:43:07.336137 TX Bit3 (974~990) 17 982, Bit11 (968~989) 22 978,
1836 00:43:07.336184 TX Bit4 (977~998) 22 987, Bit12 (972~990) 19 981,
1837 00:43:07.336230 TX Bit5 (975~992) 18 983, Bit13 (970~988) 19 979,
1838 00:43:07.336280 TX Bit6 (976~993) 18 984, Bit14 (971~989) 19 980,
1839 00:43:07.336329 TX Bit7 (977~994) 18 985, Bit15 (972~991) 20 981,
1840 00:43:07.336375
1841 00:43:07.336421 Write Rank1 MR14 =0x8
1842 00:43:07.336466
1843 00:43:07.336513 CH=0, VrefRange= 0, VrefLevel = 8
1844 00:43:07.336562 TX Bit0 (978~999) 22 988, Bit8 (967~989) 23 978,
1845 00:43:07.336610 TX Bit1 (978~997) 20 987, Bit9 (968~990) 23 979,
1846 00:43:07.336656 TX Bit2 (978~998) 21 988, Bit10 (974~992) 19 983,
1847 00:43:07.336703 TX Bit3 (973~991) 19 982, Bit11 (968~989) 22 978,
1848 00:43:07.336750 TX Bit4 (977~998) 22 987, Bit12 (969~990) 22 979,
1849 00:43:07.336799 TX Bit5 (975~992) 18 983, Bit13 (969~988) 20 978,
1850 00:43:07.336847 TX Bit6 (975~993) 19 984, Bit14 (971~990) 20 980,
1851 00:43:07.336895 TX Bit7 (977~995) 19 986, Bit15 (972~991) 20 981,
1852 00:43:07.336942
1853 00:43:07.336989 Write Rank1 MR14 =0xa
1854 00:43:07.337035
1855 00:43:07.337083 CH=0, VrefRange= 0, VrefLevel = 10
1856 00:43:07.337130 TX Bit0 (978~999) 22 988, Bit8 (967~989) 23 978,
1857 00:43:07.337177 TX Bit1 (977~998) 22 987, Bit9 (968~990) 23 979,
1858 00:43:07.337224 TX Bit2 (977~998) 22 987, Bit10 (974~992) 19 983,
1859 00:43:07.337271 TX Bit3 (973~991) 19 982, Bit11 (968~990) 23 979,
1860 00:43:07.337320 TX Bit4 (977~998) 22 987, Bit12 (969~990) 22 979,
1861 00:43:07.337371 TX Bit5 (975~992) 18 983, Bit13 (968~989) 22 978,
1862 00:43:07.337419 TX Bit6 (975~994) 20 984, Bit14 (969~990) 22 979,
1863 00:43:07.337467 TX Bit7 (977~995) 19 986, Bit15 (972~991) 20 981,
1864 00:43:07.337513
1865 00:43:07.337559 Write Rank1 MR14 =0xc
1866 00:43:07.337606
1867 00:43:07.337655 CH=0, VrefRange= 0, VrefLevel = 12
1868 00:43:07.337702 TX Bit0 (978~999) 22 988, Bit8 (967~989) 23 978,
1869 00:43:07.337940 TX Bit1 (977~998) 22 987, Bit9 (968~990) 23 979,
1870 00:43:07.337994 TX Bit2 (977~998) 22 987, Bit10 (974~993) 20 983,
1871 00:43:07.338043 TX Bit3 (973~991) 19 982, Bit11 (968~990) 23 979,
1872 00:43:07.338089 TX Bit4 (977~998) 22 987, Bit12 (969~990) 22 979,
1873 00:43:07.338136 TX Bit5 (974~993) 20 983, Bit13 (968~989) 22 978,
1874 00:43:07.338186 TX Bit6 (975~994) 20 984, Bit14 (969~990) 22 979,
1875 00:43:07.338280 TX Bit7 (977~996) 20 986, Bit15 (971~992) 22 981,
1876 00:43:07.338327
1877 00:43:07.338373 Write Rank1 MR14 =0xe
1878 00:43:07.338419
1879 00:43:07.338469 CH=0, VrefRange= 0, VrefLevel = 14
1880 00:43:07.338518 TX Bit0 (977~1000) 24 988, Bit8 (967~990) 24 978,
1881 00:43:07.338565 TX Bit1 (977~998) 22 987, Bit9 (968~990) 23 979,
1882 00:43:07.338612 TX Bit2 (977~999) 23 988, Bit10 (974~993) 20 983,
1883 00:43:07.338659 TX Bit3 (972~992) 21 982, Bit11 (967~990) 24 978,
1884 00:43:07.338709 TX Bit4 (977~999) 23 988, Bit12 (968~990) 23 979,
1885 00:43:07.338756 TX Bit5 (974~994) 21 984, Bit13 (968~989) 22 978,
1886 00:43:07.338803 TX Bit6 (974~995) 22 984, Bit14 (969~990) 22 979,
1887 00:43:07.338850 TX Bit7 (977~997) 21 987, Bit15 (971~992) 22 981,
1888 00:43:07.338897
1889 00:43:07.338942 Write Rank1 MR14 =0x10
1890 00:43:07.338990
1891 00:43:07.339036 CH=0, VrefRange= 0, VrefLevel = 16
1892 00:43:07.339085 TX Bit0 (977~1001) 25 989, Bit8 (967~990) 24 978,
1893 00:43:07.339132 TX Bit1 (977~998) 22 987, Bit9 (968~990) 23 979,
1894 00:43:07.339179 TX Bit2 (977~999) 23 988, Bit10 (974~994) 21 984,
1895 00:43:07.339226 TX Bit3 (972~992) 21 982, Bit11 (967~990) 24 978,
1896 00:43:07.339275 TX Bit4 (976~1000) 25 988, Bit12 (968~991) 24 979,
1897 00:43:07.339322 TX Bit5 (973~994) 22 983, Bit13 (968~989) 22 978,
1898 00:43:07.339368 TX Bit6 (974~996) 23 985, Bit14 (968~990) 23 979,
1899 00:43:07.339415 TX Bit7 (977~997) 21 987, Bit15 (971~992) 22 981,
1900 00:43:07.339461
1901 00:43:07.339508 Write Rank1 MR14 =0x12
1902 00:43:07.339557
1903 00:43:07.339605 CH=0, VrefRange= 0, VrefLevel = 18
1904 00:43:07.339652 TX Bit0 (977~1001) 25 989, Bit8 (967~990) 24 978,
1905 00:43:07.339699 TX Bit1 (977~999) 23 988, Bit9 (968~991) 24 979,
1906 00:43:07.339747 TX Bit2 (977~1000) 24 988, Bit10 (973~994) 22 983,
1907 00:43:07.339796 TX Bit3 (971~993) 23 982, Bit11 (967~990) 24 978,
1908 00:43:07.339843 TX Bit4 (976~1000) 25 988, Bit12 (968~991) 24 979,
1909 00:43:07.339890 TX Bit5 (973~994) 22 983, Bit13 (968~990) 23 979,
1910 00:43:07.339937 TX Bit6 (974~996) 23 985, Bit14 (968~991) 24 979,
1911 00:43:07.339984 TX Bit7 (976~997) 22 986, Bit15 (970~993) 24 981,
1912 00:43:07.340033
1913 00:43:07.340080 Write Rank1 MR14 =0x14
1914 00:43:07.340128
1915 00:43:07.340174 CH=0, VrefRange= 0, VrefLevel = 20
1916 00:43:07.340220 TX Bit0 (977~1001) 25 989, Bit8 (967~990) 24 978,
1917 00:43:07.340270 TX Bit1 (977~999) 23 988, Bit9 (968~990) 23 979,
1918 00:43:07.340317 TX Bit2 (977~1000) 24 988, Bit10 (973~995) 23 984,
1919 00:43:07.340364 TX Bit3 (971~993) 23 982, Bit11 (967~990) 24 978,
1920 00:43:07.340411 TX Bit4 (976~1000) 25 988, Bit12 (968~991) 24 979,
1921 00:43:07.340457 TX Bit5 (972~995) 24 983, Bit13 (967~990) 24 978,
1922 00:43:07.340504 TX Bit6 (973~997) 25 985, Bit14 (968~991) 24 979,
1923 00:43:07.340554 TX Bit7 (975~998) 24 986, Bit15 (970~993) 24 981,
1924 00:43:07.340602
1925 00:43:07.340648 Write Rank1 MR14 =0x16
1926 00:43:07.340693
1927 00:43:07.340740 CH=0, VrefRange= 0, VrefLevel = 22
1928 00:43:07.340786 TX Bit0 (977~1002) 26 989, Bit8 (967~990) 24 978,
1929 00:43:07.340837 TX Bit1 (977~999) 23 988, Bit9 (967~991) 25 979,
1930 00:43:07.340884 TX Bit2 (976~1000) 25 988, Bit10 (973~995) 23 984,
1931 00:43:07.340931 TX Bit3 (971~994) 24 982, Bit11 (967~991) 25 979,
1932 00:43:07.340977 TX Bit4 (976~1001) 26 988, Bit12 (968~991) 24 979,
1933 00:43:07.341025 TX Bit5 (972~996) 25 984, Bit13 (967~990) 24 978,
1934 00:43:07.341070 TX Bit6 (972~997) 26 984, Bit14 (967~991) 25 979,
1935 00:43:07.341120 TX Bit7 (976~998) 23 987, Bit15 (969~993) 25 981,
1936 00:43:07.341169
1937 00:43:07.341215 Write Rank1 MR14 =0x18
1938 00:43:07.341261
1939 00:43:07.341306 CH=0, VrefRange= 0, VrefLevel = 24
1940 00:43:07.341353 TX Bit0 (977~1002) 26 989, Bit8 (966~990) 25 978,
1941 00:43:07.341404 TX Bit1 (976~1000) 25 988, Bit9 (967~991) 25 979,
1942 00:43:07.341452 TX Bit2 (976~1000) 25 988, Bit10 (973~996) 24 984,
1943 00:43:07.341498 TX Bit3 (970~994) 25 982, Bit11 (967~991) 25 979,
1944 00:43:07.341545 TX Bit4 (976~1001) 26 988, Bit12 (968~991) 24 979,
1945 00:43:07.341592 TX Bit5 (971~995) 25 983, Bit13 (967~990) 24 978,
1946 00:43:07.341639 TX Bit6 (972~997) 26 984, Bit14 (967~991) 25 979,
1947 00:43:07.341692 TX Bit7 (975~998) 24 986, Bit15 (969~992) 24 980,
1948 00:43:07.341740
1949 00:43:07.341786 Write Rank1 MR14 =0x1a
1950 00:43:07.341832
1951 00:43:07.341878 CH=0, VrefRange= 0, VrefLevel = 26
1952 00:43:07.341925 TX Bit0 (977~1002) 26 989, Bit8 (966~990) 25 978,
1953 00:43:07.341974 TX Bit1 (976~1000) 25 988, Bit9 (967~991) 25 979,
1954 00:43:07.342021 TX Bit2 (976~1000) 25 988, Bit10 (973~996) 24 984,
1955 00:43:07.342068 TX Bit3 (970~994) 25 982, Bit11 (967~991) 25 979,
1956 00:43:07.342115 TX Bit4 (976~1001) 26 988, Bit12 (968~991) 24 979,
1957 00:43:07.342161 TX Bit5 (971~995) 25 983, Bit13 (967~990) 24 978,
1958 00:43:07.342208 TX Bit6 (972~997) 26 984, Bit14 (967~991) 25 979,
1959 00:43:07.342298 TX Bit7 (975~998) 24 986, Bit15 (969~992) 24 980,
1960 00:43:07.342345
1961 00:43:07.342390 Write Rank1 MR14 =0x1c
1962 00:43:07.342436
1963 00:43:07.342482 CH=0, VrefRange= 0, VrefLevel = 28
1964 00:43:07.342533 TX Bit0 (977~1002) 26 989, Bit8 (966~990) 25 978,
1965 00:43:07.342580 TX Bit1 (976~1000) 25 988, Bit9 (967~991) 25 979,
1966 00:43:07.342627 TX Bit2 (976~1000) 25 988, Bit10 (973~996) 24 984,
1967 00:43:07.342674 TX Bit3 (970~994) 25 982, Bit11 (967~991) 25 979,
1968 00:43:07.342906 TX Bit4 (976~1001) 26 988, Bit12 (968~991) 24 979,
1969 00:43:07.342959 TX Bit5 (971~995) 25 983, Bit13 (967~990) 24 978,
1970 00:43:07.343007 TX Bit6 (972~997) 26 984, Bit14 (967~991) 25 979,
1971 00:43:07.343058 TX Bit7 (975~998) 24 986, Bit15 (969~992) 24 980,
1972 00:43:07.343106
1973 00:43:07.343152 Write Rank1 MR14 =0x1e
1974 00:43:07.343198
1975 00:43:07.343265 CH=0, VrefRange= 0, VrefLevel = 30
1976 00:43:07.618771 TX Bit0 (977~1002) 26 989, Bit8 (966~990) 25 978,
1977 00:43:07.618887 TX Bit1 (976~1000) 25 988, Bit9 (967~991) 25 979,
1978 00:43:07.618950 TX Bit2 (976~1000) 25 988, Bit10 (973~996) 24 984,
1979 00:43:07.619009 TX Bit3 (970~994) 25 982, Bit11 (967~991) 25 979,
1980 00:43:07.619061 TX Bit4 (976~1001) 26 988, Bit12 (968~991) 24 979,
1981 00:43:07.619111 TX Bit5 (971~995) 25 983, Bit13 (967~990) 24 978,
1982 00:43:07.619161 TX Bit6 (972~997) 26 984, Bit14 (967~991) 25 979,
1983 00:43:07.619211 TX Bit7 (975~998) 24 986, Bit15 (969~992) 24 980,
1984 00:43:07.619262
1985 00:43:07.619311
1986 00:43:07.619358 TX Vref found, early break! 377< 378
1987 00:43:07.619407 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =753/100 ps
1988 00:43:07.619455 u1DelayCellOfst[0]=9 cells (7 PI)
1989 00:43:07.619503 u1DelayCellOfst[1]=7 cells (6 PI)
1990 00:43:07.619550 u1DelayCellOfst[2]=7 cells (6 PI)
1991 00:43:07.619601 u1DelayCellOfst[3]=0 cells (0 PI)
1992 00:43:07.619648 u1DelayCellOfst[4]=7 cells (6 PI)
1993 00:43:07.619695 u1DelayCellOfst[5]=1 cells (1 PI)
1994 00:43:07.619742 u1DelayCellOfst[6]=2 cells (2 PI)
1995 00:43:07.619788 u1DelayCellOfst[7]=5 cells (4 PI)
1996 00:43:07.619835 Byte0, DQ PI dly=982, DQM PI dly= 985
1997 00:43:07.619886 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 22)
1998 00:43:07.619934
1999 00:43:07.619981 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 22)
2000 00:43:07.620030
2001 00:43:07.620077 u1DelayCellOfst[8]=0 cells (0 PI)
2002 00:43:07.620124 u1DelayCellOfst[9]=1 cells (1 PI)
2003 00:43:07.620174 u1DelayCellOfst[10]=7 cells (6 PI)
2004 00:43:07.620221 u1DelayCellOfst[11]=1 cells (1 PI)
2005 00:43:07.620268 u1DelayCellOfst[12]=1 cells (1 PI)
2006 00:43:07.620315 u1DelayCellOfst[13]=0 cells (0 PI)
2007 00:43:07.620361 u1DelayCellOfst[14]=1 cells (1 PI)
2008 00:43:07.620408 u1DelayCellOfst[15]=2 cells (2 PI)
2009 00:43:07.620457 Byte1, DQ PI dly=978, DQM PI dly= 981
2010 00:43:07.620504 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 18)
2011 00:43:07.620552
2012 00:43:07.620599 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 18)
2013 00:43:07.620647
2014 00:43:07.620694 Write Rank1 MR14 =0x18
2015 00:43:07.620744
2016 00:43:07.620791 Final TX Range 0 Vref 24
2017 00:43:07.620841
2018 00:43:07.620891 [TX_K_DQM_WITH_WDBI] Step1: K DQM with DBI_ON, and check DQM window spec.
2019 00:43:07.620940
2020 00:43:07.620987 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
2021 00:43:07.621038 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
2022 00:43:07.621086 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
2023 00:43:07.621133 Write Rank1 MR3 =0xb0
2024 00:43:07.621179 DramC Write-DBI on
2025 00:43:07.621226 ==
2026 00:43:07.621273 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
2027 00:43:07.621322 fsp= 1, odt_onoff= 1, Byte mode= 0
2028 00:43:07.621370 ==
2029 00:43:07.621418 [TxWindowPerbitCal] calType=1, VrefScanEnable 0
2030 00:43:07.621465
2031 00:43:07.621511 Begin, DQ Scan Range 701~765
2032 00:43:07.621558
2033 00:43:07.621607
2034 00:43:07.621655 TX Vref Scan disable
2035 00:43:07.621701 701 |2 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
2036 00:43:07.621749 702 |2 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
2037 00:43:07.621797 703 |2 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
2038 00:43:07.621844 704 |2 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
2039 00:43:07.621893 705 |2 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
2040 00:43:07.621944 706 |2 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
2041 00:43:07.621992 707 |2 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
2042 00:43:07.622039 708 |2 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
2043 00:43:07.622087 709 |2 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
2044 00:43:07.622135 710 |2 6 6|[0] xxxxxxxx oooooooo [MSB]
2045 00:43:07.622189 711 |2 6 7|[0] xxxxxxxx oooooooo [MSB]
2046 00:43:07.622249 712 |2 6 8|[0] xxxxxxxx oooooooo [MSB]
2047 00:43:07.622299 713 |2 6 9|[0] xxxxxxxx oooooooo [MSB]
2048 00:43:07.622347 714 |2 6 10|[0] xxxxxxxx oooooooo [MSB]
2049 00:43:07.622394 715 |2 6 11|[0] xxxxxxxx oooooooo [MSB]
2050 00:43:07.622442 716 |2 6 12|[0] xxxxxxxx oooooooo [MSB]
2051 00:43:07.622493 717 |2 6 13|[0] xxxxxxxx oooooooo [MSB]
2052 00:43:07.622541 735 |2 6 31|[0] oooooooo xxxxxxxx [MSB]
2053 00:43:07.622589 736 |2 6 32|[0] oooooooo xxxxxxxx [MSB]
2054 00:43:07.622637 737 |2 6 33|[0] oooooooo xxxxxxxx [MSB]
2055 00:43:07.622685 738 |2 6 34|[0] oooooooo xxxxxxxx [MSB]
2056 00:43:07.622732 739 |2 6 35|[0] oooooooo xxxxxxxx [MSB]
2057 00:43:07.622782 740 |2 6 36|[0] oooooooo xxxxxxxx [MSB]
2058 00:43:07.622831 741 |2 6 37|[0] oooooooo xxxxxxxx [MSB]
2059 00:43:07.622878 742 |2 6 38|[0] oooooooo xxxxxxxx [MSB]
2060 00:43:07.622926 743 |2 6 39|[0] oooooooo xxxxxxxx [MSB]
2061 00:43:07.622974 744 |2 6 40|[0] xxxxxxxx xxxxxxxx [MSB]
2062 00:43:07.623021 Byte0, DQ PI dly=730, DQM PI dly= 730
2063 00:43:07.623070 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 26)
2064 00:43:07.623117
2065 00:43:07.623164 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 26)
2066 00:43:07.623211
2067 00:43:07.623261 Byte1, DQ PI dly=722, DQM PI dly= 722
2068 00:43:07.623317 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 18)
2069 00:43:07.623369
2070 00:43:07.623416 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 18)
2071 00:43:07.623463
2072 00:43:07.623510 Before -1MCK, ucdq_final_ui_large_dqs0 = 2, ucdq_final_ui_large_dqs1 = 2
2073 00:43:07.623559 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
2074 00:43:07.623610 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
2075 00:43:07.623658 Write Rank1 MR3 =0x30
2076 00:43:07.623705 DramC Write-DBI off
2077 00:43:07.623752
2078 00:43:07.623798 [DATLAT]
2079 00:43:07.623844 Freq=1600, CH0 RK1, use_rxtx_scan=0
2080 00:43:07.623893
2081 00:43:07.623941 DATLAT Default: 0x10
2082 00:43:07.623988 7, 0xFFFF, sum=0
2083 00:43:07.624036 8, 0xFFFF, sum=0
2084 00:43:07.624084 9, 0xFFFF, sum=0
2085 00:43:07.624135 10, 0xFFFF, sum=0
2086 00:43:07.624192 11, 0xFFFF, sum=0
2087 00:43:07.624240 12, 0xFFFF, sum=0
2088 00:43:07.624288 13, 0xFFFF, sum=0
2089 00:43:07.624558 14, 0x0, sum=1
2090 00:43:07.624634 15, 0x0, sum=2
2091 00:43:07.624695 16, 0x0, sum=3
2092 00:43:07.624749 17, 0x0, sum=4
2093 00:43:07.624802 pattern=2 first_step=14 total pass=5 best_step=16
2094 00:43:07.624856 ==
2095 00:43:07.624911 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
2096 00:43:07.624963 fsp= 1, odt_onoff= 1, Byte mode= 0
2097 00:43:07.625017 ==
2098 00:43:07.625065 Start DQ dly to find pass range UseTestEngine =1
2099 00:43:07.625114 x-axis: bit #, y-axis: DQ dly (-127~63)
2100 00:43:07.625163 RX Vref Scan = 0
2101 00:43:07.625209 -26, [0] xxxxxxxx xxxxxxxx [MSB]
2102 00:43:07.625258 -25, [0] xxxxxxxx xxxxxxxx [MSB]
2103 00:43:07.625307 -24, [0] xxxxxxxx xxxxxxxx [MSB]
2104 00:43:07.625356 -23, [0] xxxxxxxx xxxxxxxx [MSB]
2105 00:43:07.625404 -22, [0] xxxxxxxx xxxxxxxx [MSB]
2106 00:43:07.625452 -21, [0] xxxxxxxx xxxxxxxx [MSB]
2107 00:43:07.625500 -20, [0] xxxxxxxx xxxxxxxx [MSB]
2108 00:43:07.625548 -19, [0] xxxxxxxx xxxxxxxx [MSB]
2109 00:43:07.625596 -18, [0] xxxxxxxx xxxxxxxx [MSB]
2110 00:43:07.625644 -17, [0] xxxxxxxx xxxxxxxx [MSB]
2111 00:43:07.625692 -16, [0] xxxxxxxx xxxxxxxx [MSB]
2112 00:43:07.625741 -15, [0] xxxxxxxx xxxxxxxx [MSB]
2113 00:43:07.625789 -14, [0] xxxxxxxx xxxxxxxx [MSB]
2114 00:43:07.625838 -13, [0] xxxxxxxx xxxxxxxx [MSB]
2115 00:43:07.625886 -12, [0] xxxxxxxx xxxxxxxx [MSB]
2116 00:43:07.625934 -11, [0] xxxxxxxx xxxxxxxx [MSB]
2117 00:43:07.625982 -10, [0] xxxxxxxx xxxxxxxx [MSB]
2118 00:43:07.626031 -9, [0] xxxxxxxx xxxxxxxx [MSB]
2119 00:43:07.626080 -8, [0] xxxxxxxx xxxxxxxx [MSB]
2120 00:43:07.626128 -7, [0] xxxxxxxx xxxxxxxx [MSB]
2121 00:43:07.626176 -6, [0] xxxxxxxx xxxxxxxx [MSB]
2122 00:43:07.626232 -5, [0] xxxxxxxx xxxxxxxx [MSB]
2123 00:43:07.626283 -4, [0] xxxoxxxx xxxxxxxx [MSB]
2124 00:43:07.626332 -3, [0] xxxoxxxx xxxxxxxx [MSB]
2125 00:43:07.626379 -2, [0] xxxoxoxx xxxxxxxx [MSB]
2126 00:43:07.626428 -1, [0] xxxoxoxx oxxxxxxx [MSB]
2127 00:43:07.626477 0, [0] xxxoxoxx oxxoxxxx [MSB]
2128 00:43:07.626526 1, [0] xxxoxoox oxxoxoxx [MSB]
2129 00:43:07.626575 2, [0] xxxoxooo ooxoooox [MSB]
2130 00:43:07.626624 3, [0] xxxoxooo ooxooooo [MSB]
2131 00:43:07.626671 4, [0] xxxoxooo ooxooooo [MSB]
2132 00:43:07.626719 5, [0] xoxoxooo ooxooooo [MSB]
2133 00:43:07.626767 6, [0] xoxooooo oooooooo [MSB]
2134 00:43:07.626815 32, [0] oooxoooo oooooooo [MSB]
2135 00:43:07.626863 33, [0] oooxoooo oooooooo [MSB]
2136 00:43:07.626911 34, [0] oooxoxoo oooooxoo [MSB]
2137 00:43:07.626959 35, [0] oooxoxox oooxoxxo [MSB]
2138 00:43:07.627007 36, [0] oooxoxxx xooxoxxo [MSB]
2139 00:43:07.627055 37, [0] oooxoxxx xxoxoxxo [MSB]
2140 00:43:07.627103 38, [0] oooxoxxx xxoxxxxo [MSB]
2141 00:43:07.627151 39, [0] oooxoxxx xxoxxxxx [MSB]
2142 00:43:07.627199 40, [0] ooxxoxxx xxoxxxxx [MSB]
2143 00:43:07.627247 41, [0] oxxxxxxx xxxxxxxx [MSB]
2144 00:43:07.627296 42, [0] xxxxxxxx xxxxxxxx [MSB]
2145 00:43:07.627343 iDelay=42, Bit 0, Center 24 (7 ~ 41) 35
2146 00:43:07.627399 iDelay=42, Bit 1, Center 22 (5 ~ 40) 36
2147 00:43:07.627448 iDelay=42, Bit 2, Center 23 (7 ~ 39) 33
2148 00:43:07.627495 iDelay=42, Bit 3, Center 13 (-4 ~ 31) 36
2149 00:43:07.627542 iDelay=42, Bit 4, Center 23 (6 ~ 40) 35
2150 00:43:07.627589 iDelay=42, Bit 5, Center 15 (-2 ~ 33) 36
2151 00:43:07.627636 iDelay=42, Bit 6, Center 18 (1 ~ 35) 35
2152 00:43:07.627683 iDelay=42, Bit 7, Center 18 (2 ~ 34) 33
2153 00:43:07.627730 iDelay=42, Bit 8, Center 17 (-1 ~ 35) 37
2154 00:43:07.627777 iDelay=42, Bit 9, Center 19 (2 ~ 36) 35
2155 00:43:07.627824 iDelay=42, Bit 10, Center 23 (6 ~ 40) 35
2156 00:43:07.627871 iDelay=42, Bit 11, Center 17 (0 ~ 34) 35
2157 00:43:07.627919 iDelay=42, Bit 12, Center 19 (2 ~ 37) 36
2158 00:43:07.627976 iDelay=42, Bit 13, Center 17 (1 ~ 33) 33
2159 00:43:07.628024 iDelay=42, Bit 14, Center 18 (2 ~ 34) 33
2160 00:43:07.628071 iDelay=42, Bit 15, Center 20 (3 ~ 38) 36
2161 00:43:07.628118 ==
2162 00:43:07.628166 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
2163 00:43:07.628214 fsp= 1, odt_onoff= 1, Byte mode= 0
2164 00:43:07.628260 ==
2165 00:43:07.628307 DQS Delay:
2166 00:43:07.628354 DQS0 = 0, DQS1 = 0
2167 00:43:07.628401 DQM Delay:
2168 00:43:07.628447 DQM0 = 19, DQM1 = 18
2169 00:43:07.628495 DQ Delay:
2170 00:43:07.628542 DQ0 =24, DQ1 =22, DQ2 =23, DQ3 =13
2171 00:43:07.628588 DQ4 =23, DQ5 =15, DQ6 =18, DQ7 =18
2172 00:43:07.628635 DQ8 =17, DQ9 =19, DQ10 =23, DQ11 =17
2173 00:43:07.628682 DQ12 =19, DQ13 =17, DQ14 =18, DQ15 =20
2174 00:43:07.628729
2175 00:43:07.628775
2176 00:43:07.628820
2177 00:43:07.628866 [DramC_TX_OE_Calibration] TA2
2178 00:43:07.628913 Original DQ_B0 (3 6) =30, OEN = 27
2179 00:43:07.628962 Original DQ_B1 (3 6) =30, OEN = 27
2180 00:43:07.629010 23, 0x0, End_B0=23 End_B1=23
2181 00:43:07.629058 24, 0x0, End_B0=24 End_B1=24
2182 00:43:07.629106 25, 0x0, End_B0=25 End_B1=25
2183 00:43:07.629154 26, 0x0, End_B0=26 End_B1=26
2184 00:43:07.629201 27, 0x0, End_B0=27 End_B1=27
2185 00:43:07.629248 28, 0x0, End_B0=28 End_B1=28
2186 00:43:07.629296 29, 0x0, End_B0=29 End_B1=29
2187 00:43:07.629347 30, 0x0, End_B0=30 End_B1=30
2188 00:43:07.629395 31, 0xFFFF, End_B0=30 End_B1=30
2189 00:43:07.629443 Byte0 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
2190 00:43:07.629491 Byte1 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
2191 00:43:07.629538
2192 00:43:07.629585
2193 00:43:07.629632 Write Rank1 MR23 =0x3f
2194 00:43:07.629679 [DQSOSC]
2195 00:43:07.629726 [DQSOSCAuto] RK1, (LSB)MR18= 0x8c, (MSB)MR19= 0x3, tDQSOscB0 = 346 ps tDQSOscB1 = 0 ps
2196 00:43:07.629775 CH0_RK1: MR19=0x3, MR18=0x8C, DQSOSC=346, MR23=63, INC=20, DEC=30
2197 00:43:07.629823 Write Rank1 MR23 =0x3f
2198 00:43:07.629870 [DQSOSC]
2199 00:43:07.629917 [DQSOSCAuto] RK1, (LSB)MR18= 0x8e, (MSB)MR19= 0x3, tDQSOscB0 = 346 ps tDQSOscB1 = 0 ps
2200 00:43:07.629965 CH0 RK1: MR19=3, MR18=8E
2201 00:43:07.630012 [RxdqsGatingPostProcess] freq 1600
2202 00:43:07.630060 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
2203 00:43:07.630107 Rank: 0
2204 00:43:07.630154 best DQS0 dly(2T, 0.5T) = (2, 5)
2205 00:43:07.630200 best DQS1 dly(2T, 0.5T) = (2, 5)
2206 00:43:07.630258 best DQS0 P1 dly(2T, 0.5T) = (3, 1)
2207 00:43:07.630306 best DQS1 P1 dly(2T, 0.5T) = (3, 1)
2208 00:43:07.630353 Rank: 1
2209 00:43:07.630400 best DQS0 dly(2T, 0.5T) = (2, 6)
2210 00:43:07.630447 best DQS1 dly(2T, 0.5T) = (2, 6)
2211 00:43:07.630494 best DQS0 P1 dly(2T, 0.5T) = (3, 2)
2212 00:43:07.630541 best DQS1 P1 dly(2T, 0.5T) = (3, 2)
2213 00:43:07.630588 TX_dly_DQSgated check: min 2 max 3, ChangeDQSINCTL=-1
2214 00:43:07.630827 DQSINCTL=5, RANKINCTL=3, u4XRTR2R=9
2215 00:43:07.630881 [DualRankRxdatlatCal] RK0: 16, RK1: 16, Final_Datlat 16
2216 00:43:07.630930 Write Rank0 MR13 =0x59
2217 00:43:07.630978 ==
2218 00:43:07.631024 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2219 00:43:07.631072 fsp= 1, odt_onoff= 1, Byte mode= 0
2220 00:43:07.631119 ==
2221 00:43:07.631167 === u2Vref_new: 0x56 --> 0x3a
2222 00:43:07.631215 === u2Vref_new: 0x58 --> 0x58
2223 00:43:07.631262 === u2Vref_new: 0x5a --> 0x5a
2224 00:43:07.631318 === u2Vref_new: 0x5c --> 0x78
2225 00:43:07.631375 === u2Vref_new: 0x5e --> 0x7a
2226 00:43:07.631427 === u2Vref_new: 0x60 --> 0x90
2227 00:43:07.631474 [CA 0] Center 37 (11~63) winsize 53
2228 00:43:07.631521 [CA 1] Center 36 (9~63) winsize 55
2229 00:43:07.631568 [CA 2] Center 34 (5~63) winsize 59
2230 00:43:07.631615 [CA 3] Center 33 (4~63) winsize 60
2231 00:43:07.631662 [CA 4] Center 34 (6~63) winsize 58
2232 00:43:07.631710 [CA 5] Center 27 (-1~56) winsize 58
2233 00:43:07.631756
2234 00:43:07.631803 [CATrainingPosCal] consider 1 rank data
2235 00:43:07.631851 u2DelayCellTimex100 = 753/100 ps
2236 00:43:07.631898 CA0 delay=37 (11~63),Diff = 10 PI (12 cell)
2237 00:43:07.631945 CA1 delay=36 (9~63),Diff = 9 PI (11 cell)
2238 00:43:07.631991 CA2 delay=34 (5~63),Diff = 7 PI (9 cell)
2239 00:43:07.632058 CA3 delay=33 (4~63),Diff = 6 PI (7 cell)
2240 00:43:07.632134 CA4 delay=34 (6~63),Diff = 7 PI (9 cell)
2241 00:43:07.632213 CA5 delay=27 (-1~56),Diff = 0 PI (0 cell)
2242 00:43:07.632269
2243 00:43:07.632317 CA PerBit enable=1, Macro0, CA PI delay=27
2244 00:43:07.632365 === u2Vref_new: 0x58 --> 0x58
2245 00:43:07.632412
2246 00:43:07.632458 Vref(ca) range 1: 24
2247 00:43:07.632505
2248 00:43:07.632551 CS Dly= 12 (43-0-32)
2249 00:43:07.632599 Write Rank0 MR13 =0xd8
2250 00:43:07.632647 Write Rank0 MR13 =0xd8
2251 00:43:07.632694 Write Rank0 MR12 =0x58
2252 00:43:07.632740 Write Rank1 MR13 =0x59
2253 00:43:07.632787 ==
2254 00:43:07.632834 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
2255 00:43:07.632882 fsp= 1, odt_onoff= 1, Byte mode= 0
2256 00:43:07.632929 ==
2257 00:43:07.632976 === u2Vref_new: 0x56 --> 0x3a
2258 00:43:07.633022 === u2Vref_new: 0x58 --> 0x58
2259 00:43:07.633070 === u2Vref_new: 0x5a --> 0x5a
2260 00:43:07.633117 === u2Vref_new: 0x5c --> 0x78
2261 00:43:07.633164 === u2Vref_new: 0x5e --> 0x7a
2262 00:43:07.633211 === u2Vref_new: 0x60 --> 0x90
2263 00:43:07.633259
2264 00:43:07.633315 CBT Vref found, early break!
2265 00:43:07.633365 [CA 0] Center 37 (11~63) winsize 53
2266 00:43:07.633413 [CA 1] Center 36 (9~63) winsize 55
2267 00:43:07.633461 [CA 2] Center 33 (4~63) winsize 60
2268 00:43:07.633508 [CA 3] Center 33 (4~63) winsize 60
2269 00:43:07.633556 [CA 4] Center 35 (8~63) winsize 56
2270 00:43:07.633603 [CA 5] Center 27 (-1~56) winsize 58
2271 00:43:07.633650
2272 00:43:07.633697 [CATrainingPosCal] consider 2 rank data
2273 00:43:07.633744 u2DelayCellTimex100 = 753/100 ps
2274 00:43:07.633791 CA0 delay=37 (11~63),Diff = 10 PI (12 cell)
2275 00:43:07.633838 CA1 delay=36 (9~63),Diff = 9 PI (11 cell)
2276 00:43:07.633885 CA2 delay=34 (5~63),Diff = 7 PI (9 cell)
2277 00:43:07.633932 CA3 delay=33 (4~63),Diff = 6 PI (7 cell)
2278 00:43:07.633979 CA4 delay=35 (8~63),Diff = 8 PI (10 cell)
2279 00:43:07.634042 CA5 delay=27 (-1~56),Diff = 0 PI (0 cell)
2280 00:43:07.634116
2281 00:43:07.634191 CA PerBit enable=1, Macro0, CA PI delay=27
2282 00:43:07.634286 === u2Vref_new: 0x58 --> 0x58
2283 00:43:07.634336
2284 00:43:07.634384 Vref(ca) range 1: 24
2285 00:43:07.634431
2286 00:43:07.634478 CS Dly= 12 (43-0-32)
2287 00:43:07.634525 Write Rank1 MR13 =0xd8
2288 00:43:07.634572 Write Rank1 MR13 =0xd8
2289 00:43:07.634619 Write Rank1 MR12 =0x58
2290 00:43:07.634666 [RankSwap] Rank num 2, (Multi 1), Rank 0
2291 00:43:07.634713 Write Rank0 MR2 =0xad
2292 00:43:07.634760 [Write Leveling]
2293 00:43:07.634806 delay byte0 byte1 byte2 byte3
2294 00:43:07.634853
2295 00:43:07.634900 10 0 0
2296 00:43:07.634947 11 0 0
2297 00:43:07.634996 12 0 0
2298 00:43:07.635044 13 0 0
2299 00:43:07.635093 14 0 0
2300 00:43:07.635141 15 0 0
2301 00:43:07.635188 16 0 0
2302 00:43:07.635236 17 0 0
2303 00:43:07.635286 18 0 0
2304 00:43:07.635352 19 0 0
2305 00:43:07.635404 20 0 0
2306 00:43:07.635452 21 0 0
2307 00:43:07.635500 22 0 0
2308 00:43:07.635547 23 0 0
2309 00:43:07.635595 24 0 0
2310 00:43:07.635642 25 0 0
2311 00:43:07.635690 26 0 0
2312 00:43:07.635738 27 0 0
2313 00:43:07.635786 28 0 0
2314 00:43:07.635833 29 0 0
2315 00:43:07.635881 30 0 0
2316 00:43:07.635929 31 0 0
2317 00:43:07.635976 32 0 0
2318 00:43:07.636024 33 0 ff
2319 00:43:07.636082 34 0 ff
2320 00:43:07.636131 35 0 ff
2321 00:43:07.636179 36 0 ff
2322 00:43:07.636227 37 ff ff
2323 00:43:07.636275 38 ff ff
2324 00:43:07.636323 39 ff ff
2325 00:43:07.636371 40 ff ff
2326 00:43:07.636418 41 ff ff
2327 00:43:07.636466 42 ff ff
2328 00:43:07.636513 43 ff ff
2329 00:43:07.636561 pass bytecount = 0xff (0xff: all bytes pass)
2330 00:43:07.636607
2331 00:43:07.636653 DQS0 dly: 37
2332 00:43:07.636700 DQS1 dly: 33
2333 00:43:07.636747 Write Rank0 MR2 =0x2d
2334 00:43:07.636794 [RankSwap] Rank num 2, (Multi 1), Rank 0
2335 00:43:07.636840 Write Rank0 MR1 =0xd6
2336 00:43:07.636887 [Gating]
2337 00:43:07.636934 ==
2338 00:43:07.636980 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2339 00:43:07.637029 fsp= 1, odt_onoff= 1, Byte mode= 0
2340 00:43:07.637076 ==
2341 00:43:07.637123 3 1 0 |3534 2c2b |(11 11)(11 11) |(1 1)(0 0)| 0
2342 00:43:07.637171 3 1 4 |3534 2c2b |(11 11)(11 11) |(0 0)(1 0)| 0
2343 00:43:07.637220 3 1 8 |3534 2c2b |(11 11)(11 11) |(0 0)(1 0)| 0
2344 00:43:07.637267 3 1 12 |3534 2c2b |(11 11)(11 11) |(0 0)(1 0)| 0
2345 00:43:07.637323 3 1 16 |3534 2c2b |(11 11)(11 11) |(0 0)(1 0)| 0
2346 00:43:07.637396 3 1 20 |3534 2c2b |(11 11)(11 11) |(0 0)(1 0)| 0
2347 00:43:07.637469 3 1 24 |3534 2c2b |(11 11)(11 11) |(0 1)(1 0)| 0
2348 00:43:07.637533 3 1 28 |3534 2c2b |(11 11)(11 11) |(1 1)(1 0)| 0
2349 00:43:07.637586 3 2 0 |201 2c2b |(11 11)(11 11) |(1 1)(1 0)| 0
2350 00:43:07.640875 3 2 4 |3d3d 201 |(11 11)(11 11) |(1 1)(0 0)| 0
2351 00:43:07.647535 3 2 8 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
2352 00:43:07.650957 3 2 12 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
2353 00:43:07.654202 3 2 16 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
2354 00:43:07.660904 3 2 20 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
2355 00:43:07.664266 3 2 24 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
2356 00:43:07.667630 3 2 28 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
2357 00:43:07.670965 3 3 0 |3d3d 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
2358 00:43:07.677569 3 3 4 |403 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
2359 00:43:07.681252 3 3 8 |2c2b 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
2360 00:43:07.684441 [Byte 0] Lead/lag Transition tap number (1)
2361 00:43:07.687933 3 3 12 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
2362 00:43:07.694502 3 3 16 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
2363 00:43:07.697971 3 3 20 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
2364 00:43:07.701225 3 3 24 |3534 3534 |(11 11)(11 11) |(0 1)(0 0)| 0
2365 00:43:07.707996 3 3 28 |3534 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
2366 00:43:07.711347 3 4 0 |201 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
2367 00:43:07.714987 3 4 4 |3d3d 706 |(11 11)(11 11) |(1 1)(1 1)| 0
2368 00:43:07.718149 3 4 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2369 00:43:07.724991 3 4 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2370 00:43:07.728305 3 4 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2371 00:43:07.731535 3 4 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2372 00:43:07.738132 3 4 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2373 00:43:07.741583 3 4 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2374 00:43:07.745215 3 5 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2375 00:43:07.751603 3 5 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2376 00:43:07.755082 3 5 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2377 00:43:07.758166 3 5 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2378 00:43:07.764832 3 5 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2379 00:43:07.768329 3 5 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2380 00:43:07.771762 [Byte 0] Lead/lag falling Transition (3, 5, 20)
2381 00:43:07.775009 3 5 24 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 1)| 0
2382 00:43:07.781890 [Byte 0] Lead/lag Transition tap number (2)
2383 00:43:07.785133 [Byte 1] Lead/lag falling Transition (3, 5, 24)
2384 00:43:07.788481 3 5 28 |3d3d 3d3d |(11 11)(11 11) |(0 0)(1 0)| 0
2385 00:43:07.791958 3 6 0 |a0a 3d3d |(11 11)(11 11) |(0 0)(1 0)| 0
2386 00:43:07.798403 [Byte 1] Lead/lag Transition tap number (3)
2387 00:43:07.801913 3 6 4 |4646 e0e |(0 0)(11 11) |(0 0)(0 0)| 0
2388 00:43:07.805577 [Byte 0]First pass (3, 6, 4)
2389 00:43:07.808963 3 6 8 |4646 4646 |(0 0)(10 10) |(0 0)(0 0)| 0
2390 00:43:07.812212 3 6 12 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2391 00:43:07.815419 [Byte 1]First pass (3, 6, 12)
2392 00:43:07.818741 3 6 16 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2393 00:43:07.821948 3 6 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2394 00:43:07.825270 3 6 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2395 00:43:07.831948 3 6 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2396 00:43:07.835450 3 7 0 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2397 00:43:07.838948 3 7 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2398 00:43:07.842475 3 7 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2399 00:43:07.845830 3 7 12 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2400 00:43:07.852493 All bytes gating window > 1UI, Early break!
2401 00:43:07.852583
2402 00:43:07.855864 best DQS0 dly(2T, 0.5T, PI) = (3, 5, 24)
2403 00:43:07.855953
2404 00:43:07.859164 best DQS1 dly(2T, 0.5T, PI) = (3, 5, 30)
2405 00:43:07.859229
2406 00:43:07.859295
2407 00:43:07.859346
2408 00:43:07.862229 best DQS0 P1 dly(2T, 0.5T, PI) = (4, 1, 24)
2409 00:43:07.862291
2410 00:43:07.865572 best DQS1 P1 dly(2T, 0.5T, PI) = (4, 1, 30)
2411 00:43:07.865637
2412 00:43:07.865689
2413 00:43:07.869009 Write Rank0 MR1 =0x56
2414 00:43:07.869073
2415 00:43:07.872305 best RODT dly(2T, 0.5T) = (2, 2)
2416 00:43:07.872379
2417 00:43:07.875678 best RODT dly(2T, 0.5T) = (2, 2)
2418 00:43:07.875753 ==
2419 00:43:07.879187 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2420 00:43:07.882407 fsp= 1, odt_onoff= 1, Byte mode= 0
2421 00:43:07.882482 ==
2422 00:43:07.888996 Start DQ dly to find pass range UseTestEngine =0
2423 00:43:07.892429 x-axis: bit #, y-axis: DQ dly (-127~63)
2424 00:43:07.892506 RX Vref Scan = 0
2425 00:43:07.895612 -26, [0] xxxxxxxx xxxxxxxx [MSB]
2426 00:43:07.898971 -25, [0] xxxxxxxx xxxxxxxx [MSB]
2427 00:43:07.902542 -24, [0] xxxxxxxx xxxxxxxx [MSB]
2428 00:43:07.905547 -23, [0] xxxxxxxx xxxxxxxx [MSB]
2429 00:43:07.909067 -22, [0] xxxxxxxx xxxxxxxx [MSB]
2430 00:43:07.912211 -21, [0] xxxxxxxx xxxxxxxx [MSB]
2431 00:43:07.912271 -20, [0] xxxxxxxx xxxxxxxx [MSB]
2432 00:43:07.915840 -19, [0] xxxxxxxx xxxxxxxx [MSB]
2433 00:43:07.918893 -18, [0] xxxxxxxx xxxxxxxx [MSB]
2434 00:43:07.922293 -17, [0] xxxxxxxx xxxxxxxx [MSB]
2435 00:43:07.925571 -16, [0] xxxxxxxx xxxxxxxx [MSB]
2436 00:43:07.929033 -15, [0] xxxxxxxx xxxxxxxx [MSB]
2437 00:43:07.932488 -14, [0] xxxxxxxx xxxxxxxx [MSB]
2438 00:43:07.935703 -13, [0] xxxxxxxx xxxxxxxx [MSB]
2439 00:43:07.935773 -12, [0] xxxxxxxx xxxxxxxx [MSB]
2440 00:43:07.939018 -11, [0] xxxxxxxx xxxxxxxx [MSB]
2441 00:43:07.942389 -10, [0] xxxxxxxx xxxxxxxx [MSB]
2442 00:43:07.945710 -9, [0] xxxxxxxx xxxxxxxx [MSB]
2443 00:43:07.949107 -8, [0] xxxxxxxx xxxxxxxx [MSB]
2444 00:43:07.952447 -7, [0] xxxxxxxx xxxxxxxx [MSB]
2445 00:43:07.956021 -6, [0] xxxxxxxx xxxxxxxx [MSB]
2446 00:43:07.956091 -5, [0] xxxxxxxx xxxxxxxx [MSB]
2447 00:43:07.959195 -4, [0] xxxxxxxx xxxxxxxx [MSB]
2448 00:43:07.962880 -3, [0] xxxxxxxx xxxxxxxx [MSB]
2449 00:43:07.965900 -2, [0] xxxxxxxx xxxxxxxo [MSB]
2450 00:43:07.969352 -1, [0] xxxxxxxx xxxxxxxo [MSB]
2451 00:43:07.972462 0, [0] xxxoxxxx xxxxxxxo [MSB]
2452 00:43:07.972526 1, [0] xxooxxxx oxoxxxxo [MSB]
2453 00:43:07.975649 2, [0] xxooxxxo oxoxxxxo [MSB]
2454 00:43:07.979025 3, [0] xxoooxxo oooxxxxo [MSB]
2455 00:43:07.982520 4, [0] xxoooxxo ooooxooo [MSB]
2456 00:43:07.985885 5, [0] xooooxxo oooooooo [MSB]
2457 00:43:07.989287 6, [0] xooooxoo oooooooo [MSB]
2458 00:43:07.989388 31, [0] oooooooo oooooooo [MSB]
2459 00:43:07.992534 32, [0] oooxoooo oooooooo [MSB]
2460 00:43:07.995815 33, [0] ooxxoooo ooooooox [MSB]
2461 00:43:07.999495 34, [0] ooxxoooo oxooooox [MSB]
2462 00:43:08.002412 35, [0] ooxxoooo oxxxooox [MSB]
2463 00:43:08.006059 36, [0] ooxxoooo xxxxooxx [MSB]
2464 00:43:08.009179 37, [0] ooxxxoox xxxxoxxx [MSB]
2465 00:43:08.009245 38, [0] ooxxxoox xxxxoxxx [MSB]
2466 00:43:08.012657 39, [0] ooxxxoox xxxxxxxx [MSB]
2467 00:43:08.015870 40, [0] ooxxxoox xxxxxxxx [MSB]
2468 00:43:08.019077 41, [0] ooxxxoxx xxxxxxxx [MSB]
2469 00:43:08.022452 42, [0] xxxxxxxx xxxxxxxx [MSB]
2470 00:43:08.025641 iDelay=42, Bit 0, Center 24 (7 ~ 41) 35
2471 00:43:08.029015 iDelay=42, Bit 1, Center 23 (5 ~ 41) 37
2472 00:43:08.032858 iDelay=42, Bit 2, Center 16 (1 ~ 32) 32
2473 00:43:08.035892 iDelay=42, Bit 3, Center 15 (0 ~ 31) 32
2474 00:43:08.039394 iDelay=42, Bit 4, Center 19 (3 ~ 36) 34
2475 00:43:08.042306 iDelay=42, Bit 5, Center 24 (7 ~ 41) 35
2476 00:43:08.045728 iDelay=42, Bit 6, Center 23 (6 ~ 40) 35
2477 00:43:08.048800 iDelay=42, Bit 7, Center 19 (2 ~ 36) 35
2478 00:43:08.052387 iDelay=42, Bit 8, Center 18 (1 ~ 35) 35
2479 00:43:08.058987 iDelay=42, Bit 9, Center 18 (3 ~ 33) 31
2480 00:43:08.062333 iDelay=42, Bit 10, Center 17 (1 ~ 34) 34
2481 00:43:08.065687 iDelay=42, Bit 11, Center 19 (4 ~ 34) 31
2482 00:43:08.069042 iDelay=42, Bit 12, Center 21 (5 ~ 38) 34
2483 00:43:08.072307 iDelay=42, Bit 13, Center 20 (4 ~ 36) 33
2484 00:43:08.075736 iDelay=42, Bit 14, Center 19 (4 ~ 35) 32
2485 00:43:08.078940 iDelay=42, Bit 15, Center 15 (-2 ~ 32) 35
2486 00:43:08.079001 ==
2487 00:43:08.085727 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2488 00:43:08.089232 fsp= 1, odt_onoff= 1, Byte mode= 0
2489 00:43:08.089325 ==
2490 00:43:08.089407 DQS Delay:
2491 00:43:08.089492 DQS0 = 0, DQS1 = 0
2492 00:43:08.092434 DQM Delay:
2493 00:43:08.092499 DQM0 = 20, DQM1 = 18
2494 00:43:08.095920 DQ Delay:
2495 00:43:08.099134 DQ0 =24, DQ1 =23, DQ2 =16, DQ3 =15
2496 00:43:08.102446 DQ4 =19, DQ5 =24, DQ6 =23, DQ7 =19
2497 00:43:08.105869 DQ8 =18, DQ9 =18, DQ10 =17, DQ11 =19
2498 00:43:08.109120 DQ12 =21, DQ13 =20, DQ14 =19, DQ15 =15
2499 00:43:08.109184
2500 00:43:08.109236
2501 00:43:08.109286 DramC Write-DBI off
2502 00:43:08.109339 ==
2503 00:43:08.115717 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2504 00:43:08.119018 fsp= 1, odt_onoff= 1, Byte mode= 0
2505 00:43:08.119079 ==
2506 00:43:08.122292 [TxWindowPerbitCal] calType=2, VrefScanEnable 0
2507 00:43:08.122349
2508 00:43:08.125683 Begin, DQ Scan Range 929~1185
2509 00:43:08.125741
2510 00:43:08.125790
2511 00:43:08.129030 TX Vref Scan disable
2512 00:43:08.133026 929 |3 4 33|[0] xxxxxxxx xxxxxxxx [MSB]
2513 00:43:08.135746 930 |3 4 34|[0] xxxxxxxx xxxxxxxx [MSB]
2514 00:43:08.139054 931 |3 4 35|[0] xxxxxxxx xxxxxxxx [MSB]
2515 00:43:08.142467 932 |3 4 36|[0] xxxxxxxx xxxxxxxx [MSB]
2516 00:43:08.145925 933 |3 4 37|[0] xxxxxxxx xxxxxxxx [MSB]
2517 00:43:08.149146 934 |3 4 38|[0] xxxxxxxx xxxxxxxx [MSB]
2518 00:43:08.152383 935 |3 4 39|[0] xxxxxxxx xxxxxxxx [MSB]
2519 00:43:08.155783 936 |3 4 40|[0] xxxxxxxx xxxxxxxx [MSB]
2520 00:43:08.159294 937 |3 4 41|[0] xxxxxxxx xxxxxxxx [MSB]
2521 00:43:08.162705 938 |3 4 42|[0] xxxxxxxx xxxxxxxx [MSB]
2522 00:43:08.165754 939 |3 4 43|[0] xxxxxxxx xxxxxxxx [MSB]
2523 00:43:08.169287 940 |3 4 44|[0] xxxxxxxx xxxxxxxx [MSB]
2524 00:43:08.172490 941 |3 4 45|[0] xxxxxxxx xxxxxxxx [MSB]
2525 00:43:08.176081 942 |3 4 46|[0] xxxxxxxx xxxxxxxx [MSB]
2526 00:43:08.179424 943 |3 4 47|[0] xxxxxxxx xxxxxxxx [MSB]
2527 00:43:08.185828 944 |3 4 48|[0] xxxxxxxx xxxxxxxx [MSB]
2528 00:43:08.189304 945 |3 4 49|[0] xxxxxxxx xxxxxxxx [MSB]
2529 00:43:08.192399 946 |3 4 50|[0] xxxxxxxx xxxxxxxx [MSB]
2530 00:43:08.195734 947 |3 4 51|[0] xxxxxxxx xxxxxxxx [MSB]
2531 00:43:08.199253 948 |3 4 52|[0] xxxxxxxx xxxxxxxx [MSB]
2532 00:43:08.202667 949 |3 4 53|[0] xxxxxxxx xxxxxxxx [MSB]
2533 00:43:08.206033 950 |3 4 54|[0] xxxxxxxx xxxxxxxx [MSB]
2534 00:43:08.209222 951 |3 4 55|[0] xxxxxxxx xxxxxxxx [MSB]
2535 00:43:08.212764 952 |3 4 56|[0] xxxxxxxx xxxxxxxx [MSB]
2536 00:43:08.215911 953 |3 4 57|[0] xxxxxxxx xxxxxxxx [MSB]
2537 00:43:08.219231 954 |3 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
2538 00:43:08.222542 955 |3 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
2539 00:43:08.225989 956 |3 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
2540 00:43:08.229270 957 |3 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
2541 00:43:08.232993 958 |3 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
2542 00:43:08.235975 959 |3 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
2543 00:43:08.239315 960 |3 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
2544 00:43:08.242962 961 |3 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
2545 00:43:08.246064 962 |3 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
2546 00:43:08.249527 963 |3 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
2547 00:43:08.255849 964 |3 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
2548 00:43:08.259360 965 |3 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
2549 00:43:08.262864 966 |3 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
2550 00:43:08.266227 967 |3 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
2551 00:43:08.269437 968 |3 6 8|[0] xxxxxxxx xxxxxxxx [MSB]
2552 00:43:08.272888 969 |3 6 9|[0] xxxxxxxx xxxxxxxo [MSB]
2553 00:43:08.275955 970 |3 6 10|[0] xxxxxxxx ooxxxxxo [MSB]
2554 00:43:08.279630 971 |3 6 11|[0] xxxxxxxx oooxxxoo [MSB]
2555 00:43:08.282986 972 |3 6 12|[0] xxxxxxxx oooooxoo [MSB]
2556 00:43:08.286186 973 |3 6 13|[0] xxxoxxxx oooooooo [MSB]
2557 00:43:08.289586 974 |3 6 14|[0] xxxoxxxx oooooooo [MSB]
2558 00:43:08.292923 975 |3 6 15|[0] xxooxxxx oooooooo [MSB]
2559 00:43:08.296208 976 |3 6 16|[0] xxoooxxo oooooooo [MSB]
2560 00:43:08.303793 992 |3 6 32|[0] oooooooo xxxxxxxx [MSB]
2561 00:43:08.307256 993 |3 6 33|[0] oooooooo xxxxxxxx [MSB]
2562 00:43:08.310795 994 |3 6 34|[0] oooxoooo xxxxxxxx [MSB]
2563 00:43:08.313969 995 |3 6 35|[0] ooxxoooo xxxxxxxx [MSB]
2564 00:43:08.317248 996 |3 6 36|[0] ooxxoooo xxxxxxxx [MSB]
2565 00:43:08.320659 997 |3 6 37|[0] ooxxoooo xxxxxxxx [MSB]
2566 00:43:08.324080 998 |3 6 38|[0] ooxxxoox xxxxxxxx [MSB]
2567 00:43:08.327425 999 |3 6 39|[0] oxxxxxxx xxxxxxxx [MSB]
2568 00:43:08.330726 1000 |3 6 40|[0] xxxxxxxx xxxxxxxx [MSB]
2569 00:43:08.334049 Byte0, DQ PI dly=985, DQM PI dly= 985
2570 00:43:08.337569 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 25)
2571 00:43:08.337639
2572 00:43:08.343967 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 25)
2573 00:43:08.344037
2574 00:43:08.347538 Byte1, DQ PI dly=981, DQM PI dly= 981
2575 00:43:08.350899 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 21)
2576 00:43:08.350966
2577 00:43:08.354136 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 21)
2578 00:43:08.354244
2579 00:43:08.354306 ==
2580 00:43:08.360916 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2581 00:43:08.364476 fsp= 1, odt_onoff= 1, Byte mode= 0
2582 00:43:08.364551 ==
2583 00:43:08.367366 [TxWindowPerbitCal] calType=0, VrefScanEnable 1
2584 00:43:08.367441
2585 00:43:08.371049 Begin, DQ Scan Range 957~1021
2586 00:43:08.374156 Write Rank0 MR14 =0x0
2587 00:43:08.381160
2588 00:43:08.381235 CH=1, VrefRange= 0, VrefLevel = 0
2589 00:43:08.387953 TX Bit0 (980~997) 18 988, Bit8 (971~990) 20 980,
2590 00:43:08.391192 TX Bit1 (978~995) 18 986, Bit9 (971~989) 19 980,
2591 00:43:08.398003 TX Bit2 (977~990) 14 983, Bit10 (974~989) 16 981,
2592 00:43:08.401396 TX Bit3 (975~990) 16 982, Bit11 (975~991) 17 983,
2593 00:43:08.404612 TX Bit4 (977~992) 16 984, Bit12 (975~992) 18 983,
2594 00:43:08.411428 TX Bit5 (979~997) 19 988, Bit13 (976~990) 15 983,
2595 00:43:08.414774 TX Bit6 (979~997) 19 988, Bit14 (975~989) 15 982,
2596 00:43:08.418018 TX Bit7 (978~992) 15 985, Bit15 (970~987) 18 978,
2597 00:43:08.418084
2598 00:43:08.421026 Write Rank0 MR14 =0x2
2599 00:43:08.429485
2600 00:43:08.429554 CH=1, VrefRange= 0, VrefLevel = 2
2601 00:43:08.436441 TX Bit0 (980~998) 19 989, Bit8 (971~991) 21 981,
2602 00:43:08.439564 TX Bit1 (978~996) 19 987, Bit9 (971~989) 19 980,
2603 00:43:08.446277 TX Bit2 (976~991) 16 983, Bit10 (975~989) 15 982,
2604 00:43:08.449417 TX Bit3 (975~990) 16 982, Bit11 (974~991) 18 982,
2605 00:43:08.452946 TX Bit4 (977~993) 17 985, Bit12 (975~992) 18 983,
2606 00:43:08.459618 TX Bit5 (978~998) 21 988, Bit13 (976~991) 16 983,
2607 00:43:08.462862 TX Bit6 (980~998) 19 989, Bit14 (975~990) 16 982,
2608 00:43:08.466321 TX Bit7 (977~992) 16 984, Bit15 (970~988) 19 979,
2609 00:43:08.466383
2610 00:43:08.469606 Write Rank0 MR14 =0x4
2611 00:43:08.477915
2612 00:43:08.477979 CH=1, VrefRange= 0, VrefLevel = 4
2613 00:43:08.484751 TX Bit0 (979~998) 20 988, Bit8 (971~991) 21 981,
2614 00:43:08.488066 TX Bit1 (978~997) 20 987, Bit9 (971~990) 20 980,
2615 00:43:08.491448 TX Bit2 (976~991) 16 983, Bit10 (973~991) 19 982,
2616 00:43:08.498282 TX Bit3 (975~991) 17 983, Bit11 (974~992) 19 983,
2617 00:43:08.501618 TX Bit4 (977~993) 17 985, Bit12 (975~992) 18 983,
2618 00:43:08.508211 TX Bit5 (978~998) 21 988, Bit13 (975~991) 17 983,
2619 00:43:08.511580 TX Bit6 (978~998) 21 988, Bit14 (974~991) 18 982,
2620 00:43:08.515124 TX Bit7 (977~992) 16 984, Bit15 (970~988) 19 979,
2621 00:43:08.515186
2622 00:43:08.518031 Write Rank0 MR14 =0x6
2623 00:43:08.526471
2624 00:43:08.526537 CH=1, VrefRange= 0, VrefLevel = 6
2625 00:43:08.532969 TX Bit0 (979~998) 20 988, Bit8 (970~991) 22 980,
2626 00:43:08.536354 TX Bit1 (977~997) 21 987, Bit9 (971~991) 21 981,
2627 00:43:08.543047 TX Bit2 (976~992) 17 984, Bit10 (972~991) 20 981,
2628 00:43:08.546429 TX Bit3 (975~991) 17 983, Bit11 (973~991) 19 982,
2629 00:43:08.549663 TX Bit4 (976~994) 19 985, Bit12 (974~992) 19 983,
2630 00:43:08.556333 TX Bit5 (978~998) 21 988, Bit13 (975~992) 18 983,
2631 00:43:08.559715 TX Bit6 (978~998) 21 988, Bit14 (973~991) 19 982,
2632 00:43:08.562928 TX Bit7 (977~993) 17 985, Bit15 (970~989) 20 979,
2633 00:43:08.562989
2634 00:43:08.566255 Write Rank0 MR14 =0x8
2635 00:43:08.574587
2636 00:43:08.574656 CH=1, VrefRange= 0, VrefLevel = 8
2637 00:43:08.581388 TX Bit0 (978~998) 21 988, Bit8 (970~991) 22 980,
2638 00:43:08.584702 TX Bit1 (977~997) 21 987, Bit9 (970~991) 22 980,
2639 00:43:08.591435 TX Bit2 (976~992) 17 984, Bit10 (973~991) 19 982,
2640 00:43:08.594861 TX Bit3 (974~991) 18 982, Bit11 (973~992) 20 982,
2641 00:43:08.598185 TX Bit4 (976~995) 20 985, Bit12 (973~993) 21 983,
2642 00:43:08.604878 TX Bit5 (978~998) 21 988, Bit13 (975~992) 18 983,
2643 00:43:08.608320 TX Bit6 (978~998) 21 988, Bit14 (973~991) 19 982,
2644 00:43:08.611575 TX Bit7 (977~993) 17 985, Bit15 (969~989) 21 979,
2645 00:43:08.611639
2646 00:43:08.615059 Write Rank0 MR14 =0xa
2647 00:43:08.623187
2648 00:43:08.626530 CH=1, VrefRange= 0, VrefLevel = 10
2649 00:43:08.629821 TX Bit0 (979~998) 20 988, Bit8 (970~992) 23 981,
2650 00:43:08.633104 TX Bit1 (977~997) 21 987, Bit9 (970~991) 22 980,
2651 00:43:08.639740 TX Bit2 (976~992) 17 984, Bit10 (971~992) 22 981,
2652 00:43:08.643102 TX Bit3 (974~992) 19 983, Bit11 (973~992) 20 982,
2653 00:43:08.646458 TX Bit4 (976~996) 21 986, Bit12 (973~993) 21 983,
2654 00:43:08.653226 TX Bit5 (977~998) 22 987, Bit13 (974~992) 19 983,
2655 00:43:08.656972 TX Bit6 (978~998) 21 988, Bit14 (972~992) 21 982,
2656 00:43:08.660205 TX Bit7 (977~994) 18 985, Bit15 (969~990) 22 979,
2657 00:43:08.660267
2658 00:43:08.663420 Write Rank0 MR14 =0xc
2659 00:43:08.671939
2660 00:43:08.672004 CH=1, VrefRange= 0, VrefLevel = 12
2661 00:43:08.678802 TX Bit0 (978~999) 22 988, Bit8 (970~992) 23 981,
2662 00:43:08.681876 TX Bit1 (977~998) 22 987, Bit9 (970~991) 22 980,
2663 00:43:08.688543 TX Bit2 (975~993) 19 984, Bit10 (971~992) 22 981,
2664 00:43:08.691937 TX Bit3 (973~992) 20 982, Bit11 (972~993) 22 982,
2665 00:43:08.695443 TX Bit4 (976~996) 21 986, Bit12 (973~993) 21 983,
2666 00:43:08.702120 TX Bit5 (978~998) 21 988, Bit13 (973~992) 20 982,
2667 00:43:08.705168 TX Bit6 (977~999) 23 988, Bit14 (972~992) 21 982,
2668 00:43:08.708424 TX Bit7 (977~995) 19 986, Bit15 (969~991) 23 980,
2669 00:43:08.708493
2670 00:43:08.712133 Write Rank0 MR14 =0xe
2671 00:43:08.720423
2672 00:43:08.724167 CH=1, VrefRange= 0, VrefLevel = 14
2673 00:43:08.727283 TX Bit0 (978~999) 22 988, Bit8 (970~992) 23 981,
2674 00:43:08.730645 TX Bit1 (977~998) 22 987, Bit9 (969~992) 24 980,
2675 00:43:08.736924 TX Bit2 (975~993) 19 984, Bit10 (971~992) 22 981,
2676 00:43:08.740463 TX Bit3 (973~993) 21 983, Bit11 (972~993) 22 982,
2677 00:43:08.743929 TX Bit4 (976~997) 22 986, Bit12 (972~993) 22 982,
2678 00:43:08.750453 TX Bit5 (977~999) 23 988, Bit13 (973~993) 21 983,
2679 00:43:08.753890 TX Bit6 (977~999) 23 988, Bit14 (972~992) 21 982,
2680 00:43:08.757166 TX Bit7 (977~996) 20 986, Bit15 (969~991) 23 980,
2681 00:43:08.757230
2682 00:43:08.760500 Write Rank0 MR14 =0x10
2683 00:43:08.769221
2684 00:43:08.772299 CH=1, VrefRange= 0, VrefLevel = 16
2685 00:43:08.775699 TX Bit0 (977~999) 23 988, Bit8 (970~992) 23 981,
2686 00:43:08.779166 TX Bit1 (977~998) 22 987, Bit9 (970~992) 23 981,
2687 00:43:08.786171 TX Bit2 (975~994) 20 984, Bit10 (970~992) 23 981,
2688 00:43:08.789207 TX Bit3 (973~993) 21 983, Bit11 (971~993) 23 982,
2689 00:43:08.792545 TX Bit4 (975~997) 23 986, Bit12 (972~994) 23 983,
2690 00:43:08.799191 TX Bit5 (977~999) 23 988, Bit13 (973~993) 21 983,
2691 00:43:08.802436 TX Bit6 (977~999) 23 988, Bit14 (971~992) 22 981,
2692 00:43:08.805818 TX Bit7 (976~997) 22 986, Bit15 (968~991) 24 979,
2693 00:43:08.805883
2694 00:43:08.809088 Write Rank0 MR14 =0x12
2695 00:43:08.818064
2696 00:43:08.821557 CH=1, VrefRange= 0, VrefLevel = 18
2697 00:43:08.824826 TX Bit0 (977~1000) 24 988, Bit8 (970~993) 24 981,
2698 00:43:08.827953 TX Bit1 (976~998) 23 987, Bit9 (970~992) 23 981,
2699 00:43:08.834789 TX Bit2 (975~995) 21 985, Bit10 (970~993) 24 981,
2700 00:43:08.838100 TX Bit3 (973~994) 22 983, Bit11 (971~994) 24 982,
2701 00:43:08.841260 TX Bit4 (976~997) 22 986, Bit12 (972~994) 23 983,
2702 00:43:08.848054 TX Bit5 (977~999) 23 988, Bit13 (972~993) 22 982,
2703 00:43:08.851254 TX Bit6 (977~1000) 24 988, Bit14 (971~993) 23 982,
2704 00:43:08.854761 TX Bit7 (976~997) 22 986, Bit15 (968~992) 25 980,
2705 00:43:08.857868
2706 00:43:08.857937 Write Rank0 MR14 =0x14
2707 00:43:08.866995
2708 00:43:08.870671 CH=1, VrefRange= 0, VrefLevel = 20
2709 00:43:08.873829 TX Bit0 (977~1000) 24 988, Bit8 (969~993) 25 981,
2710 00:43:08.877348 TX Bit1 (976~998) 23 987, Bit9 (969~992) 24 980,
2711 00:43:08.884146 TX Bit2 (974~995) 22 984, Bit10 (970~993) 24 981,
2712 00:43:08.887379 TX Bit3 (972~994) 23 983, Bit11 (971~994) 24 982,
2713 00:43:08.890849 TX Bit4 (975~998) 24 986, Bit12 (972~994) 23 983,
2714 00:43:08.897327 TX Bit5 (977~1000) 24 988, Bit13 (972~993) 22 982,
2715 00:43:08.900598 TX Bit6 (977~1000) 24 988, Bit14 (971~993) 23 982,
2716 00:43:08.904146 TX Bit7 (976~997) 22 986, Bit15 (968~991) 24 979,
2717 00:43:08.904215
2718 00:43:08.907292 Write Rank0 MR14 =0x16
2719 00:43:08.916326
2720 00:43:08.919637 CH=1, VrefRange= 0, VrefLevel = 22
2721 00:43:08.922844 TX Bit0 (977~1000) 24 988, Bit8 (969~992) 24 980,
2722 00:43:08.926435 TX Bit1 (976~999) 24 987, Bit9 (970~992) 23 981,
2723 00:43:08.933291 TX Bit2 (974~996) 23 985, Bit10 (971~993) 23 982,
2724 00:43:08.936493 TX Bit3 (971~995) 25 983, Bit11 (971~994) 24 982,
2725 00:43:08.939787 TX Bit4 (975~998) 24 986, Bit12 (971~994) 24 982,
2726 00:43:08.946313 TX Bit5 (976~999) 24 987, Bit13 (971~993) 23 982,
2727 00:43:08.949549 TX Bit6 (977~1000) 24 988, Bit14 (970~993) 24 981,
2728 00:43:08.952955 TX Bit7 (976~998) 23 987, Bit15 (968~992) 25 980,
2729 00:43:08.953025
2730 00:43:08.956308 Write Rank0 MR14 =0x18
2731 00:43:08.965421
2732 00:43:08.968811 CH=1, VrefRange= 0, VrefLevel = 24
2733 00:43:08.972266 TX Bit0 (977~1001) 25 989, Bit8 (969~992) 24 980,
2734 00:43:08.975748 TX Bit1 (976~999) 24 987, Bit9 (969~992) 24 980,
2735 00:43:08.982139 TX Bit2 (974~997) 24 985, Bit10 (969~994) 26 981,
2736 00:43:08.985570 TX Bit3 (971~995) 25 983, Bit11 (971~994) 24 982,
2737 00:43:08.989089 TX Bit4 (975~998) 24 986, Bit12 (971~995) 25 983,
2738 00:43:08.995637 TX Bit5 (976~999) 24 987, Bit13 (971~994) 24 982,
2739 00:43:08.998810 TX Bit6 (977~1000) 24 988, Bit14 (970~993) 24 981,
2740 00:43:09.002299 TX Bit7 (975~998) 24 986, Bit15 (968~992) 25 980,
2741 00:43:09.002361
2742 00:43:09.005638 Write Rank0 MR14 =0x1a
2743 00:43:09.014577
2744 00:43:09.018207 CH=1, VrefRange= 0, VrefLevel = 26
2745 00:43:09.021296 TX Bit0 (977~1001) 25 989, Bit8 (969~992) 24 980,
2746 00:43:09.024586 TX Bit1 (976~999) 24 987, Bit9 (969~992) 24 980,
2747 00:43:09.031316 TX Bit2 (974~997) 24 985, Bit10 (969~994) 26 981,
2748 00:43:09.034821 TX Bit3 (971~995) 25 983, Bit11 (971~994) 24 982,
2749 00:43:09.038120 TX Bit4 (975~998) 24 986, Bit12 (971~995) 25 983,
2750 00:43:09.044871 TX Bit5 (976~999) 24 987, Bit13 (971~994) 24 982,
2751 00:43:09.047892 TX Bit6 (977~1000) 24 988, Bit14 (970~993) 24 981,
2752 00:43:09.051308 TX Bit7 (975~998) 24 986, Bit15 (968~992) 25 980,
2753 00:43:09.054530
2754 00:43:09.054594 Write Rank0 MR14 =0x1c
2755 00:43:09.064167
2756 00:43:09.067527 CH=1, VrefRange= 0, VrefLevel = 28
2757 00:43:09.070434 TX Bit0 (977~1001) 25 989, Bit8 (969~992) 24 980,
2758 00:43:09.073723 TX Bit1 (976~999) 24 987, Bit9 (969~992) 24 980,
2759 00:43:09.080761 TX Bit2 (974~997) 24 985, Bit10 (969~994) 26 981,
2760 00:43:09.084065 TX Bit3 (971~995) 25 983, Bit11 (971~994) 24 982,
2761 00:43:09.087324 TX Bit4 (975~998) 24 986, Bit12 (971~995) 25 983,
2762 00:43:09.093894 TX Bit5 (976~999) 24 987, Bit13 (971~994) 24 982,
2763 00:43:09.097377 TX Bit6 (977~1000) 24 988, Bit14 (970~993) 24 981,
2764 00:43:09.100835 TX Bit7 (975~998) 24 986, Bit15 (968~992) 25 980,
2765 00:43:09.104016
2766 00:43:09.104079 Write Rank0 MR14 =0x1e
2767 00:43:09.112907
2768 00:43:09.116278 CH=1, VrefRange= 0, VrefLevel = 30
2769 00:43:09.119920 TX Bit0 (977~1001) 25 989, Bit8 (969~992) 24 980,
2770 00:43:09.123141 TX Bit1 (976~999) 24 987, Bit9 (969~992) 24 980,
2771 00:43:09.129588 TX Bit2 (974~997) 24 985, Bit10 (969~994) 26 981,
2772 00:43:09.132945 TX Bit3 (971~995) 25 983, Bit11 (971~994) 24 982,
2773 00:43:09.136187 TX Bit4 (975~998) 24 986, Bit12 (971~995) 25 983,
2774 00:43:09.142977 TX Bit5 (976~999) 24 987, Bit13 (971~994) 24 982,
2775 00:43:09.146306 TX Bit6 (977~1000) 24 988, Bit14 (970~993) 24 981,
2776 00:43:09.149706 TX Bit7 (975~998) 24 986, Bit15 (968~992) 25 980,
2777 00:43:09.152805
2778 00:43:09.152872 Write Rank0 MR14 =0x20
2779 00:43:09.162254
2780 00:43:09.165232 CH=1, VrefRange= 0, VrefLevel = 32
2781 00:43:09.168611 TX Bit0 (977~1001) 25 989, Bit8 (969~992) 24 980,
2782 00:43:09.172121 TX Bit1 (976~999) 24 987, Bit9 (969~992) 24 980,
2783 00:43:09.178738 TX Bit2 (974~997) 24 985, Bit10 (969~994) 26 981,
2784 00:43:09.182031 TX Bit3 (971~995) 25 983, Bit11 (971~994) 24 982,
2785 00:43:09.185588 TX Bit4 (975~998) 24 986, Bit12 (971~995) 25 983,
2786 00:43:09.192006 TX Bit5 (976~999) 24 987, Bit13 (971~994) 24 982,
2787 00:43:09.195319 TX Bit6 (977~1000) 24 988, Bit14 (970~993) 24 981,
2788 00:43:09.198971 TX Bit7 (975~998) 24 986, Bit15 (968~992) 25 980,
2789 00:43:09.199042
2790 00:43:09.201947 Write Rank0 MR14 =0x22
2791 00:43:09.211077
2792 00:43:09.214523 CH=1, VrefRange= 0, VrefLevel = 34
2793 00:43:09.218054 TX Bit0 (977~1001) 25 989, Bit8 (969~992) 24 980,
2794 00:43:09.221204 TX Bit1 (976~999) 24 987, Bit9 (969~992) 24 980,
2795 00:43:09.227846 TX Bit2 (974~997) 24 985, Bit10 (969~994) 26 981,
2796 00:43:09.231201 TX Bit3 (971~995) 25 983, Bit11 (971~994) 24 982,
2797 00:43:09.234484 TX Bit4 (975~998) 24 986, Bit12 (971~995) 25 983,
2798 00:43:09.241112 TX Bit5 (976~999) 24 987, Bit13 (971~994) 24 982,
2799 00:43:09.244586 TX Bit6 (977~1000) 24 988, Bit14 (970~993) 24 981,
2800 00:43:09.247972 TX Bit7 (975~998) 24 986, Bit15 (968~992) 25 980,
2801 00:43:09.248033
2802 00:43:09.251180
2803 00:43:09.251239 TX Vref found, early break! 357< 370
2804 00:43:09.258074 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =753/100 ps
2805 00:43:09.261447 u1DelayCellOfst[0]=7 cells (6 PI)
2806 00:43:09.264705 u1DelayCellOfst[1]=5 cells (4 PI)
2807 00:43:09.267914 u1DelayCellOfst[2]=2 cells (2 PI)
2808 00:43:09.271448 u1DelayCellOfst[3]=0 cells (0 PI)
2809 00:43:09.271509 u1DelayCellOfst[4]=3 cells (3 PI)
2810 00:43:09.274514 u1DelayCellOfst[5]=5 cells (4 PI)
2811 00:43:09.277879 u1DelayCellOfst[6]=6 cells (5 PI)
2812 00:43:09.281497 u1DelayCellOfst[7]=3 cells (3 PI)
2813 00:43:09.284836 Byte0, DQ PI dly=983, DQM PI dly= 986
2814 00:43:09.288021 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 23)
2815 00:43:09.291841
2816 00:43:09.294613 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 23)
2817 00:43:09.294682
2818 00:43:09.298040 u1DelayCellOfst[8]=0 cells (0 PI)
2819 00:43:09.301414 u1DelayCellOfst[9]=0 cells (0 PI)
2820 00:43:09.304983 u1DelayCellOfst[10]=1 cells (1 PI)
2821 00:43:09.305047 u1DelayCellOfst[11]=2 cells (2 PI)
2822 00:43:09.308127 u1DelayCellOfst[12]=3 cells (3 PI)
2823 00:43:09.311460 u1DelayCellOfst[13]=2 cells (2 PI)
2824 00:43:09.314737 u1DelayCellOfst[14]=1 cells (1 PI)
2825 00:43:09.318379 u1DelayCellOfst[15]=0 cells (0 PI)
2826 00:43:09.321608 Byte1, DQ PI dly=980, DQM PI dly= 981
2827 00:43:09.328238 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 20)
2828 00:43:09.328317
2829 00:43:09.331764 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 20)
2830 00:43:09.331840
2831 00:43:09.331899 Write Rank0 MR14 =0x18
2832 00:43:09.334908
2833 00:43:09.334983 Final TX Range 0 Vref 24
2834 00:43:09.335040
2835 00:43:09.341851 [TX_K_DQM_WITH_WDBI] Step1: K DQM with DBI_ON, and check DQM window spec.
2836 00:43:09.341926
2837 00:43:09.348764 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
2838 00:43:09.354980 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
2839 00:43:09.361823 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
2840 00:43:09.364985 Write Rank0 MR3 =0xb0
2841 00:43:09.365059 DramC Write-DBI on
2842 00:43:09.368316 ==
2843 00:43:09.371851 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2844 00:43:09.375166 fsp= 1, odt_onoff= 1, Byte mode= 0
2845 00:43:09.375241 ==
2846 00:43:09.378352 [TxWindowPerbitCal] calType=1, VrefScanEnable 0
2847 00:43:09.378427
2848 00:43:09.381908 Begin, DQ Scan Range 701~765
2849 00:43:09.381983
2850 00:43:09.382041
2851 00:43:09.385063 TX Vref Scan disable
2852 00:43:09.388750 701 |2 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
2853 00:43:09.391951 702 |2 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
2854 00:43:09.395154 703 |2 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
2855 00:43:09.398555 704 |2 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
2856 00:43:09.401731 705 |2 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
2857 00:43:09.405200 706 |2 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
2858 00:43:09.408538 707 |2 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
2859 00:43:09.412058 708 |2 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
2860 00:43:09.415269 709 |2 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
2861 00:43:09.418576 710 |2 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
2862 00:43:09.421772 711 |2 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
2863 00:43:09.425140 712 |2 6 8|[0] xxxxxxxx oooooooo [MSB]
2864 00:43:09.428644 713 |2 6 9|[0] xxxxxxxx oooooooo [MSB]
2865 00:43:09.432041 714 |2 6 10|[0] xxxxxxxx oooooooo [MSB]
2866 00:43:09.435398 715 |2 6 11|[0] xxxxxxxx oooooooo [MSB]
2867 00:43:09.438743 716 |2 6 12|[0] xxxxxxxx oooooooo [MSB]
2868 00:43:09.445459 717 |2 6 13|[0] xxxxxxxx oooooooo [MSB]
2869 00:43:09.448874 737 |2 6 33|[0] oooooooo xxxxxxxx [MSB]
2870 00:43:09.455520 738 |2 6 34|[0] oooooooo xxxxxxxx [MSB]
2871 00:43:09.458832 739 |2 6 35|[0] oooooooo xxxxxxxx [MSB]
2872 00:43:09.462048 740 |2 6 36|[0] oooooooo xxxxxxxx [MSB]
2873 00:43:09.465540 741 |2 6 37|[0] oooooooo xxxxxxxx [MSB]
2874 00:43:09.468687 742 |2 6 38|[0] oooooooo xxxxxxxx [MSB]
2875 00:43:09.472323 743 |2 6 39|[0] oooooooo xxxxxxxx [MSB]
2876 00:43:09.475330 744 |2 6 40|[0] xxxxxxxx xxxxxxxx [MSB]
2877 00:43:09.478782 Byte0, DQ PI dly=730, DQM PI dly= 730
2878 00:43:09.482464 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 26)
2879 00:43:09.482541
2880 00:43:09.488998 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 26)
2881 00:43:09.489074
2882 00:43:09.492269 Byte1, DQ PI dly=724, DQM PI dly= 724
2883 00:43:09.495542 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 20)
2884 00:43:09.495613
2885 00:43:09.499124 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 20)
2886 00:43:09.499196
2887 00:43:09.505626 Before -1MCK, ucdq_final_ui_large_dqs0 = 2, ucdq_final_ui_large_dqs1 = 2
2888 00:43:09.512327 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
2889 00:43:09.518965 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
2890 00:43:09.522353 Write Rank0 MR3 =0x30
2891 00:43:09.522421 DramC Write-DBI off
2892 00:43:09.525645
2893 00:43:09.525709 [DATLAT]
2894 00:43:09.529540 Freq=1600, CH1 RK0, use_rxtx_scan=0
2895 00:43:09.529622
2896 00:43:09.529713 DATLAT Default: 0xf
2897 00:43:09.532529 7, 0xFFFF, sum=0
2898 00:43:09.532595 8, 0xFFFF, sum=0
2899 00:43:09.535799 9, 0xFFFF, sum=0
2900 00:43:09.535863 10, 0xFFFF, sum=0
2901 00:43:09.538921 11, 0xFFFF, sum=0
2902 00:43:09.538991 12, 0xFFFF, sum=0
2903 00:43:09.542223 13, 0xFFFF, sum=0
2904 00:43:09.542321 14, 0x0, sum=1
2905 00:43:09.545652 15, 0x0, sum=2
2906 00:43:09.545715 16, 0x0, sum=3
2907 00:43:09.545772 17, 0x0, sum=4
2908 00:43:09.552613 pattern=2 first_step=14 total pass=5 best_step=16
2909 00:43:09.552680 ==
2910 00:43:09.555842 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2911 00:43:09.558961 fsp= 1, odt_onoff= 1, Byte mode= 0
2912 00:43:09.559028 ==
2913 00:43:09.565772 Start DQ dly to find pass range UseTestEngine =1
2914 00:43:09.568920 x-axis: bit #, y-axis: DQ dly (-127~63)
2915 00:43:09.569000 RX Vref Scan = 1
2916 00:43:09.684436
2917 00:43:09.684525 RX Vref found, early break!
2918 00:43:09.684585
2919 00:43:09.691079 Final RX Vref 12, apply to both rank0 and 1
2920 00:43:09.691177 ==
2921 00:43:09.694176 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2922 00:43:09.697849 fsp= 1, odt_onoff= 1, Byte mode= 0
2923 00:43:09.697916 ==
2924 00:43:09.697973 DQS Delay:
2925 00:43:09.700843 DQS0 = 0, DQS1 = 0
2926 00:43:09.700908 DQM Delay:
2927 00:43:09.704297 DQM0 = 20, DQM1 = 18
2928 00:43:09.704363 DQ Delay:
2929 00:43:09.707703 DQ0 =24, DQ1 =23, DQ2 =17, DQ3 =14
2930 00:43:09.710889 DQ4 =19, DQ5 =24, DQ6 =24, DQ7 =19
2931 00:43:09.714315 DQ8 =18, DQ9 =17, DQ10 =18, DQ11 =19
2932 00:43:09.717751 DQ12 =21, DQ13 =19, DQ14 =20, DQ15 =15
2933 00:43:09.717814
2934 00:43:09.717868
2935 00:43:09.717919
2936 00:43:09.720982 [DramC_TX_OE_Calibration] TA2
2937 00:43:09.724400 Original DQ_B0 (3 6) =30, OEN = 27
2938 00:43:09.727580 Original DQ_B1 (3 6) =30, OEN = 27
2939 00:43:09.730888 23, 0x0, End_B0=23 End_B1=23
2940 00:43:09.730955 24, 0x0, End_B0=24 End_B1=24
2941 00:43:09.734311 25, 0x0, End_B0=25 End_B1=25
2942 00:43:09.737707 26, 0x0, End_B0=26 End_B1=26
2943 00:43:09.741238 27, 0x0, End_B0=27 End_B1=27
2944 00:43:09.741302 28, 0x0, End_B0=28 End_B1=28
2945 00:43:09.744240 29, 0x0, End_B0=29 End_B1=29
2946 00:43:09.747686 30, 0x0, End_B0=30 End_B1=30
2947 00:43:09.750957 31, 0xFFFF, End_B0=30 End_B1=30
2948 00:43:09.757827 Byte0 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
2949 00:43:09.760931 Byte1 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
2950 00:43:09.760997
2951 00:43:09.761051
2952 00:43:09.764469 Write Rank0 MR23 =0x3f
2953 00:43:09.764535 [DQSOSC]
2954 00:43:09.770888 [DQSOSCAuto] RK0, (LSB)MR18= 0xa3, (MSB)MR19= 0x3, tDQSOscB0 = 338 ps tDQSOscB1 = 0 ps
2955 00:43:09.777828 CH1_RK0: MR19=0x3, MR18=0xA3, DQSOSC=338, MR23=63, INC=21, DEC=32
2956 00:43:09.781146 Write Rank0 MR23 =0x3f
2957 00:43:09.781212 [DQSOSC]
2958 00:43:09.787610 [DQSOSCAuto] RK0, (LSB)MR18= 0xa0, (MSB)MR19= 0x3, tDQSOscB0 = 339 ps tDQSOscB1 = 0 ps
2959 00:43:09.790927 CH1 RK0: MR19=3, MR18=A0
2960 00:43:09.794434 [RankSwap] Rank num 2, (Multi 1), Rank 1
2961 00:43:09.797905 Write Rank0 MR2 =0xad
2962 00:43:09.797972 [Write Leveling]
2963 00:43:09.801069 delay byte0 byte1 byte2 byte3
2964 00:43:09.801137
2965 00:43:09.801193 10 0 0
2966 00:43:09.804587 11 0 0
2967 00:43:09.804652 12 0 0
2968 00:43:09.807928 13 0 0
2969 00:43:09.807992 14 0 0
2970 00:43:09.811111 15 0 0
2971 00:43:09.811177 16 0 0
2972 00:43:09.811231 17 0 0
2973 00:43:09.814518 18 0 0
2974 00:43:09.814584 19 0 0
2975 00:43:09.817672 20 0 0
2976 00:43:09.817734 21 0 0
2977 00:43:09.817786 22 0 0
2978 00:43:09.820971 23 0 0
2979 00:43:09.821031 24 0 0
2980 00:43:09.824362 25 0 0
2981 00:43:09.824424 26 0 0
2982 00:43:09.824476 27 0 0
2983 00:43:09.827943 28 0 0
2984 00:43:09.828005 29 0 0
2985 00:43:09.831522 30 0 0
2986 00:43:09.831604 31 0 ff
2987 00:43:09.834581 32 0 ff
2988 00:43:09.834644 33 0 ff
2989 00:43:09.834696 34 0 ff
2990 00:43:09.837952 35 0 ff
2991 00:43:09.838015 36 0 ff
2992 00:43:09.841353 37 ff ff
2993 00:43:09.841416 38 ff ff
2994 00:43:09.844715 39 ff ff
2995 00:43:09.844778 40 ff ff
2996 00:43:09.847983 41 ff ff
2997 00:43:09.848047 42 ff ff
2998 00:43:09.851152 43 ff ff
2999 00:43:09.854654 pass bytecount = 0xff (0xff: all bytes pass)
3000 00:43:09.854718
3001 00:43:09.854769 DQS0 dly: 37
3002 00:43:09.858009 DQS1 dly: 31
3003 00:43:09.858073 Write Rank0 MR2 =0x2d
3004 00:43:09.861368 [RankSwap] Rank num 2, (Multi 1), Rank 0
3005 00:43:09.864741 Write Rank1 MR1 =0xd6
3006 00:43:09.864804 [Gating]
3007 00:43:09.864856 ==
3008 00:43:09.871404 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3009 00:43:09.874667 fsp= 1, odt_onoff= 1, Byte mode= 0
3010 00:43:09.874732 ==
3011 00:43:09.878087 3 1 0 |3534 2c2b |(11 11)(11 11) |(1 1)(0 0)| 0
3012 00:43:09.881525 3 1 4 |3534 2c2b |(11 11)(11 11) |(0 0)(1 0)| 0
3013 00:43:09.888190 3 1 8 |3534 2c2b |(11 11)(11 11) |(0 0)(1 0)| 0
3014 00:43:09.891518 3 1 12 |3534 2c2b |(11 11)(11 11) |(0 0)(1 0)| 0
3015 00:43:09.894819 3 1 16 |3534 2c2b |(11 11)(11 11) |(0 0)(1 0)| 0
3016 00:43:09.898162 3 1 20 |3534 2c2b |(11 11)(11 11) |(0 0)(1 0)| 0
3017 00:43:09.904861 3 1 24 |3534 2c2b |(11 11)(11 11) |(0 1)(1 0)| 0
3018 00:43:09.908030 3 1 28 |3534 2c2b |(11 11)(11 11) |(0 1)(1 0)| 0
3019 00:43:09.911657 3 2 0 |201 2c2b |(11 11)(11 11) |(1 1)(1 0)| 0
3020 00:43:09.918177 3 2 4 |3d3d 302 |(11 11)(11 11) |(1 1)(0 0)| 0
3021 00:43:09.921489 3 2 8 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
3022 00:43:09.924977 3 2 12 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
3023 00:43:09.931572 3 2 16 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
3024 00:43:09.935295 3 2 20 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
3025 00:43:09.938764 3 2 24 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
3026 00:43:09.941717 3 2 28 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
3027 00:43:09.948489 3 3 0 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
3028 00:43:09.952058 3 3 4 |3d3d 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
3029 00:43:09.955400 3 3 8 |201 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
3030 00:43:09.962016 3 3 12 |3534 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
3031 00:43:09.964904 [Byte 0] Lead/lag Transition tap number (1)
3032 00:43:09.968265 3 3 16 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
3033 00:43:09.971797 3 3 20 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
3034 00:43:09.978360 3 3 24 |3534 3534 |(11 11)(11 11) |(0 1)(0 0)| 0
3035 00:43:09.981558 3 3 28 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
3036 00:43:09.984724 3 4 0 |403 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
3037 00:43:09.991571 3 4 4 |3d3d 201 |(11 11)(11 11) |(1 1)(1 1)| 0
3038 00:43:09.994804 3 4 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3039 00:43:09.998005 3 4 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3040 00:43:10.004811 3 4 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3041 00:43:10.008063 3 4 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3042 00:43:10.011673 3 4 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3043 00:43:10.014917 3 4 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3044 00:43:10.021571 3 5 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3045 00:43:10.025041 3 5 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3046 00:43:10.028521 3 5 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3047 00:43:10.035369 3 5 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3048 00:43:10.038466 3 5 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3049 00:43:10.041891 3 5 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3050 00:43:10.048268 [Byte 0] Lead/lag falling Transition (3, 5, 20)
3051 00:43:10.051681 3 5 24 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 1)| 0
3052 00:43:10.054987 [Byte 1] Lead/lag falling Transition (3, 5, 24)
3053 00:43:10.058450 3 5 28 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 0)| 0
3054 00:43:10.064896 [Byte 0] Lead/lag Transition tap number (3)
3055 00:43:10.068643 3 6 0 |202 3d3d |(11 11)(11 11) |(0 0)(1 0)| 0
3056 00:43:10.071650 [Byte 1] Lead/lag Transition tap number (3)
3057 00:43:10.075043 3 6 4 |4646 403 |(10 10)(11 11) |(0 0)(0 0)| 0
3058 00:43:10.081534 3 6 8 |4646 4646 |(0 0)(10 10) |(0 0)(0 0)| 0
3059 00:43:10.081607 [Byte 0]First pass (3, 6, 8)
3060 00:43:10.088402 3 6 12 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3061 00:43:10.088469 [Byte 1]First pass (3, 6, 12)
3062 00:43:10.094928 3 6 16 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3063 00:43:10.098571 3 6 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3064 00:43:10.101590 3 6 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3065 00:43:10.105059 3 6 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3066 00:43:10.108316 3 7 0 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3067 00:43:10.114906 3 7 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3068 00:43:10.118344 3 7 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3069 00:43:10.122001 3 7 12 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3070 00:43:10.125012 All bytes gating window > 1UI, Early break!
3071 00:43:10.125074
3072 00:43:10.128302 best DQS0 dly(2T, 0.5T, PI) = (3, 5, 26)
3073 00:43:10.128364
3074 00:43:10.131761 best DQS1 dly(2T, 0.5T, PI) = (3, 5, 30)
3075 00:43:10.131828
3076 00:43:10.135227
3077 00:43:10.135296
3078 00:43:10.138558 best DQS0 P1 dly(2T, 0.5T, PI) = (4, 1, 26)
3079 00:43:10.138627
3080 00:43:10.142050 best DQS1 P1 dly(2T, 0.5T, PI) = (4, 1, 30)
3081 00:43:10.142116
3082 00:43:10.142171
3083 00:43:10.145278 Write Rank1 MR1 =0x56
3084 00:43:10.145338
3085 00:43:10.148630 best RODT dly(2T, 0.5T) = (2, 2)
3086 00:43:10.148695
3087 00:43:10.148748 best RODT dly(2T, 0.5T) = (2, 2)
3088 00:43:10.152037 ==
3089 00:43:10.155393 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3090 00:43:10.158626 fsp= 1, odt_onoff= 1, Byte mode= 0
3091 00:43:10.158688 ==
3092 00:43:10.161907 Start DQ dly to find pass range UseTestEngine =0
3093 00:43:10.165494 x-axis: bit #, y-axis: DQ dly (-127~63)
3094 00:43:10.168974 RX Vref Scan = 0
3095 00:43:10.172007 -26, [0] xxxxxxxx xxxxxxxx [MSB]
3096 00:43:10.175403 -25, [0] xxxxxxxx xxxxxxxx [MSB]
3097 00:43:10.175476 -24, [0] xxxxxxxx xxxxxxxx [MSB]
3098 00:43:10.178992 -23, [0] xxxxxxxx xxxxxxxx [MSB]
3099 00:43:10.182239 -22, [0] xxxxxxxx xxxxxxxx [MSB]
3100 00:43:10.185486 -21, [0] xxxxxxxx xxxxxxxx [MSB]
3101 00:43:10.188887 -20, [0] xxxxxxxx xxxxxxxx [MSB]
3102 00:43:10.192243 -19, [0] xxxxxxxx xxxxxxxx [MSB]
3103 00:43:10.195598 -18, [0] xxxxxxxx xxxxxxxx [MSB]
3104 00:43:10.198905 -17, [0] xxxxxxxx xxxxxxxx [MSB]
3105 00:43:10.198980 -16, [0] xxxxxxxx xxxxxxxx [MSB]
3106 00:43:10.202364 -15, [0] xxxxxxxx xxxxxxxx [MSB]
3107 00:43:10.205607 -14, [0] xxxxxxxx xxxxxxxx [MSB]
3108 00:43:10.208984 -13, [0] xxxxxxxx xxxxxxxx [MSB]
3109 00:43:10.212462 -12, [0] xxxxxxxx xxxxxxxx [MSB]
3110 00:43:10.215601 -11, [0] xxxxxxxx xxxxxxxx [MSB]
3111 00:43:10.219053 -10, [0] xxxxxxxx xxxxxxxx [MSB]
3112 00:43:10.222327 -9, [0] xxxxxxxx xxxxxxxx [MSB]
3113 00:43:10.222406 -8, [0] xxxxxxxx xxxxxxxx [MSB]
3114 00:43:10.225624 -7, [0] xxxxxxxx xxxxxxxx [MSB]
3115 00:43:10.229116 -6, [0] xxxxxxxx xxxxxxxx [MSB]
3116 00:43:10.232403 -5, [0] xxxxxxxx xxxxxxxx [MSB]
3117 00:43:10.235975 -4, [0] xxxxxxxx xxxxxxxx [MSB]
3118 00:43:10.239047 -3, [0] xxxxxxxx xxxxxxxx [MSB]
3119 00:43:10.242698 -2, [0] xxxoxxxx xxxxxxxo [MSB]
3120 00:43:10.242767 -1, [0] xxxoxxxx xxxxxxxo [MSB]
3121 00:43:10.245834 0, [0] xxooxxxx xxoxxxxo [MSB]
3122 00:43:10.249078 1, [0] xxooxxxo oxoxxxxo [MSB]
3123 00:43:10.252622 2, [0] xxoooxxo oooxxxxo [MSB]
3124 00:43:10.256028 3, [0] xxoooxxo oooxxxoo [MSB]
3125 00:43:10.256099 4, [0] xxoooxxo ooooxxoo [MSB]
3126 00:43:10.259061 5, [0] xooooxxo oooooooo [MSB]
3127 00:43:10.262469 6, [0] xoooooxo oooooooo [MSB]
3128 00:43:10.265931 33, [0] oooxoooo oooooooo [MSB]
3129 00:43:10.269324 34, [0] oooxoooo ooooooox [MSB]
3130 00:43:10.272721 35, [0] ooxxoooo oxooooox [MSB]
3131 00:43:10.275902 36, [0] ooxxoooo oxooooox [MSB]
3132 00:43:10.276005 37, [0] ooxxoooo xxxxooox [MSB]
3133 00:43:10.279488 38, [0] ooxxoooo xxxxooox [MSB]
3134 00:43:10.282514 39, [0] ooxxxoox xxxxooxx [MSB]
3135 00:43:10.286119 40, [0] ooxxxoox xxxxoxxx [MSB]
3136 00:43:10.289620 41, [0] ooxxxoox xxxxxxxx [MSB]
3137 00:43:10.292721 42, [0] ooxxxxox xxxxxxxx [MSB]
3138 00:43:10.292791 43, [0] oxxxxxxx xxxxxxxx [MSB]
3139 00:43:10.296506 44, [0] xxxxxxxx xxxxxxxx [MSB]
3140 00:43:10.299639 iDelay=44, Bit 0, Center 25 (7 ~ 43) 37
3141 00:43:10.303031 iDelay=44, Bit 1, Center 23 (5 ~ 42) 38
3142 00:43:10.306182 iDelay=44, Bit 2, Center 17 (0 ~ 34) 35
3143 00:43:10.312969 iDelay=44, Bit 3, Center 15 (-2 ~ 32) 35
3144 00:43:10.316236 iDelay=44, Bit 4, Center 20 (2 ~ 38) 37
3145 00:43:10.319752 iDelay=44, Bit 5, Center 23 (6 ~ 41) 36
3146 00:43:10.322863 iDelay=44, Bit 6, Center 24 (7 ~ 42) 36
3147 00:43:10.326202 iDelay=44, Bit 7, Center 19 (1 ~ 38) 38
3148 00:43:10.329431 iDelay=44, Bit 8, Center 18 (1 ~ 36) 36
3149 00:43:10.332693 iDelay=44, Bit 9, Center 18 (2 ~ 34) 33
3150 00:43:10.336164 iDelay=44, Bit 10, Center 18 (0 ~ 36) 37
3151 00:43:10.339402 iDelay=44, Bit 11, Center 20 (4 ~ 36) 33
3152 00:43:10.342822 iDelay=44, Bit 12, Center 22 (5 ~ 40) 36
3153 00:43:10.346235 iDelay=44, Bit 13, Center 22 (5 ~ 39) 35
3154 00:43:10.349652 iDelay=44, Bit 14, Center 20 (3 ~ 38) 36
3155 00:43:10.353069 iDelay=44, Bit 15, Center 15 (-2 ~ 33) 36
3156 00:43:10.356070 ==
3157 00:43:10.359590 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3158 00:43:10.362932 fsp= 1, odt_onoff= 1, Byte mode= 0
3159 00:43:10.362992 ==
3160 00:43:10.363045 DQS Delay:
3161 00:43:10.366217 DQS0 = 0, DQS1 = 0
3162 00:43:10.366288 DQM Delay:
3163 00:43:10.369447 DQM0 = 20, DQM1 = 19
3164 00:43:10.369506 DQ Delay:
3165 00:43:10.373122 DQ0 =25, DQ1 =23, DQ2 =17, DQ3 =15
3166 00:43:10.376194 DQ4 =20, DQ5 =23, DQ6 =24, DQ7 =19
3167 00:43:10.379620 DQ8 =18, DQ9 =18, DQ10 =18, DQ11 =20
3168 00:43:10.382842 DQ12 =22, DQ13 =22, DQ14 =20, DQ15 =15
3169 00:43:10.382904
3170 00:43:10.382954
3171 00:43:10.386151 DramC Write-DBI off
3172 00:43:10.386216 ==
3173 00:43:10.389651 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3174 00:43:10.393156 fsp= 1, odt_onoff= 1, Byte mode= 0
3175 00:43:10.393226 ==
3176 00:43:10.396508 [TxWindowPerbitCal] calType=2, VrefScanEnable 0
3177 00:43:10.399684
3178 00:43:10.399745 Begin, DQ Scan Range 927~1183
3179 00:43:10.399802
3180 00:43:10.399854
3181 00:43:10.403104 TX Vref Scan disable
3182 00:43:10.406251 927 |3 4 31|[0] xxxxxxxx xxxxxxxx [MSB]
3183 00:43:10.409700 928 |3 4 32|[0] xxxxxxxx xxxxxxxx [MSB]
3184 00:43:10.412920 929 |3 4 33|[0] xxxxxxxx xxxxxxxx [MSB]
3185 00:43:10.416344 930 |3 4 34|[0] xxxxxxxx xxxxxxxx [MSB]
3186 00:43:10.419607 931 |3 4 35|[0] xxxxxxxx xxxxxxxx [MSB]
3187 00:43:10.422900 932 |3 4 36|[0] xxxxxxxx xxxxxxxx [MSB]
3188 00:43:10.426518 933 |3 4 37|[0] xxxxxxxx xxxxxxxx [MSB]
3189 00:43:10.429624 934 |3 4 38|[0] xxxxxxxx xxxxxxxx [MSB]
3190 00:43:10.433196 935 |3 4 39|[0] xxxxxxxx xxxxxxxx [MSB]
3191 00:43:10.439737 936 |3 4 40|[0] xxxxxxxx xxxxxxxx [MSB]
3192 00:43:10.442950 937 |3 4 41|[0] xxxxxxxx xxxxxxxx [MSB]
3193 00:43:10.446418 938 |3 4 42|[0] xxxxxxxx xxxxxxxx [MSB]
3194 00:43:10.449903 939 |3 4 43|[0] xxxxxxxx xxxxxxxx [MSB]
3195 00:43:10.453353 940 |3 4 44|[0] xxxxxxxx xxxxxxxx [MSB]
3196 00:43:10.456490 941 |3 4 45|[0] xxxxxxxx xxxxxxxx [MSB]
3197 00:43:10.459938 942 |3 4 46|[0] xxxxxxxx xxxxxxxx [MSB]
3198 00:43:10.463194 943 |3 4 47|[0] xxxxxxxx xxxxxxxx [MSB]
3199 00:43:10.466857 944 |3 4 48|[0] xxxxxxxx xxxxxxxx [MSB]
3200 00:43:10.470029 945 |3 4 49|[0] xxxxxxxx xxxxxxxx [MSB]
3201 00:43:10.473193 946 |3 4 50|[0] xxxxxxxx xxxxxxxx [MSB]
3202 00:43:10.476748 947 |3 4 51|[0] xxxxxxxx xxxxxxxx [MSB]
3203 00:43:10.479976 948 |3 4 52|[0] xxxxxxxx xxxxxxxx [MSB]
3204 00:43:10.483251 949 |3 4 53|[0] xxxxxxxx xxxxxxxx [MSB]
3205 00:43:10.486571 950 |3 4 54|[0] xxxxxxxx xxxxxxxx [MSB]
3206 00:43:10.490044 951 |3 4 55|[0] xxxxxxxx xxxxxxxx [MSB]
3207 00:43:10.493364 952 |3 4 56|[0] xxxxxxxx xxxxxxxx [MSB]
3208 00:43:10.499996 953 |3 4 57|[0] xxxxxxxx xxxxxxxx [MSB]
3209 00:43:10.503189 954 |3 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
3210 00:43:10.506615 955 |3 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
3211 00:43:10.509993 956 |3 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
3212 00:43:10.513191 957 |3 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
3213 00:43:10.516913 958 |3 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
3214 00:43:10.520140 959 |3 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
3215 00:43:10.523506 960 |3 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
3216 00:43:10.526956 961 |3 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
3217 00:43:10.530137 962 |3 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
3218 00:43:10.533204 963 |3 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
3219 00:43:10.536579 964 |3 6 4|[0] xxxxxxxx xxxxxxxo [MSB]
3220 00:43:10.539874 965 |3 6 5|[0] xxxxxxxx xxxxxxxo [MSB]
3221 00:43:10.543393 966 |3 6 6|[0] xxxxxxxx xxxxxxxo [MSB]
3222 00:43:10.546531 967 |3 6 7|[0] xxxxxxxx ooxxxxxo [MSB]
3223 00:43:10.550233 968 |3 6 8|[0] xxxxxxxx oooxxxxo [MSB]
3224 00:43:10.553526 969 |3 6 9|[0] xxxxxxxx ooooxooo [MSB]
3225 00:43:10.556834 970 |3 6 10|[0] xxxxxxxx oooooooo [MSB]
3226 00:43:10.560254 971 |3 6 11|[0] xxxxxxxx oooooooo [MSB]
3227 00:43:10.563428 972 |3 6 12|[0] xxxxxxxx oooooooo [MSB]
3228 00:43:10.566854 973 |3 6 13|[0] xxxxxxxx oooooooo [MSB]
3229 00:43:10.570341 974 |3 6 14|[0] xxxxxxxx oooooooo [MSB]
3230 00:43:10.573592 975 |3 6 15|[0] xxoooxxx oooooooo [MSB]
3231 00:43:10.580218 976 |3 6 16|[0] xooooxxo oooooooo [MSB]
3232 00:43:10.583531 989 |3 6 29|[0] oooooooo ooooooox [MSB]
3233 00:43:10.587059 990 |3 6 30|[0] oooooooo xxxxxxxx [MSB]
3234 00:43:10.590280 991 |3 6 31|[0] oooooooo xxxxxxxx [MSB]
3235 00:43:10.593561 992 |3 6 32|[0] oooooooo xxxxxxxx [MSB]
3236 00:43:10.597011 993 |3 6 33|[0] oooooooo xxxxxxxx [MSB]
3237 00:43:10.600336 994 |3 6 34|[0] oooooooo xxxxxxxx [MSB]
3238 00:43:10.603566 995 |3 6 35|[0] oooooooo xxxxxxxx [MSB]
3239 00:43:10.610313 996 |3 6 36|[0] oooxoooo xxxxxxxx [MSB]
3240 00:43:10.613666 997 |3 6 37|[0] ooxxoooo xxxxxxxx [MSB]
3241 00:43:10.616984 998 |3 6 38|[0] ooxxxoox xxxxxxxx [MSB]
3242 00:43:10.620460 999 |3 6 39|[0] xxxxxxxx xxxxxxxx [MSB]
3243 00:43:10.623757 Byte0, DQ PI dly=986, DQM PI dly= 986
3244 00:43:10.627338 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 26)
3245 00:43:10.627403
3246 00:43:10.630564 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 26)
3247 00:43:10.630624
3248 00:43:10.633642 Byte1, DQ PI dly=977, DQM PI dly= 977
3249 00:43:10.640412 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 17)
3250 00:43:10.640481
3251 00:43:10.643756 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 17)
3252 00:43:10.643819
3253 00:43:10.643872 ==
3254 00:43:10.650627 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3255 00:43:10.653787 fsp= 1, odt_onoff= 1, Byte mode= 0
3256 00:43:10.653856 ==
3257 00:43:10.657441 [TxWindowPerbitCal] calType=0, VrefScanEnable 1
3258 00:43:10.657505
3259 00:43:10.660461 Begin, DQ Scan Range 953~1017
3260 00:43:10.660523 Write Rank1 MR14 =0x0
3261 00:43:10.670965
3262 00:43:10.671023 CH=1, VrefRange= 0, VrefLevel = 0
3263 00:43:10.677536 TX Bit0 (979~998) 20 988, Bit8 (969~986) 18 977,
3264 00:43:10.680793 TX Bit1 (977~997) 21 987, Bit9 (969~986) 18 977,
3265 00:43:10.687640 TX Bit2 (976~992) 17 984, Bit10 (970~985) 16 977,
3266 00:43:10.690852 TX Bit3 (975~991) 17 983, Bit11 (971~987) 17 979,
3267 00:43:10.694261 TX Bit4 (977~994) 18 985, Bit12 (971~990) 20 980,
3268 00:43:10.700977 TX Bit5 (978~998) 21 988, Bit13 (971~986) 16 978,
3269 00:43:10.704437 TX Bit6 (978~998) 21 988, Bit14 (971~987) 17 979,
3270 00:43:10.707558 TX Bit7 (977~994) 18 985, Bit15 (967~985) 19 976,
3271 00:43:10.707621
3272 00:43:10.710961 Write Rank1 MR14 =0x2
3273 00:43:10.720032
3274 00:43:10.720098 CH=1, VrefRange= 0, VrefLevel = 2
3275 00:43:10.726474 TX Bit0 (977~998) 22 987, Bit8 (969~987) 19 978,
3276 00:43:10.730043 TX Bit1 (977~997) 21 987, Bit9 (969~986) 18 977,
3277 00:43:10.736585 TX Bit2 (975~992) 18 983, Bit10 (970~986) 17 978,
3278 00:43:10.739901 TX Bit3 (975~991) 17 983, Bit11 (971~989) 19 980,
3279 00:43:10.743376 TX Bit4 (976~994) 19 985, Bit12 (971~990) 20 980,
3280 00:43:10.749891 TX Bit5 (978~998) 21 988, Bit13 (971~987) 17 979,
3281 00:43:10.753340 TX Bit6 (978~998) 21 988, Bit14 (970~987) 18 978,
3282 00:43:10.756707 TX Bit7 (977~995) 19 986, Bit15 (966~985) 20 975,
3283 00:43:10.756769
3284 00:43:10.760024 Write Rank1 MR14 =0x4
3285 00:43:10.769149
3286 00:43:10.769212 CH=1, VrefRange= 0, VrefLevel = 4
3287 00:43:10.775617 TX Bit0 (978~998) 21 988, Bit8 (969~987) 19 978,
3288 00:43:10.779019 TX Bit1 (977~997) 21 987, Bit9 (969~986) 18 977,
3289 00:43:10.785578 TX Bit2 (975~992) 18 983, Bit10 (970~986) 17 978,
3290 00:43:10.789278 TX Bit3 (974~991) 18 982, Bit11 (970~990) 21 980,
3291 00:43:10.792476 TX Bit4 (976~995) 20 985, Bit12 (971~990) 20 980,
3292 00:43:10.799170 TX Bit5 (978~998) 21 988, Bit13 (971~987) 17 979,
3293 00:43:10.802479 TX Bit6 (978~998) 21 988, Bit14 (970~987) 18 978,
3294 00:43:10.805947 TX Bit7 (977~996) 20 986, Bit15 (966~985) 20 975,
3295 00:43:10.806009
3296 00:43:10.809142 Write Rank1 MR14 =0x6
3297 00:43:10.818091
3298 00:43:10.818154 CH=1, VrefRange= 0, VrefLevel = 6
3299 00:43:10.824869 TX Bit0 (977~998) 22 987, Bit8 (968~988) 21 978,
3300 00:43:10.828326 TX Bit1 (977~998) 22 987, Bit9 (968~987) 20 977,
3301 00:43:10.831818 TX Bit2 (975~993) 19 984, Bit10 (970~986) 17 978,
3302 00:43:10.838478 TX Bit3 (974~992) 19 983, Bit11 (970~990) 21 980,
3303 00:43:10.841892 TX Bit4 (976~996) 21 986, Bit12 (971~991) 21 981,
3304 00:43:10.848348 TX Bit5 (977~998) 22 987, Bit13 (970~989) 20 979,
3305 00:43:10.851709 TX Bit6 (977~998) 22 987, Bit14 (970~989) 20 979,
3306 00:43:10.855261 TX Bit7 (976~996) 21 986, Bit15 (966~985) 20 975,
3307 00:43:10.855337
3308 00:43:10.858278 Write Rank1 MR14 =0x8
3309 00:43:10.867567
3310 00:43:10.867643 CH=1, VrefRange= 0, VrefLevel = 8
3311 00:43:10.874187 TX Bit0 (977~999) 23 988, Bit8 (968~989) 22 978,
3312 00:43:10.877289 TX Bit1 (976~998) 23 987, Bit9 (968~988) 21 978,
3313 00:43:10.884014 TX Bit2 (975~993) 19 984, Bit10 (970~987) 18 978,
3314 00:43:10.887497 TX Bit3 (974~992) 19 983, Bit11 (970~991) 22 980,
3315 00:43:10.890843 TX Bit4 (976~996) 21 986, Bit12 (970~991) 22 980,
3316 00:43:10.897611 TX Bit5 (977~998) 22 987, Bit13 (970~989) 20 979,
3317 00:43:10.901082 TX Bit6 (977~999) 23 988, Bit14 (970~989) 20 979,
3318 00:43:10.904189 TX Bit7 (977~996) 20 986, Bit15 (965~986) 22 975,
3319 00:43:10.904253
3320 00:43:10.907290 Write Rank1 MR14 =0xa
3321 00:43:10.916618
3322 00:43:10.920048 CH=1, VrefRange= 0, VrefLevel = 10
3323 00:43:10.923220 TX Bit0 (977~999) 23 988, Bit8 (968~989) 22 978,
3324 00:43:10.926756 TX Bit1 (976~998) 23 987, Bit9 (968~988) 21 978,
3325 00:43:10.933372 TX Bit2 (974~994) 21 984, Bit10 (969~988) 20 978,
3326 00:43:10.937171 TX Bit3 (973~993) 21 983, Bit11 (970~990) 21 980,
3327 00:43:10.940111 TX Bit4 (976~996) 21 986, Bit12 (970~991) 22 980,
3328 00:43:10.946622 TX Bit5 (977~999) 23 988, Bit13 (970~990) 21 980,
3329 00:43:10.950046 TX Bit6 (977~999) 23 988, Bit14 (969~990) 22 979,
3330 00:43:10.953300 TX Bit7 (976~997) 22 986, Bit15 (964~986) 23 975,
3331 00:43:10.953363
3332 00:43:10.956819 Write Rank1 MR14 =0xc
3333 00:43:10.965986
3334 00:43:10.969402 CH=1, VrefRange= 0, VrefLevel = 12
3335 00:43:10.973026 TX Bit0 (977~999) 23 988, Bit8 (968~990) 23 979,
3336 00:43:10.976180 TX Bit1 (976~998) 23 987, Bit9 (968~989) 22 978,
3337 00:43:10.982967 TX Bit2 (974~995) 22 984, Bit10 (969~989) 21 979,
3338 00:43:10.986067 TX Bit3 (973~994) 22 983, Bit11 (970~991) 22 980,
3339 00:43:10.989531 TX Bit4 (975~997) 23 986, Bit12 (970~991) 22 980,
3340 00:43:10.995948 TX Bit5 (977~999) 23 988, Bit13 (969~990) 22 979,
3341 00:43:10.999634 TX Bit6 (977~999) 23 988, Bit14 (969~990) 22 979,
3342 00:43:11.002726 TX Bit7 (976~997) 22 986, Bit15 (964~987) 24 975,
3343 00:43:11.002789
3344 00:43:11.005982 Write Rank1 MR14 =0xe
3345 00:43:11.015740
3346 00:43:11.018833 CH=1, VrefRange= 0, VrefLevel = 14
3347 00:43:11.022422 TX Bit0 (977~1000) 24 988, Bit8 (968~990) 23 979,
3348 00:43:11.025574 TX Bit1 (976~998) 23 987, Bit9 (968~990) 23 979,
3349 00:43:11.032440 TX Bit2 (974~996) 23 985, Bit10 (968~990) 23 979,
3350 00:43:11.035602 TX Bit3 (972~995) 24 983, Bit11 (969~992) 24 980,
3351 00:43:11.038956 TX Bit4 (975~997) 23 986, Bit12 (970~992) 23 981,
3352 00:43:11.045616 TX Bit5 (977~999) 23 988, Bit13 (969~991) 23 980,
3353 00:43:11.048918 TX Bit6 (977~1000) 24 988, Bit14 (969~991) 23 980,
3354 00:43:11.052426 TX Bit7 (976~997) 22 986, Bit15 (964~987) 24 975,
3355 00:43:11.052490
3356 00:43:11.055491 Write Rank1 MR14 =0x10
3357 00:43:11.065471
3358 00:43:11.068647 CH=1, VrefRange= 0, VrefLevel = 16
3359 00:43:11.072187 TX Bit0 (977~1000) 24 988, Bit8 (967~990) 24 978,
3360 00:43:11.075792 TX Bit1 (976~999) 24 987, Bit9 (967~990) 24 978,
3361 00:43:11.082120 TX Bit2 (974~996) 23 985, Bit10 (968~990) 23 979,
3362 00:43:11.085519 TX Bit3 (972~995) 24 983, Bit11 (969~991) 23 980,
3363 00:43:11.089069 TX Bit4 (975~997) 23 986, Bit12 (970~992) 23 981,
3364 00:43:11.095662 TX Bit5 (977~999) 23 988, Bit13 (970~991) 22 980,
3365 00:43:11.099059 TX Bit6 (977~1000) 24 988, Bit14 (969~991) 23 980,
3366 00:43:11.102368 TX Bit7 (976~998) 23 987, Bit15 (964~989) 26 976,
3367 00:43:11.102436
3368 00:43:11.105303 Write Rank1 MR14 =0x12
3369 00:43:11.115278
3370 00:43:11.118533 CH=1, VrefRange= 0, VrefLevel = 18
3371 00:43:11.121870 TX Bit0 (977~1001) 25 989, Bit8 (967~991) 25 979,
3372 00:43:11.125166 TX Bit1 (976~999) 24 987, Bit9 (967~990) 24 978,
3373 00:43:11.131990 TX Bit2 (973~997) 25 985, Bit10 (968~991) 24 979,
3374 00:43:11.134980 TX Bit3 (972~996) 25 984, Bit11 (969~992) 24 980,
3375 00:43:11.138203 TX Bit4 (975~997) 23 986, Bit12 (969~992) 24 980,
3376 00:43:11.145173 TX Bit5 (976~1000) 25 988, Bit13 (969~991) 23 980,
3377 00:43:11.148660 TX Bit6 (976~1000) 25 988, Bit14 (968~991) 24 979,
3378 00:43:11.155051 TX Bit7 (975~998) 24 986, Bit15 (964~990) 27 977,
3379 00:43:11.155121
3380 00:43:11.155177 Write Rank1 MR14 =0x14
3381 00:43:11.165343
3382 00:43:11.168990 CH=1, VrefRange= 0, VrefLevel = 20
3383 00:43:11.172050 TX Bit0 (977~1001) 25 989, Bit8 (967~991) 25 979,
3384 00:43:11.175618 TX Bit1 (976~999) 24 987, Bit9 (966~991) 26 978,
3385 00:43:11.181884 TX Bit2 (972~997) 26 984, Bit10 (968~991) 24 979,
3386 00:43:11.185411 TX Bit3 (971~996) 26 983, Bit11 (969~992) 24 980,
3387 00:43:11.188829 TX Bit4 (974~998) 25 986, Bit12 (970~992) 23 981,
3388 00:43:11.195355 TX Bit5 (976~1000) 25 988, Bit13 (969~991) 23 980,
3389 00:43:11.198634 TX Bit6 (976~1001) 26 988, Bit14 (968~991) 24 979,
3390 00:43:11.201908 TX Bit7 (975~998) 24 986, Bit15 (963~990) 28 976,
3391 00:43:11.205244
3392 00:43:11.205309 Write Rank1 MR14 =0x16
3393 00:43:11.215433
3394 00:43:11.218568 CH=1, VrefRange= 0, VrefLevel = 22
3395 00:43:11.221959 TX Bit0 (977~1001) 25 989, Bit8 (966~991) 26 978,
3396 00:43:11.225228 TX Bit1 (976~999) 24 987, Bit9 (966~991) 26 978,
3397 00:43:11.232008 TX Bit2 (972~997) 26 984, Bit10 (967~991) 25 979,
3398 00:43:11.235413 TX Bit3 (971~997) 27 984, Bit11 (968~992) 25 980,
3399 00:43:11.238992 TX Bit4 (974~998) 25 986, Bit12 (969~992) 24 980,
3400 00:43:11.245575 TX Bit5 (976~1000) 25 988, Bit13 (969~991) 23 980,
3401 00:43:11.249040 TX Bit6 (976~1001) 26 988, Bit14 (968~991) 24 979,
3402 00:43:11.252166 TX Bit7 (975~998) 24 986, Bit15 (963~990) 28 976,
3403 00:43:11.252227
3404 00:43:11.255492 Write Rank1 MR14 =0x18
3405 00:43:11.265167
3406 00:43:11.268851 CH=1, VrefRange= 0, VrefLevel = 24
3407 00:43:11.271970 TX Bit0 (976~1001) 26 988, Bit8 (966~991) 26 978,
3408 00:43:11.275299 TX Bit1 (975~999) 25 987, Bit9 (966~991) 26 978,
3409 00:43:11.282029 TX Bit2 (971~997) 27 984, Bit10 (967~991) 25 979,
3410 00:43:11.285356 TX Bit3 (970~997) 28 983, Bit11 (968~992) 25 980,
3411 00:43:11.288675 TX Bit4 (973~998) 26 985, Bit12 (969~992) 24 980,
3412 00:43:11.295407 TX Bit5 (976~1001) 26 988, Bit13 (968~992) 25 980,
3413 00:43:11.298824 TX Bit6 (976~1001) 26 988, Bit14 (968~991) 24 979,
3414 00:43:11.302149 TX Bit7 (975~998) 24 986, Bit15 (963~990) 28 976,
3415 00:43:11.305244
3416 00:43:11.305312 Write Rank1 MR14 =0x1a
3417 00:43:11.315772
3418 00:43:11.318906 CH=1, VrefRange= 0, VrefLevel = 26
3419 00:43:11.322078 TX Bit0 (976~1002) 27 989, Bit8 (965~991) 27 978,
3420 00:43:11.325335 TX Bit1 (975~999) 25 987, Bit9 (965~991) 27 978,
3421 00:43:11.332194 TX Bit2 (971~997) 27 984, Bit10 (967~991) 25 979,
3422 00:43:11.335444 TX Bit3 (970~997) 28 983, Bit11 (968~992) 25 980,
3423 00:43:11.338753 TX Bit4 (973~998) 26 985, Bit12 (969~992) 24 980,
3424 00:43:11.345538 TX Bit5 (976~1000) 25 988, Bit13 (968~992) 25 980,
3425 00:43:11.348955 TX Bit6 (976~1001) 26 988, Bit14 (967~991) 25 979,
3426 00:43:11.352055 TX Bit7 (974~998) 25 986, Bit15 (963~990) 28 976,
3427 00:43:11.355299
3428 00:43:11.355363 Write Rank1 MR14 =0x1c
3429 00:43:11.365323
3430 00:43:11.368824 CH=1, VrefRange= 0, VrefLevel = 28
3431 00:43:11.372021 TX Bit0 (976~1002) 27 989, Bit8 (965~991) 27 978,
3432 00:43:11.375336 TX Bit1 (975~999) 25 987, Bit9 (965~991) 27 978,
3433 00:43:11.382469 TX Bit2 (971~997) 27 984, Bit10 (967~991) 25 979,
3434 00:43:11.385672 TX Bit3 (970~997) 28 983, Bit11 (968~992) 25 980,
3435 00:43:11.388768 TX Bit4 (973~998) 26 985, Bit12 (969~992) 24 980,
3436 00:43:11.395586 TX Bit5 (976~1000) 25 988, Bit13 (968~992) 25 980,
3437 00:43:11.398668 TX Bit6 (976~1001) 26 988, Bit14 (967~991) 25 979,
3438 00:43:11.402114 TX Bit7 (974~998) 25 986, Bit15 (963~990) 28 976,
3439 00:43:11.405388
3440 00:43:11.405457 Write Rank1 MR14 =0x1e
3441 00:43:11.415458
3442 00:43:11.418605 CH=1, VrefRange= 0, VrefLevel = 30
3443 00:43:11.422389 TX Bit0 (976~1002) 27 989, Bit8 (965~991) 27 978,
3444 00:43:11.425696 TX Bit1 (975~999) 25 987, Bit9 (965~991) 27 978,
3445 00:43:11.432412 TX Bit2 (971~997) 27 984, Bit10 (967~991) 25 979,
3446 00:43:11.435469 TX Bit3 (970~997) 28 983, Bit11 (968~992) 25 980,
3447 00:43:11.439329 TX Bit4 (973~998) 26 985, Bit12 (969~992) 24 980,
3448 00:43:11.445970 TX Bit5 (976~1000) 25 988, Bit13 (968~992) 25 980,
3449 00:43:11.449056 TX Bit6 (976~1001) 26 988, Bit14 (967~991) 25 979,
3450 00:43:11.452163 TX Bit7 (974~998) 25 986, Bit15 (963~990) 28 976,
3451 00:43:11.452228
3452 00:43:11.455428 Write Rank1 MR14 =0x20
3453 00:43:11.465177
3454 00:43:11.468735 CH=1, VrefRange= 0, VrefLevel = 32
3455 00:43:11.471826 TX Bit0 (976~1002) 27 989, Bit8 (965~991) 27 978,
3456 00:43:11.475163 TX Bit1 (975~999) 25 987, Bit9 (965~991) 27 978,
3457 00:43:11.481987 TX Bit2 (971~997) 27 984, Bit10 (967~991) 25 979,
3458 00:43:11.485366 TX Bit3 (970~997) 28 983, Bit11 (968~992) 25 980,
3459 00:43:11.488607 TX Bit4 (973~998) 26 985, Bit12 (969~992) 24 980,
3460 00:43:11.495439 TX Bit5 (976~1000) 25 988, Bit13 (968~992) 25 980,
3461 00:43:11.498931 TX Bit6 (976~1001) 26 988, Bit14 (967~991) 25 979,
3462 00:43:11.502361 TX Bit7 (974~998) 25 986, Bit15 (963~990) 28 976,
3463 00:43:11.502434
3464 00:43:11.505600
3465 00:43:11.505663 TX Vref found, early break! 392< 394
3466 00:43:11.512366 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =753/100 ps
3467 00:43:11.515517 u1DelayCellOfst[0]=7 cells (6 PI)
3468 00:43:11.518937 u1DelayCellOfst[1]=5 cells (4 PI)
3469 00:43:11.522155 u1DelayCellOfst[2]=1 cells (1 PI)
3470 00:43:11.525554 u1DelayCellOfst[3]=0 cells (0 PI)
3471 00:43:11.525620 u1DelayCellOfst[4]=2 cells (2 PI)
3472 00:43:11.528889 u1DelayCellOfst[5]=6 cells (5 PI)
3473 00:43:11.532093 u1DelayCellOfst[6]=6 cells (5 PI)
3474 00:43:11.535572 u1DelayCellOfst[7]=3 cells (3 PI)
3475 00:43:11.539180 Byte0, DQ PI dly=983, DQM PI dly= 986
3476 00:43:11.542347 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 23)
3477 00:43:11.545940
3478 00:43:11.548856 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 23)
3479 00:43:11.548917
3480 00:43:11.552249 u1DelayCellOfst[8]=2 cells (2 PI)
3481 00:43:11.555681 u1DelayCellOfst[9]=2 cells (2 PI)
3482 00:43:11.559054 u1DelayCellOfst[10]=3 cells (3 PI)
3483 00:43:11.559121 u1DelayCellOfst[11]=5 cells (4 PI)
3484 00:43:11.562136 u1DelayCellOfst[12]=5 cells (4 PI)
3485 00:43:11.565446 u1DelayCellOfst[13]=5 cells (4 PI)
3486 00:43:11.569014 u1DelayCellOfst[14]=3 cells (3 PI)
3487 00:43:11.572122 u1DelayCellOfst[15]=0 cells (0 PI)
3488 00:43:11.575595 Byte1, DQ PI dly=976, DQM PI dly= 978
3489 00:43:11.582331 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 16)
3490 00:43:11.582399
3491 00:43:11.585509 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 16)
3492 00:43:11.585572
3493 00:43:11.588963 Write Rank1 MR14 =0x1a
3494 00:43:11.589034
3495 00:43:11.589090 Final TX Range 0 Vref 26
3496 00:43:11.589142
3497 00:43:11.595464 [TX_K_DQM_WITH_WDBI] Step1: K DQM with DBI_ON, and check DQM window spec.
3498 00:43:11.595592
3499 00:43:11.602317 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3500 00:43:11.609055 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3501 00:43:11.615545 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3502 00:43:11.618915 Write Rank1 MR3 =0xb0
3503 00:43:11.622226 DramC Write-DBI on
3504 00:43:11.622299 ==
3505 00:43:11.625392 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3506 00:43:11.628833 fsp= 1, odt_onoff= 1, Byte mode= 0
3507 00:43:11.628922 ==
3508 00:43:11.632198 [TxWindowPerbitCal] calType=1, VrefScanEnable 0
3509 00:43:11.632285
3510 00:43:11.635485 Begin, DQ Scan Range 698~762
3511 00:43:11.635547
3512 00:43:11.635602
3513 00:43:11.639068 TX Vref Scan disable
3514 00:43:11.642257 698 |2 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
3515 00:43:11.645500 699 |2 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
3516 00:43:11.648857 700 |2 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
3517 00:43:11.652186 701 |2 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
3518 00:43:11.655480 702 |2 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
3519 00:43:11.659033 703 |2 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
3520 00:43:11.662409 704 |2 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
3521 00:43:11.665818 705 |2 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
3522 00:43:11.668913 706 |2 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
3523 00:43:11.672329 707 |2 6 3|[0] xxxxxxxx oooooooo [MSB]
3524 00:43:11.675649 708 |2 6 4|[0] xxxxxxxx oooooooo [MSB]
3525 00:43:11.682150 709 |2 6 5|[0] xxxxxxxx oooooooo [MSB]
3526 00:43:11.686037 710 |2 6 6|[0] xxxxxxxx oooooooo [MSB]
3527 00:43:11.689095 711 |2 6 7|[0] xxxxxxxx oooooooo [MSB]
3528 00:43:11.692254 712 |2 6 8|[0] xxxxxxxx oooooooo [MSB]
3529 00:43:11.696210 713 |2 6 9|[0] xxxxxxxx oooooooo [MSB]
3530 00:43:11.699008 714 |2 6 10|[0] xxxxxxxx oooooooo [MSB]
3531 00:43:11.702468 715 |2 6 11|[0] xxxxxxxx oooooooo [MSB]
3532 00:43:11.705838 716 |2 6 12|[0] xxxxxxxx oooooooo [MSB]
3533 00:43:11.713194 736 |2 6 32|[0] oooooooo xxxxxxxx [MSB]
3534 00:43:11.716960 737 |2 6 33|[0] oooooooo xxxxxxxx [MSB]
3535 00:43:11.719873 738 |2 6 34|[0] oooooooo xxxxxxxx [MSB]
3536 00:43:11.723172 739 |2 6 35|[0] oooooooo xxxxxxxx [MSB]
3537 00:43:11.726511 740 |2 6 36|[0] oooooooo xxxxxxxx [MSB]
3538 00:43:11.729997 741 |2 6 37|[0] oooooooo xxxxxxxx [MSB]
3539 00:43:11.733116 742 |2 6 38|[0] oooooooo xxxxxxxx [MSB]
3540 00:43:11.736393 743 |2 6 39|[0] oooooooo xxxxxxxx [MSB]
3541 00:43:11.740326 744 |2 6 40|[0] xxxxxxxx xxxxxxxx [MSB]
3542 00:43:11.743173 Byte0, DQ PI dly=730, DQM PI dly= 730
3543 00:43:11.746589 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 26)
3544 00:43:11.746677
3545 00:43:11.753211 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 26)
3546 00:43:11.753283
3547 00:43:11.756666 Byte1, DQ PI dly=721, DQM PI dly= 721
3548 00:43:11.759980 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 17)
3549 00:43:11.760068
3550 00:43:11.763212 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 17)
3551 00:43:11.763279
3552 00:43:11.769835 Before -1MCK, ucdq_final_ui_large_dqs0 = 2, ucdq_final_ui_large_dqs1 = 2
3553 00:43:11.776566 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3554 00:43:11.786405 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3555 00:43:11.786477 Write Rank1 MR3 =0x30
3556 00:43:11.790325 DramC Write-DBI off
3557 00:43:11.790413
3558 00:43:11.790484 [DATLAT]
3559 00:43:11.793179 Freq=1600, CH1 RK1, use_rxtx_scan=0
3560 00:43:11.793267
3561 00:43:11.796601 DATLAT Default: 0x10
3562 00:43:11.796692 7, 0xFFFF, sum=0
3563 00:43:11.796777 8, 0xFFFF, sum=0
3564 00:43:11.799951 9, 0xFFFF, sum=0
3565 00:43:11.800046 10, 0xFFFF, sum=0
3566 00:43:11.803471 11, 0xFFFF, sum=0
3567 00:43:11.803559 12, 0xFFFF, sum=0
3568 00:43:11.806577 13, 0xFFFF, sum=0
3569 00:43:11.806642 14, 0x0, sum=1
3570 00:43:11.810160 15, 0x0, sum=2
3571 00:43:11.810288 16, 0x0, sum=3
3572 00:43:11.813110 17, 0x0, sum=4
3573 00:43:11.816518 pattern=2 first_step=14 total pass=5 best_step=16
3574 00:43:11.816579 ==
3575 00:43:11.819908 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3576 00:43:11.823201 fsp= 1, odt_onoff= 1, Byte mode= 0
3577 00:43:11.823262 ==
3578 00:43:11.829845 Start DQ dly to find pass range UseTestEngine =1
3579 00:43:11.833687 x-axis: bit #, y-axis: DQ dly (-127~63)
3580 00:43:11.833754 RX Vref Scan = 0
3581 00:43:11.836577 -26, [0] xxxxxxxx xxxxxxxx [MSB]
3582 00:43:11.840080 -25, [0] xxxxxxxx xxxxxxxx [MSB]
3583 00:43:11.843416 -24, [0] xxxxxxxx xxxxxxxx [MSB]
3584 00:43:11.846788 -23, [0] xxxxxxxx xxxxxxxx [MSB]
3585 00:43:11.850289 -22, [0] xxxxxxxx xxxxxxxx [MSB]
3586 00:43:11.853473 -21, [0] xxxxxxxx xxxxxxxx [MSB]
3587 00:43:11.853566 -20, [0] xxxxxxxx xxxxxxxx [MSB]
3588 00:43:11.857196 -19, [0] xxxxxxxx xxxxxxxx [MSB]
3589 00:43:11.860292 -18, [0] xxxxxxxx xxxxxxxx [MSB]
3590 00:43:11.863560 -17, [0] xxxxxxxx xxxxxxxx [MSB]
3591 00:43:11.866759 -16, [0] xxxxxxxx xxxxxxxx [MSB]
3592 00:43:11.870219 -15, [0] xxxxxxxx xxxxxxxx [MSB]
3593 00:43:11.873664 -14, [0] xxxxxxxx xxxxxxxx [MSB]
3594 00:43:11.876999 -13, [0] xxxxxxxx xxxxxxxx [MSB]
3595 00:43:11.877092 -12, [0] xxxxxxxx xxxxxxxx [MSB]
3596 00:43:11.880310 -11, [0] xxxxxxxx xxxxxxxx [MSB]
3597 00:43:11.883849 -10, [0] xxxxxxxx xxxxxxxx [MSB]
3598 00:43:11.887114 -9, [0] xxxxxxxx xxxxxxxx [MSB]
3599 00:43:11.890139 -8, [0] xxxxxxxx xxxxxxxx [MSB]
3600 00:43:11.893430 -7, [0] xxxxxxxx xxxxxxxx [MSB]
3601 00:43:11.896949 -6, [0] xxxxxxxx xxxxxxxx [MSB]
3602 00:43:11.897045 -5, [0] xxxxxxxx xxxxxxxx [MSB]
3603 00:43:11.900066 -4, [0] xxxxxxxx xxxxxxxx [MSB]
3604 00:43:11.903559 -3, [0] xxxxxxxx xxxxxxxx [MSB]
3605 00:43:11.906843 -2, [0] xxxoxxxx xxxxxxxo [MSB]
3606 00:43:11.910396 -1, [0] xxxoxxxx xxxxxxxo [MSB]
3607 00:43:11.913761 0, [0] xxooxxxx xxxxxxxo [MSB]
3608 00:43:11.913832 1, [0] xxooxxxx oooxxxxo [MSB]
3609 00:43:11.916792 2, [0] xxooxxxx ooooxxxo [MSB]
3610 00:43:11.920331 3, [0] xxoooxxo ooooxxxo [MSB]
3611 00:43:11.923915 4, [0] xxoooxxo ooooxooo [MSB]
3612 00:43:11.926953 5, [0] xxoooxxo oooooooo [MSB]
3613 00:43:11.930377 6, [0] xooooxxo oooooooo [MSB]
3614 00:43:11.930443 7, [0] ooooooxo oooooooo [MSB]
3615 00:43:11.935395 33, [0] oooxoooo ooooooox [MSB]
3616 00:43:11.938800 34, [0] oooxoooo ooooooox [MSB]
3617 00:43:11.941991 35, [0] ooxxoooo ooooooox [MSB]
3618 00:43:11.945337 36, [0] ooxxoooo ooxoooox [MSB]
3619 00:43:11.948752 37, [0] ooxxoooo xxxxooox [MSB]
3620 00:43:11.952272 38, [0] ooxxxoox xxxxooxx [MSB]
3621 00:43:11.952345 39, [0] ooxxxoox xxxxoxxx [MSB]
3622 00:43:11.955615 40, [0] ooxxxoox xxxxxxxx [MSB]
3623 00:43:11.959286 41, [0] ooxxxxox xxxxxxxx [MSB]
3624 00:43:11.962488 42, [0] oxxxxxox xxxxxxxx [MSB]
3625 00:43:11.965590 43, [0] xxxxxxxx xxxxxxxx [MSB]
3626 00:43:11.969105 iDelay=43, Bit 0, Center 24 (7 ~ 42) 36
3627 00:43:11.972206 iDelay=43, Bit 1, Center 23 (6 ~ 41) 36
3628 00:43:11.975570 iDelay=43, Bit 2, Center 17 (0 ~ 34) 35
3629 00:43:11.978882 iDelay=43, Bit 3, Center 15 (-2 ~ 32) 35
3630 00:43:11.982325 iDelay=43, Bit 4, Center 20 (3 ~ 37) 35
3631 00:43:11.985511 iDelay=43, Bit 5, Center 23 (7 ~ 40) 34
3632 00:43:11.989100 iDelay=43, Bit 6, Center 25 (8 ~ 42) 35
3633 00:43:11.992443 iDelay=43, Bit 7, Center 20 (3 ~ 37) 35
3634 00:43:11.995757 iDelay=43, Bit 8, Center 18 (1 ~ 36) 36
3635 00:43:11.999196 iDelay=43, Bit 9, Center 18 (1 ~ 36) 36
3636 00:43:12.005596 iDelay=43, Bit 10, Center 18 (1 ~ 35) 35
3637 00:43:12.009228 iDelay=43, Bit 11, Center 19 (2 ~ 36) 35
3638 00:43:12.012430 iDelay=43, Bit 12, Center 22 (5 ~ 39) 35
3639 00:43:12.015601 iDelay=43, Bit 13, Center 21 (4 ~ 38) 35
3640 00:43:12.018945 iDelay=43, Bit 14, Center 20 (4 ~ 37) 34
3641 00:43:12.022392 iDelay=43, Bit 15, Center 15 (-2 ~ 32) 35
3642 00:43:12.022463 ==
3643 00:43:12.029008 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3644 00:43:12.029081 fsp= 1, odt_onoff= 1, Byte mode= 0
3645 00:43:12.032428 ==
3646 00:43:12.032491 DQS Delay:
3647 00:43:12.032550 DQS0 = 0, DQS1 = 0
3648 00:43:12.035717 DQM Delay:
3649 00:43:12.035780 DQM0 = 20, DQM1 = 18
3650 00:43:12.039435 DQ Delay:
3651 00:43:12.039505 DQ0 =24, DQ1 =23, DQ2 =17, DQ3 =15
3652 00:43:12.042467 DQ4 =20, DQ5 =23, DQ6 =25, DQ7 =20
3653 00:43:12.045735 DQ8 =18, DQ9 =18, DQ10 =18, DQ11 =19
3654 00:43:12.049226 DQ12 =22, DQ13 =21, DQ14 =20, DQ15 =15
3655 00:43:12.049296
3656 00:43:12.052634
3657 00:43:12.052697
3658 00:43:12.052756 [DramC_TX_OE_Calibration] TA2
3659 00:43:12.055807 Original DQ_B0 (3 6) =30, OEN = 27
3660 00:43:12.059157 Original DQ_B1 (3 6) =30, OEN = 27
3661 00:43:12.062712 23, 0x0, End_B0=23 End_B1=23
3662 00:43:12.065887 24, 0x0, End_B0=24 End_B1=24
3663 00:43:12.069110 25, 0x0, End_B0=25 End_B1=25
3664 00:43:12.069175 26, 0x0, End_B0=26 End_B1=26
3665 00:43:12.072666 27, 0x0, End_B0=27 End_B1=27
3666 00:43:12.076036 28, 0x0, End_B0=28 End_B1=28
3667 00:43:12.079011 29, 0x0, End_B0=29 End_B1=29
3668 00:43:12.079076 30, 0x0, End_B0=30 End_B1=30
3669 00:43:12.083009 31, 0xFFFF, End_B0=30 End_B1=30
3670 00:43:12.089501 Byte0 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
3671 00:43:12.095846 Byte1 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
3672 00:43:12.095918
3673 00:43:12.095975
3674 00:43:12.096035 Write Rank1 MR23 =0x3f
3675 00:43:12.099297 [DQSOSC]
3676 00:43:12.106094 [DQSOSCAuto] RK1, (LSB)MR18= 0xa5, (MSB)MR19= 0x3, tDQSOscB0 = 337 ps tDQSOscB1 = 0 ps
3677 00:43:12.109662 CH1_RK1: MR19=0x3, MR18=0xA5, DQSOSC=337, MR23=63, INC=21, DEC=32
3678 00:43:12.113048 Write Rank1 MR23 =0x3f
3679 00:43:12.113110 [DQSOSC]
3680 00:43:12.122804 [DQSOSCAuto] RK1, (LSB)MR18= 0xa4, (MSB)MR19= 0x3, tDQSOscB0 = 337 ps tDQSOscB1 = 0 ps
3681 00:43:12.122874 CH1 RK1: MR19=3, MR18=A4
3682 00:43:12.126121 [RxdqsGatingPostProcess] freq 1600
3683 00:43:12.133160 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
3684 00:43:12.133234 Rank: 0
3685 00:43:12.136472 best DQS0 dly(2T, 0.5T) = (2, 5)
3686 00:43:12.139845 best DQS1 dly(2T, 0.5T) = (2, 5)
3687 00:43:12.143227 best DQS0 P1 dly(2T, 0.5T) = (3, 1)
3688 00:43:12.146479 best DQS1 P1 dly(2T, 0.5T) = (3, 1)
3689 00:43:12.146542 Rank: 1
3690 00:43:12.149702 best DQS0 dly(2T, 0.5T) = (2, 5)
3691 00:43:12.153033 best DQS1 dly(2T, 0.5T) = (2, 5)
3692 00:43:12.156790 best DQS0 P1 dly(2T, 0.5T) = (3, 1)
3693 00:43:12.159840 best DQS1 P1 dly(2T, 0.5T) = (3, 1)
3694 00:43:12.163490 TX_dly_DQSgated check: min 2 max 3, ChangeDQSINCTL=-1
3695 00:43:12.166643 DQSINCTL=5, RANKINCTL=3, u4XRTR2R=9
3696 00:43:12.169999 [DualRankRxdatlatCal] RK0: 16, RK1: 16, Final_Datlat 16
3697 00:43:12.173522
3698 00:43:12.173588
3699 00:43:12.176766 [Calibration Summary] Freqency 1600
3700 00:43:12.176825 CH 0, Rank 0
3701 00:43:12.176877 All Pass.
3702 00:43:12.176926
3703 00:43:12.180142 CH 0, Rank 1
3704 00:43:12.180199 All Pass.
3705 00:43:12.180249
3706 00:43:12.180298 CH 1, Rank 0
3707 00:43:12.183193 All Pass.
3708 00:43:12.183250
3709 00:43:12.183307 CH 1, Rank 1
3710 00:43:12.183355 All Pass.
3711 00:43:12.183403
3712 00:43:12.189849 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3713 00:43:12.196702 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3714 00:43:12.203387 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3715 00:43:12.206793 Write Rank0 MR3 =0xb0
3716 00:43:12.213422 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3717 00:43:12.220086 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3718 00:43:12.226809 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3719 00:43:12.230133 Write Rank1 MR3 =0xb0
3720 00:43:12.236575 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3721 00:43:12.243251 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3722 00:43:12.250321 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3723 00:43:12.253359 Write Rank0 MR3 =0xb0
3724 00:43:12.256790 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3725 00:43:12.266605 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3726 00:43:12.273556 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3727 00:43:12.273628 Write Rank1 MR3 =0xb0
3728 00:43:12.276699 DramC Write-DBI on
3729 00:43:12.280008 [GetDramInforAfterCalByMRR] Vendor 1.
3730 00:43:12.283614 [GetDramInforAfterCalByMRR] Revision 7.
3731 00:43:12.283679 MR8 12
3732 00:43:12.286810 CH0, RK0, DieNum 1, Density 80000000, RKsize 80000000.
3733 00:43:12.290009 MR8 12
3734 00:43:12.293461 CH0, RK1, DieNum 1, Density 80000000, RKsize 80000000.
3735 00:43:12.293534 MR8 12
3736 00:43:12.300704 CH1, RK0, DieNum 1, Density 80000000, RKsize 80000000.
3737 00:43:12.300776 MR8 12
3738 00:43:12.303498 CH1, RK1, DieNum 1, Density 80000000, RKsize 80000000.
3739 00:43:12.313637 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 119, TRFCpb 44, TRFCpb_05T 0
3740 00:43:12.316968 Write Rank0 MR13 =0xd0
3741 00:43:12.317041 Write Rank1 MR13 =0xd0
3742 00:43:12.320307 Write Rank0 MR13 =0xd0
3743 00:43:12.323514 Write Rank1 MR13 =0xd0
3744 00:43:12.323580 Save calibration result to emmc
3745 00:43:12.323636
3746 00:43:12.326896
3747 00:43:12.330415 [DramcModeReg_Check] Freq_1600, FSP_1
3748 00:43:12.330478 FSP_1, CH_0, RK0
3749 00:43:12.333612 Write Rank0 MR13 =0xd8
3750 00:43:12.336748 MR12 = 0x56 (global = 0x56) match
3751 00:43:12.340217 MR14 = 0x18 (global = 0x18) match
3752 00:43:12.340283 FSP_1, CH_0, RK1
3753 00:43:12.343656 Write Rank1 MR13 =0xd8
3754 00:43:12.346897 MR12 = 0x56 (global = 0x56) match
3755 00:43:12.350258 MR14 = 0x18 (global = 0x18) match
3756 00:43:12.350340 FSP_1, CH_1, RK0
3757 00:43:12.353598 Write Rank0 MR13 =0xd8
3758 00:43:12.356861 MR12 = 0x58 (global = 0x58) match
3759 00:43:12.360386 MR14 = 0x18 (global = 0x18) match
3760 00:43:12.360453 FSP_1, CH_1, RK1
3761 00:43:12.363649 Write Rank1 MR13 =0xd8
3762 00:43:12.367091 MR12 = 0x58 (global = 0x58) match
3763 00:43:12.370200 MR14 = 0x1a (global = 0x1a) match
3764 00:43:12.370287
3765 00:43:12.374061 [MEM_TEST] 02: After DFS, before run time config
3766 00:43:12.384118 [MEM_TEST] Rank 0 OK.(uiFixedAddr 0x40000000, Pass count =16384, Fail count =0)
3767 00:43:12.384192
3768 00:43:12.384250 [TA2_TEST]
3769 00:43:12.384302 === TA2 HW
3770 00:43:12.387667 TA2 PAT: XTALK
3771 00:43:12.390790 HW channel(0) Rank(0), TA2 pass, pass_cnt:1, err_cnt:0
3772 00:43:12.397160 HW channel(0) Rank(1), TA2 pass, pass_cnt:2, err_cnt:0
3773 00:43:12.400478 HW channel(1) Rank(0), TA2 pass, pass_cnt:3, err_cnt:0
3774 00:43:12.404394 HW channel(1) Rank(1), TA2 pass, pass_cnt:4, err_cnt:0
3775 00:43:12.407330
3776 00:43:12.407403
3777 00:43:12.407460 Settings after calibration
3778 00:43:12.407513
3779 00:43:12.410543 [DramcRunTimeConfig]
3780 00:43:12.414131 TransferPLLToSPMControl - MODE SW PHYPLL
3781 00:43:12.414198 TX_TRACKING: ON
3782 00:43:12.417445 RX_TRACKING: ON
3783 00:43:12.417511 HW_GATING: ON
3784 00:43:12.420835 HW_GATING DBG: OFF
3785 00:43:12.420901 ddr_geometry:1
3786 00:43:12.423849 ddr_geometry:1
3787 00:43:12.423918 ddr_geometry:1
3788 00:43:12.423972 ddr_geometry:1
3789 00:43:12.427412 ddr_geometry:1
3790 00:43:12.427475 ddr_geometry:1
3791 00:43:12.430824 ddr_geometry:1
3792 00:43:12.430886 ddr_geometry:1
3793 00:43:12.434003 High Freq DUMMY_READ_FOR_TRACKING: ON
3794 00:43:12.437639 ZQCS_ENABLE_LP4: OFF
3795 00:43:12.440720 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
3796 00:43:12.443974 DUMMY_READ_FOR_DQS_GATING_RETRY: OFF
3797 00:43:12.444046 SPM_CONTROL_AFTERK: ON
3798 00:43:12.447161 IMPEDANCE_TRACKING: ON
3799 00:43:12.447228 TEMP_SENSOR: ON
3800 00:43:12.450684 PER_BANK_REFRESH: ON
3801 00:43:12.450750 HW_SAVE_FOR_SR: ON
3802 00:43:12.454062 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3803 00:43:12.457298 CLK_FREE_FUN_FOR_DRAMC_PSEL: ON
3804 00:43:12.460761 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: ON
3805 00:43:12.464259 Read ODT Tracking: ON
3806 00:43:12.467884 =========================
3807 00:43:12.467953
3808 00:43:12.468009 [TA2_TEST]
3809 00:43:12.468062 === TA2 HW
3810 00:43:12.474165 HW channel(0) Rank(0), TA2 pass, pass_cnt:5, err_cnt:0
3811 00:43:12.477344 HW channel(0) Rank(1), TA2 pass, pass_cnt:6, err_cnt:0
3812 00:43:12.483885 HW channel(1) Rank(0), TA2 pass, pass_cnt:7, err_cnt:0
3813 00:43:12.487355 HW channel(1) Rank(1), TA2 pass, pass_cnt:8, err_cnt:0
3814 00:43:12.487431
3815 00:43:12.490585 [MEM_TEST] 03: After run time config
3816 00:43:12.501859 [MEM_TEST] Rank 0 OK.(uiFixedAddr 0x40000000, Pass count =16384, Fail count =0)
3817 00:43:12.505103 [complex_mem_test] start addr:0x40024000, len:131072
3818 00:43:12.709429 1st complex R/W mem test pass
3819 00:43:12.715891 save_calibration_params with freq_sel:1, frequency:1600, _MappingFreqArray:0
3820 00:43:12.719318 sync preloader write leveling
3821 00:43:12.722640 sync preloader cbt_mr12
3822 00:43:12.722716 sync preloader cbt_clk_dly
3823 00:43:12.726046 sync preloader cbt_cmd_dly
3824 00:43:12.729458 sync preloader cbt_cs
3825 00:43:12.732936 sync preloader cbt_ca_perbit_delay
3826 00:43:12.732999 sync preloader clk_delay
3827 00:43:12.736502 sync preloader dqs_delay
3828 00:43:12.739341 sync preloader u1Gating2T_Save
3829 00:43:12.743185 sync preloader u1Gating05T_Save
3830 00:43:12.746373 sync preloader u1Gatingfine_tune_Save
3831 00:43:12.749267 sync preloader u1Gatingucpass_count_Save
3832 00:43:12.752864 sync preloader u1TxWindowPerbitVref_Save
3833 00:43:12.756063 sync preloader u1TxCenter_min_Save
3834 00:43:12.759364 sync preloader u1TxCenter_max_Save
3835 00:43:12.762823 sync preloader u1Txwin_center_Save
3836 00:43:12.765845 sync preloader u1Txfirst_pass_Save
3837 00:43:12.769600 sync preloader u1Txlast_pass_Save
3838 00:43:12.769676 sync preloader u1RxDatlat_Save
3839 00:43:12.772798 sync preloader u1RxWinPerbitVref_Save
3840 00:43:12.779430 sync preloader u1RxWinPerbitDQ_firsbypass_Save
3841 00:43:12.782871 sync preloader u1RxWinPerbitDQ_lastbypass_Save
3842 00:43:12.786065 sync preloader delay_cell_unit
3843 00:43:12.792694 save_calibration_params with freq_sel:3, frequency:1200, _MappingFreqArray:1
3844 00:43:12.796107 sync preloader write leveling
3845 00:43:12.796179 sync preloader cbt_mr12
3846 00:43:12.799432 sync preloader cbt_clk_dly
3847 00:43:12.802948 sync preloader cbt_cmd_dly
3848 00:43:12.803014 sync preloader cbt_cs
3849 00:43:12.806111 sync preloader cbt_ca_perbit_delay
3850 00:43:12.809471 sync preloader clk_delay
3851 00:43:12.809533 sync preloader dqs_delay
3852 00:43:12.812802 sync preloader u1Gating2T_Save
3853 00:43:12.816307 sync preloader u1Gating05T_Save
3854 00:43:12.819517 sync preloader u1Gatingfine_tune_Save
3855 00:43:12.823113 sync preloader u1Gatingucpass_count_Save
3856 00:43:12.826096 sync preloader u1TxWindowPerbitVref_Save
3857 00:43:12.829520 sync preloader u1TxCenter_min_Save
3858 00:43:12.832936 sync preloader u1TxCenter_max_Save
3859 00:43:12.836061 sync preloader u1Txwin_center_Save
3860 00:43:12.839540 sync preloader u1Txfirst_pass_Save
3861 00:43:12.843233 sync preloader u1Txlast_pass_Save
3862 00:43:12.846047 sync preloader u1RxDatlat_Save
3863 00:43:12.849400 sync preloader u1RxWinPerbitVref_Save
3864 00:43:12.853264 sync preloader u1RxWinPerbitDQ_firsbypass_Save
3865 00:43:12.856181 sync preloader u1RxWinPerbitDQ_lastbypass_Save
3866 00:43:12.859454 sync preloader delay_cell_unit
3867 00:43:12.866166 save_calibration_params with freq_sel:5, frequency:800, _MappingFreqArray:2
3868 00:43:12.869632 sync preloader write leveling
3869 00:43:12.872927 sync preloader cbt_mr12
3870 00:43:12.873002 sync preloader cbt_clk_dly
3871 00:43:12.876280 sync preloader cbt_cmd_dly
3872 00:43:12.879619 sync preloader cbt_cs
3873 00:43:12.879694 sync preloader cbt_ca_perbit_delay
3874 00:43:12.882950 sync preloader clk_delay
3875 00:43:12.886505 sync preloader dqs_delay
3876 00:43:12.889748 sync preloader u1Gating2T_Save
3877 00:43:12.889821 sync preloader u1Gating05T_Save
3878 00:43:12.896411 sync preloader u1Gatingfine_tune_Save
3879 00:43:12.899718 sync preloader u1Gatingucpass_count_Save
3880 00:43:12.903049 sync preloader u1TxWindowPerbitVref_Save
3881 00:43:12.906700 sync preloader u1TxCenter_min_Save
3882 00:43:12.909721 sync preloader u1TxCenter_max_Save
3883 00:43:12.909789 sync preloader u1Txwin_center_Save
3884 00:43:12.912868 sync preloader u1Txfirst_pass_Save
3885 00:43:12.916245 sync preloader u1Txlast_pass_Save
3886 00:43:12.919758 sync preloader u1RxDatlat_Save
3887 00:43:12.922947 sync preloader u1RxWinPerbitVref_Save
3888 00:43:12.926402 sync preloader u1RxWinPerbitDQ_firsbypass_Save
3889 00:43:12.933026 sync preloader u1RxWinPerbitDQ_lastbypass_Save
3890 00:43:12.933093 sync preloader delay_cell_unit
3891 00:43:12.939634 just_for_test_dump_coreboot_params dump all params
3892 00:43:12.939702 dump source = 0x0
3893 00:43:12.943026 dump params frequency:1600
3894 00:43:12.946190 dump params rank number:2
3895 00:43:12.946291
3896 00:43:12.949654 dump params write leveling
3897 00:43:12.949720 write leveling[0][0][0] = 0x21
3898 00:43:12.953090 write leveling[0][0][1] = 0x1c
3899 00:43:12.956582 write leveling[0][1][0] = 0x23
3900 00:43:12.959843 write leveling[0][1][1] = 0x1e
3901 00:43:12.962889 write leveling[1][0][0] = 0x25
3902 00:43:12.962956 write leveling[1][0][1] = 0x21
3903 00:43:12.966341 write leveling[1][1][0] = 0x25
3904 00:43:12.969577 write leveling[1][1][1] = 0x1f
3905 00:43:12.972835 dump params cbt_cs
3906 00:43:12.972906 cbt_cs[0][0] = 0x8
3907 00:43:12.976361 cbt_cs[0][1] = 0x8
3908 00:43:12.976427 cbt_cs[1][0] = 0xc
3909 00:43:12.979916 cbt_cs[1][1] = 0xc
3910 00:43:12.979987 dump params cbt_mr12
3911 00:43:12.982962 cbt_mr12[0][0] = 0x16
3912 00:43:12.983025 cbt_mr12[0][1] = 0x16
3913 00:43:12.986450 cbt_mr12[1][0] = 0x18
3914 00:43:12.990078 cbt_mr12[1][1] = 0x18
3915 00:43:12.990147 dump params tx window
3916 00:43:12.993248 tx_center_min[0][0][0] = 980
3917 00:43:12.996433 tx_center_max[0][0][0] = 987
3918 00:43:12.999957 tx_center_min[0][0][1] = 975
3919 00:43:13.000028 tx_center_max[0][0][1] = 979
3920 00:43:13.002931 tx_center_min[0][1][0] = 982
3921 00:43:13.006548 tx_center_max[0][1][0] = 989
3922 00:43:13.009813 tx_center_min[0][1][1] = 978
3923 00:43:13.013137 tx_center_max[0][1][1] = 984
3924 00:43:13.013203 tx_center_min[1][0][0] = 983
3925 00:43:13.016421 tx_center_max[1][0][0] = 989
3926 00:43:13.019731 tx_center_min[1][0][1] = 980
3927 00:43:13.023004 tx_center_max[1][0][1] = 983
3928 00:43:13.023071 tx_center_min[1][1][0] = 983
3929 00:43:13.026539 tx_center_max[1][1][0] = 989
3930 00:43:13.029913 tx_center_min[1][1][1] = 976
3931 00:43:13.033478 tx_center_max[1][1][1] = 980
3932 00:43:13.033542 dump params tx window
3933 00:43:13.036472 tx_win_center[0][0][0] = 987
3934 00:43:13.039898 tx_first_pass[0][0][0] = 975
3935 00:43:13.043224 tx_last_pass[0][0][0] = 999
3936 00:43:13.043288 tx_win_center[0][0][1] = 986
3937 00:43:13.046514 tx_first_pass[0][0][1] = 975
3938 00:43:13.049871 tx_last_pass[0][0][1] = 998
3939 00:43:13.053387 tx_win_center[0][0][2] = 986
3940 00:43:13.056668 tx_first_pass[0][0][2] = 975
3941 00:43:13.056729 tx_last_pass[0][0][2] = 998
3942 00:43:13.059985 tx_win_center[0][0][3] = 980
3943 00:43:13.063199 tx_first_pass[0][0][3] = 968
3944 00:43:13.066617 tx_last_pass[0][0][3] = 992
3945 00:43:13.066680 tx_win_center[0][0][4] = 986
3946 00:43:13.069902 tx_first_pass[0][0][4] = 975
3947 00:43:13.073454 tx_last_pass[0][0][4] = 998
3948 00:43:13.076963 tx_win_center[0][0][5] = 981
3949 00:43:13.080297 tx_first_pass[0][0][5] = 970
3950 00:43:13.080364 tx_last_pass[0][0][5] = 993
3951 00:43:13.083495 tx_win_center[0][0][6] = 982
3952 00:43:13.086954 tx_first_pass[0][0][6] = 970
3953 00:43:13.090572 tx_last_pass[0][0][6] = 995
3954 00:43:13.090635 tx_win_center[0][0][7] = 983
3955 00:43:13.093556 tx_first_pass[0][0][7] = 971
3956 00:43:13.096848 tx_last_pass[0][0][7] = 996
3957 00:43:13.100312 tx_win_center[0][0][8] = 976
3958 00:43:13.100390 tx_first_pass[0][0][8] = 963
3959 00:43:13.103856 tx_last_pass[0][0][8] = 989
3960 00:43:13.107331 tx_win_center[0][0][9] = 977
3961 00:43:13.110179 tx_first_pass[0][0][9] = 965
3962 00:43:13.110279 tx_last_pass[0][0][9] = 989
3963 00:43:13.113866 tx_win_center[0][0][10] = 979
3964 00:43:13.117164 tx_first_pass[0][0][10] = 968
3965 00:43:13.120481 tx_last_pass[0][0][10] = 991
3966 00:43:13.123943 tx_win_center[0][0][11] = 976
3967 00:43:13.127099 tx_first_pass[0][0][11] = 963
3968 00:43:13.127165 tx_last_pass[0][0][11] = 989
3969 00:43:13.130601 tx_win_center[0][0][12] = 977
3970 00:43:13.133770 tx_first_pass[0][0][12] = 965
3971 00:43:13.137045 tx_last_pass[0][0][12] = 989
3972 00:43:13.137107 tx_win_center[0][0][13] = 975
3973 00:43:13.140365 tx_first_pass[0][0][13] = 963
3974 00:43:13.144238 tx_last_pass[0][0][13] = 988
3975 00:43:13.147159 tx_win_center[0][0][14] = 976
3976 00:43:13.150347 tx_first_pass[0][0][14] = 964
3977 00:43:13.153828 tx_last_pass[0][0][14] = 989
3978 00:43:13.153887 tx_win_center[0][0][15] = 978
3979 00:43:13.156928 tx_first_pass[0][0][15] = 966
3980 00:43:13.160741 tx_last_pass[0][0][15] = 990
3981 00:43:13.163723 tx_win_center[0][1][0] = 989
3982 00:43:13.163792 tx_first_pass[0][1][0] = 977
3983 00:43:13.167144 tx_last_pass[0][1][0] = 1002
3984 00:43:13.170297 tx_win_center[0][1][1] = 988
3985 00:43:13.173789 tx_first_pass[0][1][1] = 976
3986 00:43:13.176989 tx_last_pass[0][1][1] = 1000
3987 00:43:13.177059 tx_win_center[0][1][2] = 988
3988 00:43:13.180385 tx_first_pass[0][1][2] = 976
3989 00:43:13.183593 tx_last_pass[0][1][2] = 1000
3990 00:43:13.186976 tx_win_center[0][1][3] = 982
3991 00:43:13.190321 tx_first_pass[0][1][3] = 970
3992 00:43:13.190390 tx_last_pass[0][1][3] = 994
3993 00:43:13.193772 tx_win_center[0][1][4] = 988
3994 00:43:13.197082 tx_first_pass[0][1][4] = 976
3995 00:43:13.200607 tx_last_pass[0][1][4] = 1001
3996 00:43:13.200681 tx_win_center[0][1][5] = 983
3997 00:43:13.203756 tx_first_pass[0][1][5] = 971
3998 00:43:13.207111 tx_last_pass[0][1][5] = 995
3999 00:43:13.210332 tx_win_center[0][1][6] = 984
4000 00:43:13.213685 tx_first_pass[0][1][6] = 972
4001 00:43:13.213751 tx_last_pass[0][1][6] = 997
4002 00:43:13.217052 tx_win_center[0][1][7] = 986
4003 00:43:13.220355 tx_first_pass[0][1][7] = 975
4004 00:43:13.224510 tx_last_pass[0][1][7] = 998
4005 00:43:13.224578 tx_win_center[0][1][8] = 978
4006 00:43:13.226977 tx_first_pass[0][1][8] = 966
4007 00:43:13.230434 tx_last_pass[0][1][8] = 990
4008 00:43:13.233936 tx_win_center[0][1][9] = 979
4009 00:43:13.237010 tx_first_pass[0][1][9] = 967
4010 00:43:13.237072 tx_last_pass[0][1][9] = 991
4011 00:43:13.240633 tx_win_center[0][1][10] = 984
4012 00:43:13.243800 tx_first_pass[0][1][10] = 973
4013 00:43:13.247356 tx_last_pass[0][1][10] = 996
4014 00:43:13.247421 tx_win_center[0][1][11] = 979
4015 00:43:13.250491 tx_first_pass[0][1][11] = 967
4016 00:43:13.254059 tx_last_pass[0][1][11] = 991
4017 00:43:13.257268 tx_win_center[0][1][12] = 979
4018 00:43:13.260820 tx_first_pass[0][1][12] = 968
4019 00:43:13.260878 tx_last_pass[0][1][12] = 991
4020 00:43:13.264012 tx_win_center[0][1][13] = 978
4021 00:43:13.267170 tx_first_pass[0][1][13] = 967
4022 00:43:13.270630 tx_last_pass[0][1][13] = 990
4023 00:43:13.273937 tx_win_center[0][1][14] = 979
4024 00:43:13.274006 tx_first_pass[0][1][14] = 967
4025 00:43:13.277662 tx_last_pass[0][1][14] = 991
4026 00:43:13.281149 tx_win_center[0][1][15] = 980
4027 00:43:13.284104 tx_first_pass[0][1][15] = 969
4028 00:43:13.287415 tx_last_pass[0][1][15] = 992
4029 00:43:13.287473 tx_win_center[1][0][0] = 989
4030 00:43:13.290597 tx_first_pass[1][0][0] = 977
4031 00:43:13.294150 tx_last_pass[1][0][0] = 1001
4032 00:43:13.297425 tx_win_center[1][0][1] = 987
4033 00:43:13.300748 tx_first_pass[1][0][1] = 976
4034 00:43:13.300822 tx_last_pass[1][0][1] = 999
4035 00:43:13.304293 tx_win_center[1][0][2] = 985
4036 00:43:13.307398 tx_first_pass[1][0][2] = 974
4037 00:43:13.310919 tx_last_pass[1][0][2] = 997
4038 00:43:13.310985 tx_win_center[1][0][3] = 983
4039 00:43:13.314047 tx_first_pass[1][0][3] = 971
4040 00:43:13.317614 tx_last_pass[1][0][3] = 995
4041 00:43:13.320877 tx_win_center[1][0][4] = 986
4042 00:43:13.320973 tx_first_pass[1][0][4] = 975
4043 00:43:13.324486 tx_last_pass[1][0][4] = 998
4044 00:43:13.327556 tx_win_center[1][0][5] = 987
4045 00:43:13.330852 tx_first_pass[1][0][5] = 976
4046 00:43:13.334304 tx_last_pass[1][0][5] = 999
4047 00:43:13.334381 tx_win_center[1][0][6] = 988
4048 00:43:13.337706 tx_first_pass[1][0][6] = 977
4049 00:43:13.340888 tx_last_pass[1][0][6] = 1000
4050 00:43:13.344356 tx_win_center[1][0][7] = 986
4051 00:43:13.344425 tx_first_pass[1][0][7] = 975
4052 00:43:13.347583 tx_last_pass[1][0][7] = 998
4053 00:43:13.351142 tx_win_center[1][0][8] = 980
4054 00:43:13.354416 tx_first_pass[1][0][8] = 969
4055 00:43:13.357747 tx_last_pass[1][0][8] = 992
4056 00:43:13.357847 tx_win_center[1][0][9] = 980
4057 00:43:13.361157 tx_first_pass[1][0][9] = 969
4058 00:43:13.364580 tx_last_pass[1][0][9] = 992
4059 00:43:13.367655 tx_win_center[1][0][10] = 981
4060 00:43:13.367728 tx_first_pass[1][0][10] = 969
4061 00:43:13.371149 tx_last_pass[1][0][10] = 994
4062 00:43:13.374427 tx_win_center[1][0][11] = 982
4063 00:43:13.377777 tx_first_pass[1][0][11] = 971
4064 00:43:13.380995 tx_last_pass[1][0][11] = 994
4065 00:43:13.381055 tx_win_center[1][0][12] = 983
4066 00:43:13.384581 tx_first_pass[1][0][12] = 971
4067 00:43:13.387732 tx_last_pass[1][0][12] = 995
4068 00:43:13.391070 tx_win_center[1][0][13] = 982
4069 00:43:13.394442 tx_first_pass[1][0][13] = 971
4070 00:43:13.394504 tx_last_pass[1][0][13] = 994
4071 00:43:13.397744 tx_win_center[1][0][14] = 981
4072 00:43:13.401062 tx_first_pass[1][0][14] = 970
4073 00:43:13.404785 tx_last_pass[1][0][14] = 993
4074 00:43:13.407699 tx_win_center[1][0][15] = 980
4075 00:43:13.407765 tx_first_pass[1][0][15] = 968
4076 00:43:13.411078 tx_last_pass[1][0][15] = 992
4077 00:43:13.414336 tx_win_center[1][1][0] = 989
4078 00:43:13.417538 tx_first_pass[1][1][0] = 976
4079 00:43:13.421131 tx_last_pass[1][1][0] = 1002
4080 00:43:13.421231 tx_win_center[1][1][1] = 987
4081 00:43:13.424441 tx_first_pass[1][1][1] = 975
4082 00:43:13.427951 tx_last_pass[1][1][1] = 999
4083 00:43:13.431291 tx_win_center[1][1][2] = 984
4084 00:43:13.431365 tx_first_pass[1][1][2] = 971
4085 00:43:13.434653 tx_last_pass[1][1][2] = 997
4086 00:43:13.438155 tx_win_center[1][1][3] = 983
4087 00:43:13.441251 tx_first_pass[1][1][3] = 970
4088 00:43:13.444722 tx_last_pass[1][1][3] = 997
4089 00:43:13.444797 tx_win_center[1][1][4] = 985
4090 00:43:13.448044 tx_first_pass[1][1][4] = 973
4091 00:43:13.451361 tx_last_pass[1][1][4] = 998
4092 00:43:13.454410 tx_win_center[1][1][5] = 988
4093 00:43:13.454485 tx_first_pass[1][1][5] = 976
4094 00:43:13.458136 tx_last_pass[1][1][5] = 1000
4095 00:43:13.461187 tx_win_center[1][1][6] = 988
4096 00:43:13.464503 tx_first_pass[1][1][6] = 976
4097 00:43:13.467856 tx_last_pass[1][1][6] = 1001
4098 00:43:13.467933 tx_win_center[1][1][7] = 986
4099 00:43:13.471285 tx_first_pass[1][1][7] = 974
4100 00:43:13.474699 tx_last_pass[1][1][7] = 998
4101 00:43:13.478143 tx_win_center[1][1][8] = 978
4102 00:43:13.478217 tx_first_pass[1][1][8] = 965
4103 00:43:13.481627 tx_last_pass[1][1][8] = 991
4104 00:43:13.484779 tx_win_center[1][1][9] = 978
4105 00:43:13.488126 tx_first_pass[1][1][9] = 965
4106 00:43:13.488187 tx_last_pass[1][1][9] = 991
4107 00:43:13.491266 tx_win_center[1][1][10] = 979
4108 00:43:13.494717 tx_first_pass[1][1][10] = 967
4109 00:43:13.498101 tx_last_pass[1][1][10] = 991
4110 00:43:13.501566 tx_win_center[1][1][11] = 980
4111 00:43:13.504881 tx_first_pass[1][1][11] = 968
4112 00:43:13.504950 tx_last_pass[1][1][11] = 992
4113 00:43:13.508740 tx_win_center[1][1][12] = 980
4114 00:43:13.511686 tx_first_pass[1][1][12] = 969
4115 00:43:13.514965 tx_last_pass[1][1][12] = 992
4116 00:43:13.515033 tx_win_center[1][1][13] = 980
4117 00:43:13.518126 tx_first_pass[1][1][13] = 968
4118 00:43:13.521574 tx_last_pass[1][1][13] = 992
4119 00:43:13.524920 tx_win_center[1][1][14] = 979
4120 00:43:13.528128 tx_first_pass[1][1][14] = 967
4121 00:43:13.528196 tx_last_pass[1][1][14] = 991
4122 00:43:13.531515 tx_win_center[1][1][15] = 976
4123 00:43:13.534889 tx_first_pass[1][1][15] = 963
4124 00:43:13.538329 tx_last_pass[1][1][15] = 990
4125 00:43:13.538397 dump params rx window
4126 00:43:13.541343 rx_firspass[0][0][0] = 8
4127 00:43:13.544669 rx_lastpass[0][0][0] = 40
4128 00:43:13.548054 rx_firspass[0][0][1] = 6
4129 00:43:13.548122 rx_lastpass[0][0][1] = 39
4130 00:43:13.551668 rx_firspass[0][0][2] = 8
4131 00:43:13.554625 rx_lastpass[0][0][2] = 38
4132 00:43:13.554691 rx_firspass[0][0][3] = -4
4133 00:43:13.558037 rx_lastpass[0][0][3] = 29
4134 00:43:13.561171 rx_firspass[0][0][4] = 6
4135 00:43:13.564695 rx_lastpass[0][0][4] = 38
4136 00:43:13.564761 rx_firspass[0][0][5] = -1
4137 00:43:13.568102 rx_lastpass[0][0][5] = 30
4138 00:43:13.571413 rx_firspass[0][0][6] = 1
4139 00:43:13.571518 rx_lastpass[0][0][6] = 32
4140 00:43:13.574615 rx_firspass[0][0][7] = 3
4141 00:43:13.578499 rx_lastpass[0][0][7] = 32
4142 00:43:13.578564 rx_firspass[0][0][8] = 0
4143 00:43:13.581337 rx_lastpass[0][0][8] = 34
4144 00:43:13.584833 rx_firspass[0][0][9] = 4
4145 00:43:13.584900 rx_lastpass[0][0][9] = 34
4146 00:43:13.588086 rx_firspass[0][0][10] = 6
4147 00:43:13.591443 rx_lastpass[0][0][10] = 38
4148 00:43:13.595575 rx_firspass[0][0][11] = 0
4149 00:43:13.595641 rx_lastpass[0][0][11] = 34
4150 00:43:13.598153 rx_firspass[0][0][12] = 2
4151 00:43:13.601568 rx_lastpass[0][0][12] = 36
4152 00:43:13.601644 rx_firspass[0][0][13] = 2
4153 00:43:13.605009 rx_lastpass[0][0][13] = 30
4154 00:43:13.608239 rx_firspass[0][0][14] = -1
4155 00:43:13.611609 rx_lastpass[0][0][14] = 36
4156 00:43:13.611675 rx_firspass[0][0][15] = 3
4157 00:43:13.614866 rx_lastpass[0][0][15] = 36
4158 00:43:13.618371 rx_firspass[0][1][0] = 7
4159 00:43:13.621643 rx_lastpass[0][1][0] = 41
4160 00:43:13.621713 rx_firspass[0][1][1] = 5
4161 00:43:13.625041 rx_lastpass[0][1][1] = 40
4162 00:43:13.628430 rx_firspass[0][1][2] = 7
4163 00:43:13.628501 rx_lastpass[0][1][2] = 39
4164 00:43:13.631942 rx_firspass[0][1][3] = -4
4165 00:43:13.635176 rx_lastpass[0][1][3] = 31
4166 00:43:13.635246 rx_firspass[0][1][4] = 6
4167 00:43:13.638566 rx_lastpass[0][1][4] = 40
4168 00:43:13.642093 rx_firspass[0][1][5] = -2
4169 00:43:13.645412 rx_lastpass[0][1][5] = 33
4170 00:43:13.645481 rx_firspass[0][1][6] = 1
4171 00:43:13.648709 rx_lastpass[0][1][6] = 35
4172 00:43:13.651842 rx_firspass[0][1][7] = 2
4173 00:43:13.651912 rx_lastpass[0][1][7] = 34
4174 00:43:13.655101 rx_firspass[0][1][8] = -1
4175 00:43:13.658910 rx_lastpass[0][1][8] = 35
4176 00:43:13.658980 rx_firspass[0][1][9] = 2
4177 00:43:13.661815 rx_lastpass[0][1][9] = 36
4178 00:43:13.665094 rx_firspass[0][1][10] = 6
4179 00:43:13.668755 rx_lastpass[0][1][10] = 40
4180 00:43:13.668828 rx_firspass[0][1][11] = 0
4181 00:43:13.671984 rx_lastpass[0][1][11] = 34
4182 00:43:13.675419 rx_firspass[0][1][12] = 2
4183 00:43:13.675484 rx_lastpass[0][1][12] = 37
4184 00:43:13.678960 rx_firspass[0][1][13] = 1
4185 00:43:13.681963 rx_lastpass[0][1][13] = 33
4186 00:43:13.685469 rx_firspass[0][1][14] = 2
4187 00:43:13.685535 rx_lastpass[0][1][14] = 34
4188 00:43:13.688978 rx_firspass[0][1][15] = 3
4189 00:43:13.692105 rx_lastpass[0][1][15] = 38
4190 00:43:13.692169 rx_firspass[1][0][0] = 7
4191 00:43:13.695447 rx_lastpass[1][0][0] = 40
4192 00:43:13.698420 rx_firspass[1][0][1] = 6
4193 00:43:13.701864 rx_lastpass[1][0][1] = 40
4194 00:43:13.701936 rx_firspass[1][0][2] = 0
4195 00:43:13.705478 rx_lastpass[1][0][2] = 34
4196 00:43:13.708676 rx_firspass[1][0][3] = -3
4197 00:43:13.708739 rx_lastpass[1][0][3] = 33
4198 00:43:13.712183 rx_firspass[1][0][4] = 3
4199 00:43:13.715338 rx_lastpass[1][0][4] = 35
4200 00:43:13.715399 rx_firspass[1][0][5] = 7
4201 00:43:13.718842 rx_lastpass[1][0][5] = 40
4202 00:43:13.722058 rx_firspass[1][0][6] = 9
4203 00:43:13.725353 rx_lastpass[1][0][6] = 40
4204 00:43:13.725414 rx_firspass[1][0][7] = 4
4205 00:43:13.729027 rx_lastpass[1][0][7] = 35
4206 00:43:13.732439 rx_firspass[1][0][8] = 1
4207 00:43:13.732502 rx_lastpass[1][0][8] = 35
4208 00:43:13.735524 rx_firspass[1][0][9] = 0
4209 00:43:13.738801 rx_lastpass[1][0][9] = 35
4210 00:43:13.738871 rx_firspass[1][0][10] = 1
4211 00:43:13.742345 rx_lastpass[1][0][10] = 33
4212 00:43:13.745572 rx_firspass[1][0][11] = 2
4213 00:43:13.749085 rx_lastpass[1][0][11] = 36
4214 00:43:13.749153 rx_firspass[1][0][12] = 4
4215 00:43:13.752120 rx_lastpass[1][0][12] = 37
4216 00:43:13.755418 rx_firspass[1][0][13] = 3
4217 00:43:13.755495 rx_lastpass[1][0][13] = 35
4218 00:43:13.759054 rx_firspass[1][0][14] = 3
4219 00:43:13.762139 rx_lastpass[1][0][14] = 35
4220 00:43:13.765535 rx_firspass[1][0][15] = -1
4221 00:43:13.765596 rx_lastpass[1][0][15] = 31
4222 00:43:13.769016 rx_firspass[1][1][0] = 7
4223 00:43:13.772393 rx_lastpass[1][1][0] = 42
4224 00:43:13.772461 rx_firspass[1][1][1] = 6
4225 00:43:13.775613 rx_lastpass[1][1][1] = 41
4226 00:43:13.779077 rx_firspass[1][1][2] = 0
4227 00:43:13.782689 rx_lastpass[1][1][2] = 34
4228 00:43:13.782764 rx_firspass[1][1][3] = -2
4229 00:43:13.785775 rx_lastpass[1][1][3] = 32
4230 00:43:13.789202 rx_firspass[1][1][4] = 3
4231 00:43:13.789278 rx_lastpass[1][1][4] = 37
4232 00:43:13.792520 rx_firspass[1][1][5] = 7
4233 00:43:13.795742 rx_lastpass[1][1][5] = 40
4234 00:43:13.795818 rx_firspass[1][1][6] = 8
4235 00:43:13.799169 rx_lastpass[1][1][6] = 42
4236 00:43:13.802449 rx_firspass[1][1][7] = 3
4237 00:43:13.806381 rx_lastpass[1][1][7] = 37
4238 00:43:13.806447 rx_firspass[1][1][8] = 1
4239 00:43:13.809231 rx_lastpass[1][1][8] = 36
4240 00:43:13.812688 rx_firspass[1][1][9] = 1
4241 00:43:13.812753 rx_lastpass[1][1][9] = 36
4242 00:43:13.815730 rx_firspass[1][1][10] = 1
4243 00:43:13.819295 rx_lastpass[1][1][10] = 35
4244 00:43:13.819358 rx_firspass[1][1][11] = 2
4245 00:43:13.822512 rx_lastpass[1][1][11] = 36
4246 00:43:13.825715 rx_firspass[1][1][12] = 5
4247 00:43:13.829149 rx_lastpass[1][1][12] = 39
4248 00:43:13.829214 rx_firspass[1][1][13] = 4
4249 00:43:13.832711 rx_lastpass[1][1][13] = 38
4250 00:43:13.836072 rx_firspass[1][1][14] = 4
4251 00:43:13.839183 rx_lastpass[1][1][14] = 37
4252 00:43:13.839259 rx_firspass[1][1][15] = -2
4253 00:43:13.842520 rx_lastpass[1][1][15] = 32
4254 00:43:13.845837 dump params clk_delay
4255 00:43:13.845909 clk_delay[0] = 0
4256 00:43:13.849446 clk_delay[1] = 0
4257 00:43:13.849514 dump params dqs_delay
4258 00:43:13.852790 dqs_delay[0][0] = -1
4259 00:43:13.852856 dqs_delay[0][1] = 2
4260 00:43:13.855963 dqs_delay[1][0] = 0
4261 00:43:13.856030 dqs_delay[1][1] = 0
4262 00:43:13.859316 dump params delay_cell_unit = 753
4263 00:43:13.862514 dump source = 0x0
4264 00:43:13.862577 dump params frequency:1200
4265 00:43:13.865944 dump params rank number:2
4266 00:43:13.866002
4267 00:43:13.869297 dump params write leveling
4268 00:43:13.872718 write leveling[0][0][0] = 0x0
4269 00:43:13.872786 write leveling[0][0][1] = 0x0
4270 00:43:13.876104 write leveling[0][1][0] = 0x0
4271 00:43:13.879521 write leveling[0][1][1] = 0x0
4272 00:43:13.882787 write leveling[1][0][0] = 0x0
4273 00:43:13.886102 write leveling[1][0][1] = 0x0
4274 00:43:13.886176 write leveling[1][1][0] = 0x0
4275 00:43:13.889535 write leveling[1][1][1] = 0x0
4276 00:43:13.892918 dump params cbt_cs
4277 00:43:13.892993 cbt_cs[0][0] = 0x0
4278 00:43:13.895842 cbt_cs[0][1] = 0x0
4279 00:43:13.895917 cbt_cs[1][0] = 0x0
4280 00:43:13.899463 cbt_cs[1][1] = 0x0
4281 00:43:13.899539 dump params cbt_mr12
4282 00:43:13.902632 cbt_mr12[0][0] = 0x0
4283 00:43:13.905935 cbt_mr12[0][1] = 0x0
4284 00:43:13.906034 cbt_mr12[1][0] = 0x0
4285 00:43:13.909348 cbt_mr12[1][1] = 0x0
4286 00:43:13.909423 dump params tx window
4287 00:43:13.912839 tx_center_min[0][0][0] = 0
4288 00:43:13.916258 tx_center_max[0][0][0] = 0
4289 00:43:13.919399 tx_center_min[0][0][1] = 0
4290 00:43:13.919474 tx_center_max[0][0][1] = 0
4291 00:43:13.922864 tx_center_min[0][1][0] = 0
4292 00:43:13.926080 tx_center_max[0][1][0] = 0
4293 00:43:13.926180 tx_center_min[0][1][1] = 0
4294 00:43:13.929305 tx_center_max[0][1][1] = 0
4295 00:43:13.932918 tx_center_min[1][0][0] = 0
4296 00:43:13.935989 tx_center_max[1][0][0] = 0
4297 00:43:13.936064 tx_center_min[1][0][1] = 0
4298 00:43:13.939557 tx_center_max[1][0][1] = 0
4299 00:43:13.942567 tx_center_min[1][1][0] = 0
4300 00:43:13.946044 tx_center_max[1][1][0] = 0
4301 00:43:13.946120 tx_center_min[1][1][1] = 0
4302 00:43:13.949357 tx_center_max[1][1][1] = 0
4303 00:43:13.952874 dump params tx window
4304 00:43:13.952950 tx_win_center[0][0][0] = 0
4305 00:43:13.956152 tx_first_pass[0][0][0] = 0
4306 00:43:13.959482 tx_last_pass[0][0][0] = 0
4307 00:43:13.962996 tx_win_center[0][0][1] = 0
4308 00:43:13.963071 tx_first_pass[0][0][1] = 0
4309 00:43:13.966272 tx_last_pass[0][0][1] = 0
4310 00:43:13.969581 tx_win_center[0][0][2] = 0
4311 00:43:13.969656 tx_first_pass[0][0][2] = 0
4312 00:43:13.972965 tx_last_pass[0][0][2] = 0
4313 00:43:13.976086 tx_win_center[0][0][3] = 0
4314 00:43:13.979567 tx_first_pass[0][0][3] = 0
4315 00:43:13.979642 tx_last_pass[0][0][3] = 0
4316 00:43:13.982631 tx_win_center[0][0][4] = 0
4317 00:43:13.986136 tx_first_pass[0][0][4] = 0
4318 00:43:13.989438 tx_last_pass[0][0][4] = 0
4319 00:43:13.989507 tx_win_center[0][0][5] = 0
4320 00:43:13.992851 tx_first_pass[0][0][5] = 0
4321 00:43:13.995949 tx_last_pass[0][0][5] = 0
4322 00:43:13.996017 tx_win_center[0][0][6] = 0
4323 00:43:13.999504 tx_first_pass[0][0][6] = 0
4324 00:43:14.002794 tx_last_pass[0][0][6] = 0
4325 00:43:14.006206 tx_win_center[0][0][7] = 0
4326 00:43:14.006342 tx_first_pass[0][0][7] = 0
4327 00:43:14.009557 tx_last_pass[0][0][7] = 0
4328 00:43:14.012944 tx_win_center[0][0][8] = 0
4329 00:43:14.013035 tx_first_pass[0][0][8] = 0
4330 00:43:14.016153 tx_last_pass[0][0][8] = 0
4331 00:43:14.019488 tx_win_center[0][0][9] = 0
4332 00:43:14.022872 tx_first_pass[0][0][9] = 0
4333 00:43:14.022962 tx_last_pass[0][0][9] = 0
4334 00:43:14.026286 tx_win_center[0][0][10] = 0
4335 00:43:14.029851 tx_first_pass[0][0][10] = 0
4336 00:43:14.032923 tx_last_pass[0][0][10] = 0
4337 00:43:14.033013 tx_win_center[0][0][11] = 0
4338 00:43:14.036438 tx_first_pass[0][0][11] = 0
4339 00:43:14.039654 tx_last_pass[0][0][11] = 0
4340 00:43:14.043101 tx_win_center[0][0][12] = 0
4341 00:43:14.043187 tx_first_pass[0][0][12] = 0
4342 00:43:14.046610 tx_last_pass[0][0][12] = 0
4343 00:43:14.049813 tx_win_center[0][0][13] = 0
4344 00:43:14.053130 tx_first_pass[0][0][13] = 0
4345 00:43:14.053219 tx_last_pass[0][0][13] = 0
4346 00:43:14.056463 tx_win_center[0][0][14] = 0
4347 00:43:14.060005 tx_first_pass[0][0][14] = 0
4348 00:43:14.063264 tx_last_pass[0][0][14] = 0
4349 00:43:14.063331 tx_win_center[0][0][15] = 0
4350 00:43:14.066716 tx_first_pass[0][0][15] = 0
4351 00:43:14.069990 tx_last_pass[0][0][15] = 0
4352 00:43:14.070086 tx_win_center[0][1][0] = 0
4353 00:43:14.073330 tx_first_pass[0][1][0] = 0
4354 00:43:14.076569 tx_last_pass[0][1][0] = 0
4355 00:43:14.079858 tx_win_center[0][1][1] = 0
4356 00:43:14.079945 tx_first_pass[0][1][1] = 0
4357 00:43:14.083147 tx_last_pass[0][1][1] = 0
4358 00:43:14.086456 tx_win_center[0][1][2] = 0
4359 00:43:14.089860 tx_first_pass[0][1][2] = 0
4360 00:43:14.089946 tx_last_pass[0][1][2] = 0
4361 00:43:14.093491 tx_win_center[0][1][3] = 0
4362 00:43:14.096485 tx_first_pass[0][1][3] = 0
4363 00:43:14.096576 tx_last_pass[0][1][3] = 0
4364 00:43:14.099942 tx_win_center[0][1][4] = 0
4365 00:43:14.103261 tx_first_pass[0][1][4] = 0
4366 00:43:14.106652 tx_last_pass[0][1][4] = 0
4367 00:43:14.106731 tx_win_center[0][1][5] = 0
4368 00:43:14.109861 tx_first_pass[0][1][5] = 0
4369 00:43:14.113252 tx_last_pass[0][1][5] = 0
4370 00:43:14.113348 tx_win_center[0][1][6] = 0
4371 00:43:14.116628 tx_first_pass[0][1][6] = 0
4372 00:43:14.120164 tx_last_pass[0][1][6] = 0
4373 00:43:14.123458 tx_win_center[0][1][7] = 0
4374 00:43:14.123550 tx_first_pass[0][1][7] = 0
4375 00:43:14.126682 tx_last_pass[0][1][7] = 0
4376 00:43:14.130345 tx_win_center[0][1][8] = 0
4377 00:43:14.133294 tx_first_pass[0][1][8] = 0
4378 00:43:14.133382 tx_last_pass[0][1][8] = 0
4379 00:43:14.136647 tx_win_center[0][1][9] = 0
4380 00:43:14.140068 tx_first_pass[0][1][9] = 0
4381 00:43:14.140159 tx_last_pass[0][1][9] = 0
4382 00:43:14.143326 tx_win_center[0][1][10] = 0
4383 00:43:14.146799 tx_first_pass[0][1][10] = 0
4384 00:43:14.150445 tx_last_pass[0][1][10] = 0
4385 00:43:14.150537 tx_win_center[0][1][11] = 0
4386 00:43:14.153549 tx_first_pass[0][1][11] = 0
4387 00:43:14.156873 tx_last_pass[0][1][11] = 0
4388 00:43:14.160252 tx_win_center[0][1][12] = 0
4389 00:43:14.160347 tx_first_pass[0][1][12] = 0
4390 00:43:14.163688 tx_last_pass[0][1][12] = 0
4391 00:43:14.166837 tx_win_center[0][1][13] = 0
4392 00:43:14.170353 tx_first_pass[0][1][13] = 0
4393 00:43:14.170431 tx_last_pass[0][1][13] = 0
4394 00:43:14.173342 tx_win_center[0][1][14] = 0
4395 00:43:14.176824 tx_first_pass[0][1][14] = 0
4396 00:43:14.180059 tx_last_pass[0][1][14] = 0
4397 00:43:14.180138 tx_win_center[0][1][15] = 0
4398 00:43:14.183424 tx_first_pass[0][1][15] = 0
4399 00:43:14.186847 tx_last_pass[0][1][15] = 0
4400 00:43:14.190138 tx_win_center[1][0][0] = 0
4401 00:43:14.190220 tx_first_pass[1][0][0] = 0
4402 00:43:14.193696 tx_last_pass[1][0][0] = 0
4403 00:43:14.196880 tx_win_center[1][0][1] = 0
4404 00:43:14.196955 tx_first_pass[1][0][1] = 0
4405 00:43:14.200303 tx_last_pass[1][0][1] = 0
4406 00:43:14.203907 tx_win_center[1][0][2] = 0
4407 00:43:14.206837 tx_first_pass[1][0][2] = 0
4408 00:43:14.206913 tx_last_pass[1][0][2] = 0
4409 00:43:14.210194 tx_win_center[1][0][3] = 0
4410 00:43:14.213552 tx_first_pass[1][0][3] = 0
4411 00:43:14.217035 tx_last_pass[1][0][3] = 0
4412 00:43:14.217110 tx_win_center[1][0][4] = 0
4413 00:43:14.220046 tx_first_pass[1][0][4] = 0
4414 00:43:14.223436 tx_last_pass[1][0][4] = 0
4415 00:43:14.223511 tx_win_center[1][0][5] = 0
4416 00:43:14.226806 tx_first_pass[1][0][5] = 0
4417 00:43:14.230407 tx_last_pass[1][0][5] = 0
4418 00:43:14.233632 tx_win_center[1][0][6] = 0
4419 00:43:14.233708 tx_first_pass[1][0][6] = 0
4420 00:43:14.236856 tx_last_pass[1][0][6] = 0
4421 00:43:14.240197 tx_win_center[1][0][7] = 0
4422 00:43:14.240271 tx_first_pass[1][0][7] = 0
4423 00:43:14.243748 tx_last_pass[1][0][7] = 0
4424 00:43:14.247098 tx_win_center[1][0][8] = 0
4425 00:43:14.250153 tx_first_pass[1][0][8] = 0
4426 00:43:14.250248 tx_last_pass[1][0][8] = 0
4427 00:43:14.253405 tx_win_center[1][0][9] = 0
4428 00:43:14.256948 tx_first_pass[1][0][9] = 0
4429 00:43:14.260523 tx_last_pass[1][0][9] = 0
4430 00:43:14.260598 tx_win_center[1][0][10] = 0
4431 00:43:14.263747 tx_first_pass[1][0][10] = 0
4432 00:43:14.266832 tx_last_pass[1][0][10] = 0
4433 00:43:14.270285 tx_win_center[1][0][11] = 0
4434 00:43:14.270375 tx_first_pass[1][0][11] = 0
4435 00:43:14.273626 tx_last_pass[1][0][11] = 0
4436 00:43:14.277323 tx_win_center[1][0][12] = 0
4437 00:43:14.280327 tx_first_pass[1][0][12] = 0
4438 00:43:14.280403 tx_last_pass[1][0][12] = 0
4439 00:43:14.283696 tx_win_center[1][0][13] = 0
4440 00:43:14.286998 tx_first_pass[1][0][13] = 0
4441 00:43:14.287074 tx_last_pass[1][0][13] = 0
4442 00:43:14.290412 tx_win_center[1][0][14] = 0
4443 00:43:14.293747 tx_first_pass[1][0][14] = 0
4444 00:43:14.297546 tx_last_pass[1][0][14] = 0
4445 00:43:14.297622 tx_win_center[1][0][15] = 0
4446 00:43:14.300629 tx_first_pass[1][0][15] = 0
4447 00:43:14.303860 tx_last_pass[1][0][15] = 0
4448 00:43:14.306892 tx_win_center[1][1][0] = 0
4449 00:43:14.306969 tx_first_pass[1][1][0] = 0
4450 00:43:14.310593 tx_last_pass[1][1][0] = 0
4451 00:43:14.313903 tx_win_center[1][1][1] = 0
4452 00:43:14.316934 tx_first_pass[1][1][1] = 0
4453 00:43:14.317006 tx_last_pass[1][1][1] = 0
4454 00:43:14.320425 tx_win_center[1][1][2] = 0
4455 00:43:14.323873 tx_first_pass[1][1][2] = 0
4456 00:43:14.327311 tx_last_pass[1][1][2] = 0
4457 00:43:14.327388 tx_win_center[1][1][3] = 0
4458 00:43:14.330478 tx_first_pass[1][1][3] = 0
4459 00:43:14.333752 tx_last_pass[1][1][3] = 0
4460 00:43:14.333829 tx_win_center[1][1][4] = 0
4461 00:43:14.337485 tx_first_pass[1][1][4] = 0
4462 00:43:14.340477 tx_last_pass[1][1][4] = 0
4463 00:43:14.343779 tx_win_center[1][1][5] = 0
4464 00:43:14.343856 tx_first_pass[1][1][5] = 0
4465 00:43:14.347091 tx_last_pass[1][1][5] = 0
4466 00:43:14.350406 tx_win_center[1][1][6] = 0
4467 00:43:14.350483 tx_first_pass[1][1][6] = 0
4468 00:43:14.353933 tx_last_pass[1][1][6] = 0
4469 00:43:14.357354 tx_win_center[1][1][7] = 0
4470 00:43:14.360232 tx_first_pass[1][1][7] = 0
4471 00:43:14.360309 tx_last_pass[1][1][7] = 0
4472 00:43:14.363766 tx_win_center[1][1][8] = 0
4473 00:43:14.367046 tx_first_pass[1][1][8] = 0
4474 00:43:14.370396 tx_last_pass[1][1][8] = 0
4475 00:43:14.370473 tx_win_center[1][1][9] = 0
4476 00:43:14.373926 tx_first_pass[1][1][9] = 0
4477 00:43:14.377067 tx_last_pass[1][1][9] = 0
4478 00:43:14.377143 tx_win_center[1][1][10] = 0
4479 00:43:14.380340 tx_first_pass[1][1][10] = 0
4480 00:43:14.383846 tx_last_pass[1][1][10] = 0
4481 00:43:14.387216 tx_win_center[1][1][11] = 0
4482 00:43:14.387292 tx_first_pass[1][1][11] = 0
4483 00:43:14.390559 tx_last_pass[1][1][11] = 0
4484 00:43:14.393742 tx_win_center[1][1][12] = 0
4485 00:43:14.397112 tx_first_pass[1][1][12] = 0
4486 00:43:14.397189 tx_last_pass[1][1][12] = 0
4487 00:43:14.400501 tx_win_center[1][1][13] = 0
4488 00:43:14.403872 tx_first_pass[1][1][13] = 0
4489 00:43:14.407022 tx_last_pass[1][1][13] = 0
4490 00:43:14.407098 tx_win_center[1][1][14] = 0
4491 00:43:14.410482 tx_first_pass[1][1][14] = 0
4492 00:43:14.413788 tx_last_pass[1][1][14] = 0
4493 00:43:14.417220 tx_win_center[1][1][15] = 0
4494 00:43:14.417297 tx_first_pass[1][1][15] = 0
4495 00:43:14.420469 tx_last_pass[1][1][15] = 0
4496 00:43:14.424122 dump params rx window
4497 00:43:14.424199 rx_firspass[0][0][0] = 0
4498 00:43:14.427074 rx_lastpass[0][0][0] = 0
4499 00:43:14.430638 rx_firspass[0][0][1] = 0
4500 00:43:14.433828 rx_lastpass[0][0][1] = 0
4501 00:43:14.433903 rx_firspass[0][0][2] = 0
4502 00:43:14.437378 rx_lastpass[0][0][2] = 0
4503 00:43:14.440439 rx_firspass[0][0][3] = 0
4504 00:43:14.440523 rx_lastpass[0][0][3] = 0
4505 00:43:14.443722 rx_firspass[0][0][4] = 0
4506 00:43:14.447176 rx_lastpass[0][0][4] = 0
4507 00:43:14.447252 rx_firspass[0][0][5] = 0
4508 00:43:14.450549 rx_lastpass[0][0][5] = 0
4509 00:43:14.453861 rx_firspass[0][0][6] = 0
4510 00:43:14.453937 rx_lastpass[0][0][6] = 0
4511 00:43:14.457355 rx_firspass[0][0][7] = 0
4512 00:43:14.460638 rx_lastpass[0][0][7] = 0
4513 00:43:14.460715 rx_firspass[0][0][8] = 0
4514 00:43:14.463954 rx_lastpass[0][0][8] = 0
4515 00:43:14.467294 rx_firspass[0][0][9] = 0
4516 00:43:14.467371 rx_lastpass[0][0][9] = 0
4517 00:43:14.470767 rx_firspass[0][0][10] = 0
4518 00:43:14.473933 rx_lastpass[0][0][10] = 0
4519 00:43:14.477183 rx_firspass[0][0][11] = 0
4520 00:43:14.477259 rx_lastpass[0][0][11] = 0
4521 00:43:14.480689 rx_firspass[0][0][12] = 0
4522 00:43:14.484093 rx_lastpass[0][0][12] = 0
4523 00:43:14.484169 rx_firspass[0][0][13] = 0
4524 00:43:14.487486 rx_lastpass[0][0][13] = 0
4525 00:43:14.490774 rx_firspass[0][0][14] = 0
4526 00:43:14.493971 rx_lastpass[0][0][14] = 0
4527 00:43:14.494047 rx_firspass[0][0][15] = 0
4528 00:43:14.497336 rx_lastpass[0][0][15] = 0
4529 00:43:14.500987 rx_firspass[0][1][0] = 0
4530 00:43:14.501063 rx_lastpass[0][1][0] = 0
4531 00:43:14.504299 rx_firspass[0][1][1] = 0
4532 00:43:14.507163 rx_lastpass[0][1][1] = 0
4533 00:43:14.507240 rx_firspass[0][1][2] = 0
4534 00:43:14.510771 rx_lastpass[0][1][2] = 0
4535 00:43:14.513938 rx_firspass[0][1][3] = 0
4536 00:43:14.514014 rx_lastpass[0][1][3] = 0
4537 00:43:14.517338 rx_firspass[0][1][4] = 0
4538 00:43:14.520634 rx_lastpass[0][1][4] = 0
4539 00:43:14.520710 rx_firspass[0][1][5] = 0
4540 00:43:14.524177 rx_lastpass[0][1][5] = 0
4541 00:43:14.527351 rx_firspass[0][1][6] = 0
4542 00:43:14.530998 rx_lastpass[0][1][6] = 0
4543 00:43:14.531074 rx_firspass[0][1][7] = 0
4544 00:43:14.533803 rx_lastpass[0][1][7] = 0
4545 00:43:14.537686 rx_firspass[0][1][8] = 0
4546 00:43:14.537763 rx_lastpass[0][1][8] = 0
4547 00:43:14.540611 rx_firspass[0][1][9] = 0
4548 00:43:14.544015 rx_lastpass[0][1][9] = 0
4549 00:43:14.544091 rx_firspass[0][1][10] = 0
4550 00:43:14.547617 rx_lastpass[0][1][10] = 0
4551 00:43:14.550983 rx_firspass[0][1][11] = 0
4552 00:43:14.551059 rx_lastpass[0][1][11] = 0
4553 00:43:14.554113 rx_firspass[0][1][12] = 0
4554 00:43:14.557425 rx_lastpass[0][1][12] = 0
4555 00:43:14.560806 rx_firspass[0][1][13] = 0
4556 00:43:14.560883 rx_lastpass[0][1][13] = 0
4557 00:43:14.564116 rx_firspass[0][1][14] = 0
4558 00:43:14.567407 rx_lastpass[0][1][14] = 0
4559 00:43:14.567483 rx_firspass[0][1][15] = 0
4560 00:43:14.571058 rx_lastpass[0][1][15] = 0
4561 00:43:14.574208 rx_firspass[1][0][0] = 0
4562 00:43:14.574291 rx_lastpass[1][0][0] = 0
4563 00:43:14.577563 rx_firspass[1][0][1] = 0
4564 00:43:14.580955 rx_lastpass[1][0][1] = 0
4565 00:43:14.584259 rx_firspass[1][0][2] = 0
4566 00:43:14.584335 rx_lastpass[1][0][2] = 0
4567 00:43:14.587953 rx_firspass[1][0][3] = 0
4568 00:43:14.591026 rx_lastpass[1][0][3] = 0
4569 00:43:14.591102 rx_firspass[1][0][4] = 0
4570 00:43:14.594626 rx_lastpass[1][0][4] = 0
4571 00:43:14.597723 rx_firspass[1][0][5] = 0
4572 00:43:14.597803 rx_lastpass[1][0][5] = 0
4573 00:43:14.601230 rx_firspass[1][0][6] = 0
4574 00:43:14.604327 rx_lastpass[1][0][6] = 0
4575 00:43:14.604403 rx_firspass[1][0][7] = 0
4576 00:43:14.607794 rx_lastpass[1][0][7] = 0
4577 00:43:14.610855 rx_firspass[1][0][8] = 0
4578 00:43:14.610931 rx_lastpass[1][0][8] = 0
4579 00:43:14.614440 rx_firspass[1][0][9] = 0
4580 00:43:14.617583 rx_lastpass[1][0][9] = 0
4581 00:43:14.617659 rx_firspass[1][0][10] = 0
4582 00:43:14.620955 rx_lastpass[1][0][10] = 0
4583 00:43:14.624301 rx_firspass[1][0][11] = 0
4584 00:43:14.627811 rx_lastpass[1][0][11] = 0
4585 00:43:14.627887 rx_firspass[1][0][12] = 0
4586 00:43:14.630963 rx_lastpass[1][0][12] = 0
4587 00:43:14.634180 rx_firspass[1][0][13] = 0
4588 00:43:14.634298 rx_lastpass[1][0][13] = 0
4589 00:43:14.637860 rx_firspass[1][0][14] = 0
4590 00:43:14.641227 rx_lastpass[1][0][14] = 0
4591 00:43:14.644385 rx_firspass[1][0][15] = 0
4592 00:43:14.644461 rx_lastpass[1][0][15] = 0
4593 00:43:14.647912 rx_firspass[1][1][0] = 0
4594 00:43:14.651113 rx_lastpass[1][1][0] = 0
4595 00:43:14.651190 rx_firspass[1][1][1] = 0
4596 00:43:14.654482 rx_lastpass[1][1][1] = 0
4597 00:43:14.657739 rx_firspass[1][1][2] = 0
4598 00:43:14.657815 rx_lastpass[1][1][2] = 0
4599 00:43:14.661426 rx_firspass[1][1][3] = 0
4600 00:43:14.664599 rx_lastpass[1][1][3] = 0
4601 00:43:14.664675 rx_firspass[1][1][4] = 0
4602 00:43:14.667870 rx_lastpass[1][1][4] = 0
4603 00:43:14.671145 rx_firspass[1][1][5] = 0
4604 00:43:14.671221 rx_lastpass[1][1][5] = 0
4605 00:43:14.674593 rx_firspass[1][1][6] = 0
4606 00:43:14.678247 rx_lastpass[1][1][6] = 0
4607 00:43:14.678323 rx_firspass[1][1][7] = 0
4608 00:43:14.681336 rx_lastpass[1][1][7] = 0
4609 00:43:14.684499 rx_firspass[1][1][8] = 0
4610 00:43:14.688037 rx_lastpass[1][1][8] = 0
4611 00:43:14.688113 rx_firspass[1][1][9] = 0
4612 00:43:14.691164 rx_lastpass[1][1][9] = 0
4613 00:43:14.694484 rx_firspass[1][1][10] = 0
4614 00:43:14.694560 rx_lastpass[1][1][10] = 0
4615 00:43:14.698099 rx_firspass[1][1][11] = 0
4616 00:43:14.701297 rx_lastpass[1][1][11] = 0
4617 00:43:14.701374 rx_firspass[1][1][12] = 0
4618 00:43:14.704601 rx_lastpass[1][1][12] = 0
4619 00:43:14.708084 rx_firspass[1][1][13] = 0
4620 00:43:14.711193 rx_lastpass[1][1][13] = 0
4621 00:43:14.711269 rx_firspass[1][1][14] = 0
4622 00:43:14.714613 rx_lastpass[1][1][14] = 0
4623 00:43:14.718021 rx_firspass[1][1][15] = 0
4624 00:43:14.718098 rx_lastpass[1][1][15] = 0
4625 00:43:14.721420 dump params clk_delay
4626 00:43:14.721496 clk_delay[0] = 0
4627 00:43:14.724819 clk_delay[1] = 0
4628 00:43:14.727883 dump params dqs_delay
4629 00:43:14.727960 dqs_delay[0][0] = 0
4630 00:43:14.731453 dqs_delay[0][1] = 0
4631 00:43:14.731529 dqs_delay[1][0] = 0
4632 00:43:14.734980 dqs_delay[1][1] = 0
4633 00:43:14.738173 dump params delay_cell_unit = 753
4634 00:43:14.738291 dump source = 0x0
4635 00:43:14.741405 dump params frequency:800
4636 00:43:14.741482 dump params rank number:2
4637 00:43:14.744921
4638 00:43:14.744997 dump params write leveling
4639 00:43:14.748362 write leveling[0][0][0] = 0x0
4640 00:43:14.751570 write leveling[0][0][1] = 0x0
4641 00:43:14.755025 write leveling[0][1][0] = 0x0
4642 00:43:14.755101 write leveling[0][1][1] = 0x0
4643 00:43:14.758386 write leveling[1][0][0] = 0x0
4644 00:43:14.761580 write leveling[1][0][1] = 0x0
4645 00:43:14.764903 write leveling[1][1][0] = 0x0
4646 00:43:14.768289 write leveling[1][1][1] = 0x0
4647 00:43:14.768366 dump params cbt_cs
4648 00:43:14.771980 cbt_cs[0][0] = 0x0
4649 00:43:14.772056 cbt_cs[0][1] = 0x0
4650 00:43:14.774816 cbt_cs[1][0] = 0x0
4651 00:43:14.774892 cbt_cs[1][1] = 0x0
4652 00:43:14.778147 dump params cbt_mr12
4653 00:43:14.778268 cbt_mr12[0][0] = 0x0
4654 00:43:14.781509 cbt_mr12[0][1] = 0x0
4655 00:43:14.784768 cbt_mr12[1][0] = 0x0
4656 00:43:14.784845 cbt_mr12[1][1] = 0x0
4657 00:43:14.788097 dump params tx window
4658 00:43:14.788172 tx_center_min[0][0][0] = 0
4659 00:43:14.791782 tx_center_max[0][0][0] = 0
4660 00:43:14.795114 tx_center_min[0][0][1] = 0
4661 00:43:14.798199 tx_center_max[0][0][1] = 0
4662 00:43:14.798298 tx_center_min[0][1][0] = 0
4663 00:43:14.801792 tx_center_max[0][1][0] = 0
4664 00:43:14.804860 tx_center_min[0][1][1] = 0
4665 00:43:14.808664 tx_center_max[0][1][1] = 0
4666 00:43:14.808741 tx_center_min[1][0][0] = 0
4667 00:43:14.811814 tx_center_max[1][0][0] = 0
4668 00:43:14.815052 tx_center_min[1][0][1] = 0
4669 00:43:14.815129 tx_center_max[1][0][1] = 0
4670 00:43:14.818171 tx_center_min[1][1][0] = 0
4671 00:43:14.821645 tx_center_max[1][1][0] = 0
4672 00:43:14.824811 tx_center_min[1][1][1] = 0
4673 00:43:14.824887 tx_center_max[1][1][1] = 0
4674 00:43:14.828246 dump params tx window
4675 00:43:14.831853 tx_win_center[0][0][0] = 0
4676 00:43:14.834825 tx_first_pass[0][0][0] = 0
4677 00:43:14.834892 tx_last_pass[0][0][0] = 0
4678 00:43:14.838089 tx_win_center[0][0][1] = 0
4679 00:43:14.841356 tx_first_pass[0][0][1] = 0
4680 00:43:14.841425 tx_last_pass[0][0][1] = 0
4681 00:43:14.844734 tx_win_center[0][0][2] = 0
4682 00:43:14.848198 tx_first_pass[0][0][2] = 0
4683 00:43:14.851480 tx_last_pass[0][0][2] = 0
4684 00:43:14.851544 tx_win_center[0][0][3] = 0
4685 00:43:14.854911 tx_first_pass[0][0][3] = 0
4686 00:43:14.858392 tx_last_pass[0][0][3] = 0
4687 00:43:14.858459 tx_win_center[0][0][4] = 0
4688 00:43:14.861784 tx_first_pass[0][0][4] = 0
4689 00:43:14.865069 tx_last_pass[0][0][4] = 0
4690 00:43:14.868158 tx_win_center[0][0][5] = 0
4691 00:43:14.868224 tx_first_pass[0][0][5] = 0
4692 00:43:14.871591 tx_last_pass[0][0][5] = 0
4693 00:43:14.875447 tx_win_center[0][0][6] = 0
4694 00:43:14.878051 tx_first_pass[0][0][6] = 0
4695 00:43:14.878124 tx_last_pass[0][0][6] = 0
4696 00:43:14.881426 tx_win_center[0][0][7] = 0
4697 00:43:14.884699 tx_first_pass[0][0][7] = 0
4698 00:43:14.884766 tx_last_pass[0][0][7] = 0
4699 00:43:14.888187 tx_win_center[0][0][8] = 0
4700 00:43:14.891727 tx_first_pass[0][0][8] = 0
4701 00:43:14.895152 tx_last_pass[0][0][8] = 0
4702 00:43:14.895223 tx_win_center[0][0][9] = 0
4703 00:43:14.898394 tx_first_pass[0][0][9] = 0
4704 00:43:14.901921 tx_last_pass[0][0][9] = 0
4705 00:43:14.901998 tx_win_center[0][0][10] = 0
4706 00:43:14.905164 tx_first_pass[0][0][10] = 0
4707 00:43:14.908611 tx_last_pass[0][0][10] = 0
4708 00:43:14.912161 tx_win_center[0][0][11] = 0
4709 00:43:14.912237 tx_first_pass[0][0][11] = 0
4710 00:43:14.915097 tx_last_pass[0][0][11] = 0
4711 00:43:14.918730 tx_win_center[0][0][12] = 0
4712 00:43:14.921669 tx_first_pass[0][0][12] = 0
4713 00:43:14.921746 tx_last_pass[0][0][12] = 0
4714 00:43:14.925256 tx_win_center[0][0][13] = 0
4715 00:43:14.928355 tx_first_pass[0][0][13] = 0
4716 00:43:14.931885 tx_last_pass[0][0][13] = 0
4717 00:43:14.931961 tx_win_center[0][0][14] = 0
4718 00:43:14.935199 tx_first_pass[0][0][14] = 0
4719 00:43:14.938457 tx_last_pass[0][0][14] = 0
4720 00:43:14.941737 tx_win_center[0][0][15] = 0
4721 00:43:14.941813 tx_first_pass[0][0][15] = 0
4722 00:43:14.945140 tx_last_pass[0][0][15] = 0
4723 00:43:14.948410 tx_win_center[0][1][0] = 0
4724 00:43:14.952041 tx_first_pass[0][1][0] = 0
4725 00:43:14.952117 tx_last_pass[0][1][0] = 0
4726 00:43:14.955448 tx_win_center[0][1][1] = 0
4727 00:43:14.958729 tx_first_pass[0][1][1] = 0
4728 00:43:14.961718 tx_last_pass[0][1][1] = 0
4729 00:43:14.961794 tx_win_center[0][1][2] = 0
4730 00:43:14.965432 tx_first_pass[0][1][2] = 0
4731 00:43:14.968474 tx_last_pass[0][1][2] = 0
4732 00:43:14.968551 tx_win_center[0][1][3] = 0
4733 00:43:14.971817 tx_first_pass[0][1][3] = 0
4734 00:43:14.975370 tx_last_pass[0][1][3] = 0
4735 00:43:14.978544 tx_win_center[0][1][4] = 0
4736 00:43:14.978621 tx_first_pass[0][1][4] = 0
4737 00:43:14.981698 tx_last_pass[0][1][4] = 0
4738 00:43:14.985102 tx_win_center[0][1][5] = 0
4739 00:43:14.988413 tx_first_pass[0][1][5] = 0
4740 00:43:14.988490 tx_last_pass[0][1][5] = 0
4741 00:43:14.991795 tx_win_center[0][1][6] = 0
4742 00:43:14.995176 tx_first_pass[0][1][6] = 0
4743 00:43:14.995253 tx_last_pass[0][1][6] = 0
4744 00:43:14.998848 tx_win_center[0][1][7] = 0
4745 00:43:15.002003 tx_first_pass[0][1][7] = 0
4746 00:43:15.005454 tx_last_pass[0][1][7] = 0
4747 00:43:15.005531 tx_win_center[0][1][8] = 0
4748 00:43:15.008805 tx_first_pass[0][1][8] = 0
4749 00:43:15.011771 tx_last_pass[0][1][8] = 0
4750 00:43:15.011847 tx_win_center[0][1][9] = 0
4751 00:43:15.015425 tx_first_pass[0][1][9] = 0
4752 00:43:15.018426 tx_last_pass[0][1][9] = 0
4753 00:43:15.021982 tx_win_center[0][1][10] = 0
4754 00:43:15.022059 tx_first_pass[0][1][10] = 0
4755 00:43:15.025292 tx_last_pass[0][1][10] = 0
4756 00:43:15.028385 tx_win_center[0][1][11] = 0
4757 00:43:15.031920 tx_first_pass[0][1][11] = 0
4758 00:43:15.031997 tx_last_pass[0][1][11] = 0
4759 00:43:15.035167 tx_win_center[0][1][12] = 0
4760 00:43:15.038489 tx_first_pass[0][1][12] = 0
4761 00:43:15.042137 tx_last_pass[0][1][12] = 0
4762 00:43:15.042236 tx_win_center[0][1][13] = 0
4763 00:43:15.045053 tx_first_pass[0][1][13] = 0
4764 00:43:15.048430 tx_last_pass[0][1][13] = 0
4765 00:43:15.052199 tx_win_center[0][1][14] = 0
4766 00:43:15.052275 tx_first_pass[0][1][14] = 0
4767 00:43:15.055262 tx_last_pass[0][1][14] = 0
4768 00:43:15.059046 tx_win_center[0][1][15] = 0
4769 00:43:15.062457 tx_first_pass[0][1][15] = 0
4770 00:43:15.062534 tx_last_pass[0][1][15] = 0
4771 00:43:15.065505 tx_win_center[1][0][0] = 0
4772 00:43:15.068573 tx_first_pass[1][0][0] = 0
4773 00:43:15.068642 tx_last_pass[1][0][0] = 0
4774 00:43:15.072061 tx_win_center[1][0][1] = 0
4775 00:43:15.075560 tx_first_pass[1][0][1] = 0
4776 00:43:15.078701 tx_last_pass[1][0][1] = 0
4777 00:43:15.078768 tx_win_center[1][0][2] = 0
4778 00:43:15.082338 tx_first_pass[1][0][2] = 0
4779 00:43:15.085726 tx_last_pass[1][0][2] = 0
4780 00:43:15.088997 tx_win_center[1][0][3] = 0
4781 00:43:15.089063 tx_first_pass[1][0][3] = 0
4782 00:43:15.092164 tx_last_pass[1][0][3] = 0
4783 00:43:15.095562 tx_win_center[1][0][4] = 0
4784 00:43:15.095633 tx_first_pass[1][0][4] = 0
4785 00:43:15.098939 tx_last_pass[1][0][4] = 0
4786 00:43:15.102380 tx_win_center[1][0][5] = 0
4787 00:43:15.105633 tx_first_pass[1][0][5] = 0
4788 00:43:15.105700 tx_last_pass[1][0][5] = 0
4789 00:43:15.108840 tx_win_center[1][0][6] = 0
4790 00:43:15.112152 tx_first_pass[1][0][6] = 0
4791 00:43:15.112217 tx_last_pass[1][0][6] = 0
4792 00:43:15.115746 tx_win_center[1][0][7] = 0
4793 00:43:15.118749 tx_first_pass[1][0][7] = 0
4794 00:43:15.122178 tx_last_pass[1][0][7] = 0
4795 00:43:15.122255 tx_win_center[1][0][8] = 0
4796 00:43:15.125642 tx_first_pass[1][0][8] = 0
4797 00:43:15.128759 tx_last_pass[1][0][8] = 0
4798 00:43:15.132506 tx_win_center[1][0][9] = 0
4799 00:43:15.132571 tx_first_pass[1][0][9] = 0
4800 00:43:15.135359 tx_last_pass[1][0][9] = 0
4801 00:43:15.138812 tx_win_center[1][0][10] = 0
4802 00:43:15.141999 tx_first_pass[1][0][10] = 0
4803 00:43:15.142066 tx_last_pass[1][0][10] = 0
4804 00:43:15.145793 tx_win_center[1][0][11] = 0
4805 00:43:15.149099 tx_first_pass[1][0][11] = 0
4806 00:43:15.149168 tx_last_pass[1][0][11] = 0
4807 00:43:15.152069 tx_win_center[1][0][12] = 0
4808 00:43:15.155535 tx_first_pass[1][0][12] = 0
4809 00:43:15.158872 tx_last_pass[1][0][12] = 0
4810 00:43:15.158937 tx_win_center[1][0][13] = 0
4811 00:43:15.162171 tx_first_pass[1][0][13] = 0
4812 00:43:15.165756 tx_last_pass[1][0][13] = 0
4813 00:43:15.168913 tx_win_center[1][0][14] = 0
4814 00:43:15.168978 tx_first_pass[1][0][14] = 0
4815 00:43:15.172317 tx_last_pass[1][0][14] = 0
4816 00:43:15.175655 tx_win_center[1][0][15] = 0
4817 00:43:15.179247 tx_first_pass[1][0][15] = 0
4818 00:43:15.179319 tx_last_pass[1][0][15] = 0
4819 00:43:15.182351 tx_win_center[1][1][0] = 0
4820 00:43:15.185713 tx_first_pass[1][1][0] = 0
4821 00:43:15.189095 tx_last_pass[1][1][0] = 0
4822 00:43:15.189159 tx_win_center[1][1][1] = 0
4823 00:43:15.192500 tx_first_pass[1][1][1] = 0
4824 00:43:15.195851 tx_last_pass[1][1][1] = 0
4825 00:43:15.195917 tx_win_center[1][1][2] = 0
4826 00:43:15.199047 tx_first_pass[1][1][2] = 0
4827 00:43:15.202239 tx_last_pass[1][1][2] = 0
4828 00:43:15.205664 tx_win_center[1][1][3] = 0
4829 00:43:15.205741 tx_first_pass[1][1][3] = 0
4830 00:43:15.209016 tx_last_pass[1][1][3] = 0
4831 00:43:15.212504 tx_win_center[1][1][4] = 0
4832 00:43:15.215807 tx_first_pass[1][1][4] = 0
4833 00:43:15.215883 tx_last_pass[1][1][4] = 0
4834 00:43:15.218949 tx_win_center[1][1][5] = 0
4835 00:43:15.222438 tx_first_pass[1][1][5] = 0
4836 00:43:15.222514 tx_last_pass[1][1][5] = 0
4837 00:43:15.225737 tx_win_center[1][1][6] = 0
4838 00:43:15.229229 tx_first_pass[1][1][6] = 0
4839 00:43:15.232489 tx_last_pass[1][1][6] = 0
4840 00:43:15.232566 tx_win_center[1][1][7] = 0
4841 00:43:15.235816 tx_first_pass[1][1][7] = 0
4842 00:43:15.239195 tx_last_pass[1][1][7] = 0
4843 00:43:15.239286 tx_win_center[1][1][8] = 0
4844 00:43:15.242410 tx_first_pass[1][1][8] = 0
4845 00:43:15.245977 tx_last_pass[1][1][8] = 0
4846 00:43:15.249217 tx_win_center[1][1][9] = 0
4847 00:43:15.249294 tx_first_pass[1][1][9] = 0
4848 00:43:15.252733 tx_last_pass[1][1][9] = 0
4849 00:43:15.255798 tx_win_center[1][1][10] = 0
4850 00:43:15.259063 tx_first_pass[1][1][10] = 0
4851 00:43:15.259163 tx_last_pass[1][1][10] = 0
4852 00:43:15.262647 tx_win_center[1][1][11] = 0
4853 00:43:15.265872 tx_first_pass[1][1][11] = 0
4854 00:43:15.269193 tx_last_pass[1][1][11] = 0
4855 00:43:15.269269 tx_win_center[1][1][12] = 0
4856 00:43:15.272452 tx_first_pass[1][1][12] = 0
4857 00:43:15.275947 tx_last_pass[1][1][12] = 0
4858 00:43:15.279091 tx_win_center[1][1][13] = 0
4859 00:43:15.279167 tx_first_pass[1][1][13] = 0
4860 00:43:15.282664 tx_last_pass[1][1][13] = 0
4861 00:43:15.285982 tx_win_center[1][1][14] = 0
4862 00:43:15.289333 tx_first_pass[1][1][14] = 0
4863 00:43:15.289409 tx_last_pass[1][1][14] = 0
4864 00:43:15.292444 tx_win_center[1][1][15] = 0
4865 00:43:15.296201 tx_first_pass[1][1][15] = 0
4866 00:43:15.299449 tx_last_pass[1][1][15] = 0
4867 00:43:15.299526 dump params rx window
4868 00:43:15.302744 rx_firspass[0][0][0] = 0
4869 00:43:15.305868 rx_lastpass[0][0][0] = 0
4870 00:43:15.305944 rx_firspass[0][0][1] = 0
4871 00:43:15.309280 rx_lastpass[0][0][1] = 0
4872 00:43:15.313055 rx_firspass[0][0][2] = 0
4873 00:43:15.313132 rx_lastpass[0][0][2] = 0
4874 00:43:15.316016 rx_firspass[0][0][3] = 0
4875 00:43:15.319223 rx_lastpass[0][0][3] = 0
4876 00:43:15.319300 rx_firspass[0][0][4] = 0
4877 00:43:15.322610 rx_lastpass[0][0][4] = 0
4878 00:43:15.326053 rx_firspass[0][0][5] = 0
4879 00:43:15.326153 rx_lastpass[0][0][5] = 0
4880 00:43:15.329332 rx_firspass[0][0][6] = 0
4881 00:43:15.332534 rx_lastpass[0][0][6] = 0
4882 00:43:15.332611 rx_firspass[0][0][7] = 0
4883 00:43:15.335855 rx_lastpass[0][0][7] = 0
4884 00:43:15.339145 rx_firspass[0][0][8] = 0
4885 00:43:15.339242 rx_lastpass[0][0][8] = 0
4886 00:43:15.342604 rx_firspass[0][0][9] = 0
4887 00:43:15.345878 rx_lastpass[0][0][9] = 0
4888 00:43:15.349471 rx_firspass[0][0][10] = 0
4889 00:43:15.349547 rx_lastpass[0][0][10] = 0
4890 00:43:15.352678 rx_firspass[0][0][11] = 0
4891 00:43:15.356143 rx_lastpass[0][0][11] = 0
4892 00:43:15.356220 rx_firspass[0][0][12] = 0
4893 00:43:15.359756 rx_lastpass[0][0][12] = 0
4894 00:43:15.362769 rx_firspass[0][0][13] = 0
4895 00:43:15.362846 rx_lastpass[0][0][13] = 0
4896 00:43:15.366232 rx_firspass[0][0][14] = 0
4897 00:43:15.369384 rx_lastpass[0][0][14] = 0
4898 00:43:15.372838 rx_firspass[0][0][15] = 0
4899 00:43:15.372914 rx_lastpass[0][0][15] = 0
4900 00:43:15.376164 rx_firspass[0][1][0] = 0
4901 00:43:15.379645 rx_lastpass[0][1][0] = 0
4902 00:43:15.379721 rx_firspass[0][1][1] = 0
4903 00:43:15.382909 rx_lastpass[0][1][1] = 0
4904 00:43:15.386146 rx_firspass[0][1][2] = 0
4905 00:43:15.386281 rx_lastpass[0][1][2] = 0
4906 00:43:15.389628 rx_firspass[0][1][3] = 0
4907 00:43:15.393118 rx_lastpass[0][1][3] = 0
4908 00:43:15.393195 rx_firspass[0][1][4] = 0
4909 00:43:15.396457 rx_lastpass[0][1][4] = 0
4910 00:43:15.399777 rx_firspass[0][1][5] = 0
4911 00:43:15.399854 rx_lastpass[0][1][5] = 0
4912 00:43:15.403114 rx_firspass[0][1][6] = 0
4913 00:43:15.406361 rx_lastpass[0][1][6] = 0
4914 00:43:15.409963 rx_firspass[0][1][7] = 0
4915 00:43:15.410063 rx_lastpass[0][1][7] = 0
4916 00:43:15.413162 rx_firspass[0][1][8] = 0
4917 00:43:15.416247 rx_lastpass[0][1][8] = 0
4918 00:43:15.416324 rx_firspass[0][1][9] = 0
4919 00:43:15.419598 rx_lastpass[0][1][9] = 0
4920 00:43:15.423107 rx_firspass[0][1][10] = 0
4921 00:43:15.423182 rx_lastpass[0][1][10] = 0
4922 00:43:15.426345 rx_firspass[0][1][11] = 0
4923 00:43:15.429679 rx_lastpass[0][1][11] = 0
4924 00:43:15.429755 rx_firspass[0][1][12] = 0
4925 00:43:15.433205 rx_lastpass[0][1][12] = 0
4926 00:43:15.436483 rx_firspass[0][1][13] = 0
4927 00:43:15.439594 rx_lastpass[0][1][13] = 0
4928 00:43:15.439669 rx_firspass[0][1][14] = 0
4929 00:43:15.443088 rx_lastpass[0][1][14] = 0
4930 00:43:15.446594 rx_firspass[0][1][15] = 0
4931 00:43:15.446670 rx_lastpass[0][1][15] = 0
4932 00:43:15.449724 rx_firspass[1][0][0] = 0
4933 00:43:15.453107 rx_lastpass[1][0][0] = 0
4934 00:43:15.456408 rx_firspass[1][0][1] = 0
4935 00:43:15.456482 rx_lastpass[1][0][1] = 0
4936 00:43:15.459846 rx_firspass[1][0][2] = 0
4937 00:43:15.462880 rx_lastpass[1][0][2] = 0
4938 00:43:15.462951 rx_firspass[1][0][3] = 0
4939 00:43:15.466347 rx_lastpass[1][0][3] = 0
4940 00:43:15.469654 rx_firspass[1][0][4] = 0
4941 00:43:15.469720 rx_lastpass[1][0][4] = 0
4942 00:43:15.473032 rx_firspass[1][0][5] = 0
4943 00:43:15.476331 rx_lastpass[1][0][5] = 0
4944 00:43:15.476403 rx_firspass[1][0][6] = 0
4945 00:43:15.479434 rx_lastpass[1][0][6] = 0
4946 00:43:15.482800 rx_firspass[1][0][7] = 0
4947 00:43:15.482865 rx_lastpass[1][0][7] = 0
4948 00:43:15.486207 rx_firspass[1][0][8] = 0
4949 00:43:15.489541 rx_lastpass[1][0][8] = 0
4950 00:43:15.489604 rx_firspass[1][0][9] = 0
4951 00:43:15.493030 rx_lastpass[1][0][9] = 0
4952 00:43:15.496311 rx_firspass[1][0][10] = 0
4953 00:43:15.499462 rx_lastpass[1][0][10] = 0
4954 00:43:15.499534 rx_firspass[1][0][11] = 0
4955 00:43:15.502795 rx_lastpass[1][0][11] = 0
4956 00:43:15.506208 rx_firspass[1][0][12] = 0
4957 00:43:15.506278 rx_lastpass[1][0][12] = 0
4958 00:43:15.509510 rx_firspass[1][0][13] = 0
4959 00:43:15.512890 rx_lastpass[1][0][13] = 0
4960 00:43:15.516478 rx_firspass[1][0][14] = 0
4961 00:43:15.516545 rx_lastpass[1][0][14] = 0
4962 00:43:15.519737 rx_firspass[1][0][15] = 0
4963 00:43:15.522976 rx_lastpass[1][0][15] = 0
4964 00:43:15.523042 rx_firspass[1][1][0] = 0
4965 00:43:15.526284 rx_lastpass[1][1][0] = 0
4966 00:43:15.529603 rx_firspass[1][1][1] = 0
4967 00:43:15.529664 rx_lastpass[1][1][1] = 0
4968 00:43:15.532939 rx_firspass[1][1][2] = 0
4969 00:43:15.536290 rx_lastpass[1][1][2] = 0
4970 00:43:15.536351 rx_firspass[1][1][3] = 0
4971 00:43:15.539696 rx_lastpass[1][1][3] = 0
4972 00:43:15.542999 rx_firspass[1][1][4] = 0
4973 00:43:15.546439 rx_lastpass[1][1][4] = 0
4974 00:43:15.546498 rx_firspass[1][1][5] = 0
4975 00:43:15.549978 rx_lastpass[1][1][5] = 0
4976 00:43:15.553215 rx_firspass[1][1][6] = 0
4977 00:43:15.553281 rx_lastpass[1][1][6] = 0
4978 00:43:15.556309 rx_firspass[1][1][7] = 0
4979 00:43:15.559576 rx_lastpass[1][1][7] = 0
4980 00:43:15.559634 rx_firspass[1][1][8] = 0
4981 00:43:15.563006 rx_lastpass[1][1][8] = 0
4982 00:43:15.566342 rx_firspass[1][1][9] = 0
4983 00:43:15.566399 rx_lastpass[1][1][9] = 0
4984 00:43:15.569512 rx_firspass[1][1][10] = 0
4985 00:43:15.572789 rx_lastpass[1][1][10] = 0
4986 00:43:15.576235 rx_firspass[1][1][11] = 0
4987 00:43:15.576294 rx_lastpass[1][1][11] = 0
4988 00:43:15.579702 rx_firspass[1][1][12] = 0
4989 00:43:15.583023 rx_lastpass[1][1][12] = 0
4990 00:43:15.583087 rx_firspass[1][1][13] = 0
4991 00:43:15.586178 rx_lastpass[1][1][13] = 0
4992 00:43:15.589483 rx_firspass[1][1][14] = 0
4993 00:43:15.592966 rx_lastpass[1][1][14] = 0
4994 00:43:15.593030 rx_firspass[1][1][15] = 0
4995 00:43:15.596340 rx_lastpass[1][1][15] = 0
4996 00:43:15.599890 dump params clk_delay
4997 00:43:15.599966 clk_delay[0] = 0
4998 00:43:15.600024 clk_delay[1] = 0
4999 00:43:15.602963 dump params dqs_delay
5000 00:43:15.606337 dqs_delay[0][0] = 0
5001 00:43:15.606403 dqs_delay[0][1] = 0
5002 00:43:15.609877 dqs_delay[1][0] = 0
5003 00:43:15.609952 dqs_delay[1][1] = 0
5004 00:43:15.612885 dump params delay_cell_unit = 753
5005 00:43:15.616427 mt_set_emi_preloader end
5006 00:43:15.619690 [mt_mem_init] dram size: 0x100000000, rank number: 2
5007 00:43:15.626348 [complex_mem_test] start addr:0x40000000, len:20480
5008 00:43:15.661731 [mt_mem_init] preloader addr:0x40000000 complex R/W mem test pass : 0
5009 00:43:15.668403 [complex_mem_test] start addr:0x80000000, len:20480
5010 00:43:15.703941 [mt_mem_init] preloader addr:0x80000000 complex R/W mem test pass : 0
5011 00:43:15.710776 [complex_mem_test] start addr:0xc0000000, len:20480
5012 00:43:15.746593 [mt_mem_init] preloader addr:0xc0000000 complex R/W mem test pass : 0
5013 00:43:15.752871 [complex_mem_test] start addr:0x56000000, len:8192
5014 00:43:15.769788 [MEM] 1st complex R/W mem test pass (start addr:0x56000000)
5015 00:43:15.769865 ddr_geometry:1
5016 00:43:15.776167 [complex_mem_test] start addr:0x80000000, len:8192
5017 00:43:15.793094 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
5018 00:43:15.796681 dram_init: dram init end (result: 0)
5019 00:43:15.803196 Successfully loaded DRAM blobs and ran DRAM calibration
5020 00:43:15.813536 Mapping address range [0000000040000000:0000000140000000) as cacheable | read-write | non-secure | normal
5021 00:43:15.813609 CBMEM:
5022 00:43:15.816752 IMD: root @ 00000000fffff000 254 entries.
5023 00:43:15.820215 IMD: root @ 00000000ffffec00 62 entries.
5024 00:43:15.826914 VBOOT: copying vboot_working_data (256 bytes) to CBMEM...
5025 00:43:15.833699 out: cmd=0xa4: 03 6c a4 00 00 00 0c 00 00 01 00 00 50 7f 11 00 00 00 00 00
5026 00:43:15.836552 in-header: 03 a1 00 00 08 00 00 00
5027 00:43:15.839865 in-data: 84 60 60 10 00 00 00 00
5028 00:43:15.843528 Chrome EC: clear events_b mask to 0x0000000020004000
5029 00:43:15.850796 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
5030 00:43:15.854081 in-header: 03 fd 00 00 00 00 00 00
5031 00:43:15.854180 in-data:
5032 00:43:15.860627 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5033 00:43:15.860704 CBFS @ 21000 size 3d4000
5034 00:43:15.867381 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5035 00:43:15.870824 CBFS: Locating 'fallback/ramstage'
5036 00:43:15.873887 CBFS: Found @ offset 10d40 size d563
5037 00:43:15.895096 read SPI 0x31d94 0xd547: 16640 us, 3281 KB/s, 26.248 Mbps
5038 00:43:15.907384 Accumulated console time in romstage 12821 ms
5039 00:43:15.907461
5040 00:43:15.907521
5041 00:43:15.917341 coreboot-v1.9308_26_0.0.22-10565-g8487d48179 Sun Jan 30 03:25:20 UTC 2022 ramstage starting (log level: 8)...
5042 00:43:15.920474 ARM64: Exception handlers installed.
5043 00:43:15.920550 ARM64: Testing exception
5044 00:43:15.923889 ARM64: Done test exception
5045 00:43:15.927299 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
5046 00:43:15.930560 Manufacturer: ef
5047 00:43:15.933966 SF: Detected W25Q64DW with sector size 0x1000, total 0x800000
5048 00:43:15.940603 WARNING: RO_VPD is uninitialized or empty.
5049 00:43:15.944016 FMAP: area RW_VPD found @ 550000 (16384 bytes)
5050 00:43:15.947171 FMAP: area RW_VPD found @ 550000 (16384 bytes)
5051 00:43:15.956828 read SPI 0x550600 0x3a00: 4533 us, 3275 KB/s, 26.200 Mbps
5052 00:43:15.960452 BS: BS_PRE_DEVICE times (ms): entry 0 run 0 exit 0
5053 00:43:15.966905 BS: BS_DEV_INIT_CHIPS times (ms): entry 0 run 0 exit 0
5054 00:43:15.966983 Enumerating buses...
5055 00:43:15.973507 Show all devs... Before device enumeration.
5056 00:43:15.973585 Root Device: enabled 1
5057 00:43:15.977157 CPU_CLUSTER: 0: enabled 1
5058 00:43:15.977234 CPU: 00: enabled 1
5059 00:43:15.980376 Compare with tree...
5060 00:43:15.983610 Root Device: enabled 1
5061 00:43:15.983686 CPU_CLUSTER: 0: enabled 1
5062 00:43:15.987245 CPU: 00: enabled 1
5063 00:43:15.987322 Root Device scanning...
5064 00:43:15.990207 root_dev_scan_bus for Root Device
5065 00:43:15.993643 CPU_CLUSTER: 0 enabled
5066 00:43:15.996907 root_dev_scan_bus for Root Device done
5067 00:43:16.003558 scan_bus: scanning of bus Root Device took 10690 usecs
5068 00:43:16.003636 done
5069 00:43:16.006978 BS: BS_DEV_ENUMERATE times (ms): entry 0 run 0 exit 0
5070 00:43:16.010395 Allocating resources...
5071 00:43:16.010472 Reading resources...
5072 00:43:16.013729 Root Device read_resources bus 0 link: 0
5073 00:43:16.020360 CPU_CLUSTER: 0 read_resources bus 0 link: 0
5074 00:43:16.020438 CPU: 00 missing read_resources
5075 00:43:16.027082 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
5076 00:43:16.030244 Root Device read_resources bus 0 link: 0 done
5077 00:43:16.030327 Done reading resources.
5078 00:43:16.037122 Show resources in subtree (Root Device)...After reading.
5079 00:43:16.040686 Root Device child on link 0 CPU_CLUSTER: 0
5080 00:43:16.043965 CPU_CLUSTER: 0 child on link 0 CPU: 00
5081 00:43:16.053842 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
5082 00:43:16.053916 CPU: 00
5083 00:43:16.057091 Setting resources...
5084 00:43:16.060353 Root Device assign_resources, bus 0 link: 0
5085 00:43:16.063667 CPU_CLUSTER: 0 missing set_resources
5086 00:43:16.067117 Root Device assign_resources, bus 0 link: 0
5087 00:43:16.070569 Done setting resources.
5088 00:43:16.073924 Show resources in subtree (Root Device)...After assigning values.
5089 00:43:16.080626 Root Device child on link 0 CPU_CLUSTER: 0
5090 00:43:16.083984 CPU_CLUSTER: 0 child on link 0 CPU: 00
5091 00:43:16.090531 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
5092 00:43:16.093917 CPU: 00
5093 00:43:16.093993 Done allocating resources.
5094 00:43:16.100682 BS: BS_DEV_RESOURCES times (ms): entry 0 run 0 exit 0
5095 00:43:16.100770 Enabling resources...
5096 00:43:16.100832 done.
5097 00:43:16.107687 BS: BS_DEV_ENABLE times (ms): entry 0 run 0 exit 0
5098 00:43:16.107765 Initializing devices...
5099 00:43:16.110920 Root Device init ...
5100 00:43:16.114172 mainboard_init: Starting display init.
5101 00:43:16.117206 ADC[4]: Raw value=77032 ID=0
5102 00:43:16.139524 anx7625_power_on_init: Init interface.
5103 00:43:16.143716 anx7625_disable_pd_protocol: Disabled PD feature.
5104 00:43:16.149515 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
5105 00:43:16.206835 anx7625_start_dp_work: Secure OCM version=00
5106 00:43:16.209890 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
5107 00:43:16.226922 sp_tx_get_edid_block: EDID Block = 1
5108 00:43:16.344349 Extracted contents:
5109 00:43:16.347604 header: 00 ff ff ff ff ff ff 00
5110 00:43:16.351008 serial number: 06 af 5c 14 00 00 00 00 00 1a
5111 00:43:16.354449 version: 01 04
5112 00:43:16.357567 basic params: 95 1a 0e 78 02
5113 00:43:16.360973 chroma info: 99 85 95 55 56 92 28 22 50 54
5114 00:43:16.364230 established: 00 00 00
5115 00:43:16.367784 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
5116 00:43:16.374281 descriptor 1: ce 1d 56 ea 50 00 1a 30 30 20 46 00 00 90 10 00 00 18
5117 00:43:16.381061 descriptor 2: 00 00 00 0f 00 00 00 00 00 00 00 00 00 00 00 00 00 20
5118 00:43:16.387588 descriptor 3: 00 00 00 fe 00 41 55 4f 0a 20 20 20 20 20 20 20 20 20
5119 00:43:16.394045 descriptor 4: 00 00 00 fe 00 42 31 31 36 58 41 42 30 31 2e 34 20 0a
5120 00:43:16.397415 extensions: 00
5121 00:43:16.397492 checksum: ae
5122 00:43:16.397552
5123 00:43:16.400818 Manufacturer: AUO Model 145c Serial Number 0
5124 00:43:16.404145 Made week 0 of 2016
5125 00:43:16.404221 EDID version: 1.4
5126 00:43:16.407606 Digital display
5127 00:43:16.410992 6 bits per primary color channel
5128 00:43:16.411070 DisplayPort interface
5129 00:43:16.414340 Maximum image size: 26 cm x 14 cm
5130 00:43:16.417978 Gamma: 220%
5131 00:43:16.418076 Check DPMS levels
5132 00:43:16.420816 Supported color formats: RGB 4:4:4
5133 00:43:16.424223 First detailed timing is preferred timing
5134 00:43:16.427573 Established timings supported:
5135 00:43:16.431151 Standard timings supported:
5136 00:43:16.431227 Detailed timings
5137 00:43:16.434199 Hex of detail: ce1d56ea50001a3030204600009010000018
5138 00:43:16.441056 Detailed mode (IN HEX): Clock 76300 KHz, 100 mm x 90 mm
5139 00:43:16.444421 0556 0586 05a6 0640 hborder 0
5140 00:43:16.447504 0300 0304 030a 031a vborder 0
5141 00:43:16.450817 -hsync -vsync
5142 00:43:16.454389 Did detailed timing
5143 00:43:16.457721 Hex of detail: 0000000f0000000000000000000000000020
5144 00:43:16.461018 Manufacturer-specified data, tag 15
5145 00:43:16.464366 Hex of detail: 000000fe0041554f0a202020202020202020
5146 00:43:16.467778 ASCII string: AUO
5147 00:43:16.471023 Hex of detail: 000000fe004231313658414230312e34200a
5148 00:43:16.474888 ASCII string: B116XAB01.4
5149 00:43:16.474965 Checksum
5150 00:43:16.477676 Checksum: 0xae (valid)
5151 00:43:16.481336 get_active_panel: Found ID 1: 'AUO B116XAB01.4 ' 1366x768@0Hz
5152 00:43:16.484247 DSI data_rate: 457800000 bps
5153 00:43:16.491187 anx7625_parse_edid: set default k value to 0x3d for panel
5154 00:43:16.494347 anx7625_parse_edid: pixelclock(76300).
5155 00:43:16.497718 hactive(1366), hsync(32), hfp(48), hbp(154)
5156 00:43:16.501165 vactive(768), vsync(6), vfp(4), vbp(16)
5157 00:43:16.504642 anx7625_dsi_config: config dsi.
5158 00:43:16.512546 anx7625_dsi_video_config: compute M(12500992), N(552960), divider(8).
5159 00:43:16.534009 anx7625_dsi_config: success to config DSI
5160 00:43:16.536655 anx7625_dp_start: MIPI phy setup OK.
5161 00:43:16.540059 [SSUSB] Setting up USB HOST controller...
5162 00:43:16.543391 [SSUSB] u3phy_ports_enable u2p:1, u3p:0
5163 00:43:16.546955 [SSUSB] phy power-on done.
5164 00:43:16.550723 out: cmd=0xf: 03 da 0f 00 00 00 04 00 10 00 00 00
5165 00:43:16.554085 in-header: 03 fc 01 00 00 00 00 00
5166 00:43:16.554151 in-data:
5167 00:43:16.557698 handle_proto3_response: EC response with error code: 1
5168 00:43:16.560645 SPM: pcm index = 1
5169 00:43:16.564080 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5170 00:43:16.567367 CBFS @ 21000 size 3d4000
5171 00:43:16.574314 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5172 00:43:16.577411 CBFS: Locating 'pcm_allinone_lp4_3200.bin'
5173 00:43:16.580912 CBFS: Found @ offset 1e7c0 size 1026
5174 00:43:16.587422 read SPI 0x3f808 0x1026: 1271 us, 3252 KB/s, 26.016 Mbps
5175 00:43:16.590989 SPM: binary array size = 2988
5176 00:43:16.594114 SPM: version = pcm_allinone_v1.17.2_20180829
5177 00:43:16.597597 SPM binary loaded in 32 msecs
5178 00:43:16.604573 spm_kick_im_to_fetch: ptr = 000000004021eec2
5179 00:43:16.607931 spm_kick_im_to_fetch: len = 2988
5180 00:43:16.608000 SPM: spm_kick_pcm_to_run
5181 00:43:16.611586 SPM: spm_kick_pcm_to_run done
5182 00:43:16.614610 SPM: spm_init done in 52 msecs
5183 00:43:16.618039 Root Device init finished in 505261 usecs
5184 00:43:16.621194 CPU_CLUSTER: 0 init ...
5185 00:43:16.628038 Mapping address range [0000000000200000:0000000000280000) as cacheable | read-write | secure | device
5186 00:43:16.634782 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5187 00:43:16.634859 CBFS @ 21000 size 3d4000
5188 00:43:16.641746 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5189 00:43:16.644926 CBFS: Locating 'sspm.bin'
5190 00:43:16.648263 CBFS: Found @ offset 208c0 size 41cb
5191 00:43:16.658080 read SPI 0x418f8 0x41cb: 5141 us, 3276 KB/s, 26.208 Mbps
5192 00:43:16.665819 CPU_CLUSTER: 0 init finished in 42800 usecs
5193 00:43:16.665896 Devices initialized
5194 00:43:16.669399 Show all devs... After init.
5195 00:43:16.672730 Root Device: enabled 1
5196 00:43:16.672806 CPU_CLUSTER: 0: enabled 1
5197 00:43:16.675671 CPU: 00: enabled 1
5198 00:43:16.679129 BS: BS_DEV_INIT times (ms): entry 0 run 234 exit 0
5199 00:43:16.682410 FMAP: area RW_ELOG found @ 558000 (4096 bytes)
5200 00:43:16.685832 ELOG: NV offset 0x558000 size 0x1000
5201 00:43:16.693483 read SPI 0x558000 0x1000: 1259 us, 3253 KB/s, 26.024 Mbps
5202 00:43:16.700100 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
5203 00:43:16.703390 ELOG: Event(17) added with size 13 at 2024-06-16 00:43:16 UTC
5204 00:43:16.706757 out: cmd=0x121: 03 db 21 01 00 00 00 00
5205 00:43:16.710599 in-header: 03 9e 00 00 2c 00 00 00
5206 00:43:16.723473 in-data: 84 49 00 00 00 00 00 00 02 10 00 00 06 80 00 00 80 a8 09 00 06 80 00 00 3f d2 22 00 06 80 00 00 f8 ea 00 00 06 80 00 00 d5 1f 02 00
5207 00:43:16.726869 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
5208 00:43:16.730142 in-header: 03 19 00 00 08 00 00 00
5209 00:43:16.733409 in-data: a2 e0 47 00 13 00 00 00
5210 00:43:16.736723 Chrome EC: UHEPI supported
5211 00:43:16.743460 out: cmd=0xa4: 03 54 a4 00 00 00 0c 00 00 01 00 00 f8 ff 01 00 00 00 00 00
5212 00:43:16.746866 in-header: 03 e1 00 00 08 00 00 00
5213 00:43:16.750128 in-data: 84 20 60 10 00 00 00 00
5214 00:43:16.753848 FMAP: area RW_NVRAM found @ 554000 (8192 bytes)
5215 00:43:16.760149 out: cmd=0xa4: 03 c9 a4 00 00 00 0c 00 00 01 00 00 00 20 23 40 00 00 00 00
5216 00:43:16.763692 in-header: 03 e1 00 00 08 00 00 00
5217 00:43:16.766851 in-data: 84 20 60 10 00 00 00 00
5218 00:43:16.773628 ELOG: Event(A1) added with size 10 at 2024-06-16 00:43:16 UTC
5219 00:43:16.780201 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
5220 00:43:16.783715 ELOG: Event(A0) added with size 9 at 2024-06-16 00:43:16 UTC
5221 00:43:16.787035 elog_add_boot_reason: Logged dev mode boot
5222 00:43:16.790550 Finalize devices...
5223 00:43:16.790622 Devices finalized
5224 00:43:16.797115 BS: BS_POST_DEVICE times (ms): entry 2 run 0 exit 0
5225 00:43:16.800509 BS: BS_OS_RESUME_CHECK times (ms): entry 0 run 0 exit 0
5226 00:43:16.806821 ELOG: Event(91) added with size 10 at 2024-06-16 00:43:16 UTC
5227 00:43:16.810293 Writing coreboot table at 0xffeda000
5228 00:43:16.813545 0. 0000000000114000-000000000011efff: RAMSTAGE
5229 00:43:16.816814 1. 0000000040000000-000000004023cfff: RAMSTAGE
5230 00:43:16.823618 2. 000000004023d000-00000000545fffff: RAM
5231 00:43:16.826739 3. 0000000054600000-000000005465ffff: BL31
5232 00:43:16.830060 4. 0000000054660000-00000000ffed9fff: RAM
5233 00:43:16.836970 5. 00000000ffeda000-00000000ffffffff: CONFIGURATION TABLES
5234 00:43:16.840283 6. 0000000100000000-000000013fffffff: RAM
5235 00:43:16.840349 Passing 5 GPIOs to payload:
5236 00:43:16.846881 NAME | PORT | POLARITY | VALUE
5237 00:43:16.850093 write protect | 0x00000096 | low | high
5238 00:43:16.856854 EC in RW | 0x000000b1 | high | undefined
5239 00:43:16.860025 EC interrupt | 0x00000097 | low | undefined
5240 00:43:16.863689 TPM interrupt | 0x00000099 | high | undefined
5241 00:43:16.870013 speaker enable | 0x000000af | high | undefined
5242 00:43:16.873472 out: cmd=0x6: 03 f7 06 00 00 00 00 00
5243 00:43:16.876907 in-header: 03 f7 00 00 02 00 00 00
5244 00:43:16.876972 in-data: 04 00
5245 00:43:16.880414 Board ID: 4
5246 00:43:16.880474 ADC[3]: Raw value=1040656 ID=8
5247 00:43:16.883404 RAM code: 8
5248 00:43:16.883463 SKU ID: 16
5249 00:43:16.886963 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5250 00:43:16.890296 CBFS @ 21000 size 3d4000
5251 00:43:16.897076 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5252 00:43:16.900270 Wrote coreboot table at: 00000000ffeda000, 0x394 bytes, checksum 5a2
5253 00:43:16.903685 coreboot table: 940 bytes.
5254 00:43:16.906859 IMD ROOT 0. 00000000fffff000 00001000
5255 00:43:16.910319 IMD SMALL 1. 00000000ffffe000 00001000
5256 00:43:16.913542 CONSOLE 2. 00000000fffde000 00020000
5257 00:43:16.920256 FMAP 3. 00000000fffdd000 0000047c
5258 00:43:16.923641 TIME STAMP 4. 00000000fffdc000 00000910
5259 00:43:16.926742 RAMOOPS 5. 00000000ffedc000 00100000
5260 00:43:16.929985 COREBOOT 6. 00000000ffeda000 00002000
5261 00:43:16.930050 IMD small region:
5262 00:43:16.933719 IMD ROOT 0. 00000000ffffec00 00000400
5263 00:43:16.940035 VBOOT WORK 1. 00000000ffffeb00 00000100
5264 00:43:16.943628 EC HOSTEVENT 2. 00000000ffffeae0 00000008
5265 00:43:16.946879 VPD 3. 00000000ffffea60 0000006c
5266 00:43:16.949939 BS: BS_WRITE_TABLES times (ms): entry 0 run 0 exit 0
5267 00:43:16.957095 out: cmd=0xa4: 03 95 a4 00 00 00 0c 00 00 01 00 00 24 32 21 40 00 00 00 00
5268 00:43:16.960315 in-header: 03 e1 00 00 08 00 00 00
5269 00:43:16.963314 in-data: 84 20 60 10 00 00 00 00
5270 00:43:16.970090 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5271 00:43:16.970161 CBFS @ 21000 size 3d4000
5272 00:43:16.976926 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5273 00:43:16.980060 CBFS: Locating 'fallback/payload'
5274 00:43:16.987328 CBFS: Found @ offset dc040 size 439a0
5275 00:43:17.075235 read SPI 0xfd078 0x439a0: 84379 us, 3281 KB/s, 26.248 Mbps
5276 00:43:17.078600 Checking segment from ROM address 0x0000000040003a00
5277 00:43:17.085407 Checking segment from ROM address 0x0000000040003a1c
5278 00:43:17.088620 Loading segment from ROM address 0x0000000040003a00
5279 00:43:17.091849 code (compression=0)
5280 00:43:17.101772 New segment dstaddr 0x0000000080000000 memsize 0x11994a0 srcaddr 0x0000000040003a38 filesize 0x43968
5281 00:43:17.108388 Loading Segment: addr: 0x0000000080000000 memsz: 0x00000000011994a0 filesz: 0x0000000000043968
5282 00:43:17.112783 it's not compressed!
5283 00:43:17.115198 [ 0x80000000, 80043968, 0x811994a0) <- 40003a38
5284 00:43:17.121852 Clearing Segment: addr: 0x0000000080043968 memsz: 0x0000000001155b38
5285 00:43:17.129585 Loading segment from ROM address 0x0000000040003a1c
5286 00:43:17.132874 Entry Point 0x0000000080000000
5287 00:43:17.132937 Loaded segments
5288 00:43:17.139875 BS: BS_PAYLOAD_LOAD times (ms): entry 0 run 92 exit 0
5289 00:43:17.142967 Jumping to boot code at 0000000080000000(00000000ffeda000)
5290 00:43:17.152864 CPU0: stack: 0000000000114000 - 0000000000118000, lowest used address 0000000000117540, stack used: 2752 bytes
5291 00:43:17.156117 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5292 00:43:17.159492 CBFS @ 21000 size 3d4000
5293 00:43:17.166279 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5294 00:43:17.166343 CBFS: Locating 'fallback/bl31'
5295 00:43:17.169953 CBFS: Found @ offset 36dc0 size 5820
5296 00:43:17.183238 read SPI 0x57de8 0x5820: 6880 us, 3279 KB/s, 26.232 Mbps
5297 00:43:17.186626 Checking segment from ROM address 0x0000000040003a00
5298 00:43:17.193557 Checking segment from ROM address 0x0000000040003a1c
5299 00:43:17.196855 Loading segment from ROM address 0x0000000040003a00
5300 00:43:17.200308 code (compression=1)
5301 00:43:17.206588 New segment dstaddr 0x0000000054600000 memsize 0x29000 srcaddr 0x0000000040003a38 filesize 0x57e8
5302 00:43:17.216590 Loading Segment: addr: 0x0000000054600000 memsz: 0x0000000000029000 filesz: 0x00000000000057e8
5303 00:43:17.216664 using LZMA
5304 00:43:17.225375 [ 0x54600000, 5460f420, 0x54629000) <- 40003a38
5305 00:43:17.232002 Clearing Segment: addr: 0x000000005460f420 memsz: 0x0000000000019be0
5306 00:43:17.235251 Loading segment from ROM address 0x0000000040003a1c
5307 00:43:17.238667 Entry Point 0x0000000054601000
5308 00:43:17.238733 Loaded segments
5309 00:43:17.241930 NOTICE: MT8183 bl31_setup
5310 00:43:17.248893 NOTICE: BL31: v2.1(debug):v2.1-806-g3addeb68c
5311 00:43:17.252358 NOTICE: BL31: Built : Sun Jan 30 03:25:20 UTC 2022
5312 00:43:17.255580 INFO: [DEVAPC] dump DEVAPC registers:
5313 00:43:17.265636 INFO: [DEVAPC] (INFRA)D0_APC_0 = 0x0, (INFRA)D1_APC_0 = 0xfcfffffc, (INFRA)D2_APC_0 = 0x0
5314 00:43:17.272509 INFO: [DEVAPC] (INFRA)D0_APC_1 = 0x0, (INFRA)D1_APC_1 = 0xffffffff, (INFRA)D2_APC_1 = 0x0
5315 00:43:17.279276 INFO: [DEVAPC] (INFRA)D0_APC_2 = 0x0, (INFRA)D1_APC_2 = 0xffffffff, (INFRA)D2_APC_2 = 0x0
5316 00:43:17.289075 INFO: [DEVAPC] (INFRA)D0_APC_3 = 0x0, (INFRA)D1_APC_3 = 0xffffffff, (INFRA)D2_APC_3 = 0x0
5317 00:43:17.299129 INFO: [DEVAPC] (INFRA)D0_APC_4 = 0x80000000, (INFRA)D1_APC_4 = 0xffffffff, (INFRA)D2_APC_4 = 0x0
5318 00:43:17.305858 INFO: [DEVAPC] (INFRA)D0_APC_5 = 0x2aaa, (INFRA)D1_APC_5 = 0xfcff3fff, (INFRA)D2_APC_5 = 0x0
5319 00:43:17.312462 INFO: [DEVAPC] (INFRA)D0_APC_6 = 0x0, (INFRA)D1_APC_6 = 0xffffffff, (INFRA)D2_APC_6 = 0x0
5320 00:43:17.322285 INFO: [DEVAPC] (INFRA)D0_APC_7 = 0x0, (INFRA)D1_APC_7 = 0xffffffff, (INFRA)D2_APC_7 = 0x0
5321 00:43:17.328914 INFO: [DEVAPC] (INFRA)D0_APC_8 = 0x0, (INFRA)D1_APC_8 = 0xffffffff, (INFRA)D2_APC_8 = 0x0
5322 00:43:17.339020 INFO: [DEVAPC] (INFRA)D0_APC_9 = 0x0, (INFRA)D1_APC_9 = 0xffffffff, (INFRA)D2_APC_9 = 0x0
5323 00:43:17.346015 INFO: [DEVAPC] (INFRA)D0_APC_10 = 0x0, (INFRA)D1_APC_10 = 0xffffffff, (INFRA)D2_APC_10 = 0x0
5324 00:43:17.355863 INFO: [DEVAPC] (INFRA)D0_APC_11 = 0x0, (INFRA)D1_APC_11 = 0xffffffff, (INFRA)D2_APC_11 = 0x0
5325 00:43:17.362503 INFO: [DEVAPC] (INFRA)D0_APC_12 = 0x0, (INFRA)D1_APC_12 = 0xff, (INFRA)D2_APC_12 = 0x0
5326 00:43:17.369204 INFO: [DEVAPC] (MM)D0_APC_0 = 0x0, (MM)D1_APC_0 = 0xffc000ff, (MM)D2_APC_0 = 0x0
5327 00:43:17.376128 INFO: [DEVAPC] (MM)D0_APC_1 = 0x0, (MM)D1_APC_1 = 0x3fffffff, (MM)D2_APC_1 = 0x0
5328 00:43:17.385916 INFO: [DEVAPC] (MM)D0_APC_2 = 0x0, (MM)D1_APC_2 = 0xcffff33c, (MM)D2_APC_2 = 0x0
5329 00:43:17.392911 INFO: [DEVAPC] (MM)D0_APC_3 = 0x0, (MM)D1_APC_3 = 0x3ccfc0ff, (MM)D2_APC_3 = 0x0
5330 00:43:17.399518 INFO: [DEVAPC] (MM)D0_APC_4 = 0x0, (MM)D1_APC_4 = 0xffff0000, (MM)D2_APC_4 = 0x0
5331 00:43:17.405937 INFO: [DEVAPC] (MM)D0_APC_5 = 0x0, (MM)D1_APC_5 = 0xffffffff, (MM)D2_APC_5 = 0x0
5332 00:43:17.412646 INFO: [DEVAPC] (MM)D0_APC_6 = 0x0, (MM)D1_APC_6 = 0xffffffff, (MM)D2_APC_6 = 0x0
5333 00:43:17.422855 INFO: [DEVAPC] (MM)D0_APC_7 = 0x0, (MM)D1_APC_7 = 0xffffffff, (MM)D2_APC_7 = 0x0
5334 00:43:17.429496 INFO: [DEVAPC] (MM)D0_APC_8 = 0x0, (MM)D1_APC_8 = 0x3ffffff, (MM)D2_APC_8 = 0x0
5335 00:43:17.432789 INFO: [DEVAPC] MAS_DOM_0 = 0x1
5336 00:43:17.436143 INFO: [DEVAPC] MAS_DOM_1 = 0x200
5337 00:43:17.439743 INFO: [DEVAPC] MAS_DOM_2 = 0x0
5338 00:43:17.443161 INFO: [DEVAPC] MAS_DOM_3 = 0x2000
5339 00:43:17.446159 INFO: [DEVAPC] MAS_SEC_0 = 0x8000000
5340 00:43:17.452761 INFO: [DEVAPC] (INFRA)MAS_DOMAIN_REMAP_0 = 0x88, (INFRA)MAS_DOMAIN_REMAP_1 = 0x0
5341 00:43:17.456206 INFO: [DEVAPC] (MM)MAS_DOMAIN_REMAP_0 = 0x24
5342 00:43:17.459416 WARNING: region 0:
5343 00:43:17.462831 WARNING: apc:0x168, sa:0x0, ea:0xfff
5344 00:43:17.462900 WARNING: region 1:
5345 00:43:17.466104 WARNING: apc:0x140, sa:0x1000, ea:0x128f
5346 00:43:17.469300 WARNING: region 2:
5347 00:43:17.472726 WARNING: apc:0x168, sa:0x1290, ea:0x1fff
5348 00:43:17.472797 WARNING: region 3:
5349 00:43:17.479559 WARNING: apc:0x168, sa:0x2000, ea:0xbfff
5350 00:43:17.479628 WARNING: region 4:
5351 00:43:17.482799 WARNING: apc:0x168, sa:0xc000, ea:0x1ffff
5352 00:43:17.486283 WARNING: region 5:
5353 00:43:17.489353 WARNING: apc:0x0, sa:0x0, ea:0x0
5354 00:43:17.489418 WARNING: region 6:
5355 00:43:17.492826 WARNING: apc:0x0, sa:0x0, ea:0x0
5356 00:43:17.496142 WARNING: region 7:
5357 00:43:17.499158 WARNING: apc:0x0, sa:0x0, ea:0x0
5358 00:43:17.506085 INFO: GICv3 without legacy support detected. ARM GICv3 driver initialized in EL3
5359 00:43:17.509361 INFO: SPM: enable SPMC mode
5360 00:43:17.509428 NOTICE: spm_boot_init() start
5361 00:43:17.512804 NOTICE: spm_boot_init() end
5362 00:43:17.516070 INFO: BL31: Initializing runtime services
5363 00:43:17.522653 INFO: BL31: cortex_a53: CPU workaround for 855873 was applied
5364 00:43:17.529378 INFO: BL31: Preparing for EL3 exit to normal world
5365 00:43:17.532679 INFO: Entry point address = 0x80000000
5366 00:43:17.532774 INFO: SPSR = 0x8
5367 00:43:17.555476
5368 00:43:17.555550
5369 00:43:17.555608
5370 00:43:17.555662 Starting depthcharge on Juniper...
5371 00:43:17.556087 end: 2.2.3 depthcharge-start (duration 00:00:10) [common]
5372 00:43:17.556180 start: 2.2.4 bootloader-commands (timeout 00:04:28) [common]
5373 00:43:17.556259 Setting prompt string to ['jacuzzi:']
5374 00:43:17.556328 bootloader-commands: Wait for prompt ['jacuzzi:'] (timeout 00:04:28)
5375 00:43:17.558693
5376 00:43:17.561950 vboot_handoff: creating legacy vboot_handoff structure
5377 00:43:17.562026
5378 00:43:17.565360 ec_init(0): CrosEC protocol v3 supported (544, 544)
5379 00:43:17.565438
5380 00:43:17.568763 Wipe memory regions:
5381 00:43:17.568829
5382 00:43:17.571895 [0x00000040000000, 0x00000054600000)
5383 00:43:17.614783
5384 00:43:17.614864 [0x00000054660000, 0x00000080000000)
5385 00:43:17.706075
5386 00:43:17.706194 [0x000000811994a0, 0x000000ffeda000)
5387 00:43:17.965461
5388 00:43:17.965572 [0x00000100000000, 0x00000140000000)
5389 00:43:18.098221
5390 00:43:18.101453 Initializing XHCI USB controller at 0x11200000.
5391 00:43:18.124557
5392 00:43:18.127726 [firmware-jacuzzi-12573.B-collabora] Jun 8 2022 08:18:54
5393 00:43:18.127794
5394 00:43:18.127850
5395 00:43:18.128113 Setting prompt string to ['jacuzzi:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
5397 00:43:18.228404 jacuzzi: tftpboot 192.168.201.1 14368368/tftp-deploy-pdqfsrpp/kernel/image.itb 14368368/tftp-deploy-pdqfsrpp/kernel/cmdline
5398 00:43:18.228984 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
5399 00:43:18.229386 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:27)
5400 00:43:18.233372 tftpboot 192.168.201.1 14368368/tftp-deploy-pdqfsrpp/kernel/image.ittp-deploy-pdqfsrpp/kernel/cmdline
5401 00:43:18.233785
5402 00:43:18.234100 Waiting for link
5403 00:43:18.784507
5404 00:43:18.784978 R8152: Initializing
5405 00:43:18.785304
5406 00:43:18.787685 Version 9 (ocp_data = 6010)
5407 00:43:18.788119
5408 00:43:18.791368 R8152: Done initializing
5409 00:43:18.791755
5410 00:43:18.792070 Adding net device
5411 00:43:18.970120
5412 00:43:18.970597 R8152: Initializing
5413 00:43:18.970913
5414 00:43:18.973164 Version 9 (ocp_data = 6010)
5415 00:43:18.973514
5416 00:43:18.976669 R8152: Done initializing
5417 00:43:18.977017
5418 00:43:18.980089 net_add_device: Attemp to include the same device
5419 00:43:19.365492
5420 00:43:19.365613 done.
5421 00:43:19.365675
5422 00:43:19.365730 MAC: 00:e0:4c:68:03:2b
5423 00:43:19.365783
5424 00:43:19.368899 Sending DHCP discover... done.
5425 00:43:19.368963
5426 00:43:19.372406 Waiting for reply... done.
5427 00:43:19.372471
5428 00:43:19.375475 Sending DHCP request... done.
5429 00:43:19.375543
5430 00:43:19.380476 Waiting for reply... done.
5431 00:43:19.380537
5432 00:43:19.380588 My ip is 192.168.201.17
5433 00:43:19.380638
5434 00:43:19.383954 The DHCP server ip is 192.168.201.1
5435 00:43:19.384019
5436 00:43:19.390742 TFTP server IP predefined by user: 192.168.201.1
5437 00:43:19.390812
5438 00:43:19.397114 Bootfile predefined by user: 14368368/tftp-deploy-pdqfsrpp/kernel/image.itb
5439 00:43:19.397184
5440 00:43:19.397238 Sending tftp read request... done.
5441 00:43:19.400191
5442 00:43:19.403765 Waiting for the transfer...
5443 00:43:19.403834
5444 00:43:19.653739 00000000 ################################################################
5445 00:43:19.653881
5446 00:43:19.927378 00080000 ################################################################
5447 00:43:19.927528
5448 00:43:20.203237 00100000 ################################################################
5449 00:43:20.203359
5450 00:43:20.460441 00180000 ################################################################
5451 00:43:20.460595
5452 00:43:20.711015 00200000 ################################################################
5453 00:43:20.711153
5454 00:43:20.959639 00280000 ################################################################
5455 00:43:20.959781
5456 00:43:21.211737 00300000 ################################################################
5457 00:43:21.211866
5458 00:43:21.482758 00380000 ################################################################
5459 00:43:21.482884
5460 00:43:21.759142 00400000 ################################################################
5461 00:43:21.759254
5462 00:43:22.023375 00480000 ################################################################
5463 00:43:22.023497
5464 00:43:22.281328 00500000 ################################################################
5465 00:43:22.281465
5466 00:43:22.536284 00580000 ################################################################
5467 00:43:22.536417
5468 00:43:22.795400 00600000 ################################################################
5469 00:43:22.795564
5470 00:43:23.049742 00680000 ################################################################
5471 00:43:23.049872
5472 00:43:23.310138 00700000 ################################################################
5473 00:43:23.310262
5474 00:43:23.562221 00780000 ################################################################
5475 00:43:23.562341
5476 00:43:23.816016 00800000 ################################################################
5477 00:43:23.816133
5478 00:43:24.081893 00880000 ################################################################
5479 00:43:24.082037
5480 00:43:24.337365 00900000 ################################################################
5481 00:43:24.337500
5482 00:43:24.609755 00980000 ################################################################
5483 00:43:24.609911
5484 00:43:24.879027 00a00000 ################################################################
5485 00:43:24.879199
5486 00:43:25.130417 00a80000 ################################################################
5487 00:43:25.130553
5488 00:43:25.382174 00b00000 ################################################################
5489 00:43:25.382307
5490 00:43:25.633102 00b80000 ################################################################
5491 00:43:25.633269
5492 00:43:25.882951 00c00000 ################################################################
5493 00:43:25.883101
5494 00:43:26.136307 00c80000 ################################################################
5495 00:43:26.136424
5496 00:43:26.409702 00d00000 ################################################################
5497 00:43:26.409855
5498 00:43:26.660981 00d80000 ################################################################
5499 00:43:26.661142
5500 00:43:26.915017 00e00000 ################################################################
5501 00:43:26.915147
5502 00:43:27.170190 00e80000 ################################################################
5503 00:43:27.170370
5504 00:43:27.420782 00f00000 ################################################################
5505 00:43:27.420931
5506 00:43:27.671140 00f80000 ################################################################
5507 00:43:27.671256
5508 00:43:27.923798 01000000 ################################################################
5509 00:43:27.923911
5510 00:43:28.178148 01080000 ################################################################
5511 00:43:28.178340
5512 00:43:28.450847 01100000 ################################################################
5513 00:43:28.450968
5514 00:43:28.709935 01180000 ################################################################
5515 00:43:28.710048
5516 00:43:28.968542 01200000 ################################################################
5517 00:43:28.968660
5518 00:43:29.233776 01280000 ################################################################
5519 00:43:29.233896
5520 00:43:29.483637 01300000 ################################################################
5521 00:43:29.483793
5522 00:43:29.736985 01380000 ################################################################
5523 00:43:29.737130
5524 00:43:29.999994 01400000 ################################################################
5525 00:43:30.000131
5526 00:43:30.251766 01480000 ################################################################
5527 00:43:30.251887
5528 00:43:30.503607 01500000 ################################################################
5529 00:43:30.503736
5530 00:43:30.759594 01580000 ################################################################
5531 00:43:30.759713
5532 00:43:31.028879 01600000 ################################################################
5533 00:43:31.028998
5534 00:43:31.285609 01680000 ################################################################
5535 00:43:31.285730
5536 00:43:31.537595 01700000 ################################################################
5537 00:43:31.537716
5538 00:43:31.792967 01780000 ################################################################
5539 00:43:31.793110
5540 00:43:32.067865 01800000 ################################################################
5541 00:43:32.067984
5542 00:43:32.319299 01880000 ################################################################
5543 00:43:32.319435
5544 00:43:32.576323 01900000 ################################################################
5545 00:43:32.576500
5546 00:43:32.829823 01980000 ################################################################
5547 00:43:32.829968
5548 00:43:33.100075 01a00000 ################################################################
5549 00:43:33.100216
5550 00:43:33.350938 01a80000 ################################################################
5551 00:43:33.351062
5552 00:43:33.618352 01b00000 ################################################################
5553 00:43:33.618505
5554 00:43:33.891874 01b80000 ################################################################
5555 00:43:33.892036
5556 00:43:34.168288 01c00000 ################################################################
5557 00:43:34.168396
5558 00:43:34.421585 01c80000 ################################################################
5559 00:43:34.421734
5560 00:43:34.680392 01d00000 ################################################################
5561 00:43:34.680529
5562 00:43:34.931400 01d80000 ################################################################
5563 00:43:34.931508
5564 00:43:35.152757 01e00000 ######################################################### done.
5565 00:43:35.152867
5566 00:43:35.155823 The bootfile was 31919322 bytes long.
5567 00:43:35.155897
5568 00:43:35.158999 Sending tftp read request... done.
5569 00:43:35.159091
5570 00:43:35.162420 Waiting for the transfer...
5571 00:43:35.162487
5572 00:43:35.162546 00000000 # done.
5573 00:43:35.162602
5574 00:43:35.172359 Command line loaded dynamically from TFTP file: 14368368/tftp-deploy-pdqfsrpp/kernel/cmdline
5575 00:43:35.172456
5576 00:43:35.195708 The command line is: earlyprintk=ttyS0,115200n8 console=tty1 console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14368368/extract-nfsrootfs-vnd37feq,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
5577 00:43:35.195789
5578 00:43:35.199242 Loading FIT.
5579 00:43:35.199314
5580 00:43:35.202271 Image ramdisk-1 has 18733210 bytes.
5581 00:43:35.202344
5582 00:43:35.202400 Image fdt-1 has 57695 bytes.
5583 00:43:35.205703
5584 00:43:35.205793 Image kernel-1 has 13126376 bytes.
5585 00:43:35.205874
5586 00:43:35.215783 Compat preference: google,juniper-rev4-sku16 google,juniper-sku16 google,juniper-rev4 google,juniper
5587 00:43:35.215852
5588 00:43:35.229287 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,juniper-sku16 (match) google,juniper mediatek,mt8183
5589 00:43:35.229387
5590 00:43:35.232725 Choosing best match conf-1 for compat google,juniper-sku16.
5591 00:43:35.237786
5592 00:43:35.242281 Connected to device vid:did:rid of 1ae0:0028:00
5593 00:43:35.249721
5594 00:43:35.252412 tpm_get_response: command 0x17b, return code 0x0
5595 00:43:35.252501
5596 00:43:35.256046 tpm_cleanup: add release locality here.
5597 00:43:35.256112
5598 00:43:35.259405 Shutting down all USB controllers.
5599 00:43:35.259490
5600 00:43:35.262775 Removing current net device
5601 00:43:35.262855
5602 00:43:35.266194 Exiting depthcharge with code 4 at timestamp: 34091791
5603 00:43:35.266316
5604 00:43:35.269561 LZMA decompressing kernel-1 to 0x80193568
5605 00:43:35.269652
5606 00:43:35.273159 LZMA decompressing kernel-1 to 0x40000000
5607 00:43:37.140505
5608 00:43:37.140616 jumping to kernel
5609 00:43:37.141445 end: 2.2.4 bootloader-commands (duration 00:00:20) [common]
5610 00:43:37.141539 start: 2.2.5 auto-login-action (timeout 00:04:08) [common]
5611 00:43:37.141609 Setting prompt string to ['Linux version [0-9]']
5612 00:43:37.141673 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
5613 00:43:37.141742 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
5614 00:43:37.215678
5615 00:43:37.218889 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd034]
5616 00:43:37.222337 start: 2.2.5.1 login-action (timeout 00:04:08) [common]
5617 00:43:37.222452 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
5618 00:43:37.222546 Setting prompt string to []
5619 00:43:37.222643 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
5620 00:43:37.222734 Using line separator: #'\n'#
5621 00:43:37.222814 No login prompt set.
5622 00:43:37.222873 Parsing kernel messages
5623 00:43:37.222925 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
5624 00:43:37.223017 [login-action] Waiting for messages, (timeout 00:04:08)
5625 00:43:37.223077 Waiting using forced prompt support (timeout 00:02:04)
5626 00:43:37.242322 [ 0.000000] Linux version 6.1.92-cip22 (KernelCI@build-j232175-arm64-gcc-10-defconfig-arm64-chromebook-7lg8d) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sun Jun 16 00:28:47 UTC 2024
5627 00:43:37.245566 [ 0.000000] random: crng init done
5628 00:43:37.252482 [ 0.000000] Machine model: Google juniper sku16 board
5629 00:43:37.252576 [ 0.000000] efi: UEFI not found.
5630 00:43:37.262405 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
5631 00:43:37.268897 [ 0.000000] OF: reserved mem: initialized node memory@50000000, compatible id shared-dma-pool
5632 00:43:37.279171 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
5633 00:43:37.282184 [ 0.000000] printk: bootconsole [mtk8250] enabled
5634 00:43:37.290657 [ 0.000000] NUMA: No NUMA configuration found
5635 00:43:37.297164 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000013fffffff]
5636 00:43:37.304114 [ 0.000000] NUMA: NODE_DATA [mem 0x13f7bea00-0x13f7c0fff]
5637 00:43:37.304183 [ 0.000000] Zone ranges:
5638 00:43:37.310727 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
5639 00:43:37.314163 [ 0.000000] DMA32 empty
5640 00:43:37.320550 [ 0.000000] Normal [mem 0x0000000100000000-0x000000013fffffff]
5641 00:43:37.323851 [ 0.000000] Movable zone start for each node
5642 00:43:37.327357 [ 0.000000] Early memory node ranges
5643 00:43:37.333811 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
5644 00:43:37.340667 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
5645 00:43:37.347187 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
5646 00:43:37.353744 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
5647 00:43:37.360400 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000013fffffff]
5648 00:43:37.367031 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000013fffffff]
5649 00:43:37.383337 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
5650 00:43:37.389305 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
5651 00:43:37.396011 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
5652 00:43:37.399374 [ 0.000000] psci: probing for conduit method from DT.
5653 00:43:37.406062 [ 0.000000] psci: PSCIv1.1 detected in firmware.
5654 00:43:37.409596 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
5655 00:43:37.416166 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
5656 00:43:37.419687 [ 0.000000] psci: SMC Calling Convention v1.1
5657 00:43:37.426335 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
5658 00:43:37.429548 [ 0.000000] Detected VIPT I-cache on CPU0
5659 00:43:37.436218 [ 0.000000] CPU features: detected: GIC system register CPU interface
5660 00:43:37.442830 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
5661 00:43:37.449581 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
5662 00:43:37.452732 [ 0.000000] CPU features: detected: ARM erratum 845719
5663 00:43:37.459490 [ 0.000000] alternatives: applying boot alternatives
5664 00:43:37.462999 [ 0.000000] Fallback order for Node 0: 0
5665 00:43:37.469439 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1031424
5666 00:43:37.473017 [ 0.000000] Policy zone: Normal
5667 00:43:37.499449 [ 0.000000] Kernel command line: earlyprintk=ttyS0,115200n8 console=tty1 console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14368368/extract-nfsrootfs-vnd37feq,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
5668 00:43:37.512911 <5>[ 0.000000] Unknown kernel command line parameters "earlyprintk=ttyS0,115200n8 tftpserverip=192.168.201.1", will be passed to user space.
5669 00:43:37.522932 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
5670 00:43:37.529761 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
5671 00:43:37.536037 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
5672 00:43:37.539758 <6>[ 0.000000] software IO TLB: area num 8.
5673 00:43:37.566239 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
5674 00:43:37.624310 <6>[ 0.000000] Memory: 3896776K/4191232K available (18112K kernel code, 4120K rwdata, 22644K rodata, 8512K init, 616K bss, 261688K reserved, 32768K cma-reserved)
5675 00:43:37.630903 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
5676 00:43:37.637715 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
5677 00:43:37.640932 <6>[ 0.000000] rcu: RCU event tracing is enabled.
5678 00:43:37.647563 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
5679 00:43:37.654318 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
5680 00:43:37.657728 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
5681 00:43:37.667832 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
5682 00:43:37.674296 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
5683 00:43:37.677532 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
5684 00:43:37.689479 <6>[ 0.000000] GIC: enabling workaround for GICv3: Mediatek Chromebook GICR save problem
5685 00:43:37.696060 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
5686 00:43:37.699506 <6>[ 0.000000] GICv3: 640 SPIs implemented
5687 00:43:37.702548 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
5688 00:43:37.706314 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
5689 00:43:37.712829 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
5690 00:43:37.719286 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c100000
5691 00:43:37.729528 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@1[1] /cpus/cpu@2[2] /cpus/cpu@3[3] }
5692 00:43:37.742914 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@100[4] /cpus/cpu@101[5] /cpus/cpu@102[6] /cpus/cpu@103[7] }
5693 00:43:37.749434 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
5694 00:43:37.761220 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
5695 00:43:37.774585 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
5696 00:43:37.781138 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
5697 00:43:37.787999 <6>[ 0.009468] Console: colour dummy device 80x25
5698 00:43:37.791504 <6>[ 0.014511] printk: console [tty1] enabled
5699 00:43:37.801182 <6>[ 0.018896] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
5700 00:43:37.808193 <6>[ 0.029361] pid_max: default: 32768 minimum: 301
5701 00:43:37.811281 <6>[ 0.034243] LSM: Security Framework initializing
5702 00:43:37.821352 <6>[ 0.039159] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
5703 00:43:37.827875 <6>[ 0.046783] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
5704 00:43:37.834552 <4>[ 0.055651] cacheinfo: Unable to detect cache hierarchy for CPU 0
5705 00:43:37.844823 <6>[ 0.062278] cblist_init_generic: Setting adjustable number of callback queues.
5706 00:43:37.847974 <6>[ 0.069723] cblist_init_generic: Setting shift to 3 and lim to 1.
5707 00:43:37.857903 <6>[ 0.076076] cblist_init_generic: Setting adjustable number of callback queues.
5708 00:43:37.864566 <6>[ 0.083521] cblist_init_generic: Setting shift to 3 and lim to 1.
5709 00:43:37.867919 <6>[ 0.089919] rcu: Hierarchical SRCU implementation.
5710 00:43:37.874504 <6>[ 0.094945] rcu: Max phase no-delay instances is 1000.
5711 00:43:37.881139 <6>[ 0.102869] EFI services will not be available.
5712 00:43:37.884633 <6>[ 0.107818] smp: Bringing up secondary CPUs ...
5713 00:43:37.895263 <6>[ 0.113082] Detected VIPT I-cache on CPU1
5714 00:43:37.901642 <4>[ 0.113129] cacheinfo: Unable to detect cache hierarchy for CPU 1
5715 00:43:37.908457 <6>[ 0.113139] GICv3: CPU1: found redistributor 1 region 0:0x000000000c120000
5716 00:43:37.915010 <6>[ 0.113171] CPU1: Booted secondary processor 0x0000000001 [0x410fd034]
5717 00:43:37.918543 <6>[ 0.113652] Detected VIPT I-cache on CPU2
5718 00:43:37.925406 <4>[ 0.113685] cacheinfo: Unable to detect cache hierarchy for CPU 2
5719 00:43:37.931676 <6>[ 0.113690] GICv3: CPU2: found redistributor 2 region 0:0x000000000c140000
5720 00:43:37.938338 <6>[ 0.113702] CPU2: Booted secondary processor 0x0000000002 [0x410fd034]
5721 00:43:37.941813 <6>[ 0.114147] Detected VIPT I-cache on CPU3
5722 00:43:37.948239 <4>[ 0.114178] cacheinfo: Unable to detect cache hierarchy for CPU 3
5723 00:43:37.954937 <6>[ 0.114183] GICv3: CPU3: found redistributor 3 region 0:0x000000000c160000
5724 00:43:37.961590 <6>[ 0.114193] CPU3: Booted secondary processor 0x0000000003 [0x410fd034]
5725 00:43:37.968284 <6>[ 0.114767] CPU features: detected: Spectre-v2
5726 00:43:37.971708 <6>[ 0.114777] CPU features: detected: Spectre-BHB
5727 00:43:37.978363 <6>[ 0.114781] CPU features: detected: ARM erratum 858921
5728 00:43:37.981739 <6>[ 0.114786] Detected VIPT I-cache on CPU4
5729 00:43:37.988329 <4>[ 0.114834] cacheinfo: Unable to detect cache hierarchy for CPU 4
5730 00:43:37.994970 <6>[ 0.114841] GICv3: CPU4: found redistributor 100 region 0:0x000000000c180000
5731 00:43:38.001832 <6>[ 0.114850] arch_timer: Enabling local workaround for ARM erratum 858921
5732 00:43:38.008351 <6>[ 0.114860] arch_timer: CPU4: Trapping CNTVCT access
5733 00:43:38.014952 <6>[ 0.114868] CPU4: Booted secondary processor 0x0000000100 [0x410fd092]
5734 00:43:38.018381 <6>[ 0.115354] Detected VIPT I-cache on CPU5
5735 00:43:38.024835 <4>[ 0.115395] cacheinfo: Unable to detect cache hierarchy for CPU 5
5736 00:43:38.031573 <6>[ 0.115400] GICv3: CPU5: found redistributor 101 region 0:0x000000000c1a0000
5737 00:43:38.038013 <6>[ 0.115407] arch_timer: Enabling local workaround for ARM erratum 858921
5738 00:43:38.044745 <6>[ 0.115414] arch_timer: CPU5: Trapping CNTVCT access
5739 00:43:38.051446 <6>[ 0.115418] CPU5: Booted secondary processor 0x0000000101 [0x410fd092]
5740 00:43:38.054908 <6>[ 0.115854] Detected VIPT I-cache on CPU6
5741 00:43:38.061379 <4>[ 0.115900] cacheinfo: Unable to detect cache hierarchy for CPU 6
5742 00:43:38.068209 <6>[ 0.115906] GICv3: CPU6: found redistributor 102 region 0:0x000000000c1c0000
5743 00:43:38.074841 <6>[ 0.115913] arch_timer: Enabling local workaround for ARM erratum 858921
5744 00:43:38.081472 <6>[ 0.115919] arch_timer: CPU6: Trapping CNTVCT access
5745 00:43:38.088235 <6>[ 0.115924] CPU6: Booted secondary processor 0x0000000102 [0x410fd092]
5746 00:43:38.091347 <6>[ 0.116454] Detected VIPT I-cache on CPU7
5747 00:43:38.098007 <4>[ 0.116497] cacheinfo: Unable to detect cache hierarchy for CPU 7
5748 00:43:38.104653 <6>[ 0.116502] GICv3: CPU7: found redistributor 103 region 0:0x000000000c1e0000
5749 00:43:38.111358 <6>[ 0.116509] arch_timer: Enabling local workaround for ARM erratum 858921
5750 00:43:38.118286 <6>[ 0.116516] arch_timer: CPU7: Trapping CNTVCT access
5751 00:43:38.124744 <6>[ 0.116521] CPU7: Booted secondary processor 0x0000000103 [0x410fd092]
5752 00:43:38.128111 <6>[ 0.116568] smp: Brought up 1 node, 8 CPUs
5753 00:43:38.134782 <6>[ 0.355472] SMP: Total of 8 processors activated.
5754 00:43:38.138208 <6>[ 0.360407] CPU features: detected: 32-bit EL0 Support
5755 00:43:38.144757 <6>[ 0.365785] CPU features: detected: 32-bit EL1 Support
5756 00:43:38.151401 <6>[ 0.371152] CPU features: detected: CRC32 instructions
5757 00:43:38.154933 <6>[ 0.376580] CPU: All CPU(s) started at EL2
5758 00:43:38.161273 <6>[ 0.380918] alternatives: applying system-wide alternatives
5759 00:43:38.164898 <6>[ 0.389087] devtmpfs: initialized
5760 00:43:38.179915 <6>[ 0.398049] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
5761 00:43:38.189904 <6>[ 0.407996] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
5762 00:43:38.193152 <6>[ 0.415726] pinctrl core: initialized pinctrl subsystem
5763 00:43:38.201283 <6>[ 0.422839] DMI not present or invalid.
5764 00:43:38.208065 <6>[ 0.427210] NET: Registered PF_NETLINK/PF_ROUTE protocol family
5765 00:43:38.214749 <6>[ 0.434117] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
5766 00:43:38.224565 <6>[ 0.441645] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
5767 00:43:38.231363 <6>[ 0.449895] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
5768 00:43:38.238245 <6>[ 0.458073] audit: initializing netlink subsys (disabled)
5769 00:43:38.244485 <5>[ 0.463779] audit: type=2000 audit(0.332:1): state=initialized audit_enabled=0 res=1
5770 00:43:38.251260 <6>[ 0.464741] thermal_sys: Registered thermal governor 'step_wise'
5771 00:43:38.258300 <6>[ 0.471746] thermal_sys: Registered thermal governor 'power_allocator'
5772 00:43:38.261183 <6>[ 0.478044] cpuidle: using governor menu
5773 00:43:38.267844 <6>[ 0.489005] NET: Registered PF_QIPCRTR protocol family
5774 00:43:38.274500 <6>[ 0.494500] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
5775 00:43:38.281459 <6>[ 0.501596] ASID allocator initialised with 32768 entries
5776 00:43:38.284625 <6>[ 0.508365] Serial: AMBA PL011 UART driver
5777 00:43:38.296996 <4>[ 0.518765] Trying to register duplicate clock ID: 113
5778 00:43:38.356808 <6>[ 0.575180] platform 14014000.dsi: Fixed dependency cycle(s) with /soc/i2c@11008000/anx7625@58
5779 00:43:38.371300 <6>[ 0.589530] platform panel: Fixed dependency cycle(s) with /soc/i2c@11008000/anx7625@58
5780 00:43:38.374902 <6>[ 0.599285] KASLR enabled
5781 00:43:38.389475 <6>[ 0.607270] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
5782 00:43:38.395945 <6>[ 0.614272] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
5783 00:43:38.402396 <6>[ 0.620749] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
5784 00:43:38.409278 <6>[ 0.627741] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
5785 00:43:38.416157 <6>[ 0.634214] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
5786 00:43:38.422301 <6>[ 0.641204] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
5787 00:43:38.429041 <6>[ 0.647678] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
5788 00:43:38.435809 <6>[ 0.654668] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
5789 00:43:38.438978 <6>[ 0.662203] ACPI: Interpreter disabled.
5790 00:43:38.448697 <6>[ 0.670221] iommu: Default domain type: Translated
5791 00:43:38.455462 <6>[ 0.675379] iommu: DMA domain TLB invalidation policy: strict mode
5792 00:43:38.458769 <5>[ 0.682007] SCSI subsystem initialized
5793 00:43:38.465421 <6>[ 0.686457] usbcore: registered new interface driver usbfs
5794 00:43:38.472248 <6>[ 0.692186] usbcore: registered new interface driver hub
5795 00:43:38.475336 <6>[ 0.697729] usbcore: registered new device driver usb
5796 00:43:38.482439 <6>[ 0.704044] pps_core: LinuxPPS API ver. 1 registered
5797 00:43:38.492776 <6>[ 0.709230] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
5798 00:43:38.495856 <6>[ 0.718555] PTP clock support registered
5799 00:43:38.499133 <6>[ 0.722809] EDAC MC: Ver: 3.0.0
5800 00:43:38.507161 <6>[ 0.728451] FPGA manager framework
5801 00:43:38.510328 <6>[ 0.732130] Advanced Linux Sound Architecture Driver Initialized.
5802 00:43:38.514130 <6>[ 0.738867] vgaarb: loaded
5803 00:43:38.520832 <6>[ 0.742000] clocksource: Switched to clocksource arch_sys_counter
5804 00:43:38.527413 <5>[ 0.748432] VFS: Disk quotas dquot_6.6.0
5805 00:43:38.533954 <6>[ 0.752610] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
5806 00:43:38.537338 <6>[ 0.759782] pnp: PnP ACPI: disabled
5807 00:43:38.545186 <6>[ 0.766662] NET: Registered PF_INET protocol family
5808 00:43:38.551979 <6>[ 0.771894] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
5809 00:43:38.563689 <6>[ 0.781807] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
5810 00:43:38.570193 <6>[ 0.790560] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
5811 00:43:38.580223 <6>[ 0.798510] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
5812 00:43:38.586826 <6>[ 0.806741] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear)
5813 00:43:38.593787 <6>[ 0.814834] TCP: Hash tables configured (established 32768 bind 32768)
5814 00:43:38.603588 <6>[ 0.821660] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear)
5815 00:43:38.610393 <6>[ 0.828631] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear)
5816 00:43:38.617082 <6>[ 0.836108] NET: Registered PF_UNIX/PF_LOCAL protocol family
5817 00:43:38.620243 <6>[ 0.842203] RPC: Registered named UNIX socket transport module.
5818 00:43:38.626982 <6>[ 0.848346] RPC: Registered udp transport module.
5819 00:43:38.630521 <6>[ 0.853270] RPC: Registered tcp transport module.
5820 00:43:38.636968 <6>[ 0.858193] RPC: Registered tcp NFSv4.1 backchannel transport module.
5821 00:43:38.643707 <6>[ 0.864846] PCI: CLS 0 bytes, default 64
5822 00:43:38.646861 <6>[ 0.869102] Unpacking initramfs...
5823 00:43:38.660341 <6>[ 0.878586] hw perfevents: enabled with armv8_cortex_a53 PMU driver, 7 counters available
5824 00:43:38.670584 <6>[ 0.887210] hw perfevents: enabled with armv8_cortex_a73 PMU driver, 7 counters available
5825 00:43:38.673680 <6>[ 0.896054] kvm [1]: IPA Size Limit: 40 bits
5826 00:43:38.680721 <6>[ 0.902388] kvm [1]: vgic-v2@c420000
5827 00:43:38.684159 <6>[ 0.906204] kvm [1]: GIC system register CPU interface enabled
5828 00:43:38.690892 <6>[ 0.912382] kvm [1]: vgic interrupt IRQ18
5829 00:43:38.694284 <6>[ 0.916742] kvm [1]: Hyp mode initialized successfully
5830 00:43:38.701612 <5>[ 0.923058] Initialise system trusted keyrings
5831 00:43:38.708147 <6>[ 0.927880] workingset: timestamp_bits=42 max_order=20 bucket_order=0
5832 00:43:38.716325 <6>[ 0.937835] squashfs: version 4.0 (2009/01/31) Phillip Lougher
5833 00:43:38.723170 <5>[ 0.944303] NFS: Registering the id_resolver key type
5834 00:43:38.726494 <5>[ 0.949616] Key type id_resolver registered
5835 00:43:38.733336 <5>[ 0.954027] Key type id_legacy registered
5836 00:43:38.739848 <6>[ 0.958334] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
5837 00:43:38.746531 <6>[ 0.965254] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
5838 00:43:38.753099 <6>[ 0.973015] 9p: Installing v9fs 9p2000 file system support
5839 00:43:38.780930 <5>[ 1.002069] Key type asymmetric registered
5840 00:43:38.783834 <5>[ 1.006415] Asymmetric key parser 'x509' registered
5841 00:43:38.793994 <6>[ 1.011578] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
5842 00:43:38.797257 <6>[ 1.019191] io scheduler mq-deadline registered
5843 00:43:38.800462 <6>[ 1.023947] io scheduler kyber registered
5844 00:43:38.823468 <6>[ 1.044823] EINJ: ACPI disabled.
5845 00:43:38.830194 <4>[ 1.048607] of_fixed_factor_clk: probe of fixed-factor-clock-13m failed with error -17
5846 00:43:38.868626 <6>[ 1.089582] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
5847 00:43:38.876978 <6>[ 1.098108] printk: console [ttyS0] disabled
5848 00:43:38.905223 <6>[ 1.122755] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 242, base_baud = 1625000) is a ST16650V2
5849 00:43:38.911477 <6>[ 1.132230] printk: console [ttyS0] enabled
5850 00:43:38.914837 <6>[ 1.132230] printk: console [ttyS0] enabled
5851 00:43:38.921378 <6>[ 1.141151] printk: bootconsole [mtk8250] disabled
5852 00:43:38.924619 <6>[ 1.141151] printk: bootconsole [mtk8250] disabled
5853 00:43:38.935108 <3>[ 1.151689] mt8183-pinctrl 10005000.pinctrl: pin_config_group_set op failed for group 47
5854 00:43:38.941652 <3>[ 1.160072] mt6577-uart 11003000.serial: Error applying setting, reverse things back
5855 00:43:38.970631 <6>[ 1.188487] 11003000.serial: ttyS1 at MMIO 0x11003000 (irq = 243, base_baud = 1625000) is a ST16650V2
5856 00:43:38.977360 <6>[ 1.198153] serial serial0: tty port ttyS1 registered
5857 00:43:38.984034 <6>[ 1.204712] SuperH (H)SCI(F) driver initialized
5858 00:43:38.987260 <6>[ 1.210239] msm_serial: driver initialized
5859 00:43:39.002873 <6>[ 1.220564] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14008000
5860 00:43:39.013049 <6>[ 1.229162] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14009000
5861 00:43:39.019645 <6>[ 1.237739] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@1400a000
5862 00:43:39.029319 <6>[ 1.246312] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@1400b000
5863 00:43:39.036181 <6>[ 1.254968] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@1400c000
5864 00:43:39.046247 <6>[ 1.263630] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@1400e000
5865 00:43:39.056097 <6>[ 1.272371] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400f000
5866 00:43:39.062986 <6>[ 1.281110] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@14010000
5867 00:43:39.073018 <6>[ 1.289689] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@14011000
5868 00:43:39.079284 <6>[ 1.298498] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/dsi@14014000
5869 00:43:39.090036 <4>[ 1.310904] cacheinfo: Unable to detect cache hierarchy for CPU 0
5870 00:43:39.099129 <6>[ 1.320314] loop: module loaded
5871 00:43:39.111333 <6>[ 1.332296] vsim1: Bringing 1800000uV into 2700000-2700000uV
5872 00:43:39.129234 <6>[ 1.350407] megasas: 07.719.03.00-rc1
5873 00:43:39.137944 <6>[ 1.359148] spi-nor spi1.0: w25q64dw (8192 Kbytes)
5874 00:43:39.152300 <6>[ 1.373409] tpm_tis_spi spi0.0: TPM ready IRQ confirmed on attempt 2
5875 00:43:39.169164 <6>[ 1.390163] tpm_tis_spi spi0.0: 2.0 TPM (device-id 0x28, rev-id 0)
5876 00:43:39.226035 <6>[ 1.440273] tpm_tis_spi spi0.0: Cr50 firmware version: B2-C:0 RO_B:0.0.11/4d655eab RW_B:0.5.130/cr50_v2.94_mp.110-683b8
5877 00:43:39.258031 <6>[ 1.479059] Freeing initrd memory: 18292K
5878 00:43:39.273351 <4>[ 1.490931] sysfs: cannot create duplicate filename '/bus/platform/devices/fixed-factor-clock-13m'
5879 00:43:39.279915 <4>[ 1.500160] CPU: 7 PID: 1 Comm: swapper/0 Not tainted 6.1.92-cip22 #1
5880 00:43:39.286837 <4>[ 1.506859] Hardware name: Google juniper sku16 board (DT)
5881 00:43:39.289967 <4>[ 1.512598] Call trace:
5882 00:43:39.293262 <4>[ 1.515298] dump_backtrace.part.0+0xe0/0xf0
5883 00:43:39.296605 <4>[ 1.519834] show_stack+0x18/0x30
5884 00:43:39.300242 <4>[ 1.523406] dump_stack_lvl+0x68/0x84
5885 00:43:39.303248 <4>[ 1.527327] dump_stack+0x18/0x34
5886 00:43:39.310032 <4>[ 1.530897] sysfs_warn_dup+0x64/0x80
5887 00:43:39.313329 <4>[ 1.534819] sysfs_do_create_link_sd+0xf0/0x100
5888 00:43:39.316646 <4>[ 1.539606] sysfs_create_link+0x20/0x40
5889 00:43:39.323437 <4>[ 1.543786] bus_add_device+0x68/0x10c
5890 00:43:39.326635 <4>[ 1.547791] device_add+0x340/0x7ac
5891 00:43:39.329925 <4>[ 1.551535] of_device_add+0x44/0x60
5892 00:43:39.333131 <4>[ 1.555368] of_platform_device_create_pdata+0x90/0x120
5893 00:43:39.340127 <4>[ 1.560850] of_platform_bus_create+0x170/0x370
5894 00:43:39.343593 <4>[ 1.565637] of_platform_populate+0x50/0xfc
5895 00:43:39.349965 <4>[ 1.570076] parse_mtd_partitions+0x1dc/0x510
5896 00:43:39.353301 <4>[ 1.574690] mtd_device_parse_register+0xf8/0x2e0
5897 00:43:39.356750 <4>[ 1.579647] spi_nor_probe+0x21c/0x2f0
5898 00:43:39.360187 <4>[ 1.583653] spi_mem_probe+0x6c/0xb0
5899 00:43:39.363479 <4>[ 1.587486] spi_probe+0x84/0xe4
5900 00:43:39.370261 <4>[ 1.590968] really_probe+0xbc/0x2e0
5901 00:43:39.373570 <4>[ 1.594798] __driver_probe_device+0x78/0x11c
5902 00:43:39.377100 <4>[ 1.599410] driver_probe_device+0xd8/0x160
5903 00:43:39.383496 <4>[ 1.603848] __device_attach_driver+0xb8/0x134
5904 00:43:39.387394 <4>[ 1.608547] bus_for_each_drv+0x78/0xd0
5905 00:43:39.390668 <4>[ 1.612637] __device_attach+0xa8/0x1c0
5906 00:43:39.393827 <4>[ 1.616728] device_initial_probe+0x14/0x20
5907 00:43:39.400720 <4>[ 1.621166] bus_probe_device+0x9c/0xa4
5908 00:43:39.404124 <4>[ 1.625256] device_add+0x3ac/0x7ac
5909 00:43:39.407265 <4>[ 1.628998] __spi_add_device+0x78/0x120
5910 00:43:39.410583 <4>[ 1.633177] spi_add_device+0x40/0x7c
5911 00:43:39.417160 <4>[ 1.637094] spi_register_controller+0x610/0xad0
5912 00:43:39.420451 <4>[ 1.641967] devm_spi_register_controller+0x4c/0xa4
5913 00:43:39.423850 <4>[ 1.647100] mtk_spi_probe+0x3f8/0x650
5914 00:43:39.430746 <4>[ 1.651104] platform_probe+0x68/0xe0
5915 00:43:39.433972 <4>[ 1.655022] really_probe+0xbc/0x2e0
5916 00:43:39.437400 <4>[ 1.658852] __driver_probe_device+0x78/0x11c
5917 00:43:39.440694 <4>[ 1.663463] driver_probe_device+0xd8/0x160
5918 00:43:39.447298 <4>[ 1.667901] __driver_attach+0x94/0x19c
5919 00:43:39.450906 <4>[ 1.671991] bus_for_each_dev+0x70/0xd0
5920 00:43:39.454095 <4>[ 1.676081] driver_attach+0x24/0x30
5921 00:43:39.457494 <4>[ 1.679911] bus_add_driver+0x154/0x20c
5922 00:43:39.460658 <4>[ 1.684001] driver_register+0x78/0x130
5923 00:43:39.467270 <4>[ 1.688092] __platform_driver_register+0x28/0x34
5924 00:43:39.470524 <4>[ 1.693052] mtk_spi_driver_init+0x1c/0x28
5925 00:43:39.474037 <4>[ 1.697405] do_one_initcall+0x50/0x1d0
5926 00:43:39.480725 <4>[ 1.701496] kernel_init_freeable+0x21c/0x288
5927 00:43:39.483690 <4>[ 1.706109] kernel_init+0x24/0x12c
5928 00:43:39.486825 <4>[ 1.709854] ret_from_fork+0x10/0x20
5929 00:43:39.497307 <6>[ 1.718763] tun: Universal TUN/TAP device driver, 1.6
5930 00:43:39.500554 <6>[ 1.725062] thunder_xcv, ver 1.0
5931 00:43:39.504118 <6>[ 1.728582] thunder_bgx, ver 1.0
5932 00:43:39.507260 <6>[ 1.732089] nicpf, ver 1.0
5933 00:43:39.518305 <6>[ 1.736458] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
5934 00:43:39.521919 <6>[ 1.743943] hns3: Copyright (c) 2017 Huawei Corporation.
5935 00:43:39.525177 <6>[ 1.749541] hclge is initializing
5936 00:43:39.531785 <6>[ 1.753126] e1000: Intel(R) PRO/1000 Network Driver
5937 00:43:39.538486 <6>[ 1.758261] e1000: Copyright (c) 1999-2006 Intel Corporation.
5938 00:43:39.541627 <6>[ 1.764281] e1000e: Intel(R) PRO/1000 Network Driver
5939 00:43:39.548501 <6>[ 1.769502] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
5940 00:43:39.555193 <6>[ 1.775694] igb: Intel(R) Gigabit Ethernet Network Driver
5941 00:43:39.562045 <6>[ 1.781348] igb: Copyright (c) 2007-2014 Intel Corporation.
5942 00:43:39.568437 <6>[ 1.787192] igbvf: Intel(R) Gigabit Virtual Function Network Driver
5943 00:43:39.571922 <6>[ 1.793715] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
5944 00:43:39.578957 <6>[ 1.800267] sky2: driver version 1.30
5945 00:43:39.585652 <6>[ 1.805515] usbcore: registered new device driver r8152-cfgselector
5946 00:43:39.592399 <6>[ 1.812059] usbcore: registered new interface driver r8152
5947 00:43:39.595482 <6>[ 1.817896] VFIO - User Level meta-driver version: 0.3
5948 00:43:39.604419 <6>[ 1.825674] mtu3 11201000.usb: uwk - reg:0x420, version:101
5949 00:43:39.610928 <4>[ 1.831546] mtu3 11201000.usb: supply vbus not found, using dummy regulator
5950 00:43:39.617725 <6>[ 1.838829] mtu3 11201000.usb: dr_mode: 1, drd: auto
5951 00:43:39.624408 <6>[ 1.844054] mtu3 11201000.usb: u2p_dis_msk: 0, u3p_dis_msk: 0
5952 00:43:39.627703 <6>[ 1.850239] mtu3 11201000.usb: usb3-drd: 0
5953 00:43:39.637516 <6>[ 1.855803] mtu3 11201000.usb: xHCI platform device register success...
5954 00:43:39.644263 <4>[ 1.864481] xhci-mtk 11200000.usb: supply vbus not found, using dummy regulator
5955 00:43:39.650901 <6>[ 1.872427] xhci-mtk 11200000.usb: xHCI Host Controller
5956 00:43:39.657434 <6>[ 1.877938] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
5957 00:43:39.664473 <6>[ 1.885660] xhci-mtk 11200000.usb: USB3 root hub has no ports
5958 00:43:39.674327 <6>[ 1.891669] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
5959 00:43:39.681276 <6>[ 1.901092] xhci-mtk 11200000.usb: irq 253, io mem 0x11200000
5960 00:43:39.687747 <6>[ 1.907171] xhci-mtk 11200000.usb: xHCI Host Controller
5961 00:43:39.694689 <6>[ 1.912659] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
5962 00:43:39.701402 <6>[ 1.920317] xhci-mtk 11200000.usb: Host supports USB 3.0 SuperSpeed
5963 00:43:39.704615 <6>[ 1.927167] hub 1-0:1.0: USB hub found
5964 00:43:39.707797 <6>[ 1.931195] hub 1-0:1.0: 1 port detected
5965 00:43:39.718536 <6>[ 1.936561] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
5966 00:43:39.721974 <6>[ 1.945192] hub 2-0:1.0: USB hub found
5967 00:43:39.728648 <3>[ 1.949219] hub 2-0:1.0: config failed, hub doesn't have any ports! (err -19)
5968 00:43:39.735652 <6>[ 1.957112] usbcore: registered new interface driver usb-storage
5969 00:43:39.742275 <6>[ 1.963730] usbcore: registered new device driver onboard-usb-hub
5970 00:43:39.759806 <4>[ 1.978100] onboard-usb-hub 11200000.usb:hub@1: supply vdd not found, using dummy regulator
5971 00:43:39.768951 <6>[ 1.990459] mt6397-rtc mt6358-rtc: registered as rtc0
5972 00:43:39.779076 <6>[ 1.995944] mt6397-rtc mt6358-rtc: setting system clock to 2024-06-16T00:43:39 UTC (1718498619)
5973 00:43:39.782284 <6>[ 2.005848] i2c_dev: i2c /dev entries driver
5974 00:43:39.794154 <6>[ 2.012253] platform panel: Fixed dependency cycle(s) with /soc/i2c@11008000/anx7625@58
5975 00:43:39.804365 <6>[ 2.020640] platform 14014000.dsi: Fixed dependency cycle(s) with /soc/i2c@11008000/anx7625@58
5976 00:43:39.807421 <6>[ 2.029549] i2c 4-0058: Fixed dependency cycle(s) with /panel
5977 00:43:39.817615 <6>[ 2.035621] i2c 4-0058: Fixed dependency cycle(s) with /soc/dsi@14014000
5978 00:43:39.824090 <3>[ 2.043087] anx7625 4-0058: [drm:anx7625_i2c_probe] *ERROR* fail to find dsi host.
5979 00:43:39.841670 <6>[ 2.063069] cpu cpu0: EM: created perf domain
5980 00:43:39.851616 <6>[ 2.068565] cpufreq: cpufreq_online: CPU4: Running at unlisted initial frequency: 1199999 KHz, changing to: 1248000 KHz
5981 00:43:39.858635 <6>[ 2.079845] cpu cpu4: EM: created perf domain
5982 00:43:39.864928 <6>[ 2.086517] sdhci: Secure Digital Host Controller Interface driver
5983 00:43:39.871811 <6>[ 2.092973] sdhci: Copyright(c) Pierre Ossman
5984 00:43:39.878357 <6>[ 2.098372] Synopsys Designware Multimedia Card Interface Driver
5985 00:43:39.885172 <6>[ 2.098852] mtk-msdc 11240000.mmc: allocated mmc-pwrseq
5986 00:43:39.888521 <6>[ 2.105431] sdhci-pltfm: SDHCI platform and OF driver helper
5987 00:43:39.896783 <6>[ 2.117965] ledtrig-cpu: registered to indicate activity on CPUs
5988 00:43:39.904257 <6>[ 2.125672] usbcore: registered new interface driver usbhid
5989 00:43:39.907511 <6>[ 2.131513] usbhid: USB HID core driver
5990 00:43:39.918167 <6>[ 2.135809] spi_master spi2: will run message pump with realtime priority
5991 00:43:39.921764 <4>[ 2.136055] i2c_hid_of 2-002c: supply vdd not found, using dummy regulator
5992 00:43:39.932396 <4>[ 2.150163] i2c_hid_of 2-002c: supply vddl not found, using dummy regulator
5993 00:43:39.942679 <6>[ 2.154227] input: cros_ec as /devices/platform/soc/11012000.spi/spi_master/spi2/spi2.0/11012000.spi:cros-ec@0:keyboard-controller/input/input0
5994 00:43:39.960988 <6>[ 2.172592] input: cros_ec_buttons as /devices/platform/soc/11012000.spi/spi_master/spi2/spi2.0/11012000.spi:cros-ec@0:keyboard-controller/input/input1
5995 00:43:39.967831 <4>[ 2.185592] mmc1: queuing unknown CIS tuple 0x01 [d9 01 ff] (3 bytes)
5996 00:43:39.971077 <6>[ 2.186848] cros-ec-spi spi2.0: Chrome EC device registered
5997 00:43:39.986955 <4>[ 2.204879] mmc1: queuing unknown CIS tuple 0x1a [01 01 00 02 07] (5 bytes)
5998 00:43:39.990528 <6>[ 2.211376] mtk-msdc 11230000.mmc: Final PAD_DS_TUNE: 0x11c14
5999 00:43:40.000396 <4>[ 2.217584] mmc1: queuing unknown CIS tuple 0x1b [c1 41 30 30 ff ff 32 00] (8 bytes)
6000 00:43:40.003586 <6>[ 2.219364] mmc0: new HS400 MMC card at address 0001
6001 00:43:40.010679 <4>[ 2.227032] mmc1: queuing unknown CIS tuple 0x14 [] (0 bytes)
6002 00:43:40.016875 <6>[ 2.231993] mmcblk0: mmc0:0001 TB2932 29.2 GiB
6003 00:43:40.027964 <6>[ 2.249392] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
6004 00:43:40.034526 <6>[ 2.251248] mmc1: new ultra high speed SDR104 SDIO card at address 0001
6005 00:43:40.041939 <6>[ 2.262829] mmcblk0boot0: mmc0:0001 TB2932 4.00 MiB
6006 00:43:40.051578 <6>[ 2.266608] mt6358-sound mt6358-sound: mt6358_platform_driver_probe(), dev name mt6358-sound
6007 00:43:40.055051 <6>[ 2.269449] mmcblk0boot1: mmc0:0001 TB2932 4.00 MiB
6008 00:43:40.064929 <6>[ 2.280445] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6009 00:43:40.071618 <6>[ 2.283551] mmcblk0rpmb: mmc0:0001 TB2932 4.00 MiB, chardev (507:0)
6010 00:43:40.078169 <6>[ 2.294192] NET: Registered PF_PACKET protocol family
6011 00:43:40.081787 <6>[ 2.304776] 9pnet: Installing 9P2000 support
6012 00:43:40.094883 <6>[ 2.306518] input: hid-over-i2c 06CB:CDB5 Mouse as /devices/platform/soc/11009000.i2c/i2c-2/2-002c/0018:06CB:CDB5.0001/input/input2
6013 00:43:40.098517 <5>[ 2.309346] Key type dns_resolver registered
6014 00:43:40.108363 <6>[ 2.321901] hid-generic 0018:06CB:CDB5.0001: input: I2C HID v1.00 Mouse [hid-over-i2c 06CB:CDB5] on 2-002c
6015 00:43:40.114816 <6>[ 2.326447] registered taskstats version 1
6016 00:43:40.118319 <5>[ 2.340201] Loading compiled-in X.509 certificates
6017 00:43:40.131974 <6>[ 2.350109] usb 1-1: new high-speed USB device number 2 using xhci-mtk
6018 00:43:40.160857 <3>[ 2.378940] anx7625 4-0058: [drm:anx7625_link_bridge] *ERROR* fail to parse DT for panel : -517
6019 00:43:40.193318 <6>[ 2.408191] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6020 00:43:40.204470 <6>[ 2.422559] mtk-iommu 10205000.iommu: bound 14017000.larb (ops mtk_smi_larb_component_ops)
6021 00:43:40.214526 <6>[ 2.431124] mtk-iommu 10205000.iommu: bound 16010000.larb (ops mtk_smi_larb_component_ops)
6022 00:43:40.221065 <6>[ 2.440030] mtk-iommu 10205000.iommu: bound 1502f000.larb (ops mtk_smi_larb_component_ops)
6023 00:43:40.231109 <6>[ 2.448660] mtk-iommu 10205000.iommu: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
6024 00:43:40.237698 <6>[ 2.457208] mtk-iommu 10205000.iommu: bound 17010000.larb (ops mtk_smi_larb_component_ops)
6025 00:43:40.248063 <6>[ 2.465790] mtk-iommu 10205000.iommu: bound 15021000.larb (ops mtk_smi_larb_component_ops)
6026 00:43:40.257937 <6>[ 2.474329] mtk-iommu 10205000.iommu: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
6027 00:43:40.264580 <6>[ 2.483816] mediatek-disp-ovl 14008000.ovl: Adding to iommu group 0
6028 00:43:40.271126 <6>[ 2.491157] mediatek-disp-ovl 14009000.ovl: Adding to iommu group 0
6029 00:43:40.277945 <6>[ 2.498299] mediatek-disp-ovl 1400a000.ovl: Adding to iommu group 0
6030 00:43:40.281016 <6>[ 2.505042] hub 1-1:1.0: USB hub found
6031 00:43:40.288037 <6>[ 2.505614] mediatek-disp-rdma 1400b000.rdma: Adding to iommu group 0
6032 00:43:40.294873 <6>[ 2.509517] hub 1-1:1.0: 3 ports detected
6033 00:43:40.301062 <6>[ 2.516501] mediatek-disp-rdma 1400c000.rdma: Adding to iommu group 0
6034 00:43:40.308106 <6>[ 2.528420] panfrost 13040000.gpu: clock rate = 511999970
6035 00:43:40.318612 <6>[ 2.534119] panfrost 13040000.gpu: [drm:panfrost_devfreq_init] More than 1 supply is not supported yet
6036 00:43:40.325077 <6>[ 2.544381] panfrost 13040000.gpu: mali-g72 id 0x6221 major 0x0 minor 0x3 status 0x0
6037 00:43:40.335024 <6>[ 2.552389] panfrost 13040000.gpu: features: 00000000,000004f7, issues: 00000000,00000400
6038 00:43:40.348297 <6>[ 2.560823] panfrost 13040000.gpu: Features: L2:0x07120206 Shader:0x00000000 Tiler:0x00000809 Mem:0x1 MMU:0x00002830 AS:0xff JS:0x7
6039 00:43:40.354490 <6>[ 2.572900] panfrost 13040000.gpu: shader_present=0x7 l2_present=0x1
6040 00:43:40.366465 <6>[ 2.584351] [drm] Initialized panfrost 1.2.0 20180908 for 13040000.gpu on minor 0
6041 00:43:40.376565 <6>[ 2.592933] mediatek-drm mediatek-drm.1.auto: bound 14008000.ovl (ops mtk_disp_ovl_component_ops)
6042 00:43:40.386624 <6>[ 2.602085] mediatek-drm mediatek-drm.1.auto: bound 14009000.ovl (ops mtk_disp_ovl_component_ops)
6043 00:43:40.393289 <6>[ 2.611216] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ovl (ops mtk_disp_ovl_component_ops)
6044 00:43:40.403253 <6>[ 2.620344] mediatek-drm mediatek-drm.1.auto: bound 1400b000.rdma (ops mtk_disp_rdma_component_ops)
6045 00:43:40.413146 <6>[ 2.629644] mediatek-drm mediatek-drm.1.auto: bound 1400c000.rdma (ops mtk_disp_rdma_component_ops)
6046 00:43:40.423056 <6>[ 2.638944] mediatek-drm mediatek-drm.1.auto: bound 1400e000.color (ops mtk_disp_color_component_ops)
6047 00:43:40.433563 <6>[ 2.648417] mediatek-drm mediatek-drm.1.auto: bound 1400f000.ccorr (ops mtk_disp_ccorr_component_ops)
6048 00:43:40.440021 <6>[ 2.657890] mediatek-drm mediatek-drm.1.auto: bound 14010000.aal (ops mtk_disp_aal_component_ops)
6049 00:43:40.449961 <6>[ 2.667016] mediatek-drm mediatek-drm.1.auto: bound 14011000.gamma (ops mtk_disp_gamma_component_ops)
6050 00:43:40.524401 <6>[ 2.741682] mediatek-drm mediatek-drm.1.auto: bound 14014000.dsi (ops mtk_dsi_component_ops)
6051 00:43:40.533857 <6>[ 2.750566] mediatek-drm mediatek-drm.1.auto: Not creating crtc 1 because component 10 is disabled or missing
6052 00:43:40.544675 <6>[ 2.762409] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 1
6053 00:43:40.592592 <6>[ 2.810034] usb 1-1.1: new high-speed USB device number 3 using xhci-mtk
6054 00:43:40.699868 <6>[ 2.920864] hub 1-1.1:1.0: USB hub found
6055 00:43:40.703348 <6>[ 2.925387] hub 1-1.1:1.0: 4 ports detected
6056 00:43:41.231033 <6>[ 3.435232] Console: switching to colour frame buffer device 170x48
6057 00:43:41.241073 <6>[ 3.458456] mediatek-drm mediatek-drm.1.auto: [drm] fb0: mediatekdrmfb frame buffer device
6058 00:43:41.262989 <6>[ 3.477062] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6059 00:43:41.282809 <6>[ 3.497122] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6060 00:43:41.289689 <6>[ 3.509667] input: wifi-wakeup as /devices/platform/wifi-wakeup/input/input4
6061 00:43:41.300451 <6>[ 3.517760] input: volume-buttons as /devices/platform/volume-buttons/input/input5
6062 00:43:41.310190 <6>[ 3.525567] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6063 00:43:41.331087 <6>[ 3.545158] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6064 00:43:41.337847 <6>[ 3.550057] usb 1-1.2: new high-speed USB device number 4 using xhci-mtk
6065 00:43:41.344343 <6>[ 3.563297] Trying to probe devices needed for running init ...
6066 00:43:41.358326 <3>[ 3.576043] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: could not get audiosys reset:-517
6067 00:43:41.374480 <6>[ 3.588501] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6068 00:43:41.544459 <6>[ 3.762157] usb 1-1.1.1: new high-speed USB device number 5 using xhci-mtk
6069 00:43:41.736523 <6>[ 3.954325] r8152-cfgselector 1-1.2: reset high-speed USB device number 4 using xhci-mtk
6070 00:43:41.862249 <4>[ 4.079670] r8152 1-1.2:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
6071 00:43:41.872442 <4>[ 4.088892] r8152 1-1.2:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
6072 00:43:41.925203 <6>[ 4.142291] r8152-cfgselector 1-1.1.1: reset high-speed USB device number 5 using xhci-mtk
6073 00:43:41.928068 <6>[ 4.143132] r8152 1-1.2:1.0 eth0: v1.12.13
6074 00:43:41.952616 <6>[ 4.166982] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6075 00:43:42.062099 <4>[ 4.279558] r8152 1-1.1.1:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
6076 00:43:42.076442 <4>[ 4.293854] r8152 1-1.1.1:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
6077 00:43:42.124617 <6>[ 4.342152] usb 1-1.3: new high-speed USB device number 6 using xhci-mtk
6078 00:43:42.139151 <6>[ 4.360121] r8152 1-1.1.1:1.0 eth1: v1.12.13
6079 00:43:42.167131 <6>[ 4.381274] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6080 00:43:42.263952 <6>[ 4.478088] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6081 00:43:43.519853 <6>[ 5.740941] r8152 1-1.2:1.0 eth0: carrier on
6082 00:43:45.641308 <5>[ 5.766018] Sending DHCP requests .., OK
6083 00:43:45.653966 <6>[ 7.871222] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.17
6084 00:43:45.663422 <6>[ 7.884411] IP-Config: Complete:
6085 00:43:45.678333 <6>[ 7.892706] device=eth0, hwaddr=00:e0:4c:68:03:2b, ipaddr=192.168.201.17, mask=255.255.255.0, gw=192.168.201.1
6086 00:43:45.690870 <6>[ 7.908384] host=mt8183-kukui-jacuzzi-juniper-sku16-cbg-5, domain=lava-rack, nis-domain=(none)
6087 00:43:45.704450 <6>[ 7.921611] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
6088 00:43:45.711586 <6>[ 7.921620] nameserver0=192.168.201.1
6089 00:43:45.742611 <6>[ 7.963532] clk: Disabling unused clocks
6090 00:43:45.746336 <6>[ 7.970620] ALSA device list:
6091 00:43:45.755068 <6>[ 7.976032] No soundcards found.
6092 00:43:45.763290 <6>[ 7.983916] Freeing unused kernel memory: 8512K
6093 00:43:45.769690 <6>[ 7.990720] Run /init as init process
6094 00:43:45.781096 Loading, please wait...
6095 00:43:45.816614 Starting systemd-udevd version 252.22-1~deb12u1
6096 00:43:46.155586 <6>[ 8.372962] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
6097 00:43:46.159048 <3>[ 8.373503] thermal_sys: Failed to find 'trips' node
6098 00:43:46.172108 <3>[ 8.381284] mt8183-pinctrl 10005000.pinctrl: pin GPIO7 already requested by 2-002c; cannot claim for 2-0015
6099 00:43:46.175357 <3>[ 8.381488] mtk-scp 10500000.scp: invalid resource
6100 00:43:46.182093 <6>[ 8.381536] mtk-scp 10500000.scp: assigned reserved memory node memory@50000000
6101 00:43:46.189043 <6>[ 8.384005] remoteproc remoteproc0: scp is available
6102 00:43:46.195250 <4>[ 8.384080] remoteproc remoteproc0: Direct firmware load for scp.img failed with error -2
6103 00:43:46.202651 <6>[ 8.384087] remoteproc remoteproc0: powering up scp
6104 00:43:46.212169 <4>[ 8.384101] remoteproc remoteproc0: Direct firmware load for scp.img failed with error -2
6105 00:43:46.215158 <3>[ 8.384105] remoteproc remoteproc0: request_firmware failed: -2
6106 00:43:46.225819 <3>[ 8.386322] thermal_sys: Failed to find trip points for thermal-sensor1 id=0
6107 00:43:46.232237 <4>[ 8.386839] elants_i2c 0-0010: supply vcc33 not found, using dummy regulator
6108 00:43:46.238870 <4>[ 8.387945] elants_i2c 0-0010: supply vccio not found, using dummy regulator
6109 00:43:46.245865 <3>[ 8.396954] mt8183-pinctrl 10005000.pinctrl: pin-7 (2-0015) status -22
6110 00:43:46.255229 <3>[ 8.401423] generic-adc-thermal thermal-sensor1: Thermal zone sensor register failed: -22
6111 00:43:46.262251 <4>[ 8.401434] generic-adc-thermal: probe of thermal-sensor1 failed with error -22
6112 00:43:46.272253 <3>[ 8.402576] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6113 00:43:46.275687 <3>[ 8.404193] thermal_sys: Failed to find 'trips' node
6114 00:43:46.285496 <3>[ 8.404203] thermal_sys: Failed to find trip points for thermal-sensor2 id=0
6115 00:43:46.291969 <3>[ 8.404212] generic-adc-thermal thermal-sensor2: Thermal zone sensor register failed: -22
6116 00:43:46.302335 <4>[ 8.404217] generic-adc-thermal: probe of thermal-sensor2 failed with error -22
6117 00:43:46.312478 <4>[ 8.407711] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: No cache defaults, reading back from HW
6118 00:43:46.322473 <6>[ 8.408369] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 20
6119 00:43:46.332758 <3>[ 8.409163] mt8183-pinctrl 10005000.pinctrl: could not request pin 7 (GPIO7) from group GPIO7 on device pinctrl_paris
6120 00:43:46.346042 <6>[ 8.413294] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6121 00:43:46.352685 <3>[ 8.414333] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6122 00:43:46.359207 <6>[ 8.421907] mc: Linux media interface: v0.10
6123 00:43:46.366158 <3>[ 8.422732] elan_i2c 2-0015: Error applying setting, reverse things back
6124 00:43:46.372785 <3>[ 8.427874] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6125 00:43:46.379199 <6>[ 8.454495] videodev: Linux video capture interface: v2.00
6126 00:43:46.392405 <3>[ 8.459531] debugfs: Directory '11220000.audio-controller:mt8183-afe-pcm' with parent 'mt8183_mt6358_ts3a227_max98357' already present!
6127 00:43:46.402757 <5>[ 8.459973] cfg80211: Loading compiled-in X.509 certificates for regulatory database
6128 00:43:46.409035 <3>[ 8.466292] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6129 00:43:46.419160 <6>[ 8.471528] sbs-battery 12-000b: sbs-battery: battery gas gauge device registered
6130 00:43:46.425672 <5>[ 8.474462] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
6131 00:43:46.429082 <6>[ 8.478603] r8152 1-1.1.1:1.0 enx88541f0f7aca: renamed from eth1
6132 00:43:46.438794 <3>[ 8.481319] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6133 00:43:46.445742 <6>[ 8.489231] cs_system_cfg: CoreSight Configuration manager initialised
6134 00:43:46.455616 <5>[ 8.489503] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
6135 00:43:46.462140 <3>[ 8.497728] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6136 00:43:46.472154 <6>[ 8.541846] input: Elan Touchscreen as /devices/platform/soc/11007000.i2c/i2c-0/0-0010/input/input7
6137 00:43:46.482091 <3>[ 8.548895] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6138 00:43:46.488619 <4>[ 8.559898] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
6139 00:43:46.498502 <3>[ 8.570706] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6140 00:43:46.508475 <3>[ 8.570767] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6141 00:43:46.511996 <6>[ 8.579575] cfg80211: failed to load regulatory.db
6142 00:43:46.522582 <6>[ 8.581786] coresight-cpu-debug d410000.cpu-debug: Coresight debug-CPU0 initialized
6143 00:43:46.531922 <6>[ 8.581980] coresight-cpu-debug d510000.cpu-debug: Coresight debug-CPU1 initialized
6144 00:43:46.538641 <6>[ 8.583809] coresight-cpu-debug d610000.cpu-debug: Coresight debug-CPU2 initialized
6145 00:43:46.548404 <6>[ 8.583951] coresight-cpu-debug d710000.cpu-debug: Coresight debug-CPU3 initialized
6146 00:43:46.551789 <6>[ 8.584245] Bluetooth: Core ver 2.22
6147 00:43:46.558732 <6>[ 8.584301] NET: Registered PF_BLUETOOTH protocol family
6148 00:43:46.565585 <6>[ 8.584303] Bluetooth: HCI device and connection manager initialized
6149 00:43:46.572111 <6>[ 8.584318] Bluetooth: HCI socket layer initialized
6150 00:43:46.578787 <6>[ 8.584324] Bluetooth: L2CAP socket layer initialized
6151 00:43:46.582091 <6>[ 8.584336] Bluetooth: SCO socket layer initialized
6152 00:43:46.589151 <6>[ 8.607677] usb 1-1.3: Found UVC 1.00 device HD WebCam (04f2:b567)
6153 00:43:46.599818 <6>[ 8.619689] coresight-cpu-debug d810000.cpu-debug: Coresight debug-CPU4 initialized
6154 00:43:46.606586 <6>[ 8.620018] mtk-mdp3 14001000.dma-controller0: Adding to iommu group 0
6155 00:43:46.612804 <6>[ 8.620227] mtk-jpeg 17030000.venc_jpg: Adding to iommu group 0
6156 00:43:46.623158 <6>[ 8.620564] mtk-jpeg 17030000.venc_jpg: mtk-jpeg-enc device registered as /dev/video0 (81,0)
6157 00:43:46.629381 <6>[ 8.620650] mtk-mdp3 14001000.dma-controller0: Driver registered as /dev/video1
6158 00:43:46.636732 <6>[ 8.628076] Bluetooth: HCI UART driver ver 2.3
6159 00:43:46.646412 <6>[ 8.636027] coresight-cpu-debug d910000.cpu-debug: Coresight debug-CPU5 initialized
6160 00:43:46.649743 <6>[ 8.643574] Bluetooth: HCI UART protocol H4 registered
6161 00:43:46.659663 <6>[ 8.650436] coresight-cpu-debug da10000.cpu-debug: Coresight debug-CPU6 initialized
6162 00:43:46.662984 <6>[ 8.656619] Bluetooth: HCI UART protocol LL registered
6163 00:43:46.676429 <6>[ 8.660949] input: HD WebCam: HD WebCam as /devices/platform/soc/11201000.usb/11200000.usb/usb1/1-1/1-1.3/1-1.3:1.0/input/input8
6164 00:43:46.683398 <6>[ 8.661101] usbcore: registered new interface driver uvcvideo
6165 00:43:46.693194 Begin: Loading e<6>[ 8.665601] ath10k_sdio mmc1:0001:1: qca6174 hw3.2 sdio target 0x05030000 chip_id 0x00000000 sub 0000:0000
6166 00:43:46.706722 ssential drivers<3>[ 8.665657] mt8183_mt6358_ts3a227 mt8183-sound: ASoC: driver name too long 'mt8183_mt6358_ts3a227_max98357' -> 'mt8183_mt6358_t'
6167 00:43:46.710178 ... done.
6168 00:43:46.716786 Begi<3>[ 8.666801] debugfs: File 'Playback' in directory 'dapm' already present!
6169 00:43:46.723655 n: Running /scri<3>[ 8.666808] debugfs: File 'Capture' in directory 'dapm' already present!
6170 00:43:46.737244 pts/init-premoun<6>[ 8.668799] input: mt8183_mt6358_ts3a227_max98357 Headset Jack as /devices/platform/mt8183-sound/sound/card0/input6
6171 00:43:46.737780 t ... done.
6172 00:43:46.746956 Beg<6>[ 8.671988] coresight-cpu-debug db10000.cpu-debug: Coresight debug-CPU7 initialized
6173 00:43:46.753930 in: Mounting roo<6>[ 8.672027] Bluetooth: HCI UART protocol Three-wire (H5) registered
6174 00:43:46.763748 t file system ..<6>[ 8.680604] ath10k_sdio mmc1:0001:1: kconfig debug 0 debugfs 0 tracing 0 dfs 0 testmode 0
6175 00:43:46.770453 . Begin: Running<6>[ 8.689221] Bluetooth: HCI UART protocol Broadcom registered
6176 00:43:46.783559 /scripts/nfs-to<6>[ 8.698582] ath10k_sdio mmc1:0001:1: firmware ver WLAN.RMH.4.4.1-00174 api 6 features wowlan,ignore-otp,mfp crc32 7319fa77
6177 00:43:46.784071 p ... done.
6178 00:43:46.790348 Beg<6>[ 8.706714] Bluetooth: HCI UART protocol QCA registered
6179 00:43:46.796898 in: Running /scr<6>[ 8.707665] Bluetooth: hci0: setting up ROME/QCA6390
6180 00:43:46.806638 ipts/nfs-premoun<6>[ 8.864990] ath10k_sdio mmc1:0001:1: board_file api 2 bmi_id 0:4 crc32 d2863f91
6181 00:43:46.813915 t ... Waiting up<6>[ 8.870489] Bluetooth: HCI UART protocol Marvell registered
6182 00:43:46.823140 to 60 secs for <4>[ 8.898591] sbs-battery 12-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
6183 00:43:46.826794 <4>[ 8.898591] Fallback method does not support PEC.
6184 00:43:46.836067 any ethernet to <3>[ 8.921103] Bluetooth: hci0: Frame reassembly failed (-84)
6185 00:43:46.845981 become available<3>[ 8.935298] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6186 00:43:46.846554
6187 00:43:46.849367 Device /sys/class/net/enx88541f0f7aca found
6188 00:43:46.849794 done.
6189 00:43:46.855978 Begin: Waiting up to 180 secs for any network device to become available ... done.
6190 00:43:46.886913 <3>[ 9.104612] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6191 00:43:46.921305 IP-Config: eth0 hardware address 00:e0:4c:68:03:2b mtu 1500 DHCP
6192 00:43:46.952812 IP-Config: enx88541f0f7aca hardware address 88:54:1f:0f:7a:ca mtu 1500 DHCP
6193 00:43:46.966400 IP-Config: eth0 complete (dhcp from 192.168.201.1):
6194 00:43:46.972909 address: 1<6>[ 9.191448] Bluetooth: hci0: QCA Product ID :0x00000008
6195 00:43:46.979944 92.168.201.17 broadcast: 192.1<6>[ 9.200557] Bluetooth: hci0: QCA SOC Version :0x00000044
6196 00:43:46.990055 68.201.255 netmask: 255.255.255<6>[ 9.208930] Bluetooth: hci0: QCA ROM Version :0x00000302
6197 00:43:46.990624 .0
6198 00:43:47.000070 gateway: 192.168.201.1 dns0 : 192<6>[ 9.218362] Bluetooth: hci0: QCA Patch Version:0x00000111
6199 00:43:47.003097 .168.201.1 dns1 : 0.0.0.0
6200 00:43:47.009848 host <6>[ 9.228229] Bluetooth: hci0: QCA controller version 0x00440302
6201 00:43:47.019617 : mt8183-kukui-jacuzzi-juniper-sku16-cbg-5 <6>[ 9.238207] Bluetooth: hci0: QCA Downloading qca/rampatch_00440302.bin
6202 00:43:47.022933
6203 00:43:47.032622 domain : l<4>[ 9.248762] bluetooth hci0: Direct firmware load for qca/rampatch_00440302.bin failed with error -2
6204 00:43:47.042704 ava-rack <3>[ 9.260572] Bluetooth: hci0: QCA Failed to request file: qca/rampatch_00440302.bin (-2)
6205 00:43:47.045997
6206 00:43:47.052600 <3>[ 9.271410] Bluetooth: hci0: QCA Failed to download patch (-2)
6207 00:43:47.052996
6208 00:43:47.055771 rootserver: 192.168.201.1 rootpath:
6209 00:43:47.059103 filename :
6210 00:43:47.059493 done.
6211 00:43:47.062576 Begin: Running /scripts/nfs-bottom ... done.
6212 00:43:47.075605 Begin: Running /scripts/init-botto<6>[ 9.289638] ath10k_sdio mmc1:0001:1: htt-ver 3.87 wmi-op 4 htt-op 3 cal otp max-sta 32 raw 0 hwcrypto 1
6213 00:43:47.080221 m ... done.
6214 00:43:47.157054 <4>[ 9.377617] mmc1: queuing unknown CIS tuple 0x01 [d9 01 ff] (3 bytes)
6215 00:43:47.178299 <4>[ 9.395808] mmc1: queuing unknown CIS tuple 0x1a [01 01 00 02 07] (5 bytes)
6216 00:43:47.191096 <4>[ 9.408748] mmc1: queuing unknown CIS tuple 0x1b [c1 41 30 30 ff ff 32 00] (8 bytes)
6217 00:43:47.200978 <4>[ 9.421690] mmc1: queuing unknown CIS tuple 0x14 [] (0 bytes)
6218 00:43:48.439392 <6>[ 10.659850] NET: Registered PF_INET6 protocol family
6219 00:43:48.451588 <6>[ 10.672381] Segment Routing with IPv6
6220 00:43:48.459918 <6>[ 10.680903] In-situ OAM (IOAM) with IPv6
6221 00:43:48.643442 <30>[ 10.837536] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
6222 00:43:48.664614 <30>[ 10.885296] systemd[1]: Detected architecture arm64.
6223 00:43:48.678413
6224 00:43:48.681351 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
6225 00:43:48.681887
6226 00:43:48.706418 <30>[ 10.927386] systemd[1]: Hostname set to <debian-bookworm-arm64>.
6227 00:43:49.827647 <30>[ 12.044967] systemd[1]: Queued start job for default target graphical.target.
6228 00:43:49.866340 <30>[ 12.083576] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
6229 00:43:49.878928 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
6230 00:43:49.898830 <30>[ 12.116402] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
6231 00:43:49.912646 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
6232 00:43:49.930948 <30>[ 12.148525] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
6233 00:43:49.945385 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
6234 00:43:49.961973 <30>[ 12.179584] systemd[1]: Created slice user.slice - User and Session Slice.
6235 00:43:49.974182 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
6236 00:43:49.996672 <30>[ 12.210604] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
6237 00:43:50.009356 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
6238 00:43:50.032379 <30>[ 12.246434] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
6239 00:43:50.044466 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
6240 00:43:50.070873 <30>[ 12.278384] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
6241 00:43:50.090321 <30>[ 12.307652] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
6242 00:43:50.097822 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
6243 00:43:50.116688 <30>[ 12.334205] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
6244 00:43:50.129416 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
6245 00:43:50.148814 <30>[ 12.366236] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
6246 00:43:50.162581 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
6247 00:43:50.177345 <30>[ 12.398293] systemd[1]: Reached target paths.target - Path Units.
6248 00:43:50.191882 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
6249 00:43:50.208872 <30>[ 12.426199] systemd[1]: Reached target remote-fs.target - Remote File Systems.
6250 00:43:50.221234 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
6251 00:43:50.233385 <30>[ 12.454166] systemd[1]: Reached target slices.target - Slice Units.
6252 00:43:50.247943 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
6253 00:43:50.261910 <30>[ 12.482217] systemd[1]: Reached target swap.target - Swaps.
6254 00:43:50.271868 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
6255 00:43:50.293260 <30>[ 12.510268] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
6256 00:43:50.305969 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
6257 00:43:50.325007 <30>[ 12.542573] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
6258 00:43:50.338943 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
6259 00:43:50.360096 <30>[ 12.577572] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
6260 00:43:50.373498 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
6261 00:43:50.390453 <30>[ 12.607791] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
6262 00:43:50.404146 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
6263 00:43:50.421291 <30>[ 12.638846] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
6264 00:43:50.433840 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
6265 00:43:50.454538 <30>[ 12.671828] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
6266 00:43:50.467878 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
6267 00:43:50.487980 <30>[ 12.705465] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
6268 00:43:50.501332 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
6269 00:43:50.517488 <30>[ 12.734726] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
6270 00:43:50.530312 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
6271 00:43:50.572809 <30>[ 12.790341] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
6272 00:43:50.585388 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
6273 00:43:50.605712 <30>[ 12.823214] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
6274 00:43:50.619068 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
6275 00:43:50.640616 <30>[ 12.858156] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
6276 00:43:50.653382 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
6277 00:43:50.675759 <30>[ 12.886623] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
6278 00:43:50.699170 <30>[ 12.916515] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
6279 00:43:50.712118 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
6280 00:43:50.735382 <30>[ 12.952463] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
6281 00:43:50.747134 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
6282 00:43:50.769438 <30>[ 12.986971] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
6283 00:43:50.780727 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
6284 00:43:50.800486 <30>[ 13.018056] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
6285 00:43:50.811452 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
6286 00:43:50.821404 <6>[ 13.037871] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
6287 00:43:50.837509 <30>[ 13.054633] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
6288 00:43:50.851543 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
6289 00:43:50.875447 <30>[ 13.092754] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
6290 00:43:50.886291 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
6291 00:43:50.914991 <6>[ 13.135525] fuse: init (API version 7.37)
6292 00:43:50.950208 <30>[ 13.167783] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
6293 00:43:50.963906 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
6294 00:43:50.991886 <30>[ 13.209522] systemd[1]: Starting systemd-journald.service - Journal Service...
6295 00:43:51.002234 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
6296 00:43:51.057607 <30>[ 13.275107] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
6297 00:43:51.068610 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
6298 00:43:51.096306 <30>[ 13.310592] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
6299 00:43:51.107967 Starting [0;1;39msystemd-network-g… units from Kernel command line...
6300 00:43:51.133493 <30>[ 13.350823] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
6301 00:43:51.145437 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
6302 00:43:51.186381 <30>[ 13.402729] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
6303 00:43:51.192936 <3>[ 13.411224] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6304 00:43:51.208880 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug Al<3>[ 13.427247] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6305 00:43:51.211866 l udev Devices...
6306 00:43:51.228193 <3>[ 13.444999] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6307 00:43:51.244634 <3>[ 13.461974] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6308 00:43:51.251251 <30>[ 13.463513] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
6309 00:43:51.262582 <3>[ 13.479495] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6310 00:43:51.282496 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File S<3>[ 13.499355] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6311 00:43:51.282905 ystem.
6312 00:43:51.300446 <3>[ 13.517664] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6313 00:43:51.311578 <30>[ 13.526890] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
6314 00:43:51.318168 <3>[ 13.535754] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6315 00:43:51.332035 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
6316 00:43:51.349976 <30>[ 13.567080] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
6317 00:43:51.360902 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
6318 00:43:51.381417 <30>[ 13.598817] systemd[1]: Started systemd-journald.service - Journal Service.
6319 00:43:51.391222 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
6320 00:43:51.411175 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
6321 00:43:51.432299 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
6322 00:43:51.451705 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
6323 00:43:51.472120 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
6324 00:43:51.491630 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
6325 00:43:51.511707 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
6326 00:43:51.535560 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
6327 00:43:51.558597 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
6328 00:43:51.578277 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
6329 00:43:51.598540 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
6330 00:43:51.620428 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
6331 00:43:51.657376 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
6332 00:43:51.677618 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
6333 00:43:51.701321 <4>[ 13.911687] synth uevent: /devices/platform/soc/11012000.spi/spi_master/spi2/spi2.0/11012000.spi:cros-ec@0:i2c-tunnel/i2c-12/12-000b/power_supply/sbs-12-000b: failed to send uevent
6334 00:43:51.712315 <3>[ 13.929382] power_supply sbs-12-000b: uevent: failed to send synthetic uevent: -5
6335 00:43:51.726182 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage..<4>[ 13.944582] power_supply_show_property: 3 callbacks suppressed
6336 00:43:51.726673 .
6337 00:43:51.738502 <3>[ 13.944606] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6338 00:43:51.756553 Starting [0;1;39msystemd-random-se…ice[0m - Load/Sa<3>[ 13.973844] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6339 00:43:51.759849 ve Random Seed...
6340 00:43:51.776204 <3>[ 13.993528] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6341 00:43:51.795856 <3>[ 14.013056] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6342 00:43:51.816179 <3>[ 14.033315] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6343 00:43:51.836776 <3>[ 14.053384] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6344 00:43:51.857267 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables..<3>[ 14.072927] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6345 00:43:51.857866 .
6346 00:43:51.875297 <3>[ 14.092351] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6347 00:43:51.884748 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
6348 00:43:51.895033 <3>[ 14.112218] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6349 00:43:51.913484 <3>[ 14.130254] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6350 00:43:51.925796 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
6351 00:43:51.932311 <46>[ 14.151289] systemd-journald[318]: Received client request to flush runtime journal.
6352 00:43:51.945006 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
6353 00:43:51.962180 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
6354 00:43:51.982309 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
6355 00:43:52.003078 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
6356 00:43:52.023832 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
6357 00:43:52.061751 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
6358 00:43:53.389265 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
6359 00:43:53.437958 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
6360 00:43:53.453809 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
6361 00:43:53.473688 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
6362 00:43:53.517713 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
6363 00:43:53.543800 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
6364 00:43:53.814985 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
6365 00:43:53.861255 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
6366 00:43:53.944982 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
6367 00:43:54.186035 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
6368 00:43:54.204431 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
6369 00:43:54.244871 Starting [0;1;39msystemd-backlight…ess of backlight:backlight_lcd0...
6370 00:43:54.334860 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
6371 00:43:54.353756 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
6372 00:43:54.409707 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
6373 00:43:54.434102 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
6374 00:43:54.490693 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of backlight:backlight_lcd0.
6375 00:43:54.542761 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
6376 00:43:54.670508 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
6377 00:43:54.694691 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
6378 00:43:54.722577 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
6379 00:43:54.753236 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
6380 00:43:54.771948 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
6381 00:43:54.794649 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
6382 00:43:54.818413 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
6383 00:43:54.842905 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
6384 00:43:54.866011 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
6385 00:43:54.887014 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
6386 00:43:54.906442 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
6387 00:43:54.927566 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
6388 00:43:54.951274 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
6389 00:43:54.975860 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
6390 00:43:54.995609 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
6391 00:43:55.013788 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
6392 00:43:55.031612 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
6393 00:43:55.052202 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
6394 00:43:55.069064 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
6395 00:43:55.085055 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
6396 00:43:55.103458 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
6397 00:43:55.120918 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
6398 00:43:55.137059 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
6399 00:43:55.190590 Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
6400 00:43:55.209584 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
6401 00:43:55.244039 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
6402 00:43:55.324858 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
6403 00:43:55.350494 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
6404 00:43:55.370483 [[0;32m OK [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
6405 00:43:55.390766 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
6406 00:43:55.576597 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
6407 00:43:55.627455 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
6408 00:43:55.678716 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
6409 00:43:55.696408 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
6410 00:43:55.712327 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
6411 00:43:55.747027 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
6412 00:43:55.769210 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
6413 00:43:55.791734 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
6414 00:43:55.808801 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
6415 00:43:55.857515 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
6416 00:43:55.965727 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
6417 00:43:56.043724
6418 00:43:56.046884 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
6419 00:43:56.047321
6420 00:43:56.050137 debian-bookworm-arm64 login: root (automatic login)
6421 00:43:56.050633
6422 00:43:56.366573 Linux debian-bookworm-arm64 6.1.92-cip22 #1 SMP PREEMPT Sun Jun 16 00:28:47 UTC 2024 aarch64
6423 00:43:56.367015
6424 00:43:56.373328 The programs included with the Debian GNU/Linux system are free software;
6425 00:43:56.379839 the exact distribution terms for each program are described in the
6426 00:43:56.383106 individual files in /usr/share/doc/*/copyright.
6427 00:43:56.383500
6428 00:43:56.390115 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
6429 00:43:56.393366 permitted by applicable law.
6430 00:43:57.594910 Matched prompt #10: / #
6432 00:43:57.596054 Setting prompt string to ['/ #']
6433 00:43:57.596483 end: 2.2.5.1 login-action (duration 00:00:20) [common]
6435 00:43:57.597373 end: 2.2.5 auto-login-action (duration 00:00:20) [common]
6436 00:43:57.597783 start: 2.2.6 expect-shell-connection (timeout 00:03:48) [common]
6437 00:43:57.598125 Setting prompt string to ['/ #']
6438 00:43:57.598457 Forcing a shell prompt, looking for ['/ #']
6440 00:43:57.649131 / #
6441 00:43:57.649421 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
6442 00:43:57.649567 Waiting using forced prompt support (timeout 00:02:30)
6443 00:43:57.655060
6444 00:43:57.655416 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
6445 00:43:57.655565 start: 2.2.7 export-device-env (timeout 00:03:47) [common]
6447 00:43:57.756074 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14368368/extract-nfsrootfs-vnd37feq'
6448 00:43:57.762032 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14368368/extract-nfsrootfs-vnd37feq'
6450 00:43:57.863455 / # export NFS_SERVER_IP='192.168.201.1'
6451 00:43:57.869547 export NFS_SERVER_IP='192.168.201.1'
6452 00:43:57.870395 end: 2.2.7 export-device-env (duration 00:00:00) [common]
6453 00:43:57.870895 end: 2.2 depthcharge-retry (duration 00:01:13) [common]
6454 00:43:57.871386 end: 2 depthcharge-action (duration 00:01:13) [common]
6455 00:43:57.871843 start: 3 lava-test-retry (timeout 00:08:10) [common]
6456 00:43:57.872311 start: 3.1 lava-test-shell (timeout 00:08:10) [common]
6457 00:43:57.872704 Using namespace: common
6459 00:43:57.973827 / # #
6460 00:43:57.974481 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
6461 00:43:57.980159 #
6462 00:43:57.980955 Using /lava-14368368
6464 00:43:58.082157 / # export SHELL=/bin/bash
6465 00:43:58.088293 export SHELL=/bin/bash
6467 00:43:58.189914 / # . /lava-14368368/environment
6468 00:43:58.195771 . /lava-14368368/environment
6470 00:43:58.302163 / # /lava-14368368/bin/lava-test-runner /lava-14368368/0
6471 00:43:58.302895 Test shell timeout: 10s (minimum of the action and connection timeout)
6472 00:43:58.308734 /lava-14368368/bin/lava-test-runner /lava-14368368/0
6473 00:43:58.558112 + export TESTRUN_ID=0_timesync-off
6474 00:43:58.561344 + TESTRUN_ID=0_timesync-off
6475 00:43:58.564965 + cd /lava-14368368/0/tests/0_timesync-off
6476 00:43:58.567824 ++ cat uuid
6477 00:43:58.573768 + UUID=14368368_1.6.2.3.1
6478 00:43:58.574167 + set +x
6479 00:43:58.580259 <LAVA_SIGNAL_STARTRUN 0_timesync-off 14368368_1.6.2.3.1>
6480 00:43:58.580963 Received signal: <STARTRUN> 0_timesync-off 14368368_1.6.2.3.1
6481 00:43:58.581306 Starting test lava.0_timesync-off (14368368_1.6.2.3.1)
6482 00:43:58.581714 Skipping test definition patterns.
6483 00:43:58.583620 + systemctl stop systemd-timesyncd
6484 00:43:58.654342 + set +x
6485 00:43:58.657738 <LAVA_SIGNAL_ENDRUN 0_timesync-off 14368368_1.6.2.3.1>
6486 00:43:58.658461 Received signal: <ENDRUN> 0_timesync-off 14368368_1.6.2.3.1
6487 00:43:58.658931 Ending use of test pattern.
6488 00:43:58.659321 Ending test lava.0_timesync-off (14368368_1.6.2.3.1), duration 0.08
6490 00:43:58.735877 + export TESTRUN_ID=1_kselftest-alsa
6491 00:43:58.739007 + TESTRUN_ID=1_kselftest-alsa
6492 00:43:58.746004 + cd /lava-14368368/0/tests/1_kselftest-alsa
6493 00:43:58.746485 ++ cat uuid
6494 00:43:58.753005 + UUID=14368368_1.6.2.3.5
6495 00:43:58.753442 + set +x
6496 00:43:58.759577 <LAVA_SIGNAL_STARTRUN 1_kselftest-alsa 14368368_1.6.2.3.5>
6497 00:43:58.760211 Received signal: <STARTRUN> 1_kselftest-alsa 14368368_1.6.2.3.5
6498 00:43:58.760537 Starting test lava.1_kselftest-alsa (14368368_1.6.2.3.5)
6499 00:43:58.760888 Skipping test definition patterns.
6500 00:43:58.763048 + cd ./automated/linux/kselftest/
6501 00:43:58.789228 + ./kselftest.sh -c alsa -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-24-g0315de64ea248/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8183-kukui-jacuzzi-juniper-sku16 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
6502 00:43:58.833710 INFO: install_deps skipped
6503 00:43:59.343137 --2024-06-16 00:43:59-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-24-g0315de64ea248/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
6504 00:43:59.367717 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
6505 00:43:59.493505 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
6506 00:43:59.619588 HTTP request sent, awaiting response... 200 OK
6507 00:43:59.622440 Length: 1647580 (1.6M) [application/octet-stream]
6508 00:43:59.626104 Saving to: 'kselftest_armhf.tar.gz'
6509 00:43:59.626668
6510 00:43:59.627011
6511 00:43:59.869715 kselftest_armhf.tar 0%[ ] 0 --.-KB/s
6512 00:44:00.119917 kselftest_armhf.tar 2%[ ] 43.57K 171KB/s
6513 00:44:00.388731 kselftest_armhf.tar 13%[=> ] 213.25K 418KB/s
6514 00:44:00.622698 kselftest_armhf.tar 41%[=======> ] 662.44K 845KB/s
6515 00:44:00.768935 kselftest_armhf.tar 73%[=============> ] 1.16M 1.13MB/s
6516 00:44:00.775100 kselftest_armhf.tar 100%[===================>] 1.57M 1.34MB/s in 1.2s
6517 00:44:00.775536
6518 00:44:00.920111 2024-06-16 00:44:00 (1.34 MB/s) - 'kselftest_armhf.tar.gz' saved [1647580/1647580]
6519 00:44:00.920234
6520 00:44:05.119988 skiplist:
6521 00:44:05.123039 ========================================
6522 00:44:05.126385 ========================================
6523 00:44:05.176243 alsa:mixer-test
6524 00:44:05.197577 ============== Tests to run ===============
6525 00:44:05.197966 alsa:mixer-test
6526 00:44:05.200921 ===========End Tests to run ===============
6527 00:44:05.205666 shardfile-alsa pass
6528 00:44:05.318709 <12>[ 27.539357] kselftest: Running tests in alsa
6529 00:44:05.329621 TAP version 13
6530 00:44:05.346207 1..1
6531 00:44:05.365221 # selftests: alsa: mixer-test
6532 00:44:05.480126 <6>[ 27.694041] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_adda_dmic_set(), kcontrol name MTKAIF_DMIC, mtkaif_dmic 0
6533 00:44:05.493161 <6>[ 27.706406] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_adda_dmic_set(), kcontrol name MTKAIF_DMIC, mtkaif_dmic 0
6534 00:44:05.506595 <6>[ 27.718736] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_adda_dmic_set(), kcontrol name MTKAIF_DMIC, mtkaif_dmic 1
6535 00:44:05.516560 <6>[ 27.731143] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_adda_dmic_set(), kcontrol name MTKAIF_DMIC, mtkaif_dmic 0
6536 00:44:05.529806 <6>[ 27.743364] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_adda_dmic_set(), kcontrol name MTKAIF_DMIC, mtkaif_dmic 0
6537 00:44:05.542990 <6>[ 27.755632] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S5_HD_Mux, hd_en 0
6538 00:44:05.552923 <6>[ 27.767019] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S5_HD_Mux, hd_en 0
6539 00:44:05.562829 <6>[ 27.778371] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S5_HD_Mux, hd_en 1
6540 00:44:05.576212 <6>[ 27.789718] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S5_HD_Mux, hd_en 0
6541 00:44:05.586190 <6>[ 27.801058] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S5_HD_Mux, hd_en 0
6542 00:44:05.599524 <6>[ 27.812396] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S3_HD_Mux, hd_en 0
6543 00:44:05.609719 <6>[ 27.823728] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S3_HD_Mux, hd_en 0
6544 00:44:05.619535 <6>[ 27.835057] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S3_HD_Mux, hd_en 1
6545 00:44:05.632932 <6>[ 27.846390] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S3_HD_Mux, hd_en 0
6546 00:44:05.642905 <6>[ 27.857726] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S3_HD_Mux, hd_en 0
6547 00:44:05.656056 <6>[ 27.869062] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S2_HD_Mux, hd_en 0
6548 00:44:05.666281 <6>[ 27.880399] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S2_HD_Mux, hd_en 0
6549 00:44:05.675753 <6>[ 27.891747] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S2_HD_Mux, hd_en 1
6550 00:44:05.689060 <6>[ 27.903090] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S2_HD_Mux, hd_en 0
6551 00:44:05.699183 <6>[ 27.914441] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S2_HD_Mux, hd_en 0
6552 00:44:05.712276 <6>[ 27.925812] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S1_HD_Mux, hd_en 0
6553 00:44:05.722393 <6>[ 27.937164] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S1_HD_Mux, hd_en 0
6554 00:44:05.735728 <6>[ 27.948521] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S1_HD_Mux, hd_en 1
6555 00:44:05.745866 <6>[ 27.959898] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S1_HD_Mux, hd_en 0
6556 00:44:05.758628 <6>[ 27.971299] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S1_HD_Mux, hd_en 0
6557 00:44:05.768614 <6>[ 27.982682] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S0_HD_Mux, hd_en 0
6558 00:44:05.778862 <6>[ 27.994043] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S0_HD_Mux, hd_en 0
6559 00:44:05.792014 <6>[ 28.005419] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S0_HD_Mux, hd_en 1
6560 00:44:05.802153 <6>[ 28.016800] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S0_HD_Mux, hd_en 0
6561 00:44:05.815412 <6>[ 28.028167] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S0_HD_Mux, hd_en 0
6562 00:44:05.815932 # TAP version 13
6563 00:44:05.816267 # 1..658
6564 00:44:05.818834 # ok 1 get_value.0.93
6565 00:44:05.822096 # ok 2 name.0.93
6566 00:44:05.822632 # ok 3 write_default.0.93
6567 00:44:05.825220 # ok 4 write_valid.0.93
6568 00:44:05.829035 # ok 5 write_invalid.0.93
6569 00:44:05.829543 # ok 6 event_missing.0.93
6570 00:44:05.832010 # ok 7 event_spurious.0.93
6571 00:44:05.835552 # ok 8 get_value.0.92
6572 00:44:05.836062 # ok 9 name.0.92
6573 00:44:05.838739 # ok 10 write_default.0.92
6574 00:44:05.842144 # ok 11 write_valid.0.92
6575 00:44:05.842687 # ok 12 write_invalid.0.92
6576 00:44:05.845478 # ok 13 event_missing.0.92
6577 00:44:05.848489 # ok 14 event_spurious.0.92
6578 00:44:05.848956 # ok 15 get_value.0.91
6579 00:44:05.851818 # ok 16 name.0.91
6580 00:44:05.855405 # ok 17 write_default.0.91
6581 00:44:05.855833 # ok 18 write_valid.0.91
6582 00:44:05.858495 # ok 19 write_invalid.0.91
6583 00:44:05.861969 # ok 20 event_missing.0.91
6584 00:44:05.865347 # ok 21 event_spurious.0.91
6585 00:44:05.865934 # ok 22 get_value.0.90
6586 00:44:05.868752 # ok 23 name.0.90
6587 00:44:05.872122 # ok 24 write_default.0.90
6588 00:44:05.872627 # ok 25 write_valid.0.90
6589 00:44:05.875080 # ok 26 write_invalid.0.90
6590 00:44:05.878558 # ok 27 event_missing.0.90
6591 00:44:05.881832 # ok 28 event_spurious.0.90
6592 00:44:05.882381 # ok 29 get_value.0.89
6593 00:44:05.884919 # ok 30 name.0.89
6594 00:44:05.888417 # ok 31 write_default.0.89
6595 00:44:05.888842 # ok 32 write_valid.0.89
6596 00:44:05.891840 # ok 33 write_invalid.0.89
6597 00:44:05.894941 # ok 34 event_missing.0.89
6598 00:44:05.898840 # ok 35 event_spurious.0.89
6599 00:44:05.899349 # ok 36 get_value.0.88
6600 00:44:05.901639 # ok 37 name.0.88
6601 00:44:05.905002 # ok 38 write_default.0.88
6602 00:44:05.908407 # # Spurious event generated for AIF Out Mux
6603 00:44:05.911589 # # AIF Out Mux.0 expected 1 but read 0, is_volatile 0
6604 00:44:05.918449 # # Spurious event generated for AIF Out Mux
6605 00:44:05.918961 # not ok 39 write_valid.0.88
6606 00:44:05.921937 # ok 40 write_invalid.0.88
6607 00:44:05.924977 # ok 41 event_missing.0.88
6608 00:44:05.928638 # not ok 42 event_spurious.0.88
6609 00:44:05.929147 # ok 43 get_value.0.87
6610 00:44:05.931846 # ok 44 name.0.87
6611 00:44:05.935196 # ok 45 write_default.0.87
6612 00:44:05.935702 # ok 46 write_valid.0.87
6613 00:44:05.938439 # ok 47 write_invalid.0.87
6614 00:44:05.941874 # ok 48 event_missing.0.87
6615 00:44:05.945354 # ok 49 event_spurious.0.87
6616 00:44:05.945865 # ok 50 get_value.0.86
6617 00:44:05.948165 # ok 51 name.0.86
6618 00:44:05.951469 # ok 52 write_default.0.86
6619 00:44:05.954832 # # HPR Mux.0 expected 5 but read 0, is_volatile 0
6620 00:44:05.958173 # # HPR Mux.0 expected 6 but read 0, is_volatile 0
6621 00:44:05.964799 # # HPR Mux.0 expected 7 but read 0, is_volatile 0
6622 00:44:05.968301 # not ok 53 write_valid.0.86
6623 00:44:05.968958 # ok 54 write_invalid.0.86
6624 00:44:05.971276 # ok 55 event_missing.0.86
6625 00:44:05.974484 # ok 56 event_spurious.0.86
6626 00:44:05.977857 # ok 57 get_value.0.85
6627 00:44:05.978439 # ok 58 name.0.85
6628 00:44:05.981519 # ok 59 write_default.0.85
6629 00:44:05.984821 # # HPL Mux.0 expected 5 but read 0, is_volatile 0
6630 00:44:05.991732 # # HPL Mux.0 expected 6 but read 0, is_volatile 0
6631 00:44:05.994811 # # HPL Mux.0 expected 7 but read 0, is_volatile 0
6632 00:44:05.998193 # not ok 60 write_valid.0.85
6633 00:44:06.001242 # ok 61 write_invalid.0.85
6634 00:44:06.001976 # ok 62 event_missing.0.85
6635 00:44:06.004573 # ok 63 event_spurious.0.85
6636 00:44:06.008012 # ok 64 get_value.0.84
6637 00:44:06.008578 # ok 65 name.0.84
6638 00:44:06.011335 # ok 66 write_default.0.84
6639 00:44:06.014493 # ok 67 write_valid.0.84
6640 00:44:06.014798 # ok 68 write_invalid.0.84
6641 00:44:06.017846 # ok 69 event_missing.0.84
6642 00:44:06.021002 # ok 70 event_spurious.0.84
6643 00:44:06.024522 # ok 71 get_value.0.83
6644 00:44:06.024701 # ok 72 name.0.83
6645 00:44:06.027535 # ok 73 write_default.0.83
6646 00:44:06.031326 # ok 74 write_valid.0.83
6647 00:44:06.031474 # ok 75 write_invalid.0.83
6648 00:44:06.034280 # ok 76 event_missing.0.83
6649 00:44:06.037576 # ok 77 event_spurious.0.83
6650 00:44:06.040809 # ok 78 get_value.0.82
6651 00:44:06.040919 # ok 79 name.0.82
6652 00:44:06.044263 # # Headset Jack is not writeable
6653 00:44:06.047434 # ok 80 # SKIP write_default.0.82
6654 00:44:06.050818 # # Headset Jack is not writeable
6655 00:44:06.054112 # ok 81 # SKIP write_valid.0.82
6656 00:44:06.057434 # # Headset Jack is not writeable
6657 00:44:06.060934 # ok 82 # SKIP write_invalid.0.82
6658 00:44:06.061010 # ok 83 event_missing.0.82
6659 00:44:06.064349 # ok 84 event_spurious.0.82
6660 00:44:06.067369 # ok 85 get_value.0.81
6661 00:44:06.067446 # ok 86 name.0.81
6662 00:44:06.070718 # ok 87 write_default.0.81
6663 00:44:06.077364 # # No event generated for Wake-on-Voice Phase2 Switch
6664 00:44:06.080850 # # No event generated for Wake-on-Voice Phase2 Switch
6665 00:44:06.084036 # ok 88 write_valid.0.81
6666 00:44:06.090726 # # Wake-on-Voice Phase2 Switch.0 Invalid boolean value 2
6667 00:44:06.094371 # # No event generated for Wake-on-Voice Phase2 Switch
6668 00:44:06.097528 # not ok 89 write_invalid.0.81
6669 00:44:06.100551 # not ok 90 event_missing.0.81
6670 00:44:06.103946 # ok 91 event_spurious.0.81
6671 00:44:06.104026 # ok 92 get_value.0.80
6672 00:44:06.107378 # ok 93 name.0.80
6673 00:44:06.107455 # ok 94 write_default.0.80
6674 00:44:06.110679 # ok 95 write_valid.0.80
6675 00:44:06.113990 # ok 96 write_invalid.0.80
6676 00:44:06.117441 # ok 97 event_missing.0.80
6677 00:44:06.117522 # ok 98 event_spurious.0.80
6678 00:44:06.123812 # # Handset Volume.0 value -13 less than minimum 0
6679 00:44:06.127374 # not ok 99 get_value.0.79
6680 00:44:06.127462 # ok 100 name.0.79
6681 00:44:06.133942 # # snd_ctl_elem_write() failed: Invalid argument
6682 00:44:06.134053 # not ok 101 write_default.0.79
6683 00:44:06.140568 # # snd_ctl_elem_write() failed: Invalid argument
6684 00:44:06.143767 # not ok 102 write_valid.0.79
6685 00:44:06.147296 # # snd_ctl_elem_write() failed: Invalid argument
6686 00:44:06.150482 # not ok 103 write_invalid.0.79
6687 00:44:06.153739 # ok 104 event_missing.0.79
6688 00:44:06.157125 # ok 105 event_spurious.0.79
6689 00:44:06.160441 # # Lineout Volume.0 value -13 less than minimum 0
6690 00:44:06.163720 # # Lineout Volume.1 value -13 less than minimum 0
6691 00:44:06.167195 # not ok 106 get_value.0.78
6692 00:44:06.170400 # ok 107 name.0.78
6693 00:44:06.173703 # # snd_ctl_elem_write() failed: Invalid argument
6694 00:44:06.177140 # not ok 108 write_default.0.78
6695 00:44:06.180483 # # snd_ctl_elem_write() failed: Invalid argument
6696 00:44:06.183959 # not ok 109 write_valid.0.78
6697 00:44:06.186955 # # snd_ctl_elem_write() failed: Invalid argument
6698 00:44:06.190364 # not ok 110 write_invalid.0.78
6699 00:44:06.193546 # ok 111 event_missing.0.78
6700 00:44:06.197065 # ok 112 event_spurious.0.78
6701 00:44:06.200198 # # Headphone Volume.0 value -13 less than minimum 0
6702 00:44:06.206816 # # Headphone Volume.1 value -13 less than minimum 0
6703 00:44:06.210250 # not ok 113 get_value.0.77
6704 00:44:06.210350 # ok 114 name.0.77
6705 00:44:06.213468 # # snd_ctl_elem_write() failed: Invalid argument
6706 00:44:06.216684 # not ok 115 write_default.0.77
6707 00:44:06.223477 # # snd_ctl_elem_write() failed: Invalid argument
6708 00:44:06.226810 # not ok 116 write_valid.0.77
6709 00:44:06.230129 # # snd_ctl_elem_write() failed: Invalid argument
6710 00:44:06.233486 # not ok 117 write_invalid.0.77
6711 00:44:06.237075 # ok 118 event_missing.0.77
6712 00:44:06.237152 # ok 119 event_spurious.0.77
6713 00:44:06.240121 # ok 120 get_value.0.76
6714 00:44:06.246920 # # 0.76 ADDA_DL_CH2 PCM_2_CAP_CH2 is a writeable boolean but not a Switch
6715 00:44:06.250064 # not ok 121 name.0.76
6716 00:44:06.250140 # ok 122 write_default.0.76
6717 00:44:06.253452 # ok 123 write_valid.0.76
6718 00:44:06.256836 # ok 124 write_invalid.0.76
6719 00:44:06.260144 # ok 125 event_missing.0.76
6720 00:44:06.263611 # ok 126 event_spurious.0.76
6721 00:44:06.263710 # ok 127 get_value.0.75
6722 00:44:06.270268 # # 0.75 ADDA_DL_CH2 PCM_1_CAP_CH2 is a writeable boolean but not a Switch
6723 00:44:06.273479 # not ok 128 name.0.75
6724 00:44:06.276837 # ok 129 write_default.0.75
6725 00:44:06.276917 # ok 130 write_valid.0.75
6726 00:44:06.280295 # ok 131 write_invalid.0.75
6727 00:44:06.283458 # ok 132 event_missing.0.75
6728 00:44:06.286830 # ok 133 event_spurious.0.75
6729 00:44:06.286906 # ok 134 get_value.0.74
6730 00:44:06.293781 # # 0.74 ADDA_DL_CH2 PCM_2_CAP_CH1 is a writeable boolean but not a Switch
6731 00:44:06.296896 # not ok 135 name.0.74
6732 00:44:06.300077 # ok 136 write_default.0.74
6733 00:44:06.303498 # ok 137 write_valid.0.74
6734 00:44:06.303575 # ok 138 write_invalid.0.74
6735 00:44:06.306689 # ok 139 event_missing.0.74
6736 00:44:06.309980 # ok 140 event_spurious.0.74
6737 00:44:06.313292 # ok 141 get_value.0.73
6738 00:44:06.319860 # # 0.73 ADDA_DL_CH2 PCM_1_CAP_CH1 is a writeable boolean but not a Switch
6739 00:44:06.319940 # not ok 142 name.0.73
6740 00:44:06.323163 # ok 143 write_default.0.73
6741 00:44:06.326640 # ok 144 write_valid.0.73
6742 00:44:06.329882 # ok 145 write_invalid.0.73
6743 00:44:06.329958 # ok 146 event_missing.0.73
6744 00:44:06.333233 # ok 147 event_spurious.0.73
6745 00:44:06.336602 # ok 148 get_value.0.72
6746 00:44:06.343455 # # 0.72 ADDA_DL_CH2 ADDA_UL_CH1 is a writeable boolean but not a Switch
6747 00:44:06.343532 # not ok 149 name.0.72
6748 00:44:06.346537 # ok 150 write_default.0.72
6749 00:44:06.350318 # ok 151 write_valid.0.72
6750 00:44:06.353357 # ok 152 write_invalid.0.72
6751 00:44:06.356784 # ok 153 event_missing.0.72
6752 00:44:06.356862 # ok 154 event_spurious.0.72
6753 00:44:06.359988 # ok 155 get_value.0.71
6754 00:44:06.366766 # # 0.71 ADDA_DL_CH2 ADDA_UL_CH2 is a writeable boolean but not a Switch
6755 00:44:06.369866 # not ok 156 name.0.71
6756 00:44:06.369947 # ok 157 write_default.0.71
6757 00:44:06.373382 # ok 158 write_valid.0.71
6758 00:44:06.376581 # ok 159 write_invalid.0.71
6759 00:44:06.380084 # ok 160 event_missing.0.71
6760 00:44:06.383383 # ok 161 event_spurious.0.71
6761 00:44:06.383459 # ok 162 get_value.0.70
6762 00:44:06.390374 # # 0.70 ADDA_DL_CH2 DL3_CH2 is a writeable boolean but not a Switch
6763 00:44:06.393899 # not ok 163 name.0.70
6764 00:44:06.397170 # ok 164 write_default.0.70
6765 00:44:06.397561 # ok 165 write_valid.0.70
6766 00:44:06.400327 # ok 166 write_invalid.0.70
6767 00:44:06.403585 # ok 167 event_missing.0.70
6768 00:44:06.407518 # ok 168 event_spurious.0.70
6769 00:44:06.407989 # ok 169 get_value.0.69
6770 00:44:06.414100 # # 0.69 ADDA_DL_CH2 DL3_CH1 is a writeable boolean but not a Switch
6771 00:44:06.417004 # not ok 170 name.0.69
6772 00:44:06.420359 # ok 171 write_default.0.69
6773 00:44:06.420749 # ok 172 write_valid.0.69
6774 00:44:06.423933 # ok 173 write_invalid.0.69
6775 00:44:06.426963 # ok 174 event_missing.0.69
6776 00:44:06.430650 # ok 175 event_spurious.0.69
6777 00:44:06.431159 # ok 176 get_value.0.68
6778 00:44:06.437284 # # 0.68 ADDA_DL_CH2 DL2_CH2 is a writeable boolean but not a Switch
6779 00:44:06.440374 # not ok 177 name.0.68
6780 00:44:06.443627 # ok 178 write_default.0.68
6781 00:44:06.444053 # ok 179 write_valid.0.68
6782 00:44:06.447029 # ok 180 write_invalid.0.68
6783 00:44:06.450168 # ok 181 event_missing.0.68
6784 00:44:06.453986 # ok 182 event_spurious.0.68
6785 00:44:06.454471 # ok 183 get_value.0.67
6786 00:44:06.460501 # # 0.67 ADDA_DL_CH2 DL2_CH1 is a writeable boolean but not a Switch
6787 00:44:06.463616 # not ok 184 name.0.67
6788 00:44:06.467057 # ok 185 write_default.0.67
6789 00:44:06.467483 # ok 186 write_valid.0.67
6790 00:44:06.470498 # ok 187 write_invalid.0.67
6791 00:44:06.473850 # ok 188 event_missing.0.67
6792 00:44:06.476701 # ok 189 event_spurious.0.67
6793 00:44:06.477133 # ok 190 get_value.0.66
6794 00:44:06.483474 # # 0.66 ADDA_DL_CH2 DL1_CH2 is a writeable boolean but not a Switch
6795 00:44:06.486848 # not ok 191 name.0.66
6796 00:44:06.490113 # ok 192 write_default.0.66
6797 00:44:06.490574 # ok 193 write_valid.0.66
6798 00:44:06.493356 # ok 194 write_invalid.0.66
6799 00:44:06.496778 # ok 195 event_missing.0.66
6800 00:44:06.500243 # ok 196 event_spurious.0.66
6801 00:44:06.503628 # ok 197 get_value.0.65
6802 00:44:06.506884 # # 0.65 ADDA_DL_CH2 DL1_CH1 is a writeable boolean but not a Switch
6803 00:44:06.509896 # not ok 198 name.0.65
6804 00:44:06.513817 # ok 199 write_default.0.65
6805 00:44:06.516870 # ok 200 write_valid.0.65
6806 00:44:06.517424 # ok 201 write_invalid.0.65
6807 00:44:06.520105 # ok 202 event_missing.0.65
6808 00:44:06.523563 # ok 203 event_spurious.0.65
6809 00:44:06.527052 # ok 204 get_value.0.64
6810 00:44:06.533678 # # 0.64 ADDA_DL_CH1 PCM_2_CAP_CH1 is a writeable boolean but not a Switch
6811 00:44:06.534189 # not ok 205 name.0.64
6812 00:44:06.536921 # ok 206 write_default.0.64
6813 00:44:06.540070 # ok 207 write_valid.0.64
6814 00:44:06.543670 # ok 208 write_invalid.0.64
6815 00:44:06.544098 # ok 209 event_missing.0.64
6816 00:44:06.546785 # ok 210 event_spurious.0.64
6817 00:44:06.550269 # ok 211 get_value.0.63
6818 00:44:06.556588 # # 0.63 ADDA_DL_CH1 PCM_1_CAP_CH1 is a writeable boolean but not a Switch
6819 00:44:06.557023 # not ok 212 name.0.63
6820 00:44:06.559886 # ok 213 write_default.0.63
6821 00:44:06.563428 # ok 214 write_valid.0.63
6822 00:44:06.566504 # ok 215 write_invalid.0.63
6823 00:44:06.570101 # ok 216 event_missing.0.63
6824 00:44:06.570660 # ok 217 event_spurious.0.63
6825 00:44:06.573545 # ok 218 get_value.0.62
6826 00:44:06.579868 # # 0.62 ADDA_DL_CH1 ADDA_UL_CH1 is a writeable boolean but not a Switch
6827 00:44:06.583135 # not ok 219 name.0.62
6828 00:44:06.583566 # ok 220 write_default.0.62
6829 00:44:06.587024 # ok 221 write_valid.0.62
6830 00:44:06.589816 # ok 222 write_invalid.0.62
6831 00:44:06.593727 # ok 223 event_missing.0.62
6832 00:44:06.597046 # ok 224 event_spurious.0.62
6833 00:44:06.597551 # ok 225 get_value.0.61
6834 00:44:06.603392 # # 0.61 ADDA_DL_CH1 ADDA_UL_CH2 is a writeable boolean but not a Switch
6835 00:44:06.606936 # not ok 226 name.0.61
6836 00:44:06.609939 # ok 227 write_default.0.61
6837 00:44:06.610431 # ok 228 write_valid.0.61
6838 00:44:06.613555 # ok 229 write_invalid.0.61
6839 00:44:06.616762 # ok 230 event_missing.0.61
6840 00:44:06.620187 # ok 231 event_spurious.0.61
6841 00:44:06.620692 # ok 232 get_value.0.60
6842 00:44:06.626909 # # 0.60 ADDA_DL_CH1 DL3_CH1 is a writeable boolean but not a Switch
6843 00:44:06.629789 # not ok 233 name.0.60
6844 00:44:06.633147 # ok 234 write_default.0.60
6845 00:44:06.633571 # ok 235 write_valid.0.60
6846 00:44:06.636586 # ok 236 write_invalid.0.60
6847 00:44:06.640131 # ok 237 event_missing.0.60
6848 00:44:06.643336 # ok 238 event_spurious.0.60
6849 00:44:06.643769 # ok 239 get_value.0.59
6850 00:44:06.650315 # # 0.59 ADDA_DL_CH1 DL2_CH1 is a writeable boolean but not a Switch
6851 00:44:06.653151 # not ok 240 name.0.59
6852 00:44:06.656483 # ok 241 write_default.0.59
6853 00:44:06.656910 # ok 242 write_valid.0.59
6854 00:44:06.659820 # ok 243 write_invalid.0.59
6855 00:44:06.663018 # ok 244 event_missing.0.59
6856 00:44:06.666345 # ok 245 event_spurious.0.59
6857 00:44:06.666775 # ok 246 get_value.0.58
6858 00:44:06.673384 # # 0.58 ADDA_DL_CH1 DL1_CH1 is a writeable boolean but not a Switch
6859 00:44:06.676718 # not ok 247 name.0.58
6860 00:44:06.680006 # ok 248 write_default.0.58
6861 00:44:06.680433 # ok 249 write_valid.0.58
6862 00:44:06.683213 # ok 250 write_invalid.0.58
6863 00:44:06.686518 # ok 251 event_missing.0.58
6864 00:44:06.689971 # ok 252 event_spurious.0.58
6865 00:44:06.690438 # ok 253 get_value.0.57
6866 00:44:06.696800 # # 0.57 I2S5_CH2 DL3_CH2 is a writeable boolean but not a Switch
6867 00:44:06.699758 # not ok 254 name.0.57
6868 00:44:06.703298 # ok 255 write_default.0.57
6869 00:44:06.703804 # ok 256 write_valid.0.57
6870 00:44:06.706862 # ok 257 write_invalid.0.57
6871 00:44:06.709836 # ok 258 event_missing.0.57
6872 00:44:06.713655 # ok 259 event_spurious.0.57
6873 00:44:06.714164 # ok 260 get_value.0.56
6874 00:44:06.720020 # # 0.56 I2S5_CH2 DL2_CH2 is a writeable boolean but not a Switch
6875 00:44:06.723146 # not ok 261 name.0.56
6876 00:44:06.726514 # ok 262 write_default.0.56
6877 00:44:06.726939 # ok 263 write_valid.0.56
6878 00:44:06.729843 # ok 264 write_invalid.0.56
6879 00:44:06.733200 # ok 265 event_missing.0.56
6880 00:44:06.736550 # ok 266 event_spurious.0.56
6881 00:44:06.737059 # ok 267 get_value.0.55
6882 00:44:06.743012 # # 0.55 I2S5_CH2 DL1_CH2 is a writeable boolean but not a Switch
6883 00:44:06.746515 # not ok 268 name.0.55
6884 00:44:06.749926 # ok 269 write_default.0.55
6885 00:44:06.750471 # ok 270 write_valid.0.55
6886 00:44:06.753014 # ok 271 write_invalid.0.55
6887 00:44:06.756435 # ok 272 event_missing.0.55
6888 00:44:06.759758 # ok 273 event_spurious.0.55
6889 00:44:06.760292 # ok 274 get_value.0.54
6890 00:44:06.766200 # # 0.54 I2S5_CH1 DL3_CH1 is a writeable boolean but not a Switch
6891 00:44:06.769622 # not ok 275 name.0.54
6892 00:44:06.773092 # ok 276 write_default.0.54
6893 00:44:06.773599 # ok 277 write_valid.0.54
6894 00:44:06.776035 # ok 278 write_invalid.0.54
6895 00:44:06.779291 # ok 279 event_missing.0.54
6896 00:44:06.782714 # ok 280 event_spurious.0.54
6897 00:44:06.783151 # ok 281 get_value.0.53
6898 00:44:06.789317 # # 0.53 I2S5_CH1 DL2_CH1 is a writeable boolean but not a Switch
6899 00:44:06.793204 # not ok 282 name.0.53
6900 00:44:06.796404 # ok 283 write_default.0.53
6901 00:44:06.796911 # ok 284 write_valid.0.53
6902 00:44:06.799492 # ok 285 write_invalid.0.53
6903 00:44:06.803150 # ok 286 event_missing.0.53
6904 00:44:06.806389 # ok 287 event_spurious.0.53
6905 00:44:06.806897 # ok 288 get_value.0.52
6906 00:44:06.812986 # # 0.52 I2S5_CH1 DL1_CH1 is a writeable boolean but not a Switch
6907 00:44:06.816013 # not ok 289 name.0.52
6908 00:44:06.819744 # ok 290 write_default.0.52
6909 00:44:06.820276 # ok 291 write_valid.0.52
6910 00:44:06.823191 # ok 292 write_invalid.0.52
6911 00:44:06.826563 # ok 293 event_missing.0.52
6912 00:44:06.829557 # ok 294 event_spurious.0.52
6913 00:44:06.830001 # ok 295 get_value.0.51
6914 00:44:06.836692 # # 0.51 I2S3_CH2 DL3_CH2 is a writeable boolean but not a Switch
6915 00:44:06.839410 # not ok 296 name.0.51
6916 00:44:06.843220 # ok 297 write_default.0.51
6917 00:44:06.843727 # ok 298 write_valid.0.51
6918 00:44:06.846364 # ok 299 write_invalid.0.51
6919 00:44:06.849912 # ok 300 event_missing.0.51
6920 00:44:06.853161 # ok 301 event_spurious.0.51
6921 00:44:06.853595 # ok 302 get_value.0.50
6922 00:44:06.859419 # # 0.50 I2S3_CH2 DL2_CH2 is a writeable boolean but not a Switch
6923 00:44:06.862796 # not ok 303 name.0.50
6924 00:44:06.866328 # ok 304 write_default.0.50
6925 00:44:06.866833 # ok 305 write_valid.0.50
6926 00:44:06.869772 # ok 306 write_invalid.0.50
6927 00:44:06.873318 # ok 307 event_missing.0.50
6928 00:44:06.876397 # ok 308 event_spurious.0.50
6929 00:44:06.876842 # ok 309 get_value.0.49
6930 00:44:06.882906 # # 0.49 I2S3_CH2 DL1_CH2 is a writeable boolean but not a Switch
6931 00:44:06.886188 # not ok 310 name.0.49
6932 00:44:06.886660 # ok 311 write_default.0.49
6933 00:44:06.889641 # ok 312 write_valid.0.49
6934 00:44:06.892977 # ok 313 write_invalid.0.49
6935 00:44:06.896162 # ok 314 event_missing.0.49
6936 00:44:06.899661 # ok 315 event_spurious.0.49
6937 00:44:06.900183 # ok 316 get_value.0.48
6938 00:44:06.906380 # # 0.48 I2S3_CH1 DL3_CH1 is a writeable boolean but not a Switch
6939 00:44:06.909727 # not ok 317 name.0.48
6940 00:44:06.910277 # ok 318 write_default.0.48
6941 00:44:06.913103 # ok 319 write_valid.0.48
6942 00:44:06.916117 # ok 320 write_invalid.0.48
6943 00:44:06.919562 # ok 321 event_missing.0.48
6944 00:44:06.922955 # ok 322 event_spurious.0.48
6945 00:44:06.923459 # ok 323 get_value.0.47
6946 00:44:06.929571 # # 0.47 I2S3_CH1 DL2_CH1 is a writeable boolean but not a Switch
6947 00:44:06.932586 # not ok 324 name.0.47
6948 00:44:06.933017 # ok 325 write_default.0.47
6949 00:44:06.936178 # ok 326 write_valid.0.47
6950 00:44:06.939317 # ok 327 write_invalid.0.47
6951 00:44:06.942731 # ok 328 event_missing.0.47
6952 00:44:06.946358 # ok 329 event_spurious.0.47
6953 00:44:06.946862 # ok 330 get_value.0.46
6954 00:44:06.952920 # # 0.46 I2S3_CH1 DL1_CH1 is a writeable boolean but not a Switch
6955 00:44:06.956194 # not ok 331 name.0.46
6956 00:44:06.956629 # ok 332 write_default.0.46
6957 00:44:06.959371 # ok 333 write_valid.0.46
6958 00:44:06.962715 # ok 334 write_invalid.0.46
6959 00:44:06.966114 # ok 335 event_missing.0.46
6960 00:44:06.966663 # ok 336 event_spurious.0.46
6961 00:44:06.969409 # ok 337 get_value.0.45
6962 00:44:06.976026 # # 0.45 I2S1_CH2 DL3_CH2 is a writeable boolean but not a Switch
6963 00:44:06.979541 # not ok 338 name.0.45
6964 00:44:06.979975 # ok 339 write_default.0.45
6965 00:44:06.982777 # ok 340 write_valid.0.45
6966 00:44:06.985969 # ok 341 write_invalid.0.45
6967 00:44:06.986585 # ok 342 event_missing.0.45
6968 00:44:06.989652 # ok 343 event_spurious.0.45
6969 00:44:06.992845 # ok 344 get_value.0.44
6970 00:44:06.999352 # # 0.44 I2S1_CH2 DL2_CH2 is a writeable boolean but not a Switch
6971 00:44:06.999863 # not ok 345 name.0.44
6972 00:44:07.002605 # ok 346 write_default.0.44
6973 00:44:07.005877 # ok 347 write_valid.0.44
6974 00:44:07.008938 # ok 348 write_invalid.0.44
6975 00:44:07.009372 # ok 349 event_missing.0.44
6976 00:44:07.012467 # ok 350 event_spurious.0.44
6977 00:44:07.015807 # ok 351 get_value.0.43
6978 00:44:07.022592 # # 0.43 I2S1_CH2 DL1_CH2 is a writeable boolean but not a Switch
6979 00:44:07.023114 # not ok 352 name.0.43
6980 00:44:07.025945 # ok 353 write_default.0.43
6981 00:44:07.029454 # ok 354 write_valid.0.43
6982 00:44:07.029970 # ok 355 write_invalid.0.43
6983 00:44:07.032535 # ok 356 event_missing.0.43
6984 00:44:07.035773 # ok 357 event_spurious.0.43
6985 00:44:07.039100 # ok 358 get_value.0.42
6986 00:44:07.042518 # # 0.42 I2S1_CH1 DL3_CH1 is a writeable boolean but not a Switch
6987 00:44:07.046054 # not ok 359 name.0.42
6988 00:44:07.048896 # ok 360 write_default.0.42
6989 00:44:07.052445 # ok 361 write_valid.0.42
6990 00:44:07.052998 # ok 362 write_invalid.0.42
6991 00:44:07.055534 # ok 363 event_missing.0.42
6992 00:44:07.058791 # ok 364 event_spurious.0.42
6993 00:44:07.062121 # ok 365 get_value.0.41
6994 00:44:07.065946 # # 0.41 I2S1_CH1 DL2_CH1 is a writeable boolean but not a Switch
6995 00:44:07.068957 # not ok 366 name.0.41
6996 00:44:07.072338 # ok 367 write_default.0.41
6997 00:44:07.075735 # ok 368 write_valid.0.41
6998 00:44:07.076242 # ok 369 write_invalid.0.41
6999 00:44:07.078701 # ok 370 event_missing.0.41
7000 00:44:07.082197 # ok 371 event_spurious.0.41
7001 00:44:07.085810 # ok 372 get_value.0.40
7002 00:44:07.088995 # # 0.40 I2S1_CH1 DL1_CH1 is a writeable boolean but not a Switch
7003 00:44:07.092595 # not ok 373 name.0.40
7004 00:44:07.095844 # ok 374 write_default.0.40
7005 00:44:07.098830 # ok 375 write_valid.0.40
7006 00:44:07.099259 # ok 376 write_invalid.0.40
7007 00:44:07.102447 # ok 377 event_missing.0.40
7008 00:44:07.105650 # ok 378 event_spurious.0.40
7009 00:44:07.108980 # ok 379 get_value.0.39
7010 00:44:07.111887 # # 0.39 PCM_2_PB_CH4 DL1_CH1 is a writeable boolean but not a Switch
7011 00:44:07.115194 # not ok 380 name.0.39
7012 00:44:07.119019 # ok 381 write_default.0.39
7013 00:44:07.122150 # ok 382 write_valid.0.39
7014 00:44:07.122727 # ok 383 write_invalid.0.39
7015 00:44:07.125464 # ok 384 event_missing.0.39
7016 00:44:07.128775 # ok 385 event_spurious.0.39
7017 00:44:07.132060 # ok 386 get_value.0.38
7018 00:44:07.135524 # # 0.38 PCM_2_PB_CH2 DL2_CH2 is a writeable boolean but not a Switch
7019 00:44:07.138561 # not ok 387 name.0.38
7020 00:44:07.142004 # ok 388 write_default.0.38
7021 00:44:07.142568 # ok 389 write_valid.0.38
7022 00:44:07.145461 # ok 390 write_invalid.0.38
7023 00:44:07.148898 # ok 391 event_missing.0.38
7024 00:44:07.152027 # ok 392 event_spurious.0.38
7025 00:44:07.152529 # ok 393 get_value.0.37
7026 00:44:07.158603 # # 0.37 PCM_2_PB_CH2 ADDA_UL_CH2 is a writeable boolean but not a Switch
7027 00:44:07.161875 # not ok 394 name.0.37
7028 00:44:07.165247 # ok 395 write_default.0.37
7029 00:44:07.165769 # ok 396 write_valid.0.37
7030 00:44:07.168602 # ok 397 write_invalid.0.37
7031 00:44:07.172005 # ok 398 event_missing.0.37
7032 00:44:07.174959 # ok 399 event_spurious.0.37
7033 00:44:07.175387 # ok 400 get_value.0.36
7034 00:44:07.181738 # # 0.36 PCM_2_PB_CH1 DL2_CH1 is a writeable boolean but not a Switch
7035 00:44:07.184772 # not ok 401 name.0.36
7036 00:44:07.188486 # ok 402 write_default.0.36
7037 00:44:07.188993 # ok 403 write_valid.0.36
7038 00:44:07.191548 # ok 404 write_invalid.0.36
7039 00:44:07.194835 # ok 405 event_missing.0.36
7040 00:44:07.198471 # ok 406 event_spurious.0.36
7041 00:44:07.201745 # ok 407 get_value.0.35
7042 00:44:07.208068 # # 0.35 PCM_2_PB_CH1 ADDA_UL_CH1 is a writeable boolean but not a Switch
7043 00:44:07.208575 # not ok 408 name.0.35
7044 00:44:07.211620 # ok 409 write_default.0.35
7045 00:44:07.214865 # ok 410 write_valid.0.35
7046 00:44:07.215381 # ok 411 write_invalid.0.35
7047 00:44:07.217971 # ok 412 event_missing.0.35
7048 00:44:07.221431 # ok 413 event_spurious.0.35
7049 00:44:07.224622 # ok 414 get_value.0.34
7050 00:44:07.231341 # # 0.34 PCM_1_PB_CH4 DL1_CH1 is a writeable boolean but not a Switch
7051 00:44:07.231776 # not ok 415 name.0.34
7052 00:44:07.234837 # ok 416 write_default.0.34
7053 00:44:07.237866 # ok 417 write_valid.0.34
7054 00:44:07.241478 # ok 418 write_invalid.0.34
7055 00:44:07.242108 # ok 419 event_missing.0.34
7056 00:44:07.244547 # ok 420 event_spurious.0.34
7057 00:44:07.247887 # ok 421 get_value.0.33
7058 00:44:07.254714 # # 0.33 PCM_1_PB_CH2 DL2_CH2 is a writeable boolean but not a Switch
7059 00:44:07.255225 # not ok 422 name.0.33
7060 00:44:07.258015 # ok 423 write_default.0.33
7061 00:44:07.261531 # ok 424 write_valid.0.33
7062 00:44:07.264509 # ok 425 write_invalid.0.33
7063 00:44:07.264939 # ok 426 event_missing.0.33
7064 00:44:07.268176 # ok 427 event_spurious.0.33
7065 00:44:07.271247 # ok 428 get_value.0.32
7066 00:44:07.278010 # # 0.32 PCM_1_PB_CH2 ADDA_UL_CH2 is a writeable boolean but not a Switch
7067 00:44:07.281004 # not ok 429 name.0.32
7068 00:44:07.281441 # ok 430 write_default.0.32
7069 00:44:07.284497 # ok 431 write_valid.0.32
7070 00:44:07.287748 # ok 432 write_invalid.0.32
7071 00:44:07.291033 # ok 433 event_missing.0.32
7072 00:44:07.291466 # ok 434 event_spurious.0.32
7073 00:44:07.295073 # ok 435 get_value.0.31
7074 00:44:07.301229 # # 0.31 PCM_1_PB_CH1 DL2_CH1 is a writeable boolean but not a Switch
7075 00:44:07.304359 # not ok 436 name.0.31
7076 00:44:07.304790 # ok 437 write_default.0.31
7077 00:44:07.308024 # ok 438 write_valid.0.31
7078 00:44:07.311224 # ok 439 write_invalid.0.31
7079 00:44:07.314395 # ok 440 event_missing.0.31
7080 00:44:07.317738 # ok 441 event_spurious.0.31
7081 00:44:07.318470 # ok 442 get_value.0.30
7082 00:44:07.324461 # # 0.30 PCM_1_PB_CH1 ADDA_UL_CH1 is a writeable boolean but not a Switch
7083 00:44:07.327842 # not ok 443 name.0.30
7084 00:44:07.331063 # ok 444 write_default.0.30
7085 00:44:07.331571 # ok 445 write_valid.0.30
7086 00:44:07.334143 # ok 446 write_invalid.0.30
7087 00:44:07.337896 # ok 447 event_missing.0.30
7088 00:44:07.340815 # ok 448 event_spurious.0.30
7089 00:44:07.341249 # ok 449 get_value.0.29
7090 00:44:07.344036 # ok 450 name.0.29
7091 00:44:07.347657 # ok 451 write_default.0.29
7092 00:44:07.348191 # ok 452 write_valid.0.29
7093 00:44:07.350705 # ok 453 write_invalid.0.29
7094 00:44:07.354068 # ok 454 event_missing.0.29
7095 00:44:07.357417 # ok 455 event_spurious.0.29
7096 00:44:07.360686 # ok 456 get_value.0.28
7097 00:44:07.361117 # ok 457 name.0.28
7098 00:44:07.364046 # ok 458 write_default.0.28
7099 00:44:07.367489 # ok 459 write_valid.0.28
7100 00:44:07.367918 # ok 460 write_invalid.0.28
7101 00:44:07.370673 # ok 461 event_missing.0.28
7102 00:44:07.374117 # ok 462 event_spurious.0.28
7103 00:44:07.377482 # ok 463 get_value.0.27
7104 00:44:07.377986 # ok 464 name.0.27
7105 00:44:07.380673 # ok 465 write_default.0.27
7106 00:44:07.384032 # ok 466 write_valid.0.27
7107 00:44:07.384458 # ok 467 write_invalid.0.27
7108 00:44:07.387321 # ok 468 event_missing.0.27
7109 00:44:07.390521 # ok 469 event_spurious.0.27
7110 00:44:07.394356 # ok 470 get_value.0.26
7111 00:44:07.394869 # ok 471 name.0.26
7112 00:44:07.397486 # ok 472 write_default.0.26
7113 00:44:07.400731 # ok 473 write_valid.0.26
7114 00:44:07.403762 # ok 474 write_invalid.0.26
7115 00:44:07.404189 # ok 475 event_missing.0.26
7116 00:44:07.407598 # ok 476 event_spurious.0.26
7117 00:44:07.410892 # ok 477 get_value.0.25
7118 00:44:07.411443 # ok 478 name.0.25
7119 00:44:07.414166 # ok 479 write_default.0.25
7120 00:44:07.417429 # ok 480 write_valid.0.25
7121 00:44:07.420534 # ok 481 write_invalid.0.25
7122 00:44:07.420964 # ok 482 event_missing.0.25
7123 00:44:07.424277 # ok 483 event_spurious.0.25
7124 00:44:07.427140 # ok 484 get_value.0.24
7125 00:44:07.427574 # ok 485 name.0.24
7126 00:44:07.430687 # ok 486 write_default.0.24
7127 00:44:07.434134 # ok 487 write_valid.0.24
7128 00:44:07.437378 # ok 488 write_invalid.0.24
7129 00:44:07.437810 # ok 489 event_missing.0.24
7130 00:44:07.440630 # ok 490 event_spurious.0.24
7131 00:44:07.444280 # ok 491 get_value.0.23
7132 00:44:07.444810 # ok 492 name.0.23
7133 00:44:07.447425 # ok 493 write_default.0.23
7134 00:44:07.450754 # ok 494 write_valid.0.23
7135 00:44:07.454171 # ok 495 write_invalid.0.23
7136 00:44:07.454717 # ok 496 event_missing.0.23
7137 00:44:07.457477 # ok 497 event_spurious.0.23
7138 00:44:07.460588 # ok 498 get_value.0.22
7139 00:44:07.461021 # ok 499 name.0.22
7140 00:44:07.463990 # ok 500 write_default.0.22
7141 00:44:07.467288 # ok 501 write_valid.0.22
7142 00:44:07.470674 # ok 502 write_invalid.0.22
7143 00:44:07.473779 # ok 503 event_missing.0.22
7144 00:44:07.474245 # ok 504 event_spurious.0.22
7145 00:44:07.477451 # ok 505 get_value.0.21
7146 00:44:07.484411 # # 0.21 UL_MONO_1_CH1 ADDA_UL_CH2 is a writeable boolean but not a Switch
7147 00:44:07.487280 # not ok 506 name.0.21
7148 00:44:07.487764 # ok 507 write_default.0.21
7149 00:44:07.490774 # ok 508 write_valid.0.21
7150 00:44:07.494115 # ok 509 write_invalid.0.21
7151 00:44:07.497437 # ok 510 event_missing.0.21
7152 00:44:07.500656 # ok 511 event_spurious.0.21
7153 00:44:07.501405 # ok 512 get_value.0.20
7154 00:44:07.507228 # # 0.20 UL_MONO_1_CH1 ADDA_UL_CH1 is a writeable boolean but not a Switch
7155 00:44:07.510853 # not ok 513 name.0.20
7156 00:44:07.514303 # ok 514 write_default.0.20
7157 00:44:07.514812 # ok 515 write_valid.0.20
7158 00:44:07.517598 # ok 516 write_invalid.0.20
7159 00:44:07.520592 # ok 517 event_missing.0.20
7160 00:44:07.524293 # ok 518 event_spurious.0.20
7161 00:44:07.524799 # ok 519 get_value.0.19
7162 00:44:07.530771 # # 0.19 UL4_CH2 ADDA_UL_CH2 is a writeable boolean but not a Switch
7163 00:44:07.534233 # not ok 520 name.0.19
7164 00:44:07.537629 # ok 521 write_default.0.19
7165 00:44:07.538427 # ok 522 write_valid.0.19
7166 00:44:07.540657 # ok 523 write_invalid.0.19
7167 00:44:07.543908 # ok 524 event_missing.0.19
7168 00:44:07.547415 # ok 525 event_spurious.0.19
7169 00:44:07.547846 # ok 526 get_value.0.18
7170 00:44:07.554039 # # 0.18 UL4_CH1 ADDA_UL_CH1 is a writeable boolean but not a Switch
7171 00:44:07.557421 # not ok 527 name.0.18
7172 00:44:07.560610 # ok 528 write_default.0.18
7173 00:44:07.561042 # ok 529 write_valid.0.18
7174 00:44:07.564318 # ok 530 write_invalid.0.18
7175 00:44:07.567403 # ok 531 event_missing.0.18
7176 00:44:07.570551 # ok 532 event_spurious.0.18
7177 00:44:07.574039 # ok 533 get_value.0.17
7178 00:44:07.577225 # # 0.17 UL3_CH2 I2S2_CH2 is a writeable boolean but not a Switch
7179 00:44:07.580490 # not ok 534 name.0.17
7180 00:44:07.583932 # ok 535 write_default.0.17
7181 00:44:07.584361 # ok 536 write_valid.0.17
7182 00:44:07.587097 # ok 537 write_invalid.0.17
7183 00:44:07.590532 # ok 538 event_missing.0.17
7184 00:44:07.593932 # ok 539 event_spurious.0.17
7185 00:44:07.594499 # ok 540 get_value.0.16
7186 00:44:07.600937 # # 0.16 UL3_CH2 ADDA_UL_CH2 is a writeable boolean but not a Switch
7187 00:44:07.604017 # not ok 541 name.0.16
7188 00:44:07.607496 # ok 542 write_default.0.16
7189 00:44:07.610548 # ok 543 write_valid.0.16
7190 00:44:07.610986 # ok 544 write_invalid.0.16
7191 00:44:07.614137 # ok 545 event_missing.0.16
7192 00:44:07.617558 # ok 546 event_spurious.0.16
7193 00:44:07.620805 # ok 547 get_value.0.15
7194 00:44:07.624132 # # 0.15 UL3_CH1 I2S2_CH1 is a writeable boolean but not a Switch
7195 00:44:07.627648 # not ok 548 name.0.15
7196 00:44:07.630800 # ok 549 write_default.0.15
7197 00:44:07.631321 # ok 550 write_valid.0.15
7198 00:44:07.633994 # ok 551 write_invalid.0.15
7199 00:44:07.637553 # ok 552 event_missing.0.15
7200 00:44:07.640427 # ok 553 event_spurious.0.15
7201 00:44:07.644124 # ok 554 get_value.0.14
7202 00:44:07.647101 # # 0.14 UL3_CH1 ADDA_UL_CH1 is a writeable boolean but not a Switch
7203 00:44:07.650809 # not ok 555 name.0.14
7204 00:44:07.654353 # ok 556 write_default.0.14
7205 00:44:07.657253 # ok 557 write_valid.0.14
7206 00:44:07.657687 # ok 558 write_invalid.0.14
7207 00:44:07.660374 # ok 559 event_missing.0.14
7208 00:44:07.663944 # ok 560 event_spurious.0.14
7209 00:44:07.667347 # ok 561 get_value.0.13
7210 00:44:07.670427 # # 0.13 UL2_CH2 I2S2_CH2 is a writeable boolean but not a Switch
7211 00:44:07.673895 # not ok 562 name.0.13
7212 00:44:07.677461 # ok 563 write_default.0.13
7213 00:44:07.677972 # ok 564 write_valid.0.13
7214 00:44:07.680291 # ok 565 write_invalid.0.13
7215 00:44:07.683845 # ok 566 event_missing.0.13
7216 00:44:07.686933 # ok 567 event_spurious.0.13
7217 00:44:07.690207 # ok 568 get_value.0.12
7218 00:44:07.693537 # # 0.12 UL2_CH2 ADDA_UL_CH2 is a writeable boolean but not a Switch
7219 00:44:07.696971 # not ok 569 name.0.12
7220 00:44:07.700716 # ok 570 write_default.0.12
7221 00:44:07.704006 # ok 571 write_valid.0.12
7222 00:44:07.704535 # ok 572 write_invalid.0.12
7223 00:44:07.706792 # ok 573 event_missing.0.12
7224 00:44:07.710470 # ok 574 event_spurious.0.12
7225 00:44:07.713624 # ok 575 get_value.0.11
7226 00:44:07.716782 # # 0.11 UL2_CH1 I2S2_CH1 is a writeable boolean but not a Switch
7227 00:44:07.720140 # not ok 576 name.0.11
7228 00:44:07.723629 # ok 577 write_default.0.11
7229 00:44:07.727225 # ok 578 write_valid.0.11
7230 00:44:07.727739 # ok 579 write_invalid.0.11
7231 00:44:07.730360 # ok 580 event_missing.0.11
7232 00:44:07.733568 # ok 581 event_spurious.0.11
7233 00:44:07.736855 # ok 582 get_value.0.10
7234 00:44:07.740329 # # 0.10 UL2_CH1 ADDA_UL_CH1 is a writeable boolean but not a Switch
7235 00:44:07.743521 # not ok 583 name.0.10
7236 00:44:07.746680 # ok 584 write_default.0.10
7237 00:44:07.750278 # ok 585 write_valid.0.10
7238 00:44:07.750791 # ok 586 write_invalid.0.10
7239 00:44:07.753468 # ok 587 event_missing.0.10
7240 00:44:07.757009 # ok 588 event_spurious.0.10
7241 00:44:07.759968 # ok 589 get_value.0.9
7242 00:44:07.763724 # # 0.9 UL1_CH2 I2S0_CH2 is a writeable boolean but not a Switch
7243 00:44:07.766799 # not ok 590 name.0.9
7244 00:44:07.770007 # ok 591 write_default.0.9
7245 00:44:07.770483 # ok 592 write_valid.0.9
7246 00:44:07.773727 # ok 593 write_invalid.0.9
7247 00:44:07.777216 # ok 594 event_missing.0.9
7248 00:44:07.780089 # ok 595 event_spurious.0.9
7249 00:44:07.780520 # ok 596 get_value.0.8
7250 00:44:07.786815 # # 0.8 UL1_CH2 ADDA_UL_CH2 is a writeable boolean but not a Switch
7251 00:44:07.789882 # not ok 597 name.0.8
7252 00:44:07.793346 # ok 598 write_default.0.8
7253 00:44:07.793864 # ok 599 write_valid.0.8
7254 00:44:07.796657 # ok 600 write_invalid.0.8
7255 00:44:07.800548 # ok 601 event_missing.0.8
7256 00:44:07.803720 # ok 602 event_spurious.0.8
7257 00:44:07.804225 # ok 603 get_value.0.7
7258 00:44:07.810355 # # 0.7 UL1_CH1 I2S0_CH1 is a writeable boolean but not a Switch
7259 00:44:07.813664 # not ok 604 name.0.7
7260 00:44:07.814194 # ok 605 write_default.0.7
7261 00:44:07.817087 # ok 606 write_valid.0.7
7262 00:44:07.820332 # ok 607 write_invalid.0.7
7263 00:44:07.823635 # ok 608 event_missing.0.7
7264 00:44:07.824144 # ok 609 event_spurious.0.7
7265 00:44:07.826946 # ok 610 get_value.0.6
7266 00:44:07.833650 # # 0.6 UL1_CH1 ADDA_UL_CH1 is a writeable boolean but not a Switch
7267 00:44:07.834164 # not ok 611 name.0.6
7268 00:44:07.836658 # ok 612 write_default.0.6
7269 00:44:07.840362 # ok 613 write_valid.0.6
7270 00:44:07.843471 # ok 614 write_invalid.0.6
7271 00:44:07.843974 # ok 615 event_missing.0.6
7272 00:44:07.846929 # ok 616 event_spurious.0.6
7273 00:44:07.850024 # ok 617 get_value.0.5
7274 00:44:07.850578 # ok 618 name.0.5
7275 00:44:07.853411 # ok 619 write_default.0.5
7276 00:44:07.856950 # # No event generated for MTKAIF_DMIC
7277 00:44:07.859956 # # No event generated for MTKAIF_DMIC
7278 00:44:07.863247 # ok 620 write_valid.0.5
7279 00:44:07.866590 # ok 621 write_invalid.0.5
7280 00:44:07.869874 # not ok 622 event_missing.0.5
7281 00:44:07.870335 # ok 623 event_spurious.0.5
7282 00:44:07.873088 # ok 624 get_value.0.4
7283 00:44:07.873654 # ok 625 name.0.4
7284 00:44:07.876871 # ok 626 write_default.0.4
7285 00:44:07.880142 # # No event generated for I2S5_HD_Mux
7286 00:44:07.883326 # # No event generated for I2S5_HD_Mux
7287 00:44:07.886462 # ok 627 write_valid.0.4
7288 00:44:07.889846 # ok 628 write_invalid.0.4
7289 00:44:07.890455 # not ok 629 event_missing.0.4
7290 00:44:07.893233 # ok 630 event_spurious.0.4
7291 00:44:07.896799 # ok 631 get_value.0.3
7292 00:44:07.897382 # ok 632 name.0.3
7293 00:44:07.899914 # ok 633 write_default.0.3
7294 00:44:07.903115 # # No event generated for I2S3_HD_Mux
7295 00:44:07.906449 # # No event generated for I2S3_HD_Mux
7296 00:44:07.909852 # ok 634 write_valid.0.3
7297 00:44:07.912822 # ok 635 write_invalid.0.3
7298 00:44:07.916590 # not ok 636 event_missing.0.3
7299 00:44:07.917030 # ok 637 event_spurious.0.3
7300 00:44:07.919825 # ok 638 get_value.0.2
7301 00:44:07.920255 # ok 639 name.0.2
7302 00:44:07.923075 # ok 640 write_default.0.2
7303 00:44:07.926327 # # No event generated for I2S2_HD_Mux
7304 00:44:07.929800 # # No event generated for I2S2_HD_Mux
7305 00:44:07.933335 # ok 641 write_valid.0.2
7306 00:44:07.936507 # ok 642 write_invalid.0.2
7307 00:44:07.936935 # not ok 643 event_missing.0.2
7308 00:44:07.939719 # ok 644 event_spurious.0.2
7309 00:44:07.942979 # ok 645 get_value.0.1
7310 00:44:07.943419 # ok 646 name.0.1
7311 00:44:07.946273 # ok 647 write_default.0.1
7312 00:44:07.949681 # # No event generated for I2S1_HD_Mux
7313 00:44:07.952823 # # No event generated for I2S1_HD_Mux
7314 00:44:07.956283 # ok 648 write_valid.0.1
7315 00:44:07.959443 # ok 649 write_invalid.0.1
7316 00:44:07.962809 # not ok 650 event_missing.0.1
7317 00:44:07.963206 # ok 651 event_spurious.0.1
7318 00:44:07.966300 # ok 652 get_value.0.0
7319 00:44:07.966688 # ok 653 name.0.0
7320 00:44:07.969405 # ok 654 write_default.0.0
7321 00:44:07.972797 # # No event generated for I2S0_HD_Mux
7322 00:44:07.976181 # # No event generated for I2S0_HD_Mux
7323 00:44:07.979299 # ok 655 write_valid.0.0
7324 00:44:07.982505 # ok 656 write_invalid.0.0
7325 00:44:07.985922 # not ok 657 event_missing.0.0
7326 00:44:07.986381 # ok 658 event_spurious.0.0
7327 00:44:07.992789 # # Totals: pass:568 fail:87 xfail:0 xpass:0 skip:3 error:0
7328 00:44:07.995724 ok 1 selftests: alsa: mixer-test
7329 00:44:09.627531 alsa_mixer-test_get_value_0_93 pass
7330 00:44:09.630798 alsa_mixer-test_name_0_93 pass
7331 00:44:09.634195 alsa_mixer-test_write_default_0_93 pass
7332 00:44:09.637293 alsa_mixer-test_write_valid_0_93 pass
7333 00:44:09.640863 alsa_mixer-test_write_invalid_0_93 pass
7334 00:44:09.647524 alsa_mixer-test_event_missing_0_93 pass
7335 00:44:09.650671 alsa_mixer-test_event_spurious_0_93 pass
7336 00:44:09.653972 alsa_mixer-test_get_value_0_92 pass
7337 00:44:09.657343 alsa_mixer-test_name_0_92 pass
7338 00:44:09.660816 alsa_mixer-test_write_default_0_92 pass
7339 00:44:09.663988 alsa_mixer-test_write_valid_0_92 pass
7340 00:44:09.667350 alsa_mixer-test_write_invalid_0_92 pass
7341 00:44:09.670700 alsa_mixer-test_event_missing_0_92 pass
7342 00:44:09.674157 alsa_mixer-test_event_spurious_0_92 pass
7343 00:44:09.677519 alsa_mixer-test_get_value_0_91 pass
7344 00:44:09.680793 alsa_mixer-test_name_0_91 pass
7345 00:44:09.684099 alsa_mixer-test_write_default_0_91 pass
7346 00:44:09.687605 alsa_mixer-test_write_valid_0_91 pass
7347 00:44:09.690923 alsa_mixer-test_write_invalid_0_91 pass
7348 00:44:09.693848 alsa_mixer-test_event_missing_0_91 pass
7349 00:44:09.697721 alsa_mixer-test_event_spurious_0_91 pass
7350 00:44:09.701036 alsa_mixer-test_get_value_0_90 pass
7351 00:44:09.704518 alsa_mixer-test_name_0_90 pass
7352 00:44:09.707243 alsa_mixer-test_write_default_0_90 pass
7353 00:44:09.710933 alsa_mixer-test_write_valid_0_90 pass
7354 00:44:09.714084 alsa_mixer-test_write_invalid_0_90 pass
7355 00:44:09.717530 alsa_mixer-test_event_missing_0_90 pass
7356 00:44:09.724429 alsa_mixer-test_event_spurious_0_90 pass
7357 00:44:09.727869 alsa_mixer-test_get_value_0_89 pass
7358 00:44:09.730869 alsa_mixer-test_name_0_89 pass
7359 00:44:09.734481 alsa_mixer-test_write_default_0_89 pass
7360 00:44:09.737406 alsa_mixer-test_write_valid_0_89 pass
7361 00:44:09.740648 alsa_mixer-test_write_invalid_0_89 pass
7362 00:44:09.743872 alsa_mixer-test_event_missing_0_89 pass
7363 00:44:09.747419 alsa_mixer-test_event_spurious_0_89 pass
7364 00:44:09.754065 alsa_mixer-test_get_value_0_88 pass
7365 00:44:09.754640 alsa_mixer-test_name_0_88 pass
7366 00:44:09.760922 alsa_mixer-test_write_default_0_88 pass
7367 00:44:09.764124 alsa_mixer-test_write_valid_0_88 fail
7368 00:44:09.767268 alsa_mixer-test_write_invalid_0_88 pass
7369 00:44:09.770551 alsa_mixer-test_event_missing_0_88 pass
7370 00:44:09.774079 alsa_mixer-test_event_spurious_0_88 fail
7371 00:44:09.777374 alsa_mixer-test_get_value_0_87 pass
7372 00:44:09.780990 alsa_mixer-test_name_0_87 pass
7373 00:44:09.783976 alsa_mixer-test_write_default_0_87 pass
7374 00:44:09.787328 alsa_mixer-test_write_valid_0_87 pass
7375 00:44:09.794335 alsa_mixer-test_write_invalid_0_87 pass
7376 00:44:09.797502 alsa_mixer-test_event_missing_0_87 pass
7377 00:44:09.800617 alsa_mixer-test_event_spurious_0_87 pass
7378 00:44:09.803911 alsa_mixer-test_get_value_0_86 pass
7379 00:44:09.807248 alsa_mixer-test_name_0_86 pass
7380 00:44:09.810835 alsa_mixer-test_write_default_0_86 pass
7381 00:44:09.813961 alsa_mixer-test_write_valid_0_86 fail
7382 00:44:09.817203 alsa_mixer-test_write_invalid_0_86 pass
7383 00:44:09.824265 alsa_mixer-test_event_missing_0_86 pass
7384 00:44:09.827110 alsa_mixer-test_event_spurious_0_86 pass
7385 00:44:09.830775 alsa_mixer-test_get_value_0_85 pass
7386 00:44:09.833651 alsa_mixer-test_name_0_85 pass
7387 00:44:09.837095 alsa_mixer-test_write_default_0_85 pass
7388 00:44:09.840707 alsa_mixer-test_write_valid_0_85 fail
7389 00:44:09.844243 alsa_mixer-test_write_invalid_0_85 pass
7390 00:44:09.846956 alsa_mixer-test_event_missing_0_85 pass
7391 00:44:09.854028 alsa_mixer-test_event_spurious_0_85 pass
7392 00:44:09.856978 alsa_mixer-test_get_value_0_84 pass
7393 00:44:09.860491 alsa_mixer-test_name_0_84 pass
7394 00:44:09.863898 alsa_mixer-test_write_default_0_84 pass
7395 00:44:09.866934 alsa_mixer-test_write_valid_0_84 pass
7396 00:44:09.870153 alsa_mixer-test_write_invalid_0_84 pass
7397 00:44:09.873590 alsa_mixer-test_event_missing_0_84 pass
7398 00:44:09.876972 alsa_mixer-test_event_spurious_0_84 pass
7399 00:44:09.880331 alsa_mixer-test_get_value_0_83 pass
7400 00:44:09.883808 alsa_mixer-test_name_0_83 pass
7401 00:44:09.886947 alsa_mixer-test_write_default_0_83 pass
7402 00:44:09.890099 alsa_mixer-test_write_valid_0_83 pass
7403 00:44:09.896917 alsa_mixer-test_write_invalid_0_83 pass
7404 00:44:09.900114 alsa_mixer-test_event_missing_0_83 pass
7405 00:44:09.903654 alsa_mixer-test_event_spurious_0_83 pass
7406 00:44:09.907078 alsa_mixer-test_get_value_0_82 pass
7407 00:44:09.910295 alsa_mixer-test_name_0_82 pass
7408 00:44:09.913513 alsa_mixer-test_write_default_0_82 skip
7409 00:44:09.916903 alsa_mixer-test_write_valid_0_82 skip
7410 00:44:09.920291 alsa_mixer-test_write_invalid_0_82 skip
7411 00:44:09.923549 alsa_mixer-test_event_missing_0_82 pass
7412 00:44:09.927032 alsa_mixer-test_event_spurious_0_82 pass
7413 00:44:09.930301 alsa_mixer-test_get_value_0_81 pass
7414 00:44:09.933582 alsa_mixer-test_name_0_81 pass
7415 00:44:09.936883 alsa_mixer-test_write_default_0_81 pass
7416 00:44:09.940373 alsa_mixer-test_write_valid_0_81 pass
7417 00:44:09.943493 alsa_mixer-test_write_invalid_0_81 fail
7418 00:44:09.947081 alsa_mixer-test_event_missing_0_81 fail
7419 00:44:09.950353 alsa_mixer-test_event_spurious_0_81 pass
7420 00:44:09.953700 alsa_mixer-test_get_value_0_80 pass
7421 00:44:09.956926 alsa_mixer-test_name_0_80 pass
7422 00:44:09.960520 alsa_mixer-test_write_default_0_80 pass
7423 00:44:09.963580 alsa_mixer-test_write_valid_0_80 pass
7424 00:44:09.967079 alsa_mixer-test_write_invalid_0_80 pass
7425 00:44:09.973397 alsa_mixer-test_event_missing_0_80 pass
7426 00:44:09.977018 alsa_mixer-test_event_spurious_0_80 pass
7427 00:44:09.980204 alsa_mixer-test_get_value_0_79 fail
7428 00:44:09.980636 alsa_mixer-test_name_0_79 pass
7429 00:44:09.986720 alsa_mixer-test_write_default_0_79 fail
7430 00:44:09.989819 alsa_mixer-test_write_valid_0_79 fail
7431 00:44:09.993111 alsa_mixer-test_write_invalid_0_79 fail
7432 00:44:09.996477 alsa_mixer-test_event_missing_0_79 pass
7433 00:44:09.999852 alsa_mixer-test_event_spurious_0_79 pass
7434 00:44:10.003590 alsa_mixer-test_get_value_0_78 fail
7435 00:44:10.006648 alsa_mixer-test_name_0_78 pass
7436 00:44:10.009799 alsa_mixer-test_write_default_0_78 fail
7437 00:44:10.013301 alsa_mixer-test_write_valid_0_78 fail
7438 00:44:10.016581 alsa_mixer-test_write_invalid_0_78 fail
7439 00:44:10.019802 alsa_mixer-test_event_missing_0_78 pass
7440 00:44:10.023065 alsa_mixer-test_event_spurious_0_78 pass
7441 00:44:10.026515 alsa_mixer-test_get_value_0_77 fail
7442 00:44:10.029981 alsa_mixer-test_name_0_77 pass
7443 00:44:10.033514 alsa_mixer-test_write_default_0_77 fail
7444 00:44:10.037006 alsa_mixer-test_write_valid_0_77 fail
7445 00:44:10.040065 alsa_mixer-test_write_invalid_0_77 fail
7446 00:44:10.043105 alsa_mixer-test_event_missing_0_77 pass
7447 00:44:10.046691 alsa_mixer-test_event_spurious_0_77 pass
7448 00:44:10.050002 alsa_mixer-test_get_value_0_76 pass
7449 00:44:10.053355 alsa_mixer-test_name_0_76 fail
7450 00:44:10.056929 alsa_mixer-test_write_default_0_76 pass
7451 00:44:10.060114 alsa_mixer-test_write_valid_0_76 pass
7452 00:44:10.063461 alsa_mixer-test_write_invalid_0_76 pass
7453 00:44:10.066626 alsa_mixer-test_event_missing_0_76 pass
7454 00:44:10.069819 alsa_mixer-test_event_spurious_0_76 pass
7455 00:44:10.073255 alsa_mixer-test_get_value_0_75 pass
7456 00:44:10.076541 alsa_mixer-test_name_0_75 fail
7457 00:44:10.079589 alsa_mixer-test_write_default_0_75 pass
7458 00:44:10.083298 alsa_mixer-test_write_valid_0_75 pass
7459 00:44:10.086198 alsa_mixer-test_write_invalid_0_75 pass
7460 00:44:10.089951 alsa_mixer-test_event_missing_0_75 pass
7461 00:44:10.096655 alsa_mixer-test_event_spurious_0_75 pass
7462 00:44:10.099666 alsa_mixer-test_get_value_0_74 pass
7463 00:44:10.100098 alsa_mixer-test_name_0_74 fail
7464 00:44:10.106541 alsa_mixer-test_write_default_0_74 pass
7465 00:44:10.109955 alsa_mixer-test_write_valid_0_74 pass
7466 00:44:10.112880 alsa_mixer-test_write_invalid_0_74 pass
7467 00:44:10.116652 alsa_mixer-test_event_missing_0_74 pass
7468 00:44:10.119378 alsa_mixer-test_event_spurious_0_74 pass
7469 00:44:10.122994 alsa_mixer-test_get_value_0_73 pass
7470 00:44:10.126176 alsa_mixer-test_name_0_73 fail
7471 00:44:10.129222 alsa_mixer-test_write_default_0_73 pass
7472 00:44:10.132451 alsa_mixer-test_write_valid_0_73 pass
7473 00:44:10.135988 alsa_mixer-test_write_invalid_0_73 pass
7474 00:44:10.139238 alsa_mixer-test_event_missing_0_73 pass
7475 00:44:10.142550 alsa_mixer-test_event_spurious_0_73 pass
7476 00:44:10.146085 alsa_mixer-test_get_value_0_72 pass
7477 00:44:10.149460 alsa_mixer-test_name_0_72 fail
7478 00:44:10.152499 alsa_mixer-test_write_default_0_72 pass
7479 00:44:10.156010 alsa_mixer-test_write_valid_0_72 pass
7480 00:44:10.162831 alsa_mixer-test_write_invalid_0_72 pass
7481 00:44:10.166088 alsa_mixer-test_event_missing_0_72 pass
7482 00:44:10.169434 alsa_mixer-test_event_spurious_0_72 pass
7483 00:44:10.172585 alsa_mixer-test_get_value_0_71 pass
7484 00:44:10.175964 alsa_mixer-test_name_0_71 fail
7485 00:44:10.179147 alsa_mixer-test_write_default_0_71 pass
7486 00:44:10.182375 alsa_mixer-test_write_valid_0_71 pass
7487 00:44:10.185892 alsa_mixer-test_write_invalid_0_71 pass
7488 00:44:10.189690 alsa_mixer-test_event_missing_0_71 pass
7489 00:44:10.192240 alsa_mixer-test_event_spurious_0_71 pass
7490 00:44:10.195701 alsa_mixer-test_get_value_0_70 pass
7491 00:44:10.199023 alsa_mixer-test_name_0_70 fail
7492 00:44:10.202399 alsa_mixer-test_write_default_0_70 pass
7493 00:44:10.205602 alsa_mixer-test_write_valid_0_70 pass
7494 00:44:10.208866 alsa_mixer-test_write_invalid_0_70 pass
7495 00:44:10.212198 alsa_mixer-test_event_missing_0_70 pass
7496 00:44:10.219039 alsa_mixer-test_event_spurious_0_70 pass
7497 00:44:10.222647 alsa_mixer-test_get_value_0_69 pass
7498 00:44:10.223151 alsa_mixer-test_name_0_69 fail
7499 00:44:10.229143 alsa_mixer-test_write_default_0_69 pass
7500 00:44:10.232279 alsa_mixer-test_write_valid_0_69 pass
7501 00:44:10.235572 alsa_mixer-test_write_invalid_0_69 pass
7502 00:44:10.238960 alsa_mixer-test_event_missing_0_69 pass
7503 00:44:10.242798 alsa_mixer-test_event_spurious_0_69 pass
7504 00:44:10.245736 alsa_mixer-test_get_value_0_68 pass
7505 00:44:10.248830 alsa_mixer-test_name_0_68 fail
7506 00:44:10.252488 alsa_mixer-test_write_default_0_68 pass
7507 00:44:10.255330 alsa_mixer-test_write_valid_0_68 pass
7508 00:44:10.258528 alsa_mixer-test_write_invalid_0_68 pass
7509 00:44:10.261786 alsa_mixer-test_event_missing_0_68 pass
7510 00:44:10.265463 alsa_mixer-test_event_spurious_0_68 pass
7511 00:44:10.268634 alsa_mixer-test_get_value_0_67 pass
7512 00:44:10.271958 alsa_mixer-test_name_0_67 fail
7513 00:44:10.275435 alsa_mixer-test_write_default_0_67 pass
7514 00:44:10.278562 alsa_mixer-test_write_valid_0_67 pass
7515 00:44:10.285423 alsa_mixer-test_write_invalid_0_67 pass
7516 00:44:10.288730 alsa_mixer-test_event_missing_0_67 pass
7517 00:44:10.291789 alsa_mixer-test_event_spurious_0_67 pass
7518 00:44:10.295069 alsa_mixer-test_get_value_0_66 pass
7519 00:44:10.298476 alsa_mixer-test_name_0_66 fail
7520 00:44:10.301700 alsa_mixer-test_write_default_0_66 pass
7521 00:44:10.305371 alsa_mixer-test_write_valid_0_66 pass
7522 00:44:10.308478 alsa_mixer-test_write_invalid_0_66 pass
7523 00:44:10.312162 alsa_mixer-test_event_missing_0_66 pass
7524 00:44:10.315271 alsa_mixer-test_event_spurious_0_66 pass
7525 00:44:10.318480 alsa_mixer-test_get_value_0_65 pass
7526 00:44:10.321766 alsa_mixer-test_name_0_65 fail
7527 00:44:10.325352 alsa_mixer-test_write_default_0_65 pass
7528 00:44:10.328453 alsa_mixer-test_write_valid_0_65 pass
7529 00:44:10.331591 alsa_mixer-test_write_invalid_0_65 pass
7530 00:44:10.335391 alsa_mixer-test_event_missing_0_65 pass
7531 00:44:10.338691 alsa_mixer-test_event_spurious_0_65 pass
7532 00:44:10.341990 alsa_mixer-test_get_value_0_64 pass
7533 00:44:10.345316 alsa_mixer-test_name_0_64 fail
7534 00:44:10.348414 alsa_mixer-test_write_default_0_64 pass
7535 00:44:10.351744 alsa_mixer-test_write_valid_0_64 pass
7536 00:44:10.355079 alsa_mixer-test_write_invalid_0_64 pass
7537 00:44:10.358279 alsa_mixer-test_event_missing_0_64 pass
7538 00:44:10.364812 alsa_mixer-test_event_spurious_0_64 pass
7539 00:44:10.365319 alsa_mixer-test_get_value_0_63 pass
7540 00:44:10.368122 alsa_mixer-test_name_0_63 fail
7541 00:44:10.371422 alsa_mixer-test_write_default_0_63 pass
7542 00:44:10.374819 alsa_mixer-test_write_valid_0_63 pass
7543 00:44:10.378424 alsa_mixer-test_write_invalid_0_63 pass
7544 00:44:10.384675 alsa_mixer-test_event_missing_0_63 pass
7545 00:44:10.388386 alsa_mixer-test_event_spurious_0_63 pass
7546 00:44:10.391486 alsa_mixer-test_get_value_0_62 pass
7547 00:44:10.391914 alsa_mixer-test_name_0_62 fail
7548 00:44:10.398601 alsa_mixer-test_write_default_0_62 pass
7549 00:44:10.401299 alsa_mixer-test_write_valid_0_62 pass
7550 00:44:10.405087 alsa_mixer-test_write_invalid_0_62 pass
7551 00:44:10.407878 alsa_mixer-test_event_missing_0_62 pass
7552 00:44:10.411530 alsa_mixer-test_event_spurious_0_62 pass
7553 00:44:10.415012 alsa_mixer-test_get_value_0_61 pass
7554 00:44:10.417916 alsa_mixer-test_name_0_61 fail
7555 00:44:10.421431 alsa_mixer-test_write_default_0_61 pass
7556 00:44:10.424791 alsa_mixer-test_write_valid_0_61 pass
7557 00:44:10.427774 alsa_mixer-test_write_invalid_0_61 pass
7558 00:44:10.431242 alsa_mixer-test_event_missing_0_61 pass
7559 00:44:10.438038 alsa_mixer-test_event_spurious_0_61 pass
7560 00:44:10.441392 alsa_mixer-test_get_value_0_60 pass
7561 00:44:10.441897 alsa_mixer-test_name_0_60 fail
7562 00:44:10.447850 alsa_mixer-test_write_default_0_60 pass
7563 00:44:10.451467 alsa_mixer-test_write_valid_0_60 pass
7564 00:44:10.454666 alsa_mixer-test_write_invalid_0_60 pass
7565 00:44:10.458244 alsa_mixer-test_event_missing_0_60 pass
7566 00:44:10.461697 alsa_mixer-test_event_spurious_0_60 pass
7567 00:44:10.464526 alsa_mixer-test_get_value_0_59 pass
7568 00:44:10.467885 alsa_mixer-test_name_0_59 fail
7569 00:44:10.471323 alsa_mixer-test_write_default_0_59 pass
7570 00:44:10.478035 alsa_mixer-test_write_valid_0_59 pass
7571 00:44:10.481430 alsa_mixer-test_write_invalid_0_59 pass
7572 00:44:10.484641 alsa_mixer-test_event_missing_0_59 pass
7573 00:44:10.487744 alsa_mixer-test_event_spurious_0_59 pass
7574 00:44:10.491170 alsa_mixer-test_get_value_0_58 pass
7575 00:44:10.494419 alsa_mixer-test_name_0_58 fail
7576 00:44:10.498092 alsa_mixer-test_write_default_0_58 pass
7577 00:44:10.501309 alsa_mixer-test_write_valid_0_58 pass
7578 00:44:10.507783 alsa_mixer-test_write_invalid_0_58 pass
7579 00:44:10.511598 alsa_mixer-test_event_missing_0_58 pass
7580 00:44:10.514837 alsa_mixer-test_event_spurious_0_58 pass
7581 00:44:10.518323 alsa_mixer-test_get_value_0_57 pass
7582 00:44:10.521307 alsa_mixer-test_name_0_57 fail
7583 00:44:10.524221 alsa_mixer-test_write_default_0_57 pass
7584 00:44:10.527867 alsa_mixer-test_write_valid_0_57 pass
7585 00:44:10.531439 alsa_mixer-test_write_invalid_0_57 pass
7586 00:44:10.537919 alsa_mixer-test_event_missing_0_57 pass
7587 00:44:10.541039 alsa_mixer-test_event_spurious_0_57 pass
7588 00:44:10.544659 alsa_mixer-test_get_value_0_56 pass
7589 00:44:10.547810 alsa_mixer-test_name_0_56 fail
7590 00:44:10.551206 alsa_mixer-test_write_default_0_56 pass
7591 00:44:10.554491 alsa_mixer-test_write_valid_0_56 pass
7592 00:44:10.557668 alsa_mixer-test_write_invalid_0_56 pass
7593 00:44:10.561164 alsa_mixer-test_event_missing_0_56 pass
7594 00:44:10.567540 alsa_mixer-test_event_spurious_0_56 pass
7595 00:44:10.571113 alsa_mixer-test_get_value_0_55 pass
7596 00:44:10.574807 alsa_mixer-test_name_0_55 fail
7597 00:44:10.577950 alsa_mixer-test_write_default_0_55 pass
7598 00:44:10.581456 alsa_mixer-test_write_valid_0_55 pass
7599 00:44:10.584370 alsa_mixer-test_write_invalid_0_55 pass
7600 00:44:10.587645 alsa_mixer-test_event_missing_0_55 pass
7601 00:44:10.591069 alsa_mixer-test_event_spurious_0_55 pass
7602 00:44:10.594511 alsa_mixer-test_get_value_0_54 pass
7603 00:44:10.597721 alsa_mixer-test_name_0_54 fail
7604 00:44:10.601273 alsa_mixer-test_write_default_0_54 pass
7605 00:44:10.607616 alsa_mixer-test_write_valid_0_54 pass
7606 00:44:10.610896 alsa_mixer-test_write_invalid_0_54 pass
7607 00:44:10.614162 alsa_mixer-test_event_missing_0_54 pass
7608 00:44:10.618113 alsa_mixer-test_event_spurious_0_54 pass
7609 00:44:10.621114 alsa_mixer-test_get_value_0_53 pass
7610 00:44:10.624518 alsa_mixer-test_name_0_53 fail
7611 00:44:10.627830 alsa_mixer-test_write_default_0_53 pass
7612 00:44:10.630796 alsa_mixer-test_write_valid_0_53 pass
7613 00:44:10.637871 alsa_mixer-test_write_invalid_0_53 pass
7614 00:44:10.640827 alsa_mixer-test_event_missing_0_53 pass
7615 00:44:10.644193 alsa_mixer-test_event_spurious_0_53 pass
7616 00:44:10.647477 alsa_mixer-test_get_value_0_52 pass
7617 00:44:10.650721 alsa_mixer-test_name_0_52 fail
7618 00:44:10.654016 alsa_mixer-test_write_default_0_52 pass
7619 00:44:10.657529 alsa_mixer-test_write_valid_0_52 pass
7620 00:44:10.664096 alsa_mixer-test_write_invalid_0_52 pass
7621 00:44:10.667130 alsa_mixer-test_event_missing_0_52 pass
7622 00:44:10.670666 alsa_mixer-test_event_spurious_0_52 pass
7623 00:44:10.674105 alsa_mixer-test_get_value_0_51 pass
7624 00:44:10.677229 alsa_mixer-test_name_0_51 fail
7625 00:44:10.681070 alsa_mixer-test_write_default_0_51 pass
7626 00:44:10.684138 alsa_mixer-test_write_valid_0_51 pass
7627 00:44:10.687525 alsa_mixer-test_write_invalid_0_51 pass
7628 00:44:10.690635 alsa_mixer-test_event_missing_0_51 pass
7629 00:44:10.694292 alsa_mixer-test_event_spurious_0_51 pass
7630 00:44:10.697467 alsa_mixer-test_get_value_0_50 pass
7631 00:44:10.700917 alsa_mixer-test_name_0_50 fail
7632 00:44:10.703814 alsa_mixer-test_write_default_0_50 pass
7633 00:44:10.707027 alsa_mixer-test_write_valid_0_50 pass
7634 00:44:10.710503 alsa_mixer-test_write_invalid_0_50 pass
7635 00:44:10.714044 alsa_mixer-test_event_missing_0_50 pass
7636 00:44:10.717235 alsa_mixer-test_event_spurious_0_50 pass
7637 00:44:10.720276 alsa_mixer-test_get_value_0_49 pass
7638 00:44:10.723926 alsa_mixer-test_name_0_49 fail
7639 00:44:10.727043 alsa_mixer-test_write_default_0_49 pass
7640 00:44:10.730200 alsa_mixer-test_write_valid_0_49 pass
7641 00:44:10.733731 alsa_mixer-test_write_invalid_0_49 pass
7642 00:44:10.737295 alsa_mixer-test_event_missing_0_49 pass
7643 00:44:10.740364 alsa_mixer-test_event_spurious_0_49 pass
7644 00:44:10.744021 alsa_mixer-test_get_value_0_48 pass
7645 00:44:10.747143 alsa_mixer-test_name_0_48 fail
7646 00:44:10.750538 alsa_mixer-test_write_default_0_48 pass
7647 00:44:10.753752 alsa_mixer-test_write_valid_0_48 pass
7648 00:44:10.757209 alsa_mixer-test_write_invalid_0_48 pass
7649 00:44:10.760529 alsa_mixer-test_event_missing_0_48 pass
7650 00:44:10.763975 alsa_mixer-test_event_spurious_0_48 pass
7651 00:44:10.767193 alsa_mixer-test_get_value_0_47 pass
7652 00:44:10.770249 alsa_mixer-test_name_0_47 fail
7653 00:44:10.773408 alsa_mixer-test_write_default_0_47 pass
7654 00:44:10.776817 alsa_mixer-test_write_valid_0_47 pass
7655 00:44:10.780466 alsa_mixer-test_write_invalid_0_47 pass
7656 00:44:10.786698 alsa_mixer-test_event_missing_0_47 pass
7657 00:44:10.790182 alsa_mixer-test_event_spurious_0_47 pass
7658 00:44:10.793579 alsa_mixer-test_get_value_0_46 pass
7659 00:44:10.794096 alsa_mixer-test_name_0_46 fail
7660 00:44:10.796801 alsa_mixer-test_write_default_0_46 pass
7661 00:44:10.800562 alsa_mixer-test_write_valid_0_46 pass
7662 00:44:10.807010 alsa_mixer-test_write_invalid_0_46 pass
7663 00:44:10.810271 alsa_mixer-test_event_missing_0_46 pass
7664 00:44:10.813687 alsa_mixer-test_event_spurious_0_46 pass
7665 00:44:10.816893 alsa_mixer-test_get_value_0_45 pass
7666 00:44:10.820047 alsa_mixer-test_name_0_45 fail
7667 00:44:10.823168 alsa_mixer-test_write_default_0_45 pass
7668 00:44:10.826857 alsa_mixer-test_write_valid_0_45 pass
7669 00:44:10.829950 alsa_mixer-test_write_invalid_0_45 pass
7670 00:44:10.833256 alsa_mixer-test_event_missing_0_45 pass
7671 00:44:10.836621 alsa_mixer-test_event_spurious_0_45 pass
7672 00:44:10.839941 alsa_mixer-test_get_value_0_44 pass
7673 00:44:10.843369 alsa_mixer-test_name_0_44 fail
7674 00:44:10.846865 alsa_mixer-test_write_default_0_44 pass
7675 00:44:10.849861 alsa_mixer-test_write_valid_0_44 pass
7676 00:44:10.853222 alsa_mixer-test_write_invalid_0_44 pass
7677 00:44:10.856545 alsa_mixer-test_event_missing_0_44 pass
7678 00:44:10.859973 alsa_mixer-test_event_spurious_0_44 pass
7679 00:44:10.863641 alsa_mixer-test_get_value_0_43 pass
7680 00:44:10.866488 alsa_mixer-test_name_0_43 fail
7681 00:44:10.869838 alsa_mixer-test_write_default_0_43 pass
7682 00:44:10.872916 alsa_mixer-test_write_valid_0_43 pass
7683 00:44:10.876456 alsa_mixer-test_write_invalid_0_43 pass
7684 00:44:10.880011 alsa_mixer-test_event_missing_0_43 pass
7685 00:44:10.882856 alsa_mixer-test_event_spurious_0_43 pass
7686 00:44:10.886288 alsa_mixer-test_get_value_0_42 pass
7687 00:44:10.889754 alsa_mixer-test_name_0_42 fail
7688 00:44:10.893151 alsa_mixer-test_write_default_0_42 pass
7689 00:44:10.896445 alsa_mixer-test_write_valid_0_42 pass
7690 00:44:10.899605 alsa_mixer-test_write_invalid_0_42 pass
7691 00:44:10.902839 alsa_mixer-test_event_missing_0_42 pass
7692 00:44:10.909868 alsa_mixer-test_event_spurious_0_42 pass
7693 00:44:10.913001 alsa_mixer-test_get_value_0_41 pass
7694 00:44:10.913510 alsa_mixer-test_name_0_41 fail
7695 00:44:10.919760 alsa_mixer-test_write_default_0_41 pass
7696 00:44:10.923305 alsa_mixer-test_write_valid_0_41 pass
7697 00:44:10.926367 alsa_mixer-test_write_invalid_0_41 pass
7698 00:44:10.929327 alsa_mixer-test_event_missing_0_41 pass
7699 00:44:10.932694 alsa_mixer-test_event_spurious_0_41 pass
7700 00:44:10.936194 alsa_mixer-test_get_value_0_40 pass
7701 00:44:10.939253 alsa_mixer-test_name_0_40 fail
7702 00:44:10.942810 alsa_mixer-test_write_default_0_40 pass
7703 00:44:10.945952 alsa_mixer-test_write_valid_0_40 pass
7704 00:44:10.949598 alsa_mixer-test_write_invalid_0_40 pass
7705 00:44:10.953004 alsa_mixer-test_event_missing_0_40 pass
7706 00:44:10.956201 alsa_mixer-test_event_spurious_0_40 pass
7707 00:44:10.959462 alsa_mixer-test_get_value_0_39 pass
7708 00:44:10.962858 alsa_mixer-test_name_0_39 fail
7709 00:44:10.965878 alsa_mixer-test_write_default_0_39 pass
7710 00:44:10.969589 alsa_mixer-test_write_valid_0_39 pass
7711 00:44:10.973013 alsa_mixer-test_write_invalid_0_39 pass
7712 00:44:10.976002 alsa_mixer-test_event_missing_0_39 pass
7713 00:44:10.982821 alsa_mixer-test_event_spurious_0_39 pass
7714 00:44:10.985858 alsa_mixer-test_get_value_0_38 pass
7715 00:44:10.986326 alsa_mixer-test_name_0_38 fail
7716 00:44:10.989239 alsa_mixer-test_write_default_0_38 pass
7717 00:44:10.992589 alsa_mixer-test_write_valid_0_38 pass
7718 00:44:10.996008 alsa_mixer-test_write_invalid_0_38 pass
7719 00:44:11.002675 alsa_mixer-test_event_missing_0_38 pass
7720 00:44:11.005669 alsa_mixer-test_event_spurious_0_38 pass
7721 00:44:11.009047 alsa_mixer-test_get_value_0_37 pass
7722 00:44:11.012679 alsa_mixer-test_name_0_37 fail
7723 00:44:11.015989 alsa_mixer-test_write_default_0_37 pass
7724 00:44:11.019178 alsa_mixer-test_write_valid_0_37 pass
7725 00:44:11.022652 alsa_mixer-test_write_invalid_0_37 pass
7726 00:44:11.025919 alsa_mixer-test_event_missing_0_37 pass
7727 00:44:11.029192 alsa_mixer-test_event_spurious_0_37 pass
7728 00:44:11.032364 alsa_mixer-test_get_value_0_36 pass
7729 00:44:11.035625 alsa_mixer-test_name_0_36 fail
7730 00:44:11.038972 alsa_mixer-test_write_default_0_36 pass
7731 00:44:11.042265 alsa_mixer-test_write_valid_0_36 pass
7732 00:44:11.045513 alsa_mixer-test_write_invalid_0_36 pass
7733 00:44:11.048734 alsa_mixer-test_event_missing_0_36 pass
7734 00:44:11.052103 alsa_mixer-test_event_spurious_0_36 pass
7735 00:44:11.055598 alsa_mixer-test_get_value_0_35 pass
7736 00:44:11.058608 alsa_mixer-test_name_0_35 fail
7737 00:44:11.061916 alsa_mixer-test_write_default_0_35 pass
7738 00:44:11.068597 alsa_mixer-test_write_valid_0_35 pass
7739 00:44:11.071853 alsa_mixer-test_write_invalid_0_35 pass
7740 00:44:11.075076 alsa_mixer-test_event_missing_0_35 pass
7741 00:44:11.078516 alsa_mixer-test_event_spurious_0_35 pass
7742 00:44:11.081587 alsa_mixer-test_get_value_0_34 pass
7743 00:44:11.084947 alsa_mixer-test_name_0_34 fail
7744 00:44:11.088326 alsa_mixer-test_write_default_0_34 pass
7745 00:44:11.092063 alsa_mixer-test_write_valid_0_34 pass
7746 00:44:11.095072 alsa_mixer-test_write_invalid_0_34 pass
7747 00:44:11.098409 alsa_mixer-test_event_missing_0_34 pass
7748 00:44:11.101710 alsa_mixer-test_event_spurious_0_34 pass
7749 00:44:11.104917 alsa_mixer-test_get_value_0_33 pass
7750 00:44:11.108317 alsa_mixer-test_name_0_33 fail
7751 00:44:11.111784 alsa_mixer-test_write_default_0_33 pass
7752 00:44:11.115011 alsa_mixer-test_write_valid_0_33 pass
7753 00:44:11.118249 alsa_mixer-test_write_invalid_0_33 pass
7754 00:44:11.125126 alsa_mixer-test_event_missing_0_33 pass
7755 00:44:11.128415 alsa_mixer-test_event_spurious_0_33 pass
7756 00:44:11.131989 alsa_mixer-test_get_value_0_32 pass
7757 00:44:11.134850 alsa_mixer-test_name_0_32 fail
7758 00:44:11.138660 alsa_mixer-test_write_default_0_32 pass
7759 00:44:11.141811 alsa_mixer-test_write_valid_0_32 pass
7760 00:44:11.144792 alsa_mixer-test_write_invalid_0_32 pass
7761 00:44:11.148156 alsa_mixer-test_event_missing_0_32 pass
7762 00:44:11.151724 alsa_mixer-test_event_spurious_0_32 pass
7763 00:44:11.155150 alsa_mixer-test_get_value_0_31 pass
7764 00:44:11.158280 alsa_mixer-test_name_0_31 fail
7765 00:44:11.161417 alsa_mixer-test_write_default_0_31 pass
7766 00:44:11.164646 alsa_mixer-test_write_valid_0_31 pass
7767 00:44:11.168324 alsa_mixer-test_write_invalid_0_31 pass
7768 00:44:11.171634 alsa_mixer-test_event_missing_0_31 pass
7769 00:44:11.175101 alsa_mixer-test_event_spurious_0_31 pass
7770 00:44:11.178446 alsa_mixer-test_get_value_0_30 pass
7771 00:44:11.181761 alsa_mixer-test_name_0_30 fail
7772 00:44:11.185175 alsa_mixer-test_write_default_0_30 pass
7773 00:44:11.188832 alsa_mixer-test_write_valid_0_30 pass
7774 00:44:11.195050 alsa_mixer-test_write_invalid_0_30 pass
7775 00:44:11.198332 alsa_mixer-test_event_missing_0_30 pass
7776 00:44:11.202010 alsa_mixer-test_event_spurious_0_30 pass
7777 00:44:11.205209 alsa_mixer-test_get_value_0_29 pass
7778 00:44:11.208593 alsa_mixer-test_name_0_29 pass
7779 00:44:11.212206 alsa_mixer-test_write_default_0_29 pass
7780 00:44:11.215133 alsa_mixer-test_write_valid_0_29 pass
7781 00:44:11.218257 alsa_mixer-test_write_invalid_0_29 pass
7782 00:44:11.221524 alsa_mixer-test_event_missing_0_29 pass
7783 00:44:11.225313 alsa_mixer-test_event_spurious_0_29 pass
7784 00:44:11.228363 alsa_mixer-test_get_value_0_28 pass
7785 00:44:11.232116 alsa_mixer-test_name_0_28 pass
7786 00:44:11.235417 alsa_mixer-test_write_default_0_28 pass
7787 00:44:11.238494 alsa_mixer-test_write_valid_0_28 pass
7788 00:44:11.241945 alsa_mixer-test_write_invalid_0_28 pass
7789 00:44:11.244978 alsa_mixer-test_event_missing_0_28 pass
7790 00:44:11.251925 alsa_mixer-test_event_spurious_0_28 pass
7791 00:44:11.255016 alsa_mixer-test_get_value_0_27 pass
7792 00:44:11.255449 alsa_mixer-test_name_0_27 pass
7793 00:44:11.261934 alsa_mixer-test_write_default_0_27 pass
7794 00:44:11.265457 alsa_mixer-test_write_valid_0_27 pass
7795 00:44:11.268537 alsa_mixer-test_write_invalid_0_27 pass
7796 00:44:11.271562 alsa_mixer-test_event_missing_0_27 pass
7797 00:44:11.275350 alsa_mixer-test_event_spurious_0_27 pass
7798 00:44:11.278340 alsa_mixer-test_get_value_0_26 pass
7799 00:44:11.281847 alsa_mixer-test_name_0_26 pass
7800 00:44:11.285077 alsa_mixer-test_write_default_0_26 pass
7801 00:44:11.288259 alsa_mixer-test_write_valid_0_26 pass
7802 00:44:11.291413 alsa_mixer-test_write_invalid_0_26 pass
7803 00:44:11.294813 alsa_mixer-test_event_missing_0_26 pass
7804 00:44:11.297963 alsa_mixer-test_event_spurious_0_26 pass
7805 00:44:11.301889 alsa_mixer-test_get_value_0_25 pass
7806 00:44:11.305138 alsa_mixer-test_name_0_25 pass
7807 00:44:11.308254 alsa_mixer-test_write_default_0_25 pass
7808 00:44:11.311470 alsa_mixer-test_write_valid_0_25 pass
7809 00:44:11.318438 alsa_mixer-test_write_invalid_0_25 pass
7810 00:44:11.321334 alsa_mixer-test_event_missing_0_25 pass
7811 00:44:11.324685 alsa_mixer-test_event_spurious_0_25 pass
7812 00:44:11.328125 alsa_mixer-test_get_value_0_24 pass
7813 00:44:11.331565 alsa_mixer-test_name_0_24 pass
7814 00:44:11.335036 alsa_mixer-test_write_default_0_24 pass
7815 00:44:11.338439 alsa_mixer-test_write_valid_0_24 pass
7816 00:44:11.341597 alsa_mixer-test_write_invalid_0_24 pass
7817 00:44:11.345137 alsa_mixer-test_event_missing_0_24 pass
7818 00:44:11.348307 alsa_mixer-test_event_spurious_0_24 pass
7819 00:44:11.351606 alsa_mixer-test_get_value_0_23 pass
7820 00:44:11.354748 alsa_mixer-test_name_0_23 pass
7821 00:44:11.358402 alsa_mixer-test_write_default_0_23 pass
7822 00:44:11.361737 alsa_mixer-test_write_valid_0_23 pass
7823 00:44:11.364685 alsa_mixer-test_write_invalid_0_23 pass
7824 00:44:11.368273 alsa_mixer-test_event_missing_0_23 pass
7825 00:44:11.374967 alsa_mixer-test_event_spurious_0_23 pass
7826 00:44:11.378487 alsa_mixer-test_get_value_0_22 pass
7827 00:44:11.379004 alsa_mixer-test_name_0_22 pass
7828 00:44:11.384732 alsa_mixer-test_write_default_0_22 pass
7829 00:44:11.388106 alsa_mixer-test_write_valid_0_22 pass
7830 00:44:11.391469 alsa_mixer-test_write_invalid_0_22 pass
7831 00:44:11.394496 alsa_mixer-test_event_missing_0_22 pass
7832 00:44:11.397770 alsa_mixer-test_event_spurious_0_22 pass
7833 00:44:11.401157 alsa_mixer-test_get_value_0_21 pass
7834 00:44:11.404711 alsa_mixer-test_name_0_21 fail
7835 00:44:11.407804 alsa_mixer-test_write_default_0_21 pass
7836 00:44:11.410928 alsa_mixer-test_write_valid_0_21 pass
7837 00:44:11.414691 alsa_mixer-test_write_invalid_0_21 pass
7838 00:44:11.417929 alsa_mixer-test_event_missing_0_21 pass
7839 00:44:11.421432 alsa_mixer-test_event_spurious_0_21 pass
7840 00:44:11.424532 alsa_mixer-test_get_value_0_20 pass
7841 00:44:11.427788 alsa_mixer-test_name_0_20 fail
7842 00:44:11.431235 alsa_mixer-test_write_default_0_20 pass
7843 00:44:11.434817 alsa_mixer-test_write_valid_0_20 pass
7844 00:44:11.438006 alsa_mixer-test_write_invalid_0_20 pass
7845 00:44:11.444708 alsa_mixer-test_event_missing_0_20 pass
7846 00:44:11.447980 alsa_mixer-test_event_spurious_0_20 pass
7847 00:44:11.450944 alsa_mixer-test_get_value_0_19 pass
7848 00:44:11.454789 alsa_mixer-test_name_0_19 fail
7849 00:44:11.458163 alsa_mixer-test_write_default_0_19 pass
7850 00:44:11.460931 alsa_mixer-test_write_valid_0_19 pass
7851 00:44:11.464094 alsa_mixer-test_write_invalid_0_19 pass
7852 00:44:11.467920 alsa_mixer-test_event_missing_0_19 pass
7853 00:44:11.470931 alsa_mixer-test_event_spurious_0_19 pass
7854 00:44:11.474495 alsa_mixer-test_get_value_0_18 pass
7855 00:44:11.477664 alsa_mixer-test_name_0_18 fail
7856 00:44:11.481070 alsa_mixer-test_write_default_0_18 pass
7857 00:44:11.484443 alsa_mixer-test_write_valid_0_18 pass
7858 00:44:11.487563 alsa_mixer-test_write_invalid_0_18 pass
7859 00:44:11.490820 alsa_mixer-test_event_missing_0_18 pass
7860 00:44:11.494742 alsa_mixer-test_event_spurious_0_18 pass
7861 00:44:11.497760 alsa_mixer-test_get_value_0_17 pass
7862 00:44:11.501221 alsa_mixer-test_name_0_17 fail
7863 00:44:11.504574 alsa_mixer-test_write_default_0_17 pass
7864 00:44:11.511056 alsa_mixer-test_write_valid_0_17 pass
7865 00:44:11.514707 alsa_mixer-test_write_invalid_0_17 pass
7866 00:44:11.517575 alsa_mixer-test_event_missing_0_17 pass
7867 00:44:11.521275 alsa_mixer-test_event_spurious_0_17 pass
7868 00:44:11.524515 alsa_mixer-test_get_value_0_16 pass
7869 00:44:11.527412 alsa_mixer-test_name_0_16 fail
7870 00:44:11.530729 alsa_mixer-test_write_default_0_16 pass
7871 00:44:11.534345 alsa_mixer-test_write_valid_0_16 pass
7872 00:44:11.537394 alsa_mixer-test_write_invalid_0_16 pass
7873 00:44:11.540687 alsa_mixer-test_event_missing_0_16 pass
7874 00:44:11.544367 alsa_mixer-test_event_spurious_0_16 pass
7875 00:44:11.547239 alsa_mixer-test_get_value_0_15 pass
7876 00:44:11.550934 alsa_mixer-test_name_0_15 fail
7877 00:44:11.554337 alsa_mixer-test_write_default_0_15 pass
7878 00:44:11.557653 alsa_mixer-test_write_valid_0_15 pass
7879 00:44:11.560953 alsa_mixer-test_write_invalid_0_15 pass
7880 00:44:11.567612 alsa_mixer-test_event_missing_0_15 pass
7881 00:44:11.570683 alsa_mixer-test_event_spurious_0_15 pass
7882 00:44:11.574138 alsa_mixer-test_get_value_0_14 pass
7883 00:44:11.577200 alsa_mixer-test_name_0_14 fail
7884 00:44:11.580604 alsa_mixer-test_write_default_0_14 pass
7885 00:44:11.584141 alsa_mixer-test_write_valid_0_14 pass
7886 00:44:11.587019 alsa_mixer-test_write_invalid_0_14 pass
7887 00:44:11.590686 alsa_mixer-test_event_missing_0_14 pass
7888 00:44:11.593842 alsa_mixer-test_event_spurious_0_14 pass
7889 00:44:11.597647 alsa_mixer-test_get_value_0_13 pass
7890 00:44:11.600693 alsa_mixer-test_name_0_13 fail
7891 00:44:11.603621 alsa_mixer-test_write_default_0_13 pass
7892 00:44:11.606888 alsa_mixer-test_write_valid_0_13 pass
7893 00:44:11.610457 alsa_mixer-test_write_invalid_0_13 pass
7894 00:44:11.613949 alsa_mixer-test_event_missing_0_13 pass
7895 00:44:11.617484 alsa_mixer-test_event_spurious_0_13 pass
7896 00:44:11.620545 alsa_mixer-test_get_value_0_12 pass
7897 00:44:11.623797 alsa_mixer-test_name_0_12 fail
7898 00:44:11.626915 alsa_mixer-test_write_default_0_12 pass
7899 00:44:11.633834 alsa_mixer-test_write_valid_0_12 pass
7900 00:44:11.636730 alsa_mixer-test_write_invalid_0_12 pass
7901 00:44:11.640569 alsa_mixer-test_event_missing_0_12 pass
7902 00:44:11.643688 alsa_mixer-test_event_spurious_0_12 pass
7903 00:44:11.646760 alsa_mixer-test_get_value_0_11 pass
7904 00:44:11.650108 alsa_mixer-test_name_0_11 fail
7905 00:44:11.653779 alsa_mixer-test_write_default_0_11 pass
7906 00:44:11.656936 alsa_mixer-test_write_valid_0_11 pass
7907 00:44:11.660427 alsa_mixer-test_write_invalid_0_11 pass
7908 00:44:11.663265 alsa_mixer-test_event_missing_0_11 pass
7909 00:44:11.666697 alsa_mixer-test_event_spurious_0_11 pass
7910 00:44:11.670131 alsa_mixer-test_get_value_0_10 pass
7911 00:44:11.673199 alsa_mixer-test_name_0_10 fail
7912 00:44:11.676435 alsa_mixer-test_write_default_0_10 pass
7913 00:44:11.679751 alsa_mixer-test_write_valid_0_10 pass
7914 00:44:11.683375 alsa_mixer-test_write_invalid_0_10 pass
7915 00:44:11.686634 alsa_mixer-test_event_missing_0_10 pass
7916 00:44:11.693271 alsa_mixer-test_event_spurious_0_10 pass
7917 00:44:11.693787 alsa_mixer-test_get_value_0_9 pass
7918 00:44:11.696884 alsa_mixer-test_name_0_9 fail
7919 00:44:11.700049 alsa_mixer-test_write_default_0_9 pass
7920 00:44:11.703437 alsa_mixer-test_write_valid_0_9 pass
7921 00:44:11.706678 alsa_mixer-test_write_invalid_0_9 pass
7922 00:44:11.710070 alsa_mixer-test_event_missing_0_9 pass
7923 00:44:11.713494 alsa_mixer-test_event_spurious_0_9 pass
7924 00:44:11.716537 alsa_mixer-test_get_value_0_8 pass
7925 00:44:11.720079 alsa_mixer-test_name_0_8 fail
7926 00:44:11.723205 alsa_mixer-test_write_default_0_8 pass
7927 00:44:11.726332 alsa_mixer-test_write_valid_0_8 pass
7928 00:44:11.729569 alsa_mixer-test_write_invalid_0_8 pass
7929 00:44:11.733357 alsa_mixer-test_event_missing_0_8 pass
7930 00:44:11.736615 alsa_mixer-test_event_spurious_0_8 pass
7931 00:44:11.739717 alsa_mixer-test_get_value_0_7 pass
7932 00:44:11.743363 alsa_mixer-test_name_0_7 fail
7933 00:44:11.746485 alsa_mixer-test_write_default_0_7 pass
7934 00:44:11.749759 alsa_mixer-test_write_valid_0_7 pass
7935 00:44:11.753114 alsa_mixer-test_write_invalid_0_7 pass
7936 00:44:11.759598 alsa_mixer-test_event_missing_0_7 pass
7937 00:44:11.763007 alsa_mixer-test_event_spurious_0_7 pass
7938 00:44:11.766776 alsa_mixer-test_get_value_0_6 pass
7939 00:44:11.767239 alsa_mixer-test_name_0_6 fail
7940 00:44:11.769544 alsa_mixer-test_write_default_0_6 pass
7941 00:44:11.772916 alsa_mixer-test_write_valid_0_6 pass
7942 00:44:11.779465 alsa_mixer-test_write_invalid_0_6 pass
7943 00:44:11.782905 alsa_mixer-test_event_missing_0_6 pass
7944 00:44:11.786127 alsa_mixer-test_event_spurious_0_6 pass
7945 00:44:11.789400 alsa_mixer-test_get_value_0_5 pass
7946 00:44:11.789920 alsa_mixer-test_name_0_5 pass
7947 00:44:11.792636 alsa_mixer-test_write_default_0_5 pass
7948 00:44:11.796023 alsa_mixer-test_write_valid_0_5 pass
7949 00:44:11.802881 alsa_mixer-test_write_invalid_0_5 pass
7950 00:44:11.806044 alsa_mixer-test_event_missing_0_5 fail
7951 00:44:11.809275 alsa_mixer-test_event_spurious_0_5 pass
7952 00:44:11.812650 alsa_mixer-test_get_value_0_4 pass
7953 00:44:11.813070 alsa_mixer-test_name_0_4 pass
7954 00:44:11.816140 alsa_mixer-test_write_default_0_4 pass
7955 00:44:11.819220 alsa_mixer-test_write_valid_0_4 pass
7956 00:44:11.826100 alsa_mixer-test_write_invalid_0_4 pass
7957 00:44:11.829344 alsa_mixer-test_event_missing_0_4 fail
7958 00:44:11.832518 alsa_mixer-test_event_spurious_0_4 pass
7959 00:44:11.835732 alsa_mixer-test_get_value_0_3 pass
7960 00:44:11.836154 alsa_mixer-test_name_0_3 pass
7961 00:44:11.839262 alsa_mixer-test_write_default_0_3 pass
7962 00:44:11.842687 alsa_mixer-test_write_valid_0_3 pass
7963 00:44:11.849304 alsa_mixer-test_write_invalid_0_3 pass
7964 00:44:11.852616 alsa_mixer-test_event_missing_0_3 fail
7965 00:44:11.855599 alsa_mixer-test_event_spurious_0_3 pass
7966 00:44:11.859060 alsa_mixer-test_get_value_0_2 pass
7967 00:44:11.859476 alsa_mixer-test_name_0_2 pass
7968 00:44:11.862574 alsa_mixer-test_write_default_0_2 pass
7969 00:44:11.869158 alsa_mixer-test_write_valid_0_2 pass
7970 00:44:11.872514 alsa_mixer-test_write_invalid_0_2 pass
7971 00:44:11.875656 alsa_mixer-test_event_missing_0_2 fail
7972 00:44:11.879099 alsa_mixer-test_event_spurious_0_2 pass
7973 00:44:11.882281 alsa_mixer-test_get_value_0_1 pass
7974 00:44:11.882673 alsa_mixer-test_name_0_1 pass
7975 00:44:11.885949 alsa_mixer-test_write_default_0_1 pass
7976 00:44:11.889158 alsa_mixer-test_write_valid_0_1 pass
7977 00:44:11.895686 alsa_mixer-test_write_invalid_0_1 pass
7978 00:44:11.898989 alsa_mixer-test_event_missing_0_1 fail
7979 00:44:11.902240 alsa_mixer-test_event_spurious_0_1 pass
7980 00:44:11.905584 alsa_mixer-test_get_value_0_0 pass
7981 00:44:11.906006 alsa_mixer-test_name_0_0 pass
7982 00:44:11.909010 alsa_mixer-test_write_default_0_0 pass
7983 00:44:11.915388 alsa_mixer-test_write_valid_0_0 pass
7984 00:44:11.918848 alsa_mixer-test_write_invalid_0_0 pass
7985 00:44:11.922181 alsa_mixer-test_event_missing_0_0 fail
7986 00:44:11.925496 alsa_mixer-test_event_spurious_0_0 pass
7987 00:44:11.925888 alsa_mixer-test pass
7988 00:44:11.932049 + ../../utils/send-to-lava.sh ./output/result.txt
7989 00:44:11.935590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-alsa RESULT=pass>
7990 00:44:11.936346 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-alsa RESULT=pass
7992 00:44:11.942251 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_93 RESULT=pass
7994 00:44:11.945430 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_93 RESULT=pass>
7995 00:44:11.949015 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_93 RESULT=pass
7997 00:44:11.951879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_93 RESULT=pass>
7998 00:44:11.970583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_93 RESULT=pass>
7999 00:44:11.971401 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_93 RESULT=pass
8001 00:44:12.027719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_93 RESULT=pass>
8002 00:44:12.028381 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_93 RESULT=pass
8004 00:44:12.084246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_93 RESULT=pass>
8005 00:44:12.085127 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_93 RESULT=pass
8007 00:44:12.144655 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_93 RESULT=pass>
8008 00:44:12.145003 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_93 RESULT=pass
8010 00:44:12.192017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_93 RESULT=pass>
8011 00:44:12.192316 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_93 RESULT=pass
8013 00:44:12.246493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_92 RESULT=pass>
8014 00:44:12.247173 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_92 RESULT=pass
8016 00:44:12.299142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_92 RESULT=pass>
8017 00:44:12.299820 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_92 RESULT=pass
8019 00:44:12.360338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_92 RESULT=pass>
8020 00:44:12.361121 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_92 RESULT=pass
8022 00:44:12.410866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_92 RESULT=pass>
8023 00:44:12.411514 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_92 RESULT=pass
8025 00:44:12.472739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_92 RESULT=pass>
8026 00:44:12.473576 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_92 RESULT=pass
8028 00:44:12.525822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_92 RESULT=pass>
8029 00:44:12.526488 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_92 RESULT=pass
8031 00:44:12.582375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_92 RESULT=pass>
8032 00:44:12.583214 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_92 RESULT=pass
8034 00:44:12.643362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_91 RESULT=pass>
8035 00:44:12.644161 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_91 RESULT=pass
8037 00:44:12.697909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_91 RESULT=pass>
8038 00:44:12.698688 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_91 RESULT=pass
8040 00:44:12.756061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_91 RESULT=pass>
8041 00:44:12.756819 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_91 RESULT=pass
8043 00:44:12.807962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_91 RESULT=pass>
8044 00:44:12.808738 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_91 RESULT=pass
8046 00:44:12.857737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_91 RESULT=pass>
8047 00:44:12.858576 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_91 RESULT=pass
8049 00:44:12.912096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_91 RESULT=pass>
8050 00:44:12.912993 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_91 RESULT=pass
8052 00:44:12.972668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_91 RESULT=pass>
8053 00:44:12.973412 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_91 RESULT=pass
8055 00:44:13.036987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_90 RESULT=pass>
8056 00:44:13.037625 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_90 RESULT=pass
8058 00:44:13.091824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_90 RESULT=pass>
8059 00:44:13.092509 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_90 RESULT=pass
8061 00:44:13.153561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_90 RESULT=pass>
8062 00:44:13.154233 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_90 RESULT=pass
8064 00:44:13.218652 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_90 RESULT=pass>
8065 00:44:13.219396 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_90 RESULT=pass
8067 00:44:13.283008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_90 RESULT=pass>
8068 00:44:13.283863 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_90 RESULT=pass
8070 00:44:13.339854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_90 RESULT=pass>
8071 00:44:13.340546 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_90 RESULT=pass
8073 00:44:13.396639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_90 RESULT=pass>
8074 00:44:13.397675 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_90 RESULT=pass
8076 00:44:13.447654 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_89 RESULT=pass>
8077 00:44:13.448467 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_89 RESULT=pass
8079 00:44:13.496947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_89 RESULT=pass>
8080 00:44:13.497792 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_89 RESULT=pass
8082 00:44:13.556304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_89 RESULT=pass>
8083 00:44:13.557185 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_89 RESULT=pass
8085 00:44:13.614684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_89 RESULT=pass>
8086 00:44:13.615429 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_89 RESULT=pass
8088 00:44:13.682318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_89 RESULT=pass>
8089 00:44:13.683070 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_89 RESULT=pass
8091 00:44:13.736054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_89 RESULT=pass>
8092 00:44:13.736368 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_89 RESULT=pass
8094 00:44:13.787195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_89 RESULT=pass>
8095 00:44:13.787954 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_89 RESULT=pass
8097 00:44:13.844522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_88 RESULT=pass>
8098 00:44:13.844872 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_88 RESULT=pass
8100 00:44:13.892338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_88 RESULT=pass>
8101 00:44:13.892638 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_88 RESULT=pass
8103 00:44:13.940254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_88 RESULT=pass>
8104 00:44:13.940506 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_88 RESULT=pass
8106 00:44:13.987335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_88 RESULT=fail>
8107 00:44:13.987688 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_88 RESULT=fail
8109 00:44:14.038270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_88 RESULT=pass>
8110 00:44:14.038931 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_88 RESULT=pass
8112 00:44:14.098237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_88 RESULT=pass>
8113 00:44:14.098960 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_88 RESULT=pass
8115 00:44:14.154148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_88 RESULT=fail>
8116 00:44:14.154507 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_88 RESULT=fail
8118 00:44:14.208955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_87 RESULT=pass>
8119 00:44:14.209711 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_87 RESULT=pass
8121 00:44:14.256190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_87 RESULT=pass>
8122 00:44:14.256487 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_87 RESULT=pass
8124 00:44:14.310048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_87 RESULT=pass>
8125 00:44:14.310779 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_87 RESULT=pass
8127 00:44:14.361371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_87 RESULT=pass>
8128 00:44:14.361661 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_87 RESULT=pass
8130 00:44:14.406781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_87 RESULT=pass>
8131 00:44:14.407048 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_87 RESULT=pass
8133 00:44:14.453387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_87 RESULT=pass>
8134 00:44:14.453875 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_87 RESULT=pass
8136 00:44:14.506299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_87 RESULT=pass>
8137 00:44:14.506940 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_87 RESULT=pass
8139 00:44:14.568779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_86 RESULT=pass>
8140 00:44:14.569528 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_86 RESULT=pass
8142 00:44:14.622993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_86 RESULT=pass>
8143 00:44:14.623667 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_86 RESULT=pass
8145 00:44:14.680067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_86 RESULT=pass>
8146 00:44:14.680763 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_86 RESULT=pass
8148 00:44:14.730300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_86 RESULT=fail>
8149 00:44:14.731055 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_86 RESULT=fail
8151 00:44:14.788792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_86 RESULT=pass>
8152 00:44:14.789690 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_86 RESULT=pass
8154 00:44:14.844203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_86 RESULT=pass>
8155 00:44:14.845009 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_86 RESULT=pass
8157 00:44:14.901641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_86 RESULT=pass>
8158 00:44:14.902324 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_86 RESULT=pass
8160 00:44:14.958275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_85 RESULT=pass>
8161 00:44:14.958949 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_85 RESULT=pass
8163 00:44:15.011946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_85 RESULT=pass>
8164 00:44:15.012624 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_85 RESULT=pass
8166 00:44:15.070494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_85 RESULT=pass>
8167 00:44:15.071200 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_85 RESULT=pass
8169 00:44:15.124413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_85 RESULT=fail>
8170 00:44:15.125109 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_85 RESULT=fail
8172 00:44:15.177600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_85 RESULT=pass>
8173 00:44:15.178384 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_85 RESULT=pass
8175 00:44:15.229367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_85 RESULT=pass>
8176 00:44:15.229631 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_85 RESULT=pass
8178 00:44:15.277565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_85 RESULT=pass>
8179 00:44:15.278303 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_85 RESULT=pass
8181 00:44:15.328605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_84 RESULT=pass>
8182 00:44:15.329384 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_84 RESULT=pass
8184 00:44:15.381400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_84 RESULT=pass>
8185 00:44:15.382035 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_84 RESULT=pass
8187 00:44:15.442715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_84 RESULT=pass>
8188 00:44:15.443373 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_84 RESULT=pass
8190 00:44:15.499174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_84 RESULT=pass>
8191 00:44:15.499989 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_84 RESULT=pass
8193 00:44:15.518107 <6>[ 37.741797] vaux18: disabling
8194 00:44:15.521562 <6>[ 37.745210] vio28: disabling
8195 00:44:15.563317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_84 RESULT=pass>
8196 00:44:15.564042 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_84 RESULT=pass
8198 00:44:15.616231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_84 RESULT=pass>
8199 00:44:15.616498 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_84 RESULT=pass
8201 00:44:15.663449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_84 RESULT=pass>
8202 00:44:15.663830 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_84 RESULT=pass
8204 00:44:15.718318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_83 RESULT=pass>
8205 00:44:15.719076 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_83 RESULT=pass
8207 00:44:15.771915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_83 RESULT=pass>
8208 00:44:15.772675 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_83 RESULT=pass
8210 00:44:15.837679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_83 RESULT=pass>
8211 00:44:15.838317 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_83 RESULT=pass
8213 00:44:15.889841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_83 RESULT=pass>
8214 00:44:15.890514 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_83 RESULT=pass
8216 00:44:15.948148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_83 RESULT=pass>
8217 00:44:15.949113 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_83 RESULT=pass
8219 00:44:15.999855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_83 RESULT=pass>
8220 00:44:16.000618 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_83 RESULT=pass
8222 00:44:16.059303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_83 RESULT=pass>
8223 00:44:16.059978 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_83 RESULT=pass
8225 00:44:16.111207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_82 RESULT=pass>
8226 00:44:16.111888 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_82 RESULT=pass
8228 00:44:16.161401 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_82 RESULT=pass>
8229 00:44:16.162030 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_82 RESULT=pass
8231 00:44:16.219855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_82 RESULT=skip>
8232 00:44:16.220540 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_82 RESULT=skip
8234 00:44:16.277813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_82 RESULT=skip>
8235 00:44:16.278548 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_82 RESULT=skip
8237 00:44:16.336942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_82 RESULT=skip>
8238 00:44:16.337629 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_82 RESULT=skip
8240 00:44:16.395847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_82 RESULT=pass>
8241 00:44:16.396526 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_82 RESULT=pass
8243 00:44:16.452819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_82 RESULT=pass>
8244 00:44:16.453511 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_82 RESULT=pass
8246 00:44:16.498360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_81 RESULT=pass>
8247 00:44:16.498615 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_81 RESULT=pass
8249 00:44:16.540339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_81 RESULT=pass>
8250 00:44:16.540610 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_81 RESULT=pass
8252 00:44:16.589111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_81 RESULT=pass>
8253 00:44:16.589372 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_81 RESULT=pass
8255 00:44:16.636653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_81 RESULT=pass>
8256 00:44:16.636908 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_81 RESULT=pass
8258 00:44:16.682044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_81 RESULT=fail>
8259 00:44:16.682313 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_81 RESULT=fail
8261 00:44:16.733706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_81 RESULT=fail>
8262 00:44:16.734308 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_81 RESULT=fail
8264 00:44:16.792023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_81 RESULT=pass>
8265 00:44:16.792644 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_81 RESULT=pass
8267 00:44:16.849810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_80 RESULT=pass>
8268 00:44:16.850487 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_80 RESULT=pass
8270 00:44:16.901584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_80 RESULT=pass>
8271 00:44:16.902314 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_80 RESULT=pass
8273 00:44:16.957126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_80 RESULT=pass>
8274 00:44:16.957870 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_80 RESULT=pass
8276 00:44:17.011505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_80 RESULT=pass>
8277 00:44:17.012271 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_80 RESULT=pass
8279 00:44:17.058969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_80 RESULT=pass>
8280 00:44:17.059224 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_80 RESULT=pass
8282 00:44:17.107421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_80 RESULT=pass>
8283 00:44:17.107678 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_80 RESULT=pass
8285 00:44:17.156191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_80 RESULT=pass>
8286 00:44:17.156489 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_80 RESULT=pass
8288 00:44:17.202661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_79 RESULT=fail>
8289 00:44:17.202937 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_79 RESULT=fail
8291 00:44:17.242134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_79 RESULT=pass>
8292 00:44:17.242452 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_79 RESULT=pass
8294 00:44:17.292720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_79 RESULT=fail>
8295 00:44:17.293014 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_79 RESULT=fail
8297 00:44:17.340165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_79 RESULT=fail>
8298 00:44:17.340861 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_79 RESULT=fail
8300 00:44:17.396261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_79 RESULT=fail>
8301 00:44:17.397196 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_79 RESULT=fail
8303 00:44:17.454049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_79 RESULT=pass>
8304 00:44:17.454845 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_79 RESULT=pass
8306 00:44:17.514831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_79 RESULT=pass>
8307 00:44:17.515715 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_79 RESULT=pass
8309 00:44:17.571826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_78 RESULT=fail>
8310 00:44:17.572532 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_78 RESULT=fail
8312 00:44:17.629228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_78 RESULT=pass>
8313 00:44:17.630336 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_78 RESULT=pass
8315 00:44:17.682836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_78 RESULT=fail>
8316 00:44:17.683255 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_78 RESULT=fail
8318 00:44:17.735570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_78 RESULT=fail>
8319 00:44:17.736400 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_78 RESULT=fail
8321 00:44:17.789634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_78 RESULT=fail>
8322 00:44:17.790444 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_78 RESULT=fail
8324 00:44:17.844183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_78 RESULT=pass>
8325 00:44:17.845167 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_78 RESULT=pass
8327 00:44:17.896711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_78 RESULT=pass>
8328 00:44:17.897591 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_78 RESULT=pass
8330 00:44:17.956921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_77 RESULT=fail>
8331 00:44:17.957790 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_77 RESULT=fail
8333 00:44:18.013576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_77 RESULT=pass>
8334 00:44:18.014405 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_77 RESULT=pass
8336 00:44:18.074443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_77 RESULT=fail>
8337 00:44:18.075202 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_77 RESULT=fail
8339 00:44:18.127987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_77 RESULT=fail>
8340 00:44:18.128266 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_77 RESULT=fail
8342 00:44:18.179911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_77 RESULT=fail>
8343 00:44:18.180740 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_77 RESULT=fail
8345 00:44:18.232019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_77 RESULT=pass>
8346 00:44:18.232782 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_77 RESULT=pass
8348 00:44:18.293003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_77 RESULT=pass>
8349 00:44:18.293745 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_77 RESULT=pass
8351 00:44:18.349677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_76 RESULT=pass>
8352 00:44:18.350387 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_76 RESULT=pass
8354 00:44:18.404945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_76 RESULT=fail>
8355 00:44:18.405756 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_76 RESULT=fail
8357 00:44:18.468435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_76 RESULT=pass>
8358 00:44:18.469327 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_76 RESULT=pass
8360 00:44:18.522005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_76 RESULT=pass>
8361 00:44:18.522359 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_76 RESULT=pass
8363 00:44:18.572211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_76 RESULT=pass>
8364 00:44:18.572973 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_76 RESULT=pass
8366 00:44:18.625057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_76 RESULT=pass>
8367 00:44:18.625740 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_76 RESULT=pass
8369 00:44:18.669552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_76 RESULT=pass>
8370 00:44:18.669820 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_76 RESULT=pass
8372 00:44:18.716357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_75 RESULT=pass>
8373 00:44:18.716704 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_75 RESULT=pass
8375 00:44:18.762764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_75 RESULT=fail>
8376 00:44:18.763112 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_75 RESULT=fail
8378 00:44:18.811710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_75 RESULT=pass>
8379 00:44:18.812021 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_75 RESULT=pass
8381 00:44:18.864114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_75 RESULT=pass>
8382 00:44:18.864436 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_75 RESULT=pass
8384 00:44:18.914483 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_75 RESULT=pass>
8385 00:44:18.914838 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_75 RESULT=pass
8387 00:44:18.970647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_75 RESULT=pass>
8388 00:44:18.971403 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_75 RESULT=pass
8390 00:44:19.023481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_75 RESULT=pass>
8391 00:44:19.024212 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_75 RESULT=pass
8393 00:44:19.079563 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_74 RESULT=pass
8395 00:44:19.082598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_74 RESULT=pass>
8396 00:44:19.135017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_74 RESULT=fail>
8397 00:44:19.135817 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_74 RESULT=fail
8399 00:44:19.192038 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_74 RESULT=pass>
8400 00:44:19.192678 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_74 RESULT=pass
8402 00:44:19.248322 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_74 RESULT=pass>
8403 00:44:19.249003 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_74 RESULT=pass
8405 00:44:19.306567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_74 RESULT=pass>
8406 00:44:19.307491 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_74 RESULT=pass
8408 00:44:19.367041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_74 RESULT=pass>
8409 00:44:19.367727 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_74 RESULT=pass
8411 00:44:19.417800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_74 RESULT=pass>
8412 00:44:19.418442 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_74 RESULT=pass
8414 00:44:19.473782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_73 RESULT=pass>
8415 00:44:19.474492 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_73 RESULT=pass
8417 00:44:19.526314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_73 RESULT=fail>
8418 00:44:19.526978 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_73 RESULT=fail
8420 00:44:19.582461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_73 RESULT=pass>
8421 00:44:19.583087 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_73 RESULT=pass
8423 00:44:19.637929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_73 RESULT=pass>
8424 00:44:19.638615 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_73 RESULT=pass
8426 00:44:19.691612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_73 RESULT=pass>
8427 00:44:19.692292 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_73 RESULT=pass
8429 00:44:19.743761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_73 RESULT=pass>
8430 00:44:19.744447 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_73 RESULT=pass
8432 00:44:19.792608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_73 RESULT=pass>
8433 00:44:19.792900 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_73 RESULT=pass
8435 00:44:19.848141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_72 RESULT=pass>
8436 00:44:19.848855 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_72 RESULT=pass
8438 00:44:19.899727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_72 RESULT=fail>
8439 00:44:19.900506 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_72 RESULT=fail
8441 00:44:19.953195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_72 RESULT=pass>
8442 00:44:19.953534 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_72 RESULT=pass
8444 00:44:20.003679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_72 RESULT=pass>
8445 00:44:20.004361 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_72 RESULT=pass
8447 00:44:20.056763 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_72 RESULT=pass>
8448 00:44:20.057488 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_72 RESULT=pass
8450 00:44:20.111018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_72 RESULT=pass>
8451 00:44:20.111694 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_72 RESULT=pass
8453 00:44:20.166463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_72 RESULT=pass>
8454 00:44:20.166792 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_72 RESULT=pass
8456 00:44:20.219247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_71 RESULT=pass>
8457 00:44:20.219880 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_71 RESULT=pass
8459 00:44:20.269851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_71 RESULT=fail>
8460 00:44:20.270512 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_71 RESULT=fail
8462 00:44:20.326795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_71 RESULT=pass>
8463 00:44:20.327443 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_71 RESULT=pass
8465 00:44:20.376565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_71 RESULT=pass>
8466 00:44:20.377213 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_71 RESULT=pass
8468 00:44:20.435191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_71 RESULT=pass>
8469 00:44:20.435933 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_71 RESULT=pass
8471 00:44:20.486312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_71 RESULT=pass>
8472 00:44:20.487045 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_71 RESULT=pass
8474 00:44:20.539742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_71 RESULT=pass>
8475 00:44:20.540593 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_71 RESULT=pass
8477 00:44:20.592141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_70 RESULT=pass>
8478 00:44:20.592882 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_70 RESULT=pass
8480 00:44:20.644998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_70 RESULT=fail>
8481 00:44:20.645811 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_70 RESULT=fail
8483 00:44:20.700465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_70 RESULT=pass>
8484 00:44:20.701371 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_70 RESULT=pass
8486 00:44:20.754041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_70 RESULT=pass>
8487 00:44:20.754882 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_70 RESULT=pass
8489 00:44:20.813205 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_70 RESULT=pass>
8490 00:44:20.813995 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_70 RESULT=pass
8492 00:44:20.863985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_70 RESULT=pass>
8493 00:44:20.864824 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_70 RESULT=pass
8495 00:44:20.921154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_70 RESULT=pass>
8496 00:44:20.921929 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_70 RESULT=pass
8498 00:44:20.975873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_69 RESULT=pass>
8499 00:44:20.976692 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_69 RESULT=pass
8501 00:44:21.024213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_69 RESULT=fail>
8502 00:44:21.024963 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_69 RESULT=fail
8504 00:44:21.082925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_69 RESULT=pass>
8505 00:44:21.083580 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_69 RESULT=pass
8507 00:44:21.136321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_69 RESULT=pass>
8508 00:44:21.137047 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_69 RESULT=pass
8510 00:44:21.188112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_69 RESULT=pass>
8511 00:44:21.188867 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_69 RESULT=pass
8513 00:44:21.243597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_69 RESULT=pass>
8514 00:44:21.244408 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_69 RESULT=pass
8516 00:44:21.298914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_69 RESULT=pass>
8517 00:44:21.299655 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_69 RESULT=pass
8519 00:44:21.356768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_68 RESULT=pass>
8520 00:44:21.357499 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_68 RESULT=pass
8522 00:44:21.410608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_68 RESULT=fail>
8523 00:44:21.411233 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_68 RESULT=fail
8525 00:44:21.472017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_68 RESULT=pass>
8526 00:44:21.472804 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_68 RESULT=pass
8528 00:44:21.530322 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_68 RESULT=pass>
8529 00:44:21.531123 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_68 RESULT=pass
8531 00:44:21.583264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_68 RESULT=pass>
8532 00:44:21.584005 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_68 RESULT=pass
8534 00:44:21.640837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_68 RESULT=pass>
8535 00:44:21.641591 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_68 RESULT=pass
8537 00:44:21.695544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_68 RESULT=pass>
8538 00:44:21.696293 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_68 RESULT=pass
8540 00:44:21.748360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_67 RESULT=pass>
8541 00:44:21.749063 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_67 RESULT=pass
8543 00:44:21.803291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_67 RESULT=fail>
8544 00:44:21.803942 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_67 RESULT=fail
8546 00:44:21.863229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_67 RESULT=pass>
8547 00:44:21.863952 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_67 RESULT=pass
8549 00:44:21.926158 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_67 RESULT=pass>
8550 00:44:21.926980 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_67 RESULT=pass
8552 00:44:21.982991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_67 RESULT=pass>
8553 00:44:21.983745 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_67 RESULT=pass
8555 00:44:22.034175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_67 RESULT=pass>
8556 00:44:22.034960 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_67 RESULT=pass
8558 00:44:22.088823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_67 RESULT=pass>
8559 00:44:22.089517 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_67 RESULT=pass
8561 00:44:22.143513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_66 RESULT=pass>
8562 00:44:22.144218 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_66 RESULT=pass
8564 00:44:22.198493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_66 RESULT=fail>
8565 00:44:22.199230 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_66 RESULT=fail
8567 00:44:22.259370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_66 RESULT=pass>
8568 00:44:22.260346 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_66 RESULT=pass
8570 00:44:22.316312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_66 RESULT=pass>
8571 00:44:22.317064 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_66 RESULT=pass
8573 00:44:22.365662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_66 RESULT=pass>
8574 00:44:22.366599 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_66 RESULT=pass
8576 00:44:22.417706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_66 RESULT=pass>
8577 00:44:22.418622 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_66 RESULT=pass
8579 00:44:22.471706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_66 RESULT=pass>
8580 00:44:22.471970 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_66 RESULT=pass
8582 00:44:22.519981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_65 RESULT=pass>
8583 00:44:22.520322 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_65 RESULT=pass
8585 00:44:22.565932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_65 RESULT=fail>
8586 00:44:22.566764 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_65 RESULT=fail
8588 00:44:22.616482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_65 RESULT=pass>
8589 00:44:22.616747 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_65 RESULT=pass
8591 00:44:22.668785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_65 RESULT=pass>
8592 00:44:22.669163 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_65 RESULT=pass
8594 00:44:22.716969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_65 RESULT=pass>
8595 00:44:22.717233 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_65 RESULT=pass
8597 00:44:22.765217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_65 RESULT=pass>
8598 00:44:22.765478 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_65 RESULT=pass
8600 00:44:22.811667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_65 RESULT=pass>
8601 00:44:22.811979 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_65 RESULT=pass
8603 00:44:22.862286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_64 RESULT=pass>
8604 00:44:22.862664 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_64 RESULT=pass
8606 00:44:22.910715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_64 RESULT=fail>
8607 00:44:22.911089 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_64 RESULT=fail
8609 00:44:22.964655 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_64 RESULT=pass>
8610 00:44:22.965094 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_64 RESULT=pass
8612 00:44:23.019647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_64 RESULT=pass>
8613 00:44:23.020311 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_64 RESULT=pass
8615 00:44:23.076279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_64 RESULT=pass>
8616 00:44:23.077043 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_64 RESULT=pass
8618 00:44:23.128941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_64 RESULT=pass>
8619 00:44:23.129617 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_64 RESULT=pass
8621 00:44:23.182169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_64 RESULT=pass>
8622 00:44:23.182832 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_64 RESULT=pass
8624 00:44:23.233198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_63 RESULT=pass>
8625 00:44:23.233881 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_63 RESULT=pass
8627 00:44:23.281833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_63 RESULT=fail>
8628 00:44:23.282531 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_63 RESULT=fail
8630 00:44:23.334198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_63 RESULT=pass>
8631 00:44:23.334925 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_63 RESULT=pass
8633 00:44:23.390493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_63 RESULT=pass>
8634 00:44:23.391243 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_63 RESULT=pass
8636 00:44:23.446276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_63 RESULT=pass>
8637 00:44:23.446985 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_63 RESULT=pass
8639 00:44:23.498575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_63 RESULT=pass>
8640 00:44:23.499315 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_63 RESULT=pass
8642 00:44:23.554069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_63 RESULT=pass>
8643 00:44:23.554857 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_63 RESULT=pass
8645 00:44:23.605492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_62 RESULT=pass>
8646 00:44:23.606335 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_62 RESULT=pass
8648 00:44:23.652403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_62 RESULT=fail>
8649 00:44:23.653140 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_62 RESULT=fail
8651 00:44:23.708573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_62 RESULT=pass>
8652 00:44:23.709329 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_62 RESULT=pass
8654 00:44:23.759800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_62 RESULT=pass>
8655 00:44:23.760507 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_62 RESULT=pass
8657 00:44:23.817212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_62 RESULT=pass>
8658 00:44:23.818030 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_62 RESULT=pass
8660 00:44:23.870060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_62 RESULT=pass>
8661 00:44:23.870873 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_62 RESULT=pass
8663 00:44:23.922703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_62 RESULT=pass>
8664 00:44:23.923460 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_62 RESULT=pass
8666 00:44:23.975895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_61 RESULT=pass>
8667 00:44:23.976579 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_61 RESULT=pass
8669 00:44:24.027516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_61 RESULT=fail>
8670 00:44:24.028256 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_61 RESULT=fail
8672 00:44:24.084162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_61 RESULT=pass>
8673 00:44:24.085024 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_61 RESULT=pass
8675 00:44:24.140117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_61 RESULT=pass>
8676 00:44:24.140813 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_61 RESULT=pass
8678 00:44:24.194866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_61 RESULT=pass>
8679 00:44:24.195643 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_61 RESULT=pass
8681 00:44:24.247695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_61 RESULT=pass>
8682 00:44:24.248395 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_61 RESULT=pass
8684 00:44:24.301584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_61 RESULT=pass>
8685 00:44:24.302337 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_61 RESULT=pass
8687 00:44:24.350647 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_60 RESULT=pass
8689 00:44:24.353535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_60 RESULT=pass>
8690 00:44:24.402163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_60 RESULT=fail>
8691 00:44:24.402530 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_60 RESULT=fail
8693 00:44:24.455147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_60 RESULT=pass>
8694 00:44:24.455445 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_60 RESULT=pass
8696 00:44:24.502075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_60 RESULT=pass>
8697 00:44:24.502899 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_60 RESULT=pass
8699 00:44:24.559265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_60 RESULT=pass>
8700 00:44:24.559917 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_60 RESULT=pass
8702 00:44:24.618477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_60 RESULT=pass>
8703 00:44:24.619162 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_60 RESULT=pass
8705 00:44:24.676450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_60 RESULT=pass>
8706 00:44:24.677164 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_60 RESULT=pass
8708 00:44:24.732345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_59 RESULT=pass>
8709 00:44:24.733085 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_59 RESULT=pass
8711 00:44:24.779034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_59 RESULT=fail>
8712 00:44:24.779703 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_59 RESULT=fail
8714 00:44:24.839256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_59 RESULT=pass>
8715 00:44:24.840011 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_59 RESULT=pass
8717 00:44:24.897731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_59 RESULT=pass>
8718 00:44:24.898555 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_59 RESULT=pass
8720 00:44:24.956117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_59 RESULT=pass>
8721 00:44:24.956819 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_59 RESULT=pass
8723 00:44:25.010318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_59 RESULT=pass>
8724 00:44:25.011017 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_59 RESULT=pass
8726 00:44:25.068316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_59 RESULT=pass>
8727 00:44:25.069081 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_59 RESULT=pass
8729 00:44:25.120384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_58 RESULT=pass>
8730 00:44:25.121081 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_58 RESULT=pass
8732 00:44:25.170317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_58 RESULT=fail>
8733 00:44:25.171108 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_58 RESULT=fail
8735 00:44:25.224620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_58 RESULT=pass>
8736 00:44:25.225303 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_58 RESULT=pass
8738 00:44:25.276121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_58 RESULT=pass>
8739 00:44:25.276794 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_58 RESULT=pass
8741 00:44:25.333185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_58 RESULT=pass>
8742 00:44:25.333892 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_58 RESULT=pass
8744 00:44:25.388433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_58 RESULT=pass>
8745 00:44:25.389186 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_58 RESULT=pass
8747 00:44:25.442503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_58 RESULT=pass>
8748 00:44:25.443206 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_58 RESULT=pass
8750 00:44:25.495895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_57 RESULT=pass>
8751 00:44:25.496534 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_57 RESULT=pass
8753 00:44:25.544909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_57 RESULT=fail>
8754 00:44:25.545611 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_57 RESULT=fail
8756 00:44:25.600423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_57 RESULT=pass>
8757 00:44:25.601161 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_57 RESULT=pass
8759 00:44:25.652354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_57 RESULT=pass>
8760 00:44:25.653051 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_57 RESULT=pass
8762 00:44:25.704233 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_57 RESULT=pass>
8763 00:44:25.705072 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_57 RESULT=pass
8765 00:44:25.759861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_57 RESULT=pass>
8766 00:44:25.760614 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_57 RESULT=pass
8768 00:44:25.815955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_57 RESULT=pass>
8769 00:44:25.816744 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_57 RESULT=pass
8771 00:44:25.874131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_56 RESULT=pass>
8772 00:44:25.874937 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_56 RESULT=pass
8774 00:44:25.928610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_56 RESULT=fail>
8775 00:44:25.929335 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_56 RESULT=fail
8777 00:44:25.989823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_56 RESULT=pass>
8778 00:44:25.990564 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_56 RESULT=pass
8780 00:44:26.047180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_56 RESULT=pass>
8781 00:44:26.047896 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_56 RESULT=pass
8783 00:44:26.103131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_56 RESULT=pass>
8784 00:44:26.103860 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_56 RESULT=pass
8786 00:44:26.159426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_56 RESULT=pass>
8787 00:44:26.160094 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_56 RESULT=pass
8789 00:44:26.209298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_56 RESULT=pass>
8790 00:44:26.209549 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_56 RESULT=pass
8792 00:44:26.261522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_55 RESULT=pass>
8793 00:44:26.262316 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_55 RESULT=pass
8795 00:44:26.303440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_55 RESULT=fail>
8796 00:44:26.303737 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_55 RESULT=fail
8798 00:44:26.352987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_55 RESULT=pass>
8799 00:44:26.353281 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_55 RESULT=pass
8801 00:44:26.396528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_55 RESULT=pass>
8802 00:44:26.396822 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_55 RESULT=pass
8804 00:44:26.436627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_55 RESULT=pass>
8805 00:44:26.436918 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_55 RESULT=pass
8807 00:44:26.485296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_55 RESULT=pass>
8808 00:44:26.485583 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_55 RESULT=pass
8810 00:44:26.533763 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_55 RESULT=pass>
8811 00:44:26.534410 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_55 RESULT=pass
8813 00:44:26.592253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_54 RESULT=pass>
8814 00:44:26.593048 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_54 RESULT=pass
8816 00:44:26.641389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_54 RESULT=fail>
8817 00:44:26.642091 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_54 RESULT=fail
8819 00:44:26.698133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_54 RESULT=pass>
8820 00:44:26.698838 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_54 RESULT=pass
8822 00:44:26.755558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_54 RESULT=pass>
8823 00:44:26.756324 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_54 RESULT=pass
8825 00:44:26.812891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_54 RESULT=pass>
8826 00:44:26.813661 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_54 RESULT=pass
8828 00:44:26.862467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_54 RESULT=pass>
8829 00:44:26.863179 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_54 RESULT=pass
8831 00:44:26.915572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_54 RESULT=pass>
8832 00:44:26.916321 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_54 RESULT=pass
8834 00:44:26.971243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_53 RESULT=pass>
8835 00:44:26.971944 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_53 RESULT=pass
8837 00:44:27.025630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_53 RESULT=fail>
8838 00:44:27.026320 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_53 RESULT=fail
8840 00:44:27.085938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_53 RESULT=pass>
8841 00:44:27.086676 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_53 RESULT=pass
8843 00:44:27.135466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_53 RESULT=pass>
8844 00:44:27.136291 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_53 RESULT=pass
8846 00:44:27.183809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_53 RESULT=pass>
8847 00:44:27.184510 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_53 RESULT=pass
8849 00:44:27.240605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_53 RESULT=pass>
8850 00:44:27.241704 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_53 RESULT=pass
8852 00:44:27.297434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_53 RESULT=pass>
8853 00:44:27.298043 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_53 RESULT=pass
8855 00:44:27.354246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_52 RESULT=pass>
8856 00:44:27.355112 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_52 RESULT=pass
8858 00:44:27.405513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_52 RESULT=fail>
8859 00:44:27.406288 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_52 RESULT=fail
8861 00:44:27.466680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_52 RESULT=pass>
8862 00:44:27.467387 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_52 RESULT=pass
8864 00:44:27.516732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_52 RESULT=pass>
8865 00:44:27.517029 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_52 RESULT=pass
8867 00:44:27.562890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_52 RESULT=pass>
8868 00:44:27.563174 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_52 RESULT=pass
8870 00:44:27.607098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_52 RESULT=pass>
8871 00:44:27.607381 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_52 RESULT=pass
8873 00:44:27.653307 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_52 RESULT=pass>
8874 00:44:27.653642 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_52 RESULT=pass
8876 00:44:27.692439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_51 RESULT=pass>
8877 00:44:27.692738 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_51 RESULT=pass
8879 00:44:27.728749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_51 RESULT=fail>
8880 00:44:27.729043 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_51 RESULT=fail
8882 00:44:27.771531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_51 RESULT=pass>
8883 00:44:27.771819 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_51 RESULT=pass
8885 00:44:27.813638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_51 RESULT=pass>
8886 00:44:27.813914 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_51 RESULT=pass
8888 00:44:27.860327 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_51 RESULT=pass>
8889 00:44:27.860611 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_51 RESULT=pass
8891 00:44:27.904415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_51 RESULT=pass>
8892 00:44:27.904696 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_51 RESULT=pass
8894 00:44:27.946738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_51 RESULT=pass>
8895 00:44:27.947049 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_51 RESULT=pass
8897 00:44:27.987979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_50 RESULT=pass>
8898 00:44:27.988264 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_50 RESULT=pass
8900 00:44:28.030645 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_50 RESULT=fail>
8901 00:44:28.030930 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_50 RESULT=fail
8903 00:44:28.073324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_50 RESULT=pass>
8904 00:44:28.073600 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_50 RESULT=pass
8906 00:44:28.112909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_50 RESULT=pass>
8907 00:44:28.113194 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_50 RESULT=pass
8909 00:44:28.156759 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_50 RESULT=pass>
8910 00:44:28.157051 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_50 RESULT=pass
8912 00:44:28.200655 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_50 RESULT=pass>
8913 00:44:28.200935 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_50 RESULT=pass
8915 00:44:28.242324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_50 RESULT=pass>
8916 00:44:28.242603 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_50 RESULT=pass
8918 00:44:28.285382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_49 RESULT=pass>
8919 00:44:28.285665 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_49 RESULT=pass
8921 00:44:28.324912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_49 RESULT=fail>
8922 00:44:28.325189 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_49 RESULT=fail
8924 00:44:28.370048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_49 RESULT=pass>
8925 00:44:28.370331 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_49 RESULT=pass
8927 00:44:28.413316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_49 RESULT=pass>
8928 00:44:28.413597 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_49 RESULT=pass
8930 00:44:28.451724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_49 RESULT=pass>
8931 00:44:28.452018 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_49 RESULT=pass
8933 00:44:28.491191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_49 RESULT=pass>
8934 00:44:28.491479 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_49 RESULT=pass
8936 00:44:28.532446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_49 RESULT=pass>
8937 00:44:28.532735 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_49 RESULT=pass
8939 00:44:28.574389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_48 RESULT=pass>
8940 00:44:28.574685 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_48 RESULT=pass
8942 00:44:28.621052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_48 RESULT=fail>
8943 00:44:28.621341 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_48 RESULT=fail
8945 00:44:28.669035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_48 RESULT=pass>
8946 00:44:28.669326 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_48 RESULT=pass
8948 00:44:28.717107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_48 RESULT=pass>
8949 00:44:28.717392 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_48 RESULT=pass
8951 00:44:28.763736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_48 RESULT=pass>
8952 00:44:28.764029 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_48 RESULT=pass
8954 00:44:28.808885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_48 RESULT=pass>
8955 00:44:28.809168 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_48 RESULT=pass
8957 00:44:28.856411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_48 RESULT=pass>
8958 00:44:28.856700 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_48 RESULT=pass
8960 00:44:28.901917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_47 RESULT=pass>
8961 00:44:28.902201 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_47 RESULT=pass
8963 00:44:28.945254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_47 RESULT=fail>
8964 00:44:28.945552 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_47 RESULT=fail
8966 00:44:28.990384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_47 RESULT=pass>
8967 00:44:28.990683 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_47 RESULT=pass
8969 00:44:29.035792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_47 RESULT=pass>
8970 00:44:29.036110 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_47 RESULT=pass
8972 00:44:29.081635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_47 RESULT=pass>
8973 00:44:29.081926 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_47 RESULT=pass
8975 00:44:29.120291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_47 RESULT=pass>
8976 00:44:29.120575 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_47 RESULT=pass
8978 00:44:29.159948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_47 RESULT=pass>
8979 00:44:29.160241 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_47 RESULT=pass
8981 00:44:29.204105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_46 RESULT=pass>
8982 00:44:29.204391 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_46 RESULT=pass
8984 00:44:29.245239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_46 RESULT=fail>
8985 00:44:29.245527 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_46 RESULT=fail
8987 00:44:29.291464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_46 RESULT=pass>
8988 00:44:29.291754 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_46 RESULT=pass
8990 00:44:29.339917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_46 RESULT=pass>
8991 00:44:29.340237 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_46 RESULT=pass
8993 00:44:29.393582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_46 RESULT=pass>
8994 00:44:29.393880 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_46 RESULT=pass
8996 00:44:29.436211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_46 RESULT=pass>
8997 00:44:29.436561 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_46 RESULT=pass
8999 00:44:29.480826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_46 RESULT=pass>
9000 00:44:29.481197 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_46 RESULT=pass
9002 00:44:29.522915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_45 RESULT=pass>
9003 00:44:29.523280 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_45 RESULT=pass
9005 00:44:29.565545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_45 RESULT=fail>
9006 00:44:29.565824 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_45 RESULT=fail
9008 00:44:29.617914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_45 RESULT=pass>
9009 00:44:29.618233 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_45 RESULT=pass
9011 00:44:29.660183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_45 RESULT=pass>
9012 00:44:29.660474 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_45 RESULT=pass
9014 00:44:29.703693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_45 RESULT=pass>
9015 00:44:29.703983 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_45 RESULT=pass
9017 00:44:29.749939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_45 RESULT=pass>
9018 00:44:29.750268 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_45 RESULT=pass
9020 00:44:29.789474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_45 RESULT=pass>
9021 00:44:29.789767 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_45 RESULT=pass
9023 00:44:29.833792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_44 RESULT=pass>
9024 00:44:29.834077 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_44 RESULT=pass
9026 00:44:29.869117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_44 RESULT=fail>
9027 00:44:29.869407 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_44 RESULT=fail
9029 00:44:29.911572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_44 RESULT=pass>
9030 00:44:29.911857 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_44 RESULT=pass
9032 00:44:29.952699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_44 RESULT=pass>
9033 00:44:29.953011 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_44 RESULT=pass
9035 00:44:29.996183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_44 RESULT=pass>
9036 00:44:29.996477 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_44 RESULT=pass
9038 00:44:30.036788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_44 RESULT=pass>
9039 00:44:30.037070 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_44 RESULT=pass
9041 00:44:30.079800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_44 RESULT=pass>
9042 00:44:30.080090 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_44 RESULT=pass
9044 00:44:30.120768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_43 RESULT=pass>
9045 00:44:30.121053 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_43 RESULT=pass
9047 00:44:30.157863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_43 RESULT=fail>
9048 00:44:30.158149 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_43 RESULT=fail
9050 00:44:30.204932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_43 RESULT=pass>
9051 00:44:30.205209 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_43 RESULT=pass
9053 00:44:30.245908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_43 RESULT=pass>
9054 00:44:30.246225 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_43 RESULT=pass
9056 00:44:30.291272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_43 RESULT=pass>
9057 00:44:30.291540 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_43 RESULT=pass
9059 00:44:30.331940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_43 RESULT=pass>
9060 00:44:30.332189 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_43 RESULT=pass
9062 00:44:30.375894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_43 RESULT=pass>
9063 00:44:30.376147 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_43 RESULT=pass
9065 00:44:30.417713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_42 RESULT=pass>
9066 00:44:30.417980 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_42 RESULT=pass
9068 00:44:30.454180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_42 RESULT=fail>
9069 00:44:30.454468 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_42 RESULT=fail
9071 00:44:30.502046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_42 RESULT=pass>
9072 00:44:30.502308 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_42 RESULT=pass
9074 00:44:30.544195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_42 RESULT=pass>
9075 00:44:30.544439 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_42 RESULT=pass
9077 00:44:30.587022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_42 RESULT=pass>
9078 00:44:30.587269 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_42 RESULT=pass
9080 00:44:30.628249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_42 RESULT=pass>
9081 00:44:30.628501 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_42 RESULT=pass
9083 00:44:30.673289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_42 RESULT=pass>
9084 00:44:30.673540 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_42 RESULT=pass
9086 00:44:30.714702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_41 RESULT=pass>
9087 00:44:30.714947 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_41 RESULT=pass
9089 00:44:30.752724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_41 RESULT=fail>
9090 00:44:30.752978 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_41 RESULT=fail
9092 00:44:30.800286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_41 RESULT=pass>
9093 00:44:30.800535 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_41 RESULT=pass
9095 00:44:30.840891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_41 RESULT=pass>
9096 00:44:30.841143 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_41 RESULT=pass
9098 00:44:30.883847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_41 RESULT=pass>
9099 00:44:30.884105 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_41 RESULT=pass
9101 00:44:30.925224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_41 RESULT=pass>
9102 00:44:30.925474 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_41 RESULT=pass
9104 00:44:30.967759 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_41 RESULT=pass>
9105 00:44:30.968015 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_41 RESULT=pass
9107 00:44:31.010469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_40 RESULT=pass>
9108 00:44:31.010716 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_40 RESULT=pass
9110 00:44:31.049360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_40 RESULT=fail>
9111 00:44:31.049607 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_40 RESULT=fail
9113 00:44:31.094043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_40 RESULT=pass>
9114 00:44:31.094298 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_40 RESULT=pass
9116 00:44:31.134157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_40 RESULT=pass>
9117 00:44:31.134438 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_40 RESULT=pass
9119 00:44:31.175287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_40 RESULT=pass>
9120 00:44:31.175539 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_40 RESULT=pass
9122 00:44:31.218510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_40 RESULT=pass>
9123 00:44:31.218762 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_40 RESULT=pass
9125 00:44:31.263890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_40 RESULT=pass>
9126 00:44:31.264150 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_40 RESULT=pass
9128 00:44:31.306881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_39 RESULT=pass>
9129 00:44:31.307129 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_39 RESULT=pass
9131 00:44:31.347529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_39 RESULT=fail>
9132 00:44:31.347778 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_39 RESULT=fail
9134 00:44:31.393924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_39 RESULT=pass>
9135 00:44:31.394181 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_39 RESULT=pass
9137 00:44:31.438137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_39 RESULT=pass>
9138 00:44:31.438387 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_39 RESULT=pass
9140 00:44:31.478884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_39 RESULT=pass>
9141 00:44:31.479134 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_39 RESULT=pass
9143 00:44:31.518150 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_39 RESULT=pass>
9144 00:44:31.518440 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_39 RESULT=pass
9146 00:44:31.556541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_39 RESULT=pass>
9147 00:44:31.556788 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_39 RESULT=pass
9149 00:44:31.595731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_38 RESULT=pass>
9150 00:44:31.595975 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_38 RESULT=pass
9152 00:44:31.632849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_38 RESULT=fail>
9153 00:44:31.633097 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_38 RESULT=fail
9155 00:44:31.675763 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_38 RESULT=pass>
9156 00:44:31.676012 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_38 RESULT=pass
9158 00:44:31.717232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_38 RESULT=pass>
9159 00:44:31.717479 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_38 RESULT=pass
9161 00:44:31.757506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_38 RESULT=pass>
9162 00:44:31.757756 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_38 RESULT=pass
9164 00:44:31.800389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_38 RESULT=pass>
9165 00:44:31.800636 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_38 RESULT=pass
9167 00:44:31.841232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_38 RESULT=pass>
9168 00:44:31.841478 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_38 RESULT=pass
9170 00:44:31.881504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_37 RESULT=pass>
9171 00:44:31.881755 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_37 RESULT=pass
9173 00:44:31.921132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_37 RESULT=fail>
9174 00:44:31.921373 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_37 RESULT=fail
9176 00:44:31.967985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_37 RESULT=pass>
9177 00:44:31.968242 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_37 RESULT=pass
9179 00:44:32.012303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_37 RESULT=pass>
9180 00:44:32.012554 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_37 RESULT=pass
9182 00:44:32.055196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_37 RESULT=pass>
9183 00:44:32.055452 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_37 RESULT=pass
9185 00:44:32.097857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_37 RESULT=pass>
9186 00:44:32.098133 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_37 RESULT=pass
9188 00:44:32.139021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_37 RESULT=pass>
9189 00:44:32.139270 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_37 RESULT=pass
9191 00:44:32.182155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_36 RESULT=pass>
9192 00:44:32.182435 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_36 RESULT=pass
9194 00:44:32.221403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_36 RESULT=fail>
9195 00:44:32.221653 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_36 RESULT=fail
9197 00:44:32.263594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_36 RESULT=pass>
9198 00:44:32.263853 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_36 RESULT=pass
9200 00:44:32.304002 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_36 RESULT=pass>
9201 00:44:32.304253 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_36 RESULT=pass
9203 00:44:32.340589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_36 RESULT=pass>
9204 00:44:32.340838 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_36 RESULT=pass
9206 00:44:32.376045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_36 RESULT=pass>
9207 00:44:32.376293 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_36 RESULT=pass
9209 00:44:32.416769 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_36 RESULT=pass>
9210 00:44:32.417014 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_36 RESULT=pass
9212 00:44:32.454412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_35 RESULT=pass>
9213 00:44:32.454661 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_35 RESULT=pass
9215 00:44:32.488690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_35 RESULT=fail>
9216 00:44:32.488938 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_35 RESULT=fail
9218 00:44:32.527695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_35 RESULT=pass>
9219 00:44:32.527939 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_35 RESULT=pass
9221 00:44:32.566031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_35 RESULT=pass>
9222 00:44:32.566297 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_35 RESULT=pass
9224 00:44:32.601262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_35 RESULT=pass>
9225 00:44:32.601507 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_35 RESULT=pass
9227 00:44:32.646085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_35 RESULT=pass>
9228 00:44:32.646331 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_35 RESULT=pass
9230 00:44:32.686893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_35 RESULT=pass>
9231 00:44:32.687143 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_35 RESULT=pass
9233 00:44:32.727488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_34 RESULT=pass>
9234 00:44:32.727739 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_34 RESULT=pass
9236 00:44:32.767768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_34 RESULT=fail>
9237 00:44:32.768014 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_34 RESULT=fail
9239 00:44:32.817933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_34 RESULT=pass>
9240 00:44:32.818182 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_34 RESULT=pass
9242 00:44:32.862549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_34 RESULT=pass>
9243 00:44:32.862800 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_34 RESULT=pass
9245 00:44:32.904343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_34 RESULT=pass>
9246 00:44:32.904588 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_34 RESULT=pass
9248 00:44:32.946136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_34 RESULT=pass>
9249 00:44:32.946444 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_34 RESULT=pass
9251 00:44:32.990708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_34 RESULT=pass>
9252 00:44:32.990958 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_34 RESULT=pass
9254 00:44:33.035178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_33 RESULT=pass>
9255 00:44:33.035425 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_33 RESULT=pass
9257 00:44:33.072408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_33 RESULT=fail>
9258 00:44:33.072659 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_33 RESULT=fail
9260 00:44:33.116351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_33 RESULT=pass>
9261 00:44:33.116596 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_33 RESULT=pass
9263 00:44:33.157522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_33 RESULT=pass>
9264 00:44:33.157774 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_33 RESULT=pass
9266 00:44:33.203750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_33 RESULT=pass>
9267 00:44:33.203997 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_33 RESULT=pass
9269 00:44:33.244810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_33 RESULT=pass>
9270 00:44:33.245055 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_33 RESULT=pass
9272 00:44:33.284060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_33 RESULT=pass>
9273 00:44:33.284321 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_33 RESULT=pass
9275 00:44:33.327692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_32 RESULT=pass>
9276 00:44:33.327940 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_32 RESULT=pass
9278 00:44:33.368698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_32 RESULT=fail>
9279 00:44:33.368947 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_32 RESULT=fail
9281 00:44:33.415411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_32 RESULT=pass>
9282 00:44:33.415666 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_32 RESULT=pass
9284 00:44:33.460185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_32 RESULT=pass>
9285 00:44:33.460436 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_32 RESULT=pass
9287 00:44:33.500615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_32 RESULT=pass>
9288 00:44:33.500866 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_32 RESULT=pass
9290 00:44:33.541871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_32 RESULT=pass>
9291 00:44:33.542126 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_32 RESULT=pass
9293 00:44:33.584912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_32 RESULT=pass>
9294 00:44:33.585163 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_32 RESULT=pass
9296 00:44:33.628187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_31 RESULT=pass>
9297 00:44:33.628436 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_31 RESULT=pass
9299 00:44:33.668165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_31 RESULT=fail>
9300 00:44:33.668419 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_31 RESULT=fail
9302 00:44:33.717087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_31 RESULT=pass>
9303 00:44:33.717341 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_31 RESULT=pass
9305 00:44:33.759349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_31 RESULT=pass>
9306 00:44:33.759602 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_31 RESULT=pass
9308 00:44:33.804522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_31 RESULT=pass>
9309 00:44:33.804773 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_31 RESULT=pass
9311 00:44:33.849972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_31 RESULT=pass>
9312 00:44:33.850243 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_31 RESULT=pass
9314 00:44:33.890562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_31 RESULT=pass>
9315 00:44:33.890816 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_31 RESULT=pass
9317 00:44:33.933303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_30 RESULT=pass>
9318 00:44:33.933554 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_30 RESULT=pass
9320 00:44:33.976531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_30 RESULT=fail>
9321 00:44:33.976784 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_30 RESULT=fail
9323 00:44:34.024711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_30 RESULT=pass>
9324 00:44:34.024960 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_30 RESULT=pass
9326 00:44:34.064089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_30 RESULT=pass>
9327 00:44:34.064336 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_30 RESULT=pass
9329 00:44:34.105221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_30 RESULT=pass>
9330 00:44:34.105469 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_30 RESULT=pass
9332 00:44:34.143597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_30 RESULT=pass>
9333 00:44:34.143844 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_30 RESULT=pass
9335 00:44:34.182242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_30 RESULT=pass>
9336 00:44:34.182505 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_30 RESULT=pass
9338 00:44:34.218128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_29 RESULT=pass>
9339 00:44:34.218411 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_29 RESULT=pass
9341 00:44:34.251883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_29 RESULT=pass>
9342 00:44:34.252127 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_29 RESULT=pass
9344 00:44:34.295015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_29 RESULT=pass>
9345 00:44:34.295266 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_29 RESULT=pass
9347 00:44:34.334557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_29 RESULT=pass>
9348 00:44:34.334803 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_29 RESULT=pass
9350 00:44:34.372197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_29 RESULT=pass>
9351 00:44:34.372447 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_29 RESULT=pass
9353 00:44:34.411555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_29 RESULT=pass>
9354 00:44:34.411801 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_29 RESULT=pass
9356 00:44:34.449617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_29 RESULT=pass>
9357 00:44:34.449905 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_29 RESULT=pass
9359 00:44:34.492035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_28 RESULT=pass>
9360 00:44:34.492338 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_28 RESULT=pass
9362 00:44:34.528578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_28 RESULT=pass>
9363 00:44:34.528892 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_28 RESULT=pass
9365 00:44:34.572175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_28 RESULT=pass>
9366 00:44:34.572481 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_28 RESULT=pass
9368 00:44:34.613312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_28 RESULT=pass>
9369 00:44:34.613605 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_28 RESULT=pass
9371 00:44:34.655021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_28 RESULT=pass>
9372 00:44:34.655323 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_28 RESULT=pass
9374 00:44:34.694764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_28 RESULT=pass>
9375 00:44:34.695065 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_28 RESULT=pass
9377 00:44:34.735427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_28 RESULT=pass>
9378 00:44:34.735744 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_28 RESULT=pass
9380 00:44:34.779930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_27 RESULT=pass>
9381 00:44:34.780229 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_27 RESULT=pass
9383 00:44:34.817369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_27 RESULT=pass>
9384 00:44:34.817668 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_27 RESULT=pass
9386 00:44:34.862098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_27 RESULT=pass>
9387 00:44:34.862484 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_27 RESULT=pass
9389 00:44:34.903173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_27 RESULT=pass>
9390 00:44:34.903475 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_27 RESULT=pass
9392 00:44:34.941968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_27 RESULT=pass>
9393 00:44:34.942236 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_27 RESULT=pass
9395 00:44:34.984203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_27 RESULT=pass>
9396 00:44:34.984506 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_27 RESULT=pass
9398 00:44:35.027624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_27 RESULT=pass>
9399 00:44:35.027965 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_27 RESULT=pass
9401 00:44:35.068770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_26 RESULT=pass>
9402 00:44:35.069070 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_26 RESULT=pass
9404 00:44:35.102811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_26 RESULT=pass>
9405 00:44:35.103109 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_26 RESULT=pass
9407 00:44:35.144086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_26 RESULT=pass>
9408 00:44:35.144388 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_26 RESULT=pass
9410 00:44:35.184328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_26 RESULT=pass>
9411 00:44:35.184627 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_26 RESULT=pass
9413 00:44:35.223580 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_26 RESULT=pass>
9414 00:44:35.223879 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_26 RESULT=pass
9416 00:44:35.264314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_26 RESULT=pass>
9417 00:44:35.264650 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_26 RESULT=pass
9419 00:44:35.307198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_26 RESULT=pass>
9420 00:44:35.307500 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_26 RESULT=pass
9422 00:44:35.348715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_25 RESULT=pass>
9423 00:44:35.349016 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_25 RESULT=pass
9425 00:44:35.384885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_25 RESULT=pass>
9426 00:44:35.385182 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_25 RESULT=pass
9428 00:44:35.431632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_25 RESULT=pass>
9429 00:44:35.431932 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_25 RESULT=pass
9431 00:44:35.470085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_25 RESULT=pass>
9432 00:44:35.470443 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_25 RESULT=pass
9434 00:44:35.513302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_25 RESULT=pass>
9435 00:44:35.513602 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_25 RESULT=pass
9437 00:44:35.550754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_25 RESULT=pass>
9438 00:44:35.551053 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_25 RESULT=pass
9440 00:44:35.591372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_25 RESULT=pass>
9441 00:44:35.591672 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_25 RESULT=pass
9443 00:44:35.636084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_24 RESULT=pass>
9444 00:44:35.636403 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_24 RESULT=pass
9446 00:44:35.673785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_24 RESULT=pass>
9447 00:44:35.674087 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_24 RESULT=pass
9449 00:44:35.720068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_24 RESULT=pass>
9450 00:44:35.720377 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_24 RESULT=pass
9452 00:44:35.761993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_24 RESULT=pass>
9453 00:44:35.762288 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_24 RESULT=pass
9455 00:44:35.800013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_24 RESULT=pass>
9456 00:44:35.800317 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_24 RESULT=pass
9458 00:44:35.841644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_24 RESULT=pass>
9459 00:44:35.841947 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_24 RESULT=pass
9461 00:44:35.881755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_24 RESULT=pass>
9462 00:44:35.882058 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_24 RESULT=pass
9464 00:44:35.920034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_23 RESULT=pass>
9465 00:44:35.920336 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_23 RESULT=pass
9467 00:44:35.958179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_23 RESULT=pass>
9468 00:44:35.958568 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_23 RESULT=pass
9470 00:44:36.001346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_23 RESULT=pass>
9471 00:44:36.001651 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_23 RESULT=pass
9473 00:44:36.043594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_23 RESULT=pass>
9474 00:44:36.043896 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_23 RESULT=pass
9476 00:44:36.082570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_23 RESULT=pass>
9477 00:44:36.082872 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_23 RESULT=pass
9479 00:44:36.123236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_23 RESULT=pass>
9480 00:44:36.123586 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_23 RESULT=pass
9482 00:44:36.161650 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_23 RESULT=pass>
9483 00:44:36.161960 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_23 RESULT=pass
9485 00:44:36.203060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_22 RESULT=pass>
9486 00:44:36.203363 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_22 RESULT=pass
9488 00:44:36.241353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_22 RESULT=pass>
9489 00:44:36.241660 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_22 RESULT=pass
9491 00:44:36.291469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_22 RESULT=pass>
9492 00:44:36.291770 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_22 RESULT=pass
9494 00:44:36.338109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_22 RESULT=pass>
9495 00:44:36.338448 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_22 RESULT=pass
9497 00:44:36.383118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_22 RESULT=pass>
9498 00:44:36.383420 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_22 RESULT=pass
9500 00:44:36.426204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_22 RESULT=pass>
9501 00:44:36.426543 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_22 RESULT=pass
9503 00:44:36.467201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_22 RESULT=pass>
9504 00:44:36.467504 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_22 RESULT=pass
9506 00:44:36.507303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_21 RESULT=pass>
9507 00:44:36.507607 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_21 RESULT=pass
9509 00:44:36.542906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_21 RESULT=fail>
9510 00:44:36.543211 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_21 RESULT=fail
9512 00:44:36.587637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_21 RESULT=pass>
9513 00:44:36.587947 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_21 RESULT=pass
9515 00:44:36.627825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_21 RESULT=pass>
9516 00:44:36.628129 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_21 RESULT=pass
9518 00:44:36.669457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_21 RESULT=pass>
9519 00:44:36.669759 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_21 RESULT=pass
9521 00:44:36.711159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_21 RESULT=pass>
9522 00:44:36.711465 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_21 RESULT=pass
9524 00:44:36.753163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_21 RESULT=pass>
9525 00:44:36.753465 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_21 RESULT=pass
9527 00:44:36.793216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_20 RESULT=pass>
9528 00:44:36.793519 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_20 RESULT=pass
9530 00:44:36.830556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_20 RESULT=fail>
9531 00:44:36.830859 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_20 RESULT=fail
9533 00:44:36.875105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_20 RESULT=pass>
9534 00:44:36.875407 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_20 RESULT=pass
9536 00:44:36.914205 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_20 RESULT=pass>
9537 00:44:36.914529 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_20 RESULT=pass
9539 00:44:36.957446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_20 RESULT=pass>
9540 00:44:36.957749 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_20 RESULT=pass
9542 00:44:36.997161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_20 RESULT=pass>
9543 00:44:36.997481 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_20 RESULT=pass
9545 00:44:37.036865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_20 RESULT=pass>
9546 00:44:37.037172 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_20 RESULT=pass
9548 00:44:37.079313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_19 RESULT=pass>
9549 00:44:37.079613 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_19 RESULT=pass
9551 00:44:37.118983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_19 RESULT=fail>
9552 00:44:37.119291 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_19 RESULT=fail
9554 00:44:37.167712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_19 RESULT=pass>
9555 00:44:37.168041 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_19 RESULT=pass
9557 00:44:37.210003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_19 RESULT=pass>
9558 00:44:37.210321 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_19 RESULT=pass
9560 00:44:37.252799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_19 RESULT=pass>
9561 00:44:37.253102 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_19 RESULT=pass
9563 00:44:37.295512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_19 RESULT=pass>
9564 00:44:37.295815 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_19 RESULT=pass
9566 00:44:37.338326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_19 RESULT=pass>
9567 00:44:37.338628 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_19 RESULT=pass
9569 00:44:37.381871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_18 RESULT=pass>
9570 00:44:37.382174 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_18 RESULT=pass
9572 00:44:37.422838 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_18 RESULT=fail>
9573 00:44:37.423148 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_18 RESULT=fail
9575 00:44:37.466815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_18 RESULT=pass>
9576 00:44:37.467117 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_18 RESULT=pass
9578 00:44:37.504645 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_18 RESULT=pass>
9579 00:44:37.504949 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_18 RESULT=pass
9581 00:44:37.544312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_18 RESULT=pass>
9582 00:44:37.544615 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_18 RESULT=pass
9584 00:44:37.585252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_18 RESULT=pass>
9585 00:44:37.585557 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_18 RESULT=pass
9587 00:44:37.628916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_18 RESULT=pass>
9588 00:44:37.629220 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_18 RESULT=pass
9590 00:44:37.667529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_17 RESULT=pass>
9591 00:44:37.667834 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_17 RESULT=pass
9593 00:44:37.706953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_17 RESULT=fail>
9594 00:44:37.707256 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_17 RESULT=fail
9596 00:44:37.750191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_17 RESULT=pass>
9597 00:44:37.750530 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_17 RESULT=pass
9599 00:44:37.793799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_17 RESULT=pass>
9600 00:44:37.794115 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_17 RESULT=pass
9602 00:44:37.839015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_17 RESULT=pass>
9603 00:44:37.839316 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_17 RESULT=pass
9605 00:44:37.884079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_17 RESULT=pass>
9606 00:44:37.884376 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_17 RESULT=pass
9608 00:44:37.921594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_17 RESULT=pass>
9609 00:44:37.921895 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_17 RESULT=pass
9611 00:44:37.964630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_16 RESULT=pass>
9612 00:44:37.964933 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_16 RESULT=pass
9614 00:44:38.008825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_16 RESULT=fail>
9615 00:44:38.009125 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_16 RESULT=fail
9617 00:44:38.057244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_16 RESULT=pass>
9618 00:44:38.057549 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_16 RESULT=pass
9620 00:44:38.099044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_16 RESULT=pass>
9621 00:44:38.099343 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_16 RESULT=pass
9623 00:44:38.142620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_16 RESULT=pass>
9624 00:44:38.142920 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_16 RESULT=pass
9626 00:44:38.183013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_16 RESULT=pass>
9627 00:44:38.183314 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_16 RESULT=pass
9629 00:44:38.220676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_16 RESULT=pass>
9630 00:44:38.220978 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_16 RESULT=pass
9632 00:44:38.262538 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_15 RESULT=pass>
9633 00:44:38.262871 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_15 RESULT=pass
9635 00:44:38.303728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_15 RESULT=fail>
9636 00:44:38.304026 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_15 RESULT=fail
9638 00:44:38.345466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_15 RESULT=pass>
9639 00:44:38.345766 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_15 RESULT=pass
9641 00:44:38.382160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_15 RESULT=pass>
9642 00:44:38.382496 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_15 RESULT=pass
9644 00:44:38.424591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_15 RESULT=pass>
9645 00:44:38.424918 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_15 RESULT=pass
9647 00:44:38.464180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_15 RESULT=pass>
9648 00:44:38.464521 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_15 RESULT=pass
9650 00:44:38.509489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_15 RESULT=pass>
9651 00:44:38.509792 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_15 RESULT=pass
9653 00:44:38.554347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_14 RESULT=pass>
9654 00:44:38.554652 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_14 RESULT=pass
9656 00:44:38.592085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_14 RESULT=fail>
9657 00:44:38.592389 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_14 RESULT=fail
9659 00:44:38.635143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_14 RESULT=pass>
9660 00:44:38.635454 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_14 RESULT=pass
9662 00:44:38.679848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_14 RESULT=pass>
9663 00:44:38.680150 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_14 RESULT=pass
9665 00:44:38.725669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_14 RESULT=pass>
9666 00:44:38.725975 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_14 RESULT=pass
9668 00:44:38.771522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_14 RESULT=pass>
9669 00:44:38.771824 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_14 RESULT=pass
9671 00:44:38.814549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_14 RESULT=pass>
9672 00:44:38.814849 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_14 RESULT=pass
9674 00:44:38.854209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_13 RESULT=pass>
9675 00:44:38.854511 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_13 RESULT=pass
9677 00:44:38.895034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_13 RESULT=fail>
9678 00:44:38.895336 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_13 RESULT=fail
9680 00:44:38.938452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_13 RESULT=pass>
9681 00:44:38.938751 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_13 RESULT=pass
9683 00:44:38.980633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_13 RESULT=pass>
9684 00:44:38.980952 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_13 RESULT=pass
9686 00:44:39.022608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_13 RESULT=pass>
9687 00:44:39.022905 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_13 RESULT=pass
9689 00:44:39.062626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_13 RESULT=pass>
9690 00:44:39.062930 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_13 RESULT=pass
9692 00:44:39.104970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_13 RESULT=pass>
9693 00:44:39.105289 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_13 RESULT=pass
9695 00:44:39.142022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_12 RESULT=pass>
9696 00:44:39.142350 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_12 RESULT=pass
9698 00:44:39.178751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_12 RESULT=fail>
9699 00:44:39.179052 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_12 RESULT=fail
9701 00:44:39.221588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_12 RESULT=pass>
9702 00:44:39.221886 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_12 RESULT=pass
9704 00:44:39.263152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_12 RESULT=pass>
9705 00:44:39.263452 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_12 RESULT=pass
9707 00:44:39.303759 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_12 RESULT=pass>
9708 00:44:39.304057 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_12 RESULT=pass
9710 00:44:39.344590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_12 RESULT=pass>
9711 00:44:39.344889 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_12 RESULT=pass
9713 00:44:39.387294 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_12 RESULT=pass>
9714 00:44:39.387601 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_12 RESULT=pass
9716 00:44:39.429128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_11 RESULT=pass>
9717 00:44:39.429431 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_11 RESULT=pass
9719 00:44:39.470271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_11 RESULT=fail>
9720 00:44:39.470574 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_11 RESULT=fail
9722 00:44:39.512541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_11 RESULT=pass>
9723 00:44:39.512844 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_11 RESULT=pass
9725 00:44:39.555351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_11 RESULT=pass>
9726 00:44:39.555650 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_11 RESULT=pass
9728 00:44:39.595636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_11 RESULT=pass>
9729 00:44:39.595933 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_11 RESULT=pass
9731 00:44:39.638831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_11 RESULT=pass>
9732 00:44:39.639122 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_11 RESULT=pass
9734 00:44:39.683120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_11 RESULT=pass>
9735 00:44:39.683420 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_11 RESULT=pass
9737 00:44:39.726346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_10 RESULT=pass>
9738 00:44:39.726643 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_10 RESULT=pass
9740 00:44:39.763871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_10 RESULT=fail>
9741 00:44:39.764173 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_10 RESULT=fail
9743 00:44:39.805688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_10 RESULT=pass>
9744 00:44:39.805987 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_10 RESULT=pass
9746 00:44:39.848750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_10 RESULT=pass>
9747 00:44:39.849053 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_10 RESULT=pass
9749 00:44:39.891022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_10 RESULT=pass>
9750 00:44:39.891320 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_10 RESULT=pass
9752 00:44:39.938367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_10 RESULT=pass>
9753 00:44:39.938664 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_10 RESULT=pass
9755 00:44:39.981227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_10 RESULT=pass>
9756 00:44:39.981522 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_10 RESULT=pass
9758 00:44:40.018148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_9 RESULT=pass>
9759 00:44:40.018471 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_9 RESULT=pass
9761 00:44:40.053488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_9 RESULT=fail>
9762 00:44:40.053788 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_9 RESULT=fail
9764 00:44:40.098019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_9 RESULT=pass>
9765 00:44:40.098320 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_9 RESULT=pass
9767 00:44:40.142608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_9 RESULT=pass>
9768 00:44:40.142902 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_9 RESULT=pass
9770 00:44:40.184236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_9 RESULT=pass>
9771 00:44:40.184537 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_9 RESULT=pass
9773 00:44:40.224580 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_9 RESULT=pass>
9774 00:44:40.224882 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_9 RESULT=pass
9776 00:44:40.263613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_9 RESULT=pass>
9777 00:44:40.263910 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_9 RESULT=pass
9779 00:44:40.303101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_8 RESULT=pass>
9780 00:44:40.303401 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_8 RESULT=pass
9782 00:44:40.342545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_8 RESULT=fail>
9783 00:44:40.342841 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_8 RESULT=fail
9785 00:44:40.392151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_8 RESULT=pass>
9786 00:44:40.392449 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_8 RESULT=pass
9788 00:44:40.434951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_8 RESULT=pass>
9789 00:44:40.435253 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_8 RESULT=pass
9791 00:44:40.479047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_8 RESULT=pass>
9792 00:44:40.479348 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_8 RESULT=pass
9794 00:44:40.522853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_8 RESULT=pass>
9795 00:44:40.523152 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_8 RESULT=pass
9797 00:44:40.569408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_8 RESULT=pass>
9798 00:44:40.569715 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_8 RESULT=pass
9800 00:44:40.610099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_7 RESULT=pass>
9801 00:44:40.610418 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_7 RESULT=pass
9803 00:44:40.651335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_7 RESULT=fail>
9804 00:44:40.651652 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_7 RESULT=fail
9806 00:44:40.697167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_7 RESULT=pass>
9807 00:44:40.697479 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_7 RESULT=pass
9809 00:44:40.740101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_7 RESULT=pass>
9810 00:44:40.740403 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_7 RESULT=pass
9812 00:44:40.784727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_7 RESULT=pass>
9813 00:44:40.785027 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_7 RESULT=pass
9815 00:44:40.825552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_7 RESULT=pass>
9816 00:44:40.825847 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_7 RESULT=pass
9818 00:44:40.862760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_7 RESULT=pass>
9819 00:44:40.863059 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_7 RESULT=pass
9821 00:44:40.901127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_6 RESULT=pass>
9822 00:44:40.901428 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_6 RESULT=pass
9824 00:44:40.940569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_6 RESULT=fail>
9825 00:44:40.940869 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_6 RESULT=fail
9827 00:44:40.983124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_6 RESULT=pass>
9828 00:44:40.983422 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_6 RESULT=pass
9830 00:44:41.020979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_6 RESULT=pass>
9831 00:44:41.021278 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_6 RESULT=pass
9833 00:44:41.061519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_6 RESULT=pass>
9834 00:44:41.061820 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_6 RESULT=pass
9836 00:44:41.103071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_6 RESULT=pass>
9837 00:44:41.103372 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_6 RESULT=pass
9839 00:44:41.144285 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_6 RESULT=pass>
9840 00:44:41.144587 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_6 RESULT=pass
9842 00:44:41.188479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_5 RESULT=pass>
9843 00:44:41.188779 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_5 RESULT=pass
9845 00:44:41.229594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_5 RESULT=pass>
9846 00:44:41.229895 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_5 RESULT=pass
9848 00:44:41.269907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_5 RESULT=pass>
9849 00:44:41.270216 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_5 RESULT=pass
9851 00:44:41.311086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_5 RESULT=pass>
9852 00:44:41.311379 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_5 RESULT=pass
9854 00:44:41.355783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_5 RESULT=pass>
9855 00:44:41.356071 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_5 RESULT=pass
9857 00:44:41.396540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_5 RESULT=fail>
9858 00:44:41.396815 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_5 RESULT=fail
9860 00:44:41.436599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_5 RESULT=pass>
9861 00:44:41.436867 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_5 RESULT=pass
9863 00:44:41.474921 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_4 RESULT=pass
9865 00:44:41.477970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_4 RESULT=pass>
9866 00:44:41.511813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_4 RESULT=pass>
9867 00:44:41.512099 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_4 RESULT=pass
9869 00:44:41.555418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_4 RESULT=pass>
9870 00:44:41.555707 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_4 RESULT=pass
9872 00:44:41.595405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_4 RESULT=pass>
9873 00:44:41.595689 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_4 RESULT=pass
9875 00:44:41.640926 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_4 RESULT=pass>
9876 00:44:41.641211 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_4 RESULT=pass
9878 00:44:41.678944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_4 RESULT=fail>
9879 00:44:41.679250 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_4 RESULT=fail
9881 00:44:41.719529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_4 RESULT=pass>
9882 00:44:41.719806 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_4 RESULT=pass
9884 00:44:41.762552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_3 RESULT=pass>
9885 00:44:41.762834 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_3 RESULT=pass
9887 00:44:41.798993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_3 RESULT=pass>
9888 00:44:41.799264 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_3 RESULT=pass
9890 00:44:41.845349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_3 RESULT=pass>
9891 00:44:41.845656 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_3 RESULT=pass
9893 00:44:41.889603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_3 RESULT=pass>
9894 00:44:41.889903 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_3 RESULT=pass
9896 00:44:41.937619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_3 RESULT=pass>
9897 00:44:41.937939 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_3 RESULT=pass
9899 00:44:41.985965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_3 RESULT=fail>
9900 00:44:41.986248 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_3 RESULT=fail
9902 00:44:42.031186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_3 RESULT=pass>
9903 00:44:42.031482 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_3 RESULT=pass
9905 00:44:42.071524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_2 RESULT=pass>
9906 00:44:42.071826 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_2 RESULT=pass
9908 00:44:42.108765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_2 RESULT=pass>
9909 00:44:42.109063 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_2 RESULT=pass
9911 00:44:42.153688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_2 RESULT=pass>
9912 00:44:42.154013 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_2 RESULT=pass
9914 00:44:42.193066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_2 RESULT=pass>
9915 00:44:42.193389 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_2 RESULT=pass
9917 00:44:42.233946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_2 RESULT=pass>
9918 00:44:42.234264 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_2 RESULT=pass
9920 00:44:42.277504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_2 RESULT=fail>
9921 00:44:42.277804 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_2 RESULT=fail
9923 00:44:42.321112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_2 RESULT=pass>
9924 00:44:42.321416 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_2 RESULT=pass
9926 00:44:42.361323 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_1 RESULT=pass
9928 00:44:42.364010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_1 RESULT=pass>
9929 00:44:42.403947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_1 RESULT=pass>
9930 00:44:42.404245 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_1 RESULT=pass
9932 00:44:42.448288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_1 RESULT=pass>
9933 00:44:42.448590 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_1 RESULT=pass
9935 00:44:42.494645 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_1 RESULT=pass>
9936 00:44:42.494944 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_1 RESULT=pass
9938 00:44:42.534095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_1 RESULT=pass>
9939 00:44:42.534446 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_1 RESULT=pass
9941 00:44:42.576204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_1 RESULT=fail>
9942 00:44:42.576499 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_1 RESULT=fail
9944 00:44:42.624754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_1 RESULT=pass>
9945 00:44:42.625054 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_1 RESULT=pass
9947 00:44:42.667902 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_0 RESULT=pass
9949 00:44:42.670898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_0 RESULT=pass>
9950 00:44:42.707119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_0 RESULT=pass>
9951 00:44:42.707417 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_0 RESULT=pass
9953 00:44:42.756764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_0 RESULT=pass>
9954 00:44:42.757065 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_0 RESULT=pass
9956 00:44:42.801246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_0 RESULT=pass>
9957 00:44:42.801547 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_0 RESULT=pass
9959 00:44:42.844421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_0 RESULT=pass>
9960 00:44:42.844722 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_0 RESULT=pass
9962 00:44:42.883033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_0 RESULT=fail>
9963 00:44:42.883333 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_0 RESULT=fail
9965 00:44:42.931966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_0 RESULT=pass>
9966 00:44:42.932267 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_0 RESULT=pass
9968 00:44:42.973191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test RESULT=pass>
9969 00:44:42.973324 + set +x
9970 00:44:42.973555 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test RESULT=pass
9972 00:44:42.979671 <LAVA_SIGNAL_ENDRUN 1_kselftest-alsa 14368368_1.6.2.3.5>
9973 00:44:42.979919 Received signal: <ENDRUN> 1_kselftest-alsa 14368368_1.6.2.3.5
9974 00:44:42.979990 Ending use of test pattern.
9975 00:44:42.980047 Ending test lava.1_kselftest-alsa (14368368_1.6.2.3.5), duration 44.22
9977 00:44:42.982825 <LAVA_TEST_RUNNER EXIT>
9978 00:44:42.983068 ok: lava_test_shell seems to have completed
9979 00:44:42.986063 alsa_mixer-test: pass
alsa_mixer-test_event_missing_0_0: fail
alsa_mixer-test_event_missing_0_1: fail
alsa_mixer-test_event_missing_0_10: pass
alsa_mixer-test_event_missing_0_11: pass
alsa_mixer-test_event_missing_0_12: pass
alsa_mixer-test_event_missing_0_13: pass
alsa_mixer-test_event_missing_0_14: pass
alsa_mixer-test_event_missing_0_15: pass
alsa_mixer-test_event_missing_0_16: pass
alsa_mixer-test_event_missing_0_17: pass
alsa_mixer-test_event_missing_0_18: pass
alsa_mixer-test_event_missing_0_19: pass
alsa_mixer-test_event_missing_0_2: fail
alsa_mixer-test_event_missing_0_20: pass
alsa_mixer-test_event_missing_0_21: pass
alsa_mixer-test_event_missing_0_22: pass
alsa_mixer-test_event_missing_0_23: pass
alsa_mixer-test_event_missing_0_24: pass
alsa_mixer-test_event_missing_0_25: pass
alsa_mixer-test_event_missing_0_26: pass
alsa_mixer-test_event_missing_0_27: pass
alsa_mixer-test_event_missing_0_28: pass
alsa_mixer-test_event_missing_0_29: pass
alsa_mixer-test_event_missing_0_3: fail
alsa_mixer-test_event_missing_0_30: pass
alsa_mixer-test_event_missing_0_31: pass
alsa_mixer-test_event_missing_0_32: pass
alsa_mixer-test_event_missing_0_33: pass
alsa_mixer-test_event_missing_0_34: pass
alsa_mixer-test_event_missing_0_35: pass
alsa_mixer-test_event_missing_0_36: pass
alsa_mixer-test_event_missing_0_37: pass
alsa_mixer-test_event_missing_0_38: pass
alsa_mixer-test_event_missing_0_39: pass
alsa_mixer-test_event_missing_0_4: fail
alsa_mixer-test_event_missing_0_40: pass
alsa_mixer-test_event_missing_0_41: pass
alsa_mixer-test_event_missing_0_42: pass
alsa_mixer-test_event_missing_0_43: pass
alsa_mixer-test_event_missing_0_44: pass
alsa_mixer-test_event_missing_0_45: pass
alsa_mixer-test_event_missing_0_46: pass
alsa_mixer-test_event_missing_0_47: pass
alsa_mixer-test_event_missing_0_48: pass
alsa_mixer-test_event_missing_0_49: pass
alsa_mixer-test_event_missing_0_5: fail
alsa_mixer-test_event_missing_0_50: pass
alsa_mixer-test_event_missing_0_51: pass
alsa_mixer-test_event_missing_0_52: pass
alsa_mixer-test_event_missing_0_53: pass
alsa_mixer-test_event_missing_0_54: pass
alsa_mixer-test_event_missing_0_55: pass
alsa_mixer-test_event_missing_0_56: pass
alsa_mixer-test_event_missing_0_57: pass
alsa_mixer-test_event_missing_0_58: pass
alsa_mixer-test_event_missing_0_59: pass
alsa_mixer-test_event_missing_0_6: pass
alsa_mixer-test_event_missing_0_60: pass
alsa_mixer-test_event_missing_0_61: pass
alsa_mixer-test_event_missing_0_62: pass
alsa_mixer-test_event_missing_0_63: pass
alsa_mixer-test_event_missing_0_64: pass
alsa_mixer-test_event_missing_0_65: pass
alsa_mixer-test_event_missing_0_66: pass
alsa_mixer-test_event_missing_0_67: pass
alsa_mixer-test_event_missing_0_68: pass
alsa_mixer-test_event_missing_0_69: pass
alsa_mixer-test_event_missing_0_7: pass
alsa_mixer-test_event_missing_0_70: pass
alsa_mixer-test_event_missing_0_71: pass
alsa_mixer-test_event_missing_0_72: pass
alsa_mixer-test_event_missing_0_73: pass
alsa_mixer-test_event_missing_0_74: pass
alsa_mixer-test_event_missing_0_75: pass
alsa_mixer-test_event_missing_0_76: pass
alsa_mixer-test_event_missing_0_77: pass
alsa_mixer-test_event_missing_0_78: pass
alsa_mixer-test_event_missing_0_79: pass
alsa_mixer-test_event_missing_0_8: pass
alsa_mixer-test_event_missing_0_80: pass
alsa_mixer-test_event_missing_0_81: fail
alsa_mixer-test_event_missing_0_82: pass
alsa_mixer-test_event_missing_0_83: pass
alsa_mixer-test_event_missing_0_84: pass
alsa_mixer-test_event_missing_0_85: pass
alsa_mixer-test_event_missing_0_86: pass
alsa_mixer-test_event_missing_0_87: pass
alsa_mixer-test_event_missing_0_88: pass
alsa_mixer-test_event_missing_0_89: pass
alsa_mixer-test_event_missing_0_9: pass
alsa_mixer-test_event_missing_0_90: pass
alsa_mixer-test_event_missing_0_91: pass
alsa_mixer-test_event_missing_0_92: pass
alsa_mixer-test_event_missing_0_93: pass
alsa_mixer-test_event_spurious_0_0: pass
alsa_mixer-test_event_spurious_0_1: pass
alsa_mixer-test_event_spurious_0_10: pass
alsa_mixer-test_event_spurious_0_11: pass
alsa_mixer-test_event_spurious_0_12: pass
alsa_mixer-test_event_spurious_0_13: pass
alsa_mixer-test_event_spurious_0_14: pass
alsa_mixer-test_event_spurious_0_15: pass
alsa_mixer-test_event_spurious_0_16: pass
alsa_mixer-test_event_spurious_0_17: pass
alsa_mixer-test_event_spurious_0_18: pass
alsa_mixer-test_event_spurious_0_19: pass
alsa_mixer-test_event_spurious_0_2: pass
alsa_mixer-test_event_spurious_0_20: pass
alsa_mixer-test_event_spurious_0_21: pass
alsa_mixer-test_event_spurious_0_22: pass
alsa_mixer-test_event_spurious_0_23: pass
alsa_mixer-test_event_spurious_0_24: pass
alsa_mixer-test_event_spurious_0_25: pass
alsa_mixer-test_event_spurious_0_26: pass
alsa_mixer-test_event_spurious_0_27: pass
alsa_mixer-test_event_spurious_0_28: pass
alsa_mixer-test_event_spurious_0_29: pass
alsa_mixer-test_event_spurious_0_3: pass
alsa_mixer-test_event_spurious_0_30: pass
alsa_mixer-test_event_spurious_0_31: pass
alsa_mixer-test_event_spurious_0_32: pass
alsa_mixer-test_event_spurious_0_33: pass
alsa_mixer-test_event_spurious_0_34: pass
alsa_mixer-test_event_spurious_0_35: pass
alsa_mixer-test_event_spurious_0_36: pass
alsa_mixer-test_event_spurious_0_37: pass
alsa_mixer-test_event_spurious_0_38: pass
alsa_mixer-test_event_spurious_0_39: pass
alsa_mixer-test_event_spurious_0_4: pass
alsa_mixer-test_event_spurious_0_40: pass
alsa_mixer-test_event_spurious_0_41: pass
alsa_mixer-test_event_spurious_0_42: pass
alsa_mixer-test_event_spurious_0_43: pass
alsa_mixer-test_event_spurious_0_44: pass
alsa_mixer-test_event_spurious_0_45: pass
alsa_mixer-test_event_spurious_0_46: pass
alsa_mixer-test_event_spurious_0_47: pass
alsa_mixer-test_event_spurious_0_48: pass
alsa_mixer-test_event_spurious_0_49: pass
alsa_mixer-test_event_spurious_0_5: pass
alsa_mixer-test_event_spurious_0_50: pass
alsa_mixer-test_event_spurious_0_51: pass
alsa_mixer-test_event_spurious_0_52: pass
alsa_mixer-test_event_spurious_0_53: pass
alsa_mixer-test_event_spurious_0_54: pass
alsa_mixer-test_event_spurious_0_55: pass
alsa_mixer-test_event_spurious_0_56: pass
alsa_mixer-test_event_spurious_0_57: pass
alsa_mixer-test_event_spurious_0_58: pass
alsa_mixer-test_event_spurious_0_59: pass
alsa_mixer-test_event_spurious_0_6: pass
alsa_mixer-test_event_spurious_0_60: pass
alsa_mixer-test_event_spurious_0_61: pass
alsa_mixer-test_event_spurious_0_62: pass
alsa_mixer-test_event_spurious_0_63: pass
alsa_mixer-test_event_spurious_0_64: pass
alsa_mixer-test_event_spurious_0_65: pass
alsa_mixer-test_event_spurious_0_66: pass
alsa_mixer-test_event_spurious_0_67: pass
alsa_mixer-test_event_spurious_0_68: pass
alsa_mixer-test_event_spurious_0_69: pass
alsa_mixer-test_event_spurious_0_7: pass
alsa_mixer-test_event_spurious_0_70: pass
alsa_mixer-test_event_spurious_0_71: pass
alsa_mixer-test_event_spurious_0_72: pass
alsa_mixer-test_event_spurious_0_73: pass
alsa_mixer-test_event_spurious_0_74: pass
alsa_mixer-test_event_spurious_0_75: pass
alsa_mixer-test_event_spurious_0_76: pass
alsa_mixer-test_event_spurious_0_77: pass
alsa_mixer-test_event_spurious_0_78: pass
alsa_mixer-test_event_spurious_0_79: pass
alsa_mixer-test_event_spurious_0_8: pass
alsa_mixer-test_event_spurious_0_80: pass
alsa_mixer-test_event_spurious_0_81: pass
alsa_mixer-test_event_spurious_0_82: pass
alsa_mixer-test_event_spurious_0_83: pass
alsa_mixer-test_event_spurious_0_84: pass
alsa_mixer-test_event_spurious_0_85: pass
alsa_mixer-test_event_spurious_0_86: pass
alsa_mixer-test_event_spurious_0_87: pass
alsa_mixer-test_event_spurious_0_88: fail
alsa_mixer-test_event_spurious_0_89: pass
alsa_mixer-test_event_spurious_0_9: pass
alsa_mixer-test_event_spurious_0_90: pass
alsa_mixer-test_event_spurious_0_91: pass
alsa_mixer-test_event_spurious_0_92: pass
alsa_mixer-test_event_spurious_0_93: pass
alsa_mixer-test_get_value_0_0: pass
alsa_mixer-test_get_value_0_1: pass
alsa_mixer-test_get_value_0_10: pass
alsa_mixer-test_get_value_0_11: pass
alsa_mixer-test_get_value_0_12: pass
alsa_mixer-test_get_value_0_13: pass
alsa_mixer-test_get_value_0_14: pass
alsa_mixer-test_get_value_0_15: pass
alsa_mixer-test_get_value_0_16: pass
alsa_mixer-test_get_value_0_17: pass
alsa_mixer-test_get_value_0_18: pass
alsa_mixer-test_get_value_0_19: pass
alsa_mixer-test_get_value_0_2: pass
alsa_mixer-test_get_value_0_20: pass
alsa_mixer-test_get_value_0_21: pass
alsa_mixer-test_get_value_0_22: pass
alsa_mixer-test_get_value_0_23: pass
alsa_mixer-test_get_value_0_24: pass
alsa_mixer-test_get_value_0_25: pass
alsa_mixer-test_get_value_0_26: pass
alsa_mixer-test_get_value_0_27: pass
alsa_mixer-test_get_value_0_28: pass
alsa_mixer-test_get_value_0_29: pass
alsa_mixer-test_get_value_0_3: pass
alsa_mixer-test_get_value_0_30: pass
alsa_mixer-test_get_value_0_31: pass
alsa_mixer-test_get_value_0_32: pass
alsa_mixer-test_get_value_0_33: pass
alsa_mixer-test_get_value_0_34: pass
alsa_mixer-test_get_value_0_35: pass
alsa_mixer-test_get_value_0_36: pass
alsa_mixer-test_get_value_0_37: pass
alsa_mixer-test_get_value_0_38: pass
alsa_mixer-test_get_value_0_39: pass
alsa_mixer-test_get_value_0_4: pass
alsa_mixer-test_get_value_0_40: pass
alsa_mixer-test_get_value_0_41: pass
alsa_mixer-test_get_value_0_42: pass
alsa_mixer-test_get_value_0_43: pass
alsa_mixer-test_get_value_0_44: pass
alsa_mixer-test_get_value_0_45: pass
alsa_mixer-test_get_value_0_46: pass
alsa_mixer-test_get_value_0_47: pass
alsa_mixer-test_get_value_0_48: pass
alsa_mixer-test_get_value_0_49: pass
alsa_mixer-test_get_value_0_5: pass
alsa_mixer-test_get_value_0_50: pass
alsa_mixer-test_get_value_0_51: pass
alsa_mixer-test_get_value_0_52: pass
alsa_mixer-test_get_value_0_53: pass
alsa_mixer-test_get_value_0_54: pass
alsa_mixer-test_get_value_0_55: pass
alsa_mixer-test_get_value_0_56: pass
alsa_mixer-test_get_value_0_57: pass
alsa_mixer-test_get_value_0_58: pass
alsa_mixer-test_get_value_0_59: pass
alsa_mixer-test_get_value_0_6: pass
alsa_mixer-test_get_value_0_60: pass
alsa_mixer-test_get_value_0_61: pass
alsa_mixer-test_get_value_0_62: pass
alsa_mixer-test_get_value_0_63: pass
alsa_mixer-test_get_value_0_64: pass
alsa_mixer-test_get_value_0_65: pass
alsa_mixer-test_get_value_0_66: pass
alsa_mixer-test_get_value_0_67: pass
alsa_mixer-test_get_value_0_68: pass
alsa_mixer-test_get_value_0_69: pass
alsa_mixer-test_get_value_0_7: pass
alsa_mixer-test_get_value_0_70: pass
alsa_mixer-test_get_value_0_71: pass
alsa_mixer-test_get_value_0_72: pass
alsa_mixer-test_get_value_0_73: pass
alsa_mixer-test_get_value_0_74: pass
alsa_mixer-test_get_value_0_75: pass
alsa_mixer-test_get_value_0_76: pass
alsa_mixer-test_get_value_0_77: fail
alsa_mixer-test_get_value_0_78: fail
alsa_mixer-test_get_value_0_79: fail
alsa_mixer-test_get_value_0_8: pass
alsa_mixer-test_get_value_0_80: pass
alsa_mixer-test_get_value_0_81: pass
alsa_mixer-test_get_value_0_82: pass
alsa_mixer-test_get_value_0_83: pass
alsa_mixer-test_get_value_0_84: pass
alsa_mixer-test_get_value_0_85: pass
alsa_mixer-test_get_value_0_86: pass
alsa_mixer-test_get_value_0_87: pass
alsa_mixer-test_get_value_0_88: pass
alsa_mixer-test_get_value_0_89: pass
alsa_mixer-test_get_value_0_9: pass
alsa_mixer-test_get_value_0_90: pass
alsa_mixer-test_get_value_0_91: pass
alsa_mixer-test_get_value_0_92: pass
alsa_mixer-test_get_value_0_93: pass
alsa_mixer-test_name_0_0: pass
alsa_mixer-test_name_0_1: pass
alsa_mixer-test_name_0_10: fail
alsa_mixer-test_name_0_11: fail
alsa_mixer-test_name_0_12: fail
alsa_mixer-test_name_0_13: fail
alsa_mixer-test_name_0_14: fail
alsa_mixer-test_name_0_15: fail
alsa_mixer-test_name_0_16: fail
alsa_mixer-test_name_0_17: fail
alsa_mixer-test_name_0_18: fail
alsa_mixer-test_name_0_19: fail
alsa_mixer-test_name_0_2: pass
alsa_mixer-test_name_0_20: fail
alsa_mixer-test_name_0_21: fail
alsa_mixer-test_name_0_22: pass
alsa_mixer-test_name_0_23: pass
alsa_mixer-test_name_0_24: pass
alsa_mixer-test_name_0_25: pass
alsa_mixer-test_name_0_26: pass
alsa_mixer-test_name_0_27: pass
alsa_mixer-test_name_0_28: pass
alsa_mixer-test_name_0_29: pass
alsa_mixer-test_name_0_3: pass
alsa_mixer-test_name_0_30: fail
alsa_mixer-test_name_0_31: fail
alsa_mixer-test_name_0_32: fail
alsa_mixer-test_name_0_33: fail
alsa_mixer-test_name_0_34: fail
alsa_mixer-test_name_0_35: fail
alsa_mixer-test_name_0_36: fail
alsa_mixer-test_name_0_37: fail
alsa_mixer-test_name_0_38: fail
alsa_mixer-test_name_0_39: fail
alsa_mixer-test_name_0_4: pass
alsa_mixer-test_name_0_40: fail
alsa_mixer-test_name_0_41: fail
alsa_mixer-test_name_0_42: fail
alsa_mixer-test_name_0_43: fail
alsa_mixer-test_name_0_44: fail
alsa_mixer-test_name_0_45: fail
alsa_mixer-test_name_0_46: fail
alsa_mixer-test_name_0_47: fail
alsa_mixer-test_name_0_48: fail
alsa_mixer-test_name_0_49: fail
alsa_mixer-test_name_0_5: pass
alsa_mixer-test_name_0_50: fail
alsa_mixer-test_name_0_51: fail
alsa_mixer-test_name_0_52: fail
alsa_mixer-test_name_0_53: fail
alsa_mixer-test_name_0_54: fail
alsa_mixer-test_name_0_55: fail
alsa_mixer-test_name_0_56: fail
alsa_mixer-test_name_0_57: fail
alsa_mixer-test_name_0_58: fail
alsa_mixer-test_name_0_59: fail
alsa_mixer-test_name_0_6: fail
alsa_mixer-test_name_0_60: fail
alsa_mixer-test_name_0_61: fail
alsa_mixer-test_name_0_62: fail
alsa_mixer-test_name_0_63: fail
alsa_mixer-test_name_0_64: fail
alsa_mixer-test_name_0_65: fail
alsa_mixer-test_name_0_66: fail
alsa_mixer-test_name_0_67: fail
alsa_mixer-test_name_0_68: fail
alsa_mixer-test_name_0_69: fail
alsa_mixer-test_name_0_7: fail
alsa_mixer-test_name_0_70: fail
alsa_mixer-test_name_0_71: fail
alsa_mixer-test_name_0_72: fail
alsa_mixer-test_name_0_73: fail
alsa_mixer-test_name_0_74: fail
alsa_mixer-test_name_0_75: fail
alsa_mixer-test_name_0_76: fail
alsa_mixer-test_name_0_77: pass
alsa_mixer-test_name_0_78: pass
alsa_mixer-test_name_0_79: pass
alsa_mixer-test_name_0_8: fail
alsa_mixer-test_name_0_80: pass
alsa_mixer-test_name_0_81: pass
alsa_mixer-test_name_0_82: pass
alsa_mixer-test_name_0_83: pass
alsa_mixer-test_name_0_84: pass
alsa_mixer-test_name_0_85: pass
alsa_mixer-test_name_0_86: pass
alsa_mixer-test_name_0_87: pass
alsa_mixer-test_name_0_88: pass
alsa_mixer-test_name_0_89: pass
alsa_mixer-test_name_0_9: fail
alsa_mixer-test_name_0_90: pass
alsa_mixer-test_name_0_91: pass
alsa_mixer-test_name_0_92: pass
alsa_mixer-test_name_0_93: pass
alsa_mixer-test_write_default_0_0: pass
alsa_mixer-test_write_default_0_1: pass
alsa_mixer-test_write_default_0_10: pass
alsa_mixer-test_write_default_0_11: pass
alsa_mixer-test_write_default_0_12: pass
alsa_mixer-test_write_default_0_13: pass
alsa_mixer-test_write_default_0_14: pass
alsa_mixer-test_write_default_0_15: pass
alsa_mixer-test_write_default_0_16: pass
alsa_mixer-test_write_default_0_17: pass
alsa_mixer-test_write_default_0_18: pass
alsa_mixer-test_write_default_0_19: pass
alsa_mixer-test_write_default_0_2: pass
alsa_mixer-test_write_default_0_20: pass
alsa_mixer-test_write_default_0_21: pass
alsa_mixer-test_write_default_0_22: pass
alsa_mixer-test_write_default_0_23: pass
alsa_mixer-test_write_default_0_24: pass
alsa_mixer-test_write_default_0_25: pass
alsa_mixer-test_write_default_0_26: pass
alsa_mixer-test_write_default_0_27: pass
alsa_mixer-test_write_default_0_28: pass
alsa_mixer-test_write_default_0_29: pass
alsa_mixer-test_write_default_0_3: pass
alsa_mixer-test_write_default_0_30: pass
alsa_mixer-test_write_default_0_31: pass
alsa_mixer-test_write_default_0_32: pass
alsa_mixer-test_write_default_0_33: pass
alsa_mixer-test_write_default_0_34: pass
alsa_mixer-test_write_default_0_35: pass
alsa_mixer-test_write_default_0_36: pass
alsa_mixer-test_write_default_0_37: pass
alsa_mixer-test_write_default_0_38: pass
alsa_mixer-test_write_default_0_39: pass
alsa_mixer-test_write_default_0_4: pass
alsa_mixer-test_write_default_0_40: pass
alsa_mixer-test_write_default_0_41: pass
alsa_mixer-test_write_default_0_42: pass
alsa_mixer-test_write_default_0_43: pass
alsa_mixer-test_write_default_0_44: pass
alsa_mixer-test_write_default_0_45: pass
alsa_mixer-test_write_default_0_46: pass
alsa_mixer-test_write_default_0_47: pass
alsa_mixer-test_write_default_0_48: pass
alsa_mixer-test_write_default_0_49: pass
alsa_mixer-test_write_default_0_5: pass
alsa_mixer-test_write_default_0_50: pass
alsa_mixer-test_write_default_0_51: pass
alsa_mixer-test_write_default_0_52: pass
alsa_mixer-test_write_default_0_53: pass
alsa_mixer-test_write_default_0_54: pass
alsa_mixer-test_write_default_0_55: pass
alsa_mixer-test_write_default_0_56: pass
alsa_mixer-test_write_default_0_57: pass
alsa_mixer-test_write_default_0_58: pass
alsa_mixer-test_write_default_0_59: pass
alsa_mixer-test_write_default_0_6: pass
alsa_mixer-test_write_default_0_60: pass
alsa_mixer-test_write_default_0_61: pass
alsa_mixer-test_write_default_0_62: pass
alsa_mixer-test_write_default_0_63: pass
alsa_mixer-test_write_default_0_64: pass
alsa_mixer-test_write_default_0_65: pass
alsa_mixer-test_write_default_0_66: pass
alsa_mixer-test_write_default_0_67: pass
alsa_mixer-test_write_default_0_68: pass
alsa_mixer-test_write_default_0_69: pass
alsa_mixer-test_write_default_0_7: pass
alsa_mixer-test_write_default_0_70: pass
alsa_mixer-test_write_default_0_71: pass
alsa_mixer-test_write_default_0_72: pass
alsa_mixer-test_write_default_0_73: pass
alsa_mixer-test_write_default_0_74: pass
alsa_mixer-test_write_default_0_75: pass
alsa_mixer-test_write_default_0_76: pass
alsa_mixer-test_write_default_0_77: fail
alsa_mixer-test_write_default_0_78: fail
alsa_mixer-test_write_default_0_79: fail
alsa_mixer-test_write_default_0_8: pass
alsa_mixer-test_write_default_0_80: pass
alsa_mixer-test_write_default_0_81: pass
alsa_mixer-test_write_default_0_82: skip
alsa_mixer-test_write_default_0_83: pass
alsa_mixer-test_write_default_0_84: pass
alsa_mixer-test_write_default_0_85: pass
alsa_mixer-test_write_default_0_86: pass
alsa_mixer-test_write_default_0_87: pass
alsa_mixer-test_write_default_0_88: pass
alsa_mixer-test_write_default_0_89: pass
alsa_mixer-test_write_default_0_9: pass
alsa_mixer-test_write_default_0_90: pass
alsa_mixer-test_write_default_0_91: pass
alsa_mixer-test_write_default_0_92: pass
alsa_mixer-test_write_default_0_93: pass
alsa_mixer-test_write_invalid_0_0: pass
alsa_mixer-test_write_invalid_0_1: pass
alsa_mixer-test_write_invalid_0_10: pass
alsa_mixer-test_write_invalid_0_11: pass
alsa_mixer-test_write_invalid_0_12: pass
alsa_mixer-test_write_invalid_0_13: pass
alsa_mixer-test_write_invalid_0_14: pass
alsa_mixer-test_write_invalid_0_15: pass
alsa_mixer-test_write_invalid_0_16: pass
alsa_mixer-test_write_invalid_0_17: pass
alsa_mixer-test_write_invalid_0_18: pass
alsa_mixer-test_write_invalid_0_19: pass
alsa_mixer-test_write_invalid_0_2: pass
alsa_mixer-test_write_invalid_0_20: pass
alsa_mixer-test_write_invalid_0_21: pass
alsa_mixer-test_write_invalid_0_22: pass
alsa_mixer-test_write_invalid_0_23: pass
alsa_mixer-test_write_invalid_0_24: pass
alsa_mixer-test_write_invalid_0_25: pass
alsa_mixer-test_write_invalid_0_26: pass
alsa_mixer-test_write_invalid_0_27: pass
alsa_mixer-test_write_invalid_0_28: pass
alsa_mixer-test_write_invalid_0_29: pass
alsa_mixer-test_write_invalid_0_3: pass
alsa_mixer-test_write_invalid_0_30: pass
alsa_mixer-test_write_invalid_0_31: pass
alsa_mixer-test_write_invalid_0_32: pass
alsa_mixer-test_write_invalid_0_33: pass
alsa_mixer-test_write_invalid_0_34: pass
alsa_mixer-test_write_invalid_0_35: pass
alsa_mixer-test_write_invalid_0_36: pass
alsa_mixer-test_write_invalid_0_37: pass
alsa_mixer-test_write_invalid_0_38: pass
alsa_mixer-test_write_invalid_0_39: pass
alsa_mixer-test_write_invalid_0_4: pass
alsa_mixer-test_write_invalid_0_40: pass
alsa_mixer-test_write_invalid_0_41: pass
alsa_mixer-test_write_invalid_0_42: pass
alsa_mixer-test_write_invalid_0_43: pass
alsa_mixer-test_write_invalid_0_44: pass
alsa_mixer-test_write_invalid_0_45: pass
alsa_mixer-test_write_invalid_0_46: pass
alsa_mixer-test_write_invalid_0_47: pass
alsa_mixer-test_write_invalid_0_48: pass
alsa_mixer-test_write_invalid_0_49: pass
alsa_mixer-test_write_invalid_0_5: pass
alsa_mixer-test_write_invalid_0_50: pass
alsa_mixer-test_write_invalid_0_51: pass
alsa_mixer-test_write_invalid_0_52: pass
alsa_mixer-test_write_invalid_0_53: pass
alsa_mixer-test_write_invalid_0_54: pass
alsa_mixer-test_write_invalid_0_55: pass
alsa_mixer-test_write_invalid_0_56: pass
alsa_mixer-test_write_invalid_0_57: pass
alsa_mixer-test_write_invalid_0_58: pass
alsa_mixer-test_write_invalid_0_59: pass
alsa_mixer-test_write_invalid_0_6: pass
alsa_mixer-test_write_invalid_0_60: pass
alsa_mixer-test_write_invalid_0_61: pass
alsa_mixer-test_write_invalid_0_62: pass
alsa_mixer-test_write_invalid_0_63: pass
alsa_mixer-test_write_invalid_0_64: pass
alsa_mixer-test_write_invalid_0_65: pass
alsa_mixer-test_write_invalid_0_66: pass
alsa_mixer-test_write_invalid_0_67: pass
alsa_mixer-test_write_invalid_0_68: pass
alsa_mixer-test_write_invalid_0_69: pass
alsa_mixer-test_write_invalid_0_7: pass
alsa_mixer-test_write_invalid_0_70: pass
alsa_mixer-test_write_invalid_0_71: pass
alsa_mixer-test_write_invalid_0_72: pass
alsa_mixer-test_write_invalid_0_73: pass
alsa_mixer-test_write_invalid_0_74: pass
alsa_mixer-test_write_invalid_0_75: pass
alsa_mixer-test_write_invalid_0_76: pass
alsa_mixer-test_write_invalid_0_77: fail
alsa_mixer-test_write_invalid_0_78: fail
alsa_mixer-test_write_invalid_0_79: fail
alsa_mixer-test_write_invalid_0_8: pass
alsa_mixer-test_write_invalid_0_80: pass
alsa_mixer-test_write_invalid_0_81: fail
alsa_mixer-test_write_invalid_0_82: skip
alsa_mixer-test_write_invalid_0_83: pass
alsa_mixer-test_write_invalid_0_84: pass
alsa_mixer-test_write_invalid_0_85: pass
alsa_mixer-test_write_invalid_0_86: pass
alsa_mixer-test_write_invalid_0_87: pass
alsa_mixer-test_write_invalid_0_88: pass
alsa_mixer-test_write_invalid_0_89: pass
alsa_mixer-test_write_invalid_0_9: pass
alsa_mixer-test_write_invalid_0_90: pass
alsa_mixer-test_write_invalid_0_91: pass
alsa_mixer-test_write_invalid_0_92: pass
alsa_mixer-test_write_invalid_0_93: pass
alsa_mixer-test_write_valid_0_0: pass
alsa_mixer-test_write_valid_0_1: pass
alsa_mixer-test_write_valid_0_10: pass
alsa_mixer-test_write_valid_0_11: pass
alsa_mixer-test_write_valid_0_12: pass
alsa_mixer-test_write_valid_0_13: pass
alsa_mixer-test_write_valid_0_14: pass
alsa_mixer-test_write_valid_0_15: pass
alsa_mixer-test_write_valid_0_16: pass
alsa_mixer-test_write_valid_0_17: pass
alsa_mixer-test_write_valid_0_18: pass
alsa_mixer-test_write_valid_0_19: pass
alsa_mixer-test_write_valid_0_2: pass
alsa_mixer-test_write_valid_0_20: pass
alsa_mixer-test_write_valid_0_21: pass
alsa_mixer-test_write_valid_0_22: pass
alsa_mixer-test_write_valid_0_23: pass
alsa_mixer-test_write_valid_0_24: pass
alsa_mixer-test_write_valid_0_25: pass
alsa_mixer-test_write_valid_0_26: pass
alsa_mixer-test_write_valid_0_27: pass
alsa_mixer-test_write_valid_0_28: pass
alsa_mixer-test_write_valid_0_29: pass
alsa_mixer-test_write_valid_0_3: pass
alsa_mixer-test_write_valid_0_30: pass
alsa_mixer-test_write_valid_0_31: pass
alsa_mixer-test_write_valid_0_32: pass
alsa_mixer-test_write_valid_0_33: pass
alsa_mixer-test_write_valid_0_34: pass
alsa_mixer-test_write_valid_0_35: pass
alsa_mixer-test_write_valid_0_36: pass
alsa_mixer-test_write_valid_0_37: pass
alsa_mixer-test_write_valid_0_38: pass
alsa_mixer-test_write_valid_0_39: pass
alsa_mixer-test_write_valid_0_4: pass
alsa_mixer-test_write_valid_0_40: pass
alsa_mixer-test_write_valid_0_41: pass
alsa_mixer-test_write_valid_0_42: pass
alsa_mixer-test_write_valid_0_43: pass
alsa_mixer-test_write_valid_0_44: pass
alsa_mixer-test_write_valid_0_45: pass
alsa_mixer-test_write_valid_0_46: pass
alsa_mixer-test_write_valid_0_47: pass
alsa_mixer-test_write_valid_0_48: pass
alsa_mixer-test_write_valid_0_49: pass
alsa_mixer-test_write_valid_0_5: pass
alsa_mixer-test_write_valid_0_50: pass
alsa_mixer-test_write_valid_0_51: pass
alsa_mixer-test_write_valid_0_52: pass
alsa_mixer-test_write_valid_0_53: pass
alsa_mixer-test_write_valid_0_54: pass
alsa_mixer-test_write_valid_0_55: pass
alsa_mixer-test_write_valid_0_56: pass
alsa_mixer-test_write_valid_0_57: pass
alsa_mixer-test_write_valid_0_58: pass
alsa_mixer-test_write_valid_0_59: pass
alsa_mixer-test_write_valid_0_6: pass
alsa_mixer-test_write_valid_0_60: pass
alsa_mixer-test_write_valid_0_61: pass
alsa_mixer-test_write_valid_0_62: pass
alsa_mixer-test_write_valid_0_63: pass
alsa_mixer-test_write_valid_0_64: pass
alsa_mixer-test_write_valid_0_65: pass
alsa_mixer-test_write_valid_0_66: pass
alsa_mixer-test_write_valid_0_67: pass
alsa_mixer-test_write_valid_0_68: pass
alsa_mixer-test_write_valid_0_69: pass
alsa_mixer-test_write_valid_0_7: pass
alsa_mixer-test_write_valid_0_70: pass
alsa_mixer-test_write_valid_0_71: pass
alsa_mixer-test_write_valid_0_72: pass
alsa_mixer-test_write_valid_0_73: pass
alsa_mixer-test_write_valid_0_74: pass
alsa_mixer-test_write_valid_0_75: pass
alsa_mixer-test_write_valid_0_76: pass
alsa_mixer-test_write_valid_0_77: fail
alsa_mixer-test_write_valid_0_78: fail
alsa_mixer-test_write_valid_0_79: fail
alsa_mixer-test_write_valid_0_8: pass
alsa_mixer-test_write_valid_0_80: pass
alsa_mixer-test_write_valid_0_81: pass
alsa_mixer-test_write_valid_0_82: skip
alsa_mixer-test_write_valid_0_83: pass
alsa_mixer-test_write_valid_0_84: pass
alsa_mixer-test_write_valid_0_85: fail
alsa_mixer-test_write_valid_0_86: fail
alsa_mixer-test_write_valid_0_87: pass
alsa_mixer-test_write_valid_0_88: fail
alsa_mixer-test_write_valid_0_89: pass
alsa_mixer-test_write_valid_0_9: pass
alsa_mixer-test_write_valid_0_90: pass
alsa_mixer-test_write_valid_0_91: pass
alsa_mixer-test_write_valid_0_92: pass
alsa_mixer-test_write_valid_0_93: pass
shardfile-alsa: pass
9980 00:44:42.986507 end: 3.1 lava-test-shell (duration 00:00:45) [common]
9981 00:44:42.986593 end: 3 lava-test-retry (duration 00:00:45) [common]
9982 00:44:42.986677 start: 4 finalize (timeout 00:07:25) [common]
9983 00:44:42.986765 start: 4.1 power-off (timeout 00:00:30) [common]
9984 00:44:42.986918 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8183-kukui-jacuzzi-juniper-sku16-cbg-5', '--port=1', '--command=off']
9985 00:44:44.520221 >> Command sent successfully.
9986 00:44:44.523649 Returned 0 in 1 seconds
9987 00:44:44.624040 end: 4.1 power-off (duration 00:00:02) [common]
9989 00:44:44.624345 start: 4.2 read-feedback (timeout 00:07:23) [common]
9990 00:44:44.624575 Listened to connection for namespace 'common' for up to 1s
9991 00:44:45.624779 Finalising connection for namespace 'common'
9992 00:44:45.624943 Disconnecting from shell: Finalise
9993 00:44:45.625014 / #
9994 00:44:45.725316 end: 4.2 read-feedback (duration 00:00:01) [common]
9995 00:44:45.725478 end: 4 finalize (duration 00:00:03) [common]
9996 00:44:45.725594 Cleaning after the job
9997 00:44:45.725714 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14368368/tftp-deploy-pdqfsrpp/ramdisk
9998 00:44:45.728199 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14368368/tftp-deploy-pdqfsrpp/kernel
9999 00:44:45.739169 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14368368/tftp-deploy-pdqfsrpp/dtb
10000 00:44:45.739421 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14368368/tftp-deploy-pdqfsrpp/nfsrootfs
10001 00:44:45.805814 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14368368/tftp-deploy-pdqfsrpp/modules
10002 00:44:45.811847 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14368368
10003 00:44:46.378183 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14368368
10004 00:44:46.378385 Job finished correctly